Added demo for the MB9A314 - the IAR project is working, the Keil one is not set...

git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@1575 1d2547de-c912-0410-9cb9-b8ca96c0e9e2

diff --git a/Demo/CORTEX_MB9A310_IAR_Keil/FreeRTOSConfig.h b/Demo/CORTEX_MB9A310_IAR_Keil/FreeRTOSConfig.h
new file mode 100644 (file)
index 0000000..e058a7b
--- /dev/null
+++ b/Demo/CORTEX_MB9A310_IAR_Keil/FreeRTOSConfig.h
@@ -0,0 +1,167 @@
+/*\r
+    FreeRTOS V7.0.1 - Copyright (C) 2011 Real Time Engineers Ltd.\r
+\r
+\r
+       FreeRTOS supports many tools and architectures. V7.0.0 is sponsored by:\r
+       Atollic AB - Atollic provides professional embedded systems development\r
+       tools for C/C++ development, code analysis and test automation.\r
+       See http://www.atollic.com\r
+\r
+\r
+    ***************************************************************************\r
+     *                                                                       *\r
+     *    FreeRTOS tutorial books are available in pdf and paperback.        *\r
+     *    Complete, revised, and edited pdf reference manuals are also       *\r
+     *    available.                                                         *\r
+     *                                                                       *\r
+     *    Purchasing FreeRTOS documentation will not only help you, by       *\r
+     *    ensuring you get running as quickly as possible and with an        *\r
+     *    in-depth knowledge of how to use FreeRTOS, it will also help       *\r
+     *    the FreeRTOS project to continue with its mission of providing     *\r
+     *    professional grade, cross platform, de facto standard solutions    *\r
+     *    for microcontrollers - completely free of charge!                  *\r
+     *                                                                       *\r
+     *    >>> See http://www.FreeRTOS.org/Documentation for details. <<<     *\r
+     *                                                                       *\r
+     *    Thank you for using FreeRTOS, and thank you for your support!      *\r
+     *                                                                       *\r
+    ***************************************************************************\r
+\r
+\r
+    This file is part of the FreeRTOS distribution.\r
+\r
+    FreeRTOS is free software; you can redistribute it and/or modify it under\r
+    the terms of the GNU General Public License (version 2) as published by the\r
+    Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+    >>>NOTE<<< The modification to the GPL is included to allow you to\r
+    distribute a combined work that includes FreeRTOS without being obliged to\r
+    provide the source code for proprietary components outside of the FreeRTOS\r
+    kernel.  FreeRTOS is distributed in the hope that it will be useful, but\r
+    WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\r
+    more details. You should have received a copy of the GNU General Public\r
+    License and the FreeRTOS license exception along with FreeRTOS; if not it\r
+    can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
+    by writing to Richard Barry, contact details for whom are available on the\r
+    FreeRTOS WEB site.\r
+\r
+    1 tab == 4 spaces!\r
+\r
+    http://www.FreeRTOS.org - Documentation, latest information, license and\r
+    contact details.\r
+\r
+    http://www.SafeRTOS.com - A version that is certified for use in safety\r
+    critical systems.\r
+\r
+    http://www.OpenRTOS.com - Commercial support, development, porting,\r
+    licensing and training services.\r
+*/\r
+\r
+\r
+#ifndef FREERTOS_CONFIG_H\r
+#define FREERTOS_CONFIG_H\r
+\r
+/*-----------------------------------------------------------\r
+ * Application specific definitions.\r
+ *\r
+ * These definitions should be adjusted for your particular hardware and\r
+ * application requirements.\r
+ *\r
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE\r
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.\r
+ *\r
+ * See http://www.freertos.org/a00110.html.\r
+ *----------------------------------------------------------*/\r
+\r
+/* Use a guard to ensure the following few definitions are'nt included in\r
+assembly files that include this header file. */\r
+#ifndef __IASMARM__\r
+       #include <stdint.h>\r
+       extern uint32_t SystemCoreClock;\r
+#endif\r
+\r
+#define configUSE_PREEMPTION                   1\r
+#define configUSE_IDLE_HOOK                            1\r
+#define configUSE_TICK_HOOK                            1\r
+#define configCPU_CLOCK_HZ                             ( SystemCoreClock )\r
+#define configTICK_RATE_HZ                             ( ( portTickType ) 1000 )\r
+#define configMAX_PRIORITIES                   ( ( unsigned portBASE_TYPE ) 5 )\r
+#define configMINIMAL_STACK_SIZE               ( ( unsigned short ) 90 )\r
+#define configTOTAL_HEAP_SIZE                  ( ( size_t ) ( 30 * 1024 ) )\r
+#define configMAX_TASK_NAME_LEN                        ( 10 )\r
+#define configUSE_TRACE_FACILITY               1\r
+#define configUSE_16_BIT_TICKS                 0\r
+#define configIDLE_SHOULD_YIELD                        1\r
+#define configUSE_MUTEXES                              1\r
+#define configQUEUE_REGISTRY_SIZE              0\r
+#define configGENERATE_RUN_TIME_STATS  0\r
+#define configCHECK_FOR_STACK_OVERFLOW 2\r
+#define configUSE_RECURSIVE_MUTEXES            1\r
+#define configUSE_MALLOC_FAILED_HOOK   1\r
+#define configUSE_APPLICATION_TASK_TAG 0\r
+#define configUSE_COUNTING_SEMAPHORES  1\r
+\r
+/* Co-routine definitions. */\r
+#define configUSE_CO_ROUTINES          0\r
+#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )\r
+\r
+/* Software timer definitions. */\r
+#define configUSE_TIMERS                               1\r
+#define configTIMER_TASK_PRIORITY              ( 2 )\r
+#define configTIMER_QUEUE_LENGTH               10\r
+#define configTIMER_TASK_STACK_DEPTH   ( configMINIMAL_STACK_SIZE * 2 )\r
+\r
+/* Set the following definitions to 1 to include the API function, or zero\r
+to exclude the API function. */\r
+#define INCLUDE_vTaskPrioritySet               1\r
+#define INCLUDE_uxTaskPriorityGet              1\r
+#define INCLUDE_vTaskDelete                            1\r
+#define INCLUDE_vTaskCleanUpResources  1\r
+#define INCLUDE_vTaskSuspend                   1\r
+#define INCLUDE_vTaskDelayUntil                        1\r
+#define INCLUDE_vTaskDelay                             1\r
+\r
+/* Use the system definition, if there is one */\r
+#ifdef __NVIC_PRIO_BITS\r
+       #define configPRIO_BITS                 __NVIC_PRIO_BITS\r
+#else\r
+       #define configPRIO_BITS                 4        /* 15 priority levels */\r
+#endif\r
+\r
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY                        0xf\r
+#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY   5\r
+\r
+/* The lowest priority. */\r
+#define configKERNEL_INTERRUPT_PRIORITY        ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )\r
+/* Priority 5, or 160 as only the top three bits are implemented. */\r
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY   ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )\r
+       \r
+#define configASSERT( x ) if( ( x ) == 0 ) { taskDISABLE_INTERRUPTS(); for( ;; ); }    \r
+       \r
+#define vPortSVCHandler SVC_Handler\r
+#define xPortPendSVHandler PendSV_Handler\r
+#define vPortSVCHandler SVC_Handler\r
+#define xPortSysTickHandler SysTick_Handler\r
+\r
+/* MAC address configuration. */\r
+#define configMAC_ADDR0        0x00\r
+#define configMAC_ADDR1        0x12\r
+#define configMAC_ADDR2        0x13\r
+#define configMAC_ADDR3        0x10\r
+#define configMAC_ADDR4        0x15\r
+#define configMAC_ADDR5        0x11\r
+\r
+/* IP address configuration. */\r
+#define configIP_ADDR0         192\r
+#define configIP_ADDR1         168\r
+#define configIP_ADDR2         0\r
+#define configIP_ADDR3         200\r
+\r
+/* Netmask configuration. */\r
+#define configNET_MASK0                255\r
+#define configNET_MASK1                255\r
+#define configNET_MASK2                255\r
+#define configNET_MASK3                0\r
+\r
+#endif /* FREERTOS_CONFIG_H */\r
+\r

diff --git a/Demo/CORTEX_MB9A310_IAR_Keil/Fujitu_source/core_cm3.c b/Demo/CORTEX_MB9A310_IAR_Keil/Fujitu_source/core_cm3.c
new file mode 100644 (file)
index 0000000..f1bfb2b
--- /dev/null
+++ b/Demo/CORTEX_MB9A310_IAR_Keil/Fujitu_source/core_cm3.c
@@ -0,0 +1,359 @@
+/**************************************************************************//**\r
+ * @file     core_cm3.c\r
+ * @brief    CMSIS Cortex-M3 Core Peripheral Access Layer Source File\r
+ * @version  V1.40\r
+ * @date     18. February 2010\r
+ *\r
+ * @note\r
+ * Copyright (C) 2009-2010 ARM Limited. All rights reserved.\r
+ *\r
+ * @par\r
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M \r
+ * processor based microcontrollers.  This file can be freely distributed \r
+ * within development tools that are supporting such ARM based processors. \r
+ *\r
+ * @par\r
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+ *\r
+ ******************************************************************************/\r
+\r
+#include <stdint.h>\r
+\r
+/* define compiler specific symbols */\r
+#if defined ( __CC_ARM   )\r
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */\r
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */\r
+\r
+#elif defined ( __ICCARM__ )\r
+  #define __ASM           __asm                                       /*!< asm keyword for IAR Compiler          */\r
+  #define __INLINE        inline                                      /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */\r
+\r
+#elif defined   (  __GNUC__  )\r
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */\r
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */\r
+\r
+#elif defined   (  __TASKING__  )\r
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */\r
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */\r
+\r
+#endif\r
+\r
+\r
+/* ##########################  Core Instruction Access  ######################### */\r
+\r
+#if defined ( __CC_ARM   ) /*------------------ RealView Compiler ----------------*/\r
+\r
+/**\r
+ * @brief  Reverse byte order (16 bit)\r
+ *\r
+ * @param  value  value to reverse\r
+ * @return        reversed value\r
+ *\r
+ * Reverse byte order in unsigned short value\r
+ */\r
+#if (__ARMCC_VERSION < 400677)\r
+__ASM uint32_t __REV16(uint16_t value)\r
+{\r
+  rev16 r0, r0\r
+  bx lr\r
+}\r
+#endif /* __ARMCC_VERSION  */ \r
+\r
+/**\r
+ * @brief  Reverse byte order in signed short value with sign extension to integer\r
+ *\r
+ * @param  value  value to reverse\r
+ * @return        reversed value\r
+ *\r
+ * Reverse byte order in signed short value with sign extension to integer\r
+ */\r
+#if (__ARMCC_VERSION < 400677)\r
+__ASM int32_t __REVSH(int16_t value)\r
+{\r
+  revsh r0, r0\r
+  bx lr\r
+}\r
+#endif /* __ARMCC_VERSION  */ \r
+\r
+ /**\r
+ * @brief  Remove the exclusive lock created by ldrex\r
+ *\r
+ * Removes the exclusive lock which is created by ldrex.\r
+ */\r
+#if (__ARMCC_VERSION < 400000)\r
+__ASM void __CLREX(void)\r
+{\r
+  clrex\r
+}\r
+#endif /* __ARMCC_VERSION  */ \r
+\r
+\r
+#elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/\r
+/* obsolete */\r
+#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/\r
+/* obsolete */\r
+#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/\r
+/* obsolete */\r
+#endif\r
+\r
+\r
+/* ###########################  Core Function Access  ########################### */\r
+\r
+#if defined ( __CC_ARM   ) /*------------------ RealView Compiler ----------------*/\r
+\r
+/**\r
+ * @brief  Return the Control Register value\r
+* \r
+*  @return Control value\r
+ *\r
+ * Return the content of the control register\r
+ */\r
+#if       (__ARMCC_VERSION <  400000)\r
+__ASM uint32_t __get_CONTROL(void)\r
+{\r
+  mrs r0, control\r
+  bx lr\r
+}\r
+#endif /*  __ARMCC_VERSION  */ \r
+\r
+/**\r
+ * @brief  Set the Control Register value\r
+ *\r
+ * @param  control  Control value\r
+ *\r
+ * Set the control register\r
+ */\r
+#if       (__ARMCC_VERSION <  400000)\r
+__ASM void __set_CONTROL(uint32_t control)\r
+{\r
+  msr control, r0\r
+  bx lr\r
+}\r
+#endif /*  __ARMCC_VERSION  */ \r
+\r
+/**\r
+ * @brief  Get IPSR Register value\r
+ *\r
+ * @return uint32_t IPSR value\r
+ *\r
+ * return the content of the IPSR register\r
+ */\r
+#if       (__ARMCC_VERSION <  400000)\r
+__ASM uint32_t __get_IPSR(void)\r
+{\r
+  mrs r0, ipsr\r
+  bx lr\r
+}\r
+#endif /*  __ARMCC_VERSION  */ \r
+\r
+/**\r
+ * @brief  Get APSR Register value\r
+ *\r
+ * @return uint32_t APSR value\r
+ *\r
+ * return the content of the APSR register\r
+ */\r
+#if       (__ARMCC_VERSION <  400000)\r
+__ASM uint32_t __get_APSR(void)\r
+{\r
+  mrs r0, apsr\r
+  bx lr\r
+}\r
+#endif /*  __ARMCC_VERSION  */ \r
+\r
+/**\r
+ * @brief  Get xPSR Register value\r
+ *\r
+ * @return uint32_t xPSR value\r
+ *\r
+ * return the content of the xPSR register\r
+ */\r
+#if       (__ARMCC_VERSION <  400000)\r
+__ASM uint32_t __get_xPSR(void)\r
+{\r
+  mrs r0, xpsr\r
+  bx lr\r
+}\r
+#endif /*  __ARMCC_VERSION  */ \r
+\r
+/**\r
+ * @brief  Return the Process Stack Pointer\r
+ *\r
+ * @return ProcessStackPointer\r
+ *\r
+ * Return the actual process stack pointer\r
+ */\r
+#if       (__ARMCC_VERSION <  400000)\r
+__ASM uint32_t __get_PSP(void)\r
+{\r
+  mrs r0, psp\r
+  bx lr\r
+}\r
+#endif /*  __ARMCC_VERSION  */ \r
+ \r
+/**\r
+ * @brief  Set the Process Stack Pointer\r
+ *\r
+ * @param  topOfProcStack  Process Stack Pointer\r
+ *\r
+ * Assign the value ProcessStackPointer to the MSP \r
+ * (process stack pointer) Cortex processor register\r
+ */\r
+#if       (__ARMCC_VERSION <  400000)\r
+__ASM void __set_PSP(uint32_t topOfProcStack)\r
+{\r
+  msr psp, r0\r
+  bx lr\r
+}\r
+#endif /*  __ARMCC_VERSION  */ \r
+\r
+/**\r
+ * @brief  Return the Main Stack Pointer\r
+ *\r
+ * @return Main Stack Pointer\r
+ *\r
+ * Return the current value of the MSP (main stack pointer)\r
+ * Cortex processor register\r
+ */\r
+#if       (__ARMCC_VERSION <  400000)\r
+__ASM uint32_t __get_MSP(void)\r
+{\r
+  mrs r0, msp\r
+  bx lr\r
+}\r
+#endif /*  __ARMCC_VERSION  */ \r
+ \r
+/**\r
+ * @brief  Set the Main Stack Pointer\r
+ *\r
+ * @param  topOfMainStack  Main Stack Pointer\r
+ *\r
+ * Assign the value mainStackPointer to the MSP \r
+ * (main stack pointer) Cortex processor register\r
+ */\r
+#if       (__ARMCC_VERSION <  400000)\r
+__ASM void __set_MSP(uint32_t mainStackPointer)\r
+{\r
+  msr msp, r0\r
+  bx lr\r
+}\r
+#endif /*  __ARMCC_VERSION  */ \r
+ \r
+/**\r
+ * @brief  Return the Base Priority value\r
+ *\r
+ * @return BasePriority\r
+ *\r
+ * Return the content of the base priority register\r
+ */\r
+#if       (__ARMCC_VERSION <  400000)\r
+__ASM uint32_t  __get_BASEPRI(void)\r
+{\r
+  mrs r0, basepri\r
+  bx lr\r
+}\r
+#endif /*  __ARMCC_VERSION  */ \r
+\r
+/**\r
+ * @brief  Set the Base Priority value\r
+ *\r
+ * @param  basePri  BasePriority\r
+ *\r
+ * Set the base priority register\r
+ */\r
+#if       (__ARMCC_VERSION <  400000)\r
+__ASM void __set_BASEPRI(uint32_t basePri)\r
+{\r
+  msr basepri, r0\r
+  bx lr\r
+}\r
+#endif /*  __ARMCC_VERSION  */ \r
+ \r
+/**\r
+ * @brief  Return the Priority Mask value\r
+ *\r
+ * @return PriMask\r
+ *\r
+ * Return state of the priority mask bit from the priority mask register\r
+ */\r
+#if       (__ARMCC_VERSION <  400000)\r
+__ASM uint32_t __get_PRIMASK(void)\r
+{\r
+  mrs r0, primask\r
+  bx lr\r
+}\r
+#endif /*  __ARMCC_VERSION  */ \r
+ \r
+/**\r
+ * @brief  Set the Priority Mask value\r
+ *\r
+ * @param  priMask  PriMask\r
+ *\r
+ * Set the priority mask bit in the priority mask register\r
+ */\r
+#if       (__ARMCC_VERSION <  400000)\r
+__ASM void __set_PRIMASK(uint32_t priMask)\r
+{\r
+  msr primask, r0\r
+  bx lr\r
+}\r
+#endif /*  __ARMCC_VERSION  */ \r
+ \r
+/**\r
+ * @brief  Return the Fault Mask value\r
+ *\r
+ * @return FaultMask\r
+ *\r
+ * Return the content of the fault mask register\r
+ */\r
+#if       (__ARMCC_VERSION <  400000)\r
+__ASM uint32_t  __get_FAULTMASK(void)\r
+{\r
+  mrs r0, faultmask\r
+  bx lr\r
+}\r
+#endif /*  __ARMCC_VERSION  */ \r
+\r
+/**\r
+ * @brief  Set the Fault Mask value\r
+ *\r
+ * @param  faultMask  faultMask value\r
+ *\r
+ * Set the fault mask register\r
+ */\r
+#if       (__ARMCC_VERSION <  400000)\r
+__ASM void __set_FAULTMASK(uint32_t faultMask)\r
+{\r
+  msr faultmask, r0\r
+  bx lr\r
+}\r
+#endif /*  __ARMCC_VERSION  */ \r
+\r
+/**\r
+ * @brief  Return the FPSCR value\r
+ *\r
+ * @return FloatingPointStatusControlRegister\r
+ *\r
+ * Return the content of the FPSCR register\r
+ */\r
+\r
+/**\r
+ * @brief  Set the FPSCR value\r
+ *\r
+ * @param  fpscr  FloatingPointStatusControlRegister\r
+ *\r
+ * Set the FPSCR register\r
+ */\r
+\r
+\r
+#elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/\r
+/* obsolete */\r
+#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/\r
+/* obsolete */\r
+#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/\r
+/* obsolete */\r
+#endif\r

diff --git a/Demo/CORTEX_MB9A310_IAR_Keil/Fujitu_source/mb9af314l.h b/Demo/CORTEX_MB9A310_IAR_Keil/Fujitu_source/mb9af314l.h
new file mode 100644 (file)
index 0000000..231bb3e
--- /dev/null
+++ b/Demo/CORTEX_MB9A310_IAR_Keil/Fujitu_source/mb9af314l.h
@@ -0,0 +1,13785 @@
+/************************************************************************/\r
+/*               (C) Fujitsu Semiconductor Europe GmbH (FSEU)           */\r
+/*                                                                      */\r
+/* The following software deliverable is intended for and must only be  */\r
+/* used for reference and in an evaluation laboratory environment.      */\r
+/* It is provided on an as-is basis without charge and is subject to    */\r
+/* alterations.                                                         */\r
+/* It is the user's obligation to fully test the software in its        */\r
+/* environment and to ensure proper functionality, qualification and    */\r
+/* compliance with component specifications.                            */\r
+/*                                                                      */\r
+/* In the event the software deliverable includes the use of open       */\r
+/* source components, the provisions of the governing open source       */\r
+/* license agreement shall apply with respect to such software          */\r
+/* deliverable.                                                         */\r
+/* FSEU does not warrant that the deliverables do not infringe any      */\r
+/* third party intellectual property right (IPR). In the event that     */\r
+/* the deliverables infringe a third party IPR it is the sole           */\r
+/* responsibility of the customer to obtain necessary licenses to       */\r
+/* continue the usage of the deliverable.                               */\r
+/*                                                                      */\r
+/* To the maximum extent permitted by applicable law FSEU disclaims all */\r
+/* warranties, whether express or implied, in particular, but not       */\r
+/* limited to, warranties of merchantability and fitness for a          */\r
+/* particular purpose for which the deliverable is not designated.      */\r
+/*                                                                      */\r
+/* To the maximum extent permitted by applicable law, FSEU's liability  */\r
+/* is restricted to intentional misconduct and gross negligence.        */\r
+/* FSEU is not liable for consequential damages.                        */\r
+/*                                                                      */\r
+/* (V1.5)                                                               */\r
+/************************************************************************/\r
+/*                                                                      */\r
+/*  Header File for Device MB9AF314L                                    */\r
+/*  Version V1.00                                                       */\r
+/*  Date    2011-05-18                                                  */\r
+/*                                                                      */\r
+/************************************************************************/\r
+\r
+#ifndef _MB9AF314L_H_\r
+#define _MB9AF314L_H_\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif \r
+\r
+\r
+/******************************************************************************\r
+ * Configuration of the Cortex-M3 Processor and Core Peripherals\r
+ ******************************************************************************/\r
+#define __MPU_PRESENT           1 /* FM3 provide an MPU                           */\r
+#define __NVIC_PRIO_BITS        4 /* FM3 uses 4 Bits for the Priority Levels      */\r
+#define __Vendor_SysTickConfig  0 /* Set to 1 if different SysTick Config is used */\r
+\r
+\r
+/******************************************************************************\r
+ * Interrupt Number Definition\r
+ ******************************************************************************/\r
+typedef enum IRQn\r
+{\r
+    NMI_IRQn          = -14, /*  2 Non Maskable      */\r
+    HardFault_IRQn    = -13, /*  3 Hard Fault        */\r
+    MemManage_IRQn    = -12, /*  4 Memory Management */\r
+    BusFault_IRQn     = -11, /*  5 Bus Fault         */\r
+    UsageFault_IRQn   = -10, /*  6 Usage Fault       */\r
+    SVC_IRQn          = -5,  /* 11 SV Call           */\r
+    DebugMonitor_IRQn = -4,  /* 12 Debug Monitor     */\r
+    PendSV_IRQn       = -2,  /* 14 Pend SV           */\r
+    SysTick_IRQn      = -1,  /* 15 System Tick       */\r
+\r
+    CSV_IRQn          =  0, /* Clock Super Visor                             */\r
+    SWDT_IRQn         =  1, /* Software Watchdog Timer                       */\r
+    LVD_IRQn          =  2, /* Low Voltage Detector                          */\r
+    WFG_IRQn          =  3, /* Wave Form Generator                           */\r
+    EXINT0_7_IRQn     =  4, /* External Interrupt Request ch.0 to ch.7       */\r
+    EXINT8_15_IRQn    =  5, /* External Interrupt Request ch.8 to ch.15      */\r
+    DTIM_QDU_IRQn     =  6, /* Dual Timer / Quad Decoder                     */\r
+    MFS0RX_IRQn       =  7, /* MultiFunction Serial Reception ch.0           */\r
+    MFS0TX_IRQn       =  8, /* MultiFunction Serial Transmission ch.0        */\r
+    MFS1RX_IRQn       =  9, /* MultiFunction Serial Reception ch.1           */\r
+    MFS1TX_IRQn       = 10, /* MultiFunction Serial Transmission ch.1        */\r
+    MFS2RX_IRQn       = 11, /* MultiFunction Serial Reception ch.2           */\r
+    MFS2TX_IRQn       = 12, /* MultiFunction Serial Transmission ch.2        */\r
+    MFS3RX_IRQn       = 13, /* MultiFunction Serial Reception ch.3           */\r
+    MFS3TX_IRQn       = 14, /* MultiFunction Serial Transmission ch.3        */\r
+    MFS4RX_IRQn       = 15, /* MultiFunction Serial Reception ch.4           */\r
+    MFS4TX_IRQn       = 16, /* MultiFunction Serial Transmission ch.4        */\r
+    MFS5RX_IRQn       = 17, /* MultiFunction Serial Reception ch.5           */\r
+    MFS5TX_IRQn       = 18, /* MultiFunction Serial Transmission ch.5        */\r
+    MFS6RX_IRQn       = 19, /* MultiFunction Serial Reception ch.6           */\r
+    MFS6TX_IRQn       = 20, /* MultiFunction Serial Transmission ch.6        */\r
+    MFS7RX_IRQn       = 21, /* MultiFunction Serial Reception ch.7           */\r
+    MFS7TX_IRQn       = 22, /* MultiFunction Serial Transmission ch.7        */\r
+    PPG_IRQn          = 23, /* PPG                                           */\r
+    OSC_PLL_WC_IRQn   = 24, /* OSC / PLL / Watch Counter                     */\r
+    ADC0_IRQn         = 25, /* ADC0                                          */\r
+    ADC1_IRQn         = 26, /* ADC1                                          */\r
+    /* Reserved       = 27                                                   */\r
+    FRTIM_IRQn        = 28, /* Free-run Timer                                */\r
+    INCAP_IRQn        = 29, /* Input Capture                                 */\r
+    OUTCOMP_IRQn      = 30, /* Output Compare                                */\r
+    BTIM_IRQn         = 31, /* Base Timer ch.0 to ch.7                       */\r
+    /* Reserved       = 32                                                   */\r
+    /* Reserved       = 33                                                   */\r
+    USBF_IRQn         = 34, /* USB Function                                  */\r
+    USBF_USBH_IRQn    = 35, /* USB Function / USB Host                       */\r
+    /* Reserved       = 36                                                   */\r
+    /* Reserved       = 37                                                   */\r
+    DMAC0_IRQn        = 38, /* DMAC ch.0                                     */\r
+    DMAC1_IRQn        = 39, /* DMAC ch.1                                     */\r
+    DMAC2_IRQn        = 40, /* DMAC ch.2                                     */\r
+    DMAC3_IRQn        = 41, /* DMAC ch.3                                     */\r
+    DMAC4_IRQn        = 42, /* DMAC ch.4                                     */\r
+    DMAC5_IRQn        = 43, /* DMAC ch.5                                     */\r
+    DMAC6_IRQn        = 44, /* DMAC ch.6                                     */\r
+    DMAC7_IRQn        = 45  /* DMAC ch.7                                     */\r
+    /* Reserved       = 46                                                   */\r
+    /* Reserved       = 47                                                   */\r
+} IRQn_Type;\r
+\r
+\r
+#include <core_cm3.h>\r
+#include "system_mb9af31x.h"\r
+#include <stdint.h>\r
+\r
+#define SUCCESS  0\r
+#define ERROR    -1\r
+\r
+#ifndef NULL\r
+#define NULL 0\r
+#endif\r
+\r
+\r
+/******************************************************************************/\r
+/*                Device Specific Peripheral Registers structures             */\r
+/******************************************************************************/\r
+\r
+#if defined ( __CC_ARM   )\r
+#pragma anon_unions\r
+#endif\r
+\r
+/******************************************************************************\r
+ * Peripheral register bit fields\r
+ ******************************************************************************/\r
+\r
+/******************************************************************************\r
+ * Flash_IF_MODULE\r
+ ******************************************************************************/\r
+/* Flash_IF_MODULE register bit fields */\r
+typedef struct stc_flash_if_faszr_field\r
+{\r
+  __IO uint32_t ASZ0       : 1;\r
+  __IO uint32_t ASZ1       : 1;\r
+} stc_flash_if_faszr_field_t;\r
+\r
+typedef struct stc_flash_if_frwtr_field\r
+{\r
+  __IO uint32_t RWT0       : 1;\r
+  __IO uint32_t RWT1       : 1;\r
+} stc_flash_if_frwtr_field_t;\r
+\r
+typedef struct stc_flash_if_fstr_field\r
+{\r
+  __IO uint32_t RDY        : 1;\r
+  __IO uint32_t HNG        : 1;\r
+  __IO uint32_t EER        : 1;\r
+} stc_flash_if_fstr_field_t;\r
+\r
+typedef struct stc_flash_if_fsyndn_field\r
+{\r
+  __IO uint32_t SD0        : 1;\r
+  __IO uint32_t SD1        : 1;\r
+  __IO uint32_t SD2        : 1;\r
+} stc_flash_if_fsyndn_field_t;\r
+\r
+typedef struct stc_flash_if_crtrmm_field\r
+{\r
+  __IO uint32_t TRMM0      : 1;\r
+  __IO uint32_t TRMM1      : 1;\r
+  __IO uint32_t TRMM2      : 1;\r
+  __IO uint32_t TRMM3      : 1;\r
+  __IO uint32_t TRMM4      : 1;\r
+  __IO uint32_t TRMM5      : 1;\r
+  __IO uint32_t TRMM6      : 1;\r
+  __IO uint32_t TRMM7      : 1;\r
+  __IO uint32_t TRMM8      : 1;\r
+  __IO uint32_t TRMM9      : 1;\r
+} stc_flash_if_crtrmm_field_t;\r
+\r
+/******************************************************************************\r
+ * Clock_Reset_MODULE\r
+ ******************************************************************************/\r
+/* Clock_Reset_MODULE register bit fields */\r
+typedef struct stc_crg_scm_ctl_field\r
+{\r
+        uint8_t RESERVED1  : 1;\r
+  __IO  uint8_t MOSCE      : 1;\r
+        uint8_t RESERVED2  : 1;\r
+  __IO  uint8_t SOSCE      : 1;\r
+  __IO  uint8_t PLLE       : 1;\r
+  __IO  uint8_t RCS0       : 1;\r
+  __IO  uint8_t RCS1       : 1;\r
+  __IO  uint8_t RCS2       : 1;\r
+} stc_crg_scm_ctl_field_t;\r
+\r
+typedef struct stc_crg_scm_str_field\r
+{\r
+        uint8_t RESERVED1  : 1;\r
+  __IO  uint8_t MORDY      : 1;\r
+        uint8_t RESERVED2  : 1;\r
+  __IO  uint8_t SORDY      : 1;\r
+  __IO  uint8_t PLRDY      : 1;\r
+  __IO  uint8_t RCM0       : 1;\r
+  __IO  uint8_t RCM1       : 1;\r
+  __IO  uint8_t RCM2       : 1;\r
+} stc_crg_scm_str_field_t;\r
+\r
+typedef struct stc_crg_rst_str_field\r
+{\r
+  __IO uint16_t PONR       : 1;\r
+  __IO uint16_t INITX      : 1;\r
+       uint16_t RESERVED1  : 2;\r
+  __IO uint16_t SWDT       : 1;\r
+  __IO uint16_t HWDT       : 1;\r
+  __IO uint16_t CSVR       : 1;\r
+  __IO uint16_t FCSR       : 1;\r
+  __IO uint16_t SRST       : 1;\r
+} stc_crg_rst_str_field_t;\r
+\r
+typedef struct stc_crg_bsc_psr_field\r
+{\r
+  __IO  uint8_t BSR0       : 1;\r
+  __IO  uint8_t BSR1       : 1;\r
+  __IO  uint8_t BSR2       : 1;\r
+} stc_crg_bsc_psr_field_t;\r
+\r
+typedef struct stc_crg_apbc0_psr_field\r
+{\r
+  __IO  uint8_t APBC00     : 1;\r
+  __IO  uint8_t APBC01     : 1;\r
+} stc_crg_apbc0_psr_field_t;\r
+\r
+typedef struct stc_crg_apbc1_psr_field\r
+{\r
+  __IO  uint8_t APBC10     : 1;\r
+  __IO  uint8_t APBC11     : 1;\r
+        uint8_t RESERVED1  : 2;\r
+  __IO  uint8_t APBC1RST   : 1;\r
+        uint8_t RESERVED2  : 2;\r
+  __IO  uint8_t APBC1EN    : 1;\r
+} stc_crg_apbc1_psr_field_t;\r
+\r
+typedef struct stc_crg_apbc2_psr_field\r
+{\r
+  __IO  uint8_t APBC20     : 1;\r
+  __IO  uint8_t APBC21     : 1;\r
+        uint8_t RESERVED1  : 2;\r
+  __IO  uint8_t APBC2RST   : 1;\r
+        uint8_t RESERVED2  : 2;\r
+  __IO  uint8_t APBC2EN    : 1;\r
+} stc_crg_apbc2_psr_field_t;\r
+\r
+typedef struct stc_crg_swc_psr_field\r
+{\r
+  __IO  uint8_t SWDS0      : 1;\r
+  __IO  uint8_t SWDS1      : 1;\r
+        uint8_t RESERVED1  : 5;\r
+  __IO  uint8_t TESTB      : 1;\r
+} stc_crg_swc_psr_field_t;\r
+\r
+typedef struct stc_crg_ttc_psr_field\r
+{\r
+  __IO  uint8_t TTC        : 1;\r
+} stc_crg_ttc_psr_field_t;\r
+\r
+typedef struct stc_crg_csw_tmr_field\r
+{\r
+  __IO  uint8_t MOWT0      : 1;\r
+  __IO  uint8_t MOWT1      : 1;\r
+  __IO  uint8_t MOWT2      : 1;\r
+  __IO  uint8_t MOWT3      : 1;\r
+  __IO  uint8_t SOWT0      : 1;\r
+  __IO  uint8_t SOWT1      : 1;\r
+  __IO  uint8_t SOWT2      : 1;\r
+} stc_crg_csw_tmr_field_t;\r
+\r
+typedef struct stc_crg_psw_tmr_field\r
+{\r
+  __IO  uint8_t POWT0      : 1;\r
+  __IO  uint8_t POWT1      : 1;\r
+  __IO  uint8_t POWT2      : 1;\r
+        uint8_t RESERVED1  : 1;\r
+  __IO  uint8_t PINC       : 1;\r
+} stc_crg_psw_tmr_field_t;\r
+\r
+typedef struct stc_crg_pll_ctl1_field\r
+{\r
+  __IO  uint8_t PLLM0      : 1;\r
+  __IO  uint8_t PLLM1      : 1;\r
+  __IO  uint8_t PLLM2      : 1;\r
+  __IO  uint8_t PLLM3      : 1;\r
+  __IO  uint8_t PLLK0      : 1;\r
+  __IO  uint8_t PLLK1      : 1;\r
+  __IO  uint8_t PLLK2      : 1;\r
+  __IO  uint8_t PLLK3      : 1;\r
+} stc_crg_pll_ctl1_field_t;\r
+\r
+typedef struct stc_crg_pll_ctl2_field\r
+{\r
+  __IO  uint8_t PLLN0      : 1;\r
+  __IO  uint8_t PLLN1      : 1;\r
+  __IO  uint8_t PLLN2      : 1;\r
+  __IO  uint8_t PLLN3      : 1;\r
+  __IO  uint8_t PLLN4      : 1;\r
+  __IO  uint8_t PLLN5      : 1;\r
+} stc_crg_pll_ctl2_field_t;\r
+\r
+typedef struct stc_crg_csv_ctl_field\r
+{\r
+  __IO uint16_t MCSVE      : 1;\r
+  __IO uint16_t SCSVE      : 1;\r
+       uint16_t RESERVED1  : 6;\r
+  __IO uint16_t FCSDE      : 1;\r
+  __IO uint16_t FCSRE      : 1;\r
+       uint16_t RESERVED2  : 2;\r
+  __IO uint16_t FCD0       : 1;\r
+  __IO uint16_t FCD1       : 1;\r
+  __IO uint16_t FCD2       : 1;\r
+} stc_crg_csv_ctl_field_t;\r
+\r
+typedef struct stc_crg_csv_str_field\r
+{\r
+  __IO  uint8_t MCMF       : 1;\r
+  __IO  uint8_t SCMF       : 1;\r
+} stc_crg_csv_str_field_t;\r
+\r
+typedef struct stc_crg_dbwdt_ctl_field\r
+{\r
+        uint8_t RESERVED1  : 5;\r
+  __IO  uint8_t DPSWBE     : 1;\r
+        uint8_t RESERVED2  : 1;\r
+  __IO  uint8_t DPHWBE     : 1;\r
+} stc_crg_dbwdt_ctl_field_t;\r
+\r
+typedef struct stc_crg_int_enr_field\r
+{\r
+  __IO  uint8_t MCSE       : 1;\r
+  __IO  uint8_t SCSE       : 1;\r
+  __IO  uint8_t PCSE       : 1;\r
+        uint8_t RESERVED1  : 2;\r
+  __IO  uint8_t FCSE       : 1;\r
+} stc_crg_int_enr_field_t;\r
+\r
+typedef struct stc_crg_int_str_field\r
+{\r
+  __IO  uint8_t MCSI       : 1;\r
+  __IO  uint8_t SCSI       : 1;\r
+  __IO  uint8_t PCSI       : 1;\r
+        uint8_t RESERVED1  : 2;\r
+  __IO  uint8_t FCSI       : 1;\r
+} stc_crg_int_str_field_t;\r
+\r
+typedef struct stc_crg_int_clr_field\r
+{\r
+  __IO  uint8_t MCSC       : 1;\r
+  __IO  uint8_t SCSC       : 1;\r
+  __IO  uint8_t PCSC       : 1;\r
+        uint8_t RESERVED1  : 2;\r
+  __IO  uint8_t FCSC       : 1;\r
+} stc_crg_int_clr_field_t;\r
+\r
+/******************************************************************************\r
+ * HWWDT_MODULE\r
+ ******************************************************************************/\r
+/* HWWDT_MODULE register bit fields */\r
+typedef struct stc_hwwdt_wdg_ctl_field\r
+{\r
+  __IO  uint8_t INTEN      : 1;\r
+  __IO  uint8_t RESEN      : 1;\r
+} stc_hwwdt_wdg_ctl_field_t;\r
+\r
+typedef struct stc_hwwdt_wdg_ris_field\r
+{\r
+  __IO  uint8_t RIS        : 1;\r
+} stc_hwwdt_wdg_ris_field_t;\r
+\r
+/******************************************************************************\r
+ * SWWDT_MODULE\r
+ ******************************************************************************/\r
+/* SWWDT_MODULE register bit fields */\r
+typedef struct stc_swwdt_wdogcontrol_field\r
+{\r
+  __IO  uint8_t INTEN      : 1;\r
+  __IO  uint8_t RESEN      : 1;\r
+} stc_swwdt_wdogcontrol_field_t;\r
+\r
+typedef struct stc_swwdt_wdogris_field\r
+{\r
+  __IO  uint8_t RIS        : 1;\r
+} stc_swwdt_wdogris_field_t;\r
+\r
+/******************************************************************************\r
+ * DTIM_MODULE\r
+ ******************************************************************************/\r
+/* DTIM_MODULE register bit fields */\r
+typedef struct stc_dtim_timer1control_field\r
+{\r
+  __IO uint32_t ONESHOT    : 1;\r
+  __IO uint32_t TIMERSIZE  : 1;\r
+  __IO uint32_t TIMERPRE0  : 1;\r
+  __IO uint32_t TIMERPRE1  : 1;\r
+       uint32_t RESERVED1  : 1;\r
+  __IO uint32_t INTENABLE  : 1;\r
+  __IO uint32_t TIMERMODE  : 1;\r
+  __IO uint32_t TIMEREN    : 1;\r
+} stc_dtim_timer1control_field_t;\r
+\r
+typedef struct stc_dtim_timer1ris_field\r
+{\r
+  __IO uint32_t TIMERXRIS  : 1;\r
+} stc_dtim_timer1ris_field_t;\r
+\r
+typedef struct stc_dtim_timer1mis_field\r
+{\r
+  __IO uint32_t TIMERXRIS  : 1;\r
+} stc_dtim_timer1mis_field_t;\r
+\r
+typedef struct stc_dtim_timer2control_field\r
+{\r
+  __IO uint32_t ONESHOT    : 1;\r
+  __IO uint32_t TIMERSIZE  : 1;\r
+  __IO uint32_t TIMERPRE0  : 1;\r
+  __IO uint32_t TIMERPRE1  : 1;\r
+       uint32_t RESERVED1  : 1;\r
+  __IO uint32_t INTENABLE  : 1;\r
+  __IO uint32_t TIMERMODE  : 1;\r
+  __IO uint32_t TIMEREN    : 1;\r
+} stc_dtim_timer2control_field_t;\r
+\r
+typedef struct stc_dtim_timer2ris_field\r
+{\r
+  __IO uint32_t TIMERXRIS  : 1;\r
+} stc_dtim_timer2ris_field_t;\r
+\r
+typedef struct stc_dtim_timer2mis_field\r
+{\r
+  __IO uint32_t TIMERXRIS  : 1;\r
+} stc_dtim_timer2mis_field_t;\r
+\r
+/******************************************************************************\r
+ * MFT_FRT_MODULE\r
+ ******************************************************************************/\r
+/* MFT_FRT_MODULE register bit fields */\r
+typedef struct stc_mft_frt_tcsa0_field\r
+{\r
+  __IO uint16_t CLK0       : 1;\r
+  __IO uint16_t CLK1       : 1;\r
+  __IO uint16_t CLK2       : 1;\r
+  __IO uint16_t CLK3       : 1;\r
+  __IO uint16_t SCLR       : 1;\r
+  __IO uint16_t MODE       : 1;\r
+  __IO uint16_t STOP       : 1;\r
+  __IO uint16_t BFE        : 1;\r
+  __IO uint16_t ICRE       : 1;\r
+  __IO uint16_t ICLR       : 1;\r
+       uint16_t RESERVED1  : 3;\r
+  __IO uint16_t IRQZE      : 1;\r
+  __IO uint16_t IRQZF      : 1;\r
+  __IO uint16_t ECKE       : 1;\r
+} stc_mft_frt_tcsa0_field_t;\r
+\r
+typedef struct stc_mft_frt_tcsb0_field\r
+{\r
+  __IO uint16_t AD0E       : 1;\r
+  __IO uint16_t AD1E       : 1;\r
+  __IO uint16_t AD2E       : 1;\r
+} stc_mft_frt_tcsb0_field_t;\r
+\r
+typedef struct stc_mft_frt_tcsa1_field\r
+{\r
+  __IO uint16_t CLK0       : 1;\r
+  __IO uint16_t CLK1       : 1;\r
+  __IO uint16_t CLK2       : 1;\r
+  __IO uint16_t CLK3       : 1;\r
+  __IO uint16_t SCLR       : 1;\r
+  __IO uint16_t MODE       : 1;\r
+  __IO uint16_t STOP       : 1;\r
+  __IO uint16_t BFE        : 1;\r
+  __IO uint16_t ICRE       : 1;\r
+  __IO uint16_t ICLR       : 1;\r
+       uint16_t RESERVED1  : 3;\r
+  __IO uint16_t IRQZE      : 1;\r
+  __IO uint16_t IRQZF      : 1;\r
+  __IO uint16_t ECKE       : 1;\r
+} stc_mft_frt_tcsa1_field_t;\r
+\r
+typedef struct stc_mft_frt_tcsb1_field\r
+{\r
+  __IO uint16_t AD0E       : 1;\r
+  __IO uint16_t AD1E       : 1;\r
+  __IO uint16_t AD2E       : 1;\r
+} stc_mft_frt_tcsb1_field_t;\r
+\r
+typedef struct stc_mft_frt_tcsa2_field\r
+{\r
+  __IO uint16_t CLK0       : 1;\r
+  __IO uint16_t CLK1       : 1;\r
+  __IO uint16_t CLK2       : 1;\r
+  __IO uint16_t CLK3       : 1;\r
+  __IO uint16_t SCLR       : 1;\r
+  __IO uint16_t MODE       : 1;\r
+  __IO uint16_t STOP       : 1;\r
+  __IO uint16_t BFE        : 1;\r
+  __IO uint16_t ICRE       : 1;\r
+  __IO uint16_t ICLR       : 1;\r
+       uint16_t RESERVED1  : 3;\r
+  __IO uint16_t IRQZE      : 1;\r
+  __IO uint16_t IRQZF      : 1;\r
+  __IO uint16_t ECKE       : 1;\r
+} stc_mft_frt_tcsa2_field_t;\r
+\r
+typedef struct stc_mft_frt_tcsb2_field\r
+{\r
+  __IO uint16_t AD0E       : 1;\r
+  __IO uint16_t AD1E       : 1;\r
+  __IO uint16_t AD2E       : 1;\r
+} stc_mft_frt_tcsb2_field_t;\r
+\r
+/******************************************************************************\r
+ * MFT_OCU_MODULE\r
+ ******************************************************************************/\r
+/* MFT_OCU_MODULE register bit fields */\r
+typedef struct stc_mft_ocu_ocsa10_field\r
+{\r
+  __IO  uint8_t CST0       : 1;\r
+  __IO  uint8_t CST1       : 1;\r
+  __IO  uint8_t BDIS0      : 1;\r
+  __IO  uint8_t BDIS1      : 1;\r
+  __IO  uint8_t IOE0       : 1;\r
+  __IO  uint8_t IOE1       : 1;\r
+  __IO  uint8_t IOP0       : 1;\r
+  __IO  uint8_t IOP1       : 1;\r
+} stc_mft_ocu_ocsa10_field_t;\r
+\r
+typedef struct stc_mft_ocu_ocsb10_field\r
+{\r
+  __IO  uint8_t OTD0       : 1;\r
+  __IO  uint8_t OTD1       : 1;\r
+        uint8_t RESERVED1  : 2;\r
+  __IO  uint8_t CMOD       : 1;\r
+  __IO  uint8_t BTS0       : 1;\r
+  __IO  uint8_t BTS1       : 1;\r
+} stc_mft_ocu_ocsb10_field_t;\r
+\r
+typedef struct stc_mft_ocu_ocsa32_field\r
+{\r
+  __IO  uint8_t CST2       : 1;\r
+  __IO  uint8_t CST3       : 1;\r
+  __IO  uint8_t BDIS2      : 1;\r
+  __IO  uint8_t BDIS3      : 1;\r
+  __IO  uint8_t IOE2       : 1;\r
+  __IO  uint8_t IOE3       : 1;\r
+  __IO  uint8_t IOP2       : 1;\r
+  __IO  uint8_t IOP3       : 1;\r
+} stc_mft_ocu_ocsa32_field_t;\r
+\r
+typedef struct stc_mft_ocu_ocsb32_field\r
+{\r
+  __IO  uint8_t OTD2       : 1;\r
+  __IO  uint8_t OTD3       : 1;\r
+        uint8_t RESERVED1  : 2;\r
+  __IO  uint8_t CMOD       : 1;\r
+  __IO  uint8_t BTS2       : 1;\r
+  __IO  uint8_t BTS3       : 1;\r
+} stc_mft_ocu_ocsb32_field_t;\r
+\r
+typedef struct stc_mft_ocu_ocsa54_field\r
+{\r
+  __IO  uint8_t CST4       : 1;\r
+  __IO  uint8_t CST5       : 1;\r
+  __IO  uint8_t BDIS4      : 1;\r
+  __IO  uint8_t BDIS5      : 1;\r
+  __IO  uint8_t IOE4       : 1;\r
+  __IO  uint8_t IOE5       : 1;\r
+  __IO  uint8_t IOP4       : 1;\r
+  __IO  uint8_t IOP5       : 1;\r
+} stc_mft_ocu_ocsa54_field_t;\r
+\r
+typedef struct stc_mft_ocu_ocsb54_field\r
+{\r
+  __IO  uint8_t OTD4       : 1;\r
+  __IO  uint8_t OTD5       : 1;\r
+        uint8_t RESERVED1  : 2;\r
+  __IO  uint8_t CMOD       : 1;\r
+  __IO  uint8_t BTS4       : 1;\r
+  __IO  uint8_t BTS5       : 1;\r
+} stc_mft_ocu_ocsb54_field_t;\r
+\r
+typedef struct stc_mft_ocu_ocsc_field\r
+{\r
+  __IO  uint8_t MOD0       : 1;\r
+  __IO  uint8_t MOD1       : 1;\r
+  __IO  uint8_t MOD2       : 1;\r
+  __IO  uint8_t MOD3       : 1;\r
+  __IO  uint8_t MOD4       : 1;\r
+  __IO  uint8_t MOD5       : 1;\r
+} stc_mft_ocu_ocsc_field_t;\r
+\r
+typedef struct stc_mft_ocu_ocfs10_field\r
+{\r
+  __IO  uint8_t FSO00      : 1;\r
+  __IO  uint8_t FSO01      : 1;\r
+  __IO  uint8_t FSO02      : 1;\r
+  __IO  uint8_t FSO03      : 1;\r
+  __IO  uint8_t FSO10      : 1;\r
+  __IO  uint8_t FSO11      : 1;\r
+  __IO  uint8_t FSO12      : 1;\r
+  __IO  uint8_t FSO13      : 1;\r
+} stc_mft_ocu_ocfs10_field_t;\r
+\r
+typedef struct stc_mft_ocu_ocfs32_field\r
+{\r
+  __IO  uint8_t FSO20      : 1;\r
+  __IO  uint8_t FSO21      : 1;\r
+  __IO  uint8_t FSO22      : 1;\r
+  __IO  uint8_t FSO23      : 1;\r
+  __IO  uint8_t FSO30      : 1;\r
+  __IO  uint8_t FSO31      : 1;\r
+  __IO  uint8_t FSO32      : 1;\r
+  __IO  uint8_t FSO33      : 1;\r
+} stc_mft_ocu_ocfs32_field_t;\r
+\r
+typedef struct stc_mft_ocu_ocfs54_field\r
+{\r
+  __IO  uint8_t FSO40      : 1;\r
+  __IO  uint8_t FSO41      : 1;\r
+  __IO  uint8_t FSO42      : 1;\r
+  __IO  uint8_t FSO43      : 1;\r
+  __IO  uint8_t FSO50      : 1;\r
+  __IO  uint8_t FSO51      : 1;\r
+  __IO  uint8_t FSO52      : 1;\r
+  __IO  uint8_t FSO53      : 1;\r
+} stc_mft_ocu_ocfs54_field_t;\r
+\r
+/******************************************************************************\r
+ * MFT_WFG_MODULE\r
+ ******************************************************************************/\r
+/* MFT_WFG_MODULE register bit fields */\r
+typedef struct stc_mft_wfg_wfsa10_field\r
+{\r
+  __IO uint16_t DCK0       : 1;\r
+  __IO uint16_t DCK1       : 1;\r
+  __IO uint16_t DCK2       : 1;\r
+  __IO uint16_t TMD0       : 1;\r
+  __IO uint16_t TMD1       : 1;\r
+  __IO uint16_t TMD2       : 1;\r
+  __IO uint16_t GTEN0      : 1;\r
+  __IO uint16_t GTEN1      : 1;\r
+  __IO uint16_t PSEL0      : 1;\r
+  __IO uint16_t PSEL1      : 1;\r
+  __IO uint16_t PGEN0      : 1;\r
+  __IO uint16_t PGEN1      : 1;\r
+  __IO uint16_t DMOD       : 1;\r
+} stc_mft_wfg_wfsa10_field_t;\r
+\r
+typedef struct stc_mft_wfg_wfsa32_field\r
+{\r
+  __IO uint16_t DCK0       : 1;\r
+  __IO uint16_t DCK1       : 1;\r
+  __IO uint16_t DCK2       : 1;\r
+  __IO uint16_t TMD0       : 1;\r
+  __IO uint16_t TMD1       : 1;\r
+  __IO uint16_t TMD2       : 1;\r
+  __IO uint16_t GTEN0      : 1;\r
+  __IO uint16_t GTEN1      : 1;\r
+  __IO uint16_t PSEL0      : 1;\r
+  __IO uint16_t PSEL1      : 1;\r
+  __IO uint16_t PGEN0      : 1;\r
+  __IO uint16_t PGEN1      : 1;\r
+  __IO uint16_t DMOD       : 1;\r
+} stc_mft_wfg_wfsa32_field_t;\r
+\r
+typedef struct stc_mft_wfg_wfsa54_field\r
+{\r
+  __IO uint16_t DCK0       : 1;\r
+  __IO uint16_t DCK1       : 1;\r
+  __IO uint16_t DCK2       : 1;\r
+  __IO uint16_t TMD0       : 1;\r
+  __IO uint16_t TMD1       : 1;\r
+  __IO uint16_t TMD2       : 1;\r
+  __IO uint16_t GTEN0      : 1;\r
+  __IO uint16_t GTEN1      : 1;\r
+  __IO uint16_t PSEL0      : 1;\r
+  __IO uint16_t PSEL1      : 1;\r
+  __IO uint16_t PGEN0      : 1;\r
+  __IO uint16_t PGEN1      : 1;\r
+  __IO uint16_t DMOD       : 1;\r
+} stc_mft_wfg_wfsa54_field_t;\r
+\r
+typedef struct stc_mft_wfg_wfir_field\r
+{\r
+  __IO uint16_t DTIF       : 1;\r
+  __IO uint16_t DTIC       : 1;\r
+       uint16_t RESERVED1  : 2;\r
+  __IO uint16_t TMIF10     : 1;\r
+  __IO uint16_t TMIC10     : 1;\r
+  __IO uint16_t TMIE10     : 1;\r
+  __IO uint16_t TMIS10     : 1;\r
+  __IO uint16_t TMIF32     : 1;\r
+  __IO uint16_t TMIC32     : 1;\r
+  __IO uint16_t TMIE32     : 1;\r
+  __IO uint16_t TMIS32     : 1;\r
+  __IO uint16_t TMIF54     : 1;\r
+  __IO uint16_t TMIC54     : 1;\r
+  __IO uint16_t TMIE54     : 1;\r
+  __IO uint16_t TMIS54     : 1;\r
+} stc_mft_wfg_wfir_field_t;\r
+\r
+typedef struct stc_mft_wfg_nzcl_field\r
+{\r
+  __IO uint16_t DTIE       : 1;\r
+  __IO uint16_t NWS0       : 1;\r
+  __IO uint16_t NWS1       : 1;\r
+  __IO uint16_t NWS2       : 1;\r
+  __IO uint16_t SDTI       : 1;\r
+} stc_mft_wfg_nzcl_field_t;\r
+\r
+/******************************************************************************\r
+ * MFT_ICU_MODULE\r
+ ******************************************************************************/\r
+/* MFT_ICU_MODULE register bit fields */\r
+typedef struct stc_mft_icu_icfs10_field\r
+{\r
+  __IO  uint8_t FSI00      : 1;\r
+  __IO  uint8_t FSI01      : 1;\r
+  __IO  uint8_t FSI02      : 1;\r
+  __IO  uint8_t FSI03      : 1;\r
+  __IO  uint8_t FSI10      : 1;\r
+  __IO  uint8_t FSI11      : 1;\r
+  __IO  uint8_t FSI12      : 1;\r
+  __IO  uint8_t FSI13      : 1;\r
+} stc_mft_icu_icfs10_field_t;\r
+\r
+typedef struct stc_mft_icu_icfs32_field\r
+{\r
+  __IO  uint8_t FSI20      : 1;\r
+  __IO  uint8_t FSI21      : 1;\r
+  __IO  uint8_t FSI22      : 1;\r
+  __IO  uint8_t FSI23      : 1;\r
+  __IO  uint8_t FSI30      : 1;\r
+  __IO  uint8_t FSI31      : 1;\r
+  __IO  uint8_t FSI32      : 1;\r
+  __IO  uint8_t FSI33      : 1;\r
+} stc_mft_icu_icfs32_field_t;\r
+\r
+typedef struct stc_mft_icu_icsa10_field\r
+{\r
+  __IO  uint8_t EG00       : 1;\r
+  __IO  uint8_t EG01       : 1;\r
+  __IO  uint8_t EG10       : 1;\r
+  __IO  uint8_t EG11       : 1;\r
+  __IO  uint8_t ICE0       : 1;\r
+  __IO  uint8_t ICE1       : 1;\r
+  __IO  uint8_t ICP0       : 1;\r
+  __IO  uint8_t ICP1       : 1;\r
+} stc_mft_icu_icsa10_field_t;\r
+\r
+typedef struct stc_mft_icu_icsb10_field\r
+{\r
+  __IO  uint8_t IEI0       : 1;\r
+  __IO  uint8_t IEI1       : 1;\r
+} stc_mft_icu_icsb10_field_t;\r
+\r
+typedef struct stc_mft_icu_icsa32_field\r
+{\r
+  __IO  uint8_t EG20       : 1;\r
+  __IO  uint8_t EG21       : 1;\r
+  __IO  uint8_t EG30       : 1;\r
+  __IO  uint8_t EG31       : 1;\r
+  __IO  uint8_t ICE2       : 1;\r
+  __IO  uint8_t ICE3       : 1;\r
+  __IO  uint8_t ICP2       : 1;\r
+  __IO  uint8_t ICP3       : 1;\r
+} stc_mft_icu_icsa32_field_t;\r
+\r
+typedef struct stc_mft_icu_icsb32_field\r
+{\r
+  __IO  uint8_t IEI2       : 1;\r
+  __IO  uint8_t IEI3       : 1;\r
+} stc_mft_icu_icsb32_field_t;\r
+\r
+/******************************************************************************\r
+ * MFT_ADCMP_MODULE\r
+ ******************************************************************************/\r
+/* MFT_ADCMP_MODULE register bit fields */\r
+typedef struct stc_mft_adcmp_acsb_field\r
+{\r
+  __IO  uint8_t BDIS0      : 1;\r
+  __IO  uint8_t BDIS1      : 1;\r
+  __IO  uint8_t BDIS2      : 1;\r
+        uint8_t RESERVED1  : 1;\r
+  __IO  uint8_t BTS0       : 1;\r
+  __IO  uint8_t BTS1       : 1;\r
+  __IO  uint8_t BTS2       : 1;\r
+} stc_mft_adcmp_acsb_field_t;\r
+\r
+typedef struct stc_mft_adcmp_acsa_field\r
+{\r
+  __IO uint16_t CE00       : 1;\r
+  __IO uint16_t CE01       : 1;\r
+  __IO uint16_t CE10       : 1;\r
+  __IO uint16_t CE11       : 1;\r
+  __IO uint16_t CE20       : 1;\r
+  __IO uint16_t CE21       : 1;\r
+       uint16_t RESERVED1  : 2;\r
+  __IO uint16_t SEL00      : 1;\r
+  __IO uint16_t SEL01      : 1;\r
+  __IO uint16_t SEL10      : 1;\r
+  __IO uint16_t SEL11      : 1;\r
+  __IO uint16_t SEL20      : 1;\r
+  __IO uint16_t SEL21      : 1;\r
+} stc_mft_adcmp_acsa_field_t;\r
+\r
+typedef struct stc_mft_adcmp_atsa_field\r
+{\r
+  __IO uint16_t AD0S0      : 1;\r
+  __IO uint16_t AD0S1      : 1;\r
+  __IO uint16_t AD1S0      : 1;\r
+  __IO uint16_t AD1S1      : 1;\r
+  __IO uint16_t AD2S0      : 1;\r
+  __IO uint16_t AD2S1      : 1;\r
+       uint16_t RESERVED1  : 2;\r
+  __IO uint16_t AD0P0      : 1;\r
+  __IO uint16_t AD0P1      : 1;\r
+  __IO uint16_t AD1P0      : 1;\r
+  __IO uint16_t AD1P1      : 1;\r
+  __IO uint16_t AD2P0      : 1;\r
+  __IO uint16_t AD2P1      : 1;\r
+} stc_mft_adcmp_atsa_field_t;\r
+\r
+/******************************************************************************\r
+ * MFT_PPG_MODULE\r
+ ******************************************************************************/\r
+/* MFT_PPG_MODULE register bit fields */\r
+typedef struct stc_mft_ppg_ttcr0_field\r
+{\r
+  __IO  uint8_t STR0       : 1;\r
+  __IO  uint8_t MONI0      : 1;\r
+  __IO  uint8_t CS00       : 1;\r
+  __IO  uint8_t CS01       : 1;\r
+  __IO  uint8_t TRG0O      : 1;\r
+  __IO  uint8_t TRG2O      : 1;\r
+  __IO  uint8_t TRG4O      : 1;\r
+  __IO  uint8_t TRG6O      : 1;\r
+} stc_mft_ppg_ttcr0_field_t;\r
+\r
+typedef struct stc_mft_ppg_ttcr1_field\r
+{\r
+  __IO  uint8_t STR1       : 1;\r
+  __IO  uint8_t MONI1      : 1;\r
+  __IO  uint8_t CS10       : 1;\r
+  __IO  uint8_t CS11       : 1;\r
+  __IO  uint8_t TRG1O      : 1;\r
+  __IO  uint8_t TRG3O      : 1;\r
+  __IO  uint8_t TRG5O      : 1;\r
+  __IO  uint8_t TRG7O      : 1;\r
+} stc_mft_ppg_ttcr1_field_t;\r
+\r
+typedef struct stc_mft_ppg_trg_field\r
+{\r
+  __IO uint16_t PEN00      : 1;\r
+  __IO uint16_t PEN01      : 1;\r
+  __IO uint16_t PEN02      : 1;\r
+  __IO uint16_t PEN03      : 1;\r
+  __IO uint16_t PEN04      : 1;\r
+  __IO uint16_t PEN05      : 1;\r
+  __IO uint16_t PEN06      : 1;\r
+  __IO uint16_t PEN07      : 1;\r
+  __IO uint16_t PEN08      : 1;\r
+  __IO uint16_t PEN09      : 1;\r
+  __IO uint16_t PEN10      : 1;\r
+  __IO uint16_t PEN11      : 1;\r
+  __IO uint16_t PEN12      : 1;\r
+  __IO uint16_t PEN13      : 1;\r
+  __IO uint16_t PEN14      : 1;\r
+  __IO uint16_t PEN15      : 1;\r
+} stc_mft_ppg_trg_field_t;\r
+\r
+typedef struct stc_mft_ppg_revc_field\r
+{\r
+  __IO uint16_t REV00      : 1;\r
+  __IO uint16_t REV01      : 1;\r
+  __IO uint16_t REV02      : 1;\r
+  __IO uint16_t REV03      : 1;\r
+  __IO uint16_t REV04      : 1;\r
+  __IO uint16_t REV05      : 1;\r
+  __IO uint16_t REV06      : 1;\r
+  __IO uint16_t REV07      : 1;\r
+  __IO uint16_t REV08      : 1;\r
+  __IO uint16_t REV09      : 1;\r
+  __IO uint16_t REV10      : 1;\r
+  __IO uint16_t REV11      : 1;\r
+  __IO uint16_t REV12      : 1;\r
+  __IO uint16_t REV13      : 1;\r
+  __IO uint16_t REV14      : 1;\r
+  __IO uint16_t REV15      : 1;\r
+} stc_mft_ppg_revc_field_t;\r
+\r
+typedef struct stc_mft_ppg_ppgc1_field\r
+{\r
+  __IO  uint8_t TTRG       : 1;\r
+  __IO  uint8_t MD0        : 1;\r
+  __IO  uint8_t MD1        : 1;\r
+  __IO  uint8_t PCS0       : 1;\r
+  __IO  uint8_t PCS1       : 1;\r
+  __IO  uint8_t INTM       : 1;\r
+  __IO  uint8_t PUF        : 1;\r
+  __IO  uint8_t PIE        : 1;\r
+} stc_mft_ppg_ppgc1_field_t;\r
+\r
+typedef struct stc_mft_ppg_ppgc0_field\r
+{\r
+  __IO  uint8_t TTRG       : 1;\r
+  __IO  uint8_t MD0        : 1;\r
+  __IO  uint8_t MD1        : 1;\r
+  __IO  uint8_t PCS0       : 1;\r
+  __IO  uint8_t PCS1       : 1;\r
+  __IO  uint8_t INTM       : 1;\r
+  __IO  uint8_t PUF        : 1;\r
+  __IO  uint8_t PIE        : 1;\r
+} stc_mft_ppg_ppgc0_field_t;\r
+\r
+typedef struct stc_mft_ppg_ppgc3_field\r
+{\r
+  __IO  uint8_t TTRG       : 1;\r
+  __IO  uint8_t MD0        : 1;\r
+  __IO  uint8_t MD1        : 1;\r
+  __IO  uint8_t PCS0       : 1;\r
+  __IO  uint8_t PCS1       : 1;\r
+  __IO  uint8_t INTM       : 1;\r
+  __IO  uint8_t PUF        : 1;\r
+  __IO  uint8_t PIE        : 1;\r
+} stc_mft_ppg_ppgc3_field_t;\r
+\r
+typedef struct stc_mft_ppg_ppgc2_field\r
+{\r
+  __IO  uint8_t TTRG       : 1;\r
+  __IO  uint8_t MD0        : 1;\r
+  __IO  uint8_t MD1        : 1;\r
+  __IO  uint8_t PCS0       : 1;\r
+  __IO  uint8_t PCS1       : 1;\r
+  __IO  uint8_t INTM       : 1;\r
+  __IO  uint8_t PUF        : 1;\r
+  __IO  uint8_t PIE        : 1;\r
+} stc_mft_ppg_ppgc2_field_t;\r
+\r
+typedef struct stc_mft_ppg_gatec0_field\r
+{\r
+  __IO  uint8_t EDGE0      : 1;\r
+  __IO  uint8_t STRG0      : 1;\r
+        uint8_t RESERVED1  : 2;\r
+  __IO  uint8_t EDGE2      : 1;\r
+  __IO  uint8_t STRG2      : 1;\r
+} stc_mft_ppg_gatec0_field_t;\r
+\r
+typedef struct stc_mft_ppg_ppgc5_field\r
+{\r
+  __IO  uint8_t TTRG       : 1;\r
+  __IO  uint8_t MD0        : 1;\r
+  __IO  uint8_t MD1        : 1;\r
+  __IO  uint8_t PCS0       : 1;\r
+  __IO  uint8_t PCS1       : 1;\r
+  __IO  uint8_t INTM       : 1;\r
+  __IO  uint8_t PUF        : 1;\r
+  __IO  uint8_t PIE        : 1;\r
+} stc_mft_ppg_ppgc5_field_t;\r
+\r
+typedef struct stc_mft_ppg_ppgc4_field\r
+{\r
+  __IO  uint8_t TTRG       : 1;\r
+  __IO  uint8_t MD0        : 1;\r
+  __IO  uint8_t MD1        : 1;\r
+  __IO  uint8_t PCS0       : 1;\r
+  __IO  uint8_t PCS1       : 1;\r
+  __IO  uint8_t INTM       : 1;\r
+  __IO  uint8_t PUF        : 1;\r
+  __IO  uint8_t PIE        : 1;\r
+} stc_mft_ppg_ppgc4_field_t;\r
+\r
+typedef struct stc_mft_ppg_ppgc7_field\r
+{\r
+  __IO  uint8_t TTRG       : 1;\r
+  __IO  uint8_t MD0        : 1;\r
+  __IO  uint8_t MD1        : 1;\r
+  __IO  uint8_t PCS0       : 1;\r
+  __IO  uint8_t PCS1       : 1;\r
+  __IO  uint8_t INTM       : 1;\r
+  __IO  uint8_t PUF        : 1;\r
+  __IO  uint8_t PIE        : 1;\r
+} stc_mft_ppg_ppgc7_field_t;\r
+\r
+typedef struct stc_mft_ppg_ppgc6_field\r
+{\r
+  __IO  uint8_t TTRG       : 1;\r
+  __IO  uint8_t MD0        : 1;\r
+  __IO  uint8_t MD1        : 1;\r
+  __IO  uint8_t PCS0       : 1;\r
+  __IO  uint8_t PCS1       : 1;\r
+  __IO  uint8_t INTM       : 1;\r
+  __IO  uint8_t PUF        : 1;\r
+  __IO  uint8_t PIE        : 1;\r
+} stc_mft_ppg_ppgc6_field_t;\r
+\r
+typedef struct stc_mft_ppg_gatec4_field\r
+{\r
+  __IO  uint8_t EDGE4      : 1;\r
+  __IO  uint8_t STRG4      : 1;\r
+        uint8_t RESERVED1  : 2;\r
+  __IO  uint8_t EDGE6      : 1;\r
+  __IO  uint8_t STRG6      : 1;\r
+} stc_mft_ppg_gatec4_field_t;\r
+\r
+typedef struct stc_mft_ppg_ppgc9_field\r
+{\r
+  __IO  uint8_t TTRG       : 1;\r
+  __IO  uint8_t MD0        : 1;\r
+  __IO  uint8_t MD1        : 1;\r
+  __IO  uint8_t PCS0       : 1;\r
+  __IO  uint8_t PCS1       : 1;\r
+  __IO  uint8_t INTM       : 1;\r
+  __IO  uint8_t PUF        : 1;\r
+  __IO  uint8_t PIE        : 1;\r
+} stc_mft_ppg_ppgc9_field_t;\r
+\r
+typedef struct stc_mft_ppg_ppgc8_field\r
+{\r
+  __IO  uint8_t TTRG       : 1;\r
+  __IO  uint8_t MD0        : 1;\r
+  __IO  uint8_t MD1        : 1;\r
+  __IO  uint8_t PCS0       : 1;\r
+  __IO  uint8_t PCS1       : 1;\r
+  __IO  uint8_t INTM       : 1;\r
+  __IO  uint8_t PUF        : 1;\r
+  __IO  uint8_t PIE        : 1;\r
+} stc_mft_ppg_ppgc8_field_t;\r
+\r
+typedef struct stc_mft_ppg_ppgc11_field\r
+{\r
+  __IO  uint8_t TTRG       : 1;\r
+  __IO  uint8_t MD0        : 1;\r
+  __IO  uint8_t MD1        : 1;\r
+  __IO  uint8_t PCS0       : 1;\r
+  __IO  uint8_t PCS1       : 1;\r
+  __IO  uint8_t INTM       : 1;\r
+  __IO  uint8_t PUF        : 1;\r
+  __IO  uint8_t PIE        : 1;\r
+} stc_mft_ppg_ppgc11_field_t;\r
+\r
+typedef struct stc_mft_ppg_ppgc10_field\r
+{\r
+  __IO  uint8_t TTRG       : 1;\r
+  __IO  uint8_t MD0        : 1;\r
+  __IO  uint8_t MD1        : 1;\r
+  __IO  uint8_t PCS0       : 1;\r
+  __IO  uint8_t PCS1       : 1;\r
+  __IO  uint8_t INTM       : 1;\r
+  __IO  uint8_t PUF        : 1;\r
+  __IO  uint8_t PIE        : 1;\r
+} stc_mft_ppg_ppgc10_field_t;\r
+\r
+typedef struct stc_mft_ppg_gatec8_field\r
+{\r
+  __IO  uint8_t EDGE8      : 1;\r
+  __IO  uint8_t STRG8      : 1;\r
+        uint8_t RESERVED1  : 2;\r
+  __IO  uint8_t EDGE10     : 1;\r
+  __IO  uint8_t STRG10     : 1;\r
+} stc_mft_ppg_gatec8_field_t;\r
+\r
+typedef struct stc_mft_ppg_ppgc13_field\r
+{\r
+  __IO  uint8_t TTRG       : 1;\r
+  __IO  uint8_t MD0        : 1;\r
+  __IO  uint8_t MD1        : 1;\r
+  __IO  uint8_t PCS0       : 1;\r
+  __IO  uint8_t PCS1       : 1;\r
+  __IO  uint8_t INTM       : 1;\r
+  __IO  uint8_t PUF        : 1;\r
+  __IO  uint8_t PIE        : 1;\r
+} stc_mft_ppg_ppgc13_field_t;\r
+\r
+typedef struct stc_mft_ppg_ppgc12_field\r
+{\r
+  __IO  uint8_t TTRG       : 1;\r
+  __IO  uint8_t MD0        : 1;\r
+  __IO  uint8_t MD1        : 1;\r
+  __IO  uint8_t PCS0       : 1;\r
+  __IO  uint8_t PCS1       : 1;\r
+  __IO  uint8_t INTM       : 1;\r
+  __IO  uint8_t PUF        : 1;\r
+  __IO  uint8_t PIE        : 1;\r
+} stc_mft_ppg_ppgc12_field_t;\r
+\r
+typedef struct stc_mft_ppg_ppgc15_field\r
+{\r
+  __IO  uint8_t TTRG       : 1;\r
+  __IO  uint8_t MD0        : 1;\r
+  __IO  uint8_t MD1        : 1;\r
+  __IO  uint8_t PCS0       : 1;\r
+  __IO  uint8_t PCS1       : 1;\r
+  __IO  uint8_t INTM       : 1;\r
+  __IO  uint8_t PUF        : 1;\r
+  __IO  uint8_t PIE        : 1;\r
+} stc_mft_ppg_ppgc15_field_t;\r
+\r
+typedef struct stc_mft_ppg_ppgc14_field\r
+{\r
+  __IO  uint8_t TTRG       : 1;\r
+  __IO  uint8_t MD0        : 1;\r
+  __IO  uint8_t MD1        : 1;\r
+  __IO  uint8_t PCS0       : 1;\r
+  __IO  uint8_t PCS1       : 1;\r
+  __IO  uint8_t INTM       : 1;\r
+  __IO  uint8_t PUF        : 1;\r
+  __IO  uint8_t PIE        : 1;\r
+} stc_mft_ppg_ppgc14_field_t;\r
+\r
+typedef struct stc_mft_ppg_gatec12_field\r
+{\r
+  __IO  uint8_t EDGE12     : 1;\r
+  __IO  uint8_t STRG12     : 1;\r
+        uint8_t RESERVED1  : 2;\r
+  __IO  uint8_t EDGE14     : 1;\r
+  __IO  uint8_t STRG14     : 1;\r
+} stc_mft_ppg_gatec12_field_t;\r
+\r
+/******************************************************************************\r
+ * BT_PPG_MODULE\r
+ ******************************************************************************/\r
+/* BT_PPG_MODULE register bit fields */\r
+typedef struct stc_bt_ppg_tmcr_field\r
+{\r
+  __IO uint16_t STRG       : 1;\r
+  __IO uint16_t CTEN       : 1;\r
+  __IO uint16_t MDSE       : 1;\r
+  __IO uint16_t OSEL       : 1;\r
+  __IO uint16_t FMD0       : 1;\r
+  __IO uint16_t FMD1       : 1;\r
+  __IO uint16_t FMD2       : 1;\r
+       uint16_t RESERVED1  : 1;\r
+  __IO uint16_t EGS0       : 1;\r
+  __IO uint16_t EGS1       : 1;\r
+  __IO uint16_t PMSK       : 1;\r
+  __IO uint16_t RTGEN      : 1;\r
+  __IO uint16_t CKS0       : 1;\r
+  __IO uint16_t CKS1       : 1;\r
+  __IO uint16_t CKS2       : 1;\r
+} stc_bt_ppg_tmcr_field_t;\r
+\r
+typedef struct stc_bt_ppg_stc_field\r
+{\r
+  __IO  uint8_t UDIR       : 1;\r
+        uint8_t RESERVED1  : 1;\r
+  __IO  uint8_t TGIR       : 1;\r
+        uint8_t RESERVED2  : 1;\r
+  __IO  uint8_t UDIE       : 1;\r
+        uint8_t RESERVED3  : 1;\r
+  __IO  uint8_t TGIE       : 1;\r
+} stc_bt_ppg_stc_field_t;\r
+\r
+typedef struct stc_bt_ppg_tmcr2_field\r
+{\r
+  __IO  uint8_t CKS3       : 1;\r
+} stc_bt_ppg_tmcr2_field_t;\r
+\r
+/******************************************************************************\r
+ * BT_PWM_MODULE\r
+ ******************************************************************************/\r
+/* BT_PWM_MODULE register bit fields */\r
+typedef struct stc_bt_pwm_tmcr_field\r
+{\r
+  __IO uint16_t STRG       : 1;\r
+  __IO uint16_t CTEN       : 1;\r
+  __IO uint16_t MDSE       : 1;\r
+  __IO uint16_t OSEL       : 1;\r
+  __IO uint16_t FMD0       : 1;\r
+  __IO uint16_t FMD1       : 1;\r
+  __IO uint16_t FMD2       : 1;\r
+       uint16_t RESERVED1  : 1;\r
+  __IO uint16_t EGS0       : 1;\r
+  __IO uint16_t EGS1       : 1;\r
+  __IO uint16_t PMSK       : 1;\r
+  __IO uint16_t RTGEN      : 1;\r
+  __IO uint16_t CKS0       : 1;\r
+  __IO uint16_t CKS1       : 1;\r
+  __IO uint16_t CKS2       : 1;\r
+} stc_bt_pwm_tmcr_field_t;\r
+\r
+typedef struct stc_bt_pwm_stc_field\r
+{\r
+  __IO  uint8_t UDIR       : 1;\r
+  __IO  uint8_t DTIR       : 1;\r
+  __IO  uint8_t TGIR       : 1;\r
+        uint8_t RESERVED1  : 1;\r
+  __IO  uint8_t UDIE       : 1;\r
+  __IO  uint8_t DTIE       : 1;\r
+  __IO  uint8_t TGIE       : 1;\r
+} stc_bt_pwm_stc_field_t;\r
+\r
+typedef struct stc_bt_pwm_tmcr2_field\r
+{\r
+  __IO  uint8_t CKS3       : 1;\r
+} stc_bt_pwm_tmcr2_field_t;\r
+\r
+/******************************************************************************\r
+ * BT_RT_MODULE\r
+ ******************************************************************************/\r
+/* BT_RT_MODULE register bit fields */\r
+typedef struct stc_bt_rt_tmcr_field\r
+{\r
+  __IO uint16_t STRG       : 1;\r
+  __IO uint16_t CTEN       : 1;\r
+  __IO uint16_t MDSE       : 1;\r
+  __IO uint16_t OSEL       : 1;\r
+  __IO uint16_t FMD0       : 1;\r
+  __IO uint16_t FMD1       : 1;\r
+  __IO uint16_t FMD2       : 1;\r
+  __IO uint16_t T32        : 1;\r
+  __IO uint16_t EGS0       : 1;\r
+  __IO uint16_t EGS1       : 1;\r
+       uint16_t RESERVED1  : 2;\r
+  __IO uint16_t CKS0       : 1;\r
+  __IO uint16_t CKS1       : 1;\r
+  __IO uint16_t CKS2       : 1;\r
+} stc_bt_rt_tmcr_field_t;\r
+\r
+typedef struct stc_bt_rt_stc_field\r
+{\r
+  __IO  uint8_t UDIR       : 1;\r
+        uint8_t RESERVED1  : 1;\r
+  __IO  uint8_t TGIR       : 1;\r
+        uint8_t RESERVED2  : 1;\r
+  __IO  uint8_t UDIE       : 1;\r
+        uint8_t RESERVED3  : 1;\r
+  __IO  uint8_t TGIE       : 1;\r
+} stc_bt_rt_stc_field_t;\r
+\r
+typedef struct stc_bt_rt_tmcr2_field\r
+{\r
+  __IO  uint8_t CKS3       : 1;\r
+} stc_bt_rt_tmcr2_field_t;\r
+\r
+/******************************************************************************\r
+ * BT_PWC_MODULE\r
+ ******************************************************************************/\r
+/* BT_PWC_MODULE register bit fields */\r
+typedef struct stc_bt_pwc_tmcr_field\r
+{\r
+       uint16_t RESERVED1  : 1;\r
+  __IO uint16_t CTEN       : 1;\r
+  __IO uint16_t MDSE       : 1;\r
+       uint16_t RESERVED2  : 1;\r
+  __IO uint16_t FMD0       : 1;\r
+  __IO uint16_t FMD1       : 1;\r
+  __IO uint16_t FMD2       : 1;\r
+  __IO uint16_t T32        : 1;\r
+  __IO uint16_t EGS0       : 1;\r
+  __IO uint16_t EGS1       : 1;\r
+  __IO uint16_t EGS2       : 1;\r
+       uint16_t RESERVED3  : 1;\r
+  __IO uint16_t CKS0       : 1;\r
+  __IO uint16_t CKS1       : 1;\r
+  __IO uint16_t CKS2       : 1;\r
+} stc_bt_pwc_tmcr_field_t;\r
+\r
+typedef struct stc_bt_pwc_stc_field\r
+{\r
+  __IO  uint8_t OVIR       : 1;\r
+        uint8_t RESERVED1  : 1;\r
+  __IO  uint8_t EDIR       : 1;\r
+        uint8_t RESERVED2  : 1;\r
+  __IO  uint8_t OVIE       : 1;\r
+        uint8_t RESERVED3  : 1;\r
+  __IO  uint8_t EDIE       : 1;\r
+  __IO  uint8_t ERR        : 1;\r
+} stc_bt_pwc_stc_field_t;\r
+\r
+typedef struct stc_bt_pwc_tmcr2_field\r
+{\r
+  __IO  uint8_t CKS3       : 1;\r
+} stc_bt_pwc_tmcr2_field_t;\r
+\r
+/******************************************************************************\r
+ * BTIOSEL03_MODULE\r
+ ******************************************************************************/\r
+/* BTIOSEL03_MODULE register bit fields */\r
+typedef struct stc_btiosel03_btsel0123_field\r
+{\r
+  __IO  uint8_t SEL01_0    : 1;\r
+  __IO  uint8_t SEL01_1    : 1;\r
+  __IO  uint8_t SEL01_2    : 1;\r
+  __IO  uint8_t SEL01_3    : 1;\r
+  __IO  uint8_t SEL23_0    : 1;\r
+  __IO  uint8_t SEL23_1    : 1;\r
+  __IO  uint8_t SEL23_2    : 1;\r
+  __IO  uint8_t SEL23_3    : 1;\r
+} stc_btiosel03_btsel0123_field_t;\r
+\r
+/******************************************************************************\r
+ * BTIOSEL47_MODULE\r
+ ******************************************************************************/\r
+/* BTIOSEL47_MODULE register bit fields */\r
+typedef struct stc_btiosel47_btsel4567_field\r
+{\r
+  __IO  uint8_t SEL45_0    : 1;\r
+  __IO  uint8_t SEL45_1    : 1;\r
+  __IO  uint8_t SEL45_2    : 1;\r
+  __IO  uint8_t SEL45_3    : 1;\r
+  __IO  uint8_t SEL67_0    : 1;\r
+  __IO  uint8_t SEL67_1    : 1;\r
+  __IO  uint8_t SEL67_2    : 1;\r
+  __IO  uint8_t SEL67_3    : 1;\r
+} stc_btiosel47_btsel4567_field_t;\r
+\r
+/******************************************************************************\r
+ * SBSSR_MODULE\r
+ ******************************************************************************/\r
+/* SBSSR_MODULE register bit fields */\r
+typedef struct stc_sbssr_btsssr_field\r
+{\r
+  __IO uint16_t SSR0       : 1;\r
+  __IO uint16_t SSR1       : 1;\r
+  __IO uint16_t SSR2       : 1;\r
+  __IO uint16_t SSR3       : 1;\r
+  __IO uint16_t SSR4       : 1;\r
+  __IO uint16_t SSR5       : 1;\r
+  __IO uint16_t SSR6       : 1;\r
+  __IO uint16_t SSR7       : 1;\r
+  __IO uint16_t SSR8       : 1;\r
+  __IO uint16_t SSR9       : 1;\r
+  __IO uint16_t SSR10      : 1;\r
+  __IO uint16_t SSR11      : 1;\r
+  __IO uint16_t SSR12      : 1;\r
+  __IO uint16_t SSR13      : 1;\r
+  __IO uint16_t SSR14      : 1;\r
+  __IO uint16_t SSR15      : 1;\r
+} stc_sbssr_btsssr_field_t;\r
+\r
+/******************************************************************************\r
+ * QPRC_MODULE\r
+ ******************************************************************************/\r
+/* QPRC_MODULE register bit fields */\r
+typedef struct stc_qprc_qicr_field\r
+{\r
+  __IO uint16_t QPCMIE     : 1;\r
+  __IO uint16_t QPCMF      : 1;\r
+  __IO uint16_t QPRCMIE    : 1;\r
+  __IO uint16_t QPRCMF     : 1;\r
+  __IO uint16_t OUZIE      : 1;\r
+  __IO uint16_t UFDF       : 1;\r
+  __IO uint16_t OFDF       : 1;\r
+  __IO uint16_t ZIIF       : 1;\r
+  __IO uint16_t CDCIE      : 1;\r
+  __IO uint16_t CDCF       : 1;\r
+  __IO uint16_t DIRPC      : 1;\r
+  __IO uint16_t DIROU      : 1;\r
+  __IO uint16_t QPCNRCMIE  : 1;\r
+  __IO uint16_t QPCNRCMF   : 1;\r
+} stc_qprc_qicr_field_t;\r
+\r
+typedef struct stc_qprc_qicrl_field\r
+{\r
+  __IO  uint8_t QPCMIE     : 1;\r
+  __IO  uint8_t QPCMF      : 1;\r
+  __IO  uint8_t QPRCMIE    : 1;\r
+  __IO  uint8_t QPRCMF     : 1;\r
+  __IO  uint8_t OUZIE      : 1;\r
+  __IO  uint8_t UFDF       : 1;\r
+  __IO  uint8_t OFDF       : 1;\r
+  __IO  uint8_t ZIIF       : 1;\r
+} stc_qprc_qicrl_field_t;\r
+\r
+typedef struct stc_qprc_qicrh_field\r
+{\r
+  __IO  uint8_t CDCIE      : 1;\r
+  __IO  uint8_t CDCF       : 1;\r
+  __IO  uint8_t DIRPC      : 1;\r
+  __IO  uint8_t DIROU      : 1;\r
+  __IO  uint8_t QPCNRCMIE  : 1;\r
+  __IO  uint8_t QPCNRCMF   : 1;\r
+} stc_qprc_qicrh_field_t;\r
+\r
+typedef struct stc_qprc_qcr_field\r
+{\r
+  __IO uint16_t PCM0       : 1;\r
+  __IO uint16_t PCM1       : 1;\r
+  __IO uint16_t RCM0       : 1;\r
+  __IO uint16_t RCM1       : 1;\r
+  __IO uint16_t PSTP       : 1;\r
+  __IO uint16_t CGSC       : 1;\r
+  __IO uint16_t RSEL       : 1;\r
+  __IO uint16_t SWAP       : 1;\r
+  __IO uint16_t PCRM0      : 1;\r
+  __IO uint16_t PCRM1      : 1;\r
+  __IO uint16_t AES0       : 1;\r
+  __IO uint16_t AES1       : 1;\r
+  __IO uint16_t BES0       : 1;\r
+  __IO uint16_t BES1       : 1;\r
+  __IO uint16_t CGE0       : 1;\r
+  __IO uint16_t CGE1       : 1;\r
+} stc_qprc_qcr_field_t;\r
+\r
+typedef struct stc_qprc_qcrl_field\r
+{\r
+  __IO  uint8_t PCM0       : 1;\r
+  __IO  uint8_t PCM1       : 1;\r
+  __IO  uint8_t RCM0       : 1;\r
+  __IO  uint8_t RCM1       : 1;\r
+  __IO  uint8_t PSTP       : 1;\r
+  __IO  uint8_t CGSC       : 1;\r
+  __IO  uint8_t RSEL       : 1;\r
+  __IO  uint8_t SWAP       : 1;\r
+} stc_qprc_qcrl_field_t;\r
+\r
+typedef struct stc_qprc_qcrh_field\r
+{\r
+  __IO  uint8_t PCRM0      : 1;\r
+  __IO  uint8_t PCRM1      : 1;\r
+  __IO  uint8_t AES0       : 1;\r
+  __IO  uint8_t AES1       : 1;\r
+  __IO  uint8_t BES0       : 1;\r
+  __IO  uint8_t BES1       : 1;\r
+  __IO  uint8_t CGE0       : 1;\r
+  __IO  uint8_t CGE1       : 1;\r
+} stc_qprc_qcrh_field_t;\r
+\r
+typedef struct stc_qprc_qecr_field\r
+{\r
+  __IO uint16_t ORNGMD     : 1;\r
+  __IO uint16_t ORNGF      : 1;\r
+  __IO uint16_t ORNGIE     : 1;\r
+} stc_qprc_qecr_field_t;\r
+\r
+/******************************************************************************\r
+ * ADC12_MODULE\r
+ ******************************************************************************/\r
+/* ADC12_MODULE register bit fields */\r
+typedef struct stc_adc_adsr_field\r
+{\r
+  __IO  uint8_t SCS        : 1;\r
+  __IO  uint8_t PCS        : 1;\r
+  __IO  uint8_t PCNS       : 1;\r
+        uint8_t RESERVED1  : 3;\r
+  __IO  uint8_t FDAS       : 1;\r
+  __IO  uint8_t ADSTP      : 1;\r
+} stc_adc_adsr_field_t;\r
+\r
+typedef struct stc_adc_adcr_field\r
+{\r
+  __IO  uint8_t OVRIE      : 1;\r
+  __IO  uint8_t CMPIE      : 1;\r
+  __IO  uint8_t PCIE       : 1;\r
+  __IO  uint8_t SCIE       : 1;\r
+        uint8_t RESERVED1  : 1;\r
+  __IO  uint8_t CMPIF      : 1;\r
+  __IO  uint8_t PCIF       : 1;\r
+  __IO  uint8_t SCIF       : 1;\r
+} stc_adc_adcr_field_t;\r
+\r
+typedef struct stc_adc_sfns_field\r
+{\r
+  __IO  uint8_t SFS0       : 1;\r
+  __IO  uint8_t SFS1       : 1;\r
+  __IO  uint8_t SFS2       : 1;\r
+  __IO  uint8_t SFS3       : 1;\r
+} stc_adc_sfns_field_t;\r
+\r
+typedef struct stc_adc_sccr_field\r
+{\r
+  __IO  uint8_t SSTR       : 1;\r
+  __IO  uint8_t SHEN       : 1;\r
+  __IO  uint8_t RPT        : 1;\r
+        uint8_t RESERVED1  : 1;\r
+  __IO  uint8_t SFCLR      : 1;\r
+  __IO  uint8_t SOVR       : 1;\r
+  __IO  uint8_t SFUL       : 1;\r
+  __IO  uint8_t SEMP       : 1;\r
+} stc_adc_sccr_field_t;\r
+\r
+typedef struct stc_adc_scfd_field\r
+{\r
+  __IO uint32_t SC0        : 1;\r
+  __IO uint32_t SC1        : 1;\r
+  __IO uint32_t SC2        : 1;\r
+  __IO uint32_t SC3        : 1;\r
+  __IO uint32_t SC4        : 1;\r
+       uint32_t RESERVED1  : 3;\r
+  __IO uint32_t RS0        : 1;\r
+  __IO uint32_t RS1        : 1;\r
+       uint32_t RESERVED2  : 2;\r
+  __IO uint32_t INVL       : 1;\r
+       uint32_t RESERVED3  : 7;\r
+  __IO uint32_t SD0        : 1;\r
+  __IO uint32_t SD1        : 1;\r
+  __IO uint32_t SD2        : 1;\r
+  __IO uint32_t SD3        : 1;\r
+  __IO uint32_t SD4        : 1;\r
+  __IO uint32_t SD5        : 1;\r
+  __IO uint32_t SD6        : 1;\r
+  __IO uint32_t SD7        : 1;\r
+  __IO uint32_t SD8        : 1;\r
+  __IO uint32_t SD9        : 1;\r
+  __IO uint32_t SD10       : 1;\r
+  __IO uint32_t SD11       : 1;\r
+} stc_adc_scfd_field_t;\r
+\r
+typedef struct stc_adc_scfdl_field\r
+{\r
+  __IO uint16_t SC0        : 1;\r
+  __IO uint16_t SC1        : 1;\r
+  __IO uint16_t SC2        : 1;\r
+  __IO uint16_t SC3        : 1;\r
+  __IO uint16_t SC4        : 1;\r
+       uint16_t RESERVED1  : 3;\r
+  __IO uint16_t RS0        : 1;\r
+  __IO uint16_t RS1        : 1;\r
+       uint16_t RESERVED2  : 2;\r
+  __IO uint16_t INVL       : 1;\r
+} stc_adc_scfdl_field_t;\r
+\r
+typedef struct stc_adc_scfdh_field\r
+{\r
+       uint16_t RESERVED1  : 4;\r
+  __IO uint16_t SD0        : 1;\r
+  __IO uint16_t SD1        : 1;\r
+  __IO uint16_t SD2        : 1;\r
+  __IO uint16_t SD3        : 1;\r
+  __IO uint16_t SD4        : 1;\r
+  __IO uint16_t SD5        : 1;\r
+  __IO uint16_t SD6        : 1;\r
+  __IO uint16_t SD7        : 1;\r
+  __IO uint16_t SD8        : 1;\r
+  __IO uint16_t SD9        : 1;\r
+  __IO uint16_t SD10       : 1;\r
+  __IO uint16_t SD11       : 1;\r
+} stc_adc_scfdh_field_t;\r
+\r
+typedef struct stc_adc_scis23_field\r
+{\r
+  __IO uint16_t AN16       : 1;\r
+  __IO uint16_t AN17       : 1;\r
+  __IO uint16_t AN18       : 1;\r
+  __IO uint16_t AN19       : 1;\r
+  __IO uint16_t AN20       : 1;\r
+  __IO uint16_t AN21       : 1;\r
+  __IO uint16_t AN22       : 1;\r
+  __IO uint16_t AN23       : 1;\r
+  __IO uint16_t AN24       : 1;\r
+  __IO uint16_t AN25       : 1;\r
+  __IO uint16_t AN26       : 1;\r
+  __IO uint16_t AN27       : 1;\r
+  __IO uint16_t AN28       : 1;\r
+  __IO uint16_t AN29       : 1;\r
+  __IO uint16_t AN30       : 1;\r
+  __IO uint16_t AN31       : 1;\r
+} stc_adc_scis23_field_t;\r
+\r
+typedef struct stc_adc_scis2_field\r
+{\r
+  __IO  uint8_t AN16       : 1;\r
+  __IO  uint8_t AN17       : 1;\r
+  __IO  uint8_t AN18       : 1;\r
+  __IO  uint8_t AN19       : 1;\r
+  __IO  uint8_t AN20       : 1;\r
+  __IO  uint8_t AN21       : 1;\r
+  __IO  uint8_t AN22       : 1;\r
+  __IO  uint8_t AN23       : 1;\r
+} stc_adc_scis2_field_t;\r
+\r
+typedef struct stc_adc_scis3_field\r
+{\r
+  __IO  uint8_t AN24       : 1;\r
+  __IO  uint8_t AN25       : 1;\r
+  __IO  uint8_t AN26       : 1;\r
+  __IO  uint8_t AN27       : 1;\r
+  __IO  uint8_t AN28       : 1;\r
+  __IO  uint8_t AN29       : 1;\r
+  __IO  uint8_t AN30       : 1;\r
+  __IO  uint8_t AN31       : 1;\r
+} stc_adc_scis3_field_t;\r
+\r
+typedef struct stc_adc_scis01_field\r
+{\r
+  __IO uint16_t AN0        : 1;\r
+  __IO uint16_t AN1        : 1;\r
+  __IO uint16_t AN2        : 1;\r
+  __IO uint16_t AN3        : 1;\r
+  __IO uint16_t AN4        : 1;\r
+  __IO uint16_t AN5        : 1;\r
+  __IO uint16_t AN6        : 1;\r
+  __IO uint16_t AN7        : 1;\r
+  __IO uint16_t AN8        : 1;\r
+  __IO uint16_t AN9        : 1;\r
+  __IO uint16_t AN10       : 1;\r
+  __IO uint16_t AN11       : 1;\r
+  __IO uint16_t AN12       : 1;\r
+  __IO uint16_t AN13       : 1;\r
+  __IO uint16_t AN14       : 1;\r
+  __IO uint16_t AN15       : 1;\r
+} stc_adc_scis01_field_t;\r
+\r
+typedef struct stc_adc_scis0_field\r
+{\r
+  __IO  uint8_t AN0        : 1;\r
+  __IO  uint8_t AN1        : 1;\r
+  __IO  uint8_t AN2        : 1;\r
+  __IO  uint8_t AN3        : 1;\r
+  __IO  uint8_t AN4        : 1;\r
+  __IO  uint8_t AN5        : 1;\r
+  __IO  uint8_t AN6        : 1;\r
+  __IO  uint8_t AN7        : 1;\r
+} stc_adc_scis0_field_t;\r
+\r
+typedef struct stc_adc_scis1_field\r
+{\r
+  __IO  uint8_t AN8        : 1;\r
+  __IO  uint8_t AN9        : 1;\r
+  __IO  uint8_t AN10       : 1;\r
+  __IO  uint8_t AN11       : 1;\r
+  __IO  uint8_t AN12       : 1;\r
+  __IO  uint8_t AN13       : 1;\r
+  __IO  uint8_t AN14       : 1;\r
+  __IO  uint8_t AN15       : 1;\r
+} stc_adc_scis1_field_t;\r
+\r
+typedef struct stc_adc_pfns_field\r
+{\r
+  __IO  uint8_t PFS0       : 1;\r
+  __IO  uint8_t PFS1       : 1;\r
+        uint8_t RESERVED1  : 2;\r
+  __IO  uint8_t TEST0      : 1;\r
+  __IO  uint8_t TEST1      : 1;\r
+} stc_adc_pfns_field_t;\r
+\r
+typedef struct stc_adc_pccr_field\r
+{\r
+  __IO  uint8_t PSTR       : 1;\r
+  __IO  uint8_t PHEN       : 1;\r
+  __IO  uint8_t PEEN       : 1;\r
+  __IO  uint8_t ESCE       : 1;\r
+  __IO  uint8_t PFCLR      : 1;\r
+  __IO  uint8_t POVR       : 1;\r
+  __IO  uint8_t PFUL       : 1;\r
+  __IO  uint8_t PEMP       : 1;\r
+} stc_adc_pccr_field_t;\r
+\r
+typedef struct stc_adc_pcfd_field\r
+{\r
+  __IO uint32_t PC0        : 1;\r
+  __IO uint32_t PC1        : 1;\r
+  __IO uint32_t PC2        : 1;\r
+  __IO uint32_t PC3        : 1;\r
+  __IO uint32_t PC4        : 1;\r
+       uint32_t RESERVED1  : 3;\r
+  __IO uint32_t RS0        : 1;\r
+  __IO uint32_t RS1        : 1;\r
+  __IO uint32_t RS2        : 1;\r
+       uint32_t RESERVED2  : 1;\r
+  __IO uint32_t INVL       : 1;\r
+       uint32_t RESERVED3  : 7;\r
+  __IO uint32_t PD0        : 1;\r
+  __IO uint32_t PD1        : 1;\r
+  __IO uint32_t PD2        : 1;\r
+  __IO uint32_t PD3        : 1;\r
+  __IO uint32_t PD4        : 1;\r
+  __IO uint32_t PD5        : 1;\r
+  __IO uint32_t PD6        : 1;\r
+  __IO uint32_t PD7        : 1;\r
+  __IO uint32_t PD8        : 1;\r
+  __IO uint32_t PD9        : 1;\r
+  __IO uint32_t PD10       : 1;\r
+  __IO uint32_t PD11       : 1;\r
+} stc_adc_pcfd_field_t;\r
+\r
+typedef struct stc_adc_pcfdl_field\r
+{\r
+  __IO uint16_t PC0        : 1;\r
+  __IO uint16_t PC1        : 1;\r
+  __IO uint16_t PC2        : 1;\r
+  __IO uint16_t PC3        : 1;\r
+  __IO uint16_t PC4        : 1;\r
+       uint16_t RESERVED1  : 3;\r
+  __IO uint16_t RS0        : 1;\r
+  __IO uint16_t RS1        : 1;\r
+  __IO uint16_t RS2        : 1;\r
+       uint16_t RESERVED2  : 1;\r
+  __IO uint16_t INVL       : 1;\r
+} stc_adc_pcfdl_field_t;\r
+\r
+typedef struct stc_adc_pcfdh_field\r
+{\r
+       uint16_t RESERVED1  : 4;\r
+  __IO uint16_t PD0        : 1;\r
+  __IO uint16_t PD1        : 1;\r
+  __IO uint16_t PD2        : 1;\r
+  __IO uint16_t PD3        : 1;\r
+  __IO uint16_t PD4        : 1;\r
+  __IO uint16_t PD5        : 1;\r
+  __IO uint16_t PD6        : 1;\r
+  __IO uint16_t PD7        : 1;\r
+  __IO uint16_t PD8        : 1;\r
+  __IO uint16_t PD9        : 1;\r
+  __IO uint16_t PD10       : 1;\r
+  __IO uint16_t PD11       : 1;\r
+} stc_adc_pcfdh_field_t;\r
+\r
+typedef struct stc_adc_pcis_field\r
+{\r
+  __IO  uint8_t P1A0       : 1;\r
+  __IO  uint8_t P1A1       : 1;\r
+  __IO  uint8_t P1A2       : 1;\r
+  __IO  uint8_t P2A0       : 1;\r
+  __IO  uint8_t P2A1       : 1;\r
+  __IO  uint8_t P2A2       : 1;\r
+  __IO  uint8_t P2A3       : 1;\r
+  __IO  uint8_t P2A4       : 1;\r
+} stc_adc_pcis_field_t;\r
+\r
+typedef struct stc_adc_cmpcr_field\r
+{\r
+  __IO  uint8_t CCH0       : 1;\r
+  __IO  uint8_t CCH1       : 1;\r
+  __IO  uint8_t CCH2       : 1;\r
+  __IO  uint8_t CCH3       : 1;\r
+  __IO  uint8_t CCH4       : 1;\r
+  __IO  uint8_t CMD0       : 1;\r
+  __IO  uint8_t CMD1       : 1;\r
+  __IO  uint8_t CMPEN      : 1;\r
+} stc_adc_cmpcr_field_t;\r
+\r
+typedef struct stc_adc_cmpd_field\r
+{\r
+       uint16_t RESERVED1  : 6;\r
+  __IO uint16_t CMAD2      : 1;\r
+  __IO uint16_t CMAD3      : 1;\r
+  __IO uint16_t CMAD4      : 1;\r
+  __IO uint16_t CMAD5      : 1;\r
+  __IO uint16_t CMAD6      : 1;\r
+  __IO uint16_t CMAD7      : 1;\r
+  __IO uint16_t CMAD8      : 1;\r
+  __IO uint16_t CMAD9      : 1;\r
+  __IO uint16_t CMAD10     : 1;\r
+  __IO uint16_t CMAD11     : 1;\r
+} stc_adc_cmpd_field_t;\r
+\r
+typedef struct stc_adc_adss23_field\r
+{\r
+  __IO uint16_t TS16       : 1;\r
+  __IO uint16_t TS17       : 1;\r
+  __IO uint16_t TS18       : 1;\r
+  __IO uint16_t TS19       : 1;\r
+  __IO uint16_t TS20       : 1;\r
+  __IO uint16_t TS21       : 1;\r
+  __IO uint16_t TS22       : 1;\r
+  __IO uint16_t TS23       : 1;\r
+  __IO uint16_t TS24       : 1;\r
+  __IO uint16_t TS25       : 1;\r
+  __IO uint16_t TS26       : 1;\r
+  __IO uint16_t TS27       : 1;\r
+  __IO uint16_t TS28       : 1;\r
+  __IO uint16_t TS29       : 1;\r
+  __IO uint16_t TS30       : 1;\r
+  __IO uint16_t TS31       : 1;\r
+} stc_adc_adss23_field_t;\r
+\r
+typedef struct stc_adc_adss2_field\r
+{\r
+  __IO  uint8_t TS16       : 1;\r
+  __IO  uint8_t TS17       : 1;\r
+  __IO  uint8_t TS18       : 1;\r
+  __IO  uint8_t TS19       : 1;\r
+  __IO  uint8_t TS20       : 1;\r
+  __IO  uint8_t TS21       : 1;\r
+  __IO  uint8_t TS22       : 1;\r
+  __IO  uint8_t TS23       : 1;\r
+} stc_adc_adss2_field_t;\r
+\r
+typedef struct stc_adc_adss3_field\r
+{\r
+  __IO  uint8_t TS24       : 1;\r
+  __IO  uint8_t TS25       : 1;\r
+  __IO  uint8_t TS26       : 1;\r
+  __IO  uint8_t TS27       : 1;\r
+  __IO  uint8_t TS28       : 1;\r
+  __IO  uint8_t TS29       : 1;\r
+  __IO  uint8_t TS30       : 1;\r
+  __IO  uint8_t TS31       : 1;\r
+} stc_adc_adss3_field_t;\r
+\r
+typedef struct stc_adc_adss01_field\r
+{\r
+  __IO uint16_t TS0        : 1;\r
+  __IO uint16_t TS1        : 1;\r
+  __IO uint16_t TS2        : 1;\r
+  __IO uint16_t TS3        : 1;\r
+  __IO uint16_t TS4        : 1;\r
+  __IO uint16_t TS5        : 1;\r
+  __IO uint16_t TS6        : 1;\r
+  __IO uint16_t TS7        : 1;\r
+  __IO uint16_t TS8        : 1;\r
+  __IO uint16_t TS9        : 1;\r
+  __IO uint16_t TS10       : 1;\r
+  __IO uint16_t TS11       : 1;\r
+  __IO uint16_t TS12       : 1;\r
+  __IO uint16_t TS13       : 1;\r
+  __IO uint16_t TS14       : 1;\r
+  __IO uint16_t TS15       : 1;\r
+} stc_adc_adss01_field_t;\r
+\r
+typedef struct stc_adc_adss0_field\r
+{\r
+  __IO  uint8_t TS0        : 1;\r
+  __IO  uint8_t TS1        : 1;\r
+  __IO  uint8_t TS2        : 1;\r
+  __IO  uint8_t TS3        : 1;\r
+  __IO  uint8_t TS4        : 1;\r
+  __IO  uint8_t TS5        : 1;\r
+  __IO  uint8_t TS6        : 1;\r
+  __IO  uint8_t TS7        : 1;\r
+} stc_adc_adss0_field_t;\r
+\r
+typedef struct stc_adc_adss1_field\r
+{\r
+  __IO  uint8_t TS8        : 1;\r
+  __IO  uint8_t TS9        : 1;\r
+  __IO  uint8_t TS10       : 1;\r
+  __IO  uint8_t TS11       : 1;\r
+  __IO  uint8_t TS12       : 1;\r
+  __IO  uint8_t TS13       : 1;\r
+  __IO  uint8_t TS14       : 1;\r
+  __IO  uint8_t TS15       : 1;\r
+} stc_adc_adss1_field_t;\r
+\r
+typedef struct stc_adc_adst01_field\r
+{\r
+  __IO uint16_t ST10       : 1;\r
+  __IO uint16_t ST11       : 1;\r
+  __IO uint16_t ST12       : 1;\r
+  __IO uint16_t ST13       : 1;\r
+  __IO uint16_t ST14       : 1;\r
+  __IO uint16_t STX10      : 1;\r
+  __IO uint16_t STX11      : 1;\r
+  __IO uint16_t STX12      : 1;\r
+  __IO uint16_t ST00       : 1;\r
+  __IO uint16_t ST01       : 1;\r
+  __IO uint16_t ST02       : 1;\r
+  __IO uint16_t ST03       : 1;\r
+  __IO uint16_t ST04       : 1;\r
+  __IO uint16_t STX00      : 1;\r
+  __IO uint16_t STX01      : 1;\r
+  __IO uint16_t STX02      : 1;\r
+} stc_adc_adst01_field_t;\r
+\r
+typedef struct stc_adc_adst1_field\r
+{\r
+  __IO  uint8_t ST10       : 1;\r
+  __IO  uint8_t ST11       : 1;\r
+  __IO  uint8_t ST12       : 1;\r
+  __IO  uint8_t ST13       : 1;\r
+  __IO  uint8_t ST14       : 1;\r
+  __IO  uint8_t STX10      : 1;\r
+  __IO  uint8_t STX11      : 1;\r
+  __IO  uint8_t STX12      : 1;\r
+} stc_adc_adst1_field_t;\r
+\r
+typedef struct stc_adc_adst0_field\r
+{\r
+  __IO  uint8_t ST00       : 1;\r
+  __IO  uint8_t ST01       : 1;\r
+  __IO  uint8_t ST02       : 1;\r
+  __IO  uint8_t ST03       : 1;\r
+  __IO  uint8_t ST04       : 1;\r
+  __IO  uint8_t STX00      : 1;\r
+  __IO  uint8_t STX01      : 1;\r
+  __IO  uint8_t STX02      : 1;\r
+} stc_adc_adst0_field_t;\r
+\r
+typedef struct stc_adc_adct_field\r
+{\r
+  __IO  uint8_t CT0        : 1;\r
+  __IO  uint8_t CT1        : 1;\r
+  __IO  uint8_t CT2        : 1;\r
+  __IO  uint8_t CT3        : 1;\r
+  __IO  uint8_t CT4        : 1;\r
+  __IO  uint8_t CT5        : 1;\r
+  __IO  uint8_t CT6        : 1;\r
+  __IO  uint8_t CT7        : 1;\r
+} stc_adc_adct_field_t;\r
+\r
+typedef struct stc_adc_prtsl_field\r
+{\r
+  __IO  uint8_t PRTSL0     : 1;\r
+  __IO  uint8_t PRTSL1     : 1;\r
+  __IO  uint8_t PRTSL2     : 1;\r
+  __IO  uint8_t PRTSL3     : 1;\r
+} stc_adc_prtsl_field_t;\r
+\r
+typedef struct stc_adc_sctsl_field\r
+{\r
+  __IO  uint8_t SCTSL0     : 1;\r
+  __IO  uint8_t SCTSL1     : 1;\r
+  __IO  uint8_t SCTSL2     : 1;\r
+  __IO  uint8_t SCTSL3     : 1;\r
+} stc_adc_sctsl_field_t;\r
+\r
+typedef struct stc_adc_adcen_field\r
+{\r
+  __IO  uint8_t ENBL       : 1;\r
+  __IO  uint8_t READY      : 1;\r
+        uint8_t RESERVED1  : 2;\r
+  __IO  uint8_t CYCLSL0    : 1;\r
+  __IO  uint8_t CYCLSL1    : 1;\r
+} stc_adc_adcen_field_t;\r
+\r
+/******************************************************************************\r
+ * CRTRIM_MODULE\r
+ ******************************************************************************/\r
+/* CRTRIM_MODULE register bit fields */\r
+typedef struct stc_crtrim_mcr_psr_field\r
+{\r
+  __IO  uint8_t CSR0       : 1;\r
+  __IO  uint8_t CSR1       : 1;\r
+} stc_crtrim_mcr_psr_field_t;\r
+\r
+typedef struct stc_crtrim_mcr_ftrm_field\r
+{\r
+  __IO uint16_t TRD0       : 1;\r
+  __IO uint16_t TRD1       : 1;\r
+  __IO uint16_t TRD2       : 1;\r
+  __IO uint16_t TRD3       : 1;\r
+  __IO uint16_t TRD4       : 1;\r
+  __IO uint16_t TRD5       : 1;\r
+  __IO uint16_t TRD6       : 1;\r
+  __IO uint16_t TRD7       : 1;\r
+} stc_crtrim_mcr_ftrm_field_t;\r
+\r
+/******************************************************************************\r
+ * EXTI_MODULE\r
+ ******************************************************************************/\r
+/* EXTI_MODULE register bit fields */\r
+typedef struct stc_exti_enir_field\r
+{\r
+  __IO uint16_t EN0        : 1;\r
+  __IO uint16_t EN1        : 1;\r
+  __IO uint16_t EN2        : 1;\r
+  __IO uint16_t EN3        : 1;\r
+  __IO uint16_t EN4        : 1;\r
+  __IO uint16_t EN5        : 1;\r
+  __IO uint16_t EN6        : 1;\r
+  __IO uint16_t EN7        : 1;\r
+  __IO uint16_t EN8        : 1;\r
+       uint16_t RESERVED1  : 5;\r
+  __IO uint16_t EN14       : 1;\r
+  __IO uint16_t EN15       : 1;\r
+} stc_exti_enir_field_t;\r
+\r
+typedef struct stc_exti_eirr_field\r
+{\r
+  __IO uint16_t ER0        : 1;\r
+  __IO uint16_t ER1        : 1;\r
+  __IO uint16_t ER2        : 1;\r
+  __IO uint16_t ER3        : 1;\r
+  __IO uint16_t ER4        : 1;\r
+  __IO uint16_t ER5        : 1;\r
+  __IO uint16_t ER6        : 1;\r
+  __IO uint16_t ER7        : 1;\r
+  __IO uint16_t ER8        : 1;\r
+       uint16_t RESERVED1  : 5;\r
+  __IO uint16_t ER14       : 1;\r
+  __IO uint16_t ER15       : 1;\r
+} stc_exti_eirr_field_t;\r
+\r
+typedef struct stc_exti_eicl_field\r
+{\r
+  __IO uint16_t ECL0       : 1;\r
+  __IO uint16_t ECL1       : 1;\r
+  __IO uint16_t ECL2       : 1;\r
+  __IO uint16_t ECL3       : 1;\r
+  __IO uint16_t ECL4       : 1;\r
+  __IO uint16_t ECL5       : 1;\r
+  __IO uint16_t ECL6       : 1;\r
+  __IO uint16_t ECL7       : 1;\r
+  __IO uint16_t ECL8       : 1;\r
+       uint16_t RESERVED1  : 5;\r
+  __IO uint16_t ECL14      : 1;\r
+  __IO uint16_t ECL15      : 1;\r
+} stc_exti_eicl_field_t;\r
+\r
+typedef struct stc_exti_elvr_field\r
+{\r
+  __IO uint32_t LA0        : 1;\r
+  __IO uint32_t LB0        : 1;\r
+  __IO uint32_t LA1        : 1;\r
+  __IO uint32_t LB1        : 1;\r
+  __IO uint32_t LA2        : 1;\r
+  __IO uint32_t LB2        : 1;\r
+  __IO uint32_t LA3        : 1;\r
+  __IO uint32_t LB3        : 1;\r
+  __IO uint32_t LA4        : 1;\r
+  __IO uint32_t LB4        : 1;\r
+  __IO uint32_t LA5        : 1;\r
+  __IO uint32_t LB5        : 1;\r
+  __IO uint32_t LA6        : 1;\r
+  __IO uint32_t LB6        : 1;\r
+  __IO uint32_t LA7        : 1;\r
+  __IO uint32_t LB7        : 1;\r
+  __IO uint32_t LA8        : 1;\r
+  __IO uint32_t LB8        : 1;\r
+       uint32_t RESERVED1  : 10;\r
+  __IO uint32_t LA14       : 1;\r
+  __IO uint32_t LB14       : 1;\r
+  __IO uint32_t LA15       : 1;\r
+  __IO uint32_t LB15       : 1;\r
+} stc_exti_elvr_field_t;\r
+\r
+typedef struct stc_exti_nmirr_field\r
+{\r
+  __IO  uint8_t NR0        : 1;\r
+} stc_exti_nmirr_field_t;\r
+\r
+typedef struct stc_exti_nmicl_field\r
+{\r
+  __IO  uint8_t NCL0       : 1;\r
+} stc_exti_nmicl_field_t;\r
+\r
+/******************************************************************************\r
+ * INTREQ_MODULE\r
+ ******************************************************************************/\r
+/* INTREQ_MODULE register bit fields */\r
+typedef struct stc_intreq_drqsel_field\r
+{\r
+  __IO uint32_t DRQSEL0    : 1;\r
+  __IO uint32_t DRQSEL1    : 1;\r
+  __IO uint32_t DRQSEL2    : 1;\r
+  __IO uint32_t DRQSEL3    : 1;\r
+  __IO uint32_t DRQSEL4    : 1;\r
+  __IO uint32_t DRQSEL5    : 1;\r
+  __IO uint32_t DRQSEL6    : 1;\r
+  __IO uint32_t DRQSEL7    : 1;\r
+  __IO uint32_t DRQSEL8    : 1;\r
+  __IO uint32_t DRQSEL9    : 1;\r
+  __IO uint32_t DRQSEL10   : 1;\r
+  __IO uint32_t DRQSEL11   : 1;\r
+  __IO uint32_t DRQSEL12   : 1;\r
+  __IO uint32_t DRQSEL13   : 1;\r
+  __IO uint32_t DRQSEL14   : 1;\r
+  __IO uint32_t DRQSEL15   : 1;\r
+  __IO uint32_t DRQSEL16   : 1;\r
+  __IO uint32_t DRQSEL17   : 1;\r
+  __IO uint32_t DRQSEL18   : 1;\r
+  __IO uint32_t DRQSEL19   : 1;\r
+  __IO uint32_t DRQSEL20   : 1;\r
+  __IO uint32_t DRQSEL21   : 1;\r
+  __IO uint32_t DRQSEL22   : 1;\r
+  __IO uint32_t DRQSEL23   : 1;\r
+  __IO uint32_t DRQSEL24   : 1;\r
+  __IO uint32_t DRQSEL25   : 1;\r
+  __IO uint32_t DRQSEL26   : 1;\r
+  __IO uint32_t DRQSEL27   : 1;\r
+  __IO uint32_t DRQSEL28   : 1;\r
+  __IO uint32_t DRQSEL29   : 1;\r
+  __IO uint32_t DRQSEL30   : 1;\r
+  __IO uint32_t DRQSEL31   : 1;\r
+} stc_intreq_drqsel_field_t;\r
+\r
+typedef struct stc_intreq_oddpks_field\r
+{\r
+  __IO uint32_t ODDPKS0    : 1;\r
+  __IO uint32_t ODDPKS1    : 1;\r
+  __IO uint32_t ODDPKS2    : 1;\r
+  __IO uint32_t ODDPKS3    : 1;\r
+  __IO uint32_t ODDPKS4    : 1;\r
+} stc_intreq_oddpks_field_t;\r
+\r
+typedef struct stc_intreq_exc02mon_field\r
+{\r
+  __IO uint32_t NMI        : 1;\r
+  __IO uint32_t HWINT      : 1;\r
+} stc_intreq_exc02mon_field_t;\r
+\r
+typedef struct stc_intreq_irq00mon_field\r
+{\r
+  __IO uint32_t FCSINT     : 1;\r
+} stc_intreq_irq00mon_field_t;\r
+\r
+typedef struct stc_intreq_irq01mon_field\r
+{\r
+  __IO uint32_t SWWDTINT   : 1;\r
+} stc_intreq_irq01mon_field_t;\r
+\r
+typedef struct stc_intreq_irq02mon_field\r
+{\r
+  __IO uint32_t LVDINT     : 1;\r
+} stc_intreq_irq02mon_field_t;\r
+\r
+typedef struct stc_intreq_irq03mon_field\r
+{\r
+  __IO uint32_t WAVE0INT0  : 1;\r
+  __IO uint32_t WAVE0INT1  : 1;\r
+  __IO uint32_t WAVE0INT2  : 1;\r
+  __IO uint32_t WAVE0INT3  : 1;\r
+  __IO uint32_t WAVE1INT0  : 1;\r
+  __IO uint32_t WAVE1INT1  : 1;\r
+  __IO uint32_t WAVE1INT2  : 1;\r
+  __IO uint32_t WAVE1INT3  : 1;\r
+} stc_intreq_irq03mon_field_t;\r
+\r
+typedef struct stc_intreq_irq04mon_field\r
+{\r
+  __IO uint32_t EXTINT0    : 1;\r
+  __IO uint32_t EXTINT1    : 1;\r
+  __IO uint32_t EXTINT2    : 1;\r
+  __IO uint32_t EXTINT3    : 1;\r
+  __IO uint32_t EXTINT4    : 1;\r
+  __IO uint32_t EXTINT5    : 1;\r
+  __IO uint32_t EXTINT6    : 1;\r
+} stc_intreq_irq04mon_field_t;\r
+\r
+typedef struct stc_intreq_irq05mon_field\r
+{\r
+       uint32_t RESERVED1  : 7;\r
+  __IO uint32_t EXTINT7    : 1;\r
+} stc_intreq_irq05mon_field_t;\r
+\r
+typedef struct stc_intreq_irq06mon_field\r
+{\r
+  __IO uint32_t TIMINT0    : 1;\r
+  __IO uint32_t TIMINT1    : 1;\r
+  __IO uint32_t QUD0INT0   : 1;\r
+  __IO uint32_t QUD0INT1   : 1;\r
+  __IO uint32_t QUD0INT2   : 1;\r
+  __IO uint32_t QUD0INT3   : 1;\r
+  __IO uint32_t QUD0INT4   : 1;\r
+  __IO uint32_t QUD0INT5   : 1;\r
+  __IO uint32_t QUD1INT0   : 1;\r
+  __IO uint32_t QUD1INT1   : 1;\r
+  __IO uint32_t QUD1INT2   : 1;\r
+  __IO uint32_t QUD1INT3   : 1;\r
+  __IO uint32_t QUD1INT4   : 1;\r
+  __IO uint32_t QUD1INT5   : 1;\r
+} stc_intreq_irq06mon_field_t;\r
+\r
+typedef struct stc_intreq_irq07mon_field\r
+{\r
+  __IO uint32_t FMSINT     : 1;\r
+} stc_intreq_irq07mon_field_t;\r
+\r
+typedef struct stc_intreq_irq08mon_field\r
+{\r
+  __IO uint32_t MFSINT0    : 1;\r
+  __IO uint32_t MFSINT1    : 1;\r
+} stc_intreq_irq08mon_field_t;\r
+\r
+typedef struct stc_intreq_irq09mon_field\r
+{\r
+  __IO uint32_t FMSINT     : 1;\r
+} stc_intreq_irq09mon_field_t;\r
+\r
+typedef struct stc_intreq_irq10mon_field\r
+{\r
+  __IO uint32_t MFSINT0    : 1;\r
+  __IO uint32_t MFSINT1    : 1;\r
+} stc_intreq_irq10mon_field_t;\r
+\r
+typedef struct stc_intreq_irq11mon_field\r
+{\r
+  __IO uint32_t FMSINT     : 1;\r
+} stc_intreq_irq11mon_field_t;\r
+\r
+typedef struct stc_intreq_irq12mon_field\r
+{\r
+  __IO uint32_t MFSINT0    : 1;\r
+  __IO uint32_t MFSINT1    : 1;\r
+} stc_intreq_irq12mon_field_t;\r
+\r
+typedef struct stc_intreq_irq13mon_field\r
+{\r
+  __IO uint32_t FMSINT     : 1;\r
+} stc_intreq_irq13mon_field_t;\r
+\r
+typedef struct stc_intreq_irq14mon_field\r
+{\r
+  __IO uint32_t MFSINT0    : 1;\r
+  __IO uint32_t MFSINT1    : 1;\r
+} stc_intreq_irq14mon_field_t;\r
+\r
+typedef struct stc_intreq_irq15mon_field\r
+{\r
+  __IO uint32_t FMSINT     : 1;\r
+} stc_intreq_irq15mon_field_t;\r
+\r
+typedef struct stc_intreq_irq16mon_field\r
+{\r
+  __IO uint32_t MFSINT0    : 1;\r
+  __IO uint32_t MFSINT1    : 1;\r
+} stc_intreq_irq16mon_field_t;\r
+\r
+typedef struct stc_intreq_irq17mon_field\r
+{\r
+  __IO uint32_t FMSINT     : 1;\r
+} stc_intreq_irq17mon_field_t;\r
+\r
+typedef struct stc_intreq_irq18mon_field\r
+{\r
+  __IO uint32_t MFSINT0    : 1;\r
+  __IO uint32_t MFSINT1    : 1;\r
+} stc_intreq_irq18mon_field_t;\r
+\r
+typedef struct stc_intreq_irq19mon_field\r
+{\r
+  __IO uint32_t FMSINT     : 1;\r
+} stc_intreq_irq19mon_field_t;\r
+\r
+typedef struct stc_intreq_irq20mon_field\r
+{\r
+  __IO uint32_t MFSINT0    : 1;\r
+  __IO uint32_t MFSINT1    : 1;\r
+} stc_intreq_irq20mon_field_t;\r
+\r
+typedef struct stc_intreq_irq21mon_field\r
+{\r
+  __IO uint32_t FMSINT     : 1;\r
+} stc_intreq_irq21mon_field_t;\r
+\r
+typedef struct stc_intreq_irq22mon_field\r
+{\r
+  __IO uint32_t MFSINT0    : 1;\r
+  __IO uint32_t MFSINT1    : 1;\r
+} stc_intreq_irq22mon_field_t;\r
+\r
+typedef struct stc_intreq_irq23mon_field\r
+{\r
+  __IO uint32_t PPGINT0    : 1;\r
+  __IO uint32_t PPGINT1    : 1;\r
+  __IO uint32_t PPGINT2    : 1;\r
+  __IO uint32_t PPGINT3    : 1;\r
+  __IO uint32_t PPGINT4    : 1;\r
+  __IO uint32_t PPGINT5    : 1;\r
+} stc_intreq_irq23mon_field_t;\r
+\r
+typedef struct stc_intreq_irq24mon_field\r
+{\r
+  __IO uint32_t MOSCINT    : 1;\r
+  __IO uint32_t SOSCINT    : 1;\r
+  __IO uint32_t MPLLINT    : 1;\r
+  __IO uint32_t UPLLINT    : 1;\r
+  __IO uint32_t WCINT      : 1;\r
+} stc_intreq_irq24mon_field_t;\r
+\r
+typedef struct stc_intreq_irq25mon_field\r
+{\r
+  __IO uint32_t ADCINT0    : 1;\r
+  __IO uint32_t ADCINT1    : 1;\r
+  __IO uint32_t ADCINT2    : 1;\r
+  __IO uint32_t ADCINT3    : 1;\r
+} stc_intreq_irq25mon_field_t;\r
+\r
+typedef struct stc_intreq_irq26mon_field\r
+{\r
+  __IO uint32_t ADCINT0    : 1;\r
+  __IO uint32_t ADCINT1    : 1;\r
+  __IO uint32_t ADCINT2    : 1;\r
+  __IO uint32_t ADCINT3    : 1;\r
+} stc_intreq_irq26mon_field_t;\r
+\r
+typedef struct stc_intreq_irq28mon_field\r
+{\r
+  __IO uint32_t FRT0INT0   : 1;\r
+  __IO uint32_t FRT0INT1   : 1;\r
+  __IO uint32_t FRT0INT2   : 1;\r
+  __IO uint32_t FRT0INT3   : 1;\r
+  __IO uint32_t FRT0INT4   : 1;\r
+  __IO uint32_t FRT0INT5   : 1;\r
+  __IO uint32_t FRT1INT0   : 1;\r
+  __IO uint32_t FRT1INT1   : 1;\r
+  __IO uint32_t FRT1INT2   : 1;\r
+  __IO uint32_t FRT1INT3   : 1;\r
+  __IO uint32_t FRT1INT4   : 1;\r
+  __IO uint32_t FRT1INT5   : 1;\r
+} stc_intreq_irq28mon_field_t;\r
+\r
+typedef struct stc_intreq_irq29mon_field\r
+{\r
+  __IO uint32_t ICU0INT0   : 1;\r
+  __IO uint32_t ICU0INT1   : 1;\r
+  __IO uint32_t ICU0INT2   : 1;\r
+  __IO uint32_t ICU0INT3   : 1;\r
+  __IO uint32_t ICU1INT0   : 1;\r
+  __IO uint32_t ICU1INT1   : 1;\r
+  __IO uint32_t ICU1INT2   : 1;\r
+  __IO uint32_t ICU1INT3   : 1;\r
+} stc_intreq_irq29mon_field_t;\r
+\r
+typedef struct stc_intreq_irq30mon_field\r
+{\r
+  __IO uint32_t OCU0INT0   : 1;\r
+  __IO uint32_t OCU0INT1   : 1;\r
+  __IO uint32_t OCU0INT2   : 1;\r
+  __IO uint32_t OCU0INT3   : 1;\r
+  __IO uint32_t OCU0INT4   : 1;\r
+  __IO uint32_t OCU0INT5   : 1;\r
+  __IO uint32_t OCU1INT0   : 1;\r
+  __IO uint32_t OCU1INT1   : 1;\r
+  __IO uint32_t OCU1INT2   : 1;\r
+  __IO uint32_t OCU1INT3   : 1;\r
+  __IO uint32_t OCU1INT4   : 1;\r
+  __IO uint32_t OCU1INT5   : 1;\r
+} stc_intreq_irq30mon_field_t;\r
+\r
+typedef struct stc_intreq_irq31mon_field\r
+{\r
+  __IO uint32_t BTINT0     : 1;\r
+  __IO uint32_t BTINT1     : 1;\r
+  __IO uint32_t BTINT2     : 1;\r
+  __IO uint32_t BTINT3     : 1;\r
+  __IO uint32_t BTINT4     : 1;\r
+  __IO uint32_t BTINT5     : 1;\r
+  __IO uint32_t BTINT6     : 1;\r
+  __IO uint32_t BTINT7     : 1;\r
+  __IO uint32_t BTINT8     : 1;\r
+  __IO uint32_t BTINT9     : 1;\r
+  __IO uint32_t BTINT10    : 1;\r
+  __IO uint32_t BTINT11    : 1;\r
+  __IO uint32_t BTINT12    : 1;\r
+  __IO uint32_t BTINT13    : 1;\r
+  __IO uint32_t BTINT14    : 1;\r
+  __IO uint32_t BTINT15    : 1;\r
+} stc_intreq_irq31mon_field_t;\r
+\r
+typedef struct stc_intreq_irq34mon_field\r
+{\r
+  __IO uint32_t USB0INT0   : 1;\r
+  __IO uint32_t USB0INT1   : 1;\r
+  __IO uint32_t USB0INT2   : 1;\r
+  __IO uint32_t USB0INT3   : 1;\r
+  __IO uint32_t USB0INT4   : 1;\r
+} stc_intreq_irq34mon_field_t;\r
+\r
+typedef struct stc_intreq_irq35mon_field\r
+{\r
+  __IO uint32_t USB0INT0   : 1;\r
+  __IO uint32_t USB0INT1   : 1;\r
+  __IO uint32_t USB0INT2   : 1;\r
+  __IO uint32_t USB0INT3   : 1;\r
+  __IO uint32_t USB0INT4   : 1;\r
+  __IO uint32_t USB0INT5   : 1;\r
+} stc_intreq_irq35mon_field_t;\r
+\r
+typedef struct stc_intreq_irq38mon_field\r
+{\r
+  __IO uint32_t DMAINT     : 1;\r
+} stc_intreq_irq38mon_field_t;\r
+\r
+typedef struct stc_intreq_irq39mon_field\r
+{\r
+  __IO uint32_t DMAINT     : 1;\r
+} stc_intreq_irq39mon_field_t;\r
+\r
+typedef struct stc_intreq_irq40mon_field\r
+{\r
+  __IO uint32_t DMAINT     : 1;\r
+} stc_intreq_irq40mon_field_t;\r
+\r
+typedef struct stc_intreq_irq41mon_field\r
+{\r
+  __IO uint32_t DMAINT     : 1;\r
+} stc_intreq_irq41mon_field_t;\r
+\r
+typedef struct stc_intreq_irq42mon_field\r
+{\r
+  __IO uint32_t DMAINT     : 1;\r
+} stc_intreq_irq42mon_field_t;\r
+\r
+typedef struct stc_intreq_irq43mon_field\r
+{\r
+  __IO uint32_t DMAINT     : 1;\r
+} stc_intreq_irq43mon_field_t;\r
+\r
+typedef struct stc_intreq_irq44mon_field\r
+{\r
+  __IO uint32_t DMAINT     : 1;\r
+} stc_intreq_irq44mon_field_t;\r
+\r
+typedef struct stc_intreq_irq45mon_field\r
+{\r
+  __IO uint32_t DMAINT     : 1;\r
+} stc_intreq_irq45mon_field_t;\r
+\r
+/******************************************************************************\r
+ * GPIO_MODULE\r
+ ******************************************************************************/\r
+/* GPIO_MODULE register bit fields */\r
+typedef struct stc_gpio_pfr0_field\r
+{\r
+  __IO uint32_t P0         : 1;\r
+  __IO uint32_t P1         : 1;\r
+  __IO uint32_t P2         : 1;\r
+  __IO uint32_t P3         : 1;\r
+  __IO uint32_t P4         : 1;\r
+       uint32_t RESERVED1  : 5;\r
+  __IO uint32_t PA         : 1;\r
+  __IO uint32_t PB         : 1;\r
+  __IO uint32_t PC         : 1;\r
+       uint32_t RESERVED2  : 2;\r
+  __IO uint32_t PF         : 1;\r
+} stc_gpio_pfr0_field_t;\r
+\r
+typedef struct stc_gpio_pfr1_field\r
+{\r
+  __IO uint32_t P0         : 1;\r
+  __IO uint32_t P1         : 1;\r
+  __IO uint32_t P2         : 1;\r
+  __IO uint32_t P3         : 1;\r
+  __IO uint32_t P4         : 1;\r
+  __IO uint32_t P5         : 1;\r
+       uint32_t RESERVED1  : 1;\r
+  __IO uint32_t P7         : 1;\r
+  __IO uint32_t P8         : 1;\r
+  __IO uint32_t P9         : 1;\r
+} stc_gpio_pfr1_field_t;\r
+\r
+typedef struct stc_gpio_pfr2_field\r
+{\r
+       uint32_t RESERVED1  : 1;\r
+  __IO uint32_t P1         : 1;\r
+  __IO uint32_t P2         : 1;\r
+  __IO uint32_t P3         : 1;\r
+} stc_gpio_pfr2_field_t;\r
+\r
+typedef struct stc_gpio_pfr3_field\r
+{\r
+  __IO uint32_t P0         : 1;\r
+  __IO uint32_t P1         : 1;\r
+  __IO uint32_t P2         : 1;\r
+  __IO uint32_t P3         : 1;\r
+       uint32_t RESERVED1  : 5;\r
+  __IO uint32_t P9         : 1;\r
+  __IO uint32_t PA         : 1;\r
+  __IO uint32_t PB         : 1;\r
+  __IO uint32_t PC         : 1;\r
+  __IO uint32_t PD         : 1;\r
+  __IO uint32_t PE         : 1;\r
+  __IO uint32_t PF         : 1;\r
+} stc_gpio_pfr3_field_t;\r
+\r
+typedef struct stc_gpio_pfr4_field\r
+{\r
+       uint32_t RESERVED1  : 6;\r
+  __IO uint32_t P6         : 1;\r
+  __IO uint32_t P7         : 1;\r
+       uint32_t RESERVED2  : 1;\r
+  __IO uint32_t P9         : 1;\r
+  __IO uint32_t PA         : 1;\r
+  __IO uint32_t PB         : 1;\r
+  __IO uint32_t PC         : 1;\r
+  __IO uint32_t PD         : 1;\r
+  __IO uint32_t PE         : 1;\r
+} stc_gpio_pfr4_field_t;\r
+\r
+typedef struct stc_gpio_pfr5_field\r
+{\r
+  __IO uint32_t P0         : 1;\r
+  __IO uint32_t P1         : 1;\r
+  __IO uint32_t P2         : 1;\r
+} stc_gpio_pfr5_field_t;\r
+\r
+typedef struct stc_gpio_pfr6_field\r
+{\r
+  __IO uint32_t P0         : 1;\r
+  __IO uint32_t P1         : 1;\r
+  __IO uint32_t P2         : 1;\r
+} stc_gpio_pfr6_field_t;\r
+\r
+typedef struct stc_gpio_pfr8_field\r
+{\r
+  __IO uint32_t P0         : 1;\r
+  __IO uint32_t P1         : 1;\r
+} stc_gpio_pfr8_field_t;\r
+\r
+typedef struct stc_gpio_pfre_field\r
+{\r
+  __IO uint32_t P0         : 1;\r
+       uint32_t RESERVED1  : 1;\r
+  __IO uint32_t P2         : 1;\r
+  __IO uint32_t P3         : 1;\r
+} stc_gpio_pfre_field_t;\r
+\r
+typedef struct stc_gpio_pcr0_field\r
+{\r
+  __IO uint32_t P0         : 1;\r
+  __IO uint32_t P1         : 1;\r
+  __IO uint32_t P2         : 1;\r
+  __IO uint32_t P3         : 1;\r
+  __IO uint32_t P4         : 1;\r
+       uint32_t RESERVED1  : 5;\r
+  __IO uint32_t PA         : 1;\r
+  __IO uint32_t PB         : 1;\r
+  __IO uint32_t PC         : 1;\r
+       uint32_t RESERVED2  : 2;\r
+  __IO uint32_t PF         : 1;\r
+} stc_gpio_pcr0_field_t;\r
+\r
+typedef struct stc_gpio_pcr1_field\r
+{\r
+  __IO uint32_t P0         : 1;\r
+  __IO uint32_t P1         : 1;\r
+  __IO uint32_t P2         : 1;\r
+  __IO uint32_t P3         : 1;\r
+  __IO uint32_t P4         : 1;\r
+  __IO uint32_t P5         : 1;\r
+       uint32_t RESERVED1  : 1;\r
+  __IO uint32_t P7         : 1;\r
+  __IO uint32_t P8         : 1;\r
+  __IO uint32_t P9         : 1;\r
+} stc_gpio_pcr1_field_t;\r
+\r
+typedef struct stc_gpio_pcr2_field\r
+{\r
+       uint32_t RESERVED1  : 1;\r
+  __IO uint32_t P1         : 1;\r
+  __IO uint32_t P2         : 1;\r
+  __IO uint32_t P3         : 1;\r
+} stc_gpio_pcr2_field_t;\r
+\r
+typedef struct stc_gpio_pcr3_field\r
+{\r
+  __IO uint32_t P0         : 1;\r
+  __IO uint32_t P1         : 1;\r
+  __IO uint32_t P2         : 1;\r
+  __IO uint32_t P3         : 1;\r
+       uint32_t RESERVED1  : 5;\r
+  __IO uint32_t P9         : 1;\r
+  __IO uint32_t PA         : 1;\r
+  __IO uint32_t PB         : 1;\r
+  __IO uint32_t PC         : 1;\r
+  __IO uint32_t PD         : 1;\r
+  __IO uint32_t PE         : 1;\r
+  __IO uint32_t PF         : 1;\r
+} stc_gpio_pcr3_field_t;\r
+\r
+typedef struct stc_gpio_pcr4_field\r
+{\r
+       uint32_t RESERVED1  : 6;\r
+  __IO uint32_t P6         : 1;\r
+  __IO uint32_t P7         : 1;\r
+       uint32_t RESERVED2  : 1;\r
+  __IO uint32_t P9         : 1;\r
+  __IO uint32_t PA         : 1;\r
+  __IO uint32_t PB         : 1;\r
+  __IO uint32_t PC         : 1;\r
+  __IO uint32_t PD         : 1;\r
+  __IO uint32_t PE         : 1;\r
+} stc_gpio_pcr4_field_t;\r
+\r
+typedef struct stc_gpio_pcr5_field\r
+{\r
+  __IO uint32_t P0         : 1;\r
+  __IO uint32_t P1         : 1;\r
+  __IO uint32_t P2         : 1;\r
+} stc_gpio_pcr5_field_t;\r
+\r
+typedef struct stc_gpio_pcr6_field\r
+{\r
+  __IO uint32_t P0         : 1;\r
+  __IO uint32_t P1         : 1;\r
+  __IO uint32_t P2         : 1;\r
+} stc_gpio_pcr6_field_t;\r
+\r
+typedef struct stc_gpio_pcre_field\r
+{\r
+  __IO uint32_t P0         : 1;\r
+       uint32_t RESERVED1  : 1;\r
+  __IO uint32_t P2         : 1;\r
+  __IO uint32_t P3         : 1;\r
+} stc_gpio_pcre_field_t;\r
+\r
+typedef struct stc_gpio_ddr0_field\r
+{\r
+  __IO uint32_t P0         : 1;\r
+  __IO uint32_t P1         : 1;\r
+  __IO uint32_t P2         : 1;\r
+  __IO uint32_t P3         : 1;\r
+  __IO uint32_t P4         : 1;\r
+       uint32_t RESERVED1  : 5;\r
+  __IO uint32_t PA         : 1;\r
+  __IO uint32_t PB         : 1;\r
+  __IO uint32_t PC         : 1;\r
+       uint32_t RESERVED2  : 2;\r
+  __IO uint32_t PF         : 1;\r
+} stc_gpio_ddr0_field_t;\r
+\r
+typedef struct stc_gpio_ddr1_field\r
+{\r
+  __IO uint32_t P0         : 1;\r
+  __IO uint32_t P1         : 1;\r
+  __IO uint32_t P2         : 1;\r
+  __IO uint32_t P3         : 1;\r
+  __IO uint32_t P4         : 1;\r
+  __IO uint32_t P5         : 1;\r
+       uint32_t RESERVED1  : 1;\r
+  __IO uint32_t P7         : 1;\r
+  __IO uint32_t P8         : 1;\r
+  __IO uint32_t P9         : 1;\r
+} stc_gpio_ddr1_field_t;\r
+\r
+typedef struct stc_gpio_ddr2_field\r
+{\r
+       uint32_t RESERVED1  : 1;\r
+  __IO uint32_t P1         : 1;\r
+  __IO uint32_t P2         : 1;\r
+  __IO uint32_t P3         : 1;\r
+} stc_gpio_ddr2_field_t;\r
+\r
+typedef struct stc_gpio_ddr3_field\r
+{\r
+  __IO uint32_t P0         : 1;\r
+  __IO uint32_t P1         : 1;\r
+  __IO uint32_t P2         : 1;\r
+  __IO uint32_t P3         : 1;\r
+       uint32_t RESERVED1  : 5;\r
+  __IO uint32_t P9         : 1;\r
+  __IO uint32_t PA         : 1;\r
+  __IO uint32_t PB         : 1;\r
+  __IO uint32_t PC         : 1;\r
+  __IO uint32_t PD         : 1;\r
+  __IO uint32_t PE         : 1;\r
+  __IO uint32_t PF         : 1;\r
+} stc_gpio_ddr3_field_t;\r
+\r
+typedef struct stc_gpio_ddr4_field\r
+{\r
+       uint32_t RESERVED1  : 6;\r
+  __IO uint32_t P6         : 1;\r
+  __IO uint32_t P7         : 1;\r
+       uint32_t RESERVED2  : 1;\r
+  __IO uint32_t P9         : 1;\r
+  __IO uint32_t PA         : 1;\r
+  __IO uint32_t PB         : 1;\r
+  __IO uint32_t PC         : 1;\r
+  __IO uint32_t PD         : 1;\r
+  __IO uint32_t PE         : 1;\r
+} stc_gpio_ddr4_field_t;\r
+\r
+typedef struct stc_gpio_ddr5_field\r
+{\r
+  __IO uint32_t P0         : 1;\r
+  __IO uint32_t P1         : 1;\r
+  __IO uint32_t P2         : 1;\r
+} stc_gpio_ddr5_field_t;\r
+\r
+typedef struct stc_gpio_ddr6_field\r
+{\r
+  __IO uint32_t P0         : 1;\r
+  __IO uint32_t P1         : 1;\r
+  __IO uint32_t P2         : 1;\r
+} stc_gpio_ddr6_field_t;\r
+\r
+typedef struct stc_gpio_ddr8_field\r
+{\r
+  __IO uint32_t P0         : 1;\r
+  __IO uint32_t P1         : 1;\r
+} stc_gpio_ddr8_field_t;\r
+\r
+typedef struct stc_gpio_ddre_field\r
+{\r
+  __IO uint32_t P0         : 1;\r
+       uint32_t RESERVED1  : 1;\r
+  __IO uint32_t P2         : 1;\r
+  __IO uint32_t P3         : 1;\r
+} stc_gpio_ddre_field_t;\r
+\r
+typedef struct stc_gpio_pdir0_field\r
+{\r
+  __IO uint32_t P0         : 1;\r
+  __IO uint32_t P1         : 1;\r
+  __IO uint32_t P2         : 1;\r
+  __IO uint32_t P3         : 1;\r
+  __IO uint32_t P4         : 1;\r
+       uint32_t RESERVED1  : 5;\r
+  __IO uint32_t PA         : 1;\r
+  __IO uint32_t PB         : 1;\r
+  __IO uint32_t PC         : 1;\r
+       uint32_t RESERVED2  : 2;\r
+  __IO uint32_t PF         : 1;\r
+} stc_gpio_pdir0_field_t;\r
+\r
+typedef struct stc_gpio_pdir1_field\r
+{\r
+  __IO uint32_t P0         : 1;\r
+  __IO uint32_t P1         : 1;\r
+  __IO uint32_t P2         : 1;\r
+  __IO uint32_t P3         : 1;\r
+  __IO uint32_t P4         : 1;\r
+  __IO uint32_t P5         : 1;\r
+       uint32_t RESERVED1  : 1;\r
+  __IO uint32_t P7         : 1;\r
+  __IO uint32_t P8         : 1;\r
+  __IO uint32_t P9         : 1;\r
+} stc_gpio_pdir1_field_t;\r
+\r
+typedef struct stc_gpio_pdir2_field\r
+{\r
+       uint32_t RESERVED1  : 1;\r
+  __IO uint32_t P1         : 1;\r
+  __IO uint32_t P2         : 1;\r
+  __IO uint32_t P3         : 1;\r
+} stc_gpio_pdir2_field_t;\r
+\r
+typedef struct stc_gpio_pdir3_field\r
+{\r
+  __IO uint32_t P0         : 1;\r
+  __IO uint32_t P1         : 1;\r
+  __IO uint32_t P2         : 1;\r
+  __IO uint32_t P3         : 1;\r
+       uint32_t RESERVED1  : 5;\r
+  __IO uint32_t P9         : 1;\r
+  __IO uint32_t PA         : 1;\r
+  __IO uint32_t PB         : 1;\r
+  __IO uint32_t PC         : 1;\r
+  __IO uint32_t PD         : 1;\r
+  __IO uint32_t PE         : 1;\r
+  __IO uint32_t PF         : 1;\r
+} stc_gpio_pdir3_field_t;\r
+\r
+typedef struct stc_gpio_pdir4_field\r
+{\r
+       uint32_t RESERVED1  : 6;\r
+  __IO uint32_t P6         : 1;\r
+  __IO uint32_t P7         : 1;\r
+       uint32_t RESERVED2  : 1;\r
+  __IO uint32_t P9         : 1;\r
+  __IO uint32_t PA         : 1;\r
+  __IO uint32_t PB         : 1;\r
+  __IO uint32_t PC         : 1;\r
+  __IO uint32_t PD         : 1;\r
+  __IO uint32_t PE         : 1;\r
+} stc_gpio_pdir4_field_t;\r
+\r
+typedef struct stc_gpio_pdir5_field\r
+{\r
+  __IO uint32_t P0         : 1;\r
+  __IO uint32_t P1         : 1;\r
+  __IO uint32_t P2         : 1;\r
+} stc_gpio_pdir5_field_t;\r
+\r
+typedef struct stc_gpio_pdir6_field\r
+{\r
+  __IO uint32_t P0         : 1;\r
+  __IO uint32_t P1         : 1;\r
+  __IO uint32_t P2         : 1;\r
+} stc_gpio_pdir6_field_t;\r
+\r
+typedef struct stc_gpio_pdir8_field\r
+{\r
+  __IO uint32_t P0         : 1;\r
+  __IO uint32_t P1         : 1;\r
+} stc_gpio_pdir8_field_t;\r
+\r
+typedef struct stc_gpio_pdire_field\r
+{\r
+  __IO uint32_t P0         : 1;\r
+       uint32_t RESERVED1  : 1;\r
+  __IO uint32_t P2         : 1;\r
+  __IO uint32_t P3         : 1;\r
+} stc_gpio_pdire_field_t;\r
+\r
+typedef struct stc_gpio_pdor0_field\r
+{\r
+  __IO uint32_t P0         : 1;\r
+  __IO uint32_t P1         : 1;\r
+  __IO uint32_t P2         : 1;\r
+  __IO uint32_t P3         : 1;\r
+  __IO uint32_t P4         : 1;\r
+       uint32_t RESERVED1  : 5;\r
+  __IO uint32_t PA         : 1;\r
+  __IO uint32_t PB         : 1;\r
+  __IO uint32_t PC         : 1;\r
+       uint32_t RESERVED2  : 2;\r
+  __IO uint32_t PF         : 1;\r
+} stc_gpio_pdor0_field_t;\r
+\r
+typedef struct stc_gpio_pdor1_field\r
+{\r
+  __IO uint32_t P0         : 1;\r
+  __IO uint32_t P1         : 1;\r
+  __IO uint32_t P2         : 1;\r
+  __IO uint32_t P3         : 1;\r
+  __IO uint32_t P4         : 1;\r
+  __IO uint32_t P5         : 1;\r
+       uint32_t RESERVED1  : 1;\r
+  __IO uint32_t P7         : 1;\r
+  __IO uint32_t P8         : 1;\r
+  __IO uint32_t P9         : 1;\r
+} stc_gpio_pdor1_field_t;\r
+\r
+typedef struct stc_gpio_pdor2_field\r
+{\r
+       uint32_t RESERVED1  : 1;\r
+  __IO uint32_t P1         : 1;\r
+  __IO uint32_t P2         : 1;\r
+  __IO uint32_t P3         : 1;\r
+} stc_gpio_pdor2_field_t;\r
+\r
+typedef struct stc_gpio_pdor3_field\r
+{\r
+  __IO uint32_t P0         : 1;\r
+  __IO uint32_t P1         : 1;\r
+  __IO uint32_t P2         : 1;\r
+  __IO uint32_t P3         : 1;\r
+       uint32_t RESERVED1  : 5;\r
+  __IO uint32_t P9         : 1;\r
+  __IO uint32_t PA         : 1;\r
+  __IO uint32_t PB         : 1;\r
+  __IO uint32_t PC         : 1;\r
+  __IO uint32_t PD         : 1;\r
+  __IO uint32_t PE         : 1;\r
+  __IO uint32_t PF         : 1;\r
+} stc_gpio_pdor3_field_t;\r
+\r
+typedef struct stc_gpio_pdor4_field\r
+{\r
+       uint32_t RESERVED1  : 6;\r
+  __IO uint32_t P6         : 1;\r
+  __IO uint32_t P7         : 1;\r
+       uint32_t RESERVED2  : 1;\r
+  __IO uint32_t P9         : 1;\r
+  __IO uint32_t PA         : 1;\r
+  __IO uint32_t PB         : 1;\r
+  __IO uint32_t PC         : 1;\r
+  __IO uint32_t PD         : 1;\r
+  __IO uint32_t PE         : 1;\r
+} stc_gpio_pdor4_field_t;\r
+\r
+typedef struct stc_gpio_pdor5_field\r
+{\r
+  __IO uint32_t P0         : 1;\r
+  __IO uint32_t P1         : 1;\r
+  __IO uint32_t P2         : 1;\r
+} stc_gpio_pdor5_field_t;\r
+\r
+typedef struct stc_gpio_pdor6_field\r
+{\r
+  __IO uint32_t P0         : 1;\r
+  __IO uint32_t P1         : 1;\r
+  __IO uint32_t P2         : 1;\r
+} stc_gpio_pdor6_field_t;\r
+\r
+typedef struct stc_gpio_pdor8_field\r
+{\r
+  __IO uint32_t P0         : 1;\r
+  __IO uint32_t P1         : 1;\r
+} stc_gpio_pdor8_field_t;\r
+\r
+typedef struct stc_gpio_pdore_field\r
+{\r
+  __IO uint32_t P0         : 1;\r
+       uint32_t RESERVED1  : 1;\r
+  __IO uint32_t P2         : 1;\r
+  __IO uint32_t P3         : 1;\r
+} stc_gpio_pdore_field_t;\r
+\r
+typedef struct stc_gpio_ade_field\r
+{\r
+  __IO uint32_t AN0        : 1;\r
+  __IO uint32_t AN1        : 1;\r
+  __IO uint32_t AN2        : 1;\r
+  __IO uint32_t AN3        : 1;\r
+  __IO uint32_t AN4        : 1;\r
+  __IO uint32_t AN5        : 1;\r
+       uint32_t RESERVED1  : 1;\r
+  __IO uint32_t AN7        : 1;\r
+  __IO uint32_t AN8        : 1;\r
+  __IO uint32_t AN9        : 1;\r
+} stc_gpio_ade_field_t;\r
+\r
+typedef struct stc_gpio_spsr_field\r
+{\r
+  __IO uint32_t SUBXC      : 1;\r
+       uint32_t RESERVED1  : 1;\r
+  __IO uint32_t MAINXC     : 1;\r
+       uint32_t RESERVED2  : 1;\r
+  __IO uint32_t USB0C      : 1;\r
+} stc_gpio_spsr_field_t;\r
+\r
+typedef struct stc_gpio_epfr00_field\r
+{\r
+  __IO uint32_t NMIS       : 1;\r
+  __IO uint32_t CROUTE0    : 1;\r
+  __IO uint32_t CROUTE1    : 1;\r
+       uint32_t RESERVED1  : 6;\r
+  __IO uint32_t USB0PE     : 1;\r
+       uint32_t RESERVED2  : 6;\r
+  __IO uint32_t JTAGEN0B   : 1;\r
+  __IO uint32_t JTAGEN1S   : 1;\r
+} stc_gpio_epfr00_field_t;\r
+\r
+typedef struct stc_gpio_epfr01_field\r
+{\r
+  __IO uint32_t RTO00E0    : 1;\r
+  __IO uint32_t RTO00E1    : 1;\r
+  __IO uint32_t RTO01E0    : 1;\r
+  __IO uint32_t RTO01E1    : 1;\r
+  __IO uint32_t RTO02E0    : 1;\r
+  __IO uint32_t RTO02E1    : 1;\r
+  __IO uint32_t RTO03E0    : 1;\r
+  __IO uint32_t RTO03E1    : 1;\r
+  __IO uint32_t RTO04E0    : 1;\r
+  __IO uint32_t RTO04E1    : 1;\r
+  __IO uint32_t RTO05E0    : 1;\r
+  __IO uint32_t RTO05E1    : 1;\r
+  __IO uint32_t DTTI0C     : 1;\r
+       uint32_t RESERVED1  : 3;\r
+  __IO uint32_t DTTI0S0    : 1;\r
+  __IO uint32_t DTTI0S1    : 1;\r
+  __IO uint32_t FRCK0S0    : 1;\r
+  __IO uint32_t FRCK0S1    : 1;\r
+  __IO uint32_t IC00S0     : 1;\r
+  __IO uint32_t IC00S1     : 1;\r
+  __IO uint32_t IC00S2     : 1;\r
+  __IO uint32_t IC01S0     : 1;\r
+  __IO uint32_t IC01S1     : 1;\r
+  __IO uint32_t IC01S2     : 1;\r
+  __IO uint32_t IC02S0     : 1;\r
+  __IO uint32_t IC02S1     : 1;\r
+  __IO uint32_t IC02S2     : 1;\r
+  __IO uint32_t IC03S0     : 1;\r
+  __IO uint32_t IC03S1     : 1;\r
+  __IO uint32_t IC03S2     : 1;\r
+} stc_gpio_epfr01_field_t;\r
+\r
+typedef struct stc_gpio_epfr04_field\r
+{\r
+       uint32_t RESERVED1  : 2;\r
+  __IO uint32_t TIOA0E0    : 1;\r
+  __IO uint32_t TIOA0E1    : 1;\r
+  __IO uint32_t TIOB0S0    : 1;\r
+  __IO uint32_t TIOB0S1    : 1;\r
+       uint32_t RESERVED2  : 2;\r
+  __IO uint32_t TIOA1S0    : 1;\r
+  __IO uint32_t TIOA1S1    : 1;\r
+  __IO uint32_t TIOA1E0    : 1;\r
+  __IO uint32_t TIOA1E1    : 1;\r
+  __IO uint32_t TIOB1S0    : 1;\r
+  __IO uint32_t TIOB1S1    : 1;\r
+       uint32_t RESERVED3  : 4;\r
+  __IO uint32_t TIOA2E0    : 1;\r
+  __IO uint32_t TIOA2E1    : 1;\r
+  __IO uint32_t TIOB2S0    : 1;\r
+  __IO uint32_t TIOB2S1    : 1;\r
+       uint32_t RESERVED4  : 2;\r
+  __IO uint32_t TIOA3S0    : 1;\r
+  __IO uint32_t TIOA3S1    : 1;\r
+  __IO uint32_t TIOA3E0    : 1;\r
+  __IO uint32_t TIOA3E1    : 1;\r
+  __IO uint32_t TIOB3S0    : 1;\r
+  __IO uint32_t TIOB3S1    : 1;\r
+} stc_gpio_epfr04_field_t;\r
+\r
+typedef struct stc_gpio_epfr05_field\r
+{\r
+       uint32_t RESERVED1  : 2;\r
+  __IO uint32_t TIOA4E0    : 1;\r
+  __IO uint32_t TIOA4E1    : 1;\r
+  __IO uint32_t TIOB4S0    : 1;\r
+  __IO uint32_t TIOB4S1    : 1;\r
+       uint32_t RESERVED2  : 2;\r
+  __IO uint32_t TIOA5S0    : 1;\r
+  __IO uint32_t TIOA5S1    : 1;\r
+  __IO uint32_t TIOA5E0    : 1;\r
+  __IO uint32_t TIOA5E1    : 1;\r
+  __IO uint32_t TIOB5S0    : 1;\r
+  __IO uint32_t TIOB5S1    : 1;\r
+       uint32_t RESERVED3  : 4;\r
+  __IO uint32_t TIOA6E0    : 1;\r
+  __IO uint32_t TIOA6E1    : 1;\r
+  __IO uint32_t TIOB6S0    : 1;\r
+  __IO uint32_t TIOB6S1    : 1;\r
+       uint32_t RESERVED4  : 2;\r
+  __IO uint32_t TIOA7S0    : 1;\r
+  __IO uint32_t TIOA7S1    : 1;\r
+  __IO uint32_t TIOA7E0    : 1;\r
+  __IO uint32_t TIOA7E1    : 1;\r
+  __IO uint32_t TIOB7S0    : 1;\r
+  __IO uint32_t TIOB7S1    : 1;\r
+} stc_gpio_epfr05_field_t;\r
+\r
+typedef struct stc_gpio_epfr06_field\r
+{\r
+  __IO uint32_t EINT00S0   : 1;\r
+  __IO uint32_t EINT00S1   : 1;\r
+  __IO uint32_t EINT01S0   : 1;\r
+  __IO uint32_t EINT01S1   : 1;\r
+  __IO uint32_t EINT02S0   : 1;\r
+  __IO uint32_t EINT02S1   : 1;\r
+  __IO uint32_t EINT03S0   : 1;\r
+  __IO uint32_t EINT03S1   : 1;\r
+  __IO uint32_t EINT04S0   : 1;\r
+  __IO uint32_t EINT04S1   : 1;\r
+  __IO uint32_t EINT05S0   : 1;\r
+  __IO uint32_t EINT05S1   : 1;\r
+  __IO uint32_t EINT06S0   : 1;\r
+  __IO uint32_t EINT06S1   : 1;\r
+       uint32_t RESERVED1  : 16;\r
+  __IO uint32_t EINT15S0   : 1;\r
+  __IO uint32_t EINT15S1   : 1;\r
+} stc_gpio_epfr06_field_t;\r
+\r
+typedef struct stc_gpio_epfr07_field\r
+{\r
+       uint32_t RESERVED1  : 4;\r
+  __IO uint32_t SIN0S0     : 1;\r
+  __IO uint32_t SIN0S1     : 1;\r
+  __IO uint32_t SOT0B0     : 1;\r
+  __IO uint32_t SOT0B1     : 1;\r
+  __IO uint32_t SCK0B0     : 1;\r
+  __IO uint32_t SCK0B1     : 1;\r
+  __IO uint32_t SIN1S0     : 1;\r
+  __IO uint32_t SIN1S1     : 1;\r
+  __IO uint32_t SOT1B0     : 1;\r
+  __IO uint32_t SOT1B1     : 1;\r
+  __IO uint32_t SCK1B0     : 1;\r
+  __IO uint32_t SCK1B1     : 1;\r
+  __IO uint32_t SIN2S0     : 1;\r
+  __IO uint32_t SIN2S1     : 1;\r
+  __IO uint32_t SOT2B0     : 1;\r
+  __IO uint32_t SOT2B1     : 1;\r
+  __IO uint32_t SCK2B0     : 1;\r
+  __IO uint32_t SCK2B1     : 1;\r
+  __IO uint32_t SIN3S0     : 1;\r
+  __IO uint32_t SIN3S1     : 1;\r
+  __IO uint32_t SOT3B0     : 1;\r
+  __IO uint32_t SOT3B1     : 1;\r
+  __IO uint32_t SCK3B0     : 1;\r
+  __IO uint32_t SCK3B1     : 1;\r
+} stc_gpio_epfr07_field_t;\r
+\r
+typedef struct stc_gpio_epfr08_field\r
+{\r
+       uint32_t RESERVED1  : 4;\r
+  __IO uint32_t SIN4S0     : 1;\r
+  __IO uint32_t SIN4S1     : 1;\r
+  __IO uint32_t SOT4B0     : 1;\r
+  __IO uint32_t SOT4B1     : 1;\r
+  __IO uint32_t SCK4B0     : 1;\r
+  __IO uint32_t SCK4B1     : 1;\r
+  __IO uint32_t SIN5S0     : 1;\r
+  __IO uint32_t SIN5S1     : 1;\r
+  __IO uint32_t SOT5B0     : 1;\r
+  __IO uint32_t SOT5B1     : 1;\r
+  __IO uint32_t SCK5B0     : 1;\r
+  __IO uint32_t SCK5B1     : 1;\r
+  __IO uint32_t SIN6S0     : 1;\r
+  __IO uint32_t SIN6S1     : 1;\r
+  __IO uint32_t SOT6B0     : 1;\r
+  __IO uint32_t SOT6B1     : 1;\r
+  __IO uint32_t SCK6B0     : 1;\r
+  __IO uint32_t SCK6B1     : 1;\r
+  __IO uint32_t SIN7S0     : 1;\r
+  __IO uint32_t SIN7S1     : 1;\r
+  __IO uint32_t SOT7B0     : 1;\r
+  __IO uint32_t SOT7B1     : 1;\r
+  __IO uint32_t SCK7B0     : 1;\r
+  __IO uint32_t SCK7B1     : 1;\r
+} stc_gpio_epfr08_field_t;\r
+\r
+typedef struct stc_gpio_epfr09_field\r
+{\r
+  __IO uint32_t QAIN0S0    : 1;\r
+  __IO uint32_t QAIN0S1    : 1;\r
+  __IO uint32_t QBIN0S0    : 1;\r
+  __IO uint32_t QBIN0S1    : 1;\r
+  __IO uint32_t QZIN0S0    : 1;\r
+  __IO uint32_t QZIN0S1    : 1;\r
+  __IO uint32_t QAIN1S0    : 1;\r
+  __IO uint32_t QAIN1S1    : 1;\r
+  __IO uint32_t QBIN1S0    : 1;\r
+  __IO uint32_t QBIN1S1    : 1;\r
+  __IO uint32_t QZIN1S0    : 1;\r
+  __IO uint32_t QZIN1S1    : 1;\r
+  __IO uint32_t ADTRG0S0   : 1;\r
+  __IO uint32_t ADTRG0S1   : 1;\r
+  __IO uint32_t ADTRG0S2   : 1;\r
+  __IO uint32_t ADTRG0S3   : 1;\r
+  __IO uint32_t ADTRG1S0   : 1;\r
+  __IO uint32_t ADTRG1S1   : 1;\r
+  __IO uint32_t ADTRG1S2   : 1;\r
+  __IO uint32_t ADTRG1S3   : 1;\r
+} stc_gpio_epfr09_field_t;\r
+\r
+/******************************************************************************\r
+ * LVD_MODULE\r
+ ******************************************************************************/\r
+/* LVD_MODULE register bit fields */\r
+typedef struct stc_lvd_lvd_ctl_field\r
+{\r
+        uint8_t RESERVED1  : 2;\r
+  __IO  uint8_t SVHI0      : 1;\r
+  __IO  uint8_t SVHI1      : 1;\r
+  __IO  uint8_t SVHI2      : 1;\r
+  __IO  uint8_t SVHI3      : 1;\r
+        uint8_t RESERVED2  : 1;\r
+  __IO  uint8_t LVDIE      : 1;\r
+} stc_lvd_lvd_ctl_field_t;\r
+\r
+typedef struct stc_lvd_lvd_str_field\r
+{\r
+        uint8_t RESERVED1  : 7;\r
+  __IO  uint8_t LVDIR      : 1;\r
+} stc_lvd_lvd_str_field_t;\r
+\r
+typedef struct stc_lvd_lvd_clr_field\r
+{\r
+        uint8_t RESERVED1  : 7;\r
+  __IO  uint8_t LVDCL      : 1;\r
+} stc_lvd_lvd_clr_field_t;\r
+\r
+typedef struct stc_lvd_lvd_str2_field\r
+{\r
+        uint8_t RESERVED1  : 7;\r
+  __IO  uint8_t LVDIRDY    : 1;\r
+} stc_lvd_lvd_str2_field_t;\r
+\r
+/******************************************************************************\r
+ * USBCLK\r
+ ******************************************************************************/\r
+/* USBCLK register bit fields */\r
+typedef struct stc_usbclk_uccr_field\r
+{\r
+  __IO  uint8_t UCEN       : 1;\r
+  __IO  uint8_t UCSEL      : 1;\r
+} stc_usbclk_uccr_field_t;\r
+\r
+typedef struct stc_usbclk_upcr1_field\r
+{\r
+  __IO  uint8_t UPLLEN     : 1;\r
+  __IO  uint8_t UPINC      : 1;\r
+} stc_usbclk_upcr1_field_t;\r
+\r
+typedef struct stc_usbclk_upcr2_field\r
+{\r
+  __IO  uint8_t UPOWT0     : 1;\r
+  __IO  uint8_t UPOWT1     : 1;\r
+  __IO  uint8_t UPOWT2     : 1;\r
+} stc_usbclk_upcr2_field_t;\r
+\r
+typedef struct stc_usbclk_upcr3_field\r
+{\r
+  __IO  uint8_t UPLLK0     : 1;\r
+  __IO  uint8_t UPLLK1     : 1;\r
+  __IO  uint8_t UPLLK2     : 1;\r
+  __IO  uint8_t UPLLK3     : 1;\r
+  __IO  uint8_t UPLLK4     : 1;\r
+} stc_usbclk_upcr3_field_t;\r
+\r
+typedef struct stc_usbclk_upcr4_field\r
+{\r
+  __IO  uint8_t UPLLN0     : 1;\r
+  __IO  uint8_t UPLLN1     : 1;\r
+  __IO  uint8_t UPLLN2     : 1;\r
+  __IO  uint8_t UPLLN3     : 1;\r
+  __IO  uint8_t UPLLN4     : 1;\r
+  __IO  uint8_t UPLLN5     : 1;\r
+  __IO  uint8_t UPLLN6     : 1;\r
+} stc_usbclk_upcr4_field_t;\r
+\r
+typedef struct stc_usbclk_up_str_field\r
+{\r
+  __IO  uint8_t UPRDY      : 1;\r
+} stc_usbclk_up_str_field_t;\r
+\r
+typedef struct stc_usbclk_upint_enr_field\r
+{\r
+  __IO  uint8_t UPCSE      : 1;\r
+} stc_usbclk_upint_enr_field_t;\r
+\r
+typedef struct stc_usbclk_upint_clr_field\r
+{\r
+  __IO  uint8_t UPCSC      : 1;\r
+} stc_usbclk_upint_clr_field_t;\r
+\r
+typedef struct stc_usbclk_upint_str_field\r
+{\r
+  __IO  uint8_t UPCSI      : 1;\r
+} stc_usbclk_upint_str_field_t;\r
+\r
+typedef struct stc_usbclk_upcr5_field\r
+{\r
+  __IO  uint8_t UPLLM0     : 1;\r
+  __IO  uint8_t UPLLM1     : 1;\r
+  __IO  uint8_t UPLLM2     : 1;\r
+  __IO  uint8_t UPLLM3     : 1;\r
+} stc_usbclk_upcr5_field_t;\r
+\r
+typedef struct stc_usbclk_usben_field\r
+{\r
+  __IO  uint8_t USBEN      : 1;\r
+} stc_usbclk_usben_field_t;\r
+\r
+/******************************************************************************\r
+ * MFS03_UART_MODULE\r
+ ******************************************************************************/\r
+/* MFS03_UART_MODULE register bit fields */\r
+typedef struct stc_mfs03_uart_smr_field\r
+{\r
+  __IO  uint8_t SOE        : 1;\r
+        uint8_t RESERVED1  : 1;\r
+  __IO  uint8_t BDS        : 1;\r
+  __IO  uint8_t SBL        : 1;\r
+  __IO  uint8_t WUCR       : 1;\r
+  __IO  uint8_t MD0        : 1;\r
+  __IO  uint8_t MD1        : 1;\r
+  __IO  uint8_t MD2        : 1;\r
+} stc_mfs03_uart_smr_field_t;\r
+\r
+typedef struct stc_mfs03_uart_scr_field\r
+{\r
+  __IO  uint8_t TXE        : 1;\r
+  __IO  uint8_t RXE        : 1;\r
+  __IO  uint8_t TBIE       : 1;\r
+  __IO  uint8_t TIE        : 1;\r
+  __IO  uint8_t RIE        : 1;\r
+        uint8_t RESERVED1  : 2;\r
+  __IO  uint8_t UPCL       : 1;\r
+} stc_mfs03_uart_scr_field_t;\r
+\r
+typedef struct stc_mfs03_uart_escr_field\r
+{\r
+  __IO  uint8_t L0         : 1;\r
+  __IO  uint8_t L1         : 1;\r
+  __IO  uint8_t L2         : 1;\r
+  __IO  uint8_t P          : 1;\r
+  __IO  uint8_t PEN        : 1;\r
+  __IO  uint8_t INV        : 1;\r
+  __IO  uint8_t ESBL       : 1;\r
+  __IO  uint8_t FLWEN      : 1;\r
+} stc_mfs03_uart_escr_field_t;\r
+\r
+typedef struct stc_mfs03_uart_ssr_field\r
+{\r
+  __IO  uint8_t TBI        : 1;\r
+  __IO  uint8_t TDRE       : 1;\r
+  __IO  uint8_t RDRF       : 1;\r
+  __IO  uint8_t ORE        : 1;\r
+  __IO  uint8_t FRE        : 1;\r
+  __IO  uint8_t PE         : 1;\r
+        uint8_t RESERVED1  : 1;\r
+  __IO  uint8_t REC        : 1;\r
+} stc_mfs03_uart_ssr_field_t;\r
+\r
+typedef struct stc_mfs03_uart_rdr_field\r
+{\r
+       uint16_t RESERVED1  : 8;\r
+  __IO uint16_t AD         : 1;\r
+} stc_mfs03_uart_rdr_field_t;\r
+\r
+typedef struct stc_mfs03_uart_tdr_field\r
+{\r
+       uint16_t RESERVED1  : 8;\r
+  __IO uint16_t AD         : 1;\r
+} stc_mfs03_uart_tdr_field_t;\r
+\r
+typedef struct stc_mfs03_uart_bgr_field\r
+{\r
+       uint16_t RESERVED1  : 15;\r
+  __IO uint16_t EXT        : 1;\r
+} stc_mfs03_uart_bgr_field_t;\r
+\r
+typedef struct stc_mfs03_uart_bgr1_field\r
+{\r
+        uint8_t RESERVED1  : 7;\r
+  __IO  uint8_t EXT        : 1;\r
+} stc_mfs03_uart_bgr1_field_t;\r
+\r
+/******************************************************************************\r
+ * MFS03_CSIO_MODULE\r
+ ******************************************************************************/\r
+/* MFS03_CSIO_MODULE register bit fields */\r
+typedef struct stc_mfs03_csio_smr_field\r
+{\r
+  __IO  uint8_t SOE        : 1;\r
+  __IO  uint8_t SCKE       : 1;\r
+  __IO  uint8_t BDS        : 1;\r
+  __IO  uint8_t SCINV      : 1;\r
+  __IO  uint8_t WUCR       : 1;\r
+  __IO  uint8_t MD0        : 1;\r
+  __IO  uint8_t MD1        : 1;\r
+  __IO  uint8_t MD2        : 1;\r
+} stc_mfs03_csio_smr_field_t;\r
+\r
+typedef struct stc_mfs03_csio_scr_field\r
+{\r
+  __IO  uint8_t TXE        : 1;\r
+  __IO  uint8_t RXE        : 1;\r
+  __IO  uint8_t TBIE       : 1;\r
+  __IO  uint8_t TIE        : 1;\r
+  __IO  uint8_t RIE        : 1;\r
+  __IO  uint8_t SPI        : 1;\r
+  __IO  uint8_t MS         : 1;\r
+  __IO  uint8_t UPCL       : 1;\r
+} stc_mfs03_csio_scr_field_t;\r
+\r
+typedef struct stc_mfs03_csio_escr_field\r
+{\r
+  __IO  uint8_t L0         : 1;\r
+  __IO  uint8_t L1         : 1;\r
+  __IO  uint8_t L2         : 1;\r
+  __IO  uint8_t WT0        : 1;\r
+  __IO  uint8_t WT1        : 1;\r
+        uint8_t RESERVED1  : 2;\r
+  __IO  uint8_t SOP        : 1;\r
+} stc_mfs03_csio_escr_field_t;\r
+\r
+typedef struct stc_mfs03_csio_ssr_field\r
+{\r
+  __IO  uint8_t TBI        : 1;\r
+  __IO  uint8_t TDRE       : 1;\r
+  __IO  uint8_t RDRF       : 1;\r
+  __IO  uint8_t ORE        : 1;\r
+        uint8_t RESERVED1  : 3;\r
+  __IO  uint8_t REC        : 1;\r
+} stc_mfs03_csio_ssr_field_t;\r
+\r
+/******************************************************************************\r
+ * MFS03_LIN_MODULE\r
+ ******************************************************************************/\r
+/* MFS03_LIN_MODULE register bit fields */\r
+typedef struct stc_mfs03_lin_smr_field\r
+{\r
+  __IO  uint8_t SOE        : 1;\r
+        uint8_t RESERVED1  : 2;\r
+  __IO  uint8_t SBL        : 1;\r
+  __IO  uint8_t WUCR       : 1;\r
+  __IO  uint8_t MD0        : 1;\r
+  __IO  uint8_t MD1        : 1;\r
+  __IO  uint8_t MD2        : 1;\r
+} stc_mfs03_lin_smr_field_t;\r
+\r
+typedef struct stc_mfs03_lin_scr_field\r
+{\r
+  __IO  uint8_t TXE        : 1;\r
+  __IO  uint8_t RXE        : 1;\r
+  __IO  uint8_t TBIE       : 1;\r
+  __IO  uint8_t TIE        : 1;\r
+  __IO  uint8_t RIE        : 1;\r
+  __IO  uint8_t LBR        : 1;\r
+  __IO  uint8_t MS         : 1;\r
+  __IO  uint8_t UPCL       : 1;\r
+} stc_mfs03_lin_scr_field_t;\r
+\r
+typedef struct stc_mfs03_lin_escr_field\r
+{\r
+  __IO  uint8_t DEL0       : 1;\r
+  __IO  uint8_t DEL1       : 1;\r
+  __IO  uint8_t LBL0       : 1;\r
+  __IO  uint8_t LBL1       : 1;\r
+  __IO  uint8_t LBIE       : 1;\r
+        uint8_t RESERVED1  : 1;\r
+  __IO  uint8_t ESBL       : 1;\r
+} stc_mfs03_lin_escr_field_t;\r
+\r
+typedef struct stc_mfs03_lin_ssr_field\r
+{\r
+  __IO  uint8_t TBI        : 1;\r
+  __IO  uint8_t TDRE       : 1;\r
+  __IO  uint8_t RDRF       : 1;\r
+  __IO  uint8_t ORE        : 1;\r
+  __IO  uint8_t FRE        : 1;\r
+  __IO  uint8_t LBD        : 1;\r
+        uint8_t RESERVED1  : 1;\r
+  __IO  uint8_t REC        : 1;\r
+} stc_mfs03_lin_ssr_field_t;\r
+\r
+typedef struct stc_mfs03_lin_bgr_field\r
+{\r
+       uint16_t RESERVED1  : 15;\r
+  __IO uint16_t EXT        : 1;\r
+} stc_mfs03_lin_bgr_field_t;\r
+\r
+typedef struct stc_mfs03_lin_bgr1_field\r
+{\r
+        uint8_t RESERVED1  : 7;\r
+  __IO  uint8_t EXT        : 1;\r
+} stc_mfs03_lin_bgr1_field_t;\r
+\r
+/******************************************************************************\r
+ * MFS03_I2C_MODULE\r
+ ******************************************************************************/\r
+/* MFS03_I2C_MODULE register bit fields */\r
+typedef struct stc_mfs03_i2c_smr_field\r
+{\r
+  __IO  uint8_t ITST0      : 1;\r
+  __IO  uint8_t ITST1      : 1;\r
+  __IO  uint8_t TIE        : 1;\r
+  __IO  uint8_t RIE        : 1;\r
+  __IO  uint8_t WUCR       : 1;\r
+  __IO  uint8_t MD0        : 1;\r
+  __IO  uint8_t MD1        : 1;\r
+  __IO  uint8_t MD2        : 1;\r
+} stc_mfs03_i2c_smr_field_t;\r
+\r
+typedef struct stc_mfs03_i2c_ibcr_field\r
+{\r
+  __IO  uint8_t INT        : 1;\r
+  __IO  uint8_t BER        : 1;\r
+  __IO  uint8_t INTE       : 1;\r
+  __IO  uint8_t CNDE       : 1;\r
+  __IO  uint8_t WSEL       : 1;\r
+  __IO  uint8_t ACKE       : 1;\r
+  __IO  uint8_t SCC        : 1;\r
+  __IO  uint8_t MSS        : 1;\r
+} stc_mfs03_i2c_ibcr_field_t;\r
+\r
+typedef struct stc_mfs03_i2c_ibsr_field\r
+{\r
+  __IO  uint8_t BB         : 1;\r
+  __IO  uint8_t SPC        : 1;\r
+  __IO  uint8_t RSC        : 1;\r
+  __IO  uint8_t AL         : 1;\r
+  __IO  uint8_t TRX        : 1;\r
+  __IO  uint8_t RSA        : 1;\r
+  __IO  uint8_t RACK       : 1;\r
+  __IO  uint8_t FBT        : 1;\r
+} stc_mfs03_i2c_ibsr_field_t;\r
+\r
+typedef struct stc_mfs03_i2c_ssr_field\r
+{\r
+  __IO  uint8_t TBI        : 1;\r
+  __IO  uint8_t TDRE       : 1;\r
+  __IO  uint8_t RDRF       : 1;\r
+  __IO  uint8_t ORE        : 1;\r
+  __IO  uint8_t TBIE       : 1;\r
+  __IO  uint8_t DMA        : 1;\r
+  __IO  uint8_t TSET       : 1;\r
+  __IO  uint8_t REC        : 1;\r
+} stc_mfs03_i2c_ssr_field_t;\r
+\r
+typedef struct stc_mfs03_i2c_isba_field\r
+{\r
+  __IO  uint8_t SA0        : 1;\r
+  __IO  uint8_t SA1        : 1;\r
+  __IO  uint8_t SA2        : 1;\r
+  __IO  uint8_t SA3        : 1;\r
+  __IO  uint8_t SA4        : 1;\r
+  __IO  uint8_t SA5        : 1;\r
+  __IO  uint8_t SA6        : 1;\r
+  __IO  uint8_t SAEN       : 1;\r
+} stc_mfs03_i2c_isba_field_t;\r
+\r
+typedef struct stc_mfs03_i2c_ismk_field\r
+{\r
+  __IO  uint8_t SM0        : 1;\r
+  __IO  uint8_t SM1        : 1;\r
+  __IO  uint8_t SM2        : 1;\r
+  __IO  uint8_t SM3        : 1;\r
+  __IO  uint8_t SM4        : 1;\r
+  __IO  uint8_t SM5        : 1;\r
+  __IO  uint8_t SM6        : 1;\r
+  __IO  uint8_t EN         : 1;\r
+} stc_mfs03_i2c_ismk_field_t;\r
+\r
+/******************************************************************************\r
+ * MFS47_UART_MODULE\r
+ ******************************************************************************/\r
+/* MFS47_UART_MODULE register bit fields */\r
+typedef struct stc_mfs47_uart_smr_field\r
+{\r
+  __IO  uint8_t SOE        : 1;\r
+        uint8_t RESERVED1  : 1;\r
+  __IO  uint8_t BDS        : 1;\r
+  __IO  uint8_t SBL        : 1;\r
+  __IO  uint8_t WUCR       : 1;\r
+  __IO  uint8_t MD0        : 1;\r
+  __IO  uint8_t MD1        : 1;\r
+  __IO  uint8_t MD2        : 1;\r
+} stc_mfs47_uart_smr_field_t;\r
+\r
+typedef struct stc_mfs47_uart_scr_field\r
+{\r
+  __IO  uint8_t TXE        : 1;\r
+  __IO  uint8_t RXE        : 1;\r
+  __IO  uint8_t TBIE       : 1;\r
+  __IO  uint8_t TIE        : 1;\r
+  __IO  uint8_t RIE        : 1;\r
+        uint8_t RESERVED1  : 2;\r
+  __IO  uint8_t UPCL       : 1;\r
+} stc_mfs47_uart_scr_field_t;\r
+\r
+typedef struct stc_mfs47_uart_escr_field\r
+{\r
+  __IO  uint8_t L0         : 1;\r
+  __IO  uint8_t L1         : 1;\r
+  __IO  uint8_t L2         : 1;\r
+  __IO  uint8_t P          : 1;\r
+  __IO  uint8_t PEN        : 1;\r
+  __IO  uint8_t INV        : 1;\r
+  __IO  uint8_t ESBL       : 1;\r
+  __IO  uint8_t FLWEN      : 1;\r
+} stc_mfs47_uart_escr_field_t;\r
+\r
+typedef struct stc_mfs47_uart_ssr_field\r
+{\r
+  __IO  uint8_t TBI        : 1;\r
+  __IO  uint8_t TDRE       : 1;\r
+  __IO  uint8_t RDRF       : 1;\r
+  __IO  uint8_t ORE        : 1;\r
+  __IO  uint8_t FRE        : 1;\r
+  __IO  uint8_t PE         : 1;\r
+        uint8_t RESERVED1  : 1;\r
+  __IO  uint8_t REC        : 1;\r
+} stc_mfs47_uart_ssr_field_t;\r
+\r
+typedef struct stc_mfs47_uart_rdr_field\r
+{\r
+       uint16_t RESERVED1  : 8;\r
+  __IO uint16_t AD         : 1;\r
+} stc_mfs47_uart_rdr_field_t;\r
+\r
+typedef struct stc_mfs47_uart_tdr_field\r
+{\r
+       uint16_t RESERVED1  : 8;\r
+  __IO uint16_t AD         : 1;\r
+} stc_mfs47_uart_tdr_field_t;\r
+\r
+typedef struct stc_mfs47_uart_bgr_field\r
+{\r
+       uint16_t RESERVED1  : 15;\r
+  __IO uint16_t EXT        : 1;\r
+} stc_mfs47_uart_bgr_field_t;\r
+\r
+typedef struct stc_mfs47_uart_bgr1_field\r
+{\r
+        uint8_t RESERVED1  : 7;\r
+  __IO  uint8_t EXT        : 1;\r
+} stc_mfs47_uart_bgr1_field_t;\r
+\r
+typedef struct stc_mfs47_uart_fcr_field\r
+{\r
+  __IO uint16_t FE1        : 1;\r
+  __IO uint16_t FE2        : 1;\r
+  __IO uint16_t FCL1       : 1;\r
+  __IO uint16_t FCL2       : 1;\r
+  __IO uint16_t FSET       : 1;\r
+  __IO uint16_t FLD        : 1;\r
+  __IO uint16_t FLST       : 1;\r
+       uint16_t RESERVED1  : 1;\r
+  __IO uint16_t FSEL       : 1;\r
+  __IO uint16_t FTIE       : 1;\r
+  __IO uint16_t FDRQ       : 1;\r
+  __IO uint16_t FRIE       : 1;\r
+  __IO uint16_t FLSTE      : 1;\r
+       uint16_t RESERVED2  : 1;\r
+  __IO uint16_t FTST0      : 1;\r
+  __IO uint16_t FTST1      : 1;\r
+} stc_mfs47_uart_fcr_field_t;\r
+\r
+typedef struct stc_mfs47_uart_fcr0_field\r
+{\r
+  __IO  uint8_t FE1        : 1;\r
+  __IO  uint8_t FE2        : 1;\r
+  __IO  uint8_t FCL1       : 1;\r
+  __IO  uint8_t FCL2       : 1;\r
+  __IO  uint8_t FSET       : 1;\r
+  __IO  uint8_t FLD        : 1;\r
+  __IO  uint8_t FLST       : 1;\r
+} stc_mfs47_uart_fcr0_field_t;\r
+\r
+typedef struct stc_mfs47_uart_fcr1_field\r
+{\r
+  __IO  uint8_t FSEL       : 1;\r
+  __IO  uint8_t FTIE       : 1;\r
+  __IO  uint8_t FDRQ       : 1;\r
+  __IO  uint8_t FRIE       : 1;\r
+  __IO  uint8_t FLSTE      : 1;\r
+        uint8_t RESERVED1  : 1;\r
+  __IO  uint8_t FTST0      : 1;\r
+  __IO  uint8_t FTST1      : 1;\r
+} stc_mfs47_uart_fcr1_field_t;\r
+\r
+typedef struct stc_mfs47_uart_fbyte_field\r
+{\r
+  __IO uint16_t FD0        : 1;\r
+  __IO uint16_t FD1        : 1;\r
+  __IO uint16_t FD2        : 1;\r
+  __IO uint16_t FD3        : 1;\r
+  __IO uint16_t FD4        : 1;\r
+  __IO uint16_t FD5        : 1;\r
+  __IO uint16_t FD6        : 1;\r
+  __IO uint16_t FD7        : 1;\r
+  __IO uint16_t FD8        : 1;\r
+  __IO uint16_t FD9        : 1;\r
+  __IO uint16_t FD10       : 1;\r
+  __IO uint16_t FD11       : 1;\r
+  __IO uint16_t FD12       : 1;\r
+  __IO uint16_t FD13       : 1;\r
+  __IO uint16_t FD14       : 1;\r
+  __IO uint16_t FD15       : 1;\r
+} stc_mfs47_uart_fbyte_field_t;\r
+\r
+typedef struct stc_mfs47_uart_fbyte1_field\r
+{\r
+  __IO  uint8_t FD0        : 1;\r
+  __IO  uint8_t FD1        : 1;\r
+  __IO  uint8_t FD2        : 1;\r
+  __IO  uint8_t FD3        : 1;\r
+  __IO  uint8_t FD4        : 1;\r
+  __IO  uint8_t FD5        : 1;\r
+  __IO  uint8_t FD6        : 1;\r
+  __IO  uint8_t FD7        : 1;\r
+} stc_mfs47_uart_fbyte1_field_t;\r
+\r
+typedef struct stc_mfs47_uart_fbyte2_field\r
+{\r
+  __IO  uint8_t FD8        : 1;\r
+  __IO  uint8_t FD9        : 1;\r
+  __IO  uint8_t FD10       : 1;\r
+  __IO  uint8_t FD11       : 1;\r
+  __IO  uint8_t FD12       : 1;\r
+  __IO  uint8_t FD13       : 1;\r
+  __IO  uint8_t FD14       : 1;\r
+  __IO  uint8_t FD15       : 1;\r
+} stc_mfs47_uart_fbyte2_field_t;\r
+\r
+/******************************************************************************\r
+ * MFS47_CSIO_MODULE\r
+ ******************************************************************************/\r
+/* MFS47_CSIO_MODULE register bit fields */\r
+typedef struct stc_mfs47_csio_smr_field\r
+{\r
+  __IO  uint8_t SOE        : 1;\r
+  __IO  uint8_t SCKE       : 1;\r
+  __IO  uint8_t BDS        : 1;\r
+  __IO  uint8_t SCINV      : 1;\r
+  __IO  uint8_t WUCR       : 1;\r
+  __IO  uint8_t MD0        : 1;\r
+  __IO  uint8_t MD1        : 1;\r
+  __IO  uint8_t MD2        : 1;\r
+} stc_mfs47_csio_smr_field_t;\r
+\r
+typedef struct stc_mfs47_csio_scr_field\r
+{\r
+  __IO  uint8_t TXE        : 1;\r
+  __IO  uint8_t RXE        : 1;\r
+  __IO  uint8_t TBIE       : 1;\r
+  __IO  uint8_t TIE        : 1;\r
+  __IO  uint8_t RIE        : 1;\r
+  __IO  uint8_t SPI        : 1;\r
+  __IO  uint8_t MS         : 1;\r
+  __IO  uint8_t UPCL       : 1;\r
+} stc_mfs47_csio_scr_field_t;\r
+\r
+typedef struct stc_mfs47_csio_escr_field\r
+{\r
+  __IO  uint8_t L0         : 1;\r
+  __IO  uint8_t L1         : 1;\r
+  __IO  uint8_t L2         : 1;\r
+  __IO  uint8_t WT0        : 1;\r
+  __IO  uint8_t WT1        : 1;\r
+        uint8_t RESERVED1  : 2;\r
+  __IO  uint8_t SOP        : 1;\r
+} stc_mfs47_csio_escr_field_t;\r
+\r
+typedef struct stc_mfs47_csio_ssr_field\r
+{\r
+  __IO  uint8_t TBI        : 1;\r
+  __IO  uint8_t TDRE       : 1;\r
+  __IO  uint8_t RDRF       : 1;\r
+  __IO  uint8_t ORE        : 1;\r
+        uint8_t RESERVED1  : 3;\r
+  __IO  uint8_t REC        : 1;\r
+} stc_mfs47_csio_ssr_field_t;\r
+\r
+typedef struct stc_mfs47_csio_fcr_field\r
+{\r
+  __IO uint16_t FE1        : 1;\r
+  __IO uint16_t FE2        : 1;\r
+  __IO uint16_t FCL1       : 1;\r
+  __IO uint16_t FCL2       : 1;\r
+  __IO uint16_t FSET       : 1;\r
+  __IO uint16_t FLD        : 1;\r
+  __IO uint16_t FLST       : 1;\r
+       uint16_t RESERVED1  : 1;\r
+  __IO uint16_t FSEL       : 1;\r
+  __IO uint16_t FTIE       : 1;\r
+  __IO uint16_t FDRQ       : 1;\r
+  __IO uint16_t FRIE       : 1;\r
+  __IO uint16_t FLSTE      : 1;\r
+       uint16_t RESERVED2  : 1;\r
+  __IO uint16_t FTST0      : 1;\r
+  __IO uint16_t FTST1      : 1;\r
+} stc_mfs47_csio_fcr_field_t;\r
+\r
+typedef struct stc_mfs47_csio_fcr0_field\r
+{\r
+  __IO  uint8_t FE1        : 1;\r
+  __IO  uint8_t FE2        : 1;\r
+  __IO  uint8_t FCL1       : 1;\r
+  __IO  uint8_t FCL2       : 1;\r
+  __IO  uint8_t FSET       : 1;\r
+  __IO  uint8_t FLD        : 1;\r
+  __IO  uint8_t FLST       : 1;\r
+} stc_mfs47_csio_fcr0_field_t;\r
+\r
+typedef struct stc_mfs47_csio_fcr1_field\r
+{\r
+  __IO  uint8_t FSEL       : 1;\r
+  __IO  uint8_t FTIE       : 1;\r
+  __IO  uint8_t FDRQ       : 1;\r
+  __IO  uint8_t FRIE       : 1;\r
+  __IO  uint8_t FLSTE      : 1;\r
+        uint8_t RESERVED1  : 1;\r
+  __IO  uint8_t FTST0      : 1;\r
+  __IO  uint8_t FTST1      : 1;\r
+} stc_mfs47_csio_fcr1_field_t;\r
+\r
+typedef struct stc_mfs47_csio_fbyte_field\r
+{\r
+  __IO uint16_t FD0        : 1;\r
+  __IO uint16_t FD1        : 1;\r
+  __IO uint16_t FD2        : 1;\r
+  __IO uint16_t FD3        : 1;\r
+  __IO uint16_t FD4        : 1;\r
+  __IO uint16_t FD5        : 1;\r
+  __IO uint16_t FD6        : 1;\r
+  __IO uint16_t FD7        : 1;\r
+  __IO uint16_t FD8        : 1;\r
+  __IO uint16_t FD9        : 1;\r
+  __IO uint16_t FD10       : 1;\r
+  __IO uint16_t FD11       : 1;\r
+  __IO uint16_t FD12       : 1;\r
+  __IO uint16_t FD13       : 1;\r
+  __IO uint16_t FD14       : 1;\r
+  __IO uint16_t FD15       : 1;\r
+} stc_mfs47_csio_fbyte_field_t;\r
+\r
+typedef struct stc_mfs47_csio_fbyte1_field\r
+{\r
+  __IO  uint8_t FD0        : 1;\r
+  __IO  uint8_t FD1        : 1;\r
+  __IO  uint8_t FD2        : 1;\r
+  __IO  uint8_t FD3        : 1;\r
+  __IO  uint8_t FD4        : 1;\r
+  __IO  uint8_t FD5        : 1;\r
+  __IO  uint8_t FD6        : 1;\r
+  __IO  uint8_t FD7        : 1;\r
+} stc_mfs47_csio_fbyte1_field_t;\r
+\r
+typedef struct stc_mfs47_csio_fbyte2_field\r
+{\r
+  __IO  uint8_t FD8        : 1;\r
+  __IO  uint8_t FD9        : 1;\r
+  __IO  uint8_t FD10       : 1;\r
+  __IO  uint8_t FD11       : 1;\r
+  __IO  uint8_t FD12       : 1;\r
+  __IO  uint8_t FD13       : 1;\r
+  __IO  uint8_t FD14       : 1;\r
+  __IO  uint8_t FD15       : 1;\r
+} stc_mfs47_csio_fbyte2_field_t;\r
+\r
+/******************************************************************************\r
+ * MFS47_LIN_MODULE\r
+ ******************************************************************************/\r
+/* MFS47_LIN_MODULE register bit fields */\r
+typedef struct stc_mfs47_lin_smr_field\r
+{\r
+  __IO  uint8_t SOE        : 1;\r
+        uint8_t RESERVED1  : 2;\r
+  __IO  uint8_t SBL        : 1;\r
+  __IO  uint8_t WUCR       : 1;\r
+  __IO  uint8_t MD0        : 1;\r
+  __IO  uint8_t MD1        : 1;\r
+  __IO  uint8_t MD2        : 1;\r
+} stc_mfs47_lin_smr_field_t;\r
+\r
+typedef struct stc_mfs47_lin_scr_field\r
+{\r
+  __IO  uint8_t TXE        : 1;\r
+  __IO  uint8_t RXE        : 1;\r
+  __IO  uint8_t TBIE       : 1;\r
+  __IO  uint8_t TIE        : 1;\r
+  __IO  uint8_t RIE        : 1;\r
+  __IO  uint8_t LBR        : 1;\r
+  __IO  uint8_t MS         : 1;\r
+  __IO  uint8_t UPCL       : 1;\r
+} stc_mfs47_lin_scr_field_t;\r
+\r
+typedef struct stc_mfs47_lin_escr_field\r
+{\r
+  __IO  uint8_t DEL0       : 1;\r
+  __IO  uint8_t DEL1       : 1;\r
+  __IO  uint8_t LBL0       : 1;\r
+  __IO  uint8_t LBL1       : 1;\r
+  __IO  uint8_t LBIE       : 1;\r
+        uint8_t RESERVED1  : 1;\r
+  __IO  uint8_t ESBL       : 1;\r
+} stc_mfs47_lin_escr_field_t;\r
+\r
+typedef struct stc_mfs47_lin_ssr_field\r
+{\r
+  __IO  uint8_t TBI        : 1;\r
+  __IO  uint8_t TDRE       : 1;\r
+  __IO  uint8_t RDRF       : 1;\r
+  __IO  uint8_t ORE        : 1;\r
+  __IO  uint8_t FRE        : 1;\r
+  __IO  uint8_t LBD        : 1;\r
+        uint8_t RESERVED1  : 1;\r
+  __IO  uint8_t REC        : 1;\r
+} stc_mfs47_lin_ssr_field_t;\r
+\r
+typedef struct stc_mfs47_lin_bgr_field\r
+{\r
+       uint16_t RESERVED1  : 15;\r
+  __IO uint16_t EXT        : 1;\r
+} stc_mfs47_lin_bgr_field_t;\r
+\r
+typedef struct stc_mfs47_lin_bgr1_field\r
+{\r
+        uint8_t RESERVED1  : 7;\r
+  __IO  uint8_t EXT        : 1;\r
+} stc_mfs47_lin_bgr1_field_t;\r
+\r
+typedef struct stc_mfs47_lin_fcr_field\r
+{\r
+  __IO uint16_t FE1        : 1;\r
+  __IO uint16_t FE2        : 1;\r
+  __IO uint16_t FCL1       : 1;\r
+  __IO uint16_t FCL2       : 1;\r
+  __IO uint16_t FSET       : 1;\r
+  __IO uint16_t FLD        : 1;\r
+  __IO uint16_t FLST       : 1;\r
+       uint16_t RESERVED1  : 1;\r
+  __IO uint16_t FSEL       : 1;\r
+  __IO uint16_t FTIE       : 1;\r
+  __IO uint16_t FDRQ       : 1;\r
+  __IO uint16_t FRIE       : 1;\r
+  __IO uint16_t FLSTE      : 1;\r
+       uint16_t RESERVED2  : 1;\r
+  __IO uint16_t FTST0      : 1;\r
+  __IO uint16_t FTST1      : 1;\r
+} stc_mfs47_lin_fcr_field_t;\r
+\r
+typedef struct stc_mfs47_lin_fcr0_field\r
+{\r
+  __IO  uint8_t FE1        : 1;\r
+  __IO  uint8_t FE2        : 1;\r
+  __IO  uint8_t FCL1       : 1;\r
+  __IO  uint8_t FCL2       : 1;\r
+  __IO  uint8_t FSET       : 1;\r
+  __IO  uint8_t FLD        : 1;\r
+  __IO  uint8_t FLST       : 1;\r
+} stc_mfs47_lin_fcr0_field_t;\r
+\r
+typedef struct stc_mfs47_lin_fcr1_field\r
+{\r
+  __IO  uint8_t FSEL       : 1;\r
+  __IO  uint8_t FTIE       : 1;\r
+  __IO  uint8_t FDRQ       : 1;\r
+  __IO  uint8_t FRIE       : 1;\r
+  __IO  uint8_t FLSTE      : 1;\r
+        uint8_t RESERVED1  : 1;\r
+  __IO  uint8_t FTST0      : 1;\r
+  __IO  uint8_t FTST1      : 1;\r
+} stc_mfs47_lin_fcr1_field_t;\r
+\r
+typedef struct stc_mfs47_lin_fbyte_field\r
+{\r
+  __IO uint16_t FD0        : 1;\r
+  __IO uint16_t FD1        : 1;\r
+  __IO uint16_t FD2        : 1;\r
+  __IO uint16_t FD3        : 1;\r
+  __IO uint16_t FD4        : 1;\r
+  __IO uint16_t FD5        : 1;\r
+  __IO uint16_t FD6        : 1;\r
+  __IO uint16_t FD7        : 1;\r
+  __IO uint16_t FD8        : 1;\r
+  __IO uint16_t FD9        : 1;\r
+  __IO uint16_t FD10       : 1;\r
+  __IO uint16_t FD11       : 1;\r
+  __IO uint16_t FD12       : 1;\r
+  __IO uint16_t FD13       : 1;\r
+  __IO uint16_t FD14       : 1;\r
+  __IO uint16_t FD15       : 1;\r
+} stc_mfs47_lin_fbyte_field_t;\r
+\r
+typedef struct stc_mfs47_lin_fbyte1_field\r
+{\r
+  __IO  uint8_t FD0        : 1;\r
+  __IO  uint8_t FD1        : 1;\r
+  __IO  uint8_t FD2        : 1;\r
+  __IO  uint8_t FD3        : 1;\r
+  __IO  uint8_t FD4        : 1;\r
+  __IO  uint8_t FD5        : 1;\r
+  __IO  uint8_t FD6        : 1;\r
+  __IO  uint8_t FD7        : 1;\r
+} stc_mfs47_lin_fbyte1_field_t;\r
+\r
+typedef struct stc_mfs47_lin_fbyte2_field\r
+{\r
+  __IO  uint8_t FD8        : 1;\r
+  __IO  uint8_t FD9        : 1;\r
+  __IO  uint8_t FD10       : 1;\r
+  __IO  uint8_t FD11       : 1;\r
+  __IO  uint8_t FD12       : 1;\r
+  __IO  uint8_t FD13       : 1;\r
+  __IO  uint8_t FD14       : 1;\r
+  __IO  uint8_t FD15       : 1;\r
+} stc_mfs47_lin_fbyte2_field_t;\r
+\r
+/******************************************************************************\r
+ * MFS47_I2C_MODULE\r
+ ******************************************************************************/\r
+/* MFS47_I2C_MODULE register bit fields */\r
+typedef struct stc_mfs47_i2c_smr_field\r
+{\r
+  __IO  uint8_t ITST0      : 1;\r
+  __IO  uint8_t ITST1      : 1;\r
+  __IO  uint8_t TIE        : 1;\r
+  __IO  uint8_t RIE        : 1;\r
+  __IO  uint8_t WUCR       : 1;\r
+  __IO  uint8_t MD0        : 1;\r
+  __IO  uint8_t MD1        : 1;\r
+  __IO  uint8_t MD2        : 1;\r
+} stc_mfs47_i2c_smr_field_t;\r
+\r
+typedef struct stc_mfs47_i2c_ibcr_field\r
+{\r
+  __IO  uint8_t INT        : 1;\r
+  __IO  uint8_t BER        : 1;\r
+  __IO  uint8_t INTE       : 1;\r
+  __IO  uint8_t CNDE       : 1;\r
+  __IO  uint8_t WSEL       : 1;\r
+  __IO  uint8_t ACKE       : 1;\r
+  __IO  uint8_t SCC        : 1;\r
+  __IO  uint8_t MSS        : 1;\r
+} stc_mfs47_i2c_ibcr_field_t;\r
+\r
+typedef struct stc_mfs47_i2c_ibsr_field\r
+{\r
+  __IO  uint8_t BB         : 1;\r
+  __IO  uint8_t SPC        : 1;\r
+  __IO  uint8_t RSC        : 1;\r
+  __IO  uint8_t AL         : 1;\r
+  __IO  uint8_t TRX        : 1;\r
+  __IO  uint8_t RSA        : 1;\r
+  __IO  uint8_t RACK       : 1;\r
+  __IO  uint8_t FBT        : 1;\r
+} stc_mfs47_i2c_ibsr_field_t;\r
+\r
+typedef struct stc_mfs47_i2c_ssr_field\r
+{\r
+  __IO  uint8_t TBI        : 1;\r
+  __IO  uint8_t TDRE       : 1;\r
+  __IO  uint8_t RDRF       : 1;\r
+  __IO  uint8_t ORE        : 1;\r
+  __IO  uint8_t TBIE       : 1;\r
+  __IO  uint8_t DMA        : 1;\r
+  __IO  uint8_t TSET       : 1;\r
+  __IO  uint8_t REC        : 1;\r
+} stc_mfs47_i2c_ssr_field_t;\r
+\r
+typedef struct stc_mfs47_i2c_isba_field\r
+{\r
+  __IO  uint8_t SA0        : 1;\r
+  __IO  uint8_t SA1        : 1;\r
+  __IO  uint8_t SA2        : 1;\r
+  __IO  uint8_t SA3        : 1;\r
+  __IO  uint8_t SA4        : 1;\r
+  __IO  uint8_t SA5        : 1;\r
+  __IO  uint8_t SA6        : 1;\r
+  __IO  uint8_t SAEN       : 1;\r
+} stc_mfs47_i2c_isba_field_t;\r
+\r
+typedef struct stc_mfs47_i2c_ismk_field\r
+{\r
+  __IO  uint8_t SM0        : 1;\r
+  __IO  uint8_t SM1        : 1;\r
+  __IO  uint8_t SM2        : 1;\r
+  __IO  uint8_t SM3        : 1;\r
+  __IO  uint8_t SM4        : 1;\r
+  __IO  uint8_t SM5        : 1;\r
+  __IO  uint8_t SM6        : 1;\r
+  __IO  uint8_t EN         : 1;\r
+} stc_mfs47_i2c_ismk_field_t;\r
+\r
+typedef struct stc_mfs47_i2c_fcr_field\r
+{\r
+  __IO uint16_t FE1        : 1;\r
+  __IO uint16_t FE2        : 1;\r
+  __IO uint16_t FCL1       : 1;\r
+  __IO uint16_t FCL2       : 1;\r
+  __IO uint16_t FSET       : 1;\r
+  __IO uint16_t FLD        : 1;\r
+  __IO uint16_t FLST       : 1;\r
+       uint16_t RESERVED1  : 1;\r
+  __IO uint16_t FSEL       : 1;\r
+  __IO uint16_t FTIE       : 1;\r
+  __IO uint16_t FDRQ       : 1;\r
+  __IO uint16_t FRIE       : 1;\r
+  __IO uint16_t FLSTE      : 1;\r
+       uint16_t RESERVED2  : 1;\r
+  __IO uint16_t FTST0      : 1;\r
+  __IO uint16_t FTST1      : 1;\r
+} stc_mfs47_i2c_fcr_field_t;\r
+\r
+typedef struct stc_mfs47_i2c_fcr0_field\r
+{\r
+  __IO  uint8_t FE1        : 1;\r
+  __IO  uint8_t FE2        : 1;\r
+  __IO  uint8_t FCL1       : 1;\r
+  __IO  uint8_t FCL2       : 1;\r
+  __IO  uint8_t FSET       : 1;\r
+  __IO  uint8_t FLD        : 1;\r
+  __IO  uint8_t FLST       : 1;\r
+} stc_mfs47_i2c_fcr0_field_t;\r
+\r
+typedef struct stc_mfs47_i2c_fcr1_field\r
+{\r
+  __IO  uint8_t FSEL       : 1;\r
+  __IO  uint8_t FTIE       : 1;\r
+  __IO  uint8_t FDRQ       : 1;\r
+  __IO  uint8_t FRIE       : 1;\r
+  __IO  uint8_t FLSTE      : 1;\r
+        uint8_t RESERVED1  : 1;\r
+  __IO  uint8_t FTST0      : 1;\r
+  __IO  uint8_t FTST1      : 1;\r
+} stc_mfs47_i2c_fcr1_field_t;\r
+\r
+typedef struct stc_mfs47_i2c_fbyte_field\r
+{\r
+  __IO uint16_t FD0        : 1;\r
+  __IO uint16_t FD1        : 1;\r
+  __IO uint16_t FD2        : 1;\r
+  __IO uint16_t FD3        : 1;\r
+  __IO uint16_t FD4        : 1;\r
+  __IO uint16_t FD5        : 1;\r
+  __IO uint16_t FD6        : 1;\r
+  __IO uint16_t FD7        : 1;\r
+  __IO uint16_t FD8        : 1;\r
+  __IO uint16_t FD9        : 1;\r
+  __IO uint16_t FD10       : 1;\r
+  __IO uint16_t FD11       : 1;\r
+  __IO uint16_t FD12       : 1;\r
+  __IO uint16_t FD13       : 1;\r
+  __IO uint16_t FD14       : 1;\r
+  __IO uint16_t FD15       : 1;\r
+} stc_mfs47_i2c_fbyte_field_t;\r
+\r
+typedef struct stc_mfs47_i2c_fbyte1_field\r
+{\r
+  __IO  uint8_t FD0        : 1;\r
+  __IO  uint8_t FD1        : 1;\r
+  __IO  uint8_t FD2        : 1;\r
+  __IO  uint8_t FD3        : 1;\r
+  __IO  uint8_t FD4        : 1;\r
+  __IO  uint8_t FD5        : 1;\r
+  __IO  uint8_t FD6        : 1;\r
+  __IO  uint8_t FD7        : 1;\r
+} stc_mfs47_i2c_fbyte1_field_t;\r
+\r
+typedef struct stc_mfs47_i2c_fbyte2_field\r
+{\r
+  __IO  uint8_t FD8        : 1;\r
+  __IO  uint8_t FD9        : 1;\r
+  __IO  uint8_t FD10       : 1;\r
+  __IO  uint8_t FD11       : 1;\r
+  __IO  uint8_t FD12       : 1;\r
+  __IO  uint8_t FD13       : 1;\r
+  __IO  uint8_t FD14       : 1;\r
+  __IO  uint8_t FD15       : 1;\r
+} stc_mfs47_i2c_fbyte2_field_t;\r
+\r
+/******************************************************************************\r
+ * CRC_MODULE\r
+ ******************************************************************************/\r
+/* CRC_MODULE register bit fields */\r
+typedef struct stc_crc_crccr_field\r
+{\r
+  __IO  uint8_t INIT       : 1;\r
+  __IO  uint8_t CRC32      : 1;\r
+  __IO  uint8_t LTLEND     : 1;\r
+  __IO  uint8_t LSBFST     : 1;\r
+  __IO  uint8_t CRCLTE     : 1;\r
+  __IO  uint8_t CRCLSF     : 1;\r
+  __IO  uint8_t FXOR       : 1;\r
+} stc_crc_crccr_field_t;\r
+\r
+/******************************************************************************\r
+ * WC_MODULE\r
+ ******************************************************************************/\r
+/* WC_MODULE register bit fields */\r
+typedef struct stc_wc_wcrd_field\r
+{\r
+  __IO  uint8_t CTR0       : 1;\r
+  __IO  uint8_t CTR1       : 1;\r
+  __IO  uint8_t CTR2       : 1;\r
+  __IO  uint8_t CTR3       : 1;\r
+  __IO  uint8_t CTR4       : 1;\r
+  __IO  uint8_t CTR5       : 1;\r
+} stc_wc_wcrd_field_t;\r
+\r
+typedef struct stc_wc_wcrl_field\r
+{\r
+  __IO  uint8_t RLC0       : 1;\r
+  __IO  uint8_t RLC1       : 1;\r
+  __IO  uint8_t RLC2       : 1;\r
+  __IO  uint8_t RLC3       : 1;\r
+  __IO  uint8_t RLC4       : 1;\r
+  __IO  uint8_t RLC5       : 1;\r
+} stc_wc_wcrl_field_t;\r
+\r
+typedef struct stc_wc_wccr_field\r
+{\r
+  __IO  uint8_t WCIF       : 1;\r
+  __IO  uint8_t WCIE       : 1;\r
+  __IO  uint8_t CS0        : 1;\r
+  __IO  uint8_t CS1        : 1;\r
+        uint8_t RESERVED1  : 2;\r
+  __IO  uint8_t WCOP       : 1;\r
+  __IO  uint8_t WCEN       : 1;\r
+} stc_wc_wccr_field_t;\r
+\r
+typedef struct stc_wc_clk_sel_field\r
+{\r
+  __IO uint16_t SEL_IN     : 1;\r
+       uint16_t RESERVED1  : 7;\r
+  __IO uint16_t SEL_OUT    : 1;\r
+} stc_wc_clk_sel_field_t;\r
+\r
+typedef struct stc_wc_clk_en_field\r
+{\r
+  __IO  uint8_t CLK_EN     : 1;\r
+  __IO  uint8_t CLK_EN_R   : 1;\r
+} stc_wc_clk_en_field_t;\r
+\r
+/******************************************************************************\r
+ * USB_MODULE\r
+ ******************************************************************************/\r
+/* USB_MODULE register bit fields */\r
+typedef struct stc_usb_hcnt_field\r
+{\r
+  __IO uint16_t HOST       : 1;\r
+  __IO uint16_t URST       : 1;\r
+  __IO uint16_t SOFIRE     : 1;\r
+  __IO uint16_t DIRE       : 1;\r
+  __IO uint16_t CNNIRE     : 1;\r
+  __IO uint16_t CMPIRE     : 1;\r
+  __IO uint16_t URIRE      : 1;\r
+  __IO uint16_t RWKIRE     : 1;\r
+  __IO uint16_t RETRY      : 1;\r
+  __IO uint16_t CANCEL     : 1;\r
+  __IO uint16_t SOFSTEP    : 1;\r
+} stc_usb_hcnt_field_t;\r
+\r
+typedef struct stc_usb_hcnt0_field\r
+{\r
+  __IO  uint8_t HOST       : 1;\r
+  __IO  uint8_t URST       : 1;\r
+  __IO  uint8_t SOFIRE     : 1;\r
+  __IO  uint8_t DIRE       : 1;\r
+  __IO  uint8_t CNNIRE     : 1;\r
+  __IO  uint8_t CMPIRE     : 1;\r
+  __IO  uint8_t URIRE      : 1;\r
+  __IO  uint8_t RWKIRE     : 1;\r
+} stc_usb_hcnt0_field_t;\r
+\r
+typedef struct stc_usb_hcnt1_field\r
+{\r
+  __IO  uint8_t RETRY      : 1;\r
+  __IO  uint8_t CANCEL     : 1;\r
+  __IO  uint8_t SOFSTEP    : 1;\r
+} stc_usb_hcnt1_field_t;\r
+\r
+typedef struct stc_usb_hirq_field\r
+{\r
+  __IO  uint8_t SOFIRQ     : 1;\r
+  __IO  uint8_t DIRQ       : 1;\r
+  __IO  uint8_t CNNIRQ     : 1;\r
+  __IO  uint8_t CMPIRQ     : 1;\r
+  __IO  uint8_t URIRQ      : 1;\r
+  __IO  uint8_t RWKIRQ     : 1;\r
+        uint8_t RESERVED1  : 1;\r
+  __IO  uint8_t TCAN       : 1;\r
+} stc_usb_hirq_field_t;\r
+\r
+typedef struct stc_usb_herr_field\r
+{\r
+  __IO  uint8_t HS0        : 1;\r
+  __IO  uint8_t HS1        : 1;\r
+  __IO  uint8_t STUFF      : 1;\r
+  __IO  uint8_t TGERR      : 1;\r
+  __IO  uint8_t CRC        : 1;\r
+  __IO  uint8_t TOUT       : 1;\r
+  __IO  uint8_t RERR       : 1;\r
+  __IO  uint8_t LSTOF      : 1;\r
+} stc_usb_herr_field_t;\r
+\r
+typedef struct stc_usb_hstate_field\r
+{\r
+  __IO  uint8_t CSTAT      : 1;\r
+  __IO  uint8_t TMODE      : 1;\r
+  __IO  uint8_t SUSP       : 1;\r
+  __IO  uint8_t SOFBUSY    : 1;\r
+  __IO  uint8_t CLKSEL     : 1;\r
+  __IO  uint8_t ALIVE      : 1;\r
+} stc_usb_hstate_field_t;\r
+\r
+typedef struct stc_usb_hfcomp_field\r
+{\r
+  __IO  uint8_t FRAMECOMP0 : 1;\r
+  __IO  uint8_t FRAMECOMP1 : 1;\r
+  __IO  uint8_t FRAMECOMP2 : 1;\r
+  __IO  uint8_t FRAMECOMP3 : 1;\r
+  __IO  uint8_t FRAMECOMP4 : 1;\r
+  __IO  uint8_t FRAMECOMP5 : 1;\r
+  __IO  uint8_t FRAMECOMP6 : 1;\r
+  __IO  uint8_t FRAMECOMP7 : 1;\r
+} stc_usb_hfcomp_field_t;\r
+\r
+typedef struct stc_usb_hrtimer_field\r
+{\r
+  __IO uint16_t RTIMER0    : 1;\r
+  __IO uint16_t RTIMER1    : 1;\r
+  __IO uint16_t RTIMER2    : 1;\r
+  __IO uint16_t RTIMER3    : 1;\r
+  __IO uint16_t RTIMER4    : 1;\r
+  __IO uint16_t RTIMER5    : 1;\r
+  __IO uint16_t RTIMER6    : 1;\r
+  __IO uint16_t RTIMER7    : 1;\r
+  __IO uint16_t RTIMER8    : 1;\r
+  __IO uint16_t RTIMER9    : 1;\r
+  __IO uint16_t RTIMER10   : 1;\r
+  __IO uint16_t RTIMER11   : 1;\r
+  __IO uint16_t RTIMER12   : 1;\r
+  __IO uint16_t RTIMER13   : 1;\r
+  __IO uint16_t RTIMER14   : 1;\r
+  __IO uint16_t RTIMER15   : 1;\r
+} stc_usb_hrtimer_field_t;\r
+\r
+typedef struct stc_usb_hrtimer0_field\r
+{\r
+  __IO  uint8_t RTIMER00   : 1;\r
+  __IO  uint8_t RTIMER01   : 1;\r
+  __IO  uint8_t RTIMER02   : 1;\r
+  __IO  uint8_t RTIMER03   : 1;\r
+  __IO  uint8_t RTIMER04   : 1;\r
+  __IO  uint8_t RTIMER05   : 1;\r
+  __IO  uint8_t RTIMER06   : 1;\r
+  __IO  uint8_t RTIMER07   : 1;\r
+} stc_usb_hrtimer0_field_t;\r
+\r
+typedef struct stc_usb_hrtimer1_field\r
+{\r
+  __IO  uint8_t RTIMER10   : 1;\r
+  __IO  uint8_t RTIMER11   : 1;\r
+  __IO  uint8_t RTIMER12   : 1;\r
+  __IO  uint8_t RTIMER13   : 1;\r
+  __IO  uint8_t RTIMER14   : 1;\r
+  __IO  uint8_t RTIMER15   : 1;\r
+  __IO  uint8_t RTIMER16   : 1;\r
+  __IO  uint8_t RTIMER17   : 1;\r
+} stc_usb_hrtimer1_field_t;\r
+\r
+typedef struct stc_usb_hrtimer2_field\r
+{\r
+  __IO  uint8_t RTIMER20   : 1;\r
+  __IO  uint8_t RTIMER21   : 1;\r
+  __IO  uint8_t RTIMER22   : 1;\r
+} stc_usb_hrtimer2_field_t;\r
+\r
+typedef struct stc_usb_hadr_field\r
+{\r
+  __IO  uint8_t ADDRESS0   : 1;\r
+  __IO  uint8_t ADDRESS1   : 1;\r
+  __IO  uint8_t ADDRESS2   : 1;\r
+  __IO  uint8_t ADDRESS3   : 1;\r
+  __IO  uint8_t ADDRESS4   : 1;\r
+  __IO  uint8_t ADDRESS5   : 1;\r
+  __IO  uint8_t ADDRESS6   : 1;\r
+} stc_usb_hadr_field_t;\r
+\r
+typedef struct stc_usb_heof_field\r
+{\r
+  __IO uint16_t EOF0       : 1;\r
+  __IO uint16_t EOF1       : 1;\r
+  __IO uint16_t EOF2       : 1;\r
+  __IO uint16_t EOF3       : 1;\r
+  __IO uint16_t EOF4       : 1;\r
+  __IO uint16_t EOF5       : 1;\r
+  __IO uint16_t EOF6       : 1;\r
+  __IO uint16_t EOF7       : 1;\r
+  __IO uint16_t EOF8       : 1;\r
+  __IO uint16_t EOF9       : 1;\r
+  __IO uint16_t EOF10      : 1;\r
+  __IO uint16_t EOF11      : 1;\r
+  __IO uint16_t EOF12      : 1;\r
+  __IO uint16_t EOF13      : 1;\r
+  __IO uint16_t EOF14      : 1;\r
+  __IO uint16_t EOF15      : 1;\r
+} stc_usb_heof_field_t;\r
+\r
+typedef struct stc_usb_heof0_field\r
+{\r
+  __IO  uint8_t EOF00      : 1;\r
+  __IO  uint8_t EOF01      : 1;\r
+  __IO  uint8_t EOF02      : 1;\r
+  __IO  uint8_t EOF03      : 1;\r
+  __IO  uint8_t EOF04      : 1;\r
+  __IO  uint8_t EOF05      : 1;\r
+  __IO  uint8_t EOF06      : 1;\r
+  __IO  uint8_t EOF07      : 1;\r
+} stc_usb_heof0_field_t;\r
+\r
+typedef struct stc_usb_heof1_field\r
+{\r
+  __IO  uint8_t EOF10      : 1;\r
+  __IO  uint8_t EOF11      : 1;\r
+  __IO  uint8_t EOF12      : 1;\r
+  __IO  uint8_t EOF13      : 1;\r
+  __IO  uint8_t EOF14      : 1;\r
+  __IO  uint8_t EOF15      : 1;\r
+} stc_usb_heof1_field_t;\r
+\r
+typedef struct stc_usb_hframe_field\r
+{\r
+  __IO uint16_t FRAME0     : 1;\r
+  __IO uint16_t FRAME1     : 1;\r
+  __IO uint16_t FRAME2     : 1;\r
+  __IO uint16_t FRAME3     : 1;\r
+  __IO uint16_t FRAME4     : 1;\r
+  __IO uint16_t FRAME5     : 1;\r
+  __IO uint16_t FRAME6     : 1;\r
+  __IO uint16_t FRAME7     : 1;\r
+  __IO uint16_t FRAME8     : 1;\r
+  __IO uint16_t FRAME9     : 1;\r
+  __IO uint16_t FRAME10    : 1;\r
+} stc_usb_hframe_field_t;\r
+\r
+typedef struct stc_usb_hframe0_field\r
+{\r
+  __IO  uint8_t FRAME00    : 1;\r
+  __IO  uint8_t FRAME01    : 1;\r
+  __IO  uint8_t FRAME02    : 1;\r
+  __IO  uint8_t FRAME03    : 1;\r
+  __IO  uint8_t FRAME04    : 1;\r
+  __IO  uint8_t FRAME05    : 1;\r
+  __IO  uint8_t FRAME06    : 1;\r
+  __IO  uint8_t FRAME07    : 1;\r
+} stc_usb_hframe0_field_t;\r
+\r
+typedef struct stc_usb_hframe1_field\r
+{\r
+  __IO  uint8_t FRAME10    : 1;\r
+  __IO  uint8_t FRAME11    : 1;\r
+  __IO  uint8_t FRAME12    : 1;\r
+  __IO  uint8_t FRAME13    : 1;\r
+} stc_usb_hframe1_field_t;\r
+\r
+typedef struct stc_usb_htoken_field\r
+{\r
+  __IO  uint8_t ENDPT0     : 1;\r
+  __IO  uint8_t ENDPT1     : 1;\r
+  __IO  uint8_t ENDPT2     : 1;\r
+  __IO  uint8_t ENDPT3     : 1;\r
+  __IO  uint8_t TKNEN0     : 1;\r
+  __IO  uint8_t TKNEN1     : 1;\r
+  __IO  uint8_t TKNEN2     : 1;\r
+  __IO  uint8_t TGGL       : 1;\r
+} stc_usb_htoken_field_t;\r
+\r
+typedef struct stc_usb_udcc_field\r
+{\r
+  __IO uint16_t PWC        : 1;\r
+  __IO uint16_t RFBK       : 1;\r
+       uint16_t RESERVED1  : 1;\r
+  __IO uint16_t STALCLREN  : 1;\r
+  __IO uint16_t USTP       : 1;\r
+  __IO uint16_t HCONX      : 1;\r
+  __IO uint16_t RESUM      : 1;\r
+  __IO uint16_t RST        : 1;\r
+} stc_usb_udcc_field_t;\r
+\r
+typedef struct stc_usb_ep0c_field\r
+{\r
+  __IO uint16_t PKS00      : 1;\r
+  __IO uint16_t PKS01      : 1;\r
+  __IO uint16_t PKS02      : 1;\r
+  __IO uint16_t PKS03      : 1;\r
+  __IO uint16_t PKS04      : 1;\r
+  __IO uint16_t PKS05      : 1;\r
+  __IO uint16_t PKS06      : 1;\r
+       uint16_t RESERVED1  : 2;\r
+  __IO uint16_t STAL       : 1;\r
+} stc_usb_ep0c_field_t;\r
+\r
+typedef struct stc_usb_ep1c_field\r
+{\r
+  __IO uint16_t PKS10      : 1;\r
+  __IO uint16_t PKS11      : 1;\r
+  __IO uint16_t PKS12      : 1;\r
+  __IO uint16_t PKS13      : 1;\r
+  __IO uint16_t PKS14      : 1;\r
+  __IO uint16_t PKS15      : 1;\r
+  __IO uint16_t PKS16      : 1;\r
+  __IO uint16_t PKS17      : 1;\r
+  __IO uint16_t PKS18      : 1;\r
+  __IO uint16_t STAL       : 1;\r
+  __IO uint16_t NULE       : 1;\r
+  __IO uint16_t DMAE       : 1;\r
+  __IO uint16_t DIR        : 1;\r
+  __IO uint16_t TYPE0      : 1;\r
+  __IO uint16_t TYPE1      : 1;\r
+  __IO uint16_t EPEN       : 1;\r
+} stc_usb_ep1c_field_t;\r
+\r
+typedef struct stc_usb_ep2c_field\r
+{\r
+  __IO uint16_t PKS20      : 1;\r
+  __IO uint16_t PKS21      : 1;\r
+  __IO uint16_t PKS22      : 1;\r
+  __IO uint16_t PKS23      : 1;\r
+  __IO uint16_t PKS24      : 1;\r
+  __IO uint16_t PKS25      : 1;\r
+  __IO uint16_t PKS26      : 1;\r
+       uint16_t RESERVED1  : 2;\r
+  __IO uint16_t STAL       : 1;\r
+  __IO uint16_t NULE       : 1;\r
+  __IO uint16_t DMAE       : 1;\r
+  __IO uint16_t DIR        : 1;\r
+  __IO uint16_t TYPE0      : 1;\r
+  __IO uint16_t TYPE1      : 1;\r
+  __IO uint16_t EPEN       : 1;\r
+} stc_usb_ep2c_field_t;\r
+\r
+typedef struct stc_usb_ep3c_field\r
+{\r
+  __IO uint16_t PKS30      : 1;\r
+  __IO uint16_t PKS31      : 1;\r
+  __IO uint16_t PKS32      : 1;\r
+  __IO uint16_t PKS33      : 1;\r
+  __IO uint16_t PKS34      : 1;\r
+  __IO uint16_t PKS35      : 1;\r
+  __IO uint16_t PKS36      : 1;\r
+       uint16_t RESERVED1  : 2;\r
+  __IO uint16_t STAL       : 1;\r
+  __IO uint16_t NULE       : 1;\r
+  __IO uint16_t DMAE       : 1;\r
+  __IO uint16_t DIR        : 1;\r
+  __IO uint16_t TYPE0      : 1;\r
+  __IO uint16_t TYPE1      : 1;\r
+  __IO uint16_t EPEN       : 1;\r
+} stc_usb_ep3c_field_t;\r
+\r
+typedef struct stc_usb_ep4c_field\r
+{\r
+  __IO uint16_t PKS40      : 1;\r
+  __IO uint16_t PKS41      : 1;\r
+  __IO uint16_t PKS42      : 1;\r
+  __IO uint16_t PKS43      : 1;\r
+  __IO uint16_t PKS44      : 1;\r
+  __IO uint16_t PKS45      : 1;\r
+  __IO uint16_t PKS46      : 1;\r
+       uint16_t RESERVED1  : 2;\r
+  __IO uint16_t STAL       : 1;\r
+  __IO uint16_t NULE       : 1;\r
+  __IO uint16_t DMAE       : 1;\r
+  __IO uint16_t DIR        : 1;\r
+  __IO uint16_t TYPE0      : 1;\r
+  __IO uint16_t TYPE1      : 1;\r
+  __IO uint16_t EPEN       : 1;\r
+} stc_usb_ep4c_field_t;\r
+\r
+typedef struct stc_usb_ep5c_field\r
+{\r
+  __IO uint16_t PKS50      : 1;\r
+  __IO uint16_t PKS51      : 1;\r
+  __IO uint16_t PKS52      : 1;\r
+  __IO uint16_t PKS53      : 1;\r
+  __IO uint16_t PKS54      : 1;\r
+  __IO uint16_t PKS55      : 1;\r
+  __IO uint16_t PKS56      : 1;\r
+       uint16_t RESERVED1  : 2;\r
+  __IO uint16_t STAL       : 1;\r
+  __IO uint16_t NULE       : 1;\r
+  __IO uint16_t DMAE       : 1;\r
+  __IO uint16_t DIR        : 1;\r
+  __IO uint16_t TYPE0      : 1;\r
+  __IO uint16_t TYPE1      : 1;\r
+  __IO uint16_t EPEN       : 1;\r
+} stc_usb_ep5c_field_t;\r
+\r
+typedef struct stc_usb_tmsp_field\r
+{\r
+  __IO uint16_t TMSP0      : 1;\r
+  __IO uint16_t TMSP1      : 1;\r
+  __IO uint16_t TMSP2      : 1;\r
+  __IO uint16_t TMSP3      : 1;\r
+  __IO uint16_t TMSP4      : 1;\r
+  __IO uint16_t TMSP5      : 1;\r
+  __IO uint16_t TMSP6      : 1;\r
+  __IO uint16_t TMSP7      : 1;\r
+  __IO uint16_t TMSP8      : 1;\r
+  __IO uint16_t TMSP9      : 1;\r
+  __IO uint16_t TMSP10     : 1;\r
+} stc_usb_tmsp_field_t;\r
+\r
+typedef struct stc_usb_udcs_field\r
+{\r
+  __IO  uint8_t CONF       : 1;\r
+  __IO  uint8_t SETP       : 1;\r
+  __IO  uint8_t WKUP       : 1;\r
+  __IO  uint8_t BRST       : 1;\r
+  __IO  uint8_t SOF        : 1;\r
+  __IO  uint8_t SUSP       : 1;\r
+} stc_usb_udcs_field_t;\r
+\r
+typedef struct stc_usb_udcie_field\r
+{\r
+  __IO  uint8_t CONFIE     : 1;\r
+  __IO  uint8_t CONFN      : 1;\r
+  __IO  uint8_t WKUPIE     : 1;\r
+  __IO  uint8_t BRSTIE     : 1;\r
+  __IO  uint8_t SOFIE      : 1;\r
+  __IO  uint8_t SUSPIE     : 1;\r
+} stc_usb_udcie_field_t;\r
+\r
+typedef struct stc_usb_ep0is_field\r
+{\r
+       uint16_t RESERVED1  : 10;\r
+  __IO uint16_t DRQI       : 1;\r
+       uint16_t RESERVED2  : 3;\r
+  __IO uint16_t DRQIIE     : 1;\r
+  __IO uint16_t BFINI      : 1;\r
+} stc_usb_ep0is_field_t;\r
+\r
+typedef struct stc_usb_ep0os_field\r
+{\r
+  __IO uint16_t SIZE0      : 1;\r
+  __IO uint16_t SIZE1      : 1;\r
+  __IO uint16_t SIZE2      : 1;\r
+  __IO uint16_t SIZE3      : 1;\r
+  __IO uint16_t SIZE4      : 1;\r
+  __IO uint16_t SIZE5      : 1;\r
+  __IO uint16_t SIZE6      : 1;\r
+       uint16_t RESERVED1  : 2;\r
+  __IO uint16_t SPK        : 1;\r
+  __IO uint16_t DRQO       : 1;\r
+       uint16_t RESERVED2  : 2;\r
+  __IO uint16_t SPKIE      : 1;\r
+  __IO uint16_t DRQOIE     : 1;\r
+  __IO uint16_t BFINI      : 1;\r
+} stc_usb_ep0os_field_t;\r
+\r
+typedef struct stc_usb_ep1s_field\r
+{\r
+  __IO uint16_t SIZE10     : 1;\r
+  __IO uint16_t SIZE11     : 1;\r
+  __IO uint16_t SIZE12     : 1;\r
+  __IO uint16_t SIZE13     : 1;\r
+  __IO uint16_t SIZE14     : 1;\r
+  __IO uint16_t SIZE15     : 1;\r
+  __IO uint16_t SIZE16     : 1;\r
+  __IO uint16_t SIZE17     : 1;\r
+  __IO uint16_t SIZE18     : 1;\r
+  __IO uint16_t SPK        : 1;\r
+  __IO uint16_t DRQ        : 1;\r
+  __IO uint16_t BUSY       : 1;\r
+       uint16_t RESERVED1  : 1;\r
+  __IO uint16_t SPKIE      : 1;\r
+  __IO uint16_t DRQIE      : 1;\r
+  __IO uint16_t BFINI      : 1;\r
+} stc_usb_ep1s_field_t;\r
+\r
+typedef struct stc_usb_ep2s_field\r
+{\r
+  __IO uint16_t SIZE20     : 1;\r
+  __IO uint16_t SIZE21     : 1;\r
+  __IO uint16_t SIZE22     : 1;\r
+  __IO uint16_t SIZE23     : 1;\r
+  __IO uint16_t SIZE24     : 1;\r
+  __IO uint16_t SIZE25     : 1;\r
+  __IO uint16_t SIZE26     : 1;\r
+       uint16_t RESERVED1  : 2;\r
+  __IO uint16_t SPK        : 1;\r
+  __IO uint16_t DRQ        : 1;\r
+  __IO uint16_t BUSY       : 1;\r
+       uint16_t RESERVED2  : 1;\r
+  __IO uint16_t SPKIE      : 1;\r
+  __IO uint16_t DRQIE      : 1;\r
+  __IO uint16_t BFINI      : 1;\r
+} stc_usb_ep2s_field_t;\r
+\r
+typedef struct stc_usb_ep4s_field\r
+{\r
+  __IO uint16_t SIZE40     : 1;\r
+  __IO uint16_t SIZE41     : 1;\r
+  __IO uint16_t SIZE42     : 1;\r
+  __IO uint16_t SIZE43     : 1;\r
+  __IO uint16_t SIZE44     : 1;\r
+  __IO uint16_t SIZE45     : 1;\r
+  __IO uint16_t SIZE46     : 1;\r
+       uint16_t RESERVED1  : 2;\r
+  __IO uint16_t SPK        : 1;\r
+  __IO uint16_t DRQ        : 1;\r
+  __IO uint16_t BUSY       : 1;\r
+       uint16_t RESERVED2  : 1;\r
+  __IO uint16_t SPKIE      : 1;\r
+  __IO uint16_t DRQIE      : 1;\r
+  __IO uint16_t BFINI      : 1;\r
+} stc_usb_ep4s_field_t;\r
+\r
+typedef struct stc_usb_ep5s_field\r
+{\r
+  __IO uint16_t SIZE50     : 1;\r
+  __IO uint16_t SIZE51     : 1;\r
+  __IO uint16_t SIZE52     : 1;\r
+  __IO uint16_t SIZE53     : 1;\r
+  __IO uint16_t SIZE54     : 1;\r
+  __IO uint16_t SIZE55     : 1;\r
+  __IO uint16_t SIZE56     : 1;\r
+       uint16_t RESERVED1  : 2;\r
+  __IO uint16_t SPK        : 1;\r
+  __IO uint16_t DRQ        : 1;\r
+  __IO uint16_t BUSY       : 1;\r
+       uint16_t RESERVED2  : 1;\r
+  __IO uint16_t SPKIE      : 1;\r
+  __IO uint16_t DRQIE      : 1;\r
+  __IO uint16_t BFINI      : 1;\r
+} stc_usb_ep5s_field_t;\r
+\r
+/******************************************************************************\r
+ * DMAC_MODULE\r
+ ******************************************************************************/\r
+/* DMAC_MODULE register bit fields */\r
+typedef struct stc_dmac_dmacr_field\r
+{\r
+       uint32_t RESERVED1  : 24;\r
+  __IO uint32_t DH0        : 1;\r
+  __IO uint32_t DH1        : 1;\r
+  __IO uint32_t DH2        : 1;\r
+  __IO uint32_t DH3        : 1;\r
+  __IO uint32_t PR         : 1;\r
+       uint32_t RESERVED2  : 1;\r
+  __IO uint32_t DS         : 1;\r
+  __IO uint32_t DE         : 1;\r
+} stc_dmac_dmacr_field_t;\r
+\r
+typedef struct stc_dmac_dmaca0_field\r
+{\r
+  __IO uint32_t TC0        : 1;\r
+  __IO uint32_t TC1        : 1;\r
+  __IO uint32_t TC2        : 1;\r
+  __IO uint32_t TC3        : 1;\r
+  __IO uint32_t TC4        : 1;\r
+  __IO uint32_t TC5        : 1;\r
+  __IO uint32_t TC6        : 1;\r
+  __IO uint32_t TC7        : 1;\r
+  __IO uint32_t TC8        : 1;\r
+  __IO uint32_t TC9        : 1;\r
+  __IO uint32_t TC10       : 1;\r
+  __IO uint32_t TC11       : 1;\r
+  __IO uint32_t TC12       : 1;\r
+  __IO uint32_t TC13       : 1;\r
+  __IO uint32_t TC14       : 1;\r
+  __IO uint32_t TC15       : 1;\r
+  __IO uint32_t BC0        : 1;\r
+  __IO uint32_t BC1        : 1;\r
+  __IO uint32_t BC2        : 1;\r
+  __IO uint32_t BC3        : 1;\r
+       uint32_t RESERVED1  : 3;\r
+  __IO uint32_t IS0        : 1;\r
+  __IO uint32_t IS1        : 1;\r
+  __IO uint32_t IS2        : 1;\r
+  __IO uint32_t IS3        : 1;\r
+  __IO uint32_t IS4        : 1;\r
+  __IO uint32_t IS5        : 1;\r
+  __IO uint32_t ST         : 1;\r
+  __IO uint32_t PB         : 1;\r
+  __IO uint32_t EB         : 1;\r
+} stc_dmac_dmaca0_field_t;\r
+\r
+typedef struct stc_dmac_dmacb0_field\r
+{\r
+  __IO uint32_t EM         : 1;\r
+       uint32_t RESERVED1  : 15;\r
+  __IO uint32_t SS0        : 1;\r
+  __IO uint32_t SS1        : 1;\r
+  __IO uint32_t SS2        : 1;\r
+  __IO uint32_t CI         : 1;\r
+  __IO uint32_t EI         : 1;\r
+  __IO uint32_t RD         : 1;\r
+  __IO uint32_t RS         : 1;\r
+  __IO uint32_t RC         : 1;\r
+  __IO uint32_t FD         : 1;\r
+  __IO uint32_t FS         : 1;\r
+  __IO uint32_t TW0        : 1;\r
+  __IO uint32_t TW1        : 1;\r
+  __IO uint32_t MS0        : 1;\r
+  __IO uint32_t MS1        : 1;\r
+} stc_dmac_dmacb0_field_t;\r
+\r
+typedef struct stc_dmac_dmaca1_field\r
+{\r
+  __IO uint32_t TC0        : 1;\r
+  __IO uint32_t TC1        : 1;\r
+  __IO uint32_t TC2        : 1;\r
+  __IO uint32_t TC3        : 1;\r
+  __IO uint32_t TC4        : 1;\r
+  __IO uint32_t TC5        : 1;\r
+  __IO uint32_t TC6        : 1;\r
+  __IO uint32_t TC7        : 1;\r
+  __IO uint32_t TC8        : 1;\r
+  __IO uint32_t TC9        : 1;\r
+  __IO uint32_t TC10       : 1;\r
+  __IO uint32_t TC11       : 1;\r
+  __IO uint32_t TC12       : 1;\r
+  __IO uint32_t TC13       : 1;\r
+  __IO uint32_t TC14       : 1;\r
+  __IO uint32_t TC15       : 1;\r
+  __IO uint32_t BC0        : 1;\r
+  __IO uint32_t BC1        : 1;\r
+  __IO uint32_t BC2        : 1;\r
+  __IO uint32_t BC3        : 1;\r
+       uint32_t RESERVED1  : 3;\r
+  __IO uint32_t IS0        : 1;\r
+  __IO uint32_t IS1        : 1;\r
+  __IO uint32_t IS2        : 1;\r
+  __IO uint32_t IS3        : 1;\r
+  __IO uint32_t IS4        : 1;\r
+  __IO uint32_t IS5        : 1;\r
+  __IO uint32_t ST         : 1;\r
+  __IO uint32_t PB         : 1;\r
+  __IO uint32_t EB         : 1;\r
+} stc_dmac_dmaca1_field_t;\r
+\r
+typedef struct stc_dmac_dmacb1_field\r
+{\r
+  __IO uint32_t EM         : 1;\r
+       uint32_t RESERVED1  : 15;\r
+  __IO uint32_t SS0        : 1;\r
+  __IO uint32_t SS1        : 1;\r
+  __IO uint32_t SS2        : 1;\r
+  __IO uint32_t CI         : 1;\r
+  __IO uint32_t EI         : 1;\r
+  __IO uint32_t RD         : 1;\r
+  __IO uint32_t RS         : 1;\r
+  __IO uint32_t RC         : 1;\r
+  __IO uint32_t FD         : 1;\r
+  __IO uint32_t FS         : 1;\r
+  __IO uint32_t TW0        : 1;\r
+  __IO uint32_t TW1        : 1;\r
+  __IO uint32_t MS0        : 1;\r
+  __IO uint32_t MS1        : 1;\r
+} stc_dmac_dmacb1_field_t;\r
+\r
+typedef struct stc_dmac_dmaca2_field\r
+{\r
+  __IO uint32_t TC0        : 1;\r
+  __IO uint32_t TC1        : 1;\r
+  __IO uint32_t TC2        : 1;\r
+  __IO uint32_t TC3        : 1;\r
+  __IO uint32_t TC4        : 1;\r
+  __IO uint32_t TC5        : 1;\r
+  __IO uint32_t TC6        : 1;\r
+  __IO uint32_t TC7        : 1;\r
+  __IO uint32_t TC8        : 1;\r
+  __IO uint32_t TC9        : 1;\r
+  __IO uint32_t TC10       : 1;\r
+  __IO uint32_t TC11       : 1;\r
+  __IO uint32_t TC12       : 1;\r
+  __IO uint32_t TC13       : 1;\r
+  __IO uint32_t TC14       : 1;\r
+  __IO uint32_t TC15       : 1;\r
+  __IO uint32_t BC0        : 1;\r
+  __IO uint32_t BC1        : 1;\r
+  __IO uint32_t BC2        : 1;\r
+  __IO uint32_t BC3        : 1;\r
+       uint32_t RESERVED1  : 3;\r
+  __IO uint32_t IS0        : 1;\r
+  __IO uint32_t IS1        : 1;\r
+  __IO uint32_t IS2        : 1;\r
+  __IO uint32_t IS3        : 1;\r
+  __IO uint32_t IS4        : 1;\r
+  __IO uint32_t IS5        : 1;\r
+  __IO uint32_t ST         : 1;\r
+  __IO uint32_t PB         : 1;\r
+  __IO uint32_t EB         : 1;\r
+} stc_dmac_dmaca2_field_t;\r
+\r
+typedef struct stc_dmac_dmacb2_field\r
+{\r
+  __IO uint32_t EM         : 1;\r
+       uint32_t RESERVED1  : 15;\r
+  __IO uint32_t SS0        : 1;\r
+  __IO uint32_t SS1        : 1;\r
+  __IO uint32_t SS2        : 1;\r
+  __IO uint32_t CI         : 1;\r
+  __IO uint32_t EI         : 1;\r
+  __IO uint32_t RD         : 1;\r
+  __IO uint32_t RS         : 1;\r
+  __IO uint32_t RC         : 1;\r
+  __IO uint32_t FD         : 1;\r
+  __IO uint32_t FS         : 1;\r
+  __IO uint32_t TW0        : 1;\r
+  __IO uint32_t TW1        : 1;\r
+  __IO uint32_t MS0        : 1;\r
+  __IO uint32_t MS1        : 1;\r
+} stc_dmac_dmacb2_field_t;\r
+\r
+typedef struct stc_dmac_dmaca3_field\r
+{\r
+  __IO uint32_t TC0        : 1;\r
+  __IO uint32_t TC1        : 1;\r
+  __IO uint32_t TC2        : 1;\r
+  __IO uint32_t TC3        : 1;\r
+  __IO uint32_t TC4        : 1;\r
+  __IO uint32_t TC5        : 1;\r
+  __IO uint32_t TC6        : 1;\r
+  __IO uint32_t TC7        : 1;\r
+  __IO uint32_t TC8        : 1;\r
+  __IO uint32_t TC9        : 1;\r
+  __IO uint32_t TC10       : 1;\r
+  __IO uint32_t TC11       : 1;\r
+  __IO uint32_t TC12       : 1;\r
+  __IO uint32_t TC13       : 1;\r
+  __IO uint32_t TC14       : 1;\r
+  __IO uint32_t TC15       : 1;\r
+  __IO uint32_t BC0        : 1;\r
+  __IO uint32_t BC1        : 1;\r
+  __IO uint32_t BC2        : 1;\r
+  __IO uint32_t BC3        : 1;\r
+       uint32_t RESERVED1  : 3;\r
+  __IO uint32_t IS0        : 1;\r
+  __IO uint32_t IS1        : 1;\r
+  __IO uint32_t IS2        : 1;\r
+  __IO uint32_t IS3        : 1;\r
+  __IO uint32_t IS4        : 1;\r
+  __IO uint32_t IS5        : 1;\r
+  __IO uint32_t ST         : 1;\r
+  __IO uint32_t PB         : 1;\r
+  __IO uint32_t EB         : 1;\r
+} stc_dmac_dmaca3_field_t;\r
+\r
+typedef struct stc_dmac_dmacb3_field\r
+{\r
+  __IO uint32_t EM         : 1;\r
+       uint32_t RESERVED1  : 15;\r
+  __IO uint32_t SS0        : 1;\r
+  __IO uint32_t SS1        : 1;\r
+  __IO uint32_t SS2        : 1;\r
+  __IO uint32_t CI         : 1;\r
+  __IO uint32_t EI         : 1;\r
+  __IO uint32_t RD         : 1;\r
+  __IO uint32_t RS         : 1;\r
+  __IO uint32_t RC         : 1;\r
+  __IO uint32_t FD         : 1;\r
+  __IO uint32_t FS         : 1;\r
+  __IO uint32_t TW0        : 1;\r
+  __IO uint32_t TW1        : 1;\r
+  __IO uint32_t MS0        : 1;\r
+  __IO uint32_t MS1        : 1;\r
+} stc_dmac_dmacb3_field_t;\r
+\r
+typedef struct stc_dmac_dmaca4_field\r
+{\r
+  __IO uint32_t TC0        : 1;\r
+  __IO uint32_t TC1        : 1;\r
+  __IO uint32_t TC2        : 1;\r
+  __IO uint32_t TC3        : 1;\r
+  __IO uint32_t TC4        : 1;\r
+  __IO uint32_t TC5        : 1;\r
+  __IO uint32_t TC6        : 1;\r
+  __IO uint32_t TC7        : 1;\r
+  __IO uint32_t TC8        : 1;\r
+  __IO uint32_t TC9        : 1;\r
+  __IO uint32_t TC10       : 1;\r
+  __IO uint32_t TC11       : 1;\r
+  __IO uint32_t TC12       : 1;\r
+  __IO uint32_t TC13       : 1;\r
+  __IO uint32_t TC14       : 1;\r
+  __IO uint32_t TC15       : 1;\r
+  __IO uint32_t BC0        : 1;\r
+  __IO uint32_t BC1        : 1;\r
+  __IO uint32_t BC2        : 1;\r
+  __IO uint32_t BC3        : 1;\r
+       uint32_t RESERVED1  : 3;\r
+  __IO uint32_t IS0        : 1;\r
+  __IO uint32_t IS1        : 1;\r
+  __IO uint32_t IS2        : 1;\r
+  __IO uint32_t IS3        : 1;\r
+  __IO uint32_t IS4        : 1;\r
+  __IO uint32_t IS5        : 1;\r
+  __IO uint32_t ST         : 1;\r
+  __IO uint32_t PB         : 1;\r
+  __IO uint32_t EB         : 1;\r
+} stc_dmac_dmaca4_field_t;\r
+\r
+typedef struct stc_dmac_dmacb4_field\r
+{\r
+  __IO uint32_t EM         : 1;\r
+       uint32_t RESERVED1  : 15;\r
+  __IO uint32_t SS0        : 1;\r
+  __IO uint32_t SS1        : 1;\r
+  __IO uint32_t SS2        : 1;\r
+  __IO uint32_t CI         : 1;\r
+  __IO uint32_t EI         : 1;\r
+  __IO uint32_t RD         : 1;\r
+  __IO uint32_t RS         : 1;\r
+  __IO uint32_t RC         : 1;\r
+  __IO uint32_t FD         : 1;\r
+  __IO uint32_t FS         : 1;\r
+  __IO uint32_t TW0        : 1;\r
+  __IO uint32_t TW1        : 1;\r
+  __IO uint32_t MS0        : 1;\r
+  __IO uint32_t MS1        : 1;\r
+} stc_dmac_dmacb4_field_t;\r
+\r
+typedef struct stc_dmac_dmaca5_field\r
+{\r
+  __IO uint32_t TC0        : 1;\r
+  __IO uint32_t TC1        : 1;\r
+  __IO uint32_t TC2        : 1;\r
+  __IO uint32_t TC3        : 1;\r
+  __IO uint32_t TC4        : 1;\r
+  __IO uint32_t TC5        : 1;\r
+  __IO uint32_t TC6        : 1;\r
+  __IO uint32_t TC7        : 1;\r
+  __IO uint32_t TC8        : 1;\r
+  __IO uint32_t TC9        : 1;\r
+  __IO uint32_t TC10       : 1;\r
+  __IO uint32_t TC11       : 1;\r
+  __IO uint32_t TC12       : 1;\r
+  __IO uint32_t TC13       : 1;\r
+  __IO uint32_t TC14       : 1;\r
+  __IO uint32_t TC15       : 1;\r
+  __IO uint32_t BC0        : 1;\r
+  __IO uint32_t BC1        : 1;\r
+  __IO uint32_t BC2        : 1;\r
+  __IO uint32_t BC3        : 1;\r
+       uint32_t RESERVED1  : 3;\r
+  __IO uint32_t IS0        : 1;\r
+  __IO uint32_t IS1        : 1;\r
+  __IO uint32_t IS2        : 1;\r
+  __IO uint32_t IS3        : 1;\r
+  __IO uint32_t IS4        : 1;\r
+  __IO uint32_t IS5        : 1;\r
+  __IO uint32_t ST         : 1;\r
+  __IO uint32_t PB         : 1;\r
+  __IO uint32_t EB         : 1;\r
+} stc_dmac_dmaca5_field_t;\r
+\r
+typedef struct stc_dmac_dmacb5_field\r
+{\r
+  __IO uint32_t EM         : 1;\r
+       uint32_t RESERVED1  : 15;\r
+  __IO uint32_t SS0        : 1;\r
+  __IO uint32_t SS1        : 1;\r
+  __IO uint32_t SS2        : 1;\r
+  __IO uint32_t CI         : 1;\r
+  __IO uint32_t EI         : 1;\r
+  __IO uint32_t RD         : 1;\r
+  __IO uint32_t RS         : 1;\r
+  __IO uint32_t RC         : 1;\r
+  __IO uint32_t FD         : 1;\r
+  __IO uint32_t FS         : 1;\r
+  __IO uint32_t TW0        : 1;\r
+  __IO uint32_t TW1        : 1;\r
+  __IO uint32_t MS0        : 1;\r
+  __IO uint32_t MS1        : 1;\r
+} stc_dmac_dmacb5_field_t;\r
+\r
+typedef struct stc_dmac_dmaca6_field\r
+{\r
+  __IO uint32_t TC0        : 1;\r
+  __IO uint32_t TC1        : 1;\r
+  __IO uint32_t TC2        : 1;\r
+  __IO uint32_t TC3        : 1;\r
+  __IO uint32_t TC4        : 1;\r
+  __IO uint32_t TC5        : 1;\r
+  __IO uint32_t TC6        : 1;\r
+  __IO uint32_t TC7        : 1;\r
+  __IO uint32_t TC8        : 1;\r
+  __IO uint32_t TC9        : 1;\r
+  __IO uint32_t TC10       : 1;\r
+  __IO uint32_t TC11       : 1;\r
+  __IO uint32_t TC12       : 1;\r
+  __IO uint32_t TC13       : 1;\r
+  __IO uint32_t TC14       : 1;\r
+  __IO uint32_t TC15       : 1;\r
+  __IO uint32_t BC0        : 1;\r
+  __IO uint32_t BC1        : 1;\r
+  __IO uint32_t BC2        : 1;\r
+  __IO uint32_t BC3        : 1;\r
+       uint32_t RESERVED1  : 3;\r
+  __IO uint32_t IS0        : 1;\r
+  __IO uint32_t IS1        : 1;\r
+  __IO uint32_t IS2        : 1;\r
+  __IO uint32_t IS3        : 1;\r
+  __IO uint32_t IS4        : 1;\r
+  __IO uint32_t IS5        : 1;\r
+  __IO uint32_t ST         : 1;\r
+  __IO uint32_t PB         : 1;\r
+  __IO uint32_t EB         : 1;\r
+} stc_dmac_dmaca6_field_t;\r
+\r
+typedef struct stc_dmac_dmacb6_field\r
+{\r
+  __IO uint32_t EM         : 1;\r
+       uint32_t RESERVED1  : 15;\r
+  __IO uint32_t SS0        : 1;\r
+  __IO uint32_t SS1        : 1;\r
+  __IO uint32_t SS2        : 1;\r
+  __IO uint32_t CI         : 1;\r
+  __IO uint32_t EI         : 1;\r
+  __IO uint32_t RD         : 1;\r
+  __IO uint32_t RS         : 1;\r
+  __IO uint32_t RC         : 1;\r
+  __IO uint32_t FD         : 1;\r
+  __IO uint32_t FS         : 1;\r
+  __IO uint32_t TW0        : 1;\r
+  __IO uint32_t TW1        : 1;\r
+  __IO uint32_t MS0        : 1;\r
+  __IO uint32_t MS1        : 1;\r
+} stc_dmac_dmacb6_field_t;\r
+\r
+typedef struct stc_dmac_dmaca7_field\r
+{\r
+  __IO uint32_t TC0        : 1;\r
+  __IO uint32_t TC1        : 1;\r
+  __IO uint32_t TC2        : 1;\r
+  __IO uint32_t TC3        : 1;\r
+  __IO uint32_t TC4        : 1;\r
+  __IO uint32_t TC5        : 1;\r
+  __IO uint32_t TC6        : 1;\r
+  __IO uint32_t TC7        : 1;\r
+  __IO uint32_t TC8        : 1;\r
+  __IO uint32_t TC9        : 1;\r
+  __IO uint32_t TC10       : 1;\r
+  __IO uint32_t TC11       : 1;\r
+  __IO uint32_t TC12       : 1;\r
+  __IO uint32_t TC13       : 1;\r
+  __IO uint32_t TC14       : 1;\r
+  __IO uint32_t TC15       : 1;\r
+  __IO uint32_t BC0        : 1;\r
+  __IO uint32_t BC1        : 1;\r
+  __IO uint32_t BC2        : 1;\r
+  __IO uint32_t BC3        : 1;\r
+       uint32_t RESERVED1  : 3;\r
+  __IO uint32_t IS0        : 1;\r
+  __IO uint32_t IS1        : 1;\r
+  __IO uint32_t IS2        : 1;\r
+  __IO uint32_t IS3        : 1;\r
+  __IO uint32_t IS4        : 1;\r
+  __IO uint32_t IS5        : 1;\r
+  __IO uint32_t ST         : 1;\r
+  __IO uint32_t PB         : 1;\r
+  __IO uint32_t EB         : 1;\r
+} stc_dmac_dmaca7_field_t;\r
+\r
+typedef struct stc_dmac_dmacb7_field\r
+{\r
+  __IO uint32_t EM         : 1;\r
+       uint32_t RESERVED1  : 15;\r
+  __IO uint32_t SS0        : 1;\r
+  __IO uint32_t SS1        : 1;\r
+  __IO uint32_t SS2        : 1;\r
+  __IO uint32_t CI         : 1;\r
+  __IO uint32_t EI         : 1;\r
+  __IO uint32_t RD         : 1;\r
+  __IO uint32_t RS         : 1;\r
+  __IO uint32_t RC         : 1;\r
+  __IO uint32_t FD         : 1;\r
+  __IO uint32_t FS         : 1;\r
+  __IO uint32_t TW0        : 1;\r
+  __IO uint32_t TW1        : 1;\r
+  __IO uint32_t MS0        : 1;\r
+  __IO uint32_t MS1        : 1;\r
+} stc_dmac_dmacb7_field_t;\r
+\r
+\r
+/******************************************************************************\r
+ * Peripheral register structures\r
+ ******************************************************************************/\r
+\r
+/******************************************************************************\r
+ * Flash_IF_MODULE\r
+ ******************************************************************************/\r
+/* Flash interface registers */\r
+typedef struct\r
+{\r
+  union {\r
+    __IO uint32_t FASZR;\r
+    stc_flash_if_faszr_field_t FASZR_f;\r
+  };\r
+  union {\r
+    __IO uint32_t FRWTR;\r
+    stc_flash_if_frwtr_field_t FRWTR_f;\r
+  };\r
+  union {\r
+    __IO uint32_t FSTR;\r
+    stc_flash_if_fstr_field_t FSTR_f;\r
+  };\r
+        uint8_t RESERVED0[4];\r
+  union {\r
+    __IO uint32_t FSYNDN;\r
+    stc_flash_if_fsyndn_field_t FSYNDN_f;\r
+  };\r
+        uint8_t RESERVED1[236];\r
+  union {\r
+    __IO uint32_t CRTRMM;\r
+    stc_flash_if_crtrmm_field_t CRTRMM_f;\r
+  };\r
+}FM3_FLASH_IF_TypeDef;\r
+\r
+/******************************************************************************\r
+ * Clock_Reset_MODULE\r
+ ******************************************************************************/\r
+/* Clock and reset registers */\r
+typedef struct\r
+{\r
+  union {\r
+    __IO  uint8_t SCM_CTL;\r
+    stc_crg_scm_ctl_field_t SCM_CTL_f;\r
+  };\r
+        uint8_t RESERVED0[3];\r
+  union {\r
+    __IO  uint8_t SCM_STR;\r
+    stc_crg_scm_str_field_t SCM_STR_f;\r
+  };\r
+        uint8_t RESERVED1[3];\r
+  __IO uint32_t STB_CTL;\r
+  union {\r
+    __IO uint16_t RST_STR;\r
+    stc_crg_rst_str_field_t RST_STR_f;\r
+  };\r
+        uint8_t RESERVED2[2];\r
+  union {\r
+    __IO  uint8_t BSC_PSR;\r
+    stc_crg_bsc_psr_field_t BSC_PSR_f;\r
+  };\r
+        uint8_t RESERVED3[3];\r
+  union {\r
+    __IO  uint8_t APBC0_PSR;\r
+    stc_crg_apbc0_psr_field_t APBC0_PSR_f;\r
+  };\r
+        uint8_t RESERVED4[3];\r
+  union {\r
+    __IO  uint8_t APBC1_PSR;\r
+    stc_crg_apbc1_psr_field_t APBC1_PSR_f;\r
+  };\r
+        uint8_t RESERVED5[3];\r
+  union {\r
+    __IO  uint8_t APBC2_PSR;\r
+    stc_crg_apbc2_psr_field_t APBC2_PSR_f;\r
+  };\r
+        uint8_t RESERVED6[3];\r
+  union {\r
+    __IO  uint8_t SWC_PSR;\r
+    stc_crg_swc_psr_field_t SWC_PSR_f;\r
+  };\r
+        uint8_t RESERVED7[7];\r
+  union {\r
+    __IO  uint8_t TTC_PSR;\r
+    stc_crg_ttc_psr_field_t TTC_PSR_f;\r
+  };\r
+        uint8_t RESERVED8[7];\r
+  union {\r
+    __IO  uint8_t CSW_TMR;\r
+    stc_crg_csw_tmr_field_t CSW_TMR_f;\r
+  };\r
+        uint8_t RESERVED9[3];\r
+  union {\r
+    __IO  uint8_t PSW_TMR;\r
+    stc_crg_psw_tmr_field_t PSW_TMR_f;\r
+  };\r
+        uint8_t RESERVED10[3];\r
+  union {\r
+    __IO  uint8_t PLL_CTL1;\r
+    stc_crg_pll_ctl1_field_t PLL_CTL1_f;\r
+  };\r
+        uint8_t RESERVED11[3];\r
+  union {\r
+    __IO  uint8_t PLL_CTL2;\r
+    stc_crg_pll_ctl2_field_t PLL_CTL2_f;\r
+  };\r
+        uint8_t RESERVED12[3];\r
+  union {\r
+    __IO uint16_t CSV_CTL;\r
+    stc_crg_csv_ctl_field_t CSV_CTL_f;\r
+  };\r
+        uint8_t RESERVED13[2];\r
+  union {\r
+    __IO  uint8_t CSV_STR;\r
+    stc_crg_csv_str_field_t CSV_STR_f;\r
+  };\r
+        uint8_t RESERVED14[3];\r
+  __IO uint16_t FCSWH_CTL;\r
+        uint8_t RESERVED15[2];\r
+  __IO uint16_t FCSWL_CTL;\r
+        uint8_t RESERVED16[2];\r
+  __IO uint16_t FCSWD_CTL;\r
+        uint8_t RESERVED17[2];\r
+  union {\r
+    __IO  uint8_t DBWDT_CTL;\r
+    stc_crg_dbwdt_ctl_field_t DBWDT_CTL_f;\r
+  };\r
+        uint8_t RESERVED18[11];\r
+  union {\r
+    __IO  uint8_t INT_ENR;\r
+    stc_crg_int_enr_field_t INT_ENR_f;\r
+  };\r
+        uint8_t RESERVED19[3];\r
+  union {\r
+    __IO  uint8_t INT_STR;\r
+    stc_crg_int_str_field_t INT_STR_f;\r
+  };\r
+        uint8_t RESERVED20[3];\r
+  union {\r
+    __IO  uint8_t INT_CLR;\r
+    stc_crg_int_clr_field_t INT_CLR_f;\r
+  };\r
+}FM3_CRG_TypeDef;\r
+\r
+/******************************************************************************\r
+ * HWWDT_MODULE\r
+ ******************************************************************************/\r
+/* Hardware watchdog registers */\r
+typedef struct\r
+{\r
+  __IO uint32_t WDG_LDR;\r
+  __IO uint32_t WDG_VLR;\r
+  union {\r
+    __IO  uint8_t WDG_CTL;\r
+    stc_hwwdt_wdg_ctl_field_t WDG_CTL_f;\r
+  };\r
+        uint8_t RESERVED0[3];\r
+  __IO  uint8_t WDG_ICL;\r
+        uint8_t RESERVED1[3];\r
+  union {\r
+    __IO  uint8_t WDG_RIS;\r
+    stc_hwwdt_wdg_ris_field_t WDG_RIS_f;\r
+  };\r
+        uint8_t RESERVED2[3055];\r
+  __IO uint32_t WDG_LCK;\r
+}FM3_HWWDT_TypeDef;\r
+\r
+/******************************************************************************\r
+ * SWWDT_MODULE\r
+ ******************************************************************************/\r
+/* Software watchdog registers */\r
+typedef struct\r
+{\r
+  __IO uint32_t WDOGLOAD;\r
+  __IO uint32_t WDOGVALUE;\r
+  union {\r
+    __IO  uint8_t WDOGCONTROL;\r
+    stc_swwdt_wdogcontrol_field_t WDOGCONTROL_f;\r
+  };\r
+        uint8_t RESERVED0[3];\r
+  __IO uint32_t WDOGINTCLR;\r
+  union {\r
+    __IO  uint8_t WDOGRIS;\r
+    stc_swwdt_wdogris_field_t WDOGRIS_f;\r
+  };\r
+        uint8_t RESERVED1[3055];\r
+  __IO uint32_t WDOGLOCK;\r
+}FM3_SWWDT_TypeDef;\r
+\r
+/******************************************************************************\r
+ * DTIM_MODULE\r
+ ******************************************************************************/\r
+/* Dual timer 1/2 registers */\r
+typedef struct\r
+{\r
+  __IO uint32_t TIMER1LOAD;\r
+  __IO uint32_t TIMER1VALUE;\r
+  union {\r
+    __IO uint32_t TIMER1CONTROL;\r
+    stc_dtim_timer1control_field_t TIMER1CONTROL_f;\r
+  };\r
+  __IO uint32_t TIMER1INTCLR;\r
+  union {\r
+    __IO uint32_t TIMER1RIS;\r
+    stc_dtim_timer1ris_field_t TIMER1RIS_f;\r
+  };\r
+  union {\r
+    __IO uint32_t TIMER1MIS;\r
+    stc_dtim_timer1mis_field_t TIMER1MIS_f;\r
+  };\r
+  __IO uint32_t TIMER1BGLOAD;\r
+        uint8_t RESERVED0[4];\r
+  __IO uint32_t TIMER2LOAD;\r
+  __IO uint32_t TIMER2VALUE;\r
+  union {\r
+    __IO uint32_t TIMER2CONTROL;\r
+    stc_dtim_timer2control_field_t TIMER2CONTROL_f;\r
+  };\r
+  __IO uint32_t TIMER2INTCLR;\r
+  union {\r
+    __IO uint32_t TIMER2RIS;\r
+    stc_dtim_timer2ris_field_t TIMER2RIS_f;\r
+  };\r
+  union {\r
+    __IO uint32_t TIMER2MIS;\r
+    stc_dtim_timer2mis_field_t TIMER2MIS_f;\r
+  };\r
+  __IO uint32_t TIMER2BGLOAD;\r
+}FM3_DTIM_TypeDef;\r
+\r
+/******************************************************************************\r
+ * MFT_FRT_MODULE\r
+ ******************************************************************************/\r
+/* Multifunction Timer unit 0 Free Running Timer registers */\r
+typedef struct\r
+{\r
+        uint8_t RESERVED0[40];\r
+  __IO uint16_t TCCP0;\r
+        uint8_t RESERVED1[2];\r
+  __IO uint16_t TCDT0;\r
+        uint8_t RESERVED2[2];\r
+  union {\r
+    __IO uint16_t TCSA0;\r
+    stc_mft_frt_tcsa0_field_t TCSA0_f;\r
+  };\r
+        uint8_t RESERVED3[2];\r
+  union {\r
+    __IO uint16_t TCSB0;\r
+    stc_mft_frt_tcsb0_field_t TCSB0_f;\r
+  };\r
+        uint8_t RESERVED4[2];\r
+  __IO uint16_t TCCP1;\r
+        uint8_t RESERVED5[2];\r
+  __IO uint16_t TCDT1;\r
+        uint8_t RESERVED6[2];\r
+  union {\r
+    __IO uint16_t TCSA1;\r
+    stc_mft_frt_tcsa1_field_t TCSA1_f;\r
+  };\r
+        uint8_t RESERVED7[2];\r
+  union {\r
+    __IO uint16_t TCSB1;\r
+    stc_mft_frt_tcsb1_field_t TCSB1_f;\r
+  };\r
+        uint8_t RESERVED8[2];\r
+  __IO uint16_t TCCP2;\r
+        uint8_t RESERVED9[2];\r
+  __IO uint16_t TCDT2;\r
+        uint8_t RESERVED10[2];\r
+  union {\r
+    __IO uint16_t TCSA2;\r
+    stc_mft_frt_tcsa2_field_t TCSA2_f;\r
+  };\r
+        uint8_t RESERVED11[2];\r
+  union {\r
+    __IO uint16_t TCSB2;\r
+    stc_mft_frt_tcsb2_field_t TCSB2_f;\r
+  };\r
+}FM3_MFT_FRT_TypeDef;\r
+\r
+/******************************************************************************\r
+ * MFT_OCU_MODULE\r
+ ******************************************************************************/\r
+/* Multifunction Timer unit 0 Output Compare Unit registers */\r
+typedef struct\r
+{\r
+  __IO uint16_t OCCP0;\r
+        uint8_t RESERVED0[2];\r
+  __IO uint16_t OCCP1;\r
+        uint8_t RESERVED1[2];\r
+  __IO uint16_t OCCP2;\r
+        uint8_t RESERVED2[2];\r
+  __IO uint16_t OCCP3;\r
+        uint8_t RESERVED3[2];\r
+  __IO uint16_t OCCP4;\r
+        uint8_t RESERVED4[2];\r
+  __IO uint16_t OCCP5;\r
+        uint8_t RESERVED5[2];\r
+  union {\r
+    __IO  uint8_t OCSA10;\r
+    stc_mft_ocu_ocsa10_field_t OCSA10_f;\r
+  };\r
+  union {\r
+    __IO  uint8_t OCSB10;\r
+    stc_mft_ocu_ocsb10_field_t OCSB10_f;\r
+  };\r
+        uint8_t RESERVED6[2];\r
+  union {\r
+    __IO  uint8_t OCSA32;\r
+    stc_mft_ocu_ocsa32_field_t OCSA32_f;\r
+  };\r
+  union {\r
+    __IO  uint8_t OCSB32;\r
+    stc_mft_ocu_ocsb32_field_t OCSB32_f;\r
+  };\r
+        uint8_t RESERVED7[2];\r
+  union {\r
+    __IO  uint8_t OCSA54;\r
+    stc_mft_ocu_ocsa54_field_t OCSA54_f;\r
+  };\r
+  union {\r
+    __IO  uint8_t OCSB54;\r
+    stc_mft_ocu_ocsb54_field_t OCSB54_f;\r
+  };\r
+        uint8_t RESERVED8[3];\r
+  union {\r
+    __IO  uint8_t OCSC;\r
+    stc_mft_ocu_ocsc_field_t OCSC_f;\r
+  };\r
+        uint8_t RESERVED9[50];\r
+  union {\r
+    __IO  uint8_t OCFS10;\r
+    stc_mft_ocu_ocfs10_field_t OCFS10_f;\r
+  };\r
+  union {\r
+    __IO  uint8_t OCFS32;\r
+    stc_mft_ocu_ocfs32_field_t OCFS32_f;\r
+  };\r
+        uint8_t RESERVED10[2];\r
+  union {\r
+    __IO  uint8_t OCFS54;\r
+    stc_mft_ocu_ocfs54_field_t OCFS54_f;\r
+  };\r
+}FM3_MFT_OCU_TypeDef;\r
+\r
+/******************************************************************************\r
+ * MFT_WFG_MODULE\r
+ ******************************************************************************/\r
+/* Multifunction Timer unit 0 Waveform Generator and Noise Canceler registers */\r
+typedef struct\r
+{\r
+        uint8_t RESERVED0[128];\r
+  __IO uint16_t WFTM10;\r
+        uint8_t RESERVED1[2];\r
+  __IO uint16_t WFTM32;\r
+        uint8_t RESERVED2[2];\r
+  __IO uint16_t WFTM54;\r
+        uint8_t RESERVED3[2];\r
+  union {\r
+    __IO uint16_t WFSA10;\r
+    stc_mft_wfg_wfsa10_field_t WFSA10_f;\r
+  };\r
+        uint8_t RESERVED4[2];\r
+  union {\r
+    __IO uint16_t WFSA32;\r
+    stc_mft_wfg_wfsa32_field_t WFSA32_f;\r
+  };\r
+        uint8_t RESERVED5[2];\r
+  union {\r
+    __IO uint16_t WFSA54;\r
+    stc_mft_wfg_wfsa54_field_t WFSA54_f;\r
+  };\r
+        uint8_t RESERVED6[2];\r
+  union {\r
+    __IO uint16_t WFIR;\r
+    stc_mft_wfg_wfir_field_t WFIR_f;\r
+  };\r
+        uint8_t RESERVED7[2];\r
+  union {\r
+    __IO uint16_t NZCL;\r
+    stc_mft_wfg_nzcl_field_t NZCL_f;\r
+  };\r
+}FM3_MFT_WFG_TypeDef;\r
+\r
+/******************************************************************************\r
+ * MFT_ICU_MODULE\r
+ ******************************************************************************/\r
+/* Multifunction Timer unit 0 Input Capture Unit registers */\r
+typedef struct\r
+{\r
+        uint8_t RESERVED0[96];\r
+  union {\r
+    __IO  uint8_t ICFS10;\r
+    stc_mft_icu_icfs10_field_t ICFS10_f;\r
+  };\r
+  union {\r
+    __IO  uint8_t ICFS32;\r
+    stc_mft_icu_icfs32_field_t ICFS32_f;\r
+  };\r
+        uint8_t RESERVED1[6];\r
+  __IO uint16_t ICCP0;\r
+        uint8_t RESERVED2[2];\r
+  __IO uint16_t ICCP1;\r
+        uint8_t RESERVED3[2];\r
+  __IO uint16_t ICCP2;\r
+        uint8_t RESERVED4[2];\r
+  __IO uint16_t ICCP3;\r
+        uint8_t RESERVED5[2];\r
+  union {\r
+    __IO  uint8_t ICSA10;\r
+    stc_mft_icu_icsa10_field_t ICSA10_f;\r
+  };\r
+  union {\r
+    __IO  uint8_t ICSB10;\r
+    stc_mft_icu_icsb10_field_t ICSB10_f;\r
+  };\r
+        uint8_t RESERVED6[2];\r
+  union {\r
+    __IO  uint8_t ICSA32;\r
+    stc_mft_icu_icsa32_field_t ICSA32_f;\r
+  };\r
+  union {\r
+    __IO  uint8_t ICSB32;\r
+    stc_mft_icu_icsb32_field_t ICSB32_f;\r
+  };\r
+}FM3_MFT_ICU_TypeDef;\r
+\r
+/******************************************************************************\r
+ * MFT_ADCMP_MODULE\r
+ ******************************************************************************/\r
+/* Multifunction Timer unit 0 ADC Start Compare Unit registers */\r
+typedef struct\r
+{\r
+        uint8_t RESERVED0[160];\r
+  __IO uint16_t ACCP0;\r
+        uint8_t RESERVED1[2];\r
+  __IO uint16_t ACCPDN0;\r
+        uint8_t RESERVED2[2];\r
+  __IO uint16_t ACCP1;\r
+        uint8_t RESERVED3[2];\r
+  __IO uint16_t ACCPDN1;\r
+        uint8_t RESERVED4[2];\r
+  __IO uint16_t ACCP2;\r
+        uint8_t RESERVED5[2];\r
+  __IO uint16_t ACCPDN2;\r
+        uint8_t RESERVED6[2];\r
+  union {\r
+    __IO  uint8_t ACSB;\r
+    stc_mft_adcmp_acsb_field_t ACSB_f;\r
+  };\r
+        uint8_t RESERVED7[3];\r
+  union {\r
+    __IO uint16_t ACSA;\r
+    stc_mft_adcmp_acsa_field_t ACSA_f;\r
+  };\r
+        uint8_t RESERVED8[2];\r
+  union {\r
+    __IO uint16_t ATSA;\r
+    stc_mft_adcmp_atsa_field_t ATSA_f;\r
+  };\r
+}FM3_MFT_ADCMP_TypeDef;\r
+\r
+/******************************************************************************\r
+ * MFT_PPG_MODULE\r
+ ******************************************************************************/\r
+/* Multifunction Timer PPG registers */\r
+typedef struct\r
+{\r
+        uint8_t RESERVED0;\r
+  union {\r
+    __IO  uint8_t TTCR0;\r
+    stc_mft_ppg_ttcr0_field_t TTCR0_f;\r
+  };\r
+        uint8_t RESERVED1[7];\r
+  __IO  uint8_t COMP0;\r
+        uint8_t RESERVED2[2];\r
+  __IO  uint8_t COMP2;\r
+        uint8_t RESERVED3[4];\r
+  __IO  uint8_t COMP4;\r
+        uint8_t RESERVED4[2];\r
+  __IO  uint8_t COMP6;\r
+        uint8_t RESERVED5[12];\r
+  union {\r
+    __IO  uint8_t TTCR1;\r
+    stc_mft_ppg_ttcr1_field_t TTCR1_f;\r
+  };\r
+        uint8_t RESERVED6[7];\r
+  __IO  uint8_t COMP1;\r
+        uint8_t RESERVED7[2];\r
+  __IO  uint8_t COMP3;\r
+        uint8_t RESERVED8[4];\r
+  __IO  uint8_t COMP5;\r
+        uint8_t RESERVED9[2];\r
+  __IO  uint8_t COMP7;\r
+        uint8_t RESERVED10[203];\r
+  union {\r
+    __IO uint16_t TRG;\r
+    stc_mft_ppg_trg_field_t TRG_f;\r
+  };\r
+        uint8_t RESERVED11[2];\r
+  union {\r
+    __IO uint16_t REVC;\r
+    stc_mft_ppg_revc_field_t REVC_f;\r
+  };\r
+        uint8_t RESERVED12[250];\r
+  union {\r
+    __IO  uint8_t PPGC1;\r
+    stc_mft_ppg_ppgc1_field_t PPGC1_f;\r
+  };\r
+  union {\r
+    __IO  uint8_t PPGC0;\r
+    stc_mft_ppg_ppgc0_field_t PPGC0_f;\r
+  };\r
+        uint8_t RESERVED13[2];\r
+  union {\r
+    __IO  uint8_t PPGC3;\r
+    stc_mft_ppg_ppgc3_field_t PPGC3_f;\r
+  };\r
+  union {\r
+    __IO  uint8_t PPGC2;\r
+    stc_mft_ppg_ppgc2_field_t PPGC2_f;\r
+  };\r
+        uint8_t RESERVED14[2];\r
+  union {\r
+    __IO uint16_t PRL0;\r
+    struct {\r
+      __IO  uint8_t PRLL0;\r
+      __IO  uint8_t PRLH0;\r
+    };\r
+  };\r
+        uint8_t RESERVED15[2];\r
+  union {\r
+    __IO uint16_t PRL1;\r
+    struct {\r
+      __IO  uint8_t PRLL1;\r
+      __IO  uint8_t PRLH1;\r
+    };\r
+  };\r
+        uint8_t RESERVED16[2];\r
+  union {\r
+    __IO uint16_t PRL2;\r
+    struct {\r
+      __IO  uint8_t PRLL2;\r
+      __IO  uint8_t PRLH2;\r
+    };\r
+  };\r
+        uint8_t RESERVED17[2];\r
+  union {\r
+    __IO uint16_t PRL3;\r
+    struct {\r
+      __IO  uint8_t PRLL3;\r
+      __IO  uint8_t PRLH3;\r
+    };\r
+  };\r
+        uint8_t RESERVED18[2];\r
+  union {\r
+    __IO  uint8_t GATEC0;\r
+    stc_mft_ppg_gatec0_field_t GATEC0_f;\r
+  };\r
+        uint8_t RESERVED19[39];\r
+  union {\r
+    __IO  uint8_t PPGC5;\r
+    stc_mft_ppg_ppgc5_field_t PPGC5_f;\r
+  };\r
+  union {\r
+    __IO  uint8_t PPGC4;\r
+    stc_mft_ppg_ppgc4_field_t PPGC4_f;\r
+  };\r
+        uint8_t RESERVED20[2];\r
+  union {\r
+    __IO  uint8_t PPGC7;\r
+    stc_mft_ppg_ppgc7_field_t PPGC7_f;\r
+  };\r
+  union {\r
+    __IO  uint8_t PPGC6;\r
+    stc_mft_ppg_ppgc6_field_t PPGC6_f;\r
+  };\r
+        uint8_t RESERVED21[2];\r
+  union {\r
+    __IO uint16_t PRL4;\r
+    struct {\r
+      __IO  uint8_t PRLL4;\r
+      __IO  uint8_t PRLH4;\r
+    };\r
+  };\r
+        uint8_t RESERVED22[2];\r
+  union {\r
+    __IO uint16_t PRL5;\r
+    struct {\r
+      __IO  uint8_t PRLL5;\r
+      __IO  uint8_t PRLH5;\r
+    };\r
+  };\r
+        uint8_t RESERVED23[2];\r
+  union {\r
+    __IO uint16_t PRL6;\r
+    struct {\r
+      __IO  uint8_t PRLL6;\r
+      __IO  uint8_t PRLH6;\r
+    };\r
+  };\r
+        uint8_t RESERVED24[2];\r
+  union {\r
+    __IO uint16_t PRL7;\r
+    struct {\r
+      __IO  uint8_t PRLL7;\r
+      __IO  uint8_t PRLH7;\r
+    };\r
+  };\r
+        uint8_t RESERVED25[2];\r
+  union {\r
+    __IO  uint8_t GATEC4;\r
+    stc_mft_ppg_gatec4_field_t GATEC4_f;\r
+  };\r
+        uint8_t RESERVED26[39];\r
+  union {\r
+    __IO  uint8_t PPGC9;\r
+    stc_mft_ppg_ppgc9_field_t PPGC9_f;\r
+  };\r
+  union {\r
+    __IO  uint8_t PPGC8;\r
+    stc_mft_ppg_ppgc8_field_t PPGC8_f;\r
+  };\r
+        uint8_t RESERVED27[2];\r
+  union {\r
+    __IO  uint8_t PPGC11;\r
+    stc_mft_ppg_ppgc11_field_t PPGC11_f;\r
+  };\r
+  union {\r
+    __IO  uint8_t PPGC10;\r
+    stc_mft_ppg_ppgc10_field_t PPGC10_f;\r
+  };\r
+        uint8_t RESERVED28[2];\r
+  union {\r
+    __IO uint16_t PRL8;\r
+    struct {\r
+      __IO  uint8_t PRLL8;\r
+      __IO  uint8_t PRLH8;\r
+    };\r
+  };\r
+        uint8_t RESERVED29[2];\r
+  union {\r
+    __IO uint16_t PRL9;\r
+    struct {\r
+      __IO  uint8_t PRLL9;\r
+      __IO  uint8_t PRLH9;\r
+    };\r
+  };\r
+        uint8_t RESERVED30[2];\r
+  union {\r
+    __IO uint16_t PRL10;\r
+    struct {\r
+      __IO  uint8_t PRLL10;\r
+      __IO  uint8_t PRLH10;\r
+    };\r
+  };\r
+        uint8_t RESERVED31[2];\r
+  union {\r
+    __IO uint16_t PRL11;\r
+    struct {\r
+      __IO  uint8_t PRLL11;\r
+      __IO  uint8_t PRLH11;\r
+    };\r
+  };\r
+        uint8_t RESERVED32[2];\r
+  union {\r
+    __IO  uint8_t GATEC8;\r
+    stc_mft_ppg_gatec8_field_t GATEC8_f;\r
+  };\r
+        uint8_t RESERVED33[39];\r
+  union {\r
+    __IO  uint8_t PPGC13;\r
+    stc_mft_ppg_ppgc13_field_t PPGC13_f;\r
+  };\r
+  union {\r
+    __IO  uint8_t PPGC12;\r
+    stc_mft_ppg_ppgc12_field_t PPGC12_f;\r
+  };\r
+        uint8_t RESERVED34[2];\r
+  union {\r
+    __IO  uint8_t PPGC15;\r
+    stc_mft_ppg_ppgc15_field_t PPGC15_f;\r
+  };\r
+  union {\r
+    __IO  uint8_t PPGC14;\r
+    stc_mft_ppg_ppgc14_field_t PPGC14_f;\r
+  };\r
+        uint8_t RESERVED35[2];\r
+  union {\r
+    __IO uint16_t PRL12;\r
+    struct {\r
+      __IO  uint8_t PRLL12;\r
+      __IO  uint8_t PRLH12;\r
+    };\r
+  };\r
+        uint8_t RESERVED36[2];\r
+  union {\r
+    __IO uint16_t PRL13;\r
+    struct {\r
+      __IO  uint8_t PRLL13;\r
+      __IO  uint8_t PRLH13;\r
+    };\r
+  };\r
+        uint8_t RESERVED37[2];\r
+  union {\r
+    __IO uint16_t PRL14;\r
+    struct {\r
+      __IO  uint8_t PRLL14;\r
+      __IO  uint8_t PRLH14;\r
+    };\r
+  };\r
+        uint8_t RESERVED38[2];\r
+  union {\r
+    __IO uint16_t PRL15;\r
+    struct {\r
+      __IO  uint8_t PRLL15;\r
+      __IO  uint8_t PRLH15;\r
+    };\r
+  };\r
+        uint8_t RESERVED39[2];\r
+  union {\r
+    __IO  uint8_t GATEC12;\r
+    stc_mft_ppg_gatec12_field_t GATEC12_f;\r
+  };\r
+}FM3_MFT_PPG_TypeDef;\r
+\r
+/******************************************************************************\r
+ * BT_PPG_MODULE\r
+ ******************************************************************************/\r
+/* Base Timer 0 PPG registers */\r
+typedef struct\r
+{\r
+  __IO uint16_t PRLL;\r
+        uint8_t RESERVED0[2];\r
+  __IO uint16_t PRLH;\r
+        uint8_t RESERVED1[2];\r
+  __IO uint16_t TMR;\r
+        uint8_t RESERVED2[2];\r
+  union {\r
+    __IO uint16_t TMCR;\r
+    stc_bt_ppg_tmcr_field_t TMCR_f;\r
+  };\r
+        uint8_t RESERVED3[2];\r
+  union {\r
+    __IO  uint8_t STC;\r
+    stc_bt_ppg_stc_field_t STC_f;\r
+  };\r
+  union {\r
+    __IO  uint8_t TMCR2;\r
+    stc_bt_ppg_tmcr2_field_t TMCR2_f;\r
+  };\r
+}FM3_BT_PPG_TypeDef;\r
+\r
+/******************************************************************************\r
+ * BT_PWM_MODULE\r
+ ******************************************************************************/\r
+/* Base Timer 0 PWM registers */\r
+typedef struct\r
+{\r
+  __IO uint16_t PCSR;\r
+        uint8_t RESERVED0[2];\r
+  __IO uint16_t PDUT;\r
+        uint8_t RESERVED1[2];\r
+  __IO uint16_t TMR;\r
+        uint8_t RESERVED2[2];\r
+  union {\r
+    __IO uint16_t TMCR;\r
+    stc_bt_pwm_tmcr_field_t TMCR_f;\r
+  };\r
+        uint8_t RESERVED3[2];\r
+  union {\r
+    __IO  uint8_t STC;\r
+    stc_bt_pwm_stc_field_t STC_f;\r
+  };\r
+  union {\r
+    __IO  uint8_t TMCR2;\r
+    stc_bt_pwm_tmcr2_field_t TMCR2_f;\r
+  };\r
+}FM3_BT_PWM_TypeDef;\r
+\r
+/******************************************************************************\r
+ * BT_RT_MODULE\r
+ ******************************************************************************/\r
+/* Base Timer 0 RT registers */\r
+typedef struct\r
+{\r
+  __IO uint16_t PCSR;\r
+        uint8_t RESERVED0[6];\r
+  __IO uint16_t TMR;\r
+        uint8_t RESERVED1[2];\r
+  union {\r
+    __IO uint16_t TMCR;\r
+    stc_bt_rt_tmcr_field_t TMCR_f;\r
+  };\r
+        uint8_t RESERVED2[2];\r
+  union {\r
+    __IO  uint8_t STC;\r
+    stc_bt_rt_stc_field_t STC_f;\r
+  };\r
+  union {\r
+    __IO  uint8_t TMCR2;\r
+    stc_bt_rt_tmcr2_field_t TMCR2_f;\r
+  };\r
+}FM3_BT_RT_TypeDef;\r
+\r
+/******************************************************************************\r
+ * BT_PWC_MODULE\r
+ ******************************************************************************/\r
+/* Base Timer 0 PWC registers */\r
+typedef struct\r
+{\r
+        uint8_t RESERVED0[4];\r
+  __IO uint16_t DTBF;\r
+        uint8_t RESERVED1[6];\r
+  union {\r
+    __IO uint16_t TMCR;\r
+    stc_bt_pwc_tmcr_field_t TMCR_f;\r
+  };\r
+        uint8_t RESERVED2[2];\r
+  union {\r
+    __IO  uint8_t STC;\r
+    stc_bt_pwc_stc_field_t STC_f;\r
+  };\r
+  union {\r
+    __IO  uint8_t TMCR2;\r
+    stc_bt_pwc_tmcr2_field_t TMCR2_f;\r
+  };\r
+}FM3_BT_PWC_TypeDef;\r
+\r
+/******************************************************************************\r
+ * BTIOSEL03_MODULE\r
+ ******************************************************************************/\r
+/* Base Timer I/O selector channel 0 - channel 3 registers */\r
+typedef struct\r
+{\r
+        uint8_t RESERVED0;\r
+  union {\r
+    __IO  uint8_t BTSEL0123;\r
+    stc_btiosel03_btsel0123_field_t BTSEL0123_f;\r
+  };\r
+}FM3_BTIOSEL03_TypeDef;\r
+\r
+/******************************************************************************\r
+ * BTIOSEL47_MODULE\r
+ ******************************************************************************/\r
+/* Base Timer I/O selector channel 4 - channel 7 registers */\r
+typedef struct\r
+{\r
+        uint8_t RESERVED0;\r
+  union {\r
+    __IO  uint8_t BTSEL4567;\r
+    stc_btiosel47_btsel4567_field_t BTSEL4567_f;\r
+  };\r
+}FM3_BTIOSEL47_TypeDef;\r
+\r
+/******************************************************************************\r
+ * SBSSR_MODULE\r
+ ******************************************************************************/\r
+/* Software based Simulation Startup (Base Timer) register */\r
+typedef struct\r
+{\r
+  union {\r
+    __IO uint16_t BTSSSR;\r
+    stc_sbssr_btsssr_field_t BTSSSR_f;\r
+  };\r
+}FM3_SBSSR_TypeDef;\r
+\r
+/******************************************************************************\r
+ * QPRC_MODULE\r
+ ******************************************************************************/\r
+/* Quad position and revolution counter channel 0 registers */\r
+typedef struct\r
+{\r
+  __IO uint16_t QPCR;\r
+        uint8_t RESERVED0[2];\r
+  __IO uint16_t QRCR;\r
+        uint8_t RESERVED1[2];\r
+  __IO uint16_t QPCCR;\r
+        uint8_t RESERVED2[2];\r
+  __IO uint16_t QPRCR;\r
+        uint8_t RESERVED3[2];\r
+  __IO uint16_t QMPR;\r
+        uint8_t RESERVED4[2];\r
+  union {\r
+    union {\r
+      __IO uint16_t QICR;\r
+      stc_qprc_qicr_field_t QICR_f;\r
+    };\r
+    struct {\r
+      union {\r
+        __IO  uint8_t QICRL;\r
+        stc_qprc_qicrl_field_t QICRL_f;\r
+      };\r
+      union {\r
+        __IO  uint8_t QICRH;\r
+        stc_qprc_qicrh_field_t QICRH_f;\r
+      };\r
+    };\r
+  };\r
+        uint8_t RESERVED5[2];\r
+  union {\r
+    union {\r
+      __IO uint16_t QCR;\r
+      stc_qprc_qcr_field_t QCR_f;\r
+    };\r
+    struct {\r
+      union {\r
+        __IO  uint8_t QCRL;\r
+        stc_qprc_qcrl_field_t QCRL_f;\r
+      };\r
+      union {\r
+        __IO  uint8_t QCRH;\r
+        stc_qprc_qcrh_field_t QCRH_f;\r
+      };\r
+    };\r
+  };\r
+        uint8_t RESERVED6[2];\r
+  union {\r
+    __IO uint16_t QECR;\r
+    stc_qprc_qecr_field_t QECR_f;\r
+  };\r
+}FM3_QPRC_TypeDef;\r
+\r
+/******************************************************************************\r
+ * ADC12_MODULE\r
+ ******************************************************************************/\r
+/* 12-bit ADC unit 0 registers */\r
+typedef struct\r
+{\r
+  union {\r
+    __IO  uint8_t ADSR;\r
+    stc_adc_adsr_field_t ADSR_f;\r
+  };\r
+  union {\r
+    __IO  uint8_t ADCR;\r
+    stc_adc_adcr_field_t ADCR_f;\r
+  };\r
+        uint8_t RESERVED0[6];\r
+  union {\r
+    __IO  uint8_t SFNS;\r
+    stc_adc_sfns_field_t SFNS_f;\r
+  };\r
+  union {\r
+    __IO  uint8_t SCCR;\r
+    stc_adc_sccr_field_t SCCR_f;\r
+  };\r
+        uint8_t RESERVED1[2];\r
+  union {\r
+    union {\r
+      __IO uint32_t SCFD;\r
+      stc_adc_scfd_field_t SCFD_f;\r
+    };\r
+    struct {\r
+      union {\r
+        __IO uint16_t SCFDL;\r
+        stc_adc_scfdl_field_t SCFDL_f;\r
+      };\r
+      union {\r
+        __IO uint16_t SCFDH;\r
+        stc_adc_scfdh_field_t SCFDH_f;\r
+      };\r
+    };\r
+  };\r
+  union {\r
+    union {\r
+      __IO uint16_t SCIS23;\r
+      stc_adc_scis23_field_t SCIS23_f;\r
+    };\r
+    struct {\r
+      union {\r
+        __IO  uint8_t SCIS2;\r
+        stc_adc_scis2_field_t SCIS2_f;\r
+      };\r
+      union {\r
+        __IO  uint8_t SCIS3;\r
+        stc_adc_scis3_field_t SCIS3_f;\r
+      };\r
+    };\r
+  };\r
+        uint8_t RESERVED2[2];\r
+  union {\r
+    union {\r
+      __IO uint16_t SCIS01;\r
+      stc_adc_scis01_field_t SCIS01_f;\r
+    };\r
+    struct {\r
+      union {\r
+        __IO  uint8_t SCIS0;\r
+        stc_adc_scis0_field_t SCIS0_f;\r
+      };\r
+      union {\r
+        __IO  uint8_t SCIS1;\r
+        stc_adc_scis1_field_t SCIS1_f;\r
+      };\r
+    };\r
+  };\r
+        uint8_t RESERVED3[2];\r
+  union {\r
+    __IO  uint8_t PFNS;\r
+    stc_adc_pfns_field_t PFNS_f;\r
+  };\r
+  union {\r
+    __IO  uint8_t PCCR;\r
+    stc_adc_pccr_field_t PCCR_f;\r
+  };\r
+        uint8_t RESERVED4[2];\r
+  union {\r
+    union {\r
+      __IO uint32_t PCFD;\r
+      stc_adc_pcfd_field_t PCFD_f;\r
+    };\r
+    struct {\r
+      union {\r
+        __IO uint16_t PCFDL;\r
+        stc_adc_pcfdl_field_t PCFDL_f;\r
+      };\r
+      union {\r
+        __IO uint16_t PCFDH;\r
+        stc_adc_pcfdh_field_t PCFDH_f;\r
+      };\r
+    };\r
+  };\r
+  union {\r
+    __IO  uint8_t PCIS;\r
+    stc_adc_pcis_field_t PCIS_f;\r
+  };\r
+        uint8_t RESERVED5[3];\r
+  union {\r
+    __IO  uint8_t CMPCR;\r
+    stc_adc_cmpcr_field_t CMPCR_f;\r
+  };\r
+        uint8_t RESERVED6;\r
+  union {\r
+    __IO uint16_t CMPD;\r
+    stc_adc_cmpd_field_t CMPD_f;\r
+  };\r
+  union {\r
+    union {\r
+      __IO uint16_t ADSS23;\r
+      stc_adc_adss23_field_t ADSS23_f;\r
+    };\r
+    struct {\r
+      union {\r
+        __IO  uint8_t ADSS2;\r
+        stc_adc_adss2_field_t ADSS2_f;\r
+      };\r
+      union {\r
+        __IO  uint8_t ADSS3;\r
+        stc_adc_adss3_field_t ADSS3_f;\r
+      };\r
+    };\r
+  };\r
+        uint8_t RESERVED7[2];\r
+  union {\r
+    union {\r
+      __IO uint16_t ADSS01;\r
+      stc_adc_adss01_field_t ADSS01_f;\r
+    };\r
+    struct {\r
+      union {\r
+        __IO  uint8_t ADSS0;\r
+        stc_adc_adss0_field_t ADSS0_f;\r
+      };\r
+      union {\r
+        __IO  uint8_t ADSS1;\r
+        stc_adc_adss1_field_t ADSS1_f;\r
+      };\r
+    };\r
+  };\r
+        uint8_t RESERVED8[2];\r
+  union {\r
+    union {\r
+      __IO uint16_t ADST01;\r
+      stc_adc_adst01_field_t ADST01_f;\r
+    };\r
+    struct {\r
+      union {\r
+        __IO  uint8_t ADST1;\r
+        stc_adc_adst1_field_t ADST1_f;\r
+      };\r
+      union {\r
+        __IO  uint8_t ADST0;\r
+        stc_adc_adst0_field_t ADST0_f;\r
+      };\r
+    };\r
+  };\r
+        uint8_t RESERVED9[2];\r
+  union {\r
+    __IO  uint8_t ADCT;\r
+    stc_adc_adct_field_t ADCT_f;\r
+  };\r
+        uint8_t RESERVED10[3];\r
+  union {\r
+    __IO  uint8_t PRTSL;\r
+    stc_adc_prtsl_field_t PRTSL_f;\r
+  };\r
+  union {\r
+    __IO  uint8_t SCTSL;\r
+    stc_adc_sctsl_field_t SCTSL_f;\r
+  };\r
+        uint8_t RESERVED11[2];\r
+  union {\r
+    __IO  uint8_t ADCEN;\r
+    stc_adc_adcen_field_t ADCEN_f;\r
+  };\r
+}FM3_ADC_TypeDef;\r
+\r
+/******************************************************************************\r
+ * CRTRIM_MODULE\r
+ ******************************************************************************/\r
+/* CR trimming registers */\r
+typedef struct\r
+{\r
+  union {\r
+    __IO  uint8_t MCR_PSR;\r
+    stc_crtrim_mcr_psr_field_t MCR_PSR_f;\r
+  };\r
+        uint8_t RESERVED0[3];\r
+  union {\r
+    __IO uint16_t MCR_FTRM;\r
+    stc_crtrim_mcr_ftrm_field_t MCR_FTRM_f;\r
+  };\r
+        uint8_t RESERVED1[6];\r
+  __IO uint32_t MCR_RLR;\r
+}FM3_CRTRIM_TypeDef;\r
+\r
+/******************************************************************************\r
+ * EXTI_MODULE\r
+ ******************************************************************************/\r
+/* External interrupt registers */\r
+typedef struct\r
+{\r
+  union {\r
+    __IO uint16_t ENIR;\r
+    stc_exti_enir_field_t ENIR_f;\r
+  };\r
+        uint8_t RESERVED0[2];\r
+  union {\r
+    __IO uint16_t EIRR;\r
+    stc_exti_eirr_field_t EIRR_f;\r
+  };\r
+        uint8_t RESERVED1[2];\r
+  union {\r
+    __IO uint16_t EICL;\r
+    stc_exti_eicl_field_t EICL_f;\r
+  };\r
+        uint8_t RESERVED2[2];\r
+  union {\r
+    __IO uint32_t ELVR;\r
+    stc_exti_elvr_field_t ELVR_f;\r
+  };\r
+        uint8_t RESERVED3[4];\r
+  union {\r
+    __IO  uint8_t NMIRR;\r
+    stc_exti_nmirr_field_t NMIRR_f;\r
+  };\r
+        uint8_t RESERVED4[3];\r
+  union {\r
+    __IO  uint8_t NMICL;\r
+    stc_exti_nmicl_field_t NMICL_f;\r
+  };\r
+}FM3_EXTI_TypeDef;\r
+\r
+/******************************************************************************\r
+ * INTREQ_MODULE\r
+ ******************************************************************************/\r
+/* Interrupt request read registers */\r
+typedef struct\r
+{\r
+  union {\r
+    __IO uint32_t DRQSEL;\r
+    stc_intreq_drqsel_field_t DRQSEL_f;\r
+  };\r
+        uint8_t RESERVED0[7];\r
+  union {\r
+    __IO uint32_t ODDPKS;\r
+    stc_intreq_oddpks_field_t ODDPKS_f;\r
+  };\r
+        uint8_t RESERVED1;\r
+  union {\r
+    __IO uint32_t EXC02MON;\r
+    stc_intreq_exc02mon_field_t EXC02MON_f;\r
+  };\r
+  union {\r
+    __IO uint32_t IRQ00MON;\r
+    stc_intreq_irq00mon_field_t IRQ00MON_f;\r
+  };\r
+  union {\r
+    __IO uint32_t IRQ01MON;\r
+    stc_intreq_irq01mon_field_t IRQ01MON_f;\r
+  };\r
+  union {\r
+    __IO uint32_t IRQ02MON;\r
+    stc_intreq_irq02mon_field_t IRQ02MON_f;\r
+  };\r
+  union {\r
+    __IO uint32_t IRQ03MON;\r
+    stc_intreq_irq03mon_field_t IRQ03MON_f;\r
+  };\r
+  union {\r
+    __IO uint32_t IRQ04MON;\r
+    stc_intreq_irq04mon_field_t IRQ04MON_f;\r
+  };\r
+  union {\r
+    __IO uint32_t IRQ05MON;\r
+    stc_intreq_irq05mon_field_t IRQ05MON_f;\r
+  };\r
+  union {\r
+    __IO uint32_t IRQ06MON;\r
+    stc_intreq_irq06mon_field_t IRQ06MON_f;\r
+  };\r
+  union {\r
+    __IO uint32_t IRQ07MON;\r
+    stc_intreq_irq07mon_field_t IRQ07MON_f;\r
+  };\r
+  union {\r
+    __IO uint32_t IRQ08MON;\r
+    stc_intreq_irq08mon_field_t IRQ08MON_f;\r
+  };\r
+  union {\r
+    __IO uint32_t IRQ09MON;\r
+    stc_intreq_irq09mon_field_t IRQ09MON_f;\r
+  };\r
+  union {\r
+    __IO uint32_t IRQ10MON;\r
+    stc_intreq_irq10mon_field_t IRQ10MON_f;\r
+  };\r
+  union {\r
+    __IO uint32_t IRQ11MON;\r
+    stc_intreq_irq11mon_field_t IRQ11MON_f;\r
+  };\r
+  union {\r
+    __IO uint32_t IRQ12MON;\r
+    stc_intreq_irq12mon_field_t IRQ12MON_f;\r
+  };\r
+  union {\r
+    __IO uint32_t IRQ13MON;\r
+    stc_intreq_irq13mon_field_t IRQ13MON_f;\r
+  };\r
+  union {\r
+    __IO uint32_t IRQ14MON;\r
+    stc_intreq_irq14mon_field_t IRQ14MON_f;\r
+  };\r
+  union {\r
+    __IO uint32_t IRQ15MON;\r
+    stc_intreq_irq15mon_field_t IRQ15MON_f;\r
+  };\r
+  union {\r
+    __IO uint32_t IRQ16MON;\r
+    stc_intreq_irq16mon_field_t IRQ16MON_f;\r
+  };\r
+  union {\r
+    __IO uint32_t IRQ17MON;\r
+    stc_intreq_irq17mon_field_t IRQ17MON_f;\r
+  };\r
+  union {\r
+    __IO uint32_t IRQ18MON;\r
+    stc_intreq_irq18mon_field_t IRQ18MON_f;\r
+  };\r
+  union {\r
+    __IO uint32_t IRQ19MON;\r
+    stc_intreq_irq19mon_field_t IRQ19MON_f;\r
+  };\r
+  union {\r
+    __IO uint32_t IRQ20MON;\r
+    stc_intreq_irq20mon_field_t IRQ20MON_f;\r
+  };\r
+  union {\r
+    __IO uint32_t IRQ21MON;\r
+    stc_intreq_irq21mon_field_t IRQ21MON_f;\r
+  };\r
+  union {\r
+    __IO uint32_t IRQ22MON;\r
+    stc_intreq_irq22mon_field_t IRQ22MON_f;\r
+  };\r
+  union {\r
+    __IO uint32_t IRQ23MON;\r
+    stc_intreq_irq23mon_field_t IRQ23MON_f;\r
+  };\r
+  union {\r
+    __IO uint32_t IRQ24MON;\r
+    stc_intreq_irq24mon_field_t IRQ24MON_f;\r
+  };\r
+  union {\r
+    __IO uint32_t IRQ25MON;\r
+    stc_intreq_irq25mon_field_t IRQ25MON_f;\r
+  };\r
+  union {\r
+    __IO uint32_t IRQ26MON;\r
+    stc_intreq_irq26mon_field_t IRQ26MON_f;\r
+  };\r
+  __IO uint32_t IRQ27MON;\r
+  union {\r
+    __IO uint32_t IRQ28MON;\r
+    stc_intreq_irq28mon_field_t IRQ28MON_f;\r
+  };\r
+  union {\r
+    __IO uint32_t IRQ29MON;\r
+    stc_intreq_irq29mon_field_t IRQ29MON_f;\r
+  };\r
+  union {\r
+    __IO uint32_t IRQ30MON;\r
+    stc_intreq_irq30mon_field_t IRQ30MON_f;\r
+  };\r
+  union {\r
+    __IO uint32_t IRQ31MON;\r
+    stc_intreq_irq31mon_field_t IRQ31MON_f;\r
+  };\r
+  __IO uint32_t IRQ32MON;\r
+  __IO uint32_t IRQ33MON;\r
+  union {\r
+    __IO uint32_t IRQ34MON;\r
+    stc_intreq_irq34mon_field_t IRQ34MON_f;\r
+  };\r
+  union {\r
+    __IO uint32_t IRQ35MON;\r
+    stc_intreq_irq35mon_field_t IRQ35MON_f;\r
+  };\r
+  __IO uint32_t IRQ36MON;\r
+  __IO uint32_t IRQ37MON;\r
+  union {\r
+    __IO uint32_t IRQ38MON;\r
+    stc_intreq_irq38mon_field_t IRQ38MON_f;\r
+  };\r
+  union {\r
+    __IO uint32_t IRQ39MON;\r
+    stc_intreq_irq39mon_field_t IRQ39MON_f;\r
+  };\r
+  union {\r
+    __IO uint32_t IRQ40MON;\r
+    stc_intreq_irq40mon_field_t IRQ40MON_f;\r
+  };\r
+  union {\r
+    __IO uint32_t IRQ41MON;\r
+    stc_intreq_irq41mon_field_t IRQ41MON_f;\r
+  };\r
+  union {\r
+    __IO uint32_t IRQ42MON;\r
+    stc_intreq_irq42mon_field_t IRQ42MON_f;\r
+  };\r
+  union {\r
+    __IO uint32_t IRQ43MON;\r
+    stc_intreq_irq43mon_field_t IRQ43MON_f;\r
+  };\r
+  union {\r
+    __IO uint32_t IRQ44MON;\r
+    stc_intreq_irq44mon_field_t IRQ44MON_f;\r
+  };\r
+  union {\r
+    __IO uint32_t IRQ45MON;\r
+    stc_intreq_irq45mon_field_t IRQ45MON_f;\r
+  };\r
+  __IO uint32_t IRQ46MON;\r
+  __IO uint32_t IRQ47MON;\r
+}FM3_INTREQ_TypeDef;\r
+\r
+/******************************************************************************\r
+ * GPIO_MODULE\r
+ ******************************************************************************/\r
+/* General purpose I/O registers */\r
+typedef struct\r
+{\r
+  union {\r
+    __IO uint32_t PFR0;\r
+    stc_gpio_pfr0_field_t PFR0_f;\r
+  };\r
+  union {\r
+    __IO uint32_t PFR1;\r
+    stc_gpio_pfr1_field_t PFR1_f;\r
+  };\r
+  union {\r
+    __IO uint32_t PFR2;\r
+    stc_gpio_pfr2_field_t PFR2_f;\r
+  };\r
+  union {\r
+    __IO uint32_t PFR3;\r
+    stc_gpio_pfr3_field_t PFR3_f;\r
+  };\r
+  union {\r
+    __IO uint32_t PFR4;\r
+    stc_gpio_pfr4_field_t PFR4_f;\r
+  };\r
+  union {\r
+    __IO uint32_t PFR5;\r
+    stc_gpio_pfr5_field_t PFR5_f;\r
+  };\r
+  union {\r
+    __IO uint32_t PFR6;\r
+    stc_gpio_pfr6_field_t PFR6_f;\r
+  };\r
+        uint8_t RESERVED0[4];\r
+  union {\r
+    __IO uint32_t PFR8;\r
+    stc_gpio_pfr8_field_t PFR8_f;\r
+  };\r
+        uint8_t RESERVED1[20];\r
+  union {\r
+    __IO uint32_t PFRE;\r
+    stc_gpio_pfre_field_t PFRE_f;\r
+  };\r
+        uint8_t RESERVED2[196];\r
+  union {\r
+    __IO uint32_t PCR0;\r
+    stc_gpio_pcr0_field_t PCR0_f;\r
+  };\r
+  union {\r
+    __IO uint32_t PCR1;\r
+    stc_gpio_pcr1_field_t PCR1_f;\r
+  };\r
+  union {\r
+    __IO uint32_t PCR2;\r
+    stc_gpio_pcr2_field_t PCR2_f;\r
+  };\r
+  union {\r
+    __IO uint32_t PCR3;\r
+    stc_gpio_pcr3_field_t PCR3_f;\r
+  };\r
+  union {\r
+    __IO uint32_t PCR4;\r
+    stc_gpio_pcr4_field_t PCR4_f;\r
+  };\r
+  union {\r
+    __IO uint32_t PCR5;\r
+    stc_gpio_pcr5_field_t PCR5_f;\r
+  };\r
+  union {\r
+    __IO uint32_t PCR6;\r
+    stc_gpio_pcr6_field_t PCR6_f;\r
+  };\r
+        uint8_t RESERVED3[28];\r
+  union {\r
+    __IO uint32_t PCRE;\r
+    stc_gpio_pcre_field_t PCRE_f;\r
+  };\r
+        uint8_t RESERVED4[196];\r
+  union {\r
+    __IO uint32_t DDR0;\r
+    stc_gpio_ddr0_field_t DDR0_f;\r
+  };\r
+  union {\r
+    __IO uint32_t DDR1;\r
+    stc_gpio_ddr1_field_t DDR1_f;\r
+  };\r
+  union {\r
+    __IO uint32_t DDR2;\r
+    stc_gpio_ddr2_field_t DDR2_f;\r
+  };\r
+  union {\r
+    __IO uint32_t DDR3;\r
+    stc_gpio_ddr3_field_t DDR3_f;\r
+  };\r
+  union {\r
+    __IO uint32_t DDR4;\r
+    stc_gpio_ddr4_field_t DDR4_f;\r
+  };\r
+  union {\r
+    __IO uint32_t DDR5;\r
+    stc_gpio_ddr5_field_t DDR5_f;\r
+  };\r
+  union {\r
+    __IO uint32_t DDR6;\r
+    stc_gpio_ddr6_field_t DDR6_f;\r
+  };\r
+        uint8_t RESERVED5[4];\r
+  union {\r
+    __IO uint32_t DDR8;\r
+    stc_gpio_ddr8_field_t DDR8_f;\r
+  };\r
+        uint8_t RESERVED6[20];\r
+  union {\r
+    __IO uint32_t DDRE;\r
+    stc_gpio_ddre_field_t DDRE_f;\r
+  };\r
+        uint8_t RESERVED7[196];\r
+  union {\r
+    __IO uint32_t PDIR0;\r
+    stc_gpio_pdir0_field_t PDIR0_f;\r
+  };\r
+  union {\r
+    __IO uint32_t PDIR1;\r
+    stc_gpio_pdir1_field_t PDIR1_f;\r
+  };\r
+  union {\r
+    __IO uint32_t PDIR2;\r
+    stc_gpio_pdir2_field_t PDIR2_f;\r
+  };\r
+  union {\r
+    __IO uint32_t PDIR3;\r
+    stc_gpio_pdir3_field_t PDIR3_f;\r
+  };\r
+  union {\r
+    __IO uint32_t PDIR4;\r
+    stc_gpio_pdir4_field_t PDIR4_f;\r
+  };\r
+  union {\r
+    __IO uint32_t PDIR5;\r
+    stc_gpio_pdir5_field_t PDIR5_f;\r
+  };\r
+  union {\r
+    __IO uint32_t PDIR6;\r
+    stc_gpio_pdir6_field_t PDIR6_f;\r
+  };\r
+        uint8_t RESERVED8[4];\r
+  union {\r
+    __IO uint32_t PDIR8;\r
+    stc_gpio_pdir8_field_t PDIR8_f;\r
+  };\r
+        uint8_t RESERVED9[20];\r
+  union {\r
+    __IO uint32_t PDIRE;\r
+    stc_gpio_pdire_field_t PDIRE_f;\r
+  };\r
+        uint8_t RESERVED10[196];\r
+  union {\r
+    __IO uint32_t PDOR0;\r
+    stc_gpio_pdor0_field_t PDOR0_f;\r
+  };\r
+  union {\r
+    __IO uint32_t PDOR1;\r
+    stc_gpio_pdor1_field_t PDOR1_f;\r
+  };\r
+  union {\r
+    __IO uint32_t PDOR2;\r
+    stc_gpio_pdor2_field_t PDOR2_f;\r
+  };\r
+  union {\r
+    __IO uint32_t PDOR3;\r
+    stc_gpio_pdor3_field_t PDOR3_f;\r
+  };\r
+  union {\r
+    __IO uint32_t PDOR4;\r
+    stc_gpio_pdor4_field_t PDOR4_f;\r
+  };\r
+  union {\r
+    __IO uint32_t PDOR5;\r
+    stc_gpio_pdor5_field_t PDOR5_f;\r
+  };\r
+  union {\r
+    __IO uint32_t PDOR6;\r
+    stc_gpio_pdor6_field_t PDOR6_f;\r
+  };\r
+        uint8_t RESERVED11[4];\r
+  union {\r
+    __IO uint32_t PDOR8;\r
+    stc_gpio_pdor8_field_t PDOR8_f;\r
+  };\r
+        uint8_t RESERVED12[20];\r
+  union {\r
+    __IO uint32_t PDORE;\r
+    stc_gpio_pdore_field_t PDORE_f;\r
+  };\r
+        uint8_t RESERVED13[196];\r
+  union {\r
+    __IO uint32_t ADE;\r
+    stc_gpio_ade_field_t ADE_f;\r
+  };\r
+        uint8_t RESERVED14[124];\r
+  union {\r
+    __IO uint32_t SPSR;\r
+    stc_gpio_spsr_field_t SPSR_f;\r
+  };\r
+        uint8_t RESERVED15[124];\r
+  union {\r
+    __IO uint32_t EPFR00;\r
+    stc_gpio_epfr00_field_t EPFR00_f;\r
+  };\r
+  union {\r
+    __IO uint32_t EPFR01;\r
+    stc_gpio_epfr01_field_t EPFR01_f;\r
+  };\r
+        uint8_t RESERVED16[8];\r
+  union {\r
+    __IO uint32_t EPFR04;\r
+    stc_gpio_epfr04_field_t EPFR04_f;\r
+  };\r
+  union {\r
+    __IO uint32_t EPFR05;\r
+    stc_gpio_epfr05_field_t EPFR05_f;\r
+  };\r
+  union {\r
+    __IO uint32_t EPFR06;\r
+    stc_gpio_epfr06_field_t EPFR06_f;\r
+  };\r
+  union {\r
+    __IO uint32_t EPFR07;\r
+    stc_gpio_epfr07_field_t EPFR07_f;\r
+  };\r
+  union {\r
+    __IO uint32_t EPFR08;\r
+    stc_gpio_epfr08_field_t EPFR08_f;\r
+  };\r
+  union {\r
+    __IO uint32_t EPFR09;\r
+    stc_gpio_epfr09_field_t EPFR09_f;\r
+  };\r
+}FM3_GPIO_TypeDef;\r
+\r
+/******************************************************************************\r
+ * LVD_MODULE\r
+ ******************************************************************************/\r
+/* Low voltage detection registers */\r
+typedef struct\r
+{\r
+  union {\r
+    __IO  uint8_t LVD_CTL;\r
+    stc_lvd_lvd_ctl_field_t LVD_CTL_f;\r
+  };\r
+        uint8_t RESERVED0[3];\r
+  union {\r
+    __IO  uint8_t LVD_STR;\r
+    stc_lvd_lvd_str_field_t LVD_STR_f;\r
+  };\r
+        uint8_t RESERVED1[3];\r
+  union {\r
+    __IO  uint8_t LVD_CLR;\r
+    stc_lvd_lvd_clr_field_t LVD_CLR_f;\r
+  };\r
+        uint8_t RESERVED2[3];\r
+  __IO uint32_t LVD_RLR;\r
+  union {\r
+    __IO  uint8_t LVD_STR2;\r
+    stc_lvd_lvd_str2_field_t LVD_STR2_f;\r
+  };\r
+}FM3_LVD_TypeDef;\r
+\r
+/******************************************************************************\r
+ * USBCLK\r
+ ******************************************************************************/\r
+/* USB clock registers */\r
+typedef struct\r
+{\r
+  union {\r
+    __IO  uint8_t UCCR;\r
+    stc_usbclk_uccr_field_t UCCR_f;\r
+  };\r
+        uint8_t RESERVED0[3];\r
+  union {\r
+    __IO  uint8_t UPCR1;\r
+    stc_usbclk_upcr1_field_t UPCR1_f;\r
+  };\r
+        uint8_t RESERVED1[3];\r
+  union {\r
+    __IO  uint8_t UPCR2;\r
+    stc_usbclk_upcr2_field_t UPCR2_f;\r
+  };\r
+        uint8_t RESERVED2[3];\r
+  union {\r
+    __IO  uint8_t UPCR3;\r
+    stc_usbclk_upcr3_field_t UPCR3_f;\r
+  };\r
+        uint8_t RESERVED3[3];\r
+  union {\r
+    __IO  uint8_t UPCR4;\r
+    stc_usbclk_upcr4_field_t UPCR4_f;\r
+  };\r
+        uint8_t RESERVED4[3];\r
+  union {\r
+    __IO  uint8_t UP_STR;\r
+    stc_usbclk_up_str_field_t UP_STR_f;\r
+  };\r
+        uint8_t RESERVED5[3];\r
+  union {\r
+    __IO  uint8_t UPINT_ENR;\r
+    stc_usbclk_upint_enr_field_t UPINT_ENR_f;\r
+  };\r
+        uint8_t RESERVED6[3];\r
+  union {\r
+    __IO  uint8_t UPINT_CLR;\r
+    stc_usbclk_upint_clr_field_t UPINT_CLR_f;\r
+  };\r
+        uint8_t RESERVED7[3];\r
+  union {\r
+    __IO  uint8_t UPINT_STR;\r
+    stc_usbclk_upint_str_field_t UPINT_STR_f;\r
+  };\r
+        uint8_t RESERVED8[3];\r
+  union {\r
+    __IO  uint8_t UPCR5;\r
+    stc_usbclk_upcr5_field_t UPCR5_f;\r
+  };\r
+        uint8_t RESERVED9[11];\r
+  union {\r
+    __IO  uint8_t USBEN;\r
+    stc_usbclk_usben_field_t USBEN_f;\r
+  };\r
+}FM3_USBCLK_TypeDef;\r
+\r
+/******************************************************************************\r
+ * MFS03_UART_MODULE\r
+ ******************************************************************************/\r
+/* UART asynchronous channel 0 registers */\r
+typedef struct\r
+{\r
+  union {\r
+    __IO  uint8_t SMR;\r
+    stc_mfs03_uart_smr_field_t SMR_f;\r
+  };\r
+  union {\r
+    __IO  uint8_t SCR;\r
+    stc_mfs03_uart_scr_field_t SCR_f;\r
+  };\r
+        uint8_t RESERVED0[2];\r
+  union {\r
+    __IO  uint8_t ESCR;\r
+    stc_mfs03_uart_escr_field_t ESCR_f;\r
+  };\r
+  union {\r
+    __IO  uint8_t SSR;\r
+    stc_mfs03_uart_ssr_field_t SSR_f;\r
+  };\r
+        uint8_t RESERVED1[2];\r
+  union {\r
+    union {\r
+      __IO uint16_t RDR;\r
+      stc_mfs03_uart_rdr_field_t RDR_f;\r
+    };\r
+    union {\r
+      __IO uint16_t TDR;\r
+      stc_mfs03_uart_tdr_field_t TDR_f;\r
+    };\r
+  };\r
+        uint8_t RESERVED2[2];\r
+  union {\r
+    union {\r
+      __IO uint16_t BGR;\r
+      stc_mfs03_uart_bgr_field_t BGR_f;\r
+    };\r
+    struct {\r
+      __IO  uint8_t BGR0;\r
+      union {\r
+        __IO  uint8_t BGR1;\r
+        stc_mfs03_uart_bgr1_field_t BGR1_f;\r
+      };\r
+    };\r
+  };\r
+}FM3_MFS03_UART_TypeDef;\r
+\r
+/******************************************************************************\r
+ * MFS03_CSIO_MODULE\r
+ ******************************************************************************/\r
+/* UART synchronous channel 0 registers */\r
+typedef struct\r
+{\r
+  union {\r
+    __IO  uint8_t SMR;\r
+    stc_mfs03_csio_smr_field_t SMR_f;\r
+  };\r
+  union {\r
+    __IO  uint8_t SCR;\r
+    stc_mfs03_csio_scr_field_t SCR_f;\r
+  };\r
+        uint8_t RESERVED0[2];\r
+  union {\r
+    __IO  uint8_t ESCR;\r
+    stc_mfs03_csio_escr_field_t ESCR_f;\r
+  };\r
+  union {\r
+    __IO  uint8_t SSR;\r
+    stc_mfs03_csio_ssr_field_t SSR_f;\r
+  };\r
+        uint8_t RESERVED1[2];\r
+  union {\r
+    __IO uint16_t RDR;\r
+    __IO uint16_t TDR;\r
+  };\r
+        uint8_t RESERVED2[2];\r
+  union {\r
+    __IO uint16_t BGR;\r
+    struct {\r
+      __IO  uint8_t BGR0;\r
+      __IO  uint8_t BGR1;\r
+    };\r
+  };\r
+}FM3_MFS03_CSIO_TypeDef;\r
+\r
+/******************************************************************************\r
+ * MFS03_LIN_MODULE\r
+ ******************************************************************************/\r
+/* UART LIN channel 0 registers */\r
+typedef struct\r
+{\r
+  union {\r
+    __IO  uint8_t SMR;\r
+    stc_mfs03_lin_smr_field_t SMR_f;\r
+  };\r
+  union {\r
+    __IO  uint8_t SCR;\r
+    stc_mfs03_lin_scr_field_t SCR_f;\r
+  };\r
+        uint8_t RESERVED0[2];\r
+  union {\r
+    __IO  uint8_t ESCR;\r
+    stc_mfs03_lin_escr_field_t ESCR_f;\r
+  };\r
+  union {\r
+    __IO  uint8_t SSR;\r
+    stc_mfs03_lin_ssr_field_t SSR_f;\r
+  };\r
+        uint8_t RESERVED1[2];\r
+  union {\r
+    __IO uint16_t RDR;\r
+    __IO uint16_t TDR;\r
+  };\r
+        uint8_t RESERVED2[2];\r
+  union {\r
+    union {\r
+      __IO uint16_t BGR;\r
+      stc_mfs03_lin_bgr_field_t BGR_f;\r
+    };\r
+    struct {\r
+      __IO  uint8_t BGR0;\r
+      union {\r
+        __IO  uint8_t BGR1;\r
+        stc_mfs03_lin_bgr1_field_t BGR1_f;\r
+      };\r
+    };\r
+  };\r
+}FM3_MFS03_LIN_TypeDef;\r
+\r
+/******************************************************************************\r
+ * MFS03_I2C_MODULE\r
+ ******************************************************************************/\r
+/* I2C channel 0 registers */\r
+typedef struct\r
+{\r
+  union {\r
+    __IO  uint8_t SMR;\r
+    stc_mfs03_i2c_smr_field_t SMR_f;\r
+  };\r
+  union {\r
+    __IO  uint8_t IBCR;\r
+    stc_mfs03_i2c_ibcr_field_t IBCR_f;\r
+  };\r
+        uint8_t RESERVED0[2];\r
+  union {\r
+    __IO  uint8_t IBSR;\r
+    stc_mfs03_i2c_ibsr_field_t IBSR_f;\r
+  };\r
+  union {\r
+    __IO  uint8_t SSR;\r
+    stc_mfs03_i2c_ssr_field_t SSR_f;\r
+  };\r
+        uint8_t RESERVED1[2];\r
+  union {\r
+    __IO uint16_t RDR;\r
+    __IO uint16_t TDR;\r
+  };\r
+        uint8_t RESERVED2[2];\r
+  union {\r
+    __IO uint16_t BGR;\r
+    struct {\r
+      __IO  uint8_t BGR0;\r
+      __IO  uint8_t BGR1;\r
+    };\r
+  };\r
+        uint8_t RESERVED3[2];\r
+  union {\r
+    __IO  uint8_t ISBA;\r
+    stc_mfs03_i2c_isba_field_t ISBA_f;\r
+  };\r
+  union {\r
+    __IO  uint8_t ISMK;\r
+    stc_mfs03_i2c_ismk_field_t ISMK_f;\r
+  };\r
+}FM3_MFS03_I2C_TypeDef;\r
+\r
+/******************************************************************************\r
+ * MFS47_UART_MODULE\r
+ ******************************************************************************/\r
+/* UART asynchronous channel 4 registers */\r
+typedef struct\r
+{\r
+  union {\r
+    __IO  uint8_t SMR;\r
+    stc_mfs47_uart_smr_field_t SMR_f;\r
+  };\r
+  union {\r
+    __IO  uint8_t SCR;\r
+    stc_mfs47_uart_scr_field_t SCR_f;\r
+  };\r
+        uint8_t RESERVED0[2];\r
+  union {\r
+    __IO  uint8_t ESCR;\r
+    stc_mfs47_uart_escr_field_t ESCR_f;\r
+  };\r
+  union {\r
+    __IO  uint8_t SSR;\r
+    stc_mfs47_uart_ssr_field_t SSR_f;\r
+  };\r
+        uint8_t RESERVED1[2];\r
+  union {\r
+    union {\r
+      __IO uint16_t RDR;\r
+      stc_mfs47_uart_rdr_field_t RDR_f;\r
+    };\r
+    union {\r
+      __IO uint16_t TDR;\r
+      stc_mfs47_uart_tdr_field_t TDR_f;\r
+    };\r
+  };\r
+        uint8_t RESERVED2[2];\r
+  union {\r
+    union {\r
+      __IO uint16_t BGR;\r
+      stc_mfs47_uart_bgr_field_t BGR_f;\r
+    };\r
+    struct {\r
+      __IO  uint8_t BGR0;\r
+      union {\r
+        __IO  uint8_t BGR1;\r
+        stc_mfs47_uart_bgr1_field_t BGR1_f;\r
+      };\r
+    };\r
+  };\r
+        uint8_t RESERVED3[6];\r
+  union {\r
+    union {\r
+      __IO uint16_t FCR;\r
+      stc_mfs47_uart_fcr_field_t FCR_f;\r
+    };\r
+    struct {\r
+      union {\r
+        __IO  uint8_t FCR0;\r
+        stc_mfs47_uart_fcr0_field_t FCR0_f;\r
+      };\r
+      union {\r
+        __IO  uint8_t FCR1;\r
+        stc_mfs47_uart_fcr1_field_t FCR1_f;\r
+      };\r
+    };\r
+  };\r
+        uint8_t RESERVED4[2];\r
+  union {\r
+    union {\r
+      __IO uint16_t FBYTE;\r
+      stc_mfs47_uart_fbyte_field_t FBYTE_f;\r
+    };\r
+    struct {\r
+      union {\r
+        __IO  uint8_t FBYTE1;\r
+        stc_mfs47_uart_fbyte1_field_t FBYTE1_f;\r
+      };\r
+      union {\r
+        __IO  uint8_t FBYTE2;\r
+        stc_mfs47_uart_fbyte2_field_t FBYTE2_f;\r
+      };\r
+    };\r
+  };\r
+}FM3_MFS47_UART_TypeDef;\r
+\r
+/******************************************************************************\r
+ * MFS47_CSIO_MODULE\r
+ ******************************************************************************/\r
+/* UART synchronous channel 4 registers */\r
+typedef struct\r
+{\r
+  union {\r
+    __IO  uint8_t SMR;\r
+    stc_mfs47_csio_smr_field_t SMR_f;\r
+  };\r
+  union {\r
+    __IO  uint8_t SCR;\r
+    stc_mfs47_csio_scr_field_t SCR_f;\r
+  };\r
+        uint8_t RESERVED0[2];\r
+  union {\r
+    __IO  uint8_t ESCR;\r
+    stc_mfs47_csio_escr_field_t ESCR_f;\r
+  };\r
+  union {\r
+    __IO  uint8_t SSR;\r
+    stc_mfs47_csio_ssr_field_t SSR_f;\r
+  };\r
+        uint8_t RESERVED1[2];\r
+  union {\r
+    __IO uint16_t RDR;\r
+    __IO uint16_t TDR;\r
+  };\r
+        uint8_t RESERVED2[2];\r
+  union {\r
+    __IO uint16_t BGR;\r
+    struct {\r
+      __IO  uint8_t BGR0;\r
+      __IO  uint8_t BGR1;\r
+    };\r
+  };\r
+        uint8_t RESERVED3[6];\r
+  union {\r
+    union {\r
+      __IO uint16_t FCR;\r
+      stc_mfs47_csio_fcr_field_t FCR_f;\r
+    };\r
+    struct {\r
+      union {\r
+        __IO  uint8_t FCR0;\r
+        stc_mfs47_csio_fcr0_field_t FCR0_f;\r
+      };\r
+      union {\r
+        __IO  uint8_t FCR1;\r
+        stc_mfs47_csio_fcr1_field_t FCR1_f;\r
+      };\r
+    };\r
+  };\r
+        uint8_t RESERVED4[2];\r
+  union {\r
+    union {\r
+      __IO uint16_t FBYTE;\r
+      stc_mfs47_csio_fbyte_field_t FBYTE_f;\r
+    };\r
+    struct {\r
+      union {\r
+        __IO  uint8_t FBYTE1;\r
+        stc_mfs47_csio_fbyte1_field_t FBYTE1_f;\r
+      };\r
+      union {\r
+        __IO  uint8_t FBYTE2;\r
+        stc_mfs47_csio_fbyte2_field_t FBYTE2_f;\r
+      };\r
+    };\r
+  };\r
+}FM3_MFS47_CSIO_TypeDef;\r
+\r
+/******************************************************************************\r
+ * MFS47_LIN_MODULE\r
+ ******************************************************************************/\r
+/* UART LIN channel 4 registers */\r
+typedef struct\r
+{\r
+  union {\r
+    __IO  uint8_t SMR;\r
+    stc_mfs47_lin_smr_field_t SMR_f;\r
+  };\r
+  union {\r
+    __IO  uint8_t SCR;\r
+    stc_mfs47_lin_scr_field_t SCR_f;\r
+  };\r
+        uint8_t RESERVED0[2];\r
+  union {\r
+    __IO  uint8_t ESCR;\r
+    stc_mfs47_lin_escr_field_t ESCR_f;\r
+  };\r
+  union {\r
+    __IO  uint8_t SSR;\r
+    stc_mfs47_lin_ssr_field_t SSR_f;\r
+  };\r
+        uint8_t RESERVED1[2];\r
+  union {\r
+    __IO uint16_t RDR;\r
+    __IO uint16_t TDR;\r
+  };\r
+        uint8_t RESERVED2[2];\r
+  union {\r
+    union {\r
+      __IO uint16_t BGR;\r
+      stc_mfs47_lin_bgr_field_t BGR_f;\r
+    };\r
+    struct {\r
+      __IO  uint8_t BGR0;\r
+      union {\r
+        __IO  uint8_t BGR1;\r
+        stc_mfs47_lin_bgr1_field_t BGR1_f;\r
+      };\r
+    };\r
+  };\r
+        uint8_t RESERVED3[6];\r
+  union {\r
+    union {\r
+      __IO uint16_t FCR;\r
+      stc_mfs47_lin_fcr_field_t FCR_f;\r
+    };\r
+    struct {\r
+      union {\r
+        __IO  uint8_t FCR0;\r
+        stc_mfs47_lin_fcr0_field_t FCR0_f;\r
+      };\r
+      union {\r
+        __IO  uint8_t FCR1;\r
+        stc_mfs47_lin_fcr1_field_t FCR1_f;\r
+      };\r
+    };\r
+  };\r
+        uint8_t RESERVED4[2];\r
+  union {\r
+    union {\r
+      __IO uint16_t FBYTE;\r
+      stc_mfs47_lin_fbyte_field_t FBYTE_f;\r
+    };\r
+    struct {\r
+      union {\r
+        __IO  uint8_t FBYTE1;\r
+        stc_mfs47_lin_fbyte1_field_t FBYTE1_f;\r
+      };\r
+      union {\r
+        __IO  uint8_t FBYTE2;\r
+        stc_mfs47_lin_fbyte2_field_t FBYTE2_f;\r
+      };\r
+    };\r
+  };\r
+}FM3_MFS47_LIN_TypeDef;\r
+\r
+/******************************************************************************\r
+ * MFS47_I2C_MODULE\r
+ ******************************************************************************/\r
+/* I2C channel 4 registers */\r
+typedef struct\r
+{\r
+  union {\r
+    __IO  uint8_t SMR;\r
+    stc_mfs47_i2c_smr_field_t SMR_f;\r
+  };\r
+  union {\r
+    __IO  uint8_t IBCR;\r
+    stc_mfs47_i2c_ibcr_field_t IBCR_f;\r
+  };\r
+        uint8_t RESERVED0[2];\r
+  union {\r
+    __IO  uint8_t IBSR;\r
+    stc_mfs47_i2c_ibsr_field_t IBSR_f;\r
+  };\r
+  union {\r
+    __IO  uint8_t SSR;\r
+    stc_mfs47_i2c_ssr_field_t SSR_f;\r
+  };\r
+        uint8_t RESERVED1[2];\r
+  union {\r
+    __IO uint16_t RDR;\r
+    __IO uint16_t TDR;\r
+  };\r
+        uint8_t RESERVED2[2];\r
+  union {\r
+    __IO uint16_t BGR;\r
+    struct {\r
+      __IO  uint8_t BGR0;\r
+      __IO  uint8_t BGR1;\r
+    };\r
+  };\r
+        uint8_t RESERVED3[2];\r
+  union {\r
+    __IO  uint8_t ISBA;\r
+    stc_mfs47_i2c_isba_field_t ISBA_f;\r
+  };\r
+  union {\r
+    __IO  uint8_t ISMK;\r
+    stc_mfs47_i2c_ismk_field_t ISMK_f;\r
+  };\r
+        uint8_t RESERVED4[2];\r
+  union {\r
+    union {\r
+      __IO uint16_t FCR;\r
+      stc_mfs47_i2c_fcr_field_t FCR_f;\r
+    };\r
+    struct {\r
+      union {\r
+        __IO  uint8_t FCR0;\r
+        stc_mfs47_i2c_fcr0_field_t FCR0_f;\r
+      };\r
+      union {\r
+        __IO  uint8_t FCR1;\r
+        stc_mfs47_i2c_fcr1_field_t FCR1_f;\r
+      };\r
+    };\r
+  };\r
+        uint8_t RESERVED5[2];\r
+  union {\r
+    union {\r
+      __IO uint16_t FBYTE;\r
+      stc_mfs47_i2c_fbyte_field_t FBYTE_f;\r
+    };\r
+    struct {\r
+      union {\r
+        __IO  uint8_t FBYTE1;\r
+        stc_mfs47_i2c_fbyte1_field_t FBYTE1_f;\r
+      };\r
+      union {\r
+        __IO  uint8_t FBYTE2;\r
+        stc_mfs47_i2c_fbyte2_field_t FBYTE2_f;\r
+      };\r
+    };\r
+  };\r
+}FM3_MFS47_I2C_TypeDef;\r
+\r
+/******************************************************************************\r
+ * CRC_MODULE\r
+ ******************************************************************************/\r
+/* CRC registers */\r
+typedef struct\r
+{\r
+  union {\r
+    __IO  uint8_t CRCCR;\r
+    stc_crc_crccr_field_t CRCCR_f;\r
+  };\r
+        uint8_t RESERVED0[3];\r
+  __IO uint32_t CRCINIT;\r
+  union {\r
+    __IO uint32_t CRCIN;\r
+    struct {\r
+      union {\r
+        __IO uint16_t CRCINL;\r
+        struct {\r
+          __IO  uint8_t CRCINLL;\r
+          __IO  uint8_t CRCINLH;\r
+        };\r
+      };\r
+      union {\r
+        __IO uint16_t CRCINH;\r
+        struct {\r
+          __IO  uint8_t CRCINHL;\r
+          __IO  uint8_t CRCINHH;\r
+        };\r
+      };\r
+    };\r
+  };\r
+  __IO uint32_t CRCR;\r
+}FM3_CRC_TypeDef;\r
+\r
+/******************************************************************************\r
+ * WC_MODULE\r
+ ******************************************************************************/\r
+/* Watch counter registers */\r
+typedef struct\r
+{\r
+  union {\r
+    __IO  uint8_t WCRD;\r
+    stc_wc_wcrd_field_t WCRD_f;\r
+  };\r
+  union {\r
+    __IO  uint8_t WCRL;\r
+    stc_wc_wcrl_field_t WCRL_f;\r
+  };\r
+  union {\r
+    __IO  uint8_t WCCR;\r
+    stc_wc_wccr_field_t WCCR_f;\r
+  };\r
+        uint8_t RESERVED0[13];\r
+  union {\r
+    __IO uint16_t CLK_SEL;\r
+    stc_wc_clk_sel_field_t CLK_SEL_f;\r
+  };\r
+        uint8_t RESERVED1[2];\r
+  union {\r
+    __IO  uint8_t CLK_EN;\r
+    stc_wc_clk_en_field_t CLK_EN_f;\r
+  };\r
+}FM3_WC_TypeDef;\r
+\r
+/******************************************************************************\r
+ * USB_MODULE\r
+ ******************************************************************************/\r
+/* USB channel 0 registers */\r
+typedef struct\r
+{\r
+  union {\r
+    union {\r
+      __IO uint16_t HCNT;\r
+      stc_usb_hcnt_field_t HCNT_f;\r
+    };\r
+    struct {\r
+      union {\r
+        __IO  uint8_t HCNT0;\r
+        stc_usb_hcnt0_field_t HCNT0_f;\r
+      };\r
+      union {\r
+        __IO  uint8_t HCNT1;\r
+        stc_usb_hcnt1_field_t HCNT1_f;\r
+      };\r
+    };\r
+  };\r
+        uint8_t RESERVED0[2];\r
+  union {\r
+    __IO  uint8_t HIRQ;\r
+    stc_usb_hirq_field_t HIRQ_f;\r
+  };\r
+  union {\r
+    __IO  uint8_t HERR;\r
+    stc_usb_herr_field_t HERR_f;\r
+  };\r
+        uint8_t RESERVED1[2];\r
+  union {\r
+    __IO  uint8_t HSTATE;\r
+    stc_usb_hstate_field_t HSTATE_f;\r
+  };\r
+  union {\r
+    __IO  uint8_t HFCOMP;\r
+    stc_usb_hfcomp_field_t HFCOMP_f;\r
+  };\r
+        uint8_t RESERVED2[2];\r
+  union {\r
+    union {\r
+      __IO uint16_t HRTIMER;\r
+      stc_usb_hrtimer_field_t HRTIMER_f;\r
+    };\r
+    struct {\r
+      union {\r
+        __IO  uint8_t HRTIMER0;\r
+        stc_usb_hrtimer0_field_t HRTIMER0_f;\r
+      };\r
+      union {\r
+        __IO  uint8_t HRTIMER1;\r
+        stc_usb_hrtimer1_field_t HRTIMER1_f;\r
+      };\r
+    };\r
+  };\r
+        uint8_t RESERVED3[2];\r
+  union {\r
+    __IO  uint8_t HRTIMER2;\r
+    stc_usb_hrtimer2_field_t HRTIMER2_f;\r
+  };\r
+  union {\r
+    __IO  uint8_t HADR;\r
+    stc_usb_hadr_field_t HADR_f;\r
+  };\r
+        uint8_t RESERVED4[2];\r
+  union {\r
+    union {\r
+      __IO uint16_t HEOF;\r
+      stc_usb_heof_field_t HEOF_f;\r
+    };\r
+    struct {\r
+      union {\r
+        __IO  uint8_t HEOF0;\r
+        stc_usb_heof0_field_t HEOF0_f;\r
+      };\r
+      union {\r
+        __IO  uint8_t HEOF1;\r
+        stc_usb_heof1_field_t HEOF1_f;\r
+      };\r
+    };\r
+  };\r
+        uint8_t RESERVED5[2];\r
+  union {\r
+    union {\r
+      __IO uint16_t HFRAME;\r
+      stc_usb_hframe_field_t HFRAME_f;\r
+    };\r
+    struct {\r
+      union {\r
+        __IO  uint8_t HFRAME0;\r
+        stc_usb_hframe0_field_t HFRAME0_f;\r
+      };\r
+      union {\r
+        __IO  uint8_t HFRAME1;\r
+        stc_usb_hframe1_field_t HFRAME1_f;\r
+      };\r
+    };\r
+  };\r
+        uint8_t RESERVED6[2];\r
+  union {\r
+    __IO  uint8_t HTOKEN;\r
+    stc_usb_htoken_field_t HTOKEN_f;\r
+  };\r
+        uint8_t RESERVED7[3];\r
+  union {\r
+    __IO uint16_t UDCC;\r
+    stc_usb_udcc_field_t UDCC_f;\r
+  };\r
+        uint8_t RESERVED8[2];\r
+  union {\r
+    __IO uint16_t EP0C;\r
+    stc_usb_ep0c_field_t EP0C_f;\r
+  };\r
+        uint8_t RESERVED9[2];\r
+  union {\r
+    __IO uint16_t EP1C;\r
+    stc_usb_ep1c_field_t EP1C_f;\r
+  };\r
+        uint8_t RESERVED10[2];\r
+  union {\r
+    __IO uint16_t EP2C;\r
+    stc_usb_ep2c_field_t EP2C_f;\r
+  };\r
+        uint8_t RESERVED11[2];\r
+  union {\r
+    __IO uint16_t EP3C;\r
+    stc_usb_ep3c_field_t EP3C_f;\r
+  };\r
+        uint8_t RESERVED12[2];\r
+  union {\r
+    __IO uint16_t EP4C;\r
+    stc_usb_ep4c_field_t EP4C_f;\r
+  };\r
+        uint8_t RESERVED13[2];\r
+  union {\r
+    __IO uint16_t EP5C;\r
+    stc_usb_ep5c_field_t EP5C_f;\r
+  };\r
+        uint8_t RESERVED14[2];\r
+  union {\r
+    __IO uint16_t TMSP;\r
+    stc_usb_tmsp_field_t TMSP_f;\r
+  };\r
+        uint8_t RESERVED15[2];\r
+  union {\r
+    __IO  uint8_t UDCS;\r
+    stc_usb_udcs_field_t UDCS_f;\r
+  };\r
+  union {\r
+    __IO  uint8_t UDCIE;\r
+    stc_usb_udcie_field_t UDCIE_f;\r
+  };\r
+        uint8_t RESERVED16[2];\r
+  union {\r
+    __IO uint16_t EP0IS;\r
+    stc_usb_ep0is_field_t EP0IS_f;\r
+  };\r
+        uint8_t RESERVED17[2];\r
+  union {\r
+    __IO uint16_t EP0OS;\r
+    stc_usb_ep0os_field_t EP0OS_f;\r
+  };\r
+        uint8_t RESERVED18[2];\r
+  union {\r
+    __IO uint16_t EP1S;\r
+    stc_usb_ep1s_field_t EP1S_f;\r
+  };\r
+        uint8_t RESERVED19[2];\r
+  union {\r
+    __IO uint16_t EP2S;\r
+    stc_usb_ep2s_field_t EP2S_f;\r
+  };\r
+        uint8_t RESERVED20[2];\r
+  __IO uint16_t EP3S;\r
+        uint8_t RESERVED21[2];\r
+  union {\r
+    __IO uint16_t EP4S;\r
+    stc_usb_ep4s_field_t EP4S_f;\r
+  };\r
+        uint8_t RESERVED22[2];\r
+  union {\r
+    __IO uint16_t EP5S;\r
+    stc_usb_ep5s_field_t EP5S_f;\r
+  };\r
+        uint8_t RESERVED23[2];\r
+  union {\r
+    __IO uint16_t EP0DT;\r
+    struct {\r
+      __IO  uint8_t EP0DTL;\r
+      __IO  uint8_t EP0DTH;\r
+    };\r
+  };\r
+        uint8_t RESERVED24[2];\r
+  union {\r
+    __IO uint16_t EP1DT;\r
+    struct {\r
+      __IO  uint8_t EP1DTL;\r
+      __IO  uint8_t EP1DTH;\r
+    };\r
+  };\r
+        uint8_t RESERVED25[2];\r
+  union {\r
+    __IO uint16_t EP2DT;\r
+    struct {\r
+      __IO  uint8_t EP2DTL;\r
+      __IO  uint8_t EP2DTH;\r
+    };\r
+  };\r
+        uint8_t RESERVED26[2];\r
+  union {\r
+    __IO uint16_t EP3DT;\r
+    struct {\r
+      __IO  uint8_t EP3DTL;\r
+      __IO  uint8_t EP3DTH;\r
+    };\r
+  };\r
+        uint8_t RESERVED27[2];\r
+  union {\r
+    __IO uint16_t EP4DT;\r
+    struct {\r
+      __IO  uint8_t EP4DTL;\r
+      __IO  uint8_t EP4DTH;\r
+    };\r
+  };\r
+        uint8_t RESERVED28[2];\r
+  union {\r
+    __IO uint16_t EP5DT;\r
+    struct {\r
+      __IO  uint8_t EP5DTL;\r
+      __IO  uint8_t EP5DTH;\r
+    };\r
+  };\r
+}FM3_USB_TypeDef;\r
+\r
+/******************************************************************************\r
+ * DMAC_MODULE\r
+ ******************************************************************************/\r
+/* DMA controller */\r
+typedef struct\r
+{\r
+  union {\r
+    __IO uint32_t DMACR;\r
+    stc_dmac_dmacr_field_t DMACR_f;\r
+  };\r
+        uint8_t RESERVED0[12];\r
+  union {\r
+    __IO uint32_t DMACA0;\r
+    stc_dmac_dmaca0_field_t DMACA0_f;\r
+  };\r
+  union {\r
+    __IO uint32_t DMACB0;\r
+    stc_dmac_dmacb0_field_t DMACB0_f;\r
+  };\r
+  __IO uint32_t DMACSA0;\r
+  __IO uint32_t DMACDA0;\r
+  union {\r
+    __IO uint32_t DMACA1;\r
+    stc_dmac_dmaca1_field_t DMACA1_f;\r
+  };\r
+  union {\r
+    __IO uint32_t DMACB1;\r
+    stc_dmac_dmacb1_field_t DMACB1_f;\r
+  };\r
+  __IO uint32_t DMACSA1;\r
+  __IO uint32_t DMACDA1;\r
+  union {\r
+    __IO uint32_t DMACA2;\r
+    stc_dmac_dmaca2_field_t DMACA2_f;\r
+  };\r
+  union {\r
+    __IO uint32_t DMACB2;\r
+    stc_dmac_dmacb2_field_t DMACB2_f;\r
+  };\r
+  __IO uint32_t DMACSA2;\r
+  __IO uint32_t DMACDA2;\r
+  union {\r
+    __IO uint32_t DMACA3;\r
+    stc_dmac_dmaca3_field_t DMACA3_f;\r
+  };\r
+  union {\r
+    __IO uint32_t DMACB3;\r
+    stc_dmac_dmacb3_field_t DMACB3_f;\r
+  };\r
+  __IO uint32_t DMACSA3;\r
+  __IO uint32_t DMACDA3;\r
+  union {\r
+    __IO uint32_t DMACA4;\r
+    stc_dmac_dmaca4_field_t DMACA4_f;\r
+  };\r
+  union {\r
+    __IO uint32_t DMACB4;\r
+    stc_dmac_dmacb4_field_t DMACB4_f;\r
+  };\r
+  __IO uint32_t DMACSA4;\r
+  __IO uint32_t DMACDA4;\r
+  union {\r
+    __IO uint32_t DMACA5;\r
+    stc_dmac_dmaca5_field_t DMACA5_f;\r
+  };\r
+  union {\r
+    __IO uint32_t DMACB5;\r
+    stc_dmac_dmacb5_field_t DMACB5_f;\r
+  };\r
+  __IO uint32_t DMACSA5;\r
+  __IO uint32_t DMACDA5;\r
+  union {\r
+    __IO uint32_t DMACA6;\r
+    stc_dmac_dmaca6_field_t DMACA6_f;\r
+  };\r
+  union {\r
+    __IO uint32_t DMACB6;\r
+    stc_dmac_dmacb6_field_t DMACB6_f;\r
+  };\r
+  __IO uint32_t DMACSA6;\r
+  __IO uint32_t DMACDA6;\r
+  union {\r
+    __IO uint32_t DMACA7;\r
+    stc_dmac_dmaca7_field_t DMACA7_f;\r
+  };\r
+  union {\r
+    __IO uint32_t DMACB7;\r
+    stc_dmac_dmacb7_field_t DMACB7_f;\r
+  };\r
+  __IO uint32_t DMACSA7;\r
+  __IO uint32_t DMACDA7;\r
+}FM3_DMAC_TypeDef;\r
+\r
+\r
+/******************************************************************************\r
+ * Peripheral memory map\r
+ ******************************************************************************/\r
+#define FM3_FLASH_BASE        (0x00000000UL)                 /* Flash Base                             */\r
+#define FM3_PERIPH_BASE       (0x40000000UL)                 /* Peripheral  Base                       */\r
+#define FM3_CM3_BASE          (0xE0100000UL)                 /* CM3 Private                            */\r
+\r
+#define FM3_FLASH_IF_BASE     (FM3_PERIPH_BASE + 0x00000UL)  /* Flash interface registers              */\r
+#define FM3_CRG_BASE          (FM3_PERIPH_BASE + 0x10000UL)  /* Clock and reset registers              */\r
+#define FM3_HWWDT_BASE        (FM3_PERIPH_BASE + 0x11000UL)  /* Hardware watchdog registers            */\r
+#define FM3_SWWDT_BASE        (FM3_PERIPH_BASE + 0x12000UL)  /* Software watchdog registers            */\r
+#define FM3_DTIM_BASE         (FM3_PERIPH_BASE + 0x15000UL)  /* Dual timer 1/2 registers               */\r
+#define FM3_MFT0_FRT_BASE     (FM3_PERIPH_BASE + 0x20000UL)  /* Multifunction Timer unit 0 Free Running Timer registers */\r
+#define FM3_MFT0_OCU_BASE     (FM3_PERIPH_BASE + 0x20000UL)  /* Multifunction Timer unit 0 Output Compare Unit registers */\r
+#define FM3_MFT0_WFG_BASE     (FM3_PERIPH_BASE + 0x20000UL)  /* Multifunction Timer unit 0 Waveform Generator and Noise Canceler registers */\r
+#define FM3_MFT0_ICU_BASE     (FM3_PERIPH_BASE + 0x20000UL)  /* Multifunction Timer unit 0 Input Capture Unit registers */\r
+#define FM3_MFT0_ADCMP_BASE   (FM3_PERIPH_BASE + 0x20000UL)  /* Multifunction Timer unit 0 ADC Start Compare Unit registers */\r
+#define FM3_MFT1_FRT_BASE     (FM3_PERIPH_BASE + 0x21000UL)  /* Multifunction Timer unit 1 Free Running Timer registers */\r
+#define FM3_MFT1_OCU_BASE     (FM3_PERIPH_BASE + 0x21000UL)  /* Multifunction Timer unit 1 Output Compare Unit registers */\r
+#define FM3_MFT1_WFG_BASE     (FM3_PERIPH_BASE + 0x21000UL)  /* Multifunction Timer unit 1 Waveform Generator and Noise Canceler registers */\r
+#define FM3_MFT1_ICU_BASE     (FM3_PERIPH_BASE + 0x21000UL)  /* Multifunction Timer unit 1 Input Capture Unit registers */\r
+#define FM3_MFT1_ADCMP_BASE   (FM3_PERIPH_BASE + 0x21000UL)  /* Multifunction Timer unit 1 ADC Start Compare Unit registers */\r
+#define FM3_MFT_PPG_BASE      (FM3_PERIPH_BASE + 0x24000UL)  /* Multifunction Timer PPG registers      */\r
+#define FM3_BT0_PPG_BASE      (FM3_PERIPH_BASE + 0x25000UL)  /* Base Timer 0 PPG registers             */\r
+#define FM3_BT0_PWM_BASE      (FM3_PERIPH_BASE + 0x25000UL)  /* Base Timer 0 PWM registers             */\r
+#define FM3_BT0_RT_BASE       (FM3_PERIPH_BASE + 0x25000UL)  /* Base Timer 0 RT registers              */\r
+#define FM3_BT0_PWC_BASE      (FM3_PERIPH_BASE + 0x25000UL)  /* Base Timer 0 PWC registers             */\r
+#define FM3_BT1_PPG_BASE      (FM3_PERIPH_BASE + 0x25040UL)  /* Base Timer 1 PPG registers             */\r
+#define FM3_BT1_PWM_BASE      (FM3_PERIPH_BASE + 0x25040UL)  /* Base Timer 1 PWM registers             */\r
+#define FM3_BT1_RT_BASE       (FM3_PERIPH_BASE + 0x25040UL)  /* Base Timer 1 RT registers              */\r
+#define FM3_BT1_PWC_BASE      (FM3_PERIPH_BASE + 0x25040UL)  /* Base Timer 1 PWC registers             */\r
+#define FM3_BT2_PPG_BASE      (FM3_PERIPH_BASE + 0x25080UL)  /* Base Timer 2 PPG registers             */\r
+#define FM3_BT2_PWM_BASE      (FM3_PERIPH_BASE + 0x25080UL)  /* Base Timer 2 PWM registers             */\r
+#define FM3_BT2_RT_BASE       (FM3_PERIPH_BASE + 0x25080UL)  /* Base Timer 2 RT registers              */\r
+#define FM3_BT2_PWC_BASE      (FM3_PERIPH_BASE + 0x25080UL)  /* Base Timer 2 PWC registers             */\r
+#define FM3_BT3_PPG_BASE      (FM3_PERIPH_BASE + 0x250C0UL)  /* Base Timer 3 PPG registers             */\r
+#define FM3_BT3_PWM_BASE      (FM3_PERIPH_BASE + 0x250C0UL)  /* Base Timer 3 PWM registers             */\r
+#define FM3_BT3_RT_BASE       (FM3_PERIPH_BASE + 0x250C0UL)  /* Base Timer 3 RT registers              */\r
+#define FM3_BT3_PWC_BASE      (FM3_PERIPH_BASE + 0x250C0UL)  /* Base Timer 3 PWC registers             */\r
+#define FM3_BT4_PPG_BASE      (FM3_PERIPH_BASE + 0x25200UL)  /* Base Timer 4 PPG registers             */\r
+#define FM3_BT4_PWM_BASE      (FM3_PERIPH_BASE + 0x25200UL)  /* Base Timer 4 PWM registers             */\r
+#define FM3_BT4_RT_BASE       (FM3_PERIPH_BASE + 0x25200UL)  /* Base Timer 4 RT registers              */\r
+#define FM3_BT4_PWC_BASE      (FM3_PERIPH_BASE + 0x25200UL)  /* Base Timer 4 PWC registers             */\r
+#define FM3_BT5_PPG_BASE      (FM3_PERIPH_BASE + 0x25240UL)  /* Base Timer 5 PPG registers             */\r
+#define FM3_BT5_PWM_BASE      (FM3_PERIPH_BASE + 0x25240UL)  /* Base Timer 5 PWM registers             */\r
+#define FM3_BT5_RT_BASE       (FM3_PERIPH_BASE + 0x25240UL)  /* Base Timer 5 RT registers              */\r
+#define FM3_BT5_PWC_BASE      (FM3_PERIPH_BASE + 0x25240UL)  /* Base Timer 5 PWC registers             */\r
+#define FM3_BT6_PPG_BASE      (FM3_PERIPH_BASE + 0x25280UL)  /* Base Timer 6 PPG registers             */\r
+#define FM3_BT6_PWM_BASE      (FM3_PERIPH_BASE + 0x25280UL)  /* Base Timer 6 PWM registers             */\r
+#define FM3_BT6_RT_BASE       (FM3_PERIPH_BASE + 0x25280UL)  /* Base Timer 6 RT registers              */\r
+#define FM3_BT6_PWC_BASE      (FM3_PERIPH_BASE + 0x25280UL)  /* Base Timer 6 PWC registers             */\r
+#define FM3_BT7_PPG_BASE      (FM3_PERIPH_BASE + 0x252C0UL)  /* Base Timer 7 PPG registers             */\r
+#define FM3_BT7_PWM_BASE      (FM3_PERIPH_BASE + 0x252C0UL)  /* Base Timer 7 PWM registers             */\r
+#define FM3_BT7_RT_BASE       (FM3_PERIPH_BASE + 0x252C0UL)  /* Base Timer 7 RT registers              */\r
+#define FM3_BT7_PWC_BASE      (FM3_PERIPH_BASE + 0x252C0UL)  /* Base Timer 7 PWC registers             */\r
+#define FM3_BTIOSEL03_BASE    (FM3_PERIPH_BASE + 0x25100UL)  /* Base Timer I/O selector channel 0 - channel 3 registers */\r
+#define FM3_BTIOSEL47_BASE    (FM3_PERIPH_BASE + 0x25300UL)  /* Base Timer I/O selector channel 4 - channel 7 registers */\r
+#define FM3_SBSSR_BASE        (FM3_PERIPH_BASE + 0x25FFCUL)  /* Software based Simulation Startup (Base Timer) register */\r
+#define FM3_QPRC0_BASE        (FM3_PERIPH_BASE + 0x26000UL)  /* Quad position and revolution counter channel 0 registers */\r
+#define FM3_QPRC1_BASE        (FM3_PERIPH_BASE + 0x26040UL)  /* Quad position and revolution counter channel 1 registers */\r
+#define FM3_ADC0_BASE         (FM3_PERIPH_BASE + 0x27000UL)  /* 12-bit ADC unit 0 registers            */\r
+#define FM3_ADC1_BASE         (FM3_PERIPH_BASE + 0x27100UL)  /* 12-bit ADC unit 1 registers            */\r
+#define FM3_CRTRIM_BASE       (FM3_PERIPH_BASE + 0x2E000UL)  /* CR trimming registers                  */\r
+#define FM3_EXTI_BASE         (FM3_PERIPH_BASE + 0x30000UL)  /* External interrupt registers           */\r
+#define FM3_INTREQ_BASE       (FM3_PERIPH_BASE + 0x31000UL)  /* Interrupt request read registers       */\r
+#define FM3_GPIO_BASE         (FM3_PERIPH_BASE + 0x33000UL)  /* General purpose I/O registers          */\r
+#define FM3_LVD_BASE          (FM3_PERIPH_BASE + 0x35000UL)  /* Low voltage detection registers        */\r
+#define FM3_USBCLK_BASE       (FM3_PERIPH_BASE + 0x36000UL)  /* USB clock registers                    */\r
+#define FM3_MFS0_UART_BASE    (FM3_PERIPH_BASE + 0x38000UL)  /* UART asynchronous channel 0 registers  */\r
+#define FM3_MFS0_CSIO_BASE    (FM3_PERIPH_BASE + 0x38000UL)  /* UART synchronous channel 0 registers   */\r
+#define FM3_MFS0_LIN_BASE     (FM3_PERIPH_BASE + 0x38000UL)  /* UART LIN channel 0 registers           */\r
+#define FM3_MFS0_I2C_BASE     (FM3_PERIPH_BASE + 0x38000UL)  /* I2C channel 0 registers                */\r
+#define FM3_MFS1_UART_BASE    (FM3_PERIPH_BASE + 0x38100UL)  /* UART asynchronous channel 1 registers  */\r
+#define FM3_MFS1_CSIO_BASE    (FM3_PERIPH_BASE + 0x38100UL)  /* UART synchronous channel 1 registers   */\r
+#define FM3_MFS1_LIN_BASE     (FM3_PERIPH_BASE + 0x38100UL)  /* UART LIN channel 1 registers           */\r
+#define FM3_MFS1_I2C_BASE     (FM3_PERIPH_BASE + 0x38100UL)  /* I2C channel 1 registers                */\r
+#define FM3_MFS2_UART_BASE    (FM3_PERIPH_BASE + 0x38200UL)  /* UART asynchronous channel 2 registers  */\r
+#define FM3_MFS2_CSIO_BASE    (FM3_PERIPH_BASE + 0x38200UL)  /* UART synchronous channel 2 registers   */\r
+#define FM3_MFS2_LIN_BASE     (FM3_PERIPH_BASE + 0x38200UL)  /* UART LIN channel 2 registers           */\r
+#define FM3_MFS2_I2C_BASE     (FM3_PERIPH_BASE + 0x38200UL)  /* I2C channel 2 registers                */\r
+#define FM3_MFS3_UART_BASE    (FM3_PERIPH_BASE + 0x38300UL)  /* UART asynchronous channel 3 registers  */\r
+#define FM3_MFS3_CSIO_BASE    (FM3_PERIPH_BASE + 0x38300UL)  /* UART synchronous channel 3 registers   */\r
+#define FM3_MFS3_LIN_BASE     (FM3_PERIPH_BASE + 0x38300UL)  /* UART LIN channel 3 registers           */\r
+#define FM3_MFS3_I2C_BASE     (FM3_PERIPH_BASE + 0x38300UL)  /* I2C channel 3 registers                */\r
+#define FM3_MFS4_UART_BASE    (FM3_PERIPH_BASE + 0x38400UL)  /* UART asynchronous channel 4 registers  */\r
+#define FM3_MFS4_CSIO_BASE    (FM3_PERIPH_BASE + 0x38400UL)  /* UART synchronous channel 4 registers   */\r
+#define FM3_MFS4_LIN_BASE     (FM3_PERIPH_BASE + 0x38400UL)  /* UART LIN channel 4 registers           */\r
+#define FM3_MFS4_I2C_BASE     (FM3_PERIPH_BASE + 0x38400UL)  /* I2C channel 4 registers                */\r
+#define FM3_MFS5_UART_BASE    (FM3_PERIPH_BASE + 0x38500UL)  /* UART asynchronous channel 5 registers  */\r
+#define FM3_MFS5_CSIO_BASE    (FM3_PERIPH_BASE + 0x38500UL)  /* UART synchronous channel 5 registers   */\r
+#define FM3_MFS5_LIN_BASE     (FM3_PERIPH_BASE + 0x38500UL)  /* UART LIN channel 5 registers           */\r
+#define FM3_MFS5_I2C_BASE     (FM3_PERIPH_BASE + 0x38500UL)  /* I2C channel 5 registers                */\r
+#define FM3_MFS6_UART_BASE    (FM3_PERIPH_BASE + 0x38600UL)  /* UART asynchronous channel 6 registers  */\r
+#define FM3_MFS6_CSIO_BASE    (FM3_PERIPH_BASE + 0x38600UL)  /* UART synchronous channel 6 registers   */\r
+#define FM3_MFS6_LIN_BASE     (FM3_PERIPH_BASE + 0x38600UL)  /* UART LIN channel 6 registers           */\r
+#define FM3_MFS6_I2C_BASE     (FM3_PERIPH_BASE + 0x38600UL)  /* I2C channel 6 registers                */\r
+#define FM3_MFS7_UART_BASE    (FM3_PERIPH_BASE + 0x38700UL)  /* UART asynchronous channel 7 registers  */\r
+#define FM3_MFS7_CSIO_BASE    (FM3_PERIPH_BASE + 0x38700UL)  /* UART synchronous channel 7 registers   */\r
+#define FM3_MFS7_LIN_BASE     (FM3_PERIPH_BASE + 0x38700UL)  /* UART LIN channel 7 registers           */\r
+#define FM3_MFS7_I2C_BASE     (FM3_PERIPH_BASE + 0x38700UL)  /* I2C channel 7 registers                */\r
+#define FM3_CRC_BASE          (FM3_PERIPH_BASE + 0x39000UL)  /* CRC registers                          */\r
+#define FM3_WC_BASE           (FM3_PERIPH_BASE + 0x3A000UL)  /* Watch counter registers                */\r
+#define FM3_USB0_BASE         (FM3_PERIPH_BASE + 0x42100UL)  /* USB channel 0 registers                */\r
+#define FM3_DMAC_BASE         (FM3_PERIPH_BASE + 0x60000UL)  /* DMA controller                         */\r
+\r
+/******************************************************************************\r
+ * Peripheral declaration\r
+ ******************************************************************************/\r
+#define FM3_FLASH_IF    ((FM3_FLASH_IF_TypeDef *)FM3_FLASH_IF_BASE)\r
+#define FM3_CRG         ((FM3_CRG_TypeDef *)FM3_CRG_BASE)\r
+#define FM3_HWWDT       ((FM3_HWWDT_TypeDef *)FM3_HWWDT_BASE)\r
+#define FM3_SWWDT       ((FM3_SWWDT_TypeDef *)FM3_SWWDT_BASE)\r
+#define FM3_DTIM        ((FM3_DTIM_TypeDef *)FM3_DTIM_BASE)\r
+#define FM3_MFT0_FRT    ((FM3_MFT_FRT_TypeDef *)FM3_MFT0_FRT_BASE)\r
+#define FM3_MFT0_OCU    ((FM3_MFT_OCU_TypeDef *)FM3_MFT0_OCU_BASE)\r
+#define FM3_MFT0_WFG    ((FM3_MFT_WFG_TypeDef *)FM3_MFT0_WFG_BASE)\r
+#define FM3_MFT0_ICU    ((FM3_MFT_ICU_TypeDef *)FM3_MFT0_ICU_BASE)\r
+#define FM3_MFT0_ADCMP  ((FM3_MFT_ADCMP_TypeDef *)FM3_MFT0_ADCMP_BASE)\r
+#define FM3_MFT1_FRT    ((FM3_MFT_FRT_TypeDef *)FM3_MFT1_FRT_BASE)\r
+#define FM3_MFT1_OCU    ((FM3_MFT_OCU_TypeDef *)FM3_MFT1_OCU_BASE)\r
+#define FM3_MFT1_WFG    ((FM3_MFT_WFG_TypeDef *)FM3_MFT1_WFG_BASE)\r
+#define FM3_MFT1_ICU    ((FM3_MFT_ICU_TypeDef *)FM3_MFT1_ICU_BASE)\r
+#define FM3_MFT1_ADCMP  ((FM3_MFT_ADCMP_TypeDef *)FM3_MFT1_ADCMP_BASE)\r
+#define FM3_MFT_PPG     ((FM3_MFT_PPG_TypeDef *)FM3_MFT_PPG_BASE)\r
+#define FM3_BT0_PPG     ((FM3_BT_PPG_TypeDef *)FM3_BT0_PPG_BASE)\r
+#define FM3_BT0_PWM     ((FM3_BT_PWM_TypeDef *)FM3_BT0_PWM_BASE)\r
+#define FM3_BT0_RT      ((FM3_BT_RT_TypeDef *)FM3_BT0_RT_BASE)\r
+#define FM3_BT0_PWC     ((FM3_BT_PWC_TypeDef *)FM3_BT0_PWC_BASE)\r
+#define FM3_BT1_PPG     ((FM3_BT_PPG_TypeDef *)FM3_BT1_PPG_BASE)\r
+#define FM3_BT1_PWM     ((FM3_BT_PWM_TypeDef *)FM3_BT1_PWM_BASE)\r
+#define FM3_BT1_RT      ((FM3_BT_RT_TypeDef *)FM3_BT1_RT_BASE)\r
+#define FM3_BT1_PWC     ((FM3_BT_PWC_TypeDef *)FM3_BT1_PWC_BASE)\r
+#define FM3_BT2_PPG     ((FM3_BT_PPG_TypeDef *)FM3_BT2_PPG_BASE)\r
+#define FM3_BT2_PWM     ((FM3_BT_PWM_TypeDef *)FM3_BT2_PWM_BASE)\r
+#define FM3_BT2_RT      ((FM3_BT_RT_TypeDef *)FM3_BT2_RT_BASE)\r
+#define FM3_BT2_PWC     ((FM3_BT_PWC_TypeDef *)FM3_BT2_PWC_BASE)\r
+#define FM3_BT3_PPG     ((FM3_BT_PPG_TypeDef *)FM3_BT3_PPG_BASE)\r
+#define FM3_BT3_PWM     ((FM3_BT_PWM_TypeDef *)FM3_BT3_PWM_BASE)\r
+#define FM3_BT3_RT      ((FM3_BT_RT_TypeDef *)FM3_BT3_RT_BASE)\r
+#define FM3_BT3_PWC     ((FM3_BT_PWC_TypeDef *)FM3_BT3_PWC_BASE)\r
+#define FM3_BT4_PPG     ((FM3_BT_PPG_TypeDef *)FM3_BT4_PPG_BASE)\r
+#define FM3_BT4_PWM     ((FM3_BT_PWM_TypeDef *)FM3_BT4_PWM_BASE)\r
+#define FM3_BT4_RT      ((FM3_BT_RT_TypeDef *)FM3_BT4_RT_BASE)\r
+#define FM3_BT4_PWC     ((FM3_BT_PWC_TypeDef *)FM3_BT4_PWC_BASE)\r
+#define FM3_BT5_PPG     ((FM3_BT_PPG_TypeDef *)FM3_BT5_PPG_BASE)\r
+#define FM3_BT5_PWM     ((FM3_BT_PWM_TypeDef *)FM3_BT5_PWM_BASE)\r
+#define FM3_BT5_RT      ((FM3_BT_RT_TypeDef *)FM3_BT5_RT_BASE)\r
+#define FM3_BT5_PWC     ((FM3_BT_PWC_TypeDef *)FM3_BT5_PWC_BASE)\r
+#define FM3_BT6_PPG     ((FM3_BT_PPG_TypeDef *)FM3_BT6_PPG_BASE)\r
+#define FM3_BT6_PWM     ((FM3_BT_PWM_TypeDef *)FM3_BT6_PWM_BASE)\r
+#define FM3_BT6_RT      ((FM3_BT_RT_TypeDef *)FM3_BT6_RT_BASE)\r
+#define FM3_BT6_PWC     ((FM3_BT_PWC_TypeDef *)FM3_BT6_PWC_BASE)\r
+#define FM3_BT7_PPG     ((FM3_BT_PPG_TypeDef *)FM3_BT7_PPG_BASE)\r
+#define FM3_BT7_PWM     ((FM3_BT_PWM_TypeDef *)FM3_BT7_PWM_BASE)\r
+#define FM3_BT7_RT      ((FM3_BT_RT_TypeDef *)FM3_BT7_RT_BASE)\r
+#define FM3_BT7_PWC     ((FM3_BT_PWC_TypeDef *)FM3_BT7_PWC_BASE)\r
+#define FM3_BTIOSEL03   ((FM3_BTIOSEL03_TypeDef *)FM3_BTIOSEL03_BASE)\r
+#define FM3_BTIOSEL47   ((FM3_BTIOSEL47_TypeDef *)FM3_BTIOSEL47_BASE)\r
+#define FM3_SBSSR       ((FM3_SBSSR_TypeDef *)FM3_SBSSR_BASE)\r
+#define FM3_QPRC0       ((FM3_QPRC_TypeDef *)FM3_QPRC0_BASE)\r
+#define FM3_QPRC1       ((FM3_QPRC_TypeDef *)FM3_QPRC1_BASE)\r
+#define FM3_ADC0        ((FM3_ADC_TypeDef *)FM3_ADC0_BASE)\r
+#define FM3_ADC1        ((FM3_ADC_TypeDef *)FM3_ADC1_BASE)\r
+#define FM3_CRTRIM      ((FM3_CRTRIM_TypeDef *)FM3_CRTRIM_BASE)\r
+#define FM3_EXTI        ((FM3_EXTI_TypeDef *)FM3_EXTI_BASE)\r
+#define FM3_INTREQ      ((FM3_INTREQ_TypeDef *)FM3_INTREQ_BASE)\r
+#define FM3_GPIO        ((FM3_GPIO_TypeDef *)FM3_GPIO_BASE)\r
+#define FM3_LVD         ((FM3_LVD_TypeDef *)FM3_LVD_BASE)\r
+#define FM3_USBCLK      ((FM3_USBCLK_TypeDef *)FM3_USBCLK_BASE)\r
+#define FM3_MFS0_UART   ((FM3_MFS03_UART_TypeDef *)FM3_MFS0_UART_BASE)\r
+#define FM3_MFS0_CSIO   ((FM3_MFS03_CSIO_TypeDef *)FM3_MFS0_CSIO_BASE)\r
+#define FM3_MFS0_LIN    ((FM3_MFS03_LIN_TypeDef *)FM3_MFS0_LIN_BASE)\r
+#define FM3_MFS0_I2C    ((FM3_MFS03_I2C_TypeDef *)FM3_MFS0_I2C_BASE)\r
+#define FM3_MFS1_UART   ((FM3_MFS03_UART_TypeDef *)FM3_MFS1_UART_BASE)\r
+#define FM3_MFS1_CSIO   ((FM3_MFS03_CSIO_TypeDef *)FM3_MFS1_CSIO_BASE)\r
+#define FM3_MFS1_LIN    ((FM3_MFS03_LIN_TypeDef *)FM3_MFS1_LIN_BASE)\r
+#define FM3_MFS1_I2C    ((FM3_MFS03_I2C_TypeDef *)FM3_MFS1_I2C_BASE)\r
+#define FM3_MFS2_UART   ((FM3_MFS03_UART_TypeDef *)FM3_MFS2_UART_BASE)\r
+#define FM3_MFS2_CSIO   ((FM3_MFS03_CSIO_TypeDef *)FM3_MFS2_CSIO_BASE)\r
+#define FM3_MFS2_LIN    ((FM3_MFS03_LIN_TypeDef *)FM3_MFS2_LIN_BASE)\r
+#define FM3_MFS2_I2C    ((FM3_MFS03_I2C_TypeDef *)FM3_MFS2_I2C_BASE)\r
+#define FM3_MFS3_UART   ((FM3_MFS03_UART_TypeDef *)FM3_MFS3_UART_BASE)\r
+#define FM3_MFS3_CSIO   ((FM3_MFS03_CSIO_TypeDef *)FM3_MFS3_CSIO_BASE)\r
+#define FM3_MFS3_LIN    ((FM3_MFS03_LIN_TypeDef *)FM3_MFS3_LIN_BASE)\r
+#define FM3_MFS3_I2C    ((FM3_MFS03_I2C_TypeDef *)FM3_MFS3_I2C_BASE)\r
+#define FM3_MFS4_UART   ((FM3_MFS47_UART_TypeDef *)FM3_MFS4_UART_BASE)\r
+#define FM3_MFS4_CSIO   ((FM3_MFS47_CSIO_TypeDef *)FM3_MFS4_CSIO_BASE)\r
+#define FM3_MFS4_LIN    ((FM3_MFS47_LIN_TypeDef *)FM3_MFS4_LIN_BASE)\r
+#define FM3_MFS4_I2C    ((FM3_MFS47_I2C_TypeDef *)FM3_MFS4_I2C_BASE)\r
+#define FM3_MFS5_UART   ((FM3_MFS47_UART_TypeDef *)FM3_MFS5_UART_BASE)\r
+#define FM3_MFS5_CSIO   ((FM3_MFS47_CSIO_TypeDef *)FM3_MFS5_CSIO_BASE)\r
+#define FM3_MFS5_LIN    ((FM3_MFS47_LIN_TypeDef *)FM3_MFS5_LIN_BASE)\r
+#define FM3_MFS5_I2C    ((FM3_MFS47_I2C_TypeDef *)FM3_MFS5_I2C_BASE)\r
+#define FM3_MFS6_UART   ((FM3_MFS47_UART_TypeDef *)FM3_MFS6_UART_BASE)\r
+#define FM3_MFS6_CSIO   ((FM3_MFS47_CSIO_TypeDef *)FM3_MFS6_CSIO_BASE)\r
+#define FM3_MFS6_LIN    ((FM3_MFS47_LIN_TypeDef *)FM3_MFS6_LIN_BASE)\r
+#define FM3_MFS6_I2C    ((FM3_MFS47_I2C_TypeDef *)FM3_MFS6_I2C_BASE)\r
+#define FM3_MFS7_UART   ((FM3_MFS47_UART_TypeDef *)FM3_MFS7_UART_BASE)\r
+#define FM3_MFS7_CSIO   ((FM3_MFS47_CSIO_TypeDef *)FM3_MFS7_CSIO_BASE)\r
+#define FM3_MFS7_LIN    ((FM3_MFS47_LIN_TypeDef *)FM3_MFS7_LIN_BASE)\r
+#define FM3_MFS7_I2C    ((FM3_MFS47_I2C_TypeDef *)FM3_MFS7_I2C_BASE)\r
+#define FM3_CRC         ((FM3_CRC_TypeDef *)FM3_CRC_BASE)\r
+#define FM3_WC          ((FM3_WC_TypeDef *)FM3_WC_BASE)\r
+#define FM3_USB0        ((FM3_USB_TypeDef *)FM3_USB0_BASE)\r
+#define FM3_DMAC        ((FM3_DMAC_TypeDef *)FM3_DMAC_BASE)\r
+\r
+/******************************************************************************\r
+ * Peripheral Bit Band Alias declaration\r
+ ******************************************************************************/\r
+\r
+/* Flash interface registers */\r
+#define bFM3_FLASH_IF_FASZR_ASZ0               *((volatile unsigned int*)(0x42000000UL))\r
+#define bFM3_FLASH_IF_FASZR_ASZ1               *((volatile unsigned int*)(0x42000004UL))\r
+#define bFM3_FLASH_IF_FRWTR_RWT0               *((volatile unsigned int*)(0x42000080UL))\r
+#define bFM3_FLASH_IF_FRWTR_RWT1               *((volatile unsigned int*)(0x42000084UL))\r
+#define bFM3_FLASH_IF_FSTR_RDY                 *((volatile unsigned int*)(0x42000100UL))\r
+#define bFM3_FLASH_IF_FSTR_HNG                 *((volatile unsigned int*)(0x42000104UL))\r
+#define bFM3_FLASH_IF_FSTR_EER                 *((volatile unsigned int*)(0x42000108UL))\r
+#define bFM3_FLASH_IF_FSYNDN_SD0               *((volatile unsigned int*)(0x42000200UL))\r
+#define bFM3_FLASH_IF_FSYNDN_SD1               *((volatile unsigned int*)(0x42000204UL))\r
+#define bFM3_FLASH_IF_FSYNDN_SD2               *((volatile unsigned int*)(0x42000208UL))\r
+#define bFM3_FLASH_IF_CRTRMM_TRMM0             *((volatile unsigned int*)(0x42002000UL))\r
+#define bFM3_FLASH_IF_CRTRMM_TRMM1             *((volatile unsigned int*)(0x42002004UL))\r
+#define bFM3_FLASH_IF_CRTRMM_TRMM2             *((volatile unsigned int*)(0x42002008UL))\r
+#define bFM3_FLASH_IF_CRTRMM_TRMM3             *((volatile unsigned int*)(0x4200200CUL))\r
+#define bFM3_FLASH_IF_CRTRMM_TRMM4             *((volatile unsigned int*)(0x42002010UL))\r
+#define bFM3_FLASH_IF_CRTRMM_TRMM5             *((volatile unsigned int*)(0x42002014UL))\r
+#define bFM3_FLASH_IF_CRTRMM_TRMM6             *((volatile unsigned int*)(0x42002018UL))\r
+#define bFM3_FLASH_IF_CRTRMM_TRMM7             *((volatile unsigned int*)(0x4200201CUL))\r
+#define bFM3_FLASH_IF_CRTRMM_TRMM8             *((volatile unsigned int*)(0x42002020UL))\r
+#define bFM3_FLASH_IF_CRTRMM_TRMM9             *((volatile unsigned int*)(0x42002024UL))\r
+\r
+/* Clock and reset registers */\r
+#define bFM3_CRG_SCM_CTL_MOSCE                 *((volatile unsigned int*)(0x42200004UL))\r
+#define bFM3_CRG_SCM_CTL_SOSCE                 *((volatile unsigned int*)(0x4220000CUL))\r
+#define bFM3_CRG_SCM_CTL_PLLE                  *((volatile unsigned int*)(0x42200010UL))\r
+#define bFM3_CRG_SCM_CTL_RCS0                  *((volatile unsigned int*)(0x42200014UL))\r
+#define bFM3_CRG_SCM_CTL_RCS1                  *((volatile unsigned int*)(0x42200018UL))\r
+#define bFM3_CRG_SCM_CTL_RCS2                  *((volatile unsigned int*)(0x4220001CUL))\r
+#define bFM3_CRG_SCM_STR_MORDY                 *((volatile unsigned int*)(0x42200084UL))\r
+#define bFM3_CRG_SCM_STR_SORDY                 *((volatile unsigned int*)(0x4220008CUL))\r
+#define bFM3_CRG_SCM_STR_PLRDY                 *((volatile unsigned int*)(0x42200090UL))\r
+#define bFM3_CRG_SCM_STR_RCM0                  *((volatile unsigned int*)(0x42200094UL))\r
+#define bFM3_CRG_SCM_STR_RCM1                  *((volatile unsigned int*)(0x42200098UL))\r
+#define bFM3_CRG_SCM_STR_RCM2                  *((volatile unsigned int*)(0x4220009CUL))\r
+#define bFM3_CRG_RST_STR_PONR                  *((volatile unsigned int*)(0x42200180UL))\r
+#define bFM3_CRG_RST_STR_INITX                 *((volatile unsigned int*)(0x42200184UL))\r
+#define bFM3_CRG_RST_STR_SWDT                  *((volatile unsigned int*)(0x42200190UL))\r
+#define bFM3_CRG_RST_STR_HWDT                  *((volatile unsigned int*)(0x42200194UL))\r
+#define bFM3_CRG_RST_STR_CSVR                  *((volatile unsigned int*)(0x42200198UL))\r
+#define bFM3_CRG_RST_STR_FCSR                  *((volatile unsigned int*)(0x4220019CUL))\r
+#define bFM3_CRG_RST_STR_SRST                  *((volatile unsigned int*)(0x422001A0UL))\r
+#define bFM3_CRG_BSC_PSR_BSR0                  *((volatile unsigned int*)(0x42200200UL))\r
+#define bFM3_CRG_BSC_PSR_BSR1                  *((volatile unsigned int*)(0x42200204UL))\r
+#define bFM3_CRG_BSC_PSR_BSR2                  *((volatile unsigned int*)(0x42200208UL))\r
+#define bFM3_CRG_APBC0_PSR_APBC00              *((volatile unsigned int*)(0x42200280UL))\r
+#define bFM3_CRG_APBC0_PSR_APBC01              *((volatile unsigned int*)(0x42200284UL))\r
+#define bFM3_CRG_APBC1_PSR_APBC10              *((volatile unsigned int*)(0x42200300UL))\r
+#define bFM3_CRG_APBC1_PSR_APBC11              *((volatile unsigned int*)(0x42200304UL))\r
+#define bFM3_CRG_APBC1_PSR_APBC1RST            *((volatile unsigned int*)(0x42200310UL))\r
+#define bFM3_CRG_APBC1_PSR_APBC1EN             *((volatile unsigned int*)(0x4220031CUL))\r
+#define bFM3_CRG_APBC2_PSR_APBC20              *((volatile unsigned int*)(0x42200380UL))\r
+#define bFM3_CRG_APBC2_PSR_APBC21              *((volatile unsigned int*)(0x42200384UL))\r
+#define bFM3_CRG_APBC2_PSR_APBC2RST            *((volatile unsigned int*)(0x42200390UL))\r
+#define bFM3_CRG_APBC2_PSR_APBC2EN             *((volatile unsigned int*)(0x4220039CUL))\r
+#define bFM3_CRG_SWC_PSR_SWDS0                 *((volatile unsigned int*)(0x42200400UL))\r
+#define bFM3_CRG_SWC_PSR_SWDS1                 *((volatile unsigned int*)(0x42200404UL))\r
+#define bFM3_CRG_SWC_PSR_TESTB                 *((volatile unsigned int*)(0x4220041CUL))\r
+#define bFM3_CRG_TTC_PSR_TTC                   *((volatile unsigned int*)(0x42200500UL))\r
+#define bFM3_CRG_CSW_TMR_MOWT0                 *((volatile unsigned int*)(0x42200600UL))\r
+#define bFM3_CRG_CSW_TMR_MOWT1                 *((volatile unsigned int*)(0x42200604UL))\r
+#define bFM3_CRG_CSW_TMR_MOWT2                 *((volatile unsigned int*)(0x42200608UL))\r
+#define bFM3_CRG_CSW_TMR_MOWT3                 *((volatile unsigned int*)(0x4220060CUL))\r
+#define bFM3_CRG_CSW_TMR_SOWT0                 *((volatile unsigned int*)(0x42200610UL))\r
+#define bFM3_CRG_CSW_TMR_SOWT1                 *((volatile unsigned int*)(0x42200614UL))\r
+#define bFM3_CRG_CSW_TMR_SOWT2                 *((volatile unsigned int*)(0x42200618UL))\r
+#define bFM3_CRG_PSW_TMR_POWT0                 *((volatile unsigned int*)(0x42200680UL))\r
+#define bFM3_CRG_PSW_TMR_POWT1                 *((volatile unsigned int*)(0x42200684UL))\r
+#define bFM3_CRG_PSW_TMR_POWT2                 *((volatile unsigned int*)(0x42200688UL))\r
+#define bFM3_CRG_PSW_TMR_PINC                  *((volatile unsigned int*)(0x42200690UL))\r
+#define bFM3_CRG_PLL_CTL1_PLLM0                *((volatile unsigned int*)(0x42200700UL))\r
+#define bFM3_CRG_PLL_CTL1_PLLM1                *((volatile unsigned int*)(0x42200704UL))\r
+#define bFM3_CRG_PLL_CTL1_PLLM2                *((volatile unsigned int*)(0x42200708UL))\r
+#define bFM3_CRG_PLL_CTL1_PLLM3                *((volatile unsigned int*)(0x4220070CUL))\r
+#define bFM3_CRG_PLL_CTL1_PLLK0                *((volatile unsigned int*)(0x42200710UL))\r
+#define bFM3_CRG_PLL_CTL1_PLLK1                *((volatile unsigned int*)(0x42200714UL))\r
+#define bFM3_CRG_PLL_CTL1_PLLK2                *((volatile unsigned int*)(0x42200718UL))\r
+#define bFM3_CRG_PLL_CTL1_PLLK3                *((volatile unsigned int*)(0x4220071CUL))\r
+#define bFM3_CRG_PLL_CTL2_PLLN0                *((volatile unsigned int*)(0x42200780UL))\r
+#define bFM3_CRG_PLL_CTL2_PLLN1                *((volatile unsigned int*)(0x42200784UL))\r
+#define bFM3_CRG_PLL_CTL2_PLLN2                *((volatile unsigned int*)(0x42200788UL))\r
+#define bFM3_CRG_PLL_CTL2_PLLN3                *((volatile unsigned int*)(0x4220078CUL))\r
+#define bFM3_CRG_PLL_CTL2_PLLN4                *((volatile unsigned int*)(0x42200790UL))\r
+#define bFM3_CRG_PLL_CTL2_PLLN5                *((volatile unsigned int*)(0x42200794UL))\r
+#define bFM3_CRG_CSV_CTL_MCSVE                 *((volatile unsigned int*)(0x42200800UL))\r
+#define bFM3_CRG_CSV_CTL_SCSVE                 *((volatile unsigned int*)(0x42200804UL))\r
+#define bFM3_CRG_CSV_CTL_FCSDE                 *((volatile unsigned int*)(0x42200820UL))\r
+#define bFM3_CRG_CSV_CTL_FCSRE                 *((volatile unsigned int*)(0x42200824UL))\r
+#define bFM3_CRG_CSV_CTL_FCD0                  *((volatile unsigned int*)(0x42200830UL))\r
+#define bFM3_CRG_CSV_CTL_FCD1                  *((volatile unsigned int*)(0x42200834UL))\r
+#define bFM3_CRG_CSV_CTL_FCD2                  *((volatile unsigned int*)(0x42200838UL))\r
+#define bFM3_CRG_CSV_STR_MCMF                  *((volatile unsigned int*)(0x42200880UL))\r
+#define bFM3_CRG_CSV_STR_SCMF                  *((volatile unsigned int*)(0x42200884UL))\r
+#define bFM3_CRG_DBWDT_CTL_DPSWBE              *((volatile unsigned int*)(0x42200A94UL))\r
+#define bFM3_CRG_DBWDT_CTL_DPHWBE              *((volatile unsigned int*)(0x42200A9CUL))\r
+#define bFM3_CRG_INT_ENR_MCSE                  *((volatile unsigned int*)(0x42200C00UL))\r
+#define bFM3_CRG_INT_ENR_SCSE                  *((volatile unsigned int*)(0x42200C04UL))\r
+#define bFM3_CRG_INT_ENR_PCSE                  *((volatile unsigned int*)(0x42200C08UL))\r
+#define bFM3_CRG_INT_ENR_FCSE                  *((volatile unsigned int*)(0x42200C14UL))\r
+#define bFM3_CRG_INT_STR_MCSI                  *((volatile unsigned int*)(0x42200C80UL))\r
+#define bFM3_CRG_INT_STR_SCSI                  *((volatile unsigned int*)(0x42200C84UL))\r
+#define bFM3_CRG_INT_STR_PCSI                  *((volatile unsigned int*)(0x42200C88UL))\r
+#define bFM3_CRG_INT_STR_FCSI                  *((volatile unsigned int*)(0x42200C94UL))\r
+#define bFM3_CRG_INT_CLR_MCSC                  *((volatile unsigned int*)(0x42200D00UL))\r
+#define bFM3_CRG_INT_CLR_SCSC                  *((volatile unsigned int*)(0x42200D04UL))\r
+#define bFM3_CRG_INT_CLR_PCSC                  *((volatile unsigned int*)(0x42200D08UL))\r
+#define bFM3_CRG_INT_CLR_FCSC                  *((volatile unsigned int*)(0x42200D14UL))\r
+\r
+/* Hardware watchdog registers */\r
+#define bFM3_HWWDT_WDG_CTL_INTEN               *((volatile unsigned int*)(0x42220100UL))\r
+#define bFM3_HWWDT_WDG_CTL_RESEN               *((volatile unsigned int*)(0x42220104UL))\r
+#define bFM3_HWWDT_WDG_RIS_RIS                 *((volatile unsigned int*)(0x42220200UL))\r
+\r
+/* Software watchdog registers */\r
+#define bFM3_SWWDT_WDOGCONTROL_INTEN           *((volatile unsigned int*)(0x42240100UL))\r
+#define bFM3_SWWDT_WDOGCONTROL_RESEN           *((volatile unsigned int*)(0x42240104UL))\r
+#define bFM3_SWWDT_WDOGRIS_RIS                 *((volatile unsigned int*)(0x42240200UL))\r
+\r
+/* Dual timer 1/2 registers */\r
+#define bFM3_DTIM_TIMER1CONTROL_ONESHOT        *((volatile unsigned int*)(0x422A0100UL))\r
+#define bFM3_DTIM_TIMER1CONTROL_TIMERSIZE      *((volatile unsigned int*)(0x422A0104UL))\r
+#define bFM3_DTIM_TIMER1CONTROL_TIMERPRE0      *((volatile unsigned int*)(0x422A0108UL))\r
+#define bFM3_DTIM_TIMER1CONTROL_TIMERPRE1      *((volatile unsigned int*)(0x422A010CUL))\r
+#define bFM3_DTIM_TIMER1CONTROL_INTENABLE      *((volatile unsigned int*)(0x422A0114UL))\r
+#define bFM3_DTIM_TIMER1CONTROL_TIMERMODE      *((volatile unsigned int*)(0x422A0118UL))\r
+#define bFM3_DTIM_TIMER1CONTROL_TIMEREN        *((volatile unsigned int*)(0x422A011CUL))\r
+#define bFM3_DTIM_TIMER1RIS_TIMERXRIS          *((volatile unsigned int*)(0x422A0200UL))\r
+#define bFM3_DTIM_TIMER1MIS_TIMERXRIS          *((volatile unsigned int*)(0x422A0280UL))\r
+#define bFM3_DTIM_TIMER2CONTROL_ONESHOT        *((volatile unsigned int*)(0x422A0500UL))\r
+#define bFM3_DTIM_TIMER2CONTROL_TIMERSIZE      *((volatile unsigned int*)(0x422A0504UL))\r
+#define bFM3_DTIM_TIMER2CONTROL_TIMERPRE0      *((volatile unsigned int*)(0x422A0508UL))\r
+#define bFM3_DTIM_TIMER2CONTROL_TIMERPRE1      *((volatile unsigned int*)(0x422A050CUL))\r
+#define bFM3_DTIM_TIMER2CONTROL_INTENABLE      *((volatile unsigned int*)(0x422A0514UL))\r
+#define bFM3_DTIM_TIMER2CONTROL_TIMERMODE      *((volatile unsigned int*)(0x422A0518UL))\r
+#define bFM3_DTIM_TIMER2CONTROL_TIMEREN        *((volatile unsigned int*)(0x422A051CUL))\r
+#define bFM3_DTIM_TIMER2RIS_TIMERXRIS          *((volatile unsigned int*)(0x422A0600UL))\r
+#define bFM3_DTIM_TIMER2MIS_TIMERXRIS          *((volatile unsigned int*)(0x422A0680UL))\r
+\r
+/* Multifunction Timer unit 0 Free Running Timer registers */\r
+#define bFM3_MFT0_FRT_TCSA0_CLK0               *((volatile unsigned int*)(0x42400600UL))\r
+#define bFM3_MFT0_FRT_TCSA0_CLK1               *((volatile unsigned int*)(0x42400604UL))\r
+#define bFM3_MFT0_FRT_TCSA0_CLK2               *((volatile unsigned int*)(0x42400608UL))\r
+#define bFM3_MFT0_FRT_TCSA0_CLK3               *((volatile unsigned int*)(0x4240060CUL))\r
+#define bFM3_MFT0_FRT_TCSA0_SCLR               *((volatile unsigned int*)(0x42400610UL))\r
+#define bFM3_MFT0_FRT_TCSA0_MODE               *((volatile unsigned int*)(0x42400614UL))\r
+#define bFM3_MFT0_FRT_TCSA0_STOP               *((volatile unsigned int*)(0x42400618UL))\r
+#define bFM3_MFT0_FRT_TCSA0_BFE                *((volatile unsigned int*)(0x4240061CUL))\r
+#define bFM3_MFT0_FRT_TCSA0_ICRE               *((volatile unsigned int*)(0x42400620UL))\r
+#define bFM3_MFT0_FRT_TCSA0_ICLR               *((volatile unsigned int*)(0x42400624UL))\r
+#define bFM3_MFT0_FRT_TCSA0_IRQZE              *((volatile unsigned int*)(0x42400634UL))\r
+#define bFM3_MFT0_FRT_TCSA0_IRQZF              *((volatile unsigned int*)(0x42400638UL))\r
+#define bFM3_MFT0_FRT_TCSA0_ECKE               *((volatile unsigned int*)(0x4240063CUL))\r
+#define bFM3_MFT0_FRT_TCSB0_AD0E               *((volatile unsigned int*)(0x42400680UL))\r
+#define bFM3_MFT0_FRT_TCSB0_AD1E               *((volatile unsigned int*)(0x42400684UL))\r
+#define bFM3_MFT0_FRT_TCSB0_AD2E               *((volatile unsigned int*)(0x42400688UL))\r
+#define bFM3_MFT0_FRT_TCSA1_CLK0               *((volatile unsigned int*)(0x42400800UL))\r
+#define bFM3_MFT0_FRT_TCSA1_CLK1               *((volatile unsigned int*)(0x42400804UL))\r
+#define bFM3_MFT0_FRT_TCSA1_CLK2               *((volatile unsigned int*)(0x42400808UL))\r
+#define bFM3_MFT0_FRT_TCSA1_CLK3               *((volatile unsigned int*)(0x4240080CUL))\r
+#define bFM3_MFT0_FRT_TCSA1_SCLR               *((volatile unsigned int*)(0x42400810UL))\r
+#define bFM3_MFT0_FRT_TCSA1_MODE               *((volatile unsigned int*)(0x42400814UL))\r
+#define bFM3_MFT0_FRT_TCSA1_STOP               *((volatile unsigned int*)(0x42400818UL))\r
+#define bFM3_MFT0_FRT_TCSA1_BFE                *((volatile unsigned int*)(0x4240081CUL))\r
+#define bFM3_MFT0_FRT_TCSA1_ICRE               *((volatile unsigned int*)(0x42400820UL))\r
+#define bFM3_MFT0_FRT_TCSA1_ICLR               *((volatile unsigned int*)(0x42400824UL))\r
+#define bFM3_MFT0_FRT_TCSA1_IRQZE              *((volatile unsigned int*)(0x42400834UL))\r
+#define bFM3_MFT0_FRT_TCSA1_IRQZF              *((volatile unsigned int*)(0x42400838UL))\r
+#define bFM3_MFT0_FRT_TCSA1_ECKE               *((volatile unsigned int*)(0x4240083CUL))\r
+#define bFM3_MFT0_FRT_TCSB1_AD0E               *((volatile unsigned int*)(0x42400880UL))\r
+#define bFM3_MFT0_FRT_TCSB1_AD1E               *((volatile unsigned int*)(0x42400884UL))\r
+#define bFM3_MFT0_FRT_TCSB1_AD2E               *((volatile unsigned int*)(0x42400888UL))\r
+#define bFM3_MFT0_FRT_TCSA2_CLK0               *((volatile unsigned int*)(0x42400A00UL))\r
+#define bFM3_MFT0_FRT_TCSA2_CLK1               *((volatile unsigned int*)(0x42400A04UL))\r
+#define bFM3_MFT0_FRT_TCSA2_CLK2               *((volatile unsigned int*)(0x42400A08UL))\r
+#define bFM3_MFT0_FRT_TCSA2_CLK3               *((volatile unsigned int*)(0x42400A0CUL))\r
+#define bFM3_MFT0_FRT_TCSA2_SCLR               *((volatile unsigned int*)(0x42400A10UL))\r
+#define bFM3_MFT0_FRT_TCSA2_MODE               *((volatile unsigned int*)(0x42400A14UL))\r
+#define bFM3_MFT0_FRT_TCSA2_STOP               *((volatile unsigned int*)(0x42400A18UL))\r
+#define bFM3_MFT0_FRT_TCSA2_BFE                *((volatile unsigned int*)(0x42400A1CUL))\r
+#define bFM3_MFT0_FRT_TCSA2_ICRE               *((volatile unsigned int*)(0x42400A20UL))\r
+#define bFM3_MFT0_FRT_TCSA2_ICLR               *((volatile unsigned int*)(0x42400A24UL))\r
+#define bFM3_MFT0_FRT_TCSA2_IRQZE              *((volatile unsigned int*)(0x42400A34UL))\r
+#define bFM3_MFT0_FRT_TCSA2_IRQZF              *((volatile unsigned int*)(0x42400A38UL))\r
+#define bFM3_MFT0_FRT_TCSA2_ECKE               *((volatile unsigned int*)(0x42400A3CUL))\r
+#define bFM3_MFT0_FRT_TCSB2_AD0E               *((volatile unsigned int*)(0x42400A80UL))\r
+#define bFM3_MFT0_FRT_TCSB2_AD1E               *((volatile unsigned int*)(0x42400A84UL))\r
+#define bFM3_MFT0_FRT_TCSB2_AD2E               *((volatile unsigned int*)(0x42400A88UL))\r
+\r
+/* Multifunction Timer unit 0 Output Compare Unit registers */\r
+#define bFM3_MFT0_OCU_OCSA10_CST0              *((volatile unsigned int*)(0x42400300UL))\r
+#define bFM3_MFT0_OCU_OCSA10_CST1              *((volatile unsigned int*)(0x42400304UL))\r
+#define bFM3_MFT0_OCU_OCSA10_BDIS0             *((volatile unsigned int*)(0x42400308UL))\r
+#define bFM3_MFT0_OCU_OCSA10_BDIS1             *((volatile unsigned int*)(0x4240030CUL))\r
+#define bFM3_MFT0_OCU_OCSA10_IOE0              *((volatile unsigned int*)(0x42400310UL))\r
+#define bFM3_MFT0_OCU_OCSA10_IOE1              *((volatile unsigned int*)(0x42400314UL))\r
+#define bFM3_MFT0_OCU_OCSA10_IOP0              *((volatile unsigned int*)(0x42400318UL))\r
+#define bFM3_MFT0_OCU_OCSA10_IOP1              *((volatile unsigned int*)(0x4240031CUL))\r
+#define bFM3_MFT0_OCU_OCSB10_OTD0              *((volatile unsigned int*)(0x42400320UL))\r
+#define bFM3_MFT0_OCU_OCSB10_OTD1              *((volatile unsigned int*)(0x42400324UL))\r
+#define bFM3_MFT0_OCU_OCSB10_CMOD              *((volatile unsigned int*)(0x42400330UL))\r
+#define bFM3_MFT0_OCU_OCSB10_BTS0              *((volatile unsigned int*)(0x42400334UL))\r
+#define bFM3_MFT0_OCU_OCSB10_BTS1              *((volatile unsigned int*)(0x42400338UL))\r
+#define bFM3_MFT0_OCU_OCSA32_CST2              *((volatile unsigned int*)(0x42400380UL))\r
+#define bFM3_MFT0_OCU_OCSA32_CST3              *((volatile unsigned int*)(0x42400384UL))\r
+#define bFM3_MFT0_OCU_OCSA32_BDIS2             *((volatile unsigned int*)(0x42400388UL))\r
+#define bFM3_MFT0_OCU_OCSA32_BDIS3             *((volatile unsigned int*)(0x4240038CUL))\r
+#define bFM3_MFT0_OCU_OCSA32_IOE2              *((volatile unsigned int*)(0x42400390UL))\r
+#define bFM3_MFT0_OCU_OCSA32_IOE3              *((volatile unsigned int*)(0x42400394UL))\r
+#define bFM3_MFT0_OCU_OCSA32_IOP2              *((volatile unsigned int*)(0x42400398UL))\r
+#define bFM3_MFT0_OCU_OCSA32_IOP3              *((volatile unsigned int*)(0x4240039CUL))\r
+#define bFM3_MFT0_OCU_OCSB32_OTD2              *((volatile unsigned int*)(0x424003A0UL))\r
+#define bFM3_MFT0_OCU_OCSB32_OTD3              *((volatile unsigned int*)(0x424003A4UL))\r
+#define bFM3_MFT0_OCU_OCSB32_CMOD              *((volatile unsigned int*)(0x424003B0UL))\r
+#define bFM3_MFT0_OCU_OCSB32_BTS2              *((volatile unsigned int*)(0x424003B4UL))\r
+#define bFM3_MFT0_OCU_OCSB32_BTS3              *((volatile unsigned int*)(0x424003B8UL))\r
+#define bFM3_MFT0_OCU_OCSA54_CST4              *((volatile unsigned int*)(0x42400400UL))\r
+#define bFM3_MFT0_OCU_OCSA54_CST5              *((volatile unsigned int*)(0x42400404UL))\r
+#define bFM3_MFT0_OCU_OCSA54_BDIS4             *((volatile unsigned int*)(0x42400408UL))\r
+#define bFM3_MFT0_OCU_OCSA54_BDIS5             *((volatile unsigned int*)(0x4240040CUL))\r
+#define bFM3_MFT0_OCU_OCSA54_IOE4              *((volatile unsigned int*)(0x42400410UL))\r
+#define bFM3_MFT0_OCU_OCSA54_IOE5              *((volatile unsigned int*)(0x42400414UL))\r
+#define bFM3_MFT0_OCU_OCSA54_IOP4              *((volatile unsigned int*)(0x42400418UL))\r
+#define bFM3_MFT0_OCU_OCSA54_IOP5              *((volatile unsigned int*)(0x4240041CUL))\r
+#define bFM3_MFT0_OCU_OCSB54_OTD4              *((volatile unsigned int*)(0x42400420UL))\r
+#define bFM3_MFT0_OCU_OCSB54_OTD5              *((volatile unsigned int*)(0x42400424UL))\r
+#define bFM3_MFT0_OCU_OCSB54_CMOD              *((volatile unsigned int*)(0x42400430UL))\r
+#define bFM3_MFT0_OCU_OCSB54_BTS4              *((volatile unsigned int*)(0x42400434UL))\r
+#define bFM3_MFT0_OCU_OCSB54_BTS5              *((volatile unsigned int*)(0x42400438UL))\r
+#define bFM3_MFT0_OCU_OCSC_MOD0                *((volatile unsigned int*)(0x424004A0UL))\r
+#define bFM3_MFT0_OCU_OCSC_MOD1                *((volatile unsigned int*)(0x424004A4UL))\r
+#define bFM3_MFT0_OCU_OCSC_MOD2                *((volatile unsigned int*)(0x424004A8UL))\r
+#define bFM3_MFT0_OCU_OCSC_MOD3                *((volatile unsigned int*)(0x424004ACUL))\r
+#define bFM3_MFT0_OCU_OCSC_MOD4                *((volatile unsigned int*)(0x424004B0UL))\r
+#define bFM3_MFT0_OCU_OCSC_MOD5                *((volatile unsigned int*)(0x424004B4UL))\r
+#define bFM3_MFT0_OCU_OCFS10_FSO00             *((volatile unsigned int*)(0x42400B00UL))\r
+#define bFM3_MFT0_OCU_OCFS10_FSO01             *((volatile unsigned int*)(0x42400B04UL))\r
+#define bFM3_MFT0_OCU_OCFS10_FSO02             *((volatile unsigned int*)(0x42400B08UL))\r
+#define bFM3_MFT0_OCU_OCFS10_FSO03             *((volatile unsigned int*)(0x42400B0CUL))\r
+#define bFM3_MFT0_OCU_OCFS10_FSO10             *((volatile unsigned int*)(0x42400B10UL))\r
+#define bFM3_MFT0_OCU_OCFS10_FSO11             *((volatile unsigned int*)(0x42400B14UL))\r
+#define bFM3_MFT0_OCU_OCFS10_FSO12             *((volatile unsigned int*)(0x42400B18UL))\r
+#define bFM3_MFT0_OCU_OCFS10_FSO13             *((volatile unsigned int*)(0x42400B1CUL))\r
+#define bFM3_MFT0_OCU_OCFS32_FSO20             *((volatile unsigned int*)(0x42400B20UL))\r
+#define bFM3_MFT0_OCU_OCFS32_FSO21             *((volatile unsigned int*)(0x42400B24UL))\r
+#define bFM3_MFT0_OCU_OCFS32_FSO22             *((volatile unsigned int*)(0x42400B28UL))\r
+#define bFM3_MFT0_OCU_OCFS32_FSO23             *((volatile unsigned int*)(0x42400B2CUL))\r
+#define bFM3_MFT0_OCU_OCFS32_FSO30             *((volatile unsigned int*)(0x42400B30UL))\r
+#define bFM3_MFT0_OCU_OCFS32_FSO31             *((volatile unsigned int*)(0x42400B34UL))\r
+#define bFM3_MFT0_OCU_OCFS32_FSO32             *((volatile unsigned int*)(0x42400B38UL))\r
+#define bFM3_MFT0_OCU_OCFS32_FSO33             *((volatile unsigned int*)(0x42400B3CUL))\r
+#define bFM3_MFT0_OCU_OCFS54_FSO40             *((volatile unsigned int*)(0x42400B80UL))\r
+#define bFM3_MFT0_OCU_OCFS54_FSO41             *((volatile unsigned int*)(0x42400B84UL))\r
+#define bFM3_MFT0_OCU_OCFS54_FSO42             *((volatile unsigned int*)(0x42400B88UL))\r
+#define bFM3_MFT0_OCU_OCFS54_FSO43             *((volatile unsigned int*)(0x42400B8CUL))\r
+#define bFM3_MFT0_OCU_OCFS54_FSO50             *((volatile unsigned int*)(0x42400B90UL))\r
+#define bFM3_MFT0_OCU_OCFS54_FSO51             *((volatile unsigned int*)(0x42400B94UL))\r
+#define bFM3_MFT0_OCU_OCFS54_FSO52             *((volatile unsigned int*)(0x42400B98UL))\r
+#define bFM3_MFT0_OCU_OCFS54_FSO53             *((volatile unsigned int*)(0x42400B9CUL))\r
+\r
+/* Multifunction Timer unit 0 Waveform Generator and Noise Canceler registers */\r
+#define bFM3_MFT0_WFG_WFSA10_DCK0              *((volatile unsigned int*)(0x42401180UL))\r
+#define bFM3_MFT0_WFG_WFSA10_DCK1              *((volatile unsigned int*)(0x42401184UL))\r
+#define bFM3_MFT0_WFG_WFSA10_DCK2              *((volatile unsigned int*)(0x42401188UL))\r
+#define bFM3_MFT0_WFG_WFSA10_TMD0              *((volatile unsigned int*)(0x4240118CUL))\r
+#define bFM3_MFT0_WFG_WFSA10_TMD1              *((volatile unsigned int*)(0x42401190UL))\r
+#define bFM3_MFT0_WFG_WFSA10_TMD2              *((volatile unsigned int*)(0x42401194UL))\r
+#define bFM3_MFT0_WFG_WFSA10_GTEN0             *((volatile unsigned int*)(0x42401198UL))\r
+#define bFM3_MFT0_WFG_WFSA10_GTEN1             *((volatile unsigned int*)(0x4240119CUL))\r
+#define bFM3_MFT0_WFG_WFSA10_PSEL0             *((volatile unsigned int*)(0x424011A0UL))\r
+#define bFM3_MFT0_WFG_WFSA10_PSEL1             *((volatile unsigned int*)(0x424011A4UL))\r
+#define bFM3_MFT0_WFG_WFSA10_PGEN0             *((volatile unsigned int*)(0x424011A8UL))\r
+#define bFM3_MFT0_WFG_WFSA10_PGEN1             *((volatile unsigned int*)(0x424011ACUL))\r
+#define bFM3_MFT0_WFG_WFSA10_DMOD              *((volatile unsigned int*)(0x424011B0UL))\r
+#define bFM3_MFT0_WFG_WFSA32_DCK0              *((volatile unsigned int*)(0x42401200UL))\r
+#define bFM3_MFT0_WFG_WFSA32_DCK1              *((volatile unsigned int*)(0x42401204UL))\r
+#define bFM3_MFT0_WFG_WFSA32_DCK2              *((volatile unsigned int*)(0x42401208UL))\r
+#define bFM3_MFT0_WFG_WFSA32_TMD0              *((volatile unsigned int*)(0x4240120CUL))\r
+#define bFM3_MFT0_WFG_WFSA32_TMD1              *((volatile unsigned int*)(0x42401210UL))\r
+#define bFM3_MFT0_WFG_WFSA32_TMD2              *((volatile unsigned int*)(0x42401214UL))\r
+#define bFM3_MFT0_WFG_WFSA32_GTEN0             *((volatile unsigned int*)(0x42401218UL))\r
+#define bFM3_MFT0_WFG_WFSA32_GTEN1             *((volatile unsigned int*)(0x4240121CUL))\r
+#define bFM3_MFT0_WFG_WFSA32_PSEL0             *((volatile unsigned int*)(0x42401220UL))\r
+#define bFM3_MFT0_WFG_WFSA32_PSEL1             *((volatile unsigned int*)(0x42401224UL))\r
+#define bFM3_MFT0_WFG_WFSA32_PGEN0             *((volatile unsigned int*)(0x42401228UL))\r
+#define bFM3_MFT0_WFG_WFSA32_PGEN1             *((volatile unsigned int*)(0x4240122CUL))\r
+#define bFM3_MFT0_WFG_WFSA32_DMOD              *((volatile unsigned int*)(0x42401230UL))\r
+#define bFM3_MFT0_WFG_WFSA54_DCK0              *((volatile unsigned int*)(0x42401280UL))\r
+#define bFM3_MFT0_WFG_WFSA54_DCK1              *((volatile unsigned int*)(0x42401284UL))\r
+#define bFM3_MFT0_WFG_WFSA54_DCK2              *((volatile unsigned int*)(0x42401288UL))\r
+#define bFM3_MFT0_WFG_WFSA54_TMD0              *((volatile unsigned int*)(0x4240128CUL))\r
+#define bFM3_MFT0_WFG_WFSA54_TMD1              *((volatile unsigned int*)(0x42401290UL))\r
+#define bFM3_MFT0_WFG_WFSA54_TMD2              *((volatile unsigned int*)(0x42401294UL))\r
+#define bFM3_MFT0_WFG_WFSA54_GTEN0             *((volatile unsigned int*)(0x42401298UL))\r
+#define bFM3_MFT0_WFG_WFSA54_GTEN1             *((volatile unsigned int*)(0x4240129CUL))\r
+#define bFM3_MFT0_WFG_WFSA54_PSEL0             *((volatile unsigned int*)(0x424012A0UL))\r
+#define bFM3_MFT0_WFG_WFSA54_PSEL1             *((volatile unsigned int*)(0x424012A4UL))\r
+#define bFM3_MFT0_WFG_WFSA54_PGEN0             *((volatile unsigned int*)(0x424012A8UL))\r
+#define bFM3_MFT0_WFG_WFSA54_PGEN1             *((volatile unsigned int*)(0x424012ACUL))\r
+#define bFM3_MFT0_WFG_WFSA54_DMOD              *((volatile unsigned int*)(0x424012B0UL))\r
+#define bFM3_MFT0_WFG_WFIR_DTIF                *((volatile unsigned int*)(0x42401300UL))\r
+#define bFM3_MFT0_WFG_WFIR_DTIC                *((volatile unsigned int*)(0x42401304UL))\r
+#define bFM3_MFT0_WFG_WFIR_TMIF10              *((volatile unsigned int*)(0x42401310UL))\r
+#define bFM3_MFT0_WFG_WFIR_TMIC10              *((volatile unsigned int*)(0x42401314UL))\r
+#define bFM3_MFT0_WFG_WFIR_TMIE10              *((volatile unsigned int*)(0x42401318UL))\r
+#define bFM3_MFT0_WFG_WFIR_TMIS10              *((volatile unsigned int*)(0x4240131CUL))\r
+#define bFM3_MFT0_WFG_WFIR_TMIF32              *((volatile unsigned int*)(0x42401320UL))\r
+#define bFM3_MFT0_WFG_WFIR_TMIC32              *((volatile unsigned int*)(0x42401324UL))\r
+#define bFM3_MFT0_WFG_WFIR_TMIE32              *((volatile unsigned int*)(0x42401328UL))\r
+#define bFM3_MFT0_WFG_WFIR_TMIS32              *((volatile unsigned int*)(0x4240132CUL))\r
+#define bFM3_MFT0_WFG_WFIR_TMIF54              *((volatile unsigned int*)(0x42401330UL))\r
+#define bFM3_MFT0_WFG_WFIR_TMIC54              *((volatile unsigned int*)(0x42401334UL))\r
+#define bFM3_MFT0_WFG_WFIR_TMIE54              *((volatile unsigned int*)(0x42401338UL))\r
+#define bFM3_MFT0_WFG_WFIR_TMIS54              *((volatile unsigned int*)(0x4240133CUL))\r
+#define bFM3_MFT0_WFG_NZCL_DTIE                *((volatile unsigned int*)(0x42401380UL))\r
+#define bFM3_MFT0_WFG_NZCL_NWS0                *((volatile unsigned int*)(0x42401384UL))\r
+#define bFM3_MFT0_WFG_NZCL_NWS1                *((volatile unsigned int*)(0x42401388UL))\r
+#define bFM3_MFT0_WFG_NZCL_NWS2                *((volatile unsigned int*)(0x4240138CUL))\r
+#define bFM3_MFT0_WFG_NZCL_SDTI                *((volatile unsigned int*)(0x42401390UL))\r
+\r
+/* Multifunction Timer unit 0 Input Capture Unit registers */\r
+#define bFM3_MFT0_ICU_ICFS10_FSI00             *((volatile unsigned int*)(0x42400C00UL))\r
+#define bFM3_MFT0_ICU_ICFS10_FSI01             *((volatile unsigned int*)(0x42400C04UL))\r
+#define bFM3_MFT0_ICU_ICFS10_FSI02             *((volatile unsigned int*)(0x42400C08UL))\r
+#define bFM3_MFT0_ICU_ICFS10_FSI03             *((volatile unsigned int*)(0x42400C0CUL))\r
+#define bFM3_MFT0_ICU_ICFS10_FSI10             *((volatile unsigned int*)(0x42400C10UL))\r
+#define bFM3_MFT0_ICU_ICFS10_FSI11             *((volatile unsigned int*)(0x42400C14UL))\r
+#define bFM3_MFT0_ICU_ICFS10_FSI12             *((volatile unsigned int*)(0x42400C18UL))\r
+#define bFM3_MFT0_ICU_ICFS10_FSI13             *((volatile unsigned int*)(0x42400C1CUL))\r
+#define bFM3_MFT0_ICU_ICFS32_FSI20             *((volatile unsigned int*)(0x42400C20UL))\r
+#define bFM3_MFT0_ICU_ICFS32_FSI21             *((volatile unsigned int*)(0x42400C24UL))\r
+#define bFM3_MFT0_ICU_ICFS32_FSI22             *((volatile unsigned int*)(0x42400C28UL))\r
+#define bFM3_MFT0_ICU_ICFS32_FSI23             *((volatile unsigned int*)(0x42400C2CUL))\r
+#define bFM3_MFT0_ICU_ICFS32_FSI30             *((volatile unsigned int*)(0x42400C30UL))\r
+#define bFM3_MFT0_ICU_ICFS32_FSI31             *((volatile unsigned int*)(0x42400C34UL))\r
+#define bFM3_MFT0_ICU_ICFS32_FSI32             *((volatile unsigned int*)(0x42400C38UL))\r
+#define bFM3_MFT0_ICU_ICFS32_FSI33             *((volatile unsigned int*)(0x42400C3CUL))\r
+#define bFM3_MFT0_ICU_ICSA10_EG00              *((volatile unsigned int*)(0x42400F00UL))\r
+#define bFM3_MFT0_ICU_ICSA10_EG01              *((volatile unsigned int*)(0x42400F04UL))\r
+#define bFM3_MFT0_ICU_ICSA10_EG10              *((volatile unsigned int*)(0x42400F08UL))\r
+#define bFM3_MFT0_ICU_ICSA10_EG11              *((volatile unsigned int*)(0x42400F0CUL))\r
+#define bFM3_MFT0_ICU_ICSA10_ICE0              *((volatile unsigned int*)(0x42400F10UL))\r
+#define bFM3_MFT0_ICU_ICSA10_ICE1              *((volatile unsigned int*)(0x42400F14UL))\r
+#define bFM3_MFT0_ICU_ICSA10_ICP0              *((volatile unsigned int*)(0x42400F18UL))\r
+#define bFM3_MFT0_ICU_ICSA10_ICP1              *((volatile unsigned int*)(0x42400F1CUL))\r
+#define bFM3_MFT0_ICU_ICSB10_IEI0              *((volatile unsigned int*)(0x42400F20UL))\r
+#define bFM3_MFT0_ICU_ICSB10_IEI1              *((volatile unsigned int*)(0x42400F24UL))\r
+#define bFM3_MFT0_ICU_ICSA32_EG20              *((volatile unsigned int*)(0x42400F80UL))\r
+#define bFM3_MFT0_ICU_ICSA32_EG21              *((volatile unsigned int*)(0x42400F84UL))\r
+#define bFM3_MFT0_ICU_ICSA32_EG30              *((volatile unsigned int*)(0x42400F88UL))\r
+#define bFM3_MFT0_ICU_ICSA32_EG31              *((volatile unsigned int*)(0x42400F8CUL))\r
+#define bFM3_MFT0_ICU_ICSA32_ICE2              *((volatile unsigned int*)(0x42400F90UL))\r
+#define bFM3_MFT0_ICU_ICSA32_ICE3              *((volatile unsigned int*)(0x42400F94UL))\r
+#define bFM3_MFT0_ICU_ICSA32_ICP2              *((volatile unsigned int*)(0x42400F98UL))\r
+#define bFM3_MFT0_ICU_ICSA32_ICP3              *((volatile unsigned int*)(0x42400F9CUL))\r
+#define bFM3_MFT0_ICU_ICSB32_IEI2              *((volatile unsigned int*)(0x42400FA0UL))\r
+#define bFM3_MFT0_ICU_ICSB32_IEI3              *((volatile unsigned int*)(0x42400FA4UL))\r
+\r
+/* Multifunction Timer unit 0 ADC Start Compare Unit registers */\r
+#define bFM3_MFT0_ADCMP_ACSB_BDIS0             *((volatile unsigned int*)(0x42401700UL))\r
+#define bFM3_MFT0_ADCMP_ACSB_BDIS1             *((volatile unsigned int*)(0x42401704UL))\r
+#define bFM3_MFT0_ADCMP_ACSB_BDIS2             *((volatile unsigned int*)(0x42401708UL))\r
+#define bFM3_MFT0_ADCMP_ACSB_BTS0              *((volatile unsigned int*)(0x42401710UL))\r
+#define bFM3_MFT0_ADCMP_ACSB_BTS1              *((volatile unsigned int*)(0x42401714UL))\r
+#define bFM3_MFT0_ADCMP_ACSB_BTS2              *((volatile unsigned int*)(0x42401718UL))\r
+#define bFM3_MFT0_ADCMP_ACSA_CE00              *((volatile unsigned int*)(0x42401780UL))\r
+#define bFM3_MFT0_ADCMP_ACSA_CE01              *((volatile unsigned int*)(0x42401784UL))\r
+#define bFM3_MFT0_ADCMP_ACSA_CE10              *((volatile unsigned int*)(0x42401788UL))\r
+#define bFM3_MFT0_ADCMP_ACSA_CE11              *((volatile unsigned int*)(0x4240178CUL))\r
+#define bFM3_MFT0_ADCMP_ACSA_CE20              *((volatile unsigned int*)(0x42401790UL))\r
+#define bFM3_MFT0_ADCMP_ACSA_CE21              *((volatile unsigned int*)(0x42401794UL))\r
+#define bFM3_MFT0_ADCMP_ACSA_SEL00             *((volatile unsigned int*)(0x424017A0UL))\r
+#define bFM3_MFT0_ADCMP_ACSA_SEL01             *((volatile unsigned int*)(0x424017A4UL))\r
+#define bFM3_MFT0_ADCMP_ACSA_SEL10             *((volatile unsigned int*)(0x424017A8UL))\r
+#define bFM3_MFT0_ADCMP_ACSA_SEL11             *((volatile unsigned int*)(0x424017ACUL))\r
+#define bFM3_MFT0_ADCMP_ACSA_SEL20             *((volatile unsigned int*)(0x424017B0UL))\r
+#define bFM3_MFT0_ADCMP_ACSA_SEL21             *((volatile unsigned int*)(0x424017B4UL))\r
+#define bFM3_MFT0_ADCMP_ATSA_AD0S0             *((volatile unsigned int*)(0x42401800UL))\r
+#define bFM3_MFT0_ADCMP_ATSA_AD0S1             *((volatile unsigned int*)(0x42401804UL))\r
+#define bFM3_MFT0_ADCMP_ATSA_AD1S0             *((volatile unsigned int*)(0x42401808UL))\r
+#define bFM3_MFT0_ADCMP_ATSA_AD1S1             *((volatile unsigned int*)(0x4240180CUL))\r
+#define bFM3_MFT0_ADCMP_ATSA_AD2S0             *((volatile unsigned int*)(0x42401810UL))\r
+#define bFM3_MFT0_ADCMP_ATSA_AD2S1             *((volatile unsigned int*)(0x42401814UL))\r
+#define bFM3_MFT0_ADCMP_ATSA_AD0P0             *((volatile unsigned int*)(0x42401820UL))\r
+#define bFM3_MFT0_ADCMP_ATSA_AD0P1             *((volatile unsigned int*)(0x42401824UL))\r
+#define bFM3_MFT0_ADCMP_ATSA_AD1P0             *((volatile unsigned int*)(0x42401828UL))\r
+#define bFM3_MFT0_ADCMP_ATSA_AD1P1             *((volatile unsigned int*)(0x4240182CUL))\r
+#define bFM3_MFT0_ADCMP_ATSA_AD2P0             *((volatile unsigned int*)(0x42401830UL))\r
+#define bFM3_MFT0_ADCMP_ATSA_AD2P1             *((volatile unsigned int*)(0x42401834UL))\r
+\r
+/* Multifunction Timer unit 1 Free Running Timer registers */\r
+#define bFM3_MFT1_FRT_TCSA0_CLK0               *((volatile unsigned int*)(0x42420600UL))\r
+#define bFM3_MFT1_FRT_TCSA0_CLK1               *((volatile unsigned int*)(0x42420604UL))\r
+#define bFM3_MFT1_FRT_TCSA0_CLK2               *((volatile unsigned int*)(0x42420608UL))\r
+#define bFM3_MFT1_FRT_TCSA0_CLK3               *((volatile unsigned int*)(0x4242060CUL))\r
+#define bFM3_MFT1_FRT_TCSA0_SCLR               *((volatile unsigned int*)(0x42420610UL))\r
+#define bFM3_MFT1_FRT_TCSA0_MODE               *((volatile unsigned int*)(0x42420614UL))\r
+#define bFM3_MFT1_FRT_TCSA0_STOP               *((volatile unsigned int*)(0x42420618UL))\r
+#define bFM3_MFT1_FRT_TCSA0_BFE                *((volatile unsigned int*)(0x4242061CUL))\r
+#define bFM3_MFT1_FRT_TCSA0_ICRE               *((volatile unsigned int*)(0x42420620UL))\r
+#define bFM3_MFT1_FRT_TCSA0_ICLR               *((volatile unsigned int*)(0x42420624UL))\r
+#define bFM3_MFT1_FRT_TCSA0_IRQZE              *((volatile unsigned int*)(0x42420634UL))\r
+#define bFM3_MFT1_FRT_TCSA0_IRQZF              *((volatile unsigned int*)(0x42420638UL))\r
+#define bFM3_MFT1_FRT_TCSA0_ECKE               *((volatile unsigned int*)(0x4242063CUL))\r
+#define bFM3_MFT1_FRT_TCSB0_AD0E               *((volatile unsigned int*)(0x42420680UL))\r
+#define bFM3_MFT1_FRT_TCSB0_AD1E               *((volatile unsigned int*)(0x42420684UL))\r
+#define bFM3_MFT1_FRT_TCSB0_AD2E               *((volatile unsigned int*)(0x42420688UL))\r
+#define bFM3_MFT1_FRT_TCSA1_CLK0               *((volatile unsigned int*)(0x42420800UL))\r
+#define bFM3_MFT1_FRT_TCSA1_CLK1               *((volatile unsigned int*)(0x42420804UL))\r
+#define bFM3_MFT1_FRT_TCSA1_CLK2               *((volatile unsigned int*)(0x42420808UL))\r
+#define bFM3_MFT1_FRT_TCSA1_CLK3               *((volatile unsigned int*)(0x4242080CUL))\r
+#define bFM3_MFT1_FRT_TCSA1_SCLR               *((volatile unsigned int*)(0x42420810UL))\r
+#define bFM3_MFT1_FRT_TCSA1_MODE               *((volatile unsigned int*)(0x42420814UL))\r
+#define bFM3_MFT1_FRT_TCSA1_STOP               *((volatile unsigned int*)(0x42420818UL))\r
+#define bFM3_MFT1_FRT_TCSA1_BFE                *((volatile unsigned int*)(0x4242081CUL))\r
+#define bFM3_MFT1_FRT_TCSA1_ICRE               *((volatile unsigned int*)(0x42420820UL))\r
+#define bFM3_MFT1_FRT_TCSA1_ICLR               *((volatile unsigned int*)(0x42420824UL))\r
+#define bFM3_MFT1_FRT_TCSA1_IRQZE              *((volatile unsigned int*)(0x42420834UL))\r
+#define bFM3_MFT1_FRT_TCSA1_IRQZF              *((volatile unsigned int*)(0x42420838UL))\r
+#define bFM3_MFT1_FRT_TCSA1_ECKE               *((volatile unsigned int*)(0x4242083CUL))\r
+#define bFM3_MFT1_FRT_TCSB1_AD0E               *((volatile unsigned int*)(0x42420880UL))\r
+#define bFM3_MFT1_FRT_TCSB1_AD1E               *((volatile unsigned int*)(0x42420884UL))\r
+#define bFM3_MFT1_FRT_TCSB1_AD2E               *((volatile unsigned int*)(0x42420888UL))\r
+#define bFM3_MFT1_FRT_TCSA2_CLK0               *((volatile unsigned int*)(0x42420A00UL))\r
+#define bFM3_MFT1_FRT_TCSA2_CLK1               *((volatile unsigned int*)(0x42420A04UL))\r
+#define bFM3_MFT1_FRT_TCSA2_CLK2               *((volatile unsigned int*)(0x42420A08UL))\r
+#define bFM3_MFT1_FRT_TCSA2_CLK3               *((volatile unsigned int*)(0x42420A0CUL))\r
+#define bFM3_MFT1_FRT_TCSA2_SCLR               *((volatile unsigned int*)(0x42420A10UL))\r
+#define bFM3_MFT1_FRT_TCSA2_MODE               *((volatile unsigned int*)(0x42420A14UL))\r
+#define bFM3_MFT1_FRT_TCSA2_STOP               *((volatile unsigned int*)(0x42420A18UL))\r
+#define bFM3_MFT1_FRT_TCSA2_BFE                *((volatile unsigned int*)(0x42420A1CUL))\r
+#define bFM3_MFT1_FRT_TCSA2_ICRE               *((volatile unsigned int*)(0x42420A20UL))\r
+#define bFM3_MFT1_FRT_TCSA2_ICLR               *((volatile unsigned int*)(0x42420A24UL))\r
+#define bFM3_MFT1_FRT_TCSA2_IRQZE              *((volatile unsigned int*)(0x42420A34UL))\r
+#define bFM3_MFT1_FRT_TCSA2_IRQZF              *((volatile unsigned int*)(0x42420A38UL))\r
+#define bFM3_MFT1_FRT_TCSA2_ECKE               *((volatile unsigned int*)(0x42420A3CUL))\r
+#define bFM3_MFT1_FRT_TCSB2_AD0E               *((volatile unsigned int*)(0x42420A80UL))\r
+#define bFM3_MFT1_FRT_TCSB2_AD1E               *((volatile unsigned int*)(0x42420A84UL))\r
+#define bFM3_MFT1_FRT_TCSB2_AD2E               *((volatile unsigned int*)(0x42420A88UL))\r
+\r
+/* Multifunction Timer unit 1 Output Compare Unit registers */\r
+#define bFM3_MFT1_OCU_OCSA10_CST0              *((volatile unsigned int*)(0x42420300UL))\r
+#define bFM3_MFT1_OCU_OCSA10_CST1              *((volatile unsigned int*)(0x42420304UL))\r
+#define bFM3_MFT1_OCU_OCSA10_BDIS0             *((volatile unsigned int*)(0x42420308UL))\r
+#define bFM3_MFT1_OCU_OCSA10_BDIS1             *((volatile unsigned int*)(0x4242030CUL))\r
+#define bFM3_MFT1_OCU_OCSA10_IOE0              *((volatile unsigned int*)(0x42420310UL))\r
+#define bFM3_MFT1_OCU_OCSA10_IOE1              *((volatile unsigned int*)(0x42420314UL))\r
+#define bFM3_MFT1_OCU_OCSA10_IOP0              *((volatile unsigned int*)(0x42420318UL))\r
+#define bFM3_MFT1_OCU_OCSA10_IOP1              *((volatile unsigned int*)(0x4242031CUL))\r
+#define bFM3_MFT1_OCU_OCSB10_OTD0              *((volatile unsigned int*)(0x42420320UL))\r
+#define bFM3_MFT1_OCU_OCSB10_OTD1              *((volatile unsigned int*)(0x42420324UL))\r
+#define bFM3_MFT1_OCU_OCSB10_CMOD              *((volatile unsigned int*)(0x42420330UL))\r
+#define bFM3_MFT1_OCU_OCSB10_BTS0              *((volatile unsigned int*)(0x42420334UL))\r
+#define bFM3_MFT1_OCU_OCSB10_BTS1              *((volatile unsigned int*)(0x42420338UL))\r
+#define bFM3_MFT1_OCU_OCSA32_CST2              *((volatile unsigned int*)(0x42420380UL))\r
+#define bFM3_MFT1_OCU_OCSA32_CST3              *((volatile unsigned int*)(0x42420384UL))\r
+#define bFM3_MFT1_OCU_OCSA32_BDIS2             *((volatile unsigned int*)(0x42420388UL))\r
+#define bFM3_MFT1_OCU_OCSA32_BDIS3             *((volatile unsigned int*)(0x4242038CUL))\r
+#define bFM3_MFT1_OCU_OCSA32_IOE2              *((volatile unsigned int*)(0x42420390UL))\r
+#define bFM3_MFT1_OCU_OCSA32_IOE3              *((volatile unsigned int*)(0x42420394UL))\r
+#define bFM3_MFT1_OCU_OCSA32_IOP2              *((volatile unsigned int*)(0x42420398UL))\r
+#define bFM3_MFT1_OCU_OCSA32_IOP3              *((volatile unsigned int*)(0x4242039CUL))\r
+#define bFM3_MFT1_OCU_OCSB32_OTD2              *((volatile unsigned int*)(0x424203A0UL))\r
+#define bFM3_MFT1_OCU_OCSB32_OTD3              *((volatile unsigned int*)(0x424203A4UL))\r
+#define bFM3_MFT1_OCU_OCSB32_CMOD              *((volatile unsigned int*)(0x424203B0UL))\r
+#define bFM3_MFT1_OCU_OCSB32_BTS2              *((volatile unsigned int*)(0x424203B4UL))\r
+#define bFM3_MFT1_OCU_OCSB32_BTS3              *((volatile unsigned int*)(0x424203B8UL))\r
+#define bFM3_MFT1_OCU_OCSA54_CST4              *((volatile unsigned int*)(0x42420400UL))\r
+#define bFM3_MFT1_OCU_OCSA54_CST5              *((volatile unsigned int*)(0x42420404UL))\r
+#define bFM3_MFT1_OCU_OCSA54_BDIS4             *((volatile unsigned int*)(0x42420408UL))\r
+#define bFM3_MFT1_OCU_OCSA54_BDIS5             *((volatile unsigned int*)(0x4242040CUL))\r
+#define bFM3_MFT1_OCU_OCSA54_IOE4              *((volatile unsigned int*)(0x42420410UL))\r
+#define bFM3_MFT1_OCU_OCSA54_IOE5              *((volatile unsigned int*)(0x42420414UL))\r
+#define bFM3_MFT1_OCU_OCSA54_IOP4              *((volatile unsigned int*)(0x42420418UL))\r
+#define bFM3_MFT1_OCU_OCSA54_IOP5              *((volatile unsigned int*)(0x4242041CUL))\r
+#define bFM3_MFT1_OCU_OCSB54_OTD4              *((volatile unsigned int*)(0x42420420UL))\r
+#define bFM3_MFT1_OCU_OCSB54_OTD5              *((volatile unsigned int*)(0x42420424UL))\r
+#define bFM3_MFT1_OCU_OCSB54_CMOD              *((volatile unsigned int*)(0x42420430UL))\r
+#define bFM3_MFT1_OCU_OCSB54_BTS4              *((volatile unsigned int*)(0x42420434UL))\r
+#define bFM3_MFT1_OCU_OCSB54_BTS5              *((volatile unsigned int*)(0x42420438UL))\r
+#define bFM3_MFT1_OCU_OCSC_MOD0                *((volatile unsigned int*)(0x424204A0UL))\r
+#define bFM3_MFT1_OCU_OCSC_MOD1                *((volatile unsigned int*)(0x424204A4UL))\r
+#define bFM3_MFT1_OCU_OCSC_MOD2                *((volatile unsigned int*)(0x424204A8UL))\r
+#define bFM3_MFT1_OCU_OCSC_MOD3                *((volatile unsigned int*)(0x424204ACUL))\r
+#define bFM3_MFT1_OCU_OCSC_MOD4                *((volatile unsigned int*)(0x424204B0UL))\r
+#define bFM3_MFT1_OCU_OCSC_MOD5                *((volatile unsigned int*)(0x424204B4UL))\r
+#define bFM3_MFT1_OCU_OCFS10_FSO00             *((volatile unsigned int*)(0x42420B00UL))\r
+#define bFM3_MFT1_OCU_OCFS10_FSO01             *((volatile unsigned int*)(0x42420B04UL))\r
+#define bFM3_MFT1_OCU_OCFS10_FSO02             *((volatile unsigned int*)(0x42420B08UL))\r
+#define bFM3_MFT1_OCU_OCFS10_FSO03             *((volatile unsigned int*)(0x42420B0CUL))\r
+#define bFM3_MFT1_OCU_OCFS10_FSO10             *((volatile unsigned int*)(0x42420B10UL))\r
+#define bFM3_MFT1_OCU_OCFS10_FSO11             *((volatile unsigned int*)(0x42420B14UL))\r
+#define bFM3_MFT1_OCU_OCFS10_FSO12             *((volatile unsigned int*)(0x42420B18UL))\r
+#define bFM3_MFT1_OCU_OCFS10_FSO13             *((volatile unsigned int*)(0x42420B1CUL))\r
+#define bFM3_MFT1_OCU_OCFS32_FSO20             *((volatile unsigned int*)(0x42420B20UL))\r
+#define bFM3_MFT1_OCU_OCFS32_FSO21             *((volatile unsigned int*)(0x42420B24UL))\r
+#define bFM3_MFT1_OCU_OCFS32_FSO22             *((volatile unsigned int*)(0x42420B28UL))\r
+#define bFM3_MFT1_OCU_OCFS32_FSO23             *((volatile unsigned int*)(0x42420B2CUL))\r
+#define bFM3_MFT1_OCU_OCFS32_FSO30             *((volatile unsigned int*)(0x42420B30UL))\r
+#define bFM3_MFT1_OCU_OCFS32_FSO31             *((volatile unsigned int*)(0x42420B34UL))\r
+#define bFM3_MFT1_OCU_OCFS32_FSO32             *((volatile unsigned int*)(0x42420B38UL))\r
+#define bFM3_MFT1_OCU_OCFS32_FSO33             *((volatile unsigned int*)(0x42420B3CUL))\r
+#define bFM3_MFT1_OCU_OCFS54_FSO40             *((volatile unsigned int*)(0x42420B80UL))\r
+#define bFM3_MFT1_OCU_OCFS54_FSO41             *((volatile unsigned int*)(0x42420B84UL))\r
+#define bFM3_MFT1_OCU_OCFS54_FSO42             *((volatile unsigned int*)(0x42420B88UL))\r
+#define bFM3_MFT1_OCU_OCFS54_FSO43             *((volatile unsigned int*)(0x42420B8CUL))\r
+#define bFM3_MFT1_OCU_OCFS54_FSO50             *((volatile unsigned int*)(0x42420B90UL))\r
+#define bFM3_MFT1_OCU_OCFS54_FSO51             *((volatile unsigned int*)(0x42420B94UL))\r
+#define bFM3_MFT1_OCU_OCFS54_FSO52             *((volatile unsigned int*)(0x42420B98UL))\r
+#define bFM3_MFT1_OCU_OCFS54_FSO53             *((volatile unsigned int*)(0x42420B9CUL))\r
+\r
+/* Multifunction Timer unit 1 Waveform Generator and Noise Canceler registers */\r
+#define bFM3_MFT1_WFG_WFSA10_DCK0              *((volatile unsigned int*)(0x42421180UL))\r
+#define bFM3_MFT1_WFG_WFSA10_DCK1              *((volatile unsigned int*)(0x42421184UL))\r
+#define bFM3_MFT1_WFG_WFSA10_DCK2              *((volatile unsigned int*)(0x42421188UL))\r
+#define bFM3_MFT1_WFG_WFSA10_TMD0              *((volatile unsigned int*)(0x4242118CUL))\r
+#define bFM3_MFT1_WFG_WFSA10_TMD1              *((volatile unsigned int*)(0x42421190UL))\r
+#define bFM3_MFT1_WFG_WFSA10_TMD2              *((volatile unsigned int*)(0x42421194UL))\r
+#define bFM3_MFT1_WFG_WFSA10_GTEN0             *((volatile unsigned int*)(0x42421198UL))\r
+#define bFM3_MFT1_WFG_WFSA10_GTEN1             *((volatile unsigned int*)(0x4242119CUL))\r
+#define bFM3_MFT1_WFG_WFSA10_PSEL0             *((volatile unsigned int*)(0x424211A0UL))\r
+#define bFM3_MFT1_WFG_WFSA10_PSEL1             *((volatile unsigned int*)(0x424211A4UL))\r
+#define bFM3_MFT1_WFG_WFSA10_PGEN0             *((volatile unsigned int*)(0x424211A8UL))\r
+#define bFM3_MFT1_WFG_WFSA10_PGEN1             *((volatile unsigned int*)(0x424211ACUL))\r
+#define bFM3_MFT1_WFG_WFSA10_DMOD              *((volatile unsigned int*)(0x424211B0UL))\r
+#define bFM3_MFT1_WFG_WFSA32_DCK0              *((volatile unsigned int*)(0x42421200UL))\r
+#define bFM3_MFT1_WFG_WFSA32_DCK1              *((volatile unsigned int*)(0x42421204UL))\r
+#define bFM3_MFT1_WFG_WFSA32_DCK2              *((volatile unsigned int*)(0x42421208UL))\r
+#define bFM3_MFT1_WFG_WFSA32_TMD0              *((volatile unsigned int*)(0x4242120CUL))\r
+#define bFM3_MFT1_WFG_WFSA32_TMD1              *((volatile unsigned int*)(0x42421210UL))\r
+#define bFM3_MFT1_WFG_WFSA32_TMD2              *((volatile unsigned int*)(0x42421214UL))\r
+#define bFM3_MFT1_WFG_WFSA32_GTEN0             *((volatile unsigned int*)(0x42421218UL))\r
+#define bFM3_MFT1_WFG_WFSA32_GTEN1             *((volatile unsigned int*)(0x4242121CUL))\r
+#define bFM3_MFT1_WFG_WFSA32_PSEL0             *((volatile unsigned int*)(0x42421220UL))\r
+#define bFM3_MFT1_WFG_WFSA32_PSEL1             *((volatile unsigned int*)(0x42421224UL))\r
+#define bFM3_MFT1_WFG_WFSA32_PGEN0             *((volatile unsigned int*)(0x42421228UL))\r
+#define bFM3_MFT1_WFG_WFSA32_PGEN1             *((volatile unsigned int*)(0x4242122CUL))\r
+#define bFM3_MFT1_WFG_WFSA32_DMOD              *((volatile unsigned int*)(0x42421230UL))\r
+#define bFM3_MFT1_WFG_WFSA54_DCK0              *((volatile unsigned int*)(0x42421280UL))\r
+#define bFM3_MFT1_WFG_WFSA54_DCK1              *((volatile unsigned int*)(0x42421284UL))\r
+#define bFM3_MFT1_WFG_WFSA54_DCK2              *((volatile unsigned int*)(0x42421288UL))\r
+#define bFM3_MFT1_WFG_WFSA54_TMD0              *((volatile unsigned int*)(0x4242128CUL))\r
+#define bFM3_MFT1_WFG_WFSA54_TMD1              *((volatile unsigned int*)(0x42421290UL))\r
+#define bFM3_MFT1_WFG_WFSA54_TMD2              *((volatile unsigned int*)(0x42421294UL))\r
+#define bFM3_MFT1_WFG_WFSA54_GTEN0             *((volatile unsigned int*)(0x42421298UL))\r
+#define bFM3_MFT1_WFG_WFSA54_GTEN1             *((volatile unsigned int*)(0x4242129CUL))\r
+#define bFM3_MFT1_WFG_WFSA54_PSEL0             *((volatile unsigned int*)(0x424212A0UL))\r
+#define bFM3_MFT1_WFG_WFSA54_PSEL1             *((volatile unsigned int*)(0x424212A4UL))\r
+#define bFM3_MFT1_WFG_WFSA54_PGEN0             *((volatile unsigned int*)(0x424212A8UL))\r
+#define bFM3_MFT1_WFG_WFSA54_PGEN1             *((volatile unsigned int*)(0x424212ACUL))\r
+#define bFM3_MFT1_WFG_WFSA54_DMOD              *((volatile unsigned int*)(0x424212B0UL))\r
+#define bFM3_MFT1_WFG_WFIR_DTIF                *((volatile unsigned int*)(0x42421300UL))\r
+#define bFM3_MFT1_WFG_WFIR_DTIC                *((volatile unsigned int*)(0x42421304UL))\r
+#define bFM3_MFT1_WFG_WFIR_TMIF10              *((volatile unsigned int*)(0x42421310UL))\r
+#define bFM3_MFT1_WFG_WFIR_TMIC10              *((volatile unsigned int*)(0x42421314UL))\r
+#define bFM3_MFT1_WFG_WFIR_TMIE10              *((volatile unsigned int*)(0x42421318UL))\r
+#define bFM3_MFT1_WFG_WFIR_TMIS10              *((volatile unsigned int*)(0x4242131CUL))\r
+#define bFM3_MFT1_WFG_WFIR_TMIF32              *((volatile unsigned int*)(0x42421320UL))\r
+#define bFM3_MFT1_WFG_WFIR_TMIC32              *((volatile unsigned int*)(0x42421324UL))\r
+#define bFM3_MFT1_WFG_WFIR_TMIE32              *((volatile unsigned int*)(0x42421328UL))\r
+#define bFM3_MFT1_WFG_WFIR_TMIS32              *((volatile unsigned int*)(0x4242132CUL))\r
+#define bFM3_MFT1_WFG_WFIR_TMIF54              *((volatile unsigned int*)(0x42421330UL))\r
+#define bFM3_MFT1_WFG_WFIR_TMIC54              *((volatile unsigned int*)(0x42421334UL))\r
+#define bFM3_MFT1_WFG_WFIR_TMIE54              *((volatile unsigned int*)(0x42421338UL))\r
+#define bFM3_MFT1_WFG_WFIR_TMIS54              *((volatile unsigned int*)(0x4242133CUL))\r
+#define bFM3_MFT1_WFG_NZCL_DTIE                *((volatile unsigned int*)(0x42421380UL))\r
+#define bFM3_MFT1_WFG_NZCL_NWS0                *((volatile unsigned int*)(0x42421384UL))\r
+#define bFM3_MFT1_WFG_NZCL_NWS1                *((volatile unsigned int*)(0x42421388UL))\r
+#define bFM3_MFT1_WFG_NZCL_NWS2                *((volatile unsigned int*)(0x4242138CUL))\r
+#define bFM3_MFT1_WFG_NZCL_SDTI                *((volatile unsigned int*)(0x42421390UL))\r
+\r
+/* Multifunction Timer unit 1 Input Capture Unit registers */\r
+#define bFM3_MFT1_ICU_ICFS10_FSI00             *((volatile unsigned int*)(0x42420C00UL))\r
+#define bFM3_MFT1_ICU_ICFS10_FSI01             *((volatile unsigned int*)(0x42420C04UL))\r
+#define bFM3_MFT1_ICU_ICFS10_FSI02             *((volatile unsigned int*)(0x42420C08UL))\r
+#define bFM3_MFT1_ICU_ICFS10_FSI03             *((volatile unsigned int*)(0x42420C0CUL))\r
+#define bFM3_MFT1_ICU_ICFS10_FSI10             *((volatile unsigned int*)(0x42420C10UL))\r
+#define bFM3_MFT1_ICU_ICFS10_FSI11             *((volatile unsigned int*)(0x42420C14UL))\r
+#define bFM3_MFT1_ICU_ICFS10_FSI12             *((volatile unsigned int*)(0x42420C18UL))\r
+#define bFM3_MFT1_ICU_ICFS10_FSI13             *((volatile unsigned int*)(0x42420C1CUL))\r
+#define bFM3_MFT1_ICU_ICFS32_FSI20             *((volatile unsigned int*)(0x42420C20UL))\r
+#define bFM3_MFT1_ICU_ICFS32_FSI21             *((volatile unsigned int*)(0x42420C24UL))\r
+#define bFM3_MFT1_ICU_ICFS32_FSI22             *((volatile unsigned int*)(0x42420C28UL))\r
+#define bFM3_MFT1_ICU_ICFS32_FSI23             *((volatile unsigned int*)(0x42420C2CUL))\r
+#define bFM3_MFT1_ICU_ICFS32_FSI30             *((volatile unsigned int*)(0x42420C30UL))\r
+#define bFM3_MFT1_ICU_ICFS32_FSI31             *((volatile unsigned int*)(0x42420C34UL))\r
+#define bFM3_MFT1_ICU_ICFS32_FSI32             *((volatile unsigned int*)(0x42420C38UL))\r
+#define bFM3_MFT1_ICU_ICFS32_FSI33             *((volatile unsigned int*)(0x42420C3CUL))\r
+#define bFM3_MFT1_ICU_ICSA10_EG00              *((volatile unsigned int*)(0x42420F00UL))\r
+#define bFM3_MFT1_ICU_ICSA10_EG01              *((volatile unsigned int*)(0x42420F04UL))\r
+#define bFM3_MFT1_ICU_ICSA10_EG10              *((volatile unsigned int*)(0x42420F08UL))\r
+#define bFM3_MFT1_ICU_ICSA10_EG11              *((volatile unsigned int*)(0x42420F0CUL))\r
+#define bFM3_MFT1_ICU_ICSA10_ICE0              *((volatile unsigned int*)(0x42420F10UL))\r
+#define bFM3_MFT1_ICU_ICSA10_ICE1              *((volatile unsigned int*)(0x42420F14UL))\r
+#define bFM3_MFT1_ICU_ICSA10_ICP0              *((volatile unsigned int*)(0x42420F18UL))\r
+#define bFM3_MFT1_ICU_ICSA10_ICP1              *((volatile unsigned int*)(0x42420F1CUL))\r
+#define bFM3_MFT1_ICU_ICSB10_IEI0              *((volatile unsigned int*)(0x42420F20UL))\r
+#define bFM3_MFT1_ICU_ICSB10_IEI1              *((volatile unsigned int*)(0x42420F24UL))\r
+#define bFM3_MFT1_ICU_ICSA32_EG20              *((volatile unsigned int*)(0x42420F80UL))\r
+#define bFM3_MFT1_ICU_ICSA32_EG21              *((volatile unsigned int*)(0x42420F84UL))\r
+#define bFM3_MFT1_ICU_ICSA32_EG30              *((volatile unsigned int*)(0x42420F88UL))\r
+#define bFM3_MFT1_ICU_ICSA32_EG31              *((volatile unsigned int*)(0x42420F8CUL))\r
+#define bFM3_MFT1_ICU_ICSA32_ICE2              *((volatile unsigned int*)(0x42420F90UL))\r
+#define bFM3_MFT1_ICU_ICSA32_ICE3              *((volatile unsigned int*)(0x42420F94UL))\r
+#define bFM3_MFT1_ICU_ICSA32_ICP2              *((volatile unsigned int*)(0x42420F98UL))\r
+#define bFM3_MFT1_ICU_ICSA32_ICP3              *((volatile unsigned int*)(0x42420F9CUL))\r
+#define bFM3_MFT1_ICU_ICSB32_IEI2              *((volatile unsigned int*)(0x42420FA0UL))\r
+#define bFM3_MFT1_ICU_ICSB32_IEI3              *((volatile unsigned int*)(0x42420FA4UL))\r
+\r
+/* Multifunction Timer unit 1 ADC Start Compare Unit registers */\r
+#define bFM3_MFT1_ADCMP_ACSB_BDIS0             *((volatile unsigned int*)(0x42421700UL))\r
+#define bFM3_MFT1_ADCMP_ACSB_BDIS1             *((volatile unsigned int*)(0x42421704UL))\r
+#define bFM3_MFT1_ADCMP_ACSB_BDIS2             *((volatile unsigned int*)(0x42421708UL))\r
+#define bFM3_MFT1_ADCMP_ACSB_BTS0              *((volatile unsigned int*)(0x42421710UL))\r
+#define bFM3_MFT1_ADCMP_ACSB_BTS1              *((volatile unsigned int*)(0x42421714UL))\r
+#define bFM3_MFT1_ADCMP_ACSB_BTS2              *((volatile unsigned int*)(0x42421718UL))\r
+#define bFM3_MFT1_ADCMP_ACSA_CE00              *((volatile unsigned int*)(0x42421780UL))\r
+#define bFM3_MFT1_ADCMP_ACSA_CE01              *((volatile unsigned int*)(0x42421784UL))\r
+#define bFM3_MFT1_ADCMP_ACSA_CE10              *((volatile unsigned int*)(0x42421788UL))\r
+#define bFM3_MFT1_ADCMP_ACSA_CE11              *((volatile unsigned int*)(0x4242178CUL))\r
+#define bFM3_MFT1_ADCMP_ACSA_CE20              *((volatile unsigned int*)(0x42421790UL))\r
+#define bFM3_MFT1_ADCMP_ACSA_CE21              *((volatile unsigned int*)(0x42421794UL))\r
+#define bFM3_MFT1_ADCMP_ACSA_SEL00             *((volatile unsigned int*)(0x424217A0UL))\r
+#define bFM3_MFT1_ADCMP_ACSA_SEL01             *((volatile unsigned int*)(0x424217A4UL))\r
+#define bFM3_MFT1_ADCMP_ACSA_SEL10             *((volatile unsigned int*)(0x424217A8UL))\r
+#define bFM3_MFT1_ADCMP_ACSA_SEL11             *((volatile unsigned int*)(0x424217ACUL))\r
+#define bFM3_MFT1_ADCMP_ACSA_SEL20             *((volatile unsigned int*)(0x424217B0UL))\r
+#define bFM3_MFT1_ADCMP_ACSA_SEL21             *((volatile unsigned int*)(0x424217B4UL))\r
+#define bFM3_MFT1_ADCMP_ATSA_AD0S0             *((volatile unsigned int*)(0x42421800UL))\r
+#define bFM3_MFT1_ADCMP_ATSA_AD0S1             *((volatile unsigned int*)(0x42421804UL))\r
+#define bFM3_MFT1_ADCMP_ATSA_AD1S0             *((volatile unsigned int*)(0x42421808UL))\r
+#define bFM3_MFT1_ADCMP_ATSA_AD1S1             *((volatile unsigned int*)(0x4242180CUL))\r
+#define bFM3_MFT1_ADCMP_ATSA_AD2S0             *((volatile unsigned int*)(0x42421810UL))\r
+#define bFM3_MFT1_ADCMP_ATSA_AD2S1             *((volatile unsigned int*)(0x42421814UL))\r
+#define bFM3_MFT1_ADCMP_ATSA_AD0P0             *((volatile unsigned int*)(0x42421820UL))\r
+#define bFM3_MFT1_ADCMP_ATSA_AD0P1             *((volatile unsigned int*)(0x42421824UL))\r
+#define bFM3_MFT1_ADCMP_ATSA_AD1P0             *((volatile unsigned int*)(0x42421828UL))\r
+#define bFM3_MFT1_ADCMP_ATSA_AD1P1             *((volatile unsigned int*)(0x4242182CUL))\r
+#define bFM3_MFT1_ADCMP_ATSA_AD2P0             *((volatile unsigned int*)(0x42421830UL))\r
+#define bFM3_MFT1_ADCMP_ATSA_AD2P1             *((volatile unsigned int*)(0x42421834UL))\r
+\r
+/* Multifunction Timer PPG registers */\r
+#define bFM3_MFT_PPG_TTCR0_STR0                *((volatile unsigned int*)(0x42480020UL))\r
+#define bFM3_MFT_PPG_TTCR0_MONI0               *((volatile unsigned int*)(0x42480024UL))\r
+#define bFM3_MFT_PPG_TTCR0_CS00                *((volatile unsigned int*)(0x42480028UL))\r
+#define bFM3_MFT_PPG_TTCR0_CS01                *((volatile unsigned int*)(0x4248002CUL))\r
+#define bFM3_MFT_PPG_TTCR0_TRG0O               *((volatile unsigned int*)(0x42480030UL))\r
+#define bFM3_MFT_PPG_TTCR0_TRG2O               *((volatile unsigned int*)(0x42480034UL))\r
+#define bFM3_MFT_PPG_TTCR0_TRG4O               *((volatile unsigned int*)(0x42480038UL))\r
+#define bFM3_MFT_PPG_TTCR0_TRG6O               *((volatile unsigned int*)(0x4248003CUL))\r
+#define bFM3_MFT_PPG_TTCR1_STR1                *((volatile unsigned int*)(0x42480420UL))\r
+#define bFM3_MFT_PPG_TTCR1_MONI1               *((volatile unsigned int*)(0x42480424UL))\r
+#define bFM3_MFT_PPG_TTCR1_CS10                *((volatile unsigned int*)(0x42480428UL))\r
+#define bFM3_MFT_PPG_TTCR1_CS11                *((volatile unsigned int*)(0x4248042CUL))\r
+#define bFM3_MFT_PPG_TTCR1_TRG1O               *((volatile unsigned int*)(0x42480430UL))\r
+#define bFM3_MFT_PPG_TTCR1_TRG3O               *((volatile unsigned int*)(0x42480434UL))\r
+#define bFM3_MFT_PPG_TTCR1_TRG5O               *((volatile unsigned int*)(0x42480438UL))\r
+#define bFM3_MFT_PPG_TTCR1_TRG7O               *((volatile unsigned int*)(0x4248043CUL))\r
+#define bFM3_MFT_PPG_TRG_PEN00                 *((volatile unsigned int*)(0x42482000UL))\r
+#define bFM3_MFT_PPG_TRG_PEN01                 *((volatile unsigned int*)(0x42482004UL))\r
+#define bFM3_MFT_PPG_TRG_PEN02                 *((volatile unsigned int*)(0x42482008UL))\r
+#define bFM3_MFT_PPG_TRG_PEN03                 *((volatile unsigned int*)(0x4248200CUL))\r
+#define bFM3_MFT_PPG_TRG_PEN04                 *((volatile unsigned int*)(0x42482010UL))\r
+#define bFM3_MFT_PPG_TRG_PEN05                 *((volatile unsigned int*)(0x42482014UL))\r
+#define bFM3_MFT_PPG_TRG_PEN06                 *((volatile unsigned int*)(0x42482018UL))\r
+#define bFM3_MFT_PPG_TRG_PEN07                 *((volatile unsigned int*)(0x4248201CUL))\r
+#define bFM3_MFT_PPG_TRG_PEN08                 *((volatile unsigned int*)(0x42482020UL))\r
+#define bFM3_MFT_PPG_TRG_PEN09                 *((volatile unsigned int*)(0x42482024UL))\r
+#define bFM3_MFT_PPG_TRG_PEN10                 *((volatile unsigned int*)(0x42482028UL))\r
+#define bFM3_MFT_PPG_TRG_PEN11                 *((volatile unsigned int*)(0x4248202CUL))\r
+#define bFM3_MFT_PPG_TRG_PEN12                 *((volatile unsigned int*)(0x42482030UL))\r
+#define bFM3_MFT_PPG_TRG_PEN13                 *((volatile unsigned int*)(0x42482034UL))\r
+#define bFM3_MFT_PPG_TRG_PEN14                 *((volatile unsigned int*)(0x42482038UL))\r
+#define bFM3_MFT_PPG_TRG_PEN15                 *((volatile unsigned int*)(0x4248203CUL))\r
+#define bFM3_MFT_PPG_REVC_REV00                *((volatile unsigned int*)(0x42482080UL))\r
+#define bFM3_MFT_PPG_REVC_REV01                *((volatile unsigned int*)(0x42482084UL))\r
+#define bFM3_MFT_PPG_REVC_REV02                *((volatile unsigned int*)(0x42482088UL))\r
+#define bFM3_MFT_PPG_REVC_REV03                *((volatile unsigned int*)(0x4248208CUL))\r
+#define bFM3_MFT_PPG_REVC_REV04                *((volatile unsigned int*)(0x42482090UL))\r
+#define bFM3_MFT_PPG_REVC_REV05                *((volatile unsigned int*)(0x42482094UL))\r
+#define bFM3_MFT_PPG_REVC_REV06                *((volatile unsigned int*)(0x42482098UL))\r
+#define bFM3_MFT_PPG_REVC_REV07                *((volatile unsigned int*)(0x4248209CUL))\r
+#define bFM3_MFT_PPG_REVC_REV08                *((volatile unsigned int*)(0x424820A0UL))\r
+#define bFM3_MFT_PPG_REVC_REV09                *((volatile unsigned int*)(0x424820A4UL))\r
+#define bFM3_MFT_PPG_REVC_REV10                *((volatile unsigned int*)(0x424820A8UL))\r
+#define bFM3_MFT_PPG_REVC_REV11                *((volatile unsigned int*)(0x424820ACUL))\r
+#define bFM3_MFT_PPG_REVC_REV12                *((volatile unsigned int*)(0x424820B0UL))\r
+#define bFM3_MFT_PPG_REVC_REV13                *((volatile unsigned int*)(0x424820B4UL))\r
+#define bFM3_MFT_PPG_REVC_REV14                *((volatile unsigned int*)(0x424820B8UL))\r
+#define bFM3_MFT_PPG_REVC_REV15                *((volatile unsigned int*)(0x424820BCUL))\r
+#define bFM3_MFT_PPG_PPGC1_TTRG                *((volatile unsigned int*)(0x42484000UL))\r
+#define bFM3_MFT_PPG_PPGC1_MD0                 *((volatile unsigned int*)(0x42484004UL))\r
+#define bFM3_MFT_PPG_PPGC1_MD1                 *((volatile unsigned int*)(0x42484008UL))\r
+#define bFM3_MFT_PPG_PPGC1_PCS0                *((volatile unsigned int*)(0x4248400CUL))\r
+#define bFM3_MFT_PPG_PPGC1_PCS1                *((volatile unsigned int*)(0x42484010UL))\r
+#define bFM3_MFT_PPG_PPGC1_INTM                *((volatile unsigned int*)(0x42484014UL))\r
+#define bFM3_MFT_PPG_PPGC1_PUF                 *((volatile unsigned int*)(0x42484018UL))\r
+#define bFM3_MFT_PPG_PPGC1_PIE                 *((volatile unsigned int*)(0x4248401CUL))\r
+#define bFM3_MFT_PPG_PPGC0_TTRG                *((volatile unsigned int*)(0x42484020UL))\r
+#define bFM3_MFT_PPG_PPGC0_MD0                 *((volatile unsigned int*)(0x42484024UL))\r
+#define bFM3_MFT_PPG_PPGC0_MD1                 *((volatile unsigned int*)(0x42484028UL))\r
+#define bFM3_MFT_PPG_PPGC0_PCS0                *((volatile unsigned int*)(0x4248402CUL))\r
+#define bFM3_MFT_PPG_PPGC0_PCS1                *((volatile unsigned int*)(0x42484030UL))\r
+#define bFM3_MFT_PPG_PPGC0_INTM                *((volatile unsigned int*)(0x42484034UL))\r
+#define bFM3_MFT_PPG_PPGC0_PUF                 *((volatile unsigned int*)(0x42484038UL))\r
+#define bFM3_MFT_PPG_PPGC0_PIE                 *((volatile unsigned int*)(0x4248403CUL))\r
+#define bFM3_MFT_PPG_PPGC3_TTRG                *((volatile unsigned int*)(0x42484080UL))\r
+#define bFM3_MFT_PPG_PPGC3_MD0                 *((volatile unsigned int*)(0x42484084UL))\r
+#define bFM3_MFT_PPG_PPGC3_MD1                 *((volatile unsigned int*)(0x42484088UL))\r
+#define bFM3_MFT_PPG_PPGC3_PCS0                *((volatile unsigned int*)(0x4248408CUL))\r
+#define bFM3_MFT_PPG_PPGC3_PCS1                *((volatile unsigned int*)(0x42484090UL))\r
+#define bFM3_MFT_PPG_PPGC3_INTM                *((volatile unsigned int*)(0x42484094UL))\r
+#define bFM3_MFT_PPG_PPGC3_PUF                 *((volatile unsigned int*)(0x42484098UL))\r
+#define bFM3_MFT_PPG_PPGC3_PIE                 *((volatile unsigned int*)(0x4248409CUL))\r
+#define bFM3_MFT_PPG_PPGC2_TTRG                *((volatile unsigned int*)(0x424840A0UL))\r
+#define bFM3_MFT_PPG_PPGC2_MD0                 *((volatile unsigned int*)(0x424840A4UL))\r
+#define bFM3_MFT_PPG_PPGC2_MD1                 *((volatile unsigned int*)(0x424840A8UL))\r
+#define bFM3_MFT_PPG_PPGC2_PCS0                *((volatile unsigned int*)(0x424840ACUL))\r
+#define bFM3_MFT_PPG_PPGC2_PCS1                *((volatile unsigned int*)(0x424840B0UL))\r
+#define bFM3_MFT_PPG_PPGC2_INTM                *((volatile unsigned int*)(0x424840B4UL))\r
+#define bFM3_MFT_PPG_PPGC2_PUF                 *((volatile unsigned int*)(0x424840B8UL))\r
+#define bFM3_MFT_PPG_PPGC2_PIE                 *((volatile unsigned int*)(0x424840BCUL))\r
+#define bFM3_MFT_PPG_GATEC0_EDGE0              *((volatile unsigned int*)(0x42484300UL))\r
+#define bFM3_MFT_PPG_GATEC0_STRG0              *((volatile unsigned int*)(0x42484304UL))\r
+#define bFM3_MFT_PPG_GATEC0_EDGE2              *((volatile unsigned int*)(0x42484310UL))\r
+#define bFM3_MFT_PPG_GATEC0_STRG2              *((volatile unsigned int*)(0x42484314UL))\r
+#define bFM3_MFT_PPG_PPGC5_TTRG                *((volatile unsigned int*)(0x42484800UL))\r
+#define bFM3_MFT_PPG_PPGC5_MD0                 *((volatile unsigned int*)(0x42484804UL))\r
+#define bFM3_MFT_PPG_PPGC5_MD1                 *((volatile unsigned int*)(0x42484808UL))\r
+#define bFM3_MFT_PPG_PPGC5_PCS0                *((volatile unsigned int*)(0x4248480CUL))\r
+#define bFM3_MFT_PPG_PPGC5_PCS1                *((volatile unsigned int*)(0x42484810UL))\r
+#define bFM3_MFT_PPG_PPGC5_INTM                *((volatile unsigned int*)(0x42484814UL))\r
+#define bFM3_MFT_PPG_PPGC5_PUF                 *((volatile unsigned int*)(0x42484818UL))\r
+#define bFM3_MFT_PPG_PPGC5_PIE                 *((volatile unsigned int*)(0x4248481CUL))\r
+#define bFM3_MFT_PPG_PPGC4_TTRG                *((volatile unsigned int*)(0x42484820UL))\r
+#define bFM3_MFT_PPG_PPGC4_MD0                 *((volatile unsigned int*)(0x42484824UL))\r
+#define bFM3_MFT_PPG_PPGC4_MD1                 *((volatile unsigned int*)(0x42484828UL))\r
+#define bFM3_MFT_PPG_PPGC4_PCS0                *((volatile unsigned int*)(0x4248482CUL))\r
+#define bFM3_MFT_PPG_PPGC4_PCS1                *((volatile unsigned int*)(0x42484830UL))\r
+#define bFM3_MFT_PPG_PPGC4_INTM                *((volatile unsigned int*)(0x42484834UL))\r
+#define bFM3_MFT_PPG_PPGC4_PUF                 *((volatile unsigned int*)(0x42484838UL))\r
+#define bFM3_MFT_PPG_PPGC4_PIE                 *((volatile unsigned int*)(0x4248483CUL))\r
+#define bFM3_MFT_PPG_PPGC7_TTRG                *((volatile unsigned int*)(0x42484880UL))\r
+#define bFM3_MFT_PPG_PPGC7_MD0                 *((volatile unsigned int*)(0x42484884UL))\r
+#define bFM3_MFT_PPG_PPGC7_MD1                 *((volatile unsigned int*)(0x42484888UL))\r
+#define bFM3_MFT_PPG_PPGC7_PCS0                *((volatile unsigned int*)(0x4248488CUL))\r
+#define bFM3_MFT_PPG_PPGC7_PCS1                *((volatile unsigned int*)(0x42484890UL))\r
+#define bFM3_MFT_PPG_PPGC7_INTM                *((volatile unsigned int*)(0x42484894UL))\r
+#define bFM3_MFT_PPG_PPGC7_PUF                 *((volatile unsigned int*)(0x42484898UL))\r
+#define bFM3_MFT_PPG_PPGC7_PIE                 *((volatile unsigned int*)(0x4248489CUL))\r
+#define bFM3_MFT_PPG_PPGC6_TTRG                *((volatile unsigned int*)(0x424848A0UL))\r
+#define bFM3_MFT_PPG_PPGC6_MD0                 *((volatile unsigned int*)(0x424848A4UL))\r
+#define bFM3_MFT_PPG_PPGC6_MD1                 *((volatile unsigned int*)(0x424848A8UL))\r
+#define bFM3_MFT_PPG_PPGC6_PCS0                *((volatile unsigned int*)(0x424848ACUL))\r
+#define bFM3_MFT_PPG_PPGC6_PCS1                *((volatile unsigned int*)(0x424848B0UL))\r
+#define bFM3_MFT_PPG_PPGC6_INTM                *((volatile unsigned int*)(0x424848B4UL))\r
+#define bFM3_MFT_PPG_PPGC6_PUF                 *((volatile unsigned int*)(0x424848B8UL))\r
+#define bFM3_MFT_PPG_PPGC6_PIE                 *((volatile unsigned int*)(0x424848BCUL))\r
+#define bFM3_MFT_PPG_GATEC4_EDGE4              *((volatile unsigned int*)(0x42484B00UL))\r
+#define bFM3_MFT_PPG_GATEC4_STRG4              *((volatile unsigned int*)(0x42484B04UL))\r
+#define bFM3_MFT_PPG_GATEC4_EDGE6              *((volatile unsigned int*)(0x42484B10UL))\r
+#define bFM3_MFT_PPG_GATEC4_STRG6              *((volatile unsigned int*)(0x42484B14UL))\r
+#define bFM3_MFT_PPG_PPGC9_TTRG                *((volatile unsigned int*)(0x42485000UL))\r
+#define bFM3_MFT_PPG_PPGC9_MD0                 *((volatile unsigned int*)(0x42485004UL))\r
+#define bFM3_MFT_PPG_PPGC9_MD1                 *((volatile unsigned int*)(0x42485008UL))\r
+#define bFM3_MFT_PPG_PPGC9_PCS0                *((volatile unsigned int*)(0x4248500CUL))\r
+#define bFM3_MFT_PPG_PPGC9_PCS1                *((volatile unsigned int*)(0x42485010UL))\r
+#define bFM3_MFT_PPG_PPGC9_INTM                *((volatile unsigned int*)(0x42485014UL))\r
+#define bFM3_MFT_PPG_PPGC9_PUF                 *((volatile unsigned int*)(0x42485018UL))\r
+#define bFM3_MFT_PPG_PPGC9_PIE                 *((volatile unsigned int*)(0x4248501CUL))\r
+#define bFM3_MFT_PPG_PPGC8_TTRG                *((volatile unsigned int*)(0x42485020UL))\r
+#define bFM3_MFT_PPG_PPGC8_MD0                 *((volatile unsigned int*)(0x42485024UL))\r
+#define bFM3_MFT_PPG_PPGC8_MD1                 *((volatile unsigned int*)(0x42485028UL))\r
+#define bFM3_MFT_PPG_PPGC8_PCS0                *((volatile unsigned int*)(0x4248502CUL))\r
+#define bFM3_MFT_PPG_PPGC8_PCS1                *((volatile unsigned int*)(0x42485030UL))\r
+#define bFM3_MFT_PPG_PPGC8_INTM                *((volatile unsigned int*)(0x42485034UL))\r
+#define bFM3_MFT_PPG_PPGC8_PUF                 *((volatile unsigned int*)(0x42485038UL))\r
+#define bFM3_MFT_PPG_PPGC8_PIE                 *((volatile unsigned int*)(0x4248503CUL))\r
+#define bFM3_MFT_PPG_PPGC11_TTRG               *((volatile unsigned int*)(0x42485080UL))\r
+#define bFM3_MFT_PPG_PPGC11_MD0                *((volatile unsigned int*)(0x42485084UL))\r
+#define bFM3_MFT_PPG_PPGC11_MD1                *((volatile unsigned int*)(0x42485088UL))\r
+#define bFM3_MFT_PPG_PPGC11_PCS0               *((volatile unsigned int*)(0x4248508CUL))\r
+#define bFM3_MFT_PPG_PPGC11_PCS1               *((volatile unsigned int*)(0x42485090UL))\r
+#define bFM3_MFT_PPG_PPGC11_INTM               *((volatile unsigned int*)(0x42485094UL))\r
+#define bFM3_MFT_PPG_PPGC11_PUF                *((volatile unsigned int*)(0x42485098UL))\r
+#define bFM3_MFT_PPG_PPGC11_PIE                *((volatile unsigned int*)(0x4248509CUL))\r
+#define bFM3_MFT_PPG_PPGC10_TTRG               *((volatile unsigned int*)(0x424850A0UL))\r
+#define bFM3_MFT_PPG_PPGC10_MD0                *((volatile unsigned int*)(0x424850A4UL))\r
+#define bFM3_MFT_PPG_PPGC10_MD1                *((volatile unsigned int*)(0x424850A8UL))\r
+#define bFM3_MFT_PPG_PPGC10_PCS0               *((volatile unsigned int*)(0x424850ACUL))\r
+#define bFM3_MFT_PPG_PPGC10_PCS1               *((volatile unsigned int*)(0x424850B0UL))\r
+#define bFM3_MFT_PPG_PPGC10_INTM               *((volatile unsigned int*)(0x424850B4UL))\r
+#define bFM3_MFT_PPG_PPGC10_PUF                *((volatile unsigned int*)(0x424850B8UL))\r
+#define bFM3_MFT_PPG_PPGC10_PIE                *((volatile unsigned int*)(0x424850BCUL))\r
+#define bFM3_MFT_PPG_GATEC8_EDGE8              *((volatile unsigned int*)(0x42485300UL))\r
+#define bFM3_MFT_PPG_GATEC8_STRG8              *((volatile unsigned int*)(0x42485304UL))\r
+#define bFM3_MFT_PPG_GATEC8_EDGE10             *((volatile unsigned int*)(0x42485310UL))\r
+#define bFM3_MFT_PPG_GATEC8_STRG10             *((volatile unsigned int*)(0x42485314UL))\r
+#define bFM3_MFT_PPG_PPGC13_TTRG               *((volatile unsigned int*)(0x42485800UL))\r
+#define bFM3_MFT_PPG_PPGC13_MD0                *((volatile unsigned int*)(0x42485804UL))\r
+#define bFM3_MFT_PPG_PPGC13_MD1                *((volatile unsigned int*)(0x42485808UL))\r
+#define bFM3_MFT_PPG_PPGC13_PCS0               *((volatile unsigned int*)(0x4248580CUL))\r
+#define bFM3_MFT_PPG_PPGC13_PCS1               *((volatile unsigned int*)(0x42485810UL))\r
+#define bFM3_MFT_PPG_PPGC13_INTM               *((volatile unsigned int*)(0x42485814UL))\r
+#define bFM3_MFT_PPG_PPGC13_PUF                *((volatile unsigned int*)(0x42485818UL))\r
+#define bFM3_MFT_PPG_PPGC13_PIE                *((volatile unsigned int*)(0x4248581CUL))\r
+#define bFM3_MFT_PPG_PPGC12_TTRG               *((volatile unsigned int*)(0x42485820UL))\r
+#define bFM3_MFT_PPG_PPGC12_MD0                *((volatile unsigned int*)(0x42485824UL))\r
+#define bFM3_MFT_PPG_PPGC12_MD1                *((volatile unsigned int*)(0x42485828UL))\r
+#define bFM3_MFT_PPG_PPGC12_PCS0               *((volatile unsigned int*)(0x4248582CUL))\r
+#define bFM3_MFT_PPG_PPGC12_PCS1               *((volatile unsigned int*)(0x42485830UL))\r
+#define bFM3_MFT_PPG_PPGC12_INTM               *((volatile unsigned int*)(0x42485834UL))\r
+#define bFM3_MFT_PPG_PPGC12_PUF                *((volatile unsigned int*)(0x42485838UL))\r
+#define bFM3_MFT_PPG_PPGC12_PIE                *((volatile unsigned int*)(0x4248583CUL))\r
+#define bFM3_MFT_PPG_PPGC15_TTRG               *((volatile unsigned int*)(0x42485880UL))\r
+#define bFM3_MFT_PPG_PPGC15_MD0                *((volatile unsigned int*)(0x42485884UL))\r
+#define bFM3_MFT_PPG_PPGC15_MD1                *((volatile unsigned int*)(0x42485888UL))\r
+#define bFM3_MFT_PPG_PPGC15_PCS0               *((volatile unsigned int*)(0x4248588CUL))\r
+#define bFM3_MFT_PPG_PPGC15_PCS1               *((volatile unsigned int*)(0x42485890UL))\r
+#define bFM3_MFT_PPG_PPGC15_INTM               *((volatile unsigned int*)(0x42485894UL))\r
+#define bFM3_MFT_PPG_PPGC15_PUF                *((volatile unsigned int*)(0x42485898UL))\r
+#define bFM3_MFT_PPG_PPGC15_PIE                *((volatile unsigned int*)(0x4248589CUL))\r
+#define bFM3_MFT_PPG_PPGC14_TTRG               *((volatile unsigned int*)(0x424858A0UL))\r
+#define bFM3_MFT_PPG_PPGC14_MD0                *((volatile unsigned int*)(0x424858A4UL))\r
+#define bFM3_MFT_PPG_PPGC14_MD1                *((volatile unsigned int*)(0x424858A8UL))\r
+#define bFM3_MFT_PPG_PPGC14_PCS0               *((volatile unsigned int*)(0x424858ACUL))\r
+#define bFM3_MFT_PPG_PPGC14_PCS1               *((volatile unsigned int*)(0x424858B0UL))\r
+#define bFM3_MFT_PPG_PPGC14_INTM               *((volatile unsigned int*)(0x424858B4UL))\r
+#define bFM3_MFT_PPG_PPGC14_PUF                *((volatile unsigned int*)(0x424858B8UL))\r
+#define bFM3_MFT_PPG_PPGC14_PIE                *((volatile unsigned int*)(0x424858BCUL))\r
+#define bFM3_MFT_PPG_GATEC12_EDGE12            *((volatile unsigned int*)(0x42485B00UL))\r
+#define bFM3_MFT_PPG_GATEC12_STRG12            *((volatile unsigned int*)(0x42485B04UL))\r
+#define bFM3_MFT_PPG_GATEC12_EDGE14            *((volatile unsigned int*)(0x42485B10UL))\r
+#define bFM3_MFT_PPG_GATEC12_STRG14            *((volatile unsigned int*)(0x42485B14UL))\r
+\r
+/* Base Timer 0 PPG registers */\r
+#define bFM3_BT0_PPG_TMCR_STRG                 *((volatile unsigned int*)(0x424A0180UL))\r
+#define bFM3_BT0_PPG_TMCR_CTEN                 *((volatile unsigned int*)(0x424A0184UL))\r
+#define bFM3_BT0_PPG_TMCR_MDSE                 *((volatile unsigned int*)(0x424A0188UL))\r
+#define bFM3_BT0_PPG_TMCR_OSEL                 *((volatile unsigned int*)(0x424A018CUL))\r
+#define bFM3_BT0_PPG_TMCR_FMD0                 *((volatile unsigned int*)(0x424A0190UL))\r
+#define bFM3_BT0_PPG_TMCR_FMD1                 *((volatile unsigned int*)(0x424A0194UL))\r
+#define bFM3_BT0_PPG_TMCR_FMD2                 *((volatile unsigned int*)(0x424A0198UL))\r
+#define bFM3_BT0_PPG_TMCR_EGS0                 *((volatile unsigned int*)(0x424A01A0UL))\r
+#define bFM3_BT0_PPG_TMCR_EGS1                 *((volatile unsigned int*)(0x424A01A4UL))\r
+#define bFM3_BT0_PPG_TMCR_PMSK                 *((volatile unsigned int*)(0x424A01A8UL))\r
+#define bFM3_BT0_PPG_TMCR_RTGEN                *((volatile unsigned int*)(0x424A01ACUL))\r
+#define bFM3_BT0_PPG_TMCR_CKS0                 *((volatile unsigned int*)(0x424A01B0UL))\r
+#define bFM3_BT0_PPG_TMCR_CKS1                 *((volatile unsigned int*)(0x424A01B4UL))\r
+#define bFM3_BT0_PPG_TMCR_CKS2                 *((volatile unsigned int*)(0x424A01B8UL))\r
+#define bFM3_BT0_PPG_STC_UDIR                  *((volatile unsigned int*)(0x424A0200UL))\r
+#define bFM3_BT0_PPG_STC_TGIR                  *((volatile unsigned int*)(0x424A0208UL))\r
+#define bFM3_BT0_PPG_STC_UDIE                  *((volatile unsigned int*)(0x424A0210UL))\r
+#define bFM3_BT0_PPG_STC_TGIE                  *((volatile unsigned int*)(0x424A0218UL))\r
+#define bFM3_BT0_PPG_TMCR2_CKS3                *((volatile unsigned int*)(0x424A0220UL))\r
+\r
+/* Base Timer 0 PWM registers */\r
+#define bFM3_BT0_PWM_TMCR_STRG                 *((volatile unsigned int*)(0x424A0180UL))\r
+#define bFM3_BT0_PWM_TMCR_CTEN                 *((volatile unsigned int*)(0x424A0184UL))\r
+#define bFM3_BT0_PWM_TMCR_MDSE                 *((volatile unsigned int*)(0x424A0188UL))\r
+#define bFM3_BT0_PWM_TMCR_OSEL                 *((volatile unsigned int*)(0x424A018CUL))\r
+#define bFM3_BT0_PWM_TMCR_FMD0                 *((volatile unsigned int*)(0x424A0190UL))\r
+#define bFM3_BT0_PWM_TMCR_FMD1                 *((volatile unsigned int*)(0x424A0194UL))\r
+#define bFM3_BT0_PWM_TMCR_FMD2                 *((volatile unsigned int*)(0x424A0198UL))\r
+#define bFM3_BT0_PWM_TMCR_EGS0                 *((volatile unsigned int*)(0x424A01A0UL))\r
+#define bFM3_BT0_PWM_TMCR_EGS1                 *((volatile unsigned int*)(0x424A01A4UL))\r
+#define bFM3_BT0_PWM_TMCR_PMSK                 *((volatile unsigned int*)(0x424A01A8UL))\r
+#define bFM3_BT0_PWM_TMCR_RTGEN                *((volatile unsigned int*)(0x424A01ACUL))\r
+#define bFM3_BT0_PWM_TMCR_CKS0                 *((volatile unsigned int*)(0x424A01B0UL))\r
+#define bFM3_BT0_PWM_TMCR_CKS1                 *((volatile unsigned int*)(0x424A01B4UL))\r
+#define bFM3_BT0_PWM_TMCR_CKS2                 *((volatile unsigned int*)(0x424A01B8UL))\r
+#define bFM3_BT0_PWM_STC_UDIR                  *((volatile unsigned int*)(0x424A0200UL))\r
+#define bFM3_BT0_PWM_STC_DTIR                  *((volatile unsigned int*)(0x424A0204UL))\r
+#define bFM3_BT0_PWM_STC_TGIR                  *((volatile unsigned int*)(0x424A0208UL))\r
+#define bFM3_BT0_PWM_STC_UDIE                  *((volatile unsigned int*)(0x424A0210UL))\r
+#define bFM3_BT0_PWM_STC_DTIE                  *((volatile unsigned int*)(0x424A0214UL))\r
+#define bFM3_BT0_PWM_STC_TGIE                  *((volatile unsigned int*)(0x424A0218UL))\r
+#define bFM3_BT0_PWM_TMCR2_CKS3                *((volatile unsigned int*)(0x424A0220UL))\r
+\r
+/* Base Timer 0 RT registers */\r
+#define bFM3_BT0_RT_TMCR_STRG                  *((volatile unsigned int*)(0x424A0180UL))\r
+#define bFM3_BT0_RT_TMCR_CTEN                  *((volatile unsigned int*)(0x424A0184UL))\r
+#define bFM3_BT0_RT_TMCR_MDSE                  *((volatile unsigned int*)(0x424A0188UL))\r
+#define bFM3_BT0_RT_TMCR_OSEL                  *((volatile unsigned int*)(0x424A018CUL))\r
+#define bFM3_BT0_RT_TMCR_FMD0                  *((volatile unsigned int*)(0x424A0190UL))\r
+#define bFM3_BT0_RT_TMCR_FMD1                  *((volatile unsigned int*)(0x424A0194UL))\r
+#define bFM3_BT0_RT_TMCR_FMD2                  *((volatile unsigned int*)(0x424A0198UL))\r
+#define bFM3_BT0_RT_TMCR_T32                   *((volatile unsigned int*)(0x424A019CUL))\r
+#define bFM3_BT0_RT_TMCR_EGS0                  *((volatile unsigned int*)(0x424A01A0UL))\r
+#define bFM3_BT0_RT_TMCR_EGS1                  *((volatile unsigned int*)(0x424A01A4UL))\r
+#define bFM3_BT0_RT_TMCR_CKS0                  *((volatile unsigned int*)(0x424A01B0UL))\r
+#define bFM3_BT0_RT_TMCR_CKS1                  *((volatile unsigned int*)(0x424A01B4UL))\r
+#define bFM3_BT0_RT_TMCR_CKS2                  *((volatile unsigned int*)(0x424A01B8UL))\r
+#define bFM3_BT0_RT_STC_UDIR                   *((volatile unsigned int*)(0x424A0200UL))\r
+#define bFM3_BT0_RT_STC_TGIR                   *((volatile unsigned int*)(0x424A0208UL))\r
+#define bFM3_BT0_RT_STC_UDIE                   *((volatile unsigned int*)(0x424A0210UL))\r
+#define bFM3_BT0_RT_STC_TGIE                   *((volatile unsigned int*)(0x424A0218UL))\r
+#define bFM3_BT0_RT_TMCR2_CKS3                 *((volatile unsigned int*)(0x424A0220UL))\r
+\r
+/* Base Timer 0 PWC registers */\r
+#define bFM3_BT0_PWC_TMCR_CTEN                 *((volatile unsigned int*)(0x424A0184UL))\r
+#define bFM3_BT0_PWC_TMCR_MDSE                 *((volatile unsigned int*)(0x424A0188UL))\r
+#define bFM3_BT0_PWC_TMCR_FMD0                 *((volatile unsigned int*)(0x424A0190UL))\r
+#define bFM3_BT0_PWC_TMCR_FMD1                 *((volatile unsigned int*)(0x424A0194UL))\r
+#define bFM3_BT0_PWC_TMCR_FMD2                 *((volatile unsigned int*)(0x424A0198UL))\r
+#define bFM3_BT0_PWC_TMCR_T32                  *((volatile unsigned int*)(0x424A019CUL))\r
+#define bFM3_BT0_PWC_TMCR_EGS0                 *((volatile unsigned int*)(0x424A01A0UL))\r
+#define bFM3_BT0_PWC_TMCR_EGS1                 *((volatile unsigned int*)(0x424A01A4UL))\r
+#define bFM3_BT0_PWC_TMCR_EGS2                 *((volatile unsigned int*)(0x424A01A8UL))\r
+#define bFM3_BT0_PWC_TMCR_CKS0                 *((volatile unsigned int*)(0x424A01B0UL))\r
+#define bFM3_BT0_PWC_TMCR_CKS1                 *((volatile unsigned int*)(0x424A01B4UL))\r
+#define bFM3_BT0_PWC_TMCR_CKS2                 *((volatile unsigned int*)(0x424A01B8UL))\r
+#define bFM3_BT0_PWC_STC_OVIR                  *((volatile unsigned int*)(0x424A0200UL))\r
+#define bFM3_BT0_PWC_STC_EDIR                  *((volatile unsigned int*)(0x424A0208UL))\r
+#define bFM3_BT0_PWC_STC_OVIE                  *((volatile unsigned int*)(0x424A0210UL))\r
+#define bFM3_BT0_PWC_STC_EDIE                  *((volatile unsigned int*)(0x424A0218UL))\r
+#define bFM3_BT0_PWC_STC_ERR                   *((volatile unsigned int*)(0x424A021CUL))\r
+#define bFM3_BT0_PWC_TMCR2_CKS3                *((volatile unsigned int*)(0x424A0220UL))\r
+\r
+/* Base Timer 1 PPG registers */\r
+#define bFM3_BT1_PPG_TMCR_STRG                 *((volatile unsigned int*)(0x424A0980UL))\r
+#define bFM3_BT1_PPG_TMCR_CTEN                 *((volatile unsigned int*)(0x424A0984UL))\r
+#define bFM3_BT1_PPG_TMCR_MDSE                 *((volatile unsigned int*)(0x424A0988UL))\r
+#define bFM3_BT1_PPG_TMCR_OSEL                 *((volatile unsigned int*)(0x424A098CUL))\r
+#define bFM3_BT1_PPG_TMCR_FMD0                 *((volatile unsigned int*)(0x424A0990UL))\r
+#define bFM3_BT1_PPG_TMCR_FMD1                 *((volatile unsigned int*)(0x424A0994UL))\r
+#define bFM3_BT1_PPG_TMCR_FMD2                 *((volatile unsigned int*)(0x424A0998UL))\r
+#define bFM3_BT1_PPG_TMCR_EGS0                 *((volatile unsigned int*)(0x424A09A0UL))\r
+#define bFM3_BT1_PPG_TMCR_EGS1                 *((volatile unsigned int*)(0x424A09A4UL))\r
+#define bFM3_BT1_PPG_TMCR_PMSK                 *((volatile unsigned int*)(0x424A09A8UL))\r
+#define bFM3_BT1_PPG_TMCR_RTGEN                *((volatile unsigned int*)(0x424A09ACUL))\r
+#define bFM3_BT1_PPG_TMCR_CKS0                 *((volatile unsigned int*)(0x424A09B0UL))\r
+#define bFM3_BT1_PPG_TMCR_CKS1                 *((volatile unsigned int*)(0x424A09B4UL))\r
+#define bFM3_BT1_PPG_TMCR_CKS2                 *((volatile unsigned int*)(0x424A09B8UL))\r
+#define bFM3_BT1_PPG_STC_UDIR                  *((volatile unsigned int*)(0x424A0A00UL))\r
+#define bFM3_BT1_PPG_STC_TGIR                  *((volatile unsigned int*)(0x424A0A08UL))\r
+#define bFM3_BT1_PPG_STC_UDIE                  *((volatile unsigned int*)(0x424A0A10UL))\r
+#define bFM3_BT1_PPG_STC_TGIE                  *((volatile unsigned int*)(0x424A0A18UL))\r
+#define bFM3_BT1_PPG_TMCR2_CKS3                *((volatile unsigned int*)(0x424A0A20UL))\r
+\r
+/* Base Timer 1 PWM registers */\r
+#define bFM3_BT1_PWM_TMCR_STRG                 *((volatile unsigned int*)(0x424A0980UL))\r
+#define bFM3_BT1_PWM_TMCR_CTEN                 *((volatile unsigned int*)(0x424A0984UL))\r
+#define bFM3_BT1_PWM_TMCR_MDSE                 *((volatile unsigned int*)(0x424A0988UL))\r
+#define bFM3_BT1_PWM_TMCR_OSEL                 *((volatile unsigned int*)(0x424A098CUL))\r
+#define bFM3_BT1_PWM_TMCR_FMD0                 *((volatile unsigned int*)(0x424A0990UL))\r
+#define bFM3_BT1_PWM_TMCR_FMD1                 *((volatile unsigned int*)(0x424A0994UL))\r
+#define bFM3_BT1_PWM_TMCR_FMD2                 *((volatile unsigned int*)(0x424A0998UL))\r
+#define bFM3_BT1_PWM_TMCR_EGS0                 *((volatile unsigned int*)(0x424A09A0UL))\r
+#define bFM3_BT1_PWM_TMCR_EGS1                 *((volatile unsigned int*)(0x424A09A4UL))\r
+#define bFM3_BT1_PWM_TMCR_PMSK                 *((volatile unsigned int*)(0x424A09A8UL))\r
+#define bFM3_BT1_PWM_TMCR_RTGEN                *((volatile unsigned int*)(0x424A09ACUL))\r
+#define bFM3_BT1_PWM_TMCR_CKS0                 *((volatile unsigned int*)(0x424A09B0UL))\r
+#define bFM3_BT1_PWM_TMCR_CKS1                 *((volatile unsigned int*)(0x424A09B4UL))\r
+#define bFM3_BT1_PWM_TMCR_CKS2                 *((volatile unsigned int*)(0x424A09B8UL))\r
+#define bFM3_BT1_PWM_STC_UDIR                  *((volatile unsigned int*)(0x424A0A00UL))\r
+#define bFM3_BT1_PWM_STC_DTIR                  *((volatile unsigned int*)(0x424A0A04UL))\r
+#define bFM3_BT1_PWM_STC_TGIR                  *((volatile unsigned int*)(0x424A0A08UL))\r
+#define bFM3_BT1_PWM_STC_UDIE                  *((volatile unsigned int*)(0x424A0A10UL))\r
+#define bFM3_BT1_PWM_STC_DTIE                  *((volatile unsigned int*)(0x424A0A14UL))\r
+#define bFM3_BT1_PWM_STC_TGIE                  *((volatile unsigned int*)(0x424A0A18UL))\r
+#define bFM3_BT1_PWM_TMCR2_CKS3                *((volatile unsigned int*)(0x424A0A20UL))\r
+\r
+/* Base Timer 1 RT registers */\r
+#define bFM3_BT1_RT_TMCR_STRG                  *((volatile unsigned int*)(0x424A0980UL))\r
+#define bFM3_BT1_RT_TMCR_CTEN                  *((volatile unsigned int*)(0x424A0984UL))\r
+#define bFM3_BT1_RT_TMCR_MDSE                  *((volatile unsigned int*)(0x424A0988UL))\r
+#define bFM3_BT1_RT_TMCR_OSEL                  *((volatile unsigned int*)(0x424A098CUL))\r
+#define bFM3_BT1_RT_TMCR_FMD0                  *((volatile unsigned int*)(0x424A0990UL))\r
+#define bFM3_BT1_RT_TMCR_FMD1                  *((volatile unsigned int*)(0x424A0994UL))\r
+#define bFM3_BT1_RT_TMCR_FMD2                  *((volatile unsigned int*)(0x424A0998UL))\r
+#define bFM3_BT1_RT_TMCR_T32                   *((volatile unsigned int*)(0x424A099CUL))\r
+#define bFM3_BT1_RT_TMCR_EGS0                  *((volatile unsigned int*)(0x424A09A0UL))\r
+#define bFM3_BT1_RT_TMCR_EGS1                  *((volatile unsigned int*)(0x424A09A4UL))\r
+#define bFM3_BT1_RT_TMCR_CKS0                  *((volatile unsigned int*)(0x424A09B0UL))\r
+#define bFM3_BT1_RT_TMCR_CKS1                  *((volatile unsigned int*)(0x424A09B4UL))\r
+#define bFM3_BT1_RT_TMCR_CKS2                  *((volatile unsigned int*)(0x424A09B8UL))\r
+#define bFM3_BT1_RT_STC_UDIR                   *((volatile unsigned int*)(0x424A0A00UL))\r
+#define bFM3_BT1_RT_STC_TGIR                   *((volatile unsigned int*)(0x424A0A08UL))\r
+#define bFM3_BT1_RT_STC_UDIE                   *((volatile unsigned int*)(0x424A0A10UL))\r
+#define bFM3_BT1_RT_STC_TGIE                   *((volatile unsigned int*)(0x424A0A18UL))\r
+#define bFM3_BT1_RT_TMCR2_CKS3                 *((volatile unsigned int*)(0x424A0A20UL))\r
+\r
+/* Base Timer 1 PWC registers */\r
+#define bFM3_BT1_PWC_TMCR_CTEN                 *((volatile unsigned int*)(0x424A0984UL))\r
+#define bFM3_BT1_PWC_TMCR_MDSE                 *((volatile unsigned int*)(0x424A0988UL))\r
+#define bFM3_BT1_PWC_TMCR_FMD0                 *((volatile unsigned int*)(0x424A0990UL))\r
+#define bFM3_BT1_PWC_TMCR_FMD1                 *((volatile unsigned int*)(0x424A0994UL))\r
+#define bFM3_BT1_PWC_TMCR_FMD2                 *((volatile unsigned int*)(0x424A0998UL))\r
+#define bFM3_BT1_PWC_TMCR_T32                  *((volatile unsigned int*)(0x424A099CUL))\r
+#define bFM3_BT1_PWC_TMCR_EGS0                 *((volatile unsigned int*)(0x424A09A0UL))\r
+#define bFM3_BT1_PWC_TMCR_EGS1                 *((volatile unsigned int*)(0x424A09A4UL))\r
+#define bFM3_BT1_PWC_TMCR_EGS2                 *((volatile unsigned int*)(0x424A09A8UL))\r
+#define bFM3_BT1_PWC_TMCR_CKS0                 *((volatile unsigned int*)(0x424A09B0UL))\r
+#define bFM3_BT1_PWC_TMCR_CKS1                 *((volatile unsigned int*)(0x424A09B4UL))\r
+#define bFM3_BT1_PWC_TMCR_CKS2                 *((volatile unsigned int*)(0x424A09B8UL))\r
+#define bFM3_BT1_PWC_STC_OVIR                  *((volatile unsigned int*)(0x424A0A00UL))\r
+#define bFM3_BT1_PWC_STC_EDIR                  *((volatile unsigned int*)(0x424A0A08UL))\r
+#define bFM3_BT1_PWC_STC_OVIE                  *((volatile unsigned int*)(0x424A0A10UL))\r
+#define bFM3_BT1_PWC_STC_EDIE                  *((volatile unsigned int*)(0x424A0A18UL))\r
+#define bFM3_BT1_PWC_STC_ERR                   *((volatile unsigned int*)(0x424A0A1CUL))\r
+#define bFM3_BT1_PWC_TMCR2_CKS3                *((volatile unsigned int*)(0x424A0A20UL))\r
+\r
+/* Base Timer 2 PPG registers */\r
+#define bFM3_BT2_PPG_TMCR_STRG                 *((volatile unsigned int*)(0x424A1180UL))\r
+#define bFM3_BT2_PPG_TMCR_CTEN                 *((volatile unsigned int*)(0x424A1184UL))\r
+#define bFM3_BT2_PPG_TMCR_MDSE                 *((volatile unsigned int*)(0x424A1188UL))\r
+#define bFM3_BT2_PPG_TMCR_OSEL                 *((volatile unsigned int*)(0x424A118CUL))\r
+#define bFM3_BT2_PPG_TMCR_FMD0                 *((volatile unsigned int*)(0x424A1190UL))\r
+#define bFM3_BT2_PPG_TMCR_FMD1                 *((volatile unsigned int*)(0x424A1194UL))\r
+#define bFM3_BT2_PPG_TMCR_FMD2                 *((volatile unsigned int*)(0x424A1198UL))\r
+#define bFM3_BT2_PPG_TMCR_EGS0                 *((volatile unsigned int*)(0x424A11A0UL))\r
+#define bFM3_BT2_PPG_TMCR_EGS1                 *((volatile unsigned int*)(0x424A11A4UL))\r
+#define bFM3_BT2_PPG_TMCR_PMSK                 *((volatile unsigned int*)(0x424A11A8UL))\r
+#define bFM3_BT2_PPG_TMCR_RTGEN                *((volatile unsigned int*)(0x424A11ACUL))\r
+#define bFM3_BT2_PPG_TMCR_CKS0                 *((volatile unsigned int*)(0x424A11B0UL))\r
+#define bFM3_BT2_PPG_TMCR_CKS1                 *((volatile unsigned int*)(0x424A11B4UL))\r
+#define bFM3_BT2_PPG_TMCR_CKS2                 *((volatile unsigned int*)(0x424A11B8UL))\r
+#define bFM3_BT2_PPG_STC_UDIR                  *((volatile unsigned int*)(0x424A1200UL))\r
+#define bFM3_BT2_PPG_STC_TGIR                  *((volatile unsigned int*)(0x424A1208UL))\r
+#define bFM3_BT2_PPG_STC_UDIE                  *((volatile unsigned int*)(0x424A1210UL))\r
+#define bFM3_BT2_PPG_STC_TGIE                  *((volatile unsigned int*)(0x424A1218UL))\r
+#define bFM3_BT2_PPG_TMCR2_CKS3                *((volatile unsigned int*)(0x424A1220UL))\r
+\r
+/* Base Timer 2 PWM registers */\r
+#define bFM3_BT2_PWM_TMCR_STRG                 *((volatile unsigned int*)(0x424A1180UL))\r
+#define bFM3_BT2_PWM_TMCR_CTEN                 *((volatile unsigned int*)(0x424A1184UL))\r
+#define bFM3_BT2_PWM_TMCR_MDSE                 *((volatile unsigned int*)(0x424A1188UL))\r
+#define bFM3_BT2_PWM_TMCR_OSEL                 *((volatile unsigned int*)(0x424A118CUL))\r
+#define bFM3_BT2_PWM_TMCR_FMD0                 *((volatile unsigned int*)(0x424A1190UL))\r
+#define bFM3_BT2_PWM_TMCR_FMD1                 *((volatile unsigned int*)(0x424A1194UL))\r
+#define bFM3_BT2_PWM_TMCR_FMD2                 *((volatile unsigned int*)(0x424A1198UL))\r
+#define bFM3_BT2_PWM_TMCR_EGS0                 *((volatile unsigned int*)(0x424A11A0UL))\r
+#define bFM3_BT2_PWM_TMCR_EGS1                 *((volatile unsigned int*)(0x424A11A4UL))\r
+#define bFM3_BT2_PWM_TMCR_PMSK                 *((volatile unsigned int*)(0x424A11A8UL))\r
+#define bFM3_BT2_PWM_TMCR_RTGEN                *((volatile unsigned int*)(0x424A11ACUL))\r
+#define bFM3_BT2_PWM_TMCR_CKS0                 *((volatile unsigned int*)(0x424A11B0UL))\r
+#define bFM3_BT2_PWM_TMCR_CKS1                 *((volatile unsigned int*)(0x424A11B4UL))\r
+#define bFM3_BT2_PWM_TMCR_CKS2                 *((volatile unsigned int*)(0x424A11B8UL))\r
+#define bFM3_BT2_PWM_STC_UDIR                  *((volatile unsigned int*)(0x424A1200UL))\r
+#define bFM3_BT2_PWM_STC_DTIR                  *((volatile unsigned int*)(0x424A1204UL))\r
+#define bFM3_BT2_PWM_STC_TGIR                  *((volatile unsigned int*)(0x424A1208UL))\r
+#define bFM3_BT2_PWM_STC_UDIE                  *((volatile unsigned int*)(0x424A1210UL))\r
+#define bFM3_BT2_PWM_STC_DTIE                  *((volatile unsigned int*)(0x424A1214UL))\r
+#define bFM3_BT2_PWM_STC_TGIE                  *((volatile unsigned int*)(0x424A1218UL))\r
+#define bFM3_BT2_PWM_TMCR2_CKS3                *((volatile unsigned int*)(0x424A1220UL))\r
+\r
+/* Base Timer 2 RT registers */\r
+#define bFM3_BT2_RT_TMCR_STRG                  *((volatile unsigned int*)(0x424A1180UL))\r
+#define bFM3_BT2_RT_TMCR_CTEN                  *((volatile unsigned int*)(0x424A1184UL))\r
+#define bFM3_BT2_RT_TMCR_MDSE                  *((volatile unsigned int*)(0x424A1188UL))\r
+#define bFM3_BT2_RT_TMCR_OSEL                  *((volatile unsigned int*)(0x424A118CUL))\r
+#define bFM3_BT2_RT_TMCR_FMD0                  *((volatile unsigned int*)(0x424A1190UL))\r
+#define bFM3_BT2_RT_TMCR_FMD1                  *((volatile unsigned int*)(0x424A1194UL))\r
+#define bFM3_BT2_RT_TMCR_FMD2                  *((volatile unsigned int*)(0x424A1198UL))\r
+#define bFM3_BT2_RT_TMCR_T32                   *((volatile unsigned int*)(0x424A119CUL))\r
+#define bFM3_BT2_RT_TMCR_EGS0                  *((volatile unsigned int*)(0x424A11A0UL))\r
+#define bFM3_BT2_RT_TMCR_EGS1                  *((volatile unsigned int*)(0x424A11A4UL))\r
+#define bFM3_BT2_RT_TMCR_CKS0                  *((volatile unsigned int*)(0x424A11B0UL))\r
+#define bFM3_BT2_RT_TMCR_CKS1                  *((volatile unsigned int*)(0x424A11B4UL))\r
+#define bFM3_BT2_RT_TMCR_CKS2                  *((volatile unsigned int*)(0x424A11B8UL))\r
+#define bFM3_BT2_RT_STC_UDIR                   *((volatile unsigned int*)(0x424A1200UL))\r
+#define bFM3_BT2_RT_STC_TGIR                   *((volatile unsigned int*)(0x424A1208UL))\r
+#define bFM3_BT2_RT_STC_UDIE                   *((volatile unsigned int*)(0x424A1210UL))\r
+#define bFM3_BT2_RT_STC_TGIE                   *((volatile unsigned int*)(0x424A1218UL))\r
+#define bFM3_BT2_RT_TMCR2_CKS3                 *((volatile unsigned int*)(0x424A1220UL))\r
+\r
+/* Base Timer 2 PWC registers */\r
+#define bFM3_BT2_PWC_TMCR_CTEN                 *((volatile unsigned int*)(0x424A1184UL))\r
+#define bFM3_BT2_PWC_TMCR_MDSE                 *((volatile unsigned int*)(0x424A1188UL))\r
+#define bFM3_BT2_PWC_TMCR_FMD0                 *((volatile unsigned int*)(0x424A1190UL))\r
+#define bFM3_BT2_PWC_TMCR_FMD1                 *((volatile unsigned int*)(0x424A1194UL))\r
+#define bFM3_BT2_PWC_TMCR_FMD2                 *((volatile unsigned int*)(0x424A1198UL))\r
+#define bFM3_BT2_PWC_TMCR_T32                  *((volatile unsigned int*)(0x424A119CUL))\r
+#define bFM3_BT2_PWC_TMCR_EGS0                 *((volatile unsigned int*)(0x424A11A0UL))\r
+#define bFM3_BT2_PWC_TMCR_EGS1                 *((volatile unsigned int*)(0x424A11A4UL))\r
+#define bFM3_BT2_PWC_TMCR_EGS2                 *((volatile unsigned int*)(0x424A11A8UL))\r
+#define bFM3_BT2_PWC_TMCR_CKS0                 *((volatile unsigned int*)(0x424A11B0UL))\r
+#define bFM3_BT2_PWC_TMCR_CKS1                 *((volatile unsigned int*)(0x424A11B4UL))\r
+#define bFM3_BT2_PWC_TMCR_CKS2                 *((volatile unsigned int*)(0x424A11B8UL))\r
+#define bFM3_BT2_PWC_STC_OVIR                  *((volatile unsigned int*)(0x424A1200UL))\r
+#define bFM3_BT2_PWC_STC_EDIR                  *((volatile unsigned int*)(0x424A1208UL))\r
+#define bFM3_BT2_PWC_STC_OVIE                  *((volatile unsigned int*)(0x424A1210UL))\r
+#define bFM3_BT2_PWC_STC_EDIE                  *((volatile unsigned int*)(0x424A1218UL))\r
+#define bFM3_BT2_PWC_STC_ERR                   *((volatile unsigned int*)(0x424A121CUL))\r
+#define bFM3_BT2_PWC_TMCR2_CKS3                *((volatile unsigned int*)(0x424A1220UL))\r
+\r
+/* Base Timer 3 PPG registers */\r
+#define bFM3_BT3_PPG_TMCR_STRG                 *((volatile unsigned int*)(0x424A1980UL))\r
+#define bFM3_BT3_PPG_TMCR_CTEN                 *((volatile unsigned int*)(0x424A1984UL))\r
+#define bFM3_BT3_PPG_TMCR_MDSE                 *((volatile unsigned int*)(0x424A1988UL))\r
+#define bFM3_BT3_PPG_TMCR_OSEL                 *((volatile unsigned int*)(0x424A198CUL))\r
+#define bFM3_BT3_PPG_TMCR_FMD0                 *((volatile unsigned int*)(0x424A1990UL))\r
+#define bFM3_BT3_PPG_TMCR_FMD1                 *((volatile unsigned int*)(0x424A1994UL))\r
+#define bFM3_BT3_PPG_TMCR_FMD2                 *((volatile unsigned int*)(0x424A1998UL))\r
+#define bFM3_BT3_PPG_TMCR_EGS0                 *((volatile unsigned int*)(0x424A19A0UL))\r
+#define bFM3_BT3_PPG_TMCR_EGS1                 *((volatile unsigned int*)(0x424A19A4UL))\r
+#define bFM3_BT3_PPG_TMCR_PMSK                 *((volatile unsigned int*)(0x424A19A8UL))\r
+#define bFM3_BT3_PPG_TMCR_RTGEN                *((volatile unsigned int*)(0x424A19ACUL))\r
+#define bFM3_BT3_PPG_TMCR_CKS0                 *((volatile unsigned int*)(0x424A19B0UL))\r
+#define bFM3_BT3_PPG_TMCR_CKS1                 *((volatile unsigned int*)(0x424A19B4UL))\r
+#define bFM3_BT3_PPG_TMCR_CKS2                 *((volatile unsigned int*)(0x424A19B8UL))\r
+#define bFM3_BT3_PPG_STC_UDIR                  *((volatile unsigned int*)(0x424A1A00UL))\r
+#define bFM3_BT3_PPG_STC_TGIR                  *((volatile unsigned int*)(0x424A1A08UL))\r
+#define bFM3_BT3_PPG_STC_UDIE                  *((volatile unsigned int*)(0x424A1A10UL))\r
+#define bFM3_BT3_PPG_STC_TGIE                  *((volatile unsigned int*)(0x424A1A18UL))\r
+#define bFM3_BT3_PPG_TMCR2_CKS3                *((volatile unsigned int*)(0x424A1A20UL))\r
+\r
+/* Base Timer 3 PWM registers */\r
+#define bFM3_BT3_PWM_TMCR_STRG                 *((volatile unsigned int*)(0x424A1980UL))\r
+#define bFM3_BT3_PWM_TMCR_CTEN                 *((volatile unsigned int*)(0x424A1984UL))\r
+#define bFM3_BT3_PWM_TMCR_MDSE                 *((volatile unsigned int*)(0x424A1988UL))\r
+#define bFM3_BT3_PWM_TMCR_OSEL                 *((volatile unsigned int*)(0x424A198CUL))\r
+#define bFM3_BT3_PWM_TMCR_FMD0                 *((volatile unsigned int*)(0x424A1990UL))\r
+#define bFM3_BT3_PWM_TMCR_FMD1                 *((volatile unsigned int*)(0x424A1994UL))\r
+#define bFM3_BT3_PWM_TMCR_FMD2                 *((volatile unsigned int*)(0x424A1998UL))\r
+#define bFM3_BT3_PWM_TMCR_EGS0                 *((volatile unsigned int*)(0x424A19A0UL))\r
+#define bFM3_BT3_PWM_TMCR_EGS1                 *((volatile unsigned int*)(0x424A19A4UL))\r
+#define bFM3_BT3_PWM_TMCR_PMSK                 *((volatile unsigned int*)(0x424A19A8UL))\r
+#define bFM3_BT3_PWM_TMCR_RTGEN                *((volatile unsigned int*)(0x424A19ACUL))\r
+#define bFM3_BT3_PWM_TMCR_CKS0                 *((volatile unsigned int*)(0x424A19B0UL))\r
+#define bFM3_BT3_PWM_TMCR_CKS1                 *((volatile unsigned int*)(0x424A19B4UL))\r
+#define bFM3_BT3_PWM_TMCR_CKS2                 *((volatile unsigned int*)(0x424A19B8UL))\r
+#define bFM3_BT3_PWM_STC_UDIR                  *((volatile unsigned int*)(0x424A1A00UL))\r
+#define bFM3_BT3_PWM_STC_DTIR                  *((volatile unsigned int*)(0x424A1A04UL))\r
+#define bFM3_BT3_PWM_STC_TGIR                  *((volatile unsigned int*)(0x424A1A08UL))\r
+#define bFM3_BT3_PWM_STC_UDIE                  *((volatile unsigned int*)(0x424A1A10UL))\r
+#define bFM3_BT3_PWM_STC_DTIE                  *((volatile unsigned int*)(0x424A1A14UL))\r
+#define bFM3_BT3_PWM_STC_TGIE                  *((volatile unsigned int*)(0x424A1A18UL))\r
+#define bFM3_BT3_PWM_TMCR2_CKS3                *((volatile unsigned int*)(0x424A1A20UL))\r
+\r
+/* Base Timer 3 RT registers */\r
+#define bFM3_BT3_RT_TMCR_STRG                  *((volatile unsigned int*)(0x424A1980UL))\r
+#define bFM3_BT3_RT_TMCR_CTEN                  *((volatile unsigned int*)(0x424A1984UL))\r
+#define bFM3_BT3_RT_TMCR_MDSE                  *((volatile unsigned int*)(0x424A1988UL))\r
+#define bFM3_BT3_RT_TMCR_OSEL                  *((volatile unsigned int*)(0x424A198CUL))\r
+#define bFM3_BT3_RT_TMCR_FMD0                  *((volatile unsigned int*)(0x424A1990UL))\r
+#define bFM3_BT3_RT_TMCR_FMD1                  *((volatile unsigned int*)(0x424A1994UL))\r
+#define bFM3_BT3_RT_TMCR_FMD2                  *((volatile unsigned int*)(0x424A1998UL))\r
+#define bFM3_BT3_RT_TMCR_T32                   *((volatile unsigned int*)(0x424A199CUL))\r
+#define bFM3_BT3_RT_TMCR_EGS0                  *((volatile unsigned int*)(0x424A19A0UL))\r
+#define bFM3_BT3_RT_TMCR_EGS1                  *((volatile unsigned int*)(0x424A19A4UL))\r
+#define bFM3_BT3_RT_TMCR_CKS0                  *((volatile unsigned int*)(0x424A19B0UL))\r
+#define bFM3_BT3_RT_TMCR_CKS1                  *((volatile unsigned int*)(0x424A19B4UL))\r
+#define bFM3_BT3_RT_TMCR_CKS2                  *((volatile unsigned int*)(0x424A19B8UL))\r
+#define bFM3_BT3_RT_STC_UDIR                   *((volatile unsigned int*)(0x424A1A00UL))\r
+#define bFM3_BT3_RT_STC_TGIR                   *((volatile unsigned int*)(0x424A1A08UL))\r
+#define bFM3_BT3_RT_STC_UDIE                   *((volatile unsigned int*)(0x424A1A10UL))\r
+#define bFM3_BT3_RT_STC_TGIE                   *((volatile unsigned int*)(0x424A1A18UL))\r
+#define bFM3_BT3_RT_TMCR2_CKS3                 *((volatile unsigned int*)(0x424A1A20UL))\r
+\r
+/* Base Timer 3 PWC registers */\r
+#define bFM3_BT3_PWC_TMCR_CTEN                 *((volatile unsigned int*)(0x424A1984UL))\r
+#define bFM3_BT3_PWC_TMCR_MDSE                 *((volatile unsigned int*)(0x424A1988UL))\r
+#define bFM3_BT3_PWC_TMCR_FMD0                 *((volatile unsigned int*)(0x424A1990UL))\r
+#define bFM3_BT3_PWC_TMCR_FMD1                 *((volatile unsigned int*)(0x424A1994UL))\r
+#define bFM3_BT3_PWC_TMCR_FMD2                 *((volatile unsigned int*)(0x424A1998UL))\r
+#define bFM3_BT3_PWC_TMCR_T32                  *((volatile unsigned int*)(0x424A199CUL))\r
+#define bFM3_BT3_PWC_TMCR_EGS0                 *((volatile unsigned int*)(0x424A19A0UL))\r
+#define bFM3_BT3_PWC_TMCR_EGS1                 *((volatile unsigned int*)(0x424A19A4UL))\r
+#define bFM3_BT3_PWC_TMCR_EGS2                 *((volatile unsigned int*)(0x424A19A8UL))\r
+#define bFM3_BT3_PWC_TMCR_CKS0                 *((volatile unsigned int*)(0x424A19B0UL))\r
+#define bFM3_BT3_PWC_TMCR_CKS1                 *((volatile unsigned int*)(0x424A19B4UL))\r
+#define bFM3_BT3_PWC_TMCR_CKS2                 *((volatile unsigned int*)(0x424A19B8UL))\r
+#define bFM3_BT3_PWC_STC_OVIR                  *((volatile unsigned int*)(0x424A1A00UL))\r
+#define bFM3_BT3_PWC_STC_EDIR                  *((volatile unsigned int*)(0x424A1A08UL))\r
+#define bFM3_BT3_PWC_STC_OVIE                  *((volatile unsigned int*)(0x424A1A10UL))\r
+#define bFM3_BT3_PWC_STC_EDIE                  *((volatile unsigned int*)(0x424A1A18UL))\r
+#define bFM3_BT3_PWC_STC_ERR                   *((volatile unsigned int*)(0x424A1A1CUL))\r
+#define bFM3_BT3_PWC_TMCR2_CKS3                *((volatile unsigned int*)(0x424A1A20UL))\r
+\r
+/* Base Timer 4 PPG registers */\r
+#define bFM3_BT4_PPG_TMCR_STRG                 *((volatile unsigned int*)(0x424A4180UL))\r
+#define bFM3_BT4_PPG_TMCR_CTEN                 *((volatile unsigned int*)(0x424A4184UL))\r
+#define bFM3_BT4_PPG_TMCR_MDSE                 *((volatile unsigned int*)(0x424A4188UL))\r
+#define bFM3_BT4_PPG_TMCR_OSEL                 *((volatile unsigned int*)(0x424A418CUL))\r
+#define bFM3_BT4_PPG_TMCR_FMD0                 *((volatile unsigned int*)(0x424A4190UL))\r
+#define bFM3_BT4_PPG_TMCR_FMD1                 *((volatile unsigned int*)(0x424A4194UL))\r
+#define bFM3_BT4_PPG_TMCR_FMD2                 *((volatile unsigned int*)(0x424A4198UL))\r
+#define bFM3_BT4_PPG_TMCR_EGS0                 *((volatile unsigned int*)(0x424A41A0UL))\r
+#define bFM3_BT4_PPG_TMCR_EGS1                 *((volatile unsigned int*)(0x424A41A4UL))\r
+#define bFM3_BT4_PPG_TMCR_PMSK                 *((volatile unsigned int*)(0x424A41A8UL))\r
+#define bFM3_BT4_PPG_TMCR_RTGEN                *((volatile unsigned int*)(0x424A41ACUL))\r
+#define bFM3_BT4_PPG_TMCR_CKS0                 *((volatile unsigned int*)(0x424A41B0UL))\r
+#define bFM3_BT4_PPG_TMCR_CKS1                 *((volatile unsigned int*)(0x424A41B4UL))\r
+#define bFM3_BT4_PPG_TMCR_CKS2                 *((volatile unsigned int*)(0x424A41B8UL))\r
+#define bFM3_BT4_PPG_STC_UDIR                  *((volatile unsigned int*)(0x424A4200UL))\r
+#define bFM3_BT4_PPG_STC_TGIR                  *((volatile unsigned int*)(0x424A4208UL))\r
+#define bFM3_BT4_PPG_STC_UDIE                  *((volatile unsigned int*)(0x424A4210UL))\r
+#define bFM3_BT4_PPG_STC_TGIE                  *((volatile unsigned int*)(0x424A4218UL))\r
+#define bFM3_BT4_PPG_TMCR2_CKS3                *((volatile unsigned int*)(0x424A4220UL))\r
+\r
+/* Base Timer 4 PWM registers */\r
+#define bFM3_BT4_PWM_TMCR_STRG                 *((volatile unsigned int*)(0x424A4180UL))\r
+#define bFM3_BT4_PWM_TMCR_CTEN                 *((volatile unsigned int*)(0x424A4184UL))\r
+#define bFM3_BT4_PWM_TMCR_MDSE                 *((volatile unsigned int*)(0x424A4188UL))\r
+#define bFM3_BT4_PWM_TMCR_OSEL                 *((volatile unsigned int*)(0x424A418CUL))\r
+#define bFM3_BT4_PWM_TMCR_FMD0                 *((volatile unsigned int*)(0x424A4190UL))\r
+#define bFM3_BT4_PWM_TMCR_FMD1                 *((volatile unsigned int*)(0x424A4194UL))\r
+#define bFM3_BT4_PWM_TMCR_FMD2                 *((volatile unsigned int*)(0x424A4198UL))\r
+#define bFM3_BT4_PWM_TMCR_EGS0                 *((volatile unsigned int*)(0x424A41A0UL))\r
+#define bFM3_BT4_PWM_TMCR_EGS1                 *((volatile unsigned int*)(0x424A41A4UL))\r
+#define bFM3_BT4_PWM_TMCR_PMSK                 *((volatile unsigned int*)(0x424A41A8UL))\r
+#define bFM3_BT4_PWM_TMCR_RTGEN                *((volatile unsigned int*)(0x424A41ACUL))\r
+#define bFM3_BT4_PWM_TMCR_CKS0                 *((volatile unsigned int*)(0x424A41B0UL))\r
+#define bFM3_BT4_PWM_TMCR_CKS1                 *((volatile unsigned int*)(0x424A41B4UL))\r
+#define bFM3_BT4_PWM_TMCR_CKS2                 *((volatile unsigned int*)(0x424A41B8UL))\r
+#define bFM3_BT4_PWM_STC_UDIR                  *((volatile unsigned int*)(0x424A4200UL))\r
+#define bFM3_BT4_PWM_STC_DTIR                  *((volatile unsigned int*)(0x424A4204UL))\r
+#define bFM3_BT4_PWM_STC_TGIR                  *((volatile unsigned int*)(0x424A4208UL))\r
+#define bFM3_BT4_PWM_STC_UDIE                  *((volatile unsigned int*)(0x424A4210UL))\r
+#define bFM3_BT4_PWM_STC_DTIE                  *((volatile unsigned int*)(0x424A4214UL))\r
+#define bFM3_BT4_PWM_STC_TGIE                  *((volatile unsigned int*)(0x424A4218UL))\r
+#define bFM3_BT4_PWM_TMCR2_CKS3                *((volatile unsigned int*)(0x424A4220UL))\r
+\r
+/* Base Timer 4 RT registers */\r
+#define bFM3_BT4_RT_TMCR_STRG                  *((volatile unsigned int*)(0x424A4180UL))\r
+#define bFM3_BT4_RT_TMCR_CTEN                  *((volatile unsigned int*)(0x424A4184UL))\r
+#define bFM3_BT4_RT_TMCR_MDSE                  *((volatile unsigned int*)(0x424A4188UL))\r
+#define bFM3_BT4_RT_TMCR_OSEL                  *((volatile unsigned int*)(0x424A418CUL))\r
+#define bFM3_BT4_RT_TMCR_FMD0                  *((volatile unsigned int*)(0x424A4190UL))\r
+#define bFM3_BT4_RT_TMCR_FMD1                  *((volatile unsigned int*)(0x424A4194UL))\r
+#define bFM3_BT4_RT_TMCR_FMD2                  *((volatile unsigned int*)(0x424A4198UL))\r
+#define bFM3_BT4_RT_TMCR_T32                   *((volatile unsigned int*)(0x424A419CUL))\r
+#define bFM3_BT4_RT_TMCR_EGS0                  *((volatile unsigned int*)(0x424A41A0UL))\r
+#define bFM3_BT4_RT_TMCR_EGS1                  *((volatile unsigned int*)(0x424A41A4UL))\r
+#define bFM3_BT4_RT_TMCR_CKS0                  *((volatile unsigned int*)(0x424A41B0UL))\r
+#define bFM3_BT4_RT_TMCR_CKS1                  *((volatile unsigned int*)(0x424A41B4UL))\r
+#define bFM3_BT4_RT_TMCR_CKS2                  *((volatile unsigned int*)(0x424A41B8UL))\r
+#define bFM3_BT4_RT_STC_UDIR                   *((volatile unsigned int*)(0x424A4200UL))\r
+#define bFM3_BT4_RT_STC_TGIR                   *((volatile unsigned int*)(0x424A4208UL))\r
+#define bFM3_BT4_RT_STC_UDIE                   *((volatile unsigned int*)(0x424A4210UL))\r
+#define bFM3_BT4_RT_STC_TGIE                   *((volatile unsigned int*)(0x424A4218UL))\r
+#define bFM3_BT4_RT_TMCR2_CKS3                 *((volatile unsigned int*)(0x424A4220UL))\r
+\r
+/* Base Timer 4 PWC registers */\r
+#define bFM3_BT4_PWC_TMCR_CTEN                 *((volatile unsigned int*)(0x424A4184UL))\r
+#define bFM3_BT4_PWC_TMCR_MDSE                 *((volatile unsigned int*)(0x424A4188UL))\r
+#define bFM3_BT4_PWC_TMCR_FMD0                 *((volatile unsigned int*)(0x424A4190UL))\r
+#define bFM3_BT4_PWC_TMCR_FMD1                 *((volatile unsigned int*)(0x424A4194UL))\r
+#define bFM3_BT4_PWC_TMCR_FMD2                 *((volatile unsigned int*)(0x424A4198UL))\r
+#define bFM3_BT4_PWC_TMCR_T32                  *((volatile unsigned int*)(0x424A419CUL))\r
+#define bFM3_BT4_PWC_TMCR_EGS0                 *((volatile unsigned int*)(0x424A41A0UL))\r
+#define bFM3_BT4_PWC_TMCR_EGS1                 *((volatile unsigned int*)(0x424A41A4UL))\r
+#define bFM3_BT4_PWC_TMCR_EGS2                 *((volatile unsigned int*)(0x424A41A8UL))\r
+#define bFM3_BT4_PWC_TMCR_CKS0                 *((volatile unsigned int*)(0x424A41B0UL))\r
+#define bFM3_BT4_PWC_TMCR_CKS1                 *((volatile unsigned int*)(0x424A41B4UL))\r
+#define bFM3_BT4_PWC_TMCR_CKS2                 *((volatile unsigned int*)(0x424A41B8UL))\r
+#define bFM3_BT4_PWC_STC_OVIR                  *((volatile unsigned int*)(0x424A4200UL))\r
+#define bFM3_BT4_PWC_STC_EDIR                  *((volatile unsigned int*)(0x424A4208UL))\r
+#define bFM3_BT4_PWC_STC_OVIE                  *((volatile unsigned int*)(0x424A4210UL))\r
+#define bFM3_BT4_PWC_STC_EDIE                  *((volatile unsigned int*)(0x424A4218UL))\r
+#define bFM3_BT4_PWC_STC_ERR                   *((volatile unsigned int*)(0x424A421CUL))\r
+#define bFM3_BT4_PWC_TMCR2_CKS3                *((volatile unsigned int*)(0x424A4220UL))\r
+\r
+/* Base Timer 5 PPG registers */\r
+#define bFM3_BT5_PPG_TMCR_STRG                 *((volatile unsigned int*)(0x424A4980UL))\r
+#define bFM3_BT5_PPG_TMCR_CTEN                 *((volatile unsigned int*)(0x424A4984UL))\r
+#define bFM3_BT5_PPG_TMCR_MDSE                 *((volatile unsigned int*)(0x424A4988UL))\r
+#define bFM3_BT5_PPG_TMCR_OSEL                 *((volatile unsigned int*)(0x424A498CUL))\r
+#define bFM3_BT5_PPG_TMCR_FMD0                 *((volatile unsigned int*)(0x424A4990UL))\r
+#define bFM3_BT5_PPG_TMCR_FMD1                 *((volatile unsigned int*)(0x424A4994UL))\r
+#define bFM3_BT5_PPG_TMCR_FMD2                 *((volatile unsigned int*)(0x424A4998UL))\r
+#define bFM3_BT5_PPG_TMCR_EGS0                 *((volatile unsigned int*)(0x424A49A0UL))\r
+#define bFM3_BT5_PPG_TMCR_EGS1                 *((volatile unsigned int*)(0x424A49A4UL))\r
+#define bFM3_BT5_PPG_TMCR_PMSK                 *((volatile unsigned int*)(0x424A49A8UL))\r
+#define bFM3_BT5_PPG_TMCR_RTGEN                *((volatile unsigned int*)(0x424A49ACUL))\r
+#define bFM3_BT5_PPG_TMCR_CKS0                 *((volatile unsigned int*)(0x424A49B0UL))\r
+#define bFM3_BT5_PPG_TMCR_CKS1                 *((volatile unsigned int*)(0x424A49B4UL))\r
+#define bFM3_BT5_PPG_TMCR_CKS2                 *((volatile unsigned int*)(0x424A49B8UL))\r
+#define bFM3_BT5_PPG_STC_UDIR                  *((volatile unsigned int*)(0x424A4A00UL))\r
+#define bFM3_BT5_PPG_STC_TGIR                  *((volatile unsigned int*)(0x424A4A08UL))\r
+#define bFM3_BT5_PPG_STC_UDIE                  *((volatile unsigned int*)(0x424A4A10UL))\r
+#define bFM3_BT5_PPG_STC_TGIE                  *((volatile unsigned int*)(0x424A4A18UL))\r
+#define bFM3_BT5_PPG_TMCR2_CKS3                *((volatile unsigned int*)(0x424A4A20UL))\r
+\r
+/* Base Timer 5 PWM registers */\r
+#define bFM3_BT5_PWM_TMCR_STRG                 *((volatile unsigned int*)(0x424A4980UL))\r
+#define bFM3_BT5_PWM_TMCR_CTEN                 *((volatile unsigned int*)(0x424A4984UL))\r
+#define bFM3_BT5_PWM_TMCR_MDSE                 *((volatile unsigned int*)(0x424A4988UL))\r
+#define bFM3_BT5_PWM_TMCR_OSEL                 *((volatile unsigned int*)(0x424A498CUL))\r
+#define bFM3_BT5_PWM_TMCR_FMD0                 *((volatile unsigned int*)(0x424A4990UL))\r
+#define bFM3_BT5_PWM_TMCR_FMD1                 *((volatile unsigned int*)(0x424A4994UL))\r
+#define bFM3_BT5_PWM_TMCR_FMD2                 *((volatile unsigned int*)(0x424A4998UL))\r
+#define bFM3_BT5_PWM_TMCR_EGS0                 *((volatile unsigned int*)(0x424A49A0UL))\r
+#define bFM3_BT5_PWM_TMCR_EGS1                 *((volatile unsigned int*)(0x424A49A4UL))\r
+#define bFM3_BT5_PWM_TMCR_PMSK                 *((volatile unsigned int*)(0x424A49A8UL))\r
+#define bFM3_BT5_PWM_TMCR_RTGEN                *((volatile unsigned int*)(0x424A49ACUL))\r
+#define bFM3_BT5_PWM_TMCR_CKS0                 *((volatile unsigned int*)(0x424A49B0UL))\r
+#define bFM3_BT5_PWM_TMCR_CKS1                 *((volatile unsigned int*)(0x424A49B4UL))\r
+#define bFM3_BT5_PWM_TMCR_CKS2                 *((volatile unsigned int*)(0x424A49B8UL))\r
+#define bFM3_BT5_PWM_STC_UDIR                  *((volatile unsigned int*)(0x424A4A00UL))\r
+#define bFM3_BT5_PWM_STC_DTIR                  *((volatile unsigned int*)(0x424A4A04UL))\r
+#define bFM3_BT5_PWM_STC_TGIR                  *((volatile unsigned int*)(0x424A4A08UL))\r
+#define bFM3_BT5_PWM_STC_UDIE                  *((volatile unsigned int*)(0x424A4A10UL))\r
+#define bFM3_BT5_PWM_STC_DTIE                  *((volatile unsigned int*)(0x424A4A14UL))\r
+#define bFM3_BT5_PWM_STC_TGIE                  *((volatile unsigned int*)(0x424A4A18UL))\r
+#define bFM3_BT5_PWM_TMCR2_CKS3                *((volatile unsigned int*)(0x424A4A20UL))\r
+\r
+/* Base Timer 5 RT registers */\r
+#define bFM3_BT5_RT_TMCR_STRG                  *((volatile unsigned int*)(0x424A4980UL))\r
+#define bFM3_BT5_RT_TMCR_CTEN                  *((volatile unsigned int*)(0x424A4984UL))\r
+#define bFM3_BT5_RT_TMCR_MDSE                  *((volatile unsigned int*)(0x424A4988UL))\r
+#define bFM3_BT5_RT_TMCR_OSEL                  *((volatile unsigned int*)(0x424A498CUL))\r
+#define bFM3_BT5_RT_TMCR_FMD0                  *((volatile unsigned int*)(0x424A4990UL))\r
+#define bFM3_BT5_RT_TMCR_FMD1                  *((volatile unsigned int*)(0x424A4994UL))\r
+#define bFM3_BT5_RT_TMCR_FMD2                  *((volatile unsigned int*)(0x424A4998UL))\r
+#define bFM3_BT5_RT_TMCR_T32                   *((volatile unsigned int*)(0x424A499CUL))\r
+#define bFM3_BT5_RT_TMCR_EGS0                  *((volatile unsigned int*)(0x424A49A0UL))\r
+#define bFM3_BT5_RT_TMCR_EGS1                  *((volatile unsigned int*)(0x424A49A4UL))\r
+#define bFM3_BT5_RT_TMCR_CKS0                  *((volatile unsigned int*)(0x424A49B0UL))\r
+#define bFM3_BT5_RT_TMCR_CKS1                  *((volatile unsigned int*)(0x424A49B4UL))\r
+#define bFM3_BT5_RT_TMCR_CKS2                  *((volatile unsigned int*)(0x424A49B8UL))\r
+#define bFM3_BT5_RT_STC_UDIR                   *((volatile unsigned int*)(0x424A4A00UL))\r
+#define bFM3_BT5_RT_STC_TGIR                   *((volatile unsigned int*)(0x424A4A08UL))\r
+#define bFM3_BT5_RT_STC_UDIE                   *((volatile unsigned int*)(0x424A4A10UL))\r
+#define bFM3_BT5_RT_STC_TGIE                   *((volatile unsigned int*)(0x424A4A18UL))\r
+#define bFM3_BT5_RT_TMCR2_CKS3                 *((volatile unsigned int*)(0x424A4A20UL))\r
+\r
+/* Base Timer 5 PWC registers */\r
+#define bFM3_BT5_PWC_TMCR_CTEN                 *((volatile unsigned int*)(0x424A4984UL))\r
+#define bFM3_BT5_PWC_TMCR_MDSE                 *((volatile unsigned int*)(0x424A4988UL))\r
+#define bFM3_BT5_PWC_TMCR_FMD0                 *((volatile unsigned int*)(0x424A4990UL))\r
+#define bFM3_BT5_PWC_TMCR_FMD1                 *((volatile unsigned int*)(0x424A4994UL))\r
+#define bFM3_BT5_PWC_TMCR_FMD2                 *((volatile unsigned int*)(0x424A4998UL))\r
+#define bFM3_BT5_PWC_TMCR_T32                  *((volatile unsigned int*)(0x424A499CUL))\r
+#define bFM3_BT5_PWC_TMCR_EGS0                 *((volatile unsigned int*)(0x424A49A0UL))\r
+#define bFM3_BT5_PWC_TMCR_EGS1                 *((volatile unsigned int*)(0x424A49A4UL))\r
+#define bFM3_BT5_PWC_TMCR_EGS2                 *((volatile unsigned int*)(0x424A49A8UL))\r
+#define bFM3_BT5_PWC_TMCR_CKS0                 *((volatile unsigned int*)(0x424A49B0UL))\r
+#define bFM3_BT5_PWC_TMCR_CKS1                 *((volatile unsigned int*)(0x424A49B4UL))\r
+#define bFM3_BT5_PWC_TMCR_CKS2                 *((volatile unsigned int*)(0x424A49B8UL))\r
+#define bFM3_BT5_PWC_STC_OVIR                  *((volatile unsigned int*)(0x424A4A00UL))\r
+#define bFM3_BT5_PWC_STC_EDIR                  *((volatile unsigned int*)(0x424A4A08UL))\r
+#define bFM3_BT5_PWC_STC_OVIE                  *((volatile unsigned int*)(0x424A4A10UL))\r
+#define bFM3_BT5_PWC_STC_EDIE                  *((volatile unsigned int*)(0x424A4A18UL))\r
+#define bFM3_BT5_PWC_STC_ERR                   *((volatile unsigned int*)(0x424A4A1CUL))\r
+#define bFM3_BT5_PWC_TMCR2_CKS3                *((volatile unsigned int*)(0x424A4A20UL))\r
+\r
+/* Base Timer 6 PPG registers */\r
+#define bFM3_BT6_PPG_TMCR_STRG                 *((volatile unsigned int*)(0x424A5180UL))\r
+#define bFM3_BT6_PPG_TMCR_CTEN                 *((volatile unsigned int*)(0x424A5184UL))\r
+#define bFM3_BT6_PPG_TMCR_MDSE                 *((volatile unsigned int*)(0x424A5188UL))\r
+#define bFM3_BT6_PPG_TMCR_OSEL                 *((volatile unsigned int*)(0x424A518CUL))\r
+#define bFM3_BT6_PPG_TMCR_FMD0                 *((volatile unsigned int*)(0x424A5190UL))\r
+#define bFM3_BT6_PPG_TMCR_FMD1                 *((volatile unsigned int*)(0x424A5194UL))\r
+#define bFM3_BT6_PPG_TMCR_FMD2                 *((volatile unsigned int*)(0x424A5198UL))\r
+#define bFM3_BT6_PPG_TMCR_EGS0                 *((volatile unsigned int*)(0x424A51A0UL))\r
+#define bFM3_BT6_PPG_TMCR_EGS1                 *((volatile unsigned int*)(0x424A51A4UL))\r
+#define bFM3_BT6_PPG_TMCR_PMSK                 *((volatile unsigned int*)(0x424A51A8UL))\r
+#define bFM3_BT6_PPG_TMCR_RTGEN                *((volatile unsigned int*)(0x424A51ACUL))\r
+#define bFM3_BT6_PPG_TMCR_CKS0                 *((volatile unsigned int*)(0x424A51B0UL))\r
+#define bFM3_BT6_PPG_TMCR_CKS1                 *((volatile unsigned int*)(0x424A51B4UL))\r
+#define bFM3_BT6_PPG_TMCR_CKS2                 *((volatile unsigned int*)(0x424A51B8UL))\r
+#define bFM3_BT6_PPG_STC_UDIR                  *((volatile unsigned int*)(0x424A5200UL))\r
+#define bFM3_BT6_PPG_STC_TGIR                  *((volatile unsigned int*)(0x424A5208UL))\r
+#define bFM3_BT6_PPG_STC_UDIE                  *((volatile unsigned int*)(0x424A5210UL))\r
+#define bFM3_BT6_PPG_STC_TGIE                  *((volatile unsigned int*)(0x424A5218UL))\r
+#define bFM3_BT6_PPG_TMCR2_CKS3                *((volatile unsigned int*)(0x424A5220UL))\r
+\r
+/* Base Timer 6 PWM registers */\r
+#define bFM3_BT6_PWM_TMCR_STRG                 *((volatile unsigned int*)(0x424A5180UL))\r
+#define bFM3_BT6_PWM_TMCR_CTEN                 *((volatile unsigned int*)(0x424A5184UL))\r
+#define bFM3_BT6_PWM_TMCR_MDSE                 *((volatile unsigned int*)(0x424A5188UL))\r
+#define bFM3_BT6_PWM_TMCR_OSEL                 *((volatile unsigned int*)(0x424A518CUL))\r
+#define bFM3_BT6_PWM_TMCR_FMD0                 *((volatile unsigned int*)(0x424A5190UL))\r
+#define bFM3_BT6_PWM_TMCR_FMD1                 *((volatile unsigned int*)(0x424A5194UL))\r
+#define bFM3_BT6_PWM_TMCR_FMD2                 *((volatile unsigned int*)(0x424A5198UL))\r
+#define bFM3_BT6_PWM_TMCR_EGS0                 *((volatile unsigned int*)(0x424A51A0UL))\r
+#define bFM3_BT6_PWM_TMCR_EGS1                 *((volatile unsigned int*)(0x424A51A4UL))\r
+#define bFM3_BT6_PWM_TMCR_PMSK                 *((volatile unsigned int*)(0x424A51A8UL))\r
+#define bFM3_BT6_PWM_TMCR_RTGEN                *((volatile unsigned int*)(0x424A51ACUL))\r
+#define bFM3_BT6_PWM_TMCR_CKS0                 *((volatile unsigned int*)(0x424A51B0UL))\r
+#define bFM3_BT6_PWM_TMCR_CKS1                 *((volatile unsigned int*)(0x424A51B4UL))\r
+#define bFM3_BT6_PWM_TMCR_CKS2                 *((volatile unsigned int*)(0x424A51B8UL))\r
+#define bFM3_BT6_PWM_STC_UDIR                  *((volatile unsigned int*)(0x424A5200UL))\r
+#define bFM3_BT6_PWM_STC_DTIR                  *((volatile unsigned int*)(0x424A5204UL))\r
+#define bFM3_BT6_PWM_STC_TGIR                  *((volatile unsigned int*)(0x424A5208UL))\r
+#define bFM3_BT6_PWM_STC_UDIE                  *((volatile unsigned int*)(0x424A5210UL))\r
+#define bFM3_BT6_PWM_STC_DTIE                  *((volatile unsigned int*)(0x424A5214UL))\r
+#define bFM3_BT6_PWM_STC_TGIE                  *((volatile unsigned int*)(0x424A5218UL))\r
+#define bFM3_BT6_PWM_TMCR2_CKS3                *((volatile unsigned int*)(0x424A5220UL))\r
+\r
+/* Base Timer 6 RT registers */\r
+#define bFM3_BT6_RT_TMCR_STRG                  *((volatile unsigned int*)(0x424A5180UL))\r
+#define bFM3_BT6_RT_TMCR_CTEN                  *((volatile unsigned int*)(0x424A5184UL))\r
+#define bFM3_BT6_RT_TMCR_MDSE                  *((volatile unsigned int*)(0x424A5188UL))\r
+#define bFM3_BT6_RT_TMCR_OSEL                  *((volatile unsigned int*)(0x424A518CUL))\r
+#define bFM3_BT6_RT_TMCR_FMD0                  *((volatile unsigned int*)(0x424A5190UL))\r
+#define bFM3_BT6_RT_TMCR_FMD1                  *((volatile unsigned int*)(0x424A5194UL))\r
+#define bFM3_BT6_RT_TMCR_FMD2                  *((volatile unsigned int*)(0x424A5198UL))\r
+#define bFM3_BT6_RT_TMCR_T32                   *((volatile unsigned int*)(0x424A519CUL))\r
+#define bFM3_BT6_RT_TMCR_EGS0                  *((volatile unsigned int*)(0x424A51A0UL))\r
+#define bFM3_BT6_RT_TMCR_EGS1                  *((volatile unsigned int*)(0x424A51A4UL))\r
+#define bFM3_BT6_RT_TMCR_CKS0                  *((volatile unsigned int*)(0x424A51B0UL))\r
+#define bFM3_BT6_RT_TMCR_CKS1                  *((volatile unsigned int*)(0x424A51B4UL))\r
+#define bFM3_BT6_RT_TMCR_CKS2                  *((volatile unsigned int*)(0x424A51B8UL))\r
+#define bFM3_BT6_RT_STC_UDIR                   *((volatile unsigned int*)(0x424A5200UL))\r
+#define bFM3_BT6_RT_STC_TGIR                   *((volatile unsigned int*)(0x424A5208UL))\r
+#define bFM3_BT6_RT_STC_UDIE                   *((volatile unsigned int*)(0x424A5210UL))\r
+#define bFM3_BT6_RT_STC_TGIE                   *((volatile unsigned int*)(0x424A5218UL))\r
+#define bFM3_BT6_RT_TMCR2_CKS3                 *((volatile unsigned int*)(0x424A5220UL))\r
+\r
+/* Base Timer 6 PWC registers */\r
+#define bFM3_BT6_PWC_TMCR_CTEN                 *((volatile unsigned int*)(0x424A5184UL))\r
+#define bFM3_BT6_PWC_TMCR_MDSE                 *((volatile unsigned int*)(0x424A5188UL))\r
+#define bFM3_BT6_PWC_TMCR_FMD0                 *((volatile unsigned int*)(0x424A5190UL))\r
+#define bFM3_BT6_PWC_TMCR_FMD1                 *((volatile unsigned int*)(0x424A5194UL))\r
+#define bFM3_BT6_PWC_TMCR_FMD2                 *((volatile unsigned int*)(0x424A5198UL))\r
+#define bFM3_BT6_PWC_TMCR_T32                  *((volatile unsigned int*)(0x424A519CUL))\r
+#define bFM3_BT6_PWC_TMCR_EGS0                 *((volatile unsigned int*)(0x424A51A0UL))\r
+#define bFM3_BT6_PWC_TMCR_EGS1                 *((volatile unsigned int*)(0x424A51A4UL))\r
+#define bFM3_BT6_PWC_TMCR_EGS2                 *((volatile unsigned int*)(0x424A51A8UL))\r
+#define bFM3_BT6_PWC_TMCR_CKS0                 *((volatile unsigned int*)(0x424A51B0UL))\r
+#define bFM3_BT6_PWC_TMCR_CKS1                 *((volatile unsigned int*)(0x424A51B4UL))\r
+#define bFM3_BT6_PWC_TMCR_CKS2                 *((volatile unsigned int*)(0x424A51B8UL))\r
+#define bFM3_BT6_PWC_STC_OVIR                  *((volatile unsigned int*)(0x424A5200UL))\r
+#define bFM3_BT6_PWC_STC_EDIR                  *((volatile unsigned int*)(0x424A5208UL))\r
+#define bFM3_BT6_PWC_STC_OVIE                  *((volatile unsigned int*)(0x424A5210UL))\r
+#define bFM3_BT6_PWC_STC_EDIE                  *((volatile unsigned int*)(0x424A5218UL))\r
+#define bFM3_BT6_PWC_STC_ERR                   *((volatile unsigned int*)(0x424A521CUL))\r
+#define bFM3_BT6_PWC_TMCR2_CKS3                *((volatile unsigned int*)(0x424A5220UL))\r
+\r
+/* Base Timer 7 PPG registers */\r
+#define bFM3_BT7_PPG_TMCR_STRG                 *((volatile unsigned int*)(0x424A5980UL))\r
+#define bFM3_BT7_PPG_TMCR_CTEN                 *((volatile unsigned int*)(0x424A5984UL))\r
+#define bFM3_BT7_PPG_TMCR_MDSE                 *((volatile unsigned int*)(0x424A5988UL))\r
+#define bFM3_BT7_PPG_TMCR_OSEL                 *((volatile unsigned int*)(0x424A598CUL))\r
+#define bFM3_BT7_PPG_TMCR_FMD0                 *((volatile unsigned int*)(0x424A5990UL))\r
+#define bFM3_BT7_PPG_TMCR_FMD1                 *((volatile unsigned int*)(0x424A5994UL))\r
+#define bFM3_BT7_PPG_TMCR_FMD2                 *((volatile unsigned int*)(0x424A5998UL))\r
+#define bFM3_BT7_PPG_TMCR_EGS0                 *((volatile unsigned int*)(0x424A59A0UL))\r
+#define bFM3_BT7_PPG_TMCR_EGS1                 *((volatile unsigned int*)(0x424A59A4UL))\r
+#define bFM3_BT7_PPG_TMCR_PMSK                 *((volatile unsigned int*)(0x424A59A8UL))\r
+#define bFM3_BT7_PPG_TMCR_RTGEN                *((volatile unsigned int*)(0x424A59ACUL))\r
+#define bFM3_BT7_PPG_TMCR_CKS0                 *((volatile unsigned int*)(0x424A59B0UL))\r
+#define bFM3_BT7_PPG_TMCR_CKS1                 *((volatile unsigned int*)(0x424A59B4UL))\r
+#define bFM3_BT7_PPG_TMCR_CKS2                 *((volatile unsigned int*)(0x424A59B8UL))\r
+#define bFM3_BT7_PPG_STC_UDIR                  *((volatile unsigned int*)(0x424A5A00UL))\r
+#define bFM3_BT7_PPG_STC_TGIR                  *((volatile unsigned int*)(0x424A5A08UL))\r
+#define bFM3_BT7_PPG_STC_UDIE                  *((volatile unsigned int*)(0x424A5A10UL))\r
+#define bFM3_BT7_PPG_STC_TGIE                  *((volatile unsigned int*)(0x424A5A18UL))\r
+#define bFM3_BT7_PPG_TMCR2_CKS3                *((volatile unsigned int*)(0x424A5A20UL))\r
+\r
+/* Base Timer 7 PWM registers */\r
+#define bFM3_BT7_PWM_TMCR_STRG                 *((volatile unsigned int*)(0x424A5980UL))\r
+#define bFM3_BT7_PWM_TMCR_CTEN                 *((volatile unsigned int*)(0x424A5984UL))\r
+#define bFM3_BT7_PWM_TMCR_MDSE                 *((volatile unsigned int*)(0x424A5988UL))\r
+#define bFM3_BT7_PWM_TMCR_OSEL                 *((volatile unsigned int*)(0x424A598CUL))\r
+#define bFM3_BT7_PWM_TMCR_FMD0                 *((volatile unsigned int*)(0x424A5990UL))\r
+#define bFM3_BT7_PWM_TMCR_FMD1                 *((volatile unsigned int*)(0x424A5994UL))\r
+#define bFM3_BT7_PWM_TMCR_FMD2                 *((volatile unsigned int*)(0x424A5998UL))\r
+#define bFM3_BT7_PWM_TMCR_EGS0                 *((volatile unsigned int*)(0x424A59A0UL))\r
+#define bFM3_BT7_PWM_TMCR_EGS1                 *((volatile unsigned int*)(0x424A59A4UL))\r
+#define bFM3_BT7_PWM_TMCR_PMSK                 *((volatile unsigned int*)(0x424A59A8UL))\r
+#define bFM3_BT7_PWM_TMCR_RTGEN                *((volatile unsigned int*)(0x424A59ACUL))\r
+#define bFM3_BT7_PWM_TMCR_CKS0                 *((volatile unsigned int*)(0x424A59B0UL))\r
+#define bFM3_BT7_PWM_TMCR_CKS1                 *((volatile unsigned int*)(0x424A59B4UL))\r
+#define bFM3_BT7_PWM_TMCR_CKS2                 *((volatile unsigned int*)(0x424A59B8UL))\r
+#define bFM3_BT7_PWM_STC_UDIR                  *((volatile unsigned int*)(0x424A5A00UL))\r
+#define bFM3_BT7_PWM_STC_DTIR                  *((volatile unsigned int*)(0x424A5A04UL))\r
+#define bFM3_BT7_PWM_STC_TGIR                  *((volatile unsigned int*)(0x424A5A08UL))\r
+#define bFM3_BT7_PWM_STC_UDIE                  *((volatile unsigned int*)(0x424A5A10UL))\r
+#define bFM3_BT7_PWM_STC_DTIE                  *((volatile unsigned int*)(0x424A5A14UL))\r
+#define bFM3_BT7_PWM_STC_TGIE                  *((volatile unsigned int*)(0x424A5A18UL))\r
+#define bFM3_BT7_PWM_TMCR2_CKS3                *((volatile unsigned int*)(0x424A5A20UL))\r
+\r
+/* Base Timer 7 RT registers */\r
+#define bFM3_BT7_RT_TMCR_STRG                  *((volatile unsigned int*)(0x424A5980UL))\r
+#define bFM3_BT7_RT_TMCR_CTEN                  *((volatile unsigned int*)(0x424A5984UL))\r
+#define bFM3_BT7_RT_TMCR_MDSE                  *((volatile unsigned int*)(0x424A5988UL))\r
+#define bFM3_BT7_RT_TMCR_OSEL                  *((volatile unsigned int*)(0x424A598CUL))\r
+#define bFM3_BT7_RT_TMCR_FMD0                  *((volatile unsigned int*)(0x424A5990UL))\r
+#define bFM3_BT7_RT_TMCR_FMD1                  *((volatile unsigned int*)(0x424A5994UL))\r
+#define bFM3_BT7_RT_TMCR_FMD2                  *((volatile unsigned int*)(0x424A5998UL))\r
+#define bFM3_BT7_RT_TMCR_T32                   *((volatile unsigned int*)(0x424A599CUL))\r
+#define bFM3_BT7_RT_TMCR_EGS0                  *((volatile unsigned int*)(0x424A59A0UL))\r
+#define bFM3_BT7_RT_TMCR_EGS1                  *((volatile unsigned int*)(0x424A59A4UL))\r
+#define bFM3_BT7_RT_TMCR_CKS0                  *((volatile unsigned int*)(0x424A59B0UL))\r
+#define bFM3_BT7_RT_TMCR_CKS1                  *((volatile unsigned int*)(0x424A59B4UL))\r
+#define bFM3_BT7_RT_TMCR_CKS2                  *((volatile unsigned int*)(0x424A59B8UL))\r
+#define bFM3_BT7_RT_STC_UDIR                   *((volatile unsigned int*)(0x424A5A00UL))\r
+#define bFM3_BT7_RT_STC_TGIR                   *((volatile unsigned int*)(0x424A5A08UL))\r
+#define bFM3_BT7_RT_STC_UDIE                   *((volatile unsigned int*)(0x424A5A10UL))\r
+#define bFM3_BT7_RT_STC_TGIE                   *((volatile unsigned int*)(0x424A5A18UL))\r
+#define bFM3_BT7_RT_TMCR2_CKS3                 *((volatile unsigned int*)(0x424A5A20UL))\r
+\r
+/* Base Timer 7 PWC registers */\r
+#define bFM3_BT7_PWC_TMCR_CTEN                 *((volatile unsigned int*)(0x424A5984UL))\r
+#define bFM3_BT7_PWC_TMCR_MDSE                 *((volatile unsigned int*)(0x424A5988UL))\r
+#define bFM3_BT7_PWC_TMCR_FMD0                 *((volatile unsigned int*)(0x424A5990UL))\r
+#define bFM3_BT7_PWC_TMCR_FMD1                 *((volatile unsigned int*)(0x424A5994UL))\r
+#define bFM3_BT7_PWC_TMCR_FMD2                 *((volatile unsigned int*)(0x424A5998UL))\r
+#define bFM3_BT7_PWC_TMCR_T32                  *((volatile unsigned int*)(0x424A599CUL))\r
+#define bFM3_BT7_PWC_TMCR_EGS0                 *((volatile unsigned int*)(0x424A59A0UL))\r
+#define bFM3_BT7_PWC_TMCR_EGS1                 *((volatile unsigned int*)(0x424A59A4UL))\r
+#define bFM3_BT7_PWC_TMCR_EGS2                 *((volatile unsigned int*)(0x424A59A8UL))\r
+#define bFM3_BT7_PWC_TMCR_CKS0                 *((volatile unsigned int*)(0x424A59B0UL))\r
+#define bFM3_BT7_PWC_TMCR_CKS1                 *((volatile unsigned int*)(0x424A59B4UL))\r
+#define bFM3_BT7_PWC_TMCR_CKS2                 *((volatile unsigned int*)(0x424A59B8UL))\r
+#define bFM3_BT7_PWC_STC_OVIR                  *((volatile unsigned int*)(0x424A5A00UL))\r
+#define bFM3_BT7_PWC_STC_EDIR                  *((volatile unsigned int*)(0x424A5A08UL))\r
+#define bFM3_BT7_PWC_STC_OVIE                  *((volatile unsigned int*)(0x424A5A10UL))\r
+#define bFM3_BT7_PWC_STC_EDIE                  *((volatile unsigned int*)(0x424A5A18UL))\r
+#define bFM3_BT7_PWC_STC_ERR                   *((volatile unsigned int*)(0x424A5A1CUL))\r
+#define bFM3_BT7_PWC_TMCR2_CKS3                *((volatile unsigned int*)(0x424A5A20UL))\r
+\r
+/* Base Timer I/O selector channel 0 - channel 3 registers */\r
+#define bFM3_BTIOSEL03_BTSEL0123_SEL01_0       *((volatile unsigned int*)(0x424A2020UL))\r
+#define bFM3_BTIOSEL03_BTSEL0123_SEL01_1       *((volatile unsigned int*)(0x424A2024UL))\r
+#define bFM3_BTIOSEL03_BTSEL0123_SEL01_2       *((volatile unsigned int*)(0x424A2028UL))\r
+#define bFM3_BTIOSEL03_BTSEL0123_SEL01_3       *((volatile unsigned int*)(0x424A202CUL))\r
+#define bFM3_BTIOSEL03_BTSEL0123_SEL23_0       *((volatile unsigned int*)(0x424A2030UL))\r
+#define bFM3_BTIOSEL03_BTSEL0123_SEL23_1       *((volatile unsigned int*)(0x424A2034UL))\r
+#define bFM3_BTIOSEL03_BTSEL0123_SEL23_2       *((volatile unsigned int*)(0x424A2038UL))\r
+#define bFM3_BTIOSEL03_BTSEL0123_SEL23_3       *((volatile unsigned int*)(0x424A203CUL))\r
+\r
+/* Base Timer I/O selector channel 4 - channel 7 registers */\r
+#define bFM3_BTIOSEL47_BTSEL4567_SEL45_0       *((volatile unsigned int*)(0x424A6020UL))\r
+#define bFM3_BTIOSEL47_BTSEL4567_SEL45_1       *((volatile unsigned int*)(0x424A6024UL))\r
+#define bFM3_BTIOSEL47_BTSEL4567_SEL45_2       *((volatile unsigned int*)(0x424A6028UL))\r
+#define bFM3_BTIOSEL47_BTSEL4567_SEL45_3       *((volatile unsigned int*)(0x424A602CUL))\r
+#define bFM3_BTIOSEL47_BTSEL4567_SEL67_0       *((volatile unsigned int*)(0x424A6030UL))\r
+#define bFM3_BTIOSEL47_BTSEL4567_SEL67_1       *((volatile unsigned int*)(0x424A6034UL))\r
+#define bFM3_BTIOSEL47_BTSEL4567_SEL67_2       *((volatile unsigned int*)(0x424A6038UL))\r
+#define bFM3_BTIOSEL47_BTSEL4567_SEL67_3       *((volatile unsigned int*)(0x424A603CUL))\r
+\r
+/* Software based Simulation Startup (Base Timer) register */\r
+#define bFM3_SBSSR_BTSSSR_SSR0                 *((volatile unsigned int*)(0x424BFF80UL))\r
+#define bFM3_SBSSR_BTSSSR_SSR1                 *((volatile unsigned int*)(0x424BFF84UL))\r
+#define bFM3_SBSSR_BTSSSR_SSR2                 *((volatile unsigned int*)(0x424BFF88UL))\r
+#define bFM3_SBSSR_BTSSSR_SSR3                 *((volatile unsigned int*)(0x424BFF8CUL))\r
+#define bFM3_SBSSR_BTSSSR_SSR4                 *((volatile unsigned int*)(0x424BFF90UL))\r
+#define bFM3_SBSSR_BTSSSR_SSR5                 *((volatile unsigned int*)(0x424BFF94UL))\r
+#define bFM3_SBSSR_BTSSSR_SSR6                 *((volatile unsigned int*)(0x424BFF98UL))\r
+#define bFM3_SBSSR_BTSSSR_SSR7                 *((volatile unsigned int*)(0x424BFF9CUL))\r
+#define bFM3_SBSSR_BTSSSR_SSR8                 *((volatile unsigned int*)(0x424BFFA0UL))\r
+#define bFM3_SBSSR_BTSSSR_SSR9                 *((volatile unsigned int*)(0x424BFFA4UL))\r
+#define bFM3_SBSSR_BTSSSR_SSR10                *((volatile unsigned int*)(0x424BFFA8UL))\r
+#define bFM3_SBSSR_BTSSSR_SSR11                *((volatile unsigned int*)(0x424BFFACUL))\r
+#define bFM3_SBSSR_BTSSSR_SSR12                *((volatile unsigned int*)(0x424BFFB0UL))\r
+#define bFM3_SBSSR_BTSSSR_SSR13                *((volatile unsigned int*)(0x424BFFB4UL))\r
+#define bFM3_SBSSR_BTSSSR_SSR14                *((volatile unsigned int*)(0x424BFFB8UL))\r
+#define bFM3_SBSSR_BTSSSR_SSR15                *((volatile unsigned int*)(0x424BFFBCUL))\r
+\r
+/* Quad position and revolution counter channel 0 registers */\r
+#define bFM3_QPRC0_QICR_QPCMIE                 *((volatile unsigned int*)(0x424C0280UL))\r
+#define bFM3_QPRC0_QICR_QPCMF                  *((volatile unsigned int*)(0x424C0284UL))\r
+#define bFM3_QPRC0_QICR_QPRCMIE                *((volatile unsigned int*)(0x424C0288UL))\r
+#define bFM3_QPRC0_QICR_QPRCMF                 *((volatile unsigned int*)(0x424C028CUL))\r
+#define bFM3_QPRC0_QICR_OUZIE                  *((volatile unsigned int*)(0x424C0290UL))\r
+#define bFM3_QPRC0_QICR_UFDF                   *((volatile unsigned int*)(0x424C0294UL))\r
+#define bFM3_QPRC0_QICR_OFDF                   *((volatile unsigned int*)(0x424C0298UL))\r
+#define bFM3_QPRC0_QICR_ZIIF                   *((volatile unsigned int*)(0x424C029CUL))\r
+#define bFM3_QPRC0_QICR_CDCIE                  *((volatile unsigned int*)(0x424C02A0UL))\r
+#define bFM3_QPRC0_QICR_CDCF                   *((volatile unsigned int*)(0x424C02A4UL))\r
+#define bFM3_QPRC0_QICR_DIRPC                  *((volatile unsigned int*)(0x424C02A8UL))\r
+#define bFM3_QPRC0_QICR_DIROU                  *((volatile unsigned int*)(0x424C02ACUL))\r
+#define bFM3_QPRC0_QICR_QPCNRCMIE              *((volatile unsigned int*)(0x424C02B0UL))\r
+#define bFM3_QPRC0_QICR_QPCNRCMF               *((volatile unsigned int*)(0x424C02B4UL))\r
+#define bFM3_QPRC0_QICRL_QPCMIE                *((volatile unsigned int*)(0x424C0280UL))\r
+#define bFM3_QPRC0_QICRL_QPCMF                 *((volatile unsigned int*)(0x424C0284UL))\r
+#define bFM3_QPRC0_QICRL_QPRCMIE               *((volatile unsigned int*)(0x424C0288UL))\r
+#define bFM3_QPRC0_QICRL_QPRCMF                *((volatile unsigned int*)(0x424C028CUL))\r
+#define bFM3_QPRC0_QICRL_OUZIE                 *((volatile unsigned int*)(0x424C0290UL))\r
+#define bFM3_QPRC0_QICRL_UFDF                  *((volatile unsigned int*)(0x424C0294UL))\r
+#define bFM3_QPRC0_QICRL_OFDF                  *((volatile unsigned int*)(0x424C0298UL))\r
+#define bFM3_QPRC0_QICRL_ZIIF                  *((volatile unsigned int*)(0x424C029CUL))\r
+#define bFM3_QPRC0_QICRH_CDCIE                 *((volatile unsigned int*)(0x424C02A0UL))\r
+#define bFM3_QPRC0_QICRH_CDCF                  *((volatile unsigned int*)(0x424C02A4UL))\r
+#define bFM3_QPRC0_QICRH_DIRPC                 *((volatile unsigned int*)(0x424C02A8UL))\r
+#define bFM3_QPRC0_QICRH_DIROU                 *((volatile unsigned int*)(0x424C02ACUL))\r
+#define bFM3_QPRC0_QICRH_QPCNRCMIE             *((volatile unsigned int*)(0x424C02B0UL))\r
+#define bFM3_QPRC0_QICRH_QPCNRCMF              *((volatile unsigned int*)(0x424C02B4UL))\r
+#define bFM3_QPRC0_QCR_PCM0                    *((volatile unsigned int*)(0x424C0300UL))\r
+#define bFM3_QPRC0_QCR_PCM1                    *((volatile unsigned int*)(0x424C0304UL))\r
+#define bFM3_QPRC0_QCR_RCM0                    *((volatile unsigned int*)(0x424C0308UL))\r
+#define bFM3_QPRC0_QCR_RCM1                    *((volatile unsigned int*)(0x424C030CUL))\r
+#define bFM3_QPRC0_QCR_PSTP                    *((volatile unsigned int*)(0x424C0310UL))\r
+#define bFM3_QPRC0_QCR_CGSC                    *((volatile unsigned int*)(0x424C0314UL))\r
+#define bFM3_QPRC0_QCR_RSEL                    *((volatile unsigned int*)(0x424C0318UL))\r
+#define bFM3_QPRC0_QCR_SWAP                    *((volatile unsigned int*)(0x424C031CUL))\r
+#define bFM3_QPRC0_QCR_PCRM0                   *((volatile unsigned int*)(0x424C0320UL))\r
+#define bFM3_QPRC0_QCR_PCRM1                   *((volatile unsigned int*)(0x424C0324UL))\r
+#define bFM3_QPRC0_QCR_AES0                    *((volatile unsigned int*)(0x424C0328UL))\r
+#define bFM3_QPRC0_QCR_AES1                    *((volatile unsigned int*)(0x424C032CUL))\r
+#define bFM3_QPRC0_QCR_BES0                    *((volatile unsigned int*)(0x424C0330UL))\r
+#define bFM3_QPRC0_QCR_BES1                    *((volatile unsigned int*)(0x424C0334UL))\r
+#define bFM3_QPRC0_QCR_CGE0                    *((volatile unsigned int*)(0x424C0338UL))\r
+#define bFM3_QPRC0_QCR_CGE1                    *((volatile unsigned int*)(0x424C033CUL))\r
+#define bFM3_QPRC0_QCRL_PCM0                   *((volatile unsigned int*)(0x424C0300UL))\r
+#define bFM3_QPRC0_QCRL_PCM1                   *((volatile unsigned int*)(0x424C0304UL))\r
+#define bFM3_QPRC0_QCRL_RCM0                   *((volatile unsigned int*)(0x424C0308UL))\r
+#define bFM3_QPRC0_QCRL_RCM1                   *((volatile unsigned int*)(0x424C030CUL))\r
+#define bFM3_QPRC0_QCRL_PSTP                   *((volatile unsigned int*)(0x424C0310UL))\r
+#define bFM3_QPRC0_QCRL_CGSC                   *((volatile unsigned int*)(0x424C0314UL))\r
+#define bFM3_QPRC0_QCRL_RSEL                   *((volatile unsigned int*)(0x424C0318UL))\r
+#define bFM3_QPRC0_QCRL_SWAP                   *((volatile unsigned int*)(0x424C031CUL))\r
+#define bFM3_QPRC0_QCRH_PCRM0                  *((volatile unsigned int*)(0x424C0320UL))\r
+#define bFM3_QPRC0_QCRH_PCRM1                  *((volatile unsigned int*)(0x424C0324UL))\r
+#define bFM3_QPRC0_QCRH_AES0                   *((volatile unsigned int*)(0x424C0328UL))\r
+#define bFM3_QPRC0_QCRH_AES1                   *((volatile unsigned int*)(0x424C032CUL))\r
+#define bFM3_QPRC0_QCRH_BES0                   *((volatile unsigned int*)(0x424C0330UL))\r
+#define bFM3_QPRC0_QCRH_BES1                   *((volatile unsigned int*)(0x424C0334UL))\r
+#define bFM3_QPRC0_QCRH_CGE0                   *((volatile unsigned int*)(0x424C0338UL))\r
+#define bFM3_QPRC0_QCRH_CGE1                   *((volatile unsigned int*)(0x424C033CUL))\r
+#define bFM3_QPRC0_QECR_ORNGMD                 *((volatile unsigned int*)(0x424C0380UL))\r
+#define bFM3_QPRC0_QECR_ORNGF                  *((volatile unsigned int*)(0x424C0384UL))\r
+#define bFM3_QPRC0_QECR_ORNGIE                 *((volatile unsigned int*)(0x424C0388UL))\r
+\r
+/* Quad position and revolution counter channel 1 registers */\r
+#define bFM3_QPRC1_QICR_QPCMIE                 *((volatile unsigned int*)(0x424C0A80UL))\r
+#define bFM3_QPRC1_QICR_QPCMF                  *((volatile unsigned int*)(0x424C0A84UL))\r
+#define bFM3_QPRC1_QICR_QPRCMIE                *((volatile unsigned int*)(0x424C0A88UL))\r
+#define bFM3_QPRC1_QICR_QPRCMF                 *((volatile unsigned int*)(0x424C0A8CUL))\r
+#define bFM3_QPRC1_QICR_OUZIE                  *((volatile unsigned int*)(0x424C0A90UL))\r
+#define bFM3_QPRC1_QICR_UFDF                   *((volatile unsigned int*)(0x424C0A94UL))\r
+#define bFM3_QPRC1_QICR_OFDF                   *((volatile unsigned int*)(0x424C0A98UL))\r
+#define bFM3_QPRC1_QICR_ZIIF                   *((volatile unsigned int*)(0x424C0A9CUL))\r
+#define bFM3_QPRC1_QICR_CDCIE                  *((volatile unsigned int*)(0x424C0AA0UL))\r
+#define bFM3_QPRC1_QICR_CDCF                   *((volatile unsigned int*)(0x424C0AA4UL))\r
+#define bFM3_QPRC1_QICR_DIRPC                  *((volatile unsigned int*)(0x424C0AA8UL))\r
+#define bFM3_QPRC1_QICR_DIROU                  *((volatile unsigned int*)(0x424C0AACUL))\r
+#define bFM3_QPRC1_QICR_QPCNRCMIE              *((volatile unsigned int*)(0x424C0AB0UL))\r
+#define bFM3_QPRC1_QICR_QPCNRCMF               *((volatile unsigned int*)(0x424C0AB4UL))\r
+#define bFM3_QPRC1_QICRL_QPCMIE                *((volatile unsigned int*)(0x424C0A80UL))\r
+#define bFM3_QPRC1_QICRL_QPCMF                 *((volatile unsigned int*)(0x424C0A84UL))\r
+#define bFM3_QPRC1_QICRL_QPRCMIE               *((volatile unsigned int*)(0x424C0A88UL))\r
+#define bFM3_QPRC1_QICRL_QPRCMF                *((volatile unsigned int*)(0x424C0A8CUL))\r
+#define bFM3_QPRC1_QICRL_OUZIE                 *((volatile unsigned int*)(0x424C0A90UL))\r
+#define bFM3_QPRC1_QICRL_UFDF                  *((volatile unsigned int*)(0x424C0A94UL))\r
+#define bFM3_QPRC1_QICRL_OFDF                  *((volatile unsigned int*)(0x424C0A98UL))\r
+#define bFM3_QPRC1_QICRL_ZIIF                  *((volatile unsigned int*)(0x424C0A9CUL))\r
+#define bFM3_QPRC1_QICRH_CDCIE                 *((volatile unsigned int*)(0x424C0AA0UL))\r
+#define bFM3_QPRC1_QICRH_CDCF                  *((volatile unsigned int*)(0x424C0AA4UL))\r
+#define bFM3_QPRC1_QICRH_DIRPC                 *((volatile unsigned int*)(0x424C0AA8UL))\r
+#define bFM3_QPRC1_QICRH_DIROU                 *((volatile unsigned int*)(0x424C0AACUL))\r
+#define bFM3_QPRC1_QICRH_QPCNRCMIE             *((volatile unsigned int*)(0x424C0AB0UL))\r
+#define bFM3_QPRC1_QICRH_QPCNRCMF              *((volatile unsigned int*)(0x424C0AB4UL))\r
+#define bFM3_QPRC1_QCR_PCM0                    *((volatile unsigned int*)(0x424C0B00UL))\r
+#define bFM3_QPRC1_QCR_PCM1                    *((volatile unsigned int*)(0x424C0B04UL))\r
+#define bFM3_QPRC1_QCR_RCM0                    *((volatile unsigned int*)(0x424C0B08UL))\r
+#define bFM3_QPRC1_QCR_RCM1                    *((volatile unsigned int*)(0x424C0B0CUL))\r
+#define bFM3_QPRC1_QCR_PSTP                    *((volatile unsigned int*)(0x424C0B10UL))\r
+#define bFM3_QPRC1_QCR_CGSC                    *((volatile unsigned int*)(0x424C0B14UL))\r
+#define bFM3_QPRC1_QCR_RSEL                    *((volatile unsigned int*)(0x424C0B18UL))\r
+#define bFM3_QPRC1_QCR_SWAP                    *((volatile unsigned int*)(0x424C0B1CUL))\r
+#define bFM3_QPRC1_QCR_PCRM0                   *((volatile unsigned int*)(0x424C0B20UL))\r
+#define bFM3_QPRC1_QCR_PCRM1                   *((volatile unsigned int*)(0x424C0B24UL))\r
+#define bFM3_QPRC1_QCR_AES0                    *((volatile unsigned int*)(0x424C0B28UL))\r
+#define bFM3_QPRC1_QCR_AES1                    *((volatile unsigned int*)(0x424C0B2CUL))\r
+#define bFM3_QPRC1_QCR_BES0                    *((volatile unsigned int*)(0x424C0B30UL))\r
+#define bFM3_QPRC1_QCR_BES1                    *((volatile unsigned int*)(0x424C0B34UL))\r
+#define bFM3_QPRC1_QCR_CGE0                    *((volatile unsigned int*)(0x424C0B38UL))\r
+#define bFM3_QPRC1_QCR_CGE1                    *((volatile unsigned int*)(0x424C0B3CUL))\r
+#define bFM3_QPRC1_QCRL_PCM0                   *((volatile unsigned int*)(0x424C0B00UL))\r
+#define bFM3_QPRC1_QCRL_PCM1                   *((volatile unsigned int*)(0x424C0B04UL))\r
+#define bFM3_QPRC1_QCRL_RCM0                   *((volatile unsigned int*)(0x424C0B08UL))\r
+#define bFM3_QPRC1_QCRL_RCM1                   *((volatile unsigned int*)(0x424C0B0CUL))\r
+#define bFM3_QPRC1_QCRL_PSTP                   *((volatile unsigned int*)(0x424C0B10UL))\r
+#define bFM3_QPRC1_QCRL_CGSC                   *((volatile unsigned int*)(0x424C0B14UL))\r
+#define bFM3_QPRC1_QCRL_RSEL                   *((volatile unsigned int*)(0x424C0B18UL))\r
+#define bFM3_QPRC1_QCRL_SWAP                   *((volatile unsigned int*)(0x424C0B1CUL))\r
+#define bFM3_QPRC1_QCRH_PCRM0                  *((volatile unsigned int*)(0x424C0B20UL))\r
+#define bFM3_QPRC1_QCRH_PCRM1                  *((volatile unsigned int*)(0x424C0B24UL))\r
+#define bFM3_QPRC1_QCRH_AES0                   *((volatile unsigned int*)(0x424C0B28UL))\r
+#define bFM3_QPRC1_QCRH_AES1                   *((volatile unsigned int*)(0x424C0B2CUL))\r
+#define bFM3_QPRC1_QCRH_BES0                   *((volatile unsigned int*)(0x424C0B30UL))\r
+#define bFM3_QPRC1_QCRH_BES1                   *((volatile unsigned int*)(0x424C0B34UL))\r
+#define bFM3_QPRC1_QCRH_CGE0                   *((volatile unsigned int*)(0x424C0B38UL))\r
+#define bFM3_QPRC1_QCRH_CGE1                   *((volatile unsigned int*)(0x424C0B3CUL))\r
+#define bFM3_QPRC1_QECR_ORNGMD                 *((volatile unsigned int*)(0x424C0B80UL))\r
+#define bFM3_QPRC1_QECR_ORNGF                  *((volatile unsigned int*)(0x424C0B84UL))\r
+#define bFM3_QPRC1_QECR_ORNGIE                 *((volatile unsigned int*)(0x424C0B88UL))\r
+\r
+/* 12-bit ADC unit 0 registers */\r
+#define bFM3_ADC0_ADSR_SCS                     *((volatile unsigned int*)(0x424E0000UL))\r
+#define bFM3_ADC0_ADSR_PCS                     *((volatile unsigned int*)(0x424E0004UL))\r
+#define bFM3_ADC0_ADSR_PCNS                    *((volatile unsigned int*)(0x424E0008UL))\r
+#define bFM3_ADC0_ADSR_FDAS                    *((volatile unsigned int*)(0x424E0018UL))\r
+#define bFM3_ADC0_ADSR_ADSTP                   *((volatile unsigned int*)(0x424E001CUL))\r
+#define bFM3_ADC0_ADCR_OVRIE                   *((volatile unsigned int*)(0x424E0020UL))\r
+#define bFM3_ADC0_ADCR_CMPIE                   *((volatile unsigned int*)(0x424E0024UL))\r
+#define bFM3_ADC0_ADCR_PCIE                    *((volatile unsigned int*)(0x424E0028UL))\r
+#define bFM3_ADC0_ADCR_SCIE                    *((volatile unsigned int*)(0x424E002CUL))\r
+#define bFM3_ADC0_ADCR_CMPIF                   *((volatile unsigned int*)(0x424E0034UL))\r
+#define bFM3_ADC0_ADCR_PCIF                    *((volatile unsigned int*)(0x424E0038UL))\r
+#define bFM3_ADC0_ADCR_SCIF                    *((volatile unsigned int*)(0x424E003CUL))\r
+#define bFM3_ADC0_SFNS_SFS0                    *((volatile unsigned int*)(0x424E0100UL))\r
+#define bFM3_ADC0_SFNS_SFS1                    *((volatile unsigned int*)(0x424E0104UL))\r
+#define bFM3_ADC0_SFNS_SFS2                    *((volatile unsigned int*)(0x424E0108UL))\r
+#define bFM3_ADC0_SFNS_SFS3                    *((volatile unsigned int*)(0x424E010CUL))\r
+#define bFM3_ADC0_SCCR_SSTR                    *((volatile unsigned int*)(0x424E0120UL))\r
+#define bFM3_ADC0_SCCR_SHEN                    *((volatile unsigned int*)(0x424E0124UL))\r
+#define bFM3_ADC0_SCCR_RPT                     *((volatile unsigned int*)(0x424E0128UL))\r
+#define bFM3_ADC0_SCCR_SFCLR                   *((volatile unsigned int*)(0x424E0130UL))\r
+#define bFM3_ADC0_SCCR_SOVR                    *((volatile unsigned int*)(0x424E0134UL))\r
+#define bFM3_ADC0_SCCR_SFUL                    *((volatile unsigned int*)(0x424E0138UL))\r
+#define bFM3_ADC0_SCCR_SEMP                    *((volatile unsigned int*)(0x424E013CUL))\r
+#define bFM3_ADC0_SCFD_SC0                     *((volatile unsigned int*)(0x424E0180UL))\r
+#define bFM3_ADC0_SCFD_SC1                     *((volatile unsigned int*)(0x424E0184UL))\r
+#define bFM3_ADC0_SCFD_SC2                     *((volatile unsigned int*)(0x424E0188UL))\r
+#define bFM3_ADC0_SCFD_SC3                     *((volatile unsigned int*)(0x424E018CUL))\r
+#define bFM3_ADC0_SCFD_SC4                     *((volatile unsigned int*)(0x424E0190UL))\r
+#define bFM3_ADC0_SCFD_RS0                     *((volatile unsigned int*)(0x424E01A0UL))\r
+#define bFM3_ADC0_SCFD_RS1                     *((volatile unsigned int*)(0x424E01A4UL))\r
+#define bFM3_ADC0_SCFD_INVL                    *((volatile unsigned int*)(0x424E01B0UL))\r
+#define bFM3_ADC0_SCFD_SD0                     *((volatile unsigned int*)(0x424E01D0UL))\r
+#define bFM3_ADC0_SCFD_SD1                     *((volatile unsigned int*)(0x424E01D4UL))\r
+#define bFM3_ADC0_SCFD_SD2                     *((volatile unsigned int*)(0x424E01D8UL))\r
+#define bFM3_ADC0_SCFD_SD3                     *((volatile unsigned int*)(0x424E01DCUL))\r
+#define bFM3_ADC0_SCFD_SD4                     *((volatile unsigned int*)(0x424E01E0UL))\r
+#define bFM3_ADC0_SCFD_SD5                     *((volatile unsigned int*)(0x424E01E4UL))\r
+#define bFM3_ADC0_SCFD_SD6                     *((volatile unsigned int*)(0x424E01E8UL))\r
+#define bFM3_ADC0_SCFD_SD7                     *((volatile unsigned int*)(0x424E01ECUL))\r
+#define bFM3_ADC0_SCFD_SD8                     *((volatile unsigned int*)(0x424E01F0UL))\r
+#define bFM3_ADC0_SCFD_SD9                     *((volatile unsigned int*)(0x424E01F4UL))\r
+#define bFM3_ADC0_SCFD_SD10                    *((volatile unsigned int*)(0x424E01F8UL))\r
+#define bFM3_ADC0_SCFD_SD11                    *((volatile unsigned int*)(0x424E01FCUL))\r
+#define bFM3_ADC0_SCFDL_SC0                    *((volatile unsigned int*)(0x424E0180UL))\r
+#define bFM3_ADC0_SCFDL_SC1                    *((volatile unsigned int*)(0x424E0184UL))\r
+#define bFM3_ADC0_SCFDL_SC2                    *((volatile unsigned int*)(0x424E0188UL))\r
+#define bFM3_ADC0_SCFDL_SC3                    *((volatile unsigned int*)(0x424E018CUL))\r
+#define bFM3_ADC0_SCFDL_SC4                    *((volatile unsigned int*)(0x424E0190UL))\r
+#define bFM3_ADC0_SCFDL_RS0                    *((volatile unsigned int*)(0x424E01A0UL))\r
+#define bFM3_ADC0_SCFDL_RS1                    *((volatile unsigned int*)(0x424E01A4UL))\r
+#define bFM3_ADC0_SCFDL_INVL                   *((volatile unsigned int*)(0x424E01B0UL))\r
+#define bFM3_ADC0_SCFDH_SD0                    *((volatile unsigned int*)(0x424E01D0UL))\r
+#define bFM3_ADC0_SCFDH_SD1                    *((volatile unsigned int*)(0x424E01D4UL))\r
+#define bFM3_ADC0_SCFDH_SD2                    *((volatile unsigned int*)(0x424E01D8UL))\r
+#define bFM3_ADC0_SCFDH_SD3                    *((volatile unsigned int*)(0x424E01DCUL))\r
+#define bFM3_ADC0_SCFDH_SD4                    *((volatile unsigned int*)(0x424E01E0UL))\r
+#define bFM3_ADC0_SCFDH_SD5                    *((volatile unsigned int*)(0x424E01E4UL))\r
+#define bFM3_ADC0_SCFDH_SD6                    *((volatile unsigned int*)(0x424E01E8UL))\r
+#define bFM3_ADC0_SCFDH_SD7                    *((volatile unsigned int*)(0x424E01ECUL))\r
+#define bFM3_ADC0_SCFDH_SD8                    *((volatile unsigned int*)(0x424E01F0UL))\r
+#define bFM3_ADC0_SCFDH_SD9                    *((volatile unsigned int*)(0x424E01F4UL))\r
+#define bFM3_ADC0_SCFDH_SD10                   *((volatile unsigned int*)(0x424E01F8UL))\r
+#define bFM3_ADC0_SCFDH_SD11                   *((volatile unsigned int*)(0x424E01FCUL))\r
+#define bFM3_ADC0_SCIS23_AN16                  *((volatile unsigned int*)(0x424E0200UL))\r
+#define bFM3_ADC0_SCIS23_AN17                  *((volatile unsigned int*)(0x424E0204UL))\r
+#define bFM3_ADC0_SCIS23_AN18                  *((volatile unsigned int*)(0x424E0208UL))\r
+#define bFM3_ADC0_SCIS23_AN19                  *((volatile unsigned int*)(0x424E020CUL))\r
+#define bFM3_ADC0_SCIS23_AN20                  *((volatile unsigned int*)(0x424E0210UL))\r
+#define bFM3_ADC0_SCIS23_AN21                  *((volatile unsigned int*)(0x424E0214UL))\r
+#define bFM3_ADC0_SCIS23_AN22                  *((volatile unsigned int*)(0x424E0218UL))\r
+#define bFM3_ADC0_SCIS23_AN23                  *((volatile unsigned int*)(0x424E021CUL))\r
+#define bFM3_ADC0_SCIS23_AN24                  *((volatile unsigned int*)(0x424E0220UL))\r
+#define bFM3_ADC0_SCIS23_AN25                  *((volatile unsigned int*)(0x424E0224UL))\r
+#define bFM3_ADC0_SCIS23_AN26                  *((volatile unsigned int*)(0x424E0228UL))\r
+#define bFM3_ADC0_SCIS23_AN27                  *((volatile unsigned int*)(0x424E022CUL))\r
+#define bFM3_ADC0_SCIS23_AN28                  *((volatile unsigned int*)(0x424E0230UL))\r
+#define bFM3_ADC0_SCIS23_AN29                  *((volatile unsigned int*)(0x424E0234UL))\r
+#define bFM3_ADC0_SCIS23_AN30                  *((volatile unsigned int*)(0x424E0238UL))\r
+#define bFM3_ADC0_SCIS23_AN31                  *((volatile unsigned int*)(0x424E023CUL))\r
+#define bFM3_ADC0_SCIS2_AN16                   *((volatile unsigned int*)(0x424E0200UL))\r
+#define bFM3_ADC0_SCIS2_AN17                   *((volatile unsigned int*)(0x424E0204UL))\r
+#define bFM3_ADC0_SCIS2_AN18                   *((volatile unsigned int*)(0x424E0208UL))\r
+#define bFM3_ADC0_SCIS2_AN19                   *((volatile unsigned int*)(0x424E020CUL))\r
+#define bFM3_ADC0_SCIS2_AN20                   *((volatile unsigned int*)(0x424E0210UL))\r
+#define bFM3_ADC0_SCIS2_AN21                   *((volatile unsigned int*)(0x424E0214UL))\r
+#define bFM3_ADC0_SCIS2_AN22                   *((volatile unsigned int*)(0x424E0218UL))\r
+#define bFM3_ADC0_SCIS2_AN23                   *((volatile unsigned int*)(0x424E021CUL))\r
+#define bFM3_ADC0_SCIS3_AN24                   *((volatile unsigned int*)(0x424E0220UL))\r
+#define bFM3_ADC0_SCIS3_AN25                   *((volatile unsigned int*)(0x424E0224UL))\r
+#define bFM3_ADC0_SCIS3_AN26                   *((volatile unsigned int*)(0x424E0228UL))\r
+#define bFM3_ADC0_SCIS3_AN27                   *((volatile unsigned int*)(0x424E022CUL))\r
+#define bFM3_ADC0_SCIS3_AN28                   *((volatile unsigned int*)(0x424E0230UL))\r
+#define bFM3_ADC0_SCIS3_AN29                   *((volatile unsigned int*)(0x424E0234UL))\r
+#define bFM3_ADC0_SCIS3_AN30                   *((volatile unsigned int*)(0x424E0238UL))\r
+#define bFM3_ADC0_SCIS3_AN31                   *((volatile unsigned int*)(0x424E023CUL))\r
+#define bFM3_ADC0_SCIS01_AN0                   *((volatile unsigned int*)(0x424E0280UL))\r
+#define bFM3_ADC0_SCIS01_AN1                   *((volatile unsigned int*)(0x424E0284UL))\r
+#define bFM3_ADC0_SCIS01_AN2                   *((volatile unsigned int*)(0x424E0288UL))\r
+#define bFM3_ADC0_SCIS01_AN3                   *((volatile unsigned int*)(0x424E028CUL))\r
+#define bFM3_ADC0_SCIS01_AN4                   *((volatile unsigned int*)(0x424E0290UL))\r
+#define bFM3_ADC0_SCIS01_AN5                   *((volatile unsigned int*)(0x424E0294UL))\r
+#define bFM3_ADC0_SCIS01_AN6                   *((volatile unsigned int*)(0x424E0298UL))\r
+#define bFM3_ADC0_SCIS01_AN7                   *((volatile unsigned int*)(0x424E029CUL))\r
+#define bFM3_ADC0_SCIS01_AN8                   *((volatile unsigned int*)(0x424E02A0UL))\r
+#define bFM3_ADC0_SCIS01_AN9                   *((volatile unsigned int*)(0x424E02A4UL))\r
+#define bFM3_ADC0_SCIS01_AN10                  *((volatile unsigned int*)(0x424E02A8UL))\r
+#define bFM3_ADC0_SCIS01_AN11                  *((volatile unsigned int*)(0x424E02ACUL))\r
+#define bFM3_ADC0_SCIS01_AN12                  *((volatile unsigned int*)(0x424E02B0UL))\r
+#define bFM3_ADC0_SCIS01_AN13                  *((volatile unsigned int*)(0x424E02B4UL))\r
+#define bFM3_ADC0_SCIS01_AN14                  *((volatile unsigned int*)(0x424E02B8UL))\r
+#define bFM3_ADC0_SCIS01_AN15                  *((volatile unsigned int*)(0x424E02BCUL))\r
+#define bFM3_ADC0_SCIS0_AN0                    *((volatile unsigned int*)(0x424E0280UL))\r
+#define bFM3_ADC0_SCIS0_AN1                    *((volatile unsigned int*)(0x424E0284UL))\r
+#define bFM3_ADC0_SCIS0_AN2                    *((volatile unsigned int*)(0x424E0288UL))\r
+#define bFM3_ADC0_SCIS0_AN3                    *((volatile unsigned int*)(0x424E028CUL))\r
+#define bFM3_ADC0_SCIS0_AN4                    *((volatile unsigned int*)(0x424E0290UL))\r
+#define bFM3_ADC0_SCIS0_AN5                    *((volatile unsigned int*)(0x424E0294UL))\r
+#define bFM3_ADC0_SCIS0_AN6                    *((volatile unsigned int*)(0x424E0298UL))\r
+#define bFM3_ADC0_SCIS0_AN7                    *((volatile unsigned int*)(0x424E029CUL))\r
+#define bFM3_ADC0_SCIS1_AN8                    *((volatile unsigned int*)(0x424E02A0UL))\r
+#define bFM3_ADC0_SCIS1_AN9                    *((volatile unsigned int*)(0x424E02A4UL))\r
+#define bFM3_ADC0_SCIS1_AN10                   *((volatile unsigned int*)(0x424E02A8UL))\r
+#define bFM3_ADC0_SCIS1_AN11                   *((volatile unsigned int*)(0x424E02ACUL))\r
+#define bFM3_ADC0_SCIS1_AN12                   *((volatile unsigned int*)(0x424E02B0UL))\r
+#define bFM3_ADC0_SCIS1_AN13                   *((volatile unsigned int*)(0x424E02B4UL))\r
+#define bFM3_ADC0_SCIS1_AN14                   *((volatile unsigned int*)(0x424E02B8UL))\r
+#define bFM3_ADC0_SCIS1_AN15                   *((volatile unsigned int*)(0x424E02BCUL))\r
+#define bFM3_ADC0_PFNS_PFS0                    *((volatile unsigned int*)(0x424E0300UL))\r
+#define bFM3_ADC0_PFNS_PFS1                    *((volatile unsigned int*)(0x424E0304UL))\r
+#define bFM3_ADC0_PFNS_TEST0                   *((volatile unsigned int*)(0x424E0310UL))\r
+#define bFM3_ADC0_PFNS_TEST1                   *((volatile unsigned int*)(0x424E0314UL))\r
+#define bFM3_ADC0_PCCR_PSTR                    *((volatile unsigned int*)(0x424E0320UL))\r
+#define bFM3_ADC0_PCCR_PHEN                    *((volatile unsigned int*)(0x424E0324UL))\r
+#define bFM3_ADC0_PCCR_PEEN                    *((volatile unsigned int*)(0x424E0328UL))\r
+#define bFM3_ADC0_PCCR_ESCE                    *((volatile unsigned int*)(0x424E032CUL))\r
+#define bFM3_ADC0_PCCR_PFCLR                   *((volatile unsigned int*)(0x424E0330UL))\r
+#define bFM3_ADC0_PCCR_POVR                    *((volatile unsigned int*)(0x424E0334UL))\r
+#define bFM3_ADC0_PCCR_PFUL                    *((volatile unsigned int*)(0x424E0338UL))\r
+#define bFM3_ADC0_PCCR_PEMP                    *((volatile unsigned int*)(0x424E033CUL))\r
+#define bFM3_ADC0_PCFD_PC0                     *((volatile unsigned int*)(0x424E0380UL))\r
+#define bFM3_ADC0_PCFD_PC1                     *((volatile unsigned int*)(0x424E0384UL))\r
+#define bFM3_ADC0_PCFD_PC2                     *((volatile unsigned int*)(0x424E0388UL))\r
+#define bFM3_ADC0_PCFD_PC3                     *((volatile unsigned int*)(0x424E038CUL))\r
+#define bFM3_ADC0_PCFD_PC4                     *((volatile unsigned int*)(0x424E0390UL))\r
+#define bFM3_ADC0_PCFD_RS0                     *((volatile unsigned int*)(0x424E03A0UL))\r
+#define bFM3_ADC0_PCFD_RS1                     *((volatile unsigned int*)(0x424E03A4UL))\r
+#define bFM3_ADC0_PCFD_RS2                     *((volatile unsigned int*)(0x424E03A8UL))\r
+#define bFM3_ADC0_PCFD_INVL                    *((volatile unsigned int*)(0x424E03B0UL))\r
+#define bFM3_ADC0_PCFD_PD0                     *((volatile unsigned int*)(0x424E03D0UL))\r
+#define bFM3_ADC0_PCFD_PD1                     *((volatile unsigned int*)(0x424E03D4UL))\r
+#define bFM3_ADC0_PCFD_PD2                     *((volatile unsigned int*)(0x424E03D8UL))\r
+#define bFM3_ADC0_PCFD_PD3                     *((volatile unsigned int*)(0x424E03DCUL))\r
+#define bFM3_ADC0_PCFD_PD4                     *((volatile unsigned int*)(0x424E03E0UL))\r
+#define bFM3_ADC0_PCFD_PD5                     *((volatile unsigned int*)(0x424E03E4UL))\r
+#define bFM3_ADC0_PCFD_PD6                     *((volatile unsigned int*)(0x424E03E8UL))\r
+#define bFM3_ADC0_PCFD_PD7                     *((volatile unsigned int*)(0x424E03ECUL))\r
+#define bFM3_ADC0_PCFD_PD8                     *((volatile unsigned int*)(0x424E03F0UL))\r
+#define bFM3_ADC0_PCFD_PD9                     *((volatile unsigned int*)(0x424E03F4UL))\r
+#define bFM3_ADC0_PCFD_PD10                    *((volatile unsigned int*)(0x424E03F8UL))\r
+#define bFM3_ADC0_PCFD_PD11                    *((volatile unsigned int*)(0x424E03FCUL))\r
+#define bFM3_ADC0_PCFDL_PC0                    *((volatile unsigned int*)(0x424E0380UL))\r
+#define bFM3_ADC0_PCFDL_PC1                    *((volatile unsigned int*)(0x424E0384UL))\r
+#define bFM3_ADC0_PCFDL_PC2                    *((volatile unsigned int*)(0x424E0388UL))\r
+#define bFM3_ADC0_PCFDL_PC3                    *((volatile unsigned int*)(0x424E038CUL))\r
+#define bFM3_ADC0_PCFDL_PC4                    *((volatile unsigned int*)(0x424E0390UL))\r
+#define bFM3_ADC0_PCFDL_RS0                    *((volatile unsigned int*)(0x424E03A0UL))\r
+#define bFM3_ADC0_PCFDL_RS1                    *((volatile unsigned int*)(0x424E03A4UL))\r
+#define bFM3_ADC0_PCFDL_RS2                    *((volatile unsigned int*)(0x424E03A8UL))\r
+#define bFM3_ADC0_PCFDL_INVL                   *((volatile unsigned int*)(0x424E03B0UL))\r
+#define bFM3_ADC0_PCFDH_PD0                    *((volatile unsigned int*)(0x424E03D0UL))\r
+#define bFM3_ADC0_PCFDH_PD1                    *((volatile unsigned int*)(0x424E03D4UL))\r
+#define bFM3_ADC0_PCFDH_PD2                    *((volatile unsigned int*)(0x424E03D8UL))\r
+#define bFM3_ADC0_PCFDH_PD3                    *((volatile unsigned int*)(0x424E03DCUL))\r
+#define bFM3_ADC0_PCFDH_PD4                    *((volatile unsigned int*)(0x424E03E0UL))\r
+#define bFM3_ADC0_PCFDH_PD5                    *((volatile unsigned int*)(0x424E03E4UL))\r
+#define bFM3_ADC0_PCFDH_PD6                    *((volatile unsigned int*)(0x424E03E8UL))\r
+#define bFM3_ADC0_PCFDH_PD7                    *((volatile unsigned int*)(0x424E03ECUL))\r
+#define bFM3_ADC0_PCFDH_PD8                    *((volatile unsigned int*)(0x424E03F0UL))\r
+#define bFM3_ADC0_PCFDH_PD9                    *((volatile unsigned int*)(0x424E03F4UL))\r
+#define bFM3_ADC0_PCFDH_PD10                   *((volatile unsigned int*)(0x424E03F8UL))\r
+#define bFM3_ADC0_PCFDH_PD11                   *((volatile unsigned int*)(0x424E03FCUL))\r
+#define bFM3_ADC0_PCIS_P1A0                    *((volatile unsigned int*)(0x424E0400UL))\r
+#define bFM3_ADC0_PCIS_P1A1                    *((volatile unsigned int*)(0x424E0404UL))\r
+#define bFM3_ADC0_PCIS_P1A2                    *((volatile unsigned int*)(0x424E0408UL))\r
+#define bFM3_ADC0_PCIS_P2A0                    *((volatile unsigned int*)(0x424E040CUL))\r
+#define bFM3_ADC0_PCIS_P2A1                    *((volatile unsigned int*)(0x424E0410UL))\r
+#define bFM3_ADC0_PCIS_P2A2                    *((volatile unsigned int*)(0x424E0414UL))\r
+#define bFM3_ADC0_PCIS_P2A3                    *((volatile unsigned int*)(0x424E0418UL))\r
+#define bFM3_ADC0_PCIS_P2A4                    *((volatile unsigned int*)(0x424E041CUL))\r
+#define bFM3_ADC0_CMPCR_CCH0                   *((volatile unsigned int*)(0x424E0480UL))\r
+#define bFM3_ADC0_CMPCR_CCH1                   *((volatile unsigned int*)(0x424E0484UL))\r
+#define bFM3_ADC0_CMPCR_CCH2                   *((volatile unsigned int*)(0x424E0488UL))\r
+#define bFM3_ADC0_CMPCR_CCH3                   *((volatile unsigned int*)(0x424E048CUL))\r
+#define bFM3_ADC0_CMPCR_CCH4                   *((volatile unsigned int*)(0x424E0490UL))\r
+#define bFM3_ADC0_CMPCR_CMD0                   *((volatile unsigned int*)(0x424E0494UL))\r
+#define bFM3_ADC0_CMPCR_CMD1                   *((volatile unsigned int*)(0x424E0498UL))\r
+#define bFM3_ADC0_CMPCR_CMPEN                  *((volatile unsigned int*)(0x424E049CUL))\r
+#define bFM3_ADC0_CMPD_CMAD2                   *((volatile unsigned int*)(0x424E04D8UL))\r
+#define bFM3_ADC0_CMPD_CMAD3                   *((volatile unsigned int*)(0x424E04DCUL))\r
+#define bFM3_ADC0_CMPD_CMAD4                   *((volatile unsigned int*)(0x424E04E0UL))\r
+#define bFM3_ADC0_CMPD_CMAD5                   *((volatile unsigned int*)(0x424E04E4UL))\r
+#define bFM3_ADC0_CMPD_CMAD6                   *((volatile unsigned int*)(0x424E04E8UL))\r
+#define bFM3_ADC0_CMPD_CMAD7                   *((volatile unsigned int*)(0x424E04ECUL))\r
+#define bFM3_ADC0_CMPD_CMAD8                   *((volatile unsigned int*)(0x424E04F0UL))\r
+#define bFM3_ADC0_CMPD_CMAD9                   *((volatile unsigned int*)(0x424E04F4UL))\r
+#define bFM3_ADC0_CMPD_CMAD10                  *((volatile unsigned int*)(0x424E04F8UL))\r
+#define bFM3_ADC0_CMPD_CMAD11                  *((volatile unsigned int*)(0x424E04FCUL))\r
+#define bFM3_ADC0_ADSS23_TS16                  *((volatile unsigned int*)(0x424E0500UL))\r
+#define bFM3_ADC0_ADSS23_TS17                  *((volatile unsigned int*)(0x424E0504UL))\r
+#define bFM3_ADC0_ADSS23_TS18                  *((volatile unsigned int*)(0x424E0508UL))\r
+#define bFM3_ADC0_ADSS23_TS19                  *((volatile unsigned int*)(0x424E050CUL))\r
+#define bFM3_ADC0_ADSS23_TS20                  *((volatile unsigned int*)(0x424E0510UL))\r
+#define bFM3_ADC0_ADSS23_TS21                  *((volatile unsigned int*)(0x424E0514UL))\r
+#define bFM3_ADC0_ADSS23_TS22                  *((volatile unsigned int*)(0x424E0518UL))\r
+#define bFM3_ADC0_ADSS23_TS23                  *((volatile unsigned int*)(0x424E051CUL))\r
+#define bFM3_ADC0_ADSS23_TS24                  *((volatile unsigned int*)(0x424E0520UL))\r
+#define bFM3_ADC0_ADSS23_TS25                  *((volatile unsigned int*)(0x424E0524UL))\r
+#define bFM3_ADC0_ADSS23_TS26                  *((volatile unsigned int*)(0x424E0528UL))\r
+#define bFM3_ADC0_ADSS23_TS27                  *((volatile unsigned int*)(0x424E052CUL))\r
+#define bFM3_ADC0_ADSS23_TS28                  *((volatile unsigned int*)(0x424E0530UL))\r
+#define bFM3_ADC0_ADSS23_TS29                  *((volatile unsigned int*)(0x424E0534UL))\r
+#define bFM3_ADC0_ADSS23_TS30                  *((volatile unsigned int*)(0x424E0538UL))\r
+#define bFM3_ADC0_ADSS23_TS31                  *((volatile unsigned int*)(0x424E053CUL))\r
+#define bFM3_ADC0_ADSS2_TS16                   *((volatile unsigned int*)(0x424E0500UL))\r
+#define bFM3_ADC0_ADSS2_TS17                   *((volatile unsigned int*)(0x424E0504UL))\r
+#define bFM3_ADC0_ADSS2_TS18                   *((volatile unsigned int*)(0x424E0508UL))\r
+#define bFM3_ADC0_ADSS2_TS19                   *((volatile unsigned int*)(0x424E050CUL))\r
+#define bFM3_ADC0_ADSS2_TS20                   *((volatile unsigned int*)(0x424E0510UL))\r
+#define bFM3_ADC0_ADSS2_TS21                   *((volatile unsigned int*)(0x424E0514UL))\r
+#define bFM3_ADC0_ADSS2_TS22                   *((volatile unsigned int*)(0x424E0518UL))\r
+#define bFM3_ADC0_ADSS2_TS23                   *((volatile unsigned int*)(0x424E051CUL))\r
+#define bFM3_ADC0_ADSS3_TS24                   *((volatile unsigned int*)(0x424E0520UL))\r
+#define bFM3_ADC0_ADSS3_TS25                   *((volatile unsigned int*)(0x424E0524UL))\r
+#define bFM3_ADC0_ADSS3_TS26                   *((volatile unsigned int*)(0x424E0528UL))\r
+#define bFM3_ADC0_ADSS3_TS27                   *((volatile unsigned int*)(0x424E052CUL))\r
+#define bFM3_ADC0_ADSS3_TS28                   *((volatile unsigned int*)(0x424E0530UL))\r
+#define bFM3_ADC0_ADSS3_TS29                   *((volatile unsigned int*)(0x424E0534UL))\r
+#define bFM3_ADC0_ADSS3_TS30                   *((volatile unsigned int*)(0x424E0538UL))\r
+#define bFM3_ADC0_ADSS3_TS31                   *((volatile unsigned int*)(0x424E053CUL))\r
+#define bFM3_ADC0_ADSS01_TS0                   *((volatile unsigned int*)(0x424E0580UL))\r
+#define bFM3_ADC0_ADSS01_TS1                   *((volatile unsigned int*)(0x424E0584UL))\r
+#define bFM3_ADC0_ADSS01_TS2                   *((volatile unsigned int*)(0x424E0588UL))\r
+#define bFM3_ADC0_ADSS01_TS3                   *((volatile unsigned int*)(0x424E058CUL))\r
+#define bFM3_ADC0_ADSS01_TS4                   *((volatile unsigned int*)(0x424E0590UL))\r
+#define bFM3_ADC0_ADSS01_TS5                   *((volatile unsigned int*)(0x424E0594UL))\r
+#define bFM3_ADC0_ADSS01_TS6                   *((volatile unsigned int*)(0x424E0598UL))\r
+#define bFM3_ADC0_ADSS01_TS7                   *((volatile unsigned int*)(0x424E059CUL))\r
+#define bFM3_ADC0_ADSS01_TS8                   *((volatile unsigned int*)(0x424E05A0UL))\r
+#define bFM3_ADC0_ADSS01_TS9                   *((volatile unsigned int*)(0x424E05A4UL))\r
+#define bFM3_ADC0_ADSS01_TS10                  *((volatile unsigned int*)(0x424E05A8UL))\r
+#define bFM3_ADC0_ADSS01_TS11                  *((volatile unsigned int*)(0x424E05ACUL))\r
+#define bFM3_ADC0_ADSS01_TS12                  *((volatile unsigned int*)(0x424E05B0UL))\r
+#define bFM3_ADC0_ADSS01_TS13                  *((volatile unsigned int*)(0x424E05B4UL))\r
+#define bFM3_ADC0_ADSS01_TS14                  *((volatile unsigned int*)(0x424E05B8UL))\r
+#define bFM3_ADC0_ADSS01_TS15                  *((volatile unsigned int*)(0x424E05BCUL))\r
+#define bFM3_ADC0_ADSS0_TS0                    *((volatile unsigned int*)(0x424E0580UL))\r
+#define bFM3_ADC0_ADSS0_TS1                    *((volatile unsigned int*)(0x424E0584UL))\r
+#define bFM3_ADC0_ADSS0_TS2                    *((volatile unsigned int*)(0x424E0588UL))\r
+#define bFM3_ADC0_ADSS0_TS3                    *((volatile unsigned int*)(0x424E058CUL))\r
+#define bFM3_ADC0_ADSS0_TS4                    *((volatile unsigned int*)(0x424E0590UL))\r
+#define bFM3_ADC0_ADSS0_TS5                    *((volatile unsigned int*)(0x424E0594UL))\r
+#define bFM3_ADC0_ADSS0_TS6                    *((volatile unsigned int*)(0x424E0598UL))\r
+#define bFM3_ADC0_ADSS0_TS7                    *((volatile unsigned int*)(0x424E059CUL))\r
+#define bFM3_ADC0_ADSS1_TS8                    *((volatile unsigned int*)(0x424E05A0UL))\r
+#define bFM3_ADC0_ADSS1_TS9                    *((volatile unsigned int*)(0x424E05A4UL))\r
+#define bFM3_ADC0_ADSS1_TS10                   *((volatile unsigned int*)(0x424E05A8UL))\r
+#define bFM3_ADC0_ADSS1_TS11                   *((volatile unsigned int*)(0x424E05ACUL))\r
+#define bFM3_ADC0_ADSS1_TS12                   *((volatile unsigned int*)(0x424E05B0UL))\r
+#define bFM3_ADC0_ADSS1_TS13                   *((volatile unsigned int*)(0x424E05B4UL))\r
+#define bFM3_ADC0_ADSS1_TS14                   *((volatile unsigned int*)(0x424E05B8UL))\r
+#define bFM3_ADC0_ADSS1_TS15                   *((volatile unsigned int*)(0x424E05BCUL))\r
+#define bFM3_ADC0_ADST01_ST10                  *((volatile unsigned int*)(0x424E0600UL))\r
+#define bFM3_ADC0_ADST01_ST11                  *((volatile unsigned int*)(0x424E0604UL))\r
+#define bFM3_ADC0_ADST01_ST12                  *((volatile unsigned int*)(0x424E0608UL))\r
+#define bFM3_ADC0_ADST01_ST13                  *((volatile unsigned int*)(0x424E060CUL))\r
+#define bFM3_ADC0_ADST01_ST14                  *((volatile unsigned int*)(0x424E0610UL))\r
+#define bFM3_ADC0_ADST01_STX10                 *((volatile unsigned int*)(0x424E0614UL))\r
+#define bFM3_ADC0_ADST01_STX11                 *((volatile unsigned int*)(0x424E0618UL))\r
+#define bFM3_ADC0_ADST01_STX12                 *((volatile unsigned int*)(0x424E061CUL))\r
+#define bFM3_ADC0_ADST01_ST00                  *((volatile unsigned int*)(0x424E0620UL))\r
+#define bFM3_ADC0_ADST01_ST01                  *((volatile unsigned int*)(0x424E0624UL))\r
+#define bFM3_ADC0_ADST01_ST02                  *((volatile unsigned int*)(0x424E0628UL))\r
+#define bFM3_ADC0_ADST01_ST03                  *((volatile unsigned int*)(0x424E062CUL))\r
+#define bFM3_ADC0_ADST01_ST04                  *((volatile unsigned int*)(0x424E0630UL))\r
+#define bFM3_ADC0_ADST01_STX00                 *((volatile unsigned int*)(0x424E0634UL))\r
+#define bFM3_ADC0_ADST01_STX01                 *((volatile unsigned int*)(0x424E0638UL))\r
+#define bFM3_ADC0_ADST01_STX02                 *((volatile unsigned int*)(0x424E063CUL))\r
+#define bFM3_ADC0_ADST1_ST10                   *((volatile unsigned int*)(0x424E0600UL))\r
+#define bFM3_ADC0_ADST1_ST11                   *((volatile unsigned int*)(0x424E0604UL))\r
+#define bFM3_ADC0_ADST1_ST12                   *((volatile unsigned int*)(0x424E0608UL))\r
+#define bFM3_ADC0_ADST1_ST13                   *((volatile unsigned int*)(0x424E060CUL))\r
+#define bFM3_ADC0_ADST1_ST14                   *((volatile unsigned int*)(0x424E0610UL))\r
+#define bFM3_ADC0_ADST1_STX10                  *((volatile unsigned int*)(0x424E0614UL))\r
+#define bFM3_ADC0_ADST1_STX11                  *((volatile unsigned int*)(0x424E0618UL))\r
+#define bFM3_ADC0_ADST1_STX12                  *((volatile unsigned int*)(0x424E061CUL))\r
+#define bFM3_ADC0_ADST0_ST00                   *((volatile unsigned int*)(0x424E0620UL))\r
+#define bFM3_ADC0_ADST0_ST01                   *((volatile unsigned int*)(0x424E0624UL))\r
+#define bFM3_ADC0_ADST0_ST02                   *((volatile unsigned int*)(0x424E0628UL))\r
+#define bFM3_ADC0_ADST0_ST03                   *((volatile unsigned int*)(0x424E062CUL))\r
+#define bFM3_ADC0_ADST0_ST04                   *((volatile unsigned int*)(0x424E0630UL))\r
+#define bFM3_ADC0_ADST0_STX00                  *((volatile unsigned int*)(0x424E0634UL))\r
+#define bFM3_ADC0_ADST0_STX01                  *((volatile unsigned int*)(0x424E0638UL))\r
+#define bFM3_ADC0_ADST0_STX02                  *((volatile unsigned int*)(0x424E063CUL))\r
+#define bFM3_ADC0_ADCT_CT0                     *((volatile unsigned int*)(0x424E0680UL))\r
+#define bFM3_ADC0_ADCT_CT1                     *((volatile unsigned int*)(0x424E0684UL))\r
+#define bFM3_ADC0_ADCT_CT2                     *((volatile unsigned int*)(0x424E0688UL))\r
+#define bFM3_ADC0_ADCT_CT3                     *((volatile unsigned int*)(0x424E068CUL))\r
+#define bFM3_ADC0_ADCT_CT4                     *((volatile unsigned int*)(0x424E0690UL))\r
+#define bFM3_ADC0_ADCT_CT5                     *((volatile unsigned int*)(0x424E0694UL))\r
+#define bFM3_ADC0_ADCT_CT6                     *((volatile unsigned int*)(0x424E0698UL))\r
+#define bFM3_ADC0_ADCT_CT7                     *((volatile unsigned int*)(0x424E069CUL))\r
+#define bFM3_ADC0_PRTSL_PRTSL0                 *((volatile unsigned int*)(0x424E0700UL))\r
+#define bFM3_ADC0_PRTSL_PRTSL1                 *((volatile unsigned int*)(0x424E0704UL))\r
+#define bFM3_ADC0_PRTSL_PRTSL2                 *((volatile unsigned int*)(0x424E0708UL))\r
+#define bFM3_ADC0_PRTSL_PRTSL3                 *((volatile unsigned int*)(0x424E070CUL))\r
+#define bFM3_ADC0_SCTSL_SCTSL0                 *((volatile unsigned int*)(0x424E0720UL))\r
+#define bFM3_ADC0_SCTSL_SCTSL1                 *((volatile unsigned int*)(0x424E0724UL))\r
+#define bFM3_ADC0_SCTSL_SCTSL2                 *((volatile unsigned int*)(0x424E0728UL))\r
+#define bFM3_ADC0_SCTSL_SCTSL3                 *((volatile unsigned int*)(0x424E072CUL))\r
+#define bFM3_ADC0_ADCEN_ENBL                   *((volatile unsigned int*)(0x424E0780UL))\r
+#define bFM3_ADC0_ADCEN_READY                  *((volatile unsigned int*)(0x424E0784UL))\r
+#define bFM3_ADC0_ADCEN_CYCLSL0                *((volatile unsigned int*)(0x424E0790UL))\r
+#define bFM3_ADC0_ADCEN_CYCLSL1                *((volatile unsigned int*)(0x424E0794UL))\r
+\r
+/* 12-bit ADC unit 1 registers */\r
+#define bFM3_ADC1_ADSR_SCS                     *((volatile unsigned int*)(0x424E2000UL))\r
+#define bFM3_ADC1_ADSR_PCS                     *((volatile unsigned int*)(0x424E2004UL))\r
+#define bFM3_ADC1_ADSR_PCNS                    *((volatile unsigned int*)(0x424E2008UL))\r
+#define bFM3_ADC1_ADSR_FDAS                    *((volatile unsigned int*)(0x424E2018UL))\r
+#define bFM3_ADC1_ADSR_ADSTP                   *((volatile unsigned int*)(0x424E201CUL))\r
+#define bFM3_ADC1_ADCR_OVRIE                   *((volatile unsigned int*)(0x424E2020UL))\r
+#define bFM3_ADC1_ADCR_CMPIE                   *((volatile unsigned int*)(0x424E2024UL))\r
+#define bFM3_ADC1_ADCR_PCIE                    *((volatile unsigned int*)(0x424E2028UL))\r
+#define bFM3_ADC1_ADCR_SCIE                    *((volatile unsigned int*)(0x424E202CUL))\r
+#define bFM3_ADC1_ADCR_CMPIF                   *((volatile unsigned int*)(0x424E2034UL))\r
+#define bFM3_ADC1_ADCR_PCIF                    *((volatile unsigned int*)(0x424E2038UL))\r
+#define bFM3_ADC1_ADCR_SCIF                    *((volatile unsigned int*)(0x424E203CUL))\r
+#define bFM3_ADC1_SFNS_SFS0                    *((volatile unsigned int*)(0x424E2100UL))\r
+#define bFM3_ADC1_SFNS_SFS1                    *((volatile unsigned int*)(0x424E2104UL))\r
+#define bFM3_ADC1_SFNS_SFS2                    *((volatile unsigned int*)(0x424E2108UL))\r
+#define bFM3_ADC1_SFNS_SFS3                    *((volatile unsigned int*)(0x424E210CUL))\r
+#define bFM3_ADC1_SCCR_SSTR                    *((volatile unsigned int*)(0x424E2120UL))\r
+#define bFM3_ADC1_SCCR_SHEN                    *((volatile unsigned int*)(0x424E2124UL))\r
+#define bFM3_ADC1_SCCR_RPT                     *((volatile unsigned int*)(0x424E2128UL))\r
+#define bFM3_ADC1_SCCR_SFCLR                   *((volatile unsigned int*)(0x424E2130UL))\r
+#define bFM3_ADC1_SCCR_SOVR                    *((volatile unsigned int*)(0x424E2134UL))\r
+#define bFM3_ADC1_SCCR_SFUL                    *((volatile unsigned int*)(0x424E2138UL))\r
+#define bFM3_ADC1_SCCR_SEMP                    *((volatile unsigned int*)(0x424E213CUL))\r
+#define bFM3_ADC1_SCFD_SC0                     *((volatile unsigned int*)(0x424E2180UL))\r
+#define bFM3_ADC1_SCFD_SC1                     *((volatile unsigned int*)(0x424E2184UL))\r
+#define bFM3_ADC1_SCFD_SC2                     *((volatile unsigned int*)(0x424E2188UL))\r
+#define bFM3_ADC1_SCFD_SC3                     *((volatile unsigned int*)(0x424E218CUL))\r
+#define bFM3_ADC1_SCFD_SC4                     *((volatile unsigned int*)(0x424E2190UL))\r
+#define bFM3_ADC1_SCFD_RS0                     *((volatile unsigned int*)(0x424E21A0UL))\r
+#define bFM3_ADC1_SCFD_RS1                     *((volatile unsigned int*)(0x424E21A4UL))\r
+#define bFM3_ADC1_SCFD_INVL                    *((volatile unsigned int*)(0x424E21B0UL))\r
+#define bFM3_ADC1_SCFD_SD0                     *((volatile unsigned int*)(0x424E21D0UL))\r
+#define bFM3_ADC1_SCFD_SD1                     *((volatile unsigned int*)(0x424E21D4UL))\r
+#define bFM3_ADC1_SCFD_SD2                     *((volatile unsigned int*)(0x424E21D8UL))\r
+#define bFM3_ADC1_SCFD_SD3                     *((volatile unsigned int*)(0x424E21DCUL))\r
+#define bFM3_ADC1_SCFD_SD4                     *((volatile unsigned int*)(0x424E21E0UL))\r
+#define bFM3_ADC1_SCFD_SD5                     *((volatile unsigned int*)(0x424E21E4UL))\r
+#define bFM3_ADC1_SCFD_SD6                     *((volatile unsigned int*)(0x424E21E8UL))\r
+#define bFM3_ADC1_SCFD_SD7                     *((volatile unsigned int*)(0x424E21ECUL))\r
+#define bFM3_ADC1_SCFD_SD8                     *((volatile unsigned int*)(0x424E21F0UL))\r
+#define bFM3_ADC1_SCFD_SD9                     *((volatile unsigned int*)(0x424E21F4UL))\r
+#define bFM3_ADC1_SCFD_SD10                    *((volatile unsigned int*)(0x424E21F8UL))\r
+#define bFM3_ADC1_SCFD_SD11                    *((volatile unsigned int*)(0x424E21FCUL))\r
+#define bFM3_ADC1_SCFDL_SC0                    *((volatile unsigned int*)(0x424E2180UL))\r
+#define bFM3_ADC1_SCFDL_SC1                    *((volatile unsigned int*)(0x424E2184UL))\r
+#define bFM3_ADC1_SCFDL_SC2                    *((volatile unsigned int*)(0x424E2188UL))\r
+#define bFM3_ADC1_SCFDL_SC3                    *((volatile unsigned int*)(0x424E218CUL))\r
+#define bFM3_ADC1_SCFDL_SC4                    *((volatile unsigned int*)(0x424E2190UL))\r
+#define bFM3_ADC1_SCFDL_RS0                    *((volatile unsigned int*)(0x424E21A0UL))\r
+#define bFM3_ADC1_SCFDL_RS1                    *((volatile unsigned int*)(0x424E21A4UL))\r
+#define bFM3_ADC1_SCFDL_INVL                   *((volatile unsigned int*)(0x424E21B0UL))\r
+#define bFM3_ADC1_SCFDH_SD0                    *((volatile unsigned int*)(0x424E21D0UL))\r
+#define bFM3_ADC1_SCFDH_SD1                    *((volatile unsigned int*)(0x424E21D4UL))\r
+#define bFM3_ADC1_SCFDH_SD2                    *((volatile unsigned int*)(0x424E21D8UL))\r
+#define bFM3_ADC1_SCFDH_SD3                    *((volatile unsigned int*)(0x424E21DCUL))\r
+#define bFM3_ADC1_SCFDH_SD4                    *((volatile unsigned int*)(0x424E21E0UL))\r
+#define bFM3_ADC1_SCFDH_SD5                    *((volatile unsigned int*)(0x424E21E4UL))\r
+#define bFM3_ADC1_SCFDH_SD6                    *((volatile unsigned int*)(0x424E21E8UL))\r
+#define bFM3_ADC1_SCFDH_SD7                    *((volatile unsigned int*)(0x424E21ECUL))\r
+#define bFM3_ADC1_SCFDH_SD8                    *((volatile unsigned int*)(0x424E21F0UL))\r
+#define bFM3_ADC1_SCFDH_SD9                    *((volatile unsigned int*)(0x424E21F4UL))\r
+#define bFM3_ADC1_SCFDH_SD10                   *((volatile unsigned int*)(0x424E21F8UL))\r
+#define bFM3_ADC1_SCFDH_SD11                   *((volatile unsigned int*)(0x424E21FCUL))\r
+#define bFM3_ADC1_SCIS23_AN16                  *((volatile unsigned int*)(0x424E2200UL))\r
+#define bFM3_ADC1_SCIS23_AN17                  *((volatile unsigned int*)(0x424E2204UL))\r
+#define bFM3_ADC1_SCIS23_AN18                  *((volatile unsigned int*)(0x424E2208UL))\r
+#define bFM3_ADC1_SCIS23_AN19                  *((volatile unsigned int*)(0x424E220CUL))\r
+#define bFM3_ADC1_SCIS23_AN20                  *((volatile unsigned int*)(0x424E2210UL))\r
+#define bFM3_ADC1_SCIS23_AN21                  *((volatile unsigned int*)(0x424E2214UL))\r
+#define bFM3_ADC1_SCIS23_AN22                  *((volatile unsigned int*)(0x424E2218UL))\r
+#define bFM3_ADC1_SCIS23_AN23                  *((volatile unsigned int*)(0x424E221CUL))\r
+#define bFM3_ADC1_SCIS23_AN24                  *((volatile unsigned int*)(0x424E2220UL))\r
+#define bFM3_ADC1_SCIS23_AN25                  *((volatile unsigned int*)(0x424E2224UL))\r
+#define bFM3_ADC1_SCIS23_AN26                  *((volatile unsigned int*)(0x424E2228UL))\r
+#define bFM3_ADC1_SCIS23_AN27                  *((volatile unsigned int*)(0x424E222CUL))\r
+#define bFM3_ADC1_SCIS23_AN28                  *((volatile unsigned int*)(0x424E2230UL))\r
+#define bFM3_ADC1_SCIS23_AN29                  *((volatile unsigned int*)(0x424E2234UL))\r
+#define bFM3_ADC1_SCIS23_AN30                  *((volatile unsigned int*)(0x424E2238UL))\r
+#define bFM3_ADC1_SCIS23_AN31                  *((volatile unsigned int*)(0x424E223CUL))\r
+#define bFM3_ADC1_SCIS2_AN16                   *((volatile unsigned int*)(0x424E2200UL))\r
+#define bFM3_ADC1_SCIS2_AN17                   *((volatile unsigned int*)(0x424E2204UL))\r
+#define bFM3_ADC1_SCIS2_AN18                   *((volatile unsigned int*)(0x424E2208UL))\r
+#define bFM3_ADC1_SCIS2_AN19                   *((volatile unsigned int*)(0x424E220CUL))\r
+#define bFM3_ADC1_SCIS2_AN20                   *((volatile unsigned int*)(0x424E2210UL))\r
+#define bFM3_ADC1_SCIS2_AN21                   *((volatile unsigned int*)(0x424E2214UL))\r
+#define bFM3_ADC1_SCIS2_AN22                   *((volatile unsigned int*)(0x424E2218UL))\r
+#define bFM3_ADC1_SCIS2_AN23                   *((volatile unsigned int*)(0x424E221CUL))\r
+#define bFM3_ADC1_SCIS3_AN24                   *((volatile unsigned int*)(0x424E2220UL))\r
+#define bFM3_ADC1_SCIS3_AN25                   *((volatile unsigned int*)(0x424E2224UL))\r
+#define bFM3_ADC1_SCIS3_AN26                   *((volatile unsigned int*)(0x424E2228UL))\r
+#define bFM3_ADC1_SCIS3_AN27                   *((volatile unsigned int*)(0x424E222CUL))\r
+#define bFM3_ADC1_SCIS3_AN28                   *((volatile unsigned int*)(0x424E2230UL))\r
+#define bFM3_ADC1_SCIS3_AN29                   *((volatile unsigned int*)(0x424E2234UL))\r
+#define bFM3_ADC1_SCIS3_AN30                   *((volatile unsigned int*)(0x424E2238UL))\r
+#define bFM3_ADC1_SCIS3_AN31                   *((volatile unsigned int*)(0x424E223CUL))\r
+#define bFM3_ADC1_SCIS01_AN0                   *((volatile unsigned int*)(0x424E2280UL))\r
+#define bFM3_ADC1_SCIS01_AN1                   *((volatile unsigned int*)(0x424E2284UL))\r
+#define bFM3_ADC1_SCIS01_AN2                   *((volatile unsigned int*)(0x424E2288UL))\r
+#define bFM3_ADC1_SCIS01_AN3                   *((volatile unsigned int*)(0x424E228CUL))\r
+#define bFM3_ADC1_SCIS01_AN4                   *((volatile unsigned int*)(0x424E2290UL))\r
+#define bFM3_ADC1_SCIS01_AN5                   *((volatile unsigned int*)(0x424E2294UL))\r
+#define bFM3_ADC1_SCIS01_AN6                   *((volatile unsigned int*)(0x424E2298UL))\r
+#define bFM3_ADC1_SCIS01_AN7                   *((volatile unsigned int*)(0x424E229CUL))\r
+#define bFM3_ADC1_SCIS01_AN8                   *((volatile unsigned int*)(0x424E22A0UL))\r
+#define bFM3_ADC1_SCIS01_AN9                   *((volatile unsigned int*)(0x424E22A4UL))\r
+#define bFM3_ADC1_SCIS01_AN10                  *((volatile unsigned int*)(0x424E22A8UL))\r
+#define bFM3_ADC1_SCIS01_AN11                  *((volatile unsigned int*)(0x424E22ACUL))\r
+#define bFM3_ADC1_SCIS01_AN12                  *((volatile unsigned int*)(0x424E22B0UL))\r
+#define bFM3_ADC1_SCIS01_AN13                  *((volatile unsigned int*)(0x424E22B4UL))\r
+#define bFM3_ADC1_SCIS01_AN14                  *((volatile unsigned int*)(0x424E22B8UL))\r
+#define bFM3_ADC1_SCIS01_AN15                  *((volatile unsigned int*)(0x424E22BCUL))\r
+#define bFM3_ADC1_SCIS0_AN0                    *((volatile unsigned int*)(0x424E2280UL))\r
+#define bFM3_ADC1_SCIS0_AN1                    *((volatile unsigned int*)(0x424E2284UL))\r
+#define bFM3_ADC1_SCIS0_AN2                    *((volatile unsigned int*)(0x424E2288UL))\r
+#define bFM3_ADC1_SCIS0_AN3                    *((volatile unsigned int*)(0x424E228CUL))\r
+#define bFM3_ADC1_SCIS0_AN4                    *((volatile unsigned int*)(0x424E2290UL))\r
+#define bFM3_ADC1_SCIS0_AN5                    *((volatile unsigned int*)(0x424E2294UL))\r
+#define bFM3_ADC1_SCIS0_AN6                    *((volatile unsigned int*)(0x424E2298UL))\r
+#define bFM3_ADC1_SCIS0_AN7                    *((volatile unsigned int*)(0x424E229CUL))\r
+#define bFM3_ADC1_SCIS1_AN8                    *((volatile unsigned int*)(0x424E22A0UL))\r
+#define bFM3_ADC1_SCIS1_AN9                    *((volatile unsigned int*)(0x424E22A4UL))\r
+#define bFM3_ADC1_SCIS1_AN10                   *((volatile unsigned int*)(0x424E22A8UL))\r
+#define bFM3_ADC1_SCIS1_AN11                   *((volatile unsigned int*)(0x424E22ACUL))\r
+#define bFM3_ADC1_SCIS1_AN12                   *((volatile unsigned int*)(0x424E22B0UL))\r
+#define bFM3_ADC1_SCIS1_AN13                   *((volatile unsigned int*)(0x424E22B4UL))\r
+#define bFM3_ADC1_SCIS1_AN14                   *((volatile unsigned int*)(0x424E22B8UL))\r
+#define bFM3_ADC1_SCIS1_AN15                   *((volatile unsigned int*)(0x424E22BCUL))\r
+#define bFM3_ADC1_PFNS_PFS0                    *((volatile unsigned int*)(0x424E2300UL))\r
+#define bFM3_ADC1_PFNS_PFS1                    *((volatile unsigned int*)(0x424E2304UL))\r
+#define bFM3_ADC1_PFNS_TEST0                   *((volatile unsigned int*)(0x424E2310UL))\r
+#define bFM3_ADC1_PFNS_TEST1                   *((volatile unsigned int*)(0x424E2314UL))\r
+#define bFM3_ADC1_PCCR_PSTR                    *((volatile unsigned int*)(0x424E2320UL))\r
+#define bFM3_ADC1_PCCR_PHEN                    *((volatile unsigned int*)(0x424E2324UL))\r
+#define bFM3_ADC1_PCCR_PEEN                    *((volatile unsigned int*)(0x424E2328UL))\r
+#define bFM3_ADC1_PCCR_ESCE                    *((volatile unsigned int*)(0x424E232CUL))\r
+#define bFM3_ADC1_PCCR_PFCLR                   *((volatile unsigned int*)(0x424E2330UL))\r
+#define bFM3_ADC1_PCCR_POVR                    *((volatile unsigned int*)(0x424E2334UL))\r
+#define bFM3_ADC1_PCCR_PFUL                    *((volatile unsigned int*)(0x424E2338UL))\r
+#define bFM3_ADC1_PCCR_PEMP                    *((volatile unsigned int*)(0x424E233CUL))\r
+#define bFM3_ADC1_PCFD_PC0                     *((volatile unsigned int*)(0x424E2380UL))\r
+#define bFM3_ADC1_PCFD_PC1                     *((volatile unsigned int*)(0x424E2384UL))\r
+#define bFM3_ADC1_PCFD_PC2                     *((volatile unsigned int*)(0x424E2388UL))\r
+#define bFM3_ADC1_PCFD_PC3                     *((volatile unsigned int*)(0x424E238CUL))\r
+#define bFM3_ADC1_PCFD_PC4                     *((volatile unsigned int*)(0x424E2390UL))\r
+#define bFM3_ADC1_PCFD_RS0                     *((volatile unsigned int*)(0x424E23A0UL))\r
+#define bFM3_ADC1_PCFD_RS1                     *((volatile unsigned int*)(0x424E23A4UL))\r
+#define bFM3_ADC1_PCFD_RS2                     *((volatile unsigned int*)(0x424E23A8UL))\r
+#define bFM3_ADC1_PCFD_INVL                    *((volatile unsigned int*)(0x424E23B0UL))\r
+#define bFM3_ADC1_PCFD_PD0                     *((volatile unsigned int*)(0x424E23D0UL))\r
+#define bFM3_ADC1_PCFD_PD1                     *((volatile unsigned int*)(0x424E23D4UL))\r
+#define bFM3_ADC1_PCFD_PD2                     *((volatile unsigned int*)(0x424E23D8UL))\r
+#define bFM3_ADC1_PCFD_PD3                     *((volatile unsigned int*)(0x424E23DCUL))\r
+#define bFM3_ADC1_PCFD_PD4                     *((volatile unsigned int*)(0x424E23E0UL))\r
+#define bFM3_ADC1_PCFD_PD5                     *((volatile unsigned int*)(0x424E23E4UL))\r
+#define bFM3_ADC1_PCFD_PD6                     *((volatile unsigned int*)(0x424E23E8UL))\r
+#define bFM3_ADC1_PCFD_PD7                     *((volatile unsigned int*)(0x424E23ECUL))\r
+#define bFM3_ADC1_PCFD_PD8                     *((volatile unsigned int*)(0x424E23F0UL))\r
+#define bFM3_ADC1_PCFD_PD9                     *((volatile unsigned int*)(0x424E23F4UL))\r
+#define bFM3_ADC1_PCFD_PD10                    *((volatile unsigned int*)(0x424E23F8UL))\r
+#define bFM3_ADC1_PCFD_PD11                    *((volatile unsigned int*)(0x424E23FCUL))\r
+#define bFM3_ADC1_PCFDL_PC0                    *((volatile unsigned int*)(0x424E2380UL))\r
+#define bFM3_ADC1_PCFDL_PC1                    *((volatile unsigned int*)(0x424E2384UL))\r
+#define bFM3_ADC1_PCFDL_PC2                    *((volatile unsigned int*)(0x424E2388UL))\r
+#define bFM3_ADC1_PCFDL_PC3                    *((volatile unsigned int*)(0x424E238CUL))\r
+#define bFM3_ADC1_PCFDL_PC4                    *((volatile unsigned int*)(0x424E2390UL))\r
+#define bFM3_ADC1_PCFDL_RS0                    *((volatile unsigned int*)(0x424E23A0UL))\r
+#define bFM3_ADC1_PCFDL_RS1                    *((volatile unsigned int*)(0x424E23A4UL))\r
+#define bFM3_ADC1_PCFDL_RS2                    *((volatile unsigned int*)(0x424E23A8UL))\r
+#define bFM3_ADC1_PCFDL_INVL                   *((volatile unsigned int*)(0x424E23B0UL))\r
+#define bFM3_ADC1_PCFDH_PD0                    *((volatile unsigned int*)(0x424E23D0UL))\r
+#define bFM3_ADC1_PCFDH_PD1                    *((volatile unsigned int*)(0x424E23D4UL))\r
+#define bFM3_ADC1_PCFDH_PD2                    *((volatile unsigned int*)(0x424E23D8UL))\r
+#define bFM3_ADC1_PCFDH_PD3                    *((volatile unsigned int*)(0x424E23DCUL))\r
+#define bFM3_ADC1_PCFDH_PD4                    *((volatile unsigned int*)(0x424E23E0UL))\r
+#define bFM3_ADC1_PCFDH_PD5                    *((volatile unsigned int*)(0x424E23E4UL))\r
+#define bFM3_ADC1_PCFDH_PD6                    *((volatile unsigned int*)(0x424E23E8UL))\r
+#define bFM3_ADC1_PCFDH_PD7                    *((volatile unsigned int*)(0x424E23ECUL))\r
+#define bFM3_ADC1_PCFDH_PD8                    *((volatile unsigned int*)(0x424E23F0UL))\r
+#define bFM3_ADC1_PCFDH_PD9                    *((volatile unsigned int*)(0x424E23F4UL))\r
+#define bFM3_ADC1_PCFDH_PD10                   *((volatile unsigned int*)(0x424E23F8UL))\r
+#define bFM3_ADC1_PCFDH_PD11                   *((volatile unsigned int*)(0x424E23FCUL))\r
+#define bFM3_ADC1_PCIS_P1A0                    *((volatile unsigned int*)(0x424E2400UL))\r
+#define bFM3_ADC1_PCIS_P1A1                    *((volatile unsigned int*)(0x424E2404UL))\r
+#define bFM3_ADC1_PCIS_P1A2                    *((volatile unsigned int*)(0x424E2408UL))\r
+#define bFM3_ADC1_PCIS_P2A0                    *((volatile unsigned int*)(0x424E240CUL))\r
+#define bFM3_ADC1_PCIS_P2A1                    *((volatile unsigned int*)(0x424E2410UL))\r
+#define bFM3_ADC1_PCIS_P2A2                    *((volatile unsigned int*)(0x424E2414UL))\r
+#define bFM3_ADC1_PCIS_P2A3                    *((volatile unsigned int*)(0x424E2418UL))\r
+#define bFM3_ADC1_PCIS_P2A4                    *((volatile unsigned int*)(0x424E241CUL))\r
+#define bFM3_ADC1_CMPCR_CCH0                   *((volatile unsigned int*)(0x424E2480UL))\r
+#define bFM3_ADC1_CMPCR_CCH1                   *((volatile unsigned int*)(0x424E2484UL))\r
+#define bFM3_ADC1_CMPCR_CCH2                   *((volatile unsigned int*)(0x424E2488UL))\r
+#define bFM3_ADC1_CMPCR_CCH3                   *((volatile unsigned int*)(0x424E248CUL))\r
+#define bFM3_ADC1_CMPCR_CCH4                   *((volatile unsigned int*)(0x424E2490UL))\r
+#define bFM3_ADC1_CMPCR_CMD0                   *((volatile unsigned int*)(0x424E2494UL))\r
+#define bFM3_ADC1_CMPCR_CMD1                   *((volatile unsigned int*)(0x424E2498UL))\r
+#define bFM3_ADC1_CMPCR_CMPEN                  *((volatile unsigned int*)(0x424E249CUL))\r
+#define bFM3_ADC1_CMPD_CMAD2                   *((volatile unsigned int*)(0x424E24D8UL))\r
+#define bFM3_ADC1_CMPD_CMAD3                   *((volatile unsigned int*)(0x424E24DCUL))\r
+#define bFM3_ADC1_CMPD_CMAD4                   *((volatile unsigned int*)(0x424E24E0UL))\r
+#define bFM3_ADC1_CMPD_CMAD5                   *((volatile unsigned int*)(0x424E24E4UL))\r
+#define bFM3_ADC1_CMPD_CMAD6                   *((volatile unsigned int*)(0x424E24E8UL))\r
+#define bFM3_ADC1_CMPD_CMAD7                   *((volatile unsigned int*)(0x424E24ECUL))\r
+#define bFM3_ADC1_CMPD_CMAD8                   *((volatile unsigned int*)(0x424E24F0UL))\r
+#define bFM3_ADC1_CMPD_CMAD9                   *((volatile unsigned int*)(0x424E24F4UL))\r
+#define bFM3_ADC1_CMPD_CMAD10                  *((volatile unsigned int*)(0x424E24F8UL))\r
+#define bFM3_ADC1_CMPD_CMAD11                  *((volatile unsigned int*)(0x424E24FCUL))\r
+#define bFM3_ADC1_ADSS23_TS16                  *((volatile unsigned int*)(0x424E2500UL))\r
+#define bFM3_ADC1_ADSS23_TS17                  *((volatile unsigned int*)(0x424E2504UL))\r
+#define bFM3_ADC1_ADSS23_TS18                  *((volatile unsigned int*)(0x424E2508UL))\r
+#define bFM3_ADC1_ADSS23_TS19                  *((volatile unsigned int*)(0x424E250CUL))\r
+#define bFM3_ADC1_ADSS23_TS20                  *((volatile unsigned int*)(0x424E2510UL))\r
+#define bFM3_ADC1_ADSS23_TS21                  *((volatile unsigned int*)(0x424E2514UL))\r
+#define bFM3_ADC1_ADSS23_TS22                  *((volatile unsigned int*)(0x424E2518UL))\r
+#define bFM3_ADC1_ADSS23_TS23                  *((volatile unsigned int*)(0x424E251CUL))\r
+#define bFM3_ADC1_ADSS23_TS24                  *((volatile unsigned int*)(0x424E2520UL))\r
+#define bFM3_ADC1_ADSS23_TS25                  *((volatile unsigned int*)(0x424E2524UL))\r
+#define bFM3_ADC1_ADSS23_TS26                  *((volatile unsigned int*)(0x424E2528UL))\r
+#define bFM3_ADC1_ADSS23_TS27                  *((volatile unsigned int*)(0x424E252CUL))\r
+#define bFM3_ADC1_ADSS23_TS28                  *((volatile unsigned int*)(0x424E2530UL))\r
+#define bFM3_ADC1_ADSS23_TS29                  *((volatile unsigned int*)(0x424E2534UL))\r
+#define bFM3_ADC1_ADSS23_TS30                  *((volatile unsigned int*)(0x424E2538UL))\r
+#define bFM3_ADC1_ADSS23_TS31                  *((volatile unsigned int*)(0x424E253CUL))\r
+#define bFM3_ADC1_ADSS2_TS16                   *((volatile unsigned int*)(0x424E2500UL))\r
+#define bFM3_ADC1_ADSS2_TS17                   *((volatile unsigned int*)(0x424E2504UL))\r
+#define bFM3_ADC1_ADSS2_TS18                   *((volatile unsigned int*)(0x424E2508UL))\r
+#define bFM3_ADC1_ADSS2_TS19                   *((volatile unsigned int*)(0x424E250CUL))\r
+#define bFM3_ADC1_ADSS2_TS20                   *((volatile unsigned int*)(0x424E2510UL))\r
+#define bFM3_ADC1_ADSS2_TS21                   *((volatile unsigned int*)(0x424E2514UL))\r
+#define bFM3_ADC1_ADSS2_TS22                   *((volatile unsigned int*)(0x424E2518UL))\r
+#define bFM3_ADC1_ADSS2_TS23                   *((volatile unsigned int*)(0x424E251CUL))\r
+#define bFM3_ADC1_ADSS3_TS24                   *((volatile unsigned int*)(0x424E2520UL))\r
+#define bFM3_ADC1_ADSS3_TS25                   *((volatile unsigned int*)(0x424E2524UL))\r
+#define bFM3_ADC1_ADSS3_TS26                   *((volatile unsigned int*)(0x424E2528UL))\r
+#define bFM3_ADC1_ADSS3_TS27                   *((volatile unsigned int*)(0x424E252CUL))\r
+#define bFM3_ADC1_ADSS3_TS28                   *((volatile unsigned int*)(0x424E2530UL))\r
+#define bFM3_ADC1_ADSS3_TS29                   *((volatile unsigned int*)(0x424E2534UL))\r
+#define bFM3_ADC1_ADSS3_TS30                   *((volatile unsigned int*)(0x424E2538UL))\r
+#define bFM3_ADC1_ADSS3_TS31                   *((volatile unsigned int*)(0x424E253CUL))\r
+#define bFM3_ADC1_ADSS01_TS0                   *((volatile unsigned int*)(0x424E2580UL))\r
+#define bFM3_ADC1_ADSS01_TS1                   *((volatile unsigned int*)(0x424E2584UL))\r
+#define bFM3_ADC1_ADSS01_TS2                   *((volatile unsigned int*)(0x424E2588UL))\r
+#define bFM3_ADC1_ADSS01_TS3                   *((volatile unsigned int*)(0x424E258CUL))\r
+#define bFM3_ADC1_ADSS01_TS4                   *((volatile unsigned int*)(0x424E2590UL))\r
+#define bFM3_ADC1_ADSS01_TS5                   *((volatile unsigned int*)(0x424E2594UL))\r
+#define bFM3_ADC1_ADSS01_TS6                   *((volatile unsigned int*)(0x424E2598UL))\r
+#define bFM3_ADC1_ADSS01_TS7                   *((volatile unsigned int*)(0x424E259CUL))\r
+#define bFM3_ADC1_ADSS01_TS8                   *((volatile unsigned int*)(0x424E25A0UL))\r
+#define bFM3_ADC1_ADSS01_TS9                   *((volatile unsigned int*)(0x424E25A4UL))\r
+#define bFM3_ADC1_ADSS01_TS10                  *((volatile unsigned int*)(0x424E25A8UL))\r
+#define bFM3_ADC1_ADSS01_TS11                  *((volatile unsigned int*)(0x424E25ACUL))\r
+#define bFM3_ADC1_ADSS01_TS12                  *((volatile unsigned int*)(0x424E25B0UL))\r
+#define bFM3_ADC1_ADSS01_TS13                  *((volatile unsigned int*)(0x424E25B4UL))\r
+#define bFM3_ADC1_ADSS01_TS14                  *((volatile unsigned int*)(0x424E25B8UL))\r
+#define bFM3_ADC1_ADSS01_TS15                  *((volatile unsigned int*)(0x424E25BCUL))\r
+#define bFM3_ADC1_ADSS0_TS0                    *((volatile unsigned int*)(0x424E2580UL))\r
+#define bFM3_ADC1_ADSS0_TS1                    *((volatile unsigned int*)(0x424E2584UL))\r
+#define bFM3_ADC1_ADSS0_TS2                    *((volatile unsigned int*)(0x424E2588UL))\r
+#define bFM3_ADC1_ADSS0_TS3                    *((volatile unsigned int*)(0x424E258CUL))\r
+#define bFM3_ADC1_ADSS0_TS4                    *((volatile unsigned int*)(0x424E2590UL))\r
+#define bFM3_ADC1_ADSS0_TS5                    *((volatile unsigned int*)(0x424E2594UL))\r
+#define bFM3_ADC1_ADSS0_TS6                    *((volatile unsigned int*)(0x424E2598UL))\r
+#define bFM3_ADC1_ADSS0_TS7                    *((volatile unsigned int*)(0x424E259CUL))\r
+#define bFM3_ADC1_ADSS1_TS8                    *((volatile unsigned int*)(0x424E25A0UL))\r
+#define bFM3_ADC1_ADSS1_TS9                    *((volatile unsigned int*)(0x424E25A4UL))\r
+#define bFM3_ADC1_ADSS1_TS10                   *((volatile unsigned int*)(0x424E25A8UL))\r
+#define bFM3_ADC1_ADSS1_TS11                   *((volatile unsigned int*)(0x424E25ACUL))\r
+#define bFM3_ADC1_ADSS1_TS12                   *((volatile unsigned int*)(0x424E25B0UL))\r
+#define bFM3_ADC1_ADSS1_TS13                   *((volatile unsigned int*)(0x424E25B4UL))\r
+#define bFM3_ADC1_ADSS1_TS14                   *((volatile unsigned int*)(0x424E25B8UL))\r
+#define bFM3_ADC1_ADSS1_TS15                   *((volatile unsigned int*)(0x424E25BCUL))\r
+#define bFM3_ADC1_ADST01_ST10                  *((volatile unsigned int*)(0x424E2600UL))\r
+#define bFM3_ADC1_ADST01_ST11                  *((volatile unsigned int*)(0x424E2604UL))\r
+#define bFM3_ADC1_ADST01_ST12                  *((volatile unsigned int*)(0x424E2608UL))\r
+#define bFM3_ADC1_ADST01_ST13                  *((volatile unsigned int*)(0x424E260CUL))\r
+#define bFM3_ADC1_ADST01_ST14                  *((volatile unsigned int*)(0x424E2610UL))\r
+#define bFM3_ADC1_ADST01_STX10                 *((volatile unsigned int*)(0x424E2614UL))\r
+#define bFM3_ADC1_ADST01_STX11                 *((volatile unsigned int*)(0x424E2618UL))\r
+#define bFM3_ADC1_ADST01_STX12                 *((volatile unsigned int*)(0x424E261CUL))\r
+#define bFM3_ADC1_ADST01_ST00                  *((volatile unsigned int*)(0x424E2620UL))\r
+#define bFM3_ADC1_ADST01_ST01                  *((volatile unsigned int*)(0x424E2624UL))\r
+#define bFM3_ADC1_ADST01_ST02                  *((volatile unsigned int*)(0x424E2628UL))\r
+#define bFM3_ADC1_ADST01_ST03                  *((volatile unsigned int*)(0x424E262CUL))\r
+#define bFM3_ADC1_ADST01_ST04                  *((volatile unsigned int*)(0x424E2630UL))\r
+#define bFM3_ADC1_ADST01_STX00                 *((volatile unsigned int*)(0x424E2634UL))\r
+#define bFM3_ADC1_ADST01_STX01                 *((volatile unsigned int*)(0x424E2638UL))\r
+#define bFM3_ADC1_ADST01_STX02                 *((volatile unsigned int*)(0x424E263CUL))\r
+#define bFM3_ADC1_ADST1_ST10                   *((volatile unsigned int*)(0x424E2600UL))\r
+#define bFM3_ADC1_ADST1_ST11                   *((volatile unsigned int*)(0x424E2604UL))\r
+#define bFM3_ADC1_ADST1_ST12                   *((volatile unsigned int*)(0x424E2608UL))\r
+#define bFM3_ADC1_ADST1_ST13                   *((volatile unsigned int*)(0x424E260CUL))\r
+#define bFM3_ADC1_ADST1_ST14                   *((volatile unsigned int*)(0x424E2610UL))\r
+#define bFM3_ADC1_ADST1_STX10                  *((volatile unsigned int*)(0x424E2614UL))\r
+#define bFM3_ADC1_ADST1_STX11                  *((volatile unsigned int*)(0x424E2618UL))\r
+#define bFM3_ADC1_ADST1_STX12                  *((volatile unsigned int*)(0x424E261CUL))\r
+#define bFM3_ADC1_ADST0_ST00                   *((volatile unsigned int*)(0x424E2620UL))\r
+#define bFM3_ADC1_ADST0_ST01                   *((volatile unsigned int*)(0x424E2624UL))\r
+#define bFM3_ADC1_ADST0_ST02                   *((volatile unsigned int*)(0x424E2628UL))\r
+#define bFM3_ADC1_ADST0_ST03                   *((volatile unsigned int*)(0x424E262CUL))\r
+#define bFM3_ADC1_ADST0_ST04                   *((volatile unsigned int*)(0x424E2630UL))\r
+#define bFM3_ADC1_ADST0_STX00                  *((volatile unsigned int*)(0x424E2634UL))\r
+#define bFM3_ADC1_ADST0_STX01                  *((volatile unsigned int*)(0x424E2638UL))\r
+#define bFM3_ADC1_ADST0_STX02                  *((volatile unsigned int*)(0x424E263CUL))\r
+#define bFM3_ADC1_ADCT_CT0                     *((volatile unsigned int*)(0x424E2680UL))\r
+#define bFM3_ADC1_ADCT_CT1                     *((volatile unsigned int*)(0x424E2684UL))\r
+#define bFM3_ADC1_ADCT_CT2                     *((volatile unsigned int*)(0x424E2688UL))\r
+#define bFM3_ADC1_ADCT_CT3                     *((volatile unsigned int*)(0x424E268CUL))\r
+#define bFM3_ADC1_ADCT_CT4                     *((volatile unsigned int*)(0x424E2690UL))\r
+#define bFM3_ADC1_ADCT_CT5                     *((volatile unsigned int*)(0x424E2694UL))\r
+#define bFM3_ADC1_ADCT_CT6                     *((volatile unsigned int*)(0x424E2698UL))\r
+#define bFM3_ADC1_ADCT_CT7                     *((volatile unsigned int*)(0x424E269CUL))\r
+#define bFM3_ADC1_PRTSL_PRTSL0                 *((volatile unsigned int*)(0x424E2700UL))\r
+#define bFM3_ADC1_PRTSL_PRTSL1                 *((volatile unsigned int*)(0x424E2704UL))\r
+#define bFM3_ADC1_PRTSL_PRTSL2                 *((volatile unsigned int*)(0x424E2708UL))\r
+#define bFM3_ADC1_PRTSL_PRTSL3                 *((volatile unsigned int*)(0x424E270CUL))\r
+#define bFM3_ADC1_SCTSL_SCTSL0                 *((volatile unsigned int*)(0x424E2720UL))\r
+#define bFM3_ADC1_SCTSL_SCTSL1                 *((volatile unsigned int*)(0x424E2724UL))\r
+#define bFM3_ADC1_SCTSL_SCTSL2                 *((volatile unsigned int*)(0x424E2728UL))\r
+#define bFM3_ADC1_SCTSL_SCTSL3                 *((volatile unsigned int*)(0x424E272CUL))\r
+#define bFM3_ADC1_ADCEN_ENBL                   *((volatile unsigned int*)(0x424E2780UL))\r
+#define bFM3_ADC1_ADCEN_READY                  *((volatile unsigned int*)(0x424E2784UL))\r
+#define bFM3_ADC1_ADCEN_CYCLSL0                *((volatile unsigned int*)(0x424E2790UL))\r
+#define bFM3_ADC1_ADCEN_CYCLSL1                *((volatile unsigned int*)(0x424E2794UL))\r
+\r
+/* CR trimming registers */\r
+#define bFM3_CRTRIM_MCR_PSR_CSR0               *((volatile unsigned int*)(0x425C0000UL))\r
+#define bFM3_CRTRIM_MCR_PSR_CSR1               *((volatile unsigned int*)(0x425C0004UL))\r
+#define bFM3_CRTRIM_MCR_FTRM_TRD0              *((volatile unsigned int*)(0x425C0080UL))\r
+#define bFM3_CRTRIM_MCR_FTRM_TRD1              *((volatile unsigned int*)(0x425C0084UL))\r
+#define bFM3_CRTRIM_MCR_FTRM_TRD2              *((volatile unsigned int*)(0x425C0088UL))\r
+#define bFM3_CRTRIM_MCR_FTRM_TRD3              *((volatile unsigned int*)(0x425C008CUL))\r
+#define bFM3_CRTRIM_MCR_FTRM_TRD4              *((volatile unsigned int*)(0x425C0090UL))\r
+#define bFM3_CRTRIM_MCR_FTRM_TRD5              *((volatile unsigned int*)(0x425C0094UL))\r
+#define bFM3_CRTRIM_MCR_FTRM_TRD6              *((volatile unsigned int*)(0x425C0098UL))\r
+#define bFM3_CRTRIM_MCR_FTRM_TRD7              *((volatile unsigned int*)(0x425C009CUL))\r
+\r
+/* External interrupt registers */\r
+#define bFM3_EXTI_ENIR_EN0                     *((volatile unsigned int*)(0x42600000UL))\r
+#define bFM3_EXTI_ENIR_EN1                     *((volatile unsigned int*)(0x42600004UL))\r
+#define bFM3_EXTI_ENIR_EN2                     *((volatile unsigned int*)(0x42600008UL))\r
+#define bFM3_EXTI_ENIR_EN3                     *((volatile unsigned int*)(0x4260000CUL))\r
+#define bFM3_EXTI_ENIR_EN4                     *((volatile unsigned int*)(0x42600010UL))\r
+#define bFM3_EXTI_ENIR_EN5                     *((volatile unsigned int*)(0x42600014UL))\r
+#define bFM3_EXTI_ENIR_EN6                     *((volatile unsigned int*)(0x42600018UL))\r
+#define bFM3_EXTI_ENIR_EN7                     *((volatile unsigned int*)(0x4260001CUL))\r
+#define bFM3_EXTI_ENIR_EN8                     *((volatile unsigned int*)(0x42600020UL))\r
+#define bFM3_EXTI_ENIR_EN14                    *((volatile unsigned int*)(0x42600038UL))\r
+#define bFM3_EXTI_ENIR_EN15                    *((volatile unsigned int*)(0x4260003CUL))\r
+#define bFM3_EXTI_EIRR_ER0                     *((volatile unsigned int*)(0x42600080UL))\r
+#define bFM3_EXTI_EIRR_ER1                     *((volatile unsigned int*)(0x42600084UL))\r
+#define bFM3_EXTI_EIRR_ER2                     *((volatile unsigned int*)(0x42600088UL))\r
+#define bFM3_EXTI_EIRR_ER3                     *((volatile unsigned int*)(0x4260008CUL))\r
+#define bFM3_EXTI_EIRR_ER4                     *((volatile unsigned int*)(0x42600090UL))\r
+#define bFM3_EXTI_EIRR_ER5                     *((volatile unsigned int*)(0x42600094UL))\r
+#define bFM3_EXTI_EIRR_ER6                     *((volatile unsigned int*)(0x42600098UL))\r
+#define bFM3_EXTI_EIRR_ER7                     *((volatile unsigned int*)(0x4260009CUL))\r
+#define bFM3_EXTI_EIRR_ER8                     *((volatile unsigned int*)(0x426000A0UL))\r
+#define bFM3_EXTI_EIRR_ER14                    *((volatile unsigned int*)(0x426000B8UL))\r
+#define bFM3_EXTI_EIRR_ER15                    *((volatile unsigned int*)(0x426000BCUL))\r
+#define bFM3_EXTI_EICL_ECL0                    *((volatile unsigned int*)(0x42600100UL))\r
+#define bFM3_EXTI_EICL_ECL1                    *((volatile unsigned int*)(0x42600104UL))\r
+#define bFM3_EXTI_EICL_ECL2                    *((volatile unsigned int*)(0x42600108UL))\r
+#define bFM3_EXTI_EICL_ECL3                    *((volatile unsigned int*)(0x4260010CUL))\r
+#define bFM3_EXTI_EICL_ECL4                    *((volatile unsigned int*)(0x42600110UL))\r
+#define bFM3_EXTI_EICL_ECL5                    *((volatile unsigned int*)(0x42600114UL))\r
+#define bFM3_EXTI_EICL_ECL6                    *((volatile unsigned int*)(0x42600118UL))\r
+#define bFM3_EXTI_EICL_ECL7                    *((volatile unsigned int*)(0x4260011CUL))\r
+#define bFM3_EXTI_EICL_ECL8                    *((volatile unsigned int*)(0x42600120UL))\r
+#define bFM3_EXTI_EICL_ECL14                   *((volatile unsigned int*)(0x42600138UL))\r
+#define bFM3_EXTI_EICL_ECL15                   *((volatile unsigned int*)(0x4260013CUL))\r
+#define bFM3_EXTI_ELVR_LA0                     *((volatile unsigned int*)(0x42600180UL))\r
+#define bFM3_EXTI_ELVR_LB0                     *((volatile unsigned int*)(0x42600184UL))\r
+#define bFM3_EXTI_ELVR_LA1                     *((volatile unsigned int*)(0x42600188UL))\r
+#define bFM3_EXTI_ELVR_LB1                     *((volatile unsigned int*)(0x4260018CUL))\r
+#define bFM3_EXTI_ELVR_LA2                     *((volatile unsigned int*)(0x42600190UL))\r
+#define bFM3_EXTI_ELVR_LB2                     *((volatile unsigned int*)(0x42600194UL))\r
+#define bFM3_EXTI_ELVR_LA3                     *((volatile unsigned int*)(0x42600198UL))\r
+#define bFM3_EXTI_ELVR_LB3                     *((volatile unsigned int*)(0x4260019CUL))\r
+#define bFM3_EXTI_ELVR_LA4                     *((volatile unsigned int*)(0x426001A0UL))\r
+#define bFM3_EXTI_ELVR_LB4                     *((volatile unsigned int*)(0x426001A4UL))\r
+#define bFM3_EXTI_ELVR_LA5                     *((volatile unsigned int*)(0x426001A8UL))\r
+#define bFM3_EXTI_ELVR_LB5                     *((volatile unsigned int*)(0x426001ACUL))\r
+#define bFM3_EXTI_ELVR_LA6                     *((volatile unsigned int*)(0x426001B0UL))\r
+#define bFM3_EXTI_ELVR_LB6                     *((volatile unsigned int*)(0x426001B4UL))\r
+#define bFM3_EXTI_ELVR_LA7                     *((volatile unsigned int*)(0x426001B8UL))\r
+#define bFM3_EXTI_ELVR_LB7                     *((volatile unsigned int*)(0x426001BCUL))\r
+#define bFM3_EXTI_ELVR_LA8                     *((volatile unsigned int*)(0x426001C0UL))\r
+#define bFM3_EXTI_ELVR_LB8                     *((volatile unsigned int*)(0x426001C4UL))\r
+#define bFM3_EXTI_ELVR_LA14                    *((volatile unsigned int*)(0x426001F0UL))\r
+#define bFM3_EXTI_ELVR_LB14                    *((volatile unsigned int*)(0x426001F4UL))\r
+#define bFM3_EXTI_ELVR_LA15                    *((volatile unsigned int*)(0x426001F8UL))\r
+#define bFM3_EXTI_ELVR_LB15                    *((volatile unsigned int*)(0x426001FCUL))\r
+#define bFM3_EXTI_NMIRR_NR0                    *((volatile unsigned int*)(0x42600280UL))\r
+#define bFM3_EXTI_NMICL_NCL0                   *((volatile unsigned int*)(0x42600300UL))\r
+\r
+/* Interrupt request read registers */\r
+#define bFM3_INTREQ_DRQSEL_DRQSEL0             *((volatile unsigned int*)(0x42620000UL))\r
+#define bFM3_INTREQ_DRQSEL_DRQSEL1             *((volatile unsigned int*)(0x42620004UL))\r
+#define bFM3_INTREQ_DRQSEL_DRQSEL2             *((volatile unsigned int*)(0x42620008UL))\r
+#define bFM3_INTREQ_DRQSEL_DRQSEL3             *((volatile unsigned int*)(0x4262000CUL))\r
+#define bFM3_INTREQ_DRQSEL_DRQSEL4             *((volatile unsigned int*)(0x42620010UL))\r
+#define bFM3_INTREQ_DRQSEL_DRQSEL5             *((volatile unsigned int*)(0x42620014UL))\r
+#define bFM3_INTREQ_DRQSEL_DRQSEL6             *((volatile unsigned int*)(0x42620018UL))\r
+#define bFM3_INTREQ_DRQSEL_DRQSEL7             *((volatile unsigned int*)(0x4262001CUL))\r
+#define bFM3_INTREQ_DRQSEL_DRQSEL8             *((volatile unsigned int*)(0x42620020UL))\r
+#define bFM3_INTREQ_DRQSEL_DRQSEL9             *((volatile unsigned int*)(0x42620024UL))\r
+#define bFM3_INTREQ_DRQSEL_DRQSEL10            *((volatile unsigned int*)(0x42620028UL))\r
+#define bFM3_INTREQ_DRQSEL_DRQSEL11            *((volatile unsigned int*)(0x4262002CUL))\r
+#define bFM3_INTREQ_DRQSEL_DRQSEL12            *((volatile unsigned int*)(0x42620030UL))\r
+#define bFM3_INTREQ_DRQSEL_DRQSEL13            *((volatile unsigned int*)(0x42620034UL))\r
+#define bFM3_INTREQ_DRQSEL_DRQSEL14            *((volatile unsigned int*)(0x42620038UL))\r
+#define bFM3_INTREQ_DRQSEL_DRQSEL15            *((volatile unsigned int*)(0x4262003CUL))\r
+#define bFM3_INTREQ_DRQSEL_DRQSEL16            *((volatile unsigned int*)(0x42620040UL))\r
+#define bFM3_INTREQ_DRQSEL_DRQSEL17            *((volatile unsigned int*)(0x42620044UL))\r
+#define bFM3_INTREQ_DRQSEL_DRQSEL18            *((volatile unsigned int*)(0x42620048UL))\r
+#define bFM3_INTREQ_DRQSEL_DRQSEL19            *((volatile unsigned int*)(0x4262004CUL))\r
+#define bFM3_INTREQ_DRQSEL_DRQSEL20            *((volatile unsigned int*)(0x42620050UL))\r
+#define bFM3_INTREQ_DRQSEL_DRQSEL21            *((volatile unsigned int*)(0x42620054UL))\r
+#define bFM3_INTREQ_DRQSEL_DRQSEL22            *((volatile unsigned int*)(0x42620058UL))\r
+#define bFM3_INTREQ_DRQSEL_DRQSEL23            *((volatile unsigned int*)(0x4262005CUL))\r
+#define bFM3_INTREQ_DRQSEL_DRQSEL24            *((volatile unsigned int*)(0x42620060UL))\r
+#define bFM3_INTREQ_DRQSEL_DRQSEL25            *((volatile unsigned int*)(0x42620064UL))\r
+#define bFM3_INTREQ_DRQSEL_DRQSEL26            *((volatile unsigned int*)(0x42620068UL))\r
+#define bFM3_INTREQ_DRQSEL_DRQSEL27            *((volatile unsigned int*)(0x4262006CUL))\r
+#define bFM3_INTREQ_DRQSEL_DRQSEL28            *((volatile unsigned int*)(0x42620070UL))\r
+#define bFM3_INTREQ_DRQSEL_DRQSEL29            *((volatile unsigned int*)(0x42620074UL))\r
+#define bFM3_INTREQ_DRQSEL_DRQSEL30            *((volatile unsigned int*)(0x42620078UL))\r
+#define bFM3_INTREQ_DRQSEL_DRQSEL31            *((volatile unsigned int*)(0x4262007CUL))\r
+#define bFM3_INTREQ_ODDPKS_ODDPKS0             *((volatile unsigned int*)(0x42620160UL))\r
+#define bFM3_INTREQ_ODDPKS_ODDPKS1             *((volatile unsigned int*)(0x42620164UL))\r
+#define bFM3_INTREQ_ODDPKS_ODDPKS2             *((volatile unsigned int*)(0x42620168UL))\r
+#define bFM3_INTREQ_ODDPKS_ODDPKS3             *((volatile unsigned int*)(0x4262016CUL))\r
+#define bFM3_INTREQ_ODDPKS_ODDPKS4             *((volatile unsigned int*)(0x42620170UL))\r
+#define bFM3_INTREQ_EXC02MON_NMI               *((volatile unsigned int*)(0x42620200UL))\r
+#define bFM3_INTREQ_EXC02MON_HWINT             *((volatile unsigned int*)(0x42620204UL))\r
+#define bFM3_INTREQ_IRQ00MON_FCSINT            *((volatile unsigned int*)(0x42620280UL))\r
+#define bFM3_INTREQ_IRQ01MON_SWWDTINT          *((volatile unsigned int*)(0x42620300UL))\r
+#define bFM3_INTREQ_IRQ02MON_LVDINT            *((volatile unsigned int*)(0x42620380UL))\r
+#define bFM3_INTREQ_IRQ03MON_WAVE0INT0         *((volatile unsigned int*)(0x42620400UL))\r
+#define bFM3_INTREQ_IRQ03MON_WAVE0INT1         *((volatile unsigned int*)(0x42620404UL))\r
+#define bFM3_INTREQ_IRQ03MON_WAVE0INT2         *((volatile unsigned int*)(0x42620408UL))\r
+#define bFM3_INTREQ_IRQ03MON_WAVE0INT3         *((volatile unsigned int*)(0x4262040CUL))\r
+#define bFM3_INTREQ_IRQ03MON_WAVE1INT0         *((volatile unsigned int*)(0x42620410UL))\r
+#define bFM3_INTREQ_IRQ03MON_WAVE1INT1         *((volatile unsigned int*)(0x42620414UL))\r
+#define bFM3_INTREQ_IRQ03MON_WAVE1INT2         *((volatile unsigned int*)(0x42620418UL))\r
+#define bFM3_INTREQ_IRQ03MON_WAVE1INT3         *((volatile unsigned int*)(0x4262041CUL))\r
+#define bFM3_INTREQ_IRQ04MON_EXTINT0           *((volatile unsigned int*)(0x42620480UL))\r
+#define bFM3_INTREQ_IRQ04MON_EXTINT1           *((volatile unsigned int*)(0x42620484UL))\r
+#define bFM3_INTREQ_IRQ04MON_EXTINT2           *((volatile unsigned int*)(0x42620488UL))\r
+#define bFM3_INTREQ_IRQ04MON_EXTINT3           *((volatile unsigned int*)(0x4262048CUL))\r
+#define bFM3_INTREQ_IRQ04MON_EXTINT4           *((volatile unsigned int*)(0x42620490UL))\r
+#define bFM3_INTREQ_IRQ04MON_EXTINT5           *((volatile unsigned int*)(0x42620494UL))\r
+#define bFM3_INTREQ_IRQ04MON_EXTINT6           *((volatile unsigned int*)(0x42620498UL))\r
+#define bFM3_INTREQ_IRQ05MON_EXTINT7           *((volatile unsigned int*)(0x4262051CUL))\r
+#define bFM3_INTREQ_IRQ06MON_TIMINT0           *((volatile unsigned int*)(0x42620580UL))\r
+#define bFM3_INTREQ_IRQ06MON_TIMINT1           *((volatile unsigned int*)(0x42620584UL))\r
+#define bFM3_INTREQ_IRQ06MON_QUD0INT0          *((volatile unsigned int*)(0x42620588UL))\r
+#define bFM3_INTREQ_IRQ06MON_QUD0INT1          *((volatile unsigned int*)(0x4262058CUL))\r
+#define bFM3_INTREQ_IRQ06MON_QUD0INT2          *((volatile unsigned int*)(0x42620590UL))\r
+#define bFM3_INTREQ_IRQ06MON_QUD0INT3          *((volatile unsigned int*)(0x42620594UL))\r
+#define bFM3_INTREQ_IRQ06MON_QUD0INT4          *((volatile unsigned int*)(0x42620598UL))\r
+#define bFM3_INTREQ_IRQ06MON_QUD0INT5          *((volatile unsigned int*)(0x4262059CUL))\r
+#define bFM3_INTREQ_IRQ06MON_QUD1INT0          *((volatile unsigned int*)(0x426205A0UL))\r
+#define bFM3_INTREQ_IRQ06MON_QUD1INT1          *((volatile unsigned int*)(0x426205A4UL))\r
+#define bFM3_INTREQ_IRQ06MON_QUD1INT2          *((volatile unsigned int*)(0x426205A8UL))\r
+#define bFM3_INTREQ_IRQ06MON_QUD1INT3          *((volatile unsigned int*)(0x426205ACUL))\r
+#define bFM3_INTREQ_IRQ06MON_QUD1INT4          *((volatile unsigned int*)(0x426205B0UL))\r
+#define bFM3_INTREQ_IRQ06MON_QUD1INT5          *((volatile unsigned int*)(0x426205B4UL))\r
+#define bFM3_INTREQ_IRQ07MON_FMSINT            *((volatile unsigned int*)(0x42620600UL))\r
+#define bFM3_INTREQ_IRQ08MON_MFSINT0           *((volatile unsigned int*)(0x42620680UL))\r
+#define bFM3_INTREQ_IRQ08MON_MFSINT1           *((volatile unsigned int*)(0x42620684UL))\r
+#define bFM3_INTREQ_IRQ09MON_FMSINT            *((volatile unsigned int*)(0x42620700UL))\r
+#define bFM3_INTREQ_IRQ10MON_MFSINT0           *((volatile unsigned int*)(0x42620780UL))\r
+#define bFM3_INTREQ_IRQ10MON_MFSINT1           *((volatile unsigned int*)(0x42620784UL))\r
+#define bFM3_INTREQ_IRQ11MON_FMSINT            *((volatile unsigned int*)(0x42620800UL))\r
+#define bFM3_INTREQ_IRQ12MON_MFSINT0           *((volatile unsigned int*)(0x42620880UL))\r
+#define bFM3_INTREQ_IRQ12MON_MFSINT1           *((volatile unsigned int*)(0x42620884UL))\r
+#define bFM3_INTREQ_IRQ13MON_FMSINT            *((volatile unsigned int*)(0x42620900UL))\r
+#define bFM3_INTREQ_IRQ14MON_MFSINT0           *((volatile unsigned int*)(0x42620980UL))\r
+#define bFM3_INTREQ_IRQ14MON_MFSINT1           *((volatile unsigned int*)(0x42620984UL))\r
+#define bFM3_INTREQ_IRQ15MON_FMSINT            *((volatile unsigned int*)(0x42620A00UL))\r
+#define bFM3_INTREQ_IRQ16MON_MFSINT0           *((volatile unsigned int*)(0x42620A80UL))\r
+#define bFM3_INTREQ_IRQ16MON_MFSINT1           *((volatile unsigned int*)(0x42620A84UL))\r
+#define bFM3_INTREQ_IRQ17MON_FMSINT            *((volatile unsigned int*)(0x42620B00UL))\r
+#define bFM3_INTREQ_IRQ18MON_MFSINT0           *((volatile unsigned int*)(0x42620B80UL))\r
+#define bFM3_INTREQ_IRQ18MON_MFSINT1           *((volatile unsigned int*)(0x42620B84UL))\r
+#define bFM3_INTREQ_IRQ19MON_FMSINT            *((volatile unsigned int*)(0x42620C00UL))\r
+#define bFM3_INTREQ_IRQ20MON_MFSINT0           *((volatile unsigned int*)(0x42620C80UL))\r
+#define bFM3_INTREQ_IRQ20MON_MFSINT1           *((volatile unsigned int*)(0x42620C84UL))\r
+#define bFM3_INTREQ_IRQ21MON_FMSINT            *((volatile unsigned int*)(0x42620D00UL))\r
+#define bFM3_INTREQ_IRQ22MON_MFSINT0           *((volatile unsigned int*)(0x42620D80UL))\r
+#define bFM3_INTREQ_IRQ22MON_MFSINT1           *((volatile unsigned int*)(0x42620D84UL))\r
+#define bFM3_INTREQ_IRQ23MON_PPGINT0           *((volatile unsigned int*)(0x42620E00UL))\r
+#define bFM3_INTREQ_IRQ23MON_PPGINT1           *((volatile unsigned int*)(0x42620E04UL))\r
+#define bFM3_INTREQ_IRQ23MON_PPGINT2           *((volatile unsigned int*)(0x42620E08UL))\r
+#define bFM3_INTREQ_IRQ23MON_PPGINT3           *((volatile unsigned int*)(0x42620E0CUL))\r
+#define bFM3_INTREQ_IRQ23MON_PPGINT4           *((volatile unsigned int*)(0x42620E10UL))\r
+#define bFM3_INTREQ_IRQ23MON_PPGINT5           *((volatile unsigned int*)(0x42620E14UL))\r
+#define bFM3_INTREQ_IRQ24MON_MOSCINT           *((volatile unsigned int*)(0x42620E80UL))\r
+#define bFM3_INTREQ_IRQ24MON_SOSCINT           *((volatile unsigned int*)(0x42620E84UL))\r
+#define bFM3_INTREQ_IRQ24MON_MPLLINT           *((volatile unsigned int*)(0x42620E88UL))\r
+#define bFM3_INTREQ_IRQ24MON_UPLLINT           *((volatile unsigned int*)(0x42620E8CUL))\r
+#define bFM3_INTREQ_IRQ24MON_WCINT             *((volatile unsigned int*)(0x42620E90UL))\r
+#define bFM3_INTREQ_IRQ25MON_ADCINT0           *((volatile unsigned int*)(0x42620F00UL))\r
+#define bFM3_INTREQ_IRQ25MON_ADCINT1           *((volatile unsigned int*)(0x42620F04UL))\r
+#define bFM3_INTREQ_IRQ25MON_ADCINT2           *((volatile unsigned int*)(0x42620F08UL))\r
+#define bFM3_INTREQ_IRQ25MON_ADCINT3           *((volatile unsigned int*)(0x42620F0CUL))\r
+#define bFM3_INTREQ_IRQ26MON_ADCINT0           *((volatile unsigned int*)(0x42620F80UL))\r
+#define bFM3_INTREQ_IRQ26MON_ADCINT1           *((volatile unsigned int*)(0x42620F84UL))\r
+#define bFM3_INTREQ_IRQ26MON_ADCINT2           *((volatile unsigned int*)(0x42620F88UL))\r
+#define bFM3_INTREQ_IRQ26MON_ADCINT3           *((volatile unsigned int*)(0x42620F8CUL))\r
+#define bFM3_INTREQ_IRQ28MON_FRT0INT0          *((volatile unsigned int*)(0x42621080UL))\r
+#define bFM3_INTREQ_IRQ28MON_FRT0INT1          *((volatile unsigned int*)(0x42621084UL))\r
+#define bFM3_INTREQ_IRQ28MON_FRT0INT2          *((volatile unsigned int*)(0x42621088UL))\r
+#define bFM3_INTREQ_IRQ28MON_FRT0INT3          *((volatile unsigned int*)(0x4262108CUL))\r
+#define bFM3_INTREQ_IRQ28MON_FRT0INT4          *((volatile unsigned int*)(0x42621090UL))\r
+#define bFM3_INTREQ_IRQ28MON_FRT0INT5          *((volatile unsigned int*)(0x42621094UL))\r
+#define bFM3_INTREQ_IRQ28MON_FRT1INT0          *((volatile unsigned int*)(0x42621098UL))\r
+#define bFM3_INTREQ_IRQ28MON_FRT1INT1          *((volatile unsigned int*)(0x4262109CUL))\r
+#define bFM3_INTREQ_IRQ28MON_FRT1INT2          *((volatile unsigned int*)(0x426210A0UL))\r
+#define bFM3_INTREQ_IRQ28MON_FRT1INT3          *((volatile unsigned int*)(0x426210A4UL))\r
+#define bFM3_INTREQ_IRQ28MON_FRT1INT4          *((volatile unsigned int*)(0x426210A8UL))\r
+#define bFM3_INTREQ_IRQ28MON_FRT1INT5          *((volatile unsigned int*)(0x426210ACUL))\r
+#define bFM3_INTREQ_IRQ29MON_ICU0INT0          *((volatile unsigned int*)(0x42621100UL))\r
+#define bFM3_INTREQ_IRQ29MON_ICU0INT1          *((volatile unsigned int*)(0x42621104UL))\r
+#define bFM3_INTREQ_IRQ29MON_ICU0INT2          *((volatile unsigned int*)(0x42621108UL))\r
+#define bFM3_INTREQ_IRQ29MON_ICU0INT3          *((volatile unsigned int*)(0x4262110CUL))\r
+#define bFM3_INTREQ_IRQ29MON_ICU1INT0          *((volatile unsigned int*)(0x42621110UL))\r
+#define bFM3_INTREQ_IRQ29MON_ICU1INT1          *((volatile unsigned int*)(0x42621114UL))\r
+#define bFM3_INTREQ_IRQ29MON_ICU1INT2          *((volatile unsigned int*)(0x42621118UL))\r
+#define bFM3_INTREQ_IRQ29MON_ICU1INT3          *((volatile unsigned int*)(0x4262111CUL))\r
+#define bFM3_INTREQ_IRQ30MON_OCU0INT0          *((volatile unsigned int*)(0x42621180UL))\r
+#define bFM3_INTREQ_IRQ30MON_OCU0INT1          *((volatile unsigned int*)(0x42621184UL))\r
+#define bFM3_INTREQ_IRQ30MON_OCU0INT2          *((volatile unsigned int*)(0x42621188UL))\r
+#define bFM3_INTREQ_IRQ30MON_OCU0INT3          *((volatile unsigned int*)(0x4262118CUL))\r
+#define bFM3_INTREQ_IRQ30MON_OCU0INT4          *((volatile unsigned int*)(0x42621190UL))\r
+#define bFM3_INTREQ_IRQ30MON_OCU0INT5          *((volatile unsigned int*)(0x42621194UL))\r
+#define bFM3_INTREQ_IRQ30MON_OCU1INT0          *((volatile unsigned int*)(0x42621198UL))\r
+#define bFM3_INTREQ_IRQ30MON_OCU1INT1          *((volatile unsigned int*)(0x4262119CUL))\r
+#define bFM3_INTREQ_IRQ30MON_OCU1INT2          *((volatile unsigned int*)(0x426211A0UL))\r
+#define bFM3_INTREQ_IRQ30MON_OCU1INT3          *((volatile unsigned int*)(0x426211A4UL))\r
+#define bFM3_INTREQ_IRQ30MON_OCU1INT4          *((volatile unsigned int*)(0x426211A8UL))\r
+#define bFM3_INTREQ_IRQ30MON_OCU1INT5          *((volatile unsigned int*)(0x426211ACUL))\r
+#define bFM3_INTREQ_IRQ31MON_BTINT0            *((volatile unsigned int*)(0x42621200UL))\r
+#define bFM3_INTREQ_IRQ31MON_BTINT1            *((volatile unsigned int*)(0x42621204UL))\r
+#define bFM3_INTREQ_IRQ31MON_BTINT2            *((volatile unsigned int*)(0x42621208UL))\r
+#define bFM3_INTREQ_IRQ31MON_BTINT3            *((volatile unsigned int*)(0x4262120CUL))\r
+#define bFM3_INTREQ_IRQ31MON_BTINT4            *((volatile unsigned int*)(0x42621210UL))\r
+#define bFM3_INTREQ_IRQ31MON_BTINT5            *((volatile unsigned int*)(0x42621214UL))\r
+#define bFM3_INTREQ_IRQ31MON_BTINT6            *((volatile unsigned int*)(0x42621218UL))\r
+#define bFM3_INTREQ_IRQ31MON_BTINT7            *((volatile unsigned int*)(0x4262121CUL))\r
+#define bFM3_INTREQ_IRQ31MON_BTINT8            *((volatile unsigned int*)(0x42621220UL))\r
+#define bFM3_INTREQ_IRQ31MON_BTINT9            *((volatile unsigned int*)(0x42621224UL))\r
+#define bFM3_INTREQ_IRQ31MON_BTINT10           *((volatile unsigned int*)(0x42621228UL))\r
+#define bFM3_INTREQ_IRQ31MON_BTINT11           *((volatile unsigned int*)(0x4262122CUL))\r
+#define bFM3_INTREQ_IRQ31MON_BTINT12           *((volatile unsigned int*)(0x42621230UL))\r
+#define bFM3_INTREQ_IRQ31MON_BTINT13           *((volatile unsigned int*)(0x42621234UL))\r
+#define bFM3_INTREQ_IRQ31MON_BTINT14           *((volatile unsigned int*)(0x42621238UL))\r
+#define bFM3_INTREQ_IRQ31MON_BTINT15           *((volatile unsigned int*)(0x4262123CUL))\r
+#define bFM3_INTREQ_IRQ34MON_USB0INT0          *((volatile unsigned int*)(0x42621380UL))\r
+#define bFM3_INTREQ_IRQ34MON_USB0INT1          *((volatile unsigned int*)(0x42621384UL))\r
+#define bFM3_INTREQ_IRQ34MON_USB0INT2          *((volatile unsigned int*)(0x42621388UL))\r
+#define bFM3_INTREQ_IRQ34MON_USB0INT3          *((volatile unsigned int*)(0x4262138CUL))\r
+#define bFM3_INTREQ_IRQ34MON_USB0INT4          *((volatile unsigned int*)(0x42621390UL))\r
+#define bFM3_INTREQ_IRQ35MON_USB0INT0          *((volatile unsigned int*)(0x42621400UL))\r
+#define bFM3_INTREQ_IRQ35MON_USB0INT1          *((volatile unsigned int*)(0x42621404UL))\r
+#define bFM3_INTREQ_IRQ35MON_USB0INT2          *((volatile unsigned int*)(0x42621408UL))\r
+#define bFM3_INTREQ_IRQ35MON_USB0INT3          *((volatile unsigned int*)(0x4262140CUL))\r
+#define bFM3_INTREQ_IRQ35MON_USB0INT4          *((volatile unsigned int*)(0x42621410UL))\r
+#define bFM3_INTREQ_IRQ35MON_USB0INT5          *((volatile unsigned int*)(0x42621414UL))\r
+#define bFM3_INTREQ_IRQ38MON_DMAINT            *((volatile unsigned int*)(0x42621580UL))\r
+#define bFM3_INTREQ_IRQ39MON_DMAINT            *((volatile unsigned int*)(0x42621600UL))\r
+#define bFM3_INTREQ_IRQ40MON_DMAINT            *((volatile unsigned int*)(0x42621680UL))\r
+#define bFM3_INTREQ_IRQ41MON_DMAINT            *((volatile unsigned int*)(0x42621700UL))\r
+#define bFM3_INTREQ_IRQ42MON_DMAINT            *((volatile unsigned int*)(0x42621780UL))\r
+#define bFM3_INTREQ_IRQ43MON_DMAINT            *((volatile unsigned int*)(0x42621800UL))\r
+#define bFM3_INTREQ_IRQ44MON_DMAINT            *((volatile unsigned int*)(0x42621880UL))\r
+#define bFM3_INTREQ_IRQ45MON_DMAINT            *((volatile unsigned int*)(0x42621900UL))\r
+\r
+/* General purpose I/O registers */\r
+#define bFM3_GPIO_PFR0_P0                      *((volatile unsigned int*)(0x42660000UL))\r
+#define bFM3_GPIO_PFR0_P1                      *((volatile unsigned int*)(0x42660004UL))\r
+#define bFM3_GPIO_PFR0_P2                      *((volatile unsigned int*)(0x42660008UL))\r
+#define bFM3_GPIO_PFR0_P3                      *((volatile unsigned int*)(0x4266000CUL))\r
+#define bFM3_GPIO_PFR0_P4                      *((volatile unsigned int*)(0x42660010UL))\r
+#define bFM3_GPIO_PFR0_PA                      *((volatile unsigned int*)(0x42660028UL))\r
+#define bFM3_GPIO_PFR0_PB                      *((volatile unsigned int*)(0x4266002CUL))\r
+#define bFM3_GPIO_PFR0_PC                      *((volatile unsigned int*)(0x42660030UL))\r
+#define bFM3_GPIO_PFR0_PF                      *((volatile unsigned int*)(0x4266003CUL))\r
+#define bFM3_GPIO_PFR1_P0                      *((volatile unsigned int*)(0x42660080UL))\r
+#define bFM3_GPIO_PFR1_P1                      *((volatile unsigned int*)(0x42660084UL))\r
+#define bFM3_GPIO_PFR1_P2                      *((volatile unsigned int*)(0x42660088UL))\r
+#define bFM3_GPIO_PFR1_P3                      *((volatile unsigned int*)(0x4266008CUL))\r
+#define bFM3_GPIO_PFR1_P4                      *((volatile unsigned int*)(0x42660090UL))\r
+#define bFM3_GPIO_PFR1_P5                      *((volatile unsigned int*)(0x42660094UL))\r
+#define bFM3_GPIO_PFR1_P7                      *((volatile unsigned int*)(0x4266009CUL))\r
+#define bFM3_GPIO_PFR1_P8                      *((volatile unsigned int*)(0x426600A0UL))\r
+#define bFM3_GPIO_PFR1_P9                      *((volatile unsigned int*)(0x426600A4UL))\r
+#define bFM3_GPIO_PFR2_P1                      *((volatile unsigned int*)(0x42660104UL))\r
+#define bFM3_GPIO_PFR2_P2                      *((volatile unsigned int*)(0x42660108UL))\r
+#define bFM3_GPIO_PFR2_P3                      *((volatile unsigned int*)(0x4266010CUL))\r
+#define bFM3_GPIO_PFR3_P0                      *((volatile unsigned int*)(0x42660180UL))\r
+#define bFM3_GPIO_PFR3_P1                      *((volatile unsigned int*)(0x42660184UL))\r
+#define bFM3_GPIO_PFR3_P2                      *((volatile unsigned int*)(0x42660188UL))\r
+#define bFM3_GPIO_PFR3_P3                      *((volatile unsigned int*)(0x4266018CUL))\r
+#define bFM3_GPIO_PFR3_P9                      *((volatile unsigned int*)(0x426601A4UL))\r
+#define bFM3_GPIO_PFR3_PA                      *((volatile unsigned int*)(0x426601A8UL))\r
+#define bFM3_GPIO_PFR3_PB                      *((volatile unsigned int*)(0x426601ACUL))\r
+#define bFM3_GPIO_PFR3_PC                      *((volatile unsigned int*)(0x426601B0UL))\r
+#define bFM3_GPIO_PFR3_PD                      *((volatile unsigned int*)(0x426601B4UL))\r
+#define bFM3_GPIO_PFR3_PE                      *((volatile unsigned int*)(0x426601B8UL))\r
+#define bFM3_GPIO_PFR3_PF                      *((volatile unsigned int*)(0x426601BCUL))\r
+#define bFM3_GPIO_PFR4_P6                      *((volatile unsigned int*)(0x42660218UL))\r
+#define bFM3_GPIO_PFR4_P7                      *((volatile unsigned int*)(0x4266021CUL))\r
+#define bFM3_GPIO_PFR4_P9                      *((volatile unsigned int*)(0x42660224UL))\r
+#define bFM3_GPIO_PFR4_PA                      *((volatile unsigned int*)(0x42660228UL))\r
+#define bFM3_GPIO_PFR4_PB                      *((volatile unsigned int*)(0x4266022CUL))\r
+#define bFM3_GPIO_PFR4_PC                      *((volatile unsigned int*)(0x42660230UL))\r
+#define bFM3_GPIO_PFR4_PD                      *((volatile unsigned int*)(0x42660234UL))\r
+#define bFM3_GPIO_PFR4_PE                      *((volatile unsigned int*)(0x42660238UL))\r
+#define bFM3_GPIO_PFR5_P0                      *((volatile unsigned int*)(0x42660280UL))\r
+#define bFM3_GPIO_PFR5_P1                      *((volatile unsigned int*)(0x42660284UL))\r
+#define bFM3_GPIO_PFR5_P2                      *((volatile unsigned int*)(0x42660288UL))\r
+#define bFM3_GPIO_PFR6_P0                      *((volatile unsigned int*)(0x42660300UL))\r
+#define bFM3_GPIO_PFR6_P1                      *((volatile unsigned int*)(0x42660304UL))\r
+#define bFM3_GPIO_PFR6_P2                      *((volatile unsigned int*)(0x42660308UL))\r
+#define bFM3_GPIO_PFR8_P0                      *((volatile unsigned int*)(0x42660400UL))\r
+#define bFM3_GPIO_PFR8_P1                      *((volatile unsigned int*)(0x42660404UL))\r
+#define bFM3_GPIO_PFRE_P0                      *((volatile unsigned int*)(0x42660700UL))\r
+#define bFM3_GPIO_PFRE_P2                      *((volatile unsigned int*)(0x42660708UL))\r
+#define bFM3_GPIO_PFRE_P3                      *((volatile unsigned int*)(0x4266070CUL))\r
+#define bFM3_GPIO_PCR0_P0                      *((volatile unsigned int*)(0x42662000UL))\r
+#define bFM3_GPIO_PCR0_P1                      *((volatile unsigned int*)(0x42662004UL))\r
+#define bFM3_GPIO_PCR0_P2                      *((volatile unsigned int*)(0x42662008UL))\r
+#define bFM3_GPIO_PCR0_P3                      *((volatile unsigned int*)(0x4266200CUL))\r
+#define bFM3_GPIO_PCR0_P4                      *((volatile unsigned int*)(0x42662010UL))\r
+#define bFM3_GPIO_PCR0_PA                      *((volatile unsigned int*)(0x42662028UL))\r
+#define bFM3_GPIO_PCR0_PB                      *((volatile unsigned int*)(0x4266202CUL))\r
+#define bFM3_GPIO_PCR0_PC                      *((volatile unsigned int*)(0x42662030UL))\r
+#define bFM3_GPIO_PCR0_PF                      *((volatile unsigned int*)(0x4266203CUL))\r
+#define bFM3_GPIO_PCR1_P0                      *((volatile unsigned int*)(0x42662080UL))\r
+#define bFM3_GPIO_PCR1_P1                      *((volatile unsigned int*)(0x42662084UL))\r
+#define bFM3_GPIO_PCR1_P2                      *((volatile unsigned int*)(0x42662088UL))\r
+#define bFM3_GPIO_PCR1_P3                      *((volatile unsigned int*)(0x4266208CUL))\r
+#define bFM3_GPIO_PCR1_P4                      *((volatile unsigned int*)(0x42662090UL))\r
+#define bFM3_GPIO_PCR1_P5                      *((volatile unsigned int*)(0x42662094UL))\r
+#define bFM3_GPIO_PCR1_P7                      *((volatile unsigned int*)(0x4266209CUL))\r
+#define bFM3_GPIO_PCR1_P8                      *((volatile unsigned int*)(0x426620A0UL))\r
+#define bFM3_GPIO_PCR1_P9                      *((volatile unsigned int*)(0x426620A4UL))\r
+#define bFM3_GPIO_PCR2_P1                      *((volatile unsigned int*)(0x42662104UL))\r
+#define bFM3_GPIO_PCR2_P2                      *((volatile unsigned int*)(0x42662108UL))\r
+#define bFM3_GPIO_PCR2_P3                      *((volatile unsigned int*)(0x4266210CUL))\r
+#define bFM3_GPIO_PCR3_P0                      *((volatile unsigned int*)(0x42662180UL))\r
+#define bFM3_GPIO_PCR3_P1                      *((volatile unsigned int*)(0x42662184UL))\r
+#define bFM3_GPIO_PCR3_P2                      *((volatile unsigned int*)(0x42662188UL))\r
+#define bFM3_GPIO_PCR3_P3                      *((volatile unsigned int*)(0x4266218CUL))\r
+#define bFM3_GPIO_PCR3_P9                      *((volatile unsigned int*)(0x426621A4UL))\r
+#define bFM3_GPIO_PCR3_PA                      *((volatile unsigned int*)(0x426621A8UL))\r
+#define bFM3_GPIO_PCR3_PB                      *((volatile unsigned int*)(0x426621ACUL))\r
+#define bFM3_GPIO_PCR3_PC                      *((volatile unsigned int*)(0x426621B0UL))\r
+#define bFM3_GPIO_PCR3_PD                      *((volatile unsigned int*)(0x426621B4UL))\r
+#define bFM3_GPIO_PCR3_PE                      *((volatile unsigned int*)(0x426621B8UL))\r
+#define bFM3_GPIO_PCR3_PF                      *((volatile unsigned int*)(0x426621BCUL))\r
+#define bFM3_GPIO_PCR4_P6                      *((volatile unsigned int*)(0x42662218UL))\r
+#define bFM3_GPIO_PCR4_P7                      *((volatile unsigned int*)(0x4266221CUL))\r
+#define bFM3_GPIO_PCR4_P9                      *((volatile unsigned int*)(0x42662224UL))\r
+#define bFM3_GPIO_PCR4_PA                      *((volatile unsigned int*)(0x42662228UL))\r
+#define bFM3_GPIO_PCR4_PB                      *((volatile unsigned int*)(0x4266222CUL))\r
+#define bFM3_GPIO_PCR4_PC                      *((volatile unsigned int*)(0x42662230UL))\r
+#define bFM3_GPIO_PCR4_PD                      *((volatile unsigned int*)(0x42662234UL))\r
+#define bFM3_GPIO_PCR4_PE                      *((volatile unsigned int*)(0x42662238UL))\r
+#define bFM3_GPIO_PCR5_P0                      *((volatile unsigned int*)(0x42662280UL))\r
+#define bFM3_GPIO_PCR5_P1                      *((volatile unsigned int*)(0x42662284UL))\r
+#define bFM3_GPIO_PCR5_P2                      *((volatile unsigned int*)(0x42662288UL))\r
+#define bFM3_GPIO_PCR6_P0                      *((volatile unsigned int*)(0x42662300UL))\r
+#define bFM3_GPIO_PCR6_P1                      *((volatile unsigned int*)(0x42662304UL))\r
+#define bFM3_GPIO_PCR6_P2                      *((volatile unsigned int*)(0x42662308UL))\r
+#define bFM3_GPIO_PCRE_P0                      *((volatile unsigned int*)(0x42662700UL))\r
+#define bFM3_GPIO_PCRE_P2                      *((volatile unsigned int*)(0x42662708UL))\r
+#define bFM3_GPIO_PCRE_P3                      *((volatile unsigned int*)(0x4266270CUL))\r
+#define bFM3_GPIO_DDR0_P0                      *((volatile unsigned int*)(0x42664000UL))\r
+#define bFM3_GPIO_DDR0_P1                      *((volatile unsigned int*)(0x42664004UL))\r
+#define bFM3_GPIO_DDR0_P2                      *((volatile unsigned int*)(0x42664008UL))\r
+#define bFM3_GPIO_DDR0_P3                      *((volatile unsigned int*)(0x4266400CUL))\r
+#define bFM3_GPIO_DDR0_P4                      *((volatile unsigned int*)(0x42664010UL))\r
+#define bFM3_GPIO_DDR0_PA                      *((volatile unsigned int*)(0x42664028UL))\r
+#define bFM3_GPIO_DDR0_PB                      *((volatile unsigned int*)(0x4266402CUL))\r
+#define bFM3_GPIO_DDR0_PC                      *((volatile unsigned int*)(0x42664030UL))\r
+#define bFM3_GPIO_DDR0_PF                      *((volatile unsigned int*)(0x4266403CUL))\r
+#define bFM3_GPIO_DDR1_P0                      *((volatile unsigned int*)(0x42664080UL))\r
+#define bFM3_GPIO_DDR1_P1                      *((volatile unsigned int*)(0x42664084UL))\r
+#define bFM3_GPIO_DDR1_P2                      *((volatile unsigned int*)(0x42664088UL))\r
+#define bFM3_GPIO_DDR1_P3                      *((volatile unsigned int*)(0x4266408CUL))\r
+#define bFM3_GPIO_DDR1_P4                      *((volatile unsigned int*)(0x42664090UL))\r
+#define bFM3_GPIO_DDR1_P5                      *((volatile unsigned int*)(0x42664094UL))\r
+#define bFM3_GPIO_DDR1_P7                      *((volatile unsigned int*)(0x4266409CUL))\r
+#define bFM3_GPIO_DDR1_P8                      *((volatile unsigned int*)(0x426640A0UL))\r
+#define bFM3_GPIO_DDR1_P9                      *((volatile unsigned int*)(0x426640A4UL))\r
+#define bFM3_GPIO_DDR2_P1                      *((volatile unsigned int*)(0x42664104UL))\r
+#define bFM3_GPIO_DDR2_P2                      *((volatile unsigned int*)(0x42664108UL))\r
+#define bFM3_GPIO_DDR2_P3                      *((volatile unsigned int*)(0x4266410CUL))\r
+#define bFM3_GPIO_DDR3_P0                      *((volatile unsigned int*)(0x42664180UL))\r
+#define bFM3_GPIO_DDR3_P1                      *((volatile unsigned int*)(0x42664184UL))\r
+#define bFM3_GPIO_DDR3_P2                      *((volatile unsigned int*)(0x42664188UL))\r
+#define bFM3_GPIO_DDR3_P3                      *((volatile unsigned int*)(0x4266418CUL))\r
+#define bFM3_GPIO_DDR3_P9                      *((volatile unsigned int*)(0x426641A4UL))\r
+#define bFM3_GPIO_DDR3_PA                      *((volatile unsigned int*)(0x426641A8UL))\r
+#define bFM3_GPIO_DDR3_PB                      *((volatile unsigned int*)(0x426641ACUL))\r
+#define bFM3_GPIO_DDR3_PC                      *((volatile unsigned int*)(0x426641B0UL))\r
+#define bFM3_GPIO_DDR3_PD                      *((volatile unsigned int*)(0x426641B4UL))\r
+#define bFM3_GPIO_DDR3_PE                      *((volatile unsigned int*)(0x426641B8UL))\r
+#define bFM3_GPIO_DDR3_PF                      *((volatile unsigned int*)(0x426641BCUL))\r
+#define bFM3_GPIO_DDR4_P6                      *((volatile unsigned int*)(0x42664218UL))\r
+#define bFM3_GPIO_DDR4_P7                      *((volatile unsigned int*)(0x4266421CUL))\r
+#define bFM3_GPIO_DDR4_P9                      *((volatile unsigned int*)(0x42664224UL))\r
+#define bFM3_GPIO_DDR4_PA                      *((volatile unsigned int*)(0x42664228UL))\r
+#define bFM3_GPIO_DDR4_PB                      *((volatile unsigned int*)(0x4266422CUL))\r
+#define bFM3_GPIO_DDR4_PC                      *((volatile unsigned int*)(0x42664230UL))\r
+#define bFM3_GPIO_DDR4_PD                      *((volatile unsigned int*)(0x42664234UL))\r
+#define bFM3_GPIO_DDR4_PE                      *((volatile unsigned int*)(0x42664238UL))\r
+#define bFM3_GPIO_DDR5_P0                      *((volatile unsigned int*)(0x42664280UL))\r
+#define bFM3_GPIO_DDR5_P1                      *((volatile unsigned int*)(0x42664284UL))\r
+#define bFM3_GPIO_DDR5_P2                      *((volatile unsigned int*)(0x42664288UL))\r
+#define bFM3_GPIO_DDR6_P0                      *((volatile unsigned int*)(0x42664300UL))\r
+#define bFM3_GPIO_DDR6_P1                      *((volatile unsigned int*)(0x42664304UL))\r
+#define bFM3_GPIO_DDR6_P2                      *((volatile unsigned int*)(0x42664308UL))\r
+#define bFM3_GPIO_DDR8_P0                      *((volatile unsigned int*)(0x42664400UL))\r
+#define bFM3_GPIO_DDR8_P1                      *((volatile unsigned int*)(0x42664404UL))\r
+#define bFM3_GPIO_DDRE_P0                      *((volatile unsigned int*)(0x42664700UL))\r
+#define bFM3_GPIO_DDRE_P2                      *((volatile unsigned int*)(0x42664708UL))\r
+#define bFM3_GPIO_DDRE_P3                      *((volatile unsigned int*)(0x4266470CUL))\r
+#define bFM3_GPIO_PDIR0_P0                     *((volatile unsigned int*)(0x42666000UL))\r
+#define bFM3_GPIO_PDIR0_P1                     *((volatile unsigned int*)(0x42666004UL))\r
+#define bFM3_GPIO_PDIR0_P2                     *((volatile unsigned int*)(0x42666008UL))\r
+#define bFM3_GPIO_PDIR0_P3                     *((volatile unsigned int*)(0x4266600CUL))\r
+#define bFM3_GPIO_PDIR0_P4                     *((volatile unsigned int*)(0x42666010UL))\r
+#define bFM3_GPIO_PDIR0_PA                     *((volatile unsigned int*)(0x42666028UL))\r
+#define bFM3_GPIO_PDIR0_PB                     *((volatile unsigned int*)(0x4266602CUL))\r
+#define bFM3_GPIO_PDIR0_PC                     *((volatile unsigned int*)(0x42666030UL))\r
+#define bFM3_GPIO_PDIR0_PF                     *((volatile unsigned int*)(0x4266603CUL))\r
+#define bFM3_GPIO_PDIR1_P0                     *((volatile unsigned int*)(0x42666080UL))\r
+#define bFM3_GPIO_PDIR1_P1                     *((volatile unsigned int*)(0x42666084UL))\r
+#define bFM3_GPIO_PDIR1_P2                     *((volatile unsigned int*)(0x42666088UL))\r
+#define bFM3_GPIO_PDIR1_P3                     *((volatile unsigned int*)(0x4266608CUL))\r
+#define bFM3_GPIO_PDIR1_P4                     *((volatile unsigned int*)(0x42666090UL))\r
+#define bFM3_GPIO_PDIR1_P5                     *((volatile unsigned int*)(0x42666094UL))\r
+#define bFM3_GPIO_PDIR1_P7                     *((volatile unsigned int*)(0x4266609CUL))\r
+#define bFM3_GPIO_PDIR1_P8                     *((volatile unsigned int*)(0x426660A0UL))\r
+#define bFM3_GPIO_PDIR1_P9                     *((volatile unsigned int*)(0x426660A4UL))\r
+#define bFM3_GPIO_PDIR2_P1                     *((volatile unsigned int*)(0x42666104UL))\r
+#define bFM3_GPIO_PDIR2_P2                     *((volatile unsigned int*)(0x42666108UL))\r
+#define bFM3_GPIO_PDIR2_P3                     *((volatile unsigned int*)(0x4266610CUL))\r
+#define bFM3_GPIO_PDIR3_P0                     *((volatile unsigned int*)(0x42666180UL))\r
+#define bFM3_GPIO_PDIR3_P1                     *((volatile unsigned int*)(0x42666184UL))\r
+#define bFM3_GPIO_PDIR3_P2                     *((volatile unsigned int*)(0x42666188UL))\r
+#define bFM3_GPIO_PDIR3_P3                     *((volatile unsigned int*)(0x4266618CUL))\r
+#define bFM3_GPIO_PDIR3_P9                     *((volatile unsigned int*)(0x426661A4UL))\r
+#define bFM3_GPIO_PDIR3_PA                     *((volatile unsigned int*)(0x426661A8UL))\r
+#define bFM3_GPIO_PDIR3_PB                     *((volatile unsigned int*)(0x426661ACUL))\r
+#define bFM3_GPIO_PDIR3_PC                     *((volatile unsigned int*)(0x426661B0UL))\r
+#define bFM3_GPIO_PDIR3_PD                     *((volatile unsigned int*)(0x426661B4UL))\r
+#define bFM3_GPIO_PDIR3_PE                     *((volatile unsigned int*)(0x426661B8UL))\r
+#define bFM3_GPIO_PDIR3_PF                     *((volatile unsigned int*)(0x426661BCUL))\r
+#define bFM3_GPIO_PDIR4_P6                     *((volatile unsigned int*)(0x42666218UL))\r
+#define bFM3_GPIO_PDIR4_P7                     *((volatile unsigned int*)(0x4266621CUL))\r
+#define bFM3_GPIO_PDIR4_P9                     *((volatile unsigned int*)(0x42666224UL))\r
+#define bFM3_GPIO_PDIR4_PA                     *((volatile unsigned int*)(0x42666228UL))\r
+#define bFM3_GPIO_PDIR4_PB                     *((volatile unsigned int*)(0x4266622CUL))\r
+#define bFM3_GPIO_PDIR4_PC                     *((volatile unsigned int*)(0x42666230UL))\r
+#define bFM3_GPIO_PDIR4_PD                     *((volatile unsigned int*)(0x42666234UL))\r
+#define bFM3_GPIO_PDIR4_PE                     *((volatile unsigned int*)(0x42666238UL))\r
+#define bFM3_GPIO_PDIR5_P0                     *((volatile unsigned int*)(0x42666280UL))\r
+#define bFM3_GPIO_PDIR5_P1                     *((volatile unsigned int*)(0x42666284UL))\r
+#define bFM3_GPIO_PDIR5_P2                     *((volatile unsigned int*)(0x42666288UL))\r
+#define bFM3_GPIO_PDIR6_P0                     *((volatile unsigned int*)(0x42666300UL))\r
+#define bFM3_GPIO_PDIR6_P1                     *((volatile unsigned int*)(0x42666304UL))\r
+#define bFM3_GPIO_PDIR6_P2                     *((volatile unsigned int*)(0x42666308UL))\r
+#define bFM3_GPIO_PDIR8_P0                     *((volatile unsigned int*)(0x42666400UL))\r
+#define bFM3_GPIO_PDIR8_P1                     *((volatile unsigned int*)(0x42666404UL))\r
+#define bFM3_GPIO_PDIRE_P0                     *((volatile unsigned int*)(0x42666700UL))\r
+#define bFM3_GPIO_PDIRE_P2                     *((volatile unsigned int*)(0x42666708UL))\r
+#define bFM3_GPIO_PDIRE_P3                     *((volatile unsigned int*)(0x4266670CUL))\r
+#define bFM3_GPIO_PDOR0_P0                     *((volatile unsigned int*)(0x42668000UL))\r
+#define bFM3_GPIO_PDOR0_P1                     *((volatile unsigned int*)(0x42668004UL))\r
+#define bFM3_GPIO_PDOR0_P2                     *((volatile unsigned int*)(0x42668008UL))\r
+#define bFM3_GPIO_PDOR0_P3                     *((volatile unsigned int*)(0x4266800CUL))\r
+#define bFM3_GPIO_PDOR0_P4                     *((volatile unsigned int*)(0x42668010UL))\r
+#define bFM3_GPIO_PDOR0_PA                     *((volatile unsigned int*)(0x42668028UL))\r
+#define bFM3_GPIO_PDOR0_PB                     *((volatile unsigned int*)(0x4266802CUL))\r
+#define bFM3_GPIO_PDOR0_PC                     *((volatile unsigned int*)(0x42668030UL))\r
+#define bFM3_GPIO_PDOR0_PF                     *((volatile unsigned int*)(0x4266803CUL))\r
+#define bFM3_GPIO_PDOR1_P0                     *((volatile unsigned int*)(0x42668080UL))\r
+#define bFM3_GPIO_PDOR1_P1                     *((volatile unsigned int*)(0x42668084UL))\r
+#define bFM3_GPIO_PDOR1_P2                     *((volatile unsigned int*)(0x42668088UL))\r
+#define bFM3_GPIO_PDOR1_P3                     *((volatile unsigned int*)(0x4266808CUL))\r
+#define bFM3_GPIO_PDOR1_P4                     *((volatile unsigned int*)(0x42668090UL))\r
+#define bFM3_GPIO_PDOR1_P5                     *((volatile unsigned int*)(0x42668094UL))\r
+#define bFM3_GPIO_PDOR1_P7                     *((volatile unsigned int*)(0x4266809CUL))\r
+#define bFM3_GPIO_PDOR1_P8                     *((volatile unsigned int*)(0x426680A0UL))\r
+#define bFM3_GPIO_PDOR1_P9                     *((volatile unsigned int*)(0x426680A4UL))\r
+#define bFM3_GPIO_PDOR2_P1                     *((volatile unsigned int*)(0x42668104UL))\r
+#define bFM3_GPIO_PDOR2_P2                     *((volatile unsigned int*)(0x42668108UL))\r
+#define bFM3_GPIO_PDOR2_P3                     *((volatile unsigned int*)(0x4266810CUL))\r
+#define bFM3_GPIO_PDOR3_P0                     *((volatile unsigned int*)(0x42668180UL))\r
+#define bFM3_GPIO_PDOR3_P1                     *((volatile unsigned int*)(0x42668184UL))\r
+#define bFM3_GPIO_PDOR3_P2                     *((volatile unsigned int*)(0x42668188UL))\r
+#define bFM3_GPIO_PDOR3_P3                     *((volatile unsigned int*)(0x4266818CUL))\r
+#define bFM3_GPIO_PDOR3_P9                     *((volatile unsigned int*)(0x426681A4UL))\r
+#define bFM3_GPIO_PDOR3_PA                     *((volatile unsigned int*)(0x426681A8UL))\r
+#define bFM3_GPIO_PDOR3_PB                     *((volatile unsigned int*)(0x426681ACUL))\r
+#define bFM3_GPIO_PDOR3_PC                     *((volatile unsigned int*)(0x426681B0UL))\r
+#define bFM3_GPIO_PDOR3_PD                     *((volatile unsigned int*)(0x426681B4UL))\r
+#define bFM3_GPIO_PDOR3_PE                     *((volatile unsigned int*)(0x426681B8UL))\r
+#define bFM3_GPIO_PDOR3_PF                     *((volatile unsigned int*)(0x426681BCUL))\r
+#define bFM3_GPIO_PDOR4_P6                     *((volatile unsigned int*)(0x42668218UL))\r
+#define bFM3_GPIO_PDOR4_P7                     *((volatile unsigned int*)(0x4266821CUL))\r
+#define bFM3_GPIO_PDOR4_P9                     *((volatile unsigned int*)(0x42668224UL))\r
+#define bFM3_GPIO_PDOR4_PA                     *((volatile unsigned int*)(0x42668228UL))\r
+#define bFM3_GPIO_PDOR4_PB                     *((volatile unsigned int*)(0x4266822CUL))\r
+#define bFM3_GPIO_PDOR4_PC                     *((volatile unsigned int*)(0x42668230UL))\r
+#define bFM3_GPIO_PDOR4_PD                     *((volatile unsigned int*)(0x42668234UL))\r
+#define bFM3_GPIO_PDOR4_PE                     *((volatile unsigned int*)(0x42668238UL))\r
+#define bFM3_GPIO_PDOR5_P0                     *((volatile unsigned int*)(0x42668280UL))\r
+#define bFM3_GPIO_PDOR5_P1                     *((volatile unsigned int*)(0x42668284UL))\r
+#define bFM3_GPIO_PDOR5_P2                     *((volatile unsigned int*)(0x42668288UL))\r
+#define bFM3_GPIO_PDOR6_P0                     *((volatile unsigned int*)(0x42668300UL))\r
+#define bFM3_GPIO_PDOR6_P1                     *((volatile unsigned int*)(0x42668304UL))\r
+#define bFM3_GPIO_PDOR6_P2                     *((volatile unsigned int*)(0x42668308UL))\r
+#define bFM3_GPIO_PDOR8_P0                     *((volatile unsigned int*)(0x42668400UL))\r
+#define bFM3_GPIO_PDOR8_P1                     *((volatile unsigned int*)(0x42668404UL))\r
+#define bFM3_GPIO_PDORE_P0                     *((volatile unsigned int*)(0x42668700UL))\r
+#define bFM3_GPIO_PDORE_P2                     *((volatile unsigned int*)(0x42668708UL))\r
+#define bFM3_GPIO_PDORE_P3                     *((volatile unsigned int*)(0x4266870CUL))\r
+#define bFM3_GPIO_ADE_AN0                      *((volatile unsigned int*)(0x4266A000UL))\r
+#define bFM3_GPIO_ADE_AN1                      *((volatile unsigned int*)(0x4266A004UL))\r
+#define bFM3_GPIO_ADE_AN2                      *((volatile unsigned int*)(0x4266A008UL))\r
+#define bFM3_GPIO_ADE_AN3                      *((volatile unsigned int*)(0x4266A00CUL))\r
+#define bFM3_GPIO_ADE_AN4                      *((volatile unsigned int*)(0x4266A010UL))\r
+#define bFM3_GPIO_ADE_AN5                      *((volatile unsigned int*)(0x4266A014UL))\r
+#define bFM3_GPIO_ADE_AN7                      *((volatile unsigned int*)(0x4266A01CUL))\r
+#define bFM3_GPIO_ADE_AN8                      *((volatile unsigned int*)(0x4266A020UL))\r
+#define bFM3_GPIO_ADE_AN9                      *((volatile unsigned int*)(0x4266A024UL))\r
+#define bFM3_GPIO_SPSR_SUBXC                   *((volatile unsigned int*)(0x4266B000UL))\r
+#define bFM3_GPIO_SPSR_MAINXC                  *((volatile unsigned int*)(0x4266B008UL))\r
+#define bFM3_GPIO_SPSR_USB0C                   *((volatile unsigned int*)(0x4266B010UL))\r
+#define bFM3_GPIO_EPFR00_NMIS                  *((volatile unsigned int*)(0x4266C000UL))\r
+#define bFM3_GPIO_EPFR00_CROUTE0               *((volatile unsigned int*)(0x4266C004UL))\r
+#define bFM3_GPIO_EPFR00_CROUTE1               *((volatile unsigned int*)(0x4266C008UL))\r
+#define bFM3_GPIO_EPFR00_USB0PE                *((volatile unsigned int*)(0x4266C024UL))\r
+#define bFM3_GPIO_EPFR00_JTAGEN0B              *((volatile unsigned int*)(0x4266C040UL))\r
+#define bFM3_GPIO_EPFR00_JTAGEN1S              *((volatile unsigned int*)(0x4266C044UL))\r
+#define bFM3_GPIO_EPFR01_RTO00E0               *((volatile unsigned int*)(0x4266C080UL))\r
+#define bFM3_GPIO_EPFR01_RTO00E1               *((volatile unsigned int*)(0x4266C084UL))\r
+#define bFM3_GPIO_EPFR01_RTO01E0               *((volatile unsigned int*)(0x4266C088UL))\r
+#define bFM3_GPIO_EPFR01_RTO01E1               *((volatile unsigned int*)(0x4266C08CUL))\r
+#define bFM3_GPIO_EPFR01_RTO02E0               *((volatile unsigned int*)(0x4266C090UL))\r
+#define bFM3_GPIO_EPFR01_RTO02E1               *((volatile unsigned int*)(0x4266C094UL))\r
+#define bFM3_GPIO_EPFR01_RTO03E0               *((volatile unsigned int*)(0x4266C098UL))\r
+#define bFM3_GPIO_EPFR01_RTO03E1               *((volatile unsigned int*)(0x4266C09CUL))\r
+#define bFM3_GPIO_EPFR01_RTO04E0               *((volatile unsigned int*)(0x4266C0A0UL))\r
+#define bFM3_GPIO_EPFR01_RTO04E1               *((volatile unsigned int*)(0x4266C0A4UL))\r
+#define bFM3_GPIO_EPFR01_RTO05E0               *((volatile unsigned int*)(0x4266C0A8UL))\r
+#define bFM3_GPIO_EPFR01_RTO05E1               *((volatile unsigned int*)(0x4266C0ACUL))\r
+#define bFM3_GPIO_EPFR01_DTTI0C                *((volatile unsigned int*)(0x4266C0B0UL))\r
+#define bFM3_GPIO_EPFR01_DTTI0S0               *((volatile unsigned int*)(0x4266C0C0UL))\r
+#define bFM3_GPIO_EPFR01_DTTI0S1               *((volatile unsigned int*)(0x4266C0C4UL))\r
+#define bFM3_GPIO_EPFR01_FRCK0S0               *((volatile unsigned int*)(0x4266C0C8UL))\r
+#define bFM3_GPIO_EPFR01_FRCK0S1               *((volatile unsigned int*)(0x4266C0CCUL))\r
+#define bFM3_GPIO_EPFR01_IC00S0                *((volatile unsigned int*)(0x4266C0D0UL))\r
+#define bFM3_GPIO_EPFR01_IC00S1                *((volatile unsigned int*)(0x4266C0D4UL))\r
+#define bFM3_GPIO_EPFR01_IC00S2                *((volatile unsigned int*)(0x4266C0D8UL))\r
+#define bFM3_GPIO_EPFR01_IC01S0                *((volatile unsigned int*)(0x4266C0DCUL))\r
+#define bFM3_GPIO_EPFR01_IC01S1                *((volatile unsigned int*)(0x4266C0E0UL))\r
+#define bFM3_GPIO_EPFR01_IC01S2                *((volatile unsigned int*)(0x4266C0E4UL))\r
+#define bFM3_GPIO_EPFR01_IC02S0                *((volatile unsigned int*)(0x4266C0E8UL))\r
+#define bFM3_GPIO_EPFR01_IC02S1                *((volatile unsigned int*)(0x4266C0ECUL))\r
+#define bFM3_GPIO_EPFR01_IC02S2                *((volatile unsigned int*)(0x4266C0F0UL))\r
+#define bFM3_GPIO_EPFR01_IC03S0                *((volatile unsigned int*)(0x4266C0F4UL))\r
+#define bFM3_GPIO_EPFR01_IC03S1                *((volatile unsigned int*)(0x4266C0F8UL))\r
+#define bFM3_GPIO_EPFR01_IC03S2                *((volatile unsigned int*)(0x4266C0FCUL))\r
+#define bFM3_GPIO_EPFR04_TIOA0E0               *((volatile unsigned int*)(0x4266C208UL))\r
+#define bFM3_GPIO_EPFR04_TIOA0E1               *((volatile unsigned int*)(0x4266C20CUL))\r
+#define bFM3_GPIO_EPFR04_TIOB0S0               *((volatile unsigned int*)(0x4266C210UL))\r
+#define bFM3_GPIO_EPFR04_TIOB0S1               *((volatile unsigned int*)(0x4266C214UL))\r
+#define bFM3_GPIO_EPFR04_TIOA1S0               *((volatile unsigned int*)(0x4266C220UL))\r
+#define bFM3_GPIO_EPFR04_TIOA1S1               *((volatile unsigned int*)(0x4266C224UL))\r
+#define bFM3_GPIO_EPFR04_TIOA1E0               *((volatile unsigned int*)(0x4266C228UL))\r
+#define bFM3_GPIO_EPFR04_TIOA1E1               *((volatile unsigned int*)(0x4266C22CUL))\r
+#define bFM3_GPIO_EPFR04_TIOB1S0               *((volatile unsigned int*)(0x4266C230UL))\r
+#define bFM3_GPIO_EPFR04_TIOB1S1               *((volatile unsigned int*)(0x4266C234UL))\r
+#define bFM3_GPIO_EPFR04_TIOA2E0               *((volatile unsigned int*)(0x4266C248UL))\r
+#define bFM3_GPIO_EPFR04_TIOA2E1               *((volatile unsigned int*)(0x4266C24CUL))\r
+#define bFM3_GPIO_EPFR04_TIOB2S0               *((volatile unsigned int*)(0x4266C250UL))\r
+#define bFM3_GPIO_EPFR04_TIOB2S1               *((volatile unsigned int*)(0x4266C254UL))\r
+#define bFM3_GPIO_EPFR04_TIOA3S0               *((volatile unsigned int*)(0x4266C260UL))\r
+#define bFM3_GPIO_EPFR04_TIOA3S1               *((volatile unsigned int*)(0x4266C264UL))\r
+#define bFM3_GPIO_EPFR04_TIOA3E0               *((volatile unsigned int*)(0x4266C268UL))\r
+#define bFM3_GPIO_EPFR04_TIOA3E1               *((volatile unsigned int*)(0x4266C26CUL))\r
+#define bFM3_GPIO_EPFR04_TIOB3S0               *((volatile unsigned int*)(0x4266C270UL))\r
+#define bFM3_GPIO_EPFR04_TIOB3S1               *((volatile unsigned int*)(0x4266C274UL))\r
+#define bFM3_GPIO_EPFR05_TIOA4E0               *((volatile unsigned int*)(0x4266C288UL))\r
+#define bFM3_GPIO_EPFR05_TIOA4E1               *((volatile unsigned int*)(0x4266C28CUL))\r
+#define bFM3_GPIO_EPFR05_TIOB4S0               *((volatile unsigned int*)(0x4266C290UL))\r
+#define bFM3_GPIO_EPFR05_TIOB4S1               *((volatile unsigned int*)(0x4266C294UL))\r
+#define bFM3_GPIO_EPFR05_TIOA5S0               *((volatile unsigned int*)(0x4266C2A0UL))\r
+#define bFM3_GPIO_EPFR05_TIOA5S1               *((volatile unsigned int*)(0x4266C2A4UL))\r
+#define bFM3_GPIO_EPFR05_TIOA5E0               *((volatile unsigned int*)(0x4266C2A8UL))\r
+#define bFM3_GPIO_EPFR05_TIOA5E1               *((volatile unsigned int*)(0x4266C2ACUL))\r
+#define bFM3_GPIO_EPFR05_TIOB5S0               *((volatile unsigned int*)(0x4266C2B0UL))\r
+#define bFM3_GPIO_EPFR05_TIOB5S1               *((volatile unsigned int*)(0x4266C2B4UL))\r
+#define bFM3_GPIO_EPFR05_TIOA6E0               *((volatile unsigned int*)(0x4266C2C8UL))\r
+#define bFM3_GPIO_EPFR05_TIOA6E1               *((volatile unsigned int*)(0x4266C2CCUL))\r
+#define bFM3_GPIO_EPFR05_TIOB6S0               *((volatile unsigned int*)(0x4266C2D0UL))\r
+#define bFM3_GPIO_EPFR05_TIOB6S1               *((volatile unsigned int*)(0x4266C2D4UL))\r
+#define bFM3_GPIO_EPFR05_TIOA7S0               *((volatile unsigned int*)(0x4266C2E0UL))\r
+#define bFM3_GPIO_EPFR05_TIOA7S1               *((volatile unsigned int*)(0x4266C2E4UL))\r
+#define bFM3_GPIO_EPFR05_TIOA7E0               *((volatile unsigned int*)(0x4266C2E8UL))\r
+#define bFM3_GPIO_EPFR05_TIOA7E1               *((volatile unsigned int*)(0x4266C2ECUL))\r
+#define bFM3_GPIO_EPFR05_TIOB7S0               *((volatile unsigned int*)(0x4266C2F0UL))\r
+#define bFM3_GPIO_EPFR05_TIOB7S1               *((volatile unsigned int*)(0x4266C2F4UL))\r
+#define bFM3_GPIO_EPFR06_EINT00S0              *((volatile unsigned int*)(0x4266C300UL))\r
+#define bFM3_GPIO_EPFR06_EINT00S1              *((volatile unsigned int*)(0x4266C304UL))\r
+#define bFM3_GPIO_EPFR06_EINT01S0              *((volatile unsigned int*)(0x4266C308UL))\r
+#define bFM3_GPIO_EPFR06_EINT01S1              *((volatile unsigned int*)(0x4266C30CUL))\r
+#define bFM3_GPIO_EPFR06_EINT02S0              *((volatile unsigned int*)(0x4266C310UL))\r
+#define bFM3_GPIO_EPFR06_EINT02S1              *((volatile unsigned int*)(0x4266C314UL))\r
+#define bFM3_GPIO_EPFR06_EINT03S0              *((volatile unsigned int*)(0x4266C318UL))\r
+#define bFM3_GPIO_EPFR06_EINT03S1              *((volatile unsigned int*)(0x4266C31CUL))\r
+#define bFM3_GPIO_EPFR06_EINT04S0              *((volatile unsigned int*)(0x4266C320UL))\r
+#define bFM3_GPIO_EPFR06_EINT04S1              *((volatile unsigned int*)(0x4266C324UL))\r
+#define bFM3_GPIO_EPFR06_EINT05S0              *((volatile unsigned int*)(0x4266C328UL))\r
+#define bFM3_GPIO_EPFR06_EINT05S1              *((volatile unsigned int*)(0x4266C32CUL))\r
+#define bFM3_GPIO_EPFR06_EINT06S0              *((volatile unsigned int*)(0x4266C330UL))\r
+#define bFM3_GPIO_EPFR06_EINT06S1              *((volatile unsigned int*)(0x4266C334UL))\r
+#define bFM3_GPIO_EPFR06_EINT15S0              *((volatile unsigned int*)(0x4266C378UL))\r
+#define bFM3_GPIO_EPFR06_EINT15S1              *((volatile unsigned int*)(0x4266C37CUL))\r
+#define bFM3_GPIO_EPFR07_SIN0S0                *((volatile unsigned int*)(0x4266C390UL))\r
+#define bFM3_GPIO_EPFR07_SIN0S1                *((volatile unsigned int*)(0x4266C394UL))\r
+#define bFM3_GPIO_EPFR07_SOT0B0                *((volatile unsigned int*)(0x4266C398UL))\r
+#define bFM3_GPIO_EPFR07_SOT0B1                *((volatile unsigned int*)(0x4266C39CUL))\r
+#define bFM3_GPIO_EPFR07_SCK0B0                *((volatile unsigned int*)(0x4266C3A0UL))\r
+#define bFM3_GPIO_EPFR07_SCK0B1                *((volatile unsigned int*)(0x4266C3A4UL))\r
+#define bFM3_GPIO_EPFR07_SIN1S0                *((volatile unsigned int*)(0x4266C3A8UL))\r
+#define bFM3_GPIO_EPFR07_SIN1S1                *((volatile unsigned int*)(0x4266C3ACUL))\r
+#define bFM3_GPIO_EPFR07_SOT1B0                *((volatile unsigned int*)(0x4266C3B0UL))\r
+#define bFM3_GPIO_EPFR07_SOT1B1                *((volatile unsigned int*)(0x4266C3B4UL))\r
+#define bFM3_GPIO_EPFR07_SCK1B0                *((volatile unsigned int*)(0x4266C3B8UL))\r
+#define bFM3_GPIO_EPFR07_SCK1B1                *((volatile unsigned int*)(0x4266C3BCUL))\r
+#define bFM3_GPIO_EPFR07_SIN2S0                *((volatile unsigned int*)(0x4266C3C0UL))\r
+#define bFM3_GPIO_EPFR07_SIN2S1                *((volatile unsigned int*)(0x4266C3C4UL))\r
+#define bFM3_GPIO_EPFR07_SOT2B0                *((volatile unsigned int*)(0x4266C3C8UL))\r
+#define bFM3_GPIO_EPFR07_SOT2B1                *((volatile unsigned int*)(0x4266C3CCUL))\r
+#define bFM3_GPIO_EPFR07_SCK2B0                *((volatile unsigned int*)(0x4266C3D0UL))\r
+#define bFM3_GPIO_EPFR07_SCK2B1                *((volatile unsigned int*)(0x4266C3D4UL))\r
+#define bFM3_GPIO_EPFR07_SIN3S0                *((volatile unsigned int*)(0x4266C3D8UL))\r
+#define bFM3_GPIO_EPFR07_SIN3S1                *((volatile unsigned int*)(0x4266C3DCUL))\r
+#define bFM3_GPIO_EPFR07_SOT3B0                *((volatile unsigned int*)(0x4266C3E0UL))\r
+#define bFM3_GPIO_EPFR07_SOT3B1                *((volatile unsigned int*)(0x4266C3E4UL))\r
+#define bFM3_GPIO_EPFR07_SCK3B0                *((volatile unsigned int*)(0x4266C3E8UL))\r
+#define bFM3_GPIO_EPFR07_SCK3B1                *((volatile unsigned int*)(0x4266C3ECUL))\r
+#define bFM3_GPIO_EPFR08_SIN4S0                *((volatile unsigned int*)(0x4266C410UL))\r
+#define bFM3_GPIO_EPFR08_SIN4S1                *((volatile unsigned int*)(0x4266C414UL))\r
+#define bFM3_GPIO_EPFR08_SOT4B0                *((volatile unsigned int*)(0x4266C418UL))\r
+#define bFM3_GPIO_EPFR08_SOT4B1                *((volatile unsigned int*)(0x4266C41CUL))\r
+#define bFM3_GPIO_EPFR08_SCK4B0                *((volatile unsigned int*)(0x4266C420UL))\r
+#define bFM3_GPIO_EPFR08_SCK4B1                *((volatile unsigned int*)(0x4266C424UL))\r
+#define bFM3_GPIO_EPFR08_SIN5S0                *((volatile unsigned int*)(0x4266C428UL))\r
+#define bFM3_GPIO_EPFR08_SIN5S1                *((volatile unsigned int*)(0x4266C42CUL))\r
+#define bFM3_GPIO_EPFR08_SOT5B0                *((volatile unsigned int*)(0x4266C430UL))\r
+#define bFM3_GPIO_EPFR08_SOT5B1                *((volatile unsigned int*)(0x4266C434UL))\r
+#define bFM3_GPIO_EPFR08_SCK5B0                *((volatile unsigned int*)(0x4266C438UL))\r
+#define bFM3_GPIO_EPFR08_SCK5B1                *((volatile unsigned int*)(0x4266C43CUL))\r
+#define bFM3_GPIO_EPFR08_SIN6S0                *((volatile unsigned int*)(0x4266C440UL))\r
+#define bFM3_GPIO_EPFR08_SIN6S1                *((volatile unsigned int*)(0x4266C444UL))\r
+#define bFM3_GPIO_EPFR08_SOT6B0                *((volatile unsigned int*)(0x4266C448UL))\r
+#define bFM3_GPIO_EPFR08_SOT6B1                *((volatile unsigned int*)(0x4266C44CUL))\r
+#define bFM3_GPIO_EPFR08_SCK6B0                *((volatile unsigned int*)(0x4266C450UL))\r
+#define bFM3_GPIO_EPFR08_SCK6B1                *((volatile unsigned int*)(0x4266C454UL))\r
+#define bFM3_GPIO_EPFR08_SIN7S0                *((volatile unsigned int*)(0x4266C458UL))\r
+#define bFM3_GPIO_EPFR08_SIN7S1                *((volatile unsigned int*)(0x4266C45CUL))\r
+#define bFM3_GPIO_EPFR08_SOT7B0                *((volatile unsigned int*)(0x4266C460UL))\r
+#define bFM3_GPIO_EPFR08_SOT7B1                *((volatile unsigned int*)(0x4266C464UL))\r
+#define bFM3_GPIO_EPFR08_SCK7B0                *((volatile unsigned int*)(0x4266C468UL))\r
+#define bFM3_GPIO_EPFR08_SCK7B1                *((volatile unsigned int*)(0x4266C46CUL))\r
+#define bFM3_GPIO_EPFR09_QAIN0S0               *((volatile unsigned int*)(0x4266C480UL))\r
+#define bFM3_GPIO_EPFR09_QAIN0S1               *((volatile unsigned int*)(0x4266C484UL))\r
+#define bFM3_GPIO_EPFR09_QBIN0S0               *((volatile unsigned int*)(0x4266C488UL))\r
+#define bFM3_GPIO_EPFR09_QBIN0S1               *((volatile unsigned int*)(0x4266C48CUL))\r
+#define bFM3_GPIO_EPFR09_QZIN0S0               *((volatile unsigned int*)(0x4266C490UL))\r
+#define bFM3_GPIO_EPFR09_QZIN0S1               *((volatile unsigned int*)(0x4266C494UL))\r
+#define bFM3_GPIO_EPFR09_QAIN1S0               *((volatile unsigned int*)(0x4266C498UL))\r
+#define bFM3_GPIO_EPFR09_QAIN1S1               *((volatile unsigned int*)(0x4266C49CUL))\r
+#define bFM3_GPIO_EPFR09_QBIN1S0               *((volatile unsigned int*)(0x4266C4A0UL))\r
+#define bFM3_GPIO_EPFR09_QBIN1S1               *((volatile unsigned int*)(0x4266C4A4UL))\r
+#define bFM3_GPIO_EPFR09_QZIN1S0               *((volatile unsigned int*)(0x4266C4A8UL))\r
+#define bFM3_GPIO_EPFR09_QZIN1S1               *((volatile unsigned int*)(0x4266C4ACUL))\r
+#define bFM3_GPIO_EPFR09_ADTRG0S0              *((volatile unsigned int*)(0x4266C4B0UL))\r
+#define bFM3_GPIO_EPFR09_ADTRG0S1              *((volatile unsigned int*)(0x4266C4B4UL))\r
+#define bFM3_GPIO_EPFR09_ADTRG0S2              *((volatile unsigned int*)(0x4266C4B8UL))\r
+#define bFM3_GPIO_EPFR09_ADTRG0S3              *((volatile unsigned int*)(0x4266C4BCUL))\r
+#define bFM3_GPIO_EPFR09_ADTRG1S0              *((volatile unsigned int*)(0x4266C4C0UL))\r
+#define bFM3_GPIO_EPFR09_ADTRG1S1              *((volatile unsigned int*)(0x4266C4C4UL))\r
+#define bFM3_GPIO_EPFR09_ADTRG1S2              *((volatile unsigned int*)(0x4266C4C8UL))\r
+#define bFM3_GPIO_EPFR09_ADTRG1S3              *((volatile unsigned int*)(0x4266C4CCUL))\r
+\r
+/* Low voltage detection registers */\r
+#define bFM3_LVD_LVD_CTL_SVHI0                 *((volatile unsigned int*)(0x426A0008UL))\r
+#define bFM3_LVD_LVD_CTL_SVHI1                 *((volatile unsigned int*)(0x426A000CUL))\r
+#define bFM3_LVD_LVD_CTL_SVHI2                 *((volatile unsigned int*)(0x426A0010UL))\r
+#define bFM3_LVD_LVD_CTL_SVHI3                 *((volatile unsigned int*)(0x426A0014UL))\r
+#define bFM3_LVD_LVD_CTL_LVDIE                 *((volatile unsigned int*)(0x426A001CUL))\r
+#define bFM3_LVD_LVD_STR_LVDIR                 *((volatile unsigned int*)(0x426A009CUL))\r
+#define bFM3_LVD_LVD_CLR_LVDCL                 *((volatile unsigned int*)(0x426A011CUL))\r
+#define bFM3_LVD_LVD_STR2_LVDIRDY              *((volatile unsigned int*)(0x426A021CUL))\r
+\r
+/* USB clock registers */\r
+#define bFM3_USBCLK_UCCR_UCEN                  *((volatile unsigned int*)(0x426C0000UL))\r
+#define bFM3_USBCLK_UCCR_UCSEL                 *((volatile unsigned int*)(0x426C0004UL))\r
+#define bFM3_USBCLK_UPCR1_UPLLEN               *((volatile unsigned int*)(0x426C0080UL))\r
+#define bFM3_USBCLK_UPCR1_UPINC                *((volatile unsigned int*)(0x426C0084UL))\r
+#define bFM3_USBCLK_UPCR2_UPOWT0               *((volatile unsigned int*)(0x426C0100UL))\r
+#define bFM3_USBCLK_UPCR2_UPOWT1               *((volatile unsigned int*)(0x426C0104UL))\r
+#define bFM3_USBCLK_UPCR2_UPOWT2               *((volatile unsigned int*)(0x426C0108UL))\r
+#define bFM3_USBCLK_UPCR3_UPLLK0               *((volatile unsigned int*)(0x426C0180UL))\r
+#define bFM3_USBCLK_UPCR3_UPLLK1               *((volatile unsigned int*)(0x426C0184UL))\r
+#define bFM3_USBCLK_UPCR3_UPLLK2               *((volatile unsigned int*)(0x426C0188UL))\r
+#define bFM3_USBCLK_UPCR3_UPLLK3               *((volatile unsigned int*)(0x426C018CUL))\r
+#define bFM3_USBCLK_UPCR3_UPLLK4               *((volatile unsigned int*)(0x426C0190UL))\r
+#define bFM3_USBCLK_UPCR4_UPLLN0               *((volatile unsigned int*)(0x426C0200UL))\r
+#define bFM3_USBCLK_UPCR4_UPLLN1               *((volatile unsigned int*)(0x426C0204UL))\r
+#define bFM3_USBCLK_UPCR4_UPLLN2               *((volatile unsigned int*)(0x426C0208UL))\r
+#define bFM3_USBCLK_UPCR4_UPLLN3               *((volatile unsigned int*)(0x426C020CUL))\r
+#define bFM3_USBCLK_UPCR4_UPLLN4               *((volatile unsigned int*)(0x426C0210UL))\r
+#define bFM3_USBCLK_UPCR4_UPLLN5               *((volatile unsigned int*)(0x426C0214UL))\r
+#define bFM3_USBCLK_UPCR4_UPLLN6               *((volatile unsigned int*)(0x426C0218UL))\r
+#define bFM3_USBCLK_UP_STR_UPRDY               *((volatile unsigned int*)(0x426C0280UL))\r
+#define bFM3_USBCLK_UPINT_ENR_UPCSE            *((volatile unsigned int*)(0x426C0300UL))\r
+#define bFM3_USBCLK_UPINT_CLR_UPCSC            *((volatile unsigned int*)(0x426C0380UL))\r
+#define bFM3_USBCLK_UPINT_STR_UPCSI            *((volatile unsigned int*)(0x426C0400UL))\r
+#define bFM3_USBCLK_UPCR5_UPLLM0               *((volatile unsigned int*)(0x426C0480UL))\r
+#define bFM3_USBCLK_UPCR5_UPLLM1               *((volatile unsigned int*)(0x426C0484UL))\r
+#define bFM3_USBCLK_UPCR5_UPLLM2               *((volatile unsigned int*)(0x426C0488UL))\r
+#define bFM3_USBCLK_UPCR5_UPLLM3               *((volatile unsigned int*)(0x426C048CUL))\r
+#define bFM3_USBCLK_USBEN_USBEN                *((volatile unsigned int*)(0x426C0600UL))\r
+\r
+/* UART asynchronous channel 0 registers */\r
+#define bFM3_MFS0_UART_SMR_SOE                 *((volatile unsigned int*)(0x42700000UL))\r
+#define bFM3_MFS0_UART_SMR_BDS                 *((volatile unsigned int*)(0x42700008UL))\r
+#define bFM3_MFS0_UART_SMR_SBL                 *((volatile unsigned int*)(0x4270000CUL))\r
+#define bFM3_MFS0_UART_SMR_WUCR                *((volatile unsigned int*)(0x42700010UL))\r
+#define bFM3_MFS0_UART_SMR_MD0                 *((volatile unsigned int*)(0x42700014UL))\r
+#define bFM3_MFS0_UART_SMR_MD1                 *((volatile unsigned int*)(0x42700018UL))\r
+#define bFM3_MFS0_UART_SMR_MD2                 *((volatile unsigned int*)(0x4270001CUL))\r
+#define bFM3_MFS0_UART_SCR_TXE                 *((volatile unsigned int*)(0x42700020UL))\r
+#define bFM3_MFS0_UART_SCR_RXE                 *((volatile unsigned int*)(0x42700024UL))\r
+#define bFM3_MFS0_UART_SCR_TBIE                *((volatile unsigned int*)(0x42700028UL))\r
+#define bFM3_MFS0_UART_SCR_TIE                 *((volatile unsigned int*)(0x4270002CUL))\r
+#define bFM3_MFS0_UART_SCR_RIE                 *((volatile unsigned int*)(0x42700030UL))\r
+#define bFM3_MFS0_UART_SCR_UPCL                *((volatile unsigned int*)(0x4270003CUL))\r
+#define bFM3_MFS0_UART_ESCR_L0                 *((volatile unsigned int*)(0x42700080UL))\r
+#define bFM3_MFS0_UART_ESCR_L1                 *((volatile unsigned int*)(0x42700084UL))\r
+#define bFM3_MFS0_UART_ESCR_L2                 *((volatile unsigned int*)(0x42700088UL))\r
+#define bFM3_MFS0_UART_ESCR_P                  *((volatile unsigned int*)(0x4270008CUL))\r
+#define bFM3_MFS0_UART_ESCR_PEN                *((volatile unsigned int*)(0x42700090UL))\r
+#define bFM3_MFS0_UART_ESCR_INV                *((volatile unsigned int*)(0x42700094UL))\r
+#define bFM3_MFS0_UART_ESCR_ESBL               *((volatile unsigned int*)(0x42700098UL))\r
+#define bFM3_MFS0_UART_ESCR_FLWEN              *((volatile unsigned int*)(0x4270009CUL))\r
+#define bFM3_MFS0_UART_SSR_TBI                 *((volatile unsigned int*)(0x427000A0UL))\r
+#define bFM3_MFS0_UART_SSR_TDRE                *((volatile unsigned int*)(0x427000A4UL))\r
+#define bFM3_MFS0_UART_SSR_RDRF                *((volatile unsigned int*)(0x427000A8UL))\r
+#define bFM3_MFS0_UART_SSR_ORE                 *((volatile unsigned int*)(0x427000ACUL))\r
+#define bFM3_MFS0_UART_SSR_FRE                 *((volatile unsigned int*)(0x427000B0UL))\r
+#define bFM3_MFS0_UART_SSR_PE                  *((volatile unsigned int*)(0x427000B4UL))\r
+#define bFM3_MFS0_UART_SSR_REC                 *((volatile unsigned int*)(0x427000BCUL))\r
+#define bFM3_MFS0_UART_RDR_AD                  *((volatile unsigned int*)(0x42700120UL))\r
+#define bFM3_MFS0_UART_TDR_AD                  *((volatile unsigned int*)(0x42700120UL))\r
+#define bFM3_MFS0_UART_BGR_EXT                 *((volatile unsigned int*)(0x427001BCUL))\r
+#define bFM3_MFS0_UART_BGR1_EXT                *((volatile unsigned int*)(0x427001BCUL))\r
+\r
+/* UART synchronous channel 0 registers */\r
+#define bFM3_MFS0_CSIO_SMR_SOE                 *((volatile unsigned int*)(0x42700000UL))\r
+#define bFM3_MFS0_CSIO_SMR_SCKE                *((volatile unsigned int*)(0x42700004UL))\r
+#define bFM3_MFS0_CSIO_SMR_BDS                 *((volatile unsigned int*)(0x42700008UL))\r
+#define bFM3_MFS0_CSIO_SMR_SCINV               *((volatile unsigned int*)(0x4270000CUL))\r
+#define bFM3_MFS0_CSIO_SMR_WUCR                *((volatile unsigned int*)(0x42700010UL))\r
+#define bFM3_MFS0_CSIO_SMR_MD0                 *((volatile unsigned int*)(0x42700014UL))\r
+#define bFM3_MFS0_CSIO_SMR_MD1                 *((volatile unsigned int*)(0x42700018UL))\r
+#define bFM3_MFS0_CSIO_SMR_MD2                 *((volatile unsigned int*)(0x4270001CUL))\r
+#define bFM3_MFS0_CSIO_SCR_TXE                 *((volatile unsigned int*)(0x42700020UL))\r
+#define bFM3_MFS0_CSIO_SCR_RXE                 *((volatile unsigned int*)(0x42700024UL))\r
+#define bFM3_MFS0_CSIO_SCR_TBIE                *((volatile unsigned int*)(0x42700028UL))\r
+#define bFM3_MFS0_CSIO_SCR_TIE                 *((volatile unsigned int*)(0x4270002CUL))\r
+#define bFM3_MFS0_CSIO_SCR_RIE                 *((volatile unsigned int*)(0x42700030UL))\r
+#define bFM3_MFS0_CSIO_SCR_SPI                 *((volatile unsigned int*)(0x42700034UL))\r
+#define bFM3_MFS0_CSIO_SCR_MS                  *((volatile unsigned int*)(0x42700038UL))\r
+#define bFM3_MFS0_CSIO_SCR_UPCL                *((volatile unsigned int*)(0x4270003CUL))\r
+#define bFM3_MFS0_CSIO_ESCR_L0                 *((volatile unsigned int*)(0x42700080UL))\r
+#define bFM3_MFS0_CSIO_ESCR_L1                 *((volatile unsigned int*)(0x42700084UL))\r
+#define bFM3_MFS0_CSIO_ESCR_L2                 *((volatile unsigned int*)(0x42700088UL))\r
+#define bFM3_MFS0_CSIO_ESCR_WT0                *((volatile unsigned int*)(0x4270008CUL))\r
+#define bFM3_MFS0_CSIO_ESCR_WT1                *((volatile unsigned int*)(0x42700090UL))\r
+#define bFM3_MFS0_CSIO_ESCR_SOP                *((volatile unsigned int*)(0x4270009CUL))\r
+#define bFM3_MFS0_CSIO_SSR_TBI                 *((volatile unsigned int*)(0x427000A0UL))\r
+#define bFM3_MFS0_CSIO_SSR_TDRE                *((volatile unsigned int*)(0x427000A4UL))\r
+#define bFM3_MFS0_CSIO_SSR_RDRF                *((volatile unsigned int*)(0x427000A8UL))\r
+#define bFM3_MFS0_CSIO_SSR_ORE                 *((volatile unsigned int*)(0x427000ACUL))\r
+#define bFM3_MFS0_CSIO_SSR_REC                 *((volatile unsigned int*)(0x427000BCUL))\r
+\r
+/* UART LIN channel 0 registers */\r
+#define bFM3_MFS0_LIN_SMR_SOE                  *((volatile unsigned int*)(0x42700000UL))\r
+#define bFM3_MFS0_LIN_SMR_SBL                  *((volatile unsigned int*)(0x4270000CUL))\r
+#define bFM3_MFS0_LIN_SMR_WUCR                 *((volatile unsigned int*)(0x42700010UL))\r
+#define bFM3_MFS0_LIN_SMR_MD0                  *((volatile unsigned int*)(0x42700014UL))\r
+#define bFM3_MFS0_LIN_SMR_MD1                  *((volatile unsigned int*)(0x42700018UL))\r
+#define bFM3_MFS0_LIN_SMR_MD2                  *((volatile unsigned int*)(0x4270001CUL))\r
+#define bFM3_MFS0_LIN_SCR_TXE                  *((volatile unsigned int*)(0x42700020UL))\r
+#define bFM3_MFS0_LIN_SCR_RXE                  *((volatile unsigned int*)(0x42700024UL))\r
+#define bFM3_MFS0_LIN_SCR_TBIE                 *((volatile unsigned int*)(0x42700028UL))\r
+#define bFM3_MFS0_LIN_SCR_TIE                  *((volatile unsigned int*)(0x4270002CUL))\r
+#define bFM3_MFS0_LIN_SCR_RIE                  *((volatile unsigned int*)(0x42700030UL))\r
+#define bFM3_MFS0_LIN_SCR_LBR                  *((volatile unsigned int*)(0x42700034UL))\r
+#define bFM3_MFS0_LIN_SCR_MS                   *((volatile unsigned int*)(0x42700038UL))\r
+#define bFM3_MFS0_LIN_SCR_UPCL                 *((volatile unsigned int*)(0x4270003CUL))\r
+#define bFM3_MFS0_LIN_ESCR_DEL0                *((volatile unsigned int*)(0x42700080UL))\r
+#define bFM3_MFS0_LIN_ESCR_DEL1                *((volatile unsigned int*)(0x42700084UL))\r
+#define bFM3_MFS0_LIN_ESCR_LBL0                *((volatile unsigned int*)(0x42700088UL))\r
+#define bFM3_MFS0_LIN_ESCR_LBL1                *((volatile unsigned int*)(0x4270008CUL))\r
+#define bFM3_MFS0_LIN_ESCR_LBIE                *((volatile unsigned int*)(0x42700090UL))\r
+#define bFM3_MFS0_LIN_ESCR_ESBL                *((volatile unsigned int*)(0x42700098UL))\r
+#define bFM3_MFS0_LIN_SSR_TBI                  *((volatile unsigned int*)(0x427000A0UL))\r
+#define bFM3_MFS0_LIN_SSR_TDRE                 *((volatile unsigned int*)(0x427000A4UL))\r
+#define bFM3_MFS0_LIN_SSR_RDRF                 *((volatile unsigned int*)(0x427000A8UL))\r
+#define bFM3_MFS0_LIN_SSR_ORE                  *((volatile unsigned int*)(0x427000ACUL))\r
+#define bFM3_MFS0_LIN_SSR_FRE                  *((volatile unsigned int*)(0x427000B0UL))\r
+#define bFM3_MFS0_LIN_SSR_LBD                  *((volatile unsigned int*)(0x427000B4UL))\r
+#define bFM3_MFS0_LIN_SSR_REC                  *((volatile unsigned int*)(0x427000BCUL))\r
+#define bFM3_MFS0_LIN_BGR_EXT                  *((volatile unsigned int*)(0x427001BCUL))\r
+#define bFM3_MFS0_LIN_BGR1_EXT                 *((volatile unsigned int*)(0x427001BCUL))\r
+\r
+/* I2C channel 0 registers */\r
+#define bFM3_MFS0_I2C_SMR_ITST0                *((volatile unsigned int*)(0x42700000UL))\r
+#define bFM3_MFS0_I2C_SMR_ITST1                *((volatile unsigned int*)(0x42700004UL))\r
+#define bFM3_MFS0_I2C_SMR_TIE                  *((volatile unsigned int*)(0x42700008UL))\r
+#define bFM3_MFS0_I2C_SMR_RIE                  *((volatile unsigned int*)(0x4270000CUL))\r
+#define bFM3_MFS0_I2C_SMR_WUCR                 *((volatile unsigned int*)(0x42700010UL))\r
+#define bFM3_MFS0_I2C_SMR_MD0                  *((volatile unsigned int*)(0x42700014UL))\r
+#define bFM3_MFS0_I2C_SMR_MD1                  *((volatile unsigned int*)(0x42700018UL))\r
+#define bFM3_MFS0_I2C_SMR_MD2                  *((volatile unsigned int*)(0x4270001CUL))\r
+#define bFM3_MFS0_I2C_IBCR_INT                 *((volatile unsigned int*)(0x42700020UL))\r
+#define bFM3_MFS0_I2C_IBCR_BER                 *((volatile unsigned int*)(0x42700024UL))\r
+#define bFM3_MFS0_I2C_IBCR_INTE                *((volatile unsigned int*)(0x42700028UL))\r
+#define bFM3_MFS0_I2C_IBCR_CNDE                *((volatile unsigned int*)(0x4270002CUL))\r
+#define bFM3_MFS0_I2C_IBCR_WSEL                *((volatile unsigned int*)(0x42700030UL))\r
+#define bFM3_MFS0_I2C_IBCR_ACKE                *((volatile unsigned int*)(0x42700034UL))\r
+#define bFM3_MFS0_I2C_IBCR_ACT                 *((volatile unsigned int*)(0x42700038UL))\r
+#define bFM3_MFS0_I2C_IBCR_SCC                 *((volatile unsigned int*)(0x42700038UL))\r
+#define bFM3_MFS0_I2C_IBCR_MSS                 *((volatile unsigned int*)(0x4270003CUL))\r
+#define bFM3_MFS0_I2C_IBSR_BB                  *((volatile unsigned int*)(0x42700080UL))\r
+#define bFM3_MFS0_I2C_IBSR_SPC                 *((volatile unsigned int*)(0x42700084UL))\r
+#define bFM3_MFS0_I2C_IBSR_RSC                 *((volatile unsigned int*)(0x42700088UL))\r
+#define bFM3_MFS0_I2C_IBSR_AL                  *((volatile unsigned int*)(0x4270008CUL))\r
+#define bFM3_MFS0_I2C_IBSR_TRX                 *((volatile unsigned int*)(0x42700090UL))\r
+#define bFM3_MFS0_I2C_IBSR_RSA                 *((volatile unsigned int*)(0x42700094UL))\r
+#define bFM3_MFS0_I2C_IBSR_RACK                *((volatile unsigned int*)(0x42700098UL))\r
+#define bFM3_MFS0_I2C_IBSR_FBT                 *((volatile unsigned int*)(0x4270009CUL))\r
+#define bFM3_MFS0_I2C_SSR_TBI                  *((volatile unsigned int*)(0x427000A0UL))\r
+#define bFM3_MFS0_I2C_SSR_TDRE                 *((volatile unsigned int*)(0x427000A4UL))\r
+#define bFM3_MFS0_I2C_SSR_RDRF                 *((volatile unsigned int*)(0x427000A8UL))\r
+#define bFM3_MFS0_I2C_SSR_ORE                  *((volatile unsigned int*)(0x427000ACUL))\r
+#define bFM3_MFS0_I2C_SSR_TBIE                 *((volatile unsigned int*)(0x427000B0UL))\r
+#define bFM3_MFS0_I2C_SSR_DMA                  *((volatile unsigned int*)(0x427000B4UL))\r
+#define bFM3_MFS0_I2C_SSR_TSET                 *((volatile unsigned int*)(0x427000B8UL))\r
+#define bFM3_MFS0_I2C_SSR_REC                  *((volatile unsigned int*)(0x427000BCUL))\r
+#define bFM3_MFS0_I2C_ISBA_SA0                 *((volatile unsigned int*)(0x42700200UL))\r
+#define bFM3_MFS0_I2C_ISBA_SA1                 *((volatile unsigned int*)(0x42700204UL))\r
+#define bFM3_MFS0_I2C_ISBA_SA2                 *((volatile unsigned int*)(0x42700208UL))\r
+#define bFM3_MFS0_I2C_ISBA_SA3                 *((volatile unsigned int*)(0x4270020CUL))\r
+#define bFM3_MFS0_I2C_ISBA_SA4                 *((volatile unsigned int*)(0x42700210UL))\r
+#define bFM3_MFS0_I2C_ISBA_SA5                 *((volatile unsigned int*)(0x42700214UL))\r
+#define bFM3_MFS0_I2C_ISBA_SA6                 *((volatile unsigned int*)(0x42700218UL))\r
+#define bFM3_MFS0_I2C_ISBA_SAEN                *((volatile unsigned int*)(0x4270021CUL))\r
+#define bFM3_MFS0_I2C_ISMK_SM0                 *((volatile unsigned int*)(0x42700220UL))\r
+#define bFM3_MFS0_I2C_ISMK_SM1                 *((volatile unsigned int*)(0x42700224UL))\r
+#define bFM3_MFS0_I2C_ISMK_SM2                 *((volatile unsigned int*)(0x42700228UL))\r
+#define bFM3_MFS0_I2C_ISMK_SM3                 *((volatile unsigned int*)(0x4270022CUL))\r
+#define bFM3_MFS0_I2C_ISMK_SM4                 *((volatile unsigned int*)(0x42700230UL))\r
+#define bFM3_MFS0_I2C_ISMK_SM5                 *((volatile unsigned int*)(0x42700234UL))\r
+#define bFM3_MFS0_I2C_ISMK_SM6                 *((volatile unsigned int*)(0x42700238UL))\r
+#define bFM3_MFS0_I2C_ISMK_EN                  *((volatile unsigned int*)(0x4270023CUL))\r
+\r
+/* UART asynchronous channel 1 registers */\r
+#define bFM3_MFS1_UART_SMR_SOE                 *((volatile unsigned int*)(0x42702000UL))\r
+#define bFM3_MFS1_UART_SMR_BDS                 *((volatile unsigned int*)(0x42702008UL))\r
+#define bFM3_MFS1_UART_SMR_SBL                 *((volatile unsigned int*)(0x4270200CUL))\r
+#define bFM3_MFS1_UART_SMR_WUCR                *((volatile unsigned int*)(0x42702010UL))\r
+#define bFM3_MFS1_UART_SMR_MD0                 *((volatile unsigned int*)(0x42702014UL))\r
+#define bFM3_MFS1_UART_SMR_MD1                 *((volatile unsigned int*)(0x42702018UL))\r
+#define bFM3_MFS1_UART_SMR_MD2                 *((volatile unsigned int*)(0x4270201CUL))\r
+#define bFM3_MFS1_UART_SCR_TXE                 *((volatile unsigned int*)(0x42702020UL))\r
+#define bFM3_MFS1_UART_SCR_RXE                 *((volatile unsigned int*)(0x42702024UL))\r
+#define bFM3_MFS1_UART_SCR_TBIE                *((volatile unsigned int*)(0x42702028UL))\r
+#define bFM3_MFS1_UART_SCR_TIE                 *((volatile unsigned int*)(0x4270202CUL))\r
+#define bFM3_MFS1_UART_SCR_RIE                 *((volatile unsigned int*)(0x42702030UL))\r
+#define bFM3_MFS1_UART_SCR_UPCL                *((volatile unsigned int*)(0x4270203CUL))\r
+#define bFM3_MFS1_UART_ESCR_L0                 *((volatile unsigned int*)(0x42702080UL))\r
+#define bFM3_MFS1_UART_ESCR_L1                 *((volatile unsigned int*)(0x42702084UL))\r
+#define bFM3_MFS1_UART_ESCR_L2                 *((volatile unsigned int*)(0x42702088UL))\r
+#define bFM3_MFS1_UART_ESCR_P                  *((volatile unsigned int*)(0x4270208CUL))\r
+#define bFM3_MFS1_UART_ESCR_PEN                *((volatile unsigned int*)(0x42702090UL))\r
+#define bFM3_MFS1_UART_ESCR_INV                *((volatile unsigned int*)(0x42702094UL))\r
+#define bFM3_MFS1_UART_ESCR_ESBL               *((volatile unsigned int*)(0x42702098UL))\r
+#define bFM3_MFS1_UART_ESCR_FLWEN              *((volatile unsigned int*)(0x4270209CUL))\r
+#define bFM3_MFS1_UART_SSR_TBI                 *((volatile unsigned int*)(0x427020A0UL))\r
+#define bFM3_MFS1_UART_SSR_TDRE                *((volatile unsigned int*)(0x427020A4UL))\r
+#define bFM3_MFS1_UART_SSR_RDRF                *((volatile unsigned int*)(0x427020A8UL))\r
+#define bFM3_MFS1_UART_SSR_ORE                 *((volatile unsigned int*)(0x427020ACUL))\r
+#define bFM3_MFS1_UART_SSR_FRE                 *((volatile unsigned int*)(0x427020B0UL))\r
+#define bFM3_MFS1_UART_SSR_PE                  *((volatile unsigned int*)(0x427020B4UL))\r
+#define bFM3_MFS1_UART_SSR_REC                 *((volatile unsigned int*)(0x427020BCUL))\r
+#define bFM3_MFS1_UART_RDR_AD                  *((volatile unsigned int*)(0x42702120UL))\r
+#define bFM3_MFS1_UART_TDR_AD                  *((volatile unsigned int*)(0x42702120UL))\r
+#define bFM3_MFS1_UART_BGR_EXT                 *((volatile unsigned int*)(0x427021BCUL))\r
+#define bFM3_MFS1_UART_BGR1_EXT                *((volatile unsigned int*)(0x427021BCUL))\r
+\r
+/* UART synchronous channel 1 registers */\r
+#define bFM3_MFS1_CSIO_SMR_SOE                 *((volatile unsigned int*)(0x42702000UL))\r
+#define bFM3_MFS1_CSIO_SMR_SCKE                *((volatile unsigned int*)(0x42702004UL))\r
+#define bFM3_MFS1_CSIO_SMR_BDS                 *((volatile unsigned int*)(0x42702008UL))\r
+#define bFM3_MFS1_CSIO_SMR_SCINV               *((volatile unsigned int*)(0x4270200CUL))\r
+#define bFM3_MFS1_CSIO_SMR_WUCR                *((volatile unsigned int*)(0x42702010UL))\r
+#define bFM3_MFS1_CSIO_SMR_MD0                 *((volatile unsigned int*)(0x42702014UL))\r
+#define bFM3_MFS1_CSIO_SMR_MD1                 *((volatile unsigned int*)(0x42702018UL))\r
+#define bFM3_MFS1_CSIO_SMR_MD2                 *((volatile unsigned int*)(0x4270201CUL))\r
+#define bFM3_MFS1_CSIO_SCR_TXE                 *((volatile unsigned int*)(0x42702020UL))\r
+#define bFM3_MFS1_CSIO_SCR_RXE                 *((volatile unsigned int*)(0x42702024UL))\r
+#define bFM3_MFS1_CSIO_SCR_TBIE                *((volatile unsigned int*)(0x42702028UL))\r
+#define bFM3_MFS1_CSIO_SCR_TIE                 *((volatile unsigned int*)(0x4270202CUL))\r
+#define bFM3_MFS1_CSIO_SCR_RIE                 *((volatile unsigned int*)(0x42702030UL))\r
+#define bFM3_MFS1_CSIO_SCR_SPI                 *((volatile unsigned int*)(0x42702034UL))\r
+#define bFM3_MFS1_CSIO_SCR_MS                  *((volatile unsigned int*)(0x42702038UL))\r
+#define bFM3_MFS1_CSIO_SCR_UPCL                *((volatile unsigned int*)(0x4270203CUL))\r
+#define bFM3_MFS1_CSIO_ESCR_L0                 *((volatile unsigned int*)(0x42702080UL))\r
+#define bFM3_MFS1_CSIO_ESCR_L1                 *((volatile unsigned int*)(0x42702084UL))\r
+#define bFM3_MFS1_CSIO_ESCR_L2                 *((volatile unsigned int*)(0x42702088UL))\r
+#define bFM3_MFS1_CSIO_ESCR_WT0                *((volatile unsigned int*)(0x4270208CUL))\r
+#define bFM3_MFS1_CSIO_ESCR_WT1                *((volatile unsigned int*)(0x42702090UL))\r
+#define bFM3_MFS1_CSIO_ESCR_SOP                *((volatile unsigned int*)(0x4270209CUL))\r
+#define bFM3_MFS1_CSIO_SSR_TBI                 *((volatile unsigned int*)(0x427020A0UL))\r
+#define bFM3_MFS1_CSIO_SSR_TDRE                *((volatile unsigned int*)(0x427020A4UL))\r
+#define bFM3_MFS1_CSIO_SSR_RDRF                *((volatile unsigned int*)(0x427020A8UL))\r
+#define bFM3_MFS1_CSIO_SSR_ORE                 *((volatile unsigned int*)(0x427020ACUL))\r
+#define bFM3_MFS1_CSIO_SSR_REC                 *((volatile unsigned int*)(0x427020BCUL))\r
+\r
+/* UART LIN channel 1 registers */\r
+#define bFM3_MFS1_LIN_SMR_SOE                  *((volatile unsigned int*)(0x42702000UL))\r
+#define bFM3_MFS1_LIN_SMR_SBL                  *((volatile unsigned int*)(0x4270200CUL))\r
+#define bFM3_MFS1_LIN_SMR_WUCR                 *((volatile unsigned int*)(0x42702010UL))\r
+#define bFM3_MFS1_LIN_SMR_MD0                  *((volatile unsigned int*)(0x42702014UL))\r
+#define bFM3_MFS1_LIN_SMR_MD1                  *((volatile unsigned int*)(0x42702018UL))\r
+#define bFM3_MFS1_LIN_SMR_MD2                  *((volatile unsigned int*)(0x4270201CUL))\r
+#define bFM3_MFS1_LIN_SCR_TXE                  *((volatile unsigned int*)(0x42702020UL))\r
+#define bFM3_MFS1_LIN_SCR_RXE                  *((volatile unsigned int*)(0x42702024UL))\r
+#define bFM3_MFS1_LIN_SCR_TBIE                 *((volatile unsigned int*)(0x42702028UL))\r
+#define bFM3_MFS1_LIN_SCR_TIE                  *((volatile unsigned int*)(0x4270202CUL))\r
+#define bFM3_MFS1_LIN_SCR_RIE                  *((volatile unsigned int*)(0x42702030UL))\r
+#define bFM3_MFS1_LIN_SCR_LBR                  *((volatile unsigned int*)(0x42702034UL))\r
+#define bFM3_MFS1_LIN_SCR_MS                   *((volatile unsigned int*)(0x42702038UL))\r
+#define bFM3_MFS1_LIN_SCR_UPCL                 *((volatile unsigned int*)(0x4270203CUL))\r
+#define bFM3_MFS1_LIN_ESCR_DEL0                *((volatile unsigned int*)(0x42702080UL))\r
+#define bFM3_MFS1_LIN_ESCR_DEL1                *((volatile unsigned int*)(0x42702084UL))\r
+#define bFM3_MFS1_LIN_ESCR_LBL0                *((volatile unsigned int*)(0x42702088UL))\r
+#define bFM3_MFS1_LIN_ESCR_LBL1                *((volatile unsigned int*)(0x4270208CUL))\r
+#define bFM3_MFS1_LIN_ESCR_LBIE                *((volatile unsigned int*)(0x42702090UL))\r
+#define bFM3_MFS1_LIN_ESCR_ESBL                *((volatile unsigned int*)(0x42702098UL))\r
+#define bFM3_MFS1_LIN_SSR_TBI                  *((volatile unsigned int*)(0x427020A0UL))\r
+#define bFM3_MFS1_LIN_SSR_TDRE                 *((volatile unsigned int*)(0x427020A4UL))\r
+#define bFM3_MFS1_LIN_SSR_RDRF                 *((volatile unsigned int*)(0x427020A8UL))\r
+#define bFM3_MFS1_LIN_SSR_ORE                  *((volatile unsigned int*)(0x427020ACUL))\r
+#define bFM3_MFS1_LIN_SSR_FRE                  *((volatile unsigned int*)(0x427020B0UL))\r
+#define bFM3_MFS1_LIN_SSR_LBD                  *((volatile unsigned int*)(0x427020B4UL))\r
+#define bFM3_MFS1_LIN_SSR_REC                  *((volatile unsigned int*)(0x427020BCUL))\r
+#define bFM3_MFS1_LIN_BGR_EXT                  *((volatile unsigned int*)(0x427021BCUL))\r
+#define bFM3_MFS1_LIN_BGR1_EXT                 *((volatile unsigned int*)(0x427021BCUL))\r
+\r
+/* I2C channel 1 registers */\r
+#define bFM3_MFS1_I2C_SMR_ITST0                *((volatile unsigned int*)(0x42702000UL))\r
+#define bFM3_MFS1_I2C_SMR_ITST1                *((volatile unsigned int*)(0x42702004UL))\r
+#define bFM3_MFS1_I2C_SMR_TIE                  *((volatile unsigned int*)(0x42702008UL))\r
+#define bFM3_MFS1_I2C_SMR_RIE                  *((volatile unsigned int*)(0x4270200CUL))\r
+#define bFM3_MFS1_I2C_SMR_WUCR                 *((volatile unsigned int*)(0x42702010UL))\r
+#define bFM3_MFS1_I2C_SMR_MD0                  *((volatile unsigned int*)(0x42702014UL))\r
+#define bFM3_MFS1_I2C_SMR_MD1                  *((volatile unsigned int*)(0x42702018UL))\r
+#define bFM3_MFS1_I2C_SMR_MD2                  *((volatile unsigned int*)(0x4270201CUL))\r
+#define bFM3_MFS1_I2C_IBCR_INT                 *((volatile unsigned int*)(0x42702020UL))\r
+#define bFM3_MFS1_I2C_IBCR_BER                 *((volatile unsigned int*)(0x42702024UL))\r
+#define bFM3_MFS1_I2C_IBCR_INTE                *((volatile unsigned int*)(0x42702028UL))\r
+#define bFM3_MFS1_I2C_IBCR_CNDE                *((volatile unsigned int*)(0x4270202CUL))\r
+#define bFM3_MFS1_I2C_IBCR_WSEL                *((volatile unsigned int*)(0x42702030UL))\r
+#define bFM3_MFS1_I2C_IBCR_ACKE                *((volatile unsigned int*)(0x42702034UL))\r
+#define bFM3_MFS1_I2C_IBCR_ACT                 *((volatile unsigned int*)(0x42702038UL))\r
+#define bFM3_MFS1_I2C_IBCR_SCC                 *((volatile unsigned int*)(0x42702038UL))\r
+#define bFM3_MFS1_I2C_IBCR_MSS                 *((volatile unsigned int*)(0x4270203CUL))\r
+#define bFM3_MFS1_I2C_IBSR_BB                  *((volatile unsigned int*)(0x42702080UL))\r
+#define bFM3_MFS1_I2C_IBSR_SPC                 *((volatile unsigned int*)(0x42702084UL))\r
+#define bFM3_MFS1_I2C_IBSR_RSC                 *((volatile unsigned int*)(0x42702088UL))\r
+#define bFM3_MFS1_I2C_IBSR_AL                  *((volatile unsigned int*)(0x4270208CUL))\r
+#define bFM3_MFS1_I2C_IBSR_TRX                 *((volatile unsigned int*)(0x42702090UL))\r
+#define bFM3_MFS1_I2C_IBSR_RSA                 *((volatile unsigned int*)(0x42702094UL))\r
+#define bFM3_MFS1_I2C_IBSR_RACK                *((volatile unsigned int*)(0x42702098UL))\r
+#define bFM3_MFS1_I2C_IBSR_FBT                 *((volatile unsigned int*)(0x4270209CUL))\r
+#define bFM3_MFS1_I2C_SSR_TBI                  *((volatile unsigned int*)(0x427020A0UL))\r
+#define bFM3_MFS1_I2C_SSR_TDRE                 *((volatile unsigned int*)(0x427020A4UL))\r
+#define bFM3_MFS1_I2C_SSR_RDRF                 *((volatile unsigned int*)(0x427020A8UL))\r
+#define bFM3_MFS1_I2C_SSR_ORE                  *((volatile unsigned int*)(0x427020ACUL))\r
+#define bFM3_MFS1_I2C_SSR_TBIE                 *((volatile unsigned int*)(0x427020B0UL))\r
+#define bFM3_MFS1_I2C_SSR_DMA                  *((volatile unsigned int*)(0x427020B4UL))\r
+#define bFM3_MFS1_I2C_SSR_TSET                 *((volatile unsigned int*)(0x427020B8UL))\r
+#define bFM3_MFS1_I2C_SSR_REC                  *((volatile unsigned int*)(0x427020BCUL))\r
+#define bFM3_MFS1_I2C_ISBA_SA0                 *((volatile unsigned int*)(0x42702200UL))\r
+#define bFM3_MFS1_I2C_ISBA_SA1                 *((volatile unsigned int*)(0x42702204UL))\r
+#define bFM3_MFS1_I2C_ISBA_SA2                 *((volatile unsigned int*)(0x42702208UL))\r
+#define bFM3_MFS1_I2C_ISBA_SA3                 *((volatile unsigned int*)(0x4270220CUL))\r
+#define bFM3_MFS1_I2C_ISBA_SA4                 *((volatile unsigned int*)(0x42702210UL))\r
+#define bFM3_MFS1_I2C_ISBA_SA5                 *((volatile unsigned int*)(0x42702214UL))\r
+#define bFM3_MFS1_I2C_ISBA_SA6                 *((volatile unsigned int*)(0x42702218UL))\r
+#define bFM3_MFS1_I2C_ISBA_SAEN                *((volatile unsigned int*)(0x4270221CUL))\r
+#define bFM3_MFS1_I2C_ISMK_SM0                 *((volatile unsigned int*)(0x42702220UL))\r
+#define bFM3_MFS1_I2C_ISMK_SM1                 *((volatile unsigned int*)(0x42702224UL))\r
+#define bFM3_MFS1_I2C_ISMK_SM2                 *((volatile unsigned int*)(0x42702228UL))\r
+#define bFM3_MFS1_I2C_ISMK_SM3                 *((volatile unsigned int*)(0x4270222CUL))\r
+#define bFM3_MFS1_I2C_ISMK_SM4                 *((volatile unsigned int*)(0x42702230UL))\r
+#define bFM3_MFS1_I2C_ISMK_SM5                 *((volatile unsigned int*)(0x42702234UL))\r
+#define bFM3_MFS1_I2C_ISMK_SM6                 *((volatile unsigned int*)(0x42702238UL))\r
+#define bFM3_MFS1_I2C_ISMK_EN                  *((volatile unsigned int*)(0x4270223CUL))\r
+\r
+/* UART asynchronous channel 2 registers */\r
+#define bFM3_MFS2_UART_SMR_SOE                 *((volatile unsigned int*)(0x42704000UL))\r
+#define bFM3_MFS2_UART_SMR_BDS                 *((volatile unsigned int*)(0x42704008UL))\r
+#define bFM3_MFS2_UART_SMR_SBL                 *((volatile unsigned int*)(0x4270400CUL))\r
+#define bFM3_MFS2_UART_SMR_WUCR                *((volatile unsigned int*)(0x42704010UL))\r
+#define bFM3_MFS2_UART_SMR_MD0                 *((volatile unsigned int*)(0x42704014UL))\r
+#define bFM3_MFS2_UART_SMR_MD1                 *((volatile unsigned int*)(0x42704018UL))\r
+#define bFM3_MFS2_UART_SMR_MD2                 *((volatile unsigned int*)(0x4270401CUL))\r
+#define bFM3_MFS2_UART_SCR_TXE                 *((volatile unsigned int*)(0x42704020UL))\r
+#define bFM3_MFS2_UART_SCR_RXE                 *((volatile unsigned int*)(0x42704024UL))\r
+#define bFM3_MFS2_UART_SCR_TBIE                *((volatile unsigned int*)(0x42704028UL))\r
+#define bFM3_MFS2_UART_SCR_TIE                 *((volatile unsigned int*)(0x4270402CUL))\r
+#define bFM3_MFS2_UART_SCR_RIE                 *((volatile unsigned int*)(0x42704030UL))\r
+#define bFM3_MFS2_UART_SCR_UPCL                *((volatile unsigned int*)(0x4270403CUL))\r
+#define bFM3_MFS2_UART_ESCR_L0                 *((volatile unsigned int*)(0x42704080UL))\r
+#define bFM3_MFS2_UART_ESCR_L1                 *((volatile unsigned int*)(0x42704084UL))\r
+#define bFM3_MFS2_UART_ESCR_L2                 *((volatile unsigned int*)(0x42704088UL))\r
+#define bFM3_MFS2_UART_ESCR_P                  *((volatile unsigned int*)(0x4270408CUL))\r
+#define bFM3_MFS2_UART_ESCR_PEN                *((volatile unsigned int*)(0x42704090UL))\r
+#define bFM3_MFS2_UART_ESCR_INV                *((volatile unsigned int*)(0x42704094UL))\r
+#define bFM3_MFS2_UART_ESCR_ESBL               *((volatile unsigned int*)(0x42704098UL))\r
+#define bFM3_MFS2_UART_ESCR_FLWEN              *((volatile unsigned int*)(0x4270409CUL))\r
+#define bFM3_MFS2_UART_SSR_TBI                 *((volatile unsigned int*)(0x427040A0UL))\r
+#define bFM3_MFS2_UART_SSR_TDRE                *((volatile unsigned int*)(0x427040A4UL))\r
+#define bFM3_MFS2_UART_SSR_RDRF                *((volatile unsigned int*)(0x427040A8UL))\r
+#define bFM3_MFS2_UART_SSR_ORE                 *((volatile unsigned int*)(0x427040ACUL))\r
+#define bFM3_MFS2_UART_SSR_FRE                 *((volatile unsigned int*)(0x427040B0UL))\r
+#define bFM3_MFS2_UART_SSR_PE                  *((volatile unsigned int*)(0x427040B4UL))\r
+#define bFM3_MFS2_UART_SSR_REC                 *((volatile unsigned int*)(0x427040BCUL))\r
+#define bFM3_MFS2_UART_RDR_AD                  *((volatile unsigned int*)(0x42704120UL))\r
+#define bFM3_MFS2_UART_TDR_AD                  *((volatile unsigned int*)(0x42704120UL))\r
+#define bFM3_MFS2_UART_BGR_EXT                 *((volatile unsigned int*)(0x427041BCUL))\r
+#define bFM3_MFS2_UART_BGR1_EXT                *((volatile unsigned int*)(0x427041BCUL))\r
+\r
+/* UART synchronous channel 2 registers */\r
+#define bFM3_MFS2_CSIO_SMR_SOE                 *((volatile unsigned int*)(0x42704000UL))\r
+#define bFM3_MFS2_CSIO_SMR_SCKE                *((volatile unsigned int*)(0x42704004UL))\r
+#define bFM3_MFS2_CSIO_SMR_BDS                 *((volatile unsigned int*)(0x42704008UL))\r
+#define bFM3_MFS2_CSIO_SMR_SCINV               *((volatile unsigned int*)(0x4270400CUL))\r
+#define bFM3_MFS2_CSIO_SMR_WUCR                *((volatile unsigned int*)(0x42704010UL))\r
+#define bFM3_MFS2_CSIO_SMR_MD0                 *((volatile unsigned int*)(0x42704014UL))\r
+#define bFM3_MFS2_CSIO_SMR_MD1                 *((volatile unsigned int*)(0x42704018UL))\r
+#define bFM3_MFS2_CSIO_SMR_MD2                 *((volatile unsigned int*)(0x4270401CUL))\r
+#define bFM3_MFS2_CSIO_SCR_TXE                 *((volatile unsigned int*)(0x42704020UL))\r
+#define bFM3_MFS2_CSIO_SCR_RXE                 *((volatile unsigned int*)(0x42704024UL))\r
+#define bFM3_MFS2_CSIO_SCR_TBIE                *((volatile unsigned int*)(0x42704028UL))\r
+#define bFM3_MFS2_CSIO_SCR_TIE                 *((volatile unsigned int*)(0x4270402CUL))\r
+#define bFM3_MFS2_CSIO_SCR_RIE                 *((volatile unsigned int*)(0x42704030UL))\r
+#define bFM3_MFS2_CSIO_SCR_SPI                 *((volatile unsigned int*)(0x42704034UL))\r
+#define bFM3_MFS2_CSIO_SCR_MS                  *((volatile unsigned int*)(0x42704038UL))\r
+#define bFM3_MFS2_CSIO_SCR_UPCL                *((volatile unsigned int*)(0x4270403CUL))\r
+#define bFM3_MFS2_CSIO_ESCR_L0                 *((volatile unsigned int*)(0x42704080UL))\r
+#define bFM3_MFS2_CSIO_ESCR_L1                 *((volatile unsigned int*)(0x42704084UL))\r
+#define bFM3_MFS2_CSIO_ESCR_L2                 *((volatile unsigned int*)(0x42704088UL))\r
+#define bFM3_MFS2_CSIO_ESCR_WT0                *((volatile unsigned int*)(0x4270408CUL))\r
+#define bFM3_MFS2_CSIO_ESCR_WT1                *((volatile unsigned int*)(0x42704090UL))\r
+#define bFM3_MFS2_CSIO_ESCR_SOP                *((volatile unsigned int*)(0x4270409CUL))\r
+#define bFM3_MFS2_CSIO_SSR_TBI                 *((volatile unsigned int*)(0x427040A0UL))\r
+#define bFM3_MFS2_CSIO_SSR_TDRE                *((volatile unsigned int*)(0x427040A4UL))\r
+#define bFM3_MFS2_CSIO_SSR_RDRF                *((volatile unsigned int*)(0x427040A8UL))\r
+#define bFM3_MFS2_CSIO_SSR_ORE                 *((volatile unsigned int*)(0x427040ACUL))\r
+#define bFM3_MFS2_CSIO_SSR_REC                 *((volatile unsigned int*)(0x427040BCUL))\r
+\r
+/* UART LIN channel 2 registers */\r
+#define bFM3_MFS2_LIN_SMR_SOE                  *((volatile unsigned int*)(0x42704000UL))\r
+#define bFM3_MFS2_LIN_SMR_SBL                  *((volatile unsigned int*)(0x4270400CUL))\r
+#define bFM3_MFS2_LIN_SMR_WUCR                 *((volatile unsigned int*)(0x42704010UL))\r
+#define bFM3_MFS2_LIN_SMR_MD0                  *((volatile unsigned int*)(0x42704014UL))\r
+#define bFM3_MFS2_LIN_SMR_MD1                  *((volatile unsigned int*)(0x42704018UL))\r
+#define bFM3_MFS2_LIN_SMR_MD2                  *((volatile unsigned int*)(0x4270401CUL))\r
+#define bFM3_MFS2_LIN_SCR_TXE                  *((volatile unsigned int*)(0x42704020UL))\r
+#define bFM3_MFS2_LIN_SCR_RXE                  *((volatile unsigned int*)(0x42704024UL))\r
+#define bFM3_MFS2_LIN_SCR_TBIE                 *((volatile unsigned int*)(0x42704028UL))\r
+#define bFM3_MFS2_LIN_SCR_TIE                  *((volatile unsigned int*)(0x4270402CUL))\r
+#define bFM3_MFS2_LIN_SCR_RIE                  *((volatile unsigned int*)(0x42704030UL))\r
+#define bFM3_MFS2_LIN_SCR_LBR                  *((volatile unsigned int*)(0x42704034UL))\r
+#define bFM3_MFS2_LIN_SCR_MS                   *((volatile unsigned int*)(0x42704038UL))\r
+#define bFM3_MFS2_LIN_SCR_UPCL                 *((volatile unsigned int*)(0x4270403CUL))\r
+#define bFM3_MFS2_LIN_ESCR_DEL0                *((volatile unsigned int*)(0x42704080UL))\r
+#define bFM3_MFS2_LIN_ESCR_DEL1                *((volatile unsigned int*)(0x42704084UL))\r
+#define bFM3_MFS2_LIN_ESCR_LBL0                *((volatile unsigned int*)(0x42704088UL))\r
+#define bFM3_MFS2_LIN_ESCR_LBL1                *((volatile unsigned int*)(0x4270408CUL))\r
+#define bFM3_MFS2_LIN_ESCR_LBIE                *((volatile unsigned int*)(0x42704090UL))\r
+#define bFM3_MFS2_LIN_ESCR_ESBL                *((volatile unsigned int*)(0x42704098UL))\r
+#define bFM3_MFS2_LIN_SSR_TBI                  *((volatile unsigned int*)(0x427040A0UL))\r
+#define bFM3_MFS2_LIN_SSR_TDRE                 *((volatile unsigned int*)(0x427040A4UL))\r
+#define bFM3_MFS2_LIN_SSR_RDRF                 *((volatile unsigned int*)(0x427040A8UL))\r
+#define bFM3_MFS2_LIN_SSR_ORE                  *((volatile unsigned int*)(0x427040ACUL))\r
+#define bFM3_MFS2_LIN_SSR_FRE                  *((volatile unsigned int*)(0x427040B0UL))\r
+#define bFM3_MFS2_LIN_SSR_LBD                  *((volatile unsigned int*)(0x427040B4UL))\r
+#define bFM3_MFS2_LIN_SSR_REC                  *((volatile unsigned int*)(0x427040BCUL))\r
+#define bFM3_MFS2_LIN_BGR_EXT                  *((volatile unsigned int*)(0x427041BCUL))\r
+#define bFM3_MFS2_LIN_BGR1_EXT                 *((volatile unsigned int*)(0x427041BCUL))\r
+\r
+/* I2C channel 2 registers */\r
+#define bFM3_MFS2_I2C_SMR_ITST0                *((volatile unsigned int*)(0x42704000UL))\r
+#define bFM3_MFS2_I2C_SMR_ITST1                *((volatile unsigned int*)(0x42704004UL))\r
+#define bFM3_MFS2_I2C_SMR_TIE                  *((volatile unsigned int*)(0x42704008UL))\r
+#define bFM3_MFS2_I2C_SMR_RIE                  *((volatile unsigned int*)(0x4270400CUL))\r
+#define bFM3_MFS2_I2C_SMR_WUCR                 *((volatile unsigned int*)(0x42704010UL))\r
+#define bFM3_MFS2_I2C_SMR_MD0                  *((volatile unsigned int*)(0x42704014UL))\r
+#define bFM3_MFS2_I2C_SMR_MD1                  *((volatile unsigned int*)(0x42704018UL))\r
+#define bFM3_MFS2_I2C_SMR_MD2                  *((volatile unsigned int*)(0x4270401CUL))\r
+#define bFM3_MFS2_I2C_IBCR_INT                 *((volatile unsigned int*)(0x42704020UL))\r
+#define bFM3_MFS2_I2C_IBCR_BER                 *((volatile unsigned int*)(0x42704024UL))\r
+#define bFM3_MFS2_I2C_IBCR_INTE                *((volatile unsigned int*)(0x42704028UL))\r
+#define bFM3_MFS2_I2C_IBCR_CNDE                *((volatile unsigned int*)(0x4270402CUL))\r
+#define bFM3_MFS2_I2C_IBCR_WSEL                *((volatile unsigned int*)(0x42704030UL))\r
+#define bFM3_MFS2_I2C_IBCR_ACKE                *((volatile unsigned int*)(0x42704034UL))\r
+#define bFM3_MFS2_I2C_IBCR_ACT                 *((volatile unsigned int*)(0x42704038UL))\r
+#define bFM3_MFS2_I2C_IBCR_SCC                 *((volatile unsigned int*)(0x42704038UL))\r
+#define bFM3_MFS2_I2C_IBCR_MSS                 *((volatile unsigned int*)(0x4270403CUL))\r
+#define bFM3_MFS2_I2C_IBSR_BB                  *((volatile unsigned int*)(0x42704080UL))\r
+#define bFM3_MFS2_I2C_IBSR_SPC                 *((volatile unsigned int*)(0x42704084UL))\r
+#define bFM3_MFS2_I2C_IBSR_RSC                 *((volatile unsigned int*)(0x42704088UL))\r
+#define bFM3_MFS2_I2C_IBSR_AL                  *((volatile unsigned int*)(0x4270408CUL))\r
+#define bFM3_MFS2_I2C_IBSR_TRX                 *((volatile unsigned int*)(0x42704090UL))\r
+#define bFM3_MFS2_I2C_IBSR_RSA                 *((volatile unsigned int*)(0x42704094UL))\r
+#define bFM3_MFS2_I2C_IBSR_RACK                *((volatile unsigned int*)(0x42704098UL))\r
+#define bFM3_MFS2_I2C_IBSR_FBT                 *((volatile unsigned int*)(0x4270409CUL))\r
+#define bFM3_MFS2_I2C_SSR_TBI                  *((volatile unsigned int*)(0x427040A0UL))\r
+#define bFM3_MFS2_I2C_SSR_TDRE                 *((volatile unsigned int*)(0x427040A4UL))\r
+#define bFM3_MFS2_I2C_SSR_RDRF                 *((volatile unsigned int*)(0x427040A8UL))\r
+#define bFM3_MFS2_I2C_SSR_ORE                  *((volatile unsigned int*)(0x427040ACUL))\r
+#define bFM3_MFS2_I2C_SSR_TBIE                 *((volatile unsigned int*)(0x427040B0UL))\r
+#define bFM3_MFS2_I2C_SSR_DMA                  *((volatile unsigned int*)(0x427040B4UL))\r
+#define bFM3_MFS2_I2C_SSR_TSET                 *((volatile unsigned int*)(0x427040B8UL))\r
+#define bFM3_MFS2_I2C_SSR_REC                  *((volatile unsigned int*)(0x427040BCUL))\r
+#define bFM3_MFS2_I2C_ISBA_SA0                 *((volatile unsigned int*)(0x42704200UL))\r
+#define bFM3_MFS2_I2C_ISBA_SA1                 *((volatile unsigned int*)(0x42704204UL))\r
+#define bFM3_MFS2_I2C_ISBA_SA2                 *((volatile unsigned int*)(0x42704208UL))\r
+#define bFM3_MFS2_I2C_ISBA_SA3                 *((volatile unsigned int*)(0x4270420CUL))\r
+#define bFM3_MFS2_I2C_ISBA_SA4                 *((volatile unsigned int*)(0x42704210UL))\r
+#define bFM3_MFS2_I2C_ISBA_SA5                 *((volatile unsigned int*)(0x42704214UL))\r
+#define bFM3_MFS2_I2C_ISBA_SA6                 *((volatile unsigned int*)(0x42704218UL))\r
+#define bFM3_MFS2_I2C_ISBA_SAEN                *((volatile unsigned int*)(0x4270421CUL))\r
+#define bFM3_MFS2_I2C_ISMK_SM0                 *((volatile unsigned int*)(0x42704220UL))\r
+#define bFM3_MFS2_I2C_ISMK_SM1                 *((volatile unsigned int*)(0x42704224UL))\r
+#define bFM3_MFS2_I2C_ISMK_SM2                 *((volatile unsigned int*)(0x42704228UL))\r
+#define bFM3_MFS2_I2C_ISMK_SM3                 *((volatile unsigned int*)(0x4270422CUL))\r
+#define bFM3_MFS2_I2C_ISMK_SM4                 *((volatile unsigned int*)(0x42704230UL))\r
+#define bFM3_MFS2_I2C_ISMK_SM5                 *((volatile unsigned int*)(0x42704234UL))\r
+#define bFM3_MFS2_I2C_ISMK_SM6                 *((volatile unsigned int*)(0x42704238UL))\r
+#define bFM3_MFS2_I2C_ISMK_EN                  *((volatile unsigned int*)(0x4270423CUL))\r
+\r
+/* UART asynchronous channel 3 registers */\r
+#define bFM3_MFS3_UART_SMR_SOE                 *((volatile unsigned int*)(0x42706000UL))\r
+#define bFM3_MFS3_UART_SMR_BDS                 *((volatile unsigned int*)(0x42706008UL))\r
+#define bFM3_MFS3_UART_SMR_SBL                 *((volatile unsigned int*)(0x4270600CUL))\r
+#define bFM3_MFS3_UART_SMR_WUCR                *((volatile unsigned int*)(0x42706010UL))\r
+#define bFM3_MFS3_UART_SMR_MD0                 *((volatile unsigned int*)(0x42706014UL))\r
+#define bFM3_MFS3_UART_SMR_MD1                 *((volatile unsigned int*)(0x42706018UL))\r
+#define bFM3_MFS3_UART_SMR_MD2                 *((volatile unsigned int*)(0x4270601CUL))\r
+#define bFM3_MFS3_UART_SCR_TXE                 *((volatile unsigned int*)(0x42706020UL))\r
+#define bFM3_MFS3_UART_SCR_RXE                 *((volatile unsigned int*)(0x42706024UL))\r
+#define bFM3_MFS3_UART_SCR_TBIE                *((volatile unsigned int*)(0x42706028UL))\r
+#define bFM3_MFS3_UART_SCR_TIE                 *((volatile unsigned int*)(0x4270602CUL))\r
+#define bFM3_MFS3_UART_SCR_RIE                 *((volatile unsigned int*)(0x42706030UL))\r
+#define bFM3_MFS3_UART_SCR_UPCL                *((volatile unsigned int*)(0x4270603CUL))\r
+#define bFM3_MFS3_UART_ESCR_L0                 *((volatile unsigned int*)(0x42706080UL))\r
+#define bFM3_MFS3_UART_ESCR_L1                 *((volatile unsigned int*)(0x42706084UL))\r
+#define bFM3_MFS3_UART_ESCR_L2                 *((volatile unsigned int*)(0x42706088UL))\r
+#define bFM3_MFS3_UART_ESCR_P                  *((volatile unsigned int*)(0x4270608CUL))\r
+#define bFM3_MFS3_UART_ESCR_PEN                *((volatile unsigned int*)(0x42706090UL))\r
+#define bFM3_MFS3_UART_ESCR_INV                *((volatile unsigned int*)(0x42706094UL))\r
+#define bFM3_MFS3_UART_ESCR_ESBL               *((volatile unsigned int*)(0x42706098UL))\r
+#define bFM3_MFS3_UART_ESCR_FLWEN              *((volatile unsigned int*)(0x4270609CUL))\r
+#define bFM3_MFS3_UART_SSR_TBI                 *((volatile unsigned int*)(0x427060A0UL))\r
+#define bFM3_MFS3_UART_SSR_TDRE                *((volatile unsigned int*)(0x427060A4UL))\r
+#define bFM3_MFS3_UART_SSR_RDRF                *((volatile unsigned int*)(0x427060A8UL))\r
+#define bFM3_MFS3_UART_SSR_ORE                 *((volatile unsigned int*)(0x427060ACUL))\r
+#define bFM3_MFS3_UART_SSR_FRE                 *((volatile unsigned int*)(0x427060B0UL))\r
+#define bFM3_MFS3_UART_SSR_PE                  *((volatile unsigned int*)(0x427060B4UL))\r
+#define bFM3_MFS3_UART_SSR_REC                 *((volatile unsigned int*)(0x427060BCUL))\r
+#define bFM3_MFS3_UART_RDR_AD                  *((volatile unsigned int*)(0x42706120UL))\r
+#define bFM3_MFS3_UART_TDR_AD                  *((volatile unsigned int*)(0x42706120UL))\r
+#define bFM3_MFS3_UART_BGR_EXT                 *((volatile unsigned int*)(0x427061BCUL))\r
+#define bFM3_MFS3_UART_BGR1_EXT                *((volatile unsigned int*)(0x427061BCUL))\r
+\r
+/* UART synchronous channel 3 registers */\r
+#define bFM3_MFS3_CSIO_SMR_SOE                 *((volatile unsigned int*)(0x42706000UL))\r
+#define bFM3_MFS3_CSIO_SMR_SCKE                *((volatile unsigned int*)(0x42706004UL))\r
+#define bFM3_MFS3_CSIO_SMR_BDS                 *((volatile unsigned int*)(0x42706008UL))\r
+#define bFM3_MFS3_CSIO_SMR_SCINV               *((volatile unsigned int*)(0x4270600CUL))\r
+#define bFM3_MFS3_CSIO_SMR_WUCR                *((volatile unsigned int*)(0x42706010UL))\r
+#define bFM3_MFS3_CSIO_SMR_MD0                 *((volatile unsigned int*)(0x42706014UL))\r
+#define bFM3_MFS3_CSIO_SMR_MD1                 *((volatile unsigned int*)(0x42706018UL))\r
+#define bFM3_MFS3_CSIO_SMR_MD2                 *((volatile unsigned int*)(0x4270601CUL))\r
+#define bFM3_MFS3_CSIO_SCR_TXE                 *((volatile unsigned int*)(0x42706020UL))\r
+#define bFM3_MFS3_CSIO_SCR_RXE                 *((volatile unsigned int*)(0x42706024UL))\r
+#define bFM3_MFS3_CSIO_SCR_TBIE                *((volatile unsigned int*)(0x42706028UL))\r
+#define bFM3_MFS3_CSIO_SCR_TIE                 *((volatile unsigned int*)(0x4270602CUL))\r
+#define bFM3_MFS3_CSIO_SCR_RIE                 *((volatile unsigned int*)(0x42706030UL))\r
+#define bFM3_MFS3_CSIO_SCR_SPI                 *((volatile unsigned int*)(0x42706034UL))\r
+#define bFM3_MFS3_CSIO_SCR_MS                  *((volatile unsigned int*)(0x42706038UL))\r
+#define bFM3_MFS3_CSIO_SCR_UPCL                *((volatile unsigned int*)(0x4270603CUL))\r
+#define bFM3_MFS3_CSIO_ESCR_L0                 *((volatile unsigned int*)(0x42706080UL))\r
+#define bFM3_MFS3_CSIO_ESCR_L1                 *((volatile unsigned int*)(0x42706084UL))\r
+#define bFM3_MFS3_CSIO_ESCR_L2                 *((volatile unsigned int*)(0x42706088UL))\r
+#define bFM3_MFS3_CSIO_ESCR_WT0                *((volatile unsigned int*)(0x4270608CUL))\r
+#define bFM3_MFS3_CSIO_ESCR_WT1                *((volatile unsigned int*)(0x42706090UL))\r
+#define bFM3_MFS3_CSIO_ESCR_SOP                *((volatile unsigned int*)(0x4270609CUL))\r
+#define bFM3_MFS3_CSIO_SSR_TBI                 *((volatile unsigned int*)(0x427060A0UL))\r
+#define bFM3_MFS3_CSIO_SSR_TDRE                *((volatile unsigned int*)(0x427060A4UL))\r
+#define bFM3_MFS3_CSIO_SSR_RDRF                *((volatile unsigned int*)(0x427060A8UL))\r
+#define bFM3_MFS3_CSIO_SSR_ORE                 *((volatile unsigned int*)(0x427060ACUL))\r
+#define bFM3_MFS3_CSIO_SSR_REC                 *((volatile unsigned int*)(0x427060BCUL))\r
+\r
+/* UART LIN channel 3 registers */\r
+#define bFM3_MFS3_LIN_SMR_SOE                  *((volatile unsigned int*)(0x42706000UL))\r
+#define bFM3_MFS3_LIN_SMR_SBL                  *((volatile unsigned int*)(0x4270600CUL))\r
+#define bFM3_MFS3_LIN_SMR_WUCR                 *((volatile unsigned int*)(0x42706010UL))\r
+#define bFM3_MFS3_LIN_SMR_MD0                  *((volatile unsigned int*)(0x42706014UL))\r
+#define bFM3_MFS3_LIN_SMR_MD1                  *((volatile unsigned int*)(0x42706018UL))\r
+#define bFM3_MFS3_LIN_SMR_MD2                  *((volatile unsigned int*)(0x4270601CUL))\r
+#define bFM3_MFS3_LIN_SCR_TXE                  *((volatile unsigned int*)(0x42706020UL))\r
+#define bFM3_MFS3_LIN_SCR_RXE                  *((volatile unsigned int*)(0x42706024UL))\r
+#define bFM3_MFS3_LIN_SCR_TBIE                 *((volatile unsigned int*)(0x42706028UL))\r
+#define bFM3_MFS3_LIN_SCR_TIE                  *((volatile unsigned int*)(0x4270602CUL))\r
+#define bFM3_MFS3_LIN_SCR_RIE                  *((volatile unsigned int*)(0x42706030UL))\r
+#define bFM3_MFS3_LIN_SCR_LBR                  *((volatile unsigned int*)(0x42706034UL))\r
+#define bFM3_MFS3_LIN_SCR_MS                   *((volatile unsigned int*)(0x42706038UL))\r
+#define bFM3_MFS3_LIN_SCR_UPCL                 *((volatile unsigned int*)(0x4270603CUL))\r
+#define bFM3_MFS3_LIN_ESCR_DEL0                *((volatile unsigned int*)(0x42706080UL))\r
+#define bFM3_MFS3_LIN_ESCR_DEL1                *((volatile unsigned int*)(0x42706084UL))\r
+#define bFM3_MFS3_LIN_ESCR_LBL0                *((volatile unsigned int*)(0x42706088UL))\r
+#define bFM3_MFS3_LIN_ESCR_LBL1                *((volatile unsigned int*)(0x4270608CUL))\r
+#define bFM3_MFS3_LIN_ESCR_LBIE                *((volatile unsigned int*)(0x42706090UL))\r
+#define bFM3_MFS3_LIN_ESCR_ESBL                *((volatile unsigned int*)(0x42706098UL))\r
+#define bFM3_MFS3_LIN_SSR_TBI                  *((volatile unsigned int*)(0x427060A0UL))\r
+#define bFM3_MFS3_LIN_SSR_TDRE                 *((volatile unsigned int*)(0x427060A4UL))\r
+#define bFM3_MFS3_LIN_SSR_RDRF                 *((volatile unsigned int*)(0x427060A8UL))\r
+#define bFM3_MFS3_LIN_SSR_ORE                  *((volatile unsigned int*)(0x427060ACUL))\r
+#define bFM3_MFS3_LIN_SSR_FRE                  *((volatile unsigned int*)(0x427060B0UL))\r
+#define bFM3_MFS3_LIN_SSR_LBD                  *((volatile unsigned int*)(0x427060B4UL))\r
+#define bFM3_MFS3_LIN_SSR_REC                  *((volatile unsigned int*)(0x427060BCUL))\r
+#define bFM3_MFS3_LIN_BGR_EXT                  *((volatile unsigned int*)(0x427061BCUL))\r
+#define bFM3_MFS3_LIN_BGR1_EXT                 *((volatile unsigned int*)(0x427061BCUL))\r
+\r
+/* I2C channel 3 registers */\r
+#define bFM3_MFS3_I2C_SMR_ITST0                *((volatile unsigned int*)(0x42706000UL))\r
+#define bFM3_MFS3_I2C_SMR_ITST1                *((volatile unsigned int*)(0x42706004UL))\r
+#define bFM3_MFS3_I2C_SMR_TIE                  *((volatile unsigned int*)(0x42706008UL))\r
+#define bFM3_MFS3_I2C_SMR_RIE                  *((volatile unsigned int*)(0x4270600CUL))\r
+#define bFM3_MFS3_I2C_SMR_WUCR                 *((volatile unsigned int*)(0x42706010UL))\r
+#define bFM3_MFS3_I2C_SMR_MD0                  *((volatile unsigned int*)(0x42706014UL))\r
+#define bFM3_MFS3_I2C_SMR_MD1                  *((volatile unsigned int*)(0x42706018UL))\r
+#define bFM3_MFS3_I2C_SMR_MD2                  *((volatile unsigned int*)(0x4270601CUL))\r
+#define bFM3_MFS3_I2C_IBCR_INT                 *((volatile unsigned int*)(0x42706020UL))\r
+#define bFM3_MFS3_I2C_IBCR_BER                 *((volatile unsigned int*)(0x42706024UL))\r
+#define bFM3_MFS3_I2C_IBCR_INTE                *((volatile unsigned int*)(0x42706028UL))\r
+#define bFM3_MFS3_I2C_IBCR_CNDE                *((volatile unsigned int*)(0x4270602CUL))\r
+#define bFM3_MFS3_I2C_IBCR_WSEL                *((volatile unsigned int*)(0x42706030UL))\r
+#define bFM3_MFS3_I2C_IBCR_ACKE                *((volatile unsigned int*)(0x42706034UL))\r
+#define bFM3_MFS3_I2C_IBCR_ACT                 *((volatile unsigned int*)(0x42706038UL))\r
+#define bFM3_MFS3_I2C_IBCR_SCC                 *((volatile unsigned int*)(0x42706038UL))\r
+#define bFM3_MFS3_I2C_IBCR_MSS                 *((volatile unsigned int*)(0x4270603CUL))\r
+#define bFM3_MFS3_I2C_IBSR_BB                  *((volatile unsigned int*)(0x42706080UL))\r
+#define bFM3_MFS3_I2C_IBSR_SPC                 *((volatile unsigned int*)(0x42706084UL))\r
+#define bFM3_MFS3_I2C_IBSR_RSC                 *((volatile unsigned int*)(0x42706088UL))\r
+#define bFM3_MFS3_I2C_IBSR_AL                  *((volatile unsigned int*)(0x4270608CUL))\r
+#define bFM3_MFS3_I2C_IBSR_TRX                 *((volatile unsigned int*)(0x42706090UL))\r
+#define bFM3_MFS3_I2C_IBSR_RSA                 *((volatile unsigned int*)(0x42706094UL))\r
+#define bFM3_MFS3_I2C_IBSR_RACK                *((volatile unsigned int*)(0x42706098UL))\r
+#define bFM3_MFS3_I2C_IBSR_FBT                 *((volatile unsigned int*)(0x4270609CUL))\r
+#define bFM3_MFS3_I2C_SSR_TBI                  *((volatile unsigned int*)(0x427060A0UL))\r
+#define bFM3_MFS3_I2C_SSR_TDRE                 *((volatile unsigned int*)(0x427060A4UL))\r
+#define bFM3_MFS3_I2C_SSR_RDRF                 *((volatile unsigned int*)(0x427060A8UL))\r
+#define bFM3_MFS3_I2C_SSR_ORE                  *((volatile unsigned int*)(0x427060ACUL))\r
+#define bFM3_MFS3_I2C_SSR_TBIE                 *((volatile unsigned int*)(0x427060B0UL))\r
+#define bFM3_MFS3_I2C_SSR_DMA                  *((volatile unsigned int*)(0x427060B4UL))\r
+#define bFM3_MFS3_I2C_SSR_TSET                 *((volatile unsigned int*)(0x427060B8UL))\r
+#define bFM3_MFS3_I2C_SSR_REC                  *((volatile unsigned int*)(0x427060BCUL))\r
+#define bFM3_MFS3_I2C_ISBA_SA0                 *((volatile unsigned int*)(0x42706200UL))\r
+#define bFM3_MFS3_I2C_ISBA_SA1                 *((volatile unsigned int*)(0x42706204UL))\r
+#define bFM3_MFS3_I2C_ISBA_SA2                 *((volatile unsigned int*)(0x42706208UL))\r
+#define bFM3_MFS3_I2C_ISBA_SA3                 *((volatile unsigned int*)(0x4270620CUL))\r
+#define bFM3_MFS3_I2C_ISBA_SA4                 *((volatile unsigned int*)(0x42706210UL))\r
+#define bFM3_MFS3_I2C_ISBA_SA5                 *((volatile unsigned int*)(0x42706214UL))\r
+#define bFM3_MFS3_I2C_ISBA_SA6                 *((volatile unsigned int*)(0x42706218UL))\r
+#define bFM3_MFS3_I2C_ISBA_SAEN                *((volatile unsigned int*)(0x4270621CUL))\r
+#define bFM3_MFS3_I2C_ISMK_SM0                 *((volatile unsigned int*)(0x42706220UL))\r
+#define bFM3_MFS3_I2C_ISMK_SM1                 *((volatile unsigned int*)(0x42706224UL))\r
+#define bFM3_MFS3_I2C_ISMK_SM2                 *((volatile unsigned int*)(0x42706228UL))\r
+#define bFM3_MFS3_I2C_ISMK_SM3                 *((volatile unsigned int*)(0x4270622CUL))\r
+#define bFM3_MFS3_I2C_ISMK_SM4                 *((volatile unsigned int*)(0x42706230UL))\r
+#define bFM3_MFS3_I2C_ISMK_SM5                 *((volatile unsigned int*)(0x42706234UL))\r
+#define bFM3_MFS3_I2C_ISMK_SM6                 *((volatile unsigned int*)(0x42706238UL))\r
+#define bFM3_MFS3_I2C_ISMK_EN                  *((volatile unsigned int*)(0x4270623CUL))\r
+\r
+/* UART asynchronous channel 4 registers */\r
+#define bFM3_MFS4_UART_SMR_SOE                 *((volatile unsigned int*)(0x42708000UL))\r
+#define bFM3_MFS4_UART_SMR_BDS                 *((volatile unsigned int*)(0x42708008UL))\r
+#define bFM3_MFS4_UART_SMR_SBL                 *((volatile unsigned int*)(0x4270800CUL))\r
+#define bFM3_MFS4_UART_SMR_WUCR                *((volatile unsigned int*)(0x42708010UL))\r
+#define bFM3_MFS4_UART_SMR_MD0                 *((volatile unsigned int*)(0x42708014UL))\r
+#define bFM3_MFS4_UART_SMR_MD1                 *((volatile unsigned int*)(0x42708018UL))\r
+#define bFM3_MFS4_UART_SMR_MD2                 *((volatile unsigned int*)(0x4270801CUL))\r
+#define bFM3_MFS4_UART_SCR_TXE                 *((volatile unsigned int*)(0x42708020UL))\r
+#define bFM3_MFS4_UART_SCR_RXE                 *((volatile unsigned int*)(0x42708024UL))\r
+#define bFM3_MFS4_UART_SCR_TBIE                *((volatile unsigned int*)(0x42708028UL))\r
+#define bFM3_MFS4_UART_SCR_TIE                 *((volatile unsigned int*)(0x4270802CUL))\r
+#define bFM3_MFS4_UART_SCR_RIE                 *((volatile unsigned int*)(0x42708030UL))\r
+#define bFM3_MFS4_UART_SCR_UPCL                *((volatile unsigned int*)(0x4270803CUL))\r
+#define bFM3_MFS4_UART_ESCR_L0                 *((volatile unsigned int*)(0x42708080UL))\r
+#define bFM3_MFS4_UART_ESCR_L1                 *((volatile unsigned int*)(0x42708084UL))\r
+#define bFM3_MFS4_UART_ESCR_L2                 *((volatile unsigned int*)(0x42708088UL))\r
+#define bFM3_MFS4_UART_ESCR_P                  *((volatile unsigned int*)(0x4270808CUL))\r
+#define bFM3_MFS4_UART_ESCR_PEN                *((volatile unsigned int*)(0x42708090UL))\r
+#define bFM3_MFS4_UART_ESCR_INV                *((volatile unsigned int*)(0x42708094UL))\r
+#define bFM3_MFS4_UART_ESCR_ESBL               *((volatile unsigned int*)(0x42708098UL))\r
+#define bFM3_MFS4_UART_ESCR_FLWEN              *((volatile unsigned int*)(0x4270809CUL))\r
+#define bFM3_MFS4_UART_SSR_TBI                 *((volatile unsigned int*)(0x427080A0UL))\r
+#define bFM3_MFS4_UART_SSR_TDRE                *((volatile unsigned int*)(0x427080A4UL))\r
+#define bFM3_MFS4_UART_SSR_RDRF                *((volatile unsigned int*)(0x427080A8UL))\r
+#define bFM3_MFS4_UART_SSR_ORE                 *((volatile unsigned int*)(0x427080ACUL))\r
+#define bFM3_MFS4_UART_SSR_FRE                 *((volatile unsigned int*)(0x427080B0UL))\r
+#define bFM3_MFS4_UART_SSR_PE                  *((volatile unsigned int*)(0x427080B4UL))\r
+#define bFM3_MFS4_UART_SSR_REC                 *((volatile unsigned int*)(0x427080BCUL))\r
+#define bFM3_MFS4_UART_RDR_AD                  *((volatile unsigned int*)(0x42708120UL))\r
+#define bFM3_MFS4_UART_TDR_AD                  *((volatile unsigned int*)(0x42708120UL))\r
+#define bFM3_MFS4_UART_BGR_EXT                 *((volatile unsigned int*)(0x427081BCUL))\r
+#define bFM3_MFS4_UART_BGR1_EXT                *((volatile unsigned int*)(0x427081BCUL))\r
+#define bFM3_MFS4_UART_FCR_FE1                 *((volatile unsigned int*)(0x42708280UL))\r
+#define bFM3_MFS4_UART_FCR_FE2                 *((volatile unsigned int*)(0x42708284UL))\r
+#define bFM3_MFS4_UART_FCR_FCL1                *((volatile unsigned int*)(0x42708288UL))\r
+#define bFM3_MFS4_UART_FCR_FCL2                *((volatile unsigned int*)(0x4270828CUL))\r
+#define bFM3_MFS4_UART_FCR_FSET                *((volatile unsigned int*)(0x42708290UL))\r
+#define bFM3_MFS4_UART_FCR_FLD                 *((volatile unsigned int*)(0x42708294UL))\r
+#define bFM3_MFS4_UART_FCR_FLST                *((volatile unsigned int*)(0x42708298UL))\r
+#define bFM3_MFS4_UART_FCR_FSEL                *((volatile unsigned int*)(0x427082A0UL))\r
+#define bFM3_MFS4_UART_FCR_FTIE                *((volatile unsigned int*)(0x427082A4UL))\r
+#define bFM3_MFS4_UART_FCR_FDRQ                *((volatile unsigned int*)(0x427082A8UL))\r
+#define bFM3_MFS4_UART_FCR_FRIE                *((volatile unsigned int*)(0x427082ACUL))\r
+#define bFM3_MFS4_UART_FCR_FLSTE               *((volatile unsigned int*)(0x427082B0UL))\r
+#define bFM3_MFS4_UART_FCR_FTST0               *((volatile unsigned int*)(0x427082B8UL))\r
+#define bFM3_MFS4_UART_FCR_FTST1               *((volatile unsigned int*)(0x427082BCUL))\r
+#define bFM3_MFS4_UART_FCR0_FE1                *((volatile unsigned int*)(0x42708280UL))\r
+#define bFM3_MFS4_UART_FCR0_FE2                *((volatile unsigned int*)(0x42708284UL))\r
+#define bFM3_MFS4_UART_FCR0_FCL1               *((volatile unsigned int*)(0x42708288UL))\r
+#define bFM3_MFS4_UART_FCR0_FCL2               *((volatile unsigned int*)(0x4270828CUL))\r
+#define bFM3_MFS4_UART_FCR0_FSET               *((volatile unsigned int*)(0x42708290UL))\r
+#define bFM3_MFS4_UART_FCR0_FLD                *((volatile unsigned int*)(0x42708294UL))\r
+#define bFM3_MFS4_UART_FCR0_FLST               *((volatile unsigned int*)(0x42708298UL))\r
+#define bFM3_MFS4_UART_FCR1_FSEL               *((volatile unsigned int*)(0x427082A0UL))\r
+#define bFM3_MFS4_UART_FCR1_FTIE               *((volatile unsigned int*)(0x427082A4UL))\r
+#define bFM3_MFS4_UART_FCR1_FDRQ               *((volatile unsigned int*)(0x427082A8UL))\r
+#define bFM3_MFS4_UART_FCR1_FRIE               *((volatile unsigned int*)(0x427082ACUL))\r
+#define bFM3_MFS4_UART_FCR1_FLSTE              *((volatile unsigned int*)(0x427082B0UL))\r
+#define bFM3_MFS4_UART_FCR1_FTST0              *((volatile unsigned int*)(0x427082B8UL))\r
+#define bFM3_MFS4_UART_FCR1_FTST1              *((volatile unsigned int*)(0x427082BCUL))\r
+#define bFM3_MFS4_UART_FBYTE_FD0               *((volatile unsigned int*)(0x42708300UL))\r
+#define bFM3_MFS4_UART_FBYTE_FD1               *((volatile unsigned int*)(0x42708304UL))\r
+#define bFM3_MFS4_UART_FBYTE_FD2               *((volatile unsigned int*)(0x42708308UL))\r
+#define bFM3_MFS4_UART_FBYTE_FD3               *((volatile unsigned int*)(0x4270830CUL))\r
+#define bFM3_MFS4_UART_FBYTE_FD4               *((volatile unsigned int*)(0x42708310UL))\r
+#define bFM3_MFS4_UART_FBYTE_FD5               *((volatile unsigned int*)(0x42708314UL))\r
+#define bFM3_MFS4_UART_FBYTE_FD6               *((volatile unsigned int*)(0x42708318UL))\r
+#define bFM3_MFS4_UART_FBYTE_FD7               *((volatile unsigned int*)(0x4270831CUL))\r
+#define bFM3_MFS4_UART_FBYTE_FD8               *((volatile unsigned int*)(0x42708320UL))\r
+#define bFM3_MFS4_UART_FBYTE_FD9               *((volatile unsigned int*)(0x42708324UL))\r
+#define bFM3_MFS4_UART_FBYTE_FD10              *((volatile unsigned int*)(0x42708328UL))\r
+#define bFM3_MFS4_UART_FBYTE_FD11              *((volatile unsigned int*)(0x4270832CUL))\r
+#define bFM3_MFS4_UART_FBYTE_FD12              *((volatile unsigned int*)(0x42708330UL))\r
+#define bFM3_MFS4_UART_FBYTE_FD13              *((volatile unsigned int*)(0x42708334UL))\r
+#define bFM3_MFS4_UART_FBYTE_FD14              *((volatile unsigned int*)(0x42708338UL))\r
+#define bFM3_MFS4_UART_FBYTE_FD15              *((volatile unsigned int*)(0x4270833CUL))\r
+#define bFM3_MFS4_UART_FBYTE1_FD0              *((volatile unsigned int*)(0x42708300UL))\r
+#define bFM3_MFS4_UART_FBYTE1_FD1              *((volatile unsigned int*)(0x42708304UL))\r
+#define bFM3_MFS4_UART_FBYTE1_FD2              *((volatile unsigned int*)(0x42708308UL))\r
+#define bFM3_MFS4_UART_FBYTE1_FD3              *((volatile unsigned int*)(0x4270830CUL))\r
+#define bFM3_MFS4_UART_FBYTE1_FD4              *((volatile unsigned int*)(0x42708310UL))\r
+#define bFM3_MFS4_UART_FBYTE1_FD5              *((volatile unsigned int*)(0x42708314UL))\r
+#define bFM3_MFS4_UART_FBYTE1_FD6              *((volatile unsigned int*)(0x42708318UL))\r
+#define bFM3_MFS4_UART_FBYTE1_FD7              *((volatile unsigned int*)(0x4270831CUL))\r
+#define bFM3_MFS4_UART_FBYTE2_FD8              *((volatile unsigned int*)(0x42708320UL))\r
+#define bFM3_MFS4_UART_FBYTE2_FD9              *((volatile unsigned int*)(0x42708324UL))\r
+#define bFM3_MFS4_UART_FBYTE2_FD10             *((volatile unsigned int*)(0x42708328UL))\r
+#define bFM3_MFS4_UART_FBYTE2_FD11             *((volatile unsigned int*)(0x4270832CUL))\r
+#define bFM3_MFS4_UART_FBYTE2_FD12             *((volatile unsigned int*)(0x42708330UL))\r
+#define bFM3_MFS4_UART_FBYTE2_FD13             *((volatile unsigned int*)(0x42708334UL))\r
+#define bFM3_MFS4_UART_FBYTE2_FD14             *((volatile unsigned int*)(0x42708338UL))\r
+#define bFM3_MFS4_UART_FBYTE2_FD15             *((volatile unsigned int*)(0x4270833CUL))\r
+\r
+/* UART synchronous channel 4 registers */\r
+#define bFM3_MFS4_CSIO_SMR_SOE                 *((volatile unsigned int*)(0x42708000UL))\r
+#define bFM3_MFS4_CSIO_SMR_SCKE                *((volatile unsigned int*)(0x42708004UL))\r
+#define bFM3_MFS4_CSIO_SMR_BDS                 *((volatile unsigned int*)(0x42708008UL))\r
+#define bFM3_MFS4_CSIO_SMR_SCINV               *((volatile unsigned int*)(0x4270800CUL))\r
+#define bFM3_MFS4_CSIO_SMR_WUCR                *((volatile unsigned int*)(0x42708010UL))\r
+#define bFM3_MFS4_CSIO_SMR_MD0                 *((volatile unsigned int*)(0x42708014UL))\r
+#define bFM3_MFS4_CSIO_SMR_MD1                 *((volatile unsigned int*)(0x42708018UL))\r
+#define bFM3_MFS4_CSIO_SMR_MD2                 *((volatile unsigned int*)(0x4270801CUL))\r
+#define bFM3_MFS4_CSIO_SCR_TXE                 *((volatile unsigned int*)(0x42708020UL))\r
+#define bFM3_MFS4_CSIO_SCR_RXE                 *((volatile unsigned int*)(0x42708024UL))\r
+#define bFM3_MFS4_CSIO_SCR_TBIE                *((volatile unsigned int*)(0x42708028UL))\r
+#define bFM3_MFS4_CSIO_SCR_TIE                 *((volatile unsigned int*)(0x4270802CUL))\r
+#define bFM3_MFS4_CSIO_SCR_RIE                 *((volatile unsigned int*)(0x42708030UL))\r
+#define bFM3_MFS4_CSIO_SCR_SPI                 *((volatile unsigned int*)(0x42708034UL))\r
+#define bFM3_MFS4_CSIO_SCR_MS                  *((volatile unsigned int*)(0x42708038UL))\r
+#define bFM3_MFS4_CSIO_SCR_UPCL                *((volatile unsigned int*)(0x4270803CUL))\r
+#define bFM3_MFS4_CSIO_ESCR_L0                 *((volatile unsigned int*)(0x42708080UL))\r
+#define bFM3_MFS4_CSIO_ESCR_L1                 *((volatile unsigned int*)(0x42708084UL))\r
+#define bFM3_MFS4_CSIO_ESCR_L2                 *((volatile unsigned int*)(0x42708088UL))\r
+#define bFM3_MFS4_CSIO_ESCR_WT0                *((volatile unsigned int*)(0x4270808CUL))\r
+#define bFM3_MFS4_CSIO_ESCR_WT1                *((volatile unsigned int*)(0x42708090UL))\r
+#define bFM3_MFS4_CSIO_ESCR_SOP                *((volatile unsigned int*)(0x4270809CUL))\r
+#define bFM3_MFS4_CSIO_SSR_TBI                 *((volatile unsigned int*)(0x427080A0UL))\r
+#define bFM3_MFS4_CSIO_SSR_TDRE                *((volatile unsigned int*)(0x427080A4UL))\r
+#define bFM3_MFS4_CSIO_SSR_RDRF                *((volatile unsigned int*)(0x427080A8UL))\r
+#define bFM3_MFS4_CSIO_SSR_ORE                 *((volatile unsigned int*)(0x427080ACUL))\r
+#define bFM3_MFS4_CSIO_SSR_REC                 *((volatile unsigned int*)(0x427080BCUL))\r
+#define bFM3_MFS4_CSIO_FCR_FE1                 *((volatile unsigned int*)(0x42708280UL))\r
+#define bFM3_MFS4_CSIO_FCR_FE2                 *((volatile unsigned int*)(0x42708284UL))\r
+#define bFM3_MFS4_CSIO_FCR_FCL1                *((volatile unsigned int*)(0x42708288UL))\r
+#define bFM3_MFS4_CSIO_FCR_FCL2                *((volatile unsigned int*)(0x4270828CUL))\r
+#define bFM3_MFS4_CSIO_FCR_FSET                *((volatile unsigned int*)(0x42708290UL))\r
+#define bFM3_MFS4_CSIO_FCR_FLD                 *((volatile unsigned int*)(0x42708294UL))\r
+#define bFM3_MFS4_CSIO_FCR_FLST                *((volatile unsigned int*)(0x42708298UL))\r
+#define bFM3_MFS4_CSIO_FCR_FSEL                *((volatile unsigned int*)(0x427082A0UL))\r
+#define bFM3_MFS4_CSIO_FCR_FTIE                *((volatile unsigned int*)(0x427082A4UL))\r
+#define bFM3_MFS4_CSIO_FCR_FDRQ                *((volatile unsigned int*)(0x427082A8UL))\r
+#define bFM3_MFS4_CSIO_FCR_FRIE                *((volatile unsigned int*)(0x427082ACUL))\r
+#define bFM3_MFS4_CSIO_FCR_FLSTE               *((volatile unsigned int*)(0x427082B0UL))\r
+#define bFM3_MFS4_CSIO_FCR_FTST0               *((volatile unsigned int*)(0x427082B8UL))\r
+#define bFM3_MFS4_CSIO_FCR_FTST1               *((volatile unsigned int*)(0x427082BCUL))\r
+#define bFM3_MFS4_CSIO_FCR0_FE1                *((volatile unsigned int*)(0x42708280UL))\r
+#define bFM3_MFS4_CSIO_FCR0_FE2                *((volatile unsigned int*)(0x42708284UL))\r
+#define bFM3_MFS4_CSIO_FCR0_FCL1               *((volatile unsigned int*)(0x42708288UL))\r
+#define bFM3_MFS4_CSIO_FCR0_FCL2               *((volatile unsigned int*)(0x4270828CUL))\r
+#define bFM3_MFS4_CSIO_FCR0_FSET               *((volatile unsigned int*)(0x42708290UL))\r
+#define bFM3_MFS4_CSIO_FCR0_FLD                *((volatile unsigned int*)(0x42708294UL))\r
+#define bFM3_MFS4_CSIO_FCR0_FLST               *((volatile unsigned int*)(0x42708298UL))\r
+#define bFM3_MFS4_CSIO_FCR1_FSEL               *((volatile unsigned int*)(0x427082A0UL))\r
+#define bFM3_MFS4_CSIO_FCR1_FTIE               *((volatile unsigned int*)(0x427082A4UL))\r
+#define bFM3_MFS4_CSIO_FCR1_FDRQ               *((volatile unsigned int*)(0x427082A8UL))\r
+#define bFM3_MFS4_CSIO_FCR1_FRIE               *((volatile unsigned int*)(0x427082ACUL))\r
+#define bFM3_MFS4_CSIO_FCR1_FLSTE              *((volatile unsigned int*)(0x427082B0UL))\r
+#define bFM3_MFS4_CSIO_FCR1_FTST0              *((volatile unsigned int*)(0x427082B8UL))\r
+#define bFM3_MFS4_CSIO_FCR1_FTST1              *((volatile unsigned int*)(0x427082BCUL))\r
+#define bFM3_MFS4_CSIO_FBYTE_FD0               *((volatile unsigned int*)(0x42708300UL))\r
+#define bFM3_MFS4_CSIO_FBYTE_FD1               *((volatile unsigned int*)(0x42708304UL))\r
+#define bFM3_MFS4_CSIO_FBYTE_FD2               *((volatile unsigned int*)(0x42708308UL))\r
+#define bFM3_MFS4_CSIO_FBYTE_FD3               *((volatile unsigned int*)(0x4270830CUL))\r
+#define bFM3_MFS4_CSIO_FBYTE_FD4               *((volatile unsigned int*)(0x42708310UL))\r
+#define bFM3_MFS4_CSIO_FBYTE_FD5               *((volatile unsigned int*)(0x42708314UL))\r
+#define bFM3_MFS4_CSIO_FBYTE_FD6               *((volatile unsigned int*)(0x42708318UL))\r
+#define bFM3_MFS4_CSIO_FBYTE_FD7               *((volatile unsigned int*)(0x4270831CUL))\r
+#define bFM3_MFS4_CSIO_FBYTE_FD8               *((volatile unsigned int*)(0x42708320UL))\r
+#define bFM3_MFS4_CSIO_FBYTE_FD9               *((volatile unsigned int*)(0x42708324UL))\r
+#define bFM3_MFS4_CSIO_FBYTE_FD10              *((volatile unsigned int*)(0x42708328UL))\r
+#define bFM3_MFS4_CSIO_FBYTE_FD11              *((volatile unsigned int*)(0x4270832CUL))\r
+#define bFM3_MFS4_CSIO_FBYTE_FD12              *((volatile unsigned int*)(0x42708330UL))\r
+#define bFM3_MFS4_CSIO_FBYTE_FD13              *((volatile unsigned int*)(0x42708334UL))\r
+#define bFM3_MFS4_CSIO_FBYTE_FD14              *((volatile unsigned int*)(0x42708338UL))\r
+#define bFM3_MFS4_CSIO_FBYTE_FD15              *((volatile unsigned int*)(0x4270833CUL))\r
+#define bFM3_MFS4_CSIO_FBYTE1_FD0              *((volatile unsigned int*)(0x42708300UL))\r
+#define bFM3_MFS4_CSIO_FBYTE1_FD1              *((volatile unsigned int*)(0x42708304UL))\r
+#define bFM3_MFS4_CSIO_FBYTE1_FD2              *((volatile unsigned int*)(0x42708308UL))\r
+#define bFM3_MFS4_CSIO_FBYTE1_FD3              *((volatile unsigned int*)(0x4270830CUL))\r
+#define bFM3_MFS4_CSIO_FBYTE1_FD4              *((volatile unsigned int*)(0x42708310UL))\r
+#define bFM3_MFS4_CSIO_FBYTE1_FD5              *((volatile unsigned int*)(0x42708314UL))\r
+#define bFM3_MFS4_CSIO_FBYTE1_FD6              *((volatile unsigned int*)(0x42708318UL))\r
+#define bFM3_MFS4_CSIO_FBYTE1_FD7              *((volatile unsigned int*)(0x4270831CUL))\r
+#define bFM3_MFS4_CSIO_FBYTE2_FD8              *((volatile unsigned int*)(0x42708320UL))\r
+#define bFM3_MFS4_CSIO_FBYTE2_FD9              *((volatile unsigned int*)(0x42708324UL))\r
+#define bFM3_MFS4_CSIO_FBYTE2_FD10             *((volatile unsigned int*)(0x42708328UL))\r
+#define bFM3_MFS4_CSIO_FBYTE2_FD11             *((volatile unsigned int*)(0x4270832CUL))\r
+#define bFM3_MFS4_CSIO_FBYTE2_FD12             *((volatile unsigned int*)(0x42708330UL))\r
+#define bFM3_MFS4_CSIO_FBYTE2_FD13             *((volatile unsigned int*)(0x42708334UL))\r
+#define bFM3_MFS4_CSIO_FBYTE2_FD14             *((volatile unsigned int*)(0x42708338UL))\r
+#define bFM3_MFS4_CSIO_FBYTE2_FD15             *((volatile unsigned int*)(0x4270833CUL))\r
+\r
+/* UART LIN channel 4 registers */\r
+#define bFM3_MFS4_LIN_SMR_SOE                  *((volatile unsigned int*)(0x42708000UL))\r
+#define bFM3_MFS4_LIN_SMR_SBL                  *((volatile unsigned int*)(0x4270800CUL))\r
+#define bFM3_MFS4_LIN_SMR_WUCR                 *((volatile unsigned int*)(0x42708010UL))\r
+#define bFM3_MFS4_LIN_SMR_MD0                  *((volatile unsigned int*)(0x42708014UL))\r
+#define bFM3_MFS4_LIN_SMR_MD1                  *((volatile unsigned int*)(0x42708018UL))\r
+#define bFM3_MFS4_LIN_SMR_MD2                  *((volatile unsigned int*)(0x4270801CUL))\r
+#define bFM3_MFS4_LIN_SCR_TXE                  *((volatile unsigned int*)(0x42708020UL))\r
+#define bFM3_MFS4_LIN_SCR_RXE                  *((volatile unsigned int*)(0x42708024UL))\r
+#define bFM3_MFS4_LIN_SCR_TBIE                 *((volatile unsigned int*)(0x42708028UL))\r
+#define bFM3_MFS4_LIN_SCR_TIE                  *((volatile unsigned int*)(0x4270802CUL))\r
+#define bFM3_MFS4_LIN_SCR_RIE                  *((volatile unsigned int*)(0x42708030UL))\r
+#define bFM3_MFS4_LIN_SCR_LBR                  *((volatile unsigned int*)(0x42708034UL))\r
+#define bFM3_MFS4_LIN_SCR_MS                   *((volatile unsigned int*)(0x42708038UL))\r
+#define bFM3_MFS4_LIN_SCR_UPCL                 *((volatile unsigned int*)(0x4270803CUL))\r
+#define bFM3_MFS4_LIN_ESCR_DEL0                *((volatile unsigned int*)(0x42708080UL))\r
+#define bFM3_MFS4_LIN_ESCR_DEL1                *((volatile unsigned int*)(0x42708084UL))\r
+#define bFM3_MFS4_LIN_ESCR_LBL0                *((volatile unsigned int*)(0x42708088UL))\r
+#define bFM3_MFS4_LIN_ESCR_LBL1                *((volatile unsigned int*)(0x4270808CUL))\r
+#define bFM3_MFS4_LIN_ESCR_LBIE                *((volatile unsigned int*)(0x42708090UL))\r
+#define bFM3_MFS4_LIN_ESCR_ESBL                *((volatile unsigned int*)(0x42708098UL))\r
+#define bFM3_MFS4_LIN_SSR_TBI                  *((volatile unsigned int*)(0x427080A0UL))\r
+#define bFM3_MFS4_LIN_SSR_TDRE                 *((volatile unsigned int*)(0x427080A4UL))\r
+#define bFM3_MFS4_LIN_SSR_RDRF                 *((volatile unsigned int*)(0x427080A8UL))\r
+#define bFM3_MFS4_LIN_SSR_ORE                  *((volatile unsigned int*)(0x427080ACUL))\r
+#define bFM3_MFS4_LIN_SSR_FRE                  *((volatile unsigned int*)(0x427080B0UL))\r
+#define bFM3_MFS4_LIN_SSR_LBD                  *((volatile unsigned int*)(0x427080B4UL))\r
+#define bFM3_MFS4_LIN_SSR_REC                  *((volatile unsigned int*)(0x427080BCUL))\r
+#define bFM3_MFS4_LIN_BGR_EXT                  *((volatile unsigned int*)(0x427081BCUL))\r
+#define bFM3_MFS4_LIN_BGR1_EXT                 *((volatile unsigned int*)(0x427081BCUL))\r
+#define bFM3_MFS4_LIN_FCR_FE1                  *((volatile unsigned int*)(0x42708280UL))\r
+#define bFM3_MFS4_LIN_FCR_FE2                  *((volatile unsigned int*)(0x42708284UL))\r
+#define bFM3_MFS4_LIN_FCR_FCL1                 *((volatile unsigned int*)(0x42708288UL))\r
+#define bFM3_MFS4_LIN_FCR_FCL2                 *((volatile unsigned int*)(0x4270828CUL))\r
+#define bFM3_MFS4_LIN_FCR_FSET                 *((volatile unsigned int*)(0x42708290UL))\r
+#define bFM3_MFS4_LIN_FCR_FLD                  *((volatile unsigned int*)(0x42708294UL))\r
+#define bFM3_MFS4_LIN_FCR_FLST                 *((volatile unsigned int*)(0x42708298UL))\r
+#define bFM3_MFS4_LIN_FCR_FSEL                 *((volatile unsigned int*)(0x427082A0UL))\r
+#define bFM3_MFS4_LIN_FCR_FTIE                 *((volatile unsigned int*)(0x427082A4UL))\r
+#define bFM3_MFS4_LIN_FCR_FDRQ                 *((volatile unsigned int*)(0x427082A8UL))\r
+#define bFM3_MFS4_LIN_FCR_FRIE                 *((volatile unsigned int*)(0x427082ACUL))\r
+#define bFM3_MFS4_LIN_FCR_FLSTE                *((volatile unsigned int*)(0x427082B0UL))\r
+#define bFM3_MFS4_LIN_FCR_FTST0                *((volatile unsigned int*)(0x427082B8UL))\r
+#define bFM3_MFS4_LIN_FCR_FTST1                *((volatile unsigned int*)(0x427082BCUL))\r
+#define bFM3_MFS4_LIN_FCR0_FE1                 *((volatile unsigned int*)(0x42708280UL))\r
+#define bFM3_MFS4_LIN_FCR0_FE2                 *((volatile unsigned int*)(0x42708284UL))\r
+#define bFM3_MFS4_LIN_FCR0_FCL1                *((volatile unsigned int*)(0x42708288UL))\r
+#define bFM3_MFS4_LIN_FCR0_FCL2                *((volatile unsigned int*)(0x4270828CUL))\r
+#define bFM3_MFS4_LIN_FCR0_FSET                *((volatile unsigned int*)(0x42708290UL))\r
+#define bFM3_MFS4_LIN_FCR0_FLD                 *((volatile unsigned int*)(0x42708294UL))\r
+#define bFM3_MFS4_LIN_FCR0_FLST                *((volatile unsigned int*)(0x42708298UL))\r
+#define bFM3_MFS4_LIN_FCR1_FSEL                *((volatile unsigned int*)(0x427082A0UL))\r
+#define bFM3_MFS4_LIN_FCR1_FTIE                *((volatile unsigned int*)(0x427082A4UL))\r
+#define bFM3_MFS4_LIN_FCR1_FDRQ                *((volatile unsigned int*)(0x427082A8UL))\r
+#define bFM3_MFS4_LIN_FCR1_FRIE                *((volatile unsigned int*)(0x427082ACUL))\r
+#define bFM3_MFS4_LIN_FCR1_FLSTE               *((volatile unsigned int*)(0x427082B0UL))\r
+#define bFM3_MFS4_LIN_FCR1_FTST0               *((volatile unsigned int*)(0x427082B8UL))\r
+#define bFM3_MFS4_LIN_FCR1_FTST1               *((volatile unsigned int*)(0x427082BCUL))\r
+#define bFM3_MFS4_LIN_FBYTE_FD0                *((volatile unsigned int*)(0x42708300UL))\r
+#define bFM3_MFS4_LIN_FBYTE_FD1                *((volatile unsigned int*)(0x42708304UL))\r
+#define bFM3_MFS4_LIN_FBYTE_FD2                *((volatile unsigned int*)(0x42708308UL))\r
+#define bFM3_MFS4_LIN_FBYTE_FD3                *((volatile unsigned int*)(0x4270830CUL))\r
+#define bFM3_MFS4_LIN_FBYTE_FD4                *((volatile unsigned int*)(0x42708310UL))\r
+#define bFM3_MFS4_LIN_FBYTE_FD5                *((volatile unsigned int*)(0x42708314UL))\r
+#define bFM3_MFS4_LIN_FBYTE_FD6                *((volatile unsigned int*)(0x42708318UL))\r
+#define bFM3_MFS4_LIN_FBYTE_FD7                *((volatile unsigned int*)(0x4270831CUL))\r
+#define bFM3_MFS4_LIN_FBYTE_FD8                *((volatile unsigned int*)(0x42708320UL))\r
+#define bFM3_MFS4_LIN_FBYTE_FD9                *((volatile unsigned int*)(0x42708324UL))\r
+#define bFM3_MFS4_LIN_FBYTE_FD10               *((volatile unsigned int*)(0x42708328UL))\r
+#define bFM3_MFS4_LIN_FBYTE_FD11               *((volatile unsigned int*)(0x4270832CUL))\r
+#define bFM3_MFS4_LIN_FBYTE_FD12               *((volatile unsigned int*)(0x42708330UL))\r
+#define bFM3_MFS4_LIN_FBYTE_FD13               *((volatile unsigned int*)(0x42708334UL))\r
+#define bFM3_MFS4_LIN_FBYTE_FD14               *((volatile unsigned int*)(0x42708338UL))\r
+#define bFM3_MFS4_LIN_FBYTE_FD15               *((volatile unsigned int*)(0x4270833CUL))\r
+#define bFM3_MFS4_LIN_FBYTE1_FD0               *((volatile unsigned int*)(0x42708300UL))\r
+#define bFM3_MFS4_LIN_FBYTE1_FD1               *((volatile unsigned int*)(0x42708304UL))\r
+#define bFM3_MFS4_LIN_FBYTE1_FD2               *((volatile unsigned int*)(0x42708308UL))\r
+#define bFM3_MFS4_LIN_FBYTE1_FD3               *((volatile unsigned int*)(0x4270830CUL))\r
+#define bFM3_MFS4_LIN_FBYTE1_FD4               *((volatile unsigned int*)(0x42708310UL))\r
+#define bFM3_MFS4_LIN_FBYTE1_FD5               *((volatile unsigned int*)(0x42708314UL))\r
+#define bFM3_MFS4_LIN_FBYTE1_FD6               *((volatile unsigned int*)(0x42708318UL))\r
+#define bFM3_MFS4_LIN_FBYTE1_FD7               *((volatile unsigned int*)(0x4270831CUL))\r
+#define bFM3_MFS4_LIN_FBYTE2_FD8               *((volatile unsigned int*)(0x42708320UL))\r
+#define bFM3_MFS4_LIN_FBYTE2_FD9               *((volatile unsigned int*)(0x42708324UL))\r
+#define bFM3_MFS4_LIN_FBYTE2_FD10              *((volatile unsigned int*)(0x42708328UL))\r
+#define bFM3_MFS4_LIN_FBYTE2_FD11              *((volatile unsigned int*)(0x4270832CUL))\r
+#define bFM3_MFS4_LIN_FBYTE2_FD12              *((volatile unsigned int*)(0x42708330UL))\r
+#define bFM3_MFS4_LIN_FBYTE2_FD13              *((volatile unsigned int*)(0x42708334UL))\r
+#define bFM3_MFS4_LIN_FBYTE2_FD14              *((volatile unsigned int*)(0x42708338UL))\r
+#define bFM3_MFS4_LIN_FBYTE2_FD15              *((volatile unsigned int*)(0x4270833CUL))\r
+\r
+/* I2C channel 4 registers */\r
+#define bFM3_MFS4_I2C_SMR_ITST0                *((volatile unsigned int*)(0x42708000UL))\r
+#define bFM3_MFS4_I2C_SMR_ITST1                *((volatile unsigned int*)(0x42708004UL))\r
+#define bFM3_MFS4_I2C_SMR_TIE                  *((volatile unsigned int*)(0x42708008UL))\r
+#define bFM3_MFS4_I2C_SMR_RIE                  *((volatile unsigned int*)(0x4270800CUL))\r
+#define bFM3_MFS4_I2C_SMR_WUCR                 *((volatile unsigned int*)(0x42708010UL))\r
+#define bFM3_MFS4_I2C_SMR_MD0                  *((volatile unsigned int*)(0x42708014UL))\r
+#define bFM3_MFS4_I2C_SMR_MD1                  *((volatile unsigned int*)(0x42708018UL))\r
+#define bFM3_MFS4_I2C_SMR_MD2                  *((volatile unsigned int*)(0x4270801CUL))\r
+#define bFM3_MFS4_I2C_IBCR_INT                 *((volatile unsigned int*)(0x42708020UL))\r
+#define bFM3_MFS4_I2C_IBCR_BER                 *((volatile unsigned int*)(0x42708024UL))\r
+#define bFM3_MFS4_I2C_IBCR_INTE                *((volatile unsigned int*)(0x42708028UL))\r
+#define bFM3_MFS4_I2C_IBCR_CNDE                *((volatile unsigned int*)(0x4270802CUL))\r
+#define bFM3_MFS4_I2C_IBCR_WSEL                *((volatile unsigned int*)(0x42708030UL))\r
+#define bFM3_MFS4_I2C_IBCR_ACKE                *((volatile unsigned int*)(0x42708034UL))\r
+#define bFM3_MFS4_I2C_IBCR_ACT                 *((volatile unsigned int*)(0x42708038UL))\r
+#define bFM3_MFS4_I2C_IBCR_SCC                 *((volatile unsigned int*)(0x42708038UL))\r
+#define bFM3_MFS4_I2C_IBCR_MSS                 *((volatile unsigned int*)(0x4270803CUL))\r
+#define bFM3_MFS4_I2C_IBSR_BB                  *((volatile unsigned int*)(0x42708080UL))\r
+#define bFM3_MFS4_I2C_IBSR_SPC                 *((volatile unsigned int*)(0x42708084UL))\r
+#define bFM3_MFS4_I2C_IBSR_RSC                 *((volatile unsigned int*)(0x42708088UL))\r
+#define bFM3_MFS4_I2C_IBSR_AL                  *((volatile unsigned int*)(0x4270808CUL))\r
+#define bFM3_MFS4_I2C_IBSR_TRX                 *((volatile unsigned int*)(0x42708090UL))\r
+#define bFM3_MFS4_I2C_IBSR_RSA                 *((volatile unsigned int*)(0x42708094UL))\r
+#define bFM3_MFS4_I2C_IBSR_RACK                *((volatile unsigned int*)(0x42708098UL))\r
+#define bFM3_MFS4_I2C_IBSR_FBT                 *((volatile unsigned int*)(0x4270809CUL))\r
+#define bFM3_MFS4_I2C_SSR_TBI                  *((volatile unsigned int*)(0x427080A0UL))\r
+#define bFM3_MFS4_I2C_SSR_TDRE                 *((volatile unsigned int*)(0x427080A4UL))\r
+#define bFM3_MFS4_I2C_SSR_RDRF                 *((volatile unsigned int*)(0x427080A8UL))\r
+#define bFM3_MFS4_I2C_SSR_ORE                  *((volatile unsigned int*)(0x427080ACUL))\r
+#define bFM3_MFS4_I2C_SSR_TBIE                 *((volatile unsigned int*)(0x427080B0UL))\r
+#define bFM3_MFS4_I2C_SSR_DMA                  *((volatile unsigned int*)(0x427080B4UL))\r
+#define bFM3_MFS4_I2C_SSR_TSET                 *((volatile unsigned int*)(0x427080B8UL))\r
+#define bFM3_MFS4_I2C_SSR_REC                  *((volatile unsigned int*)(0x427080BCUL))\r
+#define bFM3_MFS4_I2C_ISBA_SA0                 *((volatile unsigned int*)(0x42708200UL))\r
+#define bFM3_MFS4_I2C_ISBA_SA1                 *((volatile unsigned int*)(0x42708204UL))\r
+#define bFM3_MFS4_I2C_ISBA_SA2                 *((volatile unsigned int*)(0x42708208UL))\r
+#define bFM3_MFS4_I2C_ISBA_SA3                 *((volatile unsigned int*)(0x4270820CUL))\r
+#define bFM3_MFS4_I2C_ISBA_SA4                 *((volatile unsigned int*)(0x42708210UL))\r
+#define bFM3_MFS4_I2C_ISBA_SA5                 *((volatile unsigned int*)(0x42708214UL))\r
+#define bFM3_MFS4_I2C_ISBA_SA6                 *((volatile unsigned int*)(0x42708218UL))\r
+#define bFM3_MFS4_I2C_ISBA_SAEN                *((volatile unsigned int*)(0x4270821CUL))\r
+#define bFM3_MFS4_I2C_ISMK_SM0                 *((volatile unsigned int*)(0x42708220UL))\r
+#define bFM3_MFS4_I2C_ISMK_SM1                 *((volatile unsigned int*)(0x42708224UL))\r
+#define bFM3_MFS4_I2C_ISMK_SM2                 *((volatile unsigned int*)(0x42708228UL))\r
+#define bFM3_MFS4_I2C_ISMK_SM3                 *((volatile unsigned int*)(0x4270822CUL))\r
+#define bFM3_MFS4_I2C_ISMK_SM4                 *((volatile unsigned int*)(0x42708230UL))\r
+#define bFM3_MFS4_I2C_ISMK_SM5                 *((volatile unsigned int*)(0x42708234UL))\r
+#define bFM3_MFS4_I2C_ISMK_SM6                 *((volatile unsigned int*)(0x42708238UL))\r
+#define bFM3_MFS4_I2C_ISMK_EN                  *((volatile unsigned int*)(0x4270823CUL))\r
+#define bFM3_MFS4_I2C_FCR_FE1                  *((volatile unsigned int*)(0x42708280UL))\r
+#define bFM3_MFS4_I2C_FCR_FE2                  *((volatile unsigned int*)(0x42708284UL))\r
+#define bFM3_MFS4_I2C_FCR_FCL1                 *((volatile unsigned int*)(0x42708288UL))\r
+#define bFM3_MFS4_I2C_FCR_FCL2                 *((volatile unsigned int*)(0x4270828CUL))\r
+#define bFM3_MFS4_I2C_FCR_FSET                 *((volatile unsigned int*)(0x42708290UL))\r
+#define bFM3_MFS4_I2C_FCR_FLD                  *((volatile unsigned int*)(0x42708294UL))\r
+#define bFM3_MFS4_I2C_FCR_FLST                 *((volatile unsigned int*)(0x42708298UL))\r
+#define bFM3_MFS4_I2C_FCR_FSEL                 *((volatile unsigned int*)(0x427082A0UL))\r
+#define bFM3_MFS4_I2C_FCR_FTIE                 *((volatile unsigned int*)(0x427082A4UL))\r
+#define bFM3_MFS4_I2C_FCR_FDRQ                 *((volatile unsigned int*)(0x427082A8UL))\r
+#define bFM3_MFS4_I2C_FCR_FRIE                 *((volatile unsigned int*)(0x427082ACUL))\r
+#define bFM3_MFS4_I2C_FCR_FLSTE                *((volatile unsigned int*)(0x427082B0UL))\r
+#define bFM3_MFS4_I2C_FCR_FTST0                *((volatile unsigned int*)(0x427082B8UL))\r
+#define bFM3_MFS4_I2C_FCR_FTST1                *((volatile unsigned int*)(0x427082BCUL))\r
+#define bFM3_MFS4_I2C_FCR0_FE1                 *((volatile unsigned int*)(0x42708280UL))\r
+#define bFM3_MFS4_I2C_FCR0_FE2                 *((volatile unsigned int*)(0x42708284UL))\r
+#define bFM3_MFS4_I2C_FCR0_FCL1                *((volatile unsigned int*)(0x42708288UL))\r
+#define bFM3_MFS4_I2C_FCR0_FCL2                *((volatile unsigned int*)(0x4270828CUL))\r
+#define bFM3_MFS4_I2C_FCR0_FSET                *((volatile unsigned int*)(0x42708290UL))\r
+#define bFM3_MFS4_I2C_FCR0_FLD                 *((volatile unsigned int*)(0x42708294UL))\r
+#define bFM3_MFS4_I2C_FCR0_FLST                *((volatile unsigned int*)(0x42708298UL))\r
+#define bFM3_MFS4_I2C_FCR1_FSEL                *((volatile unsigned int*)(0x427082A0UL))\r
+#define bFM3_MFS4_I2C_FCR1_FTIE                *((volatile unsigned int*)(0x427082A4UL))\r
+#define bFM3_MFS4_I2C_FCR1_FDRQ                *((volatile unsigned int*)(0x427082A8UL))\r
+#define bFM3_MFS4_I2C_FCR1_FRIE                *((volatile unsigned int*)(0x427082ACUL))\r
+#define bFM3_MFS4_I2C_FCR1_FLSTE               *((volatile unsigned int*)(0x427082B0UL))\r
+#define bFM3_MFS4_I2C_FCR1_FTST0               *((volatile unsigned int*)(0x427082B8UL))\r
+#define bFM3_MFS4_I2C_FCR1_FTST1               *((volatile unsigned int*)(0x427082BCUL))\r
+#define bFM3_MFS4_I2C_FBYTE_FD0                *((volatile unsigned int*)(0x42708300UL))\r
+#define bFM3_MFS4_I2C_FBYTE_FD1                *((volatile unsigned int*)(0x42708304UL))\r
+#define bFM3_MFS4_I2C_FBYTE_FD2                *((volatile unsigned int*)(0x42708308UL))\r
+#define bFM3_MFS4_I2C_FBYTE_FD3                *((volatile unsigned int*)(0x4270830CUL))\r
+#define bFM3_MFS4_I2C_FBYTE_FD4                *((volatile unsigned int*)(0x42708310UL))\r
+#define bFM3_MFS4_I2C_FBYTE_FD5                *((volatile unsigned int*)(0x42708314UL))\r
+#define bFM3_MFS4_I2C_FBYTE_FD6                *((volatile unsigned int*)(0x42708318UL))\r
+#define bFM3_MFS4_I2C_FBYTE_FD7                *((volatile unsigned int*)(0x4270831CUL))\r
+#define bFM3_MFS4_I2C_FBYTE_FD8                *((volatile unsigned int*)(0x42708320UL))\r
+#define bFM3_MFS4_I2C_FBYTE_FD9                *((volatile unsigned int*)(0x42708324UL))\r
+#define bFM3_MFS4_I2C_FBYTE_FD10               *((volatile unsigned int*)(0x42708328UL))\r
+#define bFM3_MFS4_I2C_FBYTE_FD11               *((volatile unsigned int*)(0x4270832CUL))\r
+#define bFM3_MFS4_I2C_FBYTE_FD12               *((volatile unsigned int*)(0x42708330UL))\r
+#define bFM3_MFS4_I2C_FBYTE_FD13               *((volatile unsigned int*)(0x42708334UL))\r
+#define bFM3_MFS4_I2C_FBYTE_FD14               *((volatile unsigned int*)(0x42708338UL))\r
+#define bFM3_MFS4_I2C_FBYTE_FD15               *((volatile unsigned int*)(0x4270833CUL))\r
+#define bFM3_MFS4_I2C_FBYTE1_FD0               *((volatile unsigned int*)(0x42708300UL))\r
+#define bFM3_MFS4_I2C_FBYTE1_FD1               *((volatile unsigned int*)(0x42708304UL))\r
+#define bFM3_MFS4_I2C_FBYTE1_FD2               *((volatile unsigned int*)(0x42708308UL))\r
+#define bFM3_MFS4_I2C_FBYTE1_FD3               *((volatile unsigned int*)(0x4270830CUL))\r
+#define bFM3_MFS4_I2C_FBYTE1_FD4               *((volatile unsigned int*)(0x42708310UL))\r
+#define bFM3_MFS4_I2C_FBYTE1_FD5               *((volatile unsigned int*)(0x42708314UL))\r
+#define bFM3_MFS4_I2C_FBYTE1_FD6               *((volatile unsigned int*)(0x42708318UL))\r
+#define bFM3_MFS4_I2C_FBYTE1_FD7               *((volatile unsigned int*)(0x4270831CUL))\r
+#define bFM3_MFS4_I2C_FBYTE2_FD8               *((volatile unsigned int*)(0x42708320UL))\r
+#define bFM3_MFS4_I2C_FBYTE2_FD9               *((volatile unsigned int*)(0x42708324UL))\r
+#define bFM3_MFS4_I2C_FBYTE2_FD10              *((volatile unsigned int*)(0x42708328UL))\r
+#define bFM3_MFS4_I2C_FBYTE2_FD11              *((volatile unsigned int*)(0x4270832CUL))\r
+#define bFM3_MFS4_I2C_FBYTE2_FD12              *((volatile unsigned int*)(0x42708330UL))\r
+#define bFM3_MFS4_I2C_FBYTE2_FD13              *((volatile unsigned int*)(0x42708334UL))\r
+#define bFM3_MFS4_I2C_FBYTE2_FD14              *((volatile unsigned int*)(0x42708338UL))\r
+#define bFM3_MFS4_I2C_FBYTE2_FD15              *((volatile unsigned int*)(0x4270833CUL))\r
+\r
+/* UART asynchronous channel 5 registers */\r
+#define bFM3_MFS5_UART_SMR_SOE                 *((volatile unsigned int*)(0x4270A000UL))\r
+#define bFM3_MFS5_UART_SMR_BDS                 *((volatile unsigned int*)(0x4270A008UL))\r
+#define bFM3_MFS5_UART_SMR_SBL                 *((volatile unsigned int*)(0x4270A00CUL))\r
+#define bFM3_MFS5_UART_SMR_WUCR                *((volatile unsigned int*)(0x4270A010UL))\r
+#define bFM3_MFS5_UART_SMR_MD0                 *((volatile unsigned int*)(0x4270A014UL))\r
+#define bFM3_MFS5_UART_SMR_MD1                 *((volatile unsigned int*)(0x4270A018UL))\r
+#define bFM3_MFS5_UART_SMR_MD2                 *((volatile unsigned int*)(0x4270A01CUL))\r
+#define bFM3_MFS5_UART_SCR_TXE                 *((volatile unsigned int*)(0x4270A020UL))\r
+#define bFM3_MFS5_UART_SCR_RXE                 *((volatile unsigned int*)(0x4270A024UL))\r
+#define bFM3_MFS5_UART_SCR_TBIE                *((volatile unsigned int*)(0x4270A028UL))\r
+#define bFM3_MFS5_UART_SCR_TIE                 *((volatile unsigned int*)(0x4270A02CUL))\r
+#define bFM3_MFS5_UART_SCR_RIE                 *((volatile unsigned int*)(0x4270A030UL))\r
+#define bFM3_MFS5_UART_SCR_UPCL                *((volatile unsigned int*)(0x4270A03CUL))\r
+#define bFM3_MFS5_UART_ESCR_L0                 *((volatile unsigned int*)(0x4270A080UL))\r
+#define bFM3_MFS5_UART_ESCR_L1                 *((volatile unsigned int*)(0x4270A084UL))\r
+#define bFM3_MFS5_UART_ESCR_L2                 *((volatile unsigned int*)(0x4270A088UL))\r
+#define bFM3_MFS5_UART_ESCR_P                  *((volatile unsigned int*)(0x4270A08CUL))\r
+#define bFM3_MFS5_UART_ESCR_PEN                *((volatile unsigned int*)(0x4270A090UL))\r
+#define bFM3_MFS5_UART_ESCR_INV                *((volatile unsigned int*)(0x4270A094UL))\r
+#define bFM3_MFS5_UART_ESCR_ESBL               *((volatile unsigned int*)(0x4270A098UL))\r
+#define bFM3_MFS5_UART_ESCR_FLWEN              *((volatile unsigned int*)(0x4270A09CUL))\r
+#define bFM3_MFS5_UART_SSR_TBI                 *((volatile unsigned int*)(0x4270A0A0UL))\r
+#define bFM3_MFS5_UART_SSR_TDRE                *((volatile unsigned int*)(0x4270A0A4UL))\r
+#define bFM3_MFS5_UART_SSR_RDRF                *((volatile unsigned int*)(0x4270A0A8UL))\r
+#define bFM3_MFS5_UART_SSR_ORE                 *((volatile unsigned int*)(0x4270A0ACUL))\r
+#define bFM3_MFS5_UART_SSR_FRE                 *((volatile unsigned int*)(0x4270A0B0UL))\r
+#define bFM3_MFS5_UART_SSR_PE                  *((volatile unsigned int*)(0x4270A0B4UL))\r
+#define bFM3_MFS5_UART_SSR_REC                 *((volatile unsigned int*)(0x4270A0BCUL))\r
+#define bFM3_MFS5_UART_RDR_AD                  *((volatile unsigned int*)(0x4270A120UL))\r
+#define bFM3_MFS5_UART_TDR_AD                  *((volatile unsigned int*)(0x4270A120UL))\r
+#define bFM3_MFS5_UART_BGR_EXT                 *((volatile unsigned int*)(0x4270A1BCUL))\r
+#define bFM3_MFS5_UART_BGR1_EXT                *((volatile unsigned int*)(0x4270A1BCUL))\r
+#define bFM3_MFS5_UART_FCR_FE1                 *((volatile unsigned int*)(0x4270A280UL))\r
+#define bFM3_MFS5_UART_FCR_FE2                 *((volatile unsigned int*)(0x4270A284UL))\r
+#define bFM3_MFS5_UART_FCR_FCL1                *((volatile unsigned int*)(0x4270A288UL))\r
+#define bFM3_MFS5_UART_FCR_FCL2                *((volatile unsigned int*)(0x4270A28CUL))\r
+#define bFM3_MFS5_UART_FCR_FSET                *((volatile unsigned int*)(0x4270A290UL))\r
+#define bFM3_MFS5_UART_FCR_FLD                 *((volatile unsigned int*)(0x4270A294UL))\r
+#define bFM3_MFS5_UART_FCR_FLST                *((volatile unsigned int*)(0x4270A298UL))\r
+#define bFM3_MFS5_UART_FCR_FSEL                *((volatile unsigned int*)(0x4270A2A0UL))\r
+#define bFM3_MFS5_UART_FCR_FTIE                *((volatile unsigned int*)(0x4270A2A4UL))\r
+#define bFM3_MFS5_UART_FCR_FDRQ                *((volatile unsigned int*)(0x4270A2A8UL))\r
+#define bFM3_MFS5_UART_FCR_FRIE                *((volatile unsigned int*)(0x4270A2ACUL))\r
+#define bFM3_MFS5_UART_FCR_FLSTE               *((volatile unsigned int*)(0x4270A2B0UL))\r
+#define bFM3_MFS5_UART_FCR_FTST0               *((volatile unsigned int*)(0x4270A2B8UL))\r
+#define bFM3_MFS5_UART_FCR_FTST1               *((volatile unsigned int*)(0x4270A2BCUL))\r
+#define bFM3_MFS5_UART_FCR0_FE1                *((volatile unsigned int*)(0x4270A280UL))\r
+#define bFM3_MFS5_UART_FCR0_FE2                *((volatile unsigned int*)(0x4270A284UL))\r
+#define bFM3_MFS5_UART_FCR0_FCL1               *((volatile unsigned int*)(0x4270A288UL))\r
+#define bFM3_MFS5_UART_FCR0_FCL2               *((volatile unsigned int*)(0x4270A28CUL))\r
+#define bFM3_MFS5_UART_FCR0_FSET               *((volatile unsigned int*)(0x4270A290UL))\r
+#define bFM3_MFS5_UART_FCR0_FLD                *((volatile unsigned int*)(0x4270A294UL))\r
+#define bFM3_MFS5_UART_FCR0_FLST               *((volatile unsigned int*)(0x4270A298UL))\r
+#define bFM3_MFS5_UART_FCR1_FSEL               *((volatile unsigned int*)(0x4270A2A0UL))\r
+#define bFM3_MFS5_UART_FCR1_FTIE               *((volatile unsigned int*)(0x4270A2A4UL))\r
+#define bFM3_MFS5_UART_FCR1_FDRQ               *((volatile unsigned int*)(0x4270A2A8UL))\r
+#define bFM3_MFS5_UART_FCR1_FRIE               *((volatile unsigned int*)(0x4270A2ACUL))\r
+#define bFM3_MFS5_UART_FCR1_FLSTE              *((volatile unsigned int*)(0x4270A2B0UL))\r
+#define bFM3_MFS5_UART_FCR1_FTST0              *((volatile unsigned int*)(0x4270A2B8UL))\r
+#define bFM3_MFS5_UART_FCR1_FTST1              *((volatile unsigned int*)(0x4270A2BCUL))\r
+#define bFM3_MFS5_UART_FBYTE_FD0               *((volatile unsigned int*)(0x4270A300UL))\r
+#define bFM3_MFS5_UART_FBYTE_FD1               *((volatile unsigned int*)(0x4270A304UL))\r
+#define bFM3_MFS5_UART_FBYTE_FD2               *((volatile unsigned int*)(0x4270A308UL))\r
+#define bFM3_MFS5_UART_FBYTE_FD3               *((volatile unsigned int*)(0x4270A30CUL))\r
+#define bFM3_MFS5_UART_FBYTE_FD4               *((volatile unsigned int*)(0x4270A310UL))\r
+#define bFM3_MFS5_UART_FBYTE_FD5               *((volatile unsigned int*)(0x4270A314UL))\r
+#define bFM3_MFS5_UART_FBYTE_FD6               *((volatile unsigned int*)(0x4270A318UL))\r
+#define bFM3_MFS5_UART_FBYTE_FD7               *((volatile unsigned int*)(0x4270A31CUL))\r
+#define bFM3_MFS5_UART_FBYTE_FD8               *((volatile unsigned int*)(0x4270A320UL))\r
+#define bFM3_MFS5_UART_FBYTE_FD9               *((volatile unsigned int*)(0x4270A324UL))\r
+#define bFM3_MFS5_UART_FBYTE_FD10              *((volatile unsigned int*)(0x4270A328UL))\r
+#define bFM3_MFS5_UART_FBYTE_FD11              *((volatile unsigned int*)(0x4270A32CUL))\r
+#define bFM3_MFS5_UART_FBYTE_FD12              *((volatile unsigned int*)(0x4270A330UL))\r
+#define bFM3_MFS5_UART_FBYTE_FD13              *((volatile unsigned int*)(0x4270A334UL))\r
+#define bFM3_MFS5_UART_FBYTE_FD14              *((volatile unsigned int*)(0x4270A338UL))\r
+#define bFM3_MFS5_UART_FBYTE_FD15              *((volatile unsigned int*)(0x4270A33CUL))\r
+#define bFM3_MFS5_UART_FBYTE1_FD0              *((volatile unsigned int*)(0x4270A300UL))\r
+#define bFM3_MFS5_UART_FBYTE1_FD1              *((volatile unsigned int*)(0x4270A304UL))\r
+#define bFM3_MFS5_UART_FBYTE1_FD2              *((volatile unsigned int*)(0x4270A308UL))\r
+#define bFM3_MFS5_UART_FBYTE1_FD3              *((volatile unsigned int*)(0x4270A30CUL))\r
+#define bFM3_MFS5_UART_FBYTE1_FD4              *((volatile unsigned int*)(0x4270A310UL))\r
+#define bFM3_MFS5_UART_FBYTE1_FD5              *((volatile unsigned int*)(0x4270A314UL))\r
+#define bFM3_MFS5_UART_FBYTE1_FD6              *((volatile unsigned int*)(0x4270A318UL))\r
+#define bFM3_MFS5_UART_FBYTE1_FD7              *((volatile unsigned int*)(0x4270A31CUL))\r
+#define bFM3_MFS5_UART_FBYTE2_FD8              *((volatile unsigned int*)(0x4270A320UL))\r
+#define bFM3_MFS5_UART_FBYTE2_FD9              *((volatile unsigned int*)(0x4270A324UL))\r
+#define bFM3_MFS5_UART_FBYTE2_FD10             *((volatile unsigned int*)(0x4270A328UL))\r
+#define bFM3_MFS5_UART_FBYTE2_FD11             *((volatile unsigned int*)(0x4270A32CUL))\r
+#define bFM3_MFS5_UART_FBYTE2_FD12             *((volatile unsigned int*)(0x4270A330UL))\r
+#define bFM3_MFS5_UART_FBYTE2_FD13             *((volatile unsigned int*)(0x4270A334UL))\r
+#define bFM3_MFS5_UART_FBYTE2_FD14             *((volatile unsigned int*)(0x4270A338UL))\r
+#define bFM3_MFS5_UART_FBYTE2_FD15             *((volatile unsigned int*)(0x4270A33CUL))\r
+\r
+/* UART synchronous channel 5 registers */\r
+#define bFM3_MFS5_CSIO_SMR_SOE                 *((volatile unsigned int*)(0x4270A000UL))\r
+#define bFM3_MFS5_CSIO_SMR_SCKE                *((volatile unsigned int*)(0x4270A004UL))\r
+#define bFM3_MFS5_CSIO_SMR_BDS                 *((volatile unsigned int*)(0x4270A008UL))\r
+#define bFM3_MFS5_CSIO_SMR_SCINV               *((volatile unsigned int*)(0x4270A00CUL))\r
+#define bFM3_MFS5_CSIO_SMR_WUCR                *((volatile unsigned int*)(0x4270A010UL))\r
+#define bFM3_MFS5_CSIO_SMR_MD0                 *((volatile unsigned int*)(0x4270A014UL))\r
+#define bFM3_MFS5_CSIO_SMR_MD1                 *((volatile unsigned int*)(0x4270A018UL))\r
+#define bFM3_MFS5_CSIO_SMR_MD2                 *((volatile unsigned int*)(0x4270A01CUL))\r
+#define bFM3_MFS5_CSIO_SCR_TXE                 *((volatile unsigned int*)(0x4270A020UL))\r
+#define bFM3_MFS5_CSIO_SCR_RXE                 *((volatile unsigned int*)(0x4270A024UL))\r
+#define bFM3_MFS5_CSIO_SCR_TBIE                *((volatile unsigned int*)(0x4270A028UL))\r
+#define bFM3_MFS5_CSIO_SCR_TIE                 *((volatile unsigned int*)(0x4270A02CUL))\r
+#define bFM3_MFS5_CSIO_SCR_RIE                 *((volatile unsigned int*)(0x4270A030UL))\r
+#define bFM3_MFS5_CSIO_SCR_SPI                 *((volatile unsigned int*)(0x4270A034UL))\r
+#define bFM3_MFS5_CSIO_SCR_MS                  *((volatile unsigned int*)(0x4270A038UL))\r
+#define bFM3_MFS5_CSIO_SCR_UPCL                *((volatile unsigned int*)(0x4270A03CUL))\r
+#define bFM3_MFS5_CSIO_ESCR_L0                 *((volatile unsigned int*)(0x4270A080UL))\r
+#define bFM3_MFS5_CSIO_ESCR_L1                 *((volatile unsigned int*)(0x4270A084UL))\r
+#define bFM3_MFS5_CSIO_ESCR_L2                 *((volatile unsigned int*)(0x4270A088UL))\r
+#define bFM3_MFS5_CSIO_ESCR_WT0                *((volatile unsigned int*)(0x4270A08CUL))\r
+#define bFM3_MFS5_CSIO_ESCR_WT1                *((volatile unsigned int*)(0x4270A090UL))\r
+#define bFM3_MFS5_CSIO_ESCR_SOP                *((volatile unsigned int*)(0x4270A09CUL))\r
+#define bFM3_MFS5_CSIO_SSR_TBI                 *((volatile unsigned int*)(0x4270A0A0UL))\r
+#define bFM3_MFS5_CSIO_SSR_TDRE                *((volatile unsigned int*)(0x4270A0A4UL))\r
+#define bFM3_MFS5_CSIO_SSR_RDRF                *((volatile unsigned int*)(0x4270A0A8UL))\r
+#define bFM3_MFS5_CSIO_SSR_ORE                 *((volatile unsigned int*)(0x4270A0ACUL))\r
+#define bFM3_MFS5_CSIO_SSR_REC                 *((volatile unsigned int*)(0x4270A0BCUL))\r
+#define bFM3_MFS5_CSIO_FCR_FE1                 *((volatile unsigned int*)(0x4270A280UL))\r
+#define bFM3_MFS5_CSIO_FCR_FE2                 *((volatile unsigned int*)(0x4270A284UL))\r
+#define bFM3_MFS5_CSIO_FCR_FCL1                *((volatile unsigned int*)(0x4270A288UL))\r
+#define bFM3_MFS5_CSIO_FCR_FCL2                *((volatile unsigned int*)(0x4270A28CUL))\r
+#define bFM3_MFS5_CSIO_FCR_FSET                *((volatile unsigned int*)(0x4270A290UL))\r
+#define bFM3_MFS5_CSIO_FCR_FLD                 *((volatile unsigned int*)(0x4270A294UL))\r
+#define bFM3_MFS5_CSIO_FCR_FLST                *((volatile unsigned int*)(0x4270A298UL))\r
+#define bFM3_MFS5_CSIO_FCR_FSEL                *((volatile unsigned int*)(0x4270A2A0UL))\r
+#define bFM3_MFS5_CSIO_FCR_FTIE                *((volatile unsigned int*)(0x4270A2A4UL))\r
+#define bFM3_MFS5_CSIO_FCR_FDRQ                *((volatile unsigned int*)(0x4270A2A8UL))\r
+#define bFM3_MFS5_CSIO_FCR_FRIE                *((volatile unsigned int*)(0x4270A2ACUL))\r
+#define bFM3_MFS5_CSIO_FCR_FLSTE               *((volatile unsigned int*)(0x4270A2B0UL))\r
+#define bFM3_MFS5_CSIO_FCR_FTST0               *((volatile unsigned int*)(0x4270A2B8UL))\r
+#define bFM3_MFS5_CSIO_FCR_FTST1               *((volatile unsigned int*)(0x4270A2BCUL))\r
+#define bFM3_MFS5_CSIO_FCR0_FE1                *((volatile unsigned int*)(0x4270A280UL))\r
+#define bFM3_MFS5_CSIO_FCR0_FE2                *((volatile unsigned int*)(0x4270A284UL))\r
+#define bFM3_MFS5_CSIO_FCR0_FCL1               *((volatile unsigned int*)(0x4270A288UL))\r
+#define bFM3_MFS5_CSIO_FCR0_FCL2               *((volatile unsigned int*)(0x4270A28CUL))\r
+#define bFM3_MFS5_CSIO_FCR0_FSET               *((volatile unsigned int*)(0x4270A290UL))\r
+#define bFM3_MFS5_CSIO_FCR0_FLD                *((volatile unsigned int*)(0x4270A294UL))\r
+#define bFM3_MFS5_CSIO_FCR0_FLST               *((volatile unsigned int*)(0x4270A298UL))\r
+#define bFM3_MFS5_CSIO_FCR1_FSEL               *((volatile unsigned int*)(0x4270A2A0UL))\r
+#define bFM3_MFS5_CSIO_FCR1_FTIE               *((volatile unsigned int*)(0x4270A2A4UL))\r
+#define bFM3_MFS5_CSIO_FCR1_FDRQ               *((volatile unsigned int*)(0x4270A2A8UL))\r
+#define bFM3_MFS5_CSIO_FCR1_FRIE               *((volatile unsigned int*)(0x4270A2ACUL))\r
+#define bFM3_MFS5_CSIO_FCR1_FLSTE              *((volatile unsigned int*)(0x4270A2B0UL))\r
+#define bFM3_MFS5_CSIO_FCR1_FTST0              *((volatile unsigned int*)(0x4270A2B8UL))\r
+#define bFM3_MFS5_CSIO_FCR1_FTST1              *((volatile unsigned int*)(0x4270A2BCUL))\r
+#define bFM3_MFS5_CSIO_FBYTE_FD0               *((volatile unsigned int*)(0x4270A300UL))\r
+#define bFM3_MFS5_CSIO_FBYTE_FD1               *((volatile unsigned int*)(0x4270A304UL))\r
+#define bFM3_MFS5_CSIO_FBYTE_FD2               *((volatile unsigned int*)(0x4270A308UL))\r
+#define bFM3_MFS5_CSIO_FBYTE_FD3               *((volatile unsigned int*)(0x4270A30CUL))\r
+#define bFM3_MFS5_CSIO_FBYTE_FD4               *((volatile unsigned int*)(0x4270A310UL))\r
+#define bFM3_MFS5_CSIO_FBYTE_FD5               *((volatile unsigned int*)(0x4270A314UL))\r
+#define bFM3_MFS5_CSIO_FBYTE_FD6               *((volatile unsigned int*)(0x4270A318UL))\r
+#define bFM3_MFS5_CSIO_FBYTE_FD7               *((volatile unsigned int*)(0x4270A31CUL))\r
+#define bFM3_MFS5_CSIO_FBYTE_FD8               *((volatile unsigned int*)(0x4270A320UL))\r
+#define bFM3_MFS5_CSIO_FBYTE_FD9               *((volatile unsigned int*)(0x4270A324UL))\r
+#define bFM3_MFS5_CSIO_FBYTE_FD10              *((volatile unsigned int*)(0x4270A328UL))\r
+#define bFM3_MFS5_CSIO_FBYTE_FD11              *((volatile unsigned int*)(0x4270A32CUL))\r
+#define bFM3_MFS5_CSIO_FBYTE_FD12              *((volatile unsigned int*)(0x4270A330UL))\r
+#define bFM3_MFS5_CSIO_FBYTE_FD13              *((volatile unsigned int*)(0x4270A334UL))\r
+#define bFM3_MFS5_CSIO_FBYTE_FD14              *((volatile unsigned int*)(0x4270A338UL))\r
+#define bFM3_MFS5_CSIO_FBYTE_FD15              *((volatile unsigned int*)(0x4270A33CUL))\r
+#define bFM3_MFS5_CSIO_FBYTE1_FD0              *((volatile unsigned int*)(0x4270A300UL))\r
+#define bFM3_MFS5_CSIO_FBYTE1_FD1              *((volatile unsigned int*)(0x4270A304UL))\r
+#define bFM3_MFS5_CSIO_FBYTE1_FD2              *((volatile unsigned int*)(0x4270A308UL))\r
+#define bFM3_MFS5_CSIO_FBYTE1_FD3              *((volatile unsigned int*)(0x4270A30CUL))\r
+#define bFM3_MFS5_CSIO_FBYTE1_FD4              *((volatile unsigned int*)(0x4270A310UL))\r
+#define bFM3_MFS5_CSIO_FBYTE1_FD5              *((volatile unsigned int*)(0x4270A314UL))\r
+#define bFM3_MFS5_CSIO_FBYTE1_FD6              *((volatile unsigned int*)(0x4270A318UL))\r
+#define bFM3_MFS5_CSIO_FBYTE1_FD7              *((volatile unsigned int*)(0x4270A31CUL))\r
+#define bFM3_MFS5_CSIO_FBYTE2_FD8              *((volatile unsigned int*)(0x4270A320UL))\r
+#define bFM3_MFS5_CSIO_FBYTE2_FD9              *((volatile unsigned int*)(0x4270A324UL))\r
+#define bFM3_MFS5_CSIO_FBYTE2_FD10             *((volatile unsigned int*)(0x4270A328UL))\r
+#define bFM3_MFS5_CSIO_FBYTE2_FD11             *((volatile unsigned int*)(0x4270A32CUL))\r
+#define bFM3_MFS5_CSIO_FBYTE2_FD12             *((volatile unsigned int*)(0x4270A330UL))\r
+#define bFM3_MFS5_CSIO_FBYTE2_FD13             *((volatile unsigned int*)(0x4270A334UL))\r
+#define bFM3_MFS5_CSIO_FBYTE2_FD14             *((volatile unsigned int*)(0x4270A338UL))\r
+#define bFM3_MFS5_CSIO_FBYTE2_FD15             *((volatile unsigned int*)(0x4270A33CUL))\r
+\r
+/* UART LIN channel 5 registers */\r
+#define bFM3_MFS5_LIN_SMR_SOE                  *((volatile unsigned int*)(0x4270A000UL))\r
+#define bFM3_MFS5_LIN_SMR_SBL                  *((volatile unsigned int*)(0x4270A00CUL))\r
+#define bFM3_MFS5_LIN_SMR_WUCR                 *((volatile unsigned int*)(0x4270A010UL))\r
+#define bFM3_MFS5_LIN_SMR_MD0                  *((volatile unsigned int*)(0x4270A014UL))\r
+#define bFM3_MFS5_LIN_SMR_MD1                  *((volatile unsigned int*)(0x4270A018UL))\r
+#define bFM3_MFS5_LIN_SMR_MD2                  *((volatile unsigned int*)(0x4270A01CUL))\r
+#define bFM3_MFS5_LIN_SCR_TXE                  *((volatile unsigned int*)(0x4270A020UL))\r
+#define bFM3_MFS5_LIN_SCR_RXE                  *((volatile unsigned int*)(0x4270A024UL))\r
+#define bFM3_MFS5_LIN_SCR_TBIE                 *((volatile unsigned int*)(0x4270A028UL))\r
+#define bFM3_MFS5_LIN_SCR_TIE                  *((volatile unsigned int*)(0x4270A02CUL))\r
+#define bFM3_MFS5_LIN_SCR_RIE                  *((volatile unsigned int*)(0x4270A030UL))\r
+#define bFM3_MFS5_LIN_SCR_LBR                  *((volatile unsigned int*)(0x4270A034UL))\r
+#define bFM3_MFS5_LIN_SCR_MS                   *((volatile unsigned int*)(0x4270A038UL))\r
+#define bFM3_MFS5_LIN_SCR_UPCL                 *((volatile unsigned int*)(0x4270A03CUL))\r
+#define bFM3_MFS5_LIN_ESCR_DEL0                *((volatile unsigned int*)(0x4270A080UL))\r
+#define bFM3_MFS5_LIN_ESCR_DEL1                *((volatile unsigned int*)(0x4270A084UL))\r
+#define bFM3_MFS5_LIN_ESCR_LBL0                *((volatile unsigned int*)(0x4270A088UL))\r
+#define bFM3_MFS5_LIN_ESCR_LBL1                *((volatile unsigned int*)(0x4270A08CUL))\r
+#define bFM3_MFS5_LIN_ESCR_LBIE                *((volatile unsigned int*)(0x4270A090UL))\r
+#define bFM3_MFS5_LIN_ESCR_ESBL                *((volatile unsigned int*)(0x4270A098UL))\r
+#define bFM3_MFS5_LIN_SSR_TBI                  *((volatile unsigned int*)(0x4270A0A0UL))\r
+#define bFM3_MFS5_LIN_SSR_TDRE                 *((volatile unsigned int*)(0x4270A0A4UL))\r
+#define bFM3_MFS5_LIN_SSR_RDRF                 *((volatile unsigned int*)(0x4270A0A8UL))\r
+#define bFM3_MFS5_LIN_SSR_ORE                  *((volatile unsigned int*)(0x4270A0ACUL))\r
+#define bFM3_MFS5_LIN_SSR_FRE                  *((volatile unsigned int*)(0x4270A0B0UL))\r
+#define bFM3_MFS5_LIN_SSR_LBD                  *((volatile unsigned int*)(0x4270A0B4UL))\r
+#define bFM3_MFS5_LIN_SSR_REC                  *((volatile unsigned int*)(0x4270A0BCUL))\r
+#define bFM3_MFS5_LIN_BGR_EXT                  *((volatile unsigned int*)(0x4270A1BCUL))\r
+#define bFM3_MFS5_LIN_BGR1_EXT                 *((volatile unsigned int*)(0x4270A1BCUL))\r
+#define bFM3_MFS5_LIN_FCR_FE1                  *((volatile unsigned int*)(0x4270A280UL))\r
+#define bFM3_MFS5_LIN_FCR_FE2                  *((volatile unsigned int*)(0x4270A284UL))\r
+#define bFM3_MFS5_LIN_FCR_FCL1                 *((volatile unsigned int*)(0x4270A288UL))\r
+#define bFM3_MFS5_LIN_FCR_FCL2                 *((volatile unsigned int*)(0x4270A28CUL))\r
+#define bFM3_MFS5_LIN_FCR_FSET                 *((volatile unsigned int*)(0x4270A290UL))\r
+#define bFM3_MFS5_LIN_FCR_FLD                  *((volatile unsigned int*)(0x4270A294UL))\r
+#define bFM3_MFS5_LIN_FCR_FLST                 *((volatile unsigned int*)(0x4270A298UL))\r
+#define bFM3_MFS5_LIN_FCR_FSEL                 *((volatile unsigned int*)(0x4270A2A0UL))\r
+#define bFM3_MFS5_LIN_FCR_FTIE                 *((volatile unsigned int*)(0x4270A2A4UL))\r
+#define bFM3_MFS5_LIN_FCR_FDRQ                 *((volatile unsigned int*)(0x4270A2A8UL))\r
+#define bFM3_MFS5_LIN_FCR_FRIE                 *((volatile unsigned int*)(0x4270A2ACUL))\r
+#define bFM3_MFS5_LIN_FCR_FLSTE                *((volatile unsigned int*)(0x4270A2B0UL))\r
+#define bFM3_MFS5_LIN_FCR_FTST0                *((volatile unsigned int*)(0x4270A2B8UL))\r
+#define bFM3_MFS5_LIN_FCR_FTST1                *((volatile unsigned int*)(0x4270A2BCUL))\r
+#define bFM3_MFS5_LIN_FCR0_FE1                 *((volatile unsigned int*)(0x4270A280UL))\r
+#define bFM3_MFS5_LIN_FCR0_FE2                 *((volatile unsigned int*)(0x4270A284UL))\r
+#define bFM3_MFS5_LIN_FCR0_FCL1                *((volatile unsigned int*)(0x4270A288UL))\r
+#define bFM3_MFS5_LIN_FCR0_FCL2                *((volatile unsigned int*)(0x4270A28CUL))\r
+#define bFM3_MFS5_LIN_FCR0_FSET                *((volatile unsigned int*)(0x4270A290UL))\r
+#define bFM3_MFS5_LIN_FCR0_FLD                 *((volatile unsigned int*)(0x4270A294UL))\r
+#define bFM3_MFS5_LIN_FCR0_FLST                *((volatile unsigned int*)(0x4270A298UL))\r
+#define bFM3_MFS5_LIN_FCR1_FSEL                *((volatile unsigned int*)(0x4270A2A0UL))\r
+#define bFM3_MFS5_LIN_FCR1_FTIE                *((volatile unsigned int*)(0x4270A2A4UL))\r
+#define bFM3_MFS5_LIN_FCR1_FDRQ                *((volatile unsigned int*)(0x4270A2A8UL))\r
+#define bFM3_MFS5_LIN_FCR1_FRIE                *((volatile unsigned int*)(0x4270A2ACUL))\r
+#define bFM3_MFS5_LIN_FCR1_FLSTE               *((volatile unsigned int*)(0x4270A2B0UL))\r
+#define bFM3_MFS5_LIN_FCR1_FTST0               *((volatile unsigned int*)(0x4270A2B8UL))\r
+#define bFM3_MFS5_LIN_FCR1_FTST1               *((volatile unsigned int*)(0x4270A2BCUL))\r
+#define bFM3_MFS5_LIN_FBYTE_FD0                *((volatile unsigned int*)(0x4270A300UL))\r
+#define bFM3_MFS5_LIN_FBYTE_FD1                *((volatile unsigned int*)(0x4270A304UL))\r
+#define bFM3_MFS5_LIN_FBYTE_FD2                *((volatile unsigned int*)(0x4270A308UL))\r
+#define bFM3_MFS5_LIN_FBYTE_FD3                *((volatile unsigned int*)(0x4270A30CUL))\r
+#define bFM3_MFS5_LIN_FBYTE_FD4                *((volatile unsigned int*)(0x4270A310UL))\r
+#define bFM3_MFS5_LIN_FBYTE_FD5                *((volatile unsigned int*)(0x4270A314UL))\r
+#define bFM3_MFS5_LIN_FBYTE_FD6                *((volatile unsigned int*)(0x4270A318UL))\r
+#define bFM3_MFS5_LIN_FBYTE_FD7                *((volatile unsigned int*)(0x4270A31CUL))\r
+#define bFM3_MFS5_LIN_FBYTE_FD8                *((volatile unsigned int*)(0x4270A320UL))\r
+#define bFM3_MFS5_LIN_FBYTE_FD9                *((volatile unsigned int*)(0x4270A324UL))\r
+#define bFM3_MFS5_LIN_FBYTE_FD10               *((volatile unsigned int*)(0x4270A328UL))\r
+#define bFM3_MFS5_LIN_FBYTE_FD11               *((volatile unsigned int*)(0x4270A32CUL))\r
+#define bFM3_MFS5_LIN_FBYTE_FD12               *((volatile unsigned int*)(0x4270A330UL))\r
+#define bFM3_MFS5_LIN_FBYTE_FD13               *((volatile unsigned int*)(0x4270A334UL))\r
+#define bFM3_MFS5_LIN_FBYTE_FD14               *((volatile unsigned int*)(0x4270A338UL))\r
+#define bFM3_MFS5_LIN_FBYTE_FD15               *((volatile unsigned int*)(0x4270A33CUL))\r
+#define bFM3_MFS5_LIN_FBYTE1_FD0               *((volatile unsigned int*)(0x4270A300UL))\r
+#define bFM3_MFS5_LIN_FBYTE1_FD1               *((volatile unsigned int*)(0x4270A304UL))\r
+#define bFM3_MFS5_LIN_FBYTE1_FD2               *((volatile unsigned int*)(0x4270A308UL))\r
+#define bFM3_MFS5_LIN_FBYTE1_FD3               *((volatile unsigned int*)(0x4270A30CUL))\r
+#define bFM3_MFS5_LIN_FBYTE1_FD4               *((volatile unsigned int*)(0x4270A310UL))\r
+#define bFM3_MFS5_LIN_FBYTE1_FD5               *((volatile unsigned int*)(0x4270A314UL))\r
+#define bFM3_MFS5_LIN_FBYTE1_FD6               *((volatile unsigned int*)(0x4270A318UL))\r
+#define bFM3_MFS5_LIN_FBYTE1_FD7               *((volatile unsigned int*)(0x4270A31CUL))\r
+#define bFM3_MFS5_LIN_FBYTE2_FD8               *((volatile unsigned int*)(0x4270A320UL))\r
+#define bFM3_MFS5_LIN_FBYTE2_FD9               *((volatile unsigned int*)(0x4270A324UL))\r
+#define bFM3_MFS5_LIN_FBYTE2_FD10              *((volatile unsigned int*)(0x4270A328UL))\r
+#define bFM3_MFS5_LIN_FBYTE2_FD11              *((volatile unsigned int*)(0x4270A32CUL))\r
+#define bFM3_MFS5_LIN_FBYTE2_FD12              *((volatile unsigned int*)(0x4270A330UL))\r
+#define bFM3_MFS5_LIN_FBYTE2_FD13              *((volatile unsigned int*)(0x4270A334UL))\r
+#define bFM3_MFS5_LIN_FBYTE2_FD14              *((volatile unsigned int*)(0x4270A338UL))\r
+#define bFM3_MFS5_LIN_FBYTE2_FD15              *((volatile unsigned int*)(0x4270A33CUL))\r
+\r
+/* I2C channel 5 registers */\r
+#define bFM3_MFS5_I2C_SMR_ITST0                *((volatile unsigned int*)(0x4270A000UL))\r
+#define bFM3_MFS5_I2C_SMR_ITST1                *((volatile unsigned int*)(0x4270A004UL))\r
+#define bFM3_MFS5_I2C_SMR_TIE                  *((volatile unsigned int*)(0x4270A008UL))\r
+#define bFM3_MFS5_I2C_SMR_RIE                  *((volatile unsigned int*)(0x4270A00CUL))\r
+#define bFM3_MFS5_I2C_SMR_WUCR                 *((volatile unsigned int*)(0x4270A010UL))\r
+#define bFM3_MFS5_I2C_SMR_MD0                  *((volatile unsigned int*)(0x4270A014UL))\r
+#define bFM3_MFS5_I2C_SMR_MD1                  *((volatile unsigned int*)(0x4270A018UL))\r
+#define bFM3_MFS5_I2C_SMR_MD2                  *((volatile unsigned int*)(0x4270A01CUL))\r
+#define bFM3_MFS5_I2C_IBCR_INT                 *((volatile unsigned int*)(0x4270A020UL))\r
+#define bFM3_MFS5_I2C_IBCR_BER                 *((volatile unsigned int*)(0x4270A024UL))\r
+#define bFM3_MFS5_I2C_IBCR_INTE                *((volatile unsigned int*)(0x4270A028UL))\r
+#define bFM3_MFS5_I2C_IBCR_CNDE                *((volatile unsigned int*)(0x4270A02CUL))\r
+#define bFM3_MFS5_I2C_IBCR_WSEL                *((volatile unsigned int*)(0x4270A030UL))\r
+#define bFM3_MFS5_I2C_IBCR_ACKE                *((volatile unsigned int*)(0x4270A034UL))\r
+#define bFM3_MFS5_I2C_IBCR_ACT                 *((volatile unsigned int*)(0x4270A038UL))\r
+#define bFM3_MFS5_I2C_IBCR_SCC                 *((volatile unsigned int*)(0x4270A038UL))\r
+#define bFM3_MFS5_I2C_IBCR_MSS                 *((volatile unsigned int*)(0x4270A03CUL))\r
+#define bFM3_MFS5_I2C_IBSR_BB                  *((volatile unsigned int*)(0x4270A080UL))\r
+#define bFM3_MFS5_I2C_IBSR_SPC                 *((volatile unsigned int*)(0x4270A084UL))\r
+#define bFM3_MFS5_I2C_IBSR_RSC                 *((volatile unsigned int*)(0x4270A088UL))\r
+#define bFM3_MFS5_I2C_IBSR_AL                  *((volatile unsigned int*)(0x4270A08CUL))\r
+#define bFM3_MFS5_I2C_IBSR_TRX                 *((volatile unsigned int*)(0x4270A090UL))\r
+#define bFM3_MFS5_I2C_IBSR_RSA                 *((volatile unsigned int*)(0x4270A094UL))\r
+#define bFM3_MFS5_I2C_IBSR_RACK                *((volatile unsigned int*)(0x4270A098UL))\r
+#define bFM3_MFS5_I2C_IBSR_FBT                 *((volatile unsigned int*)(0x4270A09CUL))\r
+#define bFM3_MFS5_I2C_SSR_TBI                  *((volatile unsigned int*)(0x4270A0A0UL))\r
+#define bFM3_MFS5_I2C_SSR_TDRE                 *((volatile unsigned int*)(0x4270A0A4UL))\r
+#define bFM3_MFS5_I2C_SSR_RDRF                 *((volatile unsigned int*)(0x4270A0A8UL))\r
+#define bFM3_MFS5_I2C_SSR_ORE                  *((volatile unsigned int*)(0x4270A0ACUL))\r
+#define bFM3_MFS5_I2C_SSR_TBIE                 *((volatile unsigned int*)(0x4270A0B0UL))\r
+#define bFM3_MFS5_I2C_SSR_DMA                  *((volatile unsigned int*)(0x4270A0B4UL))\r
+#define bFM3_MFS5_I2C_SSR_TSET                 *((volatile unsigned int*)(0x4270A0B8UL))\r
+#define bFM3_MFS5_I2C_SSR_REC                  *((volatile unsigned int*)(0x4270A0BCUL))\r
+#define bFM3_MFS5_I2C_ISBA_SA0                 *((volatile unsigned int*)(0x4270A200UL))\r
+#define bFM3_MFS5_I2C_ISBA_SA1                 *((volatile unsigned int*)(0x4270A204UL))\r
+#define bFM3_MFS5_I2C_ISBA_SA2                 *((volatile unsigned int*)(0x4270A208UL))\r
+#define bFM3_MFS5_I2C_ISBA_SA3                 *((volatile unsigned int*)(0x4270A20CUL))\r
+#define bFM3_MFS5_I2C_ISBA_SA4                 *((volatile unsigned int*)(0x4270A210UL))\r
+#define bFM3_MFS5_I2C_ISBA_SA5                 *((volatile unsigned int*)(0x4270A214UL))\r
+#define bFM3_MFS5_I2C_ISBA_SA6                 *((volatile unsigned int*)(0x4270A218UL))\r
+#define bFM3_MFS5_I2C_ISBA_SAEN                *((volatile unsigned int*)(0x4270A21CUL))\r
+#define bFM3_MFS5_I2C_ISMK_SM0                 *((volatile unsigned int*)(0x4270A220UL))\r
+#define bFM3_MFS5_I2C_ISMK_SM1                 *((volatile unsigned int*)(0x4270A224UL))\r
+#define bFM3_MFS5_I2C_ISMK_SM2                 *((volatile unsigned int*)(0x4270A228UL))\r
+#define bFM3_MFS5_I2C_ISMK_SM3                 *((volatile unsigned int*)(0x4270A22CUL))\r
+#define bFM3_MFS5_I2C_ISMK_SM4                 *((volatile unsigned int*)(0x4270A230UL))\r
+#define bFM3_MFS5_I2C_ISMK_SM5                 *((volatile unsigned int*)(0x4270A234UL))\r
+#define bFM3_MFS5_I2C_ISMK_SM6                 *((volatile unsigned int*)(0x4270A238UL))\r
+#define bFM3_MFS5_I2C_ISMK_EN                  *((volatile unsigned int*)(0x4270A23CUL))\r
+#define bFM3_MFS5_I2C_FCR_FE1                  *((volatile unsigned int*)(0x4270A280UL))\r
+#define bFM3_MFS5_I2C_FCR_FE2                  *((volatile unsigned int*)(0x4270A284UL))\r
+#define bFM3_MFS5_I2C_FCR_FCL1                 *((volatile unsigned int*)(0x4270A288UL))\r
+#define bFM3_MFS5_I2C_FCR_FCL2                 *((volatile unsigned int*)(0x4270A28CUL))\r
+#define bFM3_MFS5_I2C_FCR_FSET                 *((volatile unsigned int*)(0x4270A290UL))\r
+#define bFM3_MFS5_I2C_FCR_FLD                  *((volatile unsigned int*)(0x4270A294UL))\r
+#define bFM3_MFS5_I2C_FCR_FLST                 *((volatile unsigned int*)(0x4270A298UL))\r
+#define bFM3_MFS5_I2C_FCR_FSEL                 *((volatile unsigned int*)(0x4270A2A0UL))\r
+#define bFM3_MFS5_I2C_FCR_FTIE                 *((volatile unsigned int*)(0x4270A2A4UL))\r
+#define bFM3_MFS5_I2C_FCR_FDRQ                 *((volatile unsigned int*)(0x4270A2A8UL))\r
+#define bFM3_MFS5_I2C_FCR_FRIE                 *((volatile unsigned int*)(0x4270A2ACUL))\r
+#define bFM3_MFS5_I2C_FCR_FLSTE                *((volatile unsigned int*)(0x4270A2B0UL))\r
+#define bFM3_MFS5_I2C_FCR_FTST0                *((volatile unsigned int*)(0x4270A2B8UL))\r
+#define bFM3_MFS5_I2C_FCR_FTST1                *((volatile unsigned int*)(0x4270A2BCUL))\r
+#define bFM3_MFS5_I2C_FCR0_FE1                 *((volatile unsigned int*)(0x4270A280UL))\r
+#define bFM3_MFS5_I2C_FCR0_FE2                 *((volatile unsigned int*)(0x4270A284UL))\r
+#define bFM3_MFS5_I2C_FCR0_FCL1                *((volatile unsigned int*)(0x4270A288UL))\r
+#define bFM3_MFS5_I2C_FCR0_FCL2                *((volatile unsigned int*)(0x4270A28CUL))\r
+#define bFM3_MFS5_I2C_FCR0_FSET                *((volatile unsigned int*)(0x4270A290UL))\r
+#define bFM3_MFS5_I2C_FCR0_FLD                 *((volatile unsigned int*)(0x4270A294UL))\r
+#define bFM3_MFS5_I2C_FCR0_FLST                *((volatile unsigned int*)(0x4270A298UL))\r
+#define bFM3_MFS5_I2C_FCR1_FSEL                *((volatile unsigned int*)(0x4270A2A0UL))\r
+#define bFM3_MFS5_I2C_FCR1_FTIE                *((volatile unsigned int*)(0x4270A2A4UL))\r
+#define bFM3_MFS5_I2C_FCR1_FDRQ                *((volatile unsigned int*)(0x4270A2A8UL))\r
+#define bFM3_MFS5_I2C_FCR1_FRIE                *((volatile unsigned int*)(0x4270A2ACUL))\r
+#define bFM3_MFS5_I2C_FCR1_FLSTE               *((volatile unsigned int*)(0x4270A2B0UL))\r
+#define bFM3_MFS5_I2C_FCR1_FTST0               *((volatile unsigned int*)(0x4270A2B8UL))\r
+#define bFM3_MFS5_I2C_FCR1_FTST1               *((volatile unsigned int*)(0x4270A2BCUL))\r
+#define bFM3_MFS5_I2C_FBYTE_FD0                *((volatile unsigned int*)(0x4270A300UL))\r
+#define bFM3_MFS5_I2C_FBYTE_FD1                *((volatile unsigned int*)(0x4270A304UL))\r
+#define bFM3_MFS5_I2C_FBYTE_FD2                *((volatile unsigned int*)(0x4270A308UL))\r
+#define bFM3_MFS5_I2C_FBYTE_FD3                *((volatile unsigned int*)(0x4270A30CUL))\r
+#define bFM3_MFS5_I2C_FBYTE_FD4                *((volatile unsigned int*)(0x4270A310UL))\r
+#define bFM3_MFS5_I2C_FBYTE_FD5                *((volatile unsigned int*)(0x4270A314UL))\r
+#define bFM3_MFS5_I2C_FBYTE_FD6                *((volatile unsigned int*)(0x4270A318UL))\r
+#define bFM3_MFS5_I2C_FBYTE_FD7                *((volatile unsigned int*)(0x4270A31CUL))\r
+#define bFM3_MFS5_I2C_FBYTE_FD8                *((volatile unsigned int*)(0x4270A320UL))\r
+#define bFM3_MFS5_I2C_FBYTE_FD9                *((volatile unsigned int*)(0x4270A324UL))\r
+#define bFM3_MFS5_I2C_FBYTE_FD10               *((volatile unsigned int*)(0x4270A328UL))\r
+#define bFM3_MFS5_I2C_FBYTE_FD11               *((volatile unsigned int*)(0x4270A32CUL))\r
+#define bFM3_MFS5_I2C_FBYTE_FD12               *((volatile unsigned int*)(0x4270A330UL))\r
+#define bFM3_MFS5_I2C_FBYTE_FD13               *((volatile unsigned int*)(0x4270A334UL))\r
+#define bFM3_MFS5_I2C_FBYTE_FD14               *((volatile unsigned int*)(0x4270A338UL))\r
+#define bFM3_MFS5_I2C_FBYTE_FD15               *((volatile unsigned int*)(0x4270A33CUL))\r
+#define bFM3_MFS5_I2C_FBYTE1_FD0               *((volatile unsigned int*)(0x4270A300UL))\r
+#define bFM3_MFS5_I2C_FBYTE1_FD1               *((volatile unsigned int*)(0x4270A304UL))\r
+#define bFM3_MFS5_I2C_FBYTE1_FD2               *((volatile unsigned int*)(0x4270A308UL))\r
+#define bFM3_MFS5_I2C_FBYTE1_FD3               *((volatile unsigned int*)(0x4270A30CUL))\r
+#define bFM3_MFS5_I2C_FBYTE1_FD4               *((volatile unsigned int*)(0x4270A310UL))\r
+#define bFM3_MFS5_I2C_FBYTE1_FD5               *((volatile unsigned int*)(0x4270A314UL))\r
+#define bFM3_MFS5_I2C_FBYTE1_FD6               *((volatile unsigned int*)(0x4270A318UL))\r
+#define bFM3_MFS5_I2C_FBYTE1_FD7               *((volatile unsigned int*)(0x4270A31CUL))\r
+#define bFM3_MFS5_I2C_FBYTE2_FD8               *((volatile unsigned int*)(0x4270A320UL))\r
+#define bFM3_MFS5_I2C_FBYTE2_FD9               *((volatile unsigned int*)(0x4270A324UL))\r
+#define bFM3_MFS5_I2C_FBYTE2_FD10              *((volatile unsigned int*)(0x4270A328UL))\r
+#define bFM3_MFS5_I2C_FBYTE2_FD11              *((volatile unsigned int*)(0x4270A32CUL))\r
+#define bFM3_MFS5_I2C_FBYTE2_FD12              *((volatile unsigned int*)(0x4270A330UL))\r
+#define bFM3_MFS5_I2C_FBYTE2_FD13              *((volatile unsigned int*)(0x4270A334UL))\r
+#define bFM3_MFS5_I2C_FBYTE2_FD14              *((volatile unsigned int*)(0x4270A338UL))\r
+#define bFM3_MFS5_I2C_FBYTE2_FD15              *((volatile unsigned int*)(0x4270A33CUL))\r
+\r
+/* UART asynchronous channel 6 registers */\r
+#define bFM3_MFS6_UART_SMR_SOE                 *((volatile unsigned int*)(0x4270C000UL))\r
+#define bFM3_MFS6_UART_SMR_BDS                 *((volatile unsigned int*)(0x4270C008UL))\r
+#define bFM3_MFS6_UART_SMR_SBL                 *((volatile unsigned int*)(0x4270C00CUL))\r
+#define bFM3_MFS6_UART_SMR_WUCR                *((volatile unsigned int*)(0x4270C010UL))\r
+#define bFM3_MFS6_UART_SMR_MD0                 *((volatile unsigned int*)(0x4270C014UL))\r
+#define bFM3_MFS6_UART_SMR_MD1                 *((volatile unsigned int*)(0x4270C018UL))\r
+#define bFM3_MFS6_UART_SMR_MD2                 *((volatile unsigned int*)(0x4270C01CUL))\r
+#define bFM3_MFS6_UART_SCR_TXE                 *((volatile unsigned int*)(0x4270C020UL))\r
+#define bFM3_MFS6_UART_SCR_RXE                 *((volatile unsigned int*)(0x4270C024UL))\r
+#define bFM3_MFS6_UART_SCR_TBIE                *((volatile unsigned int*)(0x4270C028UL))\r
+#define bFM3_MFS6_UART_SCR_TIE                 *((volatile unsigned int*)(0x4270C02CUL))\r
+#define bFM3_MFS6_UART_SCR_RIE                 *((volatile unsigned int*)(0x4270C030UL))\r
+#define bFM3_MFS6_UART_SCR_UPCL                *((volatile unsigned int*)(0x4270C03CUL))\r
+#define bFM3_MFS6_UART_ESCR_L0                 *((volatile unsigned int*)(0x4270C080UL))\r
+#define bFM3_MFS6_UART_ESCR_L1                 *((volatile unsigned int*)(0x4270C084UL))\r
+#define bFM3_MFS6_UART_ESCR_L2                 *((volatile unsigned int*)(0x4270C088UL))\r
+#define bFM3_MFS6_UART_ESCR_P                  *((volatile unsigned int*)(0x4270C08CUL))\r
+#define bFM3_MFS6_UART_ESCR_PEN                *((volatile unsigned int*)(0x4270C090UL))\r
+#define bFM3_MFS6_UART_ESCR_INV                *((volatile unsigned int*)(0x4270C094UL))\r
+#define bFM3_MFS6_UART_ESCR_ESBL               *((volatile unsigned int*)(0x4270C098UL))\r
+#define bFM3_MFS6_UART_ESCR_FLWEN              *((volatile unsigned int*)(0x4270C09CUL))\r
+#define bFM3_MFS6_UART_SSR_TBI                 *((volatile unsigned int*)(0x4270C0A0UL))\r
+#define bFM3_MFS6_UART_SSR_TDRE                *((volatile unsigned int*)(0x4270C0A4UL))\r
+#define bFM3_MFS6_UART_SSR_RDRF                *((volatile unsigned int*)(0x4270C0A8UL))\r
+#define bFM3_MFS6_UART_SSR_ORE                 *((volatile unsigned int*)(0x4270C0ACUL))\r
+#define bFM3_MFS6_UART_SSR_FRE                 *((volatile unsigned int*)(0x4270C0B0UL))\r
+#define bFM3_MFS6_UART_SSR_PE                  *((volatile unsigned int*)(0x4270C0B4UL))\r
+#define bFM3_MFS6_UART_SSR_REC                 *((volatile unsigned int*)(0x4270C0BCUL))\r
+#define bFM3_MFS6_UART_RDR_AD                  *((volatile unsigned int*)(0x4270C120UL))\r
+#define bFM3_MFS6_UART_TDR_AD                  *((volatile unsigned int*)(0x4270C120UL))\r
+#define bFM3_MFS6_UART_BGR_EXT                 *((volatile unsigned int*)(0x4270C1BCUL))\r
+#define bFM3_MFS6_UART_BGR1_EXT                *((volatile unsigned int*)(0x4270C1BCUL))\r
+#define bFM3_MFS6_UART_FCR_FE1                 *((volatile unsigned int*)(0x4270C280UL))\r
+#define bFM3_MFS6_UART_FCR_FE2                 *((volatile unsigned int*)(0x4270C284UL))\r
+#define bFM3_MFS6_UART_FCR_FCL1                *((volatile unsigned int*)(0x4270C288UL))\r
+#define bFM3_MFS6_UART_FCR_FCL2                *((volatile unsigned int*)(0x4270C28CUL))\r
+#define bFM3_MFS6_UART_FCR_FSET                *((volatile unsigned int*)(0x4270C290UL))\r
+#define bFM3_MFS6_UART_FCR_FLD                 *((volatile unsigned int*)(0x4270C294UL))\r
+#define bFM3_MFS6_UART_FCR_FLST                *((volatile unsigned int*)(0x4270C298UL))\r
+#define bFM3_MFS6_UART_FCR_FSEL                *((volatile unsigned int*)(0x4270C2A0UL))\r
+#define bFM3_MFS6_UART_FCR_FTIE                *((volatile unsigned int*)(0x4270C2A4UL))\r
+#define bFM3_MFS6_UART_FCR_FDRQ                *((volatile unsigned int*)(0x4270C2A8UL))\r
+#define bFM3_MFS6_UART_FCR_FRIE                *((volatile unsigned int*)(0x4270C2ACUL))\r
+#define bFM3_MFS6_UART_FCR_FLSTE               *((volatile unsigned int*)(0x4270C2B0UL))\r
+#define bFM3_MFS6_UART_FCR_FTST0               *((volatile unsigned int*)(0x4270C2B8UL))\r
+#define bFM3_MFS6_UART_FCR_FTST1               *((volatile unsigned int*)(0x4270C2BCUL))\r
+#define bFM3_MFS6_UART_FCR0_FE1                *((volatile unsigned int*)(0x4270C280UL))\r
+#define bFM3_MFS6_UART_FCR0_FE2                *((volatile unsigned int*)(0x4270C284UL))\r
+#define bFM3_MFS6_UART_FCR0_FCL1               *((volatile unsigned int*)(0x4270C288UL))\r
+#define bFM3_MFS6_UART_FCR0_FCL2               *((volatile unsigned int*)(0x4270C28CUL))\r
+#define bFM3_MFS6_UART_FCR0_FSET               *((volatile unsigned int*)(0x4270C290UL))\r
+#define bFM3_MFS6_UART_FCR0_FLD                *((volatile unsigned int*)(0x4270C294UL))\r
+#define bFM3_MFS6_UART_FCR0_FLST               *((volatile unsigned int*)(0x4270C298UL))\r
+#define bFM3_MFS6_UART_FCR1_FSEL               *((volatile unsigned int*)(0x4270C2A0UL))\r
+#define bFM3_MFS6_UART_FCR1_FTIE               *((volatile unsigned int*)(0x4270C2A4UL))\r
+#define bFM3_MFS6_UART_FCR1_FDRQ               *((volatile unsigned int*)(0x4270C2A8UL))\r
+#define bFM3_MFS6_UART_FCR1_FRIE               *((volatile unsigned int*)(0x4270C2ACUL))\r
+#define bFM3_MFS6_UART_FCR1_FLSTE              *((volatile unsigned int*)(0x4270C2B0UL))\r
+#define bFM3_MFS6_UART_FCR1_FTST0              *((volatile unsigned int*)(0x4270C2B8UL))\r
+#define bFM3_MFS6_UART_FCR1_FTST1              *((volatile unsigned int*)(0x4270C2BCUL))\r
+#define bFM3_MFS6_UART_FBYTE_FD0               *((volatile unsigned int*)(0x4270C300UL))\r
+#define bFM3_MFS6_UART_FBYTE_FD1               *((volatile unsigned int*)(0x4270C304UL))\r
+#define bFM3_MFS6_UART_FBYTE_FD2               *((volatile unsigned int*)(0x4270C308UL))\r
+#define bFM3_MFS6_UART_FBYTE_FD3               *((volatile unsigned int*)(0x4270C30CUL))\r
+#define bFM3_MFS6_UART_FBYTE_FD4               *((volatile unsigned int*)(0x4270C310UL))\r
+#define bFM3_MFS6_UART_FBYTE_FD5               *((volatile unsigned int*)(0x4270C314UL))\r
+#define bFM3_MFS6_UART_FBYTE_FD6               *((volatile unsigned int*)(0x4270C318UL))\r
+#define bFM3_MFS6_UART_FBYTE_FD7               *((volatile unsigned int*)(0x4270C31CUL))\r
+#define bFM3_MFS6_UART_FBYTE_FD8               *((volatile unsigned int*)(0x4270C320UL))\r
+#define bFM3_MFS6_UART_FBYTE_FD9               *((volatile unsigned int*)(0x4270C324UL))\r
+#define bFM3_MFS6_UART_FBYTE_FD10              *((volatile unsigned int*)(0x4270C328UL))\r
+#define bFM3_MFS6_UART_FBYTE_FD11              *((volatile unsigned int*)(0x4270C32CUL))\r
+#define bFM3_MFS6_UART_FBYTE_FD12              *((volatile unsigned int*)(0x4270C330UL))\r
+#define bFM3_MFS6_UART_FBYTE_FD13              *((volatile unsigned int*)(0x4270C334UL))\r
+#define bFM3_MFS6_UART_FBYTE_FD14              *((volatile unsigned int*)(0x4270C338UL))\r
+#define bFM3_MFS6_UART_FBYTE_FD15              *((volatile unsigned int*)(0x4270C33CUL))\r
+#define bFM3_MFS6_UART_FBYTE1_FD0              *((volatile unsigned int*)(0x4270C300UL))\r
+#define bFM3_MFS6_UART_FBYTE1_FD1              *((volatile unsigned int*)(0x4270C304UL))\r
+#define bFM3_MFS6_UART_FBYTE1_FD2              *((volatile unsigned int*)(0x4270C308UL))\r
+#define bFM3_MFS6_UART_FBYTE1_FD3              *((volatile unsigned int*)(0x4270C30CUL))\r
+#define bFM3_MFS6_UART_FBYTE1_FD4              *((volatile unsigned int*)(0x4270C310UL))\r
+#define bFM3_MFS6_UART_FBYTE1_FD5              *((volatile unsigned int*)(0x4270C314UL))\r
+#define bFM3_MFS6_UART_FBYTE1_FD6              *((volatile unsigned int*)(0x4270C318UL))\r
+#define bFM3_MFS6_UART_FBYTE1_FD7              *((volatile unsigned int*)(0x4270C31CUL))\r
+#define bFM3_MFS6_UART_FBYTE2_FD8              *((volatile unsigned int*)(0x4270C320UL))\r
+#define bFM3_MFS6_UART_FBYTE2_FD9              *((volatile unsigned int*)(0x4270C324UL))\r
+#define bFM3_MFS6_UART_FBYTE2_FD10             *((volatile unsigned int*)(0x4270C328UL))\r
+#define bFM3_MFS6_UART_FBYTE2_FD11             *((volatile unsigned int*)(0x4270C32CUL))\r
+#define bFM3_MFS6_UART_FBYTE2_FD12             *((volatile unsigned int*)(0x4270C330UL))\r
+#define bFM3_MFS6_UART_FBYTE2_FD13             *((volatile unsigned int*)(0x4270C334UL))\r
+#define bFM3_MFS6_UART_FBYTE2_FD14             *((volatile unsigned int*)(0x4270C338UL))\r
+#define bFM3_MFS6_UART_FBYTE2_FD15             *((volatile unsigned int*)(0x4270C33CUL))\r
+\r
+/* UART synchronous channel 6 registers */\r
+#define bFM3_MFS6_CSIO_SMR_SOE                 *((volatile unsigned int*)(0x4270C000UL))\r
+#define bFM3_MFS6_CSIO_SMR_SCKE                *((volatile unsigned int*)(0x4270C004UL))\r
+#define bFM3_MFS6_CSIO_SMR_BDS                 *((volatile unsigned int*)(0x4270C008UL))\r
+#define bFM3_MFS6_CSIO_SMR_SCINV               *((volatile unsigned int*)(0x4270C00CUL))\r
+#define bFM3_MFS6_CSIO_SMR_WUCR                *((volatile unsigned int*)(0x4270C010UL))\r
+#define bFM3_MFS6_CSIO_SMR_MD0                 *((volatile unsigned int*)(0x4270C014UL))\r
+#define bFM3_MFS6_CSIO_SMR_MD1                 *((volatile unsigned int*)(0x4270C018UL))\r
+#define bFM3_MFS6_CSIO_SMR_MD2                 *((volatile unsigned int*)(0x4270C01CUL))\r
+#define bFM3_MFS6_CSIO_SCR_TXE                 *((volatile unsigned int*)(0x4270C020UL))\r
+#define bFM3_MFS6_CSIO_SCR_RXE                 *((volatile unsigned int*)(0x4270C024UL))\r
+#define bFM3_MFS6_CSIO_SCR_TBIE                *((volatile unsigned int*)(0x4270C028UL))\r
+#define bFM3_MFS6_CSIO_SCR_TIE                 *((volatile unsigned int*)(0x4270C02CUL))\r
+#define bFM3_MFS6_CSIO_SCR_RIE                 *((volatile unsigned int*)(0x4270C030UL))\r
+#define bFM3_MFS6_CSIO_SCR_SPI                 *((volatile unsigned int*)(0x4270C034UL))\r
+#define bFM3_MFS6_CSIO_SCR_MS                  *((volatile unsigned int*)(0x4270C038UL))\r
+#define bFM3_MFS6_CSIO_SCR_UPCL                *((volatile unsigned int*)(0x4270C03CUL))\r
+#define bFM3_MFS6_CSIO_ESCR_L0                 *((volatile unsigned int*)(0x4270C080UL))\r
+#define bFM3_MFS6_CSIO_ESCR_L1                 *((volatile unsigned int*)(0x4270C084UL))\r
+#define bFM3_MFS6_CSIO_ESCR_L2                 *((volatile unsigned int*)(0x4270C088UL))\r
+#define bFM3_MFS6_CSIO_ESCR_WT0                *((volatile unsigned int*)(0x4270C08CUL))\r
+#define bFM3_MFS6_CSIO_ESCR_WT1                *((volatile unsigned int*)(0x4270C090UL))\r
+#define bFM3_MFS6_CSIO_ESCR_SOP                *((volatile unsigned int*)(0x4270C09CUL))\r
+#define bFM3_MFS6_CSIO_SSR_TBI                 *((volatile unsigned int*)(0x4270C0A0UL))\r
+#define bFM3_MFS6_CSIO_SSR_TDRE                *((volatile unsigned int*)(0x4270C0A4UL))\r
+#define bFM3_MFS6_CSIO_SSR_RDRF                *((volatile unsigned int*)(0x4270C0A8UL))\r
+#define bFM3_MFS6_CSIO_SSR_ORE                 *((volatile unsigned int*)(0x4270C0ACUL))\r
+#define bFM3_MFS6_CSIO_SSR_REC                 *((volatile unsigned int*)(0x4270C0BCUL))\r
+#define bFM3_MFS6_CSIO_FCR_FE1                 *((volatile unsigned int*)(0x4270C280UL))\r
+#define bFM3_MFS6_CSIO_FCR_FE2                 *((volatile unsigned int*)(0x4270C284UL))\r
+#define bFM3_MFS6_CSIO_FCR_FCL1                *((volatile unsigned int*)(0x4270C288UL))\r
+#define bFM3_MFS6_CSIO_FCR_FCL2                *((volatile unsigned int*)(0x4270C28CUL))\r
+#define bFM3_MFS6_CSIO_FCR_FSET                *((volatile unsigned int*)(0x4270C290UL))\r
+#define bFM3_MFS6_CSIO_FCR_FLD                 *((volatile unsigned int*)(0x4270C294UL))\r
+#define bFM3_MFS6_CSIO_FCR_FLST                *((volatile unsigned int*)(0x4270C298UL))\r
+#define bFM3_MFS6_CSIO_FCR_FSEL                *((volatile unsigned int*)(0x4270C2A0UL))\r
+#define bFM3_MFS6_CSIO_FCR_FTIE                *((volatile unsigned int*)(0x4270C2A4UL))\r
+#define bFM3_MFS6_CSIO_FCR_FDRQ                *((volatile unsigned int*)(0x4270C2A8UL))\r
+#define bFM3_MFS6_CSIO_FCR_FRIE                *((volatile unsigned int*)(0x4270C2ACUL))\r
+#define bFM3_MFS6_CSIO_FCR_FLSTE               *((volatile unsigned int*)(0x4270C2B0UL))\r
+#define bFM3_MFS6_CSIO_FCR_FTST0               *((volatile unsigned int*)(0x4270C2B8UL))\r
+#define bFM3_MFS6_CSIO_FCR_FTST1               *((volatile unsigned int*)(0x4270C2BCUL))\r
+#define bFM3_MFS6_CSIO_FCR0_FE1                *((volatile unsigned int*)(0x4270C280UL))\r
+#define bFM3_MFS6_CSIO_FCR0_FE2                *((volatile unsigned int*)(0x4270C284UL))\r
+#define bFM3_MFS6_CSIO_FCR0_FCL1               *((volatile unsigned int*)(0x4270C288UL))\r
+#define bFM3_MFS6_CSIO_FCR0_FCL2               *((volatile unsigned int*)(0x4270C28CUL))\r
+#define bFM3_MFS6_CSIO_FCR0_FSET               *((volatile unsigned int*)(0x4270C290UL))\r
+#define bFM3_MFS6_CSIO_FCR0_FLD                *((volatile unsigned int*)(0x4270C294UL))\r
+#define bFM3_MFS6_CSIO_FCR0_FLST               *((volatile unsigned int*)(0x4270C298UL))\r
+#define bFM3_MFS6_CSIO_FCR1_FSEL               *((volatile unsigned int*)(0x4270C2A0UL))\r
+#define bFM3_MFS6_CSIO_FCR1_FTIE               *((volatile unsigned int*)(0x4270C2A4UL))\r
+#define bFM3_MFS6_CSIO_FCR1_FDRQ               *((volatile unsigned int*)(0x4270C2A8UL))\r
+#define bFM3_MFS6_CSIO_FCR1_FRIE               *((volatile unsigned int*)(0x4270C2ACUL))\r
+#define bFM3_MFS6_CSIO_FCR1_FLSTE              *((volatile unsigned int*)(0x4270C2B0UL))\r
+#define bFM3_MFS6_CSIO_FCR1_FTST0              *((volatile unsigned int*)(0x4270C2B8UL))\r
+#define bFM3_MFS6_CSIO_FCR1_FTST1              *((volatile unsigned int*)(0x4270C2BCUL))\r
+#define bFM3_MFS6_CSIO_FBYTE_FD0               *((volatile unsigned int*)(0x4270C300UL))\r
+#define bFM3_MFS6_CSIO_FBYTE_FD1               *((volatile unsigned int*)(0x4270C304UL))\r
+#define bFM3_MFS6_CSIO_FBYTE_FD2               *((volatile unsigned int*)(0x4270C308UL))\r
+#define bFM3_MFS6_CSIO_FBYTE_FD3               *((volatile unsigned int*)(0x4270C30CUL))\r
+#define bFM3_MFS6_CSIO_FBYTE_FD4               *((volatile unsigned int*)(0x4270C310UL))\r
+#define bFM3_MFS6_CSIO_FBYTE_FD5               *((volatile unsigned int*)(0x4270C314UL))\r
+#define bFM3_MFS6_CSIO_FBYTE_FD6               *((volatile unsigned int*)(0x4270C318UL))\r
+#define bFM3_MFS6_CSIO_FBYTE_FD7               *((volatile unsigned int*)(0x4270C31CUL))\r
+#define bFM3_MFS6_CSIO_FBYTE_FD8               *((volatile unsigned int*)(0x4270C320UL))\r
+#define bFM3_MFS6_CSIO_FBYTE_FD9               *((volatile unsigned int*)(0x4270C324UL))\r
+#define bFM3_MFS6_CSIO_FBYTE_FD10              *((volatile unsigned int*)(0x4270C328UL))\r
+#define bFM3_MFS6_CSIO_FBYTE_FD11              *((volatile unsigned int*)(0x4270C32CUL))\r
+#define bFM3_MFS6_CSIO_FBYTE_FD12              *((volatile unsigned int*)(0x4270C330UL))\r
+#define bFM3_MFS6_CSIO_FBYTE_FD13              *((volatile unsigned int*)(0x4270C334UL))\r
+#define bFM3_MFS6_CSIO_FBYTE_FD14              *((volatile unsigned int*)(0x4270C338UL))\r
+#define bFM3_MFS6_CSIO_FBYTE_FD15              *((volatile unsigned int*)(0x4270C33CUL))\r
+#define bFM3_MFS6_CSIO_FBYTE1_FD0              *((volatile unsigned int*)(0x4270C300UL))\r
+#define bFM3_MFS6_CSIO_FBYTE1_FD1              *((volatile unsigned int*)(0x4270C304UL))\r
+#define bFM3_MFS6_CSIO_FBYTE1_FD2              *((volatile unsigned int*)(0x4270C308UL))\r
+#define bFM3_MFS6_CSIO_FBYTE1_FD3              *((volatile unsigned int*)(0x4270C30CUL))\r
+#define bFM3_MFS6_CSIO_FBYTE1_FD4              *((volatile unsigned int*)(0x4270C310UL))\r
+#define bFM3_MFS6_CSIO_FBYTE1_FD5              *((volatile unsigned int*)(0x4270C314UL))\r
+#define bFM3_MFS6_CSIO_FBYTE1_FD6              *((volatile unsigned int*)(0x4270C318UL))\r
+#define bFM3_MFS6_CSIO_FBYTE1_FD7              *((volatile unsigned int*)(0x4270C31CUL))\r
+#define bFM3_MFS6_CSIO_FBYTE2_FD8              *((volatile unsigned int*)(0x4270C320UL))\r
+#define bFM3_MFS6_CSIO_FBYTE2_FD9              *((volatile unsigned int*)(0x4270C324UL))\r
+#define bFM3_MFS6_CSIO_FBYTE2_FD10             *((volatile unsigned int*)(0x4270C328UL))\r
+#define bFM3_MFS6_CSIO_FBYTE2_FD11             *((volatile unsigned int*)(0x4270C32CUL))\r
+#define bFM3_MFS6_CSIO_FBYTE2_FD12             *((volatile unsigned int*)(0x4270C330UL))\r
+#define bFM3_MFS6_CSIO_FBYTE2_FD13             *((volatile unsigned int*)(0x4270C334UL))\r
+#define bFM3_MFS6_CSIO_FBYTE2_FD14             *((volatile unsigned int*)(0x4270C338UL))\r
+#define bFM3_MFS6_CSIO_FBYTE2_FD15             *((volatile unsigned int*)(0x4270C33CUL))\r
+\r
+/* UART LIN channel 6 registers */\r
+#define bFM3_MFS6_LIN_SMR_SOE                  *((volatile unsigned int*)(0x4270C000UL))\r
+#define bFM3_MFS6_LIN_SMR_SBL                  *((volatile unsigned int*)(0x4270C00CUL))\r
+#define bFM3_MFS6_LIN_SMR_WUCR                 *((volatile unsigned int*)(0x4270C010UL))\r
+#define bFM3_MFS6_LIN_SMR_MD0                  *((volatile unsigned int*)(0x4270C014UL))\r
+#define bFM3_MFS6_LIN_SMR_MD1                  *((volatile unsigned int*)(0x4270C018UL))\r
+#define bFM3_MFS6_LIN_SMR_MD2                  *((volatile unsigned int*)(0x4270C01CUL))\r
+#define bFM3_MFS6_LIN_SCR_TXE                  *((volatile unsigned int*)(0x4270C020UL))\r
+#define bFM3_MFS6_LIN_SCR_RXE                  *((volatile unsigned int*)(0x4270C024UL))\r
+#define bFM3_MFS6_LIN_SCR_TBIE                 *((volatile unsigned int*)(0x4270C028UL))\r
+#define bFM3_MFS6_LIN_SCR_TIE                  *((volatile unsigned int*)(0x4270C02CUL))\r
+#define bFM3_MFS6_LIN_SCR_RIE                  *((volatile unsigned int*)(0x4270C030UL))\r
+#define bFM3_MFS6_LIN_SCR_LBR                  *((volatile unsigned int*)(0x4270C034UL))\r
+#define bFM3_MFS6_LIN_SCR_MS                   *((volatile unsigned int*)(0x4270C038UL))\r
+#define bFM3_MFS6_LIN_SCR_UPCL                 *((volatile unsigned int*)(0x4270C03CUL))\r
+#define bFM3_MFS6_LIN_ESCR_DEL0                *((volatile unsigned int*)(0x4270C080UL))\r
+#define bFM3_MFS6_LIN_ESCR_DEL1                *((volatile unsigned int*)(0x4270C084UL))\r
+#define bFM3_MFS6_LIN_ESCR_LBL0                *((volatile unsigned int*)(0x4270C088UL))\r
+#define bFM3_MFS6_LIN_ESCR_LBL1                *((volatile unsigned int*)(0x4270C08CUL))\r
+#define bFM3_MFS6_LIN_ESCR_LBIE                *((volatile unsigned int*)(0x4270C090UL))\r
+#define bFM3_MFS6_LIN_ESCR_ESBL                *((volatile unsigned int*)(0x4270C098UL))\r
+#define bFM3_MFS6_LIN_SSR_TBI                  *((volatile unsigned int*)(0x4270C0A0UL))\r
+#define bFM3_MFS6_LIN_SSR_TDRE                 *((volatile unsigned int*)(0x4270C0A4UL))\r
+#define bFM3_MFS6_LIN_SSR_RDRF                 *((volatile unsigned int*)(0x4270C0A8UL))\r
+#define bFM3_MFS6_LIN_SSR_ORE                  *((volatile unsigned int*)(0x4270C0ACUL))\r
+#define bFM3_MFS6_LIN_SSR_FRE                  *((volatile unsigned int*)(0x4270C0B0UL))\r
+#define bFM3_MFS6_LIN_SSR_LBD                  *((volatile unsigned int*)(0x4270C0B4UL))\r
+#define bFM3_MFS6_LIN_SSR_REC                  *((volatile unsigned int*)(0x4270C0BCUL))\r
+#define bFM3_MFS6_LIN_BGR_EXT                  *((volatile unsigned int*)(0x4270C1BCUL))\r
+#define bFM3_MFS6_LIN_BGR1_EXT                 *((volatile unsigned int*)(0x4270C1BCUL))\r
+#define bFM3_MFS6_LIN_FCR_FE1                  *((volatile unsigned int*)(0x4270C280UL))\r
+#define bFM3_MFS6_LIN_FCR_FE2                  *((volatile unsigned int*)(0x4270C284UL))\r
+#define bFM3_MFS6_LIN_FCR_FCL1                 *((volatile unsigned int*)(0x4270C288UL))\r
+#define bFM3_MFS6_LIN_FCR_FCL2                 *((volatile unsigned int*)(0x4270C28CUL))\r
+#define bFM3_MFS6_LIN_FCR_FSET                 *((volatile unsigned int*)(0x4270C290UL))\r
+#define bFM3_MFS6_LIN_FCR_FLD                  *((volatile unsigned int*)(0x4270C294UL))\r
+#define bFM3_MFS6_LIN_FCR_FLST                 *((volatile unsigned int*)(0x4270C298UL))\r
+#define bFM3_MFS6_LIN_FCR_FSEL                 *((volatile unsigned int*)(0x4270C2A0UL))\r
+#define bFM3_MFS6_LIN_FCR_FTIE                 *((volatile unsigned int*)(0x4270C2A4UL))\r
+#define bFM3_MFS6_LIN_FCR_FDRQ                 *((volatile unsigned int*)(0x4270C2A8UL))\r
+#define bFM3_MFS6_LIN_FCR_FRIE                 *((volatile unsigned int*)(0x4270C2ACUL))\r
+#define bFM3_MFS6_LIN_FCR_FLSTE                *((volatile unsigned int*)(0x4270C2B0UL))\r
+#define bFM3_MFS6_LIN_FCR_FTST0                *((volatile unsigned int*)(0x4270C2B8UL))\r
+#define bFM3_MFS6_LIN_FCR_FTST1                *((volatile unsigned int*)(0x4270C2BCUL))\r
+#define bFM3_MFS6_LIN_FCR0_FE1                 *((volatile unsigned int*)(0x4270C280UL))\r
+#define bFM3_MFS6_LIN_FCR0_FE2                 *((volatile unsigned int*)(0x4270C284UL))\r
+#define bFM3_MFS6_LIN_FCR0_FCL1                *((volatile unsigned int*)(0x4270C288UL))\r
+#define bFM3_MFS6_LIN_FCR0_FCL2                *((volatile unsigned int*)(0x4270C28CUL))\r
+#define bFM3_MFS6_LIN_FCR0_FSET                *((volatile unsigned int*)(0x4270C290UL))\r
+#define bFM3_MFS6_LIN_FCR0_FLD                 *((volatile unsigned int*)(0x4270C294UL))\r
+#define bFM3_MFS6_LIN_FCR0_FLST                *((volatile unsigned int*)(0x4270C298UL))\r
+#define bFM3_MFS6_LIN_FCR1_FSEL                *((volatile unsigned int*)(0x4270C2A0UL))\r
+#define bFM3_MFS6_LIN_FCR1_FTIE                *((volatile unsigned int*)(0x4270C2A4UL))\r
+#define bFM3_MFS6_LIN_FCR1_FDRQ                *((volatile unsigned int*)(0x4270C2A8UL))\r
+#define bFM3_MFS6_LIN_FCR1_FRIE                *((volatile unsigned int*)(0x4270C2ACUL))\r
+#define bFM3_MFS6_LIN_FCR1_FLSTE               *((volatile unsigned int*)(0x4270C2B0UL))\r
+#define bFM3_MFS6_LIN_FCR1_FTST0               *((volatile unsigned int*)(0x4270C2B8UL))\r
+#define bFM3_MFS6_LIN_FCR1_FTST1               *((volatile unsigned int*)(0x4270C2BCUL))\r
+#define bFM3_MFS6_LIN_FBYTE_FD0                *((volatile unsigned int*)(0x4270C300UL))\r
+#define bFM3_MFS6_LIN_FBYTE_FD1                *((volatile unsigned int*)(0x4270C304UL))\r
+#define bFM3_MFS6_LIN_FBYTE_FD2                *((volatile unsigned int*)(0x4270C308UL))\r
+#define bFM3_MFS6_LIN_FBYTE_FD3                *((volatile unsigned int*)(0x4270C30CUL))\r
+#define bFM3_MFS6_LIN_FBYTE_FD4                *((volatile unsigned int*)(0x4270C310UL))\r
+#define bFM3_MFS6_LIN_FBYTE_FD5                *((volatile unsigned int*)(0x4270C314UL))\r
+#define bFM3_MFS6_LIN_FBYTE_FD6                *((volatile unsigned int*)(0x4270C318UL))\r
+#define bFM3_MFS6_LIN_FBYTE_FD7                *((volatile unsigned int*)(0x4270C31CUL))\r
+#define bFM3_MFS6_LIN_FBYTE_FD8                *((volatile unsigned int*)(0x4270C320UL))\r
+#define bFM3_MFS6_LIN_FBYTE_FD9                *((volatile unsigned int*)(0x4270C324UL))\r
+#define bFM3_MFS6_LIN_FBYTE_FD10               *((volatile unsigned int*)(0x4270C328UL))\r
+#define bFM3_MFS6_LIN_FBYTE_FD11               *((volatile unsigned int*)(0x4270C32CUL))\r
+#define bFM3_MFS6_LIN_FBYTE_FD12               *((volatile unsigned int*)(0x4270C330UL))\r
+#define bFM3_MFS6_LIN_FBYTE_FD13               *((volatile unsigned int*)(0x4270C334UL))\r
+#define bFM3_MFS6_LIN_FBYTE_FD14               *((volatile unsigned int*)(0x4270C338UL))\r
+#define bFM3_MFS6_LIN_FBYTE_FD15               *((volatile unsigned int*)(0x4270C33CUL))\r
+#define bFM3_MFS6_LIN_FBYTE1_FD0               *((volatile unsigned int*)(0x4270C300UL))\r
+#define bFM3_MFS6_LIN_FBYTE1_FD1               *((volatile unsigned int*)(0x4270C304UL))\r
+#define bFM3_MFS6_LIN_FBYTE1_FD2               *((volatile unsigned int*)(0x4270C308UL))\r
+#define bFM3_MFS6_LIN_FBYTE1_FD3               *((volatile unsigned int*)(0x4270C30CUL))\r
+#define bFM3_MFS6_LIN_FBYTE1_FD4               *((volatile unsigned int*)(0x4270C310UL))\r
+#define bFM3_MFS6_LIN_FBYTE1_FD5               *((volatile unsigned int*)(0x4270C314UL))\r
+#define bFM3_MFS6_LIN_FBYTE1_FD6               *((volatile unsigned int*)(0x4270C318UL))\r
+#define bFM3_MFS6_LIN_FBYTE1_FD7               *((volatile unsigned int*)(0x4270C31CUL))\r
+#define bFM3_MFS6_LIN_FBYTE2_FD8               *((volatile unsigned int*)(0x4270C320UL))\r
+#define bFM3_MFS6_LIN_FBYTE2_FD9               *((volatile unsigned int*)(0x4270C324UL))\r
+#define bFM3_MFS6_LIN_FBYTE2_FD10              *((volatile unsigned int*)(0x4270C328UL))\r
+#define bFM3_MFS6_LIN_FBYTE2_FD11              *((volatile unsigned int*)(0x4270C32CUL))\r
+#define bFM3_MFS6_LIN_FBYTE2_FD12              *((volatile unsigned int*)(0x4270C330UL))\r
+#define bFM3_MFS6_LIN_FBYTE2_FD13              *((volatile unsigned int*)(0x4270C334UL))\r
+#define bFM3_MFS6_LIN_FBYTE2_FD14              *((volatile unsigned int*)(0x4270C338UL))\r
+#define bFM3_MFS6_LIN_FBYTE2_FD15              *((volatile unsigned int*)(0x4270C33CUL))\r
+\r
+/* I2C channel 6 registers */\r
+#define bFM3_MFS6_I2C_SMR_ITST0                *((volatile unsigned int*)(0x4270C000UL))\r
+#define bFM3_MFS6_I2C_SMR_ITST1                *((volatile unsigned int*)(0x4270C004UL))\r
+#define bFM3_MFS6_I2C_SMR_TIE                  *((volatile unsigned int*)(0x4270C008UL))\r
+#define bFM3_MFS6_I2C_SMR_RIE                  *((volatile unsigned int*)(0x4270C00CUL))\r
+#define bFM3_MFS6_I2C_SMR_WUCR                 *((volatile unsigned int*)(0x4270C010UL))\r
+#define bFM3_MFS6_I2C_SMR_MD0                  *((volatile unsigned int*)(0x4270C014UL))\r
+#define bFM3_MFS6_I2C_SMR_MD1                  *((volatile unsigned int*)(0x4270C018UL))\r
+#define bFM3_MFS6_I2C_SMR_MD2                  *((volatile unsigned int*)(0x4270C01CUL))\r
+#define bFM3_MFS6_I2C_IBCR_INT                 *((volatile unsigned int*)(0x4270C020UL))\r
+#define bFM3_MFS6_I2C_IBCR_BER                 *((volatile unsigned int*)(0x4270C024UL))\r
+#define bFM3_MFS6_I2C_IBCR_INTE                *((volatile unsigned int*)(0x4270C028UL))\r
+#define bFM3_MFS6_I2C_IBCR_CNDE                *((volatile unsigned int*)(0x4270C02CUL))\r
+#define bFM3_MFS6_I2C_IBCR_WSEL                *((volatile unsigned int*)(0x4270C030UL))\r
+#define bFM3_MFS6_I2C_IBCR_ACKE                *((volatile unsigned int*)(0x4270C034UL))\r
+#define bFM3_MFS6_I2C_IBCR_ACT                 *((volatile unsigned int*)(0x4270C038UL))\r
+#define bFM3_MFS6_I2C_IBCR_SCC                 *((volatile unsigned int*)(0x4270C038UL))\r
+#define bFM3_MFS6_I2C_IBCR_MSS                 *((volatile unsigned int*)(0x4270C03CUL))\r
+#define bFM3_MFS6_I2C_IBSR_BB                  *((volatile unsigned int*)(0x4270C080UL))\r
+#define bFM3_MFS6_I2C_IBSR_SPC                 *((volatile unsigned int*)(0x4270C084UL))\r
+#define bFM3_MFS6_I2C_IBSR_RSC                 *((volatile unsigned int*)(0x4270C088UL))\r
+#define bFM3_MFS6_I2C_IBSR_AL                  *((volatile unsigned int*)(0x4270C08CUL))\r
+#define bFM3_MFS6_I2C_IBSR_TRX                 *((volatile unsigned int*)(0x4270C090UL))\r
+#define bFM3_MFS6_I2C_IBSR_RSA                 *((volatile unsigned int*)(0x4270C094UL))\r
+#define bFM3_MFS6_I2C_IBSR_RACK                *((volatile unsigned int*)(0x4270C098UL))\r
+#define bFM3_MFS6_I2C_IBSR_FBT                 *((volatile unsigned int*)(0x4270C09CUL))\r
+#define bFM3_MFS6_I2C_SSR_TBI                  *((volatile unsigned int*)(0x4270C0A0UL))\r
+#define bFM3_MFS6_I2C_SSR_TDRE                 *((volatile unsigned int*)(0x4270C0A4UL))\r
+#define bFM3_MFS6_I2C_SSR_RDRF                 *((volatile unsigned int*)(0x4270C0A8UL))\r
+#define bFM3_MFS6_I2C_SSR_ORE                  *((volatile unsigned int*)(0x4270C0ACUL))\r
+#define bFM3_MFS6_I2C_SSR_TBIE                 *((volatile unsigned int*)(0x4270C0B0UL))\r
+#define bFM3_MFS6_I2C_SSR_DMA                  *((volatile unsigned int*)(0x4270C0B4UL))\r
+#define bFM3_MFS6_I2C_SSR_TSET                 *((volatile unsigned int*)(0x4270C0B8UL))\r
+#define bFM3_MFS6_I2C_SSR_REC                  *((volatile unsigned int*)(0x4270C0BCUL))\r
+#define bFM3_MFS6_I2C_ISBA_SA0                 *((volatile unsigned int*)(0x4270C200UL))\r
+#define bFM3_MFS6_I2C_ISBA_SA1                 *((volatile unsigned int*)(0x4270C204UL))\r
+#define bFM3_MFS6_I2C_ISBA_SA2                 *((volatile unsigned int*)(0x4270C208UL))\r
+#define bFM3_MFS6_I2C_ISBA_SA3                 *((volatile unsigned int*)(0x4270C20CUL))\r
+#define bFM3_MFS6_I2C_ISBA_SA4                 *((volatile unsigned int*)(0x4270C210UL))\r
+#define bFM3_MFS6_I2C_ISBA_SA5                 *((volatile unsigned int*)(0x4270C214UL))\r
+#define bFM3_MFS6_I2C_ISBA_SA6                 *((volatile unsigned int*)(0x4270C218UL))\r
+#define bFM3_MFS6_I2C_ISBA_SAEN                *((volatile unsigned int*)(0x4270C21CUL))\r
+#define bFM3_MFS6_I2C_ISMK_SM0                 *((volatile unsigned int*)(0x4270C220UL))\r
+#define bFM3_MFS6_I2C_ISMK_SM1                 *((volatile unsigned int*)(0x4270C224UL))\r
+#define bFM3_MFS6_I2C_ISMK_SM2                 *((volatile unsigned int*)(0x4270C228UL))\r
+#define bFM3_MFS6_I2C_ISMK_SM3                 *((volatile unsigned int*)(0x4270C22CUL))\r
+#define bFM3_MFS6_I2C_ISMK_SM4                 *((volatile unsigned int*)(0x4270C230UL))\r
+#define bFM3_MFS6_I2C_ISMK_SM5                 *((volatile unsigned int*)(0x4270C234UL))\r
+#define bFM3_MFS6_I2C_ISMK_SM6                 *((volatile unsigned int*)(0x4270C238UL))\r
+#define bFM3_MFS6_I2C_ISMK_EN                  *((volatile unsigned int*)(0x4270C23CUL))\r
+#define bFM3_MFS6_I2C_FCR_FE1                  *((volatile unsigned int*)(0x4270C280UL))\r
+#define bFM3_MFS6_I2C_FCR_FE2                  *((volatile unsigned int*)(0x4270C284UL))\r
+#define bFM3_MFS6_I2C_FCR_FCL1                 *((volatile unsigned int*)(0x4270C288UL))\r
+#define bFM3_MFS6_I2C_FCR_FCL2                 *((volatile unsigned int*)(0x4270C28CUL))\r
+#define bFM3_MFS6_I2C_FCR_FSET                 *((volatile unsigned int*)(0x4270C290UL))\r
+#define bFM3_MFS6_I2C_FCR_FLD                  *((volatile unsigned int*)(0x4270C294UL))\r
+#define bFM3_MFS6_I2C_FCR_FLST                 *((volatile unsigned int*)(0x4270C298UL))\r
+#define bFM3_MFS6_I2C_FCR_FSEL                 *((volatile unsigned int*)(0x4270C2A0UL))\r
+#define bFM3_MFS6_I2C_FCR_FTIE                 *((volatile unsigned int*)(0x4270C2A4UL))\r
+#define bFM3_MFS6_I2C_FCR_FDRQ                 *((volatile unsigned int*)(0x4270C2A8UL))\r
+#define bFM3_MFS6_I2C_FCR_FRIE                 *((volatile unsigned int*)(0x4270C2ACUL))\r
+#define bFM3_MFS6_I2C_FCR_FLSTE                *((volatile unsigned int*)(0x4270C2B0UL))\r
+#define bFM3_MFS6_I2C_FCR_FTST0                *((volatile unsigned int*)(0x4270C2B8UL))\r
+#define bFM3_MFS6_I2C_FCR_FTST1                *((volatile unsigned int*)(0x4270C2BCUL))\r
+#define bFM3_MFS6_I2C_FCR0_FE1                 *((volatile unsigned int*)(0x4270C280UL))\r
+#define bFM3_MFS6_I2C_FCR0_FE2                 *((volatile unsigned int*)(0x4270C284UL))\r
+#define bFM3_MFS6_I2C_FCR0_FCL1                *((volatile unsigned int*)(0x4270C288UL))\r
+#define bFM3_MFS6_I2C_FCR0_FCL2                *((volatile unsigned int*)(0x4270C28CUL))\r
+#define bFM3_MFS6_I2C_FCR0_FSET                *((volatile unsigned int*)(0x4270C290UL))\r
+#define bFM3_MFS6_I2C_FCR0_FLD                 *((volatile unsigned int*)(0x4270C294UL))\r
+#define bFM3_MFS6_I2C_FCR0_FLST                *((volatile unsigned int*)(0x4270C298UL))\r
+#define bFM3_MFS6_I2C_FCR1_FSEL                *((volatile unsigned int*)(0x4270C2A0UL))\r
+#define bFM3_MFS6_I2C_FCR1_FTIE                *((volatile unsigned int*)(0x4270C2A4UL))\r
+#define bFM3_MFS6_I2C_FCR1_FDRQ                *((volatile unsigned int*)(0x4270C2A8UL))\r
+#define bFM3_MFS6_I2C_FCR1_FRIE                *((volatile unsigned int*)(0x4270C2ACUL))\r
+#define bFM3_MFS6_I2C_FCR1_FLSTE               *((volatile unsigned int*)(0x4270C2B0UL))\r
+#define bFM3_MFS6_I2C_FCR1_FTST0               *((volatile unsigned int*)(0x4270C2B8UL))\r
+#define bFM3_MFS6_I2C_FCR1_FTST1               *((volatile unsigned int*)(0x4270C2BCUL))\r
+#define bFM3_MFS6_I2C_FBYTE_FD0                *((volatile unsigned int*)(0x4270C300UL))\r
+#define bFM3_MFS6_I2C_FBYTE_FD1                *((volatile unsigned int*)(0x4270C304UL))\r
+#define bFM3_MFS6_I2C_FBYTE_FD2                *((volatile unsigned int*)(0x4270C308UL))\r
+#define bFM3_MFS6_I2C_FBYTE_FD3                *((volatile unsigned int*)(0x4270C30CUL))\r
+#define bFM3_MFS6_I2C_FBYTE_FD4                *((volatile unsigned int*)(0x4270C310UL))\r
+#define bFM3_MFS6_I2C_FBYTE_FD5                *((volatile unsigned int*)(0x4270C314UL))\r
+#define bFM3_MFS6_I2C_FBYTE_FD6                *((volatile unsigned int*)(0x4270C318UL))\r
+#define bFM3_MFS6_I2C_FBYTE_FD7                *((volatile unsigned int*)(0x4270C31CUL))\r
+#define bFM3_MFS6_I2C_FBYTE_FD8                *((volatile unsigned int*)(0x4270C320UL))\r
+#define bFM3_MFS6_I2C_FBYTE_FD9                *((volatile unsigned int*)(0x4270C324UL))\r
+#define bFM3_MFS6_I2C_FBYTE_FD10               *((volatile unsigned int*)(0x4270C328UL))\r
+#define bFM3_MFS6_I2C_FBYTE_FD11               *((volatile unsigned int*)(0x4270C32CUL))\r
+#define bFM3_MFS6_I2C_FBYTE_FD12               *((volatile unsigned int*)(0x4270C330UL))\r
+#define bFM3_MFS6_I2C_FBYTE_FD13               *((volatile unsigned int*)(0x4270C334UL))\r
+#define bFM3_MFS6_I2C_FBYTE_FD14               *((volatile unsigned int*)(0x4270C338UL))\r
+#define bFM3_MFS6_I2C_FBYTE_FD15               *((volatile unsigned int*)(0x4270C33CUL))\r
+#define bFM3_MFS6_I2C_FBYTE1_FD0               *((volatile unsigned int*)(0x4270C300UL))\r
+#define bFM3_MFS6_I2C_FBYTE1_FD1               *((volatile unsigned int*)(0x4270C304UL))\r
+#define bFM3_MFS6_I2C_FBYTE1_FD2               *((volatile unsigned int*)(0x4270C308UL))\r
+#define bFM3_MFS6_I2C_FBYTE1_FD3               *((volatile unsigned int*)(0x4270C30CUL))\r
+#define bFM3_MFS6_I2C_FBYTE1_FD4               *((volatile unsigned int*)(0x4270C310UL))\r
+#define bFM3_MFS6_I2C_FBYTE1_FD5               *((volatile unsigned int*)(0x4270C314UL))\r
+#define bFM3_MFS6_I2C_FBYTE1_FD6               *((volatile unsigned int*)(0x4270C318UL))\r
+#define bFM3_MFS6_I2C_FBYTE1_FD7               *((volatile unsigned int*)(0x4270C31CUL))\r
+#define bFM3_MFS6_I2C_FBYTE2_FD8               *((volatile unsigned int*)(0x4270C320UL))\r
+#define bFM3_MFS6_I2C_FBYTE2_FD9               *((volatile unsigned int*)(0x4270C324UL))\r
+#define bFM3_MFS6_I2C_FBYTE2_FD10              *((volatile unsigned int*)(0x4270C328UL))\r
+#define bFM3_MFS6_I2C_FBYTE2_FD11              *((volatile unsigned int*)(0x4270C32CUL))\r
+#define bFM3_MFS6_I2C_FBYTE2_FD12              *((volatile unsigned int*)(0x4270C330UL))\r
+#define bFM3_MFS6_I2C_FBYTE2_FD13              *((volatile unsigned int*)(0x4270C334UL))\r
+#define bFM3_MFS6_I2C_FBYTE2_FD14              *((volatile unsigned int*)(0x4270C338UL))\r
+#define bFM3_MFS6_I2C_FBYTE2_FD15              *((volatile unsigned int*)(0x4270C33CUL))\r
+\r
+/* UART asynchronous channel 7 registers */\r
+#define bFM3_MFS7_UART_SMR_SOE                 *((volatile unsigned int*)(0x4270E000UL))\r
+#define bFM3_MFS7_UART_SMR_BDS                 *((volatile unsigned int*)(0x4270E008UL))\r
+#define bFM3_MFS7_UART_SMR_SBL                 *((volatile unsigned int*)(0x4270E00CUL))\r
+#define bFM3_MFS7_UART_SMR_WUCR                *((volatile unsigned int*)(0x4270E010UL))\r
+#define bFM3_MFS7_UART_SMR_MD0                 *((volatile unsigned int*)(0x4270E014UL))\r
+#define bFM3_MFS7_UART_SMR_MD1                 *((volatile unsigned int*)(0x4270E018UL))\r
+#define bFM3_MFS7_UART_SMR_MD2                 *((volatile unsigned int*)(0x4270E01CUL))\r
+#define bFM3_MFS7_UART_SCR_TXE                 *((volatile unsigned int*)(0x4270E020UL))\r
+#define bFM3_MFS7_UART_SCR_RXE                 *((volatile unsigned int*)(0x4270E024UL))\r
+#define bFM3_MFS7_UART_SCR_TBIE                *((volatile unsigned int*)(0x4270E028UL))\r
+#define bFM3_MFS7_UART_SCR_TIE                 *((volatile unsigned int*)(0x4270E02CUL))\r
+#define bFM3_MFS7_UART_SCR_RIE                 *((volatile unsigned int*)(0x4270E030UL))\r
+#define bFM3_MFS7_UART_SCR_UPCL                *((volatile unsigned int*)(0x4270E03CUL))\r
+#define bFM3_MFS7_UART_ESCR_L0                 *((volatile unsigned int*)(0x4270E080UL))\r
+#define bFM3_MFS7_UART_ESCR_L1                 *((volatile unsigned int*)(0x4270E084UL))\r
+#define bFM3_MFS7_UART_ESCR_L2                 *((volatile unsigned int*)(0x4270E088UL))\r
+#define bFM3_MFS7_UART_ESCR_P                  *((volatile unsigned int*)(0x4270E08CUL))\r
+#define bFM3_MFS7_UART_ESCR_PEN                *((volatile unsigned int*)(0x4270E090UL))\r
+#define bFM3_MFS7_UART_ESCR_INV                *((volatile unsigned int*)(0x4270E094UL))\r
+#define bFM3_MFS7_UART_ESCR_ESBL               *((volatile unsigned int*)(0x4270E098UL))\r
+#define bFM3_MFS7_UART_ESCR_FLWEN              *((volatile unsigned int*)(0x4270E09CUL))\r
+#define bFM3_MFS7_UART_SSR_TBI                 *((volatile unsigned int*)(0x4270E0A0UL))\r
+#define bFM3_MFS7_UART_SSR_TDRE                *((volatile unsigned int*)(0x4270E0A4UL))\r
+#define bFM3_MFS7_UART_SSR_RDRF                *((volatile unsigned int*)(0x4270E0A8UL))\r
+#define bFM3_MFS7_UART_SSR_ORE                 *((volatile unsigned int*)(0x4270E0ACUL))\r
+#define bFM3_MFS7_UART_SSR_FRE                 *((volatile unsigned int*)(0x4270E0B0UL))\r
+#define bFM3_MFS7_UART_SSR_PE                  *((volatile unsigned int*)(0x4270E0B4UL))\r
+#define bFM3_MFS7_UART_SSR_REC                 *((volatile unsigned int*)(0x4270E0BCUL))\r
+#define bFM3_MFS7_UART_RDR_AD                  *((volatile unsigned int*)(0x4270E120UL))\r
+#define bFM3_MFS7_UART_TDR_AD                  *((volatile unsigned int*)(0x4270E120UL))\r
+#define bFM3_MFS7_UART_BGR_EXT                 *((volatile unsigned int*)(0x4270E1BCUL))\r
+#define bFM3_MFS7_UART_BGR1_EXT                *((volatile unsigned int*)(0x4270E1BCUL))\r
+#define bFM3_MFS7_UART_FCR_FE1                 *((volatile unsigned int*)(0x4270E280UL))\r
+#define bFM3_MFS7_UART_FCR_FE2                 *((volatile unsigned int*)(0x4270E284UL))\r
+#define bFM3_MFS7_UART_FCR_FCL1                *((volatile unsigned int*)(0x4270E288UL))\r
+#define bFM3_MFS7_UART_FCR_FCL2                *((volatile unsigned int*)(0x4270E28CUL))\r
+#define bFM3_MFS7_UART_FCR_FSET                *((volatile unsigned int*)(0x4270E290UL))\r
+#define bFM3_MFS7_UART_FCR_FLD                 *((volatile unsigned int*)(0x4270E294UL))\r
+#define bFM3_MFS7_UART_FCR_FLST                *((volatile unsigned int*)(0x4270E298UL))\r
+#define bFM3_MFS7_UART_FCR_FSEL                *((volatile unsigned int*)(0x4270E2A0UL))\r
+#define bFM3_MFS7_UART_FCR_FTIE                *((volatile unsigned int*)(0x4270E2A4UL))\r
+#define bFM3_MFS7_UART_FCR_FDRQ                *((volatile unsigned int*)(0x4270E2A8UL))\r
+#define bFM3_MFS7_UART_FCR_FRIE                *((volatile unsigned int*)(0x4270E2ACUL))\r
+#define bFM3_MFS7_UART_FCR_FLSTE               *((volatile unsigned int*)(0x4270E2B0UL))\r
+#define bFM3_MFS7_UART_FCR_FTST0               *((volatile unsigned int*)(0x4270E2B8UL))\r
+#define bFM3_MFS7_UART_FCR_FTST1               *((volatile unsigned int*)(0x4270E2BCUL))\r
+#define bFM3_MFS7_UART_FCR0_FE1                *((volatile unsigned int*)(0x4270E280UL))\r
+#define bFM3_MFS7_UART_FCR0_FE2                *((volatile unsigned int*)(0x4270E284UL))\r
+#define bFM3_MFS7_UART_FCR0_FCL1               *((volatile unsigned int*)(0x4270E288UL))\r
+#define bFM3_MFS7_UART_FCR0_FCL2               *((volatile unsigned int*)(0x4270E28CUL))\r
+#define bFM3_MFS7_UART_FCR0_FSET               *((volatile unsigned int*)(0x4270E290UL))\r
+#define bFM3_MFS7_UART_FCR0_FLD                *((volatile unsigned int*)(0x4270E294UL))\r
+#define bFM3_MFS7_UART_FCR0_FLST               *((volatile unsigned int*)(0x4270E298UL))\r
+#define bFM3_MFS7_UART_FCR1_FSEL               *((volatile unsigned int*)(0x4270E2A0UL))\r
+#define bFM3_MFS7_UART_FCR1_FTIE               *((volatile unsigned int*)(0x4270E2A4UL))\r
+#define bFM3_MFS7_UART_FCR1_FDRQ               *((volatile unsigned int*)(0x4270E2A8UL))\r
+#define bFM3_MFS7_UART_FCR1_FRIE               *((volatile unsigned int*)(0x4270E2ACUL))\r
+#define bFM3_MFS7_UART_FCR1_FLSTE              *((volatile unsigned int*)(0x4270E2B0UL))\r
+#define bFM3_MFS7_UART_FCR1_FTST0              *((volatile unsigned int*)(0x4270E2B8UL))\r
+#define bFM3_MFS7_UART_FCR1_FTST1              *((volatile unsigned int*)(0x4270E2BCUL))\r
+#define bFM3_MFS7_UART_FBYTE_FD0               *((volatile unsigned int*)(0x4270E300UL))\r
+#define bFM3_MFS7_UART_FBYTE_FD1               *((volatile unsigned int*)(0x4270E304UL))\r
+#define bFM3_MFS7_UART_FBYTE_FD2               *((volatile unsigned int*)(0x4270E308UL))\r
+#define bFM3_MFS7_UART_FBYTE_FD3               *((volatile unsigned int*)(0x4270E30CUL))\r
+#define bFM3_MFS7_UART_FBYTE_FD4               *((volatile unsigned int*)(0x4270E310UL))\r
+#define bFM3_MFS7_UART_FBYTE_FD5               *((volatile unsigned int*)(0x4270E314UL))\r
+#define bFM3_MFS7_UART_FBYTE_FD6               *((volatile unsigned int*)(0x4270E318UL))\r
+#define bFM3_MFS7_UART_FBYTE_FD7               *((volatile unsigned int*)(0x4270E31CUL))\r
+#define bFM3_MFS7_UART_FBYTE_FD8               *((volatile unsigned int*)(0x4270E320UL))\r
+#define bFM3_MFS7_UART_FBYTE_FD9               *((volatile unsigned int*)(0x4270E324UL))\r
+#define bFM3_MFS7_UART_FBYTE_FD10              *((volatile unsigned int*)(0x4270E328UL))\r
+#define bFM3_MFS7_UART_FBYTE_FD11              *((volatile unsigned int*)(0x4270E32CUL))\r
+#define bFM3_MFS7_UART_FBYTE_FD12              *((volatile unsigned int*)(0x4270E330UL))\r
+#define bFM3_MFS7_UART_FBYTE_FD13              *((volatile unsigned int*)(0x4270E334UL))\r
+#define bFM3_MFS7_UART_FBYTE_FD14              *((volatile unsigned int*)(0x4270E338UL))\r
+#define bFM3_MFS7_UART_FBYTE_FD15              *((volatile unsigned int*)(0x4270E33CUL))\r
+#define bFM3_MFS7_UART_FBYTE1_FD0              *((volatile unsigned int*)(0x4270E300UL))\r
+#define bFM3_MFS7_UART_FBYTE1_FD1              *((volatile unsigned int*)(0x4270E304UL))\r
+#define bFM3_MFS7_UART_FBYTE1_FD2              *((volatile unsigned int*)(0x4270E308UL))\r
+#define bFM3_MFS7_UART_FBYTE1_FD3              *((volatile unsigned int*)(0x4270E30CUL))\r
+#define bFM3_MFS7_UART_FBYTE1_FD4              *((volatile unsigned int*)(0x4270E310UL))\r
+#define bFM3_MFS7_UART_FBYTE1_FD5              *((volatile unsigned int*)(0x4270E314UL))\r
+#define bFM3_MFS7_UART_FBYTE1_FD6              *((volatile unsigned int*)(0x4270E318UL))\r
+#define bFM3_MFS7_UART_FBYTE1_FD7              *((volatile unsigned int*)(0x4270E31CUL))\r
+#define bFM3_MFS7_UART_FBYTE2_FD8              *((volatile unsigned int*)(0x4270E320UL))\r
+#define bFM3_MFS7_UART_FBYTE2_FD9              *((volatile unsigned int*)(0x4270E324UL))\r
+#define bFM3_MFS7_UART_FBYTE2_FD10             *((volatile unsigned int*)(0x4270E328UL))\r
+#define bFM3_MFS7_UART_FBYTE2_FD11             *((volatile unsigned int*)(0x4270E32CUL))\r
+#define bFM3_MFS7_UART_FBYTE2_FD12             *((volatile unsigned int*)(0x4270E330UL))\r
+#define bFM3_MFS7_UART_FBYTE2_FD13             *((volatile unsigned int*)(0x4270E334UL))\r
+#define bFM3_MFS7_UART_FBYTE2_FD14             *((volatile unsigned int*)(0x4270E338UL))\r
+#define bFM3_MFS7_UART_FBYTE2_FD15             *((volatile unsigned int*)(0x4270E33CUL))\r
+\r
+/* UART synchronous channel 7 registers */\r
+#define bFM3_MFS7_CSIO_SMR_SOE                 *((volatile unsigned int*)(0x4270E000UL))\r
+#define bFM3_MFS7_CSIO_SMR_SCKE                *((volatile unsigned int*)(0x4270E004UL))\r
+#define bFM3_MFS7_CSIO_SMR_BDS                 *((volatile unsigned int*)(0x4270E008UL))\r
+#define bFM3_MFS7_CSIO_SMR_SCINV               *((volatile unsigned int*)(0x4270E00CUL))\r
+#define bFM3_MFS7_CSIO_SMR_WUCR                *((volatile unsigned int*)(0x4270E010UL))\r
+#define bFM3_MFS7_CSIO_SMR_MD0                 *((volatile unsigned int*)(0x4270E014UL))\r
+#define bFM3_MFS7_CSIO_SMR_MD1                 *((volatile unsigned int*)(0x4270E018UL))\r
+#define bFM3_MFS7_CSIO_SMR_MD2                 *((volatile unsigned int*)(0x4270E01CUL))\r
+#define bFM3_MFS7_CSIO_SCR_TXE                 *((volatile unsigned int*)(0x4270E020UL))\r
+#define bFM3_MFS7_CSIO_SCR_RXE                 *((volatile unsigned int*)(0x4270E024UL))\r
+#define bFM3_MFS7_CSIO_SCR_TBIE                *((volatile unsigned int*)(0x4270E028UL))\r
+#define bFM3_MFS7_CSIO_SCR_TIE                 *((volatile unsigned int*)(0x4270E02CUL))\r
+#define bFM3_MFS7_CSIO_SCR_RIE                 *((volatile unsigned int*)(0x4270E030UL))\r
+#define bFM3_MFS7_CSIO_SCR_SPI                 *((volatile unsigned int*)(0x4270E034UL))\r
+#define bFM3_MFS7_CSIO_SCR_MS                  *((volatile unsigned int*)(0x4270E038UL))\r
+#define bFM3_MFS7_CSIO_SCR_UPCL                *((volatile unsigned int*)(0x4270E03CUL))\r
+#define bFM3_MFS7_CSIO_ESCR_L0                 *((volatile unsigned int*)(0x4270E080UL))\r
+#define bFM3_MFS7_CSIO_ESCR_L1                 *((volatile unsigned int*)(0x4270E084UL))\r
+#define bFM3_MFS7_CSIO_ESCR_L2                 *((volatile unsigned int*)(0x4270E088UL))\r
+#define bFM3_MFS7_CSIO_ESCR_WT0                *((volatile unsigned int*)(0x4270E08CUL))\r
+#define bFM3_MFS7_CSIO_ESCR_WT1                *((volatile unsigned int*)(0x4270E090UL))\r
+#define bFM3_MFS7_CSIO_ESCR_SOP                *((volatile unsigned int*)(0x4270E09CUL))\r
+#define bFM3_MFS7_CSIO_SSR_TBI                 *((volatile unsigned int*)(0x4270E0A0UL))\r
+#define bFM3_MFS7_CSIO_SSR_TDRE                *((volatile unsigned int*)(0x4270E0A4UL))\r
+#define bFM3_MFS7_CSIO_SSR_RDRF                *((volatile unsigned int*)(0x4270E0A8UL))\r
+#define bFM3_MFS7_CSIO_SSR_ORE                 *((volatile unsigned int*)(0x4270E0ACUL))\r
+#define bFM3_MFS7_CSIO_SSR_REC                 *((volatile unsigned int*)(0x4270E0BCUL))\r
+#define bFM3_MFS7_CSIO_FCR_FE1                 *((volatile unsigned int*)(0x4270E280UL))\r
+#define bFM3_MFS7_CSIO_FCR_FE2                 *((volatile unsigned int*)(0x4270E284UL))\r
+#define bFM3_MFS7_CSIO_FCR_FCL1                *((volatile unsigned int*)(0x4270E288UL))\r
+#define bFM3_MFS7_CSIO_FCR_FCL2                *((volatile unsigned int*)(0x4270E28CUL))\r
+#define bFM3_MFS7_CSIO_FCR_FSET                *((volatile unsigned int*)(0x4270E290UL))\r
+#define bFM3_MFS7_CSIO_FCR_FLD                 *((volatile unsigned int*)(0x4270E294UL))\r
+#define bFM3_MFS7_CSIO_FCR_FLST                *((volatile unsigned int*)(0x4270E298UL))\r
+#define bFM3_MFS7_CSIO_FCR_FSEL                *((volatile unsigned int*)(0x4270E2A0UL))\r
+#define bFM3_MFS7_CSIO_FCR_FTIE                *((volatile unsigned int*)(0x4270E2A4UL))\r
+#define bFM3_MFS7_CSIO_FCR_FDRQ                *((volatile unsigned int*)(0x4270E2A8UL))\r
+#define bFM3_MFS7_CSIO_FCR_FRIE                *((volatile unsigned int*)(0x4270E2ACUL))\r
+#define bFM3_MFS7_CSIO_FCR_FLSTE               *((volatile unsigned int*)(0x4270E2B0UL))\r
+#define bFM3_MFS7_CSIO_FCR_FTST0               *((volatile unsigned int*)(0x4270E2B8UL))\r
+#define bFM3_MFS7_CSIO_FCR_FTST1               *((volatile unsigned int*)(0x4270E2BCUL))\r
+#define bFM3_MFS7_CSIO_FCR0_FE1                *((volatile unsigned int*)(0x4270E280UL))\r
+#define bFM3_MFS7_CSIO_FCR0_FE2                *((volatile unsigned int*)(0x4270E284UL))\r
+#define bFM3_MFS7_CSIO_FCR0_FCL1               *((volatile unsigned int*)(0x4270E288UL))\r
+#define bFM3_MFS7_CSIO_FCR0_FCL2               *((volatile unsigned int*)(0x4270E28CUL))\r
+#define bFM3_MFS7_CSIO_FCR0_FSET               *((volatile unsigned int*)(0x4270E290UL))\r
+#define bFM3_MFS7_CSIO_FCR0_FLD                *((volatile unsigned int*)(0x4270E294UL))\r
+#define bFM3_MFS7_CSIO_FCR0_FLST               *((volatile unsigned int*)(0x4270E298UL))\r
+#define bFM3_MFS7_CSIO_FCR1_FSEL               *((volatile unsigned int*)(0x4270E2A0UL))\r
+#define bFM3_MFS7_CSIO_FCR1_FTIE               *((volatile unsigned int*)(0x4270E2A4UL))\r
+#define bFM3_MFS7_CSIO_FCR1_FDRQ               *((volatile unsigned int*)(0x4270E2A8UL))\r
+#define bFM3_MFS7_CSIO_FCR1_FRIE               *((volatile unsigned int*)(0x4270E2ACUL))\r
+#define bFM3_MFS7_CSIO_FCR1_FLSTE              *((volatile unsigned int*)(0x4270E2B0UL))\r
+#define bFM3_MFS7_CSIO_FCR1_FTST0              *((volatile unsigned int*)(0x4270E2B8UL))\r
+#define bFM3_MFS7_CSIO_FCR1_FTST1              *((volatile unsigned int*)(0x4270E2BCUL))\r
+#define bFM3_MFS7_CSIO_FBYTE_FD0               *((volatile unsigned int*)(0x4270E300UL))\r
+#define bFM3_MFS7_CSIO_FBYTE_FD1               *((volatile unsigned int*)(0x4270E304UL))\r
+#define bFM3_MFS7_CSIO_FBYTE_FD2               *((volatile unsigned int*)(0x4270E308UL))\r
+#define bFM3_MFS7_CSIO_FBYTE_FD3               *((volatile unsigned int*)(0x4270E30CUL))\r
+#define bFM3_MFS7_CSIO_FBYTE_FD4               *((volatile unsigned int*)(0x4270E310UL))\r
+#define bFM3_MFS7_CSIO_FBYTE_FD5               *((volatile unsigned int*)(0x4270E314UL))\r
+#define bFM3_MFS7_CSIO_FBYTE_FD6               *((volatile unsigned int*)(0x4270E318UL))\r
+#define bFM3_MFS7_CSIO_FBYTE_FD7               *((volatile unsigned int*)(0x4270E31CUL))\r
+#define bFM3_MFS7_CSIO_FBYTE_FD8               *((volatile unsigned int*)(0x4270E320UL))\r
+#define bFM3_MFS7_CSIO_FBYTE_FD9               *((volatile unsigned int*)(0x4270E324UL))\r
+#define bFM3_MFS7_CSIO_FBYTE_FD10              *((volatile unsigned int*)(0x4270E328UL))\r
+#define bFM3_MFS7_CSIO_FBYTE_FD11              *((volatile unsigned int*)(0x4270E32CUL))\r
+#define bFM3_MFS7_CSIO_FBYTE_FD12              *((volatile unsigned int*)(0x4270E330UL))\r
+#define bFM3_MFS7_CSIO_FBYTE_FD13              *((volatile unsigned int*)(0x4270E334UL))\r
+#define bFM3_MFS7_CSIO_FBYTE_FD14              *((volatile unsigned int*)(0x4270E338UL))\r
+#define bFM3_MFS7_CSIO_FBYTE_FD15              *((volatile unsigned int*)(0x4270E33CUL))\r
+#define bFM3_MFS7_CSIO_FBYTE1_FD0              *((volatile unsigned int*)(0x4270E300UL))\r
+#define bFM3_MFS7_CSIO_FBYTE1_FD1              *((volatile unsigned int*)(0x4270E304UL))\r
+#define bFM3_MFS7_CSIO_FBYTE1_FD2              *((volatile unsigned int*)(0x4270E308UL))\r
+#define bFM3_MFS7_CSIO_FBYTE1_FD3              *((volatile unsigned int*)(0x4270E30CUL))\r
+#define bFM3_MFS7_CSIO_FBYTE1_FD4              *((volatile unsigned int*)(0x4270E310UL))\r
+#define bFM3_MFS7_CSIO_FBYTE1_FD5              *((volatile unsigned int*)(0x4270E314UL))\r
+#define bFM3_MFS7_CSIO_FBYTE1_FD6              *((volatile unsigned int*)(0x4270E318UL))\r
+#define bFM3_MFS7_CSIO_FBYTE1_FD7              *((volatile unsigned int*)(0x4270E31CUL))\r
+#define bFM3_MFS7_CSIO_FBYTE2_FD8              *((volatile unsigned int*)(0x4270E320UL))\r
+#define bFM3_MFS7_CSIO_FBYTE2_FD9              *((volatile unsigned int*)(0x4270E324UL))\r
+#define bFM3_MFS7_CSIO_FBYTE2_FD10             *((volatile unsigned int*)(0x4270E328UL))\r
+#define bFM3_MFS7_CSIO_FBYTE2_FD11             *((volatile unsigned int*)(0x4270E32CUL))\r
+#define bFM3_MFS7_CSIO_FBYTE2_FD12             *((volatile unsigned int*)(0x4270E330UL))\r
+#define bFM3_MFS7_CSIO_FBYTE2_FD13             *((volatile unsigned int*)(0x4270E334UL))\r
+#define bFM3_MFS7_CSIO_FBYTE2_FD14             *((volatile unsigned int*)(0x4270E338UL))\r
+#define bFM3_MFS7_CSIO_FBYTE2_FD15             *((volatile unsigned int*)(0x4270E33CUL))\r
+\r
+/* UART LIN channel 7 registers */\r
+#define bFM3_MFS7_LIN_SMR_SOE                  *((volatile unsigned int*)(0x4270E000UL))\r
+#define bFM3_MFS7_LIN_SMR_SBL                  *((volatile unsigned int*)(0x4270E00CUL))\r
+#define bFM3_MFS7_LIN_SMR_WUCR                 *((volatile unsigned int*)(0x4270E010UL))\r
+#define bFM3_MFS7_LIN_SMR_MD0                  *((volatile unsigned int*)(0x4270E014UL))\r
+#define bFM3_MFS7_LIN_SMR_MD1                  *((volatile unsigned int*)(0x4270E018UL))\r
+#define bFM3_MFS7_LIN_SMR_MD2                  *((volatile unsigned int*)(0x4270E01CUL))\r
+#define bFM3_MFS7_LIN_SCR_TXE                  *((volatile unsigned int*)(0x4270E020UL))\r
+#define bFM3_MFS7_LIN_SCR_RXE                  *((volatile unsigned int*)(0x4270E024UL))\r
+#define bFM3_MFS7_LIN_SCR_TBIE                 *((volatile unsigned int*)(0x4270E028UL))\r
+#define bFM3_MFS7_LIN_SCR_TIE                  *((volatile unsigned int*)(0x4270E02CUL))\r
+#define bFM3_MFS7_LIN_SCR_RIE                  *((volatile unsigned int*)(0x4270E030UL))\r
+#define bFM3_MFS7_LIN_SCR_LBR                  *((volatile unsigned int*)(0x4270E034UL))\r
+#define bFM3_MFS7_LIN_SCR_MS                   *((volatile unsigned int*)(0x4270E038UL))\r
+#define bFM3_MFS7_LIN_SCR_UPCL                 *((volatile unsigned int*)(0x4270E03CUL))\r
+#define bFM3_MFS7_LIN_ESCR_DEL0                *((volatile unsigned int*)(0x4270E080UL))\r
+#define bFM3_MFS7_LIN_ESCR_DEL1                *((volatile unsigned int*)(0x4270E084UL))\r
+#define bFM3_MFS7_LIN_ESCR_LBL0                *((volatile unsigned int*)(0x4270E088UL))\r
+#define bFM3_MFS7_LIN_ESCR_LBL1                *((volatile unsigned int*)(0x4270E08CUL))\r
+#define bFM3_MFS7_LIN_ESCR_LBIE                *((volatile unsigned int*)(0x4270E090UL))\r
+#define bFM3_MFS7_LIN_ESCR_ESBL                *((volatile unsigned int*)(0x4270E098UL))\r
+#define bFM3_MFS7_LIN_SSR_TBI                  *((volatile unsigned int*)(0x4270E0A0UL))\r
+#define bFM3_MFS7_LIN_SSR_TDRE                 *((volatile unsigned int*)(0x4270E0A4UL))\r
+#define bFM3_MFS7_LIN_SSR_RDRF                 *((volatile unsigned int*)(0x4270E0A8UL))\r
+#define bFM3_MFS7_LIN_SSR_ORE                  *((volatile unsigned int*)(0x4270E0ACUL))\r
+#define bFM3_MFS7_LIN_SSR_FRE                  *((volatile unsigned int*)(0x4270E0B0UL))\r
+#define bFM3_MFS7_LIN_SSR_LBD                  *((volatile unsigned int*)(0x4270E0B4UL))\r
+#define bFM3_MFS7_LIN_SSR_REC                  *((volatile unsigned int*)(0x4270E0BCUL))\r
+#define bFM3_MFS7_LIN_BGR_EXT                  *((volatile unsigned int*)(0x4270E1BCUL))\r
+#define bFM3_MFS7_LIN_BGR1_EXT                 *((volatile unsigned int*)(0x4270E1BCUL))\r
+#define bFM3_MFS7_LIN_FCR_FE1                  *((volatile unsigned int*)(0x4270E280UL))\r
+#define bFM3_MFS7_LIN_FCR_FE2                  *((volatile unsigned int*)(0x4270E284UL))\r
+#define bFM3_MFS7_LIN_FCR_FCL1                 *((volatile unsigned int*)(0x4270E288UL))\r
+#define bFM3_MFS7_LIN_FCR_FCL2                 *((volatile unsigned int*)(0x4270E28CUL))\r
+#define bFM3_MFS7_LIN_FCR_FSET                 *((volatile unsigned int*)(0x4270E290UL))\r
+#define bFM3_MFS7_LIN_FCR_FLD                  *((volatile unsigned int*)(0x4270E294UL))\r
+#define bFM3_MFS7_LIN_FCR_FLST                 *((volatile unsigned int*)(0x4270E298UL))\r
+#define bFM3_MFS7_LIN_FCR_FSEL                 *((volatile unsigned int*)(0x4270E2A0UL))\r
+#define bFM3_MFS7_LIN_FCR_FTIE                 *((volatile unsigned int*)(0x4270E2A4UL))\r
+#define bFM3_MFS7_LIN_FCR_FDRQ                 *((volatile unsigned int*)(0x4270E2A8UL))\r
+#define bFM3_MFS7_LIN_FCR_FRIE                 *((volatile unsigned int*)(0x4270E2ACUL))\r
+#define bFM3_MFS7_LIN_FCR_FLSTE                *((volatile unsigned int*)(0x4270E2B0UL))\r
+#define bFM3_MFS7_LIN_FCR_FTST0                *((volatile unsigned int*)(0x4270E2B8UL))\r
+#define bFM3_MFS7_LIN_FCR_FTST1                *((volatile unsigned int*)(0x4270E2BCUL))\r
+#define bFM3_MFS7_LIN_FCR0_FE1                 *((volatile unsigned int*)(0x4270E280UL))\r
+#define bFM3_MFS7_LIN_FCR0_FE2                 *((volatile unsigned int*)(0x4270E284UL))\r
+#define bFM3_MFS7_LIN_FCR0_FCL1                *((volatile unsigned int*)(0x4270E288UL))\r
+#define bFM3_MFS7_LIN_FCR0_FCL2                *((volatile unsigned int*)(0x4270E28CUL))\r
+#define bFM3_MFS7_LIN_FCR0_FSET                *((volatile unsigned int*)(0x4270E290UL))\r
+#define bFM3_MFS7_LIN_FCR0_FLD                 *((volatile unsigned int*)(0x4270E294UL))\r
+#define bFM3_MFS7_LIN_FCR0_FLST                *((volatile unsigned int*)(0x4270E298UL))\r
+#define bFM3_MFS7_LIN_FCR1_FSEL                *((volatile unsigned int*)(0x4270E2A0UL))\r
+#define bFM3_MFS7_LIN_FCR1_FTIE                *((volatile unsigned int*)(0x4270E2A4UL))\r
+#define bFM3_MFS7_LIN_FCR1_FDRQ                *((volatile unsigned int*)(0x4270E2A8UL))\r
+#define bFM3_MFS7_LIN_FCR1_FRIE                *((volatile unsigned int*)(0x4270E2ACUL))\r
+#define bFM3_MFS7_LIN_FCR1_FLSTE               *((volatile unsigned int*)(0x4270E2B0UL))\r
+#define bFM3_MFS7_LIN_FCR1_FTST0               *((volatile unsigned int*)(0x4270E2B8UL))\r
+#define bFM3_MFS7_LIN_FCR1_FTST1               *((volatile unsigned int*)(0x4270E2BCUL))\r
+#define bFM3_MFS7_LIN_FBYTE_FD0                *((volatile unsigned int*)(0x4270E300UL))\r
+#define bFM3_MFS7_LIN_FBYTE_FD1                *((volatile unsigned int*)(0x4270E304UL))\r
+#define bFM3_MFS7_LIN_FBYTE_FD2                *((volatile unsigned int*)(0x4270E308UL))\r
+#define bFM3_MFS7_LIN_FBYTE_FD3                *((volatile unsigned int*)(0x4270E30CUL))\r
+#define bFM3_MFS7_LIN_FBYTE_FD4                *((volatile unsigned int*)(0x4270E310UL))\r
+#define bFM3_MFS7_LIN_FBYTE_FD5                *((volatile unsigned int*)(0x4270E314UL))\r
+#define bFM3_MFS7_LIN_FBYTE_FD6                *((volatile unsigned int*)(0x4270E318UL))\r
+#define bFM3_MFS7_LIN_FBYTE_FD7                *((volatile unsigned int*)(0x4270E31CUL))\r
+#define bFM3_MFS7_LIN_FBYTE_FD8                *((volatile unsigned int*)(0x4270E320UL))\r
+#define bFM3_MFS7_LIN_FBYTE_FD9                *((volatile unsigned int*)(0x4270E324UL))\r
+#define bFM3_MFS7_LIN_FBYTE_FD10               *((volatile unsigned int*)(0x4270E328UL))\r
+#define bFM3_MFS7_LIN_FBYTE_FD11               *((volatile unsigned int*)(0x4270E32CUL))\r
+#define bFM3_MFS7_LIN_FBYTE_FD12               *((volatile unsigned int*)(0x4270E330UL))\r
+#define bFM3_MFS7_LIN_FBYTE_FD13               *((volatile unsigned int*)(0x4270E334UL))\r
+#define bFM3_MFS7_LIN_FBYTE_FD14               *((volatile unsigned int*)(0x4270E338UL))\r
+#define bFM3_MFS7_LIN_FBYTE_FD15               *((volatile unsigned int*)(0x4270E33CUL))\r
+#define bFM3_MFS7_LIN_FBYTE1_FD0               *((volatile unsigned int*)(0x4270E300UL))\r
+#define bFM3_MFS7_LIN_FBYTE1_FD1               *((volatile unsigned int*)(0x4270E304UL))\r
+#define bFM3_MFS7_LIN_FBYTE1_FD2               *((volatile unsigned int*)(0x4270E308UL))\r
+#define bFM3_MFS7_LIN_FBYTE1_FD3               *((volatile unsigned int*)(0x4270E30CUL))\r
+#define bFM3_MFS7_LIN_FBYTE1_FD4               *((volatile unsigned int*)(0x4270E310UL))\r
+#define bFM3_MFS7_LIN_FBYTE1_FD5               *((volatile unsigned int*)(0x4270E314UL))\r
+#define bFM3_MFS7_LIN_FBYTE1_FD6               *((volatile unsigned int*)(0x4270E318UL))\r
+#define bFM3_MFS7_LIN_FBYTE1_FD7               *((volatile unsigned int*)(0x4270E31CUL))\r
+#define bFM3_MFS7_LIN_FBYTE2_FD8               *((volatile unsigned int*)(0x4270E320UL))\r
+#define bFM3_MFS7_LIN_FBYTE2_FD9               *((volatile unsigned int*)(0x4270E324UL))\r
+#define bFM3_MFS7_LIN_FBYTE2_FD10              *((volatile unsigned int*)(0x4270E328UL))\r
+#define bFM3_MFS7_LIN_FBYTE2_FD11              *((volatile unsigned int*)(0x4270E32CUL))\r
+#define bFM3_MFS7_LIN_FBYTE2_FD12              *((volatile unsigned int*)(0x4270E330UL))\r
+#define bFM3_MFS7_LIN_FBYTE2_FD13              *((volatile unsigned int*)(0x4270E334UL))\r
+#define bFM3_MFS7_LIN_FBYTE2_FD14              *((volatile unsigned int*)(0x4270E338UL))\r
+#define bFM3_MFS7_LIN_FBYTE2_FD15              *((volatile unsigned int*)(0x4270E33CUL))\r
+\r
+/* I2C channel 7 registers */\r
+#define bFM3_MFS7_I2C_SMR_ITST0                *((volatile unsigned int*)(0x4270E000UL))\r
+#define bFM3_MFS7_I2C_SMR_ITST1                *((volatile unsigned int*)(0x4270E004UL))\r
+#define bFM3_MFS7_I2C_SMR_TIE                  *((volatile unsigned int*)(0x4270E008UL))\r
+#define bFM3_MFS7_I2C_SMR_RIE                  *((volatile unsigned int*)(0x4270E00CUL))\r
+#define bFM3_MFS7_I2C_SMR_WUCR                 *((volatile unsigned int*)(0x4270E010UL))\r
+#define bFM3_MFS7_I2C_SMR_MD0                  *((volatile unsigned int*)(0x4270E014UL))\r
+#define bFM3_MFS7_I2C_SMR_MD1                  *((volatile unsigned int*)(0x4270E018UL))\r
+#define bFM3_MFS7_I2C_SMR_MD2                  *((volatile unsigned int*)(0x4270E01CUL))\r
+#define bFM3_MFS7_I2C_IBCR_INT                 *((volatile unsigned int*)(0x4270E020UL))\r
+#define bFM3_MFS7_I2C_IBCR_BER                 *((volatile unsigned int*)(0x4270E024UL))\r
+#define bFM3_MFS7_I2C_IBCR_INTE                *((volatile unsigned int*)(0x4270E028UL))\r
+#define bFM3_MFS7_I2C_IBCR_CNDE                *((volatile unsigned int*)(0x4270E02CUL))\r
+#define bFM3_MFS7_I2C_IBCR_WSEL                *((volatile unsigned int*)(0x4270E030UL))\r
+#define bFM3_MFS7_I2C_IBCR_ACKE                *((volatile unsigned int*)(0x4270E034UL))\r
+#define bFM3_MFS7_I2C_IBCR_ACT                 *((volatile unsigned int*)(0x4270E038UL))\r
+#define bFM3_MFS7_I2C_IBCR_SCC                 *((volatile unsigned int*)(0x4270E038UL))\r
+#define bFM3_MFS7_I2C_IBCR_MSS                 *((volatile unsigned int*)(0x4270E03CUL))\r
+#define bFM3_MFS7_I2C_IBSR_BB                  *((volatile unsigned int*)(0x4270E080UL))\r
+#define bFM3_MFS7_I2C_IBSR_SPC                 *((volatile unsigned int*)(0x4270E084UL))\r
+#define bFM3_MFS7_I2C_IBSR_RSC                 *((volatile unsigned int*)(0x4270E088UL))\r
+#define bFM3_MFS7_I2C_IBSR_AL                  *((volatile unsigned int*)(0x4270E08CUL))\r
+#define bFM3_MFS7_I2C_IBSR_TRX                 *((volatile unsigned int*)(0x4270E090UL))\r
+#define bFM3_MFS7_I2C_IBSR_RSA                 *((volatile unsigned int*)(0x4270E094UL))\r
+#define bFM3_MFS7_I2C_IBSR_RACK                *((volatile unsigned int*)(0x4270E098UL))\r
+#define bFM3_MFS7_I2C_IBSR_FBT                 *((volatile unsigned int*)(0x4270E09CUL))\r
+#define bFM3_MFS7_I2C_SSR_TBI                  *((volatile unsigned int*)(0x4270E0A0UL))\r
+#define bFM3_MFS7_I2C_SSR_TDRE                 *((volatile unsigned int*)(0x4270E0A4UL))\r
+#define bFM3_MFS7_I2C_SSR_RDRF                 *((volatile unsigned int*)(0x4270E0A8UL))\r
+#define bFM3_MFS7_I2C_SSR_ORE                  *((volatile unsigned int*)(0x4270E0ACUL))\r
+#define bFM3_MFS7_I2C_SSR_TBIE                 *((volatile unsigned int*)(0x4270E0B0UL))\r
+#define bFM3_MFS7_I2C_SSR_DMA                  *((volatile unsigned int*)(0x4270E0B4UL))\r
+#define bFM3_MFS7_I2C_SSR_TSET                 *((volatile unsigned int*)(0x4270E0B8UL))\r
+#define bFM3_MFS7_I2C_SSR_REC                  *((volatile unsigned int*)(0x4270E0BCUL))\r
+#define bFM3_MFS7_I2C_ISBA_SA0                 *((volatile unsigned int*)(0x4270E200UL))\r
+#define bFM3_MFS7_I2C_ISBA_SA1                 *((volatile unsigned int*)(0x4270E204UL))\r
+#define bFM3_MFS7_I2C_ISBA_SA2                 *((volatile unsigned int*)(0x4270E208UL))\r
+#define bFM3_MFS7_I2C_ISBA_SA3                 *((volatile unsigned int*)(0x4270E20CUL))\r
+#define bFM3_MFS7_I2C_ISBA_SA4                 *((volatile unsigned int*)(0x4270E210UL))\r
+#define bFM3_MFS7_I2C_ISBA_SA5                 *((volatile unsigned int*)(0x4270E214UL))\r
+#define bFM3_MFS7_I2C_ISBA_SA6                 *((volatile unsigned int*)(0x4270E218UL))\r
+#define bFM3_MFS7_I2C_ISBA_SAEN                *((volatile unsigned int*)(0x4270E21CUL))\r
+#define bFM3_MFS7_I2C_ISMK_SM0                 *((volatile unsigned int*)(0x4270E220UL))\r
+#define bFM3_MFS7_I2C_ISMK_SM1                 *((volatile unsigned int*)(0x4270E224UL))\r
+#define bFM3_MFS7_I2C_ISMK_SM2                 *((volatile unsigned int*)(0x4270E228UL))\r
+#define bFM3_MFS7_I2C_ISMK_SM3                 *((volatile unsigned int*)(0x4270E22CUL))\r
+#define bFM3_MFS7_I2C_ISMK_SM4                 *((volatile unsigned int*)(0x4270E230UL))\r
+#define bFM3_MFS7_I2C_ISMK_SM5                 *((volatile unsigned int*)(0x4270E234UL))\r
+#define bFM3_MFS7_I2C_ISMK_SM6                 *((volatile unsigned int*)(0x4270E238UL))\r
+#define bFM3_MFS7_I2C_ISMK_EN                  *((volatile unsigned int*)(0x4270E23CUL))\r
+#define bFM3_MFS7_I2C_FCR_FE1                  *((volatile unsigned int*)(0x4270E280UL))\r
+#define bFM3_MFS7_I2C_FCR_FE2                  *((volatile unsigned int*)(0x4270E284UL))\r
+#define bFM3_MFS7_I2C_FCR_FCL1                 *((volatile unsigned int*)(0x4270E288UL))\r
+#define bFM3_MFS7_I2C_FCR_FCL2                 *((volatile unsigned int*)(0x4270E28CUL))\r
+#define bFM3_MFS7_I2C_FCR_FSET                 *((volatile unsigned int*)(0x4270E290UL))\r
+#define bFM3_MFS7_I2C_FCR_FLD                  *((volatile unsigned int*)(0x4270E294UL))\r
+#define bFM3_MFS7_I2C_FCR_FLST                 *((volatile unsigned int*)(0x4270E298UL))\r
+#define bFM3_MFS7_I2C_FCR_FSEL                 *((volatile unsigned int*)(0x4270E2A0UL))\r
+#define bFM3_MFS7_I2C_FCR_FTIE                 *((volatile unsigned int*)(0x4270E2A4UL))\r
+#define bFM3_MFS7_I2C_FCR_FDRQ                 *((volatile unsigned int*)(0x4270E2A8UL))\r
+#define bFM3_MFS7_I2C_FCR_FRIE                 *((volatile unsigned int*)(0x4270E2ACUL))\r
+#define bFM3_MFS7_I2C_FCR_FLSTE                *((volatile unsigned int*)(0x4270E2B0UL))\r
+#define bFM3_MFS7_I2C_FCR_FTST0                *((volatile unsigned int*)(0x4270E2B8UL))\r
+#define bFM3_MFS7_I2C_FCR_FTST1                *((volatile unsigned int*)(0x4270E2BCUL))\r
+#define bFM3_MFS7_I2C_FCR0_FE1                 *((volatile unsigned int*)(0x4270E280UL))\r
+#define bFM3_MFS7_I2C_FCR0_FE2                 *((volatile unsigned int*)(0x4270E284UL))\r
+#define bFM3_MFS7_I2C_FCR0_FCL1                *((volatile unsigned int*)(0x4270E288UL))\r
+#define bFM3_MFS7_I2C_FCR0_FCL2                *((volatile unsigned int*)(0x4270E28CUL))\r
+#define bFM3_MFS7_I2C_FCR0_FSET                *((volatile unsigned int*)(0x4270E290UL))\r
+#define bFM3_MFS7_I2C_FCR0_FLD                 *((volatile unsigned int*)(0x4270E294UL))\r
+#define bFM3_MFS7_I2C_FCR0_FLST                *((volatile unsigned int*)(0x4270E298UL))\r
+#define bFM3_MFS7_I2C_FCR1_FSEL                *((volatile unsigned int*)(0x4270E2A0UL))\r
+#define bFM3_MFS7_I2C_FCR1_FTIE                *((volatile unsigned int*)(0x4270E2A4UL))\r
+#define bFM3_MFS7_I2C_FCR1_FDRQ                *((volatile unsigned int*)(0x4270E2A8UL))\r
+#define bFM3_MFS7_I2C_FCR1_FRIE                *((volatile unsigned int*)(0x4270E2ACUL))\r
+#define bFM3_MFS7_I2C_FCR1_FLSTE               *((volatile unsigned int*)(0x4270E2B0UL))\r
+#define bFM3_MFS7_I2C_FCR1_FTST0               *((volatile unsigned int*)(0x4270E2B8UL))\r
+#define bFM3_MFS7_I2C_FCR1_FTST1               *((volatile unsigned int*)(0x4270E2BCUL))\r
+#define bFM3_MFS7_I2C_FBYTE_FD0                *((volatile unsigned int*)(0x4270E300UL))\r
+#define bFM3_MFS7_I2C_FBYTE_FD1                *((volatile unsigned int*)(0x4270E304UL))\r
+#define bFM3_MFS7_I2C_FBYTE_FD2                *((volatile unsigned int*)(0x4270E308UL))\r
+#define bFM3_MFS7_I2C_FBYTE_FD3                *((volatile unsigned int*)(0x4270E30CUL))\r
+#define bFM3_MFS7_I2C_FBYTE_FD4                *((volatile unsigned int*)(0x4270E310UL))\r
+#define bFM3_MFS7_I2C_FBYTE_FD5                *((volatile unsigned int*)(0x4270E314UL))\r
+#define bFM3_MFS7_I2C_FBYTE_FD6                *((volatile unsigned int*)(0x4270E318UL))\r
+#define bFM3_MFS7_I2C_FBYTE_FD7                *((volatile unsigned int*)(0x4270E31CUL))\r
+#define bFM3_MFS7_I2C_FBYTE_FD8                *((volatile unsigned int*)(0x4270E320UL))\r
+#define bFM3_MFS7_I2C_FBYTE_FD9                *((volatile unsigned int*)(0x4270E324UL))\r
+#define bFM3_MFS7_I2C_FBYTE_FD10               *((volatile unsigned int*)(0x4270E328UL))\r
+#define bFM3_MFS7_I2C_FBYTE_FD11               *((volatile unsigned int*)(0x4270E32CUL))\r
+#define bFM3_MFS7_I2C_FBYTE_FD12               *((volatile unsigned int*)(0x4270E330UL))\r
+#define bFM3_MFS7_I2C_FBYTE_FD13               *((volatile unsigned int*)(0x4270E334UL))\r
+#define bFM3_MFS7_I2C_FBYTE_FD14               *((volatile unsigned int*)(0x4270E338UL))\r
+#define bFM3_MFS7_I2C_FBYTE_FD15               *((volatile unsigned int*)(0x4270E33CUL))\r
+#define bFM3_MFS7_I2C_FBYTE1_FD0               *((volatile unsigned int*)(0x4270E300UL))\r
+#define bFM3_MFS7_I2C_FBYTE1_FD1               *((volatile unsigned int*)(0x4270E304UL))\r
+#define bFM3_MFS7_I2C_FBYTE1_FD2               *((volatile unsigned int*)(0x4270E308UL))\r
+#define bFM3_MFS7_I2C_FBYTE1_FD3               *((volatile unsigned int*)(0x4270E30CUL))\r
+#define bFM3_MFS7_I2C_FBYTE1_FD4               *((volatile unsigned int*)(0x4270E310UL))\r
+#define bFM3_MFS7_I2C_FBYTE1_FD5               *((volatile unsigned int*)(0x4270E314UL))\r
+#define bFM3_MFS7_I2C_FBYTE1_FD6               *((volatile unsigned int*)(0x4270E318UL))\r
+#define bFM3_MFS7_I2C_FBYTE1_FD7               *((volatile unsigned int*)(0x4270E31CUL))\r
+#define bFM3_MFS7_I2C_FBYTE2_FD8               *((volatile unsigned int*)(0x4270E320UL))\r
+#define bFM3_MFS7_I2C_FBYTE2_FD9               *((volatile unsigned int*)(0x4270E324UL))\r
+#define bFM3_MFS7_I2C_FBYTE2_FD10              *((volatile unsigned int*)(0x4270E328UL))\r
+#define bFM3_MFS7_I2C_FBYTE2_FD11              *((volatile unsigned int*)(0x4270E32CUL))\r
+#define bFM3_MFS7_I2C_FBYTE2_FD12              *((volatile unsigned int*)(0x4270E330UL))\r
+#define bFM3_MFS7_I2C_FBYTE2_FD13              *((volatile unsigned int*)(0x4270E334UL))\r
+#define bFM3_MFS7_I2C_FBYTE2_FD14              *((volatile unsigned int*)(0x4270E338UL))\r
+#define bFM3_MFS7_I2C_FBYTE2_FD15              *((volatile unsigned int*)(0x4270E33CUL))\r
+\r
+/* CRC registers */\r
+#define bFM3_CRC_CRCCR_INIT                    *((volatile unsigned int*)(0x42720000UL))\r
+#define bFM3_CRC_CRCCR_CRC32                   *((volatile unsigned int*)(0x42720004UL))\r
+#define bFM3_CRC_CRCCR_LTLEND                  *((volatile unsigned int*)(0x42720008UL))\r
+#define bFM3_CRC_CRCCR_LSBFST                  *((volatile unsigned int*)(0x4272000CUL))\r
+#define bFM3_CRC_CRCCR_CRCLTE                  *((volatile unsigned int*)(0x42720010UL))\r
+#define bFM3_CRC_CRCCR_CRCLSF                  *((volatile unsigned int*)(0x42720014UL))\r
+#define bFM3_CRC_CRCCR_FXOR                    *((volatile unsigned int*)(0x42720018UL))\r
+\r
+/* Watch counter registers */\r
+#define bFM3_WC_WCRD_CTR0                      *((volatile unsigned int*)(0x42740000UL))\r
+#define bFM3_WC_WCRD_CTR1                      *((volatile unsigned int*)(0x42740004UL))\r
+#define bFM3_WC_WCRD_CTR2                      *((volatile unsigned int*)(0x42740008UL))\r
+#define bFM3_WC_WCRD_CTR3                      *((volatile unsigned int*)(0x4274000CUL))\r
+#define bFM3_WC_WCRD_CTR4                      *((volatile unsigned int*)(0x42740010UL))\r
+#define bFM3_WC_WCRD_CTR5                      *((volatile unsigned int*)(0x42740014UL))\r
+#define bFM3_WC_WCRL_RLC0                      *((volatile unsigned int*)(0x42740020UL))\r
+#define bFM3_WC_WCRL_RLC1                      *((volatile unsigned int*)(0x42740024UL))\r
+#define bFM3_WC_WCRL_RLC2                      *((volatile unsigned int*)(0x42740028UL))\r
+#define bFM3_WC_WCRL_RLC3                      *((volatile unsigned int*)(0x4274002CUL))\r
+#define bFM3_WC_WCRL_RLC4                      *((volatile unsigned int*)(0x42740030UL))\r
+#define bFM3_WC_WCRL_RLC5                      *((volatile unsigned int*)(0x42740034UL))\r
+#define bFM3_WC_WCCR_WCIF                      *((volatile unsigned int*)(0x42740040UL))\r
+#define bFM3_WC_WCCR_WCIE                      *((volatile unsigned int*)(0x42740044UL))\r
+#define bFM3_WC_WCCR_CS0                       *((volatile unsigned int*)(0x42740048UL))\r
+#define bFM3_WC_WCCR_CS1                       *((volatile unsigned int*)(0x4274004CUL))\r
+#define bFM3_WC_WCCR_WCOP                      *((volatile unsigned int*)(0x42740058UL))\r
+#define bFM3_WC_WCCR_WCEN                      *((volatile unsigned int*)(0x4274005CUL))\r
+#define bFM3_WC_CLK_SEL_SEL_IN                 *((volatile unsigned int*)(0x42740200UL))\r
+#define bFM3_WC_CLK_SEL_SEL_OUT                *((volatile unsigned int*)(0x42740220UL))\r
+#define bFM3_WC_CLK_EN_CLK_EN                  *((volatile unsigned int*)(0x42740280UL))\r
+#define bFM3_WC_CLK_EN_CLK_EN_R                *((volatile unsigned int*)(0x42740284UL))\r
+\r
+/* USB channel 0 registers */\r
+#define bFM3_USB0_HCNT_HOST                    *((volatile unsigned int*)(0x42842000UL))\r
+#define bFM3_USB0_HCNT_URST                    *((volatile unsigned int*)(0x42842004UL))\r
+#define bFM3_USB0_HCNT_SOFIRE                  *((volatile unsigned int*)(0x42842008UL))\r
+#define bFM3_USB0_HCNT_DIRE                    *((volatile unsigned int*)(0x4284200CUL))\r
+#define bFM3_USB0_HCNT_CNNIRE                  *((volatile unsigned int*)(0x42842010UL))\r
+#define bFM3_USB0_HCNT_CMPIRE                  *((volatile unsigned int*)(0x42842014UL))\r
+#define bFM3_USB0_HCNT_URIRE                   *((volatile unsigned int*)(0x42842018UL))\r
+#define bFM3_USB0_HCNT_RWKIRE                  *((volatile unsigned int*)(0x4284201CUL))\r
+#define bFM3_USB0_HCNT_RETRY                   *((volatile unsigned int*)(0x42842020UL))\r
+#define bFM3_USB0_HCNT_CANCEL                  *((volatile unsigned int*)(0x42842024UL))\r
+#define bFM3_USB0_HCNT_SOFSTEP                 *((volatile unsigned int*)(0x42842028UL))\r
+#define bFM3_USB0_HCNT0_HOST                   *((volatile unsigned int*)(0x42842000UL))\r
+#define bFM3_USB0_HCNT0_URST                   *((volatile unsigned int*)(0x42842004UL))\r
+#define bFM3_USB0_HCNT0_SOFIRE                 *((volatile unsigned int*)(0x42842008UL))\r
+#define bFM3_USB0_HCNT0_DIRE                   *((volatile unsigned int*)(0x4284200CUL))\r
+#define bFM3_USB0_HCNT0_CNNIRE                 *((volatile unsigned int*)(0x42842010UL))\r
+#define bFM3_USB0_HCNT0_CMPIRE                 *((volatile unsigned int*)(0x42842014UL))\r
+#define bFM3_USB0_HCNT0_URIRE                  *((volatile unsigned int*)(0x42842018UL))\r
+#define bFM3_USB0_HCNT0_RWKIRE                 *((volatile unsigned int*)(0x4284201CUL))\r
+#define bFM3_USB0_HCNT1_RETRY                  *((volatile unsigned int*)(0x42842020UL))\r
+#define bFM3_USB0_HCNT1_CANCEL                 *((volatile unsigned int*)(0x42842024UL))\r
+#define bFM3_USB0_HCNT1_SOFSTEP                *((volatile unsigned int*)(0x42842028UL))\r
+#define bFM3_USB0_HIRQ_SOFIRQ                  *((volatile unsigned int*)(0x42842080UL))\r
+#define bFM3_USB0_HIRQ_DIRQ                    *((volatile unsigned int*)(0x42842084UL))\r
+#define bFM3_USB0_HIRQ_CNNIRQ                  *((volatile unsigned int*)(0x42842088UL))\r
+#define bFM3_USB0_HIRQ_CMPIRQ                  *((volatile unsigned int*)(0x4284208CUL))\r
+#define bFM3_USB0_HIRQ_URIRQ                   *((volatile unsigned int*)(0x42842090UL))\r
+#define bFM3_USB0_HIRQ_RWKIRQ                  *((volatile unsigned int*)(0x42842094UL))\r
+#define bFM3_USB0_HIRQ_TCAN                    *((volatile unsigned int*)(0x4284209CUL))\r
+#define bFM3_USB0_HERR_HS0                     *((volatile unsigned int*)(0x428420A0UL))\r
+#define bFM3_USB0_HERR_HS1                     *((volatile unsigned int*)(0x428420A4UL))\r
+#define bFM3_USB0_HERR_STUFF                   *((volatile unsigned int*)(0x428420A8UL))\r
+#define bFM3_USB0_HERR_TGERR                   *((volatile unsigned int*)(0x428420ACUL))\r
+#define bFM3_USB0_HERR_CRC                     *((volatile unsigned int*)(0x428420B0UL))\r
+#define bFM3_USB0_HERR_TOUT                    *((volatile unsigned int*)(0x428420B4UL))\r
+#define bFM3_USB0_HERR_RERR                    *((volatile unsigned int*)(0x428420B8UL))\r
+#define bFM3_USB0_HERR_LSTOF                   *((volatile unsigned int*)(0x428420BCUL))\r
+#define bFM3_USB0_HSTATE_CSTAT                 *((volatile unsigned int*)(0x42842100UL))\r
+#define bFM3_USB0_HSTATE_TMODE                 *((volatile unsigned int*)(0x42842104UL))\r
+#define bFM3_USB0_HSTATE_SUSP                  *((volatile unsigned int*)(0x42842108UL))\r
+#define bFM3_USB0_HSTATE_SOFBUSY               *((volatile unsigned int*)(0x4284210CUL))\r
+#define bFM3_USB0_HSTATE_CLKSEL                *((volatile unsigned int*)(0x42842110UL))\r
+#define bFM3_USB0_HSTATE_ALIVE                 *((volatile unsigned int*)(0x42842114UL))\r
+#define bFM3_USB0_HFCOMP_FRAMECOMP0            *((volatile unsigned int*)(0x42842120UL))\r
+#define bFM3_USB0_HFCOMP_FRAMECOMP1            *((volatile unsigned int*)(0x42842124UL))\r
+#define bFM3_USB0_HFCOMP_FRAMECOMP2            *((volatile unsigned int*)(0x42842128UL))\r
+#define bFM3_USB0_HFCOMP_FRAMECOMP3            *((volatile unsigned int*)(0x4284212CUL))\r
+#define bFM3_USB0_HFCOMP_FRAMECOMP4            *((volatile unsigned int*)(0x42842130UL))\r
+#define bFM3_USB0_HFCOMP_FRAMECOMP5            *((volatile unsigned int*)(0x42842134UL))\r
+#define bFM3_USB0_HFCOMP_FRAMECOMP6            *((volatile unsigned int*)(0x42842138UL))\r
+#define bFM3_USB0_HFCOMP_FRAMECOMP7            *((volatile unsigned int*)(0x4284213CUL))\r
+#define bFM3_USB0_HRTIMER_RTIMER0              *((volatile unsigned int*)(0x42842180UL))\r
+#define bFM3_USB0_HRTIMER_RTIMER1              *((volatile unsigned int*)(0x42842184UL))\r
+#define bFM3_USB0_HRTIMER_RTIMER2              *((volatile unsigned int*)(0x42842188UL))\r
+#define bFM3_USB0_HRTIMER_RTIMER3              *((volatile unsigned int*)(0x4284218CUL))\r
+#define bFM3_USB0_HRTIMER_RTIMER4              *((volatile unsigned int*)(0x42842190UL))\r
+#define bFM3_USB0_HRTIMER_RTIMER5              *((volatile unsigned int*)(0x42842194UL))\r
+#define bFM3_USB0_HRTIMER_RTIMER6              *((volatile unsigned int*)(0x42842198UL))\r
+#define bFM3_USB0_HRTIMER_RTIMER7              *((volatile unsigned int*)(0x4284219CUL))\r
+#define bFM3_USB0_HRTIMER_RTIMER8              *((volatile unsigned int*)(0x428421A0UL))\r
+#define bFM3_USB0_HRTIMER_RTIMER9              *((volatile unsigned int*)(0x428421A4UL))\r
+#define bFM3_USB0_HRTIMER_RTIMER10             *((volatile unsigned int*)(0x428421A8UL))\r
+#define bFM3_USB0_HRTIMER_RTIMER11             *((volatile unsigned int*)(0x428421ACUL))\r
+#define bFM3_USB0_HRTIMER_RTIMER12             *((volatile unsigned int*)(0x428421B0UL))\r
+#define bFM3_USB0_HRTIMER_RTIMER13             *((volatile unsigned int*)(0x428421B4UL))\r
+#define bFM3_USB0_HRTIMER_RTIMER14             *((volatile unsigned int*)(0x428421B8UL))\r
+#define bFM3_USB0_HRTIMER_RTIMER15             *((volatile unsigned int*)(0x428421BCUL))\r
+#define bFM3_USB0_HRTIMER0_RTIMER00            *((volatile unsigned int*)(0x42842180UL))\r
+#define bFM3_USB0_HRTIMER0_RTIMER01            *((volatile unsigned int*)(0x42842184UL))\r
+#define bFM3_USB0_HRTIMER0_RTIMER02            *((volatile unsigned int*)(0x42842188UL))\r
+#define bFM3_USB0_HRTIMER0_RTIMER03            *((volatile unsigned int*)(0x4284218CUL))\r
+#define bFM3_USB0_HRTIMER0_RTIMER04            *((volatile unsigned int*)(0x42842190UL))\r
+#define bFM3_USB0_HRTIMER0_RTIMER05            *((volatile unsigned int*)(0x42842194UL))\r
+#define bFM3_USB0_HRTIMER0_RTIMER06            *((volatile unsigned int*)(0x42842198UL))\r
+#define bFM3_USB0_HRTIMER0_RTIMER07            *((volatile unsigned int*)(0x4284219CUL))\r
+#define bFM3_USB0_HRTIMER1_RTIMER10            *((volatile unsigned int*)(0x428421A0UL))\r
+#define bFM3_USB0_HRTIMER1_RTIMER11            *((volatile unsigned int*)(0x428421A4UL))\r
+#define bFM3_USB0_HRTIMER1_RTIMER12            *((volatile unsigned int*)(0x428421A8UL))\r
+#define bFM3_USB0_HRTIMER1_RTIMER13            *((volatile unsigned int*)(0x428421ACUL))\r
+#define bFM3_USB0_HRTIMER1_RTIMER14            *((volatile unsigned int*)(0x428421B0UL))\r
+#define bFM3_USB0_HRTIMER1_RTIMER15            *((volatile unsigned int*)(0x428421B4UL))\r
+#define bFM3_USB0_HRTIMER1_RTIMER16            *((volatile unsigned int*)(0x428421B8UL))\r
+#define bFM3_USB0_HRTIMER1_RTIMER17            *((volatile unsigned int*)(0x428421BCUL))\r
+#define bFM3_USB0_HRTIMER2_RTIMER20            *((volatile unsigned int*)(0x42842200UL))\r
+#define bFM3_USB0_HRTIMER2_RTIMER21            *((volatile unsigned int*)(0x42842204UL))\r
+#define bFM3_USB0_HRTIMER2_RTIMER22            *((volatile unsigned int*)(0x42842208UL))\r
+#define bFM3_USB0_HADR_ADDRESS0                *((volatile unsigned int*)(0x42842220UL))\r
+#define bFM3_USB0_HADR_ADDRESS1                *((volatile unsigned int*)(0x42842224UL))\r
+#define bFM3_USB0_HADR_ADDRESS2                *((volatile unsigned int*)(0x42842228UL))\r
+#define bFM3_USB0_HADR_ADDRESS3                *((volatile unsigned int*)(0x4284222CUL))\r
+#define bFM3_USB0_HADR_ADDRESS4                *((volatile unsigned int*)(0x42842230UL))\r
+#define bFM3_USB0_HADR_ADDRESS5                *((volatile unsigned int*)(0x42842234UL))\r
+#define bFM3_USB0_HADR_ADDRESS6                *((volatile unsigned int*)(0x42842238UL))\r
+#define bFM3_USB0_HEOF_EOF0                    *((volatile unsigned int*)(0x42842280UL))\r
+#define bFM3_USB0_HEOF_EOF1                    *((volatile unsigned int*)(0x42842284UL))\r
+#define bFM3_USB0_HEOF_EOF2                    *((volatile unsigned int*)(0x42842288UL))\r
+#define bFM3_USB0_HEOF_EOF3                    *((volatile unsigned int*)(0x4284228CUL))\r
+#define bFM3_USB0_HEOF_EOF4                    *((volatile unsigned int*)(0x42842290UL))\r
+#define bFM3_USB0_HEOF_EOF5                    *((volatile unsigned int*)(0x42842294UL))\r
+#define bFM3_USB0_HEOF_EOF6                    *((volatile unsigned int*)(0x42842298UL))\r
+#define bFM3_USB0_HEOF_EOF7                    *((volatile unsigned int*)(0x4284229CUL))\r
+#define bFM3_USB0_HEOF_EOF8                    *((volatile unsigned int*)(0x428422A0UL))\r
+#define bFM3_USB0_HEOF_EOF9                    *((volatile unsigned int*)(0x428422A4UL))\r
+#define bFM3_USB0_HEOF_EOF10                   *((volatile unsigned int*)(0x428422A8UL))\r
+#define bFM3_USB0_HEOF_EOF11                   *((volatile unsigned int*)(0x428422ACUL))\r
+#define bFM3_USB0_HEOF_EOF12                   *((volatile unsigned int*)(0x428422B0UL))\r
+#define bFM3_USB0_HEOF_EOF13                   *((volatile unsigned int*)(0x428422B4UL))\r
+#define bFM3_USB0_HEOF_EOF14                   *((volatile unsigned int*)(0x428422B8UL))\r
+#define bFM3_USB0_HEOF_EOF15                   *((volatile unsigned int*)(0x428422BCUL))\r
+#define bFM3_USB0_HEOF0_EOF00                  *((volatile unsigned int*)(0x42842280UL))\r
+#define bFM3_USB0_HEOF0_EOF01                  *((volatile unsigned int*)(0x42842284UL))\r
+#define bFM3_USB0_HEOF0_EOF02                  *((volatile unsigned int*)(0x42842288UL))\r
+#define bFM3_USB0_HEOF0_EOF03                  *((volatile unsigned int*)(0x4284228CUL))\r
+#define bFM3_USB0_HEOF0_EOF04                  *((volatile unsigned int*)(0x42842290UL))\r
+#define bFM3_USB0_HEOF0_EOF05                  *((volatile unsigned int*)(0x42842294UL))\r
+#define bFM3_USB0_HEOF0_EOF06                  *((volatile unsigned int*)(0x42842298UL))\r
+#define bFM3_USB0_HEOF0_EOF07                  *((volatile unsigned int*)(0x4284229CUL))\r
+#define bFM3_USB0_HEOF1_EOF10                  *((volatile unsigned int*)(0x428422A0UL))\r
+#define bFM3_USB0_HEOF1_EOF11                  *((volatile unsigned int*)(0x428422A4UL))\r
+#define bFM3_USB0_HEOF1_EOF12                  *((volatile unsigned int*)(0x428422A8UL))\r
+#define bFM3_USB0_HEOF1_EOF13                  *((volatile unsigned int*)(0x428422ACUL))\r
+#define bFM3_USB0_HEOF1_EOF14                  *((volatile unsigned int*)(0x428422B0UL))\r
+#define bFM3_USB0_HEOF1_EOF15                  *((volatile unsigned int*)(0x428422B4UL))\r
+#define bFM3_USB0_HFRAME_FRAME0                *((volatile unsigned int*)(0x42842300UL))\r
+#define bFM3_USB0_HFRAME_FRAME1                *((volatile unsigned int*)(0x42842304UL))\r
+#define bFM3_USB0_HFRAME_FRAME2                *((volatile unsigned int*)(0x42842308UL))\r
+#define bFM3_USB0_HFRAME_FRAME3                *((volatile unsigned int*)(0x4284230CUL))\r
+#define bFM3_USB0_HFRAME_FRAME4                *((volatile unsigned int*)(0x42842310UL))\r
+#define bFM3_USB0_HFRAME_FRAME5                *((volatile unsigned int*)(0x42842314UL))\r
+#define bFM3_USB0_HFRAME_FRAME6                *((volatile unsigned int*)(0x42842318UL))\r
+#define bFM3_USB0_HFRAME_FRAME7                *((volatile unsigned int*)(0x4284231CUL))\r
+#define bFM3_USB0_HFRAME_FRAME8                *((volatile unsigned int*)(0x42842320UL))\r
+#define bFM3_USB0_HFRAME_FRAME9                *((volatile unsigned int*)(0x42842324UL))\r
+#define bFM3_USB0_HFRAME_FRAME10               *((volatile unsigned int*)(0x42842328UL))\r
+#define bFM3_USB0_HFRAME0_FRAME00              *((volatile unsigned int*)(0x42842300UL))\r
+#define bFM3_USB0_HFRAME0_FRAME01              *((volatile unsigned int*)(0x42842304UL))\r
+#define bFM3_USB0_HFRAME0_FRAME02              *((volatile unsigned int*)(0x42842308UL))\r
+#define bFM3_USB0_HFRAME0_FRAME03              *((volatile unsigned int*)(0x4284230CUL))\r
+#define bFM3_USB0_HFRAME0_FRAME04              *((volatile unsigned int*)(0x42842310UL))\r
+#define bFM3_USB0_HFRAME0_FRAME05              *((volatile unsigned int*)(0x42842314UL))\r
+#define bFM3_USB0_HFRAME0_FRAME06              *((volatile unsigned int*)(0x42842318UL))\r
+#define bFM3_USB0_HFRAME0_FRAME07              *((volatile unsigned int*)(0x4284231CUL))\r
+#define bFM3_USB0_HFRAME1_FRAME10              *((volatile unsigned int*)(0x42842320UL))\r
+#define bFM3_USB0_HFRAME1_FRAME11              *((volatile unsigned int*)(0x42842324UL))\r
+#define bFM3_USB0_HFRAME1_FRAME12              *((volatile unsigned int*)(0x42842328UL))\r
+#define bFM3_USB0_HFRAME1_FRAME13              *((volatile unsigned int*)(0x4284232CUL))\r
+#define bFM3_USB0_HTOKEN_ENDPT0                *((volatile unsigned int*)(0x42842380UL))\r
+#define bFM3_USB0_HTOKEN_ENDPT1                *((volatile unsigned int*)(0x42842384UL))\r
+#define bFM3_USB0_HTOKEN_ENDPT2                *((volatile unsigned int*)(0x42842388UL))\r
+#define bFM3_USB0_HTOKEN_ENDPT3                *((volatile unsigned int*)(0x4284238CUL))\r
+#define bFM3_USB0_HTOKEN_TKNEN0                *((volatile unsigned int*)(0x42842390UL))\r
+#define bFM3_USB0_HTOKEN_TKNEN1                *((volatile unsigned int*)(0x42842394UL))\r
+#define bFM3_USB0_HTOKEN_TKNEN2                *((volatile unsigned int*)(0x42842398UL))\r
+#define bFM3_USB0_HTOKEN_TGGL                  *((volatile unsigned int*)(0x4284239CUL))\r
+#define bFM3_USB0_UDCC_PWC                     *((volatile unsigned int*)(0x42842400UL))\r
+#define bFM3_USB0_UDCC_RFBK                    *((volatile unsigned int*)(0x42842404UL))\r
+#define bFM3_USB0_UDCC_STALCLREN               *((volatile unsigned int*)(0x4284240CUL))\r
+#define bFM3_USB0_UDCC_USTP                    *((volatile unsigned int*)(0x42842410UL))\r
+#define bFM3_USB0_UDCC_HCONX                   *((volatile unsigned int*)(0x42842414UL))\r
+#define bFM3_USB0_UDCC_RESUM                   *((volatile unsigned int*)(0x42842418UL))\r
+#define bFM3_USB0_UDCC_RST                     *((volatile unsigned int*)(0x4284241CUL))\r
+#define bFM3_USB0_EP0C_PKS00                   *((volatile unsigned int*)(0x42842480UL))\r
+#define bFM3_USB0_EP0C_PKS01                   *((volatile unsigned int*)(0x42842484UL))\r
+#define bFM3_USB0_EP0C_PKS02                   *((volatile unsigned int*)(0x42842488UL))\r
+#define bFM3_USB0_EP0C_PKS03                   *((volatile unsigned int*)(0x4284248CUL))\r
+#define bFM3_USB0_EP0C_PKS04                   *((volatile unsigned int*)(0x42842490UL))\r
+#define bFM3_USB0_EP0C_PKS05                   *((volatile unsigned int*)(0x42842494UL))\r
+#define bFM3_USB0_EP0C_PKS06                   *((volatile unsigned int*)(0x42842498UL))\r
+#define bFM3_USB0_EP0C_STAL                    *((volatile unsigned int*)(0x428424A4UL))\r
+#define bFM3_USB0_EP1C_PKS10                   *((volatile unsigned int*)(0x42842500UL))\r
+#define bFM3_USB0_EP1C_PKS11                   *((volatile unsigned int*)(0x42842504UL))\r
+#define bFM3_USB0_EP1C_PKS12                   *((volatile unsigned int*)(0x42842508UL))\r
+#define bFM3_USB0_EP1C_PKS13                   *((volatile unsigned int*)(0x4284250CUL))\r
+#define bFM3_USB0_EP1C_PKS14                   *((volatile unsigned int*)(0x42842510UL))\r
+#define bFM3_USB0_EP1C_PKS15                   *((volatile unsigned int*)(0x42842514UL))\r
+#define bFM3_USB0_EP1C_PKS16                   *((volatile unsigned int*)(0x42842518UL))\r
+#define bFM3_USB0_EP1C_PKS17                   *((volatile unsigned int*)(0x4284251CUL))\r
+#define bFM3_USB0_EP1C_PKS18                   *((volatile unsigned int*)(0x42842520UL))\r
+#define bFM3_USB0_EP1C_STAL                    *((volatile unsigned int*)(0x42842524UL))\r
+#define bFM3_USB0_EP1C_NULE                    *((volatile unsigned int*)(0x42842528UL))\r
+#define bFM3_USB0_EP1C_DMAE                    *((volatile unsigned int*)(0x4284252CUL))\r
+#define bFM3_USB0_EP1C_DIR                     *((volatile unsigned int*)(0x42842530UL))\r
+#define bFM3_USB0_EP1C_TYPE0                   *((volatile unsigned int*)(0x42842534UL))\r
+#define bFM3_USB0_EP1C_TYPE1                   *((volatile unsigned int*)(0x42842538UL))\r
+#define bFM3_USB0_EP1C_EPEN                    *((volatile unsigned int*)(0x4284253CUL))\r
+#define bFM3_USB0_EP2C_PKS20                   *((volatile unsigned int*)(0x42842580UL))\r
+#define bFM3_USB0_EP2C_PKS21                   *((volatile unsigned int*)(0x42842584UL))\r
+#define bFM3_USB0_EP2C_PKS22                   *((volatile unsigned int*)(0x42842588UL))\r
+#define bFM3_USB0_EP2C_PKS23                   *((volatile unsigned int*)(0x4284258CUL))\r
+#define bFM3_USB0_EP2C_PKS24                   *((volatile unsigned int*)(0x42842590UL))\r
+#define bFM3_USB0_EP2C_PKS25                   *((volatile unsigned int*)(0x42842594UL))\r
+#define bFM3_USB0_EP2C_PKS26                   *((volatile unsigned int*)(0x42842598UL))\r
+#define bFM3_USB0_EP2C_STAL                    *((volatile unsigned int*)(0x428425A4UL))\r
+#define bFM3_USB0_EP2C_NULE                    *((volatile unsigned int*)(0x428425A8UL))\r
+#define bFM3_USB0_EP2C_DMAE                    *((volatile unsigned int*)(0x428425ACUL))\r
+#define bFM3_USB0_EP2C_DIR                     *((volatile unsigned int*)(0x428425B0UL))\r
+#define bFM3_USB0_EP2C_TYPE0                   *((volatile unsigned int*)(0x428425B4UL))\r
+#define bFM3_USB0_EP2C_TYPE1                   *((volatile unsigned int*)(0x428425B8UL))\r
+#define bFM3_USB0_EP2C_EPEN                    *((volatile unsigned int*)(0x428425BCUL))\r
+#define bFM3_USB0_EP3C_PKS30                   *((volatile unsigned int*)(0x42842600UL))\r
+#define bFM3_USB0_EP3C_PKS31                   *((volatile unsigned int*)(0x42842604UL))\r
+#define bFM3_USB0_EP3C_PKS32                   *((volatile unsigned int*)(0x42842608UL))\r
+#define bFM3_USB0_EP3C_PKS33                   *((volatile unsigned int*)(0x4284260CUL))\r
+#define bFM3_USB0_EP3C_PKS34                   *((volatile unsigned int*)(0x42842610UL))\r
+#define bFM3_USB0_EP3C_PKS35                   *((volatile unsigned int*)(0x42842614UL))\r
+#define bFM3_USB0_EP3C_PKS36                   *((volatile unsigned int*)(0x42842618UL))\r
+#define bFM3_USB0_EP3C_STAL                    *((volatile unsigned int*)(0x42842624UL))\r
+#define bFM3_USB0_EP3C_NULE                    *((volatile unsigned int*)(0x42842628UL))\r
+#define bFM3_USB0_EP3C_DMAE                    *((volatile unsigned int*)(0x4284262CUL))\r
+#define bFM3_USB0_EP3C_DIR                     *((volatile unsigned int*)(0x42842630UL))\r
+#define bFM3_USB0_EP3C_TYPE0                   *((volatile unsigned int*)(0x42842634UL))\r
+#define bFM3_USB0_EP3C_TYPE1                   *((volatile unsigned int*)(0x42842638UL))\r
+#define bFM3_USB0_EP3C_EPEN                    *((volatile unsigned int*)(0x4284263CUL))\r
+#define bFM3_USB0_EP4C_PKS40                   *((volatile unsigned int*)(0x42842680UL))\r
+#define bFM3_USB0_EP4C_PKS41                   *((volatile unsigned int*)(0x42842684UL))\r
+#define bFM3_USB0_EP4C_PKS42                   *((volatile unsigned int*)(0x42842688UL))\r
+#define bFM3_USB0_EP4C_PKS43                   *((volatile unsigned int*)(0x4284268CUL))\r
+#define bFM3_USB0_EP4C_PKS44                   *((volatile unsigned int*)(0x42842690UL))\r
+#define bFM3_USB0_EP4C_PKS45                   *((volatile unsigned int*)(0x42842694UL))\r
+#define bFM3_USB0_EP4C_PKS46                   *((volatile unsigned int*)(0x42842698UL))\r
+#define bFM3_USB0_EP4C_STAL                    *((volatile unsigned int*)(0x428426A4UL))\r
+#define bFM3_USB0_EP4C_NULE                    *((volatile unsigned int*)(0x428426A8UL))\r
+#define bFM3_USB0_EP4C_DMAE                    *((volatile unsigned int*)(0x428426ACUL))\r
+#define bFM3_USB0_EP4C_DIR                     *((volatile unsigned int*)(0x428426B0UL))\r
+#define bFM3_USB0_EP4C_TYPE0                   *((volatile unsigned int*)(0x428426B4UL))\r
+#define bFM3_USB0_EP4C_TYPE1                   *((volatile unsigned int*)(0x428426B8UL))\r
+#define bFM3_USB0_EP4C_EPEN                    *((volatile unsigned int*)(0x428426BCUL))\r
+#define bFM3_USB0_EP5C_PKS50                   *((volatile unsigned int*)(0x42842700UL))\r
+#define bFM3_USB0_EP5C_PKS51                   *((volatile unsigned int*)(0x42842704UL))\r
+#define bFM3_USB0_EP5C_PKS52                   *((volatile unsigned int*)(0x42842708UL))\r
+#define bFM3_USB0_EP5C_PKS53                   *((volatile unsigned int*)(0x4284270CUL))\r
+#define bFM3_USB0_EP5C_PKS54                   *((volatile unsigned int*)(0x42842710UL))\r
+#define bFM3_USB0_EP5C_PKS55                   *((volatile unsigned int*)(0x42842714UL))\r
+#define bFM3_USB0_EP5C_PKS56                   *((volatile unsigned int*)(0x42842718UL))\r
+#define bFM3_USB0_EP5C_STAL                    *((volatile unsigned int*)(0x42842724UL))\r
+#define bFM3_USB0_EP5C_NULE                    *((volatile unsigned int*)(0x42842728UL))\r
+#define bFM3_USB0_EP5C_DMAE                    *((volatile unsigned int*)(0x4284272CUL))\r
+#define bFM3_USB0_EP5C_DIR                     *((volatile unsigned int*)(0x42842730UL))\r
+#define bFM3_USB0_EP5C_TYPE0                   *((volatile unsigned int*)(0x42842734UL))\r
+#define bFM3_USB0_EP5C_TYPE1                   *((volatile unsigned int*)(0x42842738UL))\r
+#define bFM3_USB0_EP5C_EPEN                    *((volatile unsigned int*)(0x4284273CUL))\r
+#define bFM3_USB0_TMSP_TMSP0                   *((volatile unsigned int*)(0x42842780UL))\r
+#define bFM3_USB0_TMSP_TMSP1                   *((volatile unsigned int*)(0x42842784UL))\r
+#define bFM3_USB0_TMSP_TMSP2                   *((volatile unsigned int*)(0x42842788UL))\r
+#define bFM3_USB0_TMSP_TMSP3                   *((volatile unsigned int*)(0x4284278CUL))\r
+#define bFM3_USB0_TMSP_TMSP4                   *((volatile unsigned int*)(0x42842790UL))\r
+#define bFM3_USB0_TMSP_TMSP5                   *((volatile unsigned int*)(0x42842794UL))\r
+#define bFM3_USB0_TMSP_TMSP6                   *((volatile unsigned int*)(0x42842798UL))\r
+#define bFM3_USB0_TMSP_TMSP7                   *((volatile unsigned int*)(0x4284279CUL))\r
+#define bFM3_USB0_TMSP_TMSP8                   *((volatile unsigned int*)(0x428427A0UL))\r
+#define bFM3_USB0_TMSP_TMSP9                   *((volatile unsigned int*)(0x428427A4UL))\r
+#define bFM3_USB0_TMSP_TMSP10                  *((volatile unsigned int*)(0x428427A8UL))\r
+#define bFM3_USB0_UDCS_CONF                    *((volatile unsigned int*)(0x42842800UL))\r
+#define bFM3_USB0_UDCS_SETP                    *((volatile unsigned int*)(0x42842804UL))\r
+#define bFM3_USB0_UDCS_WKUP                    *((volatile unsigned int*)(0x42842808UL))\r
+#define bFM3_USB0_UDCS_BRST                    *((volatile unsigned int*)(0x4284280CUL))\r
+#define bFM3_USB0_UDCS_SOF                     *((volatile unsigned int*)(0x42842810UL))\r
+#define bFM3_USB0_UDCS_SUSP                    *((volatile unsigned int*)(0x42842814UL))\r
+#define bFM3_USB0_UDCIE_CONFIE                 *((volatile unsigned int*)(0x42842820UL))\r
+#define bFM3_USB0_UDCIE_CONFN                  *((volatile unsigned int*)(0x42842824UL))\r
+#define bFM3_USB0_UDCIE_WKUPIE                 *((volatile unsigned int*)(0x42842828UL))\r
+#define bFM3_USB0_UDCIE_BRSTIE                 *((volatile unsigned int*)(0x4284282CUL))\r
+#define bFM3_USB0_UDCIE_SOFIE                  *((volatile unsigned int*)(0x42842830UL))\r
+#define bFM3_USB0_UDCIE_SUSPIE                 *((volatile unsigned int*)(0x42842834UL))\r
+#define bFM3_USB0_EP0IS_DRQI                   *((volatile unsigned int*)(0x428428A8UL))\r
+#define bFM3_USB0_EP0IS_DRQIIE                 *((volatile unsigned int*)(0x428428B8UL))\r
+#define bFM3_USB0_EP0IS_BFINI                  *((volatile unsigned int*)(0x428428BCUL))\r
+#define bFM3_USB0_EP0OS_SIZE0                  *((volatile unsigned int*)(0x42842900UL))\r
+#define bFM3_USB0_EP0OS_SIZE1                  *((volatile unsigned int*)(0x42842904UL))\r
+#define bFM3_USB0_EP0OS_SIZE2                  *((volatile unsigned int*)(0x42842908UL))\r
+#define bFM3_USB0_EP0OS_SIZE3                  *((volatile unsigned int*)(0x4284290CUL))\r
+#define bFM3_USB0_EP0OS_SIZE4                  *((volatile unsigned int*)(0x42842910UL))\r
+#define bFM3_USB0_EP0OS_SIZE5                  *((volatile unsigned int*)(0x42842914UL))\r
+#define bFM3_USB0_EP0OS_SIZE6                  *((volatile unsigned int*)(0x42842918UL))\r
+#define bFM3_USB0_EP0OS_SPK                    *((volatile unsigned int*)(0x42842924UL))\r
+#define bFM3_USB0_EP0OS_DRQO                   *((volatile unsigned int*)(0x42842928UL))\r
+#define bFM3_USB0_EP0OS_SPKIE                  *((volatile unsigned int*)(0x42842934UL))\r
+#define bFM3_USB0_EP0OS_DRQOIE                 *((volatile unsigned int*)(0x42842938UL))\r
+#define bFM3_USB0_EP0OS_BFINI                  *((volatile unsigned int*)(0x4284293CUL))\r
+#define bFM3_USB0_EP1S_SIZE10                  *((volatile unsigned int*)(0x42842980UL))\r
+#define bFM3_USB0_EP1S_SIZE11                  *((volatile unsigned int*)(0x42842984UL))\r
+#define bFM3_USB0_EP1S_SIZE12                  *((volatile unsigned int*)(0x42842988UL))\r
+#define bFM3_USB0_EP1S_SIZE13                  *((volatile unsigned int*)(0x4284298CUL))\r
+#define bFM3_USB0_EP1S_SIZE14                  *((volatile unsigned int*)(0x42842990UL))\r
+#define bFM3_USB0_EP1S_SIZE15                  *((volatile unsigned int*)(0x42842994UL))\r
+#define bFM3_USB0_EP1S_SIZE16                  *((volatile unsigned int*)(0x42842998UL))\r
+#define bFM3_USB0_EP1S_SIZE17                  *((volatile unsigned int*)(0x4284299CUL))\r
+#define bFM3_USB0_EP1S_SIZE18                  *((volatile unsigned int*)(0x428429A0UL))\r
+#define bFM3_USB0_EP1S_SPK                     *((volatile unsigned int*)(0x428429A4UL))\r
+#define bFM3_USB0_EP1S_DRQ                     *((volatile unsigned int*)(0x428429A8UL))\r
+#define bFM3_USB0_EP1S_BUSY                    *((volatile unsigned int*)(0x428429ACUL))\r
+#define bFM3_USB0_EP1S_SPKIE                   *((volatile unsigned int*)(0x428429B4UL))\r
+#define bFM3_USB0_EP1S_DRQIE                   *((volatile unsigned int*)(0x428429B8UL))\r
+#define bFM3_USB0_EP1S_BFINI                   *((volatile unsigned int*)(0x428429BCUL))\r
+#define bFM3_USB0_EP2S_SIZE20                  *((volatile unsigned int*)(0x42842A00UL))\r
+#define bFM3_USB0_EP2S_SIZE21                  *((volatile unsigned int*)(0x42842A04UL))\r
+#define bFM3_USB0_EP2S_SIZE22                  *((volatile unsigned int*)(0x42842A08UL))\r
+#define bFM3_USB0_EP2S_SIZE23                  *((volatile unsigned int*)(0x42842A0CUL))\r
+#define bFM3_USB0_EP2S_SIZE24                  *((volatile unsigned int*)(0x42842A10UL))\r
+#define bFM3_USB0_EP2S_SIZE25                  *((volatile unsigned int*)(0x42842A14UL))\r
+#define bFM3_USB0_EP2S_SIZE26                  *((volatile unsigned int*)(0x42842A18UL))\r
+#define bFM3_USB0_EP2S_SPK                     *((volatile unsigned int*)(0x42842A24UL))\r
+#define bFM3_USB0_EP2S_DRQ                     *((volatile unsigned int*)(0x42842A28UL))\r
+#define bFM3_USB0_EP2S_BUSY                    *((volatile unsigned int*)(0x42842A2CUL))\r
+#define bFM3_USB0_EP2S_SPKIE                   *((volatile unsigned int*)(0x42842A34UL))\r
+#define bFM3_USB0_EP2S_DRQIE                   *((volatile unsigned int*)(0x42842A38UL))\r
+#define bFM3_USB0_EP2S_BFINI                   *((volatile unsigned int*)(0x42842A3CUL))\r
+#define bFM3_USB0_EP3S_SIZE30                  *((volatile unsigned int*)(0x42842A80UL))\r
+#define bFM3_USB0_EP3S_SIZE31                  *((volatile unsigned int*)(0x42842A84UL))\r
+#define bFM3_USB0_EP3S_SIZE32                  *((volatile unsigned int*)(0x42842A88UL))\r
+#define bFM3_USB0_EP3S_SIZE33                  *((volatile unsigned int*)(0x42842A8CUL))\r
+#define bFM3_USB0_EP3S_SIZE34                  *((volatile unsigned int*)(0x42842A90UL))\r
+#define bFM3_USB0_EP3S_SIZE35                  *((volatile unsigned int*)(0x42842A94UL))\r
+#define bFM3_USB0_EP3S_SIZE36                  *((volatile unsigned int*)(0x42842A98UL))\r
+#define bFM3_USB0_EP3S_SPK                     *((volatile unsigned int*)(0x42842AA4UL))\r
+#define bFM3_USB0_EP3S_DRQ                     *((volatile unsigned int*)(0x42842AA8UL))\r
+#define bFM3_USB0_EP3S_BUSY                    *((volatile unsigned int*)(0x42842AACUL))\r
+#define bFM3_USB0_EP3S_SPKIE                   *((volatile unsigned int*)(0x42842AB4UL))\r
+#define bFM3_USB0_EP3S_DRQIE                   *((volatile unsigned int*)(0x42842AB8UL))\r
+#define bFM3_USB0_EP3S_BFINI                   *((volatile unsigned int*)(0x42842ABCUL))\r
+#define bFM3_USB0_EP4S_SIZE40                  *((volatile unsigned int*)(0x42842B00UL))\r
+#define bFM3_USB0_EP4S_SIZE41                  *((volatile unsigned int*)(0x42842B04UL))\r
+#define bFM3_USB0_EP4S_SIZE42                  *((volatile unsigned int*)(0x42842B08UL))\r
+#define bFM3_USB0_EP4S_SIZE43                  *((volatile unsigned int*)(0x42842B0CUL))\r
+#define bFM3_USB0_EP4S_SIZE44                  *((volatile unsigned int*)(0x42842B10UL))\r
+#define bFM3_USB0_EP4S_SIZE45                  *((volatile unsigned int*)(0x42842B14UL))\r
+#define bFM3_USB0_EP4S_SIZE46                  *((volatile unsigned int*)(0x42842B18UL))\r
+#define bFM3_USB0_EP4S_SPK                     *((volatile unsigned int*)(0x42842B24UL))\r
+#define bFM3_USB0_EP4S_DRQ                     *((volatile unsigned int*)(0x42842B28UL))\r
+#define bFM3_USB0_EP4S_BUSY                    *((volatile unsigned int*)(0x42842B2CUL))\r
+#define bFM3_USB0_EP4S_SPKIE                   *((volatile unsigned int*)(0x42842B34UL))\r
+#define bFM3_USB0_EP4S_DRQIE                   *((volatile unsigned int*)(0x42842B38UL))\r
+#define bFM3_USB0_EP4S_BFINI                   *((volatile unsigned int*)(0x42842B3CUL))\r
+#define bFM3_USB0_EP5S_SIZE50                  *((volatile unsigned int*)(0x42842B80UL))\r
+#define bFM3_USB0_EP5S_SIZE51                  *((volatile unsigned int*)(0x42842B84UL))\r
+#define bFM3_USB0_EP5S_SIZE52                  *((volatile unsigned int*)(0x42842B88UL))\r
+#define bFM3_USB0_EP5S_SIZE53                  *((volatile unsigned int*)(0x42842B8CUL))\r
+#define bFM3_USB0_EP5S_SIZE54                  *((volatile unsigned int*)(0x42842B90UL))\r
+#define bFM3_USB0_EP5S_SIZE55                  *((volatile unsigned int*)(0x42842B94UL))\r
+#define bFM3_USB0_EP5S_SIZE56                  *((volatile unsigned int*)(0x42842B98UL))\r
+#define bFM3_USB0_EP5S_SPK                     *((volatile unsigned int*)(0x42842BA4UL))\r
+#define bFM3_USB0_EP5S_DRQ                     *((volatile unsigned int*)(0x42842BA8UL))\r
+#define bFM3_USB0_EP5S_BUSY                    *((volatile unsigned int*)(0x42842BACUL))\r
+#define bFM3_USB0_EP5S_SPKIE                   *((volatile unsigned int*)(0x42842BB4UL))\r
+#define bFM3_USB0_EP5S_DRQIE                   *((volatile unsigned int*)(0x42842BB8UL))\r
+#define bFM3_USB0_EP5S_BFINI                   *((volatile unsigned int*)(0x42842BBCUL))\r
+\r
+/* DMA controller */\r
+#define bFM3_DMAC_DMACR_DH0                    *((volatile unsigned int*)(0x42C00060UL))\r
+#define bFM3_DMAC_DMACR_DH1                    *((volatile unsigned int*)(0x42C00064UL))\r
+#define bFM3_DMAC_DMACR_DH2                    *((volatile unsigned int*)(0x42C00068UL))\r
+#define bFM3_DMAC_DMACR_DH3                    *((volatile unsigned int*)(0x42C0006CUL))\r
+#define bFM3_DMAC_DMACR_PR                     *((volatile unsigned int*)(0x42C00070UL))\r
+#define bFM3_DMAC_DMACR_DS                     *((volatile unsigned int*)(0x42C00078UL))\r
+#define bFM3_DMAC_DMACR_DE                     *((volatile unsigned int*)(0x42C0007CUL))\r
+#define bFM3_DMAC_DMACA0_TC0                   *((volatile unsigned int*)(0x42C00200UL))\r
+#define bFM3_DMAC_DMACA0_TC1                   *((volatile unsigned int*)(0x42C00204UL))\r
+#define bFM3_DMAC_DMACA0_TC2                   *((volatile unsigned int*)(0x42C00208UL))\r
+#define bFM3_DMAC_DMACA0_TC3                   *((volatile unsigned int*)(0x42C0020CUL))\r
+#define bFM3_DMAC_DMACA0_TC4                   *((volatile unsigned int*)(0x42C00210UL))\r
+#define bFM3_DMAC_DMACA0_TC5                   *((volatile unsigned int*)(0x42C00214UL))\r
+#define bFM3_DMAC_DMACA0_TC6                   *((volatile unsigned int*)(0x42C00218UL))\r
+#define bFM3_DMAC_DMACA0_TC7                   *((volatile unsigned int*)(0x42C0021CUL))\r
+#define bFM3_DMAC_DMACA0_TC8                   *((volatile unsigned int*)(0x42C00220UL))\r
+#define bFM3_DMAC_DMACA0_TC9                   *((volatile unsigned int*)(0x42C00224UL))\r
+#define bFM3_DMAC_DMACA0_TC10                  *((volatile unsigned int*)(0x42C00228UL))\r
+#define bFM3_DMAC_DMACA0_TC11                  *((volatile unsigned int*)(0x42C0022CUL))\r
+#define bFM3_DMAC_DMACA0_TC12                  *((volatile unsigned int*)(0x42C00230UL))\r
+#define bFM3_DMAC_DMACA0_TC13                  *((volatile unsigned int*)(0x42C00234UL))\r
+#define bFM3_DMAC_DMACA0_TC14                  *((volatile unsigned int*)(0x42C00238UL))\r
+#define bFM3_DMAC_DMACA0_TC15                  *((volatile unsigned int*)(0x42C0023CUL))\r
+#define bFM3_DMAC_DMACA0_BC0                   *((volatile unsigned int*)(0x42C00240UL))\r
+#define bFM3_DMAC_DMACA0_BC1                   *((volatile unsigned int*)(0x42C00244UL))\r
+#define bFM3_DMAC_DMACA0_BC2                   *((volatile unsigned int*)(0x42C00248UL))\r
+#define bFM3_DMAC_DMACA0_BC3                   *((volatile unsigned int*)(0x42C0024CUL))\r
+#define bFM3_DMAC_DMACA0_IS0                   *((volatile unsigned int*)(0x42C0025CUL))\r
+#define bFM3_DMAC_DMACA0_IS1                   *((volatile unsigned int*)(0x42C00260UL))\r
+#define bFM3_DMAC_DMACA0_IS2                   *((volatile unsigned int*)(0x42C00264UL))\r
+#define bFM3_DMAC_DMACA0_IS3                   *((volatile unsigned int*)(0x42C00268UL))\r
+#define bFM3_DMAC_DMACA0_IS4                   *((volatile unsigned int*)(0x42C0026CUL))\r
+#define bFM3_DMAC_DMACA0_IS5                   *((volatile unsigned int*)(0x42C00270UL))\r
+#define bFM3_DMAC_DMACA0_ST                    *((volatile unsigned int*)(0x42C00274UL))\r
+#define bFM3_DMAC_DMACA0_PB                    *((volatile unsigned int*)(0x42C00278UL))\r
+#define bFM3_DMAC_DMACA0_EB                    *((volatile unsigned int*)(0x42C0027CUL))\r
+#define bFM3_DMAC_DMACB0_EM                    *((volatile unsigned int*)(0x42C00280UL))\r
+#define bFM3_DMAC_DMACB0_SS0                   *((volatile unsigned int*)(0x42C002C0UL))\r
+#define bFM3_DMAC_DMACB0_SS1                   *((volatile unsigned int*)(0x42C002C4UL))\r
+#define bFM3_DMAC_DMACB0_SS2                   *((volatile unsigned int*)(0x42C002C8UL))\r
+#define bFM3_DMAC_DMACB0_CI                    *((volatile unsigned int*)(0x42C002CCUL))\r
+#define bFM3_DMAC_DMACB0_EI                    *((volatile unsigned int*)(0x42C002D0UL))\r
+#define bFM3_DMAC_DMACB0_RD                    *((volatile unsigned int*)(0x42C002D4UL))\r
+#define bFM3_DMAC_DMACB0_RS                    *((volatile unsigned int*)(0x42C002D8UL))\r
+#define bFM3_DMAC_DMACB0_RC                    *((volatile unsigned int*)(0x42C002DCUL))\r
+#define bFM3_DMAC_DMACB0_FD                    *((volatile unsigned int*)(0x42C002E0UL))\r
+#define bFM3_DMAC_DMACB0_FS                    *((volatile unsigned int*)(0x42C002E4UL))\r
+#define bFM3_DMAC_DMACB0_TW0                   *((volatile unsigned int*)(0x42C002E8UL))\r
+#define bFM3_DMAC_DMACB0_TW1                   *((volatile unsigned int*)(0x42C002ECUL))\r
+#define bFM3_DMAC_DMACB0_MS0                   *((volatile unsigned int*)(0x42C002F0UL))\r
+#define bFM3_DMAC_DMACB0_MS1                   *((volatile unsigned int*)(0x42C002F4UL))\r
+#define bFM3_DMAC_DMACA1_TC0                   *((volatile unsigned int*)(0x42C00400UL))\r
+#define bFM3_DMAC_DMACA1_TC1                   *((volatile unsigned int*)(0x42C00404UL))\r
+#define bFM3_DMAC_DMACA1_TC2                   *((volatile unsigned int*)(0x42C00408UL))\r
+#define bFM3_DMAC_DMACA1_TC3                   *((volatile unsigned int*)(0x42C0040CUL))\r
+#define bFM3_DMAC_DMACA1_TC4                   *((volatile unsigned int*)(0x42C00410UL))\r
+#define bFM3_DMAC_DMACA1_TC5                   *((volatile unsigned int*)(0x42C00414UL))\r
+#define bFM3_DMAC_DMACA1_TC6                   *((volatile unsigned int*)(0x42C00418UL))\r
+#define bFM3_DMAC_DMACA1_TC7                   *((volatile unsigned int*)(0x42C0041CUL))\r
+#define bFM3_DMAC_DMACA1_TC8                   *((volatile unsigned int*)(0x42C00420UL))\r
+#define bFM3_DMAC_DMACA1_TC9                   *((volatile unsigned int*)(0x42C00424UL))\r
+#define bFM3_DMAC_DMACA1_TC10                  *((volatile unsigned int*)(0x42C00428UL))\r
+#define bFM3_DMAC_DMACA1_TC11                  *((volatile unsigned int*)(0x42C0042CUL))\r
+#define bFM3_DMAC_DMACA1_TC12                  *((volatile unsigned int*)(0x42C00430UL))\r
+#define bFM3_DMAC_DMACA1_TC13                  *((volatile unsigned int*)(0x42C00434UL))\r
+#define bFM3_DMAC_DMACA1_TC14                  *((volatile unsigned int*)(0x42C00438UL))\r
+#define bFM3_DMAC_DMACA1_TC15                  *((volatile unsigned int*)(0x42C0043CUL))\r
+#define bFM3_DMAC_DMACA1_BC0                   *((volatile unsigned int*)(0x42C00440UL))\r
+#define bFM3_DMAC_DMACA1_BC1                   *((volatile unsigned int*)(0x42C00444UL))\r
+#define bFM3_DMAC_DMACA1_BC2                   *((volatile unsigned int*)(0x42C00448UL))\r
+#define bFM3_DMAC_DMACA1_BC3                   *((volatile unsigned int*)(0x42C0044CUL))\r
+#define bFM3_DMAC_DMACA1_IS0                   *((volatile unsigned int*)(0x42C0045CUL))\r
+#define bFM3_DMAC_DMACA1_IS1                   *((volatile unsigned int*)(0x42C00460UL))\r
+#define bFM3_DMAC_DMACA1_IS2                   *((volatile unsigned int*)(0x42C00464UL))\r
+#define bFM3_DMAC_DMACA1_IS3                   *((volatile unsigned int*)(0x42C00468UL))\r
+#define bFM3_DMAC_DMACA1_IS4                   *((volatile unsigned int*)(0x42C0046CUL))\r
+#define bFM3_DMAC_DMACA1_IS5                   *((volatile unsigned int*)(0x42C00470UL))\r
+#define bFM3_DMAC_DMACA1_ST                    *((volatile unsigned int*)(0x42C00474UL))\r
+#define bFM3_DMAC_DMACA1_PB                    *((volatile unsigned int*)(0x42C00478UL))\r
+#define bFM3_DMAC_DMACA1_EB                    *((volatile unsigned int*)(0x42C0047CUL))\r
+#define bFM3_DMAC_DMACB1_EM                    *((volatile unsigned int*)(0x42C00480UL))\r
+#define bFM3_DMAC_DMACB1_SS0                   *((volatile unsigned int*)(0x42C004C0UL))\r
+#define bFM3_DMAC_DMACB1_SS1                   *((volatile unsigned int*)(0x42C004C4UL))\r
+#define bFM3_DMAC_DMACB1_SS2                   *((volatile unsigned int*)(0x42C004C8UL))\r
+#define bFM3_DMAC_DMACB1_CI                    *((volatile unsigned int*)(0x42C004CCUL))\r
+#define bFM3_DMAC_DMACB1_EI                    *((volatile unsigned int*)(0x42C004D0UL))\r
+#define bFM3_DMAC_DMACB1_RD                    *((volatile unsigned int*)(0x42C004D4UL))\r
+#define bFM3_DMAC_DMACB1_RS                    *((volatile unsigned int*)(0x42C004D8UL))\r
+#define bFM3_DMAC_DMACB1_RC                    *((volatile unsigned int*)(0x42C004DCUL))\r
+#define bFM3_DMAC_DMACB1_FD                    *((volatile unsigned int*)(0x42C004E0UL))\r
+#define bFM3_DMAC_DMACB1_FS                    *((volatile unsigned int*)(0x42C004E4UL))\r
+#define bFM3_DMAC_DMACB1_TW0                   *((volatile unsigned int*)(0x42C004E8UL))\r
+#define bFM3_DMAC_DMACB1_TW1                   *((volatile unsigned int*)(0x42C004ECUL))\r
+#define bFM3_DMAC_DMACB1_MS0                   *((volatile unsigned int*)(0x42C004F0UL))\r
+#define bFM3_DMAC_DMACB1_MS1                   *((volatile unsigned int*)(0x42C004F4UL))\r
+#define bFM3_DMAC_DMACA2_TC0                   *((volatile unsigned int*)(0x42C00600UL))\r
+#define bFM3_DMAC_DMACA2_TC1                   *((volatile unsigned int*)(0x42C00604UL))\r
+#define bFM3_DMAC_DMACA2_TC2                   *((volatile unsigned int*)(0x42C00608UL))\r
+#define bFM3_DMAC_DMACA2_TC3                   *((volatile unsigned int*)(0x42C0060CUL))\r
+#define bFM3_DMAC_DMACA2_TC4                   *((volatile unsigned int*)(0x42C00610UL))\r
+#define bFM3_DMAC_DMACA2_TC5                   *((volatile unsigned int*)(0x42C00614UL))\r
+#define bFM3_DMAC_DMACA2_TC6                   *((volatile unsigned int*)(0x42C00618UL))\r
+#define bFM3_DMAC_DMACA2_TC7                   *((volatile unsigned int*)(0x42C0061CUL))\r
+#define bFM3_DMAC_DMACA2_TC8                   *((volatile unsigned int*)(0x42C00620UL))\r
+#define bFM3_DMAC_DMACA2_TC9                   *((volatile unsigned int*)(0x42C00624UL))\r
+#define bFM3_DMAC_DMACA2_TC10                  *((volatile unsigned int*)(0x42C00628UL))\r
+#define bFM3_DMAC_DMACA2_TC11                  *((volatile unsigned int*)(0x42C0062CUL))\r
+#define bFM3_DMAC_DMACA2_TC12                  *((volatile unsigned int*)(0x42C00630UL))\r
+#define bFM3_DMAC_DMACA2_TC13                  *((volatile unsigned int*)(0x42C00634UL))\r
+#define bFM3_DMAC_DMACA2_TC14                  *((volatile unsigned int*)(0x42C00638UL))\r
+#define bFM3_DMAC_DMACA2_TC15                  *((volatile unsigned int*)(0x42C0063CUL))\r
+#define bFM3_DMAC_DMACA2_BC0                   *((volatile unsigned int*)(0x42C00640UL))\r
+#define bFM3_DMAC_DMACA2_BC1                   *((volatile unsigned int*)(0x42C00644UL))\r
+#define bFM3_DMAC_DMACA2_BC2                   *((volatile unsigned int*)(0x42C00648UL))\r
+#define bFM3_DMAC_DMACA2_BC3                   *((volatile unsigned int*)(0x42C0064CUL))\r
+#define bFM3_DMAC_DMACA2_IS0                   *((volatile unsigned int*)(0x42C0065CUL))\r
+#define bFM3_DMAC_DMACA2_IS1                   *((volatile unsigned int*)(0x42C00660UL))\r
+#define bFM3_DMAC_DMACA2_IS2                   *((volatile unsigned int*)(0x42C00664UL))\r
+#define bFM3_DMAC_DMACA2_IS3                   *((volatile unsigned int*)(0x42C00668UL))\r
+#define bFM3_DMAC_DMACA2_IS4                   *((volatile unsigned int*)(0x42C0066CUL))\r
+#define bFM3_DMAC_DMACA2_IS5                   *((volatile unsigned int*)(0x42C00670UL))\r
+#define bFM3_DMAC_DMACA2_ST                    *((volatile unsigned int*)(0x42C00674UL))\r
+#define bFM3_DMAC_DMACA2_PB                    *((volatile unsigned int*)(0x42C00678UL))\r
+#define bFM3_DMAC_DMACA2_EB                    *((volatile unsigned int*)(0x42C0067CUL))\r
+#define bFM3_DMAC_DMACB2_EM                    *((volatile unsigned int*)(0x42C00680UL))\r
+#define bFM3_DMAC_DMACB2_SS0                   *((volatile unsigned int*)(0x42C006C0UL))\r
+#define bFM3_DMAC_DMACB2_SS1                   *((volatile unsigned int*)(0x42C006C4UL))\r
+#define bFM3_DMAC_DMACB2_SS2                   *((volatile unsigned int*)(0x42C006C8UL))\r
+#define bFM3_DMAC_DMACB2_CI                    *((volatile unsigned int*)(0x42C006CCUL))\r
+#define bFM3_DMAC_DMACB2_EI                    *((volatile unsigned int*)(0x42C006D0UL))\r
+#define bFM3_DMAC_DMACB2_RD                    *((volatile unsigned int*)(0x42C006D4UL))\r
+#define bFM3_DMAC_DMACB2_RS                    *((volatile unsigned int*)(0x42C006D8UL))\r
+#define bFM3_DMAC_DMACB2_RC                    *((volatile unsigned int*)(0x42C006DCUL))\r
+#define bFM3_DMAC_DMACB2_FD                    *((volatile unsigned int*)(0x42C006E0UL))\r
+#define bFM3_DMAC_DMACB2_FS                    *((volatile unsigned int*)(0x42C006E4UL))\r
+#define bFM3_DMAC_DMACB2_TW0                   *((volatile unsigned int*)(0x42C006E8UL))\r
+#define bFM3_DMAC_DMACB2_TW1                   *((volatile unsigned int*)(0x42C006ECUL))\r
+#define bFM3_DMAC_DMACB2_MS0                   *((volatile unsigned int*)(0x42C006F0UL))\r
+#define bFM3_DMAC_DMACB2_MS1                   *((volatile unsigned int*)(0x42C006F4UL))\r
+#define bFM3_DMAC_DMACA3_TC0                   *((volatile unsigned int*)(0x42C00800UL))\r
+#define bFM3_DMAC_DMACA3_TC1                   *((volatile unsigned int*)(0x42C00804UL))\r
+#define bFM3_DMAC_DMACA3_TC2                   *((volatile unsigned int*)(0x42C00808UL))\r
+#define bFM3_DMAC_DMACA3_TC3                   *((volatile unsigned int*)(0x42C0080CUL))\r
+#define bFM3_DMAC_DMACA3_TC4                   *((volatile unsigned int*)(0x42C00810UL))\r
+#define bFM3_DMAC_DMACA3_TC5                   *((volatile unsigned int*)(0x42C00814UL))\r
+#define bFM3_DMAC_DMACA3_TC6                   *((volatile unsigned int*)(0x42C00818UL))\r
+#define bFM3_DMAC_DMACA3_TC7                   *((volatile unsigned int*)(0x42C0081CUL))\r
+#define bFM3_DMAC_DMACA3_TC8                   *((volatile unsigned int*)(0x42C00820UL))\r
+#define bFM3_DMAC_DMACA3_TC9                   *((volatile unsigned int*)(0x42C00824UL))\r
+#define bFM3_DMAC_DMACA3_TC10                  *((volatile unsigned int*)(0x42C00828UL))\r
+#define bFM3_DMAC_DMACA3_TC11                  *((volatile unsigned int*)(0x42C0082CUL))\r
+#define bFM3_DMAC_DMACA3_TC12                  *((volatile unsigned int*)(0x42C00830UL))\r
+#define bFM3_DMAC_DMACA3_TC13                  *((volatile unsigned int*)(0x42C00834UL))\r
+#define bFM3_DMAC_DMACA3_TC14                  *((volatile unsigned int*)(0x42C00838UL))\r
+#define bFM3_DMAC_DMACA3_TC15                  *((volatile unsigned int*)(0x42C0083CUL))\r
+#define bFM3_DMAC_DMACA3_BC0                   *((volatile unsigned int*)(0x42C00840UL))\r
+#define bFM3_DMAC_DMACA3_BC1                   *((volatile unsigned int*)(0x42C00844UL))\r
+#define bFM3_DMAC_DMACA3_BC2                   *((volatile unsigned int*)(0x42C00848UL))\r
+#define bFM3_DMAC_DMACA3_BC3                   *((volatile unsigned int*)(0x42C0084CUL))\r
+#define bFM3_DMAC_DMACA3_IS0                   *((volatile unsigned int*)(0x42C0085CUL))\r
+#define bFM3_DMAC_DMACA3_IS1                   *((volatile unsigned int*)(0x42C00860UL))\r
+#define bFM3_DMAC_DMACA3_IS2                   *((volatile unsigned int*)(0x42C00864UL))\r
+#define bFM3_DMAC_DMACA3_IS3                   *((volatile unsigned int*)(0x42C00868UL))\r
+#define bFM3_DMAC_DMACA3_IS4                   *((volatile unsigned int*)(0x42C0086CUL))\r
+#define bFM3_DMAC_DMACA3_IS5                   *((volatile unsigned int*)(0x42C00870UL))\r
+#define bFM3_DMAC_DMACA3_ST                    *((volatile unsigned int*)(0x42C00874UL))\r
+#define bFM3_DMAC_DMACA3_PB                    *((volatile unsigned int*)(0x42C00878UL))\r
+#define bFM3_DMAC_DMACA3_EB                    *((volatile unsigned int*)(0x42C0087CUL))\r
+#define bFM3_DMAC_DMACB3_EM                    *((volatile unsigned int*)(0x42C00880UL))\r
+#define bFM3_DMAC_DMACB3_SS0                   *((volatile unsigned int*)(0x42C008C0UL))\r
+#define bFM3_DMAC_DMACB3_SS1                   *((volatile unsigned int*)(0x42C008C4UL))\r
+#define bFM3_DMAC_DMACB3_SS2                   *((volatile unsigned int*)(0x42C008C8UL))\r
+#define bFM3_DMAC_DMACB3_CI                    *((volatile unsigned int*)(0x42C008CCUL))\r
+#define bFM3_DMAC_DMACB3_EI                    *((volatile unsigned int*)(0x42C008D0UL))\r
+#define bFM3_DMAC_DMACB3_RD                    *((volatile unsigned int*)(0x42C008D4UL))\r
+#define bFM3_DMAC_DMACB3_RS                    *((volatile unsigned int*)(0x42C008D8UL))\r
+#define bFM3_DMAC_DMACB3_RC                    *((volatile unsigned int*)(0x42C008DCUL))\r
+#define bFM3_DMAC_DMACB3_FD                    *((volatile unsigned int*)(0x42C008E0UL))\r
+#define bFM3_DMAC_DMACB3_FS                    *((volatile unsigned int*)(0x42C008E4UL))\r
+#define bFM3_DMAC_DMACB3_TW0                   *((volatile unsigned int*)(0x42C008E8UL))\r
+#define bFM3_DMAC_DMACB3_TW1                   *((volatile unsigned int*)(0x42C008ECUL))\r
+#define bFM3_DMAC_DMACB3_MS0                   *((volatile unsigned int*)(0x42C008F0UL))\r
+#define bFM3_DMAC_DMACB3_MS1                   *((volatile unsigned int*)(0x42C008F4UL))\r
+#define bFM3_DMAC_DMACA4_TC0                   *((volatile unsigned int*)(0x42C00A00UL))\r
+#define bFM3_DMAC_DMACA4_TC1                   *((volatile unsigned int*)(0x42C00A04UL))\r
+#define bFM3_DMAC_DMACA4_TC2                   *((volatile unsigned int*)(0x42C00A08UL))\r
+#define bFM3_DMAC_DMACA4_TC3                   *((volatile unsigned int*)(0x42C00A0CUL))\r
+#define bFM3_DMAC_DMACA4_TC4                   *((volatile unsigned int*)(0x42C00A10UL))\r
+#define bFM3_DMAC_DMACA4_TC5                   *((volatile unsigned int*)(0x42C00A14UL))\r
+#define bFM3_DMAC_DMACA4_TC6                   *((volatile unsigned int*)(0x42C00A18UL))\r
+#define bFM3_DMAC_DMACA4_TC7                   *((volatile unsigned int*)(0x42C00A1CUL))\r
+#define bFM3_DMAC_DMACA4_TC8                   *((volatile unsigned int*)(0x42C00A20UL))\r
+#define bFM3_DMAC_DMACA4_TC9                   *((volatile unsigned int*)(0x42C00A24UL))\r
+#define bFM3_DMAC_DMACA4_TC10                  *((volatile unsigned int*)(0x42C00A28UL))\r
+#define bFM3_DMAC_DMACA4_TC11                  *((volatile unsigned int*)(0x42C00A2CUL))\r
+#define bFM3_DMAC_DMACA4_TC12                  *((volatile unsigned int*)(0x42C00A30UL))\r
+#define bFM3_DMAC_DMACA4_TC13                  *((volatile unsigned int*)(0x42C00A34UL))\r
+#define bFM3_DMAC_DMACA4_TC14                  *((volatile unsigned int*)(0x42C00A38UL))\r
+#define bFM3_DMAC_DMACA4_TC15                  *((volatile unsigned int*)(0x42C00A3CUL))\r
+#define bFM3_DMAC_DMACA4_BC0                   *((volatile unsigned int*)(0x42C00A40UL))\r
+#define bFM3_DMAC_DMACA4_BC1                   *((volatile unsigned int*)(0x42C00A44UL))\r
+#define bFM3_DMAC_DMACA4_BC2                   *((volatile unsigned int*)(0x42C00A48UL))\r
+#define bFM3_DMAC_DMACA4_BC3                   *((volatile unsigned int*)(0x42C00A4CUL))\r
+#define bFM3_DMAC_DMACA4_IS0                   *((volatile unsigned int*)(0x42C00A5CUL))\r
+#define bFM3_DMAC_DMACA4_IS1                   *((volatile unsigned int*)(0x42C00A60UL))\r
+#define bFM3_DMAC_DMACA4_IS2                   *((volatile unsigned int*)(0x42C00A64UL))\r
+#define bFM3_DMAC_DMACA4_IS3                   *((volatile unsigned int*)(0x42C00A68UL))\r
+#define bFM3_DMAC_DMACA4_IS4                   *((volatile unsigned int*)(0x42C00A6CUL))\r
+#define bFM3_DMAC_DMACA4_IS5                   *((volatile unsigned int*)(0x42C00A70UL))\r
+#define bFM3_DMAC_DMACA4_ST                    *((volatile unsigned int*)(0x42C00A74UL))\r
+#define bFM3_DMAC_DMACA4_PB                    *((volatile unsigned int*)(0x42C00A78UL))\r
+#define bFM3_DMAC_DMACA4_EB                    *((volatile unsigned int*)(0x42C00A7CUL))\r
+#define bFM3_DMAC_DMACB4_EM                    *((volatile unsigned int*)(0x42C00A80UL))\r
+#define bFM3_DMAC_DMACB4_SS0                   *((volatile unsigned int*)(0x42C00AC0UL))\r
+#define bFM3_DMAC_DMACB4_SS1                   *((volatile unsigned int*)(0x42C00AC4UL))\r
+#define bFM3_DMAC_DMACB4_SS2                   *((volatile unsigned int*)(0x42C00AC8UL))\r
+#define bFM3_DMAC_DMACB4_CI                    *((volatile unsigned int*)(0x42C00ACCUL))\r
+#define bFM3_DMAC_DMACB4_EI                    *((volatile unsigned int*)(0x42C00AD0UL))\r
+#define bFM3_DMAC_DMACB4_RD                    *((volatile unsigned int*)(0x42C00AD4UL))\r
+#define bFM3_DMAC_DMACB4_RS                    *((volatile unsigned int*)(0x42C00AD8UL))\r
+#define bFM3_DMAC_DMACB4_RC                    *((volatile unsigned int*)(0x42C00ADCUL))\r
+#define bFM3_DMAC_DMACB4_FD                    *((volatile unsigned int*)(0x42C00AE0UL))\r
+#define bFM3_DMAC_DMACB4_FS                    *((volatile unsigned int*)(0x42C00AE4UL))\r
+#define bFM3_DMAC_DMACB4_TW0                   *((volatile unsigned int*)(0x42C00AE8UL))\r
+#define bFM3_DMAC_DMACB4_TW1                   *((volatile unsigned int*)(0x42C00AECUL))\r
+#define bFM3_DMAC_DMACB4_MS0                   *((volatile unsigned int*)(0x42C00AF0UL))\r
+#define bFM3_DMAC_DMACB4_MS1                   *((volatile unsigned int*)(0x42C00AF4UL))\r
+#define bFM3_DMAC_DMACA5_TC0                   *((volatile unsigned int*)(0x42C00C00UL))\r
+#define bFM3_DMAC_DMACA5_TC1                   *((volatile unsigned int*)(0x42C00C04UL))\r
+#define bFM3_DMAC_DMACA5_TC2                   *((volatile unsigned int*)(0x42C00C08UL))\r
+#define bFM3_DMAC_DMACA5_TC3                   *((volatile unsigned int*)(0x42C00C0CUL))\r
+#define bFM3_DMAC_DMACA5_TC4                   *((volatile unsigned int*)(0x42C00C10UL))\r
+#define bFM3_DMAC_DMACA5_TC5                   *((volatile unsigned int*)(0x42C00C14UL))\r
+#define bFM3_DMAC_DMACA5_TC6                   *((volatile unsigned int*)(0x42C00C18UL))\r
+#define bFM3_DMAC_DMACA5_TC7                   *((volatile unsigned int*)(0x42C00C1CUL))\r
+#define bFM3_DMAC_DMACA5_TC8                   *((volatile unsigned int*)(0x42C00C20UL))\r
+#define bFM3_DMAC_DMACA5_TC9                   *((volatile unsigned int*)(0x42C00C24UL))\r
+#define bFM3_DMAC_DMACA5_TC10                  *((volatile unsigned int*)(0x42C00C28UL))\r
+#define bFM3_DMAC_DMACA5_TC11                  *((volatile unsigned int*)(0x42C00C2CUL))\r
+#define bFM3_DMAC_DMACA5_TC12                  *((volatile unsigned int*)(0x42C00C30UL))\r
+#define bFM3_DMAC_DMACA5_TC13                  *((volatile unsigned int*)(0x42C00C34UL))\r
+#define bFM3_DMAC_DMACA5_TC14                  *((volatile unsigned int*)(0x42C00C38UL))\r
+#define bFM3_DMAC_DMACA5_TC15                  *((volatile unsigned int*)(0x42C00C3CUL))\r
+#define bFM3_DMAC_DMACA5_BC0                   *((volatile unsigned int*)(0x42C00C40UL))\r
+#define bFM3_DMAC_DMACA5_BC1                   *((volatile unsigned int*)(0x42C00C44UL))\r
+#define bFM3_DMAC_DMACA5_BC2                   *((volatile unsigned int*)(0x42C00C48UL))\r
+#define bFM3_DMAC_DMACA5_BC3                   *((volatile unsigned int*)(0x42C00C4CUL))\r
+#define bFM3_DMAC_DMACA5_IS0                   *((volatile unsigned int*)(0x42C00C5CUL))\r
+#define bFM3_DMAC_DMACA5_IS1                   *((volatile unsigned int*)(0x42C00C60UL))\r
+#define bFM3_DMAC_DMACA5_IS2                   *((volatile unsigned int*)(0x42C00C64UL))\r
+#define bFM3_DMAC_DMACA5_IS3                   *((volatile unsigned int*)(0x42C00C68UL))\r
+#define bFM3_DMAC_DMACA5_IS4                   *((volatile unsigned int*)(0x42C00C6CUL))\r
+#define bFM3_DMAC_DMACA5_IS5                   *((volatile unsigned int*)(0x42C00C70UL))\r
+#define bFM3_DMAC_DMACA5_ST                    *((volatile unsigned int*)(0x42C00C74UL))\r
+#define bFM3_DMAC_DMACA5_PB                    *((volatile unsigned int*)(0x42C00C78UL))\r
+#define bFM3_DMAC_DMACA5_EB                    *((volatile unsigned int*)(0x42C00C7CUL))\r
+#define bFM3_DMAC_DMACB5_EM                    *((volatile unsigned int*)(0x42C00C80UL))\r
+#define bFM3_DMAC_DMACB5_SS0                   *((volatile unsigned int*)(0x42C00CC0UL))\r
+#define bFM3_DMAC_DMACB5_SS1                   *((volatile unsigned int*)(0x42C00CC4UL))\r
+#define bFM3_DMAC_DMACB5_SS2                   *((volatile unsigned int*)(0x42C00CC8UL))\r
+#define bFM3_DMAC_DMACB5_CI                    *((volatile unsigned int*)(0x42C00CCCUL))\r
+#define bFM3_DMAC_DMACB5_EI                    *((volatile unsigned int*)(0x42C00CD0UL))\r
+#define bFM3_DMAC_DMACB5_RD                    *((volatile unsigned int*)(0x42C00CD4UL))\r
+#define bFM3_DMAC_DMACB5_RS                    *((volatile unsigned int*)(0x42C00CD8UL))\r
+#define bFM3_DMAC_DMACB5_RC                    *((volatile unsigned int*)(0x42C00CDCUL))\r
+#define bFM3_DMAC_DMACB5_FD                    *((volatile unsigned int*)(0x42C00CE0UL))\r
+#define bFM3_DMAC_DMACB5_FS                    *((volatile unsigned int*)(0x42C00CE4UL))\r
+#define bFM3_DMAC_DMACB5_TW0                   *((volatile unsigned int*)(0x42C00CE8UL))\r
+#define bFM3_DMAC_DMACB5_TW1                   *((volatile unsigned int*)(0x42C00CECUL))\r
+#define bFM3_DMAC_DMACB5_MS0                   *((volatile unsigned int*)(0x42C00CF0UL))\r
+#define bFM3_DMAC_DMACB5_MS1                   *((volatile unsigned int*)(0x42C00CF4UL))\r
+#define bFM3_DMAC_DMACA6_TC0                   *((volatile unsigned int*)(0x42C00E00UL))\r
+#define bFM3_DMAC_DMACA6_TC1                   *((volatile unsigned int*)(0x42C00E04UL))\r
+#define bFM3_DMAC_DMACA6_TC2                   *((volatile unsigned int*)(0x42C00E08UL))\r
+#define bFM3_DMAC_DMACA6_TC3                   *((volatile unsigned int*)(0x42C00E0CUL))\r
+#define bFM3_DMAC_DMACA6_TC4                   *((volatile unsigned int*)(0x42C00E10UL))\r
+#define bFM3_DMAC_DMACA6_TC5                   *((volatile unsigned int*)(0x42C00E14UL))\r
+#define bFM3_DMAC_DMACA6_TC6                   *((volatile unsigned int*)(0x42C00E18UL))\r
+#define bFM3_DMAC_DMACA6_TC7                   *((volatile unsigned int*)(0x42C00E1CUL))\r
+#define bFM3_DMAC_DMACA6_TC8                   *((volatile unsigned int*)(0x42C00E20UL))\r
+#define bFM3_DMAC_DMACA6_TC9                   *((volatile unsigned int*)(0x42C00E24UL))\r
+#define bFM3_DMAC_DMACA6_TC10                  *((volatile unsigned int*)(0x42C00E28UL))\r
+#define bFM3_DMAC_DMACA6_TC11                  *((volatile unsigned int*)(0x42C00E2CUL))\r
+#define bFM3_DMAC_DMACA6_TC12                  *((volatile unsigned int*)(0x42C00E30UL))\r
+#define bFM3_DMAC_DMACA6_TC13                  *((volatile unsigned int*)(0x42C00E34UL))\r
+#define bFM3_DMAC_DMACA6_TC14                  *((volatile unsigned int*)(0x42C00E38UL))\r
+#define bFM3_DMAC_DMACA6_TC15                  *((volatile unsigned int*)(0x42C00E3CUL))\r
+#define bFM3_DMAC_DMACA6_BC0                   *((volatile unsigned int*)(0x42C00E40UL))\r
+#define bFM3_DMAC_DMACA6_BC1                   *((volatile unsigned int*)(0x42C00E44UL))\r
+#define bFM3_DMAC_DMACA6_BC2                   *((volatile unsigned int*)(0x42C00E48UL))\r
+#define bFM3_DMAC_DMACA6_BC3                   *((volatile unsigned int*)(0x42C00E4CUL))\r
+#define bFM3_DMAC_DMACA6_IS0                   *((volatile unsigned int*)(0x42C00E5CUL))\r
+#define bFM3_DMAC_DMACA6_IS1                   *((volatile unsigned int*)(0x42C00E60UL))\r
+#define bFM3_DMAC_DMACA6_IS2                   *((volatile unsigned int*)(0x42C00E64UL))\r
+#define bFM3_DMAC_DMACA6_IS3                   *((volatile unsigned int*)(0x42C00E68UL))\r
+#define bFM3_DMAC_DMACA6_IS4                   *((volatile unsigned int*)(0x42C00E6CUL))\r
+#define bFM3_DMAC_DMACA6_IS5                   *((volatile unsigned int*)(0x42C00E70UL))\r
+#define bFM3_DMAC_DMACA6_ST                    *((volatile unsigned int*)(0x42C00E74UL))\r
+#define bFM3_DMAC_DMACA6_PB                    *((volatile unsigned int*)(0x42C00E78UL))\r
+#define bFM3_DMAC_DMACA6_EB                    *((volatile unsigned int*)(0x42C00E7CUL))\r
+#define bFM3_DMAC_DMACB6_EM                    *((volatile unsigned int*)(0x42C00E80UL))\r
+#define bFM3_DMAC_DMACB6_SS0                   *((volatile unsigned int*)(0x42C00EC0UL))\r
+#define bFM3_DMAC_DMACB6_SS1                   *((volatile unsigned int*)(0x42C00EC4UL))\r
+#define bFM3_DMAC_DMACB6_SS2                   *((volatile unsigned int*)(0x42C00EC8UL))\r
+#define bFM3_DMAC_DMACB6_CI                    *((volatile unsigned int*)(0x42C00ECCUL))\r
+#define bFM3_DMAC_DMACB6_EI                    *((volatile unsigned int*)(0x42C00ED0UL))\r
+#define bFM3_DMAC_DMACB6_RD                    *((volatile unsigned int*)(0x42C00ED4UL))\r
+#define bFM3_DMAC_DMACB6_RS                    *((volatile unsigned int*)(0x42C00ED8UL))\r
+#define bFM3_DMAC_DMACB6_RC                    *((volatile unsigned int*)(0x42C00EDCUL))\r
+#define bFM3_DMAC_DMACB6_FD                    *((volatile unsigned int*)(0x42C00EE0UL))\r
+#define bFM3_DMAC_DMACB6_FS                    *((volatile unsigned int*)(0x42C00EE4UL))\r
+#define bFM3_DMAC_DMACB6_TW0                   *((volatile unsigned int*)(0x42C00EE8UL))\r
+#define bFM3_DMAC_DMACB6_TW1                   *((volatile unsigned int*)(0x42C00EECUL))\r
+#define bFM3_DMAC_DMACB6_MS0                   *((volatile unsigned int*)(0x42C00EF0UL))\r
+#define bFM3_DMAC_DMACB6_MS1                   *((volatile unsigned int*)(0x42C00EF4UL))\r
+#define bFM3_DMAC_DMACA7_TC0                   *((volatile unsigned int*)(0x42C01000UL))\r
+#define bFM3_DMAC_DMACA7_TC1                   *((volatile unsigned int*)(0x42C01004UL))\r
+#define bFM3_DMAC_DMACA7_TC2                   *((volatile unsigned int*)(0x42C01008UL))\r
+#define bFM3_DMAC_DMACA7_TC3                   *((volatile unsigned int*)(0x42C0100CUL))\r
+#define bFM3_DMAC_DMACA7_TC4                   *((volatile unsigned int*)(0x42C01010UL))\r
+#define bFM3_DMAC_DMACA7_TC5                   *((volatile unsigned int*)(0x42C01014UL))\r
+#define bFM3_DMAC_DMACA7_TC6                   *((volatile unsigned int*)(0x42C01018UL))\r
+#define bFM3_DMAC_DMACA7_TC7                   *((volatile unsigned int*)(0x42C0101CUL))\r
+#define bFM3_DMAC_DMACA7_TC8                   *((volatile unsigned int*)(0x42C01020UL))\r
+#define bFM3_DMAC_DMACA7_TC9                   *((volatile unsigned int*)(0x42C01024UL))\r
+#define bFM3_DMAC_DMACA7_TC10                  *((volatile unsigned int*)(0x42C01028UL))\r
+#define bFM3_DMAC_DMACA7_TC11                  *((volatile unsigned int*)(0x42C0102CUL))\r
+#define bFM3_DMAC_DMACA7_TC12                  *((volatile unsigned int*)(0x42C01030UL))\r
+#define bFM3_DMAC_DMACA7_TC13                  *((volatile unsigned int*)(0x42C01034UL))\r
+#define bFM3_DMAC_DMACA7_TC14                  *((volatile unsigned int*)(0x42C01038UL))\r
+#define bFM3_DMAC_DMACA7_TC15                  *((volatile unsigned int*)(0x42C0103CUL))\r
+#define bFM3_DMAC_DMACA7_BC0                   *((volatile unsigned int*)(0x42C01040UL))\r
+#define bFM3_DMAC_DMACA7_BC1                   *((volatile unsigned int*)(0x42C01044UL))\r
+#define bFM3_DMAC_DMACA7_BC2                   *((volatile unsigned int*)(0x42C01048UL))\r
+#define bFM3_DMAC_DMACA7_BC3                   *((volatile unsigned int*)(0x42C0104CUL))\r
+#define bFM3_DMAC_DMACA7_IS0                   *((volatile unsigned int*)(0x42C0105CUL))\r
+#define bFM3_DMAC_DMACA7_IS1                   *((volatile unsigned int*)(0x42C01060UL))\r
+#define bFM3_DMAC_DMACA7_IS2                   *((volatile unsigned int*)(0x42C01064UL))\r
+#define bFM3_DMAC_DMACA7_IS3                   *((volatile unsigned int*)(0x42C01068UL))\r
+#define bFM3_DMAC_DMACA7_IS4                   *((volatile unsigned int*)(0x42C0106CUL))\r
+#define bFM3_DMAC_DMACA7_IS5                   *((volatile unsigned int*)(0x42C01070UL))\r
+#define bFM3_DMAC_DMACA7_ST                    *((volatile unsigned int*)(0x42C01074UL))\r
+#define bFM3_DMAC_DMACA7_PB                    *((volatile unsigned int*)(0x42C01078UL))\r
+#define bFM3_DMAC_DMACA7_EB                    *((volatile unsigned int*)(0x42C0107CUL))\r
+#define bFM3_DMAC_DMACB7_EM                    *((volatile unsigned int*)(0x42C01080UL))\r
+#define bFM3_DMAC_DMACB7_SS0                   *((volatile unsigned int*)(0x42C010C0UL))\r
+#define bFM3_DMAC_DMACB7_SS1                   *((volatile unsigned int*)(0x42C010C4UL))\r
+#define bFM3_DMAC_DMACB7_SS2                   *((volatile unsigned int*)(0x42C010C8UL))\r
+#define bFM3_DMAC_DMACB7_CI                    *((volatile unsigned int*)(0x42C010CCUL))\r
+#define bFM3_DMAC_DMACB7_EI                    *((volatile unsigned int*)(0x42C010D0UL))\r
+#define bFM3_DMAC_DMACB7_RD                    *((volatile unsigned int*)(0x42C010D4UL))\r
+#define bFM3_DMAC_DMACB7_RS                    *((volatile unsigned int*)(0x42C010D8UL))\r
+#define bFM3_DMAC_DMACB7_RC                    *((volatile unsigned int*)(0x42C010DCUL))\r
+#define bFM3_DMAC_DMACB7_FD                    *((volatile unsigned int*)(0x42C010E0UL))\r
+#define bFM3_DMAC_DMACB7_FS                    *((volatile unsigned int*)(0x42C010E4UL))\r
+#define bFM3_DMAC_DMACB7_TW0                   *((volatile unsigned int*)(0x42C010E8UL))\r
+#define bFM3_DMAC_DMACB7_TW1                   *((volatile unsigned int*)(0x42C010ECUL))\r
+#define bFM3_DMAC_DMACB7_MS0                   *((volatile unsigned int*)(0x42C010F0UL))\r
+#define bFM3_DMAC_DMACB7_MS1                   *((volatile unsigned int*)(0x42C010F4UL))\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* _MB9AF314L_H_ */\r
+\r

diff --git a/Demo/CORTEX_MB9A310_IAR_Keil/Fujitu_source/mcu.h b/Demo/CORTEX_MB9A310_IAR_Keil/Fujitu_source/mcu.h
new file mode 100644 (file)
index 0000000..2194d68
--- /dev/null
+++ b/Demo/CORTEX_MB9A310_IAR_Keil/Fujitu_source/mcu.h
@@ -0,0 +1,62 @@
+/************************************************************************/\r
+/*               (C) Fujitsu Semiconductor Europe GmbH (FSEU)           */\r
+/*                                                                      */\r
+/* The following software deliverable is intended for and must only be  */\r
+/* used for reference and in an evaluation laboratory environment.      */\r
+/* It is provided on an as-is basis without charge and is subject to    */\r
+/* alterations.                                                         */\r
+/* It is the user's obligation to fully test the software in its        */\r
+/* environment and to ensure proper functionality, qualification and    */\r
+/* compliance with component specifications.                            */\r
+/*                                                                      */\r
+/* In the event the software deliverable includes the use of open       */\r
+/* source components, the provisions of the governing open source       */\r
+/* license agreement shall apply with respect to such software          */\r
+/* deliverable.                                                         */\r
+/* FSEU does not warrant that the deliverables do not infringe any      */\r
+/* third party intellectual property right (IPR). In the event that     */\r
+/* the deliverables infringe a third party IPR it is the sole           */\r
+/* responsibility of the customer to obtain necessary licenses to       */\r
+/* continue the usage of the deliverable.                               */\r
+/*                                                                      */\r
+/* To the maximum extent permitted by applicable law FSEU disclaims all */\r
+/* warranties, whether express or implied, in particular, but not       */\r
+/* limited to, warranties of merchantability and fitness for a          */\r
+/* particular purpose for which the deliverable is not designated.      */\r
+/*                                                                      */\r
+/* To the maximum extent permitted by applicable law, FSEU's liability  */\r
+/* is restricted to intentional misconduct and gross negligence.        */\r
+/* FSEU is not liable for consequential damages.                        */\r
+/*                                                                      */\r
+/* (V1.5)                                                               */\r
+/************************************************************************/\r
+/**\r
+ ******************************************************************************\r
+ ** \file   mcu.h\r
+ **\r
+ ** Header File for device dependent includes\r
+ **\r
+ ** History:\r
+ ** 2011-05-19 V1.00 MWi first version\r
+ **\r
+ ******************************************************************************/\r
+\r
+/**\r
+ ******************************************************************************\r
+ ** \brief MCU header file include\r
+ **\r
+ ******************************************************************************/ \r
+#ifndef _MB9AF314L_H_\r
+  #include "mb9af314l.h"\r
+#endif\r
+\r
+/**\r
+ ******************************************************************************\r
+ ** \brief MCU system start-up header file include\r
+ **\r
+ ******************************************************************************/ \r
+#ifndef _SYSTEM_MB9AF31X_H_\r
+  #include "system_mb9af31x.h"\r
+#endif\r
+\r
+\r

diff --git a/Demo/CORTEX_MB9A310_IAR_Keil/Fujitu_source/startup_iar/startup_mb9af31x.s b/Demo/CORTEX_MB9A310_IAR_Keil/Fujitu_source/startup_iar/startup_mb9af31x.s
new file mode 100644 (file)
index 0000000..079fb37
--- /dev/null
+++ b/Demo/CORTEX_MB9A310_IAR_Keil/Fujitu_source/startup_iar/startup_mb9af31x.s
@@ -0,0 +1,392 @@
+;/************************************************************************/\r
+;/*               (C) Fujitsu Semiconductor Europe GmbH (FSEU)           */\r
+;/*                                                                      */\r
+;/* The following software deliverable is intended for and must only be  */\r
+;/* used for reference and in an evaluation laboratory environment.      */\r
+;/* It is provided on an as-is basis without charge and is subject to    */\r
+;/* alterations.                                                         */\r
+;/* It is the user's obligation to fully test the software in its        */\r
+;/* environment and to ensure proper functionality, qualification and    */\r
+;/* compliance with component specifications.                            */\r
+;/*                                                                      */\r
+;/* In the event the software deliverable includes the use of open       */\r
+;/* source components, the provisions of the governing open source       */\r
+;/* license agreement shall apply with respect to such software          */\r
+;/* deliverable.                                                         */\r
+;/* FSEU does not warrant that the deliverables do not infringe any      */\r
+;/* third party intellectual property right (IPR). In the event that     */\r
+;/* the deliverables infringe a third party IPR it is the sole           */\r
+;/* responsibility of the customer to obtain necessary licenses to       */\r
+;/* continue the usage of the deliverable.                               */\r
+;/*                                                                      */\r
+;/* To the maximum extent permitted by applicable law FSEU disclaims all */\r
+;/* warranties, whether express or implied, in particular, but not       */\r
+;/* limited to, warranties of merchantability and fitness for a          */\r
+;/* particular purpose for which the deliverable is not designated.      */\r
+;/*                                                                      */\r
+;/* To the maximum extent permitted by applicable law, FSEU's liability  */\r
+;/* is restricted to intentional misconduct and gross negligence.        */\r
+;/* FSEU is not liable for consequential damages.                        */\r
+;/*                                                                      */\r
+;/* (V1.5)                                                               */\r
+;/************************************************************************/\r
+;/*  Startup for IAR                                                     */\r
+;/*  Version     V1.03                                                   */\r
+;/*  Date        2011-05-17                                              */\r
+;/*  Target-mcu  MB9A310                                                 */\r
+;/************************************************************************/\r
+\r
+\r
+                MODULE  ?cstartup\r
+\r
+                ;; Forward declaration of sections.\r
+                SECTION CSTACK:DATA:NOROOT(3)\r
+\r
+                SECTION .intvec:CODE:NOROOT(2)\r
+\r
+                EXTERN  __iar_program_start\r
+                EXTERN  SystemInit\r
+                PUBLIC  __vector_table\r
+\r
+                DATA\r
+__vector_table  DCD     sfe(CSTACK)               ; Top of Stack\r
+                       DCD     Reset_Handler             ; Reset\r
+                DCD     NMI_Handler               ; NMI\r
+                DCD     HardFault_Handler         ; Hard Fault\r
+                DCD     MemManage_Handler         ; MPU Fault\r
+                DCD     BusFault_Handler          ; Bus Fault\r
+                DCD     UsageFault_Handler        ; Usage Fault\r
+                DCD     0                         ; Reserved\r
+                DCD     0                         ; Reserved\r
+                DCD     0                         ; Reserved\r
+                DCD     0                         ; Reserved\r
+                DCD     SVC_Handler               ; SVCall\r
+                DCD     DebugMon_Handler          ; Debug Monitor\r
+                DCD     0                         ; Reserved\r
+                DCD     PendSV_Handler            ; PendSV\r
+                DCD     SysTick_Handler           ; SysTick\r
+\r
+                DCD     CSV_Handler               ; 0: Clock Super Visor\r
+                DCD     SWDT_Handler              ; 1: Software Watchdog Timer\r
+                DCD     LVD_Handler               ; 2: Low Voltage Detector\r
+                DCD     MFT_WG_IRQHandler         ; 3: Wave Form Generator / DTIF\r
+                DCD     INT0_7_Handler            ; 4: External Interrupt Request ch.0 to ch.7\r
+                DCD     INT8_15_Handler           ; 5: External Interrupt Request ch.8 to ch.15\r
+                DCD     DT_Handler                ; 6: Dual Timer / Quad Decoder\r
+                DCD     MFS0RX_IRQHandler         ; 7: MultiFunction Serial ch.0\r
+                DCD     MFS0TX_IRQHandler         ; 8: MultiFunction Serial ch.0\r
+                DCD     MFS1RX_IRQHandler         ; 9: MultiFunction Serial ch.1\r
+                DCD     MFS1TX_IRQHandler         ; 10: MultiFunction Serial ch.1\r
+                DCD     MFS2RX_IRQHandler         ; 11: MultiFunction Serial ch.2\r
+                DCD     MFS2TX_IRQHandler         ; 12: MultiFunction Serial ch.2\r
+                DCD     MFS3RX_IRQHandler         ; 13: MultiFunction Serial ch.3\r
+                DCD     MFS3TX_IRQHandler         ; 14: MultiFunction Serial ch.3\r
+                DCD     MFS4RX_IRQHandler         ; 15: MultiFunction Serial ch.4\r
+                DCD     MFS4TX_IRQHandler         ; 16: MultiFunction Serial ch.4\r
+                DCD     MFS5RX_IRQHandler         ; 17: MultiFunction Serial ch.5\r
+                DCD     MFS5TX_IRQHandler         ; 18: MultiFunction Serial ch.5\r
+                DCD     MFS6RX_IRQHandler         ; 19: MultiFunction Serial ch.6\r
+                DCD     MFS6TX_IRQHandler         ; 20: MultiFunction Serial ch.6\r
+                DCD     MFS7RX_IRQHandler         ; 21: MultiFunction Serial ch.7\r
+                DCD     MFS7TX_IRQHandler         ; 22: MultiFunction Serial ch.7\r
+                DCD     PPG_Handler               ; 23: PPG\r
+                DCD     TIM_IRQHandler            ; 24: OSC / PLL / Watch Counter\r
+                DCD     ADC0_IRQHandler           ; 25: ADC0\r
+                DCD     ADC1_IRQHandler           ; 26: ADC1\r
+                DCD     ADC2_IRQHandler           ; 27: ADC2\r
+                DCD     MFT_FRT_IRQHandler        ; 28: Free-run Timer\r
+                DCD     MFT_IPC_IRQHandler        ; 29: Input Capture\r
+                DCD     MFT_OPC_IRQHandler        ; 30: Output Compare\r
+                DCD     BT_IRQHandler             ; 31: Base Timer ch.0 to ch.7\r
+                DCD     DummyHandler              ; 32: Reserved\r
+                DCD     DummyHandler              ; 33: Reserved\r
+                DCD     USBF_Handler              ; 34: USB Function\r
+                DCD     USB_Handler               ; 35: USB Function / USB HOST\r
+                DCD     DummyHandler              ; 36: Reserved\r
+                DCD     DummyHandler              ; 37: Reserved\r
+                DCD     DMAC0_Handler             ; 38: DMAC ch.0\r
+                DCD     DMAC1_Handler             ; 39: DMAC ch.1\r
+                DCD     DMAC2_Handler             ; 40: DMAC ch.2\r
+                DCD     DMAC3_Handler             ; 41: DMAC ch.3\r
+                DCD     DMAC4_Handler             ; 42: DMAC ch.4\r
+                DCD     DMAC5_Handler             ; 43: DMAC ch.5\r
+                DCD     DMAC6_Handler             ; 44: DMAC ch.6\r
+                DCD     DMAC7_Handler             ; 45: DMAC ch.7\r
+                DCD     DummyHandler              ; 46: Reserved\r
+                DCD     DummyHandler              ; 47: Reserved\r
+\r
+                THUMB\r
+; Dummy Exception Handlers (infinite loops which can be modified)\r
+\r
+                PUBWEAK Reset_Handler\r
+                SECTION .text:CODE:REORDER(2)\r
+Reset_Handler\r
+                LDR     R0, =SystemInit\r
+                BLX     R0\r
+                LDR     R0, =__iar_program_start\r
+                BX      R0\r
+\r
+                PUBWEAK NMI_Handler\r
+                SECTION .text:CODE:REORDER(1)\r
+NMI_Handler\r
+                B       NMI_Handler\r
+\r
+                PUBWEAK HardFault_Handler\r
+                SECTION .text:CODE:REORDER(1)\r
+HardFault_Handler\r
+                B       HardFault_Handler\r
+\r
+                PUBWEAK MemManage_Handler\r
+                SECTION .text:CODE:REORDER(1)\r
+MemManage_Handler\r
+                B       MemManage_Handler\r
+\r
+                PUBWEAK BusFault_Handler\r
+                SECTION .text:CODE:REORDER(1)\r
+BusFault_Handler\r
+                B       BusFault_Handler\r
+\r
+                PUBWEAK UsageFault_Handler\r
+                SECTION .text:CODE:REORDER(1)\r
+UsageFault_Handler\r
+                B       UsageFault_Handler\r
+\r
+                PUBWEAK SVC_Handler\r
+                SECTION .text:CODE:REORDER(1)\r
+SVC_Handler\r
+                B       SVC_Handler\r
+\r
+                PUBWEAK DebugMon_Handler\r
+                SECTION .text:CODE:REORDER(1)\r
+DebugMon_Handler\r
+                B       DebugMon_Handler\r
+\r
+                PUBWEAK PendSV_Handler\r
+                SECTION .text:CODE:REORDER(1)\r
+PendSV_Handler\r
+                B       PendSV_Handler\r
+\r
+                PUBWEAK SysTick_Handler\r
+                SECTION .text:CODE:REORDER(1)\r
+SysTick_Handler\r
+                B       SysTick_Handler\r
+\r
+\r
+\r
+                PUBWEAK CSV_Handler\r
+                SECTION .text:CODE:REORDER(1)\r
+CSV_Handler\r
+                B       CSV_Handler\r
+\r
+                PUBWEAK SWDT_Handler\r
+                SECTION .text:CODE:REORDER(1)\r
+SWDT_Handler\r
+                B       SWDT_Handler\r
+\r
+                PUBWEAK LVD_Handler\r
+                SECTION .text:CODE:REORDER(1)\r
+LVD_Handler\r
+                B       LVD_Handler\r
+\r
+                PUBWEAK MFT_WG_IRQHandler\r
+                SECTION .text:CODE:REORDER(1)\r
+MFT_WG_IRQHandler\r
+                B       MFT_WG_IRQHandler\r
+                \r
+                PUBWEAK INT0_7_Handler\r
+                SECTION .text:CODE:REORDER(1)\r
+INT0_7_Handler\r
+                B       INT0_7_Handler\r
+\r
+                PUBWEAK INT8_15_Handler\r
+                SECTION .text:CODE:REORDER(1)\r
+INT8_15_Handler\r
+                B       INT8_15_Handler\r
+                \r
+                PUBWEAK DT_Handler\r
+                SECTION .text:CODE:REORDER(1)\r
+DT_Handler\r
+                B       DT_Handler\r
+\r
+                PUBWEAK MFS0RX_IRQHandler\r
+                SECTION .text:CODE:REORDER(1)\r
+MFS0RX_IRQHandler\r
+                B       MFS0RX_IRQHandler\r
+\r
+                PUBWEAK MFS0TX_IRQHandler\r
+                SECTION .text:CODE:REORDER(1)\r
+MFS0TX_IRQHandler\r
+                B       MFS0TX_IRQHandler\r
+\r
+                PUBWEAK MFS1RX_IRQHandler\r
+                SECTION .text:CODE:REORDER(1)\r
+MFS1RX_IRQHandler\r
+                B       MFS1RX_IRQHandler\r
+\r
+                PUBWEAK MFS1TX_IRQHandler\r
+                SECTION .text:CODE:REORDER(1)\r
+MFS1TX_IRQHandler\r
+                B       MFS1TX_IRQHandler\r
+\r
+                PUBWEAK MFS2RX_IRQHandler\r
+                SECTION .text:CODE:REORDER(1)\r
+MFS2RX_IRQHandler\r
+                B       MFS2RX_IRQHandler\r
+\r
+                PUBWEAK MFS2TX_IRQHandler\r
+                SECTION .text:CODE:REORDER(1)\r
+MFS2TX_IRQHandler\r
+                B       MFS2TX_IRQHandler\r
+\r
+                PUBWEAK MFS3RX_IRQHandler\r
+                SECTION .text:CODE:REORDER(1)\r
+MFS3RX_IRQHandler\r
+                B       MFS3RX_IRQHandler\r
+\r
+                PUBWEAK MFS3TX_IRQHandler\r
+                SECTION .text:CODE:REORDER(1)\r
+MFS3TX_IRQHandler\r
+                B       MFS3TX_IRQHandler\r
+\r
+                PUBWEAK MFS4RX_IRQHandler\r
+                SECTION .text:CODE:REORDER(1)\r
+MFS4RX_IRQHandler\r
+                B       MFS4RX_IRQHandler\r
+\r
+                PUBWEAK MFS4TX_IRQHandler\r
+                SECTION .text:CODE:REORDER(1)\r
+MFS4TX_IRQHandler\r
+                B       MFS4TX_IRQHandler\r
+\r
+                PUBWEAK MFS5RX_IRQHandler\r
+                SECTION .text:CODE:REORDER(1)\r
+MFS5RX_IRQHandler\r
+                B       MFS5RX_IRQHandler\r
+\r
+                PUBWEAK MFS5TX_IRQHandler\r
+                SECTION .text:CODE:REORDER(1)\r
+MFS5TX_IRQHandler\r
+                B       MFS5TX_IRQHandler\r
+\r
+                PUBWEAK MFS6RX_IRQHandler\r
+                SECTION .text:CODE:REORDER(1)\r
+MFS6RX_IRQHandler\r
+                B       MFS6RX_IRQHandler\r
+\r
+                PUBWEAK MFS6TX_IRQHandler\r
+                SECTION .text:CODE:REORDER(1)\r
+MFS6TX_IRQHandler\r
+                B       MFS6TX_IRQHandler\r
+\r
+                PUBWEAK MFS7RX_IRQHandler\r
+                SECTION .text:CODE:REORDER(1)\r
+MFS7RX_IRQHandler\r
+                B       MFS7RX_IRQHandler\r
+\r
+                PUBWEAK MFS7TX_IRQHandler\r
+                SECTION .text:CODE:REORDER(1)\r
+MFS7TX_IRQHandler\r
+                B       MFS7TX_IRQHandler\r
+\r
+                PUBWEAK PPG_Handler\r
+                SECTION .text:CODE:REORDER(1)\r
+PPG_Handler\r
+                B       PPG_Handler\r
+\r
+                PUBWEAK TIM_IRQHandler\r
+                SECTION .text:CODE:REORDER(1)\r
+TIM_IRQHandler\r
+                B       TIM_IRQHandler\r
+\r
+                PUBWEAK ADC0_IRQHandler\r
+                SECTION .text:CODE:REORDER(1)\r
+ADC0_IRQHandler\r
+                B       ADC0_IRQHandler\r
+\r
+                PUBWEAK ADC1_IRQHandler\r
+                SECTION .text:CODE:REORDER(1)\r
+ADC1_IRQHandler\r
+                B       ADC1_IRQHandler\r
+\r
+                PUBWEAK ADC2_IRQHandler\r
+                SECTION .text:CODE:REORDER(1)\r
+ADC2_IRQHandler\r
+                B       ADC2_IRQHandler\r
+\r
+                PUBWEAK MFT_FRT_IRQHandler\r
+                SECTION .text:CODE:REORDER(1)\r
+MFT_FRT_IRQHandler\r
+                B       MFT_FRT_IRQHandler\r
+\r
+                PUBWEAK MFT_IPC_IRQHandler\r
+                SECTION .text:CODE:REORDER(1)\r
+MFT_IPC_IRQHandler\r
+                B       MFT_IPC_IRQHandler\r
+\r
+                PUBWEAK MFT_OPC_IRQHandler\r
+                SECTION .text:CODE:REORDER(1)\r
+MFT_OPC_IRQHandler\r
+                B       MFT_OPC_IRQHandler\r
+\r
+                PUBWEAK BT_IRQHandler\r
+                SECTION .text:CODE:REORDER(1)\r
+BT_IRQHandler\r
+                B       BT_IRQHandler\r
+\r
+                PUBWEAK USBF_Handler\r
+                SECTION .text:CODE:REORDER(1)\r
+USBF_Handler\r
+                B       USBF_Handler\r
+\r
+                PUBWEAK USB_Handler\r
+                SECTION .text:CODE:REORDER(1)\r
+USB_Handler\r
+                B       USB_Handler\r
+\r
+                PUBWEAK DMAC0_Handler\r
+                SECTION .text:CODE:REORDER(1)\r
+DMAC0_Handler\r
+                B       DMAC0_Handler\r
+\r
+\r
+                PUBWEAK DMAC1_Handler\r
+                SECTION .text:CODE:REORDER(1)\r
+DMAC1_Handler\r
+                B       DMAC1_Handler\r
+\r
+                PUBWEAK DMAC2_Handler\r
+                SECTION .text:CODE:REORDER(1)\r
+DMAC2_Handler\r
+                B       DMAC2_Handler\r
+\r
+                PUBWEAK DMAC3_Handler\r
+                SECTION .text:CODE:REORDER(1)\r
+DMAC3_Handler\r
+                B       DMAC3_Handler\r
+\r
+                PUBWEAK DMAC4_Handler\r
+                SECTION .text:CODE:REORDER(1)\r
+DMAC4_Handler\r
+                B       DMAC4_Handler\r
+\r
+                PUBWEAK DMAC5_Handler\r
+                SECTION .text:CODE:REORDER(1)\r
+DMAC5_Handler\r
+                B       DMAC5_Handler\r
+\r
+                PUBWEAK DMAC6_Handler\r
+                SECTION .text:CODE:REORDER(1)\r
+DMAC6_Handler\r
+                B       DMAC6_Handler\r
+\r
+                PUBWEAK DMAC7_Handler\r
+                SECTION .text:CODE:REORDER(1)\r
+DMAC7_Handler\r
+                B       DMAC7_Handler\r
+\r
+                PUBWEAK DummyHandler\r
+                SECTION .text:CODE:REORDER(1)\r
+DummyHandler\r
+                B       DummyHandler\r
+\r
+                END\r

diff --git a/Demo/CORTEX_MB9A310_IAR_Keil/Fujitu_source/startup_keil/startup_mb9bf50x.s b/Demo/CORTEX_MB9A310_IAR_Keil/Fujitu_source/startup_keil/startup_mb9bf50x.s
new file mode 100644 (file)
index 0000000..5001b9c
--- /dev/null
+++ b/Demo/CORTEX_MB9A310_IAR_Keil/Fujitu_source/startup_keil/startup_mb9bf50x.s
@@ -0,0 +1,327 @@
+;/************************************************************************/\r
+;/*               (C) Fujitsu Semiconductor Europe GmbH                  */\r
+;/*                                                                      */\r
+;/* The following software deliverable is intended for and must only be  */\r
+;/* used for reference and in an evaluation laboratory environment.      */\r
+;/* It is provided on an as-is basis without charge and is subject to    */\r
+;/* alterations.                                                         */\r
+;/* It is the user\92s obligation to fully test the software in its        */\r
+;/* environment and to ensure proper functionality, qualification and    */\r
+;/* compliance with component specifications.                            */\r
+;/*                                                                      */\r
+;/* In the event the software deliverable includes the use of open       */\r
+;/* source components, the provisions of the governing open source       */\r
+;/* license agreement shall apply with respect to such software          */\r
+;/* deliverable.                                                         */\r
+;/* FSEU does not warrant that the deliverables do not infringe any      */\r
+;/* third party intellectual property right (IPR). In the event that     */\r
+;/* the deliverables infringe a third party IPR it is the sole           */\r
+;/* responsibility of the customer to obtain necessary licenses to       */\r
+;/* continue the usage of the deliverable.                               */\r
+;/*                                                                      */\r
+;/* To the maximum extent permitted by applicable law FSEU disclaims all */\r
+;/* warranties, whether express or implied, in particular, but not       */\r
+;/* limited to, warranties of merchantability and fitness for a          */\r
+;/* particular purpose for which the deliverable is not designated.      */\r
+;/*                                                                      */\r
+;/* To the maximum extent permitted by applicable law, FSEU's liability  */\r
+;/* is restricted to intention and gross negligence.                     */\r
+;/* FSEU is not liable for consequential damages.                        */\r
+;/*                                                                      */\r
+;/* (V1.4)                                                               */\r
+;/************************************************************************/\r
+;/*  Startup for ARM                                                     */\r
+;/*  Version     V1.02                                                   */\r
+;/*  Date        2011-01-12                                              */\r
+;/*  Target-mcu  MB9B5xx                                                 */\r
+;/************************************************************************/\r
+\r
+; Stack Configuration\r
+;  Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\r
+\r
+Stack_Size      EQU     0x00000200\r
+\r
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3\r
+Stack_Mem       SPACE   Stack_Size\r
+__initial_sp\r
+\r
+\r
+; Heap Configuration\r
+;  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\r
+\r
+Heap_Size       EQU     0x00000000\r
+\r
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3\r
+__heap_base\r
+Heap_Mem        SPACE   Heap_Size\r
+__heap_limit\r
+\r
+\r
+                PRESERVE8\r
+                THUMB\r
+\r
+\r
+; Vector Table Mapped to Address 0 at Reset\r
+\r
+                AREA    RESET, DATA, READONLY\r
+                EXPORT  __Vectors\r
+                EXPORT  __Vectors_End\r
+                EXPORT  __Vectors_Size\r
+\r
+__Vectors       DCD     __initial_sp              ; Top of Stack\r
+                DCD     Reset_Handler             ; Reset Handler\r
+                DCD     NMI_Handler               ; NMI Handler\r
+                DCD     HardFault_Handler         ; Hard Fault Handler\r
+                DCD     MemManage_Handler         ; MPU Fault Handler\r
+                DCD     BusFault_Handler          ; Bus Fault Handler\r
+                DCD     UsageFault_Handler        ; Usage Fault Handler\r
+                DCD     0                         ; Reserved\r
+                DCD     0                         ; Reserved\r
+                DCD     0                         ; Reserved\r
+                DCD     0                         ; Reserved\r
+                DCD     SVC_Handler               ; SVCall Handler\r
+                DCD     DebugMon_Handler          ; Debug Monitor Handler\r
+                DCD     0                         ; Reserved\r
+                DCD     PendSV_Handler            ; PendSV Handler\r
+                DCD     SysTick_Handler           ; SysTick Handler\r
+\r
+                DCD     CSV_Handler               ; 0: Clock Super Visor\r
+                DCD     SWDT_Handler              ; 1: Software Watchdog Timer\r
+                DCD     LVD_Handler               ; 2: Low Voltage Detector\r
+                DCD     MFT_WG_IRQHandler         ; 3: Wave Form Generator / DTIF\r
+                DCD     INT0_7_Handler            ; 4: External Interrupt Request ch.0 to ch.7\r
+                DCD     INT8_15_Handler           ; 5: External Interrupt Request ch.8 to ch.15\r
+                DCD     DT_Handler                ; 6: Dual Timer / Quad Decoder\r
+                DCD     MFS0RX_IRQHandler         ; 7: MultiFunction Serial ch.0\r
+                DCD     MFS0TX_IRQHandler         ; 8: MultiFunction Serial ch.0\r
+                DCD     MFS1RX_IRQHandler         ; 9: MultiFunction Serial ch.1\r
+                DCD     MFS1TX_IRQHandler         ; 10: MultiFunction Serial ch.1\r
+                DCD     MFS2RX_IRQHandler         ; 11: MultiFunction Serial ch.2\r
+                DCD     MFS2TX_IRQHandler         ; 12: MultiFunction Serial ch.2\r
+                DCD     MFS3RX_IRQHandler         ; 13: MultiFunction Serial ch.3\r
+                DCD     MFS3TX_IRQHandler         ; 14: MultiFunction Serial ch.3\r
+                DCD     MFS4RX_IRQHandler         ; 15: MultiFunction Serial ch.4\r
+                DCD     MFS4TX_IRQHandler         ; 16: MultiFunction Serial ch.4\r
+                DCD     MFS5RX_IRQHandler         ; 17: MultiFunction Serial ch.5\r
+                DCD     MFS5TX_IRQHandler         ; 18: MultiFunction Serial ch.5\r
+                DCD     MFS6RX_IRQHandler         ; 19: MultiFunction Serial ch.6\r
+                DCD     MFS6TX_IRQHandler         ; 20: MultiFunction Serial ch.6\r
+                DCD     MFS7RX_IRQHandler         ; 21: MultiFunction Serial ch.7\r
+                DCD     MFS7TX_IRQHandler         ; 22: MultiFunction Serial ch.7\r
+                DCD     PPG_Handler               ; 23: PPG\r
+                DCD     TIM_IRQHandler            ; 24: OSC / PLL / Watch Counter\r
+                DCD     ADC0_IRQHandler           ; 25: ADC0\r
+                DCD     ADC1_IRQHandler           ; 26: ADC1\r
+                DCD     ADC2_IRQHandler           ; 27: ADC2\r
+                DCD     MFT_FRT_IRQHandler        ; 28: Free-run Timer\r
+                DCD     MFT_IPC_IRQHandler        ; 29: Input Capture\r
+                DCD     MFT_OPC_IRQHandler        ; 30: Output Compare\r
+                DCD     BT_IRQHandler             ; 31: Base Timer ch.0 to ch.7\r
+                DCD     CAN0_IRQHandler           ; 32: CAN ch.0\r
+                DCD     CAN1_IRQHandler           ; 33: CAN ch.1\r
+                DCD     USBF_Handler              ; 34: USB Function\r
+                DCD     USB_Handler               ; 35: USB Function / USB HOST\r
+                DCD     DummyHandler              ; 36: Reserved\r
+                DCD     DummyHandler              ; 37: Reserved\r
+                DCD     DMAC0_Handler             ; 38: DMAC ch.0\r
+                DCD     DMAC1_Handler             ; 39: DMAC ch.1\r
+                DCD     DMAC2_Handler             ; 40: DMAC ch.2\r
+                DCD     DMAC3_Handler             ; 41: DMAC ch.3\r
+                DCD     DMAC4_Handler             ; 42: DMAC ch.4\r
+                DCD     DMAC5_Handler             ; 43: DMAC ch.5\r
+                DCD     DMAC6_Handler             ; 44: DMAC ch.6\r
+                DCD     DMAC7_Handler             ; 45: DMAC ch.7\r
+                DCD     DummyHandler              ; 46: Reserved\r
+                DCD     DummyHandler              ; 47: Reserved\r
+__Vectors_End\r
+\r
+__Vectors_Size         EQU     __Vectors_End - __Vectors\r
+\r
+                AREA    |.text|, CODE, READONLY\r
+\r
+\r
+; Reset Handler\r
+\r
+Reset_Handler   PROC\r
+                EXPORT  Reset_Handler             [WEAK]\r
+                IMPORT  SystemInit\r
+                IMPORT  __main\r
+                LDR     R0, =SystemInit\r
+                BLX     R0\r
+                LDR     R0, =__main\r
+                BX      R0\r
+                ENDP\r
+\r
+\r
+; Dummy Exception Handlers (infinite loops which can be modified)\r
+\r
+NMI_Handler     PROC\r
+                EXPORT  NMI_Handler               [WEAK]\r
+                B       .\r
+                ENDP\r
+HardFault_Handler\\r
+                PROC\r
+                EXPORT  HardFault_Handler         [WEAK]\r
+                B       .\r
+                ENDP\r
+MemManage_Handler\\r
+                PROC\r
+                EXPORT  MemManage_Handler         [WEAK]\r
+                B       .\r
+                ENDP\r
+BusFault_Handler\\r
+                PROC\r
+                EXPORT  BusFault_Handler          [WEAK]\r
+                B       .\r
+                ENDP\r
+UsageFault_Handler\\r
+                PROC\r
+                EXPORT  UsageFault_Handler        [WEAK]\r
+                B       .\r
+                ENDP\r
+SVC_Handler     PROC\r
+                EXPORT  SVC_Handler               [WEAK]\r
+                B       .\r
+                ENDP\r
+DebugMon_Handler\\r
+                PROC\r
+                EXPORT  DebugMon_Handler          [WEAK]\r
+                B       .\r
+                ENDP\r
+PendSV_Handler  PROC\r
+                EXPORT  PendSV_Handler            [WEAK]\r
+                B       .\r
+                ENDP\r
+SysTick_Handler PROC\r
+                EXPORT  SysTick_Handler           [WEAK]\r
+                B       .\r
+                ENDP\r
+\r
+Default_Handler PROC\r
+\r
+                EXPORT  CSV_Handler                  [WEAK]\r
+                EXPORT  SWDT_Handler              [WEAK]\r
+                EXPORT  LVD_Handler               [WEAK]\r
+                EXPORT  MFT_WG_IRQHandler         [WEAK]\r
+                EXPORT  INT0_7_Handler            [WEAK]\r
+                EXPORT  INT8_15_Handler           [WEAK]\r
+                EXPORT  DT_Handler                [WEAK]\r
+                EXPORT  MFS0RX_IRQHandler         [WEAK]\r
+                EXPORT  MFS0TX_IRQHandler         [WEAK]\r
+                EXPORT  MFS1RX_IRQHandler         [WEAK]\r
+                EXPORT  MFS1TX_IRQHandler         [WEAK]\r
+                EXPORT  MFS2RX_IRQHandler         [WEAK]\r
+                EXPORT  MFS2TX_IRQHandler         [WEAK]\r
+                EXPORT  MFS3RX_IRQHandler         [WEAK]\r
+                EXPORT  MFS3TX_IRQHandler         [WEAK]\r
+                EXPORT  MFS4RX_IRQHandler         [WEAK]\r
+                EXPORT  MFS4TX_IRQHandler         [WEAK]\r
+                EXPORT  MFS5RX_IRQHandler         [WEAK]\r
+                EXPORT  MFS5TX_IRQHandler         [WEAK]\r
+                EXPORT  MFS6RX_IRQHandler         [WEAK]\r
+                EXPORT  MFS6TX_IRQHandler         [WEAK]\r
+                EXPORT  MFS7RX_IRQHandler         [WEAK]\r
+                EXPORT  MFS7TX_IRQHandler         [WEAK]\r
+                EXPORT  PPG_Handler               [WEAK]\r
+                EXPORT  TIM_IRQHandler            [WEAK]\r
+                EXPORT  ADC0_IRQHandler           [WEAK]\r
+                EXPORT  ADC1_IRQHandler           [WEAK]\r
+                EXPORT  ADC2_IRQHandler           [WEAK]\r
+                EXPORT  MFT_FRT_IRQHandler        [WEAK]\r
+                EXPORT  MFT_IPC_IRQHandler        [WEAK]\r
+                EXPORT  MFT_OPC_IRQHandler        [WEAK]\r
+                EXPORT  BT_IRQHandler             [WEAK]\r
+                EXPORT  CAN0_IRQHandler           [WEAK]\r
+                EXPORT  CAN1_IRQHandler           [WEAK]\r
+                EXPORT  USBF_Handler              [WEAK]\r
+                EXPORT  USB_Handler               [WEAK]\r
+                EXPORT  DMAC0_Handler             [WEAK]\r
+                EXPORT  DMAC1_Handler             [WEAK]\r
+                EXPORT  DMAC2_Handler             [WEAK]\r
+                EXPORT  DMAC3_Handler             [WEAK]\r
+                EXPORT  DMAC4_Handler             [WEAK]\r
+                EXPORT  DMAC5_Handler             [WEAK]\r
+                EXPORT  DMAC6_Handler             [WEAK]\r
+                EXPORT  DMAC7_Handler             [WEAK]\r
+                EXPORT  DummyHandler              [WEAK]\r
+\r
+CSV_Handler\r
+SWDT_Handler\r
+LVD_Handler\r
+MFT_WG_IRQHandler\r
+INT0_7_Handler\r
+INT8_15_Handler\r
+DT_Handler\r
+MFS0RX_IRQHandler\r
+MFS0TX_IRQHandler\r
+MFS1RX_IRQHandler\r
+MFS1TX_IRQHandler\r
+MFS2RX_IRQHandler\r
+MFS2TX_IRQHandler\r
+MFS3RX_IRQHandler\r
+MFS3TX_IRQHandler\r
+MFS4RX_IRQHandler\r
+MFS4TX_IRQHandler\r
+MFS5RX_IRQHandler\r
+MFS5TX_IRQHandler\r
+MFS6RX_IRQHandler\r
+MFS6TX_IRQHandler\r
+MFS7RX_IRQHandler\r
+MFS7TX_IRQHandler\r
+PPG_Handler\r
+TIM_IRQHandler\r
+ADC0_IRQHandler\r
+ADC1_IRQHandler\r
+ADC2_IRQHandler\r
+MFT_FRT_IRQHandler\r
+MFT_IPC_IRQHandler\r
+MFT_OPC_IRQHandler\r
+BT_IRQHandler\r
+CAN0_IRQHandler\r
+CAN1_IRQHandler\r
+USBF_Handler\r
+USB_Handler\r
+DMAC0_Handler\r
+DMAC1_Handler\r
+DMAC2_Handler\r
+DMAC3_Handler\r
+DMAC4_Handler\r
+DMAC5_Handler\r
+DMAC6_Handler\r
+DMAC7_Handler\r
+DummyHandler\r
+\r
+                B       .\r
+\r
+                ENDP\r
+\r
+\r
+                ALIGN\r
+\r
+\r
+; User Initial Stack & Heap\r
+\r
+                IF      :DEF:__MICROLIB\r
+                \r
+                EXPORT  __initial_sp\r
+                EXPORT  __heap_base\r
+                EXPORT  __heap_limit\r
+                \r
+                ELSE\r
+                \r
+                IMPORT  __use_two_region_memory\r
+                EXPORT  __user_initial_stackheap\r
+__user_initial_stackheap\r
+\r
+                LDR     R0, =  Heap_Mem\r
+                LDR     R1, =(Stack_Mem + Stack_Size)\r
+                LDR     R2, = (Heap_Mem +  Heap_Size)\r
+                LDR     R3, = Stack_Mem\r
+                BX      LR\r
+\r
+                ALIGN\r
+\r
+                ENDIF\r
+\r
+\r
+                END\r

diff --git a/Demo/CORTEX_MB9A310_IAR_Keil/Fujitu_source/system_mb9af31x.c b/Demo/CORTEX_MB9A310_IAR_Keil/Fujitu_source/system_mb9af31x.c
new file mode 100644 (file)
index 0000000..4e4f1df
--- /dev/null
+++ b/Demo/CORTEX_MB9A310_IAR_Keil/Fujitu_source/system_mb9af31x.c
@@ -0,0 +1,202 @@
+/************************************************************************/\r
+/*               (C) Fujitsu Semiconductor Europe GmbH (FSEU)           */\r
+/*                                                                      */\r
+/* The following software deliverable is intended for and must only be  */\r
+/* used for reference and in an evaluation laboratory environment.      */\r
+/* It is provided on an as-is basis without charge and is subject to    */\r
+/* alterations.                                                         */\r
+/* It is the user's obligation to fully test the software in its        */\r
+/* environment and to ensure proper functionality, qualification and    */\r
+/* compliance with component specifications.                            */\r
+/*                                                                      */\r
+/* In the event the software deliverable includes the use of open       */\r
+/* source components, the provisions of the governing open source       */\r
+/* license agreement shall apply with respect to such software          */\r
+/* deliverable.                                                         */\r
+/* FSEU does not warrant that the deliverables do not infringe any      */\r
+/* third party intellectual property right (IPR). In the event that     */\r
+/* the deliverables infringe a third party IPR it is the sole           */\r
+/* responsibility of the customer to obtain necessary licenses to       */\r
+/* continue the usage of the deliverable.                               */\r
+/*                                                                      */\r
+/* To the maximum extent permitted by applicable law FSEU disclaims all */\r
+/* warranties, whether express or implied, in particular, but not       */\r
+/* limited to, warranties of merchantability and fitness for a          */\r
+/* particular purpose for which the deliverable is not designated.      */\r
+/*                                                                      */\r
+/* To the maximum extent permitted by applicable law, FSEU's liability  */\r
+/* is restricted to intentional misconduct and gross negligence.        */\r
+/* FSEU is not liable for consequential damages.                        */\r
+/*                                                                      */\r
+/* (V1.5)                                                               */\r
+/************************************************************************/\r
+\r
+#include "mcu.h"\r
+\r
+/** \file system_mb9af31x.c\r
+ **\r
+ ** FM3 system initialization functions\r
+ ** All adjustments can be done in belonging header file.\r
+ **\r
+ ** History:\r
+ ** 2011-05-16 V1.0 MWi original version\r
+ ******************************************************************************/\r
+\r
+/**\r
+ ******************************************************************************\r
+ ** System Clock Frequency (Core Clock) Variable according CMSIS\r
+ ******************************************************************************/\r
+uint32_t SystemCoreClock = __HCLK;\r
+\r
+/**\r
+ ******************************************************************************\r
+ ** \brief  Update the System Core Clock with current core Clock retrieved from\r
+ ** cpu registers.\r
+ ** \param  none\r
+ ** \return none\r
+ ******************************************************************************/\r
+void SystemCoreClockUpdate (void) {\r
+  uint32_t masterClk;\r
+  uint32_t u32RegisterRead; // Workaround variable for MISRA C rule conformance\r
+\r
+  switch ((FM3_CRG->SCM_CTL >> 5) & 0x07) {\r
+    case 0:                                 /* internal High-speed Cr osc.    */\r
+      masterClk = __CLKHC;\r
+      break;\r
+\r
+    case 1:                                 /* external main osc.             */\r
+      masterClk = __CLKMO;\r
+      break;\r
+\r
+    case 2:                                 /* PLL clock                      */\r
+  // Workaround for preventing MISRA C:1998 Rule 46 (MISRA C:2004 Rule 12.2)\r
+  // violation:\r
+  //   "Unordered accesses to a volatile location"\r
+      u32RegisterRead = (__CLKMO  * (((FM3_CRG->PLL_CTL2) & 0x1F) + 1));\r
+      masterClk = (u32RegisterRead / (((FM3_CRG->PLL_CTL1 >> 4) & 0x0F) + 1));\r
+      break;\r
+\r
+    case 4:                                 /* internal Low-speed CR osc.     */\r
+      masterClk = __CLKLC;\r
+      break;\r
+\r
+    case 5:                                 /* external Sub osc.              */\r
+      masterClk = __CLKSO;\r
+      break;\r
+\r
+    default:\r
+      masterClk = 0Ul;\r
+      break;\r
+  }\r
+\r
+  switch (FM3_CRG->BSC_PSR & 0x07) {\r
+    case 0:\r
+      SystemCoreClock = masterClk;\r
+      break;\r
+\r
+    case 1:\r
+      SystemCoreClock = masterClk / 2;\r
+      break;\r
+\r
+    case 2:\r
+      SystemCoreClock = masterClk / 3;\r
+      break;\r
+\r
+    case 3:\r
+      SystemCoreClock = masterClk / 4;\r
+      break;\r
+\r
+    case 4:\r
+      SystemCoreClock = masterClk / 6;\r
+      break;\r
+\r
+    case 5:\r
+      SystemCoreClock = masterClk /8;\r
+      break;\r
+\r
+    case 6:\r
+      SystemCoreClock = masterClk /16;\r
+      break;\r
+\r
+    default:\r
+      SystemCoreClock = 0Ul;\r
+      break;\r
+  }\r
+\r
+}\r
+\r
+/**\r
+ ******************************************************************************\r
+ ** \brief  Setup the microcontroller system. Initialize the System and update\r
+ ** the SystemCoreClock variable.\r
+ **\r
+ ** \param  none\r
+ ** \return none\r
+ ******************************************************************************/\r
+void SystemInit (void) {\r
+\r
+  static uint32_t u32IoRegisterRead;  // Workaround variable for MISRA C rule conformance\r
+  \r
+#if (HWWD_DISABLE)                                 /* HW Watchdog Disable */\r
+  FM3_HWWDT->WDG_LCK = 0x1ACCE551;                 /* HW Watchdog Unlock */\r
+  FM3_HWWDT->WDG_LCK = 0xE5331AAE;\r
+  FM3_HWWDT->WDG_CTL = 0;                          /* HW Watchdog stop */\r
+#endif\r
+\r
+#if (CLOCK_SETUP)                                   /* Clock Setup */\r
+  FM3_CRG->BSC_PSR   = BSC_PSR_Val;                /* set System Clock presacaler */\r
+  FM3_CRG->APBC0_PSR = APBC0_PSR_Val;              /* set APB0 presacaler */\r
+  FM3_CRG->APBC1_PSR = APBC1_PSR_Val;              /* set APB1 presacaler */\r
+  FM3_CRG->APBC2_PSR = APBC2_PSR_Val;              /* set APB2 presacaler */\r
+  FM3_CRG->SWC_PSR   = SWC_PSR_Val | (1UL << 7);   /* set SW Watchdog presacaler */\r
+  FM3_CRG->TTC_PSR   = TTC_PSR_Val;                /* set Trace Clock presacaler */\r
+\r
+  FM3_CRG->CSW_TMR   = CSW_TMR_Val;                /* set oscillation stabilization wait time */\r
+  \r
+  if (SCM_CTL_Val & (1UL << 1)) {                    /* Main clock oscillator enabled ? */\r
+    FM3_CRG->SCM_CTL |= (1UL << 1);                /* enable main oscillator */ \r
+    while (!(FM3_CRG->SCM_STR & (1UL << 1)));      /* wait for Main clock oscillation stable */\r
+  }\r
+  \r
+  if (SCM_CTL_Val & (1UL << 3)) {                    /* Sub clock oscillator enabled ? */\r
+    FM3_CRG->SCM_CTL |= (1UL << 3);                /* enable sub oscillator */ \r
+    while (!(FM3_CRG->SCM_STR & (1UL << 3)));      /* wait for Sub clock oscillation stable */\r
+  }\r
+\r
+  FM3_CRG->PSW_TMR   = PSW_TMR_Val;                /* set PLL stabilization wait time */\r
+  FM3_CRG->PLL_CTL1  = PLL_CTL1_Val;               /* set PLLM and PLLK */\r
+  FM3_CRG->PLL_CTL2  = PLL_CTL2_Val;               /* set PLLN          */\r
+  \r
+  if (SCM_CTL_Val & (1UL << 4)) {                    /* PLL enabled ? */\r
+    FM3_CRG->SCM_CTL  |= (1UL << 4);               /* enable PLL */ \r
+    while (!(FM3_CRG->SCM_STR & (1UL << 4)));      /* wait for PLL stable */\r
+  }\r
+\r
+  FM3_CRG->SCM_CTL  |= (SCM_CTL_Val & 0xE0);       /* Set Master Clock switch */ \r
+  \r
+  // Workaround for preventing MISRA C:1998 Rule 46 (MISRA C:2004 Rule 12.2)\r
+  // violations:\r
+  //   "Unordered reads and writes to or from same location" and\r
+  //   "Unordered accesses to a volatile location"\r
+  do                                              \r
+  {                                               \r
+    u32IoRegisterRead = (FM3_CRG->SCM_CTL & 0xE0); \r
+  }while ((FM3_CRG->SCM_STR & 0xE0) != u32IoRegisterRead);\r
+#endif // (CLOCK_SETUP)\r
+  \r
+#if (CR_TRIM_SETUP)\r
+  /* CR Trimming Data  */\r
+  if( 0x000003FF != (FM3_FLASH_IF->CRTRMM & 0x000003FF) )\r
+  {\r
+    /* UnLock (MCR_FTRM) */\r
+    FM3_CRTRIM->MCR_RLR = 0x1ACCE554;\r
+    /* Set MCR_FTRM */\r
+    FM3_CRTRIM->MCR_FTRM = FM3_FLASH_IF->CRTRMM;\r
+    /* Lock (MCR_FTRM) */\r
+    FM3_CRTRIM->MCR_RLR = 0x00000000;\r
+  }\r
+#endif // (CR_TRIM_SETUP)\r
+}\r
+\r
+\r
+\r

diff --git a/Demo/CORTEX_MB9A310_IAR_Keil/Fujitu_source/system_mb9af31x.h b/Demo/CORTEX_MB9A310_IAR_Keil/Fujitu_source/system_mb9af31x.h
new file mode 100644 (file)
index 0000000..e55e410
--- /dev/null
+++ b/Demo/CORTEX_MB9A310_IAR_Keil/Fujitu_source/system_mb9af31x.h
@@ -0,0 +1,674 @@
+/************************************************************************/\r
+/*               (C) Fujitsu Semiconductor Europe GmbH (FSEU)           */\r
+/*                                                                      */\r
+/* The following software deliverable is intended for and must only be  */\r
+/* used for reference and in an evaluation laboratory environment.      */\r
+/* It is provided on an as-is basis without charge and is subject to    */\r
+/* alterations.                                                         */\r
+/* It is the user's obligation to fully test the software in its        */\r
+/* environment and to ensure proper functionality, qualification and    */\r
+/* compliance with component specifications.                            */\r
+/*                                                                      */\r
+/* In the event the software deliverable includes the use of open       */\r
+/* source components, the provisions of the governing open source       */\r
+/* license agreement shall apply with respect to such software          */\r
+/* deliverable.                                                         */\r
+/* FSEU does not warrant that the deliverables do not infringe any      */\r
+/* third party intellectual property right (IPR). In the event that     */\r
+/* the deliverables infringe a third party IPR it is the sole           */\r
+/* responsibility of the customer to obtain necessary licenses to       */\r
+/* continue the usage of the deliverable.                               */\r
+/*                                                                      */\r
+/* To the maximum extent permitted by applicable law FSEU disclaims all */\r
+/* warranties, whether express or implied, in particular, but not       */\r
+/* limited to, warranties of merchantability and fitness for a          */\r
+/* particular purpose for which the deliverable is not designated.      */\r
+/*                                                                      */\r
+/* To the maximum extent permitted by applicable law, FSEU's liability  */\r
+/* is restricted to intentional misconduct and gross negligence.        */\r
+/* FSEU is not liable for consequential damages.                        */\r
+/*                                                                      */\r
+/* (V1.5)                                                               */\r
+/************************************************************************/\r
+/** \file system_mb9af31x.h\r
+ **\r
+ ** Headerfile for FM3 system parameters\r
+ **\r
+ ** User clock definitions can be done for the following clock settings:\r
+ ** - CLOCK_SETUP : Execute the clock settings form the settings below in\r
+ **                 SystemInit()\r
+ ** - __CLKMO : External clock frequency for main oscillion\r
+ ** - __CLKSO : External clock frequency for sub oscillion\r
+ ** - SCM_CTL : System Clock Mode Control Register\r
+ ** - BSC_PSR : Base Clock Prescaler Register\r
+ ** - APBC0_PSR : APB0 Prescaler Register\r
+ ** - APBC1_PSR : APB1 Prescaler Register\r
+ ** - APBC2_PSR : APB2 Prescaler Register\r
+ ** - SWC_PSR : Software Watchdog Clock Prescaler Register\r
+ ** - TTC_PSR : Trace Clock Prescaler Register\r
+ ** - CSW_TMR : Clock Stabilization Wait Time Register\r
+ ** - PSW_TMR : PLL Clock Stabilization Wait Time Setup Register\r
+ ** - PLL_CTL1 : PLL Control Register 1\r
+ ** - PLL_CTL2 : PLL Control Register 2\r
+ **\r
+ ** The register settings are check for correct values of reserved bits.\r
+ ** Otherwise a preprocessor error is output and stops the build process.\r
+ ** Furthermore the 'master clock' is retrieved from the register settings\r
+ ** and the system clock (HCLK) is calculated from the Base Clock Prescaler\r
+ ** Register (BSC_PSR). This value is used for the global CMSIS variable\r
+ ** #SystemCoreClock. Also the absolute external, PLL and HCL freqeuncy is\r
+ ** is checked. Note that not all possible wrong setting are checked! The\r
+ ** user has to take care to fulfill the settings stated in the according\r
+ ** device's data sheet!\r
+ **\r
+ ** User definition for Hardware Watchdog:\r
+ ** - HWWD_DISABLE : Disables Hardware Watchdog in SystemInit()\r
+ **\r
+ ** User definition for CR Trimming:\r
+ ** - CR_TRIM_SETUP : Enables CR trimming in SystemInit()\r
+ **\r
+ ** History:\r
+ ** 2011-05-16 V1.0 MWi original version\r
+ *****************************************************************************/\r
+\r
+#ifndef _SYSTEM_MB9AF31X_H_\r
+#define _SYSTEM_MB9AF31X_H_\r
+\r
+/******************************************************************************/\r
+/* Include files                                                              */\r
+/******************************************************************************/\r
+   \r
+#include <stdint.h>\r
+\r
+/******************************************************************************/\r
+/* Global pre-processor symbols/macros ('define')                             */\r
+/******************************************************************************/\r
+   \r
+/******************************************************************************/\r
+/*                                                                            */\r
+/*                      START OF USER SETTINGS HERE                           */\r
+/*                      ===========================                           */   \r
+/*                                                                            */\r
+/*                 All lines with '<<<' can be set by user.                   */\r
+/*                                                                            */\r
+/******************************************************************************/\r
+\r
+/**\r
+ ******************************************************************************\r
+ ** \brief Clock Setup Enable\r
+ **        <i>(USER SETTING)</i>\r
+ **\r
+ ** - 0 = No clock setup done by system_mb9xfxxx.c\r
+ ** - 1 = Clock setup done by system_mb9xfxxx.c\r
+ ******************************************************************************/ \r
+#define CLOCK_SETUP               1   // <<< Define clock setup here\r
+\r
+/**\r
+ ******************************************************************************\r
+ ** \brief External Main Clock Frequency (in Hz, [value]UL)\r
+ **        <i>(USER SETTING)</i>\r
+ ******************************************************************************/    \r
+#define __CLKMO        ( 4000000UL)   // <<< External   4MHz Crystal\r
+\r
+/**\r
+ ******************************************************************************\r
+ ** \brief External Sub Clock Frequency (in Hz, [value]UL)\r
+ **        <i>(USER SETTING)</i>\r
+ ******************************************************************************/  \r
+#define __CLKSO        (   32768UL)   // <<<  External  32KHz Crystal\r
+\r
+/**\r
+ ******************************************************************************\r
+ ** \brief System Clock Mode Control Register value definition\r
+ **        <i>(USER SETTING)</i>\r
+ ** \r
+ ** SCM_CTL\r
+ **\r
+ ** Bit#7-5 : RCS[2:0]\r
+ ** - 0 = Internal high-speed CR oscillation (default)\r
+ ** - 1 = Main oscillation clock\r
+ ** - 2 = PLL oscillation clock\r
+ ** - 3 = (not allowed)\r
+ ** - 4 = Internal low-speed CR oscillation\r
+ ** - 5 = Sub clock oscillation\r
+ ** - 6 = (not allowed)\r
+ ** - 7 = (not allowed)\r
+ **\r
+ ** Bit#4 : PLLE\r
+ ** - 0 = Disable PLL (default)\r
+ ** - 1 = Enable PLL\r
+ **\r
+ ** Bit#3 : SOSCE\r
+ ** - 0 = Disable sub oscillation (default)\r
+ ** - 1 = Enable sub oscillation\r
+ **\r
+ ** Bit#2 : (reserved)\r
+ **\r
+ ** Bit#1 : MOSCE\r
+ ** - 0 = Disable main oscillation (default)\r
+ ** - 1 = Enable main oscillation  \r
+ **\r
+ ** Bit#0 : (reserved)  \r
+ ******************************************************************************/ \r
+#define SCM_CTL_Val           0x00000052    // <<< Define SCM_CTL here\r
+\r
+/**\r
+ ******************************************************************************\r
+ ** \brief Base Clock Prescaler Register value definition\r
+ **        <i>(USER SETTING)</i>\r
+ **\r
+ ** BSC_PSR\r
+ **\r
+ ** Bit#7-3 : (reserved)\r
+ **\r
+ ** Bit#2-0 : BSR[2:0]\r
+ ** - 0 = HCLK = Master Clock\r
+ ** - 1 = HCLK = Master Clock / 2\r
+ ** - 2 = HCLK = Master Clock / 3\r
+ ** - 3 = HCLK = Master Clock / 4\r
+ ** - 4 = HCLK = Master Clock / 6\r
+ ** - 5 = HCLK = Master Clock / 8\r
+ ** - 6 = HCLK = Master Clock / 16\r
+ ** - 7 = (reserved)\r
+ ******************************************************************************/    \r
+#define BSC_PSR_Val           0x00000000    // <<< Define BSC_PSR here\r
+ \r
+/**\r
+ ******************************************************************************\r
+ ** \brief APB0 Prescaler Register value definition\r
+ **        <i>(USER SETTING)</i>\r
+ ** \r
+ ** APBC0_PSR\r
+ **\r
+ ** Bit#7-2 : (reserved)\r
+ **\r
+ ** Bit#1-0 : BSR[2:0] \r
+ ** - 0 = PCLK0 = HCLK\r
+ ** - 1 = PCLK0 = HCLK / 2\r
+ ** - 2 = PCLK0 = HCLK / 4\r
+ ** - 3 = PCLK0 = HCLK / 8\r
+ ******************************************************************************/    \r
+#define APBC0_PSR_Val         0x00000001     // <<< Define APBC0_PSR here\r
+   \r
+/**\r
+ ******************************************************************************\r
+ ** \brief APB1 Prescaler Register value definition\r
+ **        <i>(USER SETTING)</i>\r
+ ** \r
+ ** APBC1_PSR\r
+ **\r
+ ** Bit#7 : APBC1EN\r
+ ** - 0 = Disable PCLK1 output\r
+ ** - 1 = Enables PCLK1 (default)\r
+ **\r
+ ** Bit#6-5 : (reserved)\r
+ **\r
+ ** Bit#4 : APBC1RST\r
+ ** - 0 = APB1 bus reset, inactive (default)\r
+ ** - 1 = APB1 bus reset, active  \r
+ **\r
+ ** Bit#3-2 : (reserved)\r
+ **\r
+ ** Bit#1-0 : APBC1[2:0]\r
+ ** - 0 = PCLK1 = HCLK\r
+ ** - 1 = PCLK1 = HCLK / 2\r
+ ** - 2 = PCLK1 = HCLK / 4\r
+ ** - 3 = PCLK1 = HCLK / 8\r
+ ******************************************************************************/     \r
+#define APBC1_PSR_Val         0x00000081    // <<< Define APBC1_PSR here\r
+   \r
+/**\r
+ ******************************************************************************\r
+ ** \brief APB2 Prescaler Register value definition\r
+ **        <i>(USER SETTING)</i>\r
+ ** \r
+ ** APBC2_PSR\r
+ **\r
+ ** Bit#7 : APBC2EN\r
+ ** - 0 = Disable PCLK2 output\r
+ ** - 1 = Enables PCLK2 (default)\r
+ **\r
+ ** Bit#6-5 : (reserved)\r
+ ** \r
+ ** Bit#4 : APBC2RST\r
+ ** - 0 = APB2 bus reset, inactive (default)\r
+ ** - 1 = APB2 bus reset, active  \r
+ **\r
+ ** Bit#3-2 : (reserved)\r
+ **\r
+ ** Bit#1-0 : APBC2[1:0]\r
+ ** - 0 = PCLK2 = HCLK\r
+ ** - 1 = PCLK2 = HCLK / 2\r
+ ** - 2 = PCLK2 = HCLK / 4\r
+ ** - 3 = PCLK2 = HCLK / 8\r
+ ******************************************************************************/    \r
+#define APBC2_PSR_Val         0x00000081    // <<< Define APBC2_PSR here\r
+\r
+/**\r
+ ******************************************************************************\r
+ ** \brief Software Watchdog Clock Prescaler Register value definition\r
+ **        <i>(USER SETTING)</i>\r
+ ** \r
+ ** SWC_PSR\r
+ **\r
+ ** Bit#7 : TESTB\r
+ ** - 0 = (not allowed)\r
+ ** - 1 = (always write "1" to this bit)\r
+ **\r
+ ** Bit#6-2 : (reserved)\r
+ **\r
+ ** Bit#1-0 : SWDS[2:0]\r
+ ** - 0 = SWDGOGCLK = PCLK0\r
+ ** - 1 = SWDGOGCLK = PCLK0 / 2\r
+ ** - 2 = SWDGOGCLK = PCLK0 / 4\r
+ ** - 3 = SWDGOGCLK = PCLK0 / 8\r
+ ******************************************************************************/  \r
+#define SWC_PSR_Val           0x00000003    // <<< Define SWC_PSR here\r
+\r
+/**\r
+ ******************************************************************************\r
+ ** \brief Trace Clock Prescaler Register value definition\r
+ **        <i>(USER SETTING)</i>\r
+ ** \r
+ ** TTC_PSR\r
+ **\r
+ ** Bit#7-1 : (reserved)\r
+ **\r
+ ** Bit#0 : TTC\r
+ ** - 0 = TPIUCLK = HCLK\r
+ ** - 1 = TPIUCLK = HCLK / 2\r
+ ******************************************************************************/  \r
+#define TTC_PSR_Val           0x00000000    // <<< Define TTC_PSR here\r
+ \r
+/**\r
+ ******************************************************************************\r
+ ** \brief Clock Stabilization Wait Time Register value definition\r
+ **        <i>(USER SETTING)</i>\r
+ ** \r
+ ** CSW_TMR\r
+ **\r
+ ** Bit#7 : (reserved)\r
+ **\r
+ ** Bit#6-4 : SOWT[2:0]\r
+ ** - 0 = ~10.3 ms (default)\r
+ ** - 1 = ~20.5 ms\r
+ ** - 2 = ~41 ms\r
+ ** - 3 = ~82 ms\r
+ ** - 4 = ~164 ms\r
+ ** - 5 = ~327 ms\r
+ ** - 6 = ~655 ms\r
+ ** - 7 = ~1.31 s \r
+ **\r
+ ** Bit#3-0 : MOWT[3:0]\r
+ ** - 0 = ~500 ns (default)\r
+ ** - 1 = ~8 us\r
+ ** - 2 = ~16 us\r
+ ** - 3 = ~32 us\r
+ ** - 4 = ~64 us\r
+ ** - 5 = ~128 us\r
+ ** - 6 = ~256 us\r
+ ** - 7 = ~512 us\r
+ ** - 8 = ~1.0 ms\r
+ ** - 9 = ~2.0 ms\r
+ ** - 10 = ~4.0 ms\r
+ ** - 11 = ~8.0 ms\r
+ ** - 12 = ~33.0 ms\r
+ ** - 13 = ~131 ms\r
+ ** - 14 = ~524 ms\r
+ ** - 15 = ~2.0 s\r
+ ******************************************************************************/     \r
+#define CSW_TMR_Val           0x0000005C    // <<< Define CSW_TMR here\r
+\r
+/**\r
+ ******************************************************************************\r
+ ** \brief PLL Clock Stabilization Wait Time Setup Register value definition\r
+ **        <i>(USER SETTING)</i>\r
+ ** \r
+ ** PSW_TMR\r
+ **\r
+ ** Bit#7-5 : (reserved)\r
+ **\r
+ ** Bit#4 : PINC\r
+ ** - 0 = Selects CLKMO (main oscillation) (default)\r
+ ** - 1 = (setting diabled)\r
+ **\r
+ ** Bit#3 : (reserved)\r
+ **\r
+ ** Bit#2-0 : POWT[2:0]\r
+ ** - 0 = ~128 us (default) \r
+ ** - 1 = ~256 us\r
+ ** - 2 = ~512 us\r
+ ** - 3 = ~1.02 ms\r
+ ** - 4 = ~2.05 ms\r
+ ** - 5 = ~4.10 ms\r
+ ** - 6 = ~8.20 ms\r
+ ** - 7 = ~16.40 ms\r
+ ******************************************************************************/    \r
+#define PSW_TMR_Val           0x00000000    // <<< Define PSW_TMR here\r
+\r
+/**\r
+ ******************************************************************************\r
+ ** \brief PLL Control Register 1 value definition\r
+ **        <i>(USER SETTING)</i>\r
+ ** \r
+ ** PLL_CTL1\r
+ **\r
+ ** Bit#7-4 : PLLK[3:0]\r
+ ** - 0 = Division(PLLK) = 1/1 (default)\r
+ ** - 1 = Division(PLLK) = 1/2\r
+ ** - 2 = Division(PLLK) = 1/3\r
+ ** - . . .\r
+ ** - 15 = Division(PLLK) = 1/16\r
+ **\r
+ ** Bit#3-0 : PLLM[3:0]\r
+ ** - 0 = Division(PLLM) = 1/1 (default)\r
+ ** - 1 = Division(PLLM) = 1/2\r
+ ** - 2 = Division(PLLM) = 1/3\r
+ ** - . . .\r
+ ** - 15 = Division(PLLM) = 1/16\r
+ ******************************************************************************/    \r
+#define PLL_CTL1_Val          0x00000004    // <<< Define PLL_CTL1 here\r
+\r
+/**\r
+ ******************************************************************************\r
+ ** \brief PLL Control Register 2 value definition\r
+ **        <i>(USER SETTING)</i>\r
+ ** \r
+ ** PLL_CTL2\r
+ **\r
+ ** Bit#7-6 : (reserved)\r
+ **\r
+ ** Bit#5-0 : PLLM[5:0]\r
+ ** - 0 = Division(PLLN) = 1/1 (default)\r
+ ** - 1 = Division(PLLN) = 1/2\r
+ ** - 2 = Division(PLLN) = 1/3\r
+ ** - . . .\r
+ ** - 63 = Division(PLLN) = 1/64\r
+ ******************************************************************************/    \r
+#define PLL_CTL2_Val          0x00000009    // <<< Define PLL_CTL2 here\r
+   \r
+/**\r
+ ******************************************************************************\r
+ ** \brief Hardware Watchdog disable definition\r
+ **        <i>(USER SETTING)</i>\r
+ **\r
+ ** - 0 = Hardware Watchdog enable\r
+ ** - 1 = Hardware Watchdog disable\r
+ ******************************************************************************/  \r
+#define HWWD_DISABLE          1   // <<< Define HW Watach dog enable here\r
+\r
+/**\r
+ ******************************************************************************\r
+ ** \brief Trimming CR\r
+ **        <i>(USER SETTING)</i>\r
+ **\r
+ ** - 0 = CR is not trimmed at startup\r
+ ** - 1 = CR is trimmed at startup\r
+ ******************************************************************************/  \r
+#define CR_TRIM_SETUP         1   // <<< Define CR trimming at startup enable here\r
+\r
+   \r
+/******************************************************************************/\r
+/*                                                                            */\r
+/*                         END OF USER SETTINGS HERE                          */\r
+/*                         =========================                          */ \r
+/*                                                                            */\r
+/******************************************************************************/\r
+\r
+/******************************************************************************/\r
+/* Device dependent System Clock absolute maximum ranges                      */\r
+/******************************************************************************/\r
+\r
+/**\r
+ ******************************************************************************\r
+ ** \brief Internal High-Speed CR Oscillator Frequency (in Hz, [value]UL)\r
+ **        <i>(USER SETTING)</i>\r
+ ******************************************************************************/    \r
+#define __CLKHC        ( 4000000UL)         /* Internal   4MHz CR Oscillator  */\r
+   \r
+/**\r
+ ******************************************************************************\r
+ ** \brief Internal Low-Speed CR Oscillator Frequency (in Hz, [value]UL)\r
+ **        <i>(USER SETTING)</i>\r
+ ******************************************************************************/ \r
+#define __CLKLC        (  100000UL)         /* Internal 100KHz CR Oscillator  */  \r
+\r
+/**\r
+ ******************************************************************************\r
+ ** \brief Any case minimum Main Clock frequency (in Hz, [value]UL)\r
+ **        <i>(DEVICE DEPENDENT SETTING)</i>\r
+ ******************************************************************************/ \r
+#define __CLKMOMIN    (  4000000UL)\r
+   \r
+/**\r
+ ******************************************************************************\r
+ ** \brief Maximum Main Clock frequency using external clock\r
+ **        <i>(DEVICE DEPENDENT SETTING)</i>\r
+ ******************************************************************************/ \r
+#define __CLKMOMAX    ( 48000000UL)\r
+\r
+/**\r
+ ******************************************************************************\r
+ ** \brief Any case minimum Sub Clock frequency\r
+ **        <i>(DEVICE DEPENDENT SETTING)</i>\r
+ ******************************************************************************/ \r
+#define __CLKSOMIN    (    32000UL)\r
+   \r
+/**\r
+ ******************************************************************************\r
+ ** \brief Maximum Sub Clock frequency using external clock\r
+ **        <i>(DEVICE DEPENDENT SETTING)</i>\r
+ ******************************************************************************/ \r
+#define __CLKSOMAX    (   100000UL)\r
+   \r
+/**\r
+ ******************************************************************************\r
+ ** \brief Absolute minimum PLL input frequency\r
+ **        <i>(DEVICE DEPENDENT SETTING)</i>\r
+ ******************************************************************************/ \r
+#define __PLLCLKINMIN (  4000000UL)\r
+   \r
+/**\r
+ ******************************************************************************\r
+ ** \brief Absolute maximum PLL input frequency\r
+ **        <i>(DEVICE DEPENDENT SETTING)</i>\r
+ ******************************************************************************/ \r
+#define __PLLCLKINMAX ( 16000000UL)\r
+\r
+/**\r
+ ******************************************************************************\r
+ ** \brief Absolute minimum PLL oscillation frequency\r
+ **        <i>(DEVICE DEPENDENT SETTING)</i>\r
+ ******************************************************************************/ \r
+#define __PLLCLKMIN   (200000000UL)\r
+   \r
+/**\r
+ ******************************************************************************\r
+ ** \brief Absolute maximum PLL oscillation  frequency\r
+ **        <i>(DEVICE DEPENDENT SETTING)</i>\r
+ ******************************************************************************/ \r
+#define __PLLCLKMAX   (300000000UL)\r
+\r
+/**\r
+ ******************************************************************************\r
+ ** \brief Absolute maximum System Clock frequency (HCLK)\r
+ **        <i>(DEVICE DEPENDENT SETTING)</i>\r
+ ******************************************************************************/ \r
+#define __HCLKMAX     ( 40000000UL)\r
+\r
+/**\r
+ ******************************************************************************\r
+ ** \brief Preprocessor macro for checking range (clock settings)\r
+ ******************************************************************************/ \r
+#define CHECK_RANGE(val, min, max)                ((val < min) || (val > max))\r
+   \r
+/**\r
+ ******************************************************************************\r
+ ** \brief Preprocessor macro for checking bits with mask (clock settings)\r
+ ******************************************************************************/ \r
+#define CHECK_RSVD(val, mask)                     (val & mask)\r
+\r
+\r
+/******************************************************************************/\r
+/* Check register settings                                                    */\r
+/******************************************************************************/\r
+#if (CHECK_RSVD((SCM_CTL_Val),    ~0x000000FA))\r
+   #error "SCM_CTL: Invalid values of reserved bits!"\r
+#endif\r
+\r
+#if ((SCM_CTL_Val & 0xE0) == 0x40) && ((SCM_CTL_Val & 0x10) != 0x10)\r
+   #error "SCM_CTL: CLKPLL is selected but PLL is not enabled!"\r
+#endif\r
+\r
+#if (CHECK_RSVD((CSW_TMR_Val),    ~0x0000007F))\r
+   #error "CSW_TMR: Invalid values of reserved bits!"\r
+#endif\r
+\r
+#if ((SCM_CTL_Val & 0x10))       /* if PLL is used */\r
+  #if (CHECK_RSVD((PSW_TMR_val),  ~0x00000007))\r
+     #error "PSW_TMR: Invalid values of reserved bits!"\r
+  #endif\r
+\r
+  #if (CHECK_RSVD((PLL_CTL1_Val), ~0x000000FF))\r
+     #error "PLL_CTL1: Invalid values of reserved bits!"\r
+  #endif\r
+\r
+  #if (CHECK_RSVD((PLL_CTL2_Val), ~0x0000003F))\r
+    #error "PLL_CTL2: Invalid values of reserved bits!"\r
+  #endif\r
+#endif\r
+\r
+#if (CHECK_RSVD((BSC_PSR_Val),    ~0x00000007))\r
+  #error "BSC_PSR: Invalid values of reserved bits!"\r
+#endif\r
+\r
+#if (CHECK_RSVD((APBC0_PSR_Val),  ~0x00000003))\r
+  #error "APBC0_PSR: Invalid values of reserved bits!"\r
+#endif\r
+\r
+#if (CHECK_RSVD((APBC1_PSR_Val),  ~0x00000083))\r
+  #error "APBC1_PSR: Invalid values of reserved bits!"\r
+#endif\r
+\r
+#if (CHECK_RSVD((APBC2_PSR_Val),  ~0x00000083))\r
+  #error "APBC2_PSR: Invalid values of reserved bits!"\r
+#endif\r
+\r
+#if (CHECK_RSVD((SWC_PSR_Val),    ~0x00000003))\r
+  #error "SWC_PSR: Invalid values of reserved bits!"\r
+#endif\r
+\r
+#if (CHECK_RSVD((TTC_PSR_Val),    ~0x00000001))\r
+  #error "TTC_PSR: Invalid values of reserved bits!"\r
+#endif\r
+\r
+/******************************************************************************/\r
+/* Define clocks with checking settings                                       */\r
+/******************************************************************************/\r
+\r
+/**\r
+ ******************************************************************************\r
+ ** \brief Calculate PLL K factor from settings\r
+ ******************************************************************************/\r
+#define __PLLK         (((PLL_CTL1_Val >> 4) & 0x0F) + 1)\r
+\r
+/**\r
+ ******************************************************************************\r
+ ** \brief Calculate PLL N factor from settings\r
+ ******************************************************************************/\r
+#define __PLLN         (((PLL_CTL2_Val     ) & 0x1F) + 1)\r
+\r
+/**\r
+ ******************************************************************************\r
+ ** \brief Calculate PLL M factor from settings\r
+ ******************************************************************************/\r
+#define __PLLM         (((PLL_CTL1_Val     ) & 0x0F) + 1)\r
+\r
+/**\r
+ ******************************************************************************\r
+ ** \brief Calculate PLL output frequency from settings\r
+ ******************************************************************************/\r
+#define __PLLCLK       ((__CLKMO  * __PLLN) / __PLLK)\r
+\r
+/******************************************************************************/\r
+/* Determine core clock frequency according to settings                       */\r
+/******************************************************************************/\r
+\r
+/**\r
+ ******************************************************************************\r
+ ** \brief Define Master Clock from settings\r
+ ******************************************************************************/\r
+#if   (((SCM_CTL_Val >> 5) & 0x07) == 0)\r
+  #define __MASTERCLK     (__CLKHC)\r
+#elif (((SCM_CTL_Val >> 5) & 0x07) == 1)\r
+  #define __MASTERCLK     (__CLKMO)\r
+#elif (((SCM_CTL_Val >> 5) & 0x07) == 2)\r
+  #define __MASTERCLK     (__PLLCLK)\r
+#elif (((SCM_CTL_Val >> 5) & 0x07) == 4)\r
+  #define __MASTERCLK     (__CLKLC)\r
+#elif (((SCM_CTL_Val >> 5) & 0x07) == 5)\r
+  #define __MASTERCLK     (__CLKSO)\r
+#else\r
+  #define __MASTERCLK     (0UL)\r
+#endif\r
+\r
+/**\r
+ ******************************************************************************\r
+ ** \brief Define System Clock Frequency (Core Clock) from settings\r
+ ******************************************************************************/\r
+#if   ((BSC_PSR_Val & 0x07) == 0)\r
+  #define __HCLK         (__MASTERCLK / 1)\r
+#elif ((BSC_PSR_Val & 0x07) == 1)\r
+  #define __HCLK         (__MASTERCLK / 2)\r
+#elif ((BSC_PSR_Val & 0x07) == 2)\r
+  #define __HCLK         (__MASTERCLK / 3)\r
+#elif ((BSC_PSR_Val & 0x07) == 3)\r
+  #define __HCLK         (__MASTERCLK / 4)\r
+#elif ((BSC_PSR_Val & 0x07) == 4)\r
+  #define __HCLK         (__MASTERCLK / 6)\r
+#elif ((BSC_PSR_Val & 0x07) == 5)\r
+  #define __HCLK         (__MASTERCLK / 8)\r
+#elif ((BSC_PSR_Val & 0x07) == 6)\r
+  #define __HCLK         (__MASTERCLK /16)\r
+#else\r
+  #define __HCLK         (0UL)\r
+#endif\r
+\r
+/******************************************************************************/\r
+/* HCLK range check                                                           */\r
+/******************************************************************************/\r
+#if (CHECK_RANGE(__CLKMO, __CLKMOMIN, __CLKMOMAX) != 0)\r
+  #error "Main Oscillator Clock (CLKMO) out of range!"\r
+#endif   \r
+\r
+#if (CHECK_RANGE(__CLKSO, __CLKSOMIN, __CLKSOMAX) != 0)\r
+  #error "Sub Oscillator Clock (CLKMO) out of range!"\r
+#endif   \r
+\r
+#if (CHECK_RANGE((__CLKMO / __PLLK), __PLLCLKINMIN, __PLLCLKINMAX) != 0)\r
+  #error "PLL input frequency out of range!"\r
+#endif  \r
+\r
+#if (CHECK_RANGE(((__CLKMO * __PLLN * __PLLM) / __PLLK), __PLLCLKMIN, __PLLCLKMAX) != 0)\r
+  #error "PLL oscillation frequency out of range!"\r
+#endif  \r
+   \r
+#if (CHECK_RANGE(__HCLK, 0, __HCLKMAX) != 0)\r
+  #error "System Clock (HCLK) out of range!"\r
+#endif\r
+   \r
+/******************************************************************************/\r
+/* Global function prototypes ('extern', definition in C source)              */\r
+/******************************************************************************/\r
+\r
+extern uint32_t SystemCoreClock;          // System Clock Frequency (Core Clock)\r
+   \r
+extern void SystemInit (void);            // Initialize the system\r
+\r
+extern void SystemCoreClockUpdate (void); // Update SystemCoreClock variable\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __SYSTEM_MB9AF31X_H */\r

diff --git a/Demo/CORTEX_MB9A310_IAR_Keil/ParTest.c b/Demo/CORTEX_MB9A310_IAR_Keil/ParTest.c
new file mode 100644 (file)
index 0000000..c73ba43
--- /dev/null
+++ b/Demo/CORTEX_MB9A310_IAR_Keil/ParTest.c
@@ -0,0 +1,154 @@
+/*\r
+    FreeRTOS V7.0.1 - Copyright (C) 2011 Real Time Engineers Ltd.\r
+       \r
+\r
+    ***************************************************************************\r
+     *                                                                       *\r
+     *    FreeRTOS tutorial books are available in pdf and paperback.        *\r
+     *    Complete, revised, and edited pdf reference manuals are also       *\r
+     *    available.                                                         *\r
+     *                                                                       *\r
+     *    Purchasing FreeRTOS documentation will not only help you, by       *\r
+     *    ensuring you get running as quickly as possible and with an        *\r
+     *    in-depth knowledge of how to use FreeRTOS, it will also help       *\r
+     *    the FreeRTOS project to continue with its mission of providing     *\r
+     *    professional grade, cross platform, de facto standard solutions    *\r
+     *    for microcontrollers - completely free of charge!                  *\r
+     *                                                                       *\r
+     *    >>> See http://www.FreeRTOS.org/Documentation for details. <<<     *\r
+     *                                                                       *\r
+     *    Thank you for using FreeRTOS, and thank you for your support!      *\r
+     *                                                                       *\r
+    ***************************************************************************\r
+\r
+\r
+    This file is part of the FreeRTOS distribution.\r
+\r
+    FreeRTOS is free software; you can redistribute it and/or modify it under\r
+    the terms of the GNU General Public License (version 2) as published by the\r
+    Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+    >>>NOTE<<< The modification to the GPL is included to allow you to\r
+    distribute a combined work that includes FreeRTOS without being obliged to\r
+    provide the source code for proprietary components outside of the FreeRTOS\r
+    kernel.  FreeRTOS is distributed in the hope that it will be useful, but\r
+    WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\r
+    more details. You should have received a copy of the GNU General Public\r
+    License and the FreeRTOS license exception along with FreeRTOS; if not it\r
+    can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
+    by writing to Richard Barry, contact details for whom are available on the\r
+    FreeRTOS WEB site.\r
+\r
+    1 tab == 4 spaces!\r
+\r
+    http://www.FreeRTOS.org - Documentation, latest information, license and\r
+    contact details.\r
+\r
+    http://www.SafeRTOS.com - A version that is certified for use in safety\r
+    critical systems.\r
+\r
+    http://www.OpenRTOS.com - Commercial support, development, porting,\r
+    licensing and training services.\r
+*/\r
+\r
+/*-----------------------------------------------------------\r
+ * Simple parallel port IO routines.\r
+ *-----------------------------------------------------------*/\r
+\r
+/* Kernel includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/* Fujitsu drivers/libraries. */\r
+#include "mcu.h"\r
+\r
+/* Only the LEDs on one of the two seven segment displays are used. */\r
+#define partstMAX_LEDS         8\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestInitialise( void )\r
+{\r
+       /* Analog inputs are not used on the LED outputs. */\r
+       FM3_GPIO->ADE  = 0x0000;\r
+\r
+       /* Set to output. */\r
+       FM3_GPIO->DDR1 |= 0xFFFF;\r
+       FM3_GPIO->DDR3 |= 0xFFFF;\r
+       \r
+       /* Set as GPIO. */\r
+       FM3_GPIO->PFR1 &= 0x0000;\r
+       FM3_GPIO->PFR3 &= 0x0000;\r
+\r
+       /* Start with all LEDs off. */\r
+       FM3_GPIO->PDOR1 = 0xFFFF;\r
+       FM3_GPIO->PDOR1 = 0xFFFF;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue )\r
+{\r
+       if( uxLED < partstMAX_LEDS )\r
+       {\r
+               /* A critical section is used as the LEDs are also accessed from an\r
+               interrupt. */\r
+               taskENTER_CRITICAL();\r
+               {\r
+                       if( xValue == pdTRUE )\r
+                       {\r
+                               FM3_GPIO->PDOR1 &= ~( 1UL << uxLED );\r
+                       }\r
+                       else\r
+                       {\r
+                               FM3_GPIO->PDOR1 |= ( 1UL << uxLED );\r
+                       }\r
+               }\r
+               taskEXIT_CRITICAL();\r
+       }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestSetLEDFromISR( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue )\r
+{\r
+unsigned portBASE_TYPE uxInterruptFlags;\r
+\r
+       uxInterruptFlags = portSET_INTERRUPT_MASK_FROM_ISR();\r
+       {\r
+               if( uxLED < partstMAX_LEDS )\r
+               {\r
+                       if( xValue == pdTRUE )\r
+                       {\r
+                               FM3_GPIO->PDOR1 &= ~( 1UL << uxLED );\r
+                       }\r
+                       else\r
+                       {\r
+                               FM3_GPIO->PDOR1 |= ( 1UL << uxLED );\r
+                       }\r
+               }\r
+       }\r
+       portCLEAR_INTERRUPT_MASK_FROM_ISR( uxInterruptFlags );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestToggleLED( unsigned portBASE_TYPE uxLED )\r
+{\r
+       if( uxLED < partstMAX_LEDS )\r
+       {\r
+               /* A critical section is used as the LEDs are also accessed from an\r
+               interrupt. */\r
+               taskENTER_CRITICAL();\r
+               {\r
+                       if( ( FM3_GPIO->PDOR1 & ( 1UL << uxLED ) ) != 0UL )\r
+                       {\r
+                               FM3_GPIO->PDOR1 &= ~( 1UL << uxLED );\r
+                       }\r
+                       else\r
+                       {\r
+                               FM3_GPIO->PDOR1 |= ( 1UL << uxLED );\r
+                       }\r
+               }\r
+               taskEXIT_CRITICAL();\r
+       }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r

diff --git a/Demo/CORTEX_MB9A310_IAR_Keil/RTOSDemo_IAR.dep b/Demo/CORTEX_MB9A310_IAR_Keil/RTOSDemo_IAR.dep
new file mode 100644 (file)
index 0000000..6539bc2
--- /dev/null
+++ b/Demo/CORTEX_MB9A310_IAR_Keil/RTOSDemo_IAR.dep
@@ -0,0 +1,1204 @@
+<?xml version="1.0" encoding="iso-8859-1"?>\r
+\r
+<project>\r
+  <fileVersion>2</fileVersion>\r
+  <fileChecksum>993780045</fileChecksum>\r
+  <configuration>\r
+    <name>Blinky</name>\r
+    <outputs>\r
+      <file>$TOOLKIT_DIR$\inc\c\ysizet.h</file>\r
+      <file>$PROJ_DIR$\FreeRTOSConfig.h</file>\r
+      <file>$PROJ_DIR$\..\..\Source\include\mpu_wrappers.h</file>\r
+      <file>$PROJ_DIR$\Blinky\Obj\queue.o</file>\r
+      <file>$PROJ_DIR$\..\..\Source\portable\IAR\ARM_CM3\port.c</file>\r
+      <file>$PROJ_DIR$\..\..\Source\include\timers.h</file>\r
+      <file>$PROJ_DIR$\..\..\Source\tasks.c</file>\r
+      <file>$PROJ_DIR$\Blinky\Obj\system_mb9af31x.o</file>\r
+      <file>$PROJ_DIR$\..\..\Source\include\StackMacros.h</file>\r
+      <file>$PROJ_DIR$\Blinky\Obj\startup_mb9af31x.o</file>\r
+      <file>$PROJ_DIR$\Fujitu_source\system_mb9af31x.c</file>\r
+      <file>$PROJ_DIR$\..\..\Source\portable\MemMang\heap_2.c</file>\r
+      <file>$PROJ_DIR$\Blinky\Obj\main_blinky.pbi</file>\r
+      <file>$PROJ_DIR$\..\..\Source\portable\IAR\ARM_CM3\portasm.s</file>\r
+      <file>$TOOLKIT_DIR$\inc\c\DLib_Defaults.h</file>\r
+      <file>$TOOLKIT_DIR$\inc\c\xencoding_limits.h</file>\r
+      <file>$TOOLKIT_DIR$\inc\c\ycheck.h</file>\r
+      <file>$TOOLKIT_DIR$\inc\c\stddef.h</file>\r
+      <file>$PROJ_DIR$\Fujitu_source\core_cm3.c</file>\r
+      <file>$PROJ_DIR$\Blinky\Obj\timers.pbi</file>\r
+      <file>$PROJ_DIR$\Blinky\Obj\RTOSDemo_IAR.pbd</file>\r
+      <file>$PROJ_DIR$\..\..\Source\include\portable.h</file>\r
+      <file>$PROJ_DIR$\Blinky\Obj\list.pbi</file>\r
+      <file>$PROJ_DIR$\Blinky\Obj\heap_2.o</file>\r
+      <file>$PROJ_DIR$\..\..\Source\queue.c</file>\r
+      <file>$PROJ_DIR$\main_blinky.c</file>\r
+      <file>$TOOLKIT_DIR$\inc\c\stdlib.h</file>\r
+      <file>$PROJ_DIR$\..\..\Source\include\projdefs.h</file>\r
+      <file>$PROJ_DIR$\Blinky\Obj\port.o</file>\r
+      <file>$TOOLKIT_DIR$\inc\c\DLib_Threads.h</file>\r
+      <file>$TOOLKIT_DIR$\inc\c\DLib_Product_string.h</file>\r
+      <file>$PROJ_DIR$\Blinky\Obj\main_blinky.o</file>\r
+      <file>$PROJ_DIR$\Blinky\Obj\system_mb9af31x.pbi</file>\r
+      <file>$TOOLKIT_DIR$\inc\c\stdint.h</file>\r
+      <file>$PROJ_DIR$\Blinky\Obj\portasm.o</file>\r
+      <file>$PROJ_DIR$\Blinky\Obj\timers.o</file>\r
+      <file>$PROJ_DIR$\Fujitu_source\startup_iar\startup_mb9af31x.s</file>\r
+      <file>$TOOLKIT_DIR$\inc\c\yvals.h</file>\r
+      <file>$TOOLKIT_DIR$\inc\c\ystdio.h</file>\r
+      <file>$PROJ_DIR$\serial.c</file>\r
+      <file>$PROJ_DIR$\Blinky\Obj\heap_2.pbi</file>\r
+      <file>$PROJ_DIR$\main-full.c</file>\r
+      <file>$PROJ_DIR$\Blinky\Obj\list.o</file>\r
+      <file>$PROJ_DIR$\..\..\Source\include\task.h</file>\r
+      <file>$PROJ_DIR$\Blinky\Obj\queue.pbi</file>\r
+      <file>$PROJ_DIR$\Blinky\Exe\RTOSDemo_IAR.out</file>\r
+      <file>$PROJ_DIR$\..\..\Source\include\list.h</file>\r
+      <file>$TOOLKIT_DIR$\inc\c\stdio.h</file>\r
+      <file>$PROJ_DIR$\ParTest.c</file>\r
+      <file>$PROJ_DIR$\Blinky\Obj\tasks.o</file>\r
+      <file>$PROJ_DIR$\Blinky\Obj\port.pbi</file>\r
+      <file>$PROJ_DIR$\Blinky\Obj\tasks.pbi</file>\r
+      <file>$PROJ_DIR$\..\..\Source\list.c</file>\r
+      <file>$TOOLKIT_DIR$\inc\c\DLib_Product.h</file>\r
+      <file>$PROJ_DIR$\..\..\Source\timers.c</file>\r
+      <file>$PROJ_DIR$\Blinky\Obj\core_cm3.o</file>\r
+      <file>$PROJ_DIR$\..\..\Source\include\FreeRTOS.h</file>\r
+      <file>$PROJ_DIR$\..\..\Source\portable\IAR\ARM_CM3\portmacro.h</file>\r
+      <file>$PROJ_DIR$\Blinky\Obj\core_cm3.pbi</file>\r
+      <file>$TOOLKIT_DIR$\inc\c\string.h</file>\r
+    </outputs>\r
+    <file>\r
+      <name>$PROJ_DIR$\..\..\Source\portable\IAR\ARM_CM3\port.c</name>\r
+      <outputs>\r
+        <tool>\r
+          <name>ICCARM</name>\r
+          <file> 28</file>\r
+        </tool>\r
+        <tool>\r
+          <name>BICOMP</name>\r
+          <file> 50</file>\r
+        </tool>\r
+      </outputs>\r
+      <inputs>\r
+        <tool>\r
+          <name>BICOMP</name>\r
+          <file> 56 17 16 37 14 53 15 29 0 27 1 33 21 57 2 43 46</file>\r
+        </tool>\r
+      </inputs>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\..\..\Source\tasks.c</name>\r
+      <outputs>\r
+        <tool>\r
+          <name>ICCARM</name>\r
+          <file> 49</file>\r
+        </tool>\r
+        <tool>\r
+          <name>BICOMP</name>\r
+          <file> 51</file>\r
+        </tool>\r
+      </outputs>\r
+      <inputs>\r
+        <tool>\r
+          <name>BICOMP</name>\r
+          <file> 47 16 37 14 53 15 29 0 38 26 59 30 56 17 27 1 33 21 57 2 43 46 5 8</file>\r
+        </tool>\r
+      </inputs>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\Fujitu_source\system_mb9af31x.c</name>\r
+      <outputs>\r
+        <tool>\r
+          <name>ICCARM</name>\r
+          <file> 7</file>\r
+        </tool>\r
+        <tool>\r
+          <name>BICOMP</name>\r
+          <file> 32</file>\r
+        </tool>\r
+      </outputs>\r
+    </file>\r
+    <file>\r
+      <name>[ROOT_NODE]</name>\r
+      <outputs>\r
+        <tool>\r
+          <name>ILINK</name>\r
+          <file> 45</file>\r
+        </tool>\r
+      </outputs>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\..\..\Source\portable\MemMang\heap_2.c</name>\r
+      <outputs>\r
+        <tool>\r
+          <name>ICCARM</name>\r
+          <file> 23</file>\r
+        </tool>\r
+        <tool>\r
+          <name>BICOMP</name>\r
+          <file> 40</file>\r
+        </tool>\r
+      </outputs>\r
+      <inputs>\r
+        <tool>\r
+          <name>BICOMP</name>\r
+          <file> 26 16 37 14 53 15 29 0 56 17 27 1 33 21 57 2 43 46</file>\r
+        </tool>\r
+      </inputs>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\..\..\Source\portable\IAR\ARM_CM3\portasm.s</name>\r
+      <outputs>\r
+        <tool>\r
+          <name>AARM</name>\r
+          <file> 34</file>\r
+        </tool>\r
+      </outputs>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\Fujitu_source\core_cm3.c</name>\r
+      <outputs>\r
+        <tool>\r
+          <name>ICCARM</name>\r
+          <file> 55</file>\r
+        </tool>\r
+        <tool>\r
+          <name>BICOMP</name>\r
+          <file> 58</file>\r
+        </tool>\r
+      </outputs>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\..\..\Source\queue.c</name>\r
+      <outputs>\r
+        <tool>\r
+          <name>ICCARM</name>\r
+          <file> 3</file>\r
+        </tool>\r
+        <tool>\r
+          <name>BICOMP</name>\r
+          <file> 44</file>\r
+        </tool>\r
+      </outputs>\r
+      <inputs>\r
+        <tool>\r
+          <name>BICOMP</name>\r
+          <file> 26 16 37 14 53 15 29 0 59 30 56 17 27 1 33 21 57 2 43 46</file>\r
+        </tool>\r
+      </inputs>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\main_blinky.c</name>\r
+      <outputs>\r
+        <tool>\r
+          <name>ICCARM</name>\r
+          <file> 31</file>\r
+        </tool>\r
+        <tool>\r
+          <name>BICOMP</name>\r
+          <file> 12</file>\r
+        </tool>\r
+      </outputs>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\Fujitu_source\startup_iar\startup_mb9af31x.s</name>\r
+      <outputs>\r
+        <tool>\r
+          <name>AARM</name>\r
+          <file> 9</file>\r
+        </tool>\r
+      </outputs>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\..\..\Source\list.c</name>\r
+      <outputs>\r
+        <tool>\r
+          <name>ICCARM</name>\r
+          <file> 42</file>\r
+        </tool>\r
+        <tool>\r
+          <name>BICOMP</name>\r
+          <file> 22</file>\r
+        </tool>\r
+      </outputs>\r
+      <inputs>\r
+        <tool>\r
+          <name>BICOMP</name>\r
+          <file> 26 16 37 14 53 15 29 0 56 17 27 1 33 21 57 2 46</file>\r
+        </tool>\r
+      </inputs>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\..\..\Source\timers.c</name>\r
+      <outputs>\r
+        <tool>\r
+          <name>ICCARM</name>\r
+          <file> 35</file>\r
+        </tool>\r
+        <tool>\r
+          <name>BICOMP</name>\r
+          <file> 19</file>\r
+        </tool>\r
+      </outputs>\r
+    </file>\r
+  </configuration>\r
+  <configuration>\r
+    <name>Full</name>\r
+    <outputs>\r
+      <file>$TOOLKIT_DIR$\inc\c\ysizet.h</file>\r
+      <file>$PROJ_DIR$\FreeRTOSConfig.h</file>\r
+      <file>$PROJ_DIR$\Full\Obj\countsem.o</file>\r
+      <file>$PROJ_DIR$\..\Common\include\death.h</file>\r
+      <file>$PROJ_DIR$\..\Common\include\flash.h</file>\r
+      <file>$PROJ_DIR$\Full\Obj\ParTest.pbi</file>\r
+      <file>$PROJ_DIR$\..\..\Source\include\mpu_wrappers.h</file>\r
+      <file>$PROJ_DIR$\..\..\Source\include\semphr.h</file>\r
+      <file>$PROJ_DIR$\Full\Obj\PollQ.pbi</file>\r
+      <file>$PROJ_DIR$\..\..\Source\portable\IAR\ARM_CM3\port.c</file>\r
+      <file>$PROJ_DIR$\..\..\Source\include\queue.h</file>\r
+      <file>$PROJ_DIR$\..\..\Source\tasks.c</file>\r
+      <file>$PROJ_DIR$\..\Common\Minimal\recmutex.c</file>\r
+      <file>$PROJ_DIR$\Fujitu_source\system_mb9af31x.c</file>\r
+      <file>$PROJ_DIR$\Full\Obj\system_mb9af31x.o</file>\r
+      <file>$PROJ_DIR$\..\..\Source\portable\MemMang\heap_2.c</file>\r
+      <file>$PROJ_DIR$\..\Common\include\dynamic.h</file>\r
+      <file>$PROJ_DIR$\..\Common\include\comtest.h</file>\r
+      <file>$PROJ_DIR$\..\..\Source\portable\IAR\ARM_CM3\portasm.s</file>\r
+      <file>$TOOLKIT_DIR$\inc\c\DLib_Defaults.h</file>\r
+      <file>$PROJ_DIR$\Full\Obj\system_mb9af31x.pbi</file>\r
+      <file>$PROJ_DIR$\Full\Obj\TimerDemo.o</file>\r
+      <file>$TOOLKIT_DIR$\inc\c\xencoding_limits.h</file>\r
+      <file>$TOOLKIT_DIR$\inc\c\ycheck.h</file>\r
+      <file>$PROJ_DIR$\Full\Obj\flash.o</file>\r
+      <file>$PROJ_DIR$\..\Common\include\partest.h</file>\r
+      <file>$PROJ_DIR$\Full\Obj\BlockQ.o</file>\r
+      <file>$PROJ_DIR$\Full\Obj\dynamic.o</file>\r
+      <file>$PROJ_DIR$\Full\Obj\death.pbi</file>\r
+      <file>$PROJ_DIR$\..\Common\include\BlockQ.h</file>\r
+      <file>$PROJ_DIR$\Full\Obj\dynamic.pbi</file>\r
+      <file>$PROJ_DIR$\Full\Obj\serial.pbi</file>\r
+      <file>$PROJ_DIR$\Full\Obj\startup_mb9af31x.o</file>\r
+      <file>$TOOLKIT_DIR$\inc\c\stddef.h</file>\r
+      <file>$PROJ_DIR$\Fujitu_source\core_cm3.c</file>\r
+      <file>$PROJ_DIR$\..\..\Source\include\portable.h</file>\r
+      <file>$PROJ_DIR$\Full\Obj\QPeek.o</file>\r
+      <file>$PROJ_DIR$\Full\Obj\comtest.o</file>\r
+      <file>$PROJ_DIR$\Full\Obj\queue.o</file>\r
+      <file>$PROJ_DIR$\..\Common\include\blocktim.h</file>\r
+      <file>$PROJ_DIR$\Full\Obj\BlockQ.pbi</file>\r
+      <file>$PROJ_DIR$\..\..\Source\queue.c</file>\r
+      <file>$PROJ_DIR$\Full\Obj\main-full.pbi</file>\r
+      <file>$PROJ_DIR$\Full\Obj\QPeek.pbi</file>\r
+      <file>$PROJ_DIR$\Full\Obj\death.o</file>\r
+      <file>$PROJ_DIR$\main_blinky.c</file>\r
+      <file>$PROJ_DIR$\Full\Obj\timers.o</file>\r
+      <file>$PROJ_DIR$\..\Common\Minimal\BlockQ.c</file>\r
+      <file>$TOOLKIT_DIR$\inc\c\stdlib.h</file>\r
+      <file>$PROJ_DIR$\..\Common\include\countsem.h</file>\r
+      <file>$PROJ_DIR$\..\Common\Minimal\flash.c</file>\r
+      <file>$PROJ_DIR$\Full\Obj\blocktim.pbi</file>\r
+      <file>$PROJ_DIR$\..\..\Source\include\projdefs.h</file>\r
+      <file>$PROJ_DIR$\Full\Obj\RTOSDemo_IAR.pbd</file>\r
+      <file>$TOOLKIT_DIR$\inc\c\DLib_Threads.h</file>\r
+      <file>$PROJ_DIR$\..\Common\Minimal\TimerDemo.c</file>\r
+      <file>$PROJ_DIR$\Full\Obj\core_cm3.o</file>\r
+      <file>$PROJ_DIR$\Full\Obj\PollQ.o</file>\r
+      <file>$PROJ_DIR$\Full\Obj\tasks.pbi</file>\r
+      <file>$PROJ_DIR$\..\Common\Minimal\QPeek.c</file>\r
+      <file>$PROJ_DIR$\Full\Obj\GenQTest.o</file>\r
+      <file>$PROJ_DIR$\..\Common\Minimal\comtest.c</file>\r
+      <file>$PROJ_DIR$\Full\Obj\queue.pbi</file>\r
+      <file>$PROJ_DIR$\Full\Obj\ParTest.o</file>\r
+      <file>$TOOLKIT_DIR$\inc\c\stdint.h</file>\r
+      <file>$PROJ_DIR$\Full\Obj\timers.pbi</file>\r
+      <file>$PROJ_DIR$\..\Common\Minimal\blocktim.c</file>\r
+      <file>$PROJ_DIR$\Full\Obj\blocktim.o</file>\r
+      <file>$PROJ_DIR$\Full\Obj\flash.pbi</file>\r
+      <file>$PROJ_DIR$\Full\Obj\main-full.o</file>\r
+      <file>$PROJ_DIR$\Full\Obj\port.o</file>\r
+      <file>$PROJ_DIR$\Full\Obj\list.pbi</file>\r
+      <file>$PROJ_DIR$\Full\Obj\heap_2.pbi</file>\r
+      <file>$PROJ_DIR$\..\Common\Minimal\countsem.c</file>\r
+      <file>$PROJ_DIR$\..\Common\Minimal\dynamic.c</file>\r
+      <file>$PROJ_DIR$\..\Common\include\serial.h</file>\r
+      <file>$PROJ_DIR$\Full\Obj\serial.o</file>\r
+      <file>$PROJ_DIR$\Fujitu_source\startup_iar\startup_mb9af31x.s</file>\r
+      <file>$PROJ_DIR$\Full\Obj\heap_2.o</file>\r
+      <file>$TOOLKIT_DIR$\inc\c\yvals.h</file>\r
+      <file>$PROJ_DIR$\Full\Obj\core_cm3.pbi</file>\r
+      <file>$PROJ_DIR$\Full\Obj\comtest.pbi</file>\r
+      <file>$PROJ_DIR$\serial.c</file>\r
+      <file>$PROJ_DIR$\..\Common\include\GenQTest.h</file>\r
+      <file>$PROJ_DIR$\main-full.c</file>\r
+      <file>$PROJ_DIR$\..\Common\Minimal\PollQ.c</file>\r
+      <file>$PROJ_DIR$\Full\Obj\GenQTest.pbi</file>\r
+      <file>$PROJ_DIR$\Full\Obj\port.pbi</file>\r
+      <file>$PROJ_DIR$\Full\Obj\semtest.o</file>\r
+      <file>$PROJ_DIR$\..\Common\Minimal\semtest.c</file>\r
+      <file>$PROJ_DIR$\..\..\Source\include\task.h</file>\r
+      <file>$PROJ_DIR$\Full\Obj\recmutex.pbi</file>\r
+      <file>$PROJ_DIR$\Full\Obj\tasks.o</file>\r
+      <file>$PROJ_DIR$\Full\Obj\semtest.pbi</file>\r
+      <file>$PROJ_DIR$\Full\Obj\list.o</file>\r
+      <file>$PROJ_DIR$\..\..\Source\include\list.h</file>\r
+      <file>$PROJ_DIR$\Full\Obj\countsem.pbi</file>\r
+      <file>$PROJ_DIR$\Full\Obj\recmutex.o</file>\r
+      <file>$PROJ_DIR$\Full\Obj\portasm.o</file>\r
+      <file>$PROJ_DIR$\ParTest.c</file>\r
+      <file>$PROJ_DIR$\Full\Obj\TimerDemo.pbi</file>\r
+      <file>$PROJ_DIR$\Full\Exe\RTOSDemo_IAR.out</file>\r
+      <file>$PROJ_DIR$\..\..\Source\list.c</file>\r
+      <file>$TOOLKIT_DIR$\inc\c\DLib_Product.h</file>\r
+      <file>$PROJ_DIR$\..\..\Source\timers.c</file>\r
+      <file>$PROJ_DIR$\..\Common\include\PollQ.h</file>\r
+      <file>$PROJ_DIR$\..\Common\Minimal\death.c</file>\r
+      <file>$PROJ_DIR$\..\Common\Minimal\GenQTest.c</file>\r
+      <file>$PROJ_DIR$\..\..\Source\include\FreeRTOS.h</file>\r
+      <file>$PROJ_DIR$\..\..\Source\portable\IAR\ARM_CM3\portmacro.h</file>\r
+    </outputs>\r
+    <file>\r
+      <name>$PROJ_DIR$\..\..\Source\portable\IAR\ARM_CM3\port.c</name>\r
+      <outputs>\r
+        <tool>\r
+          <name>ICCARM</name>\r
+          <file> 70</file>\r
+        </tool>\r
+        <tool>\r
+          <name>BICOMP</name>\r
+          <file> 87</file>\r
+        </tool>\r
+      </outputs>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\..\..\Source\tasks.c</name>\r
+      <outputs>\r
+        <tool>\r
+          <name>ICCARM</name>\r
+          <file> 92</file>\r
+        </tool>\r
+        <tool>\r
+          <name>BICOMP</name>\r
+          <file> 58</file>\r
+        </tool>\r
+      </outputs>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\..\Common\Minimal\recmutex.c</name>\r
+      <outputs>\r
+        <tool>\r
+          <name>ICCARM</name>\r
+          <file> 97</file>\r
+        </tool>\r
+        <tool>\r
+          <name>BICOMP</name>\r
+          <file> 91</file>\r
+        </tool>\r
+      </outputs>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\Fujitu_source\system_mb9af31x.c</name>\r
+      <outputs>\r
+        <tool>\r
+          <name>ICCARM</name>\r
+          <file> 14</file>\r
+        </tool>\r
+        <tool>\r
+          <name>BICOMP</name>\r
+          <file> 20</file>\r
+        </tool>\r
+      </outputs>\r
+    </file>\r
+    <file>\r
+      <name>[ROOT_NODE]</name>\r
+      <outputs>\r
+        <tool>\r
+          <name>ILINK</name>\r
+          <file> 101</file>\r
+        </tool>\r
+      </outputs>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\..\..\Source\portable\MemMang\heap_2.c</name>\r
+      <outputs>\r
+        <tool>\r
+          <name>ICCARM</name>\r
+          <file> 78</file>\r
+        </tool>\r
+        <tool>\r
+          <name>BICOMP</name>\r
+          <file> 72</file>\r
+        </tool>\r
+      </outputs>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\..\..\Source\portable\IAR\ARM_CM3\portasm.s</name>\r
+      <outputs>\r
+        <tool>\r
+          <name>AARM</name>\r
+          <file> 98</file>\r
+        </tool>\r
+      </outputs>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\Fujitu_source\core_cm3.c</name>\r
+      <outputs>\r
+        <tool>\r
+          <name>ICCARM</name>\r
+          <file> 56</file>\r
+        </tool>\r
+        <tool>\r
+          <name>BICOMP</name>\r
+          <file> 80</file>\r
+        </tool>\r
+      </outputs>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\..\..\Source\queue.c</name>\r
+      <outputs>\r
+        <tool>\r
+          <name>ICCARM</name>\r
+          <file> 38</file>\r
+        </tool>\r
+        <tool>\r
+          <name>BICOMP</name>\r
+          <file> 62</file>\r
+        </tool>\r
+      </outputs>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\..\Common\Minimal\BlockQ.c</name>\r
+      <outputs>\r
+        <tool>\r
+          <name>ICCARM</name>\r
+          <file> 26</file>\r
+        </tool>\r
+        <tool>\r
+          <name>BICOMP</name>\r
+          <file> 40</file>\r
+        </tool>\r
+      </outputs>\r
+      <inputs>\r
+        <tool>\r
+          <name>BICOMP</name>\r
+          <file> 48 23 79 19 103 22 54 0 108 33 52 1 64 35 109 6 90 95 10 29</file>\r
+        </tool>\r
+      </inputs>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\..\Common\Minimal\flash.c</name>\r
+      <outputs>\r
+        <tool>\r
+          <name>ICCARM</name>\r
+          <file> 24</file>\r
+        </tool>\r
+        <tool>\r
+          <name>BICOMP</name>\r
+          <file> 68</file>\r
+        </tool>\r
+      </outputs>\r
+      <inputs>\r
+        <tool>\r
+          <name>BICOMP</name>\r
+          <file> 48 23 79 19 103 22 54 0 108 33 52 1 64 35 109 6 90 95 25 4</file>\r
+        </tool>\r
+      </inputs>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\..\Common\Minimal\TimerDemo.c</name>\r
+      <outputs>\r
+        <tool>\r
+          <name>ICCARM</name>\r
+          <file> 21</file>\r
+        </tool>\r
+        <tool>\r
+          <name>BICOMP</name>\r
+          <file> 100</file>\r
+        </tool>\r
+      </outputs>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\..\Common\Minimal\QPeek.c</name>\r
+      <outputs>\r
+        <tool>\r
+          <name>ICCARM</name>\r
+          <file> 36</file>\r
+        </tool>\r
+        <tool>\r
+          <name>BICOMP</name>\r
+          <file> 43</file>\r
+        </tool>\r
+      </outputs>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\..\Common\Minimal\comtest.c</name>\r
+      <outputs>\r
+        <tool>\r
+          <name>ICCARM</name>\r
+          <file> 37</file>\r
+        </tool>\r
+        <tool>\r
+          <name>BICOMP</name>\r
+          <file> 81</file>\r
+        </tool>\r
+      </outputs>\r
+      <inputs>\r
+        <tool>\r
+          <name>BICOMP</name>\r
+          <file> 48 23 79 19 103 22 54 0 108 33 52 1 64 35 109 6 90 95 75 17 25</file>\r
+        </tool>\r
+      </inputs>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\..\Common\Minimal\blocktim.c</name>\r
+      <outputs>\r
+        <tool>\r
+          <name>ICCARM</name>\r
+          <file> 67</file>\r
+        </tool>\r
+        <tool>\r
+          <name>BICOMP</name>\r
+          <file> 51</file>\r
+        </tool>\r
+      </outputs>\r
+      <inputs>\r
+        <tool>\r
+          <name>BICOMP</name>\r
+          <file> 108 33 23 79 19 103 22 54 0 52 1 64 35 109 6 90 95 10 39</file>\r
+        </tool>\r
+      </inputs>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\..\Common\Minimal\countsem.c</name>\r
+      <outputs>\r
+        <tool>\r
+          <name>ICCARM</name>\r
+          <file> 2</file>\r
+        </tool>\r
+        <tool>\r
+          <name>BICOMP</name>\r
+          <file> 96</file>\r
+        </tool>\r
+      </outputs>\r
+      <inputs>\r
+        <tool>\r
+          <name>BICOMP</name>\r
+          <file> 108 33 23 79 19 103 22 54 0 52 1 64 35 109 6 90 95 7 10 49</file>\r
+        </tool>\r
+      </inputs>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\..\Common\Minimal\dynamic.c</name>\r
+      <outputs>\r
+        <tool>\r
+          <name>ICCARM</name>\r
+          <file> 27</file>\r
+        </tool>\r
+        <tool>\r
+          <name>BICOMP</name>\r
+          <file> 30</file>\r
+        </tool>\r
+      </outputs>\r
+      <inputs>\r
+        <tool>\r
+          <name>BICOMP</name>\r
+          <file> 48 23 79 19 103 22 54 0 108 33 52 1 64 35 109 6 90 95 7 10 16</file>\r
+        </tool>\r
+      </inputs>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\Fujitu_source\startup_iar\startup_mb9af31x.s</name>\r
+      <outputs>\r
+        <tool>\r
+          <name>AARM</name>\r
+          <file> 32</file>\r
+        </tool>\r
+      </outputs>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\serial.c</name>\r
+      <outputs>\r
+        <tool>\r
+          <name>ICCARM</name>\r
+          <file> 76</file>\r
+        </tool>\r
+        <tool>\r
+          <name>BICOMP</name>\r
+          <file> 31</file>\r
+        </tool>\r
+      </outputs>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\main-full.c</name>\r
+      <outputs>\r
+        <tool>\r
+          <name>ICCARM</name>\r
+          <file> 69</file>\r
+        </tool>\r
+        <tool>\r
+          <name>BICOMP</name>\r
+          <file> 42</file>\r
+        </tool>\r
+      </outputs>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\..\Common\Minimal\PollQ.c</name>\r
+      <outputs>\r
+        <tool>\r
+          <name>ICCARM</name>\r
+          <file> 57</file>\r
+        </tool>\r
+        <tool>\r
+          <name>BICOMP</name>\r
+          <file> 8</file>\r
+        </tool>\r
+      </outputs>\r
+      <inputs>\r
+        <tool>\r
+          <name>BICOMP</name>\r
+          <file> 48 23 79 19 103 22 54 0 108 33 52 1 64 35 109 6 90 95 10 105</file>\r
+        </tool>\r
+      </inputs>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\..\Common\Minimal\semtest.c</name>\r
+      <outputs>\r
+        <tool>\r
+          <name>ICCARM</name>\r
+          <file> 88</file>\r
+        </tool>\r
+        <tool>\r
+          <name>BICOMP</name>\r
+          <file> 93</file>\r
+        </tool>\r
+      </outputs>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\ParTest.c</name>\r
+      <outputs>\r
+        <tool>\r
+          <name>ICCARM</name>\r
+          <file> 63</file>\r
+        </tool>\r
+        <tool>\r
+          <name>BICOMP</name>\r
+          <file> 5</file>\r
+        </tool>\r
+      </outputs>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\..\..\Source\list.c</name>\r
+      <outputs>\r
+        <tool>\r
+          <name>ICCARM</name>\r
+          <file> 94</file>\r
+        </tool>\r
+        <tool>\r
+          <name>BICOMP</name>\r
+          <file> 71</file>\r
+        </tool>\r
+      </outputs>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\..\..\Source\timers.c</name>\r
+      <outputs>\r
+        <tool>\r
+          <name>ICCARM</name>\r
+          <file> 46</file>\r
+        </tool>\r
+        <tool>\r
+          <name>BICOMP</name>\r
+          <file> 65</file>\r
+        </tool>\r
+      </outputs>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\..\Common\Minimal\death.c</name>\r
+      <outputs>\r
+        <tool>\r
+          <name>ICCARM</name>\r
+          <file> 44</file>\r
+        </tool>\r
+        <tool>\r
+          <name>BICOMP</name>\r
+          <file> 28</file>\r
+        </tool>\r
+      </outputs>\r
+      <inputs>\r
+        <tool>\r
+          <name>BICOMP</name>\r
+          <file> 48 23 79 19 103 22 54 0 108 33 52 1 64 35 109 6 90 95 3</file>\r
+        </tool>\r
+      </inputs>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\..\Common\Minimal\GenQTest.c</name>\r
+      <outputs>\r
+        <tool>\r
+          <name>ICCARM</name>\r
+          <file> 60</file>\r
+        </tool>\r
+        <tool>\r
+          <name>BICOMP</name>\r
+          <file> 86</file>\r
+        </tool>\r
+      </outputs>\r
+      <inputs>\r
+        <tool>\r
+          <name>BICOMP</name>\r
+          <file> 48 23 79 19 103 22 54 0 108 33 52 1 64 35 109 6 90 95 10 7 83</file>\r
+        </tool>\r
+      </inputs>\r
+    </file>\r
+  </configuration>\r
+  <configuration>\r
+    <name>Full_with_optimisation</name>\r
+    <outputs>\r
+      <file>$TOOLKIT_DIR$\inc\c\ysizet.h</file>\r
+      <file>$PROJ_DIR$\Full_with_optimisation\Obj\dynamic.pbi</file>\r
+      <file>$PROJ_DIR$\FreeRTOSConfig.h</file>\r
+      <file>$PROJ_DIR$\..\..\Source\include\mpu_wrappers.h</file>\r
+      <file>$PROJ_DIR$\Full_with_optimisation\Obj\dynamic.o</file>\r
+      <file>$PROJ_DIR$\Full_with_optimisation\Obj\comtest.o</file>\r
+      <file>$PROJ_DIR$\..\..\Source\portable\IAR\ARM_CM3\port.c</file>\r
+      <file>$PROJ_DIR$\..\..\Source\include\queue.h</file>\r
+      <file>$PROJ_DIR$\..\..\Source\tasks.c</file>\r
+      <file>$PROJ_DIR$\Full_with_optimisation\Obj\blocktim.o</file>\r
+      <file>$PROJ_DIR$\Full_with_optimisation\Obj\ParTest.o</file>\r
+      <file>$PROJ_DIR$\..\Common\Minimal\recmutex.c</file>\r
+      <file>$PROJ_DIR$\Fujitu_source\system_mb9af31x.c</file>\r
+      <file>$PROJ_DIR$\Full_with_optimisation\Obj\flash.o</file>\r
+      <file>$PROJ_DIR$\..\..\Source\portable\MemMang\heap_2.c</file>\r
+      <file>$PROJ_DIR$\Full_with_optimisation\Obj\TimerDemo.pbi</file>\r
+      <file>$PROJ_DIR$\Full_with_optimisation\Obj\port.pbi</file>\r
+      <file>$PROJ_DIR$\..\..\Source\portable\IAR\ARM_CM3\portasm.s</file>\r
+      <file>$TOOLKIT_DIR$\inc\c\DLib_Defaults.h</file>\r
+      <file>$PROJ_DIR$\Full_with_optimisation\Obj\semtest.pbi</file>\r
+      <file>$PROJ_DIR$\Full_with_optimisation\Obj\recmutex.o</file>\r
+      <file>$TOOLKIT_DIR$\inc\c\xencoding_limits.h</file>\r
+      <file>$TOOLKIT_DIR$\inc\c\ycheck.h</file>\r
+      <file>$PROJ_DIR$\Full_with_optimisation\Obj\death.pbi</file>\r
+      <file>$PROJ_DIR$\Full_with_optimisation\Obj\ParTest.pbi</file>\r
+      <file>$PROJ_DIR$\Full_with_optimisation\Obj\PollQ.pbi</file>\r
+      <file>$PROJ_DIR$\Full_with_optimisation\Obj\serial.pbi</file>\r
+      <file>$PROJ_DIR$\..\Common\include\BlockQ.h</file>\r
+      <file>$TOOLKIT_DIR$\inc\c\stddef.h</file>\r
+      <file>$PROJ_DIR$\Fujitu_source\core_cm3.c</file>\r
+      <file>$PROJ_DIR$\..\..\Source\include\portable.h</file>\r
+      <file>$PROJ_DIR$\Full_with_optimisation\Obj\death.o</file>\r
+      <file>$PROJ_DIR$\Full_with_optimisation\Obj\semtest.o</file>\r
+      <file>$PROJ_DIR$\..\..\Source\queue.c</file>\r
+      <file>$PROJ_DIR$\Full_with_optimisation\Obj\PollQ.o</file>\r
+      <file>$PROJ_DIR$\Full_with_optimisation\Obj\main-full.o</file>\r
+      <file>$PROJ_DIR$\Full_with_optimisation\Obj\main-full.pbi</file>\r
+      <file>$PROJ_DIR$\main_blinky.c</file>\r
+      <file>$PROJ_DIR$\..\Common\Minimal\BlockQ.c</file>\r
+      <file>$PROJ_DIR$\Full_with_optimisation\Obj\portasm.o</file>\r
+      <file>$TOOLKIT_DIR$\inc\c\stdlib.h</file>\r
+      <file>$PROJ_DIR$\..\Common\Minimal\flash.c</file>\r
+      <file>$PROJ_DIR$\Full_with_optimisation\Exe\RTOSDemo_IAR.out</file>\r
+      <file>$PROJ_DIR$\Full_with_optimisation\Obj\blocktim.pbi</file>\r
+      <file>$PROJ_DIR$\Full_with_optimisation\Obj\startup_mb9af31x.o</file>\r
+      <file>$PROJ_DIR$\Full_with_optimisation\Obj\TimerDemo.o</file>\r
+      <file>$PROJ_DIR$\..\..\Source\include\projdefs.h</file>\r
+      <file>$PROJ_DIR$\Full_with_optimisation\Obj\core_cm3.o</file>\r
+      <file>$PROJ_DIR$\Full_with_optimisation\Obj\tasks.o</file>\r
+      <file>$TOOLKIT_DIR$\inc\c\DLib_Threads.h</file>\r
+      <file>$PROJ_DIR$\Full_with_optimisation\Obj\recmutex.pbi</file>\r
+      <file>$PROJ_DIR$\Full_with_optimisation\Obj\tasks.pbi</file>\r
+      <file>$PROJ_DIR$\Full_with_optimisation\Obj\port.o</file>\r
+      <file>$PROJ_DIR$\..\Common\Minimal\TimerDemo.c</file>\r
+      <file>$PROJ_DIR$\Full_with_optimisation\Obj\countsem.o</file>\r
+      <file>$PROJ_DIR$\..\Common\Minimal\QPeek.c</file>\r
+      <file>$PROJ_DIR$\..\Common\Minimal\comtest.c</file>\r
+      <file>$TOOLKIT_DIR$\inc\c\stdint.h</file>\r
+      <file>$PROJ_DIR$\Full_with_optimisation\Obj\list.pbi</file>\r
+      <file>$PROJ_DIR$\Full_with_optimisation\Obj\BlockQ.o</file>\r
+      <file>$PROJ_DIR$\Full_with_optimisation\Obj\QPeek.pbi</file>\r
+      <file>$PROJ_DIR$\..\Common\Minimal\blocktim.c</file>\r
+      <file>$PROJ_DIR$\Full_with_optimisation\Obj\timers.o</file>\r
+      <file>$PROJ_DIR$\..\Common\Minimal\countsem.c</file>\r
+      <file>$PROJ_DIR$\Full_with_optimisation\Obj\countsem.pbi</file>\r
+      <file>$PROJ_DIR$\..\Common\Minimal\dynamic.c</file>\r
+      <file>$PROJ_DIR$\Fujitu_source\startup_iar\startup_mb9af31x.s</file>\r
+      <file>$TOOLKIT_DIR$\inc\c\yvals.h</file>\r
+      <file>$PROJ_DIR$\Full_with_optimisation\Obj\flash.pbi</file>\r
+      <file>$PROJ_DIR$\serial.c</file>\r
+      <file>$PROJ_DIR$\main-full.c</file>\r
+      <file>$PROJ_DIR$\..\Common\Minimal\PollQ.c</file>\r
+      <file>$PROJ_DIR$\Full_with_optimisation\Obj\BlockQ.pbi</file>\r
+      <file>$PROJ_DIR$\..\Common\Minimal\semtest.c</file>\r
+      <file>$PROJ_DIR$\..\..\Source\include\task.h</file>\r
+      <file>$PROJ_DIR$\Full_with_optimisation\Obj\comtest.pbi</file>\r
+      <file>$PROJ_DIR$\Full_with_optimisation\Obj\heap_2.pbi</file>\r
+      <file>$PROJ_DIR$\..\..\Source\include\list.h</file>\r
+      <file>$PROJ_DIR$\Full_with_optimisation\Obj\timers.pbi</file>\r
+      <file>$PROJ_DIR$\Full_with_optimisation\Obj\list.o</file>\r
+      <file>$PROJ_DIR$\Full_with_optimisation\Obj\serial.o</file>\r
+      <file>$PROJ_DIR$\Full_with_optimisation\Obj\core_cm3.pbi</file>\r
+      <file>$PROJ_DIR$\ParTest.c</file>\r
+      <file>$PROJ_DIR$\Full_with_optimisation\Obj\heap_2.o</file>\r
+      <file>$PROJ_DIR$\..\..\Source\list.c</file>\r
+      <file>$PROJ_DIR$\Full_with_optimisation\Obj\queue.o</file>\r
+      <file>$TOOLKIT_DIR$\inc\c\DLib_Product.h</file>\r
+      <file>$PROJ_DIR$\..\..\Source\timers.c</file>\r
+      <file>$PROJ_DIR$\Full_with_optimisation\Obj\GenQTest.o</file>\r
+      <file>$PROJ_DIR$\Full_with_optimisation\Obj\QPeek.o</file>\r
+      <file>$PROJ_DIR$\Full_with_optimisation\Obj\GenQTest.pbi</file>\r
+      <file>$PROJ_DIR$\..\Common\Minimal\death.c</file>\r
+      <file>$PROJ_DIR$\..\Common\Minimal\GenQTest.c</file>\r
+      <file>$PROJ_DIR$\Full_with_optimisation\Obj\queue.pbi</file>\r
+      <file>$PROJ_DIR$\..\..\Source\include\FreeRTOS.h</file>\r
+      <file>$PROJ_DIR$\..\..\Source\portable\IAR\ARM_CM3\portmacro.h</file>\r
+      <file>$PROJ_DIR$\Full_with_optimisation\Obj\RTOSDemo_IAR.pbd</file>\r
+      <file>$PROJ_DIR$\Full_with_optimisation\Obj\system_mb9af31x.pbi</file>\r
+      <file>$PROJ_DIR$\Full_with_optimisation\Obj\system_mb9af31x.o</file>\r
+    </outputs>\r
+    <file>\r
+      <name>$PROJ_DIR$\..\..\Source\portable\IAR\ARM_CM3\port.c</name>\r
+      <outputs>\r
+        <tool>\r
+          <name>ICCARM</name>\r
+          <file> 52</file>\r
+        </tool>\r
+        <tool>\r
+          <name>BICOMP</name>\r
+          <file> 16</file>\r
+        </tool>\r
+      </outputs>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\..\..\Source\tasks.c</name>\r
+      <outputs>\r
+        <tool>\r
+          <name>ICCARM</name>\r
+          <file> 48</file>\r
+        </tool>\r
+        <tool>\r
+          <name>BICOMP</name>\r
+          <file> 51</file>\r
+        </tool>\r
+      </outputs>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\..\Common\Minimal\recmutex.c</name>\r
+      <outputs>\r
+        <tool>\r
+          <name>ICCARM</name>\r
+          <file> 20</file>\r
+        </tool>\r
+        <tool>\r
+          <name>BICOMP</name>\r
+          <file> 50</file>\r
+        </tool>\r
+      </outputs>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\Fujitu_source\system_mb9af31x.c</name>\r
+      <outputs>\r
+        <tool>\r
+          <name>ICCARM</name>\r
+          <file> 98</file>\r
+        </tool>\r
+        <tool>\r
+          <name>BICOMP</name>\r
+          <file> 97</file>\r
+        </tool>\r
+      </outputs>\r
+    </file>\r
+    <file>\r
+      <name>[ROOT_NODE]</name>\r
+      <outputs>\r
+        <tool>\r
+          <name>ILINK</name>\r
+          <file> 42</file>\r
+        </tool>\r
+      </outputs>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\..\..\Source\portable\MemMang\heap_2.c</name>\r
+      <outputs>\r
+        <tool>\r
+          <name>ICCARM</name>\r
+          <file> 83</file>\r
+        </tool>\r
+        <tool>\r
+          <name>BICOMP</name>\r
+          <file> 76</file>\r
+        </tool>\r
+      </outputs>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\..\..\Source\portable\IAR\ARM_CM3\portasm.s</name>\r
+      <outputs>\r
+        <tool>\r
+          <name>AARM</name>\r
+          <file> 39</file>\r
+        </tool>\r
+      </outputs>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\Fujitu_source\core_cm3.c</name>\r
+      <outputs>\r
+        <tool>\r
+          <name>ICCARM</name>\r
+          <file> 47</file>\r
+        </tool>\r
+        <tool>\r
+          <name>BICOMP</name>\r
+          <file> 81</file>\r
+        </tool>\r
+      </outputs>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\..\..\Source\queue.c</name>\r
+      <outputs>\r
+        <tool>\r
+          <name>ICCARM</name>\r
+          <file> 85</file>\r
+        </tool>\r
+        <tool>\r
+          <name>BICOMP</name>\r
+          <file> 93</file>\r
+        </tool>\r
+      </outputs>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\..\Common\Minimal\BlockQ.c</name>\r
+      <outputs>\r
+        <tool>\r
+          <name>ICCARM</name>\r
+          <file> 59</file>\r
+        </tool>\r
+        <tool>\r
+          <name>BICOMP</name>\r
+          <file> 72</file>\r
+        </tool>\r
+      </outputs>\r
+      <inputs>\r
+        <tool>\r
+          <name>BICOMP</name>\r
+          <file> 40 22 67 18 86 21 49 0 94 28 46 2 57 30 95 3 74 77 7 27</file>\r
+        </tool>\r
+      </inputs>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\..\Common\Minimal\flash.c</name>\r
+      <outputs>\r
+        <tool>\r
+          <name>ICCARM</name>\r
+          <file> 13</file>\r
+        </tool>\r
+        <tool>\r
+          <name>BICOMP</name>\r
+          <file> 68</file>\r
+        </tool>\r
+      </outputs>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\..\Common\Minimal\TimerDemo.c</name>\r
+      <outputs>\r
+        <tool>\r
+          <name>ICCARM</name>\r
+          <file> 45</file>\r
+        </tool>\r
+        <tool>\r
+          <name>BICOMP</name>\r
+          <file> 15</file>\r
+        </tool>\r
+      </outputs>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\..\Common\Minimal\QPeek.c</name>\r
+      <outputs>\r
+        <tool>\r
+          <name>ICCARM</name>\r
+          <file> 89</file>\r
+        </tool>\r
+        <tool>\r
+          <name>BICOMP</name>\r
+          <file> 60</file>\r
+        </tool>\r
+      </outputs>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\..\Common\Minimal\comtest.c</name>\r
+      <outputs>\r
+        <tool>\r
+          <name>ICCARM</name>\r
+          <file> 5</file>\r
+        </tool>\r
+        <tool>\r
+          <name>BICOMP</name>\r
+          <file> 75</file>\r
+        </tool>\r
+      </outputs>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\..\Common\Minimal\blocktim.c</name>\r
+      <outputs>\r
+        <tool>\r
+          <name>ICCARM</name>\r
+          <file> 9</file>\r
+        </tool>\r
+        <tool>\r
+          <name>BICOMP</name>\r
+          <file> 43</file>\r
+        </tool>\r
+      </outputs>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\..\Common\Minimal\countsem.c</name>\r
+      <outputs>\r
+        <tool>\r
+          <name>ICCARM</name>\r
+          <file> 54</file>\r
+        </tool>\r
+        <tool>\r
+          <name>BICOMP</name>\r
+          <file> 64</file>\r
+        </tool>\r
+      </outputs>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\..\Common\Minimal\dynamic.c</name>\r
+      <outputs>\r
+        <tool>\r
+          <name>ICCARM</name>\r
+          <file> 4</file>\r
+        </tool>\r
+        <tool>\r
+          <name>BICOMP</name>\r
+          <file> 1</file>\r
+        </tool>\r
+      </outputs>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\Fujitu_source\startup_iar\startup_mb9af31x.s</name>\r
+      <outputs>\r
+        <tool>\r
+          <name>AARM</name>\r
+          <file> 44</file>\r
+        </tool>\r
+      </outputs>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\serial.c</name>\r
+      <outputs>\r
+        <tool>\r
+          <name>ICCARM</name>\r
+          <file> 80</file>\r
+        </tool>\r
+        <tool>\r
+          <name>BICOMP</name>\r
+          <file> 26</file>\r
+        </tool>\r
+      </outputs>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\main-full.c</name>\r
+      <outputs>\r
+        <tool>\r
+          <name>ICCARM</name>\r
+          <file> 35</file>\r
+        </tool>\r
+        <tool>\r
+          <name>BICOMP</name>\r
+          <file> 36</file>\r
+        </tool>\r
+      </outputs>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\..\Common\Minimal\PollQ.c</name>\r
+      <outputs>\r
+        <tool>\r
+          <name>ICCARM</name>\r
+          <file> 34</file>\r
+        </tool>\r
+        <tool>\r
+          <name>BICOMP</name>\r
+          <file> 25</file>\r
+        </tool>\r
+      </outputs>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\..\Common\Minimal\semtest.c</name>\r
+      <outputs>\r
+        <tool>\r
+          <name>ICCARM</name>\r
+          <file> 32</file>\r
+        </tool>\r
+        <tool>\r
+          <name>BICOMP</name>\r
+          <file> 19</file>\r
+        </tool>\r
+      </outputs>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\ParTest.c</name>\r
+      <outputs>\r
+        <tool>\r
+          <name>ICCARM</name>\r
+          <file> 10</file>\r
+        </tool>\r
+        <tool>\r
+          <name>BICOMP</name>\r
+          <file> 24</file>\r
+        </tool>\r
+      </outputs>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\..\..\Source\list.c</name>\r
+      <outputs>\r
+        <tool>\r
+          <name>ICCARM</name>\r
+          <file> 79</file>\r
+        </tool>\r
+        <tool>\r
+          <name>BICOMP</name>\r
+          <file> 58</file>\r
+        </tool>\r
+      </outputs>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\..\..\Source\timers.c</name>\r
+      <outputs>\r
+        <tool>\r
+          <name>ICCARM</name>\r
+          <file> 62</file>\r
+        </tool>\r
+        <tool>\r
+          <name>BICOMP</name>\r
+          <file> 78</file>\r
+        </tool>\r
+      </outputs>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\..\Common\Minimal\death.c</name>\r
+      <outputs>\r
+        <tool>\r
+          <name>ICCARM</name>\r
+          <file> 31</file>\r
+        </tool>\r
+        <tool>\r
+          <name>BICOMP</name>\r
+          <file> 23</file>\r
+        </tool>\r
+      </outputs>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\..\Common\Minimal\GenQTest.c</name>\r
+      <outputs>\r
+        <tool>\r
+          <name>ICCARM</name>\r
+          <file> 88</file>\r
+        </tool>\r
+        <tool>\r
+          <name>BICOMP</name>\r
+          <file> 90</file>\r
+        </tool>\r
+      </outputs>\r
+    </file>\r
+  </configuration>\r
+</project>\r
+\r
+\r

diff --git a/Demo/CORTEX_MB9A310_IAR_Keil/RTOSDemo_IAR.ewd b/Demo/CORTEX_MB9A310_IAR_Keil/RTOSDemo_IAR.ewd
new file mode 100644 (file)
index 0000000..2972feb
--- /dev/null
+++ b/Demo/CORTEX_MB9A310_IAR_Keil/RTOSDemo_IAR.ewd
@@ -0,0 +1,2623 @@
+<?xml version="1.0" encoding="iso-8859-1"?>\r
+\r
+<project>\r
+  <fileVersion>2</fileVersion>\r
+  <configuration>\r
+    <name>Blinky</name>\r
+    <toolchain>\r
+      <name>ARM</name>\r
+    </toolchain>\r
+    <debug>1</debug>\r
+    <settings>\r
+      <name>C-SPY</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>22</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>CInput</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CEndian</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CProcessor</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>OCVariant</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>MacOverride</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>MacFile</name>\r
+          <state>$PROJ_DIR$\config\Ram_VTOR.mac</state>\r
+        </option>\r
+        <option>\r
+          <name>MemOverride</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>MemFile</name>\r
+          <state>$TOOLKIT_DIR$\CONFIG\debugger\Fujitsu\iomb9bf506n.ddf</state>\r
+        </option>\r
+        <option>\r
+          <name>RunToEnable</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>RunToName</name>\r
+          <state>main</state>\r
+        </option>\r
+        <option>\r
+          <name>CExtraOptionsCheck</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CExtraOptions</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>CFpuProcessor</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>OCDDFArgumentProducer</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>OCDownloadSuppressDownload</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCDownloadVerifyAll</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>OCProductVersion</name>\r
+          <state>5.50.5.51996</state>\r
+        </option>\r
+        <option>\r
+          <name>OCDynDriverList</name>\r
+          <state>JLINK_ID</state>\r
+        </option>\r
+        <option>\r
+          <name>OCLastSavedByProductVersion</name>\r
+          <state>6.20.1.52589</state>\r
+        </option>\r
+        <option>\r
+          <name>OCDownloadAttachToProgram</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>UseFlashLoader</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CLowLevel</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>OCBE8Slave</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>MacFile2</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>CDevice</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>FlashLoadersV3</name>\r
+          <state>$PROJ_DIR$\config\flashloader\FlashLoader.board</state>\r
+        </option>\r
+        <option>\r
+          <name>OCImagesSuppressCheck1</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCImagesPath1</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>OCImagesSuppressCheck2</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCImagesPath2</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>OCImagesSuppressCheck3</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCImagesPath3</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>OverrideDefFlashBoard</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>OCImagesOffset1</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>OCImagesOffset2</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>OCImagesOffset3</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>OCImagesUse1</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCImagesUse2</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCImagesUse3</name>\r
+          <state>0</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>ARMSIM_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>1</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>OCSimDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>OCSimEnablePSP</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCSimPspOverrideConfig</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCSimPspConfigFile</name>\r
+          <state></state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>ANGEL_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>0</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>CCAngelHeartbeat</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CAngelCommunication</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CAngelCommBaud</name>\r
+          <version>0</version>\r
+          <state>3</state>\r
+        </option>\r
+        <option>\r
+          <name>CAngelCommPort</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>ANGELTCPIP</name>\r
+          <state>aaa.bbb.ccc.ddd</state>\r
+        </option>\r
+        <option>\r
+          <name>DoAngelLogfile</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>AngelLogFile</name>\r
+          <state>$PROJ_DIR$\cspycomm.log</state>\r
+        </option>\r
+        <option>\r
+          <name>OCDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>GDBSERVER_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>0</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>OCDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>TCPIP</name>\r
+          <state>aaa.bbb.ccc.ddd</state>\r
+        </option>\r
+        <option>\r
+          <name>DoLogfile</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>LogFile</name>\r
+          <state>$PROJ_DIR$\cspycomm.log</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJTagBreakpointRadio</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJTagDoUpdateBreakpoints</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJTagUpdateBreakpoints</name>\r
+          <state>_call_main</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>IARROM_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>1</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>CRomLogFileCheck</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CRomLogFileEditB</name>\r
+          <state>$PROJ_DIR$\cspycomm.log</state>\r
+        </option>\r
+        <option>\r
+          <name>CRomCommPort</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CRomCommBaud</name>\r
+          <version>0</version>\r
+          <state>7</state>\r
+        </option>\r
+        <option>\r
+          <name>OCDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>JLINK_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>13</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>JLinkSpeed</name>\r
+          <state>32</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkDoLogfile</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkLogFile</name>\r
+          <state>$PROJ_DIR$\cspycomm.log</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkHWResetDelay</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>JLinkInitialSpeed</name>\r
+          <state>32</state>\r
+        </option>\r
+        <option>\r
+          <name>CCDoJlinkMultiTarget</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCScanChainNonARMDevices</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkMultiTarget</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkIRLength</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkCommRadio</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkTCPIP</name>\r
+          <state>aaa.bbb.ccc.ddd</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkSpeedRadioV2</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCUSBDevice</name>\r
+          <version>1</version>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchReset</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchUndef</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchSWI</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchData</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchPrefetch</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchIRQ</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchFIQ</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkBreakpointRadio</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkDoUpdateBreakpoints</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkUpdateBreakpoints</name>\r
+          <state>_call_main</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkInterfaceRadio</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCJLinkAttachSlave</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkResetList</name>\r
+          <version>5</version>\r
+          <state>7</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkInterfaceCmdLine</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCCatchCORERESET</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCCatchMMERR</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCCatchNOCPERR</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCCatchCHRERR</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCCatchSTATERR</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCCatchBUSERR</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCCatchINTERR</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCCatchHARDERR</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCCatchDummy</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCJLinkScriptFile</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkUsbSerialNo</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>CCTcpIpAlt</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkTcpIpSerialNo</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>CCCpuClockEdit</name>\r
+          <state>72.0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCSwoClockAuto</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCSwoClockEdit</name>\r
+          <state>2000</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>LMIFTDI_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>2</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>OCDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>LmiftdiSpeed</name>\r
+          <state>500</state>\r
+        </option>\r
+        <option>\r
+          <name>CCLmiftdiDoLogfile</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCLmiftdiLogFile</name>\r
+          <state>$PROJ_DIR$\cspycomm.log</state>\r
+        </option>\r
+        <option>\r
+          <name>CCLmiFtdiInterfaceRadio</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCLmiFtdiInterfaceCmdLine</name>\r
+          <state>0</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>MACRAIGOR_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>3</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>jtag</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>EmuSpeed</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>TCPIP</name>\r
+          <state>aaa.bbb.ccc.ddd</state>\r
+        </option>\r
+        <option>\r
+          <name>DoLogfile</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>LogFile</name>\r
+          <state>$PROJ_DIR$\cspycomm.log</state>\r
+        </option>\r
+        <option>\r
+          <name>DoEmuMultiTarget</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>EmuMultiTarget</name>\r
+          <state>0@ARM7TDMI</state>\r
+        </option>\r
+        <option>\r
+          <name>EmuHWReset</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CEmuCommBaud</name>\r
+          <version>0</version>\r
+          <state>4</state>\r
+        </option>\r
+        <option>\r
+          <name>CEmuCommPort</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>jtago</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>UnusedAddr</name>\r
+          <state>0x00800000</state>\r
+        </option>\r
+        <option>\r
+          <name>CCMacraigorHWResetDelay</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>CCJTagBreakpointRadio</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJTagDoUpdateBreakpoints</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJTagUpdateBreakpoints</name>\r
+          <state>_call_main</state>\r
+        </option>\r
+        <option>\r
+          <name>CCMacraigorInterfaceRadio</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCMacraigorInterfaceCmdLine</name>\r
+          <state>0</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>PEMICRO_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>0</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>OCDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>OCPEMicroAttachSlave</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CCPEMicroInterfaceList</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCPEMicroResetDelay</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>CCPEMicroJtagSpeed</name>\r
+          <state>#UNINITIALIZED#</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJPEMicroShowSettings</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>DoLogfile</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>LogFile</name>\r
+          <state>$PROJ_DIR$\cspycomm.log</state>\r
+        </option>\r
+        <option>\r
+          <name>CCPEMicroUSBDevice</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCPEMicroSerialPort</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJPEMicroTCPIPAutoScanNetwork</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CCPEMicroTCPIP</name>\r
+          <state>10.0.0.1</state>\r
+        </option>\r
+        <option>\r
+          <name>CCPEMicroCommCmdLineProducer</name>\r
+          <state>0</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>RDI_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>2</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>CRDIDriverDll</name>\r
+          <state>###Uninitialized###</state>\r
+        </option>\r
+        <option>\r
+          <name>CRDILogFileCheck</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CRDILogFileEdit</name>\r
+          <state>$PROJ_DIR$\cspycomm.log</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDIHWReset</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchReset</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchUndef</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchSWI</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchData</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchPrefetch</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchIRQ</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchFIQ</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>STLINK_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>2</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>OCDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CCSTLinkInterfaceRadio</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCSTLinkInterfaceCmdLine</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCSTLinkResetList</name>\r
+          <version>1</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCCpuClockEdit</name>\r
+          <state>72.0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCSwoClockAuto</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCSwoClockEdit</name>\r
+          <state>2000</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>THIRDPARTY_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>0</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>CThirdPartyDriverDll</name>\r
+          <state>###Uninitialized###</state>\r
+        </option>\r
+        <option>\r
+          <name>CThirdPartyLogFileCheck</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CThirdPartyLogFileEditB</name>\r
+          <state>$PROJ_DIR$\cspycomm.log</state>\r
+        </option>\r
+        <option>\r
+          <name>OCDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <debuggerPlugins>\r
+      <plugin>\r
+        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$TOOLKIT_DIR$\plugins\rtos\PowerPac\PowerPacRTOS.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB6_Plugin.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin</file>\r
+        <loadFlag>1</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$EW_DIR$\common\plugins\FreeRTOS\FreeRTOSPlugin.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$EW_DIR$\common\plugins\OpenRTOS\OpenRTOSPlugin.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$EW_DIR$\common\plugins\Stack\Stack.ENU.ewplugin</file>\r
+        <loadFlag>1</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin</file>\r
+        <loadFlag>1</loadFlag>\r
+      </plugin>\r
+    </debuggerPlugins>\r
+  </configuration>\r
+  <configuration>\r
+    <name>Full</name>\r
+    <toolchain>\r
+      <name>ARM</name>\r
+    </toolchain>\r
+    <debug>1</debug>\r
+    <settings>\r
+      <name>C-SPY</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>22</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>CInput</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CEndian</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CProcessor</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>OCVariant</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>MacOverride</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>MacFile</name>\r
+          <state>$PROJ_DIR$\config\Ram_VTOR.mac</state>\r
+        </option>\r
+        <option>\r
+          <name>MemOverride</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>MemFile</name>\r
+          <state>$TOOLKIT_DIR$\CONFIG\debugger\Fujitsu\iomb9bf506n.ddf</state>\r
+        </option>\r
+        <option>\r
+          <name>RunToEnable</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>RunToName</name>\r
+          <state>main</state>\r
+        </option>\r
+        <option>\r
+          <name>CExtraOptionsCheck</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CExtraOptions</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>CFpuProcessor</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>OCDDFArgumentProducer</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>OCDownloadSuppressDownload</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCDownloadVerifyAll</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>OCProductVersion</name>\r
+          <state>5.50.5.51996</state>\r
+        </option>\r
+        <option>\r
+          <name>OCDynDriverList</name>\r
+          <state>JLINK_ID</state>\r
+        </option>\r
+        <option>\r
+          <name>OCLastSavedByProductVersion</name>\r
+          <state>6.20.1.52589</state>\r
+        </option>\r
+        <option>\r
+          <name>OCDownloadAttachToProgram</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>UseFlashLoader</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CLowLevel</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>OCBE8Slave</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>MacFile2</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>CDevice</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>FlashLoadersV3</name>\r
+          <state>$PROJ_DIR$\config\flashloader\FlashLoader.board</state>\r
+        </option>\r
+        <option>\r
+          <name>OCImagesSuppressCheck1</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCImagesPath1</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>OCImagesSuppressCheck2</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCImagesPath2</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>OCImagesSuppressCheck3</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCImagesPath3</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>OverrideDefFlashBoard</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>OCImagesOffset1</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>OCImagesOffset2</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>OCImagesOffset3</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>OCImagesUse1</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCImagesUse2</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCImagesUse3</name>\r
+          <state>0</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>ARMSIM_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>1</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>OCSimDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>OCSimEnablePSP</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCSimPspOverrideConfig</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCSimPspConfigFile</name>\r
+          <state></state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>ANGEL_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>0</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>CCAngelHeartbeat</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CAngelCommunication</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CAngelCommBaud</name>\r
+          <version>0</version>\r
+          <state>3</state>\r
+        </option>\r
+        <option>\r
+          <name>CAngelCommPort</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>ANGELTCPIP</name>\r
+          <state>aaa.bbb.ccc.ddd</state>\r
+        </option>\r
+        <option>\r
+          <name>DoAngelLogfile</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>AngelLogFile</name>\r
+          <state>$PROJ_DIR$\cspycomm.log</state>\r
+        </option>\r
+        <option>\r
+          <name>OCDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>GDBSERVER_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>0</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>OCDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>TCPIP</name>\r
+          <state>aaa.bbb.ccc.ddd</state>\r
+        </option>\r
+        <option>\r
+          <name>DoLogfile</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>LogFile</name>\r
+          <state>$PROJ_DIR$\cspycomm.log</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJTagBreakpointRadio</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJTagDoUpdateBreakpoints</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJTagUpdateBreakpoints</name>\r
+          <state>_call_main</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>IARROM_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>1</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>CRomLogFileCheck</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CRomLogFileEditB</name>\r
+          <state>$PROJ_DIR$\cspycomm.log</state>\r
+        </option>\r
+        <option>\r
+          <name>CRomCommPort</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CRomCommBaud</name>\r
+          <version>0</version>\r
+          <state>7</state>\r
+        </option>\r
+        <option>\r
+          <name>OCDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>JLINK_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>13</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>JLinkSpeed</name>\r
+          <state>32</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkDoLogfile</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkLogFile</name>\r
+          <state>$PROJ_DIR$\cspycomm.log</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkHWResetDelay</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>JLinkInitialSpeed</name>\r
+          <state>32</state>\r
+        </option>\r
+        <option>\r
+          <name>CCDoJlinkMultiTarget</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCScanChainNonARMDevices</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkMultiTarget</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkIRLength</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkCommRadio</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkTCPIP</name>\r
+          <state>aaa.bbb.ccc.ddd</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkSpeedRadioV2</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCUSBDevice</name>\r
+          <version>1</version>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchReset</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchUndef</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchSWI</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchData</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchPrefetch</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchIRQ</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchFIQ</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkBreakpointRadio</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkDoUpdateBreakpoints</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkUpdateBreakpoints</name>\r
+          <state>_call_main</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkInterfaceRadio</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCJLinkAttachSlave</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkResetList</name>\r
+          <version>5</version>\r
+          <state>7</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkInterfaceCmdLine</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCCatchCORERESET</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCCatchMMERR</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCCatchNOCPERR</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCCatchCHRERR</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCCatchSTATERR</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCCatchBUSERR</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCCatchINTERR</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCCatchHARDERR</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCCatchDummy</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCJLinkScriptFile</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkUsbSerialNo</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>CCTcpIpAlt</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkTcpIpSerialNo</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>CCCpuClockEdit</name>\r
+          <state>72.0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCSwoClockAuto</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCSwoClockEdit</name>\r
+          <state>2000</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>LMIFTDI_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>2</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>OCDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>LmiftdiSpeed</name>\r
+          <state>500</state>\r
+        </option>\r
+        <option>\r
+          <name>CCLmiftdiDoLogfile</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCLmiftdiLogFile</name>\r
+          <state>$PROJ_DIR$\cspycomm.log</state>\r
+        </option>\r
+        <option>\r
+          <name>CCLmiFtdiInterfaceRadio</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCLmiFtdiInterfaceCmdLine</name>\r
+          <state>0</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>MACRAIGOR_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>3</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>jtag</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>EmuSpeed</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>TCPIP</name>\r
+          <state>aaa.bbb.ccc.ddd</state>\r
+        </option>\r
+        <option>\r
+          <name>DoLogfile</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>LogFile</name>\r
+          <state>$PROJ_DIR$\cspycomm.log</state>\r
+        </option>\r
+        <option>\r
+          <name>DoEmuMultiTarget</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>EmuMultiTarget</name>\r
+          <state>0@ARM7TDMI</state>\r
+        </option>\r
+        <option>\r
+          <name>EmuHWReset</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CEmuCommBaud</name>\r
+          <version>0</version>\r
+          <state>4</state>\r
+        </option>\r
+        <option>\r
+          <name>CEmuCommPort</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>jtago</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>UnusedAddr</name>\r
+          <state>0x00800000</state>\r
+        </option>\r
+        <option>\r
+          <name>CCMacraigorHWResetDelay</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>CCJTagBreakpointRadio</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJTagDoUpdateBreakpoints</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJTagUpdateBreakpoints</name>\r
+          <state>_call_main</state>\r
+        </option>\r
+        <option>\r
+          <name>CCMacraigorInterfaceRadio</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCMacraigorInterfaceCmdLine</name>\r
+          <state>0</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>PEMICRO_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>0</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>OCDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>OCPEMicroAttachSlave</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CCPEMicroInterfaceList</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCPEMicroResetDelay</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>CCPEMicroJtagSpeed</name>\r
+          <state>#UNINITIALIZED#</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJPEMicroShowSettings</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>DoLogfile</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>LogFile</name>\r
+          <state>$PROJ_DIR$\cspycomm.log</state>\r
+        </option>\r
+        <option>\r
+          <name>CCPEMicroUSBDevice</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCPEMicroSerialPort</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJPEMicroTCPIPAutoScanNetwork</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CCPEMicroTCPIP</name>\r
+          <state>10.0.0.1</state>\r
+        </option>\r
+        <option>\r
+          <name>CCPEMicroCommCmdLineProducer</name>\r
+          <state>0</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>RDI_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>2</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>CRDIDriverDll</name>\r
+          <state>###Uninitialized###</state>\r
+        </option>\r
+        <option>\r
+          <name>CRDILogFileCheck</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CRDILogFileEdit</name>\r
+          <state>$PROJ_DIR$\cspycomm.log</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDIHWReset</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchReset</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchUndef</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchSWI</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchData</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchPrefetch</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchIRQ</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchFIQ</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>STLINK_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>2</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>OCDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CCSTLinkInterfaceRadio</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCSTLinkInterfaceCmdLine</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCSTLinkResetList</name>\r
+          <version>1</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCCpuClockEdit</name>\r
+          <state>72.0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCSwoClockAuto</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCSwoClockEdit</name>\r
+          <state>2000</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>THIRDPARTY_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>0</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>CThirdPartyDriverDll</name>\r
+          <state>###Uninitialized###</state>\r
+        </option>\r
+        <option>\r
+          <name>CThirdPartyLogFileCheck</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CThirdPartyLogFileEditB</name>\r
+          <state>$PROJ_DIR$\cspycomm.log</state>\r
+        </option>\r
+        <option>\r
+          <name>OCDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <debuggerPlugins>\r
+      <plugin>\r
+        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$TOOLKIT_DIR$\plugins\rtos\PowerPac\PowerPacRTOS.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB6_Plugin.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin</file>\r
+        <loadFlag>1</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$EW_DIR$\common\plugins\FreeRTOS\FreeRTOSPlugin.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$EW_DIR$\common\plugins\OpenRTOS\OpenRTOSPlugin.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$EW_DIR$\common\plugins\Stack\Stack.ENU.ewplugin</file>\r
+        <loadFlag>1</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin</file>\r
+        <loadFlag>1</loadFlag>\r
+      </plugin>\r
+    </debuggerPlugins>\r
+  </configuration>\r
+  <configuration>\r
+    <name>Full_with_optimisation</name>\r
+    <toolchain>\r
+      <name>ARM</name>\r
+    </toolchain>\r
+    <debug>1</debug>\r
+    <settings>\r
+      <name>C-SPY</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>22</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>CInput</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CEndian</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CProcessor</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>OCVariant</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>MacOverride</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>MacFile</name>\r
+          <state>$PROJ_DIR$\config\Ram_VTOR.mac</state>\r
+        </option>\r
+        <option>\r
+          <name>MemOverride</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>MemFile</name>\r
+          <state>$TOOLKIT_DIR$\CONFIG\debugger\Fujitsu\iomb9bf506n.ddf</state>\r
+        </option>\r
+        <option>\r
+          <name>RunToEnable</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>RunToName</name>\r
+          <state>main</state>\r
+        </option>\r
+        <option>\r
+          <name>CExtraOptionsCheck</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CExtraOptions</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>CFpuProcessor</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>OCDDFArgumentProducer</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>OCDownloadSuppressDownload</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCDownloadVerifyAll</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>OCProductVersion</name>\r
+          <state>5.50.5.51996</state>\r
+        </option>\r
+        <option>\r
+          <name>OCDynDriverList</name>\r
+          <state>JLINK_ID</state>\r
+        </option>\r
+        <option>\r
+          <name>OCLastSavedByProductVersion</name>\r
+          <state>6.20.1.52589</state>\r
+        </option>\r
+        <option>\r
+          <name>OCDownloadAttachToProgram</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>UseFlashLoader</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CLowLevel</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>OCBE8Slave</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>MacFile2</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>CDevice</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>FlashLoadersV3</name>\r
+          <state>$PROJ_DIR$\config\flashloader\FlashLoader.board</state>\r
+        </option>\r
+        <option>\r
+          <name>OCImagesSuppressCheck1</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCImagesPath1</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>OCImagesSuppressCheck2</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCImagesPath2</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>OCImagesSuppressCheck3</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCImagesPath3</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>OverrideDefFlashBoard</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>OCImagesOffset1</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>OCImagesOffset2</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>OCImagesOffset3</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>OCImagesUse1</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCImagesUse2</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCImagesUse3</name>\r
+          <state>0</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>ARMSIM_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>1</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>OCSimDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>OCSimEnablePSP</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCSimPspOverrideConfig</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCSimPspConfigFile</name>\r
+          <state></state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>ANGEL_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>0</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>CCAngelHeartbeat</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CAngelCommunication</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CAngelCommBaud</name>\r
+          <version>0</version>\r
+          <state>3</state>\r
+        </option>\r
+        <option>\r
+          <name>CAngelCommPort</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>ANGELTCPIP</name>\r
+          <state>aaa.bbb.ccc.ddd</state>\r
+        </option>\r
+        <option>\r
+          <name>DoAngelLogfile</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>AngelLogFile</name>\r
+          <state>$PROJ_DIR$\cspycomm.log</state>\r
+        </option>\r
+        <option>\r
+          <name>OCDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>GDBSERVER_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>0</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>OCDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>TCPIP</name>\r
+          <state>aaa.bbb.ccc.ddd</state>\r
+        </option>\r
+        <option>\r
+          <name>DoLogfile</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>LogFile</name>\r
+          <state>$PROJ_DIR$\cspycomm.log</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJTagBreakpointRadio</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJTagDoUpdateBreakpoints</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJTagUpdateBreakpoints</name>\r
+          <state>_call_main</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>IARROM_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>1</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>CRomLogFileCheck</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CRomLogFileEditB</name>\r
+          <state>$PROJ_DIR$\cspycomm.log</state>\r
+        </option>\r
+        <option>\r
+          <name>CRomCommPort</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CRomCommBaud</name>\r
+          <version>0</version>\r
+          <state>7</state>\r
+        </option>\r
+        <option>\r
+          <name>OCDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>JLINK_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>13</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>JLinkSpeed</name>\r
+          <state>32</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkDoLogfile</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkLogFile</name>\r
+          <state>$PROJ_DIR$\cspycomm.log</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkHWResetDelay</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>JLinkInitialSpeed</name>\r
+          <state>32</state>\r
+        </option>\r
+        <option>\r
+          <name>CCDoJlinkMultiTarget</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCScanChainNonARMDevices</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkMultiTarget</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkIRLength</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkCommRadio</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkTCPIP</name>\r
+          <state>aaa.bbb.ccc.ddd</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkSpeedRadioV2</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCUSBDevice</name>\r
+          <version>1</version>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchReset</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchUndef</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchSWI</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchData</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchPrefetch</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchIRQ</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchFIQ</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkBreakpointRadio</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkDoUpdateBreakpoints</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkUpdateBreakpoints</name>\r
+          <state>_call_main</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkInterfaceRadio</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCJLinkAttachSlave</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkResetList</name>\r
+          <version>5</version>\r
+          <state>7</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkInterfaceCmdLine</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCCatchCORERESET</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCCatchMMERR</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCCatchNOCPERR</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCCatchCHRERR</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCCatchSTATERR</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCCatchBUSERR</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCCatchINTERR</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCCatchHARDERR</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCCatchDummy</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCJLinkScriptFile</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkUsbSerialNo</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>CCTcpIpAlt</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkTcpIpSerialNo</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>CCCpuClockEdit</name>\r
+          <state>72.0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCSwoClockAuto</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCSwoClockEdit</name>\r
+          <state>2000</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>LMIFTDI_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>2</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>OCDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>LmiftdiSpeed</name>\r
+          <state>500</state>\r
+        </option>\r
+        <option>\r
+          <name>CCLmiftdiDoLogfile</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCLmiftdiLogFile</name>\r
+          <state>$PROJ_DIR$\cspycomm.log</state>\r
+        </option>\r
+        <option>\r
+          <name>CCLmiFtdiInterfaceRadio</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCLmiFtdiInterfaceCmdLine</name>\r
+          <state>0</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>MACRAIGOR_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>3</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>jtag</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>EmuSpeed</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>TCPIP</name>\r
+          <state>aaa.bbb.ccc.ddd</state>\r
+        </option>\r
+        <option>\r
+          <name>DoLogfile</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>LogFile</name>\r
+          <state>$PROJ_DIR$\cspycomm.log</state>\r
+        </option>\r
+        <option>\r
+          <name>DoEmuMultiTarget</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>EmuMultiTarget</name>\r
+          <state>0@ARM7TDMI</state>\r
+        </option>\r
+        <option>\r
+          <name>EmuHWReset</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CEmuCommBaud</name>\r
+          <version>0</version>\r
+          <state>4</state>\r
+        </option>\r
+        <option>\r
+          <name>CEmuCommPort</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>jtago</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>UnusedAddr</name>\r
+          <state>0x00800000</state>\r
+        </option>\r
+        <option>\r
+          <name>CCMacraigorHWResetDelay</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>CCJTagBreakpointRadio</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJTagDoUpdateBreakpoints</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJTagUpdateBreakpoints</name>\r
+          <state>_call_main</state>\r
+        </option>\r
+        <option>\r
+          <name>CCMacraigorInterfaceRadio</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCMacraigorInterfaceCmdLine</name>\r
+          <state>0</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>PEMICRO_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>0</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>OCDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>OCPEMicroAttachSlave</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CCPEMicroInterfaceList</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCPEMicroResetDelay</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>CCPEMicroJtagSpeed</name>\r
+          <state>#UNINITIALIZED#</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJPEMicroShowSettings</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>DoLogfile</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>LogFile</name>\r
+          <state>$PROJ_DIR$\cspycomm.log</state>\r
+        </option>\r
+        <option>\r
+          <name>CCPEMicroUSBDevice</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCPEMicroSerialPort</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJPEMicroTCPIPAutoScanNetwork</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CCPEMicroTCPIP</name>\r
+          <state>10.0.0.1</state>\r
+        </option>\r
+        <option>\r
+          <name>CCPEMicroCommCmdLineProducer</name>\r
+          <state>0</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>RDI_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>2</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>CRDIDriverDll</name>\r
+          <state>###Uninitialized###</state>\r
+        </option>\r
+        <option>\r
+          <name>CRDILogFileCheck</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CRDILogFileEdit</name>\r
+          <state>$PROJ_DIR$\cspycomm.log</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDIHWReset</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchReset</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchUndef</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchSWI</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchData</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchPrefetch</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchIRQ</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchFIQ</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>STLINK_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>2</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>OCDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CCSTLinkInterfaceRadio</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCSTLinkInterfaceCmdLine</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCSTLinkResetList</name>\r
+          <version>1</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCCpuClockEdit</name>\r
+          <state>72.0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCSwoClockAuto</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCSwoClockEdit</name>\r
+          <state>2000</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>THIRDPARTY_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>0</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>CThirdPartyDriverDll</name>\r
+          <state>###Uninitialized###</state>\r
+        </option>\r
+        <option>\r
+          <name>CThirdPartyLogFileCheck</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CThirdPartyLogFileEditB</name>\r
+          <state>$PROJ_DIR$\cspycomm.log</state>\r
+        </option>\r
+        <option>\r
+          <name>OCDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <debuggerPlugins>\r
+      <plugin>\r
+        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$TOOLKIT_DIR$\plugins\rtos\PowerPac\PowerPacRTOS.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB6_Plugin.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin</file>\r
+        <loadFlag>1</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$EW_DIR$\common\plugins\FreeRTOS\FreeRTOSPlugin.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$EW_DIR$\common\plugins\OpenRTOS\OpenRTOSPlugin.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$EW_DIR$\common\plugins\Stack\Stack.ENU.ewplugin</file>\r
+        <loadFlag>1</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin</file>\r
+        <loadFlag>1</loadFlag>\r
+      </plugin>\r
+    </debuggerPlugins>\r
+  </configuration>\r
+</project>\r
+\r
+\r

diff --git a/Demo/CORTEX_MB9A310_IAR_Keil/RTOSDemo_IAR.ewp b/Demo/CORTEX_MB9A310_IAR_Keil/RTOSDemo_IAR.ewp
new file mode 100644 (file)
index 0000000..4670d1c
--- /dev/null
+++ b/Demo/CORTEX_MB9A310_IAR_Keil/RTOSDemo_IAR.ewp
@@ -0,0 +1,2809 @@
+<?xml version="1.0" encoding="iso-8859-1"?>\r
+\r
+<project>\r
+  <fileVersion>2</fileVersion>\r
+  <configuration>\r
+    <name>Blinky</name>\r
+    <toolchain>\r
+      <name>ARM</name>\r
+    </toolchain>\r
+    <debug>1</debug>\r
+    <settings>\r
+      <name>General</name>\r
+      <archiveVersion>3</archiveVersion>\r
+      <data>\r
+        <version>21</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>ExePath</name>\r
+          <state>Blinky\Exe</state>\r
+        </option>\r
+        <option>\r
+          <name>ObjPath</name>\r
+          <state>Blinky\Obj</state>\r
+        </option>\r
+        <option>\r
+          <name>ListPath</name>\r
+          <state>Blinky\List</state>\r
+        </option>\r
+        <option>\r
+          <name>Variant</name>\r
+          <version>19</version>\r
+          <state>37</state>\r
+        </option>\r
+        <option>\r
+          <name>GEndianMode</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>Input variant</name>\r
+          <version>3</version>\r
+          <state>6</state>\r
+        </option>\r
+        <option>\r
+          <name>Input description</name>\r
+          <state>No specifier n, no float nor long long, no scan set, no assignment suppressing.</state>\r
+        </option>\r
+        <option>\r
+          <name>Output variant</name>\r
+          <version>2</version>\r
+          <state>7</state>\r
+        </option>\r
+        <option>\r
+          <name>Output description</name>\r
+          <state>No specifier a, A, no specifier n, no float nor long long, no flags.</state>\r
+        </option>\r
+        <option>\r
+          <name>GOutputBinary</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>FPU</name>\r
+          <version>2</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OGCoreOrChip</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>GRuntimeLibSelect</name>\r
+          <version>0</version>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>GRuntimeLibSelectSlave</name>\r
+          <version>0</version>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>RTDescription</name>\r
+          <state>Use the normal configuration of the C/C++ runtime library. No locale interface, C locale, no file descriptor support, no multibytes in printf and scanf, and no hex floats in strtod.</state>\r
+        </option>\r
+        <option>\r
+          <name>OGProductVersion</name>\r
+          <state>5.50.5.51996</state>\r
+        </option>\r
+        <option>\r
+          <name>OGLastSavedByProductVersion</name>\r
+          <state>6.21.1.52845</state>\r
+        </option>\r
+        <option>\r
+          <name>GeneralEnableMisra</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>GeneralMisraVerbose</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OGChipSelectEditMenu</name>\r
+          <state>MB9AF314L     Fujitsu MB9AF314L</state>\r
+        </option>\r
+        <option>\r
+          <name>GenLowLevelInterface</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>GEndianModeBE</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>OGBufferedTerminalOutput</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>GenStdoutInterface</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>GeneralMisraRules98</name>\r
+          <version>0</version>\r
+          <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>\r
+        </option>\r
+        <option>\r
+          <name>GeneralMisraVer</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>GeneralMisraRules04</name>\r
+          <version>0</version>\r
+          <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>\r
+        </option>\r
+        <option>\r
+          <name>RTConfigPath2</name>\r
+          <state>$TOOLKIT_DIR$\INC\c\DLib_Config_Normal.h</state>\r
+        </option>\r
+        <option>\r
+          <name>GFPUCoreSlave</name>\r
+          <version>19</version>\r
+          <state>37</state>\r
+        </option>\r
+        <option>\r
+          <name>GBECoreSlave</name>\r
+          <version>19</version>\r
+          <state>37</state>\r
+        </option>\r
+        <option>\r
+          <name>OGUseCmsis</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>OGUseCmsisDspLib</name>\r
+          <state>0</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>ICCARM</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>28</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>CCDefines</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>CCPreprocFile</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCPreprocComments</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCPreprocLine</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCListCFile</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCListCMnemonics</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCListCMessages</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCListAssFile</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCListAssSource</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCEnableRemarks</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCDiagSuppress</name>\r
+          <state>Pa082</state>\r
+        </option>\r
+        <option>\r
+          <name>CCDiagRemark</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>CCDiagWarning</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>CCDiagError</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>CCObjPrefix</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CCAllowList</name>\r
+          <version>1</version>\r
+          <state>0000000</state>\r
+        </option>\r
+        <option>\r
+          <name>CCDebugInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IEndianMode</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IProcessor</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IExtraOptionsCheck</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IExtraOptions</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>CCLangConformance</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCSignedPlainChar</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRequirePrototypes</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCMultibyteSupport</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCDiagWarnAreErr</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCCompilerRuntimeInfo</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IFpuProcessor</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>OutputFile</name>\r
+          <state>$FILE_BNAME$.o</state>\r
+        </option>\r
+        <option>\r
+          <name>CCLibConfigHeader</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>PreInclude</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>CompilerMisraOverride</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCIncludePath2</name>\r
+          <state>$PROJ_DIR$/Fujitu_source</state>\r
+          <state>$PROJ_DIR$</state>\r
+          <state>$PROJ_DIR$/../../Source/include</state>\r
+          <state>$PROJ_DIR$/../../Source/portable/IAR/ARM_CM3</state>\r
+        </option>\r
+        <option>\r
+          <name>CCStdIncCheck</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCCodeSection</name>\r
+          <state>.text</state>\r
+        </option>\r
+        <option>\r
+          <name>IInterwork2</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IProcessorMode2</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CCOptLevel</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCOptStrategy</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCOptLevelSlave</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CompilerMisraRules98</name>\r
+          <version>0</version>\r
+          <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>\r
+        </option>\r
+        <option>\r
+          <name>CompilerMisraRules04</name>\r
+          <version>0</version>\r
+          <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>\r
+        </option>\r
+        <option>\r
+          <name>CCPosIndRopi</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCPosIndRwpi</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCPosIndNoDynInit</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IccLang</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IccCDialect</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IccAllowVLA</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IccCppDialect</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IccExceptions</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IccRTTI</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IccStaticDestr</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IccCppInlineSemantics</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IccCmsis</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IccFloatSemantics</name>\r
+          <state>0</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>AARM</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>8</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>AObjPrefix</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>AEndian</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>ACaseSensitivity</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>MacroChars</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>AWarnEnable</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>AWarnWhat</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>AWarnOne</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>AWarnRange1</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>AWarnRange2</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>ADebug</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>AltRegisterNames</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>ADefines</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>AList</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>AListHeader</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>AListing</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>Includes</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>MacDefs</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>MacExps</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>MacExec</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OnlyAssed</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>MultiLine</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>PageLengthCheck</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>PageLength</name>\r
+          <state>80</state>\r
+        </option>\r
+        <option>\r
+          <name>TabSpacing</name>\r
+          <state>8</state>\r
+        </option>\r
+        <option>\r
+          <name>AXRef</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>AXRefDefines</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>AXRefInternal</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>AXRefDual</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>AProcessor</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>AFpuProcessor</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>AOutputFile</name>\r
+          <state>$FILE_BNAME$.o</state>\r
+        </option>\r
+        <option>\r
+          <name>AMultibyteSupport</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>ALimitErrorsCheck</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>ALimitErrorsEdit</name>\r
+          <state>100</state>\r
+        </option>\r
+        <option>\r
+          <name>AIgnoreStdInclude</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>AUserIncludes</name>\r
+          <state>$PROJ_DIR$</state>\r
+        </option>\r
+        <option>\r
+          <name>AExtraOptionsCheckV2</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>AExtraOptionsV2</name>\r
+          <state></state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>OBJCOPY</name>\r
+      <archiveVersion>0</archiveVersion>\r
+      <data>\r
+        <version>1</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>OOCOutputFormat</name>\r
+          <version>2</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCOutputOverride</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OOCOutputFile</name>\r
+          <state>RTOSDemo_IAR.srec</state>\r
+        </option>\r
+        <option>\r
+          <name>OOCCommandLineProducer</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>OOCObjCopyEnable</name>\r
+          <state>0</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>CUSTOM</name>\r
+      <archiveVersion>3</archiveVersion>\r
+      <data>\r
+        <extensions></extensions>\r
+        <cmdline></cmdline>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>BICOMP</name>\r
+      <archiveVersion>0</archiveVersion>\r
+      <data/>\r
+    </settings>\r
+    <settings>\r
+      <name>BUILDACTION</name>\r
+      <archiveVersion>1</archiveVersion>\r
+      <data>\r
+        <prebuild></prebuild>\r
+        <postbuild></postbuild>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>ILINK</name>\r
+      <archiveVersion>0</archiveVersion>\r
+      <data>\r
+        <version>13</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>IlinkLibIOConfig</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>XLinkMisraHandler</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkInputFileSlave</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkOutputFile</name>\r
+          <state>RTOSDemo_IAR.out</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkDebugInfoEnable</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkKeepSymbols</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkRawBinaryFile</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkRawBinarySymbol</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkRawBinarySegment</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkRawBinaryAlign</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkDefines</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkConfigDefines</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkMapFile</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkLogFile</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkLogInitialization</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkLogModule</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkLogSection</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkLogVeneer</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkIcfOverride</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkIcfFile</name>\r
+          <state>$PROJ_DIR$\config\mb9af314.icf</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkIcfFileSlave</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkEnableRemarks</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkSuppressDiags</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkTreatAsRem</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkTreatAsWarn</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkTreatAsErr</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkWarningsAreErrors</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkUseExtraOptions</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkExtraOptions</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkLowLevelInterfaceSlave</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkAutoLibEnable</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkAdditionalLibs</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkOverrideProgramEntryLabel</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkProgramEntryLabelSelect</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkProgramEntryLabel</name>\r
+          <state>__iar_program_start</state>\r
+        </option>\r
+        <option>\r
+          <name>DoFill</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>FillerByte</name>\r
+          <state>0xFF</state>\r
+        </option>\r
+        <option>\r
+          <name>FillerStart</name>\r
+          <state>0x0</state>\r
+        </option>\r
+        <option>\r
+          <name>FillerEnd</name>\r
+          <state>0x0</state>\r
+        </option>\r
+        <option>\r
+          <name>CrcSize</name>\r
+          <version>0</version>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CrcAlign</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CrcAlgo</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CrcPoly</name>\r
+          <state>0x11021</state>\r
+        </option>\r
+        <option>\r
+          <name>CrcCompl</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CrcBitOrder</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CrcInitialValue</name>\r
+          <state>0x0</state>\r
+        </option>\r
+        <option>\r
+          <name>DoCrc</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkBE8Slave</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkBufferedTerminalOutput</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkStdoutInterfaceSlave</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CrcFullSize</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkIElfToolPostProcess</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkLogAutoLibSelect</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkLogRedirSymbols</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkLogUnusedFragments</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkCrcReverseByteOrder</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkCrcUseAsInput</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkOptInline</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkOptExceptionsAllow</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkOptExceptionsForce</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkCmsis</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkOptMergeDuplSections</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkOptUseVfe</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkOptForceVfe</name>\r
+          <state>0</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>IARCHIVE</name>\r
+      <archiveVersion>0</archiveVersion>\r
+      <data>\r
+        <version>0</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>IarchiveInputs</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>IarchiveOverride</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IarchiveOutput</name>\r
+          <state>###Unitialized###</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>BILINK</name>\r
+      <archiveVersion>0</archiveVersion>\r
+      <data/>\r
+    </settings>\r
+  </configuration>\r
+  <configuration>\r
+    <name>Full</name>\r
+    <toolchain>\r
+      <name>ARM</name>\r
+    </toolchain>\r
+    <debug>1</debug>\r
+    <settings>\r
+      <name>General</name>\r
+      <archiveVersion>3</archiveVersion>\r
+      <data>\r
+        <version>21</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>ExePath</name>\r
+          <state>Full\Exe</state>\r
+        </option>\r
+        <option>\r
+          <name>ObjPath</name>\r
+          <state>Full\Obj</state>\r
+        </option>\r
+        <option>\r
+          <name>ListPath</name>\r
+          <state>Full\List</state>\r
+        </option>\r
+        <option>\r
+          <name>Variant</name>\r
+          <version>19</version>\r
+          <state>37</state>\r
+        </option>\r
+        <option>\r
+          <name>GEndianMode</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>Input variant</name>\r
+          <version>3</version>\r
+          <state>3</state>\r
+        </option>\r
+        <option>\r
+          <name>Input description</name>\r
+          <state>No specifier n, no float nor long long.</state>\r
+        </option>\r
+        <option>\r
+          <name>Output variant</name>\r
+          <version>2</version>\r
+          <state>3</state>\r
+        </option>\r
+        <option>\r
+          <name>Output description</name>\r
+          <state>No specifier a, A.</state>\r
+        </option>\r
+        <option>\r
+          <name>GOutputBinary</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>FPU</name>\r
+          <version>2</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OGCoreOrChip</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>GRuntimeLibSelect</name>\r
+          <version>0</version>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>GRuntimeLibSelectSlave</name>\r
+          <version>0</version>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>RTDescription</name>\r
+          <state>Use the normal configuration of the C/C++ runtime library. No locale interface, C locale, no file descriptor support, no multibytes in printf and scanf, and no hex floats in strtod.</state>\r
+        </option>\r
+        <option>\r
+          <name>OGProductVersion</name>\r
+          <state>5.50.5.51996</state>\r
+        </option>\r
+        <option>\r
+          <name>OGLastSavedByProductVersion</name>\r
+          <state>6.21.1.52845</state>\r
+        </option>\r
+        <option>\r
+          <name>GeneralEnableMisra</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>GeneralMisraVerbose</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OGChipSelectEditMenu</name>\r
+          <state>MB9AF314L     Fujitsu MB9AF314L</state>\r
+        </option>\r
+        <option>\r
+          <name>GenLowLevelInterface</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>GEndianModeBE</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>OGBufferedTerminalOutput</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>GenStdoutInterface</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>GeneralMisraRules98</name>\r
+          <version>0</version>\r
+          <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>\r
+        </option>\r
+        <option>\r
+          <name>GeneralMisraVer</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>GeneralMisraRules04</name>\r
+          <version>0</version>\r
+          <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>\r
+        </option>\r
+        <option>\r
+          <name>RTConfigPath2</name>\r
+          <state>$TOOLKIT_DIR$\INC\c\DLib_Config_Normal.h</state>\r
+        </option>\r
+        <option>\r
+          <name>GFPUCoreSlave</name>\r
+          <version>19</version>\r
+          <state>37</state>\r
+        </option>\r
+        <option>\r
+          <name>GBECoreSlave</name>\r
+          <version>19</version>\r
+          <state>37</state>\r
+        </option>\r
+        <option>\r
+          <name>OGUseCmsis</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>OGUseCmsisDspLib</name>\r
+          <state>0</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>ICCARM</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>28</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>CCDefines</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>CCPreprocFile</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCPreprocComments</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCPreprocLine</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCListCFile</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCListCMnemonics</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCListCMessages</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCListAssFile</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCListAssSource</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCEnableRemarks</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCDiagSuppress</name>\r
+          <state>Pa082</state>\r
+        </option>\r
+        <option>\r
+          <name>CCDiagRemark</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>CCDiagWarning</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>CCDiagError</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>CCObjPrefix</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CCAllowList</name>\r
+          <version>1</version>\r
+          <state>0000000</state>\r
+        </option>\r
+        <option>\r
+          <name>CCDebugInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IEndianMode</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IProcessor</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IExtraOptionsCheck</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IExtraOptions</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>CCLangConformance</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCSignedPlainChar</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRequirePrototypes</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCMultibyteSupport</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCDiagWarnAreErr</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCCompilerRuntimeInfo</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IFpuProcessor</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>OutputFile</name>\r
+          <state>$FILE_BNAME$.o</state>\r
+        </option>\r
+        <option>\r
+          <name>CCLibConfigHeader</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>PreInclude</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>CompilerMisraOverride</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCIncludePath2</name>\r
+          <state>$PROJ_DIR$/Fujitu_source</state>\r
+          <state>$PROJ_DIR$</state>\r
+          <state>$PROJ_DIR$/../../Source/include</state>\r
+          <state>$PROJ_DIR$/../../Source/portable/IAR/ARM_CM3</state>\r
+          <state>$PROJ_DIR$/../common/include</state>\r
+        </option>\r
+        <option>\r
+          <name>CCStdIncCheck</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCCodeSection</name>\r
+          <state>.text</state>\r
+        </option>\r
+        <option>\r
+          <name>IInterwork2</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IProcessorMode2</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CCOptLevel</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCOptStrategy</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCOptLevelSlave</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CompilerMisraRules98</name>\r
+          <version>0</version>\r
+          <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>\r
+        </option>\r
+        <option>\r
+          <name>CompilerMisraRules04</name>\r
+          <version>0</version>\r
+          <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>\r
+        </option>\r
+        <option>\r
+          <name>CCPosIndRopi</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCPosIndRwpi</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCPosIndNoDynInit</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IccLang</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IccCDialect</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IccAllowVLA</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IccCppDialect</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IccExceptions</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IccRTTI</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IccStaticDestr</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IccCppInlineSemantics</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IccCmsis</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IccFloatSemantics</name>\r
+          <state>0</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>AARM</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>8</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>AObjPrefix</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>AEndian</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>ACaseSensitivity</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>MacroChars</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>AWarnEnable</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>AWarnWhat</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>AWarnOne</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>AWarnRange1</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>AWarnRange2</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>ADebug</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>AltRegisterNames</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>ADefines</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>AList</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>AListHeader</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>AListing</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>Includes</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>MacDefs</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>MacExps</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>MacExec</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OnlyAssed</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>MultiLine</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>PageLengthCheck</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>PageLength</name>\r
+          <state>80</state>\r
+        </option>\r
+        <option>\r
+          <name>TabSpacing</name>\r
+          <state>8</state>\r
+        </option>\r
+        <option>\r
+          <name>AXRef</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>AXRefDefines</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>AXRefInternal</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>AXRefDual</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>AProcessor</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>AFpuProcessor</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>AOutputFile</name>\r
+          <state>$FILE_BNAME$.o</state>\r
+        </option>\r
+        <option>\r
+          <name>AMultibyteSupport</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>ALimitErrorsCheck</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>ALimitErrorsEdit</name>\r
+          <state>100</state>\r
+        </option>\r
+        <option>\r
+          <name>AIgnoreStdInclude</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>AUserIncludes</name>\r
+          <state>$PROJ_DIR$</state>\r
+        </option>\r
+        <option>\r
+          <name>AExtraOptionsCheckV2</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>AExtraOptionsV2</name>\r
+          <state></state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>OBJCOPY</name>\r
+      <archiveVersion>0</archiveVersion>\r
+      <data>\r
+        <version>1</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>OOCOutputFormat</name>\r
+          <version>2</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCOutputOverride</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OOCOutputFile</name>\r
+          <state>RTOSDemo_IAR.srec</state>\r
+        </option>\r
+        <option>\r
+          <name>OOCCommandLineProducer</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>OOCObjCopyEnable</name>\r
+          <state>0</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>CUSTOM</name>\r
+      <archiveVersion>3</archiveVersion>\r
+      <data>\r
+        <extensions></extensions>\r
+        <cmdline></cmdline>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>BICOMP</name>\r
+      <archiveVersion>0</archiveVersion>\r
+      <data/>\r
+    </settings>\r
+    <settings>\r
+      <name>BUILDACTION</name>\r
+      <archiveVersion>1</archiveVersion>\r
+      <data>\r
+        <prebuild></prebuild>\r
+        <postbuild></postbuild>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>ILINK</name>\r
+      <archiveVersion>0</archiveVersion>\r
+      <data>\r
+        <version>13</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>IlinkLibIOConfig</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>XLinkMisraHandler</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkInputFileSlave</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkOutputFile</name>\r
+          <state>RTOSDemo_IAR.out</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkDebugInfoEnable</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkKeepSymbols</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkRawBinaryFile</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkRawBinarySymbol</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkRawBinarySegment</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkRawBinaryAlign</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkDefines</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkConfigDefines</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkMapFile</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkLogFile</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkLogInitialization</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkLogModule</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkLogSection</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkLogVeneer</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkIcfOverride</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkIcfFile</name>\r
+          <state>$PROJ_DIR$\config\mb9af314.icf</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkIcfFileSlave</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkEnableRemarks</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkSuppressDiags</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkTreatAsRem</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkTreatAsWarn</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkTreatAsErr</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkWarningsAreErrors</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkUseExtraOptions</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkExtraOptions</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkLowLevelInterfaceSlave</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkAutoLibEnable</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkAdditionalLibs</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkOverrideProgramEntryLabel</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkProgramEntryLabelSelect</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkProgramEntryLabel</name>\r
+          <state>__iar_program_start</state>\r
+        </option>\r
+        <option>\r
+          <name>DoFill</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>FillerByte</name>\r
+          <state>0xFF</state>\r
+        </option>\r
+        <option>\r
+          <name>FillerStart</name>\r
+          <state>0x0</state>\r
+        </option>\r
+        <option>\r
+          <name>FillerEnd</name>\r
+          <state>0x0</state>\r
+        </option>\r
+        <option>\r
+          <name>CrcSize</name>\r
+          <version>0</version>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CrcAlign</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CrcAlgo</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CrcPoly</name>\r
+          <state>0x11021</state>\r
+        </option>\r
+        <option>\r
+          <name>CrcCompl</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CrcBitOrder</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CrcInitialValue</name>\r
+          <state>0x0</state>\r
+        </option>\r
+        <option>\r
+          <name>DoCrc</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkBE8Slave</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkBufferedTerminalOutput</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkStdoutInterfaceSlave</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CrcFullSize</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkIElfToolPostProcess</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkLogAutoLibSelect</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkLogRedirSymbols</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkLogUnusedFragments</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkCrcReverseByteOrder</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkCrcUseAsInput</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkOptInline</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkOptExceptionsAllow</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkOptExceptionsForce</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkCmsis</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkOptMergeDuplSections</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkOptUseVfe</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkOptForceVfe</name>\r
+          <state>0</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>IARCHIVE</name>\r
+      <archiveVersion>0</archiveVersion>\r
+      <data>\r
+        <version>0</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>IarchiveInputs</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>IarchiveOverride</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IarchiveOutput</name>\r
+          <state>###Unitialized###</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>BILINK</name>\r
+      <archiveVersion>0</archiveVersion>\r
+      <data/>\r
+    </settings>\r
+  </configuration>\r
+  <configuration>\r
+    <name>Full_with_optimisation</name>\r
+    <toolchain>\r
+      <name>ARM</name>\r
+    </toolchain>\r
+    <debug>1</debug>\r
+    <settings>\r
+      <name>General</name>\r
+      <archiveVersion>3</archiveVersion>\r
+      <data>\r
+        <version>21</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>ExePath</name>\r
+          <state>Full_with_optimisation\Exe</state>\r
+        </option>\r
+        <option>\r
+          <name>ObjPath</name>\r
+          <state>Full_with_optimisation\Obj</state>\r
+        </option>\r
+        <option>\r
+          <name>ListPath</name>\r
+          <state>Full_with_optimisation\List</state>\r
+        </option>\r
+        <option>\r
+          <name>Variant</name>\r
+          <version>19</version>\r
+          <state>37</state>\r
+        </option>\r
+        <option>\r
+          <name>GEndianMode</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>Input variant</name>\r
+          <version>3</version>\r
+          <state>3</state>\r
+        </option>\r
+        <option>\r
+          <name>Input description</name>\r
+          <state>No specifier n, no float nor long long.</state>\r
+        </option>\r
+        <option>\r
+          <name>Output variant</name>\r
+          <version>2</version>\r
+          <state>3</state>\r
+        </option>\r
+        <option>\r
+          <name>Output description</name>\r
+          <state>No specifier a, A.</state>\r
+        </option>\r
+        <option>\r
+          <name>GOutputBinary</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>FPU</name>\r
+          <version>2</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OGCoreOrChip</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>GRuntimeLibSelect</name>\r
+          <version>0</version>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>GRuntimeLibSelectSlave</name>\r
+          <version>0</version>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>RTDescription</name>\r
+          <state>Use the normal configuration of the C/C++ runtime library. No locale interface, C locale, no file descriptor support, no multibytes in printf and scanf, and no hex floats in strtod.</state>\r
+        </option>\r
+        <option>\r
+          <name>OGProductVersion</name>\r
+          <state>5.50.5.51996</state>\r
+        </option>\r
+        <option>\r
+          <name>OGLastSavedByProductVersion</name>\r
+          <state>6.21.1.52845</state>\r
+        </option>\r
+        <option>\r
+          <name>GeneralEnableMisra</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>GeneralMisraVerbose</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OGChipSelectEditMenu</name>\r
+          <state>MB9AF314L     Fujitsu MB9AF314L</state>\r
+        </option>\r
+        <option>\r
+          <name>GenLowLevelInterface</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>GEndianModeBE</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>OGBufferedTerminalOutput</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>GenStdoutInterface</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>GeneralMisraRules98</name>\r
+          <version>0</version>\r
+          <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>\r
+        </option>\r
+        <option>\r
+          <name>GeneralMisraVer</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>GeneralMisraRules04</name>\r
+          <version>0</version>\r
+          <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>\r
+        </option>\r
+        <option>\r
+          <name>RTConfigPath2</name>\r
+          <state>$TOOLKIT_DIR$\INC\c\DLib_Config_Normal.h</state>\r
+        </option>\r
+        <option>\r
+          <name>GFPUCoreSlave</name>\r
+          <version>19</version>\r
+          <state>37</state>\r
+        </option>\r
+        <option>\r
+          <name>GBECoreSlave</name>\r
+          <version>19</version>\r
+          <state>37</state>\r
+        </option>\r
+        <option>\r
+          <name>OGUseCmsis</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>OGUseCmsisDspLib</name>\r
+          <state>0</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>ICCARM</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>28</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>CCDefines</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>CCPreprocFile</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCPreprocComments</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCPreprocLine</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCListCFile</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCListCMnemonics</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCListCMessages</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCListAssFile</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCListAssSource</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCEnableRemarks</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCDiagSuppress</name>\r
+          <state>Pa082</state>\r
+        </option>\r
+        <option>\r
+          <name>CCDiagRemark</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>CCDiagWarning</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>CCDiagError</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>CCObjPrefix</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CCAllowList</name>\r
+          <version>1</version>\r
+          <state>1111111</state>\r
+        </option>\r
+        <option>\r
+          <name>CCDebugInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IEndianMode</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IProcessor</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IExtraOptionsCheck</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IExtraOptions</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>CCLangConformance</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCSignedPlainChar</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRequirePrototypes</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCMultibyteSupport</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCDiagWarnAreErr</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCCompilerRuntimeInfo</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IFpuProcessor</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>OutputFile</name>\r
+          <state>$FILE_BNAME$.o</state>\r
+        </option>\r
+        <option>\r
+          <name>CCLibConfigHeader</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>PreInclude</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>CompilerMisraOverride</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCIncludePath2</name>\r
+          <state>$PROJ_DIR$/Fujitu_source</state>\r
+          <state>$PROJ_DIR$</state>\r
+          <state>$PROJ_DIR$/../../Source/include</state>\r
+          <state>$PROJ_DIR$/../../Source/portable/IAR/ARM_CM3</state>\r
+          <state>$PROJ_DIR$/../common/include</state>\r
+        </option>\r
+        <option>\r
+          <name>CCStdIncCheck</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCCodeSection</name>\r
+          <state>.text</state>\r
+        </option>\r
+        <option>\r
+          <name>IInterwork2</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IProcessorMode2</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CCOptLevel</name>\r
+          <state>3</state>\r
+        </option>\r
+        <option>\r
+          <name>CCOptStrategy</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCOptLevelSlave</name>\r
+          <state>3</state>\r
+        </option>\r
+        <option>\r
+          <name>CompilerMisraRules98</name>\r
+          <version>0</version>\r
+          <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>\r
+        </option>\r
+        <option>\r
+          <name>CompilerMisraRules04</name>\r
+          <version>0</version>\r
+          <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>\r
+        </option>\r
+        <option>\r
+          <name>CCPosIndRopi</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCPosIndRwpi</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCPosIndNoDynInit</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IccLang</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IccCDialect</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IccAllowVLA</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IccCppDialect</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IccExceptions</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IccRTTI</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IccStaticDestr</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IccCppInlineSemantics</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IccCmsis</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IccFloatSemantics</name>\r
+          <state>0</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>AARM</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>8</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>AObjPrefix</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>AEndian</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>ACaseSensitivity</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>MacroChars</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>AWarnEnable</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>AWarnWhat</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>AWarnOne</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>AWarnRange1</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>AWarnRange2</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>ADebug</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>AltRegisterNames</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>ADefines</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>AList</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>AListHeader</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>AListing</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>Includes</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>MacDefs</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>MacExps</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>MacExec</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OnlyAssed</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>MultiLine</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>PageLengthCheck</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>PageLength</name>\r
+          <state>80</state>\r
+        </option>\r
+        <option>\r
+          <name>TabSpacing</name>\r
+          <state>8</state>\r
+        </option>\r
+        <option>\r
+          <name>AXRef</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>AXRefDefines</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>AXRefInternal</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>AXRefDual</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>AProcessor</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>AFpuProcessor</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>AOutputFile</name>\r
+          <state>$FILE_BNAME$.o</state>\r
+        </option>\r
+        <option>\r
+          <name>AMultibyteSupport</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>ALimitErrorsCheck</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>ALimitErrorsEdit</name>\r
+          <state>100</state>\r
+        </option>\r
+        <option>\r
+          <name>AIgnoreStdInclude</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>AUserIncludes</name>\r
+          <state>$PROJ_DIR$</state>\r
+        </option>\r
+        <option>\r
+          <name>AExtraOptionsCheckV2</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>AExtraOptionsV2</name>\r
+          <state></state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>OBJCOPY</name>\r
+      <archiveVersion>0</archiveVersion>\r
+      <data>\r
+        <version>1</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>OOCOutputFormat</name>\r
+          <version>2</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCOutputOverride</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OOCOutputFile</name>\r
+          <state>RTOSDemo_IAR.srec</state>\r
+        </option>\r
+        <option>\r
+          <name>OOCCommandLineProducer</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>OOCObjCopyEnable</name>\r
+          <state>0</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>CUSTOM</name>\r
+      <archiveVersion>3</archiveVersion>\r
+      <data>\r
+        <extensions></extensions>\r
+        <cmdline></cmdline>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>BICOMP</name>\r
+      <archiveVersion>0</archiveVersion>\r
+      <data/>\r
+    </settings>\r
+    <settings>\r
+      <name>BUILDACTION</name>\r
+      <archiveVersion>1</archiveVersion>\r
+      <data>\r
+        <prebuild></prebuild>\r
+        <postbuild></postbuild>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>ILINK</name>\r
+      <archiveVersion>0</archiveVersion>\r
+      <data>\r
+        <version>13</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>IlinkLibIOConfig</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>XLinkMisraHandler</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkInputFileSlave</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkOutputFile</name>\r
+          <state>RTOSDemo_IAR.out</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkDebugInfoEnable</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkKeepSymbols</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkRawBinaryFile</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkRawBinarySymbol</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkRawBinarySegment</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkRawBinaryAlign</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkDefines</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkConfigDefines</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkMapFile</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkLogFile</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkLogInitialization</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkLogModule</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkLogSection</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkLogVeneer</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkIcfOverride</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkIcfFile</name>\r
+          <state>$PROJ_DIR$\config\mb9af314.icf</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkIcfFileSlave</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkEnableRemarks</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkSuppressDiags</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkTreatAsRem</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkTreatAsWarn</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkTreatAsErr</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkWarningsAreErrors</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkUseExtraOptions</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkExtraOptions</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkLowLevelInterfaceSlave</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkAutoLibEnable</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkAdditionalLibs</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkOverrideProgramEntryLabel</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkProgramEntryLabelSelect</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkProgramEntryLabel</name>\r
+          <state>__iar_program_start</state>\r
+        </option>\r
+        <option>\r
+          <name>DoFill</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>FillerByte</name>\r
+          <state>0xFF</state>\r
+        </option>\r
+        <option>\r
+          <name>FillerStart</name>\r
+          <state>0x0</state>\r
+        </option>\r
+        <option>\r
+          <name>FillerEnd</name>\r
+          <state>0x0</state>\r
+        </option>\r
+        <option>\r
+          <name>CrcSize</name>\r
+          <version>0</version>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CrcAlign</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CrcAlgo</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CrcPoly</name>\r
+          <state>0x11021</state>\r
+        </option>\r
+        <option>\r
+          <name>CrcCompl</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CrcBitOrder</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CrcInitialValue</name>\r
+          <state>0x0</state>\r
+        </option>\r
+        <option>\r
+          <name>DoCrc</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkBE8Slave</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkBufferedTerminalOutput</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkStdoutInterfaceSlave</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CrcFullSize</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkIElfToolPostProcess</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkLogAutoLibSelect</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkLogRedirSymbols</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkLogUnusedFragments</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkCrcReverseByteOrder</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkCrcUseAsInput</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkOptInline</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkOptExceptionsAllow</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkOptExceptionsForce</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkCmsis</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkOptMergeDuplSections</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkOptUseVfe</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkOptForceVfe</name>\r
+          <state>0</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>IARCHIVE</name>\r
+      <archiveVersion>0</archiveVersion>\r
+      <data>\r
+        <version>0</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>IarchiveInputs</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>IarchiveOverride</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IarchiveOutput</name>\r
+          <state>###Unitialized###</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>BILINK</name>\r
+      <archiveVersion>0</archiveVersion>\r
+      <data/>\r
+    </settings>\r
+  </configuration>\r
+  <group>\r
+    <name>Common_Demo_Source</name>\r
+    <excluded>\r
+      <configuration>Blinky</configuration>\r
+    </excluded>\r
+    <file>\r
+      <name>$PROJ_DIR$\..\Common\Minimal\BlockQ.c</name>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\..\Common\Minimal\blocktim.c</name>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\..\Common\Minimal\comtest.c</name>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\..\Common\Minimal\countsem.c</name>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\..\Common\Minimal\death.c</name>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\..\Common\Minimal\dynamic.c</name>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\..\Common\Minimal\flash.c</name>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\..\Common\Minimal\GenQTest.c</name>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\..\Common\Minimal\PollQ.c</name>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\..\Common\Minimal\QPeek.c</name>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\..\Common\Minimal\recmutex.c</name>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\..\Common\Minimal\semtest.c</name>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\..\Common\Minimal\TimerDemo.c</name>\r
+    </file>\r
+  </group>\r
+  <group>\r
+    <name>FreeRTOS_Source</name>\r
+    <group>\r
+      <name>Portable</name>\r
+      <file>\r
+        <name>$PROJ_DIR$\..\..\Source\portable\MemMang\heap_2.c</name>\r
+      </file>\r
+      <file>\r
+        <name>$PROJ_DIR$\..\..\Source\portable\IAR\ARM_CM3\port.c</name>\r
+      </file>\r
+      <file>\r
+        <name>$PROJ_DIR$\..\..\Source\portable\IAR\ARM_CM3\portasm.s</name>\r
+      </file>\r
+    </group>\r
+    <file>\r
+      <name>$PROJ_DIR$\..\..\Source\list.c</name>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\..\..\Source\queue.c</name>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\..\..\Source\tasks.c</name>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\..\..\Source\timers.c</name>\r
+    </file>\r
+  </group>\r
+  <group>\r
+    <name>Fujitsu_Source</name>\r
+    <file>\r
+      <name>$PROJ_DIR$\Fujitu_source\core_cm3.c</name>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\Fujitu_source\startup_iar\startup_mb9af31x.s</name>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\Fujitu_source\system_mb9af31x.c</name>\r
+    </file>\r
+  </group>\r
+  <file>\r
+    <name>$PROJ_DIR$\main-full.c</name>\r
+    <excluded>\r
+      <configuration>Blinky</configuration>\r
+    </excluded>\r
+  </file>\r
+  <file>\r
+    <name>$PROJ_DIR$\main_blinky.c</name>\r
+    <excluded>\r
+      <configuration>Full</configuration>\r
+      <configuration>Full_with_optimisation</configuration>\r
+    </excluded>\r
+  </file>\r
+  <file>\r
+    <name>$PROJ_DIR$\ParTest.c</name>\r
+    <excluded>\r
+      <configuration>Blinky</configuration>\r
+    </excluded>\r
+  </file>\r
+  <file>\r
+    <name>$PROJ_DIR$\serial.c</name>\r
+    <excluded>\r
+      <configuration>Blinky</configuration>\r
+    </excluded>\r
+  </file>\r
+</project>\r
+\r
+\r

diff --git a/Demo/CORTEX_MB9A310_IAR_Keil/RTOSDemo_IAR.eww b/Demo/CORTEX_MB9A310_IAR_Keil/RTOSDemo_IAR.eww
new file mode 100644 (file)
index 0000000..f4971a4
--- /dev/null
+++ b/Demo/CORTEX_MB9A310_IAR_Keil/RTOSDemo_IAR.eww
@@ -0,0 +1,10 @@
+<?xml version="1.0" encoding="iso-8859-1"?>\r
+\r
+<workspace>\r
+  <project>\r
+    <path>$WS_DIR$\RTOSDemo_IAR.ewp</path>\r
+  </project>\r
+  <batchBuild/>\r
+</workspace>\r
+\r
+\r

diff --git a/Demo/CORTEX_MB9A310_IAR_Keil/RTOSDemo_Keil.uvopt b/Demo/CORTEX_MB9A310_IAR_Keil/RTOSDemo_Keil.uvopt
new file mode 100644 (file)
index 0000000..fc3f484
--- /dev/null
+++ b/Demo/CORTEX_MB9A310_IAR_Keil/RTOSDemo_Keil.uvopt
@@ -0,0 +1,1011 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_opt.xsd">
+
+  <SchemaVersion>1.0</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Extensions>
+    <cExt>*.c</cExt>
+    <aExt>*.s*; *.src; *.a*</aExt>
+    <oExt>*.obj</oExt>
+    <lExt>*.lib</lExt>
+    <tExt>*.txt; *.h; *.inc</tExt>
+    <pExt>*.plm</pExt>
+    <CppX>*.cpp</CppX>
+  </Extensions>
+
+  <DaveTm>
+    <dwLowDateTime>0</dwLowDateTime>
+    <dwHighDateTime>0</dwHighDateTime>
+  </DaveTm>
+
+  <Target>
+    <TargetName>Blinky</TargetName>
+    <ToolsetNumber>0x4</ToolsetNumber>
+    <ToolsetName>ARM-ADS</ToolsetName>
+    <TargetOption>
+      <CLKADS>4000000</CLKADS>
+      <OPTTT>
+        <gFlags>1</gFlags>
+        <BeepAtEnd>1</BeepAtEnd>
+        <RunSim>1</RunSim>
+        <RunTarget>0</RunTarget>
+      </OPTTT>
+      <OPTHX>
+        <HexSelection>1</HexSelection>
+        <FlashByte>65535</FlashByte>
+        <HexRangeLowAddress>0</HexRangeLowAddress>
+        <HexRangeHighAddress>0</HexRangeHighAddress>
+        <HexOffset>0</HexOffset>
+      </OPTHX>
+      <OPTLEX>
+        <PageWidth>79</PageWidth>
+        <PageLength>66</PageLength>
+        <TabStop>8</TabStop>
+        <ListingPath>.\</ListingPath>
+      </OPTLEX>
+      <ListingPage>
+        <CreateCListing>1</CreateCListing>
+        <CreateAListing>1</CreateAListing>
+        <CreateLListing>1</CreateLListing>
+        <CreateIListing>0</CreateIListing>
+        <AsmCond>1</AsmCond>
+        <AsmSymb>1</AsmSymb>
+        <AsmXref>0</AsmXref>
+        <CCond>1</CCond>
+        <CCode>0</CCode>
+        <CListInc>0</CListInc>
+        <CSymb>0</CSymb>
+        <LinkerCodeListing>0</LinkerCodeListing>
+      </ListingPage>
+      <OPTXL>
+        <LMap>1</LMap>
+        <LComments>1</LComments>
+        <LGenerateSymbols>1</LGenerateSymbols>
+        <LLibSym>1</LLibSym>
+        <LLines>1</LLines>
+        <LLocSym>1</LLocSym>
+        <LPubSym>1</LPubSym>
+        <LXref>0</LXref>
+        <LExpSel>0</LExpSel>
+      </OPTXL>
+      <OPTFL>
+        <tvExp>1</tvExp>
+        <tvExpOptDlg>0</tvExpOptDlg>
+        <IsCurrentTarget>0</IsCurrentTarget>
+      </OPTFL>
+      <CpuCode>255</CpuCode>
+      <Books>
+        <Book>
+          <Number>0</Number>
+          <Title>Data Sheet</Title>
+          <Path>DATASHTS\FUJITSU\MB9BF500NR-DS.pdf</Path>
+        </Book>
+        <Book>
+          <Number>1</Number>
+          <Title>User Manual</Title>
+          <Path>DATASHTS\FUJITSU\MB9Bxxx-MN.pdf</Path>
+        </Book>
+      </Books>
+      <DllOpt>
+        <SimDllName>SARMCM3.DLL</SimDllName>
+        <SimDllArguments>-MPU</SimDllArguments>
+        <SimDlgDllName>DCM.DLL</SimDlgDllName>
+        <SimDlgDllArguments>-pCM3</SimDlgDllArguments>
+        <TargetDllName>SARMCM3.DLL</TargetDllName>
+        <TargetDllArguments>-MPU</TargetDllArguments>
+        <TargetDlgDllName>TCM.DLL</TargetDlgDllName>
+        <TargetDlgDllArguments>-pCM3</TargetDlgDllArguments>
+      </DllOpt>
+      <DebugOpt>
+        <uSim>0</uSim>
+        <uTrg>1</uTrg>
+        <sLdApp>1</sLdApp>
+        <sGomain>1</sGomain>
+        <sRbreak>1</sRbreak>
+        <sRwatch>1</sRwatch>
+        <sRmem>1</sRmem>
+        <sRfunc>1</sRfunc>
+        <sRbox>1</sRbox>
+        <tLdApp>1</tLdApp>
+        <tGomain>1</tGomain>
+        <tRbreak>1</tRbreak>
+        <tRwatch>1</tRwatch>
+        <tRmem>1</tRmem>
+        <tRfunc>0</tRfunc>
+        <tRbox>1</tRbox>
+        <sRunDeb>0</sRunDeb>
+        <sLrtime>0</sLrtime>
+        <nTsel>1</nTsel>
+        <sDll></sDll>
+        <sDllPa></sDllPa>
+        <sDlgDll></sDlgDll>
+        <sDlgPa></sDlgPa>
+        <sIfile></sIfile>
+        <tDll></tDll>
+        <tDllPa></tDllPa>
+        <tDlgDll></tDlgDll>
+        <tDlgPa></tDlgPa>
+        <tIfile></tIfile>
+        <pMon>BIN\UL2CM3.DLL</pMon>
+      </DebugOpt>
+      <TargetDriverDllRegistry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>DLGTARM</Key>
+          <Name>(1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>ARMDBGFLAGS</Key>
+          <Name></Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>DLGUARM</Key>
+          <Name>(105=-1,-1,-1,-1,0)(106=-1,-1,-1,-1,0)(107=-1,-1,-1,-1,0)</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>UL2CM3</Key>
+          <Name>-UM1129BUE -O207 -S0 -C0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC800 -FN1 -FF0MB9BFx06_512 -FS00 -FL080000</Name>
+        </SetRegEntry>
+      </TargetDriverDllRegistry>
+      <MemoryWindow1>
+        <Mm>
+          <WinNumber>1</WinNumber>
+          <SubType>0</SubType>
+          <ItemText>0</ItemText>
+        </Mm>
+      </MemoryWindow1>
+      <MemoryWindow2>
+        <Mm>
+          <WinNumber>2</WinNumber>
+          <SubType>0</SubType>
+          <ItemText>0</ItemText>
+        </Mm>
+      </MemoryWindow2>
+      <MemoryWindow3>
+        <Mm>
+          <WinNumber>3</WinNumber>
+          <SubType>0</SubType>
+          <ItemText>0xaa8</ItemText>
+        </Mm>
+      </MemoryWindow3>
+      <MemoryWindow4>
+        <Mm>
+          <WinNumber>4</WinNumber>
+          <SubType>0</SubType>
+          <ItemText>0x40000000</ItemText>
+        </Mm>
+      </MemoryWindow4>
+      <DebugFlag>
+        <trace>0</trace>
+        <periodic>1</periodic>
+        <aLwin>1</aLwin>
+        <aCover>0</aCover>
+        <aSer1>0</aSer1>
+        <aSer2>0</aSer2>
+        <aPa>0</aPa>
+        <viewmode>1</viewmode>
+        <vrSel>0</vrSel>
+        <aSym>0</aSym>
+        <aTbox>0</aTbox>
+        <AscS1>0</AscS1>
+        <AscS2>0</AscS2>
+        <AscS3>0</AscS3>
+        <aSer3>0</aSer3>
+        <eProf>0</eProf>
+        <aLa>0</aLa>
+        <aPa1>0</aPa1>
+        <AscS4>0</AscS4>
+        <aSer4>0</aSer4>
+        <StkLoc>0</StkLoc>
+        <TrcWin>0</TrcWin>
+        <newCpu>0</newCpu>
+        <uProt>0</uProt>
+      </DebugFlag>
+      <LintExecutable></LintExecutable>
+      <LintConfigFile></LintConfigFile>
+    </TargetOption>
+  </Target>
+
+  <Target>
+    <TargetName>Full</TargetName>
+    <ToolsetNumber>0x4</ToolsetNumber>
+    <ToolsetName>ARM-ADS</ToolsetName>
+    <TargetOption>
+      <CLKADS>4000000</CLKADS>
+      <OPTTT>
+        <gFlags>1</gFlags>
+        <BeepAtEnd>1</BeepAtEnd>
+        <RunSim>1</RunSim>
+        <RunTarget>0</RunTarget>
+      </OPTTT>
+      <OPTHX>
+        <HexSelection>1</HexSelection>
+        <FlashByte>65535</FlashByte>
+        <HexRangeLowAddress>0</HexRangeLowAddress>
+        <HexRangeHighAddress>0</HexRangeHighAddress>
+        <HexOffset>0</HexOffset>
+      </OPTHX>
+      <OPTLEX>
+        <PageWidth>79</PageWidth>
+        <PageLength>66</PageLength>
+        <TabStop>8</TabStop>
+        <ListingPath>.\</ListingPath>
+      </OPTLEX>
+      <ListingPage>
+        <CreateCListing>1</CreateCListing>
+        <CreateAListing>1</CreateAListing>
+        <CreateLListing>1</CreateLListing>
+        <CreateIListing>0</CreateIListing>
+        <AsmCond>1</AsmCond>
+        <AsmSymb>1</AsmSymb>
+        <AsmXref>0</AsmXref>
+        <CCond>1</CCond>
+        <CCode>0</CCode>
+        <CListInc>0</CListInc>
+        <CSymb>0</CSymb>
+        <LinkerCodeListing>0</LinkerCodeListing>
+      </ListingPage>
+      <OPTXL>
+        <LMap>1</LMap>
+        <LComments>1</LComments>
+        <LGenerateSymbols>1</LGenerateSymbols>
+        <LLibSym>1</LLibSym>
+        <LLines>1</LLines>
+        <LLocSym>1</LLocSym>
+        <LPubSym>1</LPubSym>
+        <LXref>0</LXref>
+        <LExpSel>0</LExpSel>
+      </OPTXL>
+      <OPTFL>
+        <tvExp>1</tvExp>
+        <tvExpOptDlg>0</tvExpOptDlg>
+        <IsCurrentTarget>1</IsCurrentTarget>
+      </OPTFL>
+      <CpuCode>255</CpuCode>
+      <Books>
+        <Book>
+          <Number>0</Number>
+          <Title>Data Sheet</Title>
+          <Path>DATASHTS\FUJITSU\MB9BF500NR-DS.pdf</Path>
+        </Book>
+        <Book>
+          <Number>1</Number>
+          <Title>User Manual</Title>
+          <Path>DATASHTS\FUJITSU\MB9Bxxx-MN.pdf</Path>
+        </Book>
+      </Books>
+      <DllOpt>
+        <SimDllName>SARMCM3.DLL</SimDllName>
+        <SimDllArguments>-MPU</SimDllArguments>
+        <SimDlgDllName>DCM.DLL</SimDlgDllName>
+        <SimDlgDllArguments>-pCM3</SimDlgDllArguments>
+        <TargetDllName>SARMCM3.DLL</TargetDllName>
+        <TargetDllArguments>-MPU</TargetDllArguments>
+        <TargetDlgDllName>TCM.DLL</TargetDlgDllName>
+        <TargetDlgDllArguments>-pCM3</TargetDlgDllArguments>
+      </DllOpt>
+      <DebugOpt>
+        <uSim>0</uSim>
+        <uTrg>1</uTrg>
+        <sLdApp>1</sLdApp>
+        <sGomain>1</sGomain>
+        <sRbreak>1</sRbreak>
+        <sRwatch>1</sRwatch>
+        <sRmem>1</sRmem>
+        <sRfunc>1</sRfunc>
+        <sRbox>1</sRbox>
+        <tLdApp>1</tLdApp>
+        <tGomain>1</tGomain>
+        <tRbreak>1</tRbreak>
+        <tRwatch>1</tRwatch>
+        <tRmem>1</tRmem>
+        <tRfunc>0</tRfunc>
+        <tRbox>1</tRbox>
+        <sRunDeb>0</sRunDeb>
+        <sLrtime>0</sLrtime>
+        <nTsel>1</nTsel>
+        <sDll></sDll>
+        <sDllPa></sDllPa>
+        <sDlgDll></sDlgDll>
+        <sDlgPa></sDlgPa>
+        <sIfile></sIfile>
+        <tDll></tDll>
+        <tDllPa></tDllPa>
+        <tDlgDll></tDlgDll>
+        <tDlgPa></tDlgPa>
+        <tIfile></tIfile>
+        <pMon>BIN\UL2CM3.DLL</pMon>
+      </DebugOpt>
+      <TargetDriverDllRegistry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>DLGTARM</Key>
+          <Name>(1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>ARMDBGFLAGS</Key>
+          <Name></Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>DLGUARM</Key>
+          <Name>(105=-1,-1,-1,-1,0)(106=-1,-1,-1,-1,0)(107=-1,-1,-1,-1,0)</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>UL2CM3</Key>
+          <Name>-UM1129BUE -O207 -S0 -C0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC800 -FN1 -FF0MB9BFx06_512 -FS00 -FL080000</Name>
+        </SetRegEntry>
+      </TargetDriverDllRegistry>
+      <MemoryWindow1>
+        <Mm>
+          <WinNumber>1</WinNumber>
+          <SubType>0</SubType>
+          <ItemText>0</ItemText>
+        </Mm>
+      </MemoryWindow1>
+      <MemoryWindow2>
+        <Mm>
+          <WinNumber>2</WinNumber>
+          <SubType>0</SubType>
+          <ItemText>0</ItemText>
+        </Mm>
+      </MemoryWindow2>
+      <MemoryWindow3>
+        <Mm>
+          <WinNumber>3</WinNumber>
+          <SubType>0</SubType>
+          <ItemText>0xaa8</ItemText>
+        </Mm>
+      </MemoryWindow3>
+      <MemoryWindow4>
+        <Mm>
+          <WinNumber>4</WinNumber>
+          <SubType>0</SubType>
+          <ItemText>0x40000000</ItemText>
+        </Mm>
+      </MemoryWindow4>
+      <DebugFlag>
+        <trace>0</trace>
+        <periodic>1</periodic>
+        <aLwin>1</aLwin>
+        <aCover>0</aCover>
+        <aSer1>0</aSer1>
+        <aSer2>0</aSer2>
+        <aPa>0</aPa>
+        <viewmode>1</viewmode>
+        <vrSel>0</vrSel>
+        <aSym>0</aSym>
+        <aTbox>0</aTbox>
+        <AscS1>0</AscS1>
+        <AscS2>0</AscS2>
+        <AscS3>0</AscS3>
+        <aSer3>0</aSer3>
+        <eProf>0</eProf>
+        <aLa>0</aLa>
+        <aPa1>0</aPa1>
+        <AscS4>0</AscS4>
+        <aSer4>0</aSer4>
+        <StkLoc>0</StkLoc>
+        <TrcWin>0</TrcWin>
+        <newCpu>0</newCpu>
+        <uProt>0</uProt>
+      </DebugFlag>
+      <LintExecutable></LintExecutable>
+      <LintConfigFile></LintConfigFile>
+    </TargetOption>
+  </Target>
+
+  <Target>
+    <TargetName>Full_with_optimisation</TargetName>
+    <ToolsetNumber>0x4</ToolsetNumber>
+    <ToolsetName>ARM-ADS</ToolsetName>
+    <TargetOption>
+      <CLKADS>4000000</CLKADS>
+      <OPTTT>
+        <gFlags>1</gFlags>
+        <BeepAtEnd>1</BeepAtEnd>
+        <RunSim>1</RunSim>
+        <RunTarget>0</RunTarget>
+      </OPTTT>
+      <OPTHX>
+        <HexSelection>1</HexSelection>
+        <FlashByte>65535</FlashByte>
+        <HexRangeLowAddress>0</HexRangeLowAddress>
+        <HexRangeHighAddress>0</HexRangeHighAddress>
+        <HexOffset>0</HexOffset>
+      </OPTHX>
+      <OPTLEX>
+        <PageWidth>79</PageWidth>
+        <PageLength>66</PageLength>
+        <TabStop>8</TabStop>
+        <ListingPath>.\</ListingPath>
+      </OPTLEX>
+      <ListingPage>
+        <CreateCListing>1</CreateCListing>
+        <CreateAListing>1</CreateAListing>
+        <CreateLListing>1</CreateLListing>
+        <CreateIListing>0</CreateIListing>
+        <AsmCond>1</AsmCond>
+        <AsmSymb>1</AsmSymb>
+        <AsmXref>0</AsmXref>
+        <CCond>1</CCond>
+        <CCode>0</CCode>
+        <CListInc>0</CListInc>
+        <CSymb>0</CSymb>
+        <LinkerCodeListing>0</LinkerCodeListing>
+      </ListingPage>
+      <OPTXL>
+        <LMap>1</LMap>
+        <LComments>1</LComments>
+        <LGenerateSymbols>1</LGenerateSymbols>
+        <LLibSym>1</LLibSym>
+        <LLines>1</LLines>
+        <LLocSym>1</LLocSym>
+        <LPubSym>1</LPubSym>
+        <LXref>0</LXref>
+        <LExpSel>0</LExpSel>
+      </OPTXL>
+      <OPTFL>
+        <tvExp>1</tvExp>
+        <tvExpOptDlg>0</tvExpOptDlg>
+        <IsCurrentTarget>0</IsCurrentTarget>
+      </OPTFL>
+      <CpuCode>255</CpuCode>
+      <Books>
+        <Book>
+          <Number>0</Number>
+          <Title>Data Sheet</Title>
+          <Path>DATASHTS\FUJITSU\MB9BF500NR-DS.pdf</Path>
+        </Book>
+        <Book>
+          <Number>1</Number>
+          <Title>User Manual</Title>
+          <Path>DATASHTS\FUJITSU\MB9Bxxx-MN.pdf</Path>
+        </Book>
+      </Books>
+      <DllOpt>
+        <SimDllName>SARMCM3.DLL</SimDllName>
+        <SimDllArguments>-MPU</SimDllArguments>
+        <SimDlgDllName>DCM.DLL</SimDlgDllName>
+        <SimDlgDllArguments>-pCM3</SimDlgDllArguments>
+        <TargetDllName>SARMCM3.DLL</TargetDllName>
+        <TargetDllArguments>-MPU</TargetDllArguments>
+        <TargetDlgDllName>TCM.DLL</TargetDlgDllName>
+        <TargetDlgDllArguments>-pCM3</TargetDlgDllArguments>
+      </DllOpt>
+      <DebugOpt>
+        <uSim>0</uSim>
+        <uTrg>1</uTrg>
+        <sLdApp>1</sLdApp>
+        <sGomain>1</sGomain>
+        <sRbreak>1</sRbreak>
+        <sRwatch>1</sRwatch>
+        <sRmem>1</sRmem>
+        <sRfunc>1</sRfunc>
+        <sRbox>1</sRbox>
+        <tLdApp>1</tLdApp>
+        <tGomain>1</tGomain>
+        <tRbreak>1</tRbreak>
+        <tRwatch>1</tRwatch>
+        <tRmem>1</tRmem>
+        <tRfunc>0</tRfunc>
+        <tRbox>1</tRbox>
+        <sRunDeb>0</sRunDeb>
+        <sLrtime>0</sLrtime>
+        <nTsel>1</nTsel>
+        <sDll></sDll>
+        <sDllPa></sDllPa>
+        <sDlgDll></sDlgDll>
+        <sDlgPa></sDlgPa>
+        <sIfile></sIfile>
+        <tDll></tDll>
+        <tDllPa></tDllPa>
+        <tDlgDll></tDlgDll>
+        <tDlgPa></tDlgPa>
+        <tIfile></tIfile>
+        <pMon>BIN\UL2CM3.DLL</pMon>
+      </DebugOpt>
+      <TargetDriverDllRegistry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>DLGTARM</Key>
+          <Name>(1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>ARMDBGFLAGS</Key>
+          <Name></Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>DLGUARM</Key>
+          <Name>(105=-1,-1,-1,-1,0)(106=-1,-1,-1,-1,0)(107=-1,-1,-1,-1,0)</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>UL2CM3</Key>
+          <Name>-UM1129BUE -O207 -S0 -C0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC800 -FN1 -FF0MB9BFx06_512 -FS00 -FL080000</Name>
+        </SetRegEntry>
+      </TargetDriverDllRegistry>
+      <MemoryWindow1>
+        <Mm>
+          <WinNumber>1</WinNumber>
+          <SubType>0</SubType>
+          <ItemText>0</ItemText>
+        </Mm>
+      </MemoryWindow1>
+      <MemoryWindow2>
+        <Mm>
+          <WinNumber>2</WinNumber>
+          <SubType>0</SubType>
+          <ItemText>0</ItemText>
+        </Mm>
+      </MemoryWindow2>
+      <MemoryWindow3>
+        <Mm>
+          <WinNumber>3</WinNumber>
+          <SubType>0</SubType>
+          <ItemText>0xaa8</ItemText>
+        </Mm>
+      </MemoryWindow3>
+      <MemoryWindow4>
+        <Mm>
+          <WinNumber>4</WinNumber>
+          <SubType>0</SubType>
+          <ItemText>0x40000000</ItemText>
+        </Mm>
+      </MemoryWindow4>
+      <DebugFlag>
+        <trace>0</trace>
+        <periodic>1</periodic>
+        <aLwin>1</aLwin>
+        <aCover>0</aCover>
+        <aSer1>0</aSer1>
+        <aSer2>0</aSer2>
+        <aPa>0</aPa>
+        <viewmode>1</viewmode>
+        <vrSel>0</vrSel>
+        <aSym>0</aSym>
+        <aTbox>0</aTbox>
+        <AscS1>0</AscS1>
+        <AscS2>0</AscS2>
+        <AscS3>0</AscS3>
+        <aSer3>0</aSer3>
+        <eProf>0</eProf>
+        <aLa>0</aLa>
+        <aPa1>0</aPa1>
+        <AscS4>0</AscS4>
+        <aSer4>0</aSer4>
+        <StkLoc>0</StkLoc>
+        <TrcWin>0</TrcWin>
+        <newCpu>0</newCpu>
+        <uProt>0</uProt>
+      </DebugFlag>
+      <LintExecutable></LintExecutable>
+      <LintConfigFile></LintConfigFile>
+    </TargetOption>
+  </Target>
+
+  <Group>
+    <GroupName>Fujitsu Source</GroupName>
+    <tvExp>0</tvExp>
+    <tvExpOptDlg>0</tvExpOptDlg>
+    <cbSel>0</cbSel>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>1</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <Focus>0</Focus>
+      <ColumnNumber>0</ColumnNumber>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <TopLine>0</TopLine>
+      <CurrentLine>0</CurrentLine>
+      <bDave2>0</bDave2>
+      <PathWithFileName>.\Fujitu_source\system_mb9bf50x.c</PathWithFileName>
+      <FilenameWithoutPath>system_mb9bf50x.c</FilenameWithoutPath>
+    </File>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>2</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <Focus>0</Focus>
+      <ColumnNumber>0</ColumnNumber>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <TopLine>0</TopLine>
+      <CurrentLine>0</CurrentLine>
+      <bDave2>0</bDave2>
+      <PathWithFileName>.\Fujitu_source\core_cm3.c</PathWithFileName>
+      <FilenameWithoutPath>core_cm3.c</FilenameWithoutPath>
+    </File>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>3</FileNumber>
+      <FileType>2</FileType>
+      <tvExp>0</tvExp>
+      <Focus>0</Focus>
+      <ColumnNumber>0</ColumnNumber>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <TopLine>0</TopLine>
+      <CurrentLine>0</CurrentLine>
+      <bDave2>0</bDave2>
+      <PathWithFileName>.\Fujitu_source\startup_keil\startup_mb9bf50x.s</PathWithFileName>
+      <FilenameWithoutPath>startup_mb9bf50x.s</FilenameWithoutPath>
+    </File>
+  </Group>
+
+  <Group>
+    <GroupName>Common_Demo_Source</GroupName>
+    <tvExp>0</tvExp>
+    <tvExpOptDlg>0</tvExpOptDlg>
+    <cbSel>0</cbSel>
+    <File>
+      <GroupNumber>2</GroupNumber>
+      <FileNumber>4</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <Focus>0</Focus>
+      <ColumnNumber>0</ColumnNumber>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <TopLine>0</TopLine>
+      <CurrentLine>0</CurrentLine>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\Common\Minimal\TimerDemo.c</PathWithFileName>
+      <FilenameWithoutPath>TimerDemo.c</FilenameWithoutPath>
+    </File>
+    <File>
+      <GroupNumber>2</GroupNumber>
+      <FileNumber>5</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <Focus>0</Focus>
+      <ColumnNumber>0</ColumnNumber>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <TopLine>0</TopLine>
+      <CurrentLine>0</CurrentLine>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\Common\Minimal\BlockQ.c</PathWithFileName>
+      <FilenameWithoutPath>BlockQ.c</FilenameWithoutPath>
+    </File>
+    <File>
+      <GroupNumber>2</GroupNumber>
+      <FileNumber>6</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <Focus>0</Focus>
+      <ColumnNumber>0</ColumnNumber>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <TopLine>0</TopLine>
+      <CurrentLine>0</CurrentLine>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\Common\Minimal\blocktim.c</PathWithFileName>
+      <FilenameWithoutPath>blocktim.c</FilenameWithoutPath>
+    </File>
+    <File>
+      <GroupNumber>2</GroupNumber>
+      <FileNumber>7</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <Focus>0</Focus>
+      <ColumnNumber>0</ColumnNumber>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <TopLine>0</TopLine>
+      <CurrentLine>0</CurrentLine>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\Common\Minimal\comtest.c</PathWithFileName>
+      <FilenameWithoutPath>comtest.c</FilenameWithoutPath>
+    </File>
+    <File>
+      <GroupNumber>2</GroupNumber>
+      <FileNumber>8</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <Focus>0</Focus>
+      <ColumnNumber>0</ColumnNumber>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <TopLine>0</TopLine>
+      <CurrentLine>0</CurrentLine>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\Common\Minimal\countsem.c</PathWithFileName>
+      <FilenameWithoutPath>countsem.c</FilenameWithoutPath>
+    </File>
+    <File>
+      <GroupNumber>2</GroupNumber>
+      <FileNumber>9</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <Focus>0</Focus>
+      <ColumnNumber>0</ColumnNumber>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <TopLine>0</TopLine>
+      <CurrentLine>0</CurrentLine>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\Common\Minimal\death.c</PathWithFileName>
+      <FilenameWithoutPath>death.c</FilenameWithoutPath>
+    </File>
+    <File>
+      <GroupNumber>2</GroupNumber>
+      <FileNumber>10</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <Focus>0</Focus>
+      <ColumnNumber>0</ColumnNumber>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <TopLine>360</TopLine>
+      <CurrentLine>369</CurrentLine>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\Common\Minimal\dynamic.c</PathWithFileName>
+      <FilenameWithoutPath>dynamic.c</FilenameWithoutPath>
+    </File>
+    <File>
+      <GroupNumber>2</GroupNumber>
+      <FileNumber>11</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <Focus>0</Focus>
+      <ColumnNumber>0</ColumnNumber>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <TopLine>0</TopLine>
+      <CurrentLine>0</CurrentLine>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\Common\Minimal\flash.c</PathWithFileName>
+      <FilenameWithoutPath>flash.c</FilenameWithoutPath>
+    </File>
+    <File>
+      <GroupNumber>2</GroupNumber>
+      <FileNumber>12</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <Focus>0</Focus>
+      <ColumnNumber>0</ColumnNumber>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <TopLine>285</TopLine>
+      <CurrentLine>294</CurrentLine>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\Common\Minimal\GenQTest.c</PathWithFileName>
+      <FilenameWithoutPath>GenQTest.c</FilenameWithoutPath>
+    </File>
+    <File>
+      <GroupNumber>2</GroupNumber>
+      <FileNumber>13</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <Focus>0</Focus>
+      <ColumnNumber>0</ColumnNumber>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <TopLine>0</TopLine>
+      <CurrentLine>0</CurrentLine>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\Common\Minimal\PollQ.c</PathWithFileName>
+      <FilenameWithoutPath>PollQ.c</FilenameWithoutPath>
+    </File>
+    <File>
+      <GroupNumber>2</GroupNumber>
+      <FileNumber>14</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <Focus>0</Focus>
+      <ColumnNumber>0</ColumnNumber>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <TopLine>0</TopLine>
+      <CurrentLine>0</CurrentLine>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\Common\Minimal\QPeek.c</PathWithFileName>
+      <FilenameWithoutPath>QPeek.c</FilenameWithoutPath>
+    </File>
+    <File>
+      <GroupNumber>2</GroupNumber>
+      <FileNumber>15</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <Focus>0</Focus>
+      <ColumnNumber>0</ColumnNumber>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <TopLine>0</TopLine>
+      <CurrentLine>0</CurrentLine>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\Common\Minimal\recmutex.c</PathWithFileName>
+      <FilenameWithoutPath>recmutex.c</FilenameWithoutPath>
+    </File>
+    <File>
+      <GroupNumber>2</GroupNumber>
+      <FileNumber>16</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <Focus>0</Focus>
+      <ColumnNumber>0</ColumnNumber>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <TopLine>0</TopLine>
+      <CurrentLine>0</CurrentLine>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\Common\Minimal\semtest.c</PathWithFileName>
+      <FilenameWithoutPath>semtest.c</FilenameWithoutPath>
+    </File>
+  </Group>
+
+  <Group>
+    <GroupName>FreeRTOS_Source</GroupName>
+    <tvExp>0</tvExp>
+    <tvExpOptDlg>0</tvExpOptDlg>
+    <cbSel>0</cbSel>
+    <File>
+      <GroupNumber>3</GroupNumber>
+      <FileNumber>17</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <Focus>0</Focus>
+      <ColumnNumber>0</ColumnNumber>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <TopLine>0</TopLine>
+      <CurrentLine>0</CurrentLine>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\Source\timers.c</PathWithFileName>
+      <FilenameWithoutPath>timers.c</FilenameWithoutPath>
+    </File>
+    <File>
+      <GroupNumber>3</GroupNumber>
+      <FileNumber>18</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <Focus>0</Focus>
+      <ColumnNumber>0</ColumnNumber>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <TopLine>0</TopLine>
+      <CurrentLine>0</CurrentLine>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\Source\list.c</PathWithFileName>
+      <FilenameWithoutPath>list.c</FilenameWithoutPath>
+    </File>
+    <File>
+      <GroupNumber>3</GroupNumber>
+      <FileNumber>19</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <Focus>0</Focus>
+      <ColumnNumber>0</ColumnNumber>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <TopLine>0</TopLine>
+      <CurrentLine>0</CurrentLine>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\Source\queue.c</PathWithFileName>
+      <FilenameWithoutPath>queue.c</FilenameWithoutPath>
+    </File>
+    <File>
+      <GroupNumber>3</GroupNumber>
+      <FileNumber>20</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <Focus>0</Focus>
+      <ColumnNumber>0</ColumnNumber>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <TopLine>1975</TopLine>
+      <CurrentLine>1984</CurrentLine>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\Source\tasks.c</PathWithFileName>
+      <FilenameWithoutPath>tasks.c</FilenameWithoutPath>
+    </File>
+    <File>
+      <GroupNumber>3</GroupNumber>
+      <FileNumber>21</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <Focus>0</Focus>
+      <ColumnNumber>0</ColumnNumber>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <TopLine>191</TopLine>
+      <CurrentLine>200</CurrentLine>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\Source\portable\RVDS\ARM_CM3\port.c</PathWithFileName>
+      <FilenameWithoutPath>port.c</FilenameWithoutPath>
+    </File>
+    <File>
+      <GroupNumber>3</GroupNumber>
+      <FileNumber>22</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <Focus>0</Focus>
+      <ColumnNumber>0</ColumnNumber>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <TopLine>0</TopLine>
+      <CurrentLine>0</CurrentLine>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\Source\portable\MemMang\heap_2.c</PathWithFileName>
+      <FilenameWithoutPath>heap_2.c</FilenameWithoutPath>
+    </File>
+  </Group>
+
+  <Group>
+    <GroupName>Demo_Source</GroupName>
+    <tvExp>0</tvExp>
+    <tvExpOptDlg>0</tvExpOptDlg>
+    <cbSel>0</cbSel>
+    <File>
+      <GroupNumber>4</GroupNumber>
+      <FileNumber>23</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <Focus>0</Focus>
+      <ColumnNumber>9</ColumnNumber>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <TopLine>36</TopLine>
+      <CurrentLine>62</CurrentLine>
+      <bDave2>0</bDave2>
+      <PathWithFileName>.\serial.c</PathWithFileName>
+      <FilenameWithoutPath>serial.c</FilenameWithoutPath>
+    </File>
+    <File>
+      <GroupNumber>4</GroupNumber>
+      <FileNumber>24</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <Focus>0</Focus>
+      <ColumnNumber>0</ColumnNumber>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <TopLine>58</TopLine>
+      <CurrentLine>58</CurrentLine>
+      <bDave2>0</bDave2>
+      <PathWithFileName>.\main_blinky.c</PathWithFileName>
+      <FilenameWithoutPath>main_blinky.c</FilenameWithoutPath>
+    </File>
+    <File>
+      <GroupNumber>4</GroupNumber>
+      <FileNumber>25</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <Focus>0</Focus>
+      <ColumnNumber>19</ColumnNumber>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <TopLine>56</TopLine>
+      <CurrentLine>56</CurrentLine>
+      <bDave2>0</bDave2>
+      <PathWithFileName>.\main-full.c</PathWithFileName>
+      <FilenameWithoutPath>main-full.c</FilenameWithoutPath>
+    </File>
+    <File>
+      <GroupNumber>4</GroupNumber>
+      <FileNumber>26</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <Focus>0</Focus>
+      <ColumnNumber>0</ColumnNumber>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <TopLine>0</TopLine>
+      <CurrentLine>0</CurrentLine>
+      <bDave2>0</bDave2>
+      <PathWithFileName>.\ParTest.c</PathWithFileName>
+      <FilenameWithoutPath>ParTest.c</FilenameWithoutPath>
+    </File>
+  </Group>
+
+  <MDIGroups>
+    <Orientation>1</Orientation>
+    <ActiveMDIGroup>0</ActiveMDIGroup>
+    <MDIGroup>
+      <Size>100</Size>
+      <ActiveTab>0</ActiveTab>
+      <Documents>
+        <Doc>
+          <Name>.\main_blinky.c</Name>
+          <ColumnNumber>0</ColumnNumber>
+          <TopLine>58</TopLine>
+          <CurrentLine>58</CurrentLine>
+        </Doc>
+        <Doc>
+          <Name>.\main-full.c</Name>
+          <ColumnNumber>19</ColumnNumber>
+          <TopLine>56</TopLine>
+          <CurrentLine>56</CurrentLine>
+        </Doc>
+      </Documents>
+    </MDIGroup>
+  </MDIGroups>
+
+</ProjectOpt>

diff --git a/Demo/CORTEX_MB9A310_IAR_Keil/RTOSDemo_Keil.uvproj b/Demo/CORTEX_MB9A310_IAR_Keil/RTOSDemo_Keil.uvproj
new file mode 100644 (file)
index 0000000..1df538c
--- /dev/null
+++ b/Demo/CORTEX_MB9A310_IAR_Keil/RTOSDemo_Keil.uvproj
@@ -0,0 +1,2189 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_proj.xsd">
+
+  <SchemaVersion>1.1</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Targets>
+    <Target>
+      <TargetName>Blinky</TargetName>
+      <ToolsetNumber>0x4</ToolsetNumber>
+      <ToolsetName>ARM-ADS</ToolsetName>
+      <TargetOption>
+        <TargetCommonOption>
+          <Device>MB9BF506N</Device>
+          <Vendor>Fujitsu Semiconductors</Vendor>
+          <Cpu>IRAM(0x20000000-0x20007FFF) IROM(0x00000000-0x0007FFFF) CLOCK(4000000) CPUTYPE("Cortex-M3")</Cpu>
+          <FlashUtilSpec></FlashUtilSpec>
+          <StartupFile>"Startup\Fujitsu\MB9B500\startup_MB9BF50x.s" ("Fujitsu MB9BF50x Startup Code")</StartupFile>
+          <FlashDriverDll>UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC800 -FN1 -FF0MB9BFx06_512 -FS00 -FL080000)</FlashDriverDll>
+          <DeviceId>5215</DeviceId>
+          <RegisterFile>MB9BF506N.h</RegisterFile>
+          <MemoryEnv></MemoryEnv>
+          <Cmp></Cmp>
+          <Asm></Asm>
+          <Linker></Linker>
+          <OHString></OHString>
+          <InfinionOptionDll></InfinionOptionDll>
+          <SLE66CMisc></SLE66CMisc>
+          <SLE66AMisc></SLE66AMisc>
+          <SLE66LinkerMisc></SLE66LinkerMisc>
+          <SFDFile></SFDFile>
+          <UseEnv>0</UseEnv>
+          <BinPath></BinPath>
+          <IncludePath></IncludePath>
+          <LibPath></LibPath>
+          <RegisterFilePath>Fujitsu\MB9B500\</RegisterFilePath>
+          <DBRegisterFilePath>Fujitsu\MB9B500\</DBRegisterFilePath>
+          <TargetStatus>
+            <Error>0</Error>
+            <ExitCodeStop>0</ExitCodeStop>
+            <ButtonStop>0</ButtonStop>
+            <NotGenerated>0</NotGenerated>
+            <InvalidFlash>1</InvalidFlash>
+          </TargetStatus>
+          <OutputDirectory>.\output\</OutputDirectory>
+          <OutputName>RTOSDemo_Keil</OutputName>
+          <CreateExecutable>1</CreateExecutable>
+          <CreateLib>0</CreateLib>
+          <CreateHexFile>0</CreateHexFile>
+          <DebugInformation>1</DebugInformation>
+          <BrowseInformation>1</BrowseInformation>
+          <ListingPath>.\</ListingPath>
+          <HexFormatSelection>1</HexFormatSelection>
+          <Merge32K>0</Merge32K>
+          <CreateBatchFile>0</CreateBatchFile>
+          <BeforeCompile>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+          </BeforeCompile>
+          <BeforeMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+          </BeforeMake>
+          <AfterMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+          </AfterMake>
+          <SelectedForBatchBuild>0</SelectedForBatchBuild>
+          <SVCSIdString></SVCSIdString>
+        </TargetCommonOption>
+        <CommonProperty>
+          <UseCPPCompiler>0</UseCPPCompiler>
+          <RVCTCodeConst>0</RVCTCodeConst>
+          <RVCTZI>0</RVCTZI>
+          <RVCTOtherData>0</RVCTOtherData>
+          <ModuleSelection>0</ModuleSelection>
+          <IncludeInBuild>1</IncludeInBuild>
+          <AlwaysBuild>0</AlwaysBuild>
+          <GenerateAssemblyFile>0</GenerateAssemblyFile>
+          <AssembleAssemblyFile>0</AssembleAssemblyFile>
+          <PublicsOnly>0</PublicsOnly>
+          <StopOnExitCode>3</StopOnExitCode>
+          <CustomArgument></CustomArgument>
+          <IncludeLibraryModules></IncludeLibraryModules>
+        </CommonProperty>
+        <DllOption>
+          <SimDllName>SARMCM3.DLL</SimDllName>
+          <SimDllArguments>-MPU</SimDllArguments>
+          <SimDlgDll>DCM.DLL</SimDlgDll>
+          <SimDlgDllArguments>-pCM3</SimDlgDllArguments>
+          <TargetDllName>SARMCM3.DLL</TargetDllName>
+          <TargetDllArguments>-MPU</TargetDllArguments>
+          <TargetDlgDll>TCM.DLL</TargetDlgDll>
+          <TargetDlgDllArguments>-pCM3</TargetDlgDllArguments>
+        </DllOption>
+        <DebugOption>
+          <OPTHX>
+            <HexSelection>1</HexSelection>
+            <HexRangeLowAddress>0</HexRangeLowAddress>
+            <HexRangeHighAddress>0</HexRangeHighAddress>
+            <HexOffset>0</HexOffset>
+            <Oh166RecLen>16</Oh166RecLen>
+          </OPTHX>
+          <Simulator>
+            <UseSimulator>0</UseSimulator>
+            <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+            <RunToMain>1</RunToMain>
+            <RestoreBreakpoints>1</RestoreBreakpoints>
+            <RestoreWatchpoints>1</RestoreWatchpoints>
+            <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+            <RestoreFunctions>1</RestoreFunctions>
+            <RestoreToolbox>1</RestoreToolbox>
+            <LimitSpeedToRealTime>0</LimitSpeedToRealTime>
+          </Simulator>
+          <Target>
+            <UseTarget>1</UseTarget>
+            <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+            <RunToMain>1</RunToMain>
+            <RestoreBreakpoints>1</RestoreBreakpoints>
+            <RestoreWatchpoints>1</RestoreWatchpoints>
+            <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+            <RestoreFunctions>0</RestoreFunctions>
+            <RestoreToolbox>1</RestoreToolbox>
+          </Target>
+          <RunDebugAfterBuild>0</RunDebugAfterBuild>
+          <TargetSelection>1</TargetSelection>
+          <SimDlls>
+            <CpuDll></CpuDll>
+            <CpuDllArguments></CpuDllArguments>
+            <PeripheralDll></PeripheralDll>
+            <PeripheralDllArguments></PeripheralDllArguments>
+            <InitializationFile></InitializationFile>
+          </SimDlls>
+          <TargetDlls>
+            <CpuDll></CpuDll>
+            <CpuDllArguments></CpuDllArguments>
+            <PeripheralDll></PeripheralDll>
+            <PeripheralDllArguments></PeripheralDllArguments>
+            <InitializationFile></InitializationFile>
+            <Driver>BIN\UL2CM3.DLL</Driver>
+          </TargetDlls>
+        </DebugOption>
+        <Utilities>
+          <Flash1>
+            <UseTargetDll>1</UseTargetDll>
+            <UseExternalTool>0</UseExternalTool>
+            <RunIndependent>0</RunIndependent>
+            <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
+            <Capability>1</Capability>
+            <DriverSelection>4096</DriverSelection>
+          </Flash1>
+          <Flash2>BIN\UL2CM3.DLL</Flash2>
+          <Flash3>"" ()</Flash3>
+          <Flash4></Flash4>
+        </Utilities>
+        <TargetArmAds>
+          <ArmAdsMisc>
+            <GenerateListings>0</GenerateListings>
+            <asHll>1</asHll>
+            <asAsm>1</asAsm>
+            <asMacX>1</asMacX>
+            <asSyms>1</asSyms>
+            <asFals>1</asFals>
+            <asDbgD>1</asDbgD>
+            <asForm>1</asForm>
+            <ldLst>0</ldLst>
+            <ldmm>1</ldmm>
+            <ldXref>1</ldXref>
+            <BigEnd>0</BigEnd>
+            <AdsALst>1</AdsALst>
+            <AdsACrf>1</AdsACrf>
+            <AdsANop>0</AdsANop>
+            <AdsANot>0</AdsANot>
+            <AdsLLst>1</AdsLLst>
+            <AdsLmap>1</AdsLmap>
+            <AdsLcgr>1</AdsLcgr>
+            <AdsLsym>1</AdsLsym>
+            <AdsLszi>1</AdsLszi>
+            <AdsLtoi>1</AdsLtoi>
+            <AdsLsun>1</AdsLsun>
+            <AdsLven>1</AdsLven>
+            <AdsLsxf>1</AdsLsxf>
+            <RvctClst>0</RvctClst>
+            <GenPPlst>0</GenPPlst>
+            <AdsCpuType>"Cortex-M3"</AdsCpuType>
+            <RvctDeviceName></RvctDeviceName>
+            <mOS>0</mOS>
+            <uocRom>0</uocRom>
+            <uocRam>0</uocRam>
+            <hadIROM>1</hadIROM>
+            <hadIRAM>1</hadIRAM>
+            <hadXRAM>0</hadXRAM>
+            <uocXRam>0</uocXRam>
+            <RvdsVP>0</RvdsVP>
+            <hadIRAM2>0</hadIRAM2>
+            <hadIROM2>0</hadIROM2>
+            <StupSel>8</StupSel>
+            <useUlib>0</useUlib>
+            <EndSel>0</EndSel>
+            <uLtcg>0</uLtcg>
+            <RoSelD>3</RoSelD>
+            <RwSelD>3</RwSelD>
+            <CodeSel>0</CodeSel>
+            <OptFeed>0</OptFeed>
+            <NoZi1>0</NoZi1>
+            <NoZi2>0</NoZi2>
+            <NoZi3>0</NoZi3>
+            <NoZi4>0</NoZi4>
+            <NoZi5>0</NoZi5>
+            <Ro1Chk>0</Ro1Chk>
+            <Ro2Chk>0</Ro2Chk>
+            <Ro3Chk>0</Ro3Chk>
+            <Ir1Chk>1</Ir1Chk>
+            <Ir2Chk>0</Ir2Chk>
+            <Ra1Chk>0</Ra1Chk>
+            <Ra2Chk>0</Ra2Chk>
+            <Ra3Chk>0</Ra3Chk>
+            <Im1Chk>1</Im1Chk>
+            <Im2Chk>0</Im2Chk>
+            <OnChipMemories>
+              <Ocm1>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm1>
+              <Ocm2>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm2>
+              <Ocm3>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm3>
+              <Ocm4>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm4>
+              <Ocm5>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm5>
+              <Ocm6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm6>
+              <IRAM>
+                <Type>0</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x8000</Size>
+              </IRAM>
+              <IROM>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x80000</Size>
+              </IROM>
+              <XRAM>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </XRAM>
+              <OCR_RVCT1>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT1>
+              <OCR_RVCT2>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT2>
+              <OCR_RVCT3>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT3>
+              <OCR_RVCT4>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x80000</Size>
+              </OCR_RVCT4>
+              <OCR_RVCT5>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT5>
+              <OCR_RVCT6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT6>
+              <OCR_RVCT7>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT7>
+              <OCR_RVCT8>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT8>
+              <OCR_RVCT9>
+                <Type>0</Type>
+                <StartAddress>0x1fff8000</StartAddress>
+                <Size>0x10000</Size>
+              </OCR_RVCT9>
+              <OCR_RVCT10>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT10>
+            </OnChipMemories>
+            <RvctStartVector></RvctStartVector>
+          </ArmAdsMisc>
+          <Cads>
+            <interw>1</interw>
+            <Optim>1</Optim>
+            <oTime>0</oTime>
+            <SplitLS>0</SplitLS>
+            <OneElfS>0</OneElfS>
+            <Strict>0</Strict>
+            <EnumInt>0</EnumInt>
+            <PlainCh>0</PlainCh>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <wLevel>0</wLevel>
+            <uThumb>0</uThumb>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath>..\CORTEX_MB9B500_IAR_Keil;.\Fujitu_source;..\Common\include;..\..\Source\include;..\..\Source\portable\RVDS\ARM_CM3</IncludePath>
+            </VariousControls>
+          </Cads>
+          <Aads>
+            <interw>1</interw>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <thumb>0</thumb>
+            <SplitLS>0</SplitLS>
+            <SwStkChk>0</SwStkChk>
+            <NoWarn>0</NoWarn>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
+            </VariousControls>
+          </Aads>
+          <LDads>
+            <umfTarg>1</umfTarg>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <noStLib>0</noStLib>
+            <RepFail>1</RepFail>
+            <useFile>0</useFile>
+            <TextAddressRange>0x00000000</TextAddressRange>
+            <DataAddressRange>0x20000000</DataAddressRange>
+            <ScatterFile></ScatterFile>
+            <IncludeLibs></IncludeLibs>
+            <IncludeLibsPath></IncludeLibsPath>
+            <Misc></Misc>
+            <LinkerInputFile></LinkerInputFile>
+            <DisabledWarnings></DisabledWarnings>
+          </LDads>
+        </TargetArmAds>
+      </TargetOption>
+      <Groups>
+        <Group>
+          <GroupName>Fujitsu Source</GroupName>
+          <Files>
+            <File>
+              <FileName>system_mb9bf50x.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\Fujitu_source\system_mb9bf50x.c</FilePath>
+            </File>
+            <File>
+              <FileName>core_cm3.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\Fujitu_source\core_cm3.c</FilePath>
+            </File>
+            <File>
+              <FileName>startup_mb9bf50x.s</FileName>
+              <FileType>2</FileType>
+              <FilePath>.\Fujitu_source\startup_keil\startup_mb9bf50x.s</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>Common_Demo_Source</GroupName>
+          <GroupOption>
+            <CommonProperty>
+              <UseCPPCompiler>0</UseCPPCompiler>
+              <RVCTCodeConst>0</RVCTCodeConst>
+              <RVCTZI>0</RVCTZI>
+              <RVCTOtherData>0</RVCTOtherData>
+              <ModuleSelection>0</ModuleSelection>
+              <IncludeInBuild>0</IncludeInBuild>
+              <AlwaysBuild>2</AlwaysBuild>
+              <GenerateAssemblyFile>2</GenerateAssemblyFile>
+              <AssembleAssemblyFile>2</AssembleAssemblyFile>
+              <PublicsOnly>2</PublicsOnly>
+              <StopOnExitCode>11</StopOnExitCode>
+              <CustomArgument></CustomArgument>
+              <IncludeLibraryModules></IncludeLibraryModules>
+            </CommonProperty>
+            <GroupArmAds>
+              <Cads>
+                <interw>2</interw>
+                <Optim>0</Optim>
+                <oTime>2</oTime>
+                <SplitLS>2</SplitLS>
+                <OneElfS>2</OneElfS>
+                <Strict>2</Strict>
+                <EnumInt>2</EnumInt>
+                <PlainCh>2</PlainCh>
+                <Ropi>2</Ropi>
+                <Rwpi>2</Rwpi>
+                <wLevel>0</wLevel>
+                <uThumb>2</uThumb>
+                <VariousControls>
+                  <MiscControls></MiscControls>
+                  <Define></Define>
+                  <Undefine></Undefine>
+                  <IncludePath></IncludePath>
+                </VariousControls>
+              </Cads>
+              <Aads>
+                <interw>2</interw>
+                <Ropi>2</Ropi>
+                <Rwpi>2</Rwpi>
+                <thumb>2</thumb>
+                <SplitLS>2</SplitLS>
+                <SwStkChk>2</SwStkChk>
+                <NoWarn>2</NoWarn>
+                <VariousControls>
+                  <MiscControls></MiscControls>
+                  <Define></Define>
+                  <Undefine></Undefine>
+                  <IncludePath></IncludePath>
+                </VariousControls>
+              </Aads>
+            </GroupArmAds>
+          </GroupOption>
+          <Files>
+            <File>
+              <FileName>TimerDemo.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\Common\Minimal\TimerDemo.c</FilePath>
+            </File>
+            <File>
+              <FileName>BlockQ.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\Common\Minimal\BlockQ.c</FilePath>
+            </File>
+            <File>
+              <FileName>blocktim.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\Common\Minimal\blocktim.c</FilePath>
+            </File>
+            <File>
+              <FileName>comtest.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\Common\Minimal\comtest.c</FilePath>
+            </File>
+            <File>
+              <FileName>countsem.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\Common\Minimal\countsem.c</FilePath>
+            </File>
+            <File>
+              <FileName>death.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\Common\Minimal\death.c</FilePath>
+            </File>
+            <File>
+              <FileName>dynamic.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\Common\Minimal\dynamic.c</FilePath>
+            </File>
+            <File>
+              <FileName>flash.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\Common\Minimal\flash.c</FilePath>
+            </File>
+            <File>
+              <FileName>GenQTest.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\Common\Minimal\GenQTest.c</FilePath>
+            </File>
+            <File>
+              <FileName>PollQ.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\Common\Minimal\PollQ.c</FilePath>
+            </File>
+            <File>
+              <FileName>QPeek.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\Common\Minimal\QPeek.c</FilePath>
+            </File>
+            <File>
+              <FileName>recmutex.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\Common\Minimal\recmutex.c</FilePath>
+            </File>
+            <File>
+              <FileName>semtest.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\Common\Minimal\semtest.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>FreeRTOS_Source</GroupName>
+          <Files>
+            <File>
+              <FileName>timers.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\Source\timers.c</FilePath>
+            </File>
+            <File>
+              <FileName>list.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\Source\list.c</FilePath>
+            </File>
+            <File>
+              <FileName>queue.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\Source\queue.c</FilePath>
+            </File>
+            <File>
+              <FileName>tasks.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\Source\tasks.c</FilePath>
+            </File>
+            <File>
+              <FileName>port.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\Source\portable\RVDS\ARM_CM3\port.c</FilePath>
+            </File>
+            <File>
+              <FileName>heap_2.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\Source\portable\MemMang\heap_2.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>Demo_Source</GroupName>
+          <Files>
+            <File>
+              <FileName>serial.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\serial.c</FilePath>
+              <FileOption>
+                <CommonProperty>
+                  <UseCPPCompiler>2</UseCPPCompiler>
+                  <RVCTCodeConst>0</RVCTCodeConst>
+                  <RVCTZI>0</RVCTZI>
+                  <RVCTOtherData>0</RVCTOtherData>
+                  <ModuleSelection>0</ModuleSelection>
+                  <IncludeInBuild>0</IncludeInBuild>
+                  <AlwaysBuild>2</AlwaysBuild>
+                  <GenerateAssemblyFile>2</GenerateAssemblyFile>
+                  <AssembleAssemblyFile>2</AssembleAssemblyFile>
+                  <PublicsOnly>2</PublicsOnly>
+                  <StopOnExitCode>11</StopOnExitCode>
+                  <CustomArgument></CustomArgument>
+                  <IncludeLibraryModules></IncludeLibraryModules>
+                </CommonProperty>
+                <FileArmAds>
+                  <Cads>
+                    <interw>2</interw>
+                    <Optim>0</Optim>
+                    <oTime>2</oTime>
+                    <SplitLS>2</SplitLS>
+                    <OneElfS>2</OneElfS>
+                    <Strict>2</Strict>
+                    <EnumInt>2</EnumInt>
+                    <PlainCh>2</PlainCh>
+                    <Ropi>2</Ropi>
+                    <Rwpi>2</Rwpi>
+                    <wLevel>0</wLevel>
+                    <uThumb>2</uThumb>
+                    <VariousControls>
+                      <MiscControls></MiscControls>
+                      <Define></Define>
+                      <Undefine></Undefine>
+                      <IncludePath></IncludePath>
+                    </VariousControls>
+                  </Cads>
+                </FileArmAds>
+              </FileOption>
+            </File>
+            <File>
+              <FileName>main_blinky.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\main_blinky.c</FilePath>
+            </File>
+            <File>
+              <FileName>main-full.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\main-full.c</FilePath>
+              <FileOption>
+                <CommonProperty>
+                  <UseCPPCompiler>2</UseCPPCompiler>
+                  <RVCTCodeConst>0</RVCTCodeConst>
+                  <RVCTZI>0</RVCTZI>
+                  <RVCTOtherData>0</RVCTOtherData>
+                  <ModuleSelection>0</ModuleSelection>
+                  <IncludeInBuild>0</IncludeInBuild>
+                  <AlwaysBuild>2</AlwaysBuild>
+                  <GenerateAssemblyFile>2</GenerateAssemblyFile>
+                  <AssembleAssemblyFile>2</AssembleAssemblyFile>
+                  <PublicsOnly>2</PublicsOnly>
+                  <StopOnExitCode>11</StopOnExitCode>
+                  <CustomArgument></CustomArgument>
+                  <IncludeLibraryModules></IncludeLibraryModules>
+                </CommonProperty>
+                <FileArmAds>
+                  <Cads>
+                    <interw>2</interw>
+                    <Optim>0</Optim>
+                    <oTime>2</oTime>
+                    <SplitLS>2</SplitLS>
+                    <OneElfS>2</OneElfS>
+                    <Strict>2</Strict>
+                    <EnumInt>2</EnumInt>
+                    <PlainCh>2</PlainCh>
+                    <Ropi>2</Ropi>
+                    <Rwpi>2</Rwpi>
+                    <wLevel>0</wLevel>
+                    <uThumb>2</uThumb>
+                    <VariousControls>
+                      <MiscControls></MiscControls>
+                      <Define></Define>
+                      <Undefine></Undefine>
+                      <IncludePath></IncludePath>
+                    </VariousControls>
+                  </Cads>
+                </FileArmAds>
+              </FileOption>
+            </File>
+            <File>
+              <FileName>ParTest.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\ParTest.c</FilePath>
+              <FileOption>
+                <CommonProperty>
+                  <UseCPPCompiler>2</UseCPPCompiler>
+                  <RVCTCodeConst>0</RVCTCodeConst>
+                  <RVCTZI>0</RVCTZI>
+                  <RVCTOtherData>0</RVCTOtherData>
+                  <ModuleSelection>0</ModuleSelection>
+                  <IncludeInBuild>0</IncludeInBuild>
+                  <AlwaysBuild>2</AlwaysBuild>
+                  <GenerateAssemblyFile>2</GenerateAssemblyFile>
+                  <AssembleAssemblyFile>2</AssembleAssemblyFile>
+                  <PublicsOnly>2</PublicsOnly>
+                  <StopOnExitCode>11</StopOnExitCode>
+                  <CustomArgument></CustomArgument>
+                  <IncludeLibraryModules></IncludeLibraryModules>
+                </CommonProperty>
+                <FileArmAds>
+                  <Cads>
+                    <interw>2</interw>
+                    <Optim>0</Optim>
+                    <oTime>2</oTime>
+                    <SplitLS>2</SplitLS>
+                    <OneElfS>2</OneElfS>
+                    <Strict>2</Strict>
+                    <EnumInt>2</EnumInt>
+                    <PlainCh>2</PlainCh>
+                    <Ropi>2</Ropi>
+                    <Rwpi>2</Rwpi>
+                    <wLevel>0</wLevel>
+                    <uThumb>2</uThumb>
+                    <VariousControls>
+                      <MiscControls></MiscControls>
+                      <Define></Define>
+                      <Undefine></Undefine>
+                      <IncludePath></IncludePath>
+                    </VariousControls>
+                  </Cads>
+                </FileArmAds>
+              </FileOption>
+            </File>
+          </Files>
+        </Group>
+      </Groups>
+    </Target>
+    <Target>
+      <TargetName>Full</TargetName>
+      <ToolsetNumber>0x4</ToolsetNumber>
+      <ToolsetName>ARM-ADS</ToolsetName>
+      <TargetOption>
+        <TargetCommonOption>
+          <Device>MB9BF506N</Device>
+          <Vendor>Fujitsu Semiconductors</Vendor>
+          <Cpu>IRAM(0x20000000-0x20007FFF) IROM(0x00000000-0x0007FFFF) CLOCK(4000000) CPUTYPE("Cortex-M3")</Cpu>
+          <FlashUtilSpec></FlashUtilSpec>
+          <StartupFile>"Startup\Fujitsu\MB9B500\startup_MB9BF50x.s" ("Fujitsu MB9BF50x Startup Code")</StartupFile>
+          <FlashDriverDll>UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC800 -FN1 -FF0MB9BFx06_512 -FS00 -FL080000)</FlashDriverDll>
+          <DeviceId>5215</DeviceId>
+          <RegisterFile>MB9BF506N.h</RegisterFile>
+          <MemoryEnv></MemoryEnv>
+          <Cmp></Cmp>
+          <Asm></Asm>
+          <Linker></Linker>
+          <OHString></OHString>
+          <InfinionOptionDll></InfinionOptionDll>
+          <SLE66CMisc></SLE66CMisc>
+          <SLE66AMisc></SLE66AMisc>
+          <SLE66LinkerMisc></SLE66LinkerMisc>
+          <SFDFile></SFDFile>
+          <UseEnv>0</UseEnv>
+          <BinPath></BinPath>
+          <IncludePath></IncludePath>
+          <LibPath></LibPath>
+          <RegisterFilePath>Fujitsu\MB9B500\</RegisterFilePath>
+          <DBRegisterFilePath>Fujitsu\MB9B500\</DBRegisterFilePath>
+          <TargetStatus>
+            <Error>0</Error>
+            <ExitCodeStop>0</ExitCodeStop>
+            <ButtonStop>0</ButtonStop>
+            <NotGenerated>0</NotGenerated>
+            <InvalidFlash>1</InvalidFlash>
+          </TargetStatus>
+          <OutputDirectory>.\output\</OutputDirectory>
+          <OutputName>RTOSDemo_Keil</OutputName>
+          <CreateExecutable>1</CreateExecutable>
+          <CreateLib>0</CreateLib>
+          <CreateHexFile>0</CreateHexFile>
+          <DebugInformation>1</DebugInformation>
+          <BrowseInformation>1</BrowseInformation>
+          <ListingPath>.\</ListingPath>
+          <HexFormatSelection>1</HexFormatSelection>
+          <Merge32K>0</Merge32K>
+          <CreateBatchFile>0</CreateBatchFile>
+          <BeforeCompile>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+          </BeforeCompile>
+          <BeforeMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+          </BeforeMake>
+          <AfterMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+          </AfterMake>
+          <SelectedForBatchBuild>0</SelectedForBatchBuild>
+          <SVCSIdString></SVCSIdString>
+        </TargetCommonOption>
+        <CommonProperty>
+          <UseCPPCompiler>0</UseCPPCompiler>
+          <RVCTCodeConst>0</RVCTCodeConst>
+          <RVCTZI>0</RVCTZI>
+          <RVCTOtherData>0</RVCTOtherData>
+          <ModuleSelection>0</ModuleSelection>
+          <IncludeInBuild>1</IncludeInBuild>
+          <AlwaysBuild>0</AlwaysBuild>
+          <GenerateAssemblyFile>0</GenerateAssemblyFile>
+          <AssembleAssemblyFile>0</AssembleAssemblyFile>
+          <PublicsOnly>0</PublicsOnly>
+          <StopOnExitCode>3</StopOnExitCode>
+          <CustomArgument></CustomArgument>
+          <IncludeLibraryModules></IncludeLibraryModules>
+        </CommonProperty>
+        <DllOption>
+          <SimDllName>SARMCM3.DLL</SimDllName>
+          <SimDllArguments>-MPU</SimDllArguments>
+          <SimDlgDll>DCM.DLL</SimDlgDll>
+          <SimDlgDllArguments>-pCM3</SimDlgDllArguments>
+          <TargetDllName>SARMCM3.DLL</TargetDllName>
+          <TargetDllArguments>-MPU</TargetDllArguments>
+          <TargetDlgDll>TCM.DLL</TargetDlgDll>
+          <TargetDlgDllArguments>-pCM3</TargetDlgDllArguments>
+        </DllOption>
+        <DebugOption>
+          <OPTHX>
+            <HexSelection>1</HexSelection>
+            <HexRangeLowAddress>0</HexRangeLowAddress>
+            <HexRangeHighAddress>0</HexRangeHighAddress>
+            <HexOffset>0</HexOffset>
+            <Oh166RecLen>16</Oh166RecLen>
+          </OPTHX>
+          <Simulator>
+            <UseSimulator>0</UseSimulator>
+            <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+            <RunToMain>1</RunToMain>
+            <RestoreBreakpoints>1</RestoreBreakpoints>
+            <RestoreWatchpoints>1</RestoreWatchpoints>
+            <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+            <RestoreFunctions>1</RestoreFunctions>
+            <RestoreToolbox>1</RestoreToolbox>
+            <LimitSpeedToRealTime>0</LimitSpeedToRealTime>
+          </Simulator>
+          <Target>
+            <UseTarget>1</UseTarget>
+            <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+            <RunToMain>1</RunToMain>
+            <RestoreBreakpoints>1</RestoreBreakpoints>
+            <RestoreWatchpoints>1</RestoreWatchpoints>
+            <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+            <RestoreFunctions>0</RestoreFunctions>
+            <RestoreToolbox>1</RestoreToolbox>
+          </Target>
+          <RunDebugAfterBuild>0</RunDebugAfterBuild>
+          <TargetSelection>1</TargetSelection>
+          <SimDlls>
+            <CpuDll></CpuDll>
+            <CpuDllArguments></CpuDllArguments>
+            <PeripheralDll></PeripheralDll>
+            <PeripheralDllArguments></PeripheralDllArguments>
+            <InitializationFile></InitializationFile>
+          </SimDlls>
+          <TargetDlls>
+            <CpuDll></CpuDll>
+            <CpuDllArguments></CpuDllArguments>
+            <PeripheralDll></PeripheralDll>
+            <PeripheralDllArguments></PeripheralDllArguments>
+            <InitializationFile></InitializationFile>
+            <Driver>BIN\UL2CM3.DLL</Driver>
+          </TargetDlls>
+        </DebugOption>
+        <Utilities>
+          <Flash1>
+            <UseTargetDll>1</UseTargetDll>
+            <UseExternalTool>0</UseExternalTool>
+            <RunIndependent>0</RunIndependent>
+            <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
+            <Capability>1</Capability>
+            <DriverSelection>4096</DriverSelection>
+          </Flash1>
+          <Flash2>BIN\UL2CM3.DLL</Flash2>
+          <Flash3>"" ()</Flash3>
+          <Flash4></Flash4>
+        </Utilities>
+        <TargetArmAds>
+          <ArmAdsMisc>
+            <GenerateListings>0</GenerateListings>
+            <asHll>1</asHll>
+            <asAsm>1</asAsm>
+            <asMacX>1</asMacX>
+            <asSyms>1</asSyms>
+            <asFals>1</asFals>
+            <asDbgD>1</asDbgD>
+            <asForm>1</asForm>
+            <ldLst>0</ldLst>
+            <ldmm>1</ldmm>
+            <ldXref>1</ldXref>
+            <BigEnd>0</BigEnd>
+            <AdsALst>1</AdsALst>
+            <AdsACrf>1</AdsACrf>
+            <AdsANop>0</AdsANop>
+            <AdsANot>0</AdsANot>
+            <AdsLLst>1</AdsLLst>
+            <AdsLmap>1</AdsLmap>
+            <AdsLcgr>1</AdsLcgr>
+            <AdsLsym>1</AdsLsym>
+            <AdsLszi>1</AdsLszi>
+            <AdsLtoi>1</AdsLtoi>
+            <AdsLsun>1</AdsLsun>
+            <AdsLven>1</AdsLven>
+            <AdsLsxf>1</AdsLsxf>
+            <RvctClst>0</RvctClst>
+            <GenPPlst>0</GenPPlst>
+            <AdsCpuType>"Cortex-M3"</AdsCpuType>
+            <RvctDeviceName></RvctDeviceName>
+            <mOS>0</mOS>
+            <uocRom>0</uocRom>
+            <uocRam>0</uocRam>
+            <hadIROM>1</hadIROM>
+            <hadIRAM>1</hadIRAM>
+            <hadXRAM>0</hadXRAM>
+            <uocXRam>0</uocXRam>
+            <RvdsVP>0</RvdsVP>
+            <hadIRAM2>0</hadIRAM2>
+            <hadIROM2>0</hadIROM2>
+            <StupSel>8</StupSel>
+            <useUlib>0</useUlib>
+            <EndSel>0</EndSel>
+            <uLtcg>0</uLtcg>
+            <RoSelD>3</RoSelD>
+            <RwSelD>3</RwSelD>
+            <CodeSel>0</CodeSel>
+            <OptFeed>0</OptFeed>
+            <NoZi1>0</NoZi1>
+            <NoZi2>0</NoZi2>
+            <NoZi3>0</NoZi3>
+            <NoZi4>0</NoZi4>
+            <NoZi5>0</NoZi5>
+            <Ro1Chk>0</Ro1Chk>
+            <Ro2Chk>0</Ro2Chk>
+            <Ro3Chk>0</Ro3Chk>
+            <Ir1Chk>1</Ir1Chk>
+            <Ir2Chk>0</Ir2Chk>
+            <Ra1Chk>0</Ra1Chk>
+            <Ra2Chk>0</Ra2Chk>
+            <Ra3Chk>0</Ra3Chk>
+            <Im1Chk>1</Im1Chk>
+            <Im2Chk>0</Im2Chk>
+            <OnChipMemories>
+              <Ocm1>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm1>
+              <Ocm2>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm2>
+              <Ocm3>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm3>
+              <Ocm4>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm4>
+              <Ocm5>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm5>
+              <Ocm6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm6>
+              <IRAM>
+                <Type>0</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x8000</Size>
+              </IRAM>
+              <IROM>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x80000</Size>
+              </IROM>
+              <XRAM>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </XRAM>
+              <OCR_RVCT1>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT1>
+              <OCR_RVCT2>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT2>
+              <OCR_RVCT3>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT3>
+              <OCR_RVCT4>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x80000</Size>
+              </OCR_RVCT4>
+              <OCR_RVCT5>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT5>
+              <OCR_RVCT6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT6>
+              <OCR_RVCT7>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT7>
+              <OCR_RVCT8>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT8>
+              <OCR_RVCT9>
+                <Type>0</Type>
+                <StartAddress>0x1fff8000</StartAddress>
+                <Size>0x10000</Size>
+              </OCR_RVCT9>
+              <OCR_RVCT10>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT10>
+            </OnChipMemories>
+            <RvctStartVector></RvctStartVector>
+          </ArmAdsMisc>
+          <Cads>
+            <interw>1</interw>
+            <Optim>4</Optim>
+            <oTime>0</oTime>
+            <SplitLS>0</SplitLS>
+            <OneElfS>0</OneElfS>
+            <Strict>0</Strict>
+            <EnumInt>0</EnumInt>
+            <PlainCh>0</PlainCh>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <wLevel>0</wLevel>
+            <uThumb>0</uThumb>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath>..\CORTEX_MB9B500_IAR_Keil;.\Fujitu_source;..\Common\include;..\..\Source\include;..\..\Source\portable\RVDS\ARM_CM3</IncludePath>
+            </VariousControls>
+          </Cads>
+          <Aads>
+            <interw>1</interw>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <thumb>0</thumb>
+            <SplitLS>0</SplitLS>
+            <SwStkChk>0</SwStkChk>
+            <NoWarn>0</NoWarn>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
+            </VariousControls>
+          </Aads>
+          <LDads>
+            <umfTarg>1</umfTarg>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <noStLib>0</noStLib>
+            <RepFail>1</RepFail>
+            <useFile>0</useFile>
+            <TextAddressRange>0x00000000</TextAddressRange>
+            <DataAddressRange>0x20000000</DataAddressRange>
+            <ScatterFile></ScatterFile>
+            <IncludeLibs></IncludeLibs>
+            <IncludeLibsPath></IncludeLibsPath>
+            <Misc></Misc>
+            <LinkerInputFile></LinkerInputFile>
+            <DisabledWarnings></DisabledWarnings>
+          </LDads>
+        </TargetArmAds>
+      </TargetOption>
+      <Groups>
+        <Group>
+          <GroupName>Fujitsu Source</GroupName>
+          <Files>
+            <File>
+              <FileName>system_mb9bf50x.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\Fujitu_source\system_mb9bf50x.c</FilePath>
+            </File>
+            <File>
+              <FileName>core_cm3.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\Fujitu_source\core_cm3.c</FilePath>
+            </File>
+            <File>
+              <FileName>startup_mb9bf50x.s</FileName>
+              <FileType>2</FileType>
+              <FilePath>.\Fujitu_source\startup_keil\startup_mb9bf50x.s</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>Common_Demo_Source</GroupName>
+          <GroupOption>
+            <CommonProperty>
+              <UseCPPCompiler>0</UseCPPCompiler>
+              <RVCTCodeConst>0</RVCTCodeConst>
+              <RVCTZI>0</RVCTZI>
+              <RVCTOtherData>0</RVCTOtherData>
+              <ModuleSelection>0</ModuleSelection>
+              <IncludeInBuild>1</IncludeInBuild>
+              <AlwaysBuild>2</AlwaysBuild>
+              <GenerateAssemblyFile>2</GenerateAssemblyFile>
+              <AssembleAssemblyFile>2</AssembleAssemblyFile>
+              <PublicsOnly>2</PublicsOnly>
+              <StopOnExitCode>11</StopOnExitCode>
+              <CustomArgument></CustomArgument>
+              <IncludeLibraryModules></IncludeLibraryModules>
+            </CommonProperty>
+            <GroupArmAds>
+              <Cads>
+                <interw>2</interw>
+                <Optim>0</Optim>
+                <oTime>2</oTime>
+                <SplitLS>2</SplitLS>
+                <OneElfS>2</OneElfS>
+                <Strict>2</Strict>
+                <EnumInt>2</EnumInt>
+                <PlainCh>2</PlainCh>
+                <Ropi>2</Ropi>
+                <Rwpi>2</Rwpi>
+                <wLevel>0</wLevel>
+                <uThumb>2</uThumb>
+                <VariousControls>
+                  <MiscControls></MiscControls>
+                  <Define></Define>
+                  <Undefine></Undefine>
+                  <IncludePath></IncludePath>
+                </VariousControls>
+              </Cads>
+              <Aads>
+                <interw>2</interw>
+                <Ropi>2</Ropi>
+                <Rwpi>2</Rwpi>
+                <thumb>2</thumb>
+                <SplitLS>2</SplitLS>
+                <SwStkChk>2</SwStkChk>
+                <NoWarn>2</NoWarn>
+                <VariousControls>
+                  <MiscControls></MiscControls>
+                  <Define></Define>
+                  <Undefine></Undefine>
+                  <IncludePath></IncludePath>
+                </VariousControls>
+              </Aads>
+            </GroupArmAds>
+          </GroupOption>
+          <Files>
+            <File>
+              <FileName>TimerDemo.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\Common\Minimal\TimerDemo.c</FilePath>
+            </File>
+            <File>
+              <FileName>BlockQ.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\Common\Minimal\BlockQ.c</FilePath>
+            </File>
+            <File>
+              <FileName>blocktim.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\Common\Minimal\blocktim.c</FilePath>
+            </File>
+            <File>
+              <FileName>comtest.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\Common\Minimal\comtest.c</FilePath>
+            </File>
+            <File>
+              <FileName>countsem.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\Common\Minimal\countsem.c</FilePath>
+            </File>
+            <File>
+              <FileName>death.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\Common\Minimal\death.c</FilePath>
+            </File>
+            <File>
+              <FileName>dynamic.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\Common\Minimal\dynamic.c</FilePath>
+            </File>
+            <File>
+              <FileName>flash.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\Common\Minimal\flash.c</FilePath>
+            </File>
+            <File>
+              <FileName>GenQTest.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\Common\Minimal\GenQTest.c</FilePath>
+            </File>
+            <File>
+              <FileName>PollQ.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\Common\Minimal\PollQ.c</FilePath>
+            </File>
+            <File>
+              <FileName>QPeek.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\Common\Minimal\QPeek.c</FilePath>
+            </File>
+            <File>
+              <FileName>recmutex.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\Common\Minimal\recmutex.c</FilePath>
+            </File>
+            <File>
+              <FileName>semtest.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\Common\Minimal\semtest.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>FreeRTOS_Source</GroupName>
+          <Files>
+            <File>
+              <FileName>timers.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\Source\timers.c</FilePath>
+            </File>
+            <File>
+              <FileName>list.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\Source\list.c</FilePath>
+            </File>
+            <File>
+              <FileName>queue.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\Source\queue.c</FilePath>
+            </File>
+            <File>
+              <FileName>tasks.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\Source\tasks.c</FilePath>
+            </File>
+            <File>
+              <FileName>port.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\Source\portable\RVDS\ARM_CM3\port.c</FilePath>
+            </File>
+            <File>
+              <FileName>heap_2.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\Source\portable\MemMang\heap_2.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>Demo_Source</GroupName>
+          <Files>
+            <File>
+              <FileName>serial.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\serial.c</FilePath>
+              <FileOption>
+                <CommonProperty>
+                  <UseCPPCompiler>2</UseCPPCompiler>
+                  <RVCTCodeConst>0</RVCTCodeConst>
+                  <RVCTZI>0</RVCTZI>
+                  <RVCTOtherData>0</RVCTOtherData>
+                  <ModuleSelection>0</ModuleSelection>
+                  <IncludeInBuild>1</IncludeInBuild>
+                  <AlwaysBuild>2</AlwaysBuild>
+                  <GenerateAssemblyFile>2</GenerateAssemblyFile>
+                  <AssembleAssemblyFile>2</AssembleAssemblyFile>
+                  <PublicsOnly>2</PublicsOnly>
+                  <StopOnExitCode>11</StopOnExitCode>
+                  <CustomArgument></CustomArgument>
+                  <IncludeLibraryModules></IncludeLibraryModules>
+                </CommonProperty>
+                <FileArmAds>
+                  <Cads>
+                    <interw>2</interw>
+                    <Optim>0</Optim>
+                    <oTime>2</oTime>
+                    <SplitLS>2</SplitLS>
+                    <OneElfS>2</OneElfS>
+                    <Strict>2</Strict>
+                    <EnumInt>2</EnumInt>
+                    <PlainCh>2</PlainCh>
+                    <Ropi>2</Ropi>
+                    <Rwpi>2</Rwpi>
+                    <wLevel>0</wLevel>
+                    <uThumb>2</uThumb>
+                    <VariousControls>
+                      <MiscControls></MiscControls>
+                      <Define></Define>
+                      <Undefine></Undefine>
+                      <IncludePath></IncludePath>
+                    </VariousControls>
+                  </Cads>
+                </FileArmAds>
+              </FileOption>
+            </File>
+            <File>
+              <FileName>main_blinky.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\main_blinky.c</FilePath>
+              <FileOption>
+                <CommonProperty>
+                  <UseCPPCompiler>2</UseCPPCompiler>
+                  <RVCTCodeConst>0</RVCTCodeConst>
+                  <RVCTZI>0</RVCTZI>
+                  <RVCTOtherData>0</RVCTOtherData>
+                  <ModuleSelection>0</ModuleSelection>
+                  <IncludeInBuild>0</IncludeInBuild>
+                  <AlwaysBuild>2</AlwaysBuild>
+                  <GenerateAssemblyFile>2</GenerateAssemblyFile>
+                  <AssembleAssemblyFile>2</AssembleAssemblyFile>
+                  <PublicsOnly>2</PublicsOnly>
+                  <StopOnExitCode>11</StopOnExitCode>
+                  <CustomArgument></CustomArgument>
+                  <IncludeLibraryModules></IncludeLibraryModules>
+                </CommonProperty>
+                <FileArmAds>
+                  <Cads>
+                    <interw>2</interw>
+                    <Optim>0</Optim>
+                    <oTime>2</oTime>
+                    <SplitLS>2</SplitLS>
+                    <OneElfS>2</OneElfS>
+                    <Strict>2</Strict>
+                    <EnumInt>2</EnumInt>
+                    <PlainCh>2</PlainCh>
+                    <Ropi>2</Ropi>
+                    <Rwpi>2</Rwpi>
+                    <wLevel>0</wLevel>
+                    <uThumb>2</uThumb>
+                    <VariousControls>
+                      <MiscControls></MiscControls>
+                      <Define></Define>
+                      <Undefine></Undefine>
+                      <IncludePath></IncludePath>
+                    </VariousControls>
+                  </Cads>
+                </FileArmAds>
+              </FileOption>
+            </File>
+            <File>
+              <FileName>main-full.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\main-full.c</FilePath>
+              <FileOption>
+                <CommonProperty>
+                  <UseCPPCompiler>2</UseCPPCompiler>
+                  <RVCTCodeConst>0</RVCTCodeConst>
+                  <RVCTZI>0</RVCTZI>
+                  <RVCTOtherData>0</RVCTOtherData>
+                  <ModuleSelection>0</ModuleSelection>
+                  <IncludeInBuild>1</IncludeInBuild>
+                  <AlwaysBuild>2</AlwaysBuild>
+                  <GenerateAssemblyFile>2</GenerateAssemblyFile>
+                  <AssembleAssemblyFile>2</AssembleAssemblyFile>
+                  <PublicsOnly>2</PublicsOnly>
+                  <StopOnExitCode>11</StopOnExitCode>
+                  <CustomArgument></CustomArgument>
+                  <IncludeLibraryModules></IncludeLibraryModules>
+                </CommonProperty>
+                <FileArmAds>
+                  <Cads>
+                    <interw>2</interw>
+                    <Optim>0</Optim>
+                    <oTime>2</oTime>
+                    <SplitLS>2</SplitLS>
+                    <OneElfS>2</OneElfS>
+                    <Strict>2</Strict>
+                    <EnumInt>2</EnumInt>
+                    <PlainCh>2</PlainCh>
+                    <Ropi>2</Ropi>
+                    <Rwpi>2</Rwpi>
+                    <wLevel>0</wLevel>
+                    <uThumb>2</uThumb>
+                    <VariousControls>
+                      <MiscControls></MiscControls>
+                      <Define></Define>
+                      <Undefine></Undefine>
+                      <IncludePath></IncludePath>
+                    </VariousControls>
+                  </Cads>
+                </FileArmAds>
+              </FileOption>
+            </File>
+            <File>
+              <FileName>ParTest.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\ParTest.c</FilePath>
+              <FileOption>
+                <CommonProperty>
+                  <UseCPPCompiler>2</UseCPPCompiler>
+                  <RVCTCodeConst>0</RVCTCodeConst>
+                  <RVCTZI>0</RVCTZI>
+                  <RVCTOtherData>0</RVCTOtherData>
+                  <ModuleSelection>0</ModuleSelection>
+                  <IncludeInBuild>1</IncludeInBuild>
+                  <AlwaysBuild>2</AlwaysBuild>
+                  <GenerateAssemblyFile>2</GenerateAssemblyFile>
+                  <AssembleAssemblyFile>2</AssembleAssemblyFile>
+                  <PublicsOnly>2</PublicsOnly>
+                  <StopOnExitCode>11</StopOnExitCode>
+                  <CustomArgument></CustomArgument>
+                  <IncludeLibraryModules></IncludeLibraryModules>
+                </CommonProperty>
+                <FileArmAds>
+                  <Cads>
+                    <interw>2</interw>
+                    <Optim>0</Optim>
+                    <oTime>2</oTime>
+                    <SplitLS>2</SplitLS>
+                    <OneElfS>2</OneElfS>
+                    <Strict>2</Strict>
+                    <EnumInt>2</EnumInt>
+                    <PlainCh>2</PlainCh>
+                    <Ropi>2</Ropi>
+                    <Rwpi>2</Rwpi>
+                    <wLevel>0</wLevel>
+                    <uThumb>2</uThumb>
+                    <VariousControls>
+                      <MiscControls></MiscControls>
+                      <Define></Define>
+                      <Undefine></Undefine>
+                      <IncludePath></IncludePath>
+                    </VariousControls>
+                  </Cads>
+                </FileArmAds>
+              </FileOption>
+            </File>
+          </Files>
+        </Group>
+      </Groups>
+    </Target>
+    <Target>
+      <TargetName>Full_with_optimisation</TargetName>
+      <ToolsetNumber>0x4</ToolsetNumber>
+      <ToolsetName>ARM-ADS</ToolsetName>
+      <TargetOption>
+        <TargetCommonOption>
+          <Device>MB9BF506N</Device>
+          <Vendor>Fujitsu Semiconductors</Vendor>
+          <Cpu>IRAM(0x20000000-0x20007FFF) IROM(0x00000000-0x0007FFFF) CLOCK(4000000) CPUTYPE("Cortex-M3")</Cpu>
+          <FlashUtilSpec></FlashUtilSpec>
+          <StartupFile>"Startup\Fujitsu\MB9B500\startup_MB9BF50x.s" ("Fujitsu MB9BF50x Startup Code")</StartupFile>
+          <FlashDriverDll>UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC800 -FN1 -FF0MB9BFx06_512 -FS00 -FL080000)</FlashDriverDll>
+          <DeviceId>5215</DeviceId>
+          <RegisterFile>MB9BF506N.h</RegisterFile>
+          <MemoryEnv></MemoryEnv>
+          <Cmp></Cmp>
+          <Asm></Asm>
+          <Linker></Linker>
+          <OHString></OHString>
+          <InfinionOptionDll></InfinionOptionDll>
+          <SLE66CMisc></SLE66CMisc>
+          <SLE66AMisc></SLE66AMisc>
+          <SLE66LinkerMisc></SLE66LinkerMisc>
+          <SFDFile></SFDFile>
+          <UseEnv>0</UseEnv>
+          <BinPath></BinPath>
+          <IncludePath></IncludePath>
+          <LibPath></LibPath>
+          <RegisterFilePath>Fujitsu\MB9B500\</RegisterFilePath>
+          <DBRegisterFilePath>Fujitsu\MB9B500\</DBRegisterFilePath>
+          <TargetStatus>
+            <Error>0</Error>
+            <ExitCodeStop>0</ExitCodeStop>
+            <ButtonStop>0</ButtonStop>
+            <NotGenerated>0</NotGenerated>
+            <InvalidFlash>1</InvalidFlash>
+          </TargetStatus>
+          <OutputDirectory>.\output\</OutputDirectory>
+          <OutputName>RTOSDemo_Keil</OutputName>
+          <CreateExecutable>1</CreateExecutable>
+          <CreateLib>0</CreateLib>
+          <CreateHexFile>0</CreateHexFile>
+          <DebugInformation>1</DebugInformation>
+          <BrowseInformation>1</BrowseInformation>
+          <ListingPath>.\</ListingPath>
+          <HexFormatSelection>1</HexFormatSelection>
+          <Merge32K>0</Merge32K>
+          <CreateBatchFile>0</CreateBatchFile>
+          <BeforeCompile>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+          </BeforeCompile>
+          <BeforeMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+          </BeforeMake>
+          <AfterMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+          </AfterMake>
+          <SelectedForBatchBuild>0</SelectedForBatchBuild>
+          <SVCSIdString></SVCSIdString>
+        </TargetCommonOption>
+        <CommonProperty>
+          <UseCPPCompiler>0</UseCPPCompiler>
+          <RVCTCodeConst>0</RVCTCodeConst>
+          <RVCTZI>0</RVCTZI>
+          <RVCTOtherData>0</RVCTOtherData>
+          <ModuleSelection>0</ModuleSelection>
+          <IncludeInBuild>1</IncludeInBuild>
+          <AlwaysBuild>0</AlwaysBuild>
+          <GenerateAssemblyFile>0</GenerateAssemblyFile>
+          <AssembleAssemblyFile>0</AssembleAssemblyFile>
+          <PublicsOnly>0</PublicsOnly>
+          <StopOnExitCode>3</StopOnExitCode>
+          <CustomArgument></CustomArgument>
+          <IncludeLibraryModules></IncludeLibraryModules>
+        </CommonProperty>
+        <DllOption>
+          <SimDllName>SARMCM3.DLL</SimDllName>
+          <SimDllArguments>-MPU</SimDllArguments>
+          <SimDlgDll>DCM.DLL</SimDlgDll>
+          <SimDlgDllArguments>-pCM3</SimDlgDllArguments>
+          <TargetDllName>SARMCM3.DLL</TargetDllName>
+          <TargetDllArguments>-MPU</TargetDllArguments>
+          <TargetDlgDll>TCM.DLL</TargetDlgDll>
+          <TargetDlgDllArguments>-pCM3</TargetDlgDllArguments>
+        </DllOption>
+        <DebugOption>
+          <OPTHX>
+            <HexSelection>1</HexSelection>
+            <HexRangeLowAddress>0</HexRangeLowAddress>
+            <HexRangeHighAddress>0</HexRangeHighAddress>
+            <HexOffset>0</HexOffset>
+            <Oh166RecLen>16</Oh166RecLen>
+          </OPTHX>
+          <Simulator>
+            <UseSimulator>0</UseSimulator>
+            <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+            <RunToMain>1</RunToMain>
+            <RestoreBreakpoints>1</RestoreBreakpoints>
+            <RestoreWatchpoints>1</RestoreWatchpoints>
+            <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+            <RestoreFunctions>1</RestoreFunctions>
+            <RestoreToolbox>1</RestoreToolbox>
+            <LimitSpeedToRealTime>0</LimitSpeedToRealTime>
+          </Simulator>
+          <Target>
+            <UseTarget>1</UseTarget>
+            <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+            <RunToMain>1</RunToMain>
+            <RestoreBreakpoints>1</RestoreBreakpoints>
+            <RestoreWatchpoints>1</RestoreWatchpoints>
+            <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+            <RestoreFunctions>0</RestoreFunctions>
+            <RestoreToolbox>1</RestoreToolbox>
+          </Target>
+          <RunDebugAfterBuild>0</RunDebugAfterBuild>
+          <TargetSelection>1</TargetSelection>
+          <SimDlls>
+            <CpuDll></CpuDll>
+            <CpuDllArguments></CpuDllArguments>
+            <PeripheralDll></PeripheralDll>
+            <PeripheralDllArguments></PeripheralDllArguments>
+            <InitializationFile></InitializationFile>
+          </SimDlls>
+          <TargetDlls>
+            <CpuDll></CpuDll>
+            <CpuDllArguments></CpuDllArguments>
+            <PeripheralDll></PeripheralDll>
+            <PeripheralDllArguments></PeripheralDllArguments>
+            <InitializationFile></InitializationFile>
+            <Driver>BIN\UL2CM3.DLL</Driver>
+          </TargetDlls>
+        </DebugOption>
+        <Utilities>
+          <Flash1>
+            <UseTargetDll>1</UseTargetDll>
+            <UseExternalTool>0</UseExternalTool>
+            <RunIndependent>0</RunIndependent>
+            <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
+            <Capability>1</Capability>
+            <DriverSelection>4096</DriverSelection>
+          </Flash1>
+          <Flash2>BIN\UL2CM3.DLL</Flash2>
+          <Flash3>"" ()</Flash3>
+          <Flash4></Flash4>
+        </Utilities>
+        <TargetArmAds>
+          <ArmAdsMisc>
+            <GenerateListings>0</GenerateListings>
+            <asHll>1</asHll>
+            <asAsm>1</asAsm>
+            <asMacX>1</asMacX>
+            <asSyms>1</asSyms>
+            <asFals>1</asFals>
+            <asDbgD>1</asDbgD>
+            <asForm>1</asForm>
+            <ldLst>0</ldLst>
+            <ldmm>1</ldmm>
+            <ldXref>1</ldXref>
+            <BigEnd>0</BigEnd>
+            <AdsALst>1</AdsALst>
+            <AdsACrf>1</AdsACrf>
+            <AdsANop>0</AdsANop>
+            <AdsANot>0</AdsANot>
+            <AdsLLst>1</AdsLLst>
+            <AdsLmap>1</AdsLmap>
+            <AdsLcgr>1</AdsLcgr>
+            <AdsLsym>1</AdsLsym>
+            <AdsLszi>1</AdsLszi>
+            <AdsLtoi>1</AdsLtoi>
+            <AdsLsun>1</AdsLsun>
+            <AdsLven>1</AdsLven>
+            <AdsLsxf>1</AdsLsxf>
+            <RvctClst>0</RvctClst>
+            <GenPPlst>0</GenPPlst>
+            <AdsCpuType>"Cortex-M3"</AdsCpuType>
+            <RvctDeviceName></RvctDeviceName>
+            <mOS>0</mOS>
+            <uocRom>0</uocRom>
+            <uocRam>0</uocRam>
+            <hadIROM>1</hadIROM>
+            <hadIRAM>1</hadIRAM>
+            <hadXRAM>0</hadXRAM>
+            <uocXRam>0</uocXRam>
+            <RvdsVP>0</RvdsVP>
+            <hadIRAM2>0</hadIRAM2>
+            <hadIROM2>0</hadIROM2>
+            <StupSel>8</StupSel>
+            <useUlib>0</useUlib>
+            <EndSel>0</EndSel>
+            <uLtcg>0</uLtcg>
+            <RoSelD>3</RoSelD>
+            <RwSelD>3</RwSelD>
+            <CodeSel>0</CodeSel>
+            <OptFeed>0</OptFeed>
+            <NoZi1>0</NoZi1>
+            <NoZi2>0</NoZi2>
+            <NoZi3>0</NoZi3>
+            <NoZi4>0</NoZi4>
+            <NoZi5>0</NoZi5>
+            <Ro1Chk>0</Ro1Chk>
+            <Ro2Chk>0</Ro2Chk>
+            <Ro3Chk>0</Ro3Chk>
+            <Ir1Chk>1</Ir1Chk>
+            <Ir2Chk>0</Ir2Chk>
+            <Ra1Chk>0</Ra1Chk>
+            <Ra2Chk>0</Ra2Chk>
+            <Ra3Chk>0</Ra3Chk>
+            <Im1Chk>1</Im1Chk>
+            <Im2Chk>0</Im2Chk>
+            <OnChipMemories>
+              <Ocm1>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm1>
+              <Ocm2>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm2>
+              <Ocm3>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm3>
+              <Ocm4>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm4>
+              <Ocm5>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm5>
+              <Ocm6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm6>
+              <IRAM>
+                <Type>0</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x8000</Size>
+              </IRAM>
+              <IROM>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x80000</Size>
+              </IROM>
+              <XRAM>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </XRAM>
+              <OCR_RVCT1>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT1>
+              <OCR_RVCT2>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT2>
+              <OCR_RVCT3>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT3>
+              <OCR_RVCT4>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x80000</Size>
+              </OCR_RVCT4>
+              <OCR_RVCT5>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT5>
+              <OCR_RVCT6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT6>
+              <OCR_RVCT7>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT7>
+              <OCR_RVCT8>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT8>
+              <OCR_RVCT9>
+                <Type>0</Type>
+                <StartAddress>0x1fff8000</StartAddress>
+                <Size>0x10000</Size>
+              </OCR_RVCT9>
+              <OCR_RVCT10>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT10>
+            </OnChipMemories>
+            <RvctStartVector></RvctStartVector>
+          </ArmAdsMisc>
+          <Cads>
+            <interw>1</interw>
+            <Optim>1</Optim>
+            <oTime>0</oTime>
+            <SplitLS>0</SplitLS>
+            <OneElfS>0</OneElfS>
+            <Strict>0</Strict>
+            <EnumInt>0</EnumInt>
+            <PlainCh>0</PlainCh>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <wLevel>0</wLevel>
+            <uThumb>0</uThumb>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath>..\CORTEX_MB9B500_IAR_Keil;.\Fujitu_source;..\Common\include;..\..\Source\include;..\..\Source\portable\RVDS\ARM_CM3</IncludePath>
+            </VariousControls>
+          </Cads>
+          <Aads>
+            <interw>1</interw>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <thumb>0</thumb>
+            <SplitLS>0</SplitLS>
+            <SwStkChk>0</SwStkChk>
+            <NoWarn>0</NoWarn>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
+            </VariousControls>
+          </Aads>
+          <LDads>
+            <umfTarg>1</umfTarg>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <noStLib>0</noStLib>
+            <RepFail>1</RepFail>
+            <useFile>0</useFile>
+            <TextAddressRange>0x00000000</TextAddressRange>
+            <DataAddressRange>0x20000000</DataAddressRange>
+            <ScatterFile></ScatterFile>
+            <IncludeLibs></IncludeLibs>
+            <IncludeLibsPath></IncludeLibsPath>
+            <Misc></Misc>
+            <LinkerInputFile></LinkerInputFile>
+            <DisabledWarnings></DisabledWarnings>
+          </LDads>
+        </TargetArmAds>
+      </TargetOption>
+      <Groups>
+        <Group>
+          <GroupName>Fujitsu Source</GroupName>
+          <Files>
+            <File>
+              <FileName>system_mb9bf50x.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\Fujitu_source\system_mb9bf50x.c</FilePath>
+            </File>
+            <File>
+              <FileName>core_cm3.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\Fujitu_source\core_cm3.c</FilePath>
+            </File>
+            <File>
+              <FileName>startup_mb9bf50x.s</FileName>
+              <FileType>2</FileType>
+              <FilePath>.\Fujitu_source\startup_keil\startup_mb9bf50x.s</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>Common_Demo_Source</GroupName>
+          <GroupOption>
+            <CommonProperty>
+              <UseCPPCompiler>0</UseCPPCompiler>
+              <RVCTCodeConst>0</RVCTCodeConst>
+              <RVCTZI>0</RVCTZI>
+              <RVCTOtherData>0</RVCTOtherData>
+              <ModuleSelection>0</ModuleSelection>
+              <IncludeInBuild>1</IncludeInBuild>
+              <AlwaysBuild>2</AlwaysBuild>
+              <GenerateAssemblyFile>2</GenerateAssemblyFile>
+              <AssembleAssemblyFile>2</AssembleAssemblyFile>
+              <PublicsOnly>2</PublicsOnly>
+              <StopOnExitCode>11</StopOnExitCode>
+              <CustomArgument></CustomArgument>
+              <IncludeLibraryModules></IncludeLibraryModules>
+            </CommonProperty>
+            <GroupArmAds>
+              <Cads>
+                <interw>2</interw>
+                <Optim>0</Optim>
+                <oTime>2</oTime>
+                <SplitLS>2</SplitLS>
+                <OneElfS>2</OneElfS>
+                <Strict>2</Strict>
+                <EnumInt>2</EnumInt>
+                <PlainCh>2</PlainCh>
+                <Ropi>2</Ropi>
+                <Rwpi>2</Rwpi>
+                <wLevel>0</wLevel>
+                <uThumb>2</uThumb>
+                <VariousControls>
+                  <MiscControls></MiscControls>
+                  <Define></Define>
+                  <Undefine></Undefine>
+                  <IncludePath></IncludePath>
+                </VariousControls>
+              </Cads>
+              <Aads>
+                <interw>2</interw>
+                <Ropi>2</Ropi>
+                <Rwpi>2</Rwpi>
+                <thumb>2</thumb>
+                <SplitLS>2</SplitLS>
+                <SwStkChk>2</SwStkChk>
+                <NoWarn>2</NoWarn>
+                <VariousControls>
+                  <MiscControls></MiscControls>
+                  <Define></Define>
+                  <Undefine></Undefine>
+                  <IncludePath></IncludePath>
+                </VariousControls>
+              </Aads>
+            </GroupArmAds>
+          </GroupOption>
+          <Files>
+            <File>
+              <FileName>TimerDemo.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\Common\Minimal\TimerDemo.c</FilePath>
+            </File>
+            <File>
+              <FileName>BlockQ.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\Common\Minimal\BlockQ.c</FilePath>
+            </File>
+            <File>
+              <FileName>blocktim.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\Common\Minimal\blocktim.c</FilePath>
+            </File>
+            <File>
+              <FileName>comtest.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\Common\Minimal\comtest.c</FilePath>
+            </File>
+            <File>
+              <FileName>countsem.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\Common\Minimal\countsem.c</FilePath>
+            </File>
+            <File>
+              <FileName>death.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\Common\Minimal\death.c</FilePath>
+            </File>
+            <File>
+              <FileName>dynamic.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\Common\Minimal\dynamic.c</FilePath>
+            </File>
+            <File>
+              <FileName>flash.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\Common\Minimal\flash.c</FilePath>
+            </File>
+            <File>
+              <FileName>GenQTest.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\Common\Minimal\GenQTest.c</FilePath>
+            </File>
+            <File>
+              <FileName>PollQ.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\Common\Minimal\PollQ.c</FilePath>
+            </File>
+            <File>
+              <FileName>QPeek.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\Common\Minimal\QPeek.c</FilePath>
+            </File>
+            <File>
+              <FileName>recmutex.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\Common\Minimal\recmutex.c</FilePath>
+            </File>
+            <File>
+              <FileName>semtest.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\Common\Minimal\semtest.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>FreeRTOS_Source</GroupName>
+          <Files>
+            <File>
+              <FileName>timers.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\Source\timers.c</FilePath>
+            </File>
+            <File>
+              <FileName>list.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\Source\list.c</FilePath>
+            </File>
+            <File>
+              <FileName>queue.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\Source\queue.c</FilePath>
+            </File>
+            <File>
+              <FileName>tasks.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\Source\tasks.c</FilePath>
+            </File>
+            <File>
+              <FileName>port.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\Source\portable\RVDS\ARM_CM3\port.c</FilePath>
+            </File>
+            <File>
+              <FileName>heap_2.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\Source\portable\MemMang\heap_2.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>Demo_Source</GroupName>
+          <Files>
+            <File>
+              <FileName>serial.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\serial.c</FilePath>
+              <FileOption>
+                <CommonProperty>
+                  <UseCPPCompiler>2</UseCPPCompiler>
+                  <RVCTCodeConst>0</RVCTCodeConst>
+                  <RVCTZI>0</RVCTZI>
+                  <RVCTOtherData>0</RVCTOtherData>
+                  <ModuleSelection>0</ModuleSelection>
+                  <IncludeInBuild>1</IncludeInBuild>
+                  <AlwaysBuild>2</AlwaysBuild>
+                  <GenerateAssemblyFile>2</GenerateAssemblyFile>
+                  <AssembleAssemblyFile>2</AssembleAssemblyFile>
+                  <PublicsOnly>2</PublicsOnly>
+                  <StopOnExitCode>11</StopOnExitCode>
+                  <CustomArgument></CustomArgument>
+                  <IncludeLibraryModules></IncludeLibraryModules>
+                </CommonProperty>
+                <FileArmAds>
+                  <Cads>
+                    <interw>2</interw>
+                    <Optim>0</Optim>
+                    <oTime>2</oTime>
+                    <SplitLS>2</SplitLS>
+                    <OneElfS>2</OneElfS>
+                    <Strict>2</Strict>
+                    <EnumInt>2</EnumInt>
+                    <PlainCh>2</PlainCh>
+                    <Ropi>2</Ropi>
+                    <Rwpi>2</Rwpi>
+                    <wLevel>0</wLevel>
+                    <uThumb>2</uThumb>
+                    <VariousControls>
+                      <MiscControls></MiscControls>
+                      <Define></Define>
+                      <Undefine></Undefine>
+                      <IncludePath></IncludePath>
+                    </VariousControls>
+                  </Cads>
+                </FileArmAds>
+              </FileOption>
+            </File>
+            <File>
+              <FileName>main_blinky.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\main_blinky.c</FilePath>
+              <FileOption>
+                <CommonProperty>
+                  <UseCPPCompiler>2</UseCPPCompiler>
+                  <RVCTCodeConst>0</RVCTCodeConst>
+                  <RVCTZI>0</RVCTZI>
+                  <RVCTOtherData>0</RVCTOtherData>
+                  <ModuleSelection>0</ModuleSelection>
+                  <IncludeInBuild>0</IncludeInBuild>
+                  <AlwaysBuild>2</AlwaysBuild>
+                  <GenerateAssemblyFile>2</GenerateAssemblyFile>
+                  <AssembleAssemblyFile>2</AssembleAssemblyFile>
+                  <PublicsOnly>2</PublicsOnly>
+                  <StopOnExitCode>11</StopOnExitCode>
+                  <CustomArgument></CustomArgument>
+                  <IncludeLibraryModules></IncludeLibraryModules>
+                </CommonProperty>
+                <FileArmAds>
+                  <Cads>
+                    <interw>2</interw>
+                    <Optim>0</Optim>
+                    <oTime>2</oTime>
+                    <SplitLS>2</SplitLS>
+                    <OneElfS>2</OneElfS>
+                    <Strict>2</Strict>
+                    <EnumInt>2</EnumInt>
+                    <PlainCh>2</PlainCh>
+                    <Ropi>2</Ropi>
+                    <Rwpi>2</Rwpi>
+                    <wLevel>0</wLevel>
+                    <uThumb>2</uThumb>
+                    <VariousControls>
+                      <MiscControls></MiscControls>
+                      <Define></Define>
+                      <Undefine></Undefine>
+                      <IncludePath></IncludePath>
+                    </VariousControls>
+                  </Cads>
+                </FileArmAds>
+              </FileOption>
+            </File>
+            <File>
+              <FileName>main-full.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\main-full.c</FilePath>
+              <FileOption>
+                <CommonProperty>
+                  <UseCPPCompiler>2</UseCPPCompiler>
+                  <RVCTCodeConst>0</RVCTCodeConst>
+                  <RVCTZI>0</RVCTZI>
+                  <RVCTOtherData>0</RVCTOtherData>
+                  <ModuleSelection>0</ModuleSelection>
+                  <IncludeInBuild>1</IncludeInBuild>
+                  <AlwaysBuild>2</AlwaysBuild>
+                  <GenerateAssemblyFile>2</GenerateAssemblyFile>
+                  <AssembleAssemblyFile>2</AssembleAssemblyFile>
+                  <PublicsOnly>2</PublicsOnly>
+                  <StopOnExitCode>11</StopOnExitCode>
+                  <CustomArgument></CustomArgument>
+                  <IncludeLibraryModules></IncludeLibraryModules>
+                </CommonProperty>
+                <FileArmAds>
+                  <Cads>
+                    <interw>2</interw>
+                    <Optim>0</Optim>
+                    <oTime>2</oTime>
+                    <SplitLS>2</SplitLS>
+                    <OneElfS>2</OneElfS>
+                    <Strict>2</Strict>
+                    <EnumInt>2</EnumInt>
+                    <PlainCh>2</PlainCh>
+                    <Ropi>2</Ropi>
+                    <Rwpi>2</Rwpi>
+                    <wLevel>0</wLevel>
+                    <uThumb>2</uThumb>
+                    <VariousControls>
+                      <MiscControls></MiscControls>
+                      <Define></Define>
+                      <Undefine></Undefine>
+                      <IncludePath></IncludePath>
+                    </VariousControls>
+                  </Cads>
+                </FileArmAds>
+              </FileOption>
+            </File>
+            <File>
+              <FileName>ParTest.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\ParTest.c</FilePath>
+              <FileOption>
+                <CommonProperty>
+                  <UseCPPCompiler>2</UseCPPCompiler>
+                  <RVCTCodeConst>0</RVCTCodeConst>
+                  <RVCTZI>0</RVCTZI>
+                  <RVCTOtherData>0</RVCTOtherData>
+                  <ModuleSelection>0</ModuleSelection>
+                  <IncludeInBuild>1</IncludeInBuild>
+                  <AlwaysBuild>2</AlwaysBuild>
+                  <GenerateAssemblyFile>2</GenerateAssemblyFile>
+                  <AssembleAssemblyFile>2</AssembleAssemblyFile>
+                  <PublicsOnly>2</PublicsOnly>
+                  <StopOnExitCode>11</StopOnExitCode>
+                  <CustomArgument></CustomArgument>
+                  <IncludeLibraryModules></IncludeLibraryModules>
+                </CommonProperty>
+                <FileArmAds>
+                  <Cads>
+                    <interw>2</interw>
+                    <Optim>0</Optim>
+                    <oTime>2</oTime>
+                    <SplitLS>2</SplitLS>
+                    <OneElfS>2</OneElfS>
+                    <Strict>2</Strict>
+                    <EnumInt>2</EnumInt>
+                    <PlainCh>2</PlainCh>
+                    <Ropi>2</Ropi>
+                    <Rwpi>2</Rwpi>
+                    <wLevel>0</wLevel>
+                    <uThumb>2</uThumb>
+                    <VariousControls>
+                      <MiscControls></MiscControls>
+                      <Define></Define>
+                      <Undefine></Undefine>
+                      <IncludePath></IncludePath>
+                    </VariousControls>
+                  </Cads>
+                </FileArmAds>
+              </FileOption>
+            </File>
+          </Files>
+        </Group>
+      </Groups>
+    </Target>
+  </Targets>
+
+</Project>

diff --git a/Demo/CORTEX_MB9A310_IAR_Keil/config/Ram_VTOR.mac b/Demo/CORTEX_MB9A310_IAR_Keil/config/Ram_VTOR.mac
new file mode 100644 (file)
index 0000000..ebea508
--- /dev/null
+++ b/Demo/CORTEX_MB9A310_IAR_Keil/config/Ram_VTOR.mac
@@ -0,0 +1,15 @@
+execUserReset()\r
+{\r
+    __message("Executing __hwReset");\r
+    __hwReset(0);\r
+    __message("__hwReset done");\r
+     \r
+    __hwResetWithStrategy(0, 2);\r
+       \r
+       __writeMemory32(0x1FFFC000, 0xE000ED08, "Memory"); //Vector table remap at 0x1FFFC000\r
+}\r
+\r
+execUserPreload()\r
+{\r
+    __writeMemory32(0x1FFFC000, 0xE000ED08, "Memory"); //Vector table remap at 0x1FFFC000\r
+}\r

diff --git a/Demo/CORTEX_MB9A310_IAR_Keil/config/flashloader/FlashLoader.board b/Demo/CORTEX_MB9A310_IAR_Keil/config/flashloader/FlashLoader.board
new file mode 100644 (file)
index 0000000..cf5c2e7
--- /dev/null
+++ b/Demo/CORTEX_MB9A310_IAR_Keil/config/flashloader/FlashLoader.board
@@ -0,0 +1,9 @@
+<?xml version="1.0" encoding="iso-8859-1"?>\r
+\r
+<flash_board>\r
+  <pass>\r
+    <loader>$PROJ_DIR$\config\flashloader\FlashMB9A310.flash</loader>\r
+  </pass>\r
+</flash_board>\r
+\r
+\r

diff --git a/Demo/CORTEX_MB9A310_IAR_Keil/config/flashloader/FlashMB9A310.flash b/Demo/CORTEX_MB9A310_IAR_Keil/config/flashloader/FlashMB9A310.flash
new file mode 100644 (file)
index 0000000..e6be160
--- /dev/null
+++ b/Demo/CORTEX_MB9A310_IAR_Keil/config/flashloader/FlashMB9A310.flash
@@ -0,0 +1,19 @@
+<?xml version="1.0" encoding="iso-8859-1"?>\r
+\r
+<flash_device>\r
+  <exe>$PROJ_DIR$\config\flashloader\FlashMB9A310.out</exe>\r
+  <page>4</page>\r
+  <block>2 0x4000</block>\r
+  <block>1 0x18000</block>\r
+  <block>3 0x20000</block>\r
+  <flash_base>0x00000000</flash_base>\r
+  <macro>$PROJ_DIR$\config\flashloader\FlashMB9A310.mac</macro>\r
+  <aggregate>1</aggregate>\r
+  <args_doc>The "--protect" argument is used to program\r
+protection code 0x0001 in the security code area of the\r
+flash.\r
+Note: Writing the protection code disables JTAG access\r
+and debug is not possible. To release security, perform\r
+the chip erase operation using a serial writer because\r
+the security cannot be released through JTAG pins.</args_doc>\r
+</flash_device>\r

diff --git a/Demo/CORTEX_MB9A310_IAR_Keil/config/flashloader/FlashMB9A310.mac b/Demo/CORTEX_MB9A310_IAR_Keil/config/flashloader/FlashMB9A310.mac
new file mode 100644 (file)
index 0000000..6f5d648
--- /dev/null
+++ b/Demo/CORTEX_MB9A310_IAR_Keil/config/flashloader/FlashMB9A310.mac
@@ -0,0 +1,29 @@
+setup()\r
+{\r
+  /*Disable HWD*/\r
+  __writeMemory32(0x1ACCE551, 0x40011C00, "Memory"); //Unlock WDG_LCK = 0x1ACCE551\r
+  __writeMemory32(0xE5331AAE, 0x40011C00, "Memory"); //Unlock WDG_LCK = 0xE5331AAE\r
+  __writeMemory32(0x00000000, 0x40011008, "Memory"); //WDG_CTL = 0\r
+  /*Clock from High Speed internal Oscilator*/\r
+  __writeMemory32(__readMemory32(0x40010000, "Memory") & ~0xE0, 0x40010000, "Memory");\r
+  /*Wait*/ \r
+  __delay(5);\r
+  __emulatorSpeed(0);\r
+  /*Base Clock Prescaler Register*/\r
+  __writeMemory32(0, 0x40010010, "Memory"); \r
+\r
+  /*Vectors at RAM*/\r
+  __writeMemory32(0x1FFFE000, 0xE000ED08, "Memory"); //Vector table remap at 0x1FFFE000\r
+}\r
+\r
+execUserPreload()\r
+{\r
+  __message "----- Prepare hardware for Flashloader -----\n";\r
+  setup();\r
+}\r
+execUserFlashInit()  // Called by debugger before loading flash loader in RAM.\r
+{\r
+  __message "----- Prepare hardware for Flashloader -----\n";\r
+  setup();\r
+}\r
+\r

diff --git a/Demo/CORTEX_MB9A310_IAR_Keil/config/flashloader/FlashMB9A310.out b/Demo/CORTEX_MB9A310_IAR_Keil/config/flashloader/FlashMB9A310.out
new file mode 100644 (file)
index 0000000..92789e6
Binary files /dev/null and b/Demo/CORTEX_MB9A310_IAR_Keil/config/flashloader/FlashMB9A310.out differ

diff --git a/Demo/CORTEX_MB9A310_IAR_Keil/config/mb9af314.icf b/Demo/CORTEX_MB9A310_IAR_Keil/config/mb9af314.icf
new file mode 100644 (file)
index 0000000..76306c2
--- /dev/null
+++ b/Demo/CORTEX_MB9A310_IAR_Keil/config/mb9af314.icf
@@ -0,0 +1,31 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/\r
+/*-Editor annotation file-*/\r
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */\r
+/*-Specials-*/\r
+define symbol __ICFEDIT_intvec_start__ = 0x0;\r
+/*-Memory Regions-*/\r
+define symbol __ICFEDIT_region_ROM_start__ = 0x0;\r
+define symbol __ICFEDIT_region_ROM_end__   = 0x0003FFFF;\r
+define symbol __ICFEDIT_region_RAM_start__ = 0x1FFFC000;\r
+define symbol __ICFEDIT_region_RAM_end__   = 0x20003FFF;\r
+/*-Sizes-*/\r
+define symbol __ICFEDIT_size_cstack__ = 0x400;\r
+define symbol __ICFEDIT_size_heap__   = 0x800;\r
+/**** End of ICF editor section. ###ICF###*/\r
+\r
+\r
+define memory mem with size = 4G;\r
+define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];\r
+define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];\r
+\r
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };\r
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };\r
+\r
+initialize by copy { readwrite };\r
+do not initialize  { section .noinit };\r
+\r
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };\r
+\r
+place in ROM_region   { readonly };\r
+place in RAM_region   { readwrite,\r
+                        block CSTACK, block HEAP };\r

diff --git a/Demo/CORTEX_MB9A310_IAR_Keil/main-full.c b/Demo/CORTEX_MB9A310_IAR_Keil/main-full.c
new file mode 100644 (file)
index 0000000..3c738c6
--- /dev/null
+++ b/Demo/CORTEX_MB9A310_IAR_Keil/main-full.c
@@ -0,0 +1,674 @@
+/*\r
+    FreeRTOS V7.0.1 - Copyright (C) 2011 Real Time Engineers Ltd.\r
+\r
+\r
+       FreeRTOS supports many tools and architectures. V7.0.0 is sponsored by:\r
+       Atollic AB - Atollic provides professional embedded systems development\r
+       tools for C/C++ development, code analysis and test automation.\r
+       See http://www.atollic.com\r
+\r
+\r
+    ***************************************************************************\r
+     *                                                                       *\r
+     *    FreeRTOS tutorial books are available in pdf and paperback.        *\r
+     *    Complete, revised, and edited pdf reference manuals are also       *\r
+     *    available.                                                         *\r
+     *                                                                       *\r
+     *    Purchasing FreeRTOS documentation will not only help you, by       *\r
+     *    ensuring you get running as quickly as possible and with an        *\r
+     *    in-depth knowledge of how to use FreeRTOS, it will also help       *\r
+     *    the FreeRTOS project to continue with its mission of providing     *\r
+     *    professional grade, cross platform, de facto standard solutions    *\r
+     *    for microcontrollers - completely free of charge!                  *\r
+     *                                                                       *\r
+     *    >>> See http://www.FreeRTOS.org/Documentation for details. <<<     *\r
+     *                                                                       *\r
+     *    Thank you for using FreeRTOS, and thank you for your support!      *\r
+     *                                                                       *\r
+    ***************************************************************************\r
+\r
+\r
+    This file is part of the FreeRTOS distribution.\r
+\r
+    FreeRTOS is free software; you can redistribute it and/or modify it under\r
+    the terms of the GNU General Public License (version 2) as published by the\r
+    Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+    >>>NOTE<<< The modification to the GPL is included to allow you to\r
+    distribute a combined work that includes FreeRTOS without being obliged to\r
+    provide the source code for proprietary components outside of the FreeRTOS\r
+    kernel.  FreeRTOS is distributed in the hope that it will be useful, but\r
+    WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\r
+    more details. You should have received a copy of the GNU General Public\r
+    License and the FreeRTOS license exception along with FreeRTOS; if not it\r
+    can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
+    by writing to Richard Barry, contact details for whom are available on the\r
+    FreeRTOS WEB site.\r
+\r
+    1 tab == 4 spaces!\r
+\r
+    http://www.FreeRTOS.org - Documentation, latest information, license and\r
+    contact details.\r
+\r
+    http://www.SafeRTOS.com - A version that is certified for use in safety\r
+    critical systems.\r
+\r
+    http://www.OpenRTOS.com - Commercial support, development, porting,\r
+    licensing and training services.\r
+*/\r
+\r
+/*\r
+ * main-blinky.c is included when the "Blinky" build configuration is used.\r
+ * main-full.c is included when the "Full" build configuration is used.\r
+ *\r
+ * main-full.c (this file) defines a comprehensive demo that creates many\r
+ * tasks, queues, semaphores and timers.  It also demonstrates how Cortex-M3\r
+ * interrupts can interact with FreeRTOS tasks/timers.\r
+ *\r
+ * This project runs on the SK-FM3-100PMC evaluation board, which is populated\r
+ * with an MB9BF5006N Cortex-M3 based microcontroller.\r
+ *\r
+ * The main() Function:\r
+ * main() creates three demo specific software timers, one demo specific queue,\r
+ * and two demo specific tasks.  It then creates a whole host of 'standard\r
+ * demo' tasks/queues/semaphores, before starting the scheduler.  The demo\r
+ * specific tasks and timers are described in the comments here.  The standard\r
+ * demo tasks are described on the FreeRTOS.org web site.\r
+ *\r
+ * The standard demo tasks provide no specific functionality.  They are\r
+ * included to both test the FreeRTOS port, and provide examples of how the\r
+ * various FreeRTOS API functions can be used.\r
+ *\r
+ * This demo creates 43 tasks in total.  If you want a simpler demo, use the\r
+ * Blinky build configuration.\r
+ *\r
+ * The Demo Specific Queue Send Task:\r
+ * The queue send task is implemented by the prvQueueSendTask() function in\r
+ * this file.  prvQueueSendTask() sits in a loop that causes it to repeatedly\r
+ * block for 200 milliseconds, before sending the value 100 to the queue that\r
+ * was created within main().  Once the value is sent, the task loops back\r
+ * around to block for another 200 milliseconds.\r
+ *\r
+ * The Demo Specific Queue Receive Task:\r
+ * The queue receive task is implemented by the prvQueueReceiveTask() function\r
+ * in this file.  prvQueueReceiveTask() sits in a loop that causes it to\r
+ * repeatedly attempt to read data from the queue that was created within\r
+ * main().  When data is received, the task checks the value of the data, and\r
+ * if the value equals the expected 100, toggles an LED in the 7 segment display\r
+ * (see the documentation page for this demo on the FreeRTOS.org site to see\r
+ * which LED is used).  The 'block time' parameter passed to the queue receive\r
+ * function specifies that the task should be held in the Blocked state\r
+ * indefinitely to wait for data to be available on the queue.  The queue\r
+ * receive task will only leave the Blocked state when the queue send task\r
+ * writes to the queue.  As the queue send task writes to the queue every 200\r
+ * milliseconds, the queue receive task leaves the Blocked state every 200\r
+ * milliseconds, and therefore toggles the LED every 200 milliseconds.\r
+ *\r
+ * The Demo Specific LED Software Timer and the Button Interrupt:\r
+ * The user button SW2 is configured to generate an interrupt each time it is\r
+ * pressed.  The interrupt service routine switches an LED on, and resets the\r
+ * LED software timer.  The LED timer has a 5000 millisecond (5 second) period,\r
+ * and uses a callback function that is defined to just turn the LED off again.\r
+ * Therefore, pressing the user button will turn the LED on, and the LED will\r
+ * remain on until a full five seconds pass without the button being pressed.\r
+ * See the documentation page for this demo on the FreeRTOS.org web site to see\r
+ * which LED is used.\r
+ *\r
+ * The Demo Specific "Check" Callback Function:\r
+ * This is called each time the 'check' timer expires.  The check timer\r
+ * callback function inspects all the standard demo tasks to see if they are\r
+ * all executing as expected.  The check timer is initially configured to\r
+ * expire every three seconds, but will shorted this to every 500ms if an error\r
+ * is ever discovered.  The check timer callback toggles the LED defined by\r
+ * the mainCHECK_LED definition each time it executes.  Therefore, if LED\r
+ * mainCHECK_LED is toggling every three seconds, then no error have been found.\r
+ * If LED mainCHECK_LED is toggling every 500ms, then at least one errors has\r
+ * been found.  The variable pcStatusMessage is set to a string that indicates\r
+ * which task reported an error.  See the documentation page for this demo on\r
+ * the FreeRTOS.org web site to see which LED in the 7 segment display is used.\r
+ *\r
+ * The Demo Specific "Digit Counter" Callback Function:\r
+ * This is called each time the 'digit counter' timer expires.  It causes the\r
+ * digits 0 to 9 to be displayed in turn as the first character of the two\r
+ * character display.  The LEDs in the other digit of the two character\r
+ * display are used as general purpose LEDs, as described in this comment block.\r
+ *\r
+ * The Demo Specific Idle Hook Function:\r
+ * The idle hook function demonstrates how to query the amount of FreeRTOS heap\r
+ * space that is remaining (see vApplicationIdleHook() defined in this file).\r
+ *\r
+ * The Demo Specific Tick Hook Function:\r
+ * The tick hook function is used to test the interrupt safe software timer\r
+ * functionality.\r
+ */\r
+\r
+/* Kernel includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "queue.h"\r
+#include "timers.h"\r
+\r
+/* Fujitsu drivers/libraries. */\r
+#include "mcu.h"\r
+\r
+/* Common demo includes. */\r
+#include "partest.h"\r
+#include "flash.h"\r
+#include "BlockQ.h"\r
+#include "death.h"\r
+#include "blocktim.h"\r
+#include "semtest.h"\r
+#include "GenQTest.h"\r
+#include "QPeek.h"\r
+#include "recmutex.h"\r
+#include "TimerDemo.h"\r
+#include "comtest2.h"\r
+#include "PollQ.h"\r
+#include "countsem.h"\r
+#include "dynamic.h"\r
+\r
+/* The rate at which data is sent to the queue, specified in milliseconds, and\r
+converted to ticks using the portTICK_RATE_MS constant. */\r
+#define mainQUEUE_SEND_FREQUENCY_MS    ( 200 / portTICK_RATE_MS )\r
+\r
+/* The number of items the queue can hold.  This is 1 as the receive task\r
+will remove items as they are added, meaning the send task should always find\r
+the queue empty. */\r
+#define mainQUEUE_LENGTH                       ( 1 )\r
+\r
+/* The LED toggled by the check timer callback function.  This is an LED in the\r
+second digit of the two digit 7 segment display.  See the documentation page\r
+for this demo on the FreeRTOS.org web site to see which LED this relates to. */\r
+#define mainCHECK_LED                          ( 1UL << 3UL )\r
+\r
+/* The LED toggle by the queue receive task.  This is an LED in the second digit\r
+of the two digit 7 segment display.  See the documentation page for this demo on\r
+the FreeRTOS.org web site to see which LED this relates to. */\r
+#define mainTASK_CONTROLLED_LED                0x07UL\r
+\r
+/* The LED turned on by the button interrupt, and turned off by the LED timer.\r
+This is an LED in the second digit of the two digit 7 segment display.  See the\r
+documentation page for this demo on the FreeRTOS.org web site to see which LED\r
+this relates to. */\r
+#define mainTIMER_CONTROLLED_LED       0x05UL\r
+\r
+/* The LED used by the comtest tasks. See the comtest.c file for more\r
+information.  The LEDs used by the comtest task are in the second digit of the\r
+two digit 7 segment display.  See the documentation page for this demo on the\r
+FreeRTOS.org web site to see which LEDs this relates to. */\r
+#define mainCOM_TEST_LED                       0x03UL\r
+\r
+/* Constant used by the standard timer test functions. */\r
+#define mainTIMER_TEST_PERIOD          ( 50 )\r
+\r
+/* Priorities used by the various different standard demo tasks. */\r
+#define mainCHECK_TASK_PRIORITY                ( configMAX_PRIORITIES - 1 )\r
+#define mainQUEUE_POLL_PRIORITY                ( tskIDLE_PRIORITY + 1 )\r
+#define mainSEM_TEST_PRIORITY          ( tskIDLE_PRIORITY + 1 )\r
+#define mainBLOCK_Q_PRIORITY           ( tskIDLE_PRIORITY + 2 )\r
+#define mainCREATOR_TASK_PRIORITY   ( tskIDLE_PRIORITY + 3 )\r
+#define mainFLASH_TASK_PRIORITY                ( tskIDLE_PRIORITY + 1 )\r
+#define mainINTEGER_TASK_PRIORITY   ( tskIDLE_PRIORITY )\r
+#define mainGEN_QUEUE_TASK_PRIORITY    ( tskIDLE_PRIORITY )\r
+#define mainCOM_TEST_PRIORITY          ( tskIDLE_PRIORITY + 2 )\r
+\r
+/* Priorities defined in this main-full.c file. */\r
+#define mainQUEUE_RECEIVE_TASK_PRIORITY                ( tskIDLE_PRIORITY + 2 )\r
+#define        mainQUEUE_SEND_TASK_PRIORITY            ( tskIDLE_PRIORITY + 1 )\r
+\r
+/* The period at which the check timer will expire, in ms, provided no errors\r
+have been reported by any of the standard demo tasks.  ms are converted to the\r
+equivalent in ticks using the portTICK_RATE_MS constant. */\r
+#define mainCHECK_TIMER_PERIOD_MS                      ( 3000UL / portTICK_RATE_MS )\r
+\r
+/* The period at which the check timer will expire, in ms, if an error has been\r
+reported in one of the standard demo tasks.  ms are converted to the equivalent\r
+in ticks using the portTICK_RATE_MS constant. */\r
+#define mainERROR_CHECK_TIMER_PERIOD_MS        ( 500UL / portTICK_RATE_MS )\r
+\r
+/* The period at which the digit counter timer will expire, in ms, and converted\r
+to ticks using the portTICK_RATE_MS constant. */\r
+#define mainDIGIT_COUNTER_TIMER_PERIOD_MS      ( 250UL / portTICK_RATE_MS )\r
+\r
+/* The LED will remain on until the button has not been pushed for a full\r
+5000ms. */\r
+#define mainLED_TIMER_PERIOD_MS                                ( 5000UL / portTICK_RATE_MS )\r
+\r
+/* A zero block time. */\r
+#define mainDONT_BLOCK                                         ( 0UL )\r
+\r
+/* Baud rate used by the comtest tasks. */\r
+#define mainCOM_TEST_BAUD_RATE                         ( 115200UL )\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Setup the NVIC, LED outputs, and button inputs.\r
+ */\r
+static void prvSetupHardware( void );\r
+\r
+/*\r
+ * The application specific (not common demo) tasks as described in the comments\r
+ * at the top of this file.\r
+ */\r
+static void prvQueueReceiveTask( void *pvParameters );\r
+static void prvQueueSendTask( void *pvParameters );\r
+\r
+/*\r
+ * The LED timer callback function.  This does nothing but switch an LED off.\r
+ */\r
+static void prvLEDTimerCallback( xTimerHandle xTimer );\r
+\r
+/*\r
+ * The check timer callback function, as described at the top of this file.\r
+ */\r
+static void prvCheckTimerCallback( xTimerHandle xTimer );\r
+\r
+/*\r
+ * The digit counter callback function, as described at the top of this file.\r
+ */\r
+static void prvDigitCounterTimerCallback( xTimerHandle xTimer );\r
+\r
+/*\r
+ * This is not a 'standard' partest function, so the prototype is not in\r
+ * partest.h, and is instead included here.\r
+ */\r
+void vParTestSetLEDFromISR( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* The queue used by both application specific demo tasks defined in this file. */\r
+static xQueueHandle xQueue = NULL;\r
+\r
+/* The LED software timer.  This uses prvLEDTimerCallback() as it's callback\r
+function. */\r
+static xTimerHandle xLEDTimer = NULL;\r
+\r
+/* The digit counter software timer.  This displays a counting digit on one half\r
+of the seven segment displays. */\r
+static xTimerHandle xDigitCounterTimer = NULL;\r
+\r
+/* The check timer.  This uses prvCheckTimerCallback() as its callback\r
+function. */\r
+static xTimerHandle xCheckTimer = NULL;\r
+\r
+/* If an error is detected in a standard demo task, then pcStatusMessage will\r
+be set to point to a string that identifies the offending task.  This is just\r
+to make debugging easier. */\r
+static const char *pcStatusMessage = NULL;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+int main(void)\r
+{\r
+       /* Configure the NVIC, LED outputs and button inputs. */\r
+       prvSetupHardware();\r
+\r
+       /* Create the queue. */\r
+       xQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( unsigned long ) );\r
+\r
+       if( xQueue != NULL )\r
+       {\r
+               /* Start the two application specific demo tasks, as described in the\r
+               comments at the top of this     file. */\r
+               xTaskCreate( prvQueueReceiveTask, ( signed char * ) "Rx", configMINIMAL_STACK_SIZE, NULL, mainQUEUE_RECEIVE_TASK_PRIORITY, NULL );\r
+               xTaskCreate( prvQueueSendTask, ( signed char * ) "TX", configMINIMAL_STACK_SIZE, NULL, mainQUEUE_SEND_TASK_PRIORITY, NULL );\r
+\r
+               /* Create the software timer that is responsible for turning off the LED\r
+               if the button is not pushed within 5000ms, as described at the top of\r
+               this file. */\r
+               xLEDTimer = xTimerCreate(       ( const signed char * ) "LEDTimer", /* A text name, purely to help debugging. */\r
+                                                                       ( mainLED_TIMER_PERIOD_MS ),            /* The timer period, in this case 5000ms (5s). */\r
+                                                                       pdFALSE,                                                        /* This is a one shot timer, so xAutoReload is set to pdFALSE. */\r
+                                                                       ( void * ) 0,                                           /* The ID is not used, so can be set to anything. */\r
+                                                                       prvLEDTimerCallback                                     /* The callback function that switches the LED off. */\r
+                                                               );\r
+\r
+               /* Create the software timer that performs the 'check' functionality,\r
+               as described at the top of this file. */\r
+               xCheckTimer = xTimerCreate( ( const signed char * ) "CheckTimer",/* A text name, purely to help debugging. */\r
+                                                                       ( mainCHECK_TIMER_PERIOD_MS ),          /* The timer period, in this case 3000ms (3s). */\r
+                                                                       pdTRUE,                                                         /* This is an auto-reload timer, so xAutoReload is set to pdTRUE. */\r
+                                                                       ( void * ) 0,                                           /* The ID is not used, so can be set to anything. */\r
+                                                                       prvCheckTimerCallback                           /* The callback function that inspects the status of all the other tasks. */\r
+                                                                 );\r
+\r
+               /* Create the software timer that performs the 'digit counting'\r
+               functionality, as described at the top of this file. */\r
+               xDigitCounterTimer = xTimerCreate( ( const signed char * ) "DigitCounter",      /* A text name, purely to help debugging. */\r
+                                                                       ( mainDIGIT_COUNTER_TIMER_PERIOD_MS ),                  /* The timer period, in this case 3000ms (3s). */\r
+                                                                       pdTRUE,                                                                                 /* This is an auto-reload timer, so xAutoReload is set to pdTRUE. */\r
+                                                                       ( void * ) 0,                                                                   /* The ID is not used, so can be set to anything. */\r
+                                                                       prvDigitCounterTimerCallback                                    /* The callback function that inspects the status of all the other tasks. */\r
+                                                                 );            \r
+               \r
+               /* Create a lot of 'standard demo' tasks.  Over 40 tasks are created in\r
+               this demo.  For a much simpler demo, select the 'blinky' build\r
+               configuration. */\r
+               vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY );\r
+               vCreateBlockTimeTasks();\r
+               vStartSemaphoreTasks( mainSEM_TEST_PRIORITY );\r
+               vStartGenericQueueTasks( mainGEN_QUEUE_TASK_PRIORITY );\r
+               vStartLEDFlashTasks( mainFLASH_TASK_PRIORITY );\r
+               vStartQueuePeekTasks();\r
+               vStartRecursiveMutexTasks();\r
+               vStartTimerDemoTask( mainTIMER_TEST_PERIOD );\r
+               vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainCOM_TEST_BAUD_RATE, mainCOM_TEST_LED );\r
+               vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY );\r
+               vStartCountingSemaphoreTasks();\r
+               vStartDynamicPriorityTasks();\r
+               \r
+               /* The suicide tasks must be created last, as they need to know how many\r
+               tasks were running prior to their creation in order to ascertain whether\r
+               or not the correct/expected number of tasks are running at any given\r
+               time. */\r
+               vCreateSuicidalTasks( mainCREATOR_TASK_PRIORITY );\r
+\r
+               /* Start the tasks and timer running. */\r
+               vTaskStartScheduler();\r
+       }\r
+\r
+       /* If all is well, the scheduler will now be running, and the following line\r
+       will never be reached.  If the following line does execute, then there was\r
+       insufficient FreeRTOS heap memory available for the idle and/or timer tasks\r
+       to be created.  See the memory management section on the FreeRTOS web site\r
+       for more details. */\r
+       for( ;; );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvCheckTimerCallback( xTimerHandle xTimer )\r
+{\r
+       /* Check the standard demo tasks are running without error.   Latch the\r
+       latest reported error in the pcStatusMessage character pointer. */\r
+       if( xAreGenericQueueTasksStillRunning() != pdTRUE )\r
+       {\r
+               pcStatusMessage = "Error: GenQueue";\r
+       }\r
+\r
+       if( xAreQueuePeekTasksStillRunning() != pdTRUE )\r
+       {\r
+               pcStatusMessage = "Error: QueuePeek\r\n";\r
+       }\r
+\r
+       if( xAreBlockingQueuesStillRunning() != pdTRUE )\r
+       {\r
+               pcStatusMessage = "Error: BlockQueue\r\n";\r
+       }\r
+\r
+       if( xAreBlockTimeTestTasksStillRunning() != pdTRUE )\r
+       {\r
+               pcStatusMessage = "Error: BlockTime\r\n";\r
+       }\r
+\r
+       if( xAreSemaphoreTasksStillRunning() != pdTRUE )\r
+       {\r
+               pcStatusMessage = "Error: SemTest\r\n";\r
+       }\r
+\r
+       if( xIsCreateTaskStillRunning() != pdTRUE )\r
+       {\r
+               pcStatusMessage = "Error: Death\r\n";\r
+       }\r
+\r
+       if( xAreRecursiveMutexTasksStillRunning() != pdTRUE )\r
+       {\r
+               pcStatusMessage = "Error: RecMutex\r\n";\r
+       }\r
+\r
+       if( xAreComTestTasksStillRunning() != pdPASS )\r
+       {\r
+               pcStatusMessage = "Error: ComTest\r\n";\r
+       }\r
+       \r
+       if( xAreTimerDemoTasksStillRunning( ( mainCHECK_TIMER_PERIOD_MS ) ) != pdTRUE )\r
+       {\r
+               pcStatusMessage = "Error: TimerDemo";\r
+       }\r
+\r
+       if( xArePollingQueuesStillRunning() != pdTRUE )\r
+       {\r
+               pcStatusMessage = "Error: PollQueue";\r
+       }\r
+\r
+       if( xAreCountingSemaphoreTasksStillRunning() != pdTRUE )\r
+       {\r
+               pcStatusMessage = "Error: CountSem";\r
+       }\r
+       \r
+       if( xAreDynamicPriorityTasksStillRunning() != pdTRUE )\r
+       {\r
+               pcStatusMessage = "Error: DynamicPriority";\r
+       }\r
+       \r
+       /* Toggle the check LED to give an indication of the system status.  If\r
+       the LED toggles every mainCHECK_TIMER_PERIOD_MS milliseconds then\r
+       everything is ok.  A faster toggle indicates an error.  vParTestToggleLED()\r
+       is not used to toggle this particular LED as it is on a different IP port\r
+       to to the LEDs controlled by ParTest.c.  A critical section is not required\r
+       as the only other place this port is accessed is from another timer - and\r
+       only one timer can be running at any one time. */\r
+       if( ( FM3_GPIO->PDOR3 & mainCHECK_LED ) != 0 )\r
+       {\r
+               FM3_GPIO->PDOR3 &= ~mainCHECK_LED;\r
+       }\r
+       else\r
+       {\r
+               FM3_GPIO->PDOR3 |= mainCHECK_LED;\r
+       }\r
+\r
+       /* Have any errors been latch in pcStatusMessage?  If so, shorten the\r
+       period of the check timer to mainERROR_CHECK_TIMER_PERIOD_MS milliseconds.\r
+       This will result in an increase in the rate at which mainCHECK_LED\r
+       toggles. */\r
+       if( pcStatusMessage != NULL )\r
+       {\r
+               /* This call to xTimerChangePeriod() uses a zero block time.  Functions\r
+               called from inside of a timer callback function must *never* attempt\r
+               to block. */\r
+               xTimerChangePeriod( xCheckTimer, ( mainERROR_CHECK_TIMER_PERIOD_MS ), mainDONT_BLOCK );\r
+       }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvLEDTimerCallback( xTimerHandle xTimer )\r
+{\r
+       /* The timer has expired - so no button pushes have occurred in the last\r
+       five seconds - turn the LED off. */\r
+       vParTestSetLED( mainTIMER_CONTROLLED_LED, pdFALSE );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvDigitCounterTimerCallback( xTimerHandle xTimer )\r
+{\r
+/* Define the bit patterns that display numbers on the seven segment display. */\r
+static const unsigned short usNumbersPatterns[] = { 0x8004, 0xF204, 0x4804, 0x6004, 0x3204, 0x2404, 0x0404, 0xF104, 0x0004, 0x2004 };\r
+static long lCounter = 0L;\r
+const long lNumberOfDigits = 10L;\r
+unsigned short usCheckLEDState;\r
+\r
+       /* Unfortunately the LED uses the same port as the digit counter, so remember\r
+       the state of the check LED.  A critical section is not required to access\r
+       the port as only one timer can be executing at any one time. */\r
+       usCheckLEDState = ( FM3_GPIO->PDOR3 & mainCHECK_LED );\r
+       \r
+       /* Display the next number, counting up. */\r
+       FM3_GPIO->PDOR3 = usNumbersPatterns[ lCounter ] | usCheckLEDState;\r
+\r
+       /* Move onto the next digit. */ \r
+       lCounter++;\r
+       \r
+       /* Ensure the counter does not go off the end of the array. */\r
+       if( lCounter >= lNumberOfDigits )\r
+       {\r
+               lCounter = 0L;\r
+       }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* The ISR executed when the user button is pushed. */\r
+void INT0_7_Handler( void )\r
+{\r
+portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE;\r
+\r
+       /* The button was pushed, so ensure the LED is on before resetting the\r
+       LED timer.  The LED timer will turn the LED off if the button is not\r
+       pushed within 5000ms. */\r
+       vParTestSetLEDFromISR( mainTIMER_CONTROLLED_LED, pdTRUE );\r
+\r
+       /* This interrupt safe FreeRTOS function can be called from this interrupt\r
+       because the interrupt priority is below the\r
+       configMAX_SYSCALL_INTERRUPT_PRIORITY setting in FreeRTOSConfig.h. */\r
+       xTimerResetFromISR( xLEDTimer, &xHigherPriorityTaskWoken );\r
+\r
+       /* Clear the interrupt before leaving.  This just clears all the interrupts\r
+       for simplicity, as only one is actually used in this simple demo anyway. */\r
+       FM3_EXTI->EICL = 0x0000;\r
+\r
+       /* If calling xTimerResetFromISR() caused a task (in this case the timer\r
+       service/daemon task) to unblock, and the unblocked task has a priority\r
+       higher than or equal to the task that was interrupted, then\r
+       xHigherPriorityTaskWoken will now be set to pdTRUE, and calling\r
+       portEND_SWITCHING_ISR() will ensure the unblocked task runs next. */\r
+       portEND_SWITCHING_ISR( xHigherPriorityTaskWoken );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvQueueSendTask( void *pvParameters )\r
+{\r
+portTickType xNextWakeTime;\r
+const unsigned long ulValueToSend = 100UL;\r
+\r
+       /* The timer command queue will have been filled when the timer test tasks\r
+       were created in main() (this is part of the test they perform).  Therefore,\r
+       while the check and digit counter timers can be created in main(), they\r
+       cannot be started from main().  Once the scheduler has started, the timer\r
+       service task will drain the command queue, and now the check and digit\r
+       counter timers can be started successfully. */\r
+       xTimerStart( xCheckTimer, portMAX_DELAY );\r
+       xTimerStart( xDigitCounterTimer, portMAX_DELAY );\r
+\r
+       /* Initialise xNextWakeTime - this only needs to be done once. */\r
+       xNextWakeTime = xTaskGetTickCount();\r
+\r
+       for( ;; )\r
+       {\r
+               /* Place this task in the blocked state until it is time to run again.\r
+               The block time is specified in ticks, the constant used converts ticks\r
+               to ms.  While in the Blocked state this task will not consume any CPU\r
+               time. */\r
+               vTaskDelayUntil( &xNextWakeTime, mainQUEUE_SEND_FREQUENCY_MS );\r
+\r
+               /* Send to the queue - causing the queue receive task to unblock and\r
+               toggle an LED.  0 is used as the block time so the sending operation\r
+               will not block - it shouldn't need to block as the queue should always\r
+               be empty at this point in the code. */\r
+               xQueueSend( xQueue, &ulValueToSend, mainDONT_BLOCK );\r
+       }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvQueueReceiveTask( void *pvParameters )\r
+{\r
+unsigned long ulReceivedValue;\r
+\r
+       for( ;; )\r
+       {\r
+               /* Wait until something arrives in the queue - this task will block\r
+               indefinitely provided INCLUDE_vTaskSuspend is set to 1 in\r
+               FreeRTOSConfig.h. */\r
+               xQueueReceive( xQueue, &ulReceivedValue, portMAX_DELAY );\r
+\r
+               /*  To get here something must have been received from the queue, but\r
+               is it the expected value?  If it is, toggle the LED. */\r
+               if( ulReceivedValue == 100UL )\r
+               {\r
+                       vParTestToggleLED( mainTASK_CONTROLLED_LED );\r
+               }\r
+       }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvSetupHardware( void )\r
+{\r
+const unsigned short usButtonInputBit = 0x01U;\r
+\r
+       SystemInit();\r
+       SystemCoreClockUpdate();\r
+\r
+       /* Initialise the IO used for the LEDs on the 7 segment displays. */\r
+       vParTestInitialise();   \r
+       \r
+       /* Set the switches to input (P18->P1F). */\r
+       FM3_GPIO->DDR5 = 0x0000;\r
+       FM3_GPIO->PFR5 = 0x0000;\r
+\r
+       /* Assign the button input as GPIO. */\r
+       FM3_GPIO->PFR1 |= usButtonInputBit;\r
+       \r
+       /* Button interrupt on falling edge. */\r
+       FM3_EXTI->ELVR  = 0x0003;\r
+\r
+       /* Clear all external interrupts. */\r
+       FM3_EXTI->EICL  = 0x0000;\r
+\r
+       /* Enable the button interrupt. */\r
+       FM3_EXTI->ENIR |= usButtonInputBit;\r
+       \r
+       /* Setup the GPIO and the NVIC for the switch used in this simple demo. */\r
+       NVIC_SetPriority( EXINT0_7_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );\r
+    NVIC_EnableIRQ( EXINT0_7_IRQn );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationMallocFailedHook( void )\r
+{\r
+       /* Called if a call to pvPortMalloc() fails because there is insufficient\r
+       free memory available in the FreeRTOS heap.  pvPortMalloc() is called\r
+       internally by FreeRTOS API functions that create tasks, queues, software\r
+       timers, and semaphores.  The size of the FreeRTOS heap is set by the\r
+       configTOTAL_HEAP_SIZE configuration constant in FreeRTOSConfig.h. */\r
+       for( ;; );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationStackOverflowHook( xTaskHandle *pxTask, signed char *pcTaskName )\r
+{\r
+       ( void ) pcTaskName;\r
+       ( void ) pxTask;\r
+\r
+       /* Run time stack overflow checking is performed if\r
+       configconfigCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2.  This hook\r
+       function is called if a stack overflow is detected. */\r
+       taskDISABLE_INTERRUPTS();\r
+       for( ;; );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationIdleHook( void )\r
+{\r
+volatile size_t xFreeStackSpace;\r
+\r
+       /* This function is called on each cycle of the idle task.  In this case it\r
+       does nothing useful, other than report the amount of FreeRTOS heap that\r
+       remains unallocated. */\r
+       xFreeStackSpace = xPortGetFreeHeapSize();\r
+\r
+       if( xFreeStackSpace > 100 )\r
+       {\r
+               /* By now, the kernel has allocated everything it is going to, so\r
+               if there is a lot of heap remaining unallocated then\r
+               the value of configTOTAL_HEAP_SIZE in FreeRTOSConfig.h can be\r
+               reduced accordingly. */\r
+       }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationTickHook( void )\r
+{\r
+       /* Call the periodic timer test, which tests the timer API functions that\r
+       can be called from an ISR. */\r
+       vTimerPeriodicISRTests();\r
+}      \r
+/*-----------------------------------------------------------*/\r
+\r

diff --git a/Demo/CORTEX_MB9A310_IAR_Keil/main_blinky.c b/Demo/CORTEX_MB9A310_IAR_Keil/main_blinky.c
new file mode 100644 (file)
index 0000000..7a3fae2
--- /dev/null
+++ b/Demo/CORTEX_MB9A310_IAR_Keil/main_blinky.c
@@ -0,0 +1,399 @@
+/*\r
+    FreeRTOS V7.0.1 - Copyright (C) 2011 Real Time Engineers Ltd.\r
+\r
+\r
+       FreeRTOS supports many tools and architectures. V7.0.0 is sponsored by:\r
+       Atollic AB - Atollic provides professional embedded systems development\r
+       tools for C/C++ development, code analysis and test automation.\r
+       See http://www.atollic.com\r
+\r
+\r
+    ***************************************************************************\r
+     *                                                                       *\r
+     *    FreeRTOS tutorial books are available in pdf and paperback.        *\r
+     *    Complete, revised, and edited pdf reference manuals are also       *\r
+     *    available.                                                         *\r
+     *                                                                       *\r
+     *    Purchasing FreeRTOS documentation will not only help you, by       *\r
+     *    ensuring you get running as quickly as possible and with an        *\r
+     *    in-depth knowledge of how to use FreeRTOS, it will also help       *\r
+     *    the FreeRTOS project to continue with its mission of providing     *\r
+     *    professional grade, cross platform, de facto standard solutions    *\r
+     *    for microcontrollers - completely free of charge!                  *\r
+     *                                                                       *\r
+     *    >>> See http://www.FreeRTOS.org/Documentation for details. <<<     *\r
+     *                                                                       *\r
+     *    Thank you for using FreeRTOS, and thank you for your support!      *\r
+     *                                                                       *\r
+    ***************************************************************************\r
+\r
+\r
+    This file is part of the FreeRTOS distribution.\r
+\r
+    FreeRTOS is free software; you can redistribute it and/or modify it under\r
+    the terms of the GNU General Public License (version 2) as published by the\r
+    Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+    >>>NOTE<<< The modification to the GPL is included to allow you to\r
+    distribute a combined work that includes FreeRTOS without being obliged to\r
+    provide the source code for proprietary components outside of the FreeRTOS\r
+    kernel.  FreeRTOS is distributed in the hope that it will be useful, but\r
+    WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\r
+    more details. You should have received a copy of the GNU General Public\r
+    License and the FreeRTOS license exception along with FreeRTOS; if not it\r
+    can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
+    by writing to Richard Barry, contact details for whom are available on the\r
+    FreeRTOS WEB site.\r
+\r
+    1 tab == 4 spaces!\r
+\r
+    http://www.FreeRTOS.org - Documentation, latest information, license and\r
+    contact details.\r
+\r
+    http://www.SafeRTOS.com - A version that is certified for use in safety\r
+    critical systems.\r
+\r
+    http://www.OpenRTOS.com - Commercial support, development, porting,\r
+    licensing and training services.\r
+*/\r
+\r
+/*\r
+ * main-blinky.c is included when the "Blinky" build configuration is used.\r
+ * main-full.c is included when the "Full" build configuration is used.\r
+ *\r
+ * main-blinky.c (this file) defines a very simple demo that creates two tasks,\r
+ * one queue, and one timer.  It also demonstrates how Cortex-M3 interrupts can\r
+ * interact with FreeRTOS tasks/timers.\r
+ *\r
+ * This simple demo project runs on the SK-FM3-64PMC1 evaluation board, which\r
+ * is populated with an MB9A300 microcontroller.\r
+ *\r
+ * The idle hook function:\r
+ * The idle hook function demonstrates how to query the amount of FreeRTOS heap\r
+ * space that is remaining (see vApplicationIdleHook() defined in this file).\r
+ *\r
+ * The main() Function:\r
+ * main() creates one software timer, one queue, and two tasks.  It then starts\r
+ * the scheduler.\r
+ *\r
+ * The Queue Send Task:\r
+ * The queue send task is implemented by the prvQueueSendTask() function in\r
+ * this file.  prvQueueSendTask() sits in a loop that causes it to repeatedly\r
+ * block for 200 milliseconds, before sending the value 100 to the queue that\r
+ * was created within main().  Once the value is sent, the task loops back\r
+ * around to block for another 200 milliseconds.\r
+ *\r
+ * The Queue Receive Task:\r
+ * The queue receive task is implemented by the prvQueueReceiveTask() function\r
+ * in this file.  prvQueueReceiveTask() sits in a loop that causes it to\r
+ * repeatedly attempt to read data from the queue that was created within\r
+ * main().  When data is received, the task checks the value of the data, and\r
+ * if the value equals the expected 100, toggles an LED on the 7 segment\r
+ * display.  The 'block time' parameter passed to the queue receive function\r
+ * specifies that the task should be held in the Blocked state indefinitely to\r
+ * wait for data to be available on the queue.  The queue receive task will only\r
+ * leave the Blocked state when the queue send task writes to the queue.  As the\r
+ * queue send task writes to the queue every 200 milliseconds, the queue receive\r
+ * task leaves the Blocked state every 200 milliseconds, and therefore toggles\r
+ * the LED every 200 milliseconds.\r
+ *\r
+ * The LED Software Timer and the Button Interrupt:\r
+ * The user button SW2 is configured to generate an interrupt each time it is\r
+ * pressed.  The interrupt service routine switches an LED in the 7 segment\r
+ * display on, and resets the LED software timer.  The LED timer has a 5000\r
+ * millisecond (5 second) period, and uses a callback function that is defined\r
+ * to just turn the LED off again.  Therefore, pressing the user button will\r
+ * turn the LED on, and the LED will remain on until a full five seconds pass\r
+ * without the button being pressed.\r
+ */\r
+\r
+/* Kernel includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "queue.h"\r
+#include "timers.h"\r
+\r
+/* Fujitsu drivers/libraries. */\r
+#include "mcu.h"\r
+\r
+/* Priorities at which the tasks are created. */\r
+#define mainQUEUE_RECEIVE_TASK_PRIORITY                ( tskIDLE_PRIORITY + 2 )\r
+#define        mainQUEUE_SEND_TASK_PRIORITY            ( tskIDLE_PRIORITY + 1 )\r
+\r
+/* The rate at which data is sent to the queue, specified in milliseconds, and\r
+converted to ticks using the portTICK_RATE_MS constant. */\r
+#define mainQUEUE_SEND_FREQUENCY_MS                    ( 200 / portTICK_RATE_MS )\r
+\r
+/* The number of items the queue can hold.  This is 1 as the receive task\r
+will remove items as they are added, meaning the send task should always find\r
+the queue empty. */\r
+#define mainQUEUE_LENGTH                                       ( 1 )\r
+\r
+/* The LED toggle by the queue receive task. */\r
+#define mainTASK_CONTROLLED_LED                                ( 1UL << 3UL )\r
+\r
+/* The LED turned on by the button interrupt, and turned off by the LED timer. */\r
+#define mainTIMER_CONTROLLED_LED                       ( 1UL << 2UL )\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Setup the NVIC, LED outputs, and button inputs.\r
+ */\r
+static void prvSetupHardware( void );\r
+\r
+/*\r
+ * The tasks as described in the comments at the top of this file.\r
+ */\r
+static void prvQueueReceiveTask( void *pvParameters );\r
+static void prvQueueSendTask( void *pvParameters );\r
+\r
+/*\r
+ * The LED timer callback function.  This does nothing but switch off the\r
+ * LED defined by the mainTIMER_CONTROLLED_LED constant.\r
+ */\r
+static void vLEDTimerCallback( xTimerHandle xTimer );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* The queue used by both tasks. */\r
+static xQueueHandle xQueue = NULL;\r
+\r
+/* The LED software timer.  This uses vLEDTimerCallback() as its callback\r
+function. */\r
+static xTimerHandle xLEDTimer = NULL;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+int main(void)\r
+{\r
+       /* Configure the NVIC, LED outputs and button inputs. */\r
+       prvSetupHardware();\r
+       \r
+       /* Create the queue. */\r
+       xQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( unsigned long ) );\r
+\r
+       if( xQueue != NULL )\r
+       {\r
+               /* Start the two tasks as described in the comments at the top of this\r
+               file. */\r
+               xTaskCreate( prvQueueReceiveTask, ( signed char * ) "Rx", configMINIMAL_STACK_SIZE, NULL, mainQUEUE_RECEIVE_TASK_PRIORITY, NULL );\r
+               xTaskCreate( prvQueueSendTask, ( signed char * ) "TX", configMINIMAL_STACK_SIZE, NULL, mainQUEUE_SEND_TASK_PRIORITY, NULL );\r
+\r
+               /* Create the software timer that is responsible for turning off the LED\r
+               if the button is not pushed within 5000ms, as described at the top of\r
+               this file. */\r
+               xLEDTimer = xTimerCreate(       ( const signed char * ) "LEDTimer", /* A text name, purely to help debugging. */\r
+                                                                       ( 5000 / portTICK_RATE_MS ),            /* The timer period, in this case 5000ms (5s). */\r
+                                                                       pdFALSE,                                                        /* This is a one shot timer, so xAutoReload is set to pdFALSE. */\r
+                                                                       ( void * ) 0,                                           /* The ID is not used, so can be set to anything. */\r
+                                                                       vLEDTimerCallback                                       /* The callback function that switches the LED off. */\r
+                                                               );\r
+\r
+               /* Start the tasks and timer running. */\r
+               vTaskStartScheduler();\r
+       }\r
+\r
+       /* If all is well, the scheduler will now be running, and the following line\r
+       will never be reached.  If the following line does execute, then there was\r
+       insufficient FreeRTOS heap memory available for the idle and/or timer tasks\r
+       to be created.  See the memory management section on the FreeRTOS web site\r
+       for more details. */\r
+       for( ;; );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void vLEDTimerCallback( xTimerHandle xTimer )\r
+{\r
+       /* The timer has expired - so no button pushes have occurred in the last\r
+       five seconds - turn the LED off.  NOTE - accessing the LED port should use\r
+       a critical section because it is accessed from multiple tasks, and the\r
+       button interrupt - in this trivial case, for simplicity, the critical\r
+       section is omitted. */\r
+       FM3_GPIO->PDOR3 |= mainTIMER_CONTROLLED_LED;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* The ISR executed when the user button is pushed. */\r
+void INT0_7_Handler( void )\r
+{\r
+portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE;\r
+\r
+       /* The button was pushed, so ensure the LED is on before resetting the\r
+       LED timer.  The LED timer will turn the LED off if the button is not\r
+       pushed within 5000ms. */\r
+       FM3_GPIO->PDOR3 &= ~mainTIMER_CONTROLLED_LED;\r
+\r
+       /* This interrupt safe FreeRTOS function can be called from this interrupt\r
+       because the interrupt priority is below the\r
+       configMAX_SYSCALL_INTERRUPT_PRIORITY setting in FreeRTOSConfig.h. */\r
+       xTimerResetFromISR( xLEDTimer, &xHigherPriorityTaskWoken );\r
+\r
+       /* Clear the interrupt before leaving.  This just clears all the interrupts\r
+       for simplicity, as only one is actually used in this simple demo anyway. */\r
+       FM3_EXTI->EICL = 0x0000;\r
+\r
+       /* If calling xTimerResetFromISR() caused a task (in this case the timer\r
+       service/daemon task) to unblock, and the unblocked task has a priority\r
+       higher than or equal to the task that was interrupted, then\r
+       xHigherPriorityTaskWoken will now be set to pdTRUE, and calling\r
+       portEND_SWITCHING_ISR() will ensure the unblocked task runs next. */\r
+       portEND_SWITCHING_ISR( xHigherPriorityTaskWoken );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvQueueSendTask( void *pvParameters )\r
+{\r
+portTickType xNextWakeTime;\r
+const unsigned long ulValueToSend = 100UL;\r
+\r
+       /* Initialise xNextWakeTime - this only needs to be done once. */\r
+       xNextWakeTime = xTaskGetTickCount();\r
+\r
+       for( ;; )\r
+       {\r
+               /* Place this task in the blocked state until it is time to run again.\r
+               The block time is specified in ticks, the constant used converts ticks\r
+               to ms.  While in the Blocked state this task will not consume any CPU\r
+               time. */\r
+               vTaskDelayUntil( &xNextWakeTime, mainQUEUE_SEND_FREQUENCY_MS );\r
+\r
+               /* Send to the queue - causing the queue receive task to unblock and\r
+               toggle an LED.  0 is used as the block time so the sending operation\r
+               will not block - it shouldn't need to block as the queue should always\r
+               be empty at this point in the code. */\r
+               xQueueSend( xQueue, &ulValueToSend, 0 );\r
+       }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvQueueReceiveTask( void *pvParameters )\r
+{\r
+unsigned long ulReceivedValue;\r
+\r
+       for( ;; )\r
+       {\r
+               /* Wait until something arrives in the queue - this task will block\r
+               indefinitely provided INCLUDE_vTaskSuspend is set to 1 in\r
+               FreeRTOSConfig.h. */\r
+               xQueueReceive( xQueue, &ulReceivedValue, portMAX_DELAY );\r
+\r
+               /*  To get here something must have been received from the queue, but\r
+               is it the expected value?  If it is, toggle the LED. */\r
+               if( ulReceivedValue == 100UL )\r
+               {\r
+                       /* NOTE - accessing the LED port should use a critical section\r
+                       because it is accessed from multiple tasks, and the button interrupt\r
+                       - in this trivial case, for simplicity, the critical section is\r
+                       omitted. */\r
+                       if( ( FM3_GPIO->PDOR3 & mainTASK_CONTROLLED_LED ) != 0 )\r
+                       {\r
+                               FM3_GPIO->PDOR3 &= ~mainTASK_CONTROLLED_LED;\r
+                       }\r
+                       else\r
+                       {\r
+                               FM3_GPIO->PDOR3 |= mainTASK_CONTROLLED_LED;\r
+                       }\r
+               }\r
+       }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvSetupHardware( void )\r
+{\r
+const unsigned short usButtonInputBit = 0x01U;\r
+\r
+       SystemInit();\r
+       SystemCoreClockUpdate();\r
+       \r
+       /* Analog inputs are not used on the LED outputs. */\r
+       FM3_GPIO->ADE  = 0x0000;\r
+       \r
+       /* Set to output. */\r
+       FM3_GPIO->DDR1 |= 0xFFFF;\r
+       FM3_GPIO->DDR3 |= 0xFFFF;\r
+       \r
+       /* Set as GPIO. */\r
+       FM3_GPIO->PFR1 &= 0x0000;\r
+       FM3_GPIO->PFR3 &= 0x0000;\r
+\r
+       /* Start with all LEDs off. */\r
+       FM3_GPIO->PDOR3 = 0xFFFF;\r
+       FM3_GPIO->PDOR1 = 0xFFFF;\r
+       \r
+       /* Set the switches to input (P18->P1F). */\r
+       FM3_GPIO->DDR5 = 0x0000;\r
+       FM3_GPIO->PFR5 = 0x0000;\r
+\r
+       /* Assign the button input as GPIO. */\r
+       FM3_GPIO->PFR1 |= usButtonInputBit;\r
+       \r
+       /* Button interrupt on falling edge. */\r
+       FM3_EXTI->ELVR  = 0x0003;\r
+\r
+       /* Clear all external interrupts. */\r
+       FM3_EXTI->EICL  = 0x0000;\r
+\r
+       /* Enable the button interrupt. */\r
+       FM3_EXTI->ENIR |= usButtonInputBit;\r
+       \r
+       /* Setup the GPIO and the NVIC for the switch used in this simple demo. */\r
+       NVIC_SetPriority( EXINT0_7_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );\r
+    NVIC_EnableIRQ( EXINT0_7_IRQn );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationMallocFailedHook( void )\r
+{\r
+       /* Called if a call to pvPortMalloc() fails because there is insufficient\r
+       free memory available in the FreeRTOS heap.  pvPortMalloc() is called\r
+       internally by FreeRTOS API functions that create tasks, queues, software\r
+       timers, and semaphores.  The size of the FreeRTOS heap is set by the\r
+       configTOTAL_HEAP_SIZE configuration constant in FreeRTOSConfig.h. */\r
+       for( ;; );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationStackOverflowHook( xTaskHandle *pxTask, signed char *pcTaskName )\r
+{\r
+       ( void ) pcTaskName;\r
+       ( void ) pxTask;\r
+\r
+       /* Run time stack overflow checking is performed if\r
+       configconfigCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2.  This hook\r
+       function is called if a stack overflow is detected. */\r
+       for( ;; );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationTickHook( void )\r
+{\r
+       /* A tick hook is used by the "Full" build configuration.  The Full and\r
+       blinky build configurations share a FreeRTOSConfig.h header file, so this\r
+       simple build configuration also has to define a tick hook - even though it\r
+       does not actually use it for anything. */\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationIdleHook( void )\r
+{\r
+volatile size_t xFreeHeapSpace;\r
+\r
+       /* This function is called on each cycle of the idle task.  In this case it\r
+       does nothing useful, other than report the amount of FreeRTOS heap that\r
+       remains unallocated. */\r
+       xFreeHeapSpace = xPortGetFreeHeapSize();\r
+\r
+       if( xFreeHeapSpace > 100 )\r
+       {\r
+               /* By now, the kernel has allocated everything it is going to, so\r
+               if there is a lot of heap remaining unallocated then\r
+               the value of configTOTAL_HEAP_SIZE in FreeRTOSConfig.h can be\r
+               reduced accordingly. */\r
+       }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+\r
+\r
+\r

diff --git a/Demo/CORTEX_MB9A310_IAR_Keil/serial.c b/Demo/CORTEX_MB9A310_IAR_Keil/serial.c
new file mode 100644 (file)
index 0000000..698130b
--- /dev/null
+++ b/Demo/CORTEX_MB9A310_IAR_Keil/serial.c
@@ -0,0 +1,298 @@
+/*\r
+    FreeRTOS V7.0.1 - Copyright (C) 2011 Real Time Engineers Ltd.\r
+       \r
+\r
+    ***************************************************************************\r
+     *                                                                       *\r
+     *    FreeRTOS tutorial books are available in pdf and paperback.        *\r
+     *    Complete, revised, and edited pdf reference manuals are also       *\r
+     *    available.                                                         *\r
+     *                                                                       *\r
+     *    Purchasing FreeRTOS documentation will not only help you, by       *\r
+     *    ensuring you get running as quickly as possible and with an        *\r
+     *    in-depth knowledge of how to use FreeRTOS, it will also help       *\r
+     *    the FreeRTOS project to continue with its mission of providing     *\r
+     *    professional grade, cross platform, de facto standard solutions    *\r
+     *    for microcontrollers - completely free of charge!                  *\r
+     *                                                                       *\r
+     *    >>> See http://www.FreeRTOS.org/Documentation for details. <<<     *\r
+     *                                                                       *\r
+     *    Thank you for using FreeRTOS, and thank you for your support!      *\r
+     *                                                                       *\r
+    ***************************************************************************\r
+\r
+\r
+    This file is part of the FreeRTOS distribution.\r
+\r
+    FreeRTOS is free software; you can redistribute it and/or modify it under\r
+    the terms of the GNU General Public License (version 2) as published by the\r
+    Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+    >>>NOTE<<< The modification to the GPL is included to allow you to\r
+    distribute a combined work that includes FreeRTOS without being obliged to\r
+    provide the source code for proprietary components outside of the FreeRTOS\r
+    kernel.  FreeRTOS is distributed in the hope that it will be useful, but\r
+    WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\r
+    more details. You should have received a copy of the GNU General Public\r
+    License and the FreeRTOS license exception along with FreeRTOS; if not it\r
+    can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
+    by writing to Richard Barry, contact details for whom are available on the\r
+    FreeRTOS WEB site.\r
+\r
+    1 tab == 4 spaces!\r
+\r
+    http://www.FreeRTOS.org - Documentation, latest information, license and\r
+    contact details.\r
+\r
+    http://www.SafeRTOS.com - A version that is certified for use in safety\r
+    critical systems.\r
+\r
+    http://www.OpenRTOS.com - Commercial support, development, porting,\r
+    licensing and training services.\r
+*/\r
+\r
+/*\r
+       BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER FOR UART0.\r
+       \r
+       ***Note*** This example uses queues to send each character into an interrupt\r
+       service routine and out of an interrupt service routine individually.  This\r
+       is done to demonstrate queues being used in an interrupt, and to deliberately\r
+       load the system to test the FreeRTOS port.  It is *NOT* meant to be an\r
+       example of an efficient implementation.  An efficient implementation should\r
+       use FIFOs or DMA if available, and only use FreeRTOS API functions when\r
+       enough has been received to warrant a task being unblocked to process the\r
+       data.\r
+*/\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "queue.h"\r
+#include "semphr.h"\r
+#include "comtest2.h"\r
+\r
+/* Library includes. */\r
+#include "mcu.h"\r
+\r
+/* Demo application includes. */\r
+#include "serial.h"\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Register bit definitions. */\r
+#define serRX_INT_ENABLE               0x10\r
+#define serTX_INT_ENABLE               0x08\r
+#define serRX_ENABLE                   0x02\r
+#define serTX_ENABLE                   0x01\r
+#define serORE_ERROR_BIT               0x08\r
+#define serFRE_ERROR_BIT               0x10\r
+#define serPE_ERROR_BIT                        0x20\r
+#define serRX_INT                              0x04\r
+#define serTX_INT                              0x02\r
+\r
+/* Misc defines. */\r
+#define serINVALID_QUEUE                               ( ( xQueueHandle ) 0 )\r
+#define serNO_BLOCK                                            ( ( portTickType ) 0 )\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* The queue used to hold received characters. */\r
+static xQueueHandle xRxedChars;\r
+static xQueueHandle xCharsForTx;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * See the serial2.h header file.\r
+ */\r
+xComPortHandle xSerialPortInitMinimal( unsigned long ulWantedBaud, unsigned portBASE_TYPE uxQueueLength )\r
+{\r
+       /* Create the queues used to hold Rx/Tx characters. */\r
+       xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed char ) );\r
+       xCharsForTx = xQueueCreate( uxQueueLength + 1, ( unsigned portBASE_TYPE ) sizeof( signed char ) );\r
+       \r
+       /* If the queues were created correctly then setup the serial port\r
+       hardware. */\r
+       if( ( xRxedChars != serINVALID_QUEUE ) && ( xCharsForTx != serINVALID_QUEUE ) )\r
+       {\r
+               /* Ensure interrupts don't fire during the init process.  Interrupts\r
+               will be enabled automatically when the first task start running. */\r
+               portDISABLE_INTERRUPTS();\r
+               \r
+               /* Configure P21 and P22 for use by the UART. */\r
+               FM3_GPIO->PFR2 |= ( 1 << 0x01 ) | ( 1 << 0x02 );\r
+               \r
+               /* SIN0_0 and SOT0_0. */\r
+               FM3_GPIO->EPFR07 |= ( 1 << 6 );\r
+               \r
+               /* Reset. */\r
+               FM3_MFS0_UART->SCR = 0x80;\r
+               \r
+               /* Enable output in mode 0. */\r
+               FM3_MFS0_UART->SMR = 0x01;\r
+               \r
+               /* Clear all errors that may already be present. */\r
+               FM3_MFS0_UART->SSR = 0x00;\r
+               FM3_MFS0_UART->ESCR = 0x00;\r
+               \r
+               FM3_MFS0_UART->BGR = ( configCPU_CLOCK_HZ / 2UL ) / ( ulWantedBaud - 1UL );\r
+\r
+               /* Enable Rx, Tx, and the Rx interrupt. */              \r
+               FM3_MFS0_UART->SCR |= ( serRX_ENABLE | serTX_ENABLE | serRX_INT_ENABLE );\r
+               \r
+               /* Configure the NVIC for UART interrupts. */\r
+               NVIC_ClearPendingIRQ( MFS0RX_IRQn );\r
+               NVIC_EnableIRQ( MFS0RX_IRQn );\r
+               \r
+               /* The priority *MUST* be at or below\r
+               configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY as FreeRTOS API functions\r
+               are called in the interrupt handler. */\r
+               NVIC_SetPriority( MFS0RX_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );\r
+               \r
+               /* Do the same for the Tx interrupts. */\r
+               NVIC_ClearPendingIRQ( MFS0TX_IRQn );\r
+               NVIC_EnableIRQ( MFS0TX_IRQn );\r
+               \r
+               /* The priority *MUST* be at or below\r
+               configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY as FreeRTOS API functions\r
+               are called in the interrupt handler. */\r
+               NVIC_SetPriority( MFS0TX_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );\r
+       }\r
+\r
+       /* This demo file only supports a single port but we have to return\r
+       something to comply with the standard demo header file. */\r
+       return ( xComPortHandle ) 0;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed char *pcRxedChar, portTickType xBlockTime )\r
+{\r
+       /* The port handle is not required as this driver only supports one port. */\r
+       ( void ) pxPort;\r
+\r
+       /* Get the next character from the buffer.  Return false if no characters\r
+       are available, or arrive before xBlockTime expires. */\r
+       if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) )\r
+       {\r
+               return pdTRUE;\r
+       }\r
+       else\r
+       {\r
+               return pdFALSE;\r
+       }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vSerialPutString( xComPortHandle pxPort, const signed char * const pcString, unsigned short usStringLength )\r
+{\r
+signed char *pxNext;\r
+\r
+       /* A couple of parameters that this port does not use. */\r
+       ( void ) usStringLength;\r
+       ( void ) pxPort;\r
+\r
+       /* NOTE: This implementation does not handle the queue being full as no\r
+       block time is used! */\r
+\r
+       /* The port handle is not required as this driver only supports one UART. */\r
+       ( void ) pxPort;\r
+\r
+       /* Send each character in the string, one at a time. */\r
+       pxNext = ( signed char * ) pcString;\r
+       while( *pxNext )\r
+       {\r
+               xSerialPutChar( pxPort, *pxNext, serNO_BLOCK );\r
+               pxNext++;\r
+       }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed char cOutChar, portTickType xBlockTime )\r
+{\r
+signed portBASE_TYPE xReturn;\r
+\r
+       if( xQueueSend( xCharsForTx, &cOutChar, xBlockTime ) == pdPASS )\r
+       {\r
+               xReturn = pdPASS;\r
+               \r
+               /* Enable the UART Tx interrupt. */\r
+               FM3_MFS0_UART->SCR |= serTX_INT_ENABLE;\r
+       }\r
+       else\r
+       {\r
+               xReturn = pdFAIL;\r
+       }\r
+\r
+       return xReturn;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vSerialClose( xComPortHandle xPort )\r
+{\r
+       /* Not supported as not required by the demo application. */\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void MFS0RX_IRQHandler( void )\r
+{\r
+portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE;\r
+char cChar;\r
+\r
+       if( ( FM3_MFS0_UART->SSR & ( serORE_ERROR_BIT | serFRE_ERROR_BIT | serPE_ERROR_BIT ) ) != 0 )\r
+       {\r
+               /* A PE, ORE or FRE error occurred.  Clear it. */\r
+               FM3_MFS0_UART->SSR |= ( 1 << 7 );\r
+               cChar = FM3_MFS0_UART->RDR;\r
+       }\r
+       else if( FM3_MFS0_UART->SSR & serRX_INT )\r
+       {\r
+               /* A character has been received on the USART, send it to the Rx\r
+               handler task. */\r
+               cChar = FM3_MFS0_UART->RDR;\r
+               xQueueSendFromISR( xRxedChars, &cChar, &xHigherPriorityTaskWoken );\r
+       }       \r
+\r
+       /* If sending or receiving from a queue has caused a task to unblock, and\r
+       the unblocked task has a priority equal to or higher than the currently\r
+       running task (the task this ISR interrupted), then xHigherPriorityTaskWoken\r
+       will have automatically been set to pdTRUE within the queue send or receive\r
+       function.  portEND_SWITCHING_ISR() will then ensure that this ISR returns\r
+       directly to the higher priority unblocked task. */\r
+       portEND_SWITCHING_ISR( xHigherPriorityTaskWoken );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void MFS0TX_IRQHandler( void )\r
+{\r
+portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE;\r
+char cChar;\r
+\r
+       if( FM3_MFS0_UART->SSR & serTX_INT )\r
+       {\r
+               /* The interrupt was caused by the TX register becoming empty.  Are\r
+               there any more characters to transmit? */\r
+               if( xQueueReceiveFromISR( xCharsForTx, &cChar, &xHigherPriorityTaskWoken ) == pdTRUE )\r
+               {\r
+                       /* A character was retrieved from the queue so can be sent to the\r
+                       USART now. */\r
+                       FM3_MFS0_UART->TDR = cChar;\r
+               }\r
+               else\r
+               {\r
+                       /* Disable the Tx interrupt. */\r
+                       FM3_MFS0_UART->SCR &= ~serTX_INT_ENABLE;\r
+               }               \r
+       }       \r
+\r
+       /* If sending or receiving from a queue has caused a task to unblock, and\r
+       the unblocked task has a priority equal to or higher than the currently\r
+       running task (the task this ISR interrupted), then xHigherPriorityTaskWoken\r
+       will have automatically been set to pdTRUE within the queue send or receive\r
+       function.  portEND_SWITCHING_ISR() will then ensure that this ISR returns\r
+       directly to the higher priority unblocked task. */\r
+       portEND_SWITCHING_ISR( xHigherPriorityTaskWoken );\r
+}\r
+\r
+\r
+\r
+\r
+\r
+       \r