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+ <configuration configurationName="Debug">\r
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+ </storageModule>\r
+ <storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/>\r
+</cproject>\r
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>\r
+<projectDescription>\r
+ <name>RTOSDemo</name>\r
+ <comment></comment>\r
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+ </projects>\r
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+ </natures>\r
+</projectDescription>\r
--- /dev/null
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+ </configuration>\r
+</project>\r
--- /dev/null
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--- /dev/null
+{\r
+ "schemaVersion": "0.2.4",\r
+ "contentVersion": "0.2.0",\r
+ "headerVersion": "0.2.0",\r
+ "device": {\r
+ "fe310": {\r
+ "displayName": "Freedom E310-G000",\r
+ "description": "The FE310-G000 is the first Freedom E300 SoC, and is the industry's first commercially available RISC-V SoC. The FE310-G000 is built around the E31 Core Complex instantiated in the Freedom E300 platform.",\r
+ "supplier": {\r
+ "name": "sifive",\r
+ "id": "1",\r
+ "displayName": "SiFive",\r
+ "fullName": "SiFive, Inc.",\r
+ "contact": "info@sifive.com"\r
+ },\r
+ "busWidth": "32",\r
+ "resetMask": "all",\r
+ "resetValue": "0x00000000",\r
+ "access": "rw",\r
+ "headerGuardPrefix": "SIFIVE_DEVICES_FE310_",\r
+ "headerTypePrefix": "sifive_fe310_",\r
+ "headerInterruptPrefix": "sifive_fe310_interrupt_global_",\r
+ "headerInterruptEnumPrefix": "riscv_interrupts_global_",\r
+ "revision": "r0p0",\r
+ "numInterrupts": "51",\r
+ "priorityBits": "3",\r
+ "regWidth": "32",\r
+ "cores": {\r
+ "e31": {\r
+ "harts": "1",\r
+ "isa": "RV32IMAC",\r
+ "isaVersion": "2.2",\r
+ "mpu": "pmp",\r
+ "mmu": "none",\r
+ "localInterrupts": {\r
+ "machine_software": {\r
+ "description": "Machine Software Interrupt",\r
+ "value": "3"\r
+ },\r
+ "machine_timer": {\r
+ "description": "Machine Timer Interrupt",\r
+ "value": "7"\r
+ },\r
+ "machine_ext": {\r
+ "description": "Machine External Interrupt",\r
+ "value": "11"\r
+ }\r
+ },\r
+ "numLocalInterrupts": "0"\r
+ }\r
+ },\r
+ "peripherals": {\r
+ "clint": {\r
+ "description": "Core Complex Local Interruptor (CLINT) Peripheral",\r
+ "baseAddress": "0x02000000",\r
+ "size": "0x10000",\r
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+ "addressOffset": "0x0000",\r
+ "arraySize": "1"\r
+ }\r
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+ "clusters": {\r
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+ "addressOffset": "0x4000",\r
+ "arraySize": "1",\r
+ "registers": {\r
+ "low": {\r
+ "description": "Machine Compare Register Low",\r
+ "addressOffset": "0x0000"\r
+ },\r
+ "high": {\r
+ "description": "Machine Compare Register High",\r
+ "addressOffset": "0x0004"\r
+ }\r
+ }\r
+ },\r
+ "mtime": {\r
+ "description": "Machine Time Register",\r
+ "addressOffset": "0xBFF8",\r
+ "access": "r",\r
+ "registers": {\r
+ "low": {\r
+ "description": "Machine Time Register Low",\r
+ "addressOffset": "0x0000"\r
+ },\r
+ "high": {\r
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+ "addressOffset": "0x0004"\r
+ }\r
+ }\r
+ }\r
+ }\r
+ },\r
+ "plic": {\r
+ "description": "Platform-Level Interrupt Controller (PLIC) Peripheral",\r
+ "baseAddress": "0x0C000000",\r
+ "size": "0x4000000",\r
+ "registers": {\r
+ "priorities": {\r
+ "arraySize": "52",\r
+ "description": "Interrupt Priorities Registers; 0 is reserved.",\r
+ "addressOffset": "0x0000",\r
+ "fields": {\r
+ "value": {\r
+ "description": "The priority for a given global interrupt",\r
+ "bitOffset": "0",\r
+ "bitWidth": "3",\r
+ "resetMask": "all",\r
+ "resetValue": "0x0"\r
+ }\r
+ }\r
+ },\r
+ "pendings": {\r
+ "arraySize": "2",\r
+ "description": "Interrupt Pending Bits Registers",\r
+ "addressOffset": "0x1000",\r
+ "access": "r"\r
+ }\r
+ },\r
+ "clusters": {\r
+ "enablestarget0": {\r
+ "description": "Hart 0 Interrupt Enable Bits",\r
+ "addressOffset": "0x00002000",\r
+ "clusters": {\r
+ "m": {\r
+ "addressOffset": "0x0000",\r
+ "description": "Hart 0 M-mode Interrupt Enable Bits",\r
+ "registers": {\r
+ "enables": {\r
+ "arraySize": "2",\r
+ "description": "Interrupt Enable Bits Registers",\r
+ "addressOffset": "0x0000"\r
+ }\r
+ }\r
+ }\r
+ }\r
+ },\r
+ "target0": {\r
+ "description": "Hart 0 Interrupt Thresholds",\r
+ "addressOffset": "0x00200000",\r
+ "clusters": {\r
+ "m": {\r
+ "addressOffset": "0x0000",\r
+ "description": "Hart 0 M-Mode Interrupt Threshold",\r
+ "registers": {\r
+ "threshold": {\r
+ "description": "The Priority Threshold Register",\r
+ "addressOffset": "0x0000",\r
+ "fields": {\r
+ "value": {\r
+ "description": "The priority threshold value",\r
+ "bitOffset": "0",\r
+ "bitWidth": "3",\r
+ "resetMask": "all",\r
+ "resetValue": "0x0"\r
+ }\r
+ }\r
+ },\r
+ "claimcomplete": {\r
+ "description": "The Interrupt Claim/Completion Register",\r
+ "addressOffset": "0x0004"\r
+ }\r
+ }\r
+ }\r
+ }\r
+ }\r
+ }\r
+ },\r
+ "wdog": {\r
+ "description": "Watchdog Timer (WDT), part of Always-On Domain",\r
+ "baseAddress": "0x10000000",\r
+ "size": "0x0040",\r
+ "resetMask": "none",\r
+ "registers": {\r
+ "cfg": {\r
+ "description": "Watchdog Configuration Register",\r
+ "addressOffset": "0x0000",\r
+ "fields": {\r
+ "scale": {\r
+ "description": "Watchdog counter scale",\r
+ "bitOffset": "0",\r
+ "bitWidth": "4"\r
+ },\r
+ "rsten": {\r
+ "description": "Watchdog full reset enable",\r
+ "bitOffset": "8",\r
+ "bitWidth": "1",\r
+ "resetMask": "all",\r
+ "resetValue": "0x0"\r
+ },\r
+ "zerocmp": {\r
+ "description": "Watchdog zero on comparator",\r
+ "bitOffset": "9",\r
+ "bitWidth": "1"\r
+ },\r
+ "enalways": {\r
+ "description": "Watchdog enable counter always",\r
+ "bitOffset": "12",\r
+ "bitWidth": "1",\r
+ "resetMask": "all",\r
+ "resetValue": "0x0"\r
+ },\r
+ "encoreawake": {\r
+ "description": "Watchdog counter only when awake",\r
+ "bitOffset": "13",\r
+ "bitWidth": "1",\r
+ "resetMask": "all",\r
+ "resetValue": "0x0"\r
+ },\r
+ "cmpip": {\r
+ "description": "Watchdog interrupt pending",\r
+ "bitOffset": "28",\r
+ "bitWidth": "1"\r
+ }\r
+ }\r
+ },\r
+ "count": {\r
+ "description": "Watchdog Count Register",\r
+ "addressOffset": "0x0008"\r
+ },\r
+ "scale": {\r
+ "description": "Watchdog Scale Register",\r
+ "addressOffset": "0x0010",\r
+ "fields": {\r
+ "value": {\r
+ "description": "Watchdog scale value",\r
+ "bitOffset": "0",\r
+ "bitWidth": "16"\r
+ }\r
+ }\r
+ },\r
+ "feed": {\r
+ "description": "Watchdog Feed Address Register",\r
+ "addressOffset": "0x0018"\r
+ },\r
+ "key": {\r
+ "description": "Watchdog Key Register",\r
+ "addressOffset": "0x001C"\r
+ },\r
+ "cmp": {\r
+ "description": "Watchdog Compare Register",\r
+ "addressOffset": "0x0020",\r
+ "fields": {\r
+ "value": {\r
+ "description": "Watchdog compare value",\r
+ "bitOffset": "0",\r
+ "bitWidth": "16"\r
+ }\r
+ }\r
+ }\r
+ },\r
+ "interrupts": {\r
+ "wdogcmp": {\r
+ "description": "Watchdog Compare Interrupt",\r
+ "value": "1"\r
+ }\r
+ }\r
+ },\r
+ "rtc": {\r
+ "description": "Real-Time Clock (RTC), part of Always-On Domain",\r
+ "baseAddress": "0x10000040",\r
+ "size": "0x0030",\r
+ "resetMask": "none",\r
+ "registers": {\r
+ "cfg": {\r
+ "description": "RTC Configuration Register",\r
+ "addressOffset": "0x0000",\r
+ "fields": {\r
+ "scale": {\r
+ "description": "RTC clock rate scale",\r
+ "bitOffset": "0",\r
+ "bitWidth": "4"\r
+ },\r
+ "enalways": {\r
+ "description": "RTC counter enable",\r
+ "bitOffset": "12",\r
+ "bitWidth": "1",\r
+ "resetMask": "all",\r
+ "resetValue": "0x0"\r
+ },\r
+ "cmpip": {\r
+ "description": "RTC comparator interrupt pending",\r
+ "bitOffset": "28",\r
+ "bitWidth": "1",\r
+ "access": "r"\r
+ }\r
+ }\r
+ },\r
+ "low": {\r
+ "description": "RTC Counter Register Low",\r
+ "addressOffset": "0x0008"\r
+ },\r
+ "high": {\r
+ "description": "RTC Counter Register High",\r
+ "addressOffset": "0x000C",\r
+ "fields": {\r
+ "value": {\r
+ "description": "RTC counter register, high bits",\r
+ "bitOffset": "0",\r
+ "bitWidth": "16"\r
+ }\r
+ }\r
+ },\r
+ "scale": {\r
+ "description": "RTC Scale Register",\r
+ "addressOffset": "0x0010"\r
+ },\r
+ "cmp": {\r
+ "description": "RTC Compare Register",\r
+ "addressOffset": "0x0020"\r
+ }\r
+ },\r
+ "interrupts": {\r
+ "rtccmp": {\r
+ "description": "RTC Compare Interrupt",\r
+ "value": "2"\r
+ }\r
+ }\r
+ },\r
+ "pmu": {\r
+ "description": "Power-Management Unit (PMU), part of Always-On Domain",\r
+ "baseAddress": "0x10000100",\r
+ "size": "0x0050",\r
+ "resetMask": "none",\r
+ "registers": {\r
+ "wakeupi": {\r
+ "description": "Wakeup program instruction Registers",\r
+ "addressOffset": "0x0000",\r
+ "arraySize": "8"\r
+ },\r
+ "sleepi": {\r
+ "description": "Sleep Program Instruction Registers",\r
+ "addressOffset": "0x0020",\r
+ "arraySize": "8"\r
+ },\r
+ "ie": {\r
+ "description": "PMU Interrupt Enables Register",\r
+ "addressOffset": "0x0040",\r
+ "fields": {\r
+ "rtc": {\r
+ "description": "RTC Comparator active",\r
+ "bitOffset": "1",\r
+ "bitWidth": "1"\r
+ },\r
+ "dwakeup": {\r
+ "description": "dwakeup_n pin active",\r
+ "bitOffset": "2",\r
+ "bitWidth": "1"\r
+ }\r
+ }\r
+ },\r
+ "cause": {\r
+ "description": "PMU Wakeup Cause Register",\r
+ "addressOffset": "0x0044",\r
+ "fields": {\r
+ "wakeupcause": {\r
+ "description": "Wakeup cause",\r
+ "bitOffset": "0",\r
+ "bitWidth": "2",\r
+ "access": "r",\r
+ "enumerations": {\r
+ "wakeupcause-enum": {\r
+ "description": "Wakeup Cause Values Enumeration",\r
+ "values": {\r
+ "0": {\r
+ "displayName": "reset",\r
+ "description": "Reset Wakeup"\r
+ },\r
+ "1": {\r
+ "displayName": "rtc",\r
+ "description": "RTC Wakeup"\r
+ },\r
+ "2": {\r
+ "displayName": "dwakeup",\r
+ "description": "Digital input Wakeup"\r
+ },\r
+ "*": {\r
+ "displayName": "undefined"\r
+ }\r
+ }\r
+ }\r
+ }\r
+ },\r
+ "resetcause": {\r
+ "description": "Reset cause",\r
+ "bitOffset": "8",\r
+ "bitWidth": "2",\r
+ "access": "r",\r
+ "enumerations": {\r
+ "resetcause-enum": {\r
+ "description": "Reset Cause Values Enumeration",\r
+ "values": {\r
+ "1": {\r
+ "displayName": "external",\r
+ "description": "External reset"\r
+ },\r
+ "2": {\r
+ "displayName": "watchdog",\r
+ "description": "Watchdog timer reset"\r
+ },\r
+ "*": {\r
+ "displayName": "undefined"\r
+ }\r
+ }\r
+ }\r
+ }\r
+ }\r
+ }\r
+ },\r
+ "sleep": {\r
+ "description": "PMU Initiate Sleep Sequence Register",\r
+ "addressOffset": "0x0048"\r
+ },\r
+ "key": {\r
+ "description": "PMU Key Register",\r
+ "addressOffset": "0x004C"\r
+ }\r
+ }\r
+ },\r
+ "aon": {\r
+ "description": "Always-On (AON) Domain",\r
+ "baseAddress": "0x10000070",\r
+ "size": "0x0090",\r
+ "resetMask": "none",\r
+ "registers": {\r
+ "lfrosccfg": {\r
+ "description": "Internal Programmable Low-Frequency Ring Oscillator Register",\r
+ "addressOffset": "0x0000",\r
+ "fields": {\r
+ "div": {\r
+ "description": "LFROSC divider",\r
+ "bitOffset": "0",\r
+ "bitWidth": "6",\r
+ "resetMask": "all",\r
+ "resetValue": "0x04"\r
+ },\r
+ "trim": {\r
+ "description": "LFROSC trim value",\r
+ "bitOffset": "16",\r
+ "bitWidth": "5",\r
+ "resetMask": "all",\r
+ "resetValue": "0x10"\r
+ },\r
+ "en": {\r
+ "description": "LFROSC enable",\r
+ "bitOffset": "30",\r
+ "bitWidth": "1",\r
+ "resetMask": "all",\r
+ "resetValue": "0x1"\r
+ },\r
+ "rdy": {\r
+ "description": "LFROSC ready",\r
+ "bitOffset": "31",\r
+ "bitWidth": "1",\r
+ "access": "r"\r
+ }\r
+ }\r
+ },\r
+ "backup": {\r
+ "description": "Backup Registers",\r
+ "addressOffset": "0x0010",\r
+ "arraySize": "32"\r
+ }\r
+ }\r
+ },\r
+ "prci": {\r
+ "description": "Power, Reset, Clock, Interrupt (PRCI) Peripheral",\r
+ "baseAddress": "0x10008000",\r
+ "size": "0x8000",\r
+ "registers": {\r
+ "hfrosccfg": {\r
+ "description": "Internal Trimmable Programmable 72 MHz Oscillator Register",\r
+ "addressOffset": "0x0000",\r
+ "fields": {\r
+ "div": {\r
+ "description": "HFROSC divider",\r
+ "bitOffset": "0",\r
+ "bitWidth": "6",\r
+ "resetMask": "all",\r
+ "resetValue": "0x04"\r
+ },\r
+ "trim": {\r
+ "description": "HFROSC trim value",\r
+ "bitOffset": "16",\r
+ "bitWidth": "5",\r
+ "resetMask": "all",\r
+ "resetValue": "0x10"\r
+ },\r
+ "en": {\r
+ "description": "HFROSC enable",\r
+ "bitOffset": "30",\r
+ "bitWidth": "1",\r
+ "resetMask": "all",\r
+ "resetValue": "0x1"\r
+ },\r
+ "rdy": {\r
+ "description": "HFROSC ready",\r
+ "bitOffset": "31",\r
+ "bitWidth": "1",\r
+ "access": "r"\r
+ }\r
+ }\r
+ },\r
+ "hfxosccfg": {\r
+ "description": "External 16 MHz Crystal Oscillator Register",\r
+ "addressOffset": "0x0004",\r
+ "fields": {\r
+ "en": {\r
+ "description": "HFXOSC enable",\r
+ "bitOffset": "30",\r
+ "bitWidth": "1",\r
+ "resetMask": "all",\r
+ "resetValue": "0x1"\r
+ },\r
+ "rdy": {\r
+ "description": "HFXOSC ready",\r
+ "bitOffset": "31",\r
+ "bitWidth": "1",\r
+ "access": "r"\r
+ }\r
+ }\r
+ },\r
+ "pllcfg": {\r
+ "description": "Internal High-Frequency PLL (HFPLL) Register",\r
+ "addressOffset": "0x0008",\r
+ "fields": {\r
+ "r": {\r
+ "description": "PLL R input divider value",\r
+ "bitOffset": "0",\r
+ "bitWidth": "3",\r
+ "resetMask": "all",\r
+ "resetValue": "0x1",\r
+ "enumerations": {\r
+ "pllr-enum": {\r
+ "description": "Reference Clock R Divide Ratio Enumeration",\r
+ "values": {\r
+ "0": {\r
+ "displayName": "/1",\r
+ "headerName": "div1",\r
+ "description": "Unchanged"\r
+ },\r
+ "1": {\r
+ "displayName": "/2",\r
+ "headerName": "div2",\r
+ "description": "Divided by 2"\r
+ },\r
+ "2": {\r
+ "displayName": "/3",\r
+ "headerName": "div3",\r
+ "description": "Divided by 3"\r
+ },\r
+ "3": {\r
+ "displayName": "/4",\r
+ "headerName": "div4",\r
+ "description": "Divided by 4"\r
+ }\r
+ }\r
+ }\r
+ }\r
+ },\r
+ "f": {\r
+ "description": "PLL F multiplier value",\r
+ "bitOffset": "4",\r
+ "bitWidth": "6",\r
+ "resetMask": "all",\r
+ "resetValue": "0x1F",\r
+ "enumerations": {\r
+ "pllf-enum": {\r
+ "description": "Reference Clock F Multiplier Ratio Enumeration",\r
+ "values": {\r
+ "0": {\r
+ "displayName": "*2",\r
+ "headerName": "mul2",\r
+ "description": "Multiplied by 2"\r
+ },\r
+ "1": {\r
+ "displayName": "*4",\r
+ "headerName": "mul4",\r
+ "description": "Multiplied by 4"\r
+ },\r
+ "2": {\r
+ "displayName": "*6",\r
+ "headerName": "mul6",\r
+ "description": "Multiplied by 6"\r
+ },\r
+ "3": {\r
+ "displayName": "*8",\r
+ "headerName": "mul8",\r
+ "description": "Multiplied by 8"\r
+ },\r
+ "4": {\r
+ "displayName": "*10",\r
+ "headerName": "mul10",\r
+ "description": "Multiplied by 10"\r
+ },\r
+ "5": {\r
+ "displayName": "*12",\r
+ "headerName": "mul12",\r
+ "description": "Multiplied by 12"\r
+ },\r
+ "6": {\r
+ "displayName": "*14",\r
+ "headerName": "mul14",\r
+ "description": "Multiplied by 14"\r
+ },\r
+ "7": {\r
+ "displayName": "*16",\r
+ "headerName": "mul16",\r
+ "description": "Multiplied by 16"\r
+ },\r
+ "8": {\r
+ "displayName": "*18",\r
+ "headerName": "mul18",\r
+ "description": "Multiplied by 18"\r
+ },\r
+ "9": {\r
+ "displayName": "*20",\r
+ "headerName": "mul20",\r
+ "description": "Multiplied by 20"\r
+ },\r
+ "10": {\r
+ "displayName": "*22",\r
+ "headerName": "mul22",\r
+ "description": "Multiplied by 22"\r
+ },\r
+ "11": {\r
+ "displayName": "*24",\r
+ "headerName": "mul24",\r
+ "description": "Multiplied by 24"\r
+ },\r
+ "12": {\r
+ "displayName": "*26",\r
+ "headerName": "mul26",\r
+ "description": "Multiplied by 26"\r
+ },\r
+ "13": {\r
+ "displayName": "*28",\r
+ "headerName": "mul28",\r
+ "description": "Multiplied by 28"\r
+ },\r
+ "14": {\r
+ "displayName": "*30",\r
+ "headerName": "mul30",\r
+ "description": "Multiplied by 30"\r
+ },\r
+ "15": {\r
+ "displayName": "*32",\r
+ "headerName": "mul32",\r
+ "description": "Multiplied by 32"\r
+ },\r
+ "16": {\r
+ "displayName": "*34",\r
+ "headerName": "mul34",\r
+ "description": "Multiplied by 34"\r
+ },\r
+ "17": {\r
+ "displayName": "*36",\r
+ "headerName": "mul36",\r
+ "description": "Multiplied by 36"\r
+ },\r
+ "18": {\r
+ "displayName": "*38",\r
+ "headerName": "mul38",\r
+ "description": "Multiplied by 38"\r
+ },\r
+ "19": {\r
+ "displayName": "*40",\r
+ "headerName": "mul40",\r
+ "description": "Multiplied by 40"\r
+ },\r
+ "20": {\r
+ "displayName": "*42",\r
+ "headerName": "mul42",\r
+ "description": "Multiplied by 42"\r
+ },\r
+ "21": {\r
+ "displayName": "*44",\r
+ "headerName": "mul44",\r
+ "description": "Multiplied by 44"\r
+ },\r
+ "22": {\r
+ "displayName": "*46",\r
+ "headerName": "mul46",\r
+ "description": "Multiplied by 46"\r
+ },\r
+ "23": {\r
+ "displayName": "*48",\r
+ "headerName": "mul48",\r
+ "description": "Multiplied by 48"\r
+ },\r
+ "24": {\r
+ "displayName": "*50",\r
+ "headerName": "mul50",\r
+ "description": "Multiplied by 50"\r
+ },\r
+ "25": {\r
+ "displayName": "*52",\r
+ "headerName": "mul52",\r
+ "description": "Multiplied by 52"\r
+ },\r
+ "26": {\r
+ "displayName": "*54",\r
+ "headerName": "mul54",\r
+ "description": "Multiplied by 54"\r
+ },\r
+ "27": {\r
+ "displayName": "*56",\r
+ "headerName": "mul56",\r
+ "description": "Multiplied by 56"\r
+ },\r
+ "28": {\r
+ "displayName": "*58",\r
+ "headerName": "mul58",\r
+ "description": "Multiplied by 58"\r
+ },\r
+ "29": {\r
+ "displayName": "*60",\r
+ "headerName": "mul60",\r
+ "description": "Multiplied by 60"\r
+ },\r
+ "30": {\r
+ "displayName": "*62",\r
+ "headerName": "mul62",\r
+ "description": "Multiplied by 62"\r
+ },\r
+ "31": {\r
+ "displayName": "*64",\r
+ "headerName": "mul64",\r
+ "description": "Multiplied by 64"\r
+ },\r
+ "32": {\r
+ "displayName": "*66",\r
+ "headerName": "mul66",\r
+ "description": "Multiplied by 66"\r
+ },\r
+ "33": {\r
+ "displayName": "*68",\r
+ "headerName": "mul68",\r
+ "description": "Multiplied by 68"\r
+ },\r
+ "34": {\r
+ "displayName": "*70",\r
+ "headerName": "mul70",\r
+ "description": "Multiplied by 70"\r
+ },\r
+ "35": {\r
+ "displayName": "*72",\r
+ "headerName": "mul72",\r
+ "description": "Multiplied by 72"\r
+ },\r
+ "36": {\r
+ "displayName": "*74",\r
+ "headerName": "mul74",\r
+ "description": "Multiplied by 74"\r
+ },\r
+ "37": {\r
+ "displayName": "*76",\r
+ "headerName": "mul76",\r
+ "description": "Multiplied by 76"\r
+ },\r
+ "38": {\r
+ "displayName": "*78",\r
+ "headerName": "mul78",\r
+ "description": "Multiplied by 78"\r
+ },\r
+ "39": {\r
+ "displayName": "*80",\r
+ "headerName": "mul80",\r
+ "description": "Multiplied by 80"\r
+ },\r
+ "40": {\r
+ "displayName": "*82",\r
+ "headerName": "mul82",\r
+ "description": "Multiplied by 82"\r
+ },\r
+ "41": {\r
+ "displayName": "*84",\r
+ "headerName": "mul84",\r
+ "description": "Multiplied by 84"\r
+ },\r
+ "42": {\r
+ "displayName": "*86",\r
+ "headerName": "mul86",\r
+ "description": "Multiplied by 86"\r
+ },\r
+ "43": {\r
+ "displayName": "*88",\r
+ "headerName": "mul88",\r
+ "description": "Multiplied by 88"\r
+ },\r
+ "44": {\r
+ "displayName": "*90",\r
+ "headerName": "mul90",\r
+ "description": "Multiplied by 90"\r
+ },\r
+ "45": {\r
+ "displayName": "*92",\r
+ "headerName": "mul92",\r
+ "description": "Multiplied by 92"\r
+ },\r
+ "46": {\r
+ "displayName": "*94",\r
+ "headerName": "mul94",\r
+ "description": "Multiplied by 94"\r
+ },\r
+ "47": {\r
+ "displayName": "*96",\r
+ "headerName": "mul96",\r
+ "description": "Multiplied by 96"\r
+ },\r
+ "48": {\r
+ "displayName": "*98",\r
+ "headerName": "mul98",\r
+ "description": "Multiplied by 98"\r
+ },\r
+ "49": {\r
+ "displayName": "*100",\r
+ "headerName": "mul100",\r
+ "description": "Multiplied by 100"\r
+ },\r
+ "50": {\r
+ "displayName": "*102",\r
+ "headerName": "mul102",\r
+ "description": "Multiplied by 102"\r
+ },\r
+ "51": {\r
+ "displayName": "*104",\r
+ "headerName": "mul104",\r
+ "description": "Multiplied by 104"\r
+ },\r
+ "52": {\r
+ "displayName": "*106",\r
+ "headerName": "mul106",\r
+ "description": "Multiplied by 106"\r
+ },\r
+ "53": {\r
+ "displayName": "*108",\r
+ "headerName": "mul108",\r
+ "description": "Multiplied by 108"\r
+ },\r
+ "54": {\r
+ "displayName": "*110",\r
+ "headerName": "mul110",\r
+ "description": "Multiplied by 110"\r
+ },\r
+ "55": {\r
+ "displayName": "*112",\r
+ "headerName": "mul112",\r
+ "description": "Multiplied by 112"\r
+ },\r
+ "56": {\r
+ "displayName": "*114",\r
+ "headerName": "mul114",\r
+ "description": "Multiplied by 114"\r
+ },\r
+ "57": {\r
+ "displayName": "*116",\r
+ "headerName": "mul116",\r
+ "description": "Multiplied by 116"\r
+ },\r
+ "58": {\r
+ "displayName": "*118",\r
+ "headerName": "mul118",\r
+ "description": "Multiplied by 118"\r
+ },\r
+ "59": {\r
+ "displayName": "*120",\r
+ "headerName": "mul120",\r
+ "description": "Multiplied by 120"\r
+ },\r
+ "60": {\r
+ "displayName": "*122",\r
+ "headerName": "mul122",\r
+ "description": "Multiplied by 122"\r
+ },\r
+ "61": {\r
+ "displayName": "*124",\r
+ "headerName": "mul124",\r
+ "description": "Multiplied by 124"\r
+ },\r
+ "62": {\r
+ "displayName": "*126",\r
+ "headerName": "mul126",\r
+ "description": "Multiplied by 126"\r
+ },\r
+ "63": {\r
+ "displayName": "*128",\r
+ "headerName": "mul128",\r
+ "description": "Multiplied by 128"\r
+ }\r
+ }\r
+ }\r
+ }\r
+ },\r
+ "q": {\r
+ "description": "PLL Q output divider value",\r
+ "bitOffset": "10",\r
+ "bitWidth": "2",\r
+ "resetMask": "all",\r
+ "resetValue": "0x3",\r
+ "enumerations": {\r
+ "pllq-enum": {\r
+ "description": "Reference Clock Q Divide Ratio Enumeration",\r
+ "values": {\r
+ "*": {\r
+ "displayName": "n/a",\r
+ "description": "Not supported"\r
+ },\r
+ "1": {\r
+ "displayName": "/2",\r
+ "headerName": "div2",\r
+ "description": "Divided by 2"\r
+ },\r
+ "2": {\r
+ "displayName": "/4",\r
+ "headerName": "div4",\r
+ "description": "Divided by 4"\r
+ },\r
+ "3": {\r
+ "displayName": "/8",\r
+ "headerName": "div8",\r
+ "description": "Divided by 8"\r
+ }\r
+ }\r
+ }\r
+ }\r
+ },\r
+ "sel": {\r
+ "description": "PLL select",\r
+ "bitOffset": "16",\r
+ "bitWidth": "1",\r
+ "resetMask": "all",\r
+ "resetValue": "0x0"\r
+ },\r
+ "refsel": {\r
+ "description": "PLL reference select",\r
+ "bitOffset": "17",\r
+ "bitWidth": "1",\r
+ "resetMask": "all",\r
+ "resetValue": "0x1"\r
+ },\r
+ "bypass": {\r
+ "description": "PLL bypass",\r
+ "bitOffset": "18",\r
+ "bitWidth": "1",\r
+ "resetMask": "all",\r
+ "resetValue": "0x1"\r
+ },\r
+ "lock": {\r
+ "description": "PLL lock indicator",\r
+ "bitOffset": "31",\r
+ "bitWidth": "1",\r
+ "access": "r"\r
+ }\r
+ }\r
+ },\r
+ "plloutdiv": {\r
+ "description": "PLL Output Divider",\r
+ "addressOffset": "0x000C"\r
+ }\r
+ }\r
+ },\r
+ "otp": {\r
+ "description": "One-Time Programmable Memory (OTP) Peripheral",\r
+ "baseAddress": "0x10010000",\r
+ "size": "0x1000",\r
+ "registers": {\r
+ "lock": {\r
+ "description": "Programmed-I/O Lock Register",\r
+ "addressOffset": "0x0000"\r
+ },\r
+ "ck": {\r
+ "description": "Device Clock Signal Register",\r
+ "addressOffset": "0x0004"\r
+ },\r
+ "oe": {\r
+ "description": "Device Output-Enable Signal Register",\r
+ "addressOffset": "0x0008"\r
+ },\r
+ "sel": {\r
+ "description": "Device Chip-Select Signal Register",\r
+ "addressOffset": "0x000C"\r
+ },\r
+ "we": {\r
+ "description": "Device Write-Enable Signal Register",\r
+ "addressOffset": "0x0010"\r
+ },\r
+ "mr": {\r
+ "description": "Device Mode Register",\r
+ "addressOffset": "0x0014"\r
+ },\r
+ "mrr": {\r
+ "description": "Read-Voltage Regulator Control Register",\r
+ "addressOffset": "0x0018"\r
+ },\r
+ "mpp": {\r
+ "description": "Write-Voltage Charge Pump Control Register",\r
+ "addressOffset": "0x001C"\r
+ },\r
+ "vrren": {\r
+ "description": "Read-Voltage Enable Register",\r
+ "addressOffset": "0x0020"\r
+ },\r
+ "vppen": {\r
+ "description": "Write-Voltage Enable Register",\r
+ "addressOffset": "0x0024"\r
+ },\r
+ "a": {\r
+ "description": "Device Address Register",\r
+ "addressOffset": "0x0028"\r
+ },\r
+ "d": {\r
+ "description": "Device Data Input Register",\r
+ "addressOffset": "0x002C"\r
+ },\r
+ "q": {\r
+ "description": "Device Data Output Register",\r
+ "addressOffset": "0x0030"\r
+ },\r
+ "rsctrl": {\r
+ "description": "Read Sequencer Control Register",\r
+ "addressOffset": "0x0034",\r
+ "fields": {\r
+ "scale": {\r
+ "description": "OTP timescale",\r
+ "bitOffset": "0",\r
+ "bitWidth": "2",\r
+ "resetMask": "all",\r
+ "resetValue": "0x1"\r
+ },\r
+ "tas": {\r
+ "description": "Address setup time",\r
+ "bitOffset": "3",\r
+ "bitWidth": "1",\r
+ "resetMask": "all",\r
+ "resetValue": "0x0"\r
+ },\r
+ "trp": {\r
+ "description": "Read pulse time",\r
+ "bitOffset": "4",\r
+ "bitWidth": "1"\r
+ },\r
+ "tracc": {\r
+ "description": "Read access time",\r
+ "bitOffset": "5",\r
+ "bitWidth": "1"\r
+ }\r
+ }\r
+ }\r
+ }\r
+ },\r
+ "gpio": {\r
+ "description": "General Purpose Input/Output Controller (GPIO) Peripheral",\r
+ "baseAddress": "0x10012000",\r
+ "size": "0x1000",\r
+ "registers": {\r
+ "value": {\r
+ "description": "Pin Value Register",\r
+ "addressOffset": "0x000",\r
+ "fields": {\r
+ "bit": {\r
+ "repeatGenerator": "0-31",\r
+ "description": "Value Bit Field",\r
+ "bitOffset": "0",\r
+ "bitWidth": "1",\r
+ "headerName": ""\r
+ }\r
+ }\r
+ },\r
+ "inputen": {\r
+ "description": "Pin Input Enable Register",\r
+ "addressOffset": "0x004",\r
+ "fields": {\r
+ "bit": {\r
+ "repeatGenerator": "0-31",\r
+ "description": "Pin Input Enable Bit Field",\r
+ "bitOffset": "0",\r
+ "bitWidth": "1",\r
+ "headerName": ""\r
+ }\r
+ }\r
+ },\r
+ "outputen": {\r
+ "description": "Pin Output Enable Register",\r
+ "addressOffset": "0x008",\r
+ "fields": {\r
+ "bit": {\r
+ "repeatGenerator": "0-31",\r
+ "description": "Pin Output Enable Bit Field",\r
+ "bitOffset": "0",\r
+ "bitWidth": "1",\r
+ "headerName": ""\r
+ }\r
+ }\r
+ },\r
+ "port": {\r
+ "description": "Output Port Value Register",\r
+ "addressOffset": "0x00C",\r
+ "fields": {\r
+ "bit": {\r
+ "repeatGenerator": "0-31",\r
+ "description": "Output Port Value Bit Field",\r
+ "bitOffset": "0",\r
+ "bitWidth": "1",\r
+ "headerName": ""\r
+ }\r
+ }\r
+ },\r
+ "pue": {\r
+ "description": "Internal Pull-up Enable Register",\r
+ "addressOffset": "0x010",\r
+ "fields": {\r
+ "bit": {\r
+ "repeatGenerator": "0-31",\r
+ "description": "Internal Pull-up Enable Bit Field",\r
+ "bitOffset": "0",\r
+ "bitWidth": "1",\r
+ "headerName": ""\r
+ }\r
+ }\r
+ },\r
+ "ds": {\r
+ "description": "Pin Drive Strength Register",\r
+ "addressOffset": "0x014",\r
+ "fields": {\r
+ "bit": {\r
+ "repeatGenerator": "0-31",\r
+ "description": "Pin Drive Strength Bit Field",\r
+ "bitOffset": "0",\r
+ "bitWidth": "1",\r
+ "headerName": ""\r
+ }\r
+ }\r
+ },\r
+ "riseie": {\r
+ "description": "Rise Interrupt Enable Register",\r
+ "addressOffset": "0x018",\r
+ "fields": {\r
+ "bit": {\r
+ "repeatGenerator": "0-31",\r
+ "description": "Rise Interrupt Enable Bit Field",\r
+ "bitOffset": "0",\r
+ "bitWidth": "1",\r
+ "headerName": ""\r
+ }\r
+ }\r
+ },\r
+ "riseip": {\r
+ "description": "Rise Interrupt Pending Register",\r
+ "addressOffset": "0x01C",\r
+ "fields": {\r
+ "bit": {\r
+ "repeatGenerator": "0-31",\r
+ "description": "Rise Interrupt Pending Bit Field",\r
+ "bitOffset": "0",\r
+ "bitWidth": "1",\r
+ "headerName": ""\r
+ }\r
+ }\r
+ },\r
+ "fallie": {\r
+ "description": "Fall Interrupt Enable Register",\r
+ "addressOffset": "0x020",\r
+ "fields": {\r
+ "bit": {\r
+ "repeatGenerator": "0-31",\r
+ "description": "Fall Interrupt Enable Bit Field",\r
+ "bitOffset": "0",\r
+ "bitWidth": "1",\r
+ "headerName": ""\r
+ }\r
+ }\r
+ },\r
+ "fallip": {\r
+ "description": "Fall Interrupt Pending Register",\r
+ "addressOffset": "0x024",\r
+ "fields": {\r
+ "bit": {\r
+ "repeatGenerator": "0-31",\r
+ "description": "Fall Interrupt Pending Bit Field",\r
+ "bitOffset": "0",\r
+ "bitWidth": "1",\r
+ "headerName": ""\r
+ }\r
+ }\r
+ },\r
+ "highie": {\r
+ "description": "High Interrupt Enable Register",\r
+ "addressOffset": "0x028",\r
+ "fields": {\r
+ "bit": {\r
+ "repeatGenerator": "0-31",\r
+ "description": "High Interrupt Enable Bit Field",\r
+ "bitOffset": "0",\r
+ "bitWidth": "1",\r
+ "headerName": ""\r
+ }\r
+ }\r
+ },\r
+ "highip": {\r
+ "description": "High Interrupt Pending Register",\r
+ "addressOffset": "0x02C",\r
+ "fields": {\r
+ "bit": {\r
+ "repeatGenerator": "0-31",\r
+ "description": "High Interrupt Pending Bit Field",\r
+ "bitOffset": "0",\r
+ "bitWidth": "1",\r
+ "headerName": ""\r
+ }\r
+ }\r
+ },\r
+ "lowie": {\r
+ "description": "Low Interrupt Enable Register",\r
+ "addressOffset": "0x030",\r
+ "fields": {\r
+ "bit": {\r
+ "repeatGenerator": "0-31",\r
+ "description": "Low Interrupt Enable Bit Field",\r
+ "bitOffset": "0",\r
+ "bitWidth": "1",\r
+ "headerName": ""\r
+ }\r
+ }\r
+ },\r
+ "lowip": {\r
+ "description": "Low Interrupt Pending Register",\r
+ "addressOffset": "0x034",\r
+ "fields": {\r
+ "bit": {\r
+ "repeatGenerator": "0-31",\r
+ "description": "Low Interrupt Pending Bit Field",\r
+ "bitOffset": "0",\r
+ "bitWidth": "1",\r
+ "headerName": ""\r
+ }\r
+ }\r
+ },\r
+ "iofen": {\r
+ "description": "HW I/O Function Enable Register",\r
+ "addressOffset": "0x038",\r
+ "fields": {\r
+ "bit": {\r
+ "repeatGenerator": "0-31",\r
+ "description": "HW I/O Function Enable Bit Field",\r
+ "bitOffset": "0",\r
+ "bitWidth": "1",\r
+ "headerName": ""\r
+ }\r
+ }\r
+ },\r
+ "iofsel": {\r
+ "description": "HW I/O Function Select Register",\r
+ "addressOffset": "0x03C",\r
+ "fields": {\r
+ "bit": {\r
+ "repeatGenerator": "0-31",\r
+ "description": "HW I/O Function Select Bit Field",\r
+ "bitOffset": "0",\r
+ "bitWidth": "1",\r
+ "headerName": ""\r
+ }\r
+ }\r
+ },\r
+ "outxor": {\r
+ "description": "Output XOR (invert) Register",\r
+ "addressOffset": "0x040",\r
+ "fields": {\r
+ "bit": {\r
+ "repeatGenerator": "0-31",\r
+ "description": "Output XOR Bit Field",\r
+ "bitOffset": "0",\r
+ "bitWidth": "1",\r
+ "headerName": ""\r
+ }\r
+ }\r
+ }\r
+ },\r
+ "interrupts": {\r
+ "gpio0": {\r
+ "description": "GPIO0 Interrupt",\r
+ "value": "8"\r
+ },\r
+ "gpio1": {\r
+ "description": "GPIO1 Interrupt",\r
+ "value": "9"\r
+ },\r
+ "gpio2": {\r
+ "description": "GPIO2 Interrupt",\r
+ "value": "10"\r
+ },\r
+ "gpio3": {\r
+ "description": "GPIO3 Interrupt",\r
+ "value": "11"\r
+ },\r
+ "gpio4": {\r
+ "description": "GPIO4 Interrupt",\r
+ "value": "12"\r
+ },\r
+ "gpio5": {\r
+ "description": "GPIO5 Interrupt",\r
+ "value": "13"\r
+ },\r
+ "gpio6": {\r
+ "description": "GPIO6 Interrupt",\r
+ "value": "14"\r
+ },\r
+ "gpio7": {\r
+ "description": "GPIO7 Interrupt",\r
+ "value": "15"\r
+ },\r
+ "gpio8": {\r
+ "description": "GPIO8 Interrupt",\r
+ "value": "16"\r
+ },\r
+ "gpio9": {\r
+ "description": "GPIO9 Interrupt",\r
+ "value": "17"\r
+ },\r
+ "gpio10": {\r
+ "description": "GPIO10 Interrupt",\r
+ "value": "18"\r
+ },\r
+ "gpio11": {\r
+ "description": "GPIO11 Interrupt",\r
+ "value": "19"\r
+ },\r
+ "gpio12": {\r
+ "description": "GPIO12 Interrupt",\r
+ "value": "20"\r
+ },\r
+ "gpio13": {\r
+ "description": "GPIO13 Interrupt",\r
+ "value": "21"\r
+ },\r
+ "gpio14": {\r
+ "description": "GPIO14 Interrupt",\r
+ "value": "22"\r
+ },\r
+ "gpio15": {\r
+ "description": "GPIO15 Interrupt",\r
+ "value": "23"\r
+ },\r
+ "gpio16": {\r
+ "description": "GPIO16 Interrupt",\r
+ "value": "24"\r
+ },\r
+ "gpio17": {\r
+ "description": "GPIO17 Interrupt",\r
+ "value": "25"\r
+ },\r
+ "gpio18": {\r
+ "description": "GPIO18 Interrupt",\r
+ "value": "26"\r
+ },\r
+ "gpio19": {\r
+ "description": "GPIO19 Interrupt",\r
+ "value": "27"\r
+ },\r
+ "gpio20": {\r
+ "description": "GPIO20 Interrupt",\r
+ "value": "28"\r
+ },\r
+ "gpio21": {\r
+ "description": "GPIO21 Interrupt",\r
+ "value": "29"\r
+ },\r
+ "gpio22": {\r
+ "description": "GPIO22 Interrupt",\r
+ "value": "30"\r
+ },\r
+ "gpio23": {\r
+ "description": "GPIO23 Interrupt",\r
+ "value": "31"\r
+ },\r
+ "gpio24": {\r
+ "description": "GPIO24 Interrupt",\r
+ "value": "32"\r
+ },\r
+ "gpio25": {\r
+ "description": "GPIO25 Interrupt",\r
+ "value": "33"\r
+ },\r
+ "gpio26": {\r
+ "description": "GPIO26 Interrupt",\r
+ "value": "34"\r
+ },\r
+ "gpio27": {\r
+ "description": "GPIO27 Interrupt",\r
+ "value": "35"\r
+ },\r
+ "gpio28": {\r
+ "description": "GPIO28 Interrupt",\r
+ "value": "36"\r
+ },\r
+ "gpio29": {\r
+ "description": "GPIO29 Interrupt",\r
+ "value": "37"\r
+ },\r
+ "gpio30": {\r
+ "description": "GPIO30 Interrupt",\r
+ "value": "38"\r
+ },\r
+ "gpio31": {\r
+ "description": "GPIO31 Interrupt",\r
+ "value": "39"\r
+ }\r
+ }\r
+ },\r
+ "uart0": {\r
+ "description": "Universal Asynchronous Receiver/Transmitter (UART) Peripheral",\r
+ "baseAddress": "0x10013000",\r
+ "size": "0x1000",\r
+ "resetMask": "none",\r
+ "groupName": "uart",\r
+ "registers": {\r
+ "txdata": {\r
+ "description": "Transmit Data Register",\r
+ "addressOffset": "0x000",\r
+ "fields": {\r
+ "data": {\r
+ "description": "Transmit data",\r
+ "bitOffset": "0",\r
+ "bitWidth": "8"\r
+ },\r
+ "full": {\r
+ "description": "Transmit FIFO full",\r
+ "bitOffset": "31",\r
+ "bitWidth": "1"\r
+ }\r
+ }\r
+ },\r
+ "rxdata": {\r
+ "description": "Receive Data Register",\r
+ "addressOffset": "0x004",\r
+ "resetMask": "none",\r
+ "fields": {\r
+ "data": {\r
+ "description": "Received data",\r
+ "bitOffset": "0",\r
+ "bitWidth": "8",\r
+ "access": "r"\r
+ },\r
+ "empty": {\r
+ "description": "Receive FIFO empty",\r
+ "bitOffset": "31",\r
+ "bitWidth": "1"\r
+ }\r
+ }\r
+ },\r
+ "txctrl": {\r
+ "description": "Transmit Control Register ",\r
+ "addressOffset": "0x008",\r
+ "fields": {\r
+ "txen": {\r
+ "description": "Transmit enable",\r
+ "bitOffset": "0",\r
+ "bitWidth": "1",\r
+ "resetMask": "all",\r
+ "resetValue": "0x0"\r
+ },\r
+ "nstop": {\r
+ "description": "Number of stop bits",\r
+ "bitOffset": "1",\r
+ "bitWidth": "1",\r
+ "resetMask": "all",\r
+ "resetValue": "0x0"\r
+ },\r
+ "txcnt": {\r
+ "description": "Transmit watermark level",\r
+ "bitOffset": "16",\r
+ "bitWidth": "3",\r
+ "resetMask": "all",\r
+ "resetValue": "0x0"\r
+ }\r
+ }\r
+ },\r
+ "rxctrl": {\r
+ "description": "Receive Control Register",\r
+ "addressOffset": "0x00C",\r
+ "fields": {\r
+ "rxen": {\r
+ "description": "Receive enable",\r
+ "bitOffset": "0",\r
+ "bitWidth": "1",\r
+ "resetMask": "all",\r
+ "resetValue": "0x0"\r
+ },\r
+ "rxcnt": {\r
+ "description": "Receive watermark level",\r
+ "bitOffset": "16",\r
+ "bitWidth": "3",\r
+ "resetMask": "all",\r
+ "resetValue": "0x0"\r
+ }\r
+ }\r
+ },\r
+ "ie": {\r
+ "description": "Interrupt Enable Register",\r
+ "addressOffset": "0x010",\r
+ "fields": {\r
+ "txwm": {\r
+ "description": "Transmit watermark interrupt enable",\r
+ "bitOffset": "0",\r
+ "bitWidth": "1",\r
+ "resetMask": "all",\r
+ "resetValue": "0x0"\r
+ },\r
+ "rxwm": {\r
+ "description": "Receive watermark interrupt enable",\r
+ "bitOffset": "1",\r
+ "bitWidth": "1",\r
+ "resetMask": "all",\r
+ "resetValue": "0x0"\r
+ }\r
+ }\r
+ },\r
+ "ip": {\r
+ "description": "Interrupt Pending Register",\r
+ "addressOffset": "0x014",\r
+ "access": "r",\r
+ "fields": {\r
+ "txwm": {\r
+ "description": "Transmit watermark interrupt pending",\r
+ "bitOffset": "0",\r
+ "bitWidth": "1"\r
+ },\r
+ "rxwm": {\r
+ "description": "Receive watermark interrupt pending",\r
+ "bitOffset": "1",\r
+ "bitWidth": "1"\r
+ }\r
+ }\r
+ },\r
+ "div": {\r
+ "description": "Baud Rate Divisor Register",\r
+ "addressOffset": "0x018",\r
+ "fields": {\r
+ "value": {\r
+ "description": "Baud rate divisor",\r
+ "bitOffset": "0",\r
+ "bitWidth": "16",\r
+ "resetMask": "all",\r
+ "resetValue": "0x0000FFFF"\r
+ }\r
+ }\r
+ }\r
+ },\r
+ "interrupts": {\r
+ "uart0": {\r
+ "description": "UART0 Interrupt",\r
+ "value": "3"\r
+ }\r
+ }\r
+ },\r
+ "spi0": {\r
+ "description": "Serial Peripheral Interface (SPI) Peripheral",\r
+ "baseAddress": "0x10014000",\r
+ "size": "0x1000",\r
+ "resetMask": "none",\r
+ "groupName": "spi",\r
+ "registers": {\r
+ "sckdiv": {\r
+ "description": "Serial clock divisor Register",\r
+ "addressOffset": "0x000",\r
+ "fields": {\r
+ "scale": {\r
+ "description": "Divisor for serial clock",\r
+ "bitOffset": "0",\r
+ "bitWidth": "12",\r
+ "resetMask": "all",\r
+ "resetValue": "0x003"\r
+ }\r
+ }\r
+ },\r
+ "sckmode": {\r
+ "description": "Serial Clock Mode Register",\r
+ "addressOffset": "0x004",\r
+ "fields": {\r
+ "pha": {\r
+ "description": "Serial clock phase",\r
+ "bitOffset": "0",\r
+ "bitWidth": "1",\r
+ "resetMask": "all",\r
+ "resetValue": "0x0"\r
+ },\r
+ "pol": {\r
+ "description": "Serial clock polarity",\r
+ "bitOffset": "1",\r
+ "bitWidth": "1",\r
+ "resetMask": "all",\r
+ "resetValue": "0x0"\r
+ }\r
+ }\r
+ },\r
+ "csid": {\r
+ "description": "Chip Select ID Register",\r
+ "addressOffset": "0x010",\r
+ "resetMask": "all",\r
+ "resetValue": "0x00000000"\r
+ },\r
+ "csdef": {\r
+ "description": "Chip Select Default Register",\r
+ "addressOffset": "0x014",\r
+ "resetMask": "all",\r
+ "resetValue": "0x00000001"\r
+ },\r
+ "csmode": {\r
+ "description": "Chip Select Mode Register",\r
+ "addressOffset": "0x018",\r
+ "fields": {\r
+ "mode": {\r
+ "description": "Chip select mode",\r
+ "bitOffset": "0",\r
+ "bitWidth": "2",\r
+ "resetMask": "all",\r
+ "resetValue": "0x0",\r
+ "enumerations": {\r
+ "csmode-enum": {\r
+ "description": "Chip Select Modes Enumeration",\r
+ "values": {\r
+ "0": {\r
+ "displayName": "auto",\r
+ "description": "Assert/de-assert CS at the beginning/end of each frame"\r
+ },\r
+ "*": {\r
+ "displayName": "reserved"\r
+ },\r
+ "2": {\r
+ "displayName": "hold",\r
+ "description": "Keep CS continuously asserted after the initial frame"\r
+ },\r
+ "3": {\r
+ "displayName": "off",\r
+ "description": "Disable hardware control of the CS pin"\r
+ }\r
+ }\r
+ }\r
+ }\r
+ }\r
+ }\r
+ },\r
+ "delay0": {\r
+ "description": "Delay Control 0 Register",\r
+ "addressOffset": "0x028",\r
+ "fields": {\r
+ "cssck": {\r
+ "description": "CS to SCK Delay",\r
+ "bitOffset": "0",\r
+ "bitWidth": "8",\r
+ "resetMask": "all",\r
+ "resetValue": "0x01"\r
+ },\r
+ "sckcs": {\r
+ "description": "SCK to CS Delay",\r
+ "bitOffset": "16",\r
+ "bitWidth": "8",\r
+ "resetMask": "all",\r
+ "resetValue": "0x01"\r
+ }\r
+ }\r
+ },\r
+ "delay1": {\r
+ "description": "Delay Control 1 Register",\r
+ "addressOffset": "0x02C",\r
+ "fields": {\r
+ "intercs": {\r
+ "description": "Minimum CS inactive time",\r
+ "bitOffset": "0",\r
+ "bitWidth": "8",\r
+ "resetMask": "all",\r
+ "resetValue": "0x01"\r
+ },\r
+ "interxfr": {\r
+ "description": "Maximum interframe delay",\r
+ "bitOffset": "16",\r
+ "bitWidth": "8",\r
+ "resetMask": "all",\r
+ "resetValue": "0x01"\r
+ }\r
+ }\r
+ },\r
+ "fmt": {\r
+ "description": "Frame Format Register",\r
+ "addressOffset": "0x040",\r
+ "fields": {\r
+ "proto": {\r
+ "description": "SPI Protocol",\r
+ "bitOffset": "0",\r
+ "bitWidth": "2",\r
+ "resetMask": "all",\r
+ "resetValue": "0x0",\r
+ "enumerations": {\r
+ "proto-enum": {\r
+ "description": "SPI Protocol Enumeration",\r
+ "values": {\r
+ "0": {\r
+ "displayName": "single",\r
+ "description": "DQ0 (MOSI), DQ1 (MISO)"\r
+ },\r
+ "1": {\r
+ "displayName": "dual",\r
+ "description": "DQ0, DQ1"\r
+ },\r
+ "2": {\r
+ "displayName": "quad",\r
+ "description": "DQ0, DQ1, DQ2, DQ3"\r
+ },\r
+ "*": {\r
+ "displayName": "reserved"\r
+ }\r
+ }\r
+ }\r
+ }\r
+ },\r
+ "endian": {\r
+ "description": "SPI endianness",\r
+ "bitOffset": "2",\r
+ "bitWidth": "1",\r
+ "resetMask": "all",\r
+ "resetValue": "0x0",\r
+ "enumerations": {\r
+ "endian-enum": {\r
+ "description": "SPI Endianness Enumeration",\r
+ "values": {\r
+ "0": {\r
+ "displayName": "msb",\r
+ "description": "Transmit most-significant bit (MSB) first"\r
+ },\r
+ "1": {\r
+ "displayName": "lsb",\r
+ "description": "Transmit least-significant bit (LSB) first"\r
+ }\r
+ }\r
+ }\r
+ }\r
+ },\r
+ "dir": {\r
+ "description": "SPI I/O Direction",\r
+ "bitOffset": "3",\r
+ "bitWidth": "1",\r
+ "resetMask": "all",\r
+ "resetValue": "0x1",\r
+ "enumerations": {\r
+ "dir-enum": {\r
+ "description": "SPI I/O Direction Enumeration",\r
+ "values": {\r
+ "0": {\r
+ "displayName": "rx",\r
+ "description": "For dual and quad protocols, the DQ pins are tri-stated. For the single protocol, the DQ0 pin is driven with the transmit data as normal."\r
+ },\r
+ "1": {\r
+ "displayName": "tx",\r
+ "description": "The receive FIFO is not populated."\r
+ }\r
+ }\r
+ }\r
+ }\r
+ },\r
+ "len": {\r
+ "description": "Number of bits per frame",\r
+ "bitOffset": "16",\r
+ "bitWidth": "4",\r
+ "resetMask": "all",\r
+ "resetValue": "0x8"\r
+ }\r
+ }\r
+ },\r
+ "txdata": {\r
+ "description": "Tx FIFO Data Register",\r
+ "addressOffset": "0x048",\r
+ "fields": {\r
+ "data": {\r
+ "description": "Transmit data",\r
+ "bitOffset": "0",\r
+ "bitWidth": "8",\r
+ "resetMask": "all",\r
+ "resetValue": "0x00"\r
+ },\r
+ "full": {\r
+ "description": "FIFO full flag",\r
+ "bitOffset": "31",\r
+ "bitWidth": "1",\r
+ "access": "r"\r
+ }\r
+ }\r
+ },\r
+ "rxdata": {\r
+ "description": "Rx FIFO Data Register",\r
+ "addressOffset": "0x04C",\r
+ "resetMask": "none",\r
+ "access": "r",\r
+ "fields": {\r
+ "data": {\r
+ "description": "Received data",\r
+ "bitOffset": "0",\r
+ "bitWidth": "8"\r
+ },\r
+ "empty": {\r
+ "description": "FIFO empty flag",\r
+ "bitOffset": "31",\r
+ "bitWidth": "1"\r
+ }\r
+ }\r
+ },\r
+ "txmark": {\r
+ "description": "Tx FIFO Watermark Register",\r
+ "addressOffset": "0x050",\r
+ "fields": {\r
+ "value": {\r
+ "description": "Transmit watermark",\r
+ "bitOffset": "0",\r
+ "bitWidth": "3",\r
+ "resetMask": "all",\r
+ "resetValue": "0x1"\r
+ }\r
+ }\r
+ },\r
+ "rxmark": {\r
+ "description": "Rx FIFO Watermark Register",\r
+ "addressOffset": "0x054",\r
+ "fields": {\r
+ "value": {\r
+ "description": "Receive watermark",\r
+ "bitOffset": "0",\r
+ "bitWidth": "3",\r
+ "resetMask": "all",\r
+ "resetValue": "0x0"\r
+ }\r
+ }\r
+ },\r
+ "fctrl": {\r
+ "description": "Flash Interface Control Register",\r
+ "addressOffset": "0x060",\r
+ "fields": {\r
+ "en": {\r
+ "description": "SPI Flash Mode Select",\r
+ "bitOffset": "0",\r
+ "bitWidth": "1",\r
+ "resetMask": "all",\r
+ "resetValue": "0x1"\r
+ }\r
+ }\r
+ },\r
+ "ffmt": {\r
+ "description": "Flash Instruction Format Register",\r
+ "addressOffset": "0x064",\r
+ "fields": {\r
+ "cmden": {\r
+ "description": "Enable sending of command",\r
+ "bitOffset": "0",\r
+ "bitWidth": "1",\r
+ "resetMask": "all",\r
+ "resetValue": "0x1"\r
+ },\r
+ "addrlen": {\r
+ "description": "Number of address bytes(0 to 4)",\r
+ "bitOffset": "1",\r
+ "bitWidth": "3",\r
+ "resetMask": "all",\r
+ "resetValue": "0x3"\r
+ },\r
+ "padcnt": {\r
+ "description": "Number of dummy cycles",\r
+ "bitOffset": "4",\r
+ "bitWidth": "4",\r
+ "resetMask": "all",\r
+ "resetValue": "0x0"\r
+ },\r
+ "cmdproto": {\r
+ "description": "Protocol for transmitting command",\r
+ "bitOffset": "8",\r
+ "bitWidth": "2",\r
+ "resetMask": "all",\r
+ "resetValue": "0x0"\r
+ },\r
+ "addrproto": {\r
+ "description": "Protocol for transmitting address and padding",\r
+ "bitOffset": "10",\r
+ "bitWidth": "2",\r
+ "resetMask": "all",\r
+ "resetValue": "0x0"\r
+ },\r
+ "dataproto": {\r
+ "description": "Protocol for receiving data bytes",\r
+ "bitOffset": "12",\r
+ "bitWidth": "2",\r
+ "resetMask": "all",\r
+ "resetValue": "0x0"\r
+ },\r
+ "cmdcode": {\r
+ "description": "Value of command byte",\r
+ "bitOffset": "16",\r
+ "bitWidth": "8",\r
+ "resetMask": "all",\r
+ "resetValue": "0x03"\r
+ },\r
+ "padcode": {\r
+ "description": "First 8 bits to transmit during dummy cycles",\r
+ "bitOffset": "24",\r
+ "bitWidth": "8",\r
+ "resetMask": "all",\r
+ "resetValue": "0x0"\r
+ }\r
+ }\r
+ },\r
+ "ie": {\r
+ "description": "Interrupt Enable Register",\r
+ "addressOffset": "0x070",\r
+ "fields": {\r
+ "txwm": {\r
+ "description": "Transmit watermark enable",\r
+ "bitOffset": "0",\r
+ "bitWidth": "1",\r
+ "access": "r",\r
+ "resetMask": "all",\r
+ "resetValue": "0x0"\r
+ },\r
+ "rxwm": {\r
+ "description": "Receive watermark enable",\r
+ "bitOffset": "1",\r
+ "bitWidth": "1",\r
+ "access": "r",\r
+ "resetMask": "all",\r
+ "resetValue": "0x0"\r
+ }\r
+ }\r
+ },\r
+ "ip": {\r
+ "description": "Interrupt Pending Register",\r
+ "addressOffset": "0x074",\r
+ "fields": {\r
+ "txwm": {\r
+ "description": "Transmit watermark pending",\r
+ "bitOffset": "0",\r
+ "bitWidth": "1",\r
+ "access": "r"\r
+ },\r
+ "rxwm": {\r
+ "description": "Receive watermark pending",\r
+ "bitOffset": "1",\r
+ "bitWidth": "1",\r
+ "access": "r"\r
+ }\r
+ }\r
+ }\r
+ },\r
+ "interrupts": {\r
+ "spi0": {\r
+ "description": "SPI0 Interrupt",\r
+ "value": "5"\r
+ }\r
+ }\r
+ },\r
+ "pwm0": {\r
+ "description": "Pulse-Width Modulation (PWM) Peripheral",\r
+ "baseAddress": "0x10015000",\r
+ "size": "0x1000",\r
+ "resetMask": "none",\r
+ "registers": {\r
+ "cfg": {\r
+ "description": "Configuration Register",\r
+ "addressOffset": "0x000",\r
+ "fields": {\r
+ "scale": {\r
+ "description": "Counter scale",\r
+ "bitOffset": "0",\r
+ "bitWidth": "4"\r
+ },\r
+ "sticky": {\r
+ "description": "Sticky - disallow clearing pwmcmpXip bits",\r
+ "bitOffset": "8",\r
+ "bitWidth": "1"\r
+ },\r
+ "zerocmp": {\r
+ "description": "Zero - counter resets to zero after match",\r
+ "bitOffset": "9",\r
+ "bitWidth": "1"\r
+ },\r
+ "deglitch": {\r
+ "description": "Deglitch - latch pwmcmpXip within same cycle",\r
+ "bitOffset": "10",\r
+ "bitWidth": "1"\r
+ },\r
+ "enalways": {\r
+ "description": "Enable always - run continuously",\r
+ "bitOffset": "12",\r
+ "bitWidth": "1",\r
+ "resetMask": "all",\r
+ "resetValue": "0x0"\r
+ },\r
+ "enoneshot": {\r
+ "description": "enable one shot - run one cycle",\r
+ "bitOffset": "13",\r
+ "bitWidth": "1",\r
+ "resetMask": "all",\r
+ "resetValue": "0x0"\r
+ },\r
+ "cmp0center": {\r
+ "description": "PWM0 Compare Center",\r
+ "bitOffset": "16",\r
+ "bitWidth": "1"\r
+ },\r
+ "cmp1center": {\r
+ "description": "PWM1 Compare Center",\r
+ "bitOffset": "17",\r
+ "bitWidth": "1"\r
+ },\r
+ "cmp2center": {\r
+ "description": "PWM2 Compare Center",\r
+ "bitOffset": "18",\r
+ "bitWidth": "1"\r
+ },\r
+ "cmp3center": {\r
+ "description": "PWM3 Compare Center",\r
+ "bitOffset": "19",\r
+ "bitWidth": "1"\r
+ },\r
+ "cmp0gang": {\r
+ "description": "PWM0/PWM1 Compare Gang",\r
+ "bitOffset": "24",\r
+ "bitWidth": "1"\r
+ },\r
+ "cmp1gang": {\r
+ "description": "PWM1/PWM2 Compare Gang",\r
+ "bitOffset": "25",\r
+ "bitWidth": "1"\r
+ },\r
+ "cmp2gang": {\r
+ "description": "PWM2/PWM3 Compare Gang",\r
+ "bitOffset": "26",\r
+ "bitWidth": "1"\r
+ },\r
+ "cmp3gang": {\r
+ "description": "PWM3/PWM0 Compare Gang",\r
+ "bitOffset": "27",\r
+ "bitWidth": "1"\r
+ },\r
+ "cmp0ip": {\r
+ "description": "PWM0 Interrupt Pending",\r
+ "bitOffset": "28",\r
+ "bitWidth": "1"\r
+ },\r
+ "cmp1ip": {\r
+ "description": "PWM1 Interrupt Pending",\r
+ "bitOffset": "29",\r
+ "bitWidth": "1"\r
+ },\r
+ "cmp2ip": {\r
+ "description": "PWM2 Interrupt Pending",\r
+ "bitOffset": "30",\r
+ "bitWidth": "1"\r
+ },\r
+ "cmp3ip": {\r
+ "description": "PWM3 Interrupt Pending",\r
+ "bitOffset": "31",\r
+ "bitWidth": "1"\r
+ }\r
+ }\r
+ },\r
+ "count": {\r
+ "description": "Configuration Register",\r
+ "addressOffset": "0x008"\r
+ },\r
+ "scale": {\r
+ "description": "Scale Register",\r
+ "addressOffset": "0x010",\r
+ "fields": {\r
+ "value": {\r
+ "description": "Compare value",\r
+ "bitOffset": "0",\r
+ "bitWidth": "8"\r
+ }\r
+ }\r
+ },\r
+ "cmp": {\r
+ "arraySize": "4",\r
+ "description": "Compare Registers",\r
+ "addressOffset": "0x020",\r
+ "fields": {\r
+ "value": {\r
+ "description": "Compare value",\r
+ "bitOffset": "0",\r
+ "bitWidth": "8"\r
+ }\r
+ }\r
+ }\r
+ },\r
+ "interrupts": {\r
+ "pwm0cmp0": {\r
+ "description": "PWM0 Compare 0 Interrupt",\r
+ "value": "40"\r
+ },\r
+ "pwm0cmp1": {\r
+ "description": "PWM0 Compare 1 Interrupt",\r
+ "value": "41"\r
+ },\r
+ "pwm0cmp2": {\r
+ "description": "PWM0 Compare 2 Interrupt",\r
+ "value": "42"\r
+ },\r
+ "pwm0cmp3": {\r
+ "description": "PWM0 Compare 3 Interrupt",\r
+ "value": "43"\r
+ }\r
+ }\r
+ },\r
+ "uart1": {\r
+ "baseAddress": "0x10023000",\r
+ "derivedFrom": "uart0",\r
+ "groupName": "uart",\r
+ "interrupts": {\r
+ "uart1": {\r
+ "description": "UART1 Interrupt",\r
+ "value": "4"\r
+ }\r
+ }\r
+ },\r
+ "spi1": {\r
+ "baseAddress": "0x10024000",\r
+ "derivedFrom": "spi0",\r
+ "groupName": "spi",\r
+ "interrupts": {\r
+ "spi1": {\r
+ "description": "SPI1 Interrupt",\r
+ "value": "6"\r
+ }\r
+ }\r
+ },\r
+ "pwm1": {\r
+ "description": "Pulse-Width Modulation (PWM) Peripheral",\r
+ "baseAddress": "0x10025000",\r
+ "groupName": "pwm",\r
+ "size": "0x1000",\r
+ "resetMask": "none",\r
+ "groupName": "pwm",\r
+ "registers": {\r
+ "cfg": {\r
+ "description": "Configuration Register",\r
+ "addressOffset": "0x000",\r
+ "fields": {\r
+ "scale": {\r
+ "description": "Counter scale",\r
+ "bitOffset": "0",\r
+ "bitWidth": "4"\r
+ },\r
+ "sticky": {\r
+ "description": "Sticky - disallow clearing pwmcmpXip bits",\r
+ "bitOffset": "8",\r
+ "bitWidth": "1"\r
+ },\r
+ "zerocmp": {\r
+ "description": "Zero - counter resets to zero after match",\r
+ "bitOffset": "9",\r
+ "bitWidth": "1"\r
+ },\r
+ "deglitch": {\r
+ "description": "Deglitch - latch pwmcmpXip within same cycle",\r
+ "bitOffset": "10",\r
+ "bitWidth": "1"\r
+ },\r
+ "enalways": {\r
+ "description": "Enable always - run continuously",\r
+ "bitOffset": "12",\r
+ "bitWidth": "1",\r
+ "resetMask": "all",\r
+ "resetValue": "0x0"\r
+ },\r
+ "enoneshot": {\r
+ "description": "enable one shot - run one cycle",\r
+ "bitOffset": "13",\r
+ "bitWidth": "1",\r
+ "resetMask": "all",\r
+ "resetValue": "0x0"\r
+ },\r
+ "cmp0center": {\r
+ "description": "PWM0 Compare Center",\r
+ "bitOffset": "16",\r
+ "bitWidth": "1"\r
+ },\r
+ "cmp1center": {\r
+ "description": "PWM1 Compare Center",\r
+ "bitOffset": "17",\r
+ "bitWidth": "1"\r
+ },\r
+ "cmp2center": {\r
+ "description": "PWM2 Compare Center",\r
+ "bitOffset": "18",\r
+ "bitWidth": "1"\r
+ },\r
+ "cmp3center": {\r
+ "description": "PWM3 Compare Center",\r
+ "bitOffset": "19",\r
+ "bitWidth": "1"\r
+ },\r
+ "cmp0gang": {\r
+ "description": "PWM0/PWM1 Compare Gang",\r
+ "bitOffset": "24",\r
+ "bitWidth": "1"\r
+ },\r
+ "cmp1gang": {\r
+ "description": "PWM1/PWM2 Compare Gang",\r
+ "bitOffset": "25",\r
+ "bitWidth": "1"\r
+ },\r
+ "cmp2gang": {\r
+ "description": "PWM2/PWM3 Compare Gang",\r
+ "bitOffset": "26",\r
+ "bitWidth": "1"\r
+ },\r
+ "cmp3gang": {\r
+ "description": "PWM3/PWM0 Compare Gang",\r
+ "bitOffset": "27",\r
+ "bitWidth": "1"\r
+ },\r
+ "cmp0ip": {\r
+ "description": "PWM0 Interrupt Pending",\r
+ "bitOffset": "28",\r
+ "bitWidth": "1"\r
+ },\r
+ "cmp1ip": {\r
+ "description": "PWM1 Interrupt Pending",\r
+ "bitOffset": "29",\r
+ "bitWidth": "1"\r
+ },\r
+ "cmp2ip": {\r
+ "description": "PWM2 Interrupt Pending",\r
+ "bitOffset": "30",\r
+ "bitWidth": "1"\r
+ },\r
+ "cmp3ip": {\r
+ "description": "PWM3 Interrupt Pending",\r
+ "bitOffset": "31",\r
+ "bitWidth": "1"\r
+ }\r
+ }\r
+ },\r
+ "count": {\r
+ "description": "Configuration Register",\r
+ "addressOffset": "0x008"\r
+ },\r
+ "scale": {\r
+ "description": "Scale Register",\r
+ "addressOffset": "0x010",\r
+ "fields": {\r
+ "value": {\r
+ "description": "Compare value",\r
+ "bitOffset": "0",\r
+ "bitWidth": "16"\r
+ }\r
+ }\r
+ },\r
+ "cmp": {\r
+ "arraySize": "4",\r
+ "description": "Compare Registers",\r
+ "addressOffset": "0x020",\r
+ "fields": {\r
+ "value": {\r
+ "description": "Compare value",\r
+ "bitOffset": "0",\r
+ "bitWidth": "16"\r
+ }\r
+ }\r
+ }\r
+ },\r
+ "interrupts": {\r
+ "pwm1cmp0": {\r
+ "description": "PWM1 Compare 0 Interrupt",\r
+ "value": "44"\r
+ },\r
+ "pwm1cmp1": {\r
+ "description": "PWM1 Compare 1 Interrupt",\r
+ "value": "45"\r
+ },\r
+ "pwm1cmp2": {\r
+ "description": "PWM1 Compare 2 Interrupt",\r
+ "value": "46"\r
+ },\r
+ "pwm1cmp3": {\r
+ "description": "PWM1 Compare 3 Interrupt",\r
+ "value": "47"\r
+ }\r
+ }\r
+ },\r
+ "spi2": {\r
+ "baseAddress": "0x10034000",\r
+ "derivedFrom": "spi0",\r
+ "groupName": "spi",\r
+ "interrupts": {\r
+ "spi2": {\r
+ "description": "SPI2 Interrupt",\r
+ "value": "7"\r
+ }\r
+ }\r
+ },\r
+ "pwm2": {\r
+ "baseAddress": "0x10035000",\r
+ "derivedFrom": "pwm1",\r
+ "groupName": "pwm",\r
+ "interrupts": {\r
+ "pwm2cmp0": {\r
+ "description": "PWM2 Compare 0 Interrupt",\r
+ "value": "48"\r
+ },\r
+ "pwm2cmp1": {\r
+ "description": "PWM2 Compare 1 Interrupt",\r
+ "value": "49"\r
+ },\r
+ "pwm2cmp2": {\r
+ "description": "PWM2 Compare 2 Interrupt",\r
+ "value": "50"\r
+ },\r
+ "pwm2cmp3": {\r
+ "description": "PWM2 Compare 3 Interrupt",\r
+ "value": "51"\r
+ }\r
+ }\r
+ }\r
+ }\r
+ }\r
+ }\r
+}
\ No newline at end of file
--- /dev/null
+
+This software, except as otherwise noted in subrepositories,
+is licensed under the Apache 2 license, quoted below.
+
+
+ Apache License
+ Version 2.0, January 2004
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+
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+ Copyright 2016 SiFive, Inc.
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
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+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
--- /dev/null
+// See LICENSE file for license details\r
+\r
+#include "platform.h"\r
+\r
+#ifdef PRCI_CTRL_ADDR\r
+#include "fe300prci/fe300prci_driver.h"\r
+#include <unistd.h>\r
+\r
+#define rdmcycle(x) { \\r
+ uint32_t lo, hi, hi2; \\r
+ __asm__ __volatile__ ("1:\n\t" \\r
+ "csrr %0, mcycleh\n\t" \\r
+ "csrr %1, mcycle\n\t" \\r
+ "csrr %2, mcycleh\n\t" \\r
+ "bne %0, %2, 1b\n\t" \\r
+ : "=r" (hi), "=r" (lo), "=r" (hi2)) ; \\r
+ *(x) = lo | ((uint64_t) hi << 32); \\r
+ }\r
+\r
+uint32_t PRCI_measure_mcycle_freq(uint32_t mtime_ticks, uint32_t mtime_freq)\r
+{\r
+\r
+ uint32_t start_mtime = CLINT_REG(CLINT_MTIME);\r
+ uint32_t end_mtime = start_mtime + mtime_ticks + 1;\r
+\r
+ // Make sure we won't get rollover.\r
+ while (end_mtime < start_mtime){\r
+ start_mtime = CLINT_REG(CLINT_MTIME);\r
+ end_mtime = start_mtime + mtime_ticks + 1;\r
+ }\r
+\r
+ // Don't start measuring until mtime edge.\r
+ uint32_t tmp = start_mtime;\r
+ do {\r
+ start_mtime = CLINT_REG(CLINT_MTIME);\r
+ } while (start_mtime == tmp);\r
+ \r
+ uint64_t start_mcycle;\r
+ rdmcycle(&start_mcycle);\r
+ \r
+ while (CLINT_REG(CLINT_MTIME) < end_mtime) ;\r
+ \r
+ uint64_t end_mcycle;\r
+ rdmcycle(&end_mcycle);\r
+ uint32_t difference = (uint32_t) (end_mcycle - start_mcycle);\r
+\r
+ uint64_t freq = ((uint64_t) difference * mtime_freq) / mtime_ticks;\r
+ return (uint32_t) freq & 0xFFFFFFFF;\r
+ \r
+}\r
+ \r
+\r
+void PRCI_use_hfrosc(int div, int trim)\r
+{\r
+ // Make sure the HFROSC is running at its default setting\r
+ // It is OK to change this even if we are running off of it.\r
+ \r
+ PRCI_REG(PRCI_HFROSCCFG) = (ROSC_DIV(div) | ROSC_TRIM(trim) | ROSC_EN(1));\r
+\r
+ while ((PRCI_REG(PRCI_HFROSCCFG) & ROSC_RDY(1)) == 0);\r
+ \r
+ PRCI_REG(PRCI_PLLCFG) &= ~PLL_SEL(1);\r
+}\r
+\r
+void PRCI_use_pll(int refsel, int bypass,\r
+ int r, int f, int q, int finaldiv,\r
+ int hfroscdiv, int hfrosctrim)\r
+{\r
+ // Ensure that we aren't running off the PLL before we mess with it.\r
+ if (PRCI_REG(PRCI_PLLCFG) & PLL_SEL(1)) {\r
+ // Make sure the HFROSC is running at its default setting\r
+ PRCI_use_hfrosc(4, 16);\r
+ }\r
+ \r
+ // Set PLL Source to be HFXOSC if desired.\r
+ uint32_t config_value = 0;\r
+\r
+ config_value |= PLL_REFSEL(refsel);\r
+ \r
+ if (bypass) {\r
+ // Bypass\r
+ config_value |= PLL_BYPASS(1);\r
+\r
+ PRCI_REG(PRCI_PLLCFG) = config_value;\r
+\r
+ // If we don't have an HFXTAL, this doesn't really matter.\r
+ // Set our Final output divide to divide-by-1:\r
+ PRCI_REG(PRCI_PLLDIV) = (PLL_FINAL_DIV_BY_1(1) | PLL_FINAL_DIV(0));\r
+ } else {\r
+ \r
+ // To overclock, use the hfrosc\r
+ if (hfrosctrim >= 0 && hfroscdiv >= 0) {\r
+ PRCI_use_hfrosc(hfroscdiv, hfrosctrim);\r
+ }\r
+ \r
+ // Set DIV Settings for PLL\r
+ \r
+ // (Legal values of f_REF are 6-48MHz)\r
+\r
+ // Set DIVR to divide-by-2 to get 8MHz frequency\r
+ // (legal values of f_R are 6-12 MHz)\r
+\r
+ config_value |= PLL_BYPASS(1);\r
+ config_value |= PLL_R(r);\r
+\r
+ // Set DIVF to get 512Mhz frequncy\r
+ // There is an implied multiply-by-2, 16Mhz.\r
+ // So need to write 32-1\r
+ // (legal values of f_F are 384-768 MHz)\r
+ config_value |= PLL_F(f);\r
+\r
+ // Set DIVQ to divide-by-2 to get 256 MHz frequency\r
+ // (legal values of f_Q are 50-400Mhz)\r
+ config_value |= PLL_Q(q);\r
+\r
+ // Set our Final output divide to divide-by-1:\r
+ if (finaldiv == 1){\r
+ PRCI_REG(PRCI_PLLDIV) = (PLL_FINAL_DIV_BY_1(1) | PLL_FINAL_DIV(0));\r
+ } else {\r
+ PRCI_REG(PRCI_PLLDIV) = (PLL_FINAL_DIV(finaldiv-1));\r
+ }\r
+\r
+ PRCI_REG(PRCI_PLLCFG) = config_value;\r
+\r
+ // Un-Bypass the PLL.\r
+ PRCI_REG(PRCI_PLLCFG) &= ~PLL_BYPASS(1);\r
+\r
+ // Wait for PLL Lock\r
+ // Note that the Lock signal can be glitchy.\r
+ // Need to wait 100 us\r
+ // RTC is running at 32kHz.\r
+ // So wait 4 ticks of RTC.\r
+ uint32_t now = CLINT_REG(CLINT_MTIME);\r
+ while (CLINT_REG(CLINT_MTIME) - now < 4) ;\r
+ \r
+ // Now it is safe to check for PLL Lock\r
+ while ((PRCI_REG(PRCI_PLLCFG) & PLL_LOCK(1)) == 0);\r
+\r
+ }\r
+\r
+ // Switch over to PLL Clock source\r
+ PRCI_REG(PRCI_PLLCFG) |= PLL_SEL(1);\r
+\r
+ // If we're running off HFXOSC, turn off the HFROSC to\r
+ // save power.\r
+ if (refsel) {\r
+ PRCI_REG(PRCI_HFROSCCFG) &= ~ROSC_EN(1);\r
+ }\r
+ \r
+}\r
+\r
+void PRCI_use_default_clocks()\r
+{\r
+ // Turn off the LFROSC\r
+ AON_REG(AON_LFROSC) &= ~ROSC_EN(1);\r
+\r
+ // Use HFROSC\r
+ PRCI_use_hfrosc(4, 16);\r
+}\r
+\r
+void PRCI_use_hfxosc(uint32_t finaldiv)\r
+{\r
+ \r
+ PRCI_use_pll(1, // Use HFXTAL\r
+ 1, // Bypass = 1\r
+ 0, // PLL settings don't matter\r
+ 0, // PLL settings don't matter\r
+ 0, // PLL settings don't matter\r
+ finaldiv,\r
+ -1,\r
+ -1);\r
+}\r
+\r
+// This is a generic function, which\r
+// doesn't span the entire range of HFROSC settings.\r
+// It only adjusts the trim, which can span a hundred MHz or so.\r
+// This function does not check the legality of the PLL settings\r
+// at all, and it is quite possible to configure invalid PLL settings\r
+// this way.\r
+// It returns the actual measured CPU frequency.\r
+\r
+uint32_t PRCI_set_hfrosctrim_for_f_cpu(uint32_t f_cpu, PRCI_freq_target target )\r
+{\r
+\r
+ uint32_t hfrosctrim = 0;\r
+ uint32_t hfroscdiv = 4;\r
+ uint32_t prev_trim = 0;\r
+\r
+ // In this function we use PLL settings which\r
+ // will give us a 32x multiplier from the output\r
+ // of the HFROSC source to the output of the\r
+ // PLL. We first measure our HFROSC to get the\r
+ // right trim, then finally use it as the PLL source.\r
+ // We should really check here that the f_cpu\r
+ // requested is something in the limit of the PLL. For\r
+ // now that is up to the user.\r
+\r
+ // This will undershoot for frequencies not divisible by 16.\r
+ uint32_t desired_hfrosc_freq = (f_cpu/ 16);\r
+\r
+ PRCI_use_hfrosc(hfroscdiv, hfrosctrim);\r
+ \r
+ // Ignore the first run (for icache reasons)\r
+ uint32_t cpu_freq = PRCI_measure_mcycle_freq(3000, RTC_FREQ);\r
+\r
+ cpu_freq = PRCI_measure_mcycle_freq(3000, RTC_FREQ);\r
+ uint32_t prev_freq = cpu_freq;\r
+ \r
+ while ((cpu_freq < desired_hfrosc_freq) && (hfrosctrim < 0x1F)){\r
+ prev_trim = hfrosctrim;\r
+ prev_freq = cpu_freq;\r
+ hfrosctrim ++;\r
+ PRCI_use_hfrosc(hfroscdiv, hfrosctrim);\r
+ cpu_freq = PRCI_measure_mcycle_freq(3000, RTC_FREQ);\r
+ } \r
+\r
+ // We couldn't go low enough\r
+ if (prev_freq > desired_hfrosc_freq){\r
+ PRCI_use_pll(0, 0, 1, 31, 1, 1, hfroscdiv, prev_trim);\r
+ cpu_freq = PRCI_measure_mcycle_freq(1000, RTC_FREQ);\r
+ return cpu_freq;\r
+ }\r
+ \r
+ // We couldn't go high enough\r
+ if (cpu_freq < desired_hfrosc_freq){\r
+ PRCI_use_pll(0, 0, 1, 31, 1, 1, hfroscdiv, prev_trim);\r
+ cpu_freq = PRCI_measure_mcycle_freq(1000, RTC_FREQ);\r
+ return cpu_freq;\r
+ }\r
+\r
+ // Check for over/undershoot\r
+ switch(target) {\r
+ case(PRCI_FREQ_CLOSEST):\r
+ if ((desired_hfrosc_freq - prev_freq) < (cpu_freq - desired_hfrosc_freq)) {\r
+ PRCI_use_pll(0, 0, 1, 31, 1, 1, hfroscdiv, prev_trim);\r
+ } else {\r
+ PRCI_use_pll(0, 0, 1, 31, 1, 1, hfroscdiv, hfrosctrim);\r
+ }\r
+ break;\r
+ case(PRCI_FREQ_UNDERSHOOT):\r
+ PRCI_use_pll(0, 0, 1, 31, 1, 1, hfroscdiv, prev_trim);\r
+ break;\r
+ default:\r
+ PRCI_use_pll(0, 0, 1, 31, 1, 1, hfroscdiv, hfrosctrim);\r
+ }\r
+\r
+ cpu_freq = PRCI_measure_mcycle_freq(1000, RTC_FREQ);\r
+ return cpu_freq;\r
+\r
+}\r
+\r
+#endif\r
--- /dev/null
+// See LICENSE file for license details\r
+\r
+#ifndef _FE300PRCI_DRIVER_H_\r
+#define _FE300PRCI_DRIVER_H_\r
+\r
+__BEGIN_DECLS\r
+\r
+#include <unistd.h>\r
+\r
+typedef enum prci_freq_target {\r
+ \r
+ PRCI_FREQ_OVERSHOOT,\r
+ PRCI_FREQ_CLOSEST,\r
+ PRCI_FREQ_UNDERSHOOT\r
+\r
+} PRCI_freq_target;\r
+\r
+/* Measure and return the approximate frequency of the \r
+ * CPU, as given by measuring the mcycle counter against \r
+ * the mtime ticks.\r
+ */\r
+uint32_t PRCI_measure_mcycle_freq(uint32_t mtime_ticks, uint32_t mtime_freq);\r
+\r
+/* Safely switch over to the HFROSC using the given div\r
+ * and trim settings.\r
+ */\r
+void PRCI_use_hfrosc(int div, int trim);\r
+\r
+/* Safely switch over to the 16MHz HFXOSC,\r
+ * applying the finaldiv clock divider (1 is the lowest\r
+ * legal value).\r
+ */\r
+void PRCI_use_hfxosc(uint32_t finaldiv);\r
+\r
+/* Safely switch over to the PLL using the given\r
+ * settings.\r
+ * \r
+ * Note that not all combinations of the inputs are actually\r
+ * legal, and this function does not check for their\r
+ * legality ("safely" means that this function won't turn off\r
+ * or glitch the clock the CPU is actually running off, but\r
+ * doesn't protect against you making it too fast or slow.)\r
+ */\r
+\r
+void PRCI_use_pll(int refsel, int bypass,\r
+ int r, int f, int q, int finaldiv,\r
+ int hfroscdiv, int hfrosctrim);\r
+\r
+/* Use the default clocks configured at reset.\r
+ * This is ~16Mhz HFROSC and turns off the LFROSC\r
+ * (on the current FE310 Dev Platforms, an external LFROSC is \r
+ * used as it is more power efficient).\r
+ */\r
+void PRCI_use_default_clocks();\r
+\r
+/* This routine will adjust the HFROSC trim\r
+ * while using HFROSC as the clock source, \r
+ * measure the resulting frequency, then\r
+ * use it as the PLL clock source, \r
+ * in an attempt to get over, under, or close to the \r
+ * requested frequency. It returns the actual measured \r
+ * frequency. \r
+ *\r
+ * Note that the requested frequency must be within the \r
+ * range supported by the PLL so not all values are \r
+ * achievable with this function, and not all \r
+ * are guaranteed to actually work. The PLL\r
+ * is rated higher than the hardware.\r
+ * \r
+ * There is no check on the desired f_cpu frequency, it\r
+ * is up to the user to specify something reasonable.\r
+ */\r
+\r
+uint32_t PRCI_set_hfrosctrim_for_f_cpu(uint32_t f_cpu, PRCI_freq_target target);\r
+\r
+__END_DECLS\r
+\r
+#endif\r
+ \r
--- /dev/null
+// See LICENSE for license details.\r
+\r
+#include "sifive/devices/plic.h"\r
+#include "plic/plic_driver.h"\r
+#include "platform.h"\r
+#include "encoding.h"\r
+#include <string.h>\r
+\r
+\r
+// Note that there are no assertions or bounds checking on these\r
+// parameter values.\r
+\r
+void volatile_memzero(uint8_t * base, unsigned int size)\r
+{\r
+ volatile uint8_t * ptr;\r
+ for (ptr = base; ptr < (base + size); ptr++){\r
+ *ptr = 0;\r
+ }\r
+}\r
+\r
+void PLIC_init (\r
+ plic_instance_t * this_plic,\r
+ uintptr_t base_addr,\r
+ uint32_t num_sources,\r
+ uint32_t num_priorities\r
+ )\r
+{\r
+ \r
+ this_plic->base_addr = base_addr;\r
+ this_plic->num_sources = num_sources;\r
+ this_plic->num_priorities = num_priorities;\r
+ \r
+ // Disable all interrupts (don't assume that these registers are reset).\r
+ unsigned long hart_id = read_csr(mhartid);\r
+ volatile_memzero((uint8_t*) (this_plic->base_addr +\r
+ PLIC_ENABLE_OFFSET +\r
+ (hart_id << PLIC_ENABLE_SHIFT_PER_TARGET)),\r
+ (num_sources + 8) / 8);\r
+ \r
+ // Set all priorities to 0 (equal priority -- don't assume that these are reset).\r
+ volatile_memzero ((uint8_t *)(this_plic->base_addr +\r
+ PLIC_PRIORITY_OFFSET),\r
+ (num_sources + 1) << PLIC_PRIORITY_SHIFT_PER_SOURCE);\r
+\r
+ // Set the threshold to 0.\r
+ volatile plic_threshold* threshold = (plic_threshold*)\r
+ (this_plic->base_addr +\r
+ PLIC_THRESHOLD_OFFSET +\r
+ (hart_id << PLIC_THRESHOLD_SHIFT_PER_TARGET));\r
+\r
+ *threshold = 0;\r
+ \r
+}\r
+\r
+void PLIC_set_threshold (plic_instance_t * this_plic,\r
+ plic_threshold threshold){\r
+\r
+ unsigned long hart_id = read_csr(mhartid); \r
+ volatile plic_threshold* threshold_ptr = (plic_threshold*) (this_plic->base_addr +\r
+ PLIC_THRESHOLD_OFFSET +\r
+ (hart_id << PLIC_THRESHOLD_SHIFT_PER_TARGET));\r
+\r
+ *threshold_ptr = threshold;\r
+\r
+}\r
+ \r
+\r
+void PLIC_enable_interrupt (plic_instance_t * this_plic, plic_source source){\r
+\r
+ unsigned long hart_id = read_csr(mhartid);\r
+ volatile uint8_t * current_ptr = (volatile uint8_t *)(this_plic->base_addr +\r
+ PLIC_ENABLE_OFFSET +\r
+ (hart_id << PLIC_ENABLE_SHIFT_PER_TARGET) +\r
+ (source >> 3));\r
+ uint8_t current = *current_ptr;\r
+ current = current | ( 1 << (source & 0x7));\r
+ *current_ptr = current;\r
+\r
+}\r
+\r
+void PLIC_disable_interrupt (plic_instance_t * this_plic, plic_source source){\r
+ \r
+ unsigned long hart_id = read_csr(mhartid);\r
+ volatile uint8_t * current_ptr = (volatile uint8_t *) (this_plic->base_addr +\r
+ PLIC_ENABLE_OFFSET +\r
+ (hart_id << PLIC_ENABLE_SHIFT_PER_TARGET) +\r
+ (source >> 3));\r
+ uint8_t current = *current_ptr;\r
+ current = current & ~(( 1 << (source & 0x7)));\r
+ *current_ptr = current;\r
+ \r
+}\r
+\r
+void PLIC_set_priority (plic_instance_t * this_plic, plic_source source, plic_priority priority){\r
+\r
+ if (this_plic->num_priorities > 0) {\r
+ volatile plic_priority * priority_ptr = (volatile plic_priority *)\r
+ (this_plic->base_addr +\r
+ PLIC_PRIORITY_OFFSET +\r
+ (source << PLIC_PRIORITY_SHIFT_PER_SOURCE));\r
+ *priority_ptr = priority;\r
+ }\r
+}\r
+\r
+plic_source PLIC_claim_interrupt(plic_instance_t * this_plic){\r
+ \r
+ unsigned long hart_id = read_csr(mhartid);\r
+\r
+ volatile plic_source * claim_addr = (volatile plic_source * )\r
+ (this_plic->base_addr +\r
+ PLIC_CLAIM_OFFSET +\r
+ (hart_id << PLIC_CLAIM_SHIFT_PER_TARGET));\r
+\r
+ return *claim_addr;\r
+ \r
+}\r
+\r
+void PLIC_complete_interrupt(plic_instance_t * this_plic, plic_source source){\r
+ \r
+ unsigned long hart_id = read_csr(mhartid);\r
+ volatile plic_source * claim_addr = (volatile plic_source *) (this_plic->base_addr +\r
+ PLIC_CLAIM_OFFSET +\r
+ (hart_id << PLIC_CLAIM_SHIFT_PER_TARGET));\r
+ *claim_addr = source;\r
+ \r
+}\r
+\r
--- /dev/null
+// See LICENSE file for licence details\r
+\r
+#ifndef PLIC_DRIVER_H\r
+#define PLIC_DRIVER_H\r
+\r
+\r
+__BEGIN_DECLS\r
+\r
+#include "platform.h"\r
+\r
+typedef struct __plic_instance_t\r
+{\r
+ uintptr_t base_addr;\r
+\r
+ uint32_t num_sources;\r
+ uint32_t num_priorities;\r
+ \r
+} plic_instance_t;\r
+\r
+typedef uint32_t plic_source;\r
+typedef uint32_t plic_priority;\r
+typedef uint32_t plic_threshold;\r
+\r
+void PLIC_init (\r
+ plic_instance_t * this_plic,\r
+ uintptr_t base_addr,\r
+ uint32_t num_sources,\r
+ uint32_t num_priorities\r
+ );\r
+\r
+void PLIC_set_threshold (plic_instance_t * this_plic,\r
+ plic_threshold threshold);\r
+ \r
+void PLIC_enable_interrupt (plic_instance_t * this_plic,\r
+ plic_source source);\r
+\r
+void PLIC_disable_interrupt (plic_instance_t * this_plic,\r
+ plic_source source);\r
+ \r
+void PLIC_set_priority (plic_instance_t * this_plic,\r
+ plic_source source,\r
+ plic_priority priority);\r
+\r
+plic_source PLIC_claim_interrupt(plic_instance_t * this_plic);\r
+\r
+void PLIC_complete_interrupt(plic_instance_t * this_plic,\r
+ plic_source source);\r
+\r
+__END_DECLS\r
+\r
+#endif\r
--- /dev/null
+// See LICENSE for license details.\r
+\r
+#ifndef RISCV_CSR_ENCODING_H\r
+#define RISCV_CSR_ENCODING_H\r
+\r
+#define MSTATUS_UIE 0x00000001\r
+#define MSTATUS_SIE 0x00000002\r
+#define MSTATUS_HIE 0x00000004\r
+#define MSTATUS_MIE 0x00000008\r
+#define MSTATUS_UPIE 0x00000010\r
+#define MSTATUS_SPIE 0x00000020\r
+#define MSTATUS_HPIE 0x00000040\r
+#define MSTATUS_MPIE 0x00000080\r
+#define MSTATUS_SPP 0x00000100\r
+#define MSTATUS_HPP 0x00000600\r
+#define MSTATUS_MPP 0x00001800\r
+#define MSTATUS_FS 0x00006000\r
+#define MSTATUS_XS 0x00018000\r
+#define MSTATUS_MPRV 0x00020000\r
+#define MSTATUS_PUM 0x00040000\r
+#define MSTATUS_MXR 0x00080000\r
+#define MSTATUS_VM 0x1F000000\r
+#define MSTATUS32_SD 0x80000000\r
+#define MSTATUS64_SD 0x8000000000000000\r
+\r
+#define SSTATUS_UIE 0x00000001\r
+#define SSTATUS_SIE 0x00000002\r
+#define SSTATUS_UPIE 0x00000010\r
+#define SSTATUS_SPIE 0x00000020\r
+#define SSTATUS_SPP 0x00000100\r
+#define SSTATUS_FS 0x00006000\r
+#define SSTATUS_XS 0x00018000\r
+#define SSTATUS_PUM 0x00040000\r
+#define SSTATUS32_SD 0x80000000\r
+#define SSTATUS64_SD 0x8000000000000000\r
+\r
+#define DCSR_XDEBUGVER (3U<<30)\r
+#define DCSR_NDRESET (1<<29)\r
+#define DCSR_FULLRESET (1<<28)\r
+#define DCSR_EBREAKM (1<<15)\r
+#define DCSR_EBREAKH (1<<14)\r
+#define DCSR_EBREAKS (1<<13)\r
+#define DCSR_EBREAKU (1<<12)\r
+#define DCSR_STOPCYCLE (1<<10)\r
+#define DCSR_STOPTIME (1<<9)\r
+#define DCSR_CAUSE (7<<6)\r
+#define DCSR_DEBUGINT (1<<5)\r
+#define DCSR_HALT (1<<3)\r
+#define DCSR_STEP (1<<2)\r
+#define DCSR_PRV (3<<0)\r
+\r
+#define DCSR_CAUSE_NONE 0\r
+#define DCSR_CAUSE_SWBP 1\r
+#define DCSR_CAUSE_HWBP 2\r
+#define DCSR_CAUSE_DEBUGINT 3\r
+#define DCSR_CAUSE_STEP 4\r
+#define DCSR_CAUSE_HALT 5\r
+\r
+#define MCONTROL_TYPE(xlen) (0xfULL<<((xlen)-4))\r
+#define MCONTROL_DMODE(xlen) (1ULL<<((xlen)-5))\r
+#define MCONTROL_MASKMAX(xlen) (0x3fULL<<((xlen)-11))\r
+\r
+#define MCONTROL_SELECT (1<<19)\r
+#define MCONTROL_TIMING (1<<18)\r
+#define MCONTROL_ACTION (0x3f<<12)\r
+#define MCONTROL_CHAIN (1<<11)\r
+#define MCONTROL_MATCH (0xf<<7)\r
+#define MCONTROL_M (1<<6)\r
+#define MCONTROL_H (1<<5)\r
+#define MCONTROL_S (1<<4)\r
+#define MCONTROL_U (1<<3)\r
+#define MCONTROL_EXECUTE (1<<2)\r
+#define MCONTROL_STORE (1<<1)\r
+#define MCONTROL_LOAD (1<<0)\r
+\r
+#define MCONTROL_TYPE_NONE 0\r
+#define MCONTROL_TYPE_MATCH 2\r
+\r
+#define MCONTROL_ACTION_DEBUG_EXCEPTION 0\r
+#define MCONTROL_ACTION_DEBUG_MODE 1\r
+#define MCONTROL_ACTION_TRACE_START 2\r
+#define MCONTROL_ACTION_TRACE_STOP 3\r
+#define MCONTROL_ACTION_TRACE_EMIT 4\r
+\r
+#define MCONTROL_MATCH_EQUAL 0\r
+#define MCONTROL_MATCH_NAPOT 1\r
+#define MCONTROL_MATCH_GE 2\r
+#define MCONTROL_MATCH_LT 3\r
+#define MCONTROL_MATCH_MASK_LOW 4\r
+#define MCONTROL_MATCH_MASK_HIGH 5\r
+\r
+#define MIP_SSIP (1 << IRQ_S_SOFT)\r
+#define MIP_HSIP (1 << IRQ_H_SOFT)\r
+#define MIP_MSIP (1 << IRQ_M_SOFT)\r
+#define MIP_STIP (1 << IRQ_S_TIMER)\r
+#define MIP_HTIP (1 << IRQ_H_TIMER)\r
+#define MIP_MTIP (1 << IRQ_M_TIMER)\r
+#define MIP_SEIP (1 << IRQ_S_EXT)\r
+#define MIP_HEIP (1 << IRQ_H_EXT)\r
+#define MIP_MEIP (1 << IRQ_M_EXT)\r
+\r
+#define SIP_SSIP MIP_SSIP\r
+#define SIP_STIP MIP_STIP\r
+\r
+#define PRV_U 0\r
+#define PRV_S 1\r
+#define PRV_H 2\r
+#define PRV_M 3\r
+\r
+#define VM_MBARE 0\r
+#define VM_MBB 1\r
+#define VM_MBBID 2\r
+#define VM_SV32 8\r
+#define VM_SV39 9\r
+#define VM_SV48 10\r
+\r
+#define IRQ_S_SOFT 1\r
+#define IRQ_H_SOFT 2\r
+#define IRQ_M_SOFT 3\r
+#define IRQ_S_TIMER 5\r
+#define IRQ_H_TIMER 6\r
+#define IRQ_M_TIMER 7\r
+#define IRQ_S_EXT 9\r
+#define IRQ_H_EXT 10\r
+#define IRQ_M_EXT 11\r
+#define IRQ_COP 12\r
+#define IRQ_HOST 13\r
+\r
+#define DEFAULT_RSTVEC 0x00001000\r
+#define DEFAULT_NMIVEC 0x00001004\r
+#define DEFAULT_MTVEC 0x00001010\r
+#define CONFIG_STRING_ADDR 0x0000100C\r
+#define EXT_IO_BASE 0x40000000\r
+#define DRAM_BASE 0x80000000\r
+\r
+// page table entry (PTE) fields\r
+#define PTE_V 0x001 // Valid\r
+#define PTE_R 0x002 // Read\r
+#define PTE_W 0x004 // Write\r
+#define PTE_X 0x008 // Execute\r
+#define PTE_U 0x010 // User\r
+#define PTE_G 0x020 // Global\r
+#define PTE_A 0x040 // Accessed\r
+#define PTE_D 0x080 // Dirty\r
+#define PTE_SOFT 0x300 // Reserved for Software\r
+\r
+#define PTE_PPN_SHIFT 10\r
+\r
+#define PTE_TABLE(PTE) (((PTE) & (PTE_V | PTE_R | PTE_W | PTE_X)) == PTE_V)\r
+\r
+#ifdef __riscv\r
+\r
+#ifdef __riscv64\r
+# define MSTATUS_SD MSTATUS64_SD\r
+# define SSTATUS_SD SSTATUS64_SD\r
+# define RISCV_PGLEVEL_BITS 9\r
+#else\r
+# define MSTATUS_SD MSTATUS32_SD\r
+# define SSTATUS_SD SSTATUS32_SD\r
+# define RISCV_PGLEVEL_BITS 10\r
+#endif\r
+#define RISCV_PGSHIFT 12\r
+#define RISCV_PGSIZE (1 << RISCV_PGSHIFT)\r
+\r
+#ifndef __ASSEMBLER__\r
+\r
+#ifdef __GNUC__\r
+\r
+#define read_csr(reg) ({ unsigned long __tmp; \\r
+ asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \\r
+ __tmp; })\r
+\r
+#define write_csr(reg, val) ({ \\r
+ if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \\r
+ asm volatile ("csrw " #reg ", %0" :: "i"(val)); \\r
+ else \\r
+ asm volatile ("csrw " #reg ", %0" :: "r"(val)); })\r
+\r
+#define swap_csr(reg, val) ({ unsigned long __tmp; \\r
+ if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \\r
+ asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "i"(val)); \\r
+ else \\r
+ asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "r"(val)); \\r
+ __tmp; })\r
+\r
+#define set_csr(reg, bit) ({ unsigned long __tmp; \\r
+ if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \\r
+ asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \\r
+ else \\r
+ asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \\r
+ __tmp; })\r
+\r
+#define clear_csr(reg, bit) ({ unsigned long __tmp; \\r
+ if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \\r
+ asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \\r
+ else \\r
+ asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \\r
+ __tmp; })\r
+\r
+#define rdtime() read_csr(time)\r
+#define rdcycle() read_csr(cycle)\r
+#define rdinstret() read_csr(instret)\r
+\r
+#endif\r
+\r
+#endif\r
+\r
+#endif\r
+\r
+#endif\r
+/* Automatically generated by parse-opcodes */\r
+#ifndef RISCV_ENCODING_H\r
+#define RISCV_ENCODING_H\r
+#define MATCH_BEQ 0x63\r
+#define MASK_BEQ 0x707f\r
+#define MATCH_BNE 0x1063\r
+#define MASK_BNE 0x707f\r
+#define MATCH_BLT 0x4063\r
+#define MASK_BLT 0x707f\r
+#define MATCH_BGE 0x5063\r
+#define MASK_BGE 0x707f\r
+#define MATCH_BLTU 0x6063\r
+#define MASK_BLTU 0x707f\r
+#define MATCH_BGEU 0x7063\r
+#define MASK_BGEU 0x707f\r
+#define MATCH_JALR 0x67\r
+#define MASK_JALR 0x707f\r
+#define MATCH_JAL 0x6f\r
+#define MASK_JAL 0x7f\r
+#define MATCH_LUI 0x37\r
+#define MASK_LUI 0x7f\r
+#define MATCH_AUIPC 0x17\r
+#define MASK_AUIPC 0x7f\r
+#define MATCH_ADDI 0x13\r
+#define MASK_ADDI 0x707f\r
+#define MATCH_SLLI 0x1013\r
+#define MASK_SLLI 0xfc00707f\r
+#define MATCH_SLTI 0x2013\r
+#define MASK_SLTI 0x707f\r
+#define MATCH_SLTIU 0x3013\r
+#define MASK_SLTIU 0x707f\r
+#define MATCH_XORI 0x4013\r
+#define MASK_XORI 0x707f\r
+#define MATCH_SRLI 0x5013\r
+#define MASK_SRLI 0xfc00707f\r
+#define MATCH_SRAI 0x40005013\r
+#define MASK_SRAI 0xfc00707f\r
+#define MATCH_ORI 0x6013\r
+#define MASK_ORI 0x707f\r
+#define MATCH_ANDI 0x7013\r
+#define MASK_ANDI 0x707f\r
+#define MATCH_ADD 0x33\r
+#define MASK_ADD 0xfe00707f\r
+#define MATCH_SUB 0x40000033\r
+#define MASK_SUB 0xfe00707f\r
+#define MATCH_SLL 0x1033\r
+#define MASK_SLL 0xfe00707f\r
+#define MATCH_SLT 0x2033\r
+#define MASK_SLT 0xfe00707f\r
+#define MATCH_SLTU 0x3033\r
+#define MASK_SLTU 0xfe00707f\r
+#define MATCH_XOR 0x4033\r
+#define MASK_XOR 0xfe00707f\r
+#define MATCH_SRL 0x5033\r
+#define MASK_SRL 0xfe00707f\r
+#define MATCH_SRA 0x40005033\r
+#define MASK_SRA 0xfe00707f\r
+#define MATCH_OR 0x6033\r
+#define MASK_OR 0xfe00707f\r
+#define MATCH_AND 0x7033\r
+#define MASK_AND 0xfe00707f\r
+#define MATCH_ADDIW 0x1b\r
+#define MASK_ADDIW 0x707f\r
+#define MATCH_SLLIW 0x101b\r
+#define MASK_SLLIW 0xfe00707f\r
+#define MATCH_SRLIW 0x501b\r
+#define MASK_SRLIW 0xfe00707f\r
+#define MATCH_SRAIW 0x4000501b\r
+#define MASK_SRAIW 0xfe00707f\r
+#define MATCH_ADDW 0x3b\r
+#define MASK_ADDW 0xfe00707f\r
+#define MATCH_SUBW 0x4000003b\r
+#define MASK_SUBW 0xfe00707f\r
+#define MATCH_SLLW 0x103b\r
+#define MASK_SLLW 0xfe00707f\r
+#define MATCH_SRLW 0x503b\r
+#define MASK_SRLW 0xfe00707f\r
+#define MATCH_SRAW 0x4000503b\r
+#define MASK_SRAW 0xfe00707f\r
+#define MATCH_LB 0x3\r
+#define MASK_LB 0x707f\r
+#define MATCH_LH 0x1003\r
+#define MASK_LH 0x707f\r
+#define MATCH_LW 0x2003\r
+#define MASK_LW 0x707f\r
+#define MATCH_LD 0x3003\r
+#define MASK_LD 0x707f\r
+#define MATCH_LBU 0x4003\r
+#define MASK_LBU 0x707f\r
+#define MATCH_LHU 0x5003\r
+#define MASK_LHU 0x707f\r
+#define MATCH_LWU 0x6003\r
+#define MASK_LWU 0x707f\r
+#define MATCH_SB 0x23\r
+#define MASK_SB 0x707f\r
+#define MATCH_SH 0x1023\r
+#define MASK_SH 0x707f\r
+#define MATCH_SW 0x2023\r
+#define MASK_SW 0x707f\r
+#define MATCH_SD 0x3023\r
+#define MASK_SD 0x707f\r
+#define MATCH_FENCE 0xf\r
+#define MASK_FENCE 0x707f\r
+#define MATCH_FENCE_I 0x100f\r
+#define MASK_FENCE_I 0x707f\r
+#define MATCH_MUL 0x2000033\r
+#define MASK_MUL 0xfe00707f\r
+#define MATCH_MULH 0x2001033\r
+#define MASK_MULH 0xfe00707f\r
+#define MATCH_MULHSU 0x2002033\r
+#define MASK_MULHSU 0xfe00707f\r
+#define MATCH_MULHU 0x2003033\r
+#define MASK_MULHU 0xfe00707f\r
+#define MATCH_DIV 0x2004033\r
+#define MASK_DIV 0xfe00707f\r
+#define MATCH_DIVU 0x2005033\r
+#define MASK_DIVU 0xfe00707f\r
+#define MATCH_REM 0x2006033\r
+#define MASK_REM 0xfe00707f\r
+#define MATCH_REMU 0x2007033\r
+#define MASK_REMU 0xfe00707f\r
+#define MATCH_MULW 0x200003b\r
+#define MASK_MULW 0xfe00707f\r
+#define MATCH_DIVW 0x200403b\r
+#define MASK_DIVW 0xfe00707f\r
+#define MATCH_DIVUW 0x200503b\r
+#define MASK_DIVUW 0xfe00707f\r
+#define MATCH_REMW 0x200603b\r
+#define MASK_REMW 0xfe00707f\r
+#define MATCH_REMUW 0x200703b\r
+#define MASK_REMUW 0xfe00707f\r
+#define MATCH_AMOADD_W 0x202f\r
+#define MASK_AMOADD_W 0xf800707f\r
+#define MATCH_AMOXOR_W 0x2000202f\r
+#define MASK_AMOXOR_W 0xf800707f\r
+#define MATCH_AMOOR_W 0x4000202f\r
+#define MASK_AMOOR_W 0xf800707f\r
+#define MATCH_AMOAND_W 0x6000202f\r
+#define MASK_AMOAND_W 0xf800707f\r
+#define MATCH_AMOMIN_W 0x8000202f\r
+#define MASK_AMOMIN_W 0xf800707f\r
+#define MATCH_AMOMAX_W 0xa000202f\r
+#define MASK_AMOMAX_W 0xf800707f\r
+#define MATCH_AMOMINU_W 0xc000202f\r
+#define MASK_AMOMINU_W 0xf800707f\r
+#define MATCH_AMOMAXU_W 0xe000202f\r
+#define MASK_AMOMAXU_W 0xf800707f\r
+#define MATCH_AMOSWAP_W 0x800202f\r
+#define MASK_AMOSWAP_W 0xf800707f\r
+#define MATCH_LR_W 0x1000202f\r
+#define MASK_LR_W 0xf9f0707f\r
+#define MATCH_SC_W 0x1800202f\r
+#define MASK_SC_W 0xf800707f\r
+#define MATCH_AMOADD_D 0x302f\r
+#define MASK_AMOADD_D 0xf800707f\r
+#define MATCH_AMOXOR_D 0x2000302f\r
+#define MASK_AMOXOR_D 0xf800707f\r
+#define MATCH_AMOOR_D 0x4000302f\r
+#define MASK_AMOOR_D 0xf800707f\r
+#define MATCH_AMOAND_D 0x6000302f\r
+#define MASK_AMOAND_D 0xf800707f\r
+#define MATCH_AMOMIN_D 0x8000302f\r
+#define MASK_AMOMIN_D 0xf800707f\r
+#define MATCH_AMOMAX_D 0xa000302f\r
+#define MASK_AMOMAX_D 0xf800707f\r
+#define MATCH_AMOMINU_D 0xc000302f\r
+#define MASK_AMOMINU_D 0xf800707f\r
+#define MATCH_AMOMAXU_D 0xe000302f\r
+#define MASK_AMOMAXU_D 0xf800707f\r
+#define MATCH_AMOSWAP_D 0x800302f\r
+#define MASK_AMOSWAP_D 0xf800707f\r
+#define MATCH_LR_D 0x1000302f\r
+#define MASK_LR_D 0xf9f0707f\r
+#define MATCH_SC_D 0x1800302f\r
+#define MASK_SC_D 0xf800707f\r
+#define MATCH_ECALL 0x73\r
+#define MASK_ECALL 0xffffffff\r
+#define MATCH_EBREAK 0x100073\r
+#define MASK_EBREAK 0xffffffff\r
+#define MATCH_URET 0x200073\r
+#define MASK_URET 0xffffffff\r
+#define MATCH_SRET 0x10200073\r
+#define MASK_SRET 0xffffffff\r
+#define MATCH_HRET 0x20200073\r
+#define MASK_HRET 0xffffffff\r
+#define MATCH_MRET 0x30200073\r
+#define MASK_MRET 0xffffffff\r
+#define MATCH_DRET 0x7b200073\r
+#define MASK_DRET 0xffffffff\r
+#define MATCH_SFENCE_VM 0x10400073\r
+#define MASK_SFENCE_VM 0xfff07fff\r
+#define MATCH_WFI 0x10500073\r
+#define MASK_WFI 0xffffffff\r
+#define MATCH_CSRRW 0x1073\r
+#define MASK_CSRRW 0x707f\r
+#define MATCH_CSRRS 0x2073\r
+#define MASK_CSRRS 0x707f\r
+#define MATCH_CSRRC 0x3073\r
+#define MASK_CSRRC 0x707f\r
+#define MATCH_CSRRWI 0x5073\r
+#define MASK_CSRRWI 0x707f\r
+#define MATCH_CSRRSI 0x6073\r
+#define MASK_CSRRSI 0x707f\r
+#define MATCH_CSRRCI 0x7073\r
+#define MASK_CSRRCI 0x707f\r
+#define MATCH_FADD_S 0x53\r
+#define MASK_FADD_S 0xfe00007f\r
+#define MATCH_FSUB_S 0x8000053\r
+#define MASK_FSUB_S 0xfe00007f\r
+#define MATCH_FMUL_S 0x10000053\r
+#define MASK_FMUL_S 0xfe00007f\r
+#define MATCH_FDIV_S 0x18000053\r
+#define MASK_FDIV_S 0xfe00007f\r
+#define MATCH_FSGNJ_S 0x20000053\r
+#define MASK_FSGNJ_S 0xfe00707f\r
+#define MATCH_FSGNJN_S 0x20001053\r
+#define MASK_FSGNJN_S 0xfe00707f\r
+#define MATCH_FSGNJX_S 0x20002053\r
+#define MASK_FSGNJX_S 0xfe00707f\r
+#define MATCH_FMIN_S 0x28000053\r
+#define MASK_FMIN_S 0xfe00707f\r
+#define MATCH_FMAX_S 0x28001053\r
+#define MASK_FMAX_S 0xfe00707f\r
+#define MATCH_FSQRT_S 0x58000053\r
+#define MASK_FSQRT_S 0xfff0007f\r
+#define MATCH_FADD_D 0x2000053\r
+#define MASK_FADD_D 0xfe00007f\r
+#define MATCH_FSUB_D 0xa000053\r
+#define MASK_FSUB_D 0xfe00007f\r
+#define MATCH_FMUL_D 0x12000053\r
+#define MASK_FMUL_D 0xfe00007f\r
+#define MATCH_FDIV_D 0x1a000053\r
+#define MASK_FDIV_D 0xfe00007f\r
+#define MATCH_FSGNJ_D 0x22000053\r
+#define MASK_FSGNJ_D 0xfe00707f\r
+#define MATCH_FSGNJN_D 0x22001053\r
+#define MASK_FSGNJN_D 0xfe00707f\r
+#define MATCH_FSGNJX_D 0x22002053\r
+#define MASK_FSGNJX_D 0xfe00707f\r
+#define MATCH_FMIN_D 0x2a000053\r
+#define MASK_FMIN_D 0xfe00707f\r
+#define MATCH_FMAX_D 0x2a001053\r
+#define MASK_FMAX_D 0xfe00707f\r
+#define MATCH_FCVT_S_D 0x40100053\r
+#define MASK_FCVT_S_D 0xfff0007f\r
+#define MATCH_FCVT_D_S 0x42000053\r
+#define MASK_FCVT_D_S 0xfff0007f\r
+#define MATCH_FSQRT_D 0x5a000053\r
+#define MASK_FSQRT_D 0xfff0007f\r
+#define MATCH_FLE_S 0xa0000053\r
+#define MASK_FLE_S 0xfe00707f\r
+#define MATCH_FLT_S 0xa0001053\r
+#define MASK_FLT_S 0xfe00707f\r
+#define MATCH_FEQ_S 0xa0002053\r
+#define MASK_FEQ_S 0xfe00707f\r
+#define MATCH_FLE_D 0xa2000053\r
+#define MASK_FLE_D 0xfe00707f\r
+#define MATCH_FLT_D 0xa2001053\r
+#define MASK_FLT_D 0xfe00707f\r
+#define MATCH_FEQ_D 0xa2002053\r
+#define MASK_FEQ_D 0xfe00707f\r
+#define MATCH_FCVT_W_S 0xc0000053\r
+#define MASK_FCVT_W_S 0xfff0007f\r
+#define MATCH_FCVT_WU_S 0xc0100053\r
+#define MASK_FCVT_WU_S 0xfff0007f\r
+#define MATCH_FCVT_L_S 0xc0200053\r
+#define MASK_FCVT_L_S 0xfff0007f\r
+#define MATCH_FCVT_LU_S 0xc0300053\r
+#define MASK_FCVT_LU_S 0xfff0007f\r
+#define MATCH_FMV_X_S 0xe0000053\r
+#define MASK_FMV_X_S 0xfff0707f\r
+#define MATCH_FCLASS_S 0xe0001053\r
+#define MASK_FCLASS_S 0xfff0707f\r
+#define MATCH_FCVT_W_D 0xc2000053\r
+#define MASK_FCVT_W_D 0xfff0007f\r
+#define MATCH_FCVT_WU_D 0xc2100053\r
+#define MASK_FCVT_WU_D 0xfff0007f\r
+#define MATCH_FCVT_L_D 0xc2200053\r
+#define MASK_FCVT_L_D 0xfff0007f\r
+#define MATCH_FCVT_LU_D 0xc2300053\r
+#define MASK_FCVT_LU_D 0xfff0007f\r
+#define MATCH_FMV_X_D 0xe2000053\r
+#define MASK_FMV_X_D 0xfff0707f\r
+#define MATCH_FCLASS_D 0xe2001053\r
+#define MASK_FCLASS_D 0xfff0707f\r
+#define MATCH_FCVT_S_W 0xd0000053\r
+#define MASK_FCVT_S_W 0xfff0007f\r
+#define MATCH_FCVT_S_WU 0xd0100053\r
+#define MASK_FCVT_S_WU 0xfff0007f\r
+#define MATCH_FCVT_S_L 0xd0200053\r
+#define MASK_FCVT_S_L 0xfff0007f\r
+#define MATCH_FCVT_S_LU 0xd0300053\r
+#define MASK_FCVT_S_LU 0xfff0007f\r
+#define MATCH_FMV_S_X 0xf0000053\r
+#define MASK_FMV_S_X 0xfff0707f\r
+#define MATCH_FCVT_D_W 0xd2000053\r
+#define MASK_FCVT_D_W 0xfff0007f\r
+#define MATCH_FCVT_D_WU 0xd2100053\r
+#define MASK_FCVT_D_WU 0xfff0007f\r
+#define MATCH_FCVT_D_L 0xd2200053\r
+#define MASK_FCVT_D_L 0xfff0007f\r
+#define MATCH_FCVT_D_LU 0xd2300053\r
+#define MASK_FCVT_D_LU 0xfff0007f\r
+#define MATCH_FMV_D_X 0xf2000053\r
+#define MASK_FMV_D_X 0xfff0707f\r
+#define MATCH_FLW 0x2007\r
+#define MASK_FLW 0x707f\r
+#define MATCH_FLD 0x3007\r
+#define MASK_FLD 0x707f\r
+#define MATCH_FSW 0x2027\r
+#define MASK_FSW 0x707f\r
+#define MATCH_FSD 0x3027\r
+#define MASK_FSD 0x707f\r
+#define MATCH_FMADD_S 0x43\r
+#define MASK_FMADD_S 0x600007f\r
+#define MATCH_FMSUB_S 0x47\r
+#define MASK_FMSUB_S 0x600007f\r
+#define MATCH_FNMSUB_S 0x4b\r
+#define MASK_FNMSUB_S 0x600007f\r
+#define MATCH_FNMADD_S 0x4f\r
+#define MASK_FNMADD_S 0x600007f\r
+#define MATCH_FMADD_D 0x2000043\r
+#define MASK_FMADD_D 0x600007f\r
+#define MATCH_FMSUB_D 0x2000047\r
+#define MASK_FMSUB_D 0x600007f\r
+#define MATCH_FNMSUB_D 0x200004b\r
+#define MASK_FNMSUB_D 0x600007f\r
+#define MATCH_FNMADD_D 0x200004f\r
+#define MASK_FNMADD_D 0x600007f\r
+#define MATCH_C_NOP 0x1\r
+#define MASK_C_NOP 0xffff\r
+#define MATCH_C_ADDI16SP 0x6101\r
+#define MASK_C_ADDI16SP 0xef83\r
+#define MATCH_C_JR 0x8002\r
+#define MASK_C_JR 0xf07f\r
+#define MATCH_C_JALR 0x9002\r
+#define MASK_C_JALR 0xf07f\r
+#define MATCH_C_EBREAK 0x9002\r
+#define MASK_C_EBREAK 0xffff\r
+#define MATCH_C_LD 0x6000\r
+#define MASK_C_LD 0xe003\r
+#define MATCH_C_SD 0xe000\r
+#define MASK_C_SD 0xe003\r
+#define MATCH_C_ADDIW 0x2001\r
+#define MASK_C_ADDIW 0xe003\r
+#define MATCH_C_LDSP 0x6002\r
+#define MASK_C_LDSP 0xe003\r
+#define MATCH_C_SDSP 0xe002\r
+#define MASK_C_SDSP 0xe003\r
+#define MATCH_C_ADDI4SPN 0x0\r
+#define MASK_C_ADDI4SPN 0xe003\r
+#define MATCH_C_FLD 0x2000\r
+#define MASK_C_FLD 0xe003\r
+#define MATCH_C_LW 0x4000\r
+#define MASK_C_LW 0xe003\r
+#define MATCH_C_FLW 0x6000\r
+#define MASK_C_FLW 0xe003\r
+#define MATCH_C_FSD 0xa000\r
+#define MASK_C_FSD 0xe003\r
+#define MATCH_C_SW 0xc000\r
+#define MASK_C_SW 0xe003\r
+#define MATCH_C_FSW 0xe000\r
+#define MASK_C_FSW 0xe003\r
+#define MATCH_C_ADDI 0x1\r
+#define MASK_C_ADDI 0xe003\r
+#define MATCH_C_JAL 0x2001\r
+#define MASK_C_JAL 0xe003\r
+#define MATCH_C_LI 0x4001\r
+#define MASK_C_LI 0xe003\r
+#define MATCH_C_LUI 0x6001\r
+#define MASK_C_LUI 0xe003\r
+#define MATCH_C_SRLI 0x8001\r
+#define MASK_C_SRLI 0xec03\r
+#define MATCH_C_SRAI 0x8401\r
+#define MASK_C_SRAI 0xec03\r
+#define MATCH_C_ANDI 0x8801\r
+#define MASK_C_ANDI 0xec03\r
+#define MATCH_C_SUB 0x8c01\r
+#define MASK_C_SUB 0xfc63\r
+#define MATCH_C_XOR 0x8c21\r
+#define MASK_C_XOR 0xfc63\r
+#define MATCH_C_OR 0x8c41\r
+#define MASK_C_OR 0xfc63\r
+#define MATCH_C_AND 0x8c61\r
+#define MASK_C_AND 0xfc63\r
+#define MATCH_C_SUBW 0x9c01\r
+#define MASK_C_SUBW 0xfc63\r
+#define MATCH_C_ADDW 0x9c21\r
+#define MASK_C_ADDW 0xfc63\r
+#define MATCH_C_J 0xa001\r
+#define MASK_C_J 0xe003\r
+#define MATCH_C_BEQZ 0xc001\r
+#define MASK_C_BEQZ 0xe003\r
+#define MATCH_C_BNEZ 0xe001\r
+#define MASK_C_BNEZ 0xe003\r
+#define MATCH_C_SLLI 0x2\r
+#define MASK_C_SLLI 0xe003\r
+#define MATCH_C_FLDSP 0x2002\r
+#define MASK_C_FLDSP 0xe003\r
+#define MATCH_C_LWSP 0x4002\r
+#define MASK_C_LWSP 0xe003\r
+#define MATCH_C_FLWSP 0x6002\r
+#define MASK_C_FLWSP 0xe003\r
+#define MATCH_C_MV 0x8002\r
+#define MASK_C_MV 0xf003\r
+#define MATCH_C_ADD 0x9002\r
+#define MASK_C_ADD 0xf003\r
+#define MATCH_C_FSDSP 0xa002\r
+#define MASK_C_FSDSP 0xe003\r
+#define MATCH_C_SWSP 0xc002\r
+#define MASK_C_SWSP 0xe003\r
+#define MATCH_C_FSWSP 0xe002\r
+#define MASK_C_FSWSP 0xe003\r
+#define MATCH_CUSTOM0 0xb\r
+#define MASK_CUSTOM0 0x707f\r
+#define MATCH_CUSTOM0_RS1 0x200b\r
+#define MASK_CUSTOM0_RS1 0x707f\r
+#define MATCH_CUSTOM0_RS1_RS2 0x300b\r
+#define MASK_CUSTOM0_RS1_RS2 0x707f\r
+#define MATCH_CUSTOM0_RD 0x400b\r
+#define MASK_CUSTOM0_RD 0x707f\r
+#define MATCH_CUSTOM0_RD_RS1 0x600b\r
+#define MASK_CUSTOM0_RD_RS1 0x707f\r
+#define MATCH_CUSTOM0_RD_RS1_RS2 0x700b\r
+#define MASK_CUSTOM0_RD_RS1_RS2 0x707f\r
+#define MATCH_CUSTOM1 0x2b\r
+#define MASK_CUSTOM1 0x707f\r
+#define MATCH_CUSTOM1_RS1 0x202b\r
+#define MASK_CUSTOM1_RS1 0x707f\r
+#define MATCH_CUSTOM1_RS1_RS2 0x302b\r
+#define MASK_CUSTOM1_RS1_RS2 0x707f\r
+#define MATCH_CUSTOM1_RD 0x402b\r
+#define MASK_CUSTOM1_RD 0x707f\r
+#define MATCH_CUSTOM1_RD_RS1 0x602b\r
+#define MASK_CUSTOM1_RD_RS1 0x707f\r
+#define MATCH_CUSTOM1_RD_RS1_RS2 0x702b\r
+#define MASK_CUSTOM1_RD_RS1_RS2 0x707f\r
+#define MATCH_CUSTOM2 0x5b\r
+#define MASK_CUSTOM2 0x707f\r
+#define MATCH_CUSTOM2_RS1 0x205b\r
+#define MASK_CUSTOM2_RS1 0x707f\r
+#define MATCH_CUSTOM2_RS1_RS2 0x305b\r
+#define MASK_CUSTOM2_RS1_RS2 0x707f\r
+#define MATCH_CUSTOM2_RD 0x405b\r
+#define MASK_CUSTOM2_RD 0x707f\r
+#define MATCH_CUSTOM2_RD_RS1 0x605b\r
+#define MASK_CUSTOM2_RD_RS1 0x707f\r
+#define MATCH_CUSTOM2_RD_RS1_RS2 0x705b\r
+#define MASK_CUSTOM2_RD_RS1_RS2 0x707f\r
+#define MATCH_CUSTOM3 0x7b\r
+#define MASK_CUSTOM3 0x707f\r
+#define MATCH_CUSTOM3_RS1 0x207b\r
+#define MASK_CUSTOM3_RS1 0x707f\r
+#define MATCH_CUSTOM3_RS1_RS2 0x307b\r
+#define MASK_CUSTOM3_RS1_RS2 0x707f\r
+#define MATCH_CUSTOM3_RD 0x407b\r
+#define MASK_CUSTOM3_RD 0x707f\r
+#define MATCH_CUSTOM3_RD_RS1 0x607b\r
+#define MASK_CUSTOM3_RD_RS1 0x707f\r
+#define MATCH_CUSTOM3_RD_RS1_RS2 0x707b\r
+#define MASK_CUSTOM3_RD_RS1_RS2 0x707f\r
+#define CSR_FFLAGS 0x1\r
+#define CSR_FRM 0x2\r
+#define CSR_FCSR 0x3\r
+#define CSR_CYCLE 0xc00\r
+#define CSR_TIME 0xc01\r
+#define CSR_INSTRET 0xc02\r
+#define CSR_HPMCOUNTER3 0xc03\r
+#define CSR_HPMCOUNTER4 0xc04\r
+#define CSR_HPMCOUNTER5 0xc05\r
+#define CSR_HPMCOUNTER6 0xc06\r
+#define CSR_HPMCOUNTER7 0xc07\r
+#define CSR_HPMCOUNTER8 0xc08\r
+#define CSR_HPMCOUNTER9 0xc09\r
+#define CSR_HPMCOUNTER10 0xc0a\r
+#define CSR_HPMCOUNTER11 0xc0b\r
+#define CSR_HPMCOUNTER12 0xc0c\r
+#define CSR_HPMCOUNTER13 0xc0d\r
+#define CSR_HPMCOUNTER14 0xc0e\r
+#define CSR_HPMCOUNTER15 0xc0f\r
+#define CSR_HPMCOUNTER16 0xc10\r
+#define CSR_HPMCOUNTER17 0xc11\r
+#define CSR_HPMCOUNTER18 0xc12\r
+#define CSR_HPMCOUNTER19 0xc13\r
+#define CSR_HPMCOUNTER20 0xc14\r
+#define CSR_HPMCOUNTER21 0xc15\r
+#define CSR_HPMCOUNTER22 0xc16\r
+#define CSR_HPMCOUNTER23 0xc17\r
+#define CSR_HPMCOUNTER24 0xc18\r
+#define CSR_HPMCOUNTER25 0xc19\r
+#define CSR_HPMCOUNTER26 0xc1a\r
+#define CSR_HPMCOUNTER27 0xc1b\r
+#define CSR_HPMCOUNTER28 0xc1c\r
+#define CSR_HPMCOUNTER29 0xc1d\r
+#define CSR_HPMCOUNTER30 0xc1e\r
+#define CSR_HPMCOUNTER31 0xc1f\r
+#define CSR_SSTATUS 0x100\r
+#define CSR_SIE 0x104\r
+#define CSR_STVEC 0x105\r
+#define CSR_SSCRATCH 0x140\r
+#define CSR_SEPC 0x141\r
+#define CSR_SCAUSE 0x142\r
+#define CSR_SBADADDR 0x143\r
+#define CSR_SIP 0x144\r
+#define CSR_SPTBR 0x180\r
+#define CSR_MSTATUS 0x300\r
+#define CSR_MISA 0x301\r
+#define CSR_MEDELEG 0x302\r
+#define CSR_MIDELEG 0x303\r
+#define CSR_MIE 0x304\r
+#define CSR_MTVEC 0x305\r
+#define CSR_MSCRATCH 0x340\r
+#define CSR_MEPC 0x341\r
+#define CSR_MCAUSE 0x342\r
+#define CSR_MBADADDR 0x343\r
+#define CSR_MIP 0x344\r
+#define CSR_TSELECT 0x7a0\r
+#define CSR_TDATA1 0x7a1\r
+#define CSR_TDATA2 0x7a2\r
+#define CSR_TDATA3 0x7a3\r
+#define CSR_DCSR 0x7b0\r
+#define CSR_DPC 0x7b1\r
+#define CSR_DSCRATCH 0x7b2\r
+#define CSR_MCYCLE 0xb00\r
+#define CSR_MINSTRET 0xb02\r
+#define CSR_MHPMCOUNTER3 0xb03\r
+#define CSR_MHPMCOUNTER4 0xb04\r
+#define CSR_MHPMCOUNTER5 0xb05\r
+#define CSR_MHPMCOUNTER6 0xb06\r
+#define CSR_MHPMCOUNTER7 0xb07\r
+#define CSR_MHPMCOUNTER8 0xb08\r
+#define CSR_MHPMCOUNTER9 0xb09\r
+#define CSR_MHPMCOUNTER10 0xb0a\r
+#define CSR_MHPMCOUNTER11 0xb0b\r
+#define CSR_MHPMCOUNTER12 0xb0c\r
+#define CSR_MHPMCOUNTER13 0xb0d\r
+#define CSR_MHPMCOUNTER14 0xb0e\r
+#define CSR_MHPMCOUNTER15 0xb0f\r
+#define CSR_MHPMCOUNTER16 0xb10\r
+#define CSR_MHPMCOUNTER17 0xb11\r
+#define CSR_MHPMCOUNTER18 0xb12\r
+#define CSR_MHPMCOUNTER19 0xb13\r
+#define CSR_MHPMCOUNTER20 0xb14\r
+#define CSR_MHPMCOUNTER21 0xb15\r
+#define CSR_MHPMCOUNTER22 0xb16\r
+#define CSR_MHPMCOUNTER23 0xb17\r
+#define CSR_MHPMCOUNTER24 0xb18\r
+#define CSR_MHPMCOUNTER25 0xb19\r
+#define CSR_MHPMCOUNTER26 0xb1a\r
+#define CSR_MHPMCOUNTER27 0xb1b\r
+#define CSR_MHPMCOUNTER28 0xb1c\r
+#define CSR_MHPMCOUNTER29 0xb1d\r
+#define CSR_MHPMCOUNTER30 0xb1e\r
+#define CSR_MHPMCOUNTER31 0xb1f\r
+#define CSR_MUCOUNTEREN 0x320\r
+#define CSR_MSCOUNTEREN 0x321\r
+#define CSR_MHPMEVENT3 0x323\r
+#define CSR_MHPMEVENT4 0x324\r
+#define CSR_MHPMEVENT5 0x325\r
+#define CSR_MHPMEVENT6 0x326\r
+#define CSR_MHPMEVENT7 0x327\r
+#define CSR_MHPMEVENT8 0x328\r
+#define CSR_MHPMEVENT9 0x329\r
+#define CSR_MHPMEVENT10 0x32a\r
+#define CSR_MHPMEVENT11 0x32b\r
+#define CSR_MHPMEVENT12 0x32c\r
+#define CSR_MHPMEVENT13 0x32d\r
+#define CSR_MHPMEVENT14 0x32e\r
+#define CSR_MHPMEVENT15 0x32f\r
+#define CSR_MHPMEVENT16 0x330\r
+#define CSR_MHPMEVENT17 0x331\r
+#define CSR_MHPMEVENT18 0x332\r
+#define CSR_MHPMEVENT19 0x333\r
+#define CSR_MHPMEVENT20 0x334\r
+#define CSR_MHPMEVENT21 0x335\r
+#define CSR_MHPMEVENT22 0x336\r
+#define CSR_MHPMEVENT23 0x337\r
+#define CSR_MHPMEVENT24 0x338\r
+#define CSR_MHPMEVENT25 0x339\r
+#define CSR_MHPMEVENT26 0x33a\r
+#define CSR_MHPMEVENT27 0x33b\r
+#define CSR_MHPMEVENT28 0x33c\r
+#define CSR_MHPMEVENT29 0x33d\r
+#define CSR_MHPMEVENT30 0x33e\r
+#define CSR_MHPMEVENT31 0x33f\r
+#define CSR_MVENDORID 0xf11\r
+#define CSR_MARCHID 0xf12\r
+#define CSR_MIMPID 0xf13\r
+#define CSR_MHARTID 0xf14\r
+#define CSR_CYCLEH 0xc80\r
+#define CSR_TIMEH 0xc81\r
+#define CSR_INSTRETH 0xc82\r
+#define CSR_HPMCOUNTER3H 0xc83\r
+#define CSR_HPMCOUNTER4H 0xc84\r
+#define CSR_HPMCOUNTER5H 0xc85\r
+#define CSR_HPMCOUNTER6H 0xc86\r
+#define CSR_HPMCOUNTER7H 0xc87\r
+#define CSR_HPMCOUNTER8H 0xc88\r
+#define CSR_HPMCOUNTER9H 0xc89\r
+#define CSR_HPMCOUNTER10H 0xc8a\r
+#define CSR_HPMCOUNTER11H 0xc8b\r
+#define CSR_HPMCOUNTER12H 0xc8c\r
+#define CSR_HPMCOUNTER13H 0xc8d\r
+#define CSR_HPMCOUNTER14H 0xc8e\r
+#define CSR_HPMCOUNTER15H 0xc8f\r
+#define CSR_HPMCOUNTER16H 0xc90\r
+#define CSR_HPMCOUNTER17H 0xc91\r
+#define CSR_HPMCOUNTER18H 0xc92\r
+#define CSR_HPMCOUNTER19H 0xc93\r
+#define CSR_HPMCOUNTER20H 0xc94\r
+#define CSR_HPMCOUNTER21H 0xc95\r
+#define CSR_HPMCOUNTER22H 0xc96\r
+#define CSR_HPMCOUNTER23H 0xc97\r
+#define CSR_HPMCOUNTER24H 0xc98\r
+#define CSR_HPMCOUNTER25H 0xc99\r
+#define CSR_HPMCOUNTER26H 0xc9a\r
+#define CSR_HPMCOUNTER27H 0xc9b\r
+#define CSR_HPMCOUNTER28H 0xc9c\r
+#define CSR_HPMCOUNTER29H 0xc9d\r
+#define CSR_HPMCOUNTER30H 0xc9e\r
+#define CSR_HPMCOUNTER31H 0xc9f\r
+#define CSR_MCYCLEH 0xb80\r
+#define CSR_MINSTRETH 0xb82\r
+#define CSR_MHPMCOUNTER3H 0xb83\r
+#define CSR_MHPMCOUNTER4H 0xb84\r
+#define CSR_MHPMCOUNTER5H 0xb85\r
+#define CSR_MHPMCOUNTER6H 0xb86\r
+#define CSR_MHPMCOUNTER7H 0xb87\r
+#define CSR_MHPMCOUNTER8H 0xb88\r
+#define CSR_MHPMCOUNTER9H 0xb89\r
+#define CSR_MHPMCOUNTER10H 0xb8a\r
+#define CSR_MHPMCOUNTER11H 0xb8b\r
+#define CSR_MHPMCOUNTER12H 0xb8c\r
+#define CSR_MHPMCOUNTER13H 0xb8d\r
+#define CSR_MHPMCOUNTER14H 0xb8e\r
+#define CSR_MHPMCOUNTER15H 0xb8f\r
+#define CSR_MHPMCOUNTER16H 0xb90\r
+#define CSR_MHPMCOUNTER17H 0xb91\r
+#define CSR_MHPMCOUNTER18H 0xb92\r
+#define CSR_MHPMCOUNTER19H 0xb93\r
+#define CSR_MHPMCOUNTER20H 0xb94\r
+#define CSR_MHPMCOUNTER21H 0xb95\r
+#define CSR_MHPMCOUNTER22H 0xb96\r
+#define CSR_MHPMCOUNTER23H 0xb97\r
+#define CSR_MHPMCOUNTER24H 0xb98\r
+#define CSR_MHPMCOUNTER25H 0xb99\r
+#define CSR_MHPMCOUNTER26H 0xb9a\r
+#define CSR_MHPMCOUNTER27H 0xb9b\r
+#define CSR_MHPMCOUNTER28H 0xb9c\r
+#define CSR_MHPMCOUNTER29H 0xb9d\r
+#define CSR_MHPMCOUNTER30H 0xb9e\r
+#define CSR_MHPMCOUNTER31H 0xb9f\r
+#define CAUSE_MISALIGNED_FETCH 0x0\r
+#define CAUSE_FAULT_FETCH 0x1\r
+#define CAUSE_ILLEGAL_INSTRUCTION 0x2\r
+#define CAUSE_BREAKPOINT 0x3\r
+#define CAUSE_MISALIGNED_LOAD 0x4\r
+#define CAUSE_FAULT_LOAD 0x5\r
+#define CAUSE_MISALIGNED_STORE 0x6\r
+#define CAUSE_FAULT_STORE 0x7\r
+#define CAUSE_USER_ECALL 0x8\r
+#define CAUSE_SUPERVISOR_ECALL 0x9\r
+#define CAUSE_HYPERVISOR_ECALL 0xa\r
+#define CAUSE_MACHINE_ECALL 0xb\r
+#endif\r
+#ifdef DECLARE_INSN\r
+DECLARE_INSN(beq, MATCH_BEQ, MASK_BEQ)\r
+DECLARE_INSN(bne, MATCH_BNE, MASK_BNE)\r
+DECLARE_INSN(blt, MATCH_BLT, MASK_BLT)\r
+DECLARE_INSN(bge, MATCH_BGE, MASK_BGE)\r
+DECLARE_INSN(bltu, MATCH_BLTU, MASK_BLTU)\r
+DECLARE_INSN(bgeu, MATCH_BGEU, MASK_BGEU)\r
+DECLARE_INSN(jalr, MATCH_JALR, MASK_JALR)\r
+DECLARE_INSN(jal, MATCH_JAL, MASK_JAL)\r
+DECLARE_INSN(lui, MATCH_LUI, MASK_LUI)\r
+DECLARE_INSN(auipc, MATCH_AUIPC, MASK_AUIPC)\r
+DECLARE_INSN(addi, MATCH_ADDI, MASK_ADDI)\r
+DECLARE_INSN(slli, MATCH_SLLI, MASK_SLLI)\r
+DECLARE_INSN(slti, MATCH_SLTI, MASK_SLTI)\r
+DECLARE_INSN(sltiu, MATCH_SLTIU, MASK_SLTIU)\r
+DECLARE_INSN(xori, MATCH_XORI, MASK_XORI)\r
+DECLARE_INSN(srli, MATCH_SRLI, MASK_SRLI)\r
+DECLARE_INSN(srai, MATCH_SRAI, MASK_SRAI)\r
+DECLARE_INSN(ori, MATCH_ORI, MASK_ORI)\r
+DECLARE_INSN(andi, MATCH_ANDI, MASK_ANDI)\r
+DECLARE_INSN(add, MATCH_ADD, MASK_ADD)\r
+DECLARE_INSN(sub, MATCH_SUB, MASK_SUB)\r
+DECLARE_INSN(sll, MATCH_SLL, MASK_SLL)\r
+DECLARE_INSN(slt, MATCH_SLT, MASK_SLT)\r
+DECLARE_INSN(sltu, MATCH_SLTU, MASK_SLTU)\r
+DECLARE_INSN(xor, MATCH_XOR, MASK_XOR)\r
+DECLARE_INSN(srl, MATCH_SRL, MASK_SRL)\r
+DECLARE_INSN(sra, MATCH_SRA, MASK_SRA)\r
+DECLARE_INSN(or, MATCH_OR, MASK_OR)\r
+DECLARE_INSN(and, MATCH_AND, MASK_AND)\r
+DECLARE_INSN(addiw, MATCH_ADDIW, MASK_ADDIW)\r
+DECLARE_INSN(slliw, MATCH_SLLIW, MASK_SLLIW)\r
+DECLARE_INSN(srliw, MATCH_SRLIW, MASK_SRLIW)\r
+DECLARE_INSN(sraiw, MATCH_SRAIW, MASK_SRAIW)\r
+DECLARE_INSN(addw, MATCH_ADDW, MASK_ADDW)\r
+DECLARE_INSN(subw, MATCH_SUBW, MASK_SUBW)\r
+DECLARE_INSN(sllw, MATCH_SLLW, MASK_SLLW)\r
+DECLARE_INSN(srlw, MATCH_SRLW, MASK_SRLW)\r
+DECLARE_INSN(sraw, MATCH_SRAW, MASK_SRAW)\r
+DECLARE_INSN(lb, MATCH_LB, MASK_LB)\r
+DECLARE_INSN(lh, MATCH_LH, MASK_LH)\r
+DECLARE_INSN(lw, MATCH_LW, MASK_LW)\r
+DECLARE_INSN(ld, MATCH_LD, MASK_LD)\r
+DECLARE_INSN(lbu, MATCH_LBU, MASK_LBU)\r
+DECLARE_INSN(lhu, MATCH_LHU, MASK_LHU)\r
+DECLARE_INSN(lwu, MATCH_LWU, MASK_LWU)\r
+DECLARE_INSN(sb, MATCH_SB, MASK_SB)\r
+DECLARE_INSN(sh, MATCH_SH, MASK_SH)\r
+DECLARE_INSN(sw, MATCH_SW, MASK_SW)\r
+DECLARE_INSN(sd, MATCH_SD, MASK_SD)\r
+DECLARE_INSN(fence, MATCH_FENCE, MASK_FENCE)\r
+DECLARE_INSN(fence_i, MATCH_FENCE_I, MASK_FENCE_I)\r
+DECLARE_INSN(mul, MATCH_MUL, MASK_MUL)\r
+DECLARE_INSN(mulh, MATCH_MULH, MASK_MULH)\r
+DECLARE_INSN(mulhsu, MATCH_MULHSU, MASK_MULHSU)\r
+DECLARE_INSN(mulhu, MATCH_MULHU, MASK_MULHU)\r
+DECLARE_INSN(div, MATCH_DIV, MASK_DIV)\r
+DECLARE_INSN(divu, MATCH_DIVU, MASK_DIVU)\r
+DECLARE_INSN(rem, MATCH_REM, MASK_REM)\r
+DECLARE_INSN(remu, MATCH_REMU, MASK_REMU)\r
+DECLARE_INSN(mulw, MATCH_MULW, MASK_MULW)\r
+DECLARE_INSN(divw, MATCH_DIVW, MASK_DIVW)\r
+DECLARE_INSN(divuw, MATCH_DIVUW, MASK_DIVUW)\r
+DECLARE_INSN(remw, MATCH_REMW, MASK_REMW)\r
+DECLARE_INSN(remuw, MATCH_REMUW, MASK_REMUW)\r
+DECLARE_INSN(amoadd_w, MATCH_AMOADD_W, MASK_AMOADD_W)\r
+DECLARE_INSN(amoxor_w, MATCH_AMOXOR_W, MASK_AMOXOR_W)\r
+DECLARE_INSN(amoor_w, MATCH_AMOOR_W, MASK_AMOOR_W)\r
+DECLARE_INSN(amoand_w, MATCH_AMOAND_W, MASK_AMOAND_W)\r
+DECLARE_INSN(amomin_w, MATCH_AMOMIN_W, MASK_AMOMIN_W)\r
+DECLARE_INSN(amomax_w, MATCH_AMOMAX_W, MASK_AMOMAX_W)\r
+DECLARE_INSN(amominu_w, MATCH_AMOMINU_W, MASK_AMOMINU_W)\r
+DECLARE_INSN(amomaxu_w, MATCH_AMOMAXU_W, MASK_AMOMAXU_W)\r
+DECLARE_INSN(amoswap_w, MATCH_AMOSWAP_W, MASK_AMOSWAP_W)\r
+DECLARE_INSN(lr_w, MATCH_LR_W, MASK_LR_W)\r
+DECLARE_INSN(sc_w, MATCH_SC_W, MASK_SC_W)\r
+DECLARE_INSN(amoadd_d, MATCH_AMOADD_D, MASK_AMOADD_D)\r
+DECLARE_INSN(amoxor_d, MATCH_AMOXOR_D, MASK_AMOXOR_D)\r
+DECLARE_INSN(amoor_d, MATCH_AMOOR_D, MASK_AMOOR_D)\r
+DECLARE_INSN(amoand_d, MATCH_AMOAND_D, MASK_AMOAND_D)\r
+DECLARE_INSN(amomin_d, MATCH_AMOMIN_D, MASK_AMOMIN_D)\r
+DECLARE_INSN(amomax_d, MATCH_AMOMAX_D, MASK_AMOMAX_D)\r
+DECLARE_INSN(amominu_d, MATCH_AMOMINU_D, MASK_AMOMINU_D)\r
+DECLARE_INSN(amomaxu_d, MATCH_AMOMAXU_D, MASK_AMOMAXU_D)\r
+DECLARE_INSN(amoswap_d, MATCH_AMOSWAP_D, MASK_AMOSWAP_D)\r
+DECLARE_INSN(lr_d, MATCH_LR_D, MASK_LR_D)\r
+DECLARE_INSN(sc_d, MATCH_SC_D, MASK_SC_D)\r
+DECLARE_INSN(ecall, MATCH_ECALL, MASK_ECALL)\r
+DECLARE_INSN(ebreak, MATCH_EBREAK, MASK_EBREAK)\r
+DECLARE_INSN(uret, MATCH_URET, MASK_URET)\r
+DECLARE_INSN(sret, MATCH_SRET, MASK_SRET)\r
+DECLARE_INSN(hret, MATCH_HRET, MASK_HRET)\r
+DECLARE_INSN(mret, MATCH_MRET, MASK_MRET)\r
+DECLARE_INSN(dret, MATCH_DRET, MASK_DRET)\r
+DECLARE_INSN(sfence_vm, MATCH_SFENCE_VM, MASK_SFENCE_VM)\r
+DECLARE_INSN(wfi, MATCH_WFI, MASK_WFI)\r
+DECLARE_INSN(csrrw, MATCH_CSRRW, MASK_CSRRW)\r
+DECLARE_INSN(csrrs, MATCH_CSRRS, MASK_CSRRS)\r
+DECLARE_INSN(csrrc, MATCH_CSRRC, MASK_CSRRC)\r
+DECLARE_INSN(csrrwi, MATCH_CSRRWI, MASK_CSRRWI)\r
+DECLARE_INSN(csrrsi, MATCH_CSRRSI, MASK_CSRRSI)\r
+DECLARE_INSN(csrrci, MATCH_CSRRCI, MASK_CSRRCI)\r
+DECLARE_INSN(fadd_s, MATCH_FADD_S, MASK_FADD_S)\r
+DECLARE_INSN(fsub_s, MATCH_FSUB_S, MASK_FSUB_S)\r
+DECLARE_INSN(fmul_s, MATCH_FMUL_S, MASK_FMUL_S)\r
+DECLARE_INSN(fdiv_s, MATCH_FDIV_S, MASK_FDIV_S)\r
+DECLARE_INSN(fsgnj_s, MATCH_FSGNJ_S, MASK_FSGNJ_S)\r
+DECLARE_INSN(fsgnjn_s, MATCH_FSGNJN_S, MASK_FSGNJN_S)\r
+DECLARE_INSN(fsgnjx_s, MATCH_FSGNJX_S, MASK_FSGNJX_S)\r
+DECLARE_INSN(fmin_s, MATCH_FMIN_S, MASK_FMIN_S)\r
+DECLARE_INSN(fmax_s, MATCH_FMAX_S, MASK_FMAX_S)\r
+DECLARE_INSN(fsqrt_s, MATCH_FSQRT_S, MASK_FSQRT_S)\r
+DECLARE_INSN(fadd_d, MATCH_FADD_D, MASK_FADD_D)\r
+DECLARE_INSN(fsub_d, MATCH_FSUB_D, MASK_FSUB_D)\r
+DECLARE_INSN(fmul_d, MATCH_FMUL_D, MASK_FMUL_D)\r
+DECLARE_INSN(fdiv_d, MATCH_FDIV_D, MASK_FDIV_D)\r
+DECLARE_INSN(fsgnj_d, MATCH_FSGNJ_D, MASK_FSGNJ_D)\r
+DECLARE_INSN(fsgnjn_d, MATCH_FSGNJN_D, MASK_FSGNJN_D)\r
+DECLARE_INSN(fsgnjx_d, MATCH_FSGNJX_D, MASK_FSGNJX_D)\r
+DECLARE_INSN(fmin_d, MATCH_FMIN_D, MASK_FMIN_D)\r
+DECLARE_INSN(fmax_d, MATCH_FMAX_D, MASK_FMAX_D)\r
+DECLARE_INSN(fcvt_s_d, MATCH_FCVT_S_D, MASK_FCVT_S_D)\r
+DECLARE_INSN(fcvt_d_s, MATCH_FCVT_D_S, MASK_FCVT_D_S)\r
+DECLARE_INSN(fsqrt_d, MATCH_FSQRT_D, MASK_FSQRT_D)\r
+DECLARE_INSN(fle_s, MATCH_FLE_S, MASK_FLE_S)\r
+DECLARE_INSN(flt_s, MATCH_FLT_S, MASK_FLT_S)\r
+DECLARE_INSN(feq_s, MATCH_FEQ_S, MASK_FEQ_S)\r
+DECLARE_INSN(fle_d, MATCH_FLE_D, MASK_FLE_D)\r
+DECLARE_INSN(flt_d, MATCH_FLT_D, MASK_FLT_D)\r
+DECLARE_INSN(feq_d, MATCH_FEQ_D, MASK_FEQ_D)\r
+DECLARE_INSN(fcvt_w_s, MATCH_FCVT_W_S, MASK_FCVT_W_S)\r
+DECLARE_INSN(fcvt_wu_s, MATCH_FCVT_WU_S, MASK_FCVT_WU_S)\r
+DECLARE_INSN(fcvt_l_s, MATCH_FCVT_L_S, MASK_FCVT_L_S)\r
+DECLARE_INSN(fcvt_lu_s, MATCH_FCVT_LU_S, MASK_FCVT_LU_S)\r
+DECLARE_INSN(fmv_x_s, MATCH_FMV_X_S, MASK_FMV_X_S)\r
+DECLARE_INSN(fclass_s, MATCH_FCLASS_S, MASK_FCLASS_S)\r
+DECLARE_INSN(fcvt_w_d, MATCH_FCVT_W_D, MASK_FCVT_W_D)\r
+DECLARE_INSN(fcvt_wu_d, MATCH_FCVT_WU_D, MASK_FCVT_WU_D)\r
+DECLARE_INSN(fcvt_l_d, MATCH_FCVT_L_D, MASK_FCVT_L_D)\r
+DECLARE_INSN(fcvt_lu_d, MATCH_FCVT_LU_D, MASK_FCVT_LU_D)\r
+DECLARE_INSN(fmv_x_d, MATCH_FMV_X_D, MASK_FMV_X_D)\r
+DECLARE_INSN(fclass_d, MATCH_FCLASS_D, MASK_FCLASS_D)\r
+DECLARE_INSN(fcvt_s_w, MATCH_FCVT_S_W, MASK_FCVT_S_W)\r
+DECLARE_INSN(fcvt_s_wu, MATCH_FCVT_S_WU, MASK_FCVT_S_WU)\r
+DECLARE_INSN(fcvt_s_l, MATCH_FCVT_S_L, MASK_FCVT_S_L)\r
+DECLARE_INSN(fcvt_s_lu, MATCH_FCVT_S_LU, MASK_FCVT_S_LU)\r
+DECLARE_INSN(fmv_s_x, MATCH_FMV_S_X, MASK_FMV_S_X)\r
+DECLARE_INSN(fcvt_d_w, MATCH_FCVT_D_W, MASK_FCVT_D_W)\r
+DECLARE_INSN(fcvt_d_wu, MATCH_FCVT_D_WU, MASK_FCVT_D_WU)\r
+DECLARE_INSN(fcvt_d_l, MATCH_FCVT_D_L, MASK_FCVT_D_L)\r
+DECLARE_INSN(fcvt_d_lu, MATCH_FCVT_D_LU, MASK_FCVT_D_LU)\r
+DECLARE_INSN(fmv_d_x, MATCH_FMV_D_X, MASK_FMV_D_X)\r
+DECLARE_INSN(flw, MATCH_FLW, MASK_FLW)\r
+DECLARE_INSN(fld, MATCH_FLD, MASK_FLD)\r
+DECLARE_INSN(fsw, MATCH_FSW, MASK_FSW)\r
+DECLARE_INSN(fsd, MATCH_FSD, MASK_FSD)\r
+DECLARE_INSN(fmadd_s, MATCH_FMADD_S, MASK_FMADD_S)\r
+DECLARE_INSN(fmsub_s, MATCH_FMSUB_S, MASK_FMSUB_S)\r
+DECLARE_INSN(fnmsub_s, MATCH_FNMSUB_S, MASK_FNMSUB_S)\r
+DECLARE_INSN(fnmadd_s, MATCH_FNMADD_S, MASK_FNMADD_S)\r
+DECLARE_INSN(fmadd_d, MATCH_FMADD_D, MASK_FMADD_D)\r
+DECLARE_INSN(fmsub_d, MATCH_FMSUB_D, MASK_FMSUB_D)\r
+DECLARE_INSN(fnmsub_d, MATCH_FNMSUB_D, MASK_FNMSUB_D)\r
+DECLARE_INSN(fnmadd_d, MATCH_FNMADD_D, MASK_FNMADD_D)\r
+DECLARE_INSN(c_nop, MATCH_C_NOP, MASK_C_NOP)\r
+DECLARE_INSN(c_addi16sp, MATCH_C_ADDI16SP, MASK_C_ADDI16SP)\r
+DECLARE_INSN(c_jr, MATCH_C_JR, MASK_C_JR)\r
+DECLARE_INSN(c_jalr, MATCH_C_JALR, MASK_C_JALR)\r
+DECLARE_INSN(c_ebreak, MATCH_C_EBREAK, MASK_C_EBREAK)\r
+DECLARE_INSN(c_ld, MATCH_C_LD, MASK_C_LD)\r
+DECLARE_INSN(c_sd, MATCH_C_SD, MASK_C_SD)\r
+DECLARE_INSN(c_addiw, MATCH_C_ADDIW, MASK_C_ADDIW)\r
+DECLARE_INSN(c_ldsp, MATCH_C_LDSP, MASK_C_LDSP)\r
+DECLARE_INSN(c_sdsp, MATCH_C_SDSP, MASK_C_SDSP)\r
+DECLARE_INSN(c_addi4spn, MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN)\r
+DECLARE_INSN(c_fld, MATCH_C_FLD, MASK_C_FLD)\r
+DECLARE_INSN(c_lw, MATCH_C_LW, MASK_C_LW)\r
+DECLARE_INSN(c_flw, MATCH_C_FLW, MASK_C_FLW)\r
+DECLARE_INSN(c_fsd, MATCH_C_FSD, MASK_C_FSD)\r
+DECLARE_INSN(c_sw, MATCH_C_SW, MASK_C_SW)\r
+DECLARE_INSN(c_fsw, MATCH_C_FSW, MASK_C_FSW)\r
+DECLARE_INSN(c_addi, MATCH_C_ADDI, MASK_C_ADDI)\r
+DECLARE_INSN(c_jal, MATCH_C_JAL, MASK_C_JAL)\r
+DECLARE_INSN(c_li, MATCH_C_LI, MASK_C_LI)\r
+DECLARE_INSN(c_lui, MATCH_C_LUI, MASK_C_LUI)\r
+DECLARE_INSN(c_srli, MATCH_C_SRLI, MASK_C_SRLI)\r
+DECLARE_INSN(c_srai, MATCH_C_SRAI, MASK_C_SRAI)\r
+DECLARE_INSN(c_andi, MATCH_C_ANDI, MASK_C_ANDI)\r
+DECLARE_INSN(c_sub, MATCH_C_SUB, MASK_C_SUB)\r
+DECLARE_INSN(c_xor, MATCH_C_XOR, MASK_C_XOR)\r
+DECLARE_INSN(c_or, MATCH_C_OR, MASK_C_OR)\r
+DECLARE_INSN(c_and, MATCH_C_AND, MASK_C_AND)\r
+DECLARE_INSN(c_subw, MATCH_C_SUBW, MASK_C_SUBW)\r
+DECLARE_INSN(c_addw, MATCH_C_ADDW, MASK_C_ADDW)\r
+DECLARE_INSN(c_j, MATCH_C_J, MASK_C_J)\r
+DECLARE_INSN(c_beqz, MATCH_C_BEQZ, MASK_C_BEQZ)\r
+DECLARE_INSN(c_bnez, MATCH_C_BNEZ, MASK_C_BNEZ)\r
+DECLARE_INSN(c_slli, MATCH_C_SLLI, MASK_C_SLLI)\r
+DECLARE_INSN(c_fldsp, MATCH_C_FLDSP, MASK_C_FLDSP)\r
+DECLARE_INSN(c_lwsp, MATCH_C_LWSP, MASK_C_LWSP)\r
+DECLARE_INSN(c_flwsp, MATCH_C_FLWSP, MASK_C_FLWSP)\r
+DECLARE_INSN(c_mv, MATCH_C_MV, MASK_C_MV)\r
+DECLARE_INSN(c_add, MATCH_C_ADD, MASK_C_ADD)\r
+DECLARE_INSN(c_fsdsp, MATCH_C_FSDSP, MASK_C_FSDSP)\r
+DECLARE_INSN(c_swsp, MATCH_C_SWSP, MASK_C_SWSP)\r
+DECLARE_INSN(c_fswsp, MATCH_C_FSWSP, MASK_C_FSWSP)\r
+DECLARE_INSN(custom0, MATCH_CUSTOM0, MASK_CUSTOM0)\r
+DECLARE_INSN(custom0_rs1, MATCH_CUSTOM0_RS1, MASK_CUSTOM0_RS1)\r
+DECLARE_INSN(custom0_rs1_rs2, MATCH_CUSTOM0_RS1_RS2, MASK_CUSTOM0_RS1_RS2)\r
+DECLARE_INSN(custom0_rd, MATCH_CUSTOM0_RD, MASK_CUSTOM0_RD)\r
+DECLARE_INSN(custom0_rd_rs1, MATCH_CUSTOM0_RD_RS1, MASK_CUSTOM0_RD_RS1)\r
+DECLARE_INSN(custom0_rd_rs1_rs2, MATCH_CUSTOM0_RD_RS1_RS2, MASK_CUSTOM0_RD_RS1_RS2)\r
+DECLARE_INSN(custom1, MATCH_CUSTOM1, MASK_CUSTOM1)\r
+DECLARE_INSN(custom1_rs1, MATCH_CUSTOM1_RS1, MASK_CUSTOM1_RS1)\r
+DECLARE_INSN(custom1_rs1_rs2, MATCH_CUSTOM1_RS1_RS2, MASK_CUSTOM1_RS1_RS2)\r
+DECLARE_INSN(custom1_rd, MATCH_CUSTOM1_RD, MASK_CUSTOM1_RD)\r
+DECLARE_INSN(custom1_rd_rs1, MATCH_CUSTOM1_RD_RS1, MASK_CUSTOM1_RD_RS1)\r
+DECLARE_INSN(custom1_rd_rs1_rs2, MATCH_CUSTOM1_RD_RS1_RS2, MASK_CUSTOM1_RD_RS1_RS2)\r
+DECLARE_INSN(custom2, MATCH_CUSTOM2, MASK_CUSTOM2)\r
+DECLARE_INSN(custom2_rs1, MATCH_CUSTOM2_RS1, MASK_CUSTOM2_RS1)\r
+DECLARE_INSN(custom2_rs1_rs2, MATCH_CUSTOM2_RS1_RS2, MASK_CUSTOM2_RS1_RS2)\r
+DECLARE_INSN(custom2_rd, MATCH_CUSTOM2_RD, MASK_CUSTOM2_RD)\r
+DECLARE_INSN(custom2_rd_rs1, MATCH_CUSTOM2_RD_RS1, MASK_CUSTOM2_RD_RS1)\r
+DECLARE_INSN(custom2_rd_rs1_rs2, MATCH_CUSTOM2_RD_RS1_RS2, MASK_CUSTOM2_RD_RS1_RS2)\r
+DECLARE_INSN(custom3, MATCH_CUSTOM3, MASK_CUSTOM3)\r
+DECLARE_INSN(custom3_rs1, MATCH_CUSTOM3_RS1, MASK_CUSTOM3_RS1)\r
+DECLARE_INSN(custom3_rs1_rs2, MATCH_CUSTOM3_RS1_RS2, MASK_CUSTOM3_RS1_RS2)\r
+DECLARE_INSN(custom3_rd, MATCH_CUSTOM3_RD, MASK_CUSTOM3_RD)\r
+DECLARE_INSN(custom3_rd_rs1, MATCH_CUSTOM3_RD_RS1, MASK_CUSTOM3_RD_RS1)\r
+DECLARE_INSN(custom3_rd_rs1_rs2, MATCH_CUSTOM3_RD_RS1_RS2, MASK_CUSTOM3_RD_RS1_RS2)\r
+#endif\r
+#ifdef DECLARE_CSR\r
+DECLARE_CSR(fflags, CSR_FFLAGS)\r
+DECLARE_CSR(frm, CSR_FRM)\r
+DECLARE_CSR(fcsr, CSR_FCSR)\r
+DECLARE_CSR(cycle, CSR_CYCLE)\r
+DECLARE_CSR(time, CSR_TIME)\r
+DECLARE_CSR(instret, CSR_INSTRET)\r
+DECLARE_CSR(hpmcounter3, CSR_HPMCOUNTER3)\r
+DECLARE_CSR(hpmcounter4, CSR_HPMCOUNTER4)\r
+DECLARE_CSR(hpmcounter5, CSR_HPMCOUNTER5)\r
+DECLARE_CSR(hpmcounter6, CSR_HPMCOUNTER6)\r
+DECLARE_CSR(hpmcounter7, CSR_HPMCOUNTER7)\r
+DECLARE_CSR(hpmcounter8, CSR_HPMCOUNTER8)\r
+DECLARE_CSR(hpmcounter9, CSR_HPMCOUNTER9)\r
+DECLARE_CSR(hpmcounter10, CSR_HPMCOUNTER10)\r
+DECLARE_CSR(hpmcounter11, CSR_HPMCOUNTER11)\r
+DECLARE_CSR(hpmcounter12, CSR_HPMCOUNTER12)\r
+DECLARE_CSR(hpmcounter13, CSR_HPMCOUNTER13)\r
+DECLARE_CSR(hpmcounter14, CSR_HPMCOUNTER14)\r
+DECLARE_CSR(hpmcounter15, CSR_HPMCOUNTER15)\r
+DECLARE_CSR(hpmcounter16, CSR_HPMCOUNTER16)\r
+DECLARE_CSR(hpmcounter17, CSR_HPMCOUNTER17)\r
+DECLARE_CSR(hpmcounter18, CSR_HPMCOUNTER18)\r
+DECLARE_CSR(hpmcounter19, CSR_HPMCOUNTER19)\r
+DECLARE_CSR(hpmcounter20, CSR_HPMCOUNTER20)\r
+DECLARE_CSR(hpmcounter21, CSR_HPMCOUNTER21)\r
+DECLARE_CSR(hpmcounter22, CSR_HPMCOUNTER22)\r
+DECLARE_CSR(hpmcounter23, CSR_HPMCOUNTER23)\r
+DECLARE_CSR(hpmcounter24, CSR_HPMCOUNTER24)\r
+DECLARE_CSR(hpmcounter25, CSR_HPMCOUNTER25)\r
+DECLARE_CSR(hpmcounter26, CSR_HPMCOUNTER26)\r
+DECLARE_CSR(hpmcounter27, CSR_HPMCOUNTER27)\r
+DECLARE_CSR(hpmcounter28, CSR_HPMCOUNTER28)\r
+DECLARE_CSR(hpmcounter29, CSR_HPMCOUNTER29)\r
+DECLARE_CSR(hpmcounter30, CSR_HPMCOUNTER30)\r
+DECLARE_CSR(hpmcounter31, CSR_HPMCOUNTER31)\r
+DECLARE_CSR(sstatus, CSR_SSTATUS)\r
+DECLARE_CSR(sie, CSR_SIE)\r
+DECLARE_CSR(stvec, CSR_STVEC)\r
+DECLARE_CSR(sscratch, CSR_SSCRATCH)\r
+DECLARE_CSR(sepc, CSR_SEPC)\r
+DECLARE_CSR(scause, CSR_SCAUSE)\r
+DECLARE_CSR(sbadaddr, CSR_SBADADDR)\r
+DECLARE_CSR(sip, CSR_SIP)\r
+DECLARE_CSR(sptbr, CSR_SPTBR)\r
+DECLARE_CSR(mstatus, CSR_MSTATUS)\r
+DECLARE_CSR(misa, CSR_MISA)\r
+DECLARE_CSR(medeleg, CSR_MEDELEG)\r
+DECLARE_CSR(mideleg, CSR_MIDELEG)\r
+DECLARE_CSR(mie, CSR_MIE)\r
+DECLARE_CSR(mtvec, CSR_MTVEC)\r
+DECLARE_CSR(mscratch, CSR_MSCRATCH)\r
+DECLARE_CSR(mepc, CSR_MEPC)\r
+DECLARE_CSR(mcause, CSR_MCAUSE)\r
+DECLARE_CSR(mbadaddr, CSR_MBADADDR)\r
+DECLARE_CSR(mip, CSR_MIP)\r
+DECLARE_CSR(tselect, CSR_TSELECT)\r
+DECLARE_CSR(tdata1, CSR_TDATA1)\r
+DECLARE_CSR(tdata2, CSR_TDATA2)\r
+DECLARE_CSR(tdata3, CSR_TDATA3)\r
+DECLARE_CSR(dcsr, CSR_DCSR)\r
+DECLARE_CSR(dpc, CSR_DPC)\r
+DECLARE_CSR(dscratch, CSR_DSCRATCH)\r
+DECLARE_CSR(mcycle, CSR_MCYCLE)\r
+DECLARE_CSR(minstret, CSR_MINSTRET)\r
+DECLARE_CSR(mhpmcounter3, CSR_MHPMCOUNTER3)\r
+DECLARE_CSR(mhpmcounter4, CSR_MHPMCOUNTER4)\r
+DECLARE_CSR(mhpmcounter5, CSR_MHPMCOUNTER5)\r
+DECLARE_CSR(mhpmcounter6, CSR_MHPMCOUNTER6)\r
+DECLARE_CSR(mhpmcounter7, CSR_MHPMCOUNTER7)\r
+DECLARE_CSR(mhpmcounter8, CSR_MHPMCOUNTER8)\r
+DECLARE_CSR(mhpmcounter9, CSR_MHPMCOUNTER9)\r
+DECLARE_CSR(mhpmcounter10, CSR_MHPMCOUNTER10)\r
+DECLARE_CSR(mhpmcounter11, CSR_MHPMCOUNTER11)\r
+DECLARE_CSR(mhpmcounter12, CSR_MHPMCOUNTER12)\r
+DECLARE_CSR(mhpmcounter13, CSR_MHPMCOUNTER13)\r
+DECLARE_CSR(mhpmcounter14, CSR_MHPMCOUNTER14)\r
+DECLARE_CSR(mhpmcounter15, CSR_MHPMCOUNTER15)\r
+DECLARE_CSR(mhpmcounter16, CSR_MHPMCOUNTER16)\r
+DECLARE_CSR(mhpmcounter17, CSR_MHPMCOUNTER17)\r
+DECLARE_CSR(mhpmcounter18, CSR_MHPMCOUNTER18)\r
+DECLARE_CSR(mhpmcounter19, CSR_MHPMCOUNTER19)\r
+DECLARE_CSR(mhpmcounter20, CSR_MHPMCOUNTER20)\r
+DECLARE_CSR(mhpmcounter21, CSR_MHPMCOUNTER21)\r
+DECLARE_CSR(mhpmcounter22, CSR_MHPMCOUNTER22)\r
+DECLARE_CSR(mhpmcounter23, CSR_MHPMCOUNTER23)\r
+DECLARE_CSR(mhpmcounter24, CSR_MHPMCOUNTER24)\r
+DECLARE_CSR(mhpmcounter25, CSR_MHPMCOUNTER25)\r
+DECLARE_CSR(mhpmcounter26, CSR_MHPMCOUNTER26)\r
+DECLARE_CSR(mhpmcounter27, CSR_MHPMCOUNTER27)\r
+DECLARE_CSR(mhpmcounter28, CSR_MHPMCOUNTER28)\r
+DECLARE_CSR(mhpmcounter29, CSR_MHPMCOUNTER29)\r
+DECLARE_CSR(mhpmcounter30, CSR_MHPMCOUNTER30)\r
+DECLARE_CSR(mhpmcounter31, CSR_MHPMCOUNTER31)\r
+DECLARE_CSR(mucounteren, CSR_MUCOUNTEREN)\r
+DECLARE_CSR(mscounteren, CSR_MSCOUNTEREN)\r
+DECLARE_CSR(mhpmevent3, CSR_MHPMEVENT3)\r
+DECLARE_CSR(mhpmevent4, CSR_MHPMEVENT4)\r
+DECLARE_CSR(mhpmevent5, CSR_MHPMEVENT5)\r
+DECLARE_CSR(mhpmevent6, CSR_MHPMEVENT6)\r
+DECLARE_CSR(mhpmevent7, CSR_MHPMEVENT7)\r
+DECLARE_CSR(mhpmevent8, CSR_MHPMEVENT8)\r
+DECLARE_CSR(mhpmevent9, CSR_MHPMEVENT9)\r
+DECLARE_CSR(mhpmevent10, CSR_MHPMEVENT10)\r
+DECLARE_CSR(mhpmevent11, CSR_MHPMEVENT11)\r
+DECLARE_CSR(mhpmevent12, CSR_MHPMEVENT12)\r
+DECLARE_CSR(mhpmevent13, CSR_MHPMEVENT13)\r
+DECLARE_CSR(mhpmevent14, CSR_MHPMEVENT14)\r
+DECLARE_CSR(mhpmevent15, CSR_MHPMEVENT15)\r
+DECLARE_CSR(mhpmevent16, CSR_MHPMEVENT16)\r
+DECLARE_CSR(mhpmevent17, CSR_MHPMEVENT17)\r
+DECLARE_CSR(mhpmevent18, CSR_MHPMEVENT18)\r
+DECLARE_CSR(mhpmevent19, CSR_MHPMEVENT19)\r
+DECLARE_CSR(mhpmevent20, CSR_MHPMEVENT20)\r
+DECLARE_CSR(mhpmevent21, CSR_MHPMEVENT21)\r
+DECLARE_CSR(mhpmevent22, CSR_MHPMEVENT22)\r
+DECLARE_CSR(mhpmevent23, CSR_MHPMEVENT23)\r
+DECLARE_CSR(mhpmevent24, CSR_MHPMEVENT24)\r
+DECLARE_CSR(mhpmevent25, CSR_MHPMEVENT25)\r
+DECLARE_CSR(mhpmevent26, CSR_MHPMEVENT26)\r
+DECLARE_CSR(mhpmevent27, CSR_MHPMEVENT27)\r
+DECLARE_CSR(mhpmevent28, CSR_MHPMEVENT28)\r
+DECLARE_CSR(mhpmevent29, CSR_MHPMEVENT29)\r
+DECLARE_CSR(mhpmevent30, CSR_MHPMEVENT30)\r
+DECLARE_CSR(mhpmevent31, CSR_MHPMEVENT31)\r
+DECLARE_CSR(mvendorid, CSR_MVENDORID)\r
+DECLARE_CSR(marchid, CSR_MARCHID)\r
+DECLARE_CSR(mimpid, CSR_MIMPID)\r
+DECLARE_CSR(mhartid, CSR_MHARTID)\r
+DECLARE_CSR(cycleh, CSR_CYCLEH)\r
+DECLARE_CSR(timeh, CSR_TIMEH)\r
+DECLARE_CSR(instreth, CSR_INSTRETH)\r
+DECLARE_CSR(hpmcounter3h, CSR_HPMCOUNTER3H)\r
+DECLARE_CSR(hpmcounter4h, CSR_HPMCOUNTER4H)\r
+DECLARE_CSR(hpmcounter5h, CSR_HPMCOUNTER5H)\r
+DECLARE_CSR(hpmcounter6h, CSR_HPMCOUNTER6H)\r
+DECLARE_CSR(hpmcounter7h, CSR_HPMCOUNTER7H)\r
+DECLARE_CSR(hpmcounter8h, CSR_HPMCOUNTER8H)\r
+DECLARE_CSR(hpmcounter9h, CSR_HPMCOUNTER9H)\r
+DECLARE_CSR(hpmcounter10h, CSR_HPMCOUNTER10H)\r
+DECLARE_CSR(hpmcounter11h, CSR_HPMCOUNTER11H)\r
+DECLARE_CSR(hpmcounter12h, CSR_HPMCOUNTER12H)\r
+DECLARE_CSR(hpmcounter13h, CSR_HPMCOUNTER13H)\r
+DECLARE_CSR(hpmcounter14h, CSR_HPMCOUNTER14H)\r
+DECLARE_CSR(hpmcounter15h, CSR_HPMCOUNTER15H)\r
+DECLARE_CSR(hpmcounter16h, CSR_HPMCOUNTER16H)\r
+DECLARE_CSR(hpmcounter17h, CSR_HPMCOUNTER17H)\r
+DECLARE_CSR(hpmcounter18h, CSR_HPMCOUNTER18H)\r
+DECLARE_CSR(hpmcounter19h, CSR_HPMCOUNTER19H)\r
+DECLARE_CSR(hpmcounter20h, CSR_HPMCOUNTER20H)\r
+DECLARE_CSR(hpmcounter21h, CSR_HPMCOUNTER21H)\r
+DECLARE_CSR(hpmcounter22h, CSR_HPMCOUNTER22H)\r
+DECLARE_CSR(hpmcounter23h, CSR_HPMCOUNTER23H)\r
+DECLARE_CSR(hpmcounter24h, CSR_HPMCOUNTER24H)\r
+DECLARE_CSR(hpmcounter25h, CSR_HPMCOUNTER25H)\r
+DECLARE_CSR(hpmcounter26h, CSR_HPMCOUNTER26H)\r
+DECLARE_CSR(hpmcounter27h, CSR_HPMCOUNTER27H)\r
+DECLARE_CSR(hpmcounter28h, CSR_HPMCOUNTER28H)\r
+DECLARE_CSR(hpmcounter29h, CSR_HPMCOUNTER29H)\r
+DECLARE_CSR(hpmcounter30h, CSR_HPMCOUNTER30H)\r
+DECLARE_CSR(hpmcounter31h, CSR_HPMCOUNTER31H)\r
+DECLARE_CSR(mcycleh, CSR_MCYCLEH)\r
+DECLARE_CSR(minstreth, CSR_MINSTRETH)\r
+DECLARE_CSR(mhpmcounter3h, CSR_MHPMCOUNTER3H)\r
+DECLARE_CSR(mhpmcounter4h, CSR_MHPMCOUNTER4H)\r
+DECLARE_CSR(mhpmcounter5h, CSR_MHPMCOUNTER5H)\r
+DECLARE_CSR(mhpmcounter6h, CSR_MHPMCOUNTER6H)\r
+DECLARE_CSR(mhpmcounter7h, CSR_MHPMCOUNTER7H)\r
+DECLARE_CSR(mhpmcounter8h, CSR_MHPMCOUNTER8H)\r
+DECLARE_CSR(mhpmcounter9h, CSR_MHPMCOUNTER9H)\r
+DECLARE_CSR(mhpmcounter10h, CSR_MHPMCOUNTER10H)\r
+DECLARE_CSR(mhpmcounter11h, CSR_MHPMCOUNTER11H)\r
+DECLARE_CSR(mhpmcounter12h, CSR_MHPMCOUNTER12H)\r
+DECLARE_CSR(mhpmcounter13h, CSR_MHPMCOUNTER13H)\r
+DECLARE_CSR(mhpmcounter14h, CSR_MHPMCOUNTER14H)\r
+DECLARE_CSR(mhpmcounter15h, CSR_MHPMCOUNTER15H)\r
+DECLARE_CSR(mhpmcounter16h, CSR_MHPMCOUNTER16H)\r
+DECLARE_CSR(mhpmcounter17h, CSR_MHPMCOUNTER17H)\r
+DECLARE_CSR(mhpmcounter18h, CSR_MHPMCOUNTER18H)\r
+DECLARE_CSR(mhpmcounter19h, CSR_MHPMCOUNTER19H)\r
+DECLARE_CSR(mhpmcounter20h, CSR_MHPMCOUNTER20H)\r
+DECLARE_CSR(mhpmcounter21h, CSR_MHPMCOUNTER21H)\r
+DECLARE_CSR(mhpmcounter22h, CSR_MHPMCOUNTER22H)\r
+DECLARE_CSR(mhpmcounter23h, CSR_MHPMCOUNTER23H)\r
+DECLARE_CSR(mhpmcounter24h, CSR_MHPMCOUNTER24H)\r
+DECLARE_CSR(mhpmcounter25h, CSR_MHPMCOUNTER25H)\r
+DECLARE_CSR(mhpmcounter26h, CSR_MHPMCOUNTER26H)\r
+DECLARE_CSR(mhpmcounter27h, CSR_MHPMCOUNTER27H)\r
+DECLARE_CSR(mhpmcounter28h, CSR_MHPMCOUNTER28H)\r
+DECLARE_CSR(mhpmcounter29h, CSR_MHPMCOUNTER29H)\r
+DECLARE_CSR(mhpmcounter30h, CSR_MHPMCOUNTER30H)\r
+DECLARE_CSR(mhpmcounter31h, CSR_MHPMCOUNTER31H)\r
+#endif\r
+#ifdef DECLARE_CAUSE\r
+DECLARE_CAUSE("misaligned fetch", CAUSE_MISALIGNED_FETCH)\r
+DECLARE_CAUSE("fault fetch", CAUSE_FAULT_FETCH)\r
+DECLARE_CAUSE("illegal instruction", CAUSE_ILLEGAL_INSTRUCTION)\r
+DECLARE_CAUSE("breakpoint", CAUSE_BREAKPOINT)\r
+DECLARE_CAUSE("misaligned load", CAUSE_MISALIGNED_LOAD)\r
+DECLARE_CAUSE("fault load", CAUSE_FAULT_LOAD)\r
+DECLARE_CAUSE("misaligned store", CAUSE_MISALIGNED_STORE)\r
+DECLARE_CAUSE("fault store", CAUSE_FAULT_STORE)\r
+DECLARE_CAUSE("user_ecall", CAUSE_USER_ECALL)\r
+DECLARE_CAUSE("supervisor_ecall", CAUSE_SUPERVISOR_ECALL)\r
+DECLARE_CAUSE("hypervisor_ecall", CAUSE_HYPERVISOR_ECALL)\r
+DECLARE_CAUSE("machine_ecall", CAUSE_MACHINE_ECALL)\r
+#endif\r
--- /dev/null
+// See LICENSE for license details\r
+\r
+#ifndef ENTRY_S\r
+#define ENTRY_S\r
+\r
+#include "encoding.h"\r
+#include "sifive/bits.h"\r
+\r
+ .section .text.entry \r
+ .align 2\r
+ .weak trap_entry\r
+ .global trap_entry\r
+trap_entry:\r
+ addi sp, sp, -32*REGBYTES\r
+\r
+ STORE x1, 1*REGBYTES(sp)\r
+ STORE x2, 2*REGBYTES(sp)\r
+ STORE x3, 3*REGBYTES(sp)\r
+ STORE x4, 4*REGBYTES(sp)\r
+ STORE x5, 5*REGBYTES(sp)\r
+ STORE x6, 6*REGBYTES(sp)\r
+ STORE x7, 7*REGBYTES(sp)\r
+ STORE x8, 8*REGBYTES(sp)\r
+ STORE x9, 9*REGBYTES(sp)\r
+ STORE x10, 10*REGBYTES(sp)\r
+ STORE x11, 11*REGBYTES(sp)\r
+ STORE x12, 12*REGBYTES(sp)\r
+ STORE x13, 13*REGBYTES(sp)\r
+ STORE x14, 14*REGBYTES(sp)\r
+ STORE x15, 15*REGBYTES(sp)\r
+ STORE x16, 16*REGBYTES(sp)\r
+ STORE x17, 17*REGBYTES(sp)\r
+ STORE x18, 18*REGBYTES(sp)\r
+ STORE x19, 19*REGBYTES(sp)\r
+ STORE x20, 20*REGBYTES(sp)\r
+ STORE x21, 21*REGBYTES(sp)\r
+ STORE x22, 22*REGBYTES(sp)\r
+ STORE x23, 23*REGBYTES(sp)\r
+ STORE x24, 24*REGBYTES(sp)\r
+ STORE x25, 25*REGBYTES(sp)\r
+ STORE x26, 26*REGBYTES(sp)\r
+ STORE x27, 27*REGBYTES(sp)\r
+ STORE x28, 28*REGBYTES(sp)\r
+ STORE x29, 29*REGBYTES(sp)\r
+ STORE x30, 30*REGBYTES(sp)\r
+ STORE x31, 31*REGBYTES(sp)\r
+\r
+ csrr a0, mcause\r
+ csrr a1, mepc\r
+ mv a2, sp\r
+ call handle_trap\r
+ csrw mepc, a0\r
+\r
+ # Remain in M-mode after mret\r
+ li t0, MSTATUS_MPP\r
+ csrs mstatus, t0\r
+\r
+ LOAD x1, 1*REGBYTES(sp)\r
+ LOAD x2, 2*REGBYTES(sp)\r
+ LOAD x3, 3*REGBYTES(sp)\r
+ LOAD x4, 4*REGBYTES(sp)\r
+ LOAD x5, 5*REGBYTES(sp)\r
+ LOAD x6, 6*REGBYTES(sp)\r
+ LOAD x7, 7*REGBYTES(sp)\r
+ LOAD x8, 8*REGBYTES(sp)\r
+ LOAD x9, 9*REGBYTES(sp)\r
+ LOAD x10, 10*REGBYTES(sp)\r
+ LOAD x11, 11*REGBYTES(sp)\r
+ LOAD x12, 12*REGBYTES(sp)\r
+ LOAD x13, 13*REGBYTES(sp)\r
+ LOAD x14, 14*REGBYTES(sp)\r
+ LOAD x15, 15*REGBYTES(sp)\r
+ LOAD x16, 16*REGBYTES(sp)\r
+ LOAD x17, 17*REGBYTES(sp)\r
+ LOAD x18, 18*REGBYTES(sp)\r
+ LOAD x19, 19*REGBYTES(sp)\r
+ LOAD x20, 20*REGBYTES(sp)\r
+ LOAD x21, 21*REGBYTES(sp)\r
+ LOAD x22, 22*REGBYTES(sp)\r
+ LOAD x23, 23*REGBYTES(sp)\r
+ LOAD x24, 24*REGBYTES(sp)\r
+ LOAD x25, 25*REGBYTES(sp)\r
+ LOAD x26, 26*REGBYTES(sp)\r
+ LOAD x27, 27*REGBYTES(sp)\r
+ LOAD x28, 28*REGBYTES(sp)\r
+ LOAD x29, 29*REGBYTES(sp)\r
+ LOAD x30, 30*REGBYTES(sp)\r
+ LOAD x31, 31*REGBYTES(sp)\r
+\r
+ addi sp, sp, 32*REGBYTES\r
+ mret\r
+\r
+.weak handle_trap\r
+handle_trap:\r
+1:\r
+ j 1b\r
+ \r
+#endif\r
--- /dev/null
+OUTPUT_ARCH( "riscv" )\r
+\r
+ENTRY( _start )\r
+\r
+MEMORY\r
+{\r
+ flash (rxai!w) : ORIGIN = 0x20400000, LENGTH = 512M\r
+ ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 16K\r
+}\r
+\r
+PHDRS\r
+{\r
+ flash PT_LOAD;\r
+ ram_init PT_LOAD;\r
+ ram PT_NULL;\r
+}\r
+\r
+SECTIONS\r
+{\r
+ __stack_size = DEFINED(__stack_size) ? __stack_size : 2K;\r
+\r
+ .init :\r
+ {\r
+ KEEP (*(SORT_NONE(.init)))\r
+ } >flash AT>flash :flash\r
+\r
+ .text :\r
+ {\r
+ *(.text.unlikely .text.unlikely.*)\r
+ *(.text.startup .text.startup.*)\r
+ *(.text .text.*)\r
+ *(.gnu.linkonce.t.*)\r
+ } >flash AT>flash :flash\r
+\r
+ .fini :\r
+ {\r
+ KEEP (*(SORT_NONE(.fini)))\r
+ } >flash AT>flash :flash\r
+\r
+ PROVIDE (__etext = .);\r
+ PROVIDE (_etext = .);\r
+ PROVIDE (etext = .);\r
+\r
+ . = ALIGN(4);\r
+\r
+ .preinit_array :\r
+ {\r
+ PROVIDE_HIDDEN (__preinit_array_start = .);\r
+ KEEP (*(.preinit_array))\r
+ PROVIDE_HIDDEN (__preinit_array_end = .);\r
+ } >flash AT>flash :flash\r
+\r
+ .init_array :\r
+ {\r
+ PROVIDE_HIDDEN (__init_array_start = .);\r
+ KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))\r
+ KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))\r
+ PROVIDE_HIDDEN (__init_array_end = .);\r
+ } >flash AT>flash :flash\r
+\r
+ .fini_array :\r
+ {\r
+ PROVIDE_HIDDEN (__fini_array_start = .);\r
+ KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))\r
+ KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))\r
+ PROVIDE_HIDDEN (__fini_array_end = .);\r
+ } >flash AT>flash :flash\r
+\r
+ .ctors :\r
+ {\r
+ /* gcc uses crtbegin.o to find the start of\r
+ the constructors, so we make sure it is\r
+ first. Because this is a wildcard, it\r
+ doesn't matter if the user does not\r
+ actually link against crtbegin.o; the\r
+ linker won't look for a file to match a\r
+ wildcard. The wildcard also means that it\r
+ doesn't matter which directory crtbegin.o\r
+ is in. */\r
+ KEEP (*crtbegin.o(.ctors))\r
+ KEEP (*crtbegin?.o(.ctors))\r
+ /* We don't want to include the .ctor section from\r
+ the crtend.o file until after the sorted ctors.\r
+ The .ctor section from the crtend file contains the\r
+ end of ctors marker and it must be last */\r
+ KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))\r
+ KEEP (*(SORT(.ctors.*)))\r
+ KEEP (*(.ctors))\r
+ } >flash AT>flash :flash\r
+\r
+ .dtors :\r
+ {\r
+ KEEP (*crtbegin.o(.dtors))\r
+ KEEP (*crtbegin?.o(.dtors))\r
+ KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))\r
+ KEEP (*(SORT(.dtors.*)))\r
+ KEEP (*(.dtors))\r
+ } >flash AT>flash :flash\r
+\r
+ .lalign :\r
+ {\r
+ . = ALIGN(4);\r
+ PROVIDE( _data_lma = . );\r
+ } >flash AT>flash :flash\r
+\r
+ .dalign :\r
+ {\r
+ . = ALIGN(4);\r
+ PROVIDE( _data = . );\r
+ } >ram AT>flash :ram_init\r
+\r
+ .data :\r
+ {\r
+ *(.rdata)\r
+ *(.rodata .rodata.*)\r
+ *(.gnu.linkonce.r.*)\r
+ *(.data .data.*)\r
+ *(.gnu.linkonce.d.*)\r
+ . = ALIGN(8);\r
+ PROVIDE( __global_pointer$ = . + 0x800 );\r
+ *(.sdata .sdata.*)\r
+ *(.gnu.linkonce.s.*)\r
+ . = ALIGN(8);\r
+ *(.srodata.cst16)\r
+ *(.srodata.cst8)\r
+ *(.srodata.cst4)\r
+ *(.srodata.cst2)\r
+ *(.srodata .srodata.*)\r
+ } >ram AT>flash :ram_init\r
+\r
+ . = ALIGN(4);\r
+ PROVIDE( _edata = . );\r
+ PROVIDE( edata = . );\r
+\r
+ PROVIDE( _fbss = . );\r
+ PROVIDE( __bss_start = . );\r
+ .bss :\r
+ {\r
+ *(.sbss*)\r
+ *(.gnu.linkonce.sb.*)\r
+ *(.bss .bss.*)\r
+ *(.gnu.linkonce.b.*)\r
+ *(COMMON)\r
+ . = ALIGN(4);\r
+ } >ram AT>ram :ram\r
+\r
+ . = ALIGN(8);\r
+ PROVIDE( _end = . );\r
+ PROVIDE( end = . );\r
+\r
+ .stack ORIGIN(ram) + LENGTH(ram) - __stack_size :\r
+ {\r
+ PROVIDE( _heap_end = . );\r
+ . = __stack_size;\r
+ PROVIDE( _sp = . );\r
+ } >ram AT>ram :ram\r
+}\r
--- /dev/null
+OUTPUT_ARCH( "riscv" )\r
+\r
+ENTRY( _start )\r
+\r
+MEMORY\r
+{\r
+ flash (rxai!w) : ORIGIN = 0x20400000, LENGTH = 512M\r
+ ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 16K\r
+}\r
+\r
+PHDRS\r
+{\r
+ flash PT_LOAD;\r
+ ram_init PT_LOAD;\r
+ ram PT_NULL;\r
+}\r
+\r
+SECTIONS\r
+{\r
+ __stack_size = DEFINED(__stack_size) ? __stack_size : 2K;\r
+\r
+ .init :\r
+ {\r
+ KEEP (*(SORT_NONE(.init)))\r
+ } >flash AT>flash :flash\r
+\r
+ .text :\r
+ {\r
+ *(.text.unlikely .text.unlikely.*)\r
+ *(.text.startup .text.startup.*)\r
+ *(.text .text.*)\r
+ *(.gnu.linkonce.t.*)\r
+ } >flash AT>flash :flash\r
+\r
+ .fini :\r
+ {\r
+ KEEP (*(SORT_NONE(.fini)))\r
+ } >flash AT>flash :flash\r
+\r
+ PROVIDE (__etext = .);\r
+ PROVIDE (_etext = .);\r
+ PROVIDE (etext = .);\r
+\r
+ .rodata :\r
+ {\r
+ *(.rdata)\r
+ *(.rodata .rodata.*)\r
+ *(.gnu.linkonce.r.*)\r
+ } >flash AT>flash :flash\r
+\r
+ . = ALIGN(4);\r
+\r
+ .preinit_array :\r
+ {\r
+ PROVIDE_HIDDEN (__preinit_array_start = .);\r
+ KEEP (*(.preinit_array))\r
+ PROVIDE_HIDDEN (__preinit_array_end = .);\r
+ } >flash AT>flash :flash\r
+\r
+ .init_array :\r
+ {\r
+ PROVIDE_HIDDEN (__init_array_start = .);\r
+ KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))\r
+ KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))\r
+ PROVIDE_HIDDEN (__init_array_end = .);\r
+ } >flash AT>flash :flash\r
+\r
+ .fini_array :\r
+ {\r
+ PROVIDE_HIDDEN (__fini_array_start = .);\r
+ KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))\r
+ KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))\r
+ PROVIDE_HIDDEN (__fini_array_end = .);\r
+ } >flash AT>flash :flash\r
+\r
+ .ctors :\r
+ {\r
+ /* gcc uses crtbegin.o to find the start of\r
+ the constructors, so we make sure it is\r
+ first. Because this is a wildcard, it\r
+ doesn't matter if the user does not\r
+ actually link against crtbegin.o; the\r
+ linker won't look for a file to match a\r
+ wildcard. The wildcard also means that it\r
+ doesn't matter which directory crtbegin.o\r
+ is in. */\r
+ KEEP (*crtbegin.o(.ctors))\r
+ KEEP (*crtbegin?.o(.ctors))\r
+ /* We don't want to include the .ctor section from\r
+ the crtend.o file until after the sorted ctors.\r
+ The .ctor section from the crtend file contains the\r
+ end of ctors marker and it must be last */\r
+ KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))\r
+ KEEP (*(SORT(.ctors.*)))\r
+ KEEP (*(.ctors))\r
+ } >flash AT>flash :flash\r
+\r
+ .dtors :\r
+ {\r
+ KEEP (*crtbegin.o(.dtors))\r
+ KEEP (*crtbegin?.o(.dtors))\r
+ KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))\r
+ KEEP (*(SORT(.dtors.*)))\r
+ KEEP (*(.dtors))\r
+ } >flash AT>flash :flash\r
+\r
+ .lalign :\r
+ {\r
+ . = ALIGN(4);\r
+ PROVIDE( _data_lma = . );\r
+ } >flash AT>flash :flash\r
+\r
+ .dalign :\r
+ {\r
+ . = ALIGN(4);\r
+ PROVIDE( _data = . );\r
+ } >ram AT>flash :ram_init\r
+\r
+ .data :\r
+ {\r
+ *(.data .data.*)\r
+ *(.gnu.linkonce.d.*)\r
+ . = ALIGN(8);\r
+ PROVIDE( __global_pointer$ = . + 0x800 );\r
+ *(.sdata .sdata.*)\r
+ *(.gnu.linkonce.s.*)\r
+ . = ALIGN(8);\r
+ *(.srodata.cst16)\r
+ *(.srodata.cst8)\r
+ *(.srodata.cst4)\r
+ *(.srodata.cst2)\r
+ *(.srodata .srodata.*)\r
+ } >ram AT>flash :ram_init\r
+\r
+ . = ALIGN(4);\r
+ PROVIDE( _edata = . );\r
+ PROVIDE( edata = . );\r
+\r
+ PROVIDE( _fbss = . );\r
+ PROVIDE( __bss_start = . );\r
+ .bss :\r
+ {\r
+ *(.sbss*)\r
+ *(.gnu.linkonce.sb.*)\r
+ *(.bss .bss.*)\r
+ *(.gnu.linkonce.b.*)\r
+ *(COMMON)\r
+ . = ALIGN(4);\r
+ } >ram AT>ram :ram\r
+\r
+ . = ALIGN(8);\r
+ PROVIDE( _end = . );\r
+ PROVIDE( end = . );\r
+\r
+ .stack ORIGIN(ram) + LENGTH(ram) - __stack_size :\r
+ {\r
+ PROVIDE( _heap_end = . );\r
+ . = __stack_size;\r
+ PROVIDE( _sp = . );\r
+ } >ram AT>ram :ram\r
+}\r
--- /dev/null
+#include <stdint.h>\r
+#include <stdio.h>\r
+#include <unistd.h>\r
+\r
+#include "platform.h"\r
+#include "encoding.h"\r
+\r
+extern int main(int argc, char** argv);\r
+extern void trap_entry();\r
+\r
+static unsigned long mtime_lo(void)\r
+{\r
+ return *(volatile unsigned long *)(CLINT_CTRL_ADDR + CLINT_MTIME);\r
+}\r
+\r
+#ifdef __riscv32\r
+\r
+static uint32_t mtime_hi(void)\r
+{\r
+ return *(volatile uint32_t *)(CLINT_CTRL_ADDR + CLINT_MTIME + 4);\r
+}\r
+\r
+uint64_t get_timer_value()\r
+{\r
+ while (1) {\r
+ uint32_t hi = mtime_hi();\r
+ uint32_t lo = mtime_lo();\r
+ if (hi == mtime_hi())\r
+ return ((uint64_t)hi << 32) | lo;\r
+ }\r
+}\r
+\r
+#else /* __riscv32 */\r
+\r
+uint64_t get_timer_value()\r
+{\r
+ return mtime_lo();\r
+}\r
+\r
+#endif\r
+\r
+unsigned long get_timer_freq()\r
+{\r
+ return 32768;\r
+}\r
+\r
+static void use_hfrosc(int div, int trim)\r
+{\r
+ // Make sure the HFROSC is running at its default setting\r
+ PRCI_REG(PRCI_HFROSCCFG) = (ROSC_DIV(div) | ROSC_TRIM(trim) | ROSC_EN(1));\r
+ while ((PRCI_REG(PRCI_HFROSCCFG) & ROSC_RDY(1)) == 0) ;\r
+ PRCI_REG(PRCI_PLLCFG) &= ~PLL_SEL(1);\r
+}\r
+\r
+static void use_pll(int refsel, int bypass, int r, int f, int q)\r
+{\r
+ // Ensure that we aren't running off the PLL before we mess with it.\r
+ if (PRCI_REG(PRCI_PLLCFG) & PLL_SEL(1)) {\r
+ // Make sure the HFROSC is running at its default setting\r
+ use_hfrosc(4, 16);\r
+ }\r
+\r
+ // Set PLL Source to be HFXOSC if available.\r
+ uint32_t config_value = 0;\r
+\r
+ config_value |= PLL_REFSEL(refsel);\r
+\r
+ if (bypass) {\r
+ // Bypass\r
+ config_value |= PLL_BYPASS(1);\r
+\r
+ PRCI_REG(PRCI_PLLCFG) = config_value;\r
+\r
+ // If we don't have an HFXTAL, this doesn't really matter.\r
+ // Set our Final output divide to divide-by-1:\r
+ PRCI_REG(PRCI_PLLDIV) = (PLL_FINAL_DIV_BY_1(1) | PLL_FINAL_DIV(0));\r
+ } else {\r
+ // In case we are executing from QSPI,\r
+ // (which is quite likely) we need to\r
+ // set the QSPI clock divider appropriately\r
+ // before boosting the clock frequency.\r
+\r
+ // Div = f_sck/2\r
+ SPI0_REG(SPI_REG_SCKDIV) = 8;\r
+\r
+ // Set DIV Settings for PLL\r
+ // Both HFROSC and HFXOSC are modeled as ideal\r
+ // 16MHz sources (assuming dividers are set properly for\r
+ // HFROSC).\r
+ // (Legal values of f_REF are 6-48MHz)\r
+\r
+ // Set DIVR to divide-by-2 to get 8MHz frequency\r
+ // (legal values of f_R are 6-12 MHz)\r
+\r
+ config_value |= PLL_BYPASS(1);\r
+ config_value |= PLL_R(r);\r
+\r
+ // Set DIVF to get 512Mhz frequncy\r
+ // There is an implied multiply-by-2, 16Mhz.\r
+ // So need to write 32-1\r
+ // (legal values of f_F are 384-768 MHz)\r
+ config_value |= PLL_F(f);\r
+\r
+ // Set DIVQ to divide-by-2 to get 256 MHz frequency\r
+ // (legal values of f_Q are 50-400Mhz)\r
+ config_value |= PLL_Q(q);\r
+\r
+ // Set our Final output divide to divide-by-1:\r
+ PRCI_REG(PRCI_PLLDIV) = (PLL_FINAL_DIV_BY_1(1) | PLL_FINAL_DIV(0));\r
+\r
+ PRCI_REG(PRCI_PLLCFG) = config_value;\r
+\r
+ // Un-Bypass the PLL.\r
+ PRCI_REG(PRCI_PLLCFG) &= ~PLL_BYPASS(1);\r
+\r
+ // Wait for PLL Lock\r
+ // Note that the Lock signal can be glitchy.\r
+ // Need to wait 100 us\r
+ // RTC is running at 32kHz.\r
+ // So wait 4 ticks of RTC.\r
+ uint32_t now = mtime_lo();\r
+ while (mtime_lo() - now < 4) ;\r
+\r
+ // Now it is safe to check for PLL Lock\r
+ while ((PRCI_REG(PRCI_PLLCFG) & PLL_LOCK(1)) == 0) ;\r
+ }\r
+\r
+ // Switch over to PLL Clock source\r
+ PRCI_REG(PRCI_PLLCFG) |= PLL_SEL(1);\r
+}\r
+\r
+static void use_default_clocks()\r
+{\r
+ // Turn off the LFROSC\r
+ AON_REG(AON_LFROSC) &= ~ROSC_EN(1);\r
+\r
+ // Use HFROSC\r
+ use_hfrosc(4, 16);\r
+}\r
+\r
+static unsigned long __attribute__((noinline)) measure_cpu_freq(size_t n)\r
+{\r
+ unsigned long start_mtime, delta_mtime;\r
+ unsigned long mtime_freq = get_timer_freq();\r
+\r
+ // Don't start measuruing until we see an mtime tick\r
+ unsigned long tmp = mtime_lo();\r
+ do {\r
+ start_mtime = mtime_lo();\r
+ } while (start_mtime == tmp);\r
+\r
+ unsigned long start_mcycle = read_csr(mcycle);\r
+\r
+ do {\r
+ delta_mtime = mtime_lo() - start_mtime;\r
+ } while (delta_mtime < n);\r
+\r
+ unsigned long delta_mcycle = read_csr(mcycle) - start_mcycle;\r
+\r
+ return (delta_mcycle / delta_mtime) * mtime_freq\r
+ + ((delta_mcycle % delta_mtime) * mtime_freq) / delta_mtime;\r
+}\r
+\r
+unsigned long get_cpu_freq()\r
+{\r
+ static uint32_t cpu_freq;\r
+\r
+ if (!cpu_freq) {\r
+ // warm up I$\r
+ measure_cpu_freq(1);\r
+ // measure for real\r
+ cpu_freq = measure_cpu_freq(10);\r
+ }\r
+\r
+ return cpu_freq;\r
+}\r
+\r
+static void uart_init(size_t baud_rate)\r
+{\r
+ GPIO_REG(GPIO_IOF_SEL) &= ~IOF0_UART0_MASK;\r
+ GPIO_REG(GPIO_IOF_EN) |= IOF0_UART0_MASK;\r
+ UART0_REG(UART_REG_DIV) = get_cpu_freq() / baud_rate - 1;\r
+ UART0_REG(UART_REG_TXCTRL) |= UART_TXEN;\r
+}\r
+\r
+\r
+\r
+#ifdef USE_PLIC\r
+extern void handle_m_ext_interrupt();\r
+#endif\r
+\r
+#ifdef USE_M_TIME\r
+extern void handle_m_time_interrupt();\r
+#endif\r
+\r
+uintptr_t handle_trap(uintptr_t mcause, uintptr_t epc)\r
+{\r
+ if (0){\r
+#ifdef USE_PLIC\r
+ // External Machine-Level interrupt from PLIC\r
+ } else if ((mcause & MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) == IRQ_M_EXT)) {\r
+ handle_m_ext_interrupt();\r
+#endif\r
+#ifdef USE_M_TIME\r
+ // External Machine-Level interrupt from PLIC\r
+ } else if ((mcause & MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) == IRQ_M_TIMER)){\r
+ handle_m_time_interrupt();\r
+#endif\r
+ }\r
+ else {\r
+ write(1, "trap\n", 5);\r
+ _exit(1 + mcause);\r
+ }\r
+ return epc;\r
+}\r
+\r
+void _init()\r
+{\r
+ \r
+ #ifndef NO_INIT\r
+ use_default_clocks();\r
+ use_pll(0, 0, 1, 31, 1);\r
+ uart_init(115200);\r
+\r
+ printf("core freq at %d Hz\n", get_cpu_freq());\r
+\r
+ write_csr(mtvec, &trap_entry);\r
+ if (read_csr(misa) & (1 << ('F' - 'A'))) { // if F extension is present\r
+ write_csr(mstatus, MSTATUS_FS); // allow FPU instructions without trapping\r
+ write_csr(fcsr, 0); // initialize rounding mode, undefined at reset\r
+ }\r
+ #endif\r
+ \r
+}\r
+\r
+void _fini()\r
+{\r
+}\r
--- /dev/null
+adapter_khz 10000\r
+\r
+interface ftdi\r
+ftdi_device_desc "Dual RS232-HS"\r
+ftdi_vid_pid 0x0403 0x6010\r
+\r
+ftdi_layout_init 0x0008 0x001b\r
+ftdi_layout_signal nSRST -oe 0x0020 -data 0x0020\r
+\r
+#Reset Stretcher logic on FE310 is ~1 second long\r
+#This doesn't apply if you use\r
+# ftdi_set_signal, but still good to document\r
+#adapter_nsrst_delay 1500\r
+\r
+set _CHIPNAME riscv\r
+jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913\r
+\r
+set _TARGETNAME $_CHIPNAME.cpu\r
+target create $_TARGETNAME riscv -chain-position $_TARGETNAME\r
+$_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1\r
+\r
+flash bank onboard_spi_flash fespi 0x20000000 0 0 0 $_TARGETNAME\r
+init\r
+#reset -- This type of reset is not implemented yet\r
+if {[ info exists pulse_srst]} {\r
+ ftdi_set_signal nSRST 0\r
+ ftdi_set_signal nSRST z\r
+ #Wait for the reset stretcher\r
+ #It will work without this, but\r
+ #will incur lots of delays for later commands.\r
+ sleep 1500\r
+} \r
+halt\r
+#flash protect 0 64 last off\r
--- /dev/null
+// See LICENSE for license details.\r
+\r
+#ifndef _SIFIVE_PLATFORM_H\r
+#define _SIFIVE_PLATFORM_H\r
+\r
+// Some things missing from the official encoding.h\r
+#define MCAUSE_INT 0x80000000\r
+#define MCAUSE_CAUSE 0x7FFFFFFF\r
+\r
+#include "sifive/const.h"\r
+#include "sifive/devices/aon.h"\r
+#include "sifive/devices/clint.h"\r
+#include "sifive/devices/gpio.h"\r
+#include "sifive/devices/otp.h"\r
+#include "sifive/devices/plic.h"\r
+#include "sifive/devices/prci.h"\r
+#include "sifive/devices/pwm.h"\r
+#include "sifive/devices/spi.h"\r
+#include "sifive/devices/uart.h"\r
+\r
+/****************************************************************************\r
+ * Platform definitions\r
+ *****************************************************************************/\r
+\r
+// Memory map\r
+#define MASKROM_MEM_ADDR _AC(0x00001000,UL)\r
+#define TRAPVEC_TABLE_CTRL_ADDR _AC(0x00001010,UL)\r
+#define OTP_MEM_ADDR _AC(0x00020000,UL)\r
+#define CLINT_CTRL_ADDR _AC(0x02000000,UL)\r
+#define PLIC_CTRL_ADDR _AC(0x0C000000,UL)\r
+#define AON_CTRL_ADDR _AC(0x10000000,UL)\r
+#define PRCI_CTRL_ADDR _AC(0x10008000,UL)\r
+#define OTP_CTRL_ADDR _AC(0x10010000,UL)\r
+#define GPIO_CTRL_ADDR _AC(0x10012000,UL)\r
+#define UART0_CTRL_ADDR _AC(0x10013000,UL)\r
+#define SPI0_CTRL_ADDR _AC(0x10014000,UL)\r
+#define PWM0_CTRL_ADDR _AC(0x10015000,UL)\r
+#define UART1_CTRL_ADDR _AC(0x10023000,UL)\r
+#define SPI1_CTRL_ADDR _AC(0x10024000,UL)\r
+#define PWM1_CTRL_ADDR _AC(0x10025000,UL)\r
+#define SPI2_CTRL_ADDR _AC(0x10034000,UL)\r
+#define PWM2_CTRL_ADDR _AC(0x10035000,UL)\r
+#define SPI0_MEM_ADDR _AC(0x20000000,UL)\r
+#define MEM_CTRL_ADDR _AC(0x80000000,UL)\r
+\r
+// IOF masks\r
+#define IOF0_SPI1_MASK _AC(0x000007FC,UL)\r
+#define SPI11_NUM_SS (4)\r
+#define IOF_SPI1_SS0 (2u)\r
+#define IOF_SPI1_SS1 (8u)\r
+#define IOF_SPI1_SS2 (9u)\r
+#define IOF_SPI1_SS3 (10u)\r
+#define IOF_SPI1_MOSI (3u)\r
+#define IOF_SPI1_MISO (4u)\r
+#define IOF_SPI1_SCK (5u)\r
+#define IOF_SPI1_DQ0 (3u)\r
+#define IOF_SPI1_DQ1 (4u)\r
+#define IOF_SPI1_DQ2 (6u)\r
+#define IOF_SPI1_DQ3 (7u)\r
+\r
+#define IOF0_SPI2_MASK _AC(0xFC000000,UL)\r
+#define SPI2_NUM_SS (1)\r
+#define IOF_SPI2_SS0 (26u)\r
+#define IOF_SPI2_MOSI (27u)\r
+#define IOF_SPI2_MISO (28u)\r
+#define IOF_SPI2_SCK (29u)\r
+#define IOF_SPI2_DQ0 (27u)\r
+#define IOF_SPI2_DQ1 (28u)\r
+#define IOF_SPI2_DQ2 (30u)\r
+#define IOF_SPI2_DQ3 (31u)\r
+\r
+//#define IOF0_I2C_MASK _AC(0x00003000,UL)\r
+\r
+#define IOF0_UART0_MASK _AC(0x00030000, UL)\r
+#define IOF_UART0_RX (16u)\r
+#define IOF_UART0_TX (17u)\r
+\r
+#define IOF0_UART1_MASK _AC(0x03000000, UL)\r
+#define IOF_UART1_RX (24u)\r
+#define IOF_UART1_TX (25u)\r
+\r
+#define IOF1_PWM0_MASK _AC(0x0000000F, UL)\r
+#define IOF1_PWM1_MASK _AC(0x00780000, UL)\r
+#define IOF1_PWM2_MASK _AC(0x00003C00, UL)\r
+\r
+// Interrupt numbers\r
+#define INT_RESERVED 0\r
+#define INT_WDOGCMP 1\r
+#define INT_RTCCMP 2\r
+#define INT_UART0_BASE 3\r
+#define INT_UART1_BASE 4\r
+#define INT_SPI0_BASE 5\r
+#define INT_SPI1_BASE 6\r
+#define INT_SPI2_BASE 7\r
+#define INT_GPIO_BASE 8\r
+#define INT_PWM0_BASE 40\r
+#define INT_PWM1_BASE 44\r
+#define INT_PWM2_BASE 48\r
+\r
+// Helper functions\r
+#define _REG32(p, i) (*(volatile uint32_t *) ((p) + (i)))\r
+#define _REG32P(p, i) ((volatile uint32_t *) ((p) + (i)))\r
+#define AON_REG(offset) _REG32(AON_CTRL_ADDR, offset)\r
+#define CLINT_REG(offset) _REG32(CLINT_CTRL_ADDR, offset)\r
+#define GPIO_REG(offset) _REG32(GPIO_CTRL_ADDR, offset)\r
+#define OTP_REG(offset) _REG32(OTP_CTRL_ADDR, offset)\r
+#define PLIC_REG(offset) _REG32(PLIC_CTRL_ADDR, offset)\r
+#define PRCI_REG(offset) _REG32(PRCI_CTRL_ADDR, offset)\r
+#define PWM0_REG(offset) _REG32(PWM0_CTRL_ADDR, offset)\r
+#define PWM1_REG(offset) _REG32(PWM1_CTRL_ADDR, offset)\r
+#define PWM2_REG(offset) _REG32(PWM2_CTRL_ADDR, offset)\r
+#define SPI0_REG(offset) _REG32(SPI0_CTRL_ADDR, offset)\r
+#define SPI1_REG(offset) _REG32(SPI1_CTRL_ADDR, offset)\r
+#define SPI2_REG(offset) _REG32(SPI2_CTRL_ADDR, offset)\r
+#define UART0_REG(offset) _REG32(UART0_CTRL_ADDR, offset)\r
+#define UART1_REG(offset) _REG32(UART1_CTRL_ADDR, offset)\r
+\r
+// Misc\r
+\r
+#include <stdint.h>\r
+\r
+#define NUM_GPIO 32\r
+\r
+#define PLIC_NUM_INTERRUPTS 52\r
+#define PLIC_NUM_PRIORITIES 7\r
+\r
+#include "hifive1.h"\r
+\r
+unsigned long get_cpu_freq(void);\r
+unsigned long get_timer_freq(void);\r
+uint64_t get_timer_value(void);\r
+\r
+#endif /* _SIFIVE_PLATFORM_H */\r
--- /dev/null
+// See LICENSE for license details.\r
+\r
+#ifndef _SIFIVE_HIFIVE1_H\r
+#define _SIFIVE_HIFIVE1_H\r
+\r
+#include <stdint.h>\r
+\r
+/****************************************************************************\r
+ * GPIO Connections\r
+ *****************************************************************************/\r
+\r
+// These are the GPIO bit offsets for the RGB LED on HiFive1 Board.\r
+// These are also mapped to RGB LEDs on the Freedom E300 Arty\r
+// FPGA\r
+// Dev Kit.\r
+\r
+#define RED_LED_OFFSET 22\r
+#define GREEN_LED_OFFSET 19\r
+#define BLUE_LED_OFFSET 21\r
+\r
+// These are the GPIO bit offsets for the differen digital pins\r
+// on the headers for both the HiFive1 Board and the Freedom E300 Arty FPGA Dev Kit.\r
+#define PIN_0_OFFSET 16\r
+#define PIN_1_OFFSET 17\r
+#define PIN_2_OFFSET 18\r
+#define PIN_3_OFFSET 19\r
+#define PIN_4_OFFSET 20\r
+#define PIN_5_OFFSET 21\r
+#define PIN_6_OFFSET 22\r
+#define PIN_7_OFFSET 23\r
+#define PIN_8_OFFSET 0\r
+#define PIN_9_OFFSET 1\r
+#define PIN_10_OFFSET 2\r
+#define PIN_11_OFFSET 3\r
+#define PIN_12_OFFSET 4\r
+#define PIN_13_OFFSET 5\r
+//#define PIN_14_OFFSET 8 //This pin is not connected on either board.\r
+#define PIN_15_OFFSET 9\r
+#define PIN_16_OFFSET 10\r
+#define PIN_17_OFFSET 11\r
+#define PIN_18_OFFSET 12\r
+#define PIN_19_OFFSET 13\r
+\r
+// These are *PIN* numbers, not\r
+// GPIO Offset Numbers.\r
+#define PIN_SPI1_SCK (13u)\r
+#define PIN_SPI1_MISO (12u)\r
+#define PIN_SPI1_MOSI (11u)\r
+#define PIN_SPI1_SS0 (10u)\r
+#define PIN_SPI1_SS1 (14u) \r
+#define PIN_SPI1_SS2 (15u)\r
+#define PIN_SPI1_SS3 (16u)\r
+\r
+#define SS_PIN_TO_CS_ID(x) \\r
+ ((x==PIN_SPI1_SS0 ? 0 : \\r
+ (x==PIN_SPI1_SS1 ? 1 : \\r
+ (x==PIN_SPI1_SS2 ? 2 : \\r
+ (x==PIN_SPI1_SS3 ? 3 : \\r
+ -1))))) \r
+\r
+\r
+// These buttons are present only on the Freedom E300 Arty Dev Kit.\r
+#ifdef HAS_BOARD_BUTTONS\r
+#define BUTTON_0_OFFSET 15\r
+#define BUTTON_1_OFFSET 30\r
+#define BUTTON_2_OFFSET 31\r
+\r
+#define INT_DEVICE_BUTTON_0 (INT_GPIO_BASE + BUTTON_0_OFFSET)\r
+#define INT_DEVICE_BUTTON_1 (INT_GPIO_BASE + BUTTON_1_OFFSET)\r
+#define INT_DEVICE_BUTTON_2 (INT_GPIO_BASE + BUTTON_2_OFFSET)\r
+\r
+#endif\r
+\r
+#define HAS_HFXOSC 1\r
+#define HAS_LFROSC_BYPASS 1\r
+\r
+#define RTC_FREQ 32768\r
+\r
+void write_hex(int fd, unsigned long int hex);\r
+\r
+#endif /* _SIFIVE_HIFIVE1_H */\r
--- /dev/null
+// See LICENSE for license details.\r
+\r
+/* This is defined in sifive/platform.h, but that can't be included from\r
+ * assembly. */\r
+#define CLINT_CTRL_ADDR 0x02000000\r
+\r
+ .section .init\r
+ .globl _start\r
+ .type _start,@function\r
+\r
+_start:\r
+ .cfi_startproc\r
+ .cfi_undefined ra\r
+.option push\r
+.option norelax\r
+ la gp, __global_pointer$\r
+.option pop\r
+ la sp, _sp\r
+\r
+#if defined(ENABLE_SMP)\r
+ smp_pause(t0, t1)\r
+#endif\r
+\r
+ /* Load data section */\r
+ la a0, _data_lma\r
+ la a1, _data\r
+ la a2, _edata\r
+ bgeu a1, a2, 2f\r
+1:\r
+ lw t0, (a0)\r
+ sw t0, (a1)\r
+ addi a0, a0, 4\r
+ addi a1, a1, 4\r
+ bltu a1, a2, 1b\r
+2:\r
+\r
+ /* Clear bss section */\r
+ la a0, __bss_start\r
+ la a1, _end\r
+ bgeu a0, a1, 2f\r
+1:\r
+ sw zero, (a0)\r
+ addi a0, a0, 4\r
+ bltu a0, a1, 1b\r
+2:\r
+\r
+ /* Call global constructors */\r
+ la a0, __libc_fini_array\r
+ call atexit\r
+ call __libc_init_array\r
+\r
+#ifndef __riscv_float_abi_soft\r
+ /* Enable FPU */\r
+ li t0, MSTATUS_FS\r
+ csrs mstatus, t0\r
+ csrr t1, mstatus\r
+ and t1, t1, t0\r
+ beqz t1, 1f\r
+ fssr x0\r
+1:\r
+#endif\r
+\r
+#if defined(ENABLE_SMP)\r
+ smp_resume(t0, t1)\r
+\r
+ csrr a0, mhartid\r
+ bnez a0, 2f\r
+#endif\r
+\r
+ auipc ra, 0\r
+ addi sp, sp, -16\r
+#if __riscv_xlen == 32\r
+ sw ra, 8(sp)\r
+#else\r
+ sd ra, 8(sp)\r
+#endif\r
+\r
+ /* argc = argv = 0 */\r
+ li a0, 0\r
+ li a1, 0\r
+ call main\r
+ tail exit\r
+1:\r
+ j 1b\r
+\r
+#if defined(ENABLE_SMP)\r
+2:\r
+ la t0, trap_entry\r
+ csrw mtvec, t0\r
+\r
+ csrr a0, mhartid\r
+ la t1, _sp\r
+ slli t0, a0, 10\r
+ sub sp, t1, t0\r
+\r
+ auipc ra, 0\r
+ addi sp, sp, -16\r
+#if __riscv_xlen == 32\r
+ sw ra, 8(sp)\r
+#else\r
+ sd ra, 8(sp)\r
+#endif\r
+\r
+ call secondary_main\r
+ tail exit\r
+\r
+1:\r
+ j 1b\r
+#endif\r
+ .cfi_endproc\r
--- /dev/null
+// See LICENSE for license details.\r
+#ifndef _RISCV_BITS_H\r
+#define _RISCV_BITS_H\r
+\r
+#define likely(x) __builtin_expect((x), 1)\r
+#define unlikely(x) __builtin_expect((x), 0)\r
+\r
+#define ROUNDUP(a, b) ((((a)-1)/(b)+1)*(b))\r
+#define ROUNDDOWN(a, b) ((a)/(b)*(b))\r
+\r
+#define MAX(a, b) ((a) > (b) ? (a) : (b))\r
+#define MIN(a, b) ((a) < (b) ? (a) : (b))\r
+#define CLAMP(a, lo, hi) MIN(MAX(a, lo), hi)\r
+\r
+#define EXTRACT_FIELD(val, which) (((val) & (which)) / ((which) & ~((which)-1)))\r
+#define INSERT_FIELD(val, which, fieldval) (((val) & ~(which)) | ((fieldval) * ((which) & ~((which)-1))))\r
+\r
+#define STR(x) XSTR(x)\r
+#define XSTR(x) #x\r
+\r
+#if __riscv_xlen == 64\r
+# define SLL32 sllw\r
+# define STORE sd\r
+# define LOAD ld\r
+# define LWU lwu\r
+# define LOG_REGBYTES 3\r
+#else\r
+# define SLL32 sll\r
+# define STORE sw\r
+# define LOAD lw\r
+# define LWU lw\r
+# define LOG_REGBYTES 2\r
+#endif\r
+#define REGBYTES (1 << LOG_REGBYTES)\r
+\r
+#endif\r
--- /dev/null
+// See LICENSE for license details.\r
+/* Derived from <linux/const.h> */\r
+\r
+#ifndef _SIFIVE_CONST_H\r
+#define _SIFIVE_CONST_H\r
+\r
+#ifdef __ASSEMBLER__\r
+#define _AC(X,Y) X\r
+#define _AT(T,X) X\r
+#else\r
+#define _AC(X,Y) (X##Y)\r
+#define _AT(T,X) ((T)(X))\r
+#endif /* !__ASSEMBLER__*/\r
+\r
+#define _BITUL(x) (_AC(1,UL) << (x))\r
+#define _BITULL(x) (_AC(1,ULL) << (x))\r
+\r
+#endif /* _SIFIVE_CONST_H */\r
--- /dev/null
+// See LICENSE for license details.\r
+\r
+#ifndef _SIFIVE_AON_H\r
+#define _SIFIVE_AON_H\r
+\r
+/* Register offsets */\r
+\r
+#define AON_WDOGCFG 0x000\r
+#define AON_WDOGCOUNT 0x008\r
+#define AON_WDOGS 0x010\r
+#define AON_WDOGFEED 0x018\r
+#define AON_WDOGKEY 0x01C\r
+#define AON_WDOGCMP 0x020\r
+\r
+#define AON_RTCCFG 0x040\r
+#define AON_RTCLO 0x048\r
+#define AON_RTCHI 0x04C\r
+#define AON_RTCS 0x050\r
+#define AON_RTCCMP 0x060\r
+\r
+#define AON_BACKUP0 0x080\r
+#define AON_BACKUP1 0x084\r
+#define AON_BACKUP2 0x088\r
+#define AON_BACKUP3 0x08C\r
+#define AON_BACKUP4 0x090\r
+#define AON_BACKUP5 0x094\r
+#define AON_BACKUP6 0x098\r
+#define AON_BACKUP7 0x09C\r
+#define AON_BACKUP8 0x0A0\r
+#define AON_BACKUP9 0x0A4\r
+#define AON_BACKUP10 0x0A8\r
+#define AON_BACKUP11 0x0AC\r
+#define AON_BACKUP12 0x0B0\r
+#define AON_BACKUP13 0x0B4\r
+#define AON_BACKUP14 0x0B8\r
+#define AON_BACKUP15 0x0BC\r
+\r
+#define AON_PMUWAKEUPI0 0x100\r
+#define AON_PMUWAKEUPI1 0x104\r
+#define AON_PMUWAKEUPI2 0x108\r
+#define AON_PMUWAKEUPI3 0x10C\r
+#define AON_PMUWAKEUPI4 0x110\r
+#define AON_PMUWAKEUPI5 0x114\r
+#define AON_PMUWAKEUPI6 0x118\r
+#define AON_PMUWAKEUPI7 0x11C\r
+#define AON_PMUSLEEPI0 0x120\r
+#define AON_PMUSLEEPI1 0x124\r
+#define AON_PMUSLEEPI2 0x128\r
+#define AON_PMUSLEEPI3 0x12C\r
+#define AON_PMUSLEEPI4 0x130\r
+#define AON_PMUSLEEPI5 0x134\r
+#define AON_PMUSLEEPI6 0x138\r
+#define AON_PMUSLEEPI7 0x13C\r
+#define AON_PMUIE 0x140\r
+#define AON_PMUCAUSE 0x144\r
+#define AON_PMUSLEEP 0x148\r
+#define AON_PMUKEY 0x14C\r
+\r
+#define AON_LFROSC 0x070\r
+/* Constants */\r
+\r
+#define AON_WDOGKEY_VALUE 0x51F15E\r
+#define AON_WDOGFEED_VALUE 0xD09F00D\r
+\r
+#define AON_WDOGCFG_SCALE 0x0000000F\r
+#define AON_WDOGCFG_RSTEN 0x00000100\r
+#define AON_WDOGCFG_ZEROCMP 0x00000200\r
+#define AON_WDOGCFG_ENALWAYS 0x00001000\r
+#define AON_WDOGCFG_ENCOREAWAKE 0x00002000\r
+#define AON_WDOGCFG_CMPIP 0x10000000\r
+\r
+#define AON_RTCCFG_SCALE 0x0000000F\r
+#define AON_RTCCFG_ENALWAYS 0x00001000\r
+#define AON_RTCCFG_CMPIP 0x10000000\r
+\r
+#define AON_WAKEUPCAUSE_RESET 0x00\r
+#define AON_WAKEUPCAUSE_RTC 0x01\r
+#define AON_WAKEUPCAUSE_DWAKEUP 0x02\r
+#define AON_WAKEUPCAUSE_AWAKEUP 0x03\r
+\r
+#define AON_RESETCAUSE_POWERON 0x0000\r
+#define AON_RESETCAUSE_EXTERNAL 0x0100\r
+#define AON_RESETCAUSE_WATCHDOG 0x0200\r
+\r
+#define AON_PMUCAUSE_WAKEUPCAUSE 0x00FF\r
+#define AON_PMUCAUSE_RESETCAUSE 0xFF00\r
+\r
+#endif /* _SIFIVE_AON_H */\r
--- /dev/null
+// See LICENSE for license details\r
+\r
+#ifndef _SIFIVE_CLINT_H\r
+#define _SIFIVE_CLINT_H\r
+\r
+\r
+#define CLINT_MSIP 0x0000\r
+#define CLINT_MSIP_size 0x4\r
+#define CLINT_MTIMECMP 0x4000\r
+#define CLINT_MTIMECMP_size 0x8\r
+#define CLINT_MTIME 0xBFF8\r
+#define CLINT_MTIME_size 0x8\r
+\r
+#endif /* _SIFIVE_CLINT_H */ \r
--- /dev/null
+// See LICENSE for license details.\r
+\r
+#ifndef _SIFIVE_GPIO_H\r
+#define _SIFIVE_GPIO_H\r
+\r
+#define GPIO_INPUT_VAL (0x00)\r
+#define GPIO_INPUT_EN (0x04)\r
+#define GPIO_OUTPUT_EN (0x08)\r
+#define GPIO_OUTPUT_VAL (0x0C)\r
+#define GPIO_PULLUP_EN (0x10)\r
+#define GPIO_DRIVE (0x14)\r
+#define GPIO_RISE_IE (0x18)\r
+#define GPIO_RISE_IP (0x1C)\r
+#define GPIO_FALL_IE (0x20)\r
+#define GPIO_FALL_IP (0x24)\r
+#define GPIO_HIGH_IE (0x28)\r
+#define GPIO_HIGH_IP (0x2C)\r
+#define GPIO_LOW_IE (0x30)\r
+#define GPIO_LOW_IP (0x34)\r
+#define GPIO_IOF_EN (0x38)\r
+#define GPIO_IOF_SEL (0x3C)\r
+#define GPIO_OUTPUT_XOR (0x40)\r
+\r
+#endif /* _SIFIVE_GPIO_H */\r
--- /dev/null
+// See LICENSE for license details.\r
+\r
+#ifndef _SIFIVE_OTP_H\r
+#define _SIFIVE_OTP_H\r
+\r
+/* Register offsets */\r
+\r
+#define OTP_LOCK 0x00\r
+#define OTP_CK 0x04\r
+#define OTP_OE 0x08\r
+#define OTP_SEL 0x0C\r
+#define OTP_WE 0x10\r
+#define OTP_MR 0x14\r
+#define OTP_MRR 0x18\r
+#define OTP_MPP 0x1C\r
+#define OTP_VRREN 0x20\r
+#define OTP_VPPEN 0x24\r
+#define OTP_A 0x28\r
+#define OTP_D 0x2C\r
+#define OTP_Q 0x30\r
+#define OTP_READ_TIMINGS 0x34\r
+\r
+#endif\r
--- /dev/null
+// See LICENSE for license details.\r
+\r
+#ifndef PLIC_H\r
+#define PLIC_H\r
+\r
+#include <sifive/const.h>\r
+\r
+// 32 bits per source\r
+#define PLIC_PRIORITY_OFFSET _AC(0x0000,UL)\r
+#define PLIC_PRIORITY_SHIFT_PER_SOURCE 2\r
+// 1 bit per source (1 address)\r
+#define PLIC_PENDING_OFFSET _AC(0x1000,UL)\r
+#define PLIC_PENDING_SHIFT_PER_SOURCE 0\r
+\r
+//0x80 per target\r
+#define PLIC_ENABLE_OFFSET _AC(0x2000,UL)\r
+#define PLIC_ENABLE_SHIFT_PER_TARGET 7\r
+\r
+\r
+#define PLIC_THRESHOLD_OFFSET _AC(0x200000,UL)\r
+#define PLIC_CLAIM_OFFSET _AC(0x200004,UL)\r
+#define PLIC_THRESHOLD_SHIFT_PER_TARGET 12\r
+#define PLIC_CLAIM_SHIFT_PER_TARGET 12\r
+\r
+#define PLIC_MAX_SOURCE 1023\r
+#define PLIC_SOURCE_MASK 0x3FF\r
+\r
+#define PLIC_MAX_TARGET 15871\r
+#define PLIC_TARGET_MASK 0x3FFF\r
+\r
+#endif /* PLIC_H */\r
--- /dev/null
+// See LICENSE for license details.\r
+\r
+#ifndef _SIFIVE_PRCI_H\r
+#define _SIFIVE_PRCI_H\r
+\r
+/* Register offsets */\r
+\r
+#define PRCI_HFROSCCFG (0x0000)\r
+#define PRCI_HFXOSCCFG (0x0004)\r
+#define PRCI_PLLCFG (0x0008)\r
+#define PRCI_PLLDIV (0x000C)\r
+#define PRCI_PROCMONCFG (0x00F0)\r
+\r
+/* Fields */\r
+#define ROSC_DIV(x) (((x) & 0x2F) << 0 ) \r
+#define ROSC_TRIM(x) (((x) & 0x1F) << 16)\r
+#define ROSC_EN(x) (((x) & 0x1 ) << 30) \r
+#define ROSC_RDY(x) (((x) & 0x1 ) << 31)\r
+\r
+#define XOSC_EN(x) (((x) & 0x1) << 30)\r
+#define XOSC_RDY(x) (((x) & 0x1) << 31)\r
+\r
+#define PLL_R(x) (((x) & 0x7) << 0)\r
+// single reserved bit for F LSB.\r
+#define PLL_F(x) (((x) & 0x3F) << 4)\r
+#define PLL_Q(x) (((x) & 0x3) << 10)\r
+#define PLL_SEL(x) (((x) & 0x1) << 16)\r
+#define PLL_REFSEL(x) (((x) & 0x1) << 17)\r
+#define PLL_BYPASS(x) (((x) & 0x1) << 18)\r
+#define PLL_LOCK(x) (((x) & 0x1) << 31)\r
+\r
+#define PLL_R_default 0x1\r
+#define PLL_F_default 0x1F\r
+#define PLL_Q_default 0x3\r
+\r
+#define PLL_REFSEL_HFROSC 0x0\r
+#define PLL_REFSEL_HFXOSC 0x1\r
+\r
+#define PLL_SEL_HFROSC 0x0\r
+#define PLL_SEL_PLL 0x1\r
+\r
+#define PLL_FINAL_DIV(x) (((x) & 0x3F) << 0)\r
+#define PLL_FINAL_DIV_BY_1(x) (((x) & 0x1 ) << 8)\r
+\r
+#define PROCMON_DIV(x) (((x) & 0x1F) << 0)\r
+#define PROCMON_TRIM(x) (((x) & 0x1F) << 8)\r
+#define PROCMON_EN(x) (((x) & 0x1) << 16)\r
+#define PROCMON_SEL(x) (((x) & 0x3) << 24)\r
+#define PROCMON_NT_EN(x) (((x) & 0x1) << 28)\r
+\r
+#define PROCMON_SEL_HFCLK 0\r
+#define PROCMON_SEL_HFXOSCIN 1\r
+#define PROCMON_SEL_PLLOUTDIV 2\r
+#define PROCMON_SEL_PROCMON 3\r
+\r
+#endif // _SIFIVE_PRCI_H\r
--- /dev/null
+// See LICENSE for license details.\r
+\r
+#ifndef _SIFIVE_PWM_H\r
+#define _SIFIVE_PWM_H\r
+\r
+/* Register offsets */\r
+\r
+#define PWM_CFG 0x00\r
+#define PWM_COUNT 0x08\r
+#define PWM_S 0x10\r
+#define PWM_CMP0 0x20\r
+#define PWM_CMP1 0x24\r
+#define PWM_CMP2 0x28\r
+#define PWM_CMP3 0x2C\r
+\r
+/* Constants */\r
+\r
+#define PWM_CFG_SCALE 0x0000000F\r
+#define PWM_CFG_STICKY 0x00000100\r
+#define PWM_CFG_ZEROCMP 0x00000200\r
+#define PWM_CFG_DEGLITCH 0x00000400\r
+#define PWM_CFG_ENALWAYS 0x00001000\r
+#define PWM_CFG_ONESHOT 0x00002000\r
+#define PWM_CFG_CMP0CENTER 0x00010000\r
+#define PWM_CFG_CMP1CENTER 0x00020000\r
+#define PWM_CFG_CMP2CENTER 0x00040000\r
+#define PWM_CFG_CMP3CENTER 0x00080000\r
+#define PWM_CFG_CMP0GANG 0x01000000\r
+#define PWM_CFG_CMP1GANG 0x02000000\r
+#define PWM_CFG_CMP2GANG 0x04000000\r
+#define PWM_CFG_CMP3GANG 0x08000000\r
+#define PWM_CFG_CMP0IP 0x10000000\r
+#define PWM_CFG_CMP1IP 0x20000000\r
+#define PWM_CFG_CMP2IP 0x40000000\r
+#define PWM_CFG_CMP3IP 0x80000000\r
+\r
+#endif /* _SIFIVE_PWM_H */\r
--- /dev/null
+// See LICENSE for license details.\r
+\r
+#ifndef _SIFIVE_SPI_H\r
+#define _SIFIVE_SPI_H\r
+\r
+/* Register offsets */\r
+\r
+#define SPI_REG_SCKDIV 0x00\r
+#define SPI_REG_SCKMODE 0x04\r
+#define SPI_REG_CSID 0x10\r
+#define SPI_REG_CSDEF 0x14\r
+#define SPI_REG_CSMODE 0x18\r
+\r
+#define SPI_REG_DCSSCK 0x28\r
+#define SPI_REG_DSCKCS 0x2a\r
+#define SPI_REG_DINTERCS 0x2c\r
+#define SPI_REG_DINTERXFR 0x2e\r
+\r
+#define SPI_REG_FMT 0x40\r
+#define SPI_REG_TXFIFO 0x48\r
+#define SPI_REG_RXFIFO 0x4c\r
+#define SPI_REG_TXCTRL 0x50\r
+#define SPI_REG_RXCTRL 0x54\r
+\r
+#define SPI_REG_FCTRL 0x60\r
+#define SPI_REG_FFMT 0x64\r
+\r
+#define SPI_REG_IE 0x70\r
+#define SPI_REG_IP 0x74\r
+\r
+/* Fields */\r
+\r
+#define SPI_SCK_PHA 0x1\r
+#define SPI_SCK_POL 0x2\r
+\r
+#define SPI_FMT_PROTO(x) ((x) & 0x3)\r
+#define SPI_FMT_ENDIAN(x) (((x) & 0x1) << 2)\r
+#define SPI_FMT_DIR(x) (((x) & 0x1) << 3)\r
+#define SPI_FMT_LEN(x) (((x) & 0xf) << 16)\r
+\r
+/* TXCTRL register */\r
+#define SPI_TXWM(x) ((x) & 0xffff)\r
+/* RXCTRL register */\r
+#define SPI_RXWM(x) ((x) & 0xffff)\r
+\r
+#define SPI_IP_TXWM 0x1\r
+#define SPI_IP_RXWM 0x2\r
+\r
+#define SPI_FCTRL_EN 0x1\r
+\r
+#define SPI_INSN_CMD_EN 0x1\r
+#define SPI_INSN_ADDR_LEN(x) (((x) & 0x7) << 1)\r
+#define SPI_INSN_PAD_CNT(x) (((x) & 0xf) << 4)\r
+#define SPI_INSN_CMD_PROTO(x) (((x) & 0x3) << 8)\r
+#define SPI_INSN_ADDR_PROTO(x) (((x) & 0x3) << 10)\r
+#define SPI_INSN_DATA_PROTO(x) (((x) & 0x3) << 12)\r
+#define SPI_INSN_CMD_CODE(x) (((x) & 0xff) << 16)\r
+#define SPI_INSN_PAD_CODE(x) (((x) & 0xff) << 24)\r
+\r
+#define SPI_TXFIFO_FULL (1 << 31) \r
+#define SPI_RXFIFO_EMPTY (1 << 31) \r
+\r
+/* Values */\r
+\r
+#define SPI_CSMODE_AUTO 0\r
+#define SPI_CSMODE_HOLD 2\r
+#define SPI_CSMODE_OFF 3\r
+\r
+#define SPI_DIR_RX 0\r
+#define SPI_DIR_TX 1\r
+\r
+#define SPI_PROTO_S 0\r
+#define SPI_PROTO_D 1\r
+#define SPI_PROTO_Q 2\r
+\r
+#define SPI_ENDIAN_MSB 0\r
+#define SPI_ENDIAN_LSB 1\r
+\r
+\r
+#endif /* _SIFIVE_SPI_H */\r
--- /dev/null
+// See LICENSE for license details.\r
+\r
+#ifndef _SIFIVE_UART_H\r
+#define _SIFIVE_UART_H\r
+\r
+/* Register offsets */\r
+#define UART_REG_TXFIFO 0x00\r
+#define UART_REG_RXFIFO 0x04\r
+#define UART_REG_TXCTRL 0x08\r
+#define UART_REG_RXCTRL 0x0c\r
+#define UART_REG_IE 0x10\r
+#define UART_REG_IP 0x14\r
+#define UART_REG_DIV 0x18\r
+\r
+/* TXCTRL register */\r
+#define UART_TXEN 0x1\r
+#define UART_TXWM(x) (((x) & 0xffff) << 16)\r
+\r
+/* RXCTRL register */\r
+#define UART_RXEN 0x1\r
+#define UART_RXWM(x) (((x) & 0xffff) << 16)\r
+\r
+/* IP register */\r
+#define UART_IP_TXWM 0x1\r
+#define UART_IP_RXWM 0x2\r
+\r
+#endif /* _SIFIVE_UART_H */\r
--- /dev/null
+// See LICENSE for license details.\r
+#ifndef _SECTIONS_H\r
+#define _SECTIONS_H\r
+\r
+extern unsigned char _rom[];\r
+extern unsigned char _rom_end[];\r
+\r
+extern unsigned char _ram[];\r
+extern unsigned char _ram_end[];\r
+\r
+extern unsigned char _ftext[];\r
+extern unsigned char _etext[];\r
+extern unsigned char _fbss[];\r
+extern unsigned char _ebss[];\r
+extern unsigned char _end[];\r
+\r
+#endif /* _SECTIONS_H */\r
--- /dev/null
+#ifndef SIFIVE_SMP\r
+#define SIFIVE_SMP\r
+\r
+// The maximum number of HARTs this code supports\r
+#ifndef MAX_HARTS\r
+#define MAX_HARTS 32\r
+#endif\r
+#define CLINT_END_HART_IPI CLINT_CTRL_ADDR + (MAX_HARTS*4)\r
+\r
+// The hart that non-SMP tests should run on\r
+#ifndef NONSMP_HART\r
+#define NONSMP_HART 0\r
+#endif\r
+\r
+/* If your test cannot handle multiple-threads, use this: \r
+ * smp_disable(reg1)\r
+ */\r
+#define smp_disable(reg1, reg2) \\r
+ csrr reg1, mhartid ;\\r
+ li reg2, NONSMP_HART ;\\r
+ beq reg1, reg2, hart0_entry ;\\r
+42: ;\\r
+ wfi ;\\r
+ j 42b ;\\r
+hart0_entry:\r
+\r
+/* If your test needs to temporarily block multiple-threads, do this:\r
+ * smp_pause(reg1, reg2)\r
+ * ... single-threaded work ...\r
+ * smp_resume(reg1, reg2)\r
+ * ... multi-threaded work ...\r
+ */\r
+\r
+#define smp_pause(reg1, reg2) \\r
+ li reg2, 0x8 ;\\r
+ csrw mie, reg2 ;\\r
+ csrr reg2, mhartid ;\\r
+ bnez reg2, 42f\r
+\r
+#define smp_resume(reg1, reg2) \\r
+ li reg1, CLINT_CTRL_ADDR ;\\r
+41: ;\\r
+ li reg2, 1 ;\\r
+ sw reg2, 0(reg1) ;\\r
+ addi reg1, reg1, 4 ;\\r
+ li reg2, CLINT_END_HART_IPI ;\\r
+ blt reg1, reg2, 41b ;\\r
+42: ;\\r
+ wfi ;\\r
+ csrr reg2, mip ;\\r
+ andi reg2, reg2, 0x8 ;\\r
+ beqz reg2, 42b ;\\r
+ li reg1, CLINT_CTRL_ADDR ;\\r
+ csrr reg2, mhartid ;\\r
+ slli reg2, reg2, 2 ;\\r
+ add reg2, reg2, reg1 ;\\r
+ sw zero, 0(reg2) ;\\r
+41: ;\\r
+ lw reg2, 0(reg1) ;\\r
+ bnez reg2, 41b ;\\r
+ addi reg1, reg1, 4 ;\\r
+ li reg2, CLINT_END_HART_IPI ;\\r
+ blt reg1, reg2, 41b\r
+\r
+#endif\r
--- /dev/null
+/* See LICENSE of license details. */\r
+\r
+#include <stdint.h>\r
+#include <unistd.h>\r
+#include "platform.h"\r
+\r
+void write_hex(int fd, unsigned long int hex)\r
+{\r
+ uint8_t ii;\r
+ uint8_t jj;\r
+ char towrite;\r
+ write(fd , "0x", 2);\r
+ for (ii = sizeof(unsigned long int) * 2 ; ii > 0; ii--) {\r
+ jj = ii - 1;\r
+ uint8_t digit = ((hex & (0xF << (jj*4))) >> (jj*4));\r
+ towrite = digit < 0xA ? ('0' + digit) : ('A' + (digit - 0xA));\r
+ write(fd, &towrite, 1);\r
+ }\r
+}\r
--- /dev/null
+/* See LICENSE for license details. */\r
+\r
+/* These functions are intended for embedded RV32 systems and are\r
+ obviously incorrect in general. */\r
+\r
+void* __wrap_malloc(unsigned long sz)\r
+{\r
+ extern void* sbrk(long);\r
+ void* res = sbrk(sz);\r
+ if ((long)res == -1)\r
+ return 0;\r
+ return res;\r
+}\r
+\r
+void __wrap_free(void* ptr)\r
+{\r
+}\r
--- /dev/null
+/* See LICENSE of license details. */\r
+\r
+#include <unistd.h>\r
+#include "platform.h"\r
+#include "weak_under_alias.h"\r
+\r
+void __wrap_exit(int code)\r
+{\r
+ const char message[] = "\nProgam has exited with code:";\r
+\r
+ write(STDERR_FILENO, message, sizeof(message) - 1);\r
+ write_hex(STDERR_FILENO, code);\r
+ write(STDERR_FILENO, "\n", 1);\r
+\r
+ for (;;);\r
+}\r
+weak_under_alias(exit);\r
--- /dev/null
+/* See LICENSE of license details. */\r
+\r
+#include <errno.h>\r
+#include "stub.h"\r
+#include "weak_under_alias.h"\r
+\r
+int __wrap_close(int fd)\r
+{\r
+ return _stub(EBADF);\r
+}\r
+weak_under_alias(close);\r
--- /dev/null
+/* See LICENSE of license details. */\r
+\r
+#include <errno.h>\r
+#include "stub.h"\r
+#include "weak_under_alias.h"\r
+\r
+int __wrap_execve(const char* name, char* const argv[], char* const env[])\r
+{\r
+ return _stub(ENOMEM);\r
+}\r
+weak_under_alias(execve);\r
--- /dev/null
+/* See LICENSE of license details. */\r
+\r
+#include <errno.h>\r
+#include "stub.h"\r
+\r
+int fork(void)\r
+{\r
+ return _stub(EAGAIN);\r
+}\r
--- /dev/null
+/* See LICENSE of license details. */\r
+\r
+#include <errno.h>\r
+#include <unistd.h>\r
+#include <sys/stat.h>\r
+#include "stub.h"\r
+#include "weak_under_alias.h"\r
+\r
+int __wrap_fstat(int fd, struct stat* st)\r
+{\r
+ if (isatty(fd)) {\r
+ st->st_mode = S_IFCHR;\r
+ return 0;\r
+ }\r
+\r
+ return _stub(EBADF);\r
+}\r
+weak_under_alias(fstat);\r
--- /dev/null
+/* See LICENSE of license details. */\r
+#include "weak_under_alias.h"\r
+\r
+int __wrap_getpid(void)\r
+{\r
+ return 1;\r
+}\r
+weak_under_alias(getpid);\r
--- /dev/null
+/* See LICENSE of license details. */\r
+\r
+#include <unistd.h>\r
+#include "weak_under_alias.h"\r
+\r
+int __wrap_isatty(int fd)\r
+{\r
+ if (fd == STDOUT_FILENO || fd == STDERR_FILENO)\r
+ return 1;\r
+\r
+ return 0;\r
+}\r
+weak_under_alias(isatty);\r
--- /dev/null
+/* See LICENSE of license details. */\r
+\r
+#include <errno.h>\r
+#include "stub.h"\r
+#include "weak_under_alias.h"\r
+\r
+int __wrap_kill(int pid, int sig)\r
+{\r
+ return _stub(EINVAL);\r
+}\r
+weak_under_alias(kill);\r
--- /dev/null
+/* See LICENSE of license details. */\r
+\r
+#include <errno.h>\r
+#include "stub.h"\r
+#include "weak_under_alias.h"\r
+\r
+int __wrap_link(const char *old_name, const char *new_name)\r
+{\r
+ return _stub(EMLINK);\r
+}\r
+weak_under_alias(link);\r
--- /dev/null
+/* See LICENSE of license details. */\r
+\r
+#include <errno.h>\r
+#include <unistd.h>\r
+#include <sys/types.h>\r
+#include "stub.h"\r
+#include "weak_under_alias.h"\r
+\r
+off_t __wrap_lseek(int fd, off_t ptr, int dir)\r
+{\r
+ if (isatty(fd))\r
+ return 0;\r
+\r
+ return _stub(EBADF);\r
+}\r
+weak_under_alias(lseek);\r
--- /dev/null
+/* See LICENSE of license details. */\r
+\r
+#include <errno.h>\r
+#include "stub.h"\r
+#include "weak_under_alias.h"\r
+\r
+int __wrap_open(const char* name, int flags, int mode)\r
+{\r
+ return _stub(ENOENT);\r
+}\r
+weak_under_alias(open);\r
--- /dev/null
+/* See LICENSE of license details. */\r
+\r
+#include <errno.h>\r
+#include "stub.h"\r
+#include "weak_under_alias.h"\r
+\r
+int __wrap_openat(int dirfd, const char* name, int flags, int mode)\r
+{\r
+ return _stub(ENOENT);\r
+}\r
+weak_under_alias(openat);\r
--- /dev/null
+/* See LICENSE of license details. */\r
+\r
+#include <stdint.h>\r
+#include <errno.h>\r
+#include <unistd.h>\r
+#include <sys/types.h>\r
+\r
+#include "platform.h"\r
+#include "stub.h"\r
+#include "weak_under_alias.h"\r
+\r
+int __wrap_puts(const char *s)\r
+{\r
+ while (*s != '\0') {\r
+ while (UART0_REG(UART_REG_TXFIFO) & 0x80000000) ;\r
+ UART0_REG(UART_REG_TXFIFO) = *s;\r
+\r
+ if (*s == '\n') {\r
+ while (UART0_REG(UART_REG_TXFIFO) & 0x80000000) ;\r
+ UART0_REG(UART_REG_TXFIFO) = '\r';\r
+ }\r
+\r
+ ++s;\r
+ }\r
+\r
+ return 0;\r
+}\r
+weak_under_alias(puts);\r
--- /dev/null
+/* See LICENSE of license details. */\r
+\r
+#include <stdint.h>\r
+#include <errno.h>\r
+#include <unistd.h>\r
+#include <sys/types.h>\r
+\r
+#include "platform.h"\r
+#include "stub.h"\r
+#include "weak_under_alias.h"\r
+\r
+ssize_t __wrap_read(int fd, void* ptr, size_t len)\r
+{\r
+ uint8_t * current = (uint8_t *)ptr;\r
+ volatile uint32_t * uart_rx = (uint32_t *)(UART0_CTRL_ADDR + UART_REG_RXFIFO);\r
+ volatile uint8_t * uart_rx_cnt = (uint8_t *)(UART0_CTRL_ADDR + UART_REG_RXCTRL + 2);\r
+\r
+ ssize_t result = 0;\r
+\r
+ if (isatty(fd)) {\r
+ for (current = (uint8_t *)ptr;\r
+ (current < ((uint8_t *)ptr) + len) && (*uart_rx_cnt > 0);\r
+ current ++) {\r
+ *current = *uart_rx;\r
+ result++;\r
+ }\r
+ return result;\r
+ }\r
+\r
+ return _stub(EBADF);\r
+}\r
+weak_under_alias(read);\r
--- /dev/null
+/* See LICENSE of license details. */\r
+\r
+#include <stddef.h>\r
+#include "weak_under_alias.h"\r
+\r
+void *__wrap_sbrk(ptrdiff_t incr)\r
+{\r
+ extern char _end[];\r
+ extern char _heap_end[];\r
+ static char *curbrk = _end;\r
+\r
+ if ((curbrk + incr < _end) || (curbrk + incr > _heap_end))\r
+ return NULL - 1;\r
+\r
+ curbrk += incr;\r
+ return curbrk - incr;\r
+}\r
+weak_under_alias(sbrk);\r
--- /dev/null
+/* See LICENSE of license details. */\r
+\r
+#include <errno.h>\r
+#include <sys/stat.h>\r
+#include "stub.h"\r
+#include "weak_under_alias.h"\r
+\r
+int __wrap_stat(const char* file, struct stat* st)\r
+{\r
+ return _stub(EACCES);\r
+}\r
+weak_under_alias(stat);\r
--- /dev/null
+/* See LICENSE of license details. */\r
+#ifndef _SIFIVE_SYS_STUB_H\r
+#define _SIFIVE_SYS_STUB_H\r
+\r
+static inline int _stub(int err)\r
+{\r
+ return -1;\r
+}\r
+\r
+#endif /* _SIFIVE_SYS_STUB_H */\r
--- /dev/null
+/* See LICENSE of license details. */\r
+\r
+#include <errno.h>\r
+#include <sys/times.h>\r
+#include "stub.h"\r
+#include "weak_under_alias.h"\r
+\r
+clock_t __wrap_times(struct tms* buf)\r
+{\r
+ return _stub(EACCES);\r
+}\r
+weak_under_alias(times);\r
--- /dev/null
+/* See LICENSE of license details. */\r
+\r
+#include <errno.h>\r
+#include "stub.h"\r
+#include "weak_under_alias.h"\r
+\r
+int __wrap_unlink(const char* name)\r
+{\r
+ return _stub(ENOENT);\r
+}\r
+weak_under_alias(unlink);\r
--- /dev/null
+/* See LICENSE of license details. */\r
+\r
+#include <errno.h>\r
+#include "stub.h"\r
+\r
+int wait(int* status)\r
+{\r
+ return _stub(ECHILD);\r
+}\r
--- /dev/null
+#ifndef _BSP_LIBWRAP_WEAK_UNDER_ALIAS_H\r
+#define _BSP_LIBWRAP_WEAK_UNDER_ALIAS_H\r
+\r
+#define weak_under_alias(name) \\r
+ extern __typeof (__wrap_##name) __wrap__##name __attribute__ ((weak, alias ("__wrap_"#name)))\r
+\r
+#endif\r
--- /dev/null
+/* See LICENSE of license details. */\r
+\r
+#include <stdint.h>\r
+#include <errno.h>\r
+#include <unistd.h>\r
+#include <sys/types.h>\r
+\r
+#include "platform.h"\r
+#include "stub.h"\r
+#include "weak_under_alias.h"\r
+\r
+ssize_t __wrap_write(int fd, const void* ptr, size_t len)\r
+{\r
+ const uint8_t * current = (const char *)ptr;\r
+\r
+ if (isatty(fd)) {\r
+ for (size_t jj = 0; jj < len; jj++) {\r
+ while (UART0_REG(UART_REG_TXFIFO) & 0x80000000) ;\r
+ UART0_REG(UART_REG_TXFIFO) = current[jj];\r
+\r
+ if (current[jj] == '\n') {\r
+ while (UART0_REG(UART_REG_TXFIFO) & 0x80000000) ;\r
+ UART0_REG(UART_REG_TXFIFO) = '\r';\r
+ }\r
+ }\r
+ return len;\r
+ }\r
+\r
+ return _stub(EBADF);\r
+}\r
+weak_under_alias(write);\r
--- /dev/null
+// See LICENSE for license details.\r
+\r
+#include <stdio.h>\r
+#include <stdlib.h>\r
+#include "platform.h"\r
+#include <string.h>\r
+#include "plic/plic_driver.h"\r
+#include "encoding.h"\r
+#include <unistd.h>\r
+#include "stdatomic.h"\r
+\r
+void reset_demo (void);\r
+\r
+// Structures for registering different interrupt handlers\r
+// for different parts of the application.\r
+typedef void (*function_ptr_t) (void);\r
+\r
+void no_interrupt_handler (void) {};\r
+\r
+function_ptr_t g_ext_interrupt_handlers[PLIC_NUM_INTERRUPTS];\r
+\r
+\r
+// Instance data for the PLIC.\r
+\r
+plic_instance_t g_plic;\r
+\r
+\r
+/*Entry Point for PLIC Interrupt Handler*/\r
+void handle_m_ext_interrupt(){\r
+ plic_source int_num = PLIC_claim_interrupt(&g_plic);\r
+ if ((int_num >=1 ) && (int_num < PLIC_NUM_INTERRUPTS)) {\r
+ g_ext_interrupt_handlers[int_num]();\r
+ }\r
+ else {\r
+ exit(1 + (uintptr_t) int_num);\r
+ }\r
+ PLIC_complete_interrupt(&g_plic, int_num);\r
+}\r
+\r
+\r
+/*Entry Point for Machine Timer Interrupt Handler*/\r
+void handle_m_time_interrupt(){\r
+\r
+ clear_csr(mie, MIP_MTIP);\r
+\r
+ // Reset the timer for 3s in the future.\r
+ // This also clears the existing timer interrupt.\r
+\r
+ volatile uint64_t * mtime = (uint64_t*) (CLINT_CTRL_ADDR + CLINT_MTIME);\r
+ volatile uint64_t * mtimecmp = (uint64_t*) (CLINT_CTRL_ADDR + CLINT_MTIMECMP);\r
+ uint64_t now = *mtime;\r
+ uint64_t then = now + 2 * RTC_FREQ;\r
+ *mtimecmp = then;\r
+\r
+ // read the current value of the LEDS and invert them.\r
+ uint32_t leds = GPIO_REG(GPIO_OUTPUT_VAL);\r
+\r
+ GPIO_REG(GPIO_OUTPUT_VAL) ^= ((0x1 << RED_LED_OFFSET) |\r
+ (0x1 << GREEN_LED_OFFSET) |\r
+ (0x1 << BLUE_LED_OFFSET));\r
+ \r
+ // Re-enable the timer interrupt.\r
+ set_csr(mie, MIP_MTIP);\r
+\r
+}\r
+\r
+\r
+const char * instructions_msg = " \\r
+\n\\r
+ SIFIVE, INC.\n\\r
+\n\\r
+ 5555555555555555555555555\n\\r
+ 5555 5555\n\\r
+ 5555 5555\n\\r
+ 5555 5555\n\\r
+ 5555 5555555555555555555555\n\\r
+ 5555 555555555555555555555555\n\\r
+ 5555 5555\n\\r
+ 5555 5555\n\\r
+ 5555 5555\n\\r
+5555555555555555555555555555 55555\n\\r
+ 55555 555555555 55555\n\\r
+ 55555 55555 55555\n\\r
+ 55555 5 55555\n\\r
+ 55555 55555\n\\r
+ 55555 55555\n\\r
+ 55555 55555\n\\r
+ 55555 55555\n\\r
+ 55555 55555\n\\r
+ 555555555\n\\r
+ 55555\n\\r
+ 5\n\\r
+\n\\r
+SiFive E-Series Software Development Kit 'demo_gpio' program.\n\\r
+Every 2 second, the Timer Interrupt will invert the LEDs.\n\\r
+(Arty Dev Kit Only): Press Buttons 0, 1, 2 to Set the LEDs.\n\\r
+Pin 19 (HiFive1) or A5 (Arty Dev Kit) is being bit-banged\n\\r
+for GPIO speed demonstration.\n\\r
+\n\\r
+ ";\r
+\r
+void print_instructions() {\r
+\r
+ write (STDOUT_FILENO, instructions_msg, strlen(instructions_msg));\r
+\r
+}\r
+\r
+#ifdef HAS_BOARD_BUTTONS\r
+void button_0_handler(void) {\r
+\r
+ // Red LED on\r
+ GPIO_REG(GPIO_OUTPUT_VAL) |= (0x1 << RED_LED_OFFSET);\r
+\r
+ // Clear the GPIO Pending interrupt by writing 1.\r
+ GPIO_REG(GPIO_RISE_IP) = (0x1 << BUTTON_0_OFFSET);\r
+\r
+};\r
+\r
+void button_1_handler(void) {\r
+\r
+ // Green LED On\r
+ GPIO_REG(GPIO_OUTPUT_VAL) |= (1 << GREEN_LED_OFFSET);\r
+\r
+ // Clear the GPIO Pending interrupt by writing 1.\r
+ GPIO_REG(GPIO_RISE_IP) = (0x1 << BUTTON_1_OFFSET);\r
+\r
+};\r
+\r
+\r
+void button_2_handler(void) {\r
+\r
+ // Blue LED On\r
+ GPIO_REG(GPIO_OUTPUT_VAL) |= (1 << BLUE_LED_OFFSET);\r
+\r
+ GPIO_REG(GPIO_RISE_IP) = (0x1 << BUTTON_2_OFFSET);\r
+\r
+};\r
+#endif\r
+\r
+void reset_demo (){\r
+\r
+ // Disable the machine & timer interrupts until setup is done.\r
+\r
+ clear_csr(mie, MIP_MEIP);\r
+ clear_csr(mie, MIP_MTIP);\r
+\r
+ for (int ii = 0; ii < PLIC_NUM_INTERRUPTS; ii ++){\r
+ g_ext_interrupt_handlers[ii] = no_interrupt_handler;\r
+ }\r
+\r
+#ifdef HAS_BOARD_BUTTONS\r
+ g_ext_interrupt_handlers[INT_DEVICE_BUTTON_0] = button_0_handler;\r
+ g_ext_interrupt_handlers[INT_DEVICE_BUTTON_1] = button_1_handler;\r
+ g_ext_interrupt_handlers[INT_DEVICE_BUTTON_2] = button_2_handler;\r
+#endif\r
+\r
+ print_instructions();\r
+\r
+#ifdef HAS_BOARD_BUTTONS\r
+\r
+ // Have to enable the interrupt both at the GPIO level,\r
+ // and at the PLIC level.\r
+ PLIC_enable_interrupt (&g_plic, INT_DEVICE_BUTTON_0);\r
+ PLIC_enable_interrupt (&g_plic, INT_DEVICE_BUTTON_1);\r
+ PLIC_enable_interrupt (&g_plic, INT_DEVICE_BUTTON_2);\r
+\r
+ // Priority must be set > 0 to trigger the interrupt.\r
+ PLIC_set_priority(&g_plic, INT_DEVICE_BUTTON_0, 1);\r
+ PLIC_set_priority(&g_plic, INT_DEVICE_BUTTON_1, 1);\r
+ PLIC_set_priority(&g_plic, INT_DEVICE_BUTTON_2, 1);\r
+\r
+ GPIO_REG(GPIO_RISE_IE) |= (1 << BUTTON_0_OFFSET);\r
+ GPIO_REG(GPIO_RISE_IE) |= (1 << BUTTON_1_OFFSET);\r
+ GPIO_REG(GPIO_RISE_IE) |= (1 << BUTTON_2_OFFSET);\r
+\r
+#endif\r
+\r
+ // Set the machine timer to go off in 3 seconds.\r
+ // The\r
+ volatile uint64_t * mtime = (uint64_t*) (CLINT_CTRL_ADDR + CLINT_MTIME);\r
+ volatile uint64_t * mtimecmp = (uint64_t*) (CLINT_CTRL_ADDR + CLINT_MTIMECMP);\r
+ uint64_t now = *mtime;\r
+ uint64_t then = now + 2*RTC_FREQ;\r
+ *mtimecmp = then;\r
+\r
+ // Enable the Machine-External bit in MIE\r
+ set_csr(mie, MIP_MEIP);\r
+\r
+ // Enable the Machine-Timer bit in MIE\r
+ set_csr(mie, MIP_MTIP);\r
+\r
+ // Enable interrupts in general.\r
+ set_csr(mstatus, MSTATUS_MIE);\r
+}\r
+\r
+int main(int argc, char **argv)\r
+{\r
+ // Set up the GPIOs such that the LED GPIO\r
+ // can be used as both Inputs and Outputs.\r
+ \r
+\r
+#ifdef HAS_BOARD_BUTTONS\r
+ GPIO_REG(GPIO_OUTPUT_EN) &= ~((0x1 << BUTTON_0_OFFSET) | (0x1 << BUTTON_1_OFFSET) | (0x1 << BUTTON_2_OFFSET));\r
+ GPIO_REG(GPIO_PULLUP_EN) &= ~((0x1 << BUTTON_0_OFFSET) | (0x1 << BUTTON_1_OFFSET) | (0x1 << BUTTON_2_OFFSET));\r
+ GPIO_REG(GPIO_INPUT_EN) |= ((0x1 << BUTTON_0_OFFSET) | (0x1 << BUTTON_1_OFFSET) | (0x1 << BUTTON_2_OFFSET));\r
+#endif\r
+\r
+ GPIO_REG(GPIO_INPUT_EN) &= ~((0x1<< RED_LED_OFFSET) | (0x1<< GREEN_LED_OFFSET) | (0x1 << BLUE_LED_OFFSET)) ;\r
+ GPIO_REG(GPIO_OUTPUT_EN) |= ((0x1<< RED_LED_OFFSET)| (0x1<< GREEN_LED_OFFSET) | (0x1 << BLUE_LED_OFFSET)) ;\r
+ GPIO_REG(GPIO_OUTPUT_VAL) |= (0x1 << BLUE_LED_OFFSET) ;\r
+ GPIO_REG(GPIO_OUTPUT_VAL) &= ~((0x1<< RED_LED_OFFSET) | (0x1<< GREEN_LED_OFFSET)) ;\r
+\r
+ \r
+ // For Bit-banging with Atomics demo.\r
+ \r
+ uint32_t bitbang_mask = 0;\r
+#ifdef _SIFIVE_HIFIVE1_H\r
+ bitbang_mask = (1 << PIN_19_OFFSET);\r
+#else\r
+#ifdef _SIFIVE_COREPLEXIP_ARTY_H\r
+ bitbang_mask = (0x1 << JA_0_OFFSET);\r
+#endif\r
+#endif\r
+\r
+ GPIO_REG(GPIO_OUTPUT_EN) |= bitbang_mask;\r
+ \r
+ /**************************************************************************\r
+ * Set up the PLIC\r
+ *\r
+ *************************************************************************/\r
+ PLIC_init(&g_plic,\r
+ PLIC_CTRL_ADDR,\r
+ PLIC_NUM_INTERRUPTS,\r
+ PLIC_NUM_PRIORITIES);\r
+\r
+ reset_demo();\r
+\r
+ /**************************************************************************\r
+ * Demonstrate fast GPIO bit-banging.\r
+ * One can bang it faster than this if you know\r
+ * the entire OUTPUT_VAL that you want to write, but \r
+ * Atomics give a quick way to control a single bit.\r
+ *************************************************************************/\r
+ // For Bit-banging with Atomics demo.\r
+ \r
+ while (1){\r
+ atomic_fetch_xor_explicit(&GPIO_REG(GPIO_OUTPUT_VAL), bitbang_mask, memory_order_relaxed);\r
+ }\r
+\r
+ return 0;\r
+\r
+}\r
+\r
+\r
+void trap_entry( void )\r
+{\r
+#warning Dummy until kernel code is incldued.\r
+}\r
--- /dev/null
+adapter_khz 10000\r
+\r
+interface ftdi\r
+ftdi_device_desc "Dual RS232-HS"\r
+ftdi_vid_pid 0x0403 0x6010\r
+\r
+ftdi_layout_init 0x0008 0x001b\r
+ftdi_layout_signal nSRST -oe 0x0020 -data 0x0020\r
+\r
+#Reset Stretcher logic on FE310 is ~1 second long\r
+#This doesn't apply if you use\r
+# ftdi_set_signal, but still good to document\r
+#adapter_nsrst_delay 1500\r
+\r
+set _CHIPNAME riscv\r
+jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913\r
+\r
+set _TARGETNAME $_CHIPNAME.cpu\r
+target create $_TARGETNAME riscv -chain-position $_TARGETNAME\r
+$_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1\r
+\r
+flash bank onboard_spi_flash fespi 0x20000000 0 0 0 $_TARGETNAME\r
+init\r
+#reset -- This type of reset is not implemented yet\r
+if {[ info exists pulse_srst]} {\r
+ ftdi_set_signal nSRST 0\r
+ ftdi_set_signal nSRST z\r
+ #Wait for the reset stretcher\r
+ #It will work without this, but\r
+ #will incur lots of delays for later commands.\r
+ sleep 1500\r
+} \r
+halt\r
+flash protect 0 64 last off\r
projects / freertos / commitdiff