}\r
else\r
{\r
- printf( "FAILED! Error code: %u\r\n", result );\r
+ printf( "FAILED! Error code: %u\r\n", ( unsigned int ) result );\r
all_tests_passed = 0u;\r
}\r
\r
***************************************************************************\r
\r
\r
- http://www.FreeRTOS.org - Documentation, books, training, latest versions, \r
+ http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
license and Real Time Engineers Ltd. contact details.\r
\r
http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
including FreeRTOS+Trace - an indispensable productivity tool, and our new\r
fully thread aware and reentrant UDP/IP stack.\r
\r
- http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High \r
- Integrity Systems, who sell the code with commercial support, \r
+ http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
+ Integrity Systems, who sell the code with commercial support,\r
indemnification and middleware, under the OpenRTOS brand.\r
- \r
- http://www.SafeRTOS.com - High Integrity Systems also provide a safety \r
- engineered and independently SIL3 certified version for use in safety and \r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
mission critical applications that require provable dependability.\r
*/\r
\r
#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )\r
#define portYIELD() vPortYield()\r
#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT\r
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )\r
/*-----------------------------------------------------------*/\r
\r
\r
***************************************************************************\r
\r
\r
- http://www.FreeRTOS.org - Documentation, books, training, latest versions, \r
+ http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
license and Real Time Engineers Ltd. contact details.\r
\r
http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
including FreeRTOS+Trace - an indispensable productivity tool, and our new\r
fully thread aware and reentrant UDP/IP stack.\r
\r
- http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High \r
- Integrity Systems, who sell the code with commercial support, \r
+ http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
+ Integrity Systems, who sell the code with commercial support,\r
indemnification and middleware, under the OpenRTOS brand.\r
- \r
- http://www.SafeRTOS.com - High Integrity Systems also provide a safety \r
- engineered and independently SIL3 certified version for use in safety and \r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
mission critical applications that require provable dependability.\r
*/\r
\r
#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )\r
#define portYIELD() vPortYield()\r
#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT\r
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )\r
/*-----------------------------------------------------------*/\r
\r
/* Critical section management. */\r
***************************************************************************\r
\r
\r
- http://www.FreeRTOS.org - Documentation, books, training, latest versions, \r
+ http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
license and Real Time Engineers Ltd. contact details.\r
\r
http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
including FreeRTOS+Trace - an indispensable productivity tool, and our new\r
fully thread aware and reentrant UDP/IP stack.\r
\r
- http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High \r
- Integrity Systems, who sell the code with commercial support, \r
+ http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
+ Integrity Systems, who sell the code with commercial support,\r
indemnification and middleware, under the OpenRTOS brand.\r
- \r
- http://www.SafeRTOS.com - High Integrity Systems also provide a safety \r
- engineered and independently SIL3 certified version for use in safety and \r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
mission critical applications that require provable dependability.\r
*/\r
\r
#define portNVIC_INT_CTRL ( ( volatile unsigned portLONG *) 0xe000ed04 )\r
#define portNVIC_PENDSVSET 0x10000000\r
#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) *(portNVIC_INT_CTRL) = portNVIC_PENDSVSET\r
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )\r
/*-----------------------------------------------------------*/\r
\r
\r
\r
/*\r
* Set basepri back to 0 without effective other registers.\r
- * r0 is clobbered. FAQ: Setting BASEPRI to 0 is not a bug. Please see \r
+ * r0 is clobbered. FAQ: Setting BASEPRI to 0 is not a bug. Please see\r
* http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html before disagreeing.\r
*/\r
#define portCLEAR_INTERRUPT_MASK() \\r
:::"r0" \\r
)\r
\r
-/* FAQ: Setting BASEPRI to 0 is not a bug. Please see \r
+/* FAQ: Setting BASEPRI to 0 is not a bug. Please see\r
http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html before disagreeing. */\r
#define portSET_INTERRUPT_MASK_FROM_ISR() 0;portSET_INTERRUPT_MASK()\r
#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) portCLEAR_INTERRUPT_MASK();(void)x\r
\r
#define portNOP()\r
\r
-/* There are an uneven number of items on the initial stack, so \r
+/* There are an uneven number of items on the initial stack, so\r
portALIGNMENT_ASSERT_pxCurrentTCB() will trigger false positive asserts. */\r
#define portALIGNMENT_ASSERT_pxCurrentTCB ( void )\r
\r
#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )\r
#define portYIELD() vPortYield()\r
#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT\r
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )\r
/*-----------------------------------------------------------*/\r
\r
/* Critical section management. */\r
***************************************************************************\r
\r
\r
- http://www.FreeRTOS.org - Documentation, books, training, latest versions, \r
+ http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
license and Real Time Engineers Ltd. contact details.\r
\r
http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
including FreeRTOS+Trace - an indispensable productivity tool, and our new\r
fully thread aware and reentrant UDP/IP stack.\r
\r
- http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High \r
- Integrity Systems, who sell the code with commercial support, \r
+ http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
+ Integrity Systems, who sell the code with commercial support,\r
indemnification and middleware, under the OpenRTOS brand.\r
- \r
- http://www.SafeRTOS.com - High Integrity Systems also provide a safety \r
- engineered and independently SIL3 certified version for use in safety and \r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
mission critical applications that require provable dependability.\r
*/\r
\r
typedef unsigned portLONG portTickType;\r
#define portMAX_DELAY ( portTickType ) 0xffffffff\r
#endif\r
-/*-----------------------------------------------------------*/ \r
+/*-----------------------------------------------------------*/\r
\r
/* Architecture specifics. */\r
#define portSTACK_GROWTH ( -1 )\r
-#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ ) \r
+#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ )\r
#define portBYTE_ALIGNMENT 8\r
-/*-----------------------------------------------------------*/ \r
+/*-----------------------------------------------------------*/\r
\r
\r
/* Scheduler utilities. */\r
#define portNVIC_PENDSVSET 0x10000000\r
#define portYIELD() vPortYield()\r
#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) *(portNVIC_INT_CTRL) = portNVIC_PENDSVSET\r
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )\r
/*-----------------------------------------------------------*/\r
\r
\r
***************************************************************************\r
\r
\r
- http://www.FreeRTOS.org - Documentation, books, training, latest versions, \r
+ http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
license and Real Time Engineers Ltd. contact details.\r
\r
http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
including FreeRTOS+Trace - an indispensable productivity tool, and our new\r
fully thread aware and reentrant UDP/IP stack.\r
\r
- http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High \r
- Integrity Systems, who sell the code with commercial support, \r
+ http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
+ Integrity Systems, who sell the code with commercial support,\r
indemnification and middleware, under the OpenRTOS brand.\r
- \r
- http://www.SafeRTOS.com - High Integrity Systems also provide a safety \r
- engineered and independently SIL3 certified version for use in safety and \r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
mission critical applications that require provable dependability.\r
*/\r
\r
typedef unsigned portLONG portTickType;\r
#define portMAX_DELAY ( portTickType ) 0xffffffff\r
#endif\r
-/*-----------------------------------------------------------*/ \r
+/*-----------------------------------------------------------*/\r
\r
/* Architecture specifics. */\r
#define portSTACK_GROWTH ( -1 )\r
-#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ ) \r
+#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ )\r
#define portBYTE_ALIGNMENT 8\r
-/*-----------------------------------------------------------*/ \r
+/*-----------------------------------------------------------*/\r
\r
/* Scheduler utilities. */\r
extern void vPortYield( void );\r
#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )\r
#define portYIELD() vPortYield()\r
#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT\r
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )\r
/*-----------------------------------------------------------*/\r
\r
/* Architecture specific optimisations. */\r
***************************************************************************\r
\r
\r
- http://www.FreeRTOS.org - Documentation, books, training, latest versions, \r
+ http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
license and Real Time Engineers Ltd. contact details.\r
\r
http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
including FreeRTOS+Trace - an indispensable productivity tool, and our new\r
fully thread aware and reentrant UDP/IP stack.\r
\r
- http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High \r
- Integrity Systems, who sell the code with commercial support, \r
+ http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
+ Integrity Systems, who sell the code with commercial support,\r
indemnification and middleware, under the OpenRTOS brand.\r
- \r
- http://www.SafeRTOS.com - High Integrity Systems also provide a safety \r
- engineered and independently SIL3 certified version for use in safety and \r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
mission critical applications that require provable dependability.\r
*/\r
\r
typedef unsigned portLONG portTickType;\r
#define portMAX_DELAY ( portTickType ) 0xffffffff\r
#endif\r
-/*-----------------------------------------------------------*/ \r
+/*-----------------------------------------------------------*/\r
\r
/* Architecture specifics. */\r
#define portSTACK_GROWTH ( -1 )\r
-#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ ) \r
+#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ )\r
#define portBYTE_ALIGNMENT 8\r
-/*-----------------------------------------------------------*/ \r
+/*-----------------------------------------------------------*/\r
\r
/* Scheduler utilities. */\r
extern void vPortYield( void );\r
#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )\r
#define portYIELD() vPortYield()\r
#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT\r
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )\r
/*-----------------------------------------------------------*/\r
\r
/* Architecture specific optimisations. */\r
#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vPortClearInterruptMask( x )\r
/*-----------------------------------------------------------*/\r
\r
-/* There are an uneven number of items on the initial stack, so \r
+/* There are an uneven number of items on the initial stack, so\r
portALIGNMENT_ASSERT_pxCurrentTCB() will trigger false positive asserts. */\r
#define portALIGNMENT_ASSERT_pxCurrentTCB ( void )\r
/*-----------------------------------------------------------*/\r
portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters )\r
{\r
xThreadState *pxThreadState = NULL;\r
+char *pcTopOfStack = ( char * ) pxTopOfStack;\r
\r
/* In this simulated case a stack is not initialised, but instead a thread\r
is created that will execute the task being created. The thread handles\r
the stack that was created for the task - so the stack buffer is still\r
used, just not in the conventional way. It will not be used for anything\r
other than holding this structure. */\r
- pxThreadState = ( xThreadState * ) ( pxTopOfStack - sizeof( xThreadState ) );\r
+ pxThreadState = ( xThreadState * ) ( pcTopOfStack - sizeof( xThreadState ) );\r
\r
/* Create the thread itself. */\r
pxThreadState->pvThread = CreateThread( NULL, 0, ( LPTHREAD_START_ROUTINE ) pxCode, pvParameters, CREATE_SUSPENDED, NULL );\r
\r
void vPortGenerateSimulatedInterrupt( unsigned long ulInterruptNumber )\r
{\r
-xThreadState *pxThreadState;\r
-\r
if( ( ulInterruptNumber < portMAX_INTERRUPTS ) && ( pvInterruptEventMutex != NULL ) )\r
{\r
/* Yield interrupts are processed even when critical nesting is non-zero. */\r
be in a critical section as calls to wait for mutexes are accumulative. */\r
if( ulCriticalNesting == 0 )\r
{\r
- /* The event handler needs to know to signal the interrupt acknowledge event\r
- the next time this task runs. */\r
- pxThreadState = ( xThreadState * ) *( ( unsigned long * ) pxCurrentTCB );\r
SetEvent( pvInterruptEvent ); \r
}\r
\r
\r
void vPortExitCritical( void )\r
{\r
-xThreadState *pxThreadState;\r
long lMutexNeedsReleasing;\r
\r
/* The interrupt event mutex should already be held by this thread as it was\r
{\r
SetEvent( pvInterruptEvent );\r
\r
- /* The event handler needs to know to signal the interrupt \r
- acknowledge event the next time this task runs. */\r
- pxThreadState = ( xThreadState * ) *( ( unsigned long * ) pxCurrentTCB );\r
-\r
/* Mutex will be released now, so does not require releasing\r
on function exit. */\r
lMutexNeedsReleasing = pdFALSE;\r
#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )\r
#define portYIELD() vPortYield()\r
#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT\r
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )\r
/*-----------------------------------------------------------*/\r
\r
/* Critical section management. */\r
***************************************************************************\r
\r
\r
- http://www.FreeRTOS.org - Documentation, books, training, latest versions, \r
+ http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
license and Real Time Engineers Ltd. contact details.\r
\r
http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
including FreeRTOS+Trace - an indispensable productivity tool, and our new\r
fully thread aware and reentrant UDP/IP stack.\r
\r
- http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High \r
- Integrity Systems, who sell the code with commercial support, \r
+ http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
+ Integrity Systems, who sell the code with commercial support,\r
indemnification and middleware, under the OpenRTOS brand.\r
- \r
- http://www.SafeRTOS.com - High Integrity Systems also provide a safety \r
- engineered and independently SIL3 certified version for use in safety and \r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
mission critical applications that require provable dependability.\r
*/\r
\r
#endif\r
\r
/*-----------------------------------------------------------\r
- * Port specific definitions. \r
+ * Port specific definitions.\r
*\r
* The settings in this file configure FreeRTOS correctly for the\r
* given hardware and compiler.\r
typedef unsigned portLONG portTickType;\r
#define portMAX_DELAY ( portTickType ) 0xffffffff\r
#endif\r
-/*-----------------------------------------------------------*/ \r
+/*-----------------------------------------------------------*/\r
\r
/* Architecture specifics. */\r
#define portSTACK_GROWTH ( -1 )\r
-#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ ) \r
+#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ )\r
#define portBYTE_ALIGNMENT 8\r
-/*-----------------------------------------------------------*/ \r
+/*-----------------------------------------------------------*/\r
\r
/* Scheduler utilities. */\r
extern void vPortYield( void );\r
#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )\r
#define portYIELD() vPortYield()\r
#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT\r
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )\r
/*-----------------------------------------------------------*/\r
\r
/* Critical section management. */\r
\r
/*-----------------------------------------------------------*/\r
\r
-/* There are an uneven number of items on the initial stack, so \r
+/* There are an uneven number of items on the initial stack, so\r
portALIGNMENT_ASSERT_pxCurrentTCB() will trigger false positive asserts. */\r
#define portALIGNMENT_ASSERT_pxCurrentTCB ( void )\r
/*-----------------------------------------------------------*/\r
#define portYIELD() vPortYield()\r
\r
#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) *(portNVIC_INT_CTRL) = portNVIC_PENDSVSET\r
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )\r
/*-----------------------------------------------------------*/\r
\r
\r