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--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>\r
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+ <name>RTOSDemo</name>\r
+ <comment></comment>\r
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+ <value>false</value>\r
+ </dictionary>\r
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+ </buildCommand>\r
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+ <name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>\r
+ <arguments>\r
+ </arguments>\r
+ </buildCommand>\r
+ </buildSpec>\r
+ <natures>\r
+ <nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>\r
+ <nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>\r
+ <nature>org.eclipse.cdt.core.cnature</nature>\r
+ </natures>\r
+ <linkedResources>\r
+ <link>\r
+ <name>Demo_Source</name>\r
+ <type>2</type>\r
+ <locationURI>FREERTOS_ROOT/Demo/Common</locationURI>\r
+ </link>\r
+ <link>\r
+ <name>FreeRTOS_Source</name>\r
+ <type>2</type>\r
+ <locationURI>FREERTOS_ROOT/Source</locationURI>\r
+ </link>\r
+ </linkedResources>\r
+</projectDescription>\r
--- /dev/null
+/*\r
+ FreeRTOS.org V5.0.3 - Copyright (C) 2003-2008 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS.org distribution.\r
+\r
+ FreeRTOS.org is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS.org is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS.org; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS.org, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section\r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ ***************************************************************************\r
+ * *\r
+ * SAVE TIME AND MONEY! We can port FreeRTOS.org to your own hardware, *\r
+ * and even write all or part of your application on your behalf. *\r
+ * See http://www.OpenRTOS.com for details of the services we provide to *\r
+ * expedite your project. *\r
+ * *\r
+ ***************************************************************************\r
+ ***************************************************************************\r
+\r
+ Please ensure to read the configuration and relevant port sections of the\r
+ online documentation.\r
+\r
+ http://www.FreeRTOS.org - Documentation, latest information, license and\r
+ contact details.\r
+\r
+ http://www.SafeRTOS.com - A version that is certified for use in safety\r
+ critical systems.\r
+\r
+ http://www.OpenRTOS.com - Commercial support, development, porting,\r
+ licensing and training services.\r
+*/\r
+\r
+#ifndef FREERTOS_CONFIG_H\r
+#define FREERTOS_CONFIG_H\r
+\r
+#include "MCF5282.h"\r
+\r
+/*-----------------------------------------------------------\r
+ * Application specific definitions.\r
+ *\r
+ * These definitions should be adjusted for your particular hardware and\r
+ * application requirements.\r
+ *\r
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE\r
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.\r
+ *----------------------------------------------------------*/\r
+\r
+#define configUSE_PREEMPTION 1\r
+#define configUSE_IDLE_HOOK 0\r
+#define configUSE_TICK_HOOK 0\r
+#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 25000000 )\r
+#define configTICK_RATE_HZ ( ( portTickType ) 1000 )\r
+#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 60 )\r
+#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 24000 ) )\r
+#define configMAX_TASK_NAME_LEN ( 12 )\r
+#define configUSE_TRACE_FACILITY 1\r
+#define configUSE_16_BIT_TICKS 0\r
+#define configIDLE_SHOULD_YIELD 0\r
+#define configUSE_CO_ROUTINES 0\r
+#define configUSE_MUTEXES 1\r
+#define configCHECK_FOR_STACK_OVERFLOW 2\r
+#define configUSE_RECURSIVE_MUTEXES 1\r
+#define configQUEUE_REGISTRY_SIZE 10\r
+\r
+#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 5 )\r
+#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )\r
+\r
+/* Set the following definitions to 1 to include the API function, or zero\r
+to exclude the API function. */\r
+\r
+#define INCLUDE_vTaskPrioritySet 1\r
+#define INCLUDE_uxTaskPriorityGet 1\r
+#define INCLUDE_vTaskDelete 1\r
+#define INCLUDE_vTaskCleanUpResources 0\r
+#define INCLUDE_vTaskSuspend 1\r
+#define INCLUDE_vTaskDelayUntil 1\r
+#define INCLUDE_vTaskDelay 1\r
+#define INCLUDE_uxTaskGetStackHighWaterMark 1\r
+\r
+\r
+\r
+#define configKERNEL_INTERRUPT_PRIORITY 1\r
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY 191 /* equivalent to 0xa0, or priority 5. */\r
+\r
+\r
+#endif /* FREERTOS_CONFIG_H */\r
--- /dev/null
+/*\r
+ FreeRTOS.org V5.0.3 - Copyright (C) 2003-2008 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS.org distribution.\r
+\r
+ FreeRTOS.org is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS.org is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS.org; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS.org, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section\r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ ***************************************************************************\r
+ * *\r
+ * SAVE TIME AND MONEY! We can port FreeRTOS.org to your own hardware, *\r
+ * and even write all or part of your application on your behalf. *\r
+ * See http://www.OpenRTOS.com for details of the services we provide to *\r
+ * expedite your project. *\r
+ * *\r
+ ***************************************************************************\r
+ ***************************************************************************\r
+\r
+ Please ensure to read the configuration and relevant port sections of the\r
+ online documentation.\r
+\r
+ http://www.FreeRTOS.org - Documentation, latest information, license and\r
+ contact details.\r
+\r
+ http://www.SafeRTOS.com - A version that is certified for use in safety\r
+ critical systems.\r
+\r
+ http://www.OpenRTOS.com - Commercial support, development, porting,\r
+ licensing and training services.\r
+*/\r
+\r
+#include "FreeRTOS.h"\r
+\r
+#define portPRESCALE_VALUE 64\r
+#define portPRESCALE_REG_SETTING ( 5 << 8 )\r
+#define portPIT_INTERRUPT_ENABLED ( 0x08 )\r
+#define configPIT0_INTERRUPT_VECTOR ( 55 )\r
+\r
+static void vApplicationSetupInterrupts( void )\r
+{\r
+const unsigned portSHORT usCompareMatchValue = ( ( configCPU_CLOCK_HZ / portPRESCALE_VALUE ) / configTICK_RATE_HZ );\r
+\r
+ /* Configure interrupt priority and level and unmask interrupt. */\r
+ MCF_INTC0_ICR55 = ( configKERNEL_INTERRUPT_PRIORITY | ( 1 << 3 ) );\r
+ MCF_INTC0_IMRH &= ~( MCF_INTC_IMRH_INT_MASK55 );\r
+\r
+ MCF_INTC0_ICR63 = ( configKERNEL_INTERRUPT_PRIORITY | ( 1 << 3 ) );\r
+ MCF_INTC0_IMRH &= ~( MCF_INTC_IMRH_INT_MASK63 );\r
+\r
+ MCF_PIT0_PCSR |= MCF_PIT_PCSR_PIF;\r
+ MCF_PIT0_PCSR = ( portPRESCALE_REG_SETTING | MCF_PIT_PCSR_PIE | MCF_PIT_PCSR_RLD | MCF_PIT_PCSR_EN );\r
+ MCF_PIT0_PMR = usCompareMatchValue;\r
+}\r
+\r
+void __attribute__ ((interrupt)) __cs3_isr_interrupt_127(void)\r
+{\r
+ MCF_INTC0_INTFRCH &= ~( 1UL << 31UL );\r
+}\r
+\r
+void __attribute__ ((interrupt)) __cs3_isr_interrupt_119(void)\r
+{\r
+ MCF_PIT0_PCSR |= MCF_PIT_PCSR_PIF;\r
+ MCF_INTC0_INTFRCH |= ( 1UL << 31UL );\r
+}\r
--- /dev/null
+/* Coldfire C Header File\r
+ * Copyright Freescale Semiconductor Inc\r
+ * All rights reserved.\r
+ *\r
+ * 2007/03/19 Revision: 0.9\r
+ */\r
+\r
+#ifndef __MCF5282_H__\r
+#define __MCF5282_H__\r
+\r
+\r
+/********************************************************************/\r
+/*\r
+ * The basic data types\r
+ */\r
+\r
+typedef unsigned char uint8; /* 8 bits */\r
+typedef unsigned short int uint16; /* 16 bits */\r
+typedef unsigned long int uint32; /* 32 bits */\r
+\r
+typedef signed char int8; /* 8 bits */\r
+typedef signed short int int16; /* 16 bits */\r
+typedef signed long int int32; /* 32 bits */\r
+\r
+typedef volatile uint8 vuint8; /* 8 bits */\r
+typedef volatile uint16 vuint16; /* 16 bits */\r
+typedef volatile uint32 vuint32; /* 32 bits */\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+#if 0\r
+#pragma define_section system ".system" far_absolute RW\r
+\r
+/***\r
+ * MCF5282 Derivative Memory map definitions from linker command files:\r
+ * __IPSBAR, __FLASHBAR, __FLASHBAR_SIZE, __RAMBAR, __RAMBAR_SIZE\r
+ * linker symbols must be defined in the linker command file.\r
+ */\r
+\r
+extern __declspec(system) uint8 __IPSBAR[];\r
+extern __declspec(system) uint8 __FLASHBAR[];\r
+extern __declspec(system) uint8 __FLASHBAR_SIZE[];\r
+extern __declspec(system) uint8 __RAMBAR[];\r
+extern __declspec(system) uint8 __RAMBAR_SIZE[];\r
+#endif\r
+\r
+#define __IPSBAR ((uint8*)0x40000000)\r
+\r
+#define IPSBAR_ADDRESS (uint32)__IPSBAR\r
+#define FLASHBAR_ADDRESS (uint32)__FLASHBAR\r
+#define FLASHBAR_SIZE (uint32)__FLASHBAR_SIZE\r
+#define RAMBAR_ADDRESS (uint32)__RAMBAR\r
+#define RAMBAR_SIZE (uint32)__RAMBAR_SIZE\r
+\r
+\r
+#include "MCF5282_SCM.h"\r
+#include "MCF5282_SDRAMC.h"\r
+#include "MCF5282_CS.h"\r
+#include "MCF5282_DMA.h"\r
+#include "MCF5282_UART.h"\r
+#include "MCF5282_I2C.h"\r
+#include "MCF5282_QSPI.h"\r
+#include "MCF5282_DTIM.h"\r
+#include "MCF5282_INTC.h"\r
+#include "MCF5282_GIACR.h"\r
+#include "MCF5282_FEC.h"\r
+#include "MCF5282_GPIO.h"\r
+#include "MCF5282_PAD.h"\r
+#include "MCF5282_RCM.h"\r
+#include "MCF5282_PMM.h"\r
+#include "MCF5282_CCM.h"\r
+#include "MCF5282_CLOCK.h"\r
+#include "MCF5282_EPORT.h"\r
+#include "MCF5282_WTM.h"\r
+#include "MCF5282_PIT.h"\r
+#include "MCF5282_QADC.h"\r
+#include "MCF5282_GPTA.h"\r
+#include "MCF5282_GPTB.h"\r
+#include "MCF5282_FlexCAN.h"\r
+#include "MCF5282_CFM.h"\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+\r
+#endif /* __MCF5282_H__ */\r
--- /dev/null
+/* Coldfire C Header File\r
+ * Copyright Freescale Semiconductor Inc\r
+ * All rights reserved.\r
+ *\r
+ * 2007/03/19 Revision: 0.9\r
+ */\r
+\r
+#ifndef __MCF5282_CCM_H__\r
+#define __MCF5282_CCM_H__\r
+\r
+\r
+/*********************************************************************\r
+*\r
+* Chip Configuration Module (CCM)\r
+*\r
+*********************************************************************/\r
+\r
+/* Register read/write macros */\r
+#define MCF_CCM_CCR (*(vuint16*)(&__IPSBAR[0x110004]))\r
+#define MCF_CCM_RCON (*(vuint16*)(&__IPSBAR[0x110008]))\r
+#define MCF_CCM_CIR (*(vuint16*)(&__IPSBAR[0x11000A]))\r
+\r
+\r
+/* Bit definitions and macros for MCF_CCM_CCR */\r
+#define MCF_CCM_CCR_BMT(x) (((x)&0x7)<<0)\r
+#define MCF_CCM_CCR_BMT_65536 (0)\r
+#define MCF_CCM_CCR_BMT_32768 (0x1)\r
+#define MCF_CCM_CCR_BMT_16384 (0x2)\r
+#define MCF_CCM_CCR_BMT_8192 (0x3)\r
+#define MCF_CCM_CCR_BMT_4096 (0x4)\r
+#define MCF_CCM_CCR_BMT_2048 (0x5)\r
+#define MCF_CCM_CCR_BMT_1024 (0x6)\r
+#define MCF_CCM_CCR_BMT_512 (0x7)\r
+#define MCF_CCM_CCR_BME (0x8)\r
+#define MCF_CCM_CCR_PSTEN (0x20)\r
+#define MCF_CCM_CCR_SZEN (0x40)\r
+#define MCF_CCM_CCR_MODE(x) (((x)&0x7)<<0x8)\r
+#define MCF_CCM_CCR_LOAD (0x8000)\r
+\r
+/* Bit definitions and macros for MCF_CCM_RCON */\r
+#define MCF_CCM_RCON_MODE (0x1)\r
+#define MCF_CCM_RCON_BOOTSEL (0x4)\r
+#define MCF_CCM_RCON_BOOTPS(x) (((x)&0x3)<<0x3)\r
+#define MCF_CCM_RCON_RLOAD (0x20)\r
+#define MCF_CCM_RCON_RPLLREF (0x40)\r
+#define MCF_CCM_RCON_RPLLSEL (0x80)\r
+#define MCF_CCM_RCON_RCSC(x) (((x)&0x3)<<0x8)\r
+\r
+/* Bit definitions and macros for MCF_CCM_CIR */\r
+#define MCF_CCM_CIR_PRN(x) (((x)&0xFF)<<0)\r
+#define MCF_CCM_CIR_PIN(x) (((x)&0xFF)<<0x8)\r
+\r
+\r
+#endif /* __MCF5282_CCM_H__ */\r
--- /dev/null
+/* Coldfire C Header File\r
+ * Copyright Freescale Semiconductor Inc\r
+ * All rights reserved.\r
+ *\r
+ * 2007/03/19 Revision: 0.9\r
+ */\r
+\r
+#ifndef __MCF5282_CFM_H__\r
+#define __MCF5282_CFM_H__\r
+\r
+\r
+/*********************************************************************\r
+*\r
+* ColdFire Flash Module (CFM)\r
+*\r
+*********************************************************************/\r
+\r
+/* Register read/write macros */\r
+#define MCF_CFM_CFMMCR (*(vuint16*)(&__IPSBAR[0x1D0000]))\r
+#define MCF_CFM_CFMCLKD (*(vuint8 *)(&__IPSBAR[0x1D0002]))\r
+#define MCF_CFM_CFMSEC (*(vuint32*)(&__IPSBAR[0x1D0008]))\r
+#define MCF_CFM_CFMPROT (*(vuint32*)(&__IPSBAR[0x1D0010]))\r
+#define MCF_CFM_CFMSACC (*(vuint32*)(&__IPSBAR[0x1D0014]))\r
+#define MCF_CFM_CFMDACC (*(vuint32*)(&__IPSBAR[0x1D0018]))\r
+#define MCF_CFM_CFMUSTAT (*(vuint8 *)(&__IPSBAR[0x1D0020]))\r
+#define MCF_CFM_CFMCMD (*(vuint8 *)(&__IPSBAR[0x1D0024]))\r
+\r
+\r
+/* Bit definitions and macros for MCF_CFM_CFMMCR */\r
+#define MCF_CFM_CFMMCR_KEYACC (0x20)\r
+#define MCF_CFM_CFMMCR_CCIE (0x40)\r
+#define MCF_CFM_CFMMCR_CBEIE (0x80)\r
+#define MCF_CFM_CFMMCR_AEIE (0x100)\r
+#define MCF_CFM_CFMMCR_PVIE (0x200)\r
+#define MCF_CFM_CFMMCR_LOCK (0x400)\r
+\r
+/* Bit definitions and macros for MCF_CFM_CFMCLKD */\r
+#define MCF_CFM_CFMCLKD_DIV(x) (((x)&0x3F)<<0)\r
+#define MCF_CFM_CFMCLKD_PRDIV8 (0x40)\r
+#define MCF_CFM_CFMCLKD_DIVLD (0x80)\r
+\r
+/* Bit definitions and macros for MCF_CFM_CFMSEC */\r
+#define MCF_CFM_CFMSEC_SEC(x) (((x)&0xFFFF)<<0)\r
+#define MCF_CFM_CFMSEC_SECSTAT (0x40000000)\r
+#define MCF_CFM_CFMSEC_KEYEN (0x80000000)\r
+\r
+/* Bit definitions and macros for MCF_CFM_CFMPROT */\r
+#define MCF_CFM_CFMPROT_PROT(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_CFM_CFMSACC */\r
+#define MCF_CFM_CFMSACC_SUPV(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_CFM_CFMDACC */\r
+#define MCF_CFM_CFMDACC_DATA(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_CFM_CFMUSTAT */\r
+#define MCF_CFM_CFMUSTAT_BLANK (0x4)\r
+#define MCF_CFM_CFMUSTAT_ACCERR (0x10)\r
+#define MCF_CFM_CFMUSTAT_PVIOL (0x20)\r
+#define MCF_CFM_CFMUSTAT_CCIF (0x40)\r
+#define MCF_CFM_CFMUSTAT_CBEIF (0x80)\r
+\r
+/* Bit definitions and macros for MCF_CFM_CFMCMD */\r
+#define MCF_CFM_CFMCMD_CMD(x) (((x)&0x7F)<<0)\r
+#define MCF_CFM_CFMCMD_BLANK_CHECK (0x5)\r
+#define MCF_CFM_CFMCMD_PAGE_ERASE_VERIFY (0x6)\r
+#define MCF_CFM_CFMCMD_WORD_PROGRAM (0x20)\r
+#define MCF_CFM_CFMCMD_PAGE_ERASE (0x40)\r
+#define MCF_CFM_CFMCMD_MASS_ERASE (0x41)\r
+\r
+\r
+#endif /* __MCF5282_CFM_H__ */\r
--- /dev/null
+/* Coldfire C Header File\r
+ * Copyright Freescale Semiconductor Inc\r
+ * All rights reserved.\r
+ *\r
+ * 2007/03/19 Revision: 0.9\r
+ */\r
+\r
+#ifndef __MCF5282_CLOCK_H__\r
+#define __MCF5282_CLOCK_H__\r
+\r
+\r
+/*********************************************************************\r
+*\r
+* Clock Module (CLOCK)\r
+*\r
+*********************************************************************/\r
+\r
+/* Register read/write macros */\r
+#define MCF_CLOCK_SYNCR (*(vuint16*)(&__IPSBAR[0x120000]))\r
+#define MCF_CLOCK_SYNSR (*(vuint8 *)(&__IPSBAR[0x120002]))\r
+\r
+\r
+/* Bit definitions and macros for MCF_CLOCK_SYNCR */\r
+#define MCF_CLOCK_SYNCR_STPMD0 (0x4)\r
+#define MCF_CLOCK_SYNCR_STPMD1 (0x8)\r
+#define MCF_CLOCK_SYNCR_FWKUP (0x20)\r
+#define MCF_CLOCK_SYNCR_DISCLK (0x40)\r
+#define MCF_CLOCK_SYNCR_LOCEN (0x80)\r
+#define MCF_CLOCK_SYNCR_RFD(x) (((x)&0x7)<<0x8)\r
+#define MCF_CLOCK_SYNCR_LOCRE (0x800)\r
+#define MCF_CLOCK_SYNCR_MFD(x) (((x)&0x7)<<0xC)\r
+#define MCF_CLOCK_SYNCR_LOLRE (0x8000)\r
+\r
+/* Bit definitions and macros for MCF_CLOCK_SYNSR */\r
+#define MCF_CLOCK_SYNSR_LOCS (0x4)\r
+#define MCF_CLOCK_SYNSR_LOCK (0x8)\r
+#define MCF_CLOCK_SYNSR_LOCKS (0x10)\r
+#define MCF_CLOCK_SYNSR_PLLREF (0x20)\r
+#define MCF_CLOCK_SYNSR_PLLSEL (0x40)\r
+#define MCF_CLOCK_SYNSR_PLLMODE (0x80)\r
+\r
+\r
+#endif /* __MCF5282_CLOCK_H__ */\r
--- /dev/null
+/* Coldfire C Header File\r
+ * Copyright Freescale Semiconductor Inc\r
+ * All rights reserved.\r
+ *\r
+ * 2007/03/19 Revision: 0.9\r
+ */\r
+\r
+#ifndef __MCF5282_CS_H__\r
+#define __MCF5282_CS_H__\r
+\r
+\r
+/*********************************************************************\r
+*\r
+* Chip Select Module (CS)\r
+*\r
+*********************************************************************/\r
+\r
+/* Register read/write macros */\r
+#define MCF_CS0_CSAR (*(vuint16*)(&__IPSBAR[0x80]))\r
+#define MCF_CS0_CSMR (*(vuint32*)(&__IPSBAR[0x84]))\r
+#define MCF_CS0_CSCR (*(vuint16*)(&__IPSBAR[0x8A]))\r
+\r
+#define MCF_CS1_CSAR (*(vuint16*)(&__IPSBAR[0x8C]))\r
+#define MCF_CS1_CSMR (*(vuint32*)(&__IPSBAR[0x90]))\r
+#define MCF_CS1_CSCR (*(vuint16*)(&__IPSBAR[0x96]))\r
+\r
+#define MCF_CS2_CSAR (*(vuint16*)(&__IPSBAR[0x98]))\r
+#define MCF_CS2_CSMR (*(vuint32*)(&__IPSBAR[0x9C]))\r
+#define MCF_CS2_CSCR (*(vuint16*)(&__IPSBAR[0xA2]))\r
+\r
+#define MCF_CS3_CSAR (*(vuint16*)(&__IPSBAR[0xA4]))\r
+#define MCF_CS3_CSMR (*(vuint32*)(&__IPSBAR[0xA8]))\r
+#define MCF_CS3_CSCR (*(vuint16*)(&__IPSBAR[0xAE]))\r
+\r
+#define MCF_CS4_CSAR (*(vuint16*)(&__IPSBAR[0xB0]))\r
+#define MCF_CS4_CSMR (*(vuint32*)(&__IPSBAR[0xB4]))\r
+#define MCF_CS4_CSCR (*(vuint16*)(&__IPSBAR[0xBA]))\r
+\r
+#define MCF_CS5_CSAR (*(vuint16*)(&__IPSBAR[0xBC]))\r
+#define MCF_CS5_CSMR (*(vuint32*)(&__IPSBAR[0xC0]))\r
+#define MCF_CS5_CSCR (*(vuint16*)(&__IPSBAR[0xC6]))\r
+\r
+#define MCF_CS6_CSAR (*(vuint16*)(&__IPSBAR[0xC8]))\r
+#define MCF_CS6_CSMR (*(vuint32*)(&__IPSBAR[0xCC]))\r
+#define MCF_CS6_CSCR (*(vuint16*)(&__IPSBAR[0xD2]))\r
+\r
+#define MCF_CS_CSAR(x) (*(vuint16*)(&__IPSBAR[0x80 + ((x)*0xC)]))\r
+#define MCF_CS_CSMR(x) (*(vuint32*)(&__IPSBAR[0x84 + ((x)*0xC)]))\r
+#define MCF_CS_CSCR(x) (*(vuint16*)(&__IPSBAR[0x8A + ((x)*0xC)]))\r
+\r
+\r
+/* Bit definitions and macros for MCF_CS_CSAR */\r
+#define MCF_CS_CSAR_BA(x) (vuint16)(((x)&0xFFFF0000)>>0x10)\r
+\r
+/* Bit definitions and macros for MCF_CS_CSMR */\r
+#define MCF_CS_CSMR_V (0x1)\r
+#define MCF_CS_CSMR_UD (0x2)\r
+#define MCF_CS_CSMR_UC (0x4)\r
+#define MCF_CS_CSMR_SD (0x8)\r
+#define MCF_CS_CSMR_SC (0x10)\r
+#define MCF_CS_CSMR_CI (0x20)\r
+#define MCF_CS_CSMR_AM (0x40)\r
+#define MCF_CS_CSMR_WP (0x100)\r
+#define MCF_CS_CSMR_BAM(x) (((x)&0xFFFF)<<0x10)\r
+#define MCF_CS_CSMR_BAM_4G (0xFFFF0000)\r
+#define MCF_CS_CSMR_BAM_2G (0x7FFF0000)\r
+#define MCF_CS_CSMR_BAM_1G (0x3FFF0000)\r
+#define MCF_CS_CSMR_BAM_1024M (0x3FFF0000)\r
+#define MCF_CS_CSMR_BAM_512M (0x1FFF0000)\r
+#define MCF_CS_CSMR_BAM_256M (0xFFF0000)\r
+#define MCF_CS_CSMR_BAM_128M (0x7FF0000)\r
+#define MCF_CS_CSMR_BAM_64M (0x3FF0000)\r
+#define MCF_CS_CSMR_BAM_32M (0x1FF0000)\r
+#define MCF_CS_CSMR_BAM_16M (0xFF0000)\r
+#define MCF_CS_CSMR_BAM_8M (0x7F0000)\r
+#define MCF_CS_CSMR_BAM_4M (0x3F0000)\r
+#define MCF_CS_CSMR_BAM_2M (0x1F0000)\r
+#define MCF_CS_CSMR_BAM_1M (0xF0000)\r
+#define MCF_CS_CSMR_BAM_1024K (0xF0000)\r
+#define MCF_CS_CSMR_BAM_512K (0x70000)\r
+#define MCF_CS_CSMR_BAM_256K (0x30000)\r
+#define MCF_CS_CSMR_BAM_128K (0x10000)\r
+#define MCF_CS_CSMR_BAM_64K (0)\r
+\r
+/* Bit definitions and macros for MCF_CS_CSCR */\r
+#define MCF_CS_CSCR_BSTW (0x8)\r
+#define MCF_CS_CSCR_BSTR (0x10)\r
+#define MCF_CS_CSCR_BEM (0x20)\r
+#define MCF_CS_CSCR_PS(x) (((x)&0x3)<<0x6)\r
+#define MCF_CS_CSCR_PS_32 (0)\r
+#define MCF_CS_CSCR_PS_8 (0x40)\r
+#define MCF_CS_CSCR_PS_16 (0x80)\r
+#define MCF_CS_CSCR_AA (0x100)\r
+#define MCF_CS_CSCR_WS(x) (((x)&0xF)<<0xA)\r
+\r
+\r
+#endif /* __MCF5282_CS_H__ */\r
--- /dev/null
+/* Coldfire C Header File\r
+ * Copyright Freescale Semiconductor Inc\r
+ * All rights reserved.\r
+ *\r
+ * 2007/03/19 Revision: 0.9\r
+ */\r
+\r
+#ifndef __MCF5282_DMA_H__\r
+#define __MCF5282_DMA_H__\r
+\r
+\r
+/*********************************************************************\r
+*\r
+* DMA Controller (DMA)\r
+*\r
+*********************************************************************/\r
+\r
+/* Register read/write macros */\r
+#define MCF_DMA0_SAR (*(vuint32*)(&__IPSBAR[0x100]))\r
+#define MCF_DMA0_DAR (*(vuint32*)(&__IPSBAR[0x104]))\r
+#define MCF_DMA0_DCR (*(vuint32*)(&__IPSBAR[0x108]))\r
+#define MCF_DMA0_BCR (*(vuint32*)(&__IPSBAR[0x10C]))\r
+#define MCF_DMA0_DSR (*(vuint8 *)(&__IPSBAR[0x110]))\r
+\r
+#define MCF_DMA1_SAR (*(vuint32*)(&__IPSBAR[0x140]))\r
+#define MCF_DMA1_DAR (*(vuint32*)(&__IPSBAR[0x144]))\r
+#define MCF_DMA1_DCR (*(vuint32*)(&__IPSBAR[0x148]))\r
+#define MCF_DMA1_BCR (*(vuint32*)(&__IPSBAR[0x14C]))\r
+#define MCF_DMA1_DSR (*(vuint8 *)(&__IPSBAR[0x150]))\r
+\r
+#define MCF_DMA2_SAR (*(vuint32*)(&__IPSBAR[0x180]))\r
+#define MCF_DMA2_DAR (*(vuint32*)(&__IPSBAR[0x184]))\r
+#define MCF_DMA2_DCR (*(vuint32*)(&__IPSBAR[0x188]))\r
+#define MCF_DMA2_BCR (*(vuint32*)(&__IPSBAR[0x18C]))\r
+#define MCF_DMA2_DSR (*(vuint8 *)(&__IPSBAR[0x190]))\r
+\r
+#define MCF_DMA3_SAR (*(vuint32*)(&__IPSBAR[0x1C0]))\r
+#define MCF_DMA3_DAR (*(vuint32*)(&__IPSBAR[0x1C4]))\r
+#define MCF_DMA3_DCR (*(vuint32*)(&__IPSBAR[0x1C8]))\r
+#define MCF_DMA3_BCR (*(vuint32*)(&__IPSBAR[0x1CC]))\r
+#define MCF_DMA3_DSR (*(vuint8 *)(&__IPSBAR[0x1D0]))\r
+\r
+#define MCF_DMA_SAR(x) (*(vuint32*)(&__IPSBAR[0x100 + ((x)*0x40)]))\r
+#define MCF_DMA_DAR(x) (*(vuint32*)(&__IPSBAR[0x104 + ((x)*0x40)]))\r
+#define MCF_DMA_DCR(x) (*(vuint32*)(&__IPSBAR[0x108 + ((x)*0x40)]))\r
+#define MCF_DMA_BCR(x) (*(vuint32*)(&__IPSBAR[0x10C + ((x)*0x40)]))\r
+#define MCF_DMA_DSR(x) (*(vuint8 *)(&__IPSBAR[0x110 + ((x)*0x40)]))\r
+\r
+\r
+/* Bit definitions and macros for MCF_DMA_SAR */\r
+#define MCF_DMA_SAR_SAR(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_DMA_DAR */\r
+#define MCF_DMA_DAR_DAR(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_DMA_DCR */\r
+#define MCF_DMA_DCR_AT (0x8000)\r
+#define MCF_DMA_DCR_START (0x10000)\r
+#define MCF_DMA_DCR_DSIZE(x) (((x)&0x3)<<0x11)\r
+#define MCF_DMA_DCR_DSIZE_LONG (0)\r
+#define MCF_DMA_DCR_DSIZE_BYTE (0x1)\r
+#define MCF_DMA_DCR_DSIZE_WORD (0x2)\r
+#define MCF_DMA_DCR_DSIZE_LINE (0x3)\r
+#define MCF_DMA_DCR_DINC (0x80000)\r
+#define MCF_DMA_DCR_SSIZE(x) (((x)&0x3)<<0x14)\r
+#define MCF_DMA_DCR_SSIZE_LONG (0)\r
+#define MCF_DMA_DCR_SSIZE_BYTE (0x1)\r
+#define MCF_DMA_DCR_SSIZE_WORD (0x2)\r
+#define MCF_DMA_DCR_SSIZE_LINE (0x3)\r
+#define MCF_DMA_DCR_SINC (0x400000)\r
+#define MCF_DMA_DCR_BWC(x) (((x)&0x7)<<0x19)\r
+#define MCF_DMA_DCR_AA (0x10000000)\r
+#define MCF_DMA_DCR_CS (0x20000000)\r
+#define MCF_DMA_DCR_EEXT (0x40000000)\r
+#define MCF_DMA_DCR_INT (0x80000000)\r
+#define MCF_DMA_DCR_BWC_DMA (0)\r
+#define MCF_DMA_DCR_BWC_512 (0x2000000)\r
+#define MCF_DMA_DCR_BWC_1024 (0x4000000)\r
+#define MCF_DMA_DCR_BWC_2048 (0x6000000)\r
+#define MCF_DMA_DCR_BWC_4096 (0x8000000)\r
+#define MCF_DMA_DCR_BWC_8192 (0xA000000)\r
+#define MCF_DMA_DCR_BWC_16384 (0xC000000)\r
+#define MCF_DMA_DCR_BWC_32768 (0xE000000)\r
+\r
+/* Bit definitions and macros for MCF_DMA_BCR */\r
+#define MCF_DMA_BCR_BCR(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_DMA_DSR */\r
+#define MCF_DMA_DSR_DONE (0x1)\r
+#define MCF_DMA_DSR_BSY (0x2)\r
+#define MCF_DMA_DSR_REQ (0x4)\r
+#define MCF_DMA_DSR_BED (0x10)\r
+#define MCF_DMA_DSR_BES (0x20)\r
+#define MCF_DMA_DSR_CE (0x40)\r
+\r
+\r
+#endif /* __MCF5282_DMA_H__ */\r
--- /dev/null
+/* Coldfire C Header File\r
+ * Copyright Freescale Semiconductor Inc\r
+ * All rights reserved.\r
+ *\r
+ * 2007/03/19 Revision: 0.9\r
+ */\r
+\r
+#ifndef __MCF5282_DTIM_H__\r
+#define __MCF5282_DTIM_H__\r
+\r
+\r
+/*********************************************************************\r
+*\r
+* DMA Timers (DTIM)\r
+*\r
+*********************************************************************/\r
+\r
+/* Register read/write macros */\r
+#define MCF_DTIM0_DTMR (*(vuint16*)(&__IPSBAR[0x400]))\r
+#define MCF_DTIM0_DTXMR (*(vuint8 *)(&__IPSBAR[0x402]))\r
+#define MCF_DTIM0_DTER (*(vuint8 *)(&__IPSBAR[0x403]))\r
+#define MCF_DTIM0_DTRR (*(vuint32*)(&__IPSBAR[0x404]))\r
+#define MCF_DTIM0_DTCR (*(vuint32*)(&__IPSBAR[0x408]))\r
+#define MCF_DTIM0_DTCN (*(vuint32*)(&__IPSBAR[0x40C]))\r
+\r
+#define MCF_DTIM1_DTMR (*(vuint16*)(&__IPSBAR[0x440]))\r
+#define MCF_DTIM1_DTXMR (*(vuint8 *)(&__IPSBAR[0x442]))\r
+#define MCF_DTIM1_DTER (*(vuint8 *)(&__IPSBAR[0x443]))\r
+#define MCF_DTIM1_DTRR (*(vuint32*)(&__IPSBAR[0x444]))\r
+#define MCF_DTIM1_DTCR (*(vuint32*)(&__IPSBAR[0x448]))\r
+#define MCF_DTIM1_DTCN (*(vuint32*)(&__IPSBAR[0x44C]))\r
+\r
+#define MCF_DTIM2_DTMR (*(vuint16*)(&__IPSBAR[0x480]))\r
+#define MCF_DTIM2_DTXMR (*(vuint8 *)(&__IPSBAR[0x482]))\r
+#define MCF_DTIM2_DTER (*(vuint8 *)(&__IPSBAR[0x483]))\r
+#define MCF_DTIM2_DTRR (*(vuint32*)(&__IPSBAR[0x484]))\r
+#define MCF_DTIM2_DTCR (*(vuint32*)(&__IPSBAR[0x488]))\r
+#define MCF_DTIM2_DTCN (*(vuint32*)(&__IPSBAR[0x48C]))\r
+\r
+#define MCF_DTIM3_DTMR (*(vuint16*)(&__IPSBAR[0x4C0]))\r
+#define MCF_DTIM3_DTXMR (*(vuint8 *)(&__IPSBAR[0x4C2]))\r
+#define MCF_DTIM3_DTER (*(vuint8 *)(&__IPSBAR[0x4C3]))\r
+#define MCF_DTIM3_DTRR (*(vuint32*)(&__IPSBAR[0x4C4]))\r
+#define MCF_DTIM3_DTCR (*(vuint32*)(&__IPSBAR[0x4C8]))\r
+#define MCF_DTIM3_DTCN (*(vuint32*)(&__IPSBAR[0x4CC]))\r
+\r
+#define MCF_DTIM_DTMR(x) (*(vuint16*)(&__IPSBAR[0x400 + ((x)*0x40)]))\r
+#define MCF_DTIM_DTXMR(x) (*(vuint8 *)(&__IPSBAR[0x402 + ((x)*0x40)]))\r
+#define MCF_DTIM_DTER(x) (*(vuint8 *)(&__IPSBAR[0x403 + ((x)*0x40)]))\r
+#define MCF_DTIM_DTRR(x) (*(vuint32*)(&__IPSBAR[0x404 + ((x)*0x40)]))\r
+#define MCF_DTIM_DTCR(x) (*(vuint32*)(&__IPSBAR[0x408 + ((x)*0x40)]))\r
+#define MCF_DTIM_DTCN(x) (*(vuint32*)(&__IPSBAR[0x40C + ((x)*0x40)]))\r
+\r
+\r
+/* Bit definitions and macros for MCF_DTIM_DTMR */\r
+#define MCF_DTIM_DTMR_RST (0x1)\r
+#define MCF_DTIM_DTMR_CLK(x) (((x)&0x3)<<0x1)\r
+#define MCF_DTIM_DTMR_CLK_STOP (0)\r
+#define MCF_DTIM_DTMR_CLK_DIV1 (0x2)\r
+#define MCF_DTIM_DTMR_CLK_DIV16 (0x4)\r
+#define MCF_DTIM_DTMR_CLK_DTIN (0x6)\r
+#define MCF_DTIM_DTMR_FRR (0x8)\r
+#define MCF_DTIM_DTMR_ORRI (0x10)\r
+#define MCF_DTIM_DTMR_OM (0x20)\r
+#define MCF_DTIM_DTMR_CE(x) (((x)&0x3)<<0x6)\r
+#define MCF_DTIM_DTMR_CE_NONE (0)\r
+#define MCF_DTIM_DTMR_CE_RISE (0x40)\r
+#define MCF_DTIM_DTMR_CE_FALL (0x80)\r
+#define MCF_DTIM_DTMR_CE_ANY (0xC0)\r
+#define MCF_DTIM_DTMR_PS(x) (((x)&0xFF)<<0x8)\r
+\r
+/* Bit definitions and macros for MCF_DTIM_DTXMR */\r
+#define MCF_DTIM_DTXMR_MODE16 (0x1)\r
+#define MCF_DTIM_DTXMR_DMAEN (0x80)\r
+\r
+/* Bit definitions and macros for MCF_DTIM_DTER */\r
+#define MCF_DTIM_DTER_CAP (0x1)\r
+#define MCF_DTIM_DTER_REF (0x2)\r
+\r
+/* Bit definitions and macros for MCF_DTIM_DTRR */\r
+#define MCF_DTIM_DTRR_REF(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_DTIM_DTCR */\r
+#define MCF_DTIM_DTCR_CAP(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_DTIM_DTCN */\r
+#define MCF_DTIM_DTCN_CNT(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+\r
+#endif /* __MCF5282_DTIM_H__ */\r
--- /dev/null
+/* Coldfire C Header File\r
+ * Copyright Freescale Semiconductor Inc\r
+ * All rights reserved.\r
+ *\r
+ * 2007/03/19 Revision: 0.9\r
+ */\r
+\r
+#ifndef __MCF5282_EPORT_H__\r
+#define __MCF5282_EPORT_H__\r
+\r
+\r
+/*********************************************************************\r
+*\r
+* Edge Port Module (EPORT)\r
+*\r
+*********************************************************************/\r
+\r
+/* Register read/write macros */\r
+#define MCF_EPORT_EPPAR (*(vuint16*)(&__IPSBAR[0x130000]))\r
+#define MCF_EPORT_EPDDR (*(vuint8 *)(&__IPSBAR[0x130002]))\r
+#define MCF_EPORT_EPIER (*(vuint8 *)(&__IPSBAR[0x130003]))\r
+#define MCF_EPORT_EPDR (*(vuint8 *)(&__IPSBAR[0x130004]))\r
+#define MCF_EPORT_EPPDR (*(vuint8 *)(&__IPSBAR[0x130005]))\r
+#define MCF_EPORT_EPFR (*(vuint8 *)(&__IPSBAR[0x130006]))\r
+\r
+\r
+\r
+/* Bit definitions and macros for MCF_EPORT_EPPAR */\r
+#define MCF_EPORT_EPPAR_EPPA1(x) (((x)&0x3)<<0x2)\r
+#define MCF_EPORT_EPPAR_EPPA1_LEVEL (0)\r
+#define MCF_EPORT_EPPAR_EPPA1_RISING (0x4)\r
+#define MCF_EPORT_EPPAR_EPPA1_FALLING (0x8)\r
+#define MCF_EPORT_EPPAR_EPPA1_BOTH (0xC)\r
+#define MCF_EPORT_EPPAR_EPPA2(x) (((x)&0x3)<<0x4)\r
+#define MCF_EPORT_EPPAR_EPPA2_LEVEL (0)\r
+#define MCF_EPORT_EPPAR_EPPA2_RISING (0x10)\r
+#define MCF_EPORT_EPPAR_EPPA2_FALLING (0x20)\r
+#define MCF_EPORT_EPPAR_EPPA2_BOTH (0x30)\r
+#define MCF_EPORT_EPPAR_EPPA3(x) (((x)&0x3)<<0x6)\r
+#define MCF_EPORT_EPPAR_EPPA3_LEVEL (0)\r
+#define MCF_EPORT_EPPAR_EPPA3_RISING (0x40)\r
+#define MCF_EPORT_EPPAR_EPPA3_FALLING (0x80)\r
+#define MCF_EPORT_EPPAR_EPPA3_BOTH (0xC0)\r
+#define MCF_EPORT_EPPAR_EPPA4(x) (((x)&0x3)<<0x8)\r
+#define MCF_EPORT_EPPAR_EPPA4_LEVEL (0)\r
+#define MCF_EPORT_EPPAR_EPPA4_RISING (0x100)\r
+#define MCF_EPORT_EPPAR_EPPA4_FALLING (0x200)\r
+#define MCF_EPORT_EPPAR_EPPA4_BOTH (0x300)\r
+#define MCF_EPORT_EPPAR_EPPA5(x) (((x)&0x3)<<0xA)\r
+#define MCF_EPORT_EPPAR_EPPA5_LEVEL (0)\r
+#define MCF_EPORT_EPPAR_EPPA5_RISING (0x400)\r
+#define MCF_EPORT_EPPAR_EPPA5_FALLING (0x800)\r
+#define MCF_EPORT_EPPAR_EPPA5_BOTH (0xC00)\r
+#define MCF_EPORT_EPPAR_EPPA6(x) (((x)&0x3)<<0xC)\r
+#define MCF_EPORT_EPPAR_EPPA6_LEVEL (0)\r
+#define MCF_EPORT_EPPAR_EPPA6_RISING (0x1000)\r
+#define MCF_EPORT_EPPAR_EPPA6_FALLING (0x2000)\r
+#define MCF_EPORT_EPPAR_EPPA6_BOTH (0x3000)\r
+#define MCF_EPORT_EPPAR_EPPA7(x) (((x)&0x3)<<0xE)\r
+#define MCF_EPORT_EPPAR_EPPA7_LEVEL (0)\r
+#define MCF_EPORT_EPPAR_EPPA7_RISING (0x4000)\r
+#define MCF_EPORT_EPPAR_EPPA7_FALLING (0x8000)\r
+#define MCF_EPORT_EPPAR_EPPA7_BOTH (0xC000)\r
+#define MCF_EPORT_EPPAR_LEVEL (0)\r
+#define MCF_EPORT_EPPAR_RISING (0x1)\r
+#define MCF_EPORT_EPPAR_FALLING (0x2)\r
+#define MCF_EPORT_EPPAR_BOTH (0x3)\r
+\r
+/* Bit definitions and macros for MCF_EPORT_EPDDR */\r
+#define MCF_EPORT_EPDDR_EPDD1 (0x2)\r
+#define MCF_EPORT_EPDDR_EPDD2 (0x4)\r
+#define MCF_EPORT_EPDDR_EPDD3 (0x8)\r
+#define MCF_EPORT_EPDDR_EPDD4 (0x10)\r
+#define MCF_EPORT_EPDDR_EPDD5 (0x20)\r
+#define MCF_EPORT_EPDDR_EPDD6 (0x40)\r
+#define MCF_EPORT_EPDDR_EPDD7 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_EPORT_EPIER */\r
+#define MCF_EPORT_EPIER_EPIE1 (0x2)\r
+#define MCF_EPORT_EPIER_EPIE2 (0x4)\r
+#define MCF_EPORT_EPIER_EPIE3 (0x8)\r
+#define MCF_EPORT_EPIER_EPIE4 (0x10)\r
+#define MCF_EPORT_EPIER_EPIE5 (0x20)\r
+#define MCF_EPORT_EPIER_EPIE6 (0x40)\r
+#define MCF_EPORT_EPIER_EPIE7 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_EPORT_EPDR */\r
+#define MCF_EPORT_EPDR_EPD1 (0x2)\r
+#define MCF_EPORT_EPDR_EPD2 (0x4)\r
+#define MCF_EPORT_EPDR_EPD3 (0x8)\r
+#define MCF_EPORT_EPDR_EPD4 (0x10)\r
+#define MCF_EPORT_EPDR_EPD5 (0x20)\r
+#define MCF_EPORT_EPDR_EPD6 (0x40)\r
+#define MCF_EPORT_EPDR_EPD7 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_EPORT_EPPDR */\r
+#define MCF_EPORT_EPPDR_EPPD1 (0x2)\r
+#define MCF_EPORT_EPPDR_EPPD2 (0x4)\r
+#define MCF_EPORT_EPPDR_EPPD3 (0x8)\r
+#define MCF_EPORT_EPPDR_EPPD4 (0x10)\r
+#define MCF_EPORT_EPPDR_EPPD5 (0x20)\r
+#define MCF_EPORT_EPPDR_EPPD6 (0x40)\r
+#define MCF_EPORT_EPPDR_EPPD7 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_EPORT_EPFR */\r
+#define MCF_EPORT_EPFR_EPF1 (0x2)\r
+#define MCF_EPORT_EPFR_EPF2 (0x4)\r
+#define MCF_EPORT_EPFR_EPF3 (0x8)\r
+#define MCF_EPORT_EPFR_EPF4 (0x10)\r
+#define MCF_EPORT_EPFR_EPF5 (0x20)\r
+#define MCF_EPORT_EPFR_EPF6 (0x40)\r
+#define MCF_EPORT_EPFR_EPF7 (0x80)\r
+\r
+\r
+#endif /* __MCF5282_EPORT_H__ */\r
--- /dev/null
+/* Coldfire C Header File\r
+ * Copyright Freescale Semiconductor Inc\r
+ * All rights reserved.\r
+ *\r
+ * 2007/03/19 Revision: 0.9\r
+ */\r
+\r
+#ifndef __MCF5282_FEC_H__\r
+#define __MCF5282_FEC_H__\r
+\r
+\r
+/*********************************************************************\r
+*\r
+* Fast Ethernet Controller(FEC)\r
+*\r
+*********************************************************************/\r
+\r
+/* Register read/write macros */\r
+#define MCF_FEC_EIR (*(vuint32*)(&__IPSBAR[0x1004]))\r
+#define MCF_FEC_EIMR (*(vuint32*)(&__IPSBAR[0x1008]))\r
+#define MCF_FEC_RDAR (*(vuint32*)(&__IPSBAR[0x1010]))\r
+#define MCF_FEC_TDAR (*(vuint32*)(&__IPSBAR[0x1014]))\r
+#define MCF_FEC_ECR (*(vuint32*)(&__IPSBAR[0x1024]))\r
+#define MCF_FEC_MMFR (*(vuint32*)(&__IPSBAR[0x1040]))\r
+#define MCF_FEC_MSCR (*(vuint32*)(&__IPSBAR[0x1044]))\r
+#define MCF_FEC_MIBC (*(vuint32*)(&__IPSBAR[0x1064]))\r
+#define MCF_FEC_RCR (*(vuint32*)(&__IPSBAR[0x1084]))\r
+#define MCF_FEC_TCR (*(vuint32*)(&__IPSBAR[0x10C4]))\r
+#define MCF_FEC_PALR (*(vuint32*)(&__IPSBAR[0x10E4]))\r
+#define MCF_FEC_PAUR (*(vuint32*)(&__IPSBAR[0x10E8]))\r
+#define MCF_FEC_OPD (*(vuint32*)(&__IPSBAR[0x10EC]))\r
+#define MCF_FEC_IAUR (*(vuint32*)(&__IPSBAR[0x1118]))\r
+#define MCF_FEC_IALR (*(vuint32*)(&__IPSBAR[0x111C]))\r
+#define MCF_FEC_GAUR (*(vuint32*)(&__IPSBAR[0x1120]))\r
+#define MCF_FEC_GALR (*(vuint32*)(&__IPSBAR[0x1124]))\r
+#define MCF_FEC_TFWR (*(vuint32*)(&__IPSBAR[0x1144]))\r
+#define MCF_FEC_FRBR (*(vuint32*)(&__IPSBAR[0x114C]))\r
+#define MCF_FEC_FRSR (*(vuint32*)(&__IPSBAR[0x1150]))\r
+#define MCF_FEC_ERDSR (*(vuint32*)(&__IPSBAR[0x1180]))\r
+#define MCF_FEC_ETSDR (*(vuint32*)(&__IPSBAR[0x1184]))\r
+#define MCF_FEC_EMRBR (*(vuint32*)(&__IPSBAR[0x1188]))\r
+#define MCF_FEC_RMON_T_DROP (*(vuint32*)(&__IPSBAR[0x1200]))\r
+#define MCF_FEC_RMON_T_PACKETS (*(vuint32*)(&__IPSBAR[0x1204]))\r
+#define MCF_FEC_RMON_T_BC_PKT (*(vuint32*)(&__IPSBAR[0x1208]))\r
+#define MCF_FEC_RMON_T_MC_PKT (*(vuint32*)(&__IPSBAR[0x120C]))\r
+#define MCF_FEC_RMON_T_CRC_ALIGN (*(vuint32*)(&__IPSBAR[0x1210]))\r
+#define MCF_FEC_RMON_T_UNDERSIZE (*(vuint32*)(&__IPSBAR[0x1214]))\r
+#define MCF_FEC_RMON_T_OVERSIZE (*(vuint32*)(&__IPSBAR[0x1218]))\r
+#define MCF_FEC_RMON_T_FRAG (*(vuint32*)(&__IPSBAR[0x121C]))\r
+#define MCF_FEC_RMON_T_JAB (*(vuint32*)(&__IPSBAR[0x1220]))\r
+#define MCF_FEC_RMON_T_COL (*(vuint32*)(&__IPSBAR[0x1224]))\r
+#define MCF_FEC_RMON_T_P64 (*(vuint32*)(&__IPSBAR[0x1228]))\r
+#define MCF_FEC_RMON_T_P65TO127 (*(vuint32*)(&__IPSBAR[0x122C]))\r
+#define MCF_FEC_RMON_T_P128TO255 (*(vuint32*)(&__IPSBAR[0x1230]))\r
+#define MCF_FEC_RMON_T_P256TO511 (*(vuint32*)(&__IPSBAR[0x1234]))\r
+#define MCF_FEC_RMON_T_P512TO1023 (*(vuint32*)(&__IPSBAR[0x1238]))\r
+#define MCF_FEC_RMON_T_P1024TO2047 (*(vuint32*)(&__IPSBAR[0x123C]))\r
+#define MCF_FEC_RMON_T_P_GTE2048 (*(vuint32*)(&__IPSBAR[0x1240]))\r
+#define MCF_FEC_RMON_T_OCTETS (*(vuint32*)(&__IPSBAR[0x1244]))\r
+#define MCF_FEC_IEEE_T_DROP (*(vuint32*)(&__IPSBAR[0x1248]))\r
+#define MCF_FEC_IEEE_T_FRAME_OK (*(vuint32*)(&__IPSBAR[0x124C]))\r
+#define MCF_FEC_IEEE_T_1COL (*(vuint32*)(&__IPSBAR[0x1250]))\r
+#define MCF_FEC_IEEE_T_MCOL (*(vuint32*)(&__IPSBAR[0x1254]))\r
+#define MCF_FEC_IEEE_T_DEF (*(vuint32*)(&__IPSBAR[0x1258]))\r
+#define MCF_FEC_IEEE_T_LCOL (*(vuint32*)(&__IPSBAR[0x125C]))\r
+#define MCF_FEC_IEEE_T_EXCOL (*(vuint32*)(&__IPSBAR[0x1260]))\r
+#define MCF_FEC_IEEE_T_MACERR (*(vuint32*)(&__IPSBAR[0x1264]))\r
+#define MCF_FEC_IEEE_T_CSERR (*(vuint32*)(&__IPSBAR[0x1268]))\r
+#define MCF_FEC_IEEE_T_SQE (*(vuint32*)(&__IPSBAR[0x126C]))\r
+#define MCF_FEC_IEEE_T_FDXFC (*(vuint32*)(&__IPSBAR[0x1270]))\r
+#define MCF_FEC_IEEE_T_OCTETS_OK (*(vuint32*)(&__IPSBAR[0x1274]))\r
+#define MCF_FEC_RMON_R_PACKETS (*(vuint32*)(&__IPSBAR[0x1284]))\r
+#define MCF_FEC_RMON_R_BC_PKT (*(vuint32*)(&__IPSBAR[0x1288]))\r
+#define MCF_FEC_RMON_R_MC_PKT (*(vuint32*)(&__IPSBAR[0x128C]))\r
+#define MCF_FEC_RMON_R_CRC_ALIGN (*(vuint32*)(&__IPSBAR[0x1290]))\r
+#define MCF_FEC_RMON_R_UNDERSIZE (*(vuint32*)(&__IPSBAR[0x1294]))\r
+#define MCF_FEC_RMON_R_OVERSIZE (*(vuint32*)(&__IPSBAR[0x1298]))\r
+#define MCF_FEC_RMON_R_FRAG (*(vuint32*)(&__IPSBAR[0x129C]))\r
+#define MCF_FEC_RMON_R_JAB (*(vuint32*)(&__IPSBAR[0x12A0]))\r
+#define MCF_FEC_RMON_R_RESVD_0 (*(vuint32*)(&__IPSBAR[0x12A4]))\r
+#define MCF_FEC_RMON_R_P64 (*(vuint32*)(&__IPSBAR[0x12A8]))\r
+#define MCF_FEC_RMON_R_P65TO127 (*(vuint32*)(&__IPSBAR[0x12AC]))\r
+#define MCF_FEC_RMON_R_P128TO255 (*(vuint32*)(&__IPSBAR[0x12B0]))\r
+#define MCF_FEC_RMON_R_P256TO511 (*(vuint32*)(&__IPSBAR[0x12B4]))\r
+#define MCF_FEC_RMON_R_P512TO1023 (*(vuint32*)(&__IPSBAR[0x12B8]))\r
+#define MCF_FEC_RMON_R_P1024TO2047 (*(vuint32*)(&__IPSBAR[0x12BC]))\r
+#define MCF_FEC_RMON_R_P_GTE2048 (*(vuint32*)(&__IPSBAR[0x12C0]))\r
+#define MCF_FEC_RMON_R_OCTETS (*(vuint32*)(&__IPSBAR[0x12C4]))\r
+#define MCF_FEC_IEEE_R_DROP (*(vuint32*)(&__IPSBAR[0x12C8]))\r
+#define MCF_FEC_IEEE_R_FRAME_OK (*(vuint32*)(&__IPSBAR[0x12CC]))\r
+#define MCF_FEC_IEEE_R_CRC (*(vuint32*)(&__IPSBAR[0x12D0]))\r
+#define MCF_FEC_IEEE_R_ALIGN (*(vuint32*)(&__IPSBAR[0x12D4]))\r
+#define MCF_FEC_IEEE_R_MACERR (*(vuint32*)(&__IPSBAR[0x12D8]))\r
+#define MCF_FEC_IEEE_R_FDXFC (*(vuint32*)(&__IPSBAR[0x12DC]))\r
+#define MCF_FEC_IEEE_R_OCTETS_OK (*(vuint32*)(&__IPSBAR[0x12E0]))\r
+\r
+\r
+\r
+/* Bit definitions and macros for MCF_FEC_EIR */\r
+#define MCF_FEC_EIR_UN (0x80000)\r
+#define MCF_FEC_EIR_RL (0x100000)\r
+#define MCF_FEC_EIR_LC (0x200000)\r
+#define MCF_FEC_EIR_EBERR (0x400000)\r
+#define MCF_FEC_EIR_MII (0x800000)\r
+#define MCF_FEC_EIR_RXB (0x1000000)\r
+#define MCF_FEC_EIR_RXF (0x2000000)\r
+#define MCF_FEC_EIR_TXB (0x4000000)\r
+#define MCF_FEC_EIR_TXF (0x8000000)\r
+#define MCF_FEC_EIR_GRA (0x10000000)\r
+#define MCF_FEC_EIR_BABT (0x20000000)\r
+#define MCF_FEC_EIR_BABR (0x40000000)\r
+#define MCF_FEC_EIR_HBERR (0x80000000)\r
+#define MCF_FEC_EIR_CLEAR_ALL (0xFFFFFFFF)\r
+\r
+/* Bit definitions and macros for MCF_FEC_EIMR */\r
+#define MCF_FEC_EIMR_UN (0x80000)\r
+#define MCF_FEC_EIMR_RL (0x100000)\r
+#define MCF_FEC_EIMR_LC (0x200000)\r
+#define MCF_FEC_EIMR_EBERR (0x400000)\r
+#define MCF_FEC_EIMR_MII (0x800000)\r
+#define MCF_FEC_EIMR_RXB (0x1000000)\r
+#define MCF_FEC_EIMR_RXF (0x2000000)\r
+#define MCF_FEC_EIMR_TXB (0x4000000)\r
+#define MCF_FEC_EIMR_TXF (0x8000000)\r
+#define MCF_FEC_EIMR_GRA (0x10000000)\r
+#define MCF_FEC_EIMR_BABT (0x20000000)\r
+#define MCF_FEC_EIMR_BABR (0x40000000)\r
+#define MCF_FEC_EIMR_HBERR (0x80000000)\r
+#define MCF_FEC_EIMR_MASK_ALL (0)\r
+#define MCF_FEC_EIMR_UNMASK_ALL (0xFFFFFFFF)\r
+\r
+/* Bit definitions and macros for MCF_FEC_RDAR */\r
+#define MCF_FEC_RDAR_R_DES_ACTIVE (0x1000000)\r
+\r
+/* Bit definitions and macros for MCF_FEC_TDAR */\r
+#define MCF_FEC_TDAR_X_DES_ACTIVE (0x1000000)\r
+\r
+/* Bit definitions and macros for MCF_FEC_ECR */\r
+#define MCF_FEC_ECR_RESET (0x1)\r
+#define MCF_FEC_ECR_ETHER_EN (0x2)\r
+\r
+/* Bit definitions and macros for MCF_FEC_MMFR */\r
+#define MCF_FEC_MMFR_DATA(x) (((x)&0xFFFF)<<0)\r
+#define MCF_FEC_MMFR_TA(x) (((x)&0x3)<<0x10)\r
+#define MCF_FEC_MMFR_TA_10 (0x20000)\r
+#define MCF_FEC_MMFR_RA(x) (((x)&0x1F)<<0x12)\r
+#define MCF_FEC_MMFR_PA(x) (((x)&0x1F)<<0x17)\r
+#define MCF_FEC_MMFR_OP(x) (((x)&0x3)<<0x1C)\r
+#define MCF_FEC_MMFR_OP_READ (0x20000000)\r
+#define MCF_FEC_MMFR_OP_WRITE (0x10000000)\r
+#define MCF_FEC_MMFR_ST(x) (((x)&0x3)<<0x1E)\r
+#define MCF_FEC_MMFR_ST_01 (0x40000000)\r
+\r
+/* Bit definitions and macros for MCF_FEC_MSCR */\r
+#define MCF_FEC_MSCR_MII_SPEED(x) (((x)&0x3F)<<0x1)\r
+#define MCF_FEC_MSCR_DIS_PREAMBLE (0x80)\r
+\r
+/* Bit definitions and macros for MCF_FEC_MIBC */\r
+#define MCF_FEC_MIBC_MIB_IDLE (0x40000000)\r
+#define MCF_FEC_MIBC_MIB_DISABLE (0x80000000)\r
+\r
+/* Bit definitions and macros for MCF_FEC_RCR */\r
+#define MCF_FEC_RCR_LOOP (0x1)\r
+#define MCF_FEC_RCR_DRT (0x2)\r
+#define MCF_FEC_RCR_MII_MODE (0x4)\r
+#define MCF_FEC_RCR_PROM (0x8)\r
+#define MCF_FEC_RCR_BC_REJ (0x10)\r
+#define MCF_FEC_RCR_FCE (0x20)\r
+#define MCF_FEC_RCR_MAX_FL(x) (((x)&0x7FF)<<0x10)\r
+\r
+/* Bit definitions and macros for MCF_FEC_TCR */\r
+#define MCF_FEC_TCR_GTS (0x1)\r
+#define MCF_FEC_TCR_HBC (0x2)\r
+#define MCF_FEC_TCR_FDEN (0x4)\r
+#define MCF_FEC_TCR_TFC_PAUSE (0x8)\r
+#define MCF_FEC_TCR_RFC_PAUSE (0x10)\r
+\r
+/* Bit definitions and macros for MCF_FEC_PALR */\r
+#define MCF_FEC_PALR_PADDR1(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_PAUR */\r
+#define MCF_FEC_PAUR_TYPE(x) (((x)&0xFFFF)<<0)\r
+#define MCF_FEC_PAUR_PADDR2(x) (((x)&0xFFFF)<<0x10)\r
+\r
+/* Bit definitions and macros for MCF_FEC_OPD */\r
+#define MCF_FEC_OPD_PAUSE_DUR(x) (((x)&0xFFFF)<<0)\r
+#define MCF_FEC_OPD_OPCODE(x) (((x)&0xFFFF)<<0x10)\r
+\r
+/* Bit definitions and macros for MCF_FEC_IAUR */\r
+#define MCF_FEC_IAUR_IADDR1(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_IALR */\r
+#define MCF_FEC_IALR_IADDR2(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_GAUR */\r
+#define MCF_FEC_GAUR_GADDR1(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_GALR */\r
+#define MCF_FEC_GALR_GADDR2(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_TFWR */\r
+#define MCF_FEC_TFWR_X_WMRK(x) (((x)&0x3)<<0)\r
+#define MCF_FEC_TFWR_X_WMRK_64 (0)\r
+#define MCF_FEC_TFWR_X_WMRK_128 (0x2)\r
+#define MCF_FEC_TFWR_X_WMRK_192 (0x3)\r
+\r
+/* Bit definitions and macros for MCF_FEC_FRBR */\r
+#define MCF_FEC_FRBR_R_BOUND(x) (((x)&0xFF)<<0x2)\r
+\r
+/* Bit definitions and macros for MCF_FEC_FRSR */\r
+#define MCF_FEC_FRSR_R_FSTART(x) (((x)&0xFF)<<0x2)\r
+\r
+/* Bit definitions and macros for MCF_FEC_ERDSR */\r
+#define MCF_FEC_ERDSR_R_DES_START(x) (((x)&0x3FFFFFFF)<<0x2)\r
+\r
+/* Bit definitions and macros for MCF_FEC_ETSDR */\r
+#define MCF_FEC_ETSDR_X_DES_START(x) (((x)&0x3FFFFFFF)<<0x2)\r
+\r
+/* Bit definitions and macros for MCF_FEC_EMRBR */\r
+#define MCF_FEC_EMRBR_R_BUF_SIZE(x) (((x)&0x7F)<<0x4)\r
+\r
+/* Bit definitions and macros for MCF_FEC_RMON_T_DROP */\r
+#define MCF_FEC_RMON_T_DROP_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_RMON_T_PACKETS */\r
+#define MCF_FEC_RMON_T_PACKETS_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_RMON_T_BC_PKT */\r
+#define MCF_FEC_RMON_T_BC_PKT_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_RMON_T_MC_PKT */\r
+#define MCF_FEC_RMON_T_MC_PKT_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_RMON_T_CRC_ALIGN */\r
+#define MCF_FEC_RMON_T_CRC_ALIGN_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_RMON_T_UNDERSIZE */\r
+#define MCF_FEC_RMON_T_UNDERSIZE_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_RMON_T_OVERSIZE */\r
+#define MCF_FEC_RMON_T_OVERSIZE_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_RMON_T_FRAG */\r
+#define MCF_FEC_RMON_T_FRAG_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_RMON_T_JAB */\r
+#define MCF_FEC_RMON_T_JAB_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_RMON_T_COL */\r
+#define MCF_FEC_RMON_T_COL_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_RMON_T_P64 */\r
+#define MCF_FEC_RMON_T_P64_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_RMON_T_P65TO127 */\r
+#define MCF_FEC_RMON_T_P65TO127_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_RMON_T_P128TO255 */\r
+#define MCF_FEC_RMON_T_P128TO255_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_RMON_T_P256TO511 */\r
+#define MCF_FEC_RMON_T_P256TO511_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_RMON_T_P512TO1023 */\r
+#define MCF_FEC_RMON_T_P512TO1023_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_RMON_T_P1024TO2047 */\r
+#define MCF_FEC_RMON_T_P1024TO2047_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_RMON_T_P_GTE2048 */\r
+#define MCF_FEC_RMON_T_P_GTE2048_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_RMON_T_OCTETS */\r
+#define MCF_FEC_RMON_T_OCTETS_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_IEEE_T_DROP */\r
+#define MCF_FEC_IEEE_T_DROP_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_IEEE_T_FRAME_OK */\r
+#define MCF_FEC_IEEE_T_FRAME_OK_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_IEEE_T_1COL */\r
+#define MCF_FEC_IEEE_T_1COL_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_IEEE_T_MCOL */\r
+#define MCF_FEC_IEEE_T_MCOL_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_IEEE_T_DEF */\r
+#define MCF_FEC_IEEE_T_DEF_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_IEEE_T_LCOL */\r
+#define MCF_FEC_IEEE_T_LCOL_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_IEEE_T_EXCOL */\r
+#define MCF_FEC_IEEE_T_EXCOL_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_IEEE_T_MACERR */\r
+#define MCF_FEC_IEEE_T_MACERR_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_IEEE_T_CSERR */\r
+#define MCF_FEC_IEEE_T_CSERR_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_IEEE_T_SQE */\r
+#define MCF_FEC_IEEE_T_SQE_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_IEEE_T_FDXFC */\r
+#define MCF_FEC_IEEE_T_FDXFC_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_IEEE_T_OCTETS_OK */\r
+#define MCF_FEC_IEEE_T_OCTETS_OK_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_RMON_R_PACKETS */\r
+#define MCF_FEC_RMON_R_PACKETS_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_RMON_R_BC_PKT */\r
+#define MCF_FEC_RMON_R_BC_PKT_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_RMON_R_MC_PKT */\r
+#define MCF_FEC_RMON_R_MC_PKT_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_RMON_R_CRC_ALIGN */\r
+#define MCF_FEC_RMON_R_CRC_ALIGN_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_RMON_R_UNDERSIZE */\r
+#define MCF_FEC_RMON_R_UNDERSIZE_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_RMON_R_OVERSIZE */\r
+#define MCF_FEC_RMON_R_OVERSIZE_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_RMON_R_FRAG */\r
+#define MCF_FEC_RMON_R_FRAG_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_RMON_R_JAB */\r
+#define MCF_FEC_RMON_R_JAB_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_RMON_R_RESVD_0 */\r
+#define MCF_FEC_RMON_R_RESVD_0_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_RMON_R_P64 */\r
+#define MCF_FEC_RMON_R_P64_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_RMON_R_P65TO127 */\r
+#define MCF_FEC_RMON_R_P65TO127_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_RMON_R_P128TO255 */\r
+#define MCF_FEC_RMON_R_P128TO255_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_RMON_R_P256TO511 */\r
+#define MCF_FEC_RMON_R_P256TO511_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_RMON_R_P512TO1023 */\r
+#define MCF_FEC_RMON_R_P512TO1023_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_RMON_R_P1024TO2047 */\r
+#define MCF_FEC_RMON_R_P1024TO2047_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_RMON_R_P_GTE2048 */\r
+#define MCF_FEC_RMON_R_P_GTE2048_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_RMON_R_OCTETS */\r
+#define MCF_FEC_RMON_R_OCTETS_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_IEEE_R_DROP */\r
+#define MCF_FEC_IEEE_R_DROP_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_IEEE_R_FRAME_OK */\r
+#define MCF_FEC_IEEE_R_FRAME_OK_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_IEEE_R_CRC */\r
+#define MCF_FEC_IEEE_R_CRC_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_IEEE_R_ALIGN */\r
+#define MCF_FEC_IEEE_R_ALIGN_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_IEEE_R_MACERR */\r
+#define MCF_FEC_IEEE_R_MACERR_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_IEEE_R_FDXFC */\r
+#define MCF_FEC_IEEE_R_FDXFC_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_IEEE_R_OCTETS_OK */\r
+#define MCF_FEC_IEEE_R_OCTETS_OK_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+\r
+#endif /* __MCF5282_FEC_H__ */\r
--- /dev/null
+/* Coldfire C Header File\r
+ * Copyright Freescale Semiconductor Inc\r
+ * All rights reserved.\r
+ *\r
+ * 2007/03/19 Revision: 0.9\r
+ */\r
+\r
+#ifndef __MCF5282_FlexCAN_H__\r
+#define __MCF5282_FlexCAN_H__\r
+\r
+\r
+/*********************************************************************\r
+*\r
+* Flex Controller Area Network (FlexCAN)\r
+*\r
+*********************************************************************/\r
+\r
+/* Register read/write macros */\r
+#define MCF_FlexCAN_CANMCR (*(vuint16*)(&__IPSBAR[0x1C0000]))\r
+#define MCF_FlexCAN_CANCTRL0 (*(vuint8 *)(&__IPSBAR[0x1C0006]))\r
+#define MCF_FlexCAN_CANCTRL1 (*(vuint8 *)(&__IPSBAR[0x1C0007]))\r
+#define MCF_FlexCAN_PRESDIV (*(vuint8 *)(&__IPSBAR[0x1C0008]))\r
+#define MCF_FlexCAN_CANCTRL2 (*(vuint8 *)(&__IPSBAR[0x1C0009]))\r
+#define MCF_FlexCAN_TIMER (*(vuint16*)(&__IPSBAR[0x1C000A]))\r
+#define MCF_FlexCAN_RXGMASK (*(vuint32*)(&__IPSBAR[0x1C0010]))\r
+#define MCF_FlexCAN_RX14MASK (*(vuint32*)(&__IPSBAR[0x1C0014]))\r
+#define MCF_FlexCAN_RX15MASK (*(vuint32*)(&__IPSBAR[0x1C0018]))\r
+#define MCF_FlexCAN_ESTAT (*(vuint16*)(&__IPSBAR[0x1C0020]))\r
+#define MCF_FlexCAN_IMASK (*(vuint16*)(&__IPSBAR[0x1C0022]))\r
+#define MCF_FlexCAN_IFLAG (*(vuint16*)(&__IPSBAR[0x1C0024]))\r
+#define MCF_FlexCAN_RXECTR (*(vuint8 *)(&__IPSBAR[0x1C0026]))\r
+#define MCF_FlexCAN_TXECTR (*(vuint8 *)(&__IPSBAR[0x1C0028]))\r
+\r
+\r
+\r
+/* Bit definitions and macros for MCF_FlexCAN_CANMCR */\r
+#define MCF_FlexCAN_CANMCR_STOPACK (0x10)\r
+#define MCF_FlexCAN_CANMCR_APS (0x20)\r
+#define MCF_FlexCAN_CANMCR_SELFWAKE (0x40)\r
+#define MCF_FlexCAN_CANMCR_SUPV (0x80)\r
+#define MCF_FlexCAN_CANMCR_FRZACK (0x100)\r
+#define MCF_FlexCAN_CANMCR_SOFTRST (0x200)\r
+#define MCF_FlexCAN_CANMCR_WAKEMSK (0x400)\r
+#define MCF_FlexCAN_CANMCR_NOTRDY (0x800)\r
+#define MCF_FlexCAN_CANMCR_HALT (0x1000)\r
+#define MCF_FlexCAN_CANMCR_FRZ (0x4000)\r
+#define MCF_FlexCAN_CANMCR_STOP (0x8000)\r
+\r
+/* Bit definitions and macros for MCF_FlexCAN_CANCTRL0 */\r
+#define MCF_FlexCAN_CANCTRL0_TXMODE(x) (((x)&0x3)<<0)\r
+#define MCF_FlexCAN_CANCTRL0_RXMODE (0x4)\r
+#define MCF_FlexCAN_CANCTRL0_ERRMSK (0x40)\r
+#define MCF_FlexCAN_CANCTRL0_BOFFMSK (0x80)\r
+\r
+/* Bit definitions and macros for MCF_FlexCAN_CANCTRL1 */\r
+#define MCF_FlexCAN_CANCTRL1_PROPSEG(x) (((x)&0x7)<<0)\r
+#define MCF_FlexCAN_CANCTRL1_LOM (0x8)\r
+#define MCF_FlexCAN_CANCTRL1_LBUF (0x10)\r
+#define MCF_FlexCAN_CANCTRL1_TSYNC (0x20)\r
+#define MCF_FlexCAN_CANCTRL1_SAMP (0x80)\r
+\r
+/* Bit definitions and macros for MCF_FlexCAN_PRESDIV */\r
+#define MCF_FlexCAN_PRESDIV_PRES_DIV(x) (((x)&0xFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FlexCAN_CANCTRL2 */\r
+#define MCF_FlexCAN_CANCTRL2_PSEG2(x) (((x)&0x7)<<0)\r
+#define MCF_FlexCAN_CANCTRL2_PSEG1(x) (((x)&0x7)<<0x3)\r
+#define MCF_FlexCAN_CANCTRL2_RJW(x) (((x)&0x3)<<0x6)\r
+\r
+/* Bit definitions and macros for MCF_FlexCAN_TIMER */\r
+#define MCF_FlexCAN_TIMER_TIMER(x) (((x)&0xFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FlexCAN_RXGMASK */\r
+#define MCF_FlexCAN_RXGMASK_MID(x) (((x)&0x7FFFFFFF)<<0x1)\r
+\r
+/* Bit definitions and macros for MCF_FlexCAN_RX14MASK */\r
+#define MCF_FlexCAN_RX14MASK_MID(x) (((x)&0x7FFFFFFF)<<0x1)\r
+\r
+/* Bit definitions and macros for MCF_FlexCAN_RX15MASK */\r
+#define MCF_FlexCAN_RX15MASK_MID(x) (((x)&0x7FFFFFFF)<<0x1)\r
+\r
+/* Bit definitions and macros for MCF_FlexCAN_ESTAT */\r
+#define MCF_FlexCAN_ESTAT_WAKEINT (0x1)\r
+#define MCF_FlexCAN_ESTAT_BOFFINT (0x2)\r
+#define MCF_FlexCAN_ESTAT_ERRINT (0x4)\r
+#define MCF_FlexCAN_ESTAT_FCS(x) (((x)&0x3)<<0x4)\r
+#define MCF_FlexCAN_ESTAT_FCS_ACTIVE (0)\r
+#define MCF_FlexCAN_ESTAT_FCS_PASSIVE (0x10)\r
+#define MCF_FlexCAN_ESTAT_TXRX (0x40)\r
+#define MCF_FlexCAN_ESTAT_IDLE (0x80)\r
+#define MCF_FlexCAN_ESTAT_RXWARN (0x100)\r
+#define MCF_FlexCAN_ESTAT_TXWARN (0x200)\r
+#define MCF_FlexCAN_ESTAT_STUFFERR (0x400)\r
+#define MCF_FlexCAN_ESTAT_FORMERR (0x800)\r
+#define MCF_FlexCAN_ESTAT_CRCERR (0x1000)\r
+#define MCF_FlexCAN_ESTAT_ACKERR (0x2000)\r
+#define MCF_FlexCAN_ESTAT_BITERR(x) (((x)&0x3)<<0xE)\r
+\r
+/* Bit definitions and macros for MCF_FlexCAN_IMASK */\r
+#define MCF_FlexCAN_IMASK_BUF0M (0x1)\r
+#define MCF_FlexCAN_IMASK_BUF1M (0x2)\r
+#define MCF_FlexCAN_IMASK_BUF2M (0x4)\r
+#define MCF_FlexCAN_IMASK_BUF3M (0x8)\r
+#define MCF_FlexCAN_IMASK_BUF4M (0x10)\r
+#define MCF_FlexCAN_IMASK_BUF5M (0x20)\r
+#define MCF_FlexCAN_IMASK_BUF6M (0x40)\r
+#define MCF_FlexCAN_IMASK_BUF7M (0x80)\r
+#define MCF_FlexCAN_IMASK_BUF8M (0x100)\r
+#define MCF_FlexCAN_IMASK_BUF9M (0x200)\r
+#define MCF_FlexCAN_IMASK_BUF10M (0x400)\r
+#define MCF_FlexCAN_IMASK_BUF11M (0x800)\r
+#define MCF_FlexCAN_IMASK_BUF12M (0x1000)\r
+#define MCF_FlexCAN_IMASK_BUF13M (0x2000)\r
+#define MCF_FlexCAN_IMASK_BUF14M (0x4000)\r
+#define MCF_FlexCAN_IMASK_BUF15M (0x8000)\r
+#define MCF_FlexCAN_IMASK_BUF(x) (0x1<<(x))\r
+\r
+/* Bit definitions and macros for MCF_FlexCAN_IFLAG */\r
+#define MCF_FlexCAN_IFLAG_BUF0I (0x1)\r
+#define MCF_FlexCAN_IFLAG_BUF1I (0x2)\r
+#define MCF_FlexCAN_IFLAG_BUF2I (0x4)\r
+#define MCF_FlexCAN_IFLAG_BUF3I (0x8)\r
+#define MCF_FlexCAN_IFLAG_BUF4I (0x10)\r
+#define MCF_FlexCAN_IFLAG_BUF5I (0x20)\r
+#define MCF_FlexCAN_IFLAG_BUF6I (0x40)\r
+#define MCF_FlexCAN_IFLAG_BUF7I (0x80)\r
+#define MCF_FlexCAN_IFLAG_BUF8I (0x100)\r
+#define MCF_FlexCAN_IFLAG_BUF9I (0x200)\r
+#define MCF_FlexCAN_IFLAG_BUF10I (0x400)\r
+#define MCF_FlexCAN_IFLAG_BUF11I (0x800)\r
+#define MCF_FlexCAN_IFLAG_BUF12I (0x1000)\r
+#define MCF_FlexCAN_IFLAG_BUF13I (0x2000)\r
+#define MCF_FlexCAN_IFLAG_BUF14I (0x4000)\r
+#define MCF_FlexCAN_IFLAG_BUF15I (0x8000)\r
+#define MCF_FlexCAN_IFLAG_BUF(x) (0x1<<(x))\r
+\r
+/* Bit definitions and macros for MCF_FlexCAN_RXECTR */\r
+#define MCF_FlexCAN_RXECTR_RXECTR(x) (((x)&0xFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FlexCAN_TXECTR */\r
+#define MCF_FlexCAN_TXECTR_TXECTR(x) (((x)&0xFF)<<0)\r
+\r
+\r
+#endif /* __MCF5282_FlexCAN_H__ */\r
--- /dev/null
+/* Coldfire C Header File\r
+ * Copyright Freescale Semiconductor Inc\r
+ * All rights reserved.\r
+ *\r
+ * 2007/03/19 Revision: 0.9\r
+ */\r
+\r
+#ifndef __MCF5282_GIACR_H__\r
+#define __MCF5282_GIACR_H__\r
+\r
+\r
+/*********************************************************************\r
+*\r
+* Global Interrupt Acknowledge Control Registers Module (GIACR)\r
+*\r
+*********************************************************************/\r
+\r
+/* Register read/write macros */\r
+#define MCF_GIACR_GSWIACK (*(vuint8 *)(&__IPSBAR[0xFE0]))\r
+#define MCF_GIACR_GL1IACK (*(vuint8 *)(&__IPSBAR[0xFE4]))\r
+#define MCF_GIACR_GL2IACK (*(vuint8 *)(&__IPSBAR[0xFE8]))\r
+#define MCF_GIACR_GL3IACK (*(vuint8 *)(&__IPSBAR[0xFEC]))\r
+#define MCF_GIACR_GL4IACK (*(vuint8 *)(&__IPSBAR[0xFF0]))\r
+#define MCF_GIACR_GL5IACK (*(vuint8 *)(&__IPSBAR[0xFF4]))\r
+#define MCF_GIACR_GL6IACK (*(vuint8 *)(&__IPSBAR[0xFF8]))\r
+#define MCF_GIACR_GL7IACK (*(vuint8 *)(&__IPSBAR[0xFFC]))\r
+#define MCF_GIACR_GLIACK(x) (*(vuint8 *)(&__IPSBAR[0xFE4 + ((x-1)*0x4)]))\r
+\r
+\r
+/* Bit definitions and macros for MCF_GIACR_GSWIACK */\r
+#define MCF_GIACR_GSWIACK_VECTOR(x) (((x)&0xFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_GIACR_GLIACK */\r
+#define MCF_GIACR_GLIACK_VECTOR(x) (((x)&0xFF)<<0)\r
+\r
+\r
+#endif /* __MCF5282_GIACR_H__ */\r
--- /dev/null
+/* Coldfire C Header File\r
+ * Copyright Freescale Semiconductor Inc\r
+ * All rights reserved.\r
+ *\r
+ * 2007/03/19 Revision: 0.9\r
+ */\r
+\r
+#ifndef __MCF5282_GPIO_H__\r
+#define __MCF5282_GPIO_H__\r
+\r
+\r
+/*********************************************************************\r
+*\r
+* General Purpose I/O (GPIO)\r
+*\r
+*********************************************************************/\r
+\r
+/* Register read/write macros */\r
+#define MCF_GPIO_PORTA (*(vuint8 *)(&__IPSBAR[0x100000]))\r
+#define MCF_GPIO_DDRA (*(vuint8 *)(&__IPSBAR[0x100014]))\r
+#define MCF_GPIO_SETA (*(vuint8 *)(&__IPSBAR[0x100028]))\r
+#define MCF_GPIO_CLRA (*(vuint8 *)(&__IPSBAR[0x10003C]))\r
+\r
+#define MCF_GPIO_PORTB (*(vuint8 *)(&__IPSBAR[0x100001]))\r
+#define MCF_GPIO_DDRB (*(vuint8 *)(&__IPSBAR[0x100015]))\r
+#define MCF_GPIO_SETB (*(vuint8 *)(&__IPSBAR[0x100029]))\r
+#define MCF_GPIO_CLRB (*(vuint8 *)(&__IPSBAR[0x10003D]))\r
+\r
+#define MCF_GPIO_PORTC (*(vuint8 *)(&__IPSBAR[0x100002]))\r
+#define MCF_GPIO_DDRC (*(vuint8 *)(&__IPSBAR[0x100016]))\r
+#define MCF_GPIO_SETC (*(vuint8 *)(&__IPSBAR[0x10002A]))\r
+#define MCF_GPIO_CLRC (*(vuint8 *)(&__IPSBAR[0x10003E]))\r
+\r
+#define MCF_GPIO_PORTD (*(vuint8 *)(&__IPSBAR[0x100003]))\r
+#define MCF_GPIO_DDRD (*(vuint8 *)(&__IPSBAR[0x100017]))\r
+#define MCF_GPIO_SETD (*(vuint8 *)(&__IPSBAR[0x10002B]))\r
+#define MCF_GPIO_CLRD (*(vuint8 *)(&__IPSBAR[0x10003F]))\r
+\r
+#define MCF_GPIO_PORTE (*(vuint8 *)(&__IPSBAR[0x100004]))\r
+#define MCF_GPIO_DDRE (*(vuint8 *)(&__IPSBAR[0x100018]))\r
+#define MCF_GPIO_SETE (*(vuint8 *)(&__IPSBAR[0x10002C]))\r
+#define MCF_GPIO_CLRE (*(vuint8 *)(&__IPSBAR[0x100040]))\r
+\r
+#define MCF_GPIO_PORTF (*(vuint8 *)(&__IPSBAR[0x100005]))\r
+#define MCF_GPIO_DDRF (*(vuint8 *)(&__IPSBAR[0x100019]))\r
+#define MCF_GPIO_SETF (*(vuint8 *)(&__IPSBAR[0x10002D]))\r
+#define MCF_GPIO_CLRF (*(vuint8 *)(&__IPSBAR[0x100041]))\r
+\r
+#define MCF_GPIO_PORTG (*(vuint8 *)(&__IPSBAR[0x100006]))\r
+#define MCF_GPIO_DDRG (*(vuint8 *)(&__IPSBAR[0x10001A]))\r
+#define MCF_GPIO_SETG (*(vuint8 *)(&__IPSBAR[0x10002E]))\r
+#define MCF_GPIO_CLRG (*(vuint8 *)(&__IPSBAR[0x100042]))\r
+\r
+#define MCF_GPIO_PORTH (*(vuint8 *)(&__IPSBAR[0x100007]))\r
+#define MCF_GPIO_DDRH (*(vuint8 *)(&__IPSBAR[0x10001B]))\r
+#define MCF_GPIO_SETH (*(vuint8 *)(&__IPSBAR[0x10002F]))\r
+#define MCF_GPIO_CLRH (*(vuint8 *)(&__IPSBAR[0x100043]))\r
+\r
+#define MCF_GPIO_PORTJ (*(vuint8 *)(&__IPSBAR[0x100008]))\r
+#define MCF_GPIO_DDRJ (*(vuint8 *)(&__IPSBAR[0x10001C]))\r
+#define MCF_GPIO_SETJ (*(vuint8 *)(&__IPSBAR[0x100030]))\r
+#define MCF_GPIO_CLRJ (*(vuint8 *)(&__IPSBAR[0x100044]))\r
+\r
+#define MCF_GPIO_PORTDD (*(vuint8 *)(&__IPSBAR[0x100009]))\r
+#define MCF_GPIO_DDRDD (*(vuint8 *)(&__IPSBAR[0x10001D]))\r
+#define MCF_GPIO_SETDD (*(vuint8 *)(&__IPSBAR[0x100031]))\r
+#define MCF_GPIO_CLRDD (*(vuint8 *)(&__IPSBAR[0x100045]))\r
+\r
+#define MCF_GPIO_PORTEH (*(vuint8 *)(&__IPSBAR[0x10000A]))\r
+#define MCF_GPIO_DDREH (*(vuint8 *)(&__IPSBAR[0x10001E]))\r
+#define MCF_GPIO_SETEH (*(vuint8 *)(&__IPSBAR[0x100032]))\r
+#define MCF_GPIO_CLREH (*(vuint8 *)(&__IPSBAR[0x100046]))\r
+\r
+#define MCF_GPIO_PORTEL (*(vuint8 *)(&__IPSBAR[0x10000B]))\r
+#define MCF_GPIO_DDREL (*(vuint8 *)(&__IPSBAR[0x10001F]))\r
+#define MCF_GPIO_SETEL (*(vuint8 *)(&__IPSBAR[0x100033]))\r
+#define MCF_GPIO_CLREL (*(vuint8 *)(&__IPSBAR[0x100047]))\r
+\r
+#define MCF_GPIO_PORTAS (*(vuint8 *)(&__IPSBAR[0x10000C]))\r
+#define MCF_GPIO_DDRAS (*(vuint8 *)(&__IPSBAR[0x100020]))\r
+#define MCF_GPIO_SETAS (*(vuint8 *)(&__IPSBAR[0x100034]))\r
+#define MCF_GPIO_CLRAS (*(vuint8 *)(&__IPSBAR[0x100048]))\r
+\r
+#define MCF_GPIO_PORTQS (*(vuint8 *)(&__IPSBAR[0x10000D]))\r
+#define MCF_GPIO_DDRQS (*(vuint8 *)(&__IPSBAR[0x100021]))\r
+#define MCF_GPIO_SETQS (*(vuint8 *)(&__IPSBAR[0x100035]))\r
+#define MCF_GPIO_CLRQS (*(vuint8 *)(&__IPSBAR[0x100049]))\r
+\r
+#define MCF_GPIO_PORTSD (*(vuint8 *)(&__IPSBAR[0x10000E]))\r
+#define MCF_GPIO_DDRSD (*(vuint8 *)(&__IPSBAR[0x100022]))\r
+#define MCF_GPIO_SETSD (*(vuint8 *)(&__IPSBAR[0x100036]))\r
+#define MCF_GPIO_CLRSD (*(vuint8 *)(&__IPSBAR[0x10004A]))\r
+\r
+#define MCF_GPIO_PORTTC (*(vuint8 *)(&__IPSBAR[0x10000F]))\r
+#define MCF_GPIO_DDRTC (*(vuint8 *)(&__IPSBAR[0x100023]))\r
+#define MCF_GPIO_SETTC (*(vuint8 *)(&__IPSBAR[0x100037]))\r
+#define MCF_GPIO_CLRTC (*(vuint8 *)(&__IPSBAR[0x10004B]))\r
+\r
+#define MCF_GPIO_PORTTD (*(vuint8 *)(&__IPSBAR[0x100010]))\r
+#define MCF_GPIO_DDRTD (*(vuint8 *)(&__IPSBAR[0x100024]))\r
+#define MCF_GPIO_SETTD (*(vuint8 *)(&__IPSBAR[0x100038]))\r
+#define MCF_GPIO_CLRTD (*(vuint8 *)(&__IPSBAR[0x10004C]))\r
+\r
+#define MCF_GPIO_PORTUA (*(vuint8 *)(&__IPSBAR[0x100011]))\r
+#define MCF_GPIO_DDRUA (*(vuint8 *)(&__IPSBAR[0x100025]))\r
+#define MCF_GPIO_SETUA (*(vuint8 *)(&__IPSBAR[0x100039]))\r
+#define MCF_GPIO_CLRUA (*(vuint8 *)(&__IPSBAR[0x10004D]))\r
+\r
+\r
+\r
+/* Bit definitions and macros for MCF_GPIO_PORTA */\r
+#define MCF_GPIO_PORTA_PORTA0 (0x1)\r
+#define MCF_GPIO_PORTA_PORTA1 (0x2)\r
+#define MCF_GPIO_PORTA_PORTA2 (0x4)\r
+#define MCF_GPIO_PORTA_PORTA3 (0x8)\r
+#define MCF_GPIO_PORTA_PORTA4 (0x10)\r
+#define MCF_GPIO_PORTA_PORTA5 (0x20)\r
+#define MCF_GPIO_PORTA_PORTA6 (0x40)\r
+#define MCF_GPIO_PORTA_PORTA7 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_DDRA */\r
+#define MCF_GPIO_DDRA_DDRA0 (0x1)\r
+#define MCF_GPIO_DDRA_DDRA1 (0x2)\r
+#define MCF_GPIO_DDRA_DDRA2 (0x4)\r
+#define MCF_GPIO_DDRA_DDRA3 (0x8)\r
+#define MCF_GPIO_DDRA_DDRA4 (0x10)\r
+#define MCF_GPIO_DDRA_DDRA5 (0x20)\r
+#define MCF_GPIO_DDRA_DDRA6 (0x40)\r
+#define MCF_GPIO_DDRA_DDRA7 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_SETA */\r
+#define MCF_GPIO_SETA_SETA0 (0x1)\r
+#define MCF_GPIO_SETA_SETA1 (0x2)\r
+#define MCF_GPIO_SETA_SETA2 (0x4)\r
+#define MCF_GPIO_SETA_SETA3 (0x8)\r
+#define MCF_GPIO_SETA_SETA4 (0x10)\r
+#define MCF_GPIO_SETA_SETA5 (0x20)\r
+#define MCF_GPIO_SETA_SETA6 (0x40)\r
+#define MCF_GPIO_SETA_SETA7 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_CLRA */\r
+#define MCF_GPIO_CLRA_CLRA0 (0x1)\r
+#define MCF_GPIO_CLRA_CLRA1 (0x2)\r
+#define MCF_GPIO_CLRA_CLRA2 (0x4)\r
+#define MCF_GPIO_CLRA_CLRA3 (0x8)\r
+#define MCF_GPIO_CLRA_CLRA4 (0x10)\r
+#define MCF_GPIO_CLRA_CLRA5 (0x20)\r
+#define MCF_GPIO_CLRA_CLRA6 (0x40)\r
+#define MCF_GPIO_CLRA_CLRA7 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_PORTB */\r
+#define MCF_GPIO_PORTB_PORTB0 (0x1)\r
+#define MCF_GPIO_PORTB_PORTB1 (0x2)\r
+#define MCF_GPIO_PORTB_PORTB2 (0x4)\r
+#define MCF_GPIO_PORTB_PORTB3 (0x8)\r
+#define MCF_GPIO_PORTB_PORTB4 (0x10)\r
+#define MCF_GPIO_PORTB_PORTB5 (0x20)\r
+#define MCF_GPIO_PORTB_PORTB6 (0x40)\r
+#define MCF_GPIO_PORTB_PORTB7 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_DDRB */\r
+#define MCF_GPIO_DDRB_DDRB0 (0x1)\r
+#define MCF_GPIO_DDRB_DDRB1 (0x2)\r
+#define MCF_GPIO_DDRB_DDRB2 (0x4)\r
+#define MCF_GPIO_DDRB_DDRB3 (0x8)\r
+#define MCF_GPIO_DDRB_DDRB4 (0x10)\r
+#define MCF_GPIO_DDRB_DDRB5 (0x20)\r
+#define MCF_GPIO_DDRB_DDRB6 (0x40)\r
+#define MCF_GPIO_DDRB_DDRB7 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_SETB */\r
+#define MCF_GPIO_SETB_SETB0 (0x1)\r
+#define MCF_GPIO_SETB_SETB1 (0x2)\r
+#define MCF_GPIO_SETB_SETB2 (0x4)\r
+#define MCF_GPIO_SETB_SETB3 (0x8)\r
+#define MCF_GPIO_SETB_SETB4 (0x10)\r
+#define MCF_GPIO_SETB_SETB5 (0x20)\r
+#define MCF_GPIO_SETB_SETB6 (0x40)\r
+#define MCF_GPIO_SETB_SETB7 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_CLRB */\r
+#define MCF_GPIO_CLRB_CLRB0 (0x1)\r
+#define MCF_GPIO_CLRB_CLRB1 (0x2)\r
+#define MCF_GPIO_CLRB_CLRB2 (0x4)\r
+#define MCF_GPIO_CLRB_CLRB3 (0x8)\r
+#define MCF_GPIO_CLRB_CLRB4 (0x10)\r
+#define MCF_GPIO_CLRB_CLRB5 (0x20)\r
+#define MCF_GPIO_CLRB_CLRB6 (0x40)\r
+#define MCF_GPIO_CLRB_CLRB7 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_PORTC */\r
+#define MCF_GPIO_PORTC_PORTC0 (0x1)\r
+#define MCF_GPIO_PORTC_PORTC1 (0x2)\r
+#define MCF_GPIO_PORTC_PORTC2 (0x4)\r
+#define MCF_GPIO_PORTC_PORTC3 (0x8)\r
+#define MCF_GPIO_PORTC_PORTC4 (0x10)\r
+#define MCF_GPIO_PORTC_PORTC5 (0x20)\r
+#define MCF_GPIO_PORTC_PORTC6 (0x40)\r
+#define MCF_GPIO_PORTC_PORTC7 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_DDRC */\r
+#define MCF_GPIO_DDRC_DDRC0 (0x1)\r
+#define MCF_GPIO_DDRC_DDRC1 (0x2)\r
+#define MCF_GPIO_DDRC_DDRC2 (0x4)\r
+#define MCF_GPIO_DDRC_DDRC3 (0x8)\r
+#define MCF_GPIO_DDRC_DDRC4 (0x10)\r
+#define MCF_GPIO_DDRC_DDRC5 (0x20)\r
+#define MCF_GPIO_DDRC_DDRC6 (0x40)\r
+#define MCF_GPIO_DDRC_DDRC7 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_SETC */\r
+#define MCF_GPIO_SETC_SETC0 (0x1)\r
+#define MCF_GPIO_SETC_SETC1 (0x2)\r
+#define MCF_GPIO_SETC_SETC2 (0x4)\r
+#define MCF_GPIO_SETC_SETC3 (0x8)\r
+#define MCF_GPIO_SETC_SETC4 (0x10)\r
+#define MCF_GPIO_SETC_SETC5 (0x20)\r
+#define MCF_GPIO_SETC_SETC6 (0x40)\r
+#define MCF_GPIO_SETC_SETC7 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_CLRC */\r
+#define MCF_GPIO_CLRC_CLRC0 (0x1)\r
+#define MCF_GPIO_CLRC_CLRC1 (0x2)\r
+#define MCF_GPIO_CLRC_CLRC2 (0x4)\r
+#define MCF_GPIO_CLRC_CLRC3 (0x8)\r
+#define MCF_GPIO_CLRC_CLRC4 (0x10)\r
+#define MCF_GPIO_CLRC_CLRC5 (0x20)\r
+#define MCF_GPIO_CLRC_CLRC6 (0x40)\r
+#define MCF_GPIO_CLRC_CLRC7 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_PORTD */\r
+#define MCF_GPIO_PORTD_PORTD0 (0x1)\r
+#define MCF_GPIO_PORTD_PORTD1 (0x2)\r
+#define MCF_GPIO_PORTD_PORTD2 (0x4)\r
+#define MCF_GPIO_PORTD_PORTD3 (0x8)\r
+#define MCF_GPIO_PORTD_PORTD4 (0x10)\r
+#define MCF_GPIO_PORTD_PORTD5 (0x20)\r
+#define MCF_GPIO_PORTD_PORTD6 (0x40)\r
+#define MCF_GPIO_PORTD_PORTD7 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_DDRD */\r
+#define MCF_GPIO_DDRD_DDRD0 (0x1)\r
+#define MCF_GPIO_DDRD_DDRD1 (0x2)\r
+#define MCF_GPIO_DDRD_DDRD2 (0x4)\r
+#define MCF_GPIO_DDRD_DDRD3 (0x8)\r
+#define MCF_GPIO_DDRD_DDRD4 (0x10)\r
+#define MCF_GPIO_DDRD_DDRD5 (0x20)\r
+#define MCF_GPIO_DDRD_DDRD6 (0x40)\r
+#define MCF_GPIO_DDRD_DDRD7 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_SETD */\r
+#define MCF_GPIO_SETD_SETD0 (0x1)\r
+#define MCF_GPIO_SETD_SETD1 (0x2)\r
+#define MCF_GPIO_SETD_SETD2 (0x4)\r
+#define MCF_GPIO_SETD_SETD3 (0x8)\r
+#define MCF_GPIO_SETD_SETD4 (0x10)\r
+#define MCF_GPIO_SETD_SETD5 (0x20)\r
+#define MCF_GPIO_SETD_SETD6 (0x40)\r
+#define MCF_GPIO_SETD_SETD7 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_CLRD */\r
+#define MCF_GPIO_CLRD_CLRD0 (0x1)\r
+#define MCF_GPIO_CLRD_CLRD1 (0x2)\r
+#define MCF_GPIO_CLRD_CLRD2 (0x4)\r
+#define MCF_GPIO_CLRD_CLRD3 (0x8)\r
+#define MCF_GPIO_CLRD_CLRD4 (0x10)\r
+#define MCF_GPIO_CLRD_CLRD5 (0x20)\r
+#define MCF_GPIO_CLRD_CLRD6 (0x40)\r
+#define MCF_GPIO_CLRD_CLRD7 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_PORTE */\r
+#define MCF_GPIO_PORTE_PORTE0 (0x1)\r
+#define MCF_GPIO_PORTE_PORTE1 (0x2)\r
+#define MCF_GPIO_PORTE_PORTE2 (0x4)\r
+#define MCF_GPIO_PORTE_PORTE3 (0x8)\r
+#define MCF_GPIO_PORTE_PORTE4 (0x10)\r
+#define MCF_GPIO_PORTE_PORTE5 (0x20)\r
+#define MCF_GPIO_PORTE_PORTE6 (0x40)\r
+#define MCF_GPIO_PORTE_PORTE7 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_DDRE */\r
+#define MCF_GPIO_DDRE_DDRE0 (0x1)\r
+#define MCF_GPIO_DDRE_DDRE1 (0x2)\r
+#define MCF_GPIO_DDRE_DDRE2 (0x4)\r
+#define MCF_GPIO_DDRE_DDRE3 (0x8)\r
+#define MCF_GPIO_DDRE_DDRE4 (0x10)\r
+#define MCF_GPIO_DDRE_DDRE5 (0x20)\r
+#define MCF_GPIO_DDRE_DDRE6 (0x40)\r
+#define MCF_GPIO_DDRE_DDRE7 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_SETE */\r
+#define MCF_GPIO_SETE_SETE0 (0x1)\r
+#define MCF_GPIO_SETE_SETE1 (0x2)\r
+#define MCF_GPIO_SETE_SETE2 (0x4)\r
+#define MCF_GPIO_SETE_SETE3 (0x8)\r
+#define MCF_GPIO_SETE_SETE4 (0x10)\r
+#define MCF_GPIO_SETE_SETE5 (0x20)\r
+#define MCF_GPIO_SETE_SETE6 (0x40)\r
+#define MCF_GPIO_SETE_SETE7 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_CLRE */\r
+#define MCF_GPIO_CLRE_CLRE0 (0x1)\r
+#define MCF_GPIO_CLRE_CLRE1 (0x2)\r
+#define MCF_GPIO_CLRE_CLRE2 (0x4)\r
+#define MCF_GPIO_CLRE_CLRE3 (0x8)\r
+#define MCF_GPIO_CLRE_CLRE4 (0x10)\r
+#define MCF_GPIO_CLRE_CLRE5 (0x20)\r
+#define MCF_GPIO_CLRE_CLRE6 (0x40)\r
+#define MCF_GPIO_CLRE_CLRE7 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_PORTF */\r
+#define MCF_GPIO_PORTF_PORTF0 (0x1)\r
+#define MCF_GPIO_PORTF_PORTF1 (0x2)\r
+#define MCF_GPIO_PORTF_PORTF2 (0x4)\r
+#define MCF_GPIO_PORTF_PORTF3 (0x8)\r
+#define MCF_GPIO_PORTF_PORTF4 (0x10)\r
+#define MCF_GPIO_PORTF_PORTF5 (0x20)\r
+#define MCF_GPIO_PORTF_PORTF6 (0x40)\r
+#define MCF_GPIO_PORTF_PORTF7 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_DDRF */\r
+#define MCF_GPIO_DDRF_DDRF0 (0x1)\r
+#define MCF_GPIO_DDRF_DDRF1 (0x2)\r
+#define MCF_GPIO_DDRF_DDRF2 (0x4)\r
+#define MCF_GPIO_DDRF_DDRF3 (0x8)\r
+#define MCF_GPIO_DDRF_DDRF4 (0x10)\r
+#define MCF_GPIO_DDRF_DDRF5 (0x20)\r
+#define MCF_GPIO_DDRF_DDRF6 (0x40)\r
+#define MCF_GPIO_DDRF_DDRF7 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_SETF */\r
+#define MCF_GPIO_SETF_SETF0 (0x1)\r
+#define MCF_GPIO_SETF_SETF1 (0x2)\r
+#define MCF_GPIO_SETF_SETF2 (0x4)\r
+#define MCF_GPIO_SETF_SETF3 (0x8)\r
+#define MCF_GPIO_SETF_SETF4 (0x10)\r
+#define MCF_GPIO_SETF_SETF5 (0x20)\r
+#define MCF_GPIO_SETF_SETF6 (0x40)\r
+#define MCF_GPIO_SETF_SETF7 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_CLRF */\r
+#define MCF_GPIO_CLRF_CLRF0 (0x1)\r
+#define MCF_GPIO_CLRF_CLRF1 (0x2)\r
+#define MCF_GPIO_CLRF_CLRF2 (0x4)\r
+#define MCF_GPIO_CLRF_CLRF3 (0x8)\r
+#define MCF_GPIO_CLRF_CLRF4 (0x10)\r
+#define MCF_GPIO_CLRF_CLRF5 (0x20)\r
+#define MCF_GPIO_CLRF_CLRF6 (0x40)\r
+#define MCF_GPIO_CLRF_CLRF7 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_PORTG */\r
+#define MCF_GPIO_PORTG_PORTG0 (0x1)\r
+#define MCF_GPIO_PORTG_PORTG1 (0x2)\r
+#define MCF_GPIO_PORTG_PORTG2 (0x4)\r
+#define MCF_GPIO_PORTG_PORTG3 (0x8)\r
+#define MCF_GPIO_PORTG_PORTG4 (0x10)\r
+#define MCF_GPIO_PORTG_PORTG5 (0x20)\r
+#define MCF_GPIO_PORTG_PORTG6 (0x40)\r
+#define MCF_GPIO_PORTG_PORTG7 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_DDRG */\r
+#define MCF_GPIO_DDRG_DDRG0 (0x1)\r
+#define MCF_GPIO_DDRG_DDRG1 (0x2)\r
+#define MCF_GPIO_DDRG_DDRG2 (0x4)\r
+#define MCF_GPIO_DDRG_DDRG3 (0x8)\r
+#define MCF_GPIO_DDRG_DDRG4 (0x10)\r
+#define MCF_GPIO_DDRG_DDRG5 (0x20)\r
+#define MCF_GPIO_DDRG_DDRG6 (0x40)\r
+#define MCF_GPIO_DDRG_DDRG7 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_SETG */\r
+#define MCF_GPIO_SETG_SETG0 (0x1)\r
+#define MCF_GPIO_SETG_SETG1 (0x2)\r
+#define MCF_GPIO_SETG_SETG2 (0x4)\r
+#define MCF_GPIO_SETG_SETG3 (0x8)\r
+#define MCF_GPIO_SETG_SETG4 (0x10)\r
+#define MCF_GPIO_SETG_SETG5 (0x20)\r
+#define MCF_GPIO_SETG_SETG6 (0x40)\r
+#define MCF_GPIO_SETG_SETG7 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_CLRG */\r
+#define MCF_GPIO_CLRG_CLRG0 (0x1)\r
+#define MCF_GPIO_CLRG_CLRG1 (0x2)\r
+#define MCF_GPIO_CLRG_CLRG2 (0x4)\r
+#define MCF_GPIO_CLRG_CLRG3 (0x8)\r
+#define MCF_GPIO_CLRG_CLRG4 (0x10)\r
+#define MCF_GPIO_CLRG_CLRG5 (0x20)\r
+#define MCF_GPIO_CLRG_CLRG6 (0x40)\r
+#define MCF_GPIO_CLRG_CLRG7 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_PORTH */\r
+#define MCF_GPIO_PORTH_PORTH0 (0x1)\r
+#define MCF_GPIO_PORTH_PORTH1 (0x2)\r
+#define MCF_GPIO_PORTH_PORTH2 (0x4)\r
+#define MCF_GPIO_PORTH_PORTH3 (0x8)\r
+#define MCF_GPIO_PORTH_PORTH4 (0x10)\r
+#define MCF_GPIO_PORTH_PORTH5 (0x20)\r
+#define MCF_GPIO_PORTH_PORTH6 (0x40)\r
+#define MCF_GPIO_PORTH_PORTH7 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_DDRH */\r
+#define MCF_GPIO_DDRH_DDRH0 (0x1)\r
+#define MCF_GPIO_DDRH_DDRH1 (0x2)\r
+#define MCF_GPIO_DDRH_DDRH2 (0x4)\r
+#define MCF_GPIO_DDRH_DDRH3 (0x8)\r
+#define MCF_GPIO_DDRH_DDRH4 (0x10)\r
+#define MCF_GPIO_DDRH_DDRH5 (0x20)\r
+#define MCF_GPIO_DDRH_DDRH6 (0x40)\r
+#define MCF_GPIO_DDRH_DDRH7 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_SETH */\r
+#define MCF_GPIO_SETH_SETH0 (0x1)\r
+#define MCF_GPIO_SETH_SETH1 (0x2)\r
+#define MCF_GPIO_SETH_SETH2 (0x4)\r
+#define MCF_GPIO_SETH_SETH3 (0x8)\r
+#define MCF_GPIO_SETH_SETH4 (0x10)\r
+#define MCF_GPIO_SETH_SETH5 (0x20)\r
+#define MCF_GPIO_SETH_SETH6 (0x40)\r
+#define MCF_GPIO_SETH_SETH7 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_CLRH */\r
+#define MCF_GPIO_CLRH_CLRH0 (0x1)\r
+#define MCF_GPIO_CLRH_CLRH1 (0x2)\r
+#define MCF_GPIO_CLRH_CLRH2 (0x4)\r
+#define MCF_GPIO_CLRH_CLRH3 (0x8)\r
+#define MCF_GPIO_CLRH_CLRH4 (0x10)\r
+#define MCF_GPIO_CLRH_CLRH5 (0x20)\r
+#define MCF_GPIO_CLRH_CLRH6 (0x40)\r
+#define MCF_GPIO_CLRH_CLRH7 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_PORTJ */\r
+#define MCF_GPIO_PORTJ_PORTJ0 (0x1)\r
+#define MCF_GPIO_PORTJ_PORTJ1 (0x2)\r
+#define MCF_GPIO_PORTJ_PORTJ2 (0x4)\r
+#define MCF_GPIO_PORTJ_PORTJ3 (0x8)\r
+#define MCF_GPIO_PORTJ_PORTJ4 (0x10)\r
+#define MCF_GPIO_PORTJ_PORTJ5 (0x20)\r
+#define MCF_GPIO_PORTJ_PORTJ6 (0x40)\r
+#define MCF_GPIO_PORTJ_PORTJ7 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_DDRJ */\r
+#define MCF_GPIO_DDRJ_DDRJ0 (0x1)\r
+#define MCF_GPIO_DDRJ_DDRJ1 (0x2)\r
+#define MCF_GPIO_DDRJ_DDRJ2 (0x4)\r
+#define MCF_GPIO_DDRJ_DDRJ3 (0x8)\r
+#define MCF_GPIO_DDRJ_DDRJ4 (0x10)\r
+#define MCF_GPIO_DDRJ_DDRJ5 (0x20)\r
+#define MCF_GPIO_DDRJ_DDRJ6 (0x40)\r
+#define MCF_GPIO_DDRJ_DDRJ7 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_SETJ */\r
+#define MCF_GPIO_SETJ_SETJ0 (0x1)\r
+#define MCF_GPIO_SETJ_SETJ1 (0x2)\r
+#define MCF_GPIO_SETJ_SETJ2 (0x4)\r
+#define MCF_GPIO_SETJ_SETJ3 (0x8)\r
+#define MCF_GPIO_SETJ_SETJ4 (0x10)\r
+#define MCF_GPIO_SETJ_SETJ5 (0x20)\r
+#define MCF_GPIO_SETJ_SETJ6 (0x40)\r
+#define MCF_GPIO_SETJ_SETJ7 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_CLRJ */\r
+#define MCF_GPIO_CLRJ_CLRJ0 (0x1)\r
+#define MCF_GPIO_CLRJ_CLRJ1 (0x2)\r
+#define MCF_GPIO_CLRJ_CLRJ2 (0x4)\r
+#define MCF_GPIO_CLRJ_CLRJ3 (0x8)\r
+#define MCF_GPIO_CLRJ_CLRJ4 (0x10)\r
+#define MCF_GPIO_CLRJ_CLRJ5 (0x20)\r
+#define MCF_GPIO_CLRJ_CLRJ6 (0x40)\r
+#define MCF_GPIO_CLRJ_CLRJ7 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_PORTDD */\r
+#define MCF_GPIO_PORTDD_PORTDD0 (0x1)\r
+#define MCF_GPIO_PORTDD_PORTDD1 (0x2)\r
+#define MCF_GPIO_PORTDD_PORTDD2 (0x4)\r
+#define MCF_GPIO_PORTDD_PORTDD3 (0x8)\r
+#define MCF_GPIO_PORTDD_PORTDD4 (0x10)\r
+#define MCF_GPIO_PORTDD_PORTDD5 (0x20)\r
+#define MCF_GPIO_PORTDD_PORTDD6 (0x40)\r
+#define MCF_GPIO_PORTDD_PORTDD7 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_DDRDD */\r
+#define MCF_GPIO_DDRDD_DDRDD0 (0x1)\r
+#define MCF_GPIO_DDRDD_DDRDD1 (0x2)\r
+#define MCF_GPIO_DDRDD_DDRDD2 (0x4)\r
+#define MCF_GPIO_DDRDD_DDRDD3 (0x8)\r
+#define MCF_GPIO_DDRDD_DDRDD4 (0x10)\r
+#define MCF_GPIO_DDRDD_DDRDD5 (0x20)\r
+#define MCF_GPIO_DDRDD_DDRDD6 (0x40)\r
+#define MCF_GPIO_DDRDD_DDRDD7 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_SETDD */\r
+#define MCF_GPIO_SETDD_SETDD0 (0x1)\r
+#define MCF_GPIO_SETDD_SETDD1 (0x2)\r
+#define MCF_GPIO_SETDD_SETDD2 (0x4)\r
+#define MCF_GPIO_SETDD_SETDD3 (0x8)\r
+#define MCF_GPIO_SETDD_SETDD4 (0x10)\r
+#define MCF_GPIO_SETDD_SETDD5 (0x20)\r
+#define MCF_GPIO_SETDD_SETDD6 (0x40)\r
+#define MCF_GPIO_SETDD_SETDD7 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_CLRDD */\r
+#define MCF_GPIO_CLRDD_CLRDD0 (0x1)\r
+#define MCF_GPIO_CLRDD_CLRDD1 (0x2)\r
+#define MCF_GPIO_CLRDD_CLRDD2 (0x4)\r
+#define MCF_GPIO_CLRDD_CLRDD3 (0x8)\r
+#define MCF_GPIO_CLRDD_CLRDD4 (0x10)\r
+#define MCF_GPIO_CLRDD_CLRDD5 (0x20)\r
+#define MCF_GPIO_CLRDD_CLRDD6 (0x40)\r
+#define MCF_GPIO_CLRDD_CLRDD7 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_PORTEH */\r
+#define MCF_GPIO_PORTEH_PORTEH0 (0x1)\r
+#define MCF_GPIO_PORTEH_PORTEH1 (0x2)\r
+#define MCF_GPIO_PORTEH_PORTEH2 (0x4)\r
+#define MCF_GPIO_PORTEH_PORTEH3 (0x8)\r
+#define MCF_GPIO_PORTEH_PORTEH4 (0x10)\r
+#define MCF_GPIO_PORTEH_PORTEH5 (0x20)\r
+#define MCF_GPIO_PORTEH_PORTEH6 (0x40)\r
+#define MCF_GPIO_PORTEH_PORTEH7 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_DDREH */\r
+#define MCF_GPIO_DDREH_DDREH0 (0x1)\r
+#define MCF_GPIO_DDREH_DDREH1 (0x2)\r
+#define MCF_GPIO_DDREH_DDREH2 (0x4)\r
+#define MCF_GPIO_DDREH_DDREH3 (0x8)\r
+#define MCF_GPIO_DDREH_DDREH4 (0x10)\r
+#define MCF_GPIO_DDREH_DDREH5 (0x20)\r
+#define MCF_GPIO_DDREH_DDREH6 (0x40)\r
+#define MCF_GPIO_DDREH_DDREH7 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_SETEH */\r
+#define MCF_GPIO_SETEH_SETEH0 (0x1)\r
+#define MCF_GPIO_SETEH_SETEH1 (0x2)\r
+#define MCF_GPIO_SETEH_SETEH2 (0x4)\r
+#define MCF_GPIO_SETEH_SETEH3 (0x8)\r
+#define MCF_GPIO_SETEH_SETEH4 (0x10)\r
+#define MCF_GPIO_SETEH_SETEH5 (0x20)\r
+#define MCF_GPIO_SETEH_SETEH6 (0x40)\r
+#define MCF_GPIO_SETEH_SETEH7 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_CLREH */\r
+#define MCF_GPIO_CLREH_CLREH0 (0x1)\r
+#define MCF_GPIO_CLREH_CLREH1 (0x2)\r
+#define MCF_GPIO_CLREH_CLREH2 (0x4)\r
+#define MCF_GPIO_CLREH_CLREH3 (0x8)\r
+#define MCF_GPIO_CLREH_CLREH4 (0x10)\r
+#define MCF_GPIO_CLREH_CLREH5 (0x20)\r
+#define MCF_GPIO_CLREH_CLREH6 (0x40)\r
+#define MCF_GPIO_CLREH_CLREH7 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_PORTEL */\r
+#define MCF_GPIO_PORTEL_PORTEL0 (0x1)\r
+#define MCF_GPIO_PORTEL_PORTEL1 (0x2)\r
+#define MCF_GPIO_PORTEL_PORTEL2 (0x4)\r
+#define MCF_GPIO_PORTEL_PORTEL3 (0x8)\r
+#define MCF_GPIO_PORTEL_PORTEL4 (0x10)\r
+#define MCF_GPIO_PORTEL_PORTEL5 (0x20)\r
+#define MCF_GPIO_PORTEL_PORTEL6 (0x40)\r
+#define MCF_GPIO_PORTEL_PORTEL7 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_DDREL */\r
+#define MCF_GPIO_DDREL_DDREL0 (0x1)\r
+#define MCF_GPIO_DDREL_DDREL1 (0x2)\r
+#define MCF_GPIO_DDREL_DDREL2 (0x4)\r
+#define MCF_GPIO_DDREL_DDREL3 (0x8)\r
+#define MCF_GPIO_DDREL_DDREL4 (0x10)\r
+#define MCF_GPIO_DDREL_DDREL5 (0x20)\r
+#define MCF_GPIO_DDREL_DDREL6 (0x40)\r
+#define MCF_GPIO_DDREL_DDREL7 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_SETEL */\r
+#define MCF_GPIO_SETEL_SETEL0 (0x1)\r
+#define MCF_GPIO_SETEL_SETEL1 (0x2)\r
+#define MCF_GPIO_SETEL_SETEL2 (0x4)\r
+#define MCF_GPIO_SETEL_SETEL3 (0x8)\r
+#define MCF_GPIO_SETEL_SETEL4 (0x10)\r
+#define MCF_GPIO_SETEL_SETEL5 (0x20)\r
+#define MCF_GPIO_SETEL_SETEL6 (0x40)\r
+#define MCF_GPIO_SETEL_SETEL7 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_CLREL */\r
+#define MCF_GPIO_CLREL_CLREL0 (0x1)\r
+#define MCF_GPIO_CLREL_CLREL1 (0x2)\r
+#define MCF_GPIO_CLREL_CLREL2 (0x4)\r
+#define MCF_GPIO_CLREL_CLREL3 (0x8)\r
+#define MCF_GPIO_CLREL_CLREL4 (0x10)\r
+#define MCF_GPIO_CLREL_CLREL5 (0x20)\r
+#define MCF_GPIO_CLREL_CLREL6 (0x40)\r
+#define MCF_GPIO_CLREL_CLREL7 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_PORTAS */\r
+#define MCF_GPIO_PORTAS_PORTAS0 (0x1)\r
+#define MCF_GPIO_PORTAS_PORTAS1 (0x2)\r
+#define MCF_GPIO_PORTAS_PORTAS2 (0x4)\r
+#define MCF_GPIO_PORTAS_PORTAS3 (0x8)\r
+#define MCF_GPIO_PORTAS_PORTAS4 (0x10)\r
+#define MCF_GPIO_PORTAS_PORTAS5 (0x20)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_DDRAS */\r
+#define MCF_GPIO_DDRAS_DDRAS0 (0x1)\r
+#define MCF_GPIO_DDRAS_DDRAS1 (0x2)\r
+#define MCF_GPIO_DDRAS_DDRAS2 (0x4)\r
+#define MCF_GPIO_DDRAS_DDRAS3 (0x8)\r
+#define MCF_GPIO_DDRAS_DDRAS4 (0x10)\r
+#define MCF_GPIO_DDRAS_DDRAS5 (0x20)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_SETAS */\r
+#define MCF_GPIO_SETAS_SETAS0 (0x1)\r
+#define MCF_GPIO_SETAS_SETAS1 (0x2)\r
+#define MCF_GPIO_SETAS_SETAS2 (0x4)\r
+#define MCF_GPIO_SETAS_SETAS3 (0x8)\r
+#define MCF_GPIO_SETAS_SETAS4 (0x10)\r
+#define MCF_GPIO_SETAS_SETAS5 (0x20)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_CLRAS */\r
+#define MCF_GPIO_CLRAS_CLRAS0 (0x1)\r
+#define MCF_GPIO_CLRAS_CLRAS1 (0x2)\r
+#define MCF_GPIO_CLRAS_CLRAS2 (0x4)\r
+#define MCF_GPIO_CLRAS_CLRAS3 (0x8)\r
+#define MCF_GPIO_CLRAS_CLRAS4 (0x10)\r
+#define MCF_GPIO_CLRAS_CLRAS5 (0x20)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_PORTQS */\r
+#define MCF_GPIO_PORTQS_PORTQS0 (0x1)\r
+#define MCF_GPIO_PORTQS_PORTQS1 (0x2)\r
+#define MCF_GPIO_PORTQS_PORTQS2 (0x4)\r
+#define MCF_GPIO_PORTQS_PORTQS3 (0x8)\r
+#define MCF_GPIO_PORTQS_PORTQS4 (0x10)\r
+#define MCF_GPIO_PORTQS_PORTQS5 (0x20)\r
+#define MCF_GPIO_PORTQS_PORTQS6 (0x40)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_DDRQS */\r
+#define MCF_GPIO_DDRQS_DDRQS0 (0x1)\r
+#define MCF_GPIO_DDRQS_DDRQS1 (0x2)\r
+#define MCF_GPIO_DDRQS_DDRQS2 (0x4)\r
+#define MCF_GPIO_DDRQS_DDRQS3 (0x8)\r
+#define MCF_GPIO_DDRQS_DDRQS4 (0x10)\r
+#define MCF_GPIO_DDRQS_DDRQS5 (0x20)\r
+#define MCF_GPIO_DDRQS_DDRQS6 (0x40)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_SETQS */\r
+#define MCF_GPIO_SETQS_SETQS0 (0x1)\r
+#define MCF_GPIO_SETQS_SETQS1 (0x2)\r
+#define MCF_GPIO_SETQS_SETQS2 (0x4)\r
+#define MCF_GPIO_SETQS_SETQS3 (0x8)\r
+#define MCF_GPIO_SETQS_SETQS4 (0x10)\r
+#define MCF_GPIO_SETQS_SETQS5 (0x20)\r
+#define MCF_GPIO_SETQS_SETQS6 (0x40)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_CLRQS */\r
+#define MCF_GPIO_CLRQS_CLRQS0 (0x1)\r
+#define MCF_GPIO_CLRQS_CLRQS1 (0x2)\r
+#define MCF_GPIO_CLRQS_CLRQS2 (0x4)\r
+#define MCF_GPIO_CLRQS_CLRQS3 (0x8)\r
+#define MCF_GPIO_CLRQS_CLRQS4 (0x10)\r
+#define MCF_GPIO_CLRQS_CLRQS5 (0x20)\r
+#define MCF_GPIO_CLRQS_CLRQS6 (0x40)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_PORTSD */\r
+#define MCF_GPIO_PORTSD_PORTSD0 (0x1)\r
+#define MCF_GPIO_PORTSD_PORTSD1 (0x2)\r
+#define MCF_GPIO_PORTSD_PORTSD2 (0x4)\r
+#define MCF_GPIO_PORTSD_PORTSD3 (0x8)\r
+#define MCF_GPIO_PORTSD_PORTSD4 (0x10)\r
+#define MCF_GPIO_PORTSD_PORTSD5 (0x20)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_DDRSD */\r
+#define MCF_GPIO_DDRSD_DDRSD0 (0x1)\r
+#define MCF_GPIO_DDRSD_DDRSD1 (0x2)\r
+#define MCF_GPIO_DDRSD_DDRSD2 (0x4)\r
+#define MCF_GPIO_DDRSD_DDRSD3 (0x8)\r
+#define MCF_GPIO_DDRSD_DDRSD4 (0x10)\r
+#define MCF_GPIO_DDRSD_DDRSD5 (0x20)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_SETSD */\r
+#define MCF_GPIO_SETSD_SETSD0 (0x1)\r
+#define MCF_GPIO_SETSD_SETSD1 (0x2)\r
+#define MCF_GPIO_SETSD_SETSD2 (0x4)\r
+#define MCF_GPIO_SETSD_SETSD3 (0x8)\r
+#define MCF_GPIO_SETSD_SETSD4 (0x10)\r
+#define MCF_GPIO_SETSD_SETSD5 (0x20)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_CLRSD */\r
+#define MCF_GPIO_CLRSD_CLRSD0 (0x1)\r
+#define MCF_GPIO_CLRSD_CLRSD1 (0x2)\r
+#define MCF_GPIO_CLRSD_CLRSD2 (0x4)\r
+#define MCF_GPIO_CLRSD_CLRSD3 (0x8)\r
+#define MCF_GPIO_CLRSD_CLRSD4 (0x10)\r
+#define MCF_GPIO_CLRSD_CLRSD5 (0x20)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_PORTTC */\r
+#define MCF_GPIO_PORTTC_PORTTC0 (0x1)\r
+#define MCF_GPIO_PORTTC_PORTTC1 (0x2)\r
+#define MCF_GPIO_PORTTC_PORTTC2 (0x4)\r
+#define MCF_GPIO_PORTTC_PORTTC3 (0x8)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_DDRTC */\r
+#define MCF_GPIO_DDRTC_DDRTC0 (0x1)\r
+#define MCF_GPIO_DDRTC_DDRTC1 (0x2)\r
+#define MCF_GPIO_DDRTC_DDRTC2 (0x4)\r
+#define MCF_GPIO_DDRTC_DDRTC3 (0x8)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_SETTC */\r
+#define MCF_GPIO_SETTC_SETTC0 (0x1)\r
+#define MCF_GPIO_SETTC_SETTC1 (0x2)\r
+#define MCF_GPIO_SETTC_SETTC2 (0x4)\r
+#define MCF_GPIO_SETTC_SETTC3 (0x8)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_CLRTC */\r
+#define MCF_GPIO_CLRTC_CLRTC0 (0x1)\r
+#define MCF_GPIO_CLRTC_CLRTC1 (0x2)\r
+#define MCF_GPIO_CLRTC_CLRTC2 (0x4)\r
+#define MCF_GPIO_CLRTC_CLRTC3 (0x8)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_PORTTD */\r
+#define MCF_GPIO_PORTTD_PORTTD0 (0x1)\r
+#define MCF_GPIO_PORTTD_PORTTD1 (0x2)\r
+#define MCF_GPIO_PORTTD_PORTTD2 (0x4)\r
+#define MCF_GPIO_PORTTD_PORTTD3 (0x8)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_DDRTD */\r
+#define MCF_GPIO_DDRTD_DDRTD0 (0x1)\r
+#define MCF_GPIO_DDRTD_DDRTD1 (0x2)\r
+#define MCF_GPIO_DDRTD_DDRTD2 (0x4)\r
+#define MCF_GPIO_DDRTD_DDRTD3 (0x8)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_SETTD */\r
+#define MCF_GPIO_SETTD_SETTD0 (0x1)\r
+#define MCF_GPIO_SETTD_SETTD1 (0x2)\r
+#define MCF_GPIO_SETTD_SETTD2 (0x4)\r
+#define MCF_GPIO_SETTD_SETTD3 (0x8)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_CLRTD */\r
+#define MCF_GPIO_CLRTD_CLRTD0 (0x1)\r
+#define MCF_GPIO_CLRTD_CLRTD1 (0x2)\r
+#define MCF_GPIO_CLRTD_CLRTD2 (0x4)\r
+#define MCF_GPIO_CLRTD_CLRTD3 (0x8)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_PORTUA */\r
+#define MCF_GPIO_PORTUA_PORTUA0 (0x1)\r
+#define MCF_GPIO_PORTUA_PORTUA1 (0x2)\r
+#define MCF_GPIO_PORTUA_PORTUA2 (0x4)\r
+#define MCF_GPIO_PORTUA_PORTUA3 (0x8)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_DDRUA */\r
+#define MCF_GPIO_DDRUA_DDRUA0 (0x1)\r
+#define MCF_GPIO_DDRUA_DDRUA1 (0x2)\r
+#define MCF_GPIO_DDRUA_DDRUA2 (0x4)\r
+#define MCF_GPIO_DDRUA_DDRUA3 (0x8)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_SETUA */\r
+#define MCF_GPIO_SETUA_SETUA0 (0x1)\r
+#define MCF_GPIO_SETUA_SETUA1 (0x2)\r
+#define MCF_GPIO_SETUA_SETUA2 (0x4)\r
+#define MCF_GPIO_SETUA_SETUA3 (0x8)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_CLRUA */\r
+#define MCF_GPIO_CLRUA_CLRUA0 (0x1)\r
+#define MCF_GPIO_CLRUA_CLRUA1 (0x2)\r
+#define MCF_GPIO_CLRUA_CLRUA2 (0x4)\r
+#define MCF_GPIO_CLRUA_CLRUA3 (0x8)\r
+\r
+\r
+#endif /* __MCF5282_GPIO_H__ */\r
--- /dev/null
+/* Coldfire C Header File\r
+ * Copyright Freescale Semiconductor Inc\r
+ * All rights reserved.\r
+ *\r
+ * 2007/03/19 Revision: 0.9\r
+ */\r
+\r
+#ifndef __MCF5282_GPTA_H__\r
+#define __MCF5282_GPTA_H__\r
+\r
+\r
+/*********************************************************************\r
+*\r
+* General Purpose Timer Module (GPT)\r
+*\r
+*********************************************************************/\r
+\r
+/* Register read/write macros */\r
+#define MCF_GPTA_GPTIOS (*(vuint8 *)(&__IPSBAR[0x1A0000]))\r
+#define MCF_GPTA_GPTCFORC (*(vuint8 *)(&__IPSBAR[0x1A0001]))\r
+#define MCF_GPTA_GPTOC3M (*(vuint8 *)(&__IPSBAR[0x1A0002]))\r
+#define MCF_GPTA_GPTOC3D (*(vuint8 *)(&__IPSBAR[0x1A0003]))\r
+#define MCF_GPTA_GPTCNT (*(vuint16*)(&__IPSBAR[0x1A0004]))\r
+#define MCF_GPTA_GPTSCR1 (*(vuint8 *)(&__IPSBAR[0x1A0006]))\r
+#define MCF_GPTA_GPTTOV (*(vuint8 *)(&__IPSBAR[0x1A0008]))\r
+#define MCF_GPTA_GPTCTL1 (*(vuint8 *)(&__IPSBAR[0x1A0009]))\r
+#define MCF_GPTA_GPTCTL2 (*(vuint8 *)(&__IPSBAR[0x1A000B]))\r
+#define MCF_GPTA_GPTIE (*(vuint8 *)(&__IPSBAR[0x1A000C]))\r
+#define MCF_GPTA_GPTSCR2 (*(vuint8 *)(&__IPSBAR[0x1A000D]))\r
+#define MCF_GPTA_GPTFLG1 (*(vuint8 *)(&__IPSBAR[0x1A000E]))\r
+#define MCF_GPTA_GPTFLG2 (*(vuint8 *)(&__IPSBAR[0x1A000F]))\r
+#define MCF_GPTA_GPTC0 (*(vuint16*)(&__IPSBAR[0x1A0010]))\r
+#define MCF_GPTA_GPTC1 (*(vuint16*)(&__IPSBAR[0x1A0012]))\r
+#define MCF_GPTA_GPTC2 (*(vuint16*)(&__IPSBAR[0x1A0014]))\r
+#define MCF_GPTA_GPTC3 (*(vuint16*)(&__IPSBAR[0x1A0016]))\r
+#define MCF_GPTA_GPTPACTL (*(vuint8 *)(&__IPSBAR[0x1A0018]))\r
+#define MCF_GPTA_GPTPAFLG (*(vuint8 *)(&__IPSBAR[0x1A0019]))\r
+#define MCF_GPTA_GPTPACNT (*(vuint16*)(&__IPSBAR[0x1A001A]))\r
+#define MCF_GPTA_GPTPORT (*(vuint8 *)(&__IPSBAR[0x1A001D]))\r
+#define MCF_GPTA_GPTDDR (*(vuint8 *)(&__IPSBAR[0x1A001E]))\r
+#define MCF_GPTA_GPTC(x) (*(vuint16*)(&__IPSBAR[0x1A0010 + ((x)*0x2)]))\r
+\r
+\r
+/* Bit definitions and macros for MCF_GPTA_GPTIOS */\r
+#define MCF_GPTA_GPTIOS_IOS0 (0x1)\r
+#define MCF_GPTA_GPTIOS_IOS1 (0x2)\r
+#define MCF_GPTA_GPTIOS_IOS2 (0x4)\r
+#define MCF_GPTA_GPTIOS_IOS3 (0x8)\r
+\r
+/* Bit definitions and macros for MCF_GPTA_GPTCFORC */\r
+#define MCF_GPTA_GPTCFORC_FOC0 (0x1)\r
+#define MCF_GPTA_GPTCFORC_FOC1 (0x2)\r
+#define MCF_GPTA_GPTCFORC_FOC2 (0x4)\r
+#define MCF_GPTA_GPTCFORC_FOC3 (0x8)\r
+\r
+/* Bit definitions and macros for MCF_GPTA_GPTOC3M */\r
+#define MCF_GPTA_GPTOC3M_OC3M0 (0x1)\r
+#define MCF_GPTA_GPTOC3M_OC3M1 (0x2)\r
+#define MCF_GPTA_GPTOC3M_OC3M2 (0x4)\r
+#define MCF_GPTA_GPTOC3M_OC3M3 (0x8)\r
+\r
+/* Bit definitions and macros for MCF_GPTA_GPTOC3D */\r
+#define MCF_GPTA_GPTOC3D_OC3D0 (0x1)\r
+#define MCF_GPTA_GPTOC3D_OC3D1 (0x2)\r
+#define MCF_GPTA_GPTOC3D_OC3D2 (0x4)\r
+#define MCF_GPTA_GPTOC3D_OC3D3 (0x8)\r
+\r
+/* Bit definitions and macros for MCF_GPTA_GPTCNT */\r
+#define MCF_GPTA_GPTCNT_CNTR(x) (((x)&0xFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_GPTA_GPTSCR1 */\r
+#define MCF_GPTA_GPTSCR1_TFFCA (0x10)\r
+#define MCF_GPTA_GPTSCR1_GPTEN (0x80)\r
+\r
+/* Bit definitions and macros for MCF_GPTA_GPTTOV */\r
+#define MCF_GPTA_GPTTOV_TOV0 (0x1)\r
+#define MCF_GPTA_GPTTOV_TOV1 (0x2)\r
+#define MCF_GPTA_GPTTOV_TOV2 (0x4)\r
+#define MCF_GPTA_GPTTOV_TOV3 (0x8)\r
+\r
+/* Bit definitions and macros for MCF_GPTA_GPTCTL1 */\r
+#define MCF_GPTA_GPTCTL1_OL0 (0x1)\r
+#define MCF_GPTA_GPTCTL1_OM0 (0x2)\r
+#define MCF_GPTA_GPTCTL1_OL1 (0x4)\r
+#define MCF_GPTA_GPTCTL1_OM1 (0x8)\r
+#define MCF_GPTA_GPTCTL1_OL2 (0x10)\r
+#define MCF_GPTA_GPTCTL1_OM2 (0x20)\r
+#define MCF_GPTA_GPTCTL1_OL3 (0x40)\r
+#define MCF_GPTA_GPTCTL1_OM3 (0x80)\r
+#define MCF_GPTA_GPTCTL1_OUTPUT0_NOTHING (0)\r
+#define MCF_GPTA_GPTCTL1_OUTPUT0_TOGGLE (0x1)\r
+#define MCF_GPTA_GPTCTL1_OUTPUT0_CLEAR (0x2)\r
+#define MCF_GPTA_GPTCTL1_OUTPUT0_SET (0x3)\r
+#define MCF_GPTA_GPTCTL1_OUTPUT1_NOTHING (0)\r
+#define MCF_GPTA_GPTCTL1_OUTPUT1_TOGGLE (0x4)\r
+#define MCF_GPTA_GPTCTL1_OUTPUT1_CLEAR (0x8)\r
+#define MCF_GPTA_GPTCTL1_OUTPUT1_SET (0xC)\r
+#define MCF_GPTA_GPTCTL1_OUTPUT2_NOTHING (0)\r
+#define MCF_GPTA_GPTCTL1_OUTPUT2_TOGGLE (0x10)\r
+#define MCF_GPTA_GPTCTL1_OUTPUT2_CLEAR (0x20)\r
+#define MCF_GPTA_GPTCTL1_OUTPUT2_SET (0x30)\r
+#define MCF_GPTA_GPTCTL1_OUTPUT3_NOTHING (0)\r
+#define MCF_GPTA_GPTCTL1_OUTPUT3_TOGGLE (0x40)\r
+#define MCF_GPTA_GPTCTL1_OUTPUT3_CLEAR (0x80)\r
+#define MCF_GPTA_GPTCTL1_OUTPUT3_SET (0xC0)\r
+\r
+/* Bit definitions and macros for MCF_GPTA_GPTCTL2 */\r
+#define MCF_GPTA_GPTCTL2_EDG0A (0x1)\r
+#define MCF_GPTA_GPTCTL2_EDG0B (0x2)\r
+#define MCF_GPTA_GPTCTL2_EDG1A (0x4)\r
+#define MCF_GPTA_GPTCTL2_EDG1B (0x8)\r
+#define MCF_GPTA_GPTCTL2_EDG2A (0x10)\r
+#define MCF_GPTA_GPTCTL2_EDG2B (0x20)\r
+#define MCF_GPTA_GPTCTL2_EDG3A (0x40)\r
+#define MCF_GPTA_GPTCTL2_EDG3B (0x80)\r
+#define MCF_GPTA_GPTCTL2_INPUT0_DISABLED (0)\r
+#define MCF_GPTA_GPTCTL2_INPUT0_RISING (0x1)\r
+#define MCF_GPTA_GPTCTL2_INPUT0_FALLING (0x2)\r
+#define MCF_GPTA_GPTCTL2_INPUT0_ANY (0x3)\r
+#define MCF_GPTA_GPTCTL2_INPUT1_DISABLED (0)\r
+#define MCF_GPTA_GPTCTL2_INPUT1_RISING (0x4)\r
+#define MCF_GPTA_GPTCTL2_INPUT1_FALLING (0x8)\r
+#define MCF_GPTA_GPTCTL2_INPUT1_ANY (0xC)\r
+#define MCF_GPTA_GPTCTL2_INPUT2_DISABLED (0)\r
+#define MCF_GPTA_GPTCTL2_INPUT2_RISING (0x10)\r
+#define MCF_GPTA_GPTCTL2_INPUT2_FALLING (0x20)\r
+#define MCF_GPTA_GPTCTL2_INPUT2_ANY (0x30)\r
+#define MCF_GPTA_GPTCTL2_INPUT3_DISABLED (0)\r
+#define MCF_GPTA_GPTCTL2_INPUT3_RISING (0x40)\r
+#define MCF_GPTA_GPTCTL2_INPUT3_FALLING (0x80)\r
+#define MCF_GPTA_GPTCTL2_INPUT3_ANY (0xC0)\r
+\r
+/* Bit definitions and macros for MCF_GPTA_GPTIE */\r
+#define MCF_GPTA_GPTIE_CI0 (0x1)\r
+#define MCF_GPTA_GPTIE_CI1 (0x2)\r
+#define MCF_GPTA_GPTIE_CI2 (0x4)\r
+#define MCF_GPTA_GPTIE_CI3 (0x8)\r
+\r
+/* Bit definitions and macros for MCF_GPTA_GPTSCR2 */\r
+#define MCF_GPTA_GPTSCR2_PR(x) (((x)&0x7)<<0)\r
+#define MCF_GPTA_GPTSCR2_PR_1 (0)\r
+#define MCF_GPTA_GPTSCR2_PR_2 (0x1)\r
+#define MCF_GPTA_GPTSCR2_PR_4 (0x2)\r
+#define MCF_GPTA_GPTSCR2_PR_8 (0x3)\r
+#define MCF_GPTA_GPTSCR2_PR_16 (0x4)\r
+#define MCF_GPTA_GPTSCR2_PR_32 (0x5)\r
+#define MCF_GPTA_GPTSCR2_PR_64 (0x6)\r
+#define MCF_GPTA_GPTSCR2_PR_128 (0x7)\r
+#define MCF_GPTA_GPTSCR2_TCRE (0x8)\r
+#define MCF_GPTA_GPTSCR2_RDPT (0x10)\r
+#define MCF_GPTA_GPTSCR2_PUPT (0x20)\r
+#define MCF_GPTA_GPTSCR2_TOI (0x80)\r
+\r
+/* Bit definitions and macros for MCF_GPTA_GPTFLG1 */\r
+#define MCF_GPTA_GPTFLG1_CF0 (0x1)\r
+#define MCF_GPTA_GPTFLG1_CF1 (0x2)\r
+#define MCF_GPTA_GPTFLG1_CF2 (0x4)\r
+#define MCF_GPTA_GPTFLG1_CF3 (0x8)\r
+\r
+/* Bit definitions and macros for MCF_GPTA_GPTFLG2 */\r
+#define MCF_GPTA_GPTFLG2_TOF (0x80)\r
+\r
+/* Bit definitions and macros for MCF_GPTA_GPTC */\r
+#define MCF_GPTA_GPTC_CCNT(x) (((x)&0xFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_GPTA_GPTPACTL */\r
+#define MCF_GPTA_GPTPACTL_PAI (0x1)\r
+#define MCF_GPTA_GPTPACTL_PAOVI (0x2)\r
+#define MCF_GPTA_GPTPACTL_CLK(x) (((x)&0x3)<<0x2)\r
+#define MCF_GPTA_GPTPACTL_CLK_GPTPR (0)\r
+#define MCF_GPTA_GPTPACTL_CLK_PACLK (0x1)\r
+#define MCF_GPTA_GPTPACTL_CLK_PACLK_256 (0x2)\r
+#define MCF_GPTA_GPTPACTL_CLK_PACLK_65536 (0x3)\r
+#define MCF_GPTA_GPTPACTL_PEDGE (0x10)\r
+#define MCF_GPTA_GPTPACTL_PAMOD (0x20)\r
+#define MCF_GPTA_GPTPACTL_PAE (0x40)\r
+\r
+/* Bit definitions and macros for MCF_GPTA_GPTPAFLG */\r
+#define MCF_GPTA_GPTPAFLG_PAIF (0x1)\r
+#define MCF_GPTA_GPTPAFLG_PAOVF (0x2)\r
+\r
+/* Bit definitions and macros for MCF_GPTA_GPTPACNT */\r
+#define MCF_GPTA_GPTPACNT_PACNT(x) (((x)&0xFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_GPTA_GPTPORT */\r
+#define MCF_GPTA_GPTPORT_PORTT0 (0x1)\r
+#define MCF_GPTA_GPTPORT_PORTT1 (0x2)\r
+#define MCF_GPTA_GPTPORT_PORTT2 (0x4)\r
+#define MCF_GPTA_GPTPORT_PORTT3 (0x8)\r
+\r
+/* Bit definitions and macros for MCF_GPTA_GPTDDR */\r
+#define MCF_GPTA_GPTDDR_DDRT0 (0x1)\r
+#define MCF_GPTA_GPTDDR_DDRT1 (0x2)\r
+#define MCF_GPTA_GPTDDR_DDRT2 (0x4)\r
+#define MCF_GPTA_GPTDDR_DDRT3 (0x8)\r
+\r
+\r
+#endif /* __MCF5282_GPTA_H__ */\r
--- /dev/null
+/* Coldfire C Header File\r
+ * Copyright Freescale Semiconductor Inc\r
+ * All rights reserved.\r
+ *\r
+ * 2007/03/19 Revision: 0.9\r
+ */\r
+\r
+#ifndef __MCF5282_GPTB_H__\r
+#define __MCF5282_GPTB_H__\r
+\r
+\r
+/*********************************************************************\r
+*\r
+* General Purpose Timer Module (GPT)\r
+*\r
+*********************************************************************/\r
+\r
+/* Register read/write macros */\r
+#define MCF_GPTB_GPTIOS (*(vuint8 *)(&__IPSBAR[0x1B0000]))\r
+#define MCF_GPTB_GPTCFORC (*(vuint8 *)(&__IPSBAR[0x1B0001]))\r
+#define MCF_GPTB_GPTOC3M (*(vuint8 *)(&__IPSBAR[0x1B0002]))\r
+#define MCF_GPTB_GPTOC3D (*(vuint8 *)(&__IPSBAR[0x1B0003]))\r
+#define MCF_GPTB_GPTCNT (*(vuint16*)(&__IPSBAR[0x1B0004]))\r
+#define MCF_GPTB_GPTSCR1 (*(vuint8 *)(&__IPSBAR[0x1B0006]))\r
+#define MCF_GPTB_GPTTOV (*(vuint8 *)(&__IPSBAR[0x1B0008]))\r
+#define MCF_GPTB_GPTCTL1 (*(vuint8 *)(&__IPSBAR[0x1B0009]))\r
+#define MCF_GPTB_GPTCTL2 (*(vuint8 *)(&__IPSBAR[0x1B000B]))\r
+#define MCF_GPTB_GPTIE (*(vuint8 *)(&__IPSBAR[0x1B000C]))\r
+#define MCF_GPTB_GPTSCR2 (*(vuint8 *)(&__IPSBAR[0x1B000D]))\r
+#define MCF_GPTB_GPTFLG1 (*(vuint8 *)(&__IPSBAR[0x1B000E]))\r
+#define MCF_GPTB_GPTFLG2 (*(vuint8 *)(&__IPSBAR[0x1B000F]))\r
+#define MCF_GPTB_GPTC0 (*(vuint16*)(&__IPSBAR[0x1B0010]))\r
+#define MCF_GPTB_GPTC1 (*(vuint16*)(&__IPSBAR[0x1B0012]))\r
+#define MCF_GPTB_GPTC2 (*(vuint16*)(&__IPSBAR[0x1B0014]))\r
+#define MCF_GPTB_GPTC3 (*(vuint16*)(&__IPSBAR[0x1B0016]))\r
+#define MCF_GPTB_GPTPACTL (*(vuint8 *)(&__IPSBAR[0x1B0018]))\r
+#define MCF_GPTB_GPTPAFLG (*(vuint8 *)(&__IPSBAR[0x1B0019]))\r
+#define MCF_GPTB_GPTPACNT (*(vuint16*)(&__IPSBAR[0x1B001A]))\r
+#define MCF_GPTB_GPTPORT (*(vuint8 *)(&__IPSBAR[0x1B001D]))\r
+#define MCF_GPTB_GPTDDR (*(vuint8 *)(&__IPSBAR[0x1B001E]))\r
+#define MCF_GPTB_GPTC(x) (*(vuint16*)(&__IPSBAR[0x1B0010 + ((x)*0x2)]))\r
+\r
+\r
+/* Bit definitions and macros for MCF_GPTB_GPTIOS */\r
+#define MCF_GPTB_GPTIOS_IOS0 (0x1)\r
+#define MCF_GPTB_GPTIOS_IOS1 (0x2)\r
+#define MCF_GPTB_GPTIOS_IOS2 (0x4)\r
+#define MCF_GPTB_GPTIOS_IOS3 (0x8)\r
+\r
+/* Bit definitions and macros for MCF_GPTB_GPTCFORC */\r
+#define MCF_GPTB_GPTCFORC_FOC0 (0x1)\r
+#define MCF_GPTB_GPTCFORC_FOC1 (0x2)\r
+#define MCF_GPTB_GPTCFORC_FOC2 (0x4)\r
+#define MCF_GPTB_GPTCFORC_FOC3 (0x8)\r
+\r
+/* Bit definitions and macros for MCF_GPTB_GPTOC3M */\r
+#define MCF_GPTB_GPTOC3M_OC3M0 (0x1)\r
+#define MCF_GPTB_GPTOC3M_OC3M1 (0x2)\r
+#define MCF_GPTB_GPTOC3M_OC3M2 (0x4)\r
+#define MCF_GPTB_GPTOC3M_OC3M3 (0x8)\r
+\r
+/* Bit definitions and macros for MCF_GPTB_GPTOC3D */\r
+#define MCF_GPTB_GPTOC3D_OC3D0 (0x1)\r
+#define MCF_GPTB_GPTOC3D_OC3D1 (0x2)\r
+#define MCF_GPTB_GPTOC3D_OC3D2 (0x4)\r
+#define MCF_GPTB_GPTOC3D_OC3D3 (0x8)\r
+\r
+/* Bit definitions and macros for MCF_GPTB_GPTCNT */\r
+#define MCF_GPTB_GPTCNT_CNTR(x) (((x)&0xFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_GPTB_GPTSCR1 */\r
+#define MCF_GPTB_GPTSCR1_TFFCA (0x10)\r
+#define MCF_GPTB_GPTSCR1_GPTEN (0x80)\r
+\r
+/* Bit definitions and macros for MCF_GPTB_GPTTOV */\r
+#define MCF_GPTB_GPTTOV_TOV0 (0x1)\r
+#define MCF_GPTB_GPTTOV_TOV1 (0x2)\r
+#define MCF_GPTB_GPTTOV_TOV2 (0x4)\r
+#define MCF_GPTB_GPTTOV_TOV3 (0x8)\r
+\r
+/* Bit definitions and macros for MCF_GPTB_GPTCTL1 */\r
+#define MCF_GPTB_GPTCTL1_OL0 (0x1)\r
+#define MCF_GPTB_GPTCTL1_OM0 (0x2)\r
+#define MCF_GPTB_GPTCTL1_OL1 (0x4)\r
+#define MCF_GPTB_GPTCTL1_OM1 (0x8)\r
+#define MCF_GPTB_GPTCTL1_OL2 (0x10)\r
+#define MCF_GPTB_GPTCTL1_OM2 (0x20)\r
+#define MCF_GPTB_GPTCTL1_OL3 (0x40)\r
+#define MCF_GPTB_GPTCTL1_OM3 (0x80)\r
+#define MCF_GPTB_GPTCTL1_OUTPUT0_NOTHING (0)\r
+#define MCF_GPTB_GPTCTL1_OUTPUT0_TOGGLE (0x1)\r
+#define MCF_GPTB_GPTCTL1_OUTPUT0_CLEAR (0x2)\r
+#define MCF_GPTB_GPTCTL1_OUTPUT0_SET (0x3)\r
+#define MCF_GPTB_GPTCTL1_OUTPUT1_NOTHING (0)\r
+#define MCF_GPTB_GPTCTL1_OUTPUT1_TOGGLE (0x4)\r
+#define MCF_GPTB_GPTCTL1_OUTPUT1_CLEAR (0x8)\r
+#define MCF_GPTB_GPTCTL1_OUTPUT1_SET (0xC)\r
+#define MCF_GPTB_GPTCTL1_OUTPUT2_NOTHING (0)\r
+#define MCF_GPTB_GPTCTL1_OUTPUT2_TOGGLE (0x10)\r
+#define MCF_GPTB_GPTCTL1_OUTPUT2_CLEAR (0x20)\r
+#define MCF_GPTB_GPTCTL1_OUTPUT2_SET (0x30)\r
+#define MCF_GPTB_GPTCTL1_OUTPUT3_NOTHING (0)\r
+#define MCF_GPTB_GPTCTL1_OUTPUT3_TOGGLE (0x40)\r
+#define MCF_GPTB_GPTCTL1_OUTPUT3_CLEAR (0x80)\r
+#define MCF_GPTB_GPTCTL1_OUTPUT3_SET (0xC0)\r
+\r
+/* Bit definitions and macros for MCF_GPTB_GPTCTL2 */\r
+#define MCF_GPTB_GPTCTL2_EDG0A (0x1)\r
+#define MCF_GPTB_GPTCTL2_EDG0B (0x2)\r
+#define MCF_GPTB_GPTCTL2_EDG1A (0x4)\r
+#define MCF_GPTB_GPTCTL2_EDG1B (0x8)\r
+#define MCF_GPTB_GPTCTL2_EDG2A (0x10)\r
+#define MCF_GPTB_GPTCTL2_EDG2B (0x20)\r
+#define MCF_GPTB_GPTCTL2_EDG3A (0x40)\r
+#define MCF_GPTB_GPTCTL2_EDG3B (0x80)\r
+#define MCF_GPTB_GPTCTL2_INPUT0_DISABLED (0)\r
+#define MCF_GPTB_GPTCTL2_INPUT0_RISING (0x1)\r
+#define MCF_GPTB_GPTCTL2_INPUT0_FALLING (0x2)\r
+#define MCF_GPTB_GPTCTL2_INPUT0_ANY (0x3)\r
+#define MCF_GPTB_GPTCTL2_INPUT1_DISABLED (0)\r
+#define MCF_GPTB_GPTCTL2_INPUT1_RISING (0x4)\r
+#define MCF_GPTB_GPTCTL2_INPUT1_FALLING (0x8)\r
+#define MCF_GPTB_GPTCTL2_INPUT1_ANY (0xC)\r
+#define MCF_GPTB_GPTCTL2_INPUT2_DISABLED (0)\r
+#define MCF_GPTB_GPTCTL2_INPUT2_RISING (0x10)\r
+#define MCF_GPTB_GPTCTL2_INPUT2_FALLING (0x20)\r
+#define MCF_GPTB_GPTCTL2_INPUT2_ANY (0x30)\r
+#define MCF_GPTB_GPTCTL2_INPUT3_DISABLED (0)\r
+#define MCF_GPTB_GPTCTL2_INPUT3_RISING (0x40)\r
+#define MCF_GPTB_GPTCTL2_INPUT3_FALLING (0x80)\r
+#define MCF_GPTB_GPTCTL2_INPUT3_ANY (0xC0)\r
+\r
+/* Bit definitions and macros for MCF_GPTB_GPTIE */\r
+#define MCF_GPTB_GPTIE_CI0 (0x1)\r
+#define MCF_GPTB_GPTIE_CI1 (0x2)\r
+#define MCF_GPTB_GPTIE_CI2 (0x4)\r
+#define MCF_GPTB_GPTIE_CI3 (0x8)\r
+\r
+/* Bit definitions and macros for MCF_GPTB_GPTSCR2 */\r
+#define MCF_GPTB_GPTSCR2_PR(x) (((x)&0x7)<<0)\r
+#define MCF_GPTB_GPTSCR2_PR_1 (0)\r
+#define MCF_GPTB_GPTSCR2_PR_2 (0x1)\r
+#define MCF_GPTB_GPTSCR2_PR_4 (0x2)\r
+#define MCF_GPTB_GPTSCR2_PR_8 (0x3)\r
+#define MCF_GPTB_GPTSCR2_PR_16 (0x4)\r
+#define MCF_GPTB_GPTSCR2_PR_32 (0x5)\r
+#define MCF_GPTB_GPTSCR2_PR_64 (0x6)\r
+#define MCF_GPTB_GPTSCR2_PR_128 (0x7)\r
+#define MCF_GPTB_GPTSCR2_TCRE (0x8)\r
+#define MCF_GPTB_GPTSCR2_RDPT (0x10)\r
+#define MCF_GPTB_GPTSCR2_PUPT (0x20)\r
+#define MCF_GPTB_GPTSCR2_TOI (0x80)\r
+\r
+/* Bit definitions and macros for MCF_GPTB_GPTFLG1 */\r
+#define MCF_GPTB_GPTFLG1_CF0 (0x1)\r
+#define MCF_GPTB_GPTFLG1_CF1 (0x2)\r
+#define MCF_GPTB_GPTFLG1_CF2 (0x4)\r
+#define MCF_GPTB_GPTFLG1_CF3 (0x8)\r
+\r
+/* Bit definitions and macros for MCF_GPTB_GPTFLG2 */\r
+#define MCF_GPTB_GPTFLG2_TOF (0x80)\r
+\r
+/* Bit definitions and macros for MCF_GPTB_GPTC */\r
+#define MCF_GPTB_GPTC_CCNT(x) (((x)&0xFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_GPTB_GPTPACTL */\r
+#define MCF_GPTB_GPTPACTL_PAI (0x1)\r
+#define MCF_GPTB_GPTPACTL_PAOVI (0x2)\r
+#define MCF_GPTB_GPTPACTL_CLK(x) (((x)&0x3)<<0x2)\r
+#define MCF_GPTB_GPTPACTL_CLK_GPTPR (0)\r
+#define MCF_GPTB_GPTPACTL_CLK_PACLK (0x1)\r
+#define MCF_GPTB_GPTPACTL_CLK_PACLK_256 (0x2)\r
+#define MCF_GPTB_GPTPACTL_CLK_PACLK_65536 (0x3)\r
+#define MCF_GPTB_GPTPACTL_PEDGE (0x10)\r
+#define MCF_GPTB_GPTPACTL_PAMOD (0x20)\r
+#define MCF_GPTB_GPTPACTL_PAE (0x40)\r
+\r
+/* Bit definitions and macros for MCF_GPTB_GPTPAFLG */\r
+#define MCF_GPTB_GPTPAFLG_PAIF (0x1)\r
+#define MCF_GPTB_GPTPAFLG_PAOVF (0x2)\r
+\r
+/* Bit definitions and macros for MCF_GPTB_GPTPACNT */\r
+#define MCF_GPTB_GPTPACNT_PACNT(x) (((x)&0xFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_GPTB_GPTPORT */\r
+#define MCF_GPTB_GPTPORT_PORTT0 (0x1)\r
+#define MCF_GPTB_GPTPORT_PORTT1 (0x2)\r
+#define MCF_GPTB_GPTPORT_PORTT2 (0x4)\r
+#define MCF_GPTB_GPTPORT_PORTT3 (0x8)\r
+\r
+/* Bit definitions and macros for MCF_GPTB_GPTDDR */\r
+#define MCF_GPTB_GPTDDR_DDRT0 (0x1)\r
+#define MCF_GPTB_GPTDDR_DDRT1 (0x2)\r
+#define MCF_GPTB_GPTDDR_DDRT2 (0x4)\r
+#define MCF_GPTB_GPTDDR_DDRT3 (0x8)\r
+\r
+\r
+#endif /* __MCF5282_GPTB_H__ */\r
--- /dev/null
+/* Coldfire C Header File\r
+ * Copyright Freescale Semiconductor Inc\r
+ * All rights reserved.\r
+ *\r
+ * 2007/03/19 Revision: 0.9\r
+ */\r
+\r
+#ifndef __MCF5282_I2C_H__\r
+#define __MCF5282_I2C_H__\r
+\r
+\r
+/*********************************************************************\r
+*\r
+* I2C Module (I2C)\r
+*\r
+*********************************************************************/\r
+\r
+/* Register read/write macros */\r
+#define MCF_I2C_I2ADR (*(vuint8 *)(&__IPSBAR[0x300]))\r
+#define MCF_I2C_I2FDR (*(vuint8 *)(&__IPSBAR[0x304]))\r
+#define MCF_I2C_I2CR (*(vuint8 *)(&__IPSBAR[0x308]))\r
+#define MCF_I2C_I2SR (*(vuint8 *)(&__IPSBAR[0x30C]))\r
+#define MCF_I2C_I2DR (*(vuint8 *)(&__IPSBAR[0x310]))\r
+\r
+\r
+\r
+/* Bit definitions and macros for MCF_I2C_I2ADR */\r
+#define MCF_I2C_I2ADR_ADR(x) (((x)&0x7F)<<0x1)\r
+\r
+/* Bit definitions and macros for MCF_I2C_I2FDR */\r
+#define MCF_I2C_I2FDR_IC(x) (((x)&0x3F)<<0)\r
+\r
+/* Bit definitions and macros for MCF_I2C_I2CR */\r
+#define MCF_I2C_I2CR_RSTA (0x4)\r
+#define MCF_I2C_I2CR_TXAK (0x8)\r
+#define MCF_I2C_I2CR_MTX (0x10)\r
+#define MCF_I2C_I2CR_MSTA (0x20)\r
+#define MCF_I2C_I2CR_IIEN (0x40)\r
+#define MCF_I2C_I2CR_IEN (0x80)\r
+\r
+/* Bit definitions and macros for MCF_I2C_I2SR */\r
+#define MCF_I2C_I2SR_RXAK (0x1)\r
+#define MCF_I2C_I2SR_IIF (0x2)\r
+#define MCF_I2C_I2SR_SRW (0x4)\r
+#define MCF_I2C_I2SR_IAL (0x10)\r
+#define MCF_I2C_I2SR_IBB (0x20)\r
+#define MCF_I2C_I2SR_IAAS (0x40)\r
+#define MCF_I2C_I2SR_ICF (0x80)\r
+\r
+/* Bit definitions and macros for MCF_I2C_I2DR */\r
+#define MCF_I2C_I2DR_DATA(x) (((x)&0xFF)<<0)\r
+\r
+\r
+#endif /* __MCF5282_I2C_H__ */\r
--- /dev/null
+/* Coldfire C Header File\r
+ * Copyright Freescale Semiconductor Inc\r
+ * All rights reserved.\r
+ *\r
+ * 2007/03/19 Revision: 0.9\r
+ */\r
+\r
+#ifndef __MCF5282_INTC_H__\r
+#define __MCF5282_INTC_H__\r
+\r
+\r
+/*********************************************************************\r
+*\r
+* Interrupt Controller (INTC)\r
+*\r
+*********************************************************************/\r
+\r
+/* Register read/write macros */\r
+#define MCF_INTC0_IPRH (*(vuint32*)(&__IPSBAR[0xC00]))\r
+#define MCF_INTC0_IPRL (*(vuint32*)(&__IPSBAR[0xC04]))\r
+#define MCF_INTC0_IMRH (*(vuint32*)(&__IPSBAR[0xC08]))\r
+#define MCF_INTC0_IMRL (*(vuint32*)(&__IPSBAR[0xC0C]))\r
+#define MCF_INTC0_INTFRCH (*(vuint32*)(&__IPSBAR[0xC10]))\r
+#define MCF_INTC0_INTFRCL (*(vuint32*)(&__IPSBAR[0xC14]))\r
+#define MCF_INTC0_IRLR (*(vuint8 *)(&__IPSBAR[0xC18]))\r
+#define MCF_INTC0_IACKLPR (*(vuint8 *)(&__IPSBAR[0xC19]))\r
+#define MCF_INTC0_ICR01 (*(vuint8 *)(&__IPSBAR[0xC41]))\r
+#define MCF_INTC0_ICR02 (*(vuint8 *)(&__IPSBAR[0xC42]))\r
+#define MCF_INTC0_ICR03 (*(vuint8 *)(&__IPSBAR[0xC43]))\r
+#define MCF_INTC0_ICR04 (*(vuint8 *)(&__IPSBAR[0xC44]))\r
+#define MCF_INTC0_ICR05 (*(vuint8 *)(&__IPSBAR[0xC45]))\r
+#define MCF_INTC0_ICR06 (*(vuint8 *)(&__IPSBAR[0xC46]))\r
+#define MCF_INTC0_ICR07 (*(vuint8 *)(&__IPSBAR[0xC47]))\r
+#define MCF_INTC0_ICR08 (*(vuint8 *)(&__IPSBAR[0xC48]))\r
+#define MCF_INTC0_ICR09 (*(vuint8 *)(&__IPSBAR[0xC49]))\r
+#define MCF_INTC0_ICR10 (*(vuint8 *)(&__IPSBAR[0xC4A]))\r
+#define MCF_INTC0_ICR11 (*(vuint8 *)(&__IPSBAR[0xC4B]))\r
+#define MCF_INTC0_ICR12 (*(vuint8 *)(&__IPSBAR[0xC4C]))\r
+#define MCF_INTC0_ICR13 (*(vuint8 *)(&__IPSBAR[0xC4D]))\r
+#define MCF_INTC0_ICR14 (*(vuint8 *)(&__IPSBAR[0xC4E]))\r
+#define MCF_INTC0_ICR15 (*(vuint8 *)(&__IPSBAR[0xC4F]))\r
+#define MCF_INTC0_ICR16 (*(vuint8 *)(&__IPSBAR[0xC50]))\r
+#define MCF_INTC0_ICR17 (*(vuint8 *)(&__IPSBAR[0xC51]))\r
+#define MCF_INTC0_ICR18 (*(vuint8 *)(&__IPSBAR[0xC52]))\r
+#define MCF_INTC0_ICR19 (*(vuint8 *)(&__IPSBAR[0xC53]))\r
+#define MCF_INTC0_ICR20 (*(vuint8 *)(&__IPSBAR[0xC54]))\r
+#define MCF_INTC0_ICR21 (*(vuint8 *)(&__IPSBAR[0xC55]))\r
+#define MCF_INTC0_ICR22 (*(vuint8 *)(&__IPSBAR[0xC56]))\r
+#define MCF_INTC0_ICR23 (*(vuint8 *)(&__IPSBAR[0xC57]))\r
+#define MCF_INTC0_ICR24 (*(vuint8 *)(&__IPSBAR[0xC58]))\r
+#define MCF_INTC0_ICR25 (*(vuint8 *)(&__IPSBAR[0xC59]))\r
+#define MCF_INTC0_ICR26 (*(vuint8 *)(&__IPSBAR[0xC5A]))\r
+#define MCF_INTC0_ICR27 (*(vuint8 *)(&__IPSBAR[0xC5B]))\r
+#define MCF_INTC0_ICR28 (*(vuint8 *)(&__IPSBAR[0xC5C]))\r
+#define MCF_INTC0_ICR29 (*(vuint8 *)(&__IPSBAR[0xC5D]))\r
+#define MCF_INTC0_ICR30 (*(vuint8 *)(&__IPSBAR[0xC5E]))\r
+#define MCF_INTC0_ICR31 (*(vuint8 *)(&__IPSBAR[0xC5F]))\r
+#define MCF_INTC0_ICR32 (*(vuint8 *)(&__IPSBAR[0xC60]))\r
+#define MCF_INTC0_ICR33 (*(vuint8 *)(&__IPSBAR[0xC61]))\r
+#define MCF_INTC0_ICR34 (*(vuint8 *)(&__IPSBAR[0xC62]))\r
+#define MCF_INTC0_ICR35 (*(vuint8 *)(&__IPSBAR[0xC63]))\r
+#define MCF_INTC0_ICR36 (*(vuint8 *)(&__IPSBAR[0xC64]))\r
+#define MCF_INTC0_ICR37 (*(vuint8 *)(&__IPSBAR[0xC65]))\r
+#define MCF_INTC0_ICR38 (*(vuint8 *)(&__IPSBAR[0xC66]))\r
+#define MCF_INTC0_ICR39 (*(vuint8 *)(&__IPSBAR[0xC67]))\r
+#define MCF_INTC0_ICR40 (*(vuint8 *)(&__IPSBAR[0xC68]))\r
+#define MCF_INTC0_ICR41 (*(vuint8 *)(&__IPSBAR[0xC69]))\r
+#define MCF_INTC0_ICR42 (*(vuint8 *)(&__IPSBAR[0xC6A]))\r
+#define MCF_INTC0_ICR43 (*(vuint8 *)(&__IPSBAR[0xC6B]))\r
+#define MCF_INTC0_ICR44 (*(vuint8 *)(&__IPSBAR[0xC6C]))\r
+#define MCF_INTC0_ICR45 (*(vuint8 *)(&__IPSBAR[0xC6D]))\r
+#define MCF_INTC0_ICR46 (*(vuint8 *)(&__IPSBAR[0xC6E]))\r
+#define MCF_INTC0_ICR47 (*(vuint8 *)(&__IPSBAR[0xC6F]))\r
+#define MCF_INTC0_ICR48 (*(vuint8 *)(&__IPSBAR[0xC70]))\r
+#define MCF_INTC0_ICR49 (*(vuint8 *)(&__IPSBAR[0xC71]))\r
+#define MCF_INTC0_ICR50 (*(vuint8 *)(&__IPSBAR[0xC72]))\r
+#define MCF_INTC0_ICR51 (*(vuint8 *)(&__IPSBAR[0xC73]))\r
+#define MCF_INTC0_ICR52 (*(vuint8 *)(&__IPSBAR[0xC74]))\r
+#define MCF_INTC0_ICR53 (*(vuint8 *)(&__IPSBAR[0xC75]))\r
+#define MCF_INTC0_ICR54 (*(vuint8 *)(&__IPSBAR[0xC76]))\r
+#define MCF_INTC0_ICR55 (*(vuint8 *)(&__IPSBAR[0xC77]))\r
+#define MCF_INTC0_ICR56 (*(vuint8 *)(&__IPSBAR[0xC78]))\r
+#define MCF_INTC0_ICR57 (*(vuint8 *)(&__IPSBAR[0xC79]))\r
+#define MCF_INTC0_ICR58 (*(vuint8 *)(&__IPSBAR[0xC7A]))\r
+#define MCF_INTC0_ICR59 (*(vuint8 *)(&__IPSBAR[0xC7B]))\r
+#define MCF_INTC0_ICR60 (*(vuint8 *)(&__IPSBAR[0xC7C]))\r
+#define MCF_INTC0_ICR61 (*(vuint8 *)(&__IPSBAR[0xC7D]))\r
+#define MCF_INTC0_ICR62 (*(vuint8 *)(&__IPSBAR[0xC7E]))\r
+#define MCF_INTC0_ICR63 (*(vuint8 *)(&__IPSBAR[0xC7F]))\r
+#define MCF_INTC0_SWIACK (*(vuint8 *)(&__IPSBAR[0xCE0]))\r
+#define MCF_INTC0_L1IACK (*(vuint8 *)(&__IPSBAR[0xCE4]))\r
+#define MCF_INTC0_L2IACK (*(vuint8 *)(&__IPSBAR[0xCE8]))\r
+#define MCF_INTC0_L3IACK (*(vuint8 *)(&__IPSBAR[0xCEC]))\r
+#define MCF_INTC0_L4IACK (*(vuint8 *)(&__IPSBAR[0xCF0]))\r
+#define MCF_INTC0_L5IACK (*(vuint8 *)(&__IPSBAR[0xCF4]))\r
+#define MCF_INTC0_L6IACK (*(vuint8 *)(&__IPSBAR[0xCF8]))\r
+#define MCF_INTC0_L7IACK (*(vuint8 *)(&__IPSBAR[0xCFC]))\r
+#define MCF_INTC0_ICR(x) (*(vuint8 *)(&__IPSBAR[0xC41 + ((x-1)*0x1)]))\r
+#define MCF_INTC0_LIACK(x) (*(vuint8 *)(&__IPSBAR[0xCE4 + ((x-1)*0x4)]))\r
+\r
+#define MCF_INTC1_IPRH (*(vuint32*)(&__IPSBAR[0xD00]))\r
+#define MCF_INTC1_IPRL (*(vuint32*)(&__IPSBAR[0xD04]))\r
+#define MCF_INTC1_IMRH (*(vuint32*)(&__IPSBAR[0xD08]))\r
+#define MCF_INTC1_IMRL (*(vuint32*)(&__IPSBAR[0xD0C]))\r
+#define MCF_INTC1_INTFRCH (*(vuint32*)(&__IPSBAR[0xD10]))\r
+#define MCF_INTC1_INTFRCL (*(vuint32*)(&__IPSBAR[0xD14]))\r
+#define MCF_INTC1_IRLR (*(vuint8 *)(&__IPSBAR[0xD18]))\r
+#define MCF_INTC1_IACKLPR (*(vuint8 *)(&__IPSBAR[0xD19]))\r
+#define MCF_INTC1_ICR01 (*(vuint8 *)(&__IPSBAR[0xD41]))\r
+#define MCF_INTC1_ICR02 (*(vuint8 *)(&__IPSBAR[0xD42]))\r
+#define MCF_INTC1_ICR03 (*(vuint8 *)(&__IPSBAR[0xD43]))\r
+#define MCF_INTC1_ICR04 (*(vuint8 *)(&__IPSBAR[0xD44]))\r
+#define MCF_INTC1_ICR05 (*(vuint8 *)(&__IPSBAR[0xD45]))\r
+#define MCF_INTC1_ICR06 (*(vuint8 *)(&__IPSBAR[0xD46]))\r
+#define MCF_INTC1_ICR07 (*(vuint8 *)(&__IPSBAR[0xD47]))\r
+#define MCF_INTC1_ICR08 (*(vuint8 *)(&__IPSBAR[0xD48]))\r
+#define MCF_INTC1_ICR09 (*(vuint8 *)(&__IPSBAR[0xD49]))\r
+#define MCF_INTC1_ICR10 (*(vuint8 *)(&__IPSBAR[0xD4A]))\r
+#define MCF_INTC1_ICR11 (*(vuint8 *)(&__IPSBAR[0xD4B]))\r
+#define MCF_INTC1_ICR12 (*(vuint8 *)(&__IPSBAR[0xD4C]))\r
+#define MCF_INTC1_ICR13 (*(vuint8 *)(&__IPSBAR[0xD4D]))\r
+#define MCF_INTC1_ICR14 (*(vuint8 *)(&__IPSBAR[0xD4E]))\r
+#define MCF_INTC1_ICR15 (*(vuint8 *)(&__IPSBAR[0xD4F]))\r
+#define MCF_INTC1_ICR16 (*(vuint8 *)(&__IPSBAR[0xD50]))\r
+#define MCF_INTC1_ICR17 (*(vuint8 *)(&__IPSBAR[0xD51]))\r
+#define MCF_INTC1_ICR18 (*(vuint8 *)(&__IPSBAR[0xD52]))\r
+#define MCF_INTC1_ICR19 (*(vuint8 *)(&__IPSBAR[0xD53]))\r
+#define MCF_INTC1_ICR20 (*(vuint8 *)(&__IPSBAR[0xD54]))\r
+#define MCF_INTC1_ICR21 (*(vuint8 *)(&__IPSBAR[0xD55]))\r
+#define MCF_INTC1_ICR22 (*(vuint8 *)(&__IPSBAR[0xD56]))\r
+#define MCF_INTC1_ICR23 (*(vuint8 *)(&__IPSBAR[0xD57]))\r
+#define MCF_INTC1_ICR24 (*(vuint8 *)(&__IPSBAR[0xD58]))\r
+#define MCF_INTC1_ICR25 (*(vuint8 *)(&__IPSBAR[0xD59]))\r
+#define MCF_INTC1_ICR26 (*(vuint8 *)(&__IPSBAR[0xD5A]))\r
+#define MCF_INTC1_ICR27 (*(vuint8 *)(&__IPSBAR[0xD5B]))\r
+#define MCF_INTC1_ICR28 (*(vuint8 *)(&__IPSBAR[0xD5C]))\r
+#define MCF_INTC1_ICR29 (*(vuint8 *)(&__IPSBAR[0xD5D]))\r
+#define MCF_INTC1_ICR30 (*(vuint8 *)(&__IPSBAR[0xD5E]))\r
+#define MCF_INTC1_ICR31 (*(vuint8 *)(&__IPSBAR[0xD5F]))\r
+#define MCF_INTC1_ICR32 (*(vuint8 *)(&__IPSBAR[0xD60]))\r
+#define MCF_INTC1_ICR33 (*(vuint8 *)(&__IPSBAR[0xD61]))\r
+#define MCF_INTC1_ICR34 (*(vuint8 *)(&__IPSBAR[0xD62]))\r
+#define MCF_INTC1_ICR35 (*(vuint8 *)(&__IPSBAR[0xD63]))\r
+#define MCF_INTC1_ICR36 (*(vuint8 *)(&__IPSBAR[0xD64]))\r
+#define MCF_INTC1_ICR37 (*(vuint8 *)(&__IPSBAR[0xD65]))\r
+#define MCF_INTC1_ICR38 (*(vuint8 *)(&__IPSBAR[0xD66]))\r
+#define MCF_INTC1_ICR39 (*(vuint8 *)(&__IPSBAR[0xD67]))\r
+#define MCF_INTC1_ICR40 (*(vuint8 *)(&__IPSBAR[0xD68]))\r
+#define MCF_INTC1_ICR41 (*(vuint8 *)(&__IPSBAR[0xD69]))\r
+#define MCF_INTC1_ICR42 (*(vuint8 *)(&__IPSBAR[0xD6A]))\r
+#define MCF_INTC1_ICR43 (*(vuint8 *)(&__IPSBAR[0xD6B]))\r
+#define MCF_INTC1_ICR44 (*(vuint8 *)(&__IPSBAR[0xD6C]))\r
+#define MCF_INTC1_ICR45 (*(vuint8 *)(&__IPSBAR[0xD6D]))\r
+#define MCF_INTC1_ICR46 (*(vuint8 *)(&__IPSBAR[0xD6E]))\r
+#define MCF_INTC1_ICR47 (*(vuint8 *)(&__IPSBAR[0xD6F]))\r
+#define MCF_INTC1_ICR48 (*(vuint8 *)(&__IPSBAR[0xD70]))\r
+#define MCF_INTC1_ICR49 (*(vuint8 *)(&__IPSBAR[0xD71]))\r
+#define MCF_INTC1_ICR50 (*(vuint8 *)(&__IPSBAR[0xD72]))\r
+#define MCF_INTC1_ICR51 (*(vuint8 *)(&__IPSBAR[0xD73]))\r
+#define MCF_INTC1_ICR52 (*(vuint8 *)(&__IPSBAR[0xD74]))\r
+#define MCF_INTC1_ICR53 (*(vuint8 *)(&__IPSBAR[0xD75]))\r
+#define MCF_INTC1_ICR54 (*(vuint8 *)(&__IPSBAR[0xD76]))\r
+#define MCF_INTC1_ICR55 (*(vuint8 *)(&__IPSBAR[0xD77]))\r
+#define MCF_INTC1_ICR56 (*(vuint8 *)(&__IPSBAR[0xD78]))\r
+#define MCF_INTC1_ICR57 (*(vuint8 *)(&__IPSBAR[0xD79]))\r
+#define MCF_INTC1_ICR58 (*(vuint8 *)(&__IPSBAR[0xD7A]))\r
+#define MCF_INTC1_ICR59 (*(vuint8 *)(&__IPSBAR[0xD7B]))\r
+#define MCF_INTC1_ICR60 (*(vuint8 *)(&__IPSBAR[0xD7C]))\r
+#define MCF_INTC1_ICR61 (*(vuint8 *)(&__IPSBAR[0xD7D]))\r
+#define MCF_INTC1_ICR62 (*(vuint8 *)(&__IPSBAR[0xD7E]))\r
+#define MCF_INTC1_ICR63 (*(vuint8 *)(&__IPSBAR[0xD7F]))\r
+#define MCF_INTC1_SWIACK (*(vuint8 *)(&__IPSBAR[0xDE0]))\r
+#define MCF_INTC1_L1IACK (*(vuint8 *)(&__IPSBAR[0xDE4]))\r
+#define MCF_INTC1_L2IACK (*(vuint8 *)(&__IPSBAR[0xDE8]))\r
+#define MCF_INTC1_L3IACK (*(vuint8 *)(&__IPSBAR[0xDEC]))\r
+#define MCF_INTC1_L4IACK (*(vuint8 *)(&__IPSBAR[0xDF0]))\r
+#define MCF_INTC1_L5IACK (*(vuint8 *)(&__IPSBAR[0xDF4]))\r
+#define MCF_INTC1_L6IACK (*(vuint8 *)(&__IPSBAR[0xDF8]))\r
+#define MCF_INTC1_L7IACK (*(vuint8 *)(&__IPSBAR[0xDFC]))\r
+#define MCF_INTC1_ICR(x) (*(vuint8 *)(&__IPSBAR[0xD41 + ((x-1)*0x1)]))\r
+#define MCF_INTC1_LIACK(x) (*(vuint8 *)(&__IPSBAR[0xDE4 + ((x-1)*0x4)]))\r
+\r
+#define MCF_INTC_IPRH(x) (*(vuint32*)(&__IPSBAR[0xC00 + ((x)*0x100)]))\r
+#define MCF_INTC_IPRL(x) (*(vuint32*)(&__IPSBAR[0xC04 + ((x)*0x100)]))\r
+#define MCF_INTC_IMRH(x) (*(vuint32*)(&__IPSBAR[0xC08 + ((x)*0x100)]))\r
+#define MCF_INTC_IMRL(x) (*(vuint32*)(&__IPSBAR[0xC0C + ((x)*0x100)]))\r
+#define MCF_INTC_INTFRCH(x) (*(vuint32*)(&__IPSBAR[0xC10 + ((x)*0x100)]))\r
+#define MCF_INTC_INTFRCL(x) (*(vuint32*)(&__IPSBAR[0xC14 + ((x)*0x100)]))\r
+#define MCF_INTC_IRLR(x) (*(vuint8 *)(&__IPSBAR[0xC18 + ((x)*0x100)]))\r
+#define MCF_INTC_IACKLPR(x) (*(vuint8 *)(&__IPSBAR[0xC19 + ((x)*0x100)]))\r
+#define MCF_INTC_ICR01(x) (*(vuint8 *)(&__IPSBAR[0xC41 + ((x)*0x100)]))\r
+#define MCF_INTC_ICR02(x) (*(vuint8 *)(&__IPSBAR[0xC42 + ((x)*0x100)]))\r
+#define MCF_INTC_ICR03(x) (*(vuint8 *)(&__IPSBAR[0xC43 + ((x)*0x100)]))\r
+#define MCF_INTC_ICR04(x) (*(vuint8 *)(&__IPSBAR[0xC44 + ((x)*0x100)]))\r
+#define MCF_INTC_ICR05(x) (*(vuint8 *)(&__IPSBAR[0xC45 + ((x)*0x100)]))\r
+#define MCF_INTC_ICR06(x) (*(vuint8 *)(&__IPSBAR[0xC46 + ((x)*0x100)]))\r
+#define MCF_INTC_ICR07(x) (*(vuint8 *)(&__IPSBAR[0xC47 + ((x)*0x100)]))\r
+#define MCF_INTC_ICR08(x) (*(vuint8 *)(&__IPSBAR[0xC48 + ((x)*0x100)]))\r
+#define MCF_INTC_ICR09(x) (*(vuint8 *)(&__IPSBAR[0xC49 + ((x)*0x100)]))\r
+#define MCF_INTC_ICR10(x) (*(vuint8 *)(&__IPSBAR[0xC4A + ((x)*0x100)]))\r
+#define MCF_INTC_ICR11(x) (*(vuint8 *)(&__IPSBAR[0xC4B + ((x)*0x100)]))\r
+#define MCF_INTC_ICR12(x) (*(vuint8 *)(&__IPSBAR[0xC4C + ((x)*0x100)]))\r
+#define MCF_INTC_ICR13(x) (*(vuint8 *)(&__IPSBAR[0xC4D + ((x)*0x100)]))\r
+#define MCF_INTC_ICR14(x) (*(vuint8 *)(&__IPSBAR[0xC4E + ((x)*0x100)]))\r
+#define MCF_INTC_ICR15(x) (*(vuint8 *)(&__IPSBAR[0xC4F + ((x)*0x100)]))\r
+#define MCF_INTC_ICR16(x) (*(vuint8 *)(&__IPSBAR[0xC50 + ((x)*0x100)]))\r
+#define MCF_INTC_ICR17(x) (*(vuint8 *)(&__IPSBAR[0xC51 + ((x)*0x100)]))\r
+#define MCF_INTC_ICR18(x) (*(vuint8 *)(&__IPSBAR[0xC52 + ((x)*0x100)]))\r
+#define MCF_INTC_ICR19(x) (*(vuint8 *)(&__IPSBAR[0xC53 + ((x)*0x100)]))\r
+#define MCF_INTC_ICR20(x) (*(vuint8 *)(&__IPSBAR[0xC54 + ((x)*0x100)]))\r
+#define MCF_INTC_ICR21(x) (*(vuint8 *)(&__IPSBAR[0xC55 + ((x)*0x100)]))\r
+#define MCF_INTC_ICR22(x) (*(vuint8 *)(&__IPSBAR[0xC56 + ((x)*0x100)]))\r
+#define MCF_INTC_ICR23(x) (*(vuint8 *)(&__IPSBAR[0xC57 + ((x)*0x100)]))\r
+#define MCF_INTC_ICR24(x) (*(vuint8 *)(&__IPSBAR[0xC58 + ((x)*0x100)]))\r
+#define MCF_INTC_ICR25(x) (*(vuint8 *)(&__IPSBAR[0xC59 + ((x)*0x100)]))\r
+#define MCF_INTC_ICR26(x) (*(vuint8 *)(&__IPSBAR[0xC5A + ((x)*0x100)]))\r
+#define MCF_INTC_ICR27(x) (*(vuint8 *)(&__IPSBAR[0xC5B + ((x)*0x100)]))\r
+#define MCF_INTC_ICR28(x) (*(vuint8 *)(&__IPSBAR[0xC5C + ((x)*0x100)]))\r
+#define MCF_INTC_ICR29(x) (*(vuint8 *)(&__IPSBAR[0xC5D + ((x)*0x100)]))\r
+#define MCF_INTC_ICR30(x) (*(vuint8 *)(&__IPSBAR[0xC5E + ((x)*0x100)]))\r
+#define MCF_INTC_ICR31(x) (*(vuint8 *)(&__IPSBAR[0xC5F + ((x)*0x100)]))\r
+#define MCF_INTC_ICR32(x) (*(vuint8 *)(&__IPSBAR[0xC60 + ((x)*0x100)]))\r
+#define MCF_INTC_ICR33(x) (*(vuint8 *)(&__IPSBAR[0xC61 + ((x)*0x100)]))\r
+#define MCF_INTC_ICR34(x) (*(vuint8 *)(&__IPSBAR[0xC62 + ((x)*0x100)]))\r
+#define MCF_INTC_ICR35(x) (*(vuint8 *)(&__IPSBAR[0xC63 + ((x)*0x100)]))\r
+#define MCF_INTC_ICR36(x) (*(vuint8 *)(&__IPSBAR[0xC64 + ((x)*0x100)]))\r
+#define MCF_INTC_ICR37(x) (*(vuint8 *)(&__IPSBAR[0xC65 + ((x)*0x100)]))\r
+#define MCF_INTC_ICR38(x) (*(vuint8 *)(&__IPSBAR[0xC66 + ((x)*0x100)]))\r
+#define MCF_INTC_ICR39(x) (*(vuint8 *)(&__IPSBAR[0xC67 + ((x)*0x100)]))\r
+#define MCF_INTC_ICR40(x) (*(vuint8 *)(&__IPSBAR[0xC68 + ((x)*0x100)]))\r
+#define MCF_INTC_ICR41(x) (*(vuint8 *)(&__IPSBAR[0xC69 + ((x)*0x100)]))\r
+#define MCF_INTC_ICR42(x) (*(vuint8 *)(&__IPSBAR[0xC6A + ((x)*0x100)]))\r
+#define MCF_INTC_ICR43(x) (*(vuint8 *)(&__IPSBAR[0xC6B + ((x)*0x100)]))\r
+#define MCF_INTC_ICR44(x) (*(vuint8 *)(&__IPSBAR[0xC6C + ((x)*0x100)]))\r
+#define MCF_INTC_ICR45(x) (*(vuint8 *)(&__IPSBAR[0xC6D + ((x)*0x100)]))\r
+#define MCF_INTC_ICR46(x) (*(vuint8 *)(&__IPSBAR[0xC6E + ((x)*0x100)]))\r
+#define MCF_INTC_ICR47(x) (*(vuint8 *)(&__IPSBAR[0xC6F + ((x)*0x100)]))\r
+#define MCF_INTC_ICR48(x) (*(vuint8 *)(&__IPSBAR[0xC70 + ((x)*0x100)]))\r
+#define MCF_INTC_ICR49(x) (*(vuint8 *)(&__IPSBAR[0xC71 + ((x)*0x100)]))\r
+#define MCF_INTC_ICR50(x) (*(vuint8 *)(&__IPSBAR[0xC72 + ((x)*0x100)]))\r
+#define MCF_INTC_ICR51(x) (*(vuint8 *)(&__IPSBAR[0xC73 + ((x)*0x100)]))\r
+#define MCF_INTC_ICR52(x) (*(vuint8 *)(&__IPSBAR[0xC74 + ((x)*0x100)]))\r
+#define MCF_INTC_ICR53(x) (*(vuint8 *)(&__IPSBAR[0xC75 + ((x)*0x100)]))\r
+#define MCF_INTC_ICR54(x) (*(vuint8 *)(&__IPSBAR[0xC76 + ((x)*0x100)]))\r
+#define MCF_INTC_ICR55(x) (*(vuint8 *)(&__IPSBAR[0xC77 + ((x)*0x100)]))\r
+#define MCF_INTC_ICR56(x) (*(vuint8 *)(&__IPSBAR[0xC78 + ((x)*0x100)]))\r
+#define MCF_INTC_ICR57(x) (*(vuint8 *)(&__IPSBAR[0xC79 + ((x)*0x100)]))\r
+#define MCF_INTC_ICR58(x) (*(vuint8 *)(&__IPSBAR[0xC7A + ((x)*0x100)]))\r
+#define MCF_INTC_ICR59(x) (*(vuint8 *)(&__IPSBAR[0xC7B + ((x)*0x100)]))\r
+#define MCF_INTC_ICR60(x) (*(vuint8 *)(&__IPSBAR[0xC7C + ((x)*0x100)]))\r
+#define MCF_INTC_ICR61(x) (*(vuint8 *)(&__IPSBAR[0xC7D + ((x)*0x100)]))\r
+#define MCF_INTC_ICR62(x) (*(vuint8 *)(&__IPSBAR[0xC7E + ((x)*0x100)]))\r
+#define MCF_INTC_ICR63(x) (*(vuint8 *)(&__IPSBAR[0xC7F + ((x)*0x100)]))\r
+#define MCF_INTC_SWIACK(x) (*(vuint8 *)(&__IPSBAR[0xCE0 + ((x)*0x100)]))\r
+#define MCF_INTC_L1IACK(x) (*(vuint8 *)(&__IPSBAR[0xCE4 + ((x)*0x100)]))\r
+#define MCF_INTC_L2IACK(x) (*(vuint8 *)(&__IPSBAR[0xCE8 + ((x)*0x100)]))\r
+#define MCF_INTC_L3IACK(x) (*(vuint8 *)(&__IPSBAR[0xCEC + ((x)*0x100)]))\r
+#define MCF_INTC_L4IACK(x) (*(vuint8 *)(&__IPSBAR[0xCF0 + ((x)*0x100)]))\r
+#define MCF_INTC_L5IACK(x) (*(vuint8 *)(&__IPSBAR[0xCF4 + ((x)*0x100)]))\r
+#define MCF_INTC_L6IACK(x) (*(vuint8 *)(&__IPSBAR[0xCF8 + ((x)*0x100)]))\r
+#define MCF_INTC_L7IACK(x) (*(vuint8 *)(&__IPSBAR[0xCFC + ((x)*0x100)]))\r
+\r
+\r
+/* Bit definitions and macros for MCF_INTC_IPRH */\r
+#define MCF_INTC_IPRH_INT32 (0x1)\r
+#define MCF_INTC_IPRH_INT33 (0x2)\r
+#define MCF_INTC_IPRH_INT34 (0x4)\r
+#define MCF_INTC_IPRH_INT35 (0x8)\r
+#define MCF_INTC_IPRH_INT36 (0x10)\r
+#define MCF_INTC_IPRH_INT37 (0x20)\r
+#define MCF_INTC_IPRH_INT38 (0x40)\r
+#define MCF_INTC_IPRH_INT39 (0x80)\r
+#define MCF_INTC_IPRH_INT40 (0x100)\r
+#define MCF_INTC_IPRH_INT41 (0x200)\r
+#define MCF_INTC_IPRH_INT42 (0x400)\r
+#define MCF_INTC_IPRH_INT43 (0x800)\r
+#define MCF_INTC_IPRH_INT44 (0x1000)\r
+#define MCF_INTC_IPRH_INT45 (0x2000)\r
+#define MCF_INTC_IPRH_INT46 (0x4000)\r
+#define MCF_INTC_IPRH_INT47 (0x8000)\r
+#define MCF_INTC_IPRH_INT48 (0x10000)\r
+#define MCF_INTC_IPRH_INT49 (0x20000)\r
+#define MCF_INTC_IPRH_INT50 (0x40000)\r
+#define MCF_INTC_IPRH_INT51 (0x80000)\r
+#define MCF_INTC_IPRH_INT52 (0x100000)\r
+#define MCF_INTC_IPRH_INT53 (0x200000)\r
+#define MCF_INTC_IPRH_INT54 (0x400000)\r
+#define MCF_INTC_IPRH_INT55 (0x800000)\r
+#define MCF_INTC_IPRH_INT56 (0x1000000)\r
+#define MCF_INTC_IPRH_INT57 (0x2000000)\r
+#define MCF_INTC_IPRH_INT58 (0x4000000)\r
+#define MCF_INTC_IPRH_INT59 (0x8000000)\r
+#define MCF_INTC_IPRH_INT60 (0x10000000)\r
+#define MCF_INTC_IPRH_INT61 (0x20000000)\r
+#define MCF_INTC_IPRH_INT62 (0x40000000)\r
+#define MCF_INTC_IPRH_INT63 (0x80000000)\r
+\r
+/* Bit definitions and macros for MCF_INTC_IPRL */\r
+#define MCF_INTC_IPRL_INT1 (0x2)\r
+#define MCF_INTC_IPRL_INT2 (0x4)\r
+#define MCF_INTC_IPRL_INT3 (0x8)\r
+#define MCF_INTC_IPRL_INT4 (0x10)\r
+#define MCF_INTC_IPRL_INT5 (0x20)\r
+#define MCF_INTC_IPRL_INT6 (0x40)\r
+#define MCF_INTC_IPRL_INT7 (0x80)\r
+#define MCF_INTC_IPRL_INT8 (0x100)\r
+#define MCF_INTC_IPRL_INT9 (0x200)\r
+#define MCF_INTC_IPRL_INT10 (0x400)\r
+#define MCF_INTC_IPRL_INT11 (0x800)\r
+#define MCF_INTC_IPRL_INT12 (0x1000)\r
+#define MCF_INTC_IPRL_INT13 (0x2000)\r
+#define MCF_INTC_IPRL_INT14 (0x4000)\r
+#define MCF_INTC_IPRL_INT15 (0x8000)\r
+#define MCF_INTC_IPRL_INT16 (0x10000)\r
+#define MCF_INTC_IPRL_INT17 (0x20000)\r
+#define MCF_INTC_IPRL_INT18 (0x40000)\r
+#define MCF_INTC_IPRL_INT19 (0x80000)\r
+#define MCF_INTC_IPRL_INT20 (0x100000)\r
+#define MCF_INTC_IPRL_INT21 (0x200000)\r
+#define MCF_INTC_IPRL_INT22 (0x400000)\r
+#define MCF_INTC_IPRL_INT23 (0x800000)\r
+#define MCF_INTC_IPRL_INT24 (0x1000000)\r
+#define MCF_INTC_IPRL_INT25 (0x2000000)\r
+#define MCF_INTC_IPRL_INT26 (0x4000000)\r
+#define MCF_INTC_IPRL_INT27 (0x8000000)\r
+#define MCF_INTC_IPRL_INT28 (0x10000000)\r
+#define MCF_INTC_IPRL_INT29 (0x20000000)\r
+#define MCF_INTC_IPRL_INT30 (0x40000000)\r
+#define MCF_INTC_IPRL_INT31 (0x80000000)\r
+\r
+/* Bit definitions and macros for MCF_INTC_IMRH */\r
+#define MCF_INTC_IMRH_INT_MASK32 (0x1)\r
+#define MCF_INTC_IMRH_INT_MASK33 (0x2)\r
+#define MCF_INTC_IMRH_INT_MASK34 (0x4)\r
+#define MCF_INTC_IMRH_INT_MASK35 (0x8)\r
+#define MCF_INTC_IMRH_INT_MASK36 (0x10)\r
+#define MCF_INTC_IMRH_INT_MASK37 (0x20)\r
+#define MCF_INTC_IMRH_INT_MASK38 (0x40)\r
+#define MCF_INTC_IMRH_INT_MASK39 (0x80)\r
+#define MCF_INTC_IMRH_INT_MASK40 (0x100)\r
+#define MCF_INTC_IMRH_INT_MASK41 (0x200)\r
+#define MCF_INTC_IMRH_INT_MASK42 (0x400)\r
+#define MCF_INTC_IMRH_INT_MASK43 (0x800)\r
+#define MCF_INTC_IMRH_INT_MASK44 (0x1000)\r
+#define MCF_INTC_IMRH_INT_MASK45 (0x2000)\r
+#define MCF_INTC_IMRH_INT_MASK46 (0x4000)\r
+#define MCF_INTC_IMRH_INT_MASK47 (0x8000)\r
+#define MCF_INTC_IMRH_INT_MASK48 (0x10000)\r
+#define MCF_INTC_IMRH_INT_MASK49 (0x20000)\r
+#define MCF_INTC_IMRH_INT_MASK50 (0x40000)\r
+#define MCF_INTC_IMRH_INT_MASK51 (0x80000)\r
+#define MCF_INTC_IMRH_INT_MASK52 (0x100000)\r
+#define MCF_INTC_IMRH_INT_MASK53 (0x200000)\r
+#define MCF_INTC_IMRH_INT_MASK54 (0x400000)\r
+#define MCF_INTC_IMRH_INT_MASK55 (0x800000)\r
+#define MCF_INTC_IMRH_INT_MASK56 (0x1000000)\r
+#define MCF_INTC_IMRH_INT_MASK57 (0x2000000)\r
+#define MCF_INTC_IMRH_INT_MASK58 (0x4000000)\r
+#define MCF_INTC_IMRH_INT_MASK59 (0x8000000)\r
+#define MCF_INTC_IMRH_INT_MASK60 (0x10000000)\r
+#define MCF_INTC_IMRH_INT_MASK61 (0x20000000)\r
+#define MCF_INTC_IMRH_INT_MASK62 (0x40000000)\r
+#define MCF_INTC_IMRH_INT_MASK63 (0x80000000)\r
+\r
+/* Bit definitions and macros for MCF_INTC_IMRL */\r
+#define MCF_INTC_IMRL_MASKALL (0x1)\r
+#define MCF_INTC_IMRL_INT_MASK1 (0x2)\r
+#define MCF_INTC_IMRL_INT_MASK2 (0x4)\r
+#define MCF_INTC_IMRL_INT_MASK3 (0x8)\r
+#define MCF_INTC_IMRL_INT_MASK4 (0x10)\r
+#define MCF_INTC_IMRL_INT_MASK5 (0x20)\r
+#define MCF_INTC_IMRL_INT_MASK6 (0x40)\r
+#define MCF_INTC_IMRL_INT_MASK7 (0x80)\r
+#define MCF_INTC_IMRL_INT_MASK8 (0x100)\r
+#define MCF_INTC_IMRL_INT_MASK9 (0x200)\r
+#define MCF_INTC_IMRL_INT_MASK10 (0x400)\r
+#define MCF_INTC_IMRL_INT_MASK11 (0x800)\r
+#define MCF_INTC_IMRL_INT_MASK12 (0x1000)\r
+#define MCF_INTC_IMRL_INT_MASK13 (0x2000)\r
+#define MCF_INTC_IMRL_INT_MASK14 (0x4000)\r
+#define MCF_INTC_IMRL_INT_MASK15 (0x8000)\r
+#define MCF_INTC_IMRL_INT_MASK16 (0x10000)\r
+#define MCF_INTC_IMRL_INT_MASK17 (0x20000)\r
+#define MCF_INTC_IMRL_INT_MASK18 (0x40000)\r
+#define MCF_INTC_IMRL_INT_MASK19 (0x80000)\r
+#define MCF_INTC_IMRL_INT_MASK20 (0x100000)\r
+#define MCF_INTC_IMRL_INT_MASK21 (0x200000)\r
+#define MCF_INTC_IMRL_INT_MASK22 (0x400000)\r
+#define MCF_INTC_IMRL_INT_MASK23 (0x800000)\r
+#define MCF_INTC_IMRL_INT_MASK24 (0x1000000)\r
+#define MCF_INTC_IMRL_INT_MASK25 (0x2000000)\r
+#define MCF_INTC_IMRL_INT_MASK26 (0x4000000)\r
+#define MCF_INTC_IMRL_INT_MASK27 (0x8000000)\r
+#define MCF_INTC_IMRL_INT_MASK28 (0x10000000)\r
+#define MCF_INTC_IMRL_INT_MASK29 (0x20000000)\r
+#define MCF_INTC_IMRL_INT_MASK30 (0x40000000)\r
+#define MCF_INTC_IMRL_INT_MASK31 (0x80000000)\r
+\r
+/* Bit definitions and macros for MCF_INTC_INTFRCH */\r
+#define MCF_INTC_INTFRCH_INTFRC32 (0x1)\r
+#define MCF_INTC_INTFRCH_INTFRC33 (0x2)\r
+#define MCF_INTC_INTFRCH_INTFRC34 (0x4)\r
+#define MCF_INTC_INTFRCH_INTFRC35 (0x8)\r
+#define MCF_INTC_INTFRCH_INTFRC36 (0x10)\r
+#define MCF_INTC_INTFRCH_INTFRC37 (0x20)\r
+#define MCF_INTC_INTFRCH_INTFRC38 (0x40)\r
+#define MCF_INTC_INTFRCH_INTFRC39 (0x80)\r
+#define MCF_INTC_INTFRCH_INTFRC40 (0x100)\r
+#define MCF_INTC_INTFRCH_INTFRC41 (0x200)\r
+#define MCF_INTC_INTFRCH_INTFRC42 (0x400)\r
+#define MCF_INTC_INTFRCH_INTFRC43 (0x800)\r
+#define MCF_INTC_INTFRCH_INTFRC44 (0x1000)\r
+#define MCF_INTC_INTFRCH_INTFRC45 (0x2000)\r
+#define MCF_INTC_INTFRCH_INTFRC46 (0x4000)\r
+#define MCF_INTC_INTFRCH_INTFRC47 (0x8000)\r
+#define MCF_INTC_INTFRCH_INTFRC48 (0x10000)\r
+#define MCF_INTC_INTFRCH_INTFRC49 (0x20000)\r
+#define MCF_INTC_INTFRCH_INTFRC50 (0x40000)\r
+#define MCF_INTC_INTFRCH_INTFRC51 (0x80000)\r
+#define MCF_INTC_INTFRCH_INTFRC52 (0x100000)\r
+#define MCF_INTC_INTFRCH_INTFRC53 (0x200000)\r
+#define MCF_INTC_INTFRCH_INTFRC54 (0x400000)\r
+#define MCF_INTC_INTFRCH_INTFRC55 (0x800000)\r
+#define MCF_INTC_INTFRCH_INTFRC56 (0x1000000)\r
+#define MCF_INTC_INTFRCH_INTFRC57 (0x2000000)\r
+#define MCF_INTC_INTFRCH_INTFRC58 (0x4000000)\r
+#define MCF_INTC_INTFRCH_INTFRC59 (0x8000000)\r
+#define MCF_INTC_INTFRCH_INTFRC60 (0x10000000)\r
+#define MCF_INTC_INTFRCH_INTFRC61 (0x20000000)\r
+#define MCF_INTC_INTFRCH_INTFRC62 (0x40000000)\r
+#define MCF_INTC_INTFRCH_INTFRC63 (0x80000000)\r
+\r
+/* Bit definitions and macros for MCF_INTC_INTFRCL */\r
+#define MCF_INTC_INTFRCL_INTFRC1 (0x2)\r
+#define MCF_INTC_INTFRCL_INTFRC2 (0x4)\r
+#define MCF_INTC_INTFRCL_INTFRC3 (0x8)\r
+#define MCF_INTC_INTFRCL_INTFRC4 (0x10)\r
+#define MCF_INTC_INTFRCL_INTFRC5 (0x20)\r
+#define MCF_INTC_INTFRCL_INTFRC6 (0x40)\r
+#define MCF_INTC_INTFRCL_INTFRC7 (0x80)\r
+#define MCF_INTC_INTFRCL_INTFRC8 (0x100)\r
+#define MCF_INTC_INTFRCL_INTFRC9 (0x200)\r
+#define MCF_INTC_INTFRCL_INTFRC10 (0x400)\r
+#define MCF_INTC_INTFRCL_INTFRC11 (0x800)\r
+#define MCF_INTC_INTFRCL_INTFRC12 (0x1000)\r
+#define MCF_INTC_INTFRCL_INTFRC13 (0x2000)\r
+#define MCF_INTC_INTFRCL_INTFRC14 (0x4000)\r
+#define MCF_INTC_INTFRCL_INTFRC15 (0x8000)\r
+#define MCF_INTC_INTFRCL_INTFRC16 (0x10000)\r
+#define MCF_INTC_INTFRCL_INTFRC17 (0x20000)\r
+#define MCF_INTC_INTFRCL_INTFRC18 (0x40000)\r
+#define MCF_INTC_INTFRCL_INTFRC19 (0x80000)\r
+#define MCF_INTC_INTFRCL_INTFRC20 (0x100000)\r
+#define MCF_INTC_INTFRCL_INTFRC21 (0x200000)\r
+#define MCF_INTC_INTFRCL_INTFRC22 (0x400000)\r
+#define MCF_INTC_INTFRCL_INTFRC23 (0x800000)\r
+#define MCF_INTC_INTFRCL_INTFRC24 (0x1000000)\r
+#define MCF_INTC_INTFRCL_INTFRC25 (0x2000000)\r
+#define MCF_INTC_INTFRCL_INTFRC26 (0x4000000)\r
+#define MCF_INTC_INTFRCL_INTFRC27 (0x8000000)\r
+#define MCF_INTC_INTFRCL_INTFRC28 (0x10000000)\r
+#define MCF_INTC_INTFRCL_INTFRC29 (0x20000000)\r
+#define MCF_INTC_INTFRCL_INTFRC30 (0x40000000)\r
+#define MCF_INTC_INTFRCL_INTFRC31 (0x80000000)\r
+\r
+/* Bit definitions and macros for MCF_INTC_IRLR */\r
+#define MCF_INTC_IRLR_IRQ(x) (((x)&0x7F)<<0x1)\r
+\r
+/* Bit definitions and macros for MCF_INTC_IACKLPR */\r
+#define MCF_INTC_IACKLPR_PRI(x) (((x)&0xF)<<0)\r
+#define MCF_INTC_IACKLPR_LEVEL(x) (((x)&0x7)<<0x4)\r
+\r
+/* Bit definitions and macros for MCF_INTC_ICR */\r
+#define MCF_INTC_ICR_IP(x) (((x)&0x7)<<0)\r
+#define MCF_INTC_ICR_IL(x) (((x)&0x7)<<0x3)\r
+\r
+/* Bit definitions and macros for MCF_INTC_SWIACK */\r
+#define MCF_INTC_SWIACK_VECTOR(x) (((x)&0xFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_INTC_LIACK */\r
+#define MCF_INTC_LIACK_VECTOR(x) (((x)&0xFF)<<0)\r
+\r
+\r
+#endif /* __MCF5282_INTC_H__ */\r
--- /dev/null
+/* Coldfire C Header File\r
+ * Copyright Freescale Semiconductor Inc\r
+ * All rights reserved.\r
+ *\r
+ * 2007/03/19 Revision: 0.9\r
+ */\r
+\r
+#ifndef __MCF5282_PAD_H__\r
+#define __MCF5282_PAD_H__\r
+\r
+\r
+/*********************************************************************\r
+*\r
+* Common GPIO Registers\r
+*\r
+*********************************************************************/\r
+\r
+/* Register read/write macros */\r
+#define MCF_PAD_PBCDPAR (*(vuint8 *)(&__IPSBAR[0x100050]))\r
+#define MCF_PAD_PFPAR (*(vuint8 *)(&__IPSBAR[0x100051]))\r
+#define MCF_PAD_PEPAR (*(vuint16*)(&__IPSBAR[0x100052]))\r
+#define MCF_PAD_PJPAR (*(vuint8 *)(&__IPSBAR[0x100054]))\r
+#define MCF_PAD_PSDPAR (*(vuint8 *)(&__IPSBAR[0x100055]))\r
+#define MCF_PAD_PASPAR (*(vuint16*)(&__IPSBAR[0x100056]))\r
+#define MCF_PAD_PEHLPAR (*(vuint8 *)(&__IPSBAR[0x100058]))\r
+#define MCF_PAD_PQSPAR (*(vuint8 *)(&__IPSBAR[0x100059]))\r
+#define MCF_PAD_PTCPAR (*(vuint8 *)(&__IPSBAR[0x10005A]))\r
+#define MCF_PAD_PTDPAR (*(vuint8 *)(&__IPSBAR[0x10005B]))\r
+#define MCF_PAD_PUAPAR (*(vuint8 *)(&__IPSBAR[0x10005C]))\r
+\r
+\r
+/* Bit definitions and macros for MCF_PAD_PBCDPAR */\r
+#define MCF_PAD_PBCDPAR_PCDPA (0x40)\r
+#define MCF_PAD_PBCDPAR_PBPA (0x80)\r
+\r
+/* Bit definitions and macros for MCF_PAD_PFPAR */\r
+#define MCF_PAD_PFPAR_PFPA5 (0x20)\r
+#define MCF_PAD_PFPAR_PFPA6 (0x40)\r
+#define MCF_PAD_PFPAR_PFPA7 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_PAD_PEPAR */\r
+#define MCF_PAD_PEPAR_PEPA0(x) (((x)&0x3)<<0)\r
+#define MCF_PAD_PEPAR_PEPA0_GPIO (0)\r
+#define MCF_PAD_PEPAR_PEPA0_SYNCB (0x2)\r
+#define MCF_PAD_PEPAR_PEPA0_TIP (0x3)\r
+#define MCF_PAD_PEPAR_PEPA1(x) (((x)&0x3)<<0x2)\r
+#define MCF_PAD_PEPAR_PEPA1_GPIO (0)\r
+#define MCF_PAD_PEPAR_PEPA1_SYNCA (0x8)\r
+#define MCF_PAD_PEPAR_PEPA1_TS (0xC)\r
+#define MCF_PAD_PEPAR_PEPA2 (0x10)\r
+#define MCF_PAD_PEPAR_PEPA3 (0x40)\r
+#define MCF_PAD_PEPAR_PEPA4 (0x100)\r
+#define MCF_PAD_PEPAR_PEPA5 (0x400)\r
+#define MCF_PAD_PEPAR_PEPA6 (0x1000)\r
+#define MCF_PAD_PEPAR_PEPA7 (0x4000)\r
+\r
+/* Bit definitions and macros for MCF_PAD_PJPAR */\r
+#define MCF_PAD_PJPAR_PJPA0 (0x1)\r
+#define MCF_PAD_PJPAR_PJPA1 (0x2)\r
+#define MCF_PAD_PJPAR_PJPA2 (0x4)\r
+#define MCF_PAD_PJPAR_PJPA3 (0x8)\r
+#define MCF_PAD_PJPAR_PJPA4 (0x10)\r
+#define MCF_PAD_PJPAR_PJPA5 (0x20)\r
+#define MCF_PAD_PJPAR_PJPA6 (0x40)\r
+#define MCF_PAD_PJPAR_PJPA7 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_PAD_PSDPAR */\r
+#define MCF_PAD_PSDPAR_PSDPA (0x80)\r
+\r
+/* Bit definitions and macros for MCF_PAD_PASPAR */\r
+#define MCF_PAD_PASPAR_PASPA0(x) (((x)&0x3)<<0)\r
+#define MCF_PAD_PASPAR_PASPA0_GPIO (0)\r
+#define MCF_PAD_PASPAR_PASPA0_UTXD2 (0x2)\r
+#define MCF_PAD_PASPAR_PASPA0_SCL (0x3)\r
+#define MCF_PAD_PASPAR_PASPA1(x) (((x)&0x3)<<0x2)\r
+#define MCF_PAD_PASPAR_PASPA1_GPIO (0)\r
+#define MCF_PAD_PASPAR_PASPA1_URXD2 (0x8)\r
+#define MCF_PAD_PASPAR_PASPA1_SDA (0xC)\r
+#define MCF_PAD_PASPAR_PASPA2(x) (((x)&0x3)<<0x4)\r
+#define MCF_PAD_PASPAR_PASPA2_GPIO (0)\r
+#define MCF_PAD_PASPAR_PASPA2_UTXD2 (0x20)\r
+#define MCF_PAD_PASPAR_PASPA2_CANTX (0x30)\r
+#define MCF_PAD_PASPAR_PASPA3(x) (((x)&0x3)<<0x6)\r
+#define MCF_PAD_PASPAR_PASPA3_GPIO (0)\r
+#define MCF_PAD_PASPAR_PASPA3_URXD2 (0x80)\r
+#define MCF_PAD_PASPAR_PASPA3_CANRX (0xC0)\r
+#define MCF_PAD_PASPAR_PASPA4(x) (((x)&0x3)<<0x8)\r
+#define MCF_PAD_PASPAR_PASPA4_GPIO (0)\r
+#define MCF_PAD_PASPAR_PASPA4_UTXD2 (0x200)\r
+#define MCF_PAD_PASPAR_PASPA4_EMDC (0x300)\r
+#define MCF_PAD_PASPAR_PASPA5(x) (((x)&0x3)<<0xA)\r
+#define MCF_PAD_PASPAR_PASPA5_GPIO (0)\r
+#define MCF_PAD_PASPAR_PASPA5_URXD2 (0x800)\r
+#define MCF_PAD_PASPAR_PASPA5_EMDIO (0xC00)\r
+\r
+/* Bit definitions and macros for MCF_PAD_PEHLPAR */\r
+#define MCF_PAD_PEHLPAR_PELPA (0x40)\r
+#define MCF_PAD_PEHLPAR_PEHPA (0x80)\r
+\r
+/* Bit definitions and macros for MCF_PAD_PQSPAR */\r
+#define MCF_PAD_PQSPAR_PQSPA0 (0x1)\r
+#define MCF_PAD_PQSPAR_PQSPA1 (0x2)\r
+#define MCF_PAD_PQSPAR_PQSPA2 (0x4)\r
+#define MCF_PAD_PQSPAR_PQSPA3 (0x8)\r
+#define MCF_PAD_PQSPAR_PQSPA4 (0x10)\r
+#define MCF_PAD_PQSPAR_PQSPA5 (0x20)\r
+#define MCF_PAD_PQSPAR_PQSPA6 (0x40)\r
+\r
+/* Bit definitions and macros for MCF_PAD_PTCPAR */\r
+#define MCF_PAD_PTCPAR_PTCPA0(x) (((x)&0x3)<<0)\r
+#define MCF_PAD_PTCPAR_PTCPA0_GPIO (0)\r
+#define MCF_PAD_PTCPAR_PTCPA0_UCTS0 (0x1)\r
+#define MCF_PAD_PTCPAR_PTCPA0_UCTS1 (0x2)\r
+#define MCF_PAD_PTCPAR_PTCPA0_TOUT2 (0x3)\r
+#define MCF_PAD_PTCPAR_PTCPA1(x) (((x)&0x3)<<0x2)\r
+#define MCF_PAD_PTCPAR_PTCPA1_GPIO (0)\r
+#define MCF_PAD_PTCPAR_PTCPA1_UCTS0 (0x4)\r
+#define MCF_PAD_PTCPAR_PTCPA1_UCTS1 (0x8)\r
+#define MCF_PAD_PTCPAR_PTCPA1_TIN2 (0xC)\r
+#define MCF_PAD_PTCPAR_PTCPA2(x) (((x)&0x3)<<0x4)\r
+#define MCF_PAD_PTCPAR_PTCPA2_GPIO (0)\r
+#define MCF_PAD_PTCPAR_PTCPA2_URTS0 (0x10)\r
+#define MCF_PAD_PTCPAR_PTCPA2_URTS1 (0x20)\r
+#define MCF_PAD_PTCPAR_PTCPA2_TOUT3 (0x30)\r
+#define MCF_PAD_PTCPAR_PTCPA3(x) (((x)&0x3)<<0x6)\r
+#define MCF_PAD_PTCPAR_PTCPA3_GPIO (0)\r
+#define MCF_PAD_PTCPAR_PTCPA3_URTS0 (0x40)\r
+#define MCF_PAD_PTCPAR_PTCPA3_URTS1 (0x80)\r
+#define MCF_PAD_PTCPAR_PTCPA3_TIN3 (0xC0)\r
+\r
+/* Bit definitions and macros for MCF_PAD_PTDPAR */\r
+#define MCF_PAD_PTDPAR_PTDPA0(x) (((x)&0x3)<<0)\r
+#define MCF_PAD_PTDPAR_PTDPA0_GPIO (0)\r
+#define MCF_PAD_PTDPAR_PTDPA0_UCTS0 (0x1)\r
+#define MCF_PAD_PTDPAR_PTDPA0_UCTS1 (0x2)\r
+#define MCF_PAD_PTDPAR_PTDPA0_TOUT0 (0x3)\r
+#define MCF_PAD_PTDPAR_PTDPA1(x) (((x)&0x3)<<0x2)\r
+#define MCF_PAD_PTDPAR_PTDPA2_GPIO (0)\r
+#define MCF_PAD_PTDPAR_PTDPA2_UCTS0 (0x4)\r
+#define MCF_PAD_PTDPAR_PTDPA2_UCTS1 (0x8)\r
+#define MCF_PAD_PTDPAR_PTDPA2_TIN0 (0xC)\r
+#define MCF_PAD_PTDPAR_PTDPA2(x) (((x)&0x3)<<0x4)\r
+#define MCF_PAD_PTDPAR_PTDPA2_URTS0 (0x10)\r
+#define MCF_PAD_PTDPAR_PTDPA2_URTS1 (0x20)\r
+#define MCF_PAD_PTDPAR_PTDPA2_TOUT1 (0x30)\r
+#define MCF_PAD_PTDPAR_PTDPA3(x) (((x)&0x3)<<0x6)\r
+#define MCF_PAD_PTDPAR_PTDPA3_GPIO (0)\r
+#define MCF_PAD_PTDPAR_PTDPA3_URTS0 (0x40)\r
+#define MCF_PAD_PTDPAR_PTDPA3_URTS1 (0x80)\r
+#define MCF_PAD_PTDPAR_PTDPA3_TIN1 (0xC0)\r
+\r
+/* Bit definitions and macros for MCF_PAD_PUAPAR */\r
+#define MCF_PAD_PUAPAR_PUAPA0 (0x1)\r
+#define MCF_PAD_PUAPAR_PUAPA1 (0x2)\r
+#define MCF_PAD_PUAPAR_PUAPA2 (0x4)\r
+#define MCF_PAD_PUAPAR_PUAPA3 (0x8)\r
+\r
+\r
+#endif /* __MCF5282_PAD_H__ */\r
--- /dev/null
+/* Coldfire C Header File\r
+ * Copyright Freescale Semiconductor Inc\r
+ * All rights reserved.\r
+ *\r
+ * 2007/03/19 Revision: 0.9\r
+ */\r
+\r
+#ifndef __MCF5282_PIT_H__\r
+#define __MCF5282_PIT_H__\r
+\r
+\r
+/*********************************************************************\r
+*\r
+* Programmable Interrupt Timer (PIT)\r
+*\r
+*********************************************************************/\r
+\r
+/* Register read/write macros */\r
+#define MCF_PIT0_PCSR (*(vuint16*)(&__IPSBAR[0x150000]))\r
+#define MCF_PIT0_PMR (*(vuint16*)(&__IPSBAR[0x150002]))\r
+#define MCF_PIT0_PCNTR (*(vuint16*)(&__IPSBAR[0x150004]))\r
+\r
+#define MCF_PIT1_PCSR (*(vuint16*)(&__IPSBAR[0x160000]))\r
+#define MCF_PIT1_PMR (*(vuint16*)(&__IPSBAR[0x160002]))\r
+#define MCF_PIT1_PCNTR (*(vuint16*)(&__IPSBAR[0x160004]))\r
+\r
+#define MCF_PIT2_PCSR (*(vuint16*)(&__IPSBAR[0x170000]))\r
+#define MCF_PIT2_PMR (*(vuint16*)(&__IPSBAR[0x170002]))\r
+#define MCF_PIT2_PCNTR (*(vuint16*)(&__IPSBAR[0x170004]))\r
+\r
+#define MCF_PIT3_PCSR (*(vuint16*)(&__IPSBAR[0x180000]))\r
+#define MCF_PIT3_PMR (*(vuint16*)(&__IPSBAR[0x180002]))\r
+#define MCF_PIT3_PCNTR (*(vuint16*)(&__IPSBAR[0x180004]))\r
+\r
+#define MCF_PIT_PCSR(x) (*(vuint16*)(&__IPSBAR[0x150000 + ((x)*0x10000)]))\r
+#define MCF_PIT_PMR(x) (*(vuint16*)(&__IPSBAR[0x150002 + ((x)*0x10000)]))\r
+#define MCF_PIT_PCNTR(x) (*(vuint16*)(&__IPSBAR[0x150004 + ((x)*0x10000)]))\r
+\r
+\r
+/* Bit definitions and macros for MCF_PIT_PCSR */\r
+#define MCF_PIT_PCSR_EN (0x1)\r
+#define MCF_PIT_PCSR_RLD (0x2)\r
+#define MCF_PIT_PCSR_PIF (0x4)\r
+#define MCF_PIT_PCSR_PIE (0x8)\r
+#define MCF_PIT_PCSR_OVW (0x10)\r
+#define MCF_PIT_PCSR_HALTED (0x20)\r
+#define MCF_PIT_PCSR_DOZE (0x40)\r
+#define MCF_PIT_PCSR_PRE(x) (((x)&0xF)<<0x8)\r
+\r
+/* Bit definitions and macros for MCF_PIT_PMR */\r
+#define MCF_PIT_PMR_PM(x) (((x)&0xFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_PIT_PCNTR */\r
+#define MCF_PIT_PCNTR_PC(x) (((x)&0xFFFF)<<0)\r
+\r
+\r
+#endif /* __MCF5282_PIT_H__ */\r
--- /dev/null
+/* Coldfire C Header File\r
+ * Copyright Freescale Semiconductor Inc\r
+ * All rights reserved.\r
+ *\r
+ * 2007/03/19 Revision: 0.9\r
+ */\r
+\r
+#ifndef __MCF5282_PMM_H__\r
+#define __MCF5282_PMM_H__\r
+\r
+\r
+/*********************************************************************\r
+*\r
+* Power Management (PMM)\r
+*\r
+*********************************************************************/\r
+\r
+/* Register read/write macros */\r
+#define MCF_PMM_LPICR (*(vuint8 *)(&__IPSBAR[0x12]))\r
+#define MCF_PMM_LPCR (*(vuint8 *)(&__IPSBAR[0x110007]))\r
+\r
+\r
+/* Bit definitions and macros for MCF_PMM_LPICR */\r
+#define MCF_PMM_LPICR_XLPM_IPL(x) (((x)&0x7)<<0x4)\r
+#define MCF_PMM_LPICR_ENBSTOP (0x80)\r
+\r
+/* Bit definitions and macros for MCF_PMM_LPCR */\r
+#define MCF_PMM_LPCR_LVDSE (0x2)\r
+#define MCF_PMM_LPCR_STPMD(x) (((x)&0x3)<<0x3)\r
+#define MCF_PMM_LPCR_STPMD_SYS_DISABLED (0)\r
+#define MCF_PMM_LPCR_STPMD_SYS_CLKOUT_DISABLED (0x8)\r
+#define MCF_PMM_LPCR_STPMD_ONLY_OSC_ENABLED (0x10)\r
+#define MCF_PMM_LPCR_STPMD_ALL_DISABLED (0x18)\r
+#define MCF_PMM_LPCR_LPMD(x) (((x)&0x3)<<0x6)\r
+#define MCF_PMM_LPCR_LPMD_RUN (0)\r
+#define MCF_PMM_LPCR_LPMD_DOZE (0x40)\r
+#define MCF_PMM_LPCR_LPMD_WAIT (0x80)\r
+#define MCF_PMM_LPCR_LPMD_STOP (0xC0)\r
+\r
+\r
+#endif /* __MCF5282_PMM_H__ */\r
--- /dev/null
+/* Coldfire C Header File\r
+ * Copyright Freescale Semiconductor Inc\r
+ * All rights reserved.\r
+ *\r
+ * 2007/03/19 Revision: 0.9\r
+ */\r
+\r
+#ifndef __MCF5282_QADC_H__\r
+#define __MCF5282_QADC_H__\r
+\r
+\r
+/*********************************************************************\r
+*\r
+* Queued Analog-to-Digital Converter (QADC)\r
+*\r
+*********************************************************************/\r
+\r
+/* Register read/write macros */\r
+#define MCF_QADC_QADCMCR (*(vuint16*)(&__IPSBAR[0x190000]))\r
+#define MCF_QADC_PORTQA (*(vuint8 *)(&__IPSBAR[0x190006]))\r
+#define MCF_QADC_PORTQB (*(vuint8 *)(&__IPSBAR[0x190007]))\r
+#define MCF_QADC_DDRQA (*(vuint8 *)(&__IPSBAR[0x190008]))\r
+#define MCF_QADC_DDRQB (*(vuint8 *)(&__IPSBAR[0x190009]))\r
+#define MCF_QADC_QACR0 (*(vuint16*)(&__IPSBAR[0x19000A]))\r
+#define MCF_QADC_QACR1 (*(vuint16*)(&__IPSBAR[0x19000C]))\r
+#define MCF_QADC_QACR2 (*(vuint16*)(&__IPSBAR[0x19000E]))\r
+#define MCF_QADC_QASR0 (*(vuint16*)(&__IPSBAR[0x190010]))\r
+#define MCF_QADC_QASR1 (*(vuint16*)(&__IPSBAR[0x190012]))\r
+\r
+/* Other macros */\r
+#define MCF_QADC_CCW(x) (*(vuint16*)(&__IPSBAR[0x190200 + (x*2)]))\r
+#define MCF_QADC_CCW_CHAN(x) (((x)&0x3F)<<0)\r
+#define MCF_QADC_CCW_IST(x) (((x)&0x3)<<0x6)\r
+#define MCF_QADC_CCW_IST_QCLK2 (0)\r
+#define MCF_QADC_CCW_IST_QCLK4 (0x40)\r
+#define MCF_QADC_CCW_IST_QCLK8 (0x80)\r
+#define MCF_QADC_CCW_IST_QCLK16 (0xC0)\r
+#define MCF_QADC_CCW_BYP (0x100)\r
+#define MCF_QADC_CCW_P (0x200)\r
+#define MCF_QADC_RJURR(x) (*(vuint16*)(&__IPSBAR[0x190280 + (x*2)]))\r
+#define MCF_QADC_LJSRR(x) (*(vuint16*)(&__IPSBAR[0x190300 + (x*2)]))\r
+#define MCF_QADC_LJURR(x) (*(vuint16*)(&__IPSBAR[0x190380 + (x*2)]))\r
+\r
+\r
+/* Bit definitions and macros for MCF_QADC_QADCMCR */\r
+#define MCF_QADC_QADCMCR_SUPV (0x80)\r
+#define MCF_QADC_QADCMCR_QDBG (0x4000)\r
+#define MCF_QADC_QADCMCR_QSTOP (0x8000)\r
+\r
+/* Bit definitions and macros for MCF_QADC_PORTQA */\r
+#define MCF_QADC_PORTQA_PQA0 (0x1)\r
+#define MCF_QADC_PORTQA_PQA1 (0x2)\r
+#define MCF_QADC_PORTQA_PQA2 (0x8)\r
+#define MCF_QADC_PORTQA_PQA3 (0x10)\r
+\r
+/* Bit definitions and macros for MCF_QADC_PORTQB */\r
+#define MCF_QADC_PORTQB_PQB0 (0x1)\r
+#define MCF_QADC_PORTQB_PQB1 (0x2)\r
+#define MCF_QADC_PORTQB_PQB2 (0x4)\r
+#define MCF_QADC_PORTQB_PQB3 (0x8)\r
+\r
+/* Bit definitions and macros for MCF_QADC_DDRQA */\r
+#define MCF_QADC_DDRQA_DDQA0 (0x1)\r
+#define MCF_QADC_DDRQA_DDQA1 (0x2)\r
+#define MCF_QADC_DDRQA_DDQA2 (0x8)\r
+#define MCF_QADC_DDRQA_DDQA3 (0x10)\r
+\r
+/* Bit definitions and macros for MCF_QADC_DDRQB */\r
+#define MCF_QADC_DDRQB_DDQB0 (0x1)\r
+#define MCF_QADC_DDRQB_DDQB1 (0x2)\r
+#define MCF_QADC_DDRQB_DDQB2 (0x4)\r
+#define MCF_QADC_DDRQB_DDQB3 (0x8)\r
+\r
+/* Bit definitions and macros for MCF_QADC_QACR0 */\r
+#define MCF_QADC_QACR0_QPR(x) (((x)&0x7F)<<0)\r
+#define MCF_QADC_QACR0_TRG (0x1000)\r
+#define MCF_QADC_QACR0_MUX (0x8000)\r
+\r
+/* Bit definitions and macros for MCF_QADC_QACR1 */\r
+#define MCF_QADC_QACR1_MQ1(x) (((x)&0x1F)<<0x8)\r
+#define MCF_QADC_QACR1_SSE1 (0x2000)\r
+#define MCF_QADC_QACR1_PIE1 (0x4000)\r
+#define MCF_QADC_QACR1_CIE1 (0x8000)\r
+\r
+/* Bit definitions and macros for MCF_QADC_QACR2 */\r
+#define MCF_QADC_QACR2_BQ2(x) (((x)&0x7F)<<0)\r
+#define MCF_QADC_QACR2_RESUME (0x80)\r
+#define MCF_QADC_QACR2_MQ2(x) (((x)&0x1F)<<0x8)\r
+#define MCF_QADC_QACR2_SSE2 (0x2000)\r
+#define MCF_QADC_QACR2_PIE2 (0x4000)\r
+#define MCF_QADC_QACR2_CIE2 (0x8000)\r
+\r
+/* Bit definitions and macros for MCF_QADC_QASR0 */\r
+#define MCF_QADC_QASR0_CWP(x) (((x)&0x3F)<<0)\r
+#define MCF_QADC_QASR0_QS(x) (((x)&0xF)<<0x6)\r
+#define MCF_QADC_QASR0_TOR2 (0x400)\r
+#define MCF_QADC_QASR0_TOR1 (0x800)\r
+#define MCF_QADC_QASR0_PF2 (0x1000)\r
+#define MCF_QADC_QASR0_CF2 (0x2000)\r
+#define MCF_QADC_QASR0_PF1 (0x4000)\r
+#define MCF_QADC_QASR0_CF1 (0x8000)\r
+\r
+/* Bit definitions and macros for MCF_QADC_QASR1 */\r
+#define MCF_QADC_QASR1_CWPQ2(x) (((x)&0x3F)<<0)\r
+#define MCF_QADC_QASR1_CWPQ1(x) (((x)&0x3F)<<0x8)\r
+\r
+\r
+#endif /* __MCF5282_QADC_H__ */\r
--- /dev/null
+/* Coldfire C Header File\r
+ * Copyright Freescale Semiconductor Inc\r
+ * All rights reserved.\r
+ *\r
+ * 2007/03/19 Revision: 0.9\r
+ */\r
+\r
+#ifndef __MCF5282_QSPI_H__\r
+#define __MCF5282_QSPI_H__\r
+\r
+\r
+/*********************************************************************\r
+*\r
+* Queued Serial Peripheral Interface (QSPI)\r
+*\r
+*********************************************************************/\r
+\r
+/* Register read/write macros */\r
+#define MCF_QSPI_QMR (*(vuint16*)(&__IPSBAR[0x340]))\r
+#define MCF_QSPI_QDLYR (*(vuint16*)(&__IPSBAR[0x344]))\r
+#define MCF_QSPI_QWR (*(vuint16*)(&__IPSBAR[0x348]))\r
+#define MCF_QSPI_QIR (*(vuint16*)(&__IPSBAR[0x34C]))\r
+#define MCF_QSPI_QAR (*(vuint16*)(&__IPSBAR[0x350]))\r
+#define MCF_QSPI_QDR (*(vuint16*)(&__IPSBAR[0x354]))\r
+\r
+\r
+/* Bit definitions and macros for MCF_QSPI_QMR */\r
+#define MCF_QSPI_QMR_BAUD(x) (((x)&0xFF)<<0)\r
+#define MCF_QSPI_QMR_CPHA (0x100)\r
+#define MCF_QSPI_QMR_CPOL (0x200)\r
+#define MCF_QSPI_QMR_BITS(x) (((x)&0xF)<<0xA)\r
+#define MCF_QSPI_QMR_DOHIE (0x4000)\r
+#define MCF_QSPI_QMR_MSTR (0x8000)\r
+\r
+/* Bit definitions and macros for MCF_QSPI_QDLYR */\r
+#define MCF_QSPI_QDLYR_DTL(x) (((x)&0xFF)<<0)\r
+#define MCF_QSPI_QDLYR_QCD(x) (((x)&0x7F)<<0x8)\r
+#define MCF_QSPI_QDLYR_SPE (0x8000)\r
+\r
+/* Bit definitions and macros for MCF_QSPI_QWR */\r
+#define MCF_QSPI_QWR_NEWQP(x) (((x)&0xF)<<0)\r
+#define MCF_QSPI_QWR_CPTQP(x) (((x)&0xF)<<0x4)\r
+#define MCF_QSPI_QWR_ENDQP(x) (((x)&0xF)<<0x8)\r
+#define MCF_QSPI_QWR_CSIV (0x1000)\r
+#define MCF_QSPI_QWR_WRTO (0x2000)\r
+#define MCF_QSPI_QWR_WREN (0x4000)\r
+#define MCF_QSPI_QWR_HALT (0x8000)\r
+\r
+/* Bit definitions and macros for MCF_QSPI_QIR */\r
+#define MCF_QSPI_QIR_SPIF (0x1)\r
+#define MCF_QSPI_QIR_ABRT (0x4)\r
+#define MCF_QSPI_QIR_WCEF (0x8)\r
+#define MCF_QSPI_QIR_SPIFE (0x100)\r
+#define MCF_QSPI_QIR_ABRTE (0x400)\r
+#define MCF_QSPI_QIR_WCEFE (0x800)\r
+#define MCF_QSPI_QIR_ABRTL (0x1000)\r
+#define MCF_QSPI_QIR_ABRTB (0x4000)\r
+#define MCF_QSPI_QIR_WCEFB (0x8000)\r
+\r
+/* Bit definitions and macros for MCF_QSPI_QAR */\r
+#define MCF_QSPI_QAR_ADDR(x) (((x)&0x3F)<<0)\r
+#define MCF_QSPI_QAR_TRANS (0)\r
+#define MCF_QSPI_QAR_RECV (0x10)\r
+#define MCF_QSPI_QAR_CMD (0x20)\r
+\r
+/* Bit definitions and macros for MCF_QSPI_QDR */\r
+#define MCF_QSPI_QDR_DATA(x) (((x)&0xFFFF)<<0)\r
+#define MCF_QSPI_QDR_CONT (0x8000)\r
+#define MCF_QSPI_QDR_BITSE (0x4000)\r
+#define MCF_QSPI_QDR_DT (0x2000)\r
+#define MCF_QSPI_QDR_DSCK (0x1000)\r
+#define MCF_QSPI_QDR_QSPI_CS3 (0x800)\r
+#define MCF_QSPI_QDR_QSPI_CS2 (0x400)\r
+#define MCF_QSPI_QDR_QSPI_CS1 (0x200)\r
+#define MCF_QSPI_QDR_QSPI_CS0 (0x100)\r
+\r
+\r
+#endif /* __MCF5282_QSPI_H__ */\r
--- /dev/null
+/* Coldfire C Header File\r
+ * Copyright Freescale Semiconductor Inc\r
+ * All rights reserved.\r
+ *\r
+ * 2007/03/19 Revision: 0.9\r
+ */\r
+\r
+#ifndef __MCF5282_RCM_H__\r
+#define __MCF5282_RCM_H__\r
+\r
+\r
+/*********************************************************************\r
+*\r
+* Reset Controller Module (RCM)\r
+*\r
+*********************************************************************/\r
+\r
+/* Register read/write macros */\r
+#define MCF_RCM_RCR (*(vuint8 *)(&__IPSBAR[0x110000]))\r
+#define MCF_RCM_RSR (*(vuint8 *)(&__IPSBAR[0x110001]))\r
+\r
+\r
+/* Bit definitions and macros for MCF_RCM_RCR */\r
+#define MCF_RCM_RCR_LVDE (0x1)\r
+#define MCF_RCM_RCR_LVDRE (0x4)\r
+#define MCF_RCM_RCR_LVDIE (0x8)\r
+#define MCF_RCM_RCR_LVDF (0x10)\r
+#define MCF_RCM_RCR_FRCRSTOUT (0x40)\r
+#define MCF_RCM_RCR_SOFTRST (0x80)\r
+\r
+/* Bit definitions and macros for MCF_RCM_RSR */\r
+#define MCF_RCM_RSR_LOL (0x1)\r
+#define MCF_RCM_RSR_LOC (0x2)\r
+#define MCF_RCM_RSR_EXT (0x4)\r
+#define MCF_RCM_RSR_POR (0x8)\r
+#define MCF_RCM_RSR_WDR (0x10)\r
+#define MCF_RCM_RSR_SOFT (0x20)\r
+#define MCF_RCM_RSR_LVD (0x40)\r
+\r
+\r
+#endif /* __MCF5282_RCM_H__ */\r
--- /dev/null
+/* Coldfire C Header File\r
+ * Copyright Freescale Semiconductor Inc\r
+ * All rights reserved.\r
+ *\r
+ * 2007/03/19 Revision: 0.9\r
+ */\r
+\r
+#ifndef __MCF5282_SCM_H__\r
+#define __MCF5282_SCM_H__\r
+\r
+\r
+/*********************************************************************\r
+*\r
+* System Control Module (SCM)\r
+*\r
+*********************************************************************/\r
+\r
+/* Register read/write macros */\r
+#define MCF_SCM_RAMBAR (*(vuint32*)(&__IPSBAR[0x8]))\r
+#define MCF_SCM_CRSR (*(vuint8 *)(&__IPSBAR[0x10]))\r
+#define MCF_SCM_CWCR (*(vuint8 *)(&__IPSBAR[0x11]))\r
+#define MCF_SCM_CWSR (*(vuint8 *)(&__IPSBAR[0x13]))\r
+#define MCF_SCM_DMAREQC (*(vuint32*)(&__IPSBAR[0x14]))\r
+#define MCF_SCM_MPARK (*(vuint32*)(&__IPSBAR[0x1C]))\r
+#define MCF_SCM_MPR (*(vuint8 *)(&__IPSBAR[0x20]))\r
+#define MCF_SCM_PACR0 (*(vuint8 *)(&__IPSBAR[0x24]))\r
+#define MCF_SCM_PACR1 (*(vuint8 *)(&__IPSBAR[0x25]))\r
+#define MCF_SCM_PACR2 (*(vuint8 *)(&__IPSBAR[0x26]))\r
+#define MCF_SCM_PACR3 (*(vuint8 *)(&__IPSBAR[0x27]))\r
+#define MCF_SCM_PACR4 (*(vuint8 *)(&__IPSBAR[0x28]))\r
+#define MCF_SCM_PACR5 (*(vuint8 *)(&__IPSBAR[0x2A]))\r
+#define MCF_SCM_PACR6 (*(vuint8 *)(&__IPSBAR[0x2B]))\r
+#define MCF_SCM_PACR7 (*(vuint8 *)(&__IPSBAR[0x2C]))\r
+#define MCF_SCM_PACR8 (*(vuint8 *)(&__IPSBAR[0x2E]))\r
+#define MCF_SCM_GPACR0 (*(vuint8 *)(&__IPSBAR[0x30]))\r
+#define MCF_SCM_GPACR1 (*(vuint8 *)(&__IPSBAR[0x31]))\r
+#define MCF_SCM_GPACR(x) (*(vuint8 *)(&__IPSBAR[0x30 + ((x)*0x1)]))\r
+\r
+/* Other macros */\r
+#define MCF_SCM_IPSBAR (*(vuint32*)(&__IPSBAR[0x0]))\r
+#define MCF_SCM_IPSBAR_V (0x1)\r
+#define MCF_SCM_IPSBAR_BA(x) ((x)&0xC0000000)\r
+\r
+\r
+/* Bit definitions and macros for MCF_SCM_RAMBAR */\r
+#define MCF_SCM_RAMBAR_BDE (0x200)\r
+#define MCF_SCM_RAMBAR_BA(x) ((x)&0xFFFF0000)\r
+\r
+/* Bit definitions and macros for MCF_SCM_CRSR */\r
+#define MCF_SCM_CRSR_CWDR (0x20)\r
+#define MCF_SCM_CRSR_EXT (0x80)\r
+\r
+/* Bit definitions and macros for MCF_SCM_CWCR */\r
+#define MCF_SCM_CWCR_CWTIF (0x1)\r
+#define MCF_SCM_CWCR_CWTAVAL (0x2)\r
+#define MCF_SCM_CWCR_CWTA (0x4)\r
+#define MCF_SCM_CWCR_CWT(x) (((x)&0x7)<<0x3)\r
+#define MCF_SCM_CWCR_CWT_2_9 (0)\r
+#define MCF_SCM_CWCR_CWT_2_11 (0x8)\r
+#define MCF_SCM_CWCR_CWT_2_13 (0x10)\r
+#define MCF_SCM_CWCR_CWT_2_15 (0x18)\r
+#define MCF_SCM_CWCR_CWT_2_19 (0x20)\r
+#define MCF_SCM_CWCR_CWT_2_23 (0x28)\r
+#define MCF_SCM_CWCR_CWT_2_27 (0x30)\r
+#define MCF_SCM_CWCR_CWT_2_31 (0x38)\r
+#define MCF_SCM_CWCR_CWRI (0x40)\r
+#define MCF_SCM_CWCR_CWE (0x80)\r
+\r
+/* Bit definitions and macros for MCF_SCM_CWSR */\r
+#define MCF_SCM_CWSR_CWSR(x) (((x)&0xFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_SCM_DMAREQC */\r
+#define MCF_SCM_DMAREQC_DMAC0(x) (((x)&0xF)<<0)\r
+#define MCF_SCM_DMAREQC_DMAC1(x) (((x)&0xF)<<0x4)\r
+#define MCF_SCM_DMAREQC_DMAC2(x) (((x)&0xF)<<0x8)\r
+#define MCF_SCM_DMAREQC_DMAC3(x) (((x)&0xF)<<0xC)\r
+\r
+/* Bit definitions and macros for MCF_SCM_MPARK */\r
+#define MCF_SCM_MPARK_LCKOUT_TIME(x) (((x)&0xF)<<0x8)\r
+#define MCF_SCM_MPARK_PRKLAST (0x1000)\r
+#define MCF_SCM_MPARK_TIMEOUT (0x2000)\r
+#define MCF_SCM_MPARK_FIXED (0x4000)\r
+#define MCF_SCM_MPARK_M1_PRTY(x) (((x)&0x3)<<0x10)\r
+#define MCF_SCM_MPARK_M0_PRTY(x) (((x)&0x3)<<0x12)\r
+#define MCF_SCM_MPARK_M2_PRTY(x) (((x)&0x3)<<0x14)\r
+#define MCF_SCM_MPARK_M3_PRTY(x) (((x)&0x3)<<0x16)\r
+#define MCF_SCM_MPARK_BCR24BIT (0x1000000)\r
+#define MCF_SCM_MPARK_M2_P_EN (0x2000000)\r
+\r
+/* Bit definitions and macros for MCF_SCM_MPR */\r
+#define MCF_SCM_MPR_MPR(x) (((x)&0xF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_SCM_PACR0 */\r
+#define MCF_SCM_PACR0_ACCESS_CTRL0(x) (((x)&0x7)<<0)\r
+#define MCF_SCM_PACR0_LOCK0 (0x8)\r
+#define MCF_SCM_PACR0_ACCESS_CTRL1(x) (((x)&0x7)<<0x4)\r
+#define MCF_SCM_PACR0_LOCK1 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_SCM_PACR1 */\r
+#define MCF_SCM_PACR1_ACCESS_CTRL0(x) (((x)&0x7)<<0)\r
+#define MCF_SCM_PACR1_LOCK0 (0x8)\r
+#define MCF_SCM_PACR1_ACCESS_CTRL1(x) (((x)&0x7)<<0x4)\r
+#define MCF_SCM_PACR1_LOCK1 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_SCM_PACR2 */\r
+#define MCF_SCM_PACR2_ACCESS_CTRL0(x) (((x)&0x7)<<0)\r
+#define MCF_SCM_PACR2_LOCK0 (0x8)\r
+#define MCF_SCM_PACR2_ACCESS_CTRL1(x) (((x)&0x7)<<0x4)\r
+#define MCF_SCM_PACR2_LOCK1 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_SCM_PACR3 */\r
+#define MCF_SCM_PACR3_ACCESS_CTRL0(x) (((x)&0x7)<<0)\r
+#define MCF_SCM_PACR3_LOCK0 (0x8)\r
+#define MCF_SCM_PACR3_ACCESS_CTRL1(x) (((x)&0x7)<<0x4)\r
+#define MCF_SCM_PACR3_LOCK1 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_SCM_PACR4 */\r
+#define MCF_SCM_PACR4_ACCESS_CTRL0(x) (((x)&0x7)<<0)\r
+#define MCF_SCM_PACR4_LOCK0 (0x8)\r
+#define MCF_SCM_PACR4_ACCESS_CTRL1(x) (((x)&0x7)<<0x4)\r
+#define MCF_SCM_PACR4_LOCK1 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_SCM_PACR5 */\r
+#define MCF_SCM_PACR5_ACCESS_CTRL0(x) (((x)&0x7)<<0)\r
+#define MCF_SCM_PACR5_LOCK0 (0x8)\r
+#define MCF_SCM_PACR5_ACCESS_CTRL1(x) (((x)&0x7)<<0x4)\r
+#define MCF_SCM_PACR5_LOCK1 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_SCM_PACR6 */\r
+#define MCF_SCM_PACR6_ACCESS_CTRL0(x) (((x)&0x7)<<0)\r
+#define MCF_SCM_PACR6_LOCK0 (0x8)\r
+#define MCF_SCM_PACR6_ACCESS_CTRL1(x) (((x)&0x7)<<0x4)\r
+#define MCF_SCM_PACR6_LOCK1 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_SCM_PACR7 */\r
+#define MCF_SCM_PACR7_ACCESS_CTRL0(x) (((x)&0x7)<<0)\r
+#define MCF_SCM_PACR7_LOCK0 (0x8)\r
+#define MCF_SCM_PACR7_ACCESS_CTRL1(x) (((x)&0x7)<<0x4)\r
+#define MCF_SCM_PACR7_LOCK1 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_SCM_PACR8 */\r
+#define MCF_SCM_PACR8_ACCESS_CTRL0(x) (((x)&0x7)<<0)\r
+#define MCF_SCM_PACR8_LOCK0 (0x8)\r
+#define MCF_SCM_PACR8_ACCESS_CTRL1(x) (((x)&0x7)<<0x4)\r
+#define MCF_SCM_PACR8_LOCK1 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_SCM_GPACR */\r
+#define MCF_SCM_GPACR_ACCESS_CTRL(x) (((x)&0xF)<<0)\r
+#define MCF_SCM_GPACR_LOCK (0x80)\r
+\r
+\r
+#endif /* __MCF5282_SCM_H__ */\r
--- /dev/null
+/* Coldfire C Header File\r
+ * Copyright Freescale Semiconductor Inc\r
+ * All rights reserved.\r
+ *\r
+ * 2007/03/19 Revision: 0.9\r
+ */\r
+\r
+#ifndef __MCF5282_SDRAMC_H__\r
+#define __MCF5282_SDRAMC_H__\r
+\r
+\r
+/*********************************************************************\r
+*\r
+* Synchronous DRAM Controller (SDRAMC)\r
+*\r
+*********************************************************************/\r
+\r
+/* Register read/write macros */\r
+#define MCF_SDRAMC_DCR (*(vuint16*)(&__IPSBAR[0x40]))\r
+#define MCF_SDRAMC_DACR0 (*(vuint32*)(&__IPSBAR[0x48]))\r
+#define MCF_SDRAMC_DMR0 (*(vuint32*)(&__IPSBAR[0x4C]))\r
+#define MCF_SDRAMC_DACR1 (*(vuint32*)(&__IPSBAR[0x50]))\r
+#define MCF_SDRAMC_DMR1 (*(vuint32*)(&__IPSBAR[0x54]))\r
+#define MCF_SDRAMC_DACR(x) (*(vuint32*)(&__IPSBAR[0x48 + ((x)*0x8)]))\r
+#define MCF_SDRAMC_DMR(x) (*(vuint32*)(&__IPSBAR[0x4C + ((x)*0x8)]))\r
+\r
+\r
+/* Bit definitions and macros for MCF_SDRAMC_DCR */\r
+#define MCF_SDRAMC_DCR_RC(x) (((x)&0x1FF)<<0)\r
+#define MCF_SDRAMC_DCR_RTIM(x) (((x)&0x3)<<0x9)\r
+#define MCF_SDRAMC_DCR_RTIM_3 (0)\r
+#define MCF_SDRAMC_DCR_RTIM_6 (0x200)\r
+#define MCF_SDRAMC_DCR_RTIM_9 (0x400)\r
+#define MCF_SDRAMC_DCR_IS (0x800)\r
+#define MCF_SDRAMC_DCR_COC (0x1000)\r
+#define MCF_SDRAMC_DCR_NAM (0x2000)\r
+\r
+/* Bit definitions and macros for MCF_SDRAMC_DACR */\r
+#define MCF_SDRAMC_DACR_IP (0x8)\r
+#define MCF_SDRAMC_DACR_PS(x) (((x)&0x3)<<0x4)\r
+#define MCF_SDRAMC_DACR_PS_32 (0)\r
+#define MCF_SDRAMC_DACR_PS_8 (0x10)\r
+#define MCF_SDRAMC_DACR_PS_16 (0x20)\r
+#define MCF_SDRAMC_DACR_IMRS (0x40)\r
+#define MCF_SDRAMC_DACR_CBM(x) (((x)&0x7)<<0x8)\r
+#define MCF_SDRAMC_DACR_CASL(x) (((x)&0x3)<<0xC)\r
+#define MCF_SDRAMC_DACR_RE (0x8000)\r
+#define MCF_SDRAMC_DACR_BA(x) ((x)&0xFFFC0000)\r
+#define MCF_SDRAMC_DACR_CASL_1 (0)\r
+#define MCF_SDRAMC_DACR_CASL_2 (0x1000)\r
+#define MCF_SDRAMC_DACR_CASL_3 (0x2000)\r
+\r
+/* Bit definitions and macros for MCF_SDRAMC_DMR */\r
+#define MCF_SDRAMC_DMR_V (0x1)\r
+#define MCF_SDRAMC_DMR_UD (0x2)\r
+#define MCF_SDRAMC_DMR_UC (0x4)\r
+#define MCF_SDRAMC_DMR_SD (0x8)\r
+#define MCF_SDRAMC_DMR_SC (0x10)\r
+#define MCF_SDRAMC_DMR_AM (0x20)\r
+#define MCF_SDRAMC_DMR_CI (0x40)\r
+#define MCF_SDRAMC_DMR_WP (0x100)\r
+#define MCF_SDRAMC_DMR_BAM(x) (((x)&0x3FFF)<<0x12)\r
+#define MCF_SDRAMC_DMR_BAM_4G (0xFFFC0000)\r
+#define MCF_SDRAMC_DMR_BAM_2G (0x7FFC0000)\r
+#define MCF_SDRAMC_DMR_BAM_1G (0x3FFC0000)\r
+#define MCF_SDRAMC_DMR_BAM_1024M (0x3FFC0000)\r
+#define MCF_SDRAMC_DMR_BAM_512M (0x1FFC0000)\r
+#define MCF_SDRAMC_DMR_BAM_256M (0xFFC0000)\r
+#define MCF_SDRAMC_DMR_BAM_128M (0x7FC0000)\r
+#define MCF_SDRAMC_DMR_BAM_64M (0x3FC0000)\r
+#define MCF_SDRAMC_DMR_BAM_32M (0x1FC0000)\r
+#define MCF_SDRAMC_DMR_BAM_16M (0xFC0000)\r
+#define MCF_SDRAMC_DMR_BAM_8M (0x7C0000)\r
+#define MCF_SDRAMC_DMR_BAM_4M (0x3C0000)\r
+#define MCF_SDRAMC_DMR_BAM_2M (0x1C0000)\r
+#define MCF_SDRAMC_DMR_BAM_1M (0xC0000)\r
+#define MCF_SDRAMC_DMR_BAM_1024K (0xC0000)\r
+#define MCF_SDRAMC_DMR_BAM_512K (0x40000)\r
+#define MCF_SDRAMC_DMR_BAM_256K (0)\r
+\r
+\r
+#endif /* __MCF5282_SDRAMC_H__ */\r
--- /dev/null
+/* Coldfire C Header File\r
+ * Copyright Freescale Semiconductor Inc\r
+ * All rights reserved.\r
+ *\r
+ * 2007/03/19 Revision: 0.9\r
+ */\r
+\r
+#ifndef __MCF5282_UART_H__\r
+#define __MCF5282_UART_H__\r
+\r
+\r
+/*********************************************************************\r
+*\r
+* Universal Asynchronous Receiver Transmitter (UART)\r
+*\r
+*********************************************************************/\r
+\r
+/* Register read/write macros */\r
+#define MCF_UART0_UMR1 (*(vuint8 *)(&__IPSBAR[0x200]))\r
+#define MCF_UART0_UMR2 (*(vuint8 *)(&__IPSBAR[0x200]))\r
+#define MCF_UART0_USR (*(vuint8 *)(&__IPSBAR[0x204]))\r
+#define MCF_UART0_UCSR (*(vuint8 *)(&__IPSBAR[0x204]))\r
+#define MCF_UART0_UCR (*(vuint8 *)(&__IPSBAR[0x208]))\r
+#define MCF_UART0_URB (*(vuint8 *)(&__IPSBAR[0x20C]))\r
+#define MCF_UART0_UTB (*(vuint8 *)(&__IPSBAR[0x20C]))\r
+#define MCF_UART0_UIPCR (*(vuint8 *)(&__IPSBAR[0x210]))\r
+#define MCF_UART0_UACR (*(vuint8 *)(&__IPSBAR[0x210]))\r
+#define MCF_UART0_UIMR (*(vuint8 *)(&__IPSBAR[0x214]))\r
+#define MCF_UART0_UISR (*(vuint8 *)(&__IPSBAR[0x214]))\r
+#define MCF_UART0_UBG1 (*(vuint8 *)(&__IPSBAR[0x218]))\r
+#define MCF_UART0_UBG2 (*(vuint8 *)(&__IPSBAR[0x21C]))\r
+#define MCF_UART0_UIP (*(vuint8 *)(&__IPSBAR[0x234]))\r
+#define MCF_UART0_UOP1 (*(vuint8 *)(&__IPSBAR[0x238]))\r
+#define MCF_UART0_UOP0 (*(vuint8 *)(&__IPSBAR[0x23C]))\r
+\r
+#define MCF_UART1_UMR1 (*(vuint8 *)(&__IPSBAR[0x240]))\r
+#define MCF_UART1_UMR2 (*(vuint8 *)(&__IPSBAR[0x240]))\r
+#define MCF_UART1_USR (*(vuint8 *)(&__IPSBAR[0x244]))\r
+#define MCF_UART1_UCSR (*(vuint8 *)(&__IPSBAR[0x244]))\r
+#define MCF_UART1_UCR (*(vuint8 *)(&__IPSBAR[0x248]))\r
+#define MCF_UART1_URB (*(vuint8 *)(&__IPSBAR[0x24C]))\r
+#define MCF_UART1_UTB (*(vuint8 *)(&__IPSBAR[0x24C]))\r
+#define MCF_UART1_UIPCR (*(vuint8 *)(&__IPSBAR[0x250]))\r
+#define MCF_UART1_UACR (*(vuint8 *)(&__IPSBAR[0x250]))\r
+#define MCF_UART1_UIMR (*(vuint8 *)(&__IPSBAR[0x254]))\r
+#define MCF_UART1_UISR (*(vuint8 *)(&__IPSBAR[0x254]))\r
+#define MCF_UART1_UBG1 (*(vuint8 *)(&__IPSBAR[0x258]))\r
+#define MCF_UART1_UBG2 (*(vuint8 *)(&__IPSBAR[0x25C]))\r
+#define MCF_UART1_UIP (*(vuint8 *)(&__IPSBAR[0x274]))\r
+#define MCF_UART1_UOP1 (*(vuint8 *)(&__IPSBAR[0x278]))\r
+#define MCF_UART1_UOP0 (*(vuint8 *)(&__IPSBAR[0x27C]))\r
+\r
+#define MCF_UART2_UMR1 (*(vuint8 *)(&__IPSBAR[0x280]))\r
+#define MCF_UART2_UMR2 (*(vuint8 *)(&__IPSBAR[0x280]))\r
+#define MCF_UART2_USR (*(vuint8 *)(&__IPSBAR[0x284]))\r
+#define MCF_UART2_UCSR (*(vuint8 *)(&__IPSBAR[0x284]))\r
+#define MCF_UART2_UCR (*(vuint8 *)(&__IPSBAR[0x288]))\r
+#define MCF_UART2_URB (*(vuint8 *)(&__IPSBAR[0x28C]))\r
+#define MCF_UART2_UTB (*(vuint8 *)(&__IPSBAR[0x28C]))\r
+#define MCF_UART2_UIPCR (*(vuint8 *)(&__IPSBAR[0x290]))\r
+#define MCF_UART2_UACR (*(vuint8 *)(&__IPSBAR[0x290]))\r
+#define MCF_UART2_UIMR (*(vuint8 *)(&__IPSBAR[0x294]))\r
+#define MCF_UART2_UISR (*(vuint8 *)(&__IPSBAR[0x294]))\r
+#define MCF_UART2_UBG1 (*(vuint8 *)(&__IPSBAR[0x298]))\r
+#define MCF_UART2_UBG2 (*(vuint8 *)(&__IPSBAR[0x29C]))\r
+#define MCF_UART2_UIP (*(vuint8 *)(&__IPSBAR[0x2B4]))\r
+#define MCF_UART2_UOP1 (*(vuint8 *)(&__IPSBAR[0x2B8]))\r
+#define MCF_UART2_UOP0 (*(vuint8 *)(&__IPSBAR[0x2BC]))\r
+\r
+#define MCF_UART_UMR(x) (*(vuint8 *)(&__IPSBAR[0x200 + ((x)*0x40)]))\r
+#define MCF_UART_USR(x) (*(vuint8 *)(&__IPSBAR[0x204 + ((x)*0x40)]))\r
+#define MCF_UART_UCSR(x) (*(vuint8 *)(&__IPSBAR[0x204 + ((x)*0x40)]))\r
+#define MCF_UART_UCR(x) (*(vuint8 *)(&__IPSBAR[0x208 + ((x)*0x40)]))\r
+#define MCF_UART_URB(x) (*(vuint8 *)(&__IPSBAR[0x20C + ((x)*0x40)]))\r
+#define MCF_UART_UTB(x) (*(vuint8 *)(&__IPSBAR[0x20C + ((x)*0x40)]))\r
+#define MCF_UART_UIPCR(x) (*(vuint8 *)(&__IPSBAR[0x210 + ((x)*0x40)]))\r
+#define MCF_UART_UACR(x) (*(vuint8 *)(&__IPSBAR[0x210 + ((x)*0x40)]))\r
+#define MCF_UART_UIMR(x) (*(vuint8 *)(&__IPSBAR[0x214 + ((x)*0x40)]))\r
+#define MCF_UART_UISR(x) (*(vuint8 *)(&__IPSBAR[0x214 + ((x)*0x40)]))\r
+#define MCF_UART_UBG1(x) (*(vuint8 *)(&__IPSBAR[0x218 + ((x)*0x40)]))\r
+#define MCF_UART_UBG2(x) (*(vuint8 *)(&__IPSBAR[0x21C + ((x)*0x40)]))\r
+#define MCF_UART_UIP(x) (*(vuint8 *)(&__IPSBAR[0x234 + ((x)*0x40)]))\r
+#define MCF_UART_UOP1(x) (*(vuint8 *)(&__IPSBAR[0x238 + ((x)*0x40)]))\r
+#define MCF_UART_UOP0(x) (*(vuint8 *)(&__IPSBAR[0x23C + ((x)*0x40)]))\r
+\r
+/* Bit definitions and macros for MCF_UART_UMR */\r
+#define MCF_UART_UMR_BC(x) (((x)&0x3)<<0)\r
+#define MCF_UART_UMR_BC_5 (0)\r
+#define MCF_UART_UMR_BC_6 (0x1)\r
+#define MCF_UART_UMR_BC_7 (0x2)\r
+#define MCF_UART_UMR_BC_8 (0x3)\r
+#define MCF_UART_UMR_PT (0x4)\r
+#define MCF_UART_UMR_PM(x) (((x)&0x3)<<0x3)\r
+#define MCF_UART_UMR_ERR (0x20)\r
+#define MCF_UART_UMR_RXIRQ (0x40)\r
+#define MCF_UART_UMR_RXRTS (0x80)\r
+#define MCF_UART_UMR_PM_MULTI_ADDR (0x1C)\r
+#define MCF_UART_UMR_PM_MULTI_DATA (0x18)\r
+#define MCF_UART_UMR_PM_NONE (0x10)\r
+#define MCF_UART_UMR_PM_FORCE_HI (0xC)\r
+#define MCF_UART_UMR_PM_FORCE_LO (0x8)\r
+#define MCF_UART_UMR_PM_ODD (0x4)\r
+#define MCF_UART_UMR_PM_EVEN (0)\r
+#define MCF_UART_UMR_SB(x) (((x)&0xF)<<0)\r
+#define MCF_UART_UMR_SB_STOP_BITS_1 (0x7)\r
+#define MCF_UART_UMR_SB_STOP_BITS_15 (0x8)\r
+#define MCF_UART_UMR_SB_STOP_BITS_2 (0xF)\r
+#define MCF_UART_UMR_TXCTS (0x10)\r
+#define MCF_UART_UMR_TXRTS (0x20)\r
+#define MCF_UART_UMR_CM(x) (((x)&0x3)<<0x6)\r
+#define MCF_UART_UMR_CM_NORMAL (0)\r
+#define MCF_UART_UMR_CM_ECHO (0x40)\r
+#define MCF_UART_UMR_CM_LOCAL_LOOP (0x80)\r
+#define MCF_UART_UMR_CM_REMOTE_LOOP (0xC0)\r
+\r
+/* Bit definitions and macros for MCF_UART_USR */\r
+#define MCF_UART_USR_RXRDY (0x1)\r
+#define MCF_UART_USR_FFULL (0x2)\r
+#define MCF_UART_USR_TXRDY (0x4)\r
+#define MCF_UART_USR_TXEMP (0x8)\r
+#define MCF_UART_USR_OE (0x10)\r
+#define MCF_UART_USR_PE (0x20)\r
+#define MCF_UART_USR_FE (0x40)\r
+#define MCF_UART_USR_RB (0x80)\r
+\r
+/* Bit definitions and macros for MCF_UART_UCSR */\r
+#define MCF_UART_UCSR_TCS(x) (((x)&0xF)<<0)\r
+#define MCF_UART_UCSR_TCS_SYS_CLK (0xD)\r
+#define MCF_UART_UCSR_TCS_CTM16 (0xE)\r
+#define MCF_UART_UCSR_TCS_CTM (0xF)\r
+#define MCF_UART_UCSR_RCS(x) (((x)&0xF)<<0x4)\r
+#define MCF_UART_UCSR_RCS_SYS_CLK (0xD0)\r
+#define MCF_UART_UCSR_RCS_CTM16 (0xE0)\r
+#define MCF_UART_UCSR_RCS_CTM (0xF0)\r
+\r
+/* Bit definitions and macros for MCF_UART_UCR */\r
+#define MCF_UART_UCR_RC(x) (((x)&0x3)<<0)\r
+#define MCF_UART_UCR_RX_ENABLED (0x1)\r
+#define MCF_UART_UCR_RX_DISABLED (0x2)\r
+#define MCF_UART_UCR_TC(x) (((x)&0x3)<<0x2)\r
+#define MCF_UART_UCR_TX_ENABLED (0x4)\r
+#define MCF_UART_UCR_TX_DISABLED (0x8)\r
+#define MCF_UART_UCR_MISC(x) (((x)&0x7)<<0x4)\r
+#define MCF_UART_UCR_NONE (0)\r
+#define MCF_UART_UCR_RESET_MR (0x10)\r
+#define MCF_UART_UCR_RESET_RX (0x20)\r
+#define MCF_UART_UCR_RESET_TX (0x30)\r
+#define MCF_UART_UCR_RESET_ERROR (0x40)\r
+#define MCF_UART_UCR_RESET_BKCHGINT (0x50)\r
+#define MCF_UART_UCR_START_BREAK (0x60)\r
+#define MCF_UART_UCR_STOP_BREAK (0x70)\r
+\r
+/* Bit definitions and macros for MCF_UART_URB */\r
+#define MCF_UART_URB_RB(x) (((x)&0xFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_UART_UTB */\r
+#define MCF_UART_UTB_TB(x) (((x)&0xFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_UART_UIPCR */\r
+#define MCF_UART_UIPCR_CTS (0x1)\r
+#define MCF_UART_UIPCR_COS (0x10)\r
+\r
+/* Bit definitions and macros for MCF_UART_UACR */\r
+#define MCF_UART_UACR_IEC (0x1)\r
+\r
+/* Bit definitions and macros for MCF_UART_UIMR */\r
+#define MCF_UART_UIMR_TXRDY (0x1)\r
+#define MCF_UART_UIMR_FFULL_RXRDY (0x2)\r
+#define MCF_UART_UIMR_DB (0x4)\r
+#define MCF_UART_UIMR_COS (0x80)\r
+\r
+/* Bit definitions and macros for MCF_UART_UISR */\r
+#define MCF_UART_UISR_TXRDY (0x1)\r
+#define MCF_UART_UISR_FFULL_RXRDY (0x2)\r
+#define MCF_UART_UISR_DB (0x4)\r
+#define MCF_UART_UISR_COS (0x80)\r
+\r
+/* Bit definitions and macros for MCF_UART_UBG1 */\r
+#define MCF_UART_UBG1_Divider_MSB(x) (((x)&0xFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_UART_UBG2 */\r
+#define MCF_UART_UBG2_Divider_LSB(x) (((x)&0xFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_UART_UIP */\r
+#define MCF_UART_UIP_CTS (0x1)\r
+\r
+/* Bit definitions and macros for MCF_UART_UOP1 */\r
+#define MCF_UART_UOP1_RTS (0x1)\r
+\r
+/* Bit definitions and macros for MCF_UART_UOP0 */\r
+#define MCF_UART_UOP0_RTS (0x1)\r
+\r
+\r
+#endif /* __MCF5282_UART_H__ */\r
--- /dev/null
+/* Coldfire C Header File\r
+ * Copyright Freescale Semiconductor Inc\r
+ * All rights reserved.\r
+ *\r
+ * 2007/03/19 Revision: 0.9\r
+ */\r
+\r
+#ifndef __MCF5282_WTM_H__\r
+#define __MCF5282_WTM_H__\r
+\r
+\r
+/*********************************************************************\r
+*\r
+* Watchdog Timer Module (WTM)\r
+*\r
+*********************************************************************/\r
+\r
+/* Register read/write macros */\r
+#define MCF_WTM_WCR (*(vuint16*)(&__IPSBAR[0x140000]))\r
+#define MCF_WTM_WMR (*(vuint16*)(&__IPSBAR[0x140002]))\r
+#define MCF_WTM_WCNTR (*(vuint16*)(&__IPSBAR[0x140004]))\r
+#define MCF_WTM_WSR (*(vuint16*)(&__IPSBAR[0x140006]))\r
+\r
+\r
+/* Bit definitions and macros for MCF_WTM_WCR */\r
+#define MCF_WTM_WCR_EN (0x1)\r
+#define MCF_WTM_WCR_HALTED (0x2)\r
+#define MCF_WTM_WCR_DOZE (0x4)\r
+#define MCF_WTM_WCR_WAIT (0x8)\r
+\r
+/* Bit definitions and macros for MCF_WTM_WMR */\r
+#define MCF_WTM_WMR_WM(x) (((x)&0xFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_WTM_WCNTR */\r
+#define MCF_WTM_WCNTR_WC(x) (((x)&0xFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_WTM_WSR */\r
+#define MCF_WTM_WSR_WS(x) (((x)&0xFFFF)<<0)\r
+\r
+\r
+#endif /* __MCF5282_WTM_H__ */\r
--- /dev/null
+RM := rm -rf\r
+\r
+FREERTOS_SOURCE_DIR=./../../../Source\r
+PORT_SOURCE_DIR=./../../../Source/portable/GCC/ColdFire_V2\r
+COMMON_DEMO_CODE_DIR=./../../Common/Minimal\r
+OUTPUT_DIR=./bin\r
+CPU=528x\r
+LINKER_SCRIPT=m5282evb-ram-hosted.ld\r
+OUTPUT_FILENAME=RTOSDemo.elf\r
+CC=m68k-elf-gcc\r
+AS=m68K-elf-as\r
+VPATH=$(FREERTOS_SOURCE_DIR) : $(PORT_SOURCE_DIR) : $(COMMON_DEMO_CODE_DIR) : $(FREERTOS_SOURCE_DIR)/portable/MemMang : . : ./ParTest\r
+\r
+OBJS = $(OUTPUT_DIR)/portasm.o \\r
+ $(OUTPUT_DIR)/main.o \\r
+ $(OUTPUT_DIR)/ParTest.o \\r
+ $(OUTPUT_DIR)/BlockQ.o \\r
+ $(OUTPUT_DIR)/blocktim.o \\r
+ $(OUTPUT_DIR)/death.o \\r
+ $(OUTPUT_DIR)/integer.o \\r
+ $(OUTPUT_DIR)/PollQ.o \\r
+ $(OUTPUT_DIR)/semtest.o \\r
+ $(OUTPUT_DIR)/GenQTest.o \\r
+ $(OUTPUT_DIR)/QPeek.o \\r
+ $(OUTPUT_DIR)/recmutex.o \\r
+ $(OUTPUT_DIR)/port.o \\r
+ $(OUTPUT_DIR)/list.o \\r
+ $(OUTPUT_DIR)/tasks.o \\r
+ $(OUTPUT_DIR)/queue.o \\r
+ $(OUTPUT_DIR)/heap_2.o \\r
+ $(OUTPUT_DIR)/FreeRTOS_Timer.o\r
+ \r
+C_DEPS = $(OBJS:.o=.d)\r
+\r
+\r
+CFLAGS= -I"$(FREERTOS_SOURCE_DIR)/include" \\r
+ -I"include" \\r
+ -I"$(COMMON_DEMO_CODE_DIR)/../include" \\r
+ -I"$(PORT_SOURCE_DIR)" \\r
+ -I./MCF5282 \\r
+ -I. \\r
+ -D COLDFIRE_V2_GCC \\r
+ -O0 \\r
+ -g3 \\r
+ -Wall \\r
+ -Wextra \\r
+ -c \\r
+ -ffunction-sections \\r
+ -fdata-sections \\r
+ -fmessage-length=0 \\r
+ -funsigned-char \\r
+ -Wextra \\r
+ -mcpu=$(CPU) \\r
+ -MMD \\r
+ -MP \\r
+ -MF"$(@:%.o=%.d)" \\r
+ -MT"$(@:%.o=%.d)"\r
+\r
+ASFLAGS= -m528x \\r
+ --register-prefix-optional \\r
+ --bitwise-or\r
+\r
+LIBS=\r
+\r
+# Add inputs and outputs from these tool invocations to the build variables \r
+\r
+# All Target\r
+all: $(OUTPUT_DIR)/$(OUTPUT_FILENAME)\r
+\r
+# Tool invocations \r
+$(OUTPUT_DIR)/$(OUTPUT_FILENAME): $(OBJS)\r
+ $(CC) -nostartfiles --gc-sections -Xlinker -Map=$(OUTPUT_DIR)/output.map -mcpu=$(CPU) -T $(LINKER_SCRIPT) -o"$(OUTPUT_DIR)/$(OUTPUT_FILENAME)" $(OBJS) $(USER_OBJS) $(LIBS)\r
+\r
+$(OUTPUT_DIR)/%.o: %.c Makefile\r
+ $(CC) $(CFLAGS) -o"$@" "$<"\r
+\r
+$(OUTPUT_DIR)/%.o: %.S\r
+ $(AS) $(ASFLAGS) -o"$@" "$<"\r
+\r
+# Other Targets\r
+clean:\r
+ -$(RM) $(OBJS) $(C_DEPS) $(EXECUTABLES) $(OUTPUT_DIR)/$(OUTPUT_FILENAME)\r
+ -@echo ' '\r
+\r
+#\r
+# The rule to create the target directory\r
+#\r
+$(OUTPUT_DIR):\r
+ @mkdir $(OUTPUT_DIR)\r
+\r
+\r
+.PHONY: all clean dependents\r
+.SECONDARY: post-build\r
+\r
+-include $(wildcard $(OUTPUT_DIR)/*.d) __dummy__\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS.org V5.0.3 - Copyright (C) 2003-2008 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS.org distribution.\r
+\r
+ FreeRTOS.org is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS.org is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS.org; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS.org, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section\r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ ***************************************************************************\r
+ * *\r
+ * SAVE TIME AND MONEY! We can port FreeRTOS.org to your own hardware, *\r
+ * and even write all or part of your application on your behalf. *\r
+ * See http://www.OpenRTOS.com for details of the services we provide to *\r
+ * expedite your project. *\r
+ * *\r
+ ***************************************************************************\r
+ ***************************************************************************\r
+\r
+ Please ensure to read the configuration and relevant port sections of the\r
+ online documentation.\r
+\r
+ http://www.FreeRTOS.org - Documentation, latest information, license and\r
+ contact details.\r
+\r
+ http://www.SafeRTOS.com - A version that is certified for use in safety\r
+ critical systems.\r
+\r
+ http://www.OpenRTOS.com - Commercial support, development, porting,\r
+ licensing and training services.\r
+*/\r
+\r
+/*\r
+ Changes from V2.5.2\r
+\r
+ + All LED's are turned off to start.\r
+*/\r
+\r
+\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "partest.h"\r
+\r
+#define partstNUM_LEDs 4\r
+\r
+#define LED0_POS 0x01\r
+#define LED1_POS 0x04\r
+#define LED2_POS 0x01\r
+#define LED3_POS 0x04\r
+\r
+static const unsigned portCHAR ucLEDDefinitions[ partstNUM_LEDs ] = { LED0_POS, LED1_POS, LED2_POS, LED3_POS };\r
+\r
+/*-----------------------------------------------------------\r
+ * Simple parallel port IO routines.\r
+ *-----------------------------------------------------------*/\r
+\r
+void vParTestInitialise( void )\r
+{\r
+ /* Set the LEDs to outputs. */\r
+ MCF_GPIO_DDRTD |= ( LED0_POS | LED1_POS );\r
+ MCF_GPIO_DDRTC |= ( LED2_POS | LED3_POS );\r
+\r
+ /* Turn LEDs off. */\r
+ MCF_GPIO_SETTC |= ( LED0_POS | LED1_POS );\r
+ MCF_GPIO_SETTD |= ( LED2_POS | LED3_POS );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue )\r
+{\r
+ if( uxLED < 2 )\r
+ {\r
+ if( xValue != 0 )\r
+ {\r
+ taskENTER_CRITICAL();\r
+ MCF_GPIO_PORTTD |= ucLEDDefinitions[ uxLED ];\r
+ taskEXIT_CRITICAL();\r
+ }\r
+ else\r
+ {\r
+ taskENTER_CRITICAL();\r
+ MCF_GPIO_PORTTD &= ~ucLEDDefinitions[ uxLED ];\r
+ taskEXIT_CRITICAL();\r
+ }\r
+ }\r
+ else if( uxLED < 4 )\r
+ {\r
+ if( xValue != 0 )\r
+ {\r
+ taskENTER_CRITICAL();\r
+ MCF_GPIO_PORTTC |= ucLEDDefinitions[ uxLED ];\r
+ taskEXIT_CRITICAL();\r
+ }\r
+ else\r
+ {\r
+ taskENTER_CRITICAL();\r
+ MCF_GPIO_PORTTC &= ~ucLEDDefinitions[ uxLED ];\r
+ taskEXIT_CRITICAL();\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestToggleLED( unsigned portBASE_TYPE uxLED )\r
+{\r
+ if( uxLED < 2 )\r
+ {\r
+ taskENTER_CRITICAL();\r
+ {\r
+ if( ( MCF_GPIO_PORTTD & ucLEDDefinitions[ uxLED ] ) == ( unsigned portCHAR ) 0 )\r
+ {\r
+ MCF_GPIO_PORTTD |= ucLEDDefinitions[ uxLED ];\r
+ }\r
+ else\r
+ {\r
+ MCF_GPIO_PORTTD &= ~ucLEDDefinitions[ uxLED ];\r
+ }\r
+ }\r
+ taskEXIT_CRITICAL();\r
+ }\r
+ else if( uxLED < 4 )\r
+ {\r
+ taskENTER_CRITICAL();\r
+ {\r
+ if( ( MCF_GPIO_PORTTC & ucLEDDefinitions[ uxLED ] ) == ( unsigned portCHAR ) 0 )\r
+ {\r
+ MCF_GPIO_PORTTC |= ucLEDDefinitions[ uxLED ];\r
+ }\r
+ else\r
+ {\r
+ MCF_GPIO_PORTTC &= ~ucLEDDefinitions[ uxLED ];\r
+ }\r
+ }\r
+ taskEXIT_CRITICAL();\r
+ }\r
+}\r
+\r
--- /dev/null
+Archive member included because of file (symbol)\r
+\r
+c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libc.a(lib_a-atexit.o)\r
+ (atexit)\r
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+ c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libc.a(lib_a-exit.o) (__call_exitprocs)\r
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+c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libc.a(lib_a-fflush.o)\r
+ c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libc.a(lib_a-vfprintf.o) (_fflush_r)\r
+c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libc.a(lib_a-findfp.o)\r
+ c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libc.a(lib_a-vfprintf.o) (__sinit)\r
+c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libc.a(lib_a-fini.o)\r
+ c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libc.a(lib_a-__call_atexit.o) (__libc_fini_array)\r
+c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libc.a(lib_a-freer.o)\r
+ c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libc.a(lib_a-wsetup.o) (_free_r)\r
+c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libc.a(lib_a-fvwrite.o)\r
+ c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libc.a(lib_a-vfprintf.o) (__sfvwrite_r)\r
+c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libc.a(lib_a-fwalk.o)\r
+ c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libc.a(lib_a-findfp.o) (_fwalk)\r
+c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libc.a(lib_a-locale.o)\r
+ c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libc.a(lib_a-vfprintf.o) (_localeconv_r)\r
+c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libc.a(lib_a-makebuf.o)\r
+ c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libc.a(lib_a-wsetup.o) (__smakebuf_r)\r
+c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libc.a(lib_a-mallocr.o)\r
+ c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libc.a(lib_a-findfp.o) (_malloc_r)\r
+c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libc.a(lib_a-memchr.o)\r
+ c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libc.a(lib_a-vfprintf.o) (memchr)\r
+c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libc.a(lib_a-memmove.o)\r
+ c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libc.a(lib_a-fvwrite.o) (memmove)\r
+c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libc.a(lib_a-mlock.o)\r
+ c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libc.a(lib_a-freer.o) (__malloc_lock)\r
+c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libc.a(lib_a-mprec.o)\r
+ c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libc.a(lib_a-dtoa.o) (_Bfree)\r
+c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libc.a(lib_a-reallocr.o)\r
+ c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libc.a(lib_a-fvwrite.o) (_realloc_r)\r
+c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libc.a(lib_a-s_isinfd.o)\r
+ c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libc.a(lib_a-vfprintf.o) (__isinfd)\r
+c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libc.a(lib_a-s_isnand.o)\r
+ c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libc.a(lib_a-vfprintf.o) (__isnand)\r
+c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libc.a(lib_a-sbrkr.o)\r
+ c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libc.a(lib_a-freer.o) (_sbrk_r)\r
+c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libc.a(lib_a-stdio.o)\r
+ c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libc.a(lib_a-findfp.o) (__sclose)\r
+c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libc.a(lib_a-strcmp.o)\r
+ c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libc.a(lib_a-locale.o) (strcmp)\r
+c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libc.a(lib_a-writer.o)\r
+ c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libc.a(lib_a-stdio.o) (_write_r)\r
+c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libc.a(lib_a-callocr.o)\r
+ c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libc.a(lib_a-mprec.o) (_calloc_r)\r
+c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libc.a(lib_a-closer.o)\r
+ c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libc.a(lib_a-stdio.o) (_close_r)\r
+c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libc.a(lib_a-fclose.o)\r
+ c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libc.a(lib_a-findfp.o) (fclose)\r
+c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libc.a(lib_a-fstatr.o)\r
+ c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libc.a(lib_a-makebuf.o) (_fstat_r)\r
+c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libc.a(lib_a-isattyr.o)\r
+ c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libc.a(lib_a-makebuf.o) (_isatty_r)\r
+c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libc.a(lib_a-lseekr.o)\r
+ c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libc.a(lib_a-stdio.o) (_lseek_r)\r
+c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libc.a(lib_a-readr.o)\r
+ c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libc.a(lib_a-stdio.o) (_read_r)\r
+c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libc.a(lib_a-reent.o)\r
+ c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libc.a(lib_a-sbrkr.o) (errno)\r
+c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/m5208\libgcc.a(_double.o)\r
+ c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libc.a(lib_a-dtoa.o) (__adddf3)\r
+c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/m5208\libgcc.a(_floatex.o)\r
+ c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/m5208\libgcc.a(_double.o) (_fpCCR)\r
+c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/m5208\libgcc.a(_eqdf2.o)\r
+ c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libc.a(lib_a-vfprintf.o) (__eqdf2)\r
+c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/m5208\libgcc.a(_nedf2.o)\r
+ c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libc.a(lib_a-vfprintf.o) (__nedf2)\r
+c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/m5208\libgcc.a(_gtdf2.o)\r
+ c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libc.a(lib_a-dtoa.o) (__gtdf2)\r
+c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/m5208\libgcc.a(_gedf2.o)\r
+ c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libc.a(lib_a-dtoa.o) (__gedf2)\r
+c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/m5208\libgcc.a(_ltdf2.o)\r
+ c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libc.a(lib_a-vfprintf.o) (__ltdf2)\r
+c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/m5208\libgcc.a(_udivdi3.o)\r
+ c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libc.a(lib_a-vfprintf.o) (__udivdi3)\r
+c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/m5208\libgcc.a(_umoddi3.o)\r
+ c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libc.a(lib_a-vfprintf.o) (__umoddi3)\r
+c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/m5208\libgcc.a(fpgnulib.o)\r
+ c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libc.a(lib_a-dtoa.o) (__floatunsidf)\r
+c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libcs3.a(start_c.o)\r
+ (__cs3_start_c)\r
+c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libcs3.a(m5282evb-reset.o)\r
+ (__cs3_reset_m5282evb)\r
+c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libcs3hosted.a(hosted-_exit.o)\r
+ c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libc.a(lib_a-exit.o) (_exit)\r
+c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libcs3hosted.a(hosted-close.o)\r
+ c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libc.a(lib_a-closer.o) (close)\r
+c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libcs3hosted.a(hosted-fstat.o)\r
+ c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libc.a(lib_a-fstatr.o) (fstat)\r
+c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libcs3hosted.a(hosted-isatty.o)\r
+ c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libc.a(lib_a-isattyr.o) (isatty)\r
+c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libcs3hosted.a(hosted-lseek.o)\r
+ c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libc.a(lib_a-lseekr.o) (lseek)\r
+c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libcs3hosted.a(hosted-read.o)\r
+ c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libc.a(lib_a-readr.o) (read)\r
+c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libcs3hosted.a(hosted-sbrk.o)\r
+ c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libc.a(lib_a-sbrkr.o) (sbrk)\r
+c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libcs3hosted.a(hosted-write.o)\r
+ c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libc.a(lib_a-writer.o) (write)\r
+c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libcs3hosted.a(hosted-gdb.o)\r
+ c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libcs3hosted.a(hosted-lseek.o) (__cs3_hosted_to_gdb_lseek_flags)\r
+c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libcs3hosted.a(start.o)\r
+ (_start)\r
+c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libcs3coldfire.a(coldfire-vector.o)\r
+ (__cs3_interrupt_vector_coldfire)\r
+c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libcs3coldfire.a(coldfire_isr_other_interrupt.o)\r
+ (__cs3_isr_interrupt_6)\r
+c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libcs3coldfire.a(coldfire_isr_unimplemented_opcode.o)\r
+ (__cs3_isr_unimplemented_line_a_opcode)\r
+c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libcs3coldfire.a(coldfire_isr_breakpoint_debug_interrupt.o)\r
+ (__cs3_isr_non_pc_breakpoint_debug_interrupt)\r
+c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libcs3coldfire.a(coldfire_isr_trap_interrupt.o)\r
+ (__cs3_isr_trap0)\r
+c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libcs3coldfire.a(coldfire_isr_fp_interrupt.o)\r
+ (__cs3_isr_fp_branch_unordered)\r
+c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libcs3coldfire.a(coldfire_isr_access_error.o)\r
+ (__cs3_isr_access_error)\r
+c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libcs3coldfire.a(coldfire_isr_address_error.o)\r
+ (__cs3_isr_address_error)\r
+c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libcs3coldfire.a(coldfire_isr_illegal_instruction.o)\r
+ (__cs3_isr_illegal_instruction)\r
+c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libcs3coldfire.a(coldfire_isr_divide_by_zero.o)\r
+ (__cs3_isr_divide_by_zero)\r
+c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libcs3coldfire.a(coldfire_isr_privilege_violation.o)\r
+ (__cs3_isr_privilege_violation)\r
+c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libcs3coldfire.a(coldfire_isr_trace.o)\r
+ (__cs3_isr_trace)\r
+c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libcs3coldfire.a(coldfire_isr_format_error.o)\r
+ (__cs3_isr_format_error)\r
+c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libcs3coldfire.a(coldfire_isr_spurious_interrupt.o)\r
+ (__cs3_isr_spurious_interrupt)\r
+c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libcs3coldfire.a(coldfire_isr_unsupported_instruction.o)\r
+ (__cs3_isr_unsupported_instruction)\r
+c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libc.a(lib_a-errno.o)\r
+ c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libcs3hosted.a(hosted-close.o) (__errno)\r
+c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libc.a(lib_a-init.o)\r
+ c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libcs3.a(start_c.o) (__libc_init_array)\r
+c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libcs3.a(heap.o)\r
+ c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libcs3hosted.a(hosted-sbrk.o) (__cs3_heap_limit)\r
+\r
+Allocating common symbols\r
+Common symbol size file\r
+\r
+errno 0x4 c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libc.a(lib_a-reent.o)\r
+xHighPriorityTask 0x4 ./bin/QPeek.o\r
+xMediumPriorityTask\r
+ 0x4 ./bin/QPeek.o\r
+xHighestPriorityTask\r
+ 0x4 ./bin/QPeek.o\r
+xCreatedTask 0x4 ./bin/death.o\r
+\r
+Memory Configuration\r
+\r
+Name Origin Length Attributes\r
+ram 0x00000000 0x01000000 xrw\r
+rom 0xffe00000 0x00200000 xr\r
+rombar 0xf0000000 0x00080000 xr\r
+rambar 0x20000000 0x00010000 xrw\r
+ipsbar 0x40000000 0x20000000 rw\r
+*default* 0x00000000 0xffffffff\r
+\r
+Linker script and memory map\r
+\r
+LOAD ./bin/portasm.o\r
+LOAD ./bin/main.o\r
+LOAD ./bin/ParTest.o\r
+LOAD ./bin/BlockQ.o\r
+LOAD ./bin/blocktim.o\r
+LOAD ./bin/death.o\r
+LOAD ./bin/integer.o\r
+LOAD ./bin/PollQ.o\r
+LOAD ./bin/semtest.o\r
+LOAD ./bin/GenQTest.o\r
+LOAD ./bin/QPeek.o\r
+LOAD ./bin/recmutex.o\r
+LOAD ./bin/port.o\r
+LOAD ./bin/list.o\r
+LOAD ./bin/tasks.o\r
+LOAD ./bin/queue.o\r
+LOAD ./bin/heap_2.o\r
+LOAD ./bin/FreeRTOS_Timer.o\r
+LOAD c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/m5208\libgcc.a\r
+LOAD c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libc.a\r
+LOAD c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/m5208\libgcc.a\r
+START GROUP\r
+LOAD c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/m5208\libgcc.a\r
+LOAD c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libc.a\r
+LOAD c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libcs3.a\r
+LOAD c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libcs3hosted.a\r
+LOAD c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libcs3coldfire.a\r
+END GROUP\r
+ 0x000149d8 PROVIDE (__cs3_heap_start, _end)\r
+ 0x01000000 PROVIDE (__cs3_heap_end, (__cs3_region_start_ram + __cs3_region_size_ram))\r
+ 0x00000003 PROVIDE (__cs3_region_num, ((__cs3_regions_end - __cs3_regions) / 0x14))\r
+ 0x01000000 PROVIDE (__cs3_stack, (__cs3_region_start_ram + __cs3_region_size_ram))\r
+\r
+.text 0x00000000 0xdccc\r
+ CREATE_OBJECT_SYMBOLS\r
+ 0x00000000 __cs3_region_start_ram = .\r
+ *(.cs3.region-head.ram)\r
+ 0x00000001 ASSERT ((. == __cs3_region_start_ram), .cs3.region-head.ram not permitted)\r
+ 0x00000000 __cs3_interrupt_vector = __cs3_interrupt_vector_coldfire\r
+ *(.cs3.interrupt_vector)\r
+ .cs3.interrupt_vector\r
+ 0x00000000 0x400 c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libcs3coldfire.a(coldfire-vector.o)\r
+ 0x00000000 __cs3_interrupt_vector_coldfire\r
+ 0x00000001 ASSERT ((. != __cs3_interrupt_vector_coldfire), No interrupt vector)\r
+ 0x0000dba0 PROVIDE (__cs3_reset_m5282evb, _start)\r
+ 0x00000400 __cs3_reset = __cs3_reset_m5282evb\r
+ *(.cs3.reset)\r
+ .cs3.reset 0x00000400 0xe6 c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libcs3.a(m5282evb-reset.o)\r
+ 0x00000400 __cs3_reset_m5282evb\r
+ *(.text .text.* .gnu.linkonce.t.*)\r
+ *fill* 0x000004e6 0x2 00\r
+ .text 0x000004e8 0x36 ./bin/portasm.o\r
+ *fill* 0x0000051e 0x2 00\r
+ .text 0x00000520 0x0 ./bin/main.o\r
+ .text.main 0x00000520 0x6c ./bin/main.o\r
+ 0x00000520 main\r
+ .text.prvSetupHardware\r
+ 0x0000058c 0xe ./bin/main.o\r
+ .text.vApplicationStackOverflowHook\r
+ 0x0000059a 0x6 ./bin/main.o\r
+ 0x0000059a vApplicationStackOverflowHook\r
+ .text 0x000005a0 0x0 ./bin/ParTest.o\r
+ .text.vParTestInitialise\r
+ 0x000005a0 0x60 ./bin/ParTest.o\r
+ 0x000005a0 vParTestInitialise\r
+ .text.vParTestSetLED\r
+ 0x00000600 0xf0 ./bin/ParTest.o\r
+ 0x00000600 vParTestSetLED\r
+ .text.vParTestToggleLED\r
+ 0x000006f0 0x106 ./bin/ParTest.o\r
+ 0x000006f0 vParTestToggleLED\r
+ *fill* 0x000007f6 0x2 00\r
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+ .text.vStartBlockingQueueTasks\r
+ 0x000007f8 0x26c ./bin/BlockQ.o\r
+ 0x000007f8 vStartBlockingQueueTasks\r
+ .text.vBlockingQueueProducer\r
+ 0x00000a64 0x6e ./bin/BlockQ.o\r
+ .text.vBlockingQueueConsumer\r
+ 0x00000ad2 0x88 ./bin/BlockQ.o\r
+ .text.xAreBlockingQueuesStillRunning\r
+ 0x00000b5a 0xc8 ./bin/BlockQ.o\r
+ 0x00000b5a xAreBlockingQueuesStillRunning\r
+ *fill* 0x00000c22 0x2 00\r
+ .text 0x00000c24 0x0 ./bin/blocktim.o\r
+ .text.vCreateBlockTimeTasks\r
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+ 0x00000c24 vCreateBlockTimeTasks\r
+ .text.vPrimaryBlockTimeTestTask\r
+ 0x00000caa 0x452 ./bin/blocktim.o\r
+ .text.vSecondaryBlockTimeTestTask\r
+ 0x000010fc 0x132 ./bin/blocktim.o\r
+ .text.xAreBlockTimeTestTasksStillRunning\r
+ 0x0000122e 0x62 ./bin/blocktim.o\r
+ 0x0000122e xAreBlockTimeTestTasksStillRunning\r
+ .text 0x00001290 0x0 ./bin/death.o\r
+ .text.vCreateSuicidalTasks\r
+ 0x00001290 0x64 ./bin/death.o\r
+ 0x00001290 vCreateSuicidalTasks\r
+ .text.vSuicidalTask\r
+ 0x000012f4 0x72 ./bin/death.o\r
+ .text.vCreateTasks\r
+ 0x00001366 0x9e ./bin/death.o\r
+ .text.xIsCreateTaskStillRunning\r
+ 0x00001404 0x7c ./bin/death.o\r
+ 0x00001404 xIsCreateTaskStillRunning\r
+ .text 0x00001480 0x0 ./bin/integer.o\r
+ .text.vStartIntegerMathTasks\r
+ 0x00001480 0x56 ./bin/integer.o\r
+ 0x00001480 vStartIntegerMathTasks\r
+ .text.vCompeteingIntMathTask\r
+ 0x000014d6 0x78 ./bin/integer.o\r
+ .text.xAreIntegerMathsTaskStillRunning\r
+ 0x0000154e 0x56 ./bin/integer.o\r
+ 0x0000154e xAreIntegerMathsTaskStillRunning\r
+ .text 0x000015a4 0x0 ./bin/PollQ.o\r
+ .text.vStartPolledQueueTasks\r
+ 0x000015a4 0x8e ./bin/PollQ.o\r
+ 0x000015a4 vStartPolledQueueTasks\r
+ .text.vPolledQueueProducer\r
+ 0x00001632 0x8a ./bin/PollQ.o\r
+ .text.vPolledQueueConsumer\r
+ 0x000016bc 0xa2 ./bin/PollQ.o\r
+ .text.xArePollingQueuesStillRunning\r
+ 0x0000175e 0x38 ./bin/PollQ.o\r
+ 0x0000175e xArePollingQueuesStillRunning\r
+ *fill* 0x00001796 0x2 00\r
+ .text 0x00001798 0x0 ./bin/semtest.o\r
+ .text.vStartSemaphoreTasks\r
+ 0x00001798 0x1ee ./bin/semtest.o\r
+ 0x00001798 vStartSemaphoreTasks\r
+ .text.prvSemaphoreTest\r
+ 0x00001986 0x148 ./bin/semtest.o\r
+ .text.xAreSemaphoreTasksStillRunning\r
+ 0x00001ace 0x76 ./bin/semtest.o\r
+ 0x00001ace xAreSemaphoreTasksStillRunning\r
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+ .text.vStartGenericQueueTasks\r
+ 0x00001b44 0xf2 ./bin/GenQTest.o\r
+ 0x00001b44 vStartGenericQueueTasks\r
+ .text.prvSendFrontAndBackTest\r
+ 0x00001c36 0x486 ./bin/GenQTest.o\r
+ .text.prvLowPriorityMutexTask\r
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+ .text.prvMediumPriorityMutexTask\r
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+ .text.prvHighPriorityMutexTask\r
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+ .text.xAreGenericQueueTasksStillRunning\r
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+ 0x000022d4 vStartQueuePeekTasks\r
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+ .text.prvHighPriorityPeekTask\r
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+ .text.prvLowPriorityPeekTask\r
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+ .text.xAreQueuePeekTasksStillRunning\r
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+ 0x000027b6 xAreQueuePeekTasksStillRunning\r
+ *fill* 0x00002802 0x2 00\r
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+ .text.vStartRecursiveMutexTasks\r
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+ 0x00002804 vStartRecursiveMutexTasks\r
+ .text.prvRecursiveMutexControllingTask\r
+ 0x000028b2 0xe6 ./bin/recmutex.o\r
+ .text.prvRecursiveMutexBlockingTask\r
+ 0x00002998 0xa2 ./bin/recmutex.o\r
+ .text.prvRecursiveMutexPollingTask\r
+ 0x00002a3a 0x80 ./bin/recmutex.o\r
+ .text.xAreRecursiveMutexTasksStillRunning\r
+ 0x00002aba 0x96 ./bin/recmutex.o\r
+ 0x00002aba xAreRecursiveMutexTasksStillRunning\r
+ .text 0x00002b50 0x0 ./bin/port.o\r
+ .text.pxPortInitialiseStack\r
+ 0x00002b50 0xa ./bin/port.o\r
+ 0x00002b50 pxPortInitialiseStack\r
+ .text.xPortStartScheduler\r
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+ 0x00002b5a xPortStartScheduler\r
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+ 0x00002b68 vPortEndScheduler\r
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+ 0x00002b70 vPortEnterCritical\r
+ .text.vPortExitCritical\r
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+ 0x00002b86 vPortExitCritical\r
+ .text.uxPortSetInterruptMaskFromISR\r
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+ 0x00002b9c uxPortSetInterruptMaskFromISR\r
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+ 0x00002ba6 vPortClearInterruptMaskFromISR\r
+ *fill* 0x00002bae 0x2 00\r
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+ 0x00002bb0 vListInitialise\r
+ .text.vListInitialiseItem\r
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+ 0x00002bf2 vListInitialiseItem\r
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+ 0x00002c02 vListInsertEnd\r
+ .text.vListInsert\r
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+ 0x00003348 xTaskIsTaskSuspended\r
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+ 0x00003390 vTaskResume\r
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+ 0x00003430 xTaskResumeFromISR\r
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+ 0x000036fc uxTaskGetNumberOfTasks\r
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+ 0x0000371e vTaskList\r
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+ 0x0000385e vTaskStartTrace\r
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+ 0x000038dc vTaskIncrementTick\r
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+ 0x00003c78 xTaskRemoveFromEventList\r
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+ 0x00003e38 vTaskMissedYield\r
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+ .text.prvInitialiseTCBVariables\r
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+ .text.prvInitialiseTaskLists\r
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+ .text.prvListTaskWithinSingleList\r
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+ 0x00004f7a xQueueIsQueueFullFromISR\r
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+ 0x00004fac vQueueAddToRegistry\r
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+ 0x00005206 vPortFree\r
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+ 0x0000531a __cs3_isr_interrupt_119\r
+ .text 0x00005354 0x18 c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libc.a(lib_a-atexit.o)\r
+ 0x00005354 atexit\r
+ .text 0x0000536c 0x32 c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libc.a(lib_a-exit.o)\r
+ 0x0000536c exit\r
+ *fill* 0x0000539e 0x2 00\r
+ .text 0x000053a0 0x0 c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libc.a(lib_a-impure.o)\r
+ .text 0x000053a0 0x72 c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libc.a(lib_a-memcmp.o)\r
+ 0x000053a0 memcmp\r
+ *fill* 0x00005412 0x2 00\r
+ .text 0x00005414 0x70 c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libc.a(lib_a-memcpy.o)\r
+ 0x00005414 memcpy\r
+ .text 0x00005484 0x6c c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libc.a(lib_a-memset.o)\r
+ 0x00005484 memset\r
+ .text 0x000054f0 0xba c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libc.a(lib_a-sprintf.o)\r
+ 0x0000554e _sprintf_r\r
+ 0x000054f0 sprintf\r
+ *fill* 0x000055aa 0x2 00\r
+ .text 0x000055ac 0x7c c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libc.a(lib_a-strcat.o)\r
+ 0x000055ac strcat\r
+ .text 0x00005628 0x22 c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libc.a(lib_a-strcpy.o)\r
+ 0x00005628 strcpy\r
+ *fill* 0x0000564a 0x2 00\r
+ .text 0x0000564c 0x1a c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libc.a(lib_a-strlen.o)\r
+ 0x0000564c strlen\r
+ *fill* 0x00005666 0x2 00\r
+ .text 0x00005668 0x8e c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libc.a(lib_a-strncpy.o)\r
+ 0x00005668 strncpy\r
+ *fill* 0x000056f6 0x2 00\r
+ .text 0x000056f8 0x1cd4 c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libc.a(lib_a-vfprintf.o)\r
+ 0x0000573c _vfprintf_r\r
+ 0x000073ae vfprintf\r
+ .text 0x000073cc 0x13e c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libc.a(lib_a-wsetup.o)\r
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+ 0x0000dbb4 __cs3_isr_interrupt_205\r
+ 0x0000dbb4 __cs3_isr_interrupt_17\r
+ 0x0000dbb4 __cs3_isr_interrupt_140\r
+ 0x0000dbb4 __cs3_isr_interrupt_6\r
+ 0x0000dbb4 __cs3_isr_interrupt_226\r
+ 0x0000dbb4 __cs3_isr_interrupt_252\r
+ 0x0000dbb4 __cs3_isr_interrupt_209\r
+ 0x0000dbb4 __cs3_isr_interrupt_202\r
+ 0x0000dbb4 __cs3_isr_interrupt_245\r
+ 0x0000dbb4 __cs3_isr_interrupt_19\r
+ 0x0000dbb4 __cs3_isr_interrupt_171\r
+ 0x0000dbb4 __cs3_isr_interrupt_234\r
+ 0x0000dbb4 __cs3_isr_interrupt_232\r
+ 0x0000dbb4 __cs3_isr_interrupt_239\r
+ 0x0000dbb4 __cs3_isr_interrupt_21\r
+ 0x0000dbb4 __cs3_isr_interrupt_62\r
+ 0x0000dbb4 __cs3_isr_interrupt_98\r
+ 0x0000dbb4 __cs3_isr_interrupt_240\r
+ 0x0000dbb4 __cs3_isr_interrupt_106\r
+ 0x0000dbb4 __cs3_isr_interrupt_109\r
+ 0x0000dbb4 __cs3_isr_interrupt_190\r
+ 0x0000dbb4 __cs3_isr_interrupt_193\r
+ 0x0000dbb4 __cs3_isr_interrupt_57\r
+ 0x0000dbb4 __cs3_isr_interrupt_168\r
+ 0x0000dbb4 __cs3_isr_interrupt_153\r
+ 0x0000dbb4 __cs3_isr_interrupt_81\r
+ 0x0000dbb4 __cs3_isr_interrupt_110\r
+ 0x0000dbb4 __cs3_isr_interrupt_163\r
+ 0x0000dbb4 __cs3_isr_interrupt_123\r
+ 0x0000dbb4 __cs3_isr_interrupt_185\r
+ 0x0000dbb4 __cs3_isr_interrupt_70\r
+ 0x0000dbb4 __cs3_isr_interrupt_136\r
+ 0x0000dbb4 __cs3_isr_interrupt_134\r
+ 0x0000dbb4 __cs3_isr_interrupt_230\r
+ 0x0000dbb4 __cs3_isr_interrupt_94\r
+ 0x0000dbb4 __cs3_isr_interrupt_85\r
+ 0x0000dbb4 __cs3_isr_interrupt_186\r
+ 0x0000dbb4 __cs3_isr_interrupt_58\r
+ 0x0000dbb4 __cs3_isr_interrupt_196\r
+ 0x0000dbb4 __cs3_isr_interrupt_132\r
+ 0x0000dbb4 __cs3_isr_interrupt_29\r
+ 0x0000dbb4 __cs3_isr_interrupt_15\r
+ 0x0000dbb4 __cs3_isr_interrupt_224\r
+ 0x0000dbb4 __cs3_isr_interrupt_207\r
+ 0x0000dbb4 __cs3_isr_interrupt_182\r
+ 0x0000dbb4 __cs3_isr_interrupt_255\r
+ 0x0000dbb4 __cs3_isr_interrupt_217\r
+ 0x0000dbb4 __cs3_isr_interrupt_92\r
+ 0x0000dbb4 __cs3_isr_interrupt_128\r
+ 0x0000dbb4 __cs3_isr_interrupt_212\r
+ 0x0000dbb4 __cs3_isr_interrupt_210\r
+ 0x0000dbb4 __cs3_isr_interrupt_188\r
+ 0x0000dbb4 __cs3_isr_interrupt_117\r
+ 0x0000dbb4 __cs3_isr_interrupt_144\r
+ 0x0000dbb4 __cs3_isr_interrupt_175\r
+ 0x0000dbb4 __cs3_isr_interrupt_172\r
+ 0x0000dbb4 __cs3_isr_interrupt_83\r
+ 0x0000dbb4 __cs3_isr_interrupt_253\r
+ 0x0000dbb4 __cs3_isr_interrupt_73\r
+ 0x0000dbb4 __cs3_isr_interrupt_78\r
+ 0x0000dbb4 __cs3_isr_interrupt_75\r
+ 0x0000dbb4 __cs3_isr_interrupt_228\r
+ 0x0000dbb4 __cs3_isr_interrupt_169\r
+ 0x0000dbb4 __cs3_isr_interrupt_7\r
+ 0x0000dbb4 __cs3_isr_interrupt_124\r
+ 0x0000dbb4 __cs3_isr_interrupt_170\r
+ 0x0000dbb4 __cs3_isr_interrupt_22\r
+ 0x0000dbb4 __cs3_isr_interrupt_63\r
+ 0x0000dbb4 __cs3_isr_interrupt_183\r
+ 0x0000dbb4 __cs3_isr_interrupt_161\r
+ 0x0000dbb4 __cs3_isr_interrupt_137\r
+ 0x0000dbb4 __cs3_isr_interrupt_31\r
+ 0x0000dbb4 __cs3_isr_interrupt_195\r
+ 0x0000dbb4 __cs3_isr_interrupt_229\r
+ 0x0000dbb4 __cs3_isr_interrupt_243\r
+ 0x0000dbb4 __cs3_isr_interrupt_200\r
+ 0x0000dbb4 __cs3_isr_interrupt_89\r
+ 0x0000dbb4 __cs3_isr_interrupt_88\r
+ 0x0000dbb4 __cs3_isr_interrupt_187\r
+ 0x0000dbb4 __cs3_isr_interrupt_236\r
+ 0x0000dbb4 __cs3_isr_interrupt_151\r
+ 0x0000dbb4 __cs3_isr_interrupt_105\r
+ 0x0000dbb4 __cs3_isr_interrupt_199\r
+ 0x0000dbb4 __cs3_isr_interrupt_96\r
+ 0x0000dbb4 __cs3_isr_interrupt_166\r
+ 0x0000dbb4 __cs3_isr_interrupt_121\r
+ 0x0000dbb4 __cs3_isr_interrupt_71\r
+ 0x0000dbb4 __cs3_isr_interrupt_20\r
+ 0x0000dbb4 __cs3_isr_interrupt_218\r
+ 0x0000dbb4 __cs3_isr_interrupt_213\r
+ 0x0000dbb4 __cs3_isr_interrupt_86\r
+ 0x0000dbb4 __cs3_isr_interrupt_138\r
+ 0x0000dbb4 __cs3_isr_interrupt_180\r
+ 0x0000dbb4 __cs3_isr_interrupt_225\r
+ 0x0000dbb4 __cs3_isr_interrupt_59\r
+ 0x0000dbb4 __cs3_isr_interrupt_56\r
+ 0x0000dbb4 __cs3_isr_interrupt_249\r
+ 0x0000dbb4 __cs3_isr_interrupt_93\r
+ 0x0000dbb4 __cs3_isr_interrupt_167\r
+ 0x0000dbb4 __cs3_isr_interrupt_206\r
+ 0x0000dbb4 __cs3_isr_interrupt_122\r
+ 0x0000dbb4 __cs3_isr_interrupt_147\r
+ 0x0000dbb4 __cs3_isr_interrupt_25\r
+ 0x0000dbb4 __cs3_isr_interrupt_159\r
+ 0x0000dbb4 __cs3_isr_interrupt_102\r
+ 0x0000dbb4 __cs3_isr_interrupt_142\r
+ 0x0000dbb4 __cs3_isr_interrupt_16\r
+ 0x0000dbb4 __cs3_isr_interrupt_99\r
+ 0x0000dbb4 __cs3_isr_interrupt_176\r
+ 0x0000dbb4 __cs3_isr_interrupt_135\r
+ 0x0000dbb4 __cs3_isr_interrupt_130\r
+ 0x0000dbb4 __cs3_isr_interrupt_60\r
+ 0x0000dbb4 __cs3_isr_interrupt_116\r
+ 0x0000dbb4 __cs3_isr_interrupt_222\r
+ 0x0000dbb4 __cs3_isr_interrupt_28\r
+ 0x0000dbb4 __cs3_isr_interrupt_177\r
+ 0x0000dbb4 __cs3_isr_interrupt_165\r
+ 0x0000dbb4 __cs3_isr_interrupt_160\r
+ 0x0000dbb4 __cs3_isr_interrupt_120\r
+ 0x0000dbb4 __cs3_isr_interrupt_67\r
+ 0x0000dbb4 __cs3_isr_interrupt_198\r
+ 0x0000dbb4 __cs3_isr_interrupt_66\r
+ 0x0000dbb4 __cs3_isr_interrupt_129\r
+ 0x0000dbb4 __cs3_isr_interrupt_76\r
+ 0x0000dbb4 __cs3_isr_interrupt_214\r
+ 0x0000dbb4 __cs3_isr_interrupt_69\r
+ 0x0000dbb4 __cs3_isr_interrupt_26\r
+ 0x0000dbb4 __cs3_isr_other_interrupt\r
+ 0x0000dbb4 __cs3_isr_interrupt_90\r
+ 0x0000dbb4 __cs3_isr_interrupt_18\r
+ 0x0000dbb4 __cs3_isr_interrupt_241\r
+ 0x0000dbb4 __cs3_isr_interrupt_235\r
+ 0x0000dbb4 __cs3_isr_interrupt_216\r
+ 0x0000dbb4 __cs3_isr_interrupt_211\r
+ 0x0000dbb4 __cs3_isr_interrupt_246\r
+ 0x0000dbb4 __cs3_isr_interrupt_118\r
+ 0x0000dbb4 __cs3_isr_interrupt_223\r
+ 0x0000dbb4 __cs3_isr_interrupt_203\r
+ 0x0000dbb4 __cs3_isr_interrupt_126\r
+ 0x0000dbb4 __cs3_isr_interrupt_197\r
+ 0x0000dbb4 __cs3_isr_interrupt_23\r
+ 0x0000dbb4 __cs3_isr_interrupt_64\r
+ 0x0000dbb4 __cs3_isr_interrupt_251\r
+ 0x0000dbb4 __cs3_isr_interrupt_164\r
+ 0x0000dbb4 __cs3_isr_interrupt_72\r
+ *fill* 0x0000dbbe 0x2 00\r
+ .text 0x0000dbc0 0xa c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libcs3coldfire.a(coldfire_isr_unimplemented_opcode.o)\r
+ 0x0000dbc0 __cs3_isr_unimplemented_opcode\r
+ 0x0000dbc0 __cs3_isr_unimplemented_line_a_opcode\r
+ 0x0000dbc0 __cs3_isr_unimplemented_line_f_opcode\r
+ *fill* 0x0000dbca 0x2 00\r
+ .text 0x0000dbcc 0xa c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libcs3coldfire.a(coldfire_isr_breakpoint_debug_interrupt.o)\r
+ 0x0000dbcc __cs3_isr_breakpoint_debug_interrupt\r
+ 0x0000dbcc __cs3_isr_pc_breakpoint_debug_interrupt\r
+ 0x0000dbcc __cs3_isr_non_pc_breakpoint_debug_interrupt\r
+ *fill* 0x0000dbd6 0x2 00\r
+ .text 0x0000dbd8 0xa c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libcs3coldfire.a(coldfire_isr_trap_interrupt.o)\r
+ 0x0000dbd8 __cs3_isr_trap7\r
+ 0x0000dbd8 __cs3_isr_trap2\r
+ 0x0000dbd8 __cs3_isr_trap14\r
+ 0x0000dbd8 __cs3_isr_trap13\r
+ 0x0000dbd8 __cs3_isr_trap_interrupt\r
+ 0x0000dbd8 __cs3_isr_trap8\r
+ 0x0000dbd8 __cs3_isr_trap9\r
+ 0x0000dbd8 __cs3_isr_trap1\r
+ 0x0000dbd8 __cs3_isr_trap4\r
+ 0x0000dbd8 __cs3_isr_trap15\r
+ 0x0000dbd8 __cs3_isr_trap6\r
+ 0x0000dbd8 __cs3_isr_trap10\r
+ 0x0000dbd8 __cs3_isr_trap5\r
+ 0x0000dbd8 __cs3_isr_trap0\r
+ 0x0000dbd8 __cs3_isr_trap3\r
+ 0x0000dbd8 __cs3_isr_trap12\r
+ 0x0000dbd8 __cs3_isr_trap11\r
+ *fill* 0x0000dbe2 0x2 00\r
+ .text 0x0000dbe4 0xa c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libcs3coldfire.a(coldfire_isr_fp_interrupt.o)\r
+ 0x0000dbe4 __cs3_isr_fp_divide_by_zero\r
+ 0x0000dbe4 __cs3_isr_fp_interrupt\r
+ 0x0000dbe4 __cs3_isr_fp_operand_error\r
+ 0x0000dbe4 __cs3_isr_fp_inexact_result\r
+ 0x0000dbe4 __cs3_isr_fp_input_not_a_number\r
+ 0x0000dbe4 __cs3_isr_fp_overflow\r
+ 0x0000dbe4 __cs3_isr_fp_input_denormalized_number\r
+ 0x0000dbe4 __cs3_isr_fp_branch_unordered\r
+ 0x0000dbe4 __cs3_isr_fp_underflow\r
+ *fill* 0x0000dbee 0x2 00\r
+ .text 0x0000dbf0 0xa c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libcs3coldfire.a(coldfire_isr_access_error.o)\r
+ 0x0000dbf0 __cs3_isr_access_error\r
+ *fill* 0x0000dbfa 0x2 00\r
+ .text 0x0000dbfc 0xa c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libcs3coldfire.a(coldfire_isr_address_error.o)\r
+ 0x0000dbfc __cs3_isr_address_error\r
+ *fill* 0x0000dc06 0x2 00\r
+ .text 0x0000dc08 0xa c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libcs3coldfire.a(coldfire_isr_illegal_instruction.o)\r
+ 0x0000dc08 __cs3_isr_illegal_instruction\r
+ *fill* 0x0000dc12 0x2 00\r
+ .text 0x0000dc14 0xa c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libcs3coldfire.a(coldfire_isr_divide_by_zero.o)\r
+ 0x0000dc14 __cs3_isr_divide_by_zero\r
+ *fill* 0x0000dc1e 0x2 00\r
+ .text 0x0000dc20 0xa c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libcs3coldfire.a(coldfire_isr_privilege_violation.o)\r
+ 0x0000dc20 __cs3_isr_privilege_violation\r
+ *fill* 0x0000dc2a 0x2 00\r
+ .text 0x0000dc2c 0xa c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libcs3coldfire.a(coldfire_isr_trace.o)\r
+ 0x0000dc2c __cs3_isr_trace\r
+ *fill* 0x0000dc36 0x2 00\r
+ .text 0x0000dc38 0xa c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libcs3coldfire.a(coldfire_isr_format_error.o)\r
+ 0x0000dc38 __cs3_isr_format_error\r
+ *fill* 0x0000dc42 0x2 00\r
+ .text 0x0000dc44 0xa c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libcs3coldfire.a(coldfire_isr_spurious_interrupt.o)\r
+ 0x0000dc44 __cs3_isr_spurious_interrupt\r
+ *fill* 0x0000dc4e 0x2 00\r
+ .text 0x0000dc50 0xa c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libcs3coldfire.a(coldfire_isr_unsupported_instruction.o)\r
+ 0x0000dc50 __cs3_isr_unsupported_instruction\r
+ *fill* 0x0000dc5a 0x2 00\r
+ .text 0x0000dc5c 0xe c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libc.a(lib_a-errno.o)\r
+ 0x0000dc5c __errno\r
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+ .text 0x0000dc6c 0x60 c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libc.a(lib_a-init.o)\r
+ 0x0000dc6c __libc_init_array\r
+ .text 0x0000dccc 0x0 c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libcs3.a(heap.o)\r
+ 0x0000dccc . = ALIGN (0x4)\r
+ *crtbegin.o(.jcr)\r
+ *(EXCLUDE_FILE(*crtend.o) .jcr)\r
+ *crtend.o(.jcr)\r
+ 0x0000dccc . = ALIGN (0x4)\r
+ *(.gcc_except_table .gcc_except_table.*)\r
+\r
+.eh_frame_hdr\r
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+\r
+.eh_frame 0x0000dccc 0x6c\r
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+ .eh_frame 0x0000dd0c 0x2c c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/m5208\libgcc.a(_umoddi3.o)\r
+ 0x40 (size before relaxing)\r
+\r
+.rodata 0x0000dd38 0x3d0\r
+ *(.rodata .rodata.* .gnu.linkonce.r.*)\r
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+ .rodata.ucExpectedStackBytes.3510\r
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+ .rodata 0x0000dec0 0x4 c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libc.a(lib_a-impure.o)\r
+ 0x0000dec0 _global_impure_ptr\r
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+ .rodata.str1.1\r
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+ .rodata 0x0000df1b 0x20 c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libc.a(lib_a-vfprintf.o)\r
+ .rodata.str1.1\r
+ 0x0000df3b 0xd c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libc.a(lib_a-dtoa.o)\r
+ 0xf (size before relaxing)\r
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+ 0x0000df48 0xd c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libc.a(lib_a-locale.o)\r
+ 0x10 (size before relaxing)\r
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+ .rodata 0x0000df8a 0x124 c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libc.a(lib_a-mprec.o)\r
+ 0x0000e07a __mprec_tinytens\r
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+ *(.preinit_array)\r
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+ .ctors.65535 0x0000e0c0 0x4 c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libc.a(lib_a-__call_atexit.o)\r
+ .ctors.65535 0x0000e0c4 0x4 c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libcs3.a(m5282evb-reset.o)\r
+ *crtend.o(.ctors)\r
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+ *(SORT(.dtors.*))\r
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+ *(.lit)\r
+ 0x0000e0c8 . = ALIGN (0x4)\r
+ 0x0000e0c8 __cs3_regions = .\r
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+ 0x0000e0d8 0x4 LONG 0x6088 __cs3_region_zero_size_ram\r
+ 0x0000e0dc 0x4 LONG 0x0\r
+ 0x0000e0e0 0x4 LONG 0xf0000000 __cs3_region_init_rombar\r
+ 0x0000e0e4 0x4 LONG 0xf0000000 __cs3_region_start_rombar\r
+ 0x0000e0e8 0x4 LONG 0x0 __cs3_region_init_size_rombar\r
+ 0x0000e0ec 0x4 LONG 0x0 __cs3_region_zero_size_rombar\r
+ 0x0000e0f0 0x4 LONG 0x0\r
+ 0x0000e0f4 0x4 LONG 0x20000000 __cs3_region_init_rambar\r
+ 0x0000e0f8 0x4 LONG 0x20000000 __cs3_region_start_rambar\r
+ 0x0000e0fc 0x4 LONG 0x0 __cs3_region_init_size_rambar\r
+ 0x0000e100 0x4 LONG 0x0 __cs3_region_zero_size_rambar\r
+ 0x0000e104 __cs3_regions_end = .\r
+ 0x0000e108 . = ALIGN (0x8)\r
+ *fill* 0x0000e104 0x4 00\r
+ 0x0000e108 . = ALIGN (0x8)\r
+ 0x0000e108 _etext = .\r
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+ 0xffe00000 __cs3_region_start_rom = .\r
+ *(.cs3.region-head.rom)\r
+ *(.rom)\r
+ 0xffe00000 . = ALIGN (0x8)\r
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+.cs3.rom.bss 0xffe00000 0x0\r
+ *(.rom.b)\r
+ 0xffe00000 . = ALIGN (0x8)\r
+ 0x00000000 __cs3_region_end_rom = (__cs3_region_start_rom + 0x200000)\r
+ 0x00200000 __cs3_region_size_rom = 0x200000\r
+ 0xffe00000 __cs3_region_init_rom = LOADADDR (.cs3.rom)\r
+ 0x00000000 __cs3_region_init_size_rom = (LOADADDR (.cs3.rom.bss) - LOADADDR (.cs3.rom))\r
+ 0x00000000 __cs3_region_zero_size_rom = SIZEOF (.cs3.rom.bss)\r
+\r
+.cs3.rombar 0xf0000000 0x0\r
+ 0xf0000000 __cs3_region_start_rombar = .\r
+ *(.cs3.region-head.rombar)\r
+ *(.rombar)\r
+ 0xf0000000 . = ALIGN (0x8)\r
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+ 0x00080000 __cs3_region_size_rombar = 0x80000\r
+ 0xf0000000 __cs3_region_init_rombar = LOADADDR (.cs3.rombar)\r
+ 0x00000000 __cs3_region_init_size_rombar = (LOADADDR (.cs3.rombar.bss) - LOADADDR (.cs3.rombar))\r
+ 0x00000000 __cs3_region_zero_size_rombar = SIZEOF (.cs3.rombar.bss)\r
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+.cs3.rambar 0x20000000 0x0\r
+ 0x20000000 __cs3_region_start_rambar = .\r
+ *(.cs3.region-head.rambar)\r
+ *(.rambar)\r
+ 0x20000000 . = ALIGN (0x8)\r
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+.cs3.rambar.bss\r
+ 0x20000000 0x0\r
+ *(.rambar.b)\r
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+ 0x00010000 __cs3_region_size_rambar = 0x10000\r
+ 0x20000000 __cs3_region_init_rambar = LOADADDR (.cs3.rambar)\r
+ 0x00000000 __cs3_region_init_size_rambar = (LOADADDR (.cs3.rambar.bss) - LOADADDR (.cs3.rambar))\r
+ 0x00000000 __cs3_region_zero_size_rambar = SIZEOF (.cs3.rambar.bss)\r
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+.cs3.ipsbar 0x40000000 0x0\r
+ 0x40000000 __cs3_region_start_ipsbar = .\r
+ *(.cs3.region-head.ipsbar)\r
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+ 0x20000000 __cs3_region_size_ipsbar = 0x20000000\r
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+ *(.got.plt)\r
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+ *(.shdata)\r
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+ .debug_frame 0x00001ff8 0x40 c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/m5208\libgcc.a(_umoddi3.o)\r
+ .debug_frame 0x00002038 0x144 c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/m5208\libgcc.a(fpgnulib.o)\r
+ .debug_frame 0x0000217c 0x3c c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libcs3.a(start_c.o)\r
+ .debug_frame 0x000021b8 0x2c c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libcs3hosted.a(hosted-_exit.o)\r
+ .debug_frame 0x000021e4 0x30 c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libcs3hosted.a(hosted-close.o)\r
+ .debug_frame 0x00002214 0x38 c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libcs3hosted.a(hosted-fstat.o)\r
+ .debug_frame 0x0000224c 0x30 c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libcs3hosted.a(hosted-isatty.o)\r
+ .debug_frame 0x0000227c 0x38 c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libcs3hosted.a(hosted-lseek.o)\r
+ .debug_frame 0x000022b4 0x30 c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libcs3hosted.a(hosted-read.o)\r
+ .debug_frame 0x000022e4 0x2c c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libcs3hosted.a(hosted-sbrk.o)\r
+ .debug_frame 0x00002310 0x30 c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libcs3hosted.a(hosted-write.o)\r
+ .debug_frame 0x00002340 0xac c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libcs3hosted.a(hosted-gdb.o)\r
+ .debug_frame 0x000023ec 0x2c c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libcs3coldfire.a(coldfire_isr_other_interrupt.o)\r
+ .debug_frame 0x00002418 0x2c c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libcs3coldfire.a(coldfire_isr_unimplemented_opcode.o)\r
+ .debug_frame 0x00002444 0x2c c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libcs3coldfire.a(coldfire_isr_breakpoint_debug_interrupt.o)\r
+ .debug_frame 0x00002470 0x2c c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libcs3coldfire.a(coldfire_isr_trap_interrupt.o)\r
+ .debug_frame 0x0000249c 0x2c c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libcs3coldfire.a(coldfire_isr_fp_interrupt.o)\r
+ .debug_frame 0x000024c8 0x2c c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libcs3coldfire.a(coldfire_isr_access_error.o)\r
+ .debug_frame 0x000024f4 0x2c c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libcs3coldfire.a(coldfire_isr_address_error.o)\r
+ .debug_frame 0x00002520 0x2c c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libcs3coldfire.a(coldfire_isr_illegal_instruction.o)\r
+ .debug_frame 0x0000254c 0x2c c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libcs3coldfire.a(coldfire_isr_divide_by_zero.o)\r
+ .debug_frame 0x00002578 0x2c c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libcs3coldfire.a(coldfire_isr_privilege_violation.o)\r
+ .debug_frame 0x000025a4 0x2c c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libcs3coldfire.a(coldfire_isr_trace.o)\r
+ .debug_frame 0x000025d0 0x2c c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libcs3coldfire.a(coldfire_isr_format_error.o)\r
+ .debug_frame 0x000025fc 0x2c c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libcs3coldfire.a(coldfire_isr_spurious_interrupt.o)\r
+ .debug_frame 0x00002628 0x2c c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libcs3coldfire.a(coldfire_isr_unsupported_instruction.o)\r
+ .debug_frame 0x00002654 0x2c c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libc.a(lib_a-errno.o)\r
+ .debug_frame 0x00002680 0x34 c:/devtools/codesourcery_coldfire/sourcery g++ lite/bin/../lib/gcc/m68k-elf/4.2.3/../../../../m68k-elf/lib/m5208\libc.a(lib_a-init.o)\r
+\r
+.debug_str 0x00000000 0x2c4\r
+ *(.debug_str)\r
+ .debug_str 0x00000000 0x3d ./bin/BlockQ.o\r
+ .debug_str 0x0000003d 0x2c ./bin/blocktim.o\r
+ .debug_str 0x00000069 0x18 ./bin/death.o\r
+ .debug_str 0x00000081 0xd ./bin/PollQ.o\r
+ .debug_str 0x0000008e 0x1d ./bin/semtest.o\r
+ .debug_str 0x000000ab 0x14 ./bin/GenQTest.o\r
+ .debug_str 0x000000bf 0x1c ./bin/QPeek.o\r
+ .debug_str 0x000000db 0xd ./bin/recmutex.o\r
+ .debug_str 0x000000e8 0x36 ./bin/list.o\r
+ .debug_str 0x0000011e 0xe2 ./bin/tasks.o\r
+ .debug_str 0x00000200 0xae ./bin/queue.o\r
+ .debug_str 0x000002ae 0x16 ./bin/heap_2.o\r
+\r
+.debug_loc 0x00000000 0xf00\r
+ *(.debug_loc)\r
+ .debug_loc 0x00000000 0x60 ./bin/main.o\r
+ .debug_loc 0x00000060 0x60 ./bin/ParTest.o\r
+ .debug_loc 0x000000c0 0x80 ./bin/BlockQ.o\r
+ .debug_loc 0x00000140 0x80 ./bin/blocktim.o\r
+ .debug_loc 0x000001c0 0x80 ./bin/death.o\r
+ .debug_loc 0x00000240 0x60 ./bin/integer.o\r
+ .debug_loc 0x000002a0 0x80 ./bin/PollQ.o\r
+ .debug_loc 0x00000320 0x60 ./bin/semtest.o\r
+ .debug_loc 0x00000380 0xc0 ./bin/GenQTest.o\r
+ .debug_loc 0x00000440 0xc0 ./bin/QPeek.o\r
+ .debug_loc 0x00000500 0xa0 ./bin/recmutex.o\r
+ .debug_loc 0x000005a0 0xe0 ./bin/port.o\r
+ .debug_loc 0x00000680 0xa0 ./bin/list.o\r
+ .debug_loc 0x00000720 0x4c0 ./bin/tasks.o\r
+ .debug_loc 0x00000be0 0x280 ./bin/queue.o\r
+ .debug_loc 0x00000e60 0x40 ./bin/heap_2.o\r
+ .debug_loc 0x00000ea0 0x60 ./bin/FreeRTOS_Timer.o\r
+\r
+.debug_macinfo 0x00000000 0x1e5a94\r
+ *(.debug_macinfo)\r
+ .debug_macinfo\r
+ 0x00000000 0x1e3ac ./bin/main.o\r
+ .debug_macinfo\r
+ 0x0001e3ac 0x1ad25 ./bin/ParTest.o\r
+ .debug_macinfo\r
+ 0x000390d1 0x1d0da ./bin/BlockQ.o\r
+ .debug_macinfo\r
+ 0x000561ab 0x1b482 ./bin/blocktim.o\r
+ .debug_macinfo\r
+ 0x0007162d 0x1ca2d ./bin/death.o\r
+ .debug_macinfo\r
+ 0x0008e05a 0x1cb1c ./bin/integer.o\r
+ .debug_macinfo\r
+ 0x000aab76 0x1d209 ./bin/PollQ.o\r
+ .debug_macinfo\r
+ 0x000c7d7f 0x1d725 ./bin/semtest.o\r
+ .debug_macinfo\r
+ 0x000e54a4 0x1d728 ./bin/GenQTest.o\r
+ .debug_macinfo\r
+ 0x00102bcc 0x1d738 ./bin/QPeek.o\r
+ .debug_macinfo\r
+ 0x00120304 0x1ba17 ./bin/recmutex.o\r
+ .debug_macinfo\r
+ 0x0013bd1b 0x1ac83 ./bin/port.o\r
+ .debug_macinfo\r
+ 0x0015699e 0x1c84d ./bin/list.o\r
+ .debug_macinfo\r
+ 0x001731eb 0x1e157 ./bin/tasks.o\r
+ .debug_macinfo\r
+ 0x00191342 0x1d2af ./bin/queue.o\r
+ .debug_macinfo\r
+ 0x001ae5f1 0x1cd23 ./bin/heap_2.o\r
+ .debug_macinfo\r
+ 0x001cb314 0x1a780 ./bin/FreeRTOS_Timer.o\r
+\r
+.debug_weaknames\r
+ *(.debug_weaknames)\r
+\r
+.debug_funcnames\r
+ *(.debug_funcnames)\r
+\r
+.debug_typenames\r
+ *(.debug_typenames)\r
+\r
+.debug_varnames\r
+ *(.debug_varnames)\r
+OUTPUT(./bin/RTOSDemo.elf elf32-m68k)\r
+\r
+.comment 0x00000000 0x2a8\r
+ .comment 0x00000000 0x28 ./bin/main.o\r
+ .comment 0x00000028 0x28 ./bin/ParTest.o\r
+ .comment 0x00000050 0x28 ./bin/BlockQ.o\r
+ .comment 0x00000078 0x28 ./bin/blocktim.o\r
+ .comment 0x000000a0 0x28 ./bin/death.o\r
+ .comment 0x000000c8 0x28 ./bin/integer.o\r
+ .comment 0x000000f0 0x28 ./bin/PollQ.o\r
+ .comment 0x00000118 0x28 ./bin/semtest.o\r
+ .comment 0x00000140 0x28 ./bin/GenQTest.o\r
+ .comment 0x00000168 0x28 ./bin/QPeek.o\r
+ .comment 0x00000190 0x28 ./bin/recmutex.o\r
+ .comment 0x000001b8 0x28 ./bin/port.o\r
+ .comment 0x000001e0 0x28 ./bin/list.o\r
+ .comment 0x00000208 0x28 ./bin/tasks.o\r
+ .comment 0x00000230 0x28 ./bin/queue.o\r
+ .comment 0x00000258 0x28 ./bin/heap_2.o\r
+ .comment 0x00000280 0x28 ./bin/FreeRTOS_Timer.o\r
--- /dev/null
+/* Linker script for m5282evb
+ *
+ * Version:Sourcery G++ Lite 4.2-125
+ * BugURL:https://support.codesourcery.com/GNUToolchain/
+ *
+ * Copyright 2007, 2008 CodeSourcery.
+ *
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply. */
+
+OUTPUT_ARCH(m68k)
+ENTRY(_start)
+SEARCH_DIR(.)
+GROUP(-lgcc -lc -lcs3 -lcs3hosted -lcs3coldfire)
+
+MEMORY
+{
+ ram (rwx) : ORIGIN = 0x00000000, LENGTH = 16M
+ rom (rx) : ORIGIN = 0xFFE00000, LENGTH = 2M
+ rombar (rx) : ORIGIN = 0xf0000000, LENGTH = 512K
+ rambar (rwx) : ORIGIN = 0x20000000, LENGTH = 64K
+ ipsbar (rw) : ORIGIN = 0x40000000, LENGTH = 0x20000000
+}
+
+/* These force the linker to search for particular symbols from
+ * the start of the link process and thus ensure the user's
+ * overrides are picked up
+ */
+EXTERN(__cs3_reset_m5282evb)
+INCLUDE coldfire-names.inc
+EXTERN(__cs3_interrupt_vector_coldfire)
+EXTERN(__cs3_start_c main __cs3_stack __cs3_heap_end)
+EXTERN(_start)
+/* force exit to be picked up in a hosted or os environment */
+EXTERN(exit atexit)
+
+PROVIDE(__cs3_heap_start = _end);
+PROVIDE(__cs3_heap_end = __cs3_region_start_ram + __cs3_region_size_ram);
+PROVIDE(__cs3_region_num = (__cs3_regions_end - __cs3_regions) / 20);
+PROVIDE(__cs3_stack = __cs3_region_start_ram + __cs3_region_size_ram);
+
+SECTIONS
+{
+
+ .text :
+ {
+ CREATE_OBJECT_SYMBOLS
+ __cs3_region_start_ram = .;
+ *(.cs3.region-head.ram)
+ ASSERT (. == __cs3_region_start_ram, ".cs3.region-head.ram not permitted");
+ __cs3_interrupt_vector = __cs3_interrupt_vector_coldfire;
+ *(.cs3.interrupt_vector)
+ /* Make sure we pulled in an interrupt vector. */
+ ASSERT (. != __cs3_interrupt_vector_coldfire, "No interrupt vector");
+
+ PROVIDE(__cs3_reset_m5282evb = _start);
+ __cs3_reset = __cs3_reset_m5282evb;
+ *(.cs3.reset)
+
+ *(.text .text.* .gnu.linkonce.t.*)
+
+ . = ALIGN(0x4);
+ KEEP (*crtbegin.o(.jcr))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .jcr))
+ KEEP (*crtend.o(.jcr))
+
+ . = ALIGN(0x4);
+ *(.gcc_except_table .gcc_except_table.*)
+ } >ram
+ .eh_frame_hdr : ALIGN (4)
+ {
+ KEEP (*(.eh_frame_hdr))
+ } >ram
+ .eh_frame : ALIGN (4)
+ {
+ KEEP (*(.eh_frame))
+ } >ram
+ .rodata : ALIGN (4)
+ {
+ *(.rodata .rodata.* .gnu.linkonce.r.*)
+
+ . = ALIGN(4);
+ _init = .;
+ LONG (0x4e560000) /* linkw %fp,#0 */
+ KEEP(*(.init))
+ SHORT (0x4e5e) /* unlk %fp */
+ SHORT (0x4e75) /* rts */
+
+ . = ALIGN(4);
+ __preinit_array_start = .;
+ KEEP (*(.preinit_array))
+ __preinit_array_end = .;
+
+ . = ALIGN(4);
+ __init_array_start = .;
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array))
+ __init_array_end = .;
+
+ . = ALIGN(4);
+ _fini = .;
+ LONG (0x4e560000) /* linkw %fp,#0 */
+ KEEP(*(.fini))
+ SHORT (0x4e5e) /* unlk %fp */
+ SHORT (0x4e75) /* rts */
+
+ . = ALIGN(4);
+ __fini_array_start = .;
+ KEEP (*(.fini_array))
+ KEEP (*(SORT(.fini_array.*)))
+ __fini_array_end = .;
+
+ . = ALIGN(0x4);
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*crtend.o(.ctors))
+
+ . = ALIGN(0x4);
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*crtend.o(.dtors))
+
+ *(.lit)
+
+ . = ALIGN(4);
+ __cs3_regions = .;
+ LONG (0)
+ LONG (__cs3_region_init_ram)
+ LONG (__cs3_region_start_ram)
+ LONG (__cs3_region_init_size_ram)
+ LONG (__cs3_region_zero_size_ram)
+ LONG (0)
+ LONG (__cs3_region_init_rombar)
+ LONG (__cs3_region_start_rombar)
+ LONG (__cs3_region_init_size_rombar)
+ LONG (__cs3_region_zero_size_rombar)
+ LONG (0)
+ LONG (__cs3_region_init_rambar)
+ LONG (__cs3_region_start_rambar)
+ LONG (__cs3_region_init_size_rambar)
+ LONG (__cs3_region_zero_size_rambar)
+ __cs3_regions_end = .;
+
+ . = ALIGN (8);
+ . = ALIGN (8);
+ _etext = .;
+ } >ram
+
+ .cs3.rom : ALIGN (8)
+ {
+ __cs3_region_start_rom = .;
+ *(.cs3.region-head.rom)
+ *(.rom)
+ . = ALIGN (8);
+ } >rom
+ .cs3.rom.bss :
+ {
+ *(.rom.b)
+ . = ALIGN (8);
+ } >rom
+ /* __cs3_region_end_rom is deprecated */
+ __cs3_region_end_rom = __cs3_region_start_rom + LENGTH(rom);
+ __cs3_region_size_rom = LENGTH(rom);
+ __cs3_region_init_rom = LOADADDR (.cs3.rom);
+ __cs3_region_init_size_rom = LOADADDR (.cs3.rom.bss) - LOADADDR (.cs3.rom);
+ __cs3_region_zero_size_rom = SIZEOF(.cs3.rom.bss);
+
+ .cs3.rombar : ALIGN (8)
+ {
+ __cs3_region_start_rombar = .;
+ *(.cs3.region-head.rombar)
+ *(.rombar)
+ . = ALIGN (8);
+ } >rombar
+ .cs3.rombar.bss :
+ {
+ *(.rombar.b)
+ . = ALIGN (8);
+ } >rombar
+ /* __cs3_region_end_rombar is deprecated */
+ __cs3_region_end_rombar = __cs3_region_start_rombar + LENGTH(rombar);
+ __cs3_region_size_rombar = LENGTH(rombar);
+ __cs3_region_init_rombar = LOADADDR (.cs3.rombar);
+ __cs3_region_init_size_rombar = LOADADDR (.cs3.rombar.bss) - LOADADDR (.cs3.rombar);
+ __cs3_region_zero_size_rombar = SIZEOF(.cs3.rombar.bss);
+
+ .cs3.rambar : ALIGN (8)
+ {
+ __cs3_region_start_rambar = .;
+ *(.cs3.region-head.rambar)
+ *(.rambar)
+ . = ALIGN (8);
+ } >rambar
+ .cs3.rambar.bss :
+ {
+ *(.rambar.b)
+ . = ALIGN (8);
+ } >rambar
+ /* __cs3_region_end_rambar is deprecated */
+ __cs3_region_end_rambar = __cs3_region_start_rambar + LENGTH(rambar);
+ __cs3_region_size_rambar = LENGTH(rambar);
+ __cs3_region_init_rambar = LOADADDR (.cs3.rambar);
+ __cs3_region_init_size_rambar = LOADADDR (.cs3.rambar.bss) - LOADADDR (.cs3.rambar);
+ __cs3_region_zero_size_rambar = SIZEOF(.cs3.rambar.bss);
+
+ .cs3.ipsbar :
+ {
+ __cs3_region_start_ipsbar = .;
+ *(.cs3.region-head.ipsbar)
+ . = ALIGN (8);
+ } >ipsbar
+ /* __cs3_region_end_ipsbar is deprecated */
+ __cs3_region_end_ipsbar = __cs3_region_start_ipsbar + LENGTH(ipsbar);
+ __cs3_region_size_ipsbar = LENGTH(ipsbar);
+
+ .data : ALIGN (8)
+ {
+
+ *(.got.plt) *(.got)
+ *(.shdata)
+ *(.data .data.* .gnu.linkonce.d.*)
+ . = ALIGN (8);
+ *(.ram)
+ _edata = .;
+ } >ram
+ .bss :
+ {
+ *(.shbss)
+ *(.bss .bss.* .gnu.linkonce.b.*)
+ *(COMMON)
+ . = ALIGN (8);
+ *(.ram.b)
+ _end = .;
+ __end = .;
+ } >ram
+ /* __cs3_region_end_ram is deprecated */
+ __cs3_region_end_ram = __cs3_region_start_ram + LENGTH(ram);
+ __cs3_region_size_ram = LENGTH(ram);
+ __cs3_region_init_ram = LOADADDR (.text);
+ __cs3_region_init_size_ram = _edata - ADDR (.text);
+ __cs3_region_zero_size_ram = _end - _edata;
+
+ .stab 0 (NOLOAD) : { *(.stab) }
+ .stabstr 0 (NOLOAD) : { *(.stabstr) }
+ /* DWARF debug sections.
+ * Symbols in the DWARF debugging sections are relative to the beginning
+ * of the section so we begin them at 0. */
+ /* DWARF 1 */
+ .debug 0 : { *(.debug) }
+ .line 0 : { *(.line) }
+ /* GNU DWARF 1 extensions */
+ .debug_srcinfo 0 : { *(.debug_srcinfo) }
+ .debug_sfnames 0 : { *(.debug_sfnames) }
+ /* DWARF 1.1 and DWARF 2 */
+ .debug_aranges 0 : { *(.debug_aranges) }
+ .debug_pubnames 0 : { *(.debug_pubnames) }
+ /* DWARF 2 */
+ .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
+ .debug_abbrev 0 : { *(.debug_abbrev) }
+ .debug_line 0 : { *(.debug_line) }
+ .debug_frame 0 : { *(.debug_frame) }
+ .debug_str 0 : { *(.debug_str) }
+ .debug_loc 0 : { *(.debug_loc) }
+ .debug_macinfo 0 : { *(.debug_macinfo) }
+ /* SGI/MIPS DWARF 2 extensions */
+ .debug_weaknames 0 : { *(.debug_weaknames) }
+ .debug_funcnames 0 : { *(.debug_funcnames) }
+ .debug_typenames 0 : { *(.debug_typenames) }
+ .debug_varnames 0 : { *(.debug_varnames) }
+}
--- /dev/null
+/* Linker script for m5282evb
+ *
+ * Version:Sourcery G++ Lite 4.2-125
+ * BugURL:https://support.codesourcery.com/GNUToolchain/
+ *
+ * Copyright 2007, 2008 CodeSourcery.
+ *
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply. */
+
+OUTPUT_ARCH(m68k)
+ENTRY(_start)
+SEARCH_DIR(.)
+GROUP(-lgcc -lc -lcs3 -lcs3unhosted -lcs3coldfire)
+
+MEMORY
+{
+ ram (rwx) : ORIGIN = 0x00000000, LENGTH = 16M
+ rom (rx) : ORIGIN = 0xFFE00000, LENGTH = 2M
+ rombar (rx) : ORIGIN = 0xf0000000, LENGTH = 512K
+ rambar (rwx) : ORIGIN = 0x20000000, LENGTH = 64K
+ ipsbar (rw) : ORIGIN = 0x40000000, LENGTH = 0x20000000
+}
+
+/* These force the linker to search for particular symbols from
+ * the start of the link process and thus ensure the user's
+ * overrides are picked up
+ */
+EXTERN(__cs3_reset_m5282evb)
+INCLUDE coldfire-names.inc
+EXTERN(__cs3_interrupt_vector_coldfire)
+EXTERN(__cs3_start_c main __cs3_stack __cs3_heap_end)
+EXTERN(_start)
+
+PROVIDE(__cs3_heap_start = _end);
+PROVIDE(__cs3_heap_end = __cs3_region_start_ram + __cs3_region_size_ram);
+PROVIDE(__cs3_region_num = (__cs3_regions_end - __cs3_regions) / 20);
+PROVIDE(__cs3_stack = __cs3_region_start_ram + __cs3_region_size_ram);
+
+SECTIONS
+{
+
+ .text :
+ {
+ CREATE_OBJECT_SYMBOLS
+ __cs3_region_start_ram = .;
+ *(.cs3.region-head.ram)
+ ASSERT (. == __cs3_region_start_ram, ".cs3.region-head.ram not permitted");
+ __cs3_interrupt_vector = __cs3_interrupt_vector_coldfire;
+ *(.cs3.interrupt_vector)
+ /* Make sure we pulled in an interrupt vector. */
+ ASSERT (. != __cs3_interrupt_vector_coldfire, "No interrupt vector");
+
+ PROVIDE(__cs3_reset_m5282evb = _start);
+ __cs3_reset = __cs3_reset_m5282evb;
+ *(.cs3.reset)
+
+ *(.text .text.* .gnu.linkonce.t.*)
+
+ . = ALIGN(0x4);
+ KEEP (*crtbegin.o(.jcr))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .jcr))
+ KEEP (*crtend.o(.jcr))
+
+ . = ALIGN(0x4);
+ *(.gcc_except_table .gcc_except_table.*)
+ } >ram
+ .eh_frame_hdr : ALIGN (4)
+ {
+ KEEP (*(.eh_frame_hdr))
+ } >ram
+ .eh_frame : ALIGN (4)
+ {
+ KEEP (*(.eh_frame))
+ } >ram
+ .rodata : ALIGN (4)
+ {
+ *(.rodata .rodata.* .gnu.linkonce.r.*)
+
+ . = ALIGN(4);
+ _init = .;
+ LONG (0x4e560000) /* linkw %fp,#0 */
+ KEEP(*(.init))
+ SHORT (0x4e5e) /* unlk %fp */
+ SHORT (0x4e75) /* rts */
+
+ . = ALIGN(4);
+ __preinit_array_start = .;
+ KEEP (*(.preinit_array))
+ __preinit_array_end = .;
+
+ . = ALIGN(4);
+ __init_array_start = .;
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array))
+ __init_array_end = .;
+
+ . = ALIGN(4);
+ _fini = .;
+ LONG (0x4e560000) /* linkw %fp,#0 */
+ KEEP(*(.fini))
+ SHORT (0x4e5e) /* unlk %fp */
+ SHORT (0x4e75) /* rts */
+
+ . = ALIGN(4);
+ __fini_array_start = .;
+ KEEP (*(.fini_array))
+ KEEP (*(SORT(.fini_array.*)))
+ __fini_array_end = .;
+
+ . = ALIGN(0x4);
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*crtend.o(.ctors))
+
+ . = ALIGN(0x4);
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*crtend.o(.dtors))
+
+ *(.lit)
+
+ . = ALIGN(4);
+ __cs3_regions = .;
+ LONG (0)
+ LONG (__cs3_region_init_ram)
+ LONG (__cs3_region_start_ram)
+ LONG (__cs3_region_init_size_ram)
+ LONG (__cs3_region_zero_size_ram)
+ LONG (0)
+ LONG (__cs3_region_init_rombar)
+ LONG (__cs3_region_start_rombar)
+ LONG (__cs3_region_init_size_rombar)
+ LONG (__cs3_region_zero_size_rombar)
+ LONG (0)
+ LONG (__cs3_region_init_rambar)
+ LONG (__cs3_region_start_rambar)
+ LONG (__cs3_region_init_size_rambar)
+ LONG (__cs3_region_zero_size_rambar)
+ __cs3_regions_end = .;
+
+ . = ALIGN (8);
+ . = ALIGN (8);
+ _etext = .;
+ } >ram
+
+ .cs3.rom : ALIGN (8)
+ {
+ __cs3_region_start_rom = .;
+ *(.cs3.region-head.rom)
+ *(.rom)
+ . = ALIGN (8);
+ } >rom
+ .cs3.rom.bss :
+ {
+ *(.rom.b)
+ . = ALIGN (8);
+ } >rom
+ /* __cs3_region_end_rom is deprecated */
+ __cs3_region_end_rom = __cs3_region_start_rom + LENGTH(rom);
+ __cs3_region_size_rom = LENGTH(rom);
+ __cs3_region_init_rom = LOADADDR (.cs3.rom);
+ __cs3_region_init_size_rom = LOADADDR (.cs3.rom.bss) - LOADADDR (.cs3.rom);
+ __cs3_region_zero_size_rom = SIZEOF(.cs3.rom.bss);
+
+ .cs3.rombar : ALIGN (8)
+ {
+ __cs3_region_start_rombar = .;
+ *(.cs3.region-head.rombar)
+ *(.rombar)
+ . = ALIGN (8);
+ } >rombar
+ .cs3.rombar.bss :
+ {
+ *(.rombar.b)
+ . = ALIGN (8);
+ } >rombar
+ /* __cs3_region_end_rombar is deprecated */
+ __cs3_region_end_rombar = __cs3_region_start_rombar + LENGTH(rombar);
+ __cs3_region_size_rombar = LENGTH(rombar);
+ __cs3_region_init_rombar = LOADADDR (.cs3.rombar);
+ __cs3_region_init_size_rombar = LOADADDR (.cs3.rombar.bss) - LOADADDR (.cs3.rombar);
+ __cs3_region_zero_size_rombar = SIZEOF(.cs3.rombar.bss);
+
+ .cs3.rambar : ALIGN (8)
+ {
+ __cs3_region_start_rambar = .;
+ *(.cs3.region-head.rambar)
+ *(.rambar)
+ . = ALIGN (8);
+ } >rambar
+ .cs3.rambar.bss :
+ {
+ *(.rambar.b)
+ . = ALIGN (8);
+ } >rambar
+ /* __cs3_region_end_rambar is deprecated */
+ __cs3_region_end_rambar = __cs3_region_start_rambar + LENGTH(rambar);
+ __cs3_region_size_rambar = LENGTH(rambar);
+ __cs3_region_init_rambar = LOADADDR (.cs3.rambar);
+ __cs3_region_init_size_rambar = LOADADDR (.cs3.rambar.bss) - LOADADDR (.cs3.rambar);
+ __cs3_region_zero_size_rambar = SIZEOF(.cs3.rambar.bss);
+
+ .cs3.ipsbar :
+ {
+ __cs3_region_start_ipsbar = .;
+ *(.cs3.region-head.ipsbar)
+ . = ALIGN (8);
+ } >ipsbar
+ /* __cs3_region_end_ipsbar is deprecated */
+ __cs3_region_end_ipsbar = __cs3_region_start_ipsbar + LENGTH(ipsbar);
+ __cs3_region_size_ipsbar = LENGTH(ipsbar);
+
+ .data : ALIGN (8)
+ {
+
+ *(.got.plt) *(.got)
+ *(.shdata)
+ *(.data .data.* .gnu.linkonce.d.*)
+ . = ALIGN (8);
+ *(.ram)
+ _edata = .;
+ } >ram
+ .bss :
+ {
+ *(.shbss)
+ *(.bss .bss.* .gnu.linkonce.b.*)
+ *(COMMON)
+ . = ALIGN (8);
+ *(.ram.b)
+ _end = .;
+ __end = .;
+ } >ram
+ /* __cs3_region_end_ram is deprecated */
+ __cs3_region_end_ram = __cs3_region_start_ram + LENGTH(ram);
+ __cs3_region_size_ram = LENGTH(ram);
+ __cs3_region_init_ram = LOADADDR (.text);
+ __cs3_region_init_size_ram = _edata - ADDR (.text);
+ __cs3_region_zero_size_ram = _end - _edata;
+
+ .stab 0 (NOLOAD) : { *(.stab) }
+ .stabstr 0 (NOLOAD) : { *(.stabstr) }
+ /* DWARF debug sections.
+ * Symbols in the DWARF debugging sections are relative to the beginning
+ * of the section so we begin them at 0. */
+ /* DWARF 1 */
+ .debug 0 : { *(.debug) }
+ .line 0 : { *(.line) }
+ /* GNU DWARF 1 extensions */
+ .debug_srcinfo 0 : { *(.debug_srcinfo) }
+ .debug_sfnames 0 : { *(.debug_sfnames) }
+ /* DWARF 1.1 and DWARF 2 */
+ .debug_aranges 0 : { *(.debug_aranges) }
+ .debug_pubnames 0 : { *(.debug_pubnames) }
+ /* DWARF 2 */
+ .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
+ .debug_abbrev 0 : { *(.debug_abbrev) }
+ .debug_line 0 : { *(.debug_line) }
+ .debug_frame 0 : { *(.debug_frame) }
+ .debug_str 0 : { *(.debug_str) }
+ .debug_loc 0 : { *(.debug_loc) }
+ .debug_macinfo 0 : { *(.debug_macinfo) }
+ /* SGI/MIPS DWARF 2 extensions */
+ .debug_weaknames 0 : { *(.debug_weaknames) }
+ .debug_funcnames 0 : { *(.debug_funcnames) }
+ .debug_typenames 0 : { *(.debug_typenames) }
+ .debug_varnames 0 : { *(.debug_varnames) }
+}
--- /dev/null
+/*\r
+ FreeRTOS.org V5.0.3 - Copyright (C) 2003-2008 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS.org distribution.\r
+\r
+ FreeRTOS.org is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS.org is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS.org; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS.org, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section\r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ ***************************************************************************\r
+ * *\r
+ * SAVE TIME AND MONEY! We can port FreeRTOS.org to your own hardware, *\r
+ * and even write all or part of your application on your behalf. *\r
+ * See http://www.OpenRTOS.com for details of the services we provide to *\r
+ * expedite your project. *\r
+ * *\r
+ ***************************************************************************\r
+ ***************************************************************************\r
+\r
+ Please ensure to read the configuration and relevant port sections of the\r
+ online documentation.\r
+\r
+ http://www.FreeRTOS.org - Documentation, latest information, license and\r
+ contact details.\r
+\r
+ http://www.SafeRTOS.com - A version that is certified for use in safety\r
+ critical systems.\r
+\r
+ http://www.OpenRTOS.com - Commercial support, development, porting,\r
+ licensing and training services.\r
+*/\r
+\r
+\r
+/*\r
+ * Creates all the demo application tasks, then starts the scheduler. The WEB\r
+ * documentation provides more details of the standard demo application tasks.\r
+ * In addition to the standard demo tasks, the following tasks and tests are\r
+ * defined and/or created within this file:\r
+ *\r
+ * "Check" task - This only executes every five seconds but has a high priority\r
+ * to ensure it gets processor time. Its main function is to check that all the\r
+ * standard demo tasks are still operational. While no errors have been\r
+ * discovered the check task will toggle an LED every 5 seconds - the toggle\r
+ * rate increasing to 500ms then being a visual indication that at least one\r
+ * task has reported unexpected behaviour.\r
+ *\r
+ */\r
+\r
+/* Standard includes. */\r
+#include <stdio.h>\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "queue.h"\r
+#include "semphr.h"\r
+\r
+/* Demo app includes. */\r
+#include "BlockQ.h"\r
+#include "death.h"\r
+#include "integer.h"\r
+#include "blocktim.h"\r
+#include "flash.h"\r
+#include "partest.h"\r
+#include "semtest.h"\r
+#include "PollQ.h"\r
+#include "GenQTest.h"\r
+#include "QPeek.h"\r
+#include "recmutex.h"\r
+#include "IntQueue.h"\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* The time between cycles of the 'check' functionality (defined within the\r
+tick hook. */\r
+#define mainCHECK_DELAY ( ( portTickType ) 5000 / portTICK_RATE_MS )\r
+\r
+/* Task priorities. */\r
+#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
+#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 )\r
+#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 )\r
+#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
+#define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 )\r
+#define mainINTEGER_TASK_PRIORITY ( tskIDLE_PRIORITY )\r
+#define mainGEN_QUEUE_TASK_PRIORITY ( tskIDLE_PRIORITY )\r
+\r
+\r
+/*\r
+ * Configure the hardware for the demo.\r
+ */\r
+static void prvSetupHardware( void );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+int main( void )\r
+{\r
+ prvSetupHardware();\r
+\r
+ /* Start the standard demo tasks. */\r
+ vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY );\r
+ vCreateBlockTimeTasks();\r
+ vStartSemaphoreTasks( mainSEM_TEST_PRIORITY );\r
+ vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY );\r
+ vStartIntegerMathTasks( mainINTEGER_TASK_PRIORITY );\r
+ vStartGenericQueueTasks( mainGEN_QUEUE_TASK_PRIORITY );\r
+ vStartQueuePeekTasks();\r
+ vStartRecursiveMutexTasks();\r
+\r
+ /* The suicide tasks must be created last as they need to know how many\r
+ tasks were running prior to their creation in order to ascertain whether\r
+ or not the correct/expected number of tasks are running at any given time. */\r
+ vCreateSuicidalTasks( mainCREATOR_TASK_PRIORITY );\r
+\r
+ /* Start the scheduler. */\r
+ vTaskStartScheduler();\r
+\r
+ /* Will only get here if there was insufficient memory to create the idle\r
+ task. */\r
+ return 0;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void prvSetupHardware( void )\r
+{\r
+ vParTestInitialise();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationStackOverflowHook( xTaskHandle *pxTask, signed portCHAR *pcTaskName )\r
+{\r
+ ( void ) pxTask;\r
+ ( void ) pcTaskName;\r
+\r
+ for( ;; );\r
+}\r
+\r
+\r
projects / freertos / commitdiff