lpc1768.cfg abstracted and moved to lpc17xx.cfg

- Moved variant-independent code to lpc17xx.cfg, which will be included from
lpc17??.cfg files automatically.
- lpc1768.cfg filled with variant-dependent code.

Change-Id: I7dabe6ed7da7be640ed38c13aaaa096b8796d9a0
Signed-off-by: Vandra Akos <axos88@gmail.com>
Reviewed-on: http://openocd.zylin.com/675
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>

diff --git a/tcl/target/lpc1768.cfg b/tcl/target/lpc1768.cfg
index 8bcab9ba5dadcfaaa9551318e1ab980d7c492fd0..a436b30f69bbdee7b6bbb7257d909790eb0ece51 100644 (file)
--- a/tcl/target/lpc1768.cfg
+++ b/tcl/target/lpc1768.cfg
@@ -1,14 +1,8 @@
 # NXP LPC1768 Cortex-M3 with 512kB Flash and 32kB+32kB Local On-Chip SRAM,
-
-# LPC17xx chips support both JTAG and SWD transports.
-# Adapt based on what transport is active.
-source [find target/swj-dp.tcl]
-
-if { [info exists CHIPNAME] } {
-       set _CHIPNAME $CHIPNAME
-} else {
-       set _CHIPNAME lpc1768
-}
+set CHIPNAME lpc1768
+set CPUTAPID 0x4ba00477
+set CPURAMSIZE 0x8000
+set CPUROMSIZE 0x80000
 
 # After reset the chip is clocked by the ~4MHz internal RC oscillator.
 # When board-specific code (reset-init handler or device firmware)
@@ -17,70 +11,7 @@ if { [info exists CHIPNAME] } {
 # (The ROM code doing those updates cares about core clock speed...)
 #
 # CCLK is the core clock frequency in KHz
-if { [info exists CCLK] } {
-       set _CCLK $CCLK
-} else {
-       set _CCLK 4000
-}
-
-if { [info exists CPUTAPID] } {
-       set _CPUTAPID $CPUTAPID
-} else {
-       set _CPUTAPID 0x4ba00477
-}
-
-if { [info exists CPURAMSIZE] } {
-  set _CPURAMSIZE $CPURAMSIZE
-} else {
-  set _CPURAMSIZE 0x8000
-}
-
-if { [info exists CPUROMSIZE] } {
-  set _CPUROMSIZE $CPUROMSIZE
-} else {
-  set _CPUROMSIZE 0x80000
-}
-
-#delays on reset lines
-adapter_nsrst_delay 200
-jtag_ntrst_delay 200
-
-#jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
-swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
-
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m3 -chain-position $_TARGETNAME
-
-# LPC1768 has 32kB of SRAM In the ARMv7-M "Code" area (at 0x10000000)
-# and 32K more on AHB, in the ARMv7-M "SRAM" area, (at 0x2007c000).
-$_TARGETNAME configure -work-area-phys 0x10000000 -work-area-size $_CPURAMSIZE
-
-# LPC1768 has 512kB of flash memory, managed by ROM code (including a
-# boot loader which verifies the flash exception table's checksum).
-# flash bank <name> lpc2000 <base> <size> 0 0 <target#> <variant> <clock> [calc checksum]
-set _FLASHNAME $_CHIPNAME.flash
-flash bank $_FLASHNAME lpc2000 0x0 $_CPUROMSIZE 0 0 $_TARGETNAME \
-       lpc1700 $_CCLK calc_checksum
-
-# Run with *real slow* clock by default since the
-# boot rom could have been playing with the PLL, so
-# we have no idea what clock the target is running at.
-adapter_khz 10
-
-$_TARGETNAME configure -event reset-init {
-       # Do not remap 0x0000-0x0020 to anything but the flash (i.e. select
-       # "User Flash Mode" where interrupt vectors are _not_ remapped,
-       # and reside in flash instead).
-       #
-       # See Table 612. Memory Mapping Control register (MEMMAP - 0x400F C040) bit description
-       # Bit Symbol Value Description Reset
-       # value
-       # 0 MAP Memory map control. 0
-       # 0 Boot mode. A portion of the Boot ROM is mapped to address 0.
-       # 1 User mode. The on-chip Flash memory is mapped to address 0.
-       # 31:1 - Reserved. The value read from a reserved bit is not defined. NA
-       #
-       # http://ics.nxp.com/support/documents/microcontrollers/?scope=LPC1768&type=user
+set CCLK 4000
 
-       mww 0x400FC040 0x01
-}
+#Include the main configuration file.
+source [find target/lpc17xx.cfg];

diff --git a/tcl/target/lpc17xx.cfg b/tcl/target/lpc17xx.cfg
new file mode 100644 (file)
index 0000000..379bcfb
--- /dev/null
+++ b/tcl/target/lpc17xx.cfg
@@ -0,0 +1,93 @@
+# Main file for NXP LPC17xx Cortex-M3
+#
+# !!!!!!
+#
+# This file should not be included directly, rather
+# by the lpc1751.cfg, lpc1752.cfg, etc. which set the
+# needed variables to the appropriate values.
+#
+# !!!!!!
+
+# LPC17xx chips support both JTAG and SWD transports.
+# Adapt based on what transport is active.
+source [find target/swj-dp.tcl]
+
+if { [info exists CHIPNAME] } {
+       set _CHIPNAME $CHIPNAME
+} else {
+       error "_CHIPNAME not set. Please do not include lpc17xx.cfg directly, but the specific chip configuration file (lpc1751.cfg, lpc1764.cfg, etc)."
+}
+
+# After reset the chip is clocked by the ~4MHz internal RC oscillator.
+# When board-specific code (reset-init handler or device firmware)
+# configures another oscillator and/or PLL0, set CCLK to match; if
+# you don't, then flash erase and write operations may misbehave.
+# (The ROM code doing those updates cares about core clock speed...)
+#
+# CCLK is the core clock frequency in KHz
+if { [info exists CCLK] } {
+       set _CCLK $CCLK
+} else {
+       set _CCLK 4000
+}
+
+if { [info exists CPUTAPID] } {
+       set _CPUTAPID $CPUTAPID
+} else {
+       error "_CPUTAPID not set. Please do not include lpc17xx.cfg directly, but the specific chip configuration file (lpc1751.cfg, lpc1764.cfg, etc)."
+}
+
+if { [info exists CPURAMSIZE] } {
+  set _CPURAMSIZE $CPURAMSIZE
+} else {
+       error "_CPURAMSIZE not set. Please do not include lpc17xx.cfg directly, but the specific chip configuration file (lpc1751.cfg, lpc1764.cfg, etc)."
+}
+
+if { [info exists CPUROMSIZE] } {
+  set _CPUROMSIZE $CPUROMSIZE
+} else {
+       error "_CPUROMSIZE not set. Please do not include lpc17xx.cfg directly, but the specific chip configuration file (lpc1751.cfg, lpc1764.cfg, etc)."
+}
+
+#delays on reset lines
+adapter_nsrst_delay 200
+jtag_ntrst_delay 200
+
+#jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
+swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m3 -chain-position $_TARGETNAME
+
+# The LPC17xx devices have 8/16/32kB of SRAM In the ARMv7-M "Code" area (at 0x10000000)
+$_TARGETNAME configure -work-area-phys 0x10000000 -work-area-size $_CPURAMSIZE
+
+# The LPC17xx devies have 32/64/128/256/512kB of flash memory, managed by ROM code
+# (including a boot loader which verifies the flash exception table's checksum).
+# flash bank <name> lpc2000 <base> <size> 0 0 <target#> <variant> <clock> [calc checksum]
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME lpc2000 0x0 $_CPUROMSIZE 0 0 $_TARGETNAME \
+       lpc1700 $_CCLK calc_checksum
+
+# Run with *real slow* clock by default since the
+# boot rom could have been playing with the PLL, so
+# we have no idea what clock the target is running at.
+adapter_khz 10
+
+$_TARGETNAME configure -event reset-init {
+       # Do not remap 0x0000-0x0020 to anything but the flash (i.e. select
+       # "User Flash Mode" where interrupt vectors are _not_ remapped,
+       # and reside in flash instead).
+       #
+       # See Table 612. Memory Mapping Control register (MEMMAP - 0x400F C040) bit description
+       # Bit Symbol Value Description Reset
+       # value
+       # 0 MAP Memory map control. 0
+       # 0 Boot mode. A portion of the Boot ROM is mapped to address 0.
+       # 1 User mode. The on-chip Flash memory is mapped to address 0.
+       # 31:1 - Reserved. The value read from a reserved bit is not defined. NA
+       #
+       # http://ics.nxp.com/support/documents/microcontrollers/?scope=LPC1768&type=user
+
+       mww 0x400FC040 0x01
+}