]> git.sur5r.net Git - openocd/commitdiff
at91: add chip register definition and generic init support
authorJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Sat, 9 Apr 2011 16:06:36 +0000 (18:06 +0200)
committerØyvind Harboe <oyvind.harboe@zylin.com>
Sat, 9 Apr 2011 17:18:03 +0000 (19:18 +0200)
for
 - pio
 - pmc
 - rstc
 - wdt
 - sdramc
 - smc

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Cc: Nicolas Ferre <nicolas.ferre@atmel.com>
Cc: Patrice Vilchez <patrice.vilchez@atmel.com>
tcl/chip/atmel/at91/at91_pio.cfg [new file with mode: 0644]
tcl/chip/atmel/at91/at91_pmc.cfg [new file with mode: 0644]
tcl/chip/atmel/at91/at91_rstc.cfg [new file with mode: 0644]
tcl/chip/atmel/at91/at91_wdt.cfg [new file with mode: 0644]
tcl/chip/atmel/at91/at91sam9_init.cfg [new file with mode: 0644]
tcl/chip/atmel/at91/at91sam9_sdramc.cfg [new file with mode: 0644]
tcl/chip/atmel/at91/at91sam9_smc.cfg [new file with mode: 0644]
tcl/chip/atmel/at91/hardware.cfg [new file with mode: 0644]
tcl/chip/atmel/at91/sam9_smc.cfg [new file with mode: 0644]

diff --git a/tcl/chip/atmel/at91/at91_pio.cfg b/tcl/chip/atmel/at91/at91_pio.cfg
new file mode 100644 (file)
index 0000000..2373c19
--- /dev/null
@@ -0,0 +1,29 @@
+set PIO_PER    0x00    ;# Enable Register
+set PIO_PDR    0x04    ;# Disable Register
+set PIO_PSR    0x08    ;# Status Register
+set PIO_OER    0x10    ;# Output Enable Register
+set PIO_ODR    0x14    ;# Output Disable Register
+set PIO_OSR    0x18    ;# Output Status Register
+set PIO_IFER   0x20    ;# Glitch Input Filter Enable
+set PIO_IFDR   0x24    ;# Glitch Input Filter Disable
+set PIO_IFSR   0x28    ;# Glitch Input Filter Status
+set PIO_SODR   0x30    ;# Set Output Data Register
+set PIO_CODR   0x34    ;# Clear Output Data Register
+set PIO_ODSR   0x38    ;# Output Data Status Register
+set PIO_PDSR   0x3c    ;# Pin Data Status Register
+set PIO_IER    0x40    ;# Interrupt Enable Register
+set PIO_IDR    0x44    ;# Interrupt Disable Register
+set PIO_IMR    0x48    ;# Interrupt Mask Register
+set PIO_ISR    0x4c    ;# Interrupt Status Register
+set PIO_MDER   0x50    ;# Multi-driver Enable Register
+set PIO_MDDR   0x54    ;# Multi-driver Disable Register
+set PIO_MDSR   0x58    ;# Multi-driver Status Register
+set PIO_PUDR   0x60    ;# Pull-up Disable Register
+set PIO_PUER   0x64    ;# Pull-up Enable Register
+set PIO_PUSR   0x68    ;# Pull-up Status Register
+set PIO_ASR    0x70    ;# Peripheral A Select Register
+set PIO_BSR    0x74    ;# Peripheral B Select Register
+set PIO_ABSR   0x78    ;# AB Status Register
+set PIO_OWER   0xa0    ;# Output Write Enable Register
+set PIO_OWDR   0xa4    ;# Output Write Disable Register
+set PIO_OWSR   0xa8    ;# Output Write Status Register
diff --git a/tcl/chip/atmel/at91/at91_pmc.cfg b/tcl/chip/atmel/at91/at91_pmc.cfg
new file mode 100644 (file)
index 0000000..88b1370
--- /dev/null
@@ -0,0 +1,113 @@
+set    AT91_PMC_SCER           [expr ($AT91_PMC + 0x00)]       ;# System Clock Enable Register
+set    AT91_PMC_SCDR           [expr ($AT91_PMC + 0x04)]       ;# System Clock Disable Register
+
+set    AT91_PMC_SCSR           [expr ($AT91_PMC + 0x08)]       ;# System Clock Status Register
+set            AT91_PMC_PCK            [expr (1 <<  0)]                ;# Processor Clock
+set            AT91RM9200_PMC_UDP      [expr (1 <<  1)]                ;# USB Devcice Port Clock [AT91RM9200 only]
+set            AT91RM9200_PMC_MCKUDP   [expr (1 <<  2)]                ;# USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only]
+set            AT91CAP9_PMC_DDR        [expr (1 <<  2)]                ;# DDR Clock [CAP9 revC & some SAM9 only]
+set            AT91RM9200_PMC_UHP      [expr (1 <<  4)]                ;# USB Host Port Clock [AT91RM9200 only]
+set            AT91SAM926x_PMC_UHP     [expr (1 <<  6)]                ;# USB Host Port Clock [AT91SAM926x only]
+set            AT91CAP9_PMC_UHP        [expr (1 <<  6)]                ;# USB Host Port Clock [AT91CAP9 only]
+set            AT91SAM926x_PMC_UDP     [expr (1 <<  7)]                ;# USB Devcice Port Clock [AT91SAM926x only]
+set            AT91_PMC_PCK0           [expr (1 <<  8)]                ;# Programmable Clock 0
+set            AT91_PMC_PCK1           [expr (1 <<  9)]                ;# Programmable Clock 1
+set            AT91_PMC_PCK2           [expr (1 << 10)]                ;# Programmable Clock 2
+set            AT91_PMC_PCK3           [expr (1 << 11)]                ;# Programmable Clock 3
+set            AT91_PMC_HCK0           [expr (1 << 16)]                ;# AHB Clock (USB host) [AT91SAM9261 only]
+set            AT91_PMC_HCK1           [expr (1 << 17)]                ;# AHB Clock (LCD) [AT91SAM9261 only]
+
+set    AT91_PMC_PCER           [expr ($AT91_PMC + 0x10)]       ;# Peripheral Clock Enable Register
+set    AT91_PMC_PCDR           [expr ($AT91_PMC + 0x14)]       ;# Peripheral Clock Disable Register
+set    AT91_PMC_PCSR           [expr ($AT91_PMC + 0x18)]       ;# Peripheral Clock Status Register
+
+set    AT91_CKGR_UCKR          [expr ($AT91_PMC + 0x1C)]       ;# UTMI Clock Register [some SAM9, CAP9]
+set            AT91_PMC_UPLLEN         [expr (1   << 16)]              ;# UTMI PLL Enable
+set            AT91_PMC_UPLLCOUNT      [expr (0xf << 20)]              ;# UTMI PLL Start-up Time
+set            AT91_PMC_BIASEN         [expr (1   << 24)]              ;# UTMI BIAS Enable
+set            AT91_PMC_BIASCOUNT      [expr (0xf << 28)]              ;# UTMI BIAS Start-up Time
+
+set    AT91_CKGR_MOR           [expr ($AT91_PMC + 0x20)]       ;# Main Oscillator Register [not on SAM9RL]
+set            AT91_PMC_MOSCEN         [expr (1    << 0)]              ;# Main Oscillator Enable
+set            AT91_PMC_OSCBYPASS      [expr (1    << 1)]              ;# Oscillator Bypass [SAM9x, CAP9]
+set            AT91_PMC_OSCOUNT        [expr (0xff << 8)]              ;# Main Oscillator Start-up Time
+
+set    AT91_CKGR_MCFR          [expr ($AT91_PMC + 0x24)]       ;# Main Clock Frequency Register
+set            AT91_PMC_MAINF          [expr (0xffff <<  0)]           ;# Main Clock Frequency
+set            AT91_PMC_MAINRDY        [expr (1        << 16)]         ;# Main Clock Ready
+
+set    AT91_CKGR_PLLAR         [expr ($AT91_PMC + 0x28)]       ;# PLL A Register
+set    AT91_CKGR_PLLBR         [expr ($AT91_PMC + 0x2c)]       ;# PLL B Register
+set            AT91_PMC_DIV            [expr (0xff  <<  0)]            ;# Divider
+set            AT91_PMC_PLLCOUNT       [expr (0x3f  <<  8)]            ;# PLL Counter
+set            AT91_PMC_OUT            [expr (3     << 14)]            ;# PLL Clock Frequency Range
+set            AT91_PMC_MUL            [expr (0x7ff << 16)]            ;# PLL Multiplier
+set            AT91_PMC_USBDIV         [expr (3     << 28)]            ;# USB Divisor (PLLB only)
+set                    AT91_PMC_USBDIV_1               [expr (0 << 28)]
+set                    AT91_PMC_USBDIV_2               [expr (1 << 28)]
+set                    AT91_PMC_USBDIV_4               [expr (2 << 28)]
+set            AT91_PMC_USB96M         [expr (1     << 28)]            ;# Divider by 2 Enable (PLLB only)
+set            AT91_PMC_PLLA_WR_ERRATA [expr (1     << 29)]            ;# Bit 29 must always be set to 1 when programming the CKGR_PLLAR register
+
+set    AT91_PMC_MCKR           [expr ($AT91_PMC + 0x30)]       ;# Master Clock Register
+set            AT91_PMC_CSS            [expr (3 <<  0)]                ;# Master Clock Selection
+set                    AT91_PMC_CSS_SLOW               [expr (0 << 0)]
+set                    AT91_PMC_CSS_MAIN               [expr (1 << 0)]
+set                    AT91_PMC_CSS_PLLA               [expr (2 << 0)]
+set                    AT91_PMC_CSS_PLLB               [expr (3 << 0)]
+set                    AT91_PMC_CSS_UPLL               [expr (3 << 0)] ;# [some SAM9 only]
+set            AT91_PMC_PRES           [expr (7 <<  2)]                ;# Master Clock Prescaler
+set                    AT91_PMC_PRES_1                 [expr (0 << 2)]
+set                    AT91_PMC_PRES_2                 [expr (1 << 2)]
+set                    AT91_PMC_PRES_4                 [expr (2 << 2)]
+set                    AT91_PMC_PRES_8                 [expr (3 << 2)]
+set                    AT91_PMC_PRES_16                [expr (4 << 2)]
+set                    AT91_PMC_PRES_32                [expr (5 << 2)]
+set                    AT91_PMC_PRES_64                [expr (6 << 2)]
+set            AT91_PMC_MDIV           [expr (3 <<  8)]                ;# Master Clock Division
+set                    AT91RM9200_PMC_MDIV_1           [expr (0 << 8)] ;# [AT91RM9200 only]
+set                    AT91RM9200_PMC_MDIV_2           [expr (1 << 8)]
+set                    AT91RM9200_PMC_MDIV_3           [expr (2 << 8)]
+set                    AT91RM9200_PMC_MDIV_4           [expr (3 << 8)]
+set                    AT91SAM9_PMC_MDIV_1             [expr (0 << 8)] ;# [SAM9,CAP9 only]
+set                    AT91SAM9_PMC_MDIV_2             [expr (1 << 8)]
+set                    AT91SAM9_PMC_MDIV_4             [expr (2 << 8)]
+set                    AT91SAM9_PMC_MDIV_6             [expr (3 << 8)] ;# [some SAM9 only]
+set                    AT91SAM9_PMC_MDIV_3             [expr (3 << 8)] ;# [some SAM9 only]
+set            AT91_PMC_PDIV           [expr (1 << 12)]                ;# Processor Clock Division [some SAM9 only]
+set                    AT91_PMC_PDIV_1                 [expr (0 << 12)]
+set                    AT91_PMC_PDIV_2                 [expr (1 << 12)]
+set            AT91_PMC_PLLADIV2       [expr (1 << 12)]                ;# PLLA divisor by 2 [some SAM9 only]
+set                    AT91_PMC_PLLADIV2_OFF           [expr (0 << 12)]
+set                    AT91_PMC_PLLADIV2_ON            [expr (1 << 12)]
+
+set    AT91_PMC_USB            [expr ($AT91_PMC + 0x38)]       ;# USB Clock Register [some SAM9 only]
+set            AT91_PMC_USBS           [expr (0x1 <<  0)]              ;# USB OHCI Input clock selection
+set                    AT91_PMC_USBS_PLLA              [expr (0 << 0)]
+set                    AT91_PMC_USBS_UPLL              [expr (1 << 0)]
+set            AT91_PMC_OHCIUSBDIV     [expr (0xF <<  8)]              ;# Divider for USB OHCI Clock
+
+;# set AT91_PMC_PCKR(n)        [expr ($AT91_PMC + 0x40 + ((n) * 4))]   ;# Programmable Clock 0-N Registers
+set            AT91_PMC_CSSMCK         [expr (0x1 <<  8)]              ;# CSS or Master Clock Selection
+set                    AT91_PMC_CSSMCK_CSS             [expr (0 << 8)]
+set                    AT91_PMC_CSSMCK_MCK             [expr (1 << 8)]
+
+set    AT91_PMC_IER            [expr ($AT91_PMC + 0x60)]       ;# Interrupt Enable Register
+set    AT91_PMC_IDR            [expr ($AT91_PMC + 0x64)]       ;# Interrupt Disable Register
+set    AT91_PMC_SR             [expr ($AT91_PMC + 0x68)]       ;# Status Register
+set            AT91_PMC_MOSCS          [expr (1 <<  0)]                ;# MOSCS Flag
+set            AT91_PMC_LOCKA          [expr (1 <<  1)]                ;# PLLA Lock
+set            AT91_PMC_LOCKB          [expr (1 <<  2)]                ;# PLLB Lock
+set            AT91_PMC_MCKRDY         [expr (1 <<  3)]                ;# Master Clock
+set            AT91_PMC_LOCKU          [expr (1 <<  6)]                ;# UPLL Lock [some SAM9, AT91CAP9 only]
+set            AT91_PMC_OSCSEL         [expr (1 <<  7)]                ;# Slow Clock Oscillator [AT91CAP9 revC only]
+set            AT91_PMC_PCK0RDY        [expr (1 <<  8)]                ;# Programmable Clock 0
+set            AT91_PMC_PCK1RDY        [expr (1 <<  9)]                ;# Programmable Clock 1
+set            AT91_PMC_PCK2RDY        [expr (1 << 10)]                ;# Programmable Clock 2
+set            AT91_PMC_PCK3RDY        [expr (1 << 11)]                ;# Programmable Clock 3
+set    AT91_PMC_IMR            [expr ($AT91_PMC + 0x6c)]       ;# Interrupt Mask Register
+
+set AT91_PMC_PROT              [expr ($AT91_PMC + 0xe4)]       ;# Protect Register [AT91CAP9 revC only]
+set            AT91_PMC_PROTKEY        0x504d4301      ;# Activation Code
+
+set AT91_PMC_VER               [expr ($AT91_PMC + 0xfc)]       ;# PMC Module Version [AT91CAP9 only]
diff --git a/tcl/chip/atmel/at91/at91_rstc.cfg b/tcl/chip/atmel/at91/at91_rstc.cfg
new file mode 100644 (file)
index 0000000..ed60822
--- /dev/null
@@ -0,0 +1,21 @@
+set AT91_RSTC_CR               [expr ($AT91_RSTC + 0x00)]      ;# Reset Controller Control Register
+set            AT91_RSTC_PROCRST       [expr (1 << 0)]         ;# Processor Reset
+set            AT91_RSTC_PERRST        [expr (1 << 2)]         ;# Peripheral Reset
+set            AT91_RSTC_EXTRST        [expr (1 << 3)]         ;# External Reset
+set            AT91_RSTC_KEY           [expr (0xa5 << 24)]             ;# KEY Password
+
+set AT91_RSTC_SR               [expr ($AT91_RSTC + 0x04)]      ;# Reset Controller Status Register
+set            AT91_RSTC_URSTS         [expr (1 << 0)]         ;# User Reset Status
+set            AT91_RSTC_RSTTYP        [expr (7 << 8)]         ;# Reset Type
+set                    AT91_RSTC_RSTTYP_GENERAL        [expr (0 << 8)]
+set                    AT91_RSTC_RSTTYP_WAKEUP         [expr (1 << 8)]
+set                    AT91_RSTC_RSTTYP_WATCHDOG       [expr (2 << 8)]
+set                    AT91_RSTC_RSTTYP_SOFTWARE       [expr (3 << 8)]
+set                    AT91_RSTC_RSTTYP_USER   [expr (4 << 8)]
+set            AT91_RSTC_NRSTL         [expr (1 << 16)]                ;# NRST Pin Level
+set            AT91_RSTC_SRCMP         [expr (1 << 17)]                ;# Software Reset Command in Progress
+
+set AT91_RSTC_MR               [expr ($AT91_RSTC + 0x08)]      ;# Reset Controller Mode Register
+set            AT91_RSTC_URSTEN        [expr (1 << 0)]         ;# User Reset Enable
+set            AT91_RSTC_URSTIEN       [expr (1 << 4)]         ;# User Reset Interrupt Enable
+set            AT91_RSTC_ERSTL         [expr (0xf << 8)]               ;# External Reset Length
diff --git a/tcl/chip/atmel/at91/at91_wdt.cfg b/tcl/chip/atmel/at91/at91_wdt.cfg
new file mode 100644 (file)
index 0000000..a263cc7
--- /dev/null
@@ -0,0 +1,17 @@
+set AT91_WDT_CR                [expr ($AT91_WDT + 0x00)]       ;# Watchdog Control Register
+set            AT91_WDT_WDRSTT         [expr (1    << 0)]      ;# Restart
+set            AT91_WDT_KEY            [expr (0xa5 << 24)]     ;# KEY Password
+
+set AT91_WDT_MR                [expr ($AT91_WDT + 0x04)]       ;# Watchdog Mode Register
+set            AT91_WDT_WDV            [expr (0xfff << 0)]     ;# Counter Value
+set            AT91_WDT_WDFIEN         [expr (1     << 12)]    ;# Fault Interrupt Enable
+set            AT91_WDT_WDRSTEN        [expr (1     << 13)]    ;# Reset Processor
+set            AT91_WDT_WDRPROC        [expr (1     << 14)]    ;# Timer Restart
+set            AT91_WDT_WDDIS          [expr (1     << 15)]    ;# Watchdog Disable
+set            AT91_WDT_WDD            [expr (0xfff << 16)]    ;# Delta Value
+set            AT91_WDT_WDDBGHLT       [expr (1     << 28)]    ;# Debug Halt
+set            AT91_WDT_WDIDLEHLT      [expr (1     << 29)]    ;# Idle Halt
+
+set AT91_WDT_SR                [expr ($AT91_WDT + 0x08)]       ;# Watchdog Status Register
+set            AT91_WDT_WDUNF          [expr (1 << 0)]         ;# Watchdog Underflow
+set            AT91_WDT_WDERR          [expr (1 << 1)]         ;# Watchdog Error
diff --git a/tcl/chip/atmel/at91/at91sam9_init.cfg b/tcl/chip/atmel/at91/at91sam9_init.cfg
new file mode 100644 (file)
index 0000000..47d22e0
--- /dev/null
@@ -0,0 +1,86 @@
+uplevel #0 [list source [find chip/atmel/at91/at91sam9_sdramc.cfg]]
+uplevel #0 [list source [find chip/atmel/at91/at91_pmc.cfg]]
+uplevel #0 [list source [find chip/atmel/at91/at91_pio.cfg]]
+uplevel #0 [list source [find chip/atmel/at91/at91_rstc.cfg]]
+uplevel #0 [list source [find chip/atmel/at91/at91_wdt.cfg]]
+
+proc at91sam9_reset_start { } {
+
+       arm7_9 fast_memory_access disable
+
+       jtag_rclk 8
+       halt
+       wait_halt 10000
+       set rstc_mr_val [expr $::AT91_RSTC_KEY]
+       set rstc_mr_val [expr ($rstc_mr_val | (5 << 8))]
+       set rstc_mr_val [expr ($rstc_mr_val | $::AT91_RSTC_URSTEN)]
+       mww $::AT91_RSTC_MR $rstc_mr_val        ;# RSTC_MR : enable user reset.
+}
+
+proc at91sam9_reset_init { config } {
+
+       mww $::AT91_WDT_MR $config(wdt_mr_val)  ;# disable watchdog
+
+       set ckgr_mor [expr ($::AT91_PMC_MOSCEN | (255 << 8))]
+
+       mww $::AT91_CKGR_MOR $ckgr_mor  ;# CKGR_MOR - enable main osc.
+       while { [expr [mrw $::AT91_PMC_SR] & $::AT91_PMC_MOSCS] != $::AT91_PMC_MOSCS } { sleep 1 }
+
+       set pllar_val   [expr $::AT91_PMC_PLLA_WR_ERRATA] ;# Bit 29 must be 1 when prog
+       set pllar_val   [expr ($pllar_val | $::AT91_PMC_OUT)]
+       set pllar_val   [expr ($pllar_val | $::AT91_PMC_PLLCOUNT)]
+       set pllar_val   [expr ($pllar_val | ($config(master_pll_mul) - 1) << 16)]
+       set pllar_val   [expr ($pllar_val | $config(master_pll_div))]
+
+       mww $::AT91_CKGR_PLLAR $pllar_val        ;# CKGR_PLLA - (18.432MHz/13)*141 = 199.9 MHz
+       while { [expr [mrw $::AT91_PMC_SR] & $::AT91_PMC_LOCKA] != $::AT91_PMC_LOCKA } { sleep 1 }
+
+       ;# PCK/2 = MCK Master Clock from PLLA
+       set mckr_val    [expr $::AT91_PMC_CSS_PLLA]
+       set mckr_val    [expr ($mckr_val | $::AT91_PMC_PRES_1)]
+       set mckr_val    [expr ($mckr_val | $::AT91SAM9_PMC_MDIV_2)]
+       set mckr_val    [expr ($mckr_val | $::AT91_PMC_PDIV_1)]
+
+       mww $::AT91_PMC_MCKR $mckr_val  ;# PMC_MCKR (MCLK: 0x102 - (CLK/2)MHZ, 0x202 - (CLK/3)MHz)
+       while { [expr [mrw $::AT91_PMC_SR] & $::AT91_PMC_MCKRDY] != $::AT91_PMC_MCKRDY } { sleep 1 }
+
+       ## switch JTAG clock to highseepd clock
+       jtag_rclk 0
+
+       arm7_9 dcc_downloads enable     ;# Enable faster DCC downloads
+       arm7_9 fast_memory_access enable
+
+       set rstc_mr_val [expr ($::AT91_RSTC_KEY)]
+       set rstc_mr_val [expr ($rstc_mr_val | $::AT91_RSTC_URSTEN)]
+       mww $::AT91_RSTC_MR $rstc_mr_val        ;# user reset enable
+
+       set pdr_addr [expr ($::AT91_PIOC + $::PIO_PDR)]
+       mww $pdr_addr 0xffff0000                                ;# define PDC[31:16] as DATA[31:16]
+       set pudr_addr [expr ($::AT91_PIOC + $::PIO_PUDR)]
+       mww $pudr_addr 0xffff0000                               ;# no pull-up for D[31:16]
+
+       mww $config(matrix_ebicsa_addr) $config(matrix_ebicsa_val)
+       mww $::AT91_SDRAMC_MR   $::AT91_SDRAMC_MODE_NORMAL      ;# SDRAMC_MR Mode register
+       mww $::AT91_SDRAMC_TR   $config(sdram_tr_val)           ;# SDRAMC_TR - Refresh Timer register
+       mww $::AT91_SDRAMC_CR   $config(sdram_cr_val)           ;# SDRAMC_CR - Configuration register
+       mww $::AT91_SDRAMC_MDR  $::AT91_SDRAMC_MD_SDRAM         ;# Memory Device Register -> SDRAM
+       mww $::AT91_SDRAMC_MR   $::AT91_SDRAMC_MODE_PRECHARGE   ;# SDRAMC_MR
+       mww $config(sdram_base) 0                               ;# SDRAM_BASE
+       mww $::AT91_SDRAMC_MR   $::AT91_SDRAMC_MODE_REFRESH     ;# SDRC_MR
+       mww $config(sdram_base) 0                               ;# SDRAM_BASE
+       mww $config(sdram_base) 0                               ;# SDRAM_BASE
+       mww $config(sdram_base) 0                               ;# SDRAM_BASE
+       mww $config(sdram_base) 0                               ;# SDRAM_BASE
+       mww $config(sdram_base) 0                               ;# SDRAM_BASE
+       mww $config(sdram_base) 0                               ;# SDRAM_BASE
+       mww $config(sdram_base) 0                               ;# SDRAM_BASE
+       mww $config(sdram_base) 0                               ;# SDRAM_BASE
+       mww $::AT91_SDRAMC_MR   $::AT91_SDRAMC_MODE_LMR         ;# SDRC_MR
+       mww $config(sdram_base) 0                               ;# SDRAM_BASE
+       mww $::AT91_SDRAMC_MR   $::AT91_SDRAMC_MODE_NORMAL      ;# SDRC_MR
+       mww $config(sdram_base) 0                               ;# SDRAM_BASE
+       mww $::AT91_SDRAMC_TR   1200                            ;# SDRAM_TR
+       mww $config(sdram_base) 0                               ;# SDRAM_BASE
+
+       mww $::AT91_MATRIX 0xf          ;# MATRIX_MCFG - REMAP all masters
+}
diff --git a/tcl/chip/atmel/at91/at91sam9_sdramc.cfg b/tcl/chip/atmel/at91/at91sam9_sdramc.cfg
new file mode 100644 (file)
index 0000000..dbca497
--- /dev/null
@@ -0,0 +1,66 @@
+
+# SDRAM Controller (SDRAMC) registers
+set AT91_SDRAMC_MR             [expr ($AT91_SDRAMC + 0x00)]    ;# SDRAM Controller Mode Register
+set            AT91_SDRAMC_MODE        [expr (0xf << 0)]       ;# Command Mode
+set                    AT91_SDRAMC_MODE_NORMAL         0
+set                    AT91_SDRAMC_MODE_NOP            1
+set                    AT91_SDRAMC_MODE_PRECHARGE      2
+set                    AT91_SDRAMC_MODE_LMR            3
+set                    AT91_SDRAMC_MODE_REFRESH        4
+set                    AT91_SDRAMC_MODE_EXT_LMR        5
+set                    AT91_SDRAMC_MODE_DEEP           6
+
+set AT91_SDRAMC_TR             [expr ($AT91_SDRAMC + 0x04)]    ;# SDRAM Controller Refresh Timer Register
+set            AT91_SDRAMC_COUNT       [expr (0xfff << 0)]             ;# Refresh Timer Counter
+
+set AT91_SDRAMC_CR             [expr ($AT91_SDRAMC + 0x08)]    ;# SDRAM Controller Configuration Register
+set            AT91_SDRAMC_NC          [expr (3 << 0)]         ;# Number of Column Bits
+set                    AT91_SDRAMC_NC_8        [expr (0 << 0)]
+set                    AT91_SDRAMC_NC_9        [expr (1 << 0)]
+set                    AT91_SDRAMC_NC_10       [expr (2 << 0)]
+set                    AT91_SDRAMC_NC_11       [expr (3 << 0)]
+set            AT91_SDRAMC_NR          [expr (3 << 2)]         ;# Number of Row Bits
+set                    AT91_SDRAMC_NR_11       [expr (0 << 2)]
+set                    AT91_SDRAMC_NR_12       [expr (1 << 2)]
+set                    AT91_SDRAMC_NR_13       [expr (2 << 2)]
+set            AT91_SDRAMC_NB          [expr (1 << 4)]         ;# Number of Banks
+set                    AT91_SDRAMC_NB_2        [expr (0 << 4)]
+set                    AT91_SDRAMC_NB_4        [expr (1 << 4)]
+set            AT91_SDRAMC_CAS         [expr (3 << 5)]         ;# CAS Latency
+set                    AT91_SDRAMC_CAS_1       [expr (1 << 5)]
+set                    AT91_SDRAMC_CAS_2       [expr (2 << 5)]
+set                    AT91_SDRAMC_CAS_3       [expr (3 << 5)]
+set            AT91_SDRAMC_DBW         [expr (1 << 7)]         ;# Data Bus Width
+set                    AT91_SDRAMC_DBW_32      [expr (0 << 7)]
+set                    AT91_SDRAMC_DBW_16      [expr (1 << 7)]
+set            AT91_SDRAMC_TWR         [expr (0xf <<  8)]              ;# Write Recovery Delay
+set            AT91_SDRAMC_TRC         [expr (0xf << 12)]              ;# Row Cycle Delay
+set            AT91_SDRAMC_TRP         [expr (0xf << 16)]              ;# Row Precharge Delay
+set            AT91_SDRAMC_TRCD        [expr (0xf << 20)]              ;# Row to Column Delay
+set            AT91_SDRAMC_TRAS        [expr (0xf << 24)]              ;# Active to Precharge Delay
+set            AT91_SDRAMC_TXSR        [expr (0xf << 28)]              ;# Exit Self Refresh to Active Delay
+
+set AT91_SDRAMC_LPR            [expr ($AT91_SDRAMC + 0x10)]    ;# SDRAM Controller Low Power Register
+set            AT91_SDRAMC_LPCB                [expr (3 << 0)] ;# Low-power Configurations
+set                    AT91_SDRAMC_LPCB_DISABLE                0
+set                    AT91_SDRAMC_LPCB_SELF_REFRESH           1
+set                    AT91_SDRAMC_LPCB_POWER_DOWN             2
+set                    AT91_SDRAMC_LPCB_DEEP_POWER_DOWN        3
+set            AT91_SDRAMC_PASR                [expr (7 << 4)] ;# Partial Array Self Refresh
+set            AT91_SDRAMC_TCSR                [expr (3 << 8)] ;# Temperature Compensated Self Refresh
+set            AT91_SDRAMC_DS                  [expr (3 << 10)]        ;# Drive Strength
+set            AT91_SDRAMC_TIMEOUT             [expr (3 << 12)]        ;# Time to define when Low Power Mode is enabled
+set                    AT91_SDRAMC_TIMEOUT_0_CLK_CYCLES        [expr (0 << 12)]
+set                    AT91_SDRAMC_TIMEOUT_64_CLK_CYCLES       [expr (1 << 12)]
+set                    AT91_SDRAMC_TIMEOUT_128_CLK_CYCLES      [expr (2 << 12)]
+
+set AT91_SDRAMC_IER            [expr ($AT91_SDRAMC + 0x14)]    ;# SDRAM Controller Interrupt Enable Register
+set AT91_SDRAMC_IDR            [expr ($AT91_SDRAMC + 0x18)]    ;# SDRAM Controller Interrupt Disable Register
+set AT91_SDRAMC_IMR            [expr ($AT91_SDRAMC + 0x1C)]    ;# SDRAM Controller Interrupt Mask Register
+set AT91_SDRAMC_ISR            [expr ($AT91_SDRAMC + 0x20)]    ;# SDRAM Controller Interrupt Status Register
+set            AT91_SDRAMC_RES         [expr (1 << 0)]         ;# Refresh Error Status
+
+set AT91_SDRAMC_MDR            [expr ($AT91_SDRAMC + 0x24)]    ;# SDRAM Memory Device Register
+set            AT91_SDRAMC_MD          [expr (3 << 0)]         ;# Memory Device Type
+set                    AT91_SDRAMC_MD_SDRAM            0
+set                    AT91_SDRAMC_MD_LOW_POWER_SDRAM  1
diff --git a/tcl/chip/atmel/at91/at91sam9_smc.cfg b/tcl/chip/atmel/at91/at91sam9_smc.cfg
new file mode 100644 (file)
index 0000000..7dc7638
--- /dev/null
@@ -0,0 +1,20 @@
+set            AT91_SMC_READMODE       [expr (1 <<  0)]                ;# Read Mode
+set            AT91_SMC_WRITEMODE      [expr (1 <<  1)]                ;# Write Mode
+set            AT91_SMC_EXNWMODE       [expr (3 <<  4)]                ;# NWAIT Mode
+set                    AT91_SMC_EXNWMODE_DISABLE       [expr (0 << 4)]
+set                    AT91_SMC_EXNWMODE_FROZEN        [expr (2 << 4)]
+set                    AT91_SMC_EXNWMODE_READY         [expr (3 << 4)]
+set            AT91_SMC_BAT            [expr (1 <<  8)]                ;# Byte Access Type
+set                    AT91_SMC_BAT_SELECT             [expr (0 << 8)]
+set                    AT91_SMC_BAT_WRITE              [expr (1 << 8)]
+set            AT91_SMC_DBW            [expr (3 << 12)]                ;# Data Bus Width */
+set                    AT91_SMC_DBW_8                  [expr (0 << 12)]
+set                    AT91_SMC_DBW_16                 [expr (1 << 12)]
+set                    AT91_SMC_DBW_32                 [expr (2 << 12)]
+set            AT91_SMC_TDFMODE        [expr (1 << 20)]                ;# TDF Optimization - Enabled
+set            AT91_SMC_PMEN           [expr (1 << 24)]                ;# Page Mode Enabled
+set            AT91_SMC_PS             [expr (3 << 28)]                ;# Page Size
+set                    AT91_SMC_PS_4                   [expr (0 << 28)]
+set                    AT91_SMC_PS_8                   [expr (1 << 28)]
+set                    AT91_SMC_PS_16                  [expr (2 << 28)]
+set                    AT91_SMC_PS_32                  [expr (3 << 28)]
diff --git a/tcl/chip/atmel/at91/hardware.cfg b/tcl/chip/atmel/at91/hardware.cfg
new file mode 100644 (file)
index 0000000..a25eab9
--- /dev/null
@@ -0,0 +1,9 @@
+# External Memory Map
+set AT91_CHIPSELECT_0  0x10000000
+set AT91_CHIPSELECT_1  0x20000000
+set AT91_CHIPSELECT_2  0x30000000
+set AT91_CHIPSELECT_3  0x40000000
+set AT91_CHIPSELECT_4  0x50000000
+set AT91_CHIPSELECT_5  0x60000000
+set AT91_CHIPSELECT_6  0x70000000
+set AT91_CHIPSELECT_7  0x80000000
diff --git a/tcl/chip/atmel/at91/sam9_smc.cfg b/tcl/chip/atmel/at91/sam9_smc.cfg
new file mode 100644 (file)
index 0000000..db943cb
--- /dev/null
@@ -0,0 +1,55 @@
+# Setup register
+#
+# ncs_read_setup
+# nrd_setup
+# ncs_write_setup
+# set nwe_setup
+#
+#
+# Pulse register
+#
+# ncs_read_pulse
+# nrd_pulse
+# ncs_write_pulse
+# nwe_pulse
+#
+#
+# Cycle register
+#
+# read_cycle 0
+# write_cycle 0
+#
+#
+# Mode register
+#
+# mode
+# tdf_cycles
+proc sam9_smc_config { cs smc_config } {
+       ;# Setup Register for CS n
+       set AT91_SMC_SETUP [expr ($::AT91_SMC + 0x00 + ((cs)*0x10))]
+       set val [expr ($smc_config(nwe_setup) << 0)]
+       set val [expr ($val | $smc_config(ncs_write_setup) << 8]
+       set val [expr ($val | $smc_config(nrd_setup)) << 16]
+       set val [expr ($val | $smc_config(ncs_read_setup) << 24]
+       mww $AT91_SMC_SETUP $val
+
+       ;# Pulse Register for CS n
+       set AT91_SMC_PULSE [expr ($::AT91_SMC + 0x04 + ((cs)*0x10))]
+       set val [expr ($smc_config(nwe_pulse) << 0)]
+       set val [expr ($val | $smc_config(ncs_write_pulse) << 8]
+       set val [expr ($val | $smc_config(nrd_pulse) << 16]
+       set val [expr ($val | $smc_config(ncs_read_pulse) << 24]
+       mww $AT91_SMC_PULSE $val
+
+       ;# Cycle Register for CS n
+       set AT91_SMC_CYCLE [expr ($::AT91_SMC + 0x08 + ((cs)*0x10))]
+       set val [expr ($smc_config(write_cycle) << 0)]
+       set val [expr ($val | $smc_config(read_cycle) << 16]
+       mww $AT91_SMC_CYCLE $val
+
+       ;# Mode Register for CS n
+       set AT91_SMC_MODE [expr ($::AT91_SMC + 0x0c + ((cs)*0x10))]
+       set val [expr ($smc_config(mode) << 0)]
+       set val [expr ($val | $smc_config(tdf_cycles) << 16]
+       mww $AT91_SMC_MODE $val
+}