--- /dev/null
+# Hey Emacs, this is a -*- makefile -*-
+
+# Goals available on make command line:
+#
+# [all] Default goal: build the project.
+# clean Clean up the project.
+# rebuild Rebuild the project.
+# ccversion Display CC version information.
+# cppfiles file.i Generate preprocessed files from C source files.
+# asfiles file.x Generate preprocessed assembler files from C and assembler source files.
+# objfiles file.o Generate object files from C and assembler source files.
+# a file.a Archive: create A output file from object files.
+# elf file.elf Link: create ELF output file from object files.
+# lss file.lss Create extended listing from target output file.
+# sym file.sym Create symbol table from target output file.
+# bin file.bin Create binary image from ELF output file.
+# sizes Display target size information.
+# cpuinfo Get CPU information.
+# halt Stop CPU execution.
+# program Program MCU memory from ELF output file.
+# reset Reset CPU.
+# debug Open a debug connection with the MCU.
+# run Start CPU execution.
+# readregs Read CPU registers.
+# doc Build the documentation.
+# cleandoc Clean up the documentation.
+# rebuilddoc Rebuild the documentation.
+# verbose Display main executed commands.
+
+# Copyright (c) 2007, Atmel Corporation All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#
+# 1. Redistributions of source code must retain the above copyright notice, this
+# list of conditions and the following disclaimer.
+#
+# 2. Redistributions in binary form must reproduce the above copyright notice,
+# this list of conditions and the following disclaimer in the documentation and/
+# or other materials provided with the distribution.
+#
+# 3. The name of ATMEL may not be used to endorse or promote products derived
+# from this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
+# WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+# MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
+# SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
+# INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+# OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+# EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+
+# ** ** ** *** ** ** ** ** ** ** ** ** ** ** **
+# ENVIRONMENT SETTINGS
+# ** ** ** *** ** ** ** ** ** ** ** ** ** ** **
+
+FirstWord = $(if $(1),$(word 1,$(1)))
+LastWord = $(if $(1),$(word $(words $(1)),$(1)))
+
+MAKE = make
+MAKECFG = config.mk
+TGTTYPE = $(suffix $(TARGET))
+TGTFILE = $(PART)-$(TARGET)
+
+RM = rm -Rf
+
+AR = avr32-ar
+ARFLAGS = rcs
+
+CPP = $(CC) -E
+CPPFLAGS = -march=$(ARCH) -mpart=$(PART) $(WARNINGS) $(DEFS) \
+ $(PLATFORM_INC_PATH:%=-I%) $(INC_PATH:%=-I%) $(CPP_EXTRA_FLAGS)
+DPNDFILES = $(CSRCS:.c=.d) $(ASSRCS:.S=.d)
+CPPFILES = $(CSRCS:.c=.i)
+
+CC = avr32-gcc
+CFLAGS = $(DEBUG) $(OPTIMIZATION) $(C_EXTRA_FLAGS)
+ASFILES = $(CSRCS:.c=.x) $(ASSRCS:.S=.x)
+
+AS = avr32-as
+ASFLAGS = $(DEBUG) $(AS_EXTRA_FLAGS)
+OBJFILES = $(CSRCS:.c=.o) $(ASSRCS:.S=.o)
+
+LD = avr32-ld
+LDFLAGS = -march=$(ARCH) -mpart=$(PART) \
+ $(LIB_PATH:%=-L%) $(LINKER_SCRIPT:%=-T%) $(LD_EXTRA_FLAGS)
+LOADLIBES =
+LDLIBS = $(LIBS:%=-l%)
+
+OBJDUMP = avr32-objdump
+LSS = $(TGTFILE:$(TGTTYPE)=.lss)
+
+NM = avr32-nm
+SYM = $(TGTFILE:$(TGTTYPE)=.sym)
+
+OBJCOPY = avr32-objcopy
+BIN = $(TGTFILE:$(TGTTYPE)=.bin)
+
+SIZE = avr32-size
+
+SUDO = $(shell if [ -x /usr/bin/sudo ]; then echo sudo; fi)
+
+SLEEP = sleep
+SLEEPUSB = 9
+
+PROGRAM = avr32program
+
+DBGPROXY = avr32gdbproxy
+
+DOCGEN = doxygen
+
+
+# ** ** ** *** ** ** ** ** ** ** ** ** ** ** **
+# MESSAGES
+# ** ** ** *** ** ** ** ** ** ** ** ** ** ** **
+
+ERR_TARGET_TYPE = Target type not supported: `$(TGTTYPE)'
+MSG_CLEANING = Cleaning project.
+MSG_PREPROCESSING = Preprocessing \`$<\' to \`$@\'.
+MSG_COMPILING = Compiling \`$<\' to \`$@\'.
+MSG_ASSEMBLING = Assembling \`$<\' to \`$@\'.
+MSG_ARCHIVING = Archiving to \`$@\'.
+MSG_LINKING = Linking to \`$@\'.
+MSG_EXTENDED_LISTING = Creating extended listing to \`$@\'.
+MSG_SYMBOL_TABLE = Creating symbol table to \`$@\'.
+MSG_BINARY_IMAGE = Creating binary image to \`$@\'.
+MSG_GETTING_CPU_INFO = Getting CPU information.
+MSG_HALTING = Stopping CPU execution.
+MSG_PROGRAMMING = Programming MCU memory from \`$<\'.
+MSG_RESETTING = Resetting CPU.
+MSG_DEBUGGING = Opening debug connection with MCU.
+MSG_RUNNING = Starting CPU execution.
+MSG_READING_CPU_REGS = Reading CPU registers.
+MSG_CLEANING_DOC = Cleaning documentation.
+MSG_GENERATING_DOC = Generating documentation to \`$(DOC_PATH)\'.
+
+
+# ** ** ** *** ** ** ** ** ** ** ** ** ** ** **
+# MAKE RULES
+# ** ** ** *** ** ** ** ** ** ** ** ** ** ** **
+
+# Include the make configuration file.
+include $(MAKECFG)
+
+# ** ** TOP-LEVEL RULES ** **
+
+# Default goal: build the project.
+ifeq ($(TGTTYPE),.a)
+.PHONY: all
+all: ccversion a lss sym
+else
+ifeq ($(TGTTYPE),.elf)
+.PHONY: all
+all: ccversion elf lss sym bin sizes
+else
+$(error $(ERR_TARGET_TYPE))
+endif
+endif
+
+# Clean up the project.
+.PHONY: clean
+clean:
+ @echo $(MSG_CLEANING)
+ -$(VERBOSE_CMD)$(RM) $(BIN)
+ -$(VERBOSE_CMD)$(RM) $(SYM)
+ -$(VERBOSE_CMD)$(RM) $(LSS)
+ -$(VERBOSE_CMD)$(RM) $(TGTFILE)
+ -$(VERBOSE_CMD)$(RM) $(OBJFILES)
+ -$(VERBOSE_CMD)$(RM) $(ASFILES)
+ -$(VERBOSE_CMD)$(RM) $(CPPFILES)
+ -$(VERBOSE_CMD)$(RM) $(DPNDFILES)
+ $(VERBOSE_NL)
+
+# Rebuild the project.
+.PHONY: rebuild
+rebuild: clean all
+
+# Display CC version information.
+.PHONY: ccversion
+ccversion:
+ @echo
+ @echo
+ @$(CC) --version
+
+# Generate preprocessed files from C source files.
+.PHONY: cppfiles
+cppfiles: $(CPPFILES)
+
+# Generate preprocessed assembler files from C and assembler source files.
+.PHONY: asfiles
+asfiles: $(ASFILES)
+
+# Generate object files from C and assembler source files.
+.PHONY: objfiles
+objfiles: $(OBJFILES)
+
+ifeq ($(TGTTYPE),.a)
+# Archive: create A output file from object files.
+.PHONY: a
+a: $(TGTFILE)
+else
+ifeq ($(TGTTYPE),.elf)
+# Link: create ELF output file from object files.
+.PHONY: elf
+elf: $(TGTFILE)
+endif
+endif
+
+# Create extended listing from target output file.
+.PHONY: lss
+lss: $(LSS)
+
+# Create symbol table from target output file.
+.PHONY: sym
+sym: $(SYM)
+
+ifeq ($(TGTTYPE),.elf)
+# Create binary image from ELF output file.
+.PHONY: bin
+bin: $(BIN)
+endif
+
+# Display target size information.
+.PHONY: sizes
+sizes: $(TGTFILE)
+ @echo
+ @echo
+ @$(SIZE) -Ax $<
+
+ifeq ($(TGTTYPE),.elf)
+
+# Get CPU information.
+.PHONY: cpuinfo
+cpuinfo:
+ @echo
+ @echo $(MSG_GETTING_CPU_INFO)
+ $(VERBOSE_CMD)$(SUDO) $(PROGRAM) -cUSB cpuinfo
+ifneq ($(call LastWord,$(filter cpuinfo program reset debug run readregs,$(MAKECMDGOALS))),cpuinfo)
+ @$(SLEEP) $(SLEEPUSB)
+else
+ @echo
+endif
+
+# Stop CPU execution.
+.PHONY: halt
+halt:
+ifeq ($(filter cpuinfo program reset run readregs,$(MAKECMDGOALS)),)
+ @echo
+ @echo $(MSG_HALTING)
+ $(VERBOSE_CMD)$(SUDO) $(PROGRAM) -cUSB halt
+ifneq ($(call LastWord,$(filter halt debug,$(MAKECMDGOALS))),halt)
+ @$(SLEEP) $(SLEEPUSB)
+else
+ @echo
+endif
+else
+ @echo > /dev/null
+endif
+
+# Program MCU memory from ELF output file.
+.PHONY: program
+program: $(TGTFILE)
+ @echo
+ @echo $(MSG_PROGRAMMING)
+ $(VERBOSE_CMD)$(SUDO) $(PROGRAM) -cUSB program $(FLASH:%=-f%) -e -v -R $(if $(findstring run,$(MAKECMDGOALS)),-r) $<
+ifneq ($(call LastWord,$(filter cpuinfo program debug readregs,$(MAKECMDGOALS))),program)
+ @$(SLEEP) $(SLEEPUSB)
+else
+ @echo
+endif
+
+# Reset CPU.
+.PHONY: reset
+reset:
+ifeq ($(filter program run,$(MAKECMDGOALS)),)
+ @echo
+ @echo $(MSG_RESETTING)
+ $(VERBOSE_CMD)$(SUDO) $(PROGRAM) -cUSB reset
+ifneq ($(call LastWord,$(filter cpuinfo reset debug readregs,$(MAKECMDGOALS))),reset)
+ @$(SLEEP) $(SLEEPUSB)
+else
+ @echo
+endif
+else
+ @echo > /dev/null
+endif
+
+# Open a debug connection with the MCU.
+.PHONY: debug
+debug:
+ @echo
+ @echo $(MSG_DEBUGGING)
+ $(VERBOSE_CMD)$(SUDO) $(DBGPROXY) -cUSB $(patsubst cfi@%,-f%,$(FLASH:internal@%=-f%))
+ifneq ($(call LastWord,$(filter cpuinfo halt program reset debug run readregs,$(MAKECMDGOALS))),debug)
+ @$(SLEEP) $(SLEEPUSB)
+else
+ @echo
+endif
+
+# Start CPU execution.
+.PHONY: run
+run:
+ifeq ($(findstring program,$(MAKECMDGOALS)),)
+ @echo
+ @echo $(MSG_RUNNING)
+ $(VERBOSE_CMD)$(SUDO) $(PROGRAM) -cUSB run $(if $(findstring reset,$(MAKECMDGOALS)),-R)
+ifneq ($(call LastWord,$(filter cpuinfo debug run readregs,$(MAKECMDGOALS))),run)
+ @$(SLEEP) $(SLEEPUSB)
+else
+ @echo
+endif
+else
+ @echo > /dev/null
+endif
+
+# Read CPU registers.
+.PHONY: readregs
+readregs:
+ @echo
+ @echo $(MSG_READING_CPU_REGS)
+ $(VERBOSE_CMD)$(SUDO) $(PROGRAM) -cUSB readregs
+ifneq ($(call LastWord,$(filter cpuinfo program reset debug run readregs,$(MAKECMDGOALS))),readregs)
+ @$(SLEEP) $(SLEEPUSB)
+else
+ @echo
+endif
+
+endif
+
+# Build the documentation.
+.PHONY: doc
+doc:
+ @echo
+ @echo $(MSG_GENERATING_DOC)
+ $(VERBOSE_CMD)cd $(dir $(DOC_CFG)) && $(DOCGEN) $(notdir $(DOC_CFG))
+ @echo
+
+# Clean up the documentation.
+.PHONY: cleandoc
+cleandoc:
+ @echo $(MSG_CLEANING_DOC)
+ -$(VERBOSE_CMD)$(RM) $(DOC_PATH)
+ $(VERBOSE_NL)
+
+# Rebuild the documentation.
+.PHONY: rebuilddoc
+rebuilddoc: cleandoc doc
+
+# Display main executed commands.
+.PHONY: verbose
+ifeq ($(MAKECMDGOALS),verbose)
+verbose: all
+else
+verbose:
+ @echo > /dev/null
+endif
+ifneq ($(findstring verbose,$(MAKECMDGOALS)),)
+# Prefix displaying the following command if and only if verbose is a goal.
+VERBOSE_CMD =
+# New line displayed if and only if verbose is a goal.
+VERBOSE_NL = @echo
+else
+VERBOSE_CMD = @
+VERBOSE_NL =
+endif
+
+# ** ** COMPILATION RULES ** **
+
+# Include silently the dependency files.
+-include $(DPNDFILES)
+
+# The dependency files are not built alone but along with first generation files.
+$(DPNDFILES):
+
+# First generation files depend on make files.
+$(CPPFILES) $(ASFILES) $(OBJFILES): Makefile $(MAKECFG)
+
+ifeq ($(TGTTYPE),.elf)
+# Files resulting from linking depend on linker script.
+$(TGTFILE): $(LINKER_SCRIPT)
+endif
+
+# Preprocess: create preprocessed files from C source files.
+%.i: %.c %.d
+ @echo $(MSG_PREPROCESSING)
+ $(VERBOSE_CMD)$(CPP) $(CPPFLAGS) -MD -MP -MT '$*.i $*.x $*.o' -o $@ $<
+ @touch $*.d
+ @touch $@
+ $(VERBOSE_NL)
+
+# Preprocess & compile: create assembler files from C source files.
+%.x: %.c %.d
+ @echo $(MSG_COMPILING)
+ $(VERBOSE_CMD)$(CC) -S $(CPPFLAGS) -MD -MP -MT '$*.i $*.o' $(CFLAGS) -o $@ $<
+ @touch $*.d
+ @touch $@
+ $(VERBOSE_NL)
+
+# Preprocess: create preprocessed files from assembler source files.
+%.x: %.S %.d
+ @echo $(MSG_PREPROCESSING)
+ $(VERBOSE_CMD)$(CPP) $(CPPFLAGS) -MD -MP -MT '$*.x $*.o' -o $@ $<
+ @touch $*.d
+ @touch $@
+ $(VERBOSE_NL)
+
+# Preprocess, compile & assemble: create object files from C source files.
+%.o: %.c %.d
+ @echo $(MSG_COMPILING)
+ $(VERBOSE_CMD)$(CC) -c $(CPPFLAGS) -MD -MP -MT '$*.i $*.x' $(CFLAGS) -o $@ $<
+ @touch $*.d
+ @touch $@
+ $(VERBOSE_NL)
+
+# Preprocess & assemble: create object files from assembler source files.
+%.o: %.S %.d
+ @echo $(MSG_ASSEMBLING)
+ $(VERBOSE_CMD)$(CC) -c $(CPPFLAGS) -MD -MP -MT '$*.x' $(ASFLAGS) -o $@ $<
+ @touch $*.d
+ @touch $@
+ $(VERBOSE_NL)
+
+.PRECIOUS: $(OBJFILES)
+ifeq ($(TGTTYPE),.a)
+# Archive: create A output file from object files.
+.SECONDARY: $(TGTFILE)
+$(TGTFILE): $(OBJFILES)
+ @echo $(MSG_ARCHIVING)
+ $(VERBOSE_CMD)$(AR) $(ARFLAGS) $@ $(filter %.o,$+)
+ $(VERBOSE_NL)
+else
+ifeq ($(TGTTYPE),.elf)
+# Link: create ELF output file from object files.
+.SECONDARY: $(TGTFILE)
+$(TGTFILE): $(OBJFILES)
+ @echo $(MSG_LINKING)
+ $(VERBOSE_CMD)$(CC) $(LDFLAGS) $(filter %.o,$+) $(LOADLIBES) $(LDLIBS) -o $@
+ $(VERBOSE_NL)
+endif
+endif
+
+# Create extended listing from target output file.
+$(LSS): $(TGTFILE)
+ @echo $(MSG_EXTENDED_LISTING)
+ $(VERBOSE_CMD)$(OBJDUMP) -h -S $< > $@
+ $(VERBOSE_NL)
+
+# Create symbol table from target output file.
+$(SYM): $(TGTFILE)
+ @echo $(MSG_SYMBOL_TABLE)
+ $(VERBOSE_CMD)$(NM) -n $< > $@
+ $(VERBOSE_NL)
+
+ifeq ($(TGTTYPE),.elf)
+# Create binary image from ELF output file.
+$(BIN): $(TGTFILE)
+ @echo $(MSG_BINARY_IMAGE)
+ $(VERBOSE_CMD)$(OBJCOPY) -O binary $< $@
+ $(VERBOSE_NL)
+endif
--- /dev/null
+# Hey Emacs, this is a -*- makefile -*-\r
+\r
+# The purpose of this file is to define the build configuration variables used\r
+# by the generic Makefile. See Makefile header for further information.\r
+\r
+# Copyright (c) 2007, Atmel Corporation All rights reserved.\r
+#\r
+# Redistribution and use in source and binary forms, with or without\r
+# modification, are permitted provided that the following conditions are met:\r
+#\r
+# 1. Redistributions of source code must retain the above copyright notice, this\r
+# list of conditions and the following disclaimer.\r
+#\r
+# 2. Redistributions in binary form must reproduce the above copyright notice,\r
+# this list of conditions and the following disclaimer in the documentation and/\r
+# or other materials provided with the distribution.\r
+#\r
+# 3. The name of ATMEL may not be used to endorse or promote products derived\r
+# from this software without specific prior written permission.\r
+#\r
+# THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED\r
+# WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+# MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND\r
+# SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,\r
+# INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\r
+# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\r
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY\r
+# OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+# EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+\r
+\r
+# Base paths\r
+PRJ_PATH = ../..\r
+APPS_PATH = $(PRJ_PATH)/APPLICATIONS\r
+BRDS_PATH = $(PRJ_PATH)/BOARDS\r
+COMP_PATH = $(PRJ_PATH)/COMPONENTS\r
+DRVR_PATH = $(PRJ_PATH)/DRIVERS\r
+SERV_PATH = $(PRJ_PATH)/SERVICES\r
+UTIL_PATH = $(PRJ_PATH)/UTILS\r
+\r
+# Demo paths\r
+FREERTOS_PATH = ../../../..\r
+FREERTOS_PORT_PATH = $(FREERTOS_PATH)/Source/portable/GCC/AVR32_UC3\r
+FREERTOS_MEM_PATH = $(FREERTOS_PATH)/Source/portable/MemMang\r
+DEMO_PATH = ../..\r
+ETH_PATH = $(DEMO_PATH)/NETWORK\r
+WEB_PATH = $(ETH_PATH)/BasicWEB\r
+TFTP_PATH = $(ETH_PATH)/BasicTFTP\r
+SMTP_PATH = $(ETH_PATH)/BasicSMTP\r
+EMAC_PATH = $(ETH_PATH)/EMAC\r
+LWIP_PATH = $(FREERTOS_PATH)/Demo/Common/ethernet/lwIP\r
+LWIP_PORT_PATH = $(ETH_PATH)/lwip-port/AT32UC3A\r
+\r
+# CPU architecture: {ap|uc}\r
+ARCH = uc\r
+\r
+# Part: {none|ap7000|ap7010|ap7020|uc3a0256|uc3a0512|uc3a1128|uc3a1256|uc3a1512}\r
+PART = uc3a0512\r
+\r
+# Flash memories: [type@address,size]...\r
+FLASH = internal@0x80000000,512Kb\r
+\r
+# Device/Platform/Board include path\r
+PLATFORM_INC_PATH = \\r
+ $(BRDS_PATH)/\r
+\r
+# Target name: {*.a|*.elf}\r
+TARGET = lwipdemo.elf\r
+\r
+# Definitions: [-D name[=definition]...] [-U name...]\r
+# Things that might be added to DEFS:\r
+# BOARD Board used: {EVK1100}\r
+DEFS = -D BOARD=EVK1100 -D FREERTOS_USED -D HTTP_USED=1 -D TFTP_USED=1 -D SMTP_USED=0\r
+\r
+# Include path\r
+INC_PATH = \\r
+ $(UTIL_PATH)/ \\r
+ $(UTIL_PATH)/PREPROCESSOR/ \\r
+ $(DRVR_PATH)/INTC/ \\r
+ $(DRVR_PATH)/TC/ \\r
+ $(DRVR_PATH)/PM/ \\r
+ $(DRVR_PATH)/GPIO/ \\r
+ $(DRVR_PATH)/FLASHC/ \\r
+ $(DEMO_PATH)/ \\r
+ $(FREERTOS_PATH)/Source/include/ \\r
+ $(FREERTOS_PATH)/Demo/Common/include/ \\r
+ $(FREERTOS_PORT_PATH)/ \\r
+ $(FREERTOS_MEM_PATH)/ \\r
+ $(ETH_PATH)/ \\r
+ $(EMAC_PATH)/ \\r
+ $(LWIP_PATH)/include/ \\r
+ $(LWIP_PATH)/include/ipv4/ \\r
+ $(LWIP_PORT_PATH)/ \\r
+ $(WEB_PATH)/ \\r
+ $(TFTP_PATH)/ \\r
+ $(SMTP_PATH)/\r
+\r
+# C source files\r
+\r
+LWIP_SRC = \\r
+ $(LWIP_PATH)/core/inet.c \\r
+ $(LWIP_PATH)/core/mem.c \\r
+ $(LWIP_PATH)/core/memp.c \\r
+ $(LWIP_PATH)/core/netif.c \\r
+ $(LWIP_PATH)/core/pbuf.c \\r
+ $(LWIP_PATH)/core/raw.c \\r
+ $(LWIP_PATH)/core/stats.c \\r
+ $(LWIP_PATH)/core/sys.c \\r
+ $(LWIP_PATH)/core/tcp.c \\r
+ $(LWIP_PATH)/core/tcp_in.c \\r
+ $(LWIP_PATH)/core/tcp_out.c \\r
+ $(LWIP_PATH)/core/ipv4/ip.c \\r
+ $(LWIP_PATH)/core/ipv4/ip_addr.c \\r
+ $(LWIP_PATH)/core/ipv4/icmp.c \\r
+ $(LWIP_PATH)/api/sockets.c \\r
+ $(LWIP_PATH)/api/tcpip.c \\r
+ $(LWIP_PATH)/api/api_msg.c \\r
+ $(LWIP_PATH)/api/err.c \\r
+ $(LWIP_PATH)/api/api_lib.c \\r
+ $(LWIP_PATH)/netif/etharp.c \\r
+ $(LWIP_PATH)/core/udp.c \\r
+ $(LWIP_PATH)/core/ipv4/ip_frag.c\r
+\r
+CSRCS = \\r
+ $(BRDS_PATH)/EVK1100/led.c \\r
+ $(DRVR_PATH)/INTC/intc.c \\r
+ $(DRVR_PATH)/TC/tc.c \\r
+ $(DRVR_PATH)/PM/pm.c \\r
+ $(DRVR_PATH)/GPIO/gpio.c \\r
+ $(DRVR_PATH)/FLASHC/flashc.c \\r
+ $(DEMO_PATH)/main.c \\r
+ $(DEMO_PATH)/PARTEST/ParTest.c \\r
+ $(DEMO_PATH)/SERIAL/serial.c \\r
+ $(FREERTOS_PATH)/Source/tasks.c \\r
+ $(FREERTOS_PATH)/Source/queue.c \\r
+ $(FREERTOS_PATH)/Source/list.c \\r
+ $(FREERTOS_PATH)/Source/croutine.c \\r
+ $(FREERTOS_PATH)/Demo/Common/Minimal/flash.c \\r
+ $(FREERTOS_PORT_PATH)/port.c \\r
+ $(FREERTOS_MEM_PATH)/heap_3.c \\r
+ $(LWIP_SRC) \\r
+ $(LWIP_PORT_PATH)/sys_arch.c \\r
+ $(LWIP_PORT_PATH)/ethernetif.c \\r
+ $(WEB_PATH)/BasicWEB.c \\r
+ $(TFTP_PATH)/BasicTFTP.c \\r
+ $(SMTP_PATH)/BasicSMTP.c \\r
+ $(ETH_PATH)/ethernet.c \\r
+ $(EMAC_PATH)/AVR32_EMAC.c \\r
+ $(EMAC_PATH)/AVR32_EMAC_ISR.c \\r
+ $(DEMO_PATH)/printf-stdarg.c\r
+\r
+# Assembler source files\r
+ASSRCS = \\r
+ $(FREERTOS_PORT_PATH)/exception.S\r
+\r
+# Library path\r
+LIB_PATH =\r
+\r
+# Libraries to link with the project\r
+LIBS =\r
+\r
+# Linker script file if any\r
+LINKER_SCRIPT =\r
+\r
+# Options to request or suppress warnings: [-fsyntax-only] [-pedantic[-errors]] [-w] [-Wwarning...]\r
+# For further details, refer to the chapter "GCC Command Options" of the GCC manual.\r
+WARNINGS = -Wall\r
+\r
+# Options for debugging: [-g]...\r
+# For further details, refer to the chapter "GCC Command Options" of the GCC manual.\r
+DEBUG = -g\r
+\r
+# Options that control optimization: [-O[0|1|2|3|s]]...\r
+# For further details, refer to the chapter "GCC Command Options" of the GCC manual.\r
+OPTIMIZATION = -O0 -ffunction-sections -fdata-sections\r
+\r
+# Extra flags to use when preprocessing\r
+CPP_EXTRA_FLAGS =\r
+\r
+# Extra flags to use when compiling\r
+C_EXTRA_FLAGS =\r
+\r
+# Extra flags to use when assembling\r
+AS_EXTRA_FLAGS =\r
+\r
+# Extra flags to use when linking\r
+LD_EXTRA_FLAGS = -Wl,--gc-sections\r
+\r
+# Documentation path\r
+DOC_PATH = ./DOC/\r
+\r
+# Documentation configuration file\r
+DOC_CFG = ./doxyfile.doxygen\r
--- /dev/null
+target extended-remote 127.0.0.1:1024\r
+symbol uc3a0512-demo.elf\r
+\r
+\r
+define current_task\r
+printf "Task name: %s\n", ((tskTCB *)pxCurrentTCB)->pcTaskName\r
+printf "pxTopOfStack: %x\n", ((tskTCB *)pxCurrentTCB)->pxTopOfStack\r
+end\r
--- /dev/null
+/* This header file is part of the ATMEL FREERTOS-0.9.0 Release */\r
+\r
+/*This file is prepared for Doxygen automatic documentation generation.*/\r
+/*! \file *********************************************************************\r
+ *\r
+ * \brief AT32UC3A EVK1100 board header file.\r
+ *\r
+ * This file contains definitions and services related to the features of the\r
+ * EVK1100 board.\r
+ *\r
+ * - Compiler: IAR EWAVR32 and GNU GCC for AVR32\r
+ * - Supported devices: All AVR32 AT32UC3A devices can be used.\r
+ * - AppNote:\r
+ *\r
+ * \author Atmel Corporation: http://www.atmel.com \n\r
+ * Support email: avr32@atmel.com\r
+ *\r
+ ******************************************************************************/\r
+\r
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of ATMEL may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND\r
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,\r
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\r
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\r
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF\r
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ */\r
+\r
+\r
+#ifndef _EVK1100_H_\r
+#define _EVK1100_H_\r
+\r
+#include "compiler.h"\r
+\r
+#ifdef __AVR32_ABI_COMPILER__ // Automatically defined when compiling for AVR32, not when assembling.\r
+# include "led.h"\r
+#endif // __AVR32_ABI_COMPILER__\r
+\r
+\r
+/*! \name Oscillator Definitions\r
+ */\r
+//! @{\r
+\r
+// RCOsc has no custom calibration by default. Set the following definition to\r
+// the appropriate value if a custom RCOsc calibration has been applied to your\r
+// part.\r
+//#define FRCOSC 115200 //!< RCOsc frequency: Hz.\r
+\r
+#define FOSC32 32000 //!< Osc32 frequency: Hz.\r
+#define OSC32_STARTUP 3 //!< Osc32 startup time: RCOsc periods.\r
+\r
+#define FOSC0 12000000 //!< Osc0 frequency: Hz.\r
+#define OSC0_STARTUP 3 //!< Osc0 startup time: RCOsc periods.\r
+\r
+// Osc1 crystal is not mounted by default. Set the following definitions to the\r
+// appropriate values if a custom Osc1 crystal is mounted on your board.\r
+//#define FOSC1 12000000 //!< Osc1 frequency: Hz.\r
+//#define OSC1_STARTUP 3 //!< Osc1 startup time: RCOsc periods.\r
+\r
+//! @}\r
+\r
+\r
+/*! \name SDRAM Definitions\r
+ */\r
+//! @{\r
+\r
+//! Part header file of used SDRAM(s).\r
+#define SDRAM_PART_HDR "MT48LC16M16A2TG7E/mt48lc16m16a2tg7e.h"\r
+\r
+//! Data bus width to use the SDRAM(s) with (16 or 32 bits; always 16 bits on\r
+//! UC3).\r
+#define SDRAM_DBW 16\r
+\r
+//! @}\r
+\r
+\r
+/*! \name USB Definitions\r
+ */\r
+//! @{\r
+\r
+//! Multiplexed pin used for USB_ID: AVR32_USBB_USB_ID_x_x.\r
+//! To be selected according to the AVR32_USBB_USB_ID_x_x_PIN and\r
+//! AVR32_USBB_USB_ID_x_x_FUNCTION definitions from <avr32/uc3axxxx.h>.\r
+#define USB_ID AVR32_USBB_USB_ID_0_0\r
+\r
+//! Multiplexed pin used for USB_VBOF: AVR32_USBB_USB_VBOF_x_x.\r
+//! To be selected according to the AVR32_USBB_USB_VBOF_x_x_PIN and\r
+//! AVR32_USBB_USB_VBOF_x_x_FUNCTION definitions from <avr32/uc3axxxx.h>.\r
+#ifdef EVK1100_REVA\r
+# define USB_VBOF AVR32_USBB_USB_VBOF_0_0\r
+#else\r
+# define USB_VBOF AVR32_USBB_USB_VBOF_0_1\r
+#endif\r
+\r
+//! Active level of the USB_VBOF output pin.\r
+#ifdef EVK1100_REVA\r
+# define USB_VBOF_ACTIVE_LEVEL HIGH\r
+#else\r
+# define USB_VBOF_ACTIVE_LEVEL LOW\r
+#endif\r
+\r
+//! @}\r
+\r
+\r
+//! GPIO connection of the MAC PHY PWR_DOWN/INT signal.\r
+#ifdef EVK1100_REVA\r
+# define MACB_INTERRUPT_PIN AVR32_PIN_PX12\r
+#else\r
+# define MACB_INTERRUPT_PIN AVR32_PIN_PA24\r
+#endif\r
+\r
+\r
+//! Number of LEDs.\r
+#define LED_COUNT 8\r
+\r
+/*! \name GPIO Connections of LEDs\r
+ */\r
+//! @{\r
+#ifdef EVK1100_REVA\r
+# define LED0_GPIO AVR32_PIN_PX13\r
+# define LED1_GPIO AVR32_PIN_PX14\r
+# define LED2_GPIO AVR32_PIN_PX15\r
+# define LED3_GPIO AVR32_PIN_PX16\r
+# define LED4_GPIO AVR32_PIN_PB19\r
+# define LED5_GPIO AVR32_PIN_PB20\r
+# define LED6_GPIO AVR32_PIN_PB21\r
+# define LED7_GPIO AVR32_PIN_PB22\r
+#else\r
+# define LED0_GPIO AVR32_PIN_PB27\r
+# define LED1_GPIO AVR32_PIN_PB28\r
+# define LED2_GPIO AVR32_PIN_PB29\r
+# define LED3_GPIO AVR32_PIN_PB30\r
+# define LED4_GPIO AVR32_PIN_PB19\r
+# define LED5_GPIO AVR32_PIN_PB20\r
+# define LED6_GPIO AVR32_PIN_PB21\r
+# define LED7_GPIO AVR32_PIN_PB22\r
+#endif\r
+//! @}\r
+\r
+/*! \name PWM Channels of LEDs\r
+ */\r
+//! @{\r
+#define LED0_PWM (-1)\r
+#define LED1_PWM (-1)\r
+#define LED2_PWM (-1)\r
+#define LED3_PWM (-1)\r
+#define LED4_PWM 0\r
+#define LED5_PWM 1\r
+#define LED6_PWM 2\r
+#define LED7_PWM 3\r
+//! @}\r
+\r
+/*! \name PWM Functions of LEDs\r
+ */\r
+//! @{\r
+#define LED0_PWM_FUNCTION (-1)\r
+#define LED1_PWM_FUNCTION (-1)\r
+#define LED2_PWM_FUNCTION (-1)\r
+#define LED3_PWM_FUNCTION (-1)\r
+#define LED4_PWM_FUNCTION AVR32_PWM_PWM_0_FUNCTION\r
+#define LED5_PWM_FUNCTION AVR32_PWM_PWM_1_FUNCTION\r
+#define LED6_PWM_FUNCTION AVR32_PWM_PWM_2_FUNCTION\r
+#define LED7_PWM_FUNCTION AVR32_PWM_PWM_3_FUNCTION\r
+//! @}\r
+\r
+/*! \name Color Identifiers of LEDs to Use with LED Functions\r
+ */\r
+//! @{\r
+#ifdef EVK1100_REVA\r
+# define LED_MONO0_GREEN LED4\r
+# define LED_MONO1_GREEN LED5\r
+# define LED_MONO2_GREEN LED6\r
+# define LED_MONO3_GREEN LED7\r
+# define LED_BI0_GREEN LED1\r
+# define LED_BI0_RED LED0\r
+# define LED_BI1_GREEN LED3\r
+# define LED_BI1_RED LED2\r
+#else\r
+# define LED_MONO0_GREEN LED0\r
+# define LED_MONO1_GREEN LED1\r
+# define LED_MONO2_GREEN LED2\r
+# define LED_MONO3_GREEN LED3\r
+# define LED_BI0_GREEN LED5\r
+# define LED_BI0_RED LED4\r
+# define LED_BI1_GREEN LED7\r
+# define LED_BI1_RED LED6\r
+#endif\r
+//! @}\r
+\r
+\r
+/*! \name GPIO Connections of Push Buttons\r
+ */\r
+//! @{\r
+#ifdef EVK1100_REVA\r
+# define GPIO_PUSH_BUTTON_0 AVR32_PIN_PB28\r
+# define GPIO_PUSH_BUTTON_1 AVR32_PIN_PB29\r
+# define GPIO_PUSH_BUTTON_2 AVR32_PIN_PB27\r
+#else\r
+# define GPIO_PUSH_BUTTON_0 AVR32_PIN_PX16\r
+# define GPIO_PUSH_BUTTON_1 AVR32_PIN_PX19\r
+# define GPIO_PUSH_BUTTON_2 AVR32_PIN_PX22\r
+#endif\r
+//! @}\r
+\r
+\r
+/*! \name GPIO Connections of the Joystick\r
+ */\r
+//! @{\r
+#define GPIO_JOYSTICK_PUSH AVR32_PIN_PA20\r
+#define GPIO_JOYSTICK_LEFT AVR32_PIN_PA25\r
+#define GPIO_JOYSTICK_RIGHT AVR32_PIN_PA28\r
+#define GPIO_JOYSTICK_UP AVR32_PIN_PA26\r
+#define GPIO_JOYSTICK_DOWN AVR32_PIN_PA27\r
+//! @}\r
+\r
+\r
+/*! \name ADC Connection of the Potentiometer\r
+ */\r
+//! @{\r
+#define ADC_POTENTIOMETER_CHANNEL 1\r
+#define ADC_POTENTIOMETER_PIN AVR32_ADC_AD_1_PIN\r
+#define ADC_POTENTIOMETER_FUNCTION AVR32_ADC_AD_1_FUNCTION\r
+//! @}\r
+\r
+\r
+/*! \name ADC Connection of the Temperature Sensor\r
+ */\r
+//! @{\r
+#define ADC_TEMPERATURE_CHANNEL 0\r
+#define ADC_TEMPERATURE_PIN AVR32_ADC_AD_0_PIN\r
+#define ADC_TEMPERATURE_FUNCTION AVR32_ADC_AD_0_FUNCTION\r
+//! @}\r
+\r
+\r
+/*! \name ADC Connection of the Light Sensor\r
+ */\r
+//! @{\r
+#define ADC_LIGHT_CHANNEL 2\r
+#define ADC_LIGHT_PIN AVR32_ADC_AD_2_PIN\r
+#define ADC_LIGHT_FUNCTION AVR32_ADC_AD_2_FUNCTION\r
+//! @}\r
+\r
+\r
+/*! \name SPI Connections of the DIP204 LCD\r
+ */\r
+//! @{\r
+#define DIP204_SPI (&AVR32_SPI1)\r
+#define DIP204_SPI_CS 2\r
+#define DIP204_SPI_SCK_PIN AVR32_SPI1_SCK_0_PIN\r
+#define DIP204_SPI_SCK_FUNCTION AVR32_SPI1_SCK_0_FUNCTION\r
+#define DIP204_SPI_MISO_PIN AVR32_SPI1_MISO_0_PIN\r
+#define DIP204_SPI_MISO_FUNCTION AVR32_SPI1_MISO_0_FUNCTION\r
+#define DIP204_SPI_MOSI_PIN AVR32_SPI1_MOSI_0_PIN\r
+#define DIP204_SPI_MOSI_FUNCTION AVR32_SPI1_MOSI_0_FUNCTION\r
+#define DIP204_SPI_NPCS_PIN AVR32_SPI1_NPCS_2_PIN\r
+#define DIP204_SPI_NPCS_FUNCTION AVR32_SPI1_NPCS_2_FUNCTION\r
+//! @}\r
+\r
+/*! \name GPIO and PWM Connections of the DIP204 LCD Backlight\r
+ */\r
+//! @{\r
+#define DIP204_BACKLIGHT_PIN AVR32_PIN_PB18\r
+#define DIP204_PWM_CHANNEL AVR32_PWM_CHID6\r
+#define DIP204_PWM_PIN AVR32_PWM_PWM_6_PIN\r
+#define DIP204_PWM_FUNCTION AVR32_PWM_PWM_6_FUNCTION\r
+//! @}\r
+\r
+\r
+/*! \name SPI Connections of the AT45DBX Data Flash Memory\r
+ */\r
+//! @{\r
+#define AT45DBX_SPI (&AVR32_SPI1)\r
+#define AT45DBX_SPI_SCK_PIN AVR32_SPI1_SCK_0_PIN\r
+#define AT45DBX_SPI_SCK_FUNCTION AVR32_SPI1_SCK_0_FUNCTION\r
+#define AT45DBX_SPI_MISO_PIN AVR32_SPI1_MISO_0_PIN\r
+#define AT45DBX_SPI_MISO_FUNCTION AVR32_SPI1_MISO_0_FUNCTION\r
+#define AT45DBX_SPI_MOSI_PIN AVR32_SPI1_MOSI_0_PIN\r
+#define AT45DBX_SPI_MOSI_FUNCTION AVR32_SPI1_MOSI_0_FUNCTION\r
+#define AT45DBX_SPI_NPCS0_PIN AVR32_SPI1_NPCS_0_PIN\r
+#define AT45DBX_SPI_NPCS0_FUNCTION AVR32_SPI1_NPCS_0_FUNCTION\r
+//! @}\r
+\r
+\r
+/*! \name SPI Connections of the SD/MMC Connector\r
+ */\r
+//! @{\r
+#define SD_MMC_SPI (&AVR32_SPI1)\r
+#define SD_MMC_SPI_CS 1\r
+#define SD_MMC_SPI_SCK_PIN AVR32_SPI1_SCK_0_PIN\r
+#define SD_MMC_SPI_SCK_FUNCTION AVR32_SPI1_SCK_0_FUNCTION\r
+#define SD_MMC_SPI_MISO_PIN AVR32_SPI1_MISO_0_PIN\r
+#define SD_MMC_SPI_MISO_FUNCTION AVR32_SPI1_MISO_0_FUNCTION\r
+#define SD_MMC_SPI_MOSI_PIN AVR32_SPI1_MOSI_0_PIN\r
+#define SD_MMC_SPI_MOSI_FUNCTION AVR32_SPI1_MOSI_0_FUNCTION\r
+#define SD_MMC_SPI_NPCS_PIN AVR32_SPI1_NPCS_1_PIN\r
+#define SD_MMC_SPI_NPCS_FUNCTION AVR32_SPI1_NPCS_1_FUNCTION\r
+//! @}\r
+\r
+\r
+#endif // _EVK1100_H_\r
--- /dev/null
+/* This source file is part of the ATMEL FREERTOS-0.9.0 Release */\r
+\r
+/*This file is prepared for Doxygen automatic documentation generation.*/\r
+/*! \file *********************************************************************\r
+ *\r
+ * \brief AT32UC3A EVK1100 board LEDs support package.\r
+ *\r
+ * This file contains definitions and services related to the LED features of\r
+ * the EVK1100 board.\r
+ *\r
+ * - Compiler: IAR EWAVR32 and GNU GCC for AVR32\r
+ * - Supported devices: All AVR32 AT32UC3A devices can be used.\r
+ * - AppNote:\r
+ *\r
+ * \author Atmel Corporation: http://www.atmel.com \n\r
+ * Support email: avr32@atmel.com\r
+ *\r
+ ******************************************************************************/\r
+\r
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of ATMEL may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND\r
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,\r
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\r
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\r
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF\r
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ */\r
+\r
+\r
+#if __GNUC__\r
+# include <avr32/io.h>\r
+#elif __ICCAVR32__\r
+# include <avr32/iouc3a0512.h>\r
+#else\r
+# error Unknown compiler\r
+#endif\r
+\r
+#include "preprocessor.h"\r
+#include "compiler.h"\r
+#include "evk1100.h"\r
+#include "led.h"\r
+\r
+\r
+//! Structure describing LED hardware connections.\r
+typedef const struct\r
+{\r
+ struct\r
+ {\r
+ U32 PORT; //!< LED GPIO port.\r
+ U32 PIN_MASK; //!< Bit-mask of LED pin in GPIO port.\r
+ } GPIO; //!< LED GPIO descriptor.\r
+ struct\r
+ {\r
+ S32 CHANNEL; //!< LED PWM channel (< 0 if N/A).\r
+ S32 FUNCTION; //!< LED pin PWM function (< 0 if N/A).\r
+ } PWM; //!< LED PWM descriptor.\r
+} tLED_DESCRIPTOR;\r
+\r
+\r
+//! Hardware descriptors of all LEDs.\r
+static tLED_DESCRIPTOR LED_DESCRIPTOR[LED_COUNT] =\r
+{\r
+#define INSERT_LED_DESCRIPTOR(LED_NO, unused) \\r
+ { \\r
+ {LED##LED_NO##_GPIO / 32, 1 << (LED##LED_NO##_GPIO % 32)},\\r
+ {LED##LED_NO##_PWM, LED##LED_NO##_PWM_FUNCTION } \\r
+ },\r
+ MREPEAT(LED_COUNT, INSERT_LED_DESCRIPTOR, ~)\r
+#undef INSERT_LED_DESCRIPTOR\r
+};\r
+\r
+\r
+//! Saved state of all LEDs.\r
+static U32 LED_State = (1 << LED_COUNT) - 1;\r
+\r
+\r
+U32 LED_Read_Display(void)\r
+{\r
+ return LED_State;\r
+}\r
+\r
+\r
+void LED_Display(U32 leds)\r
+{\r
+ tLED_DESCRIPTOR *led_descriptor;\r
+ volatile avr32_gpio_port_t *led_gpio_port;\r
+\r
+ leds &= (1 << LED_COUNT) - 1;\r
+ LED_State = leds;\r
+ for (led_descriptor = &LED_DESCRIPTOR[0];\r
+ led_descriptor < LED_DESCRIPTOR + LED_COUNT;\r
+ led_descriptor++)\r
+ {\r
+ led_gpio_port = &AVR32_GPIO.port[led_descriptor->GPIO.PORT];\r
+ if (leds & 1)\r
+ {\r
+ led_gpio_port->ovrc = led_descriptor->GPIO.PIN_MASK;\r
+ }\r
+ else\r
+ {\r
+ led_gpio_port->ovrs = led_descriptor->GPIO.PIN_MASK;\r
+ }\r
+ led_gpio_port->oders = led_descriptor->GPIO.PIN_MASK;\r
+ led_gpio_port->gpers = led_descriptor->GPIO.PIN_MASK;\r
+ leds >>= 1;\r
+ }\r
+}\r
+\r
+\r
+U32 LED_Read_Display_Mask(U32 mask)\r
+{\r
+ return Rd_bits(LED_State, mask);\r
+}\r
+\r
+\r
+void LED_Display_Mask(U32 mask, U32 leds)\r
+{\r
+ tLED_DESCRIPTOR *led_descriptor = &LED_DESCRIPTOR[0] - 1;\r
+ volatile avr32_gpio_port_t *led_gpio_port;\r
+ U8 led_shift;\r
+\r
+ mask &= (1 << LED_COUNT) - 1;\r
+ Wr_bits(LED_State, mask, leds);\r
+ while (mask)\r
+ {\r
+ led_shift = 1 + ctz(mask);\r
+ led_descriptor += led_shift;\r
+ led_gpio_port = &AVR32_GPIO.port[led_descriptor->GPIO.PORT];\r
+ leds >>= led_shift - 1;\r
+ if (leds & 1)\r
+ {\r
+ led_gpio_port->ovrc = led_descriptor->GPIO.PIN_MASK;\r
+ }\r
+ else\r
+ {\r
+ led_gpio_port->ovrs = led_descriptor->GPIO.PIN_MASK;\r
+ }\r
+ led_gpio_port->oders = led_descriptor->GPIO.PIN_MASK;\r
+ led_gpio_port->gpers = led_descriptor->GPIO.PIN_MASK;\r
+ leds >>= 1;\r
+ mask >>= led_shift;\r
+ }\r
+}\r
+\r
+\r
+Bool LED_Test(U32 leds)\r
+{\r
+ return Tst_bits(LED_State, leds);\r
+}\r
+\r
+\r
+void LED_Off(U32 leds)\r
+{\r
+ tLED_DESCRIPTOR *led_descriptor = &LED_DESCRIPTOR[0] - 1;\r
+ volatile avr32_gpio_port_t *led_gpio_port;\r
+ U8 led_shift;\r
+\r
+ leds &= (1 << LED_COUNT) - 1;\r
+ Clr_bits(LED_State, leds);\r
+ while (leds)\r
+ {\r
+ led_shift = 1 + ctz(leds);\r
+ led_descriptor += led_shift;\r
+ led_gpio_port = &AVR32_GPIO.port[led_descriptor->GPIO.PORT];\r
+ led_gpio_port->ovrs = led_descriptor->GPIO.PIN_MASK;\r
+ led_gpio_port->oders = led_descriptor->GPIO.PIN_MASK;\r
+ led_gpio_port->gpers = led_descriptor->GPIO.PIN_MASK;\r
+ leds >>= led_shift;\r
+ }\r
+}\r
+\r
+\r
+void LED_On(U32 leds)\r
+{\r
+ tLED_DESCRIPTOR *led_descriptor = &LED_DESCRIPTOR[0] - 1;\r
+ volatile avr32_gpio_port_t *led_gpio_port;\r
+ U8 led_shift;\r
+\r
+ leds &= (1 << LED_COUNT) - 1;\r
+ Set_bits(LED_State, leds);\r
+ while (leds)\r
+ {\r
+ led_shift = 1 + ctz(leds);\r
+ led_descriptor += led_shift;\r
+ led_gpio_port = &AVR32_GPIO.port[led_descriptor->GPIO.PORT];\r
+ led_gpio_port->ovrc = led_descriptor->GPIO.PIN_MASK;\r
+ led_gpio_port->oders = led_descriptor->GPIO.PIN_MASK;\r
+ led_gpio_port->gpers = led_descriptor->GPIO.PIN_MASK;\r
+ leds >>= led_shift;\r
+ }\r
+}\r
+\r
+\r
+void LED_Toggle(U32 leds)\r
+{\r
+ tLED_DESCRIPTOR *led_descriptor = &LED_DESCRIPTOR[0] - 1;\r
+ volatile avr32_gpio_port_t *led_gpio_port;\r
+ U8 led_shift;\r
+\r
+ leds &= (1 << LED_COUNT) - 1;\r
+ Tgl_bits(LED_State, leds);\r
+ while (leds)\r
+ {\r
+ led_shift = 1 + ctz(leds);\r
+ led_descriptor += led_shift;\r
+ led_gpio_port = &AVR32_GPIO.port[led_descriptor->GPIO.PORT];\r
+ led_gpio_port->ovrt = led_descriptor->GPIO.PIN_MASK;\r
+ led_gpio_port->oders = led_descriptor->GPIO.PIN_MASK;\r
+ led_gpio_port->gpers = led_descriptor->GPIO.PIN_MASK;\r
+ leds >>= led_shift;\r
+ }\r
+}\r
+\r
+\r
+U32 LED_Read_Display_Field(U32 field)\r
+{\r
+ return Rd_bitfield(LED_State, field);\r
+}\r
+\r
+\r
+void LED_Display_Field(U32 field, U32 leds)\r
+{\r
+ LED_Display_Mask(field, leds << ctz(field));\r
+}\r
+\r
+\r
+U8 LED_Get_Intensity(U32 led)\r
+{\r
+ tLED_DESCRIPTOR *led_descriptor;\r
+\r
+ // Check that the argument value is valid.\r
+ led = ctz(led);\r
+ led_descriptor = &LED_DESCRIPTOR[led];\r
+ if (led >= LED_COUNT || led_descriptor->PWM.CHANNEL < 0) return 0;\r
+\r
+ // Return the duty cycle value if the LED PWM channel is enabled, else 0.\r
+ return (AVR32_PWM.sr & (1 << led_descriptor->PWM.CHANNEL)) ?\r
+ AVR32_PWM.channel[led_descriptor->PWM.CHANNEL].cdty : 0;\r
+}\r
+\r
+\r
+void LED_Set_Intensity(U32 leds, U8 intensity)\r
+{\r
+ tLED_DESCRIPTOR *led_descriptor = &LED_DESCRIPTOR[0] - 1;\r
+ volatile avr32_pwm_channel_t *led_pwm_channel;\r
+ volatile avr32_gpio_port_t *led_gpio_port;\r
+ U8 led_shift;\r
+\r
+ // For each specified LED...\r
+ for (leds &= (1 << LED_COUNT) - 1; leds; leds >>= led_shift)\r
+ {\r
+ // Select the next specified LED and check that it has a PWM channel.\r
+ led_shift = 1 + ctz(leds);\r
+ led_descriptor += led_shift;\r
+ if (led_descriptor->PWM.CHANNEL < 0) continue;\r
+\r
+ // Initialize or update the LED PWM channel.\r
+ led_pwm_channel = &AVR32_PWM.channel[led_descriptor->PWM.CHANNEL];\r
+ if (!(AVR32_PWM.sr & (1 << led_descriptor->PWM.CHANNEL)))\r
+ {\r
+ led_pwm_channel->cmr = (AVR32_PWM_CPRE_MCK << AVR32_PWM_CPRE_OFFSET) &\r
+ ~(AVR32_PWM_CALG_MASK |\r
+ AVR32_PWM_CPOL_MASK |\r
+ AVR32_PWM_CPD_MASK);\r
+ led_pwm_channel->cprd = 0x000000FF;\r
+ led_pwm_channel->cdty = intensity;\r
+ AVR32_PWM.ena = 1 << led_descriptor->PWM.CHANNEL;\r
+ }\r
+ else\r
+ {\r
+ AVR32_PWM.isr;\r
+ while (!(AVR32_PWM.isr & (1 << led_descriptor->PWM.CHANNEL)));\r
+ led_pwm_channel->cupd = intensity;\r
+ }\r
+\r
+ // Switch the LED pin to its PWM function.\r
+ led_gpio_port = &AVR32_GPIO.port[led_descriptor->GPIO.PORT];\r
+ if (led_descriptor->PWM.FUNCTION & 0x1)\r
+ {\r
+ led_gpio_port->pmr0s = led_descriptor->GPIO.PIN_MASK;\r
+ }\r
+ else\r
+ {\r
+ led_gpio_port->pmr0c = led_descriptor->GPIO.PIN_MASK;\r
+ }\r
+ if (led_descriptor->PWM.FUNCTION & 0x2)\r
+ {\r
+ led_gpio_port->pmr1s = led_descriptor->GPIO.PIN_MASK;\r
+ }\r
+ else\r
+ {\r
+ led_gpio_port->pmr1c = led_descriptor->GPIO.PIN_MASK;\r
+ }\r
+ led_gpio_port->gperc = led_descriptor->GPIO.PIN_MASK;\r
+ }\r
+}\r
--- /dev/null
+/* This header file is part of the ATMEL FREERTOS-0.9.0 Release */\r
+\r
+/*This file is prepared for Doxygen automatic documentation generation.*/\r
+/*! \file *********************************************************************\r
+ *\r
+ * \brief AT32UC3A EVK1100 board LEDs support package.\r
+ *\r
+ * This file contains definitions and services related to the LED features of\r
+ * the EVK1100 board.\r
+ *\r
+ * - Compiler: IAR EWAVR32 and GNU GCC for AVR32\r
+ * - Supported devices: All AVR32 AT32UC3A devices can be used.\r
+ * - AppNote:\r
+ *\r
+ * \author Atmel Corporation: http://www.atmel.com \n\r
+ * Support email: avr32@atmel.com\r
+ *\r
+ ******************************************************************************/\r
+\r
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of ATMEL may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND\r
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,\r
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\r
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\r
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF\r
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ */\r
+\r
+\r
+#ifndef _LED_H_\r
+#define _LED_H_\r
+\r
+#include "compiler.h"\r
+\r
+\r
+/*! \name Identifiers of LEDs to Use with LED Functions\r
+ */\r
+//! @{\r
+#define LED0 0x01\r
+#define LED1 0x02\r
+#define LED2 0x04\r
+#define LED3 0x08\r
+#define LED4 0x10\r
+#define LED5 0x20\r
+#define LED6 0x40\r
+#define LED7 0x80\r
+//! @}\r
+\r
+\r
+/*! \brief Gets the last state of all LEDs set through the LED API.\r
+ *\r
+ * \return State of all LEDs (1 bit per LED).\r
+ *\r
+ * \note The GPIO pin configuration of all LEDs is left unchanged.\r
+ */\r
+extern U32 LED_Read_Display(void);\r
+\r
+/*! \brief Sets the state of all LEDs.\r
+ *\r
+ * \param leds New state of all LEDs (1 bit per LED).\r
+ *\r
+ * \note The pins of all LEDs are set to GPIO output mode.\r
+ */\r
+extern void LED_Display(U32 leds);\r
+\r
+/*! \brief Gets the last state of the specified LEDs set through the LED API.\r
+ *\r
+ * \param mask LEDs of which to get the state (1 bit per LED).\r
+ *\r
+ * \return State of the specified LEDs (1 bit per LED).\r
+ *\r
+ * \note The GPIO pin configuration of all LEDs is left unchanged.\r
+ */\r
+extern U32 LED_Read_Display_Mask(U32 mask);\r
+\r
+/*! \brief Sets the state of the specified LEDs.\r
+ *\r
+ * \param mask LEDs of which to set the state (1 bit per LED).\r
+ *\r
+ * \param leds New state of the specified LEDs (1 bit per LED).\r
+ *\r
+ * \note The pins of the specified LEDs are set to GPIO output mode.\r
+ */\r
+extern void LED_Display_Mask(U32 mask, U32 leds);\r
+\r
+/*! \brief Tests the last state of the specified LEDs set through the LED API.\r
+ *\r
+ * \param leds LEDs of which to test the state (1 bit per LED).\r
+ *\r
+ * \return \c TRUE if at least one of the specified LEDs has a state on, else\r
+ * \c FALSE.\r
+ *\r
+ * \note The GPIO pin configuration of all LEDs is left unchanged.\r
+ */\r
+extern Bool LED_Test(U32 leds);\r
+\r
+/*! \brief Turns off the specified LEDs.\r
+ *\r
+ * \param leds LEDs to turn off (1 bit per LED).\r
+ *\r
+ * \note The pins of the specified LEDs are set to GPIO output mode.\r
+ */\r
+extern void LED_Off(U32 leds);\r
+\r
+/*! \brief Turns on the specified LEDs.\r
+ *\r
+ * \param leds LEDs to turn on (1 bit per LED).\r
+ *\r
+ * \note The pins of the specified LEDs are set to GPIO output mode.\r
+ */\r
+extern void LED_On(U32 leds);\r
+\r
+/*! \brief Toggles the specified LEDs.\r
+ *\r
+ * \param leds LEDs to toggle (1 bit per LED).\r
+ *\r
+ * \note The pins of the specified LEDs are set to GPIO output mode.\r
+ */\r
+extern void LED_Toggle(U32 leds);\r
+\r
+/*! \brief Gets as a bit-field the last state of the specified LEDs set through\r
+ * the LED API.\r
+ *\r
+ * \param field LEDs of which to get the state (1 bit per LED).\r
+ *\r
+ * \return State of the specified LEDs (1 bit per LED, beginning with the first\r
+ * specified LED).\r
+ *\r
+ * \note The GPIO pin configuration of all LEDs is left unchanged.\r
+ */\r
+extern U32 LED_Read_Display_Field(U32 field);\r
+\r
+/*! \brief Sets as a bit-field the state of the specified LEDs.\r
+ *\r
+ * \param field LEDs of which to set the state (1 bit per LED).\r
+ * \param leds New state of the specified LEDs (1 bit per LED, beginning with\r
+ * the first specified LED).\r
+ *\r
+ * \note The pins of the specified LEDs are set to GPIO output mode.\r
+ */\r
+extern void LED_Display_Field(U32 field, U32 leds);\r
+\r
+/*! \brief Gets the intensity of the specified LED.\r
+ *\r
+ * \param led LED of which to get the intensity (1 bit per LED; only the least\r
+ * significant set bit is used).\r
+ *\r
+ * \return Intensity of the specified LED (0x00 to 0xFF).\r
+ *\r
+ * \warning The PWM channel of the specified LED is supposed to be used only by\r
+ * this module.\r
+ *\r
+ * \note The GPIO pin configuration of all LEDs is left unchanged.\r
+ */\r
+extern U8 LED_Get_Intensity(U32 led);\r
+\r
+/*! \brief Sets the intensity of the specified LEDs.\r
+ *\r
+ * \param leds LEDs of which to set the intensity (1 bit per LED).\r
+ * \param intensity New intensity of the specified LEDs (0x00 to 0xFF).\r
+ *\r
+ * \warning The PWM channels of the specified LEDs are supposed to be used only\r
+ * by this module.\r
+ *\r
+ * \note The pins of the specified LEDs are set to PWM output mode.\r
+ */\r
+extern void LED_Set_Intensity(U32 leds, U8 intensity);\r
+\r
+\r
+#endif // _LED_H_\r
--- /dev/null
+/* This header file is part of the ATMEL FREERTOS-0.9.0 Release */\r
+\r
+/*This file is prepared for Doxygen automatic documentation generation.*/\r
+/*! \file *********************************************************************\r
+ *\r
+ * \brief Standard board header file.\r
+ *\r
+ * This file includes the appropriate board header file according to the\r
+ * defined board.\r
+ *\r
+ * - Compiler: IAR EWAVR32 and GNU GCC for AVR32\r
+ * - Supported devices: All AVR32 devices can be used.\r
+ * - AppNote:\r
+ *\r
+ * \author Atmel Corporation: http://www.atmel.com \n\r
+ * Support email: avr32@atmel.com\r
+ *\r
+ ******************************************************************************/\r
+\r
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of ATMEL may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND\r
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,\r
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\r
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\r
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF\r
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ */\r
+\r
+\r
+#ifndef _BOARD_H_\r
+#define _BOARD_H_\r
+\r
+#if __GNUC__\r
+# include <avr32/io.h>\r
+#elif __ICCAVR32__ || __AAVR32__\r
+# include <avr32/iouc3a0512.h>\r
+#else\r
+# error Unknown compiler\r
+#endif\r
+\r
+#define EVK1100 1 //!< AT32UC3A EVK1100 board.\r
+\r
+#if BOARD == EVK1100\r
+# include "EVK1100/evk1100.h"\r
+#else\r
+# error No known AVR32 board defined\r
+#endif\r
+\r
+\r
+#ifndef FRCOSC\r
+# define FRCOSC AVR32_PM_RCOSC_FREQUENCY //!< Default RCOsc frequency.\r
+#endif\r
+\r
+\r
+#endif // _BOARD_H_\r
--- /dev/null
+/* This source file is part of the ATMEL FREERTOS-0.9.0 Release */\r
+\r
+/*This file has been prepared for Doxygen automatic documentation generation.*/\r
+/*! \file *********************************************************************\r
+ *\r
+ * \brief Flash Controller driver.\r
+ *\r
+ * This file defines a useful set of functions for the flash controller\r
+ * on AVR32A devices.\r
+ *\r
+ * - Compiler: IAR EWAVR32 and GNU GCC for AVR32\r
+ * - Supported devices: All AVR32A devices.\r
+ *\r
+ * \author Atmel Corporation: http://www.atmel.com \n\r
+ * Support email: avr32@atmel.com\r
+ *\r
+ *****************************************************************************/\r
+\r
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of ATMEL may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND\r
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,\r
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\r
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\r
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF\r
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ */\r
+\r
+\r
+#include "flashc.h"\r
+\r
+/*! Flash command key*/\r
+#define X_KEY 0xA5000000\r
+\r
+\r
+/*! Get locke error.\r
+ * \warning: Flash status register (FCR) is read, and Programmming error status may be automatically\r
+ * cleared when reading FCR.\r
+ */\r
+#define Flashc_get_lockerror() ((AVR32_FLASHC.fsr & AVR32_FLASHC_FSR_LOCKE_MASK)>>AVR32_FLASHC_FSR_LOCKE_OFFSET)\r
+\r
+/*! Get programming error.\r
+ * \warning: Flash status register (FCR) is read, and locke error status may be automatically\r
+ * cleared when reading FCR.\r
+ */\r
+#define Flashc_get_programming_error() ((AVR32_FLASHC.fsr & AVR32_FLASHC_FSR_PROGE_MASK)>>AVR32_FLASHC_FSR_PROGE_OFFSET)\r
+\r
+/*! Check if page is erased (used with the quick page read command result)\r
+ * \warning: Flash status register (FCR) is read, and error status may be automatically\r
+ * cleared when reading FCR.\r
+ */\r
+#define Flashc_is_page_erased() ((AVR32_FLASHC.fsr & AVR32_FLASHC_FSR_QPRR_MASK)>>AVR32_FLASHC_FSR_QPRR_OFFSET)\r
+\r
+/*! Set: No erase is performed before programming. */\r
+#define Flashc_set_no_erase_before_programming() (AVR32_FLASHC.fcr |= AVR32_FLASHC_FCR_NEBP_MASK)\r
+\r
+/*! Set: Page erase is performed before programming. */\r
+#define Flashc_set_erase_before_programming() (AVR32_FLASHC.fcr &= ~AVR32_FLASHC_FCR_NEBP_MASK)\r
+\r
+\r
+/*!\r
+ * Memcopy function\r
+ * \param *s1 destination\r
+ * \param *s2 source\r
+ * \param n word numbers to copy\r
+ */\r
+U32 *flashc_memcpy(U32 *s1, const U32 *s2, const U32 n) {\r
+ register U32 *u32pdst;\r
+ register U32 i;\r
+ u32pdst = s1;\r
+ for (i = n; i > 0; i--) *u32pdst++ = *s2++;\r
+ return s1;\r
+}\r
+\r
+/*!\r
+ * Set number of wait state for flash controller.\r
+ */\r
+int flashc_set_wait_state(U16 ws)\r
+{\r
+ if (ws > 1 ) return FLASHC_INVALID_INPUT;\r
+ if (ws == 0) AVR32_FLASHC.fcr &= ~AVR32_FLASHC_FWS_MASK; // update flash control register FCR\r
+ if (ws == 1) AVR32_FLASHC.fcr |= AVR32_FLASHC_FWS_MASK;\r
+ return FLASHC_SUCCESS;\r
+}\r
+\r
+\r
+/*!\r
+ * Page write n\r
+ * \param n page number\r
+ * \warning Assuming the page address is already loaded\r
+ */\r
+void flashc_page_write_n(U16 page_n) {\r
+ register U32 u32Command;\r
+ u32Command = X_KEY | AVR32_FLASHC_FCMD_CMD_WP; // key and command\r
+ u32Command |= ((page_n<<AVR32_FLASHC_FCMD_PAGEN_OFFSET) & AVR32_FLASHC_FCMD_PAGEN_MASK); // update page field\r
+ flashc_busy_wait();\r
+ AVR32_FLASHC.fcmd = u32Command;\r
+}\r
+\r
+/* Page write\r
+ * Assuming the page address is already loaded\r
+ */\r
+void flashc_page_write(U16 page_n) {\r
+ register U32 u32Command;\r
+ u32Command = X_KEY | AVR32_FLASHC_FCMD_CMD_WP; // key and command\r
+ u32Command |= ((page_n<<AVR32_FLASHC_FCMD_PAGEN_OFFSET) & AVR32_FLASHC_FCMD_PAGEN_MASK); // update page field\r
+ flashc_busy_wait();\r
+ AVR32_FLASHC.fcmd = u32Command;\r
+}\r
+\r
+/* Clear page buffer */\r
+void flashc_clear_page_buffer(void){\r
+ register U32 u32Command;\r
+ u32Command = X_KEY | AVR32_FLASHC_FCMD_CMD_CPB; // key and command clear page buffer\r
+ flashc_busy_wait();\r
+ AVR32_FLASHC.fcmd = u32Command;\r
+}\r
+\r
+/* Page erase\r
+ * Assuming the page address is already loaded\r
+ */\r
+void flashc_erase_page(U16 page_n){\r
+ register U32 u32Command;\r
+ u32Command = X_KEY | AVR32_FLASHC_FCMD_CMD_EP; // key and command,\r
+ u32Command |= ((page_n<<AVR32_FLASHC_FCMD_PAGEN_OFFSET) & AVR32_FLASHC_FCMD_PAGEN_MASK); // update page field\r
+ flashc_busy_wait();\r
+ AVR32_FLASHC.fcmd = u32Command;\r
+}\r
+\r
+/* Erase all Pages */\r
+void flashc_erase_all(void){\r
+ register U32 u32Command;\r
+ u32Command = X_KEY | AVR32_FLASHC_FCMD_CMD_EA; // key and command,\r
+ //u32Command |= ((page_n<<AVR32_FLASHC_FCMD_PAGEN_OFFSET) & AVR32_FLASHC_FCMD_PAGEN_MASK); // update page field\r
+ flashc_busy_wait();\r
+ AVR32_FLASHC.fcmd = u32Command;\r
+ flashc_busy_wait();\r
+}\r
+\r
+/* Erase a page and check if OK with the quick page read command */\r
+int flashc_erase_page_and_check(U16 page_n)\r
+{\r
+ flashc_erase_page(page_n); // erase page page_n first\r
+\r
+ flashc_busy_wait();\r
+\r
+ AVR32_FLASHC.fcmd = X_KEY | ((page_n<<AVR32_FLASHC_PAGEN_OFFSET)&AVR32_FLASHC_PAGEN_MASK) | AVR32_FLASHC_FCMD_CMD_QPR; // qpr on current page number\r
+ while(!((AVR32_FLASHC.fsr & AVR32_FLASHC_FSR_FRDY_MASK)>>AVR32_FLASHC_FSR_FRDY_OFFSET));\r
+\r
+ if (Flashc_is_page_erased() == 0) // check QPRR bit in FCR to have the result of the quick page read\r
+ return FLASHC_FAILURE;\r
+ return FLASHC_SUCCESS;\r
+}\r
+\r
+/*!\r
+ * Page load and write\r
+ * \warning Dest is a FLASH address at a page size boundary\r
+ * (assuming the page is already erased)\r
+ */\r
+void flashc_page_copy_write(U32 *u32dest, const U32 *src) {\r
+ register U32 u32command,pagen;\r
+ flashc_memcpy(u32dest, src, AVR32_FLASHC_PAGE_SIZE / 4); // copy Src to Dest (Dest is a FLASH address at a page boundary)\r
+ pagen = (U32)(((U32)u32dest-AVR32_FLASH_ADDRESS)/AVR32_FLASHC_PAGE_SIZE); // memory page addr\r
+ u32command = X_KEY | ((pagen<<AVR32_FLASHC_PAGEN_OFFSET)&AVR32_FLASHC_PAGEN_MASK) |AVR32_FLASHC_FCMD_CMD_WP; // key and command\r
+ flashc_busy_wait();\r
+ AVR32_FLASHC.fcmd = u32command;\r
+}\r
+\r
+/* Copy data into page buffer */\r
+#if __GNUC__\r
+__attribute__((__always_inline__))\r
+#endif\r
+static __inline__ void flash_fill_temp_buffer(U32 u32Data, U32 u32Address)\r
+{\r
+ *((U32*)u32Address) = u32Data;\r
+}\r
+\r
+/* Read word from flash\r
+ * addr should be 32-bit aligned.\r
+ */\r
+#if __GNUC__\r
+__attribute__((__always_inline__))\r
+#endif\r
+static __inline__ U32 flash_rd_word(U32 const* addr)\r
+{\r
+ return *addr;\r
+}\r
+\r
+/**\r
+ * This function allows to write up to 65535 bytes in the flash memory.\r
+ * This function manages alignement issue (byte and page alignements).\r
+ */\r
+int flash_wr_block(U32 * src, U32 dst, U32 n)\r
+{\r
+ U32 u32NbWord=0;\r
+ U32 u32Temp=0;\r
+ U32 u32SavePageAddr=0;\r
+\r
+ U32 u32Address = dst-(dst%AVR32_FLASHC_PAGE_SIZE); // Compute the start of the page to be modified\r
+\r
+ while(n) // While there is data to load from src buffer\r
+ {\r
+ // u32Address = dst-((dst&0xFFFFffff)%AVR32_FLASHC_PAGE_SIZE); // Compute the start of the page to be modified\r
+ u32SavePageAddr = (u32Address-AVR32_FLASH_ADDRESS)/AVR32_FLASHC_PAGE_SIZE; //memorize page addr\r
+\r
+ // For each word in this page\r
+ for(u32NbWord=0 ; u32NbWord<AVR32_FLASHC_PAGE_SIZE/4 ; u32NbWord++)\r
+ {\r
+ if(n) //Still some data to load from src\r
+ {\r
+ if(u32Address >= dst) //current address is inside the target range adr\r
+ {\r
+ u32Temp = * ((U32*)src); // load word from buffer src\r
+ src++;\r
+ n--;\r
+ }\r
+ else //current word addr out of dst target\r
+ {\r
+ u32Temp = flash_rd_word((U32 const*)u32Address); // load word from existing flash\r
+ }\r
+ }\r
+ else //complete page with words from existing flash\r
+ {\r
+ u32Temp = flash_rd_word((U32 const*)u32Address);\r
+ }\r
+ flash_fill_temp_buffer(u32Temp, u32Address); // fill page buffer\r
+ u32Address+=4; // one more word for u32Address\r
+ }\r
+\r
+ // u32Address = u32SavePageAddr*AVR32_FLASHC_PAGE_SIZE+AVR32_FLASH_ADDRESS;\r
+\r
+ /*\r
+ // Done with QPR\r
+ for(u32NbWord=0 ; u32NbWord<AVR32_FLASHC_PAGE_SIZE/4 ; u32NbWord++)\r
+ {\r
+ if(flash_rd_word((U32 farcode*)u32Address)!=0xFFFFffff) // check if the page is erased\r
+ {\r
+ Flash_page_erase(u32SavePageAddr);\r
+ break;\r
+ }\r
+ u32Address+=4;\r
+ }\r
+ */\r
+\r
+ // Check if page is erased\r
+ AVR32_FLASHC.fcmd = X_KEY | ((u32SavePageAddr<<AVR32_FLASHC_PAGEN_OFFSET)&AVR32_FLASHC_PAGEN_MASK) | AVR32_FLASHC_CMD_QPR; // qpr on current page number\r
+ while(!((AVR32_FLASHC.fsr & AVR32_FLASHC_FSR_FRDY_MASK)>>AVR32_FLASHC_FSR_FRDY_OFFSET));\r
+\r
+ if ( (AVR32_FLASHC.fsr & AVR32_FLASHC_FSR_QPRR_MASK)>> AVR32_FLASHC_FSR_QPRR_OFFSET == 0 ) // test QPR bit in FSR\r
+ { // erase page\r
+ AVR32_FLASHC.fcmd = X_KEY | ((u32SavePageAddr<<AVR32_FLASHC_PAGEN_OFFSET)&AVR32_FLASHC_PAGEN_MASK) | AVR32_FLASHC_FCMD_CMD_EP; //page n erase cmd\r
+ while(!((AVR32_FLASHC.fsr & AVR32_FLASHC_FSR_FRDY_MASK)>>AVR32_FLASHC_FSR_FRDY_OFFSET));\r
+ }\r
+\r
+ flashc_page_write_n(u32SavePageAddr); // write the corresponding page number\r
+ flashc_clear_page_buffer();\r
+ } // end while (n)\r
+ return FLASHC_SUCCESS;\r
+}\r
+\r
+/* Erase all flash with pages access */\r
+void flash_erase(void)\r
+{\r
+ U32 u32NbPage = flashc_get_page_count();\r
+ while (u32NbPage) flashc_erase_page(--u32NbPage);\r
+}\r
--- /dev/null
+/* This header file is part of the ATMEL FREERTOS-0.9.0 Release */\r
+\r
+/*This file has been prepared for Doxygen automatic documentation generation.*/\r
+/*! \file *********************************************************************\r
+ *\r
+ * \brief Flash Controller driver .h file.\r
+ *\r
+ * This file defines a useful set of functions for the flash controller\r
+ * on AVR32A devices.\r
+ *\r
+ * - Compiler: IAR EWAVR32 and GNU GCC for AVR32\r
+ * - Supported devices: All AVR32A devices.\r
+ *\r
+ * \author Atmel Corporation: http://www.atmel.com \n\r
+ * Support email: avr32@atmel.com\r
+ *\r
+ *****************************************************************************/\r
+\r
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of ATMEL may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND\r
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,\r
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\r
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\r
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF\r
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ */\r
+\r
+\r
+#ifndef _FLASHC_H_\r
+#define _FLASHC_H_\r
+\r
+#if __GNUC__\r
+# include <avr32/io.h>\r
+#elif __ICCAVR32__\r
+# include <avr32/iouc3a0512.h>\r
+# include <avr32/uc3a0512.h>\r
+#else\r
+# error Unknown compiler\r
+#endif\r
+\r
+#include "compiler.h"\r
+\r
+\r
+/*! Value returned by function when it completed successfully */\r
+#define FLASHC_SUCCESS 0\r
+\r
+/*! Value returned by function when it was unable to complete successfully\r
+ for some unspecified reason */\r
+#define FLASHC_FAILURE -1\r
+\r
+/*! Value returned by function when the input paramters are out of range */\r
+#define FLASHC_INVALID_INPUT 1\r
+\r
+\r
+/*! Get Flash size */\r
+#if __GNUC__\r
+__attribute__((__always_inline__))\r
+#endif\r
+extern __inline__ unsigned int flashc_get_flash_size(void)\r
+{\r
+ static const unsigned int FLASHC_SIZE[1 << AVR32_FLASHC_FSR_FSZ_SIZE] =\r
+ {\r
+ 32 << 10,\r
+ 64 << 10,\r
+ 128 << 10,\r
+ 256 << 10,\r
+ 384 << 10,\r
+ 512 << 10,\r
+ 768 << 10,\r
+ 1024 << 10\r
+ };\r
+\r
+ return FLASHC_SIZE[Rd_bitfield(AVR32_FLASHC.fsr, AVR32_FLASHC_FSR_FSZ_MASK)];\r
+}\r
+\r
+/*! Get Flash page count */\r
+#if __GNUC__\r
+__attribute__((__always_inline__))\r
+#endif\r
+extern __inline__ unsigned int flashc_get_page_count(void)\r
+{\r
+ return flashc_get_flash_size() / AVR32_FLASHC_PAGE_SIZE;\r
+}\r
+\r
+/*! Get Flash page count per region */\r
+#if __GNUC__\r
+__attribute__((__always_inline__))\r
+#endif\r
+extern __inline__ unsigned int flashc_get_page_count_per_region(void)\r
+{\r
+ return flashc_get_page_count() / 16;\r
+}\r
+\r
+/*! Wait flash ready status, the application must wait before running a new command.\r
+ * Warning: Flash status register (FCR) is read, and error status may be automatically\r
+ * cleared when reading FCR.\r
+ */\r
+#if __GNUC__\r
+__attribute__((__always_inline__))\r
+#endif\r
+extern __inline__ void flashc_busy_wait(void)\r
+{\r
+ while (!Tst_bits(AVR32_FLASHC.fsr, AVR32_FLASHC_FSR_FRDY_MASK));\r
+}\r
+\r
+/*! Check if security bit is active.\r
+ * \warning: Flash status register (FCR) is read, and error status may be automatically\r
+ * cleared when reading FCR.\r
+ */\r
+#if __GNUC__\r
+__attribute__((__always_inline__))\r
+#endif\r
+extern __inline__ Bool flashc_is_security_active(void)\r
+{\r
+ return Tst_bits(AVR32_FLASHC.fsr, AVR32_FLASHC_FSR_SECURITY_MASK);\r
+}\r
+\r
+/*! \brief Memcopy function\r
+ * \param *s1 destination\r
+ * \param *s2 source\r
+ * \param n number of words to copy\r
+ */\r
+extern U32 *flashc_memcpy(U32 *s1, const U32 *s2, const U32 n);\r
+\r
+/*! \brief Set number of wait state\r
+ * \param ws 0 if for no-wait state, for 1 wait-state\r
+ * \return FLASHC_SUCCESS, FLASHC_INVALID_INPUT or FLASHC_FAILURE\r
+ */\r
+extern int flashc_set_wait_state(U16 ws);\r
+\r
+/*! \brief Page write number n. Assuming page bubuffer is already loaded.\r
+ * \param n Page number\r
+ */\r
+extern void flashc_page_write_n(U16 n);\r
+\r
+/*! \brief Page write\r
+ * Assuming the page address is already loaded\r
+ */\r
+extern void flashc_page_write(U16 page_n);\r
+\r
+/*! \brief Clear page buffer\r
+ */\r
+extern void flashc_clear_page_buffer(void);\r
+\r
+/*! \brief Page erase\r
+ * Assuming the page address is already loaded\r
+ */\r
+extern void flashc_erase_page(U16 page_n);\r
+\r
+/*! \brief Erase all Pages\r
+ */\r
+extern void flashc_erase_all(void);\r
+\r
+/*! \brief Erase a page and check if erase is OK\r
+ */\r
+extern int flashc_erase_page_and_check(U16 page_n);\r
+\r
+/*! \brief Page load and write\r
+ * \warning Dest is a FLASH address at a page boundary\r
+ * (assuming the page is already erased)\r
+ */\r
+extern void flashc_page_copy_write(U32 *Dest, const U32 *Src) ;\r
+\r
+/*! \brief This function allows to write up to 65535 bytes in the flash memory.\r
+ * This function manages alignement issue (byte and page alignements).\r
+ *\r
+ * \param *src Address of data to write.\r
+ * \param dst Start address in flash memory where write data\r
+ * \param n Number of word to write\r
+ * \return FLASHC_SUCCESS or FLASHC_FAILURE\r
+ */\r
+extern int flash_wr_block(U32 * src, U32 dst, U32 n);\r
+\r
+\r
+#endif /* #ifndef _FLASHC_H_*/\r
--- /dev/null
+/* This source file is part of the ATMEL FREERTOS-0.9.0 Release */\r
+\r
+/*This file has been prepared for Doxygen automatic documentation generation.*/\r
+/*! \file *********************************************************************\r
+ *\r
+ * \brief GPIO driver for AVR32 UC3.\r
+ *\r
+ * This file defines a useful set of functions for the GPIO.\r
+ *\r
+ * - Compiler: IAR EWAVR32 and GNU GCC for AVR32\r
+ * - Supported devices: All AVR32 devices with a PWM module can be used.\r
+ * - AppNote:\r
+ *\r
+ * \author Atmel Corporation: http://www.atmel.com \n\r
+ * Support email: avr32@atmel.com\r
+ *\r
+ *****************************************************************************/\r
+\r
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of ATMEL may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND\r
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,\r
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\r
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\r
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF\r
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ */\r
+\r
+\r
+#include "gpio.h"\r
+\r
+\r
+//! GPIO module instance.\r
+#define GPIO AVR32_GPIO\r
+\r
+\r
+int gpio_enable_module(avr32_gpiomap_t gpiomap, int size)\r
+{\r
+ int i,status=GPIO_SUCCESS;\r
+\r
+ for(i=0; i<size; i++) {\r
+ status |= gpio_enable_module_pin(**gpiomap, *(*gpiomap+1) );\r
+ gpiomap++;\r
+ }\r
+\r
+ return status;\r
+}\r
+\r
+\r
+int gpio_enable_module_pin(int pin, int function)\r
+{\r
+ volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin/32];\r
+\r
+ // Enable the correct function\r
+ switch(function)\r
+ {\r
+ case 0: // A function\r
+ gpio_port->pmr0c = (1<<(pin%32));\r
+ gpio_port->pmr1c = (1<<(pin%32));\r
+ break;\r
+ case 1: // B function\r
+ gpio_port->pmr0s = (1<<(pin%32));\r
+ gpio_port->pmr1c = (1<<(pin%32));\r
+ break;\r
+ case 2: // C function\r
+ gpio_port->pmr0c = (1<<(pin%32));\r
+ gpio_port->pmr1s = (1<<(pin%32));\r
+ break;\r
+ default:\r
+ return GPIO_INVALID_ARGUMENT;\r
+ }\r
+\r
+ // Disable gpio control\r
+ gpio_port->gperc = (1<<(pin%32));\r
+\r
+ return GPIO_SUCCESS;\r
+}\r
+\r
+\r
+void gpio_enable_gpio(avr32_gpiomap_t gpiomap, int size)\r
+{\r
+ int i;\r
+\r
+ for(i=0; i<size; i++){\r
+ gpio_enable_gpio_pin(**gpiomap);\r
+ gpiomap++;\r
+ }\r
+}\r
+\r
+\r
+void gpio_enable_gpio_pin(int pin)\r
+{\r
+ volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin/32];\r
+ gpio_port->gpers = 1<<(pin%32);\r
+}\r
+\r
+\r
+void gpio_enable_gpio_glitch_filter(int pin)\r
+{\r
+ volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin/32];\r
+ gpio_port->gfers = 1<<(pin%32);\r
+}\r
+\r
+\r
+void gpio_disable_gpio_glitch_filter(int pin)\r
+{\r
+ volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin/32];\r
+ gpio_port->gferc = 1<<(pin%32);\r
+}\r
+\r
+\r
+void gpio_disable_module(avr32_gpiomap_t gpiomap, int size)\r
+{\r
+ int i;\r
+\r
+ for(i=0; i<size; i++){\r
+ gpio_disable_gpio_pin(**gpiomap);\r
+ gpiomap++;\r
+ }\r
+}\r
+\r
+\r
+void gpio_disable_gpio_pin(int pin)\r
+{\r
+ volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin/32];\r
+ gpio_port->gperc = 1<<(pin%32);\r
+}\r
+\r
+\r
+int gpio_pin_value(int pin)\r
+{\r
+ volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin/32];\r
+ return (gpio_port->pvr >>(pin%32))&1;\r
+}\r
+\r
+\r
+void gpio_set_gpio_pin(int pin)\r
+{\r
+ // The port holding that pin.\r
+ volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin/32];\r
+\r
+ gpio_port->ovrs = (1<<(pin%32)); // Value to be driven on the I/O line: 1\r
+ gpio_port->oders = (1<<(pin%32)); // The GPIO output driver is enabled for that pin.\r
+ gpio_port->gpers = (1<<(pin%32)); // The GPIO module controls that pin.\r
+}\r
+\r
+\r
+void gpio_clr_gpio_pin(int pin)\r
+{\r
+ volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin/32]; // The port holding that pin.\r
+\r
+ gpio_port->ovrc = (1<<(pin%32)); // Value to be driven on the I/O line: 0\r
+ gpio_port->oders = (1<<(pin%32)); // The GPIO output driver is enabled for that pin.\r
+ gpio_port->gpers = (1<<(pin%32)); // The GPIO module controls that pin.\r
+}\r
+\r
+\r
+void gpio_tgl_gpio_pin(int pin)\r
+{\r
+ volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin/32]; // The port holding that pin.\r
+\r
+ gpio_port->ovrt = (1<<(pin%32)); // Toggle the I/O line.\r
+ gpio_port->oders = (1<<(pin%32)); // The GPIO output driver is enabled for that pin.\r
+ gpio_port->gpers = (1<<(pin%32)); // The GPIO module controls that pin.\r
+}\r
+\r
+\r
+void gpio_cfg_int_gpio_pin(int pin, int level)\r
+{\r
+ volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin/32]; // The port holding that pin.\r
+\r
+ gpio_port->gpers = 1<<(pin%32); // GPIO controller enable\r
+ gpio_port->gfers = 1<<(pin%32); // GPIO glitch filter enable\r
+ switch (level)\r
+ {\r
+ case GPIO_RISING_EDGE:\r
+ {\r
+ // mode rising edge\r
+ gpio_port->imr0s = 1<<(pin%32);\r
+ gpio_port->imr1c = 1<<(pin%32);\r
+ break;\r
+ }\r
+ case GPIO_FALLING_EDGE:\r
+ {\r
+ // mode falling edge\r
+ gpio_port->imr0c = 1<<(pin%32);\r
+ gpio_port->imr1s = 1<<(pin%32);\r
+ break;\r
+ }\r
+ default :\r
+ {\r
+ // mode pin change\r
+ gpio_port->imr0c = 1<<(pin%32);\r
+ gpio_port->imr1c = 1<<(pin%32);\r
+ break;\r
+ }\r
+ }\r
+ gpio_port->iers = 1<<(pin%32); // GPIO interrupt enable\r
+}\r
--- /dev/null
+/* This header file is part of the ATMEL FREERTOS-0.9.0 Release */\r
+\r
+/*This file has been prepared for Doxygen automatic documentation generation.*/\r
+/*! \file *********************************************************************\r
+ *\r
+ * \brief GPIO header for AVR32 UC3.\r
+ *\r
+ * This file contains basic GPIO driver functions.\r
+ *\r
+ * - Compiler: IAR EWAVR32 and GNU GCC for AVR32\r
+ * - Supported devices: All AVR32 devices with a GPIO module can be used.\r
+ * - AppNote:\r
+ *\r
+ * \author Atmel Corporation: http://www.atmel.com \n\r
+ * Support email: avr32@atmel.com\r
+ *\r
+ *****************************************************************************/\r
+\r
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of ATMEL may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND\r
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,\r
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\r
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\r
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF\r
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ */\r
+\r
+\r
+#ifndef _GPIO_H_\r
+#define _GPIO_H_\r
+\r
+#if __GNUC__\r
+# include <avr32/io.h>\r
+#elif __ICCAVR32__\r
+# include <avr32/iouc3a0512.h>\r
+#else\r
+# error Unknown compiler\r
+#endif\r
+\r
+\r
+/*! \name General GPIO API defines\r
+ * These values are returned by the GPIO API:\r
+ */\r
+//! @{\r
+#define GPIO_SUCCESS 0 //!< Function successfully completed\r
+#define GPIO_FAILURE -1 //!< Function did not successfully complete for some unspecified reason\r
+#define GPIO_INVALID_ARGUMENT 1 //!< Input paramters are out of range\r
+//! @}\r
+\r
+\r
+/*! \name Interrupt configuration defines\r
+ * Configure the method used to trigger the interrupt:\r
+ */\r
+//! @{\r
+#define GPIO_RISING_EDGE 1 //!< configure IT upon Rising Edge\r
+#define GPIO_FALLING_EDGE 2 //!< configure IT upon Falling Edge\r
+#define GPIO_INPUT_CHANGE 3 //!< configure IT upon Pin Change\r
+//! @}\r
+\r
+\r
+/*!\r
+ * A type definitions of pins and module connectivity.\r
+ * First column is the pin number, the second is gpio connectivity.\r
+ */\r
+typedef char avr32_gpiomap_t[][2];\r
+\r
+\r
+/*!\r
+ * \brief Enable a module pin for a given set of pins and respective modules.\r
+ *\r
+ * \param gpiomap A list of pins and pio connectivity\r
+ * \param size The number of pins in \a gpiomap\r
+ * \return \ref GPIO_SUCCESS or \ref GPIO_INVALID_ARGUMENT\r
+ */\r
+extern int gpio_enable_module(avr32_gpiomap_t gpiomap, int size);\r
+\r
+/*!\r
+ * \brief Enable a special module (function) for a pin (pin number).\r
+ *\r
+ * \param pin The pin number\r
+ * \param function The pin function\r
+ * \return \ref GPIO_SUCCESS or \ref GPIO_INVALID_ARGUMENT\r
+ */\r
+extern int gpio_enable_module_pin(int pin, int function);\r
+\r
+/*!\r
+ * \brief Enable pins of a module according gpiomap.\r
+ *\r
+ * \param gpiomap The pin map\r
+ * \param size The number of pins in \a gpiomap\r
+ */\r
+extern void gpio_enable_gpio(avr32_gpiomap_t gpiomap, int size);\r
+\r
+/*!\r
+ * \brief Enable the GPIO module to control the pin.\r
+ *\r
+ * \param pin The pin number\r
+ */\r
+extern void gpio_enable_gpio_pin(int pin);\r
+\r
+/*!\r
+ * \brief Enable the GPIO glitch filter.\r
+ *\r
+ * When the glitch filter is enabled, a\r
+ * glitch with duration of less than 1 clock cycle is automatically rejected, while a pulse with duration\r
+ * of 2 clock cycles or more is accepted. For pulse durations between 1 clock cycle and 2 clock\r
+ * cycles, the pulse may or may not be taken into account, depending on the precise timing of its\r
+ * occurrence. Thus for a pulse to be guaranteed visible it must exceed 2 clock cycles, whereas for\r
+ * a glitch to be reliably filtered out, its duration must not exceed 1 clock cycle. The filter introduces\r
+ * 2 clock cycles latency.\r
+ *\r
+ * \param pin The pin number\r
+ * \return \ref GPIO_SUCCESS\r
+ */\r
+extern void gpio_enable_gpio_glitch_filter(int pin);\r
+\r
+/*!\r
+ * \brief Disable the GPIO glitch filter.\r
+ *\r
+ * \param pin The pin number\r
+ */\r
+extern void gpio_disable_gpio_glitch_filter(int pin);\r
+\r
+/*!\r
+ * \brief Return the pin value\r
+ *\r
+ * \param pin The pin number\r
+ * \return pin value\r
+ */\r
+extern int gpio_pin_value(int pin);\r
+\r
+/*!\r
+ * \brief Disable the GPIO module to control a set of pins according to gpiomap.\r
+ *\r
+ * \param gpiomap The pin map\r
+ * \param size The number of pins in \a gpiomap\r
+ */\r
+extern void gpio_disable_module(avr32_gpiomap_t gpiomap, int size);\r
+\r
+/*!\r
+ * \brief Disable the GPIO module to control the pin.\r
+ *\r
+ * \param pin The pin number\r
+ */\r
+extern void gpio_disable_gpio_pin(int pin);\r
+\r
+/*!\r
+ * \brief Configure a pin to generate IT\r
+ *\r
+ * \param pin GPIO pin number to configure.\r
+ * \param level level to configure (\ref GPIO_RISING_EDGE, \ref GPIO_FALLING_EDGE, \ref GPIO_INPUT_CHANGE).\r
+ */\r
+extern void gpio_cfg_int_gpio_pin(int pin, int level);\r
+\r
+/*!\r
+ * \brief Drive a gpio pin value to 1.\r
+ *\r
+ * \param pin The pin number\r
+ */\r
+extern void gpio_set_gpio_pin(int pin);\r
+\r
+/*!\r
+ * \brief Drive a gpio pin value to 0.\r
+ *\r
+ * \param pin The pin number\r
+ */\r
+extern void gpio_clr_gpio_pin(int pin);\r
+\r
+/*!\r
+ * \brief This function toggle a gpio pin value.\r
+ *\r
+ * \param pin The pin number\r
+ */\r
+extern void gpio_tgl_gpio_pin(int pin);\r
+\r
+\r
+#endif // _GPIO_H_\r
--- /dev/null
+/*This file is prepared for Doxygen automatic documentation generation.*/\r
+/*! \file *********************************************************************\r
+ *\r
+ * \brief INTC driver for AVR32 UC3.\r
+ *\r
+ * AVR32 Interrupt Controller driver module.\r
+ *\r
+ * - Compiler: IAR EWAVR32 and GNU GCC for AVR32\r
+ * - Supported devices: All AVR32 devices with an INTC module can be used.\r
+ * - AppNote:\r
+ *\r
+ * \author Atmel Corporation: http://www.atmel.com \n\r
+ * Support email: avr32@atmel.com\r
+ *\r
+ ******************************************************************************/\r
+\r
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of ATMEL may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND\r
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,\r
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\r
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\r
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF\r
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ */\r
+\r
+\r
+#if __GNUC__\r
+# include <avr32/io.h>\r
+#elif __ICCAVR32__\r
+# include <avr32/iouc3a0512.h>\r
+#else\r
+# error Unknown compiler\r
+#endif\r
+\r
+#include "compiler.h"\r
+#include "preprocessor.h"\r
+#include "intc.h"\r
+\r
+\r
+//! Values to store in the interrupt priority registers for the various interrupt priority levels.\r
+extern const unsigned int ipr_val[AVR32_INTC_NUM_INT_LEVELS];\r
+\r
+//! Creates a table of interrupt line handlers per interrupt group in order to optimize RAM space.\r
+//! Each line handler table contains a set of pointers to interrupt handlers.\r
+#define DECL_INT_LINE_HANDLER_TABLE(GRP, unused) \\r
+static volatile __int_handler _int_line_handler_table_##GRP[AVR32_INTC_NUM_IRQS_PER_GRP##GRP];\r
+MREPEAT(AVR32_INTC_NUM_INT_GRPS, DECL_INT_LINE_HANDLER_TABLE, ~);\r
+#undef DECL_INT_LINE_HANDLER_TABLE\r
+\r
+//! Table containing for each interrupt group the number of interrupt request\r
+//! lines and a pointer to the table of interrupt line handlers.\r
+static const struct\r
+{\r
+ unsigned int num_irqs;\r
+ volatile __int_handler *_int_line_handler_table;\r
+} _int_handler_table[AVR32_INTC_NUM_INT_GRPS] =\r
+{\r
+#define INSERT_INT_LINE_HANDLER_TABLE(GRP, unused) \\r
+ {AVR32_INTC_NUM_IRQS_PER_GRP##GRP, _int_line_handler_table_##GRP},\r
+ MREPEAT(AVR32_INTC_NUM_INT_GRPS, INSERT_INT_LINE_HANDLER_TABLE, ~)\r
+#undef INSERT_INT_LINE_HANDLER_TABLE\r
+};\r
+\r
+\r
+/*! \brief Default interrupt handler.\r
+ *\r
+ * \note Taken and adapted from Newlib.\r
+ */\r
+#if __GNUC__\r
+__attribute__((__interrupt__))\r
+#elif __ICCAVR32__\r
+__interrupt\r
+#endif\r
+static void _unhandled_interrupt(void)\r
+{\r
+ // Catch unregistered interrupts.\r
+ while (TRUE);\r
+}\r
+\r
+\r
+/*! \brief Gets the interrupt handler of the current event at the \a int_lev\r
+ * interrupt priority level (called from exception.S).\r
+ *\r
+ * \param int_lev Interrupt priority level to handle.\r
+ *\r
+ * \return Interrupt handler to execute.\r
+ *\r
+ * \note Taken and adapted from Newlib.\r
+ */\r
+__int_handler _get_interrupt_handler(unsigned int int_lev)\r
+{\r
+ // ICR3 is mapped first, ICR0 last.\r
+ // Code in exception.S puts int_lev in R12 which is used by AVR32-GCC to pass\r
+ // a single argument to a function.\r
+ unsigned int int_grp = (&AVR32_INTC.icr3)[INT3 - int_lev];\r
+ unsigned int int_req = AVR32_INTC.irr[int_grp];\r
+\r
+ // As an interrupt may disappear while it is being fetched by the CPU\r
+ // (spurious interrupt caused by a delayed response from an MCU peripheral to\r
+ // an interrupt flag clear or interrupt disable instruction), check if there\r
+ // are remaining interrupt lines to process.\r
+ // If a spurious interrupt occurs, the status register (SR) contains an\r
+ // execution mode and interrupt level masks corresponding to a level 0\r
+ // interrupt, whatever the interrupt priority level causing the spurious\r
+ // event. This behavior has been chosen because a spurious interrupt has not\r
+ // to be a priority one and because it may not cause any trouble to other\r
+ // interrupts.\r
+ // However, these spurious interrupts place the hardware in an unstable state\r
+ // and could give problems in other/future versions of the CPU, so the\r
+ // software has to be written so that they never occur. The only safe way of\r
+ // achieving this is to always clear or disable peripheral interrupts with the\r
+ // following sequence:\r
+ // 1: Mask the interrupt in the CPU by setting GM (or IxM) in SR.\r
+ // 2: Perform the bus access to the peripheral register that clears or\r
+ // disables the interrupt.\r
+ // 3: Wait until the interrupt has actually been cleared or disabled by the\r
+ // peripheral. This is usually performed by reading from a register in the\r
+ // same peripheral (it DOES NOT have to be the same register that was\r
+ // accessed in step 2, but it MUST be in the same peripheral), what takes\r
+ // bus system latencies into account, but peripheral internal latencies\r
+ // (generally 0 cycle) also have to be considered.\r
+ // 4: Unmask the interrupt in the CPU by clearing GM (or IxM) in SR.\r
+ // Note that steps 1 and 4 are useless inside interrupt handlers as the\r
+ // corresponding interrupt level is automatically masked by IxM (unless IxM is\r
+ // explicitly cleared by the software).\r
+ //\r
+ // Get the right IRQ handler.\r
+ //\r
+ // If several interrupt lines are active in the group, the interrupt line with\r
+ // the highest number is selected. This is to be coherent with the\r
+ // prioritization of interrupt groups performed by the hardware interrupt\r
+ // controller.\r
+ //\r
+ // If no handler has been registered for the pending interrupt,\r
+ // _unhandled_interrupt will be selected thanks to the initialization of\r
+ // _int_line_handler_table_x by INTC_init_interrupts.\r
+ //\r
+ // exception.S will provide the interrupt handler with a clean interrupt stack\r
+ // frame, with nothing more pushed onto the stack. The interrupt handler must\r
+ // manage the `rete' instruction, what can be done thanks to pure assembly,\r
+ // inline assembly or the `__attribute__((__interrupt__))' C function\r
+ // attribute.\r
+ return (int_req) ? _int_handler_table[int_grp]._int_line_handler_table[32 - clz(int_req) - 1] : NULL;\r
+}\r
+\r
+\r
+void INTC_init_interrupts(void)\r
+{\r
+ unsigned int int_grp, int_req;\r
+\r
+ // For all interrupt groups,\r
+ for (int_grp = 0; int_grp < AVR32_INTC_NUM_INT_GRPS; int_grp++)\r
+ {\r
+ // For all interrupt request lines of each group,\r
+ for (int_req = 0; int_req < _int_handler_table[int_grp].num_irqs; int_req++)\r
+ {\r
+ // Assign _unhandled_interrupt as default interrupt handler.\r
+ _int_handler_table[int_grp]._int_line_handler_table[int_req] = &_unhandled_interrupt;\r
+ }\r
+\r
+ // Set the interrupt group priority register to its default value.\r
+ // By default, all interrupt groups are linked to the interrupt priority\r
+ // level 0 and to the interrupt vector _int0.\r
+ AVR32_INTC.ipr[int_grp] = ipr_val[INT0];\r
+ }\r
+}\r
+\r
+\r
+void INTC_register_interrupt(__int_handler handler, unsigned int irq, unsigned int int_lev)\r
+{\r
+ unsigned int int_grp = irq / AVR32_INTC_MAX_NUM_IRQS_PER_GRP;\r
+\r
+ // Store in _int_line_handler_table_x the pointer to the interrupt handler, so\r
+ // that _get_interrupt_handler can retrieve it when the interrupt is vectored.\r
+ _int_handler_table[int_grp]._int_line_handler_table[irq % AVR32_INTC_MAX_NUM_IRQS_PER_GRP] = handler;\r
+\r
+ // Program the corresponding IPRX register to set the interrupt priority level\r
+ // and the interrupt vector offset that will be fetched by the core interrupt\r
+ // system.\r
+ // NOTE: The _intx functions are intermediate assembly functions between the\r
+ // core interrupt system and the user interrupt handler.\r
+ AVR32_INTC.ipr[int_grp] = ipr_val[int_lev & (AVR32_INTC_IPR0_INTLEV_MASK >> AVR32_INTC_IPR0_INTLEV_OFFSET)];\r
+}\r
--- /dev/null
+/*This file is prepared for Doxygen automatic documentation generation.*/\r
+/*! \file *********************************************************************\r
+ *\r
+ * \brief INTC driver for AVR32 UC3.\r
+ *\r
+ * AVR32 Interrupt Controller driver module.\r
+ *\r
+ * - Compiler: IAR EWAVR32 and GNU GCC for AVR32\r
+ * - Supported devices: All AVR32 devices with an INTC module can be used.\r
+ * - AppNote:\r
+ *\r
+ * \author Atmel Corporation: http://www.atmel.com \n\r
+ * Support email: avr32@atmel.com\r
+ *\r
+ ******************************************************************************/\r
+\r
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of ATMEL may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND\r
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,\r
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\r
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\r
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF\r
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ */\r
+\r
+\r
+#ifndef _INTC_H_\r
+#define _INTC_H_\r
+\r
+#include "compiler.h"\r
+\r
+\r
+//! Maximal number of interrupt request lines per group.\r
+#define AVR32_INTC_MAX_NUM_IRQS_PER_GRP 32\r
+\r
+//! Number of interrupt priority levels.\r
+#define AVR32_INTC_NUM_INT_LEVELS (1 << AVR32_INTC_IPR0_INTLEV_SIZE)\r
+\r
+/*! \name Interrupt Priority Levels\r
+ */\r
+//! @{\r
+#define INT0 0 //!< Lowest interrupt priority level.\r
+#define INT1 1\r
+#define INT2 2\r
+#define INT3 3 //!< Highest interrupt priority level.\r
+//! @}\r
+\r
+\r
+#ifdef __AVR32_ABI_COMPILER__ // Automatically defined when compiling for AVR32, not when assembling.\r
+\r
+//! Pointer to interrupt handler.\r
+#if __GNUC__\r
+typedef void (*__int_handler)(void);\r
+#elif __ICCAVR32__\r
+typedef void (__interrupt *__int_handler)(void);\r
+#endif\r
+\r
+\r
+/*! \brief Initializes the hardware interrupt controller driver.\r
+ *\r
+ * \note Taken and adapted from Newlib.\r
+ */\r
+extern void INTC_init_interrupts(void);\r
+\r
+/*! \brief Registers an interrupt handler.\r
+ *\r
+ * \param handler Interrupt handler to register.\r
+ * \param irq IRQ of the interrupt handler to register.\r
+ * \param int_lev Interrupt priority level to assign to the group of this IRQ.\r
+ *\r
+ * \warning The interrupt handler must manage the `rete' instruction, what can\r
+ * be done thanks to pure assembly, inline assembly or the\r
+ * `__attribute__((__interrupt__))' C function attribute.\r
+ *\r
+ * \warning If several interrupt handlers of a same group are registered with\r
+ * different priority levels, only the latest priority level set will\r
+ * be effective.\r
+ *\r
+ * \note Taken and adapted from Newlib.\r
+ */\r
+extern void INTC_register_interrupt(__int_handler handler, unsigned int irq, unsigned int int_lev);\r
+\r
+#endif // __AVR32_ABI_COMPILER__\r
+\r
+\r
+#endif // _INTC_H_\r
--- /dev/null
+/*This file has been prepared for Doxygen automatic documentation generation.*/\r
+/*! \file *********************************************************************\r
+ *\r
+ * \brief Power Manager driver.\r
+ *\r
+ *\r
+ * - Compiler: IAR EWAVR32 and GNU GCC for AVR32\r
+ * - Supported devices: All AVR32 devices.\r
+ * - AppNote:\r
+ *\r
+ * \author Atmel Corporation: http://www.atmel.com \n\r
+ * Support email: avr32@atmel.com\r
+ *\r
+ *****************************************************************************/\r
+\r
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of ATMEL may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND\r
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,\r
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\r
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\r
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF\r
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ */\r
+\r
+\r
+#include "pm.h"\r
+\r
+\r
+void pm_enable_osc0_ext_clock(volatile avr32_pm_t *pm)\r
+{\r
+ union {\r
+ unsigned long oscctrl0;\r
+ avr32_pm_oscctrl0_t OSCCTRL0;\r
+ } oscctrl0 ;\r
+ // Read\r
+ oscctrl0.oscctrl0 = pm->oscctrl0;\r
+ // Modify\r
+ oscctrl0.OSCCTRL0.mode = AVR32_PM_OSCCTRL0_MODE_EXT_CLOCK;\r
+ // Write\r
+ pm->oscctrl0 = oscctrl0.oscctrl0;\r
+}\r
+\r
+\r
+void pm_enable_osc0_crystal(volatile avr32_pm_t *pm, unsigned int fosc0)\r
+{\r
+ union {\r
+ unsigned long oscctrl0;\r
+ avr32_pm_oscctrl0_t OSCCTRL0;\r
+ } oscctrl0 ;\r
+ // Read\r
+ oscctrl0.oscctrl0 = pm->oscctrl0;\r
+ // Modify\r
+ oscctrl0.OSCCTRL0.mode = (fosc0 < 8000000) ? AVR32_PM_OSCCTRL0_MODE_CRYSTAL_G2 :\r
+ AVR32_PM_OSCCTRL0_MODE_CRYSTAL_G3;\r
+ // Write\r
+ pm->oscctrl0 = oscctrl0.oscctrl0;\r
+}\r
+\r
+\r
+void pm_enable_clk0(volatile avr32_pm_t *pm, unsigned int startup)\r
+{\r
+ union {\r
+ avr32_pm_mcctrl_t MCCTRL;\r
+ unsigned long mcctrl;\r
+ } mcctrl;\r
+ union {\r
+ unsigned long oscctrl0;\r
+ avr32_pm_oscctrl0_t OSCCTRL0;\r
+ } oscctrl0 ;\r
+\r
+ // Read register\r
+ mcctrl.mcctrl = pm->mcctrl;\r
+ oscctrl0.oscctrl0 = pm->oscctrl0;\r
+ // Modify\r
+ mcctrl.MCCTRL.osc0en = 1;\r
+ oscctrl0.OSCCTRL0.startup = startup;\r
+ // Write back\r
+ pm->oscctrl0 = oscctrl0.oscctrl0;\r
+ pm->mcctrl = mcctrl.mcctrl;\r
+\r
+ while(!pm->ISR.osc0rdy); //For osc output valid\r
+}\r
+\r
+\r
+void pm_disable_clk0(volatile avr32_pm_t *pm)\r
+{\r
+ union {\r
+ avr32_pm_mcctrl_t MCCTRL;\r
+ unsigned long mcctrl;\r
+ } mcctrl;\r
+\r
+ // Read register\r
+ mcctrl.mcctrl = pm->mcctrl;\r
+\r
+ // Modify\r
+ mcctrl.MCCTRL.osc0en = 0;\r
+\r
+ // Write back\r
+ pm->mcctrl = mcctrl.mcctrl;\r
+}\r
+\r
+\r
+void pm_enable_clk0_no_wait(volatile avr32_pm_t *pm, unsigned int startup)\r
+{\r
+ union {\r
+ avr32_pm_mcctrl_t MCCTRL;\r
+ unsigned long mcctrl;\r
+ } mcctrl;\r
+ union {\r
+ unsigned long oscctrl0;\r
+ avr32_pm_oscctrl0_t OSCCTRL0;\r
+ } oscctrl0 ;\r
+\r
+ // Read register\r
+ mcctrl.mcctrl = pm->mcctrl;\r
+ oscctrl0.oscctrl0 = pm->oscctrl0;\r
+ // Modify\r
+ mcctrl.MCCTRL.osc0en = 1;\r
+ oscctrl0.OSCCTRL0.startup=startup;\r
+ // Write back\r
+ pm->mcctrl = mcctrl.mcctrl;\r
+ pm->oscctrl0 = oscctrl0.oscctrl0;\r
+}\r
+\r
+\r
+void pm_wait_for_clk0_ready(volatile avr32_pm_t *pm)\r
+{\r
+ while(!pm->ISR.osc0rdy);\r
+}\r
+\r
+\r
+void pm_enable_osc1_ext_clock(volatile avr32_pm_t *pm)\r
+{\r
+ union {\r
+ unsigned long oscctrl1;\r
+ avr32_pm_oscctrl1_t OSCCTRL1;\r
+ } oscctrl1 ;\r
+ // Read\r
+ oscctrl1.oscctrl1= pm->oscctrl1;\r
+ // Modify\r
+ oscctrl1.OSCCTRL1.mode = AVR32_PM_OSCCTRL1_MODE_EXT_CLOCK;\r
+ // Write\r
+ pm->oscctrl1 = oscctrl1.oscctrl1;\r
+}\r
+\r
+\r
+void pm_enable_osc1_crystal(volatile avr32_pm_t *pm, unsigned int fosc1)\r
+{\r
+ union {\r
+ unsigned long oscctrl1;\r
+ avr32_pm_oscctrl1_t OSCCTRL1;\r
+ } oscctrl1 ;\r
+ // Read\r
+ oscctrl1.oscctrl1= pm->oscctrl1;\r
+ // Modify\r
+ oscctrl1.OSCCTRL1.mode = (fosc1 < 8000000) ? AVR32_PM_OSCCTRL1_MODE_CRYSTAL_G2 :\r
+ AVR32_PM_OSCCTRL1_MODE_CRYSTAL_G3;\r
+ // Write\r
+ pm->oscctrl1 = oscctrl1.oscctrl1;\r
+}\r
+\r
+\r
+void pm_enable_clk1(volatile avr32_pm_t *pm, unsigned int startup)\r
+{\r
+ union {\r
+ avr32_pm_mcctrl_t MCCTRL;\r
+ unsigned long mcctrl;\r
+ } mcctrl;\r
+ union {\r
+ unsigned long oscctrl1;\r
+ avr32_pm_oscctrl1_t OSCCTRL1;\r
+ } oscctrl1 ;\r
+\r
+ // Read register\r
+ mcctrl.mcctrl = pm->mcctrl;\r
+ oscctrl1.oscctrl1 = pm->oscctrl1;\r
+\r
+ mcctrl.MCCTRL.osc1en = 1;\r
+ oscctrl1.OSCCTRL1.startup=startup;\r
+ // Write back\r
+ pm->oscctrl1 = oscctrl1.oscctrl1;\r
+ pm->mcctrl = mcctrl.mcctrl;\r
+\r
+ while(!pm->ISR.osc1rdy);\r
+}\r
+\r
+\r
+void pm_disable_clk1(volatile avr32_pm_t *pm)\r
+{\r
+ union {\r
+ avr32_pm_mcctrl_t MCCTRL;\r
+ unsigned long mcctrl;\r
+ } mcctrl;\r
+\r
+\r
+ // Read register\r
+ mcctrl.mcctrl = pm->mcctrl;\r
+\r
+ // Modify\r
+ mcctrl.MCCTRL.osc1en = 0;\r
+\r
+ // Write back\r
+ pm->mcctrl = mcctrl.mcctrl;\r
+}\r
+\r
+\r
+void pm_enable_clk1_no_wait(volatile avr32_pm_t *pm, unsigned int startup)\r
+{\r
+ union {\r
+ avr32_pm_mcctrl_t MCCTRL;\r
+ unsigned long mcctrl;\r
+ } mcctrl;\r
+ union {\r
+ unsigned long oscctrl1;\r
+ avr32_pm_oscctrl1_t OSCCTRL1;\r
+ } oscctrl1 ;\r
+\r
+ // Read register\r
+ mcctrl.mcctrl = pm->mcctrl;\r
+ oscctrl1.oscctrl1 = pm->oscctrl1;\r
+\r
+ mcctrl.MCCTRL.osc1en = 1;\r
+ oscctrl1.OSCCTRL1.startup=startup;\r
+ // Write back\r
+ pm->oscctrl1 = oscctrl1.oscctrl1;\r
+ pm->mcctrl = mcctrl.mcctrl;\r
+}\r
+\r
+\r
+void pm_wait_for_clk1_ready(volatile avr32_pm_t *pm)\r
+{\r
+ while(!pm->ISR.osc1rdy);\r
+}\r
+\r
+\r
+void pm_enable_osc32_ext_clock(volatile avr32_pm_t *pm)\r
+{\r
+ union {\r
+ unsigned long oscctrl32;\r
+ avr32_pm_oscctrl32_t OSCCTRL32;\r
+ } u_ctrl;\r
+ u_ctrl.oscctrl32 = pm->oscctrl32;\r
+ u_ctrl.OSCCTRL32.mode = AVR32_PM_OSCCTRL32_MODE_EXT_CLOCK;\r
+ pm->oscctrl32 = u_ctrl.oscctrl32;\r
+}\r
+\r
+\r
+void pm_enable_osc32_crystal(volatile avr32_pm_t *pm)\r
+{\r
+ union {\r
+ unsigned long oscctrl32;\r
+ avr32_pm_oscctrl32_t OSCCTRL32;\r
+ } u_ctrl;\r
+ u_ctrl.oscctrl32 = pm->oscctrl32;\r
+ u_ctrl.OSCCTRL32.mode = AVR32_PM_OSCCTRL32_MODE_CRYSTAL;\r
+ pm->oscctrl32 = u_ctrl.oscctrl32;\r
+}\r
+\r
+\r
+void pm_enable_clk32(volatile avr32_pm_t *pm, unsigned int startup)\r
+{\r
+ union {\r
+ unsigned long oscctrl32;\r
+ avr32_pm_oscctrl32_t OSCCTRL32;\r
+ } oscctrl32 ;\r
+\r
+ // Read register\r
+ oscctrl32.oscctrl32 = pm->oscctrl32;\r
+ // Modify\r
+ oscctrl32.OSCCTRL32.osc32en = 1;\r
+ oscctrl32.OSCCTRL32.startup=startup;\r
+ // Write back\r
+ pm->oscctrl32 = oscctrl32.oscctrl32;\r
+\r
+ while(!pm->ISR.osc32rdy);\r
+}\r
+\r
+\r
+void pm_disable_clk32(volatile avr32_pm_t *pm)\r
+{\r
+ // To get rid of a GCC bug\r
+ // This makes C code longer, but not ASM\r
+ union {\r
+ unsigned long oscctrl32;\r
+ avr32_pm_oscctrl32_t OSCCTRL32;\r
+ } oscctrl32 ;\r
+\r
+ // Read register\r
+ oscctrl32.oscctrl32 = pm->oscctrl32;\r
+ // Modify\r
+ oscctrl32.OSCCTRL32.osc32en = 0;\r
+ // Write back\r
+ pm->oscctrl32 = oscctrl32.oscctrl32;\r
+}\r
+\r
+\r
+void pm_enable_clk32_no_wait(volatile avr32_pm_t *pm, unsigned int startup)\r
+{\r
+ union {\r
+ unsigned long oscctrl32;\r
+ avr32_pm_oscctrl32_t OSCCTRL32;\r
+ } oscctrl32 ;\r
+\r
+ // Read register\r
+ oscctrl32.oscctrl32 = pm->oscctrl32;\r
+ // Modify\r
+ oscctrl32.OSCCTRL32.osc32en = 1;\r
+ oscctrl32.OSCCTRL32.startup=startup;\r
+ // Write back\r
+ pm->oscctrl32 = oscctrl32.oscctrl32;\r
+}\r
+\r
+\r
+void pm_wait_for_clk32_ready(volatile avr32_pm_t *pm)\r
+{\r
+ // To get rid of a GCC bug\r
+ // This makes C code longer, but not ASM\r
+\r
+ while(!pm->ISR.osc32rdy);\r
+}\r
+\r
+\r
+void pm_cksel(volatile avr32_pm_t *pm,\r
+ unsigned int pbadiv,\r
+ unsigned int pbasel,\r
+ unsigned int pbbdiv,\r
+ unsigned int pbbsel,\r
+ unsigned int hsbdiv,\r
+ unsigned int hsbsel)\r
+{\r
+ // Force the compiler to generate only one 32 bits access\r
+ union {\r
+ avr32_pm_cksel_t selval ;\r
+ unsigned long uword32;\r
+ } cksel;\r
+\r
+ cksel.uword32 = 0;\r
+\r
+ cksel.selval.cpudiv = hsbdiv;\r
+ cksel.selval.cpusel = hsbsel;\r
+ cksel.selval.hsbdiv = hsbdiv;\r
+ cksel.selval.hsbsel = hsbsel;\r
+ cksel.selval.pbbdiv = pbbdiv;\r
+ cksel.selval.pbbsel = pbbsel;\r
+ cksel.selval.pbadiv = pbadiv;\r
+ cksel.selval.pbasel = pbasel;\r
+\r
+ pm->cksel = cksel.uword32;\r
+\r
+ // Wait for ckrdy bit and then clear it\r
+ while(!(pm->ISR.ckrdy));\r
+\r
+ return;\r
+}\r
+\r
+\r
+void pm_gc_setup(volatile avr32_pm_t *pm,\r
+ unsigned int gc,\r
+ unsigned int osc_or_pll, // Use Osc (=0) or PLL (=1)\r
+ unsigned int pll_osc, // Sel Osc0/PLL0 or Osc1/PLL1\r
+ unsigned int diven,\r
+ unsigned int div) {\r
+ union {\r
+ unsigned long gcctrl;\r
+ avr32_pm_gcctrl_t GCCTRL;\r
+ } u_gc;\r
+\r
+ u_gc.GCCTRL.oscsel = pll_osc;\r
+ u_gc.GCCTRL.pllsel = osc_or_pll;\r
+ u_gc.GCCTRL.diven = diven;\r
+ u_gc.GCCTRL.div = div;\r
+ u_gc.GCCTRL.cen = 0; // Disable GC first\r
+ pm->gcctrl[gc] = u_gc.gcctrl;\r
+}\r
+\r
+\r
+void pm_gc_enable(volatile avr32_pm_t *pm,\r
+ unsigned int gc) {\r
+ union {\r
+ unsigned long gcctrl;\r
+ avr32_pm_gcctrl_t GCCTRL;\r
+ } u_gc;\r
+ u_gc.gcctrl = pm->gcctrl[gc];\r
+ u_gc.GCCTRL.cen = 1;\r
+ pm->gcctrl[gc] = u_gc.gcctrl;\r
+}\r
+\r
+\r
+void pm_gc_disable(volatile avr32_pm_t *pm,\r
+ unsigned int gc) {\r
+ union {\r
+ unsigned long gcctrl;\r
+ avr32_pm_gcctrl_t GCCTRL;\r
+ } u_gc;\r
+ u_gc.gcctrl = pm->gcctrl[gc];\r
+ u_gc.GCCTRL.cen = 0;\r
+ pm->gcctrl[gc] = u_gc.gcctrl;\r
+}\r
+\r
+\r
+void pm_pll_setup(volatile avr32_pm_t *pm,\r
+ unsigned int pll,\r
+ unsigned int mul,\r
+ unsigned int div,\r
+ unsigned int osc,\r
+ unsigned int lockcount) {\r
+\r
+ union {\r
+ unsigned long pll ;\r
+ avr32_pm_pll_t PLL ;\r
+ } u_pll;\r
+\r
+ u_pll.pll=0;\r
+\r
+ u_pll.PLL.pllmul = mul;\r
+ u_pll.PLL.plldiv = div;\r
+ u_pll.PLL.pllosc = osc;\r
+ u_pll.PLL.pllcount = lockcount;\r
+\r
+ u_pll.PLL.pllopt = 0;\r
+\r
+ u_pll.PLL.plltest = 0;\r
+\r
+ (pm->pll)[pll] = u_pll.pll;\r
+}\r
+\r
+\r
+void pm_pll_set_option(volatile avr32_pm_t *pm,\r
+ unsigned int pll,\r
+ unsigned int pll_freq,\r
+ unsigned int pll_div2,\r
+ unsigned int pll_wbwdisable) {\r
+ union {\r
+ unsigned long pll ;\r
+ avr32_pm_pll_t PLL ;\r
+ } u_pll;\r
+\r
+ u_pll.pll = (pm->pll)[pll];\r
+ u_pll.PLL.pllopt = pll_freq | (pll_div2<<1) | (pll_wbwdisable<<2);\r
+ (pm->pll)[pll] = u_pll.pll;\r
+}\r
+\r
+\r
+unsigned int pm_pll_get_option(volatile avr32_pm_t *pm,\r
+ unsigned int pll) {\r
+ return (pm->PLL)[pll].pllopt;\r
+}\r
+\r
+\r
+void pm_pll_enable(volatile avr32_pm_t *pm,\r
+ unsigned int pll) {\r
+ union {\r
+ unsigned long pll ;\r
+ avr32_pm_pll_t PLL ;\r
+ } u_pll;\r
+\r
+ u_pll.pll = (pm->pll)[pll];\r
+ u_pll.PLL.pllen = 1;\r
+ (pm->pll)[pll] = u_pll.pll;\r
+}\r
+\r
+\r
+void pm_pll_disable(volatile avr32_pm_t *pm,\r
+ unsigned int pll) {\r
+ union {\r
+ unsigned long pll ;\r
+ avr32_pm_pll_t PLL ;\r
+ } u_pll;\r
+\r
+ u_pll.pll = (pm->pll)[pll];\r
+ u_pll.PLL.pllen = 0;\r
+ (pm->pll)[pll] = u_pll.pll;\r
+}\r
+\r
+\r
+void pm_wait_for_pll0_locked(volatile avr32_pm_t *pm)\r
+{\r
+ while(!pm->ISR.lock0);\r
+\r
+ // Bypass the lock signal of the PLL\r
+ pm->pll[0] |= AVR32_PM_PLL0_PLLBPL_MASK;\r
+}\r
+\r
+\r
+void pm_wait_for_pll1_locked(volatile avr32_pm_t *pm)\r
+{\r
+ while(!pm->ISR.lock1);\r
+\r
+ // Bypass the lock signal of the PLL\r
+ pm->pll[1] |= AVR32_PM_PLL1_PLLBPL_MASK;\r
+}\r
+\r
+\r
+void pm_switch_to_clock(volatile avr32_pm_t *pm, unsigned long clock)\r
+{\r
+ union {\r
+ avr32_pm_mcctrl_t MCCTRL;\r
+ unsigned long mcctrl;\r
+ } mcctrl;\r
+ // Read\r
+ mcctrl.mcctrl = pm->mcctrl;\r
+ // Modify\r
+ mcctrl.MCCTRL.mcsel = clock;\r
+ // Write Back\r
+ pm->MCCTRL.mcsel = mcctrl.mcctrl;\r
+}\r
+\r
+\r
+void pm_switch_to_osc0(volatile avr32_pm_t *pm, unsigned int fosc0, unsigned int startup)\r
+{\r
+ pm_enable_osc0_crystal(pm, fosc0); // Enable the Osc0 in crystal mode\r
+ pm_enable_clk0(pm, startup); // Crystal startup time - This parameter is critical and depends on the characteristics of the crystal\r
+ pm_switch_to_clock(pm, AVR32_PM_MCSEL_OSC0); // Then switch main clock to Osc0\r
+}\r
+\r
+\r
+void pm_bod_enable_irq(volatile struct avr32_pm_t *pm) {\r
+\r
+ union {\r
+ unsigned long ier ;\r
+ avr32_pm_ier_t IER ;\r
+ } u_ier;\r
+ u_ier.ier = 0;\r
+ u_ier.IER.boddet = 1;\r
+\r
+ pm->ier = u_ier.ier;\r
+}\r
+\r
+\r
+void pm_bod_disable_irq(volatile struct avr32_pm_t *pm) {\r
+\r
+ union {\r
+ unsigned long idr ;\r
+ avr32_pm_idr_t IDR ;\r
+ } u_idr;\r
+ u_idr.idr = 0;\r
+ u_idr.IDR.boddet = 1;\r
+\r
+ pm->idr = u_idr.idr;\r
+}\r
+\r
+\r
+void pm_bod_clear_irq(volatile struct avr32_pm_t *pm) {\r
+\r
+ union {\r
+ unsigned long icr ;\r
+ avr32_pm_idr_t ICR ;\r
+ } u_icr;\r
+ u_icr.icr = 0;\r
+ u_icr.ICR.boddet = 1;\r
+\r
+ pm->icr = u_icr.icr;\r
+}\r
+\r
+\r
+unsigned long pm_bod_get_irq_status(volatile struct avr32_pm_t *pm) {\r
+\r
+ return pm->ISR.boddet;\r
+}\r
+\r
+\r
+unsigned long pm_bod_get_irq_enable_bit(volatile struct avr32_pm_t *pm) {\r
+\r
+ return pm->IMR.boddet;\r
+}\r
+\r
+\r
+unsigned long pm_bod_get_level(volatile avr32_pm_t *pm) {\r
+ union {\r
+ unsigned long bod ;\r
+ avr32_pm_bod_t BOD ;\r
+ } u_bod;\r
+\r
+ u_bod.bod = pm->bod;\r
+\r
+ return (unsigned long) u_bod.BOD.level;\r
+\r
+}\r
+\r
+\r
+void pm_write_gplp(volatile avr32_pm_t *pm,unsigned long gplp, unsigned long value) {\r
+ (pm->gplp)[gplp] = value;\r
+\r
+}\r
+\r
+\r
+unsigned long pm_read_gplp(volatile avr32_pm_t *pm,unsigned long gplp) {\r
+\r
+ return (pm->gplp)[gplp];\r
+}\r
--- /dev/null
+/*This file has been prepared for Doxygen automatic documentation generation.*/\r
+/*! \file *********************************************************************\r
+ *\r
+ * \brief Power Manager driver.\r
+ *\r
+ *\r
+ * - Compiler: IAR EWAVR32 and GNU GCC for AVR32\r
+ * - Supported devices: All AVR32 devices.\r
+ * - AppNote:\r
+ *\r
+ * \author Atmel Corporation: http://www.atmel.com \n\r
+ * Support email: avr32@atmel.com\r
+ *\r
+ *****************************************************************************/\r
+\r
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of ATMEL may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND\r
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,\r
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\r
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\r
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF\r
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ */\r
+\r
+\r
+#ifndef _PM_H_\r
+#define _PM_H_\r
+\r
+#if __GNUC__\r
+# include <avr32/io.h>\r
+#elif __ICCAVR32__\r
+# include <avr32/iouc3a0512.h>\r
+# include <avr32/uc3a0512.h>\r
+#else\r
+# error Unknown compiler\r
+#endif\r
+\r
+#include "compiler.h"\r
+#include "preprocessor.h"\r
+\r
+\r
+/*! \brief Sets the MCU in the specified sleep mode.\r
+ *\r
+ * \param mode Sleep mode:\r
+ * \arg \c AVR32_PM_SMODE_IDLE: Idle;\r
+ * \arg \c AVR32_PM_SMODE_FROZEN: Frozen;\r
+ * \arg \c AVR32_PM_SMODE_STANDBY: Standby;\r
+ * \arg \c AVR32_PM_SMODE_STOP: Stop;\r
+ * \arg \c AVR32_PM_SMODE_SHUTDOWN: Shutdown (DeepStop);\r
+ * \arg \c AVR32_PM_SMODE_STATIC: Static.\r
+ */\r
+#define SLEEP(mode) {__asm__ __volatile__ ("sleep "STRINGZ(mode));}\r
+\r
+\r
+/*!\r
+ * \brief This function will enable the external clock mode of the oscillator 0.\r
+ * \param pm Base address of the Power Manager (i.e. &AVR32_PM)\r
+ */\r
+extern void pm_enable_osc0_ext_clock(volatile avr32_pm_t *pm);\r
+\r
+\r
+/*!\r
+ * \brief This function will enable the crystal mode of the oscillator 0.\r
+ * \param pm Base address of the Power Manager (i.e. &AVR32_PM)\r
+ * \param fosc0 Oscillator 0 crystal frequency (Hz)\r
+ */\r
+extern void pm_enable_osc0_crystal(volatile avr32_pm_t *pm, unsigned int fosc0);\r
+\r
+\r
+/*!\r
+ * \brief This function will enable the oscillator 0 to be used with a startup time.\r
+ * \param pm Base address of the Power Manager (i.e. &AVR32_PM)\r
+ * \param startup Clock 0 startup time. Time is expressed in term of RCOsc periods (3-bit value)\r
+ */\r
+extern void pm_enable_clk0(volatile avr32_pm_t *pm, unsigned int startup);\r
+\r
+\r
+/*!\r
+ * \brief This function will disable the oscillator 0.\r
+ * \param pm Base address of the Power Manager (i.e. &AVR32_PM)\r
+ */\r
+extern void pm_disable_clk0(volatile avr32_pm_t *pm);\r
+\r
+\r
+/*!\r
+ * \brief This function will enable the oscillator 0 to be used with no startup time.\r
+ * \param pm Base address of the Power Manager (i.e. &AVR32_PM)\r
+ * \param startup Clock 0 startup time. Time is expressed in term of RCOsc periods (3-bit value) but not checked.\r
+ */\r
+extern void pm_enable_clk0_no_wait(volatile avr32_pm_t *pm, unsigned int startup);\r
+\r
+\r
+/*!\r
+ * \brief This function will wait until the Osc0 clock is ready.\r
+ * \param pm Base address of the Power Manager (i.e. &AVR32_PM)\r
+ */\r
+extern void pm_wait_for_clk0_ready(volatile avr32_pm_t *pm);\r
+\r
+\r
+/*!\r
+ * \brief This function will enable the external clock mode of the oscillator 1.\r
+ * \param pm Base address of the Power Manager (i.e. &AVR32_PM)\r
+ */\r
+extern void pm_enable_osc1_ext_clock(volatile avr32_pm_t *pm);\r
+\r
+\r
+/*!\r
+ * \brief This function will enable the crystal mode of the oscillator 1.\r
+ * \param pm Base address of the Power Manager (i.e. &AVR32_PM)\r
+ * \param fosc1 Oscillator 1 crystal frequency (Hz)\r
+ */\r
+extern void pm_enable_osc1_crystal(volatile avr32_pm_t *pm, unsigned int fosc1);\r
+\r
+\r
+/*!\r
+ * \brief This function will enable the oscillator 1 to be used with a startup time.\r
+ * \param pm Base address of the Power Manager (i.e. &AVR32_PM)\r
+ * \param startup Clock 1 startup time. Time is expressed in term of RCOsc periods (3-bit value)\r
+ */\r
+extern void pm_enable_clk1(volatile avr32_pm_t *pm, unsigned int startup);\r
+\r
+\r
+/*!\r
+ * \brief This function will disable the oscillator 1.\r
+ * \param pm Base address of the Power Manager (i.e. &AVR32_PM)\r
+ */\r
+extern void pm_disable_clk1(volatile avr32_pm_t *pm);\r
+\r
+\r
+/*!\r
+ * \brief This function will enable the oscillator 1 to be used with no startup time.\r
+ * \param pm Base address of the Power Manager (i.e. &AVR32_PM)\r
+ * \param startup Clock 1 startup time. Time is expressed in term of RCOsc periods (3-bit value) but not checked.\r
+ */\r
+extern void pm_enable_clk1_no_wait(volatile avr32_pm_t *pm, unsigned int startup);\r
+\r
+\r
+/*!\r
+ * \brief This function will wait until the Osc1 clock is ready.\r
+ * \param pm Base address of the Power Manager (i.e. &AVR32_PM)\r
+ */\r
+extern void pm_wait_for_clk1_ready(volatile avr32_pm_t *pm);\r
+\r
+\r
+/*!\r
+ * \brief This function will enable the external clock mode of the 32-kHz oscillator.\r
+ * \param pm Base address of the Power Manager (i.e. &AVR32_PM)\r
+ */\r
+extern void pm_enable_osc32_ext_clock(volatile avr32_pm_t *pm);\r
+\r
+\r
+/*!\r
+ * \brief This function will enable the crystal mode of the 32-kHz oscillator.\r
+ * \param pm Base address of the Power Manager (i.e. &AVR32_PM)\r
+ */\r
+extern void pm_enable_osc32_crystal(volatile avr32_pm_t *pm);\r
+\r
+\r
+/*!\r
+ * \brief This function will enable the oscillator 32 to be used with a startup time.\r
+ * \param pm Base address of the Power Manager (i.e. &AVR32_PM)\r
+ * \param startup Clock 32 kHz startup time. Time is expressed in term of RCOsc periods (3-bit value)\r
+ */\r
+extern void pm_enable_clk32(volatile avr32_pm_t *pm, unsigned int startup);\r
+\r
+\r
+/*!\r
+ * \brief This function will disable the oscillator 32.\r
+ * \param pm Base address of the Power Manager (i.e. &AVR32_PM)\r
+ */\r
+extern void pm_disable_clk32(volatile avr32_pm_t *pm);\r
+\r
+\r
+/*!\r
+ * \brief This function will enable the oscillator 32 to be used with no startup time.\r
+ * \param pm Base address of the Power Manager (i.e. &AVR32_PM)\r
+ * \param startup Clock 32 kHz startup time. Time is expressed in term of RCOsc periods (3-bit value) but not checked.\r
+ */\r
+extern void pm_enable_clk32_no_wait(volatile avr32_pm_t *pm, unsigned int startup);\r
+\r
+\r
+/*!\r
+ * \brief This function will wait until the osc32 clock is ready.\r
+ * \param pm Base address of the Power Manager (i.e. &AVR32_PM)\r
+ */\r
+extern void pm_wait_for_clk32_ready(volatile avr32_pm_t *pm);\r
+\r
+\r
+//FIXME update this header -SM\r
+/*!\r
+ * \brief This function will select all the power manager clocks.\r
+ * \param pm Base address of the Power Manager (i.e. &AVR32_PM)\r
+ * \param pbadiv Peripheral Bus A clock divisor enable\r
+ * \param pbasel Peripheral Bus A select\r
+ * \param pbbdiv Peripheral Bus B clock divisor enable\r
+ * \param pbbsel Peripheral Bus B select\r
+ * \param hsbdiv High Speed Bus clock divisor enable (CPU clock = HSB clock)\r
+ * \param hsbsel High Speed Bus select (CPU clock = HSB clock )\r
+ */\r
+extern void pm_cksel(volatile avr32_pm_t *pm, unsigned int pbadiv, unsigned int pbasel, unsigned int pbbdiv, unsigned int pbbsel, unsigned int hsbdiv, unsigned int hsbsel);\r
+\r
+\r
+/*!\r
+ * \brief This function will setup a generic clock.\r
+ * \param pm Base address of the Power Manager (i.e. &AVR32_PM)\r
+ * \param gc generic clock number (0 for gc0...)\r
+ * \param osc_or_pll Use OSC (=0) or PLL (=1)\r
+ * \param pll_osc Select Osc0/PLL0 or Osc1/PLL1\r
+ * \param diven Generic clock divisor enable\r
+ * \param div Generic clock divisor\r
+ */\r
+extern void pm_gc_setup(volatile avr32_pm_t *pm, unsigned int gc, unsigned int osc_or_pll, unsigned int pll_osc, unsigned int diven, unsigned int div);\r
+\r
+\r
+/*!\r
+ * \brief This function will enable a generic clock.\r
+ * \param pm Base address of the Power Manager (i.e. &AVR32_PM)\r
+ * \param gc generic clock number (0 for gc0...)\r
+ */\r
+extern void pm_gc_enable(volatile avr32_pm_t *pm, unsigned int gc);\r
+\r
+\r
+/*!\r
+ * \brief This function will disable a generic clock.\r
+ * \param pm Base address of the Power Manager (i.e. &AVR32_PM)\r
+ * \param gc generic clock number (0 for gc0...)\r
+ */\r
+extern void pm_gc_disable(volatile avr32_pm_t *pm, unsigned int gc);\r
+\r
+\r
+//FIXME update this header -SM\r
+/*!\r
+ * \brief This function will setup a PLL.\r
+ * \param pm Base address of the Power Manager (i.e. &AVR32_PM)\r
+ * \param pll PLL number(0 for PLL0, 1 for PLL1)\r
+ * \param mul\r
+ * \param div\r
+ * \param osc\r
+ * \param lockcount\r
+ */\r
+extern void pm_pll_setup(volatile avr32_pm_t *pm, unsigned int pll, unsigned int mul, unsigned int div, unsigned int osc, unsigned int lockcount);\r
+\r
+\r
+//FIXME update this header -SM\r
+/*!\r
+ * \brief This function will set a PLL option.\r
+ * \param pm Base address of the Power Manager (i.e. &AVR32_PM)\r
+ * \param pll PLL number(0 for PLL0, 1 for PLL1)\r
+ * \param pll_freq Set to 1 for VCO frequency range 80-180MHz, set to 0 for VCO frequency range 160-240Mhz.\r
+ * \param pll_div2 Divide the PLL output frequency by 2 (this settings does not change the FVCO value)\r
+ * \param pll_wbwdisable 1 Disable the Wide-Bandith Mode (Wide-Bandwith mode allow a faster startup time and out-of-lock time). 0 to enable the Wide-Bandith Mode.\r
+ */\r
+extern void pm_pll_set_option(volatile avr32_pm_t *pm, unsigned int pll, unsigned int pll_freq, unsigned int pll_div2, unsigned int pll_wbwdisable);\r
+\r
+\r
+//FIXME update this header -SM\r
+/*!\r
+ * \brief This function will get a PLL option.\r
+ * \param pm Base address of the Power Manager (i.e. &AVR32_PM)\r
+ * \param pll PLL number(0 for PLL0, 1 for PLL1)\r
+ * \return Option\r
+ */\r
+extern unsigned int pm_pll_get_option(volatile avr32_pm_t *pm, unsigned int pll);\r
+\r
+\r
+/*!\r
+ * \brief This function will enable a PLL.\r
+ * \param pm Base address of the Power Manager (i.e. &AVR32_PM)\r
+ * \param pll PLL number(0 for PLL0, 1 for PLL1)\r
+ */\r
+extern void pm_pll_enable(volatile avr32_pm_t *pm, unsigned int pll);\r
+\r
+\r
+/*!\r
+ * \brief This function will disable a PLL.\r
+ * \param pm Base address of the Power Manager (i.e. &AVR32_PM)\r
+ * \param pll PLL number(0 for PLL0, 1 for PLL1)\r
+ */\r
+extern void pm_pll_disable(volatile avr32_pm_t *pm, unsigned int pll);\r
+\r
+\r
+/*!\r
+ * \brief This function will wait for PLL0 locked\r
+ * \param pm Base address of the Power Manager (i.e. &AVR32_PM)\r
+ */\r
+extern void pm_wait_for_pll0_locked(volatile avr32_pm_t *pm);\r
+\r
+\r
+/*!\r
+ * \brief This function will wait for PLL1 locked\r
+ * \param pm Base address of the Power Manager (i.e. &AVR32_PM)\r
+ */\r
+extern void pm_wait_for_pll1_locked(volatile avr32_pm_t *pm);\r
+\r
+\r
+/*!\r
+ * \brief This function will switch the power manager main clock.\r
+ * \param pm Base address of the Power Manager (i.e. &AVR32_PM)\r
+ * \param clock Clock to be switched on. AVR32_PM_MCSEL_SLOW for RCOsc, AVR32_PM_MCSEL_OSC0 for Osc0, AVR32_PM_MCSEL_PLL0 for PLL0.\r
+ */\r
+extern void pm_switch_to_clock(volatile avr32_pm_t *pm, unsigned long clock);\r
+\r
+\r
+/*!\r
+ * \brief Switch main clock to clock Osc0 (crystal mode)\r
+ * \param pm Base address of the Power Manager (i.e. &AVR32_PM)\r
+ * \param fosc0 Oscillator 0 crystal frequency (Hz)\r
+ * \param startup Crystal 0 startup time. Time is expressed in term of RCOsc periods (3-bit value)\r
+ */\r
+extern void pm_switch_to_osc0(volatile avr32_pm_t *pm, unsigned int fosc0, unsigned int startup);\r
+\r
+\r
+#endif // _PM_H_\r
--- /dev/null
+/*This file is prepared for Doxygen automatic documentation generation.*/\r
+/*! \file *********************************************************************\r
+ *\r
+ * \brief TC driver for AVR32 UC3.\r
+ *\r
+ * AVR32 Timer/Counter driver module.\r
+ *\r
+ * - Compiler: IAR EWAVR32 and GNU GCC for AVR32\r
+ * - Supported devices: All AVR32 devices with a TC module can be used.\r
+ * - AppNote:\r
+ *\r
+ * \author Atmel Corporation: http://www.atmel.com \n\r
+ * Support email: avr32@atmel.com\r
+ *\r
+ ******************************************************************************/\r
+\r
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of ATMEL may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND\r
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,\r
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\r
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\r
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF\r
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ */\r
+\r
+\r
+#if __GNUC__\r
+# include <avr32/io.h>\r
+#elif __ICCAVR32__\r
+# include <avr32/iouc3a0512.h>\r
+#else\r
+# error Unknown compiler\r
+#endif\r
+\r
+#include "compiler.h"\r
+#include "tc.h"\r
+\r
+\r
+int tc_get_interrupt_settings(volatile avr32_tc_t *tc, unsigned int channel)\r
+{\r
+ // Check for valid input.\r
+ if (channel >= TC_NUMBER_OF_CHANNELS)\r
+ return TC_INVALID_ARGUMENT;\r
+\r
+ return tc->channel[channel].imr;\r
+}\r
+\r
+\r
+int tc_configure_interrupts(volatile avr32_tc_t *tc, unsigned int channel, const tc_interrupt_t *bitfield)\r
+{\r
+ // Check for valid input.\r
+ if (channel >= TC_NUMBER_OF_CHANNELS)\r
+ return TC_INVALID_ARGUMENT;\r
+\r
+ // Enable the appropriate interrupts.\r
+ tc->channel[channel].ier = bitfield->etrgs << AVR32_TC_ETRGS_OFFSET |\r
+ bitfield->ldrbs << AVR32_TC_LDRBS_OFFSET |\r
+ bitfield->ldras << AVR32_TC_LDRAS_OFFSET |\r
+ bitfield->cpcs << AVR32_TC_CPCS_OFFSET |\r
+ bitfield->cpbs << AVR32_TC_CPBS_OFFSET |\r
+ bitfield->cpas << AVR32_TC_CPAS_OFFSET |\r
+ bitfield->lovrs << AVR32_TC_LOVRS_OFFSET |\r
+ bitfield->covfs << AVR32_TC_COVFS_OFFSET;\r
+\r
+ // Disable the appropriate interrupts.\r
+ tc->channel[channel].idr = (~bitfield->etrgs & 1) << AVR32_TC_ETRGS_OFFSET |\r
+ (~bitfield->ldrbs & 1) << AVR32_TC_LDRBS_OFFSET |\r
+ (~bitfield->ldras & 1) << AVR32_TC_LDRAS_OFFSET |\r
+ (~bitfield->cpcs & 1) << AVR32_TC_CPCS_OFFSET |\r
+ (~bitfield->cpbs & 1) << AVR32_TC_CPBS_OFFSET |\r
+ (~bitfield->cpas & 1) << AVR32_TC_CPAS_OFFSET |\r
+ (~bitfield->lovrs & 1) << AVR32_TC_LOVRS_OFFSET |\r
+ (~bitfield->covfs & 1) << AVR32_TC_COVFS_OFFSET;\r
+\r
+ return 0;\r
+}\r
+\r
+\r
+int tc_select_external_clock(volatile avr32_tc_t *tc, unsigned int channel, unsigned int ext_clk_sig_src)\r
+{\r
+ // Check for valid input.\r
+ if (channel >= TC_NUMBER_OF_CHANNELS || ext_clk_sig_src >= 1 << AVR32_TC_BMR_TC0XC0S_SIZE)\r
+ return TC_INVALID_ARGUMENT;\r
+\r
+ // Clear bit-field and set the correct behavior.\r
+ tc->bmr = (tc->bmr & ~(AVR32_TC_BMR_TC0XC0S_MASK << (channel * AVR32_TC_BMR_TC0XC0S_SIZE))) |\r
+ (ext_clk_sig_src << (channel * AVR32_TC_BMR_TC0XC0S_SIZE));\r
+\r
+ return 0;\r
+}\r
+\r
+\r
+int tc_init_capture(volatile avr32_tc_t *tc, const tc_capture_opt_t *opt)\r
+{\r
+ // Check for valid input.\r
+ if (opt->channel >= TC_NUMBER_OF_CHANNELS)\r
+ return TC_INVALID_ARGUMENT;\r
+\r
+ // MEASURE SIGNALS: Capture operating mode.\r
+ tc->channel[opt->channel].cmr = opt->ldrb << AVR32_TC_LDRB_OFFSET |\r
+ opt->ldra << AVR32_TC_LDRA_OFFSET |\r
+ 0 << AVR32_TC_WAVE_OFFSET |\r
+ opt->cpctrg << AVR32_TC_CPCTRG_OFFSET |\r
+ opt->abetrg << AVR32_TC_ABETRG_OFFSET |\r
+ opt->etrgedg << AVR32_TC_ETRGEDG_OFFSET|\r
+ opt->ldbdis << AVR32_TC_LDBDIS_OFFSET |\r
+ opt->ldbstop << AVR32_TC_LDBSTOP_OFFSET |\r
+ opt->burst << AVR32_TC_BURST_OFFSET |\r
+ opt->clki << AVR32_TC_CLKI_OFFSET |\r
+ opt->tcclks << AVR32_TC_TCCLKS_OFFSET;\r
+\r
+ return 0;\r
+}\r
+\r
+\r
+int tc_init_waveform(volatile avr32_tc_t *tc, const tc_waveform_opt_t *opt)\r
+{\r
+ // Check for valid input.\r
+ if (opt->channel >= TC_NUMBER_OF_CHANNELS)\r
+ return TC_INVALID_ARGUMENT;\r
+\r
+ // GENERATE SIGNALS: Waveform operating mode.\r
+ tc->channel[opt->channel].cmr = opt->bswtrg << AVR32_TC_BSWTRG_OFFSET |\r
+ opt->beevt << AVR32_TC_BEEVT_OFFSET |\r
+ opt->bcpc << AVR32_TC_BCPC_OFFSET |\r
+ opt->bcpb << AVR32_TC_BCPB_OFFSET |\r
+ opt->aswtrg << AVR32_TC_ASWTRG_OFFSET |\r
+ opt->aeevt << AVR32_TC_AEEVT_OFFSET |\r
+ opt->acpc << AVR32_TC_ACPC_OFFSET |\r
+ opt->acpa << AVR32_TC_ACPA_OFFSET |\r
+ 1 << AVR32_TC_WAVE_OFFSET |\r
+ opt->wavsel << AVR32_TC_WAVSEL_OFFSET |\r
+ opt->enetrg << AVR32_TC_ENETRG_OFFSET |\r
+ opt->eevt << AVR32_TC_EEVT_OFFSET |\r
+ opt->eevtedg << AVR32_TC_EEVTEDG_OFFSET |\r
+ opt->cpcdis << AVR32_TC_CPCDIS_OFFSET |\r
+ opt->cpcstop << AVR32_TC_CPCSTOP_OFFSET |\r
+ opt->burst << AVR32_TC_BURST_OFFSET |\r
+ opt->clki << AVR32_TC_CLKI_OFFSET |\r
+ opt->tcclks << AVR32_TC_TCCLKS_OFFSET;\r
+\r
+ return 0;\r
+}\r
+\r
+\r
+int tc_start(volatile avr32_tc_t *tc, unsigned int channel)\r
+{\r
+ // Check for valid input.\r
+ if (channel >= TC_NUMBER_OF_CHANNELS)\r
+ return TC_INVALID_ARGUMENT;\r
+\r
+ // Enable, reset and start the selected timer/counter channel.\r
+ tc->channel[channel].ccr = AVR32_TC_SWTRG_MASK | AVR32_TC_CLKEN_MASK;\r
+\r
+ return 0;\r
+}\r
+\r
+\r
+int tc_stop(volatile avr32_tc_t *tc, unsigned int channel)\r
+{\r
+ // Check for valid input.\r
+ if (channel >= TC_NUMBER_OF_CHANNELS)\r
+ return TC_INVALID_ARGUMENT;\r
+\r
+ // Disable the selected timer/counter channel.\r
+ tc->channel[channel].ccr = AVR32_TC_CLKDIS_MASK;\r
+\r
+ return 0;\r
+}\r
+\r
+\r
+int tc_software_trigger(volatile avr32_tc_t *tc, unsigned int channel)\r
+{\r
+ // Check for valid input.\r
+ if (channel >= TC_NUMBER_OF_CHANNELS)\r
+ return TC_INVALID_ARGUMENT;\r
+\r
+ // Reset the selected timer/counter channel.\r
+ tc->channel[channel].ccr = AVR32_TC_SWTRG_MASK;\r
+\r
+ return 0;\r
+}\r
+\r
+\r
+void tc_sync_trigger(volatile avr32_tc_t *tc)\r
+{\r
+ // Reset all channels of the selected timer/counter.\r
+ tc->bcr = AVR32_TC_BCR_SYNC_MASK;\r
+}\r
+\r
+\r
+int tc_read_sr(volatile avr32_tc_t *tc, unsigned int channel)\r
+{\r
+ // Check for valid input.\r
+ if (channel >= TC_NUMBER_OF_CHANNELS)\r
+ return TC_INVALID_ARGUMENT;\r
+\r
+ return tc->channel[channel].sr;\r
+}\r
+\r
+\r
+int tc_read_tc(volatile avr32_tc_t *tc, unsigned int channel)\r
+{\r
+ // Check for valid input.\r
+ if (channel >= TC_NUMBER_OF_CHANNELS)\r
+ return TC_INVALID_ARGUMENT;\r
+\r
+ return Rd_bitfield(tc->channel[channel].cv, AVR32_TC_CV_MASK);\r
+}\r
+\r
+\r
+int tc_read_ra(volatile avr32_tc_t *tc, unsigned int channel)\r
+{\r
+ // Check for valid input.\r
+ if (channel >= TC_NUMBER_OF_CHANNELS)\r
+ return TC_INVALID_ARGUMENT;\r
+\r
+ return Rd_bitfield(tc->channel[channel].ra, AVR32_TC_RA_MASK);\r
+}\r
+\r
+\r
+int tc_read_rb(volatile avr32_tc_t *tc, unsigned int channel)\r
+{\r
+ // Check for valid input.\r
+ if (channel >= TC_NUMBER_OF_CHANNELS)\r
+ return TC_INVALID_ARGUMENT;\r
+\r
+ return Rd_bitfield(tc->channel[channel].rb, AVR32_TC_RB_MASK);\r
+}\r
+\r
+\r
+int tc_read_rc(volatile avr32_tc_t *tc, unsigned int channel)\r
+{\r
+ // Check for valid input.\r
+ if (channel >= TC_NUMBER_OF_CHANNELS)\r
+ return TC_INVALID_ARGUMENT;\r
+\r
+ return Rd_bitfield(tc->channel[channel].rc, AVR32_TC_RC_MASK);\r
+}\r
+\r
+\r
+int tc_write_ra(volatile avr32_tc_t *tc, unsigned int channel, unsigned short value)\r
+{\r
+ // Check for valid input.\r
+ if (channel >= TC_NUMBER_OF_CHANNELS)\r
+ return TC_INVALID_ARGUMENT;\r
+\r
+ // This function is only available in WAVEFORM mode.\r
+ if (Tst_bits(tc->channel[channel].cmr, AVR32_TC_WAVE_MASK))\r
+ Wr_bitfield(tc->channel[channel].ra, AVR32_TC_RA_MASK, value);\r
+\r
+ return value;\r
+}\r
+\r
+\r
+int tc_write_rb(volatile avr32_tc_t *tc, unsigned int channel, unsigned short value)\r
+{\r
+ // Check for valid input.\r
+ if (channel >= TC_NUMBER_OF_CHANNELS)\r
+ return TC_INVALID_ARGUMENT;\r
+\r
+ // This function is only available in WAVEFORM mode.\r
+ if (Tst_bits(tc->channel[channel].cmr, AVR32_TC_WAVE_MASK))\r
+ Wr_bitfield(tc->channel[channel].rb, AVR32_TC_RB_MASK, value);\r
+\r
+ return value;\r
+}\r
+\r
+\r
+int tc_write_rc(volatile avr32_tc_t *tc, unsigned int channel, unsigned short value)\r
+{\r
+ // Check for valid input.\r
+ if (channel >= TC_NUMBER_OF_CHANNELS)\r
+ return TC_INVALID_ARGUMENT;\r
+\r
+ // This function is only available in WAVEFORM mode.\r
+ if (Tst_bits(tc->channel[channel].cmr, AVR32_TC_WAVE_MASK))\r
+ Wr_bitfield(tc->channel[channel].rc, AVR32_TC_RC_MASK, value);\r
+\r
+ return value;\r
+}\r
--- /dev/null
+/*This file is prepared for Doxygen automatic documentation generation.*/\r
+/*! \file *********************************************************************\r
+ *\r
+ * \brief Timer/Counter driver for AVR32 UC3.\r
+ *\r
+ * AVR32 Timer/Counter driver module.\r
+ *\r
+ * - Compiler: IAR EWAVR32 and GNU GCC for AVR32\r
+ * - Supported devices: All AVR32 devices with a TC module can be used.\r
+ * - AppNote:\r
+ *\r
+ * \author Atmel Corporation: http://www.atmel.com \n\r
+ * Support email: avr32@atmel.com\r
+ *\r
+ ******************************************************************************/\r
+\r
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of ATMEL may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND\r
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,\r
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\r
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\r
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF\r
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ */\r
+\r
+\r
+#ifndef _TC_H_\r
+#define _TC_H_\r
+\r
+#if __GNUC__\r
+# include <avr32/io.h>\r
+#elif __ICCAVR32__\r
+# include <avr32/iouc3a0512.h>\r
+#else\r
+# error Unknown compiler\r
+#endif\r
+\r
+\r
+//! TC driver functions return value in case of invalid argument(s).\r
+#define TC_INVALID_ARGUMENT -1\r
+\r
+//! Number of timer/counter channels.\r
+#define TC_NUMBER_OF_CHANNELS (sizeof(((avr32_tc_t *)0)->channel) / sizeof(avr32_tc_channel_t))\r
+\r
+/*! \name External Clock Signal 0 Selection\r
+ */\r
+//! @{\r
+#define TC_CH0_EXT_CLK0_SRC_TCLK0 AVR32_TC_TC0XC0S_TCLK0\r
+#define TC_CH0_EXT_CLK0_SRC_NO_CLK AVR32_TC_TC0XC0S_NO_CLK\r
+#define TC_CH0_EXT_CLK0_SRC_TIOA1 AVR32_TC_TC0XC0S_TIOA1\r
+#define TC_CH0_EXT_CLK0_SRC_TIOA2 AVR32_TC_TC0XC0S_TIOA2\r
+//! @}\r
+\r
+/*! \name External Clock Signal 1 Selection\r
+ */\r
+//! @{\r
+#define TC_CH1_EXT_CLK1_SRC_TCLK1 AVR32_TC_TC1XC1S_TCLK1\r
+#define TC_CH1_EXT_CLK1_SRC_NO_CLK AVR32_TC_TC1XC1S_NO_CLK\r
+#define TC_CH1_EXT_CLK1_SRC_TIOA0 AVR32_TC_TC1XC1S_TIOA0\r
+#define TC_CH1_EXT_CLK1_SRC_TIOA2 AVR32_TC_TC1XC1S_TIOA2\r
+//! @}\r
+\r
+/*! \name External Clock Signal 2 Selection\r
+ */\r
+//! @{\r
+#define TC_CH2_EXT_CLK2_SRC_TCLK2 AVR32_TC_TC2XC2S_TCLK2\r
+#define TC_CH2_EXT_CLK2_SRC_NO_CLK AVR32_TC_TC2XC2S_NO_CLK\r
+#define TC_CH2_EXT_CLK2_SRC_TIOA0 AVR32_TC_TC2XC2S_TIOA0\r
+#define TC_CH2_EXT_CLK2_SRC_TIOA1 AVR32_TC_TC2XC2S_TIOA1\r
+//! @}\r
+\r
+/*! \name Event/Trigger Actions on Output\r
+ */\r
+//! @{\r
+#define TC_EVT_EFFECT_NOOP AVR32_TC_NONE\r
+#define TC_EVT_EFFECT_SET AVR32_TC_SET\r
+#define TC_EVT_EFFECT_CLEAR AVR32_TC_CLEAR\r
+#define TC_EVT_EFFECT_TOGGLE AVR32_TC_TOGGLE\r
+//! @}\r
+\r
+/*! \name RC Compare Trigger Enable\r
+ */\r
+//! @{\r
+#define TC_NO_TRIGGER_COMPARE_RC 0\r
+#define TC_TRIGGER_COMPARE_RC 1\r
+//! @}\r
+\r
+/*! \name Waveform Selection\r
+ */\r
+//! @{\r
+#define TC_WAVEFORM_SEL_UP_MODE AVR32_TC_WAVSEL_UP_NO_AUTO\r
+#define TC_WAVEFORM_SEL_UP_MODE_RC_TRIGGER AVR32_TC_WAVSEL_UP_AUTO\r
+#define TC_WAVEFORM_SEL_UPDOWN_MODE AVR32_TC_WAVSEL_UPDOWN_NO_AUTO\r
+#define TC_WAVEFORM_SEL_UPDOWN_MODE_RC_TRIGGER AVR32_TC_WAVSEL_UPDOWN_AUTO\r
+//! @}\r
+\r
+/*! \name TIOA or TIOB External Trigger Selection\r
+ */\r
+//! @{\r
+#define TC_EXT_TRIG_SEL_TIOA 1\r
+#define TC_EXT_TRIG_SEL_TIOB 0\r
+//! @}\r
+\r
+/*! \name External Event Selection\r
+ */\r
+//! @{\r
+#define TC_EXT_EVENT_SEL_TIOB_INPUT AVR32_TC_EEVT_TIOB_INPUT\r
+#define TC_EXT_EVENT_SEL_XC0_OUTPUT AVR32_TC_EEVT_XC0_OUTPUT\r
+#define TC_EXT_EVENT_SEL_XC1_OUTPUT AVR32_TC_EEVT_XC1_OUTPUT\r
+#define TC_EXT_EVENT_SEL_XC2_OUTPUT AVR32_TC_EEVT_XC2_OUTPUT\r
+//! @}\r
+\r
+/*! \name Edge Selection\r
+ */\r
+//! @{\r
+#define TC_SEL_NO_EDGE AVR32_TC_EEVTEDG_NO_EDGE\r
+#define TC_SEL_RISING_EDGE AVR32_TC_EEVTEDG_POS_EDGE\r
+#define TC_SEL_FALLING_EDGE AVR32_TC_EEVTEDG_NEG_EDGE\r
+#define TC_SEL_EACH_EDGE AVR32_TC_EEVTEDG_BOTH_EDGES\r
+//! @}\r
+\r
+/*! \name Burst Signal Selection\r
+ */\r
+//! @{\r
+#define TC_BURST_NOT_GATED AVR32_TC_BURST_NOT_GATED\r
+#define TC_BURST_CLK_AND_XC0 AVR32_TC_BURST_CLK_AND_XC0\r
+#define TC_BURST_CLK_AND_XC1 AVR32_TC_BURST_CLK_AND_XC1\r
+#define TC_BURST_CLK_AND_XC2 AVR32_TC_BURST_CLK_AND_XC2\r
+//! @}\r
+\r
+/*! \name Clock Invert\r
+ */\r
+//! @{\r
+#define TC_CLOCK_RISING_EDGE 0\r
+#define TC_CLOCK_FALLING_EDGE 1\r
+//! @}\r
+\r
+/*! \name Clock Selection\r
+ */\r
+//! @{\r
+#define TC_CLOCK_SOURCE_TC1 AVR32_TC_TCCLKS_TIMER_DIV1_CLOCK\r
+#define TC_CLOCK_SOURCE_TC2 AVR32_TC_TCCLKS_TIMER_DIV2_CLOCK\r
+#define TC_CLOCK_SOURCE_TC3 AVR32_TC_TCCLKS_TIMER_DIV3_CLOCK\r
+#define TC_CLOCK_SOURCE_TC4 AVR32_TC_TCCLKS_TIMER_DIV4_CLOCK\r
+#define TC_CLOCK_SOURCE_TC5 AVR32_TC_TCCLKS_TIMER_DIV5_CLOCK\r
+#define TC_CLOCK_SOURCE_XC0 AVR32_TC_TCCLKS_XC0\r
+#define TC_CLOCK_SOURCE_XC1 AVR32_TC_TCCLKS_XC1\r
+#define TC_CLOCK_SOURCE_XC2 AVR32_TC_TCCLKS_XC2\r
+//! @}\r
+\r
+\r
+//! Timer/counter interrupts.\r
+typedef struct\r
+{\r
+ unsigned int :24;\r
+\r
+ //! External trigger interrupt.\r
+ unsigned int etrgs : 1;\r
+\r
+ //! RB load interrupt.\r
+ unsigned int ldrbs : 1;\r
+\r
+ //! RA load interrupt.\r
+ unsigned int ldras : 1;\r
+\r
+ //! RC compare interrupt.\r
+ unsigned int cpcs : 1;\r
+\r
+ //! RB compare interrupt.\r
+ unsigned int cpbs : 1;\r
+\r
+ //! RA compare interrupt.\r
+ unsigned int cpas : 1;\r
+\r
+ //! Load overrun interrupt.\r
+ unsigned int lovrs : 1;\r
+\r
+ //! Counter overflow interrupt.\r
+ unsigned int covfs : 1;\r
+} tc_interrupt_t;\r
+\r
+//! Parameters when initializing a timer/counter in capture mode.\r
+typedef struct\r
+{\r
+ //! Channel to initialize.\r
+ unsigned int channel ;\r
+\r
+ unsigned int :12;\r
+\r
+ //! RB loading selection:\n\r
+ //! - \ref TC_SEL_NO_EDGE;\n\r
+ //! - \ref TC_SEL_RISING_EDGE;\n\r
+ //! - \ref TC_SEL_FALLING_EDGE;\n\r
+ //! - \ref TC_SEL_EACH_EDGE.\r
+ unsigned int ldrb : 2;\r
+\r
+ //! RA loading selection:\n\r
+ //! - \ref TC_SEL_NO_EDGE;\n\r
+ //! - \ref TC_SEL_RISING_EDGE;\n\r
+ //! - \ref TC_SEL_FALLING_EDGE;\n\r
+ //! - \ref TC_SEL_EACH_EDGE.\r
+ unsigned int ldra : 2;\r
+\r
+ unsigned int : 1;\r
+\r
+ //! RC compare trigger enable:\n\r
+ //! - \ref TC_NO_TRIGGER_COMPARE_RC;\n\r
+ //! - \ref TC_TRIGGER_COMPARE_RC.\r
+ unsigned int cpctrg : 1;\r
+\r
+ unsigned int : 3;\r
+\r
+ //! TIOA or TIOB external trigger selection:\n\r
+ //! - \ref TC_EXT_TRIG_SEL_TIOA;\n\r
+ //! - \ref TC_EXT_TRIG_SEL_TIOB.\r
+ unsigned int abetrg : 1;\r
+\r
+ //! External trigger edge selection:\n\r
+ //! - \ref TC_SEL_NO_EDGE;\n\r
+ //! - \ref TC_SEL_RISING_EDGE;\n\r
+ //! - \ref TC_SEL_FALLING_EDGE;\n\r
+ //! - \ref TC_SEL_EACH_EDGE.\r
+ unsigned int etrgedg : 2;\r
+\r
+ //! Counter clock disable with RB loading:\n\r
+ //! - \c FALSE;\n\r
+ //! - \c TRUE.\r
+ unsigned int ldbdis : 1;\r
+\r
+ //! Counter clock stopped with RB loading:\n\r
+ //! - \c FALSE;\n\r
+ //! - \c TRUE.\r
+ unsigned int ldbstop : 1;\r
+\r
+ //! Burst signal selection:\n\r
+ //! - \ref TC_BURST_NOT_GATED;\n\r
+ //! - \ref TC_BURST_CLK_AND_XC0;\n\r
+ //! - \ref TC_BURST_CLK_AND_XC1;\n\r
+ //! - \ref TC_BURST_CLK_AND_XC2.\r
+ unsigned int burst : 2;\r
+\r
+ //! Clock invert:\n\r
+ //! - \ref TC_CLOCK_RISING_EDGE;\n\r
+ //! - \ref TC_CLOCK_FALLING_EDGE.\r
+ unsigned int clki : 1;\r
+\r
+ //! Clock selection:\n\r
+ //! - \ref TC_CLOCK_SOURCE_TC1;\n\r
+ //! - \ref TC_CLOCK_SOURCE_TC2;\n\r
+ //! - \ref TC_CLOCK_SOURCE_TC3;\n\r
+ //! - \ref TC_CLOCK_SOURCE_TC4;\n\r
+ //! - \ref TC_CLOCK_SOURCE_TC5;\n\r
+ //! - \ref TC_CLOCK_SOURCE_XC0;\n\r
+ //! - \ref TC_CLOCK_SOURCE_XC1;\n\r
+ //! - \ref TC_CLOCK_SOURCE_XC2.\r
+ unsigned int tcclks : 3;\r
+} tc_capture_opt_t;\r
+\r
+//! Parameters when initializing a timer/counter in waveform mode.\r
+typedef struct\r
+{\r
+ //! Channel to initialize.\r
+ unsigned int channel ;\r
+\r
+ //! Software trigger effect on TIOB:\n\r
+ //! - \ref TC_EVT_EFFECT_NOOP;\n\r
+ //! - \ref TC_EVT_EFFECT_SET;\n\r
+ //! - \ref TC_EVT_EFFECT_CLEAR;\n\r
+ //! - \ref TC_EVT_EFFECT_TOGGLE.\r
+ unsigned int bswtrg : 2;\r
+\r
+ //! External event effect on TIOB:\n\r
+ //! - \ref TC_EVT_EFFECT_NOOP;\n\r
+ //! - \ref TC_EVT_EFFECT_SET;\n\r
+ //! - \ref TC_EVT_EFFECT_CLEAR;\n\r
+ //! - \ref TC_EVT_EFFECT_TOGGLE.\r
+ unsigned int beevt : 2;\r
+\r
+ //! RC compare effect on TIOB:\n\r
+ //! - \ref TC_EVT_EFFECT_NOOP;\n\r
+ //! - \ref TC_EVT_EFFECT_SET;\n\r
+ //! - \ref TC_EVT_EFFECT_CLEAR;\n\r
+ //! - \ref TC_EVT_EFFECT_TOGGLE.\r
+ unsigned int bcpc : 2;\r
+\r
+ //! RB compare effect on TIOB:\n\r
+ //! - \ref TC_EVT_EFFECT_NOOP;\n\r
+ //! - \ref TC_EVT_EFFECT_SET;\n\r
+ //! - \ref TC_EVT_EFFECT_CLEAR;\n\r
+ //! - \ref TC_EVT_EFFECT_TOGGLE.\r
+ unsigned int bcpb : 2;\r
+\r
+ //! Software trigger effect on TIOA:\n\r
+ //! - \ref TC_EVT_EFFECT_NOOP;\n\r
+ //! - \ref TC_EVT_EFFECT_SET;\n\r
+ //! - \ref TC_EVT_EFFECT_CLEAR;\n\r
+ //! - \ref TC_EVT_EFFECT_TOGGLE.\r
+ unsigned int aswtrg : 2;\r
+\r
+ //! External event effect on TIOA:\n\r
+ //! - \ref TC_EVT_EFFECT_NOOP;\n\r
+ //! - \ref TC_EVT_EFFECT_SET;\n\r
+ //! - \ref TC_EVT_EFFECT_CLEAR;\n\r
+ //! - \ref TC_EVT_EFFECT_TOGGLE.\r
+ unsigned int aeevt : 2;\r
+\r
+ //! RC compare effect on TIOA:\n\r
+ //! - \ref TC_EVT_EFFECT_NOOP;\n\r
+ //! - \ref TC_EVT_EFFECT_SET;\n\r
+ //! - \ref TC_EVT_EFFECT_CLEAR;\n\r
+ //! - \ref TC_EVT_EFFECT_TOGGLE.\r
+ unsigned int acpc : 2;\r
+\r
+ //! RA compare effect on TIOA:\n\r
+ //! - \ref TC_EVT_EFFECT_NOOP;\n\r
+ //! - \ref TC_EVT_EFFECT_SET;\n\r
+ //! - \ref TC_EVT_EFFECT_CLEAR;\n\r
+ //! - \ref TC_EVT_EFFECT_TOGGLE.\r
+ unsigned int acpa : 2;\r
+\r
+ unsigned int : 1;\r
+\r
+ //! Waveform selection:\n\r
+ //! - \ref TC_WAVEFORM_SEL_UP_MODE;\n\r
+ //! - \ref TC_WAVEFORM_SEL_UP_MODE_RC_TRIGGER;\n\r
+ //! - \ref TC_WAVEFORM_SEL_UPDOWN_MODE;\n\r
+ //! - \ref TC_WAVEFORM_SEL_UPDOWN_MODE_RC_TRIGGER.\r
+ unsigned int wavsel : 2;\r
+\r
+ //! External event trigger enable:\n\r
+ //! - \c FALSE;\n\r
+ //! - \c TRUE.\r
+ unsigned int enetrg : 1;\r
+\r
+ //! External event selection:\n\r
+ //! - \ref TC_EXT_EVENT_SEL_TIOB_INPUT;\n\r
+ //! - \ref TC_EXT_EVENT_SEL_XC0_OUTPUT;\n\r
+ //! - \ref TC_EXT_EVENT_SEL_XC1_OUTPUT;\n\r
+ //! - \ref TC_EXT_EVENT_SEL_XC2_OUTPUT.\r
+ unsigned int eevt : 2;\r
+\r
+ //! External event edge selection:\n\r
+ //! - \ref TC_SEL_NO_EDGE;\n\r
+ //! - \ref TC_SEL_RISING_EDGE;\n\r
+ //! - \ref TC_SEL_FALLING_EDGE;\n\r
+ //! - \ref TC_SEL_EACH_EDGE.\r
+ unsigned int eevtedg : 2;\r
+\r
+ //! Counter clock disable with RC compare:\n\r
+ //! - \c FALSE;\n\r
+ //! - \c TRUE.\r
+ unsigned int cpcdis : 1;\r
+\r
+ //! Counter clock stopped with RC compare:\n\r
+ //! - \c FALSE;\n\r
+ //! - \c TRUE.\r
+ unsigned int cpcstop : 1;\r
+\r
+ //! Burst signal selection:\n\r
+ //! - \ref TC_BURST_NOT_GATED;\n\r
+ //! - \ref TC_BURST_CLK_AND_XC0;\n\r
+ //! - \ref TC_BURST_CLK_AND_XC1;\n\r
+ //! - \ref TC_BURST_CLK_AND_XC2.\r
+ unsigned int burst : 2;\r
+\r
+ //! Clock invert:\n\r
+ //! - \ref TC_CLOCK_RISING_EDGE;\n\r
+ //! - \ref TC_CLOCK_FALLING_EDGE.\r
+ unsigned int clki : 1;\r
+\r
+ //! Clock selection:\n\r
+ //! - \ref TC_CLOCK_SOURCE_TC1;\n\r
+ //! - \ref TC_CLOCK_SOURCE_TC2;\n\r
+ //! - \ref TC_CLOCK_SOURCE_TC3;\n\r
+ //! - \ref TC_CLOCK_SOURCE_TC4;\n\r
+ //! - \ref TC_CLOCK_SOURCE_TC5;\n\r
+ //! - \ref TC_CLOCK_SOURCE_XC0;\n\r
+ //! - \ref TC_CLOCK_SOURCE_XC1;\n\r
+ //! - \ref TC_CLOCK_SOURCE_XC2.\r
+ unsigned int tcclks : 3;\r
+} tc_waveform_opt_t;\r
+\r
+\r
+/*! \brief Reads timer/counter interrupt settings.\r
+ *\r
+ * \param tc Pointer to the TC instance to access.\r
+ * \param channel The TC instance channel to access.\r
+ *\r
+ * \retval >=0 The interrupt enable configuration organized according to \ref tc_interrupt_t.\r
+ * \retval TC_INVALID_ARGUMENT Invalid argument(s).\r
+ */\r
+extern int tc_get_interrupt_settings(volatile avr32_tc_t *tc, unsigned int channel);\r
+\r
+/*! \brief Enables various timer/counter interrupts.\r
+ *\r
+ * \param tc Pointer to the TC instance to access.\r
+ * \param channel The TC instance channel to access.\r
+ * \param bitfield The interrupt enable configuration.\r
+ *\r
+ * \retval 0 Success.\r
+ * \retval TC_INVALID_ARGUMENT Invalid argument(s).\r
+ */\r
+extern int tc_configure_interrupts(volatile avr32_tc_t *tc, unsigned int channel, const tc_interrupt_t *bitfield);\r
+\r
+/*! \brief Selects which external clock to use and how to configure it.\r
+ *\r
+ * \param tc Pointer to the TC instance to access.\r
+ * \param channel The TC instance channel to access.\r
+ * \param ext_clk_sig_src External clock signal selection:\r
+ * \arg \c TC_CH0_EXT_CLK0_SRC_TCLK0;\r
+ * \arg \c TC_CH0_EXT_CLK0_SRC_NO_CLK;\r
+ * \arg \c TC_CH0_EXT_CLK0_SRC_TIOA1;\r
+ * \arg \c TC_CH0_EXT_CLK0_SRC_TIOA2;\r
+ * \arg \c TC_CH1_EXT_CLK1_SRC_TCLK1;\r
+ * \arg \c TC_CH1_EXT_CLK1_SRC_NO_CLK;\r
+ * \arg \c TC_CH1_EXT_CLK1_SRC_TIOA0;\r
+ * \arg \c TC_CH1_EXT_CLK1_SRC_TIOA2;\r
+ * \arg \c TC_CH2_EXT_CLK2_SRC_TCLK2;\r
+ * \arg \c TC_CH2_EXT_CLK2_SRC_NO_CLK;\r
+ * \arg \c TC_CH2_EXT_CLK2_SRC_TIOA0;\r
+ * \arg \c TC_CH2_EXT_CLK2_SRC_TIOA1.\r
+ *\r
+ * \retval 0 Success.\r
+ * \retval TC_INVALID_ARGUMENT Invalid argument(s).\r
+ */\r
+extern int tc_select_external_clock(volatile avr32_tc_t *tc, unsigned int channel, unsigned int ext_clk_sig_src);\r
+\r
+/*! \brief Sets options for timer/counter capture initialization.\r
+ *\r
+ * \param tc Pointer to the TC instance to access.\r
+ * \param opt Options for capture mode.\r
+ *\r
+ * \retval 0 Success.\r
+ * \retval TC_INVALID_ARGUMENT Invalid argument(s).\r
+ */\r
+extern int tc_init_capture(volatile avr32_tc_t *tc, const tc_capture_opt_t *opt);\r
+\r
+/*! \brief Sets options for timer/counter waveform initialization.\r
+ *\r
+ * \param tc Pointer to the TC instance to access.\r
+ * \param opt Options for waveform generation.\r
+ *\r
+ * \retval 0 Success.\r
+ * \retval TC_INVALID_ARGUMENT Invalid argument(s).\r
+ */\r
+extern int tc_init_waveform(volatile avr32_tc_t *tc, const tc_waveform_opt_t *opt);\r
+\r
+/*! \brief Starts a timer/counter.\r
+ *\r
+ * \param tc Pointer to the TC instance to access.\r
+ * \param channel The TC instance channel to access.\r
+ *\r
+ * \retval 0 Success.\r
+ * \retval TC_INVALID_ARGUMENT Invalid argument(s).\r
+ */\r
+extern int tc_start(volatile avr32_tc_t *tc, unsigned int channel);\r
+\r
+/*! \brief Stops a timer/counter.\r
+ *\r
+ * \param tc Pointer to the TC instance to access.\r
+ * \param channel The TC instance channel to access.\r
+ *\r
+ * \retval 0 Success.\r
+ * \retval TC_INVALID_ARGUMENT Invalid argument(s).\r
+ */\r
+extern int tc_stop(volatile avr32_tc_t *tc, unsigned int channel);\r
+\r
+/*! \brief Performs a software trigger: the counter is reset and the clock is started.\r
+ *\r
+ * \param tc Pointer to the TC instance to access.\r
+ * \param channel The TC instance channel to access.\r
+ *\r
+ * \retval 0 Success.\r
+ * \retval TC_INVALID_ARGUMENT Invalid argument(s).\r
+ */\r
+extern int tc_software_trigger(volatile avr32_tc_t *tc, unsigned int channel);\r
+\r
+/*! \brief Asserts a SYNC signal to generate a software trigger and reset all channels.\r
+ *\r
+ * \param tc Pointer to the TC instance to access.\r
+ */\r
+extern void tc_sync_trigger(volatile avr32_tc_t *tc);\r
+\r
+/*! \brief Reads the status register.\r
+ *\r
+ * \param tc Pointer to the TC instance to access.\r
+ * \param channel The TC instance channel to access.\r
+ *\r
+ * \retval >=0 Status register value.\r
+ * \retval TC_INVALID_ARGUMENT Invalid argument(s).\r
+ */\r
+extern int tc_read_sr(volatile avr32_tc_t *tc, unsigned int channel);\r
+\r
+/*! \brief Reads the channel's TC counter and returns the value.\r
+ *\r
+ * \param tc Pointer to the TC instance to access.\r
+ * \param channel The TC instance channel to access.\r
+ *\r
+ * \retval >=0 TC counter value.\r
+ * \retval TC_INVALID_ARGUMENT Invalid argument(s).\r
+ */\r
+extern int tc_read_tc(volatile avr32_tc_t *tc, unsigned int channel);\r
+\r
+/*! \brief Reads the channel's RA register and returns the value.\r
+ *\r
+ * \param tc Pointer to the TC instance to access.\r
+ * \param channel The TC instance channel to access.\r
+ *\r
+ * \retval >=0 RA register value.\r
+ * \retval TC_INVALID_ARGUMENT Invalid argument(s).\r
+ */\r
+extern int tc_read_ra(volatile avr32_tc_t *tc, unsigned int channel);\r
+\r
+/*! \brief Reads the channel's RB register and returns the value.\r
+ *\r
+ * \param tc Pointer to the TC instance to access.\r
+ * \param channel The TC instance channel to access.\r
+ *\r
+ * \retval >=0 RB register value.\r
+ * \retval TC_INVALID_ARGUMENT Invalid argument(s).\r
+ */\r
+extern int tc_read_rb(volatile avr32_tc_t *tc, unsigned int channel);\r
+\r
+/*! \brief Reads the channel's RC register and returns the value.\r
+ *\r
+ * \param tc Pointer to the TC instance to access.\r
+ * \param channel The TC instance channel to access.\r
+ *\r
+ * \retval >=0 RC register value.\r
+ * \retval TC_INVALID_ARGUMENT Invalid argument(s).\r
+ */\r
+extern int tc_read_rc(volatile avr32_tc_t *tc, unsigned int channel);\r
+\r
+/*! \brief Writes a value to the channel's RA register.\r
+ *\r
+ * \param tc Pointer to the TC instance to access.\r
+ * \param channel The TC instance channel to access.\r
+ * \param value Value to write to the RA register.\r
+ *\r
+ * \retval >=0 Written value.\r
+ * \retval TC_INVALID_ARGUMENT Invalid argument(s).\r
+ */\r
+extern int tc_write_ra(volatile avr32_tc_t *tc, unsigned int channel, unsigned short value);\r
+\r
+/*! \brief Writes a value to the channel's RB register.\r
+ *\r
+ * \param tc Pointer to the TC instance to access.\r
+ * \param channel The TC instance channel to access.\r
+ * \param value Value to write to the RB register.\r
+ *\r
+ * \retval >=0 Written value.\r
+ * \retval TC_INVALID_ARGUMENT Invalid argument(s).\r
+ */\r
+extern int tc_write_rb(volatile avr32_tc_t *tc, unsigned int channel, unsigned short value);\r
+\r
+/*! \brief Writes a value to the channel's RC register.\r
+ *\r
+ * \param tc Pointer to the TC instance to access.\r
+ * \param channel The TC instance channel to access.\r
+ * \param value Value to write to the RC register.\r
+ *\r
+ * \retval >=0 Written value.\r
+ * \retval TC_INVALID_ARGUMENT Invalid argument(s).\r
+ */\r
+extern int tc_write_rc(volatile avr32_tc_t *tc, unsigned int channel, unsigned short value);\r
+\r
+\r
+#endif // _TC_H_\r
--- /dev/null
+/*This file has been prepared for Doxygen automatic documentation generation.*/\r
+/*! \file *********************************************************************\r
+ *\r
+ * \brief FreeRTOS and lwIP example for AVR32 UC3.\r
+ *\r
+ * - Compiler: IAR EWAVR32 and GNU GCC for AVR32\r
+ * - Supported devices: All AVR32 devices can be used.\r
+ * - AppNote:\r
+ *\r
+ * \author Atmel Corporation: http://www.atmel.com \n\r
+ * Support email: avr32@atmel.com\r
+ *\r
+ *****************************************************************************/\r
+\r
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of ATMEL may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND\r
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,\r
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\r
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\r
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF\r
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ */\r
+\r
+\r
+#ifndef FREERTOS_CONFIG_H\r
+#define FREERTOS_CONFIG_H\r
+\r
+#include "board.h"\r
+\r
+/*-----------------------------------------------------------\r
+ * Application specific definitions.\r
+ *\r
+ * These definitions should be adjusted for your particular hardware and\r
+ * application requirements.\r
+ *\r
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE\r
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.\r
+ *----------------------------------------------------------*/\r
+\r
+#define configUSE_PREEMPTION 1\r
+#define configUSE_IDLE_HOOK 0\r
+#define configUSE_TICK_HOOK 0\r
+#define configCPU_CLOCK_HZ ( 48000000 ) /* Hz clk gen */\r
+#define configPBA_CLOCK_HZ ( 24000000 )\r
+#define configTICK_RATE_HZ ( ( portTickType ) 1000 )\r
+#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 8 )\r
+#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 256 )\r
+#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 0 ) )\r
+#define configMAX_TASK_NAME_LEN ( 20 )\r
+#define configUSE_TRACE_FACILITY 1\r
+#define configUSE_16_BIT_TICKS 0\r
+#define configIDLE_SHOULD_YIELD 1\r
+\r
+/* Co-routine definitions. */\r
+#define configUSE_CO_ROUTINES 0\r
+#define configMAX_CO_ROUTINE_PRIORITIES ( 0 )\r
+\r
+/* Set the following definitions to 1 to include the API function, or zero\r
+to exclude the API function. */\r
+\r
+#define INCLUDE_vTaskPrioritySet 1\r
+#define INCLUDE_uxTaskPriorityGet 1\r
+#define INCLUDE_vTaskDelete 1\r
+#define INCLUDE_vTaskCleanUpResources 0\r
+#define INCLUDE_vTaskSuspend 1\r
+#define INCLUDE_vTaskDelayUntil 1\r
+#define INCLUDE_vTaskDelay 1\r
+#define INCLUDE_xTaskGetCurrentTaskHandle 1\r
+\r
+/* configTICK_USE_TC is a boolean indicating whether to use a Timer Counter\r
+ for the tick generation. Timer Counter will generate an accurate Tick;\r
+ otherwise the CPU will generate a tick but with time drift\r
+ configTICK_TC_CHANNEL is the TC channel.*/\r
+#define configTICK_USE_TC 1\r
+#define configTICK_TC_CHANNEL 2\r
+\r
+#endif /* FREERTOS_CONFIG_H */\r
--- /dev/null
+/* This source file is part of the ATMEL FREERTOS-0.9.0 Release */\r
+\r
+/*This file has been prepared for Doxygen automatic documentation generation.*/\r
+/*! \file *********************************************************************\r
+ *\r
+ * \brief Basic SMTP Host for AVR32 UC3.\r
+ *\r
+ * - Compiler: GNU GCC for AVR32\r
+ * - Supported devices: All AVR32 devices can be used.\r
+ * - AppNote:\r
+ *\r
+ * \author Atmel Corporation: http://www.atmel.com \n\r
+ * Support email: avr32@atmel.com\r
+ *\r
+ *****************************************************************************/\r
+\r
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of ATMEL may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND\r
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,\r
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\r
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\r
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF\r
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ */\r
+\r
+\r
+/*\r
+ Implements a simplistic SMTP client.\r
+*/\r
+\r
+#if (SMTP_USED == 1)\r
+\r
+#include <string.h>\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "BasicSMTP.h"\r
+\r
+\r
+/* Demo includes. */\r
+#include "AVR32_EMAC.h"\r
+#include "portmacro.h"\r
+#include "partest.h"\r
+\r
+/* lwIP includes. */\r
+#include "lwip/api.h"\r
+#include "lwip/tcpip.h"\r
+#include "lwip/memp.h"\r
+#include "lwip/stats.h"\r
+#include "lwip/opt.h"\r
+#include "lwip/api.h"\r
+#include "lwip/arch.h"\r
+#include "lwip/sys.h"\r
+#include "lwip/sockets.h"\r
+#include "netif/loopif.h"\r
+\r
+/*! SMTP default port */\r
+#define SMTP_PORT 25\r
+/*! SMTP EHLO code answer */\r
+#define SMTP_EHLO_STRING "220"\r
+/*! SMTP end of transmission code answer */\r
+#define SMTP_END_OF_TRANSMISSION_STRING "221"\r
+/*! SMTP OK code answer */\r
+#define SMTP_OK_STRING "250"\r
+/*! SMTP start of transmission code answer */\r
+#define SMTP_START_OF_TRANSMISSION_STRING "354"\r
+/*! SMTP DATA<CRLF> */\r
+#define SMTP_DATA_STRING "DATA\r\n"\r
+/*! SMTP <CRLF>.<CRLF> */\r
+#define SMTP_MAIL_END_STRING "\r\n.\r\n"\r
+/*! SMTP QUIT<CRLFCRLF> */\r
+#define SMTP_QUIT_STRING "QUIT\r\n\r\n"\r
+\r
+\r
+/*! Server address */\r
+portCHAR cServer[] = "192.168.0.1";\r
+\r
+/*! Fill here the ehlo with your SMTP server name */\r
+#error configure SMTP server\r
+char ehlo[] = "EHLO smtp.domain.com\r\n";\r
+\r
+/*! Fill here the mailfrom with your mail address */\r
+#error configure mail sender\r
+char mailfrom[] = "MAIL FROM: <sender@domain.com>\r\n";\r
+\r
+/*! Fill here the mailto with your contact mail address */\r
+#error configure mail receiver\r
+char mailto[] = "RCPT TO: <receiver@domain.com>\r\n";\r
+\r
+/*! Fill here the mailcontent with the mail you want to send */\r
+#error configure mail content\r
+char mailcontent[] ="Subject: *** SPAM ***\r\nFROM: \"Your Name here\" <sender@domain.com>\r\nTO: \"Your Contact here\" <receiver@domain.com>\r\n\r\nSay what you want here.";\r
+\r
+Bool bSendMail = pdTRUE;\r
+portCHAR cTempBuffer[200];\r
+\r
+/*! Basic SMTP Host task definition */\r
+portTASK_FUNCTION( vBasicSMTPHost, pvParameters )\r
+{\r
+ struct sockaddr_in stServeurSockAddr; \r
+ portLONG lRetval;\r
+ portLONG lSocket = -1;\r
+ \r
+ \r
+ for (;;)\r
+ {\r
+ // wait for a signal to send a mail\r
+ while (bSendMail != pdTRUE) vTaskDelay(200);\r
+\r
+ // Set up port\r
+ memset(&stServeurSockAddr, 0, sizeof(stServeurSockAddr));\r
+ stServeurSockAddr.sin_len = sizeof(stServeurSockAddr);\r
+ stServeurSockAddr.sin_addr.s_addr = inet_addr(cServer);\r
+ stServeurSockAddr.sin_port = htons(SMTP_PORT);\r
+ stServeurSockAddr.sin_family = AF_INET;\r
+\r
+ // clear the flag \r
+ bSendMail = pdFALSE;\r
+ \r
+ // socket as a stream\r
+ if ( (lSocket = socket(AF_INET, SOCK_STREAM, 0)) < 0)\r
+ {\r
+ // socket failed, blink a LED and stay here\r
+ for (;;) {\r
+ vParTestToggleLED( 0 );\r
+ vTaskDelay( 200 );\r
+ }\r
+ }\r
+ // connect to the server\r
+ if(connect(lSocket,(struct sockaddr *)&stServeurSockAddr, sizeof(stServeurSockAddr)) < 0)\r
+ {\r
+ // connect failed, blink a LED and stay here\r
+ for (;;) {\r
+ vParTestToggleLED( 1 );\r
+ vTaskDelay( 200 );\r
+ }\r
+ }\r
+ else\r
+ {\r
+//Server: 220 SMTP Ready \r
+ /* wait for SMTP Server answer */\r
+ do\r
+ {\r
+ lRetval = recv(lSocket, cTempBuffer, sizeof(cTempBuffer), 0);\r
+ }while (lRetval <= 0); \r
+ if (strncmp(cTempBuffer, SMTP_EHLO_STRING, sizeof(cTempBuffer)) >= 0)\r
+ {\r
+//Client: EHLO smtp.domain.com\r
+ /* send ehlo */\r
+ send(lSocket, cEhlo, strlen(cEhlo), 0);\r
+//Server: 250 \r
+ /* wait for SMTP Server answer */\r
+ do\r
+ {\r
+ lRetval = recv(lSocket, cTempBuffer, sizeof(cTempBuffer), 0);\r
+ }while (lRetval <= 0); \r
+ if (strncmp(cTempBuffer, SMTP_OK_STRING, sizeof(cTempBuffer)) >= 0)\r
+ {\r
+//Server: 250 HELP\r
+ do\r
+ {\r
+ lRetval = recv(lSocket, cTempBuffer, sizeof(cTempBuffer), 0);\r
+ }while (lRetval <= 0); \r
+//Client: MAIL FROM:<sender@domain.com>\r
+ /* send MAIL FROM */\r
+ send(lSocket, cMailfrom, strlen(cMailfrom), 0); \r
+//Server: 250 OK\r
+ /* wait for SMTP Server answer */\r
+ do\r
+ {\r
+ lRetval = recv(lSocket, cTempBuffer, sizeof(cTempBuffer), 0);\r
+ }while (lRetval <= 0); \r
+ if (strncmp(cTempBuffer, SMTP_OK_STRING, sizeof(cTempBuffer)) >= 0)\r
+ {\r
+//Client: RCPT TO:<receiver@domain.com>\r
+ /* send RCPT TO */\r
+ send(lSocket, cMailto, strlen(cMailto), 0); \r
+//Server: 250 OK\r
+ /* wait for SMTP Server answer */\r
+ do\r
+ {\r
+ lRetval = recv(lSocket, cTempBuffer, sizeof(cTempBuffer), 0);\r
+ }while (lRetval <= 0);\r
+ if (strncmp(cTempBuffer, SMTP_OK_STRING, sizeof(cTempBuffer)) >= 0)\r
+ {\r
+//Client: DATA<CRLF>\r
+ /* send DATA */\r
+ send(lSocket, SMTP_DATA_STRING, 6, 0); \r
+//Server: 354 Start mail input; end with <CRLF>.<CRLF> \r
+ /* wait for SMTP Server answer */\r
+ do\r
+ {\r
+ lRetval = recv(lSocket, cTempBuffer, sizeof(cTempBuffer), 0);\r
+ }while (lRetval <= 0);\r
+ if (strncmp(cTempBuffer, SMTP_START_OF_TRANSMISSION_STRING, sizeof(cTempBuffer)) >= 0)\r
+ {\r
+ /* send content */\r
+ send(lSocket, cMailcontent, strlen(cMailcontent), 0); \r
+//Client: <CRLF>.<CRLF>\r
+ /* send "<CRLF>.<CRLF>" */\r
+ send(lSocket, SMTP_MAIL_END_STRING, 5, 0);\r
+//Server: 250 OK\r
+ /* wait for SMTP Server answer */\r
+ do\r
+ {\r
+ lRetval = recv(lSocket, cTempBuffer, sizeof(cTempBuffer), 0);\r
+ }while (lRetval <= 0);\r
+ if (strncmp(cTempBuffer, SMTP_OK_STRING, sizeof(cTempBuffer)) >= 0)\r
+ {\r
+//Client: QUIT<CRLFCRLF>\r
+ /* send QUIT */\r
+ send(lSocket, SMTP_QUIT_STRING, 8, 0); \r
+//Server: 221 smtp.domain.com closing transmission\r
+ do\r
+ {\r
+ lRetval = recv(lSocket, cTempBuffer, sizeof(cTempBuffer), 0);\r
+ }while (lRetval <= 0); \r
+ if (strncmp(cTempBuffer, SMTP_END_OF_TRANSMISSION_STRING, sizeof(cTempBuffer)) >= 0)\r
+ {\r
+ vParTestSetLED( 3 , pdTRUE );\r
+ }\r
+ }\r
+ }\r
+ } \r
+ }\r
+ } \r
+ /* close socket */\r
+ close(lSocket);\r
+ }\r
+ }\r
+ }\r
+}\r
+#endif\r
--- /dev/null
+/* This header file is part of the ATMEL FREERTOS-0.9.0 Release */\r
+\r
+/*This file has been prepared for Doxygen automatic documentation generation.*/\r
+/*! \file *********************************************************************\r
+ *\r
+ * \brief Basic SMTP Host for AVR32 UC3.\r
+ *\r
+ * - Compiler: GNU GCC for AVR32\r
+ * - Supported devices: All AVR32 devices can be used.\r
+ * - AppNote:\r
+ *\r
+ * \author Atmel Corporation: http://www.atmel.com \n\r
+ * Support email: avr32@atmel.com\r
+ *\r
+ *****************************************************************************/\r
+\r
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of ATMEL may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND\r
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,\r
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\r
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\r
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF\r
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ */\r
+\r
+\r
+#ifndef BASIC_SMTP_SERVER_H\r
+#define BASIC_SMTP_SERVER_H\r
+\r
+#include "portmacro.h"\r
+\r
+\r
+/* The function that implements the SMTP host task. */\r
+portTASK_FUNCTION_PROTO( vBasicSMTPHost, pvParameters );\r
+\r
+\r
+\r
+#endif\r
+\r
--- /dev/null
+/* This source file is part of the ATMEL FREERTOS-0.9.0 Release */\r
+\r
+/*This file has been prepared for Doxygen automatic documentation generation.*/\r
+/*! \file *********************************************************************\r
+ *\r
+ * \brief Basic TFTP Server for AVR32 UC3.\r
+ *\r
+ * - Compiler: GNU GCC for AVR32\r
+ * - Supported devices: All AVR32 devices can be used.\r
+ * - AppNote:\r
+ *\r
+ * \author Atmel Corporation: http://www.atmel.com \n\r
+ * Support email: avr32@atmel.com\r
+ *\r
+ *****************************************************************************/\r
+\r
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of ATMEL may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND\r
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,\r
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\r
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\r
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF\r
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ */\r
+\r
+\r
+/*\r
+ Implements a simplistic TFTP server.\r
+ \r
+ In order to put data on the TFTP server (not over 2048 bytes)\r
+ tftp 192.168.0.2 PUT <src_filename>\r
+ this will copy file from your hard drive to the RAM buffer of the application\r
+\r
+ tftp 192.168.0.2 GET <dst_filename>\r
+ this will copy file from the RAM buffer of the application to your hard drive\r
+ You can then check that src_filename and dst_filename are identical \r
+*/\r
+\r
+#if (TFTP_USED == 1)\r
+\r
+#include <string.h>\r
+\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "partest.h"\r
+#include "BasicTFTP.h"\r
+\r
+\r
+/* Demo includes. */\r
+#include "AVR32_EMAC.h"\r
+#include "portmacro.h"\r
+\r
+/* lwIP includes. */\r
+#include "lwip/api.h"\r
+#include "lwip/tcpip.h"\r
+#include "lwip/memp.h"\r
+#include "lwip/stats.h"\r
+#include "lwip/opt.h"\r
+#include "lwip/api.h"\r
+#include "lwip/arch.h"\r
+#include "lwip/sys.h"\r
+#include "netif/loopif.h"\r
+#include "lwip/sockets.h"\r
+\r
+#define O_WRONLY 1\r
+#define O_RDONLY 2\r
+\r
+\r
+/* The port on which we listen. */\r
+#define TFTP_PORT ( 69 )\r
+\r
+/* Delay on close error. */\r
+#define TFTP_DELAY ( 10 )\r
+\r
+/* Delay on bind error. */\r
+#define TFTP_ERROR_DELAY ( 40 )\r
+\r
+#define TFTP_LED ( 4 )\r
+\r
+char data_out[SEGSIZE+sizeof(struct tftphdr)];\r
+char data_in[SEGSIZE+sizeof(struct tftphdr)];\r
+\r
+//struct tftp_server *server;\r
+\r
+/*------------------------------------------------------------*/\r
+static char * errmsg[] = {\r
+ "Undefined error code", // 0 nothing defined\r
+ "File not found", // 1 TFTP_ENOTFOUND \r
+ "Access violation", // 2 TFTP_EACCESS \r
+ "Disk full or allocation exceeded", // 3 TFTP_ENOSPACE \r
+ "Illegal TFTP operation", // 4 TFTP_EBADOP \r
+ "Unknown transfer ID", // 5 TFTP_EBADID \r
+ "File already exists", // 6 TFTP_EEXISTS \r
+ "No such user", // 7 TFTP_ENOUSER \r
+};\r
+\r
+\r
+/* Send an error packet to the client */\r
+static void \r
+tftpd_send_error(int s, struct tftphdr * reply, int err,\r
+ struct sockaddr_in *from_addr, int from_len)\r
+{\r
+ if ( ( 0 <= err ) && ( sizeof(errmsg)/sizeof(errmsg[0]) > err) ) {\r
+ reply->th_opcode = htons(ERROR);\r
+ reply->th_code = htons(err);\r
+ if ( (0 > err) || (sizeof(errmsg)/sizeof(errmsg[0]) <= err) )\r
+ err = 0; // Do not copy a random string from hyperspace\r
+ strcpy(reply->th_msg, errmsg[err]);\r
+ sendto(s, reply, 4+strlen(reply->th_msg)+1, 0, \r
+ (struct sockaddr *)from_addr, from_len);\r
+ }\r
+}\r
+\r
+portCHAR cRamBuffer[2048];\r
+int lCurrentBlock = 0;\r
+int lTotalLength = 0;\r
+\r
+\r
+int tftpd_close_data_file(int fd)\r
+{\r
+ lCurrentBlock = 0;\r
+ return (5);\r
+}\r
+\r
+int tftpd_open_data_file(int fd, int mode)\r
+{\r
+ lCurrentBlock = 0; \r
+ return (5);\r
+}\r
+\r
+int tftpd_read_data_file(int fd, portCHAR * buffer, int length)\r
+{\r
+int lReturnValue;\r
+\r
+ if ((lTotalLength -= length) >= 0) {\r
+ lReturnValue = length;\r
+ }\r
+ else\r
+ {\r
+ lReturnValue = lTotalLength + length;\r
+ lTotalLength = 0;\r
+ }\r
+ memcpy(buffer, &cRamBuffer[lCurrentBlock * SEGSIZE], lReturnValue);\r
+ lCurrentBlock++;\r
+ return (lReturnValue);\r
+}\r
+\r
+//\r
+// callback to store data to the RAM buffer\r
+//\r
+int tftpd_write_data_file(int fd, portCHAR * buffer, int length)\r
+{\r
+ lTotalLength += length;\r
+ memcpy(&cRamBuffer[lCurrentBlock * SEGSIZE], buffer, length);\r
+ lCurrentBlock++;\r
+ return (length);\r
+}\r
+\r
+//\r
+// Receive a file from the client\r
+//\r
+static void\r
+tftpd_write_file(struct tftphdr *hdr,\r
+ struct sockaddr_in *from_addr, int from_len)\r
+{\r
+\r
+ struct tftphdr *reply = (struct tftphdr *)data_out;\r
+ struct tftphdr *response = (struct tftphdr *)data_in;\r
+ int fd, len, ok, tries, closed, data_len, s;\r
+ unsigned short block;\r
+ struct timeval timeout;\r
+ fd_set fds;\r
+ int total_timeouts = 0;\r
+ struct sockaddr_in client_addr, local_addr;\r
+ int client_len;\r
+\r
+\r
+ s = socket(AF_INET, SOCK_DGRAM, 0);\r
+ if (s < 0) {\r
+ return;\r
+ }\r
+\r
+ memset((char *)&local_addr, 0, sizeof(local_addr));\r
+ local_addr.sin_family = AF_INET;\r
+ local_addr.sin_len = sizeof(local_addr);\r
+ local_addr.sin_addr.s_addr = htonl(INADDR_ANY);\r
+ local_addr.sin_port = htons(INADDR_ANY);\r
+\r
+ if (bind(s, (struct sockaddr *)&local_addr, sizeof(local_addr)) < 0) {\r
+ // Problem setting up my end\r
+ close(s);\r
+ return;\r
+ }\r
+\r
+ if ((fd = tftpd_open_data_file((int)hdr->th_stuff, O_WRONLY)) < 0) {\r
+ tftpd_send_error(s,reply,TFTP_ENOTFOUND,from_addr, from_len);\r
+ close(s);\r
+ return;\r
+ }\r
+\r
+ ok = pdTRUE;\r
+ closed = pdFALSE;\r
+ block = 0;\r
+ while (ok) {\r
+ // Send ACK telling client he can send data\r
+ reply->th_opcode = htons(ACK);\r
+ reply->th_block = htons(block++); // postincrement\r
+ for (tries = 0; tries < TFTP_RETRIES_MAX; tries++) {\r
+ sendto(s, reply, 4, 0, (struct sockaddr *)from_addr, from_len);\r
+ repeat_select:\r
+ timeout.tv_sec = TFTP_TIMEOUT_PERIOD;\r
+ timeout.tv_usec = 0;\r
+ FD_ZERO(&fds);\r
+ FD_SET(s, &fds);\r
+ vParTestToggleLED( TFTP_LED );\r
+ if (lwip_select(s+1, &fds, 0, 0, &timeout) <= 0) {\r
+ if (++total_timeouts > TFTP_TIMEOUT_MAX) {\r
+ tftpd_send_error(s,reply,TFTP_EBADOP,from_addr, from_len);\r
+ ok = pdFALSE;\r
+ break;\r
+ }\r
+ continue; // retry the send, using up one retry.\r
+ }\r
+ vParTestToggleLED( TFTP_LED );\r
+ // Some data has arrived\r
+ data_len = sizeof(data_in);\r
+ client_len = sizeof(client_addr);\r
+ if ((data_len = recvfrom(s, data_in, data_len, 0, \r
+ (struct sockaddr *)&client_addr, &client_len)) < 0) {\r
+ // What happened? No data here!\r
+ continue; // retry the send, using up one retry.\r
+ }\r
+ if (ntohs(response->th_opcode) == DATA &&\r
+ ntohs(response->th_block) < block) {\r
+ // Then it is repeat DATA with an old block; listen again,\r
+ // but do not repeat sending the current ack, and do not\r
+ // use up a retry count. (we do re-send the ack if\r
+ // subsequently we time out)\r
+ goto repeat_select;\r
+ }\r
+ if (ntohs(response->th_opcode) == DATA &&\r
+ ntohs(response->th_block) == block) {\r
+ // Good data - write to file\r
+ len = tftpd_write_data_file(fd, response->th_data, data_len-4);\r
+ if (len < (data_len-4)) {\r
+ // File is "full"\r
+ tftpd_send_error(s,reply,TFTP_ENOSPACE,\r
+ from_addr, from_len); \r
+ ok = pdFALSE; // Give up\r
+ break; // out of the retries loop\r
+ }\r
+ if (data_len < (SEGSIZE+4)) {\r
+ // End of file\r
+ closed = pdTRUE;\r
+ ok = pdFALSE;\r
+ vParTestSetLED( 0 , 0 );\r
+\r
+ if (tftpd_close_data_file(fd) == -1) {\r
+ tftpd_send_error(s,reply,TFTP_EACCESS,\r
+ from_addr, from_len);\r
+\r
+ break; // out of the retries loop\r
+ }\r
+ // Exception to the loop structure: we must ACK the last\r
+ // packet, the one that implied EOF:\r
+ reply->th_opcode = htons(ACK);\r
+ reply->th_block = htons(block++); // postincrement\r
+ sendto(s, reply, 4, 0, (struct sockaddr *)from_addr, from_len);\r
+ break; // out of the retries loop\r
+ }\r
+ // Happy! Break out of the retries loop.\r
+ break;\r
+ }\r
+ } // End of the retries loop.\r
+ if (TFTP_RETRIES_MAX <= tries) {\r
+ tftpd_send_error(s,reply,TFTP_EBADOP,from_addr, from_len);\r
+ ok = pdFALSE;\r
+ }\r
+ }\r
+ close(s);\r
+ if (!closed) {\r
+ tftpd_close_data_file(fd);\r
+ }\r
+}\r
+\r
+\r
+//\r
+// Send a file to the client\r
+//\r
+static void\r
+tftpd_read_file(struct tftphdr *hdr,\r
+ struct sockaddr_in *from_addr, int from_len)\r
+{\r
+ struct tftphdr *reply = (struct tftphdr *)data_out;\r
+ struct tftphdr *response = (struct tftphdr *)data_in;\r
+ int fd, len, tries, ok, data_len, s;\r
+ unsigned short block;\r
+ struct timeval timeout;\r
+ fd_set fds;\r
+ int total_timeouts = 0;\r
+ struct sockaddr_in client_addr, local_addr;\r
+ int client_len;\r
+\r
+ s = socket(AF_INET, SOCK_DGRAM, 0);\r
+ if (s < 0) {\r
+ return;\r
+ }\r
+ memset((char *)&local_addr, 0, sizeof(local_addr));\r
+ local_addr.sin_family = AF_INET;\r
+ local_addr.sin_len = sizeof(local_addr);\r
+ local_addr.sin_addr.s_addr = htonl(INADDR_ANY);\r
+ local_addr.sin_port = htons(INADDR_ANY);\r
+ if (bind(s, (struct sockaddr *)&local_addr, sizeof(local_addr)) < 0) {\r
+ // Problem setting up my end\r
+ close(s);\r
+ return;\r
+ }\r
+ if ((fd = tftpd_open_data_file((int)hdr->th_stuff, O_RDONLY)) < 0) {\r
+ tftpd_send_error(s,reply,TFTP_ENOTFOUND,from_addr, from_len);\r
+ close(s);\r
+ return;\r
+ }\r
+ block = 0;\r
+ ok = pdTRUE;\r
+ while (ok) {\r
+ // Read next chunk of file\r
+ len = tftpd_read_data_file(fd, reply->th_data, SEGSIZE);\r
+ reply->th_block = htons(++block); // preincrement\r
+ reply->th_opcode = htons(DATA);\r
+ for (tries = 0; tries < TFTP_RETRIES_MAX; tries++) {\r
+ if (sendto(s, reply, 4+len, 0,\r
+ (struct sockaddr *)from_addr, from_len) < 0) {\r
+ // Something went wrong with the network!\r
+ ok = pdFALSE;\r
+ break;\r
+ }\r
+ repeat_select:\r
+ timeout.tv_sec = TFTP_TIMEOUT_PERIOD;\r
+ timeout.tv_usec = 0;\r
+ FD_ZERO(&fds);\r
+ FD_SET(s, &fds);\r
+ vParTestToggleLED( TFTP_LED );\r
+ if (select(s+1, &fds, 0, 0, &timeout) <= 0) {\r
+ if (++total_timeouts > TFTP_TIMEOUT_MAX) {\r
+ tftpd_send_error(s,reply,TFTP_EBADOP,from_addr, from_len);\r
+ ok = pdFALSE;\r
+ break;\r
+ }\r
+ continue; // retry the send, using up one retry.\r
+ }\r
+ vParTestToggleLED( TFTP_LED );\r
+ data_len = sizeof(data_in);\r
+ client_len = sizeof(client_addr);\r
+ if ((data_len = recvfrom(s, data_in, data_len, 0, \r
+ (struct sockaddr *)&client_addr,\r
+ &client_len)) < 0) {\r
+ // What happened? Maybe someone lied to us...\r
+ continue; // retry the send, using up one retry.\r
+ }\r
+ if ((ntohs(response->th_opcode) == ACK) &&\r
+ (ntohs(response->th_block) < block)) {\r
+ // Then it is a repeat ACK for an old block; listen again,\r
+ // but do not repeat sending the current block, and do not\r
+ // use up a retry count. (we do re-send the data if\r
+ // subsequently we time out)\r
+ goto repeat_select;\r
+ }\r
+ if ((ntohs(response->th_opcode) == ACK) &&\r
+ (ntohs(response->th_block) == block)) {\r
+ // Happy! Break out of the retries loop.\r
+ break;\r
+ }\r
+ } // End of the retries loop.\r
+ if (TFTP_RETRIES_MAX <= tries) {\r
+ tftpd_send_error(s,reply,TFTP_EBADOP,from_addr, from_len);\r
+ ok = pdFALSE;\r
+ }\r
+ if (len < SEGSIZE) {\r
+ break; // That's end of file then.\r
+ }\r
+ }\r
+ close(s);\r
+ tftpd_close_data_file(fd);\r
+}\r
+\r
+\r
+\r
+portTASK_FUNCTION( vBasicTFTPServer, pvParameters )\r
+{\r
+ int lSocket;\r
+ int lDataLen, lRecvLen, lFromLen;\r
+ struct sockaddr_in sLocalAddr, sFromAddr;\r
+ portCHAR cData[SEGSIZE+sizeof(struct tftphdr)];\r
+ struct tftphdr *sHdr = (struct tftphdr *)cData;\r
+\r
+ // Set up port\r
+ // Network order in info; host order in server:\r
+\r
+ for (;;) {\r
+ // Create socket\r
+ lSocket = socket(AF_INET, SOCK_DGRAM, 0);\r
+ if (lSocket < 0) {\r
+ return;\r
+ }\r
+ memset((char *)&sLocalAddr, 0, sizeof(sLocalAddr));\r
+ sLocalAddr.sin_family = AF_INET;\r
+ sLocalAddr.sin_len = sizeof(sLocalAddr);\r
+ sLocalAddr.sin_addr.s_addr = htonl(INADDR_ANY);\r
+ sLocalAddr.sin_port = TFTP_PORT;\r
+\r
+ if (bind(lSocket, (struct sockaddr *)&sLocalAddr, sizeof(sLocalAddr)) < 0) {\r
+ // Problem setting up my end\r
+ close(lSocket);\r
+ return;\r
+ }\r
+\r
+\r
+ lRecvLen = sizeof(cData);\r
+ lFromLen = sizeof(sFromAddr);\r
+ lDataLen = recvfrom(lSocket, sHdr, lRecvLen, 0,\r
+ (struct sockaddr *)&sFromAddr, &lFromLen);\r
+ vParTestSetLED( TFTP_LED , pdTRUE );\r
+ close(lSocket); // so that other servers can bind to the TFTP socket\r
+\r
+ if ( lDataLen < 0) {\r
+\r
+ } else {\r
+ switch (ntohs(sHdr->th_opcode)) {\r
+ case WRQ:\r
+ tftpd_write_file(sHdr, &sFromAddr, lFromLen);\r
+ vParTestSetLED( TFTP_LED , pdFALSE );\r
+ break;\r
+ case RRQ:\r
+ tftpd_read_file(sHdr, &sFromAddr, lFromLen);\r
+ vParTestSetLED( TFTP_LED , pdFALSE );\r
+ break;\r
+ case ACK:\r
+ case DATA:\r
+ case ERROR:\r
+ vParTestSetLED( TFTP_LED , pdFALSE );\r
+ // Ignore\r
+ break;\r
+ default:\r
+ for(;;)\r
+ {\r
+ vParTestToggleLED( TFTP_LED );\r
+ vTaskDelay(200); \r
+ }\r
+ }\r
+ }\r
+ }\r
+}\r
+#endif\r
--- /dev/null
+/* This header file is part of the ATMEL FREERTOS-0.9.0 Release */\r
+\r
+/*This file has been prepared for Doxygen automatic documentation generation.*/\r
+/*! \file *********************************************************************\r
+ *\r
+ * \brief Basic TFTP Server for AVR32 UC3.\r
+ *\r
+ * - Compiler: GNU GCC for AVR32\r
+ * - Supported devices: All AVR32 devices can be used.\r
+ * - AppNote:\r
+ *\r
+ * \author Atmel Corporation: http://www.atmel.com \n\r
+ * Support email: avr32@atmel.com\r
+ *\r
+ *****************************************************************************/\r
+\r
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of ATMEL may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND\r
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,\r
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\r
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\r
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF\r
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ */\r
+\r
+\r
+#ifndef BASIC_TFTP_SERVER_H\r
+#define BASIC_TFTP_SERVER_H\r
+\r
+#include "portmacro.h"\r
+\r
+/* tftp_support.h */\r
+\r
+/*\r
+ * File transfer modes\r
+ */\r
+#define TFTP_NETASCII 0 // Text files\r
+#define TFTP_OCTET 1 // Binary files\r
+\r
+/*\r
+ * Errors\r
+ */\r
+\r
+// These initial 7 are passed across the net in "ERROR" packets.\r
+#define TFTP_ENOTFOUND 1 /* file not found */\r
+#define TFTP_EACCESS 2 /* access violation */\r
+#define TFTP_ENOSPACE 3 /* disk full or allocation exceeded */\r
+#define TFTP_EBADOP 4 /* illegal TFTP operation */\r
+#define TFTP_EBADID 5 /* unknown transfer ID */\r
+#define TFTP_EEXISTS 6 /* file already exists */\r
+#define TFTP_ENOUSER 7 /* no such user */\r
+// These extensions are return codes in our API, *never* passed on the net.\r
+#define TFTP_TIMEOUT 8 /* operation timed out */\r
+#define TFTP_NETERR 9 /* some sort of network error */\r
+#define TFTP_INVALID 10 /* invalid parameter */\r
+#define TFTP_PROTOCOL 11 /* protocol violation */\r
+#define TFTP_TOOLARGE 12 /* file is larger than buffer */\r
+\r
+#define TFTP_TIMEOUT_PERIOD 5 // Seconds between retries\r
+#define TFTP_TIMEOUT_MAX 50 // Max timeouts over all blocks\r
+#define TFTP_RETRIES_MAX 5 // retries per block before giving up\r
+\r
+/* netdb.h */\r
+// Internet services\r
+struct servent {\r
+char *s_name; /* official service name */\r
+char **s_aliases; /* alias list */\r
+int s_port; /* port number */\r
+char *s_proto; /* protocol to use */\r
+};\r
+\r
+/* arpa/tftp.h */\r
+\r
+/*\r
+ * Trivial File Transfer Protocol (IEN-133)\r
+ */\r
+#define SEGSIZE 512 /* data segment size */\r
+\r
+/*\r
+ * Packet types.\r
+ */\r
+\r
+#define th_block th_u.tu_block\r
+#define th_code th_u.tu_code\r
+#define th_stuff th_u.tu_stuff\r
+#define th_msg th_data\r
+\r
+/*\r
+ * Error codes.\r
+ */\r
+#define EUNDEF 0 /* not defined */\r
+#define ENOTFOUND 1 /* file not found */\r
+#define EACCESS 2 /* access violation */\r
+#define ENOSPACE 3 /* disk full or allocation exceeded */\r
+#define EBADOP 4 /* illegal TFTP operation */\r
+#define EBADID 5 /* unknown transfer ID */\r
+#define EEXISTS 6 /* file already exists */\r
+#define ENOUSER 7 /* no such user */\r
+\r
+\r
+\r
+#define RRQ 01 /* read request */\r
+#define WRQ 02 /* write request */\r
+#define DATA 03 /* data packet */\r
+#define ACK 04 /* acknowledgement */\r
+#define ERROR 05 /* error code */\r
+\r
+struct tftphdr {\r
+ short th_opcode; /* packet type */\r
+ union {\r
+ unsigned short tu_block; /* block # */\r
+ short tu_code; /* error code */\r
+ char tu_stuff[1]; /* request packet stuff */\r
+ } __attribute__ ((packed)) th_u;\r
+ char th_data[1]; /* data or error string */\r
+} __attribute__ ((packed));\r
+\r
+\r
+/* The function that implements the TFTP server task. */\r
+portTASK_FUNCTION_PROTO( vBasicTFTPServer, pvParameters );\r
+\r
+\r
+\r
+#endif\r
+\r
--- /dev/null
+/* This source file is part of the ATMEL FREERTOS-0.9.0 Release */\r
+\r
+/*This file has been prepared for Doxygen automatic documentation generation.*/\r
+/*! \file *********************************************************************\r
+ *\r
+ * \brief Basic WEB Server for AVR32 UC3.\r
+ *\r
+ * - Compiler: GNU GCC for AVR32\r
+ * - Supported devices: All AVR32 devices can be used.\r
+ * - AppNote:\r
+ *\r
+ * \author Atmel Corporation: http://www.atmel.com \n\r
+ * Support email: avr32@atmel.com\r
+ *\r
+ *****************************************************************************/\r
+\r
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of ATMEL may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND\r
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,\r
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\r
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\r
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF\r
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ */\r
+\r
+\r
+/*\r
+ Implements a simplistic WEB server. Every time a connection is made and\r
+ data is received a dynamic page that shows the current FreeRTOS.org kernel \r
+ statistics is generated and returned. The connection is then closed.\r
+\r
+ This file was adapted from a FreeRTOS lwIP slip demo supplied by a third\r
+ party.\r
+*/\r
+\r
+#if (HTTP_USED == 1)\r
+\r
+\r
+/* Standard includes. */\r
+#include <stdio.h>\r
+#include <string.h>\r
+#include <fcntl.h>\r
+\r
+#include "conf_eth.h"\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "semphr.h"\r
+#include "partest.h"\r
+#include "serial.h"\r
+\r
+/* Demo includes. */\r
+/* Demo app includes. */\r
+#include "AVR32_EMAC.h"\r
+#include "portmacro.h"\r
+\r
+/* lwIP includes. */\r
+#include "lwip/api.h" \r
+#include "lwip/tcpip.h"\r
+#include "lwip/memp.h" \r
+#include "lwip/stats.h"\r
+#include "netif/loopif.h"\r
+\r
+/* ethernet includes */\r
+#include "ethernet.h"\r
+\r
+/*! The size of the buffer in which the dynamic WEB page is created. */\r
+#define webMAX_PAGE_SIZE 512\r
+\r
+/*! Standard GET response. */\r
+#define webHTTP_OK "HTTP/1.0 200 OK\r\nContent-type: text/html\r\n\r\n"\r
+\r
+/*! The port on which we listen. */\r
+#define webHTTP_PORT ( 80 )\r
+\r
+/*! Delay on close error. */\r
+#define webSHORT_DELAY ( 10 )\r
+\r
+/*! Format of the dynamic page that is returned on each connection. */\r
+#define webHTML_START \\r
+"<html>\\r
+<head>\\r
+</head>\\r
+<BODY onLoad=\"window.setTimeout("location.href='index.html'",1000)\" bgcolor=\"#FFFFFF\" text=\"#2477E6\">\\r
+\r\nPage Hits = "\r
+\r
+#define webHTML_END \\r
+"\r\n</pre>\\r
+\r\n</font></BODY>\\r
+</html>"\r
+\r
+portCHAR cDynamicPage[ webMAX_PAGE_SIZE ];\r
+portCHAR cPageHits[ 11 ];\r
+\r
+\r
+/*! Function to process the current connection */\r
+static void prvweb_ParseHTMLRequest( struct netconn *pxNetCon );\r
+\r
+\r
+/*! \brief WEB server main task\r
+ * check for incoming connection and process it\r
+ *\r
+ * \param pvParameters Input. Not Used.\r
+ *\r
+ */\r
+portTASK_FUNCTION( vBasicWEBServer, pvParameters )\r
+{\r
+struct netconn *pxHTTPListener, *pxNewConnection;\r
+\r
+ /* Create a new tcp connection handle */\r
+ pxHTTPListener = netconn_new( NETCONN_TCP );\r
+ netconn_bind(pxHTTPListener, NULL, webHTTP_PORT );\r
+ netconn_listen( pxHTTPListener );\r
+\r
+ /* Loop forever */\r
+ for( ;; )\r
+ {\r
+ /* Wait for a first connection. */\r
+ pxNewConnection = netconn_accept(pxHTTPListener);\r
+ vParTestSetLED(webCONN_LED, pdTRUE);\r
+\r
+ if(pxNewConnection != NULL)\r
+ {\r
+ prvweb_ParseHTMLRequest(pxNewConnection);\r
+ }/* end if new connection */\r
+\r
+ vParTestSetLED(webCONN_LED, pdFALSE);\r
+\r
+ } /* end infinite loop */\r
+}\r
+\r
+\r
+/*! \brief parse the incoming request\r
+ * parse the HTML request and send file\r
+ *\r
+ * \param pxNetCon Input. The netconn to use to send and receive data.\r
+ *\r
+ */\r
+static void prvweb_ParseHTMLRequest( struct netconn *pxNetCon )\r
+{\r
+struct netbuf *pxRxBuffer;\r
+portCHAR *pcRxString;\r
+unsigned portSHORT usLength;\r
+static unsigned portLONG ulPageHits = 0;\r
+\r
+ /* We expect to immediately get data. */\r
+ pxRxBuffer = netconn_recv( pxNetCon );\r
+\r
+ if( pxRxBuffer != NULL )\r
+ {\r
+ /* Where is the data? */\r
+ netbuf_data( pxRxBuffer, ( void * ) &pcRxString, &usLength );\r
+\r
+ /* Is this a GET? We don't handle anything else. */\r
+ if( !strncmp( pcRxString, "GET", 3 ) )\r
+ {\r
+ pcRxString = cDynamicPage;\r
+\r
+ /* Update the hit count. */\r
+ ulPageHits++;\r
+ sprintf( cPageHits, "%d", (int)ulPageHits );\r
+\r
+ /* Write out the HTTP OK header. */\r
+ netconn_write( pxNetCon, webHTTP_OK, (u16_t) strlen( webHTTP_OK ), NETCONN_COPY );\r
+\r
+ /* Generate the dynamic page... First the page header. */\r
+ strcpy( cDynamicPage, webHTML_START );\r
+\r
+ /* ... Then the hit count... */\r
+ strcat( cDynamicPage, cPageHits );\r
+ strcat( cDynamicPage, "<p><pre>Task State Priority Stack #<br>************************************************<br>" );\r
+\r
+ /* ... Then the list of tasks and their status... */\r
+ vTaskList( ( signed portCHAR * ) cDynamicPage + strlen( cDynamicPage ) );\r
+\r
+ /* ... Finally the page footer. */\r
+ strcat( cDynamicPage, webHTML_END );\r
+\r
+ /* Write out the dynamically generated page. */\r
+ netconn_write( pxNetCon, cDynamicPage, (u16_t) strlen( cDynamicPage ), NETCONN_COPY );\r
+ }\r
+ netbuf_delete( pxRxBuffer );\r
+ }\r
+\r
+ netconn_close( pxNetCon );\r
+ netconn_delete( pxNetCon );\r
+}\r
+\r
+#endif\r
+\r
--- /dev/null
+/* This header file is part of the ATMEL FREERTOS-0.9.0 Release */\r
+\r
+/*This file has been prepared for Doxygen automatic documentation generation.*/\r
+/*! \file *********************************************************************\r
+ *\r
+ * \brief Basic WEB Server for AVR32 UC3.\r
+ *\r
+ * - Compiler: GNU GCC for AVR32\r
+ * - Supported devices: All AVR32 devices can be used.\r
+ * - AppNote:\r
+ *\r
+ * \author Atmel Corporation: http://www.atmel.com \n\r
+ * Support email: avr32@atmel.com\r
+ *\r
+ *****************************************************************************/\r
+\r
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of ATMEL may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND\r
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,\r
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\r
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\r
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF\r
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ */\r
+\r
+\r
+#ifndef BASIC_WEB_SERVER_H\r
+#define BASIC_WEB_SERVER_H\r
+\r
+#include "portmacro.h"\r
+\r
+\r
+/*! \brief WEB server main task\r
+ *\r
+ * \param pvParameters Input. Not Used.\r
+ *\r
+ */\r
+portTASK_FUNCTION_PROTO( vBasicWEBServer, pvParameters );\r
+\r
+#endif\r
+\r
--- /dev/null
+/* This header file is part of the ATMEL FREERTOS-0.9.0 Release */\r
+\r
+/*This file has been prepared for Doxygen automatic documentation generation.*/\r
+/*! \file *********************************************************************\r
+ *\r
+ * \brief EMAC abstraction layer for AVR32 UC3.\r
+ *\r
+ * - Compiler: GNU GCC for AVR32\r
+ * - Supported devices: All AVR32 devices can be used.\r
+ * - AppNote:\r
+ *\r
+ * \author Atmel Corporation: http://www.atmel.com \n\r
+ * Support email: avr32@atmel.com\r
+ *\r
+ *****************************************************************************/\r
+\r
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of ATMEL may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND\r
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,\r
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\r
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\r
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF\r
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ */\r
+\r
+#ifndef AVR32_CONF_EMAC_H\r
+#define AVR32_CONF_EMAC_H\r
+\r
+#include "lwip/opt.h"\r
+\r
+/*! Number of receive buffers */\r
+#define NB_RX_BUFFERS 20\r
+\r
+/*! USE_RMII_INTERFACE must be defined as 1 to use an RMII interface, or 0\r
+to use an MII interface. */\r
+#define USE_RMII_INTERFACE 1\r
+\r
+/*! Number of Transmit buffers */\r
+#define NB_TX_BUFFERS ( MEMP_NUM_PBUF / 2 )\r
+\r
+/*! Size of each Transmit buffer. */\r
+#define ETH_TX_BUFFER_SIZE 1024 //( PBUF_POOL_BUFSIZE )\r
+\r
+#endif //* AVR32_CONF_EMAC_H\r
--- /dev/null
+/* This source file is part of the ATMEL FREERTOS-0.9.0 Release */\r
+\r
+/*This file has been prepared for Doxygen automatic documentation generation.*/\r
+/*! \file *********************************************************************\r
+ *\r
+ * \brief EMAC abstraction layer for AVR32 UC3.\r
+ *\r
+ * - Compiler: GNU GCC for AVR32\r
+ * - Supported devices: All AVR32 devices with a MACB can be used.\r
+ * - AppNote:\r
+ *\r
+ * \author Atmel Corporation: http://www.atmel.com \n\r
+ * Support email: avr32@atmel.com\r
+ *\r
+ *****************************************************************************/\r
+\r
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of ATMEL may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND\r
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,\r
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\r
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\r
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF\r
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ */\r
+\r
+\r
+/*\r
+ * Interrupt driven driver for the EMAC peripheral. This driver is not\r
+ * reentrant, re-entrancy is handled by a semaphore at the network interface\r
+ * level. \r
+ */\r
+\r
+\r
+/* Standard includes. */\r
+#include <stdio.h>\r
+#include <string.h>\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "semphr.h"\r
+#include "task.h"\r
+\r
+/* Demo app includes. */\r
+#include "AVR32_EMAC.h"\r
+#include "AVR32_CONF_EMAC.h"\r
+#include "DP83848.h"\r
+#include "intc.h"\r
+\r
+/* Hardware specific includes. */\r
+#include "gpio.h"\r
+\r
+/* Size of each receive buffer - DO NOT CHANGE. */\r
+#define ETH_RX_BUFFER_SIZE 128\r
+\r
+/* The buffer addresses written into the descriptors must be aligned so the\r
+last few bits are zero. These bits have special meaning for the EMAC\r
+peripheral and cannot be used as part of the address. */\r
+#define emacADDRESS_MASK ( ( unsigned portLONG ) 0xFFFFFFFC )\r
+\r
+/* Bit used within the address stored in the descriptor to mark the last\r
+descriptor in the array. */\r
+#define emacRX_WRAP_BIT ( ( unsigned portLONG ) 0x02 )\r
+\r
+\r
+/* A short delay is used to wait for a buffer to become available, should\r
+one not be immediately available when trying to transmit a frame. */\r
+#define emacBUFFER_WAIT_DELAY ( 2 )\r
+#define emacMAX_WAIT_CYCLES ( ( portBASE_TYPE ) ( configTICK_RATE_HZ / 40 ) )\r
+\r
+/* The time to block waiting for input. */\r
+#define emacBLOCK_TIME_WAITING_FOR_INPUT ( ( portTickType ) 100 )\r
+\r
+/* Misc defines. */\r
+#define emacNO_DELAY ( 0 )\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Buffer written to by the EMAC DMA. Must be aligned as described by the\r
+comment above the emacADDRESS_MASK definition. */\r
+static volatile portCHAR pcRxBuffer[ NB_RX_BUFFERS * ETH_RX_BUFFER_SIZE ] __attribute__ ((aligned (8)));\r
+\r
+/* Buffer read by the EMAC DMA. Must be aligned as described by the comment\r
+above the emacADDRESS_MASK definition. */\r
+static portCHAR pcTxBuffer[ NB_TX_BUFFERS * ETH_TX_BUFFER_SIZE ] __attribute__ ((aligned (8)));\r
+\r
+/* Descriptors used to communicate between the program and the EMAC peripheral.\r
+These descriptors hold the locations and state of the Rx and Tx buffers. */\r
+static volatile AVR32_TxTdDescriptor xTxDescriptors[ NB_TX_BUFFERS ];\r
+static volatile AVR32_RxTdDescriptor xRxDescriptors[ NB_RX_BUFFERS ];\r
+\r
+/* The IP and Ethernet addresses are read from the header files. */\r
+portCHAR cMACAddress[ 6 ] = { emacETHADDR0, emacETHADDR1, emacETHADDR2, emacETHADDR3, emacETHADDR4, emacETHADDR5 };\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* See the header file for descriptions of public functions. */\r
+\r
+/*\r
+ * Prototype for the EMAC interrupt function - called by the asm wrapper.\r
+ */\r
+void vEMAC_ISR( void ) __attribute__ ((naked));\r
+\r
+/*\r
+ * Initialise both the Tx and Rx descriptors used by the EMAC.\r
+ */\r
+static void prvSetupDescriptors(void);\r
+\r
+/*\r
+ * Write our MAC address into the EMAC. \r
+ */\r
+static void prvSetupMACAddress( void );\r
+\r
+/*\r
+ * Configure the EMAC and AIC for EMAC interrupts.\r
+ */\r
+static void prvSetupEMACInterrupt( void );\r
+\r
+/*\r
+ * Some initialisation functions taken from the Atmel EMAC sample code.\r
+ */\r
+static unsigned portLONG vReadPHY( unsigned portCHAR ucAddress );\r
+\r
+static void vWritePHY( unsigned portCHAR ucAddress, unsigned portLONG ulValue);\r
+\r
+static portBASE_TYPE prvProbePHY( void );\r
+\r
+/* The semaphore used by the EMAC ISR to wake the EMAC task. */\r
+static xSemaphoreHandle xSemaphore = NULL;\r
+\r
+/* Holds the index to the next buffer from which data will be read. */\r
+static volatile unsigned portLONG ulNextRxBuffer = 0;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* See the header file for descriptions of public functions. */\r
+portLONG lEMACSend( portCHAR *pcFrom, unsigned portLONG ulLength, portLONG lEndOfFrame )\r
+{\r
+static unsigned portBASE_TYPE uxTxBufferIndex = 0;\r
+//portBASE_TYPE xWaitCycles = 0;\r
+portLONG lReturn = pdPASS;\r
+portCHAR *pcBuffer;\r
+unsigned portLONG ulLastBuffer, ulDataBuffered = 0, ulDataRemainingToSend, ulLengthToSend;\r
+\r
+ /* If the length of data to be transmitted is greater than each individual\r
+ transmit buffer then the data will be split into more than one buffer.\r
+ Loop until the entire length has been buffered. */\r
+ while( ulDataBuffered < ulLength )\r
+ {\r
+ /* Is a buffer available? */\r
+ while( !( xTxDescriptors[ uxTxBufferIndex ].U_Status.status & AVR32_TRANSMIT_OK ) )\r
+ {\r
+ /* There is no room to write the Tx data to the Tx buffer. Wait a\r
+ short while, then try again. */\r
+ vTaskDelay( emacBUFFER_WAIT_DELAY );\r
+ }\r
+ \r
+ /* lReturn will only be pdPASS if a buffer is available. */\r
+ if( lReturn == pdPASS )\r
+ {\r
+ portENTER_CRITICAL();\r
+ {\r
+ /* Get the address of the buffer from the descriptor, then copy\r
+ the data into the buffer. */\r
+ pcBuffer = ( portCHAR * ) xTxDescriptors[ uxTxBufferIndex ].addr;\r
+\r
+ /* How much can we write to the buffer? */\r
+ ulDataRemainingToSend = ulLength - ulDataBuffered;\r
+ if( ulDataRemainingToSend <= ETH_TX_BUFFER_SIZE )\r
+ {\r
+ /* We can write all the remaining bytes. */\r
+ ulLengthToSend = ulDataRemainingToSend;\r
+ }\r
+ else\r
+ {\r
+ /* We can not write more than ETH_TX_BUFFER_SIZE in one go. */\r
+ ulLengthToSend = ETH_TX_BUFFER_SIZE;\r
+ }\r
+\r
+ /* Copy the data into the buffer. */\r
+ memcpy( ( void * ) pcBuffer, ( void * ) &( pcFrom[ ulDataBuffered ] ), ulLengthToSend );\r
+ ulDataBuffered += ulLengthToSend;\r
+\r
+ /* Is this the last data for the frame? */\r
+ if( lEndOfFrame && ( ulDataBuffered >= ulLength ) )\r
+ {\r
+ /* No more data remains for this frame so we can start the\r
+ transmission. */\r
+ ulLastBuffer = AVR32_LAST_BUFFER;\r
+ }\r
+ else\r
+ {\r
+ /* More data to come for this frame. */\r
+ ulLastBuffer = 0;\r
+ }\r
+ \r
+ /* Fill out the necessary in the descriptor to get the data sent,\r
+ then move to the next descriptor, wrapping if necessary. */\r
+ if( uxTxBufferIndex >= ( NB_TX_BUFFERS - 1 ) )\r
+ {\r
+ xTxDescriptors[ uxTxBufferIndex ].U_Status.status = ( ulLengthToSend & ( unsigned portLONG ) AVR32_LENGTH_FRAME )\r
+ | ulLastBuffer\r
+ | AVR32_TRANSMIT_WRAP;\r
+ uxTxBufferIndex = 0;\r
+ }\r
+ else\r
+ {\r
+ xTxDescriptors[ uxTxBufferIndex ].U_Status.status = ( ulLengthToSend & ( unsigned portLONG ) AVR32_LENGTH_FRAME )\r
+ | ulLastBuffer;\r
+ uxTxBufferIndex++;\r
+ }\r
+ \r
+ /* If this is the last buffer to be sent for this frame we can\r
+ start the transmission. */\r
+ if( ulLastBuffer )\r
+ {\r
+ AVR32_MACB.ncr |= AVR32_MACB_TSTART_MASK;\r
+ }\r
+ }\r
+ portEXIT_CRITICAL();\r
+ }\r
+ else\r
+ {\r
+ break;\r
+ }\r
+ }\r
+\r
+ return lReturn;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* See the header file for descriptions of public functions. */\r
+unsigned portLONG ulEMACInputLength( void )\r
+{\r
+register unsigned portLONG ulIndex , ulLength = 0;\r
+\r
+ /* Skip any fragments. We are looking for the first buffer that contains\r
+ data and has the SOF (start of frame) bit set. */\r
+ while( ( xRxDescriptors[ ulNextRxBuffer ].addr & AVR32_OWNERSHIP_BIT ) && !( xRxDescriptors[ ulNextRxBuffer ].U_Status.status & AVR32_SOF ) )\r
+ {\r
+ /* Ignoring this buffer. Mark it as free again. */\r
+ xRxDescriptors[ ulNextRxBuffer ].addr &= ~( AVR32_OWNERSHIP_BIT );\r
+ ulNextRxBuffer++;\r
+ if( ulNextRxBuffer >= NB_RX_BUFFERS )\r
+ {\r
+ ulNextRxBuffer = 0;\r
+ }\r
+ }\r
+\r
+ /* We are going to walk through the descriptors that make up this frame,\r
+ but don't want to alter ulNextRxBuffer as this would prevent vEMACRead()\r
+ from finding the data. Therefore use a copy of ulNextRxBuffer instead. */\r
+ ulIndex = ulNextRxBuffer;\r
+ /* Walk through the descriptors until we find the last buffer for this\r
+ frame. The last buffer will give us the length of the entire frame. */\r
+ while( ( xRxDescriptors[ ulIndex ].addr & AVR32_OWNERSHIP_BIT ) && !ulLength )\r
+ {\r
+ ulLength = xRxDescriptors[ ulIndex ].U_Status.status & AVR32_LENGTH_FRAME;\r
+ /* Increment to the next buffer, wrapping if necessary. */\r
+ ulIndex++;\r
+ if( ulIndex >= NB_RX_BUFFERS )\r
+ {\r
+ ulIndex = 0;\r
+ }\r
+ }\r
+ return ulLength;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* See the header file for descriptions of public functions. */\r
+void vEMACRead( portCHAR *pcTo, unsigned portLONG ulSectionLength, unsigned portLONG ulTotalFrameLength )\r
+{\r
+static unsigned portLONG ulSectionBytesReadSoFar = 0, ulBufferPosition = 0, ulFameBytesReadSoFar = 0;\r
+static portCHAR *pcSource;\r
+register unsigned portLONG ulBytesRemainingInBuffer, ulRemainingSectionBytes;\r
+\r
+ /* Read ulSectionLength bytes from the Rx buffers. This is not necessarily any\r
+ correspondence between the length of our Rx buffers, and the length of the\r
+ data we are returning or the length of the data being requested. Therefore,\r
+ between calls we have to remember not only which buffer we are currently\r
+ processing, but our position within that buffer. This would be greatly\r
+ simplified if PBUF_POOL_BUFSIZE could be guaranteed to be greater than\r
+ the size of each Rx buffer, and that memory fragmentation did not occur.\r
+ \r
+ This function should only be called after a call to ulEMACInputLength().\r
+ This will ensure ulNextRxBuffer is set to the correct buffer. */\r
+\r
+\r
+ /* vEMACRead is called with pcTo set to NULL to indicate that we are about\r
+ to read a new frame. Any fragments remaining in the frame we were\r
+ processing during the last call should be dropped. */\r
+ if( pcTo == NULL )\r
+ {\r
+ /* How many bytes are indicated as being in this buffer? If none then\r
+ the buffer is completely full and the frame is contained within more\r
+ than one buffer. */\r
+ /* Reset our state variables ready for the next read from this buffer. */\r
+ pcSource = ( portCHAR * )( xRxDescriptors[ ulNextRxBuffer ].addr & emacADDRESS_MASK );\r
+ ulFameBytesReadSoFar = ( unsigned portLONG ) 0;\r
+ ulBufferPosition = ( unsigned portLONG ) 0;\r
+ }\r
+ else\r
+ {\r
+ /* Loop until we have obtained the required amount of data. */\r
+ ulSectionBytesReadSoFar = 0;\r
+ while( ulSectionBytesReadSoFar < ulSectionLength )\r
+ {\r
+ /* We may have already read some data from this buffer. How much\r
+ data remains in the buffer? */\r
+ ulBytesRemainingInBuffer = ( ETH_RX_BUFFER_SIZE - ulBufferPosition );\r
+\r
+ /* How many more bytes do we need to read before we have the\r
+ required amount of data? */\r
+ ulRemainingSectionBytes = ulSectionLength - ulSectionBytesReadSoFar;\r
+\r
+ /* Do we want more data than remains in the buffer? */\r
+ if( ulRemainingSectionBytes > ulBytesRemainingInBuffer )\r
+ {\r
+ /* We want more data than remains in the buffer so we can\r
+ write the remains of the buffer to the destination, then move\r
+ onto the next buffer to get the rest. */\r
+ memcpy( &( pcTo[ ulSectionBytesReadSoFar ] ), &( pcSource[ ulBufferPosition ] ), ulBytesRemainingInBuffer );\r
+ ulSectionBytesReadSoFar += ulBytesRemainingInBuffer;\r
+ ulFameBytesReadSoFar += ulBytesRemainingInBuffer;\r
+\r
+ /* Mark the buffer as free again. */\r
+ xRxDescriptors[ ulNextRxBuffer ].addr &= ~( AVR32_OWNERSHIP_BIT );\r
+ /* Move onto the next buffer. */\r
+ ulNextRxBuffer++;\r
+ if( ulNextRxBuffer >= NB_RX_BUFFERS )\r
+ {\r
+ ulNextRxBuffer = ( unsigned portLONG ) 0;\r
+ }\r
+\r
+ /* Reset the variables for the new buffer. */\r
+ pcSource = ( portCHAR * )( xRxDescriptors[ ulNextRxBuffer ].addr & emacADDRESS_MASK );\r
+ ulBufferPosition = ( unsigned portLONG ) 0;\r
+ }\r
+ else\r
+ {\r
+ /* We have enough data in this buffer to send back. Read out\r
+ enough data and remember how far we read up to. */\r
+ memcpy( &( pcTo[ ulSectionBytesReadSoFar ] ), &( pcSource[ ulBufferPosition ] ), ulRemainingSectionBytes );\r
+\r
+ /* There may be more data in this buffer yet. Increment our\r
+ position in this buffer past the data we have just read. */\r
+ ulBufferPosition += ulRemainingSectionBytes;\r
+ ulSectionBytesReadSoFar += ulRemainingSectionBytes;\r
+ ulFameBytesReadSoFar += ulRemainingSectionBytes;\r
+\r
+ /* Have we now finished with this buffer? */\r
+ if( ( ulBufferPosition >= ETH_RX_BUFFER_SIZE ) || ( ulFameBytesReadSoFar >= ulTotalFrameLength ) )\r
+ {\r
+ /* Mark the buffer as free again. */\r
+ xRxDescriptors[ ulNextRxBuffer ].addr &= ~( AVR32_OWNERSHIP_BIT );\r
+ /* Move onto the next buffer. */\r
+ ulNextRxBuffer++;\r
+ if( ulNextRxBuffer >= NB_RX_BUFFERS )\r
+ {\r
+ ulNextRxBuffer = 0;\r
+ }\r
+ pcSource = ( portCHAR * )( xRxDescriptors[ ulNextRxBuffer ].addr & emacADDRESS_MASK );\r
+ ulBufferPosition = 0;\r
+ }\r
+ }\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+void vEMACSetMACAddress(const portCHAR * EMACAddress)\r
+{\r
+ memcpy(cMACAddress, EMACAddress, sizeof(cMACAddress));\r
+}\r
+\r
+/* See the header file for descriptions of public functions. */\r
+xSemaphoreHandle xEMACInit( void )\r
+{\r
+unsigned long status;\r
+\r
+ /* enable GPIO's */\r
+ gpio_enable_module_pin(AVR32_MACB_TX_CLK_0_PIN, AVR32_MACB_TX_CLK_0_FUNCTION); //PB0\r
+ gpio_enable_module_pin(AVR32_MACB_TX_EN_0_PIN, AVR32_MACB_TX_EN_0_FUNCTION); //PB1\r
+ gpio_enable_module_pin(AVR32_MACB_TXD_0_PIN, AVR32_MACB_TXD_0_FUNCTION); //PB2\r
+ gpio_enable_module_pin(AVR32_MACB_TXD_1_PIN, AVR32_MACB_TXD_1_FUNCTION); //PB3\r
+\r
+ gpio_enable_module_pin(AVR32_MACB_RXD_0_PIN, AVR32_MACB_RXD_0_FUNCTION); //PB5\r
+ gpio_enable_module_pin(AVR32_MACB_RXD_1_PIN, AVR32_MACB_RXD_1_FUNCTION); //PB6\r
+ gpio_enable_module_pin(AVR32_MACB_RX_ER_0_PIN, AVR32_MACB_RX_ER_0_FUNCTION); //PB7\r
+ gpio_enable_module_pin(AVR32_MACB_MDC_0_PIN, AVR32_MACB_MDC_0_FUNCTION); //PB8\r
+ gpio_enable_module_pin(AVR32_MACB_MDIO_0_PIN, AVR32_MACB_MDIO_0_FUNCTION); //PB9\r
+\r
+ gpio_enable_module_pin(AVR32_MACB_RX_DV_0_PIN, AVR32_MACB_RX_DV_0_FUNCTION); //PB15\r
+\r
+\r
+ /* set up registers */\r
+ AVR32_MACB.ncr = 0;\r
+ AVR32_MACB.tsr = ~0UL;\r
+ AVR32_MACB.rsr = ~0UL;\r
+ AVR32_MACB.idr = ~0UL;\r
+ status = AVR32_MACB.isr;\r
+\r
+\r
+#ifndef USE_RMII_INTERFACE\r
+ // RMII not used, set 1 to the USRIO Register\r
+ AVR32_MACB.usrio |= AVR32_MACB_RMII_MASK;\r
+#else\r
+ // RMII used, set 0 to the USRIO Register\r
+ AVR32_MACB.usrio &= ~AVR32_MACB_RMII_MASK;\r
+#endif\r
+\r
+ /* Load our MAC address into the EMAC. */\r
+ prvSetupMACAddress();\r
+\r
+ /* Setup the buffers and descriptors. */\r
+ prvSetupDescriptors();\r
+\r
+#if configCPU_CLOCK_HZ <= 20000000\r
+ AVR32_MACB.ncfgr |= (AVR32_MACB_NCFGR_CLK_DIV8 << AVR32_MACB_NCFGR_CLK_OFFSET);\r
+#elif configCPU_CLOCK_HZ <= 40000000\r
+ AVR32_MACB.ncfgr |= (AVR32_MACB_NCFGR_CLK_DIV16 << AVR32_MACB_NCFGR_CLK_OFFSET);\r
+#elif configCPU_CLOCK_HZ <= 80000000\r
+ AVR32_MACB.ncfgr |= AVR32_MACB_NCFGR_CLK_DIV32 << AVR32_MACB_NCFGR_CLK_OFFSET;\r
+#elif configCPU_CLOCK_HZ <= 160000000\r
+ AVR32_MACB.ncfgr |= AVR32_MACB_NCFGR_CLK_DIV64 << AVR32_MACB_NCFGR_CLK_OFFSET;\r
+#else\r
+# error System clock too fast\r
+#endif\r
+\r
+ /* Are we connected? */\r
+ if( prvProbePHY() )\r
+ {\r
+ /* Enable the interrupt! */\r
+ portENTER_CRITICAL();\r
+ {\r
+ prvSetupEMACInterrupt();\r
+ vPassEMACSemaphore( xSemaphore );\r
+ }\r
+ portEXIT_CRITICAL();\r
+ /* Enable Rx and Tx, plus the stats register. */\r
+ AVR32_MACB.ncr = AVR32_MACB_NCR_TE_MASK | AVR32_MACB_NCR_RE_MASK;\r
+ }\r
+ return xSemaphore;\r
+}\r
+\r
+/* See the header file for descriptions of public functions. */\r
+void vClearEMACTxBuffer( void )\r
+{\r
+static unsigned portBASE_TYPE uxNextBufferToClear = 0;\r
+\r
+ /* Called on Tx interrupt events to set the AT91C_TRANSMIT_OK bit in each\r
+ Tx buffer within the frame just transmitted. This marks all the buffers\r
+ as available again.\r
+\r
+ The first buffer in the frame should have the bit set automatically. */\r
+ if( xTxDescriptors[ uxNextBufferToClear ].U_Status.status & AVR32_TRANSMIT_OK )\r
+ {\r
+ /* Loop through the other buffers in the frame. */\r
+ while( !( xTxDescriptors[ uxNextBufferToClear ].U_Status.status & AVR32_LAST_BUFFER ) )\r
+ {\r
+ uxNextBufferToClear++;\r
+\r
+ if( uxNextBufferToClear >= NB_TX_BUFFERS )\r
+ {\r
+ uxNextBufferToClear = 0;\r
+ }\r
+\r
+ xTxDescriptors[ uxNextBufferToClear ].U_Status.status |= AVR32_TRANSMIT_OK;\r
+ }\r
+\r
+ /* Start with the next buffer the next time a Tx interrupt is called. */\r
+ uxNextBufferToClear++;\r
+\r
+ /* Do we need to wrap back to the first buffer? */\r
+ if( uxNextBufferToClear >= NB_TX_BUFFERS )\r
+ {\r
+ uxNextBufferToClear = 0;\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvSetupDescriptors(void)\r
+{\r
+unsigned portBASE_TYPE xIndex;\r
+unsigned portLONG ulAddress;\r
+\r
+ /* Initialise xRxDescriptors descriptor. */\r
+ for( xIndex = 0; xIndex < NB_RX_BUFFERS; ++xIndex )\r
+ {\r
+ /* Calculate the address of the nth buffer within the array. */\r
+ ulAddress = ( unsigned portLONG )( pcRxBuffer + ( xIndex * ETH_RX_BUFFER_SIZE ) );\r
+\r
+ /* Write the buffer address into the descriptor. The DMA will place\r
+ the data at this address when this descriptor is being used. Mask off\r
+ the bottom bits of the address as these have special meaning. */\r
+ xRxDescriptors[ xIndex ].addr = ulAddress & emacADDRESS_MASK;\r
+ }\r
+\r
+ /* The last buffer has the wrap bit set so the EMAC knows to wrap back\r
+ to the first buffer. */\r
+ xRxDescriptors[ NB_RX_BUFFERS - 1 ].addr |= emacRX_WRAP_BIT;\r
+\r
+ /* Initialise xTxDescriptors. */\r
+ for( xIndex = 0; xIndex < NB_TX_BUFFERS; ++xIndex )\r
+ {\r
+ /* Calculate the address of the nth buffer within the array. */\r
+ ulAddress = ( unsigned portLONG )( pcTxBuffer + ( xIndex * ETH_TX_BUFFER_SIZE ) );\r
+\r
+ /* Write the buffer address into the descriptor. The DMA will read\r
+ data from here when the descriptor is being used. */\r
+ xTxDescriptors[ xIndex ].addr = ulAddress & emacADDRESS_MASK;\r
+ xTxDescriptors[ xIndex ].U_Status.status = AVR32_TRANSMIT_OK;\r
+ }\r
+\r
+ /* The last buffer has the wrap bit set so the EMAC knows to wrap back\r
+ to the first buffer. */\r
+ xTxDescriptors[ NB_TX_BUFFERS - 1 ].U_Status.status = AVR32_TRANSMIT_WRAP | AVR32_TRANSMIT_OK;\r
+\r
+ /* Tell the EMAC where to find the descriptors. */\r
+ AVR32_MACB.rbqp = ( unsigned portLONG )xRxDescriptors;\r
+ AVR32_MACB.tbqp = ( unsigned portLONG )xTxDescriptors;\r
+\r
+ /* Enable the copy of data into the buffers, ignore broadcasts,\r
+ and don't copy FCS. */\r
+ AVR32_MACB.ncfgr |= (AVR32_MACB_CAF_MASK | AVR32_MACB_NBC_MASK | AVR32_MACB_NCFGR_DRFCS_MASK);\r
+\r
+} \r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvSetupMACAddress( void )\r
+{\r
+ /* Must be written SA1L then SA1H. */\r
+ AVR32_MACB.sa1b = ( ( unsigned portLONG ) cMACAddress[ 3 ] << 24 ) |\r
+ ( ( unsigned portLONG ) cMACAddress[ 2 ] << 16 ) |\r
+ ( ( unsigned portLONG ) cMACAddress[ 1 ] << 8 ) |\r
+ cMACAddress[ 0 ];\r
+\r
+ AVR32_MACB.sa1t = ( ( unsigned portLONG ) cMACAddress[ 5 ] << 8 ) |\r
+ cMACAddress[ 4 ];\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvSetupEMACInterrupt( void )\r
+{\r
+ /* Create the semaphore used to trigger the EMAC task. */\r
+ if (xSemaphore == NULL)\r
+ {\r
+ vSemaphoreCreateBinary( xSemaphore );\r
+ }\r
+\r
+ if( xSemaphore )\r
+ {\r
+ /* We start by 'taking' the semaphore so the ISR can 'give' it when the\r
+ first interrupt occurs. */\r
+ xSemaphoreTake( xSemaphore, emacNO_DELAY );\r
+ portENTER_CRITICAL();\r
+ {\r
+ /* Setup the interrupt for USART0.\r
+ Register the USART0 interrupt handler to the interrupt controller\r
+ at interrupt level 2. */\r
+ INTC_register_interrupt(&vEMAC_ISR, AVR32_MACB_IRQ, INT2);\r
+\r
+ /* We want to interrupt on Rx and Tx events. */\r
+ AVR32_MACB.ier = AVR32_MACB_IER_RCOMP_MASK | AVR32_MACB_IER_TCOMP_MASK;\r
+ }\r
+ portEXIT_CRITICAL();\r
+ }\r
+}\r
+\r
+/*\r
+ * The following functions are initialisation functions taken from the Atmel\r
+ * EMAC sample code.\r
+ */\r
+static portBASE_TYPE prvProbePHY( void )\r
+{\r
+unsigned long mii_status, advertise, lpa, phy_ctrl;\r
+unsigned long config;\r
+unsigned long upper, lower,mode;\r
+unsigned long physID;\r
+\r
+ /* Read Phy Identifier register 1 & 2 */\r
+ lower = vReadPHY(PHY_PHYSID2);\r
+ upper = vReadPHY(PHY_PHYSID1);\r
+ /* get Phy ID, ignore Revision */\r
+ physID = ((upper << 16) & 0xFFFF0000) | (lower & 0xFFF0);\r
+ /* check if it match config */\r
+ if (physID == MII_DP83848_ID)\r
+ {\r
+ /* read RBR */\r
+ mode = vReadPHY(PHY_RBR);\r
+ /* set RMII mode if not done */\r
+ if ((mode & RBR_RMII) != RBR_RMII)\r
+ {\r
+ /* force RMII flag if strap options are wrong */\r
+ mode |= RBR_RMII;\r
+ vWritePHY(PHY_RBR,mode);\r
+ }\r
+\r
+ /* set advertise register */\r
+#if ETHERNET_CONF_AN_ENABLE == 1\r
+ advertise = ADVERTISE_CSMA | ADVERTISE_ALL;\r
+#else\r
+ advertise = ADVERTISE_CSMA;\r
+ #if ETHERNET_CONF_USE_100MB\r
+ #if ETHERNET_CONF_USE_FULL_DUPLEX\r
+ advertise |= ADVERTISE_100FULL;\r
+ #else\r
+ advertise |= ADVERTISE_100HALF;\r
+ #endif\r
+ #else\r
+ #if ETHERNET_CONF_USE_FULL_DUPLEX\r
+ advertise |= ADVERTISE_10FULL;\r
+ #else\r
+ advertise |= ADVERTISE_10HALF;\r
+ #endif\r
+ #endif\r
+#endif\r
+ /* write advertise register */\r
+ vWritePHY(PHY_ADVERTISE, advertise);\r
+ /* read Control register */\r
+ config = vReadPHY(PHY_BMCR);\r
+ /* read Phy Control register */\r
+ phy_ctrl = vReadPHY(PHY_PHYCR);\r
+#if ETHERNET_CONF_AN_ENABLE\r
+ #if ETHERNET_CONF_AUTO_CROSS_ENABLE\r
+ /* enable Auto MDIX */\r
+ phy_ctrl |= PHYCR_MDIX_EN;\r
+ #else\r
+ /* disable Auto MDIX */\r
+ phy_ctrl &= ~PHYCR_MDIX_EN;\r
+ #if ETHERNET_CONF_CROSSED_LINK\r
+ /* force direct link = Use crossed RJ45 cable */\r
+ phy_ctrl &= ~PHYCR_MDIX_FORCE;\r
+ #else\r
+ /* force crossed link = Use direct RJ45 cable */\r
+ phy_ctrl |= PHYCR_MDIX_FORCE;\r
+ #endif\r
+ #endif\r
+ /* reset auto-negociation capability */\r
+ config |= (BMCR_ANRESTART | BMCR_ANENABLE);\r
+#else\r
+ /* disable Auto MDIX */\r
+ phy_ctrl &= ~PHYCR_MDIX_EN;\r
+ #if ETHERNET_CONF_CROSSED_LINK\r
+ /* force direct link = Use crossed RJ45 cable */\r
+ phy_ctrl &= ~PHYCR_MDIX_FORCE;\r
+ #else\r
+ /* force crossed link = Use direct RJ45 cable */\r
+ phy_ctrl |= PHYCR_MDIX_FORCE;\r
+ #endif\r
+ /* clear AN bit */\r
+ config &= ~BMCR_ANENABLE;\r
+\r
+ #if ETHERNET_CONF_USE_100MB\r
+ config |= BMCR_SPEED100;\r
+ #else\r
+ config &= ~BMCR_SPEED100;\r
+ #endif\r
+ #if ETHERNET_CONF_USE_FULL_DUPLEX\r
+ config |= BMCR_FULLDPLX;\r
+ #else\r
+ config &= ~BMCR_FULLDPLX;\r
+ #endif\r
+#endif\r
+ /* update Phy ctrl register */\r
+ vWritePHY(PHY_PHYCR, phy_ctrl);\r
+\r
+ /* update ctrl register */\r
+ vWritePHY(PHY_BMCR, config);\r
+\r
+ /* loop while link status isn't OK */\r
+ do {\r
+ mii_status = vReadPHY(PHY_BMSR);\r
+ } while (!(mii_status & BMSR_LSTATUS));\r
+\r
+ /* read the LPA configuration of the PHY */\r
+ lpa = vReadPHY(PHY_LPA);\r
+\r
+ /* read the MACB config register */\r
+ config = AVR32_MACB.ncfgr;\r
+\r
+ /* if 100MB needed */\r
+ if ((lpa & advertise) & (LPA_100HALF | LPA_100FULL))\r
+ {\r
+ config |= AVR32_MACB_SPD_MASK;\r
+ }\r
+ else\r
+ {\r
+ config &= ~(AVR32_MACB_SPD_MASK);\r
+ }\r
+\r
+ /* if FULL DUPLEX needed */\r
+ if ((lpa & advertise) & (LPA_10FULL | LPA_100FULL))\r
+ {\r
+ config |= AVR32_MACB_FD_MASK;\r
+ }\r
+ else\r
+ {\r
+ config &= ~(AVR32_MACB_FD_MASK);\r
+ }\r
+\r
+ /* write the MACB config register */\r
+ AVR32_MACB.ncfgr = config;\r
+\r
+ return pdPASS;\r
+ }\r
+ return pdFAIL;\r
+}\r
+\r
+static unsigned portLONG vReadPHY( unsigned portCHAR ucAddress )\r
+{\r
+ unsigned portLONG pulValue;\r
+\r
+ /* Enable management port */\r
+ AVR32_MACB.ncr |= AVR32_MACB_NCR_MPE_MASK;\r
+\r
+ /* configure MDIO frame in MAN register */\r
+ AVR32_MACB.man = (AVR32_MACB_SOF_MASK & (0x01<<AVR32_MACB_SOF_OFFSET)) // SOF\r
+ | (2 << AVR32_MACB_CODE_OFFSET) // Code\r
+ | (2 << AVR32_MACB_RW_OFFSET) // Read operation\r
+ | ((DP83848_PHY_ADDR & 0x1f) << AVR32_MACB_PHYA_OFFSET) // Phy Add\r
+ | (ucAddress << AVR32_MACB_REGA_OFFSET); // Reg Add\r
+\r
+ /* Wait until IDLE bit in Network Status register is cleared. */\r
+ while( !( AVR32_MACB.nsr & AVR32_MACB_NSR_IDLE_MASK ) )\r
+ {\r
+ __asm( "NOP" );\r
+ }\r
+\r
+ pulValue = (AVR32_MACB.man & 0x0000ffff );\r
+\r
+ /* Disable management port */\r
+ AVR32_MACB.ncr &= ~AVR32_MACB_NCR_MPE_MASK;\r
+\r
+ return (pulValue);\r
+}\r
+\r
+\r
+static void vWritePHY( unsigned portCHAR ucAddress, unsigned portLONG ulValue )\r
+{\r
+ /* Enable management port */\r
+ AVR32_MACB.ncr |= AVR32_MACB_NCR_MPE_MASK;\r
+\r
+ /* configure MDIO frame in MAN register */\r
+ AVR32_MACB.man = (( AVR32_MACB_SOF_MASK & (0x01<<AVR32_MACB_SOF_OFFSET)) // SOF\r
+ | (2 << AVR32_MACB_CODE_OFFSET) // Code\r
+ | (1 << AVR32_MACB_RW_OFFSET) // Write operation\r
+ | ((DP83848_PHY_ADDR & 0x1f) << AVR32_MACB_PHYA_OFFSET) // Phy Add\r
+ | (ucAddress << AVR32_MACB_REGA_OFFSET)) // Reg Add\r
+ | (ulValue & 0xffff); // Data\r
+\r
+ /* Wait until IDLE bit in Network Status register is cleared */\r
+ while( !( AVR32_MACB.nsr & AVR32_MACB_NSR_IDLE_MASK ) )\r
+ {\r
+ __asm( "NOP" );\r
+ };\r
+\r
+ /* Disable management port */\r
+ AVR32_MACB.ncr &= ~AVR32_MACB_NCR_MPE_MASK;\r
+\r
+}\r
+\r
+void vEMACWaitForInput( void )\r
+{\r
+ /* Just wait until we are signled from an ISR that data is available, or\r
+ we simply time out. */\r
+ xSemaphoreTake( xSemaphore, emacBLOCK_TIME_WAITING_FOR_INPUT );\r
+}\r
--- /dev/null
+/* This header file is part of the ATMEL FREERTOS-0.9.0 Release */\r
+\r
+/*This file has been prepared for Doxygen automatic documentation generation.*/\r
+/*! \file *********************************************************************\r
+ *\r
+ * \brief EMAC abstraction layer for AVR32 UC3.\r
+ *\r
+ * - Compiler: GNU GCC for AVR32\r
+ * - Supported devices: All AVR32 devices can be used.\r
+ * - AppNote:\r
+ *\r
+ * \author Atmel Corporation: http://www.atmel.com \n\r
+ * Support email: avr32@atmel.com\r
+ *\r
+ *****************************************************************************/\r
+\r
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of ATMEL may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND\r
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,\r
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\r
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\r
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF\r
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ */\r
+\r
+\r
+\r
+#ifndef AVR32_EMAC_H\r
+#define AVR32_EMAC_H\r
+\r
+#if __GNUC__\r
+# include <avr32/io.h>\r
+#elif __ICCAVR32__\r
+# include <avr32/iouc3a0512.h>\r
+#else\r
+# error Unknown compiler\r
+#endif\r
+\r
+#include <arch/sys_arch.h>\r
+\r
+#include "conf_eth.h"\r
+\r
+\r
+/* Receive Transfer descriptor structure */\r
+typedef struct _AVR32_RxTdDescriptor {\r
+ unsigned int addr;\r
+ union\r
+ {\r
+ unsigned int status;\r
+ struct {\r
+ unsigned int BroadCast:1;\r
+ unsigned int MultiCast:1;\r
+ unsigned int UniCast:1;\r
+ unsigned int ExternalAdd:1;\r
+ unsigned int Res1:1;\r
+ unsigned int Sa1Match:1;\r
+ unsigned int Sa2Match:1;\r
+ unsigned int Sa3Match:1;\r
+ unsigned int Sa4Match:1;\r
+ unsigned int TypeID:1;\r
+ unsigned int VlanTag:1;\r
+ unsigned int PriorityTag:1;\r
+ unsigned int VlanPriority:3;\r
+ unsigned int Cfi:1;\r
+ unsigned int EndOfFrame:1;\r
+ unsigned int StartOfFrame:1;\r
+ unsigned int Rxbuf_off:2;\r
+ unsigned int Res0:1;\r
+ unsigned int Length:11;\r
+ }S_Status;\r
+ }U_Status;\r
+}AVR32_RxTdDescriptor, *AVR32P_RxTdDescriptor;\r
+\r
+\r
+/* Transmit Transfer descriptor structure */\r
+typedef struct _AVR32_TxTdDescriptor {\r
+ unsigned int addr;\r
+ union\r
+ {\r
+ unsigned int status;\r
+ struct {\r
+ unsigned int BuffUsed:1;\r
+ unsigned int Wrap:1;\r
+ unsigned int TransmitError:1;\r
+ unsigned int TransmitUnderrun:1;\r
+ unsigned int BufExhausted:1;\r
+ unsigned int Res1:10;\r
+ unsigned int NoCrc:1;\r
+ unsigned int LastBuff:1;\r
+ unsigned int Res0:4;\r
+ unsigned int Length:11;\r
+ }S_Status;\r
+ }U_Status;\r
+}AVR32_TxTdDescriptor, *AVR32P_TxTdDescriptor;\r
+\r
+#define AVR32_OWNERSHIP_BIT 0x00000001\r
+\r
+/* Receive status defintion */\r
+#define AVR32_BROADCAST_ADDR ((unsigned int) (1 << 31)) //* Broadcat address detected\r
+#define AVR32_MULTICAST_HASH ((unsigned int) (1 << 30)) //* MultiCast hash match\r
+#define AVR32_UNICAST_HASH ((unsigned int) (1 << 29)) //* UniCast hash match\r
+#define AVR32_EXTERNAL_ADDR ((unsigned int) (1 << 28)) //* External Address match\r
+#define AVR32_SA1_ADDR ((unsigned int) (1 << 26)) //* Specific address 1 match\r
+#define AVR32_SA2_ADDR ((unsigned int) (1 << 25)) //* Specific address 2 match\r
+#define AVR32_SA3_ADDR ((unsigned int) (1 << 24)) //* Specific address 3 match\r
+#define AVR32_SA4_ADDR ((unsigned int) (1 << 23)) //* Specific address 4 match\r
+#define AVR32_TYPE_ID ((unsigned int) (1 << 22)) //* Type ID match\r
+#define AVR32_VLAN_TAG ((unsigned int) (1 << 21)) //* VLAN tag detected\r
+#define AVR32_PRIORITY_TAG ((unsigned int) (1 << 20)) //* PRIORITY tag detected\r
+#define AVR32_VLAN_PRIORITY ((unsigned int) (7 << 17)) //* PRIORITY Mask\r
+#define AVR32_CFI_IND ((unsigned int) (1 << 16)) //* CFI indicator\r
+#define AVR32_EOF ((unsigned int) (1 << 15)) //* EOF\r
+#define AVR32_SOF ((unsigned int) (1 << 14)) //* SOF\r
+#define AVR32_RBF_OFFSET ((unsigned int) (3 << 12)) //* Receive Buffer Offset Mask\r
+#define AVR32_LENGTH_FRAME ((unsigned int) 0x0FFF) //* Length of frame\r
+\r
+/* Transmit Status definition */\r
+#define AVR32_TRANSMIT_OK ((unsigned int) (1 << 31)) //*\r
+#define AVR32_TRANSMIT_WRAP ((unsigned int) (1 << 30)) //* Wrap bit: mark the last descriptor\r
+#define AVR32_TRANSMIT_ERR ((unsigned int) (1 << 29)) //* RLE:transmit error\r
+#define AVR32_TRANSMIT_UND ((unsigned int) (1 << 28)) //* Transmit Underrun\r
+#define AVR32_BUF_EX ((unsigned int) (1 << 27)) //* Buffers exhausted in mid frame\r
+#define AVR32_TRANSMIT_NO_CRC ((unsigned int) (1 << 16)) //* No CRC will be appended to the current frame\r
+#define AVR32_LAST_BUFFER ((unsigned int) (1 << 15)) //*\r
+\r
+#define AVR32_EMAC_CLKEN 0x2\r
+\r
+/*\r
+ * Initialise the EMAC driver. If successful a semaphore is returned that\r
+ * is used by the EMAC ISR to indicate that Rx packets have been received.\r
+ * If the initialisation fails then NULL is returned.\r
+ */\r
+xSemaphoreHandle xEMACInit( void );\r
+\r
+/*\r
+ * Send ulLength bytes from pcFrom. This copies the buffer to one of the\r
+ * EMAC Tx buffers, then indicates to the EMAC that the buffer is ready.\r
+ * If lEndOfFrame is true then the data being copied is the end of the frame\r
+ * and the frame can be transmitted.\r
+ */\r
+portLONG lEMACSend( portCHAR *pcFrom, unsigned portLONG ulLength, portLONG lEndOfFrame );\r
+\r
+/*\r
+ * Frames can be read from the EMAC in multiple sections.\r
+ * Read ulSectionLength bytes from the EMAC receive buffers to pcTo.\r
+ * ulTotalFrameLength is the size of the entire frame. Generally vEMACRead\r
+ * will be repetedly called until the sum of all the ulSectionLenths totals\r
+ * the value of ulTotalFrameLength.\r
+ */\r
+void vEMACRead( portCHAR *pcTo, unsigned portLONG ulSectionLength, unsigned portLONG ulTotalFrameLength );\r
+\r
+/*\r
+ * The EMAC driver and interrupt service routines are defined in different\r
+ * files as the driver is compiled to THUMB, and the ISR to ARM. This function\r
+ * simply passes the semaphore used to communicate between the two.\r
+ */\r
+void vPassEMACSemaphore( xSemaphoreHandle xCreatedSemaphore );\r
+\r
+/*\r
+ * Called by the Tx interrupt, this function traverses the buffers used to\r
+ * hold the frame that has just completed transmission and marks each as\r
+ * free again.\r
+ */\r
+void vClearEMACTxBuffer( void );\r
+\r
+/*\r
+ * Suspend on a semaphore waiting either for the semaphore to be obtained\r
+ * or a timeout. The semaphore is used by the EMAC ISR to indicate that\r
+ * data has been received and is ready for processing.\r
+ */\r
+void vEMACWaitForInput( void );\r
+\r
+/*\r
+ * Return the length of the next frame in the receive buffers.\r
+ */\r
+unsigned portLONG ulEMACInputLength( void );\r
+\r
+/*\r
+ * Set the MACB Physical address (SA1B & SA1T registers).\r
+ */\r
+void vEMACSetMACAddress(const portCHAR * EMACAddress);\r
+\r
+/*\r
+ * Get the MACB Physical address (SA1B & SA1T registers).\r
+ */\r
+void vEMACGetMACAddress(portCHAR * EMACAddress);\r
+\r
+#endif\r
--- /dev/null
+/* This source file is part of the ATMEL FREERTOS-0.9.0 Release */\r
+\r
+/*This file has been prepared for Doxygen automatic documentation generation.*/\r
+/*! \file *********************************************************************\r
+ *\r
+ * \brief EMAC abstraction layer for AVR32 UC3.\r
+ *\r
+ * - Compiler: GNU GCC for AVR32\r
+ * - Supported devices: All AVR32 devices can be used.\r
+ * - AppNote:\r
+ *\r
+ * \author Atmel Corporation: http://www.atmel.com \n\r
+ * Support email: avr32@atmel.com\r
+ *\r
+ *****************************************************************************/\r
+\r
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of ATMEL may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND\r
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,\r
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\r
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\r
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF\r
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ */\r
+\r
+\r
+\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "semphr.h"\r
+\r
+#include "AVR32_EMAC.h"\r
+#include "AVR32_CONF_EMAC.h"\r
+\r
+#include "lwipopts.h"\r
+\r
+\r
+\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* The semaphore used to signal the arrival of new data to the interface\r
+task. */\r
+static xSemaphoreHandle xSemaphore = NULL;\r
+\r
+static __attribute__((__noinline__)) portBASE_TYPE prvEMAC_ISR_NonNakedBehaviour( void );\r
+\r
+\r
+/*\r
+ * The EMAC ISR. Handles both Tx and Rx complete interrupts.\r
+ */\r
+//__attribute__((naked,section (".handlers"))) void vEMAC_ISR( void )\r
+__attribute__((naked)) void vEMAC_ISR( void )\r
+{\r
+ /* This ISR can cause a context switch, so the first statement must be a\r
+ call to the portENTER_SWITCHING_ISR() macro. This must be BEFORE any\r
+ variable declarations. */\r
+ portENTER_SWITCHING_ISR();\r
+\r
+ prvEMAC_ISR_NonNakedBehaviour();\r
+ /* Exit the ISR. If a task was woken by either a character being received\r
+ or transmitted then a context switch will occur. */\r
+\r
+ portEXIT_SWITCHING_ISR();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static __attribute__((__noinline__)) portBASE_TYPE prvEMAC_ISR_NonNakedBehaviour( void )\r
+{\r
+\r
+ /* Variable definitions can be made now. */\r
+ volatile unsigned portLONG ulIntStatus, ulEventStatus;\r
+ portBASE_TYPE xSwitchRequired = pdFALSE;\r
+ extern void vClearEMACTxBuffer( void );\r
+\r
+ /* Find the cause of the interrupt. */\r
+ ulIntStatus = AVR32_MACB.isr;\r
+ ulEventStatus = AVR32_MACB.rsr;\r
+\r
+ if( ( ulIntStatus & AVR32_MACB_IDR_RCOMP_MASK ) || ( ulEventStatus & AVR32_MACB_REC_MASK ) )\r
+ {\r
+ /* A frame has been received, signal the lwIP task so it can process\r
+ the Rx descriptors. */\r
+ portENTER_CRITICAL();\r
+ xSwitchRequired = xSemaphoreGiveFromISR( xSemaphore, pdFALSE );\r
+ portEXIT_CRITICAL();\r
+ AVR32_MACB.rsr = AVR32_MACB_REC_MASK;\r
+ AVR32_MACB.rsr;\r
+ }\r
+\r
+ if( ulIntStatus & AVR32_MACB_TCOMP_MASK )\r
+ {\r
+ /* A frame has been transmitted. Mark all the buffers used by the\r
+ frame just transmitted as free again. */\r
+ vClearEMACTxBuffer();\r
+ AVR32_MACB.tsr = AVR32_MACB_TSR_COMP_MASK;\r
+ AVR32_MACB.tsr;\r
+ }\r
+\r
+ return ( xSwitchRequired );\r
+}\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPassEMACSemaphore( xSemaphoreHandle xCreatedSemaphore )\r
+{\r
+ /* Simply store the semaphore that should be used by the ISR. */\r
+ xSemaphore = xCreatedSemaphore;\r
+}\r
+\r
+\r
--- /dev/null
+/* This header file is part of the ATMEL FREERTOS-0.9.0 Release */\r
+\r
+/*This file has been prepared for Doxygen automatic documentation generation.*/\r
+/*! \file *********************************************************************\r
+ *\r
+ * \brief PHY abstraction layer for AVR32 UC3 on EVK1100.\r
+ *\r
+ * - Compiler: GNU GCC for AVR32\r
+ * - Supported devices: All AVR32 devices can be used.\r
+ * - AppNote:\r
+ *\r
+ * \author Atmel Corporation: http://www.atmel.com \n\r
+ * Support email: avr32@atmel.com\r
+ *\r
+ *****************************************************************************/\r
+\r
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of ATMEL may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND\r
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,\r
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\r
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\r
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF\r
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ */\r
+\r
+/* DP83848 registers. */\r
+/*! Generic MII registers. */\r
+#define PHY_BMCR 0x00 /* Basic mode control register */\r
+#define PHY_BMSR 0x01 /* Basic mode status register */\r
+#define PHY_PHYSID1 0x02 /* PHYS ID 1 */\r
+#define PHY_PHYSID2 0x03 /* PHYS ID 2 */\r
+#define PHY_ADVERTISE 0x04 /* Advertisement control reg */\r
+#define PHY_LPA 0x05 /* Link partner ability reg */\r
+\r
+#if BOARD == EVK1100\r
+/*! Extended registers for DP83848 */\r
+#define PHY_RBR 0x17 /* RMII Bypass reg */\r
+#define PHY_MICR 0x11 /* Interrupt Control reg */\r
+#define PHY_MISR 0x12 /* Interrupt Status reg */\r
+#define PHY_PHYCR 0x19 /* Phy CTRL reg */\r
+#endif\r
+\r
+\r
+/*! Basic mode control register. */\r
+#define BMCR_RESV 0x007f /* Unused... */\r
+#define BMCR_CTST 0x0080 /* Collision test */\r
+#define BMCR_FULLDPLX 0x0100 /* Full duplex */\r
+#define BMCR_ANRESTART 0x0200 /* Auto negotiation restart */\r
+#define BMCR_ISOLATE 0x0400 /* Disconnect PHY from MII */\r
+#define BMCR_PDOWN 0x0800 /* Powerdown the PHY */\r
+#define BMCR_ANENABLE 0x1000 /* Enable auto negotiation */\r
+#define BMCR_SPEED100 0x2000 /* Select 100Mbps */\r
+#define BMCR_LOOPBACK 0x4000 /* TXD loopback bits */\r
+#define BMCR_RESET 0x8000 /* Reset the PHY */\r
+\r
+/*! Basic mode status register. */\r
+#define BMSR_ERCAP 0x0001 /* Ext-reg capability */\r
+#define BMSR_JCD 0x0002 /* Jabber detected */\r
+#define BMSR_LSTATUS 0x0004 /* Link status */\r
+#define BMSR_ANEGCAPABLE 0x0008 /* Able to do auto-negotiation */\r
+#define BMSR_RFAULT 0x0010 /* Remote fault detected */\r
+#define BMSR_ANEGCOMPLETE 0x0020 /* Auto-negotiation complete */\r
+#define BMSR_RESV 0x00c0 /* Unused... */\r
+#define BMSR_ESTATEN 0x0100 /* Extended Status in R15 */\r
+#define BMSR_100FULL2 0x0200 /* Can do 100BASE-T2 HDX */\r
+#define BMSR_100HALF2 0x0400 /* Can do 100BASE-T2 FDX */\r
+#define BMSR_10HALF 0x0800 /* Can do 10mbps, half-duplex */\r
+#define BMSR_10FULL 0x1000 /* Can do 10mbps, full-duplex */\r
+#define BMSR_100HALF 0x2000 /* Can do 100mbps, half-duplex */\r
+#define BMSR_100FULL 0x4000 /* Can do 100mbps, full-duplex */\r
+#define BMSR_100BASE4 0x8000 /* Can do 100mbps, 4k packets */\r
+\r
+/*! Advertisement control register. */\r
+#define ADVERTISE_SLCT 0x001f /* Selector bits */\r
+#define ADVERTISE_CSMA 0x0001 /* Only selector supported */\r
+#define ADVERTISE_10HALF 0x0020 /* Try for 10mbps half-duplex */\r
+#define ADVERTISE_1000XFULL 0x0020 /* Try for 1000BASE-X full-duplex */\r
+#define ADVERTISE_10FULL 0x0040 /* Try for 10mbps full-duplex */\r
+#define ADVERTISE_1000XHALF 0x0040 /* Try for 1000BASE-X half-duplex */\r
+#define ADVERTISE_100HALF 0x0080 /* Try for 100mbps half-duplex */\r
+#define ADVERTISE_1000XPAUSE 0x0080 /* Try for 1000BASE-X pause */\r
+#define ADVERTISE_100FULL 0x0100 /* Try for 100mbps full-duplex */\r
+#define ADVERTISE_1000XPSE_ASYM 0x0100 /* Try for 1000BASE-X asym pause */\r
+#define ADVERTISE_100BASE4 0x0200 /* Try for 100mbps 4k packets */\r
+#define ADVERTISE_PAUSE_CAP 0x0400 /* Try for pause */\r
+#define ADVERTISE_PAUSE_ASYM 0x0800 /* Try for asymetric pause */\r
+#define ADVERTISE_RESV 0x1000 /* Unused... */\r
+#define ADVERTISE_RFAULT 0x2000 /* Say we can detect faults */\r
+#define ADVERTISE_LPACK 0x4000 /* Ack link partners response */\r
+#define ADVERTISE_NPAGE 0x8000 /* Next page bit */\r
+\r
+#define ADVERTISE_FULL (ADVERTISE_100FULL | ADVERTISE_10FULL | ADVERTISE_CSMA)\r
+#define ADVERTISE_ALL (ADVERTISE_10HALF | ADVERTISE_10FULL | \\r
+ ADVERTISE_100HALF | ADVERTISE_100FULL)\r
+\r
+/*! Link partner ability register. */\r
+#define LPA_SLCT 0x001f /* Same as advertise selector */\r
+#define LPA_10HALF 0x0020 /* Can do 10mbps half-duplex */\r
+#define LPA_1000XFULL 0x0020 /* Can do 1000BASE-X full-duplex */\r
+#define LPA_10FULL 0x0040 /* Can do 10mbps full-duplex */\r
+#define LPA_1000XHALF 0x0040 /* Can do 1000BASE-X half-duplex */\r
+#define LPA_100HALF 0x0080 /* Can do 100mbps half-duplex */\r
+#define LPA_1000XPAUSE 0x0080 /* Can do 1000BASE-X pause */\r
+#define LPA_100FULL 0x0100 /* Can do 100mbps full-duplex */\r
+#define LPA_1000XPAUSE_ASYM 0x0100 /* Can do 1000BASE-X pause asym*/\r
+#define LPA_100BASE4 0x0200 /* Can do 100mbps 4k packets */\r
+#define LPA_PAUSE_CAP 0x0400 /* Can pause */\r
+#define LPA_PAUSE_ASYM 0x0800 /* Can pause asymetrically */\r
+#define LPA_RESV 0x1000 /* Unused... */\r
+#define LPA_RFAULT 0x2000 /* Link partner faulted */\r
+#define LPA_LPACK 0x4000 /* Link partner acked us */\r
+#define LPA_NPAGE 0x8000 /* Next page bit */\r
+\r
+#define LPA_DUPLEX (LPA_10FULL | LPA_100FULL)\r
+#define LPA_100 (LPA_100FULL | LPA_100HALF | LPA_100BASE4)\r
+\r
+#if BOARD == EVK1100\r
+/*! RMII Bypass Register */\r
+#define RBR_RMII 0x0020 /* RMII Mode */\r
+/*! Interrupt Ctrl Register */\r
+#define MICR_INTEN 0x0002 /* Enable interrupts */\r
+#define MICR_INTOE 0x0001 /* Enable INT output */\r
+/*! Interrupt Status Register */\r
+#define MISR_ED_INT_EN 0x0040 /* Energy Detect enabled */\r
+#define MISR_LINK_INT_EN 0x0020 /* Link status change enabled */\r
+#define MISR_SPD_INT_EN 0x0010 /* Speed change enabled */\r
+#define MISR_DP_INT_EN 0x0008 /* Duplex mode change enabled */\r
+#define MISR_ANC_INT_EN 0x0004 /* Auto-Neg complete enabled */\r
+#define MISR_FHF_INT_EN 0x0002 /* False Carrier enabled */\r
+#define MISR_RHF_INT_EN 0x0001 /* Receive Error enabled */\r
+#define MISR_ED_INT 0x4000 /* Energy Detect */\r
+#define MISR_LINK_INT 0x2000 /* Link status change */\r
+#define MISR_SPD_INT 0x1000 /* Speed change */\r
+#define MISR_DP_INT 0x0800 /* Duplex mode change */\r
+#define MISR_ANC_INT 0x0400 /* Auto-Neg complete */\r
+#define MISR_FHF_INT 0x0200 /* False Carrier */\r
+#define MISR_RHF_INT 0x0100 /* Receive Error */\r
+/*! Phy Ctrl Register */\r
+#define PHYCR_MDIX_EN 0x8000 /* Enable Auto MDIX */\r
+#define PHYCR_MDIX_FORCE 0x4000 /* Force MDIX crossed */\r
+#endif\r
+\r
+/*! PHY ID */\r
+#define MII_DP83848_ID 0x20005C90 /* 0x00225541 */\r
+\r
+/*! PHY Address */\r
+#define DP83848_PHY_ADDR 0x01\r
+\r
--- /dev/null
+/* This source file is part of the ATMEL FREERTOS-0.9.0 Release */\r
+\r
+/*This file has been prepared for Doxygen automatic documentation generation.*/\r
+/*! \file *********************************************************************\r
+ *\r
+ * \brief ethernet management for AVR32 UC3.\r
+ *\r
+ * - Compiler: IAR EWAVR32 and GNU GCC for AVR32\r
+ * - Supported devices: All AVR32 devices can be used.\r
+ * - AppNote:\r
+ *\r
+ * \author Atmel Corporation: http://www.atmel.com \n\r
+ * Support email: avr32@atmel.com\r
+ *\r
+ *****************************************************************************/\r
+\r
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of ATMEL may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND\r
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,\r
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\r
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\r
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF\r
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ */\r
+\r
+\r
+\r
+#include <string.h>\r
+\r
+#include "conf_eth.h"\r
+\r
+/* Scheduler include files. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/* Demo program include files. */\r
+#include "partest.h"\r
+#include "serial.h"\r
+\r
+\r
+/* ethernet includes */\r
+#include "ethernet.h"\r
+#include "AVR32_EMAC.h"\r
+\r
+#if (HTTP_USED == 1)\r
+ #include "BasicWEB.h"\r
+#endif\r
+\r
+#if (TFTP_USED == 1)\r
+ #include "BasicTFTP.h"\r
+#endif\r
+\r
+#if (SMTP_USED == 1)\r
+ #include "BasicSMTP.h"\r
+#endif\r
+\r
+/* lwIP includes */\r
+#include "lwip/sys.h"\r
+#include "lwip/api.h" \r
+#include "lwip/tcpip.h"\r
+#include "lwip/memp.h" \r
+#include "lwip/stats.h"\r
+#include "netif/loopif.h"\r
+\r
+\r
+//_____ M A C R O S ________________________________________________________\r
+\r
+\r
+//_____ D E F I N I T I O N S ______________________________________________\r
+\r
+/* global variable containing MAC Config (hw addr, IP, GW, ...) */\r
+struct netif EMAC_if;\r
+\r
+//_____ D E C L A R A T I O N S ____________________________________________\r
+\r
+/* Initialisation required by lwIP. */\r
+static void prvlwIPInit( void );\r
+\r
+/* Initialisation of ethernet interfaces by reading config file */\r
+static void prvEthernetConfigureInterface(void * param);\r
+\r
+\r
+/*! \brief create ethernet task, for ethernet management.\r
+ *\r
+ * \param uxPriority Input. priority for the task, it should be low\r
+ *\r
+ */\r
+void vStartEthernetTask( unsigned portBASE_TYPE uxPriority )\r
+{\r
+ /* Setup lwIP. */\r
+ prvlwIPInit();\r
+\r
+#if (HTTP_USED == 1)\r
+ /* Create the WEB server task. This uses the lwIP RTOS abstraction layer.*/\r
+ sys_thread_new( vBasicWEBServer, ( void * ) NULL, ethWEBSERVER_PRIORITY );\r
+#endif\r
+\r
+#if (TFTP_USED == 1)\r
+ /* Create the TFTP server task. This uses the lwIP RTOS abstraction layer.*/\r
+ sys_thread_new( vBasicTFTPServer, ( void * ) NULL, ethTFTPSERVER_PRIORITY );\r
+#endif\r
+\r
+#if (SMTP_USED == 1)\r
+ /* Create the SMTP Host task. This uses the lwIP RTOS abstraction layer.*/\r
+ sys_thread_new( vBasicSMTPHost, ( void * ) NULL, ethSMTPHOST_PRIORITY );\r
+#endif\r
+\r
+}\r
+\r
+\r
+/*!\r
+ * \brief start lwIP layer.\r
+ */\r
+static void prvlwIPInit( void )\r
+{\r
+ /* Initialize lwIP and its interface layer. */\r
+ #if LWIP_STATS\r
+ stats_init();\r
+ #endif\r
+\r
+ sys_init();\r
+ mem_init();\r
+ memp_init();\r
+ pbuf_init();\r
+ netif_init();\r
+ \r
+ /* once TCP stack has been initalized, set hw and IP parameters, initialize MACB too */\r
+ tcpip_init( prvEthernetConfigureInterface, NULL );\r
+}\r
+\r
+/*!\r
+ * \brief set ethernet config \r
+ */\r
+static void prvEthernetConfigureInterface(void * param)\r
+{\r
+struct ip_addr xIpAddr, xNetMask, xGateway;\r
+extern err_t ethernetif_init( struct netif *netif );\r
+portCHAR MacAddress[6];\r
+\r
+ /* Default MAC addr. */\r
+ MacAddress[0] = emacETHADDR0;\r
+ MacAddress[1] = emacETHADDR1;\r
+ MacAddress[2] = emacETHADDR2;\r
+ MacAddress[3] = emacETHADDR3;\r
+ MacAddress[4] = emacETHADDR4;\r
+ MacAddress[5] = emacETHADDR5;\r
+ \r
+ /* pass the EMAC address to AVR32_EMAC module */\r
+ vEMACSetMACAddress( MacAddress );\r
+ \r
+ /* set MAC hardware address length to be used by lwIP */\r
+ EMAC_if.hwaddr_len = 6;\r
+ \r
+ /* set MAC hardware address to be used by lwIP */\r
+ memcpy( EMAC_if.hwaddr, MacAddress, EMAC_if.hwaddr_len );\r
+ \r
+ /* Default ip addr. */\r
+ IP4_ADDR( &xIpAddr,emacIPADDR0,emacIPADDR1,emacIPADDR2,emacIPADDR3 );\r
+ \r
+ /* Default Subnet mask. */\r
+ IP4_ADDR( &xNetMask,emacNET_MASK0,emacNET_MASK1,emacNET_MASK2,emacNET_MASK3 );\r
+ \r
+ /* Default Gw addr. */\r
+ IP4_ADDR( &xGateway,emacGATEWAY_ADDR0,emacGATEWAY_ADDR1,emacGATEWAY_ADDR2,emacGATEWAY_ADDR3 );\r
+ \r
+ /* add data to netif */\r
+ netif_add( &EMAC_if, &xIpAddr, &xNetMask, &xGateway, NULL, ethernetif_init, tcpip_input );\r
+ \r
+ /* make it the default interface */\r
+ netif_set_default( &EMAC_if );\r
+ \r
+ /* bring it up */\r
+ netif_set_up( &EMAC_if );\r
+}\r
+\r
+\r
+\r
--- /dev/null
+/* This header file is part of the ATMEL FREERTOS-0.9.0 Release */\r
+\r
+/*This file has been prepared for Doxygen automatic documentation generation.*/\r
+/*! \file *********************************************************************\r
+ *\r
+ * \brief ethernet headers for AVR32 UC3.\r
+ *\r
+ * - Compiler: IAR EWAVR32 and GNU GCC for AVR32\r
+ * - Supported devices: All AVR32 devices can be used.\r
+ * - AppNote:\r
+ *\r
+ * \author Atmel Corporation: http://www.atmel.com \n\r
+ * Support email: avr32@atmel.com\r
+ *\r
+ *****************************************************************************/\r
+\r
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of ATMEL may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND\r
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,\r
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\r
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\r
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF\r
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ */\r
+\r
+\r
+#ifndef ETHERNET_H\r
+#define ETHERNET_H\r
+\r
+/*! \brief create ethernet task, for ethernet management.\r
+ *\r
+ * \param uxPriority Input. priority for the task, it should be low\r
+ *\r
+ */\r
+void vStartEthernetTask( unsigned portBASE_TYPE uxPriority );\r
+\r
+\r
+\r
+#endif\r
+\r
+\r
--- /dev/null
+/* This header file is part of the ATMEL FREERTOS-0.9.0 Release */\r
+\r
+/*This file has been prepared for Doxygen automatic documentation generation.*/\r
+/*! \file *********************************************************************\r
+ *\r
+ * \brief lwIP abstraction layer for AVR32 UC3.\r
+ *\r
+ * - Compiler: GNU GCC for AVR32\r
+ * - Supported devices: All AVR32 devices can be used.\r
+ * - AppNote:\r
+ *\r
+ * \author Atmel Corporation: http://www.atmel.com \n\r
+ * Support email: avr32@atmel.com\r
+ *\r
+ *****************************************************************************/\r
+\r
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of ATMEL may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND\r
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,\r
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\r
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\r
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF\r
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ */\r
+\r
+#ifndef __CC_H__\r
+#define __CC_H__\r
+\r
+#include "cpu.h"\r
+\r
+typedef unsigned char u8_t;\r
+typedef signed char s8_t;\r
+typedef unsigned short u16_t;\r
+typedef signed short s16_t;\r
+typedef unsigned long u32_t;\r
+typedef signed long s32_t;\r
+typedef u32_t mem_ptr_t;\r
+typedef int sys_prot_t;\r
+\r
+/*! Defines for the LWIP_STATS feature. */\r
+#define S16_F "d"\r
+#define U16_F "d"\r
+#define X16_F "d"\r
+#define X32_F "d"\r
+#define U32_F "d"\r
+#define S32_F "d"\r
+\r
+#define LWIP_PLATFORM_DIAG(x) \r
+#define LWIP_PLATFORM_ASSERT(x) \r
+\r
+/* */\r
+#define PACK_STRUCT_BEGIN\r
+#define PACK_STRUCT_STRUCT __attribute__ ((__packed__))\r
+#define PACK_STRUCT_END\r
+#define PACK_STRUCT_FIELD(x) x\r
+\r
+#endif /* __CC_H__ */\r
--- /dev/null
+/* This header file is part of the ATMEL FREERTOS-0.9.0 Release */\r
+\r
+/*This file has been prepared for Doxygen automatic documentation generation.*/\r
+/*! \file *********************************************************************\r
+ *\r
+ * \brief lwIP abstraction layer for AVR32 UC3.\r
+ *\r
+ * - Compiler: GNU GCC for AVR32\r
+ * - Supported devices: All AVR32 devices can be used.\r
+ * - AppNote:\r
+ *\r
+ * \author Atmel Corporation: http://www.atmel.com \n\r
+ * Support email: avr32@atmel.com\r
+ *\r
+ *****************************************************************************/\r
+\r
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of ATMEL may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND\r
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,\r
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\r
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\r
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF\r
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ */\r
+\r
+\r
+#ifndef __CPU_H__\r
+#define __CPU_H__\r
+\r
+#define BYTE_ORDER BIG_ENDIAN\r
+\r
+#endif /* __CPU_H__ */\r
--- /dev/null
+/* This header file is part of the ATMEL FREERTOS-0.9.0 Release */\r
+\r
+/*This file has been prepared for Doxygen automatic documentation generation.*/\r
+/*! \file *********************************************************************\r
+ *\r
+ * \brief lwIP abstraction layer for AVR32 UC3.\r
+ *\r
+ * - Compiler: GNU GCC for AVR32\r
+ * - Supported devices: All AVR32 devices can be used.\r
+ * - AppNote:\r
+ *\r
+ * \author Atmel Corporation: http://www.atmel.com \n\r
+ * Support email: avr32@atmel.com\r
+ *\r
+ *****************************************************************************/\r
+\r
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of ATMEL may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND\r
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,\r
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\r
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\r
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF\r
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ */\r
+\r
+\r
+#ifndef __ARCH_INIT_H__\r
+#define __ARCH_INIT_H__\r
+\r
+#define TCPIP_INIT_DONE(arg) tcpip_init_done(arg)\r
+\r
+void tcpip_init_done(void *);\r
+int wait_for_tcpip_init(void);\r
+\r
+#endif /* __ARCH_INIT_H__ */\r
+\r
+\r
+\r
+\r
--- /dev/null
+/* This header file is part of the ATMEL FREERTOS-0.9.0 Release */\r
+\r
+/*This file has been prepared for Doxygen automatic documentation generation.*/\r
+/*! \file *********************************************************************\r
+ *\r
+ * \brief lwIP abstraction layer for AVR32 UC3.\r
+ *\r
+ * - Compiler: GNU GCC for AVR32\r
+ * - Supported devices: All AVR32 devices can be used.\r
+ * - AppNote:\r
+ *\r
+ * \author Atmel Corporation: http://www.atmel.com \n\r
+ * Support email: avr32@atmel.com\r
+ *\r
+ *****************************************************************************/\r
+\r
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of ATMEL may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND\r
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,\r
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\r
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\r
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF\r
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ */\r
+\r
+#ifndef __LIB_H__\r
+#define __LIB_H__\r
+\r
+#include <string.h>\r
+\r
+\r
+#endif /* __LIB_H__ */\r
--- /dev/null
+/* This header file is part of the ATMEL FREERTOS-0.9.0 Release */\r
+\r
+/*This file has been prepared for Doxygen automatic documentation generation.*/\r
+/*! \file *********************************************************************\r
+ *\r
+ * \brief lwIP abstraction layer for AVR32 UC3.\r
+ *\r
+ * - Compiler: GNU GCC for AVR32\r
+ * - Supported devices: All AVR32 devices can be used.\r
+ * - AppNote:\r
+ *\r
+ * \author Atmel Corporation: http://www.atmel.com \n\r
+ * Support email: avr32@atmel.com\r
+ *\r
+ *****************************************************************************/\r
+\r
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of ATMEL may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND\r
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,\r
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\r
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\r
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF\r
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ */\r
+\r
+#ifndef __PERF_H__\r
+#define __PERF_H__\r
+\r
+#define PERF_START /* null definition */\r
+#define PERF_STOP(x) /* null definition */\r
+\r
+#endif /* __PERF_H__ */\r
--- /dev/null
+/* This header file is part of the ATMEL FREERTOS-0.9.0 Release */\r
+\r
+/*This file has been prepared for Doxygen automatic documentation generation.*/\r
+/*! \file *********************************************************************\r
+ *\r
+ * \brief lwIP abstraction layer for AVR32 UC3.\r
+ *\r
+ * - Compiler: GNU GCC for AVR32\r
+ * - Supported devices: All AVR32 devices can be used.\r
+ * - AppNote:\r
+ *\r
+ * \author Atmel Corporation: http://www.atmel.com \n\r
+ * Support email: avr32@atmel.com\r
+ *\r
+ *****************************************************************************/\r
+\r
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of ATMEL may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND\r
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,\r
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\r
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\r
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF\r
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ */\r
+\r
+#ifndef __SYS_RTXC_H__\r
+#define __SYS_RTXC_H__\r
+\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "queue.h"\r
+#include "semphr.h"\r
+\r
+#define SYS_MBOX_NULL (xQueueHandle)0\r
+#define SYS_SEM_NULL (xSemaphoreHandle)0\r
+\r
+typedef xSemaphoreHandle sys_sem_t;\r
+typedef xQueueHandle sys_mbox_t;\r
+typedef xTaskHandle sys_thread_t;\r
+\r
+#endif /* __SYS_RTXC_H__ */\r
+\r
--- /dev/null
+/* This source file is part of the ATMEL FREERTOS-0.9.0 Release */\r
+\r
+/*\r
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.\r
+ * All rights reserved. \r
+ * \r
+ * Redistribution and use in source and binary forms, with or without modification, \r
+ * are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. The name of the author may not be used to endorse or promote products\r
+ * derived from this software without specific prior written permission. \r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED \r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF \r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT \r
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, \r
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT \r
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS \r
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN \r
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING \r
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY \r
+ * OF SUCH DAMAGE.\r
+ *\r
+ * This file is part of the lwIP TCP/IP stack.\r
+ * \r
+ * Author: Adam Dunkels <adam@sics.se>\r
+ *\r
+ */\r
+\r
+/*\r
+ * This file is a skeleton for developing Ethernet network interface\r
+ * drivers for lwIP. Add code to the low_level functions and do a\r
+ * search-and-replace for the word "ethernetif" to replace it with\r
+ * something that better describes your network interface.\r
+ */\r
+\r
+#include "lwip/opt.h"\r
+#include "lwip/def.h"\r
+#include "lwip/mem.h"\r
+#include "lwip/pbuf.h"\r
+#include "lwip/sys.h"\r
+#include <lwip/stats.h>\r
+\r
+#include "conf_eth.h"\r
+\r
+#include "netif/etharp.h"\r
+\r
+/* FreeRTOS includes. */\r
+#include "FreeRTOS.h"\r
+#include "AVR32_EMAC.h"\r
+#include "AVR32_CONF_EMAC.h"\r
+\r
+#define netifMTU ( 1500 )\r
+#define netifGUARD_BLOCK_TIME ( 250 )\r
+#define IFNAME0 'e'\r
+#define IFNAME1 'm'\r
+\r
+\r
+struct ethernetif {\r
+ struct eth_addr *ethaddr;\r
+ /* Add whatever per-interface state that is needed here. */\r
+};\r
+\r
+static const struct eth_addr ethbroadcast = {{0xff,0xff,0xff,0xff,0xff,0xff}};\r
+\r
+/* Forward declarations. */\r
+void ethernetif_input(void * );\r
+static err_t ethernetif_output(struct netif *netif, struct pbuf *p,\r
+ struct ip_addr *ipaddr);\r
+static struct netif *xNetIf = NULL;\r
+\r
+\r
+static void\r
+low_level_init(struct netif *netif)\r
+{\r
+// struct ethernetif *ethernetif = netif->state;\r
+ unsigned portBASE_TYPE uxPriority;\r
+\r
+ /* maximum transfer unit */\r
+ netif->mtu = netifMTU;\r
+ \r
+ /* broadcast capability */\r
+ netif->flags = NETIF_FLAG_BROADCAST;\r
+ \r
+ /* Do whatever else is needed to initialize interface. */ \r
+ xNetIf = netif;\r
+\r
+ /* Initialise the EMAC. This routine contains code that polls status bits.\r
+ If the Ethernet cable is not plugged in then this can take a considerable\r
+ time. To prevent this starving lower priority tasks of processing time we\r
+ lower our priority prior to the call, then raise it back again once the\r
+ initialisation is complete. */\r
+ uxPriority = uxTaskPriorityGet( NULL );\r
+ vTaskPrioritySet( NULL, tskIDLE_PRIORITY );\r
+ while( xEMACInit() == NULL )\r
+ {\r
+ __asm( "NOP" );\r
+ }\r
+ vTaskPrioritySet( NULL, uxPriority );\r
+\r
+ /* Create the task that handles the EMAC. */\r
+ // xTaskCreate( ethernetif_input, ( signed portCHAR * ) "ETH_INT", netifINTERFACE_TASK_STACK_SIZE, NULL, netifINTERFACE_TASK_PRIORITY, NULL );\r
+ sys_thread_new( ethernetif_input, NULL, netifINTERFACE_TASK_PRIORITY );\r
+}\r
+\r
+/*\r
+ * low_level_output():\r
+ *\r
+ * Should do the actual transmission of the packet. The packet is\r
+ * contained in the pbuf that is passed to the function. This pbuf\r
+ * might be chained.\r
+ *\r
+ */\r
+\r
+static err_t\r
+low_level_output(struct netif *netif, struct pbuf *p)\r
+{\r
+struct pbuf *q;\r
+static xSemaphoreHandle xTxSemaphore = NULL;\r
+err_t xReturn = ERR_OK;\r
+\r
+ /* Parameter not used. */\r
+ ( void ) netif;\r
+\r
+ if( xTxSemaphore == NULL )\r
+ {\r
+ vSemaphoreCreateBinary( xTxSemaphore );\r
+ }\r
+\r
+ #if ETH_PAD_SIZE\r
+ pbuf_header( p, -ETH_PAD_SIZE ); /* drop the padding word */\r
+ #endif\r
+\r
+ /* Access to the EMAC is guarded using a semaphore. */\r
+ if( xSemaphoreTake( xTxSemaphore, netifGUARD_BLOCK_TIME ) )\r
+ {\r
+ for( q = p; q != NULL; q = q->next )\r
+ {\r
+ /* Send the data from the pbuf to the interface, one pbuf at a\r
+ time. The size of the data in each pbuf is kept in the ->len\r
+ variable. if q->next == NULL then this is the last pbuf in the\r
+ chain. */\r
+ if( !lEMACSend( q->payload, q->len, ( q->next == NULL ) ) )\r
+ {\r
+ xReturn = ~ERR_OK;\r
+ }\r
+ }\r
+\r
+ xSemaphoreGive( xTxSemaphore );\r
+ }\r
+ \r
+\r
+ #if ETH_PAD_SIZE\r
+ pbuf_header( p, ETH_PAD_SIZE ); /* reclaim the padding word */\r
+ #endif\r
+\r
+ #if LINK_STATS\r
+ lwip_stats.link.xmit++;\r
+ #endif /* LINK_STATS */\r
+\r
+ return xReturn;\r
+}\r
+\r
+/*\r
+ * low_level_input():\r
+ *\r
+ * Should allocate a pbuf and transfer the bytes of the incoming\r
+ * packet from the interface into the pbuf.\r
+ *\r
+ */\r
+\r
+static struct pbuf *\r
+low_level_input(struct netif *netif) {\r
+struct pbuf *p = NULL;\r
+struct pbuf *q;\r
+u16_t len = 0;\r
+static xSemaphoreHandle xRxSemaphore = NULL;\r
+\r
+ /* Parameter not used. */\r
+ ( void ) netif;\r
+\r
+ if( xRxSemaphore == NULL )\r
+ {\r
+ vSemaphoreCreateBinary( xRxSemaphore );\r
+ }\r
+\r
+ /* Access to the emac is guarded using a semaphore. */\r
+ if( xSemaphoreTake( xRxSemaphore, netifGUARD_BLOCK_TIME ) )\r
+ {\r
+ /* Obtain the size of the packet. */\r
+ len = ulEMACInputLength();\r
+\r
+ if( len )\r
+ {\r
+ #if ETH_PAD_SIZE\r
+ len += ETH_PAD_SIZE; /* allow room for Ethernet padding */\r
+ #endif\r
+ \r
+ /* We allocate a pbuf chain of pbufs from the pool. */\r
+ p = pbuf_alloc( PBUF_RAW, len, PBUF_POOL );\r
+ \r
+ if( p != NULL )\r
+ {\r
+ #if ETH_PAD_SIZE\r
+ pbuf_header( p, -ETH_PAD_SIZE ); /* drop the padding word */\r
+ #endif\r
+ \r
+ /* Let the driver know we are going to read a new packet. */\r
+ vEMACRead( NULL, 0, len );\r
+ \r
+ /* We iterate over the pbuf chain until we have read the entire\r
+ packet into the pbuf. */\r
+ for( q = p; q != NULL; q = q->next )\r
+ {\r
+ /* Read enough bytes to fill this pbuf in the chain. The\r
+ available data in the pbuf is given by the q->len variable. */\r
+ vEMACRead( q->payload, q->len, len );\r
+ }\r
+ \r
+ #if ETH_PAD_SIZE\r
+ pbuf_header( p, ETH_PAD_SIZE ); /* reclaim the padding word */\r
+ #endif\r
+ #if LINK_STATS\r
+ lwip_stats.link.recv++;\r
+ #endif /* LINK_STATS */\r
+ }\r
+ else\r
+ {\r
+ #if LINK_STATS\r
+ lwip_stats.link.memerr++;\r
+ lwip_stats.link.drop++;\r
+ #endif /* LINK_STATS */\r
+ }\r
+ }\r
+ xSemaphoreGive( xRxSemaphore );\r
+ }\r
+\r
+ return p;\r
+}\r
+\r
+/*\r
+ * ethernetif_output():\r
+ *\r
+ * This function is called by the TCP/IP stack when an IP packet\r
+ * should be sent. It calls the function called low_level_output() to\r
+ * do the actual transmission of the packet.\r
+ *\r
+ */\r
+\r
+static err_t\r
+ethernetif_output(struct netif *netif, struct pbuf *p,\r
+ struct ip_addr *ipaddr)\r
+{\r
+ \r
+ /* resolve hardware address, then send (or queue) packet */\r
+ return etharp_output(netif, ipaddr, p);\r
+ \r
+}\r
+\r
+/*\r
+ * ethernetif_input():\r
+ *\r
+ * This function should be called when a packet is ready to be read\r
+ * from the interface. It uses the function low_level_input() that\r
+ * should handle the actual reception of bytes from the network\r
+ * interface.\r
+ *\r
+ */\r
+\r
+void ethernetif_input( void * pvParameters )\r
+{\r
+struct ethernetif *ethernetif;\r
+struct eth_hdr *ethhdr;\r
+struct pbuf *p;\r
+\r
+ ( void ) pvParameters;\r
+\r
+ for( ;; ) {\r
+ \r
+ ethernetif = xNetIf->state;\r
+ do\r
+ {\r
+ ethernetif = xNetIf->state;\r
+\r
+ /* move received packet into a new pbuf */\r
+ p = low_level_input( xNetIf );\r
+\r
+ if( p == NULL )\r
+ {\r
+ /* No packet could be read. Wait a for an interrupt to tell us\r
+ there is more data available. */\r
+ vEMACWaitForInput();\r
+ }\r
+\r
+ } while( p == NULL );\r
+\r
+ /* points to packet payload, which starts with an Ethernet header */\r
+ ethhdr = p->payload;\r
+ \r
+ #if LINK_STATS\r
+ lwip_stats.link.recv++;\r
+ #endif /* LINK_STATS */\r
+ \r
+ ethhdr = p->payload;\r
+ \r
+ switch( htons( ethhdr->type ) )\r
+ {\r
+ /* IP packet? */\r
+ case ETHTYPE_IP:\r
+ /* update ARP table */\r
+ etharp_ip_input( xNetIf, p );\r
+ \r
+ /* skip Ethernet header */\r
+ pbuf_header( p, (s16_t)-sizeof(struct eth_hdr) );\r
+ \r
+ /* pass to network layer */\r
+ xNetIf->input( p, xNetIf );\r
+ break;\r
+ \r
+ case ETHTYPE_ARP:\r
+ /* pass p to ARP module */\r
+ etharp_arp_input( xNetIf, ethernetif->ethaddr, p );\r
+ break;\r
+ \r
+ default:\r
+ pbuf_free( p );\r
+ p = NULL;\r
+ break;\r
+ }\r
+ }\r
+}\r
+\r
+static void\r
+arp_timer(void *arg)\r
+{\r
+ etharp_tmr();\r
+ sys_timeout(ARP_TMR_INTERVAL, arp_timer, NULL);\r
+}\r
+\r
+/*\r
+ * ethernetif_init():\r
+ *\r
+ * Should be called at the beginning of the program to set up the\r
+ * network interface. It calls the function low_level_init() to do the\r
+ * actual setup of the hardware.\r
+ *\r
+ */\r
+extern struct netif EMAC_if;\r
+err_t\r
+ethernetif_init(struct netif *netif)\r
+{\r
+ struct ethernetif *ethernetif;\r
+ int i;\r
+ \r
+ ethernetif = (struct ethernetif *)mem_malloc(sizeof(struct ethernetif));\r
+ \r
+ if (ethernetif == NULL)\r
+ {\r
+ LWIP_DEBUGF(NETIF_DEBUG, ("ethernetif_init: out of memory\n"));\r
+ return ERR_MEM;\r
+ }\r
+ \r
+ netif->state = ethernetif;\r
+ netif->name[0] = IFNAME0;\r
+ netif->name[1] = IFNAME1;\r
+ netif->output = ethernetif_output;\r
+ netif->linkoutput = low_level_output;\r
+ \r
+ for(i = 0; i < 6; i++) netif->hwaddr[i] = EMAC_if.hwaddr[i];\r
+ \r
+ low_level_init(netif);\r
+\r
+ etharp_init();\r
+\r
+ sys_timeout(ARP_TMR_INTERVAL, arp_timer, NULL);\r
+\r
+ return ERR_OK;\r
+}\r
+\r
--- /dev/null
+/* This header file is part of the ATMEL FREERTOS-0.9.0 Release */\r
+\r
+/*\r
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.\r
+ * All rights reserved. \r
+ * \r
+ * Redistribution and use in source and binary forms, with or without modification, \r
+ * are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. The name of the author may not be used to endorse or promote products\r
+ * derived from this software without specific prior written permission. \r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED \r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF \r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT \r
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, \r
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT \r
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS \r
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN \r
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING \r
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY \r
+ * OF SUCH DAMAGE.\r
+ *\r
+ * This file is part of the lwIP TCP/IP stack.\r
+ * \r
+ * Author: Adam Dunkels <adam@sics.se>\r
+ *\r
+ */\r
+#ifndef __LWIP_OPT_H__\r
+#define __LWIP_OPT_H__\r
+\r
+/* Include user defined options first */\r
+#include "lwipopts.h"\r
+#include "lwip/debug.h"\r
+\r
+/* Define default values for unconfigured parameters. */\r
+\r
+/* Platform specific locking */\r
+\r
+/*\r
+ * enable SYS_LIGHTWEIGHT_PROT in lwipopts.h if you want inter-task protection\r
+ * for certain critical regions during buffer allocation, deallocation and memory\r
+ * allocation and deallocation.\r
+ */\r
+#ifndef SYS_LIGHTWEIGHT_PROT\r
+#define SYS_LIGHTWEIGHT_PROT 0\r
+#endif\r
+\r
+#ifndef NO_SYS\r
+#define NO_SYS 0\r
+#endif\r
+/* ---------- Memory options ---------- */\r
+#ifndef MEM_LIBC_MALLOC\r
+#define MEM_LIBC_MALLOC 0\r
+#endif\r
+\r
+/* MEM_ALIGNMENT: should be set to the alignment of the CPU for which\r
+ lwIP is compiled. 4 byte alignment -> define MEM_ALIGNMENT to 4, 2\r
+ byte alignment -> define MEM_ALIGNMENT to 2. */\r
+\r
+#ifndef MEM_ALIGNMENT\r
+#define MEM_ALIGNMENT 1\r
+#endif\r
+\r
+/* MEM_SIZE: the size of the heap memory. If the application will send\r
+a lot of data that needs to be copied, this should be set high. */\r
+#ifndef MEM_SIZE\r
+#define MEM_SIZE 1600\r
+#endif\r
+\r
+#ifndef MEMP_SANITY_CHECK\r
+#define MEMP_SANITY_CHECK 0\r
+#endif\r
+\r
+/* MEMP_NUM_PBUF: the number of memp struct pbufs. If the application\r
+ sends a lot of data out of ROM (or other static memory), this\r
+ should be set high. */\r
+#ifndef MEMP_NUM_PBUF\r
+#define MEMP_NUM_PBUF 16\r
+#endif\r
+\r
+/* Number of raw connection PCBs */\r
+#ifndef MEMP_NUM_RAW_PCB\r
+#define MEMP_NUM_RAW_PCB 4\r
+#endif\r
+\r
+/* MEMP_NUM_UDP_PCB: the number of UDP protocol control blocks. One\r
+ per active UDP "connection". */\r
+#ifndef MEMP_NUM_UDP_PCB\r
+#define MEMP_NUM_UDP_PCB 4\r
+#endif\r
+/* MEMP_NUM_TCP_PCB: the number of simulatenously active TCP\r
+ connections. */\r
+#ifndef MEMP_NUM_TCP_PCB\r
+#define MEMP_NUM_TCP_PCB 5\r
+#endif\r
+/* MEMP_NUM_TCP_PCB_LISTEN: the number of listening TCP\r
+ connections. */\r
+#ifndef MEMP_NUM_TCP_PCB_LISTEN\r
+#define MEMP_NUM_TCP_PCB_LISTEN 8\r
+#endif\r
+/* MEMP_NUM_TCP_SEG: the number of simultaneously queued TCP\r
+ segments. */\r
+#ifndef MEMP_NUM_TCP_SEG\r
+#define MEMP_NUM_TCP_SEG 16\r
+#endif\r
+/* MEMP_NUM_SYS_TIMEOUT: the number of simulateously active\r
+ timeouts. */\r
+#ifndef MEMP_NUM_SYS_TIMEOUT\r
+#define MEMP_NUM_SYS_TIMEOUT 3\r
+#endif\r
+\r
+/* The following four are used only with the sequential API and can be\r
+ set to 0 if the application only will use the raw API. */\r
+/* MEMP_NUM_NETBUF: the number of struct netbufs. */\r
+#ifndef MEMP_NUM_NETBUF\r
+#define MEMP_NUM_NETBUF 2\r
+#endif\r
+/* MEMP_NUM_NETCONN: the number of struct netconns. */\r
+#ifndef MEMP_NUM_NETCONN\r
+#define MEMP_NUM_NETCONN 4\r
+#endif\r
+/* MEMP_NUM_APIMSG: the number of struct api_msg, used for\r
+ communication between the TCP/IP stack and the sequential\r
+ programs. */\r
+#ifndef MEMP_NUM_API_MSG\r
+#define MEMP_NUM_API_MSG 8\r
+#endif\r
+/* MEMP_NUM_TCPIPMSG: the number of struct tcpip_msg, which is used\r
+ for sequential API communication and incoming packets. Used in\r
+ src/api/tcpip.c. */\r
+#ifndef MEMP_NUM_TCPIP_MSG\r
+#define MEMP_NUM_TCPIP_MSG 8\r
+#endif\r
+\r
+/* ---------- Pbuf options ---------- */\r
+/* PBUF_POOL_SIZE: the number of buffers in the pbuf pool. */\r
+\r
+#ifndef PBUF_POOL_SIZE\r
+#define PBUF_POOL_SIZE 16\r
+#endif\r
+\r
+/* PBUF_POOL_BUFSIZE: the size of each pbuf in the pbuf pool. */\r
+\r
+#ifndef PBUF_POOL_BUFSIZE\r
+#define PBUF_POOL_BUFSIZE 128\r
+#endif\r
+\r
+/* PBUF_LINK_HLEN: the number of bytes that should be allocated for a\r
+ link level header. Defaults to 14 for Ethernet. */\r
+\r
+#ifndef PBUF_LINK_HLEN\r
+#define PBUF_LINK_HLEN 14\r
+#endif\r
+\r
+\r
+\r
+/* ---------- ARP options ---------- */\r
+\r
+/** Number of active hardware address, IP address pairs cached */\r
+#ifndef ARP_TABLE_SIZE\r
+#define ARP_TABLE_SIZE 10\r
+#endif\r
+\r
+/**\r
+ * If enabled, outgoing packets are queued during hardware address\r
+ * resolution.\r
+ *\r
+ * This feature has not stabilized yet. Single-packet queueing is\r
+ * believed to be stable, multi-packet queueing is believed to\r
+ * clash with the TCP segment queueing.\r
+ * \r
+ * As multi-packet-queueing is currently disabled, enabling this\r
+ * _should_ work, but we need your testing feedback on lwip-users.\r
+ *\r
+ */\r
+#ifndef ARP_QUEUEING\r
+#define ARP_QUEUEING 1\r
+#endif\r
+\r
+/* This option is deprecated */\r
+#ifdef ETHARP_QUEUE_FIRST\r
+#error ETHARP_QUEUE_FIRST option is deprecated. Remove it from your lwipopts.h.\r
+#endif\r
+\r
+/* This option is removed to comply with the ARP standard */\r
+#ifdef ETHARP_ALWAYS_INSERT\r
+#error ETHARP_ALWAYS_INSERT option is deprecated. Remove it from your lwipopts.h.\r
+#endif\r
+\r
+/* ---------- IP options ---------- */\r
+/* Define IP_FORWARD to 1 if you wish to have the ability to forward\r
+ IP packets across network interfaces. If you are going to run lwIP\r
+ on a device with only one network interface, define this to 0. */\r
+#ifndef IP_FORWARD\r
+#define IP_FORWARD 0\r
+#endif\r
+\r
+/* If defined to 1, IP options are allowed (but not parsed). If\r
+ defined to 0, all packets with IP options are dropped. */\r
+#ifndef IP_OPTIONS\r
+#define IP_OPTIONS 1\r
+#endif\r
+\r
+/** IP reassembly and segmentation. Even if they both deal with IP\r
+ * fragments, note that these are orthogonal, one dealing with incoming\r
+ * packets, the other with outgoing packets\r
+ */\r
+\r
+/** Reassemble incoming fragmented IP packets */\r
+#ifndef IP_REASSEMBLY\r
+#define IP_REASSEMBLY 1\r
+#endif\r
+\r
+/** Fragment outgoing IP packets if their size exceeds MTU */\r
+#ifndef IP_FRAG\r
+#define IP_FRAG 1\r
+#endif\r
+\r
+/* IP reassemly default age in seconds */\r
+#ifndef IP_REASS_MAXAGE\r
+#define IP_REASS_MAXAGE 3\r
+#endif\r
+\r
+/* IP reassembly buffer size (minus IP header) */\r
+#ifndef IP_REASS_BUFSIZE\r
+#define IP_REASS_BUFSIZE 5760\r
+#endif\r
+\r
+/* Assumed max MTU on any interface for IP frag buffer */\r
+#ifndef IP_FRAG_MAX_MTU\r
+#define IP_FRAG_MAX_MTU 1500\r
+#endif\r
+\r
+/** Global default value for Time To Live used by transport layers. */\r
+#ifndef IP_DEFAULT_TTL\r
+#define IP_DEFAULT_TTL 255\r
+#endif\r
+\r
+/* ---------- ICMP options ---------- */\r
+\r
+#ifndef ICMP_TTL\r
+#define ICMP_TTL (IP_DEFAULT_TTL)\r
+#endif\r
+\r
+/* ---------- RAW options ---------- */\r
+\r
+#ifndef LWIP_RAW\r
+#define LWIP_RAW 1\r
+#endif\r
+\r
+#ifndef RAW_TTL\r
+#define RAW_TTL (IP_DEFAULT_TTL)\r
+#endif\r
+\r
+/* ---------- DHCP options ---------- */\r
+\r
+#ifndef LWIP_DHCP\r
+#define LWIP_DHCP 0\r
+#endif\r
+\r
+/* 1 if you want to do an ARP check on the offered address\r
+ (recommended). */\r
+#ifndef DHCP_DOES_ARP_CHECK\r
+#define DHCP_DOES_ARP_CHECK 1\r
+#endif\r
+\r
+/* ---------- SNMP options ---------- */\r
+/** @note UDP must be available for SNMP transport */\r
+#ifndef LWIP_SNMP\r
+#define LWIP_SNMP 0\r
+#endif\r
+\r
+/** @note At least one request buffer is required. */\r
+#ifndef SNMP_CONCURRENT_REQUESTS\r
+#define SNMP_CONCURRENT_REQUESTS 1\r
+#endif\r
+\r
+/** @note At least one trap destination is required */\r
+#ifndef SNMP_TRAP_DESTINATIONS\r
+#define SNMP_TRAP_DESTINATIONS 1\r
+#endif\r
+\r
+#ifndef SNMP_PRIVATE_MIB\r
+#define SNMP_PRIVATE_MIB 0\r
+#endif\r
+\r
+/* ---------- UDP options ---------- */\r
+#ifndef LWIP_UDP\r
+#define LWIP_UDP 1\r
+#endif\r
+\r
+#ifndef UDP_TTL\r
+#define UDP_TTL (IP_DEFAULT_TTL)\r
+#endif\r
+\r
+/* ---------- TCP options ---------- */\r
+#ifndef LWIP_TCP\r
+#define LWIP_TCP 1\r
+#endif\r
+\r
+#ifndef TCP_TTL\r
+#define TCP_TTL (IP_DEFAULT_TTL)\r
+#endif\r
+\r
+#ifndef TCP_WND\r
+#define TCP_WND 2048\r
+#endif \r
+\r
+#ifndef TCP_MAXRTX\r
+#define TCP_MAXRTX 12\r
+#endif\r
+\r
+#ifndef TCP_SYNMAXRTX\r
+#define TCP_SYNMAXRTX 6\r
+#endif\r
+\r
+\r
+/* Controls if TCP should queue segments that arrive out of\r
+ order. Define to 0 if your device is low on memory. */\r
+#ifndef TCP_QUEUE_OOSEQ\r
+#define TCP_QUEUE_OOSEQ 1\r
+#endif\r
+\r
+/* TCP Maximum segment size. */\r
+#ifndef TCP_MSS\r
+#define TCP_MSS 128 /* A *very* conservative default. */\r
+#endif\r
+\r
+/* TCP sender buffer space (bytes). */\r
+#ifndef TCP_SND_BUF\r
+#define TCP_SND_BUF 256\r
+#endif\r
+\r
+/* TCP sender buffer space (pbufs). This must be at least = 2 *\r
+ TCP_SND_BUF/TCP_MSS for things to work. */\r
+#ifndef TCP_SND_QUEUELEN\r
+#define TCP_SND_QUEUELEN 4 * TCP_SND_BUF/TCP_MSS\r
+#endif\r
+\r
+\r
+/* Maximum number of retransmissions of data segments. */\r
+\r
+/* Maximum number of retransmissions of SYN segments. */\r
+\r
+/* TCP writable space (bytes). This must be less than or equal\r
+ to TCP_SND_BUF. It is the amount of space which must be\r
+ available in the tcp snd_buf for select to return writable */\r
+#ifndef TCP_SNDLOWAT\r
+#define TCP_SNDLOWAT TCP_SND_BUF/2\r
+#endif\r
+\r
+/* Support loop interface (127.0.0.1) */\r
+#ifndef LWIP_HAVE_LOOPIF\r
+#define LWIP_HAVE_LOOPIF 0\r
+#endif\r
+\r
+#ifndef LWIP_EVENT_API\r
+#define LWIP_EVENT_API 0\r
+#define LWIP_CALLBACK_API 1\r
+#else \r
+#define LWIP_EVENT_API 1\r
+#define LWIP_CALLBACK_API 0\r
+#endif \r
+\r
+#ifndef LWIP_COMPAT_SOCKETS\r
+#define LWIP_COMPAT_SOCKETS 1\r
+#endif\r
+\r
+\r
+#ifndef TCPIP_THREAD_PRIO\r
+#define TCPIP_THREAD_PRIO 1\r
+#endif\r
+\r
+#ifndef SLIPIF_THREAD_PRIO\r
+#define SLIPIF_THREAD_PRIO 1\r
+#endif\r
+\r
+#ifndef PPP_THREAD_PRIO\r
+#define PPP_THREAD_PRIO 1\r
+#endif\r
+\r
+#ifndef DEFAULT_THREAD_PRIO\r
+#define DEFAULT_THREAD_PRIO 1\r
+#endif\r
+\r
+\r
+/* ---------- Socket Options ---------- */\r
+/* Enable SO_REUSEADDR and SO_REUSEPORT options */ \r
+#ifdef SO_REUSE\r
+/* I removed the lot since this was an ugly hack. It broke the raw-API.\r
+ It also came with many ugly goto's, Christiaan Simons. */\r
+#error "SO_REUSE currently unavailable, this was a hack"\r
+#endif \r
+\r
+\r
+/* ---------- Statistics options ---------- */\r
+#ifndef LWIP_STATS\r
+#define LWIP_STATS 1\r
+#endif\r
+\r
+#if LWIP_STATS\r
+\r
+#ifndef LWIP_STATS_DISPLAY\r
+#define LWIP_STATS_DISPLAY 0\r
+#endif\r
+\r
+#ifndef LINK_STATS\r
+#define LINK_STATS 1\r
+#endif\r
+\r
+#ifndef IP_STATS\r
+#define IP_STATS 1\r
+#endif\r
+\r
+#ifndef IPFRAG_STATS\r
+#define IPFRAG_STATS 1\r
+#endif\r
+\r
+#ifndef ICMP_STATS\r
+#define ICMP_STATS 1\r
+#endif\r
+\r
+#ifndef UDP_STATS\r
+#define UDP_STATS 1\r
+#endif\r
+\r
+#ifndef TCP_STATS\r
+#define TCP_STATS 1\r
+#endif\r
+\r
+#ifndef MEM_STATS\r
+#define MEM_STATS 1\r
+#endif\r
+\r
+#ifndef MEMP_STATS\r
+#define MEMP_STATS 1\r
+#endif\r
+\r
+#ifndef PBUF_STATS\r
+#define PBUF_STATS 1\r
+#endif\r
+\r
+#ifndef SYS_STATS\r
+#define SYS_STATS 1\r
+#endif\r
+\r
+#ifndef RAW_STATS\r
+#define RAW_STATS 0\r
+#endif\r
+\r
+#else\r
+\r
+#define LINK_STATS 0\r
+#define IP_STATS 0\r
+#define IPFRAG_STATS 0\r
+#define ICMP_STATS 0\r
+#define UDP_STATS 0\r
+#define TCP_STATS 0\r
+#define MEM_STATS 0\r
+#define MEMP_STATS 0\r
+#define PBUF_STATS 0\r
+#define SYS_STATS 0\r
+#define RAW_STATS 0\r
+#define LWIP_STATS_DISPLAY 0\r
+\r
+#endif /* LWIP_STATS */\r
+\r
+/* ---------- PPP options ---------- */\r
+\r
+#ifndef PPP_SUPPORT\r
+#define PPP_SUPPORT 0 /* Set for PPP */\r
+#endif\r
+\r
+#if PPP_SUPPORT \r
+\r
+#define NUM_PPP 1 /* Max PPP sessions. */\r
+\r
+\r
+\r
+#ifndef PAP_SUPPORT\r
+#define PAP_SUPPORT 0 /* Set for PAP. */\r
+#endif\r
+\r
+#ifndef CHAP_SUPPORT\r
+#define CHAP_SUPPORT 0 /* Set for CHAP. */\r
+#endif\r
+\r
+#define MSCHAP_SUPPORT 0 /* Set for MSCHAP (NOT FUNCTIONAL!) */\r
+#define CBCP_SUPPORT 0 /* Set for CBCP (NOT FUNCTIONAL!) */\r
+#define CCP_SUPPORT 0 /* Set for CCP (NOT FUNCTIONAL!) */\r
+\r
+#ifndef VJ_SUPPORT\r
+#define VJ_SUPPORT 0 /* Set for VJ header compression. */\r
+#endif\r
+\r
+#ifndef MD5_SUPPORT\r
+#define MD5_SUPPORT 0 /* Set for MD5 (see also CHAP) */\r
+#endif\r
+\r
+\r
+/*\r
+ * Timeouts.\r
+ */\r
+#define FSM_DEFTIMEOUT 6 /* Timeout time in seconds */\r
+#define FSM_DEFMAXTERMREQS 2 /* Maximum Terminate-Request transmissions */\r
+#define FSM_DEFMAXCONFREQS 10 /* Maximum Configure-Request transmissions */\r
+#define FSM_DEFMAXNAKLOOPS 5 /* Maximum number of nak loops */\r
+\r
+#define UPAP_DEFTIMEOUT 6 /* Timeout (seconds) for retransmitting req */\r
+#define UPAP_DEFREQTIME 30 /* Time to wait for auth-req from peer */\r
+\r
+#define CHAP_DEFTIMEOUT 6 /* Timeout time in seconds */\r
+#define CHAP_DEFTRANSMITS 10 /* max # times to send challenge */\r
+\r
+\r
+/* Interval in seconds between keepalive echo requests, 0 to disable. */\r
+#if 1\r
+#define LCP_ECHOINTERVAL 0\r
+#else\r
+#define LCP_ECHOINTERVAL 10\r
+#endif\r
+\r
+/* Number of unanswered echo requests before failure. */\r
+#define LCP_MAXECHOFAILS 3\r
+\r
+/* Max Xmit idle time (in jiffies) before resend flag char. */\r
+#define PPP_MAXIDLEFLAG 100\r
+\r
+/*\r
+ * Packet sizes\r
+ *\r
+ * Note - lcp shouldn't be allowed to negotiate stuff outside these\r
+ * limits. See lcp.h in the pppd directory.\r
+ * (XXX - these constants should simply be shared by lcp.c instead\r
+ * of living in lcp.h)\r
+ */\r
+#define PPP_MTU 1500 /* Default MTU (size of Info field) */\r
+#if 0\r
+#define PPP_MAXMTU 65535 - (PPP_HDRLEN + PPP_FCSLEN)\r
+#else\r
+#define PPP_MAXMTU 1500 /* Largest MTU we allow */\r
+#endif\r
+#define PPP_MINMTU 64\r
+#define PPP_MRU 1500 /* default MRU = max length of info field */\r
+#define PPP_MAXMRU 1500 /* Largest MRU we allow */\r
+#define PPP_DEFMRU 296 /* Try for this */\r
+#define PPP_MINMRU 128 /* No MRUs below this */\r
+\r
+\r
+#define MAXNAMELEN 256 /* max length of hostname or name for auth */\r
+#define MAXSECRETLEN 256 /* max length of password or secret */\r
+\r
+#endif /* PPP_SUPPORT */\r
+\r
+/* checksum options - set to zero for hardware checksum support */\r
+\r
+#ifndef CHECKSUM_GEN_IP\r
+#define CHECKSUM_GEN_IP 1\r
+#endif\r
+ \r
+#ifndef CHECKSUM_GEN_UDP\r
+#define CHECKSUM_GEN_UDP 1\r
+#endif\r
+ \r
+#ifndef CHECKSUM_GEN_TCP\r
+#define CHECKSUM_GEN_TCP 1\r
+#endif\r
+ \r
+#ifndef CHECKSUM_CHECK_IP\r
+#define CHECKSUM_CHECK_IP 1\r
+#endif\r
+ \r
+#ifndef CHECKSUM_CHECK_UDP\r
+#define CHECKSUM_CHECK_UDP 1\r
+#endif\r
+\r
+#ifndef CHECKSUM_CHECK_TCP\r
+#define CHECKSUM_CHECK_TCP 1\r
+#endif\r
+\r
+/* Debugging options all default to off */\r
+\r
+#ifndef DBG_TYPES_ON\r
+#define DBG_TYPES_ON 0\r
+#endif\r
+\r
+#ifndef ETHARP_DEBUG\r
+#define ETHARP_DEBUG DBG_OFF\r
+#endif\r
+\r
+#ifndef NETIF_DEBUG\r
+#define NETIF_DEBUG DBG_OFF\r
+#endif\r
+\r
+#ifndef PBUF_DEBUG\r
+#define PBUF_DEBUG DBG_OFF\r
+#endif\r
+\r
+#ifndef API_LIB_DEBUG\r
+#define API_LIB_DEBUG DBG_OFF\r
+#endif\r
+\r
+#ifndef API_MSG_DEBUG\r
+#define API_MSG_DEBUG DBG_OFF\r
+#endif\r
+\r
+#ifndef SOCKETS_DEBUG\r
+#define SOCKETS_DEBUG DBG_OFF\r
+#endif\r
+\r
+#ifndef ICMP_DEBUG\r
+#define ICMP_DEBUG DBG_OFF\r
+#endif\r
+\r
+#ifndef INET_DEBUG\r
+#define INET_DEBUG DBG_OFF\r
+#endif\r
+\r
+#ifndef IP_DEBUG\r
+#define IP_DEBUG DBG_OFF\r
+#endif\r
+\r
+#ifndef IP_REASS_DEBUG\r
+#define IP_REASS_DEBUG DBG_OFF\r
+#endif\r
+\r
+#ifndef RAW_DEBUG\r
+#define RAW_DEBUG DBG_OFF\r
+#endif\r
+\r
+#ifndef MEM_DEBUG\r
+#define MEM_DEBUG DBG_OFF\r
+#endif\r
+\r
+#ifndef MEMP_DEBUG\r
+#define MEMP_DEBUG DBG_OFF\r
+#endif\r
+\r
+#ifndef SYS_DEBUG\r
+#define SYS_DEBUG DBG_OFF\r
+#endif\r
+\r
+#ifndef TCP_DEBUG\r
+#define TCP_DEBUG DBG_OFF\r
+#endif\r
+\r
+#ifndef TCP_INPUT_DEBUG\r
+#define TCP_INPUT_DEBUG DBG_OFF\r
+#endif\r
+\r
+#ifndef TCP_FR_DEBUG\r
+#define TCP_FR_DEBUG DBG_OFF\r
+#endif\r
+\r
+#ifndef TCP_RTO_DEBUG\r
+#define TCP_RTO_DEBUG DBG_OFF\r
+#endif\r
+\r
+#ifndef TCP_REXMIT_DEBUG\r
+#define TCP_REXMIT_DEBUG DBG_OFF\r
+#endif\r
+\r
+#ifndef TCP_CWND_DEBUG\r
+#define TCP_CWND_DEBUG DBG_OFF\r
+#endif\r
+\r
+#ifndef TCP_WND_DEBUG\r
+#define TCP_WND_DEBUG DBG_OFF\r
+#endif\r
+\r
+#ifndef TCP_OUTPUT_DEBUG\r
+#define TCP_OUTPUT_DEBUG DBG_OFF\r
+#endif\r
+\r
+#ifndef TCP_RST_DEBUG\r
+#define TCP_RST_DEBUG DBG_OFF\r
+#endif\r
+\r
+#ifndef TCP_QLEN_DEBUG\r
+#define TCP_QLEN_DEBUG DBG_OFF\r
+#endif\r
+\r
+#ifndef UDP_DEBUG\r
+#define UDP_DEBUG DBG_OFF\r
+#endif\r
+\r
+#ifndef TCPIP_DEBUG\r
+#define TCPIP_DEBUG DBG_OFF\r
+#endif\r
+\r
+#ifndef PPP_DEBUG \r
+#define PPP_DEBUG DBG_OFF\r
+#endif\r
+\r
+#ifndef SLIP_DEBUG \r
+#define SLIP_DEBUG DBG_OFF\r
+#endif\r
+\r
+#ifndef DHCP_DEBUG \r
+#define DHCP_DEBUG DBG_OFF\r
+#endif\r
+\r
+#ifndef SNMP_MSG_DEBUG \r
+#define SNMP_MSG_DEBUG DBG_OFF\r
+#endif\r
+\r
+#ifndef SNMP_MIB_DEBUG \r
+#define SNMP_MIB_DEBUG DBG_OFF\r
+#endif\r
+\r
+#ifndef DBG_MIN_LEVEL\r
+#define DBG_MIN_LEVEL DBG_LEVEL_OFF\r
+#endif\r
+\r
+#endif /* __LWIP_OPT_H__ */\r
+\r
+\r
+\r
--- /dev/null
+/* This header file is part of the ATMEL FREERTOS-0.9.0 Release */\r
+\r
+/*This file has been prepared for Doxygen automatic documentation generation.*/\r
+/*! \file *********************************************************************\r
+ *\r
+ * \brief lwIP configuration for AVR32 UC3.\r
+ *\r
+ * - Compiler: GNU GCC for AVR32\r
+ * - Supported devices: All AVR32 devices can be used.\r
+ * - AppNote:\r
+ *\r
+ * \author Atmel Corporation: http://www.atmel.com \n\r
+ * Support email: avr32@atmel.com\r
+ *\r
+ *****************************************************************************/\r
+\r
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of ATMEL may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND\r
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,\r
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\r
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\r
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF\r
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ */\r
+\r
+\r
+\r
+#ifndef __LWIPOPTS_H__\r
+#define __LWIPOPTS_H__\r
+\r
+/* Include user defined options first */\r
+#include "conf_eth.h"\r
+// #include "lwip/debug.h"\r
+\r
+/* Define default values for unconfigured parameters. */\r
+#define LWIP_NOASSERT 1 // To suppress some errors for now (no debug output)\r
+\r
+/* These two control is reclaimer functions should be compiled\r
+ in. Should always be turned on (1). */\r
+#define MEM_RECLAIM 1\r
+#define MEMP_RECLAIM 1\r
+\r
+\r
+/* Platform specific locking */\r
+\r
+/*\r
+ * enable SYS_LIGHTWEIGHT_PROT in lwipopts.h if you want inter-task protection\r
+ * for certain critical regions during buffer allocation, deallocation and memory\r
+ * allocation and deallocation.\r
+ */\r
+#define SYS_LIGHTWEIGHT_PROT 1\r
+\r
+/* ---------- Memory options ---------- */\r
+// #define MEM_LIBC_MALLOC 0\r
+\r
+/* MEM_ALIGNMENT: should be set to the alignment of the CPU for which\r
+ lwIP is compiled. 4 byte alignment -> define MEM_ALIGNMENT to 4, 2\r
+ byte alignment -> define MEM_ALIGNMENT to 2. */\r
+#define MEM_ALIGNMENT 4\r
+\r
+/* MEM_SIZE: the size of the heap memory. If the application will send\r
+a lot of data that needs to be copied, this should be set high. */\r
+#define MEM_SIZE 3 * 1024\r
+\r
+// #define MEMP_SANITY_CHECK 1\r
+\r
+/* MEMP_NUM_PBUF: the number of memp struct pbufs. If the application\r
+ sends a lot of data out of ROM (or other static memory), this\r
+ should be set high. */\r
+#define MEMP_NUM_PBUF 6\r
+\r
+/* Number of raw connection PCBs */\r
+#define MEMP_NUM_RAW_PCB 1\r
+\r
+#if (TFTP_USED == 1)\r
+ /* ---------- UDP options ---------- */\r
+ #define LWIP_UDP 1\r
+ #define UDP_TTL 255\r
+ /* MEMP_NUM_UDP_PCB: the number of UDP protocol control blocks. One\r
+ per active UDP "connection". */\r
+\r
+ #define MEMP_NUM_UDP_PCB 1\r
+#else\r
+ /* ---------- UDP options ---------- */\r
+ #define LWIP_UDP 0\r
+ #define UDP_TTL 0\r
+ /* MEMP_NUM_UDP_PCB: the number of UDP protocol control blocks. One\r
+ per active UDP "connection". */\r
+\r
+ #define MEMP_NUM_UDP_PCB 0\r
+#endif\r
+\r
+/* MEMP_NUM_TCP_PCB: the number of simulatenously active TCP\r
+ connections. */\r
+#define MEMP_NUM_TCP_PCB 14\r
+/* MEMP_NUM_TCP_PCB_LISTEN: the number of listening TCP\r
+ connections. */\r
+#define MEMP_NUM_TCP_PCB_LISTEN 2\r
+/* MEMP_NUM_TCP_SEG: the number of simultaneously queued TCP\r
+ segments. */\r
+#define MEMP_NUM_TCP_SEG 6\r
+/* MEMP_NUM_SYS_TIMEOUT: the number of simulateously active\r
+ timeouts. */\r
+#define MEMP_NUM_SYS_TIMEOUT 6\r
+\r
+/* The following four are used only with the sequential API and can be\r
+ set to 0 if the application only will use the raw API. */\r
+/* MEMP_NUM_NETBUF: the number of struct netbufs. */\r
+#define MEMP_NUM_NETBUF 3\r
+/* MEMP_NUM_NETCONN: the number of struct netconns. */\r
+#define MEMP_NUM_NETCONN 6\r
+/* MEMP_NUM_APIMSG: the number of struct api_msg, used for\r
+ communication between the TCP/IP stack and the sequential\r
+ programs. */\r
+#define MEMP_NUM_API_MSG 4\r
+/* MEMP_NUM_TCPIPMSG: the number of struct tcpip_msg, which is used\r
+ for sequential API communication and incoming packets. Used in\r
+ src/api/tcpip.c. */\r
+#define MEMP_NUM_TCPIP_MSG 4\r
+\r
+\r
+/* ---------- Pbuf options ---------- */\r
+/* PBUF_POOL_SIZE: the number of buffers in the pbuf pool. */\r
+\r
+#define PBUF_POOL_SIZE 6\r
+\r
+/* PBUF_POOL_BUFSIZE: the size of each pbuf in the pbuf pool. */\r
+\r
+#define PBUF_POOL_BUFSIZE 500\r
+\r
+/* PBUF_LINK_HLEN: the number of bytes that should be allocated for a\r
+ link level header. */\r
+#define PBUF_LINK_HLEN 16\r
+\r
+/* ---------- TCP options ---------- */\r
+#define LWIP_TCP 1\r
+#define TCP_TTL 255\r
+/* TCP receive window. */\r
+#define TCP_WND 1500\r
+/* Controls if TCP should queue segments that arrive out of\r
+ order. Define to 0 if your device is low on memory. */\r
+#define TCP_QUEUE_OOSEQ 1\r
+\r
+/* TCP Maximum segment size. */\r
+#define TCP_MSS 1500\r
+\r
+/* TCP sender buffer space (bytes). */\r
+#define TCP_SND_BUF 2150\r
+\r
+/* TCP sender buffer space (pbufs). This must be at least = 2 *\r
+ TCP_SND_BUF/TCP_MSS for things to work. */\r
+#define TCP_SND_QUEUELEN 6 * TCP_SND_BUF/TCP_MSS\r
+\r
+\r
+\r
+/* Maximum number of retransmissions of data segments. */\r
+#define TCP_MAXRTX 12\r
+\r
+/* Maximum number of retransmissions of SYN segments. */\r
+#define TCP_SYNMAXRTX 4\r
+\r
+/* ---------- ARP options ---------- */\r
+#define ARP_TABLE_SIZE 10\r
+#define ARP_QUEUEING 0\r
+\r
+/* ---------- IP options ---------- */\r
+/* Define IP_FORWARD to 1 if you wish to have the ability to forward\r
+ IP packets across network interfaces. If you are going to run lwIP\r
+ on a device with only one network interface, define this to 0. */\r
+#define IP_FORWARD 0\r
+\r
+/* If defined to 1, IP options are allowed (but not parsed). If\r
+ defined to 0, all packets with IP options are dropped. */\r
+#define IP_OPTIONS 1\r
+\r
+/* ---------- ICMP options ---------- */\r
+#define ICMP_TTL 255\r
+\r
+\r
+/* ---------- DHCP options ---------- */\r
+/* Define LWIP_DHCP to 1 if you want DHCP configuration of\r
+ interfaces. DHCP is not implemented in lwIP 0.5.1, however, so\r
+ turning this on does currently not work. */\r
+#define LWIP_DHCP 0\r
+\r
+/* 1 if you want to do an ARP check on the offered address\r
+ (recommended). */\r
+#define DHCP_DOES_ARP_CHECK 1\r
+\r
+#define TCPIP_THREAD_PRIO lwipINTERFACE_TASK_PRIORITY\r
+\r
+/* ---------- Statistics options ---------- */\r
+#define LWIP_STATS 1\r
+\r
+#define LWIP_STATS_DISPLAY 1\r
+\r
+#if LWIP_STATS\r
+#define LINK_STATS 1\r
+#define IP_STATS 1\r
+#define ICMP_STATS 1\r
+#define UDP_STATS 1\r
+#define TCP_STATS 1\r
+#define MEM_STATS 1\r
+#define MEMP_STATS 1\r
+#define PBUF_STATS 1\r
+#define SYS_STATS 1\r
+#endif /* STATS */\r
+\r
+\r
+#endif /* __LWIPOPTS_H__ */\r
--- /dev/null
+/* This source file is part of the ATMEL FREERTOS-0.9.0 Release */\r
+\r
+/*This file has been prepared for Doxygen automatic documentation generation.*/\r
+/*! \file *********************************************************************\r
+ *\r
+ * \brief lwIP abstraction layer for AVR32 UC3.\r
+ *\r
+ * - Compiler: GNU GCC for AVR32\r
+ * - Supported devices: All AVR32 devices can be used.\r
+ * - AppNote:\r
+ *\r
+ * \author Atmel Corporation: http://www.atmel.com \n\r
+ * Support email: avr32@atmel.com\r
+ *\r
+ *****************************************************************************/\r
+\r
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of ATMEL may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND\r
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,\r
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\r
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\r
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF\r
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ */\r
+\r
+\r
+#include "conf_eth.h"\r
+\r
+#if (HTTP_USED == 1)\r
+ #include "BasicWEB.h"\r
+#endif\r
+\r
+#if (TFTP_USED == 1)\r
+ #include "BasicTFTP.h"\r
+#endif\r
+\r
+#if (SMTP_USED == 1)\r
+ #include "BasicSMTP.h"\r
+#endif\r
+\r
+/* lwIP includes. */\r
+#include "lwip/debug.h"\r
+#include "lwip/def.h"\r
+#include "lwip/sys.h"\r
+#include "lwip/mem.h"\r
+\r
+/* Message queue constants. */\r
+#define archMESG_QUEUE_LENGTH ( 6 )\r
+#define archPOST_BLOCK_TIME_MS ( ( unsigned portLONG ) 10000 )\r
+\r
+struct timeoutlist \r
+{\r
+ struct sys_timeouts timeouts;\r
+ xTaskHandle pid;\r
+};\r
+\r
+static struct timeoutlist timeoutlist[SYS_THREAD_MAX];\r
+static u16_t nextthread = 0;\r
+int intlevel = 0;\r
+\r
+extern void ethernetif_input( void * pvParameters );\r
+\r
+/*-----------------------------------------------------------------------------------*/\r
+// Creates an empty mailbox.\r
+sys_mbox_t\r
+sys_mbox_new(void)\r
+{\r
+ xQueueHandle mbox;\r
+\r
+ mbox = xQueueCreate( archMESG_QUEUE_LENGTH, sizeof( void * ) );\r
+\r
+ return mbox;\r
+}\r
+\r
+/*-----------------------------------------------------------------------------------*/\r
+/*\r
+ Deallocates a mailbox. If there are messages still present in the\r
+ mailbox when the mailbox is deallocated, it is an indication of a\r
+ programming error in lwIP and the developer should be notified.\r
+*/\r
+void\r
+sys_mbox_free(sys_mbox_t mbox)\r
+{\r
+ if( uxQueueMessagesWaiting( mbox ) )\r
+ {\r
+ /* Line for breakpoint. Should never break here! */\r
+ __asm volatile ( "NOP" );\r
+ }\r
+\r
+ vQueueDelete( mbox );\r
+}\r
+\r
+/*-----------------------------------------------------------------------------------*/\r
+// Posts the "msg" to the mailbox.\r
+void\r
+sys_mbox_post(sys_mbox_t mbox, void *data)\r
+{ \r
+ xQueueSend( mbox, &data, ( portTickType ) ( archPOST_BLOCK_TIME_MS / portTICK_RATE_MS ) );\r
+}\r
+\r
+\r
+/*-----------------------------------------------------------------------------------*/\r
+/*\r
+ Blocks the thread until a message arrives in the mailbox, but does\r
+ not block the thread longer than "timeout" milliseconds (similar to\r
+ the sys_arch_sem_wait() function). The "msg" argument is a result\r
+ parameter that is set by the function (i.e., by doing "*msg =\r
+ ptr"). The "msg" parameter maybe NULL to indicate that the message\r
+ should be dropped.\r
+\r
+ The return values are the same as for the sys_arch_sem_wait() function:\r
+ Number of milliseconds spent waiting or SYS_ARCH_TIMEOUT if there was a\r
+ timeout.\r
+\r
+ Note that a function with a similar name, sys_mbox_fetch(), is\r
+ implemented by lwIP. \r
+*/\r
+u32_t sys_arch_mbox_fetch(sys_mbox_t mbox, void **msg, u32_t timeout)\r
+{\r
+void *dummyptr;\r
+portTickType StartTime, EndTime, Elapsed;\r
+\r
+ StartTime = xTaskGetTickCount();\r
+\r
+ if( msg == NULL )\r
+ {\r
+ msg = &dummyptr;\r
+ }\r
+ \r
+ if( timeout != 0 )\r
+ {\r
+ if(pdTRUE == xQueueReceive( mbox, &(*msg), timeout ) )\r
+ {\r
+ EndTime = xTaskGetTickCount();\r
+ Elapsed = EndTime - StartTime;\r
+ if( Elapsed == 0 )\r
+ {\r
+ Elapsed = 1;\r
+ }\r
+ return ( Elapsed );\r
+ }\r
+ else // timed out blocking for message\r
+ {\r
+ *msg = NULL;\r
+ return SYS_ARCH_TIMEOUT;\r
+ }\r
+ }\r
+ else // block forever for a message.\r
+ {\r
+ while( pdTRUE != xQueueReceive( mbox, &(*msg), 10000 ) ) // time is arbitrary\r
+ {\r
+ ;\r
+ }\r
+ EndTime = xTaskGetTickCount();\r
+ Elapsed = EndTime - StartTime;\r
+ if( Elapsed == 0 )\r
+ {\r
+ Elapsed = 1;\r
+ }\r
+ return ( Elapsed ); // return time blocked TBD test\r
+ }\r
+}\r
+\r
+/*-----------------------------------------------------------------------------------*/\r
+// Creates and returns a new semaphore. The "count" argument specifies\r
+// the initial state of the semaphore. TBD finish and test\r
+sys_sem_t\r
+sys_sem_new(u8_t count)\r
+{\r
+ xSemaphoreHandle xSemaphore = NULL;\r
+\r
+ portENTER_CRITICAL();\r
+ vSemaphoreCreateBinary( xSemaphore );\r
+ if( xSemaphore == NULL )\r
+ {\r
+ return NULL; // TBD need assert\r
+ }\r
+ if(count == 0) // Means we want the sem to be unavailable at init state.\r
+ {\r
+ xSemaphoreTake(xSemaphore,1);\r
+ }\r
+ portEXIT_CRITICAL();\r
+\r
+ return xSemaphore;\r
+}\r
+\r
+/*-----------------------------------------------------------------------------------*/\r
+/*\r
+ Blocks the thread while waiting for the semaphore to be\r
+ signaled. If the "timeout" argument is non-zero, the thread should\r
+ only be blocked for the specified time (measured in\r
+ milliseconds).\r
+\r
+ If the timeout argument is non-zero, the return value is the number of\r
+ milliseconds spent waiting for the semaphore to be signaled. If the\r
+ semaphore wasn't signaled within the specified time, the return value is\r
+ SYS_ARCH_TIMEOUT. If the thread didn't have to wait for the semaphore\r
+ (i.e., it was already signaled), the function may return zero.\r
+\r
+ Notice that lwIP implements a function with a similar name,\r
+ sys_sem_wait(), that uses the sys_arch_sem_wait() function.\r
+*/\r
+u32_t\r
+sys_arch_sem_wait(sys_sem_t sem, u32_t timeout)\r
+{\r
+portTickType StartTime, EndTime, Elapsed;\r
+\r
+ StartTime = xTaskGetTickCount();\r
+\r
+ if( timeout != 0)\r
+ {\r
+ if( xSemaphoreTake( sem, timeout ) == pdTRUE )\r
+ {\r
+ EndTime = xTaskGetTickCount();\r
+ Elapsed = EndTime - StartTime;\r
+ if( Elapsed == 0 )\r
+ {\r
+ Elapsed = 1;\r
+ }\r
+ return (Elapsed); // return time blocked TBD test\r
+ }\r
+ else\r
+ {\r
+ return SYS_ARCH_TIMEOUT;\r
+ }\r
+ }\r
+ else // must block without a timeout\r
+ {\r
+ while( xSemaphoreTake( sem, 10000 ) != pdTRUE )\r
+ {\r
+ ;\r
+ }\r
+ EndTime = xTaskGetTickCount();\r
+ Elapsed = EndTime - StartTime;\r
+ if( Elapsed == 0 )\r
+ {\r
+ Elapsed = 1;\r
+ }\r
+\r
+ return ( Elapsed ); // return time blocked\r
+ \r
+ }\r
+}\r
+\r
+/*-----------------------------------------------------------------------------------*/\r
+// Signals a semaphore\r
+void\r
+sys_sem_signal(sys_sem_t sem)\r
+{\r
+ xSemaphoreGive( sem );\r
+}\r
+\r
+/*-----------------------------------------------------------------------------------*/\r
+// Deallocates a semaphore\r
+void\r
+sys_sem_free(sys_sem_t sem)\r
+{\r
+ vQueueDelete( sem );\r
+}\r
+\r
+/*-----------------------------------------------------------------------------------*/\r
+// Initialize sys arch\r
+void\r
+sys_init(void)\r
+{\r
+\r
+ int i;\r
+\r
+ // Initialize the the per-thread sys_timeouts structures\r
+ // make sure there are no valid pids in the list\r
+ for(i = 0; i < SYS_THREAD_MAX; i++)\r
+ {\r
+ timeoutlist[i].pid = 0;\r
+ timeoutlist[i].timeouts.next = NULL;\r
+ }\r
+\r
+ // keep track of how many threads have been created\r
+ nextthread = 0;\r
+}\r
+\r
+/*-----------------------------------------------------------------------------------*/\r
+/*\r
+ Returns a pointer to the per-thread sys_timeouts structure. In lwIP,\r
+ each thread has a list of timeouts which is represented as a linked\r
+ list of sys_timeout structures. The sys_timeouts structure holds a\r
+ pointer to a linked list of timeouts. This function is called by\r
+ the lwIP timeout scheduler and must not return a NULL value. \r
+\r
+ In a single threaded sys_arch implementation, this function will\r
+ simply return a pointer to a global sys_timeouts variable stored in\r
+ the sys_arch module.\r
+*/\r
+struct sys_timeouts *\r
+sys_arch_timeouts(void)\r
+{\r
+int i;\r
+xTaskHandle pid;\r
+struct timeoutlist *tl; \r
+\r
+ pid = xTaskGetCurrentTaskHandle( );\r
+\r
+ for(i = 0; i < nextthread; i++)\r
+ {\r
+ tl = &(timeoutlist[i]);\r
+ if(tl->pid == pid)\r
+ {\r
+ return &(tl->timeouts);\r
+ }\r
+ }\r
+\r
+\r
+ // If we're here, this means the scheduler gave the focus to the task as it was\r
+ // being created(because of a higher priority). Since timeoutlist[]Â update is\r
+ // done just after the task creation, the array is not up-to-date.\r
+ // => the last array entry must be the one of the current task.\r
+ return( &( timeoutlist[nextthread].timeouts ) );\r
+/*\r
+ // Error\r
+ return NULL;\r
+*/\r
+}\r
+\r
+/*-----------------------------------------------------------------------------------*/\r
+/*-----------------------------------------------------------------------------------*/\r
+// TBD \r
+/*-----------------------------------------------------------------------------------*/\r
+/*\r
+ Starts a new thread with priority "prio" that will begin its execution in the\r
+ function "thread()". The "arg" argument will be passed as an argument to the\r
+ thread() function. The id of the new thread is returned. Both the id and\r
+ the priority are system dependent.\r
+*/\r
+sys_thread_t sys_thread_new(void (* thread)(void *arg), void *arg, int prio)\r
+{\r
+xTaskHandle CreatedTask;\r
+int result = pdFAIL;\r
+static int iCall = 0;\r
+\r
+ if( thread == ethernetif_input )\r
+ {\r
+ result = xTaskCreate( thread, ( signed portCHAR * ) "ETHINT", netifINTERFACE_TASK_STACK_SIZE, arg, prio, &CreatedTask );\r
+ }\r
+ else if( iCall == 0 )\r
+ {\r
+ /* The first time this is called we are creating the lwIP handler. */\r
+ result = xTaskCreate( thread, ( signed portCHAR * ) "lwIP", lwipINTERFACE_STACK_SIZE, arg, prio, &CreatedTask );\r
+ iCall++;\r
+ }\r
+#if (HTTP_USED == 1)\r
+ else if (thread == vBasicWEBServer)\r
+ {\r
+ result = xTaskCreate( thread, ( signed portCHAR * ) "WEB", lwipBASIC_WEB_SERVER_STACK_SIZE, arg, prio, &CreatedTask );\r
+ }\r
+#endif\r
+#if (TFTP_USED == 1)\r
+ else if (thread == vBasicTFTPServer)\r
+ {\r
+ result = xTaskCreate( thread, ( signed portCHAR * ) "TFTP", lwipBASIC_TFTP_SERVER_STACK_SIZE, arg, prio, &CreatedTask );\r
+ }\r
+#endif\r
+#if (SMTP_USED == 1)\r
+ else if (thread == vBasicSMTPHost)\r
+ {\r
+ result = xTaskCreate( thread, ( signed portCHAR * ) "SMTP", lwipBASIC_SMTP_HOST_STACK_SIZE, arg, prio, &CreatedTask );\r
+ }\r
+#endif\r
+\r
+\r
+ // For each task created, store the task handle (pid) in the timers array.\r
+ // This scheme doesn't allow for threads to be deleted\r
+ timeoutlist[nextthread++].pid = CreatedTask;\r
+\r
+ if(result == pdPASS)\r
+ {\r
+ return CreatedTask;\r
+ }\r
+ else\r
+ {\r
+ return NULL;\r
+ }\r
+}\r
+\r
+/*\r
+ This optional function does a "fast" critical region protection and returns\r
+ the previous protection level. This function is only called during very short\r
+ critical regions. An embedded system which supports ISR-based drivers might\r
+ want to implement this function by disabling interrupts. Task-based systems\r
+ might want to implement this by using a mutex or disabling tasking. This\r
+ function should support recursive calls from the same task or interrupt. In\r
+ other words, sys_arch_protect() could be called while already protected. In\r
+ that case the return value indicates that it is already protected.\r
+\r
+ sys_arch_protect() is only required if your port is supporting an operating\r
+ system.\r
+*/\r
+sys_prot_t sys_arch_protect(void)\r
+{\r
+ vPortEnterCritical();\r
+ return 1;\r
+}\r
+\r
+/*\r
+ This optional function does a "fast" set of critical region protection to the\r
+ value specified by pval. See the documentation for sys_arch_protect() for\r
+ more information. This function is only required if your port is supporting\r
+ an operating system.\r
+*/\r
+void sys_arch_unprotect(sys_prot_t pval)\r
+{ \r
+ ( void ) pval;\r
+ vPortExitCritical();\r
+}\r
+\r
--- /dev/null
+/* This source file is part of the ATMEL FREERTOS-0.9.0 Release */\r
+\r
+/*This file has been prepared for Doxygen automatic documentation generation.*/\r
+/*! \file *********************************************************************\r
+ *\r
+ * \brief FreeRTOS Led Driver example for AVR32 UC3.\r
+ *\r
+ * - Compiler: IAR EWAVR32 and GNU GCC for AVR32\r
+ * - Supported devices: All AVR32 devices can be used.\r
+ * - AppNote:\r
+ *\r
+ * \author Atmel Corporation: http://www.atmel.com \n\r
+ * Support email: avr32@atmel.com\r
+ *\r
+ *****************************************************************************/\r
+\r
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of ATMEL may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND\r
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,\r
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\r
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\r
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF\r
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ */\r
+\r
+\r
+#if __GNUC__\r
+# include <avr32/io.h>\r
+#elif __ICCAVR32__\r
+# include <avr32/iouc3a0512.h>\r
+#else\r
+# error Unknown compiler\r
+#endif\r
+\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "partest.h"\r
+\r
+\r
+/*-----------------------------------------------------------\r
+ * Simple parallel port IO routines.\r
+ *-----------------------------------------------------------*/\r
+\r
+#define partstALL_OUTPUTS_OFF ( ( unsigned portCHAR ) 0x00 )\r
+#define partstMAX_OUTPUT_LED ( ( unsigned portCHAR ) 8 )\r
+\r
+static volatile unsigned portCHAR ucCurrentOutputValue = partstALL_OUTPUTS_OFF; /*lint !e956 File scope parameters okay here. */\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestInitialise( void )\r
+{\r
+ LED_Display(partstALL_OUTPUTS_OFF); /* Start with all LEDs off. */\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue )\r
+{\r
+unsigned portCHAR ucBit;\r
+\r
+ if( uxLED >= partstMAX_OUTPUT_LED )\r
+ {\r
+ return;\r
+ }\r
+\r
+ ucBit = ( ( unsigned portCHAR ) 1 ) << uxLED;\r
+\r
+ vTaskSuspendAll();\r
+ {\r
+ if( xValue == pdTRUE )\r
+ {\r
+ ucCurrentOutputValue |= ucBit;\r
+ }\r
+ else\r
+ {\r
+ ucCurrentOutputValue &= ~ucBit;\r
+ }\r
+\r
+ LED_Display(ucCurrentOutputValue);\r
+ }\r
+ xTaskResumeAll();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestToggleLED( unsigned portBASE_TYPE uxLED )\r
+{\r
+ unsigned portCHAR ucBit;\r
+\r
+ if( uxLED >= partstMAX_OUTPUT_LED )\r
+ {\r
+ return;\r
+ }\r
+\r
+ ucBit = ( ( unsigned portCHAR ) 1 ) << uxLED;\r
+\r
+ vTaskSuspendAll();\r
+ {\r
+ ucCurrentOutputValue ^= ucBit;\r
+ LED_Display(ucCurrentOutputValue);\r
+ }\r
+ xTaskResumeAll();\r
+}\r
+\r
--- /dev/null
+/* This source file is part of the ATMEL FREERTOS-0.9.0 Release */\r
+\r
+/*This file has been prepared for Doxygen automatic documentation generation.*/\r
+/*! \file *********************************************************************\r
+ *\r
+ * \brief FreeRTOS serial port for AVR32 UC3.\r
+ *\r
+ * - Compiler: IAR EWAVR32 and GNU GCC for AVR32\r
+ * - Supported devices: All AVR32 devices can be used.\r
+ * - AppNote:\r
+ *\r
+ * \author Atmel Corporation: http://www.atmel.com \n\r
+ * Support email: avr32@atmel.com\r
+ *\r
+ *****************************************************************************/\r
+\r
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of ATMEL may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND\r
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,\r
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\r
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\r
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF\r
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ */\r
+\r
+\r
+/*\r
+ BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER FOR USART0.\r
+*/\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "queue.h"\r
+#include "task.h"\r
+\r
+/* Demo application includes. */\r
+#include "serial.h"\r
+#if __GNUC__\r
+# include <avr32/io.h>\r
+#elif __ICCAVR32__\r
+# include <avr32/iouc3a0512.h>\r
+#else\r
+# error Unknown compiler\r
+#endif\r
+#include "board.h"\r
+#include "gpio.h"\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Constants to setup and access the USART. */\r
+#define serINVALID_COMPORT_HANDLER ( ( xComPortHandle ) 0 )\r
+#define serINVALID_QUEUE ( ( xQueueHandle ) 0 )\r
+#define serHANDLE ( ( xComPortHandle ) 1 )\r
+#define serNO_BLOCK ( ( portTickType ) 0 )\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Queues used to hold received characters, and characters waiting to be\r
+transmitted. */\r
+static xQueueHandle xRxedChars;\r
+static xQueueHandle xCharsForTx;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Forward declaration. */\r
+static void vprvSerialCreateQueues( unsigned portBASE_TYPE uxQueueLength,\r
+ xQueueHandle *pxRxedChars,\r
+ xQueueHandle *pxCharsForTx );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+#if __GNUC__\r
+__attribute__((__noinline__))\r
+#elif __ICCAVR32__\r
+#pragma optimize = no_inline\r
+#endif\r
+static portBASE_TYPE prvUSART0_ISR_NonNakedBehaviour( void )\r
+{\r
+ /* Now we can declare the local variables. */\r
+ signed portCHAR cChar;\r
+ portBASE_TYPE xTaskWokenByTx = pdFALSE, xTaskWokenByRx = pdFALSE;\r
+ unsigned portLONG ulStatus;\r
+ volatile avr32_usart_t *usart0 = &AVR32_USART0;\r
+ portBASE_TYPE retstatus;\r
+\r
+ /* What caused the interrupt? */\r
+ ulStatus = usart0->csr & usart0->imr;\r
+\r
+ if (ulStatus & AVR32_USART_CSR_TXRDY_MASK)\r
+ {\r
+ /* The interrupt was caused by the THR becoming empty. Are there any\r
+ more characters to transmit? */\r
+ /* Because FreeRTOS is not supposed to run with nested interrupts, put all OS\r
+ calls in a critical section . */\r
+ portENTER_CRITICAL();\r
+ retstatus = xQueueReceiveFromISR(xCharsForTx, &cChar, &xTaskWokenByTx);\r
+ portEXIT_CRITICAL();\r
+ if (retstatus == pdTRUE)\r
+ {\r
+ /* A character was retrieved from the queue so can be sent to the\r
+ THR now. */\r
+ usart0->thr = cChar;\r
+ }\r
+ else\r
+ {\r
+ /* Queue empty, nothing to send so turn off the Tx interrupt. */\r
+ usart0->idr = AVR32_USART_IDR_TXRDY_MASK;\r
+ }\r
+ }\r
+\r
+ if (ulStatus & AVR32_USART_CSR_RXRDY_MASK)\r
+ {\r
+ /* The interrupt was caused by the receiver getting data. */\r
+ cChar = usart0->rhr; //TODO\r
+\r
+ /* Because FreeRTOS is not supposed to run with nested interrupts, put all OS\r
+ calls in a critical section . */\r
+ portENTER_CRITICAL();\r
+ retstatus = xQueueSendFromISR(xRxedChars, &cChar, pdFALSE);\r
+ portEXIT_CRITICAL();\r
+ if (retstatus)\r
+ {\r
+ xTaskWokenByRx = pdTRUE;\r
+ }\r
+ }\r
+\r
+ /* The return value will be used by portEXIT_SWITCHING_ISR() to know if it\r
+ should perform a vTaskSwitchContext(). */\r
+ return ( xTaskWokenByTx || xTaskWokenByRx );\r
+}\r
+\r
+\r
+/*\r
+ * USART0 interrupt service routine.\r
+ */\r
+#if __GNUC__\r
+__attribute__((__naked__))\r
+#elif __ICCAVR32__\r
+#pragma shadow_registers = full // All registers shadowed\r
+#pragma handler = AVR32_USART0_IRQ_GROUP, 0\r
+__interrupt\r
+#endif\r
+static void vUSART0_ISR( void )\r
+{\r
+\r
+ /* This ISR can cause a context switch, so the first statement must be a\r
+ call to the portENTER_SWITCHING_ISR() macro. This must be BEFORE any\r
+ variable declarations. */\r
+ portENTER_SWITCHING_ISR();\r
+ prvUSART0_ISR_NonNakedBehaviour();\r
+ /* Exit the ISR. If a task was woken by either a character being received\r
+ or transmitted then a context switch will occur. */\r
+ portEXIT_SWITCHING_ISR();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+\r
+\r
+/*\r
+ * Init the serial port for the Minimal implementation.\r
+ */\r
+xComPortHandle xSerialPortInitMinimal( unsigned portLONG ulWantedBaud, unsigned portBASE_TYPE uxQueueLength )\r
+{\r
+ xComPortHandle xReturn = serHANDLE;\r
+ volatile avr32_usart_t *usart0 = &AVR32_USART0;\r
+ int cd; /* USART0 Clock Divider. */\r
+\r
+ /* Create the rx and tx queues. */\r
+ vprvSerialCreateQueues( uxQueueLength, &xRxedChars, &xCharsForTx );\r
+\r
+ /* Configure USART0. */\r
+ if( ( xRxedChars != serINVALID_QUEUE ) &&\r
+ ( xCharsForTx != serINVALID_QUEUE ) &&\r
+ ( ulWantedBaud != ( unsigned portLONG ) 0 ) )\r
+ {\r
+ portENTER_CRITICAL();\r
+ {\r
+ /**\r
+ ** Reset USART0.\r
+ **/\r
+ /* Disable all USART0 interrupt sources to begin... */\r
+ usart0->idr = 0xFFFFFFFF;\r
+\r
+ /* Reset mode and other registers that could cause unpredictable\r
+ behaviour after reset */\r
+ usart0->mr = 0; /* Reset Mode register. */\r
+ usart0->rtor = 0; /* Reset Receiver Time-out register. */\r
+ usart0->ttgr = 0; /* Reset Transmitter Timeguard register. */\r
+\r
+ /* Shutdown RX and TX, reset status bits, reset iterations in CSR, reset NACK\r
+ and turn off DTR and RTS */\r
+ usart0->cr = AVR32_USART_CR_RSTRX_MASK |\r
+ AVR32_USART_CR_RSTTX_MASK |\r
+ AVR32_USART_CR_RXDIS_MASK |\r
+ AVR32_USART_CR_TXDIS_MASK |\r
+ AVR32_USART_CR_RSTSTA_MASK |\r
+ AVR32_USART_CR_RSTIT_MASK |\r
+ AVR32_USART_CR_RSTNACK_MASK |\r
+ AVR32_USART_CR_DTRDIS_MASK |\r
+ AVR32_USART_CR_RTSDIS_MASK;\r
+\r
+ /**\r
+ ** Configure USART0.\r
+ **/\r
+ /* Enable USART0 RXD & TXD pins. */\r
+ gpio_enable_module_pin(AVR32_USART0_RXD_0_PIN, AVR32_USART0_RXD_0_FUNCTION);\r
+ gpio_enable_module_pin(AVR32_USART0_TXD_0_PIN, AVR32_USART0_TXD_0_FUNCTION);\r
+\r
+ /* Set the USART0 baudrate to be as close as possible to the wanted baudrate. */\r
+ /*\r
+ * ** BAUDRATE CALCULATION **\r
+ *\r
+ * Selected Clock Selected Clock\r
+ * baudrate = ---------------- or baudrate = ----------------\r
+ * 16 x CD 8 x CD\r
+ *\r
+ * (with 16x oversampling) (with 8x oversampling)\r
+ */\r
+ if ( ulWantedBaud < (configCPU_CLOCK_HZ/16) ){\r
+ /* Use 8x oversampling */\r
+ usart0->mr |= (1<<AVR32_USART_MR_OVER_OFFSET);\r
+ cd = configCPU_CLOCK_HZ / (8*ulWantedBaud);\r
+\r
+ if (cd < 2) {\r
+ return serINVALID_COMPORT_HANDLER;\r
+ }\r
+ usart0->brgr = (cd << AVR32_USART_BRGR_CD_OFFSET);\r
+ } else {\r
+ /* Use 16x oversampling */\r
+ usart0->mr &= ~(1<<AVR32_USART_MR_OVER_OFFSET);\r
+ cd = configCPU_CLOCK_HZ / (16*ulWantedBaud);\r
+\r
+ if (cd > 65535) {\r
+ /* Baudrate is too low */\r
+ return serINVALID_COMPORT_HANDLER;\r
+ }\r
+ }\r
+ usart0->brgr = (cd << AVR32_USART_BRGR_CD_OFFSET);\r
+\r
+ /* Set the USART0 Mode register: Mode=Normal(0), Clk selection=MCK(0),\r
+ CHRL=8, SYNC=0(asynchronous), PAR=None, NBSTOP=1, CHMODE=0, MSBF=0,\r
+ MODE9=0, CKLO=0, OVER(previously done when setting the baudrate),\r
+ other fields not used in this mode. */\r
+ usart0->mr |= ((8-5) << AVR32_USART_MR_CHRL_OFFSET ) |\r
+ ( 4 << AVR32_USART_MR_PAR_OFFSET ) |\r
+ ( 1 << AVR32_USART_MR_NBSTOP_OFFSET);\r
+\r
+ /* Write the Transmit Timeguard Register */\r
+ usart0->ttgr = 0;\r
+\r
+#if __GNUC__\r
+ // Register the USART0 interrupt handler to the interrupt controller and\r
+ // enable the USART0 interrupt.\r
+ INTC_register_interrupt(&vUSART0_ISR, AVR32_USART0_IRQ, INT1);\r
+#endif\r
+\r
+ /* Enable USART0 interrupt sources (but not Tx for now)... */\r
+ usart0->ier = AVR32_USART_IER_RXRDY_MASK;\r
+\r
+ /* Enable receiver and transmitter... */\r
+ usart0->cr |= AVR32_USART_CR_TXEN_MASK | AVR32_USART_CR_RXEN_MASK;\r
+ }\r
+ portEXIT_CRITICAL();\r
+ }\r
+ else\r
+ {\r
+ xReturn = serINVALID_COMPORT_HANDLER;\r
+ }\r
+\r
+ return xReturn;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed portCHAR *pcRxedChar, portTickType xBlockTime )\r
+{\r
+ /* The port handle is not required as this driver only supports UART0. */\r
+ ( void ) pxPort;\r
+\r
+ /* Get the next character from the buffer. Return false if no characters\r
+ are available, or arrive before xBlockTime expires. */\r
+ if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) )\r
+ {\r
+ return pdTRUE;\r
+ }\r
+ else\r
+ {\r
+ return pdFALSE;\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vSerialPutString( xComPortHandle pxPort, const signed portCHAR * const pcString, unsigned portSHORT usStringLength )\r
+{\r
+signed portCHAR *pxNext;\r
+\r
+ /* NOTE: This implementation does not handle the queue being full as no\r
+ block time is used! */\r
+\r
+ /* The port handle is not required as this driver only supports UART0. */\r
+ ( void ) pxPort;\r
+\r
+ /* Send each character in the string, one at a time. */\r
+ pxNext = ( signed portCHAR * ) pcString;\r
+ while( *pxNext )\r
+ {\r
+ xSerialPutChar( pxPort, *pxNext, serNO_BLOCK );\r
+ pxNext++;\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed portCHAR cOutChar, portTickType xBlockTime )\r
+{\r
+volatile avr32_usart_t *usart0 = &AVR32_USART0;\r
+\r
+ /* Place the character in the queue of characters to be transmitted. */\r
+ if( xQueueSend( xCharsForTx, &cOutChar, xBlockTime ) != pdPASS )\r
+ {\r
+ return pdFAIL;\r
+ }\r
+\r
+ /* Turn on the Tx interrupt so the ISR will remove the character from the\r
+ queue and send it. This does not need to be in a critical section as\r
+ if the interrupt has already removed the character the next interrupt\r
+ will simply turn off the Tx interrupt again. */\r
+ usart0->ier = (1 << AVR32_USART_IER_TXRDY_OFFSET);\r
+\r
+ return pdPASS;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vSerialClose( xComPortHandle xPort )\r
+{\r
+ /* Not supported as not required by the demo application. */\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/*###########################################################*/\r
+\r
+/*\r
+ * Create the rx and tx queues.\r
+ */\r
+static void vprvSerialCreateQueues( unsigned portBASE_TYPE uxQueueLength, xQueueHandle *pxRxedChars, xQueueHandle *pxCharsForTx )\r
+{\r
+ /* Create the queues used to hold Rx and Tx characters. */\r
+ xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) );\r
+ xCharsForTx = xQueueCreate( uxQueueLength + 1, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) );\r
+\r
+ /* Pass back a reference to the queues so the serial API file can\r
+ post/receive characters. */\r
+ *pxRxedChars = xRxedChars;\r
+ *pxCharsForTx = xCharsForTx;\r
+}\r
+/*-----------------------------------------------------------*/\r
--- /dev/null
+/* This header file is part of the ATMEL FREERTOS-0.9.0 Release */\r
+\r
+/*This file is prepared for Doxygen automatic documentation generation.*/\r
+/*! \file *********************************************************************\r
+ *\r
+ * \brief Preprocessor macro repeating utils.\r
+ *\r
+ * - Compiler: IAR EWAVR32 and GNU GCC for AVR32\r
+ * - Supported devices: All AVR32 devices can be used.\r
+ *\r
+ * \author Atmel Corporation: http://www.atmel.com \n\r
+ * Support email: avr32@atmel.com\r
+ *\r
+ ******************************************************************************/\r
+\r
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of ATMEL may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND\r
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,\r
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\r
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\r
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF\r
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ */\r
+\r
+\r
+#ifndef _MREPEAT_H_\r
+#define _MREPEAT_H_\r
+\r
+#include "preprocessor.h"\r
+\r
+\r
+//! Maximal number of repetitions supported by MREPEAT.\r
+#define MREPEAT_LIMIT 256\r
+\r
+/*! \brief Macro repeat.\r
+ *\r
+ * This macro represents a horizontal repetition construct.\r
+ *\r
+ * \param count The number of repetitious calls to macro. Valid values range from 0 to MREPEAT_LIMIT.\r
+ * \param macro A binary operation of the form macro(n, data). This macro is expanded by MREPEAT with\r
+ * the current repetition number and the auxiliary data argument.\r
+ * \param data Auxiliary data passed to macro.\r
+ *\r
+ * \return <tt>macro(0, data) macro(1, data) ... macro(count - 1, data)</tt>\r
+ */\r
+#define MREPEAT(count, macro, data) TPASTE2(MREPEAT, count)(macro, data)\r
+\r
+#define MREPEAT0( macro, data)\r
+#define MREPEAT1( macro, data) MREPEAT0( macro, data) macro( 0, data)\r
+#define MREPEAT2( macro, data) MREPEAT1( macro, data) macro( 1, data)\r
+#define MREPEAT3( macro, data) MREPEAT2( macro, data) macro( 2, data)\r
+#define MREPEAT4( macro, data) MREPEAT3( macro, data) macro( 3, data)\r
+#define MREPEAT5( macro, data) MREPEAT4( macro, data) macro( 4, data)\r
+#define MREPEAT6( macro, data) MREPEAT5( macro, data) macro( 5, data)\r
+#define MREPEAT7( macro, data) MREPEAT6( macro, data) macro( 6, data)\r
+#define MREPEAT8( macro, data) MREPEAT7( macro, data) macro( 7, data)\r
+#define MREPEAT9( macro, data) MREPEAT8( macro, data) macro( 8, data)\r
+#define MREPEAT10( macro, data) MREPEAT9( macro, data) macro( 9, data)\r
+#define MREPEAT11( macro, data) MREPEAT10( macro, data) macro( 10, data)\r
+#define MREPEAT12( macro, data) MREPEAT11( macro, data) macro( 11, data)\r
+#define MREPEAT13( macro, data) MREPEAT12( macro, data) macro( 12, data)\r
+#define MREPEAT14( macro, data) MREPEAT13( macro, data) macro( 13, data)\r
+#define MREPEAT15( macro, data) MREPEAT14( macro, data) macro( 14, data)\r
+#define MREPEAT16( macro, data) MREPEAT15( macro, data) macro( 15, data)\r
+#define MREPEAT17( macro, data) MREPEAT16( macro, data) macro( 16, data)\r
+#define MREPEAT18( macro, data) MREPEAT17( macro, data) macro( 17, data)\r
+#define MREPEAT19( macro, data) MREPEAT18( macro, data) macro( 18, data)\r
+#define MREPEAT20( macro, data) MREPEAT19( macro, data) macro( 19, data)\r
+#define MREPEAT21( macro, data) MREPEAT20( macro, data) macro( 20, data)\r
+#define MREPEAT22( macro, data) MREPEAT21( macro, data) macro( 21, data)\r
+#define MREPEAT23( macro, data) MREPEAT22( macro, data) macro( 22, data)\r
+#define MREPEAT24( macro, data) MREPEAT23( macro, data) macro( 23, data)\r
+#define MREPEAT25( macro, data) MREPEAT24( macro, data) macro( 24, data)\r
+#define MREPEAT26( macro, data) MREPEAT25( macro, data) macro( 25, data)\r
+#define MREPEAT27( macro, data) MREPEAT26( macro, data) macro( 26, data)\r
+#define MREPEAT28( macro, data) MREPEAT27( macro, data) macro( 27, data)\r
+#define MREPEAT29( macro, data) MREPEAT28( macro, data) macro( 28, data)\r
+#define MREPEAT30( macro, data) MREPEAT29( macro, data) macro( 29, data)\r
+#define MREPEAT31( macro, data) MREPEAT30( macro, data) macro( 30, data)\r
+#define MREPEAT32( macro, data) MREPEAT31( macro, data) macro( 31, data)\r
+#define MREPEAT33( macro, data) MREPEAT32( macro, data) macro( 32, data)\r
+#define MREPEAT34( macro, data) MREPEAT33( macro, data) macro( 33, data)\r
+#define MREPEAT35( macro, data) MREPEAT34( macro, data) macro( 34, data)\r
+#define MREPEAT36( macro, data) MREPEAT35( macro, data) macro( 35, data)\r
+#define MREPEAT37( macro, data) MREPEAT36( macro, data) macro( 36, data)\r
+#define MREPEAT38( macro, data) MREPEAT37( macro, data) macro( 37, data)\r
+#define MREPEAT39( macro, data) MREPEAT38( macro, data) macro( 38, data)\r
+#define MREPEAT40( macro, data) MREPEAT39( macro, data) macro( 39, data)\r
+#define MREPEAT41( macro, data) MREPEAT40( macro, data) macro( 40, data)\r
+#define MREPEAT42( macro, data) MREPEAT41( macro, data) macro( 41, data)\r
+#define MREPEAT43( macro, data) MREPEAT42( macro, data) macro( 42, data)\r
+#define MREPEAT44( macro, data) MREPEAT43( macro, data) macro( 43, data)\r
+#define MREPEAT45( macro, data) MREPEAT44( macro, data) macro( 44, data)\r
+#define MREPEAT46( macro, data) MREPEAT45( macro, data) macro( 45, data)\r
+#define MREPEAT47( macro, data) MREPEAT46( macro, data) macro( 46, data)\r
+#define MREPEAT48( macro, data) MREPEAT47( macro, data) macro( 47, data)\r
+#define MREPEAT49( macro, data) MREPEAT48( macro, data) macro( 48, data)\r
+#define MREPEAT50( macro, data) MREPEAT49( macro, data) macro( 49, data)\r
+#define MREPEAT51( macro, data) MREPEAT50( macro, data) macro( 50, data)\r
+#define MREPEAT52( macro, data) MREPEAT51( macro, data) macro( 51, data)\r
+#define MREPEAT53( macro, data) MREPEAT52( macro, data) macro( 52, data)\r
+#define MREPEAT54( macro, data) MREPEAT53( macro, data) macro( 53, data)\r
+#define MREPEAT55( macro, data) MREPEAT54( macro, data) macro( 54, data)\r
+#define MREPEAT56( macro, data) MREPEAT55( macro, data) macro( 55, data)\r
+#define MREPEAT57( macro, data) MREPEAT56( macro, data) macro( 56, data)\r
+#define MREPEAT58( macro, data) MREPEAT57( macro, data) macro( 57, data)\r
+#define MREPEAT59( macro, data) MREPEAT58( macro, data) macro( 58, data)\r
+#define MREPEAT60( macro, data) MREPEAT59( macro, data) macro( 59, data)\r
+#define MREPEAT61( macro, data) MREPEAT60( macro, data) macro( 60, data)\r
+#define MREPEAT62( macro, data) MREPEAT61( macro, data) macro( 61, data)\r
+#define MREPEAT63( macro, data) MREPEAT62( macro, data) macro( 62, data)\r
+#define MREPEAT64( macro, data) MREPEAT63( macro, data) macro( 63, data)\r
+#define MREPEAT65( macro, data) MREPEAT64( macro, data) macro( 64, data)\r
+#define MREPEAT66( macro, data) MREPEAT65( macro, data) macro( 65, data)\r
+#define MREPEAT67( macro, data) MREPEAT66( macro, data) macro( 66, data)\r
+#define MREPEAT68( macro, data) MREPEAT67( macro, data) macro( 67, data)\r
+#define MREPEAT69( macro, data) MREPEAT68( macro, data) macro( 68, data)\r
+#define MREPEAT70( macro, data) MREPEAT69( macro, data) macro( 69, data)\r
+#define MREPEAT71( macro, data) MREPEAT70( macro, data) macro( 70, data)\r
+#define MREPEAT72( macro, data) MREPEAT71( macro, data) macro( 71, data)\r
+#define MREPEAT73( macro, data) MREPEAT72( macro, data) macro( 72, data)\r
+#define MREPEAT74( macro, data) MREPEAT73( macro, data) macro( 73, data)\r
+#define MREPEAT75( macro, data) MREPEAT74( macro, data) macro( 74, data)\r
+#define MREPEAT76( macro, data) MREPEAT75( macro, data) macro( 75, data)\r
+#define MREPEAT77( macro, data) MREPEAT76( macro, data) macro( 76, data)\r
+#define MREPEAT78( macro, data) MREPEAT77( macro, data) macro( 77, data)\r
+#define MREPEAT79( macro, data) MREPEAT78( macro, data) macro( 78, data)\r
+#define MREPEAT80( macro, data) MREPEAT79( macro, data) macro( 79, data)\r
+#define MREPEAT81( macro, data) MREPEAT80( macro, data) macro( 80, data)\r
+#define MREPEAT82( macro, data) MREPEAT81( macro, data) macro( 81, data)\r
+#define MREPEAT83( macro, data) MREPEAT82( macro, data) macro( 82, data)\r
+#define MREPEAT84( macro, data) MREPEAT83( macro, data) macro( 83, data)\r
+#define MREPEAT85( macro, data) MREPEAT84( macro, data) macro( 84, data)\r
+#define MREPEAT86( macro, data) MREPEAT85( macro, data) macro( 85, data)\r
+#define MREPEAT87( macro, data) MREPEAT86( macro, data) macro( 86, data)\r
+#define MREPEAT88( macro, data) MREPEAT87( macro, data) macro( 87, data)\r
+#define MREPEAT89( macro, data) MREPEAT88( macro, data) macro( 88, data)\r
+#define MREPEAT90( macro, data) MREPEAT89( macro, data) macro( 89, data)\r
+#define MREPEAT91( macro, data) MREPEAT90( macro, data) macro( 90, data)\r
+#define MREPEAT92( macro, data) MREPEAT91( macro, data) macro( 91, data)\r
+#define MREPEAT93( macro, data) MREPEAT92( macro, data) macro( 92, data)\r
+#define MREPEAT94( macro, data) MREPEAT93( macro, data) macro( 93, data)\r
+#define MREPEAT95( macro, data) MREPEAT94( macro, data) macro( 94, data)\r
+#define MREPEAT96( macro, data) MREPEAT95( macro, data) macro( 95, data)\r
+#define MREPEAT97( macro, data) MREPEAT96( macro, data) macro( 96, data)\r
+#define MREPEAT98( macro, data) MREPEAT97( macro, data) macro( 97, data)\r
+#define MREPEAT99( macro, data) MREPEAT98( macro, data) macro( 98, data)\r
+#define MREPEAT100(macro, data) MREPEAT99( macro, data) macro( 99, data)\r
+#define MREPEAT101(macro, data) MREPEAT100(macro, data) macro(100, data)\r
+#define MREPEAT102(macro, data) MREPEAT101(macro, data) macro(101, data)\r
+#define MREPEAT103(macro, data) MREPEAT102(macro, data) macro(102, data)\r
+#define MREPEAT104(macro, data) MREPEAT103(macro, data) macro(103, data)\r
+#define MREPEAT105(macro, data) MREPEAT104(macro, data) macro(104, data)\r
+#define MREPEAT106(macro, data) MREPEAT105(macro, data) macro(105, data)\r
+#define MREPEAT107(macro, data) MREPEAT106(macro, data) macro(106, data)\r
+#define MREPEAT108(macro, data) MREPEAT107(macro, data) macro(107, data)\r
+#define MREPEAT109(macro, data) MREPEAT108(macro, data) macro(108, data)\r
+#define MREPEAT110(macro, data) MREPEAT109(macro, data) macro(109, data)\r
+#define MREPEAT111(macro, data) MREPEAT110(macro, data) macro(110, data)\r
+#define MREPEAT112(macro, data) MREPEAT111(macro, data) macro(111, data)\r
+#define MREPEAT113(macro, data) MREPEAT112(macro, data) macro(112, data)\r
+#define MREPEAT114(macro, data) MREPEAT113(macro, data) macro(113, data)\r
+#define MREPEAT115(macro, data) MREPEAT114(macro, data) macro(114, data)\r
+#define MREPEAT116(macro, data) MREPEAT115(macro, data) macro(115, data)\r
+#define MREPEAT117(macro, data) MREPEAT116(macro, data) macro(116, data)\r
+#define MREPEAT118(macro, data) MREPEAT117(macro, data) macro(117, data)\r
+#define MREPEAT119(macro, data) MREPEAT118(macro, data) macro(118, data)\r
+#define MREPEAT120(macro, data) MREPEAT119(macro, data) macro(119, data)\r
+#define MREPEAT121(macro, data) MREPEAT120(macro, data) macro(120, data)\r
+#define MREPEAT122(macro, data) MREPEAT121(macro, data) macro(121, data)\r
+#define MREPEAT123(macro, data) MREPEAT122(macro, data) macro(122, data)\r
+#define MREPEAT124(macro, data) MREPEAT123(macro, data) macro(123, data)\r
+#define MREPEAT125(macro, data) MREPEAT124(macro, data) macro(124, data)\r
+#define MREPEAT126(macro, data) MREPEAT125(macro, data) macro(125, data)\r
+#define MREPEAT127(macro, data) MREPEAT126(macro, data) macro(126, data)\r
+#define MREPEAT128(macro, data) MREPEAT127(macro, data) macro(127, data)\r
+#define MREPEAT129(macro, data) MREPEAT128(macro, data) macro(128, data)\r
+#define MREPEAT130(macro, data) MREPEAT129(macro, data) macro(129, data)\r
+#define MREPEAT131(macro, data) MREPEAT130(macro, data) macro(130, data)\r
+#define MREPEAT132(macro, data) MREPEAT131(macro, data) macro(131, data)\r
+#define MREPEAT133(macro, data) MREPEAT132(macro, data) macro(132, data)\r
+#define MREPEAT134(macro, data) MREPEAT133(macro, data) macro(133, data)\r
+#define MREPEAT135(macro, data) MREPEAT134(macro, data) macro(134, data)\r
+#define MREPEAT136(macro, data) MREPEAT135(macro, data) macro(135, data)\r
+#define MREPEAT137(macro, data) MREPEAT136(macro, data) macro(136, data)\r
+#define MREPEAT138(macro, data) MREPEAT137(macro, data) macro(137, data)\r
+#define MREPEAT139(macro, data) MREPEAT138(macro, data) macro(138, data)\r
+#define MREPEAT140(macro, data) MREPEAT139(macro, data) macro(139, data)\r
+#define MREPEAT141(macro, data) MREPEAT140(macro, data) macro(140, data)\r
+#define MREPEAT142(macro, data) MREPEAT141(macro, data) macro(141, data)\r
+#define MREPEAT143(macro, data) MREPEAT142(macro, data) macro(142, data)\r
+#define MREPEAT144(macro, data) MREPEAT143(macro, data) macro(143, data)\r
+#define MREPEAT145(macro, data) MREPEAT144(macro, data) macro(144, data)\r
+#define MREPEAT146(macro, data) MREPEAT145(macro, data) macro(145, data)\r
+#define MREPEAT147(macro, data) MREPEAT146(macro, data) macro(146, data)\r
+#define MREPEAT148(macro, data) MREPEAT147(macro, data) macro(147, data)\r
+#define MREPEAT149(macro, data) MREPEAT148(macro, data) macro(148, data)\r
+#define MREPEAT150(macro, data) MREPEAT149(macro, data) macro(149, data)\r
+#define MREPEAT151(macro, data) MREPEAT150(macro, data) macro(150, data)\r
+#define MREPEAT152(macro, data) MREPEAT151(macro, data) macro(151, data)\r
+#define MREPEAT153(macro, data) MREPEAT152(macro, data) macro(152, data)\r
+#define MREPEAT154(macro, data) MREPEAT153(macro, data) macro(153, data)\r
+#define MREPEAT155(macro, data) MREPEAT154(macro, data) macro(154, data)\r
+#define MREPEAT156(macro, data) MREPEAT155(macro, data) macro(155, data)\r
+#define MREPEAT157(macro, data) MREPEAT156(macro, data) macro(156, data)\r
+#define MREPEAT158(macro, data) MREPEAT157(macro, data) macro(157, data)\r
+#define MREPEAT159(macro, data) MREPEAT158(macro, data) macro(158, data)\r
+#define MREPEAT160(macro, data) MREPEAT159(macro, data) macro(159, data)\r
+#define MREPEAT161(macro, data) MREPEAT160(macro, data) macro(160, data)\r
+#define MREPEAT162(macro, data) MREPEAT161(macro, data) macro(161, data)\r
+#define MREPEAT163(macro, data) MREPEAT162(macro, data) macro(162, data)\r
+#define MREPEAT164(macro, data) MREPEAT163(macro, data) macro(163, data)\r
+#define MREPEAT165(macro, data) MREPEAT164(macro, data) macro(164, data)\r
+#define MREPEAT166(macro, data) MREPEAT165(macro, data) macro(165, data)\r
+#define MREPEAT167(macro, data) MREPEAT166(macro, data) macro(166, data)\r
+#define MREPEAT168(macro, data) MREPEAT167(macro, data) macro(167, data)\r
+#define MREPEAT169(macro, data) MREPEAT168(macro, data) macro(168, data)\r
+#define MREPEAT170(macro, data) MREPEAT169(macro, data) macro(169, data)\r
+#define MREPEAT171(macro, data) MREPEAT170(macro, data) macro(170, data)\r
+#define MREPEAT172(macro, data) MREPEAT171(macro, data) macro(171, data)\r
+#define MREPEAT173(macro, data) MREPEAT172(macro, data) macro(172, data)\r
+#define MREPEAT174(macro, data) MREPEAT173(macro, data) macro(173, data)\r
+#define MREPEAT175(macro, data) MREPEAT174(macro, data) macro(174, data)\r
+#define MREPEAT176(macro, data) MREPEAT175(macro, data) macro(175, data)\r
+#define MREPEAT177(macro, data) MREPEAT176(macro, data) macro(176, data)\r
+#define MREPEAT178(macro, data) MREPEAT177(macro, data) macro(177, data)\r
+#define MREPEAT179(macro, data) MREPEAT178(macro, data) macro(178, data)\r
+#define MREPEAT180(macro, data) MREPEAT179(macro, data) macro(179, data)\r
+#define MREPEAT181(macro, data) MREPEAT180(macro, data) macro(180, data)\r
+#define MREPEAT182(macro, data) MREPEAT181(macro, data) macro(181, data)\r
+#define MREPEAT183(macro, data) MREPEAT182(macro, data) macro(182, data)\r
+#define MREPEAT184(macro, data) MREPEAT183(macro, data) macro(183, data)\r
+#define MREPEAT185(macro, data) MREPEAT184(macro, data) macro(184, data)\r
+#define MREPEAT186(macro, data) MREPEAT185(macro, data) macro(185, data)\r
+#define MREPEAT187(macro, data) MREPEAT186(macro, data) macro(186, data)\r
+#define MREPEAT188(macro, data) MREPEAT187(macro, data) macro(187, data)\r
+#define MREPEAT189(macro, data) MREPEAT188(macro, data) macro(188, data)\r
+#define MREPEAT190(macro, data) MREPEAT189(macro, data) macro(189, data)\r
+#define MREPEAT191(macro, data) MREPEAT190(macro, data) macro(190, data)\r
+#define MREPEAT192(macro, data) MREPEAT191(macro, data) macro(191, data)\r
+#define MREPEAT193(macro, data) MREPEAT192(macro, data) macro(192, data)\r
+#define MREPEAT194(macro, data) MREPEAT193(macro, data) macro(193, data)\r
+#define MREPEAT195(macro, data) MREPEAT194(macro, data) macro(194, data)\r
+#define MREPEAT196(macro, data) MREPEAT195(macro, data) macro(195, data)\r
+#define MREPEAT197(macro, data) MREPEAT196(macro, data) macro(196, data)\r
+#define MREPEAT198(macro, data) MREPEAT197(macro, data) macro(197, data)\r
+#define MREPEAT199(macro, data) MREPEAT198(macro, data) macro(198, data)\r
+#define MREPEAT200(macro, data) MREPEAT199(macro, data) macro(199, data)\r
+#define MREPEAT201(macro, data) MREPEAT200(macro, data) macro(200, data)\r
+#define MREPEAT202(macro, data) MREPEAT201(macro, data) macro(201, data)\r
+#define MREPEAT203(macro, data) MREPEAT202(macro, data) macro(202, data)\r
+#define MREPEAT204(macro, data) MREPEAT203(macro, data) macro(203, data)\r
+#define MREPEAT205(macro, data) MREPEAT204(macro, data) macro(204, data)\r
+#define MREPEAT206(macro, data) MREPEAT205(macro, data) macro(205, data)\r
+#define MREPEAT207(macro, data) MREPEAT206(macro, data) macro(206, data)\r
+#define MREPEAT208(macro, data) MREPEAT207(macro, data) macro(207, data)\r
+#define MREPEAT209(macro, data) MREPEAT208(macro, data) macro(208, data)\r
+#define MREPEAT210(macro, data) MREPEAT209(macro, data) macro(209, data)\r
+#define MREPEAT211(macro, data) MREPEAT210(macro, data) macro(210, data)\r
+#define MREPEAT212(macro, data) MREPEAT211(macro, data) macro(211, data)\r
+#define MREPEAT213(macro, data) MREPEAT212(macro, data) macro(212, data)\r
+#define MREPEAT214(macro, data) MREPEAT213(macro, data) macro(213, data)\r
+#define MREPEAT215(macro, data) MREPEAT214(macro, data) macro(214, data)\r
+#define MREPEAT216(macro, data) MREPEAT215(macro, data) macro(215, data)\r
+#define MREPEAT217(macro, data) MREPEAT216(macro, data) macro(216, data)\r
+#define MREPEAT218(macro, data) MREPEAT217(macro, data) macro(217, data)\r
+#define MREPEAT219(macro, data) MREPEAT218(macro, data) macro(218, data)\r
+#define MREPEAT220(macro, data) MREPEAT219(macro, data) macro(219, data)\r
+#define MREPEAT221(macro, data) MREPEAT220(macro, data) macro(220, data)\r
+#define MREPEAT222(macro, data) MREPEAT221(macro, data) macro(221, data)\r
+#define MREPEAT223(macro, data) MREPEAT222(macro, data) macro(222, data)\r
+#define MREPEAT224(macro, data) MREPEAT223(macro, data) macro(223, data)\r
+#define MREPEAT225(macro, data) MREPEAT224(macro, data) macro(224, data)\r
+#define MREPEAT226(macro, data) MREPEAT225(macro, data) macro(225, data)\r
+#define MREPEAT227(macro, data) MREPEAT226(macro, data) macro(226, data)\r
+#define MREPEAT228(macro, data) MREPEAT227(macro, data) macro(227, data)\r
+#define MREPEAT229(macro, data) MREPEAT228(macro, data) macro(228, data)\r
+#define MREPEAT230(macro, data) MREPEAT229(macro, data) macro(229, data)\r
+#define MREPEAT231(macro, data) MREPEAT230(macro, data) macro(230, data)\r
+#define MREPEAT232(macro, data) MREPEAT231(macro, data) macro(231, data)\r
+#define MREPEAT233(macro, data) MREPEAT232(macro, data) macro(232, data)\r
+#define MREPEAT234(macro, data) MREPEAT233(macro, data) macro(233, data)\r
+#define MREPEAT235(macro, data) MREPEAT234(macro, data) macro(234, data)\r
+#define MREPEAT236(macro, data) MREPEAT235(macro, data) macro(235, data)\r
+#define MREPEAT237(macro, data) MREPEAT236(macro, data) macro(236, data)\r
+#define MREPEAT238(macro, data) MREPEAT237(macro, data) macro(237, data)\r
+#define MREPEAT239(macro, data) MREPEAT238(macro, data) macro(238, data)\r
+#define MREPEAT240(macro, data) MREPEAT239(macro, data) macro(239, data)\r
+#define MREPEAT241(macro, data) MREPEAT240(macro, data) macro(240, data)\r
+#define MREPEAT242(macro, data) MREPEAT241(macro, data) macro(241, data)\r
+#define MREPEAT243(macro, data) MREPEAT242(macro, data) macro(242, data)\r
+#define MREPEAT244(macro, data) MREPEAT243(macro, data) macro(243, data)\r
+#define MREPEAT245(macro, data) MREPEAT244(macro, data) macro(244, data)\r
+#define MREPEAT246(macro, data) MREPEAT245(macro, data) macro(245, data)\r
+#define MREPEAT247(macro, data) MREPEAT246(macro, data) macro(246, data)\r
+#define MREPEAT248(macro, data) MREPEAT247(macro, data) macro(247, data)\r
+#define MREPEAT249(macro, data) MREPEAT248(macro, data) macro(248, data)\r
+#define MREPEAT250(macro, data) MREPEAT249(macro, data) macro(249, data)\r
+#define MREPEAT251(macro, data) MREPEAT250(macro, data) macro(250, data)\r
+#define MREPEAT252(macro, data) MREPEAT251(macro, data) macro(251, data)\r
+#define MREPEAT253(macro, data) MREPEAT252(macro, data) macro(252, data)\r
+#define MREPEAT254(macro, data) MREPEAT253(macro, data) macro(253, data)\r
+#define MREPEAT255(macro, data) MREPEAT254(macro, data) macro(254, data)\r
+#define MREPEAT256(macro, data) MREPEAT255(macro, data) macro(255, data)\r
+\r
+\r
+#endif // _MREPEAT_H_\r
--- /dev/null
+/* This header file is part of the ATMEL FREERTOS-0.9.0 Release */\r
+\r
+/*This file is prepared for Doxygen automatic documentation generation.*/\r
+/*! \file *********************************************************************\r
+ *\r
+ * \brief Preprocessor utils.\r
+ *\r
+ * - Compiler: IAR EWAVR32 and GNU GCC for AVR32\r
+ * - Supported devices: All AVR32 devices can be used.\r
+ *\r
+ * \author Atmel Corporation: http://www.atmel.com \n\r
+ * Support email: avr32@atmel.com\r
+ *\r
+ ******************************************************************************/\r
+\r
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of ATMEL may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND\r
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,\r
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\r
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\r
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF\r
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ */\r
+\r
+\r
+#ifndef _PREPROCESSOR_H_\r
+#define _PREPROCESSOR_H_\r
+\r
+#include "tpaste.h"\r
+#include "stringz.h"\r
+#include "mrepeat.h"\r
+\r
+\r
+#endif // _PREPROCESSOR_H_\r
--- /dev/null
+/* This header file is part of the ATMEL FREERTOS-0.9.0 Release */\r
+\r
+/*This file is prepared for Doxygen automatic documentation generation.*/\r
+/*! \file *********************************************************************\r
+ *\r
+ * \brief Preprocessor stringizing utils.\r
+ *\r
+ * - Compiler: IAR EWAVR32 and GNU GCC for AVR32\r
+ * - Supported devices: All AVR32 devices can be used.\r
+ *\r
+ * \author Atmel Corporation: http://www.atmel.com \n\r
+ * Support email: avr32@atmel.com\r
+ *\r
+ ******************************************************************************/\r
+\r
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of ATMEL may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND\r
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,\r
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\r
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\r
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF\r
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ */\r
+\r
+\r
+#ifndef _STRINGZ_H_\r
+#define _STRINGZ_H_\r
+\r
+\r
+/*! \brief Stringize.\r
+ *\r
+ * Stringize a preprocessing token, this token being allowed to be #defined.\r
+ *\r
+ * May be used only within macros with the token passed as an argument if the token is #defined.\r
+ *\r
+ * For example, writing STRINGZ(PIN) within a macro #defined by PIN_NAME(PIN)\r
+ * and invoked as PIN_NAME(PIN0) with PIN0 #defined as A0 is equivalent to\r
+ * writing "A0".\r
+ */\r
+#define STRINGZ(x) #x\r
+\r
+/*! \brief Absolute stringize.\r
+ *\r
+ * Stringize a preprocessing token, this token being allowed to be #defined.\r
+ *\r
+ * No restriction of use if the token is #defined.\r
+ *\r
+ * For example, writing ASTRINGZ(PIN0) anywhere with PIN0 #defined as A0 is\r
+ * equivalent to writing "A0".\r
+ */\r
+#define ASTRINGZ(x) STRINGZ(x)\r
+\r
+\r
+#endif // _STRINGZ_H_\r
--- /dev/null
+/* This header file is part of the ATMEL FREERTOS-0.9.0 Release */\r
+\r
+/*This file is prepared for Doxygen automatic documentation generation.*/\r
+/*! \file *********************************************************************\r
+ *\r
+ * \brief Preprocessor token pasting utils.\r
+ *\r
+ * - Compiler: IAR EWAVR32 and GNU GCC for AVR32\r
+ * - Supported devices: All AVR32 devices can be used.\r
+ *\r
+ * \author Atmel Corporation: http://www.atmel.com \n\r
+ * Support email: avr32@atmel.com\r
+ *\r
+ ******************************************************************************/\r
+\r
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of ATMEL may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND\r
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,\r
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\r
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\r
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF\r
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ */\r
+\r
+\r
+#ifndef _TPASTE_H_\r
+#define _TPASTE_H_\r
+\r
+\r
+/*! \name Token Paste\r
+ *\r
+ * Paste N preprocessing tokens together, these tokens being allowed to be #defined.\r
+ *\r
+ * May be used only within macros with the tokens passed as arguments if the tokens are #defined.\r
+ *\r
+ * For example, writing TPASTE2(U, WIDTH) within a macro #defined by\r
+ * UTYPE(WIDTH) and invoked as UTYPE(UL_WIDTH) with UL_WIDTH #defined as 32 is\r
+ * equivalent to writing U32.\r
+ */\r
+//! @{\r
+#define TPASTE2( a, b) a##b\r
+#define TPASTE3( a, b, c) a##b##c\r
+#define TPASTE4( a, b, c, d) a##b##c##d\r
+#define TPASTE5( a, b, c, d, e) a##b##c##d##e\r
+#define TPASTE6( a, b, c, d, e, f) a##b##c##d##e##f\r
+#define TPASTE7( a, b, c, d, e, f, g) a##b##c##d##e##f##g\r
+#define TPASTE8( a, b, c, d, e, f, g, h) a##b##c##d##e##f##g##h\r
+#define TPASTE9( a, b, c, d, e, f, g, h, i) a##b##c##d##e##f##g##h##i\r
+#define TPASTE10(a, b, c, d, e, f, g, h, i, j) a##b##c##d##e##f##g##h##i##j\r
+//! @}\r
+\r
+/*! \name Absolute Token Paste\r
+ *\r
+ * Paste N preprocessing tokens together, these tokens being allowed to be #defined.\r
+ *\r
+ * No restriction of use if the tokens are #defined.\r
+ *\r
+ * For example, writing ATPASTE2(U, UL_WIDTH) anywhere with UL_WIDTH #defined\r
+ * as 32 is equivalent to writing U32.\r
+ */\r
+//! @{\r
+#define ATPASTE2( a, b) TPASTE2( a, b)\r
+#define ATPASTE3( a, b, c) TPASTE3( a, b, c)\r
+#define ATPASTE4( a, b, c, d) TPASTE4( a, b, c, d)\r
+#define ATPASTE5( a, b, c, d, e) TPASTE5( a, b, c, d, e)\r
+#define ATPASTE6( a, b, c, d, e, f) TPASTE6( a, b, c, d, e, f)\r
+#define ATPASTE7( a, b, c, d, e, f, g) TPASTE7( a, b, c, d, e, f, g)\r
+#define ATPASTE8( a, b, c, d, e, f, g, h) TPASTE8( a, b, c, d, e, f, g, h)\r
+#define ATPASTE9( a, b, c, d, e, f, g, h, i) TPASTE9( a, b, c, d, e, f, g, h, i)\r
+#define ATPASTE10(a, b, c, d, e, f, g, h, i, j) TPASTE10(a, b, c, d, e, f, g, h, i, j)\r
+//! @}\r
+\r
+\r
+#endif // _TPASTE_H_\r
--- /dev/null
+/* This header file is part of the ATMEL FREERTOS-0.9.0 Release */\r
+\r
+/*This file is prepared for Doxygen automatic documentation generation.*/\r
+/*! \file *********************************************************************\r
+ *\r
+ * \brief Compiler file for AVR32.\r
+ *\r
+ * This file defines commonly used types and macros.\r
+ *\r
+ * - Compiler: IAR EWAVR32 and GNU GCC for AVR32\r
+ * - Supported devices: All AVR32 devices can be used.\r
+ * - AppNote:\r
+ *\r
+ * \author Atmel Corporation: http://www.atmel.com \n\r
+ * Support email: avr32@atmel.com\r
+ *\r
+ ******************************************************************************/\r
+\r
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of ATMEL may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND\r
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,\r
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\r
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\r
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF\r
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ */\r
+\r
+\r
+#ifndef _COMPILER_H_\r
+#define _COMPILER_H_\r
+\r
+#if __GNUC__\r
+# include <avr32/io.h>\r
+#elif __ICCAVR32__ || __AAVR32__\r
+# include <avr32/iouc3a0512.h>\r
+# include <avr32/uc3a0512.h>\r
+# if __ICCAVR32__\r
+# include <intrinsics.h>\r
+# endif\r
+#else\r
+# error Unknown compiler\r
+#endif\r
+\r
+#include "preprocessor.h"\r
+\r
+\r
+//_____ D E C L A R A T I O N S ____________________________________________\r
+\r
+#ifdef __AVR32_ABI_COMPILER__ // Automatically defined when compiling for AVR32, not when assembling.\r
+\r
+#include <stddef.h>\r
+#include <stdlib.h>\r
+\r
+/*! \name Usual Types\r
+ */\r
+//! @{\r
+typedef unsigned char Bool; //!< Boolean.\r
+typedef unsigned char U8 ; //!< 8-bit unsigned integer.\r
+typedef unsigned short int U16; //!< 16-bit unsigned integer.\r
+typedef unsigned long int U32; //!< 32-bit unsigned integer.\r
+typedef unsigned long long int U64; //!< 64-bit unsigned integer.\r
+typedef signed char S8 ; //!< 8-bit signed integer.\r
+typedef signed short int S16; //!< 16-bit signed integer.\r
+typedef signed long int S32; //!< 32-bit signed integer.\r
+typedef signed long long int S64; //!< 64-bit signed integer.\r
+typedef float F32; //!< 32-bit floating-point number.\r
+typedef double F64; //!< 64-bit floating-point number.\r
+//! @}\r
+\r
+/*! \name Status Types\r
+ */\r
+//! @{\r
+typedef Bool Status_bool_t; //!< Boolean status.\r
+typedef U8 Status_t; //!< 8-bit-coded status.\r
+//! @}\r
+\r
+#if __ICCAVR32__\r
+\r
+/*! \name Compiler Keywords\r
+ *\r
+ * Translation of some keywords from GNU GCC for AVR32 to IAR Embedded Workbench for Atmel AVR32.\r
+ */\r
+//! @{\r
+#define __asm__ asm\r
+#define __inline__ inline\r
+#define __volatile__\r
+//! @}\r
+\r
+#endif\r
+\r
+/*! \name Aliasing Aggregate Types\r
+ */\r
+//! @{\r
+\r
+//! 16-bit union.\r
+typedef union\r
+{\r
+ U16 u16 ;\r
+ U8 u8 [2];\r
+} Union16;\r
+\r
+//! 32-bit union.\r
+typedef union\r
+{\r
+ U32 u32 ;\r
+ U16 u16[2];\r
+ U8 u8 [4];\r
+} Union32;\r
+\r
+//! 64-bit union.\r
+typedef union\r
+{\r
+ U64 u64 ;\r
+ U32 u32[2];\r
+ U16 u16[4];\r
+ U8 u8 [8];\r
+} Union64;\r
+\r
+//! Union of pointers to 64-, 32-, 16- and 8-bit unsigned integers.\r
+typedef union\r
+{\r
+ U64 *u64ptr;\r
+ U32 *u32ptr;\r
+ U16 *u16ptr;\r
+ U8 *u8ptr ;\r
+} UnionPtr;\r
+\r
+//! Union of pointers to volatile 64-, 32-, 16- and 8-bit unsigned integers.\r
+typedef union\r
+{\r
+ volatile U64 *u64ptr;\r
+ volatile U32 *u32ptr;\r
+ volatile U16 *u16ptr;\r
+ volatile U8 *u8ptr ;\r
+} UnionVPtr;\r
+\r
+//! Union of pointers to constant 64-, 32-, 16- and 8-bit unsigned integers.\r
+typedef union\r
+{\r
+ const U64 *u64ptr;\r
+ const U32 *u32ptr;\r
+ const U16 *u16ptr;\r
+ const U8 *u8ptr ;\r
+} UnionCPtr;\r
+\r
+//! Union of pointers to constant volatile 64-, 32-, 16- and 8-bit unsigned integers.\r
+typedef union\r
+{\r
+ const volatile U64 *u64ptr;\r
+ const volatile U32 *u32ptr;\r
+ const volatile U16 *u16ptr;\r
+ const volatile U8 *u8ptr ;\r
+} UnionCVPtr;\r
+\r
+//! Structure of pointers to 64-, 32-, 16- and 8-bit unsigned integers.\r
+typedef struct\r
+{\r
+ U64 *u64ptr;\r
+ U32 *u32ptr;\r
+ U16 *u16ptr;\r
+ U8 *u8ptr ;\r
+} StructPtr;\r
+\r
+//! Structure of pointers to volatile 64-, 32-, 16- and 8-bit unsigned integers.\r
+typedef struct\r
+{\r
+ volatile U64 *u64ptr;\r
+ volatile U32 *u32ptr;\r
+ volatile U16 *u16ptr;\r
+ volatile U8 *u8ptr ;\r
+} StructVPtr;\r
+\r
+//! Structure of pointers to constant 64-, 32-, 16- and 8-bit unsigned integers.\r
+typedef struct\r
+{\r
+ const U64 *u64ptr;\r
+ const U32 *u32ptr;\r
+ const U16 *u16ptr;\r
+ const U8 *u8ptr ;\r
+} StructCPtr;\r
+\r
+//! Structure of pointers to constant volatile 64-, 32-, 16- and 8-bit unsigned integers.\r
+typedef struct\r
+{\r
+ const volatile U64 *u64ptr;\r
+ const volatile U32 *u32ptr;\r
+ const volatile U16 *u16ptr;\r
+ const volatile U8 *u8ptr ;\r
+} StructCVPtr;\r
+\r
+//! @}\r
+\r
+#endif // __AVR32_ABI_COMPILER__\r
+\r
+//_____ M A C R O S ________________________________________________________\r
+\r
+/*! \name Usual Constants\r
+ */\r
+//! @{\r
+#define DISABLE 0\r
+#define ENABLE 1\r
+#define DISABLED 0\r
+#define ENABLED 1\r
+#define OFF 0\r
+#define ON 1\r
+#define FALSE 0\r
+#define TRUE 1\r
+#define KO 0\r
+#define OK 1\r
+#define PASS 0\r
+#define FAIL 1\r
+#define LOW 0\r
+#define HIGH 1\r
+#define CLR 0\r
+#define SET 1\r
+//! @}\r
+\r
+#ifdef __AVR32_ABI_COMPILER__ // Automatically defined when compiling for AVR32, not when assembling.\r
+\r
+/*! \name Bit-Field Handling Macros\r
+ */\r
+//! @{\r
+\r
+/*! \brief Reads the bits of a value specified by a given bit-mask.\r
+ *\r
+ * \param value Value to read bits from.\r
+ * \param mask Bit-mask indicating bits to read.\r
+ *\r
+ * \return Read bits.\r
+ */\r
+#define Rd_bits( value, mask) ((value) & (mask))\r
+\r
+/*! \brief Writes the bits of a C lvalue specified by a given bit-mask.\r
+ *\r
+ * \param lvalue C lvalue to write bits to.\r
+ * \param mask Bit-mask indicating bits to write.\r
+ * \param bits Bits to write.\r
+ *\r
+ * \return Resulting value with written bits.\r
+ */\r
+#define Wr_bits(lvalue, mask, bits) ((lvalue) = ((lvalue) & ~(mask)) |\\r
+ ((bits ) & (mask)))\r
+\r
+/*! \brief Tests the bits of a value specified by a given bit-mask.\r
+ *\r
+ * \param value Value of which to test bits.\r
+ * \param mask Bit-mask indicating bits to test.\r
+ *\r
+ * \return \c 1 if at least one of the tested bits is set, else \c 0.\r
+ */\r
+#define Tst_bits( value, mask) (Rd_bits(value, mask) != 0)\r
+\r
+/*! \brief Clears the bits of a C lvalue specified by a given bit-mask.\r
+ *\r
+ * \param lvalue C lvalue of which to clear bits.\r
+ * \param mask Bit-mask indicating bits to clear.\r
+ *\r
+ * \return Resulting value with cleared bits.\r
+ */\r
+#define Clr_bits(lvalue, mask) ((lvalue) &= ~(mask))\r
+\r
+/*! \brief Sets the bits of a C lvalue specified by a given bit-mask.\r
+ *\r
+ * \param lvalue C lvalue of which to set bits.\r
+ * \param mask Bit-mask indicating bits to set.\r
+ *\r
+ * \return Resulting value with set bits.\r
+ */\r
+#define Set_bits(lvalue, mask) ((lvalue) |= (mask))\r
+\r
+/*! \brief Toggles the bits of a C lvalue specified by a given bit-mask.\r
+ *\r
+ * \param lvalue C lvalue of which to toggle bits.\r
+ * \param mask Bit-mask indicating bits to toggle.\r
+ *\r
+ * \return Resulting value with toggled bits.\r
+ */\r
+#define Tgl_bits(lvalue, mask) ((lvalue) ^= (mask))\r
+\r
+/*! \brief Reads the bit-field of a value specified by a given bit-mask.\r
+ *\r
+ * \param value Value to read a bit-field from.\r
+ * \param mask Bit-mask indicating the bit-field to read.\r
+ *\r
+ * \return Read bit-field.\r
+ */\r
+#define Rd_bitfield( value, mask) (Rd_bits( value, mask) >> ctz(mask))\r
+\r
+/*! \brief Writes the bit-field of a C lvalue specified by a given bit-mask.\r
+ *\r
+ * \param lvalue C lvalue to write a bit-field to.\r
+ * \param mask Bit-mask indicating the bit-field to write.\r
+ * \param bitfield Bit-field to write.\r
+ *\r
+ * \return Resulting value with written bit-field.\r
+ */\r
+#define Wr_bitfield(lvalue, mask, bitfield) (Wr_bits(lvalue, mask, (U32)(bitfield) << ctz(mask)))\r
+\r
+//! @}\r
+\r
+/*! \brief This macro is used to test fatal errors.\r
+ *\r
+ * The macro tests if the expression is FALSE. If it is, a fatal error is\r
+ * detected and the application hangs up.\r
+ *\r
+ * \param expr Expression to evaluate and supposed to be nonzero.\r
+ */\r
+#ifdef _ASSERT_ENABLE_\r
+ #define Assert(expr) \\r
+ {\\r
+ if (!(expr)) while (TRUE);\\r
+ }\r
+#else\r
+ #define Assert(expr)\r
+#endif\r
+\r
+/*! \name Zero-Bit Counting Macros\r
+ *\r
+ * Under AVR32-GCC, __builtin_clz and __builtin_ctz behave like macros when\r
+ * applied to constant expressions (values known at compile time), so they are\r
+ * more optimized than the use of the corresponding assembly instructions and\r
+ * they can be used as constant expressions e.g. to initialize objects having\r
+ * static storage duration, and like the corresponding assembly instructions\r
+ * when applied to non-constant expressions (values unknown at compile time), so\r
+ * they are more optimized than an assembly periphrasis. Hence, clz and ctz\r
+ * ensure a possible and optimized behavior for both constant and non-constant\r
+ * expressions.\r
+ */\r
+//! @{\r
+\r
+/*! \brief Counts the leading zero bits of the given value considered as a 32-bit integer.\r
+ *\r
+ * \param u Value of which to count the leading zero bits.\r
+ *\r
+ * \return The count of leading zero bits in \a u.\r
+ */\r
+#if __GNUC__\r
+ #define clz(u) __builtin_clz(u)\r
+#elif __ICCAVR32__\r
+ #define clz(u) __count_leading_zeros(u)\r
+#endif\r
+\r
+/*! \brief Counts the trailing zero bits of the given value considered as a 32-bit integer.\r
+ *\r
+ * \param u Value of which to count the trailing zero bits.\r
+ *\r
+ * \return The count of trailing zero bits in \a u.\r
+ */\r
+#if __GNUC__\r
+ #define ctz(u) __builtin_ctz(u)\r
+#elif __ICCAVR32__\r
+ #define ctz(u) __count_trailing_zeros(u)\r
+#endif\r
+\r
+//! @}\r
+\r
+/*! \name Alignment Macros\r
+ */\r
+//! @{\r
+\r
+/*! \brief Tests alignment of the number \a val with the \a n boundary.\r
+ *\r
+ * \param val Input value.\r
+ * \param n Boundary.\r
+ *\r
+ * \return \c 1 if the number \a val is aligned with the \a n boundary, else \c 0.\r
+ */\r
+#define Test_align(val, n ) (!Tst_bits( val, (n) - 1 ) )\r
+\r
+/*! \brief Gets alignment of the number \a val with respect to the \a n boundary.\r
+ *\r
+ * \param val Input value.\r
+ * \param n Boundary.\r
+ *\r
+ * \return Alignment of the number \a val with respect to the \a n boundary.\r
+ */\r
+#define Get_align( val, n ) ( Rd_bits( val, (n) - 1 ) )\r
+\r
+/*! \brief Sets alignment of the lvalue number \a lval to \a alg with respect to the \a n boundary.\r
+ *\r
+ * \param lval Input/output lvalue.\r
+ * \param n Boundary.\r
+ * \param alg Alignment.\r
+ *\r
+ * \return New value of \a lval resulting from its alignment set to \a alg with respect to the \a n boundary.\r
+ */\r
+#define Set_align(lval, n, alg) ( Wr_bits(lval, (n) - 1, alg) )\r
+\r
+/*! \brief Aligns the number \a val with the upper \a n boundary.\r
+ *\r
+ * \param val Input value.\r
+ * \param n Boundary.\r
+ *\r
+ * \return Value resulting from the number \a val aligned with the upper \a n boundary.\r
+ */\r
+#define Align_up( val, n ) (((val) + ((n) - 1)) & ~((n) - 1))\r
+\r
+/*! \brief Aligns the number \a val with the lower \a n boundary.\r
+ *\r
+ * \param val Input value.\r
+ * \param n Boundary.\r
+ *\r
+ * \return Value resulting from the number \a val aligned with the lower \a n boundary.\r
+ */\r
+#define Align_down(val, n ) ( (val) & ~((n) - 1))\r
+\r
+//! @}\r
+\r
+/*! \name Mathematics Macros\r
+ *\r
+ * The same considerations as for clz and ctz apply here but AVR32-GCC does not\r
+ * provide built-in functions to access the assembly instructions abs, min and\r
+ * max and it does not produce them by itself in most cases, so two sets of\r
+ * macros are defined here:\r
+ * - Abs, Min and Max to apply to constant expressions (values known at\r
+ * compile time);\r
+ * - abs, min and max to apply to non-constant expressions (values unknown at\r
+ * compile time).\r
+ */\r
+//! @{\r
+\r
+/*! \brief Takes the absolute value of \a a.\r
+ *\r
+ * \param a Input value.\r
+ *\r
+ * \return Absolute value of \a a.\r
+ *\r
+ * \note More optimized if only used with values known at compile time.\r
+ */\r
+#define Abs(a) (((a) < 0 ) ? -(a) : (a))\r
+\r
+/*! \brief Takes the minimal value of \a a and \a b.\r
+ *\r
+ * \param a Input value.\r
+ * \param b Input value.\r
+ *\r
+ * \return Minimal value of \a a and \a b.\r
+ *\r
+ * \note More optimized if only used with values known at compile time.\r
+ */\r
+#define Min(a, b) (((a) < (b)) ? (a) : (b))\r
+\r
+/*! \brief Takes the maximal value of \a a and \a b.\r
+ *\r
+ * \param a Input value.\r
+ * \param b Input value.\r
+ *\r
+ * \return Maximal value of \a a and \a b.\r
+ *\r
+ * \note More optimized if only used with values known at compile time.\r
+ */\r
+#define Max(a, b) (((a) > (b)) ? (a) : (b))\r
+\r
+/*! \brief Takes the absolute value of \a a.\r
+ *\r
+ * \param a Input value.\r
+ *\r
+ * \return Absolute value of \a a.\r
+ *\r
+ * \note More optimized if only used with values unknown at compile time.\r
+ */\r
+#if __GNUC__\r
+ #define abs(a) \\r
+ (\\r
+ {\\r
+ int __value = (a);\\r
+ __asm__ ("abs\t%0" : "+r" (__value) : : "cc");\\r
+ __value;\\r
+ }\\r
+ )\r
+#elif __ICCAVR32__\r
+ #define abs(a) Abs(a)\r
+#endif\r
+\r
+/*! \brief Takes the minimal value of \a a and \a b.\r
+ *\r
+ * \param a Input value.\r
+ * \param b Input value.\r
+ *\r
+ * \return Minimal value of \a a and \a b.\r
+ *\r
+ * \note More optimized if only used with values unknown at compile time.\r
+ */\r
+#if __GNUC__\r
+ #define min(a, b) \\r
+ (\\r
+ {\\r
+ int __value, __arg_a = (a), __arg_b = (b);\\r
+ __asm__ ("min\t%0, %1, %2" : "=r" (__value) : "r" (__arg_a), "r" (__arg_b));\\r
+ __value;\\r
+ }\\r
+ )\r
+#elif __ICCAVR32__\r
+ #define min(a, b) Min(a, b)\r
+#endif\r
+\r
+/*! \brief Takes the maximal value of \a a and \a b.\r
+ *\r
+ * \param a Input value.\r
+ * \param b Input value.\r
+ *\r
+ * \return Maximal value of \a a and \a b.\r
+ *\r
+ * \note More optimized if only used with values unknown at compile time.\r
+ */\r
+#if __GNUC__\r
+ #define max(a, b) \\r
+ (\\r
+ {\\r
+ int __value, __arg_a = (a), __arg_b = (b);\\r
+ __asm__ ("max\t%0, %1, %2" : "=r" (__value) : "r" (__arg_a), "r" (__arg_b));\\r
+ __value;\\r
+ }\\r
+ )\r
+#elif __ICCAVR32__\r
+ #define max(a, b) Max(a, b)\r
+#endif\r
+\r
+//! @}\r
+\r
+/*! \brief Calls the routine at address \a addr.\r
+ *\r
+ * It generates a long call opcode.\r
+ *\r
+ * For example, `Long_call(0x80000000)' generates a software reset on a UC3 if\r
+ * it is invoked from the CPU supervisor mode.\r
+ *\r
+ * \param addr Address of the routine to call.\r
+ *\r
+ * \note It may be used as a long jump opcode in some special cases.\r
+ */\r
+#define Long_call(addr) ((*(void (*)(void))(addr))())\r
+\r
+/*! \brief Resets the CPU by software.\r
+ *\r
+ * \warning It shall not be called from the CPU application mode.\r
+ */\r
+#if __GNUC__\r
+ #define Reset_CPU() \\r
+ (\\r
+ {\\r
+ __asm__ __volatile__ (\\r
+ "lda.w r8, _start\n\t"\\r
+ "lddpc r9, 1f\n\t"\\r
+ "stm --sp, r8-r9\n\t"\\r
+ "mfsr r8, %[SR]\n\t"\\r
+ "bfextu r8, r8, %[SR_MX_OFFSET], %[SR_MX_SIZE]\n\t"\\r
+ "cp.w r8, 0b001\n\t"\\r
+ "breq 0f\n\t"\\r
+ "rete\n"\\r
+ "0:\n\t"\\r
+ "rets\n\t"\\r
+ ".balign 4\n"\\r
+ "1:\n\t"\\r
+ ".word %[RESET_SR]"\\r
+ :\\r
+ : [SR] "i" (AVR32_SR),\\r
+ [SR_MX_OFFSET] "i" (AVR32_SR_M0_OFFSET),\\r
+ [SR_MX_SIZE] "i" (AVR32_SR_M0_SIZE + AVR32_SR_M1_SIZE + AVR32_SR_M2_SIZE),\\r
+ [RESET_SR] "i" (AVR32_SR_GM_MASK | AVR32_SR_EM_MASK | AVR32_SR_M0_MASK)\\r
+ );\\r
+ }\\r
+ )\r
+#elif __ICCAVR32__\r
+ #define Reset_CPU() \\r
+ {\\r
+ extern void *volatile __program_start;\\r
+ __asm__ __volatile__ (\\r
+ "mov r8, LWRD(__program_start)\n\t"\\r
+ "orh r8, HWRD(__program_start)\n\t"\\r
+ "mov r9, LWRD("ASTRINGZ(AVR32_SR_GM_MASK | AVR32_SR_EM_MASK | AVR32_SR_M0_MASK)")\n\t"\\r
+ "orh r9, HWRD("ASTRINGZ(AVR32_SR_GM_MASK | AVR32_SR_EM_MASK | AVR32_SR_M0_MASK)")\n\t"\\r
+ "stm --sp, r8-r9\n\t"\\r
+ "mfsr r8, "ASTRINGZ(AVR32_SR)"\n\t"\\r
+ "bfextu r8, r8, "ASTRINGZ(AVR32_SR_M0_OFFSET)", "ASTRINGZ(AVR32_SR_M0_SIZE + AVR32_SR_M1_SIZE + AVR32_SR_M2_SIZE)"\n\t"\\r
+ "cp.w r8, 001b\n\t"\\r
+ "breq $ + 4\n\t"\\r
+ "rete\n\t"\\r
+ "rets"\\r
+ );\\r
+ __program_start;\\r
+}\r
+#endif\r
+\r
+/*! \name CPU Status Register Macros\r
+ */\r
+//! @{\r
+\r
+/*! \brief Disables all exceptions.\r
+ */\r
+#if __GNUC__\r
+ #define Disable_global_exception() ({__asm__ __volatile__ ("ssrf\t%0" : : "i" (AVR32_SR_EM_OFFSET));})\r
+#elif __ICCAVR32__\r
+ #define Disable_global_exception() (__set_status_flag(AVR32_SR_EM_OFFSET))\r
+#endif\r
+\r
+/*! \brief Enables all exceptions.\r
+ */\r
+#if __GNUC__\r
+ #define Enable_global_exception() ({__asm__ __volatile__ ("csrf\t%0" : : "i" (AVR32_SR_EM_OFFSET));})\r
+#elif __ICCAVR32__\r
+ #define Enable_global_exception() (__clear_status_flag(AVR32_SR_EM_OFFSET))\r
+#endif\r
+\r
+/*! \brief Disables all interrupts.\r
+ */\r
+#if __GNUC__\r
+ #define Disable_global_interrupt() ({__asm__ __volatile__ ("ssrf\t%0\n\tnop\n\tnop" : : "i" (AVR32_SR_GM_OFFSET));})\r
+#elif __ICCAVR32__\r
+ #define Disable_global_interrupt() {__asm__ __volatile__ ("ssrf\t"ASTRINGZ(AVR32_SR_GM_OFFSET)"\n\tnop\n\tnop");}\r
+#endif\r
+\r
+/*! \brief Enables all interrupts.\r
+ */\r
+#if __GNUC__\r
+ #define Enable_global_interrupt() ({__asm__ __volatile__ ("csrf\t%0" : : "i" (AVR32_SR_GM_OFFSET));})\r
+#elif __ICCAVR32__\r
+ #define Enable_global_interrupt() (__enable_interrupt())\r
+#endif\r
+\r
+/*! \brief Disables interrupt level \a int_lev.\r
+ *\r
+ * \param int_lev Interrupt level to disable (0 to 3).\r
+ */\r
+#if __GNUC__\r
+ #define Disable_interrupt_level(int_lev) ({__asm__ __volatile__ ("ssrf\t%0\n\tnop\n\tnop" : : "i" (TPASTE3(AVR32_SR_I, int_lev, M_OFFSET)));})\r
+#elif __ICCAVR32__\r
+ #define Disable_interrupt_level(int_lev) {__asm__ __volatile__ ("ssrf\t"ASTRINGZ(TPASTE3(AVR32_SR_I, int_lev, M_OFFSET))"\n\tnop\n\tnop");}\r
+#endif\r
+\r
+/*! \brief Enables interrupt level \a int_lev.\r
+ *\r
+ * \param int_lev Interrupt level to enable (0 to 3).\r
+ */\r
+#if __GNUC__\r
+ #define Enable_interrupt_level(int_lev) ({__asm__ __volatile__ ("csrf\t%0" : : "i" (TPASTE3(AVR32_SR_I, int_lev, M_OFFSET)));})\r
+#elif __ICCAVR32__\r
+ #define Enable_interrupt_level(int_lev) (__clear_status_flag(TPASTE3(AVR32_SR_I, int_lev, M_OFFSET)))\r
+#endif\r
+\r
+//! @}\r
+\r
+/*! \name System Register Access Macros\r
+ */\r
+//! @{\r
+\r
+/*! \brief Gets the value of the \a sysreg system register.\r
+ *\r
+ * \param sysreg Address of the system register of which to get the value.\r
+ *\r
+ * \return Value of the \a sysreg system register.\r
+ */\r
+#if __GNUC__\r
+ #define Get_system_register(sysreg) __builtin_mfsr(sysreg)\r
+#elif __ICCAVR32__\r
+ #define Get_system_register(sysreg) __get_system_register(sysreg)\r
+#endif\r
+\r
+/*! \brief Sets the value of the \a sysreg system register to \a value.\r
+ *\r
+ * \param sysreg Address of the system register of which to set the value.\r
+ * \param value Value to set the \a sysreg system register to.\r
+ */\r
+#if __GNUC__\r
+ #define Set_system_register(sysreg, value) __builtin_mtsr(sysreg, value)\r
+#elif __ICCAVR32__\r
+ #define Set_system_register(sysreg, value) __set_system_register(sysreg, value)\r
+#endif\r
+\r
+//! @}\r
+\r
+#endif // __AVR32_ABI_COMPILER__\r
+\r
+//! Boolean evaluating MCU little endianism.\r
+#if (__GNUC__ && __AVR32__) || (__ICCAVR32__ || __AAVR32__)\r
+ #define LITTLE_ENDIAN_MCU FALSE\r
+#endif\r
+\r
+// Check that MCU endianism is correctly defined.\r
+#ifndef LITTLE_ENDIAN_MCU\r
+ #error YOU MUST define the MCU endianism with LITTLE_ENDIAN_MCU: either FALSE or TRUE\r
+#endif\r
+\r
+//! Boolean evaluating MCU big endianism.\r
+#define BIG_ENDIAN_MCU (!LITTLE_ENDIAN_MCU)\r
+\r
+#ifdef __AVR32_ABI_COMPILER__ // Automatically defined when compiling for AVR32, not when assembling.\r
+\r
+/*! \name U16/U32/U64 MCU Endianism Handling Macros\r
+ */\r
+//! @{\r
+#if LITTLE_ENDIAN_MCU\r
+ #define LSB(u16) (((U8 *)&(u16))[0]) //!< Least significant byte of \a u16.\r
+ #define MSB(u16) (((U8 *)&(u16))[1]) //!< Most significant byte of \a u16.\r
+ #define LSH(u32) (((U16 *)&(u32))[0]) //!< Least significant half-word of \a u32.\r
+ #define MSH(u32) (((U16 *)&(u32))[1]) //!< Most significant half-word of \a u32.\r
+ #define LSB0W(u32) (((U8 *)&(u32))[0]) //!< Least significant byte of 1st rank of \a u32.\r
+ #define LSB1W(u32) (((U8 *)&(u32))[1]) //!< Least significant byte of 2nd rank of \a u32.\r
+ #define LSB2W(u32) (((U8 *)&(u32))[2]) //!< Least significant byte of 3rd rank of \a u32.\r
+ #define LSB3W(u32) (((U8 *)&(u32))[3]) //!< Least significant byte of 4th rank of \a u32.\r
+ #define MSB3W(u32) LSB0W(u32) //!< Most significant byte of 1st rank of \a u32.\r
+ #define MSB2W(u32) LSB1W(u32) //!< Most significant byte of 2nd rank of \a u32.\r
+ #define MSB1W(u32) LSB2W(u32) //!< Most significant byte of 3rd rank of \a u32.\r
+ #define MSB0W(u32) LSB3W(u32) //!< Most significant byte of 4th rank of \a u32.\r
+ #define LSW(u64) (((U32 *)&(u64))[0]) //!< Least significant word of \a u64.\r
+ #define MSW(u64) (((U32 *)&(u64))[1]) //!< Most significant word of \a u64.\r
+ #define LSH0(u64) (((U16 *)&(u64))[0]) //!< Least significant half-word of 1st rank of \a u64.\r
+ #define LSH1(u64) (((U16 *)&(u64))[1]) //!< Least significant half-word of 2nd rank of \a u64.\r
+ #define LSH2(u64) (((U16 *)&(u64))[2]) //!< Least significant half-word of 3rd rank of \a u64.\r
+ #define LSH3(u64) (((U16 *)&(u64))[3]) //!< Least significant half-word of 4th rank of \a u64.\r
+ #define MSH3(u64) LSH0(u64) //!< Most significant half-word of 1st rank of \a u64.\r
+ #define MSH2(u64) LSH1(u64) //!< Most significant half-word of 2nd rank of \a u64.\r
+ #define MSH1(u64) LSH2(u64) //!< Most significant half-word of 3rd rank of \a u64.\r
+ #define MSH0(u64) LSH3(u64) //!< Most significant half-word of 4th rank of \a u64.\r
+ #define LSB0D(u64) (((U8 *)&(u64))[0]) //!< Least significant byte of 1st rank of \a u64.\r
+ #define LSB1D(u64) (((U8 *)&(u64))[1]) //!< Least significant byte of 2nd rank of \a u64.\r
+ #define LSB2D(u64) (((U8 *)&(u64))[2]) //!< Least significant byte of 3rd rank of \a u64.\r
+ #define LSB3D(u64) (((U8 *)&(u64))[3]) //!< Least significant byte of 4th rank of \a u64.\r
+ #define LSB4D(u64) (((U8 *)&(u64))[4]) //!< Least significant byte of 5th rank of \a u64.\r
+ #define LSB5D(u64) (((U8 *)&(u64))[5]) //!< Least significant byte of 6th rank of \a u64.\r
+ #define LSB6D(u64) (((U8 *)&(u64))[6]) //!< Least significant byte of 7th rank of \a u64.\r
+ #define LSB7D(u64) (((U8 *)&(u64))[7]) //!< Least significant byte of 8th rank of \a u64.\r
+ #define MSB7D(u64) LSB0D(u64) //!< Most significant byte of 1st rank of \a u64.\r
+ #define MSB6D(u64) LSB1D(u64) //!< Most significant byte of 2nd rank of \a u64.\r
+ #define MSB5D(u64) LSB2D(u64) //!< Most significant byte of 3rd rank of \a u64.\r
+ #define MSB4D(u64) LSB3D(u64) //!< Most significant byte of 4th rank of \a u64.\r
+ #define MSB3D(u64) LSB4D(u64) //!< Most significant byte of 5th rank of \a u64.\r
+ #define MSB2D(u64) LSB5D(u64) //!< Most significant byte of 6th rank of \a u64.\r
+ #define MSB1D(u64) LSB6D(u64) //!< Most significant byte of 7th rank of \a u64.\r
+ #define MSB0D(u64) LSB7D(u64) //!< Most significant byte of 8th rank of \a u64.\r
+#else // BIG_ENDIAN_MCU\r
+ #define MSB(u16) (((U8 *)&(u16))[0]) //!< Most significant byte of \a u16.\r
+ #define LSB(u16) (((U8 *)&(u16))[1]) //!< Least significant byte of \a u16.\r
+ #define MSH(u32) (((U16 *)&(u32))[0]) //!< Most significant half-word of \a u32.\r
+ #define LSH(u32) (((U16 *)&(u32))[1]) //!< Least significant half-word of \a u32.\r
+ #define MSB0W(u32) (((U8 *)&(u32))[0]) //!< Most significant byte of 1st rank of \a u32.\r
+ #define MSB1W(u32) (((U8 *)&(u32))[1]) //!< Most significant byte of 2nd rank of \a u32.\r
+ #define MSB2W(u32) (((U8 *)&(u32))[2]) //!< Most significant byte of 3rd rank of \a u32.\r
+ #define MSB3W(u32) (((U8 *)&(u32))[3]) //!< Most significant byte of 4th rank of \a u32.\r
+ #define LSB3W(u32) MSB0W(u32) //!< Least significant byte of 1st rank of \a u32.\r
+ #define LSB2W(u32) MSB1W(u32) //!< Least significant byte of 2nd rank of \a u32.\r
+ #define LSB1W(u32) MSB2W(u32) //!< Least significant byte of 3rd rank of \a u32.\r
+ #define LSB0W(u32) MSB3W(u32) //!< Least significant byte of 4th rank of \a u32.\r
+ #define MSW(u64) (((U32 *)&(u64))[0]) //!< Most significant word of \a u64.\r
+ #define LSW(u64) (((U32 *)&(u64))[1]) //!< Least significant word of \a u64.\r
+ #define MSH0(u64) (((U16 *)&(u64))[0]) //!< Most significant half-word of 1st rank of \a u64.\r
+ #define MSH1(u64) (((U16 *)&(u64))[1]) //!< Most significant half-word of 2nd rank of \a u64.\r
+ #define MSH2(u64) (((U16 *)&(u64))[2]) //!< Most significant half-word of 3rd rank of \a u64.\r
+ #define MSH3(u64) (((U16 *)&(u64))[3]) //!< Most significant half-word of 4th rank of \a u64.\r
+ #define LSH3(u64) MSH0(u64) //!< Least significant half-word of 1st rank of \a u64.\r
+ #define LSH2(u64) MSH1(u64) //!< Least significant half-word of 2nd rank of \a u64.\r
+ #define LSH1(u64) MSH2(u64) //!< Least significant half-word of 3rd rank of \a u64.\r
+ #define LSH0(u64) MSH3(u64) //!< Least significant half-word of 4th rank of \a u64.\r
+ #define MSB0D(u64) (((U8 *)&(u64))[0]) //!< Most significant byte of 1st rank of \a u64.\r
+ #define MSB1D(u64) (((U8 *)&(u64))[1]) //!< Most significant byte of 2nd rank of \a u64.\r
+ #define MSB2D(u64) (((U8 *)&(u64))[2]) //!< Most significant byte of 3rd rank of \a u64.\r
+ #define MSB3D(u64) (((U8 *)&(u64))[3]) //!< Most significant byte of 4th rank of \a u64.\r
+ #define MSB4D(u64) (((U8 *)&(u64))[4]) //!< Most significant byte of 5th rank of \a u64.\r
+ #define MSB5D(u64) (((U8 *)&(u64))[5]) //!< Most significant byte of 6th rank of \a u64.\r
+ #define MSB6D(u64) (((U8 *)&(u64))[6]) //!< Most significant byte of 7th rank of \a u64.\r
+ #define MSB7D(u64) (((U8 *)&(u64))[7]) //!< Most significant byte of 8th rank of \a u64.\r
+ #define LSB7D(u64) MSB0D(u64) //!< Least significant byte of 1st rank of \a u64.\r
+ #define LSB6D(u64) MSB1D(u64) //!< Least significant byte of 2nd rank of \a u64.\r
+ #define LSB5D(u64) MSB2D(u64) //!< Least significant byte of 3rd rank of \a u64.\r
+ #define LSB4D(u64) MSB3D(u64) //!< Least significant byte of 4th rank of \a u64.\r
+ #define LSB3D(u64) MSB4D(u64) //!< Least significant byte of 5th rank of \a u64.\r
+ #define LSB2D(u64) MSB5D(u64) //!< Least significant byte of 6th rank of \a u64.\r
+ #define LSB1D(u64) MSB6D(u64) //!< Least significant byte of 7th rank of \a u64.\r
+ #define LSB0D(u64) MSB7D(u64) //!< Least significant byte of 8th rank of \a u64.\r
+#endif\r
+//! @}\r
+\r
+/*! \name Endianism Conversion Macros\r
+ *\r
+ * The same considerations as for clz and ctz apply here but AVR32-GCC's\r
+ * __builtin_bswap_16 and __builtin_bswap_32 do not behave like macros when\r
+ * applied to constant expressions, so two sets of macros are defined here:\r
+ * - Swap16, Swap32 and Swap64 to apply to constant expressions (values known\r
+ * at compile time);\r
+ * - swap16, swap32 and swap64 to apply to non-constant expressions (values\r
+ * unknown at compile time).\r
+ */\r
+//! @{\r
+\r
+/*! \brief Toggles the endianism of \a u16 (by swapping its bytes).\r
+ *\r
+ * \param u16 U16 of which to toggle the endianism.\r
+ *\r
+ * \return Value resulting from \a u16 with toggled endianism.\r
+ *\r
+ * \note More optimized if only used with values known at compile time.\r
+ */\r
+#define Swap16(u16) ((U16)(((U16)(u16) >> 8) |\\r
+ ((U16)(u16) << 8)))\r
+\r
+/*! \brief Toggles the endianism of \a u32 (by swapping its bytes).\r
+ *\r
+ * \param u32 U32 of which to toggle the endianism.\r
+ *\r
+ * \return Value resulting from \a u32 with toggled endianism.\r
+ *\r
+ * \note More optimized if only used with values known at compile time.\r
+ */\r
+#define Swap32(u32) ((U32)(((U32)Swap16((U32)(u32) >> 16)) |\\r
+ ((U32)Swap16((U32)(u32)) << 16)))\r
+\r
+/*! \brief Toggles the endianism of \a u64 (by swapping its bytes).\r
+ *\r
+ * \param u64 U64 of which to toggle the endianism.\r
+ *\r
+ * \return Value resulting from \a u64 with toggled endianism.\r
+ *\r
+ * \note More optimized if only used with values known at compile time.\r
+ */\r
+#define Swap64(u64) ((U64)(((U64)Swap32((U64)(u64) >> 32)) |\\r
+ ((U64)Swap32((U64)(u64)) << 32)))\r
+\r
+/*! \brief Toggles the endianism of \a u16 (by swapping its bytes).\r
+ *\r
+ * \param u16 U16 of which to toggle the endianism.\r
+ *\r
+ * \return Value resulting from \a u16 with toggled endianism.\r
+ *\r
+ * \note More optimized if only used with values unknown at compile time.\r
+ */\r
+#if __GNUC__\r
+ #define swap16(u16) __builtin_bswap_16(u16)\r
+#elif __ICCAVR32__\r
+ #define swap16(u16) Swap16(u16)\r
+#endif\r
+\r
+/*! \brief Toggles the endianism of \a u32 (by swapping its bytes).\r
+ *\r
+ * \param u32 U32 of which to toggle the endianism.\r
+ *\r
+ * \return Value resulting from \a u32 with toggled endianism.\r
+ *\r
+ * \note More optimized if only used with values unknown at compile time.\r
+ */\r
+#if __GNUC__\r
+ #define swap32(u32) __builtin_bswap_32(u32)\r
+#elif __ICCAVR32__\r
+ #define swap32(u32) Swap32(u32)\r
+#endif\r
+\r
+/*! \brief Toggles the endianism of \a u64 (by swapping its bytes).\r
+ *\r
+ * \param u64 U64 of which to toggle the endianism.\r
+ *\r
+ * \return Value resulting from \a u64 with toggled endianism.\r
+ *\r
+ * \note More optimized if only used with values unknown at compile time.\r
+ */\r
+#define swap64(u64) ((U64)(((U64)swap32((U64)(u64) >> 32)) |\\r
+ ((U64)swap32((U64)(u64)) << 32)))\r
+\r
+//! @}\r
+\r
+#endif // __AVR32_ABI_COMPILER__\r
+\r
+\r
+#endif // _COMPILER_H_\r
--- /dev/null
+/* This header file is part of the ATMEL FREERTOS-0.9.0 Release */\r
+\r
+/*This file is prepared for Doxygen automatic documentation generation.*/\r
+/*! \file ******************************************************************\r
+ *\r
+ * \brief Ethernet module configuration file.\r
+ *\r
+ * This file contains the possible external configuration of the Ethernet module.\r
+ *\r
+ * - Compiler: IAR EWAVR32 and GNU GCC for AVR32\r
+ * - Supported devices: All AVR32 devices can be used.\r
+ * - AppNote:\r
+ *\r
+ * \author Atmel Corporation: http://www.atmel.com \n\r
+ * Support email: avr32@atmel.com\r
+ *\r
+ ***************************************************************************/\r
+\r
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of ATMEL may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND\r
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,\r
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\r
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\r
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF\r
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ */\r
+\r
+\r
+#ifndef _CONF_ETH_H_\r
+#define _CONF_ETH_H_\r
+\r
+/*! define stack size for WEB server task */\r
+#define lwipBASIC_WEB_SERVER_STACK_SIZE 256\r
+\r
+/*! define stack size for TFTP server task */\r
+#define lwipBASIC_TFTP_SERVER_STACK_SIZE 1024\r
+\r
+/*! define stack size for SMTP host task */\r
+#define lwipBASIC_SMTP_HOST_STACK_SIZE 256\r
+\r
+/*! define stack size for lwIP task */\r
+#define lwipINTERFACE_STACK_SIZE 512\r
+\r
+/*! define stack size for netif task */\r
+#define netifINTERFACE_TASK_STACK_SIZE 256\r
+\r
+/*! define WEB server priority */\r
+#define ethWEBSERVER_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
+\r
+/*! define TFTP server priority */\r
+#define ethTFTPSERVER_PRIORITY ( tskIDLE_PRIORITY + 3 )\r
+\r
+/*! define SMTP host priority */\r
+#define ethSMTPHOST_PRIORITY ( tskIDLE_PRIORITY + 5 )\r
+\r
+/*! define lwIP task priority */\r
+#define lwipINTERFACE_TASK_PRIORITY ( configMAX_PRIORITIES - 1 )\r
+\r
+/*! define netif task priority */\r
+#define netifINTERFACE_TASK_PRIORITY ( configMAX_PRIORITIES - 1 )\r
+\r
+/*! Number of threads that can be started with sys_thread_new() */\r
+#define SYS_THREAD_MAX 6\r
+\r
+/*! LED used by the ethernet task, toggled on each activation */\r
+#define webCONN_LED 7\r
+\r
+/*! Use Auto Negociation to get speed and duplex */\r
+#define ETHERNET_CONF_AN_ENABLE 1\r
+\r
+/*! Do not use auto cross capability */\r
+#define ETHERNET_CONF_AUTO_CROSS_ENABLE 0\r
+/*! use direct cable */\r
+#define ETHERNET_CONF_CROSSED_LINK 0\r
+\r
+\r
+/* ethernet default parameters */\r
+/*! MAC address definition. The MAC address must be unique on the network. */\r
+#define emacETHADDR0 0x00\r
+#define emacETHADDR1 0x04\r
+#define emacETHADDR2 0x25\r
+#define emacETHADDR3 0x40\r
+#define emacETHADDR4 0x40\r
+#define emacETHADDR5 0x40\r
+\r
+#if 0\r
+/*! The IP address being used. */\r
+#define emacIPADDR0 10\r
+#define emacIPADDR1 172\r
+#define emacIPADDR2 214\r
+#define emacIPADDR3 40\r
+\r
+/*! The gateway address being used. */\r
+#define emacGATEWAY_ADDR0 10\r
+#define emacGATEWAY_ADDR1 172\r
+#define emacGATEWAY_ADDR2 250\r
+#define emacGATEWAY_ADDR3 1\r
+\r
+/*! The network mask being used. */\r
+#define emacNET_MASK0 255\r
+#define emacNET_MASK1 255\r
+#define emacNET_MASK2 0\r
+#define emacNET_MASK3 0\r
+\r
+#else\r
+/*! The IP address being used. */\r
+#define emacIPADDR0 192\r
+#define emacIPADDR1 168\r
+#define emacIPADDR2 0\r
+#define emacIPADDR3 2\r
+\r
+/*! The gateway address being used. */\r
+#define emacGATEWAY_ADDR0 192\r
+#define emacGATEWAY_ADDR1 168\r
+#define emacGATEWAY_ADDR2 0\r
+#define emacGATEWAY_ADDR3 1\r
+\r
+/*! The network mask being used. */\r
+#define emacNET_MASK0 255\r
+#define emacNET_MASK1 255\r
+#define emacNET_MASK2 255\r
+#define emacNET_MASK3 0\r
+#endif\r
+\r
+#endif\r
--- /dev/null
+/* This source file is part of the ATMEL FREERTOS-0.9.0 Release */\r
+\r
+/*This file has been prepared for Doxygen automatic documentation generation.*/\r
+/*! \file *********************************************************************\r
+ *\r
+ * \brief FreeRTOS and lwIP example for AVR32 UC3.\r
+ *\r
+ * - Compiler: GNU GCC for AVR32\r
+ * - Supported devices: All AVR32 devices can be used.\r
+ * - AppNote:\r
+ *\r
+ * \author Atmel Corporation: http://www.atmel.com \n\r
+ * Support email: avr32@atmel.com\r
+ *\r
+ *****************************************************************************/\r
+\r
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of ATMEL may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND\r
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,\r
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\r
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\r
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF\r
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ */\r
+\r
+\r
+/* Environment include files. */\r
+#include <stdlib.h>\r
+#include <string.h>\r
+#include "pm.h"\r
+#include "flashc.h"\r
+\r
+/* Scheduler include files. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/* Demo file headers. */\r
+#include "partest.h"\r
+#include "serial.h"\r
+#include "ethernet.h"\r
+#include "netif/etharp.h"\r
+#include "flash.h"\r
+\r
+/* Priority definitions for most of the tasks in the demo application. */\r
+#define mainLED_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 )\r
+#define mainETH_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 )\r
+\r
+/* Baud rate used by the serial port tasks. */\r
+#define mainCOM_BAUD_RATE ( ( unsigned portLONG ) 57600 )\r
+#define mainCOM_BUFFER_LEN ( ( unsigned portLONG ) 70 )\r
+\r
+/* An address in the internal Flash used to count resets. This is used to check that\r
+the demo application is not unexpectedly resetting. */\r
+#define mainRESET_COUNT_ADDRESS ( ( void * ) 0xC0000000 )\r
+\r
+\r
+//!\r
+//! \fn main\r
+//! \brief start the software here\r
+//! 1) Initialize the microcontroller and the shared hardware resources\r
+//! of the board.\r
+//! 2) Launch the IP modules.\r
+//! 3) Start FreeRTOS.\r
+//! \return 42, which should never occur.\r
+//! \note\r
+//!\r
+int main( void )\r
+{\r
+volatile avr32_pm_t* pm = &AVR32_PM;\r
+\r
+ /* 1) Initialize the microcontroller and the shared hardware resources of the board. */\r
+\r
+ /* Switch to external oscillator 0 */\r
+ pm_switch_to_osc0( pm, FOSC0, OSC0_STARTUP );\r
+\r
+ /* Setup PLL0 on OSC0, mul+1=16 ,divisor by 1, lockcount=16, ie. 12Mhzx16/1 = 192MHz output.\r
+ Extra div by 2 => 96MHz */\r
+ pm_pll_setup(pm, /* volatile avr32_pm_t* pm */\r
+ 0, /* unsigned int pll */\r
+ 15, /* unsigned int mul */\r
+ 1, /* unsigned int div, Sel Osc0/PLL0 or Osc1/Pll1 */\r
+ 0, /* unsigned int osc */\r
+ 16); /* unsigned int lockcount */\r
+\r
+ pm_pll_set_option( pm, 0, // pll0\r
+ 0, // Choose the range 160-240MHz.\r
+ 1, // div2\r
+ 0 ); // wbwdisable\r
+\r
+ /* Enable PLL0 */\r
+ pm_pll_enable(pm,0);\r
+\r
+ /* Wait for PLL0 locked */\r
+ pm_wait_for_pll0_locked(pm) ;\r
+\r
+ /* Setup generic clock number 2 on PLL, with OSC0/PLL0, no divisor */\r
+ pm_gc_setup(pm,\r
+ 0,\r
+ 1, /* Use Osc (=0) or PLL (=1) */\r
+ 0, /* Sel Osc0/PLL0 or Osc1/Pll1 */\r
+ 0,\r
+ 1);\r
+\r
+ /* Enable Generic clock 0*/\r
+ pm_gc_enable(pm, 0);\r
+\r
+ /* switch to clock */\r
+ pm_cksel( pm, 1, 1, 1, 0, 1, 0 );\r
+ flashc_set_wait_state( 1 );\r
+ pm_switch_to_clock( pm, AVR32_PM_MCCTRL_MCSEL_PLL0 );\r
+\r
+ /* Setup the LED's for output. */\r
+ vParTestInitialise();\r
+\r
+ /* Start the flash tasks just to provide visual feedback that the demo is\r
+ executing. */\r
+ vStartLEDFlashTasks( mainLED_TASK_PRIORITY );\r
+\r
+ /* 2) Start ethernet task. */\r
+ vStartEthernetTask( mainETH_TASK_PRIORITY );\r
+\r
+ /* 3) Start FreeRTOS. */\r
+ vTaskStartScheduler();\r
+\r
+ /* Will only reach here if there was insufficient memory to create the idle task. */\r
+\r
+ return 0;\r
+}\r
+/*-----------------------------------------------------------*/\r
--- /dev/null
+/* This source file is part of the ATMEL FREERTOS-0.9.0 Release */\r
+\r
+/*This file has been prepared for Doxygen automatic documentation generation.*/\r
+/*! \file *********************************************************************\r
+ *\r
+ * \brief sprintf functions to replace newlib for AVR32 UC3.\r
+ *\r
+ * - Compiler: IAR EWAVR32 and GNU GCC for AVR32\r
+ * - Supported devices: All AVR32 devices can be used.\r
+ * - AppNote:\r
+ *\r
+ * \author Atmel Corporation: http://www.atmel.com \n\r
+ * Support email: avr32@atmel.com\r
+ *\r
+ *****************************************************************************/\r
+\r
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of ATMEL may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND\r
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,\r
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\r
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\r
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF\r
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ */\r
+\r
+/*\r
+ Copyright 2001, 2002 Georges Menie (www.menie.org)\r
+ stdarg version contributed by Christian Ettinger\r
+\r
+ This program is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU Lesser General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ This program is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU Lesser General Public License for more details.\r
+\r
+ You should have received a copy of the GNU Lesser General Public License\r
+ along with this program; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+*/\r
+\r
+/*\r
+ putchar is the only external dependency for this file,\r
+ if you have a working putchar, leave it commented out.\r
+ If not, uncomment the define below and\r
+ replace outbyte(c) by your own function call.\r
+\r
+#define putchar(c) outbyte(c)\r
+*/\r
+\r
+#include <sys/reent.h>\r
+#include <stdarg.h>\r
+\r
+\r
+static void printchar(char **str, int c)\r
+{\r
+ extern int putchar(int c);\r
+ \r
+ if (str) {\r
+ **str = c;\r
+ ++(*str);\r
+ }\r
+ else (void)putchar(c);\r
+}\r
+\r
+#define PAD_RIGHT 1\r
+#define PAD_ZERO 2\r
+\r
+static int prints(char **out, const char *string, int width, int pad)\r
+{\r
+ register int pc = 0, padchar = ' ';\r
+\r
+ if (width > 0) {\r
+ register int len = 0;\r
+ register const char *ptr;\r
+ for (ptr = string; *ptr; ++ptr) ++len;\r
+ if (len >= width) width = 0;\r
+ else width -= len;\r
+ if (pad & PAD_ZERO) padchar = '0';\r
+ }\r
+ if (!(pad & PAD_RIGHT)) {\r
+ for ( ; width > 0; --width) {\r
+ printchar (out, padchar);\r
+ ++pc;\r
+ }\r
+ }\r
+ for ( ; *string ; ++string) {\r
+ printchar (out, *string);\r
+ ++pc;\r
+ }\r
+ for ( ; width > 0; --width) {\r
+ printchar (out, padchar);\r
+ ++pc;\r
+ }\r
+\r
+ return pc;\r
+}\r
+\r
+/* the following should be enough for 32 bit int */\r
+#define PRINT_BUF_LEN 12\r
+\r
+static int printi(char **out, int i, int b, int sg, int width, int pad, int letbase)\r
+{\r
+ char print_buf[PRINT_BUF_LEN];\r
+ register char *s;\r
+ register int t, neg = 0, pc = 0;\r
+ register unsigned int u = i;\r
+\r
+ if (i == 0) {\r
+ print_buf[0] = '0';\r
+ print_buf[1] = '\0';\r
+ return prints (out, print_buf, width, pad);\r
+ }\r
+\r
+ if (sg && b == 10 && i < 0) {\r
+ neg = 1;\r
+ u = -i;\r
+ }\r
+\r
+ s = print_buf + PRINT_BUF_LEN-1;\r
+ *s = '\0';\r
+\r
+ while (u) {\r
+ t = u % b;\r
+ if( t >= 10 )\r
+ t += letbase - '0' - 10;\r
+ *--s = t + '0';\r
+ u /= b;\r
+ }\r
+\r
+ if (neg) {\r
+ if( width && (pad & PAD_ZERO) ) {\r
+ printchar (out, '-');\r
+ ++pc;\r
+ --width;\r
+ }\r
+ else {\r
+ *--s = '-';\r
+ }\r
+ }\r
+\r
+ return pc + prints (out, s, width, pad);\r
+}\r
+\r
+int fprintf(__FILE *stream, const char *format, ...)\r
+{\r
+return 0;\r
+}\r
+static int print(char **out, const char *format, va_list args )\r
+{\r
+ register int width, pad;\r
+ register int pc = 0;\r
+ char scr[2];\r
+\r
+ for (; *format != 0; ++format) {\r
+ if (*format == '%') {\r
+ ++format;\r
+ width = pad = 0;\r
+ if (*format == '\0') break;\r
+ if (*format == '%') goto out;\r
+ if (*format == '-') {\r
+ ++format;\r
+ pad = PAD_RIGHT;\r
+ }\r
+ while (*format == '0') {\r
+ ++format;\r
+ pad |= PAD_ZERO;\r
+ }\r
+ for ( ; *format >= '0' && *format <= '9'; ++format) {\r
+ width *= 10;\r
+ width += *format - '0';\r
+ }\r
+ if( *format == 's' ) {\r
+ register char *s = (char *)va_arg( args, int );\r
+ pc += prints (out, s?s:"(null)", width, pad);\r
+ continue;\r
+ }\r
+ if( *format == 'd' ) {\r
+ pc += printi (out, va_arg( args, int ), 10, 1, width, pad, 'a');\r
+ continue;\r
+ }\r
+ if( *format == 'x' ) {\r
+ pc += printi (out, va_arg( args, int ), 16, 0, width, pad, 'a');\r
+ continue;\r
+ }\r
+ if( *format == 'X' ) {\r
+ pc += printi (out, va_arg( args, int ), 16, 0, width, pad, 'A');\r
+ continue;\r
+ }\r
+ if( *format == 'u' ) {\r
+ pc += printi (out, va_arg( args, int ), 10, 0, width, pad, 'a');\r
+ continue;\r
+ }\r
+ if( *format == 'c' ) {\r
+ /* char are converted to int then pushed on the stack */\r
+ scr[0] = (char)va_arg( args, int );\r
+ scr[1] = '\0';\r
+ pc += prints (out, scr, width, pad);\r
+ continue;\r
+ }\r
+ }\r
+ else {\r
+ out:\r
+ printchar (out, *format);\r
+ ++pc;\r
+ }\r
+ }\r
+ if (out) **out = '\0';\r
+ va_end( args );\r
+ return pc;\r
+}\r
+\r
+int printk(const char *format, ...)\r
+{\r
+ va_list args;\r
+ \r
+ va_start( args, format );\r
+ return print( 0, format, args );\r
+}\r
+\r
+int sprintf(char *out, const char *format, ...)\r
+{\r
+ va_list args;\r
+ \r
+ va_start( args, format );\r
+ return print( &out, format, args );\r
+}\r
+\r
+#ifdef TEST_PRINTF\r
+int main(void)\r
+{\r
+ char *ptr = "Hello world!";\r
+ char *np = 0;\r
+ int i = 5;\r
+ unsigned int bs = sizeof(int)*8;\r
+ int mi;\r
+ char buf[80];\r
+\r
+ mi = (1 << (bs-1)) + 1;\r
+ printf("%s\n", ptr);\r
+ printf("printf test\n");\r
+ printf("%s is null pointer\n", np);\r
+ printf("%d = 5\n", i);\r
+ printf("%d = - max int\n", mi);\r
+ printf("char %c = 'a'\n", 'a');\r
+ printf("hex %x = ff\n", 0xff);\r
+ printf("hex %02x = 00\n", 0);\r
+ printf("signed %d = unsigned %u = hex %x\n", -3, -3, -3);\r
+ printf("%d %s(s)%", 0, "message");\r
+ printf("\n");\r
+ printf("%d %s(s) with %%\n", 0, "message");\r
+ sprintf(buf, "justif: \"%-10s\"\n", "left"); printf("%s", buf);\r
+ sprintf(buf, "justif: \"%10s\"\n", "right"); printf("%s", buf);\r
+ sprintf(buf, " 3: %04d zero padded\n", 3); printf("%s", buf);\r
+ sprintf(buf, " 3: %-4d left justif.\n", 3); printf("%s", buf);\r
+ sprintf(buf, " 3: %4d right justif.\n", 3); printf("%s", buf);\r
+ sprintf(buf, "-3: %04d zero padded\n", -3); printf("%s", buf);\r
+ sprintf(buf, "-3: %-4d left justif.\n", -3); printf("%s", buf);\r
+ sprintf(buf, "-3: %4d right justif.\n", -3); printf("%s", buf);\r
+\r
+ return 0;\r
+}\r
+\r
+/*\r
+ * if you compile this file with\r
+ * gcc -Wall $(YOUR_C_OPTIONS) -DTEST_PRINTF -c printf.c\r
+ * you will get a normal warning:\r
+ * printf.c:214: warning: spurious trailing `%' in format\r
+ * this line is testing an invalid % at the end of the format string.\r
+ *\r
+ * this should display (on 32bit int machine) :\r
+ *\r
+ * Hello world!\r
+ * printf test\r
+ * (null) is null pointer\r
+ * 5 = 5\r
+ * -2147483647 = - max int\r
+ * char a = 'a'\r
+ * hex ff = ff\r
+ * hex 00 = 00\r
+ * signed -3 = unsigned 4294967293 = hex fffffffd\r
+ * 0 message(s)\r
+ * 0 message(s) with %\r
+ * justif: "left "\r
+ * justif: " right"\r
+ * 3: 0003 zero padded\r
+ * 3: 3 left justif.\r
+ * 3: 3 right justif.\r
+ * -3: -003 zero padded\r
+ * -3: -3 left justif.\r
+ * -3: -3 right justif.\r
+ */\r
+\r
+#endif\r
--- /dev/null
+<!doctype HTML public "-//W3C//DTD HTML 4.0 Frameset//EN">
+<html>
+ <head>
+ <link rel="stylesheet" type="text/css" href="../../../../.docsrc/AVR32_ns.css">
+ </head>
+ <body>
+<p align="left" class="whs2"><a href="../../../AVR32_SERVICES_Readme.html"<font color="red"></font>Back to main page</a></p>
+<h1 align="center" class="whs1">AVR®32 AT32UC3 Series Software Library: Basic Web server and TFTP server example.<br>
+</h1>
+
+<p align="center" class="whs2">Copyright © 2007 Atmel Corporation</p>
+
+<a><h2>Introduction</a></h2>
+ <p>This example implements a basic Web server and a basic TFTP server.
+ It is running on top of the <a href="http://www.sics.se/~adam/lwip"<font color="red"></font>lwIP TCP/IP stack</a> and the AVR32 UC3 <a href="http://freertos.org"<font color="red"></font>freeRTOS.org</a> port.</p>
+ <p>This example thus contains a port of the <a href="http://www.sics.se/~adam/lwip"<font color="red"></font>lwIP TCP/IP stack</a>. This port is using both the AVR32 UC3 <a href="http://freertos.org"<font color="red"></font>freeRTOS.org</a> port and the AVR32 UC3A MACB interface for the Ethernet access.</p>
+
+<p> </p>
+
+<a><h2>lwIP TCP/IP stack</a></h2>
+ <p>lwIP is an implementation of the TCP/IP protocol suite. The focus of the lwIP TCP/IP implementation is to reduce resource usage while still having a full scale TCP.</p>
+ <DT><B><u>lwIP features</u>:</B>
+ <DD><p class="whs3"><li>IP (Internet Protocol) including packet forwarding over multiple network interfaces</p></li>
+ <DD><p class="whs3"><li>ICMP (Internet Control Message Protocol) for network maintenance and debugging</p></li>
+ <DD><p class="whs3"><li>UDP (User Datagram Protocol) including experimental UDP-lite extensions</p></li>
+ <DD><p class="whs3"><li>TCP (Transmission Control Protocol) with congestion control, RTT estimation and fast recovery/fast retransmit</p></li>
+ <DD><p class="whs3"><li>Specialized raw API for enhanced performance</p></li>
+ <DD><p class="whs3"><li>Optional Berkeley-alike socket API</p></li>
+ <DD><p class="whs3"><li>DHCP (Dynamic Host Configuration Protocol)</p></li>
+ <DD><p class="whs3"><li>PPP (Point-to-Point Protocol)</p></li>
+ <DD><p class="whs3"><li>ARP (Address Resolution Protocol) for Ethernet</p></li>
+
+<p> </p>
+
+<a><h2>The Basic Web server</a></h2>
+ <p>Implements a simplistic WEB server.</p>
+ <B><u>Demo description</u>:</B> Every time a connection is made and data is received, a dynamic page that shows the current FreeRTOS.org kernel statistics is generated and returned. The connection is then closed.</p>
+ <B><u>Note</u>:</B> The WEB server is reachable at the IP address 192.168.0.2.
+
+<p> </p>
+
+<a><h2>The Basic TFTP server</a></h2>
+ <p>Implements a simplistic TFTP server.</p>
+ <DT><B><u>Demo description</u>:</B>
+ <DD><p class="whs3"><li>To put a file onto the TFTP server (Supported file size < 2048 bytes), on a PC command line type <i><b>tftp 192.168.0.2 PUT "a_file"</i></b>: this will copy <i>a_file</i> from your hard drive to a RAM buffer of the demo.</p></li>
+ <DD><p class="whs3"><li>To get a file from the TFTP server, on a PC command line type <i><b>tftp 192.168.0.2 GET "a_file"</i></b>: this will copy <i>a_file</i> from the RAM buffer of the application to the PC's hard drive.</p></li>
+ <B><u>Note 1</u>:</B> only one file at a time is supported on this TFTP server. This is because the TFTP server being a simplistic example, it does not use a file system to store files but a predefined RAM area of 2048 Bytes.
+ <p><B><u>Note 2</u>:</B> The TFTP server is reachable at the IP address 192.168.0.2.</p>
+
+<p> </p>
+
+<a><h2>Device Info</a></h2>
+ All AVR32 UC3A devices with a MACB module can be used. This example has been tested with the following setup(s):
+ <DD><p class="whs3"><li type="disc">AT32UC3A0512 on the EVK1100 evaluation kit.</li></p>
+
+<p> </p>
+
+<a><h2>Contact Info</a></h2>
+For more info about Atmel AVR32 visit <a href="http://www.atmel.com/products/AVR32/">Atmel AVR32</a> <br>
+ <a href="http://www.atmel.com/dyn/products/app_notes.asp?family_id=682">AVR32 Application Notes</a><br>
+ Support mail: <a href="mailto:avr32@atmel.com">avr32@atmel.com</a>
+
+<p> </p>
+
+<a><h2>License</a></h2>
+
+Copyright (c) 2007, Atmel Corporation All rights reserved.
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+<ol>
+<li>Redistributions of source code must retain the above copyright notice,
+this list of conditions and the following disclaimer.
+<li>Redistributions in binary form must reproduce the above copyright notice,
+this list of conditions and the following disclaimer in the documentation
+and/or other materials provided with the distribution.
+<li>The name of ATMEL may not be used to endorse or promote products derived
+from this software without specific prior written permission.
+</ol>
+<p> </p>
+THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
+WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
+SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+
+<p> </p>
+
+
+<hr align="center" width="50%" class="whs4">
+
+ <p class=legalfooter>AVR is a registered trademark of
+ Atmel Corporation.</p>
+
+ </body>
+</html>
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