--- /dev/null
+/*\r
+ FreeRTOS.org V4.3.0 - Copyright (C) 2003-2007 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS.org distribution.\r
+\r
+ FreeRTOS.org is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS.org is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS.org; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS.org, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section\r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license\r
+ and contact details. Please ensure to read the configuration and relevant\r
+ port sections of the online documentation.\r
+\r
+ Also see http://www.SafeRTOS.com for an IEC 61508 compliant version along\r
+ with commercial development and support options.\r
+ ***************************************************************************\r
+*/\r
+\r
+#ifndef FREERTOS_CONFIG_H\r
+#define FREERTOS_CONFIG_H\r
+\r
+/*-----------------------------------------------------------\r
+ * Application specific definitions.\r
+ *\r
+ * These definitions should be adjusted for your particular hardware and\r
+ * application requirements.\r
+ *\r
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE\r
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.\r
+ *----------------------------------------------------------*/\r
+\r
+#define configUSE_PREEMPTION 1\r
+#define configUSE_IDLE_HOOK 0\r
+#define configUSE_TICK_HOOK 0\r
+#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 50000000 )\r
+#define configTICK_RATE_HZ ( ( portTickType ) 1000 )\r
+#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 70 )\r
+#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 12000 ) )\r
+#define configMAX_TASK_NAME_LEN ( 12 )\r
+#define configUSE_TRACE_FACILITY 1\r
+#define configUSE_16_BIT_TICKS 0\r
+#define configIDLE_SHOULD_YIELD 0\r
+#define configUSE_CO_ROUTINES 0\r
+\r
+#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 5 )\r
+#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )\r
+\r
+/* Set the following definitions to 1 to include the API function, or zero\r
+to exclude the API function. */\r
+\r
+#define INCLUDE_vTaskPrioritySet 1\r
+#define INCLUDE_uxTaskPriorityGet 0\r
+#define INCLUDE_vTaskDelete 1\r
+#define INCLUDE_vTaskCleanUpResources 0\r
+#define INCLUDE_vTaskSuspend 1\r
+#define INCLUDE_vTaskDelayUntil 1\r
+#define INCLUDE_vTaskDelay 1\r
+\r
+\r
+#define configKERNEL_INTERRUPT_PRIORITY 255\r
+\r
+\r
+#endif /* FREERTOS_CONFIG_H */\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// LM3Sxxx.h - Header file for Luminary Micro LM3Sxxx microcontrollers.\r
+//\r
+// Copyright (c) 2006-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __LM3SXXX_H__\r
+#define __LM3SXXX_H__\r
+\r
+#include "hw_adc.h"\r
+#include "hw_comp.h"\r
+#include "hw_flash.h"\r
+#include "hw_gpio.h"\r
+#include "hw_i2c.h"\r
+#include "hw_ints.h"\r
+#include "hw_memmap.h"\r
+#include "hw_nvic.h"\r
+#include "hw_pwm.h"\r
+#include "hw_qei.h"\r
+#include "hw_ssi.h"\r
+#include "hw_sysctl.h"\r
+#include "hw_timer.h"\r
+#include "hw_types.h"\r
+#include "hw_uart.h"\r
+#include "hw_watchdog.h"\r
+#include "adc.h"\r
+#include "comp.h"\r
+#include "cpu.h"\r
+#include "debug.h"\r
+#include "flash.h"\r
+#include "gpio.h"\r
+#include "i2c.h"\r
+#include "interrupt.h"\r
+#include "pwm.h"\r
+#include "qei.h"\r
+#include "ssi.h"\r
+#include "sysctl.h"\r
+#include "systick.h"\r
+#include "timer.h"\r
+#include "uart.h"\r
+#include "watchdog.h"\r
+\r
+#endif // __LM3SXXX_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// LM3Sxxxx.h - Header file for Luminary Micro LM3Sxxxx microcontrollers.\r
+//\r
+// Copyright (c) 2006-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __LM3SXXXX_H__\r
+#define __LM3SXXXX_H__\r
+\r
+#include "hw_adc.h"\r
+#include "hw_can.h"\r
+#include "hw_comp.h"\r
+#include "hw_ethernet.h"\r
+#include "hw_flash.h"\r
+#include "hw_gpio.h"\r
+#include "hw_hibernate.h"\r
+#include "hw_i2c.h"\r
+#include "hw_ints.h"\r
+#include "hw_memmap.h"\r
+#include "hw_nvic.h"\r
+#include "hw_pwm.h"\r
+#include "hw_qei.h"\r
+#include "hw_ssi.h"\r
+#include "hw_sysctl.h"\r
+#include "hw_timer.h"\r
+#include "hw_types.h"\r
+#include "hw_uart.h"\r
+#include "hw_watchdog.h"\r
+#include "adc.h"\r
+#include "can.h"\r
+#include "comp.h"\r
+#include "cpu.h"\r
+#include "debug.h"\r
+#include "ethernet.h"\r
+#include "flash.h"\r
+#include "gpio.h"\r
+#include "hibernate.h"\r
+#include "i2c.h"\r
+#include "interrupt.h"\r
+#include "pwm.h"\r
+#include "qei.h"\r
+#include "ssi.h"\r
+#include "sysctl.h"\r
+#include "systick.h"\r
+#include "timer.h"\r
+#include "uart.h"\r
+#include "watchdog.h"\r
+\r
+#endif // __LM3SXXXX_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// flash.h - Prototypes for the flash driver.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __FLASH_H__\r
+#define __FLASH_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to FlashProtectSet(), and returned by\r
+// FlashProtectGet().\r
+//\r
+//*****************************************************************************\r
+typedef enum\r
+{\r
+ FlashReadWrite, // Flash can be read and written\r
+ FlashReadOnly, // Flash can only be read\r
+ FlashExecuteOnly // Flash can only be executed\r
+}\r
+tFlashProtection;\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+extern unsigned long FlashUsecGet(void);\r
+extern void FlashUsecSet(unsigned long ulClocks);\r
+extern long FlashErase(unsigned long ulAddress);\r
+extern long FlashProgram(unsigned long *pulData, unsigned long ulAddress,\r
+ unsigned long ulCount);\r
+extern tFlashProtection FlashProtectGet(unsigned long ulAddress);\r
+extern long FlashProtectSet(unsigned long ulAddress,\r
+ tFlashProtection eProtect);\r
+extern long FlashProtectSave(void);\r
+extern long FlashUserGet(unsigned long *pulUser0, unsigned long *pulUser1);\r
+extern long FlashUserSet(unsigned long ulUser0, unsigned long ulUser1);\r
+extern long FlashUserSave(void);\r
+extern void FlashIntRegister(void (*pfnHandler)(void));\r
+extern void FlashIntUnregister(void);\r
+extern void FlashIntEnable(unsigned long ulIntFlags);\r
+extern void FlashIntDisable(unsigned long ulIntFlags);\r
+extern unsigned long FlashIntGetStatus(tBoolean bMasked);\r
+extern void FlashIntClear(unsigned long ulIntFlags);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __FLASH_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// timer.h - Prototypes for the timer module\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __TIMER_H__\r
+#define __TIMER_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to TimerConfigure as the ulConfig parameter.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_CFG_32_BIT_OS 0x00000001 // 32-bit one-shot timer\r
+#define TIMER_CFG_32_BIT_PER 0x00000002 // 32-bit periodic timer\r
+#define TIMER_CFG_32_RTC 0x01000000 // 32-bit RTC timer\r
+#define TIMER_CFG_16_BIT_PAIR 0x04000000 // Two 16-bit timers\r
+#define TIMER_CFG_A_ONE_SHOT 0x00000001 // Timer A one-shot timer\r
+#define TIMER_CFG_A_PERIODIC 0x00000002 // Timer A periodic timer\r
+#define TIMER_CFG_A_CAP_COUNT 0x00000003 // Timer A event counter\r
+#define TIMER_CFG_A_CAP_TIME 0x00000007 // Timer A event timer\r
+#define TIMER_CFG_A_PWM 0x0000000A // Timer A PWM output\r
+#define TIMER_CFG_B_ONE_SHOT 0x00000100 // Timer B one-shot timer\r
+#define TIMER_CFG_B_PERIODIC 0x00000200 // Timer B periodic timer\r
+#define TIMER_CFG_B_CAP_COUNT 0x00000300 // Timer B event counter\r
+#define TIMER_CFG_B_CAP_TIME 0x00000700 // Timer B event timer\r
+#define TIMER_CFG_B_PWM 0x00000A00 // Timer B PWM output\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to TimerIntEnable, TimerIntDisable, and\r
+// TimerIntClear as the ulIntFlags parameter, and returned from TimerIntStatus.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_CAPB_EVENT 0x00000400 // CaptureB event interrupt\r
+#define TIMER_CAPB_MATCH 0x00000200 // CaptureB match interrupt\r
+#define TIMER_TIMB_TIMEOUT 0x00000100 // TimerB time out interrupt\r
+#define TIMER_RTC_MATCH 0x00000008 // RTC interrupt mask\r
+#define TIMER_CAPA_EVENT 0x00000004 // CaptureA event interrupt\r
+#define TIMER_CAPA_MATCH 0x00000002 // CaptureA match interrupt\r
+#define TIMER_TIMA_TIMEOUT 0x00000001 // TimerA time out interrupt\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to TimerControlEvent as the ulEvent parameter.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_EVENT_POS_EDGE 0x00000000 // Count positive edges\r
+#define TIMER_EVENT_NEG_EDGE 0x00000404 // Count negative edges\r
+#define TIMER_EVENT_BOTH_EDGES 0x00000C0C // Count both edges\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to most of the timer APIs as the ulTimer\r
+// parameter.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_A 0x000000ff // Timer A\r
+#define TIMER_B 0x0000ff00 // Timer B\r
+#define TIMER_BOTH 0x0000ffff // Timer Both\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+extern void TimerEnable(unsigned long ulBase, unsigned long ulTimer);\r
+extern void TimerDisable(unsigned long ulBase, unsigned long ulTimer);\r
+extern void TimerConfigure(unsigned long ulBase, unsigned long ulConfig);\r
+extern void TimerControlLevel(unsigned long ulBase, unsigned long ulTimer,\r
+ tBoolean bInvert);\r
+extern void TimerControlTrigger(unsigned long ulBase, unsigned long ulTimer,\r
+ tBoolean bEnable);\r
+extern void TimerControlEvent(unsigned long ulBase, unsigned long ulTimer,\r
+ unsigned long ulEvent);\r
+extern void TimerControlStall(unsigned long ulBase, unsigned long ulTimer,\r
+ tBoolean bStall);\r
+extern void TimerRTCEnable(unsigned long ulBase);\r
+extern void TimerRTCDisable(unsigned long ulBase);\r
+extern void TimerPrescaleSet(unsigned long ulBase, unsigned long ulTimer,\r
+ unsigned long ulValue);\r
+extern unsigned long TimerPrescaleGet(unsigned long ulBase,\r
+ unsigned long ulTimer);\r
+extern void TimerPrescaleMatchSet(unsigned long ulBase, unsigned long ulTimer,\r
+ unsigned long ulValue);\r
+extern unsigned long TimerPrescaleMatchGet(unsigned long ulBase,\r
+ unsigned long ulTimer);\r
+extern void TimerLoadSet(unsigned long ulBase, unsigned long ulTimer,\r
+ unsigned long ulValue);\r
+extern unsigned long TimerLoadGet(unsigned long ulBase, unsigned long ulTimer);\r
+extern unsigned long TimerValueGet(unsigned long ulBase,\r
+ unsigned long ulTimer);\r
+extern void TimerMatchSet(unsigned long ulBase, unsigned long ulTimer,\r
+ unsigned long ulValue);\r
+extern unsigned long TimerMatchGet(unsigned long ulBase,\r
+ unsigned long ulTimer);\r
+extern void TimerIntRegister(unsigned long ulBase, unsigned long ulTimer,\r
+ void (*pfnHandler)(void));\r
+extern void TimerIntUnregister(unsigned long ulBase, unsigned long ulTimer);\r
+extern void TimerIntEnable(unsigned long ulBase, unsigned long ulIntFlags);\r
+extern void TimerIntDisable(unsigned long ulBase, unsigned long ulIntFlags);\r
+extern unsigned long TimerIntStatus(unsigned long ulBase, tBoolean bMasked);\r
+extern void TimerIntClear(unsigned long ulBase, unsigned long ulIntFlags);\r
+extern void TimerQuiesce(unsigned long ulBase);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __TIMER_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// adc.h - ADC headers for using the ADC driver functions.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __ADC_H__\r
+#define __ADC_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to ADCSequenceConfigure as the ulTrigger\r
+// parameter.\r
+//\r
+//*****************************************************************************\r
+#define ADC_TRIGGER_PROCESSOR 0x00000000 // Processor event\r
+#define ADC_TRIGGER_COMP0 0x00000001 // Analog comparator 0 event\r
+#define ADC_TRIGGER_COMP1 0x00000002 // Analog comparator 1 event\r
+#define ADC_TRIGGER_COMP2 0x00000003 // Analog comparator 2 event\r
+#define ADC_TRIGGER_EXTERNAL 0x00000004 // External event\r
+#define ADC_TRIGGER_TIMER 0x00000005 // Timer event\r
+#define ADC_TRIGGER_PWM0 0x00000006 // PWM0 event\r
+#define ADC_TRIGGER_PWM1 0x00000007 // PWM1 event\r
+#define ADC_TRIGGER_PWM2 0x00000008 // PWM2 event\r
+#define ADC_TRIGGER_ALWAYS 0x0000000F // Always event\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to ADCSequenceStepConfigure as the ulConfig\r
+// parameter.\r
+//\r
+//*****************************************************************************\r
+#define ADC_CTL_TS 0x00000080 // Temperature sensor select\r
+#define ADC_CTL_IE 0x00000040 // Interrupt enable\r
+#define ADC_CTL_END 0x00000020 // Sequence end select\r
+#define ADC_CTL_D 0x00000010 // Differential select\r
+#define ADC_CTL_CH0 0x00000000 // Input channel 0\r
+#define ADC_CTL_CH1 0x00000001 // Input channel 1\r
+#define ADC_CTL_CH2 0x00000002 // Input channel 2\r
+#define ADC_CTL_CH3 0x00000003 // Input channel 3\r
+#define ADC_CTL_CH4 0x00000004 // Input channel 4\r
+#define ADC_CTL_CH5 0x00000005 // Input channel 5\r
+#define ADC_CTL_CH6 0x00000006 // Input channel 6\r
+#define ADC_CTL_CH7 0x00000007 // Input channel 7\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+extern void ADCIntRegister(unsigned long ulBase, unsigned long ulSequenceNum,\r
+ void (*pfnHandler)(void));\r
+extern void ADCIntUnregister(unsigned long ulBase,\r
+ unsigned long ulSequenceNum);\r
+extern void ADCIntDisable(unsigned long ulBase, unsigned long ulSequenceNum);\r
+extern void ADCIntEnable(unsigned long ulBase, unsigned long ulSequenceNum);\r
+extern unsigned long ADCIntStatus(unsigned long ulBase,\r
+ unsigned long ulSequenceNum,\r
+ tBoolean bMasked);\r
+extern void ADCIntClear(unsigned long ulBase, unsigned long ulSequenceNum);\r
+extern void ADCSequenceEnable(unsigned long ulBase,\r
+ unsigned long ulSequenceNum);\r
+extern void ADCSequenceDisable(unsigned long ulBase,\r
+ unsigned long ulSequenceNum);\r
+extern void ADCSequenceConfigure(unsigned long ulBase,\r
+ unsigned long ulSequenceNum,\r
+ unsigned long ulTrigger,\r
+ unsigned long ulPriority);\r
+extern void ADCSequenceStepConfigure(unsigned long ulBase,\r
+ unsigned long ulSequenceNum,\r
+ unsigned long ulStep,\r
+ unsigned long ulConfig);\r
+extern long ADCSequenceOverflow(unsigned long ulBase,\r
+ unsigned long ulSequenceNum);\r
+extern void ADCSequenceOverflowClear(unsigned long ulBase,\r
+ unsigned long ulSequenceNum);\r
+extern long ADCSequenceUnderflow(unsigned long ulBase,\r
+ unsigned long ulSequenceNum);\r
+extern void ADCSequenceUnderflowClear(unsigned long ulBase,\r
+ unsigned long ulSequenceNum);\r
+extern long ADCSequenceDataGet(unsigned long ulBase,\r
+ unsigned long ulSequenceNum,\r
+ unsigned long *pulBuffer);\r
+extern void ADCProcessorTrigger(unsigned long ulBase,\r
+ unsigned long ulSequenceNum);\r
+extern void ADCSoftwareOversampleConfigure(unsigned long ulBase,\r
+ unsigned long ulSequenceNum,\r
+ unsigned long ulFactor);\r
+extern void ADCSoftwareOversampleStepConfigure(unsigned long ulBase,\r
+ unsigned long ulSequenceNum,\r
+ unsigned long ulStep,\r
+ unsigned long ulConfig);\r
+extern void ADCSoftwareOversampleDataGet(unsigned long ulBase,\r
+ unsigned long ulSequenceNum,\r
+ unsigned long *pulBuffer,\r
+ unsigned long ulCount);\r
+extern void ADCHardwareOversampleConfigure(unsigned long ulBase,\r
+ unsigned long ulFactor);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __ADC_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// can.h - Defines and Macros for the CAN controller.\r
+//\r
+// Copyright (c) 2006-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __CAN_H__\r
+#define __CAN_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! \addtogroup can_api\r
+//! @{\r
+//\r
+//*****************************************************************************\r
+\r
+//*****************************************************************************\r
+//\r
+// Miscellaneous defines for Message ID Types\r
+//\r
+//*****************************************************************************\r
+\r
+//*****************************************************************************\r
+//\r
+//! These are the flags used by the tCANMsgObject variable when calling the\r
+//! the CANMessageSet() and CANMessageGet() APIs.\r
+//\r
+//*****************************************************************************\r
+typedef enum\r
+{\r
+ //\r
+ //! This indicates that transmit interrupts should be enabled, or are\r
+ //! enabled.\r
+ //\r
+ MSG_OBJ_TX_INT_ENABLE = 0x00000001,\r
+\r
+ //\r
+ //! This indicates that receive interrupts should be enabled or are\r
+ //! enabled.\r
+ //\r
+ MSG_OBJ_RX_INT_ENABLE = 0x00000002,\r
+\r
+ //\r
+ //! This indicates that a message object will use or is using an extended\r
+ //! identifier.\r
+ //\r
+ MSG_OBJ_EXTENDED_ID = 0x00000004,\r
+\r
+ //\r
+ //! This indicates that a message object will use or is using filtering\r
+ //! based on the object's message Identifier.\r
+ //\r
+ MSG_OBJ_USE_ID_FILTER = 0x00000008,\r
+\r
+ //\r
+ //! This indicates that new data was available in the message object.\r
+ //\r
+ MSG_OBJ_NEW_DATA = 0x00000080,\r
+\r
+ //\r
+ //! This indicates that data was lost since this message object was last\r
+ //! read.\r
+ //\r
+ MSG_OBJ_DATA_LOST = 0x00000100,\r
+\r
+ //\r
+ //! This indicates that a message object will use or is using filtering\r
+ //! based on the direction of the transfer. If the direction filtering is\r
+ //! used then ID filtering must also be enabled.\r
+ //\r
+ MSG_OBJ_USE_DIR_FILTER = (0x00000010 | MSG_OBJ_USE_ID_FILTER),\r
+\r
+ //\r
+ //! This indicates that a message object will use or is using message\r
+ //! identifier filtering based of the the extended identifier.\r
+ //! If the extended identifier filtering is used then ID filtering must\r
+ //! also be enabled.\r
+ //\r
+ MSG_OBJ_USE_EXT_FILTER = (0x00000020 | MSG_OBJ_USE_ID_FILTER),\r
+\r
+ //\r
+ //! This indicates that a message object is a remote frame.\r
+ //\r
+ MSG_OBJ_REMOTE_FRAME = 0x00000040,\r
+\r
+ //\r
+ //! This indicates that a message object has no flags set.\r
+ //\r
+ MSG_OBJ_NO_FLAGS = 0x00000000\r
+}\r
+tCANObjFlags;\r
+\r
+//*****************************************************************************\r
+//\r
+//! This define is used with the #tCANObjFlags enumerated values to allow\r
+//! checking only status flags and not configuration flags.\r
+//\r
+//*****************************************************************************\r
+#define MSG_OBJ_STATUS_MASK (MSG_OBJ_NEW_DATA | MSG_OBJ_DATA_LOST)\r
+\r
+//*****************************************************************************\r
+//\r
+//! This structure used for encapsulating all the items associated with a CAN\r
+//! message object in the CAN controller.\r
+//\r
+//*****************************************************************************\r
+typedef struct\r
+{\r
+ //\r
+ //! The CAN message identifier used for 11 or 29 bit identifiers.\r
+ //\r
+ unsigned long ulMsgID;\r
+\r
+ //\r
+ //! The message identifier mask used when identifier filtering is enabled.\r
+ //\r
+ unsigned long ulMsgIDMask;\r
+\r
+ //\r
+ //! This value holds various status flags and settings specified by\r
+ //! tCANObjFlags.\r
+ //\r
+ unsigned long ulFlags;\r
+\r
+ //\r
+ //! This value is the number of bytes of data in the message object.\r
+ //\r
+ unsigned long ulMsgLen;\r
+\r
+ //\r
+ //! This is a pointer to the message object's data.\r
+ //\r
+ unsigned char *pucMsgData;\r
+}\r
+tCANMsgObject;\r
+\r
+//*****************************************************************************\r
+//\r
+//! This structure is used for encapsulating the values associated with setting\r
+//! up the bit timing for a CAN controller. The structure is used when calling\r
+//! the CANGetBitTiming and CANSetBitTiming functions.\r
+//\r
+//*****************************************************************************\r
+typedef struct\r
+{\r
+ //\r
+ //! This value holds the sum of the Synchronization, Propagation, and Phase\r
+ //! Buffer 1 segments, measured in time quanta. The valid values for this\r
+ //! setting range from 2 to 16.\r
+ //\r
+ unsigned int uSyncPropPhase1Seg;\r
+\r
+ //\r
+ //! This value holds the Phase Buffer 2 segment in time quanta. The valid\r
+ //! values for this setting range from 1 to 8.\r
+ //\r
+ unsigned int uPhase2Seg;\r
+\r
+ //\r
+ //! This value holds the Resynchronization Jump Width in time quanta. The\r
+ //! valid values for this setting range from 1 to 4.\r
+ //\r
+ unsigned int uSJW;\r
+\r
+ //\r
+ //! This value holds the CAN_CLK divider used to determine time quanta.\r
+ //! The valid values for this setting range from 1 to 1023.\r
+ //\r
+ unsigned int uQuantumPrescaler;\r
+\r
+}\r
+tCANBitClkParms;\r
+\r
+//*****************************************************************************\r
+//\r
+//! This data type is used to identify the interrupt status register. This is\r
+//! used when calling the a CANIntStatus() function.\r
+//\r
+//*****************************************************************************\r
+typedef enum\r
+{\r
+ //\r
+ //! Read the CAN interrupt status information.\r
+ //\r
+ CAN_INT_STS_CAUSE,\r
+\r
+ //\r
+ //! Read a message object's interrupt status.\r
+ //\r
+ CAN_INT_STS_OBJECT\r
+}\r
+tCANIntStsReg;\r
+\r
+//*****************************************************************************\r
+//\r
+//! This data type is used to identify which of the several status registers\r
+//! to read when calling the CANStatusGet() function.\r
+//\r
+//*****************************************************************************\r
+typedef enum\r
+{\r
+ //\r
+ //! Read the full CAN controller status.\r
+ //\r
+ CAN_STS_CONTROL,\r
+\r
+ //\r
+ //! Read the full 32 bit mask of message objects with a transmit request\r
+ //! set.\r
+ //\r
+ CAN_STS_TXREQUEST,\r
+\r
+ //\r
+ //! Read the full 32 bit mask of message objects with a new data available.\r
+ //\r
+ CAN_STS_NEWDAT,\r
+\r
+ //\r
+ //! Read the full 32 bit mask of message objects that are enabled.\r
+ //\r
+ CAN_STS_MSGVAL\r
+}\r
+tCANStsReg;\r
+\r
+//*****************************************************************************\r
+//\r
+//! These definitions are used to specify interrupt sources to CANIntEnable()\r
+//! and CANIntDisable().\r
+//\r
+//*****************************************************************************\r
+typedef enum\r
+{\r
+ //\r
+ //! This flag is used to allow a CAN controller to generate error\r
+ //! interrupts.\r
+ //\r
+ CAN_INT_ERROR = 0x00000008,\r
+\r
+ //\r
+ //! This flag is used to allow a CAN controller to generate status\r
+ //! interrupts.\r
+ //\r
+ CAN_INT_STATUS = 0x00000004,\r
+\r
+ //\r
+ //! This flag is used to allow a CAN controller to generate any CAN\r
+ //! interrupts. If this is not set then no interrupts will be generated by\r
+ //! the CAN controller.\r
+ //\r
+ CAN_INT_MASTER = 0x00000002\r
+}\r
+tCANIntFlags;\r
+\r
+//*****************************************************************************\r
+//\r
+//! This definition is used to determine the type of message object that will\r
+//! be set up via a call to the CANMessageSet() API.\r
+//\r
+//*****************************************************************************\r
+typedef enum\r
+{\r
+ //\r
+ //! Transmit message object.\r
+ //\r
+ MSG_OBJ_TYPE_TX,\r
+\r
+ //\r
+ //! Transmit remote request message object\r
+ //\r
+ MSG_OBJ_TYPE_TX_REMOTE,\r
+\r
+ //\r
+ //! Receive message object.\r
+ //\r
+ MSG_OBJ_TYPE_RX,\r
+\r
+ //\r
+ //! Receive remote request message object.\r
+ //\r
+ MSG_OBJ_TYPE_RX_REMOTE,\r
+\r
+ //\r
+ //! Remote frame receive remote, with auto-transmit message object.\r
+ //\r
+ MSG_OBJ_TYPE_RXTX_REMOTE\r
+}\r
+tMsgObjType;\r
+\r
+//*****************************************************************************\r
+//\r
+//! The following enumeration contains all error or status indicators that\r
+//! can be returned when calling the CANStatusGet() API.\r
+//\r
+//*****************************************************************************\r
+typedef enum\r
+{\r
+ //\r
+ //! CAN controller has entered a Bus Off state.\r
+ //\r
+ CAN_STATUS_BUS_OFF = 0x00000080,\r
+\r
+ //\r
+ //! CAN controller error level has reached warning level.\r
+ //\r
+ CAN_STATUS_EWARN = 0x00000040,\r
+\r
+ //\r
+ //! CAN controller error level has reached error passive level.\r
+ //\r
+ CAN_STATUS_EPASS = 0x00000020,\r
+\r
+ //\r
+ //! A message was received successfully since the last read of this status.\r
+ //\r
+ CAN_STATUS_RXOK = 0x00000010,\r
+\r
+ //\r
+ //! A message was transmitted successfully since the last read of this\r
+ //! status.\r
+ //\r
+ CAN_STATUS_TXOK = 0x00000008,\r
+\r
+ //\r
+ //! This is the mask for the last error code field.\r
+ //\r
+ CAN_STATUS_LEC_MSK = 0x00000007,\r
+\r
+ //\r
+ //! There was no error.\r
+ //\r
+ CAN_STATUS_LEC_NONE = 0x00000000,\r
+\r
+ //\r
+ //! A bit stuffing error has occurred.\r
+ //\r
+ CAN_STATUS_LEC_STUFF = 0x00000001,\r
+\r
+ //\r
+ //! A formatting error has occurred.\r
+ //\r
+ CAN_STATUS_LEC_FORM = 0x00000002,\r
+\r
+ //\r
+ //! An acknowledge error has occurred.\r
+ //\r
+ CAN_STATUS_LEC_ACK = 0x00000003,\r
+\r
+ //\r
+ //! The bus remained a bit level of 1 for longer than is allowed.\r
+ //\r
+ CAN_STATUS_LEC_BIT1 = 0x00000004,\r
+\r
+ //\r
+ //! The bus remained a bit level of 0 for longer than is allowed.\r
+ //\r
+ CAN_STATUS_LEC_BIT0 = 0x00000005,\r
+\r
+ //\r
+ //! A CRC error has occurred.\r
+ //\r
+ CAN_STATUS_LEC_CRC = 0x00000006,\r
+\r
+ //\r
+ //! This is the mask for the CAN Last Error Code (LEC).\r
+ //\r
+ CAN_STATUS_LEC_MASK = 0x00000007\r
+}\r
+tCANStatusCtrl;\r
+\r
+//*****************************************************************************\r
+//\r
+// API Function prototypes\r
+//\r
+//*****************************************************************************\r
+extern void CANInit(unsigned long ulBase);\r
+extern void CANEnable(unsigned long ulBase);\r
+extern void CANDisable(unsigned long ulBase);\r
+extern void CANSetBitTiming(unsigned long ulBase, tCANBitClkParms *pClkParms);\r
+extern void CANGetBitTiming(unsigned long ulBase, tCANBitClkParms *pClkParms);\r
+extern unsigned long CANReadReg(unsigned long ulRegAddress);\r
+extern void CANWriteReg(unsigned long ulRegAddress, unsigned long ulRegValue);\r
+extern void CANMessageSet(unsigned long ulBase, unsigned long ulObjID,\r
+ tCANMsgObject *pMsgObject, tMsgObjType eMsgType);\r
+extern void CANMessageGet(unsigned long ulBase, unsigned long ulObjID,\r
+ tCANMsgObject *pMsgObject, tBoolean bClrPendingInt);\r
+extern unsigned long CANStatusGet(unsigned long ulBase, tCANStsReg eStatusReg);\r
+extern void CANMessageClear(unsigned long ulBase, unsigned long ulObjID);\r
+extern void CANIntRegister(unsigned long ulBase, void (*pfnHandler)(void));\r
+extern void CANIntEnable(unsigned long ulBase, unsigned long ulIntFlags);\r
+extern void CANIntDisable(unsigned long ulBase, unsigned long ulIntFlags);\r
+extern void CANIntClear(unsigned long ulBase, unsigned long ulIntClr);\r
+extern unsigned long CANIntStatus(unsigned long ulBase,\r
+ tCANIntStsReg eIntStsReg);\r
+extern tBoolean CANRetryGet(unsigned long ulBase);\r
+extern void CANRetrySet(unsigned long ulBase, tBoolean bAutoRetry);\r
+extern tBoolean CANErrCntrGet(unsigned long ulBase, unsigned long *pulRxCount,\r
+ unsigned long *pulTxCount);\r
+extern long CANGetIntNumber(unsigned long ulBase);\r
+extern void CANReadDataReg(unsigned char *pucData, unsigned long *pulRegister,\r
+ int iSize);\r
+extern void CANWriteDataReg(unsigned char *pucData, unsigned long *pulRegister,\r
+ int iSize);\r
+\r
+//*****************************************************************************\r
+//\r
+// Close the Doxygen group.\r
+//! @}\r
+//\r
+//*****************************************************************************\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __CAN_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// comp.h - Prototypes for the analog comparator driver.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __COMP_H__\r
+#define __COMP_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to ComparatorConfigure() as the ulConfig\r
+// parameter. For each group (i.e. COMP_TRIG_xxx, COMP_INT_xxx, etc.), one of\r
+// the values may be selected and ORed together will values from the other\r
+// groups.\r
+//\r
+//*****************************************************************************\r
+#define COMP_TRIG_NONE 0x00000000 // No ADC trigger\r
+#define COMP_TRIG_HIGH 0x00000880 // Trigger when high\r
+#define COMP_TRIG_LOW 0x00000800 // Trigger when low\r
+#define COMP_TRIG_FALL 0x00000820 // Trigger on falling edge\r
+#define COMP_TRIG_RISE 0x00000840 // Trigger on rising edge\r
+#define COMP_TRIG_BOTH 0x00000860 // Trigger on both edges\r
+#define COMP_INT_HIGH 0x00000010 // Interrupt when high\r
+#define COMP_INT_LOW 0x00000000 // Interrupt when low\r
+#define COMP_INT_FALL 0x00000004 // Interrupt on falling edge\r
+#define COMP_INT_RISE 0x00000008 // Interrupt on rising edge\r
+#define COMP_INT_BOTH 0x0000000C // Interrupt on both edges\r
+#define COMP_ASRCP_PIN 0x00000000 // Dedicated Comp+ pin\r
+#define COMP_ASRCP_PIN0 0x00000200 // Comp0+ pin\r
+#define COMP_ASRCP_REF 0x00000400 // Internal voltage reference\r
+#ifndef DEPRECATED\r
+#define COMP_OUTPUT_NONE 0x00000000 // No comparator output\r
+#endif\r
+#define COMP_OUTPUT_NORMAL 0x00000000 // Comparator output normal\r
+#define COMP_OUTPUT_INVERT 0x00000002 // Comparator output inverted\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to ComparatorSetRef() as the ulRef parameter.\r
+//\r
+//*****************************************************************************\r
+#define COMP_REF_OFF 0x00000000 // Turn off the internal reference\r
+#define COMP_REF_0V 0x00000300 // Internal reference of 0V\r
+#define COMP_REF_0_1375V 0x00000301 // Internal reference of 0.1375V\r
+#define COMP_REF_0_275V 0x00000302 // Internal reference of 0.275V\r
+#define COMP_REF_0_4125V 0x00000303 // Internal reference of 0.4125V\r
+#define COMP_REF_0_55V 0x00000304 // Internal reference of 0.55V\r
+#define COMP_REF_0_6875V 0x00000305 // Internal reference of 0.6875V\r
+#define COMP_REF_0_825V 0x00000306 // Internal reference of 0.825V\r
+#define COMP_REF_0_928125V 0x00000201 // Internal reference of 0.928125V\r
+#define COMP_REF_0_9625V 0x00000307 // Internal reference of 0.9625V\r
+#define COMP_REF_1_03125V 0x00000202 // Internal reference of 1.03125V\r
+#define COMP_REF_1_134375V 0x00000203 // Internal reference of 1.134375V\r
+#define COMP_REF_1_1V 0x00000308 // Internal reference of 1.1V\r
+#define COMP_REF_1_2375V 0x00000309 // Internal reference of 1.2375V\r
+#define COMP_REF_1_340625V 0x00000205 // Internal reference of 1.340625V\r
+#define COMP_REF_1_375V 0x0000030A // Internal reference of 1.375V\r
+#define COMP_REF_1_44375V 0x00000206 // Internal reference of 1.44375V\r
+#define COMP_REF_1_5125V 0x0000030B // Internal reference of 1.5125V\r
+#define COMP_REF_1_546875V 0x00000207 // Internal reference of 1.546875V\r
+#define COMP_REF_1_65V 0x0000030C // Internal reference of 1.65V\r
+#define COMP_REF_1_753125V 0x00000209 // Internal reference of 1.753125V\r
+#define COMP_REF_1_7875V 0x0000030D // Internal reference of 1.7875V\r
+#define COMP_REF_1_85625V 0x0000020A // Internal reference of 1.85625V\r
+#define COMP_REF_1_925V 0x0000030E // Internal reference of 1.925V\r
+#define COMP_REF_1_959375V 0x0000020B // Internal reference of 1.959375V\r
+#define COMP_REF_2_0625V 0x0000030F // Internal reference of 2.0625V\r
+#define COMP_REF_2_165625V 0x0000020D // Internal reference of 2.165625V\r
+#define COMP_REF_2_26875V 0x0000020E // Internal reference of 2.26875V\r
+#define COMP_REF_2_371875V 0x0000020F // Internal reference of 2.371875V\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+extern void ComparatorConfigure(unsigned long ulBase, unsigned long ulComp,\r
+ unsigned long ulConfig);\r
+extern void ComparatorRefSet(unsigned long ulBase, unsigned long ulRef);\r
+extern tBoolean ComparatorValueGet(unsigned long ulBase, unsigned long ulComp);\r
+extern void ComparatorIntRegister(unsigned long ulBase, unsigned long ulComp,\r
+ void (*pfnHandler)(void));\r
+extern void ComparatorIntUnregister(unsigned long ulBase,\r
+ unsigned long ulComp);\r
+extern void ComparatorIntEnable(unsigned long ulBase, unsigned long ulComp);\r
+extern void ComparatorIntDisable(unsigned long ulBase, unsigned long ulComp);\r
+extern tBoolean ComparatorIntStatus(unsigned long ulBase, unsigned long ulComp,\r
+ tBoolean bMasked);\r
+extern void ComparatorIntClear(unsigned long ulBase, unsigned long ulComp);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __COMP_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// cpu.h - Prototypes for the CPU instruction wrapper functions.\r
+//\r
+// Copyright (c) 2006-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __CPU_H__\r
+#define __CPU_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes.\r
+//\r
+//*****************************************************************************\r
+extern void CPUcpsid(void);\r
+extern void CPUcpsie(void);\r
+extern void CPUwfi(void);\r
+\r
+#endif // __CPU_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// debug.h - Macros for assisting debug of the driver library.\r
+//\r
+// Copyright (c) 2006-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __DEBUG_H__\r
+#define __DEBUG_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototype for the function that is called when an invalid argument is passed\r
+// to an API. This is only used when doing a DEBUG build.\r
+//\r
+//*****************************************************************************\r
+extern void __error__(char *pcFilename, unsigned long ulLine);\r
+\r
+//*****************************************************************************\r
+//\r
+// The ASSERT macro, which does the actual assertion checking. Typically, this\r
+// will be for procedure arguments.\r
+//\r
+//*****************************************************************************\r
+#ifdef DEBUG\r
+#define ASSERT(expr) { \\r
+ if(!(expr)) \\r
+ { \\r
+ __error__(__FILE__, __LINE__); \\r
+ } \\r
+ }\r
+#else\r
+#define ASSERT(expr)\r
+#endif\r
+\r
+#endif // __DEBUG_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// ethernet.h - Defines and Macros for the ethernet module.\r
+//\r
+// Copyright (c) 2006-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __ETHERNET_H__\r
+#define __ETHERNET_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to EthernetConfigSet as the ulConfig value, and\r
+// returned from EthernetConfigGet.\r
+//\r
+//*****************************************************************************\r
+#define ETH_CFG_RX_BADCRCDIS 0x000800 // Disable RX BAD CRC Packets\r
+#define ETH_CFG_RX_PRMSEN 0x000400 // Enable RX Promiscuous\r
+#define ETH_CFG_RX_AMULEN 0x000200 // Enable RX Multicast\r
+#define ETH_CFG_TX_DPLXEN 0x000010 // Enable TX Duplex Mode\r
+#define ETH_CFG_TX_CRCEN 0x000004 // Enable TX CRC Generation\r
+#define ETH_CFG_TX_PADEN 0x000002 // Enable TX Padding\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to EthernetIntEnable, EthernetIntDisable, and\r
+// EthernetIntClear as the ulIntFlags parameter, and returned from\r
+// EthernetIntStatus.\r
+//\r
+//*****************************************************************************\r
+#define ETH_INT_PHY 0x040 // PHY Event/Interrupt\r
+#define ETH_INT_MDIO 0x020 // Management Transaction\r
+#define ETH_INT_RXER 0x010 // RX Error\r
+#define ETH_INT_RXOF 0x008 // RX FIFO Overrun\r
+#define ETH_INT_TX 0x004 // TX Complete\r
+#define ETH_INT_TXER 0x002 // TX Error\r
+#define ETH_INT_RX 0x001 // RX Complete\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define values that can be passed as register addresses to\r
+// EthernetPHYRead and EthernetPHYWrite.\r
+//\r
+//*****************************************************************************\r
+#define PHY_MR0 0 // Control\r
+#define PHY_MR1 1 // Status\r
+#define PHY_MR2 2 // PHY Identifier 1\r
+#define PHY_MR3 3 // PHY Identifier 2\r
+#define PHY_MR4 4 // Auto-Neg. Advertisement\r
+#define PHY_MR5 5 // Auto-Neg. Link Partner Ability\r
+#define PHY_MR6 6 // Auto-Neg. Expansion\r
+ // 7-15 Reserved/Not Implemented\r
+#define PHY_MR16 16 // Vendor Specific\r
+#define PHY_MR17 17 // Interrupt Control/Status\r
+#define PHY_MR18 18 // Diagnostic Register\r
+#define PHY_MR19 19 // Transceiver Control\r
+ // 20-22 Reserved\r
+#define PHY_MR23 23 // LED Configuration Register\r
+#define PHY_MR24 24 // MDI/MDIX Control Register\r
+ // 25-31 Reserved/Not Implemented\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define bit fields in the ETH_MR0 register\r
+//\r
+//*****************************************************************************\r
+#define PHY_MR0_RESET 0x8000 // Reset the PHY\r
+#define PHY_MR0_LOOPBK 0x4000 // TXD to RXD Loopback\r
+#define PHY_MR0_SPEEDSL 0x2000 // Speed Selection\r
+#define PHY_MR0_SPEEDSL_10 0x0000 // Speed Selection 10BASE-T\r
+#define PHY_MR0_SPEEDSL_100 0x2000 // Speed Selection 100BASE-T\r
+#define PHY_MR0_ANEGEN 0x1000 // Auto-Negotiation Enable\r
+#define PHY_MR0_PWRDN 0x0800 // Power Down\r
+#define PHY_MR0_RANEG 0x0200 // Restart Auto-Negotiation\r
+#define PHY_MR0_DUPLEX 0x0100 // Enable full duplex\r
+#define PHY_MR0_DUPLEX_HALF 0x0000 // Enable half duplex mode\r
+#define PHY_MR0_DUPLEX_FULL 0x0100 // Enable full duplex mode\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define bit fields in the ETH_MR1 register\r
+//\r
+//*****************************************************************************\r
+#define PHY_MR1_ANEGC 0x0020 // Auto-Negotiate Complete\r
+#define PHY_MR1_RFAULT 0x0010 // Remove Fault Detected\r
+#define PHY_MR1_LINK 0x0004 // Link Established\r
+#define PHY_MR1_JAB 0x0002 // Jabber Condition Detected\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define bit fields in the ETH_MR17 register\r
+//\r
+//*****************************************************************************\r
+#define PHY_MR17_RXER_IE 0x4000 // Enable Receive Error Interrupt\r
+#define PHY_MR17_LSCHG_IE 0x0400 // Enable Link Status Change Int.\r
+#define PHY_MR17_ANEGCOMP_IE 0x0100 // Enable Auto-Negotiate Cmpl. Int.\r
+#define PHY_MR17_RXER_INT 0x0040 // Receive Error Interrupt\r
+#define PHY_MR17_LSCHG_INT 0x0004 // Link Status Change Interrupt\r
+#define PHY_MR17_ANEGCOMP_INT 0x0001 // Auto-Negotiate Complete Int.\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define bit fields in the ETH_MR18 register\r
+//\r
+//*****************************************************************************\r
+#define PHY_MR18_ANEGF 0x1000 // Auto-Negotiate Failed\r
+#define PHY_MR18_DPLX 0x0800 // Duplex Mode Negotiated\r
+#define PHY_MR18_DPLX_HALF 0x0000 // Half Duplex Mode Negotiated\r
+#define PHY_MR18_DPLX_FULL 0x0800 // Full Duplex Mode Negotiated\r
+#define PHY_MR18_RATE 0x0400 // Rate Negotiated\r
+#define PHY_MR18_RATE_10 0x0000 // Rate Negotiated is 10BASE-T\r
+#define PHY_MR18_RATE_100 0x0400 // Rate Negotiated is 100BASE-TX\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define bit fields in the ETH_MR23 register\r
+//\r
+//*****************************************************************************\r
+#define PHY_MR23_LED1 0x00f0 // LED1 Configuration\r
+#define PHY_MR23_LED1_LINK 0x0000 // LED1 is Link Status\r
+#define PHY_MR23_LED1_RXTX 0x0010 // LED1 is RX or TX Activity\r
+#define PHY_MR23_LED1_TX 0x0020 // LED1 is TX Activity\r
+#define PHY_MR23_LED1_RX 0x0030 // LED1 is RX Activity\r
+#define PHY_MR23_LED1_COL 0x0040 // LED1 is RX Activity\r
+#define PHY_MR23_LED1_100 0x0050 // LED1 is RX Activity\r
+#define PHY_MR23_LED1_10 0x0060 // LED1 is RX Activity\r
+#define PHY_MR23_LED1_DUPLEX 0x0070 // LED1 is RX Activity\r
+#define PHY_MR23_LED1_LINKACT 0x0080 // LED1 is Link Status + Activity\r
+#define PHY_MR23_LED0 0x000f // LED0 Configuration\r
+#define PHY_MR23_LED0_LINK 0x0000 // LED0 is Link Status\r
+#define PHY_MR23_LED0_RXTX 0x0001 // LED0 is RX or TX Activity\r
+#define PHY_MR23_LED0_TX 0x0002 // LED0 is TX Activity\r
+#define PHY_MR23_LED0_RX 0x0003 // LED0 is RX Activity\r
+#define PHY_MR23_LED0_COL 0x0004 // LED0 is RX Activity\r
+#define PHY_MR23_LED0_100 0x0005 // LED0 is RX Activity\r
+#define PHY_MR23_LED0_10 0x0006 // LED0 is RX Activity\r
+#define PHY_MR23_LED0_DUPLEX 0x0007 // LED0 is RX Activity\r
+#define PHY_MR23_LED0_LINKACT 0x0008 // LED0 is Link Status + Activity\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define bit fields in the ETH_MR24 register\r
+//\r
+//*****************************************************************************\r
+#define PHY_MR24_MDIX 0x0020 // Auto-Switching Configuration\r
+#define PHY_MR24_MDIX_NORMAL 0x0000 // Auto-Switching in passthrough\r
+#define PHY_MR23_MDIX_CROSSOVER 0x0020 // Auto-Switching in crossover\r
+\r
+//*****************************************************************************\r
+//\r
+// Helper Macros for Ethernet Processing\r
+//\r
+//*****************************************************************************\r
+//\r
+// htonl/ntohl - big endian/little endian byte swapping macros for\r
+// 32-bit (long) values\r
+//\r
+//*****************************************************************************\r
+#ifndef htonl\r
+ #define htonl(a) \\r
+ ((((a) >> 24) & 0x000000ff) | \\r
+ (((a) >> 8) & 0x0000ff00) | \\r
+ (((a) << 8) & 0x00ff0000) | \\r
+ (((a) << 24) & 0xff000000))\r
+#endif\r
+\r
+#ifndef ntohl\r
+ #define ntohl(a) htonl((a))\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// htons/ntohs - big endian/little endian byte swapping macros for\r
+// 16-bit (short) values\r
+//\r
+//*****************************************************************************\r
+#ifndef htons\r
+ #define htons(a) \\r
+ ((((a) >> 8) & 0x00ff) | \\r
+ (((a) << 8) & 0xff00))\r
+#endif\r
+\r
+#ifndef ntohs\r
+ #define ntohs(a) htons((a))\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// API Function prototypes\r
+//\r
+//*****************************************************************************\r
+extern void EthernetInit(unsigned long ulBase);\r
+extern void EthernetConfigSet(unsigned long ulBase, unsigned long ulConfig);\r
+extern unsigned long EthernetConfigGet(unsigned long ulBase);\r
+extern void EthernetMACAddrSet(unsigned long ulBase,\r
+ unsigned char *pucMACAddr);\r
+extern void EthernetMACAddrGet(unsigned long ulBase,\r
+ unsigned char *pucMACAddr);\r
+extern void EthernetEnable(unsigned long ulBase);\r
+extern void EthernetDisable(unsigned long ulBase);\r
+extern tBoolean EthernetPacketAvail(unsigned long ulBase);\r
+extern tBoolean EthernetSpaceAvail(unsigned long ulBase);\r
+extern long EthernetPacketNonBlockingGet(unsigned long ulBase,\r
+ unsigned char *pucBuf,\r
+ long lBufLen);\r
+extern long EthernetPacketGet(unsigned long ulBase, unsigned char *pucBuf,\r
+ long lBufLen);\r
+extern long EthernetPacketNonBlockingPut(unsigned long ulBase,\r
+ unsigned char *pucBuf,\r
+ long lBufLen);\r
+extern long EthernetPacketPut(unsigned long ulBase, unsigned char *pucBuf,\r
+ long lBufLen);\r
+extern void EthernetIntRegister(unsigned long ulBase,\r
+ void (*pfnHandler)(void));\r
+extern void EthernetIntUnregister(unsigned long ulBase);\r
+extern void EthernetIntEnable(unsigned long ulBase, unsigned long ulIntFlags);\r
+extern void EthernetIntDisable(unsigned long ulBase, unsigned long ulIntFlags);\r
+extern unsigned long EthernetIntStatus(unsigned long ulBase, tBoolean bMasked);\r
+extern void EthernetIntClear(unsigned long ulBase, unsigned long ulIntFlags);\r
+extern void EthernetPHYWrite(unsigned long ulBase, unsigned char ucRegAddr,\r
+ unsigned long ulData);\r
+extern unsigned long EthernetPHYRead(unsigned long ulBase,\r
+ unsigned char ucRegAddr);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __ETHERNET_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// gpio.h - Defines and Macros for GPIO API.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __GPIO_H__\r
+#define __GPIO_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// The following values define the bit field for the ucPins argument to several\r
+// of the APIs.\r
+//\r
+//*****************************************************************************\r
+#define GPIO_PIN_0 0x00000001 // GPIO pin 0\r
+#define GPIO_PIN_1 0x00000002 // GPIO pin 1\r
+#define GPIO_PIN_2 0x00000004 // GPIO pin 2\r
+#define GPIO_PIN_3 0x00000008 // GPIO pin 3\r
+#define GPIO_PIN_4 0x00000010 // GPIO pin 4\r
+#define GPIO_PIN_5 0x00000020 // GPIO pin 5\r
+#define GPIO_PIN_6 0x00000040 // GPIO pin 6\r
+#define GPIO_PIN_7 0x00000080 // GPIO pin 7\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to GPIODirModeSet as the ulPinIO parameter, and\r
+// returned from GPIODirModeGet.\r
+//\r
+//*****************************************************************************\r
+#define GPIO_DIR_MODE_IN 0x00000000 // Pin is a GPIO input\r
+#define GPIO_DIR_MODE_OUT 0x00000001 // Pin is a GPIO output\r
+#define GPIO_DIR_MODE_HW 0x00000002 // Pin is a peripheral function\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to GPIOIntTypeSet as the ulIntType parameter, and\r
+// returned from GPIOIntTypeGet.\r
+//\r
+//*****************************************************************************\r
+#define GPIO_FALLING_EDGE 0x00000000 // Interrupt on falling edge\r
+#define GPIO_RISING_EDGE 0x00000004 // Interrupt on rising edge\r
+#define GPIO_BOTH_EDGES 0x00000001 // Interrupt on both edges\r
+#define GPIO_LOW_LEVEL 0x00000002 // Interrupt on low level\r
+#define GPIO_HIGH_LEVEL 0x00000007 // Interrupt on high level\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to GPIOPadConfigSet as the ulStrength parameter,\r
+// and returned by GPIOPadConfigGet in the *pulStrength parameter.\r
+//\r
+//*****************************************************************************\r
+#define GPIO_STRENGTH_2MA 0x00000001 // 2mA drive strength\r
+#define GPIO_STRENGTH_4MA 0x00000002 // 4mA drive strength\r
+#define GPIO_STRENGTH_8MA 0x00000004 // 8mA drive strength\r
+#define GPIO_STRENGTH_8MA_SC 0x0000000C // 8mA drive with slew rate control\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to GPIOPadConfigSet as the ulPadType parameter,\r
+// and returned by GPIOPadConfigGet in the *pulPadType parameter.\r
+//\r
+//*****************************************************************************\r
+#define GPIO_PIN_TYPE_STD 0x00000008 // Push-pull\r
+#define GPIO_PIN_TYPE_STD_WPU 0x0000000A // Push-pull with weak pull-up\r
+#define GPIO_PIN_TYPE_STD_WPD 0x0000000C // Push-pull with weak pull-down\r
+#define GPIO_PIN_TYPE_OD 0x00000009 // Open-drain\r
+#define GPIO_PIN_TYPE_OD_WPU 0x0000000B // Open-drain with weak pull-up\r
+#define GPIO_PIN_TYPE_OD_WPD 0x0000000D // Open-drain with weak pull-down\r
+#define GPIO_PIN_TYPE_ANALOG 0x00000000 // Analog comparator\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+extern void GPIODirModeSet(unsigned long ulPort, unsigned char ucPins,\r
+ unsigned long ulPinIO);\r
+extern unsigned long GPIODirModeGet(unsigned long ulPort, unsigned char ucPin);\r
+extern void GPIOIntTypeSet(unsigned long ulPort, unsigned char ucPins,\r
+ unsigned long ulIntType);\r
+extern unsigned long GPIOIntTypeGet(unsigned long ulPort, unsigned char ucPin);\r
+extern void GPIOPadConfigSet(unsigned long ulPort, unsigned char ucPins,\r
+ unsigned long ulStrength,\r
+ unsigned long ulPadType);\r
+extern void GPIOPadConfigGet(unsigned long ulPort, unsigned char ucPin,\r
+ unsigned long *pulStrength,\r
+ unsigned long *pulPadType);\r
+extern void GPIOPinIntEnable(unsigned long ulPort, unsigned char ucPins);\r
+extern void GPIOPinIntDisable(unsigned long ulPort, unsigned char ucPins);\r
+extern long GPIOPinIntStatus(unsigned long ulPort, tBoolean bMasked);\r
+extern void GPIOPinIntClear(unsigned long ulPort, unsigned char ucPins);\r
+extern void GPIOPortIntRegister(unsigned long ulPort,\r
+ void (*pfIntHandler)(void));\r
+extern void GPIOPortIntUnregister(unsigned long ulPort);\r
+extern long GPIOPinRead(unsigned long ulPort, unsigned char ucPins);\r
+extern void GPIOPinWrite(unsigned long ulPort, unsigned char ucPins,\r
+ unsigned char ucVal);\r
+extern void GPIOPinTypeComparator(unsigned long ulPort, unsigned char ucPins);\r
+extern void GPIOPinTypeI2C(unsigned long ulPort, unsigned char ucPins);\r
+extern void GPIOPinTypePWM(unsigned long ulPort, unsigned char ucPins);\r
+extern void GPIOPinTypeQEI(unsigned long ulPort, unsigned char ucPins);\r
+extern void GPIOPinTypeSSI(unsigned long ulPort, unsigned char ucPins);\r
+extern void GPIOPinTypeTimer(unsigned long ulPort, unsigned char ucPins);\r
+extern void GPIOPinTypeUART(unsigned long ulPort, unsigned char ucPins);\r
+extern void GPIOPinTypeCAN(unsigned long ulPort, unsigned char ucPins);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __GPIO_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hibernate.h - API definition for the Hibernation module.\r
+//\r
+// Copyright (c) 2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HIBERNATE_H__\r
+#define __HIBERNATE_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Macros needed for selecting the clock source for HibernateClockSelect()\r
+//\r
+//*****************************************************************************\r
+#define HIBERNATE_CLOCK_SEL_RAW 0x04\r
+#define HIBERNATE_CLOCK_SEL_DIV128 0x00\r
+\r
+//*****************************************************************************\r
+//\r
+// Macros need to configure wake events for HibernateWakeSet()\r
+//\r
+//*****************************************************************************\r
+#define HIBERNATE_WAKE_PIN 0x10\r
+#define HIBERNATE_WAKE_RTC 0x08\r
+\r
+//*****************************************************************************\r
+//\r
+// Macros needed to configure low battery detect for HibernateLowBatSet()\r
+//\r
+//*****************************************************************************\r
+#define HIBERNATE_LOW_BAT_DETECT 0x20\r
+#define HIBERNATE_LOW_BAT_ABORT 0xA0\r
+\r
+//*****************************************************************************\r
+//\r
+// Macros defining interrupt source bits for the interrupt functions.\r
+//\r
+//*****************************************************************************\r
+#define HIBERNATE_INT_PIN_WAKE 0x08\r
+#define HIBERNATE_INT_LOW_BAT 0x04\r
+#define HIBERNATE_INT_RTC_MATCH_0 0x01\r
+#define HIBERNATE_INT_RTC_MATCH_1 0x02\r
+\r
+//*****************************************************************************\r
+//\r
+// API Function prototypes\r
+//\r
+//*****************************************************************************\r
+extern void HibernateEnable(void);\r
+extern void HibernateDisable(void);\r
+extern void HibernateClockSelect(unsigned long ulClockInput);\r
+extern void HibernateRTCEnable(void);\r
+extern void HibernateRTCDisable(void);\r
+extern void HibernateWakeSet(unsigned long ulWakeFlags);\r
+extern unsigned long HibernateWakeGet(void);\r
+extern void HibernateLowBatSet(unsigned long ulLowBatFlags);\r
+extern unsigned long HibernateLowBatGet(void);\r
+extern void HibernateRTCSet(unsigned long ulRTCValue);\r
+extern unsigned long HibernateRTCGet(void);\r
+extern void HibernateRTCMatch0Set(unsigned long ulMatch);\r
+extern unsigned long HibernateRTCMatch0Get(void);\r
+extern void HibernateRTCMatch1Set(unsigned long ulMatch);\r
+extern unsigned long HibernateRTCMatch1Get(void);\r
+extern void HibernateRTCTrimSet(unsigned long ulTrim);\r
+extern unsigned long HibernateRTCTrimGet(void);\r
+extern void HibernateDataSet(unsigned long *pulData, unsigned long ulCount);\r
+extern void HibernateDataGet(unsigned long *pulData, unsigned long ulCount);\r
+extern void HibernateRequest(void);\r
+extern void HibernateIntEnable(unsigned long ulIntFlags);\r
+extern void HibernateIntDisable(unsigned long ulIntFlags);\r
+extern void HibernateIntRegister(void (*pfnHandler)(void));\r
+extern void HibernateIntUnregister(void);\r
+extern unsigned long HibernateIntStatus(tBoolean bMasked);\r
+extern void HibernateIntClear(unsigned long ulIntFlags);\r
+extern unsigned int HibernateIsActive(void);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __HIBERNATE_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_adc.h - Macros used when accessing the ADC hardware.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_ADC_H__\r
+#define __HW_ADC_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the offsets of the ADC registers.\r
+//\r
+//*****************************************************************************\r
+#define ADC_O_ACTSS 0x00000000 // Active sample register\r
+#define ADC_O_RIS 0x00000004 // Raw interrupt status register\r
+#define ADC_O_IM 0x00000008 // Interrupt mask register\r
+#define ADC_O_ISC 0x0000000C // Interrupt status/clear register\r
+#define ADC_O_OSTAT 0x00000010 // Overflow status register\r
+#define ADC_O_EMUX 0x00000014 // Event multiplexer select reg.\r
+#define ADC_O_USTAT 0x00000018 // Underflow status register\r
+#define ADC_O_SSPRI 0x00000020 // Channel priority register\r
+#define ADC_O_PSSI 0x00000028 // Processor sample initiate reg.\r
+#define ADC_O_SAC 0x00000030 // Sample Averaging Control reg.\r
+#define ADC_O_SSMUX0 0x00000040 // Multiplexer select 0 register\r
+#define ADC_O_SSCTL0 0x00000044 // Sample sequence control 0 reg.\r
+#define ADC_O_SSFIFO0 0x00000048 // Result FIFO 0 register\r
+#define ADC_O_SSFSTAT0 0x0000004C // FIFO 0 status register\r
+#define ADC_O_SSMUX1 0x00000060 // Multiplexer select 1 register\r
+#define ADC_O_SSCTL1 0x00000064 // Sample sequence control 1 reg.\r
+#define ADC_O_SSFIFO1 0x00000068 // Result FIFO 1 register\r
+#define ADC_O_SSFSTAT1 0x0000006C // FIFO 1 status register\r
+#define ADC_O_SSMUX2 0x00000080 // Multiplexer select 2 register\r
+#define ADC_O_SSCTL2 0x00000084 // Sample sequence control 2 reg.\r
+#define ADC_O_SSFIFO2 0x00000088 // Result FIFO 2 register\r
+#define ADC_O_SSFSTAT2 0x0000008C // FIFO 2 status register\r
+#define ADC_O_SSMUX3 0x000000A0 // Multiplexer select 3 register\r
+#define ADC_O_SSCTL3 0x000000A4 // Sample sequence control 3 reg.\r
+#define ADC_O_SSFIFO3 0x000000A8 // Result FIFO 3 register\r
+#define ADC_O_SSFSTAT3 0x000000AC // FIFO 3 status register\r
+#define ADC_O_TMLB 0x00000100 // Test mode loopback register\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the offsets of the ADC sequence registers.\r
+//\r
+//*****************************************************************************\r
+#define ADC_O_SEQ 0x00000040 // Offset to the first sequence\r
+#define ADC_O_SEQ_STEP 0x00000020 // Increment to the next sequence\r
+#define ADC_O_X_SSMUX 0x00000000 // Multiplexer select register\r
+#define ADC_O_X_SSCTL 0x00000004 // Sample sequence control register\r
+#define ADC_O_X_SSFIFO 0x00000008 // Result FIFO register\r
+#define ADC_O_X_SSFSTAT 0x0000000C // FIFO status register\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the ADC_ACTSS register.\r
+//\r
+//*****************************************************************************\r
+#define ADC_ACTSS_ASEN3 0x00000008 // Sample sequence 3 enable\r
+#define ADC_ACTSS_ASEN2 0x00000004 // Sample sequence 2 enable\r
+#define ADC_ACTSS_ASEN1 0x00000002 // Sample sequence 1 enable\r
+#define ADC_ACTSS_ASEN0 0x00000001 // Sample sequence 0 enable\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the ADC_RIS register.\r
+//\r
+//*****************************************************************************\r
+#define ADC_RIS_INR3 0x00000008 // Sample sequence 3 interrupt\r
+#define ADC_RIS_INR2 0x00000004 // Sample sequence 2 interrupt\r
+#define ADC_RIS_INR1 0x00000002 // Sample sequence 1 interrupt\r
+#define ADC_RIS_INR0 0x00000001 // Sample sequence 0 interrupt\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the ADC_IM register.\r
+//\r
+//*****************************************************************************\r
+#define ADC_IM_MASK3 0x00000008 // Sample sequence 3 mask\r
+#define ADC_IM_MASK2 0x00000004 // Sample sequence 2 mask\r
+#define ADC_IM_MASK1 0x00000002 // Sample sequence 1 mask\r
+#define ADC_IM_MASK0 0x00000001 // Sample sequence 0 mask\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the ADC_ISC register.\r
+//\r
+//*****************************************************************************\r
+#define ADC_ISC_IN3 0x00000008 // Sample sequence 3 interrupt\r
+#define ADC_ISC_IN2 0x00000004 // Sample sequence 2 interrupt\r
+#define ADC_ISC_IN1 0x00000002 // Sample sequence 1 interrupt\r
+#define ADC_ISC_IN0 0x00000001 // Sample sequence 0 interrupt\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the ADC_OSTAT register.\r
+//\r
+//*****************************************************************************\r
+#define ADC_OSTAT_OV3 0x00000008 // Sample sequence 3 overflow\r
+#define ADC_OSTAT_OV2 0x00000004 // Sample sequence 2 overflow\r
+#define ADC_OSTAT_OV1 0x00000002 // Sample sequence 1 overflow\r
+#define ADC_OSTAT_OV0 0x00000001 // Sample sequence 0 overflow\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the ADC_EMUX register.\r
+//\r
+//*****************************************************************************\r
+#define ADC_EMUX_EM3_MASK 0x0000F000 // Event mux 3 mask\r
+#define ADC_EMUX_EM3_PROCESSOR 0x00000000 // Processor event\r
+#define ADC_EMUX_EM3_COMP0 0x00001000 // Analog comparator 0 event\r
+#define ADC_EMUX_EM3_COMP1 0x00002000 // Analog comparator 1 event\r
+#define ADC_EMUX_EM3_COMP2 0x00003000 // Analog comparator 2 event\r
+#define ADC_EMUX_EM3_EXTERNAL 0x00004000 // External event\r
+#define ADC_EMUX_EM3_TIMER 0x00005000 // Timer event\r
+#define ADC_EMUX_EM3_PWM0 0x00006000 // PWM0 event\r
+#define ADC_EMUX_EM3_PWM1 0x00007000 // PWM1 event\r
+#define ADC_EMUX_EM3_PWM2 0x00008000 // PWM2 event\r
+#define ADC_EMUX_EM3_ALWAYS 0x0000F000 // Always event\r
+#define ADC_EMUX_EM2_MASK 0x00000F00 // Event mux 2 mask\r
+#define ADC_EMUX_EM2_PROCESSOR 0x00000000 // Processor event\r
+#define ADC_EMUX_EM2_COMP0 0x00000100 // Analog comparator 0 event\r
+#define ADC_EMUX_EM2_COMP1 0x00000200 // Analog comparator 1 event\r
+#define ADC_EMUX_EM2_COMP2 0x00000300 // Analog comparator 2 event\r
+#define ADC_EMUX_EM2_EXTERNAL 0x00000400 // External event\r
+#define ADC_EMUX_EM2_TIMER 0x00000500 // Timer event\r
+#define ADC_EMUX_EM2_PWM0 0x00000600 // PWM0 event\r
+#define ADC_EMUX_EM2_PWM1 0x00000700 // PWM1 event\r
+#define ADC_EMUX_EM2_PWM2 0x00000800 // PWM2 event\r
+#define ADC_EMUX_EM2_ALWAYS 0x00000F00 // Always event\r
+#define ADC_EMUX_EM1_MASK 0x000000F0 // Event mux 1 mask\r
+#define ADC_EMUX_EM1_PROCESSOR 0x00000000 // Processor event\r
+#define ADC_EMUX_EM1_COMP0 0x00000010 // Analog comparator 0 event\r
+#define ADC_EMUX_EM1_COMP1 0x00000020 // Analog comparator 1 event\r
+#define ADC_EMUX_EM1_COMP2 0x00000030 // Analog comparator 2 event\r
+#define ADC_EMUX_EM1_EXTERNAL 0x00000040 // External event\r
+#define ADC_EMUX_EM1_TIMER 0x00000050 // Timer event\r
+#define ADC_EMUX_EM1_PWM0 0x00000060 // PWM0 event\r
+#define ADC_EMUX_EM1_PWM1 0x00000070 // PWM1 event\r
+#define ADC_EMUX_EM1_PWM2 0x00000080 // PWM2 event\r
+#define ADC_EMUX_EM1_ALWAYS 0x000000F0 // Always event\r
+#define ADC_EMUX_EM0_MASK 0x0000000F // Event mux 0 mask\r
+#define ADC_EMUX_EM0_PROCESSOR 0x00000000 // Processor event\r
+#define ADC_EMUX_EM0_COMP0 0x00000001 // Analog comparator 0 event\r
+#define ADC_EMUX_EM0_COMP1 0x00000002 // Analog comparator 1 event\r
+#define ADC_EMUX_EM0_COMP2 0x00000003 // Analog comparator 2 event\r
+#define ADC_EMUX_EM0_EXTERNAL 0x00000004 // External event\r
+#define ADC_EMUX_EM0_TIMER 0x00000005 // Timer event\r
+#define ADC_EMUX_EM0_PWM0 0x00000006 // PWM0 event\r
+#define ADC_EMUX_EM0_PWM1 0x00000007 // PWM1 event\r
+#define ADC_EMUX_EM0_PWM2 0x00000008 // PWM2 event\r
+#define ADC_EMUX_EM0_ALWAYS 0x0000000F // Always event\r
+#define ADC_EMUX_EM0_SHIFT 0 // The shift for the first event\r
+#define ADC_EMUX_EM1_SHIFT 4 // The shift for the second event\r
+#define ADC_EMUX_EM2_SHIFT 8 // The shift for the third event\r
+#define ADC_EMUX_EM3_SHIFT 12 // The shift for the fourth event\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the ADC_USTAT register.\r
+//\r
+//*****************************************************************************\r
+#define ADC_USTAT_UV3 0x00000008 // Sample sequence 3 underflow\r
+#define ADC_USTAT_UV2 0x00000004 // Sample sequence 2 underflow\r
+#define ADC_USTAT_UV1 0x00000002 // Sample sequence 1 underflow\r
+#define ADC_USTAT_UV0 0x00000001 // Sample sequence 0 underflow\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the ADC_SSPRI register.\r
+//\r
+//*****************************************************************************\r
+#define ADC_SSPRI_SS3_MASK 0x00003000 // Sequencer 3 priority mask\r
+#define ADC_SSPRI_SS3_1ST 0x00000000 // First priority\r
+#define ADC_SSPRI_SS3_2ND 0x00001000 // Second priority\r
+#define ADC_SSPRI_SS3_3RD 0x00002000 // Third priority\r
+#define ADC_SSPRI_SS3_4TH 0x00003000 // Fourth priority\r
+#define ADC_SSPRI_SS2_MASK 0x00000300 // Sequencer 2 priority mask\r
+#define ADC_SSPRI_SS2_1ST 0x00000000 // First priority\r
+#define ADC_SSPRI_SS2_2ND 0x00000100 // Second priority\r
+#define ADC_SSPRI_SS2_3RD 0x00000200 // Third priority\r
+#define ADC_SSPRI_SS2_4TH 0x00000300 // Fourth priority\r
+#define ADC_SSPRI_SS1_MASK 0x00000030 // Sequencer 1 priority mask\r
+#define ADC_SSPRI_SS1_1ST 0x00000000 // First priority\r
+#define ADC_SSPRI_SS1_2ND 0x00000010 // Second priority\r
+#define ADC_SSPRI_SS1_3RD 0x00000020 // Third priority\r
+#define ADC_SSPRI_SS1_4TH 0x00000030 // Fourth priority\r
+#define ADC_SSPRI_SS0_MASK 0x00000003 // Sequencer 0 priority mask\r
+#define ADC_SSPRI_SS0_1ST 0x00000000 // First priority\r
+#define ADC_SSPRI_SS0_2ND 0x00000001 // Second priority\r
+#define ADC_SSPRI_SS0_3RD 0x00000002 // Third priority\r
+#define ADC_SSPRI_SS0_4TH 0x00000003 // Fourth priority\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the ADC_PSSI register.\r
+//\r
+//*****************************************************************************\r
+#define ADC_PSSI_SS3 0x00000008 // Trigger sample sequencer 3\r
+#define ADC_PSSI_SS2 0x00000004 // Trigger sample sequencer 2\r
+#define ADC_PSSI_SS1 0x00000002 // Trigger sample sequencer 1\r
+#define ADC_PSSI_SS0 0x00000001 // Trigger sample sequencer 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the ADC_SAC register.\r
+//\r
+//*****************************************************************************\r
+#define ADC_SAC_AVG_OFF 0x00000000 // No hardware oversampling\r
+#define ADC_SAC_AVG_2X 0x00000001 // 2x hardware oversampling\r
+#define ADC_SAC_AVG_4X 0x00000002 // 4x hardware oversampling\r
+#define ADC_SAC_AVG_8X 0x00000003 // 8x hardware oversampling\r
+#define ADC_SAC_AVG_16X 0x00000004 // 16x hardware oversampling\r
+#define ADC_SAC_AVG_32X 0x00000005 // 32x hardware oversampling\r
+#define ADC_SAC_AVG_64X 0x00000006 // 64x hardware oversampling\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the ADC_SSMUX0, ADC_SSMUX1,\r
+// ADC_SSMUX2, and ADC_SSMUX3 registers. Not all fields are present in all\r
+// registers.\r
+//\r
+//*****************************************************************************\r
+#define ADC_SSMUX_MUX7_MASK 0x70000000 // 8th mux select mask\r
+#define ADC_SSMUX_MUX6_MASK 0x07000000 // 7th mux select mask\r
+#define ADC_SSMUX_MUX5_MASK 0x00700000 // 6th mux select mask\r
+#define ADC_SSMUX_MUX4_MASK 0x00070000 // 5th mux select mask\r
+#define ADC_SSMUX_MUX3_MASK 0x00007000 // 4th mux select mask\r
+#define ADC_SSMUX_MUX2_MASK 0x00000700 // 3rd mux select mask\r
+#define ADC_SSMUX_MUX1_MASK 0x00000070 // 2nd mux select mask\r
+#define ADC_SSMUX_MUX0_MASK 0x00000007 // 1st mux select mask\r
+#define ADC_SSMUX_MUX7_SHIFT 28\r
+#define ADC_SSMUX_MUX6_SHIFT 24\r
+#define ADC_SSMUX_MUX5_SHIFT 20\r
+#define ADC_SSMUX_MUX4_SHIFT 16\r
+#define ADC_SSMUX_MUX3_SHIFT 12\r
+#define ADC_SSMUX_MUX2_SHIFT 8\r
+#define ADC_SSMUX_MUX1_SHIFT 4\r
+#define ADC_SSMUX_MUX0_SHIFT 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the ADC_SSCTL0, ADC_SSCTL1,\r
+// ADC_SSCTL2, and ADC_SSCTL3 registers. Not all fields are present in all\r
+// registers.\r
+//\r
+//*****************************************************************************\r
+#define ADC_SSCTL_TS7 0x80000000 // 8th temperature sensor select\r
+#define ADC_SSCTL_IE7 0x40000000 // 8th interrupt enable\r
+#define ADC_SSCTL_END7 0x20000000 // 8th sequence end select\r
+#define ADC_SSCTL_D7 0x10000000 // 8th differential select\r
+#define ADC_SSCTL_TS6 0x08000000 // 7th temperature sensor select\r
+#define ADC_SSCTL_IE6 0x04000000 // 7th interrupt enable\r
+#define ADC_SSCTL_END6 0x02000000 // 7th sequence end select\r
+#define ADC_SSCTL_D6 0x01000000 // 7th differential select\r
+#define ADC_SSCTL_TS5 0x00800000 // 6th temperature sensor select\r
+#define ADC_SSCTL_IE5 0x00400000 // 6th interrupt enable\r
+#define ADC_SSCTL_END5 0x00200000 // 6th sequence end select\r
+#define ADC_SSCTL_D5 0x00100000 // 6th differential select\r
+#define ADC_SSCTL_TS4 0x00080000 // 5th temperature sensor select\r
+#define ADC_SSCTL_IE4 0x00040000 // 5th interrupt enable\r
+#define ADC_SSCTL_END4 0x00020000 // 5th sequence end select\r
+#define ADC_SSCTL_D4 0x00010000 // 5th differential select\r
+#define ADC_SSCTL_TS3 0x00008000 // 4th temperature sensor select\r
+#define ADC_SSCTL_IE3 0x00004000 // 4th interrupt enable\r
+#define ADC_SSCTL_END3 0x00002000 // 4th sequence end select\r
+#define ADC_SSCTL_D3 0x00001000 // 4th differential select\r
+#define ADC_SSCTL_TS2 0x00000800 // 3rd temperature sensor select\r
+#define ADC_SSCTL_IE2 0x00000400 // 3rd interrupt enable\r
+#define ADC_SSCTL_END2 0x00000200 // 3rd sequence end select\r
+#define ADC_SSCTL_D2 0x00000100 // 3rd differential select\r
+#define ADC_SSCTL_TS1 0x00000080 // 2nd temperature sensor select\r
+#define ADC_SSCTL_IE1 0x00000040 // 2nd interrupt enable\r
+#define ADC_SSCTL_END1 0x00000020 // 2nd sequence end select\r
+#define ADC_SSCTL_D1 0x00000010 // 2nd differential select\r
+#define ADC_SSCTL_TS0 0x00000008 // 1st temperature sensor select\r
+#define ADC_SSCTL_IE0 0x00000004 // 1st interrupt enable\r
+#define ADC_SSCTL_END0 0x00000002 // 1st sequence end select\r
+#define ADC_SSCTL_D0 0x00000001 // 1st differential select\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the ADC_SSFIFO0, ADC_SSFIFO1,\r
+// ADC_SSFIFO2, and ADC_SSFIFO3 registers.\r
+//\r
+//*****************************************************************************\r
+#define ADC_SSFIFO_DATA_MASK 0x000003FF // Sample data\r
+#define ADC_SSFIFO_DATA_SHIFT 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the ADC_SSFSTAT0, ADC_SSFSTAT1,\r
+// ADC_SSFSTAT2, and ADC_SSFSTAT3 registers.\r
+//\r
+//*****************************************************************************\r
+#define ADC_SSFSTAT_FULL 0x00001000 // FIFO is full\r
+#define ADC_SSFSTAT_EMPTY 0x00000100 // FIFO is empty\r
+#define ADC_SSFSTAT_HPTR 0x000000F0 // FIFO head pointer\r
+#define ADC_SSFSTAT_TPTR 0x0000000F // FIFO tail pointer\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the ADC_TMLB register.\r
+//\r
+//*****************************************************************************\r
+#define ADC_TMLB_LB 0x00000001 // Loopback control signals\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the loopback ADC data.\r
+//\r
+//*****************************************************************************\r
+#define ADC_LB_CNT_MASK 0x000003C0 // Sample counter mask\r
+#define ADC_LB_CONT 0x00000020 // Continuation sample\r
+#define ADC_LB_DIFF 0x00000010 // Differential sample\r
+#define ADC_LB_TS 0x00000008 // Temperature sensor sample\r
+#define ADC_LB_MUX_MASK 0x00000007 // Input channel number mask\r
+#define ADC_LB_CNT_SHIFT 6 // Sample counter shift\r
+#define ADC_LB_MUX_SHIFT 0 // Input channel number shift\r
+\r
+#endif // __HW_ADC_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_can.h - Defines and macros used when accessing the can.\r
+//\r
+// Copyright (c) 2006-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_CAN_H__\r
+#define __HW_CAN_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the offsets of the can registers.\r
+//\r
+//*****************************************************************************\r
+#define CAN_O_CTL 0x00000000 // Control register\r
+#define CAN_O_STS 0x00000004 // Status register\r
+#define CAN_O_ERR 0x00000008 // Error register\r
+#define CAN_O_BIT 0x0000000C // Bit Timing register\r
+#define CAN_O_INT 0x00000010 // Interrupt register\r
+#define CAN_O_TST 0x00000014 // Test register\r
+#define CAN_O_BRPE 0x00000018 // Baud Rate Prescaler register\r
+#define CAN_O_IF1CRQ 0x00000020 // Interface 1 Command Request reg.\r
+#define CAN_O_IF1CMSK 0x00000024 // Interface 1 Command Mask reg.\r
+#define CAN_O_IF1MSK1 0x00000028 // Interface 1 Mask 1 register\r
+#define CAN_O_IF1MSK2 0x0000002C // Interface 1 Mask 2 register\r
+#define CAN_O_IF1ARB1 0x00000030 // Interface 1 Arbitration 1 reg.\r
+#define CAN_O_IF1ARB2 0x00000034 // Interface 1 Arbitration 2 reg.\r
+#define CAN_O_IF1MCTL 0x00000038 // Interface 1 Message Control reg.\r
+#define CAN_O_IF1DA1 0x0000003C // Interface 1 DataA 1 register\r
+#define CAN_O_IF1DA2 0x00000040 // Interface 1 DataA 2 register\r
+#define CAN_O_IF1DB1 0x00000044 // Interface 1 DataB 1 register\r
+#define CAN_O_IF1DB2 0x00000048 // Interface 1 DataB 2 register\r
+#define CAN_O_IF2CRQ 0x00000080 // Interface 2 Command Request reg.\r
+#define CAN_O_IF2CMSK 0x00000084 // Interface 2 Command Mask reg.\r
+#define CAN_O_IF2MSK1 0x00000088 // Interface 2 Mask 1 register\r
+#define CAN_O_IF2MSK2 0x0000008C // Interface 2 Mask 2 register\r
+#define CAN_O_IF2ARB1 0x00000090 // Interface 2 Arbitration 1 reg.\r
+#define CAN_O_IF2ARB2 0x00000094 // Interface 2 Arbitration 2 reg.\r
+#define CAN_O_IF2MCTL 0x00000098 // Interface 2 Message Control reg.\r
+#define CAN_O_IF2DA1 0x0000009C // Interface 2 DataA 1 register\r
+#define CAN_O_IF2DA2 0x000000A0 // Interface 2 DataA 2 register\r
+#define CAN_O_IF2DB1 0x000000A4 // Interface 2 DataB 1 register\r
+#define CAN_O_IF2DB2 0x000000A8 // Interface 2 DataB 2 register\r
+#define CAN_O_TXRQ1 0x00000100 // Transmission Request 1 register\r
+#define CAN_O_TXRQ2 0x00000104 // Transmission Request 2 register\r
+#define CAN_O_NWDA1 0x00000120 // New Data 1 register\r
+#define CAN_O_NWDA2 0x00000124 // New Data 2 register\r
+#define CAN_O_MSGINT1 0x00000140 // Intr. Pending in Msg Obj 1 reg.\r
+#define CAN_O_MSGINT2 0x00000144 // Intr. Pending in Msg Obj 2 reg.\r
+#define CAN_O_MSGVAL1 0x00000160 // Message Valid in Msg Obj 1 reg.\r
+#define CAN_O_MSGVAL2 0x00000164 // Message Valid in Msg Obj 2 reg.\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the reset values of the can registers.\r
+//\r
+//*****************************************************************************\r
+#define CAN_RV_CTL 0x00000001\r
+#define CAN_RV_STS 0x00000000\r
+#define CAN_RV_ERR 0x00000000\r
+#define CAN_RV_BIT 0x00002301\r
+#define CAN_RV_INT 0x00000000\r
+#define CAN_RV_TST 0x00000000\r
+#define CAN_RV_BRPE 0x00000000\r
+#define CAN_RV_IF1CRQ 0x00000001\r
+#define CAN_RV_IF1CMSK 0x00000000\r
+#define CAN_RV_IF1MSK1 0x0000FFFF\r
+#define CAN_RV_IF1MSK2 0x0000FFFF\r
+#define CAN_RV_IF1ARB1 0x00000000\r
+#define CAN_RV_IF1ARB2 0x00000000\r
+#define CAN_RV_IF1MCTL 0x00000000\r
+#define CAN_RV_IF1DA1 0x00000000\r
+#define CAN_RV_IF1DA2 0x00000000\r
+#define CAN_RV_IF1DB1 0x00000000\r
+#define CAN_RV_IF1DB2 0x00000000\r
+#define CAN_RV_IF2CRQ 0x00000001\r
+#define CAN_RV_IF2CMSK 0x00000000\r
+#define CAN_RV_IF2MSK1 0x0000FFFF\r
+#define CAN_RV_IF2MSK2 0x0000FFFF\r
+#define CAN_RV_IF2ARB1 0x00000000\r
+#define CAN_RV_IF2ARB2 0x00000000\r
+#define CAN_RV_IF2MCTL 0x00000000\r
+#define CAN_RV_IF2DA1 0x00000000\r
+#define CAN_RV_IF2DA2 0x00000000\r
+#define CAN_RV_IF2DB1 0x00000000\r
+#define CAN_RV_IF2DB2 0x00000000\r
+#define CAN_RV_TXRQ1 0x00000000\r
+#define CAN_RV_TXRQ2 0x00000000\r
+#define CAN_RV_NWDA1 0x00000000\r
+#define CAN_RV_NWDA2 0x00000000\r
+#define CAN_RV_MSGINT1 0x00000000\r
+#define CAN_RV_MSGINT2 0x00000000\r
+#define CAN_RV_MSGVAL1 0x00000000\r
+#define CAN_RV_MSGVAL2 0x00000000\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the CAN_CTL register.\r
+//\r
+//*****************************************************************************\r
+#define CAN_CTL_TEST 0x00000080 // Test mode enable\r
+#define CAN_CTL_CCE 0x00000040 // Configuration change enable\r
+#define CAN_CTL_DAR 0x00000020 // Disable automatic retransmission\r
+#define CAN_CTL_EIE 0x00000008 // Error interrupt enable\r
+#define CAN_CTL_SIE 0x00000004 // Status change interrupt enable\r
+#define CAN_CTL_IE 0x00000002 // Module interrupt enable\r
+#define CAN_CTL_INIT 0x00000001 // Initialization\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the CAN_STS register.\r
+//\r
+//*****************************************************************************\r
+#define CAN_STS_BOFF 0x00000080 // Bus Off status\r
+#define CAN_STS_EWARN 0x00000040 // Error Warning status\r
+#define CAN_STS_EPASS 0x00000020 // Error Passive status\r
+#define CAN_STS_RXOK 0x00000010 // Received Message Successful\r
+#define CAN_STS_TXOK 0x00000008 // Transmitted Message Successful\r
+#define CAN_STS_LEC_MSK 0x00000007 // Last Error Code\r
+#define CAN_STS_LEC_NONE 0x00000000 // No error\r
+#define CAN_STS_LEC_STUFF 0x00000001 // Stuff error\r
+#define CAN_STS_LEC_FORM 0x00000002 // Form(at) error\r
+#define CAN_STS_LEC_ACK 0x00000003 // Ack error\r
+#define CAN_STS_LEC_BIT1 0x00000004 // Bit 1 error\r
+#define CAN_STS_LEC_BIT0 0x00000005 // Bit 0 error\r
+#define CAN_STS_LEC_CRC 0x00000006 // CRC error\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the CAN_ERR register.\r
+//\r
+//*****************************************************************************\r
+#define CAN_ERR_RP 0x00008000 // Receive error passive status\r
+#define CAN_ERR_REC_MASK 0x00007F00 // Receive error counter status\r
+#define CAN_ERR_REC_SHIFT 8 // Receive error counter bit pos\r
+#define CAN_ERR_TEC_MASK 0x000000FF // Transmit error counter status\r
+#define CAN_ERR_TEC_SHIFT 0 // Transmit error counter bit pos\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the CAN_BIT register.\r
+//\r
+//*****************************************************************************\r
+#define CAN_BIT_TSEG2 0x00007000 // Time segment after sample point\r
+#define CAN_BIT_TSEG1 0x00000F00 // Time segment before sample point\r
+#define CAN_BIT_SJW 0x000000C0 // (Re)Synchronization jump width\r
+#define CAN_BIT_BRP 0x0000003F // Baud rate prescaler\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the CAN_INT register.\r
+//\r
+//*****************************************************************************\r
+#define CAN_INT_INTID_MSK 0x0000FFFF // Interrupt Identifier\r
+#define CAN_INT_INTID_NONE 0x00000000 // No Interrupt Pending\r
+#define CAN_INT_INTID_STATUS 0x00008000 // Status Interrupt\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the CAN_TST register.\r
+//\r
+//*****************************************************************************\r
+#define CAN_TST_RX 0x00000080 // CAN_RX pin status\r
+#define CAN_TST_TX_MSK 0x00000060 // Overide control of CAN_TX pin\r
+#define CAN_TST_TX_CANCTL 0x00000000 // CAN core controls CAN_TX\r
+#define CAN_TST_TX_SAMPLE 0x00000020 // Sample Point on CAN_TX\r
+#define CAN_TST_TX_DOMINANT 0x00000040 // Dominant value on CAN_TX\r
+#define CAN_TST_TX_RECESSIVE 0x00000060 // Recessive value on CAN_TX\r
+#define CAN_TST_LBACK 0x00000010 // Loop back mode\r
+#define CAN_TST_SILENT 0x00000008 // Silent mode\r
+#define CAN_TST_BASIC 0x00000004 // Basic mode\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the CAN_BRPE register.\r
+//\r
+//*****************************************************************************\r
+#define CAN_BRPE_BRPE 0x0000000F // Baud rate prescaler extension\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the CAN_IF1CRQ and CAN_IF1CRQ\r
+// registers.\r
+// Note: All bits may not be available in all registers\r
+//\r
+//*****************************************************************************\r
+#define CAN_IFCRQ_BUSY 0x00008000 // Busy flag status\r
+#define CAN_IFCRQ_MNUM_MSK 0x0000003F // Message Number\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the CAN_IF1CMSK and CAN_IF2CMSK\r
+// registers.\r
+// Note: All bits may not be available in all registers\r
+//\r
+//*****************************************************************************\r
+#define CAN_IFCMSK_WRNRD 0x00000080 // Write, not Read\r
+#define CAN_IFCMSK_MASK 0x00000040 // Access Mask Bits\r
+#define CAN_IFCMSK_ARB 0x00000020 // Access Arbitration Bits\r
+#define CAN_IFCMSK_CONTROL 0x00000010 // Access Control Bits\r
+#define CAN_IFCMSK_CLRINTPND 0x00000008 // Clear interrupt pending Bit\r
+#define CAN_IFCMSK_TXRQST 0x00000004 // Access Tx request bit (WRNRD=1)\r
+#define CAN_IFCMSK_NEWDAT 0x00000004 // Access New Data bit (WRNRD=0)\r
+#define CAN_IFCMSK_DATAA 0x00000002 // DataA access - bytes 0 to 3\r
+#define CAN_IFCMSK_DATAB 0x00000001 // DataB access - bytes 4 to 7\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the CAN_IF1MSK1 and CAN_IF2MSK1\r
+// registers.\r
+// Note: All bits may not be available in all registers\r
+//\r
+//*****************************************************************************\r
+#define CAN_IFMSK1_MSK 0x0000FFFF // Identifier Mask\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the CAN_IF1MSK2 and CAN_IF2MSK2\r
+// registers.\r
+// Note: All bits may not be available in all registers\r
+//\r
+//*****************************************************************************\r
+#define CAN_IFMSK2_MXTD 0x00008000 // Mask extended identifier\r
+#define CAN_IFMSK2_MDIR 0x00004000 // Mask message direction\r
+#define CAN_IFMSK2_MSK 0x00001FFF // Mask identifier\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the CAN_IF1ARB1 and CAN_IF2ARB1\r
+// registers.\r
+// Note: All bits may not be available in all registers\r
+//\r
+//*****************************************************************************\r
+#define CAN_IFARB1_ID 0x0000FFFF // Identifier\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the CAN_IF1ARB2 and CAN_IF2ARB2\r
+// registers.\r
+// Note: All bits may not be available in all registers\r
+//\r
+//*****************************************************************************\r
+#define CAN_IFARB2_MSGVAL 0x00008000 // Message valid\r
+#define CAN_IFARB2_XTD 0x00004000 // Extended identifier\r
+#define CAN_IFARB2_DIR 0x00002000 // Message direction\r
+#define CAN_IFARB2_ID 0x00001FFF // Message identifier\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the CAN_IF1MCTL and CAN_IF2MCTL\r
+// registers.\r
+// Note: All bits may not be available in all registers\r
+//\r
+//*****************************************************************************\r
+#define CAN_IFMCTL_NEWDAT 0x00008000 // New Data\r
+#define CAN_IFMCTL_MSGLST 0x00004000 // Message lost\r
+#define CAN_IFMCTL_INTPND 0x00002000 // Interrupt pending\r
+#define CAN_IFMCTL_UMASK 0x00001000 // Use acceptance mask\r
+#define CAN_IFMCTL_TXIE 0x00000800 // Transmit interrupt enable\r
+#define CAN_IFMCTL_RXIE 0x00000400 // Receive interrupt enable\r
+#define CAN_IFMCTL_RMTEN 0x00000200 // Remote enable\r
+#define CAN_IFMCTL_TXRQST 0x00000100 // Transmit request\r
+#define CAN_IFMCTL_EOB 0x00000080 // End of buffer\r
+#define CAN_IFMCTL_DLC 0x0000000F // Data length code\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the CAN_IF1DA1 and CAN_IF2DA1\r
+// registers.\r
+// Note: All bits may not be available in all registers\r
+//\r
+//*****************************************************************************\r
+#define CAN_IFDA1_DATA 0x0000FFFF // Data - bytes 1 and 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the CAN_IF1DA2 and CAN_IF2DA2\r
+// registers.\r
+// Note: All bits may not be available in all registers\r
+//\r
+//*****************************************************************************\r
+#define CAN_IFDA2_DATA 0x0000FFFF // Data - bytes 3 and 2\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the CAN_IF1DB1 and CAN_IF2DB1\r
+// registers.\r
+// Note: All bits may not be available in all registers\r
+//\r
+//*****************************************************************************\r
+#define CAN_IFDB1_DATA 0x0000FFFF // Data - bytes 5 and 4\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the CAN_IF1DB2 and CAN_IF2DB2\r
+// registers.\r
+// Note: All bits may not be available in all registers\r
+//\r
+//*****************************************************************************\r
+#define CAN_IFDB2_DATA 0x0000FFFF // Data - bytes 7 and 6\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the CAN_TXRQ1 register.\r
+//\r
+//*****************************************************************************\r
+#define CAN_TXRQ1_TXRQST 0x0000FFFF // Transmission Request Bits\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the CAN_TXRQ2 register.\r
+//\r
+//*****************************************************************************\r
+#define CAN_TXRQ2_TXRQST 0x0000FFFF // Transmission Request Bits\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the CAN_NWDA1 register.\r
+//\r
+//*****************************************************************************\r
+#define CAN_NWDA1_NEWDATA 0x0000FFFF // New Data Bits\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the CAN_NWDA2 register.\r
+//\r
+//*****************************************************************************\r
+#define CAN_NWDA2_NEWDATA 0x0000FFFF // New Data Bits\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the CAN_MSGINT1 register.\r
+//\r
+//*****************************************************************************\r
+#define CAN_MSGINT1_INTPND 0x0000FFFF // Interrupt Pending Bits\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the CAN_MSGINT2 register.\r
+//\r
+//*****************************************************************************\r
+#define CAN_MSGINT2_INTPND 0x0000FFFF // Interrupt Pending Bits\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the CAN_MSGVAL1 register.\r
+//\r
+//*****************************************************************************\r
+#define CAN_MSGVAL1_MSGVAL 0x0000FFFF // Message Valid Bits\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the CAN_MSGVAL2 register.\r
+//\r
+//*****************************************************************************\r
+#define CAN_MSGVAL2_MSGVAL 0x0000FFFF // Message Valid Bits\r
+\r
+#endif // __HW_CAN_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_comp.h - Macros used when accessing the comparator hardware.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_COMP_H__\r
+#define __HW_COMP_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the offsets of the comparator registers.\r
+//\r
+//*****************************************************************************\r
+#define COMP_O_MIS 0x00000000 // Interrupt status register\r
+#define COMP_O_RIS 0x00000004 // Raw interrupt status register\r
+#define COMP_O_INTEN 0x00000008 // Interrupt enable register\r
+#define COMP_O_REFCTL 0x00000010 // Reference voltage control reg.\r
+#define COMP_O_ACSTAT0 0x00000020 // Comp0 status register\r
+#define COMP_O_ACCTL0 0x00000024 // Comp0 control register\r
+#define COMP_O_ACSTAT1 0x00000040 // Comp1 status register\r
+#define COMP_O_ACCTL1 0x00000044 // Comp1 control register\r
+#define COMP_O_ACSTAT2 0x00000060 // Comp2 status register\r
+#define COMP_O_ACCTL2 0x00000064 // Comp2 control register\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the COMP_MIS, COMP_RIS, and\r
+// COMP_INTEN registers.\r
+//\r
+//*****************************************************************************\r
+#define COMP_INT_2 0x00000004 // Comp2 interrupt\r
+#define COMP_INT_1 0x00000002 // Comp1 interrupt\r
+#define COMP_INT_0 0x00000001 // Comp0 interrupt\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the COMP_REFCTL register.\r
+//\r
+//*****************************************************************************\r
+#define COMP_REFCTL_EN 0x00000200 // Reference voltage enable\r
+#define COMP_REFCTL_RNG 0x00000100 // Reference voltage range\r
+#define COMP_REFCTL_VREF_MASK 0x0000000F // Reference voltage select mask\r
+#define COMP_REFCTL_VREF_SHIFT 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the COMP_ACSTAT0, COMP_ACSTAT1, and\r
+// COMP_ACSTAT2 registers.\r
+//\r
+//*****************************************************************************\r
+#define COMP_ACSTAT_OVAL 0x00000002 // Comparator output value\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the COMP_ACCTL0, COMP_ACCTL1, and\r
+// COMP_ACCTL2 registers.\r
+//\r
+//*****************************************************************************\r
+#define COMP_ACCTL_TMASK 0x00000800 // Trigger enable\r
+#define COMP_ACCTL_ASRCP_MASK 0x00000600 // Vin+ source select mask\r
+#define COMP_ACCTL_ASRCP_PIN 0x00000000 // Dedicated Comp+ pin\r
+#define COMP_ACCTL_ASRCP_PIN0 0x00000200 // Comp0+ pin\r
+#define COMP_ACCTL_ASRCP_REF 0x00000400 // Internal voltage reference\r
+#define COMP_ACCTL_ASRCP_RES 0x00000600 // Reserved\r
+#define COMP_ACCTL_OEN 0x00000100 // Comparator output enable\r
+#define COMP_ACCTL_TSVAL 0x00000080 // Trigger polarity select\r
+#define COMP_ACCTL_TSEN_MASK 0x00000060 // Trigger sense mask\r
+#define COMP_ACCTL_TSEN_LEVEL 0x00000000 // Trigger is level sense\r
+#define COMP_ACCTL_TSEN_FALL 0x00000020 // Trigger is falling edge\r
+#define COMP_ACCTL_TSEN_RISE 0x00000040 // Trigger is rising edge\r
+#define COMP_ACCTL_TSEN_BOTH 0x00000060 // Trigger is both edges\r
+#define COMP_ACCTL_ISLVAL 0x00000010 // Interrupt polarity select\r
+#define COMP_ACCTL_ISEN_MASK 0x0000000C // Interrupt sense mask\r
+#define COMP_ACCTL_ISEN_LEVEL 0x00000000 // Interrupt is level sense\r
+#define COMP_ACCTL_ISEN_FALL 0x00000004 // Interrupt is falling edge\r
+#define COMP_ACCTL_ISEN_RISE 0x00000008 // Interrupt is rising edge\r
+#define COMP_ACCTL_ISEN_BOTH 0x0000000C // Interrupt is both edges\r
+#define COMP_ACCTL_CINV 0x00000002 // Comparator output invert\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the reset values for the comparator registers.\r
+//\r
+//*****************************************************************************\r
+#define COMP_RV_MIS 0x00000000 // Interrupt status register\r
+#define COMP_RV_RIS 0x00000000 // Raw interrupt status register\r
+#define COMP_RV_INTEN 0x00000000 // Interrupt enable register\r
+#define COMP_RV_REFCTL 0x00000000 // Reference voltage control reg.\r
+#define COMP_RV_ACSTAT0 0x00000000 // Comp0 status register\r
+#define COMP_RV_ACCTL0 0x00000000 // Comp0 control register\r
+#define COMP_RV_ACSTAT1 0x00000000 // Comp1 status register\r
+#define COMP_RV_ACCTL1 0x00000000 // Comp1 control register\r
+#define COMP_RV_ACSTAT2 0x00000000 // Comp2 status register\r
+#define COMP_RV_ACCTL2 0x00000000 // Comp2 control register\r
+\r
+#endif // __HW_COMP_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_ethernet.h - Macros used when accessing the ethernet hardware.\r
+//\r
+// Copyright (c) 2006-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_ETHERNET_H__\r
+#define __HW_ETHERNET_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the offsets of the MAC registers in the Ethernet\r
+// Controller.\r
+//\r
+//*****************************************************************************\r
+#define MAC_O_IS 0x00000000 // Interrupt Status Register\r
+#define MAC_O_IACK 0x00000000 // Interrupt Acknowledge Register\r
+#define MAC_O_IM 0x00000004 // Interrupt Mask Register\r
+#define MAC_O_RCTL 0x00000008 // Receive Control Register\r
+#define MAC_O_TCTL 0x0000000C // Transmit Control Register\r
+#define MAC_O_DATA 0x00000010 // Data Register\r
+#define MAC_O_IA0 0x00000014 // Individual Address Register 0\r
+#define MAC_O_IA1 0x00000018 // Individual Address Register 1\r
+#define MAC_O_THR 0x0000001C // Threshold Register\r
+#define MAC_O_MCTL 0x00000020 // Management Control Register\r
+#define MAC_O_MDV 0x00000024 // Management Divider Register\r
+#define MAC_O_MADD 0x00000028 // Management Address Register\r
+#define MAC_O_MTXD 0x0000002C // Management Transmit Data Reg\r
+#define MAC_O_MRXD 0x00000030 // Management Receive Data Reg\r
+#define MAC_O_NP 0x00000034 // Number of Packets Register\r
+#define MAC_O_TR 0x00000038 // Transmission Request Register\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the reset values of the MAC registers.\r
+//\r
+//*****************************************************************************\r
+#define MAC_RV_IS 0x00000000\r
+#define MAC_RV_IACK 0x00000000\r
+#define MAC_RV_IM 0x0000007F\r
+#define MAC_RV_RCTL 0x00000008\r
+#define MAC_RV_TCTL 0x00000000\r
+#define MAC_RV_DATA 0x00000000\r
+#define MAC_RV_IA0 0x00000000\r
+#define MAC_RV_IA1 0x00000000\r
+#define MAC_RV_THR 0x0000003F\r
+#define MAC_RV_MCTL 0x00000000\r
+#define MAC_RV_MDV 0x00000080\r
+#define MAC_RV_MADD 0x00000000\r
+#define MAC_RV_MTXD 0x00000000\r
+#define MAC_RV_MRXD 0x00000000\r
+#define MAC_RV_NP 0x00000000\r
+#define MAC_RV_TR 0x00000000\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the MAC_IS register.\r
+//\r
+//*****************************************************************************\r
+#define MAC_IS_PHYINT 0x00000040 // PHY Interrupt\r
+#define MAC_IS_MDINT 0x00000020 // MDI Transaction Complete\r
+#define MAC_IS_RXER 0x00000010 // RX Error\r
+#define MAC_IS_FOV 0x00000008 // RX FIFO Overrun\r
+#define MAC_IS_TXEMP 0x00000004 // TX FIFO Empy\r
+#define MAC_IS_TXER 0x00000002 // TX Error\r
+#define MAC_IS_RXINT 0x00000001 // RX Packet Available\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the MAC_IACK register.\r
+//\r
+//*****************************************************************************\r
+#define MAC_IACK_PHYINT 0x00000040 // Clear PHY Interrupt\r
+#define MAC_IACK_MDINT 0x00000020 // Clear MDI Transaction Complete\r
+#define MAC_IACK_RXER 0x00000010 // Clear RX Error\r
+#define MAC_IACK_FOV 0x00000008 // Clear RX FIFO Overrun\r
+#define MAC_IACK_TXEMP 0x00000004 // Clear TX FIFO Empy\r
+#define MAC_IACK_TXER 0x00000002 // Clear TX Error\r
+#define MAC_IACK_RXINT 0x00000001 // Clear RX Packet Available\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the MAC_IM register.\r
+//\r
+//*****************************************************************************\r
+#define MAC_IM_PHYINTM 0x00000040 // Mask PHY Interrupt\r
+#define MAC_IM_MDINTM 0x00000020 // Mask MDI Transaction Complete\r
+#define MAC_IM_RXERM 0x00000010 // Mask RX Error\r
+#define MAC_IM_FOVM 0x00000008 // Mask RX FIFO Overrun\r
+#define MAC_IM_TXEMPM 0x00000004 // Mask TX FIFO Empy\r
+#define MAC_IM_TXERM 0x00000002 // Mask TX Error\r
+#define MAC_IM_RXINTM 0x00000001 // Mask RX Packet Available\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the MAC_RCTL register.\r
+//\r
+//*****************************************************************************\r
+#define MAC_RCTL_RSTFIFO 0x00000010 // Clear the Receive FIFO\r
+#define MAC_RCTL_BADCRC 0x00000008 // Reject Packets With Bad CRC\r
+#define MAC_RCTL_PRMS 0x00000004 // Enable Promiscuous Mode\r
+#define MAC_RCTL_AMUL 0x00000002 // Enable Multicast Packets\r
+#define MAC_RCTL_RXEN 0x00000001 // Enable Ethernet Receiver\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the MAC_TCTL register.\r
+//\r
+//*****************************************************************************\r
+#define MAC_TCTL_DUPLEX 0x00000010 // Enable Duplex mode\r
+#define MAC_TCTL_CRC 0x00000004 // Enable CRC Generation\r
+#define MAC_TCTL_PADEN 0x00000002 // Enable Automatic Padding\r
+#define MAC_TCTL_TXEN 0x00000001 // Enable Ethernet Transmitter\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the MAC_IA0 register.\r
+//\r
+//*****************************************************************************\r
+#define MAC_IA0_MACOCT4 0xFF000000 // 4th Octet of MAC address\r
+#define MAC_IA0_MACOCT3 0x00FF0000 // 3rd Octet of MAC address\r
+#define MAC_IA0_MACOCT2 0x0000FF00 // 2nd Octet of MAC address\r
+#define MAC_IA0_MACOCT1 0x000000FF // 1st Octet of MAC address\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the MAC_IA1 register.\r
+//\r
+//*****************************************************************************\r
+#define MAC_IA1_MACOCT6 0x0000FF00 // 6th Octet of MAC address\r
+#define MAC_IA1_MACOCT5 0x000000FF // 5th Octet of MAC address\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the MAC_TXTH register.\r
+//\r
+//*****************************************************************************\r
+#define MAC_THR_THRESH 0x0000003F // Transmit Threshold Value\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the MAC_MCTL register.\r
+//\r
+//*****************************************************************************\r
+#define MAC_MCTL_REGADR 0x000000F8 // Address for Next MII Transaction\r
+#define MAC_MCTL_WRITE 0x00000002 // Next MII Transaction is Write\r
+#define MAC_MCTL_START 0x00000001 // Start MII Transaction\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the MAC_MDV register.\r
+//\r
+//*****************************************************************************\r
+#define MAC_MDV_DIV 0x000000FF // Clock Divider for MDC for TX\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the MAC_MTXD register.\r
+//\r
+//*****************************************************************************\r
+#define MAC_MTXD_MDTX 0x0000FFFF // Data for Next MII Transaction\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the MAC_MRXD register.\r
+//\r
+//*****************************************************************************\r
+#define MAC_MRXD_MDRX 0x0000FFFF // Data Read from Last MII Trans.\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the MAC_NP register.\r
+//\r
+//*****************************************************************************\r
+#define MAC_NP_NPR 0x0000003F // Number of RX Frames in FIFO\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the MAC_TXRQ register.\r
+//\r
+//*****************************************************************************\r
+#define MAC_TR_NEWTX 0x00000001 // Start an Ethernet Transmission\r
+\r
+#endif // __HW_ETHERNET_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_flash.h - Macros used when accessing the flash controller.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_FLASH_H__\r
+#define __HW_FLASH_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the offsets of the FLASH registers.\r
+//\r
+//*****************************************************************************\r
+#define FLASH_FMA 0x400FD000 // Memory address register\r
+#define FLASH_FMD 0x400FD004 // Memory data register\r
+#define FLASH_FMC 0x400FD008 // Memory control register\r
+#define FLASH_FCRIS 0x400FD00c // Raw interrupt status register\r
+#define FLASH_FCIM 0x400FD010 // Interrupt mask register\r
+#define FLASH_FCMISC 0x400FD014 // Interrupt status register\r
+#define FLASH_FMPRE 0x400FE130 // FLASH read protect register\r
+#define FLASH_FMPPE 0x400FE134 // FLASH program protect register\r
+#define FLASH_USECRL 0x400FE140 // uSec reload register\r
+#define FLASH_FMPRE0 0x400FE200 // FLASH read protect register 0\r
+#define FLASH_FMPRE1 0x400FE204 // FLASH read protect register 1\r
+#define FLASH_FMPRE2 0x400FE208 // FLASH read protect register 2\r
+#define FLASH_FMPRE3 0x400FE20C // FLASH read protect register 3\r
+#define FLASH_FMPPE0 0x400FE400 // FLASH program protect register 0\r
+#define FLASH_FMPPE1 0x400FE404 // FLASH program protect register 1\r
+#define FLASH_FMPPE2 0x400FE408 // FLASH program protect register 2\r
+#define FLASH_FMPPE3 0x400FE40C // FLASH program protect register 3\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the FLASH_FMC register.\r
+//\r
+//*****************************************************************************\r
+#define FLASH_FMC_WRKEY_MASK 0xFFFF0000 // FLASH write key mask\r
+#define FLASH_FMC_WRKEY 0xA4420000 // FLASH write key\r
+#define FLASH_FMC_COMT 0x00000008 // Commit user register\r
+#define FLASH_FMC_MERASE 0x00000004 // Mass erase FLASH\r
+#define FLASH_FMC_ERASE 0x00000002 // Erase FLASH page\r
+#define FLASH_FMC_WRITE 0x00000001 // Write FLASH word\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the FLASH_FCRIS register.\r
+//\r
+//*****************************************************************************\r
+#define FLASH_FCRIS_PROGRAM 0x00000002 // Programming status\r
+#define FLASH_FCRIS_ACCESS 0x00000001 // Invalid access status\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the FLASH_FCIM register.\r
+//\r
+//*****************************************************************************\r
+#define FLASH_FCIM_PROGRAM 0x00000002 // Programming mask\r
+#define FLASH_FCIM_ACCESS 0x00000001 // Invalid access mask\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the FLASH_FMIS register.\r
+//\r
+//*****************************************************************************\r
+#define FLASH_FCMISC_PROGRAM 0x00000002 // Programming status\r
+#define FLASH_FCMISC_ACCESS 0x00000001 // Invalid access status\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the FLASH_FMPRE and FLASH_FMPPE\r
+// registers.\r
+//\r
+//*****************************************************************************\r
+#define FLASH_FMP_BLOCK_31 0x80000000 // Enable for block 31\r
+#define FLASH_FMP_BLOCK_30 0x40000000 // Enable for block 30\r
+#define FLASH_FMP_BLOCK_29 0x20000000 // Enable for block 29\r
+#define FLASH_FMP_BLOCK_28 0x10000000 // Enable for block 28\r
+#define FLASH_FMP_BLOCK_27 0x08000000 // Enable for block 27\r
+#define FLASH_FMP_BLOCK_26 0x04000000 // Enable for block 26\r
+#define FLASH_FMP_BLOCK_25 0x02000000 // Enable for block 25\r
+#define FLASH_FMP_BLOCK_24 0x01000000 // Enable for block 24\r
+#define FLASH_FMP_BLOCK_23 0x00800000 // Enable for block 23\r
+#define FLASH_FMP_BLOCK_22 0x00400000 // Enable for block 22\r
+#define FLASH_FMP_BLOCK_21 0x00200000 // Enable for block 21\r
+#define FLASH_FMP_BLOCK_20 0x00100000 // Enable for block 20\r
+#define FLASH_FMP_BLOCK_19 0x00080000 // Enable for block 19\r
+#define FLASH_FMP_BLOCK_18 0x00040000 // Enable for block 18\r
+#define FLASH_FMP_BLOCK_17 0x00020000 // Enable for block 17\r
+#define FLASH_FMP_BLOCK_16 0x00010000 // Enable for block 16\r
+#define FLASH_FMP_BLOCK_15 0x00008000 // Enable for block 15\r
+#define FLASH_FMP_BLOCK_14 0x00004000 // Enable for block 14\r
+#define FLASH_FMP_BLOCK_13 0x00002000 // Enable for block 13\r
+#define FLASH_FMP_BLOCK_12 0x00001000 // Enable for block 12\r
+#define FLASH_FMP_BLOCK_11 0x00000800 // Enable for block 11\r
+#define FLASH_FMP_BLOCK_10 0x00000400 // Enable for block 10\r
+#define FLASH_FMP_BLOCK_9 0x00000200 // Enable for block 9\r
+#define FLASH_FMP_BLOCK_8 0x00000100 // Enable for block 8\r
+#define FLASH_FMP_BLOCK_7 0x00000080 // Enable for block 7\r
+#define FLASH_FMP_BLOCK_6 0x00000040 // Enable for block 6\r
+#define FLASH_FMP_BLOCK_5 0x00000020 // Enable for block 5\r
+#define FLASH_FMP_BLOCK_4 0x00000010 // Enable for block 4\r
+#define FLASH_FMP_BLOCK_3 0x00000008 // Enable for block 3\r
+#define FLASH_FMP_BLOCK_2 0x00000004 // Enable for block 2\r
+#define FLASH_FMP_BLOCK_1 0x00000002 // Enable for block 1\r
+#define FLASH_FMP_BLOCK_0 0x00000001 // Enable for block 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the FLASH_USECRL register.\r
+//\r
+//*****************************************************************************\r
+#define FLASH_USECRL_MASK 0x000000FF // Clock per uSec\r
+#define FLASH_USECRL_SHIFT 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The erase size is the size of the FLASH block that is erased by an erase\r
+// operation, and the protect size is the size of the FLASH block that is\r
+// protected by each protection register.\r
+//\r
+//*****************************************************************************\r
+#define FLASH_ERASE_SIZE 0x00000400\r
+#define FLASH_PROTECT_SIZE 0x00000800\r
+\r
+#endif // __HW_FLASH_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_gpio.h - Defines and Macros for GPIO hardware.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_GPIO_H__\r
+#define __HW_GPIO_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// GPIO Register Offsets.\r
+//\r
+//*****************************************************************************\r
+#define GPIO_O_DATA 0x00000000 // Data register.\r
+#define GPIO_O_DIR 0x00000400 // Data direction register.\r
+#define GPIO_O_IS 0x00000404 // Interrupt sense register.\r
+#define GPIO_O_IBE 0x00000408 // Interrupt both edges register.\r
+#define GPIO_O_IEV 0x0000040C // Intterupt event register.\r
+#define GPIO_O_IM 0x00000410 // Interrupt mask register.\r
+#define GPIO_O_RIS 0x00000414 // Raw interrupt status register.\r
+#define GPIO_O_MIS 0x00000418 // Masked interrupt status reg.\r
+#define GPIO_O_ICR 0x0000041C // Interrupt clear register.\r
+#define GPIO_O_AFSEL 0x00000420 // Mode control select register.\r
+#define GPIO_O_DR2R 0x00000500 // 2ma drive select register.\r
+#define GPIO_O_DR4R 0x00000504 // 4ma drive select register.\r
+#define GPIO_O_DR8R 0x00000508 // 8ma drive select register.\r
+#define GPIO_O_ODR 0x0000050C // Open drain select register.\r
+#define GPIO_O_PUR 0x00000510 // Pull up select register.\r
+#define GPIO_O_PDR 0x00000514 // Pull down select register.\r
+#define GPIO_O_SLR 0x00000518 // Slew rate control enable reg.\r
+#define GPIO_O_DEN 0x0000051C // Digital input enable register.\r
+#define GPIO_O_LOCK 0x00000520 // Lock register.\r
+#define GPIO_O_CR 0x00000524 // Commit register.\r
+#define GPIO_O_PeriphID4 0x00000FD0 //\r
+#define GPIO_O_PeriphID5 0x00000FD4 //\r
+#define GPIO_O_PeriphID6 0x00000FD8 //\r
+#define GPIO_O_PeriphID7 0x00000FDC //\r
+#define GPIO_O_PeriphID0 0x00000FE0 //\r
+#define GPIO_O_PeriphID1 0x00000FE4 //\r
+#define GPIO_O_PeriphID2 0x00000FE8 //\r
+#define GPIO_O_PeriphID3 0x00000FEC //\r
+#define GPIO_O_PCellID0 0x00000FF0 //\r
+#define GPIO_O_PCellID1 0x00000FF4 //\r
+#define GPIO_O_PCellID2 0x00000FF8 //\r
+#define GPIO_O_PCellID3 0x00000FFC //\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the GPIO_LOCK register.\r
+//\r
+//*****************************************************************************\r
+#define GPIO_LOCK_LOCKED 0x00000001 // GPIO_CR register is locked\r
+#define GPIO_LOCK_UNLOCKED 0x00000000 // GPIO_CR register is unlocked\r
+#define GPIO_LOCK_KEY 0x1ACCE551 // Unlocks the GPIO_CR register\r
+\r
+//*****************************************************************************\r
+//\r
+// GPIO Register reset values.\r
+//\r
+//*****************************************************************************\r
+#define GPIO_RV_DATA 0x00000000 // Data register reset value.\r
+#define GPIO_RV_DIR 0x00000000 // Data direction reg RV.\r
+#define GPIO_RV_IS 0x00000000 // Interrupt sense reg RV.\r
+#define GPIO_RV_IBE 0x00000000 // Interrupt both edges reg RV.\r
+#define GPIO_RV_IEV 0x00000000 // Intterupt event reg RV.\r
+#define GPIO_RV_IM 0x00000000 // Interrupt mask reg RV.\r
+#define GPIO_RV_RIS 0x00000000 // Raw interrupt status reg RV.\r
+#define GPIO_RV_MIS 0x00000000 // Masked interrupt status reg RV.\r
+#define GPIO_RV_IC 0x00000000 // Interrupt clear reg RV.\r
+#define GPIO_RV_AFSEL 0x00000000 // Mode control select reg RV.\r
+#define GPIO_RV_DR2R 0x000000FF // 2ma drive select reg RV.\r
+#define GPIO_RV_DR4R 0x00000000 // 4ma drive select reg RV.\r
+#define GPIO_RV_DR8R 0x00000000 // 8ma drive select reg RV.\r
+#define GPIO_RV_ODR 0x00000000 // Open drain select reg RV.\r
+#define GPIO_RV_PUR 0x000000FF // Pull up select reg RV.\r
+#define GPIO_RV_PDR 0x00000000 // Pull down select reg RV.\r
+#define GPIO_RV_SLR 0x00000000 // Slew rate control enable reg RV.\r
+#define GPIO_RV_DEN 0x000000FF // Digital input enable reg RV.\r
+#define GPIO_RV_LOCK 0x00000001 // Lock register RV.\r
+#define GPIO_RV_PeriphID4 0x00000000 //\r
+#define GPIO_RV_PeriphID5 0x00000000 //\r
+#define GPIO_RV_PeriphID6 0x00000000 //\r
+#define GPIO_RV_PeriphID7 0x00000000 //\r
+#define GPIO_RV_PeriphID0 0x00000061 //\r
+#define GPIO_RV_PeriphID1 0x00000010 //\r
+#define GPIO_RV_PeriphID2 0x00000004 //\r
+#define GPIO_RV_PeriphID3 0x00000000 //\r
+#define GPIO_RV_PCellID0 0x0000000D //\r
+#define GPIO_RV_PCellID1 0x000000F0 //\r
+#define GPIO_RV_PCellID2 0x00000005 //\r
+#define GPIO_RV_PCellID3 0x000000B1 //\r
+\r
+#endif // __HW_GPIO_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_hibernate.h - Defines and Macros for the Hibernation module.\r
+//\r
+// Copyright (c) 2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_HIBERNATE_H__\r
+#define __HW_HIBERNATE_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the addresses of the hibernation module registers.\r
+//\r
+//*****************************************************************************\r
+#define HIB_RTCC 0x400fc000 // Hibernate RTC counter\r
+#define HIB_RTCM0 0x400fc004 // Hibernate RTC match 0\r
+#define HIB_RTCM1 0x400fc008 // Hibernate RTC match 1\r
+#define HIB_RTCLD 0x400fc00C // Hibernate RTC load\r
+#define HIB_CTL 0x400fc010 // Hibernate RTC control\r
+#define HIB_IM 0x400fc014 // Hibernate interrupt mask\r
+#define HIB_RIS 0x400fc018 // Hibernate raw interrupt status\r
+#define HIB_MIS 0x400fc01C // Hibernate masked interrupt stat\r
+#define HIB_IC 0x400fc020 // Hibernate interrupt clear\r
+#define HIB_RTCT 0x400fc024 // Hibernate RTC trim\r
+#define HIB_DATA 0x400fc030 // Hibernate data area\r
+#define HIB_DATA_END 0x400fc130 // end of data area, exclusive\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the Hibernate RTC counter register.\r
+//\r
+//*****************************************************************************\r
+#define HIB_RTCC_MASK 0xffffffff // RTC counter mask\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the Hibernate RTC match 0 register.\r
+//\r
+//*****************************************************************************\r
+#define HIB_RTCM0_MASK 0xffffffff // RTC match 0 mask\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the Hibernate RTC match 1 register.\r
+//\r
+//*****************************************************************************\r
+#define HIB_RTCM1_MASK 0xffffffff // RTC match 1 mask\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the Hibernate RTC load register.\r
+//\r
+//*****************************************************************************\r
+#define HIB_RTCLD_MASK 0xffffffff // RTC load mask\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the Hibernate control register\r
+//\r
+//*****************************************************************************\r
+#define HIB_CTL_VABORT 0x00000080 // low bat abort\r
+#define HIB_CTL_CLK32EN 0x00000040 // enable clock/oscillator\r
+#define HIB_CTL_LOWBATEN 0x00000020 // enable low battery detect\r
+#define HIB_CTL_PINWEN 0x00000010 // enable wake on WAKE pin\r
+#define HIB_CTL_RTCWEN 0x00000008 // enable wake on RTC match\r
+#define HIB_CTL_CLKSEL 0x00000004 // clock input selection\r
+#define HIB_CTL_HIBREQ 0x00000002 // request hibernation\r
+#define HIB_CTL_RTCEN 0x00000001 // RTC enable\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the Hibernate interrupt mask reg.\r
+//\r
+//*****************************************************************************\r
+#define HIB_IM_EXTW 0x00000008 // wake from external pin interrupt\r
+#define HIB_IM_LOWBAT 0x00000004 // low battery interrupt\r
+#define HIB_IM_RTCALT1 0x00000002 // RTC match 1 interrupt\r
+#define HIB_IM_RTCALT0 0x00000001 // RTC match 0 interrupt\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the Hibernate raw interrupt status.\r
+//\r
+//*****************************************************************************\r
+#define HIB_RIS_EXTW 0x00000008 // wake from external pin interrupt\r
+#define HIB_RIS_LOWBAT 0x00000004 // low battery interrupt\r
+#define HIB_RIS_RTCALT1 0x00000002 // RTC match 1 interrupt\r
+#define HIB_RID_RTCALT0 0x00000001 // RTC match 0 interrupt\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the Hibernate masked int status.\r
+//\r
+//*****************************************************************************\r
+#define HIB_MIS_EXTW 0x00000008 // wake from external pin interrupt\r
+#define HIB_MIS_LOWBAT 0x00000004 // low battery interrupt\r
+#define HIB_MIS_RTCALT1 0x00000002 // RTC match 1 interrupt\r
+#define HIB_MID_RTCALT0 0x00000001 // RTC match 0 interrupt\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the Hibernate interrupt clear reg.\r
+//\r
+//*****************************************************************************\r
+#define HIB_IC_EXTW 0x00000008 // wake from external pin interrupt\r
+#define HIB_IC_LOWBAT 0x00000004 // low battery interrupt\r
+#define HIB_IC_RTCALT1 0x00000002 // RTC match 1 interrupt\r
+#define HIB_IC_RTCALT0 0x00000001 // RTC match 0 interrupt\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the Hibernate RTC trim register.\r
+//\r
+//*****************************************************************************\r
+#define HIB_RTCT_MASK 0x0000ffff // RTC trim mask\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the Hibernate data register.\r
+//\r
+//*****************************************************************************\r
+#define HIB_DATA_MASK 0xffffffff // NV memory data mask\r
+\r
+#endif // __HW_HIBERNATE_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_i2c.h - Macros used when accessing the I2C master and slave hardware.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_I2C_H__\r
+#define __HW_I2C_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// The following defines the offset between the I2C master and slave registers.\r
+//\r
+//*****************************************************************************\r
+#define I2C_O_SLAVE 0x00000800 // Offset from master to slave\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the offsets of the I2C master registers.\r
+//\r
+//*****************************************************************************\r
+#define I2C_MASTER_O_SA 0x00000000 // Slave address register\r
+#define I2C_MASTER_O_CS 0x00000004 // Control and Status register\r
+#define I2C_MASTER_O_DR 0x00000008 // Data register\r
+#define I2C_MASTER_O_TPR 0x0000000C // Timer period register\r
+#define I2C_MASTER_O_IMR 0x00000010 // Interrupt mask register\r
+#define I2C_MASTER_O_RIS 0x00000014 // Raw interrupt status register\r
+#define I2C_MASTER_O_MIS 0x00000018 // Masked interrupt status reg\r
+#define I2C_MASTER_O_MICR 0x0000001c // Interrupt clear register\r
+#define I2C_MASTER_O_CR 0x00000020 // Configuration register\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the offsets of the I2C slave registers.\r
+//\r
+//*****************************************************************************\r
+#define I2C_SLAVE_O_OAR 0x00000000 // Own address register\r
+#define I2C_SLAVE_O_CSR 0x00000004 // Control/Status register\r
+#define I2C_SLAVE_O_DR 0x00000008 // Data register\r
+#define I2C_SLAVE_O_IM 0x0000000C // Interrupt mask register\r
+#define I2C_SLAVE_O_RIS 0x00000010 // Raw interrupt status register\r
+#define I2C_SLAVE_O_MIS 0x00000014 // Masked interrupt status reg\r
+#define I2C_SLAVE_O_SICR 0x00000018 // Interrupt clear register\r
+\r
+//*****************************************************************************\r
+//\r
+// The followng define the bit fields in the I2C master slave address register.\r
+//\r
+//*****************************************************************************\r
+#define I2C_MASTER_SA_SA_MASK 0x000000FE // Slave address\r
+#define I2C_MASTER_SA_RS 0x00000001 // Receive/send\r
+#define I2C_MASTER_SA_SA_SHIFT 1\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the I2C Master Control and Status\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define I2C_MASTER_CS_ACK 0x00000008 // Acknowlegde\r
+#define I2C_MASTER_CS_STOP 0x00000004 // Stop\r
+#define I2C_MASTER_CS_START 0x00000002 // Start\r
+#define I2C_MASTER_CS_RUN 0x00000001 // Run\r
+#define I2C_MASTER_CS_BUS_BUSY 0x00000040 // Bus busy\r
+#define I2C_MASTER_CS_IDLE 0x00000020 // Idle\r
+#define I2C_MASTER_CS_ARB_LOST 0x00000010 // Lost arbitration\r
+#define I2C_MASTER_CS_DATA_ACK 0x00000008 // Data byte not acknowledged\r
+#define I2C_MASTER_CS_ADDR_ACK 0x00000004 // Address byte not acknowledged\r
+#define I2C_MASTER_CS_ERROR 0x00000002 // Error occurred\r
+#define I2C_MASTER_CS_BUSY 0x00000001 // Controller is TX/RX data\r
+#define I2C_MASTER_CS_ERR_MASK 0x0000001C\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define values used in determining the contents of the I2C\r
+// Master Timer Period register.\r
+//\r
+//*****************************************************************************\r
+#define I2C_MASTER_TPR_SCL_HP 0x00000004 // SCL high period\r
+#define I2C_MASTER_TPR_SCL_LP 0x00000006 // SCL low period\r
+#define I2C_MASTER_TPR_SCL (I2C_MASTER_TPR_SCL_HP + I2C_MASTER_TPR_SCL_LP)\r
+#define I2C_SCL_STANDARD 100000 // SCL standard frequency\r
+#define I2C_SCL_FAST 400000 // SCL fast frequency\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the I2C Master Interrupt Mask\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define I2C_MASTER_IMR_IM 0x00000001 // Master interrupt mask\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the I2C Master Raw Interrupt Status\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define I2C_MASTER_RIS_RIS 0x00000001 // Master raw interrupt status\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the I2C Master Masked Interrupt\r
+// Status register.\r
+//\r
+//*****************************************************************************\r
+#define I2C_MASTER_MIS_MIS 0x00000001 // Master masked interrupt status\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the I2C Master Interrupt Clear\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define I2C_MASTER_MICR_IC 0x00000001 // Master interrupt clear\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the I2C Master Configuration\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define I2C_MASTER_CR_SFE 0x00000020 // Slave function enable\r
+#define I2C_MASTER_CR_MFE 0x00000010 // Master function enable\r
+#define I2C_MASTER_CR_LPBK 0x00000001 // Loopback enable\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the I2C Slave Own Address register.\r
+//\r
+//*****************************************************************************\r
+#define I2C_SLAVE_SOAR_OAR_MASK 0x0000007F // Slave address\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the I2C Slave Control/Status\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define I2C_SLAVE_CSR_DA 0x00000001 // Enable the device\r
+#define I2C_SLAVE_CSR_TREQ 0x00000002 // Transmit request received\r
+#define I2C_SLAVE_CSR_RREQ 0x00000001 // Receive data from I2C master\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the I2C Slave Interrupt Mask\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define I2C_SLAVE_IMR_IM 0x00000001 // Slave interrupt mask\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the I2C Slave Raw Interrupt Status\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define I2C_SLAVE_RIS_RIS 0x00000001 // Slave raw interrupt status\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the I2C Slave Masked Interrupt\r
+// Status register.\r
+//\r
+//*****************************************************************************\r
+#define I2C_SLAVE_MIS_MIS 0x00000001 // Slave masked interrupt status\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the I2C Slave Interrupt Clear\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define I2C_SLAVE_SICR_IC 0x00000001 // Slave interrupt clear\r
+\r
+#endif // __HW_I2C_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_ints.h - Macros that define the interrupt assignment on Stellaris.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_INTS_H__\r
+#define __HW_INTS_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the fault assignments.\r
+//\r
+//*****************************************************************************\r
+#define FAULT_NMI 2 // NMI fault\r
+#define FAULT_HARD 3 // Hard fault\r
+#define FAULT_MPU 4 // MPU fault\r
+#define FAULT_BUS 5 // Bus fault\r
+#define FAULT_USAGE 6 // Usage fault\r
+#define FAULT_SVCALL 11 // SVCall\r
+#define FAULT_DEBUG 12 // Debug monitor\r
+#define FAULT_PENDSV 14 // PendSV\r
+#define FAULT_SYSTICK 15 // System Tick\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the interrupt assignments.\r
+//\r
+//*****************************************************************************\r
+#define INT_GPIOA 16 // GPIO Port A\r
+#define INT_GPIOB 17 // GPIO Port B\r
+#define INT_GPIOC 18 // GPIO Port C\r
+#define INT_GPIOD 19 // GPIO Port D\r
+#define INT_GPIOE 20 // GPIO Port E\r
+#define INT_UART0 21 // UART0 Rx and Tx\r
+#define INT_UART1 22 // UART1 Rx and Tx\r
+#define INT_SSI 23 // SSI Rx and Tx\r
+#define INT_SSI0 23 // SSI0 Rx and Tx\r
+#define INT_I2C 24 // I2C Master and Slave\r
+#define INT_I2C0 24 // I2C0 Master and Slave\r
+#define INT_PWM_FAULT 25 // PWM Fault\r
+#define INT_PWM0 26 // PWM Generator 0\r
+#define INT_PWM1 27 // PWM Generator 1\r
+#define INT_PWM2 28 // PWM Generator 2\r
+#define INT_QEI 29 // Quadrature Encoder\r
+#define INT_QEI0 29 // Quadrature Encoder 0\r
+#define INT_ADC0 30 // ADC Sequence 0\r
+#define INT_ADC1 31 // ADC Sequence 1\r
+#define INT_ADC2 32 // ADC Sequence 2\r
+#define INT_ADC3 33 // ADC Sequence 3\r
+#define INT_WATCHDOG 34 // Watchdog timer\r
+#define INT_TIMER0A 35 // Timer 0 subtimer A\r
+#define INT_TIMER0B 36 // Timer 0 subtimer B\r
+#define INT_TIMER1A 37 // Timer 1 subtimer A\r
+#define INT_TIMER1B 38 // Timer 1 subtimer B\r
+#define INT_TIMER2A 39 // Timer 2 subtimer A\r
+#define INT_TIMER2B 40 // Timer 2 subtimer B\r
+#define INT_COMP0 41 // Analog Comparator 0\r
+#define INT_COMP1 42 // Analog Comparator 1\r
+#define INT_COMP2 43 // Analog Comparator 2\r
+#define INT_SYSCTL 44 // System Control (PLL, OSC, BO)\r
+#define INT_FLASH 45 // FLASH Control\r
+#define INT_GPIOF 46 // GPIO Port F\r
+#define INT_GPIOG 47 // GPIO Port G\r
+#define INT_GPIOH 48 // GPIO Port H\r
+#define INT_UART2 49 // UART2 Rx and Tx\r
+#define INT_SSI1 50 // SSI1 Rx and Tx\r
+#define INT_TIMER3A 51 // Timer 3 subtimer A\r
+#define INT_TIMER3B 52 // Timer 3 subtimer B\r
+#define INT_I2C1 53 // I2C1 Master and Slave\r
+#define INT_QEI1 54 // Quadrature Encoder 1\r
+#define INT_CAN0 55 // CAN0\r
+#define INT_CAN1 56 // CAN1\r
+#define INT_ETH 58 // Ethernet\r
+#define INT_HIBERNATE 59 // Hibernation module\r
+\r
+//*****************************************************************************\r
+//\r
+// The total number of interrupts.\r
+//\r
+//*****************************************************************************\r
+#define NUM_INTERRUPTS 60\r
+\r
+//*****************************************************************************\r
+//\r
+// The total number of priority levels.\r
+//\r
+//*****************************************************************************\r
+#define NUM_PRIORITY 8\r
+#define NUM_PRIORITY_BITS 3\r
+\r
+#endif // __HW_INTS_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_memmap.h - Macros defining the memory map of Stellaris.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_MEMMAP_H__\r
+#define __HW_MEMMAP_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the base address of the memories and peripherals.\r
+//\r
+//*****************************************************************************\r
+#define FLASH_BASE 0x00000000 // FLASH memory\r
+#define SRAM_BASE 0x20000000 // SRAM memory\r
+#define WATCHDOG_BASE 0x40000000 // Watchdog\r
+#define GPIO_PORTA_BASE 0x40004000 // GPIO Port A\r
+#define GPIO_PORTB_BASE 0x40005000 // GPIO Port B\r
+#define GPIO_PORTC_BASE 0x40006000 // GPIO Port C\r
+#define GPIO_PORTD_BASE 0x40007000 // GPIO Port D\r
+#define SSI_BASE 0x40008000 // SSI\r
+#define SSI0_BASE 0x40008000 // SSI0\r
+#define SSI1_BASE 0x40009000 // SSI1\r
+#define UART0_BASE 0x4000C000 // UART0\r
+#define UART1_BASE 0x4000D000 // UART1\r
+#define UART2_BASE 0x4000E000 // UART2\r
+#define I2C_MASTER_BASE 0x40020000 // I2C Master\r
+#define I2C_SLAVE_BASE 0x40020800 // I2C Slave\r
+#define I2C0_MASTER_BASE 0x40020000 // I2C0 Master\r
+#define I2C0_SLAVE_BASE 0x40020800 // I2C0 Slave\r
+#define I2C1_MASTER_BASE 0x40021000 // I2C1 Master\r
+#define I2C1_SLAVE_BASE 0x40021800 // I2C1 Slave\r
+#define GPIO_PORTE_BASE 0x40024000 // GPIO Port E\r
+#define GPIO_PORTF_BASE 0x40025000 // GPIO Port F\r
+#define GPIO_PORTG_BASE 0x40026000 // GPIO Port G\r
+#define GPIO_PORTH_BASE 0x40027000 // GPIO Port H\r
+#define PWM_BASE 0x40028000 // PWM\r
+#define QEI_BASE 0x4002C000 // QEI\r
+#define QEI0_BASE 0x4002C000 // QEI0\r
+#define QEI1_BASE 0x4002D000 // QEI1\r
+#define TIMER0_BASE 0x40030000 // Timer0\r
+#define TIMER1_BASE 0x40031000 // Timer1\r
+#define TIMER2_BASE 0x40032000 // Timer2\r
+#define TIMER3_BASE 0x40033000 // Timer3\r
+#define ADC_BASE 0x40038000 // ADC\r
+#define COMP_BASE 0x4003C000 // Analog comparators\r
+#define CAN0_BASE 0x40040000 // CAN0\r
+#define CAN1_BASE 0x40041000 // CAN1\r
+#define ETH_BASE 0x40048000 // Ethernet\r
+#define FLASH_CTRL_BASE 0x400FD000 // FLASH Controller\r
+#define SYSCTL_BASE 0x400FE000 // System Control\r
+#define ITM_BASE 0xE0000000 // Instrumentation Trace Macrocell\r
+#define DWT_BASE 0xE0001000 // Data Watchpoint and Trace\r
+#define FPB_BASE 0xE0002000 // FLASH Patch and Breakpoint\r
+#define NVIC_BASE 0xE000E000 // Nested Vectored Interrupt Ctrl\r
+#define TPIU_BASE 0xE0040000 // Trace Port Interface Unit\r
+\r
+#endif // __HW_MEMMAP_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_nvic.h - Macros used when accessing the NVIC hardware.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_NVIC_H__\r
+#define __HW_NVIC_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the addresses of the NVIC registers.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_INT_TYPE 0xE000E004 // Interrupt Controller Type Reg.\r
+#define NVIC_ST_CTRL 0xE000E010 // SysTick Control and Status Reg.\r
+#define NVIC_ST_RELOAD 0xE000E014 // SysTick Reload Value Register\r
+#define NVIC_ST_CURRENT 0xE000E018 // SysTick Current Value Register\r
+#define NVIC_ST_CAL 0xE000E01C // SysTick Calibration Value Reg.\r
+#define NVIC_EN0 0xE000E100 // IRQ 0 to 31 Set Enable Register\r
+#define NVIC_EN1 0xE000E104 // IRQ 32 to 63 Set Enable Register\r
+#define NVIC_DIS0 0xE000E180 // IRQ 0 to 31 Clear Enable Reg.\r
+#define NVIC_DIS1 0xE000E184 // IRQ 32 to 63 Clear Enable Reg.\r
+#define NVIC_PEND0 0xE000E200 // IRQ 0 to 31 Set Pending Register\r
+#define NVIC_PEND1 0xE000E204 // IRQ 32 to 63 Set Pending Reg.\r
+#define NVIC_UNPEND0 0xE000E280 // IRQ 0 to 31 Clear Pending Reg.\r
+#define NVIC_UNPEND1 0xE000E284 // IRQ 32 to 63 Clear Pending Reg.\r
+#define NVIC_ACTIVE0 0xE000E300 // IRQ 0 to 31 Active Register\r
+#define NVIC_ACTIVE1 0xE000E304 // IRQ 32 to 63 Active Register\r
+#define NVIC_PRI0 0xE000E400 // IRQ 0 to 3 Priority Register\r
+#define NVIC_PRI1 0xE000E404 // IRQ 4 to 7 Priority Register\r
+#define NVIC_PRI2 0xE000E408 // IRQ 8 to 11 Priority Register\r
+#define NVIC_PRI3 0xE000E40C // IRQ 12 to 15 Priority Register\r
+#define NVIC_PRI4 0xE000E410 // IRQ 16 to 19 Priority Register\r
+#define NVIC_PRI5 0xE000E414 // IRQ 20 to 23 Priority Register\r
+#define NVIC_PRI6 0xE000E418 // IRQ 24 to 27 Priority Register\r
+#define NVIC_PRI7 0xE000E41C // IRQ 28 to 31 Priority Register\r
+#define NVIC_PRI8 0xE000E420 // IRQ 32 to 35 Priority Register\r
+#define NVIC_PRI9 0xE000E424 // IRQ 36 to 39 Priority Register\r
+#define NVIC_PRI10 0xE000E428 // IRQ 40 to 43 Priority Register\r
+#define NVIC_CPUID 0xE000ED00 // CPUID Base Register\r
+#define NVIC_INT_CTRL 0xE000ED04 // Interrupt Control State Register\r
+#define NVIC_VTABLE 0xE000ED08 // Vector Table Offset Register\r
+#define NVIC_APINT 0xE000ED0C // App. Int & Reset Control Reg.\r
+#define NVIC_SYS_CTRL 0xE000ED10 // System Control Register\r
+#define NVIC_CFG_CTRL 0xE000ED14 // Configuration Control Register\r
+#define NVIC_SYS_PRI1 0xE000ED18 // Sys. Handlers 4 to 7 Priority\r
+#define NVIC_SYS_PRI2 0xE000ED1C // Sys. Handlers 8 to 11 Priority\r
+#define NVIC_SYS_PRI3 0xE000ED20 // Sys. Handlers 12 to 15 Priority\r
+#define NVIC_SYS_HND_CTRL 0xE000ED24 // System Handler Control and State\r
+#define NVIC_FAULT_STAT 0xE000ED28 // Configurable Fault Status Reg.\r
+#define NVIC_HFAULT_STAT 0xE000ED2C // Hard Fault Status Register\r
+#define NVIC_DEBUG_STAT 0xE000ED30 // Debug Status Register\r
+#define NVIC_MM_ADDR 0xE000ED34 // Mem Manage Address Register\r
+#define NVIC_FAULT_ADDR 0xE000ED38 // Bus Fault Address Register\r
+#define NVIC_MPU_TYPE 0xE000ED90 // MPU Type Register\r
+#define NVIC_MPU_CTRL 0xE000ED94 // MPU Control Register\r
+#define NVIC_MPU_NUMBER 0xE000ED98 // MPU Region Number Register\r
+#define NVIC_MPU_BASE 0xE000ED9C // MPU Region Base Address Register\r
+#define NVIC_MPU_ATTR 0xE000EDA0 // MPU Region Attribute & Size Reg.\r
+#define NVIC_DBG_CTRL 0xE000EDF0 // Debug Control and Status Reg.\r
+#define NVIC_DBG_XFER 0xE000EDF4 // Debug Core Reg. Transfer Select\r
+#define NVIC_DBG_DATA 0xE000EDF8 // Debug Core Register Data\r
+#define NVIC_DBG_INT 0xE000EDFC // Debug Reset Interrupt Control\r
+#define NVIC_SW_TRIG 0xE000EF00 // Software Trigger Interrupt Reg.\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_INT_TYPE register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_INT_TYPE_LINES_M 0x0000001F // Number of interrupt lines (x32)\r
+#define NVIC_INT_TYPE_LINES_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_ST_CTRL register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_ST_CTRL_COUNT 0x00010000 // Count flag\r
+#define NVIC_ST_CTRL_CLK_SRC 0x00000004 // Clock Source\r
+#define NVIC_ST_CTRL_INTEN 0x00000002 // Interrupt enable\r
+#define NVIC_ST_CTRL_ENABLE 0x00000001 // Counter mode\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_ST_RELOAD register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_ST_RELOAD_M 0x00FFFFFF // Counter load value\r
+#define NVIC_ST_RELOAD_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_ST_CURRENT register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_ST_CURRENT_M 0x00FFFFFF // Counter current value\r
+#define NVIC_ST_CURRENT_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_ST_CAL register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_ST_CAL_NOREF 0x80000000 // No reference clock\r
+#define NVIC_ST_CAL_SKEW 0x40000000 // Clock skew\r
+#define NVIC_ST_CAL_ONEMS_M 0x00FFFFFF // 1ms reference value\r
+#define NVIC_ST_CAL_ONEMS_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_EN0 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_EN0_INT31 0x80000000 // Interrupt 31 enable\r
+#define NVIC_EN0_INT30 0x40000000 // Interrupt 30 enable\r
+#define NVIC_EN0_INT29 0x20000000 // Interrupt 29 enable\r
+#define NVIC_EN0_INT28 0x10000000 // Interrupt 28 enable\r
+#define NVIC_EN0_INT27 0x08000000 // Interrupt 27 enable\r
+#define NVIC_EN0_INT26 0x04000000 // Interrupt 26 enable\r
+#define NVIC_EN0_INT25 0x02000000 // Interrupt 25 enable\r
+#define NVIC_EN0_INT24 0x01000000 // Interrupt 24 enable\r
+#define NVIC_EN0_INT23 0x00800000 // Interrupt 23 enable\r
+#define NVIC_EN0_INT22 0x00400000 // Interrupt 22 enable\r
+#define NVIC_EN0_INT21 0x00200000 // Interrupt 21 enable\r
+#define NVIC_EN0_INT20 0x00100000 // Interrupt 20 enable\r
+#define NVIC_EN0_INT19 0x00080000 // Interrupt 19 enable\r
+#define NVIC_EN0_INT18 0x00040000 // Interrupt 18 enable\r
+#define NVIC_EN0_INT17 0x00020000 // Interrupt 17 enable\r
+#define NVIC_EN0_INT16 0x00010000 // Interrupt 16 enable\r
+#define NVIC_EN0_INT15 0x00008000 // Interrupt 15 enable\r
+#define NVIC_EN0_INT14 0x00004000 // Interrupt 14 enable\r
+#define NVIC_EN0_INT13 0x00002000 // Interrupt 13 enable\r
+#define NVIC_EN0_INT12 0x00001000 // Interrupt 12 enable\r
+#define NVIC_EN0_INT11 0x00000800 // Interrupt 11 enable\r
+#define NVIC_EN0_INT10 0x00000400 // Interrupt 10 enable\r
+#define NVIC_EN0_INT9 0x00000200 // Interrupt 9 enable\r
+#define NVIC_EN0_INT8 0x00000100 // Interrupt 8 enable\r
+#define NVIC_EN0_INT7 0x00000080 // Interrupt 7 enable\r
+#define NVIC_EN0_INT6 0x00000040 // Interrupt 6 enable\r
+#define NVIC_EN0_INT5 0x00000020 // Interrupt 5 enable\r
+#define NVIC_EN0_INT4 0x00000010 // Interrupt 4 enable\r
+#define NVIC_EN0_INT3 0x00000008 // Interrupt 3 enable\r
+#define NVIC_EN0_INT2 0x00000004 // Interrupt 2 enable\r
+#define NVIC_EN0_INT1 0x00000002 // Interrupt 1 enable\r
+#define NVIC_EN0_INT0 0x00000001 // Interrupt 0 enable\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_EN1 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_EN1_INT59 0x08000000 // Interrupt 59 enable\r
+#define NVIC_EN1_INT58 0x04000000 // Interrupt 58 enable\r
+#define NVIC_EN1_INT57 0x02000000 // Interrupt 57 enable\r
+#define NVIC_EN1_INT56 0x01000000 // Interrupt 56 enable\r
+#define NVIC_EN1_INT55 0x00800000 // Interrupt 55 enable\r
+#define NVIC_EN1_INT54 0x00400000 // Interrupt 54 enable\r
+#define NVIC_EN1_INT53 0x00200000 // Interrupt 53 enable\r
+#define NVIC_EN1_INT52 0x00100000 // Interrupt 52 enable\r
+#define NVIC_EN1_INT51 0x00080000 // Interrupt 51 enable\r
+#define NVIC_EN1_INT50 0x00040000 // Interrupt 50 enable\r
+#define NVIC_EN1_INT49 0x00020000 // Interrupt 49 enable\r
+#define NVIC_EN1_INT48 0x00010000 // Interrupt 48 enable\r
+#define NVIC_EN1_INT47 0x00008000 // Interrupt 47 enable\r
+#define NVIC_EN1_INT46 0x00004000 // Interrupt 46 enable\r
+#define NVIC_EN1_INT45 0x00002000 // Interrupt 45 enable\r
+#define NVIC_EN1_INT44 0x00001000 // Interrupt 44 enable\r
+#define NVIC_EN1_INT43 0x00000800 // Interrupt 43 enable\r
+#define NVIC_EN1_INT42 0x00000400 // Interrupt 42 enable\r
+#define NVIC_EN1_INT41 0x00000200 // Interrupt 41 enable\r
+#define NVIC_EN1_INT40 0x00000100 // Interrupt 40 enable\r
+#define NVIC_EN1_INT39 0x00000080 // Interrupt 39 enable\r
+#define NVIC_EN1_INT38 0x00000040 // Interrupt 38 enable\r
+#define NVIC_EN1_INT37 0x00000020 // Interrupt 37 enable\r
+#define NVIC_EN1_INT36 0x00000010 // Interrupt 36 enable\r
+#define NVIC_EN1_INT35 0x00000008 // Interrupt 35 enable\r
+#define NVIC_EN1_INT34 0x00000004 // Interrupt 34 enable\r
+#define NVIC_EN1_INT33 0x00000002 // Interrupt 33 enable\r
+#define NVIC_EN1_INT32 0x00000001 // Interrupt 32 enable\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_DIS0 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_DIS0_INT31 0x80000000 // Interrupt 31 disable\r
+#define NVIC_DIS0_INT30 0x40000000 // Interrupt 30 disable\r
+#define NVIC_DIS0_INT29 0x20000000 // Interrupt 29 disable\r
+#define NVIC_DIS0_INT28 0x10000000 // Interrupt 28 disable\r
+#define NVIC_DIS0_INT27 0x08000000 // Interrupt 27 disable\r
+#define NVIC_DIS0_INT26 0x04000000 // Interrupt 26 disable\r
+#define NVIC_DIS0_INT25 0x02000000 // Interrupt 25 disable\r
+#define NVIC_DIS0_INT24 0x01000000 // Interrupt 24 disable\r
+#define NVIC_DIS0_INT23 0x00800000 // Interrupt 23 disable\r
+#define NVIC_DIS0_INT22 0x00400000 // Interrupt 22 disable\r
+#define NVIC_DIS0_INT21 0x00200000 // Interrupt 21 disable\r
+#define NVIC_DIS0_INT20 0x00100000 // Interrupt 20 disable\r
+#define NVIC_DIS0_INT19 0x00080000 // Interrupt 19 disable\r
+#define NVIC_DIS0_INT18 0x00040000 // Interrupt 18 disable\r
+#define NVIC_DIS0_INT17 0x00020000 // Interrupt 17 disable\r
+#define NVIC_DIS0_INT16 0x00010000 // Interrupt 16 disable\r
+#define NVIC_DIS0_INT15 0x00008000 // Interrupt 15 disable\r
+#define NVIC_DIS0_INT14 0x00004000 // Interrupt 14 disable\r
+#define NVIC_DIS0_INT13 0x00002000 // Interrupt 13 disable\r
+#define NVIC_DIS0_INT12 0x00001000 // Interrupt 12 disable\r
+#define NVIC_DIS0_INT11 0x00000800 // Interrupt 11 disable\r
+#define NVIC_DIS0_INT10 0x00000400 // Interrupt 10 disable\r
+#define NVIC_DIS0_INT9 0x00000200 // Interrupt 9 disable\r
+#define NVIC_DIS0_INT8 0x00000100 // Interrupt 8 disable\r
+#define NVIC_DIS0_INT7 0x00000080 // Interrupt 7 disable\r
+#define NVIC_DIS0_INT6 0x00000040 // Interrupt 6 disable\r
+#define NVIC_DIS0_INT5 0x00000020 // Interrupt 5 disable\r
+#define NVIC_DIS0_INT4 0x00000010 // Interrupt 4 disable\r
+#define NVIC_DIS0_INT3 0x00000008 // Interrupt 3 disable\r
+#define NVIC_DIS0_INT2 0x00000004 // Interrupt 2 disable\r
+#define NVIC_DIS0_INT1 0x00000002 // Interrupt 1 disable\r
+#define NVIC_DIS0_INT0 0x00000001 // Interrupt 0 disable\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_DIS1 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_DIS1_INT59 0x08000000 // Interrupt 59 disable\r
+#define NVIC_DIS1_INT58 0x04000000 // Interrupt 58 disable\r
+#define NVIC_DIS1_INT57 0x02000000 // Interrupt 57 disable\r
+#define NVIC_DIS1_INT56 0x01000000 // Interrupt 56 disable\r
+#define NVIC_DIS1_INT55 0x00800000 // Interrupt 55 disable\r
+#define NVIC_DIS1_INT54 0x00400000 // Interrupt 54 disable\r
+#define NVIC_DIS1_INT53 0x00200000 // Interrupt 53 disable\r
+#define NVIC_DIS1_INT52 0x00100000 // Interrupt 52 disable\r
+#define NVIC_DIS1_INT51 0x00080000 // Interrupt 51 disable\r
+#define NVIC_DIS1_INT50 0x00040000 // Interrupt 50 disable\r
+#define NVIC_DIS1_INT49 0x00020000 // Interrupt 49 disable\r
+#define NVIC_DIS1_INT48 0x00010000 // Interrupt 48 disable\r
+#define NVIC_DIS1_INT47 0x00008000 // Interrupt 47 disable\r
+#define NVIC_DIS1_INT46 0x00004000 // Interrupt 46 disable\r
+#define NVIC_DIS1_INT45 0x00002000 // Interrupt 45 disable\r
+#define NVIC_DIS1_INT44 0x00001000 // Interrupt 44 disable\r
+#define NVIC_DIS1_INT43 0x00000800 // Interrupt 43 disable\r
+#define NVIC_DIS1_INT42 0x00000400 // Interrupt 42 disable\r
+#define NVIC_DIS1_INT41 0x00000200 // Interrupt 41 disable\r
+#define NVIC_DIS1_INT40 0x00000100 // Interrupt 40 disable\r
+#define NVIC_DIS1_INT39 0x00000080 // Interrupt 39 disable\r
+#define NVIC_DIS1_INT38 0x00000040 // Interrupt 38 disable\r
+#define NVIC_DIS1_INT37 0x00000020 // Interrupt 37 disable\r
+#define NVIC_DIS1_INT36 0x00000010 // Interrupt 36 disable\r
+#define NVIC_DIS1_INT35 0x00000008 // Interrupt 35 disable\r
+#define NVIC_DIS1_INT34 0x00000004 // Interrupt 34 disable\r
+#define NVIC_DIS1_INT33 0x00000002 // Interrupt 33 disable\r
+#define NVIC_DIS1_INT32 0x00000001 // Interrupt 32 disable\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_PEND0 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_PEND0_INT31 0x80000000 // Interrupt 31 pend\r
+#define NVIC_PEND0_INT30 0x40000000 // Interrupt 30 pend\r
+#define NVIC_PEND0_INT29 0x20000000 // Interrupt 29 pend\r
+#define NVIC_PEND0_INT28 0x10000000 // Interrupt 28 pend\r
+#define NVIC_PEND0_INT27 0x08000000 // Interrupt 27 pend\r
+#define NVIC_PEND0_INT26 0x04000000 // Interrupt 26 pend\r
+#define NVIC_PEND0_INT25 0x02000000 // Interrupt 25 pend\r
+#define NVIC_PEND0_INT24 0x01000000 // Interrupt 24 pend\r
+#define NVIC_PEND0_INT23 0x00800000 // Interrupt 23 pend\r
+#define NVIC_PEND0_INT22 0x00400000 // Interrupt 22 pend\r
+#define NVIC_PEND0_INT21 0x00200000 // Interrupt 21 pend\r
+#define NVIC_PEND0_INT20 0x00100000 // Interrupt 20 pend\r
+#define NVIC_PEND0_INT19 0x00080000 // Interrupt 19 pend\r
+#define NVIC_PEND0_INT18 0x00040000 // Interrupt 18 pend\r
+#define NVIC_PEND0_INT17 0x00020000 // Interrupt 17 pend\r
+#define NVIC_PEND0_INT16 0x00010000 // Interrupt 16 pend\r
+#define NVIC_PEND0_INT15 0x00008000 // Interrupt 15 pend\r
+#define NVIC_PEND0_INT14 0x00004000 // Interrupt 14 pend\r
+#define NVIC_PEND0_INT13 0x00002000 // Interrupt 13 pend\r
+#define NVIC_PEND0_INT12 0x00001000 // Interrupt 12 pend\r
+#define NVIC_PEND0_INT11 0x00000800 // Interrupt 11 pend\r
+#define NVIC_PEND0_INT10 0x00000400 // Interrupt 10 pend\r
+#define NVIC_PEND0_INT9 0x00000200 // Interrupt 9 pend\r
+#define NVIC_PEND0_INT8 0x00000100 // Interrupt 8 pend\r
+#define NVIC_PEND0_INT7 0x00000080 // Interrupt 7 pend\r
+#define NVIC_PEND0_INT6 0x00000040 // Interrupt 6 pend\r
+#define NVIC_PEND0_INT5 0x00000020 // Interrupt 5 pend\r
+#define NVIC_PEND0_INT4 0x00000010 // Interrupt 4 pend\r
+#define NVIC_PEND0_INT3 0x00000008 // Interrupt 3 pend\r
+#define NVIC_PEND0_INT2 0x00000004 // Interrupt 2 pend\r
+#define NVIC_PEND0_INT1 0x00000002 // Interrupt 1 pend\r
+#define NVIC_PEND0_INT0 0x00000001 // Interrupt 0 pend\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_PEND1 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_PEND1_INT59 0x08000000 // Interrupt 59 pend\r
+#define NVIC_PEND1_INT58 0x04000000 // Interrupt 58 pend\r
+#define NVIC_PEND1_INT57 0x02000000 // Interrupt 57 pend\r
+#define NVIC_PEND1_INT56 0x01000000 // Interrupt 56 pend\r
+#define NVIC_PEND1_INT55 0x00800000 // Interrupt 55 pend\r
+#define NVIC_PEND1_INT54 0x00400000 // Interrupt 54 pend\r
+#define NVIC_PEND1_INT53 0x00200000 // Interrupt 53 pend\r
+#define NVIC_PEND1_INT52 0x00100000 // Interrupt 52 pend\r
+#define NVIC_PEND1_INT51 0x00080000 // Interrupt 51 pend\r
+#define NVIC_PEND1_INT50 0x00040000 // Interrupt 50 pend\r
+#define NVIC_PEND1_INT49 0x00020000 // Interrupt 49 pend\r
+#define NVIC_PEND1_INT48 0x00010000 // Interrupt 48 pend\r
+#define NVIC_PEND1_INT47 0x00008000 // Interrupt 47 pend\r
+#define NVIC_PEND1_INT46 0x00004000 // Interrupt 46 pend\r
+#define NVIC_PEND1_INT45 0x00002000 // Interrupt 45 pend\r
+#define NVIC_PEND1_INT44 0x00001000 // Interrupt 44 pend\r
+#define NVIC_PEND1_INT43 0x00000800 // Interrupt 43 pend\r
+#define NVIC_PEND1_INT42 0x00000400 // Interrupt 42 pend\r
+#define NVIC_PEND1_INT41 0x00000200 // Interrupt 41 pend\r
+#define NVIC_PEND1_INT40 0x00000100 // Interrupt 40 pend\r
+#define NVIC_PEND1_INT39 0x00000080 // Interrupt 39 pend\r
+#define NVIC_PEND1_INT38 0x00000040 // Interrupt 38 pend\r
+#define NVIC_PEND1_INT37 0x00000020 // Interrupt 37 pend\r
+#define NVIC_PEND1_INT36 0x00000010 // Interrupt 36 pend\r
+#define NVIC_PEND1_INT35 0x00000008 // Interrupt 35 pend\r
+#define NVIC_PEND1_INT34 0x00000004 // Interrupt 34 pend\r
+#define NVIC_PEND1_INT33 0x00000002 // Interrupt 33 pend\r
+#define NVIC_PEND1_INT32 0x00000001 // Interrupt 32 pend\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_UNPEND0 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_UNPEND0_INT31 0x80000000 // Interrupt 31 unpend\r
+#define NVIC_UNPEND0_INT30 0x40000000 // Interrupt 30 unpend\r
+#define NVIC_UNPEND0_INT29 0x20000000 // Interrupt 29 unpend\r
+#define NVIC_UNPEND0_INT28 0x10000000 // Interrupt 28 unpend\r
+#define NVIC_UNPEND0_INT27 0x08000000 // Interrupt 27 unpend\r
+#define NVIC_UNPEND0_INT26 0x04000000 // Interrupt 26 unpend\r
+#define NVIC_UNPEND0_INT25 0x02000000 // Interrupt 25 unpend\r
+#define NVIC_UNPEND0_INT24 0x01000000 // Interrupt 24 unpend\r
+#define NVIC_UNPEND0_INT23 0x00800000 // Interrupt 23 unpend\r
+#define NVIC_UNPEND0_INT22 0x00400000 // Interrupt 22 unpend\r
+#define NVIC_UNPEND0_INT21 0x00200000 // Interrupt 21 unpend\r
+#define NVIC_UNPEND0_INT20 0x00100000 // Interrupt 20 unpend\r
+#define NVIC_UNPEND0_INT19 0x00080000 // Interrupt 19 unpend\r
+#define NVIC_UNPEND0_INT18 0x00040000 // Interrupt 18 unpend\r
+#define NVIC_UNPEND0_INT17 0x00020000 // Interrupt 17 unpend\r
+#define NVIC_UNPEND0_INT16 0x00010000 // Interrupt 16 unpend\r
+#define NVIC_UNPEND0_INT15 0x00008000 // Interrupt 15 unpend\r
+#define NVIC_UNPEND0_INT14 0x00004000 // Interrupt 14 unpend\r
+#define NVIC_UNPEND0_INT13 0x00002000 // Interrupt 13 unpend\r
+#define NVIC_UNPEND0_INT12 0x00001000 // Interrupt 12 unpend\r
+#define NVIC_UNPEND0_INT11 0x00000800 // Interrupt 11 unpend\r
+#define NVIC_UNPEND0_INT10 0x00000400 // Interrupt 10 unpend\r
+#define NVIC_UNPEND0_INT9 0x00000200 // Interrupt 9 unpend\r
+#define NVIC_UNPEND0_INT8 0x00000100 // Interrupt 8 unpend\r
+#define NVIC_UNPEND0_INT7 0x00000080 // Interrupt 7 unpend\r
+#define NVIC_UNPEND0_INT6 0x00000040 // Interrupt 6 unpend\r
+#define NVIC_UNPEND0_INT5 0x00000020 // Interrupt 5 unpend\r
+#define NVIC_UNPEND0_INT4 0x00000010 // Interrupt 4 unpend\r
+#define NVIC_UNPEND0_INT3 0x00000008 // Interrupt 3 unpend\r
+#define NVIC_UNPEND0_INT2 0x00000004 // Interrupt 2 unpend\r
+#define NVIC_UNPEND0_INT1 0x00000002 // Interrupt 1 unpend\r
+#define NVIC_UNPEND0_INT0 0x00000001 // Interrupt 0 unpend\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_UNPEND1 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_UNPEND1_INT59 0x08000000 // Interrupt 59 unpend\r
+#define NVIC_UNPEND1_INT58 0x04000000 // Interrupt 58 unpend\r
+#define NVIC_UNPEND1_INT57 0x02000000 // Interrupt 57 unpend\r
+#define NVIC_UNPEND1_INT56 0x01000000 // Interrupt 56 unpend\r
+#define NVIC_UNPEND1_INT55 0x00800000 // Interrupt 55 unpend\r
+#define NVIC_UNPEND1_INT54 0x00400000 // Interrupt 54 unpend\r
+#define NVIC_UNPEND1_INT53 0x00200000 // Interrupt 53 unpend\r
+#define NVIC_UNPEND1_INT52 0x00100000 // Interrupt 52 unpend\r
+#define NVIC_UNPEND1_INT51 0x00080000 // Interrupt 51 unpend\r
+#define NVIC_UNPEND1_INT50 0x00040000 // Interrupt 50 unpend\r
+#define NVIC_UNPEND1_INT49 0x00020000 // Interrupt 49 unpend\r
+#define NVIC_UNPEND1_INT48 0x00010000 // Interrupt 48 unpend\r
+#define NVIC_UNPEND1_INT47 0x00008000 // Interrupt 47 unpend\r
+#define NVIC_UNPEND1_INT46 0x00004000 // Interrupt 46 unpend\r
+#define NVIC_UNPEND1_INT45 0x00002000 // Interrupt 45 unpend\r
+#define NVIC_UNPEND1_INT44 0x00001000 // Interrupt 44 unpend\r
+#define NVIC_UNPEND1_INT43 0x00000800 // Interrupt 43 unpend\r
+#define NVIC_UNPEND1_INT42 0x00000400 // Interrupt 42 unpend\r
+#define NVIC_UNPEND1_INT41 0x00000200 // Interrupt 41 unpend\r
+#define NVIC_UNPEND1_INT40 0x00000100 // Interrupt 40 unpend\r
+#define NVIC_UNPEND1_INT39 0x00000080 // Interrupt 39 unpend\r
+#define NVIC_UNPEND1_INT38 0x00000040 // Interrupt 38 unpend\r
+#define NVIC_UNPEND1_INT37 0x00000020 // Interrupt 37 unpend\r
+#define NVIC_UNPEND1_INT36 0x00000010 // Interrupt 36 unpend\r
+#define NVIC_UNPEND1_INT35 0x00000008 // Interrupt 35 unpend\r
+#define NVIC_UNPEND1_INT34 0x00000004 // Interrupt 34 unpend\r
+#define NVIC_UNPEND1_INT33 0x00000002 // Interrupt 33 unpend\r
+#define NVIC_UNPEND1_INT32 0x00000001 // Interrupt 32 unpend\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_ACTIVE0 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_ACTIVE0_INT31 0x80000000 // Interrupt 31 active\r
+#define NVIC_ACTIVE0_INT30 0x40000000 // Interrupt 30 active\r
+#define NVIC_ACTIVE0_INT29 0x20000000 // Interrupt 29 active\r
+#define NVIC_ACTIVE0_INT28 0x10000000 // Interrupt 28 active\r
+#define NVIC_ACTIVE0_INT27 0x08000000 // Interrupt 27 active\r
+#define NVIC_ACTIVE0_INT26 0x04000000 // Interrupt 26 active\r
+#define NVIC_ACTIVE0_INT25 0x02000000 // Interrupt 25 active\r
+#define NVIC_ACTIVE0_INT24 0x01000000 // Interrupt 24 active\r
+#define NVIC_ACTIVE0_INT23 0x00800000 // Interrupt 23 active\r
+#define NVIC_ACTIVE0_INT22 0x00400000 // Interrupt 22 active\r
+#define NVIC_ACTIVE0_INT21 0x00200000 // Interrupt 21 active\r
+#define NVIC_ACTIVE0_INT20 0x00100000 // Interrupt 20 active\r
+#define NVIC_ACTIVE0_INT19 0x00080000 // Interrupt 19 active\r
+#define NVIC_ACTIVE0_INT18 0x00040000 // Interrupt 18 active\r
+#define NVIC_ACTIVE0_INT17 0x00020000 // Interrupt 17 active\r
+#define NVIC_ACTIVE0_INT16 0x00010000 // Interrupt 16 active\r
+#define NVIC_ACTIVE0_INT15 0x00008000 // Interrupt 15 active\r
+#define NVIC_ACTIVE0_INT14 0x00004000 // Interrupt 14 active\r
+#define NVIC_ACTIVE0_INT13 0x00002000 // Interrupt 13 active\r
+#define NVIC_ACTIVE0_INT12 0x00001000 // Interrupt 12 active\r
+#define NVIC_ACTIVE0_INT11 0x00000800 // Interrupt 11 active\r
+#define NVIC_ACTIVE0_INT10 0x00000400 // Interrupt 10 active\r
+#define NVIC_ACTIVE0_INT9 0x00000200 // Interrupt 9 active\r
+#define NVIC_ACTIVE0_INT8 0x00000100 // Interrupt 8 active\r
+#define NVIC_ACTIVE0_INT7 0x00000080 // Interrupt 7 active\r
+#define NVIC_ACTIVE0_INT6 0x00000040 // Interrupt 6 active\r
+#define NVIC_ACTIVE0_INT5 0x00000020 // Interrupt 5 active\r
+#define NVIC_ACTIVE0_INT4 0x00000010 // Interrupt 4 active\r
+#define NVIC_ACTIVE0_INT3 0x00000008 // Interrupt 3 active\r
+#define NVIC_ACTIVE0_INT2 0x00000004 // Interrupt 2 active\r
+#define NVIC_ACTIVE0_INT1 0x00000002 // Interrupt 1 active\r
+#define NVIC_ACTIVE0_INT0 0x00000001 // Interrupt 0 active\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_ACTIVE1 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_ACTIVE1_INT59 0x08000000 // Interrupt 59 active\r
+#define NVIC_ACTIVE1_INT58 0x04000000 // Interrupt 58 active\r
+#define NVIC_ACTIVE1_INT57 0x02000000 // Interrupt 57 active\r
+#define NVIC_ACTIVE1_INT56 0x01000000 // Interrupt 56 active\r
+#define NVIC_ACTIVE1_INT55 0x00800000 // Interrupt 55 active\r
+#define NVIC_ACTIVE1_INT54 0x00400000 // Interrupt 54 active\r
+#define NVIC_ACTIVE1_INT53 0x00200000 // Interrupt 53 active\r
+#define NVIC_ACTIVE1_INT52 0x00100000 // Interrupt 52 active\r
+#define NVIC_ACTIVE1_INT51 0x00080000 // Interrupt 51 active\r
+#define NVIC_ACTIVE1_INT50 0x00040000 // Interrupt 50 active\r
+#define NVIC_ACTIVE1_INT49 0x00020000 // Interrupt 49 active\r
+#define NVIC_ACTIVE1_INT48 0x00010000 // Interrupt 48 active\r
+#define NVIC_ACTIVE1_INT47 0x00008000 // Interrupt 47 active\r
+#define NVIC_ACTIVE1_INT46 0x00004000 // Interrupt 46 active\r
+#define NVIC_ACTIVE1_INT45 0x00002000 // Interrupt 45 active\r
+#define NVIC_ACTIVE1_INT44 0x00001000 // Interrupt 44 active\r
+#define NVIC_ACTIVE1_INT43 0x00000800 // Interrupt 43 active\r
+#define NVIC_ACTIVE1_INT42 0x00000400 // Interrupt 42 active\r
+#define NVIC_ACTIVE1_INT41 0x00000200 // Interrupt 41 active\r
+#define NVIC_ACTIVE1_INT40 0x00000100 // Interrupt 40 active\r
+#define NVIC_ACTIVE1_INT39 0x00000080 // Interrupt 39 active\r
+#define NVIC_ACTIVE1_INT38 0x00000040 // Interrupt 38 active\r
+#define NVIC_ACTIVE1_INT37 0x00000020 // Interrupt 37 active\r
+#define NVIC_ACTIVE1_INT36 0x00000010 // Interrupt 36 active\r
+#define NVIC_ACTIVE1_INT35 0x00000008 // Interrupt 35 active\r
+#define NVIC_ACTIVE1_INT34 0x00000004 // Interrupt 34 active\r
+#define NVIC_ACTIVE1_INT33 0x00000002 // Interrupt 33 active\r
+#define NVIC_ACTIVE1_INT32 0x00000001 // Interrupt 32 active\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_PRI0 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_PRI0_INT3_M 0xFF000000 // Interrupt 3 priority mask\r
+#define NVIC_PRI0_INT2_M 0x00FF0000 // Interrupt 2 priority mask\r
+#define NVIC_PRI0_INT1_M 0x0000FF00 // Interrupt 1 priority mask\r
+#define NVIC_PRI0_INT0_M 0x000000FF // Interrupt 0 priority mask\r
+#define NVIC_PRI0_INT3_S 24\r
+#define NVIC_PRI0_INT2_S 16\r
+#define NVIC_PRI0_INT1_S 8\r
+#define NVIC_PRI0_INT0_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_PRI1 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_PRI1_INT7_M 0xFF000000 // Interrupt 7 priority mask\r
+#define NVIC_PRI1_INT6_M 0x00FF0000 // Interrupt 6 priority mask\r
+#define NVIC_PRI1_INT5_M 0x0000FF00 // Interrupt 5 priority mask\r
+#define NVIC_PRI1_INT4_M 0x000000FF // Interrupt 4 priority mask\r
+#define NVIC_PRI1_INT7_S 24\r
+#define NVIC_PRI1_INT6_S 16\r
+#define NVIC_PRI1_INT5_S 8\r
+#define NVIC_PRI1_INT4_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_PRI2 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_PRI2_INT11_M 0xFF000000 // Interrupt 11 priority mask\r
+#define NVIC_PRI2_INT10_M 0x00FF0000 // Interrupt 10 priority mask\r
+#define NVIC_PRI2_INT9_M 0x0000FF00 // Interrupt 9 priority mask\r
+#define NVIC_PRI2_INT8_M 0x000000FF // Interrupt 8 priority mask\r
+#define NVIC_PRI2_INT11_S 24\r
+#define NVIC_PRI2_INT10_S 16\r
+#define NVIC_PRI2_INT9_S 8\r
+#define NVIC_PRI2_INT8_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_PRI3 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_PRI3_INT15_M 0xFF000000 // Interrupt 15 priority mask\r
+#define NVIC_PRI3_INT14_M 0x00FF0000 // Interrupt 14 priority mask\r
+#define NVIC_PRI3_INT13_M 0x0000FF00 // Interrupt 13 priority mask\r
+#define NVIC_PRI3_INT12_M 0x000000FF // Interrupt 12 priority mask\r
+#define NVIC_PRI3_INT15_S 24\r
+#define NVIC_PRI3_INT14_S 16\r
+#define NVIC_PRI3_INT13_S 8\r
+#define NVIC_PRI3_INT12_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_PRI4 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_PRI4_INT19_M 0xFF000000 // Interrupt 19 priority mask\r
+#define NVIC_PRI4_INT18_M 0x00FF0000 // Interrupt 18 priority mask\r
+#define NVIC_PRI4_INT17_M 0x0000FF00 // Interrupt 17 priority mask\r
+#define NVIC_PRI4_INT16_M 0x000000FF // Interrupt 16 priority mask\r
+#define NVIC_PRI4_INT19_S 24\r
+#define NVIC_PRI4_INT18_S 16\r
+#define NVIC_PRI4_INT17_S 8\r
+#define NVIC_PRI4_INT16_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_PRI5 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_PRI5_INT23_M 0xFF000000 // Interrupt 23 priority mask\r
+#define NVIC_PRI5_INT22_M 0x00FF0000 // Interrupt 22 priority mask\r
+#define NVIC_PRI5_INT21_M 0x0000FF00 // Interrupt 21 priority mask\r
+#define NVIC_PRI5_INT20_M 0x000000FF // Interrupt 20 priority mask\r
+#define NVIC_PRI5_INT23_S 24\r
+#define NVIC_PRI5_INT22_S 16\r
+#define NVIC_PRI5_INT21_S 8\r
+#define NVIC_PRI5_INT20_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_PRI6 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_PRI6_INT27_M 0xFF000000 // Interrupt 27 priority mask\r
+#define NVIC_PRI6_INT26_M 0x00FF0000 // Interrupt 26 priority mask\r
+#define NVIC_PRI6_INT25_M 0x0000FF00 // Interrupt 25 priority mask\r
+#define NVIC_PRI6_INT24_M 0x000000FF // Interrupt 24 priority mask\r
+#define NVIC_PRI6_INT27_S 24\r
+#define NVIC_PRI6_INT26_S 16\r
+#define NVIC_PRI6_INT25_S 8\r
+#define NVIC_PRI6_INT24_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_PRI7 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_PRI7_INT31_M 0xFF000000 // Interrupt 31 priority mask\r
+#define NVIC_PRI7_INT30_M 0x00FF0000 // Interrupt 30 priority mask\r
+#define NVIC_PRI7_INT29_M 0x0000FF00 // Interrupt 29 priority mask\r
+#define NVIC_PRI7_INT28_M 0x000000FF // Interrupt 28 priority mask\r
+#define NVIC_PRI7_INT31_S 24\r
+#define NVIC_PRI7_INT30_S 16\r
+#define NVIC_PRI7_INT29_S 8\r
+#define NVIC_PRI7_INT28_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_PRI8 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_PRI8_INT35_M 0xFF000000 // Interrupt 35 priority mask\r
+#define NVIC_PRI8_INT34_M 0x00FF0000 // Interrupt 34 priority mask\r
+#define NVIC_PRI8_INT33_M 0x0000FF00 // Interrupt 33 priority mask\r
+#define NVIC_PRI8_INT32_M 0x000000FF // Interrupt 32 priority mask\r
+#define NVIC_PRI8_INT35_S 24\r
+#define NVIC_PRI8_INT34_S 16\r
+#define NVIC_PRI8_INT33_S 8\r
+#define NVIC_PRI8_INT32_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_PRI9 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_PRI9_INT39_M 0xFF000000 // Interrupt 39 priority mask\r
+#define NVIC_PRI9_INT38_M 0x00FF0000 // Interrupt 38 priority mask\r
+#define NVIC_PRI9_INT37_M 0x0000FF00 // Interrupt 37 priority mask\r
+#define NVIC_PRI9_INT36_M 0x000000FF // Interrupt 36 priority mask\r
+#define NVIC_PRI9_INT39_S 24\r
+#define NVIC_PRI9_INT38_S 16\r
+#define NVIC_PRI9_INT37_S 8\r
+#define NVIC_PRI9_INT36_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_PRI10 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_PRI10_INT43_M 0xFF000000 // Interrupt 43 priority mask\r
+#define NVIC_PRI10_INT42_M 0x00FF0000 // Interrupt 42 priority mask\r
+#define NVIC_PRI10_INT41_M 0x0000FF00 // Interrupt 41 priority mask\r
+#define NVIC_PRI10_INT40_M 0x000000FF // Interrupt 40 priority mask\r
+#define NVIC_PRI10_INT43_S 24\r
+#define NVIC_PRI10_INT42_S 16\r
+#define NVIC_PRI10_INT41_S 8\r
+#define NVIC_PRI10_INT40_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_CPUID register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_CPUID_IMP_M 0xFF000000 // Implementer\r
+#define NVIC_CPUID_VAR_M 0x00F00000 // Variant\r
+#define NVIC_CPUID_PARTNO_M 0x0000FFF0 // Processor part number\r
+#define NVIC_CPUID_REV_M 0x0000000F // Revision\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_INT_CTRL register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_INT_CTRL_NMI_SET 0x80000000 // Pend a NMI\r
+#define NVIC_INT_CTRL_PEND_SV 0x10000000 // Pend a PendSV\r
+#define NVIC_INT_CTRL_UNPEND_SV 0x08000000 // Unpend a PendSV\r
+#define NVIC_INT_CTRL_ISR_PRE 0x00800000 // Debug interrupt handling\r
+#define NVIC_INT_CTRL_ISR_PEND 0x00400000 // Debug interrupt pending\r
+#define NVIC_INT_CTRL_VEC_PEN_M 0x003FF000 // Highest pending exception\r
+#define NVIC_INT_CTRL_RET_BASE 0x00000800 // Return to base\r
+#define NVIC_INT_CTRL_VEC_ACT_M 0x000003FF // Current active exception\r
+#define NVIC_INT_CTRL_VEC_PEN_S 12\r
+#define NVIC_INT_CTRL_VEC_ACT_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_VTABLE register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_VTABLE_BASE 0x20000000 // Vector table base\r
+#define NVIC_VTABLE_OFFSET_M 0x1FFFFF00 // Vector table offset\r
+#define NVIC_VTABLE_OFFSET_S 8\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_APINT register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_APINT_VECTKEY_M 0xFFFF0000 // Vector key mask\r
+#define NVIC_APINT_VECTKEY 0x05FA0000 // Vector key\r
+#define NVIC_APINT_ENDIANESS 0x00008000 // Data endianess\r
+#define NVIC_APINT_PRIGROUP_M 0x00000700 // Priority group\r
+#define NVIC_APINT_PRIGROUP_7_1 0x00000000 // Priority group 7.1 split\r
+#define NVIC_APINT_PRIGROUP_6_2 0x00000100 // Priority group 6.2 split\r
+#define NVIC_APINT_PRIGROUP_5_3 0x00000200 // Priority group 5.3 split\r
+#define NVIC_APINT_PRIGROUP_4_4 0x00000300 // Priority group 4.4 split\r
+#define NVIC_APINT_PRIGROUP_3_5 0x00000400 // Priority group 3.5 split\r
+#define NVIC_APINT_PRIGROUP_2_6 0x00000500 // Priority group 2.6 split\r
+#define NVIC_APINT_PRIGROUP_1_7 0x00000600 // Priority group 1.7 split\r
+#define NVIC_APINT_PRIGROUP_0_8 0x00000700 // Priority group 0.8 split\r
+#define NVIC_APINT_SYSRESETREQ 0x00000004 // System reset request\r
+#define NVIC_APINT_VECT_CLR_ACT 0x00000002 // Clear active NMI/fault info\r
+#define NVIC_APINT_VECT_RESET 0x00000001 // System reset\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_SYS_CTRL register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_SYS_CTRL_SEVONPEND 0x00000010 // Wakeup on pend\r
+#define NVIC_SYS_CTRL_SLEEPDEEP 0x00000004 // Deep sleep enable\r
+#define NVIC_SYS_CTRL_SLEEPEXIT 0x00000002 // Sleep on ISR exit\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_CFG_CTRL register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_CFG_CTRL_BFHFNMIGN 0x00000100 // Ignore bus fault in NMI/fault\r
+#define NVIC_CFG_CTRL_DIV0 0x00000010 // Trap on divide by 0\r
+#define NVIC_CFG_CTRL_UNALIGNED 0x00000008 // Trap on unaligned access\r
+#define NVIC_CFG_CTRL_DEEP_PEND 0x00000004 // Allow deep interrupt trigger\r
+#define NVIC_CFG_CTRL_MAIN_PEND 0x00000002 // Allow main interrupt trigger\r
+#define NVIC_CFG_CTRL_BASE_THR 0x00000001 // Thread state control\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_SYS_PRI1 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_SYS_PRI1_RES_M 0xFF000000 // Priority of reserved handler\r
+#define NVIC_SYS_PRI1_USAGE_M 0x00FF0000 // Priority of usage fault handler\r
+#define NVIC_SYS_PRI1_BUS_M 0x0000FF00 // Priority of bus fault handler\r
+#define NVIC_SYS_PRI1_MEM_M 0x000000FF // Priority of mem manage handler\r
+#define NVIC_SYS_PRI1_USAGE_S 16\r
+#define NVIC_SYS_PRI1_BUS_S 8\r
+#define NVIC_SYS_PRI1_MEM_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_SYS_PRI2 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_SYS_PRI2_SVC_M 0xFF000000 // Priority of SVCall handler\r
+#define NVIC_SYS_PRI2_RES_M 0x00FFFFFF // Priority of reserved handlers\r
+#define NVIC_SYS_PRI2_SVC_S 24\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_SYS_PRI3 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_SYS_PRI3_TICK_M 0xFF000000 // Priority of Sys Tick handler\r
+#define NVIC_SYS_PRI3_PENDSV_M 0x00FF0000 // Priority of PendSV handler\r
+#define NVIC_SYS_PRI3_RES_M 0x0000FF00 // Priority of reserved handler\r
+#define NVIC_SYS_PRI3_DEBUG_M 0x000000FF // Priority of debug handler\r
+#define NVIC_SYS_PRI3_TICK_S 24\r
+#define NVIC_SYS_PRI3_PENDSV_S 16\r
+#define NVIC_SYS_PRI3_DEBUG_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_SYS_HND_CTRL register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_SYS_HND_CTRL_USAGE 0x00040000 // Usage fault enable\r
+#define NVIC_SYS_HND_CTRL_BUS 0x00020000 // Bus fault enable\r
+#define NVIC_SYS_HND_CTRL_MEM 0x00010000 // Mem manage fault enable\r
+#define NVIC_SYS_HND_CTRL_SVC 0x00008000 // SVCall is pended\r
+#define NVIC_SYS_HND_CTRL_BUSP 0x00004000 // Bus fault is pended\r
+#define NVIC_SYS_HND_CTRL_TICK 0x00000800 // Sys tick is active\r
+#define NVIC_SYS_HND_CTRL_PNDSV 0x00000400 // PendSV is active\r
+#define NVIC_SYS_HND_CTRL_MON 0x00000100 // Monitor is active\r
+#define NVIC_SYS_HND_CTRL_SVCA 0x00000080 // SVCall is active\r
+#define NVIC_SYS_HND_CTRL_USGA 0x00000008 // Usage fault is active\r
+#define NVIC_SYS_HND_CTRL_BUSA 0x00000002 // Bus fault is active\r
+#define NVIC_SYS_HND_CTRL_MEMA 0x00000001 // Mem manage is active\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_FAULT_STAT register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_FAULT_STAT_DIV0 0x02000000 // Divide by zero fault\r
+#define NVIC_FAULT_STAT_UNALIGN 0x01000000 // Unaligned access fault\r
+#define NVIC_FAULT_STAT_NOCP 0x00080000 // No coprocessor fault\r
+#define NVIC_FAULT_STAT_INVPC 0x00040000 // Invalid PC fault\r
+#define NVIC_FAULT_STAT_INVSTAT 0x00020000 // Invalid state fault\r
+#define NVIC_FAULT_STAT_UNDEF 0x00010000 // Undefined instruction fault\r
+#define NVIC_FAULT_STAT_BFARV 0x00008000 // BFAR is valid\r
+#define NVIC_FAULT_STAT_BSTKE 0x00001000 // Stack bus fault\r
+#define NVIC_FAULT_STAT_BUSTKE 0x00000800 // Unstack bus fault\r
+#define NVIC_FAULT_STAT_IMPRE 0x00000400 // Imprecise data bus error\r
+#define NVIC_FAULT_STAT_PRECISE 0x00000200 // Precise data bus error\r
+#define NVIC_FAULT_STAT_IBUS 0x00000100 // Instruction bus fault\r
+#define NVIC_FAULT_STAT_MMARV 0x00000080 // MMAR is valid\r
+#define NVIC_FAULT_STAT_MSTKE 0x00000010 // Stack access violation\r
+#define NVIC_FAULT_STAT_MUSTKE 0x00000008 // Unstack access violation\r
+#define NVIC_FAULT_STAT_DERR 0x00000002 // Data access violation\r
+#define NVIC_FAULT_STAT_IERR 0x00000001 // Instruction access violation\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_HFAULT_STAT register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_HFAULT_STAT_DBG 0x80000000 // Debug event\r
+#define NVIC_HFAULT_STAT_FORCED 0x40000000 // Cannot execute fault handler\r
+#define NVIC_HFAULT_STAT_VECT 0x00000002 // Vector table read fault\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_DEBUG_STAT register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_DEBUG_STAT_EXTRNL 0x00000010 // EDBGRQ asserted\r
+#define NVIC_DEBUG_STAT_VCATCH 0x00000008 // Vector catch\r
+#define NVIC_DEBUG_STAT_DWTTRAP 0x00000004 // DWT match\r
+#define NVIC_DEBUG_STAT_BKPT 0x00000002 // Breakpoint instruction\r
+#define NVIC_DEBUG_STAT_HALTED 0x00000001 // Halt request\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_MM_ADDR register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_MM_ADDR_M 0xFFFFFFFF // Data fault address\r
+#define NVIC_MM_ADDR_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_FAULT_ADDR register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_FAULT_ADDR_M 0xFFFFFFFF // Data bus fault address\r
+#define NVIC_FAULT_ADDR_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_EXC_STACK register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_EXC_STACK_DEEP 0x00000001 // Exception stack\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_EXC_NUM register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_EXC_NUM_M 0x000003FF // Exception number\r
+#define NVIC_EXC_NUM_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_COPRO register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_COPRO_15_M 0xC0000000 // Coprocessor 15 access mask\r
+#define NVIC_COPRO_15_DENIED 0x00000000 // Coprocessor 15 access denied\r
+#define NVIC_COPRO_15_PRIV 0x40000000 // Coprocessor 15 privileged addess\r
+#define NVIC_COPRO_15_FULL 0xC0000000 // Coprocessor 15 full access\r
+#define NVIC_COPRO_14_M 0x30000000 // Coprocessor 14 access mask\r
+#define NVIC_COPRO_14_DENIED 0x00000000 // Coprocessor 14 access denied\r
+#define NVIC_COPRO_14_PRIV 0x10000000 // Coprocessor 14 privileged addess\r
+#define NVIC_COPRO_14_FULL 0x30000000 // Coprocessor 14 full access\r
+#define NVIC_COPRO_13_M 0x0C000000 // Coprocessor 13 access mask\r
+#define NVIC_COPRO_13_DENIED 0x00000000 // Coprocessor 13 access denied\r
+#define NVIC_COPRO_13_PRIV 0x04000000 // Coprocessor 13 privileged addess\r
+#define NVIC_COPRO_13_FULL 0x0C000000 // Coprocessor 13 full access\r
+#define NVIC_COPRO_12_M 0x03000000 // Coprocessor 12 access mask\r
+#define NVIC_COPRO_12_DENIED 0x00000000 // Coprocessor 12 access denied\r
+#define NVIC_COPRO_12_PRIV 0x01000000 // Coprocessor 12 privileged addess\r
+#define NVIC_COPRO_12_FULL 0x03000000 // Coprocessor 12 full access\r
+#define NVIC_COPRO_11_M 0x00C00000 // Coprocessor 11 access mask\r
+#define NVIC_COPRO_11_DENIED 0x00000000 // Coprocessor 11 access denied\r
+#define NVIC_COPRO_11_PRIV 0x00400000 // Coprocessor 11 privileged addess\r
+#define NVIC_COPRO_11_FULL 0x00C00000 // Coprocessor 11 full access\r
+#define NVIC_COPRO_10_M 0x00300000 // Coprocessor 10 access mask\r
+#define NVIC_COPRO_10_DENIED 0x00000000 // Coprocessor 10 access denied\r
+#define NVIC_COPRO_10_PRIV 0x00100000 // Coprocessor 10 privileged addess\r
+#define NVIC_COPRO_10_FULL 0x00300000 // Coprocessor 10 full access\r
+#define NVIC_COPRO_9_M 0x000C0000 // Coprocessor 9 access mask\r
+#define NVIC_COPRO_9_DENIED 0x00000000 // Coprocessor 9 access denied\r
+#define NVIC_COPRO_9_PRIV 0x00040000 // Coprocessor 9 privileged addess\r
+#define NVIC_COPRO_9_FULL 0x000C0000 // Coprocessor 9 full access\r
+#define NVIC_COPRO_8_M 0x00030000 // Coprocessor 8 access mask\r
+#define NVIC_COPRO_8_DENIED 0x00000000 // Coprocessor 8 access denied\r
+#define NVIC_COPRO_8_PRIV 0x00010000 // Coprocessor 8 privileged addess\r
+#define NVIC_COPRO_8_FULL 0x00030000 // Coprocessor 8 full access\r
+#define NVIC_COPRO_7_M 0x0000C000 // Coprocessor 7 access mask\r
+#define NVIC_COPRO_7_DENIED 0x00000000 // Coprocessor 7 access denied\r
+#define NVIC_COPRO_7_PRIV 0x00004000 // Coprocessor 7 privileged addess\r
+#define NVIC_COPRO_7_FULL 0x0000C000 // Coprocessor 7 full access\r
+#define NVIC_COPRO_6_M 0x00003000 // Coprocessor 6 access mask\r
+#define NVIC_COPRO_6_DENIED 0x00000000 // Coprocessor 6 access denied\r
+#define NVIC_COPRO_6_PRIV 0x00001000 // Coprocessor 6 privileged addess\r
+#define NVIC_COPRO_6_FULL 0x00003000 // Coprocessor 6 full access\r
+#define NVIC_COPRO_5_M 0x00000C00 // Coprocessor 5 access mask\r
+#define NVIC_COPRO_5_DENIED 0x00000000 // Coprocessor 5 access denied\r
+#define NVIC_COPRO_5_PRIV 0x00000400 // Coprocessor 5 privileged addess\r
+#define NVIC_COPRO_5_FULL 0x00000C00 // Coprocessor 5 full access\r
+#define NVIC_COPRO_4_M 0x00000300 // Coprocessor 4 access mask\r
+#define NVIC_COPRO_4_DENIED 0x00000000 // Coprocessor 4 access denied\r
+#define NVIC_COPRO_4_PRIV 0x00000100 // Coprocessor 4 privileged addess\r
+#define NVIC_COPRO_4_FULL 0x00000300 // Coprocessor 4 full access\r
+#define NVIC_COPRO_3_M 0x000000C0 // Coprocessor 3 access mask\r
+#define NVIC_COPRO_3_DENIED 0x00000000 // Coprocessor 3 access denied\r
+#define NVIC_COPRO_3_PRIV 0x00000040 // Coprocessor 3 privileged addess\r
+#define NVIC_COPRO_3_FULL 0x000000C0 // Coprocessor 3 full access\r
+#define NVIC_COPRO_2_M 0x00000030 // Coprocessor 2 access mask\r
+#define NVIC_COPRO_2_DENIED 0x00000000 // Coprocessor 2 access denied\r
+#define NVIC_COPRO_2_PRIV 0x00000010 // Coprocessor 2 privileged addess\r
+#define NVIC_COPRO_2_FULL 0x00000030 // Coprocessor 2 full access\r
+#define NVIC_COPRO_1_M 0x0000000C // Coprocessor 1 access mask\r
+#define NVIC_COPRO_1_DENIED 0x00000000 // Coprocessor 1 access denied\r
+#define NVIC_COPRO_1_PRIV 0x00000004 // Coprocessor 1 privileged addess\r
+#define NVIC_COPRO_1_FULL 0x0000000C // Coprocessor 1 full access\r
+#define NVIC_COPRO_0_M 0x00000003 // Coprocessor 0 access mask\r
+#define NVIC_COPRO_0_DENIED 0x00000000 // Coprocessor 0 access denied\r
+#define NVIC_COPRO_0_PRIV 0x00000001 // Coprocessor 0 privileged addess\r
+#define NVIC_COPRO_0_FULL 0x00000003 // Coprocessor 0 full access\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_MPU_TYPE register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_MPU_TYPE_IREGION_M 0x00FF0000 // Number of I regions\r
+#define NVIC_MPU_TYPE_DREGION_M 0x0000FF00 // Number of D regions\r
+#define NVIC_MPU_TYPE_SEPARATE 0x00000001 // Separate or unified MPU\r
+#define NVIC_MPU_TYPE_IREGION_S 16\r
+#define NVIC_MPU_TYPE_DREGION_S 8\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_MPU_CTRL register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_MPU_CTRL_HFNMIENA 0x00000002 // MPU enabled during faults\r
+#define NVIC_MPU_CTRL_ENABLE 0x00000001 // MPU enable\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_MPU_NUMBER register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_MPU_NUMBER_M 0x000000FF // MPU region to access\r
+#define NVIC_MPU_NUMBER_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_MPU_BASE register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_MPU_BASE_ADDR_M 0xFFFFFF00 // Base address\r
+#define NVIC_MPU_BASE_VALID 0x00000010 // Region number valid\r
+#define NVIC_MPU_BASE_REGION_M 0x0000000F // Region number\r
+#define NVIC_MPU_BASE_ADDR_S 8\r
+#define NVIC_MPU_BASE_REGION_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_MPU_ATTR register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_MPU_ATTR_ATTRS 0xFFFF0000 // Attributes\r
+#define NVIC_MPU_ATTR_SRD 0x0000FF00 // Sub-region disable\r
+#define NVIC_MPU_ATTR_SZENABLE 0x000000FF // Region size\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_DBG_CTRL register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_DBG_CTRL_DBGKEY_M 0xFFFF0000 // Debug key mask\r
+#define NVIC_DBG_CTRL_DBGKEY 0xA05F0000 // Debug key\r
+#define NVIC_DBG_CTRL_MON_PEND 0x00008000 // Pend the monitor\r
+#define NVIC_DBG_CTRL_MON_REQ 0x00004000 // Monitor request\r
+#define NVIC_DBG_CTRL_MON_EN 0x00002000 // Debug monitor enable\r
+#define NVIC_DBG_CTRL_MONSTEP 0x00001000 // Monitor step the core\r
+#define NVIC_DBG_CTRL_S_SLEEP 0x00000400 // Core is sleeping\r
+#define NVIC_DBG_CTRL_S_HALT 0x00000200 // Core status on halt\r
+#define NVIC_DBG_CTRL_S_REGRDY 0x00000100 // Register read/write available\r
+#define NVIC_DBG_CTRL_S_LOCKUP 0x00000080 // Core is locked up\r
+#define NVIC_DBG_CTRL_C_RESET 0x00000010 // Reset the core\r
+#define NVIC_DBG_CTRL_C_MASKINT 0x00000008 // Mask interrupts when stepping\r
+#define NVIC_DBG_CTRL_C_STEP 0x00000004 // Step the core\r
+#define NVIC_DBG_CTRL_C_HALT 0x00000002 // Halt the core\r
+#define NVIC_DBG_CTRL_C_DEBUGEN 0x00000001 // Enable debug\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_DBG_XFER register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_DBG_XFER_REG_WNR 0x00010000 // Write or not read\r
+#define NVIC_DBG_XFER_REG_SEL_M 0x0000001F // Register\r
+#define NVIC_DBG_XFER_REG_R0 0x00000000 // Register R0\r
+#define NVIC_DBG_XFER_REG_R1 0x00000001 // Register R1\r
+#define NVIC_DBG_XFER_REG_R2 0x00000002 // Register R2\r
+#define NVIC_DBG_XFER_REG_R3 0x00000003 // Register R3\r
+#define NVIC_DBG_XFER_REG_R4 0x00000004 // Register R4\r
+#define NVIC_DBG_XFER_REG_R5 0x00000005 // Register R5\r
+#define NVIC_DBG_XFER_REG_R6 0x00000006 // Register R6\r
+#define NVIC_DBG_XFER_REG_R7 0x00000007 // Register R7\r
+#define NVIC_DBG_XFER_REG_R8 0x00000008 // Register R8\r
+#define NVIC_DBG_XFER_REG_R9 0x00000009 // Register R9\r
+#define NVIC_DBG_XFER_REG_R10 0x0000000A // Register R10\r
+#define NVIC_DBG_XFER_REG_R11 0x0000000B // Register R11\r
+#define NVIC_DBG_XFER_REG_R12 0x0000000C // Register R12\r
+#define NVIC_DBG_XFER_REG_R13 0x0000000D // Register R13\r
+#define NVIC_DBG_XFER_REG_R14 0x0000000E // Register R14\r
+#define NVIC_DBG_XFER_REG_R15 0x0000000F // Register R15\r
+#define NVIC_DBG_XFER_REG_FLAGS 0x00000010 // xPSR/Flags register\r
+#define NVIC_DBG_XFER_REG_MSP 0x00000011 // Main SP\r
+#define NVIC_DBG_XFER_REG_PSP 0x00000012 // Process SP\r
+#define NVIC_DBG_XFER_REG_DSP 0x00000013 // Deep SP\r
+#define NVIC_DBG_XFER_REG_CFBP 0x00000014 // Control/Fault/BasePri/PriMask\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_DBG_DATA register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_DBG_DATA_M 0xFFFFFFFF // Data temporary cache\r
+#define NVIC_DBG_DATA_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_DBG_INT register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_DBG_INT_HARDERR 0x00000400 // Debug trap on hard fault\r
+#define NVIC_DBG_INT_INTERR 0x00000200 // Debug trap on interrupt errors\r
+#define NVIC_DBG_INT_BUSERR 0x00000100 // Debug trap on bus error\r
+#define NVIC_DBG_INT_STATERR 0x00000080 // Debug trap on usage fault state\r
+#define NVIC_DBG_INT_CHKERR 0x00000040 // Debug trap on usage fault check\r
+#define NVIC_DBG_INT_NOCPERR 0x00000020 // Debug trap on coprocessor error\r
+#define NVIC_DBG_INT_MMERR 0x00000010 // Debug trap on mem manage fault\r
+#define NVIC_DBG_INT_RESET 0x00000008 // Core reset status\r
+#define NVIC_DBG_INT_RSTPENDCLR 0x00000004 // Clear pending core reset\r
+#define NVIC_DBG_INT_RSTPENDING 0x00000002 // Core reset is pending\r
+#define NVIC_DBG_INT_RSTVCATCH 0x00000001 // Reset vector catch\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_SW_TRIG register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_SW_TRIG_INTID_M 0x000003FF // Interrupt to trigger\r
+#define NVIC_SW_TRIG_INTID_S 0\r
+\r
+#endif // __HW_NVIC_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_pwm.h - Defines and Macros for Pulse Width Modulation (PWM) ports\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_PWM_H__\r
+#define __HW_PWM_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// PWM Module Register Offsets.\r
+//\r
+//*****************************************************************************\r
+#define PWM_O_CTL 0x00000000 // PWM Master Control register\r
+#define PWM_O_SYNC 0x00000004 // PWM Time Base Sync register\r
+#define PWM_O_ENABLE 0x00000008 // PWM Output Enable register\r
+#define PWM_O_INVERT 0x0000000C // PWM Output Inversion register\r
+#define PWM_O_FAULT 0x00000010 // PWM Output Fault register\r
+#define PWM_O_INTEN 0x00000014 // PWM Interrupt Enable register\r
+#define PWM_O_RIS 0x00000018 // PWM Interrupt Raw Status reg.\r
+#define PWM_O_ISC 0x0000001C // PWM Interrupt Status register\r
+#define PWM_O_STATUS 0x00000020 // PWM Status register\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the PWM Master Control register.\r
+//\r
+//*****************************************************************************\r
+#define PWM_CTL_GLOBAL_SYNC2 0x00000004 // Global sync generator 2\r
+#define PWM_CTL_GLOBAL_SYNC1 0x00000002 // Global sync generator 1\r
+#define PWM_CTL_GLOBAL_SYNC0 0x00000001 // Global sync generator 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the PWM Time Base Sync register.\r
+//\r
+//*****************************************************************************\r
+#define PWM_SYNC_SYNC2 0x00000004 // Reset generator 2 counter\r
+#define PWM_SYNC_SYNC1 0x00000002 // Reset generator 1 counter\r
+#define PWM_SYNC_SYNC0 0x00000001 // Reset generator 0 counter\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the PWM Output Enable register.\r
+//\r
+//*****************************************************************************\r
+#define PWM_ENABLE_PWM5EN 0x00000020 // PWM5 pin enable\r
+#define PWM_ENABLE_PWM4EN 0x00000010 // PWM4 pin enable\r
+#define PWM_ENABLE_PWM3EN 0x00000008 // PWM3 pin enable\r
+#define PWM_ENABLE_PWM2EN 0x00000004 // PWM2 pin enable\r
+#define PWM_ENABLE_PWM1EN 0x00000002 // PWM1 pin enable\r
+#define PWM_ENABLE_PWM0EN 0x00000001 // PWM0 pin enable\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the PWM Inversion register.\r
+//\r
+//*****************************************************************************\r
+#define PWM_INVERT_PWM5INV 0x00000020 // PWM5 pin invert\r
+#define PWM_INVERT_PWM4INV 0x00000010 // PWM4 pin invert\r
+#define PWM_INVERT_PWM3INV 0x00000008 // PWM3 pin invert\r
+#define PWM_INVERT_PWM2INV 0x00000004 // PWM2 pin invert\r
+#define PWM_INVERT_PWM1INV 0x00000002 // PWM1 pin invert\r
+#define PWM_INVERT_PWM0INV 0x00000001 // PWM0 pin invert\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the PWM Fault register.\r
+//\r
+//*****************************************************************************\r
+#define PWM_FAULT_FAULT5 0x00000020 // PWM5 pin fault\r
+#define PWM_FAULT_FAULT4 0x00000010 // PWM5 pin fault\r
+#define PWM_FAULT_FAULT3 0x00000008 // PWM5 pin fault\r
+#define PWM_FAULT_FAULT2 0x00000004 // PWM5 pin fault\r
+#define PWM_FAULT_FAULT1 0x00000002 // PWM5 pin fault\r
+#define PWM_FAULT_FAULT0 0x00000001 // PWM5 pin fault\r
+\r
+//*****************************************************************************\r
+//\r
+// PWM Interrupt Register bit definitions.\r
+//\r
+//*****************************************************************************\r
+#define PWM_INT_INTFAULT 0x00010000 // Fault interrupt pending\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the PWM Status register.\r
+//\r
+//*****************************************************************************\r
+#define PWM_STATUS_FAULT 0x00000001 // Fault status\r
+\r
+//*****************************************************************************\r
+//\r
+// PWM Generator standard offsets.\r
+//\r
+//*****************************************************************************\r
+#define PWM_GEN_0_OFFSET 0x00000040 // PWM0 base\r
+#define PWM_GEN_1_OFFSET 0x00000080 // PWM1 base\r
+#define PWM_GEN_2_OFFSET 0x000000C0 // PWM2 base\r
+\r
+#define PWM_O_X_CTL 0x00000000 // Gen Control Reg\r
+#define PWM_O_X_INTEN 0x00000004 // Gen Int/Trig Enable Reg\r
+#define PWM_O_X_RIS 0x00000008 // Gen Raw Int Status Reg\r
+#define PWM_O_X_ISC 0x0000000C // Gen Int Status Reg\r
+#define PWM_O_X_LOAD 0x00000010 // Gen Load Reg\r
+#define PWM_O_X_COUNT 0x00000014 // Gen Counter Reg\r
+#define PWM_O_X_CMPA 0x00000018 // Gen Compare A Reg\r
+#define PWM_O_X_CMPB 0x0000001C // Gen Compare B Reg\r
+#define PWM_O_X_GENA 0x00000020 // Gen Generator A Ctrl Reg\r
+#define PWM_O_X_GENB 0x00000024 // Gen Generator B Ctrl Reg\r
+#define PWM_O_X_DBCTL 0x00000028 // Gen Dead Band Ctrl Reg\r
+#define PWM_O_X_DBRISE 0x0000002C // Gen DB Rising Edge Delay Reg\r
+#define PWM_O_X_DBFALL 0x00000030 // Gen DB Falling Edge Delay Reg\r
+\r
+//*****************************************************************************\r
+//\r
+// PWM_X Control Register bit definitions.\r
+//\r
+//*****************************************************************************\r
+#define PWM_X_CTL_ENABLE 0x00000001 // Master enable for gen block\r
+#define PWM_X_CTL_MODE 0x00000002 // Counter mode, down or up/down\r
+#define PWM_X_CTL_DEBUG 0x00000004 // Debug mode\r
+#define PWM_X_CTL_LOADUPD 0x00000008 // Update mode for the load reg\r
+#define PWM_X_CTL_CMPAUPD 0x00000010 // Update mode for comp A reg\r
+#define PWM_X_CTL_CMPBUPD 0x00000020 // Update mode for comp B reg\r
+\r
+//*****************************************************************************\r
+//\r
+// PWM_X Interrupt/Trigger Enable Register bit definitions.\r
+//\r
+//*****************************************************************************\r
+#define PWM_X_INTEN_INTCNTZERO 0x00000001 // Int if COUNT = 0\r
+#define PWM_X_INTEN_INTCNTLOAD 0x00000002 // Int if COUNT = LOAD\r
+#define PWM_X_INTEN_INTCMPAU 0x00000004 // Int if COUNT = CMPA U\r
+#define PWM_X_INTEN_INTCMPAD 0x00000008 // Int if COUNT = CMPA D\r
+#define PWM_X_INTEN_INTCMPBU 0x00000010 // Int if COUNT = CMPA U\r
+#define PWM_X_INTEN_INTCMPBD 0x00000020 // Int if COUNT = CMPA D\r
+#define PWM_X_INTEN_TRCNTZERO 0x00000100 // Trig if COUNT = 0\r
+#define PWM_X_INTEN_TRCNTLOAD 0x00000200 // Trig if COUNT = LOAD\r
+#define PWM_X_INTEN_TRCMPAU 0x00000400 // Trig if COUNT = CMPA U\r
+#define PWM_X_INTEN_TRCMPAD 0x00000800 // Trig if COUNT = CMPA D\r
+#define PWM_X_INTEN_TRCMPBU 0x00001000 // Trig if COUNT = CMPA U\r
+#define PWM_X_INTEN_TRCMPBD 0x00002000 // Trig if COUNT = CMPA D\r
+\r
+//*****************************************************************************\r
+//\r
+// PWM_X Raw Interrupt Status Register bit definitions.\r
+//\r
+//*****************************************************************************\r
+#define PWM_X_RIS_INTCNTZERO 0x00000001 // PWM_X_COUNT = 0 int\r
+#define PWM_X_RIS_INTCNTLOAD 0x00000002 // PWM_X_COUNT = PWM_X_LOAD int\r
+#define PWM_X_RIS_INTCMPAU 0x00000004 // PWM_X_COUNT = PWM_X_CMPA U int\r
+#define PWM_X_RIS_INTCMPAD 0x00000008 // PWM_X_COUNT = PWM_X_CMPA D int\r
+#define PWM_X_RIS_INTCMPBU 0x00000010 // PWM_X_COUNT = PWM_X_CMPB U int\r
+#define PWM_X_RIS_INTCMPBD 0x00000020 // PWM_X_COUNT = PWM_X_CMPB D int\r
+\r
+//*****************************************************************************\r
+//\r
+// PWM_X Interrupt Status Register bit definitions.\r
+//\r
+//*****************************************************************************\r
+#define PWM_X_INT_INTCNTZERO 0x00000001 // PWM_X_COUNT = 0 received\r
+#define PWM_X_INT_INTCNTLOAD 0x00000002 // PWM_X_COUNT = PWM_X_LOAD rcvd\r
+#define PWM_X_INT_INTCMPAU 0x00000004 // PWM_X_COUNT = PWM_X_CMPA U rcvd\r
+#define PWM_X_INT_INTCMPAD 0x00000008 // PWM_X_COUNT = PWM_X_CMPA D rcvd\r
+#define PWM_X_INT_INTCMPBU 0x00000010 // PWM_X_COUNT = PWM_X_CMPB U rcvd\r
+#define PWM_X_INT_INTCMPBD 0x00000020 // PWM_X_COUNT = PWM_X_CMPB D rcvd\r
+\r
+//*****************************************************************************\r
+//\r
+// PWM_X Generator A/B Control Register bit definitions.\r
+//\r
+//*****************************************************************************\r
+#define PWM_X_GEN_Y_ACTZERO 0x00000003 // Act PWM_X_COUNT = 0\r
+#define PWM_X_GEN_Y_ACTLOAD 0x0000000C // Act PWM_X_COUNT = PWM_X_LOAD\r
+#define PWM_X_GEN_Y_ACTCMPAU 0x00000030 // Act PWM_X_COUNT = PWM_X_CMPA U\r
+#define PWM_X_GEN_Y_ACTCMPAD 0x000000C0 // Act PWM_X_COUNT = PWM_X_CMPA D\r
+#define PWM_X_GEN_Y_ACTCMPBU 0x00000300 // Act PWM_X_COUNT = PWM_X_CMPB U\r
+#define PWM_X_GEN_Y_ACTCMPBD 0x00000C00 // Act PWM_X_COUNT = PWM_X_CMPB D\r
+\r
+//*****************************************************************************\r
+//\r
+// PWM_X Generator A/B Control Register action definitions.\r
+//\r
+//*****************************************************************************\r
+#define PWM_GEN_ACT_NONE 0x0 // Do nothing\r
+#define PWM_GEN_ACT_INV 0x1 // Invert the output signal\r
+#define PWM_GEN_ACT_ZERO 0x2 // Set the output signal to zero\r
+#define PWM_GEN_ACT_ONE 0x3 // Set the output signal to one\r
+#define PWM_GEN_ACT_ZERO_SHIFT 0 // Shift amount for the zero action\r
+#define PWM_GEN_ACT_LOAD_SHIFT 2 // Shift amount for the load action\r
+#define PWM_GEN_ACT_A_UP_SHIFT 4 // Shift amount for the A up action\r
+#define PWM_GEN_ACT_A_DN_SHIFT 6 // Shift amount for the A dn action\r
+#define PWM_GEN_ACT_B_UP_SHIFT 8 // Shift amount for the B up action\r
+#define PWM_GEN_ACT_B_DN_SHIFT 10 // Shift amount for the B dn action\r
+\r
+//*****************************************************************************\r
+//\r
+// PWM_X Dead Band Control Register bit definitions.\r
+//\r
+//*****************************************************************************\r
+#define PWM_DBCTL_ENABLE 0x00000001 // Enable dead band insertion\r
+\r
+//*****************************************************************************\r
+//\r
+// PWM Register reset values.\r
+//\r
+//*****************************************************************************\r
+#define PWM_RV_CTL 0x00000000 // Master control of the PWM module\r
+#define PWM_RV_SYNC 0x00000000 // Counter synch for PWM generators\r
+#define PWM_RV_ENABLE 0x00000000 // Master enable for the PWM\r
+ // output pins\r
+#define PWM_RV_INVERT 0x00000000 // Inversion control for\r
+ // PWM output pins\r
+#define PWM_RV_FAULT 0x00000000 // Fault handling for the PWM\r
+ // output pins\r
+#define PWM_RV_INTEN 0x00000000 // Interrupt enable\r
+#define PWM_RV_RIS 0x00000000 // Raw interrupt status\r
+#define PWM_RV_ISC 0x00000000 // Interrupt status and clearing\r
+#define PWM_RV_STATUS 0x00000000 // Status\r
+#define PWM_RV_X_CTL 0x00000000 // Master control of the PWM\r
+ // generator block\r
+#define PWM_RV_X_INTEN 0x00000000 // Interrupt and trigger enable\r
+#define PWM_RV_X_RIS 0x00000000 // Raw interrupt status\r
+#define PWM_RV_X_ISC 0x00000000 // Interrupt status and clearing\r
+#define PWM_RV_X_LOAD 0x00000000 // The load value for the counter\r
+#define PWM_RV_X_COUNT 0x00000000 // The current counter value\r
+#define PWM_RV_X_CMPA 0x00000000 // The comparator A value\r
+#define PWM_RV_X_CMPB 0x00000000 // The comparator B value\r
+#define PWM_RV_X_GENA 0x00000000 // Controls PWM generator A\r
+#define PWM_RV_X_GENB 0x00000000 // Controls PWM generator B\r
+#define PWM_RV_X_DBCTL 0x00000000 // Control the dead band generator\r
+#define PWM_RV_X_DBRISE 0x00000000 // The dead band rising edge delay\r
+ // count\r
+#define PWM_RV_X_DBFALL 0x00000000 // The dead band falling edge delay\r
+ // count\r
+\r
+#endif // __HW_PWM_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_qei.h - Macros used when accessing the QEI hardware.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_QEI_H__\r
+#define __HW_QEI_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the offsets of the QEI registers.\r
+//\r
+//*****************************************************************************\r
+#define QEI_O_CTL 0x00000000 // Configuration and control reg.\r
+#define QEI_O_STAT 0x00000004 // Status register\r
+#define QEI_O_POS 0x00000008 // Current position register\r
+#define QEI_O_MAXPOS 0x0000000C // Maximum position register\r
+#define QEI_O_LOAD 0x00000010 // Velocity timer load register\r
+#define QEI_O_TIME 0x00000014 // Velocity timer register\r
+#define QEI_O_COUNT 0x00000018 // Velocity pulse count register\r
+#define QEI_O_SPEED 0x0000001C // Velocity speed register\r
+#define QEI_O_INTEN 0x00000020 // Interrupt enable register\r
+#define QEI_O_RIS 0x00000024 // Raw interrupt status register\r
+#define QEI_O_ISC 0x00000028 // Interrupt status register\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the QEI_CTL register.\r
+//\r
+//*****************************************************************************\r
+#define QEI_CTL_STALLEN 0x00001000 // Stall enable\r
+#define QEI_CTL_INVI 0x00000800 // Invert Index input\r
+#define QEI_CTL_INVB 0x00000400 // Invert PhB input\r
+#define QEI_CTL_INVA 0x00000200 // Invert PhA input\r
+#define QEI_CTL_VELDIV_M 0x000001C0 // Velocity predivider mask\r
+#define QEI_CTL_VELDIV_1 0x00000000 // Predivide by 1\r
+#define QEI_CTL_VELDIV_2 0x00000040 // Predivide by 2\r
+#define QEI_CTL_VELDIV_4 0x00000080 // Predivide by 4\r
+#define QEI_CTL_VELDIV_8 0x000000C0 // Predivide by 8\r
+#define QEI_CTL_VELDIV_16 0x00000100 // Predivide by 16\r
+#define QEI_CTL_VELDIV_32 0x00000140 // Predivide by 32\r
+#define QEI_CTL_VELDIV_64 0x00000180 // Predivide by 64\r
+#define QEI_CTL_VELDIV_128 0x000001C0 // Predivide by 128\r
+#define QEI_CTL_VELEN 0x00000020 // Velocity enable\r
+#define QEI_CTL_RESMODE 0x00000010 // Position counter reset mode\r
+#define QEI_CTL_CAPMODE 0x00000008 // Edge capture mode\r
+#define QEI_CTL_SIGMODE 0x00000004 // Encoder signaling mode\r
+#define QEI_CTL_SWAP 0x00000002 // Swap input signals\r
+#define QEI_CTL_ENABLE 0x00000001 // QEI enable\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the QEI_STAT register.\r
+//\r
+//*****************************************************************************\r
+#define QEI_STAT_DIRECTION 0x00000002 // Direction of rotation\r
+#define QEI_STAT_ERROR 0x00000001 // Signalling error detected\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the QEI_POS register.\r
+//\r
+//*****************************************************************************\r
+#define QEI_POS_M 0xFFFFFFFF // Current encoder position\r
+#define QEI_POS_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the QEI_MAXPOS register.\r
+//\r
+//*****************************************************************************\r
+#define QEI_MAXPOS_M 0xFFFFFFFF // Maximum encoder position\r
+#define QEI_MAXPOS_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the QEI_LOAD register.\r
+//\r
+//*****************************************************************************\r
+#define QEI_LOAD_M 0xFFFFFFFF // Velocity timer load value\r
+#define QEI_LOAD_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the QEI_TIME register.\r
+//\r
+//*****************************************************************************\r
+#define QEI_TIME_M 0xFFFFFFFF // Velocity timer current value\r
+#define QEI_TIME_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the QEI_COUNT register.\r
+//\r
+//*****************************************************************************\r
+#define QEI_COUNT_M 0xFFFFFFFF // Encoder running pulse count\r
+#define QEI_COUNT_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the QEI_SPEED register.\r
+//\r
+//*****************************************************************************\r
+#define QEI_SPEED_M 0xFFFFFFFF // Encoder pulse count\r
+#define QEI_SPEED_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the QEI_INTEN register.\r
+//\r
+//*****************************************************************************\r
+#define QEI_INTEN_ERROR 0x00000008 // Phase error detected\r
+#define QEI_INTEN_DIR 0x00000004 // Direction change\r
+#define QEI_INTEN_TIMER 0x00000002 // Velocity timer expired\r
+#define QEI_INTEN_INDEX 0x00000001 // Index pulse detected\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the QEI_RIS register.\r
+//\r
+//*****************************************************************************\r
+#define QEI_RIS_ERROR 0x00000008 // Phase error detected\r
+#define QEI_RIS_DIR 0x00000004 // Direction change\r
+#define QEI_RIS_TIMER 0x00000002 // Velocity timer expired\r
+#define QEI_RIS_INDEX 0x00000001 // Index pulse detected\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the QEI_ISC register.\r
+//\r
+//*****************************************************************************\r
+#define QEI_INT_ERROR 0x00000008 // Phase error detected\r
+#define QEI_INT_DIR 0x00000004 // Direction change\r
+#define QEI_INT_TIMER 0x00000002 // Velocity timer expired\r
+#define QEI_INT_INDEX 0x00000001 // Index pulse detected\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the reset values for the QEI registers.\r
+//\r
+//*****************************************************************************\r
+#define QEI_RV_CTL 0x00000000 // Configuration and control reg.\r
+#define QEI_RV_STAT 0x00000000 // Status register\r
+#define QEI_RV_POS 0x00000000 // Current position register\r
+#define QEI_RV_MAXPOS 0x00000000 // Maximum position register\r
+#define QEI_RV_LOAD 0x00000000 // Velocity timer load register\r
+#define QEI_RV_TIME 0x00000000 // Velocity timer register\r
+#define QEI_RV_COUNT 0x00000000 // Velocity pulse count register\r
+#define QEI_RV_SPEED 0x00000000 // Velocity speed register\r
+#define QEI_RV_INTEN 0x00000000 // Interrupt enable register\r
+#define QEI_RV_RIS 0x00000000 // Raw interrupt status register\r
+#define QEI_RV_ISC 0x00000000 // Interrupt status register\r
+\r
+#endif // __HW_QEI_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_ssi.h - Macros used when accessing the SSI hardware.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_SSI_H__\r
+#define __HW_SSI_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the offsets of the SSI registers.\r
+//\r
+//*****************************************************************************\r
+#define SSI_O_CR0 0x00000000 // Control register 0\r
+#define SSI_O_CR1 0x00000004 // Control register 1\r
+#define SSI_O_DR 0x00000008 // Data register\r
+#define SSI_O_SR 0x0000000C // Status register\r
+#define SSI_O_CPSR 0x00000010 // Clock prescale register\r
+#define SSI_O_IM 0x00000014 // Int mask set and clear register\r
+#define SSI_O_RIS 0x00000018 // Raw interrupt register\r
+#define SSI_O_MIS 0x0000001C // Masked interrupt register\r
+#define SSI_O_ICR 0x00000020 // Interrupt clear register\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SSI Control register 0.\r
+//\r
+//*****************************************************************************\r
+#define SSI_CR0_SCR 0x0000FF00 // Serial clock rate\r
+#define SSI_CR0_SPH 0x00000080 // SSPCLKOUT phase\r
+#define SSI_CR0_SPO 0x00000040 // SSPCLKOUT polarity\r
+#define SSI_CR0_FRF_MASK 0x00000030 // Frame format mask\r
+#define SSI_CR0_FRF_MOTO 0x00000000 // Motorola SPI frame format\r
+#define SSI_CR0_FRF_TI 0x00000010 // TI sync serial frame format\r
+#define SSI_CR0_FRF_NMW 0x00000020 // National Microwire frame format\r
+#define SSI_CR0_DSS 0x0000000F // Data size select\r
+#define SSI_CR0_DSS_4 0x00000003 // 4 bit data\r
+#define SSI_CR0_DSS_5 0x00000004 // 5 bit data\r
+#define SSI_CR0_DSS_6 0x00000005 // 6 bit data\r
+#define SSI_CR0_DSS_7 0x00000006 // 7 bit data\r
+#define SSI_CR0_DSS_8 0x00000007 // 8 bit data\r
+#define SSI_CR0_DSS_9 0x00000008 // 9 bit data\r
+#define SSI_CR0_DSS_10 0x00000009 // 10 bit data\r
+#define SSI_CR0_DSS_11 0x0000000A // 11 bit data\r
+#define SSI_CR0_DSS_12 0x0000000B // 12 bit data\r
+#define SSI_CR0_DSS_13 0x0000000C // 13 bit data\r
+#define SSI_CR0_DSS_14 0x0000000D // 14 bit data\r
+#define SSI_CR0_DSS_15 0x0000000E // 15 bit data\r
+#define SSI_CR0_DSS_16 0x0000000F // 16 bit data\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SSI Control register 1.\r
+//\r
+//*****************************************************************************\r
+#define SSI_CR1_SOD 0x00000008 // Slave mode output disable\r
+#define SSI_CR1_MS 0x00000004 // Master or slave mode select\r
+#define SSI_CR1_SSE 0x00000002 // Sync serial port enable\r
+#define SSI_CR1_LBM 0x00000001 // Loopback mode\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SSI Status register.\r
+//\r
+//*****************************************************************************\r
+#define SSI_SR_BSY 0x00000010 // SSI busy\r
+#define SSI_SR_RFF 0x00000008 // RX FIFO full\r
+#define SSI_SR_RNE 0x00000004 // RX FIFO not empty\r
+#define SSI_SR_TNF 0x00000002 // TX FIFO not full\r
+#define SSI_SR_TFE 0x00000001 // TX FIFO empty\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SSI clock prescale register.\r
+//\r
+//*****************************************************************************\r
+#define SSI_CPSR_CPSDVSR_MASK 0x000000FF // Clock prescale\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define information concerning the SSI Data register.\r
+//\r
+//*****************************************************************************\r
+#define TX_FIFO_SIZE (8) // Number of entries in the TX FIFO\r
+#define RX_FIFO_SIZE (8) // Number of entries in the RX FIFO\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the interrupt mask set and clear,\r
+// raw interrupt, masked interrupt, and interrupt clear registers.\r
+//\r
+//*****************************************************************************\r
+#define SSI_INT_TXFF 0x00000008 // TX FIFO interrupt\r
+#define SSI_INT_RXFF 0x00000004 // RX FIFO interrupt\r
+#define SSI_INT_RXTO 0x00000002 // RX timeout interrupt\r
+#define SSI_INT_RXOR 0x00000001 // RX overrun interrupt\r
+\r
+#endif // __HW_SSI_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_sysctl.h - Macros used when accessing the system control hardware.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_SYSCTL_H__\r
+#define __HW_SYSCTL_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the addresses of the system control registers.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_DID0 0x400fe000 // Device identification register 0\r
+#define SYSCTL_DID1 0x400fe004 // Device identification register 1\r
+#define SYSCTL_DC0 0x400fe008 // Device capabilities register 0\r
+#define SYSCTL_DC1 0x400fe010 // Device capabilities register 1\r
+#define SYSCTL_DC2 0x400fe014 // Device capabilities register 2\r
+#define SYSCTL_DC3 0x400fe018 // Device capabilities register 3\r
+#define SYSCTL_DC4 0x400fe01C // Device capabilities register 4\r
+#define SYSCTL_PBORCTL 0x400fe030 // POR/BOR reset control register\r
+#define SYSCTL_LDOPCTL 0x400fe034 // LDO power control register\r
+#define SYSCTL_SRCR0 0x400fe040 // Software reset control reg 0\r
+#define SYSCTL_SRCR1 0x400fe044 // Software reset control reg 1\r
+#define SYSCTL_SRCR2 0x400fe048 // Software reset control reg 2\r
+#define SYSCTL_RIS 0x400fe050 // Raw interrupt status register\r
+#define SYSCTL_IMC 0x400fe054 // Interrupt mask/control register\r
+#define SYSCTL_MISC 0x400fe058 // Interrupt status register\r
+#define SYSCTL_RESC 0x400fe05c // Reset cause register\r
+#define SYSCTL_RCC 0x400fe060 // Run-mode clock config register\r
+#define SYSCTL_PLLCFG 0x400fe064 // PLL configuration register\r
+#define SYSCTL_RCC2 0x400fe070 // Run-mode clock config register 2\r
+#define SYSCTL_RCGC0 0x400fe100 // Run-mode clock gating register 0\r
+#define SYSCTL_RCGC1 0x400fe104 // Run-mode clock gating register 1\r
+#define SYSCTL_RCGC2 0x400fe108 // Run-mode clock gating register 2\r
+#define SYSCTL_SCGC0 0x400fe110 // Sleep-mode clock gating reg 0\r
+#define SYSCTL_SCGC1 0x400fe114 // Sleep-mode clock gating reg 1\r
+#define SYSCTL_SCGC2 0x400fe118 // Sleep-mode clock gating reg 2\r
+#define SYSCTL_DCGC0 0x400fe120 // Deep Sleep-mode clock gate reg 0\r
+#define SYSCTL_DCGC1 0x400fe124 // Deep Sleep-mode clock gate reg 1\r
+#define SYSCTL_DCGC2 0x400fe128 // Deep Sleep-mode clock gate reg 2\r
+#define SYSCTL_DSLPCLKCFG 0x400fe144 // Deep Sleep-mode clock config reg\r
+#define SYSCTL_CLKVCLR 0x400fe150 // Clock verifcation clear register\r
+#define SYSCTL_LDOARST 0x400fe160 // LDO reset control register\r
+#define SYSCTL_USER0 0x400fe1e0 // NV User Register 0\r
+#define SYSCTL_USER1 0x400fe1e4 // NV User Register 1\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_DID0 register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_DID0_VER_MASK 0x70000000 // DID0 version mask\r
+#define SYSCTL_DID0_VER_0 0x00000000 // DID0 version 0\r
+#define SYSCTL_DID0_VER_1 0x10000000 // DID0 version 1\r
+#define SYSCTL_DID0_CLASS_MASK 0x00FF0000 // Device Class\r
+#define SYSCTL_DID0_CLASS_SANDSTORM 0x00000000 // LM3Snnn Sandstorm Device\r
+#define SYSCTL_DID0_CLASS_FURY 0x00010000 // LM3Snnnn Fury Device\r
+#define SYSCTL_DID0_MAJ_MASK 0x0000FF00 // Major revision mask\r
+#define SYSCTL_DID0_MAJ_A 0x00000000 // Major revision A\r
+#define SYSCTL_DID0_MAJ_B 0x00000100 // Major revision B\r
+#define SYSCTL_DID0_MAJ_C 0x00000200 // Major revision C\r
+#define SYSCTL_DID0_MIN_MASK 0x000000FF // Minor revision mask\r
+#define SYSCTL_DID0_MIN_0 0x00000000 // Minor revision 0\r
+#define SYSCTL_DID0_MIN_1 0x00000001 // Minor revision 1\r
+#define SYSCTL_DID0_MIN_2 0x00000002 // Minor revision 2\r
+#define SYSCTL_DID0_MIN_3 0x00000003 // Minor revision 3\r
+#define SYSCTL_DID0_MIN_4 0x00000004 // Minor revision 4\r
+#define SYSCTL_DID0_MIN_5 0x00000005 // Minor revision 5\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_DID1 register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_DID1_VER_MASK 0xF0000000 // Register version mask\r
+#define SYSCTL_DID1_FAM_MASK 0x0F000000 // Family mask\r
+#define SYSCTL_DID1_FAM_S 0x00000000 // Stellaris family\r
+#define SYSCTL_DID1_PRTNO_MASK 0x00FF0000 // Part number mask\r
+#define SYSCTL_DID1_PRTNO_101 0x00010000 // LM3S101\r
+#define SYSCTL_DID1_PRTNO_102 0x00020000 // LM3S102\r
+#define SYSCTL_DID1_PRTNO_301 0x00110000 // LM3S301\r
+#define SYSCTL_DID1_PRTNO_310 0x00120000 // LM3S310\r
+#define SYSCTL_DID1_PRTNO_315 0x00130000 // LM3S315\r
+#define SYSCTL_DID1_PRTNO_316 0x00140000 // LM3S316\r
+#define SYSCTL_DID1_PRTNO_317 0x00170000 // LM3S317\r
+#define SYSCTL_DID1_PRTNO_328 0x00150000 // LM3S328\r
+#define SYSCTL_DID1_PRTNO_601 0x00210000 // LM3S601\r
+#define SYSCTL_DID1_PRTNO_610 0x00220000 // LM3S610\r
+#define SYSCTL_DID1_PRTNO_611 0x00230000 // LM3S611\r
+#define SYSCTL_DID1_PRTNO_612 0x00240000 // LM3S612\r
+#define SYSCTL_DID1_PRTNO_613 0x00250000 // LM3S613\r
+#define SYSCTL_DID1_PRTNO_615 0x00260000 // LM3S615\r
+#define SYSCTL_DID1_PRTNO_617 0x00280000 // LM3S617\r
+#define SYSCTL_DID1_PRTNO_618 0x00290000 // LM3S618\r
+#define SYSCTL_DID1_PRTNO_628 0x00270000 // LM3S628\r
+#define SYSCTL_DID1_PRTNO_801 0x00310000 // LM3S801\r
+#define SYSCTL_DID1_PRTNO_811 0x00320000 // LM3S811\r
+#define SYSCTL_DID1_PRTNO_812 0x00330000 // LM3S812\r
+#define SYSCTL_DID1_PRTNO_815 0x00340000 // LM3S815\r
+#define SYSCTL_DID1_PRTNO_817 0x00360000 // LM3S817\r
+#define SYSCTL_DID1_PRTNO_818 0x00370000 // LM3S818\r
+#define SYSCTL_DID1_PRTNO_828 0x00350000 // LM3S828\r
+#define SYSCTL_DID1_PRTNO_2110 0x00510000 // LM3S2110\r
+#define SYSCTL_DID1_PRTNO_2139 0x00840000 // LM3S2139\r
+#define SYSCTL_DID1_PRTNO_2410 0x00A20000 // LM3S2410\r
+#define SYSCTL_DID1_PRTNO_2412 0x00590000 // LM3S2412\r
+#define SYSCTL_DID1_PRTNO_2432 0x00560000 // LM3S2432\r
+#define SYSCTL_DID1_PRTNO_2533 0x005A0000 // LM3S2533\r
+#define SYSCTL_DID1_PRTNO_2620 0x00570000 // LM3S2620\r
+#define SYSCTL_DID1_PRTNO_2637 0x00850000 // LM3S2637\r
+#define SYSCTL_DID1_PRTNO_2651 0x00530000 // LM3S2651\r
+#define SYSCTL_DID1_PRTNO_2730 0x00A40000 // LM3S2730\r
+#define SYSCTL_DID1_PRTNO_2739 0x00520000 // LM3S2739\r
+#define SYSCTL_DID1_PRTNO_2939 0x00540000 // LM3S2939\r
+#define SYSCTL_DID1_PRTNO_2948 0x008F0000 // LM3S2948\r
+#define SYSCTL_DID1_PRTNO_2950 0x00580000 // LM3S2950\r
+#define SYSCTL_DID1_PRTNO_2965 0x00550000 // LM3S2965\r
+#define SYSCTL_DID1_PRTNO_6100 0x00A10000 // LM3S6100\r
+#define SYSCTL_DID1_PRTNO_6110 0x00740000 // LM3S6110\r
+#define SYSCTL_DID1_PRTNO_6420 0x00A50000 // LM3S6420\r
+#define SYSCTL_DID1_PRTNO_6422 0x00820000 // LM3S6422\r
+#define SYSCTL_DID1_PRTNO_6432 0x00750000 // LM3S6432\r
+#define SYSCTL_DID1_PRTNO_6610 0x00710000 // LM3S6610\r
+#define SYSCTL_DID1_PRTNO_6633 0x00830000 // LM3S6633\r
+#define SYSCTL_DID1_PRTNO_6637 0x008B0000 // LM3S6637\r
+#define SYSCTL_DID1_PRTNO_6730 0x00A30000 // LM3S6730\r
+#define SYSCTL_DID1_PRTNO_6938 0x00890000 // LM3S6938\r
+#define SYSCTL_DID1_PRTNO_6952 0x00780000 // LM3S6952\r
+#define SYSCTL_DID1_PRTNO_6965 0x00730000 // LM3S6965\r
+#define SYSCTL_DID1_PINCNT_MASK 0x0000E000 // Pin count\r
+#define SYSCTL_DID1_PINCNT_100 0x00004000 // 100 pin package\r
+#define SYSCTL_DID1_TEMP_MASK 0x000000E0 // Temperature range mask\r
+#define SYSCTL_DID1_TEMP_C 0x00000000 // Commercial temp range (0..70C)\r
+#define SYSCTL_DID1_TEMP_I 0x00000020 // Industrial temp range (-40..85C)\r
+#define SYSCTL_DID1_PKG_MASK 0x00000018 // Package mask\r
+#define SYSCTL_DID1_PKG_28SOIC 0x00000000 // 28-pin SOIC\r
+#define SYSCTL_DID1_PKG_48QFP 0x00000008 // 48-pin QFP\r
+#define SYSCTL_DID1_ROHS 0x00000004 // Part is RoHS compliant\r
+#define SYSCTL_DID1_QUAL_MASK 0x00000003 // Qualification status mask\r
+#define SYSCTL_DID1_QUAL_ES 0x00000000 // Engineering sample (unqualified)\r
+#define SYSCTL_DID1_QUAL_PP 0x00000001 // Pilot production (unqualified)\r
+#define SYSCTL_DID1_QUAL_FQ 0x00000002 // Fully qualified\r
+#define SYSCTL_DID1_PRTNO_SHIFT 16\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_DC0 register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_DC0_SRAMSZ_MASK 0xFFFF0000 // SRAM size mask\r
+#define SYSCTL_DC0_SRAMSZ_2KB 0x00070000 // 2 KB of SRAM\r
+#define SYSCTL_DC0_SRAMSZ_4KB 0x000F0000 // 4 KB of SRAM\r
+#define SYSCTL_DC0_SRAMSZ_8KB 0x001F0000 // 8 KB of SRAM\r
+#define SYSCTL_DC0_SRAMSZ_16KB 0x003F0000 // 16 KB of SRAM\r
+#define SYSCTL_DC0_SRAMSZ_32KB 0x007F0000 // 32 KB of SRAM\r
+#define SYSCTL_DC0_SRAMSZ_64KB 0x00FF0000 // 64 KB of SRAM\r
+#define SYSCTL_DC0_FLASHSZ_MASK 0x0000FFFF // Flash size mask\r
+#define SYSCTL_DC0_FLASHSZ_8KB 0x00000003 // 8 KB of flash\r
+#define SYSCTL_DC0_FLASHSZ_16KB 0x00000007 // 16 KB of flash\r
+#define SYSCTL_DC0_FLASHSZ_32KB 0x0000000F // 32 KB of flash\r
+#define SYSCTL_DC0_FLASHSZ_64KB 0x0000001F // 64 KB of flash\r
+#define SYSCTL_DC0_FLASHSZ_96KB 0x0000002F // 96 KB of flash\r
+#define SYSCTL_DC0_FLASHSZ_128K 0x0000003F // 128 KB of flash\r
+#define SYSCTL_DC0_FLASHSZ_256K 0x0000007F // 256 KB of flash\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_DC1 register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_DC1_CAN1 0x02000000 // CAN1 module present\r
+#define SYSCTL_DC1_CAN0 0x01000000 // CAN0 module present\r
+#define SYSCTL_DC1_PWM 0x00100000 // PWM module present\r
+#define SYSCTL_DC1_ADC 0x00010000 // ADC module present\r
+#define SYSCTL_DC1_SYSDIV_MASK 0x0000F000 // Minimum system divider mask\r
+#define SYSCTL_DC1_ADCSPD_MASK 0x00000F00 // ADC speed mask\r
+#define SYSCTL_DC1_ADCSPD_1M 0x00000300 // 1Msps ADC\r
+#define SYSCTL_DC1_ADCSPD_500K 0x00000200 // 500Ksps ADC\r
+#define SYSCTL_DC1_ADCSPD_250K 0x00000100 // 250Ksps ADC\r
+#define SYSCTL_DC1_ADCSPD_125K 0x00000000 // 125Ksps ADC\r
+#define SYSCTL_DC1_MPU 0x00000080 // Cortex M3 MPU present\r
+#define SYSCTL_DC1_HIB 0x00000040 // Hibernation module present\r
+#define SYSCTL_DC1_TEMP 0x00000020 // Temperature sensor present\r
+#define SYSCTL_DC1_PLL 0x00000010 // PLL present\r
+#define SYSCTL_DC1_WDOG 0x00000008 // Watchdog present\r
+#define SYSCTL_DC1_SWO 0x00000004 // Serial wire output present\r
+#define SYSCTL_DC1_SWD 0x00000002 // Serial wire debug present\r
+#define SYSCTL_DC1_JTAG 0x00000001 // JTAG debug present\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_DC2 register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_DC2_COMP2 0x04000000 // Analog comparator 2 present\r
+#define SYSCTL_DC2_COMP1 0x02000000 // Analog comparator 1 present\r
+#define SYSCTL_DC2_COMP0 0x01000000 // Analog comparator 0 present\r
+#define SYSCTL_DC2_TIMER3 0x00080000 // Timer 3 present\r
+#define SYSCTL_DC2_TIMER2 0x00040000 // Timer 2 present\r
+#define SYSCTL_DC2_TIMER1 0x00020000 // Timer 1 present\r
+#define SYSCTL_DC2_TIMER0 0x00010000 // Timer 0 present\r
+#define SYSCTL_DC2_I2C1 0x00002000 // I2C 1 present\r
+#define SYSCTL_DC2_I2C0 0x00001000 // I2C 0 present\r
+#ifndef DEPRECATED\r
+#define SYSCTL_DC2_I2C 0x00001000 // I2C present\r
+#endif\r
+#define SYSCTL_DC2_QEI1 0x00000200 // QEI 1 present\r
+#define SYSCTL_DC2_QEI0 0x00000100 // QEI 0 present\r
+#ifndef DEPRECATED\r
+#define SYSCTL_DC2_QEI 0x00000100 // QEI present\r
+#endif\r
+#define SYSCTL_DC2_SSI1 0x00000020 // SSI 1 present\r
+#define SYSCTL_DC2_SSI0 0x00000010 // SSI 0 present\r
+#ifndef DEPRECATED\r
+#define SYSCTL_DC2_SSI 0x00000010 // SSI present\r
+#endif\r
+#define SYSCTL_DC2_UART2 0x00000004 // UART 2 present\r
+#define SYSCTL_DC2_UART1 0x00000002 // UART 1 present\r
+#define SYSCTL_DC2_UART0 0x00000001 // UART 0 present\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_DC3 register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_DC3_32KHZ 0x80000000 // 32kHz pin present\r
+#define SYSCTL_DC3_CCP5 0x20000000 // CCP5 pin present\r
+#define SYSCTL_DC3_CCP4 0x10000000 // CCP4 pin present\r
+#define SYSCTL_DC3_CCP3 0x08000000 // CCP3 pin present\r
+#define SYSCTL_DC3_CCP2 0x04000000 // CCP2 pin present\r
+#define SYSCTL_DC3_CCP1 0x02000000 // CCP1 pin present\r
+#define SYSCTL_DC3_CCP0 0x01000000 // CCP0 pin present\r
+#define SYSCTL_DC3_ADC7 0x00800000 // ADC7 pin present\r
+#define SYSCTL_DC3_ADC6 0x00400000 // ADC6 pin present\r
+#define SYSCTL_DC3_ADC5 0x00200000 // ADC5 pin present\r
+#define SYSCTL_DC3_ADC4 0x00100000 // ADC4 pin present\r
+#define SYSCTL_DC3_ADC3 0x00080000 // ADC3 pin present\r
+#define SYSCTL_DC3_ADC2 0x00040000 // ADC2 pin present\r
+#define SYSCTL_DC3_ADC1 0x00020000 // ADC1 pin present\r
+#define SYSCTL_DC3_ADC0 0x00010000 // ADC0 pin present\r
+#define SYSCTL_DC3_MC_FAULT0 0x00008000 // MC0 fault pin present\r
+#define SYSCTL_DC3_C2O 0x00004000 // C2o pin present\r
+#define SYSCTL_DC3_C2PLUS 0x00002000 // C2+ pin present\r
+#define SYSCTL_DC3_C2MINUS 0x00001000 // C2- pin present\r
+#define SYSCTL_DC3_C1O 0x00000800 // C1o pin present\r
+#define SYSCTL_DC3_C1PLUS 0x00000400 // C1+ pin present\r
+#define SYSCTL_DC3_C1MINUS 0x00000200 // C1- pin present\r
+#define SYSCTL_DC3_C0O 0x00000100 // C0o pin present\r
+#define SYSCTL_DC3_C0PLUS 0x00000080 // C0+ pin present\r
+#define SYSCTL_DC3_C0MINUS 0x00000040 // C0- pin present\r
+#define SYSCTL_DC3_PWM5 0x00000020 // PWM5 pin present\r
+#define SYSCTL_DC3_PWM4 0x00000010 // PWM4 pin present\r
+#define SYSCTL_DC3_PWM3 0x00000008 // PWM3 pin present\r
+#define SYSCTL_DC3_PWM2 0x00000004 // PWM2 pin present\r
+#define SYSCTL_DC3_PWM1 0x00000002 // PWM1 pin present\r
+#define SYSCTL_DC3_PWM0 0x00000001 // PWM0 pin present\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_DC4 register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_DC4_ETH 0x50000000 // Ethernet present\r
+#define SYSCTL_DC4_GPIOH 0x00000080 // GPIO port H present\r
+#define SYSCTL_DC4_GPIOG 0x00000040 // GPIO port G present\r
+#define SYSCTL_DC4_GPIOF 0x00000020 // GPIO port F present\r
+#define SYSCTL_DC4_GPIOE 0x00000010 // GPIO port E present\r
+#define SYSCTL_DC4_GPIOD 0x00000008 // GPIO port D present\r
+#define SYSCTL_DC4_GPIOC 0x00000004 // GPIO port C present\r
+#define SYSCTL_DC4_GPIOB 0x00000002 // GPIO port B present\r
+#define SYSCTL_DC4_GPIOA 0x00000001 // GPIO port A present\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_PBORCTL register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_PBORCTL_BOR_MASK 0x0000FFFC // BOR wait timer\r
+#define SYSCTL_PBORCTL_BORIOR 0x00000002 // BOR interrupt or reset\r
+#define SYSCTL_PBORCTL_BORWT 0x00000001 // BOR wait and check for noise\r
+#define SYSCTL_PBORCTL_BOR_SH 2\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_LDOPCTL register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_LDOPCTL_MASK 0x0000003F // Voltage adjust mask\r
+#define SYSCTL_LDOPCTL_2_25V 0x00000005 // LDO output of 2.25V\r
+#define SYSCTL_LDOPCTL_2_30V 0x00000004 // LDO output of 2.30V\r
+#define SYSCTL_LDOPCTL_2_35V 0x00000003 // LDO output of 2.35V\r
+#define SYSCTL_LDOPCTL_2_40V 0x00000002 // LDO output of 2.40V\r
+#define SYSCTL_LDOPCTL_2_45V 0x00000001 // LDO output of 2.45V\r
+#define SYSCTL_LDOPCTL_2_50V 0x00000000 // LDO output of 2.50V\r
+#define SYSCTL_LDOPCTL_2_55V 0x0000001F // LDO output of 2.55V\r
+#define SYSCTL_LDOPCTL_2_60V 0x0000001E // LDO output of 2.60V\r
+#define SYSCTL_LDOPCTL_2_65V 0x0000001D // LDO output of 2.65V\r
+#define SYSCTL_LDOPCTL_2_70V 0x0000001C // LDO output of 2.70V\r
+#define SYSCTL_LDOPCTL_2_75V 0x0000001B // LDO output of 2.75V\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_SRCR0, SYSCTL_RCGC0,\r
+// SYSCTL_SCGC0, and SYSCTL_DCGC0 registers.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_SET0_CAN1 0x02000000 // CAN 1 module\r
+#define SYSCTL_SET0_CAN0 0x01000000 // CAN 0 module\r
+#define SYSCTL_SET0_PWM 0x00100000 // PWM module\r
+#define SYSCTL_SET0_ADC 0x00010000 // ADC module\r
+#define SYSCTL_SET0_ADCSPD_MASK 0x00000F00 // ADC speed mask\r
+#define SYSCTL_SET0_ADCSPD_1M 0x00000300 // 1Msps ADC\r
+#define SYSCTL_SET0_ADCSPD_500K 0x00000200 // 500Ksps ADC\r
+#define SYSCTL_SET0_ADCSPD_250K 0x00000100 // 250Ksps ADC\r
+#define SYSCTL_SET0_ADCSPD_125K 0x00000000 // 125Ksps ADC\r
+#define SYSCTL_SET0_HIB 0x00000040 // Hibernation module\r
+#define SYSCTL_SET0_WDOG 0x00000008 // Watchdog module\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_SRCR1, SYSCTL_RCGC1,\r
+// SYSCTL_SCGC1, and SYSCTL_DCGC1 registers.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_SET1_COMP2 0x04000000 // Analog comparator module 2\r
+#define SYSCTL_SET1_COMP1 0x02000000 // Analog comparator module 1\r
+#define SYSCTL_SET1_COMP0 0x01000000 // Analog comparator module 0\r
+#define SYSCTL_SET1_TIMER3 0x00080000 // Timer module 3\r
+#define SYSCTL_SET1_TIMER2 0x00040000 // Timer module 2\r
+#define SYSCTL_SET1_TIMER1 0x00020000 // Timer module 1\r
+#define SYSCTL_SET1_TIMER0 0x00010000 // Timer module 0\r
+#define SYSCTL_SET1_I2C1 0x00002000 // I2C module 1\r
+#define SYSCTL_SET1_I2C0 0x00001000 // I2C module 0\r
+#ifndef DEPRECATED\r
+#define SYSCTL_SET1_I2C 0x00001000 // I2C module\r
+#endif\r
+#define SYSCTL_SET1_QEI1 0x00000200 // QEI module 1\r
+#define SYSCTL_SET1_QEI0 0x00000100 // QEI module 0\r
+#ifndef DEPRECATED\r
+#define SYSCTL_SET1_QEI 0x00000100 // QEI module\r
+#endif\r
+#define SYSCTL_SET1_SSI1 0x00000020 // SSI module 1\r
+#define SYSCTL_SET1_SSI0 0x00000010 // SSI module 0\r
+#ifndef DEPRECATED\r
+#define SYSCTL_SET1_SSI 0x00000010 // SSI module\r
+#endif\r
+#define SYSCTL_SET1_UART2 0x00000004 // UART module 2\r
+#define SYSCTL_SET1_UART1 0x00000002 // UART module 1\r
+#define SYSCTL_SET1_UART0 0x00000001 // UART module 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_SRCR2, SYSCTL_RCGC2,\r
+// SYSCTL_SCGC2, and SYSCTL_DCGC2 registers.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_SET2_ETH 0x50000000 // ETH module\r
+#define SYSCTL_SET2_GPIOH 0x00000080 // GPIO H module\r
+#define SYSCTL_SET2_GPIOG 0x00000040 // GPIO G module\r
+#define SYSCTL_SET2_GPIOF 0x00000020 // GPIO F module\r
+#define SYSCTL_SET2_GPIOE 0x00000010 // GPIO E module\r
+#define SYSCTL_SET2_GPIOD 0x00000008 // GPIO D module\r
+#define SYSCTL_SET2_GPIOC 0x00000004 // GPIO C module\r
+#define SYSCTL_SET2_GPIOB 0x00000002 // GPIO B module\r
+#define SYSCTL_SET2_GPIOA 0x00000001 // GIPO A module\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_RIS, SYSCTL_IMC, and\r
+// SYSCTL_IMS registers.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_INT_PLL_LOCK 0x00000040 // PLL lock interrupt\r
+#define SYSCTL_INT_CUR_LIMIT 0x00000020 // Current limit interrupt\r
+#define SYSCTL_INT_IOSC_FAIL 0x00000010 // Internal oscillator failure int\r
+#define SYSCTL_INT_MOSC_FAIL 0x00000008 // Main oscillator failure int\r
+#define SYSCTL_INT_POR 0x00000004 // Power on reset interrupt\r
+#define SYSCTL_INT_BOR 0x00000002 // Brown out interrupt\r
+#define SYSCTL_INT_PLL_FAIL 0x00000001 // PLL failure interrupt\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_RESC register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_RESC_LDO 0x00000020 // LDO power OK lost reset\r
+#define SYSCTL_RESC_SW 0x00000010 // Software reset\r
+#define SYSCTL_RESC_WDOG 0x00000008 // Watchdog reset\r
+#define SYSCTL_RESC_BOR 0x00000004 // Brown-out reset\r
+#define SYSCTL_RESC_POR 0x00000002 // Power on reset\r
+#define SYSCTL_RESC_EXT 0x00000001 // External reset\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_RCC register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_RCC_ACG 0x08000000 // Automatic clock gating\r
+#define SYSCTL_RCC_SYSDIV_MASK 0x07800000 // System clock divider\r
+#define SYSCTL_RCC_SYSDIV_2 0x00800000 // System clock /2\r
+#define SYSCTL_RCC_SYSDIV_3 0x01000000 // System clock /3\r
+#define SYSCTL_RCC_SYSDIV_4 0x01800000 // System clock /4\r
+#define SYSCTL_RCC_SYSDIV_5 0x02000000 // System clock /5\r
+#define SYSCTL_RCC_SYSDIV_6 0x02800000 // System clock /6\r
+#define SYSCTL_RCC_SYSDIV_7 0x03000000 // System clock /7\r
+#define SYSCTL_RCC_SYSDIV_8 0x03800000 // System clock /8\r
+#define SYSCTL_RCC_SYSDIV_9 0x04000000 // System clock /9\r
+#define SYSCTL_RCC_SYSDIV_10 0x04800000 // System clock /10\r
+#define SYSCTL_RCC_SYSDIV_11 0x05000000 // System clock /11\r
+#define SYSCTL_RCC_SYSDIV_12 0x05800000 // System clock /12\r
+#define SYSCTL_RCC_SYSDIV_13 0x06000000 // System clock /13\r
+#define SYSCTL_RCC_SYSDIV_14 0x06800000 // System clock /14\r
+#define SYSCTL_RCC_SYSDIV_15 0x07000000 // System clock /15\r
+#define SYSCTL_RCC_SYSDIV_16 0x07800000 // System clock /16\r
+#define SYSCTL_RCC_USE_SYSDIV 0x00400000 // Use sytem clock divider\r
+#define SYSCTL_RCC_USE_PWMDIV 0x00100000 // Use PWM clock divider\r
+#define SYSCTL_RCC_PWMDIV_MASK 0x000E0000 // PWM clock divider\r
+#define SYSCTL_RCC_PWMDIV_2 0x00000000 // PWM clock /2\r
+#define SYSCTL_RCC_PWMDIV_4 0x00020000 // PWM clock /4\r
+#define SYSCTL_RCC_PWMDIV_8 0x00040000 // PWM clock /8\r
+#define SYSCTL_RCC_PWMDIV_16 0x00060000 // PWM clock /16\r
+#define SYSCTL_RCC_PWMDIV_32 0x00080000 // PWM clock /32\r
+#define SYSCTL_RCC_PWMDIV_64 0x000A0000 // PWM clock /64\r
+#define SYSCTL_RCC_PWRDN 0x00002000 // PLL power down\r
+#define SYSCTL_RCC_OE 0x00001000 // PLL output enable\r
+#define SYSCTL_RCC_BYPASS 0x00000800 // PLL bypass\r
+#define SYSCTL_RCC_PLLVER 0x00000400 // PLL verification timer enable\r
+#define SYSCTL_RCC_XTAL_MASK 0x000003C0 // Crystal attached to main osc\r
+#define SYSCTL_RCC_XTAL_3_57MHZ 0x00000100 // Using a 3.579545MHz crystal\r
+#define SYSCTL_RCC_XTAL_3_68MHz 0x00000140 // Using a 3.6864MHz crystal\r
+#define SYSCTL_RCC_XTAL_4MHz 0x00000180 // Using a 4MHz crystal\r
+#define SYSCTL_RCC_XTAL_4_09MHZ 0x000001C0 // Using a 4.096MHz crystal\r
+#define SYSCTL_RCC_XTAL_4_91MHZ 0x00000200 // Using a 4.9152MHz crystal\r
+#define SYSCTL_RCC_XTAL_5MHZ 0x00000240 // Using a 5MHz crystal\r
+#define SYSCTL_RCC_XTAL_5_12MHZ 0x00000280 // Using a 5.12MHz crystal\r
+#define SYSCTL_RCC_XTAL_6MHZ 0x000002C0 // Using a 6MHz crystal\r
+#define SYSCTL_RCC_XTAL_6_14MHZ 0x00000300 // Using a 6.144MHz crystal\r
+#define SYSCTL_RCC_XTAL_7_37MHZ 0x00000340 // Using a 7.3728MHz crystal\r
+#define SYSCTL_RCC_XTAL_8MHZ 0x00000380 // Using a 8MHz crystal\r
+#define SYSCTL_RCC_XTAL_8_19MHZ 0x000003C0 // Using a 8.192MHz crystal\r
+#define SYSCTL_RCC_OSCSRC_MASK 0x00000030 // Oscillator input select\r
+#define SYSCTL_RCC_OSCSRC_MAIN 0x00000000 // Use the main oscillator\r
+#define SYSCTL_RCC_OSCSRC_INT 0x00000010 // Use the internal oscillator\r
+#define SYSCTL_RCC_OSCSRC_INT4 0x00000020 // Use the internal oscillator / 4\r
+#define SYSCTL_RCC_IOSCVER 0x00000008 // Int. osc. verification timer en\r
+#define SYSCTL_RCC_MOSCVER 0x00000004 // Main osc. verification timer en\r
+#define SYSCTL_RCC_IOSCDIS 0x00000002 // Internal oscillator disable\r
+#define SYSCTL_RCC_MOSCDIS 0x00000001 // Main oscillator disable\r
+#define SYSCTL_RCC_SYSDIV_SHIFT 23 // Shift to the SYSDIV field\r
+#define SYSCTL_RCC_PWMDIV_SHIFT 17 // Shift to the PWMDIV field\r
+#define SYSCTL_RCC_XTAL_SHIFT 6 // Shift to the XTAL field\r
+#define SYSCTL_RCC_OSCSRC_SHIFT 4 // Shift to the OSCSRC field\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_PLLCFG register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_PLLCFG_OD_MASK 0x0000C000 // Output divider\r
+#define SYSCTL_PLLCFG_OD_1 0x00000000 // Output divider is 1\r
+#define SYSCTL_PLLCFG_OD_2 0x00004000 // Output divider is 2\r
+#define SYSCTL_PLLCFG_OD_4 0x00008000 // Output divider is 4\r
+#define SYSCTL_PLLCFG_F_MASK 0x00003FE0 // PLL multiplier\r
+#define SYSCTL_PLLCFG_R_MASK 0x0000001F // Input predivider\r
+#define SYSCTL_PLLCFG_F_SHIFT 5\r
+#define SYSCTL_PLLCFG_R_SHIFT 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_RCC2 register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_RCC2_USERCC2 0x80000000 // Use RCC2\r
+#define SYSCTL_RCC2_SYSDIV2_MSK 0x1F800000 // System clock divider\r
+#define SYSCTL_RCC2_SYSDIV2_2 0x00800000 // System clock /2\r
+#define SYSCTL_RCC2_SYSDIV2_3 0x01000000 // System clock /3\r
+#define SYSCTL_RCC2_SYSDIV2_4 0x01800000 // System clock /4\r
+#define SYSCTL_RCC2_SYSDIV2_5 0x02000000 // System clock /5\r
+#define SYSCTL_RCC2_SYSDIV2_6 0x02800000 // System clock /6\r
+#define SYSCTL_RCC2_SYSDIV2_7 0x03000000 // System clock /7\r
+#define SYSCTL_RCC2_SYSDIV2_8 0x03800000 // System clock /8\r
+#define SYSCTL_RCC2_SYSDIV2_9 0x04000000 // System clock /9\r
+#define SYSCTL_RCC2_SYSDIV2_10 0x04800000 // System clock /10\r
+#define SYSCTL_RCC2_SYSDIV2_11 0x05000000 // System clock /11\r
+#define SYSCTL_RCC2_SYSDIV2_12 0x05800000 // System clock /12\r
+#define SYSCTL_RCC2_SYSDIV2_13 0x06000000 // System clock /13\r
+#define SYSCTL_RCC2_SYSDIV2_14 0x06800000 // System clock /14\r
+#define SYSCTL_RCC2_SYSDIV2_15 0x07000000 // System clock /15\r
+#define SYSCTL_RCC2_SYSDIV2_16 0x07800000 // System clock /16\r
+#define SYSCTL_RCC2_SYSDIV2_17 0x08000000 // System clock /17\r
+#define SYSCTL_RCC2_SYSDIV2_18 0x08800000 // System clock /18\r
+#define SYSCTL_RCC2_SYSDIV2_19 0x09000000 // System clock /19\r
+#define SYSCTL_RCC2_SYSDIV2_20 0x09800000 // System clock /20\r
+#define SYSCTL_RCC2_SYSDIV2_21 0x0A000000 // System clock /21\r
+#define SYSCTL_RCC2_SYSDIV2_22 0x0A800000 // System clock /22\r
+#define SYSCTL_RCC2_SYSDIV2_23 0x0B000000 // System clock /23\r
+#define SYSCTL_RCC2_SYSDIV2_24 0x0B800000 // System clock /24\r
+#define SYSCTL_RCC2_SYSDIV2_25 0x0C000000 // System clock /25\r
+#define SYSCTL_RCC2_SYSDIV2_26 0x0C800000 // System clock /26\r
+#define SYSCTL_RCC2_SYSDIV2_27 0x0D000000 // System clock /27\r
+#define SYSCTL_RCC2_SYSDIV2_28 0x0D800000 // System clock /28\r
+#define SYSCTL_RCC2_SYSDIV2_29 0x0E000000 // System clock /29\r
+#define SYSCTL_RCC2_SYSDIV2_30 0x0E800000 // System clock /30\r
+#define SYSCTL_RCC2_SYSDIV2_31 0x0F000000 // System clock /31\r
+#define SYSCTL_RCC2_SYSDIV2_32 0x0F800000 // System clock /32\r
+#define SYSCTL_RCC2_SYSDIV2_33 0x10000000 // System clock /33\r
+#define SYSCTL_RCC2_SYSDIV2_34 0x10800000 // System clock /34\r
+#define SYSCTL_RCC2_SYSDIV2_35 0x11000000 // System clock /35\r
+#define SYSCTL_RCC2_SYSDIV2_36 0x11800000 // System clock /36\r
+#define SYSCTL_RCC2_SYSDIV2_37 0x12000000 // System clock /37\r
+#define SYSCTL_RCC2_SYSDIV2_38 0x12800000 // System clock /38\r
+#define SYSCTL_RCC2_SYSDIV2_39 0x13000000 // System clock /39\r
+#define SYSCTL_RCC2_SYSDIV2_40 0x13800000 // System clock /40\r
+#define SYSCTL_RCC2_SYSDIV2_41 0x14000000 // System clock /41\r
+#define SYSCTL_RCC2_SYSDIV2_42 0x14800000 // System clock /42\r
+#define SYSCTL_RCC2_SYSDIV2_43 0x15000000 // System clock /43\r
+#define SYSCTL_RCC2_SYSDIV2_44 0x15800000 // System clock /44\r
+#define SYSCTL_RCC2_SYSDIV2_45 0x16000000 // System clock /45\r
+#define SYSCTL_RCC2_SYSDIV2_46 0x16800000 // System clock /46\r
+#define SYSCTL_RCC2_SYSDIV2_47 0x17000000 // System clock /47\r
+#define SYSCTL_RCC2_SYSDIV2_48 0x17800000 // System clock /48\r
+#define SYSCTL_RCC2_SYSDIV2_49 0x18000000 // System clock /49\r
+#define SYSCTL_RCC2_SYSDIV2_50 0x18800000 // System clock /50\r
+#define SYSCTL_RCC2_SYSDIV2_51 0x19000000 // System clock /51\r
+#define SYSCTL_RCC2_SYSDIV2_52 0x19800000 // System clock /52\r
+#define SYSCTL_RCC2_SYSDIV2_53 0x1A000000 // System clock /53\r
+#define SYSCTL_RCC2_SYSDIV2_54 0x1A800000 // System clock /54\r
+#define SYSCTL_RCC2_SYSDIV2_55 0x1B000000 // System clock /55\r
+#define SYSCTL_RCC2_SYSDIV2_56 0x1B800000 // System clock /56\r
+#define SYSCTL_RCC2_SYSDIV2_57 0x1C000000 // System clock /57\r
+#define SYSCTL_RCC2_SYSDIV2_58 0x1C800000 // System clock /58\r
+#define SYSCTL_RCC2_SYSDIV2_59 0x1D000000 // System clock /59\r
+#define SYSCTL_RCC2_SYSDIV2_60 0x1D800000 // System clock /60\r
+#define SYSCTL_RCC2_SYSDIV2_61 0x1E000000 // System clock /61\r
+#define SYSCTL_RCC2_SYSDIV2_62 0x1E800000 // System clock /62\r
+#define SYSCTL_RCC2_SYSDIV2_63 0x1F000000 // System clock /63\r
+#define SYSCTL_RCC2_SYSDIV2_64 0x1F800000 // System clock /64\r
+#define SYSCTL_RCC2_PWRDN2 0x00002000 // PLL power down\r
+#define SYSCTL_RCC2_BYPASS2 0x00000800 // PLL bypass\r
+#define SYSCTL_RCC2_OSCSRC2_MSK 0x00000070 // Oscillator input select\r
+#define SYSCTL_RCC2_OSCSRC2_MO 0x00000000 // Use the main oscillator\r
+#define SYSCTL_RCC2_OSCSRC2_IO 0x00000010 // Use the internal oscillator\r
+#define SYSCTL_RCC2_OSCSRC2_IO4 0x00000020 // Use the internal oscillator / 4\r
+#define SYSCTL_RCC2_OSCSRC2_30 0x00000030 // Use the 30 KHz internal osc.\r
+#define SYSCTL_RCC2_OSCSRC2_32 0x00000070 // Use the 32 KHz external osc.\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_DSLPCLKCFG register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_DSLPCLKCFG_D_MSK 0x1f800000 // Deep sleep system clock override\r
+#define SYSCTL_DSLPCLKCFG_D_2 0x00800000 // System clock /2\r
+#define SYSCTL_DSLPCLKCFG_D_3 0x01000000 // System clock /3\r
+#define SYSCTL_DSLPCLKCFG_D_4 0x01800000 // System clock /4\r
+#define SYSCTL_DSLPCLKCFG_D_5 0x02000000 // System clock /5\r
+#define SYSCTL_DSLPCLKCFG_D_6 0x02800000 // System clock /6\r
+#define SYSCTL_DSLPCLKCFG_D_7 0x03000000 // System clock /7\r
+#define SYSCTL_DSLPCLKCFG_D_8 0x03800000 // System clock /8\r
+#define SYSCTL_DSLPCLKCFG_D_9 0x04000000 // System clock /9\r
+#define SYSCTL_DSLPCLKCFG_D_10 0x04800000 // System clock /10\r
+#define SYSCTL_DSLPCLKCFG_D_11 0x05000000 // System clock /11\r
+#define SYSCTL_DSLPCLKCFG_D_12 0x05800000 // System clock /12\r
+#define SYSCTL_DSLPCLKCFG_D_13 0x06000000 // System clock /13\r
+#define SYSCTL_DSLPCLKCFG_D_14 0x06800000 // System clock /14\r
+#define SYSCTL_DSLPCLKCFG_D_15 0x07000000 // System clock /15\r
+#define SYSCTL_DSLPCLKCFG_D_16 0x07800000 // System clock /16\r
+#define SYSCTL_DSLPCLKCFG_D_17 0x08000000 // System clock /17\r
+#define SYSCTL_DSLPCLKCFG_D_18 0x08800000 // System clock /18\r
+#define SYSCTL_DSLPCLKCFG_D_19 0x09000000 // System clock /19\r
+#define SYSCTL_DSLPCLKCFG_D_20 0x09800000 // System clock /20\r
+#define SYSCTL_DSLPCLKCFG_D_21 0x0A000000 // System clock /21\r
+#define SYSCTL_DSLPCLKCFG_D_22 0x0A800000 // System clock /22\r
+#define SYSCTL_DSLPCLKCFG_D_23 0x0B000000 // System clock /23\r
+#define SYSCTL_DSLPCLKCFG_D_24 0x0B800000 // System clock /24\r
+#define SYSCTL_DSLPCLKCFG_D_25 0x0C000000 // System clock /25\r
+#define SYSCTL_DSLPCLKCFG_D_26 0x0C800000 // System clock /26\r
+#define SYSCTL_DSLPCLKCFG_D_27 0x0D000000 // System clock /27\r
+#define SYSCTL_DSLPCLKCFG_D_28 0x0D800000 // System clock /28\r
+#define SYSCTL_DSLPCLKCFG_D_29 0x0E000000 // System clock /29\r
+#define SYSCTL_DSLPCLKCFG_D_30 0x0E800000 // System clock /30\r
+#define SYSCTL_DSLPCLKCFG_D_31 0x0F000000 // System clock /31\r
+#define SYSCTL_DSLPCLKCFG_D_32 0x0F800000 // System clock /32\r
+#define SYSCTL_DSLPCLKCFG_D_33 0x10000000 // System clock /33\r
+#define SYSCTL_DSLPCLKCFG_D_34 0x10800000 // System clock /34\r
+#define SYSCTL_DSLPCLKCFG_D_35 0x11000000 // System clock /35\r
+#define SYSCTL_DSLPCLKCFG_D_36 0x11800000 // System clock /36\r
+#define SYSCTL_DSLPCLKCFG_D_37 0x12000000 // System clock /37\r
+#define SYSCTL_DSLPCLKCFG_D_38 0x12800000 // System clock /38\r
+#define SYSCTL_DSLPCLKCFG_D_39 0x13000000 // System clock /39\r
+#define SYSCTL_DSLPCLKCFG_D_40 0x13800000 // System clock /40\r
+#define SYSCTL_DSLPCLKCFG_D_41 0x14000000 // System clock /41\r
+#define SYSCTL_DSLPCLKCFG_D_42 0x14800000 // System clock /42\r
+#define SYSCTL_DSLPCLKCFG_D_43 0x15000000 // System clock /43\r
+#define SYSCTL_DSLPCLKCFG_D_44 0x15800000 // System clock /44\r
+#define SYSCTL_DSLPCLKCFG_D_45 0x16000000 // System clock /45\r
+#define SYSCTL_DSLPCLKCFG_D_46 0x16800000 // System clock /46\r
+#define SYSCTL_DSLPCLKCFG_D_47 0x17000000 // System clock /47\r
+#define SYSCTL_DSLPCLKCFG_D_48 0x17800000 // System clock /48\r
+#define SYSCTL_DSLPCLKCFG_D_49 0x18000000 // System clock /49\r
+#define SYSCTL_DSLPCLKCFG_D_50 0x18800000 // System clock /50\r
+#define SYSCTL_DSLPCLKCFG_D_51 0x19000000 // System clock /51\r
+#define SYSCTL_DSLPCLKCFG_D_52 0x19800000 // System clock /52\r
+#define SYSCTL_DSLPCLKCFG_D_53 0x1A000000 // System clock /53\r
+#define SYSCTL_DSLPCLKCFG_D_54 0x1A800000 // System clock /54\r
+#define SYSCTL_DSLPCLKCFG_D_55 0x1B000000 // System clock /55\r
+#define SYSCTL_DSLPCLKCFG_D_56 0x1B800000 // System clock /56\r
+#define SYSCTL_DSLPCLKCFG_D_57 0x1C000000 // System clock /57\r
+#define SYSCTL_DSLPCLKCFG_D_58 0x1C800000 // System clock /58\r
+#define SYSCTL_DSLPCLKCFG_D_59 0x1D000000 // System clock /59\r
+#define SYSCTL_DSLPCLKCFG_D_60 0x1D800000 // System clock /60\r
+#define SYSCTL_DSLPCLKCFG_D_61 0x1E000000 // System clock /61\r
+#define SYSCTL_DSLPCLKCFG_D_62 0x1E800000 // System clock /62\r
+#define SYSCTL_DSLPCLKCFG_D_63 0x1F000000 // System clock /63\r
+#define SYSCTL_DSLPCLKCFG_D_64 0x1F800000 // System clock /64\r
+#define SYSCTL_DSLPCLKCFG_O_MSK 0x00000070 // Deep sleep oscillator override\r
+#define SYSCTL_DSLPCLKCFG_O_IGN 0x00000000 // Do not override\r
+#define SYSCTL_DSLPCLKCFG_O_IO 0x00000010 // Use the internal oscillator\r
+#define SYSCTL_DSLPCLKCFG_O_30 0x00000030 // Use the 30 KHz internal osc.\r
+#define SYSCTL_DSLPCLKCFG_O_32 0x00000070 // Use the 32 KHz external osc.\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_CLKVCLR register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_CLKVCLR_CLR 0x00000001 // Clear clock verification fault\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_LDOARST register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_LDOARST_ARST 0x00000001 // Allow LDO to reset device\r
+\r
+#endif // __HW_SYSCTL_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_timer.h - Defines and macros used when accessing the timer.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_TIMER_H__\r
+#define __HW_TIMER_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the offsets of the timer registers.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_O_CFG 0x00000000 // Configuration register\r
+#define TIMER_O_TAMR 0x00000004 // TimerA mode register\r
+#define TIMER_O_TBMR 0x00000008 // TimerB mode register\r
+#define TIMER_O_CTL 0x0000000C // Control register\r
+#define TIMER_O_IMR 0x00000018 // Interrupt mask register\r
+#define TIMER_O_RIS 0x0000001C // Interrupt status register\r
+#define TIMER_O_MIS 0x00000020 // Masked interrupt status reg.\r
+#define TIMER_O_ICR 0x00000024 // Interrupt clear register\r
+#define TIMER_O_TAILR 0x00000028 // TimerA interval load register\r
+#define TIMER_O_TBILR 0x0000002C // TimerB interval load register\r
+#define TIMER_O_TAMATCHR 0x00000030 // TimerA match register\r
+#define TIMER_O_TBMATCHR 0x00000034 // TimerB match register\r
+#define TIMER_O_TAPR 0x00000038 // TimerA prescale register\r
+#define TIMER_O_TBPR 0x0000003C // TimerB prescale register\r
+#define TIMER_O_TAPMR 0x00000040 // TimerA prescale match register\r
+#define TIMER_O_TBPMR 0x00000044 // TimerB prescale match register\r
+#define TIMER_O_TAR 0x00000048 // TimerA register\r
+#define TIMER_O_TBR 0x0000004C // TimerB register\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the reset values of the timer registers.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_RV_CFG 0x00000000 // Configuration register RV\r
+#define TIMER_RV_TAMR 0x00000000 // TimerA mode register RV\r
+#define TIMER_RV_TBMR 0x00000000 // TimerB mode register RV\r
+#define TIMER_RV_CTL 0x00000000 // Control register RV\r
+#define TIMER_RV_IMR 0x00000000 // Interrupt mask register RV\r
+#define TIMER_RV_RIS 0x00000000 // Interrupt status register RV\r
+#define TIMER_RV_MIS 0x00000000 // Masked interrupt status reg RV\r
+#define TIMER_RV_ICR 0x00000000 // Interrupt clear register RV\r
+#define TIMER_RV_TAILR 0xFFFFFFFF // TimerA interval load reg RV\r
+#define TIMER_RV_TBILR 0x0000FFFF // TimerB interval load reg RV\r
+#define TIMER_RV_TAMATCHR 0xFFFFFFFF // TimerA match register RV\r
+#define TIMER_RV_TBMATCHR 0x0000FFFF // TimerB match register RV\r
+#define TIMER_RV_TAPR 0x00000000 // TimerA prescale register RV\r
+#define TIMER_RV_TBPR 0x00000000 // TimerB prescale register RV\r
+#define TIMER_RV_TAPMR 0x00000000 // TimerA prescale match reg RV\r
+#define TIMER_RV_TBPMR 0x00000000 // TimerB prescale match regi RV\r
+#define TIMER_RV_TAR 0xFFFFFFFF // TimerA register RV\r
+#define TIMER_RV_TBR 0x0000FFFF // TimerB register RV\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the TIMER_CFG register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_CFG_CFG_MSK 0x00000007 // Configuration options mask\r
+#define TIMER_CFG_16_BIT 0x00000004 // Two 16 bit timers\r
+#define TIMER_CFG_32_BIT_RTC 0x00000001 // 32 bit RTC\r
+#define TIMER_CFG_32_BIT_TIMER 0x00000000 // 32 bit timer\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the TIMER_TnMR register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_TNMR_TNAMS 0x00000008 // Alternate mode select\r
+#define TIMER_TNMR_TNCMR 0x00000004 // Capture mode - count or time\r
+#define TIMER_TNMR_TNTMR_MSK 0x00000003 // Timer mode mask\r
+#define TIMER_TNMR_TNTMR_CAP 0x00000003 // Mode - capture\r
+#define TIMER_TNMR_TNTMR_PERIOD 0x00000002 // Mode - periodic\r
+#define TIMER_TNMR_TNTMR_1_SHOT 0x00000001 // Mode - one shot\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the TIMER_CTL register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_CTL_TBPWML 0x00004000 // TimerB PWM output level invert\r
+#define TIMER_CTL_TBOTE 0x00002000 // TimerB output trigger enable\r
+#define TIMER_CTL_TBEVENT_MSK 0x00000C00 // TimerB event mode mask\r
+#define TIMER_CTL_TBEVENT_BOTH 0x00000C00 // TimerB event mode - both edges\r
+#define TIMER_CTL_TBEVENT_NEG 0x00000400 // TimerB event mode - neg edge\r
+#define TIMER_CTL_TBEVENT_POS 0x00000000 // TimerB event mode - pos edge\r
+#define TIMER_CTL_TBSTALL 0x00000200 // TimerB stall enable\r
+#define TIMER_CTL_TBEN 0x00000100 // TimerB enable\r
+#define TIMER_CTL_TAPWML 0x00000040 // TimerA PWM output level invert\r
+#define TIMER_CTL_TAOTE 0x00000020 // TimerA output trigger enable\r
+#define TIMER_CTL_RTCEN 0x00000010 // RTC counter enable\r
+#define TIMER_CTL_TAEVENT_MSK 0x0000000C // TimerA event mode mask\r
+#define TIMER_CTL_TAEVENT_BOTH 0x0000000C // TimerA event mode - both edges\r
+#define TIMER_CTL_TAEVENT_NEG 0x00000004 // TimerA event mode - neg edge\r
+#define TIMER_CTL_TAEVENT_POS 0x00000000 // TimerA event mode - pos edge\r
+#define TIMER_CTL_TASTALL 0x00000002 // TimerA stall enable\r
+#define TIMER_CTL_TAEN 0x00000001 // TimerA enable\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the TIMER_IMR register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_IMR_CBEIM 0x00000400 // CaptureB event interrupt mask\r
+#define TIMER_IMR_CBMIM 0x00000200 // CaptureB match interrupt mask\r
+#define TIMER_IMR_TBTOIM 0x00000100 // TimerB time out interrupt mask\r
+#define TIMER_IMR_RTCIM 0x00000008 // RTC interrupt mask\r
+#define TIMER_IMR_CAEIM 0x00000004 // CaptureA event interrupt mask\r
+#define TIMER_IMR_CAMIM 0x00000002 // CaptureA match interrupt mask\r
+#define TIMER_IMR_TATOIM 0x00000001 // TimerA time out interrupt mask\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the TIMER_RIS register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_RIS_CBERIS 0x00000400 // CaptureB event raw int status\r
+#define TIMER_RIS_CBMRIS 0x00000200 // CaptureB match raw int status\r
+#define TIMER_RIS_TBTORIS 0x00000100 // TimerB time out raw int status\r
+#define TIMER_RIS_RTCRIS 0x00000008 // RTC raw int status\r
+#define TIMER_RIS_CAERIS 0x00000004 // CaptureA event raw int status\r
+#define TIMER_RIS_CAMRIS 0x00000002 // CaptureA match raw int status\r
+#define TIMER_RIS_TATORIS 0x00000001 // TimerA time out raw int status\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the TIMER_MIS register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_RIS_CBEMIS 0x00000400 // CaptureB event masked int status\r
+#define TIMER_RIS_CBMMIS 0x00000200 // CaptureB match masked int status\r
+#define TIMER_RIS_TBTOMIS 0x00000100 // TimerB time out masked int stat\r
+#define TIMER_RIS_RTCMIS 0x00000008 // RTC masked int status\r
+#define TIMER_RIS_CAEMIS 0x00000004 // CaptureA event masked int status\r
+#define TIMER_RIS_CAMMIS 0x00000002 // CaptureA match masked int status\r
+#define TIMER_RIS_TATOMIS 0x00000001 // TimerA time out masked int stat\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the TIMER_ICR register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_ICR_CBECINT 0x00000400 // CaptureB event interrupt clear\r
+#define TIMER_ICR_CBMCINT 0x00000200 // CaptureB match interrupt clear\r
+#define TIMER_ICR_TBTOCINT 0x00000100 // TimerB time out interrupt clear\r
+#define TIMER_ICR_RTCCINT 0x00000008 // RTC interrupt clear\r
+#define TIMER_ICR_CAECINT 0x00000004 // CaptureA event interrupt clear\r
+#define TIMER_ICR_CAMCINT 0x00000002 // CaptureA match interrupt clear\r
+#define TIMER_ICR_TATOCINT 0x00000001 // TimerA time out interrupt clear\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the TIMER_TAILR register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_TAILR_TAILRH 0xFFFF0000 // TimerB load val in 32 bit mode\r
+#define TIMER_TAILR_TAILRL 0x0000FFFF // TimerA interval load value\r
+\r
+//*****************************************************************************\r
+//\r
+// The following defines the bit fields in the TIMER_TBILR register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_TBILR_TBILRL 0x0000FFFF // TimerB interval load value\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the TIMER_TAMATCHR register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_TAMATCHR_TAMRH 0xFFFF0000 // TimerB match val in 32 bit mode\r
+#define TIMER_TAMATCHR_TAMRL 0x0000FFFF // TimerA match value\r
+\r
+//*****************************************************************************\r
+//\r
+// The following defines the bit fields in the TIMER_TBMATCHR register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_TBMATCHR_TBMRL 0x0000FFFF // TimerB match load value\r
+\r
+//*****************************************************************************\r
+//\r
+// The following defines the bit fields in the TIMER_TnPR register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_TNPR_TNPSR 0x000000FF // TimerN prescale value\r
+\r
+//*****************************************************************************\r
+//\r
+// The following defines the bit fields in the TIMER_TnPMR register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_TNPMR_TNPSMR 0x000000FF // TimerN prescale match value\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the TIMER_TAR register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_TAR_TARH 0xFFFF0000 // TimerB val in 32 bit mode\r
+#define TIMER_TAR_TARL 0x0000FFFF // TimerA value\r
+\r
+//*****************************************************************************\r
+//\r
+// The following defines the bit fields in the TIMER_TBR register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_TBR_TBRL 0x0000FFFF // TimerB value\r
+\r
+#endif // __HW_TIMER_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_types.h - Common types and macros.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_TYPES_H__\r
+#define __HW_TYPES_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// Define a boolean type, and values for true and false.\r
+//\r
+//*****************************************************************************\r
+typedef unsigned char tBoolean;\r
+\r
+#ifndef true\r
+#define true 1\r
+#endif\r
+\r
+#ifndef false\r
+#define false 0\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Macros for hardware access, both direct and via the bit-band region.\r
+//\r
+//*****************************************************************************\r
+#define HWREG(x) \\r
+ (*((volatile unsigned long *)(x)))\r
+#define HWREGH(x) \\r
+ (*((volatile unsigned short *)(x)))\r
+#define HWREGB(x) \\r
+ (*((volatile unsigned char *)(x)))\r
+#define HWREGBITW(x, b) \\r
+ HWREG(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \\r
+ (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2))\r
+#define HWREGBITH(x, b) \\r
+ HWREGH(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \\r
+ (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2))\r
+#define HWREGBITB(x, b) \\r
+ HWREGB(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \\r
+ (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2))\r
+\r
+//*****************************************************************************\r
+//\r
+// Helper Macros for determining silicon revisions, etc.\r
+//\r
+// These macros will be used by Driverlib at "run-time" to create necessary\r
+// conditional code blocks that will allow a single version of the Driverlib\r
+// "binary" code to support multiple(all) Stellaris silicon revisions.\r
+//\r
+// It is expected that these macros will be used inside of a standard 'C' \r
+// conditional block of code, e.g.\r
+//\r
+// if(DEVICE_IS_SANDSTORM())\r
+// {\r
+// do some Sandstorm specific code here.\r
+// }\r
+//\r
+// By default, these macros will be defined as run-time checks of the\r
+// appropriate register(s) to allow creation of run-time conditional code\r
+// blocks for a common DriverLib across the entire Stellaris family.\r
+//\r
+// However, if code-space optimization is required, these macros can be "hard-\r
+// coded" for a specific version of Stellaris silicon. Many compilers will\r
+// then detect the "hard-coded" conditionals, and appropriately optimize the\r
+// code blocks, eliminating any "unreachable" code. This would result in \r
+// a smaller Driverlib, thus producing a smaller final application size, but\r
+// at the cost of limiting the Driverlib binary to a specific Stellaris\r
+// silicon revision.\r
+//\r
+//*****************************************************************************\r
+#ifndef DEVICE_IS_SANDSTORM\r
+#define DEVICE_IS_SANDSTORM \\r
+ (((HWREG(SYSCTL_DID0) & SYSCTL_DID0_VER_MASK) == SYSCTL_DID0_VER_0) || \\r
+ (((HWREG(SYSCTL_DID0) & SYSCTL_DID0_VER_MASK) == SYSCTL_DID0_VER_1) && \\r
+ ((HWREG(SYSCTL_DID0) & SYSCTL_DID0_CLASS_MASK) == \\r
+ SYSCTL_DID0_CLASS_SANDSTORM)))\r
+#endif\r
+\r
+#ifndef DEVICE_IS_FURY\r
+#define DEVICE_IS_FURY \\r
+ (((HWREG(SYSCTL_DID0) & SYSCTL_DID0_VER_MASK) == SYSCTL_DID0_VER_1) && \\r
+ ((HWREG(SYSCTL_DID0) & SYSCTL_DID0_CLASS_MASK) == \\r
+ SYSCTL_DID0_CLASS_FURY))\r
+#endif\r
+\r
+#ifndef DEVICE_IS_REVA2\r
+#define DEVICE_IS_REVA2 \\r
+ (((HWREG(SYSCTL_DID0) & SYSCTL_DID0_MAJ_MASK) == SYSCTL_DID0_MAJ_A) && \\r
+ ((HWREG(SYSCTL_DID0) & SYSCTL_DID0_MIN_MASK) == SYSCTL_DID0_MIN_2))\r
+#endif\r
+\r
+#ifndef DEVICE_IS_REVC1\r
+#define DEVICE_IS_REVC1 \\r
+ (((HWREG(SYSCTL_DID0) & SYSCTL_DID0_MAJ_MASK) == SYSCTL_DID0_MAJ_C) && \\r
+ ((HWREG(SYSCTL_DID0) & SYSCTL_DID0_MIN_MASK) == SYSCTL_DID0_MIN_1))\r
+#endif\r
+\r
+#ifndef DEVICE_IS_REVC2\r
+#define DEVICE_IS_REVC2 \\r
+ (((HWREG(SYSCTL_DID0) & SYSCTL_DID0_MAJ_MASK) == SYSCTL_DID0_MAJ_C) && \\r
+ ((HWREG(SYSCTL_DID0) & SYSCTL_DID0_MIN_MASK) == SYSCTL_DID0_MIN_2))\r
+#endif\r
+\r
+#endif // __HW_TYPES_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_uart.h - Macros and defines used when accessing the UART hardware\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_UART_H__\r
+#define __HW_UART_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// UART Register Offsets.\r
+//\r
+//*****************************************************************************\r
+#define UART_O_DR 0x00000000 // Data Register\r
+#define UART_O_RSR 0x00000004 // Receive Status Register (read)\r
+#define UART_O_ECR 0x00000004 // Error Clear Register (write)\r
+#define UART_O_FR 0x00000018 // Flag Register (read only)\r
+#define UART_O_IBRD 0x00000024 // Integer Baud Rate Divisor Reg\r
+#define UART_O_FBRD 0x00000028 // Fractional Baud Rate Divisor Reg\r
+#define UART_O_LCR_H 0x0000002C // Line Control Register, HIGH byte\r
+#define UART_O_CTL 0x00000030 // Control Register\r
+#define UART_O_IFLS 0x00000034 // Interrupt FIFO Level Select Reg\r
+#define UART_O_IM 0x00000038 // Interrupt Mask Set/Clear Reg\r
+#define UART_O_RIS 0x0000003C // Raw Interrupt Status Register\r
+#define UART_O_MIS 0x00000040 // Masked Interrupt Status Register\r
+#define UART_O_ICR 0x00000044 // Interrupt Clear Register\r
+#define UART_O_PeriphID4 0x00000FD0 //\r
+#define UART_O_PeriphID5 0x00000FD4 //\r
+#define UART_O_PeriphID6 0x00000FD8 //\r
+#define UART_O_PeriphID7 0x00000FDC //\r
+#define UART_O_PeriphID0 0x00000FE0 //\r
+#define UART_O_PeriphID1 0x00000FE4 //\r
+#define UART_O_PeriphID2 0x00000FE8 //\r
+#define UART_O_PeriphID3 0x00000FEC //\r
+#define UART_O_PCellID0 0x00000FF0 //\r
+#define UART_O_PCellID1 0x00000FF4 //\r
+#define UART_O_PCellID2 0x00000FF8 //\r
+#define UART_O_PCellID3 0x00000FFC //\r
+\r
+//*****************************************************************************\r
+//\r
+// Data Register bits\r
+//\r
+//*****************************************************************************\r
+#define UART_DR_OE 0x00000800 // Overrun Error\r
+#define UART_DR_BE 0x00000400 // Break Error\r
+#define UART_DR_PE 0x00000200 // Parity Error\r
+#define UART_DR_FE 0x00000100 // Framing Error\r
+#define UART_DR_DATA_MASK 0x000000FF // UART data\r
+\r
+//*****************************************************************************\r
+//\r
+// Receive Status Register bits\r
+//\r
+//*****************************************************************************\r
+#define UART_RSR_OE 0x00000008 // Overrun Error\r
+#define UART_RSR_BE 0x00000004 // Break Error\r
+#define UART_RSR_PE 0x00000002 // Parity Error\r
+#define UART_RSR_FE 0x00000001 // Framing Error\r
+\r
+//*****************************************************************************\r
+//\r
+// Flag Register bits\r
+//\r
+//*****************************************************************************\r
+#define UART_FR_TXFE 0x00000080 // TX FIFO Empty\r
+#define UART_FR_RXFF 0x00000040 // RX FIFO Full\r
+#define UART_FR_TXFF 0x00000020 // TX FIFO Full\r
+#define UART_FR_RXFE 0x00000010 // RX FIFO Empty\r
+#define UART_FR_BUSY 0x00000008 // UART Busy\r
+\r
+//*****************************************************************************\r
+//\r
+// Integer baud-rate divisor\r
+//\r
+//*****************************************************************************\r
+#define UART_IBRD_DIVINT_MASK 0x0000FFFF // Integer baud-rate divisor\r
+\r
+//*****************************************************************************\r
+//\r
+// Fractional baud-rate divisor\r
+//\r
+//*****************************************************************************\r
+#define UART_FBRD_DIVFRAC_MASK 0x0000003F // Fractional baud-rate divisor\r
+\r
+//*****************************************************************************\r
+//\r
+// Line Control Register High bits\r
+//\r
+//*****************************************************************************\r
+#define UART_LCR_H_SPS 0x00000080 // Stick Parity Select\r
+#define UART_LCR_H_WLEN 0x00000060 // Word length\r
+#define UART_LCR_H_WLEN_8 0x00000060 // 8 bit data\r
+#define UART_LCR_H_WLEN_7 0x00000040 // 7 bit data\r
+#define UART_LCR_H_WLEN_6 0x00000020 // 6 bit data\r
+#define UART_LCR_H_WLEN_5 0x00000000 // 5 bit data\r
+#define UART_LCR_H_FEN 0x00000010 // Enable FIFO\r
+#define UART_LCR_H_STP2 0x00000008 // Two Stop Bits Select\r
+#define UART_LCR_H_EPS 0x00000004 // Even Parity Select\r
+#define UART_LCR_H_PEN 0x00000002 // Parity Enable\r
+#define UART_LCR_H_BRK 0x00000001 // Send Break\r
+\r
+//*****************************************************************************\r
+//\r
+// Control Register bits\r
+//\r
+//*****************************************************************************\r
+#define UART_CTL_RXE 0x00000200 // Receive Enable\r
+#define UART_CTL_TXE 0x00000100 // Transmit Enable\r
+#define UART_CTL_LBE 0x00000080 // Loopback Enable\r
+#define UART_CTL_SIRLP 0x00000004 // SIR (IrDA) Low Power Enable\r
+#define UART_CTL_SIREN 0x00000002 // SIR (IrDA) Enable\r
+#define UART_CTL_UARTEN 0x00000001 // UART Enable\r
+\r
+//*****************************************************************************\r
+//\r
+// Interrupt FIFO Level Select Register bits\r
+//\r
+//*****************************************************************************\r
+#define UART_IFLS_RX1_8 0x00000000 // 1/8 Full\r
+#define UART_IFLS_RX2_8 0x00000010 // 1/4 Full\r
+#define UART_IFLS_RX4_8 0x00000020 // 1/2 Full\r
+#define UART_IFLS_RX6_8 0x00000030 // 3/4 Full\r
+#define UART_IFLS_RX7_8 0x00000040 // 7/8 Full\r
+#define UART_IFLS_TX1_8 0x00000000 // 1/8 Full\r
+#define UART_IFLS_TX2_8 0x00000001 // 1/4 Full\r
+#define UART_IFLS_TX4_8 0x00000002 // 1/2 Full\r
+#define UART_IFLS_TX6_8 0x00000003 // 3/4 Full\r
+#define UART_IFLS_TX7_8 0x00000004 // 7/8 Full\r
+\r
+//*****************************************************************************\r
+//\r
+// Interrupt Mask Set/Clear Register bits\r
+//\r
+//*****************************************************************************\r
+#define UART_IM_OEIM 0x00000400 // Overrun Error Interrupt Mask\r
+#define UART_IM_BEIM 0x00000200 // Break Error Interrupt Mask\r
+#define UART_IM_PEIM 0x00000100 // Parity Error Interrupt Mask\r
+#define UART_IM_FEIM 0x00000080 // Framing Error Interrupt Mask\r
+#define UART_IM_RTIM 0x00000040 // Receive Timeout Interrupt Mask\r
+#define UART_IM_TXIM 0x00000020 // Transmit Interrupt Mask\r
+#define UART_IM_RXIM 0x00000010 // Receive Interrupt Mask\r
+\r
+//*****************************************************************************\r
+//\r
+// Raw Interrupt Status Register\r
+//\r
+//*****************************************************************************\r
+#define UART_RIS_OERIS 0x00000400 // Overrun Error Interrupt Status\r
+#define UART_RIS_BERIS 0x00000200 // Break Error Interrupt Status\r
+#define UART_RIS_PERIS 0x00000100 // Parity Error Interrupt Status\r
+#define UART_RIS_FERIS 0x00000080 // Framing Error Interrupt Status\r
+#define UART_RIS_RTRIS 0x00000040 // Receive Timeout Interrupt Status\r
+#define UART_RIS_TXRIS 0x00000020 // Transmit Interrupt Status\r
+#define UART_RIS_RXRIS 0x00000010 // Receive Interrupt Status\r
+\r
+//*****************************************************************************\r
+//\r
+// Masked Interrupt Status Register\r
+//\r
+//*****************************************************************************\r
+#define UART_MIS_OEMIS 0x00000400 // Overrun Error Interrupt Status\r
+#define UART_MIS_BEMIS 0x00000200 // Break Error Interrupt Status\r
+#define UART_MIS_PEMIS 0x00000100 // Parity Error Interrupt Status\r
+#define UART_MIS_FEMIS 0x00000080 // Framing Error Interrupt Status\r
+#define UART_MIS_RTMIS 0x00000040 // Receive Timeout Interrupt Status\r
+#define UART_MIS_TXMIS 0x00000020 // Transmit Interrupt Status\r
+#define UART_MIS_RXMIS 0x00000010 // Receive Interrupt Status\r
+\r
+//*****************************************************************************\r
+//\r
+// Interrupt Clear Register bits\r
+//\r
+//*****************************************************************************\r
+#define UART_ICR_OEIC 0x00000400 // Overrun Error Interrupt Clear\r
+#define UART_ICR_BEIC 0x00000200 // Break Error Interrupt Clear\r
+#define UART_ICR_PEIC 0x00000100 // Parity Error Interrupt Clear\r
+#define UART_ICR_FEIC 0x00000080 // Framing Error Interrupt Clear\r
+#define UART_ICR_RTIC 0x00000040 // Receive Timeout Interrupt Clear\r
+#define UART_ICR_TXIC 0x00000020 // Transmit Interrupt Clear\r
+#define UART_ICR_RXIC 0x00000010 // Receive Interrupt Clear\r
+\r
+#define UART_RSR_ANY (UART_RSR_OE | \\r
+ UART_RSR_BE | \\r
+ UART_RSR_PE | \\r
+ UART_RSR_FE)\r
+\r
+//*****************************************************************************\r
+//\r
+// Reset Values for UART Registers.\r
+//\r
+//*****************************************************************************\r
+#define UART_RV_DR 0x00000000\r
+#define UART_RV_RSR 0x00000000\r
+#define UART_RV_ECR 0x00000000\r
+#define UART_RV_FR 0x00000090\r
+#define UART_RV_IBRD 0x00000000\r
+#define UART_RV_FBRD 0x00000000\r
+#define UART_RV_LCR_H 0x00000000\r
+#define UART_RV_CTL 0x00000300\r
+#define UART_RV_IFLS 0x00000012\r
+#define UART_RV_IM 0x00000000\r
+#define UART_RV_RIS 0x00000000\r
+#define UART_RV_MIS 0x00000000\r
+#define UART_RV_ICR 0x00000000\r
+#define UART_RV_PeriphID4 0x00000000\r
+#define UART_RV_PeriphID5 0x00000000\r
+#define UART_RV_PeriphID6 0x00000000\r
+#define UART_RV_PeriphID7 0x00000000\r
+#define UART_RV_PeriphID0 0x00000011\r
+#define UART_RV_PeriphID1 0x00000000\r
+#define UART_RV_PeriphID2 0x00000018\r
+#define UART_RV_PeriphID3 0x00000001\r
+#define UART_RV_PCellID0 0x0000000D\r
+#define UART_RV_PCellID1 0x000000F0\r
+#define UART_RV_PCellID2 0x00000005\r
+#define UART_RV_PCellID3 0x000000B1\r
+\r
+#endif // __HW_UART_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_watchdog.h - Macros used when accessing the Watchdog Timer hardware.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_WATCHDOG_H__\r
+#define __HW_WATCHDOG_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the offsets of the Watchdog Timer registers.\r
+//\r
+//*****************************************************************************\r
+#define WDT_O_LOAD 0x00000000 // Load register\r
+#define WDT_O_VALUE 0x00000004 // Current value register\r
+#define WDT_O_CTL 0x00000008 // Control register\r
+#define WDT_O_ICR 0x0000000C // Interrupt clear register\r
+#define WDT_O_RIS 0x00000010 // Raw interrupt status register\r
+#define WDT_O_MIS 0x00000014 // Masked interrupt status register\r
+#define WDT_O_TEST 0x00000418 // Test register\r
+#define WDT_O_LOCK 0x00000C00 // Lock register\r
+#define WDT_O_PeriphID4 0x00000FD0 //\r
+#define WDT_O_PeriphID5 0x00000FD4 //\r
+#define WDT_O_PeriphID6 0x00000FD8 //\r
+#define WDT_O_PeriphID7 0x00000FDC //\r
+#define WDT_O_PeriphID0 0x00000FE0 //\r
+#define WDT_O_PeriphID1 0x00000FE4 //\r
+#define WDT_O_PeriphID2 0x00000FE8 //\r
+#define WDT_O_PeriphID3 0x00000FEC //\r
+#define WDT_O_PCellID0 0x00000FF0 //\r
+#define WDT_O_PCellID1 0x00000FF4 //\r
+#define WDT_O_PCellID2 0x00000FF8 //\r
+#define WDT_O_PCellID3 0x00000FFC //\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the WDT_CTL register.\r
+//\r
+//*****************************************************************************\r
+#define WDT_CTL_RESEN 0x00000002 // Enable reset output\r
+#define WDT_CTL_INTEN 0x00000001 // Enable the WDT counter and int\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the WDT_ISR, WDT_RIS, and WDT_MIS\r
+// registers.\r
+//\r
+//*****************************************************************************\r
+#define WDT_INT_TIMEOUT 0x00000001 // Watchdog timer expired\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the WDT_TEST register.\r
+//\r
+//*****************************************************************************\r
+#define WDT_TEST_STALL 0x00000100 // Watchdog stall enable\r
+#ifndef DEPRECATED\r
+#define WDT_TEST_STALL_EN 0x00000100 // Watchdog stall enable\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the WDT_LOCK register.\r
+//\r
+//*****************************************************************************\r
+#define WDT_LOCK_LOCKED 0x00000001 // Watchdog timer is locked\r
+#define WDT_LOCK_UNLOCKED 0x00000000 // Watchdog timer is unlocked\r
+#define WDT_LOCK_UNLOCK 0x1ACCE551 // Unlocks the watchdog timer\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the reset values for the WDT registers.\r
+//\r
+//*****************************************************************************\r
+#define WDT_RV_LOAD 0xFFFFFFFF // Load register\r
+#define WDT_RV_VALUE 0xFFFFFFFF // Current value register\r
+#define WDT_RV_CTL 0x00000000 // Control register\r
+#define WDT_RV_RIS 0x00000000 // Raw interrupt status register\r
+#define WDT_RV_MIS 0x00000000 // Masked interrupt status register\r
+#define WDT_RV_LOCK 0x00000000 // Lock register\r
+#define WDT_RV_PeriphID4 0x00000000 //\r
+#define WDT_RV_PeriphID5 0x00000000 //\r
+#define WDT_RV_PeriphID6 0x00000000 //\r
+#define WDT_RV_PeriphID7 0x00000000 //\r
+#define WDT_RV_PeriphID0 0x00000005 //\r
+#define WDT_RV_PeriphID1 0x00000018 //\r
+#define WDT_RV_PeriphID2 0x00000018 //\r
+#define WDT_RV_PeriphID3 0x00000001 //\r
+#define WDT_RV_PCellID0 0x0000000D //\r
+#define WDT_RV_PCellID1 0x000000F0 //\r
+#define WDT_RV_PCellID2 0x00000005 //\r
+#define WDT_RV_PCellID3 0x000000B1 //\r
+\r
+#endif // __HW_WATCHDOG_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// i2c.h - Prototypes for the I2C Driver.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __I2C_H__\r
+#define __I2C_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Defines for the API.\r
+//\r
+//*****************************************************************************\r
+//*****************************************************************************\r
+//\r
+// Interrupt defines.\r
+//\r
+//*****************************************************************************\r
+#define I2C_INT_MASTER 0x00000001\r
+#define I2C_INT_SLAVE 0x00000002\r
+\r
+//*****************************************************************************\r
+//\r
+// I2C Master commands.\r
+//\r
+//*****************************************************************************\r
+#define I2C_MASTER_CMD_SINGLE_SEND \\r
+ (I2C_MASTER_CS_STOP | I2C_MASTER_CS_START | I2C_MASTER_CS_RUN)\r
+#define I2C_MASTER_CMD_SINGLE_RECEIVE \\r
+ (I2C_MASTER_CS_STOP | I2C_MASTER_CS_START | I2C_MASTER_CS_RUN)\r
+#define I2C_MASTER_CMD_BURST_SEND_START \\r
+ (I2C_MASTER_CS_START | I2C_MASTER_CS_RUN)\r
+#define I2C_MASTER_CMD_BURST_SEND_CONT \\r
+ (I2C_MASTER_CS_RUN)\r
+#define I2C_MASTER_CMD_BURST_SEND_FINISH \\r
+ (I2C_MASTER_CS_STOP | I2C_MASTER_CS_RUN)\r
+#define I2C_MASTER_CMD_BURST_SEND_ERROR_STOP \\r
+ (I2C_MASTER_CS_STOP)\r
+#define I2C_MASTER_CMD_BURST_RECEIVE_START \\r
+ (I2C_MASTER_CS_ACK | I2C_MASTER_CS_START | I2C_MASTER_CS_RUN)\r
+#define I2C_MASTER_CMD_BURST_RECEIVE_CONT \\r
+ (I2C_MASTER_CS_ACK | I2C_MASTER_CS_RUN)\r
+#define I2C_MASTER_CMD_BURST_RECEIVE_FINISH \\r
+ (I2C_MASTER_CS_STOP | I2C_MASTER_CS_RUN)\r
+#define I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP \\r
+ (I2C_MASTER_CS_STOP | I2C_MASTER_CS_RUN)\r
+\r
+//*****************************************************************************\r
+//\r
+// I2C Master error status.\r
+//\r
+//*****************************************************************************\r
+#define I2C_MASTER_ERR_NONE 0\r
+#define I2C_MASTER_ERR_ADDR_ACK 0x00000004\r
+#define I2C_MASTER_ERR_DATA_ACK 0x00000008\r
+#define I2C_MASTER_ERR_ARB_LOST 0x00000010\r
+\r
+//*****************************************************************************\r
+//\r
+// I2C Slave action requests\r
+//\r
+//*****************************************************************************\r
+#define I2C_SLAVE_ACT_NONE 0\r
+#define I2C_SLAVE_ACT_RREQ 0x00000001 // Master has sent data\r
+#define I2C_SLAVE_ACT_TREQ 0x00000002 // Master has requested data\r
+\r
+//*****************************************************************************\r
+// Miscellaneous I2C driver definitions.\r
+//*****************************************************************************\r
+#define I2C_MASTER_MAX_RETRIES 1000 // Number of retries\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+extern void I2CIntRegister(unsigned long ulBase, void(fnHandler)(void));\r
+extern void I2CIntUnregister(unsigned long ulBase);\r
+extern tBoolean I2CMasterBusBusy(unsigned long ulBase);\r
+extern tBoolean I2CMasterBusy(unsigned long ulBase);\r
+extern void I2CMasterControl(unsigned long ulBase, unsigned long ulCmd);\r
+extern unsigned long I2CMasterDataGet(unsigned long ulBase);\r
+extern void I2CMasterDataPut(unsigned long ulBase, unsigned char ucData);\r
+extern void I2CMasterDisable(unsigned long ulBase);\r
+extern void I2CMasterEnable(unsigned long ulBase);\r
+extern unsigned long I2CMasterErr(unsigned long ulBase);\r
+extern void I2CMasterInit(unsigned long ulBase, tBoolean bFast);\r
+extern void I2CMasterIntClear(unsigned long ulBase);\r
+extern void I2CMasterIntDisable(unsigned long ulBase);\r
+extern void I2CMasterIntEnable(unsigned long ulBase);\r
+extern tBoolean I2CMasterIntStatus(unsigned long ulBase, tBoolean bMasked);\r
+extern void I2CMasterSlaveAddrSet(unsigned long ulBase,\r
+ unsigned char ucSlaveAddr,\r
+ tBoolean bReceive);\r
+extern unsigned long I2CSlaveDataGet(unsigned long ulBase);\r
+extern void I2CSlaveDataPut(unsigned long ulBase, unsigned char ucData);\r
+extern void I2CSlaveDisable(unsigned long ulBase);\r
+extern void I2CSlaveEnable(unsigned long ulBase);\r
+extern void I2CSlaveInit(unsigned long ulBase, unsigned char ucSlaveAddr);\r
+extern void I2CSlaveIntClear(unsigned long ulBase);\r
+extern void I2CSlaveIntDisable(unsigned long ulBase);\r
+extern void I2CSlaveIntEnable(unsigned long ulBase);\r
+extern tBoolean I2CSlaveIntStatus(unsigned long ulBase, tBoolean bMasked);\r
+extern unsigned long I2CSlaveStatus(unsigned long ulBase);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __I2C_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// interrupt.h - Prototypes for the NVIC Interrupt Controller Driver.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __INTERRUPT_H__\r
+#define __INTERRUPT_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+extern void IntMasterEnable(void);\r
+extern void IntMasterDisable(void);\r
+extern void IntRegister(unsigned long ulInterrupt, void (*pfnHandler)(void));\r
+extern void IntUnregister(unsigned long ulInterrupt);\r
+extern void IntPriorityGroupingSet(unsigned long ulBits);\r
+extern unsigned long IntPriorityGroupingGet(void);\r
+extern void IntPrioritySet(unsigned long ulInterrupt,\r
+ unsigned char ucPriority);\r
+extern long IntPriorityGet(unsigned long ulInterrupt);\r
+extern void IntEnable(unsigned long ulInterrupt);\r
+extern void IntDisable(unsigned long ulInterrupt);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __INTERRUPT_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// flash.h - Prototypes for the flash driver.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __FLASH_H__\r
+#define __FLASH_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to FlashProtectSet(), and returned by\r
+// FlashProtectGet().\r
+//\r
+//*****************************************************************************\r
+typedef enum\r
+{\r
+ FlashReadWrite, // Flash can be read and written\r
+ FlashReadOnly, // Flash can only be read\r
+ FlashExecuteOnly // Flash can only be executed\r
+}\r
+tFlashProtection;\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+extern unsigned long FlashUsecGet(void);\r
+extern void FlashUsecSet(unsigned long ulClocks);\r
+extern long FlashErase(unsigned long ulAddress);\r
+extern long FlashProgram(unsigned long *pulData, unsigned long ulAddress,\r
+ unsigned long ulCount);\r
+extern tFlashProtection FlashProtectGet(unsigned long ulAddress);\r
+extern long FlashProtectSet(unsigned long ulAddress,\r
+ tFlashProtection eProtect);\r
+extern long FlashProtectSave(void);\r
+extern long FlashUserGet(unsigned long *pulUser0, unsigned long *pulUser1);\r
+extern long FlashUserSet(unsigned long ulUser0, unsigned long ulUser1);\r
+extern long FlashUserSave(void);\r
+extern void FlashIntRegister(void (*pfnHandler)(void));\r
+extern void FlashIntUnregister(void);\r
+extern void FlashIntEnable(unsigned long ulIntFlags);\r
+extern void FlashIntDisable(unsigned long ulIntFlags);\r
+extern unsigned long FlashIntGetStatus(tBoolean bMasked);\r
+extern void FlashIntClear(unsigned long ulIntFlags);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __FLASH_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// timer.h - Prototypes for the timer module\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __TIMER_H__\r
+#define __TIMER_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to TimerConfigure as the ulConfig parameter.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_CFG_32_BIT_OS 0x00000001 // 32-bit one-shot timer\r
+#define TIMER_CFG_32_BIT_PER 0x00000002 // 32-bit periodic timer\r
+#define TIMER_CFG_32_RTC 0x01000000 // 32-bit RTC timer\r
+#define TIMER_CFG_16_BIT_PAIR 0x04000000 // Two 16-bit timers\r
+#define TIMER_CFG_A_ONE_SHOT 0x00000001 // Timer A one-shot timer\r
+#define TIMER_CFG_A_PERIODIC 0x00000002 // Timer A periodic timer\r
+#define TIMER_CFG_A_CAP_COUNT 0x00000003 // Timer A event counter\r
+#define TIMER_CFG_A_CAP_TIME 0x00000007 // Timer A event timer\r
+#define TIMER_CFG_A_PWM 0x0000000A // Timer A PWM output\r
+#define TIMER_CFG_B_ONE_SHOT 0x00000100 // Timer B one-shot timer\r
+#define TIMER_CFG_B_PERIODIC 0x00000200 // Timer B periodic timer\r
+#define TIMER_CFG_B_CAP_COUNT 0x00000300 // Timer B event counter\r
+#define TIMER_CFG_B_CAP_TIME 0x00000700 // Timer B event timer\r
+#define TIMER_CFG_B_PWM 0x00000A00 // Timer B PWM output\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to TimerIntEnable, TimerIntDisable, and\r
+// TimerIntClear as the ulIntFlags parameter, and returned from TimerIntStatus.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_CAPB_EVENT 0x00000400 // CaptureB event interrupt\r
+#define TIMER_CAPB_MATCH 0x00000200 // CaptureB match interrupt\r
+#define TIMER_TIMB_TIMEOUT 0x00000100 // TimerB time out interrupt\r
+#define TIMER_RTC_MATCH 0x00000008 // RTC interrupt mask\r
+#define TIMER_CAPA_EVENT 0x00000004 // CaptureA event interrupt\r
+#define TIMER_CAPA_MATCH 0x00000002 // CaptureA match interrupt\r
+#define TIMER_TIMA_TIMEOUT 0x00000001 // TimerA time out interrupt\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to TimerControlEvent as the ulEvent parameter.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_EVENT_POS_EDGE 0x00000000 // Count positive edges\r
+#define TIMER_EVENT_NEG_EDGE 0x00000404 // Count negative edges\r
+#define TIMER_EVENT_BOTH_EDGES 0x00000C0C // Count both edges\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to most of the timer APIs as the ulTimer\r
+// parameter.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_A 0x000000ff // Timer A\r
+#define TIMER_B 0x0000ff00 // Timer B\r
+#define TIMER_BOTH 0x0000ffff // Timer Both\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+extern void TimerEnable(unsigned long ulBase, unsigned long ulTimer);\r
+extern void TimerDisable(unsigned long ulBase, unsigned long ulTimer);\r
+extern void TimerConfigure(unsigned long ulBase, unsigned long ulConfig);\r
+extern void TimerControlLevel(unsigned long ulBase, unsigned long ulTimer,\r
+ tBoolean bInvert);\r
+extern void TimerControlTrigger(unsigned long ulBase, unsigned long ulTimer,\r
+ tBoolean bEnable);\r
+extern void TimerControlEvent(unsigned long ulBase, unsigned long ulTimer,\r
+ unsigned long ulEvent);\r
+extern void TimerControlStall(unsigned long ulBase, unsigned long ulTimer,\r
+ tBoolean bStall);\r
+extern void TimerRTCEnable(unsigned long ulBase);\r
+extern void TimerRTCDisable(unsigned long ulBase);\r
+extern void TimerPrescaleSet(unsigned long ulBase, unsigned long ulTimer,\r
+ unsigned long ulValue);\r
+extern unsigned long TimerPrescaleGet(unsigned long ulBase,\r
+ unsigned long ulTimer);\r
+extern void TimerPrescaleMatchSet(unsigned long ulBase, unsigned long ulTimer,\r
+ unsigned long ulValue);\r
+extern unsigned long TimerPrescaleMatchGet(unsigned long ulBase,\r
+ unsigned long ulTimer);\r
+extern void TimerLoadSet(unsigned long ulBase, unsigned long ulTimer,\r
+ unsigned long ulValue);\r
+extern unsigned long TimerLoadGet(unsigned long ulBase, unsigned long ulTimer);\r
+extern unsigned long TimerValueGet(unsigned long ulBase,\r
+ unsigned long ulTimer);\r
+extern void TimerMatchSet(unsigned long ulBase, unsigned long ulTimer,\r
+ unsigned long ulValue);\r
+extern unsigned long TimerMatchGet(unsigned long ulBase,\r
+ unsigned long ulTimer);\r
+extern void TimerIntRegister(unsigned long ulBase, unsigned long ulTimer,\r
+ void (*pfnHandler)(void));\r
+extern void TimerIntUnregister(unsigned long ulBase, unsigned long ulTimer);\r
+extern void TimerIntEnable(unsigned long ulBase, unsigned long ulIntFlags);\r
+extern void TimerIntDisable(unsigned long ulBase, unsigned long ulIntFlags);\r
+extern unsigned long TimerIntStatus(unsigned long ulBase, tBoolean bMasked);\r
+extern void TimerIntClear(unsigned long ulBase, unsigned long ulIntFlags);\r
+extern void TimerQuiesce(unsigned long ulBase);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __TIMER_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// osram128x64x4.c - Driver for the OSRAM 128x64x4 graphical OLED display.\r
+//\r
+// Copyright (c) 2006-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+//*****************************************************************************\r
+//\r
+//! \addtogroup ek_lm3sx965_api\r
+//! @{\r
+//\r
+//*****************************************************************************\r
+\r
+#include "hw_ssi.h"\r
+#include "hw_memmap.h"\r
+#include "hw_sysctl.h"\r
+#include "hw_types.h"\r
+#include "debug.h"\r
+#include "gpio.h"\r
+#include "ssi.h"\r
+#include "sysctl.h"\r
+#include "osram128x64x4.h"\r
+\r
+//*****************************************************************************\r
+//\r
+// Flag to indicate if SSI port is enabled for OSRAM usage.\r
+//\r
+//*****************************************************************************\r
+static volatile tBoolean g_bSSIEnabled = false;\r
+\r
+//*****************************************************************************\r
+//\r
+// Define the OSRAM 128x64x4 Remap Setting(s). This will be used in\r
+// several places in the code to switch between vertical and horizontal\r
+// address incrementing.\r
+//\r
+// The Remap Command (0xA0) takes one 8-bit parameter. The parameter is\r
+// defined as follows.\r
+//\r
+// Bit 7: Reserved\r
+// Bit 6: Disable(0)/Enable(1) COM Split Odd Even\r
+// When enabled, the COM signals are split Odd on one side, even on\r
+// the other. Otherwise, they are split 0-39 on one side, 40-79 on\r
+// the other.\r
+// Bit 5: Reserved\r
+// Bit 4: Disable(0)/Enable(1) COM Remap\r
+// When Enabled, ROW 0-79 map to COM 79-0 (i.e. reverse row order)\r
+// Bit 3: Reserved\r
+// Bit 2: Horizontal(0)/Vertical(1) Address Increment\r
+// When set, data RAM address will increment along the column rather\r
+// than along the row.\r
+// Bit 1: Disable(0)/Enable(1) Nibble Remap\r
+// When enabled, the upper and lower nibbles in the DATA bus for access\r
+// to the data RAM are swapped.\r
+// Bit 0: Disable(0)/Enable(1) Column Address Remap\r
+// When enabled, DATA RAM columns 0-63 are remapped to Segment Columns\r
+// 127-0.\r
+//\r
+//*****************************************************************************\r
+#define OSRAM_INIT_REMAP 0x52\r
+#define OSRAM_INIT_OFFSET 0x4C\r
+static const unsigned char g_pucOSRAM128x64x4VerticalInc[] = { 0xA0, 0x56 };\r
+static const unsigned char g_pucOSRAM128x64x4HorizontalInc[] = { 0xA0, 0x52 };\r
+\r
+//*****************************************************************************\r
+//\r
+// A 5x7 font (in a 6x8 cell, where the sixth column is omitted from this\r
+// table) for displaying text on the OLED display. The data is organized as\r
+// bytes from the left column to the right column, with each byte containing\r
+// the top row in the LSB and the bottom row in the MSB.\r
+//\r
+// Note: This is the same font data that is used in the EK-LM3S811\r
+// osram96x16x1 driver. The single bit-per-pixel is expaned in the StringDraw\r
+// function to the appropriate four bit-per-pixel gray scale format.\r
+//\r
+//*****************************************************************************\r
+static const unsigned char g_pucFont[96][5] =\r
+{\r
+ { 0x00, 0x00, 0x00, 0x00, 0x00 }, // " "\r
+ { 0x00, 0x00, 0x4f, 0x00, 0x00 }, // !\r
+ { 0x00, 0x07, 0x00, 0x07, 0x00 }, // "\r
+ { 0x14, 0x7f, 0x14, 0x7f, 0x14 }, // #\r
+ { 0x24, 0x2a, 0x7f, 0x2a, 0x12 }, // $\r
+ { 0x23, 0x13, 0x08, 0x64, 0x62 }, // %\r
+ { 0x36, 0x49, 0x55, 0x22, 0x50 }, // &\r
+ { 0x00, 0x05, 0x03, 0x00, 0x00 }, // '\r
+ { 0x00, 0x1c, 0x22, 0x41, 0x00 }, // (\r
+ { 0x00, 0x41, 0x22, 0x1c, 0x00 }, // )\r
+ { 0x14, 0x08, 0x3e, 0x08, 0x14 }, // *\r
+ { 0x08, 0x08, 0x3e, 0x08, 0x08 }, // +\r
+ { 0x00, 0x50, 0x30, 0x00, 0x00 }, // ,\r
+ { 0x08, 0x08, 0x08, 0x08, 0x08 }, // -\r
+ { 0x00, 0x60, 0x60, 0x00, 0x00 }, // .\r
+ { 0x20, 0x10, 0x08, 0x04, 0x02 }, // /\r
+ { 0x3e, 0x51, 0x49, 0x45, 0x3e }, // 0\r
+ { 0x00, 0x42, 0x7f, 0x40, 0x00 }, // 1\r
+ { 0x42, 0x61, 0x51, 0x49, 0x46 }, // 2\r
+ { 0x21, 0x41, 0x45, 0x4b, 0x31 }, // 3\r
+ { 0x18, 0x14, 0x12, 0x7f, 0x10 }, // 4\r
+ { 0x27, 0x45, 0x45, 0x45, 0x39 }, // 5\r
+ { 0x3c, 0x4a, 0x49, 0x49, 0x30 }, // 6\r
+ { 0x01, 0x71, 0x09, 0x05, 0x03 }, // 7\r
+ { 0x36, 0x49, 0x49, 0x49, 0x36 }, // 8\r
+ { 0x06, 0x49, 0x49, 0x29, 0x1e }, // 9\r
+ { 0x00, 0x36, 0x36, 0x00, 0x00 }, // :\r
+ { 0x00, 0x56, 0x36, 0x00, 0x00 }, // ;\r
+ { 0x08, 0x14, 0x22, 0x41, 0x00 }, // <\r
+ { 0x14, 0x14, 0x14, 0x14, 0x14 }, // =\r
+ { 0x00, 0x41, 0x22, 0x14, 0x08 }, // >\r
+ { 0x02, 0x01, 0x51, 0x09, 0x06 }, // ?\r
+ { 0x32, 0x49, 0x79, 0x41, 0x3e }, // @\r
+ { 0x7e, 0x11, 0x11, 0x11, 0x7e }, // A\r
+ { 0x7f, 0x49, 0x49, 0x49, 0x36 }, // B\r
+ { 0x3e, 0x41, 0x41, 0x41, 0x22 }, // C\r
+ { 0x7f, 0x41, 0x41, 0x22, 0x1c }, // D\r
+ { 0x7f, 0x49, 0x49, 0x49, 0x41 }, // E\r
+ { 0x7f, 0x09, 0x09, 0x09, 0x01 }, // F\r
+ { 0x3e, 0x41, 0x49, 0x49, 0x7a }, // G\r
+ { 0x7f, 0x08, 0x08, 0x08, 0x7f }, // H\r
+ { 0x00, 0x41, 0x7f, 0x41, 0x00 }, // I\r
+ { 0x20, 0x40, 0x41, 0x3f, 0x01 }, // J\r
+ { 0x7f, 0x08, 0x14, 0x22, 0x41 }, // K\r
+ { 0x7f, 0x40, 0x40, 0x40, 0x40 }, // L\r
+ { 0x7f, 0x02, 0x0c, 0x02, 0x7f }, // M\r
+ { 0x7f, 0x04, 0x08, 0x10, 0x7f }, // N\r
+ { 0x3e, 0x41, 0x41, 0x41, 0x3e }, // O\r
+ { 0x7f, 0x09, 0x09, 0x09, 0x06 }, // P\r
+ { 0x3e, 0x41, 0x51, 0x21, 0x5e }, // Q\r
+ { 0x7f, 0x09, 0x19, 0x29, 0x46 }, // R\r
+ { 0x46, 0x49, 0x49, 0x49, 0x31 }, // S\r
+ { 0x01, 0x01, 0x7f, 0x01, 0x01 }, // T\r
+ { 0x3f, 0x40, 0x40, 0x40, 0x3f }, // U\r
+ { 0x1f, 0x20, 0x40, 0x20, 0x1f }, // V\r
+ { 0x3f, 0x40, 0x38, 0x40, 0x3f }, // W\r
+ { 0x63, 0x14, 0x08, 0x14, 0x63 }, // X\r
+ { 0x07, 0x08, 0x70, 0x08, 0x07 }, // Y\r
+ { 0x61, 0x51, 0x49, 0x45, 0x43 }, // Z\r
+ { 0x00, 0x7f, 0x41, 0x41, 0x00 }, // [\r
+ { 0x02, 0x04, 0x08, 0x10, 0x20 }, // "\"\r
+ { 0x00, 0x41, 0x41, 0x7f, 0x00 }, // ]\r
+ { 0x04, 0x02, 0x01, 0x02, 0x04 }, // ^\r
+ { 0x40, 0x40, 0x40, 0x40, 0x40 }, // _\r
+ { 0x00, 0x01, 0x02, 0x04, 0x00 }, // `\r
+ { 0x20, 0x54, 0x54, 0x54, 0x78 }, // a\r
+ { 0x7f, 0x48, 0x44, 0x44, 0x38 }, // b\r
+ { 0x38, 0x44, 0x44, 0x44, 0x20 }, // c\r
+ { 0x38, 0x44, 0x44, 0x48, 0x7f }, // d\r
+ { 0x38, 0x54, 0x54, 0x54, 0x18 }, // e\r
+ { 0x08, 0x7e, 0x09, 0x01, 0x02 }, // f\r
+ { 0x0c, 0x52, 0x52, 0x52, 0x3e }, // g\r
+ { 0x7f, 0x08, 0x04, 0x04, 0x78 }, // h\r
+ { 0x00, 0x44, 0x7d, 0x40, 0x00 }, // i\r
+ { 0x20, 0x40, 0x44, 0x3d, 0x00 }, // j\r
+ { 0x7f, 0x10, 0x28, 0x44, 0x00 }, // k\r
+ { 0x00, 0x41, 0x7f, 0x40, 0x00 }, // l\r
+ { 0x7c, 0x04, 0x18, 0x04, 0x78 }, // m\r
+ { 0x7c, 0x08, 0x04, 0x04, 0x78 }, // n\r
+ { 0x38, 0x44, 0x44, 0x44, 0x38 }, // o\r
+ { 0x7c, 0x14, 0x14, 0x14, 0x08 }, // p\r
+ { 0x08, 0x14, 0x14, 0x18, 0x7c }, // q\r
+ { 0x7c, 0x08, 0x04, 0x04, 0x08 }, // r\r
+ { 0x48, 0x54, 0x54, 0x54, 0x20 }, // s\r
+ { 0x04, 0x3f, 0x44, 0x40, 0x20 }, // t\r
+ { 0x3c, 0x40, 0x40, 0x20, 0x7c }, // u\r
+ { 0x1c, 0x20, 0x40, 0x20, 0x1c }, // v\r
+ { 0x3c, 0x40, 0x30, 0x40, 0x3c }, // w\r
+ { 0x44, 0x28, 0x10, 0x28, 0x44 }, // x\r
+ { 0x0c, 0x50, 0x50, 0x50, 0x3c }, // y\r
+ { 0x44, 0x64, 0x54, 0x4c, 0x44 }, // z\r
+ { 0x00, 0x08, 0x36, 0x41, 0x00 }, // {\r
+ { 0x00, 0x00, 0x7f, 0x00, 0x00 }, // |\r
+ { 0x00, 0x41, 0x36, 0x08, 0x00 }, // }\r
+ { 0x02, 0x01, 0x02, 0x04, 0x02 }, // ~\r
+ { 0x02, 0x01, 0x02, 0x04, 0x02 }, // ~\r
+};\r
+\r
+//*****************************************************************************\r
+//\r
+// The sequence of commands used to initialize the SSD0303 controller. Each\r
+// command is described as follows: there is a byte specifying the number of\r
+// bytes in the command sequence, followed by that many bytes of command data.\r
+// Note: This initialization sequence is derived from OSRAM App Note AN018.\r
+//\r
+//*****************************************************************************\r
+static const unsigned char g_pucOSRAM128x64x4Init[] =\r
+{\r
+ //\r
+ // Column Address\r
+ //\r
+ 4, 0x15, 0, 63, 0xe3,\r
+\r
+ //\r
+ // Row Address\r
+ //\r
+ 4, 0x75, 0, 63, 0xe3,\r
+\r
+ //\r
+ // Contrast Control\r
+ //\r
+ 3, 0x81, 50, 0xe3,\r
+\r
+ //\r
+ // Half Current Range\r
+ //\r
+ 2, 0x85, 0xe3,\r
+\r
+ //\r
+ // Display Re-map\r
+ //\r
+ 3, 0xA0, OSRAM_INIT_REMAP, 0xe3,\r
+\r
+ //\r
+ // Display Start Line\r
+ //\r
+ 3, 0xA1, 0, 0xe3,\r
+\r
+ //\r
+ // Display Offset\r
+ //\r
+ 3, 0xA2, OSRAM_INIT_OFFSET, 0xe3,\r
+\r
+ //\r
+ // Display Mode Normal\r
+ //\r
+ 2, 0xA4, 0xe3,\r
+\r
+ //\r
+ // Multiplex Ratio\r
+ //\r
+ 3, 0xA8, 63, 0xe3,\r
+\r
+ //\r
+ // Phase Length\r
+ //\r
+ 3, 0xB1, 0x22, 0xe3,\r
+\r
+ //\r
+ // Row Period\r
+ //\r
+ 3, 0xB2, 70, 0xe3,\r
+\r
+ //\r
+ // Display Clock Divide\r
+ //\r
+ 3, 0xB3, 0xF1, 0xe3,\r
+\r
+ //\r
+ // VSL\r
+ //\r
+ 3, 0xBF, 0x0D, 0xe3,\r
+\r
+ //\r
+ // VCOMH\r
+ //\r
+ 3, 0xBE, 0x02, 0xe3,\r
+\r
+ //\r
+ // VP\r
+ //\r
+ 3, 0xBC, 0x10, 0xe3,\r
+\r
+ //\r
+ // Gamma\r
+ //\r
+ 10, 0xB8, 0x01, 0x11, 0x22, 0x32, 0x43, 0x54, 0x65, 0x76, 0xe3,\r
+\r
+ //\r
+ // Set DC-DC\r
+ 3, 0xAD, 0x03, 0xe3,\r
+\r
+ //\r
+ // Display ON/OFF\r
+ //\r
+ 2, 0xAF, 0xe3,\r
+};\r
+\r
+//*****************************************************************************\r
+//\r
+//! \internal\r
+//!\r
+//! Write a sequence of command bytes to the SSD0323 controller.\r
+//!\r
+//! The data is written in a polled fashion; this function will not return\r
+//! until the entire byte sequence has been written to the controller.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+static void\r
+OSRAMWriteCommand(const unsigned char *pucBuffer, unsigned long ulCount)\r
+{\r
+ unsigned long ulTemp;\r
+\r
+ //\r
+ // Return iff SSI port is not enabled for OSRAM.\r
+ //\r
+ if(!g_bSSIEnabled)\r
+ {\r
+ return;\r
+ }\r
+\r
+ //\r
+ // Clear the command/control bit to enable command mode.\r
+ //\r
+ GPIOPinWrite(GPIO_PORTC_BASE, GPIO_PIN_7, 0);\r
+\r
+ //\r
+ // Loop while there are more bytes left to be transferred.\r
+ //\r
+ while(ulCount != 0)\r
+ {\r
+ //\r
+ // Write the next byte to the controller.\r
+ //\r
+ SSIDataPut(SSI0_BASE, *pucBuffer++);\r
+\r
+ //\r
+ // Dummy read to drain the fifo and time the GPIO signal.\r
+ //\r
+ SSIDataGet(SSI0_BASE, &ulTemp);\r
+\r
+ //\r
+ // Decrement the BYTE counter.\r
+ //\r
+ ulCount--;\r
+ }\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! \internal\r
+//!\r
+//! Write a sequence of data bytes to the SSD0323 controller.\r
+//!\r
+//! The data is written in a polled fashion; this function will not return\r
+//! until the entire byte sequence has been written to the controller.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+static void\r
+OSRAMWriteData(const unsigned char *pucBuffer, unsigned long ulCount)\r
+{\r
+ unsigned long ulTemp;\r
+\r
+ //\r
+ // Return iff SSI port is not enabled for OSRAM.\r
+ //\r
+ if(!g_bSSIEnabled)\r
+ {\r
+ return;\r
+ }\r
+\r
+ //\r
+ // Set the command/control bit to enable data mode.\r
+ //\r
+ GPIOPinWrite(GPIO_PORTC_BASE, GPIO_PIN_7, GPIO_PIN_7);\r
+\r
+ //\r
+ // Loop while there are more bytes left to be transferred.\r
+ //\r
+ while(ulCount != 0)\r
+ {\r
+ //\r
+ // Write the next byte to the controller.\r
+ //\r
+ SSIDataPut(SSI0_BASE, *pucBuffer++);\r
+\r
+ //\r
+ // Dummy read to drain the fifo and time the GPIO signal.\r
+ //\r
+ SSIDataGet(SSI0_BASE, &ulTemp);\r
+\r
+ //\r
+ // Decrement the BYTE counter.\r
+ //\r
+ ulCount--;\r
+ }\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! Clears the OLED display.\r
+//!\r
+//! This function will clear the display RAM. All pixels in the display will\r
+//! be turned off.\r
+//!\r
+//! This function is contained in <tt>osram128x64x4.c</tt>, with\r
+//! <tt>osram128x64x4.h</tt> containing the API definition for use by\r
+//! applications.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+void\r
+OSRAM128x64x4Clear(void)\r
+{\r
+ static const unsigned char pucCommand1[] = { 0x15, 0, 63 };\r
+ static const unsigned char pucCommand2[] = { 0x75, 0, 79 };\r
+ unsigned long ulRow, ulColumn;\r
+ static unsigned char pucZeroBuffer[8] = { 0, 0, 0, 0, 0, 0, 0, 0};\r
+\r
+ //\r
+ // Set the window to fill the entire display.\r
+ //\r
+ OSRAMWriteCommand(pucCommand1, sizeof(pucCommand1));\r
+ OSRAMWriteCommand(pucCommand2, sizeof(pucCommand2));\r
+ OSRAMWriteCommand(g_pucOSRAM128x64x4VerticalInc,\r
+ sizeof(g_pucOSRAM128x64x4VerticalInc));\r
+\r
+ //\r
+ // In vertical address increment mode, loop through each column, filling\r
+ // each row with 0.\r
+ //\r
+ for(ulColumn = 0; ulColumn < (128/2); ulColumn++)\r
+ {\r
+ //\r
+ // 8 rows (bytes) per row of text.\r
+ //\r
+ for(ulRow = 0; ulRow < 80; ulRow += 8)\r
+ {\r
+ OSRAMWriteData(pucZeroBuffer, sizeof(pucZeroBuffer));\r
+ }\r
+ }\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! Displays a string on the OLED display.\r
+//!\r
+//! \param pcStr is a pointer to the string to display.\r
+//! \param ulX is the horizontal position to display the string, specified in\r
+//! columns from the left edge of the display.\r
+//! \param ulY is the vertical position to display the string, specified in\r
+//! rows from the top edge of the display.\r
+//! \param ucLevel is the 4-bit grey scale value to be used for displayed text.\r
+//!\r
+//! This function will draw a string on the display. Only the ASCII characters\r
+//! between 32 (space) and 126 (tilde) are supported; other characters will\r
+//! result in random data being draw on the display (based on whatever appears\r
+//! before/after the font in memory). The font is mono-spaced, so characters\r
+//! such as "i" and "l" have more white space around them than characters such\r
+//! as "m" or "w".\r
+//!\r
+//! If the drawing of the string reaches the right edge of the display, no more\r
+//! characters will be drawn. Therefore, special care is not required to avoid\r
+//! supplying a string that is "too long" to display.\r
+//!\r
+//! This function is contained in <tt>osram128x64x4.c</tt>, with\r
+//! <tt>osram128x64x4.h</tt> containing the API definition for use by\r
+//! applications.\r
+//!\r
+//! \note Because the OLED display packs 2 pixels of data in a single byte, the\r
+//! parameter \e ulX must be an even column number (e.g. 0, 2, 4, etc).\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+void\r
+OSRAM128x64x4StringDraw(const char *pcStr, unsigned long ulX,\r
+ unsigned long ulY, unsigned char ucLevel)\r
+{\r
+ static unsigned char pucBuffer[8];\r
+ unsigned long ulIdx1, ulIdx2;\r
+ unsigned char ucTemp;\r
+\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT(ulX < 128);\r
+ ASSERT((ulX & 1) == 0);\r
+ ASSERT(ulY < 64);\r
+ ASSERT(ucLevel < 16);\r
+\r
+ //\r
+ // Setup a window starting at the specified column and row, ending\r
+ // at the right edge of the display and 8 rows down (single character row).\r
+ //\r
+ pucBuffer[0] = 0x15;\r
+ pucBuffer[1] = ulX / 2;\r
+ pucBuffer[2] = 63;\r
+ OSRAMWriteCommand(pucBuffer, 3);\r
+ pucBuffer[0] = 0x75;\r
+ pucBuffer[1] = ulY;\r
+ pucBuffer[2] = ulY + 7;\r
+ OSRAMWriteCommand(pucBuffer, 3);\r
+ OSRAMWriteCommand(g_pucOSRAM128x64x4VerticalInc,\r
+ sizeof(g_pucOSRAM128x64x4VerticalInc));\r
+\r
+ //\r
+ // Loop while there are more characters in the string.\r
+ //\r
+ while(*pcStr != 0)\r
+ {\r
+ //\r
+ // Get a working copy of the current character and convert to an\r
+ // index into the character bit-map array.\r
+ //\r
+ ucTemp = *pcStr;\r
+ ucTemp &= 0x7F;\r
+ if(ucTemp < ' ')\r
+ {\r
+ ucTemp = ' ';\r
+ }\r
+ else\r
+ {\r
+ ucTemp -= ' ';\r
+ }\r
+\r
+ //\r
+ // Build and display the character buffer.\r
+ //\r
+ for(ulIdx1 = 0; ulIdx1 < 3; ulIdx1++)\r
+ {\r
+ //\r
+ // Convert two columns of 1-bit font data into a single data\r
+ // byte column of 4-bit font data.\r
+ //\r
+ for(ulIdx2 = 0; ulIdx2 < 8; ulIdx2++)\r
+ {\r
+ pucBuffer[ulIdx2] = 0;\r
+ if(g_pucFont[ucTemp][ulIdx1*2] & (1 << ulIdx2))\r
+ {\r
+ pucBuffer[ulIdx2] = ((ucLevel << 4) & 0xf0);\r
+ }\r
+ if((ulIdx1 < 2) &&\r
+ (g_pucFont[ucTemp][ulIdx1*2+1] & (1 << ulIdx2)))\r
+ {\r
+ pucBuffer[ulIdx2] |= ((ucLevel << 0) & 0x0f);\r
+ }\r
+ }\r
+\r
+ //\r
+ // If there is room, dump the single data byte column to the\r
+ // display. Otherwise, bail out.\r
+ //\r
+ if(ulX < 126)\r
+ {\r
+ OSRAMWriteData(pucBuffer, 8);\r
+ ulX += 2;\r
+ }\r
+ else\r
+ {\r
+ return;\r
+ }\r
+ }\r
+\r
+ //\r
+ // Advance to the next character.\r
+ //\r
+ pcStr++;\r
+ }\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! Displays an image on the OLED display.\r
+//!\r
+//! \param pucImage is a pointer to the image data.\r
+//! \param ulX is the horizontal position to display this image, specified in\r
+//! columns from the left edge of the display.\r
+//! \param ulY is the vertical position to display this image, specified in\r
+//! rows from the top of the display.\r
+//! \param ulWidth is the width of the image, specified in columns.\r
+//! \param ulHeight is the height of the image, specified in rows.\r
+//!\r
+//! This function will display a bitmap graphic on the display. Because of the\r
+//! format of the display RAM, the starting column (/e ulX) and the number of\r
+//! columns (/e ulWidth) must be an integer multiple of two.\r
+//!\r
+//! The image data is organized with the first row of image data appearing left\r
+//! to right, followed immediately by the second row of image data. Each byte\r
+//! contains the data for two columns in the current row, with the leftmost\r
+//! column being contained in bits 7:4 and the rightmost column being contained\r
+//! in bits 3:0.\r
+//!\r
+//! For example, an image six columns wide and seven scan lines tall would\r
+//! be arranged as follows (showing how the twenty one bytes of the image would\r
+//! appear on the display):\r
+//!\r
+//! \verbatim\r
+//! +-------------------+-------------------+-------------------+\r
+//! | Byte 0 | Byte 1 | Byte 2 |\r
+//! +---------+---------+---------+---------+---------+---------+\r
+//! | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 |\r
+//! +---------+---------+---------+---------+---------+---------+\r
+//! | Byte 3 | Byte 4 | Byte 5 |\r
+//! +---------+---------+---------+---------+---------+---------+\r
+//! | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 |\r
+//! +---------+---------+---------+---------+---------+---------+\r
+//! | Byte 6 | Byte 7 | Byte 8 |\r
+//! +---------+---------+---------+---------+---------+---------+\r
+//! | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 |\r
+//! +---------+---------+---------+---------+---------+---------+\r
+//! | Byte 9 | Byte 10 | Byte 11 |\r
+//! +---------+---------+---------+---------+---------+---------+\r
+//! | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 |\r
+//! +---------+---------+---------+---------+---------+---------+\r
+//! | Byte 12 | Byte 13 | Byte 14 |\r
+//! +---------+---------+---------+--3------+---------+---------+\r
+//! | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 |\r
+//! +---------+---------+---------+---------+---------+---------+\r
+//! | Byte 15 | Byte 16 | Byte 17 |\r
+//! +---------+---------+---------+---------+---------+---------+\r
+//! | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 |\r
+//! +---------+---------+---------+---------+---------+---------+\r
+//! | Byte 18 | Byte 19 | Byte 20 |\r
+//! +---------+---------+---------+---------+---------+---------+\r
+//! | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 |\r
+//! +---------+---------+---------+---------+---------+---------+\r
+//! \endverbatim\r
+//!\r
+//! This function is contained in <tt>osram128x64x4.c</tt>, with\r
+//! <tt>osram128x64x4.h</tt> containing the API definition for use by`\r
+//! applications.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+void\r
+OSRAM128x64x4ImageDraw(const unsigned char *pucImage, unsigned long ulX,\r
+ unsigned long ulY, unsigned long ulWidth,\r
+ unsigned long ulHeight)\r
+{\r
+ static unsigned char pucBuffer[8];\r
+\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT(ulX < 128);\r
+ ASSERT((ulX & 1) == 0);\r
+ ASSERT(ulY < 64);\r
+ ASSERT((ulX + ulWidth) <= 128);\r
+ ASSERT((ulY + ulHeight) <= 64);\r
+ ASSERT((ulWidth & 1) == 0);\r
+\r
+ //\r
+ // Setup a window starting at the specified column and row, and ending\r
+ // at the column + width and row+height.\r
+ //\r
+ pucBuffer[0] = 0x15;\r
+ pucBuffer[1] = ulX / 2;\r
+ pucBuffer[2] = (ulX + ulWidth - 2) / 2;\r
+ OSRAMWriteCommand(pucBuffer, 3);\r
+ pucBuffer[0] = 0x75;\r
+ pucBuffer[1] = ulY;\r
+ pucBuffer[2] = ulY + ulHeight - 1;\r
+ OSRAMWriteCommand(pucBuffer, 3);\r
+ OSRAMWriteCommand(g_pucOSRAM128x64x4HorizontalInc,\r
+ sizeof(g_pucOSRAM128x64x4HorizontalInc));\r
+\r
+ //\r
+ // Loop while there are more rows to display.\r
+ //\r
+ while(ulHeight--)\r
+ {\r
+ //\r
+ // Write this row of image data.\r
+ //\r
+ OSRAMWriteData(pucImage, (ulWidth / 2));\r
+\r
+ //\r
+ // Advance to the next row of the image.\r
+ //\r
+ pucImage += (ulWidth / 2);\r
+ }\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! Enable the SSI component of the OLED display driver.\r
+//!\r
+//! \param ulFrequency specifies the SSI Clock Frequency to be used.\r
+//!\r
+//! This function initializes the SSI interface to the OLED display.\r
+//!\r
+//! This function is contained in <tt>osram128x64x4.c</tt>, with\r
+//! <tt>osram128x64x4.h</tt> containing the API definition for use by\r
+//! applications.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+void\r
+OSRAM128x64x4Enable(unsigned long ulFrequency)\r
+{\r
+ unsigned long ulTemp;\r
+\r
+ //\r
+ // Disable the SSI port.\r
+ //\r
+ SSIDisable(SSI0_BASE);\r
+\r
+ //\r
+ // Configure the SSI0 port for master mode.\r
+ //\r
+ SSIConfig(SSI0_BASE, SSI_FRF_MOTO_MODE_2, SSI_MODE_MASTER, ulFrequency, 8);\r
+\r
+ //\r
+ // (Re)Enable SSI control of the FSS pin.\r
+ //\r
+ GPIOPinTypeSSI(GPIO_PORTA_BASE, GPIO_PIN_3);\r
+ GPIOPadConfigSet(GPIO_PORTA_BASE, GPIO_PIN_3, GPIO_STRENGTH_8MA,\r
+ GPIO_PIN_TYPE_STD_WPU);\r
+\r
+ //\r
+ // Enable the SSI port.\r
+ //\r
+ SSIEnable(SSI0_BASE);\r
+\r
+ //\r
+ // Drain the receive fifo.\r
+ //\r
+ while(SSIDataNonBlockingGet(SSI0_BASE, &ulTemp) != 0)\r
+ {\r
+ }\r
+\r
+ //\r
+ // Indicate that the OSRAM driver can use the SSI Port.\r
+ //\r
+ g_bSSIEnabled = true;\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! Enable the SSI component of the OLED display driver.\r
+//!\r
+//! \param ulFrequency specifies the SSI Clock Frequency to be used.\r
+//!\r
+//! This function initializes the SSI interface to the OLED display.\r
+//!\r
+//! This function is contained in <tt>osram128x64x4.c</tt>, with\r
+//! <tt>osram128x64x4.h</tt> containing the API definition for use by\r
+//! applications.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+void\r
+OSRAM128x64x4Disable(void)\r
+{\r
+ unsigned long ulTemp;\r
+\r
+ //\r
+ // Indicate that the OSRAM driver can no longer use the SSI Port.\r
+ //\r
+ g_bSSIEnabled = false;\r
+\r
+ //\r
+ // Drain the receive fifo.\r
+ //\r
+ while(SSIDataNonBlockingGet(SSI0_BASE, &ulTemp) != 0)\r
+ {\r
+ }\r
+\r
+ //\r
+ // Disable the SSI port.\r
+ //\r
+ SSIDisable(SSI0_BASE);\r
+\r
+ //\r
+ // Disable SSI control of the FSS pin.\r
+ //\r
+ GPIODirModeSet(GPIO_PORTA_BASE, GPIO_PIN_3, GPIO_DIR_MODE_OUT);\r
+ GPIOPadConfigSet(GPIO_PORTA_BASE, GPIO_PIN_3, GPIO_STRENGTH_8MA,\r
+ GPIO_PIN_TYPE_STD_WPU);\r
+ GPIOPinWrite(GPIO_PORTA_BASE, GPIO_PIN_3, GPIO_PIN_3);\r
+\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! Initialize the OLED display.\r
+//!\r
+//! \param ulFrequency specifies the SSI Clock Frequency to be used.\r
+//!\r
+//! This function initializes the SSI interface to the OLED display and\r
+//! configures the SSD0323 controller on the panel.\r
+//!\r
+//! This function is contained in <tt>osram128x64x4.c</tt>, with\r
+//! <tt>osram128x64x4.h</tt> containing the API definition for use by\r
+//! applications.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+void\r
+OSRAM128x64x4Init(unsigned long ulFrequency)\r
+{\r
+ unsigned long ulIdx;\r
+\r
+ //\r
+ // Enable the SSI0 and GPIO port blocks as they are needed by this driver.\r
+ //\r
+ SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI0);\r
+ SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA);\r
+ SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOC);\r
+\r
+ //\r
+ // Configure the SSI0CLK and SSIOTX pins for SSI operation.\r
+ //\r
+ GPIOPinTypeSSI(GPIO_PORTA_BASE, GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_5);\r
+ GPIOPadConfigSet(GPIO_PORTA_BASE, GPIO_PIN_2, GPIO_STRENGTH_8MA,\r
+ GPIO_PIN_TYPE_STD_WPU);\r
+ GPIOPadConfigSet(GPIO_PORTA_BASE, GPIO_PIN_3, GPIO_STRENGTH_8MA,\r
+ GPIO_PIN_TYPE_STD_WPU);\r
+ GPIOPadConfigSet(GPIO_PORTA_BASE, GPIO_PIN_5, GPIO_STRENGTH_8MA,\r
+ GPIO_PIN_TYPE_STD_WPU);\r
+\r
+ //\r
+ // Configure the PC7 pin as a D/Cn signal for OLED device.\r
+ //\r
+ GPIODirModeSet(GPIO_PORTC_BASE, GPIO_PIN_7, GPIO_DIR_MODE_OUT);\r
+ GPIOPadConfigSet(GPIO_PORTC_BASE, GPIO_PIN_7, GPIO_STRENGTH_8MA,\r
+ GPIO_PIN_TYPE_STD);\r
+ GPIOPinWrite(GPIO_PORTC_BASE, GPIO_PIN_7, GPIO_PIN_7);\r
+\r
+ //\r
+ // Configure and enable the SSI0 port for master mode.\r
+ //\r
+ OSRAM128x64x4Enable(ulFrequency);\r
+\r
+ //\r
+ // Clear the frame buffer.\r
+ //\r
+ OSRAM128x64x4Clear();\r
+\r
+ //\r
+ // Initialize the SSD0323 controller. Loop through the initialization\r
+ // sequence array, sending each command "string" to the controller.\r
+ //\r
+ for(ulIdx = 0; ulIdx < sizeof(g_pucOSRAM128x64x4Init);\r
+ ulIdx += g_pucOSRAM128x64x4Init[ulIdx] + 1)\r
+ {\r
+ //\r
+ // Send this command.\r
+ //\r
+ OSRAMWriteCommand(g_pucOSRAM128x64x4Init + ulIdx + 1,\r
+ g_pucOSRAM128x64x4Init[ulIdx] - 1);\r
+ }\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! Turns on the OLED display.\r
+//!\r
+//! This function will turn on the OLED display, causing it to display the\r
+//! contents of its internal frame buffer.\r
+//!\r
+//! This function is contained in <tt>osram128x64x4.c</tt>, with\r
+//! <tt>osram128x64x4.h</tt> containing the API definition for use by\r
+//! applications.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+void\r
+OSRAM128x64x4DisplayOn(void)\r
+{\r
+ unsigned long ulIdx;\r
+\r
+ //\r
+ // Initialize the SSD0323 controller. Loop through the initialization\r
+ // sequence array, sending each command "string" to the controller.\r
+ //\r
+ for(ulIdx = 0; ulIdx < sizeof(g_pucOSRAM128x64x4Init);\r
+ ulIdx += g_pucOSRAM128x64x4Init[ulIdx] + 1)\r
+ {\r
+ //\r
+ // Send this command.\r
+ //\r
+ OSRAMWriteCommand(g_pucOSRAM128x64x4Init + ulIdx + 1,\r
+ g_pucOSRAM128x64x4Init[ulIdx] - 1);\r
+ }\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! Turns off the OLED display.\r
+//!\r
+//! This function will turn off the OLED display. This will stop the scanning\r
+//! of the panel and turn off the on-chip DC-DC converter, preventing damage to\r
+//! the panel due to burn-in (it has similar characters to a CRT in this\r
+//! respect).\r
+//!\r
+//! This function is contained in <tt>osram128x64x4.c</tt>, with\r
+//! <tt>osram128x64x4.h</tt> containing the API definition for use by\r
+//! applications.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+void\r
+OSRAM128x64x4DisplayOff(void)\r
+{\r
+ static const unsigned char pucCommand1[] =\r
+ {\r
+ 0xAE, 0xAD, 0x02\r
+ };\r
+\r
+ //\r
+ // Turn off the DC-DC converter and the display.\r
+ //\r
+ OSRAMWriteCommand(pucCommand1, sizeof(pucCommand1));\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+// Close the Doxygen group.\r
+//! @}\r
+//\r
+//*****************************************************************************\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// osram128x64x4.h - Prototypes for the driver for the OSRAM 128x64x4 graphical\r
+// OLED display.\r
+//\r
+// Copyright (c) 2006-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __OSRAM128X64X4_H__\r
+#define __OSRAM128X64X4_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the driver APIs.\r
+//\r
+//*****************************************************************************\r
+extern void OSRAM128x64x4Clear(void);\r
+extern void OSRAM128x64x4StringDraw(const char *pcStr,\r
+ unsigned long ulX,\r
+ unsigned long ulY,\r
+ unsigned char ucLevel);\r
+extern void OSRAM128x64x4ImageDraw(const unsigned char *pucImage,\r
+ unsigned long ulX,\r
+ unsigned long ulY,\r
+ unsigned long ulWidth,\r
+ unsigned long ulHeight);\r
+extern void OSRAM128x64x4Init(unsigned long ulFrequency);\r
+extern void OSRAM128x64x4Enable(unsigned long ulFrequency);\r
+extern void OSRAM128x64x4Disable(void);\r
+extern void OSRAM128x64x4DisplayOn(void);\r
+extern void OSRAM128x64x4DisplayOff(void);\r
+\r
+//*****************************************************************************\r
+//\r
+// The following macro(s) map old names for the OSRAM functions to the new\r
+// names. In new code, the new names should be used in favor of the old names.\r
+//\r
+//*****************************************************************************\r
+#ifndef DEPRECATED\r
+#define OSRAM128x64x1InitSSI OSRAM128x64x4Enable\r
+#endif\r
+\r
+#endif // __OSRAM128X64X4_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// pwm.h - API function protoypes for Pulse Width Modulation (PWM) ports\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __PWM_H__\r
+#define __PWM_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// The following defines are passed to PWMGenConfigure() as the ulConfig\r
+// parameter and specify the configuration of the PWM generator.\r
+//\r
+//*****************************************************************************\r
+#define PWM_GEN_MODE_DOWN 0x00000000 // Down count mode\r
+#define PWM_GEN_MODE_UP_DOWN 0x00000002 // Up/Down count mode\r
+#define PWM_GEN_MODE_SYNC 0x00000038 // Synchronous updates\r
+#define PWM_GEN_MODE_NO_SYNC 0x00000000 // Immediate updates\r
+#define PWM_GEN_MODE_DBG_RUN 0x00000004 // Continue running in debug mode\r
+#define PWM_GEN_MODE_DBG_STOP 0x00000000 // Stop running in debug mode\r
+\r
+//*****************************************************************************\r
+//\r
+// Defines for enabling, disabling, and clearing PWM generator interrupts and\r
+// triggers.\r
+//\r
+//*****************************************************************************\r
+#define PWM_INT_CNT_ZERO 0x00000001 // Int if COUNT = 0\r
+#define PWM_INT_CNT_LOAD 0x00000002 // Int if COUNT = LOAD\r
+#define PWM_INT_CNT_AU 0x00000004 // Int if COUNT = CMPA U\r
+#define PWM_INT_CNT_AD 0x00000008 // Int if COUNT = CMPA D\r
+#define PWM_INT_CNT_BU 0x00000010 // Int if COUNT = CMPA U\r
+#define PWM_INT_CNT_BD 0x00000020 // Int if COUNT = CMPA D\r
+#define PWM_TR_CNT_ZERO 0x00000100 // Trig if COUNT = 0\r
+#define PWM_TR_CNT_LOAD 0x00000200 // Trig if COUNT = LOAD\r
+#define PWM_TR_CNT_AU 0x00000400 // Trig if COUNT = CMPA U\r
+#define PWM_TR_CNT_AD 0x00000800 // Trig if COUNT = CMPA D\r
+#define PWM_TR_CNT_BU 0x00001000 // Trig if COUNT = CMPA U\r
+#define PWM_TR_CNT_BD 0x00002000 // Trig if COUNT = CMPA D\r
+\r
+//*****************************************************************************\r
+//\r
+// Defines for enabling, disabling, and clearing PWM interrupts.\r
+//\r
+//*****************************************************************************\r
+#define PWM_INT_GEN_0 0x00000001 // Generator 0 interrupt\r
+#define PWM_INT_GEN_1 0x00000002 // Generator 1 interrupt\r
+#define PWM_INT_GEN_2 0x00000004 // Generator 2 interrupt\r
+#define PWM_INT_FAULT 0x00010000 // Fault interrupt\r
+\r
+//*****************************************************************************\r
+//\r
+// Defines to identify the generators within a module.\r
+//\r
+//*****************************************************************************\r
+#define PWM_GEN_0 0x00000040 // Offset address of Gen0\r
+#define PWM_GEN_1 0x00000080 // Offset address of Gen1\r
+#define PWM_GEN_2 0x000000C0 // Offset address of Gen2\r
+\r
+#define PWM_GEN_0_BIT 0x00000001 // Bit-wise ID for Gen0\r
+#define PWM_GEN_1_BIT 0x00000002 // Bit-wise ID for Gen1\r
+#define PWM_GEN_2_BIT 0x00000004 // Bit-wise ID for Gen2\r
+\r
+//*****************************************************************************\r
+//\r
+// Defines to identify the outputs within a module.\r
+//\r
+//*****************************************************************************\r
+#define PWM_OUT_0 0x00000040 // Encoded offset address of PWM0\r
+#define PWM_OUT_1 0x00000041 // Encoded offset address of PWM1\r
+#define PWM_OUT_2 0x00000082 // Encoded offset address of PWM2\r
+#define PWM_OUT_3 0x00000083 // Encoded offset address of PWM3\r
+#define PWM_OUT_4 0x000000C4 // Encoded offset address of PWM4\r
+#define PWM_OUT_5 0x000000C5 // Encoded offset address of PWM5\r
+\r
+#define PWM_OUT_0_BIT 0x00000001 // Bit-wise ID for PWM0\r
+#define PWM_OUT_1_BIT 0x00000002 // Bit-wise ID for PWM1\r
+#define PWM_OUT_2_BIT 0x00000004 // Bit-wise ID for PWM2\r
+#define PWM_OUT_3_BIT 0x00000008 // Bit-wise ID for PWM3\r
+#define PWM_OUT_4_BIT 0x00000010 // Bit-wise ID for PWM4\r
+#define PWM_OUT_5_BIT 0x00000020 // Bit-wise ID for PWM5\r
+\r
+//*****************************************************************************\r
+//\r
+// API Function prototypes\r
+//\r
+//*****************************************************************************\r
+extern void PWMGenConfigure(unsigned long ulBase, unsigned long ulGen,\r
+ unsigned long ulConfig);\r
+extern void PWMGenPeriodSet(unsigned long ulBase, unsigned long ulGen,\r
+ unsigned long ulPeriod);\r
+extern unsigned long PWMGenPeriodGet(unsigned long ulBase,\r
+ unsigned long ulGen);\r
+extern void PWMGenEnable(unsigned long ulBase, unsigned long ulGen);\r
+extern void PWMGenDisable(unsigned long ulBase, unsigned long ulGen);\r
+extern void PWMPulseWidthSet(unsigned long ulBase, unsigned long ulPWMOut,\r
+ unsigned long ulWidth);\r
+extern unsigned long PWMPulseWidthGet(unsigned long ulBase,\r
+ unsigned long ulPWMOut);\r
+extern void PWMDeadBandEnable(unsigned long ulBase, unsigned long ulGen,\r
+ unsigned short usRise, unsigned short usFall);\r
+extern void PWMDeadBandDisable(unsigned long ulBase, unsigned long ulGen);\r
+extern void PWMSyncUpdate(unsigned long ulBase, unsigned long ulGenBits);\r
+extern void PWMSyncTimeBase(unsigned long ulBase, unsigned long ulGenBits);\r
+extern void PWMOutputState(unsigned long ulBase, unsigned long ulPWMOutBits,\r
+ tBoolean bEnable);\r
+extern void PWMOutputInvert(unsigned long ulBase, unsigned long ulPWMOutBits,\r
+ tBoolean bInvert);\r
+extern void PWMOutputFault(unsigned long ulBase, unsigned long ulPWMOutBits,\r
+ tBoolean bFaultKill);\r
+extern void PWMGenIntRegister(unsigned long ulBase, unsigned long ulGen,\r
+ void (*pfnIntHandler)(void));\r
+extern void PWMGenIntUnregister(unsigned long ulBase, unsigned long ulGen);\r
+extern void PWMFaultIntRegister(unsigned long ulBase,\r
+ void (*pfnIntHandler)(void));\r
+extern void PWMFaultIntUnregister(unsigned long ulBase);\r
+extern void PWMGenIntTrigEnable(unsigned long ulBase, unsigned long ulGen,\r
+ unsigned long ulIntTrig);\r
+extern void PWMGenIntTrigDisable(unsigned long ulBase, unsigned long ulGen,\r
+ unsigned long ulIntTrig);\r
+extern unsigned long PWMGenIntStatus(unsigned long ulBase, unsigned long ulGen,\r
+ tBoolean bMasked);\r
+extern void PWMGenIntClear(unsigned long ulBase, unsigned long ulGen,\r
+ unsigned long ulInts);\r
+extern void PWMIntEnable(unsigned long ulBase, unsigned long ulGenFault);\r
+extern void PWMIntDisable(unsigned long ulBase, unsigned long ulGenFault);\r
+extern void PWMFaultIntClear(unsigned long ulBase);\r
+extern unsigned long PWMIntStatus(unsigned long ulBase, tBoolean bMasked);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __PWM_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// qei.h - Prototypes for the Quadrature Encoder Driver.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __QEI_H__\r
+#define __QEI_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to QEIConfigure as the ulConfig paramater.\r
+//\r
+//*****************************************************************************\r
+#define QEI_CONFIG_CAPTURE_A 0x00000000 // Count on ChA edges only\r
+#define QEI_CONFIG_CAPTURE_A_B 0x00000008 // Count on ChA and ChB edges\r
+#define QEI_CONFIG_NO_RESET 0x00000000 // Do not reset on index pulse\r
+#define QEI_CONFIG_RESET_IDX 0x00000010 // Reset position on index pulse\r
+#define QEI_CONFIG_QUADRATURE 0x00000000 // ChA and ChB are quadrature\r
+#define QEI_CONFIG_CLOCK_DIR 0x00000004 // ChA and ChB are clock and dir\r
+#define QEI_CONFIG_NO_SWAP 0x00000000 // Do not swap ChA and ChB\r
+#define QEI_CONFIG_SWAP 0x00000002 // Swap ChA and ChB\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to QEIVelocityConfigure as the ulPreDiv parameter.\r
+//\r
+//*****************************************************************************\r
+#define QEI_VELDIV_1 0x00000000 // Predivide by 1\r
+#define QEI_VELDIV_2 0x00000040 // Predivide by 2\r
+#define QEI_VELDIV_4 0x00000080 // Predivide by 4\r
+#define QEI_VELDIV_8 0x000000C0 // Predivide by 8\r
+#define QEI_VELDIV_16 0x00000100 // Predivide by 16\r
+#define QEI_VELDIV_32 0x00000140 // Predivide by 32\r
+#define QEI_VELDIV_64 0x00000180 // Predivide by 64\r
+#define QEI_VELDIV_128 0x000001C0 // Predivide by 128\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to QEIEnableInts, QEIDisableInts, and QEIClearInts\r
+// as the ulIntFlags parameter, and returned by QEIGetIntStatus.\r
+//\r
+//*****************************************************************************\r
+#define QEI_INTERROR 0x00000008 // Phase error detected\r
+#define QEI_INTDIR 0x00000004 // Direction change\r
+#define QEI_INTTIMER 0x00000002 // Velocity timer expired\r
+#define QEI_INTINDEX 0x00000001 // Index pulse detected\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+extern void QEIEnable(unsigned long ulBase);\r
+extern void QEIDisable(unsigned long ulBase);\r
+extern void QEIConfigure(unsigned long ulBase, unsigned long ulConfig,\r
+ unsigned long ulMaxPosition);\r
+extern unsigned long QEIPositionGet(unsigned long ulBase);\r
+extern void QEIPositionSet(unsigned long ulBase, unsigned long ulPosition);\r
+extern long QEIDirectionGet(unsigned long ulBase);\r
+extern tBoolean QEIErrorGet(unsigned long ulBase);\r
+extern void QEIVelocityEnable(unsigned long ulBase);\r
+extern void QEIVelocityDisable(unsigned long ulBase);\r
+extern void QEIVelocityConfigure(unsigned long ulBase, unsigned long ulPreDiv,\r
+ unsigned long ulPeriod);\r
+extern unsigned long QEIVelocityGet(unsigned long ulBase);\r
+extern void QEIIntRegister(unsigned long ulBase, void (*pfnHandler)(void));\r
+extern void QEIIntUnregister(unsigned long ulBase);\r
+extern void QEIIntEnable(unsigned long ulBase, unsigned long ulIntFlags);\r
+extern void QEIIntDisable(unsigned long ulBase, unsigned long ulIntFlags);\r
+extern unsigned long QEIIntStatus(unsigned long ulBase, tBoolean bMasked);\r
+extern void QEIIntClear(unsigned long ulBase, unsigned long ulIntFlags);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __QEI_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// ssi.h - Prototypes for the Synchronous Serial Interface Driver.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __SSI_H__\r
+#define __SSI_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to SSIIntEnable, SSIIntDisable, and SSIIntClear\r
+// as the ulIntFlags parameter, and returned by SSIIntStatus.\r
+//\r
+//*****************************************************************************\r
+#define SSI_TXFF 0x00000008 // TX FIFO half empty or less\r
+#define SSI_RXFF 0x00000004 // RX FIFO half full or less\r
+#define SSI_RXTO 0x00000002 // RX timeout\r
+#define SSI_RXOR 0x00000001 // RX overrun\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to SSIConfig.\r
+//\r
+//*****************************************************************************\r
+#define SSI_FRF_MOTO_MODE_0 0x00000000 // Moto fmt, polarity 0, phase 0\r
+#define SSI_FRF_MOTO_MODE_1 0x00000002 // Moto fmt, polarity 0, phase 1\r
+#define SSI_FRF_MOTO_MODE_2 0x00000001 // Moto fmt, polarity 1, phase 0\r
+#define SSI_FRF_MOTO_MODE_3 0x00000003 // Moto fmt, polarity 1, phase 1\r
+#define SSI_FRF_TI 0x00000010 // TI frame format\r
+#define SSI_FRF_NMW 0x00000020 // National MicroWire frame format\r
+\r
+#define SSI_MODE_MASTER 0x00000000 // SSI master\r
+#define SSI_MODE_SLAVE 0x00000001 // SSI slave\r
+#define SSI_MODE_SLAVE_OD 0x00000002 // SSI slave with output disabled\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+extern void SSIConfig(unsigned long ulBase, unsigned long ulProtocol,\r
+ unsigned long ulMode, unsigned long ulBitRate,\r
+ unsigned long ulDataWidth);\r
+extern void SSIDataGet(unsigned long ulBase, unsigned long *pulData);\r
+extern long SSIDataNonBlockingGet(unsigned long ulBase,\r
+ unsigned long *pulData);\r
+extern void SSIDataPut(unsigned long ulBase, unsigned long ulData);\r
+extern long SSIDataNonBlockingPut(unsigned long ulBase, unsigned long ulData);\r
+extern void SSIDisable(unsigned long ulBase);\r
+extern void SSIEnable(unsigned long ulBase);\r
+extern void SSIIntClear(unsigned long ulBase, unsigned long ulIntFlags);\r
+extern void SSIIntDisable(unsigned long ulBase, unsigned long ulIntFlags);\r
+extern void SSIIntEnable(unsigned long ulBase, unsigned long ulIntFlags);\r
+extern void SSIIntRegister(unsigned long ulBase, void(*pfnHandler)(void));\r
+extern unsigned long SSIIntStatus(unsigned long ulBase, tBoolean bMasked);\r
+extern void SSIIntUnregister(unsigned long ulBase);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __SSI_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// sysctl.h - Prototypes for the system control driver.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __SYSCTL_H__\r
+#define __SYSCTL_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the\r
+// SysCtlPeripheralPresent(), SysCtlPeripheralEnable(),\r
+// SysCtlPeripheralDisable(), and SysCtlPeripheralReset() APIs as the\r
+// ulPeripheral parameter. The peripherals in the fourth group (upper nibble\r
+// is 3) can only be used with the SysCtlPeripheralPresent() API.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_PERIPH_PWM 0x00100010 // PWM\r
+#define SYSCTL_PERIPH_ADC 0x00100001 // ADC\r
+#define SYSCTL_PERIPH_HIBERNATE 0x00000040 // Hibernation module\r
+#define SYSCTL_PERIPH_WDOG 0x00000008 // Watchdog\r
+#define SYSCTL_PERIPH_CAN0 0x00100100 // CAN 0\r
+#define SYSCTL_PERIPH_CAN1 0x00100200 // CAN 1\r
+#define SYSCTL_PERIPH_UART0 0x10000001 // UART 0\r
+#define SYSCTL_PERIPH_UART1 0x10000002 // UART 1\r
+#define SYSCTL_PERIPH_UART2 0x10000004 // UART 2\r
+#define SYSCTL_PERIPH_SSI 0x10000010 // SSI\r
+#define SYSCTL_PERIPH_SSI0 0x10000010 // SSI 0\r
+#define SYSCTL_PERIPH_SSI1 0x10000020 // SSI 1\r
+#define SYSCTL_PERIPH_QEI 0x10000100 // QEI\r
+#define SYSCTL_PERIPH_QEI0 0x10000100 // QEI 0\r
+#define SYSCTL_PERIPH_QEI1 0x10000200 // QEI 1\r
+#define SYSCTL_PERIPH_I2C 0x10001000 // I2C\r
+#define SYSCTL_PERIPH_I2C0 0x10001000 // I2C 0\r
+#define SYSCTL_PERIPH_I2C1 0x10004000 // I2C 1\r
+#define SYSCTL_PERIPH_TIMER0 0x10100001 // Timer 0\r
+#define SYSCTL_PERIPH_TIMER1 0x10100002 // Timer 1\r
+#define SYSCTL_PERIPH_TIMER2 0x10100004 // Timer 2\r
+#define SYSCTL_PERIPH_TIMER3 0x10100008 // Timer 3\r
+#define SYSCTL_PERIPH_COMP0 0x10100100 // Analog comparator 0\r
+#define SYSCTL_PERIPH_COMP1 0x10100200 // Analog comparator 1\r
+#define SYSCTL_PERIPH_COMP2 0x10100400 // Analog comparator 2\r
+#define SYSCTL_PERIPH_GPIOA 0x20000001 // GPIO A\r
+#define SYSCTL_PERIPH_GPIOB 0x20000002 // GPIO B\r
+#define SYSCTL_PERIPH_GPIOC 0x20000004 // GPIO C\r
+#define SYSCTL_PERIPH_GPIOD 0x20000008 // GPIO D\r
+#define SYSCTL_PERIPH_GPIOE 0x20000010 // GPIO E\r
+#define SYSCTL_PERIPH_GPIOF 0x20000020 // GPIO F\r
+#define SYSCTL_PERIPH_GPIOG 0x20000040 // GPIO G\r
+#define SYSCTL_PERIPH_GPIOH 0x20000080 // GPIO H\r
+#define SYSCTL_PERIPH_ETH 0x20105000 // ETH\r
+#define SYSCTL_PERIPH_MPU 0x30000080 // Cortex M3 MPU\r
+#define SYSCTL_PERIPH_TEMP 0x30000020 // Temperature sensor\r
+#define SYSCTL_PERIPH_PLL 0x30000010 // PLL\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the SysCtlPinPresent() API\r
+// as the ulPin parameter.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_PIN_PWM0 0x00000001 // PWM0 pin\r
+#define SYSCTL_PIN_PWM1 0x00000002 // PWM1 pin\r
+#define SYSCTL_PIN_PWM2 0x00000004 // PWM2 pin\r
+#define SYSCTL_PIN_PWM3 0x00000008 // PWM3 pin\r
+#define SYSCTL_PIN_PWM4 0x00000010 // PWM4 pin\r
+#define SYSCTL_PIN_PWM5 0x00000020 // PWM5 pin\r
+#define SYSCTL_PIN_C0MINUS 0x00000040 // C0- pin\r
+#define SYSCTL_PIN_C0PLUS 0x00000080 // C0+ pin\r
+#define SYSCTL_PIN_C0O 0x00000100 // C0o pin\r
+#define SYSCTL_PIN_C1MINUS 0x00000200 // C1- pin\r
+#define SYSCTL_PIN_C1PLUS 0x00000400 // C1+ pin\r
+#define SYSCTL_PIN_C1O 0x00000800 // C1o pin\r
+#define SYSCTL_PIN_C2MINUS 0x00001000 // C2- pin\r
+#define SYSCTL_PIN_C2PLUS 0x00002000 // C2+ pin\r
+#define SYSCTL_PIN_C2O 0x00004000 // C2o pin\r
+#define SYSCTL_PIN_MC_FAULT0 0x00008000 // MC0 Fault pin\r
+#define SYSCTL_PIN_ADC0 0x00010000 // ADC0 pin\r
+#define SYSCTL_PIN_ADC1 0x00020000 // ADC1 pin\r
+#define SYSCTL_PIN_ADC2 0x00040000 // ADC2 pin\r
+#define SYSCTL_PIN_ADC3 0x00080000 // ADC3 pin\r
+#define SYSCTL_PIN_ADC4 0x00100000 // ADC4 pin\r
+#define SYSCTL_PIN_ADC5 0x00200000 // ADC5 pin\r
+#define SYSCTL_PIN_ADC6 0x00400000 // ADC6 pin\r
+#define SYSCTL_PIN_ADC7 0x00800000 // ADC7 pin\r
+#define SYSCTL_PIN_CCP0 0x01000000 // CCP0 pin\r
+#define SYSCTL_PIN_CCP1 0x02000000 // CCP1 pin\r
+#define SYSCTL_PIN_CCP2 0x04000000 // CCP2 pin\r
+#define SYSCTL_PIN_CCP3 0x08000000 // CCP3 pin\r
+#define SYSCTL_PIN_CCP4 0x10000000 // CCP4 pin\r
+#define SYSCTL_PIN_CCP5 0x20000000 // CCP5 pin\r
+#define SYSCTL_PIN_32KHZ 0x80000000 // 32kHz pin\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the SysCtlLDOSet() API as\r
+// the ulVoltage value, or returned by the SysCtlLDOGet() API.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_LDO_2_25V 0x00000005 // LDO output of 2.25V\r
+#define SYSCTL_LDO_2_30V 0x00000004 // LDO output of 2.30V\r
+#define SYSCTL_LDO_2_35V 0x00000003 // LDO output of 2.35V\r
+#define SYSCTL_LDO_2_40V 0x00000002 // LDO output of 2.40V\r
+#define SYSCTL_LDO_2_45V 0x00000001 // LDO output of 2.45V\r
+#define SYSCTL_LDO_2_50V 0x00000000 // LDO output of 2.50V\r
+#define SYSCTL_LDO_2_55V 0x0000001f // LDO output of 2.55V\r
+#define SYSCTL_LDO_2_60V 0x0000001e // LDO output of 2.60V\r
+#define SYSCTL_LDO_2_65V 0x0000001d // LDO output of 2.65V\r
+#define SYSCTL_LDO_2_70V 0x0000001c // LDO output of 2.70V\r
+#define SYSCTL_LDO_2_75V 0x0000001b // LDO output of 2.75V\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the SysCtlLDOConfigSet() API.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_LDOCFG_ARST 0x00000001 // Allow LDO failure to reset\r
+#define SYSCTL_LDOCFG_NORST 0x00000000 // Do not reset on LDO failure\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the SysCtlIntEnable(),\r
+// SysCtlIntDisable(), and SysCtlIntClear() APIs, or returned in the bit mask\r
+// by the SysCtlIntStatus() API.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_INT_PLL_LOCK 0x00000040 // PLL lock interrupt\r
+#define SYSCTL_INT_CUR_LIMIT 0x00000020 // Current limit interrupt\r
+#define SYSCTL_INT_IOSC_FAIL 0x00000010 // Internal oscillator failure int\r
+#define SYSCTL_INT_MOSC_FAIL 0x00000008 // Main oscillator failure int\r
+#define SYSCTL_INT_POR 0x00000004 // Power on reset interrupt\r
+#define SYSCTL_INT_BOR 0x00000002 // Brown out interrupt\r
+#define SYSCTL_INT_PLL_FAIL 0x00000001 // PLL failure interrupt\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the SysCtlResetCauseClear()\r
+// API or returned by the SysCtlResetCauseGet() API.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_CAUSE_LDO 0x00000020 // LDO power not OK reset\r
+#define SYSCTL_CAUSE_SW 0x00000010 // Software reset\r
+#define SYSCTL_CAUSE_WDOG 0x00000008 // Watchdog reset\r
+#define SYSCTL_CAUSE_BOR 0x00000004 // Brown-out reset\r
+#define SYSCTL_CAUSE_POR 0x00000002 // Power on reset\r
+#define SYSCTL_CAUSE_EXT 0x00000001 // External reset\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the SysCtlBrownOutConfigSet()\r
+// API as the ulConfig parameter.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_BOR_RESET 0x00000002 // Reset instead of interrupting\r
+#define SYSCTL_BOR_RESAMPLE 0x00000001 // Resample BOR before asserting\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the SysCtlPWMClockSet() API\r
+// as the ulConfig parameter, and can be returned by the SysCtlPWMClockGet()\r
+// API.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_PWMDIV_1 0x00000000 // PWM clock is processor clock /1\r
+#define SYSCTL_PWMDIV_2 0x00100000 // PWM clock is processor clock /2\r
+#define SYSCTL_PWMDIV_4 0x00120000 // PWM clock is processor clock /4\r
+#define SYSCTL_PWMDIV_8 0x00140000 // PWM clock is processor clock /8\r
+#define SYSCTL_PWMDIV_16 0x00160000 // PWM clock is processor clock /16\r
+#define SYSCTL_PWMDIV_32 0x00180000 // PWM clock is processor clock /32\r
+#define SYSCTL_PWMDIV_64 0x001A0000 // PWM clock is processor clock /64\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the SysCtlADCSpeedSet() API\r
+// as the ulSpeed parameter, and can be returned by the SyCtlADCSpeedGet()\r
+// API.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_ADCSPEED_1MSPS 0x00000300 // 1,000,000 samples per second\r
+#define SYSCTL_ADCSPEED_500KSPS 0x00000200 // 500,000 samples per second\r
+#define SYSCTL_ADCSPEED_250KSPS 0x00000100 // 250,000 samples per second\r
+#define SYSCTL_ADCSPEED_125KSPS 0x00000000 // 125,000 samples per second\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the SysCtlClockSet() API as\r
+// the ulConfig parameter.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_SYSDIV_1 0x07800000 // Processor clock is osc/pll /1\r
+#define SYSCTL_SYSDIV_2 0x00C00000 // Processor clock is osc/pll /2\r
+#define SYSCTL_SYSDIV_3 0x01400000 // Processor clock is osc/pll /3\r
+#define SYSCTL_SYSDIV_4 0x01C00000 // Processor clock is osc/pll /4\r
+#define SYSCTL_SYSDIV_5 0x02400000 // Processor clock is osc/pll /5\r
+#define SYSCTL_SYSDIV_6 0x02C00000 // Processor clock is osc/pll /6\r
+#define SYSCTL_SYSDIV_7 0x03400000 // Processor clock is osc/pll /7\r
+#define SYSCTL_SYSDIV_8 0x03C00000 // Processor clock is osc/pll /8\r
+#define SYSCTL_SYSDIV_9 0x04400000 // Processor clock is osc/pll /9\r
+#define SYSCTL_SYSDIV_10 0x04C00000 // Processor clock is osc/pll /10\r
+#define SYSCTL_SYSDIV_11 0x05400000 // Processor clock is osc/pll /11\r
+#define SYSCTL_SYSDIV_12 0x05C00000 // Processor clock is osc/pll /12\r
+#define SYSCTL_SYSDIV_13 0x06400000 // Processor clock is osc/pll /13\r
+#define SYSCTL_SYSDIV_14 0x06C00000 // Processor clock is osc/pll /14\r
+#define SYSCTL_SYSDIV_15 0x07400000 // Processor clock is osc/pll /15\r
+#define SYSCTL_SYSDIV_16 0x07C00000 // Processor clock is osc/pll /16\r
+#define SYSCTL_USE_PLL 0x00000000 // System clock is the PLL clock\r
+#define SYSCTL_USE_OSC 0x00003800 // System clock is the osc clock\r
+#define SYSCTL_XTAL_3_57MHZ 0x00000100 // External crystal is 3.579545MHz\r
+#define SYSCTL_XTAL_3_68MHZ 0x00000140 // External crystal is 3.6864MHz\r
+#define SYSCTL_XTAL_4MHZ 0x00000180 // External crystal is 4MHz\r
+#define SYSCTL_XTAL_4_09MHZ 0x000001C0 // External crystal is 4.096MHz\r
+#define SYSCTL_XTAL_4_91MHZ 0x00000200 // External crystal is 4.9152MHz\r
+#define SYSCTL_XTAL_5MHZ 0x00000240 // External crystal is 5MHz\r
+#define SYSCTL_XTAL_5_12MHZ 0x00000280 // External crystal is 5.12MHz\r
+#define SYSCTL_XTAL_6MHZ 0x000002C0 // External crystal is 6MHz\r
+#define SYSCTL_XTAL_6_14MHZ 0x00000300 // External crystal is 6.144MHz\r
+#define SYSCTL_XTAL_7_37MHZ 0x00000340 // External crystal is 7.3728MHz\r
+#define SYSCTL_XTAL_8MHZ 0x00000380 // External crystal is 8MHz\r
+#define SYSCTL_XTAL_8_19MHZ 0x000003C0 // External crystal is 8.192MHz\r
+#define SYSCTL_OSC_MAIN 0x00000000 // Oscillator source is main osc\r
+#define SYSCTL_OSC_INT 0x00000010 // Oscillator source is int. osc\r
+#define SYSCTL_OSC_INT4 0x00000020 // Oscillator source is int. osc /4\r
+#define SYSCTL_INT_OSC_DIS 0x00000002 // Disable internal oscillator\r
+#define SYSCTL_MAIN_OSC_DIS 0x00000001 // Disable main oscillator\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+extern unsigned long SysCtlSRAMSizeGet(void);\r
+extern unsigned long SysCtlFlashSizeGet(void);\r
+extern tBoolean SysCtlPinPresent(unsigned long ulPin);\r
+extern tBoolean SysCtlPeripheralPresent(unsigned long ulPeripheral);\r
+extern void SysCtlPeripheralReset(unsigned long ulPeripheral);\r
+extern void SysCtlPeripheralEnable(unsigned long ulPeripheral);\r
+extern void SysCtlPeripheralDisable(unsigned long ulPeripheral);\r
+extern void SysCtlPeripheralSleepEnable(unsigned long ulPeripheral);\r
+extern void SysCtlPeripheralSleepDisable(unsigned long ulPeripheral);\r
+extern void SysCtlPeripheralDeepSleepEnable(unsigned long ulPeripheral);\r
+extern void SysCtlPeripheralDeepSleepDisable(unsigned long ulPeripheral);\r
+extern void SysCtlPeripheralClockGating(tBoolean bEnable);\r
+extern void SysCtlIntRegister(void (*pfnHandler)(void));\r
+extern void SysCtlIntUnregister(void);\r
+extern void SysCtlIntEnable(unsigned long ulInts);\r
+extern void SysCtlIntDisable(unsigned long ulInts);\r
+extern void SysCtlIntClear(unsigned long ulInts);\r
+extern unsigned long SysCtlIntStatus(tBoolean bMasked);\r
+extern void SysCtlLDOSet(unsigned long ulVoltage);\r
+extern unsigned long SysCtlLDOGet(void);\r
+extern void SysCtlLDOConfigSet(unsigned long ulConfig);\r
+extern void SysCtlReset(void);\r
+extern void SysCtlSleep(void);\r
+extern void SysCtlDeepSleep(void);\r
+extern unsigned long SysCtlResetCauseGet(void);\r
+extern void SysCtlResetCauseClear(unsigned long ulCauses);\r
+extern void SysCtlBrownOutConfigSet(unsigned long ulConfig,\r
+ unsigned long ulDelay);\r
+extern void SysCtlClockSet(unsigned long ulConfig);\r
+extern unsigned long SysCtlClockGet(void);\r
+extern void SysCtlPWMClockSet(unsigned long ulConfig);\r
+extern unsigned long SysCtlPWMClockGet(void);\r
+extern void SysCtlADCSpeedSet(unsigned long ulSpeed);\r
+extern unsigned long SysCtlADCSpeedGet(void);\r
+extern void SysCtlIOSCVerificationSet(tBoolean bEnable);\r
+extern void SysCtlMOSCVerificationSet(tBoolean bEnable);\r
+extern void SysCtlPLLVerificationSet(tBoolean bEnable);\r
+extern void SysCtlClkVerificationClear(void);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __SYSCTL_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// systick.h - Prototypes for the SysTick driver.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __SYSTICK_H__\r
+#define __SYSTICK_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+extern void SysTickEnable(void);\r
+extern void SysTickDisable(void);\r
+extern void SysTickIntRegister(void (*pfnHandler)(void));\r
+extern void SysTickIntUnregister(void);\r
+extern void SysTickIntEnable(void);\r
+extern void SysTickIntDisable(void);\r
+extern void SysTickPeriodSet(unsigned long ulPeriod);\r
+extern unsigned long SysTickPeriodGet(void);\r
+extern unsigned long SysTickValueGet(void);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __SYSTICK_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// uart.h - Defines and Macros for the UART.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __UART_H__\r
+#define __UART_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to UARTIntEnable, UARTIntDisable, and UARTIntClear\r
+// as the ulIntFlags parameter, and returned from UARTIntStatus.\r
+//\r
+//*****************************************************************************\r
+#define UART_INT_OE 0x400 // Overrun Error Interrupt Mask\r
+#define UART_INT_BE 0x200 // Break Error Interrupt Mask\r
+#define UART_INT_PE 0x100 // Parity Error Interrupt Mask\r
+#define UART_INT_FE 0x080 // Framing Error Interrupt Mask\r
+#define UART_INT_RT 0x040 // Receive Timeout Interrupt Mask\r
+#define UART_INT_TX 0x020 // Transmit Interrupt Mask\r
+#define UART_INT_RX 0x010 // Receive Interrupt Mask\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to UARTConfigSet as the ulConfig parameter and\r
+// returned by UARTConfigGet in the pulConfig parameter. Additionally, the\r
+// UART_CONFIG_PAR_* subset can be passed to UARTParityModeSet as the ulParity\r
+// parameter, and are returned by UARTParityModeGet.\r
+//\r
+//*****************************************************************************\r
+#define UART_CONFIG_WLEN_8 0x00000060 // 8 bit data\r
+#define UART_CONFIG_WLEN_7 0x00000040 // 7 bit data\r
+#define UART_CONFIG_WLEN_6 0x00000020 // 6 bit data\r
+#define UART_CONFIG_WLEN_5 0x00000000 // 5 bit data\r
+#define UART_CONFIG_STOP_ONE 0x00000000 // One stop bit\r
+#define UART_CONFIG_STOP_TWO 0x00000008 // Two stop bits\r
+#define UART_CONFIG_PAR_NONE 0x00000000 // No parity\r
+#define UART_CONFIG_PAR_EVEN 0x00000006 // Even parity\r
+#define UART_CONFIG_PAR_ODD 0x00000002 // Odd parity\r
+#define UART_CONFIG_PAR_ONE 0x00000086 // Parity bit is one\r
+#define UART_CONFIG_PAR_ZERO 0x00000082 // Parity bit is zero\r
+\r
+//*****************************************************************************\r
+//\r
+// API Function prototypes\r
+//\r
+//*****************************************************************************\r
+extern void UARTParityModeSet(unsigned long ulBase, unsigned long ulParity);\r
+extern unsigned long UARTParityModeGet(unsigned long ulBase);\r
+extern void UARTConfigSet(unsigned long ulBase, unsigned long ulBaud,\r
+ unsigned long ulConfig);\r
+extern void UARTConfigGet(unsigned long ulBase, unsigned long *pulBaud,\r
+ unsigned long *pulConfig);\r
+extern void UARTEnable(unsigned long ulBase);\r
+extern void UARTDisable(unsigned long ulBase);\r
+extern void UARTEnableSIR(unsigned long ulBase, tBoolean bLowPower);\r
+extern void UARTDisableSIR(unsigned long ulBase);\r
+extern tBoolean UARTCharsAvail(unsigned long ulBase);\r
+extern tBoolean UARTSpaceAvail(unsigned long ulBase);\r
+extern long UARTCharNonBlockingGet(unsigned long ulBase);\r
+extern long UARTCharGet(unsigned long ulBase);\r
+extern tBoolean UARTCharNonBlockingPut(unsigned long ulBase,\r
+ unsigned char ucData);\r
+extern void UARTCharPut(unsigned long ulBase, unsigned char ucData);\r
+extern void UARTBreakCtl(unsigned long ulBase, tBoolean bBreakState);\r
+extern void UARTIntRegister(unsigned long ulBase, void(*pfnHandler)(void));\r
+extern void UARTIntUnregister(unsigned long ulBase);\r
+extern void UARTIntEnable(unsigned long ulBase, unsigned long ulIntFlags);\r
+extern void UARTIntDisable(unsigned long ulBase, unsigned long ulIntFlags);\r
+extern unsigned long UARTIntStatus(unsigned long ulBase, tBoolean bMasked);\r
+extern void UARTIntClear(unsigned long ulBase, unsigned long ulIntFlags);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __UART_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// ustdlib.c - Simple standard library functions.\r
+//\r
+// Copyright (c) 2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+//*****************************************************************************\r
+\r
+#include <stdarg.h>\r
+#include <string.h>\r
+#include "debug.h"\r
+\r
+//*****************************************************************************\r
+//\r
+//! \addtogroup utilities_api\r
+//! @{\r
+//\r
+//*****************************************************************************\r
+\r
+//*****************************************************************************\r
+//\r
+// A mapping from an integer between 0 and 15 to its ASCII character\r
+// equivalent.\r
+//\r
+//*****************************************************************************\r
+static const char * const g_pcHex = "0123456789abcdef";\r
+\r
+//*****************************************************************************\r
+//\r
+//! A simple sprintf function supporting \%c, \%d, \%s, \%u, \%x, and \%X.\r
+//!\r
+//! \param pcBuf is the buffer where the converted string is stored.\r
+//! \param pcString is the format string.\r
+//! \param ... are the optional arguments, which depend on the contents of the\r
+//! format string.\r
+//!\r
+//! This function is very similar to the C library <tt>sprintf()</tt> function.\r
+//! Only the following formatting characters are supported:\r
+//!\r
+//! - \%c to print a character\r
+//! - \%d to print a decimal value\r
+//! - \%s to print a string\r
+//! - \%u to print an unsigned decimal value\r
+//! - \%x to print a hexadecimal value using lower case letters\r
+//! - \%X to print a hexadecimal value using lower case letters (not upper case\r
+//! letters as would typically be used)\r
+//! - \%\% to print out a \% character\r
+//!\r
+//! For \%d, \%u, \%x, and \%X, an optional number may reside between the \%\r
+//! and the format character, which specifies the minimum number of characters\r
+//! to use for that value; if preceeded by a 0 then the extra characters will\r
+//! be filled with zeros instead of spaces. For example, ``\%8d'' will use\r
+//! eight characters to print the decimal value with spaces added to reach\r
+//! eight; ``\%08d'' will use eight characters as well but will add zeros\r
+//! instead of spaces.\r
+//!\r
+//! The type of the arguments after \b pcString must match the requirements of\r
+//! the format string. For example, if an integer was passed where a string\r
+//! was expected, an error of some kind will most likely occur.\r
+//!\r
+//! The caller must ensure that the buffer pcBuf is large enough to hold the\r
+//! entire converted string, including the null termination character.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+void\r
+usprintf(char *pcBuf, const char *pcString, ...)\r
+{\r
+ unsigned long ulIdx, ulValue, ulPos, ulCount, ulBase;\r
+ char *pcStr, cFill;\r
+ va_list vaArgP;\r
+\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT(pcString != 0);\r
+ ASSERT(pcBuf != 0);\r
+\r
+ //\r
+ // Start the varargs processing.\r
+ //\r
+ va_start(vaArgP, pcString);\r
+\r
+ //\r
+ // Loop while there are more characters in the string.\r
+ //\r
+ while(*pcString)\r
+ {\r
+ //\r
+ // Find the first non-% character, or the end of the string.\r
+ //\r
+ for(ulIdx = 0; (pcString[ulIdx] != '%') && (pcString[ulIdx] != '\0');\r
+ ulIdx++)\r
+ {\r
+ }\r
+\r
+ //\r
+ // Write this portion of the string.\r
+ //\r
+ strncpy(pcBuf, pcString, ulIdx);\r
+\r
+ //\r
+ // Skip the portion of the string that was written.\r
+ //\r
+ pcString += ulIdx;\r
+ pcBuf += ulIdx;\r
+\r
+ //\r
+ // See if the next character is a %.\r
+ //\r
+ if(*pcString == '%')\r
+ {\r
+ //\r
+ // Skip the %.\r
+ //\r
+ pcString++;\r
+\r
+ //\r
+ // Set the digit count to zero, and the fill character to space\r
+ // (i.e. to the defaults).\r
+ //\r
+ ulCount = 0;\r
+ cFill = ' ';\r
+\r
+ //\r
+ // It may be necessary to get back here to process more characters.\r
+ // Goto's aren't pretty, but effective. I feel extremely dirty for\r
+ // using not one but two of the beasts.\r
+ //\r
+again:\r
+\r
+ //\r
+ // Determine how to handle the next character.\r
+ //\r
+ switch(*pcString++)\r
+ {\r
+ //\r
+ // Handle the digit characters.\r
+ //\r
+ case '0':\r
+ case '1':\r
+ case '2':\r
+ case '3':\r
+ case '4':\r
+ case '5':\r
+ case '6':\r
+ case '7':\r
+ case '8':\r
+ case '9':\r
+ {\r
+ //\r
+ // If this is a zero, and it is the first digit, then the\r
+ // fill character is a zero instead of a space.\r
+ //\r
+ if((pcString[-1] == '0') && (ulCount == 0))\r
+ {\r
+ cFill = '0';\r
+ }\r
+\r
+ //\r
+ // Update the digit count.\r
+ //\r
+ ulCount *= 10;\r
+ ulCount += pcString[-1] - '0';\r
+\r
+ //\r
+ // Get the next character.\r
+ //\r
+ goto again;\r
+ }\r
+\r
+ //\r
+ // Handle the %c command.\r
+ //\r
+ case 'c':\r
+ {\r
+ //\r
+ // Get the value from the varargs.\r
+ //\r
+ ulValue = va_arg(vaArgP, unsigned long);\r
+\r
+ //\r
+ // Print out the character.\r
+ //\r
+ *pcBuf++ = (char)ulValue;\r
+\r
+ //\r
+ // This command has been handled.\r
+ //\r
+ break;\r
+ }\r
+\r
+ //\r
+ // Handle the %d command.\r
+ //\r
+ case 'd':\r
+ {\r
+ //\r
+ // Get the value from the varargs.\r
+ //\r
+ ulValue = va_arg(vaArgP, unsigned long);\r
+\r
+ //\r
+ // Reset the buffer position.\r
+ //\r
+ ulPos = 0;\r
+\r
+ //\r
+ // If the value is negative, make it positive and stick a\r
+ // minus sign in the beginning of the buffer.\r
+ //\r
+ if((long)ulValue < 0)\r
+ {\r
+ *pcBuf++ = '-';\r
+ ulPos++;\r
+ ulValue = -(long)ulValue;\r
+ }\r
+\r
+ //\r
+ // Set the base to 10.\r
+ //\r
+ ulBase = 10;\r
+\r
+ //\r
+ // Convert the value to ASCII.\r
+ //\r
+ goto convert;\r
+ }\r
+\r
+ //\r
+ // Handle the %s command.\r
+ //\r
+ case 's':\r
+ {\r
+ //\r
+ // Get the string pointer from the varargs.\r
+ //\r
+ pcStr = va_arg(vaArgP, char *);\r
+\r
+ //\r
+ // Determine the length of the string.\r
+ //\r
+ for(ulIdx = 0; pcStr[ulIdx] != '\0'; ulIdx++)\r
+ {\r
+ }\r
+\r
+ //\r
+ // Write the string.\r
+ //\r
+ strncpy(pcBuf, pcStr, ulIdx);\r
+ pcBuf += ulIdx;\r
+\r
+ //\r
+ // This command has been handled.\r
+ //\r
+ break;\r
+ }\r
+\r
+ //\r
+ // Handle the %u command.\r
+ //\r
+ case 'u':\r
+ {\r
+ //\r
+ // Get the value from the varargs.\r
+ //\r
+ ulValue = va_arg(vaArgP, unsigned long);\r
+\r
+ //\r
+ // Reset the buffer position.\r
+ //\r
+ ulPos = 0;\r
+\r
+ //\r
+ // Set the base to 10.\r
+ //\r
+ ulBase = 10;\r
+\r
+ //\r
+ // Convert the value to ASCII.\r
+ //\r
+ goto convert;\r
+ }\r
+\r
+ //\r
+ // Handle the %x and %X commands. Note that they are treated\r
+ // identically; i.e. %X will use lower case letters for a-f\r
+ // instead of the upper case letters is should use.\r
+ //\r
+ case 'x':\r
+ case 'X':\r
+ {\r
+ //\r
+ // Get the value from the varargs.\r
+ //\r
+ ulValue = va_arg(vaArgP, unsigned long);\r
+\r
+ //\r
+ // Reset the buffer position.\r
+ //\r
+ ulPos = 0;\r
+\r
+ //\r
+ // Set the base to 16.\r
+ //\r
+ ulBase = 16;\r
+\r
+ //\r
+ // Determine the number of digits in the string version of\r
+ // the value.\r
+ //\r
+convert:\r
+ for(ulIdx = 1;\r
+ (((ulIdx * ulBase) <= ulValue) &&\r
+ (((ulIdx * ulBase) / ulBase) == ulIdx));\r
+ ulIdx *= ulBase, ulCount--)\r
+ {\r
+ }\r
+\r
+ //\r
+ // Provide additional padding at the beginning of the\r
+ // string conversion if needed.\r
+ //\r
+ if((ulCount > 1) && (ulCount < 16))\r
+ {\r
+ for(ulCount--; ulCount; ulCount--)\r
+ {\r
+ *pcBuf++ = cFill;\r
+ ulPos++;\r
+ }\r
+ }\r
+\r
+ //\r
+ // Convert the value into a string.\r
+ //\r
+ for(; ulIdx; ulIdx /= ulBase)\r
+ {\r
+ *pcBuf++ = g_pcHex[(ulValue / ulIdx) % ulBase];\r
+ ulPos++;\r
+ }\r
+\r
+ //\r
+ // This command has been handled.\r
+ //\r
+ break;\r
+ }\r
+\r
+ //\r
+ // Handle the %% command.\r
+ //\r
+ case '%':\r
+ {\r
+ //\r
+ // Simply write a single %.\r
+ //\r
+ *pcBuf++ = pcString[-1];\r
+\r
+ //\r
+ // This command has been handled.\r
+ //\r
+ break;\r
+ }\r
+\r
+ //\r
+ // Handle all other commands.\r
+ //\r
+ default:\r
+ {\r
+ //\r
+ // Indicate an error.\r
+ //\r
+ strncpy(pcBuf, "ERROR", 5);\r
+ pcBuf += 5;\r
+\r
+ //\r
+ // This command has been handled.\r
+ //\r
+ break;\r
+ }\r
+ }\r
+ }\r
+ }\r
+\r
+ //\r
+ // End the varargs processing.\r
+ //\r
+ va_end(vaArgP);\r
+\r
+ //\r
+ // Null terminate the string in the buffer.\r
+ //\r
+ *pcBuf = 0;\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+// Close the Doxygen group.\r
+//! @}\r
+//\r
+//*****************************************************************************\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// uartstdlib.h - Prototypes for simple standard library functions.\r
+//\r
+// Copyright (c) 2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __UARTSTDLIB_H__\r
+#define __UARTSTDLIB_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+extern void usprintf(char *, const char *pcString, ...);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __UARTSTDLIB_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// watchdog.h - Prototypes for the Watchdog Timer API\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __WATCHDOG_H__\r
+#define __WATCHDOG_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+extern tBoolean WatchdogRunning(unsigned long ulBase);\r
+extern void WatchdogEnable(unsigned long ulBase);\r
+extern void WatchdogResetEnable(unsigned long ulBase);\r
+extern void WatchdogResetDisable(unsigned long ulBase);\r
+extern void WatchdogLock(unsigned long ulBase);\r
+extern void WatchdogUnlock(unsigned long ulBase);\r
+extern tBoolean WatchdogLockState(unsigned long ulBase);\r
+extern void WatchdogReloadSet(unsigned long ulBase, unsigned long ulLoadVal);\r
+extern unsigned long WatchdogReloadGet(unsigned long ulBase);\r
+extern unsigned long WatchdogValueGet(unsigned long ulBase);\r
+extern void WatchdogIntRegister(unsigned long ulBase, void(*pfnHandler)(void));\r
+extern void WatchdogIntUnregister(unsigned long ulBase);\r
+extern void WatchdogIntEnable(unsigned long ulBase);\r
+extern unsigned long WatchdogIntStatus(unsigned long ulBase, tBoolean bMasked);\r
+extern void WatchdogIntClear(unsigned long ulBase);\r
+extern void WatchdogStallDisable(unsigned long ulBase);\r
+extern void WatchdogStallDisable(unsigned long ulBase);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __WATCHDOG_H__\r
--- /dev/null
+#******************************************************************************
+#
+# Makefile - Rules for building the driver library and examples.
+#
+# Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
+#
+# Software License Agreement
+#
+# Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+# exclusively on LMI's Stellaris Family of microcontroller products.
+#
+# The software is owned by LMI and/or its suppliers, and is protected under
+# applicable copyright laws. All rights are reserved. Any use in violation
+# of the foregoing restrictions may subject the user to criminal sanctions
+# under applicable laws, as well as to civil liability for the breach of the
+# terms and conditions of this license.
+#
+# THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+# OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+# MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+# LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+# CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+#
+#******************************************************************************
+
+include makedefs
+
+RTOS_SOURCE_DIR=../../Source
+DEMO_SOURCE_DIR=../Common/Minimal
+
+CFLAGS+=-I LuminaryDrivers -I . -I ${RTOS_SOURCE_DIR}/include -I ${RTOS_SOURCE_DIR}/portable/GCC/ARM_CM3 -I ../Common/include -D GCC_ARMCM3_LM3S102 -D inline= -D sprintf=usprintf
+
+VPATH=${RTOS_SOURCE_DIR}:${RTOS_SOURCE_DIR}/portable/MemMang:${RTOS_SOURCE_DIR}/portable/GCC/ARM_CM3:${DEMO_SOURCE_DIR}:LuminaryDrivers:ParTest
+
+OBJS=${COMPILER}/main.o \
+ ${COMPILER}/list.o \
+ ${COMPILER}/queue.o \
+ ${COMPILER}/tasks.o \
+ ${COMPILER}/port.o \
+ ${COMPILER}/heap_2.o \
+ ${COMPILER}/BlockQ.o \
+ ${COMPILER}/PollQ.o \
+ ${COMPILER}/integer.o \
+ ${COMPILER}/semtest.o \
+ ${COMPILER}/osram128x64x4.o \
+ ${COMPILER}/blocktim.o \
+ ${COMPILER}/death.o \
+ ${COMPILER}/ParTest.o \
+ ${COMPILER}/timertest.o \
+ ${COMPILER}/ustdlib.o
+
+INIT_OBJS= ${COMPILER}/startup.o
+
+LIBS= LuminaryDrivers/libdriver.a
+
+
+#
+# The default rule, which causes init to be built.
+#
+all: ${COMPILER} \
+ ${COMPILER}/RTOSDemo.axf \
+
+#
+# The rule to clean out all the build products
+#
+
+clean:
+ @rm -rf ${COMPILER} ${wildcard *.bin} RTOSDemo.axf
+
+#
+# The rule to create the target directory
+#
+${COMPILER}:
+ @mkdir ${COMPILER}
+
+${COMPILER}/RTOSDemo.axf: ${INIT_OBJS} ${OBJS} ${LIBS}
+SCATTER_RTOSDemo=standalone.ld
+ENTRY_RTOSDemo=ResetISR
+
+#
+#
+# Include the automatically generated dependency files.
+#
+-include ${wildcard ${COMPILER}/*.d} __dummy__
+
--- /dev/null
+/*\r
+ FreeRTOS.org V4.3.0 - Copyright (C) 2003-2007 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS.org distribution.\r
+\r
+ FreeRTOS.org is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS.org is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS.org; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS.org, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section\r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license\r
+ and contact details. Please ensure to read the configuration and relevant\r
+ port sections of the online documentation.\r
+\r
+ Also see http://www.SafeRTOS.com for an IEC 61508 compliant version along\r
+ with commercial development and support options.\r
+ ***************************************************************************\r
+*/\r
+\r
+/*-----------------------------------------------------------\r
+ * Simple parallel port IO routines.\r
+ *-----------------------------------------------------------*/\r
+\r
+/*\r
+*/\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/* Demo includes. */\r
+#include "partest.h"\r
+\r
+/* Library includes. */\r
+#include "hw_types.h"\r
+#include "gpio.h"\r
+#include "hw_memmap.h"\r
+\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestInitialise( void )\r
+{\r
+ GPIODirModeSet( GPIO_PORTF_BASE, GPIO_PIN_0, GPIO_DIR_MODE_OUT );\r
+ GPIOPadConfigSet( GPIO_PORTF_BASE, GPIO_PIN_0, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD );\r
+ GPIOPinWrite( GPIO_PORTF_BASE, GPIO_PIN_0, 0 );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue )\r
+{\r
+ /* There is only one LED. */\r
+ ( void ) uxLED;\r
+ \r
+ GPIOPinWrite( GPIO_PORTF_BASE, GPIO_PIN_0, xValue );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+unsigned portBASE_TYPE uxParTestGetLED( unsigned portBASE_TYPE uxLED )\r
+{\r
+ /* There is only one LED. */\r
+ ( void ) uxLED;\r
+\r
+ return GPIOPinRead( GPIO_PORTF_BASE, GPIO_PIN_0 ); \r
+}\r
+\r
+\r
--- /dev/null
+#ifndef BITMAP_H\r
+#define BITMAP_H\r
+\r
+const unsigned char pucImage[] =\r
+{\r
+0x00, 0x0a, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,\r
+0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,\r
+0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,\r
+0xaa, 0xaa, 0xaa, 0x00, 0x0a, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,\r
+0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,\r
+0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,\r
+0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xa0, 0x0a, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,\r
+0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,\r
+0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,\r
+0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xaa, 0xaa, 0xaa, 0xaf, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfa, 0xaa,\r
+0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf7,\r
+0x00, 0x8f, 0xff, 0xff, 0xf8, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0xff, 0xff, 0xff, 0xff, 0xf8, 0x88, 0x88, 0x88,\r
+0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x8f, 0xff, 0xff, 0xff, 0xff, 0xff, 0x88, 0x77, 0x77, 0x78, 0x8f, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xf8, 0x88, 0x77, 0x77, 0x88, 0x8f, 0xff, 0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff,\r
+0xff, 0xff, 0xf0, 0x00, 0x00, 0x8f, 0x00, 0xff, 0x87, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x78, 0xff, 0xff,\r
+0xf7, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x78, 0xff, 0xff, 0xff, 0x87, 0x77, 0x77, 0x77, 0x77, 0x77,\r
+0x77, 0x77, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x7f, 0xff, 0xff, 0xfa, 0xaa,\r
+0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0x70, 0x00, 0x00, 0x8f, 0x00, 0xff, 0x87, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77,\r
+0x77, 0x77, 0xff, 0xff, 0xf7, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x78, 0xff, 0xff, 0xf8, 0x77, 0x77,\r
+0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x78, 0xff, 0xff, 0xff, 0xff, 0x87, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x8f,\r
+0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0x70, 0x08, 0x00, 0x8f, 0x00, 0xff, 0x87, 0x77, 0x77, 0x77,\r
+0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x8f, 0xff, 0xf7, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x78, 0xff,\r
+0xff, 0x87, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x8f, 0xff, 0xff, 0xf8, 0x77, 0x77, 0x77, 0x77, 0x77,\r
+0x77, 0x77, 0x77, 0x8f, 0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0x00, 0x0f, 0x00, 0x8f, 0x00, 0xff,\r
+0x87, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x78, 0xff, 0xf7, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77,\r
+0x77, 0x77, 0x78, 0xff, 0xf8, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x78, 0xff, 0xff, 0xf8, 0x77,\r
+0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x8f, 0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0x70, 0x07,\r
+0x00, 0x70, 0x00, 0xff, 0x87, 0x77, 0x77, 0x77, 0xff, 0xff, 0xf8, 0x77, 0x77, 0x77, 0x77, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0x77, 0x77, 0x77, 0x7f, 0xff, 0xff, 0xff, 0xff, 0x87, 0x77, 0x77, 0x77, 0x78, 0xff, 0xff, 0xf8, 0x77, 0x77, 0x77, 0x77,\r
+0xff, 0xff, 0x87, 0x77, 0x77, 0x77, 0x8f, 0xff, 0xff, 0xff, 0x88, 0x8f, 0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff,\r
+0xff, 0xff, 0x80, 0x00, 0x00, 0x00, 0x07, 0xff, 0x87, 0x77, 0x77, 0x77, 0xff, 0xff, 0xff, 0x87, 0x77, 0x77, 0x77, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0x77, 0x77, 0x77, 0x7f, 0xff, 0xff, 0xff, 0xff, 0x77, 0x77, 0x77, 0x77, 0xff, 0xff, 0xff, 0xff,\r
+0x87, 0x77, 0x77, 0x77, 0xff, 0xff, 0x77, 0x77, 0x77, 0x77, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfa, 0xaa,\r
+0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0xf7, 0x00, 0x00, 0x00, 0x0f, 0xff, 0x87, 0x77, 0x77, 0x77, 0xff, 0xff, 0xff, 0xf8,\r
+0x77, 0x77, 0x77, 0xff, 0xff, 0xff, 0xff, 0xff, 0x77, 0x77, 0x77, 0x7f, 0xff, 0xff, 0xff, 0xff, 0x77, 0x77, 0x77, 0x77,\r
+0xff, 0xff, 0xff, 0xff, 0xf7, 0x77, 0x77, 0x77, 0x8f, 0xff, 0x77, 0x77, 0x77, 0x77, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0xff, 0x70, 0x00, 0x00, 0xff, 0xff, 0x87, 0x77, 0x77, 0x77,\r
+0xff, 0xff, 0xff, 0xf8, 0x77, 0x77, 0x77, 0xff, 0xff, 0xff, 0xff, 0xff, 0x77, 0x77, 0x77, 0x7f, 0xff, 0xff, 0xff, 0xff,\r
+0x77, 0x77, 0x77, 0x78, 0xff, 0xff, 0xff, 0xff, 0xf8, 0x77, 0x77, 0x77, 0x8f, 0xff, 0x77, 0x77, 0x77, 0x77, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0x87, 0x77, 0x77, 0x77, 0xff, 0xff, 0xff, 0xf7, 0x77, 0x77, 0x78, 0xff, 0xff, 0xff, 0xff, 0xff, 0x77, 0x77, 0x77, 0x7f,\r
+0xff, 0xff, 0xff, 0xf8, 0x77, 0x77, 0x77, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xff, 0x87, 0x77, 0x77, 0x78, 0xff, 0x87, 0x77,\r
+0x77, 0x77, 0x78, 0x8f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0x88, 0xff, 0xff, 0xff, 0x87, 0x77, 0x77, 0x77, 0xff, 0xff, 0xf8, 0x87, 0x77, 0x77, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0x77, 0x77, 0x77, 0x7f, 0xff, 0xff, 0xff, 0xf8, 0x77, 0x77, 0x77, 0x8f, 0xff, 0xff, 0xff, 0xff, 0xff, 0x87, 0x77, 0x77,\r
+0x78, 0xff, 0x87, 0x77, 0x77, 0x77, 0x77, 0x77, 0x8f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0x80, 0x00, 0x8f, 0x8f, 0xff, 0x87, 0x77, 0x77, 0x77, 0x88, 0x88, 0x77, 0x77, 0x77, 0x77, 0x8f, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0x77, 0x77, 0x77, 0x7f, 0xff, 0xff, 0xff, 0xf8, 0x77, 0x77, 0x77, 0x8f, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0x87, 0x77, 0x77, 0x78, 0xff, 0xf7, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x88, 0xff, 0xff, 0xff, 0xff, 0xfa, 0xaa,\r
+0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0xf7, 0x00, 0x00, 0x8f, 0x07, 0xff, 0x87, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77,\r
+0x77, 0x77, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x77, 0x77, 0x77, 0x7f, 0xff, 0xff, 0xff, 0xf8, 0x77, 0x77, 0x77, 0x8f,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0x87, 0x77, 0x77, 0x78, 0xff, 0xf8, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x8f, 0xff,\r
+0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0x70, 0x07, 0x00, 0x8f, 0x00, 0xff, 0x87, 0x77, 0x77, 0x77,\r
+0x77, 0x77, 0x77, 0x77, 0x88, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x77, 0x77, 0x77, 0x7f, 0xff, 0xff, 0xff, 0xf8,\r
+0x77, 0x77, 0x77, 0x8f, 0xff, 0xff, 0xff, 0xff, 0xff, 0x87, 0x77, 0x77, 0x78, 0xff, 0xff, 0xf8, 0x77, 0x77, 0x77, 0x77,\r
+0x77, 0x77, 0x77, 0x8f, 0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0x70, 0x0f, 0x00, 0x8f, 0x00, 0xff,\r
+0x87, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x8f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x77, 0x77, 0x77, 0x7f,\r
+0xff, 0xff, 0xff, 0xf8, 0x77, 0x77, 0x77, 0x8f, 0xff, 0xff, 0xff, 0xff, 0xff, 0x87, 0x77, 0x77, 0x78, 0xff, 0xff, 0xff,\r
+0x87, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x78, 0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0x00, 0x0f,\r
+0x00, 0x8f, 0x00, 0xff, 0x87, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x78, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0x77, 0x77, 0x77, 0x7f, 0xff, 0xff, 0xff, 0xf8, 0x77, 0x77, 0x77, 0x8f, 0xff, 0xff, 0xff, 0xff, 0xff, 0x87, 0x77, 0x77,\r
+0x78, 0xff, 0xff, 0xff, 0xff, 0x88, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff,\r
+0xff, 0xff, 0x70, 0x08, 0x00, 0x88, 0x00, 0xff, 0x87, 0x77, 0x77, 0x77, 0x88, 0x88, 0x77, 0x77, 0x77, 0x78, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0x77, 0x77, 0x77, 0x7f, 0xff, 0xff, 0xff, 0xf8, 0x77, 0x77, 0x77, 0x8f, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0x87, 0x77, 0x77, 0x78, 0xff, 0xff, 0xff, 0xff, 0xff, 0x88, 0x77, 0x77, 0x77, 0x77, 0x77, 0xff, 0xff, 0xfa, 0xaa,\r
+0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0x70, 0x00, 0x00, 0x70, 0x07, 0xff, 0x87, 0x77, 0x77, 0x77, 0xff, 0xff, 0x77, 0x77,\r
+0x77, 0x77, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x77, 0x77, 0x77, 0x7f, 0xff, 0xff, 0xff, 0xf8, 0x77, 0x77, 0x77, 0x7f,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0x87, 0x77, 0x77, 0x78, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf8, 0x77, 0x77, 0x77, 0x77,\r
+0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0xf8, 0x00, 0x00, 0x00, 0x7f, 0xff, 0x87, 0x77, 0x77, 0x77,\r
+0xff, 0xff, 0xf7, 0x77, 0x77, 0x77, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x77, 0x77, 0x77, 0x7f, 0xff, 0xff, 0xff, 0xff,\r
+0x77, 0x77, 0x77, 0x78, 0xff, 0xff, 0xff, 0xff, 0xf8, 0x77, 0x77, 0x77, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0x87, 0x77, 0x77, 0x77, 0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0xff, 0x80, 0x00, 0x00, 0xff, 0xff,\r
+0x87, 0x77, 0x77, 0x77, 0xff, 0xff, 0xf8, 0x77, 0x77, 0x77, 0x8f, 0xff, 0xff, 0xff, 0xff, 0xff, 0x77, 0x77, 0x77, 0x7f,\r
+0xff, 0xff, 0xff, 0xff, 0x77, 0x77, 0x77, 0x77, 0xff, 0xff, 0xff, 0xff, 0xf7, 0x77, 0x77, 0x77, 0x8f, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0x87, 0x77, 0x77, 0x77, 0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0x87, 0x88,\r
+0x88, 0x8f, 0xff, 0xff, 0x87, 0x77, 0x77, 0x77, 0xff, 0xff, 0xff, 0x77, 0x77, 0x77, 0x8f, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0x77, 0x77, 0x77, 0x7f, 0xff, 0xff, 0xff, 0xff, 0x77, 0x77, 0x77, 0x77, 0xff, 0xff, 0xff, 0xff, 0x87, 0x77, 0x77, 0x77,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x87, 0x77, 0x77, 0x77, 0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff,\r
+0xff, 0xff, 0x00, 0x07, 0xff, 0xff, 0xff, 0xff, 0x87, 0x77, 0x77, 0x77, 0xff, 0xff, 0xff, 0x87, 0x77, 0x77, 0x7f, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0x77, 0x77, 0x77, 0x7f, 0xff, 0xff, 0xff, 0xff, 0x87, 0x77, 0x77, 0x77, 0x8f, 0xff, 0xff, 0xff,\r
+0x77, 0x77, 0x77, 0x77, 0xff, 0xff, 0xf7, 0x88, 0xff, 0xff, 0xff, 0xff, 0x87, 0x77, 0x77, 0x77, 0xff, 0xff, 0xfa, 0xaa,\r
+0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0x80, 0x00, 0xff, 0xff, 0xff, 0xff, 0x87, 0x77, 0x77, 0x77, 0xff, 0xff, 0xff, 0xf7,\r
+0x77, 0x77, 0x78, 0xff, 0xff, 0xff, 0xff, 0xff, 0x77, 0x77, 0x77, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xf8, 0x77, 0x77, 0x77,\r
+0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x78, 0xff, 0xff, 0x87, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x78,\r
+0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0xf7, 0x00, 0x88, 0x88, 0x88, 0xff, 0x87, 0x77, 0x77, 0x77,\r
+0xff, 0xff, 0xff, 0xf8, 0x77, 0x77, 0x77, 0xff, 0xff, 0xff, 0xff, 0xff, 0x77, 0x77, 0x77, 0x7f, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0x87, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x8f, 0xff, 0xff, 0x87, 0x77, 0x77, 0x77, 0x77, 0x77,\r
+0x77, 0x77, 0x77, 0x7f, 0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0x70, 0x00, 0x00, 0x00, 0x00, 0xff,\r
+0x87, 0x77, 0x77, 0x77, 0xff, 0xff, 0xff, 0xf8, 0x77, 0x77, 0x77, 0x8f, 0xff, 0xff, 0xff, 0xff, 0x77, 0x77, 0x77, 0x7f,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xf8, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x78, 0xff, 0xff, 0xff, 0x87, 0x77,\r
+0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0xff, 0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0x70, 0x00,\r
+0x00, 0x00, 0x00, 0xff, 0x87, 0x77, 0x77, 0x77, 0xff, 0xff, 0xff, 0xff, 0x77, 0x77, 0x77, 0x7f, 0xff, 0xff, 0xff, 0xff,\r
+0x77, 0x77, 0x77, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x87, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x8f, 0xff,\r
+0xff, 0xff, 0x87, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x8f, 0xff, 0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff,\r
+0xff, 0xff, 0x70, 0x00, 0x00, 0x00, 0x07, 0xff, 0x88, 0x88, 0x88, 0x88, 0xff, 0xff, 0xff, 0xff, 0x88, 0x88, 0x88, 0x88,\r
+0xff, 0xff, 0xff, 0xff, 0x88, 0x88, 0x88, 0x8f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf8, 0x87, 0x77, 0x77, 0x77,\r
+0x88, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x88, 0x77, 0x77, 0x77, 0x77, 0x88, 0x8f, 0xff, 0xff, 0xff, 0xff, 0xfa, 0xaa,\r
+0xaa, 0xaf, 0xff, 0xff, 0x00, 0x0f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff, 0x00, 0x0f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff, 0x00, 0x0f, 0x70, 0x08, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff, 0x00, 0x07, 0x70, 0x07,\r
+0x88, 0x88, 0x88, 0xff, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88,\r
+0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88,\r
+0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff,\r
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xfa, 0xaa,\r
+0xaa, 0xaf, 0xff, 0xff, 0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r
+0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff, 0xf7, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x70, 0x00, 0x00, 0x00,\r
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r
+0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0x70, 0x08, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0x70, 0x08,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfa, 0xaa,\r
+0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaa, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,\r
+0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,\r
+0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,\r
+0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x0a, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,\r
+0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,\r
+0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,\r
+0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xa0, 0x00, 0xaa, 0xaa, 0xaa,\r
+0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,\r
+0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,\r
+0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x00,\r
+0x00 };\r
+\r
+#define bmpBITMAP_HEIGHT 50\r
+#define bmpBITMAP_WIDTH 128\r
+\r
+#endif\r
--- /dev/null
+#ifndef LCD_MESSAGE_H\r
+#define LCD_MESSAGE_H\r
+\r
+typedef struct\r
+{\r
+ char *pcMessage;\r
+} xOLEDMessage;\r
+\r
+#endif /* LCD_MESSAGE_H */\r
--- /dev/null
+/*\r
+ FreeRTOS.org V4.3.0 - Copyright (C) 2003-2007 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS.org distribution.\r
+\r
+ FreeRTOS.org is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS.org is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS.org; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS.org, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section\r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license\r
+ and contact details. Please ensure to read the configuration and relevant\r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+\r
+/*\r
+ * Creates all the demo application tasks, then starts the scheduler. The WEB\r
+ * documentation provides more details of the standard demo application tasks.\r
+ * In addition to the standard demo tasks, the following tasks and tests are\r
+ * defined and/or created within this file:\r
+ *\r
+ * "Fast Interrupt Test" - A high frequency periodic interrupt is generated\r
+ * using a free running timer to demonstrate the use of the\r
+ * configKERNEL_INTERRUPT_PRIORITY configuration constant. The interrupt\r
+ * service routine measures the number of processor clocks that occur between\r
+ * each interrupt - and in so doing measures the jitter in the interrupt timing.\r
+ * The maximum measured jitter time is latched in the ulMaxJitter variable, and\r
+ * displayed on the OLED display by the 'Check' task as described below. The\r
+ * fast interrupt is configured and handled in the timertest.c source file.\r
+ *\r
+ * "OLED" task - the OLED task is a 'gatekeeper' task. It is the only task that\r
+ * is permitted to access the display directly. Other tasks wishing to write a\r
+ * message to the OLED send the message on a queue to the OLED task instead of\r
+ * accessing the OLED themselves. The OLED task just blocks on the queue waiting\r
+ * for messages - waking and displaying the messages as they arrive.\r
+ *\r
+ * "Check" task - This only executes every five seconds but has the highest\r
+ * priority so is guaranteed to get processor time. Its main function is to\r
+ * check that all the standard demo tasks are still operational. Should any\r
+ * unexpected behaviour within a demo task be discovered the 'check' task will\r
+ * write an error to the OLED (via the OLED task). If all the demo tasks are\r
+ * executing with their expected behaviour then the check task writes PASS\r
+ * along with the max jitter time to the OLED (again via the OLED task), as\r
+ * described above.\r
+ *\r
+ */\r
+\r
+\r
+\r
+/* Standard includes. */\r
+#include <stdio.h>\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "Task.h"\r
+#include "queue.h"\r
+#include "semphr.h"\r
+\r
+/* Demo app includes. */\r
+#include "BlockQ.h"\r
+#include "death.h"\r
+#include "integer.h"\r
+#include "blocktim.h"\r
+#include "flash.h"\r
+#include "partest.h"\r
+#include "semtest.h"\r
+#include "pollq.h"\r
+#include "lcd_message.h"\r
+#include "bitmap.h"\r
+\r
+/* Hardware library includes. */\r
+#include "hw_memmap.h"\r
+#include "hw_types.h"\r
+#include "sysctl.h"\r
+#include "gpio.h"\r
+#include "osram128x64x4.h"\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* The time between cycles of the 'check' task. */\r
+#define mainCHECK_DELAY ( ( portTickType ) 5000 / portTICK_RATE_MS )\r
+\r
+/* The check task uses the sprintf function so requires a little more stack too. */\r
+#define mainCHECK_TASK_STACK_SIZE ( configMINIMAL_STACK_SIZE + 50 )\r
+\r
+/* Task priorities. */\r
+#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
+#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 )\r
+#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 )\r
+#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
+#define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 )\r
+#define mainINTEGER_TASK_PRIORITY ( tskIDLE_PRIORITY )\r
+\r
+/* The maximum number of message that can be waiting for display at any one\r
+time. */\r
+#define mainOLED_QUEUE_SIZE ( 3 )\r
+\r
+/* Dimensions the buffer into which the jitter time is written. */\r
+#define mainMAX_MSG_LEN 25\r
+\r
+/* The period of the system clock in nano seconds. This is used to calculate\r
+the jitter time in nano seconds. */\r
+#define mainNS_PER_CLOCK ( ( unsigned portLONG ) ( ( 1.0 / ( double ) configCPU_CLOCK_HZ ) * 1000000000.0 ) )\r
+\r
+/* Constants used when writing strings to the display. */\r
+#define mainCHARACTER_HEIGHT ( 9 )\r
+#define mainMAX_ROWS ( mainCHARACTER_HEIGHT * 7 )\r
+#define mainFULL_SCALE ( 15 )\r
+#define ulSSI_FREQUENCY 1000000\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Checks the status of all the demo tasks then prints a message to the\r
+ * display. The message will be either PASS - an include in brackets the\r
+ * maximum measured jitter time (as described at the to of the file), or a\r
+ * message that describes which of the standard demo tasks an error has been\r
+ * discovered in.\r
+ *\r
+ * Messages are not written directly to the terminal, but passed to vOLEDTask\r
+ * via a queue.\r
+ */\r
+static void vCheckTask( void *pvParameters );\r
+\r
+/*\r
+ * The display is written two by more than one task so is controlled by a\r
+ * 'gatekeeper' task. This is the only task that is actually permitted to\r
+ * access the display directly. Other tasks wanting to display a message send\r
+ * the message to the gatekeeper.\r
+ */\r
+static void vOLEDTask( void *pvParameters );\r
+\r
+/*\r
+ * Configure the hardware for the demo.\r
+ */\r
+static void prvSetupHardware( void );\r
+\r
+/*\r
+ * Configures the high frequency timers - those used to measure the timing\r
+ * jitter while the real time kernel is executing.\r
+ */\r
+extern void vSetupTimer( void );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* The queue used to send messages to the OLED task. */\r
+xQueueHandle xOLEDQueue;\r
+\r
+/* The welcome text. */\r
+const portCHAR * const pcWelcomeMessage = " www.FreeRTOS.org";\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+int main( void )\r
+{\r
+ prvSetupHardware();\r
+\r
+ /* Create the queue used by the OLED task. Messages for display on the OLED\r
+ are received via this queue. */\r
+ xOLEDQueue = xQueueCreate( mainOLED_QUEUE_SIZE, sizeof( xOLEDMessage ) );\r
+\r
+ /* Start the standard demo tasks. */\r
+ vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY );\r
+ vCreateBlockTimeTasks();\r
+ vStartSemaphoreTasks( mainSEM_TEST_PRIORITY );\r
+ vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY );\r
+ vStartIntegerMathTasks( mainINTEGER_TASK_PRIORITY );\r
+\r
+ /* Start the tasks defined within this file/specific to this demo. */\r
+ xTaskCreate( vCheckTask, ( signed portCHAR * ) "Check", mainCHECK_TASK_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL );\r
+ xTaskCreate( vOLEDTask, ( signed portCHAR * ) "OLED", configMINIMAL_STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );\r
+\r
+ /* The suicide tasks must be created last as they need to know how many\r
+ tasks were running prior to their creation in order to ascertain whether\r
+ or not the correct/expected number of tasks are running at any given time. */\r
+ vCreateSuicidalTasks( mainCREATOR_TASK_PRIORITY );\r
+\r
+ /* Configure the high frequency interrupt used to measure the interrupt\r
+ jitter time. */\r
+ #ifdef __ICCARM__\r
+ vSetupTimer();\r
+ #endif\r
+ \r
+ /* Start the scheduler. */\r
+ vTaskStartScheduler();\r
+\r
+ /* Will only get here if there was insufficient memory to create the idle\r
+ task. */\r
+ return 0;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void prvSetupHardware( void )\r
+{\r
+ /* Set the clocking to run from the PLL at 50 MHz */\r
+ SysCtlClockSet( SYSCTL_SYSDIV_4 | SYSCTL_USE_PLL | SYSCTL_OSC_MAIN | SYSCTL_XTAL_8MHZ );\r
+ \r
+ /* Enable Port F for Ethernet LEDs\r
+ LED0 Bit 3 Output\r
+ LED1 Bit 2 Output */\r
+ SysCtlPeripheralEnable( SYSCTL_PERIPH_GPIOF );\r
+ GPIODirModeSet( GPIO_PORTF_BASE, (GPIO_PIN_2 | GPIO_PIN_3), GPIO_DIR_MODE_HW );\r
+ GPIOPadConfigSet( GPIO_PORTF_BASE, (GPIO_PIN_2 | GPIO_PIN_3 ), GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD ); \r
+ \r
+ vParTestInitialise();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void vCheckTask( void *pvParameters )\r
+{\r
+portTickType xLastExecutionTime;\r
+xOLEDMessage xMessage;\r
+static portCHAR cPassMessage[ mainMAX_MSG_LEN ];\r
+extern unsigned portLONG ulMaxJitter;\r
+\r
+ xLastExecutionTime = xTaskGetTickCount();\r
+ xMessage.pcMessage = cPassMessage;\r
+ \r
+ for( ;; )\r
+ {\r
+ /* Perform this check every mainCHECK_DELAY milliseconds. */\r
+ vTaskDelayUntil( &xLastExecutionTime, mainCHECK_DELAY );\r
+\r
+ /* Has an error been found in any task? */\r
+\r
+ if( xAreBlockingQueuesStillRunning() != pdTRUE )\r
+ {\r
+ xMessage.pcMessage = "ERROR IN BLOCK Q";\r
+ }\r
+ else if( xAreBlockTimeTestTasksStillRunning() != pdTRUE )\r
+ {\r
+ xMessage.pcMessage = "ERROR IN BLOCK TIME";\r
+ }\r
+ else if( xAreSemaphoreTasksStillRunning() != pdTRUE )\r
+ {\r
+ xMessage.pcMessage = "ERROR IN SEMAPHORE";\r
+ }\r
+ else if( xArePollingQueuesStillRunning() != pdTRUE )\r
+ {\r
+ xMessage.pcMessage = "ERROR IN POLL Q";\r
+ }\r
+ else if( xIsCreateTaskStillRunning() != pdTRUE )\r
+ {\r
+ xMessage.pcMessage = "ERROR IN CREATE";\r
+ }\r
+ else if( xAreIntegerMathsTaskStillRunning() != pdTRUE )\r
+ {\r
+ xMessage.pcMessage = "ERROR IN MATH";\r
+ }\r
+ else\r
+ {\r
+ #ifdef __ICCARM__\r
+ sprintf( cPassMessage, "PASS [%uns]", ulMaxJitter * mainNS_PER_CLOCK );\r
+ #else\r
+ sprintf( cPassMessage, "PASS" );\r
+ #endif\r
+ }\r
+\r
+ /* Send the message to the OLED gatekeeper for display. */\r
+ xQueueSend( xOLEDQueue, &xMessage, portMAX_DELAY );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+\r
+\r
+void vOLEDTask( void *pvParameters )\r
+{\r
+xOLEDMessage xMessage;\r
+unsigned portLONG ulY = mainMAX_ROWS;\r
+\r
+ /* Initialise the OLED and display a startup message. */\r
+ OSRAM128x64x4Init( ulSSI_FREQUENCY ); \r
+ \r
+ OSRAM128x64x4StringDraw( " POWERED BY FreeRTOS", 0, 0, mainFULL_SCALE );\r
+ OSRAM128x64x4ImageDraw( pucImage, 0, mainCHARACTER_HEIGHT + 1, bmpBITMAP_WIDTH, bmpBITMAP_HEIGHT );\r
+ \r
+ for( ;; )\r
+ {\r
+ /* Wait for a message to arrive that requires displaying. */\r
+ xQueueReceive( xOLEDQueue, &xMessage, portMAX_DELAY );\r
+ \r
+ /* Write the message on the next available row. */\r
+ ulY += mainCHARACTER_HEIGHT;\r
+ if( ulY >= mainMAX_ROWS )\r
+ {\r
+ ulY = mainCHARACTER_HEIGHT;\r
+ OSRAM128x64x4Clear();\r
+ OSRAM128x64x4StringDraw( pcWelcomeMessage, 0, 0, mainFULL_SCALE ); \r
+ }\r
+\r
+ /* Display the message. */\r
+ OSRAM128x64x4StringDraw( xMessage.pcMessage, 0, ulY, mainFULL_SCALE );\r
+ }\r
+}\r
--- /dev/null
+#******************************************************************************
+#
+# makedefs - Definitions common to all makefiles.
+#
+# Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
+#
+# Software License Agreement
+#
+# Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+# exclusively on LMI's Stellaris Family of microcontroller products.
+#
+# The software is owned by LMI and/or its suppliers, and is protected under
+# applicable copyright laws. All rights are reserved. Any use in violation
+# of the foregoing restrictions may subject the user to criminal sanctions
+# under applicable laws, as well as to civil liability for the breach of the
+# terms and conditions of this license.
+#
+# THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+# OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+# MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+# LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+# CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+#
+#******************************************************************************
+
+#******************************************************************************
+#
+# Get the operating system name. If this is Cygwin, the .d files will be
+# munged to convert c: into /cygdrive/c so that "make" will be happy with the
+# auto-generated dependencies.
+#
+#******************************************************************************
+os:=${shell uname -s}
+
+#******************************************************************************
+#
+# The compiler to be used.
+#
+#******************************************************************************
+ifndef COMPILER
+COMPILER=gcc
+endif
+
+#******************************************************************************
+#
+# The debugger to be used.
+#
+#******************************************************************************
+ifndef DEBUGGER
+DEBUGGER=gdb
+endif
+
+#******************************************************************************
+#
+# Definitions for using GCC.
+#
+#******************************************************************************
+ifeq (${COMPILER}, gcc)
+
+#
+# The command for calling the compiler.
+#
+CC=arm-stellaris-eabi-gcc
+
+#
+# The flags passed to the assembler.
+#
+AFLAGS=-mthumb \
+ -mcpu=cortex-m3 \
+ -MD
+
+#
+# The flags passed to the compiler.
+#
+CFLAGS=-mthumb \
+ -mcpu=cortex-m3 \
+ -O2 \
+ -MD
+
+#
+# The command for calling the library archiver.
+#
+AR=arm-stellaris-eabi-ar
+
+#
+# The command for calling the linker.
+#
+LD=arm-stellaris-eabi-ld
+
+#
+# The flags passed to the linker.
+#
+LDFLAGS= -Map gcc/out.map
+
+#
+# Get the location of libgcc.a from the GCC front-end.
+#
+LIBGCC=${shell ${CC} -mthumb -march=armv6t2 -print-libgcc-file-name}
+
+#
+# Get the location of libc.a from the GCC front-end.
+#
+LIBC=${shell ${CC} -mthumb -march=armv6t2 -print-file-name=libc.a}
+
+#
+# The command for extracting images from the linked executables.
+#
+OBJCOPY=arm-stellaris-eabi-objcopy
+
+endif
+
+#******************************************************************************
+#
+# Tell the compiler to include debugging information if the DEBUG environment
+# variable is set.
+#
+#******************************************************************************
+ifdef DEBUG
+CFLAGS += -g
+endif
+
+#******************************************************************************
+#
+# The rule for building the object file from each C source file.
+#
+#******************************************************************************
+${COMPILER}/%.o: %.c
+ @if [ 'x${VERBOSE}' = x ]; \
+ then \
+ echo " CC ${<}"; \
+ else \
+ echo ${CC} ${CFLAGS} -D${COMPILER} -o ${@} -c ${<}; \
+ fi
+ @${CC} ${CFLAGS} -D${COMPILER} -o ${@} -c ${<}
+ifeq (${COMPILER}, rvds)
+ @mv -f ${notdir ${@:.o=.d}} ${COMPILER}
+endif
+ifneq ($(findstring CYGWIN, ${os}), )
+ @perl -i.bak -p -e 's/[Cc]:/\/cygdrive\/c/g' ${@:.o=.d}
+endif
+
+#******************************************************************************
+#
+# The rule for building the object file from each assembly source file.
+#
+#******************************************************************************
+${COMPILER}/%.o: %.S
+ @if [ 'x${VERBOSE}' = x ]; \
+ then \
+ echo " CC ${<}"; \
+ else \
+ echo ${CC} ${AFLAGS} -D${COMPILER} -o ${@} -c ${<}; \
+ fi
+ifeq (${COMPILER}, rvds)
+ @${CC} ${AFLAGS} -D${COMPILER} -E ${<} > ${@:.o=_.S}
+ @${CC} ${AFLAGS} -o ${@} -c ${@:.o=_.S}
+ @rm ${@:.o=_.S}
+ @${CC} ${AFLAGS} -D${COMPILER} --md -E ${<}
+ @sed 's,<stdout>,${@},g' ${notdir ${<:.S=.d}} > ${@:.o=.d}
+ @rm ${notdir ${<:.S=.d}}
+endif
+ifeq (${COMPILER}, gcc)
+ @${CC} ${AFLAGS} -D${COMPILER} -o ${@} -c ${<}
+endif
+ifneq ($(findstring CYGWIN, ${os}), )
+ @perl -i.bak -p -e 's/[Cc]:/\/cygdrive\/c/g' ${@:.o=.d}
+endif
+
+#******************************************************************************
+#
+# The rule for creating an object library.
+#
+#******************************************************************************
+${COMPILER}/%.a:
+ @if [ 'x${VERBOSE}' = x ]; \
+ then \
+ echo " AR ${@}"; \
+ else \
+ echo ${AR} -cr ${@} ${^}; \
+ fi
+ @${AR} -cr ${@} ${^}
+
+#******************************************************************************
+#
+# The rule for linking the application.
+#
+#******************************************************************************
+${COMPILER}/%.axf:
+ @if [ 'x${VERBOSE}' = x ]; \
+ then \
+ echo " LD ${@}"; \
+ fi
+ifeq (${COMPILER}, gcc)
+ @if [ 'x${VERBOSE}' != x ]; \
+ then \
+ echo ${LD} -T ${SCATTER_${notdir ${@:.axf=}}} \
+ --entry ${ENTRY_${notdir ${@:.axf=}}} \
+ ${LDFLAGSgcc_${notdir ${@:.axf=}}} \
+ ${LDFLAGS} -o ${@} ${^} \
+ '${LIBC}' '${LIBGCC}'; \
+ fi
+ @${LD} -T ${SCATTER_${notdir ${@:.axf=}}} \
+ --entry ${ENTRY_${notdir ${@:.axf=}}} \
+ ${LDFLAGSgcc_${notdir ${@:.axf=}}} \
+ ${LDFLAGS} -o ${@} ${^} \
+ '${LIBC}' '${LIBGCC}'
+ @${OBJCOPY} -O binary ${@} ${@:.axf=.bin}
+endif
--- /dev/null
+/******************************************************************************\r
+ *\r
+ * standalone.ld - Linker script for applications using startup.c and\r
+ * DriverLib.\r
+ *\r
+ * Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+ * \r
+ * Software License Agreement\r
+ * \r
+ * Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+ * exclusively on LMI's microcontroller products.\r
+ * \r
+ * The software is owned by LMI and/or its suppliers, and is protected under\r
+ * applicable copyright laws. All rights are reserved. Any use in violation\r
+ * of the foregoing restrictions may subject the user to criminal sanctions\r
+ * under applicable laws, as well as to civil liability for the breach of the\r
+ * terms and conditions of this license.\r
+ * \r
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+ * LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+ * \r
+ * This is part of revision 1392 of the Stellaris Peripheral Driver Library.\r
+ *\r
+ *****************************************************************************/\r
+\r
+MEMORY\r
+{\r
+ FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 256K\r
+ SRAM (rwx) : ORIGIN = 0x20000000, LENGTH = 64K\r
+}\r
+\r
+SECTIONS\r
+{\r
+ .text :\r
+ {\r
+ KEEP(*(.isr_vector))\r
+ *(.text*)\r
+ *(.rodata*)\r
+ _etext = .;\r
+ } > FLASH\r
+\r
+ .data : AT (ADDR(.text) + SIZEOF(.text))\r
+ {\r
+ _data = .;\r
+ *(vtable)\r
+ *(.data*)\r
+ _edata = .;\r
+ } > SRAM\r
+\r
+ .bss :\r
+ {\r
+ _bss = .;\r
+ *(.bss*)\r
+ *(COMMON)\r
+ _ebss = .;\r
+ } > SRAM\r
+}\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// startup.c - Boot code for Stellaris.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1392 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+//*****************************************************************************\r
+//\r
+// Forward declaration of the default fault handlers.\r
+//\r
+//*****************************************************************************\r
+void ResetISR(void);\r
+static void NmiSR(void);\r
+static void FaultISR(void);\r
+static void IntDefaultHandler(void);\r
+\r
+//*****************************************************************************\r
+//\r
+// The entry point for the application.\r
+//\r
+//*****************************************************************************\r
+extern int main(void);\r
+extern void xPortPendSVHandler(void);\r
+extern void xPortSysTickHandler(void);\r
+extern void Timer0IntHandler(void);\r
+\r
+//*****************************************************************************\r
+//\r
+// Reserve space for the system stack.\r
+//\r
+//*****************************************************************************\r
+#ifndef STACK_SIZE\r
+#define STACK_SIZE 64\r
+#endif\r
+static unsigned long pulStack[STACK_SIZE];\r
+\r
+//*****************************************************************************\r
+//\r
+// The minimal vector table for a Cortex M3. Note that the proper constructs\r
+// must be placed on this to ensure that it ends up at physical address\r
+// 0x0000.0000.\r
+//\r
+//*****************************************************************************\r
+__attribute__ ((section(".isr_vector")))\r
+void (* const g_pfnVectors[])(void) =\r
+{\r
+ (void (*)(void))((unsigned long)pulStack + sizeof(pulStack)),\r
+ // The initial stack pointer\r
+ ResetISR, // The reset handler\r
+ NmiSR, // The NMI handler\r
+ FaultISR, // The hard fault handler\r
+ IntDefaultHandler, // The MPU fault handler\r
+ IntDefaultHandler, // The bus fault handler\r
+ IntDefaultHandler, // The usage fault handler\r
+ 0, // Reserved\r
+ 0, // Reserved\r
+ 0, // Reserved\r
+ 0, // Reserved\r
+ IntDefaultHandler, // SVCall handler\r
+ IntDefaultHandler, // Debug monitor handler\r
+ 0, // Reserved\r
+ xPortPendSVHandler, // The PendSV handler\r
+ xPortSysTickHandler, // The SysTick handler\r
+ IntDefaultHandler, // GPIO Port A\r
+ IntDefaultHandler, // GPIO Port B\r
+ IntDefaultHandler, // GPIO Port C\r
+ IntDefaultHandler, // GPIO Port D\r
+ IntDefaultHandler, // GPIO Port E\r
+ IntDefaultHandler, // UART0 Rx and Tx\r
+ IntDefaultHandler, // UART1 Rx and Tx\r
+ IntDefaultHandler, // SSI Rx and Tx\r
+ IntDefaultHandler, // I2C Master and Slave\r
+ IntDefaultHandler, // PWM Fault\r
+ IntDefaultHandler, // PWM Generator 0\r
+ IntDefaultHandler, // PWM Generator 1\r
+ IntDefaultHandler, // PWM Generator 2\r
+ IntDefaultHandler, // Quadrature Encoder\r
+ IntDefaultHandler, // ADC Sequence 0\r
+ IntDefaultHandler, // ADC Sequence 1\r
+ IntDefaultHandler, // ADC Sequence 2\r
+ IntDefaultHandler, // ADC Sequence 3\r
+ IntDefaultHandler, // Watchdog timer\r
+ Timer0IntHandler, // Timer 0 subtimer A\r
+ IntDefaultHandler, // Timer 0 subtimer B\r
+ IntDefaultHandler, // Timer 1 subtimer A\r
+ IntDefaultHandler, // Timer 1 subtimer B\r
+ IntDefaultHandler, // Timer 2 subtimer A\r
+ IntDefaultHandler, // Timer 2 subtimer B\r
+ IntDefaultHandler, // Analog Comparator 0\r
+ IntDefaultHandler, // Analog Comparator 1\r
+ IntDefaultHandler, // Analog Comparator 2\r
+ IntDefaultHandler, // System Control (PLL, OSC, BO)\r
+ IntDefaultHandler, // FLASH Control\r
+ IntDefaultHandler, // GPIO Port F\r
+ IntDefaultHandler, // GPIO Port G\r
+ IntDefaultHandler, // GPIO Port H\r
+ IntDefaultHandler, // UART2 Rx and Tx\r
+ IntDefaultHandler, // SSI1 Rx and Tx\r
+ IntDefaultHandler, // Timer 3 subtimer A\r
+ IntDefaultHandler, // Timer 3 subtimer B\r
+ IntDefaultHandler, // I2C1 Master and Slave\r
+ IntDefaultHandler, // Quadrature Encoder 1\r
+ IntDefaultHandler, // CAN0\r
+ IntDefaultHandler, // CAN1\r
+ 0, // Reserved\r
+ IntDefaultHandler, // Ethernet\r
+ IntDefaultHandler // Hibernate\r
+};\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are constructs created by the linker, indicating where the\r
+// the "data" and "bss" segments reside in memory. The initializers for the\r
+// for the "data" segment resides immediately following the "text" segment.\r
+//\r
+//*****************************************************************************\r
+extern unsigned long _etext;\r
+extern unsigned long _data;\r
+extern unsigned long _edata;\r
+extern unsigned long _bss;\r
+extern unsigned long _ebss;\r
+\r
+//*****************************************************************************\r
+//\r
+// This is the code that gets called when the processor first starts execution\r
+// following a reset event. Only the absolutely necessary set is performed,\r
+// after which the application supplied main() routine is called. Any fancy\r
+// actions (such as making decisions based on the reset cause register, and\r
+// resetting the bits in that register) are left solely in the hands of the\r
+// application.\r
+//\r
+//*****************************************************************************\r
+void\r
+ResetISR(void)\r
+{\r
+ unsigned long *pulSrc, *pulDest;\r
+\r
+ //\r
+ // Copy the data segment initializers from flash to SRAM.\r
+ //\r
+ pulSrc = &_etext;\r
+ for(pulDest = &_data; pulDest < &_edata; )\r
+ {\r
+ *pulDest++ = *pulSrc++;\r
+ }\r
+\r
+ //\r
+ // Zero fill the bss segment.\r
+ //\r
+ for(pulDest = &_bss; pulDest < &_ebss; )\r
+ {\r
+ *pulDest++ = 0;\r
+ }\r
+\r
+ //\r
+ // Call the application's entry point.\r
+ //\r
+ main();\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+// This is the code that gets called when the processor receives a NMI. This\r
+// simply enters an infinite loop, preserving the system state for examination\r
+// by a debugger.\r
+//\r
+//*****************************************************************************\r
+static void\r
+NmiSR(void)\r
+{\r
+ //\r
+ // Enter an infinite loop.\r
+ //\r
+ while(1)\r
+ {\r
+ }\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+// This is the code that gets called when the processor receives a fault\r
+// interrupt. This simply enters an infinite loop, preserving the system state\r
+// for examination by a debugger.\r
+//\r
+//*****************************************************************************\r
+static void\r
+FaultISR(void)\r
+{\r
+ //\r
+ // Enter an infinite loop.\r
+ //\r
+ while(1)\r
+ {\r
+ }\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+// This is the code that gets called when the processor receives an unexpected\r
+// interrupt. This simply enters an infinite loop, preserving the system state\r
+// for examination by a debugger.\r
+//\r
+//*****************************************************************************\r
+static void\r
+IntDefaultHandler(void)\r
+{\r
+ //\r
+ // Go into an infinite loop.\r
+ //\r
+ while(1)\r
+ {\r
+ }\r
+}\r
--- /dev/null
+/*\r
+ FreeRTOS.org V4.3.0 - Copyright (C) 2003-2007 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS.org distribution.\r
+\r
+ FreeRTOS.org is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS.org is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS.org; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS.org, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section\r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license\r
+ and contact details. Please ensure to read the configuration and relevant\r
+ port sections of the online documentation.\r
+\r
+ Also see http://www.SafeRTOS.com for an IEC 61508 compliant version along\r
+ with commercial development and support options.\r
+ ***************************************************************************\r
+*/\r
+\r
+/* High speed timer test as described in main.c. */\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+\r
+/* Library includes. */\r
+#include "hw_ints.h"\r
+#include "hw_memmap.h"\r
+#include "hw_types.h"\r
+#include "interrupt.h"\r
+#include "sysctl.h"\r
+#include "LMI_timer.h"\r
+\r
+/* The set frequency of the interrupt. Deviations from this are measured as\r
+the jitter. */\r
+#define timerINTERRUPT_FREQUENCY ( 20000UL )\r
+\r
+/* The expected time between each of the timer interrupts - if the jitter was\r
+zero. */\r
+#define timerEXPECTED_DIFFERENCE_VALUE ( configCPU_CLOCK_HZ / timerINTERRUPT_FREQUENCY )\r
+\r
+/* The highest available interrupt priority. */\r
+#define timerHIGHEST_PRIORITY ( 0 )\r
+\r
+/* Misc defines. */\r
+#define timerMAX_32BIT_VALUE ( 0xffffffffUL )\r
+#define timerTIMER_1_COUNT_VALUE ( * ( ( unsigned long * ) ( TIMER1_BASE + 0x48 ) ) )\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Interrupt handler in which the jitter is measured. */\r
+void Timer0IntHandler( void );\r
+\r
+/* Stores the value of the maximum recorded jitter between interrupts. */\r
+unsigned portLONG ulMaxJitter = 0;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void vSetupTimer( void )\r
+{\r
+unsigned long ulFrequency;\r
+\r
+ /* Timer zero is used to generate the interrupts, and timer 1 is used\r
+ to measure the jitter. */\r
+ SysCtlPeripheralEnable( SYSCTL_PERIPH_TIMER0 );\r
+ SysCtlPeripheralEnable( SYSCTL_PERIPH_TIMER1 );\r
+ TimerConfigure( TIMER0_BASE, TIMER_CFG_32_BIT_PER );\r
+ TimerConfigure( TIMER1_BASE, TIMER_CFG_32_BIT_PER );\r
+ \r
+ /* Set the timer interrupt to be above the kernel - highest. */\r
+ IntPrioritySet( INT_TIMER0A, timerHIGHEST_PRIORITY );\r
+\r
+ /* Just used to measure time. */\r
+ TimerLoadSet(TIMER1_BASE, TIMER_A, timerMAX_32BIT_VALUE );\r
+ \r
+ /* The rate at which the timer will interrupt. */\r
+ ulFrequency = configCPU_CLOCK_HZ / timerINTERRUPT_FREQUENCY; \r
+ TimerLoadSet( TIMER0_BASE, TIMER_A, ulFrequency );\r
+ IntEnable( INT_TIMER0A );\r
+ TimerIntEnable( TIMER0_BASE, TIMER_TIMA_TIMEOUT );\r
+\r
+ /* Enable both timers. */ \r
+ TimerEnable( TIMER0_BASE, TIMER_A );\r
+ TimerEnable( TIMER1_BASE, TIMER_A );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void Timer0IntHandler( void )\r
+{\r
+unsigned portLONG ulDifference, ulCurrentCount;\r
+static portLONG ulMaxDifference = 0, ulLastCount = 0;\r
+\r
+ /* We use the timer 1 counter value to measure the clock cycles between\r
+ the timer 0 interrupts. */\r
+ ulCurrentCount = timerTIMER_1_COUNT_VALUE;\r
+\r
+ if( ulCurrentCount < ulLastCount )\r
+ { \r
+ /* How many times has timer 1 counted since the last interrupt? */\r
+ ulDifference = ulLastCount - ulCurrentCount;\r
+ \r
+ /* Is this the largest difference we have measured yet? */\r
+ if( ulDifference > ulMaxDifference )\r
+ {\r
+ ulMaxDifference = ulDifference;\r
+ ulMaxJitter = ulMaxDifference - timerEXPECTED_DIFFERENCE_VALUE;\r
+ }\r
+ }\r
+ \r
+ ulLastCount = ulCurrentCount;\r
+\r
+ TimerIntClear( TIMER0_BASE, TIMER_TIMA_TIMEOUT );\r
+}\r
+\r
+\r
+\r
+\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS.org V4.3.0 - Copyright (C) 2003-2007 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS.org distribution.\r
+\r
+ FreeRTOS.org is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS.org is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS.org; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS.org, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section\r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license\r
+ and contact details. Please ensure to read the configuration and relevant\r
+ port sections of the online documentation.\r
+\r
+ Also see http://www.SafeRTOS.com for an IEC 61508 compliant version along\r
+ with commercial development and support options.\r
+ ***************************************************************************\r
+*/\r
+\r
+#ifndef FREERTOS_CONFIG_H\r
+#define FREERTOS_CONFIG_H\r
+\r
+/*-----------------------------------------------------------\r
+ * Application specific definitions.\r
+ *\r
+ * These definitions should be adjusted for your particular hardware and\r
+ * application requirements.\r
+ *\r
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE\r
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.\r
+ *----------------------------------------------------------*/\r
+\r
+#define configUSE_PREEMPTION 1\r
+#define configUSE_IDLE_HOOK 0\r
+#define configUSE_TICK_HOOK 0\r
+#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 50000000 )\r
+#define configTICK_RATE_HZ ( ( portTickType ) 1000 )\r
+#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 70 )\r
+#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 12000 ) )\r
+#define configMAX_TASK_NAME_LEN ( 12 )\r
+#define configUSE_TRACE_FACILITY 1\r
+#define configUSE_16_BIT_TICKS 0\r
+#define configIDLE_SHOULD_YIELD 0\r
+#define configUSE_CO_ROUTINES 1\r
+\r
+#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 5 )\r
+#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )\r
+\r
+/* Set the following definitions to 1 to include the API function, or zero\r
+to exclude the API function. */\r
+\r
+#define INCLUDE_vTaskPrioritySet 1\r
+#define INCLUDE_uxTaskPriorityGet 0\r
+#define INCLUDE_vTaskDelete 1\r
+#define INCLUDE_vTaskCleanUpResources 0\r
+#define INCLUDE_vTaskSuspend 1\r
+#define INCLUDE_vTaskDelayUntil 1\r
+#define INCLUDE_vTaskDelay 1\r
+\r
+\r
+#define configKERNEL_INTERRUPT_PRIORITY 255\r
+\r
+\r
+#endif /* FREERTOS_CONFIG_H */\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// LM3Sxxx.h - Header file for Luminary Micro LM3Sxxx microcontrollers.\r
+//\r
+// Copyright (c) 2006-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __LM3SXXX_H__\r
+#define __LM3SXXX_H__\r
+\r
+#include "hw_adc.h"\r
+#include "hw_comp.h"\r
+#include "hw_flash.h"\r
+#include "hw_gpio.h"\r
+#include "hw_i2c.h"\r
+#include "hw_ints.h"\r
+#include "hw_memmap.h"\r
+#include "hw_nvic.h"\r
+#include "hw_pwm.h"\r
+#include "hw_qei.h"\r
+#include "hw_ssi.h"\r
+#include "hw_sysctl.h"\r
+#include "hw_timer.h"\r
+#include "hw_types.h"\r
+#include "hw_uart.h"\r
+#include "hw_watchdog.h"\r
+#include "adc.h"\r
+#include "comp.h"\r
+#include "cpu.h"\r
+#include "debug.h"\r
+#include "flash.h"\r
+#include "gpio.h"\r
+#include "i2c.h"\r
+#include "interrupt.h"\r
+#include "pwm.h"\r
+#include "qei.h"\r
+#include "ssi.h"\r
+#include "sysctl.h"\r
+#include "systick.h"\r
+#include "timer.h"\r
+#include "uart.h"\r
+#include "watchdog.h"\r
+\r
+#endif // __LM3SXXX_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// LM3Sxxxx.h - Header file for Luminary Micro LM3Sxxxx microcontrollers.\r
+//\r
+// Copyright (c) 2006-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __LM3SXXXX_H__\r
+#define __LM3SXXXX_H__\r
+\r
+#include "hw_adc.h"\r
+#include "hw_can.h"\r
+#include "hw_comp.h"\r
+#include "hw_ethernet.h"\r
+#include "hw_flash.h"\r
+#include "hw_gpio.h"\r
+#include "hw_hibernate.h"\r
+#include "hw_i2c.h"\r
+#include "hw_ints.h"\r
+#include "hw_memmap.h"\r
+#include "hw_nvic.h"\r
+#include "hw_pwm.h"\r
+#include "hw_qei.h"\r
+#include "hw_ssi.h"\r
+#include "hw_sysctl.h"\r
+#include "hw_timer.h"\r
+#include "hw_types.h"\r
+#include "hw_uart.h"\r
+#include "hw_watchdog.h"\r
+#include "adc.h"\r
+#include "can.h"\r
+#include "comp.h"\r
+#include "cpu.h"\r
+#include "debug.h"\r
+#include "ethernet.h"\r
+#include "flash.h"\r
+#include "gpio.h"\r
+#include "hibernate.h"\r
+#include "i2c.h"\r
+#include "interrupt.h"\r
+#include "pwm.h"\r
+#include "qei.h"\r
+#include "ssi.h"\r
+#include "sysctl.h"\r
+#include "systick.h"\r
+#include "timer.h"\r
+#include "uart.h"\r
+#include "watchdog.h"\r
+\r
+#endif // __LM3SXXXX_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// flash.h - Prototypes for the flash driver.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __FLASH_H__\r
+#define __FLASH_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to FlashProtectSet(), and returned by\r
+// FlashProtectGet().\r
+//\r
+//*****************************************************************************\r
+typedef enum\r
+{\r
+ FlashReadWrite, // Flash can be read and written\r
+ FlashReadOnly, // Flash can only be read\r
+ FlashExecuteOnly // Flash can only be executed\r
+}\r
+tFlashProtection;\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+extern unsigned long FlashUsecGet(void);\r
+extern void FlashUsecSet(unsigned long ulClocks);\r
+extern long FlashErase(unsigned long ulAddress);\r
+extern long FlashProgram(unsigned long *pulData, unsigned long ulAddress,\r
+ unsigned long ulCount);\r
+extern tFlashProtection FlashProtectGet(unsigned long ulAddress);\r
+extern long FlashProtectSet(unsigned long ulAddress,\r
+ tFlashProtection eProtect);\r
+extern long FlashProtectSave(void);\r
+extern long FlashUserGet(unsigned long *pulUser0, unsigned long *pulUser1);\r
+extern long FlashUserSet(unsigned long ulUser0, unsigned long ulUser1);\r
+extern long FlashUserSave(void);\r
+extern void FlashIntRegister(void (*pfnHandler)(void));\r
+extern void FlashIntUnregister(void);\r
+extern void FlashIntEnable(unsigned long ulIntFlags);\r
+extern void FlashIntDisable(unsigned long ulIntFlags);\r
+extern unsigned long FlashIntGetStatus(tBoolean bMasked);\r
+extern void FlashIntClear(unsigned long ulIntFlags);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __FLASH_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// timer.h - Prototypes for the timer module\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __TIMER_H__\r
+#define __TIMER_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to TimerConfigure as the ulConfig parameter.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_CFG_32_BIT_OS 0x00000001 // 32-bit one-shot timer\r
+#define TIMER_CFG_32_BIT_PER 0x00000002 // 32-bit periodic timer\r
+#define TIMER_CFG_32_RTC 0x01000000 // 32-bit RTC timer\r
+#define TIMER_CFG_16_BIT_PAIR 0x04000000 // Two 16-bit timers\r
+#define TIMER_CFG_A_ONE_SHOT 0x00000001 // Timer A one-shot timer\r
+#define TIMER_CFG_A_PERIODIC 0x00000002 // Timer A periodic timer\r
+#define TIMER_CFG_A_CAP_COUNT 0x00000003 // Timer A event counter\r
+#define TIMER_CFG_A_CAP_TIME 0x00000007 // Timer A event timer\r
+#define TIMER_CFG_A_PWM 0x0000000A // Timer A PWM output\r
+#define TIMER_CFG_B_ONE_SHOT 0x00000100 // Timer B one-shot timer\r
+#define TIMER_CFG_B_PERIODIC 0x00000200 // Timer B periodic timer\r
+#define TIMER_CFG_B_CAP_COUNT 0x00000300 // Timer B event counter\r
+#define TIMER_CFG_B_CAP_TIME 0x00000700 // Timer B event timer\r
+#define TIMER_CFG_B_PWM 0x00000A00 // Timer B PWM output\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to TimerIntEnable, TimerIntDisable, and\r
+// TimerIntClear as the ulIntFlags parameter, and returned from TimerIntStatus.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_CAPB_EVENT 0x00000400 // CaptureB event interrupt\r
+#define TIMER_CAPB_MATCH 0x00000200 // CaptureB match interrupt\r
+#define TIMER_TIMB_TIMEOUT 0x00000100 // TimerB time out interrupt\r
+#define TIMER_RTC_MATCH 0x00000008 // RTC interrupt mask\r
+#define TIMER_CAPA_EVENT 0x00000004 // CaptureA event interrupt\r
+#define TIMER_CAPA_MATCH 0x00000002 // CaptureA match interrupt\r
+#define TIMER_TIMA_TIMEOUT 0x00000001 // TimerA time out interrupt\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to TimerControlEvent as the ulEvent parameter.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_EVENT_POS_EDGE 0x00000000 // Count positive edges\r
+#define TIMER_EVENT_NEG_EDGE 0x00000404 // Count negative edges\r
+#define TIMER_EVENT_BOTH_EDGES 0x00000C0C // Count both edges\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to most of the timer APIs as the ulTimer\r
+// parameter.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_A 0x000000ff // Timer A\r
+#define TIMER_B 0x0000ff00 // Timer B\r
+#define TIMER_BOTH 0x0000ffff // Timer Both\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+extern void TimerEnable(unsigned long ulBase, unsigned long ulTimer);\r
+extern void TimerDisable(unsigned long ulBase, unsigned long ulTimer);\r
+extern void TimerConfigure(unsigned long ulBase, unsigned long ulConfig);\r
+extern void TimerControlLevel(unsigned long ulBase, unsigned long ulTimer,\r
+ tBoolean bInvert);\r
+extern void TimerControlTrigger(unsigned long ulBase, unsigned long ulTimer,\r
+ tBoolean bEnable);\r
+extern void TimerControlEvent(unsigned long ulBase, unsigned long ulTimer,\r
+ unsigned long ulEvent);\r
+extern void TimerControlStall(unsigned long ulBase, unsigned long ulTimer,\r
+ tBoolean bStall);\r
+extern void TimerRTCEnable(unsigned long ulBase);\r
+extern void TimerRTCDisable(unsigned long ulBase);\r
+extern void TimerPrescaleSet(unsigned long ulBase, unsigned long ulTimer,\r
+ unsigned long ulValue);\r
+extern unsigned long TimerPrescaleGet(unsigned long ulBase,\r
+ unsigned long ulTimer);\r
+extern void TimerPrescaleMatchSet(unsigned long ulBase, unsigned long ulTimer,\r
+ unsigned long ulValue);\r
+extern unsigned long TimerPrescaleMatchGet(unsigned long ulBase,\r
+ unsigned long ulTimer);\r
+extern void TimerLoadSet(unsigned long ulBase, unsigned long ulTimer,\r
+ unsigned long ulValue);\r
+extern unsigned long TimerLoadGet(unsigned long ulBase, unsigned long ulTimer);\r
+extern unsigned long TimerValueGet(unsigned long ulBase,\r
+ unsigned long ulTimer);\r
+extern void TimerMatchSet(unsigned long ulBase, unsigned long ulTimer,\r
+ unsigned long ulValue);\r
+extern unsigned long TimerMatchGet(unsigned long ulBase,\r
+ unsigned long ulTimer);\r
+extern void TimerIntRegister(unsigned long ulBase, unsigned long ulTimer,\r
+ void (*pfnHandler)(void));\r
+extern void TimerIntUnregister(unsigned long ulBase, unsigned long ulTimer);\r
+extern void TimerIntEnable(unsigned long ulBase, unsigned long ulIntFlags);\r
+extern void TimerIntDisable(unsigned long ulBase, unsigned long ulIntFlags);\r
+extern unsigned long TimerIntStatus(unsigned long ulBase, tBoolean bMasked);\r
+extern void TimerIntClear(unsigned long ulBase, unsigned long ulIntFlags);\r
+extern void TimerQuiesce(unsigned long ulBase);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __TIMER_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// adc.h - ADC headers for using the ADC driver functions.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __ADC_H__\r
+#define __ADC_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to ADCSequenceConfigure as the ulTrigger\r
+// parameter.\r
+//\r
+//*****************************************************************************\r
+#define ADC_TRIGGER_PROCESSOR 0x00000000 // Processor event\r
+#define ADC_TRIGGER_COMP0 0x00000001 // Analog comparator 0 event\r
+#define ADC_TRIGGER_COMP1 0x00000002 // Analog comparator 1 event\r
+#define ADC_TRIGGER_COMP2 0x00000003 // Analog comparator 2 event\r
+#define ADC_TRIGGER_EXTERNAL 0x00000004 // External event\r
+#define ADC_TRIGGER_TIMER 0x00000005 // Timer event\r
+#define ADC_TRIGGER_PWM0 0x00000006 // PWM0 event\r
+#define ADC_TRIGGER_PWM1 0x00000007 // PWM1 event\r
+#define ADC_TRIGGER_PWM2 0x00000008 // PWM2 event\r
+#define ADC_TRIGGER_ALWAYS 0x0000000F // Always event\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to ADCSequenceStepConfigure as the ulConfig\r
+// parameter.\r
+//\r
+//*****************************************************************************\r
+#define ADC_CTL_TS 0x00000080 // Temperature sensor select\r
+#define ADC_CTL_IE 0x00000040 // Interrupt enable\r
+#define ADC_CTL_END 0x00000020 // Sequence end select\r
+#define ADC_CTL_D 0x00000010 // Differential select\r
+#define ADC_CTL_CH0 0x00000000 // Input channel 0\r
+#define ADC_CTL_CH1 0x00000001 // Input channel 1\r
+#define ADC_CTL_CH2 0x00000002 // Input channel 2\r
+#define ADC_CTL_CH3 0x00000003 // Input channel 3\r
+#define ADC_CTL_CH4 0x00000004 // Input channel 4\r
+#define ADC_CTL_CH5 0x00000005 // Input channel 5\r
+#define ADC_CTL_CH6 0x00000006 // Input channel 6\r
+#define ADC_CTL_CH7 0x00000007 // Input channel 7\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+extern void ADCIntRegister(unsigned long ulBase, unsigned long ulSequenceNum,\r
+ void (*pfnHandler)(void));\r
+extern void ADCIntUnregister(unsigned long ulBase,\r
+ unsigned long ulSequenceNum);\r
+extern void ADCIntDisable(unsigned long ulBase, unsigned long ulSequenceNum);\r
+extern void ADCIntEnable(unsigned long ulBase, unsigned long ulSequenceNum);\r
+extern unsigned long ADCIntStatus(unsigned long ulBase,\r
+ unsigned long ulSequenceNum,\r
+ tBoolean bMasked);\r
+extern void ADCIntClear(unsigned long ulBase, unsigned long ulSequenceNum);\r
+extern void ADCSequenceEnable(unsigned long ulBase,\r
+ unsigned long ulSequenceNum);\r
+extern void ADCSequenceDisable(unsigned long ulBase,\r
+ unsigned long ulSequenceNum);\r
+extern void ADCSequenceConfigure(unsigned long ulBase,\r
+ unsigned long ulSequenceNum,\r
+ unsigned long ulTrigger,\r
+ unsigned long ulPriority);\r
+extern void ADCSequenceStepConfigure(unsigned long ulBase,\r
+ unsigned long ulSequenceNum,\r
+ unsigned long ulStep,\r
+ unsigned long ulConfig);\r
+extern long ADCSequenceOverflow(unsigned long ulBase,\r
+ unsigned long ulSequenceNum);\r
+extern void ADCSequenceOverflowClear(unsigned long ulBase,\r
+ unsigned long ulSequenceNum);\r
+extern long ADCSequenceUnderflow(unsigned long ulBase,\r
+ unsigned long ulSequenceNum);\r
+extern void ADCSequenceUnderflowClear(unsigned long ulBase,\r
+ unsigned long ulSequenceNum);\r
+extern long ADCSequenceDataGet(unsigned long ulBase,\r
+ unsigned long ulSequenceNum,\r
+ unsigned long *pulBuffer);\r
+extern void ADCProcessorTrigger(unsigned long ulBase,\r
+ unsigned long ulSequenceNum);\r
+extern void ADCSoftwareOversampleConfigure(unsigned long ulBase,\r
+ unsigned long ulSequenceNum,\r
+ unsigned long ulFactor);\r
+extern void ADCSoftwareOversampleStepConfigure(unsigned long ulBase,\r
+ unsigned long ulSequenceNum,\r
+ unsigned long ulStep,\r
+ unsigned long ulConfig);\r
+extern void ADCSoftwareOversampleDataGet(unsigned long ulBase,\r
+ unsigned long ulSequenceNum,\r
+ unsigned long *pulBuffer,\r
+ unsigned long ulCount);\r
+extern void ADCHardwareOversampleConfigure(unsigned long ulBase,\r
+ unsigned long ulFactor);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __ADC_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// can.h - Defines and Macros for the CAN controller.\r
+//\r
+// Copyright (c) 2006-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __CAN_H__\r
+#define __CAN_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! \addtogroup can_api\r
+//! @{\r
+//\r
+//*****************************************************************************\r
+\r
+//*****************************************************************************\r
+//\r
+// Miscellaneous defines for Message ID Types\r
+//\r
+//*****************************************************************************\r
+\r
+//*****************************************************************************\r
+//\r
+//! These are the flags used by the tCANMsgObject variable when calling the\r
+//! the CANMessageSet() and CANMessageGet() APIs.\r
+//\r
+//*****************************************************************************\r
+typedef enum\r
+{\r
+ //\r
+ //! This indicates that transmit interrupts should be enabled, or are\r
+ //! enabled.\r
+ //\r
+ MSG_OBJ_TX_INT_ENABLE = 0x00000001,\r
+\r
+ //\r
+ //! This indicates that receive interrupts should be enabled or are\r
+ //! enabled.\r
+ //\r
+ MSG_OBJ_RX_INT_ENABLE = 0x00000002,\r
+\r
+ //\r
+ //! This indicates that a message object will use or is using an extended\r
+ //! identifier.\r
+ //\r
+ MSG_OBJ_EXTENDED_ID = 0x00000004,\r
+\r
+ //\r
+ //! This indicates that a message object will use or is using filtering\r
+ //! based on the object's message Identifier.\r
+ //\r
+ MSG_OBJ_USE_ID_FILTER = 0x00000008,\r
+\r
+ //\r
+ //! This indicates that new data was available in the message object.\r
+ //\r
+ MSG_OBJ_NEW_DATA = 0x00000080,\r
+\r
+ //\r
+ //! This indicates that data was lost since this message object was last\r
+ //! read.\r
+ //\r
+ MSG_OBJ_DATA_LOST = 0x00000100,\r
+\r
+ //\r
+ //! This indicates that a message object will use or is using filtering\r
+ //! based on the direction of the transfer. If the direction filtering is\r
+ //! used then ID filtering must also be enabled.\r
+ //\r
+ MSG_OBJ_USE_DIR_FILTER = (0x00000010 | MSG_OBJ_USE_ID_FILTER),\r
+\r
+ //\r
+ //! This indicates that a message object will use or is using message\r
+ //! identifier filtering based of the the extended identifier.\r
+ //! If the extended identifier filtering is used then ID filtering must\r
+ //! also be enabled.\r
+ //\r
+ MSG_OBJ_USE_EXT_FILTER = (0x00000020 | MSG_OBJ_USE_ID_FILTER),\r
+\r
+ //\r
+ //! This indicates that a message object is a remote frame.\r
+ //\r
+ MSG_OBJ_REMOTE_FRAME = 0x00000040,\r
+\r
+ //\r
+ //! This indicates that a message object has no flags set.\r
+ //\r
+ MSG_OBJ_NO_FLAGS = 0x00000000\r
+}\r
+tCANObjFlags;\r
+\r
+//*****************************************************************************\r
+//\r
+//! This define is used with the #tCANObjFlags enumerated values to allow\r
+//! checking only status flags and not configuration flags.\r
+//\r
+//*****************************************************************************\r
+#define MSG_OBJ_STATUS_MASK (MSG_OBJ_NEW_DATA | MSG_OBJ_DATA_LOST)\r
+\r
+//*****************************************************************************\r
+//\r
+//! This structure used for encapsulating all the items associated with a CAN\r
+//! message object in the CAN controller.\r
+//\r
+//*****************************************************************************\r
+typedef struct\r
+{\r
+ //\r
+ //! The CAN message identifier used for 11 or 29 bit identifiers.\r
+ //\r
+ unsigned long ulMsgID;\r
+\r
+ //\r
+ //! The message identifier mask used when identifier filtering is enabled.\r
+ //\r
+ unsigned long ulMsgIDMask;\r
+\r
+ //\r
+ //! This value holds various status flags and settings specified by\r
+ //! tCANObjFlags.\r
+ //\r
+ unsigned long ulFlags;\r
+\r
+ //\r
+ //! This value is the number of bytes of data in the message object.\r
+ //\r
+ unsigned long ulMsgLen;\r
+\r
+ //\r
+ //! This is a pointer to the message object's data.\r
+ //\r
+ unsigned char *pucMsgData;\r
+}\r
+tCANMsgObject;\r
+\r
+//*****************************************************************************\r
+//\r
+//! This structure is used for encapsulating the values associated with setting\r
+//! up the bit timing for a CAN controller. The structure is used when calling\r
+//! the CANGetBitTiming and CANSetBitTiming functions.\r
+//\r
+//*****************************************************************************\r
+typedef struct\r
+{\r
+ //\r
+ //! This value holds the sum of the Synchronization, Propagation, and Phase\r
+ //! Buffer 1 segments, measured in time quanta. The valid values for this\r
+ //! setting range from 2 to 16.\r
+ //\r
+ unsigned int uSyncPropPhase1Seg;\r
+\r
+ //\r
+ //! This value holds the Phase Buffer 2 segment in time quanta. The valid\r
+ //! values for this setting range from 1 to 8.\r
+ //\r
+ unsigned int uPhase2Seg;\r
+\r
+ //\r
+ //! This value holds the Resynchronization Jump Width in time quanta. The\r
+ //! valid values for this setting range from 1 to 4.\r
+ //\r
+ unsigned int uSJW;\r
+\r
+ //\r
+ //! This value holds the CAN_CLK divider used to determine time quanta.\r
+ //! The valid values for this setting range from 1 to 1023.\r
+ //\r
+ unsigned int uQuantumPrescaler;\r
+\r
+}\r
+tCANBitClkParms;\r
+\r
+//*****************************************************************************\r
+//\r
+//! This data type is used to identify the interrupt status register. This is\r
+//! used when calling the a CANIntStatus() function.\r
+//\r
+//*****************************************************************************\r
+typedef enum\r
+{\r
+ //\r
+ //! Read the CAN interrupt status information.\r
+ //\r
+ CAN_INT_STS_CAUSE,\r
+\r
+ //\r
+ //! Read a message object's interrupt status.\r
+ //\r
+ CAN_INT_STS_OBJECT\r
+}\r
+tCANIntStsReg;\r
+\r
+//*****************************************************************************\r
+//\r
+//! This data type is used to identify which of the several status registers\r
+//! to read when calling the CANStatusGet() function.\r
+//\r
+//*****************************************************************************\r
+typedef enum\r
+{\r
+ //\r
+ //! Read the full CAN controller status.\r
+ //\r
+ CAN_STS_CONTROL,\r
+\r
+ //\r
+ //! Read the full 32 bit mask of message objects with a transmit request\r
+ //! set.\r
+ //\r
+ CAN_STS_TXREQUEST,\r
+\r
+ //\r
+ //! Read the full 32 bit mask of message objects with a new data available.\r
+ //\r
+ CAN_STS_NEWDAT,\r
+\r
+ //\r
+ //! Read the full 32 bit mask of message objects that are enabled.\r
+ //\r
+ CAN_STS_MSGVAL\r
+}\r
+tCANStsReg;\r
+\r
+//*****************************************************************************\r
+//\r
+//! These definitions are used to specify interrupt sources to CANIntEnable()\r
+//! and CANIntDisable().\r
+//\r
+//*****************************************************************************\r
+typedef enum\r
+{\r
+ //\r
+ //! This flag is used to allow a CAN controller to generate error\r
+ //! interrupts.\r
+ //\r
+ CAN_INT_ERROR = 0x00000008,\r
+\r
+ //\r
+ //! This flag is used to allow a CAN controller to generate status\r
+ //! interrupts.\r
+ //\r
+ CAN_INT_STATUS = 0x00000004,\r
+\r
+ //\r
+ //! This flag is used to allow a CAN controller to generate any CAN\r
+ //! interrupts. If this is not set then no interrupts will be generated by\r
+ //! the CAN controller.\r
+ //\r
+ CAN_INT_MASTER = 0x00000002\r
+}\r
+tCANIntFlags;\r
+\r
+//*****************************************************************************\r
+//\r
+//! This definition is used to determine the type of message object that will\r
+//! be set up via a call to the CANMessageSet() API.\r
+//\r
+//*****************************************************************************\r
+typedef enum\r
+{\r
+ //\r
+ //! Transmit message object.\r
+ //\r
+ MSG_OBJ_TYPE_TX,\r
+\r
+ //\r
+ //! Transmit remote request message object\r
+ //\r
+ MSG_OBJ_TYPE_TX_REMOTE,\r
+\r
+ //\r
+ //! Receive message object.\r
+ //\r
+ MSG_OBJ_TYPE_RX,\r
+\r
+ //\r
+ //! Receive remote request message object.\r
+ //\r
+ MSG_OBJ_TYPE_RX_REMOTE,\r
+\r
+ //\r
+ //! Remote frame receive remote, with auto-transmit message object.\r
+ //\r
+ MSG_OBJ_TYPE_RXTX_REMOTE\r
+}\r
+tMsgObjType;\r
+\r
+//*****************************************************************************\r
+//\r
+//! The following enumeration contains all error or status indicators that\r
+//! can be returned when calling the CANStatusGet() API.\r
+//\r
+//*****************************************************************************\r
+typedef enum\r
+{\r
+ //\r
+ //! CAN controller has entered a Bus Off state.\r
+ //\r
+ CAN_STATUS_BUS_OFF = 0x00000080,\r
+\r
+ //\r
+ //! CAN controller error level has reached warning level.\r
+ //\r
+ CAN_STATUS_EWARN = 0x00000040,\r
+\r
+ //\r
+ //! CAN controller error level has reached error passive level.\r
+ //\r
+ CAN_STATUS_EPASS = 0x00000020,\r
+\r
+ //\r
+ //! A message was received successfully since the last read of this status.\r
+ //\r
+ CAN_STATUS_RXOK = 0x00000010,\r
+\r
+ //\r
+ //! A message was transmitted successfully since the last read of this\r
+ //! status.\r
+ //\r
+ CAN_STATUS_TXOK = 0x00000008,\r
+\r
+ //\r
+ //! This is the mask for the last error code field.\r
+ //\r
+ CAN_STATUS_LEC_MSK = 0x00000007,\r
+\r
+ //\r
+ //! There was no error.\r
+ //\r
+ CAN_STATUS_LEC_NONE = 0x00000000,\r
+\r
+ //\r
+ //! A bit stuffing error has occurred.\r
+ //\r
+ CAN_STATUS_LEC_STUFF = 0x00000001,\r
+\r
+ //\r
+ //! A formatting error has occurred.\r
+ //\r
+ CAN_STATUS_LEC_FORM = 0x00000002,\r
+\r
+ //\r
+ //! An acknowledge error has occurred.\r
+ //\r
+ CAN_STATUS_LEC_ACK = 0x00000003,\r
+\r
+ //\r
+ //! The bus remained a bit level of 1 for longer than is allowed.\r
+ //\r
+ CAN_STATUS_LEC_BIT1 = 0x00000004,\r
+\r
+ //\r
+ //! The bus remained a bit level of 0 for longer than is allowed.\r
+ //\r
+ CAN_STATUS_LEC_BIT0 = 0x00000005,\r
+\r
+ //\r
+ //! A CRC error has occurred.\r
+ //\r
+ CAN_STATUS_LEC_CRC = 0x00000006,\r
+\r
+ //\r
+ //! This is the mask for the CAN Last Error Code (LEC).\r
+ //\r
+ CAN_STATUS_LEC_MASK = 0x00000007\r
+}\r
+tCANStatusCtrl;\r
+\r
+//*****************************************************************************\r
+//\r
+// API Function prototypes\r
+//\r
+//*****************************************************************************\r
+extern void CANInit(unsigned long ulBase);\r
+extern void CANEnable(unsigned long ulBase);\r
+extern void CANDisable(unsigned long ulBase);\r
+extern void CANSetBitTiming(unsigned long ulBase, tCANBitClkParms *pClkParms);\r
+extern void CANGetBitTiming(unsigned long ulBase, tCANBitClkParms *pClkParms);\r
+extern unsigned long CANReadReg(unsigned long ulRegAddress);\r
+extern void CANWriteReg(unsigned long ulRegAddress, unsigned long ulRegValue);\r
+extern void CANMessageSet(unsigned long ulBase, unsigned long ulObjID,\r
+ tCANMsgObject *pMsgObject, tMsgObjType eMsgType);\r
+extern void CANMessageGet(unsigned long ulBase, unsigned long ulObjID,\r
+ tCANMsgObject *pMsgObject, tBoolean bClrPendingInt);\r
+extern unsigned long CANStatusGet(unsigned long ulBase, tCANStsReg eStatusReg);\r
+extern void CANMessageClear(unsigned long ulBase, unsigned long ulObjID);\r
+extern void CANIntRegister(unsigned long ulBase, void (*pfnHandler)(void));\r
+extern void CANIntEnable(unsigned long ulBase, unsigned long ulIntFlags);\r
+extern void CANIntDisable(unsigned long ulBase, unsigned long ulIntFlags);\r
+extern void CANIntClear(unsigned long ulBase, unsigned long ulIntClr);\r
+extern unsigned long CANIntStatus(unsigned long ulBase,\r
+ tCANIntStsReg eIntStsReg);\r
+extern tBoolean CANRetryGet(unsigned long ulBase);\r
+extern void CANRetrySet(unsigned long ulBase, tBoolean bAutoRetry);\r
+extern tBoolean CANErrCntrGet(unsigned long ulBase, unsigned long *pulRxCount,\r
+ unsigned long *pulTxCount);\r
+extern long CANGetIntNumber(unsigned long ulBase);\r
+extern void CANReadDataReg(unsigned char *pucData, unsigned long *pulRegister,\r
+ int iSize);\r
+extern void CANWriteDataReg(unsigned char *pucData, unsigned long *pulRegister,\r
+ int iSize);\r
+\r
+//*****************************************************************************\r
+//\r
+// Close the Doxygen group.\r
+//! @}\r
+//\r
+//*****************************************************************************\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __CAN_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// comp.h - Prototypes for the analog comparator driver.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __COMP_H__\r
+#define __COMP_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to ComparatorConfigure() as the ulConfig\r
+// parameter. For each group (i.e. COMP_TRIG_xxx, COMP_INT_xxx, etc.), one of\r
+// the values may be selected and ORed together will values from the other\r
+// groups.\r
+//\r
+//*****************************************************************************\r
+#define COMP_TRIG_NONE 0x00000000 // No ADC trigger\r
+#define COMP_TRIG_HIGH 0x00000880 // Trigger when high\r
+#define COMP_TRIG_LOW 0x00000800 // Trigger when low\r
+#define COMP_TRIG_FALL 0x00000820 // Trigger on falling edge\r
+#define COMP_TRIG_RISE 0x00000840 // Trigger on rising edge\r
+#define COMP_TRIG_BOTH 0x00000860 // Trigger on both edges\r
+#define COMP_INT_HIGH 0x00000010 // Interrupt when high\r
+#define COMP_INT_LOW 0x00000000 // Interrupt when low\r
+#define COMP_INT_FALL 0x00000004 // Interrupt on falling edge\r
+#define COMP_INT_RISE 0x00000008 // Interrupt on rising edge\r
+#define COMP_INT_BOTH 0x0000000C // Interrupt on both edges\r
+#define COMP_ASRCP_PIN 0x00000000 // Dedicated Comp+ pin\r
+#define COMP_ASRCP_PIN0 0x00000200 // Comp0+ pin\r
+#define COMP_ASRCP_REF 0x00000400 // Internal voltage reference\r
+#ifndef DEPRECATED\r
+#define COMP_OUTPUT_NONE 0x00000000 // No comparator output\r
+#endif\r
+#define COMP_OUTPUT_NORMAL 0x00000000 // Comparator output normal\r
+#define COMP_OUTPUT_INVERT 0x00000002 // Comparator output inverted\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to ComparatorSetRef() as the ulRef parameter.\r
+//\r
+//*****************************************************************************\r
+#define COMP_REF_OFF 0x00000000 // Turn off the internal reference\r
+#define COMP_REF_0V 0x00000300 // Internal reference of 0V\r
+#define COMP_REF_0_1375V 0x00000301 // Internal reference of 0.1375V\r
+#define COMP_REF_0_275V 0x00000302 // Internal reference of 0.275V\r
+#define COMP_REF_0_4125V 0x00000303 // Internal reference of 0.4125V\r
+#define COMP_REF_0_55V 0x00000304 // Internal reference of 0.55V\r
+#define COMP_REF_0_6875V 0x00000305 // Internal reference of 0.6875V\r
+#define COMP_REF_0_825V 0x00000306 // Internal reference of 0.825V\r
+#define COMP_REF_0_928125V 0x00000201 // Internal reference of 0.928125V\r
+#define COMP_REF_0_9625V 0x00000307 // Internal reference of 0.9625V\r
+#define COMP_REF_1_03125V 0x00000202 // Internal reference of 1.03125V\r
+#define COMP_REF_1_134375V 0x00000203 // Internal reference of 1.134375V\r
+#define COMP_REF_1_1V 0x00000308 // Internal reference of 1.1V\r
+#define COMP_REF_1_2375V 0x00000309 // Internal reference of 1.2375V\r
+#define COMP_REF_1_340625V 0x00000205 // Internal reference of 1.340625V\r
+#define COMP_REF_1_375V 0x0000030A // Internal reference of 1.375V\r
+#define COMP_REF_1_44375V 0x00000206 // Internal reference of 1.44375V\r
+#define COMP_REF_1_5125V 0x0000030B // Internal reference of 1.5125V\r
+#define COMP_REF_1_546875V 0x00000207 // Internal reference of 1.546875V\r
+#define COMP_REF_1_65V 0x0000030C // Internal reference of 1.65V\r
+#define COMP_REF_1_753125V 0x00000209 // Internal reference of 1.753125V\r
+#define COMP_REF_1_7875V 0x0000030D // Internal reference of 1.7875V\r
+#define COMP_REF_1_85625V 0x0000020A // Internal reference of 1.85625V\r
+#define COMP_REF_1_925V 0x0000030E // Internal reference of 1.925V\r
+#define COMP_REF_1_959375V 0x0000020B // Internal reference of 1.959375V\r
+#define COMP_REF_2_0625V 0x0000030F // Internal reference of 2.0625V\r
+#define COMP_REF_2_165625V 0x0000020D // Internal reference of 2.165625V\r
+#define COMP_REF_2_26875V 0x0000020E // Internal reference of 2.26875V\r
+#define COMP_REF_2_371875V 0x0000020F // Internal reference of 2.371875V\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+extern void ComparatorConfigure(unsigned long ulBase, unsigned long ulComp,\r
+ unsigned long ulConfig);\r
+extern void ComparatorRefSet(unsigned long ulBase, unsigned long ulRef);\r
+extern tBoolean ComparatorValueGet(unsigned long ulBase, unsigned long ulComp);\r
+extern void ComparatorIntRegister(unsigned long ulBase, unsigned long ulComp,\r
+ void (*pfnHandler)(void));\r
+extern void ComparatorIntUnregister(unsigned long ulBase,\r
+ unsigned long ulComp);\r
+extern void ComparatorIntEnable(unsigned long ulBase, unsigned long ulComp);\r
+extern void ComparatorIntDisable(unsigned long ulBase, unsigned long ulComp);\r
+extern tBoolean ComparatorIntStatus(unsigned long ulBase, unsigned long ulComp,\r
+ tBoolean bMasked);\r
+extern void ComparatorIntClear(unsigned long ulBase, unsigned long ulComp);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __COMP_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// cpu.h - Prototypes for the CPU instruction wrapper functions.\r
+//\r
+// Copyright (c) 2006-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __CPU_H__\r
+#define __CPU_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes.\r
+//\r
+//*****************************************************************************\r
+extern void CPUcpsid(void);\r
+extern void CPUcpsie(void);\r
+extern void CPUwfi(void);\r
+\r
+#endif // __CPU_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// debug.h - Macros for assisting debug of the driver library.\r
+//\r
+// Copyright (c) 2006-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __DEBUG_H__\r
+#define __DEBUG_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototype for the function that is called when an invalid argument is passed\r
+// to an API. This is only used when doing a DEBUG build.\r
+//\r
+//*****************************************************************************\r
+extern void __error__(char *pcFilename, unsigned long ulLine);\r
+\r
+//*****************************************************************************\r
+//\r
+// The ASSERT macro, which does the actual assertion checking. Typically, this\r
+// will be for procedure arguments.\r
+//\r
+//*****************************************************************************\r
+#ifdef DEBUG\r
+#define ASSERT(expr) { \\r
+ if(!(expr)) \\r
+ { \\r
+ __error__(__FILE__, __LINE__); \\r
+ } \\r
+ }\r
+#else\r
+#define ASSERT(expr)\r
+#endif\r
+\r
+#endif // __DEBUG_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// ethernet.h - Defines and Macros for the ethernet module.\r
+//\r
+// Copyright (c) 2006-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __ETHERNET_H__\r
+#define __ETHERNET_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to EthernetConfigSet as the ulConfig value, and\r
+// returned from EthernetConfigGet.\r
+//\r
+//*****************************************************************************\r
+#define ETH_CFG_RX_BADCRCDIS 0x000800 // Disable RX BAD CRC Packets\r
+#define ETH_CFG_RX_PRMSEN 0x000400 // Enable RX Promiscuous\r
+#define ETH_CFG_RX_AMULEN 0x000200 // Enable RX Multicast\r
+#define ETH_CFG_TX_DPLXEN 0x000010 // Enable TX Duplex Mode\r
+#define ETH_CFG_TX_CRCEN 0x000004 // Enable TX CRC Generation\r
+#define ETH_CFG_TX_PADEN 0x000002 // Enable TX Padding\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to EthernetIntEnable, EthernetIntDisable, and\r
+// EthernetIntClear as the ulIntFlags parameter, and returned from\r
+// EthernetIntStatus.\r
+//\r
+//*****************************************************************************\r
+#define ETH_INT_PHY 0x040 // PHY Event/Interrupt\r
+#define ETH_INT_MDIO 0x020 // Management Transaction\r
+#define ETH_INT_RXER 0x010 // RX Error\r
+#define ETH_INT_RXOF 0x008 // RX FIFO Overrun\r
+#define ETH_INT_TX 0x004 // TX Complete\r
+#define ETH_INT_TXER 0x002 // TX Error\r
+#define ETH_INT_RX 0x001 // RX Complete\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define values that can be passed as register addresses to\r
+// EthernetPHYRead and EthernetPHYWrite.\r
+//\r
+//*****************************************************************************\r
+#define PHY_MR0 0 // Control\r
+#define PHY_MR1 1 // Status\r
+#define PHY_MR2 2 // PHY Identifier 1\r
+#define PHY_MR3 3 // PHY Identifier 2\r
+#define PHY_MR4 4 // Auto-Neg. Advertisement\r
+#define PHY_MR5 5 // Auto-Neg. Link Partner Ability\r
+#define PHY_MR6 6 // Auto-Neg. Expansion\r
+ // 7-15 Reserved/Not Implemented\r
+#define PHY_MR16 16 // Vendor Specific\r
+#define PHY_MR17 17 // Interrupt Control/Status\r
+#define PHY_MR18 18 // Diagnostic Register\r
+#define PHY_MR19 19 // Transceiver Control\r
+ // 20-22 Reserved\r
+#define PHY_MR23 23 // LED Configuration Register\r
+#define PHY_MR24 24 // MDI/MDIX Control Register\r
+ // 25-31 Reserved/Not Implemented\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define bit fields in the ETH_MR0 register\r
+//\r
+//*****************************************************************************\r
+#define PHY_MR0_RESET 0x8000 // Reset the PHY\r
+#define PHY_MR0_LOOPBK 0x4000 // TXD to RXD Loopback\r
+#define PHY_MR0_SPEEDSL 0x2000 // Speed Selection\r
+#define PHY_MR0_SPEEDSL_10 0x0000 // Speed Selection 10BASE-T\r
+#define PHY_MR0_SPEEDSL_100 0x2000 // Speed Selection 100BASE-T\r
+#define PHY_MR0_ANEGEN 0x1000 // Auto-Negotiation Enable\r
+#define PHY_MR0_PWRDN 0x0800 // Power Down\r
+#define PHY_MR0_RANEG 0x0200 // Restart Auto-Negotiation\r
+#define PHY_MR0_DUPLEX 0x0100 // Enable full duplex\r
+#define PHY_MR0_DUPLEX_HALF 0x0000 // Enable half duplex mode\r
+#define PHY_MR0_DUPLEX_FULL 0x0100 // Enable full duplex mode\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define bit fields in the ETH_MR1 register\r
+//\r
+//*****************************************************************************\r
+#define PHY_MR1_ANEGC 0x0020 // Auto-Negotiate Complete\r
+#define PHY_MR1_RFAULT 0x0010 // Remove Fault Detected\r
+#define PHY_MR1_LINK 0x0004 // Link Established\r
+#define PHY_MR1_JAB 0x0002 // Jabber Condition Detected\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define bit fields in the ETH_MR17 register\r
+//\r
+//*****************************************************************************\r
+#define PHY_MR17_RXER_IE 0x4000 // Enable Receive Error Interrupt\r
+#define PHY_MR17_LSCHG_IE 0x0400 // Enable Link Status Change Int.\r
+#define PHY_MR17_ANEGCOMP_IE 0x0100 // Enable Auto-Negotiate Cmpl. Int.\r
+#define PHY_MR17_RXER_INT 0x0040 // Receive Error Interrupt\r
+#define PHY_MR17_LSCHG_INT 0x0004 // Link Status Change Interrupt\r
+#define PHY_MR17_ANEGCOMP_INT 0x0001 // Auto-Negotiate Complete Int.\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define bit fields in the ETH_MR18 register\r
+//\r
+//*****************************************************************************\r
+#define PHY_MR18_ANEGF 0x1000 // Auto-Negotiate Failed\r
+#define PHY_MR18_DPLX 0x0800 // Duplex Mode Negotiated\r
+#define PHY_MR18_DPLX_HALF 0x0000 // Half Duplex Mode Negotiated\r
+#define PHY_MR18_DPLX_FULL 0x0800 // Full Duplex Mode Negotiated\r
+#define PHY_MR18_RATE 0x0400 // Rate Negotiated\r
+#define PHY_MR18_RATE_10 0x0000 // Rate Negotiated is 10BASE-T\r
+#define PHY_MR18_RATE_100 0x0400 // Rate Negotiated is 100BASE-TX\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define bit fields in the ETH_MR23 register\r
+//\r
+//*****************************************************************************\r
+#define PHY_MR23_LED1 0x00f0 // LED1 Configuration\r
+#define PHY_MR23_LED1_LINK 0x0000 // LED1 is Link Status\r
+#define PHY_MR23_LED1_RXTX 0x0010 // LED1 is RX or TX Activity\r
+#define PHY_MR23_LED1_TX 0x0020 // LED1 is TX Activity\r
+#define PHY_MR23_LED1_RX 0x0030 // LED1 is RX Activity\r
+#define PHY_MR23_LED1_COL 0x0040 // LED1 is RX Activity\r
+#define PHY_MR23_LED1_100 0x0050 // LED1 is RX Activity\r
+#define PHY_MR23_LED1_10 0x0060 // LED1 is RX Activity\r
+#define PHY_MR23_LED1_DUPLEX 0x0070 // LED1 is RX Activity\r
+#define PHY_MR23_LED1_LINKACT 0x0080 // LED1 is Link Status + Activity\r
+#define PHY_MR23_LED0 0x000f // LED0 Configuration\r
+#define PHY_MR23_LED0_LINK 0x0000 // LED0 is Link Status\r
+#define PHY_MR23_LED0_RXTX 0x0001 // LED0 is RX or TX Activity\r
+#define PHY_MR23_LED0_TX 0x0002 // LED0 is TX Activity\r
+#define PHY_MR23_LED0_RX 0x0003 // LED0 is RX Activity\r
+#define PHY_MR23_LED0_COL 0x0004 // LED0 is RX Activity\r
+#define PHY_MR23_LED0_100 0x0005 // LED0 is RX Activity\r
+#define PHY_MR23_LED0_10 0x0006 // LED0 is RX Activity\r
+#define PHY_MR23_LED0_DUPLEX 0x0007 // LED0 is RX Activity\r
+#define PHY_MR23_LED0_LINKACT 0x0008 // LED0 is Link Status + Activity\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define bit fields in the ETH_MR24 register\r
+//\r
+//*****************************************************************************\r
+#define PHY_MR24_MDIX 0x0020 // Auto-Switching Configuration\r
+#define PHY_MR24_MDIX_NORMAL 0x0000 // Auto-Switching in passthrough\r
+#define PHY_MR23_MDIX_CROSSOVER 0x0020 // Auto-Switching in crossover\r
+\r
+//*****************************************************************************\r
+//\r
+// Helper Macros for Ethernet Processing\r
+//\r
+//*****************************************************************************\r
+//\r
+// htonl/ntohl - big endian/little endian byte swapping macros for\r
+// 32-bit (long) values\r
+//\r
+//*****************************************************************************\r
+#ifndef htonl\r
+ #define htonl(a) \\r
+ ((((a) >> 24) & 0x000000ff) | \\r
+ (((a) >> 8) & 0x0000ff00) | \\r
+ (((a) << 8) & 0x00ff0000) | \\r
+ (((a) << 24) & 0xff000000))\r
+#endif\r
+\r
+#ifndef ntohl\r
+ #define ntohl(a) htonl((a))\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// htons/ntohs - big endian/little endian byte swapping macros for\r
+// 16-bit (short) values\r
+//\r
+//*****************************************************************************\r
+#ifndef htons\r
+ #define htons(a) \\r
+ ((((a) >> 8) & 0x00ff) | \\r
+ (((a) << 8) & 0xff00))\r
+#endif\r
+\r
+#ifndef ntohs\r
+ #define ntohs(a) htons((a))\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// API Function prototypes\r
+//\r
+//*****************************************************************************\r
+extern void EthernetInit(unsigned long ulBase);\r
+extern void EthernetConfigSet(unsigned long ulBase, unsigned long ulConfig);\r
+extern unsigned long EthernetConfigGet(unsigned long ulBase);\r
+extern void EthernetMACAddrSet(unsigned long ulBase,\r
+ unsigned char *pucMACAddr);\r
+extern void EthernetMACAddrGet(unsigned long ulBase,\r
+ unsigned char *pucMACAddr);\r
+extern void EthernetEnable(unsigned long ulBase);\r
+extern void EthernetDisable(unsigned long ulBase);\r
+extern tBoolean EthernetPacketAvail(unsigned long ulBase);\r
+extern tBoolean EthernetSpaceAvail(unsigned long ulBase);\r
+extern long EthernetPacketNonBlockingGet(unsigned long ulBase,\r
+ unsigned char *pucBuf,\r
+ long lBufLen);\r
+extern long EthernetPacketGet(unsigned long ulBase, unsigned char *pucBuf,\r
+ long lBufLen);\r
+extern long EthernetPacketNonBlockingPut(unsigned long ulBase,\r
+ unsigned char *pucBuf,\r
+ long lBufLen);\r
+extern long EthernetPacketPut(unsigned long ulBase, unsigned char *pucBuf,\r
+ long lBufLen);\r
+extern void EthernetIntRegister(unsigned long ulBase,\r
+ void (*pfnHandler)(void));\r
+extern void EthernetIntUnregister(unsigned long ulBase);\r
+extern void EthernetIntEnable(unsigned long ulBase, unsigned long ulIntFlags);\r
+extern void EthernetIntDisable(unsigned long ulBase, unsigned long ulIntFlags);\r
+extern unsigned long EthernetIntStatus(unsigned long ulBase, tBoolean bMasked);\r
+extern void EthernetIntClear(unsigned long ulBase, unsigned long ulIntFlags);\r
+extern void EthernetPHYWrite(unsigned long ulBase, unsigned char ucRegAddr,\r
+ unsigned long ulData);\r
+extern unsigned long EthernetPHYRead(unsigned long ulBase,\r
+ unsigned char ucRegAddr);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __ETHERNET_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// gpio.h - Defines and Macros for GPIO API.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __GPIO_H__\r
+#define __GPIO_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// The following values define the bit field for the ucPins argument to several\r
+// of the APIs.\r
+//\r
+//*****************************************************************************\r
+#define GPIO_PIN_0 0x00000001 // GPIO pin 0\r
+#define GPIO_PIN_1 0x00000002 // GPIO pin 1\r
+#define GPIO_PIN_2 0x00000004 // GPIO pin 2\r
+#define GPIO_PIN_3 0x00000008 // GPIO pin 3\r
+#define GPIO_PIN_4 0x00000010 // GPIO pin 4\r
+#define GPIO_PIN_5 0x00000020 // GPIO pin 5\r
+#define GPIO_PIN_6 0x00000040 // GPIO pin 6\r
+#define GPIO_PIN_7 0x00000080 // GPIO pin 7\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to GPIODirModeSet as the ulPinIO parameter, and\r
+// returned from GPIODirModeGet.\r
+//\r
+//*****************************************************************************\r
+#define GPIO_DIR_MODE_IN 0x00000000 // Pin is a GPIO input\r
+#define GPIO_DIR_MODE_OUT 0x00000001 // Pin is a GPIO output\r
+#define GPIO_DIR_MODE_HW 0x00000002 // Pin is a peripheral function\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to GPIOIntTypeSet as the ulIntType parameter, and\r
+// returned from GPIOIntTypeGet.\r
+//\r
+//*****************************************************************************\r
+#define GPIO_FALLING_EDGE 0x00000000 // Interrupt on falling edge\r
+#define GPIO_RISING_EDGE 0x00000004 // Interrupt on rising edge\r
+#define GPIO_BOTH_EDGES 0x00000001 // Interrupt on both edges\r
+#define GPIO_LOW_LEVEL 0x00000002 // Interrupt on low level\r
+#define GPIO_HIGH_LEVEL 0x00000007 // Interrupt on high level\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to GPIOPadConfigSet as the ulStrength parameter,\r
+// and returned by GPIOPadConfigGet in the *pulStrength parameter.\r
+//\r
+//*****************************************************************************\r
+#define GPIO_STRENGTH_2MA 0x00000001 // 2mA drive strength\r
+#define GPIO_STRENGTH_4MA 0x00000002 // 4mA drive strength\r
+#define GPIO_STRENGTH_8MA 0x00000004 // 8mA drive strength\r
+#define GPIO_STRENGTH_8MA_SC 0x0000000C // 8mA drive with slew rate control\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to GPIOPadConfigSet as the ulPadType parameter,\r
+// and returned by GPIOPadConfigGet in the *pulPadType parameter.\r
+//\r
+//*****************************************************************************\r
+#define GPIO_PIN_TYPE_STD 0x00000008 // Push-pull\r
+#define GPIO_PIN_TYPE_STD_WPU 0x0000000A // Push-pull with weak pull-up\r
+#define GPIO_PIN_TYPE_STD_WPD 0x0000000C // Push-pull with weak pull-down\r
+#define GPIO_PIN_TYPE_OD 0x00000009 // Open-drain\r
+#define GPIO_PIN_TYPE_OD_WPU 0x0000000B // Open-drain with weak pull-up\r
+#define GPIO_PIN_TYPE_OD_WPD 0x0000000D // Open-drain with weak pull-down\r
+#define GPIO_PIN_TYPE_ANALOG 0x00000000 // Analog comparator\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+extern void GPIODirModeSet(unsigned long ulPort, unsigned char ucPins,\r
+ unsigned long ulPinIO);\r
+extern unsigned long GPIODirModeGet(unsigned long ulPort, unsigned char ucPin);\r
+extern void GPIOIntTypeSet(unsigned long ulPort, unsigned char ucPins,\r
+ unsigned long ulIntType);\r
+extern unsigned long GPIOIntTypeGet(unsigned long ulPort, unsigned char ucPin);\r
+extern void GPIOPadConfigSet(unsigned long ulPort, unsigned char ucPins,\r
+ unsigned long ulStrength,\r
+ unsigned long ulPadType);\r
+extern void GPIOPadConfigGet(unsigned long ulPort, unsigned char ucPin,\r
+ unsigned long *pulStrength,\r
+ unsigned long *pulPadType);\r
+extern void GPIOPinIntEnable(unsigned long ulPort, unsigned char ucPins);\r
+extern void GPIOPinIntDisable(unsigned long ulPort, unsigned char ucPins);\r
+extern long GPIOPinIntStatus(unsigned long ulPort, tBoolean bMasked);\r
+extern void GPIOPinIntClear(unsigned long ulPort, unsigned char ucPins);\r
+extern void GPIOPortIntRegister(unsigned long ulPort,\r
+ void (*pfIntHandler)(void));\r
+extern void GPIOPortIntUnregister(unsigned long ulPort);\r
+extern long GPIOPinRead(unsigned long ulPort, unsigned char ucPins);\r
+extern void GPIOPinWrite(unsigned long ulPort, unsigned char ucPins,\r
+ unsigned char ucVal);\r
+extern void GPIOPinTypeComparator(unsigned long ulPort, unsigned char ucPins);\r
+extern void GPIOPinTypeI2C(unsigned long ulPort, unsigned char ucPins);\r
+extern void GPIOPinTypePWM(unsigned long ulPort, unsigned char ucPins);\r
+extern void GPIOPinTypeQEI(unsigned long ulPort, unsigned char ucPins);\r
+extern void GPIOPinTypeSSI(unsigned long ulPort, unsigned char ucPins);\r
+extern void GPIOPinTypeTimer(unsigned long ulPort, unsigned char ucPins);\r
+extern void GPIOPinTypeUART(unsigned long ulPort, unsigned char ucPins);\r
+extern void GPIOPinTypeCAN(unsigned long ulPort, unsigned char ucPins);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __GPIO_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hibernate.h - API definition for the Hibernation module.\r
+//\r
+// Copyright (c) 2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HIBERNATE_H__\r
+#define __HIBERNATE_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Macros needed for selecting the clock source for HibernateClockSelect()\r
+//\r
+//*****************************************************************************\r
+#define HIBERNATE_CLOCK_SEL_RAW 0x04\r
+#define HIBERNATE_CLOCK_SEL_DIV128 0x00\r
+\r
+//*****************************************************************************\r
+//\r
+// Macros need to configure wake events for HibernateWakeSet()\r
+//\r
+//*****************************************************************************\r
+#define HIBERNATE_WAKE_PIN 0x10\r
+#define HIBERNATE_WAKE_RTC 0x08\r
+\r
+//*****************************************************************************\r
+//\r
+// Macros needed to configure low battery detect for HibernateLowBatSet()\r
+//\r
+//*****************************************************************************\r
+#define HIBERNATE_LOW_BAT_DETECT 0x20\r
+#define HIBERNATE_LOW_BAT_ABORT 0xA0\r
+\r
+//*****************************************************************************\r
+//\r
+// Macros defining interrupt source bits for the interrupt functions.\r
+//\r
+//*****************************************************************************\r
+#define HIBERNATE_INT_PIN_WAKE 0x08\r
+#define HIBERNATE_INT_LOW_BAT 0x04\r
+#define HIBERNATE_INT_RTC_MATCH_0 0x01\r
+#define HIBERNATE_INT_RTC_MATCH_1 0x02\r
+\r
+//*****************************************************************************\r
+//\r
+// API Function prototypes\r
+//\r
+//*****************************************************************************\r
+extern void HibernateEnable(void);\r
+extern void HibernateDisable(void);\r
+extern void HibernateClockSelect(unsigned long ulClockInput);\r
+extern void HibernateRTCEnable(void);\r
+extern void HibernateRTCDisable(void);\r
+extern void HibernateWakeSet(unsigned long ulWakeFlags);\r
+extern unsigned long HibernateWakeGet(void);\r
+extern void HibernateLowBatSet(unsigned long ulLowBatFlags);\r
+extern unsigned long HibernateLowBatGet(void);\r
+extern void HibernateRTCSet(unsigned long ulRTCValue);\r
+extern unsigned long HibernateRTCGet(void);\r
+extern void HibernateRTCMatch0Set(unsigned long ulMatch);\r
+extern unsigned long HibernateRTCMatch0Get(void);\r
+extern void HibernateRTCMatch1Set(unsigned long ulMatch);\r
+extern unsigned long HibernateRTCMatch1Get(void);\r
+extern void HibernateRTCTrimSet(unsigned long ulTrim);\r
+extern unsigned long HibernateRTCTrimGet(void);\r
+extern void HibernateDataSet(unsigned long *pulData, unsigned long ulCount);\r
+extern void HibernateDataGet(unsigned long *pulData, unsigned long ulCount);\r
+extern void HibernateRequest(void);\r
+extern void HibernateIntEnable(unsigned long ulIntFlags);\r
+extern void HibernateIntDisable(unsigned long ulIntFlags);\r
+extern void HibernateIntRegister(void (*pfnHandler)(void));\r
+extern void HibernateIntUnregister(void);\r
+extern unsigned long HibernateIntStatus(tBoolean bMasked);\r
+extern void HibernateIntClear(unsigned long ulIntFlags);\r
+extern unsigned int HibernateIsActive(void);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __HIBERNATE_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_adc.h - Macros used when accessing the ADC hardware.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_ADC_H__\r
+#define __HW_ADC_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the offsets of the ADC registers.\r
+//\r
+//*****************************************************************************\r
+#define ADC_O_ACTSS 0x00000000 // Active sample register\r
+#define ADC_O_RIS 0x00000004 // Raw interrupt status register\r
+#define ADC_O_IM 0x00000008 // Interrupt mask register\r
+#define ADC_O_ISC 0x0000000C // Interrupt status/clear register\r
+#define ADC_O_OSTAT 0x00000010 // Overflow status register\r
+#define ADC_O_EMUX 0x00000014 // Event multiplexer select reg.\r
+#define ADC_O_USTAT 0x00000018 // Underflow status register\r
+#define ADC_O_SSPRI 0x00000020 // Channel priority register\r
+#define ADC_O_PSSI 0x00000028 // Processor sample initiate reg.\r
+#define ADC_O_SAC 0x00000030 // Sample Averaging Control reg.\r
+#define ADC_O_SSMUX0 0x00000040 // Multiplexer select 0 register\r
+#define ADC_O_SSCTL0 0x00000044 // Sample sequence control 0 reg.\r
+#define ADC_O_SSFIFO0 0x00000048 // Result FIFO 0 register\r
+#define ADC_O_SSFSTAT0 0x0000004C // FIFO 0 status register\r
+#define ADC_O_SSMUX1 0x00000060 // Multiplexer select 1 register\r
+#define ADC_O_SSCTL1 0x00000064 // Sample sequence control 1 reg.\r
+#define ADC_O_SSFIFO1 0x00000068 // Result FIFO 1 register\r
+#define ADC_O_SSFSTAT1 0x0000006C // FIFO 1 status register\r
+#define ADC_O_SSMUX2 0x00000080 // Multiplexer select 2 register\r
+#define ADC_O_SSCTL2 0x00000084 // Sample sequence control 2 reg.\r
+#define ADC_O_SSFIFO2 0x00000088 // Result FIFO 2 register\r
+#define ADC_O_SSFSTAT2 0x0000008C // FIFO 2 status register\r
+#define ADC_O_SSMUX3 0x000000A0 // Multiplexer select 3 register\r
+#define ADC_O_SSCTL3 0x000000A4 // Sample sequence control 3 reg.\r
+#define ADC_O_SSFIFO3 0x000000A8 // Result FIFO 3 register\r
+#define ADC_O_SSFSTAT3 0x000000AC // FIFO 3 status register\r
+#define ADC_O_TMLB 0x00000100 // Test mode loopback register\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the offsets of the ADC sequence registers.\r
+//\r
+//*****************************************************************************\r
+#define ADC_O_SEQ 0x00000040 // Offset to the first sequence\r
+#define ADC_O_SEQ_STEP 0x00000020 // Increment to the next sequence\r
+#define ADC_O_X_SSMUX 0x00000000 // Multiplexer select register\r
+#define ADC_O_X_SSCTL 0x00000004 // Sample sequence control register\r
+#define ADC_O_X_SSFIFO 0x00000008 // Result FIFO register\r
+#define ADC_O_X_SSFSTAT 0x0000000C // FIFO status register\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the ADC_ACTSS register.\r
+//\r
+//*****************************************************************************\r
+#define ADC_ACTSS_ASEN3 0x00000008 // Sample sequence 3 enable\r
+#define ADC_ACTSS_ASEN2 0x00000004 // Sample sequence 2 enable\r
+#define ADC_ACTSS_ASEN1 0x00000002 // Sample sequence 1 enable\r
+#define ADC_ACTSS_ASEN0 0x00000001 // Sample sequence 0 enable\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the ADC_RIS register.\r
+//\r
+//*****************************************************************************\r
+#define ADC_RIS_INR3 0x00000008 // Sample sequence 3 interrupt\r
+#define ADC_RIS_INR2 0x00000004 // Sample sequence 2 interrupt\r
+#define ADC_RIS_INR1 0x00000002 // Sample sequence 1 interrupt\r
+#define ADC_RIS_INR0 0x00000001 // Sample sequence 0 interrupt\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the ADC_IM register.\r
+//\r
+//*****************************************************************************\r
+#define ADC_IM_MASK3 0x00000008 // Sample sequence 3 mask\r
+#define ADC_IM_MASK2 0x00000004 // Sample sequence 2 mask\r
+#define ADC_IM_MASK1 0x00000002 // Sample sequence 1 mask\r
+#define ADC_IM_MASK0 0x00000001 // Sample sequence 0 mask\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the ADC_ISC register.\r
+//\r
+//*****************************************************************************\r
+#define ADC_ISC_IN3 0x00000008 // Sample sequence 3 interrupt\r
+#define ADC_ISC_IN2 0x00000004 // Sample sequence 2 interrupt\r
+#define ADC_ISC_IN1 0x00000002 // Sample sequence 1 interrupt\r
+#define ADC_ISC_IN0 0x00000001 // Sample sequence 0 interrupt\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the ADC_OSTAT register.\r
+//\r
+//*****************************************************************************\r
+#define ADC_OSTAT_OV3 0x00000008 // Sample sequence 3 overflow\r
+#define ADC_OSTAT_OV2 0x00000004 // Sample sequence 2 overflow\r
+#define ADC_OSTAT_OV1 0x00000002 // Sample sequence 1 overflow\r
+#define ADC_OSTAT_OV0 0x00000001 // Sample sequence 0 overflow\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the ADC_EMUX register.\r
+//\r
+//*****************************************************************************\r
+#define ADC_EMUX_EM3_MASK 0x0000F000 // Event mux 3 mask\r
+#define ADC_EMUX_EM3_PROCESSOR 0x00000000 // Processor event\r
+#define ADC_EMUX_EM3_COMP0 0x00001000 // Analog comparator 0 event\r
+#define ADC_EMUX_EM3_COMP1 0x00002000 // Analog comparator 1 event\r
+#define ADC_EMUX_EM3_COMP2 0x00003000 // Analog comparator 2 event\r
+#define ADC_EMUX_EM3_EXTERNAL 0x00004000 // External event\r
+#define ADC_EMUX_EM3_TIMER 0x00005000 // Timer event\r
+#define ADC_EMUX_EM3_PWM0 0x00006000 // PWM0 event\r
+#define ADC_EMUX_EM3_PWM1 0x00007000 // PWM1 event\r
+#define ADC_EMUX_EM3_PWM2 0x00008000 // PWM2 event\r
+#define ADC_EMUX_EM3_ALWAYS 0x0000F000 // Always event\r
+#define ADC_EMUX_EM2_MASK 0x00000F00 // Event mux 2 mask\r
+#define ADC_EMUX_EM2_PROCESSOR 0x00000000 // Processor event\r
+#define ADC_EMUX_EM2_COMP0 0x00000100 // Analog comparator 0 event\r
+#define ADC_EMUX_EM2_COMP1 0x00000200 // Analog comparator 1 event\r
+#define ADC_EMUX_EM2_COMP2 0x00000300 // Analog comparator 2 event\r
+#define ADC_EMUX_EM2_EXTERNAL 0x00000400 // External event\r
+#define ADC_EMUX_EM2_TIMER 0x00000500 // Timer event\r
+#define ADC_EMUX_EM2_PWM0 0x00000600 // PWM0 event\r
+#define ADC_EMUX_EM2_PWM1 0x00000700 // PWM1 event\r
+#define ADC_EMUX_EM2_PWM2 0x00000800 // PWM2 event\r
+#define ADC_EMUX_EM2_ALWAYS 0x00000F00 // Always event\r
+#define ADC_EMUX_EM1_MASK 0x000000F0 // Event mux 1 mask\r
+#define ADC_EMUX_EM1_PROCESSOR 0x00000000 // Processor event\r
+#define ADC_EMUX_EM1_COMP0 0x00000010 // Analog comparator 0 event\r
+#define ADC_EMUX_EM1_COMP1 0x00000020 // Analog comparator 1 event\r
+#define ADC_EMUX_EM1_COMP2 0x00000030 // Analog comparator 2 event\r
+#define ADC_EMUX_EM1_EXTERNAL 0x00000040 // External event\r
+#define ADC_EMUX_EM1_TIMER 0x00000050 // Timer event\r
+#define ADC_EMUX_EM1_PWM0 0x00000060 // PWM0 event\r
+#define ADC_EMUX_EM1_PWM1 0x00000070 // PWM1 event\r
+#define ADC_EMUX_EM1_PWM2 0x00000080 // PWM2 event\r
+#define ADC_EMUX_EM1_ALWAYS 0x000000F0 // Always event\r
+#define ADC_EMUX_EM0_MASK 0x0000000F // Event mux 0 mask\r
+#define ADC_EMUX_EM0_PROCESSOR 0x00000000 // Processor event\r
+#define ADC_EMUX_EM0_COMP0 0x00000001 // Analog comparator 0 event\r
+#define ADC_EMUX_EM0_COMP1 0x00000002 // Analog comparator 1 event\r
+#define ADC_EMUX_EM0_COMP2 0x00000003 // Analog comparator 2 event\r
+#define ADC_EMUX_EM0_EXTERNAL 0x00000004 // External event\r
+#define ADC_EMUX_EM0_TIMER 0x00000005 // Timer event\r
+#define ADC_EMUX_EM0_PWM0 0x00000006 // PWM0 event\r
+#define ADC_EMUX_EM0_PWM1 0x00000007 // PWM1 event\r
+#define ADC_EMUX_EM0_PWM2 0x00000008 // PWM2 event\r
+#define ADC_EMUX_EM0_ALWAYS 0x0000000F // Always event\r
+#define ADC_EMUX_EM0_SHIFT 0 // The shift for the first event\r
+#define ADC_EMUX_EM1_SHIFT 4 // The shift for the second event\r
+#define ADC_EMUX_EM2_SHIFT 8 // The shift for the third event\r
+#define ADC_EMUX_EM3_SHIFT 12 // The shift for the fourth event\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the ADC_USTAT register.\r
+//\r
+//*****************************************************************************\r
+#define ADC_USTAT_UV3 0x00000008 // Sample sequence 3 underflow\r
+#define ADC_USTAT_UV2 0x00000004 // Sample sequence 2 underflow\r
+#define ADC_USTAT_UV1 0x00000002 // Sample sequence 1 underflow\r
+#define ADC_USTAT_UV0 0x00000001 // Sample sequence 0 underflow\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the ADC_SSPRI register.\r
+//\r
+//*****************************************************************************\r
+#define ADC_SSPRI_SS3_MASK 0x00003000 // Sequencer 3 priority mask\r
+#define ADC_SSPRI_SS3_1ST 0x00000000 // First priority\r
+#define ADC_SSPRI_SS3_2ND 0x00001000 // Second priority\r
+#define ADC_SSPRI_SS3_3RD 0x00002000 // Third priority\r
+#define ADC_SSPRI_SS3_4TH 0x00003000 // Fourth priority\r
+#define ADC_SSPRI_SS2_MASK 0x00000300 // Sequencer 2 priority mask\r
+#define ADC_SSPRI_SS2_1ST 0x00000000 // First priority\r
+#define ADC_SSPRI_SS2_2ND 0x00000100 // Second priority\r
+#define ADC_SSPRI_SS2_3RD 0x00000200 // Third priority\r
+#define ADC_SSPRI_SS2_4TH 0x00000300 // Fourth priority\r
+#define ADC_SSPRI_SS1_MASK 0x00000030 // Sequencer 1 priority mask\r
+#define ADC_SSPRI_SS1_1ST 0x00000000 // First priority\r
+#define ADC_SSPRI_SS1_2ND 0x00000010 // Second priority\r
+#define ADC_SSPRI_SS1_3RD 0x00000020 // Third priority\r
+#define ADC_SSPRI_SS1_4TH 0x00000030 // Fourth priority\r
+#define ADC_SSPRI_SS0_MASK 0x00000003 // Sequencer 0 priority mask\r
+#define ADC_SSPRI_SS0_1ST 0x00000000 // First priority\r
+#define ADC_SSPRI_SS0_2ND 0x00000001 // Second priority\r
+#define ADC_SSPRI_SS0_3RD 0x00000002 // Third priority\r
+#define ADC_SSPRI_SS0_4TH 0x00000003 // Fourth priority\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the ADC_PSSI register.\r
+//\r
+//*****************************************************************************\r
+#define ADC_PSSI_SS3 0x00000008 // Trigger sample sequencer 3\r
+#define ADC_PSSI_SS2 0x00000004 // Trigger sample sequencer 2\r
+#define ADC_PSSI_SS1 0x00000002 // Trigger sample sequencer 1\r
+#define ADC_PSSI_SS0 0x00000001 // Trigger sample sequencer 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the ADC_SAC register.\r
+//\r
+//*****************************************************************************\r
+#define ADC_SAC_AVG_OFF 0x00000000 // No hardware oversampling\r
+#define ADC_SAC_AVG_2X 0x00000001 // 2x hardware oversampling\r
+#define ADC_SAC_AVG_4X 0x00000002 // 4x hardware oversampling\r
+#define ADC_SAC_AVG_8X 0x00000003 // 8x hardware oversampling\r
+#define ADC_SAC_AVG_16X 0x00000004 // 16x hardware oversampling\r
+#define ADC_SAC_AVG_32X 0x00000005 // 32x hardware oversampling\r
+#define ADC_SAC_AVG_64X 0x00000006 // 64x hardware oversampling\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the ADC_SSMUX0, ADC_SSMUX1,\r
+// ADC_SSMUX2, and ADC_SSMUX3 registers. Not all fields are present in all\r
+// registers.\r
+//\r
+//*****************************************************************************\r
+#define ADC_SSMUX_MUX7_MASK 0x70000000 // 8th mux select mask\r
+#define ADC_SSMUX_MUX6_MASK 0x07000000 // 7th mux select mask\r
+#define ADC_SSMUX_MUX5_MASK 0x00700000 // 6th mux select mask\r
+#define ADC_SSMUX_MUX4_MASK 0x00070000 // 5th mux select mask\r
+#define ADC_SSMUX_MUX3_MASK 0x00007000 // 4th mux select mask\r
+#define ADC_SSMUX_MUX2_MASK 0x00000700 // 3rd mux select mask\r
+#define ADC_SSMUX_MUX1_MASK 0x00000070 // 2nd mux select mask\r
+#define ADC_SSMUX_MUX0_MASK 0x00000007 // 1st mux select mask\r
+#define ADC_SSMUX_MUX7_SHIFT 28\r
+#define ADC_SSMUX_MUX6_SHIFT 24\r
+#define ADC_SSMUX_MUX5_SHIFT 20\r
+#define ADC_SSMUX_MUX4_SHIFT 16\r
+#define ADC_SSMUX_MUX3_SHIFT 12\r
+#define ADC_SSMUX_MUX2_SHIFT 8\r
+#define ADC_SSMUX_MUX1_SHIFT 4\r
+#define ADC_SSMUX_MUX0_SHIFT 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the ADC_SSCTL0, ADC_SSCTL1,\r
+// ADC_SSCTL2, and ADC_SSCTL3 registers. Not all fields are present in all\r
+// registers.\r
+//\r
+//*****************************************************************************\r
+#define ADC_SSCTL_TS7 0x80000000 // 8th temperature sensor select\r
+#define ADC_SSCTL_IE7 0x40000000 // 8th interrupt enable\r
+#define ADC_SSCTL_END7 0x20000000 // 8th sequence end select\r
+#define ADC_SSCTL_D7 0x10000000 // 8th differential select\r
+#define ADC_SSCTL_TS6 0x08000000 // 7th temperature sensor select\r
+#define ADC_SSCTL_IE6 0x04000000 // 7th interrupt enable\r
+#define ADC_SSCTL_END6 0x02000000 // 7th sequence end select\r
+#define ADC_SSCTL_D6 0x01000000 // 7th differential select\r
+#define ADC_SSCTL_TS5 0x00800000 // 6th temperature sensor select\r
+#define ADC_SSCTL_IE5 0x00400000 // 6th interrupt enable\r
+#define ADC_SSCTL_END5 0x00200000 // 6th sequence end select\r
+#define ADC_SSCTL_D5 0x00100000 // 6th differential select\r
+#define ADC_SSCTL_TS4 0x00080000 // 5th temperature sensor select\r
+#define ADC_SSCTL_IE4 0x00040000 // 5th interrupt enable\r
+#define ADC_SSCTL_END4 0x00020000 // 5th sequence end select\r
+#define ADC_SSCTL_D4 0x00010000 // 5th differential select\r
+#define ADC_SSCTL_TS3 0x00008000 // 4th temperature sensor select\r
+#define ADC_SSCTL_IE3 0x00004000 // 4th interrupt enable\r
+#define ADC_SSCTL_END3 0x00002000 // 4th sequence end select\r
+#define ADC_SSCTL_D3 0x00001000 // 4th differential select\r
+#define ADC_SSCTL_TS2 0x00000800 // 3rd temperature sensor select\r
+#define ADC_SSCTL_IE2 0x00000400 // 3rd interrupt enable\r
+#define ADC_SSCTL_END2 0x00000200 // 3rd sequence end select\r
+#define ADC_SSCTL_D2 0x00000100 // 3rd differential select\r
+#define ADC_SSCTL_TS1 0x00000080 // 2nd temperature sensor select\r
+#define ADC_SSCTL_IE1 0x00000040 // 2nd interrupt enable\r
+#define ADC_SSCTL_END1 0x00000020 // 2nd sequence end select\r
+#define ADC_SSCTL_D1 0x00000010 // 2nd differential select\r
+#define ADC_SSCTL_TS0 0x00000008 // 1st temperature sensor select\r
+#define ADC_SSCTL_IE0 0x00000004 // 1st interrupt enable\r
+#define ADC_SSCTL_END0 0x00000002 // 1st sequence end select\r
+#define ADC_SSCTL_D0 0x00000001 // 1st differential select\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the ADC_SSFIFO0, ADC_SSFIFO1,\r
+// ADC_SSFIFO2, and ADC_SSFIFO3 registers.\r
+//\r
+//*****************************************************************************\r
+#define ADC_SSFIFO_DATA_MASK 0x000003FF // Sample data\r
+#define ADC_SSFIFO_DATA_SHIFT 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the ADC_SSFSTAT0, ADC_SSFSTAT1,\r
+// ADC_SSFSTAT2, and ADC_SSFSTAT3 registers.\r
+//\r
+//*****************************************************************************\r
+#define ADC_SSFSTAT_FULL 0x00001000 // FIFO is full\r
+#define ADC_SSFSTAT_EMPTY 0x00000100 // FIFO is empty\r
+#define ADC_SSFSTAT_HPTR 0x000000F0 // FIFO head pointer\r
+#define ADC_SSFSTAT_TPTR 0x0000000F // FIFO tail pointer\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the ADC_TMLB register.\r
+//\r
+//*****************************************************************************\r
+#define ADC_TMLB_LB 0x00000001 // Loopback control signals\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the loopback ADC data.\r
+//\r
+//*****************************************************************************\r
+#define ADC_LB_CNT_MASK 0x000003C0 // Sample counter mask\r
+#define ADC_LB_CONT 0x00000020 // Continuation sample\r
+#define ADC_LB_DIFF 0x00000010 // Differential sample\r
+#define ADC_LB_TS 0x00000008 // Temperature sensor sample\r
+#define ADC_LB_MUX_MASK 0x00000007 // Input channel number mask\r
+#define ADC_LB_CNT_SHIFT 6 // Sample counter shift\r
+#define ADC_LB_MUX_SHIFT 0 // Input channel number shift\r
+\r
+#endif // __HW_ADC_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_can.h - Defines and macros used when accessing the can.\r
+//\r
+// Copyright (c) 2006-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_CAN_H__\r
+#define __HW_CAN_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the offsets of the can registers.\r
+//\r
+//*****************************************************************************\r
+#define CAN_O_CTL 0x00000000 // Control register\r
+#define CAN_O_STS 0x00000004 // Status register\r
+#define CAN_O_ERR 0x00000008 // Error register\r
+#define CAN_O_BIT 0x0000000C // Bit Timing register\r
+#define CAN_O_INT 0x00000010 // Interrupt register\r
+#define CAN_O_TST 0x00000014 // Test register\r
+#define CAN_O_BRPE 0x00000018 // Baud Rate Prescaler register\r
+#define CAN_O_IF1CRQ 0x00000020 // Interface 1 Command Request reg.\r
+#define CAN_O_IF1CMSK 0x00000024 // Interface 1 Command Mask reg.\r
+#define CAN_O_IF1MSK1 0x00000028 // Interface 1 Mask 1 register\r
+#define CAN_O_IF1MSK2 0x0000002C // Interface 1 Mask 2 register\r
+#define CAN_O_IF1ARB1 0x00000030 // Interface 1 Arbitration 1 reg.\r
+#define CAN_O_IF1ARB2 0x00000034 // Interface 1 Arbitration 2 reg.\r
+#define CAN_O_IF1MCTL 0x00000038 // Interface 1 Message Control reg.\r
+#define CAN_O_IF1DA1 0x0000003C // Interface 1 DataA 1 register\r
+#define CAN_O_IF1DA2 0x00000040 // Interface 1 DataA 2 register\r
+#define CAN_O_IF1DB1 0x00000044 // Interface 1 DataB 1 register\r
+#define CAN_O_IF1DB2 0x00000048 // Interface 1 DataB 2 register\r
+#define CAN_O_IF2CRQ 0x00000080 // Interface 2 Command Request reg.\r
+#define CAN_O_IF2CMSK 0x00000084 // Interface 2 Command Mask reg.\r
+#define CAN_O_IF2MSK1 0x00000088 // Interface 2 Mask 1 register\r
+#define CAN_O_IF2MSK2 0x0000008C // Interface 2 Mask 2 register\r
+#define CAN_O_IF2ARB1 0x00000090 // Interface 2 Arbitration 1 reg.\r
+#define CAN_O_IF2ARB2 0x00000094 // Interface 2 Arbitration 2 reg.\r
+#define CAN_O_IF2MCTL 0x00000098 // Interface 2 Message Control reg.\r
+#define CAN_O_IF2DA1 0x0000009C // Interface 2 DataA 1 register\r
+#define CAN_O_IF2DA2 0x000000A0 // Interface 2 DataA 2 register\r
+#define CAN_O_IF2DB1 0x000000A4 // Interface 2 DataB 1 register\r
+#define CAN_O_IF2DB2 0x000000A8 // Interface 2 DataB 2 register\r
+#define CAN_O_TXRQ1 0x00000100 // Transmission Request 1 register\r
+#define CAN_O_TXRQ2 0x00000104 // Transmission Request 2 register\r
+#define CAN_O_NWDA1 0x00000120 // New Data 1 register\r
+#define CAN_O_NWDA2 0x00000124 // New Data 2 register\r
+#define CAN_O_MSGINT1 0x00000140 // Intr. Pending in Msg Obj 1 reg.\r
+#define CAN_O_MSGINT2 0x00000144 // Intr. Pending in Msg Obj 2 reg.\r
+#define CAN_O_MSGVAL1 0x00000160 // Message Valid in Msg Obj 1 reg.\r
+#define CAN_O_MSGVAL2 0x00000164 // Message Valid in Msg Obj 2 reg.\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the reset values of the can registers.\r
+//\r
+//*****************************************************************************\r
+#define CAN_RV_CTL 0x00000001\r
+#define CAN_RV_STS 0x00000000\r
+#define CAN_RV_ERR 0x00000000\r
+#define CAN_RV_BIT 0x00002301\r
+#define CAN_RV_INT 0x00000000\r
+#define CAN_RV_TST 0x00000000\r
+#define CAN_RV_BRPE 0x00000000\r
+#define CAN_RV_IF1CRQ 0x00000001\r
+#define CAN_RV_IF1CMSK 0x00000000\r
+#define CAN_RV_IF1MSK1 0x0000FFFF\r
+#define CAN_RV_IF1MSK2 0x0000FFFF\r
+#define CAN_RV_IF1ARB1 0x00000000\r
+#define CAN_RV_IF1ARB2 0x00000000\r
+#define CAN_RV_IF1MCTL 0x00000000\r
+#define CAN_RV_IF1DA1 0x00000000\r
+#define CAN_RV_IF1DA2 0x00000000\r
+#define CAN_RV_IF1DB1 0x00000000\r
+#define CAN_RV_IF1DB2 0x00000000\r
+#define CAN_RV_IF2CRQ 0x00000001\r
+#define CAN_RV_IF2CMSK 0x00000000\r
+#define CAN_RV_IF2MSK1 0x0000FFFF\r
+#define CAN_RV_IF2MSK2 0x0000FFFF\r
+#define CAN_RV_IF2ARB1 0x00000000\r
+#define CAN_RV_IF2ARB2 0x00000000\r
+#define CAN_RV_IF2MCTL 0x00000000\r
+#define CAN_RV_IF2DA1 0x00000000\r
+#define CAN_RV_IF2DA2 0x00000000\r
+#define CAN_RV_IF2DB1 0x00000000\r
+#define CAN_RV_IF2DB2 0x00000000\r
+#define CAN_RV_TXRQ1 0x00000000\r
+#define CAN_RV_TXRQ2 0x00000000\r
+#define CAN_RV_NWDA1 0x00000000\r
+#define CAN_RV_NWDA2 0x00000000\r
+#define CAN_RV_MSGINT1 0x00000000\r
+#define CAN_RV_MSGINT2 0x00000000\r
+#define CAN_RV_MSGVAL1 0x00000000\r
+#define CAN_RV_MSGVAL2 0x00000000\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the CAN_CTL register.\r
+//\r
+//*****************************************************************************\r
+#define CAN_CTL_TEST 0x00000080 // Test mode enable\r
+#define CAN_CTL_CCE 0x00000040 // Configuration change enable\r
+#define CAN_CTL_DAR 0x00000020 // Disable automatic retransmission\r
+#define CAN_CTL_EIE 0x00000008 // Error interrupt enable\r
+#define CAN_CTL_SIE 0x00000004 // Status change interrupt enable\r
+#define CAN_CTL_IE 0x00000002 // Module interrupt enable\r
+#define CAN_CTL_INIT 0x00000001 // Initialization\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the CAN_STS register.\r
+//\r
+//*****************************************************************************\r
+#define CAN_STS_BOFF 0x00000080 // Bus Off status\r
+#define CAN_STS_EWARN 0x00000040 // Error Warning status\r
+#define CAN_STS_EPASS 0x00000020 // Error Passive status\r
+#define CAN_STS_RXOK 0x00000010 // Received Message Successful\r
+#define CAN_STS_TXOK 0x00000008 // Transmitted Message Successful\r
+#define CAN_STS_LEC_MSK 0x00000007 // Last Error Code\r
+#define CAN_STS_LEC_NONE 0x00000000 // No error\r
+#define CAN_STS_LEC_STUFF 0x00000001 // Stuff error\r
+#define CAN_STS_LEC_FORM 0x00000002 // Form(at) error\r
+#define CAN_STS_LEC_ACK 0x00000003 // Ack error\r
+#define CAN_STS_LEC_BIT1 0x00000004 // Bit 1 error\r
+#define CAN_STS_LEC_BIT0 0x00000005 // Bit 0 error\r
+#define CAN_STS_LEC_CRC 0x00000006 // CRC error\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the CAN_ERR register.\r
+//\r
+//*****************************************************************************\r
+#define CAN_ERR_RP 0x00008000 // Receive error passive status\r
+#define CAN_ERR_REC_MASK 0x00007F00 // Receive error counter status\r
+#define CAN_ERR_REC_SHIFT 8 // Receive error counter bit pos\r
+#define CAN_ERR_TEC_MASK 0x000000FF // Transmit error counter status\r
+#define CAN_ERR_TEC_SHIFT 0 // Transmit error counter bit pos\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the CAN_BIT register.\r
+//\r
+//*****************************************************************************\r
+#define CAN_BIT_TSEG2 0x00007000 // Time segment after sample point\r
+#define CAN_BIT_TSEG1 0x00000F00 // Time segment before sample point\r
+#define CAN_BIT_SJW 0x000000C0 // (Re)Synchronization jump width\r
+#define CAN_BIT_BRP 0x0000003F // Baud rate prescaler\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the CAN_INT register.\r
+//\r
+//*****************************************************************************\r
+#define CAN_INT_INTID_MSK 0x0000FFFF // Interrupt Identifier\r
+#define CAN_INT_INTID_NONE 0x00000000 // No Interrupt Pending\r
+#define CAN_INT_INTID_STATUS 0x00008000 // Status Interrupt\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the CAN_TST register.\r
+//\r
+//*****************************************************************************\r
+#define CAN_TST_RX 0x00000080 // CAN_RX pin status\r
+#define CAN_TST_TX_MSK 0x00000060 // Overide control of CAN_TX pin\r
+#define CAN_TST_TX_CANCTL 0x00000000 // CAN core controls CAN_TX\r
+#define CAN_TST_TX_SAMPLE 0x00000020 // Sample Point on CAN_TX\r
+#define CAN_TST_TX_DOMINANT 0x00000040 // Dominant value on CAN_TX\r
+#define CAN_TST_TX_RECESSIVE 0x00000060 // Recessive value on CAN_TX\r
+#define CAN_TST_LBACK 0x00000010 // Loop back mode\r
+#define CAN_TST_SILENT 0x00000008 // Silent mode\r
+#define CAN_TST_BASIC 0x00000004 // Basic mode\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the CAN_BRPE register.\r
+//\r
+//*****************************************************************************\r
+#define CAN_BRPE_BRPE 0x0000000F // Baud rate prescaler extension\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the CAN_IF1CRQ and CAN_IF1CRQ\r
+// registers.\r
+// Note: All bits may not be available in all registers\r
+//\r
+//*****************************************************************************\r
+#define CAN_IFCRQ_BUSY 0x00008000 // Busy flag status\r
+#define CAN_IFCRQ_MNUM_MSK 0x0000003F // Message Number\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the CAN_IF1CMSK and CAN_IF2CMSK\r
+// registers.\r
+// Note: All bits may not be available in all registers\r
+//\r
+//*****************************************************************************\r
+#define CAN_IFCMSK_WRNRD 0x00000080 // Write, not Read\r
+#define CAN_IFCMSK_MASK 0x00000040 // Access Mask Bits\r
+#define CAN_IFCMSK_ARB 0x00000020 // Access Arbitration Bits\r
+#define CAN_IFCMSK_CONTROL 0x00000010 // Access Control Bits\r
+#define CAN_IFCMSK_CLRINTPND 0x00000008 // Clear interrupt pending Bit\r
+#define CAN_IFCMSK_TXRQST 0x00000004 // Access Tx request bit (WRNRD=1)\r
+#define CAN_IFCMSK_NEWDAT 0x00000004 // Access New Data bit (WRNRD=0)\r
+#define CAN_IFCMSK_DATAA 0x00000002 // DataA access - bytes 0 to 3\r
+#define CAN_IFCMSK_DATAB 0x00000001 // DataB access - bytes 4 to 7\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the CAN_IF1MSK1 and CAN_IF2MSK1\r
+// registers.\r
+// Note: All bits may not be available in all registers\r
+//\r
+//*****************************************************************************\r
+#define CAN_IFMSK1_MSK 0x0000FFFF // Identifier Mask\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the CAN_IF1MSK2 and CAN_IF2MSK2\r
+// registers.\r
+// Note: All bits may not be available in all registers\r
+//\r
+//*****************************************************************************\r
+#define CAN_IFMSK2_MXTD 0x00008000 // Mask extended identifier\r
+#define CAN_IFMSK2_MDIR 0x00004000 // Mask message direction\r
+#define CAN_IFMSK2_MSK 0x00001FFF // Mask identifier\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the CAN_IF1ARB1 and CAN_IF2ARB1\r
+// registers.\r
+// Note: All bits may not be available in all registers\r
+//\r
+//*****************************************************************************\r
+#define CAN_IFARB1_ID 0x0000FFFF // Identifier\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the CAN_IF1ARB2 and CAN_IF2ARB2\r
+// registers.\r
+// Note: All bits may not be available in all registers\r
+//\r
+//*****************************************************************************\r
+#define CAN_IFARB2_MSGVAL 0x00008000 // Message valid\r
+#define CAN_IFARB2_XTD 0x00004000 // Extended identifier\r
+#define CAN_IFARB2_DIR 0x00002000 // Message direction\r
+#define CAN_IFARB2_ID 0x00001FFF // Message identifier\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the CAN_IF1MCTL and CAN_IF2MCTL\r
+// registers.\r
+// Note: All bits may not be available in all registers\r
+//\r
+//*****************************************************************************\r
+#define CAN_IFMCTL_NEWDAT 0x00008000 // New Data\r
+#define CAN_IFMCTL_MSGLST 0x00004000 // Message lost\r
+#define CAN_IFMCTL_INTPND 0x00002000 // Interrupt pending\r
+#define CAN_IFMCTL_UMASK 0x00001000 // Use acceptance mask\r
+#define CAN_IFMCTL_TXIE 0x00000800 // Transmit interrupt enable\r
+#define CAN_IFMCTL_RXIE 0x00000400 // Receive interrupt enable\r
+#define CAN_IFMCTL_RMTEN 0x00000200 // Remote enable\r
+#define CAN_IFMCTL_TXRQST 0x00000100 // Transmit request\r
+#define CAN_IFMCTL_EOB 0x00000080 // End of buffer\r
+#define CAN_IFMCTL_DLC 0x0000000F // Data length code\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the CAN_IF1DA1 and CAN_IF2DA1\r
+// registers.\r
+// Note: All bits may not be available in all registers\r
+//\r
+//*****************************************************************************\r
+#define CAN_IFDA1_DATA 0x0000FFFF // Data - bytes 1 and 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the CAN_IF1DA2 and CAN_IF2DA2\r
+// registers.\r
+// Note: All bits may not be available in all registers\r
+//\r
+//*****************************************************************************\r
+#define CAN_IFDA2_DATA 0x0000FFFF // Data - bytes 3 and 2\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the CAN_IF1DB1 and CAN_IF2DB1\r
+// registers.\r
+// Note: All bits may not be available in all registers\r
+//\r
+//*****************************************************************************\r
+#define CAN_IFDB1_DATA 0x0000FFFF // Data - bytes 5 and 4\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the CAN_IF1DB2 and CAN_IF2DB2\r
+// registers.\r
+// Note: All bits may not be available in all registers\r
+//\r
+//*****************************************************************************\r
+#define CAN_IFDB2_DATA 0x0000FFFF // Data - bytes 7 and 6\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the CAN_TXRQ1 register.\r
+//\r
+//*****************************************************************************\r
+#define CAN_TXRQ1_TXRQST 0x0000FFFF // Transmission Request Bits\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the CAN_TXRQ2 register.\r
+//\r
+//*****************************************************************************\r
+#define CAN_TXRQ2_TXRQST 0x0000FFFF // Transmission Request Bits\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the CAN_NWDA1 register.\r
+//\r
+//*****************************************************************************\r
+#define CAN_NWDA1_NEWDATA 0x0000FFFF // New Data Bits\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the CAN_NWDA2 register.\r
+//\r
+//*****************************************************************************\r
+#define CAN_NWDA2_NEWDATA 0x0000FFFF // New Data Bits\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the CAN_MSGINT1 register.\r
+//\r
+//*****************************************************************************\r
+#define CAN_MSGINT1_INTPND 0x0000FFFF // Interrupt Pending Bits\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the CAN_MSGINT2 register.\r
+//\r
+//*****************************************************************************\r
+#define CAN_MSGINT2_INTPND 0x0000FFFF // Interrupt Pending Bits\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the CAN_MSGVAL1 register.\r
+//\r
+//*****************************************************************************\r
+#define CAN_MSGVAL1_MSGVAL 0x0000FFFF // Message Valid Bits\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the CAN_MSGVAL2 register.\r
+//\r
+//*****************************************************************************\r
+#define CAN_MSGVAL2_MSGVAL 0x0000FFFF // Message Valid Bits\r
+\r
+#endif // __HW_CAN_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_comp.h - Macros used when accessing the comparator hardware.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_COMP_H__\r
+#define __HW_COMP_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the offsets of the comparator registers.\r
+//\r
+//*****************************************************************************\r
+#define COMP_O_MIS 0x00000000 // Interrupt status register\r
+#define COMP_O_RIS 0x00000004 // Raw interrupt status register\r
+#define COMP_O_INTEN 0x00000008 // Interrupt enable register\r
+#define COMP_O_REFCTL 0x00000010 // Reference voltage control reg.\r
+#define COMP_O_ACSTAT0 0x00000020 // Comp0 status register\r
+#define COMP_O_ACCTL0 0x00000024 // Comp0 control register\r
+#define COMP_O_ACSTAT1 0x00000040 // Comp1 status register\r
+#define COMP_O_ACCTL1 0x00000044 // Comp1 control register\r
+#define COMP_O_ACSTAT2 0x00000060 // Comp2 status register\r
+#define COMP_O_ACCTL2 0x00000064 // Comp2 control register\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the COMP_MIS, COMP_RIS, and\r
+// COMP_INTEN registers.\r
+//\r
+//*****************************************************************************\r
+#define COMP_INT_2 0x00000004 // Comp2 interrupt\r
+#define COMP_INT_1 0x00000002 // Comp1 interrupt\r
+#define COMP_INT_0 0x00000001 // Comp0 interrupt\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the COMP_REFCTL register.\r
+//\r
+//*****************************************************************************\r
+#define COMP_REFCTL_EN 0x00000200 // Reference voltage enable\r
+#define COMP_REFCTL_RNG 0x00000100 // Reference voltage range\r
+#define COMP_REFCTL_VREF_MASK 0x0000000F // Reference voltage select mask\r
+#define COMP_REFCTL_VREF_SHIFT 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the COMP_ACSTAT0, COMP_ACSTAT1, and\r
+// COMP_ACSTAT2 registers.\r
+//\r
+//*****************************************************************************\r
+#define COMP_ACSTAT_OVAL 0x00000002 // Comparator output value\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the COMP_ACCTL0, COMP_ACCTL1, and\r
+// COMP_ACCTL2 registers.\r
+//\r
+//*****************************************************************************\r
+#define COMP_ACCTL_TMASK 0x00000800 // Trigger enable\r
+#define COMP_ACCTL_ASRCP_MASK 0x00000600 // Vin+ source select mask\r
+#define COMP_ACCTL_ASRCP_PIN 0x00000000 // Dedicated Comp+ pin\r
+#define COMP_ACCTL_ASRCP_PIN0 0x00000200 // Comp0+ pin\r
+#define COMP_ACCTL_ASRCP_REF 0x00000400 // Internal voltage reference\r
+#define COMP_ACCTL_ASRCP_RES 0x00000600 // Reserved\r
+#define COMP_ACCTL_OEN 0x00000100 // Comparator output enable\r
+#define COMP_ACCTL_TSVAL 0x00000080 // Trigger polarity select\r
+#define COMP_ACCTL_TSEN_MASK 0x00000060 // Trigger sense mask\r
+#define COMP_ACCTL_TSEN_LEVEL 0x00000000 // Trigger is level sense\r
+#define COMP_ACCTL_TSEN_FALL 0x00000020 // Trigger is falling edge\r
+#define COMP_ACCTL_TSEN_RISE 0x00000040 // Trigger is rising edge\r
+#define COMP_ACCTL_TSEN_BOTH 0x00000060 // Trigger is both edges\r
+#define COMP_ACCTL_ISLVAL 0x00000010 // Interrupt polarity select\r
+#define COMP_ACCTL_ISEN_MASK 0x0000000C // Interrupt sense mask\r
+#define COMP_ACCTL_ISEN_LEVEL 0x00000000 // Interrupt is level sense\r
+#define COMP_ACCTL_ISEN_FALL 0x00000004 // Interrupt is falling edge\r
+#define COMP_ACCTL_ISEN_RISE 0x00000008 // Interrupt is rising edge\r
+#define COMP_ACCTL_ISEN_BOTH 0x0000000C // Interrupt is both edges\r
+#define COMP_ACCTL_CINV 0x00000002 // Comparator output invert\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the reset values for the comparator registers.\r
+//\r
+//*****************************************************************************\r
+#define COMP_RV_MIS 0x00000000 // Interrupt status register\r
+#define COMP_RV_RIS 0x00000000 // Raw interrupt status register\r
+#define COMP_RV_INTEN 0x00000000 // Interrupt enable register\r
+#define COMP_RV_REFCTL 0x00000000 // Reference voltage control reg.\r
+#define COMP_RV_ACSTAT0 0x00000000 // Comp0 status register\r
+#define COMP_RV_ACCTL0 0x00000000 // Comp0 control register\r
+#define COMP_RV_ACSTAT1 0x00000000 // Comp1 status register\r
+#define COMP_RV_ACCTL1 0x00000000 // Comp1 control register\r
+#define COMP_RV_ACSTAT2 0x00000000 // Comp2 status register\r
+#define COMP_RV_ACCTL2 0x00000000 // Comp2 control register\r
+\r
+#endif // __HW_COMP_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_ethernet.h - Macros used when accessing the ethernet hardware.\r
+//\r
+// Copyright (c) 2006-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_ETHERNET_H__\r
+#define __HW_ETHERNET_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the offsets of the MAC registers in the Ethernet\r
+// Controller.\r
+//\r
+//*****************************************************************************\r
+#define MAC_O_IS 0x00000000 // Interrupt Status Register\r
+#define MAC_O_IACK 0x00000000 // Interrupt Acknowledge Register\r
+#define MAC_O_IM 0x00000004 // Interrupt Mask Register\r
+#define MAC_O_RCTL 0x00000008 // Receive Control Register\r
+#define MAC_O_TCTL 0x0000000C // Transmit Control Register\r
+#define MAC_O_DATA 0x00000010 // Data Register\r
+#define MAC_O_IA0 0x00000014 // Individual Address Register 0\r
+#define MAC_O_IA1 0x00000018 // Individual Address Register 1\r
+#define MAC_O_THR 0x0000001C // Threshold Register\r
+#define MAC_O_MCTL 0x00000020 // Management Control Register\r
+#define MAC_O_MDV 0x00000024 // Management Divider Register\r
+#define MAC_O_MADD 0x00000028 // Management Address Register\r
+#define MAC_O_MTXD 0x0000002C // Management Transmit Data Reg\r
+#define MAC_O_MRXD 0x00000030 // Management Receive Data Reg\r
+#define MAC_O_NP 0x00000034 // Number of Packets Register\r
+#define MAC_O_TR 0x00000038 // Transmission Request Register\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the reset values of the MAC registers.\r
+//\r
+//*****************************************************************************\r
+#define MAC_RV_IS 0x00000000\r
+#define MAC_RV_IACK 0x00000000\r
+#define MAC_RV_IM 0x0000007F\r
+#define MAC_RV_RCTL 0x00000008\r
+#define MAC_RV_TCTL 0x00000000\r
+#define MAC_RV_DATA 0x00000000\r
+#define MAC_RV_IA0 0x00000000\r
+#define MAC_RV_IA1 0x00000000\r
+#define MAC_RV_THR 0x0000003F\r
+#define MAC_RV_MCTL 0x00000000\r
+#define MAC_RV_MDV 0x00000080\r
+#define MAC_RV_MADD 0x00000000\r
+#define MAC_RV_MTXD 0x00000000\r
+#define MAC_RV_MRXD 0x00000000\r
+#define MAC_RV_NP 0x00000000\r
+#define MAC_RV_TR 0x00000000\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the MAC_IS register.\r
+//\r
+//*****************************************************************************\r
+#define MAC_IS_PHYINT 0x00000040 // PHY Interrupt\r
+#define MAC_IS_MDINT 0x00000020 // MDI Transaction Complete\r
+#define MAC_IS_RXER 0x00000010 // RX Error\r
+#define MAC_IS_FOV 0x00000008 // RX FIFO Overrun\r
+#define MAC_IS_TXEMP 0x00000004 // TX FIFO Empy\r
+#define MAC_IS_TXER 0x00000002 // TX Error\r
+#define MAC_IS_RXINT 0x00000001 // RX Packet Available\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the MAC_IACK register.\r
+//\r
+//*****************************************************************************\r
+#define MAC_IACK_PHYINT 0x00000040 // Clear PHY Interrupt\r
+#define MAC_IACK_MDINT 0x00000020 // Clear MDI Transaction Complete\r
+#define MAC_IACK_RXER 0x00000010 // Clear RX Error\r
+#define MAC_IACK_FOV 0x00000008 // Clear RX FIFO Overrun\r
+#define MAC_IACK_TXEMP 0x00000004 // Clear TX FIFO Empy\r
+#define MAC_IACK_TXER 0x00000002 // Clear TX Error\r
+#define MAC_IACK_RXINT 0x00000001 // Clear RX Packet Available\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the MAC_IM register.\r
+//\r
+//*****************************************************************************\r
+#define MAC_IM_PHYINTM 0x00000040 // Mask PHY Interrupt\r
+#define MAC_IM_MDINTM 0x00000020 // Mask MDI Transaction Complete\r
+#define MAC_IM_RXERM 0x00000010 // Mask RX Error\r
+#define MAC_IM_FOVM 0x00000008 // Mask RX FIFO Overrun\r
+#define MAC_IM_TXEMPM 0x00000004 // Mask TX FIFO Empy\r
+#define MAC_IM_TXERM 0x00000002 // Mask TX Error\r
+#define MAC_IM_RXINTM 0x00000001 // Mask RX Packet Available\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the MAC_RCTL register.\r
+//\r
+//*****************************************************************************\r
+#define MAC_RCTL_RSTFIFO 0x00000010 // Clear the Receive FIFO\r
+#define MAC_RCTL_BADCRC 0x00000008 // Reject Packets With Bad CRC\r
+#define MAC_RCTL_PRMS 0x00000004 // Enable Promiscuous Mode\r
+#define MAC_RCTL_AMUL 0x00000002 // Enable Multicast Packets\r
+#define MAC_RCTL_RXEN 0x00000001 // Enable Ethernet Receiver\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the MAC_TCTL register.\r
+//\r
+//*****************************************************************************\r
+#define MAC_TCTL_DUPLEX 0x00000010 // Enable Duplex mode\r
+#define MAC_TCTL_CRC 0x00000004 // Enable CRC Generation\r
+#define MAC_TCTL_PADEN 0x00000002 // Enable Automatic Padding\r
+#define MAC_TCTL_TXEN 0x00000001 // Enable Ethernet Transmitter\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the MAC_IA0 register.\r
+//\r
+//*****************************************************************************\r
+#define MAC_IA0_MACOCT4 0xFF000000 // 4th Octet of MAC address\r
+#define MAC_IA0_MACOCT3 0x00FF0000 // 3rd Octet of MAC address\r
+#define MAC_IA0_MACOCT2 0x0000FF00 // 2nd Octet of MAC address\r
+#define MAC_IA0_MACOCT1 0x000000FF // 1st Octet of MAC address\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the MAC_IA1 register.\r
+//\r
+//*****************************************************************************\r
+#define MAC_IA1_MACOCT6 0x0000FF00 // 6th Octet of MAC address\r
+#define MAC_IA1_MACOCT5 0x000000FF // 5th Octet of MAC address\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the MAC_TXTH register.\r
+//\r
+//*****************************************************************************\r
+#define MAC_THR_THRESH 0x0000003F // Transmit Threshold Value\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the MAC_MCTL register.\r
+//\r
+//*****************************************************************************\r
+#define MAC_MCTL_REGADR 0x000000F8 // Address for Next MII Transaction\r
+#define MAC_MCTL_WRITE 0x00000002 // Next MII Transaction is Write\r
+#define MAC_MCTL_START 0x00000001 // Start MII Transaction\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the MAC_MDV register.\r
+//\r
+//*****************************************************************************\r
+#define MAC_MDV_DIV 0x000000FF // Clock Divider for MDC for TX\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the MAC_MTXD register.\r
+//\r
+//*****************************************************************************\r
+#define MAC_MTXD_MDTX 0x0000FFFF // Data for Next MII Transaction\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the MAC_MRXD register.\r
+//\r
+//*****************************************************************************\r
+#define MAC_MRXD_MDRX 0x0000FFFF // Data Read from Last MII Trans.\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the MAC_NP register.\r
+//\r
+//*****************************************************************************\r
+#define MAC_NP_NPR 0x0000003F // Number of RX Frames in FIFO\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the MAC_TXRQ register.\r
+//\r
+//*****************************************************************************\r
+#define MAC_TR_NEWTX 0x00000001 // Start an Ethernet Transmission\r
+\r
+#endif // __HW_ETHERNET_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_flash.h - Macros used when accessing the flash controller.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_FLASH_H__\r
+#define __HW_FLASH_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the offsets of the FLASH registers.\r
+//\r
+//*****************************************************************************\r
+#define FLASH_FMA 0x400FD000 // Memory address register\r
+#define FLASH_FMD 0x400FD004 // Memory data register\r
+#define FLASH_FMC 0x400FD008 // Memory control register\r
+#define FLASH_FCRIS 0x400FD00c // Raw interrupt status register\r
+#define FLASH_FCIM 0x400FD010 // Interrupt mask register\r
+#define FLASH_FCMISC 0x400FD014 // Interrupt status register\r
+#define FLASH_FMPRE 0x400FE130 // FLASH read protect register\r
+#define FLASH_FMPPE 0x400FE134 // FLASH program protect register\r
+#define FLASH_USECRL 0x400FE140 // uSec reload register\r
+#define FLASH_FMPRE0 0x400FE200 // FLASH read protect register 0\r
+#define FLASH_FMPRE1 0x400FE204 // FLASH read protect register 1\r
+#define FLASH_FMPRE2 0x400FE208 // FLASH read protect register 2\r
+#define FLASH_FMPRE3 0x400FE20C // FLASH read protect register 3\r
+#define FLASH_FMPPE0 0x400FE400 // FLASH program protect register 0\r
+#define FLASH_FMPPE1 0x400FE404 // FLASH program protect register 1\r
+#define FLASH_FMPPE2 0x400FE408 // FLASH program protect register 2\r
+#define FLASH_FMPPE3 0x400FE40C // FLASH program protect register 3\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the FLASH_FMC register.\r
+//\r
+//*****************************************************************************\r
+#define FLASH_FMC_WRKEY_MASK 0xFFFF0000 // FLASH write key mask\r
+#define FLASH_FMC_WRKEY 0xA4420000 // FLASH write key\r
+#define FLASH_FMC_COMT 0x00000008 // Commit user register\r
+#define FLASH_FMC_MERASE 0x00000004 // Mass erase FLASH\r
+#define FLASH_FMC_ERASE 0x00000002 // Erase FLASH page\r
+#define FLASH_FMC_WRITE 0x00000001 // Write FLASH word\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the FLASH_FCRIS register.\r
+//\r
+//*****************************************************************************\r
+#define FLASH_FCRIS_PROGRAM 0x00000002 // Programming status\r
+#define FLASH_FCRIS_ACCESS 0x00000001 // Invalid access status\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the FLASH_FCIM register.\r
+//\r
+//*****************************************************************************\r
+#define FLASH_FCIM_PROGRAM 0x00000002 // Programming mask\r
+#define FLASH_FCIM_ACCESS 0x00000001 // Invalid access mask\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the FLASH_FMIS register.\r
+//\r
+//*****************************************************************************\r
+#define FLASH_FCMISC_PROGRAM 0x00000002 // Programming status\r
+#define FLASH_FCMISC_ACCESS 0x00000001 // Invalid access status\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the FLASH_FMPRE and FLASH_FMPPE\r
+// registers.\r
+//\r
+//*****************************************************************************\r
+#define FLASH_FMP_BLOCK_31 0x80000000 // Enable for block 31\r
+#define FLASH_FMP_BLOCK_30 0x40000000 // Enable for block 30\r
+#define FLASH_FMP_BLOCK_29 0x20000000 // Enable for block 29\r
+#define FLASH_FMP_BLOCK_28 0x10000000 // Enable for block 28\r
+#define FLASH_FMP_BLOCK_27 0x08000000 // Enable for block 27\r
+#define FLASH_FMP_BLOCK_26 0x04000000 // Enable for block 26\r
+#define FLASH_FMP_BLOCK_25 0x02000000 // Enable for block 25\r
+#define FLASH_FMP_BLOCK_24 0x01000000 // Enable for block 24\r
+#define FLASH_FMP_BLOCK_23 0x00800000 // Enable for block 23\r
+#define FLASH_FMP_BLOCK_22 0x00400000 // Enable for block 22\r
+#define FLASH_FMP_BLOCK_21 0x00200000 // Enable for block 21\r
+#define FLASH_FMP_BLOCK_20 0x00100000 // Enable for block 20\r
+#define FLASH_FMP_BLOCK_19 0x00080000 // Enable for block 19\r
+#define FLASH_FMP_BLOCK_18 0x00040000 // Enable for block 18\r
+#define FLASH_FMP_BLOCK_17 0x00020000 // Enable for block 17\r
+#define FLASH_FMP_BLOCK_16 0x00010000 // Enable for block 16\r
+#define FLASH_FMP_BLOCK_15 0x00008000 // Enable for block 15\r
+#define FLASH_FMP_BLOCK_14 0x00004000 // Enable for block 14\r
+#define FLASH_FMP_BLOCK_13 0x00002000 // Enable for block 13\r
+#define FLASH_FMP_BLOCK_12 0x00001000 // Enable for block 12\r
+#define FLASH_FMP_BLOCK_11 0x00000800 // Enable for block 11\r
+#define FLASH_FMP_BLOCK_10 0x00000400 // Enable for block 10\r
+#define FLASH_FMP_BLOCK_9 0x00000200 // Enable for block 9\r
+#define FLASH_FMP_BLOCK_8 0x00000100 // Enable for block 8\r
+#define FLASH_FMP_BLOCK_7 0x00000080 // Enable for block 7\r
+#define FLASH_FMP_BLOCK_6 0x00000040 // Enable for block 6\r
+#define FLASH_FMP_BLOCK_5 0x00000020 // Enable for block 5\r
+#define FLASH_FMP_BLOCK_4 0x00000010 // Enable for block 4\r
+#define FLASH_FMP_BLOCK_3 0x00000008 // Enable for block 3\r
+#define FLASH_FMP_BLOCK_2 0x00000004 // Enable for block 2\r
+#define FLASH_FMP_BLOCK_1 0x00000002 // Enable for block 1\r
+#define FLASH_FMP_BLOCK_0 0x00000001 // Enable for block 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the FLASH_USECRL register.\r
+//\r
+//*****************************************************************************\r
+#define FLASH_USECRL_MASK 0x000000FF // Clock per uSec\r
+#define FLASH_USECRL_SHIFT 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The erase size is the size of the FLASH block that is erased by an erase\r
+// operation, and the protect size is the size of the FLASH block that is\r
+// protected by each protection register.\r
+//\r
+//*****************************************************************************\r
+#define FLASH_ERASE_SIZE 0x00000400\r
+#define FLASH_PROTECT_SIZE 0x00000800\r
+\r
+#endif // __HW_FLASH_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_gpio.h - Defines and Macros for GPIO hardware.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_GPIO_H__\r
+#define __HW_GPIO_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// GPIO Register Offsets.\r
+//\r
+//*****************************************************************************\r
+#define GPIO_O_DATA 0x00000000 // Data register.\r
+#define GPIO_O_DIR 0x00000400 // Data direction register.\r
+#define GPIO_O_IS 0x00000404 // Interrupt sense register.\r
+#define GPIO_O_IBE 0x00000408 // Interrupt both edges register.\r
+#define GPIO_O_IEV 0x0000040C // Intterupt event register.\r
+#define GPIO_O_IM 0x00000410 // Interrupt mask register.\r
+#define GPIO_O_RIS 0x00000414 // Raw interrupt status register.\r
+#define GPIO_O_MIS 0x00000418 // Masked interrupt status reg.\r
+#define GPIO_O_ICR 0x0000041C // Interrupt clear register.\r
+#define GPIO_O_AFSEL 0x00000420 // Mode control select register.\r
+#define GPIO_O_DR2R 0x00000500 // 2ma drive select register.\r
+#define GPIO_O_DR4R 0x00000504 // 4ma drive select register.\r
+#define GPIO_O_DR8R 0x00000508 // 8ma drive select register.\r
+#define GPIO_O_ODR 0x0000050C // Open drain select register.\r
+#define GPIO_O_PUR 0x00000510 // Pull up select register.\r
+#define GPIO_O_PDR 0x00000514 // Pull down select register.\r
+#define GPIO_O_SLR 0x00000518 // Slew rate control enable reg.\r
+#define GPIO_O_DEN 0x0000051C // Digital input enable register.\r
+#define GPIO_O_LOCK 0x00000520 // Lock register.\r
+#define GPIO_O_CR 0x00000524 // Commit register.\r
+#define GPIO_O_PeriphID4 0x00000FD0 //\r
+#define GPIO_O_PeriphID5 0x00000FD4 //\r
+#define GPIO_O_PeriphID6 0x00000FD8 //\r
+#define GPIO_O_PeriphID7 0x00000FDC //\r
+#define GPIO_O_PeriphID0 0x00000FE0 //\r
+#define GPIO_O_PeriphID1 0x00000FE4 //\r
+#define GPIO_O_PeriphID2 0x00000FE8 //\r
+#define GPIO_O_PeriphID3 0x00000FEC //\r
+#define GPIO_O_PCellID0 0x00000FF0 //\r
+#define GPIO_O_PCellID1 0x00000FF4 //\r
+#define GPIO_O_PCellID2 0x00000FF8 //\r
+#define GPIO_O_PCellID3 0x00000FFC //\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the GPIO_LOCK register.\r
+//\r
+//*****************************************************************************\r
+#define GPIO_LOCK_LOCKED 0x00000001 // GPIO_CR register is locked\r
+#define GPIO_LOCK_UNLOCKED 0x00000000 // GPIO_CR register is unlocked\r
+#define GPIO_LOCK_KEY 0x1ACCE551 // Unlocks the GPIO_CR register\r
+\r
+//*****************************************************************************\r
+//\r
+// GPIO Register reset values.\r
+//\r
+//*****************************************************************************\r
+#define GPIO_RV_DATA 0x00000000 // Data register reset value.\r
+#define GPIO_RV_DIR 0x00000000 // Data direction reg RV.\r
+#define GPIO_RV_IS 0x00000000 // Interrupt sense reg RV.\r
+#define GPIO_RV_IBE 0x00000000 // Interrupt both edges reg RV.\r
+#define GPIO_RV_IEV 0x00000000 // Intterupt event reg RV.\r
+#define GPIO_RV_IM 0x00000000 // Interrupt mask reg RV.\r
+#define GPIO_RV_RIS 0x00000000 // Raw interrupt status reg RV.\r
+#define GPIO_RV_MIS 0x00000000 // Masked interrupt status reg RV.\r
+#define GPIO_RV_IC 0x00000000 // Interrupt clear reg RV.\r
+#define GPIO_RV_AFSEL 0x00000000 // Mode control select reg RV.\r
+#define GPIO_RV_DR2R 0x000000FF // 2ma drive select reg RV.\r
+#define GPIO_RV_DR4R 0x00000000 // 4ma drive select reg RV.\r
+#define GPIO_RV_DR8R 0x00000000 // 8ma drive select reg RV.\r
+#define GPIO_RV_ODR 0x00000000 // Open drain select reg RV.\r
+#define GPIO_RV_PUR 0x000000FF // Pull up select reg RV.\r
+#define GPIO_RV_PDR 0x00000000 // Pull down select reg RV.\r
+#define GPIO_RV_SLR 0x00000000 // Slew rate control enable reg RV.\r
+#define GPIO_RV_DEN 0x000000FF // Digital input enable reg RV.\r
+#define GPIO_RV_LOCK 0x00000001 // Lock register RV.\r
+#define GPIO_RV_PeriphID4 0x00000000 //\r
+#define GPIO_RV_PeriphID5 0x00000000 //\r
+#define GPIO_RV_PeriphID6 0x00000000 //\r
+#define GPIO_RV_PeriphID7 0x00000000 //\r
+#define GPIO_RV_PeriphID0 0x00000061 //\r
+#define GPIO_RV_PeriphID1 0x00000010 //\r
+#define GPIO_RV_PeriphID2 0x00000004 //\r
+#define GPIO_RV_PeriphID3 0x00000000 //\r
+#define GPIO_RV_PCellID0 0x0000000D //\r
+#define GPIO_RV_PCellID1 0x000000F0 //\r
+#define GPIO_RV_PCellID2 0x00000005 //\r
+#define GPIO_RV_PCellID3 0x000000B1 //\r
+\r
+#endif // __HW_GPIO_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_hibernate.h - Defines and Macros for the Hibernation module.\r
+//\r
+// Copyright (c) 2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_HIBERNATE_H__\r
+#define __HW_HIBERNATE_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the addresses of the hibernation module registers.\r
+//\r
+//*****************************************************************************\r
+#define HIB_RTCC 0x400fc000 // Hibernate RTC counter\r
+#define HIB_RTCM0 0x400fc004 // Hibernate RTC match 0\r
+#define HIB_RTCM1 0x400fc008 // Hibernate RTC match 1\r
+#define HIB_RTCLD 0x400fc00C // Hibernate RTC load\r
+#define HIB_CTL 0x400fc010 // Hibernate RTC control\r
+#define HIB_IM 0x400fc014 // Hibernate interrupt mask\r
+#define HIB_RIS 0x400fc018 // Hibernate raw interrupt status\r
+#define HIB_MIS 0x400fc01C // Hibernate masked interrupt stat\r
+#define HIB_IC 0x400fc020 // Hibernate interrupt clear\r
+#define HIB_RTCT 0x400fc024 // Hibernate RTC trim\r
+#define HIB_DATA 0x400fc030 // Hibernate data area\r
+#define HIB_DATA_END 0x400fc130 // end of data area, exclusive\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the Hibernate RTC counter register.\r
+//\r
+//*****************************************************************************\r
+#define HIB_RTCC_MASK 0xffffffff // RTC counter mask\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the Hibernate RTC match 0 register.\r
+//\r
+//*****************************************************************************\r
+#define HIB_RTCM0_MASK 0xffffffff // RTC match 0 mask\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the Hibernate RTC match 1 register.\r
+//\r
+//*****************************************************************************\r
+#define HIB_RTCM1_MASK 0xffffffff // RTC match 1 mask\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the Hibernate RTC load register.\r
+//\r
+//*****************************************************************************\r
+#define HIB_RTCLD_MASK 0xffffffff // RTC load mask\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the Hibernate control register\r
+//\r
+//*****************************************************************************\r
+#define HIB_CTL_VABORT 0x00000080 // low bat abort\r
+#define HIB_CTL_CLK32EN 0x00000040 // enable clock/oscillator\r
+#define HIB_CTL_LOWBATEN 0x00000020 // enable low battery detect\r
+#define HIB_CTL_PINWEN 0x00000010 // enable wake on WAKE pin\r
+#define HIB_CTL_RTCWEN 0x00000008 // enable wake on RTC match\r
+#define HIB_CTL_CLKSEL 0x00000004 // clock input selection\r
+#define HIB_CTL_HIBREQ 0x00000002 // request hibernation\r
+#define HIB_CTL_RTCEN 0x00000001 // RTC enable\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the Hibernate interrupt mask reg.\r
+//\r
+//*****************************************************************************\r
+#define HIB_IM_EXTW 0x00000008 // wake from external pin interrupt\r
+#define HIB_IM_LOWBAT 0x00000004 // low battery interrupt\r
+#define HIB_IM_RTCALT1 0x00000002 // RTC match 1 interrupt\r
+#define HIB_IM_RTCALT0 0x00000001 // RTC match 0 interrupt\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the Hibernate raw interrupt status.\r
+//\r
+//*****************************************************************************\r
+#define HIB_RIS_EXTW 0x00000008 // wake from external pin interrupt\r
+#define HIB_RIS_LOWBAT 0x00000004 // low battery interrupt\r
+#define HIB_RIS_RTCALT1 0x00000002 // RTC match 1 interrupt\r
+#define HIB_RID_RTCALT0 0x00000001 // RTC match 0 interrupt\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the Hibernate masked int status.\r
+//\r
+//*****************************************************************************\r
+#define HIB_MIS_EXTW 0x00000008 // wake from external pin interrupt\r
+#define HIB_MIS_LOWBAT 0x00000004 // low battery interrupt\r
+#define HIB_MIS_RTCALT1 0x00000002 // RTC match 1 interrupt\r
+#define HIB_MID_RTCALT0 0x00000001 // RTC match 0 interrupt\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the Hibernate interrupt clear reg.\r
+//\r
+//*****************************************************************************\r
+#define HIB_IC_EXTW 0x00000008 // wake from external pin interrupt\r
+#define HIB_IC_LOWBAT 0x00000004 // low battery interrupt\r
+#define HIB_IC_RTCALT1 0x00000002 // RTC match 1 interrupt\r
+#define HIB_IC_RTCALT0 0x00000001 // RTC match 0 interrupt\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the Hibernate RTC trim register.\r
+//\r
+//*****************************************************************************\r
+#define HIB_RTCT_MASK 0x0000ffff // RTC trim mask\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the Hibernate data register.\r
+//\r
+//*****************************************************************************\r
+#define HIB_DATA_MASK 0xffffffff // NV memory data mask\r
+\r
+#endif // __HW_HIBERNATE_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_i2c.h - Macros used when accessing the I2C master and slave hardware.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_I2C_H__\r
+#define __HW_I2C_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// The following defines the offset between the I2C master and slave registers.\r
+//\r
+//*****************************************************************************\r
+#define I2C_O_SLAVE 0x00000800 // Offset from master to slave\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the offsets of the I2C master registers.\r
+//\r
+//*****************************************************************************\r
+#define I2C_MASTER_O_SA 0x00000000 // Slave address register\r
+#define I2C_MASTER_O_CS 0x00000004 // Control and Status register\r
+#define I2C_MASTER_O_DR 0x00000008 // Data register\r
+#define I2C_MASTER_O_TPR 0x0000000C // Timer period register\r
+#define I2C_MASTER_O_IMR 0x00000010 // Interrupt mask register\r
+#define I2C_MASTER_O_RIS 0x00000014 // Raw interrupt status register\r
+#define I2C_MASTER_O_MIS 0x00000018 // Masked interrupt status reg\r
+#define I2C_MASTER_O_MICR 0x0000001c // Interrupt clear register\r
+#define I2C_MASTER_O_CR 0x00000020 // Configuration register\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the offsets of the I2C slave registers.\r
+//\r
+//*****************************************************************************\r
+#define I2C_SLAVE_O_OAR 0x00000000 // Own address register\r
+#define I2C_SLAVE_O_CSR 0x00000004 // Control/Status register\r
+#define I2C_SLAVE_O_DR 0x00000008 // Data register\r
+#define I2C_SLAVE_O_IM 0x0000000C // Interrupt mask register\r
+#define I2C_SLAVE_O_RIS 0x00000010 // Raw interrupt status register\r
+#define I2C_SLAVE_O_MIS 0x00000014 // Masked interrupt status reg\r
+#define I2C_SLAVE_O_SICR 0x00000018 // Interrupt clear register\r
+\r
+//*****************************************************************************\r
+//\r
+// The followng define the bit fields in the I2C master slave address register.\r
+//\r
+//*****************************************************************************\r
+#define I2C_MASTER_SA_SA_MASK 0x000000FE // Slave address\r
+#define I2C_MASTER_SA_RS 0x00000001 // Receive/send\r
+#define I2C_MASTER_SA_SA_SHIFT 1\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the I2C Master Control and Status\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define I2C_MASTER_CS_ACK 0x00000008 // Acknowlegde\r
+#define I2C_MASTER_CS_STOP 0x00000004 // Stop\r
+#define I2C_MASTER_CS_START 0x00000002 // Start\r
+#define I2C_MASTER_CS_RUN 0x00000001 // Run\r
+#define I2C_MASTER_CS_BUS_BUSY 0x00000040 // Bus busy\r
+#define I2C_MASTER_CS_IDLE 0x00000020 // Idle\r
+#define I2C_MASTER_CS_ARB_LOST 0x00000010 // Lost arbitration\r
+#define I2C_MASTER_CS_DATA_ACK 0x00000008 // Data byte not acknowledged\r
+#define I2C_MASTER_CS_ADDR_ACK 0x00000004 // Address byte not acknowledged\r
+#define I2C_MASTER_CS_ERROR 0x00000002 // Error occurred\r
+#define I2C_MASTER_CS_BUSY 0x00000001 // Controller is TX/RX data\r
+#define I2C_MASTER_CS_ERR_MASK 0x0000001C\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define values used in determining the contents of the I2C\r
+// Master Timer Period register.\r
+//\r
+//*****************************************************************************\r
+#define I2C_MASTER_TPR_SCL_HP 0x00000004 // SCL high period\r
+#define I2C_MASTER_TPR_SCL_LP 0x00000006 // SCL low period\r
+#define I2C_MASTER_TPR_SCL (I2C_MASTER_TPR_SCL_HP + I2C_MASTER_TPR_SCL_LP)\r
+#define I2C_SCL_STANDARD 100000 // SCL standard frequency\r
+#define I2C_SCL_FAST 400000 // SCL fast frequency\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the I2C Master Interrupt Mask\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define I2C_MASTER_IMR_IM 0x00000001 // Master interrupt mask\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the I2C Master Raw Interrupt Status\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define I2C_MASTER_RIS_RIS 0x00000001 // Master raw interrupt status\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the I2C Master Masked Interrupt\r
+// Status register.\r
+//\r
+//*****************************************************************************\r
+#define I2C_MASTER_MIS_MIS 0x00000001 // Master masked interrupt status\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the I2C Master Interrupt Clear\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define I2C_MASTER_MICR_IC 0x00000001 // Master interrupt clear\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the I2C Master Configuration\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define I2C_MASTER_CR_SFE 0x00000020 // Slave function enable\r
+#define I2C_MASTER_CR_MFE 0x00000010 // Master function enable\r
+#define I2C_MASTER_CR_LPBK 0x00000001 // Loopback enable\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the I2C Slave Own Address register.\r
+//\r
+//*****************************************************************************\r
+#define I2C_SLAVE_SOAR_OAR_MASK 0x0000007F // Slave address\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the I2C Slave Control/Status\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define I2C_SLAVE_CSR_DA 0x00000001 // Enable the device\r
+#define I2C_SLAVE_CSR_TREQ 0x00000002 // Transmit request received\r
+#define I2C_SLAVE_CSR_RREQ 0x00000001 // Receive data from I2C master\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the I2C Slave Interrupt Mask\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define I2C_SLAVE_IMR_IM 0x00000001 // Slave interrupt mask\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the I2C Slave Raw Interrupt Status\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define I2C_SLAVE_RIS_RIS 0x00000001 // Slave raw interrupt status\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the I2C Slave Masked Interrupt\r
+// Status register.\r
+//\r
+//*****************************************************************************\r
+#define I2C_SLAVE_MIS_MIS 0x00000001 // Slave masked interrupt status\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the I2C Slave Interrupt Clear\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define I2C_SLAVE_SICR_IC 0x00000001 // Slave interrupt clear\r
+\r
+#endif // __HW_I2C_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_ints.h - Macros that define the interrupt assignment on Stellaris.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_INTS_H__\r
+#define __HW_INTS_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the fault assignments.\r
+//\r
+//*****************************************************************************\r
+#define FAULT_NMI 2 // NMI fault\r
+#define FAULT_HARD 3 // Hard fault\r
+#define FAULT_MPU 4 // MPU fault\r
+#define FAULT_BUS 5 // Bus fault\r
+#define FAULT_USAGE 6 // Usage fault\r
+#define FAULT_SVCALL 11 // SVCall\r
+#define FAULT_DEBUG 12 // Debug monitor\r
+#define FAULT_PENDSV 14 // PendSV\r
+#define FAULT_SYSTICK 15 // System Tick\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the interrupt assignments.\r
+//\r
+//*****************************************************************************\r
+#define INT_GPIOA 16 // GPIO Port A\r
+#define INT_GPIOB 17 // GPIO Port B\r
+#define INT_GPIOC 18 // GPIO Port C\r
+#define INT_GPIOD 19 // GPIO Port D\r
+#define INT_GPIOE 20 // GPIO Port E\r
+#define INT_UART0 21 // UART0 Rx and Tx\r
+#define INT_UART1 22 // UART1 Rx and Tx\r
+#define INT_SSI 23 // SSI Rx and Tx\r
+#define INT_SSI0 23 // SSI0 Rx and Tx\r
+#define INT_I2C 24 // I2C Master and Slave\r
+#define INT_I2C0 24 // I2C0 Master and Slave\r
+#define INT_PWM_FAULT 25 // PWM Fault\r
+#define INT_PWM0 26 // PWM Generator 0\r
+#define INT_PWM1 27 // PWM Generator 1\r
+#define INT_PWM2 28 // PWM Generator 2\r
+#define INT_QEI 29 // Quadrature Encoder\r
+#define INT_QEI0 29 // Quadrature Encoder 0\r
+#define INT_ADC0 30 // ADC Sequence 0\r
+#define INT_ADC1 31 // ADC Sequence 1\r
+#define INT_ADC2 32 // ADC Sequence 2\r
+#define INT_ADC3 33 // ADC Sequence 3\r
+#define INT_WATCHDOG 34 // Watchdog timer\r
+#define INT_TIMER0A 35 // Timer 0 subtimer A\r
+#define INT_TIMER0B 36 // Timer 0 subtimer B\r
+#define INT_TIMER1A 37 // Timer 1 subtimer A\r
+#define INT_TIMER1B 38 // Timer 1 subtimer B\r
+#define INT_TIMER2A 39 // Timer 2 subtimer A\r
+#define INT_TIMER2B 40 // Timer 2 subtimer B\r
+#define INT_COMP0 41 // Analog Comparator 0\r
+#define INT_COMP1 42 // Analog Comparator 1\r
+#define INT_COMP2 43 // Analog Comparator 2\r
+#define INT_SYSCTL 44 // System Control (PLL, OSC, BO)\r
+#define INT_FLASH 45 // FLASH Control\r
+#define INT_GPIOF 46 // GPIO Port F\r
+#define INT_GPIOG 47 // GPIO Port G\r
+#define INT_GPIOH 48 // GPIO Port H\r
+#define INT_UART2 49 // UART2 Rx and Tx\r
+#define INT_SSI1 50 // SSI1 Rx and Tx\r
+#define INT_TIMER3A 51 // Timer 3 subtimer A\r
+#define INT_TIMER3B 52 // Timer 3 subtimer B\r
+#define INT_I2C1 53 // I2C1 Master and Slave\r
+#define INT_QEI1 54 // Quadrature Encoder 1\r
+#define INT_CAN0 55 // CAN0\r
+#define INT_CAN1 56 // CAN1\r
+#define INT_ETH 58 // Ethernet\r
+#define INT_HIBERNATE 59 // Hibernation module\r
+\r
+//*****************************************************************************\r
+//\r
+// The total number of interrupts.\r
+//\r
+//*****************************************************************************\r
+#define NUM_INTERRUPTS 60\r
+\r
+//*****************************************************************************\r
+//\r
+// The total number of priority levels.\r
+//\r
+//*****************************************************************************\r
+#define NUM_PRIORITY 8\r
+#define NUM_PRIORITY_BITS 3\r
+\r
+#endif // __HW_INTS_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_memmap.h - Macros defining the memory map of Stellaris.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_MEMMAP_H__\r
+#define __HW_MEMMAP_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the base address of the memories and peripherals.\r
+//\r
+//*****************************************************************************\r
+#define FLASH_BASE 0x00000000 // FLASH memory\r
+#define SRAM_BASE 0x20000000 // SRAM memory\r
+#define WATCHDOG_BASE 0x40000000 // Watchdog\r
+#define GPIO_PORTA_BASE 0x40004000 // GPIO Port A\r
+#define GPIO_PORTB_BASE 0x40005000 // GPIO Port B\r
+#define GPIO_PORTC_BASE 0x40006000 // GPIO Port C\r
+#define GPIO_PORTD_BASE 0x40007000 // GPIO Port D\r
+#define SSI_BASE 0x40008000 // SSI\r
+#define SSI0_BASE 0x40008000 // SSI0\r
+#define SSI1_BASE 0x40009000 // SSI1\r
+#define UART0_BASE 0x4000C000 // UART0\r
+#define UART1_BASE 0x4000D000 // UART1\r
+#define UART2_BASE 0x4000E000 // UART2\r
+#define I2C_MASTER_BASE 0x40020000 // I2C Master\r
+#define I2C_SLAVE_BASE 0x40020800 // I2C Slave\r
+#define I2C0_MASTER_BASE 0x40020000 // I2C0 Master\r
+#define I2C0_SLAVE_BASE 0x40020800 // I2C0 Slave\r
+#define I2C1_MASTER_BASE 0x40021000 // I2C1 Master\r
+#define I2C1_SLAVE_BASE 0x40021800 // I2C1 Slave\r
+#define GPIO_PORTE_BASE 0x40024000 // GPIO Port E\r
+#define GPIO_PORTF_BASE 0x40025000 // GPIO Port F\r
+#define GPIO_PORTG_BASE 0x40026000 // GPIO Port G\r
+#define GPIO_PORTH_BASE 0x40027000 // GPIO Port H\r
+#define PWM_BASE 0x40028000 // PWM\r
+#define QEI_BASE 0x4002C000 // QEI\r
+#define QEI0_BASE 0x4002C000 // QEI0\r
+#define QEI1_BASE 0x4002D000 // QEI1\r
+#define TIMER0_BASE 0x40030000 // Timer0\r
+#define TIMER1_BASE 0x40031000 // Timer1\r
+#define TIMER2_BASE 0x40032000 // Timer2\r
+#define TIMER3_BASE 0x40033000 // Timer3\r
+#define ADC_BASE 0x40038000 // ADC\r
+#define COMP_BASE 0x4003C000 // Analog comparators\r
+#define CAN0_BASE 0x40040000 // CAN0\r
+#define CAN1_BASE 0x40041000 // CAN1\r
+#define ETH_BASE 0x40048000 // Ethernet\r
+#define FLASH_CTRL_BASE 0x400FD000 // FLASH Controller\r
+#define SYSCTL_BASE 0x400FE000 // System Control\r
+#define ITM_BASE 0xE0000000 // Instrumentation Trace Macrocell\r
+#define DWT_BASE 0xE0001000 // Data Watchpoint and Trace\r
+#define FPB_BASE 0xE0002000 // FLASH Patch and Breakpoint\r
+#define NVIC_BASE 0xE000E000 // Nested Vectored Interrupt Ctrl\r
+#define TPIU_BASE 0xE0040000 // Trace Port Interface Unit\r
+\r
+#endif // __HW_MEMMAP_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_nvic.h - Macros used when accessing the NVIC hardware.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_NVIC_H__\r
+#define __HW_NVIC_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the addresses of the NVIC registers.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_INT_TYPE 0xE000E004 // Interrupt Controller Type Reg.\r
+#define NVIC_ST_CTRL 0xE000E010 // SysTick Control and Status Reg.\r
+#define NVIC_ST_RELOAD 0xE000E014 // SysTick Reload Value Register\r
+#define NVIC_ST_CURRENT 0xE000E018 // SysTick Current Value Register\r
+#define NVIC_ST_CAL 0xE000E01C // SysTick Calibration Value Reg.\r
+#define NVIC_EN0 0xE000E100 // IRQ 0 to 31 Set Enable Register\r
+#define NVIC_EN1 0xE000E104 // IRQ 32 to 63 Set Enable Register\r
+#define NVIC_DIS0 0xE000E180 // IRQ 0 to 31 Clear Enable Reg.\r
+#define NVIC_DIS1 0xE000E184 // IRQ 32 to 63 Clear Enable Reg.\r
+#define NVIC_PEND0 0xE000E200 // IRQ 0 to 31 Set Pending Register\r
+#define NVIC_PEND1 0xE000E204 // IRQ 32 to 63 Set Pending Reg.\r
+#define NVIC_UNPEND0 0xE000E280 // IRQ 0 to 31 Clear Pending Reg.\r
+#define NVIC_UNPEND1 0xE000E284 // IRQ 32 to 63 Clear Pending Reg.\r
+#define NVIC_ACTIVE0 0xE000E300 // IRQ 0 to 31 Active Register\r
+#define NVIC_ACTIVE1 0xE000E304 // IRQ 32 to 63 Active Register\r
+#define NVIC_PRI0 0xE000E400 // IRQ 0 to 3 Priority Register\r
+#define NVIC_PRI1 0xE000E404 // IRQ 4 to 7 Priority Register\r
+#define NVIC_PRI2 0xE000E408 // IRQ 8 to 11 Priority Register\r
+#define NVIC_PRI3 0xE000E40C // IRQ 12 to 15 Priority Register\r
+#define NVIC_PRI4 0xE000E410 // IRQ 16 to 19 Priority Register\r
+#define NVIC_PRI5 0xE000E414 // IRQ 20 to 23 Priority Register\r
+#define NVIC_PRI6 0xE000E418 // IRQ 24 to 27 Priority Register\r
+#define NVIC_PRI7 0xE000E41C // IRQ 28 to 31 Priority Register\r
+#define NVIC_PRI8 0xE000E420 // IRQ 32 to 35 Priority Register\r
+#define NVIC_PRI9 0xE000E424 // IRQ 36 to 39 Priority Register\r
+#define NVIC_PRI10 0xE000E428 // IRQ 40 to 43 Priority Register\r
+#define NVIC_CPUID 0xE000ED00 // CPUID Base Register\r
+#define NVIC_INT_CTRL 0xE000ED04 // Interrupt Control State Register\r
+#define NVIC_VTABLE 0xE000ED08 // Vector Table Offset Register\r
+#define NVIC_APINT 0xE000ED0C // App. Int & Reset Control Reg.\r
+#define NVIC_SYS_CTRL 0xE000ED10 // System Control Register\r
+#define NVIC_CFG_CTRL 0xE000ED14 // Configuration Control Register\r
+#define NVIC_SYS_PRI1 0xE000ED18 // Sys. Handlers 4 to 7 Priority\r
+#define NVIC_SYS_PRI2 0xE000ED1C // Sys. Handlers 8 to 11 Priority\r
+#define NVIC_SYS_PRI3 0xE000ED20 // Sys. Handlers 12 to 15 Priority\r
+#define NVIC_SYS_HND_CTRL 0xE000ED24 // System Handler Control and State\r
+#define NVIC_FAULT_STAT 0xE000ED28 // Configurable Fault Status Reg.\r
+#define NVIC_HFAULT_STAT 0xE000ED2C // Hard Fault Status Register\r
+#define NVIC_DEBUG_STAT 0xE000ED30 // Debug Status Register\r
+#define NVIC_MM_ADDR 0xE000ED34 // Mem Manage Address Register\r
+#define NVIC_FAULT_ADDR 0xE000ED38 // Bus Fault Address Register\r
+#define NVIC_MPU_TYPE 0xE000ED90 // MPU Type Register\r
+#define NVIC_MPU_CTRL 0xE000ED94 // MPU Control Register\r
+#define NVIC_MPU_NUMBER 0xE000ED98 // MPU Region Number Register\r
+#define NVIC_MPU_BASE 0xE000ED9C // MPU Region Base Address Register\r
+#define NVIC_MPU_ATTR 0xE000EDA0 // MPU Region Attribute & Size Reg.\r
+#define NVIC_DBG_CTRL 0xE000EDF0 // Debug Control and Status Reg.\r
+#define NVIC_DBG_XFER 0xE000EDF4 // Debug Core Reg. Transfer Select\r
+#define NVIC_DBG_DATA 0xE000EDF8 // Debug Core Register Data\r
+#define NVIC_DBG_INT 0xE000EDFC // Debug Reset Interrupt Control\r
+#define NVIC_SW_TRIG 0xE000EF00 // Software Trigger Interrupt Reg.\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_INT_TYPE register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_INT_TYPE_LINES_M 0x0000001F // Number of interrupt lines (x32)\r
+#define NVIC_INT_TYPE_LINES_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_ST_CTRL register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_ST_CTRL_COUNT 0x00010000 // Count flag\r
+#define NVIC_ST_CTRL_CLK_SRC 0x00000004 // Clock Source\r
+#define NVIC_ST_CTRL_INTEN 0x00000002 // Interrupt enable\r
+#define NVIC_ST_CTRL_ENABLE 0x00000001 // Counter mode\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_ST_RELOAD register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_ST_RELOAD_M 0x00FFFFFF // Counter load value\r
+#define NVIC_ST_RELOAD_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_ST_CURRENT register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_ST_CURRENT_M 0x00FFFFFF // Counter current value\r
+#define NVIC_ST_CURRENT_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_ST_CAL register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_ST_CAL_NOREF 0x80000000 // No reference clock\r
+#define NVIC_ST_CAL_SKEW 0x40000000 // Clock skew\r
+#define NVIC_ST_CAL_ONEMS_M 0x00FFFFFF // 1ms reference value\r
+#define NVIC_ST_CAL_ONEMS_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_EN0 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_EN0_INT31 0x80000000 // Interrupt 31 enable\r
+#define NVIC_EN0_INT30 0x40000000 // Interrupt 30 enable\r
+#define NVIC_EN0_INT29 0x20000000 // Interrupt 29 enable\r
+#define NVIC_EN0_INT28 0x10000000 // Interrupt 28 enable\r
+#define NVIC_EN0_INT27 0x08000000 // Interrupt 27 enable\r
+#define NVIC_EN0_INT26 0x04000000 // Interrupt 26 enable\r
+#define NVIC_EN0_INT25 0x02000000 // Interrupt 25 enable\r
+#define NVIC_EN0_INT24 0x01000000 // Interrupt 24 enable\r
+#define NVIC_EN0_INT23 0x00800000 // Interrupt 23 enable\r
+#define NVIC_EN0_INT22 0x00400000 // Interrupt 22 enable\r
+#define NVIC_EN0_INT21 0x00200000 // Interrupt 21 enable\r
+#define NVIC_EN0_INT20 0x00100000 // Interrupt 20 enable\r
+#define NVIC_EN0_INT19 0x00080000 // Interrupt 19 enable\r
+#define NVIC_EN0_INT18 0x00040000 // Interrupt 18 enable\r
+#define NVIC_EN0_INT17 0x00020000 // Interrupt 17 enable\r
+#define NVIC_EN0_INT16 0x00010000 // Interrupt 16 enable\r
+#define NVIC_EN0_INT15 0x00008000 // Interrupt 15 enable\r
+#define NVIC_EN0_INT14 0x00004000 // Interrupt 14 enable\r
+#define NVIC_EN0_INT13 0x00002000 // Interrupt 13 enable\r
+#define NVIC_EN0_INT12 0x00001000 // Interrupt 12 enable\r
+#define NVIC_EN0_INT11 0x00000800 // Interrupt 11 enable\r
+#define NVIC_EN0_INT10 0x00000400 // Interrupt 10 enable\r
+#define NVIC_EN0_INT9 0x00000200 // Interrupt 9 enable\r
+#define NVIC_EN0_INT8 0x00000100 // Interrupt 8 enable\r
+#define NVIC_EN0_INT7 0x00000080 // Interrupt 7 enable\r
+#define NVIC_EN0_INT6 0x00000040 // Interrupt 6 enable\r
+#define NVIC_EN0_INT5 0x00000020 // Interrupt 5 enable\r
+#define NVIC_EN0_INT4 0x00000010 // Interrupt 4 enable\r
+#define NVIC_EN0_INT3 0x00000008 // Interrupt 3 enable\r
+#define NVIC_EN0_INT2 0x00000004 // Interrupt 2 enable\r
+#define NVIC_EN0_INT1 0x00000002 // Interrupt 1 enable\r
+#define NVIC_EN0_INT0 0x00000001 // Interrupt 0 enable\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_EN1 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_EN1_INT59 0x08000000 // Interrupt 59 enable\r
+#define NVIC_EN1_INT58 0x04000000 // Interrupt 58 enable\r
+#define NVIC_EN1_INT57 0x02000000 // Interrupt 57 enable\r
+#define NVIC_EN1_INT56 0x01000000 // Interrupt 56 enable\r
+#define NVIC_EN1_INT55 0x00800000 // Interrupt 55 enable\r
+#define NVIC_EN1_INT54 0x00400000 // Interrupt 54 enable\r
+#define NVIC_EN1_INT53 0x00200000 // Interrupt 53 enable\r
+#define NVIC_EN1_INT52 0x00100000 // Interrupt 52 enable\r
+#define NVIC_EN1_INT51 0x00080000 // Interrupt 51 enable\r
+#define NVIC_EN1_INT50 0x00040000 // Interrupt 50 enable\r
+#define NVIC_EN1_INT49 0x00020000 // Interrupt 49 enable\r
+#define NVIC_EN1_INT48 0x00010000 // Interrupt 48 enable\r
+#define NVIC_EN1_INT47 0x00008000 // Interrupt 47 enable\r
+#define NVIC_EN1_INT46 0x00004000 // Interrupt 46 enable\r
+#define NVIC_EN1_INT45 0x00002000 // Interrupt 45 enable\r
+#define NVIC_EN1_INT44 0x00001000 // Interrupt 44 enable\r
+#define NVIC_EN1_INT43 0x00000800 // Interrupt 43 enable\r
+#define NVIC_EN1_INT42 0x00000400 // Interrupt 42 enable\r
+#define NVIC_EN1_INT41 0x00000200 // Interrupt 41 enable\r
+#define NVIC_EN1_INT40 0x00000100 // Interrupt 40 enable\r
+#define NVIC_EN1_INT39 0x00000080 // Interrupt 39 enable\r
+#define NVIC_EN1_INT38 0x00000040 // Interrupt 38 enable\r
+#define NVIC_EN1_INT37 0x00000020 // Interrupt 37 enable\r
+#define NVIC_EN1_INT36 0x00000010 // Interrupt 36 enable\r
+#define NVIC_EN1_INT35 0x00000008 // Interrupt 35 enable\r
+#define NVIC_EN1_INT34 0x00000004 // Interrupt 34 enable\r
+#define NVIC_EN1_INT33 0x00000002 // Interrupt 33 enable\r
+#define NVIC_EN1_INT32 0x00000001 // Interrupt 32 enable\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_DIS0 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_DIS0_INT31 0x80000000 // Interrupt 31 disable\r
+#define NVIC_DIS0_INT30 0x40000000 // Interrupt 30 disable\r
+#define NVIC_DIS0_INT29 0x20000000 // Interrupt 29 disable\r
+#define NVIC_DIS0_INT28 0x10000000 // Interrupt 28 disable\r
+#define NVIC_DIS0_INT27 0x08000000 // Interrupt 27 disable\r
+#define NVIC_DIS0_INT26 0x04000000 // Interrupt 26 disable\r
+#define NVIC_DIS0_INT25 0x02000000 // Interrupt 25 disable\r
+#define NVIC_DIS0_INT24 0x01000000 // Interrupt 24 disable\r
+#define NVIC_DIS0_INT23 0x00800000 // Interrupt 23 disable\r
+#define NVIC_DIS0_INT22 0x00400000 // Interrupt 22 disable\r
+#define NVIC_DIS0_INT21 0x00200000 // Interrupt 21 disable\r
+#define NVIC_DIS0_INT20 0x00100000 // Interrupt 20 disable\r
+#define NVIC_DIS0_INT19 0x00080000 // Interrupt 19 disable\r
+#define NVIC_DIS0_INT18 0x00040000 // Interrupt 18 disable\r
+#define NVIC_DIS0_INT17 0x00020000 // Interrupt 17 disable\r
+#define NVIC_DIS0_INT16 0x00010000 // Interrupt 16 disable\r
+#define NVIC_DIS0_INT15 0x00008000 // Interrupt 15 disable\r
+#define NVIC_DIS0_INT14 0x00004000 // Interrupt 14 disable\r
+#define NVIC_DIS0_INT13 0x00002000 // Interrupt 13 disable\r
+#define NVIC_DIS0_INT12 0x00001000 // Interrupt 12 disable\r
+#define NVIC_DIS0_INT11 0x00000800 // Interrupt 11 disable\r
+#define NVIC_DIS0_INT10 0x00000400 // Interrupt 10 disable\r
+#define NVIC_DIS0_INT9 0x00000200 // Interrupt 9 disable\r
+#define NVIC_DIS0_INT8 0x00000100 // Interrupt 8 disable\r
+#define NVIC_DIS0_INT7 0x00000080 // Interrupt 7 disable\r
+#define NVIC_DIS0_INT6 0x00000040 // Interrupt 6 disable\r
+#define NVIC_DIS0_INT5 0x00000020 // Interrupt 5 disable\r
+#define NVIC_DIS0_INT4 0x00000010 // Interrupt 4 disable\r
+#define NVIC_DIS0_INT3 0x00000008 // Interrupt 3 disable\r
+#define NVIC_DIS0_INT2 0x00000004 // Interrupt 2 disable\r
+#define NVIC_DIS0_INT1 0x00000002 // Interrupt 1 disable\r
+#define NVIC_DIS0_INT0 0x00000001 // Interrupt 0 disable\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_DIS1 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_DIS1_INT59 0x08000000 // Interrupt 59 disable\r
+#define NVIC_DIS1_INT58 0x04000000 // Interrupt 58 disable\r
+#define NVIC_DIS1_INT57 0x02000000 // Interrupt 57 disable\r
+#define NVIC_DIS1_INT56 0x01000000 // Interrupt 56 disable\r
+#define NVIC_DIS1_INT55 0x00800000 // Interrupt 55 disable\r
+#define NVIC_DIS1_INT54 0x00400000 // Interrupt 54 disable\r
+#define NVIC_DIS1_INT53 0x00200000 // Interrupt 53 disable\r
+#define NVIC_DIS1_INT52 0x00100000 // Interrupt 52 disable\r
+#define NVIC_DIS1_INT51 0x00080000 // Interrupt 51 disable\r
+#define NVIC_DIS1_INT50 0x00040000 // Interrupt 50 disable\r
+#define NVIC_DIS1_INT49 0x00020000 // Interrupt 49 disable\r
+#define NVIC_DIS1_INT48 0x00010000 // Interrupt 48 disable\r
+#define NVIC_DIS1_INT47 0x00008000 // Interrupt 47 disable\r
+#define NVIC_DIS1_INT46 0x00004000 // Interrupt 46 disable\r
+#define NVIC_DIS1_INT45 0x00002000 // Interrupt 45 disable\r
+#define NVIC_DIS1_INT44 0x00001000 // Interrupt 44 disable\r
+#define NVIC_DIS1_INT43 0x00000800 // Interrupt 43 disable\r
+#define NVIC_DIS1_INT42 0x00000400 // Interrupt 42 disable\r
+#define NVIC_DIS1_INT41 0x00000200 // Interrupt 41 disable\r
+#define NVIC_DIS1_INT40 0x00000100 // Interrupt 40 disable\r
+#define NVIC_DIS1_INT39 0x00000080 // Interrupt 39 disable\r
+#define NVIC_DIS1_INT38 0x00000040 // Interrupt 38 disable\r
+#define NVIC_DIS1_INT37 0x00000020 // Interrupt 37 disable\r
+#define NVIC_DIS1_INT36 0x00000010 // Interrupt 36 disable\r
+#define NVIC_DIS1_INT35 0x00000008 // Interrupt 35 disable\r
+#define NVIC_DIS1_INT34 0x00000004 // Interrupt 34 disable\r
+#define NVIC_DIS1_INT33 0x00000002 // Interrupt 33 disable\r
+#define NVIC_DIS1_INT32 0x00000001 // Interrupt 32 disable\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_PEND0 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_PEND0_INT31 0x80000000 // Interrupt 31 pend\r
+#define NVIC_PEND0_INT30 0x40000000 // Interrupt 30 pend\r
+#define NVIC_PEND0_INT29 0x20000000 // Interrupt 29 pend\r
+#define NVIC_PEND0_INT28 0x10000000 // Interrupt 28 pend\r
+#define NVIC_PEND0_INT27 0x08000000 // Interrupt 27 pend\r
+#define NVIC_PEND0_INT26 0x04000000 // Interrupt 26 pend\r
+#define NVIC_PEND0_INT25 0x02000000 // Interrupt 25 pend\r
+#define NVIC_PEND0_INT24 0x01000000 // Interrupt 24 pend\r
+#define NVIC_PEND0_INT23 0x00800000 // Interrupt 23 pend\r
+#define NVIC_PEND0_INT22 0x00400000 // Interrupt 22 pend\r
+#define NVIC_PEND0_INT21 0x00200000 // Interrupt 21 pend\r
+#define NVIC_PEND0_INT20 0x00100000 // Interrupt 20 pend\r
+#define NVIC_PEND0_INT19 0x00080000 // Interrupt 19 pend\r
+#define NVIC_PEND0_INT18 0x00040000 // Interrupt 18 pend\r
+#define NVIC_PEND0_INT17 0x00020000 // Interrupt 17 pend\r
+#define NVIC_PEND0_INT16 0x00010000 // Interrupt 16 pend\r
+#define NVIC_PEND0_INT15 0x00008000 // Interrupt 15 pend\r
+#define NVIC_PEND0_INT14 0x00004000 // Interrupt 14 pend\r
+#define NVIC_PEND0_INT13 0x00002000 // Interrupt 13 pend\r
+#define NVIC_PEND0_INT12 0x00001000 // Interrupt 12 pend\r
+#define NVIC_PEND0_INT11 0x00000800 // Interrupt 11 pend\r
+#define NVIC_PEND0_INT10 0x00000400 // Interrupt 10 pend\r
+#define NVIC_PEND0_INT9 0x00000200 // Interrupt 9 pend\r
+#define NVIC_PEND0_INT8 0x00000100 // Interrupt 8 pend\r
+#define NVIC_PEND0_INT7 0x00000080 // Interrupt 7 pend\r
+#define NVIC_PEND0_INT6 0x00000040 // Interrupt 6 pend\r
+#define NVIC_PEND0_INT5 0x00000020 // Interrupt 5 pend\r
+#define NVIC_PEND0_INT4 0x00000010 // Interrupt 4 pend\r
+#define NVIC_PEND0_INT3 0x00000008 // Interrupt 3 pend\r
+#define NVIC_PEND0_INT2 0x00000004 // Interrupt 2 pend\r
+#define NVIC_PEND0_INT1 0x00000002 // Interrupt 1 pend\r
+#define NVIC_PEND0_INT0 0x00000001 // Interrupt 0 pend\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_PEND1 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_PEND1_INT59 0x08000000 // Interrupt 59 pend\r
+#define NVIC_PEND1_INT58 0x04000000 // Interrupt 58 pend\r
+#define NVIC_PEND1_INT57 0x02000000 // Interrupt 57 pend\r
+#define NVIC_PEND1_INT56 0x01000000 // Interrupt 56 pend\r
+#define NVIC_PEND1_INT55 0x00800000 // Interrupt 55 pend\r
+#define NVIC_PEND1_INT54 0x00400000 // Interrupt 54 pend\r
+#define NVIC_PEND1_INT53 0x00200000 // Interrupt 53 pend\r
+#define NVIC_PEND1_INT52 0x00100000 // Interrupt 52 pend\r
+#define NVIC_PEND1_INT51 0x00080000 // Interrupt 51 pend\r
+#define NVIC_PEND1_INT50 0x00040000 // Interrupt 50 pend\r
+#define NVIC_PEND1_INT49 0x00020000 // Interrupt 49 pend\r
+#define NVIC_PEND1_INT48 0x00010000 // Interrupt 48 pend\r
+#define NVIC_PEND1_INT47 0x00008000 // Interrupt 47 pend\r
+#define NVIC_PEND1_INT46 0x00004000 // Interrupt 46 pend\r
+#define NVIC_PEND1_INT45 0x00002000 // Interrupt 45 pend\r
+#define NVIC_PEND1_INT44 0x00001000 // Interrupt 44 pend\r
+#define NVIC_PEND1_INT43 0x00000800 // Interrupt 43 pend\r
+#define NVIC_PEND1_INT42 0x00000400 // Interrupt 42 pend\r
+#define NVIC_PEND1_INT41 0x00000200 // Interrupt 41 pend\r
+#define NVIC_PEND1_INT40 0x00000100 // Interrupt 40 pend\r
+#define NVIC_PEND1_INT39 0x00000080 // Interrupt 39 pend\r
+#define NVIC_PEND1_INT38 0x00000040 // Interrupt 38 pend\r
+#define NVIC_PEND1_INT37 0x00000020 // Interrupt 37 pend\r
+#define NVIC_PEND1_INT36 0x00000010 // Interrupt 36 pend\r
+#define NVIC_PEND1_INT35 0x00000008 // Interrupt 35 pend\r
+#define NVIC_PEND1_INT34 0x00000004 // Interrupt 34 pend\r
+#define NVIC_PEND1_INT33 0x00000002 // Interrupt 33 pend\r
+#define NVIC_PEND1_INT32 0x00000001 // Interrupt 32 pend\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_UNPEND0 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_UNPEND0_INT31 0x80000000 // Interrupt 31 unpend\r
+#define NVIC_UNPEND0_INT30 0x40000000 // Interrupt 30 unpend\r
+#define NVIC_UNPEND0_INT29 0x20000000 // Interrupt 29 unpend\r
+#define NVIC_UNPEND0_INT28 0x10000000 // Interrupt 28 unpend\r
+#define NVIC_UNPEND0_INT27 0x08000000 // Interrupt 27 unpend\r
+#define NVIC_UNPEND0_INT26 0x04000000 // Interrupt 26 unpend\r
+#define NVIC_UNPEND0_INT25 0x02000000 // Interrupt 25 unpend\r
+#define NVIC_UNPEND0_INT24 0x01000000 // Interrupt 24 unpend\r
+#define NVIC_UNPEND0_INT23 0x00800000 // Interrupt 23 unpend\r
+#define NVIC_UNPEND0_INT22 0x00400000 // Interrupt 22 unpend\r
+#define NVIC_UNPEND0_INT21 0x00200000 // Interrupt 21 unpend\r
+#define NVIC_UNPEND0_INT20 0x00100000 // Interrupt 20 unpend\r
+#define NVIC_UNPEND0_INT19 0x00080000 // Interrupt 19 unpend\r
+#define NVIC_UNPEND0_INT18 0x00040000 // Interrupt 18 unpend\r
+#define NVIC_UNPEND0_INT17 0x00020000 // Interrupt 17 unpend\r
+#define NVIC_UNPEND0_INT16 0x00010000 // Interrupt 16 unpend\r
+#define NVIC_UNPEND0_INT15 0x00008000 // Interrupt 15 unpend\r
+#define NVIC_UNPEND0_INT14 0x00004000 // Interrupt 14 unpend\r
+#define NVIC_UNPEND0_INT13 0x00002000 // Interrupt 13 unpend\r
+#define NVIC_UNPEND0_INT12 0x00001000 // Interrupt 12 unpend\r
+#define NVIC_UNPEND0_INT11 0x00000800 // Interrupt 11 unpend\r
+#define NVIC_UNPEND0_INT10 0x00000400 // Interrupt 10 unpend\r
+#define NVIC_UNPEND0_INT9 0x00000200 // Interrupt 9 unpend\r
+#define NVIC_UNPEND0_INT8 0x00000100 // Interrupt 8 unpend\r
+#define NVIC_UNPEND0_INT7 0x00000080 // Interrupt 7 unpend\r
+#define NVIC_UNPEND0_INT6 0x00000040 // Interrupt 6 unpend\r
+#define NVIC_UNPEND0_INT5 0x00000020 // Interrupt 5 unpend\r
+#define NVIC_UNPEND0_INT4 0x00000010 // Interrupt 4 unpend\r
+#define NVIC_UNPEND0_INT3 0x00000008 // Interrupt 3 unpend\r
+#define NVIC_UNPEND0_INT2 0x00000004 // Interrupt 2 unpend\r
+#define NVIC_UNPEND0_INT1 0x00000002 // Interrupt 1 unpend\r
+#define NVIC_UNPEND0_INT0 0x00000001 // Interrupt 0 unpend\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_UNPEND1 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_UNPEND1_INT59 0x08000000 // Interrupt 59 unpend\r
+#define NVIC_UNPEND1_INT58 0x04000000 // Interrupt 58 unpend\r
+#define NVIC_UNPEND1_INT57 0x02000000 // Interrupt 57 unpend\r
+#define NVIC_UNPEND1_INT56 0x01000000 // Interrupt 56 unpend\r
+#define NVIC_UNPEND1_INT55 0x00800000 // Interrupt 55 unpend\r
+#define NVIC_UNPEND1_INT54 0x00400000 // Interrupt 54 unpend\r
+#define NVIC_UNPEND1_INT53 0x00200000 // Interrupt 53 unpend\r
+#define NVIC_UNPEND1_INT52 0x00100000 // Interrupt 52 unpend\r
+#define NVIC_UNPEND1_INT51 0x00080000 // Interrupt 51 unpend\r
+#define NVIC_UNPEND1_INT50 0x00040000 // Interrupt 50 unpend\r
+#define NVIC_UNPEND1_INT49 0x00020000 // Interrupt 49 unpend\r
+#define NVIC_UNPEND1_INT48 0x00010000 // Interrupt 48 unpend\r
+#define NVIC_UNPEND1_INT47 0x00008000 // Interrupt 47 unpend\r
+#define NVIC_UNPEND1_INT46 0x00004000 // Interrupt 46 unpend\r
+#define NVIC_UNPEND1_INT45 0x00002000 // Interrupt 45 unpend\r
+#define NVIC_UNPEND1_INT44 0x00001000 // Interrupt 44 unpend\r
+#define NVIC_UNPEND1_INT43 0x00000800 // Interrupt 43 unpend\r
+#define NVIC_UNPEND1_INT42 0x00000400 // Interrupt 42 unpend\r
+#define NVIC_UNPEND1_INT41 0x00000200 // Interrupt 41 unpend\r
+#define NVIC_UNPEND1_INT40 0x00000100 // Interrupt 40 unpend\r
+#define NVIC_UNPEND1_INT39 0x00000080 // Interrupt 39 unpend\r
+#define NVIC_UNPEND1_INT38 0x00000040 // Interrupt 38 unpend\r
+#define NVIC_UNPEND1_INT37 0x00000020 // Interrupt 37 unpend\r
+#define NVIC_UNPEND1_INT36 0x00000010 // Interrupt 36 unpend\r
+#define NVIC_UNPEND1_INT35 0x00000008 // Interrupt 35 unpend\r
+#define NVIC_UNPEND1_INT34 0x00000004 // Interrupt 34 unpend\r
+#define NVIC_UNPEND1_INT33 0x00000002 // Interrupt 33 unpend\r
+#define NVIC_UNPEND1_INT32 0x00000001 // Interrupt 32 unpend\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_ACTIVE0 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_ACTIVE0_INT31 0x80000000 // Interrupt 31 active\r
+#define NVIC_ACTIVE0_INT30 0x40000000 // Interrupt 30 active\r
+#define NVIC_ACTIVE0_INT29 0x20000000 // Interrupt 29 active\r
+#define NVIC_ACTIVE0_INT28 0x10000000 // Interrupt 28 active\r
+#define NVIC_ACTIVE0_INT27 0x08000000 // Interrupt 27 active\r
+#define NVIC_ACTIVE0_INT26 0x04000000 // Interrupt 26 active\r
+#define NVIC_ACTIVE0_INT25 0x02000000 // Interrupt 25 active\r
+#define NVIC_ACTIVE0_INT24 0x01000000 // Interrupt 24 active\r
+#define NVIC_ACTIVE0_INT23 0x00800000 // Interrupt 23 active\r
+#define NVIC_ACTIVE0_INT22 0x00400000 // Interrupt 22 active\r
+#define NVIC_ACTIVE0_INT21 0x00200000 // Interrupt 21 active\r
+#define NVIC_ACTIVE0_INT20 0x00100000 // Interrupt 20 active\r
+#define NVIC_ACTIVE0_INT19 0x00080000 // Interrupt 19 active\r
+#define NVIC_ACTIVE0_INT18 0x00040000 // Interrupt 18 active\r
+#define NVIC_ACTIVE0_INT17 0x00020000 // Interrupt 17 active\r
+#define NVIC_ACTIVE0_INT16 0x00010000 // Interrupt 16 active\r
+#define NVIC_ACTIVE0_INT15 0x00008000 // Interrupt 15 active\r
+#define NVIC_ACTIVE0_INT14 0x00004000 // Interrupt 14 active\r
+#define NVIC_ACTIVE0_INT13 0x00002000 // Interrupt 13 active\r
+#define NVIC_ACTIVE0_INT12 0x00001000 // Interrupt 12 active\r
+#define NVIC_ACTIVE0_INT11 0x00000800 // Interrupt 11 active\r
+#define NVIC_ACTIVE0_INT10 0x00000400 // Interrupt 10 active\r
+#define NVIC_ACTIVE0_INT9 0x00000200 // Interrupt 9 active\r
+#define NVIC_ACTIVE0_INT8 0x00000100 // Interrupt 8 active\r
+#define NVIC_ACTIVE0_INT7 0x00000080 // Interrupt 7 active\r
+#define NVIC_ACTIVE0_INT6 0x00000040 // Interrupt 6 active\r
+#define NVIC_ACTIVE0_INT5 0x00000020 // Interrupt 5 active\r
+#define NVIC_ACTIVE0_INT4 0x00000010 // Interrupt 4 active\r
+#define NVIC_ACTIVE0_INT3 0x00000008 // Interrupt 3 active\r
+#define NVIC_ACTIVE0_INT2 0x00000004 // Interrupt 2 active\r
+#define NVIC_ACTIVE0_INT1 0x00000002 // Interrupt 1 active\r
+#define NVIC_ACTIVE0_INT0 0x00000001 // Interrupt 0 active\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_ACTIVE1 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_ACTIVE1_INT59 0x08000000 // Interrupt 59 active\r
+#define NVIC_ACTIVE1_INT58 0x04000000 // Interrupt 58 active\r
+#define NVIC_ACTIVE1_INT57 0x02000000 // Interrupt 57 active\r
+#define NVIC_ACTIVE1_INT56 0x01000000 // Interrupt 56 active\r
+#define NVIC_ACTIVE1_INT55 0x00800000 // Interrupt 55 active\r
+#define NVIC_ACTIVE1_INT54 0x00400000 // Interrupt 54 active\r
+#define NVIC_ACTIVE1_INT53 0x00200000 // Interrupt 53 active\r
+#define NVIC_ACTIVE1_INT52 0x00100000 // Interrupt 52 active\r
+#define NVIC_ACTIVE1_INT51 0x00080000 // Interrupt 51 active\r
+#define NVIC_ACTIVE1_INT50 0x00040000 // Interrupt 50 active\r
+#define NVIC_ACTIVE1_INT49 0x00020000 // Interrupt 49 active\r
+#define NVIC_ACTIVE1_INT48 0x00010000 // Interrupt 48 active\r
+#define NVIC_ACTIVE1_INT47 0x00008000 // Interrupt 47 active\r
+#define NVIC_ACTIVE1_INT46 0x00004000 // Interrupt 46 active\r
+#define NVIC_ACTIVE1_INT45 0x00002000 // Interrupt 45 active\r
+#define NVIC_ACTIVE1_INT44 0x00001000 // Interrupt 44 active\r
+#define NVIC_ACTIVE1_INT43 0x00000800 // Interrupt 43 active\r
+#define NVIC_ACTIVE1_INT42 0x00000400 // Interrupt 42 active\r
+#define NVIC_ACTIVE1_INT41 0x00000200 // Interrupt 41 active\r
+#define NVIC_ACTIVE1_INT40 0x00000100 // Interrupt 40 active\r
+#define NVIC_ACTIVE1_INT39 0x00000080 // Interrupt 39 active\r
+#define NVIC_ACTIVE1_INT38 0x00000040 // Interrupt 38 active\r
+#define NVIC_ACTIVE1_INT37 0x00000020 // Interrupt 37 active\r
+#define NVIC_ACTIVE1_INT36 0x00000010 // Interrupt 36 active\r
+#define NVIC_ACTIVE1_INT35 0x00000008 // Interrupt 35 active\r
+#define NVIC_ACTIVE1_INT34 0x00000004 // Interrupt 34 active\r
+#define NVIC_ACTIVE1_INT33 0x00000002 // Interrupt 33 active\r
+#define NVIC_ACTIVE1_INT32 0x00000001 // Interrupt 32 active\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_PRI0 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_PRI0_INT3_M 0xFF000000 // Interrupt 3 priority mask\r
+#define NVIC_PRI0_INT2_M 0x00FF0000 // Interrupt 2 priority mask\r
+#define NVIC_PRI0_INT1_M 0x0000FF00 // Interrupt 1 priority mask\r
+#define NVIC_PRI0_INT0_M 0x000000FF // Interrupt 0 priority mask\r
+#define NVIC_PRI0_INT3_S 24\r
+#define NVIC_PRI0_INT2_S 16\r
+#define NVIC_PRI0_INT1_S 8\r
+#define NVIC_PRI0_INT0_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_PRI1 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_PRI1_INT7_M 0xFF000000 // Interrupt 7 priority mask\r
+#define NVIC_PRI1_INT6_M 0x00FF0000 // Interrupt 6 priority mask\r
+#define NVIC_PRI1_INT5_M 0x0000FF00 // Interrupt 5 priority mask\r
+#define NVIC_PRI1_INT4_M 0x000000FF // Interrupt 4 priority mask\r
+#define NVIC_PRI1_INT7_S 24\r
+#define NVIC_PRI1_INT6_S 16\r
+#define NVIC_PRI1_INT5_S 8\r
+#define NVIC_PRI1_INT4_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_PRI2 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_PRI2_INT11_M 0xFF000000 // Interrupt 11 priority mask\r
+#define NVIC_PRI2_INT10_M 0x00FF0000 // Interrupt 10 priority mask\r
+#define NVIC_PRI2_INT9_M 0x0000FF00 // Interrupt 9 priority mask\r
+#define NVIC_PRI2_INT8_M 0x000000FF // Interrupt 8 priority mask\r
+#define NVIC_PRI2_INT11_S 24\r
+#define NVIC_PRI2_INT10_S 16\r
+#define NVIC_PRI2_INT9_S 8\r
+#define NVIC_PRI2_INT8_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_PRI3 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_PRI3_INT15_M 0xFF000000 // Interrupt 15 priority mask\r
+#define NVIC_PRI3_INT14_M 0x00FF0000 // Interrupt 14 priority mask\r
+#define NVIC_PRI3_INT13_M 0x0000FF00 // Interrupt 13 priority mask\r
+#define NVIC_PRI3_INT12_M 0x000000FF // Interrupt 12 priority mask\r
+#define NVIC_PRI3_INT15_S 24\r
+#define NVIC_PRI3_INT14_S 16\r
+#define NVIC_PRI3_INT13_S 8\r
+#define NVIC_PRI3_INT12_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_PRI4 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_PRI4_INT19_M 0xFF000000 // Interrupt 19 priority mask\r
+#define NVIC_PRI4_INT18_M 0x00FF0000 // Interrupt 18 priority mask\r
+#define NVIC_PRI4_INT17_M 0x0000FF00 // Interrupt 17 priority mask\r
+#define NVIC_PRI4_INT16_M 0x000000FF // Interrupt 16 priority mask\r
+#define NVIC_PRI4_INT19_S 24\r
+#define NVIC_PRI4_INT18_S 16\r
+#define NVIC_PRI4_INT17_S 8\r
+#define NVIC_PRI4_INT16_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_PRI5 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_PRI5_INT23_M 0xFF000000 // Interrupt 23 priority mask\r
+#define NVIC_PRI5_INT22_M 0x00FF0000 // Interrupt 22 priority mask\r
+#define NVIC_PRI5_INT21_M 0x0000FF00 // Interrupt 21 priority mask\r
+#define NVIC_PRI5_INT20_M 0x000000FF // Interrupt 20 priority mask\r
+#define NVIC_PRI5_INT23_S 24\r
+#define NVIC_PRI5_INT22_S 16\r
+#define NVIC_PRI5_INT21_S 8\r
+#define NVIC_PRI5_INT20_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_PRI6 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_PRI6_INT27_M 0xFF000000 // Interrupt 27 priority mask\r
+#define NVIC_PRI6_INT26_M 0x00FF0000 // Interrupt 26 priority mask\r
+#define NVIC_PRI6_INT25_M 0x0000FF00 // Interrupt 25 priority mask\r
+#define NVIC_PRI6_INT24_M 0x000000FF // Interrupt 24 priority mask\r
+#define NVIC_PRI6_INT27_S 24\r
+#define NVIC_PRI6_INT26_S 16\r
+#define NVIC_PRI6_INT25_S 8\r
+#define NVIC_PRI6_INT24_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_PRI7 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_PRI7_INT31_M 0xFF000000 // Interrupt 31 priority mask\r
+#define NVIC_PRI7_INT30_M 0x00FF0000 // Interrupt 30 priority mask\r
+#define NVIC_PRI7_INT29_M 0x0000FF00 // Interrupt 29 priority mask\r
+#define NVIC_PRI7_INT28_M 0x000000FF // Interrupt 28 priority mask\r
+#define NVIC_PRI7_INT31_S 24\r
+#define NVIC_PRI7_INT30_S 16\r
+#define NVIC_PRI7_INT29_S 8\r
+#define NVIC_PRI7_INT28_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_PRI8 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_PRI8_INT35_M 0xFF000000 // Interrupt 35 priority mask\r
+#define NVIC_PRI8_INT34_M 0x00FF0000 // Interrupt 34 priority mask\r
+#define NVIC_PRI8_INT33_M 0x0000FF00 // Interrupt 33 priority mask\r
+#define NVIC_PRI8_INT32_M 0x000000FF // Interrupt 32 priority mask\r
+#define NVIC_PRI8_INT35_S 24\r
+#define NVIC_PRI8_INT34_S 16\r
+#define NVIC_PRI8_INT33_S 8\r
+#define NVIC_PRI8_INT32_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_PRI9 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_PRI9_INT39_M 0xFF000000 // Interrupt 39 priority mask\r
+#define NVIC_PRI9_INT38_M 0x00FF0000 // Interrupt 38 priority mask\r
+#define NVIC_PRI9_INT37_M 0x0000FF00 // Interrupt 37 priority mask\r
+#define NVIC_PRI9_INT36_M 0x000000FF // Interrupt 36 priority mask\r
+#define NVIC_PRI9_INT39_S 24\r
+#define NVIC_PRI9_INT38_S 16\r
+#define NVIC_PRI9_INT37_S 8\r
+#define NVIC_PRI9_INT36_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_PRI10 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_PRI10_INT43_M 0xFF000000 // Interrupt 43 priority mask\r
+#define NVIC_PRI10_INT42_M 0x00FF0000 // Interrupt 42 priority mask\r
+#define NVIC_PRI10_INT41_M 0x0000FF00 // Interrupt 41 priority mask\r
+#define NVIC_PRI10_INT40_M 0x000000FF // Interrupt 40 priority mask\r
+#define NVIC_PRI10_INT43_S 24\r
+#define NVIC_PRI10_INT42_S 16\r
+#define NVIC_PRI10_INT41_S 8\r
+#define NVIC_PRI10_INT40_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_CPUID register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_CPUID_IMP_M 0xFF000000 // Implementer\r
+#define NVIC_CPUID_VAR_M 0x00F00000 // Variant\r
+#define NVIC_CPUID_PARTNO_M 0x0000FFF0 // Processor part number\r
+#define NVIC_CPUID_REV_M 0x0000000F // Revision\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_INT_CTRL register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_INT_CTRL_NMI_SET 0x80000000 // Pend a NMI\r
+#define NVIC_INT_CTRL_PEND_SV 0x10000000 // Pend a PendSV\r
+#define NVIC_INT_CTRL_UNPEND_SV 0x08000000 // Unpend a PendSV\r
+#define NVIC_INT_CTRL_ISR_PRE 0x00800000 // Debug interrupt handling\r
+#define NVIC_INT_CTRL_ISR_PEND 0x00400000 // Debug interrupt pending\r
+#define NVIC_INT_CTRL_VEC_PEN_M 0x003FF000 // Highest pending exception\r
+#define NVIC_INT_CTRL_RET_BASE 0x00000800 // Return to base\r
+#define NVIC_INT_CTRL_VEC_ACT_M 0x000003FF // Current active exception\r
+#define NVIC_INT_CTRL_VEC_PEN_S 12\r
+#define NVIC_INT_CTRL_VEC_ACT_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_VTABLE register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_VTABLE_BASE 0x20000000 // Vector table base\r
+#define NVIC_VTABLE_OFFSET_M 0x1FFFFF00 // Vector table offset\r
+#define NVIC_VTABLE_OFFSET_S 8\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_APINT register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_APINT_VECTKEY_M 0xFFFF0000 // Vector key mask\r
+#define NVIC_APINT_VECTKEY 0x05FA0000 // Vector key\r
+#define NVIC_APINT_ENDIANESS 0x00008000 // Data endianess\r
+#define NVIC_APINT_PRIGROUP_M 0x00000700 // Priority group\r
+#define NVIC_APINT_PRIGROUP_7_1 0x00000000 // Priority group 7.1 split\r
+#define NVIC_APINT_PRIGROUP_6_2 0x00000100 // Priority group 6.2 split\r
+#define NVIC_APINT_PRIGROUP_5_3 0x00000200 // Priority group 5.3 split\r
+#define NVIC_APINT_PRIGROUP_4_4 0x00000300 // Priority group 4.4 split\r
+#define NVIC_APINT_PRIGROUP_3_5 0x00000400 // Priority group 3.5 split\r
+#define NVIC_APINT_PRIGROUP_2_6 0x00000500 // Priority group 2.6 split\r
+#define NVIC_APINT_PRIGROUP_1_7 0x00000600 // Priority group 1.7 split\r
+#define NVIC_APINT_PRIGROUP_0_8 0x00000700 // Priority group 0.8 split\r
+#define NVIC_APINT_SYSRESETREQ 0x00000004 // System reset request\r
+#define NVIC_APINT_VECT_CLR_ACT 0x00000002 // Clear active NMI/fault info\r
+#define NVIC_APINT_VECT_RESET 0x00000001 // System reset\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_SYS_CTRL register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_SYS_CTRL_SEVONPEND 0x00000010 // Wakeup on pend\r
+#define NVIC_SYS_CTRL_SLEEPDEEP 0x00000004 // Deep sleep enable\r
+#define NVIC_SYS_CTRL_SLEEPEXIT 0x00000002 // Sleep on ISR exit\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_CFG_CTRL register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_CFG_CTRL_BFHFNMIGN 0x00000100 // Ignore bus fault in NMI/fault\r
+#define NVIC_CFG_CTRL_DIV0 0x00000010 // Trap on divide by 0\r
+#define NVIC_CFG_CTRL_UNALIGNED 0x00000008 // Trap on unaligned access\r
+#define NVIC_CFG_CTRL_DEEP_PEND 0x00000004 // Allow deep interrupt trigger\r
+#define NVIC_CFG_CTRL_MAIN_PEND 0x00000002 // Allow main interrupt trigger\r
+#define NVIC_CFG_CTRL_BASE_THR 0x00000001 // Thread state control\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_SYS_PRI1 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_SYS_PRI1_RES_M 0xFF000000 // Priority of reserved handler\r
+#define NVIC_SYS_PRI1_USAGE_M 0x00FF0000 // Priority of usage fault handler\r
+#define NVIC_SYS_PRI1_BUS_M 0x0000FF00 // Priority of bus fault handler\r
+#define NVIC_SYS_PRI1_MEM_M 0x000000FF // Priority of mem manage handler\r
+#define NVIC_SYS_PRI1_USAGE_S 16\r
+#define NVIC_SYS_PRI1_BUS_S 8\r
+#define NVIC_SYS_PRI1_MEM_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_SYS_PRI2 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_SYS_PRI2_SVC_M 0xFF000000 // Priority of SVCall handler\r
+#define NVIC_SYS_PRI2_RES_M 0x00FFFFFF // Priority of reserved handlers\r
+#define NVIC_SYS_PRI2_SVC_S 24\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_SYS_PRI3 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_SYS_PRI3_TICK_M 0xFF000000 // Priority of Sys Tick handler\r
+#define NVIC_SYS_PRI3_PENDSV_M 0x00FF0000 // Priority of PendSV handler\r
+#define NVIC_SYS_PRI3_RES_M 0x0000FF00 // Priority of reserved handler\r
+#define NVIC_SYS_PRI3_DEBUG_M 0x000000FF // Priority of debug handler\r
+#define NVIC_SYS_PRI3_TICK_S 24\r
+#define NVIC_SYS_PRI3_PENDSV_S 16\r
+#define NVIC_SYS_PRI3_DEBUG_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_SYS_HND_CTRL register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_SYS_HND_CTRL_USAGE 0x00040000 // Usage fault enable\r
+#define NVIC_SYS_HND_CTRL_BUS 0x00020000 // Bus fault enable\r
+#define NVIC_SYS_HND_CTRL_MEM 0x00010000 // Mem manage fault enable\r
+#define NVIC_SYS_HND_CTRL_SVC 0x00008000 // SVCall is pended\r
+#define NVIC_SYS_HND_CTRL_BUSP 0x00004000 // Bus fault is pended\r
+#define NVIC_SYS_HND_CTRL_TICK 0x00000800 // Sys tick is active\r
+#define NVIC_SYS_HND_CTRL_PNDSV 0x00000400 // PendSV is active\r
+#define NVIC_SYS_HND_CTRL_MON 0x00000100 // Monitor is active\r
+#define NVIC_SYS_HND_CTRL_SVCA 0x00000080 // SVCall is active\r
+#define NVIC_SYS_HND_CTRL_USGA 0x00000008 // Usage fault is active\r
+#define NVIC_SYS_HND_CTRL_BUSA 0x00000002 // Bus fault is active\r
+#define NVIC_SYS_HND_CTRL_MEMA 0x00000001 // Mem manage is active\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_FAULT_STAT register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_FAULT_STAT_DIV0 0x02000000 // Divide by zero fault\r
+#define NVIC_FAULT_STAT_UNALIGN 0x01000000 // Unaligned access fault\r
+#define NVIC_FAULT_STAT_NOCP 0x00080000 // No coprocessor fault\r
+#define NVIC_FAULT_STAT_INVPC 0x00040000 // Invalid PC fault\r
+#define NVIC_FAULT_STAT_INVSTAT 0x00020000 // Invalid state fault\r
+#define NVIC_FAULT_STAT_UNDEF 0x00010000 // Undefined instruction fault\r
+#define NVIC_FAULT_STAT_BFARV 0x00008000 // BFAR is valid\r
+#define NVIC_FAULT_STAT_BSTKE 0x00001000 // Stack bus fault\r
+#define NVIC_FAULT_STAT_BUSTKE 0x00000800 // Unstack bus fault\r
+#define NVIC_FAULT_STAT_IMPRE 0x00000400 // Imprecise data bus error\r
+#define NVIC_FAULT_STAT_PRECISE 0x00000200 // Precise data bus error\r
+#define NVIC_FAULT_STAT_IBUS 0x00000100 // Instruction bus fault\r
+#define NVIC_FAULT_STAT_MMARV 0x00000080 // MMAR is valid\r
+#define NVIC_FAULT_STAT_MSTKE 0x00000010 // Stack access violation\r
+#define NVIC_FAULT_STAT_MUSTKE 0x00000008 // Unstack access violation\r
+#define NVIC_FAULT_STAT_DERR 0x00000002 // Data access violation\r
+#define NVIC_FAULT_STAT_IERR 0x00000001 // Instruction access violation\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_HFAULT_STAT register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_HFAULT_STAT_DBG 0x80000000 // Debug event\r
+#define NVIC_HFAULT_STAT_FORCED 0x40000000 // Cannot execute fault handler\r
+#define NVIC_HFAULT_STAT_VECT 0x00000002 // Vector table read fault\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_DEBUG_STAT register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_DEBUG_STAT_EXTRNL 0x00000010 // EDBGRQ asserted\r
+#define NVIC_DEBUG_STAT_VCATCH 0x00000008 // Vector catch\r
+#define NVIC_DEBUG_STAT_DWTTRAP 0x00000004 // DWT match\r
+#define NVIC_DEBUG_STAT_BKPT 0x00000002 // Breakpoint instruction\r
+#define NVIC_DEBUG_STAT_HALTED 0x00000001 // Halt request\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_MM_ADDR register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_MM_ADDR_M 0xFFFFFFFF // Data fault address\r
+#define NVIC_MM_ADDR_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_FAULT_ADDR register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_FAULT_ADDR_M 0xFFFFFFFF // Data bus fault address\r
+#define NVIC_FAULT_ADDR_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_EXC_STACK register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_EXC_STACK_DEEP 0x00000001 // Exception stack\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_EXC_NUM register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_EXC_NUM_M 0x000003FF // Exception number\r
+#define NVIC_EXC_NUM_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_COPRO register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_COPRO_15_M 0xC0000000 // Coprocessor 15 access mask\r
+#define NVIC_COPRO_15_DENIED 0x00000000 // Coprocessor 15 access denied\r
+#define NVIC_COPRO_15_PRIV 0x40000000 // Coprocessor 15 privileged addess\r
+#define NVIC_COPRO_15_FULL 0xC0000000 // Coprocessor 15 full access\r
+#define NVIC_COPRO_14_M 0x30000000 // Coprocessor 14 access mask\r
+#define NVIC_COPRO_14_DENIED 0x00000000 // Coprocessor 14 access denied\r
+#define NVIC_COPRO_14_PRIV 0x10000000 // Coprocessor 14 privileged addess\r
+#define NVIC_COPRO_14_FULL 0x30000000 // Coprocessor 14 full access\r
+#define NVIC_COPRO_13_M 0x0C000000 // Coprocessor 13 access mask\r
+#define NVIC_COPRO_13_DENIED 0x00000000 // Coprocessor 13 access denied\r
+#define NVIC_COPRO_13_PRIV 0x04000000 // Coprocessor 13 privileged addess\r
+#define NVIC_COPRO_13_FULL 0x0C000000 // Coprocessor 13 full access\r
+#define NVIC_COPRO_12_M 0x03000000 // Coprocessor 12 access mask\r
+#define NVIC_COPRO_12_DENIED 0x00000000 // Coprocessor 12 access denied\r
+#define NVIC_COPRO_12_PRIV 0x01000000 // Coprocessor 12 privileged addess\r
+#define NVIC_COPRO_12_FULL 0x03000000 // Coprocessor 12 full access\r
+#define NVIC_COPRO_11_M 0x00C00000 // Coprocessor 11 access mask\r
+#define NVIC_COPRO_11_DENIED 0x00000000 // Coprocessor 11 access denied\r
+#define NVIC_COPRO_11_PRIV 0x00400000 // Coprocessor 11 privileged addess\r
+#define NVIC_COPRO_11_FULL 0x00C00000 // Coprocessor 11 full access\r
+#define NVIC_COPRO_10_M 0x00300000 // Coprocessor 10 access mask\r
+#define NVIC_COPRO_10_DENIED 0x00000000 // Coprocessor 10 access denied\r
+#define NVIC_COPRO_10_PRIV 0x00100000 // Coprocessor 10 privileged addess\r
+#define NVIC_COPRO_10_FULL 0x00300000 // Coprocessor 10 full access\r
+#define NVIC_COPRO_9_M 0x000C0000 // Coprocessor 9 access mask\r
+#define NVIC_COPRO_9_DENIED 0x00000000 // Coprocessor 9 access denied\r
+#define NVIC_COPRO_9_PRIV 0x00040000 // Coprocessor 9 privileged addess\r
+#define NVIC_COPRO_9_FULL 0x000C0000 // Coprocessor 9 full access\r
+#define NVIC_COPRO_8_M 0x00030000 // Coprocessor 8 access mask\r
+#define NVIC_COPRO_8_DENIED 0x00000000 // Coprocessor 8 access denied\r
+#define NVIC_COPRO_8_PRIV 0x00010000 // Coprocessor 8 privileged addess\r
+#define NVIC_COPRO_8_FULL 0x00030000 // Coprocessor 8 full access\r
+#define NVIC_COPRO_7_M 0x0000C000 // Coprocessor 7 access mask\r
+#define NVIC_COPRO_7_DENIED 0x00000000 // Coprocessor 7 access denied\r
+#define NVIC_COPRO_7_PRIV 0x00004000 // Coprocessor 7 privileged addess\r
+#define NVIC_COPRO_7_FULL 0x0000C000 // Coprocessor 7 full access\r
+#define NVIC_COPRO_6_M 0x00003000 // Coprocessor 6 access mask\r
+#define NVIC_COPRO_6_DENIED 0x00000000 // Coprocessor 6 access denied\r
+#define NVIC_COPRO_6_PRIV 0x00001000 // Coprocessor 6 privileged addess\r
+#define NVIC_COPRO_6_FULL 0x00003000 // Coprocessor 6 full access\r
+#define NVIC_COPRO_5_M 0x00000C00 // Coprocessor 5 access mask\r
+#define NVIC_COPRO_5_DENIED 0x00000000 // Coprocessor 5 access denied\r
+#define NVIC_COPRO_5_PRIV 0x00000400 // Coprocessor 5 privileged addess\r
+#define NVIC_COPRO_5_FULL 0x00000C00 // Coprocessor 5 full access\r
+#define NVIC_COPRO_4_M 0x00000300 // Coprocessor 4 access mask\r
+#define NVIC_COPRO_4_DENIED 0x00000000 // Coprocessor 4 access denied\r
+#define NVIC_COPRO_4_PRIV 0x00000100 // Coprocessor 4 privileged addess\r
+#define NVIC_COPRO_4_FULL 0x00000300 // Coprocessor 4 full access\r
+#define NVIC_COPRO_3_M 0x000000C0 // Coprocessor 3 access mask\r
+#define NVIC_COPRO_3_DENIED 0x00000000 // Coprocessor 3 access denied\r
+#define NVIC_COPRO_3_PRIV 0x00000040 // Coprocessor 3 privileged addess\r
+#define NVIC_COPRO_3_FULL 0x000000C0 // Coprocessor 3 full access\r
+#define NVIC_COPRO_2_M 0x00000030 // Coprocessor 2 access mask\r
+#define NVIC_COPRO_2_DENIED 0x00000000 // Coprocessor 2 access denied\r
+#define NVIC_COPRO_2_PRIV 0x00000010 // Coprocessor 2 privileged addess\r
+#define NVIC_COPRO_2_FULL 0x00000030 // Coprocessor 2 full access\r
+#define NVIC_COPRO_1_M 0x0000000C // Coprocessor 1 access mask\r
+#define NVIC_COPRO_1_DENIED 0x00000000 // Coprocessor 1 access denied\r
+#define NVIC_COPRO_1_PRIV 0x00000004 // Coprocessor 1 privileged addess\r
+#define NVIC_COPRO_1_FULL 0x0000000C // Coprocessor 1 full access\r
+#define NVIC_COPRO_0_M 0x00000003 // Coprocessor 0 access mask\r
+#define NVIC_COPRO_0_DENIED 0x00000000 // Coprocessor 0 access denied\r
+#define NVIC_COPRO_0_PRIV 0x00000001 // Coprocessor 0 privileged addess\r
+#define NVIC_COPRO_0_FULL 0x00000003 // Coprocessor 0 full access\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_MPU_TYPE register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_MPU_TYPE_IREGION_M 0x00FF0000 // Number of I regions\r
+#define NVIC_MPU_TYPE_DREGION_M 0x0000FF00 // Number of D regions\r
+#define NVIC_MPU_TYPE_SEPARATE 0x00000001 // Separate or unified MPU\r
+#define NVIC_MPU_TYPE_IREGION_S 16\r
+#define NVIC_MPU_TYPE_DREGION_S 8\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_MPU_CTRL register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_MPU_CTRL_HFNMIENA 0x00000002 // MPU enabled during faults\r
+#define NVIC_MPU_CTRL_ENABLE 0x00000001 // MPU enable\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_MPU_NUMBER register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_MPU_NUMBER_M 0x000000FF // MPU region to access\r
+#define NVIC_MPU_NUMBER_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_MPU_BASE register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_MPU_BASE_ADDR_M 0xFFFFFF00 // Base address\r
+#define NVIC_MPU_BASE_VALID 0x00000010 // Region number valid\r
+#define NVIC_MPU_BASE_REGION_M 0x0000000F // Region number\r
+#define NVIC_MPU_BASE_ADDR_S 8\r
+#define NVIC_MPU_BASE_REGION_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_MPU_ATTR register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_MPU_ATTR_ATTRS 0xFFFF0000 // Attributes\r
+#define NVIC_MPU_ATTR_SRD 0x0000FF00 // Sub-region disable\r
+#define NVIC_MPU_ATTR_SZENABLE 0x000000FF // Region size\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_DBG_CTRL register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_DBG_CTRL_DBGKEY_M 0xFFFF0000 // Debug key mask\r
+#define NVIC_DBG_CTRL_DBGKEY 0xA05F0000 // Debug key\r
+#define NVIC_DBG_CTRL_MON_PEND 0x00008000 // Pend the monitor\r
+#define NVIC_DBG_CTRL_MON_REQ 0x00004000 // Monitor request\r
+#define NVIC_DBG_CTRL_MON_EN 0x00002000 // Debug monitor enable\r
+#define NVIC_DBG_CTRL_MONSTEP 0x00001000 // Monitor step the core\r
+#define NVIC_DBG_CTRL_S_SLEEP 0x00000400 // Core is sleeping\r
+#define NVIC_DBG_CTRL_S_HALT 0x00000200 // Core status on halt\r
+#define NVIC_DBG_CTRL_S_REGRDY 0x00000100 // Register read/write available\r
+#define NVIC_DBG_CTRL_S_LOCKUP 0x00000080 // Core is locked up\r
+#define NVIC_DBG_CTRL_C_RESET 0x00000010 // Reset the core\r
+#define NVIC_DBG_CTRL_C_MASKINT 0x00000008 // Mask interrupts when stepping\r
+#define NVIC_DBG_CTRL_C_STEP 0x00000004 // Step the core\r
+#define NVIC_DBG_CTRL_C_HALT 0x00000002 // Halt the core\r
+#define NVIC_DBG_CTRL_C_DEBUGEN 0x00000001 // Enable debug\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_DBG_XFER register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_DBG_XFER_REG_WNR 0x00010000 // Write or not read\r
+#define NVIC_DBG_XFER_REG_SEL_M 0x0000001F // Register\r
+#define NVIC_DBG_XFER_REG_R0 0x00000000 // Register R0\r
+#define NVIC_DBG_XFER_REG_R1 0x00000001 // Register R1\r
+#define NVIC_DBG_XFER_REG_R2 0x00000002 // Register R2\r
+#define NVIC_DBG_XFER_REG_R3 0x00000003 // Register R3\r
+#define NVIC_DBG_XFER_REG_R4 0x00000004 // Register R4\r
+#define NVIC_DBG_XFER_REG_R5 0x00000005 // Register R5\r
+#define NVIC_DBG_XFER_REG_R6 0x00000006 // Register R6\r
+#define NVIC_DBG_XFER_REG_R7 0x00000007 // Register R7\r
+#define NVIC_DBG_XFER_REG_R8 0x00000008 // Register R8\r
+#define NVIC_DBG_XFER_REG_R9 0x00000009 // Register R9\r
+#define NVIC_DBG_XFER_REG_R10 0x0000000A // Register R10\r
+#define NVIC_DBG_XFER_REG_R11 0x0000000B // Register R11\r
+#define NVIC_DBG_XFER_REG_R12 0x0000000C // Register R12\r
+#define NVIC_DBG_XFER_REG_R13 0x0000000D // Register R13\r
+#define NVIC_DBG_XFER_REG_R14 0x0000000E // Register R14\r
+#define NVIC_DBG_XFER_REG_R15 0x0000000F // Register R15\r
+#define NVIC_DBG_XFER_REG_FLAGS 0x00000010 // xPSR/Flags register\r
+#define NVIC_DBG_XFER_REG_MSP 0x00000011 // Main SP\r
+#define NVIC_DBG_XFER_REG_PSP 0x00000012 // Process SP\r
+#define NVIC_DBG_XFER_REG_DSP 0x00000013 // Deep SP\r
+#define NVIC_DBG_XFER_REG_CFBP 0x00000014 // Control/Fault/BasePri/PriMask\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_DBG_DATA register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_DBG_DATA_M 0xFFFFFFFF // Data temporary cache\r
+#define NVIC_DBG_DATA_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_DBG_INT register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_DBG_INT_HARDERR 0x00000400 // Debug trap on hard fault\r
+#define NVIC_DBG_INT_INTERR 0x00000200 // Debug trap on interrupt errors\r
+#define NVIC_DBG_INT_BUSERR 0x00000100 // Debug trap on bus error\r
+#define NVIC_DBG_INT_STATERR 0x00000080 // Debug trap on usage fault state\r
+#define NVIC_DBG_INT_CHKERR 0x00000040 // Debug trap on usage fault check\r
+#define NVIC_DBG_INT_NOCPERR 0x00000020 // Debug trap on coprocessor error\r
+#define NVIC_DBG_INT_MMERR 0x00000010 // Debug trap on mem manage fault\r
+#define NVIC_DBG_INT_RESET 0x00000008 // Core reset status\r
+#define NVIC_DBG_INT_RSTPENDCLR 0x00000004 // Clear pending core reset\r
+#define NVIC_DBG_INT_RSTPENDING 0x00000002 // Core reset is pending\r
+#define NVIC_DBG_INT_RSTVCATCH 0x00000001 // Reset vector catch\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_SW_TRIG register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_SW_TRIG_INTID_M 0x000003FF // Interrupt to trigger\r
+#define NVIC_SW_TRIG_INTID_S 0\r
+\r
+#endif // __HW_NVIC_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_pwm.h - Defines and Macros for Pulse Width Modulation (PWM) ports\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_PWM_H__\r
+#define __HW_PWM_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// PWM Module Register Offsets.\r
+//\r
+//*****************************************************************************\r
+#define PWM_O_CTL 0x00000000 // PWM Master Control register\r
+#define PWM_O_SYNC 0x00000004 // PWM Time Base Sync register\r
+#define PWM_O_ENABLE 0x00000008 // PWM Output Enable register\r
+#define PWM_O_INVERT 0x0000000C // PWM Output Inversion register\r
+#define PWM_O_FAULT 0x00000010 // PWM Output Fault register\r
+#define PWM_O_INTEN 0x00000014 // PWM Interrupt Enable register\r
+#define PWM_O_RIS 0x00000018 // PWM Interrupt Raw Status reg.\r
+#define PWM_O_ISC 0x0000001C // PWM Interrupt Status register\r
+#define PWM_O_STATUS 0x00000020 // PWM Status register\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the PWM Master Control register.\r
+//\r
+//*****************************************************************************\r
+#define PWM_CTL_GLOBAL_SYNC2 0x00000004 // Global sync generator 2\r
+#define PWM_CTL_GLOBAL_SYNC1 0x00000002 // Global sync generator 1\r
+#define PWM_CTL_GLOBAL_SYNC0 0x00000001 // Global sync generator 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the PWM Time Base Sync register.\r
+//\r
+//*****************************************************************************\r
+#define PWM_SYNC_SYNC2 0x00000004 // Reset generator 2 counter\r
+#define PWM_SYNC_SYNC1 0x00000002 // Reset generator 1 counter\r
+#define PWM_SYNC_SYNC0 0x00000001 // Reset generator 0 counter\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the PWM Output Enable register.\r
+//\r
+//*****************************************************************************\r
+#define PWM_ENABLE_PWM5EN 0x00000020 // PWM5 pin enable\r
+#define PWM_ENABLE_PWM4EN 0x00000010 // PWM4 pin enable\r
+#define PWM_ENABLE_PWM3EN 0x00000008 // PWM3 pin enable\r
+#define PWM_ENABLE_PWM2EN 0x00000004 // PWM2 pin enable\r
+#define PWM_ENABLE_PWM1EN 0x00000002 // PWM1 pin enable\r
+#define PWM_ENABLE_PWM0EN 0x00000001 // PWM0 pin enable\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the PWM Inversion register.\r
+//\r
+//*****************************************************************************\r
+#define PWM_INVERT_PWM5INV 0x00000020 // PWM5 pin invert\r
+#define PWM_INVERT_PWM4INV 0x00000010 // PWM4 pin invert\r
+#define PWM_INVERT_PWM3INV 0x00000008 // PWM3 pin invert\r
+#define PWM_INVERT_PWM2INV 0x00000004 // PWM2 pin invert\r
+#define PWM_INVERT_PWM1INV 0x00000002 // PWM1 pin invert\r
+#define PWM_INVERT_PWM0INV 0x00000001 // PWM0 pin invert\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the PWM Fault register.\r
+//\r
+//*****************************************************************************\r
+#define PWM_FAULT_FAULT5 0x00000020 // PWM5 pin fault\r
+#define PWM_FAULT_FAULT4 0x00000010 // PWM5 pin fault\r
+#define PWM_FAULT_FAULT3 0x00000008 // PWM5 pin fault\r
+#define PWM_FAULT_FAULT2 0x00000004 // PWM5 pin fault\r
+#define PWM_FAULT_FAULT1 0x00000002 // PWM5 pin fault\r
+#define PWM_FAULT_FAULT0 0x00000001 // PWM5 pin fault\r
+\r
+//*****************************************************************************\r
+//\r
+// PWM Interrupt Register bit definitions.\r
+//\r
+//*****************************************************************************\r
+#define PWM_INT_INTFAULT 0x00010000 // Fault interrupt pending\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the PWM Status register.\r
+//\r
+//*****************************************************************************\r
+#define PWM_STATUS_FAULT 0x00000001 // Fault status\r
+\r
+//*****************************************************************************\r
+//\r
+// PWM Generator standard offsets.\r
+//\r
+//*****************************************************************************\r
+#define PWM_GEN_0_OFFSET 0x00000040 // PWM0 base\r
+#define PWM_GEN_1_OFFSET 0x00000080 // PWM1 base\r
+#define PWM_GEN_2_OFFSET 0x000000C0 // PWM2 base\r
+\r
+#define PWM_O_X_CTL 0x00000000 // Gen Control Reg\r
+#define PWM_O_X_INTEN 0x00000004 // Gen Int/Trig Enable Reg\r
+#define PWM_O_X_RIS 0x00000008 // Gen Raw Int Status Reg\r
+#define PWM_O_X_ISC 0x0000000C // Gen Int Status Reg\r
+#define PWM_O_X_LOAD 0x00000010 // Gen Load Reg\r
+#define PWM_O_X_COUNT 0x00000014 // Gen Counter Reg\r
+#define PWM_O_X_CMPA 0x00000018 // Gen Compare A Reg\r
+#define PWM_O_X_CMPB 0x0000001C // Gen Compare B Reg\r
+#define PWM_O_X_GENA 0x00000020 // Gen Generator A Ctrl Reg\r
+#define PWM_O_X_GENB 0x00000024 // Gen Generator B Ctrl Reg\r
+#define PWM_O_X_DBCTL 0x00000028 // Gen Dead Band Ctrl Reg\r
+#define PWM_O_X_DBRISE 0x0000002C // Gen DB Rising Edge Delay Reg\r
+#define PWM_O_X_DBFALL 0x00000030 // Gen DB Falling Edge Delay Reg\r
+\r
+//*****************************************************************************\r
+//\r
+// PWM_X Control Register bit definitions.\r
+//\r
+//*****************************************************************************\r
+#define PWM_X_CTL_ENABLE 0x00000001 // Master enable for gen block\r
+#define PWM_X_CTL_MODE 0x00000002 // Counter mode, down or up/down\r
+#define PWM_X_CTL_DEBUG 0x00000004 // Debug mode\r
+#define PWM_X_CTL_LOADUPD 0x00000008 // Update mode for the load reg\r
+#define PWM_X_CTL_CMPAUPD 0x00000010 // Update mode for comp A reg\r
+#define PWM_X_CTL_CMPBUPD 0x00000020 // Update mode for comp B reg\r
+\r
+//*****************************************************************************\r
+//\r
+// PWM_X Interrupt/Trigger Enable Register bit definitions.\r
+//\r
+//*****************************************************************************\r
+#define PWM_X_INTEN_INTCNTZERO 0x00000001 // Int if COUNT = 0\r
+#define PWM_X_INTEN_INTCNTLOAD 0x00000002 // Int if COUNT = LOAD\r
+#define PWM_X_INTEN_INTCMPAU 0x00000004 // Int if COUNT = CMPA U\r
+#define PWM_X_INTEN_INTCMPAD 0x00000008 // Int if COUNT = CMPA D\r
+#define PWM_X_INTEN_INTCMPBU 0x00000010 // Int if COUNT = CMPA U\r
+#define PWM_X_INTEN_INTCMPBD 0x00000020 // Int if COUNT = CMPA D\r
+#define PWM_X_INTEN_TRCNTZERO 0x00000100 // Trig if COUNT = 0\r
+#define PWM_X_INTEN_TRCNTLOAD 0x00000200 // Trig if COUNT = LOAD\r
+#define PWM_X_INTEN_TRCMPAU 0x00000400 // Trig if COUNT = CMPA U\r
+#define PWM_X_INTEN_TRCMPAD 0x00000800 // Trig if COUNT = CMPA D\r
+#define PWM_X_INTEN_TRCMPBU 0x00001000 // Trig if COUNT = CMPA U\r
+#define PWM_X_INTEN_TRCMPBD 0x00002000 // Trig if COUNT = CMPA D\r
+\r
+//*****************************************************************************\r
+//\r
+// PWM_X Raw Interrupt Status Register bit definitions.\r
+//\r
+//*****************************************************************************\r
+#define PWM_X_RIS_INTCNTZERO 0x00000001 // PWM_X_COUNT = 0 int\r
+#define PWM_X_RIS_INTCNTLOAD 0x00000002 // PWM_X_COUNT = PWM_X_LOAD int\r
+#define PWM_X_RIS_INTCMPAU 0x00000004 // PWM_X_COUNT = PWM_X_CMPA U int\r
+#define PWM_X_RIS_INTCMPAD 0x00000008 // PWM_X_COUNT = PWM_X_CMPA D int\r
+#define PWM_X_RIS_INTCMPBU 0x00000010 // PWM_X_COUNT = PWM_X_CMPB U int\r
+#define PWM_X_RIS_INTCMPBD 0x00000020 // PWM_X_COUNT = PWM_X_CMPB D int\r
+\r
+//*****************************************************************************\r
+//\r
+// PWM_X Interrupt Status Register bit definitions.\r
+//\r
+//*****************************************************************************\r
+#define PWM_X_INT_INTCNTZERO 0x00000001 // PWM_X_COUNT = 0 received\r
+#define PWM_X_INT_INTCNTLOAD 0x00000002 // PWM_X_COUNT = PWM_X_LOAD rcvd\r
+#define PWM_X_INT_INTCMPAU 0x00000004 // PWM_X_COUNT = PWM_X_CMPA U rcvd\r
+#define PWM_X_INT_INTCMPAD 0x00000008 // PWM_X_COUNT = PWM_X_CMPA D rcvd\r
+#define PWM_X_INT_INTCMPBU 0x00000010 // PWM_X_COUNT = PWM_X_CMPB U rcvd\r
+#define PWM_X_INT_INTCMPBD 0x00000020 // PWM_X_COUNT = PWM_X_CMPB D rcvd\r
+\r
+//*****************************************************************************\r
+//\r
+// PWM_X Generator A/B Control Register bit definitions.\r
+//\r
+//*****************************************************************************\r
+#define PWM_X_GEN_Y_ACTZERO 0x00000003 // Act PWM_X_COUNT = 0\r
+#define PWM_X_GEN_Y_ACTLOAD 0x0000000C // Act PWM_X_COUNT = PWM_X_LOAD\r
+#define PWM_X_GEN_Y_ACTCMPAU 0x00000030 // Act PWM_X_COUNT = PWM_X_CMPA U\r
+#define PWM_X_GEN_Y_ACTCMPAD 0x000000C0 // Act PWM_X_COUNT = PWM_X_CMPA D\r
+#define PWM_X_GEN_Y_ACTCMPBU 0x00000300 // Act PWM_X_COUNT = PWM_X_CMPB U\r
+#define PWM_X_GEN_Y_ACTCMPBD 0x00000C00 // Act PWM_X_COUNT = PWM_X_CMPB D\r
+\r
+//*****************************************************************************\r
+//\r
+// PWM_X Generator A/B Control Register action definitions.\r
+//\r
+//*****************************************************************************\r
+#define PWM_GEN_ACT_NONE 0x0 // Do nothing\r
+#define PWM_GEN_ACT_INV 0x1 // Invert the output signal\r
+#define PWM_GEN_ACT_ZERO 0x2 // Set the output signal to zero\r
+#define PWM_GEN_ACT_ONE 0x3 // Set the output signal to one\r
+#define PWM_GEN_ACT_ZERO_SHIFT 0 // Shift amount for the zero action\r
+#define PWM_GEN_ACT_LOAD_SHIFT 2 // Shift amount for the load action\r
+#define PWM_GEN_ACT_A_UP_SHIFT 4 // Shift amount for the A up action\r
+#define PWM_GEN_ACT_A_DN_SHIFT 6 // Shift amount for the A dn action\r
+#define PWM_GEN_ACT_B_UP_SHIFT 8 // Shift amount for the B up action\r
+#define PWM_GEN_ACT_B_DN_SHIFT 10 // Shift amount for the B dn action\r
+\r
+//*****************************************************************************\r
+//\r
+// PWM_X Dead Band Control Register bit definitions.\r
+//\r
+//*****************************************************************************\r
+#define PWM_DBCTL_ENABLE 0x00000001 // Enable dead band insertion\r
+\r
+//*****************************************************************************\r
+//\r
+// PWM Register reset values.\r
+//\r
+//*****************************************************************************\r
+#define PWM_RV_CTL 0x00000000 // Master control of the PWM module\r
+#define PWM_RV_SYNC 0x00000000 // Counter synch for PWM generators\r
+#define PWM_RV_ENABLE 0x00000000 // Master enable for the PWM\r
+ // output pins\r
+#define PWM_RV_INVERT 0x00000000 // Inversion control for\r
+ // PWM output pins\r
+#define PWM_RV_FAULT 0x00000000 // Fault handling for the PWM\r
+ // output pins\r
+#define PWM_RV_INTEN 0x00000000 // Interrupt enable\r
+#define PWM_RV_RIS 0x00000000 // Raw interrupt status\r
+#define PWM_RV_ISC 0x00000000 // Interrupt status and clearing\r
+#define PWM_RV_STATUS 0x00000000 // Status\r
+#define PWM_RV_X_CTL 0x00000000 // Master control of the PWM\r
+ // generator block\r
+#define PWM_RV_X_INTEN 0x00000000 // Interrupt and trigger enable\r
+#define PWM_RV_X_RIS 0x00000000 // Raw interrupt status\r
+#define PWM_RV_X_ISC 0x00000000 // Interrupt status and clearing\r
+#define PWM_RV_X_LOAD 0x00000000 // The load value for the counter\r
+#define PWM_RV_X_COUNT 0x00000000 // The current counter value\r
+#define PWM_RV_X_CMPA 0x00000000 // The comparator A value\r
+#define PWM_RV_X_CMPB 0x00000000 // The comparator B value\r
+#define PWM_RV_X_GENA 0x00000000 // Controls PWM generator A\r
+#define PWM_RV_X_GENB 0x00000000 // Controls PWM generator B\r
+#define PWM_RV_X_DBCTL 0x00000000 // Control the dead band generator\r
+#define PWM_RV_X_DBRISE 0x00000000 // The dead band rising edge delay\r
+ // count\r
+#define PWM_RV_X_DBFALL 0x00000000 // The dead band falling edge delay\r
+ // count\r
+\r
+#endif // __HW_PWM_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_qei.h - Macros used when accessing the QEI hardware.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_QEI_H__\r
+#define __HW_QEI_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the offsets of the QEI registers.\r
+//\r
+//*****************************************************************************\r
+#define QEI_O_CTL 0x00000000 // Configuration and control reg.\r
+#define QEI_O_STAT 0x00000004 // Status register\r
+#define QEI_O_POS 0x00000008 // Current position register\r
+#define QEI_O_MAXPOS 0x0000000C // Maximum position register\r
+#define QEI_O_LOAD 0x00000010 // Velocity timer load register\r
+#define QEI_O_TIME 0x00000014 // Velocity timer register\r
+#define QEI_O_COUNT 0x00000018 // Velocity pulse count register\r
+#define QEI_O_SPEED 0x0000001C // Velocity speed register\r
+#define QEI_O_INTEN 0x00000020 // Interrupt enable register\r
+#define QEI_O_RIS 0x00000024 // Raw interrupt status register\r
+#define QEI_O_ISC 0x00000028 // Interrupt status register\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the QEI_CTL register.\r
+//\r
+//*****************************************************************************\r
+#define QEI_CTL_STALLEN 0x00001000 // Stall enable\r
+#define QEI_CTL_INVI 0x00000800 // Invert Index input\r
+#define QEI_CTL_INVB 0x00000400 // Invert PhB input\r
+#define QEI_CTL_INVA 0x00000200 // Invert PhA input\r
+#define QEI_CTL_VELDIV_M 0x000001C0 // Velocity predivider mask\r
+#define QEI_CTL_VELDIV_1 0x00000000 // Predivide by 1\r
+#define QEI_CTL_VELDIV_2 0x00000040 // Predivide by 2\r
+#define QEI_CTL_VELDIV_4 0x00000080 // Predivide by 4\r
+#define QEI_CTL_VELDIV_8 0x000000C0 // Predivide by 8\r
+#define QEI_CTL_VELDIV_16 0x00000100 // Predivide by 16\r
+#define QEI_CTL_VELDIV_32 0x00000140 // Predivide by 32\r
+#define QEI_CTL_VELDIV_64 0x00000180 // Predivide by 64\r
+#define QEI_CTL_VELDIV_128 0x000001C0 // Predivide by 128\r
+#define QEI_CTL_VELEN 0x00000020 // Velocity enable\r
+#define QEI_CTL_RESMODE 0x00000010 // Position counter reset mode\r
+#define QEI_CTL_CAPMODE 0x00000008 // Edge capture mode\r
+#define QEI_CTL_SIGMODE 0x00000004 // Encoder signaling mode\r
+#define QEI_CTL_SWAP 0x00000002 // Swap input signals\r
+#define QEI_CTL_ENABLE 0x00000001 // QEI enable\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the QEI_STAT register.\r
+//\r
+//*****************************************************************************\r
+#define QEI_STAT_DIRECTION 0x00000002 // Direction of rotation\r
+#define QEI_STAT_ERROR 0x00000001 // Signalling error detected\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the QEI_POS register.\r
+//\r
+//*****************************************************************************\r
+#define QEI_POS_M 0xFFFFFFFF // Current encoder position\r
+#define QEI_POS_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the QEI_MAXPOS register.\r
+//\r
+//*****************************************************************************\r
+#define QEI_MAXPOS_M 0xFFFFFFFF // Maximum encoder position\r
+#define QEI_MAXPOS_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the QEI_LOAD register.\r
+//\r
+//*****************************************************************************\r
+#define QEI_LOAD_M 0xFFFFFFFF // Velocity timer load value\r
+#define QEI_LOAD_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the QEI_TIME register.\r
+//\r
+//*****************************************************************************\r
+#define QEI_TIME_M 0xFFFFFFFF // Velocity timer current value\r
+#define QEI_TIME_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the QEI_COUNT register.\r
+//\r
+//*****************************************************************************\r
+#define QEI_COUNT_M 0xFFFFFFFF // Encoder running pulse count\r
+#define QEI_COUNT_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the QEI_SPEED register.\r
+//\r
+//*****************************************************************************\r
+#define QEI_SPEED_M 0xFFFFFFFF // Encoder pulse count\r
+#define QEI_SPEED_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the QEI_INTEN register.\r
+//\r
+//*****************************************************************************\r
+#define QEI_INTEN_ERROR 0x00000008 // Phase error detected\r
+#define QEI_INTEN_DIR 0x00000004 // Direction change\r
+#define QEI_INTEN_TIMER 0x00000002 // Velocity timer expired\r
+#define QEI_INTEN_INDEX 0x00000001 // Index pulse detected\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the QEI_RIS register.\r
+//\r
+//*****************************************************************************\r
+#define QEI_RIS_ERROR 0x00000008 // Phase error detected\r
+#define QEI_RIS_DIR 0x00000004 // Direction change\r
+#define QEI_RIS_TIMER 0x00000002 // Velocity timer expired\r
+#define QEI_RIS_INDEX 0x00000001 // Index pulse detected\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the QEI_ISC register.\r
+//\r
+//*****************************************************************************\r
+#define QEI_INT_ERROR 0x00000008 // Phase error detected\r
+#define QEI_INT_DIR 0x00000004 // Direction change\r
+#define QEI_INT_TIMER 0x00000002 // Velocity timer expired\r
+#define QEI_INT_INDEX 0x00000001 // Index pulse detected\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the reset values for the QEI registers.\r
+//\r
+//*****************************************************************************\r
+#define QEI_RV_CTL 0x00000000 // Configuration and control reg.\r
+#define QEI_RV_STAT 0x00000000 // Status register\r
+#define QEI_RV_POS 0x00000000 // Current position register\r
+#define QEI_RV_MAXPOS 0x00000000 // Maximum position register\r
+#define QEI_RV_LOAD 0x00000000 // Velocity timer load register\r
+#define QEI_RV_TIME 0x00000000 // Velocity timer register\r
+#define QEI_RV_COUNT 0x00000000 // Velocity pulse count register\r
+#define QEI_RV_SPEED 0x00000000 // Velocity speed register\r
+#define QEI_RV_INTEN 0x00000000 // Interrupt enable register\r
+#define QEI_RV_RIS 0x00000000 // Raw interrupt status register\r
+#define QEI_RV_ISC 0x00000000 // Interrupt status register\r
+\r
+#endif // __HW_QEI_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_ssi.h - Macros used when accessing the SSI hardware.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_SSI_H__\r
+#define __HW_SSI_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the offsets of the SSI registers.\r
+//\r
+//*****************************************************************************\r
+#define SSI_O_CR0 0x00000000 // Control register 0\r
+#define SSI_O_CR1 0x00000004 // Control register 1\r
+#define SSI_O_DR 0x00000008 // Data register\r
+#define SSI_O_SR 0x0000000C // Status register\r
+#define SSI_O_CPSR 0x00000010 // Clock prescale register\r
+#define SSI_O_IM 0x00000014 // Int mask set and clear register\r
+#define SSI_O_RIS 0x00000018 // Raw interrupt register\r
+#define SSI_O_MIS 0x0000001C // Masked interrupt register\r
+#define SSI_O_ICR 0x00000020 // Interrupt clear register\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SSI Control register 0.\r
+//\r
+//*****************************************************************************\r
+#define SSI_CR0_SCR 0x0000FF00 // Serial clock rate\r
+#define SSI_CR0_SPH 0x00000080 // SSPCLKOUT phase\r
+#define SSI_CR0_SPO 0x00000040 // SSPCLKOUT polarity\r
+#define SSI_CR0_FRF_MASK 0x00000030 // Frame format mask\r
+#define SSI_CR0_FRF_MOTO 0x00000000 // Motorola SPI frame format\r
+#define SSI_CR0_FRF_TI 0x00000010 // TI sync serial frame format\r
+#define SSI_CR0_FRF_NMW 0x00000020 // National Microwire frame format\r
+#define SSI_CR0_DSS 0x0000000F // Data size select\r
+#define SSI_CR0_DSS_4 0x00000003 // 4 bit data\r
+#define SSI_CR0_DSS_5 0x00000004 // 5 bit data\r
+#define SSI_CR0_DSS_6 0x00000005 // 6 bit data\r
+#define SSI_CR0_DSS_7 0x00000006 // 7 bit data\r
+#define SSI_CR0_DSS_8 0x00000007 // 8 bit data\r
+#define SSI_CR0_DSS_9 0x00000008 // 9 bit data\r
+#define SSI_CR0_DSS_10 0x00000009 // 10 bit data\r
+#define SSI_CR0_DSS_11 0x0000000A // 11 bit data\r
+#define SSI_CR0_DSS_12 0x0000000B // 12 bit data\r
+#define SSI_CR0_DSS_13 0x0000000C // 13 bit data\r
+#define SSI_CR0_DSS_14 0x0000000D // 14 bit data\r
+#define SSI_CR0_DSS_15 0x0000000E // 15 bit data\r
+#define SSI_CR0_DSS_16 0x0000000F // 16 bit data\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SSI Control register 1.\r
+//\r
+//*****************************************************************************\r
+#define SSI_CR1_SOD 0x00000008 // Slave mode output disable\r
+#define SSI_CR1_MS 0x00000004 // Master or slave mode select\r
+#define SSI_CR1_SSE 0x00000002 // Sync serial port enable\r
+#define SSI_CR1_LBM 0x00000001 // Loopback mode\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SSI Status register.\r
+//\r
+//*****************************************************************************\r
+#define SSI_SR_BSY 0x00000010 // SSI busy\r
+#define SSI_SR_RFF 0x00000008 // RX FIFO full\r
+#define SSI_SR_RNE 0x00000004 // RX FIFO not empty\r
+#define SSI_SR_TNF 0x00000002 // TX FIFO not full\r
+#define SSI_SR_TFE 0x00000001 // TX FIFO empty\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SSI clock prescale register.\r
+//\r
+//*****************************************************************************\r
+#define SSI_CPSR_CPSDVSR_MASK 0x000000FF // Clock prescale\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define information concerning the SSI Data register.\r
+//\r
+//*****************************************************************************\r
+#define TX_FIFO_SIZE (8) // Number of entries in the TX FIFO\r
+#define RX_FIFO_SIZE (8) // Number of entries in the RX FIFO\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the interrupt mask set and clear,\r
+// raw interrupt, masked interrupt, and interrupt clear registers.\r
+//\r
+//*****************************************************************************\r
+#define SSI_INT_TXFF 0x00000008 // TX FIFO interrupt\r
+#define SSI_INT_RXFF 0x00000004 // RX FIFO interrupt\r
+#define SSI_INT_RXTO 0x00000002 // RX timeout interrupt\r
+#define SSI_INT_RXOR 0x00000001 // RX overrun interrupt\r
+\r
+#endif // __HW_SSI_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_sysctl.h - Macros used when accessing the system control hardware.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_SYSCTL_H__\r
+#define __HW_SYSCTL_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the addresses of the system control registers.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_DID0 0x400fe000 // Device identification register 0\r
+#define SYSCTL_DID1 0x400fe004 // Device identification register 1\r
+#define SYSCTL_DC0 0x400fe008 // Device capabilities register 0\r
+#define SYSCTL_DC1 0x400fe010 // Device capabilities register 1\r
+#define SYSCTL_DC2 0x400fe014 // Device capabilities register 2\r
+#define SYSCTL_DC3 0x400fe018 // Device capabilities register 3\r
+#define SYSCTL_DC4 0x400fe01C // Device capabilities register 4\r
+#define SYSCTL_PBORCTL 0x400fe030 // POR/BOR reset control register\r
+#define SYSCTL_LDOPCTL 0x400fe034 // LDO power control register\r
+#define SYSCTL_SRCR0 0x400fe040 // Software reset control reg 0\r
+#define SYSCTL_SRCR1 0x400fe044 // Software reset control reg 1\r
+#define SYSCTL_SRCR2 0x400fe048 // Software reset control reg 2\r
+#define SYSCTL_RIS 0x400fe050 // Raw interrupt status register\r
+#define SYSCTL_IMC 0x400fe054 // Interrupt mask/control register\r
+#define SYSCTL_MISC 0x400fe058 // Interrupt status register\r
+#define SYSCTL_RESC 0x400fe05c // Reset cause register\r
+#define SYSCTL_RCC 0x400fe060 // Run-mode clock config register\r
+#define SYSCTL_PLLCFG 0x400fe064 // PLL configuration register\r
+#define SYSCTL_RCC2 0x400fe070 // Run-mode clock config register 2\r
+#define SYSCTL_RCGC0 0x400fe100 // Run-mode clock gating register 0\r
+#define SYSCTL_RCGC1 0x400fe104 // Run-mode clock gating register 1\r
+#define SYSCTL_RCGC2 0x400fe108 // Run-mode clock gating register 2\r
+#define SYSCTL_SCGC0 0x400fe110 // Sleep-mode clock gating reg 0\r
+#define SYSCTL_SCGC1 0x400fe114 // Sleep-mode clock gating reg 1\r
+#define SYSCTL_SCGC2 0x400fe118 // Sleep-mode clock gating reg 2\r
+#define SYSCTL_DCGC0 0x400fe120 // Deep Sleep-mode clock gate reg 0\r
+#define SYSCTL_DCGC1 0x400fe124 // Deep Sleep-mode clock gate reg 1\r
+#define SYSCTL_DCGC2 0x400fe128 // Deep Sleep-mode clock gate reg 2\r
+#define SYSCTL_DSLPCLKCFG 0x400fe144 // Deep Sleep-mode clock config reg\r
+#define SYSCTL_CLKVCLR 0x400fe150 // Clock verifcation clear register\r
+#define SYSCTL_LDOARST 0x400fe160 // LDO reset control register\r
+#define SYSCTL_USER0 0x400fe1e0 // NV User Register 0\r
+#define SYSCTL_USER1 0x400fe1e4 // NV User Register 1\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_DID0 register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_DID0_VER_MASK 0x70000000 // DID0 version mask\r
+#define SYSCTL_DID0_VER_0 0x00000000 // DID0 version 0\r
+#define SYSCTL_DID0_VER_1 0x10000000 // DID0 version 1\r
+#define SYSCTL_DID0_CLASS_MASK 0x00FF0000 // Device Class\r
+#define SYSCTL_DID0_CLASS_SANDSTORM 0x00000000 // LM3Snnn Sandstorm Device\r
+#define SYSCTL_DID0_CLASS_FURY 0x00010000 // LM3Snnnn Fury Device\r
+#define SYSCTL_DID0_MAJ_MASK 0x0000FF00 // Major revision mask\r
+#define SYSCTL_DID0_MAJ_A 0x00000000 // Major revision A\r
+#define SYSCTL_DID0_MAJ_B 0x00000100 // Major revision B\r
+#define SYSCTL_DID0_MAJ_C 0x00000200 // Major revision C\r
+#define SYSCTL_DID0_MIN_MASK 0x000000FF // Minor revision mask\r
+#define SYSCTL_DID0_MIN_0 0x00000000 // Minor revision 0\r
+#define SYSCTL_DID0_MIN_1 0x00000001 // Minor revision 1\r
+#define SYSCTL_DID0_MIN_2 0x00000002 // Minor revision 2\r
+#define SYSCTL_DID0_MIN_3 0x00000003 // Minor revision 3\r
+#define SYSCTL_DID0_MIN_4 0x00000004 // Minor revision 4\r
+#define SYSCTL_DID0_MIN_5 0x00000005 // Minor revision 5\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_DID1 register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_DID1_VER_MASK 0xF0000000 // Register version mask\r
+#define SYSCTL_DID1_FAM_MASK 0x0F000000 // Family mask\r
+#define SYSCTL_DID1_FAM_S 0x00000000 // Stellaris family\r
+#define SYSCTL_DID1_PRTNO_MASK 0x00FF0000 // Part number mask\r
+#define SYSCTL_DID1_PRTNO_101 0x00010000 // LM3S101\r
+#define SYSCTL_DID1_PRTNO_102 0x00020000 // LM3S102\r
+#define SYSCTL_DID1_PRTNO_301 0x00110000 // LM3S301\r
+#define SYSCTL_DID1_PRTNO_310 0x00120000 // LM3S310\r
+#define SYSCTL_DID1_PRTNO_315 0x00130000 // LM3S315\r
+#define SYSCTL_DID1_PRTNO_316 0x00140000 // LM3S316\r
+#define SYSCTL_DID1_PRTNO_317 0x00170000 // LM3S317\r
+#define SYSCTL_DID1_PRTNO_328 0x00150000 // LM3S328\r
+#define SYSCTL_DID1_PRTNO_601 0x00210000 // LM3S601\r
+#define SYSCTL_DID1_PRTNO_610 0x00220000 // LM3S610\r
+#define SYSCTL_DID1_PRTNO_611 0x00230000 // LM3S611\r
+#define SYSCTL_DID1_PRTNO_612 0x00240000 // LM3S612\r
+#define SYSCTL_DID1_PRTNO_613 0x00250000 // LM3S613\r
+#define SYSCTL_DID1_PRTNO_615 0x00260000 // LM3S615\r
+#define SYSCTL_DID1_PRTNO_617 0x00280000 // LM3S617\r
+#define SYSCTL_DID1_PRTNO_618 0x00290000 // LM3S618\r
+#define SYSCTL_DID1_PRTNO_628 0x00270000 // LM3S628\r
+#define SYSCTL_DID1_PRTNO_801 0x00310000 // LM3S801\r
+#define SYSCTL_DID1_PRTNO_811 0x00320000 // LM3S811\r
+#define SYSCTL_DID1_PRTNO_812 0x00330000 // LM3S812\r
+#define SYSCTL_DID1_PRTNO_815 0x00340000 // LM3S815\r
+#define SYSCTL_DID1_PRTNO_817 0x00360000 // LM3S817\r
+#define SYSCTL_DID1_PRTNO_818 0x00370000 // LM3S818\r
+#define SYSCTL_DID1_PRTNO_828 0x00350000 // LM3S828\r
+#define SYSCTL_DID1_PRTNO_2110 0x00510000 // LM3S2110\r
+#define SYSCTL_DID1_PRTNO_2139 0x00840000 // LM3S2139\r
+#define SYSCTL_DID1_PRTNO_2410 0x00A20000 // LM3S2410\r
+#define SYSCTL_DID1_PRTNO_2412 0x00590000 // LM3S2412\r
+#define SYSCTL_DID1_PRTNO_2432 0x00560000 // LM3S2432\r
+#define SYSCTL_DID1_PRTNO_2533 0x005A0000 // LM3S2533\r
+#define SYSCTL_DID1_PRTNO_2620 0x00570000 // LM3S2620\r
+#define SYSCTL_DID1_PRTNO_2637 0x00850000 // LM3S2637\r
+#define SYSCTL_DID1_PRTNO_2651 0x00530000 // LM3S2651\r
+#define SYSCTL_DID1_PRTNO_2730 0x00A40000 // LM3S2730\r
+#define SYSCTL_DID1_PRTNO_2739 0x00520000 // LM3S2739\r
+#define SYSCTL_DID1_PRTNO_2939 0x00540000 // LM3S2939\r
+#define SYSCTL_DID1_PRTNO_2948 0x008F0000 // LM3S2948\r
+#define SYSCTL_DID1_PRTNO_2950 0x00580000 // LM3S2950\r
+#define SYSCTL_DID1_PRTNO_2965 0x00550000 // LM3S2965\r
+#define SYSCTL_DID1_PRTNO_6100 0x00A10000 // LM3S6100\r
+#define SYSCTL_DID1_PRTNO_6110 0x00740000 // LM3S6110\r
+#define SYSCTL_DID1_PRTNO_6420 0x00A50000 // LM3S6420\r
+#define SYSCTL_DID1_PRTNO_6422 0x00820000 // LM3S6422\r
+#define SYSCTL_DID1_PRTNO_6432 0x00750000 // LM3S6432\r
+#define SYSCTL_DID1_PRTNO_6610 0x00710000 // LM3S6610\r
+#define SYSCTL_DID1_PRTNO_6633 0x00830000 // LM3S6633\r
+#define SYSCTL_DID1_PRTNO_6637 0x008B0000 // LM3S6637\r
+#define SYSCTL_DID1_PRTNO_6730 0x00A30000 // LM3S6730\r
+#define SYSCTL_DID1_PRTNO_6938 0x00890000 // LM3S6938\r
+#define SYSCTL_DID1_PRTNO_6952 0x00780000 // LM3S6952\r
+#define SYSCTL_DID1_PRTNO_6965 0x00730000 // LM3S6965\r
+#define SYSCTL_DID1_PINCNT_MASK 0x0000E000 // Pin count\r
+#define SYSCTL_DID1_PINCNT_100 0x00004000 // 100 pin package\r
+#define SYSCTL_DID1_TEMP_MASK 0x000000E0 // Temperature range mask\r
+#define SYSCTL_DID1_TEMP_C 0x00000000 // Commercial temp range (0..70C)\r
+#define SYSCTL_DID1_TEMP_I 0x00000020 // Industrial temp range (-40..85C)\r
+#define SYSCTL_DID1_PKG_MASK 0x00000018 // Package mask\r
+#define SYSCTL_DID1_PKG_28SOIC 0x00000000 // 28-pin SOIC\r
+#define SYSCTL_DID1_PKG_48QFP 0x00000008 // 48-pin QFP\r
+#define SYSCTL_DID1_ROHS 0x00000004 // Part is RoHS compliant\r
+#define SYSCTL_DID1_QUAL_MASK 0x00000003 // Qualification status mask\r
+#define SYSCTL_DID1_QUAL_ES 0x00000000 // Engineering sample (unqualified)\r
+#define SYSCTL_DID1_QUAL_PP 0x00000001 // Pilot production (unqualified)\r
+#define SYSCTL_DID1_QUAL_FQ 0x00000002 // Fully qualified\r
+#define SYSCTL_DID1_PRTNO_SHIFT 16\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_DC0 register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_DC0_SRAMSZ_MASK 0xFFFF0000 // SRAM size mask\r
+#define SYSCTL_DC0_SRAMSZ_2KB 0x00070000 // 2 KB of SRAM\r
+#define SYSCTL_DC0_SRAMSZ_4KB 0x000F0000 // 4 KB of SRAM\r
+#define SYSCTL_DC0_SRAMSZ_8KB 0x001F0000 // 8 KB of SRAM\r
+#define SYSCTL_DC0_SRAMSZ_16KB 0x003F0000 // 16 KB of SRAM\r
+#define SYSCTL_DC0_SRAMSZ_32KB 0x007F0000 // 32 KB of SRAM\r
+#define SYSCTL_DC0_SRAMSZ_64KB 0x00FF0000 // 64 KB of SRAM\r
+#define SYSCTL_DC0_FLASHSZ_MASK 0x0000FFFF // Flash size mask\r
+#define SYSCTL_DC0_FLASHSZ_8KB 0x00000003 // 8 KB of flash\r
+#define SYSCTL_DC0_FLASHSZ_16KB 0x00000007 // 16 KB of flash\r
+#define SYSCTL_DC0_FLASHSZ_32KB 0x0000000F // 32 KB of flash\r
+#define SYSCTL_DC0_FLASHSZ_64KB 0x0000001F // 64 KB of flash\r
+#define SYSCTL_DC0_FLASHSZ_96KB 0x0000002F // 96 KB of flash\r
+#define SYSCTL_DC0_FLASHSZ_128K 0x0000003F // 128 KB of flash\r
+#define SYSCTL_DC0_FLASHSZ_256K 0x0000007F // 256 KB of flash\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_DC1 register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_DC1_CAN1 0x02000000 // CAN1 module present\r
+#define SYSCTL_DC1_CAN0 0x01000000 // CAN0 module present\r
+#define SYSCTL_DC1_PWM 0x00100000 // PWM module present\r
+#define SYSCTL_DC1_ADC 0x00010000 // ADC module present\r
+#define SYSCTL_DC1_SYSDIV_MASK 0x0000F000 // Minimum system divider mask\r
+#define SYSCTL_DC1_ADCSPD_MASK 0x00000F00 // ADC speed mask\r
+#define SYSCTL_DC1_ADCSPD_1M 0x00000300 // 1Msps ADC\r
+#define SYSCTL_DC1_ADCSPD_500K 0x00000200 // 500Ksps ADC\r
+#define SYSCTL_DC1_ADCSPD_250K 0x00000100 // 250Ksps ADC\r
+#define SYSCTL_DC1_ADCSPD_125K 0x00000000 // 125Ksps ADC\r
+#define SYSCTL_DC1_MPU 0x00000080 // Cortex M3 MPU present\r
+#define SYSCTL_DC1_HIB 0x00000040 // Hibernation module present\r
+#define SYSCTL_DC1_TEMP 0x00000020 // Temperature sensor present\r
+#define SYSCTL_DC1_PLL 0x00000010 // PLL present\r
+#define SYSCTL_DC1_WDOG 0x00000008 // Watchdog present\r
+#define SYSCTL_DC1_SWO 0x00000004 // Serial wire output present\r
+#define SYSCTL_DC1_SWD 0x00000002 // Serial wire debug present\r
+#define SYSCTL_DC1_JTAG 0x00000001 // JTAG debug present\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_DC2 register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_DC2_COMP2 0x04000000 // Analog comparator 2 present\r
+#define SYSCTL_DC2_COMP1 0x02000000 // Analog comparator 1 present\r
+#define SYSCTL_DC2_COMP0 0x01000000 // Analog comparator 0 present\r
+#define SYSCTL_DC2_TIMER3 0x00080000 // Timer 3 present\r
+#define SYSCTL_DC2_TIMER2 0x00040000 // Timer 2 present\r
+#define SYSCTL_DC2_TIMER1 0x00020000 // Timer 1 present\r
+#define SYSCTL_DC2_TIMER0 0x00010000 // Timer 0 present\r
+#define SYSCTL_DC2_I2C1 0x00002000 // I2C 1 present\r
+#define SYSCTL_DC2_I2C0 0x00001000 // I2C 0 present\r
+#ifndef DEPRECATED\r
+#define SYSCTL_DC2_I2C 0x00001000 // I2C present\r
+#endif\r
+#define SYSCTL_DC2_QEI1 0x00000200 // QEI 1 present\r
+#define SYSCTL_DC2_QEI0 0x00000100 // QEI 0 present\r
+#ifndef DEPRECATED\r
+#define SYSCTL_DC2_QEI 0x00000100 // QEI present\r
+#endif\r
+#define SYSCTL_DC2_SSI1 0x00000020 // SSI 1 present\r
+#define SYSCTL_DC2_SSI0 0x00000010 // SSI 0 present\r
+#ifndef DEPRECATED\r
+#define SYSCTL_DC2_SSI 0x00000010 // SSI present\r
+#endif\r
+#define SYSCTL_DC2_UART2 0x00000004 // UART 2 present\r
+#define SYSCTL_DC2_UART1 0x00000002 // UART 1 present\r
+#define SYSCTL_DC2_UART0 0x00000001 // UART 0 present\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_DC3 register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_DC3_32KHZ 0x80000000 // 32kHz pin present\r
+#define SYSCTL_DC3_CCP5 0x20000000 // CCP5 pin present\r
+#define SYSCTL_DC3_CCP4 0x10000000 // CCP4 pin present\r
+#define SYSCTL_DC3_CCP3 0x08000000 // CCP3 pin present\r
+#define SYSCTL_DC3_CCP2 0x04000000 // CCP2 pin present\r
+#define SYSCTL_DC3_CCP1 0x02000000 // CCP1 pin present\r
+#define SYSCTL_DC3_CCP0 0x01000000 // CCP0 pin present\r
+#define SYSCTL_DC3_ADC7 0x00800000 // ADC7 pin present\r
+#define SYSCTL_DC3_ADC6 0x00400000 // ADC6 pin present\r
+#define SYSCTL_DC3_ADC5 0x00200000 // ADC5 pin present\r
+#define SYSCTL_DC3_ADC4 0x00100000 // ADC4 pin present\r
+#define SYSCTL_DC3_ADC3 0x00080000 // ADC3 pin present\r
+#define SYSCTL_DC3_ADC2 0x00040000 // ADC2 pin present\r
+#define SYSCTL_DC3_ADC1 0x00020000 // ADC1 pin present\r
+#define SYSCTL_DC3_ADC0 0x00010000 // ADC0 pin present\r
+#define SYSCTL_DC3_MC_FAULT0 0x00008000 // MC0 fault pin present\r
+#define SYSCTL_DC3_C2O 0x00004000 // C2o pin present\r
+#define SYSCTL_DC3_C2PLUS 0x00002000 // C2+ pin present\r
+#define SYSCTL_DC3_C2MINUS 0x00001000 // C2- pin present\r
+#define SYSCTL_DC3_C1O 0x00000800 // C1o pin present\r
+#define SYSCTL_DC3_C1PLUS 0x00000400 // C1+ pin present\r
+#define SYSCTL_DC3_C1MINUS 0x00000200 // C1- pin present\r
+#define SYSCTL_DC3_C0O 0x00000100 // C0o pin present\r
+#define SYSCTL_DC3_C0PLUS 0x00000080 // C0+ pin present\r
+#define SYSCTL_DC3_C0MINUS 0x00000040 // C0- pin present\r
+#define SYSCTL_DC3_PWM5 0x00000020 // PWM5 pin present\r
+#define SYSCTL_DC3_PWM4 0x00000010 // PWM4 pin present\r
+#define SYSCTL_DC3_PWM3 0x00000008 // PWM3 pin present\r
+#define SYSCTL_DC3_PWM2 0x00000004 // PWM2 pin present\r
+#define SYSCTL_DC3_PWM1 0x00000002 // PWM1 pin present\r
+#define SYSCTL_DC3_PWM0 0x00000001 // PWM0 pin present\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_DC4 register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_DC4_ETH 0x50000000 // Ethernet present\r
+#define SYSCTL_DC4_GPIOH 0x00000080 // GPIO port H present\r
+#define SYSCTL_DC4_GPIOG 0x00000040 // GPIO port G present\r
+#define SYSCTL_DC4_GPIOF 0x00000020 // GPIO port F present\r
+#define SYSCTL_DC4_GPIOE 0x00000010 // GPIO port E present\r
+#define SYSCTL_DC4_GPIOD 0x00000008 // GPIO port D present\r
+#define SYSCTL_DC4_GPIOC 0x00000004 // GPIO port C present\r
+#define SYSCTL_DC4_GPIOB 0x00000002 // GPIO port B present\r
+#define SYSCTL_DC4_GPIOA 0x00000001 // GPIO port A present\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_PBORCTL register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_PBORCTL_BOR_MASK 0x0000FFFC // BOR wait timer\r
+#define SYSCTL_PBORCTL_BORIOR 0x00000002 // BOR interrupt or reset\r
+#define SYSCTL_PBORCTL_BORWT 0x00000001 // BOR wait and check for noise\r
+#define SYSCTL_PBORCTL_BOR_SH 2\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_LDOPCTL register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_LDOPCTL_MASK 0x0000003F // Voltage adjust mask\r
+#define SYSCTL_LDOPCTL_2_25V 0x00000005 // LDO output of 2.25V\r
+#define SYSCTL_LDOPCTL_2_30V 0x00000004 // LDO output of 2.30V\r
+#define SYSCTL_LDOPCTL_2_35V 0x00000003 // LDO output of 2.35V\r
+#define SYSCTL_LDOPCTL_2_40V 0x00000002 // LDO output of 2.40V\r
+#define SYSCTL_LDOPCTL_2_45V 0x00000001 // LDO output of 2.45V\r
+#define SYSCTL_LDOPCTL_2_50V 0x00000000 // LDO output of 2.50V\r
+#define SYSCTL_LDOPCTL_2_55V 0x0000001F // LDO output of 2.55V\r
+#define SYSCTL_LDOPCTL_2_60V 0x0000001E // LDO output of 2.60V\r
+#define SYSCTL_LDOPCTL_2_65V 0x0000001D // LDO output of 2.65V\r
+#define SYSCTL_LDOPCTL_2_70V 0x0000001C // LDO output of 2.70V\r
+#define SYSCTL_LDOPCTL_2_75V 0x0000001B // LDO output of 2.75V\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_SRCR0, SYSCTL_RCGC0,\r
+// SYSCTL_SCGC0, and SYSCTL_DCGC0 registers.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_SET0_CAN1 0x02000000 // CAN 1 module\r
+#define SYSCTL_SET0_CAN0 0x01000000 // CAN 0 module\r
+#define SYSCTL_SET0_PWM 0x00100000 // PWM module\r
+#define SYSCTL_SET0_ADC 0x00010000 // ADC module\r
+#define SYSCTL_SET0_ADCSPD_MASK 0x00000F00 // ADC speed mask\r
+#define SYSCTL_SET0_ADCSPD_1M 0x00000300 // 1Msps ADC\r
+#define SYSCTL_SET0_ADCSPD_500K 0x00000200 // 500Ksps ADC\r
+#define SYSCTL_SET0_ADCSPD_250K 0x00000100 // 250Ksps ADC\r
+#define SYSCTL_SET0_ADCSPD_125K 0x00000000 // 125Ksps ADC\r
+#define SYSCTL_SET0_HIB 0x00000040 // Hibernation module\r
+#define SYSCTL_SET0_WDOG 0x00000008 // Watchdog module\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_SRCR1, SYSCTL_RCGC1,\r
+// SYSCTL_SCGC1, and SYSCTL_DCGC1 registers.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_SET1_COMP2 0x04000000 // Analog comparator module 2\r
+#define SYSCTL_SET1_COMP1 0x02000000 // Analog comparator module 1\r
+#define SYSCTL_SET1_COMP0 0x01000000 // Analog comparator module 0\r
+#define SYSCTL_SET1_TIMER3 0x00080000 // Timer module 3\r
+#define SYSCTL_SET1_TIMER2 0x00040000 // Timer module 2\r
+#define SYSCTL_SET1_TIMER1 0x00020000 // Timer module 1\r
+#define SYSCTL_SET1_TIMER0 0x00010000 // Timer module 0\r
+#define SYSCTL_SET1_I2C1 0x00002000 // I2C module 1\r
+#define SYSCTL_SET1_I2C0 0x00001000 // I2C module 0\r
+#ifndef DEPRECATED\r
+#define SYSCTL_SET1_I2C 0x00001000 // I2C module\r
+#endif\r
+#define SYSCTL_SET1_QEI1 0x00000200 // QEI module 1\r
+#define SYSCTL_SET1_QEI0 0x00000100 // QEI module 0\r
+#ifndef DEPRECATED\r
+#define SYSCTL_SET1_QEI 0x00000100 // QEI module\r
+#endif\r
+#define SYSCTL_SET1_SSI1 0x00000020 // SSI module 1\r
+#define SYSCTL_SET1_SSI0 0x00000010 // SSI module 0\r
+#ifndef DEPRECATED\r
+#define SYSCTL_SET1_SSI 0x00000010 // SSI module\r
+#endif\r
+#define SYSCTL_SET1_UART2 0x00000004 // UART module 2\r
+#define SYSCTL_SET1_UART1 0x00000002 // UART module 1\r
+#define SYSCTL_SET1_UART0 0x00000001 // UART module 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_SRCR2, SYSCTL_RCGC2,\r
+// SYSCTL_SCGC2, and SYSCTL_DCGC2 registers.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_SET2_ETH 0x50000000 // ETH module\r
+#define SYSCTL_SET2_GPIOH 0x00000080 // GPIO H module\r
+#define SYSCTL_SET2_GPIOG 0x00000040 // GPIO G module\r
+#define SYSCTL_SET2_GPIOF 0x00000020 // GPIO F module\r
+#define SYSCTL_SET2_GPIOE 0x00000010 // GPIO E module\r
+#define SYSCTL_SET2_GPIOD 0x00000008 // GPIO D module\r
+#define SYSCTL_SET2_GPIOC 0x00000004 // GPIO C module\r
+#define SYSCTL_SET2_GPIOB 0x00000002 // GPIO B module\r
+#define SYSCTL_SET2_GPIOA 0x00000001 // GIPO A module\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_RIS, SYSCTL_IMC, and\r
+// SYSCTL_IMS registers.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_INT_PLL_LOCK 0x00000040 // PLL lock interrupt\r
+#define SYSCTL_INT_CUR_LIMIT 0x00000020 // Current limit interrupt\r
+#define SYSCTL_INT_IOSC_FAIL 0x00000010 // Internal oscillator failure int\r
+#define SYSCTL_INT_MOSC_FAIL 0x00000008 // Main oscillator failure int\r
+#define SYSCTL_INT_POR 0x00000004 // Power on reset interrupt\r
+#define SYSCTL_INT_BOR 0x00000002 // Brown out interrupt\r
+#define SYSCTL_INT_PLL_FAIL 0x00000001 // PLL failure interrupt\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_RESC register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_RESC_LDO 0x00000020 // LDO power OK lost reset\r
+#define SYSCTL_RESC_SW 0x00000010 // Software reset\r
+#define SYSCTL_RESC_WDOG 0x00000008 // Watchdog reset\r
+#define SYSCTL_RESC_BOR 0x00000004 // Brown-out reset\r
+#define SYSCTL_RESC_POR 0x00000002 // Power on reset\r
+#define SYSCTL_RESC_EXT 0x00000001 // External reset\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_RCC register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_RCC_ACG 0x08000000 // Automatic clock gating\r
+#define SYSCTL_RCC_SYSDIV_MASK 0x07800000 // System clock divider\r
+#define SYSCTL_RCC_SYSDIV_2 0x00800000 // System clock /2\r
+#define SYSCTL_RCC_SYSDIV_3 0x01000000 // System clock /3\r
+#define SYSCTL_RCC_SYSDIV_4 0x01800000 // System clock /4\r
+#define SYSCTL_RCC_SYSDIV_5 0x02000000 // System clock /5\r
+#define SYSCTL_RCC_SYSDIV_6 0x02800000 // System clock /6\r
+#define SYSCTL_RCC_SYSDIV_7 0x03000000 // System clock /7\r
+#define SYSCTL_RCC_SYSDIV_8 0x03800000 // System clock /8\r
+#define SYSCTL_RCC_SYSDIV_9 0x04000000 // System clock /9\r
+#define SYSCTL_RCC_SYSDIV_10 0x04800000 // System clock /10\r
+#define SYSCTL_RCC_SYSDIV_11 0x05000000 // System clock /11\r
+#define SYSCTL_RCC_SYSDIV_12 0x05800000 // System clock /12\r
+#define SYSCTL_RCC_SYSDIV_13 0x06000000 // System clock /13\r
+#define SYSCTL_RCC_SYSDIV_14 0x06800000 // System clock /14\r
+#define SYSCTL_RCC_SYSDIV_15 0x07000000 // System clock /15\r
+#define SYSCTL_RCC_SYSDIV_16 0x07800000 // System clock /16\r
+#define SYSCTL_RCC_USE_SYSDIV 0x00400000 // Use sytem clock divider\r
+#define SYSCTL_RCC_USE_PWMDIV 0x00100000 // Use PWM clock divider\r
+#define SYSCTL_RCC_PWMDIV_MASK 0x000E0000 // PWM clock divider\r
+#define SYSCTL_RCC_PWMDIV_2 0x00000000 // PWM clock /2\r
+#define SYSCTL_RCC_PWMDIV_4 0x00020000 // PWM clock /4\r
+#define SYSCTL_RCC_PWMDIV_8 0x00040000 // PWM clock /8\r
+#define SYSCTL_RCC_PWMDIV_16 0x00060000 // PWM clock /16\r
+#define SYSCTL_RCC_PWMDIV_32 0x00080000 // PWM clock /32\r
+#define SYSCTL_RCC_PWMDIV_64 0x000A0000 // PWM clock /64\r
+#define SYSCTL_RCC_PWRDN 0x00002000 // PLL power down\r
+#define SYSCTL_RCC_OE 0x00001000 // PLL output enable\r
+#define SYSCTL_RCC_BYPASS 0x00000800 // PLL bypass\r
+#define SYSCTL_RCC_PLLVER 0x00000400 // PLL verification timer enable\r
+#define SYSCTL_RCC_XTAL_MASK 0x000003C0 // Crystal attached to main osc\r
+#define SYSCTL_RCC_XTAL_3_57MHZ 0x00000100 // Using a 3.579545MHz crystal\r
+#define SYSCTL_RCC_XTAL_3_68MHz 0x00000140 // Using a 3.6864MHz crystal\r
+#define SYSCTL_RCC_XTAL_4MHz 0x00000180 // Using a 4MHz crystal\r
+#define SYSCTL_RCC_XTAL_4_09MHZ 0x000001C0 // Using a 4.096MHz crystal\r
+#define SYSCTL_RCC_XTAL_4_91MHZ 0x00000200 // Using a 4.9152MHz crystal\r
+#define SYSCTL_RCC_XTAL_5MHZ 0x00000240 // Using a 5MHz crystal\r
+#define SYSCTL_RCC_XTAL_5_12MHZ 0x00000280 // Using a 5.12MHz crystal\r
+#define SYSCTL_RCC_XTAL_6MHZ 0x000002C0 // Using a 6MHz crystal\r
+#define SYSCTL_RCC_XTAL_6_14MHZ 0x00000300 // Using a 6.144MHz crystal\r
+#define SYSCTL_RCC_XTAL_7_37MHZ 0x00000340 // Using a 7.3728MHz crystal\r
+#define SYSCTL_RCC_XTAL_8MHZ 0x00000380 // Using a 8MHz crystal\r
+#define SYSCTL_RCC_XTAL_8_19MHZ 0x000003C0 // Using a 8.192MHz crystal\r
+#define SYSCTL_RCC_OSCSRC_MASK 0x00000030 // Oscillator input select\r
+#define SYSCTL_RCC_OSCSRC_MAIN 0x00000000 // Use the main oscillator\r
+#define SYSCTL_RCC_OSCSRC_INT 0x00000010 // Use the internal oscillator\r
+#define SYSCTL_RCC_OSCSRC_INT4 0x00000020 // Use the internal oscillator / 4\r
+#define SYSCTL_RCC_IOSCVER 0x00000008 // Int. osc. verification timer en\r
+#define SYSCTL_RCC_MOSCVER 0x00000004 // Main osc. verification timer en\r
+#define SYSCTL_RCC_IOSCDIS 0x00000002 // Internal oscillator disable\r
+#define SYSCTL_RCC_MOSCDIS 0x00000001 // Main oscillator disable\r
+#define SYSCTL_RCC_SYSDIV_SHIFT 23 // Shift to the SYSDIV field\r
+#define SYSCTL_RCC_PWMDIV_SHIFT 17 // Shift to the PWMDIV field\r
+#define SYSCTL_RCC_XTAL_SHIFT 6 // Shift to the XTAL field\r
+#define SYSCTL_RCC_OSCSRC_SHIFT 4 // Shift to the OSCSRC field\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_PLLCFG register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_PLLCFG_OD_MASK 0x0000C000 // Output divider\r
+#define SYSCTL_PLLCFG_OD_1 0x00000000 // Output divider is 1\r
+#define SYSCTL_PLLCFG_OD_2 0x00004000 // Output divider is 2\r
+#define SYSCTL_PLLCFG_OD_4 0x00008000 // Output divider is 4\r
+#define SYSCTL_PLLCFG_F_MASK 0x00003FE0 // PLL multiplier\r
+#define SYSCTL_PLLCFG_R_MASK 0x0000001F // Input predivider\r
+#define SYSCTL_PLLCFG_F_SHIFT 5\r
+#define SYSCTL_PLLCFG_R_SHIFT 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_RCC2 register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_RCC2_USERCC2 0x80000000 // Use RCC2\r
+#define SYSCTL_RCC2_SYSDIV2_MSK 0x1F800000 // System clock divider\r
+#define SYSCTL_RCC2_SYSDIV2_2 0x00800000 // System clock /2\r
+#define SYSCTL_RCC2_SYSDIV2_3 0x01000000 // System clock /3\r
+#define SYSCTL_RCC2_SYSDIV2_4 0x01800000 // System clock /4\r
+#define SYSCTL_RCC2_SYSDIV2_5 0x02000000 // System clock /5\r
+#define SYSCTL_RCC2_SYSDIV2_6 0x02800000 // System clock /6\r
+#define SYSCTL_RCC2_SYSDIV2_7 0x03000000 // System clock /7\r
+#define SYSCTL_RCC2_SYSDIV2_8 0x03800000 // System clock /8\r
+#define SYSCTL_RCC2_SYSDIV2_9 0x04000000 // System clock /9\r
+#define SYSCTL_RCC2_SYSDIV2_10 0x04800000 // System clock /10\r
+#define SYSCTL_RCC2_SYSDIV2_11 0x05000000 // System clock /11\r
+#define SYSCTL_RCC2_SYSDIV2_12 0x05800000 // System clock /12\r
+#define SYSCTL_RCC2_SYSDIV2_13 0x06000000 // System clock /13\r
+#define SYSCTL_RCC2_SYSDIV2_14 0x06800000 // System clock /14\r
+#define SYSCTL_RCC2_SYSDIV2_15 0x07000000 // System clock /15\r
+#define SYSCTL_RCC2_SYSDIV2_16 0x07800000 // System clock /16\r
+#define SYSCTL_RCC2_SYSDIV2_17 0x08000000 // System clock /17\r
+#define SYSCTL_RCC2_SYSDIV2_18 0x08800000 // System clock /18\r
+#define SYSCTL_RCC2_SYSDIV2_19 0x09000000 // System clock /19\r
+#define SYSCTL_RCC2_SYSDIV2_20 0x09800000 // System clock /20\r
+#define SYSCTL_RCC2_SYSDIV2_21 0x0A000000 // System clock /21\r
+#define SYSCTL_RCC2_SYSDIV2_22 0x0A800000 // System clock /22\r
+#define SYSCTL_RCC2_SYSDIV2_23 0x0B000000 // System clock /23\r
+#define SYSCTL_RCC2_SYSDIV2_24 0x0B800000 // System clock /24\r
+#define SYSCTL_RCC2_SYSDIV2_25 0x0C000000 // System clock /25\r
+#define SYSCTL_RCC2_SYSDIV2_26 0x0C800000 // System clock /26\r
+#define SYSCTL_RCC2_SYSDIV2_27 0x0D000000 // System clock /27\r
+#define SYSCTL_RCC2_SYSDIV2_28 0x0D800000 // System clock /28\r
+#define SYSCTL_RCC2_SYSDIV2_29 0x0E000000 // System clock /29\r
+#define SYSCTL_RCC2_SYSDIV2_30 0x0E800000 // System clock /30\r
+#define SYSCTL_RCC2_SYSDIV2_31 0x0F000000 // System clock /31\r
+#define SYSCTL_RCC2_SYSDIV2_32 0x0F800000 // System clock /32\r
+#define SYSCTL_RCC2_SYSDIV2_33 0x10000000 // System clock /33\r
+#define SYSCTL_RCC2_SYSDIV2_34 0x10800000 // System clock /34\r
+#define SYSCTL_RCC2_SYSDIV2_35 0x11000000 // System clock /35\r
+#define SYSCTL_RCC2_SYSDIV2_36 0x11800000 // System clock /36\r
+#define SYSCTL_RCC2_SYSDIV2_37 0x12000000 // System clock /37\r
+#define SYSCTL_RCC2_SYSDIV2_38 0x12800000 // System clock /38\r
+#define SYSCTL_RCC2_SYSDIV2_39 0x13000000 // System clock /39\r
+#define SYSCTL_RCC2_SYSDIV2_40 0x13800000 // System clock /40\r
+#define SYSCTL_RCC2_SYSDIV2_41 0x14000000 // System clock /41\r
+#define SYSCTL_RCC2_SYSDIV2_42 0x14800000 // System clock /42\r
+#define SYSCTL_RCC2_SYSDIV2_43 0x15000000 // System clock /43\r
+#define SYSCTL_RCC2_SYSDIV2_44 0x15800000 // System clock /44\r
+#define SYSCTL_RCC2_SYSDIV2_45 0x16000000 // System clock /45\r
+#define SYSCTL_RCC2_SYSDIV2_46 0x16800000 // System clock /46\r
+#define SYSCTL_RCC2_SYSDIV2_47 0x17000000 // System clock /47\r
+#define SYSCTL_RCC2_SYSDIV2_48 0x17800000 // System clock /48\r
+#define SYSCTL_RCC2_SYSDIV2_49 0x18000000 // System clock /49\r
+#define SYSCTL_RCC2_SYSDIV2_50 0x18800000 // System clock /50\r
+#define SYSCTL_RCC2_SYSDIV2_51 0x19000000 // System clock /51\r
+#define SYSCTL_RCC2_SYSDIV2_52 0x19800000 // System clock /52\r
+#define SYSCTL_RCC2_SYSDIV2_53 0x1A000000 // System clock /53\r
+#define SYSCTL_RCC2_SYSDIV2_54 0x1A800000 // System clock /54\r
+#define SYSCTL_RCC2_SYSDIV2_55 0x1B000000 // System clock /55\r
+#define SYSCTL_RCC2_SYSDIV2_56 0x1B800000 // System clock /56\r
+#define SYSCTL_RCC2_SYSDIV2_57 0x1C000000 // System clock /57\r
+#define SYSCTL_RCC2_SYSDIV2_58 0x1C800000 // System clock /58\r
+#define SYSCTL_RCC2_SYSDIV2_59 0x1D000000 // System clock /59\r
+#define SYSCTL_RCC2_SYSDIV2_60 0x1D800000 // System clock /60\r
+#define SYSCTL_RCC2_SYSDIV2_61 0x1E000000 // System clock /61\r
+#define SYSCTL_RCC2_SYSDIV2_62 0x1E800000 // System clock /62\r
+#define SYSCTL_RCC2_SYSDIV2_63 0x1F000000 // System clock /63\r
+#define SYSCTL_RCC2_SYSDIV2_64 0x1F800000 // System clock /64\r
+#define SYSCTL_RCC2_PWRDN2 0x00002000 // PLL power down\r
+#define SYSCTL_RCC2_BYPASS2 0x00000800 // PLL bypass\r
+#define SYSCTL_RCC2_OSCSRC2_MSK 0x00000070 // Oscillator input select\r
+#define SYSCTL_RCC2_OSCSRC2_MO 0x00000000 // Use the main oscillator\r
+#define SYSCTL_RCC2_OSCSRC2_IO 0x00000010 // Use the internal oscillator\r
+#define SYSCTL_RCC2_OSCSRC2_IO4 0x00000020 // Use the internal oscillator / 4\r
+#define SYSCTL_RCC2_OSCSRC2_30 0x00000030 // Use the 30 KHz internal osc.\r
+#define SYSCTL_RCC2_OSCSRC2_32 0x00000070 // Use the 32 KHz external osc.\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_DSLPCLKCFG register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_DSLPCLKCFG_D_MSK 0x1f800000 // Deep sleep system clock override\r
+#define SYSCTL_DSLPCLKCFG_D_2 0x00800000 // System clock /2\r
+#define SYSCTL_DSLPCLKCFG_D_3 0x01000000 // System clock /3\r
+#define SYSCTL_DSLPCLKCFG_D_4 0x01800000 // System clock /4\r
+#define SYSCTL_DSLPCLKCFG_D_5 0x02000000 // System clock /5\r
+#define SYSCTL_DSLPCLKCFG_D_6 0x02800000 // System clock /6\r
+#define SYSCTL_DSLPCLKCFG_D_7 0x03000000 // System clock /7\r
+#define SYSCTL_DSLPCLKCFG_D_8 0x03800000 // System clock /8\r
+#define SYSCTL_DSLPCLKCFG_D_9 0x04000000 // System clock /9\r
+#define SYSCTL_DSLPCLKCFG_D_10 0x04800000 // System clock /10\r
+#define SYSCTL_DSLPCLKCFG_D_11 0x05000000 // System clock /11\r
+#define SYSCTL_DSLPCLKCFG_D_12 0x05800000 // System clock /12\r
+#define SYSCTL_DSLPCLKCFG_D_13 0x06000000 // System clock /13\r
+#define SYSCTL_DSLPCLKCFG_D_14 0x06800000 // System clock /14\r
+#define SYSCTL_DSLPCLKCFG_D_15 0x07000000 // System clock /15\r
+#define SYSCTL_DSLPCLKCFG_D_16 0x07800000 // System clock /16\r
+#define SYSCTL_DSLPCLKCFG_D_17 0x08000000 // System clock /17\r
+#define SYSCTL_DSLPCLKCFG_D_18 0x08800000 // System clock /18\r
+#define SYSCTL_DSLPCLKCFG_D_19 0x09000000 // System clock /19\r
+#define SYSCTL_DSLPCLKCFG_D_20 0x09800000 // System clock /20\r
+#define SYSCTL_DSLPCLKCFG_D_21 0x0A000000 // System clock /21\r
+#define SYSCTL_DSLPCLKCFG_D_22 0x0A800000 // System clock /22\r
+#define SYSCTL_DSLPCLKCFG_D_23 0x0B000000 // System clock /23\r
+#define SYSCTL_DSLPCLKCFG_D_24 0x0B800000 // System clock /24\r
+#define SYSCTL_DSLPCLKCFG_D_25 0x0C000000 // System clock /25\r
+#define SYSCTL_DSLPCLKCFG_D_26 0x0C800000 // System clock /26\r
+#define SYSCTL_DSLPCLKCFG_D_27 0x0D000000 // System clock /27\r
+#define SYSCTL_DSLPCLKCFG_D_28 0x0D800000 // System clock /28\r
+#define SYSCTL_DSLPCLKCFG_D_29 0x0E000000 // System clock /29\r
+#define SYSCTL_DSLPCLKCFG_D_30 0x0E800000 // System clock /30\r
+#define SYSCTL_DSLPCLKCFG_D_31 0x0F000000 // System clock /31\r
+#define SYSCTL_DSLPCLKCFG_D_32 0x0F800000 // System clock /32\r
+#define SYSCTL_DSLPCLKCFG_D_33 0x10000000 // System clock /33\r
+#define SYSCTL_DSLPCLKCFG_D_34 0x10800000 // System clock /34\r
+#define SYSCTL_DSLPCLKCFG_D_35 0x11000000 // System clock /35\r
+#define SYSCTL_DSLPCLKCFG_D_36 0x11800000 // System clock /36\r
+#define SYSCTL_DSLPCLKCFG_D_37 0x12000000 // System clock /37\r
+#define SYSCTL_DSLPCLKCFG_D_38 0x12800000 // System clock /38\r
+#define SYSCTL_DSLPCLKCFG_D_39 0x13000000 // System clock /39\r
+#define SYSCTL_DSLPCLKCFG_D_40 0x13800000 // System clock /40\r
+#define SYSCTL_DSLPCLKCFG_D_41 0x14000000 // System clock /41\r
+#define SYSCTL_DSLPCLKCFG_D_42 0x14800000 // System clock /42\r
+#define SYSCTL_DSLPCLKCFG_D_43 0x15000000 // System clock /43\r
+#define SYSCTL_DSLPCLKCFG_D_44 0x15800000 // System clock /44\r
+#define SYSCTL_DSLPCLKCFG_D_45 0x16000000 // System clock /45\r
+#define SYSCTL_DSLPCLKCFG_D_46 0x16800000 // System clock /46\r
+#define SYSCTL_DSLPCLKCFG_D_47 0x17000000 // System clock /47\r
+#define SYSCTL_DSLPCLKCFG_D_48 0x17800000 // System clock /48\r
+#define SYSCTL_DSLPCLKCFG_D_49 0x18000000 // System clock /49\r
+#define SYSCTL_DSLPCLKCFG_D_50 0x18800000 // System clock /50\r
+#define SYSCTL_DSLPCLKCFG_D_51 0x19000000 // System clock /51\r
+#define SYSCTL_DSLPCLKCFG_D_52 0x19800000 // System clock /52\r
+#define SYSCTL_DSLPCLKCFG_D_53 0x1A000000 // System clock /53\r
+#define SYSCTL_DSLPCLKCFG_D_54 0x1A800000 // System clock /54\r
+#define SYSCTL_DSLPCLKCFG_D_55 0x1B000000 // System clock /55\r
+#define SYSCTL_DSLPCLKCFG_D_56 0x1B800000 // System clock /56\r
+#define SYSCTL_DSLPCLKCFG_D_57 0x1C000000 // System clock /57\r
+#define SYSCTL_DSLPCLKCFG_D_58 0x1C800000 // System clock /58\r
+#define SYSCTL_DSLPCLKCFG_D_59 0x1D000000 // System clock /59\r
+#define SYSCTL_DSLPCLKCFG_D_60 0x1D800000 // System clock /60\r
+#define SYSCTL_DSLPCLKCFG_D_61 0x1E000000 // System clock /61\r
+#define SYSCTL_DSLPCLKCFG_D_62 0x1E800000 // System clock /62\r
+#define SYSCTL_DSLPCLKCFG_D_63 0x1F000000 // System clock /63\r
+#define SYSCTL_DSLPCLKCFG_D_64 0x1F800000 // System clock /64\r
+#define SYSCTL_DSLPCLKCFG_O_MSK 0x00000070 // Deep sleep oscillator override\r
+#define SYSCTL_DSLPCLKCFG_O_IGN 0x00000000 // Do not override\r
+#define SYSCTL_DSLPCLKCFG_O_IO 0x00000010 // Use the internal oscillator\r
+#define SYSCTL_DSLPCLKCFG_O_30 0x00000030 // Use the 30 KHz internal osc.\r
+#define SYSCTL_DSLPCLKCFG_O_32 0x00000070 // Use the 32 KHz external osc.\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_CLKVCLR register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_CLKVCLR_CLR 0x00000001 // Clear clock verification fault\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_LDOARST register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_LDOARST_ARST 0x00000001 // Allow LDO to reset device\r
+\r
+#endif // __HW_SYSCTL_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_timer.h - Defines and macros used when accessing the timer.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_TIMER_H__\r
+#define __HW_TIMER_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the offsets of the timer registers.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_O_CFG 0x00000000 // Configuration register\r
+#define TIMER_O_TAMR 0x00000004 // TimerA mode register\r
+#define TIMER_O_TBMR 0x00000008 // TimerB mode register\r
+#define TIMER_O_CTL 0x0000000C // Control register\r
+#define TIMER_O_IMR 0x00000018 // Interrupt mask register\r
+#define TIMER_O_RIS 0x0000001C // Interrupt status register\r
+#define TIMER_O_MIS 0x00000020 // Masked interrupt status reg.\r
+#define TIMER_O_ICR 0x00000024 // Interrupt clear register\r
+#define TIMER_O_TAILR 0x00000028 // TimerA interval load register\r
+#define TIMER_O_TBILR 0x0000002C // TimerB interval load register\r
+#define TIMER_O_TAMATCHR 0x00000030 // TimerA match register\r
+#define TIMER_O_TBMATCHR 0x00000034 // TimerB match register\r
+#define TIMER_O_TAPR 0x00000038 // TimerA prescale register\r
+#define TIMER_O_TBPR 0x0000003C // TimerB prescale register\r
+#define TIMER_O_TAPMR 0x00000040 // TimerA prescale match register\r
+#define TIMER_O_TBPMR 0x00000044 // TimerB prescale match register\r
+#define TIMER_O_TAR 0x00000048 // TimerA register\r
+#define TIMER_O_TBR 0x0000004C // TimerB register\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the reset values of the timer registers.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_RV_CFG 0x00000000 // Configuration register RV\r
+#define TIMER_RV_TAMR 0x00000000 // TimerA mode register RV\r
+#define TIMER_RV_TBMR 0x00000000 // TimerB mode register RV\r
+#define TIMER_RV_CTL 0x00000000 // Control register RV\r
+#define TIMER_RV_IMR 0x00000000 // Interrupt mask register RV\r
+#define TIMER_RV_RIS 0x00000000 // Interrupt status register RV\r
+#define TIMER_RV_MIS 0x00000000 // Masked interrupt status reg RV\r
+#define TIMER_RV_ICR 0x00000000 // Interrupt clear register RV\r
+#define TIMER_RV_TAILR 0xFFFFFFFF // TimerA interval load reg RV\r
+#define TIMER_RV_TBILR 0x0000FFFF // TimerB interval load reg RV\r
+#define TIMER_RV_TAMATCHR 0xFFFFFFFF // TimerA match register RV\r
+#define TIMER_RV_TBMATCHR 0x0000FFFF // TimerB match register RV\r
+#define TIMER_RV_TAPR 0x00000000 // TimerA prescale register RV\r
+#define TIMER_RV_TBPR 0x00000000 // TimerB prescale register RV\r
+#define TIMER_RV_TAPMR 0x00000000 // TimerA prescale match reg RV\r
+#define TIMER_RV_TBPMR 0x00000000 // TimerB prescale match regi RV\r
+#define TIMER_RV_TAR 0xFFFFFFFF // TimerA register RV\r
+#define TIMER_RV_TBR 0x0000FFFF // TimerB register RV\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the TIMER_CFG register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_CFG_CFG_MSK 0x00000007 // Configuration options mask\r
+#define TIMER_CFG_16_BIT 0x00000004 // Two 16 bit timers\r
+#define TIMER_CFG_32_BIT_RTC 0x00000001 // 32 bit RTC\r
+#define TIMER_CFG_32_BIT_TIMER 0x00000000 // 32 bit timer\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the TIMER_TnMR register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_TNMR_TNAMS 0x00000008 // Alternate mode select\r
+#define TIMER_TNMR_TNCMR 0x00000004 // Capture mode - count or time\r
+#define TIMER_TNMR_TNTMR_MSK 0x00000003 // Timer mode mask\r
+#define TIMER_TNMR_TNTMR_CAP 0x00000003 // Mode - capture\r
+#define TIMER_TNMR_TNTMR_PERIOD 0x00000002 // Mode - periodic\r
+#define TIMER_TNMR_TNTMR_1_SHOT 0x00000001 // Mode - one shot\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the TIMER_CTL register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_CTL_TBPWML 0x00004000 // TimerB PWM output level invert\r
+#define TIMER_CTL_TBOTE 0x00002000 // TimerB output trigger enable\r
+#define TIMER_CTL_TBEVENT_MSK 0x00000C00 // TimerB event mode mask\r
+#define TIMER_CTL_TBEVENT_BOTH 0x00000C00 // TimerB event mode - both edges\r
+#define TIMER_CTL_TBEVENT_NEG 0x00000400 // TimerB event mode - neg edge\r
+#define TIMER_CTL_TBEVENT_POS 0x00000000 // TimerB event mode - pos edge\r
+#define TIMER_CTL_TBSTALL 0x00000200 // TimerB stall enable\r
+#define TIMER_CTL_TBEN 0x00000100 // TimerB enable\r
+#define TIMER_CTL_TAPWML 0x00000040 // TimerA PWM output level invert\r
+#define TIMER_CTL_TAOTE 0x00000020 // TimerA output trigger enable\r
+#define TIMER_CTL_RTCEN 0x00000010 // RTC counter enable\r
+#define TIMER_CTL_TAEVENT_MSK 0x0000000C // TimerA event mode mask\r
+#define TIMER_CTL_TAEVENT_BOTH 0x0000000C // TimerA event mode - both edges\r
+#define TIMER_CTL_TAEVENT_NEG 0x00000004 // TimerA event mode - neg edge\r
+#define TIMER_CTL_TAEVENT_POS 0x00000000 // TimerA event mode - pos edge\r
+#define TIMER_CTL_TASTALL 0x00000002 // TimerA stall enable\r
+#define TIMER_CTL_TAEN 0x00000001 // TimerA enable\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the TIMER_IMR register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_IMR_CBEIM 0x00000400 // CaptureB event interrupt mask\r
+#define TIMER_IMR_CBMIM 0x00000200 // CaptureB match interrupt mask\r
+#define TIMER_IMR_TBTOIM 0x00000100 // TimerB time out interrupt mask\r
+#define TIMER_IMR_RTCIM 0x00000008 // RTC interrupt mask\r
+#define TIMER_IMR_CAEIM 0x00000004 // CaptureA event interrupt mask\r
+#define TIMER_IMR_CAMIM 0x00000002 // CaptureA match interrupt mask\r
+#define TIMER_IMR_TATOIM 0x00000001 // TimerA time out interrupt mask\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the TIMER_RIS register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_RIS_CBERIS 0x00000400 // CaptureB event raw int status\r
+#define TIMER_RIS_CBMRIS 0x00000200 // CaptureB match raw int status\r
+#define TIMER_RIS_TBTORIS 0x00000100 // TimerB time out raw int status\r
+#define TIMER_RIS_RTCRIS 0x00000008 // RTC raw int status\r
+#define TIMER_RIS_CAERIS 0x00000004 // CaptureA event raw int status\r
+#define TIMER_RIS_CAMRIS 0x00000002 // CaptureA match raw int status\r
+#define TIMER_RIS_TATORIS 0x00000001 // TimerA time out raw int status\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the TIMER_MIS register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_RIS_CBEMIS 0x00000400 // CaptureB event masked int status\r
+#define TIMER_RIS_CBMMIS 0x00000200 // CaptureB match masked int status\r
+#define TIMER_RIS_TBTOMIS 0x00000100 // TimerB time out masked int stat\r
+#define TIMER_RIS_RTCMIS 0x00000008 // RTC masked int status\r
+#define TIMER_RIS_CAEMIS 0x00000004 // CaptureA event masked int status\r
+#define TIMER_RIS_CAMMIS 0x00000002 // CaptureA match masked int status\r
+#define TIMER_RIS_TATOMIS 0x00000001 // TimerA time out masked int stat\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the TIMER_ICR register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_ICR_CBECINT 0x00000400 // CaptureB event interrupt clear\r
+#define TIMER_ICR_CBMCINT 0x00000200 // CaptureB match interrupt clear\r
+#define TIMER_ICR_TBTOCINT 0x00000100 // TimerB time out interrupt clear\r
+#define TIMER_ICR_RTCCINT 0x00000008 // RTC interrupt clear\r
+#define TIMER_ICR_CAECINT 0x00000004 // CaptureA event interrupt clear\r
+#define TIMER_ICR_CAMCINT 0x00000002 // CaptureA match interrupt clear\r
+#define TIMER_ICR_TATOCINT 0x00000001 // TimerA time out interrupt clear\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the TIMER_TAILR register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_TAILR_TAILRH 0xFFFF0000 // TimerB load val in 32 bit mode\r
+#define TIMER_TAILR_TAILRL 0x0000FFFF // TimerA interval load value\r
+\r
+//*****************************************************************************\r
+//\r
+// The following defines the bit fields in the TIMER_TBILR register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_TBILR_TBILRL 0x0000FFFF // TimerB interval load value\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the TIMER_TAMATCHR register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_TAMATCHR_TAMRH 0xFFFF0000 // TimerB match val in 32 bit mode\r
+#define TIMER_TAMATCHR_TAMRL 0x0000FFFF // TimerA match value\r
+\r
+//*****************************************************************************\r
+//\r
+// The following defines the bit fields in the TIMER_TBMATCHR register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_TBMATCHR_TBMRL 0x0000FFFF // TimerB match load value\r
+\r
+//*****************************************************************************\r
+//\r
+// The following defines the bit fields in the TIMER_TnPR register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_TNPR_TNPSR 0x000000FF // TimerN prescale value\r
+\r
+//*****************************************************************************\r
+//\r
+// The following defines the bit fields in the TIMER_TnPMR register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_TNPMR_TNPSMR 0x000000FF // TimerN prescale match value\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the TIMER_TAR register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_TAR_TARH 0xFFFF0000 // TimerB val in 32 bit mode\r
+#define TIMER_TAR_TARL 0x0000FFFF // TimerA value\r
+\r
+//*****************************************************************************\r
+//\r
+// The following defines the bit fields in the TIMER_TBR register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_TBR_TBRL 0x0000FFFF // TimerB value\r
+\r
+#endif // __HW_TIMER_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_types.h - Common types and macros.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_TYPES_H__\r
+#define __HW_TYPES_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// Define a boolean type, and values for true and false.\r
+//\r
+//*****************************************************************************\r
+typedef unsigned char tBoolean;\r
+\r
+#ifndef true\r
+#define true 1\r
+#endif\r
+\r
+#ifndef false\r
+#define false 0\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Macros for hardware access, both direct and via the bit-band region.\r
+//\r
+//*****************************************************************************\r
+#define HWREG(x) \\r
+ (*((volatile unsigned long *)(x)))\r
+#define HWREGH(x) \\r
+ (*((volatile unsigned short *)(x)))\r
+#define HWREGB(x) \\r
+ (*((volatile unsigned char *)(x)))\r
+#define HWREGBITW(x, b) \\r
+ HWREG(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \\r
+ (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2))\r
+#define HWREGBITH(x, b) \\r
+ HWREGH(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \\r
+ (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2))\r
+#define HWREGBITB(x, b) \\r
+ HWREGB(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \\r
+ (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2))\r
+\r
+//*****************************************************************************\r
+//\r
+// Helper Macros for determining silicon revisions, etc.\r
+//\r
+// These macros will be used by Driverlib at "run-time" to create necessary\r
+// conditional code blocks that will allow a single version of the Driverlib\r
+// "binary" code to support multiple(all) Stellaris silicon revisions.\r
+//\r
+// It is expected that these macros will be used inside of a standard 'C' \r
+// conditional block of code, e.g.\r
+//\r
+// if(DEVICE_IS_SANDSTORM())\r
+// {\r
+// do some Sandstorm specific code here.\r
+// }\r
+//\r
+// By default, these macros will be defined as run-time checks of the\r
+// appropriate register(s) to allow creation of run-time conditional code\r
+// blocks for a common DriverLib across the entire Stellaris family.\r
+//\r
+// However, if code-space optimization is required, these macros can be "hard-\r
+// coded" for a specific version of Stellaris silicon. Many compilers will\r
+// then detect the "hard-coded" conditionals, and appropriately optimize the\r
+// code blocks, eliminating any "unreachable" code. This would result in \r
+// a smaller Driverlib, thus producing a smaller final application size, but\r
+// at the cost of limiting the Driverlib binary to a specific Stellaris\r
+// silicon revision.\r
+//\r
+//*****************************************************************************\r
+#ifndef DEVICE_IS_SANDSTORM\r
+#define DEVICE_IS_SANDSTORM \\r
+ (((HWREG(SYSCTL_DID0) & SYSCTL_DID0_VER_MASK) == SYSCTL_DID0_VER_0) || \\r
+ (((HWREG(SYSCTL_DID0) & SYSCTL_DID0_VER_MASK) == SYSCTL_DID0_VER_1) && \\r
+ ((HWREG(SYSCTL_DID0) & SYSCTL_DID0_CLASS_MASK) == \\r
+ SYSCTL_DID0_CLASS_SANDSTORM)))\r
+#endif\r
+\r
+#ifndef DEVICE_IS_FURY\r
+#define DEVICE_IS_FURY \\r
+ (((HWREG(SYSCTL_DID0) & SYSCTL_DID0_VER_MASK) == SYSCTL_DID0_VER_1) && \\r
+ ((HWREG(SYSCTL_DID0) & SYSCTL_DID0_CLASS_MASK) == \\r
+ SYSCTL_DID0_CLASS_FURY))\r
+#endif\r
+\r
+#ifndef DEVICE_IS_REVA2\r
+#define DEVICE_IS_REVA2 \\r
+ (((HWREG(SYSCTL_DID0) & SYSCTL_DID0_MAJ_MASK) == SYSCTL_DID0_MAJ_A) && \\r
+ ((HWREG(SYSCTL_DID0) & SYSCTL_DID0_MIN_MASK) == SYSCTL_DID0_MIN_2))\r
+#endif\r
+\r
+#ifndef DEVICE_IS_REVC1\r
+#define DEVICE_IS_REVC1 \\r
+ (((HWREG(SYSCTL_DID0) & SYSCTL_DID0_MAJ_MASK) == SYSCTL_DID0_MAJ_C) && \\r
+ ((HWREG(SYSCTL_DID0) & SYSCTL_DID0_MIN_MASK) == SYSCTL_DID0_MIN_1))\r
+#endif\r
+\r
+#ifndef DEVICE_IS_REVC2\r
+#define DEVICE_IS_REVC2 \\r
+ (((HWREG(SYSCTL_DID0) & SYSCTL_DID0_MAJ_MASK) == SYSCTL_DID0_MAJ_C) && \\r
+ ((HWREG(SYSCTL_DID0) & SYSCTL_DID0_MIN_MASK) == SYSCTL_DID0_MIN_2))\r
+#endif\r
+\r
+#endif // __HW_TYPES_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_uart.h - Macros and defines used when accessing the UART hardware\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_UART_H__\r
+#define __HW_UART_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// UART Register Offsets.\r
+//\r
+//*****************************************************************************\r
+#define UART_O_DR 0x00000000 // Data Register\r
+#define UART_O_RSR 0x00000004 // Receive Status Register (read)\r
+#define UART_O_ECR 0x00000004 // Error Clear Register (write)\r
+#define UART_O_FR 0x00000018 // Flag Register (read only)\r
+#define UART_O_IBRD 0x00000024 // Integer Baud Rate Divisor Reg\r
+#define UART_O_FBRD 0x00000028 // Fractional Baud Rate Divisor Reg\r
+#define UART_O_LCR_H 0x0000002C // Line Control Register, HIGH byte\r
+#define UART_O_CTL 0x00000030 // Control Register\r
+#define UART_O_IFLS 0x00000034 // Interrupt FIFO Level Select Reg\r
+#define UART_O_IM 0x00000038 // Interrupt Mask Set/Clear Reg\r
+#define UART_O_RIS 0x0000003C // Raw Interrupt Status Register\r
+#define UART_O_MIS 0x00000040 // Masked Interrupt Status Register\r
+#define UART_O_ICR 0x00000044 // Interrupt Clear Register\r
+#define UART_O_PeriphID4 0x00000FD0 //\r
+#define UART_O_PeriphID5 0x00000FD4 //\r
+#define UART_O_PeriphID6 0x00000FD8 //\r
+#define UART_O_PeriphID7 0x00000FDC //\r
+#define UART_O_PeriphID0 0x00000FE0 //\r
+#define UART_O_PeriphID1 0x00000FE4 //\r
+#define UART_O_PeriphID2 0x00000FE8 //\r
+#define UART_O_PeriphID3 0x00000FEC //\r
+#define UART_O_PCellID0 0x00000FF0 //\r
+#define UART_O_PCellID1 0x00000FF4 //\r
+#define UART_O_PCellID2 0x00000FF8 //\r
+#define UART_O_PCellID3 0x00000FFC //\r
+\r
+//*****************************************************************************\r
+//\r
+// Data Register bits\r
+//\r
+//*****************************************************************************\r
+#define UART_DR_OE 0x00000800 // Overrun Error\r
+#define UART_DR_BE 0x00000400 // Break Error\r
+#define UART_DR_PE 0x00000200 // Parity Error\r
+#define UART_DR_FE 0x00000100 // Framing Error\r
+#define UART_DR_DATA_MASK 0x000000FF // UART data\r
+\r
+//*****************************************************************************\r
+//\r
+// Receive Status Register bits\r
+//\r
+//*****************************************************************************\r
+#define UART_RSR_OE 0x00000008 // Overrun Error\r
+#define UART_RSR_BE 0x00000004 // Break Error\r
+#define UART_RSR_PE 0x00000002 // Parity Error\r
+#define UART_RSR_FE 0x00000001 // Framing Error\r
+\r
+//*****************************************************************************\r
+//\r
+// Flag Register bits\r
+//\r
+//*****************************************************************************\r
+#define UART_FR_TXFE 0x00000080 // TX FIFO Empty\r
+#define UART_FR_RXFF 0x00000040 // RX FIFO Full\r
+#define UART_FR_TXFF 0x00000020 // TX FIFO Full\r
+#define UART_FR_RXFE 0x00000010 // RX FIFO Empty\r
+#define UART_FR_BUSY 0x00000008 // UART Busy\r
+\r
+//*****************************************************************************\r
+//\r
+// Integer baud-rate divisor\r
+//\r
+//*****************************************************************************\r
+#define UART_IBRD_DIVINT_MASK 0x0000FFFF // Integer baud-rate divisor\r
+\r
+//*****************************************************************************\r
+//\r
+// Fractional baud-rate divisor\r
+//\r
+//*****************************************************************************\r
+#define UART_FBRD_DIVFRAC_MASK 0x0000003F // Fractional baud-rate divisor\r
+\r
+//*****************************************************************************\r
+//\r
+// Line Control Register High bits\r
+//\r
+//*****************************************************************************\r
+#define UART_LCR_H_SPS 0x00000080 // Stick Parity Select\r
+#define UART_LCR_H_WLEN 0x00000060 // Word length\r
+#define UART_LCR_H_WLEN_8 0x00000060 // 8 bit data\r
+#define UART_LCR_H_WLEN_7 0x00000040 // 7 bit data\r
+#define UART_LCR_H_WLEN_6 0x00000020 // 6 bit data\r
+#define UART_LCR_H_WLEN_5 0x00000000 // 5 bit data\r
+#define UART_LCR_H_FEN 0x00000010 // Enable FIFO\r
+#define UART_LCR_H_STP2 0x00000008 // Two Stop Bits Select\r
+#define UART_LCR_H_EPS 0x00000004 // Even Parity Select\r
+#define UART_LCR_H_PEN 0x00000002 // Parity Enable\r
+#define UART_LCR_H_BRK 0x00000001 // Send Break\r
+\r
+//*****************************************************************************\r
+//\r
+// Control Register bits\r
+//\r
+//*****************************************************************************\r
+#define UART_CTL_RXE 0x00000200 // Receive Enable\r
+#define UART_CTL_TXE 0x00000100 // Transmit Enable\r
+#define UART_CTL_LBE 0x00000080 // Loopback Enable\r
+#define UART_CTL_SIRLP 0x00000004 // SIR (IrDA) Low Power Enable\r
+#define UART_CTL_SIREN 0x00000002 // SIR (IrDA) Enable\r
+#define UART_CTL_UARTEN 0x00000001 // UART Enable\r
+\r
+//*****************************************************************************\r
+//\r
+// Interrupt FIFO Level Select Register bits\r
+//\r
+//*****************************************************************************\r
+#define UART_IFLS_RX1_8 0x00000000 // 1/8 Full\r
+#define UART_IFLS_RX2_8 0x00000010 // 1/4 Full\r
+#define UART_IFLS_RX4_8 0x00000020 // 1/2 Full\r
+#define UART_IFLS_RX6_8 0x00000030 // 3/4 Full\r
+#define UART_IFLS_RX7_8 0x00000040 // 7/8 Full\r
+#define UART_IFLS_TX1_8 0x00000000 // 1/8 Full\r
+#define UART_IFLS_TX2_8 0x00000001 // 1/4 Full\r
+#define UART_IFLS_TX4_8 0x00000002 // 1/2 Full\r
+#define UART_IFLS_TX6_8 0x00000003 // 3/4 Full\r
+#define UART_IFLS_TX7_8 0x00000004 // 7/8 Full\r
+\r
+//*****************************************************************************\r
+//\r
+// Interrupt Mask Set/Clear Register bits\r
+//\r
+//*****************************************************************************\r
+#define UART_IM_OEIM 0x00000400 // Overrun Error Interrupt Mask\r
+#define UART_IM_BEIM 0x00000200 // Break Error Interrupt Mask\r
+#define UART_IM_PEIM 0x00000100 // Parity Error Interrupt Mask\r
+#define UART_IM_FEIM 0x00000080 // Framing Error Interrupt Mask\r
+#define UART_IM_RTIM 0x00000040 // Receive Timeout Interrupt Mask\r
+#define UART_IM_TXIM 0x00000020 // Transmit Interrupt Mask\r
+#define UART_IM_RXIM 0x00000010 // Receive Interrupt Mask\r
+\r
+//*****************************************************************************\r
+//\r
+// Raw Interrupt Status Register\r
+//\r
+//*****************************************************************************\r
+#define UART_RIS_OERIS 0x00000400 // Overrun Error Interrupt Status\r
+#define UART_RIS_BERIS 0x00000200 // Break Error Interrupt Status\r
+#define UART_RIS_PERIS 0x00000100 // Parity Error Interrupt Status\r
+#define UART_RIS_FERIS 0x00000080 // Framing Error Interrupt Status\r
+#define UART_RIS_RTRIS 0x00000040 // Receive Timeout Interrupt Status\r
+#define UART_RIS_TXRIS 0x00000020 // Transmit Interrupt Status\r
+#define UART_RIS_RXRIS 0x00000010 // Receive Interrupt Status\r
+\r
+//*****************************************************************************\r
+//\r
+// Masked Interrupt Status Register\r
+//\r
+//*****************************************************************************\r
+#define UART_MIS_OEMIS 0x00000400 // Overrun Error Interrupt Status\r
+#define UART_MIS_BEMIS 0x00000200 // Break Error Interrupt Status\r
+#define UART_MIS_PEMIS 0x00000100 // Parity Error Interrupt Status\r
+#define UART_MIS_FEMIS 0x00000080 // Framing Error Interrupt Status\r
+#define UART_MIS_RTMIS 0x00000040 // Receive Timeout Interrupt Status\r
+#define UART_MIS_TXMIS 0x00000020 // Transmit Interrupt Status\r
+#define UART_MIS_RXMIS 0x00000010 // Receive Interrupt Status\r
+\r
+//*****************************************************************************\r
+//\r
+// Interrupt Clear Register bits\r
+//\r
+//*****************************************************************************\r
+#define UART_ICR_OEIC 0x00000400 // Overrun Error Interrupt Clear\r
+#define UART_ICR_BEIC 0x00000200 // Break Error Interrupt Clear\r
+#define UART_ICR_PEIC 0x00000100 // Parity Error Interrupt Clear\r
+#define UART_ICR_FEIC 0x00000080 // Framing Error Interrupt Clear\r
+#define UART_ICR_RTIC 0x00000040 // Receive Timeout Interrupt Clear\r
+#define UART_ICR_TXIC 0x00000020 // Transmit Interrupt Clear\r
+#define UART_ICR_RXIC 0x00000010 // Receive Interrupt Clear\r
+\r
+#define UART_RSR_ANY (UART_RSR_OE | \\r
+ UART_RSR_BE | \\r
+ UART_RSR_PE | \\r
+ UART_RSR_FE)\r
+\r
+//*****************************************************************************\r
+//\r
+// Reset Values for UART Registers.\r
+//\r
+//*****************************************************************************\r
+#define UART_RV_DR 0x00000000\r
+#define UART_RV_RSR 0x00000000\r
+#define UART_RV_ECR 0x00000000\r
+#define UART_RV_FR 0x00000090\r
+#define UART_RV_IBRD 0x00000000\r
+#define UART_RV_FBRD 0x00000000\r
+#define UART_RV_LCR_H 0x00000000\r
+#define UART_RV_CTL 0x00000300\r
+#define UART_RV_IFLS 0x00000012\r
+#define UART_RV_IM 0x00000000\r
+#define UART_RV_RIS 0x00000000\r
+#define UART_RV_MIS 0x00000000\r
+#define UART_RV_ICR 0x00000000\r
+#define UART_RV_PeriphID4 0x00000000\r
+#define UART_RV_PeriphID5 0x00000000\r
+#define UART_RV_PeriphID6 0x00000000\r
+#define UART_RV_PeriphID7 0x00000000\r
+#define UART_RV_PeriphID0 0x00000011\r
+#define UART_RV_PeriphID1 0x00000000\r
+#define UART_RV_PeriphID2 0x00000018\r
+#define UART_RV_PeriphID3 0x00000001\r
+#define UART_RV_PCellID0 0x0000000D\r
+#define UART_RV_PCellID1 0x000000F0\r
+#define UART_RV_PCellID2 0x00000005\r
+#define UART_RV_PCellID3 0x000000B1\r
+\r
+#endif // __HW_UART_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_watchdog.h - Macros used when accessing the Watchdog Timer hardware.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_WATCHDOG_H__\r
+#define __HW_WATCHDOG_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the offsets of the Watchdog Timer registers.\r
+//\r
+//*****************************************************************************\r
+#define WDT_O_LOAD 0x00000000 // Load register\r
+#define WDT_O_VALUE 0x00000004 // Current value register\r
+#define WDT_O_CTL 0x00000008 // Control register\r
+#define WDT_O_ICR 0x0000000C // Interrupt clear register\r
+#define WDT_O_RIS 0x00000010 // Raw interrupt status register\r
+#define WDT_O_MIS 0x00000014 // Masked interrupt status register\r
+#define WDT_O_TEST 0x00000418 // Test register\r
+#define WDT_O_LOCK 0x00000C00 // Lock register\r
+#define WDT_O_PeriphID4 0x00000FD0 //\r
+#define WDT_O_PeriphID5 0x00000FD4 //\r
+#define WDT_O_PeriphID6 0x00000FD8 //\r
+#define WDT_O_PeriphID7 0x00000FDC //\r
+#define WDT_O_PeriphID0 0x00000FE0 //\r
+#define WDT_O_PeriphID1 0x00000FE4 //\r
+#define WDT_O_PeriphID2 0x00000FE8 //\r
+#define WDT_O_PeriphID3 0x00000FEC //\r
+#define WDT_O_PCellID0 0x00000FF0 //\r
+#define WDT_O_PCellID1 0x00000FF4 //\r
+#define WDT_O_PCellID2 0x00000FF8 //\r
+#define WDT_O_PCellID3 0x00000FFC //\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the WDT_CTL register.\r
+//\r
+//*****************************************************************************\r
+#define WDT_CTL_RESEN 0x00000002 // Enable reset output\r
+#define WDT_CTL_INTEN 0x00000001 // Enable the WDT counter and int\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the WDT_ISR, WDT_RIS, and WDT_MIS\r
+// registers.\r
+//\r
+//*****************************************************************************\r
+#define WDT_INT_TIMEOUT 0x00000001 // Watchdog timer expired\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the WDT_TEST register.\r
+//\r
+//*****************************************************************************\r
+#define WDT_TEST_STALL 0x00000100 // Watchdog stall enable\r
+#ifndef DEPRECATED\r
+#define WDT_TEST_STALL_EN 0x00000100 // Watchdog stall enable\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the WDT_LOCK register.\r
+//\r
+//*****************************************************************************\r
+#define WDT_LOCK_LOCKED 0x00000001 // Watchdog timer is locked\r
+#define WDT_LOCK_UNLOCKED 0x00000000 // Watchdog timer is unlocked\r
+#define WDT_LOCK_UNLOCK 0x1ACCE551 // Unlocks the watchdog timer\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the reset values for the WDT registers.\r
+//\r
+//*****************************************************************************\r
+#define WDT_RV_LOAD 0xFFFFFFFF // Load register\r
+#define WDT_RV_VALUE 0xFFFFFFFF // Current value register\r
+#define WDT_RV_CTL 0x00000000 // Control register\r
+#define WDT_RV_RIS 0x00000000 // Raw interrupt status register\r
+#define WDT_RV_MIS 0x00000000 // Masked interrupt status register\r
+#define WDT_RV_LOCK 0x00000000 // Lock register\r
+#define WDT_RV_PeriphID4 0x00000000 //\r
+#define WDT_RV_PeriphID5 0x00000000 //\r
+#define WDT_RV_PeriphID6 0x00000000 //\r
+#define WDT_RV_PeriphID7 0x00000000 //\r
+#define WDT_RV_PeriphID0 0x00000005 //\r
+#define WDT_RV_PeriphID1 0x00000018 //\r
+#define WDT_RV_PeriphID2 0x00000018 //\r
+#define WDT_RV_PeriphID3 0x00000001 //\r
+#define WDT_RV_PCellID0 0x0000000D //\r
+#define WDT_RV_PCellID1 0x000000F0 //\r
+#define WDT_RV_PCellID2 0x00000005 //\r
+#define WDT_RV_PCellID3 0x000000B1 //\r
+\r
+#endif // __HW_WATCHDOG_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// i2c.h - Prototypes for the I2C Driver.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __I2C_H__\r
+#define __I2C_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Defines for the API.\r
+//\r
+//*****************************************************************************\r
+//*****************************************************************************\r
+//\r
+// Interrupt defines.\r
+//\r
+//*****************************************************************************\r
+#define I2C_INT_MASTER 0x00000001\r
+#define I2C_INT_SLAVE 0x00000002\r
+\r
+//*****************************************************************************\r
+//\r
+// I2C Master commands.\r
+//\r
+//*****************************************************************************\r
+#define I2C_MASTER_CMD_SINGLE_SEND \\r
+ (I2C_MASTER_CS_STOP | I2C_MASTER_CS_START | I2C_MASTER_CS_RUN)\r
+#define I2C_MASTER_CMD_SINGLE_RECEIVE \\r
+ (I2C_MASTER_CS_STOP | I2C_MASTER_CS_START | I2C_MASTER_CS_RUN)\r
+#define I2C_MASTER_CMD_BURST_SEND_START \\r
+ (I2C_MASTER_CS_START | I2C_MASTER_CS_RUN)\r
+#define I2C_MASTER_CMD_BURST_SEND_CONT \\r
+ (I2C_MASTER_CS_RUN)\r
+#define I2C_MASTER_CMD_BURST_SEND_FINISH \\r
+ (I2C_MASTER_CS_STOP | I2C_MASTER_CS_RUN)\r
+#define I2C_MASTER_CMD_BURST_SEND_ERROR_STOP \\r
+ (I2C_MASTER_CS_STOP)\r
+#define I2C_MASTER_CMD_BURST_RECEIVE_START \\r
+ (I2C_MASTER_CS_ACK | I2C_MASTER_CS_START | I2C_MASTER_CS_RUN)\r
+#define I2C_MASTER_CMD_BURST_RECEIVE_CONT \\r
+ (I2C_MASTER_CS_ACK | I2C_MASTER_CS_RUN)\r
+#define I2C_MASTER_CMD_BURST_RECEIVE_FINISH \\r
+ (I2C_MASTER_CS_STOP | I2C_MASTER_CS_RUN)\r
+#define I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP \\r
+ (I2C_MASTER_CS_STOP | I2C_MASTER_CS_RUN)\r
+\r
+//*****************************************************************************\r
+//\r
+// I2C Master error status.\r
+//\r
+//*****************************************************************************\r
+#define I2C_MASTER_ERR_NONE 0\r
+#define I2C_MASTER_ERR_ADDR_ACK 0x00000004\r
+#define I2C_MASTER_ERR_DATA_ACK 0x00000008\r
+#define I2C_MASTER_ERR_ARB_LOST 0x00000010\r
+\r
+//*****************************************************************************\r
+//\r
+// I2C Slave action requests\r
+//\r
+//*****************************************************************************\r
+#define I2C_SLAVE_ACT_NONE 0\r
+#define I2C_SLAVE_ACT_RREQ 0x00000001 // Master has sent data\r
+#define I2C_SLAVE_ACT_TREQ 0x00000002 // Master has requested data\r
+\r
+//*****************************************************************************\r
+// Miscellaneous I2C driver definitions.\r
+//*****************************************************************************\r
+#define I2C_MASTER_MAX_RETRIES 1000 // Number of retries\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+extern void I2CIntRegister(unsigned long ulBase, void(fnHandler)(void));\r
+extern void I2CIntUnregister(unsigned long ulBase);\r
+extern tBoolean I2CMasterBusBusy(unsigned long ulBase);\r
+extern tBoolean I2CMasterBusy(unsigned long ulBase);\r
+extern void I2CMasterControl(unsigned long ulBase, unsigned long ulCmd);\r
+extern unsigned long I2CMasterDataGet(unsigned long ulBase);\r
+extern void I2CMasterDataPut(unsigned long ulBase, unsigned char ucData);\r
+extern void I2CMasterDisable(unsigned long ulBase);\r
+extern void I2CMasterEnable(unsigned long ulBase);\r
+extern unsigned long I2CMasterErr(unsigned long ulBase);\r
+extern void I2CMasterInit(unsigned long ulBase, tBoolean bFast);\r
+extern void I2CMasterIntClear(unsigned long ulBase);\r
+extern void I2CMasterIntDisable(unsigned long ulBase);\r
+extern void I2CMasterIntEnable(unsigned long ulBase);\r
+extern tBoolean I2CMasterIntStatus(unsigned long ulBase, tBoolean bMasked);\r
+extern void I2CMasterSlaveAddrSet(unsigned long ulBase,\r
+ unsigned char ucSlaveAddr,\r
+ tBoolean bReceive);\r
+extern unsigned long I2CSlaveDataGet(unsigned long ulBase);\r
+extern void I2CSlaveDataPut(unsigned long ulBase, unsigned char ucData);\r
+extern void I2CSlaveDisable(unsigned long ulBase);\r
+extern void I2CSlaveEnable(unsigned long ulBase);\r
+extern void I2CSlaveInit(unsigned long ulBase, unsigned char ucSlaveAddr);\r
+extern void I2CSlaveIntClear(unsigned long ulBase);\r
+extern void I2CSlaveIntDisable(unsigned long ulBase);\r
+extern void I2CSlaveIntEnable(unsigned long ulBase);\r
+extern tBoolean I2CSlaveIntStatus(unsigned long ulBase, tBoolean bMasked);\r
+extern unsigned long I2CSlaveStatus(unsigned long ulBase);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __I2C_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// interrupt.h - Prototypes for the NVIC Interrupt Controller Driver.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __INTERRUPT_H__\r
+#define __INTERRUPT_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+extern void IntMasterEnable(void);\r
+extern void IntMasterDisable(void);\r
+extern void IntRegister(unsigned long ulInterrupt, void (*pfnHandler)(void));\r
+extern void IntUnregister(unsigned long ulInterrupt);\r
+extern void IntPriorityGroupingSet(unsigned long ulBits);\r
+extern unsigned long IntPriorityGroupingGet(void);\r
+extern void IntPrioritySet(unsigned long ulInterrupt,\r
+ unsigned char ucPriority);\r
+extern long IntPriorityGet(unsigned long ulInterrupt);\r
+extern void IntEnable(unsigned long ulInterrupt);\r
+extern void IntDisable(unsigned long ulInterrupt);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __INTERRUPT_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// flash.h - Prototypes for the flash driver.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __FLASH_H__\r
+#define __FLASH_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to FlashProtectSet(), and returned by\r
+// FlashProtectGet().\r
+//\r
+//*****************************************************************************\r
+typedef enum\r
+{\r
+ FlashReadWrite, // Flash can be read and written\r
+ FlashReadOnly, // Flash can only be read\r
+ FlashExecuteOnly // Flash can only be executed\r
+}\r
+tFlashProtection;\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+extern unsigned long FlashUsecGet(void);\r
+extern void FlashUsecSet(unsigned long ulClocks);\r
+extern long FlashErase(unsigned long ulAddress);\r
+extern long FlashProgram(unsigned long *pulData, unsigned long ulAddress,\r
+ unsigned long ulCount);\r
+extern tFlashProtection FlashProtectGet(unsigned long ulAddress);\r
+extern long FlashProtectSet(unsigned long ulAddress,\r
+ tFlashProtection eProtect);\r
+extern long FlashProtectSave(void);\r
+extern long FlashUserGet(unsigned long *pulUser0, unsigned long *pulUser1);\r
+extern long FlashUserSet(unsigned long ulUser0, unsigned long ulUser1);\r
+extern long FlashUserSave(void);\r
+extern void FlashIntRegister(void (*pfnHandler)(void));\r
+extern void FlashIntUnregister(void);\r
+extern void FlashIntEnable(unsigned long ulIntFlags);\r
+extern void FlashIntDisable(unsigned long ulIntFlags);\r
+extern unsigned long FlashIntGetStatus(tBoolean bMasked);\r
+extern void FlashIntClear(unsigned long ulIntFlags);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __FLASH_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// timer.h - Prototypes for the timer module\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __TIMER_H__\r
+#define __TIMER_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to TimerConfigure as the ulConfig parameter.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_CFG_32_BIT_OS 0x00000001 // 32-bit one-shot timer\r
+#define TIMER_CFG_32_BIT_PER 0x00000002 // 32-bit periodic timer\r
+#define TIMER_CFG_32_RTC 0x01000000 // 32-bit RTC timer\r
+#define TIMER_CFG_16_BIT_PAIR 0x04000000 // Two 16-bit timers\r
+#define TIMER_CFG_A_ONE_SHOT 0x00000001 // Timer A one-shot timer\r
+#define TIMER_CFG_A_PERIODIC 0x00000002 // Timer A periodic timer\r
+#define TIMER_CFG_A_CAP_COUNT 0x00000003 // Timer A event counter\r
+#define TIMER_CFG_A_CAP_TIME 0x00000007 // Timer A event timer\r
+#define TIMER_CFG_A_PWM 0x0000000A // Timer A PWM output\r
+#define TIMER_CFG_B_ONE_SHOT 0x00000100 // Timer B one-shot timer\r
+#define TIMER_CFG_B_PERIODIC 0x00000200 // Timer B periodic timer\r
+#define TIMER_CFG_B_CAP_COUNT 0x00000300 // Timer B event counter\r
+#define TIMER_CFG_B_CAP_TIME 0x00000700 // Timer B event timer\r
+#define TIMER_CFG_B_PWM 0x00000A00 // Timer B PWM output\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to TimerIntEnable, TimerIntDisable, and\r
+// TimerIntClear as the ulIntFlags parameter, and returned from TimerIntStatus.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_CAPB_EVENT 0x00000400 // CaptureB event interrupt\r
+#define TIMER_CAPB_MATCH 0x00000200 // CaptureB match interrupt\r
+#define TIMER_TIMB_TIMEOUT 0x00000100 // TimerB time out interrupt\r
+#define TIMER_RTC_MATCH 0x00000008 // RTC interrupt mask\r
+#define TIMER_CAPA_EVENT 0x00000004 // CaptureA event interrupt\r
+#define TIMER_CAPA_MATCH 0x00000002 // CaptureA match interrupt\r
+#define TIMER_TIMA_TIMEOUT 0x00000001 // TimerA time out interrupt\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to TimerControlEvent as the ulEvent parameter.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_EVENT_POS_EDGE 0x00000000 // Count positive edges\r
+#define TIMER_EVENT_NEG_EDGE 0x00000404 // Count negative edges\r
+#define TIMER_EVENT_BOTH_EDGES 0x00000C0C // Count both edges\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to most of the timer APIs as the ulTimer\r
+// parameter.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_A 0x000000ff // Timer A\r
+#define TIMER_B 0x0000ff00 // Timer B\r
+#define TIMER_BOTH 0x0000ffff // Timer Both\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+extern void TimerEnable(unsigned long ulBase, unsigned long ulTimer);\r
+extern void TimerDisable(unsigned long ulBase, unsigned long ulTimer);\r
+extern void TimerConfigure(unsigned long ulBase, unsigned long ulConfig);\r
+extern void TimerControlLevel(unsigned long ulBase, unsigned long ulTimer,\r
+ tBoolean bInvert);\r
+extern void TimerControlTrigger(unsigned long ulBase, unsigned long ulTimer,\r
+ tBoolean bEnable);\r
+extern void TimerControlEvent(unsigned long ulBase, unsigned long ulTimer,\r
+ unsigned long ulEvent);\r
+extern void TimerControlStall(unsigned long ulBase, unsigned long ulTimer,\r
+ tBoolean bStall);\r
+extern void TimerRTCEnable(unsigned long ulBase);\r
+extern void TimerRTCDisable(unsigned long ulBase);\r
+extern void TimerPrescaleSet(unsigned long ulBase, unsigned long ulTimer,\r
+ unsigned long ulValue);\r
+extern unsigned long TimerPrescaleGet(unsigned long ulBase,\r
+ unsigned long ulTimer);\r
+extern void TimerPrescaleMatchSet(unsigned long ulBase, unsigned long ulTimer,\r
+ unsigned long ulValue);\r
+extern unsigned long TimerPrescaleMatchGet(unsigned long ulBase,\r
+ unsigned long ulTimer);\r
+extern void TimerLoadSet(unsigned long ulBase, unsigned long ulTimer,\r
+ unsigned long ulValue);\r
+extern unsigned long TimerLoadGet(unsigned long ulBase, unsigned long ulTimer);\r
+extern unsigned long TimerValueGet(unsigned long ulBase,\r
+ unsigned long ulTimer);\r
+extern void TimerMatchSet(unsigned long ulBase, unsigned long ulTimer,\r
+ unsigned long ulValue);\r
+extern unsigned long TimerMatchGet(unsigned long ulBase,\r
+ unsigned long ulTimer);\r
+extern void TimerIntRegister(unsigned long ulBase, unsigned long ulTimer,\r
+ void (*pfnHandler)(void));\r
+extern void TimerIntUnregister(unsigned long ulBase, unsigned long ulTimer);\r
+extern void TimerIntEnable(unsigned long ulBase, unsigned long ulIntFlags);\r
+extern void TimerIntDisable(unsigned long ulBase, unsigned long ulIntFlags);\r
+extern unsigned long TimerIntStatus(unsigned long ulBase, tBoolean bMasked);\r
+extern void TimerIntClear(unsigned long ulBase, unsigned long ulIntFlags);\r
+extern void TimerQuiesce(unsigned long ulBase);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __TIMER_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// osram128x64x4.c - Driver for the OSRAM 128x64x4 graphical OLED display.\r
+//\r
+// Copyright (c) 2006-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+//*****************************************************************************\r
+//\r
+//! \addtogroup ek_lm3sx965_api\r
+//! @{\r
+//\r
+//*****************************************************************************\r
+\r
+#include "hw_ssi.h"\r
+#include "hw_memmap.h"\r
+#include "hw_sysctl.h"\r
+#include "hw_types.h"\r
+#include "debug.h"\r
+#include "gpio.h"\r
+#include "ssi.h"\r
+#include "sysctl.h"\r
+#include "osram128x64x4.h"\r
+\r
+//*****************************************************************************\r
+//\r
+// Flag to indicate if SSI port is enabled for OSRAM usage.\r
+//\r
+//*****************************************************************************\r
+static volatile tBoolean g_bSSIEnabled = false;\r
+\r
+//*****************************************************************************\r
+//\r
+// Define the OSRAM 128x64x4 Remap Setting(s). This will be used in\r
+// several places in the code to switch between vertical and horizontal\r
+// address incrementing.\r
+//\r
+// The Remap Command (0xA0) takes one 8-bit parameter. The parameter is\r
+// defined as follows.\r
+//\r
+// Bit 7: Reserved\r
+// Bit 6: Disable(0)/Enable(1) COM Split Odd Even\r
+// When enabled, the COM signals are split Odd on one side, even on\r
+// the other. Otherwise, they are split 0-39 on one side, 40-79 on\r
+// the other.\r
+// Bit 5: Reserved\r
+// Bit 4: Disable(0)/Enable(1) COM Remap\r
+// When Enabled, ROW 0-79 map to COM 79-0 (i.e. reverse row order)\r
+// Bit 3: Reserved\r
+// Bit 2: Horizontal(0)/Vertical(1) Address Increment\r
+// When set, data RAM address will increment along the column rather\r
+// than along the row.\r
+// Bit 1: Disable(0)/Enable(1) Nibble Remap\r
+// When enabled, the upper and lower nibbles in the DATA bus for access\r
+// to the data RAM are swapped.\r
+// Bit 0: Disable(0)/Enable(1) Column Address Remap\r
+// When enabled, DATA RAM columns 0-63 are remapped to Segment Columns\r
+// 127-0.\r
+//\r
+//*****************************************************************************\r
+#define OSRAM_INIT_REMAP 0x52\r
+#define OSRAM_INIT_OFFSET 0x4C\r
+static const unsigned char g_pucOSRAM128x64x4VerticalInc[] = { 0xA0, 0x56 };\r
+static const unsigned char g_pucOSRAM128x64x4HorizontalInc[] = { 0xA0, 0x52 };\r
+\r
+//*****************************************************************************\r
+//\r
+// A 5x7 font (in a 6x8 cell, where the sixth column is omitted from this\r
+// table) for displaying text on the OLED display. The data is organized as\r
+// bytes from the left column to the right column, with each byte containing\r
+// the top row in the LSB and the bottom row in the MSB.\r
+//\r
+// Note: This is the same font data that is used in the EK-LM3S811\r
+// osram96x16x1 driver. The single bit-per-pixel is expaned in the StringDraw\r
+// function to the appropriate four bit-per-pixel gray scale format.\r
+//\r
+//*****************************************************************************\r
+static const unsigned char g_pucFont[96][5] =\r
+{\r
+ { 0x00, 0x00, 0x00, 0x00, 0x00 }, // " "\r
+ { 0x00, 0x00, 0x4f, 0x00, 0x00 }, // !\r
+ { 0x00, 0x07, 0x00, 0x07, 0x00 }, // "\r
+ { 0x14, 0x7f, 0x14, 0x7f, 0x14 }, // #\r
+ { 0x24, 0x2a, 0x7f, 0x2a, 0x12 }, // $\r
+ { 0x23, 0x13, 0x08, 0x64, 0x62 }, // %\r
+ { 0x36, 0x49, 0x55, 0x22, 0x50 }, // &\r
+ { 0x00, 0x05, 0x03, 0x00, 0x00 }, // '\r
+ { 0x00, 0x1c, 0x22, 0x41, 0x00 }, // (\r
+ { 0x00, 0x41, 0x22, 0x1c, 0x00 }, // )\r
+ { 0x14, 0x08, 0x3e, 0x08, 0x14 }, // *\r
+ { 0x08, 0x08, 0x3e, 0x08, 0x08 }, // +\r
+ { 0x00, 0x50, 0x30, 0x00, 0x00 }, // ,\r
+ { 0x08, 0x08, 0x08, 0x08, 0x08 }, // -\r
+ { 0x00, 0x60, 0x60, 0x00, 0x00 }, // .\r
+ { 0x20, 0x10, 0x08, 0x04, 0x02 }, // /\r
+ { 0x3e, 0x51, 0x49, 0x45, 0x3e }, // 0\r
+ { 0x00, 0x42, 0x7f, 0x40, 0x00 }, // 1\r
+ { 0x42, 0x61, 0x51, 0x49, 0x46 }, // 2\r
+ { 0x21, 0x41, 0x45, 0x4b, 0x31 }, // 3\r
+ { 0x18, 0x14, 0x12, 0x7f, 0x10 }, // 4\r
+ { 0x27, 0x45, 0x45, 0x45, 0x39 }, // 5\r
+ { 0x3c, 0x4a, 0x49, 0x49, 0x30 }, // 6\r
+ { 0x01, 0x71, 0x09, 0x05, 0x03 }, // 7\r
+ { 0x36, 0x49, 0x49, 0x49, 0x36 }, // 8\r
+ { 0x06, 0x49, 0x49, 0x29, 0x1e }, // 9\r
+ { 0x00, 0x36, 0x36, 0x00, 0x00 }, // :\r
+ { 0x00, 0x56, 0x36, 0x00, 0x00 }, // ;\r
+ { 0x08, 0x14, 0x22, 0x41, 0x00 }, // <\r
+ { 0x14, 0x14, 0x14, 0x14, 0x14 }, // =\r
+ { 0x00, 0x41, 0x22, 0x14, 0x08 }, // >\r
+ { 0x02, 0x01, 0x51, 0x09, 0x06 }, // ?\r
+ { 0x32, 0x49, 0x79, 0x41, 0x3e }, // @\r
+ { 0x7e, 0x11, 0x11, 0x11, 0x7e }, // A\r
+ { 0x7f, 0x49, 0x49, 0x49, 0x36 }, // B\r
+ { 0x3e, 0x41, 0x41, 0x41, 0x22 }, // C\r
+ { 0x7f, 0x41, 0x41, 0x22, 0x1c }, // D\r
+ { 0x7f, 0x49, 0x49, 0x49, 0x41 }, // E\r
+ { 0x7f, 0x09, 0x09, 0x09, 0x01 }, // F\r
+ { 0x3e, 0x41, 0x49, 0x49, 0x7a }, // G\r
+ { 0x7f, 0x08, 0x08, 0x08, 0x7f }, // H\r
+ { 0x00, 0x41, 0x7f, 0x41, 0x00 }, // I\r
+ { 0x20, 0x40, 0x41, 0x3f, 0x01 }, // J\r
+ { 0x7f, 0x08, 0x14, 0x22, 0x41 }, // K\r
+ { 0x7f, 0x40, 0x40, 0x40, 0x40 }, // L\r
+ { 0x7f, 0x02, 0x0c, 0x02, 0x7f }, // M\r
+ { 0x7f, 0x04, 0x08, 0x10, 0x7f }, // N\r
+ { 0x3e, 0x41, 0x41, 0x41, 0x3e }, // O\r
+ { 0x7f, 0x09, 0x09, 0x09, 0x06 }, // P\r
+ { 0x3e, 0x41, 0x51, 0x21, 0x5e }, // Q\r
+ { 0x7f, 0x09, 0x19, 0x29, 0x46 }, // R\r
+ { 0x46, 0x49, 0x49, 0x49, 0x31 }, // S\r
+ { 0x01, 0x01, 0x7f, 0x01, 0x01 }, // T\r
+ { 0x3f, 0x40, 0x40, 0x40, 0x3f }, // U\r
+ { 0x1f, 0x20, 0x40, 0x20, 0x1f }, // V\r
+ { 0x3f, 0x40, 0x38, 0x40, 0x3f }, // W\r
+ { 0x63, 0x14, 0x08, 0x14, 0x63 }, // X\r
+ { 0x07, 0x08, 0x70, 0x08, 0x07 }, // Y\r
+ { 0x61, 0x51, 0x49, 0x45, 0x43 }, // Z\r
+ { 0x00, 0x7f, 0x41, 0x41, 0x00 }, // [\r
+ { 0x02, 0x04, 0x08, 0x10, 0x20 }, // "\"\r
+ { 0x00, 0x41, 0x41, 0x7f, 0x00 }, // ]\r
+ { 0x04, 0x02, 0x01, 0x02, 0x04 }, // ^\r
+ { 0x40, 0x40, 0x40, 0x40, 0x40 }, // _\r
+ { 0x00, 0x01, 0x02, 0x04, 0x00 }, // `\r
+ { 0x20, 0x54, 0x54, 0x54, 0x78 }, // a\r
+ { 0x7f, 0x48, 0x44, 0x44, 0x38 }, // b\r
+ { 0x38, 0x44, 0x44, 0x44, 0x20 }, // c\r
+ { 0x38, 0x44, 0x44, 0x48, 0x7f }, // d\r
+ { 0x38, 0x54, 0x54, 0x54, 0x18 }, // e\r
+ { 0x08, 0x7e, 0x09, 0x01, 0x02 }, // f\r
+ { 0x0c, 0x52, 0x52, 0x52, 0x3e }, // g\r
+ { 0x7f, 0x08, 0x04, 0x04, 0x78 }, // h\r
+ { 0x00, 0x44, 0x7d, 0x40, 0x00 }, // i\r
+ { 0x20, 0x40, 0x44, 0x3d, 0x00 }, // j\r
+ { 0x7f, 0x10, 0x28, 0x44, 0x00 }, // k\r
+ { 0x00, 0x41, 0x7f, 0x40, 0x00 }, // l\r
+ { 0x7c, 0x04, 0x18, 0x04, 0x78 }, // m\r
+ { 0x7c, 0x08, 0x04, 0x04, 0x78 }, // n\r
+ { 0x38, 0x44, 0x44, 0x44, 0x38 }, // o\r
+ { 0x7c, 0x14, 0x14, 0x14, 0x08 }, // p\r
+ { 0x08, 0x14, 0x14, 0x18, 0x7c }, // q\r
+ { 0x7c, 0x08, 0x04, 0x04, 0x08 }, // r\r
+ { 0x48, 0x54, 0x54, 0x54, 0x20 }, // s\r
+ { 0x04, 0x3f, 0x44, 0x40, 0x20 }, // t\r
+ { 0x3c, 0x40, 0x40, 0x20, 0x7c }, // u\r
+ { 0x1c, 0x20, 0x40, 0x20, 0x1c }, // v\r
+ { 0x3c, 0x40, 0x30, 0x40, 0x3c }, // w\r
+ { 0x44, 0x28, 0x10, 0x28, 0x44 }, // x\r
+ { 0x0c, 0x50, 0x50, 0x50, 0x3c }, // y\r
+ { 0x44, 0x64, 0x54, 0x4c, 0x44 }, // z\r
+ { 0x00, 0x08, 0x36, 0x41, 0x00 }, // {\r
+ { 0x00, 0x00, 0x7f, 0x00, 0x00 }, // |\r
+ { 0x00, 0x41, 0x36, 0x08, 0x00 }, // }\r
+ { 0x02, 0x01, 0x02, 0x04, 0x02 }, // ~\r
+ { 0x02, 0x01, 0x02, 0x04, 0x02 }, // ~\r
+};\r
+\r
+//*****************************************************************************\r
+//\r
+// The sequence of commands used to initialize the SSD0303 controller. Each\r
+// command is described as follows: there is a byte specifying the number of\r
+// bytes in the command sequence, followed by that many bytes of command data.\r
+// Note: This initialization sequence is derived from OSRAM App Note AN018.\r
+//\r
+//*****************************************************************************\r
+static const unsigned char g_pucOSRAM128x64x4Init[] =\r
+{\r
+ //\r
+ // Column Address\r
+ //\r
+ 4, 0x15, 0, 63, 0xe3,\r
+\r
+ //\r
+ // Row Address\r
+ //\r
+ 4, 0x75, 0, 63, 0xe3,\r
+\r
+ //\r
+ // Contrast Control\r
+ //\r
+ 3, 0x81, 50, 0xe3,\r
+\r
+ //\r
+ // Half Current Range\r
+ //\r
+ 2, 0x85, 0xe3,\r
+\r
+ //\r
+ // Display Re-map\r
+ //\r
+ 3, 0xA0, OSRAM_INIT_REMAP, 0xe3,\r
+\r
+ //\r
+ // Display Start Line\r
+ //\r
+ 3, 0xA1, 0, 0xe3,\r
+\r
+ //\r
+ // Display Offset\r
+ //\r
+ 3, 0xA2, OSRAM_INIT_OFFSET, 0xe3,\r
+\r
+ //\r
+ // Display Mode Normal\r
+ //\r
+ 2, 0xA4, 0xe3,\r
+\r
+ //\r
+ // Multiplex Ratio\r
+ //\r
+ 3, 0xA8, 63, 0xe3,\r
+\r
+ //\r
+ // Phase Length\r
+ //\r
+ 3, 0xB1, 0x22, 0xe3,\r
+\r
+ //\r
+ // Row Period\r
+ //\r
+ 3, 0xB2, 70, 0xe3,\r
+\r
+ //\r
+ // Display Clock Divide\r
+ //\r
+ 3, 0xB3, 0xF1, 0xe3,\r
+\r
+ //\r
+ // VSL\r
+ //\r
+ 3, 0xBF, 0x0D, 0xe3,\r
+\r
+ //\r
+ // VCOMH\r
+ //\r
+ 3, 0xBE, 0x02, 0xe3,\r
+\r
+ //\r
+ // VP\r
+ //\r
+ 3, 0xBC, 0x10, 0xe3,\r
+\r
+ //\r
+ // Gamma\r
+ //\r
+ 10, 0xB8, 0x01, 0x11, 0x22, 0x32, 0x43, 0x54, 0x65, 0x76, 0xe3,\r
+\r
+ //\r
+ // Set DC-DC\r
+ 3, 0xAD, 0x03, 0xe3,\r
+\r
+ //\r
+ // Display ON/OFF\r
+ //\r
+ 2, 0xAF, 0xe3,\r
+};\r
+\r
+//*****************************************************************************\r
+//\r
+//! \internal\r
+//!\r
+//! Write a sequence of command bytes to the SSD0323 controller.\r
+//!\r
+//! The data is written in a polled fashion; this function will not return\r
+//! until the entire byte sequence has been written to the controller.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+static void\r
+OSRAMWriteCommand(const unsigned char *pucBuffer, unsigned long ulCount)\r
+{\r
+ unsigned long ulTemp;\r
+\r
+ //\r
+ // Return iff SSI port is not enabled for OSRAM.\r
+ //\r
+ if(!g_bSSIEnabled)\r
+ {\r
+ return;\r
+ }\r
+\r
+ //\r
+ // Clear the command/control bit to enable command mode.\r
+ //\r
+ GPIOPinWrite(GPIO_PORTC_BASE, GPIO_PIN_7, 0);\r
+\r
+ //\r
+ // Loop while there are more bytes left to be transferred.\r
+ //\r
+ while(ulCount != 0)\r
+ {\r
+ //\r
+ // Write the next byte to the controller.\r
+ //\r
+ SSIDataPut(SSI0_BASE, *pucBuffer++);\r
+\r
+ //\r
+ // Dummy read to drain the fifo and time the GPIO signal.\r
+ //\r
+ SSIDataGet(SSI0_BASE, &ulTemp);\r
+\r
+ //\r
+ // Decrement the BYTE counter.\r
+ //\r
+ ulCount--;\r
+ }\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! \internal\r
+//!\r
+//! Write a sequence of data bytes to the SSD0323 controller.\r
+//!\r
+//! The data is written in a polled fashion; this function will not return\r
+//! until the entire byte sequence has been written to the controller.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+static void\r
+OSRAMWriteData(const unsigned char *pucBuffer, unsigned long ulCount)\r
+{\r
+ unsigned long ulTemp;\r
+\r
+ //\r
+ // Return iff SSI port is not enabled for OSRAM.\r
+ //\r
+ if(!g_bSSIEnabled)\r
+ {\r
+ return;\r
+ }\r
+\r
+ //\r
+ // Set the command/control bit to enable data mode.\r
+ //\r
+ GPIOPinWrite(GPIO_PORTC_BASE, GPIO_PIN_7, GPIO_PIN_7);\r
+\r
+ //\r
+ // Loop while there are more bytes left to be transferred.\r
+ //\r
+ while(ulCount != 0)\r
+ {\r
+ //\r
+ // Write the next byte to the controller.\r
+ //\r
+ SSIDataPut(SSI0_BASE, *pucBuffer++);\r
+\r
+ //\r
+ // Dummy read to drain the fifo and time the GPIO signal.\r
+ //\r
+ SSIDataGet(SSI0_BASE, &ulTemp);\r
+\r
+ //\r
+ // Decrement the BYTE counter.\r
+ //\r
+ ulCount--;\r
+ }\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! Clears the OLED display.\r
+//!\r
+//! This function will clear the display RAM. All pixels in the display will\r
+//! be turned off.\r
+//!\r
+//! This function is contained in <tt>osram128x64x4.c</tt>, with\r
+//! <tt>osram128x64x4.h</tt> containing the API definition for use by\r
+//! applications.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+void\r
+OSRAM128x64x4Clear(void)\r
+{\r
+ static const unsigned char pucCommand1[] = { 0x15, 0, 63 };\r
+ static const unsigned char pucCommand2[] = { 0x75, 0, 79 };\r
+ unsigned long ulRow, ulColumn;\r
+ static unsigned char pucZeroBuffer[8] = { 0, 0, 0, 0, 0, 0, 0, 0};\r
+\r
+ //\r
+ // Set the window to fill the entire display.\r
+ //\r
+ OSRAMWriteCommand(pucCommand1, sizeof(pucCommand1));\r
+ OSRAMWriteCommand(pucCommand2, sizeof(pucCommand2));\r
+ OSRAMWriteCommand(g_pucOSRAM128x64x4VerticalInc,\r
+ sizeof(g_pucOSRAM128x64x4VerticalInc));\r
+\r
+ //\r
+ // In vertical address increment mode, loop through each column, filling\r
+ // each row with 0.\r
+ //\r
+ for(ulColumn = 0; ulColumn < (128/2); ulColumn++)\r
+ {\r
+ //\r
+ // 8 rows (bytes) per row of text.\r
+ //\r
+ for(ulRow = 0; ulRow < 80; ulRow += 8)\r
+ {\r
+ OSRAMWriteData(pucZeroBuffer, sizeof(pucZeroBuffer));\r
+ }\r
+ }\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! Displays a string on the OLED display.\r
+//!\r
+//! \param pcStr is a pointer to the string to display.\r
+//! \param ulX is the horizontal position to display the string, specified in\r
+//! columns from the left edge of the display.\r
+//! \param ulY is the vertical position to display the string, specified in\r
+//! rows from the top edge of the display.\r
+//! \param ucLevel is the 4-bit grey scale value to be used for displayed text.\r
+//!\r
+//! This function will draw a string on the display. Only the ASCII characters\r
+//! between 32 (space) and 126 (tilde) are supported; other characters will\r
+//! result in random data being draw on the display (based on whatever appears\r
+//! before/after the font in memory). The font is mono-spaced, so characters\r
+//! such as "i" and "l" have more white space around them than characters such\r
+//! as "m" or "w".\r
+//!\r
+//! If the drawing of the string reaches the right edge of the display, no more\r
+//! characters will be drawn. Therefore, special care is not required to avoid\r
+//! supplying a string that is "too long" to display.\r
+//!\r
+//! This function is contained in <tt>osram128x64x4.c</tt>, with\r
+//! <tt>osram128x64x4.h</tt> containing the API definition for use by\r
+//! applications.\r
+//!\r
+//! \note Because the OLED display packs 2 pixels of data in a single byte, the\r
+//! parameter \e ulX must be an even column number (e.g. 0, 2, 4, etc).\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+void\r
+OSRAM128x64x4StringDraw(const char *pcStr, unsigned long ulX,\r
+ unsigned long ulY, unsigned char ucLevel)\r
+{\r
+ static unsigned char pucBuffer[8];\r
+ unsigned long ulIdx1, ulIdx2;\r
+ unsigned char ucTemp;\r
+\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT(ulX < 128);\r
+ ASSERT((ulX & 1) == 0);\r
+ ASSERT(ulY < 64);\r
+ ASSERT(ucLevel < 16);\r
+\r
+ //\r
+ // Setup a window starting at the specified column and row, ending\r
+ // at the right edge of the display and 8 rows down (single character row).\r
+ //\r
+ pucBuffer[0] = 0x15;\r
+ pucBuffer[1] = ulX / 2;\r
+ pucBuffer[2] = 63;\r
+ OSRAMWriteCommand(pucBuffer, 3);\r
+ pucBuffer[0] = 0x75;\r
+ pucBuffer[1] = ulY;\r
+ pucBuffer[2] = ulY + 7;\r
+ OSRAMWriteCommand(pucBuffer, 3);\r
+ OSRAMWriteCommand(g_pucOSRAM128x64x4VerticalInc,\r
+ sizeof(g_pucOSRAM128x64x4VerticalInc));\r
+\r
+ //\r
+ // Loop while there are more characters in the string.\r
+ //\r
+ while(*pcStr != 0)\r
+ {\r
+ //\r
+ // Get a working copy of the current character and convert to an\r
+ // index into the character bit-map array.\r
+ //\r
+ ucTemp = *pcStr;\r
+ ucTemp &= 0x7F;\r
+ if(ucTemp < ' ')\r
+ {\r
+ ucTemp = ' ';\r
+ }\r
+ else\r
+ {\r
+ ucTemp -= ' ';\r
+ }\r
+\r
+ //\r
+ // Build and display the character buffer.\r
+ //\r
+ for(ulIdx1 = 0; ulIdx1 < 3; ulIdx1++)\r
+ {\r
+ //\r
+ // Convert two columns of 1-bit font data into a single data\r
+ // byte column of 4-bit font data.\r
+ //\r
+ for(ulIdx2 = 0; ulIdx2 < 8; ulIdx2++)\r
+ {\r
+ pucBuffer[ulIdx2] = 0;\r
+ if(g_pucFont[ucTemp][ulIdx1*2] & (1 << ulIdx2))\r
+ {\r
+ pucBuffer[ulIdx2] = ((ucLevel << 4) & 0xf0);\r
+ }\r
+ if((ulIdx1 < 2) &&\r
+ (g_pucFont[ucTemp][ulIdx1*2+1] & (1 << ulIdx2)))\r
+ {\r
+ pucBuffer[ulIdx2] |= ((ucLevel << 0) & 0x0f);\r
+ }\r
+ }\r
+\r
+ //\r
+ // If there is room, dump the single data byte column to the\r
+ // display. Otherwise, bail out.\r
+ //\r
+ if(ulX < 126)\r
+ {\r
+ OSRAMWriteData(pucBuffer, 8);\r
+ ulX += 2;\r
+ }\r
+ else\r
+ {\r
+ return;\r
+ }\r
+ }\r
+\r
+ //\r
+ // Advance to the next character.\r
+ //\r
+ pcStr++;\r
+ }\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! Displays an image on the OLED display.\r
+//!\r
+//! \param pucImage is a pointer to the image data.\r
+//! \param ulX is the horizontal position to display this image, specified in\r
+//! columns from the left edge of the display.\r
+//! \param ulY is the vertical position to display this image, specified in\r
+//! rows from the top of the display.\r
+//! \param ulWidth is the width of the image, specified in columns.\r
+//! \param ulHeight is the height of the image, specified in rows.\r
+//!\r
+//! This function will display a bitmap graphic on the display. Because of the\r
+//! format of the display RAM, the starting column (/e ulX) and the number of\r
+//! columns (/e ulWidth) must be an integer multiple of two.\r
+//!\r
+//! The image data is organized with the first row of image data appearing left\r
+//! to right, followed immediately by the second row of image data. Each byte\r
+//! contains the data for two columns in the current row, with the leftmost\r
+//! column being contained in bits 7:4 and the rightmost column being contained\r
+//! in bits 3:0.\r
+//!\r
+//! For example, an image six columns wide and seven scan lines tall would\r
+//! be arranged as follows (showing how the twenty one bytes of the image would\r
+//! appear on the display):\r
+//!\r
+//! \verbatim\r
+//! +-------------------+-------------------+-------------------+\r
+//! | Byte 0 | Byte 1 | Byte 2 |\r
+//! +---------+---------+---------+---------+---------+---------+\r
+//! | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 |\r
+//! +---------+---------+---------+---------+---------+---------+\r
+//! | Byte 3 | Byte 4 | Byte 5 |\r
+//! +---------+---------+---------+---------+---------+---------+\r
+//! | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 |\r
+//! +---------+---------+---------+---------+---------+---------+\r
+//! | Byte 6 | Byte 7 | Byte 8 |\r
+//! +---------+---------+---------+---------+---------+---------+\r
+//! | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 |\r
+//! +---------+---------+---------+---------+---------+---------+\r
+//! | Byte 9 | Byte 10 | Byte 11 |\r
+//! +---------+---------+---------+---------+---------+---------+\r
+//! | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 |\r
+//! +---------+---------+---------+---------+---------+---------+\r
+//! | Byte 12 | Byte 13 | Byte 14 |\r
+//! +---------+---------+---------+--3------+---------+---------+\r
+//! | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 |\r
+//! +---------+---------+---------+---------+---------+---------+\r
+//! | Byte 15 | Byte 16 | Byte 17 |\r
+//! +---------+---------+---------+---------+---------+---------+\r
+//! | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 |\r
+//! +---------+---------+---------+---------+---------+---------+\r
+//! | Byte 18 | Byte 19 | Byte 20 |\r
+//! +---------+---------+---------+---------+---------+---------+\r
+//! | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 |\r
+//! +---------+---------+---------+---------+---------+---------+\r
+//! \endverbatim\r
+//!\r
+//! This function is contained in <tt>osram128x64x4.c</tt>, with\r
+//! <tt>osram128x64x4.h</tt> containing the API definition for use by`\r
+//! applications.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+void\r
+OSRAM128x64x4ImageDraw(const unsigned char *pucImage, unsigned long ulX,\r
+ unsigned long ulY, unsigned long ulWidth,\r
+ unsigned long ulHeight)\r
+{\r
+ static unsigned char pucBuffer[8];\r
+\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT(ulX < 128);\r
+ ASSERT((ulX & 1) == 0);\r
+ ASSERT(ulY < 64);\r
+ ASSERT((ulX + ulWidth) <= 128);\r
+ ASSERT((ulY + ulHeight) <= 64);\r
+ ASSERT((ulWidth & 1) == 0);\r
+\r
+ //\r
+ // Setup a window starting at the specified column and row, and ending\r
+ // at the column + width and row+height.\r
+ //\r
+ pucBuffer[0] = 0x15;\r
+ pucBuffer[1] = ulX / 2;\r
+ pucBuffer[2] = (ulX + ulWidth - 2) / 2;\r
+ OSRAMWriteCommand(pucBuffer, 3);\r
+ pucBuffer[0] = 0x75;\r
+ pucBuffer[1] = ulY;\r
+ pucBuffer[2] = ulY + ulHeight - 1;\r
+ OSRAMWriteCommand(pucBuffer, 3);\r
+ OSRAMWriteCommand(g_pucOSRAM128x64x4HorizontalInc,\r
+ sizeof(g_pucOSRAM128x64x4HorizontalInc));\r
+\r
+ //\r
+ // Loop while there are more rows to display.\r
+ //\r
+ while(ulHeight--)\r
+ {\r
+ //\r
+ // Write this row of image data.\r
+ //\r
+ OSRAMWriteData(pucImage, (ulWidth / 2));\r
+\r
+ //\r
+ // Advance to the next row of the image.\r
+ //\r
+ pucImage += (ulWidth / 2);\r
+ }\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! Enable the SSI component of the OLED display driver.\r
+//!\r
+//! \param ulFrequency specifies the SSI Clock Frequency to be used.\r
+//!\r
+//! This function initializes the SSI interface to the OLED display.\r
+//!\r
+//! This function is contained in <tt>osram128x64x4.c</tt>, with\r
+//! <tt>osram128x64x4.h</tt> containing the API definition for use by\r
+//! applications.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+void\r
+OSRAM128x64x4Enable(unsigned long ulFrequency)\r
+{\r
+ unsigned long ulTemp;\r
+\r
+ //\r
+ // Disable the SSI port.\r
+ //\r
+ SSIDisable(SSI0_BASE);\r
+\r
+ //\r
+ // Configure the SSI0 port for master mode.\r
+ //\r
+ SSIConfig(SSI0_BASE, SSI_FRF_MOTO_MODE_2, SSI_MODE_MASTER, ulFrequency, 8);\r
+\r
+ //\r
+ // (Re)Enable SSI control of the FSS pin.\r
+ //\r
+ GPIOPinTypeSSI(GPIO_PORTA_BASE, GPIO_PIN_3);\r
+ GPIOPadConfigSet(GPIO_PORTA_BASE, GPIO_PIN_3, GPIO_STRENGTH_8MA,\r
+ GPIO_PIN_TYPE_STD_WPU);\r
+\r
+ //\r
+ // Enable the SSI port.\r
+ //\r
+ SSIEnable(SSI0_BASE);\r
+\r
+ //\r
+ // Drain the receive fifo.\r
+ //\r
+ while(SSIDataNonBlockingGet(SSI0_BASE, &ulTemp) != 0)\r
+ {\r
+ }\r
+\r
+ //\r
+ // Indicate that the OSRAM driver can use the SSI Port.\r
+ //\r
+ g_bSSIEnabled = true;\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! Enable the SSI component of the OLED display driver.\r
+//!\r
+//! \param ulFrequency specifies the SSI Clock Frequency to be used.\r
+//!\r
+//! This function initializes the SSI interface to the OLED display.\r
+//!\r
+//! This function is contained in <tt>osram128x64x4.c</tt>, with\r
+//! <tt>osram128x64x4.h</tt> containing the API definition for use by\r
+//! applications.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+void\r
+OSRAM128x64x4Disable(void)\r
+{\r
+ unsigned long ulTemp;\r
+\r
+ //\r
+ // Indicate that the OSRAM driver can no longer use the SSI Port.\r
+ //\r
+ g_bSSIEnabled = false;\r
+\r
+ //\r
+ // Drain the receive fifo.\r
+ //\r
+ while(SSIDataNonBlockingGet(SSI0_BASE, &ulTemp) != 0)\r
+ {\r
+ }\r
+\r
+ //\r
+ // Disable the SSI port.\r
+ //\r
+ SSIDisable(SSI0_BASE);\r
+\r
+ //\r
+ // Disable SSI control of the FSS pin.\r
+ //\r
+ GPIODirModeSet(GPIO_PORTA_BASE, GPIO_PIN_3, GPIO_DIR_MODE_OUT);\r
+ GPIOPadConfigSet(GPIO_PORTA_BASE, GPIO_PIN_3, GPIO_STRENGTH_8MA,\r
+ GPIO_PIN_TYPE_STD_WPU);\r
+ GPIOPinWrite(GPIO_PORTA_BASE, GPIO_PIN_3, GPIO_PIN_3);\r
+\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! Initialize the OLED display.\r
+//!\r
+//! \param ulFrequency specifies the SSI Clock Frequency to be used.\r
+//!\r
+//! This function initializes the SSI interface to the OLED display and\r
+//! configures the SSD0323 controller on the panel.\r
+//!\r
+//! This function is contained in <tt>osram128x64x4.c</tt>, with\r
+//! <tt>osram128x64x4.h</tt> containing the API definition for use by\r
+//! applications.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+void\r
+OSRAM128x64x4Init(unsigned long ulFrequency)\r
+{\r
+ unsigned long ulIdx;\r
+\r
+ //\r
+ // Enable the SSI0 and GPIO port blocks as they are needed by this driver.\r
+ //\r
+ SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI0);\r
+ SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA);\r
+ SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOC);\r
+\r
+ //\r
+ // Configure the SSI0CLK and SSIOTX pins for SSI operation.\r
+ //\r
+ GPIOPinTypeSSI(GPIO_PORTA_BASE, GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_5);\r
+ GPIOPadConfigSet(GPIO_PORTA_BASE, GPIO_PIN_2, GPIO_STRENGTH_8MA,\r
+ GPIO_PIN_TYPE_STD_WPU);\r
+ GPIOPadConfigSet(GPIO_PORTA_BASE, GPIO_PIN_3, GPIO_STRENGTH_8MA,\r
+ GPIO_PIN_TYPE_STD_WPU);\r
+ GPIOPadConfigSet(GPIO_PORTA_BASE, GPIO_PIN_5, GPIO_STRENGTH_8MA,\r
+ GPIO_PIN_TYPE_STD_WPU);\r
+\r
+ //\r
+ // Configure the PC7 pin as a D/Cn signal for OLED device.\r
+ //\r
+ GPIODirModeSet(GPIO_PORTC_BASE, GPIO_PIN_7, GPIO_DIR_MODE_OUT);\r
+ GPIOPadConfigSet(GPIO_PORTC_BASE, GPIO_PIN_7, GPIO_STRENGTH_8MA,\r
+ GPIO_PIN_TYPE_STD);\r
+ GPIOPinWrite(GPIO_PORTC_BASE, GPIO_PIN_7, GPIO_PIN_7);\r
+\r
+ //\r
+ // Configure and enable the SSI0 port for master mode.\r
+ //\r
+ OSRAM128x64x4Enable(ulFrequency);\r
+\r
+ //\r
+ // Clear the frame buffer.\r
+ //\r
+ OSRAM128x64x4Clear();\r
+\r
+ //\r
+ // Initialize the SSD0323 controller. Loop through the initialization\r
+ // sequence array, sending each command "string" to the controller.\r
+ //\r
+ for(ulIdx = 0; ulIdx < sizeof(g_pucOSRAM128x64x4Init);\r
+ ulIdx += g_pucOSRAM128x64x4Init[ulIdx] + 1)\r
+ {\r
+ //\r
+ // Send this command.\r
+ //\r
+ OSRAMWriteCommand(g_pucOSRAM128x64x4Init + ulIdx + 1,\r
+ g_pucOSRAM128x64x4Init[ulIdx] - 1);\r
+ }\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! Turns on the OLED display.\r
+//!\r
+//! This function will turn on the OLED display, causing it to display the\r
+//! contents of its internal frame buffer.\r
+//!\r
+//! This function is contained in <tt>osram128x64x4.c</tt>, with\r
+//! <tt>osram128x64x4.h</tt> containing the API definition for use by\r
+//! applications.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+void\r
+OSRAM128x64x4DisplayOn(void)\r
+{\r
+ unsigned long ulIdx;\r
+\r
+ //\r
+ // Initialize the SSD0323 controller. Loop through the initialization\r
+ // sequence array, sending each command "string" to the controller.\r
+ //\r
+ for(ulIdx = 0; ulIdx < sizeof(g_pucOSRAM128x64x4Init);\r
+ ulIdx += g_pucOSRAM128x64x4Init[ulIdx] + 1)\r
+ {\r
+ //\r
+ // Send this command.\r
+ //\r
+ OSRAMWriteCommand(g_pucOSRAM128x64x4Init + ulIdx + 1,\r
+ g_pucOSRAM128x64x4Init[ulIdx] - 1);\r
+ }\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! Turns off the OLED display.\r
+//!\r
+//! This function will turn off the OLED display. This will stop the scanning\r
+//! of the panel and turn off the on-chip DC-DC converter, preventing damage to\r
+//! the panel due to burn-in (it has similar characters to a CRT in this\r
+//! respect).\r
+//!\r
+//! This function is contained in <tt>osram128x64x4.c</tt>, with\r
+//! <tt>osram128x64x4.h</tt> containing the API definition for use by\r
+//! applications.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+void\r
+OSRAM128x64x4DisplayOff(void)\r
+{\r
+ static const unsigned char pucCommand1[] =\r
+ {\r
+ 0xAE, 0xAD, 0x02\r
+ };\r
+\r
+ //\r
+ // Turn off the DC-DC converter and the display.\r
+ //\r
+ OSRAMWriteCommand(pucCommand1, sizeof(pucCommand1));\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+// Close the Doxygen group.\r
+//! @}\r
+//\r
+//*****************************************************************************\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// osram128x64x4.h - Prototypes for the driver for the OSRAM 128x64x4 graphical\r
+// OLED display.\r
+//\r
+// Copyright (c) 2006-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __OSRAM128X64X4_H__\r
+#define __OSRAM128X64X4_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the driver APIs.\r
+//\r
+//*****************************************************************************\r
+extern void OSRAM128x64x4Clear(void);\r
+extern void OSRAM128x64x4StringDraw(const char *pcStr,\r
+ unsigned long ulX,\r
+ unsigned long ulY,\r
+ unsigned char ucLevel);\r
+extern void OSRAM128x64x4ImageDraw(const unsigned char *pucImage,\r
+ unsigned long ulX,\r
+ unsigned long ulY,\r
+ unsigned long ulWidth,\r
+ unsigned long ulHeight);\r
+extern void OSRAM128x64x4Init(unsigned long ulFrequency);\r
+extern void OSRAM128x64x4Enable(unsigned long ulFrequency);\r
+extern void OSRAM128x64x4Disable(void);\r
+extern void OSRAM128x64x4DisplayOn(void);\r
+extern void OSRAM128x64x4DisplayOff(void);\r
+\r
+//*****************************************************************************\r
+//\r
+// The following macro(s) map old names for the OSRAM functions to the new\r
+// names. In new code, the new names should be used in favor of the old names.\r
+//\r
+//*****************************************************************************\r
+#ifndef DEPRECATED\r
+#define OSRAM128x64x1InitSSI OSRAM128x64x4Enable\r
+#endif\r
+\r
+#endif // __OSRAM128X64X4_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// pwm.h - API function protoypes for Pulse Width Modulation (PWM) ports\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __PWM_H__\r
+#define __PWM_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// The following defines are passed to PWMGenConfigure() as the ulConfig\r
+// parameter and specify the configuration of the PWM generator.\r
+//\r
+//*****************************************************************************\r
+#define PWM_GEN_MODE_DOWN 0x00000000 // Down count mode\r
+#define PWM_GEN_MODE_UP_DOWN 0x00000002 // Up/Down count mode\r
+#define PWM_GEN_MODE_SYNC 0x00000038 // Synchronous updates\r
+#define PWM_GEN_MODE_NO_SYNC 0x00000000 // Immediate updates\r
+#define PWM_GEN_MODE_DBG_RUN 0x00000004 // Continue running in debug mode\r
+#define PWM_GEN_MODE_DBG_STOP 0x00000000 // Stop running in debug mode\r
+\r
+//*****************************************************************************\r
+//\r
+// Defines for enabling, disabling, and clearing PWM generator interrupts and\r
+// triggers.\r
+//\r
+//*****************************************************************************\r
+#define PWM_INT_CNT_ZERO 0x00000001 // Int if COUNT = 0\r
+#define PWM_INT_CNT_LOAD 0x00000002 // Int if COUNT = LOAD\r
+#define PWM_INT_CNT_AU 0x00000004 // Int if COUNT = CMPA U\r
+#define PWM_INT_CNT_AD 0x00000008 // Int if COUNT = CMPA D\r
+#define PWM_INT_CNT_BU 0x00000010 // Int if COUNT = CMPA U\r
+#define PWM_INT_CNT_BD 0x00000020 // Int if COUNT = CMPA D\r
+#define PWM_TR_CNT_ZERO 0x00000100 // Trig if COUNT = 0\r
+#define PWM_TR_CNT_LOAD 0x00000200 // Trig if COUNT = LOAD\r
+#define PWM_TR_CNT_AU 0x00000400 // Trig if COUNT = CMPA U\r
+#define PWM_TR_CNT_AD 0x00000800 // Trig if COUNT = CMPA D\r
+#define PWM_TR_CNT_BU 0x00001000 // Trig if COUNT = CMPA U\r
+#define PWM_TR_CNT_BD 0x00002000 // Trig if COUNT = CMPA D\r
+\r
+//*****************************************************************************\r
+//\r
+// Defines for enabling, disabling, and clearing PWM interrupts.\r
+//\r
+//*****************************************************************************\r
+#define PWM_INT_GEN_0 0x00000001 // Generator 0 interrupt\r
+#define PWM_INT_GEN_1 0x00000002 // Generator 1 interrupt\r
+#define PWM_INT_GEN_2 0x00000004 // Generator 2 interrupt\r
+#define PWM_INT_FAULT 0x00010000 // Fault interrupt\r
+\r
+//*****************************************************************************\r
+//\r
+// Defines to identify the generators within a module.\r
+//\r
+//*****************************************************************************\r
+#define PWM_GEN_0 0x00000040 // Offset address of Gen0\r
+#define PWM_GEN_1 0x00000080 // Offset address of Gen1\r
+#define PWM_GEN_2 0x000000C0 // Offset address of Gen2\r
+\r
+#define PWM_GEN_0_BIT 0x00000001 // Bit-wise ID for Gen0\r
+#define PWM_GEN_1_BIT 0x00000002 // Bit-wise ID for Gen1\r
+#define PWM_GEN_2_BIT 0x00000004 // Bit-wise ID for Gen2\r
+\r
+//*****************************************************************************\r
+//\r
+// Defines to identify the outputs within a module.\r
+//\r
+//*****************************************************************************\r
+#define PWM_OUT_0 0x00000040 // Encoded offset address of PWM0\r
+#define PWM_OUT_1 0x00000041 // Encoded offset address of PWM1\r
+#define PWM_OUT_2 0x00000082 // Encoded offset address of PWM2\r
+#define PWM_OUT_3 0x00000083 // Encoded offset address of PWM3\r
+#define PWM_OUT_4 0x000000C4 // Encoded offset address of PWM4\r
+#define PWM_OUT_5 0x000000C5 // Encoded offset address of PWM5\r
+\r
+#define PWM_OUT_0_BIT 0x00000001 // Bit-wise ID for PWM0\r
+#define PWM_OUT_1_BIT 0x00000002 // Bit-wise ID for PWM1\r
+#define PWM_OUT_2_BIT 0x00000004 // Bit-wise ID for PWM2\r
+#define PWM_OUT_3_BIT 0x00000008 // Bit-wise ID for PWM3\r
+#define PWM_OUT_4_BIT 0x00000010 // Bit-wise ID for PWM4\r
+#define PWM_OUT_5_BIT 0x00000020 // Bit-wise ID for PWM5\r
+\r
+//*****************************************************************************\r
+//\r
+// API Function prototypes\r
+//\r
+//*****************************************************************************\r
+extern void PWMGenConfigure(unsigned long ulBase, unsigned long ulGen,\r
+ unsigned long ulConfig);\r
+extern void PWMGenPeriodSet(unsigned long ulBase, unsigned long ulGen,\r
+ unsigned long ulPeriod);\r
+extern unsigned long PWMGenPeriodGet(unsigned long ulBase,\r
+ unsigned long ulGen);\r
+extern void PWMGenEnable(unsigned long ulBase, unsigned long ulGen);\r
+extern void PWMGenDisable(unsigned long ulBase, unsigned long ulGen);\r
+extern void PWMPulseWidthSet(unsigned long ulBase, unsigned long ulPWMOut,\r
+ unsigned long ulWidth);\r
+extern unsigned long PWMPulseWidthGet(unsigned long ulBase,\r
+ unsigned long ulPWMOut);\r
+extern void PWMDeadBandEnable(unsigned long ulBase, unsigned long ulGen,\r
+ unsigned short usRise, unsigned short usFall);\r
+extern void PWMDeadBandDisable(unsigned long ulBase, unsigned long ulGen);\r
+extern void PWMSyncUpdate(unsigned long ulBase, unsigned long ulGenBits);\r
+extern void PWMSyncTimeBase(unsigned long ulBase, unsigned long ulGenBits);\r
+extern void PWMOutputState(unsigned long ulBase, unsigned long ulPWMOutBits,\r
+ tBoolean bEnable);\r
+extern void PWMOutputInvert(unsigned long ulBase, unsigned long ulPWMOutBits,\r
+ tBoolean bInvert);\r
+extern void PWMOutputFault(unsigned long ulBase, unsigned long ulPWMOutBits,\r
+ tBoolean bFaultKill);\r
+extern void PWMGenIntRegister(unsigned long ulBase, unsigned long ulGen,\r
+ void (*pfnIntHandler)(void));\r
+extern void PWMGenIntUnregister(unsigned long ulBase, unsigned long ulGen);\r
+extern void PWMFaultIntRegister(unsigned long ulBase,\r
+ void (*pfnIntHandler)(void));\r
+extern void PWMFaultIntUnregister(unsigned long ulBase);\r
+extern void PWMGenIntTrigEnable(unsigned long ulBase, unsigned long ulGen,\r
+ unsigned long ulIntTrig);\r
+extern void PWMGenIntTrigDisable(unsigned long ulBase, unsigned long ulGen,\r
+ unsigned long ulIntTrig);\r
+extern unsigned long PWMGenIntStatus(unsigned long ulBase, unsigned long ulGen,\r
+ tBoolean bMasked);\r
+extern void PWMGenIntClear(unsigned long ulBase, unsigned long ulGen,\r
+ unsigned long ulInts);\r
+extern void PWMIntEnable(unsigned long ulBase, unsigned long ulGenFault);\r
+extern void PWMIntDisable(unsigned long ulBase, unsigned long ulGenFault);\r
+extern void PWMFaultIntClear(unsigned long ulBase);\r
+extern unsigned long PWMIntStatus(unsigned long ulBase, tBoolean bMasked);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __PWM_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// qei.h - Prototypes for the Quadrature Encoder Driver.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __QEI_H__\r
+#define __QEI_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to QEIConfigure as the ulConfig paramater.\r
+//\r
+//*****************************************************************************\r
+#define QEI_CONFIG_CAPTURE_A 0x00000000 // Count on ChA edges only\r
+#define QEI_CONFIG_CAPTURE_A_B 0x00000008 // Count on ChA and ChB edges\r
+#define QEI_CONFIG_NO_RESET 0x00000000 // Do not reset on index pulse\r
+#define QEI_CONFIG_RESET_IDX 0x00000010 // Reset position on index pulse\r
+#define QEI_CONFIG_QUADRATURE 0x00000000 // ChA and ChB are quadrature\r
+#define QEI_CONFIG_CLOCK_DIR 0x00000004 // ChA and ChB are clock and dir\r
+#define QEI_CONFIG_NO_SWAP 0x00000000 // Do not swap ChA and ChB\r
+#define QEI_CONFIG_SWAP 0x00000002 // Swap ChA and ChB\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to QEIVelocityConfigure as the ulPreDiv parameter.\r
+//\r
+//*****************************************************************************\r
+#define QEI_VELDIV_1 0x00000000 // Predivide by 1\r
+#define QEI_VELDIV_2 0x00000040 // Predivide by 2\r
+#define QEI_VELDIV_4 0x00000080 // Predivide by 4\r
+#define QEI_VELDIV_8 0x000000C0 // Predivide by 8\r
+#define QEI_VELDIV_16 0x00000100 // Predivide by 16\r
+#define QEI_VELDIV_32 0x00000140 // Predivide by 32\r
+#define QEI_VELDIV_64 0x00000180 // Predivide by 64\r
+#define QEI_VELDIV_128 0x000001C0 // Predivide by 128\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to QEIEnableInts, QEIDisableInts, and QEIClearInts\r
+// as the ulIntFlags parameter, and returned by QEIGetIntStatus.\r
+//\r
+//*****************************************************************************\r
+#define QEI_INTERROR 0x00000008 // Phase error detected\r
+#define QEI_INTDIR 0x00000004 // Direction change\r
+#define QEI_INTTIMER 0x00000002 // Velocity timer expired\r
+#define QEI_INTINDEX 0x00000001 // Index pulse detected\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+extern void QEIEnable(unsigned long ulBase);\r
+extern void QEIDisable(unsigned long ulBase);\r
+extern void QEIConfigure(unsigned long ulBase, unsigned long ulConfig,\r
+ unsigned long ulMaxPosition);\r
+extern unsigned long QEIPositionGet(unsigned long ulBase);\r
+extern void QEIPositionSet(unsigned long ulBase, unsigned long ulPosition);\r
+extern long QEIDirectionGet(unsigned long ulBase);\r
+extern tBoolean QEIErrorGet(unsigned long ulBase);\r
+extern void QEIVelocityEnable(unsigned long ulBase);\r
+extern void QEIVelocityDisable(unsigned long ulBase);\r
+extern void QEIVelocityConfigure(unsigned long ulBase, unsigned long ulPreDiv,\r
+ unsigned long ulPeriod);\r
+extern unsigned long QEIVelocityGet(unsigned long ulBase);\r
+extern void QEIIntRegister(unsigned long ulBase, void (*pfnHandler)(void));\r
+extern void QEIIntUnregister(unsigned long ulBase);\r
+extern void QEIIntEnable(unsigned long ulBase, unsigned long ulIntFlags);\r
+extern void QEIIntDisable(unsigned long ulBase, unsigned long ulIntFlags);\r
+extern unsigned long QEIIntStatus(unsigned long ulBase, tBoolean bMasked);\r
+extern void QEIIntClear(unsigned long ulBase, unsigned long ulIntFlags);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __QEI_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// ssi.h - Prototypes for the Synchronous Serial Interface Driver.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __SSI_H__\r
+#define __SSI_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to SSIIntEnable, SSIIntDisable, and SSIIntClear\r
+// as the ulIntFlags parameter, and returned by SSIIntStatus.\r
+//\r
+//*****************************************************************************\r
+#define SSI_TXFF 0x00000008 // TX FIFO half empty or less\r
+#define SSI_RXFF 0x00000004 // RX FIFO half full or less\r
+#define SSI_RXTO 0x00000002 // RX timeout\r
+#define SSI_RXOR 0x00000001 // RX overrun\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to SSIConfig.\r
+//\r
+//*****************************************************************************\r
+#define SSI_FRF_MOTO_MODE_0 0x00000000 // Moto fmt, polarity 0, phase 0\r
+#define SSI_FRF_MOTO_MODE_1 0x00000002 // Moto fmt, polarity 0, phase 1\r
+#define SSI_FRF_MOTO_MODE_2 0x00000001 // Moto fmt, polarity 1, phase 0\r
+#define SSI_FRF_MOTO_MODE_3 0x00000003 // Moto fmt, polarity 1, phase 1\r
+#define SSI_FRF_TI 0x00000010 // TI frame format\r
+#define SSI_FRF_NMW 0x00000020 // National MicroWire frame format\r
+\r
+#define SSI_MODE_MASTER 0x00000000 // SSI master\r
+#define SSI_MODE_SLAVE 0x00000001 // SSI slave\r
+#define SSI_MODE_SLAVE_OD 0x00000002 // SSI slave with output disabled\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+extern void SSIConfig(unsigned long ulBase, unsigned long ulProtocol,\r
+ unsigned long ulMode, unsigned long ulBitRate,\r
+ unsigned long ulDataWidth);\r
+extern void SSIDataGet(unsigned long ulBase, unsigned long *pulData);\r
+extern long SSIDataNonBlockingGet(unsigned long ulBase,\r
+ unsigned long *pulData);\r
+extern void SSIDataPut(unsigned long ulBase, unsigned long ulData);\r
+extern long SSIDataNonBlockingPut(unsigned long ulBase, unsigned long ulData);\r
+extern void SSIDisable(unsigned long ulBase);\r
+extern void SSIEnable(unsigned long ulBase);\r
+extern void SSIIntClear(unsigned long ulBase, unsigned long ulIntFlags);\r
+extern void SSIIntDisable(unsigned long ulBase, unsigned long ulIntFlags);\r
+extern void SSIIntEnable(unsigned long ulBase, unsigned long ulIntFlags);\r
+extern void SSIIntRegister(unsigned long ulBase, void(*pfnHandler)(void));\r
+extern unsigned long SSIIntStatus(unsigned long ulBase, tBoolean bMasked);\r
+extern void SSIIntUnregister(unsigned long ulBase);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __SSI_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// sysctl.h - Prototypes for the system control driver.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __SYSCTL_H__\r
+#define __SYSCTL_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the\r
+// SysCtlPeripheralPresent(), SysCtlPeripheralEnable(),\r
+// SysCtlPeripheralDisable(), and SysCtlPeripheralReset() APIs as the\r
+// ulPeripheral parameter. The peripherals in the fourth group (upper nibble\r
+// is 3) can only be used with the SysCtlPeripheralPresent() API.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_PERIPH_PWM 0x00100010 // PWM\r
+#define SYSCTL_PERIPH_ADC 0x00100001 // ADC\r
+#define SYSCTL_PERIPH_HIBERNATE 0x00000040 // Hibernation module\r
+#define SYSCTL_PERIPH_WDOG 0x00000008 // Watchdog\r
+#define SYSCTL_PERIPH_CAN0 0x00100100 // CAN 0\r
+#define SYSCTL_PERIPH_CAN1 0x00100200 // CAN 1\r
+#define SYSCTL_PERIPH_UART0 0x10000001 // UART 0\r
+#define SYSCTL_PERIPH_UART1 0x10000002 // UART 1\r
+#define SYSCTL_PERIPH_UART2 0x10000004 // UART 2\r
+#define SYSCTL_PERIPH_SSI 0x10000010 // SSI\r
+#define SYSCTL_PERIPH_SSI0 0x10000010 // SSI 0\r
+#define SYSCTL_PERIPH_SSI1 0x10000020 // SSI 1\r
+#define SYSCTL_PERIPH_QEI 0x10000100 // QEI\r
+#define SYSCTL_PERIPH_QEI0 0x10000100 // QEI 0\r
+#define SYSCTL_PERIPH_QEI1 0x10000200 // QEI 1\r
+#define SYSCTL_PERIPH_I2C 0x10001000 // I2C\r
+#define SYSCTL_PERIPH_I2C0 0x10001000 // I2C 0\r
+#define SYSCTL_PERIPH_I2C1 0x10004000 // I2C 1\r
+#define SYSCTL_PERIPH_TIMER0 0x10100001 // Timer 0\r
+#define SYSCTL_PERIPH_TIMER1 0x10100002 // Timer 1\r
+#define SYSCTL_PERIPH_TIMER2 0x10100004 // Timer 2\r
+#define SYSCTL_PERIPH_TIMER3 0x10100008 // Timer 3\r
+#define SYSCTL_PERIPH_COMP0 0x10100100 // Analog comparator 0\r
+#define SYSCTL_PERIPH_COMP1 0x10100200 // Analog comparator 1\r
+#define SYSCTL_PERIPH_COMP2 0x10100400 // Analog comparator 2\r
+#define SYSCTL_PERIPH_GPIOA 0x20000001 // GPIO A\r
+#define SYSCTL_PERIPH_GPIOB 0x20000002 // GPIO B\r
+#define SYSCTL_PERIPH_GPIOC 0x20000004 // GPIO C\r
+#define SYSCTL_PERIPH_GPIOD 0x20000008 // GPIO D\r
+#define SYSCTL_PERIPH_GPIOE 0x20000010 // GPIO E\r
+#define SYSCTL_PERIPH_GPIOF 0x20000020 // GPIO F\r
+#define SYSCTL_PERIPH_GPIOG 0x20000040 // GPIO G\r
+#define SYSCTL_PERIPH_GPIOH 0x20000080 // GPIO H\r
+#define SYSCTL_PERIPH_ETH 0x20105000 // ETH\r
+#define SYSCTL_PERIPH_MPU 0x30000080 // Cortex M3 MPU\r
+#define SYSCTL_PERIPH_TEMP 0x30000020 // Temperature sensor\r
+#define SYSCTL_PERIPH_PLL 0x30000010 // PLL\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the SysCtlPinPresent() API\r
+// as the ulPin parameter.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_PIN_PWM0 0x00000001 // PWM0 pin\r
+#define SYSCTL_PIN_PWM1 0x00000002 // PWM1 pin\r
+#define SYSCTL_PIN_PWM2 0x00000004 // PWM2 pin\r
+#define SYSCTL_PIN_PWM3 0x00000008 // PWM3 pin\r
+#define SYSCTL_PIN_PWM4 0x00000010 // PWM4 pin\r
+#define SYSCTL_PIN_PWM5 0x00000020 // PWM5 pin\r
+#define SYSCTL_PIN_C0MINUS 0x00000040 // C0- pin\r
+#define SYSCTL_PIN_C0PLUS 0x00000080 // C0+ pin\r
+#define SYSCTL_PIN_C0O 0x00000100 // C0o pin\r
+#define SYSCTL_PIN_C1MINUS 0x00000200 // C1- pin\r
+#define SYSCTL_PIN_C1PLUS 0x00000400 // C1+ pin\r
+#define SYSCTL_PIN_C1O 0x00000800 // C1o pin\r
+#define SYSCTL_PIN_C2MINUS 0x00001000 // C2- pin\r
+#define SYSCTL_PIN_C2PLUS 0x00002000 // C2+ pin\r
+#define SYSCTL_PIN_C2O 0x00004000 // C2o pin\r
+#define SYSCTL_PIN_MC_FAULT0 0x00008000 // MC0 Fault pin\r
+#define SYSCTL_PIN_ADC0 0x00010000 // ADC0 pin\r
+#define SYSCTL_PIN_ADC1 0x00020000 // ADC1 pin\r
+#define SYSCTL_PIN_ADC2 0x00040000 // ADC2 pin\r
+#define SYSCTL_PIN_ADC3 0x00080000 // ADC3 pin\r
+#define SYSCTL_PIN_ADC4 0x00100000 // ADC4 pin\r
+#define SYSCTL_PIN_ADC5 0x00200000 // ADC5 pin\r
+#define SYSCTL_PIN_ADC6 0x00400000 // ADC6 pin\r
+#define SYSCTL_PIN_ADC7 0x00800000 // ADC7 pin\r
+#define SYSCTL_PIN_CCP0 0x01000000 // CCP0 pin\r
+#define SYSCTL_PIN_CCP1 0x02000000 // CCP1 pin\r
+#define SYSCTL_PIN_CCP2 0x04000000 // CCP2 pin\r
+#define SYSCTL_PIN_CCP3 0x08000000 // CCP3 pin\r
+#define SYSCTL_PIN_CCP4 0x10000000 // CCP4 pin\r
+#define SYSCTL_PIN_CCP5 0x20000000 // CCP5 pin\r
+#define SYSCTL_PIN_32KHZ 0x80000000 // 32kHz pin\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the SysCtlLDOSet() API as\r
+// the ulVoltage value, or returned by the SysCtlLDOGet() API.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_LDO_2_25V 0x00000005 // LDO output of 2.25V\r
+#define SYSCTL_LDO_2_30V 0x00000004 // LDO output of 2.30V\r
+#define SYSCTL_LDO_2_35V 0x00000003 // LDO output of 2.35V\r
+#define SYSCTL_LDO_2_40V 0x00000002 // LDO output of 2.40V\r
+#define SYSCTL_LDO_2_45V 0x00000001 // LDO output of 2.45V\r
+#define SYSCTL_LDO_2_50V 0x00000000 // LDO output of 2.50V\r
+#define SYSCTL_LDO_2_55V 0x0000001f // LDO output of 2.55V\r
+#define SYSCTL_LDO_2_60V 0x0000001e // LDO output of 2.60V\r
+#define SYSCTL_LDO_2_65V 0x0000001d // LDO output of 2.65V\r
+#define SYSCTL_LDO_2_70V 0x0000001c // LDO output of 2.70V\r
+#define SYSCTL_LDO_2_75V 0x0000001b // LDO output of 2.75V\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the SysCtlLDOConfigSet() API.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_LDOCFG_ARST 0x00000001 // Allow LDO failure to reset\r
+#define SYSCTL_LDOCFG_NORST 0x00000000 // Do not reset on LDO failure\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the SysCtlIntEnable(),\r
+// SysCtlIntDisable(), and SysCtlIntClear() APIs, or returned in the bit mask\r
+// by the SysCtlIntStatus() API.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_INT_PLL_LOCK 0x00000040 // PLL lock interrupt\r
+#define SYSCTL_INT_CUR_LIMIT 0x00000020 // Current limit interrupt\r
+#define SYSCTL_INT_IOSC_FAIL 0x00000010 // Internal oscillator failure int\r
+#define SYSCTL_INT_MOSC_FAIL 0x00000008 // Main oscillator failure int\r
+#define SYSCTL_INT_POR 0x00000004 // Power on reset interrupt\r
+#define SYSCTL_INT_BOR 0x00000002 // Brown out interrupt\r
+#define SYSCTL_INT_PLL_FAIL 0x00000001 // PLL failure interrupt\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the SysCtlResetCauseClear()\r
+// API or returned by the SysCtlResetCauseGet() API.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_CAUSE_LDO 0x00000020 // LDO power not OK reset\r
+#define SYSCTL_CAUSE_SW 0x00000010 // Software reset\r
+#define SYSCTL_CAUSE_WDOG 0x00000008 // Watchdog reset\r
+#define SYSCTL_CAUSE_BOR 0x00000004 // Brown-out reset\r
+#define SYSCTL_CAUSE_POR 0x00000002 // Power on reset\r
+#define SYSCTL_CAUSE_EXT 0x00000001 // External reset\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the SysCtlBrownOutConfigSet()\r
+// API as the ulConfig parameter.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_BOR_RESET 0x00000002 // Reset instead of interrupting\r
+#define SYSCTL_BOR_RESAMPLE 0x00000001 // Resample BOR before asserting\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the SysCtlPWMClockSet() API\r
+// as the ulConfig parameter, and can be returned by the SysCtlPWMClockGet()\r
+// API.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_PWMDIV_1 0x00000000 // PWM clock is processor clock /1\r
+#define SYSCTL_PWMDIV_2 0x00100000 // PWM clock is processor clock /2\r
+#define SYSCTL_PWMDIV_4 0x00120000 // PWM clock is processor clock /4\r
+#define SYSCTL_PWMDIV_8 0x00140000 // PWM clock is processor clock /8\r
+#define SYSCTL_PWMDIV_16 0x00160000 // PWM clock is processor clock /16\r
+#define SYSCTL_PWMDIV_32 0x00180000 // PWM clock is processor clock /32\r
+#define SYSCTL_PWMDIV_64 0x001A0000 // PWM clock is processor clock /64\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the SysCtlADCSpeedSet() API\r
+// as the ulSpeed parameter, and can be returned by the SyCtlADCSpeedGet()\r
+// API.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_ADCSPEED_1MSPS 0x00000300 // 1,000,000 samples per second\r
+#define SYSCTL_ADCSPEED_500KSPS 0x00000200 // 500,000 samples per second\r
+#define SYSCTL_ADCSPEED_250KSPS 0x00000100 // 250,000 samples per second\r
+#define SYSCTL_ADCSPEED_125KSPS 0x00000000 // 125,000 samples per second\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the SysCtlClockSet() API as\r
+// the ulConfig parameter.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_SYSDIV_1 0x07800000 // Processor clock is osc/pll /1\r
+#define SYSCTL_SYSDIV_2 0x00C00000 // Processor clock is osc/pll /2\r
+#define SYSCTL_SYSDIV_3 0x01400000 // Processor clock is osc/pll /3\r
+#define SYSCTL_SYSDIV_4 0x01C00000 // Processor clock is osc/pll /4\r
+#define SYSCTL_SYSDIV_5 0x02400000 // Processor clock is osc/pll /5\r
+#define SYSCTL_SYSDIV_6 0x02C00000 // Processor clock is osc/pll /6\r
+#define SYSCTL_SYSDIV_7 0x03400000 // Processor clock is osc/pll /7\r
+#define SYSCTL_SYSDIV_8 0x03C00000 // Processor clock is osc/pll /8\r
+#define SYSCTL_SYSDIV_9 0x04400000 // Processor clock is osc/pll /9\r
+#define SYSCTL_SYSDIV_10 0x04C00000 // Processor clock is osc/pll /10\r
+#define SYSCTL_SYSDIV_11 0x05400000 // Processor clock is osc/pll /11\r
+#define SYSCTL_SYSDIV_12 0x05C00000 // Processor clock is osc/pll /12\r
+#define SYSCTL_SYSDIV_13 0x06400000 // Processor clock is osc/pll /13\r
+#define SYSCTL_SYSDIV_14 0x06C00000 // Processor clock is osc/pll /14\r
+#define SYSCTL_SYSDIV_15 0x07400000 // Processor clock is osc/pll /15\r
+#define SYSCTL_SYSDIV_16 0x07C00000 // Processor clock is osc/pll /16\r
+#define SYSCTL_USE_PLL 0x00000000 // System clock is the PLL clock\r
+#define SYSCTL_USE_OSC 0x00003800 // System clock is the osc clock\r
+#define SYSCTL_XTAL_3_57MHZ 0x00000100 // External crystal is 3.579545MHz\r
+#define SYSCTL_XTAL_3_68MHZ 0x00000140 // External crystal is 3.6864MHz\r
+#define SYSCTL_XTAL_4MHZ 0x00000180 // External crystal is 4MHz\r
+#define SYSCTL_XTAL_4_09MHZ 0x000001C0 // External crystal is 4.096MHz\r
+#define SYSCTL_XTAL_4_91MHZ 0x00000200 // External crystal is 4.9152MHz\r
+#define SYSCTL_XTAL_5MHZ 0x00000240 // External crystal is 5MHz\r
+#define SYSCTL_XTAL_5_12MHZ 0x00000280 // External crystal is 5.12MHz\r
+#define SYSCTL_XTAL_6MHZ 0x000002C0 // External crystal is 6MHz\r
+#define SYSCTL_XTAL_6_14MHZ 0x00000300 // External crystal is 6.144MHz\r
+#define SYSCTL_XTAL_7_37MHZ 0x00000340 // External crystal is 7.3728MHz\r
+#define SYSCTL_XTAL_8MHZ 0x00000380 // External crystal is 8MHz\r
+#define SYSCTL_XTAL_8_19MHZ 0x000003C0 // External crystal is 8.192MHz\r
+#define SYSCTL_OSC_MAIN 0x00000000 // Oscillator source is main osc\r
+#define SYSCTL_OSC_INT 0x00000010 // Oscillator source is int. osc\r
+#define SYSCTL_OSC_INT4 0x00000020 // Oscillator source is int. osc /4\r
+#define SYSCTL_INT_OSC_DIS 0x00000002 // Disable internal oscillator\r
+#define SYSCTL_MAIN_OSC_DIS 0x00000001 // Disable main oscillator\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+extern unsigned long SysCtlSRAMSizeGet(void);\r
+extern unsigned long SysCtlFlashSizeGet(void);\r
+extern tBoolean SysCtlPinPresent(unsigned long ulPin);\r
+extern tBoolean SysCtlPeripheralPresent(unsigned long ulPeripheral);\r
+extern void SysCtlPeripheralReset(unsigned long ulPeripheral);\r
+extern void SysCtlPeripheralEnable(unsigned long ulPeripheral);\r
+extern void SysCtlPeripheralDisable(unsigned long ulPeripheral);\r
+extern void SysCtlPeripheralSleepEnable(unsigned long ulPeripheral);\r
+extern void SysCtlPeripheralSleepDisable(unsigned long ulPeripheral);\r
+extern void SysCtlPeripheralDeepSleepEnable(unsigned long ulPeripheral);\r
+extern void SysCtlPeripheralDeepSleepDisable(unsigned long ulPeripheral);\r
+extern void SysCtlPeripheralClockGating(tBoolean bEnable);\r
+extern void SysCtlIntRegister(void (*pfnHandler)(void));\r
+extern void SysCtlIntUnregister(void);\r
+extern void SysCtlIntEnable(unsigned long ulInts);\r
+extern void SysCtlIntDisable(unsigned long ulInts);\r
+extern void SysCtlIntClear(unsigned long ulInts);\r
+extern unsigned long SysCtlIntStatus(tBoolean bMasked);\r
+extern void SysCtlLDOSet(unsigned long ulVoltage);\r
+extern unsigned long SysCtlLDOGet(void);\r
+extern void SysCtlLDOConfigSet(unsigned long ulConfig);\r
+extern void SysCtlReset(void);\r
+extern void SysCtlSleep(void);\r
+extern void SysCtlDeepSleep(void);\r
+extern unsigned long SysCtlResetCauseGet(void);\r
+extern void SysCtlResetCauseClear(unsigned long ulCauses);\r
+extern void SysCtlBrownOutConfigSet(unsigned long ulConfig,\r
+ unsigned long ulDelay);\r
+extern void SysCtlClockSet(unsigned long ulConfig);\r
+extern unsigned long SysCtlClockGet(void);\r
+extern void SysCtlPWMClockSet(unsigned long ulConfig);\r
+extern unsigned long SysCtlPWMClockGet(void);\r
+extern void SysCtlADCSpeedSet(unsigned long ulSpeed);\r
+extern unsigned long SysCtlADCSpeedGet(void);\r
+extern void SysCtlIOSCVerificationSet(tBoolean bEnable);\r
+extern void SysCtlMOSCVerificationSet(tBoolean bEnable);\r
+extern void SysCtlPLLVerificationSet(tBoolean bEnable);\r
+extern void SysCtlClkVerificationClear(void);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __SYSCTL_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// systick.h - Prototypes for the SysTick driver.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __SYSTICK_H__\r
+#define __SYSTICK_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+extern void SysTickEnable(void);\r
+extern void SysTickDisable(void);\r
+extern void SysTickIntRegister(void (*pfnHandler)(void));\r
+extern void SysTickIntUnregister(void);\r
+extern void SysTickIntEnable(void);\r
+extern void SysTickIntDisable(void);\r
+extern void SysTickPeriodSet(unsigned long ulPeriod);\r
+extern unsigned long SysTickPeriodGet(void);\r
+extern unsigned long SysTickValueGet(void);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __SYSTICK_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// uart.h - Defines and Macros for the UART.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __UART_H__\r
+#define __UART_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to UARTIntEnable, UARTIntDisable, and UARTIntClear\r
+// as the ulIntFlags parameter, and returned from UARTIntStatus.\r
+//\r
+//*****************************************************************************\r
+#define UART_INT_OE 0x400 // Overrun Error Interrupt Mask\r
+#define UART_INT_BE 0x200 // Break Error Interrupt Mask\r
+#define UART_INT_PE 0x100 // Parity Error Interrupt Mask\r
+#define UART_INT_FE 0x080 // Framing Error Interrupt Mask\r
+#define UART_INT_RT 0x040 // Receive Timeout Interrupt Mask\r
+#define UART_INT_TX 0x020 // Transmit Interrupt Mask\r
+#define UART_INT_RX 0x010 // Receive Interrupt Mask\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to UARTConfigSet as the ulConfig parameter and\r
+// returned by UARTConfigGet in the pulConfig parameter. Additionally, the\r
+// UART_CONFIG_PAR_* subset can be passed to UARTParityModeSet as the ulParity\r
+// parameter, and are returned by UARTParityModeGet.\r
+//\r
+//*****************************************************************************\r
+#define UART_CONFIG_WLEN_8 0x00000060 // 8 bit data\r
+#define UART_CONFIG_WLEN_7 0x00000040 // 7 bit data\r
+#define UART_CONFIG_WLEN_6 0x00000020 // 6 bit data\r
+#define UART_CONFIG_WLEN_5 0x00000000 // 5 bit data\r
+#define UART_CONFIG_STOP_ONE 0x00000000 // One stop bit\r
+#define UART_CONFIG_STOP_TWO 0x00000008 // Two stop bits\r
+#define UART_CONFIG_PAR_NONE 0x00000000 // No parity\r
+#define UART_CONFIG_PAR_EVEN 0x00000006 // Even parity\r
+#define UART_CONFIG_PAR_ODD 0x00000002 // Odd parity\r
+#define UART_CONFIG_PAR_ONE 0x00000086 // Parity bit is one\r
+#define UART_CONFIG_PAR_ZERO 0x00000082 // Parity bit is zero\r
+\r
+//*****************************************************************************\r
+//\r
+// API Function prototypes\r
+//\r
+//*****************************************************************************\r
+extern void UARTParityModeSet(unsigned long ulBase, unsigned long ulParity);\r
+extern unsigned long UARTParityModeGet(unsigned long ulBase);\r
+extern void UARTConfigSet(unsigned long ulBase, unsigned long ulBaud,\r
+ unsigned long ulConfig);\r
+extern void UARTConfigGet(unsigned long ulBase, unsigned long *pulBaud,\r
+ unsigned long *pulConfig);\r
+extern void UARTEnable(unsigned long ulBase);\r
+extern void UARTDisable(unsigned long ulBase);\r
+extern void UARTEnableSIR(unsigned long ulBase, tBoolean bLowPower);\r
+extern void UARTDisableSIR(unsigned long ulBase);\r
+extern tBoolean UARTCharsAvail(unsigned long ulBase);\r
+extern tBoolean UARTSpaceAvail(unsigned long ulBase);\r
+extern long UARTCharNonBlockingGet(unsigned long ulBase);\r
+extern long UARTCharGet(unsigned long ulBase);\r
+extern tBoolean UARTCharNonBlockingPut(unsigned long ulBase,\r
+ unsigned char ucData);\r
+extern void UARTCharPut(unsigned long ulBase, unsigned char ucData);\r
+extern void UARTBreakCtl(unsigned long ulBase, tBoolean bBreakState);\r
+extern void UARTIntRegister(unsigned long ulBase, void(*pfnHandler)(void));\r
+extern void UARTIntUnregister(unsigned long ulBase);\r
+extern void UARTIntEnable(unsigned long ulBase, unsigned long ulIntFlags);\r
+extern void UARTIntDisable(unsigned long ulBase, unsigned long ulIntFlags);\r
+extern unsigned long UARTIntStatus(unsigned long ulBase, tBoolean bMasked);\r
+extern void UARTIntClear(unsigned long ulBase, unsigned long ulIntFlags);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __UART_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// watchdog.h - Prototypes for the Watchdog Timer API\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __WATCHDOG_H__\r
+#define __WATCHDOG_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+extern tBoolean WatchdogRunning(unsigned long ulBase);\r
+extern void WatchdogEnable(unsigned long ulBase);\r
+extern void WatchdogResetEnable(unsigned long ulBase);\r
+extern void WatchdogResetDisable(unsigned long ulBase);\r
+extern void WatchdogLock(unsigned long ulBase);\r
+extern void WatchdogUnlock(unsigned long ulBase);\r
+extern tBoolean WatchdogLockState(unsigned long ulBase);\r
+extern void WatchdogReloadSet(unsigned long ulBase, unsigned long ulLoadVal);\r
+extern unsigned long WatchdogReloadGet(unsigned long ulBase);\r
+extern unsigned long WatchdogValueGet(unsigned long ulBase);\r
+extern void WatchdogIntRegister(unsigned long ulBase, void(*pfnHandler)(void));\r
+extern void WatchdogIntUnregister(unsigned long ulBase);\r
+extern void WatchdogIntEnable(unsigned long ulBase);\r
+extern unsigned long WatchdogIntStatus(unsigned long ulBase, tBoolean bMasked);\r
+extern void WatchdogIntClear(unsigned long ulBase);\r
+extern void WatchdogStallDisable(unsigned long ulBase);\r
+extern void WatchdogStallDisable(unsigned long ulBase);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __WATCHDOG_H__\r
--- /dev/null
+/*\r
+ FreeRTOS.org V4.3.0 - Copyright (C) 2003-2007 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS.org distribution.\r
+\r
+ FreeRTOS.org is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS.org is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS.org; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS.org, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section\r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license\r
+ and contact details. Please ensure to read the configuration and relevant\r
+ port sections of the online documentation.\r
+\r
+ Also see http://www.SafeRTOS.com for an IEC 61508 compliant version along\r
+ with commercial development and support options.\r
+ ***************************************************************************\r
+*/\r
+\r
+/*-----------------------------------------------------------\r
+ * Simple parallel port IO routines.\r
+ *-----------------------------------------------------------*/\r
+\r
+/*\r
+*/\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/* Demo includes. */\r
+#include "partest.h"\r
+\r
+/* Library includes. */\r
+#include "hw_types.h"\r
+#include "gpio.h"\r
+#include "hw_memmap.h"\r
+\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestInitialise( void )\r
+{\r
+ GPIODirModeSet( GPIO_PORTF_BASE, GPIO_PIN_0, GPIO_DIR_MODE_OUT );\r
+ GPIOPadConfigSet( GPIO_PORTF_BASE, GPIO_PIN_0, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD );\r
+ GPIOPinWrite( GPIO_PORTF_BASE, GPIO_PIN_0, 0 );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue )\r
+{\r
+ /* There is only one LED. */\r
+ ( void ) uxLED;\r
+ \r
+ GPIOPinWrite( GPIO_PORTF_BASE, GPIO_PIN_0, xValue );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+unsigned portBASE_TYPE uxParTestGetLED( unsigned portBASE_TYPE uxLED )\r
+{\r
+ /* There is only one LED. */\r
+ ( void ) uxLED;\r
+\r
+ return GPIOPinRead( GPIO_PORTF_BASE, GPIO_PIN_0 ); \r
+}\r
+\r
+\r
--- /dev/null
+<?xml version="1.0" encoding="iso-8859-1"?>\r
+\r
+<project>\r
+ <fileVersion>2</fileVersion>\r
+ <configuration>\r
+ <name>Debug</name>\r
+ <outputs>\r
+ <file>$TOOLKIT_DIR$\inc\stddef.h</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\flash.pbi</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\uIP_Task.pbi</file>\r
+ <file>$PROJ_DIR$\..\..\Source\include\projdefs.h</file>\r
+ <file>$PROJ_DIR$\..\..\Source\include\queue.h</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\blocktim.r79</file>\r
+ <file>$TOOLKIT_DIR$\inc\stdlib.h</file>\r
+ <file>$TOOLKIT_DIR$\lib\dl7mptnnl8n.h</file>\r
+ <file>$PROJ_DIR$\..\Common\include\blocktim.h</file>\r
+ <file>$PROJ_DIR$\..\Common\include\death.h</file>\r
+ <file>$PROJ_DIR$\webserver\httpd-fsdata.h</file>\r
+ <file>$TOOLKIT_DIR$\lib\dl7mptnnl8n.r79</file>\r
+ <file>$PROJ_DIR$\..\Common\ethernet\uIP\uip-1.0\uip\psock.h</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\httpd-cgi.r79</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\emac.r79</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\uip_arp.pbi</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\tasks.pbi</file>\r
+ <file>$PROJ_DIR$\..\..\Source\include\portable.h</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\portasm.r79</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\osram128x64x4.pbi</file>\r
+ <file>$PROJ_DIR$\webserver\httpd-fsdata.c</file>\r
+ <file>$TOOLKIT_DIR$\inc\ysizet.h</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\list.r79</file>\r
+ <file>$PROJ_DIR$\LuminaryDrivers\hw_types.h</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\BlockQ.pbi</file>\r
+ <file>$TOOLKIT_DIR$\inc\stdint.h</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\uip.r79</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\main.pbi</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\pdc.r79</file>\r
+ <file>$TOOLKIT_DIR$\inc\xencoding_limits.h</file>\r
+ <file>$PROJ_DIR$\LuminaryDrivers\pdc.c</file>\r
+ <file>$PROJ_DIR$\LuminaryDrivers\interrupt.h</file>\r
+ <file>$PROJ_DIR$\..\Common\include\BlockQ.h</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\timer.pbi</file>\r
+ <file>$PROJ_DIR$\..\Common\ethernet\uIP\uip-1.0\uip\uipopt.h</file>\r
+ <file>$PROJ_DIR$\LuminaryDrivers\hw_ints.h</file>\r
+ <file>$TOOLKIT_DIR$\inc\DLib_Defaults.h</file>\r
+ <file>$PROJ_DIR$\LuminaryDrivers\hw_memmap.h</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\main.r79</file>\r
+ <file>$PROJ_DIR$\bitmap.h</file>\r
+ <file>$PROJ_DIR$\timertest.c</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\timertest.pbi</file>\r
+ <file>$PROJ_DIR$\webserver\webserver.h</file>\r
+ <file>$PROJ_DIR$\..\Common\Minimal\semtest.c</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\PollQ.pbi</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\blocktim.pbi</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\timer.r79</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\semtest.r79</file>\r
+ <file>$PROJ_DIR$\LuminaryDrivers\gpio.h</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\startup_ewarm.pbi</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\timertest.r79</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\uip.pbi</file>\r
+ <file>$PROJ_DIR$\..\Common\ethernet\uIP\uip-1.0\uip\uip_arch.h</file>\r
+ <file>$PROJ_DIR$\lcd_message.h</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\httpd-cgi.pbi</file>\r
+ <file>$PROJ_DIR$\webserver\httpd-fs.h</file>\r
+ <file>$PROJ_DIR$\..\Common\ethernet\uIP\uip-1.0\uip\uip_arp.h</file>\r
+ <file>$TOOLKIT_DIR$\inc\yvals.h</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\BlockQ.r79</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\pdc.pbi</file>\r
+ <file>$PROJ_DIR$\..\Common\Minimal\death.c</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\integer.r79</file>\r
+ <file>$PROJ_DIR$\Debug\Exe\RTOSDemo.d79</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\ParTest.r79</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\http-strings.pbi</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\PollQ.r79</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\httpd.pbi</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\startup_ewarm.r79</file>\r
+ <file>$PROJ_DIR$\LuminaryDrivers\ssi.h</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\flash.r79</file>\r
+ <file>$PROJ_DIR$\LuminaryDrivers\sysctl.h</file>\r
+ <file>$PROJ_DIR$\..\Common\ethernet\uIP\uip-1.0\uip\lc.h</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\tasks.r79</file>\r
+ <file>$PROJ_DIR$\..\Common\include\integer.h</file>\r
+ <file>$PROJ_DIR$\webserver\http-strings.h</file>\r
+ <file>$PROJ_DIR$\LuminaryDrivers\osram128x64x4.h</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\uIP_Task.r79</file>\r
+ <file>$PROJ_DIR$\..\Common\Minimal\BlockQ.c</file>\r
+ <file>$PROJ_DIR$\..\..\..\..\..\Demo\CORTEX_LM3S6965_IAR\main.c</file>\r
+ <file>$PROJ_DIR$\..\Common\Minimal\integer.c</file>\r
+ <file>$PROJ_DIR$\..\Common\Minimal\flash.c</file>\r
+ <file>$PROJ_DIR$\..\Common\Minimal\PollQ.c</file>\r
+ <file>$PROJ_DIR$\ParTest\ParTest.c</file>\r
+ <file>$PROJ_DIR$\main.c</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\uip_arp.r79</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\port.pbi</file>\r
+ <file>$PROJ_DIR$\LuminaryDrivers\hw_sysctl.h</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\httpd-fs.pbi</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\heap_2.pbi</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\osram128x64x4.r79</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\queue.pbi</file>\r
+ <file>$PROJ_DIR$\LuminaryDrivers\hw_ssi.h</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\httpd.r79</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\death.r79</file>\r
+ <file>$PROJ_DIR$\webserver\clock-arch.h</file>\r
+ <file>$PROJ_DIR$\..\Common\ethernet\uIP\uip-1.0\uip\lc-switch.h</file>\r
+ <file>$PROJ_DIR$\FreeRTOSConfig.h</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\semtest.pbi</file>\r
+ <file>$PROJ_DIR$\webserver\uip-conf.h</file>\r
+ <file>$PROJ_DIR$\..\Common\ethernet\uIP\uip-1.0\uip\uip.h</file>\r
+ <file>$PROJ_DIR$\webserver\httpd-cgi.h</file>\r
+ <file>$PROJ_DIR$\..\..\Source\portable\IAR\ARM_CM3\portmacro.h</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\death.pbi</file>\r
+ <file>$PROJ_DIR$\..\..\Source\include\task.h</file>\r
+ <file>$PROJ_DIR$\..\Common\ethernet\uIP\uip-1.0\uip\clock.h</file>\r
+ <file>$PROJ_DIR$\..\..\Source\include\semphr.h</file>\r
+ <file>$PROJ_DIR$\..\Common\include\PollQ.h</file>\r
+ <file>$PROJ_DIR$\..\Common\ethernet\uIP\uip-1.0\uip\uip.c</file>\r
+ <file>$PROJ_DIR$\webserver\httpd-cgi.c</file>\r
+ <file>$PROJ_DIR$\LuminaryDrivers\pdc.h</file>\r
+ <file>$PROJ_DIR$\LuminaryDrivers\driverlib.r79</file>\r
+ <file>$PROJ_DIR$\..\..\Source\include\croutine.h</file>\r
+ <file>$TOOLKIT_DIR$\inc\stdio.h</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\RTOSDemo.pbd</file>\r
+ <file>$PROJ_DIR$\..\Common\include\partest.h</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\psock.pbi</file>\r
+ <file>$PROJ_DIR$\..\..\Source\tasks.c</file>\r
+ <file>$PROJ_DIR$\startup_ewarm.c</file>\r
+ <file>$PROJ_DIR$\LuminaryDrivers\ethernet.h</file>\r
+ <file>$PROJ_DIR$\..\Common\include\flash.h</file>\r
+ <file>$PROJ_DIR$\LuminaryDrivers\hw_ethernet.h</file>\r
+ <file>$PROJ_DIR$\Debug\Exe\RTOSDemo.sim</file>\r
+ <file>$PROJ_DIR$\..\Common\ethernet\uIP\uip-1.0\uip\pt.h</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\psock.r79</file>\r
+ <file>$PROJ_DIR$\..\Common\ethernet\uIP\uip-1.0\uip\timer.h</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\list.pbi</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\httpd-fs.r79</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\ParTest.pbi</file>\r
+ <file>$PROJ_DIR$\..\Common\Minimal\blocktim.c</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\http-strings.r79</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\integer.pbi</file>\r
+ <file>$PROJ_DIR$\webserver\httpd.h</file>\r
+ <file>$TOOLKIT_DIR$\inc\DLib_Product.h</file>\r
+ <file>$PROJ_DIR$\LuminaryDrivers\LMI_timer.h</file>\r
+ <file>$PROJ_DIR$\LuminaryDrivers\debug.h</file>\r
+ <file>$TOOLKIT_DIR$\inc\string.h</file>\r
+ <file>$PROJ_DIR$\RTOSDemo.xcl</file>\r
+ <file>$TOOLKIT_DIR$\inc\DLib_Threads.h</file>\r
+ <file>$PROJ_DIR$\..\..\Source\queue.c</file>\r
+ <file>$PROJ_DIR$\..\..\Source\include\list.h</file>\r
+ <file>$PROJ_DIR$\..\..\Source\portable\IAR\ARM_CM3\portasm.s</file>\r
+ <file>$PROJ_DIR$\webserver\emac.c</file>\r
+ <file>$PROJ_DIR$\..\..\Source\portable\MemMang\heap_2.c</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\queue.r79</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\port.r79</file>\r
+ <file>$PROJ_DIR$\..\..\Source\list.c</file>\r
+ <file>$PROJ_DIR$\..\..\Source\portable\IAR\ARM_CM3\port.c</file>\r
+ <file>$PROJ_DIR$\LuminaryDrivers\osram128x64x4.c</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\emac.pbi</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\heap_2.r79</file>\r
+ <file>$PROJ_DIR$\..\..\Source\include\FreeRTOS.h</file>\r
+ <file>$PROJ_DIR$\..\Common\ethernet\uIP\uip-1.0\uip\uip_arp.c</file>\r
+ <file>$PROJ_DIR$\..\Common\ethernet\uIP\uip-1.0\uip\psock.c</file>\r
+ <file>$PROJ_DIR$\webserver\httpd-fs.c</file>\r
+ <file>$PROJ_DIR$\webserver\uIP_Task.c</file>\r
+ <file>$PROJ_DIR$\webserver\httpd.c</file>\r
+ <file>$PROJ_DIR$\..\Common\ethernet\uIP\uip-1.0\uip\timer.c</file>\r
+ <file>$PROJ_DIR$\webserver\http-strings.c</file>\r
+ <file>$PROJ_DIR$\webserver\emac.h</file>\r
+ <file>$PROJ_DIR$\..\Common\include\semtest.h</file>\r
+ </outputs>\r
+ <file>\r
+ <name>$PROJ_DIR$\LuminaryDrivers\pdc.c</name>\r
+ <outputs>\r
+ <tool>\r
+ <name>ICCARM</name>\r
+ <file> 28</file>\r
+ </tool>\r
+ <tool>\r
+ <name>BICOMP</name>\r
+ <file> 59</file>\r
+ </tool>\r
+ </outputs>\r
+ <inputs>\r
+ <tool>\r
+ <name>ICCARM</name>\r
+ <file> 37 23 134 48 68 70 109</file>\r
+ </tool>\r
+ <tool>\r
+ <name>BICOMP</name>\r
+ <file> 37 23 134 48 68 70 109</file>\r
+ </tool>\r
+ </inputs>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\timertest.c</name>\r
+ <outputs>\r
+ <tool>\r
+ <name>ICCARM</name>\r
+ <file> 50</file>\r
+ </tool>\r
+ <tool>\r
+ <name>BICOMP</name>\r
+ <file> 41</file>\r
+ </tool>\r
+ </outputs>\r
+ <inputs>\r
+ <tool>\r
+ <name>ICCARM</name>\r
+ <file> 150 0 57 36 7 132 29 137 21 3 96 17 101 35 37 23 31 70 133</file>\r
+ </tool>\r
+ <tool>\r
+ <name>BICOMP</name>\r
+ <file> 150 0 57 36 132 29 137 21 3 96 17 101 35 37 23 31 70 133</file>\r
+ </tool>\r
+ </inputs>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\Common\Minimal\semtest.c</name>\r
+ <outputs>\r
+ <tool>\r
+ <name>ICCARM</name>\r
+ <file> 47</file>\r
+ </tool>\r
+ <tool>\r
+ <name>BICOMP</name>\r
+ <file> 97</file>\r
+ </tool>\r
+ </outputs>\r
+ <inputs>\r
+ <tool>\r
+ <name>ICCARM</name>\r
+ <file> 6 57 36 7 132 29 137 21 150 0 3 96 17 101 103 139 105 4 159</file>\r
+ </tool>\r
+ <tool>\r
+ <name>BICOMP</name>\r
+ <file> 6 57 36 132 29 137 21 150 0 3 96 17 101 103 139 105 4 159</file>\r
+ </tool>\r
+ </inputs>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\Common\Minimal\death.c</name>\r
+ <outputs>\r
+ <tool>\r
+ <name>ICCARM</name>\r
+ <file> 93</file>\r
+ </tool>\r
+ <tool>\r
+ <name>BICOMP</name>\r
+ <file> 102</file>\r
+ </tool>\r
+ </outputs>\r
+ <inputs>\r
+ <tool>\r
+ <name>ICCARM</name>\r
+ <file> 6 57 36 7 132 29 137 21 150 0 3 96 17 101 103 139 9</file>\r
+ </tool>\r
+ <tool>\r
+ <name>BICOMP</name>\r
+ <file> 6 57 36 132 29 137 21 150 0 3 96 17 101 103 139 9</file>\r
+ </tool>\r
+ </inputs>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\Debug\Exe\RTOSDemo.d79</name>\r
+ <outputs>\r
+ <tool>\r
+ <name>XLINK</name>\r
+ <file> 121</file>\r
+ </tool>\r
+ </outputs>\r
+ <inputs>\r
+ <tool>\r
+ <name>XLINK</name>\r
+ <file> 136 58 63 65 5 93 14 69 149 129 13 126 92 61 22 38 89 144 18 123 143 47 67 72 46 50 76 26 84 110 11</file>\r
+ </tool>\r
+ </inputs>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\Common\Minimal\BlockQ.c</name>\r
+ <outputs>\r
+ <tool>\r
+ <name>ICCARM</name>\r
+ <file> 58</file>\r
+ </tool>\r
+ <tool>\r
+ <name>BICOMP</name>\r
+ <file> 24</file>\r
+ </tool>\r
+ </outputs>\r
+ <inputs>\r
+ <tool>\r
+ <name>ICCARM</name>\r
+ <file> 6 57 36 7 132 29 137 21 150 0 3 96 17 101 103 139 4 32</file>\r
+ </tool>\r
+ <tool>\r
+ <name>BICOMP</name>\r
+ <file> 6 57 36 132 29 137 21 150 0 3 96 17 101 103 139 4 32</file>\r
+ </tool>\r
+ </inputs>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\Common\Minimal\integer.c</name>\r
+ <outputs>\r
+ <tool>\r
+ <name>ICCARM</name>\r
+ <file> 61</file>\r
+ </tool>\r
+ <tool>\r
+ <name>BICOMP</name>\r
+ <file> 130</file>\r
+ </tool>\r
+ </outputs>\r
+ <inputs>\r
+ <tool>\r
+ <name>ICCARM</name>\r
+ <file> 6 57 36 7 132 29 137 21 150 0 3 96 17 101 103 139 73</file>\r
+ </tool>\r
+ <tool>\r
+ <name>BICOMP</name>\r
+ <file> 6 57 36 132 29 137 21 150 0 3 96 17 101 103 139 73</file>\r
+ </tool>\r
+ </inputs>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\Common\Minimal\flash.c</name>\r
+ <outputs>\r
+ <tool>\r
+ <name>ICCARM</name>\r
+ <file> 69</file>\r
+ </tool>\r
+ <tool>\r
+ <name>BICOMP</name>\r
+ <file> 1</file>\r
+ </tool>\r
+ </outputs>\r
+ <inputs>\r
+ <tool>\r
+ <name>ICCARM</name>\r
+ <file> 6 57 36 7 132 29 137 21 150 0 3 96 17 101 103 139 114 119</file>\r
+ </tool>\r
+ <tool>\r
+ <name>BICOMP</name>\r
+ <file> 6 57 36 132 29 137 21 150 0 3 96 17 101 103 139 114 119</file>\r
+ </tool>\r
+ </inputs>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\Common\Minimal\PollQ.c</name>\r
+ <outputs>\r
+ <tool>\r
+ <name>ICCARM</name>\r
+ <file> 65</file>\r
+ </tool>\r
+ <tool>\r
+ <name>BICOMP</name>\r
+ <file> 44</file>\r
+ </tool>\r
+ </outputs>\r
+ <inputs>\r
+ <tool>\r
+ <name>ICCARM</name>\r
+ <file> 6 57 36 7 132 29 137 21 150 0 3 96 17 101 103 139 4 106</file>\r
+ </tool>\r
+ <tool>\r
+ <name>BICOMP</name>\r
+ <file> 6 57 36 132 29 137 21 150 0 3 96 17 101 103 139 4 106</file>\r
+ </tool>\r
+ </inputs>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\ParTest\ParTest.c</name>\r
+ <outputs>\r
+ <tool>\r
+ <name>ICCARM</name>\r
+ <file> 63</file>\r
+ </tool>\r
+ <tool>\r
+ <name>BICOMP</name>\r
+ <file> 127</file>\r
+ </tool>\r
+ </outputs>\r
+ <inputs>\r
+ <tool>\r
+ <name>ICCARM</name>\r
+ <file> 150 0 57 36 7 132 29 137 21 3 96 17 101 103 139 114 23 48 37</file>\r
+ </tool>\r
+ <tool>\r
+ <name>BICOMP</name>\r
+ <file> 150 0 57 36 132 29 137 21 3 96 17 101 103 139 114 23 48 37</file>\r
+ </tool>\r
+ </inputs>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\main.c</name>\r
+ <outputs>\r
+ <tool>\r
+ <name>ICCARM</name>\r
+ <file> 38</file>\r
+ </tool>\r
+ <tool>\r
+ <name>BICOMP</name>\r
+ <file> 27</file>\r
+ </tool>\r
+ </outputs>\r
+ <inputs>\r
+ <tool>\r
+ <name>ICCARM</name>\r
+ <file> 112 57 36 7 132 29 137 21 150 0 3 96 17 101 103 139 4 105 32 9 73 8 119 114 159 106 53 39 37 23 70 48 75</file>\r
+ </tool>\r
+ <tool>\r
+ <name>BICOMP</name>\r
+ <file> 112 57 36 132 29 137 21 150 0 3 96 17 101 103 139 4 105 32 9 73 8 119 114 159 106 53 39 37 23 70 48 75</file>\r
+ </tool>\r
+ </inputs>\r
+ </file>\r
+ <file>\r
+ <name>[ROOT_NODE]</name>\r
+ <outputs>\r
+ <tool>\r
+ <name>XLINK</name>\r
+ <file> 121 62</file>\r
+ </tool>\r
+ </outputs>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\Common\ethernet\uIP\uip-1.0\uip\uip.c</name>\r
+ <outputs>\r
+ <tool>\r
+ <name>ICCARM</name>\r
+ <file> 26</file>\r
+ </tool>\r
+ <tool>\r
+ <name>BICOMP</name>\r
+ <file> 51</file>\r
+ </tool>\r
+ </outputs>\r
+ <inputs>\r
+ <tool>\r
+ <name>ICCARM</name>\r
+ <file> 99 34 98 25 57 36 7 132 29 137 42 131 12 122 71 95 55 52 135 21</file>\r
+ </tool>\r
+ <tool>\r
+ <name>BICOMP</name>\r
+ <file> 99 34 98 25 57 36 132 29 137 42 131 12 122 71 95 55 52 135 21</file>\r
+ </tool>\r
+ </inputs>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\webserver\httpd-cgi.c</name>\r
+ <outputs>\r
+ <tool>\r
+ <name>ICCARM</name>\r
+ <file> 13</file>\r
+ </tool>\r
+ <tool>\r
+ <name>BICOMP</name>\r
+ <file> 54</file>\r
+ </tool>\r
+ </outputs>\r
+ <inputs>\r
+ <tool>\r
+ <name>ICCARM</name>\r
+ <file> 99 34 98 25 57 36 7 132 29 137 42 131 12 122 71 95 55 100 112 21 135</file>\r
+ </tool>\r
+ <tool>\r
+ <name>BICOMP</name>\r
+ <file> 99 34 98 25 57 36 132 29 137 42 131 12 122 71 95 55 100 112 21 135</file>\r
+ </tool>\r
+ </inputs>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\Debug\Obj\RTOSDemo.pbd</name>\r
+ <inputs>\r
+ <tool>\r
+ <name>BILINK</name>\r
+ <file> 24 127 44 45 102 1 88 130 125 27 19 85 90 97 49 16 41</file>\r
+ </tool>\r
+ </inputs>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Source\tasks.c</name>\r
+ <outputs>\r
+ <tool>\r
+ <name>ICCARM</name>\r
+ <file> 72</file>\r
+ </tool>\r
+ <tool>\r
+ <name>BICOMP</name>\r
+ <file> 16</file>\r
+ </tool>\r
+ </outputs>\r
+ <inputs>\r
+ <tool>\r
+ <name>ICCARM</name>\r
+ <file> 112 57 36 7 132 29 137 21 6 135 150 0 3 96 17 101 103 139</file>\r
+ </tool>\r
+ <tool>\r
+ <name>BICOMP</name>\r
+ <file> 112 57 36 132 29 137 21 6 135 150 0 3 96 17 101 103 139</file>\r
+ </tool>\r
+ </inputs>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\startup_ewarm.c</name>\r
+ <outputs>\r
+ <tool>\r
+ <name>ICCARM</name>\r
+ <file> 67</file>\r
+ </tool>\r
+ <tool>\r
+ <name>BICOMP</name>\r
+ <file> 49</file>\r
+ </tool>\r
+ </outputs>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\Common\Minimal\blocktim.c</name>\r
+ <outputs>\r
+ <tool>\r
+ <name>ICCARM</name>\r
+ <file> 5</file>\r
+ </tool>\r
+ <tool>\r
+ <name>BICOMP</name>\r
+ <file> 45</file>\r
+ </tool>\r
+ </outputs>\r
+ <inputs>\r
+ <tool>\r
+ <name>ICCARM</name>\r
+ <file> 150 0 57 36 7 132 29 137 21 3 96 17 101 103 139 4</file>\r
+ </tool>\r
+ <tool>\r
+ <name>BICOMP</name>\r
+ <file> 150 0 57 36 132 29 137 21 3 96 17 101 103 139 4</file>\r
+ </tool>\r
+ </inputs>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Source\queue.c</name>\r
+ <outputs>\r
+ <tool>\r
+ <name>ICCARM</name>\r
+ <file> 143</file>\r
+ </tool>\r
+ <tool>\r
+ <name>BICOMP</name>\r
+ <file> 90</file>\r
+ </tool>\r
+ </outputs>\r
+ <inputs>\r
+ <tool>\r
+ <name>ICCARM</name>\r
+ <file> 6 57 36 7 132 29 137 21 135 150 0 3 96 17 101 103 139 111</file>\r
+ </tool>\r
+ <tool>\r
+ <name>BICOMP</name>\r
+ <file> 6 57 36 132 29 137 21 135 150 0 3 96 17 101 103 139 111</file>\r
+ </tool>\r
+ </inputs>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Source\portable\IAR\ARM_CM3\portasm.s</name>\r
+ <outputs>\r
+ <tool>\r
+ <name>AARM</name>\r
+ <file> 18</file>\r
+ </tool>\r
+ </outputs>\r
+ <inputs>\r
+ <tool>\r
+ <name>AARM</name>\r
+ <file> 96</file>\r
+ </tool>\r
+ </inputs>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\webserver\emac.c</name>\r
+ <outputs>\r
+ <tool>\r
+ <name>ICCARM</name>\r
+ <file> 14</file>\r
+ </tool>\r
+ <tool>\r
+ <name>BICOMP</name>\r
+ <file> 148</file>\r
+ </tool>\r
+ </outputs>\r
+ <inputs>\r
+ <tool>\r
+ <name>ICCARM</name>\r
+ <file> 150 0 57 36 7 132 29 137 21 3 96 17 101 105 4 103 139 158 99 34 98 25 42 131 12 122 71 95 55 23 37 35 120 118 31</file>\r
+ </tool>\r
+ <tool>\r
+ <name>BICOMP</name>\r
+ <file> 150 0 57 36 132 29 137 21 3 96 17 101 105 4 103 139 158 99 34 98 25 42 131 12 122 71 95 55 23 37 35 120 118 31</file>\r
+ </tool>\r
+ </inputs>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Source\portable\MemMang\heap_2.c</name>\r
+ <outputs>\r
+ <tool>\r
+ <name>ICCARM</name>\r
+ <file> 149</file>\r
+ </tool>\r
+ <tool>\r
+ <name>BICOMP</name>\r
+ <file> 88</file>\r
+ </tool>\r
+ </outputs>\r
+ <inputs>\r
+ <tool>\r
+ <name>ICCARM</name>\r
+ <file> 6 57 36 7 132 29 137 21 150 0 3 96 17 101 103 139</file>\r
+ </tool>\r
+ <tool>\r
+ <name>BICOMP</name>\r
+ <file> 6 57 36 132 29 137 21 150 0 3 96 17 101 103 139</file>\r
+ </tool>\r
+ </inputs>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Source\list.c</name>\r
+ <outputs>\r
+ <tool>\r
+ <name>ICCARM</name>\r
+ <file> 22</file>\r
+ </tool>\r
+ <tool>\r
+ <name>BICOMP</name>\r
+ <file> 125</file>\r
+ </tool>\r
+ </outputs>\r
+ <inputs>\r
+ <tool>\r
+ <name>ICCARM</name>\r
+ <file> 6 57 36 7 132 29 137 21 150 0 3 96 17 101 139</file>\r
+ </tool>\r
+ <tool>\r
+ <name>BICOMP</name>\r
+ <file> 6 57 36 132 29 137 21 150 0 3 96 17 101 139</file>\r
+ </tool>\r
+ </inputs>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Source\portable\IAR\ARM_CM3\port.c</name>\r
+ <outputs>\r
+ <tool>\r
+ <name>ICCARM</name>\r
+ <file> 144</file>\r
+ </tool>\r
+ <tool>\r
+ <name>BICOMP</name>\r
+ <file> 85</file>\r
+ </tool>\r
+ </outputs>\r
+ <inputs>\r
+ <tool>\r
+ <name>ICCARM</name>\r
+ <file> 150 0 57 36 7 132 29 137 21 3 96 17 101 103 139</file>\r
+ </tool>\r
+ <tool>\r
+ <name>BICOMP</name>\r
+ <file> 150 0 57 36 132 29 137 21 3 96 17 101 103 139</file>\r
+ </tool>\r
+ </inputs>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\LuminaryDrivers\osram128x64x4.c</name>\r
+ <outputs>\r
+ <tool>\r
+ <name>ICCARM</name>\r
+ <file> 89</file>\r
+ </tool>\r
+ <tool>\r
+ <name>BICOMP</name>\r
+ <file> 19</file>\r
+ </tool>\r
+ </outputs>\r
+ <inputs>\r
+ <tool>\r
+ <name>ICCARM</name>\r
+ <file> 91 37 86 23 134 48 68 70 75</file>\r
+ </tool>\r
+ <tool>\r
+ <name>BICOMP</name>\r
+ <file> 91 37 86 23 134 48 68 70 75</file>\r
+ </tool>\r
+ </inputs>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\Common\ethernet\uIP\uip-1.0\uip\uip_arp.c</name>\r
+ <outputs>\r
+ <tool>\r
+ <name>ICCARM</name>\r
+ <file> 84</file>\r
+ </tool>\r
+ <tool>\r
+ <name>BICOMP</name>\r
+ <file> 15</file>\r
+ </tool>\r
+ </outputs>\r
+ <inputs>\r
+ <tool>\r
+ <name>ICCARM</name>\r
+ <file> 56 99 34 98 25 57 36 7 132 29 137 42 131 12 122 71 95 55 135 21</file>\r
+ </tool>\r
+ <tool>\r
+ <name>BICOMP</name>\r
+ <file> 56 99 34 98 25 57 36 132 29 137 42 131 12 122 71 95 55 135 21</file>\r
+ </tool>\r
+ </inputs>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\Common\ethernet\uIP\uip-1.0\uip\psock.c</name>\r
+ <outputs>\r
+ <tool>\r
+ <name>ICCARM</name>\r
+ <file> 123</file>\r
+ </tool>\r
+ <tool>\r
+ <name>BICOMP</name>\r
+ <file> 115</file>\r
+ </tool>\r
+ </outputs>\r
+ <inputs>\r
+ <tool>\r
+ <name>ICCARM</name>\r
+ <file> 112 57 36 7 132 29 137 21 135 34 98 25 42 131 12 122 71 95 55 99</file>\r
+ </tool>\r
+ <tool>\r
+ <name>BICOMP</name>\r
+ <file> 112 57 36 132 29 137 21 135 34 98 25 42 131 12 122 71 95 55 99</file>\r
+ </tool>\r
+ </inputs>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\webserver\httpd-fs.c</name>\r
+ <outputs>\r
+ <tool>\r
+ <name>ICCARM</name>\r
+ <file> 126</file>\r
+ </tool>\r
+ <tool>\r
+ <name>BICOMP</name>\r
+ <file> 87</file>\r
+ </tool>\r
+ </outputs>\r
+ <inputs>\r
+ <tool>\r
+ <name>ICCARM</name>\r
+ <file> 131 12 34 98 25 57 36 7 132 29 137 42 122 71 95 55 10 99 20</file>\r
+ </tool>\r
+ <tool>\r
+ <name>BICOMP</name>\r
+ <file> 131 12 34 98 25 57 36 132 29 137 42 122 71 95 55 10 99 20</file>\r
+ </tool>\r
+ </inputs>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\webserver\uIP_Task.c</name>\r
+ <outputs>\r
+ <tool>\r
+ <name>ICCARM</name>\r
+ <file> 76</file>\r
+ </tool>\r
+ <tool>\r
+ <name>BICOMP</name>\r
+ <file> 2</file>\r
+ </tool>\r
+ </outputs>\r
+ <inputs>\r
+ <tool>\r
+ <name>ICCARM</name>\r
+ <file> 135 57 36 7 132 29 137 21 150 0 3 96 17 101 103 139 105 4 53 23 99 34 98 25 42 131 12 122 71 95 55 56 124 104 94 120 118 37 158 114</file>\r
+ </tool>\r
+ <tool>\r
+ <name>BICOMP</name>\r
+ <file> 135 57 36 132 29 137 21 150 0 3 96 17 101 103 139 105 4 53 23 99 34 98 25 42 131 12 122 71 95 55 56 124 104 94 120 118 37 158 114</file>\r
+ </tool>\r
+ </inputs>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\webserver\httpd.c</name>\r
+ <outputs>\r
+ <tool>\r
+ <name>ICCARM</name>\r
+ <file> 92</file>\r
+ </tool>\r
+ <tool>\r
+ <name>BICOMP</name>\r
+ <file> 66</file>\r
+ </tool>\r
+ </outputs>\r
+ <inputs>\r
+ <tool>\r
+ <name>ICCARM</name>\r
+ <file> 99 34 98 25 57 36 7 132 29 137 42 131 12 122 71 95 55 100 74 135 21</file>\r
+ </tool>\r
+ <tool>\r
+ <name>BICOMP</name>\r
+ <file> 99 34 98 25 57 36 132 29 137 42 131 12 122 71 95 55 100 74 135 21</file>\r
+ </tool>\r
+ </inputs>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\Common\ethernet\uIP\uip-1.0\uip\timer.c</name>\r
+ <outputs>\r
+ <tool>\r
+ <name>ICCARM</name>\r
+ <file> 46</file>\r
+ </tool>\r
+ <tool>\r
+ <name>BICOMP</name>\r
+ <file> 33</file>\r
+ </tool>\r
+ </outputs>\r
+ <inputs>\r
+ <tool>\r
+ <name>ICCARM</name>\r
+ <file> 104 94 150 0 57 36 7 132 29 137 21 3 96 17 101 124</file>\r
+ </tool>\r
+ <tool>\r
+ <name>BICOMP</name>\r
+ <file> 104 94 150 0 57 36 132 29 137 21 3 96 17 101 124</file>\r
+ </tool>\r
+ </inputs>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\webserver\http-strings.c</name>\r
+ <outputs>\r
+ <tool>\r
+ <name>ICCARM</name>\r
+ <file> 129</file>\r
+ </tool>\r
+ <tool>\r
+ <name>BICOMP</name>\r
+ <file> 64</file>\r
+ </tool>\r
+ </outputs>\r
+ </file>\r
+ <forcedrebuild>\r
+ <name>[MULTI_TOOL]</name>\r
+ <tool>XLINK</tool>\r
+ </forcedrebuild>\r
+ </configuration>\r
+ <configuration>\r
+ <name>Release</name>\r
+ <outputs/>\r
+ <forcedrebuild>\r
+ <name>[MULTI_TOOL]</name>\r
+ <tool>XLINK</tool>\r
+ </forcedrebuild>\r
+ </configuration>\r
+</project>\r
+\r
+\r
--- /dev/null
+<?xml version="1.0" encoding="iso-8859-1"?>\r
+\r
+<project>\r
+ <fileVersion>1</fileVersion>\r
+ <configuration>\r
+ <name>Debug</name>\r
+ <toolchain>\r
+ <name>ARM</name>\r
+ </toolchain>\r
+ <debug>1</debug>\r
+ <settings>\r
+ <name>C-SPY</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>13</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>CInput</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CEndian</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CProcessor</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OCVariant</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>MacOverride</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>MacFile</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>MemOverride</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>MemFile</name>\r
+ <state>$TOOLKIT_DIR$\CONFIG\iolm3s828.ddf</state>\r
+ </option>\r
+ <option>\r
+ <name>RunToEnable</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>RunToName</name>\r
+ <state>main</state>\r
+ </option>\r
+ <option>\r
+ <name>CExtraOptionsCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CExtraOptions</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CFpuProcessor</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDDFArgumentProducer</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OCDownloadSuppressDownload</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDownloadVerifyAll</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OCProductVersion</name>\r
+ <state>4.41A</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDynDriverList</name>\r
+ <state>LMIFTDI_ID</state>\r
+ </option>\r
+ <option>\r
+ <name>OCLastSavedByProductVersion</name>\r
+ <state>4.41A</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDownloadAttachToProgram</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>FlashLoaders</name>\r
+ <state>,,,,(default),</state>\r
+ </option>\r
+ <option>\r
+ <name>UseFlashLoader</name>\r
+ <state>1</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>ARMSIM_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>0</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>OCSimDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>ANGEL_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>0</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>CCAngelHeartbeat</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CAngelCommunication</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CAngelCommBaud</name>\r
+ <version>0</version>\r
+ <state>3</state>\r
+ </option>\r
+ <option>\r
+ <name>CAngelCommPort</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>ANGELTCPIP</name>\r
+ <state>aaa.bbb.ccc.ddd</state>\r
+ </option>\r
+ <option>\r
+ <name>DoAngelLogfile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AngelLogFile</name>\r
+ <state>$TOOLKIT_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>IARROM_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>0</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>CRomLogFileCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CRomLogFileEditB</name>\r
+ <state>$TOOLKIT_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>CRomCommunication</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CRomCommPort</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CRomCommBaud</name>\r
+ <version>0</version>\r
+ <state>7</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>JLINK_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>6</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>JLinkSpeed</name>\r
+ <state>32</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkDoLogfile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkLogFile</name>\r
+ <state>$TOOLKIT_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkHWResetDelay</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>JLinkInitialSpeed</name>\r
+ <state>32</state>\r
+ </option>\r
+ <option>\r
+ <name>CCDoJlinkMultiTarget</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCScanChainNonARMDevices</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkMultiTarget</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkIRLength</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkCommRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkTCPIP</name>\r
+ <state>aaa.bbb.ccc.ddd</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkResetRadio</name>\r
+ <state>2</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkResetInitSeq</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkSpeedRadioV2</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCUSBDevice</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchReset</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchUndef</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchSWI</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchData</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchPrefetch</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchIRQ</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchFIQ</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkBreakpointRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkDoUpdateBreakpoints</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkUpdateBreakpoints</name>\r
+ <state>main</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>LMIFTDI_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>0</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>LmiftdiSpeed</name>\r
+ <state>500</state>\r
+ </option>\r
+ <option>\r
+ <name>CCLmiftdiResetRadio</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCLmiftdiDoLogfile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCLmiftdiLogFile</name>\r
+ <state>$TOOLKIT_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>CCLmiftdiBreakpointRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCLmiftdiDoUpdateBreakpoints</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCLmiftdiUpdateBreakpoints</name>\r
+ <state>main</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>MACRAIGOR_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>2</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>jtag</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>EmuSpeed</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>TCPIP</name>\r
+ <state>aaa.bbb.ccc.ddd</state>\r
+ </option>\r
+ <option>\r
+ <name>DoLogfile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>LogFile</name>\r
+ <state>$TOOLKIT_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>DoEmuMultiTarget</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>EmuMultiTarget</name>\r
+ <state>0@ARM7TDMI</state>\r
+ </option>\r
+ <option>\r
+ <name>EmuHWReset</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CEmuCommBaud</name>\r
+ <version>0</version>\r
+ <state>4</state>\r
+ </option>\r
+ <option>\r
+ <name>CEmuCommPort</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>jtago</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>UnusedAddr</name>\r
+ <state>0x00800000</state>\r
+ </option>\r
+ <option>\r
+ <name>CCMacraigorHWResetDelay</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCJTagBreakpointRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJTagDoUpdateBreakpoints</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJTagUpdateBreakpoints</name>\r
+ <state>main</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>RDI_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>1</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>CRDIDriverDll</name>\r
+ <state>Browse to your RDI driver</state>\r
+ </option>\r
+ <option>\r
+ <name>CRDILogFileCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CRDILogFileEdit</name>\r
+ <state>$TOOLKIT_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDIHWReset</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchReset</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchUndef</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchSWI</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchData</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchPrefetch</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchIRQ</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchFIQ</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDIUseETM</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>THIRDPARTY_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>0</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>CThirdPartyDriverDll</name>\r
+ <state>Browse to your third-party driver</state>\r
+ </option>\r
+ <option>\r
+ <name>CThirdPartyLogFileCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CThirdPartyLogFileEditB</name>\r
+ <state>$TOOLKIT_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <debuggerPlugins>\r
+ <plugin>\r
+ <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ewplugin</file>\r
+ <loadFlag>1</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$EW_DIR$\common\plugins\Orti\Orti.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$EW_DIR$\common\plugins\Profiling\Profiling.ewplugin</file>\r
+ <loadFlag>1</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$EW_DIR$\common\plugins\Stack\Stack.ewplugin</file>\r
+ <loadFlag>1</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CMXArmPlugin.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CMXTinyArmPlugin.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\OSE\OseEpsilonPlugin.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\PowerPac\PowerPacRTOS.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ </debuggerPlugins>\r
+ </configuration>\r
+ <configuration>\r
+ <name>Release</name>\r
+ <toolchain>\r
+ <name>ARM</name>\r
+ </toolchain>\r
+ <debug>0</debug>\r
+ <settings>\r
+ <name>C-SPY</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>13</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>0</debug>\r
+ <option>\r
+ <name>CInput</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CEndian</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CProcessor</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OCVariant</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>MacOverride</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>MacFile</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>MemOverride</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>MemFile</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>RunToEnable</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>RunToName</name>\r
+ <state>main</state>\r
+ </option>\r
+ <option>\r
+ <name>CExtraOptionsCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CExtraOptions</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CFpuProcessor</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDDFArgumentProducer</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OCDownloadSuppressDownload</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDownloadVerifyAll</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCProductVersion</name>\r
+ <state>4.41A</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDynDriverList</name>\r
+ <state>ARMSIM_ID</state>\r
+ </option>\r
+ <option>\r
+ <name>OCLastSavedByProductVersion</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OCDownloadAttachToProgram</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>FlashLoaders</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>UseFlashLoader</name>\r
+ <state>0</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>ARMSIM_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>0</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>0</debug>\r
+ <option>\r
+ <name>OCSimDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>ANGEL_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>0</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>0</debug>\r
+ <option>\r
+ <name>CCAngelHeartbeat</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CAngelCommunication</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CAngelCommBaud</name>\r
+ <version>0</version>\r
+ <state>3</state>\r
+ </option>\r
+ <option>\r
+ <name>CAngelCommPort</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>ANGELTCPIP</name>\r
+ <state>aaa.bbb.ccc.ddd</state>\r
+ </option>\r
+ <option>\r
+ <name>DoAngelLogfile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AngelLogFile</name>\r
+ <state>$TOOLKIT_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>IARROM_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>0</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>0</debug>\r
+ <option>\r
+ <name>CRomLogFileCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CRomLogFileEditB</name>\r
+ <state>$TOOLKIT_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>CRomCommunication</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CRomCommPort</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CRomCommBaud</name>\r
+ <version>0</version>\r
+ <state>7</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>JLINK_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>6</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>0</debug>\r
+ <option>\r
+ <name>JLinkSpeed</name>\r
+ <state>32</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkDoLogfile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkLogFile</name>\r
+ <state>$TOOLKIT_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkHWResetDelay</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>JLinkInitialSpeed</name>\r
+ <state>32</state>\r
+ </option>\r
+ <option>\r
+ <name>CCDoJlinkMultiTarget</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCScanChainNonARMDevices</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkMultiTarget</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkIRLength</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkCommRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkTCPIP</name>\r
+ <state>aaa.bbb.ccc.ddd</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkResetRadio</name>\r
+ <state>2</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkResetInitSeq</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkSpeedRadioV2</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCUSBDevice</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchReset</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchUndef</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchSWI</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchData</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchPrefetch</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchIRQ</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchFIQ</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkBreakpointRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkDoUpdateBreakpoints</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkUpdateBreakpoints</name>\r
+ <state>main</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>LMIFTDI_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>0</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>0</debug>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>LmiftdiSpeed</name>\r
+ <state>500</state>\r
+ </option>\r
+ <option>\r
+ <name>CCLmiftdiResetRadio</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCLmiftdiDoLogfile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCLmiftdiLogFile</name>\r
+ <state>$TOOLKIT_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>CCLmiftdiBreakpointRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCLmiftdiDoUpdateBreakpoints</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCLmiftdiUpdateBreakpoints</name>\r
+ <state>main</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>MACRAIGOR_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>2</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>0</debug>\r
+ <option>\r
+ <name>jtag</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>EmuSpeed</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>TCPIP</name>\r
+ <state>aaa.bbb.ccc.ddd</state>\r
+ </option>\r
+ <option>\r
+ <name>DoLogfile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>LogFile</name>\r
+ <state>$TOOLKIT_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>DoEmuMultiTarget</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>EmuMultiTarget</name>\r
+ <state>0@ARM7TDMI</state>\r
+ </option>\r
+ <option>\r
+ <name>EmuHWReset</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CEmuCommBaud</name>\r
+ <version>0</version>\r
+ <state>4</state>\r
+ </option>\r
+ <option>\r
+ <name>CEmuCommPort</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>jtago</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>UnusedAddr</name>\r
+ <state>0x00800000</state>\r
+ </option>\r
+ <option>\r
+ <name>CCMacraigorHWResetDelay</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCJTagBreakpointRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJTagDoUpdateBreakpoints</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJTagUpdateBreakpoints</name>\r
+ <state>main</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>RDI_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>1</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>0</debug>\r
+ <option>\r
+ <name>CRDIDriverDll</name>\r
+ <state>Browse to your RDI driver</state>\r
+ </option>\r
+ <option>\r
+ <name>CRDILogFileCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CRDILogFileEdit</name>\r
+ <state>$TOOLKIT_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDIHWReset</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchReset</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchUndef</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchSWI</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchData</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchPrefetch</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchIRQ</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchFIQ</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDIUseETM</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>THIRDPARTY_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>0</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>0</debug>\r
+ <option>\r
+ <name>CThirdPartyDriverDll</name>\r
+ <state>Browse to your third-party driver</state>\r
+ </option>\r
+ <option>\r
+ <name>CThirdPartyLogFileCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CThirdPartyLogFileEditB</name>\r
+ <state>$TOOLKIT_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <debuggerPlugins>\r
+ <plugin>\r
+ <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ewplugin</file>\r
+ <loadFlag>1</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$EW_DIR$\common\plugins\Orti\Orti.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$EW_DIR$\common\plugins\Profiling\Profiling.ewplugin</file>\r
+ <loadFlag>1</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$EW_DIR$\common\plugins\Stack\Stack.ewplugin</file>\r
+ <loadFlag>1</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CMXArmPlugin.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CMXTinyArmPlugin.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\OSE\OseEpsilonPlugin.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\PowerPac\PowerPacRTOS.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ </debuggerPlugins>\r
+ </configuration>\r
+</project>\r
+\r
+\r
--- /dev/null
+<?xml version="1.0" encoding="iso-8859-1"?>\r
+\r
+<project>\r
+ <fileVersion>1</fileVersion>\r
+ <configuration>\r
+ <name>Debug</name>\r
+ <toolchain>\r
+ <name>ARM</name>\r
+ </toolchain>\r
+ <debug>1</debug>\r
+ <settings>\r
+ <name>General</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>9</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>OGProductVersion</name>\r
+ <state>4.41A</state>\r
+ </option>\r
+ <option>\r
+ <name>GProcessorMode</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>ExePath</name>\r
+ <state>Debug\Exe</state>\r
+ </option>\r
+ <option>\r
+ <name>ObjPath</name>\r
+ <state>Debug\Obj</state>\r
+ </option>\r
+ <option>\r
+ <name>ListPath</name>\r
+ <state>Debug\List</state>\r
+ </option>\r
+ <option>\r
+ <name>Variant</name>\r
+ <version>5</version>\r
+ <state>25</state>\r
+ </option>\r
+ <option>\r
+ <name>GEndianMode</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>GInterwork</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>GStackAlign</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>Input variant</name>\r
+ <version>1</version>\r
+ <state>3</state>\r
+ </option>\r
+ <option>\r
+ <name>Input description</name>\r
+ <state>No specifier n, no float nor long long, no scan set, no assignment suppressing.</state>\r
+ </option>\r
+ <option>\r
+ <name>Output variant</name>\r
+ <version>0</version>\r
+ <state>2</state>\r
+ </option>\r
+ <option>\r
+ <name>Output description</name>\r
+ <state>No specifier a, A, no specifier n, no float nor long long.</state>\r
+ </option>\r
+ <option>\r
+ <name>GOutputBinary</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>FPU</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OGCoreOrChip</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>GRuntimeLibSelect</name>\r
+ <version>0</version>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>GRuntimeLibSelectSlave</name>\r
+ <version>0</version>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>RTDescription</name>\r
+ <state>Use the normal configuration of the C/C++ runtime library. No locale interface, C locale, no file descriptor support, no multibytes in printf and scanf, and no hex floats in strtod.</state>\r
+ </option>\r
+ <option>\r
+ <name>RTConfigPath</name>\r
+ <state>$TOOLKIT_DIR$\LIB\dl7mptnnl8n.h</state>\r
+ </option>\r
+ <option>\r
+ <name>RTLibraryPath</name>\r
+ <state>$TOOLKIT_DIR$\LIB\dl7mptnnl8n.r79</state>\r
+ </option>\r
+ <option>\r
+ <name>OGLastSavedByProductVersion</name>\r
+ <state>4.41A</state>\r
+ </option>\r
+ <option>\r
+ <name>GeneralMisraRules</name>\r
+ <version>0</version>\r
+ <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>\r
+ </option>\r
+ <option>\r
+ <name>GeneralEnableMisra</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>GeneralMisraVerbose</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OGChipSelectEditMenu</name>\r
+ <state>LM3Sx9xx Luminary LM3Sx9xx</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>ICCARM</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>14</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>CCDefines</name>\r
+ <state>IAR_ARMCM3_LM</state>\r
+ <state>PACK_STRUCT_END=</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPreprocFile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPreprocComments</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPreprocLine</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCListCFile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCListCMnemonics</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCListCMessages</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCListAssFile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCListAssSource</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCEnableRemarks</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCDiagSuppress</name>\r
+ <state>pa082, pe513, pe167, pe550, pe144, pe191, pe177, pa039, pa050</state>\r
+ </option>\r
+ <option>\r
+ <name>CCDiagRemark</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCDiagWarning</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCDiagError</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCObjPrefix</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCOptSizeSpeed</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCOptimization</name>\r
+ <version>0</version>\r
+ <state>2</state>\r
+ </option>\r
+ <option>\r
+ <name>CCAllowList</name>\r
+ <version>1</version>\r
+ <state>1001000</state>\r
+ </option>\r
+ <option>\r
+ <name>CCObjUseModuleName</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCObjModuleName</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCDebugInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IProcessorMode</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IEndianMode</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IProcessor</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IStackAlign</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IInterwork</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IExtraOptionsCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IExtraOptions</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCLangConformance</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSignedPlainChar</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRequirePrototypes</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCMultibyteSupport</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCDiagWarnAreErr</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCompilerRuntimeInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IFpuProcessor</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OutputFile</name>\r
+ <state>$FILE_BNAME$.r79</state>\r
+ </option>\r
+ <option>\r
+ <name>CCLangSelect</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCLibConfigHeader</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCOptSizeSpeedSlave</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCOptimizationSlave</name>\r
+ <version>0</version>\r
+ <state>2</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCodeFunctions</name>\r
+ <state>CODE</state>\r
+ </option>\r
+ <option>\r
+ <name>CCData</name>\r
+ <state>DATA</state>\r
+ </option>\r
+ <option>\r
+ <name>PreInclude</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CompilerMisraRules</name>\r
+ <version>0</version>\r
+ <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>\r
+ </option>\r
+ <option>\r
+ <name>CompilerMisraOverride</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCModuleTypeOverride</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCModuleType</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCModuleTypeCmdlineProducer</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCIncludePath2</name>\r
+ <state>$PROJ_DIR$\</state>\r
+ <state>$PROJ_DIR$\LuminaryDrivers</state>\r
+ <state>$PROJ_DIR$\..\common\include</state>\r
+ <state>$PROJ_DIR$\..\..\source\include</state>\r
+ <state>$PROJ_DIR$\webserver</state>\r
+ <state>$PROJ_DIR$\..\Common\ethernet\uIP\uip-1.0\uip</state>\r
+ </option>\r
+ <option>\r
+ <name>CCStdIncCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCStdIncludePath</name>\r
+ <state>$TOOLKIT_DIR$\INC\</state>\r
+ </option>\r
+ <option>\r
+ <name>CCInlineThreshold</name>\r
+ <version>0</version>\r
+ <state>1</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>AARM</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>7</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>AObjPrefix</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>AEndian</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>ACaseSensitivity</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>MacroChars</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AWarnEnable</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AWarnWhat</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AWarnOne</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>AWarnRange1</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>AWarnRange2</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>ADebug</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>AltRegisterNames</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>ADefines</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>AList</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AListHeader</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>AListing</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>Includes</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>MacDefs</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>MacExps</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>MacExec</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OnlyAssed</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>MultiLine</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>PageLengthCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>PageLength</name>\r
+ <state>80</state>\r
+ </option>\r
+ <option>\r
+ <name>TabSpacing</name>\r
+ <state>8</state>\r
+ </option>\r
+ <option>\r
+ <name>AXRef</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AXRefDefines</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AXRefInternal</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AXRefDual</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AProcessor</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>AFpuProcessor</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>AOutputFile</name>\r
+ <state>$FILE_BNAME$.r79</state>\r
+ </option>\r
+ <option>\r
+ <name>AMultibyteSupport</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>ALimitErrorsCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>ALimitErrorsEdit</name>\r
+ <state>100</state>\r
+ </option>\r
+ <option>\r
+ <name>AIgnoreStdInclude</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AStdIncludes</name>\r
+ <state>$TOOLKIT_DIR$\INC\</state>\r
+ </option>\r
+ <option>\r
+ <name>AUserIncludes</name>\r
+ <state>$PROJ_DIR$\</state>\r
+ </option>\r
+ <option>\r
+ <name>AExtraOptionsCheckV2</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AExtraOptionsV2</name>\r
+ <state></state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>CUSTOM</name>\r
+ <archiveVersion>3</archiveVersion>\r
+ <data>\r
+ <extensions></extensions>\r
+ <cmdline></cmdline>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>BICOMP</name>\r
+ <archiveVersion>0</archiveVersion>\r
+ <data/>\r
+ </settings>\r
+ <settings>\r
+ <name>BUILDACTION</name>\r
+ <archiveVersion>1</archiveVersion>\r
+ <data>\r
+ <prebuild></prebuild>\r
+ <postbuild></postbuild>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>XLINK</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>18</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>XOutOverride</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OutputFile</name>\r
+ <state>RTOSDemo.d79</state>\r
+ </option>\r
+ <option>\r
+ <name>OutputFormat</name>\r
+ <version>11</version>\r
+ <state>16</state>\r
+ </option>\r
+ <option>\r
+ <name>FormatVariant</name>\r
+ <version>7</version>\r
+ <state>16</state>\r
+ </option>\r
+ <option>\r
+ <name>SecondaryOutputFile</name>\r
+ <state>(None for the selected format)</state>\r
+ </option>\r
+ <option>\r
+ <name>XDefines</name>\r
+ <state>__vector_table=0</state>\r
+ </option>\r
+ <option>\r
+ <name>AlwaysOutput</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OverlapWarnings</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>NoGlobalCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>XList</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>SegmentMap</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>ListSymbols</name>\r
+ <state>2</state>\r
+ </option>\r
+ <option>\r
+ <name>PageLengthCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>PageLength</name>\r
+ <state>80</state>\r
+ </option>\r
+ <option>\r
+ <name>XIncludes</name>\r
+ <state>$TOOLKIT_DIR$\LIB\</state>\r
+ </option>\r
+ <option>\r
+ <name>ModuleStatus</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>XclOverride</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>XclFile</name>\r
+ <state>$PROJ_DIR$\RTOSDemo.xcl</state>\r
+ </option>\r
+ <option>\r
+ <name>XclFileSlave</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>DoFill</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>FillerByte</name>\r
+ <state>0xFF</state>\r
+ </option>\r
+ <option>\r
+ <name>DoCrc</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CrcSize</name>\r
+ <version>0</version>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CrcAlgo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CrcPoly</name>\r
+ <state>0x11021</state>\r
+ </option>\r
+ <option>\r
+ <name>CrcCompl</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>RangeCheckAlternatives</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>SuppressAllWarn</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>SuppressDiags</name>\r
+ <state>w6</state>\r
+ </option>\r
+ <option>\r
+ <name>TreatAsWarn</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>TreatAsErr</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>ModuleLocalSym</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CrcBitOrder</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>XExtraOptionsCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>XExtraOptions</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>IncludeSuppressed</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OXLibIOConfig</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>ModuleSummary</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>xcProgramEntryLabel</name>\r
+ <state>ResetISR</state>\r
+ </option>\r
+ <option>\r
+ <name>DebugInformation</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>RuntimeControl</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IoEmulation</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>XcRTLibraryFile</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>AllowExtraOutput</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>GenerateExtraOutput</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>XExtraOutOverride</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>ExtraOutputFile</name>\r
+ <state>RTOSDemo.sim</state>\r
+ </option>\r
+ <option>\r
+ <name>ExtraOutputFormat</name>\r
+ <version>11</version>\r
+ <state>60</state>\r
+ </option>\r
+ <option>\r
+ <name>ExtraFormatVariant</name>\r
+ <version>7</version>\r
+ <state>2</state>\r
+ </option>\r
+ <option>\r
+ <name>xcOverrideProgramEntryLabel</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>xcProgramEntryLabelSelect</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>ListOutputFormat</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>BufferedTermOutput</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OverlaySystemMap</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>RawBinaryFile</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>RawBinarySymbol</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>RawBinarySegment</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>RawBinaryAlign</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>XLinkMisraHandler</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CrcAlign</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CrcInitialValue</name>\r
+ <state>0x0</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>XAR</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>0</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>XARInputs</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>XAROverride</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>XAROutput</name>\r
+ <state>###Unitialized###</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>BILINK</name>\r
+ <archiveVersion>0</archiveVersion>\r
+ <data/>\r
+ </settings>\r
+ </configuration>\r
+ <configuration>\r
+ <name>Release</name>\r
+ <toolchain>\r
+ <name>ARM</name>\r
+ </toolchain>\r
+ <debug>0</debug>\r
+ <settings>\r
+ <name>General</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>9</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>0</debug>\r
+ <option>\r
+ <name>OGProductVersion</name>\r
+ <state>4.41A</state>\r
+ </option>\r
+ <option>\r
+ <name>GProcessorMode</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>ExePath</name>\r
+ <state>Release\Exe</state>\r
+ </option>\r
+ <option>\r
+ <name>ObjPath</name>\r
+ <state>Release\Obj</state>\r
+ </option>\r
+ <option>\r
+ <name>ListPath</name>\r
+ <state>Release\List</state>\r
+ </option>\r
+ <option>\r
+ <name>Variant</name>\r
+ <version>5</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>GEndianMode</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>GInterwork</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>GStackAlign</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>Input variant</name>\r
+ <version>1</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>Input description</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>Output variant</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>Output description</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>GOutputBinary</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>FPU</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OGCoreOrChip</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>GRuntimeLibSelect</name>\r
+ <version>0</version>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>GRuntimeLibSelectSlave</name>\r
+ <version>0</version>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>RTDescription</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>RTConfigPath</name>\r
+ <state>dl-stnl0.r79</state>\r
+ </option>\r
+ <option>\r
+ <name>RTLibraryPath</name>\r
+ <state>dl-stnl0.r79</state>\r
+ </option>\r
+ <option>\r
+ <name>OGLastSavedByProductVersion</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>GeneralMisraRules</name>\r
+ <version>0</version>\r
+ <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>\r
+ </option>\r
+ <option>\r
+ <name>GeneralEnableMisra</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>GeneralMisraVerbose</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OGChipSelectEditMenu</name>\r
+ <state>LPC2106 NXP LPC2106</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>ICCARM</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>14</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>0</debug>\r
+ <option>\r
+ <name>CCDefines</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCPreprocFile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPreprocComments</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPreprocLine</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCListCFile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCListCMnemonics</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCListCMessages</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCListAssFile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCListAssSource</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCEnableRemarks</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCDiagSuppress</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCDiagRemark</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCDiagWarning</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCDiagError</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCObjPrefix</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCOptSizeSpeed</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCOptimization</name>\r
+ <version>0</version>\r
+ <state>3</state>\r
+ </option>\r
+ <option>\r
+ <name>CCAllowList</name>\r
+ <version>1</version>\r
+ <state>1111111</state>\r
+ </option>\r
+ <option>\r
+ <name>CCObjUseModuleName</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCObjModuleName</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCDebugInfo</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IProcessorMode</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IEndianMode</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IProcessor</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IStackAlign</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IInterwork</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IExtraOptionsCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IExtraOptions</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCLangConformance</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSignedPlainChar</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRequirePrototypes</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCMultibyteSupport</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCDiagWarnAreErr</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCompilerRuntimeInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IFpuProcessor</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OutputFile</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCLangSelect</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCLibConfigHeader</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCOptSizeSpeedSlave</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCOptimizationSlave</name>\r
+ <version>0</version>\r
+ <state>3</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCodeFunctions</name>\r
+ <state>CODE</state>\r
+ </option>\r
+ <option>\r
+ <name>CCData</name>\r
+ <state>DATA</state>\r
+ </option>\r
+ <option>\r
+ <name>PreInclude</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CompilerMisraRules</name>\r
+ <version>0</version>\r
+ <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>\r
+ </option>\r
+ <option>\r
+ <name>CompilerMisraOverride</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCModuleTypeOverride</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCModuleType</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCModuleTypeCmdlineProducer</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCIncludePath2</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCStdIncCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCStdIncludePath</name>\r
+ <state>###Uninitialized###</state>\r
+ </option>\r
+ <option>\r
+ <name>CCInlineThreshold</name>\r
+ <version>0</version>\r
+ <state>1</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>AARM</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>7</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>0</debug>\r
+ <option>\r
+ <name>AObjPrefix</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>AEndian</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>ACaseSensitivity</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>MacroChars</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AWarnEnable</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AWarnWhat</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AWarnOne</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>AWarnRange1</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>AWarnRange2</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>ADebug</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AltRegisterNames</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>ADefines</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>AList</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AListHeader</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>AListing</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>Includes</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>MacDefs</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>MacExps</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>MacExec</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OnlyAssed</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>MultiLine</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>PageLengthCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>PageLength</name>\r
+ <state>80</state>\r
+ </option>\r
+ <option>\r
+ <name>TabSpacing</name>\r
+ <state>8</state>\r
+ </option>\r
+ <option>\r
+ <name>AXRef</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AXRefDefines</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AXRefInternal</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AXRefDual</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AProcessor</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>AFpuProcessor</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>AOutputFile</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>AMultibyteSupport</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>ALimitErrorsCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>ALimitErrorsEdit</name>\r
+ <state>100</state>\r
+ </option>\r
+ <option>\r
+ <name>AIgnoreStdInclude</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AStdIncludes</name>\r
+ <state>$TOOLKIT_DIR$\INC\</state>\r
+ </option>\r
+ <option>\r
+ <name>AUserIncludes</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>AExtraOptionsCheckV2</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AExtraOptionsV2</name>\r
+ <state></state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>CUSTOM</name>\r
+ <archiveVersion>3</archiveVersion>\r
+ <data>\r
+ <extensions></extensions>\r
+ <cmdline></cmdline>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>BICOMP</name>\r
+ <archiveVersion>0</archiveVersion>\r
+ <data/>\r
+ </settings>\r
+ <settings>\r
+ <name>BUILDACTION</name>\r
+ <archiveVersion>1</archiveVersion>\r
+ <data>\r
+ <prebuild></prebuild>\r
+ <postbuild></postbuild>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>XLINK</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>18</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>0</debug>\r
+ <option>\r
+ <name>XOutOverride</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OutputFile</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OutputFormat</name>\r
+ <version>11</version>\r
+ <state>16</state>\r
+ </option>\r
+ <option>\r
+ <name>FormatVariant</name>\r
+ <version>7</version>\r
+ <state>16</state>\r
+ </option>\r
+ <option>\r
+ <name>SecondaryOutputFile</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>XDefines</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>AlwaysOutput</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OverlapWarnings</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>NoGlobalCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>XList</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>SegmentMap</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>ListSymbols</name>\r
+ <state>2</state>\r
+ </option>\r
+ <option>\r
+ <name>PageLengthCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>PageLength</name>\r
+ <state>80</state>\r
+ </option>\r
+ <option>\r
+ <name>XIncludes</name>\r
+ <state>###Uninitialized###</state>\r
+ </option>\r
+ <option>\r
+ <name>ModuleStatus</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>XclOverride</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>XclFile</name>\r
+ <state>lnk0t.xcl</state>\r
+ </option>\r
+ <option>\r
+ <name>XclFileSlave</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>DoFill</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>FillerByte</name>\r
+ <state>0xFF</state>\r
+ </option>\r
+ <option>\r
+ <name>DoCrc</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CrcSize</name>\r
+ <version>0</version>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CrcAlgo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CrcPoly</name>\r
+ <state>0x11021</state>\r
+ </option>\r
+ <option>\r
+ <name>CrcCompl</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>RangeCheckAlternatives</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>SuppressAllWarn</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>SuppressDiags</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>TreatAsWarn</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>TreatAsErr</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>ModuleLocalSym</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CrcBitOrder</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>XExtraOptionsCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>XExtraOptions</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>IncludeSuppressed</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OXLibIOConfig</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>ModuleSummary</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>xcProgramEntryLabel</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>DebugInformation</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>RuntimeControl</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IoEmulation</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>XcRTLibraryFile</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>AllowExtraOutput</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>GenerateExtraOutput</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>XExtraOutOverride</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>ExtraOutputFile</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>ExtraOutputFormat</name>\r
+ <version>11</version>\r
+ <state>23</state>\r
+ </option>\r
+ <option>\r
+ <name>ExtraFormatVariant</name>\r
+ <version>7</version>\r
+ <state>2</state>\r
+ </option>\r
+ <option>\r
+ <name>xcOverrideProgramEntryLabel</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>xcProgramEntryLabelSelect</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>ListOutputFormat</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>BufferedTermOutput</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OverlaySystemMap</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>RawBinaryFile</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>RawBinarySymbol</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>RawBinarySegment</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>RawBinaryAlign</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>XLinkMisraHandler</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CrcAlign</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CrcInitialValue</name>\r
+ <state>0x0</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>XAR</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>0</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>0</debug>\r
+ <option>\r
+ <name>XARInputs</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>XAROverride</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>XAROutput</name>\r
+ <state>###Unitialized###</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>BILINK</name>\r
+ <archiveVersion>0</archiveVersion>\r
+ <data/>\r
+ </settings>\r
+ </configuration>\r
+ <group>\r
+ <name>Demo files</name>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\Common\Minimal\BlockQ.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\Common\Minimal\blocktim.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\Common\Minimal\death.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\Common\Minimal\flash.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\Common\Minimal\integer.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\main.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\ParTest\ParTest.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\Common\Minimal\PollQ.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\Common\Minimal\semtest.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\timertest.c</name>\r
+ </file>\r
+ </group>\r
+ <group>\r
+ <name>Library files</name>\r
+ <file>\r
+ <name>$PROJ_DIR$\LuminaryDrivers\driverlib.r79</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\LuminaryDrivers\osram128x64x4.c</name>\r
+ </file>\r
+ </group>\r
+ <group>\r
+ <name>Scheduler files</name>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Source\portable\MemMang\heap_2.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Source\list.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Source\portable\IAR\ARM_CM3\port.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Source\portable\IAR\ARM_CM3\portasm.s</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Source\queue.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Source\tasks.c</name>\r
+ </file>\r
+ </group>\r
+ <group>\r
+ <name>System files</name>\r
+ <file>\r
+ <name>$PROJ_DIR$\startup_ewarm.c</name>\r
+ </file>\r
+ </group>\r
+</project>\r
+\r
+\r
--- /dev/null
+<?xml version="1.0" encoding="iso-8859-1"?>\r
+\r
+<workspace>\r
+ <project>\r
+ <path>$WS_DIR$\RTOSDemo.ewp</path>\r
+ </project>\r
+ <batchBuild/>\r
+</workspace>\r
+\r
+\r
--- /dev/null
+//*****************************************************************************
+//
+// webserver-lwip.xcl - Linker script for EW-ARM.
+//
+// Copyright (c) 2006-2007 Luminary Micro, Inc. All rights reserved.
+//
+// Software License Agreement
+//
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's microcontroller products.
+//
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws. All rights are reserved. Any use in violation
+// of the foregoing restrictions may subject the user to criminal sanctions
+// under applicable laws, as well as to civil liability for the breach of the
+// terms and conditions of this license.
+//
+// THIS SOFTWARE IS PROVIDED AS IS. NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+//*****************************************************************************
+
+//
+// Set the CPU type to ARM.
+//
+-carm
+
+//
+// Define the size of flash and SRAM.
+//
+-DROMSTART=00000000
+-DROMEND=00040000
+-DRAMSTART=20000000
+-DRAMEND=20010000\r
+\r
+
+
+//
+// Define the sections to place into flash, and the order to place them.
+//
+-Z(CODE)INTVEC=ROMSTART-ROMEND
+-Z(CODE)ICODE,DIFUNCT=ROMSTART-ROMEND
+-Z(CODE)CODE=ROMSTART-ROMEND
+-Z(CONST)CODE_ID=ROMSTART-ROMEND
+-Z(CONST)INITTAB,DATA_ID,DATA_C=ROMSTART-ROMEND
+-Z(CONST)CHECKSUM=ROMSTART-ROMEND
+
+//
+// Define the sections to place into SRAM, and the order to place them.
+//
+-Z(DATA)VTABLE=RAMSTART-RAMEND
+-Z(DATA)DATA_I,DATA_Z,DATA_N=RAMSTART-RAMEND
+-Z(DATA)CODE_I=RAMSTART-RAMEND
--- /dev/null
+#ifndef BITMAP_H\r
+#define BITMAP_H\r
+\r
+const unsigned char pucImage[] =\r
+{\r
+0x00, 0x0a, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,\r
+0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,\r
+0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,\r
+0xaa, 0xaa, 0xaa, 0x00, 0x0a, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,\r
+0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,\r
+0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,\r
+0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xa0, 0x0a, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,\r
+0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,\r
+0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,\r
+0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xaa, 0xaa, 0xaa, 0xaf, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfa, 0xaa,\r
+0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf7,\r
+0x00, 0x8f, 0xff, 0xff, 0xf8, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0xff, 0xff, 0xff, 0xff, 0xf8, 0x88, 0x88, 0x88,\r
+0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x8f, 0xff, 0xff, 0xff, 0xff, 0xff, 0x88, 0x77, 0x77, 0x78, 0x8f, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xf8, 0x88, 0x77, 0x77, 0x88, 0x8f, 0xff, 0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff,\r
+0xff, 0xff, 0xf0, 0x00, 0x00, 0x8f, 0x00, 0xff, 0x87, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x78, 0xff, 0xff,\r
+0xf7, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x78, 0xff, 0xff, 0xff, 0x87, 0x77, 0x77, 0x77, 0x77, 0x77,\r
+0x77, 0x77, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x7f, 0xff, 0xff, 0xfa, 0xaa,\r
+0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0x70, 0x00, 0x00, 0x8f, 0x00, 0xff, 0x87, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77,\r
+0x77, 0x77, 0xff, 0xff, 0xf7, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x78, 0xff, 0xff, 0xf8, 0x77, 0x77,\r
+0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x78, 0xff, 0xff, 0xff, 0xff, 0x87, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x8f,\r
+0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0x70, 0x08, 0x00, 0x8f, 0x00, 0xff, 0x87, 0x77, 0x77, 0x77,\r
+0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x8f, 0xff, 0xf7, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x78, 0xff,\r
+0xff, 0x87, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x8f, 0xff, 0xff, 0xf8, 0x77, 0x77, 0x77, 0x77, 0x77,\r
+0x77, 0x77, 0x77, 0x8f, 0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0x00, 0x0f, 0x00, 0x8f, 0x00, 0xff,\r
+0x87, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x78, 0xff, 0xf7, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77,\r
+0x77, 0x77, 0x78, 0xff, 0xf8, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x78, 0xff, 0xff, 0xf8, 0x77,\r
+0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x8f, 0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0x70, 0x07,\r
+0x00, 0x70, 0x00, 0xff, 0x87, 0x77, 0x77, 0x77, 0xff, 0xff, 0xf8, 0x77, 0x77, 0x77, 0x77, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0x77, 0x77, 0x77, 0x7f, 0xff, 0xff, 0xff, 0xff, 0x87, 0x77, 0x77, 0x77, 0x78, 0xff, 0xff, 0xf8, 0x77, 0x77, 0x77, 0x77,\r
+0xff, 0xff, 0x87, 0x77, 0x77, 0x77, 0x8f, 0xff, 0xff, 0xff, 0x88, 0x8f, 0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff,\r
+0xff, 0xff, 0x80, 0x00, 0x00, 0x00, 0x07, 0xff, 0x87, 0x77, 0x77, 0x77, 0xff, 0xff, 0xff, 0x87, 0x77, 0x77, 0x77, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0x77, 0x77, 0x77, 0x7f, 0xff, 0xff, 0xff, 0xff, 0x77, 0x77, 0x77, 0x77, 0xff, 0xff, 0xff, 0xff,\r
+0x87, 0x77, 0x77, 0x77, 0xff, 0xff, 0x77, 0x77, 0x77, 0x77, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfa, 0xaa,\r
+0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0xf7, 0x00, 0x00, 0x00, 0x0f, 0xff, 0x87, 0x77, 0x77, 0x77, 0xff, 0xff, 0xff, 0xf8,\r
+0x77, 0x77, 0x77, 0xff, 0xff, 0xff, 0xff, 0xff, 0x77, 0x77, 0x77, 0x7f, 0xff, 0xff, 0xff, 0xff, 0x77, 0x77, 0x77, 0x77,\r
+0xff, 0xff, 0xff, 0xff, 0xf7, 0x77, 0x77, 0x77, 0x8f, 0xff, 0x77, 0x77, 0x77, 0x77, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0xff, 0x70, 0x00, 0x00, 0xff, 0xff, 0x87, 0x77, 0x77, 0x77,\r
+0xff, 0xff, 0xff, 0xf8, 0x77, 0x77, 0x77, 0xff, 0xff, 0xff, 0xff, 0xff, 0x77, 0x77, 0x77, 0x7f, 0xff, 0xff, 0xff, 0xff,\r
+0x77, 0x77, 0x77, 0x78, 0xff, 0xff, 0xff, 0xff, 0xf8, 0x77, 0x77, 0x77, 0x8f, 0xff, 0x77, 0x77, 0x77, 0x77, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0x87, 0x77, 0x77, 0x77, 0xff, 0xff, 0xff, 0xf7, 0x77, 0x77, 0x78, 0xff, 0xff, 0xff, 0xff, 0xff, 0x77, 0x77, 0x77, 0x7f,\r
+0xff, 0xff, 0xff, 0xf8, 0x77, 0x77, 0x77, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xff, 0x87, 0x77, 0x77, 0x78, 0xff, 0x87, 0x77,\r
+0x77, 0x77, 0x78, 0x8f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0x88, 0xff, 0xff, 0xff, 0x87, 0x77, 0x77, 0x77, 0xff, 0xff, 0xf8, 0x87, 0x77, 0x77, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0x77, 0x77, 0x77, 0x7f, 0xff, 0xff, 0xff, 0xf8, 0x77, 0x77, 0x77, 0x8f, 0xff, 0xff, 0xff, 0xff, 0xff, 0x87, 0x77, 0x77,\r
+0x78, 0xff, 0x87, 0x77, 0x77, 0x77, 0x77, 0x77, 0x8f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0x80, 0x00, 0x8f, 0x8f, 0xff, 0x87, 0x77, 0x77, 0x77, 0x88, 0x88, 0x77, 0x77, 0x77, 0x77, 0x8f, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0x77, 0x77, 0x77, 0x7f, 0xff, 0xff, 0xff, 0xf8, 0x77, 0x77, 0x77, 0x8f, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0x87, 0x77, 0x77, 0x78, 0xff, 0xf7, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x88, 0xff, 0xff, 0xff, 0xff, 0xfa, 0xaa,\r
+0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0xf7, 0x00, 0x00, 0x8f, 0x07, 0xff, 0x87, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77,\r
+0x77, 0x77, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x77, 0x77, 0x77, 0x7f, 0xff, 0xff, 0xff, 0xf8, 0x77, 0x77, 0x77, 0x8f,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0x87, 0x77, 0x77, 0x78, 0xff, 0xf8, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x8f, 0xff,\r
+0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0x70, 0x07, 0x00, 0x8f, 0x00, 0xff, 0x87, 0x77, 0x77, 0x77,\r
+0x77, 0x77, 0x77, 0x77, 0x88, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x77, 0x77, 0x77, 0x7f, 0xff, 0xff, 0xff, 0xf8,\r
+0x77, 0x77, 0x77, 0x8f, 0xff, 0xff, 0xff, 0xff, 0xff, 0x87, 0x77, 0x77, 0x78, 0xff, 0xff, 0xf8, 0x77, 0x77, 0x77, 0x77,\r
+0x77, 0x77, 0x77, 0x8f, 0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0x70, 0x0f, 0x00, 0x8f, 0x00, 0xff,\r
+0x87, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x8f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x77, 0x77, 0x77, 0x7f,\r
+0xff, 0xff, 0xff, 0xf8, 0x77, 0x77, 0x77, 0x8f, 0xff, 0xff, 0xff, 0xff, 0xff, 0x87, 0x77, 0x77, 0x78, 0xff, 0xff, 0xff,\r
+0x87, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x78, 0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0x00, 0x0f,\r
+0x00, 0x8f, 0x00, 0xff, 0x87, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x78, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0x77, 0x77, 0x77, 0x7f, 0xff, 0xff, 0xff, 0xf8, 0x77, 0x77, 0x77, 0x8f, 0xff, 0xff, 0xff, 0xff, 0xff, 0x87, 0x77, 0x77,\r
+0x78, 0xff, 0xff, 0xff, 0xff, 0x88, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff,\r
+0xff, 0xff, 0x70, 0x08, 0x00, 0x88, 0x00, 0xff, 0x87, 0x77, 0x77, 0x77, 0x88, 0x88, 0x77, 0x77, 0x77, 0x78, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0x77, 0x77, 0x77, 0x7f, 0xff, 0xff, 0xff, 0xf8, 0x77, 0x77, 0x77, 0x8f, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0x87, 0x77, 0x77, 0x78, 0xff, 0xff, 0xff, 0xff, 0xff, 0x88, 0x77, 0x77, 0x77, 0x77, 0x77, 0xff, 0xff, 0xfa, 0xaa,\r
+0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0x70, 0x00, 0x00, 0x70, 0x07, 0xff, 0x87, 0x77, 0x77, 0x77, 0xff, 0xff, 0x77, 0x77,\r
+0x77, 0x77, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x77, 0x77, 0x77, 0x7f, 0xff, 0xff, 0xff, 0xf8, 0x77, 0x77, 0x77, 0x7f,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0x87, 0x77, 0x77, 0x78, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf8, 0x77, 0x77, 0x77, 0x77,\r
+0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0xf8, 0x00, 0x00, 0x00, 0x7f, 0xff, 0x87, 0x77, 0x77, 0x77,\r
+0xff, 0xff, 0xf7, 0x77, 0x77, 0x77, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x77, 0x77, 0x77, 0x7f, 0xff, 0xff, 0xff, 0xff,\r
+0x77, 0x77, 0x77, 0x78, 0xff, 0xff, 0xff, 0xff, 0xf8, 0x77, 0x77, 0x77, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0x87, 0x77, 0x77, 0x77, 0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0xff, 0x80, 0x00, 0x00, 0xff, 0xff,\r
+0x87, 0x77, 0x77, 0x77, 0xff, 0xff, 0xf8, 0x77, 0x77, 0x77, 0x8f, 0xff, 0xff, 0xff, 0xff, 0xff, 0x77, 0x77, 0x77, 0x7f,\r
+0xff, 0xff, 0xff, 0xff, 0x77, 0x77, 0x77, 0x77, 0xff, 0xff, 0xff, 0xff, 0xf7, 0x77, 0x77, 0x77, 0x8f, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0x87, 0x77, 0x77, 0x77, 0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0x87, 0x88,\r
+0x88, 0x8f, 0xff, 0xff, 0x87, 0x77, 0x77, 0x77, 0xff, 0xff, 0xff, 0x77, 0x77, 0x77, 0x8f, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0x77, 0x77, 0x77, 0x7f, 0xff, 0xff, 0xff, 0xff, 0x77, 0x77, 0x77, 0x77, 0xff, 0xff, 0xff, 0xff, 0x87, 0x77, 0x77, 0x77,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x87, 0x77, 0x77, 0x77, 0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff,\r
+0xff, 0xff, 0x00, 0x07, 0xff, 0xff, 0xff, 0xff, 0x87, 0x77, 0x77, 0x77, 0xff, 0xff, 0xff, 0x87, 0x77, 0x77, 0x7f, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0x77, 0x77, 0x77, 0x7f, 0xff, 0xff, 0xff, 0xff, 0x87, 0x77, 0x77, 0x77, 0x8f, 0xff, 0xff, 0xff,\r
+0x77, 0x77, 0x77, 0x77, 0xff, 0xff, 0xf7, 0x88, 0xff, 0xff, 0xff, 0xff, 0x87, 0x77, 0x77, 0x77, 0xff, 0xff, 0xfa, 0xaa,\r
+0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0x80, 0x00, 0xff, 0xff, 0xff, 0xff, 0x87, 0x77, 0x77, 0x77, 0xff, 0xff, 0xff, 0xf7,\r
+0x77, 0x77, 0x78, 0xff, 0xff, 0xff, 0xff, 0xff, 0x77, 0x77, 0x77, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xf8, 0x77, 0x77, 0x77,\r
+0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x78, 0xff, 0xff, 0x87, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x78,\r
+0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0xf7, 0x00, 0x88, 0x88, 0x88, 0xff, 0x87, 0x77, 0x77, 0x77,\r
+0xff, 0xff, 0xff, 0xf8, 0x77, 0x77, 0x77, 0xff, 0xff, 0xff, 0xff, 0xff, 0x77, 0x77, 0x77, 0x7f, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0x87, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x8f, 0xff, 0xff, 0x87, 0x77, 0x77, 0x77, 0x77, 0x77,\r
+0x77, 0x77, 0x77, 0x7f, 0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0x70, 0x00, 0x00, 0x00, 0x00, 0xff,\r
+0x87, 0x77, 0x77, 0x77, 0xff, 0xff, 0xff, 0xf8, 0x77, 0x77, 0x77, 0x8f, 0xff, 0xff, 0xff, 0xff, 0x77, 0x77, 0x77, 0x7f,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xf8, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x78, 0xff, 0xff, 0xff, 0x87, 0x77,\r
+0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0xff, 0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0x70, 0x00,\r
+0x00, 0x00, 0x00, 0xff, 0x87, 0x77, 0x77, 0x77, 0xff, 0xff, 0xff, 0xff, 0x77, 0x77, 0x77, 0x7f, 0xff, 0xff, 0xff, 0xff,\r
+0x77, 0x77, 0x77, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x87, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x8f, 0xff,\r
+0xff, 0xff, 0x87, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x8f, 0xff, 0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff,\r
+0xff, 0xff, 0x70, 0x00, 0x00, 0x00, 0x07, 0xff, 0x88, 0x88, 0x88, 0x88, 0xff, 0xff, 0xff, 0xff, 0x88, 0x88, 0x88, 0x88,\r
+0xff, 0xff, 0xff, 0xff, 0x88, 0x88, 0x88, 0x8f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf8, 0x87, 0x77, 0x77, 0x77,\r
+0x88, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x88, 0x77, 0x77, 0x77, 0x77, 0x88, 0x8f, 0xff, 0xff, 0xff, 0xff, 0xfa, 0xaa,\r
+0xaa, 0xaf, 0xff, 0xff, 0x00, 0x0f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff, 0x00, 0x0f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff, 0x00, 0x0f, 0x70, 0x08, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff, 0x00, 0x07, 0x70, 0x07,\r
+0x88, 0x88, 0x88, 0xff, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88,\r
+0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88,\r
+0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff,\r
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xfa, 0xaa,\r
+0xaa, 0xaf, 0xff, 0xff, 0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r
+0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff, 0xf7, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x70, 0x00, 0x00, 0x00,\r
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r
+0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0x70, 0x08, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0x70, 0x08,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfa, 0xaa,\r
+0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaa, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,\r
+0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,\r
+0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,\r
+0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x0a, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,\r
+0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,\r
+0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,\r
+0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xa0, 0x00, 0xaa, 0xaa, 0xaa,\r
+0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,\r
+0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,\r
+0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x00,\r
+0x00 };\r
+\r
+#define bmpBITMAP_HEIGHT 50\r
+#define bmpBITMAP_WIDTH 128\r
+\r
+#endif\r
--- /dev/null
+#ifndef LCD_MESSAGE_H\r
+#define LCD_MESSAGE_H\r
+\r
+typedef struct\r
+{\r
+ signed char *pcMessage;\r
+} xOLEDMessage;\r
+\r
+#endif /* LCD_MESSAGE_H */\r
--- /dev/null
+/*\r
+ FreeRTOS.org V4.3.0 - Copyright (C) 2003-2007 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS.org distribution.\r
+\r
+ FreeRTOS.org is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS.org is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS.org; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS.org, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section\r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license\r
+ and contact details. Please ensure to read the configuration and relevant\r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+\r
+/*\r
+ * Creates all the demo application tasks, then starts the scheduler. The WEB\r
+ * documentation provides more details of the standard demo application tasks.\r
+ * In addition to the standard demo tasks, the following tasks and tests are\r
+ * defined and/or created within this file:\r
+ *\r
+ * "Fast Interrupt Test" - A high frequency periodic interrupt is generated\r
+ * using a free running timer to demonstrate the use of the\r
+ * configKERNEL_INTERRUPT_PRIORITY configuration constant. The interrupt\r
+ * service routine measures the number of processor clocks that occur between\r
+ * each interrupt - and in so doing measures the jitter in the interrupt timing.\r
+ * The maximum measured jitter time is latched in the ulMaxJitter variable, and\r
+ * displayed on the OLED display by the 'Check' task as described below. The\r
+ * fast interrupt is configured and handled in the timertest.c source file.\r
+ *\r
+ * "OLED" task - the OLED task is a 'gatekeeper' task. It is the only task that\r
+ * is permitted to access the display directly. Other tasks wishing to write a\r
+ * message to the OLED send the message on a queue to the OLED task instead of\r
+ * accessing the OLED themselves. The OLED task just blocks on the queue waiting\r
+ * for messages - waking and displaying the messages as they arrive.\r
+ *\r
+ * "Check" task - This only executes every five seconds but has the highest\r
+ * priority so is guaranteed to get processor time. Its main function is to\r
+ * check that all the standard demo tasks are still operational. Should any\r
+ * unexpected behaviour within a demo task be discovered the 'check' task will\r
+ * write an error to the OLED (via the OLED task). If all the demo tasks are\r
+ * executing with their expected behaviour then the check task writes PASS\r
+ * along with the max jitter time to the OLED (again via the OLED task), as\r
+ * described above.\r
+ *\r
+ */\r
+\r
+\r
+\r
+/* Standard includes. */\r
+#include <stdio.h>\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "Task.h"\r
+#include "queue.h"\r
+#include "semphr.h"\r
+\r
+/* Demo app includes. */\r
+#include "BlockQ.h"\r
+#include "death.h"\r
+#include "integer.h"\r
+#include "blocktim.h"\r
+#include "flash.h"\r
+#include "partest.h"\r
+#include "semtest.h"\r
+#include "pollq.h"\r
+#include "lcd_message.h"\r
+#include "bitmap.h"\r
+\r
+/* Hardware library includes. */\r
+#include "hw_memmap.h"\r
+#include "hw_types.h"\r
+#include "sysctl.h"\r
+#include "gpio.h"\r
+#include "osram128x64x4.h"\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* The time between cycles of the 'check' task. */\r
+#define mainCHECK_DELAY ( ( portTickType ) 5000 / portTICK_RATE_MS )\r
+\r
+/* The check task uses the sprintf function so requires a little more stack too. */\r
+#define mainCHECK_TASK_STACK_SIZE ( configMINIMAL_STACK_SIZE + 50 )\r
+\r
+/* Task priorities. */\r
+#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
+#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 )\r
+#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 )\r
+#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
+#define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 )\r
+#define mainINTEGER_TASK_PRIORITY ( tskIDLE_PRIORITY )\r
+\r
+/* The maximum number of message that can be waiting for display at any one\r
+time. */\r
+#define mainOLED_QUEUE_SIZE ( 3 )\r
+\r
+/* Dimensions the buffer into which the jitter time is written. */\r
+#define mainMAX_MSG_LEN 25\r
+\r
+/* The period of the system clock in nano seconds. This is used to calculate\r
+the jitter time in nano seconds. */\r
+#define mainNS_PER_CLOCK ( ( unsigned portLONG ) ( ( 1.0 / ( double ) configCPU_CLOCK_HZ ) * 1000000000.0 ) )\r
+\r
+/* Constants used when writing strings to the display. */\r
+#define mainCHARACTER_HEIGHT ( 9 )\r
+#define mainMAX_ROWS ( mainCHARACTER_HEIGHT * 7 )\r
+#define mainFULL_SCALE ( 15 )\r
+#define ulSSI_FREQUENCY 1000000\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Checks the status of all the demo tasks then prints a message to the\r
+ * display. The message will be either PASS - an include in brackets the\r
+ * maximum measured jitter time (as described at the to of the file), or a\r
+ * message that describes which of the standard demo tasks an error has been\r
+ * discovered in.\r
+ *\r
+ * Messages are not written directly to the terminal, but passed to vOLEDTask\r
+ * via a queue.\r
+ */\r
+static void vCheckTask( void *pvParameters );\r
+\r
+/*\r
+ * The display is written two by more than one task so is controlled by a\r
+ * 'gatekeeper' task. This is the only task that is actually permitted to\r
+ * access the display directly. Other tasks wanting to display a message send\r
+ * the message to the gatekeeper.\r
+ */\r
+static void vOLEDTask( void *pvParameters );\r
+\r
+/*\r
+ * Configure the hardware for the demo.\r
+ */\r
+static void prvSetupHardware( void );\r
+\r
+/*\r
+ * Configures the high frequency timers - those used to measure the timing\r
+ * jitter while the real time kernel is executing.\r
+ */\r
+extern void vSetupTimer( void );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* The queue used to send messages to the OLED task. */\r
+xQueueHandle xOLEDQueue;\r
+\r
+/* The welcome text. */\r
+const portCHAR * const pcWelcomeMessage = " www.FreeRTOS.org";\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+int main( void )\r
+{\r
+ prvSetupHardware();\r
+\r
+ /* Create the queue used by the OLED task. Messages for display on the OLED\r
+ are received via this queue. */\r
+ xOLEDQueue = xQueueCreate( mainOLED_QUEUE_SIZE, sizeof( xOLEDMessage ) );\r
+\r
+ /* Start the standard demo tasks. */\r
+ vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY );\r
+ vCreateBlockTimeTasks();\r
+ vStartSemaphoreTasks( mainSEM_TEST_PRIORITY );\r
+ vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY );\r
+ vStartIntegerMathTasks( mainINTEGER_TASK_PRIORITY );\r
+\r
+ /* Start the tasks defined within this file/specific to this demo. */\r
+ xTaskCreate( vCheckTask, ( signed portCHAR * ) "Check", mainCHECK_TASK_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL );\r
+ xTaskCreate( vOLEDTask, ( signed portCHAR * ) "OLED", configMINIMAL_STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );\r
+\r
+ /* The suicide tasks must be created last as they need to know how many\r
+ tasks were running prior to their creation in order to ascertain whether\r
+ or not the correct/expected number of tasks are running at any given time. */\r
+ vCreateSuicidalTasks( mainCREATOR_TASK_PRIORITY );\r
+\r
+ /* Configure the high frequency interrupt used to measure the interrupt\r
+ jitter time. */\r
+ vSetupTimer();\r
+ \r
+ /* Start the scheduler. */\r
+ vTaskStartScheduler();\r
+\r
+ /* Will only get here if there was insufficient memory to create the idle\r
+ task. */\r
+ return 0;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void prvSetupHardware( void )\r
+{\r
+ /* Set the clocking to run from the PLL at 50 MHz */\r
+ SysCtlClockSet( SYSCTL_SYSDIV_4 | SYSCTL_USE_PLL | SYSCTL_OSC_MAIN | SYSCTL_XTAL_8MHZ );\r
+ \r
+ /* Enable Port F for Ethernet LEDs\r
+ LED0 Bit 3 Output\r
+ LED1 Bit 2 Output */\r
+ SysCtlPeripheralEnable( SYSCTL_PERIPH_GPIOF );\r
+ GPIODirModeSet( GPIO_PORTF_BASE, (GPIO_PIN_2 | GPIO_PIN_3), GPIO_DIR_MODE_HW );\r
+ GPIOPadConfigSet( GPIO_PORTF_BASE, (GPIO_PIN_2 | GPIO_PIN_3 ), GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD ); \r
+ \r
+ vParTestInitialise();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void vCheckTask( void *pvParameters )\r
+{\r
+portTickType xLastExecutionTime;\r
+xOLEDMessage xMessage;\r
+static portCHAR cPassMessage[ mainMAX_MSG_LEN ];\r
+extern unsigned portLONG ulMaxJitter;\r
+\r
+ xLastExecutionTime = xTaskGetTickCount();\r
+ xMessage.pcMessage = cPassMessage;\r
+ \r
+ for( ;; )\r
+ {\r
+ /* Perform this check every mainCHECK_DELAY milliseconds. */\r
+ vTaskDelayUntil( &xLastExecutionTime, mainCHECK_DELAY );\r
+\r
+ /* Has an error been found in any task? */\r
+\r
+ if( xAreBlockingQueuesStillRunning() != pdTRUE )\r
+ {\r
+ xMessage.pcMessage = "ERROR IN BLOCK Q";\r
+ }\r
+ else if( xAreBlockTimeTestTasksStillRunning() != pdTRUE )\r
+ {\r
+ xMessage.pcMessage = "ERROR IN BLOCK TIME";\r
+ }\r
+ else if( xAreSemaphoreTasksStillRunning() != pdTRUE )\r
+ {\r
+ xMessage.pcMessage = "ERROR IN SEMAPHORE";\r
+ }\r
+ else if( xArePollingQueuesStillRunning() != pdTRUE )\r
+ {\r
+ xMessage.pcMessage = "ERROR IN POLL Q";\r
+ }\r
+ else if( xIsCreateTaskStillRunning() != pdTRUE )\r
+ {\r
+ xMessage.pcMessage = "ERROR IN CREATE";\r
+ }\r
+ else if( xAreIntegerMathsTaskStillRunning() != pdTRUE )\r
+ {\r
+ xMessage.pcMessage = "ERROR IN MATH";\r
+ }\r
+ else\r
+ {\r
+ sprintf( cPassMessage, "PASS [%uns]", ulMaxJitter * mainNS_PER_CLOCK );\r
+ }\r
+\r
+ /* Send the message to the OLED gatekeeper for display. */\r
+ xQueueSend( xOLEDQueue, &xMessage, portMAX_DELAY );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+\r
+\r
+void vOLEDTask( void *pvParameters )\r
+{\r
+xOLEDMessage xMessage;\r
+unsigned portLONG ulY = mainMAX_ROWS;\r
+\r
+ /* Initialise the OLED and display a startup message. */\r
+ OSRAM128x64x4Init( ulSSI_FREQUENCY ); \r
+ \r
+ OSRAM128x64x4StringDraw( " POWERED BY FreeRTOS", 0, 0, mainFULL_SCALE );\r
+ OSRAM128x64x4ImageDraw( pucImage, 0, mainCHARACTER_HEIGHT + 1, bmpBITMAP_WIDTH, bmpBITMAP_HEIGHT );\r
+ \r
+ for( ;; )\r
+ {\r
+ /* Wait for a message to arrive that requires displaying. */\r
+ xQueueReceive( xOLEDQueue, &xMessage, portMAX_DELAY );\r
+ \r
+ /* Write the message on the next available row. */\r
+ ulY += mainCHARACTER_HEIGHT;\r
+ if( ulY >= mainMAX_ROWS )\r
+ {\r
+ ulY = mainCHARACTER_HEIGHT;\r
+ OSRAM128x64x4Clear();\r
+ OSRAM128x64x4StringDraw( pcWelcomeMessage, 0, 0, mainFULL_SCALE ); \r
+ }\r
+\r
+ /* Display the message. */\r
+ OSRAM128x64x4StringDraw( xMessage.pcMessage, 0, ulY, mainFULL_SCALE );\r
+ }\r
+}\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// startup_ewarm.c - Boot code for Stellaris.\r
+//\r
+// Copyright (c) 2006-2007 Luminary Micro, Inc. All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 100 of the Stellaris Ethernet\r
+// Applications Library.\r
+//\r
+//*****************************************************************************\r
+\r
+//*****************************************************************************\r
+//\r
+// Enable the IAR extensions for this source file.\r
+//\r
+//*****************************************************************************\r
+#pragma language=extended\r
+\r
+//*****************************************************************************\r
+//\r
+// Forward declaration of the default fault handlers.\r
+//\r
+//*****************************************************************************\r
+void ResetISR(void);\r
+static void NmiSR(void);\r
+static void FaultISR(void);\r
+static void IntDefaultHandler(void);\r
+\r
+//*****************************************************************************\r
+//\r
+// External declaration for the interrupt handler used by the application.\r
+//\r
+//*****************************************************************************\r
+\r
+\r
+//*****************************************************************************\r
+//\r
+// The entry point for the application.\r
+//\r
+//*****************************************************************************\r
+extern int main(void);\r
+extern void xPortPendSVHandler(void);\r
+extern void xPortSysTickHandler(void);\r
+extern void vEMAC_ISR( void );\r
+extern Timer0IntHandler( void );\r
+\r
+//*****************************************************************************\r
+//\r
+// Reserve space for the system stack.\r
+//\r
+//*****************************************************************************\r
+#ifndef STACK_SIZE\r
+#define STACK_SIZE 64\r
+#endif\r
+static unsigned long pulStack[STACK_SIZE];\r
+\r
+//*****************************************************************************\r
+//\r
+// A union that describes the entries of the vector table. The union is needed\r
+// since the first entry is the stack pointer and the remainder are function\r
+// pointers.\r
+//\r
+//*****************************************************************************\r
+typedef union\r
+{\r
+ void (*pfnHandler)(void);\r
+ unsigned long ulPtr;\r
+}\r
+uVectorEntry;\r
+\r
+//*****************************************************************************\r
+//\r
+// The minimal vector table for a Cortex M3. Note that the proper constructs\r
+// must be placed on this to ensure that it ends up at physical address\r
+// 0x0000.0000.\r
+//\r
+//*****************************************************************************\r
+__root const uVectorEntry g_pfnVectors[] @ "INTVEC" =\r
+{\r
+ { .ulPtr = (unsigned long)pulStack + sizeof(pulStack) },\r
+ // The initial stack pointer\r
+ ResetISR, // The reset handler\r
+ NmiSR, // The NMI handler\r
+ FaultISR, // The hard fault handler\r
+ IntDefaultHandler, // The MPU fault handler\r
+ IntDefaultHandler, // The bus fault handler\r
+ IntDefaultHandler, // The usage fault handler\r
+ 0, // Reserved\r
+ 0, // Reserved\r
+ 0, // Reserved\r
+ 0, // Reserved\r
+ IntDefaultHandler, // SVCall handler\r
+ IntDefaultHandler, // Debug monitor handler\r
+ 0, // Reserved\r
+ xPortPendSVHandler, // The PendSV handler\r
+ xPortSysTickHandler, // The SysTick handler\r
+ IntDefaultHandler, // GPIO Port A\r
+ IntDefaultHandler, // GPIO Port B\r
+ IntDefaultHandler, // GPIO Port C\r
+ IntDefaultHandler, // GPIO Port D\r
+ IntDefaultHandler, // GPIO Port E\r
+ IntDefaultHandler, // UART0 Rx and Tx\r
+ IntDefaultHandler, // UART1 Rx and Tx\r
+ IntDefaultHandler, // SSI Rx and Tx\r
+ IntDefaultHandler, // I2C Master and Slave\r
+ IntDefaultHandler, // PWM Fault\r
+ IntDefaultHandler, // PWM Generator 0\r
+ IntDefaultHandler, // PWM Generator 1\r
+ IntDefaultHandler, // PWM Generator 2\r
+ IntDefaultHandler, // Quadrature Encoder\r
+ IntDefaultHandler, // ADC Sequence 0\r
+ IntDefaultHandler, // ADC Sequence 1\r
+ IntDefaultHandler, // ADC Sequence 2\r
+ IntDefaultHandler, // ADC Sequence 3\r
+ IntDefaultHandler, // Watchdog timer\r
+ Timer0IntHandler, // Timer 0 subtimer A\r
+ IntDefaultHandler, // Timer 0 subtimer B\r
+ IntDefaultHandler, // Timer 1 subtimer A\r
+ IntDefaultHandler, // Timer 1 subtimer B\r
+ IntDefaultHandler, // Timer 2 subtimer A\r
+ IntDefaultHandler, // Timer 2 subtimer B\r
+ IntDefaultHandler, // Analog Comparator 0\r
+ IntDefaultHandler, // Analog Comparator 1\r
+ IntDefaultHandler, // Analog Comparator 2\r
+ IntDefaultHandler, // System Control (PLL, OSC, BO)\r
+ IntDefaultHandler, // FLASH Control\r
+ IntDefaultHandler, // GPIO Port F\r
+ IntDefaultHandler, // GPIO Port G\r
+ IntDefaultHandler, // GPIO Port H\r
+ IntDefaultHandler, // UART2 Rx and Tx\r
+ IntDefaultHandler, // SSI1 Rx and Tx\r
+ IntDefaultHandler, // Timer 3 subtimer A\r
+ IntDefaultHandler, // Timer 3 subtimer B\r
+ IntDefaultHandler, // I2C1 Master and Slave\r
+ IntDefaultHandler, // Quadrature Encoder 1\r
+ IntDefaultHandler, // CAN0\r
+ IntDefaultHandler, // CAN1\r
+ IntDefaultHandler, // CAN2\r
+ IntDefaultHandler, // Ethernet\r
+ IntDefaultHandler // Power Island\r
+};\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are constructs created by the linker, indicating where the\r
+// the "data" and "bss" segments reside in memory. The initializers for the\r
+// for the "data" segment resides immediately following the "text" segment.\r
+//\r
+//*****************************************************************************\r
+#pragma segment="DATA_ID"\r
+#pragma segment="DATA_I"\r
+#pragma segment="DATA_Z"\r
+\r
+//*****************************************************************************\r
+//\r
+// This is the code that gets called when the processor first starts execution\r
+// following a reset event. Only the absolutely necessary set is performed,\r
+// after which the application supplied entry() routine is called. Any fancy\r
+// actions (such as making decisions based on the reset cause register, and\r
+// resetting the bits in that register) are left solely in the hands of the\r
+// application.\r
+//\r
+//*****************************************************************************\r
+void\r
+ResetISR(void)\r
+{\r
+ unsigned long *pulSrc, *pulDest, *pulEnd;\r
+\r
+ //\r
+ // Copy the data segment initializers from flash to SRAM.\r
+ //\r
+ pulSrc = __segment_begin("DATA_ID");\r
+ pulDest = __segment_begin("DATA_I");\r
+ pulEnd = __segment_end("DATA_I");\r
+ while(pulDest < pulEnd)\r
+ {\r
+ *pulDest++ = *pulSrc++;\r
+ }\r
+\r
+ //\r
+ // Zero fill the bss segment.\r
+ //\r
+ pulDest = __segment_begin("DATA_Z");\r
+ pulEnd = __segment_end("DATA_Z");\r
+ while(pulDest < pulEnd)\r
+ {\r
+ *pulDest++ = 0;\r
+ }\r
+\r
+ //\r
+ // Call the application's entry point.\r
+ //\r
+ main();\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+// This is the code that gets called when the processor receives a NMI. This\r
+// simply enters an infinite loop, preserving the system state for examination\r
+// by a debugger.\r
+//\r
+//*****************************************************************************\r
+static void\r
+NmiSR(void)\r
+{\r
+ //\r
+ // Enter an infinite loop.\r
+ //\r
+ while(1)\r
+ {\r
+ }\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+// This is the code that gets called when the processor receives a fault\r
+// interrupt. This simply enters an infinite loop, preserving the system state\r
+// for examination by a debugger.\r
+//\r
+//*****************************************************************************\r
+static void\r
+FaultISR(void)\r
+{\r
+ //\r
+ // Enter an infinite loop.\r
+ //\r
+ while(1)\r
+ {\r
+ }\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+// This is the code that gets called when the processor receives an unexpected\r
+// interrupt. This simply enters an infinite loop, preserving the system state\r
+// for examination by a debugger.\r
+//\r
+//*****************************************************************************\r
+static void\r
+IntDefaultHandler(void)\r
+{\r
+ //\r
+ // Go into an infinite loop.\r
+ //\r
+ while(1)\r
+ {\r
+ }\r
+}\r
--- /dev/null
+/*\r
+ FreeRTOS.org V4.3.0 - Copyright (C) 2003-2007 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS.org distribution.\r
+\r
+ FreeRTOS.org is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS.org is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS.org; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS.org, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section\r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license\r
+ and contact details. Please ensure to read the configuration and relevant\r
+ port sections of the online documentation.\r
+\r
+ Also see http://www.SafeRTOS.com for an IEC 61508 compliant version along\r
+ with commercial development and support options.\r
+ ***************************************************************************\r
+*/\r
+\r
+/* High speed timer test as described in main.c. */\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+\r
+/* Library includes. */\r
+#include "hw_ints.h"\r
+#include "hw_memmap.h"\r
+#include "hw_types.h"\r
+#include "interrupt.h"\r
+#include "sysctl.h"\r
+#include "LMI_timer.h"\r
+\r
+/* The set frequency of the interrupt. Deviations from this are measured as\r
+the jitter. */\r
+#define timerINTERRUPT_FREQUENCY ( 20000UL )\r
+\r
+/* The expected time between each of the timer interrupts - if the jitter was\r
+zero. */\r
+#define timerEXPECTED_DIFFERENCE_VALUE ( configCPU_CLOCK_HZ / timerINTERRUPT_FREQUENCY )\r
+\r
+/* The highest available interrupt priority. */\r
+#define timerHIGHEST_PRIORITY ( 0 )\r
+\r
+/* Misc defines. */\r
+#define timerMAX_32BIT_VALUE ( 0xffffffffUL )\r
+#define timerTIMER_1_COUNT_VALUE ( * ( ( unsigned long * ) ( TIMER1_BASE + 0x48 ) ) )\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Interrupt handler in which the jitter is measured. */\r
+void Timer0IntHandler( void );\r
+\r
+/* Stores the value of the maximum recorded jitter between interrupts. */\r
+unsigned portLONG ulMaxJitter = 0;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void vSetupTimer( void )\r
+{\r
+unsigned long ulFrequency;\r
+\r
+ /* Timer zero is used to generate the interrupts, and timer 1 is used\r
+ to measure the jitter. */\r
+ SysCtlPeripheralEnable( SYSCTL_PERIPH_TIMER0 );\r
+ SysCtlPeripheralEnable( SYSCTL_PERIPH_TIMER1 );\r
+ TimerConfigure( TIMER0_BASE, TIMER_CFG_32_BIT_PER );\r
+ TimerConfigure( TIMER1_BASE, TIMER_CFG_32_BIT_PER );\r
+ \r
+ /* Set the timer interrupt to be above the kernel - highest. */\r
+ IntPrioritySet( INT_TIMER0A, timerHIGHEST_PRIORITY );\r
+\r
+ /* Just used to measure time. */\r
+ TimerLoadSet(TIMER1_BASE, TIMER_A, timerMAX_32BIT_VALUE );\r
+ \r
+ /* The rate at which the timer will interrupt. */\r
+ ulFrequency = configCPU_CLOCK_HZ / timerINTERRUPT_FREQUENCY; \r
+ TimerLoadSet( TIMER0_BASE, TIMER_A, ulFrequency );\r
+ IntEnable( INT_TIMER0A );\r
+ TimerIntEnable( TIMER0_BASE, TIMER_TIMA_TIMEOUT );\r
+\r
+ /* Enable both timers. */ \r
+ TimerEnable( TIMER0_BASE, TIMER_A );\r
+ TimerEnable( TIMER1_BASE, TIMER_A );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void Timer0IntHandler( void )\r
+{\r
+unsigned portLONG ulDifference, ulCurrentCount;\r
+static portLONG ulMaxDifference = 0, ulLastCount = 0;\r
+\r
+ /* We use the timer 1 counter value to measure the clock cycles between\r
+ the timer 0 interrupts. */\r
+ ulCurrentCount = timerTIMER_1_COUNT_VALUE;\r
+\r
+ if( ulCurrentCount < ulLastCount )\r
+ { \r
+ /* How many times has timer 1 counted since the last interrupt? */\r
+ ulDifference = ulLastCount - ulCurrentCount;\r
+ \r
+ /* Is this the largest difference we have measured yet? */\r
+ if( ulDifference > ulMaxDifference )\r
+ {\r
+ ulMaxDifference = ulDifference;\r
+ ulMaxJitter = ulMaxDifference - timerEXPECTED_DIFFERENCE_VALUE;\r
+ }\r
+ }\r
+ \r
+ ulLastCount = ulCurrentCount;\r
+\r
+ TimerIntClear( TIMER0_BASE, TIMER_TIMA_TIMEOUT );\r
+}\r
+\r
+\r
+\r
+\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS.org V4.3.0 - Copyright (C) 2003-2007 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS.org distribution.\r
+\r
+ FreeRTOS.org is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS.org is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS.org; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS.org, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section\r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license\r
+ and contact details. Please ensure to read the configuration and relevant\r
+ port sections of the online documentation.\r
+\r
+ Also see http://www.SafeRTOS.com for an IEC 61508 compliant version along\r
+ with commercial development and support options.\r
+ ***************************************************************************\r
+*/\r
+\r
+#ifndef FREERTOS_CONFIG_H\r
+#define FREERTOS_CONFIG_H\r
+\r
+/*-----------------------------------------------------------\r
+ * Application specific definitions.\r
+ *\r
+ * These definitions should be adjusted for your particular hardware and\r
+ * application requirements.\r
+ *\r
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE\r
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.\r
+ *----------------------------------------------------------*/\r
+\r
+#define configUSE_PREEMPTION 1\r
+#define configUSE_IDLE_HOOK 0\r
+#define configUSE_TICK_HOOK 0\r
+#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 50000000 )\r
+#define configTICK_RATE_HZ ( ( portTickType ) 1000 )\r
+#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 70 )\r
+#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 12000 ) )\r
+#define configMAX_TASK_NAME_LEN ( 12 )\r
+#define configUSE_TRACE_FACILITY 1\r
+#define configUSE_16_BIT_TICKS 0\r
+#define configIDLE_SHOULD_YIELD 0\r
+#define configUSE_CO_ROUTINES 0\r
+\r
+#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 5 )\r
+#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )\r
+\r
+/* Set the following definitions to 1 to include the API function, or zero\r
+to exclude the API function. */\r
+\r
+#define INCLUDE_vTaskPrioritySet 1\r
+#define INCLUDE_uxTaskPriorityGet 0\r
+#define INCLUDE_vTaskDelete 1\r
+#define INCLUDE_vTaskCleanUpResources 0\r
+#define INCLUDE_vTaskSuspend 1\r
+#define INCLUDE_vTaskDelayUntil 1\r
+#define INCLUDE_vTaskDelay 1\r
+\r
+\r
+#define configKERNEL_INTERRUPT_PRIORITY 255\r
+\r
+\r
+#endif /* FREERTOS_CONFIG_H */\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// LM3Sxxx.h - Header file for Luminary Micro LM3Sxxx microcontrollers.\r
+//\r
+// Copyright (c) 2006-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __LM3SXXX_H__\r
+#define __LM3SXXX_H__\r
+\r
+#include "hw_adc.h"\r
+#include "hw_comp.h"\r
+#include "hw_flash.h"\r
+#include "hw_gpio.h"\r
+#include "hw_i2c.h"\r
+#include "hw_ints.h"\r
+#include "hw_memmap.h"\r
+#include "hw_nvic.h"\r
+#include "hw_pwm.h"\r
+#include "hw_qei.h"\r
+#include "hw_ssi.h"\r
+#include "hw_sysctl.h"\r
+#include "hw_timer.h"\r
+#include "hw_types.h"\r
+#include "hw_uart.h"\r
+#include "hw_watchdog.h"\r
+#include "adc.h"\r
+#include "comp.h"\r
+#include "cpu.h"\r
+#include "debug.h"\r
+#include "flash.h"\r
+#include "gpio.h"\r
+#include "i2c.h"\r
+#include "interrupt.h"\r
+#include "pwm.h"\r
+#include "qei.h"\r
+#include "ssi.h"\r
+#include "sysctl.h"\r
+#include "systick.h"\r
+#include "timer.h"\r
+#include "uart.h"\r
+#include "watchdog.h"\r
+\r
+#endif // __LM3SXXX_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// LM3Sxxxx.h - Header file for Luminary Micro LM3Sxxxx microcontrollers.\r
+//\r
+// Copyright (c) 2006-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __LM3SXXXX_H__\r
+#define __LM3SXXXX_H__\r
+\r
+#include "hw_adc.h"\r
+#include "hw_can.h"\r
+#include "hw_comp.h"\r
+#include "hw_ethernet.h"\r
+#include "hw_flash.h"\r
+#include "hw_gpio.h"\r
+#include "hw_hibernate.h"\r
+#include "hw_i2c.h"\r
+#include "hw_ints.h"\r
+#include "hw_memmap.h"\r
+#include "hw_nvic.h"\r
+#include "hw_pwm.h"\r
+#include "hw_qei.h"\r
+#include "hw_ssi.h"\r
+#include "hw_sysctl.h"\r
+#include "hw_timer.h"\r
+#include "hw_types.h"\r
+#include "hw_uart.h"\r
+#include "hw_watchdog.h"\r
+#include "adc.h"\r
+#include "can.h"\r
+#include "comp.h"\r
+#include "cpu.h"\r
+#include "debug.h"\r
+#include "ethernet.h"\r
+#include "flash.h"\r
+#include "gpio.h"\r
+#include "hibernate.h"\r
+#include "i2c.h"\r
+#include "interrupt.h"\r
+#include "pwm.h"\r
+#include "qei.h"\r
+#include "ssi.h"\r
+#include "sysctl.h"\r
+#include "systick.h"\r
+#include "timer.h"\r
+#include "uart.h"\r
+#include "watchdog.h"\r
+\r
+#endif // __LM3SXXXX_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// flash.h - Prototypes for the flash driver.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __FLASH_H__\r
+#define __FLASH_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to FlashProtectSet(), and returned by\r
+// FlashProtectGet().\r
+//\r
+//*****************************************************************************\r
+typedef enum\r
+{\r
+ FlashReadWrite, // Flash can be read and written\r
+ FlashReadOnly, // Flash can only be read\r
+ FlashExecuteOnly // Flash can only be executed\r
+}\r
+tFlashProtection;\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+extern unsigned long FlashUsecGet(void);\r
+extern void FlashUsecSet(unsigned long ulClocks);\r
+extern long FlashErase(unsigned long ulAddress);\r
+extern long FlashProgram(unsigned long *pulData, unsigned long ulAddress,\r
+ unsigned long ulCount);\r
+extern tFlashProtection FlashProtectGet(unsigned long ulAddress);\r
+extern long FlashProtectSet(unsigned long ulAddress,\r
+ tFlashProtection eProtect);\r
+extern long FlashProtectSave(void);\r
+extern long FlashUserGet(unsigned long *pulUser0, unsigned long *pulUser1);\r
+extern long FlashUserSet(unsigned long ulUser0, unsigned long ulUser1);\r
+extern long FlashUserSave(void);\r
+extern void FlashIntRegister(void (*pfnHandler)(void));\r
+extern void FlashIntUnregister(void);\r
+extern void FlashIntEnable(unsigned long ulIntFlags);\r
+extern void FlashIntDisable(unsigned long ulIntFlags);\r
+extern unsigned long FlashIntGetStatus(tBoolean bMasked);\r
+extern void FlashIntClear(unsigned long ulIntFlags);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __FLASH_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// timer.h - Prototypes for the timer module\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __TIMER_H__\r
+#define __TIMER_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to TimerConfigure as the ulConfig parameter.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_CFG_32_BIT_OS 0x00000001 // 32-bit one-shot timer\r
+#define TIMER_CFG_32_BIT_PER 0x00000002 // 32-bit periodic timer\r
+#define TIMER_CFG_32_RTC 0x01000000 // 32-bit RTC timer\r
+#define TIMER_CFG_16_BIT_PAIR 0x04000000 // Two 16-bit timers\r
+#define TIMER_CFG_A_ONE_SHOT 0x00000001 // Timer A one-shot timer\r
+#define TIMER_CFG_A_PERIODIC 0x00000002 // Timer A periodic timer\r
+#define TIMER_CFG_A_CAP_COUNT 0x00000003 // Timer A event counter\r
+#define TIMER_CFG_A_CAP_TIME 0x00000007 // Timer A event timer\r
+#define TIMER_CFG_A_PWM 0x0000000A // Timer A PWM output\r
+#define TIMER_CFG_B_ONE_SHOT 0x00000100 // Timer B one-shot timer\r
+#define TIMER_CFG_B_PERIODIC 0x00000200 // Timer B periodic timer\r
+#define TIMER_CFG_B_CAP_COUNT 0x00000300 // Timer B event counter\r
+#define TIMER_CFG_B_CAP_TIME 0x00000700 // Timer B event timer\r
+#define TIMER_CFG_B_PWM 0x00000A00 // Timer B PWM output\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to TimerIntEnable, TimerIntDisable, and\r
+// TimerIntClear as the ulIntFlags parameter, and returned from TimerIntStatus.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_CAPB_EVENT 0x00000400 // CaptureB event interrupt\r
+#define TIMER_CAPB_MATCH 0x00000200 // CaptureB match interrupt\r
+#define TIMER_TIMB_TIMEOUT 0x00000100 // TimerB time out interrupt\r
+#define TIMER_RTC_MATCH 0x00000008 // RTC interrupt mask\r
+#define TIMER_CAPA_EVENT 0x00000004 // CaptureA event interrupt\r
+#define TIMER_CAPA_MATCH 0x00000002 // CaptureA match interrupt\r
+#define TIMER_TIMA_TIMEOUT 0x00000001 // TimerA time out interrupt\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to TimerControlEvent as the ulEvent parameter.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_EVENT_POS_EDGE 0x00000000 // Count positive edges\r
+#define TIMER_EVENT_NEG_EDGE 0x00000404 // Count negative edges\r
+#define TIMER_EVENT_BOTH_EDGES 0x00000C0C // Count both edges\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to most of the timer APIs as the ulTimer\r
+// parameter.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_A 0x000000ff // Timer A\r
+#define TIMER_B 0x0000ff00 // Timer B\r
+#define TIMER_BOTH 0x0000ffff // Timer Both\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+extern void TimerEnable(unsigned long ulBase, unsigned long ulTimer);\r
+extern void TimerDisable(unsigned long ulBase, unsigned long ulTimer);\r
+extern void TimerConfigure(unsigned long ulBase, unsigned long ulConfig);\r
+extern void TimerControlLevel(unsigned long ulBase, unsigned long ulTimer,\r
+ tBoolean bInvert);\r
+extern void TimerControlTrigger(unsigned long ulBase, unsigned long ulTimer,\r
+ tBoolean bEnable);\r
+extern void TimerControlEvent(unsigned long ulBase, unsigned long ulTimer,\r
+ unsigned long ulEvent);\r
+extern void TimerControlStall(unsigned long ulBase, unsigned long ulTimer,\r
+ tBoolean bStall);\r
+extern void TimerRTCEnable(unsigned long ulBase);\r
+extern void TimerRTCDisable(unsigned long ulBase);\r
+extern void TimerPrescaleSet(unsigned long ulBase, unsigned long ulTimer,\r
+ unsigned long ulValue);\r
+extern unsigned long TimerPrescaleGet(unsigned long ulBase,\r
+ unsigned long ulTimer);\r
+extern void TimerPrescaleMatchSet(unsigned long ulBase, unsigned long ulTimer,\r
+ unsigned long ulValue);\r
+extern unsigned long TimerPrescaleMatchGet(unsigned long ulBase,\r
+ unsigned long ulTimer);\r
+extern void TimerLoadSet(unsigned long ulBase, unsigned long ulTimer,\r
+ unsigned long ulValue);\r
+extern unsigned long TimerLoadGet(unsigned long ulBase, unsigned long ulTimer);\r
+extern unsigned long TimerValueGet(unsigned long ulBase,\r
+ unsigned long ulTimer);\r
+extern void TimerMatchSet(unsigned long ulBase, unsigned long ulTimer,\r
+ unsigned long ulValue);\r
+extern unsigned long TimerMatchGet(unsigned long ulBase,\r
+ unsigned long ulTimer);\r
+extern void TimerIntRegister(unsigned long ulBase, unsigned long ulTimer,\r
+ void (*pfnHandler)(void));\r
+extern void TimerIntUnregister(unsigned long ulBase, unsigned long ulTimer);\r
+extern void TimerIntEnable(unsigned long ulBase, unsigned long ulIntFlags);\r
+extern void TimerIntDisable(unsigned long ulBase, unsigned long ulIntFlags);\r
+extern unsigned long TimerIntStatus(unsigned long ulBase, tBoolean bMasked);\r
+extern void TimerIntClear(unsigned long ulBase, unsigned long ulIntFlags);\r
+extern void TimerQuiesce(unsigned long ulBase);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __TIMER_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// adc.h - ADC headers for using the ADC driver functions.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __ADC_H__\r
+#define __ADC_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to ADCSequenceConfigure as the ulTrigger\r
+// parameter.\r
+//\r
+//*****************************************************************************\r
+#define ADC_TRIGGER_PROCESSOR 0x00000000 // Processor event\r
+#define ADC_TRIGGER_COMP0 0x00000001 // Analog comparator 0 event\r
+#define ADC_TRIGGER_COMP1 0x00000002 // Analog comparator 1 event\r
+#define ADC_TRIGGER_COMP2 0x00000003 // Analog comparator 2 event\r
+#define ADC_TRIGGER_EXTERNAL 0x00000004 // External event\r
+#define ADC_TRIGGER_TIMER 0x00000005 // Timer event\r
+#define ADC_TRIGGER_PWM0 0x00000006 // PWM0 event\r
+#define ADC_TRIGGER_PWM1 0x00000007 // PWM1 event\r
+#define ADC_TRIGGER_PWM2 0x00000008 // PWM2 event\r
+#define ADC_TRIGGER_ALWAYS 0x0000000F // Always event\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to ADCSequenceStepConfigure as the ulConfig\r
+// parameter.\r
+//\r
+//*****************************************************************************\r
+#define ADC_CTL_TS 0x00000080 // Temperature sensor select\r
+#define ADC_CTL_IE 0x00000040 // Interrupt enable\r
+#define ADC_CTL_END 0x00000020 // Sequence end select\r
+#define ADC_CTL_D 0x00000010 // Differential select\r
+#define ADC_CTL_CH0 0x00000000 // Input channel 0\r
+#define ADC_CTL_CH1 0x00000001 // Input channel 1\r
+#define ADC_CTL_CH2 0x00000002 // Input channel 2\r
+#define ADC_CTL_CH3 0x00000003 // Input channel 3\r
+#define ADC_CTL_CH4 0x00000004 // Input channel 4\r
+#define ADC_CTL_CH5 0x00000005 // Input channel 5\r
+#define ADC_CTL_CH6 0x00000006 // Input channel 6\r
+#define ADC_CTL_CH7 0x00000007 // Input channel 7\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+extern void ADCIntRegister(unsigned long ulBase, unsigned long ulSequenceNum,\r
+ void (*pfnHandler)(void));\r
+extern void ADCIntUnregister(unsigned long ulBase,\r
+ unsigned long ulSequenceNum);\r
+extern void ADCIntDisable(unsigned long ulBase, unsigned long ulSequenceNum);\r
+extern void ADCIntEnable(unsigned long ulBase, unsigned long ulSequenceNum);\r
+extern unsigned long ADCIntStatus(unsigned long ulBase,\r
+ unsigned long ulSequenceNum,\r
+ tBoolean bMasked);\r
+extern void ADCIntClear(unsigned long ulBase, unsigned long ulSequenceNum);\r
+extern void ADCSequenceEnable(unsigned long ulBase,\r
+ unsigned long ulSequenceNum);\r
+extern void ADCSequenceDisable(unsigned long ulBase,\r
+ unsigned long ulSequenceNum);\r
+extern void ADCSequenceConfigure(unsigned long ulBase,\r
+ unsigned long ulSequenceNum,\r
+ unsigned long ulTrigger,\r
+ unsigned long ulPriority);\r
+extern void ADCSequenceStepConfigure(unsigned long ulBase,\r
+ unsigned long ulSequenceNum,\r
+ unsigned long ulStep,\r
+ unsigned long ulConfig);\r
+extern long ADCSequenceOverflow(unsigned long ulBase,\r
+ unsigned long ulSequenceNum);\r
+extern void ADCSequenceOverflowClear(unsigned long ulBase,\r
+ unsigned long ulSequenceNum);\r
+extern long ADCSequenceUnderflow(unsigned long ulBase,\r
+ unsigned long ulSequenceNum);\r
+extern void ADCSequenceUnderflowClear(unsigned long ulBase,\r
+ unsigned long ulSequenceNum);\r
+extern long ADCSequenceDataGet(unsigned long ulBase,\r
+ unsigned long ulSequenceNum,\r
+ unsigned long *pulBuffer);\r
+extern void ADCProcessorTrigger(unsigned long ulBase,\r
+ unsigned long ulSequenceNum);\r
+extern void ADCSoftwareOversampleConfigure(unsigned long ulBase,\r
+ unsigned long ulSequenceNum,\r
+ unsigned long ulFactor);\r
+extern void ADCSoftwareOversampleStepConfigure(unsigned long ulBase,\r
+ unsigned long ulSequenceNum,\r
+ unsigned long ulStep,\r
+ unsigned long ulConfig);\r
+extern void ADCSoftwareOversampleDataGet(unsigned long ulBase,\r
+ unsigned long ulSequenceNum,\r
+ unsigned long *pulBuffer,\r
+ unsigned long ulCount);\r
+extern void ADCHardwareOversampleConfigure(unsigned long ulBase,\r
+ unsigned long ulFactor);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __ADC_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// can.h - Defines and Macros for the CAN controller.\r
+//\r
+// Copyright (c) 2006-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __CAN_H__\r
+#define __CAN_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! \addtogroup can_api\r
+//! @{\r
+//\r
+//*****************************************************************************\r
+\r
+//*****************************************************************************\r
+//\r
+// Miscellaneous defines for Message ID Types\r
+//\r
+//*****************************************************************************\r
+\r
+//*****************************************************************************\r
+//\r
+//! These are the flags used by the tCANMsgObject variable when calling the\r
+//! the CANMessageSet() and CANMessageGet() APIs.\r
+//\r
+//*****************************************************************************\r
+typedef enum\r
+{\r
+ //\r
+ //! This indicates that transmit interrupts should be enabled, or are\r
+ //! enabled.\r
+ //\r
+ MSG_OBJ_TX_INT_ENABLE = 0x00000001,\r
+\r
+ //\r
+ //! This indicates that receive interrupts should be enabled or are\r
+ //! enabled.\r
+ //\r
+ MSG_OBJ_RX_INT_ENABLE = 0x00000002,\r
+\r
+ //\r
+ //! This indicates that a message object will use or is using an extended\r
+ //! identifier.\r
+ //\r
+ MSG_OBJ_EXTENDED_ID = 0x00000004,\r
+\r
+ //\r
+ //! This indicates that a message object will use or is using filtering\r
+ //! based on the object's message Identifier.\r
+ //\r
+ MSG_OBJ_USE_ID_FILTER = 0x00000008,\r
+\r
+ //\r
+ //! This indicates that new data was available in the message object.\r
+ //\r
+ MSG_OBJ_NEW_DATA = 0x00000080,\r
+\r
+ //\r
+ //! This indicates that data was lost since this message object was last\r
+ //! read.\r
+ //\r
+ MSG_OBJ_DATA_LOST = 0x00000100,\r
+\r
+ //\r
+ //! This indicates that a message object will use or is using filtering\r
+ //! based on the direction of the transfer. If the direction filtering is\r
+ //! used then ID filtering must also be enabled.\r
+ //\r
+ MSG_OBJ_USE_DIR_FILTER = (0x00000010 | MSG_OBJ_USE_ID_FILTER),\r
+\r
+ //\r
+ //! This indicates that a message object will use or is using message\r
+ //! identifier filtering based of the the extended identifier.\r
+ //! If the extended identifier filtering is used then ID filtering must\r
+ //! also be enabled.\r
+ //\r
+ MSG_OBJ_USE_EXT_FILTER = (0x00000020 | MSG_OBJ_USE_ID_FILTER),\r
+\r
+ //\r
+ //! This indicates that a message object is a remote frame.\r
+ //\r
+ MSG_OBJ_REMOTE_FRAME = 0x00000040,\r
+\r
+ //\r
+ //! This indicates that a message object has no flags set.\r
+ //\r
+ MSG_OBJ_NO_FLAGS = 0x00000000\r
+}\r
+tCANObjFlags;\r
+\r
+//*****************************************************************************\r
+//\r
+//! This define is used with the #tCANObjFlags enumerated values to allow\r
+//! checking only status flags and not configuration flags.\r
+//\r
+//*****************************************************************************\r
+#define MSG_OBJ_STATUS_MASK (MSG_OBJ_NEW_DATA | MSG_OBJ_DATA_LOST)\r
+\r
+//*****************************************************************************\r
+//\r
+//! This structure used for encapsulating all the items associated with a CAN\r
+//! message object in the CAN controller.\r
+//\r
+//*****************************************************************************\r
+typedef struct\r
+{\r
+ //\r
+ //! The CAN message identifier used for 11 or 29 bit identifiers.\r
+ //\r
+ unsigned long ulMsgID;\r
+\r
+ //\r
+ //! The message identifier mask used when identifier filtering is enabled.\r
+ //\r
+ unsigned long ulMsgIDMask;\r
+\r
+ //\r
+ //! This value holds various status flags and settings specified by\r
+ //! tCANObjFlags.\r
+ //\r
+ unsigned long ulFlags;\r
+\r
+ //\r
+ //! This value is the number of bytes of data in the message object.\r
+ //\r
+ unsigned long ulMsgLen;\r
+\r
+ //\r
+ //! This is a pointer to the message object's data.\r
+ //\r
+ unsigned char *pucMsgData;\r
+}\r
+tCANMsgObject;\r
+\r
+//*****************************************************************************\r
+//\r
+//! This structure is used for encapsulating the values associated with setting\r
+//! up the bit timing for a CAN controller. The structure is used when calling\r
+//! the CANGetBitTiming and CANSetBitTiming functions.\r
+//\r
+//*****************************************************************************\r
+typedef struct\r
+{\r
+ //\r
+ //! This value holds the sum of the Synchronization, Propagation, and Phase\r
+ //! Buffer 1 segments, measured in time quanta. The valid values for this\r
+ //! setting range from 2 to 16.\r
+ //\r
+ unsigned int uSyncPropPhase1Seg;\r
+\r
+ //\r
+ //! This value holds the Phase Buffer 2 segment in time quanta. The valid\r
+ //! values for this setting range from 1 to 8.\r
+ //\r
+ unsigned int uPhase2Seg;\r
+\r
+ //\r
+ //! This value holds the Resynchronization Jump Width in time quanta. The\r
+ //! valid values for this setting range from 1 to 4.\r
+ //\r
+ unsigned int uSJW;\r
+\r
+ //\r
+ //! This value holds the CAN_CLK divider used to determine time quanta.\r
+ //! The valid values for this setting range from 1 to 1023.\r
+ //\r
+ unsigned int uQuantumPrescaler;\r
+\r
+}\r
+tCANBitClkParms;\r
+\r
+//*****************************************************************************\r
+//\r
+//! This data type is used to identify the interrupt status register. This is\r
+//! used when calling the a CANIntStatus() function.\r
+//\r
+//*****************************************************************************\r
+typedef enum\r
+{\r
+ //\r
+ //! Read the CAN interrupt status information.\r
+ //\r
+ CAN_INT_STS_CAUSE,\r
+\r
+ //\r
+ //! Read a message object's interrupt status.\r
+ //\r
+ CAN_INT_STS_OBJECT\r
+}\r
+tCANIntStsReg;\r
+\r
+//*****************************************************************************\r
+//\r
+//! This data type is used to identify which of the several status registers\r
+//! to read when calling the CANStatusGet() function.\r
+//\r
+//*****************************************************************************\r
+typedef enum\r
+{\r
+ //\r
+ //! Read the full CAN controller status.\r
+ //\r
+ CAN_STS_CONTROL,\r
+\r
+ //\r
+ //! Read the full 32 bit mask of message objects with a transmit request\r
+ //! set.\r
+ //\r
+ CAN_STS_TXREQUEST,\r
+\r
+ //\r
+ //! Read the full 32 bit mask of message objects with a new data available.\r
+ //\r
+ CAN_STS_NEWDAT,\r
+\r
+ //\r
+ //! Read the full 32 bit mask of message objects that are enabled.\r
+ //\r
+ CAN_STS_MSGVAL\r
+}\r
+tCANStsReg;\r
+\r
+//*****************************************************************************\r
+//\r
+//! These definitions are used to specify interrupt sources to CANIntEnable()\r
+//! and CANIntDisable().\r
+//\r
+//*****************************************************************************\r
+typedef enum\r
+{\r
+ //\r
+ //! This flag is used to allow a CAN controller to generate error\r
+ //! interrupts.\r
+ //\r
+ CAN_INT_ERROR = 0x00000008,\r
+\r
+ //\r
+ //! This flag is used to allow a CAN controller to generate status\r
+ //! interrupts.\r
+ //\r
+ CAN_INT_STATUS = 0x00000004,\r
+\r
+ //\r
+ //! This flag is used to allow a CAN controller to generate any CAN\r
+ //! interrupts. If this is not set then no interrupts will be generated by\r
+ //! the CAN controller.\r
+ //\r
+ CAN_INT_MASTER = 0x00000002\r
+}\r
+tCANIntFlags;\r
+\r
+//*****************************************************************************\r
+//\r
+//! This definition is used to determine the type of message object that will\r
+//! be set up via a call to the CANMessageSet() API.\r
+//\r
+//*****************************************************************************\r
+typedef enum\r
+{\r
+ //\r
+ //! Transmit message object.\r
+ //\r
+ MSG_OBJ_TYPE_TX,\r
+\r
+ //\r
+ //! Transmit remote request message object\r
+ //\r
+ MSG_OBJ_TYPE_TX_REMOTE,\r
+\r
+ //\r
+ //! Receive message object.\r
+ //\r
+ MSG_OBJ_TYPE_RX,\r
+\r
+ //\r
+ //! Receive remote request message object.\r
+ //\r
+ MSG_OBJ_TYPE_RX_REMOTE,\r
+\r
+ //\r
+ //! Remote frame receive remote, with auto-transmit message object.\r
+ //\r
+ MSG_OBJ_TYPE_RXTX_REMOTE\r
+}\r
+tMsgObjType;\r
+\r
+//*****************************************************************************\r
+//\r
+//! The following enumeration contains all error or status indicators that\r
+//! can be returned when calling the CANStatusGet() API.\r
+//\r
+//*****************************************************************************\r
+typedef enum\r
+{\r
+ //\r
+ //! CAN controller has entered a Bus Off state.\r
+ //\r
+ CAN_STATUS_BUS_OFF = 0x00000080,\r
+\r
+ //\r
+ //! CAN controller error level has reached warning level.\r
+ //\r
+ CAN_STATUS_EWARN = 0x00000040,\r
+\r
+ //\r
+ //! CAN controller error level has reached error passive level.\r
+ //\r
+ CAN_STATUS_EPASS = 0x00000020,\r
+\r
+ //\r
+ //! A message was received successfully since the last read of this status.\r
+ //\r
+ CAN_STATUS_RXOK = 0x00000010,\r
+\r
+ //\r
+ //! A message was transmitted successfully since the last read of this\r
+ //! status.\r
+ //\r
+ CAN_STATUS_TXOK = 0x00000008,\r
+\r
+ //\r
+ //! This is the mask for the last error code field.\r
+ //\r
+ CAN_STATUS_LEC_MSK = 0x00000007,\r
+\r
+ //\r
+ //! There was no error.\r
+ //\r
+ CAN_STATUS_LEC_NONE = 0x00000000,\r
+\r
+ //\r
+ //! A bit stuffing error has occurred.\r
+ //\r
+ CAN_STATUS_LEC_STUFF = 0x00000001,\r
+\r
+ //\r
+ //! A formatting error has occurred.\r
+ //\r
+ CAN_STATUS_LEC_FORM = 0x00000002,\r
+\r
+ //\r
+ //! An acknowledge error has occurred.\r
+ //\r
+ CAN_STATUS_LEC_ACK = 0x00000003,\r
+\r
+ //\r
+ //! The bus remained a bit level of 1 for longer than is allowed.\r
+ //\r
+ CAN_STATUS_LEC_BIT1 = 0x00000004,\r
+\r
+ //\r
+ //! The bus remained a bit level of 0 for longer than is allowed.\r
+ //\r
+ CAN_STATUS_LEC_BIT0 = 0x00000005,\r
+\r
+ //\r
+ //! A CRC error has occurred.\r
+ //\r
+ CAN_STATUS_LEC_CRC = 0x00000006,\r
+\r
+ //\r
+ //! This is the mask for the CAN Last Error Code (LEC).\r
+ //\r
+ CAN_STATUS_LEC_MASK = 0x00000007\r
+}\r
+tCANStatusCtrl;\r
+\r
+//*****************************************************************************\r
+//\r
+// API Function prototypes\r
+//\r
+//*****************************************************************************\r
+extern void CANInit(unsigned long ulBase);\r
+extern void CANEnable(unsigned long ulBase);\r
+extern void CANDisable(unsigned long ulBase);\r
+extern void CANSetBitTiming(unsigned long ulBase, tCANBitClkParms *pClkParms);\r
+extern void CANGetBitTiming(unsigned long ulBase, tCANBitClkParms *pClkParms);\r
+extern unsigned long CANReadReg(unsigned long ulRegAddress);\r
+extern void CANWriteReg(unsigned long ulRegAddress, unsigned long ulRegValue);\r
+extern void CANMessageSet(unsigned long ulBase, unsigned long ulObjID,\r
+ tCANMsgObject *pMsgObject, tMsgObjType eMsgType);\r
+extern void CANMessageGet(unsigned long ulBase, unsigned long ulObjID,\r
+ tCANMsgObject *pMsgObject, tBoolean bClrPendingInt);\r
+extern unsigned long CANStatusGet(unsigned long ulBase, tCANStsReg eStatusReg);\r
+extern void CANMessageClear(unsigned long ulBase, unsigned long ulObjID);\r
+extern void CANIntRegister(unsigned long ulBase, void (*pfnHandler)(void));\r
+extern void CANIntEnable(unsigned long ulBase, unsigned long ulIntFlags);\r
+extern void CANIntDisable(unsigned long ulBase, unsigned long ulIntFlags);\r
+extern void CANIntClear(unsigned long ulBase, unsigned long ulIntClr);\r
+extern unsigned long CANIntStatus(unsigned long ulBase,\r
+ tCANIntStsReg eIntStsReg);\r
+extern tBoolean CANRetryGet(unsigned long ulBase);\r
+extern void CANRetrySet(unsigned long ulBase, tBoolean bAutoRetry);\r
+extern tBoolean CANErrCntrGet(unsigned long ulBase, unsigned long *pulRxCount,\r
+ unsigned long *pulTxCount);\r
+extern long CANGetIntNumber(unsigned long ulBase);\r
+extern void CANReadDataReg(unsigned char *pucData, unsigned long *pulRegister,\r
+ int iSize);\r
+extern void CANWriteDataReg(unsigned char *pucData, unsigned long *pulRegister,\r
+ int iSize);\r
+\r
+//*****************************************************************************\r
+//\r
+// Close the Doxygen group.\r
+//! @}\r
+//\r
+//*****************************************************************************\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __CAN_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// comp.h - Prototypes for the analog comparator driver.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __COMP_H__\r
+#define __COMP_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to ComparatorConfigure() as the ulConfig\r
+// parameter. For each group (i.e. COMP_TRIG_xxx, COMP_INT_xxx, etc.), one of\r
+// the values may be selected and ORed together will values from the other\r
+// groups.\r
+//\r
+//*****************************************************************************\r
+#define COMP_TRIG_NONE 0x00000000 // No ADC trigger\r
+#define COMP_TRIG_HIGH 0x00000880 // Trigger when high\r
+#define COMP_TRIG_LOW 0x00000800 // Trigger when low\r
+#define COMP_TRIG_FALL 0x00000820 // Trigger on falling edge\r
+#define COMP_TRIG_RISE 0x00000840 // Trigger on rising edge\r
+#define COMP_TRIG_BOTH 0x00000860 // Trigger on both edges\r
+#define COMP_INT_HIGH 0x00000010 // Interrupt when high\r
+#define COMP_INT_LOW 0x00000000 // Interrupt when low\r
+#define COMP_INT_FALL 0x00000004 // Interrupt on falling edge\r
+#define COMP_INT_RISE 0x00000008 // Interrupt on rising edge\r
+#define COMP_INT_BOTH 0x0000000C // Interrupt on both edges\r
+#define COMP_ASRCP_PIN 0x00000000 // Dedicated Comp+ pin\r
+#define COMP_ASRCP_PIN0 0x00000200 // Comp0+ pin\r
+#define COMP_ASRCP_REF 0x00000400 // Internal voltage reference\r
+#ifndef DEPRECATED\r
+#define COMP_OUTPUT_NONE 0x00000000 // No comparator output\r
+#endif\r
+#define COMP_OUTPUT_NORMAL 0x00000000 // Comparator output normal\r
+#define COMP_OUTPUT_INVERT 0x00000002 // Comparator output inverted\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to ComparatorSetRef() as the ulRef parameter.\r
+//\r
+//*****************************************************************************\r
+#define COMP_REF_OFF 0x00000000 // Turn off the internal reference\r
+#define COMP_REF_0V 0x00000300 // Internal reference of 0V\r
+#define COMP_REF_0_1375V 0x00000301 // Internal reference of 0.1375V\r
+#define COMP_REF_0_275V 0x00000302 // Internal reference of 0.275V\r
+#define COMP_REF_0_4125V 0x00000303 // Internal reference of 0.4125V\r
+#define COMP_REF_0_55V 0x00000304 // Internal reference of 0.55V\r
+#define COMP_REF_0_6875V 0x00000305 // Internal reference of 0.6875V\r
+#define COMP_REF_0_825V 0x00000306 // Internal reference of 0.825V\r
+#define COMP_REF_0_928125V 0x00000201 // Internal reference of 0.928125V\r
+#define COMP_REF_0_9625V 0x00000307 // Internal reference of 0.9625V\r
+#define COMP_REF_1_03125V 0x00000202 // Internal reference of 1.03125V\r
+#define COMP_REF_1_134375V 0x00000203 // Internal reference of 1.134375V\r
+#define COMP_REF_1_1V 0x00000308 // Internal reference of 1.1V\r
+#define COMP_REF_1_2375V 0x00000309 // Internal reference of 1.2375V\r
+#define COMP_REF_1_340625V 0x00000205 // Internal reference of 1.340625V\r
+#define COMP_REF_1_375V 0x0000030A // Internal reference of 1.375V\r
+#define COMP_REF_1_44375V 0x00000206 // Internal reference of 1.44375V\r
+#define COMP_REF_1_5125V 0x0000030B // Internal reference of 1.5125V\r
+#define COMP_REF_1_546875V 0x00000207 // Internal reference of 1.546875V\r
+#define COMP_REF_1_65V 0x0000030C // Internal reference of 1.65V\r
+#define COMP_REF_1_753125V 0x00000209 // Internal reference of 1.753125V\r
+#define COMP_REF_1_7875V 0x0000030D // Internal reference of 1.7875V\r
+#define COMP_REF_1_85625V 0x0000020A // Internal reference of 1.85625V\r
+#define COMP_REF_1_925V 0x0000030E // Internal reference of 1.925V\r
+#define COMP_REF_1_959375V 0x0000020B // Internal reference of 1.959375V\r
+#define COMP_REF_2_0625V 0x0000030F // Internal reference of 2.0625V\r
+#define COMP_REF_2_165625V 0x0000020D // Internal reference of 2.165625V\r
+#define COMP_REF_2_26875V 0x0000020E // Internal reference of 2.26875V\r
+#define COMP_REF_2_371875V 0x0000020F // Internal reference of 2.371875V\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+extern void ComparatorConfigure(unsigned long ulBase, unsigned long ulComp,\r
+ unsigned long ulConfig);\r
+extern void ComparatorRefSet(unsigned long ulBase, unsigned long ulRef);\r
+extern tBoolean ComparatorValueGet(unsigned long ulBase, unsigned long ulComp);\r
+extern void ComparatorIntRegister(unsigned long ulBase, unsigned long ulComp,\r
+ void (*pfnHandler)(void));\r
+extern void ComparatorIntUnregister(unsigned long ulBase,\r
+ unsigned long ulComp);\r
+extern void ComparatorIntEnable(unsigned long ulBase, unsigned long ulComp);\r
+extern void ComparatorIntDisable(unsigned long ulBase, unsigned long ulComp);\r
+extern tBoolean ComparatorIntStatus(unsigned long ulBase, unsigned long ulComp,\r
+ tBoolean bMasked);\r
+extern void ComparatorIntClear(unsigned long ulBase, unsigned long ulComp);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __COMP_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// cpu.h - Prototypes for the CPU instruction wrapper functions.\r
+//\r
+// Copyright (c) 2006-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __CPU_H__\r
+#define __CPU_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes.\r
+//\r
+//*****************************************************************************\r
+extern void CPUcpsid(void);\r
+extern void CPUcpsie(void);\r
+extern void CPUwfi(void);\r
+\r
+#endif // __CPU_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// debug.h - Macros for assisting debug of the driver library.\r
+//\r
+// Copyright (c) 2006-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __DEBUG_H__\r
+#define __DEBUG_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototype for the function that is called when an invalid argument is passed\r
+// to an API. This is only used when doing a DEBUG build.\r
+//\r
+//*****************************************************************************\r
+extern void __error__(char *pcFilename, unsigned long ulLine);\r
+\r
+//*****************************************************************************\r
+//\r
+// The ASSERT macro, which does the actual assertion checking. Typically, this\r
+// will be for procedure arguments.\r
+//\r
+//*****************************************************************************\r
+#ifdef DEBUG\r
+#define ASSERT(expr) { \\r
+ if(!(expr)) \\r
+ { \\r
+ __error__(__FILE__, __LINE__); \\r
+ } \\r
+ }\r
+#else\r
+#define ASSERT(expr)\r
+#endif\r
+\r
+#endif // __DEBUG_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// ethernet.h - Defines and Macros for the ethernet module.\r
+//\r
+// Copyright (c) 2006-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __ETHERNET_H__\r
+#define __ETHERNET_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to EthernetConfigSet as the ulConfig value, and\r
+// returned from EthernetConfigGet.\r
+//\r
+//*****************************************************************************\r
+#define ETH_CFG_RX_BADCRCDIS 0x000800 // Disable RX BAD CRC Packets\r
+#define ETH_CFG_RX_PRMSEN 0x000400 // Enable RX Promiscuous\r
+#define ETH_CFG_RX_AMULEN 0x000200 // Enable RX Multicast\r
+#define ETH_CFG_TX_DPLXEN 0x000010 // Enable TX Duplex Mode\r
+#define ETH_CFG_TX_CRCEN 0x000004 // Enable TX CRC Generation\r
+#define ETH_CFG_TX_PADEN 0x000002 // Enable TX Padding\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to EthernetIntEnable, EthernetIntDisable, and\r
+// EthernetIntClear as the ulIntFlags parameter, and returned from\r
+// EthernetIntStatus.\r
+//\r
+//*****************************************************************************\r
+#define ETH_INT_PHY 0x040 // PHY Event/Interrupt\r
+#define ETH_INT_MDIO 0x020 // Management Transaction\r
+#define ETH_INT_RXER 0x010 // RX Error\r
+#define ETH_INT_RXOF 0x008 // RX FIFO Overrun\r
+#define ETH_INT_TX 0x004 // TX Complete\r
+#define ETH_INT_TXER 0x002 // TX Error\r
+#define ETH_INT_RX 0x001 // RX Complete\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define values that can be passed as register addresses to\r
+// EthernetPHYRead and EthernetPHYWrite.\r
+//\r
+//*****************************************************************************\r
+#define PHY_MR0 0 // Control\r
+#define PHY_MR1 1 // Status\r
+#define PHY_MR2 2 // PHY Identifier 1\r
+#define PHY_MR3 3 // PHY Identifier 2\r
+#define PHY_MR4 4 // Auto-Neg. Advertisement\r
+#define PHY_MR5 5 // Auto-Neg. Link Partner Ability\r
+#define PHY_MR6 6 // Auto-Neg. Expansion\r
+ // 7-15 Reserved/Not Implemented\r
+#define PHY_MR16 16 // Vendor Specific\r
+#define PHY_MR17 17 // Interrupt Control/Status\r
+#define PHY_MR18 18 // Diagnostic Register\r
+#define PHY_MR19 19 // Transceiver Control\r
+ // 20-22 Reserved\r
+#define PHY_MR23 23 // LED Configuration Register\r
+#define PHY_MR24 24 // MDI/MDIX Control Register\r
+ // 25-31 Reserved/Not Implemented\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define bit fields in the ETH_MR0 register\r
+//\r
+//*****************************************************************************\r
+#define PHY_MR0_RESET 0x8000 // Reset the PHY\r
+#define PHY_MR0_LOOPBK 0x4000 // TXD to RXD Loopback\r
+#define PHY_MR0_SPEEDSL 0x2000 // Speed Selection\r
+#define PHY_MR0_SPEEDSL_10 0x0000 // Speed Selection 10BASE-T\r
+#define PHY_MR0_SPEEDSL_100 0x2000 // Speed Selection 100BASE-T\r
+#define PHY_MR0_ANEGEN 0x1000 // Auto-Negotiation Enable\r
+#define PHY_MR0_PWRDN 0x0800 // Power Down\r
+#define PHY_MR0_RANEG 0x0200 // Restart Auto-Negotiation\r
+#define PHY_MR0_DUPLEX 0x0100 // Enable full duplex\r
+#define PHY_MR0_DUPLEX_HALF 0x0000 // Enable half duplex mode\r
+#define PHY_MR0_DUPLEX_FULL 0x0100 // Enable full duplex mode\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define bit fields in the ETH_MR1 register\r
+//\r
+//*****************************************************************************\r
+#define PHY_MR1_ANEGC 0x0020 // Auto-Negotiate Complete\r
+#define PHY_MR1_RFAULT 0x0010 // Remove Fault Detected\r
+#define PHY_MR1_LINK 0x0004 // Link Established\r
+#define PHY_MR1_JAB 0x0002 // Jabber Condition Detected\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define bit fields in the ETH_MR17 register\r
+//\r
+//*****************************************************************************\r
+#define PHY_MR17_RXER_IE 0x4000 // Enable Receive Error Interrupt\r
+#define PHY_MR17_LSCHG_IE 0x0400 // Enable Link Status Change Int.\r
+#define PHY_MR17_ANEGCOMP_IE 0x0100 // Enable Auto-Negotiate Cmpl. Int.\r
+#define PHY_MR17_RXER_INT 0x0040 // Receive Error Interrupt\r
+#define PHY_MR17_LSCHG_INT 0x0004 // Link Status Change Interrupt\r
+#define PHY_MR17_ANEGCOMP_INT 0x0001 // Auto-Negotiate Complete Int.\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define bit fields in the ETH_MR18 register\r
+//\r
+//*****************************************************************************\r
+#define PHY_MR18_ANEGF 0x1000 // Auto-Negotiate Failed\r
+#define PHY_MR18_DPLX 0x0800 // Duplex Mode Negotiated\r
+#define PHY_MR18_DPLX_HALF 0x0000 // Half Duplex Mode Negotiated\r
+#define PHY_MR18_DPLX_FULL 0x0800 // Full Duplex Mode Negotiated\r
+#define PHY_MR18_RATE 0x0400 // Rate Negotiated\r
+#define PHY_MR18_RATE_10 0x0000 // Rate Negotiated is 10BASE-T\r
+#define PHY_MR18_RATE_100 0x0400 // Rate Negotiated is 100BASE-TX\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define bit fields in the ETH_MR23 register\r
+//\r
+//*****************************************************************************\r
+#define PHY_MR23_LED1 0x00f0 // LED1 Configuration\r
+#define PHY_MR23_LED1_LINK 0x0000 // LED1 is Link Status\r
+#define PHY_MR23_LED1_RXTX 0x0010 // LED1 is RX or TX Activity\r
+#define PHY_MR23_LED1_TX 0x0020 // LED1 is TX Activity\r
+#define PHY_MR23_LED1_RX 0x0030 // LED1 is RX Activity\r
+#define PHY_MR23_LED1_COL 0x0040 // LED1 is RX Activity\r
+#define PHY_MR23_LED1_100 0x0050 // LED1 is RX Activity\r
+#define PHY_MR23_LED1_10 0x0060 // LED1 is RX Activity\r
+#define PHY_MR23_LED1_DUPLEX 0x0070 // LED1 is RX Activity\r
+#define PHY_MR23_LED1_LINKACT 0x0080 // LED1 is Link Status + Activity\r
+#define PHY_MR23_LED0 0x000f // LED0 Configuration\r
+#define PHY_MR23_LED0_LINK 0x0000 // LED0 is Link Status\r
+#define PHY_MR23_LED0_RXTX 0x0001 // LED0 is RX or TX Activity\r
+#define PHY_MR23_LED0_TX 0x0002 // LED0 is TX Activity\r
+#define PHY_MR23_LED0_RX 0x0003 // LED0 is RX Activity\r
+#define PHY_MR23_LED0_COL 0x0004 // LED0 is RX Activity\r
+#define PHY_MR23_LED0_100 0x0005 // LED0 is RX Activity\r
+#define PHY_MR23_LED0_10 0x0006 // LED0 is RX Activity\r
+#define PHY_MR23_LED0_DUPLEX 0x0007 // LED0 is RX Activity\r
+#define PHY_MR23_LED0_LINKACT 0x0008 // LED0 is Link Status + Activity\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define bit fields in the ETH_MR24 register\r
+//\r
+//*****************************************************************************\r
+#define PHY_MR24_MDIX 0x0020 // Auto-Switching Configuration\r
+#define PHY_MR24_MDIX_NORMAL 0x0000 // Auto-Switching in passthrough\r
+#define PHY_MR23_MDIX_CROSSOVER 0x0020 // Auto-Switching in crossover\r
+\r
+//*****************************************************************************\r
+//\r
+// Helper Macros for Ethernet Processing\r
+//\r
+//*****************************************************************************\r
+//\r
+// htonl/ntohl - big endian/little endian byte swapping macros for\r
+// 32-bit (long) values\r
+//\r
+//*****************************************************************************\r
+#ifndef htonl\r
+ #define htonl(a) \\r
+ ((((a) >> 24) & 0x000000ff) | \\r
+ (((a) >> 8) & 0x0000ff00) | \\r
+ (((a) << 8) & 0x00ff0000) | \\r
+ (((a) << 24) & 0xff000000))\r
+#endif\r
+\r
+#ifndef ntohl\r
+ #define ntohl(a) htonl((a))\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// htons/ntohs - big endian/little endian byte swapping macros for\r
+// 16-bit (short) values\r
+//\r
+//*****************************************************************************\r
+#ifndef htons\r
+ #define htons(a) \\r
+ ((((a) >> 8) & 0x00ff) | \\r
+ (((a) << 8) & 0xff00))\r
+#endif\r
+\r
+#ifndef ntohs\r
+ #define ntohs(a) htons((a))\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// API Function prototypes\r
+//\r
+//*****************************************************************************\r
+extern void EthernetInit(unsigned long ulBase);\r
+extern void EthernetConfigSet(unsigned long ulBase, unsigned long ulConfig);\r
+extern unsigned long EthernetConfigGet(unsigned long ulBase);\r
+extern void EthernetMACAddrSet(unsigned long ulBase,\r
+ unsigned char *pucMACAddr);\r
+extern void EthernetMACAddrGet(unsigned long ulBase,\r
+ unsigned char *pucMACAddr);\r
+extern void EthernetEnable(unsigned long ulBase);\r
+extern void EthernetDisable(unsigned long ulBase);\r
+extern tBoolean EthernetPacketAvail(unsigned long ulBase);\r
+extern tBoolean EthernetSpaceAvail(unsigned long ulBase);\r
+extern long EthernetPacketNonBlockingGet(unsigned long ulBase,\r
+ unsigned char *pucBuf,\r
+ long lBufLen);\r
+extern long EthernetPacketGet(unsigned long ulBase, unsigned char *pucBuf,\r
+ long lBufLen);\r
+extern long EthernetPacketNonBlockingPut(unsigned long ulBase,\r
+ unsigned char *pucBuf,\r
+ long lBufLen);\r
+extern long EthernetPacketPut(unsigned long ulBase, unsigned char *pucBuf,\r
+ long lBufLen);\r
+extern void EthernetIntRegister(unsigned long ulBase,\r
+ void (*pfnHandler)(void));\r
+extern void EthernetIntUnregister(unsigned long ulBase);\r
+extern void EthernetIntEnable(unsigned long ulBase, unsigned long ulIntFlags);\r
+extern void EthernetIntDisable(unsigned long ulBase, unsigned long ulIntFlags);\r
+extern unsigned long EthernetIntStatus(unsigned long ulBase, tBoolean bMasked);\r
+extern void EthernetIntClear(unsigned long ulBase, unsigned long ulIntFlags);\r
+extern void EthernetPHYWrite(unsigned long ulBase, unsigned char ucRegAddr,\r
+ unsigned long ulData);\r
+extern unsigned long EthernetPHYRead(unsigned long ulBase,\r
+ unsigned char ucRegAddr);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __ETHERNET_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// gpio.h - Defines and Macros for GPIO API.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __GPIO_H__\r
+#define __GPIO_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// The following values define the bit field for the ucPins argument to several\r
+// of the APIs.\r
+//\r
+//*****************************************************************************\r
+#define GPIO_PIN_0 0x00000001 // GPIO pin 0\r
+#define GPIO_PIN_1 0x00000002 // GPIO pin 1\r
+#define GPIO_PIN_2 0x00000004 // GPIO pin 2\r
+#define GPIO_PIN_3 0x00000008 // GPIO pin 3\r
+#define GPIO_PIN_4 0x00000010 // GPIO pin 4\r
+#define GPIO_PIN_5 0x00000020 // GPIO pin 5\r
+#define GPIO_PIN_6 0x00000040 // GPIO pin 6\r
+#define GPIO_PIN_7 0x00000080 // GPIO pin 7\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to GPIODirModeSet as the ulPinIO parameter, and\r
+// returned from GPIODirModeGet.\r
+//\r
+//*****************************************************************************\r
+#define GPIO_DIR_MODE_IN 0x00000000 // Pin is a GPIO input\r
+#define GPIO_DIR_MODE_OUT 0x00000001 // Pin is a GPIO output\r
+#define GPIO_DIR_MODE_HW 0x00000002 // Pin is a peripheral function\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to GPIOIntTypeSet as the ulIntType parameter, and\r
+// returned from GPIOIntTypeGet.\r
+//\r
+//*****************************************************************************\r
+#define GPIO_FALLING_EDGE 0x00000000 // Interrupt on falling edge\r
+#define GPIO_RISING_EDGE 0x00000004 // Interrupt on rising edge\r
+#define GPIO_BOTH_EDGES 0x00000001 // Interrupt on both edges\r
+#define GPIO_LOW_LEVEL 0x00000002 // Interrupt on low level\r
+#define GPIO_HIGH_LEVEL 0x00000007 // Interrupt on high level\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to GPIOPadConfigSet as the ulStrength parameter,\r
+// and returned by GPIOPadConfigGet in the *pulStrength parameter.\r
+//\r
+//*****************************************************************************\r
+#define GPIO_STRENGTH_2MA 0x00000001 // 2mA drive strength\r
+#define GPIO_STRENGTH_4MA 0x00000002 // 4mA drive strength\r
+#define GPIO_STRENGTH_8MA 0x00000004 // 8mA drive strength\r
+#define GPIO_STRENGTH_8MA_SC 0x0000000C // 8mA drive with slew rate control\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to GPIOPadConfigSet as the ulPadType parameter,\r
+// and returned by GPIOPadConfigGet in the *pulPadType parameter.\r
+//\r
+//*****************************************************************************\r
+#define GPIO_PIN_TYPE_STD 0x00000008 // Push-pull\r
+#define GPIO_PIN_TYPE_STD_WPU 0x0000000A // Push-pull with weak pull-up\r
+#define GPIO_PIN_TYPE_STD_WPD 0x0000000C // Push-pull with weak pull-down\r
+#define GPIO_PIN_TYPE_OD 0x00000009 // Open-drain\r
+#define GPIO_PIN_TYPE_OD_WPU 0x0000000B // Open-drain with weak pull-up\r
+#define GPIO_PIN_TYPE_OD_WPD 0x0000000D // Open-drain with weak pull-down\r
+#define GPIO_PIN_TYPE_ANALOG 0x00000000 // Analog comparator\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+extern void GPIODirModeSet(unsigned long ulPort, unsigned char ucPins,\r
+ unsigned long ulPinIO);\r
+extern unsigned long GPIODirModeGet(unsigned long ulPort, unsigned char ucPin);\r
+extern void GPIOIntTypeSet(unsigned long ulPort, unsigned char ucPins,\r
+ unsigned long ulIntType);\r
+extern unsigned long GPIOIntTypeGet(unsigned long ulPort, unsigned char ucPin);\r
+extern void GPIOPadConfigSet(unsigned long ulPort, unsigned char ucPins,\r
+ unsigned long ulStrength,\r
+ unsigned long ulPadType);\r
+extern void GPIOPadConfigGet(unsigned long ulPort, unsigned char ucPin,\r
+ unsigned long *pulStrength,\r
+ unsigned long *pulPadType);\r
+extern void GPIOPinIntEnable(unsigned long ulPort, unsigned char ucPins);\r
+extern void GPIOPinIntDisable(unsigned long ulPort, unsigned char ucPins);\r
+extern long GPIOPinIntStatus(unsigned long ulPort, tBoolean bMasked);\r
+extern void GPIOPinIntClear(unsigned long ulPort, unsigned char ucPins);\r
+extern void GPIOPortIntRegister(unsigned long ulPort,\r
+ void (*pfIntHandler)(void));\r
+extern void GPIOPortIntUnregister(unsigned long ulPort);\r
+extern long GPIOPinRead(unsigned long ulPort, unsigned char ucPins);\r
+extern void GPIOPinWrite(unsigned long ulPort, unsigned char ucPins,\r
+ unsigned char ucVal);\r
+extern void GPIOPinTypeComparator(unsigned long ulPort, unsigned char ucPins);\r
+extern void GPIOPinTypeI2C(unsigned long ulPort, unsigned char ucPins);\r
+extern void GPIOPinTypePWM(unsigned long ulPort, unsigned char ucPins);\r
+extern void GPIOPinTypeQEI(unsigned long ulPort, unsigned char ucPins);\r
+extern void GPIOPinTypeSSI(unsigned long ulPort, unsigned char ucPins);\r
+extern void GPIOPinTypeTimer(unsigned long ulPort, unsigned char ucPins);\r
+extern void GPIOPinTypeUART(unsigned long ulPort, unsigned char ucPins);\r
+extern void GPIOPinTypeCAN(unsigned long ulPort, unsigned char ucPins);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __GPIO_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hibernate.h - API definition for the Hibernation module.\r
+//\r
+// Copyright (c) 2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HIBERNATE_H__\r
+#define __HIBERNATE_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Macros needed for selecting the clock source for HibernateClockSelect()\r
+//\r
+//*****************************************************************************\r
+#define HIBERNATE_CLOCK_SEL_RAW 0x04\r
+#define HIBERNATE_CLOCK_SEL_DIV128 0x00\r
+\r
+//*****************************************************************************\r
+//\r
+// Macros need to configure wake events for HibernateWakeSet()\r
+//\r
+//*****************************************************************************\r
+#define HIBERNATE_WAKE_PIN 0x10\r
+#define HIBERNATE_WAKE_RTC 0x08\r
+\r
+//*****************************************************************************\r
+//\r
+// Macros needed to configure low battery detect for HibernateLowBatSet()\r
+//\r
+//*****************************************************************************\r
+#define HIBERNATE_LOW_BAT_DETECT 0x20\r
+#define HIBERNATE_LOW_BAT_ABORT 0xA0\r
+\r
+//*****************************************************************************\r
+//\r
+// Macros defining interrupt source bits for the interrupt functions.\r
+//\r
+//*****************************************************************************\r
+#define HIBERNATE_INT_PIN_WAKE 0x08\r
+#define HIBERNATE_INT_LOW_BAT 0x04\r
+#define HIBERNATE_INT_RTC_MATCH_0 0x01\r
+#define HIBERNATE_INT_RTC_MATCH_1 0x02\r
+\r
+//*****************************************************************************\r
+//\r
+// API Function prototypes\r
+//\r
+//*****************************************************************************\r
+extern void HibernateEnable(void);\r
+extern void HibernateDisable(void);\r
+extern void HibernateClockSelect(unsigned long ulClockInput);\r
+extern void HibernateRTCEnable(void);\r
+extern void HibernateRTCDisable(void);\r
+extern void HibernateWakeSet(unsigned long ulWakeFlags);\r
+extern unsigned long HibernateWakeGet(void);\r
+extern void HibernateLowBatSet(unsigned long ulLowBatFlags);\r
+extern unsigned long HibernateLowBatGet(void);\r
+extern void HibernateRTCSet(unsigned long ulRTCValue);\r
+extern unsigned long HibernateRTCGet(void);\r
+extern void HibernateRTCMatch0Set(unsigned long ulMatch);\r
+extern unsigned long HibernateRTCMatch0Get(void);\r
+extern void HibernateRTCMatch1Set(unsigned long ulMatch);\r
+extern unsigned long HibernateRTCMatch1Get(void);\r
+extern void HibernateRTCTrimSet(unsigned long ulTrim);\r
+extern unsigned long HibernateRTCTrimGet(void);\r
+extern void HibernateDataSet(unsigned long *pulData, unsigned long ulCount);\r
+extern void HibernateDataGet(unsigned long *pulData, unsigned long ulCount);\r
+extern void HibernateRequest(void);\r
+extern void HibernateIntEnable(unsigned long ulIntFlags);\r
+extern void HibernateIntDisable(unsigned long ulIntFlags);\r
+extern void HibernateIntRegister(void (*pfnHandler)(void));\r
+extern void HibernateIntUnregister(void);\r
+extern unsigned long HibernateIntStatus(tBoolean bMasked);\r
+extern void HibernateIntClear(unsigned long ulIntFlags);\r
+extern unsigned int HibernateIsActive(void);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __HIBERNATE_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_adc.h - Macros used when accessing the ADC hardware.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_ADC_H__\r
+#define __HW_ADC_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the offsets of the ADC registers.\r
+//\r
+//*****************************************************************************\r
+#define ADC_O_ACTSS 0x00000000 // Active sample register\r
+#define ADC_O_RIS 0x00000004 // Raw interrupt status register\r
+#define ADC_O_IM 0x00000008 // Interrupt mask register\r
+#define ADC_O_ISC 0x0000000C // Interrupt status/clear register\r
+#define ADC_O_OSTAT 0x00000010 // Overflow status register\r
+#define ADC_O_EMUX 0x00000014 // Event multiplexer select reg.\r
+#define ADC_O_USTAT 0x00000018 // Underflow status register\r
+#define ADC_O_SSPRI 0x00000020 // Channel priority register\r
+#define ADC_O_PSSI 0x00000028 // Processor sample initiate reg.\r
+#define ADC_O_SAC 0x00000030 // Sample Averaging Control reg.\r
+#define ADC_O_SSMUX0 0x00000040 // Multiplexer select 0 register\r
+#define ADC_O_SSCTL0 0x00000044 // Sample sequence control 0 reg.\r
+#define ADC_O_SSFIFO0 0x00000048 // Result FIFO 0 register\r
+#define ADC_O_SSFSTAT0 0x0000004C // FIFO 0 status register\r
+#define ADC_O_SSMUX1 0x00000060 // Multiplexer select 1 register\r
+#define ADC_O_SSCTL1 0x00000064 // Sample sequence control 1 reg.\r
+#define ADC_O_SSFIFO1 0x00000068 // Result FIFO 1 register\r
+#define ADC_O_SSFSTAT1 0x0000006C // FIFO 1 status register\r
+#define ADC_O_SSMUX2 0x00000080 // Multiplexer select 2 register\r
+#define ADC_O_SSCTL2 0x00000084 // Sample sequence control 2 reg.\r
+#define ADC_O_SSFIFO2 0x00000088 // Result FIFO 2 register\r
+#define ADC_O_SSFSTAT2 0x0000008C // FIFO 2 status register\r
+#define ADC_O_SSMUX3 0x000000A0 // Multiplexer select 3 register\r
+#define ADC_O_SSCTL3 0x000000A4 // Sample sequence control 3 reg.\r
+#define ADC_O_SSFIFO3 0x000000A8 // Result FIFO 3 register\r
+#define ADC_O_SSFSTAT3 0x000000AC // FIFO 3 status register\r
+#define ADC_O_TMLB 0x00000100 // Test mode loopback register\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the offsets of the ADC sequence registers.\r
+//\r
+//*****************************************************************************\r
+#define ADC_O_SEQ 0x00000040 // Offset to the first sequence\r
+#define ADC_O_SEQ_STEP 0x00000020 // Increment to the next sequence\r
+#define ADC_O_X_SSMUX 0x00000000 // Multiplexer select register\r
+#define ADC_O_X_SSCTL 0x00000004 // Sample sequence control register\r
+#define ADC_O_X_SSFIFO 0x00000008 // Result FIFO register\r
+#define ADC_O_X_SSFSTAT 0x0000000C // FIFO status register\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the ADC_ACTSS register.\r
+//\r
+//*****************************************************************************\r
+#define ADC_ACTSS_ASEN3 0x00000008 // Sample sequence 3 enable\r
+#define ADC_ACTSS_ASEN2 0x00000004 // Sample sequence 2 enable\r
+#define ADC_ACTSS_ASEN1 0x00000002 // Sample sequence 1 enable\r
+#define ADC_ACTSS_ASEN0 0x00000001 // Sample sequence 0 enable\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the ADC_RIS register.\r
+//\r
+//*****************************************************************************\r
+#define ADC_RIS_INR3 0x00000008 // Sample sequence 3 interrupt\r
+#define ADC_RIS_INR2 0x00000004 // Sample sequence 2 interrupt\r
+#define ADC_RIS_INR1 0x00000002 // Sample sequence 1 interrupt\r
+#define ADC_RIS_INR0 0x00000001 // Sample sequence 0 interrupt\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the ADC_IM register.\r
+//\r
+//*****************************************************************************\r
+#define ADC_IM_MASK3 0x00000008 // Sample sequence 3 mask\r
+#define ADC_IM_MASK2 0x00000004 // Sample sequence 2 mask\r
+#define ADC_IM_MASK1 0x00000002 // Sample sequence 1 mask\r
+#define ADC_IM_MASK0 0x00000001 // Sample sequence 0 mask\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the ADC_ISC register.\r
+//\r
+//*****************************************************************************\r
+#define ADC_ISC_IN3 0x00000008 // Sample sequence 3 interrupt\r
+#define ADC_ISC_IN2 0x00000004 // Sample sequence 2 interrupt\r
+#define ADC_ISC_IN1 0x00000002 // Sample sequence 1 interrupt\r
+#define ADC_ISC_IN0 0x00000001 // Sample sequence 0 interrupt\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the ADC_OSTAT register.\r
+//\r
+//*****************************************************************************\r
+#define ADC_OSTAT_OV3 0x00000008 // Sample sequence 3 overflow\r
+#define ADC_OSTAT_OV2 0x00000004 // Sample sequence 2 overflow\r
+#define ADC_OSTAT_OV1 0x00000002 // Sample sequence 1 overflow\r
+#define ADC_OSTAT_OV0 0x00000001 // Sample sequence 0 overflow\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the ADC_EMUX register.\r
+//\r
+//*****************************************************************************\r
+#define ADC_EMUX_EM3_MASK 0x0000F000 // Event mux 3 mask\r
+#define ADC_EMUX_EM3_PROCESSOR 0x00000000 // Processor event\r
+#define ADC_EMUX_EM3_COMP0 0x00001000 // Analog comparator 0 event\r
+#define ADC_EMUX_EM3_COMP1 0x00002000 // Analog comparator 1 event\r
+#define ADC_EMUX_EM3_COMP2 0x00003000 // Analog comparator 2 event\r
+#define ADC_EMUX_EM3_EXTERNAL 0x00004000 // External event\r
+#define ADC_EMUX_EM3_TIMER 0x00005000 // Timer event\r
+#define ADC_EMUX_EM3_PWM0 0x00006000 // PWM0 event\r
+#define ADC_EMUX_EM3_PWM1 0x00007000 // PWM1 event\r
+#define ADC_EMUX_EM3_PWM2 0x00008000 // PWM2 event\r
+#define ADC_EMUX_EM3_ALWAYS 0x0000F000 // Always event\r
+#define ADC_EMUX_EM2_MASK 0x00000F00 // Event mux 2 mask\r
+#define ADC_EMUX_EM2_PROCESSOR 0x00000000 // Processor event\r
+#define ADC_EMUX_EM2_COMP0 0x00000100 // Analog comparator 0 event\r
+#define ADC_EMUX_EM2_COMP1 0x00000200 // Analog comparator 1 event\r
+#define ADC_EMUX_EM2_COMP2 0x00000300 // Analog comparator 2 event\r
+#define ADC_EMUX_EM2_EXTERNAL 0x00000400 // External event\r
+#define ADC_EMUX_EM2_TIMER 0x00000500 // Timer event\r
+#define ADC_EMUX_EM2_PWM0 0x00000600 // PWM0 event\r
+#define ADC_EMUX_EM2_PWM1 0x00000700 // PWM1 event\r
+#define ADC_EMUX_EM2_PWM2 0x00000800 // PWM2 event\r
+#define ADC_EMUX_EM2_ALWAYS 0x00000F00 // Always event\r
+#define ADC_EMUX_EM1_MASK 0x000000F0 // Event mux 1 mask\r
+#define ADC_EMUX_EM1_PROCESSOR 0x00000000 // Processor event\r
+#define ADC_EMUX_EM1_COMP0 0x00000010 // Analog comparator 0 event\r
+#define ADC_EMUX_EM1_COMP1 0x00000020 // Analog comparator 1 event\r
+#define ADC_EMUX_EM1_COMP2 0x00000030 // Analog comparator 2 event\r
+#define ADC_EMUX_EM1_EXTERNAL 0x00000040 // External event\r
+#define ADC_EMUX_EM1_TIMER 0x00000050 // Timer event\r
+#define ADC_EMUX_EM1_PWM0 0x00000060 // PWM0 event\r
+#define ADC_EMUX_EM1_PWM1 0x00000070 // PWM1 event\r
+#define ADC_EMUX_EM1_PWM2 0x00000080 // PWM2 event\r
+#define ADC_EMUX_EM1_ALWAYS 0x000000F0 // Always event\r
+#define ADC_EMUX_EM0_MASK 0x0000000F // Event mux 0 mask\r
+#define ADC_EMUX_EM0_PROCESSOR 0x00000000 // Processor event\r
+#define ADC_EMUX_EM0_COMP0 0x00000001 // Analog comparator 0 event\r
+#define ADC_EMUX_EM0_COMP1 0x00000002 // Analog comparator 1 event\r
+#define ADC_EMUX_EM0_COMP2 0x00000003 // Analog comparator 2 event\r
+#define ADC_EMUX_EM0_EXTERNAL 0x00000004 // External event\r
+#define ADC_EMUX_EM0_TIMER 0x00000005 // Timer event\r
+#define ADC_EMUX_EM0_PWM0 0x00000006 // PWM0 event\r
+#define ADC_EMUX_EM0_PWM1 0x00000007 // PWM1 event\r
+#define ADC_EMUX_EM0_PWM2 0x00000008 // PWM2 event\r
+#define ADC_EMUX_EM0_ALWAYS 0x0000000F // Always event\r
+#define ADC_EMUX_EM0_SHIFT 0 // The shift for the first event\r
+#define ADC_EMUX_EM1_SHIFT 4 // The shift for the second event\r
+#define ADC_EMUX_EM2_SHIFT 8 // The shift for the third event\r
+#define ADC_EMUX_EM3_SHIFT 12 // The shift for the fourth event\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the ADC_USTAT register.\r
+//\r
+//*****************************************************************************\r
+#define ADC_USTAT_UV3 0x00000008 // Sample sequence 3 underflow\r
+#define ADC_USTAT_UV2 0x00000004 // Sample sequence 2 underflow\r
+#define ADC_USTAT_UV1 0x00000002 // Sample sequence 1 underflow\r
+#define ADC_USTAT_UV0 0x00000001 // Sample sequence 0 underflow\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the ADC_SSPRI register.\r
+//\r
+//*****************************************************************************\r
+#define ADC_SSPRI_SS3_MASK 0x00003000 // Sequencer 3 priority mask\r
+#define ADC_SSPRI_SS3_1ST 0x00000000 // First priority\r
+#define ADC_SSPRI_SS3_2ND 0x00001000 // Second priority\r
+#define ADC_SSPRI_SS3_3RD 0x00002000 // Third priority\r
+#define ADC_SSPRI_SS3_4TH 0x00003000 // Fourth priority\r
+#define ADC_SSPRI_SS2_MASK 0x00000300 // Sequencer 2 priority mask\r
+#define ADC_SSPRI_SS2_1ST 0x00000000 // First priority\r
+#define ADC_SSPRI_SS2_2ND 0x00000100 // Second priority\r
+#define ADC_SSPRI_SS2_3RD 0x00000200 // Third priority\r
+#define ADC_SSPRI_SS2_4TH 0x00000300 // Fourth priority\r
+#define ADC_SSPRI_SS1_MASK 0x00000030 // Sequencer 1 priority mask\r
+#define ADC_SSPRI_SS1_1ST 0x00000000 // First priority\r
+#define ADC_SSPRI_SS1_2ND 0x00000010 // Second priority\r
+#define ADC_SSPRI_SS1_3RD 0x00000020 // Third priority\r
+#define ADC_SSPRI_SS1_4TH 0x00000030 // Fourth priority\r
+#define ADC_SSPRI_SS0_MASK 0x00000003 // Sequencer 0 priority mask\r
+#define ADC_SSPRI_SS0_1ST 0x00000000 // First priority\r
+#define ADC_SSPRI_SS0_2ND 0x00000001 // Second priority\r
+#define ADC_SSPRI_SS0_3RD 0x00000002 // Third priority\r
+#define ADC_SSPRI_SS0_4TH 0x00000003 // Fourth priority\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the ADC_PSSI register.\r
+//\r
+//*****************************************************************************\r
+#define ADC_PSSI_SS3 0x00000008 // Trigger sample sequencer 3\r
+#define ADC_PSSI_SS2 0x00000004 // Trigger sample sequencer 2\r
+#define ADC_PSSI_SS1 0x00000002 // Trigger sample sequencer 1\r
+#define ADC_PSSI_SS0 0x00000001 // Trigger sample sequencer 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the ADC_SAC register.\r
+//\r
+//*****************************************************************************\r
+#define ADC_SAC_AVG_OFF 0x00000000 // No hardware oversampling\r
+#define ADC_SAC_AVG_2X 0x00000001 // 2x hardware oversampling\r
+#define ADC_SAC_AVG_4X 0x00000002 // 4x hardware oversampling\r
+#define ADC_SAC_AVG_8X 0x00000003 // 8x hardware oversampling\r
+#define ADC_SAC_AVG_16X 0x00000004 // 16x hardware oversampling\r
+#define ADC_SAC_AVG_32X 0x00000005 // 32x hardware oversampling\r
+#define ADC_SAC_AVG_64X 0x00000006 // 64x hardware oversampling\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the ADC_SSMUX0, ADC_SSMUX1,\r
+// ADC_SSMUX2, and ADC_SSMUX3 registers. Not all fields are present in all\r
+// registers.\r
+//\r
+//*****************************************************************************\r
+#define ADC_SSMUX_MUX7_MASK 0x70000000 // 8th mux select mask\r
+#define ADC_SSMUX_MUX6_MASK 0x07000000 // 7th mux select mask\r
+#define ADC_SSMUX_MUX5_MASK 0x00700000 // 6th mux select mask\r
+#define ADC_SSMUX_MUX4_MASK 0x00070000 // 5th mux select mask\r
+#define ADC_SSMUX_MUX3_MASK 0x00007000 // 4th mux select mask\r
+#define ADC_SSMUX_MUX2_MASK 0x00000700 // 3rd mux select mask\r
+#define ADC_SSMUX_MUX1_MASK 0x00000070 // 2nd mux select mask\r
+#define ADC_SSMUX_MUX0_MASK 0x00000007 // 1st mux select mask\r
+#define ADC_SSMUX_MUX7_SHIFT 28\r
+#define ADC_SSMUX_MUX6_SHIFT 24\r
+#define ADC_SSMUX_MUX5_SHIFT 20\r
+#define ADC_SSMUX_MUX4_SHIFT 16\r
+#define ADC_SSMUX_MUX3_SHIFT 12\r
+#define ADC_SSMUX_MUX2_SHIFT 8\r
+#define ADC_SSMUX_MUX1_SHIFT 4\r
+#define ADC_SSMUX_MUX0_SHIFT 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the ADC_SSCTL0, ADC_SSCTL1,\r
+// ADC_SSCTL2, and ADC_SSCTL3 registers. Not all fields are present in all\r
+// registers.\r
+//\r
+//*****************************************************************************\r
+#define ADC_SSCTL_TS7 0x80000000 // 8th temperature sensor select\r
+#define ADC_SSCTL_IE7 0x40000000 // 8th interrupt enable\r
+#define ADC_SSCTL_END7 0x20000000 // 8th sequence end select\r
+#define ADC_SSCTL_D7 0x10000000 // 8th differential select\r
+#define ADC_SSCTL_TS6 0x08000000 // 7th temperature sensor select\r
+#define ADC_SSCTL_IE6 0x04000000 // 7th interrupt enable\r
+#define ADC_SSCTL_END6 0x02000000 // 7th sequence end select\r
+#define ADC_SSCTL_D6 0x01000000 // 7th differential select\r
+#define ADC_SSCTL_TS5 0x00800000 // 6th temperature sensor select\r
+#define ADC_SSCTL_IE5 0x00400000 // 6th interrupt enable\r
+#define ADC_SSCTL_END5 0x00200000 // 6th sequence end select\r
+#define ADC_SSCTL_D5 0x00100000 // 6th differential select\r
+#define ADC_SSCTL_TS4 0x00080000 // 5th temperature sensor select\r
+#define ADC_SSCTL_IE4 0x00040000 // 5th interrupt enable\r
+#define ADC_SSCTL_END4 0x00020000 // 5th sequence end select\r
+#define ADC_SSCTL_D4 0x00010000 // 5th differential select\r
+#define ADC_SSCTL_TS3 0x00008000 // 4th temperature sensor select\r
+#define ADC_SSCTL_IE3 0x00004000 // 4th interrupt enable\r
+#define ADC_SSCTL_END3 0x00002000 // 4th sequence end select\r
+#define ADC_SSCTL_D3 0x00001000 // 4th differential select\r
+#define ADC_SSCTL_TS2 0x00000800 // 3rd temperature sensor select\r
+#define ADC_SSCTL_IE2 0x00000400 // 3rd interrupt enable\r
+#define ADC_SSCTL_END2 0x00000200 // 3rd sequence end select\r
+#define ADC_SSCTL_D2 0x00000100 // 3rd differential select\r
+#define ADC_SSCTL_TS1 0x00000080 // 2nd temperature sensor select\r
+#define ADC_SSCTL_IE1 0x00000040 // 2nd interrupt enable\r
+#define ADC_SSCTL_END1 0x00000020 // 2nd sequence end select\r
+#define ADC_SSCTL_D1 0x00000010 // 2nd differential select\r
+#define ADC_SSCTL_TS0 0x00000008 // 1st temperature sensor select\r
+#define ADC_SSCTL_IE0 0x00000004 // 1st interrupt enable\r
+#define ADC_SSCTL_END0 0x00000002 // 1st sequence end select\r
+#define ADC_SSCTL_D0 0x00000001 // 1st differential select\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the ADC_SSFIFO0, ADC_SSFIFO1,\r
+// ADC_SSFIFO2, and ADC_SSFIFO3 registers.\r
+//\r
+//*****************************************************************************\r
+#define ADC_SSFIFO_DATA_MASK 0x000003FF // Sample data\r
+#define ADC_SSFIFO_DATA_SHIFT 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the ADC_SSFSTAT0, ADC_SSFSTAT1,\r
+// ADC_SSFSTAT2, and ADC_SSFSTAT3 registers.\r
+//\r
+//*****************************************************************************\r
+#define ADC_SSFSTAT_FULL 0x00001000 // FIFO is full\r
+#define ADC_SSFSTAT_EMPTY 0x00000100 // FIFO is empty\r
+#define ADC_SSFSTAT_HPTR 0x000000F0 // FIFO head pointer\r
+#define ADC_SSFSTAT_TPTR 0x0000000F // FIFO tail pointer\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the ADC_TMLB register.\r
+//\r
+//*****************************************************************************\r
+#define ADC_TMLB_LB 0x00000001 // Loopback control signals\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the loopback ADC data.\r
+//\r
+//*****************************************************************************\r
+#define ADC_LB_CNT_MASK 0x000003C0 // Sample counter mask\r
+#define ADC_LB_CONT 0x00000020 // Continuation sample\r
+#define ADC_LB_DIFF 0x00000010 // Differential sample\r
+#define ADC_LB_TS 0x00000008 // Temperature sensor sample\r
+#define ADC_LB_MUX_MASK 0x00000007 // Input channel number mask\r
+#define ADC_LB_CNT_SHIFT 6 // Sample counter shift\r
+#define ADC_LB_MUX_SHIFT 0 // Input channel number shift\r
+\r
+#endif // __HW_ADC_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_can.h - Defines and macros used when accessing the can.\r
+//\r
+// Copyright (c) 2006-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_CAN_H__\r
+#define __HW_CAN_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the offsets of the can registers.\r
+//\r
+//*****************************************************************************\r
+#define CAN_O_CTL 0x00000000 // Control register\r
+#define CAN_O_STS 0x00000004 // Status register\r
+#define CAN_O_ERR 0x00000008 // Error register\r
+#define CAN_O_BIT 0x0000000C // Bit Timing register\r
+#define CAN_O_INT 0x00000010 // Interrupt register\r
+#define CAN_O_TST 0x00000014 // Test register\r
+#define CAN_O_BRPE 0x00000018 // Baud Rate Prescaler register\r
+#define CAN_O_IF1CRQ 0x00000020 // Interface 1 Command Request reg.\r
+#define CAN_O_IF1CMSK 0x00000024 // Interface 1 Command Mask reg.\r
+#define CAN_O_IF1MSK1 0x00000028 // Interface 1 Mask 1 register\r
+#define CAN_O_IF1MSK2 0x0000002C // Interface 1 Mask 2 register\r
+#define CAN_O_IF1ARB1 0x00000030 // Interface 1 Arbitration 1 reg.\r
+#define CAN_O_IF1ARB2 0x00000034 // Interface 1 Arbitration 2 reg.\r
+#define CAN_O_IF1MCTL 0x00000038 // Interface 1 Message Control reg.\r
+#define CAN_O_IF1DA1 0x0000003C // Interface 1 DataA 1 register\r
+#define CAN_O_IF1DA2 0x00000040 // Interface 1 DataA 2 register\r
+#define CAN_O_IF1DB1 0x00000044 // Interface 1 DataB 1 register\r
+#define CAN_O_IF1DB2 0x00000048 // Interface 1 DataB 2 register\r
+#define CAN_O_IF2CRQ 0x00000080 // Interface 2 Command Request reg.\r
+#define CAN_O_IF2CMSK 0x00000084 // Interface 2 Command Mask reg.\r
+#define CAN_O_IF2MSK1 0x00000088 // Interface 2 Mask 1 register\r
+#define CAN_O_IF2MSK2 0x0000008C // Interface 2 Mask 2 register\r
+#define CAN_O_IF2ARB1 0x00000090 // Interface 2 Arbitration 1 reg.\r
+#define CAN_O_IF2ARB2 0x00000094 // Interface 2 Arbitration 2 reg.\r
+#define CAN_O_IF2MCTL 0x00000098 // Interface 2 Message Control reg.\r
+#define CAN_O_IF2DA1 0x0000009C // Interface 2 DataA 1 register\r
+#define CAN_O_IF2DA2 0x000000A0 // Interface 2 DataA 2 register\r
+#define CAN_O_IF2DB1 0x000000A4 // Interface 2 DataB 1 register\r
+#define CAN_O_IF2DB2 0x000000A8 // Interface 2 DataB 2 register\r
+#define CAN_O_TXRQ1 0x00000100 // Transmission Request 1 register\r
+#define CAN_O_TXRQ2 0x00000104 // Transmission Request 2 register\r
+#define CAN_O_NWDA1 0x00000120 // New Data 1 register\r
+#define CAN_O_NWDA2 0x00000124 // New Data 2 register\r
+#define CAN_O_MSGINT1 0x00000140 // Intr. Pending in Msg Obj 1 reg.\r
+#define CAN_O_MSGINT2 0x00000144 // Intr. Pending in Msg Obj 2 reg.\r
+#define CAN_O_MSGVAL1 0x00000160 // Message Valid in Msg Obj 1 reg.\r
+#define CAN_O_MSGVAL2 0x00000164 // Message Valid in Msg Obj 2 reg.\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the reset values of the can registers.\r
+//\r
+//*****************************************************************************\r
+#define CAN_RV_CTL 0x00000001\r
+#define CAN_RV_STS 0x00000000\r
+#define CAN_RV_ERR 0x00000000\r
+#define CAN_RV_BIT 0x00002301\r
+#define CAN_RV_INT 0x00000000\r
+#define CAN_RV_TST 0x00000000\r
+#define CAN_RV_BRPE 0x00000000\r
+#define CAN_RV_IF1CRQ 0x00000001\r
+#define CAN_RV_IF1CMSK 0x00000000\r
+#define CAN_RV_IF1MSK1 0x0000FFFF\r
+#define CAN_RV_IF1MSK2 0x0000FFFF\r
+#define CAN_RV_IF1ARB1 0x00000000\r
+#define CAN_RV_IF1ARB2 0x00000000\r
+#define CAN_RV_IF1MCTL 0x00000000\r
+#define CAN_RV_IF1DA1 0x00000000\r
+#define CAN_RV_IF1DA2 0x00000000\r
+#define CAN_RV_IF1DB1 0x00000000\r
+#define CAN_RV_IF1DB2 0x00000000\r
+#define CAN_RV_IF2CRQ 0x00000001\r
+#define CAN_RV_IF2CMSK 0x00000000\r
+#define CAN_RV_IF2MSK1 0x0000FFFF\r
+#define CAN_RV_IF2MSK2 0x0000FFFF\r
+#define CAN_RV_IF2ARB1 0x00000000\r
+#define CAN_RV_IF2ARB2 0x00000000\r
+#define CAN_RV_IF2MCTL 0x00000000\r
+#define CAN_RV_IF2DA1 0x00000000\r
+#define CAN_RV_IF2DA2 0x00000000\r
+#define CAN_RV_IF2DB1 0x00000000\r
+#define CAN_RV_IF2DB2 0x00000000\r
+#define CAN_RV_TXRQ1 0x00000000\r
+#define CAN_RV_TXRQ2 0x00000000\r
+#define CAN_RV_NWDA1 0x00000000\r
+#define CAN_RV_NWDA2 0x00000000\r
+#define CAN_RV_MSGINT1 0x00000000\r
+#define CAN_RV_MSGINT2 0x00000000\r
+#define CAN_RV_MSGVAL1 0x00000000\r
+#define CAN_RV_MSGVAL2 0x00000000\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the CAN_CTL register.\r
+//\r
+//*****************************************************************************\r
+#define CAN_CTL_TEST 0x00000080 // Test mode enable\r
+#define CAN_CTL_CCE 0x00000040 // Configuration change enable\r
+#define CAN_CTL_DAR 0x00000020 // Disable automatic retransmission\r
+#define CAN_CTL_EIE 0x00000008 // Error interrupt enable\r
+#define CAN_CTL_SIE 0x00000004 // Status change interrupt enable\r
+#define CAN_CTL_IE 0x00000002 // Module interrupt enable\r
+#define CAN_CTL_INIT 0x00000001 // Initialization\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the CAN_STS register.\r
+//\r
+//*****************************************************************************\r
+#define CAN_STS_BOFF 0x00000080 // Bus Off status\r
+#define CAN_STS_EWARN 0x00000040 // Error Warning status\r
+#define CAN_STS_EPASS 0x00000020 // Error Passive status\r
+#define CAN_STS_RXOK 0x00000010 // Received Message Successful\r
+#define CAN_STS_TXOK 0x00000008 // Transmitted Message Successful\r
+#define CAN_STS_LEC_MSK 0x00000007 // Last Error Code\r
+#define CAN_STS_LEC_NONE 0x00000000 // No error\r
+#define CAN_STS_LEC_STUFF 0x00000001 // Stuff error\r
+#define CAN_STS_LEC_FORM 0x00000002 // Form(at) error\r
+#define CAN_STS_LEC_ACK 0x00000003 // Ack error\r
+#define CAN_STS_LEC_BIT1 0x00000004 // Bit 1 error\r
+#define CAN_STS_LEC_BIT0 0x00000005 // Bit 0 error\r
+#define CAN_STS_LEC_CRC 0x00000006 // CRC error\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the CAN_ERR register.\r
+//\r
+//*****************************************************************************\r
+#define CAN_ERR_RP 0x00008000 // Receive error passive status\r
+#define CAN_ERR_REC_MASK 0x00007F00 // Receive error counter status\r
+#define CAN_ERR_REC_SHIFT 8 // Receive error counter bit pos\r
+#define CAN_ERR_TEC_MASK 0x000000FF // Transmit error counter status\r
+#define CAN_ERR_TEC_SHIFT 0 // Transmit error counter bit pos\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the CAN_BIT register.\r
+//\r
+//*****************************************************************************\r
+#define CAN_BIT_TSEG2 0x00007000 // Time segment after sample point\r
+#define CAN_BIT_TSEG1 0x00000F00 // Time segment before sample point\r
+#define CAN_BIT_SJW 0x000000C0 // (Re)Synchronization jump width\r
+#define CAN_BIT_BRP 0x0000003F // Baud rate prescaler\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the CAN_INT register.\r
+//\r
+//*****************************************************************************\r
+#define CAN_INT_INTID_MSK 0x0000FFFF // Interrupt Identifier\r
+#define CAN_INT_INTID_NONE 0x00000000 // No Interrupt Pending\r
+#define CAN_INT_INTID_STATUS 0x00008000 // Status Interrupt\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the CAN_TST register.\r
+//\r
+//*****************************************************************************\r
+#define CAN_TST_RX 0x00000080 // CAN_RX pin status\r
+#define CAN_TST_TX_MSK 0x00000060 // Overide control of CAN_TX pin\r
+#define CAN_TST_TX_CANCTL 0x00000000 // CAN core controls CAN_TX\r
+#define CAN_TST_TX_SAMPLE 0x00000020 // Sample Point on CAN_TX\r
+#define CAN_TST_TX_DOMINANT 0x00000040 // Dominant value on CAN_TX\r
+#define CAN_TST_TX_RECESSIVE 0x00000060 // Recessive value on CAN_TX\r
+#define CAN_TST_LBACK 0x00000010 // Loop back mode\r
+#define CAN_TST_SILENT 0x00000008 // Silent mode\r
+#define CAN_TST_BASIC 0x00000004 // Basic mode\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the CAN_BRPE register.\r
+//\r
+//*****************************************************************************\r
+#define CAN_BRPE_BRPE 0x0000000F // Baud rate prescaler extension\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the CAN_IF1CRQ and CAN_IF1CRQ\r
+// registers.\r
+// Note: All bits may not be available in all registers\r
+//\r
+//*****************************************************************************\r
+#define CAN_IFCRQ_BUSY 0x00008000 // Busy flag status\r
+#define CAN_IFCRQ_MNUM_MSK 0x0000003F // Message Number\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the CAN_IF1CMSK and CAN_IF2CMSK\r
+// registers.\r
+// Note: All bits may not be available in all registers\r
+//\r
+//*****************************************************************************\r
+#define CAN_IFCMSK_WRNRD 0x00000080 // Write, not Read\r
+#define CAN_IFCMSK_MASK 0x00000040 // Access Mask Bits\r
+#define CAN_IFCMSK_ARB 0x00000020 // Access Arbitration Bits\r
+#define CAN_IFCMSK_CONTROL 0x00000010 // Access Control Bits\r
+#define CAN_IFCMSK_CLRINTPND 0x00000008 // Clear interrupt pending Bit\r
+#define CAN_IFCMSK_TXRQST 0x00000004 // Access Tx request bit (WRNRD=1)\r
+#define CAN_IFCMSK_NEWDAT 0x00000004 // Access New Data bit (WRNRD=0)\r
+#define CAN_IFCMSK_DATAA 0x00000002 // DataA access - bytes 0 to 3\r
+#define CAN_IFCMSK_DATAB 0x00000001 // DataB access - bytes 4 to 7\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the CAN_IF1MSK1 and CAN_IF2MSK1\r
+// registers.\r
+// Note: All bits may not be available in all registers\r
+//\r
+//*****************************************************************************\r
+#define CAN_IFMSK1_MSK 0x0000FFFF // Identifier Mask\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the CAN_IF1MSK2 and CAN_IF2MSK2\r
+// registers.\r
+// Note: All bits may not be available in all registers\r
+//\r
+//*****************************************************************************\r
+#define CAN_IFMSK2_MXTD 0x00008000 // Mask extended identifier\r
+#define CAN_IFMSK2_MDIR 0x00004000 // Mask message direction\r
+#define CAN_IFMSK2_MSK 0x00001FFF // Mask identifier\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the CAN_IF1ARB1 and CAN_IF2ARB1\r
+// registers.\r
+// Note: All bits may not be available in all registers\r
+//\r
+//*****************************************************************************\r
+#define CAN_IFARB1_ID 0x0000FFFF // Identifier\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the CAN_IF1ARB2 and CAN_IF2ARB2\r
+// registers.\r
+// Note: All bits may not be available in all registers\r
+//\r
+//*****************************************************************************\r
+#define CAN_IFARB2_MSGVAL 0x00008000 // Message valid\r
+#define CAN_IFARB2_XTD 0x00004000 // Extended identifier\r
+#define CAN_IFARB2_DIR 0x00002000 // Message direction\r
+#define CAN_IFARB2_ID 0x00001FFF // Message identifier\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the CAN_IF1MCTL and CAN_IF2MCTL\r
+// registers.\r
+// Note: All bits may not be available in all registers\r
+//\r
+//*****************************************************************************\r
+#define CAN_IFMCTL_NEWDAT 0x00008000 // New Data\r
+#define CAN_IFMCTL_MSGLST 0x00004000 // Message lost\r
+#define CAN_IFMCTL_INTPND 0x00002000 // Interrupt pending\r
+#define CAN_IFMCTL_UMASK 0x00001000 // Use acceptance mask\r
+#define CAN_IFMCTL_TXIE 0x00000800 // Transmit interrupt enable\r
+#define CAN_IFMCTL_RXIE 0x00000400 // Receive interrupt enable\r
+#define CAN_IFMCTL_RMTEN 0x00000200 // Remote enable\r
+#define CAN_IFMCTL_TXRQST 0x00000100 // Transmit request\r
+#define CAN_IFMCTL_EOB 0x00000080 // End of buffer\r
+#define CAN_IFMCTL_DLC 0x0000000F // Data length code\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the CAN_IF1DA1 and CAN_IF2DA1\r
+// registers.\r
+// Note: All bits may not be available in all registers\r
+//\r
+//*****************************************************************************\r
+#define CAN_IFDA1_DATA 0x0000FFFF // Data - bytes 1 and 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the CAN_IF1DA2 and CAN_IF2DA2\r
+// registers.\r
+// Note: All bits may not be available in all registers\r
+//\r
+//*****************************************************************************\r
+#define CAN_IFDA2_DATA 0x0000FFFF // Data - bytes 3 and 2\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the CAN_IF1DB1 and CAN_IF2DB1\r
+// registers.\r
+// Note: All bits may not be available in all registers\r
+//\r
+//*****************************************************************************\r
+#define CAN_IFDB1_DATA 0x0000FFFF // Data - bytes 5 and 4\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the CAN_IF1DB2 and CAN_IF2DB2\r
+// registers.\r
+// Note: All bits may not be available in all registers\r
+//\r
+//*****************************************************************************\r
+#define CAN_IFDB2_DATA 0x0000FFFF // Data - bytes 7 and 6\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the CAN_TXRQ1 register.\r
+//\r
+//*****************************************************************************\r
+#define CAN_TXRQ1_TXRQST 0x0000FFFF // Transmission Request Bits\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the CAN_TXRQ2 register.\r
+//\r
+//*****************************************************************************\r
+#define CAN_TXRQ2_TXRQST 0x0000FFFF // Transmission Request Bits\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the CAN_NWDA1 register.\r
+//\r
+//*****************************************************************************\r
+#define CAN_NWDA1_NEWDATA 0x0000FFFF // New Data Bits\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the CAN_NWDA2 register.\r
+//\r
+//*****************************************************************************\r
+#define CAN_NWDA2_NEWDATA 0x0000FFFF // New Data Bits\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the CAN_MSGINT1 register.\r
+//\r
+//*****************************************************************************\r
+#define CAN_MSGINT1_INTPND 0x0000FFFF // Interrupt Pending Bits\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the CAN_MSGINT2 register.\r
+//\r
+//*****************************************************************************\r
+#define CAN_MSGINT2_INTPND 0x0000FFFF // Interrupt Pending Bits\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the CAN_MSGVAL1 register.\r
+//\r
+//*****************************************************************************\r
+#define CAN_MSGVAL1_MSGVAL 0x0000FFFF // Message Valid Bits\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the CAN_MSGVAL2 register.\r
+//\r
+//*****************************************************************************\r
+#define CAN_MSGVAL2_MSGVAL 0x0000FFFF // Message Valid Bits\r
+\r
+#endif // __HW_CAN_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_comp.h - Macros used when accessing the comparator hardware.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_COMP_H__\r
+#define __HW_COMP_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the offsets of the comparator registers.\r
+//\r
+//*****************************************************************************\r
+#define COMP_O_MIS 0x00000000 // Interrupt status register\r
+#define COMP_O_RIS 0x00000004 // Raw interrupt status register\r
+#define COMP_O_INTEN 0x00000008 // Interrupt enable register\r
+#define COMP_O_REFCTL 0x00000010 // Reference voltage control reg.\r
+#define COMP_O_ACSTAT0 0x00000020 // Comp0 status register\r
+#define COMP_O_ACCTL0 0x00000024 // Comp0 control register\r
+#define COMP_O_ACSTAT1 0x00000040 // Comp1 status register\r
+#define COMP_O_ACCTL1 0x00000044 // Comp1 control register\r
+#define COMP_O_ACSTAT2 0x00000060 // Comp2 status register\r
+#define COMP_O_ACCTL2 0x00000064 // Comp2 control register\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the COMP_MIS, COMP_RIS, and\r
+// COMP_INTEN registers.\r
+//\r
+//*****************************************************************************\r
+#define COMP_INT_2 0x00000004 // Comp2 interrupt\r
+#define COMP_INT_1 0x00000002 // Comp1 interrupt\r
+#define COMP_INT_0 0x00000001 // Comp0 interrupt\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the COMP_REFCTL register.\r
+//\r
+//*****************************************************************************\r
+#define COMP_REFCTL_EN 0x00000200 // Reference voltage enable\r
+#define COMP_REFCTL_RNG 0x00000100 // Reference voltage range\r
+#define COMP_REFCTL_VREF_MASK 0x0000000F // Reference voltage select mask\r
+#define COMP_REFCTL_VREF_SHIFT 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the COMP_ACSTAT0, COMP_ACSTAT1, and\r
+// COMP_ACSTAT2 registers.\r
+//\r
+//*****************************************************************************\r
+#define COMP_ACSTAT_OVAL 0x00000002 // Comparator output value\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the COMP_ACCTL0, COMP_ACCTL1, and\r
+// COMP_ACCTL2 registers.\r
+//\r
+//*****************************************************************************\r
+#define COMP_ACCTL_TMASK 0x00000800 // Trigger enable\r
+#define COMP_ACCTL_ASRCP_MASK 0x00000600 // Vin+ source select mask\r
+#define COMP_ACCTL_ASRCP_PIN 0x00000000 // Dedicated Comp+ pin\r
+#define COMP_ACCTL_ASRCP_PIN0 0x00000200 // Comp0+ pin\r
+#define COMP_ACCTL_ASRCP_REF 0x00000400 // Internal voltage reference\r
+#define COMP_ACCTL_ASRCP_RES 0x00000600 // Reserved\r
+#define COMP_ACCTL_OEN 0x00000100 // Comparator output enable\r
+#define COMP_ACCTL_TSVAL 0x00000080 // Trigger polarity select\r
+#define COMP_ACCTL_TSEN_MASK 0x00000060 // Trigger sense mask\r
+#define COMP_ACCTL_TSEN_LEVEL 0x00000000 // Trigger is level sense\r
+#define COMP_ACCTL_TSEN_FALL 0x00000020 // Trigger is falling edge\r
+#define COMP_ACCTL_TSEN_RISE 0x00000040 // Trigger is rising edge\r
+#define COMP_ACCTL_TSEN_BOTH 0x00000060 // Trigger is both edges\r
+#define COMP_ACCTL_ISLVAL 0x00000010 // Interrupt polarity select\r
+#define COMP_ACCTL_ISEN_MASK 0x0000000C // Interrupt sense mask\r
+#define COMP_ACCTL_ISEN_LEVEL 0x00000000 // Interrupt is level sense\r
+#define COMP_ACCTL_ISEN_FALL 0x00000004 // Interrupt is falling edge\r
+#define COMP_ACCTL_ISEN_RISE 0x00000008 // Interrupt is rising edge\r
+#define COMP_ACCTL_ISEN_BOTH 0x0000000C // Interrupt is both edges\r
+#define COMP_ACCTL_CINV 0x00000002 // Comparator output invert\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the reset values for the comparator registers.\r
+//\r
+//*****************************************************************************\r
+#define COMP_RV_MIS 0x00000000 // Interrupt status register\r
+#define COMP_RV_RIS 0x00000000 // Raw interrupt status register\r
+#define COMP_RV_INTEN 0x00000000 // Interrupt enable register\r
+#define COMP_RV_REFCTL 0x00000000 // Reference voltage control reg.\r
+#define COMP_RV_ACSTAT0 0x00000000 // Comp0 status register\r
+#define COMP_RV_ACCTL0 0x00000000 // Comp0 control register\r
+#define COMP_RV_ACSTAT1 0x00000000 // Comp1 status register\r
+#define COMP_RV_ACCTL1 0x00000000 // Comp1 control register\r
+#define COMP_RV_ACSTAT2 0x00000000 // Comp2 status register\r
+#define COMP_RV_ACCTL2 0x00000000 // Comp2 control register\r
+\r
+#endif // __HW_COMP_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_ethernet.h - Macros used when accessing the ethernet hardware.\r
+//\r
+// Copyright (c) 2006-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_ETHERNET_H__\r
+#define __HW_ETHERNET_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the offsets of the MAC registers in the Ethernet\r
+// Controller.\r
+//\r
+//*****************************************************************************\r
+#define MAC_O_IS 0x00000000 // Interrupt Status Register\r
+#define MAC_O_IACK 0x00000000 // Interrupt Acknowledge Register\r
+#define MAC_O_IM 0x00000004 // Interrupt Mask Register\r
+#define MAC_O_RCTL 0x00000008 // Receive Control Register\r
+#define MAC_O_TCTL 0x0000000C // Transmit Control Register\r
+#define MAC_O_DATA 0x00000010 // Data Register\r
+#define MAC_O_IA0 0x00000014 // Individual Address Register 0\r
+#define MAC_O_IA1 0x00000018 // Individual Address Register 1\r
+#define MAC_O_THR 0x0000001C // Threshold Register\r
+#define MAC_O_MCTL 0x00000020 // Management Control Register\r
+#define MAC_O_MDV 0x00000024 // Management Divider Register\r
+#define MAC_O_MADD 0x00000028 // Management Address Register\r
+#define MAC_O_MTXD 0x0000002C // Management Transmit Data Reg\r
+#define MAC_O_MRXD 0x00000030 // Management Receive Data Reg\r
+#define MAC_O_NP 0x00000034 // Number of Packets Register\r
+#define MAC_O_TR 0x00000038 // Transmission Request Register\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the reset values of the MAC registers.\r
+//\r
+//*****************************************************************************\r
+#define MAC_RV_IS 0x00000000\r
+#define MAC_RV_IACK 0x00000000\r
+#define MAC_RV_IM 0x0000007F\r
+#define MAC_RV_RCTL 0x00000008\r
+#define MAC_RV_TCTL 0x00000000\r
+#define MAC_RV_DATA 0x00000000\r
+#define MAC_RV_IA0 0x00000000\r
+#define MAC_RV_IA1 0x00000000\r
+#define MAC_RV_THR 0x0000003F\r
+#define MAC_RV_MCTL 0x00000000\r
+#define MAC_RV_MDV 0x00000080\r
+#define MAC_RV_MADD 0x00000000\r
+#define MAC_RV_MTXD 0x00000000\r
+#define MAC_RV_MRXD 0x00000000\r
+#define MAC_RV_NP 0x00000000\r
+#define MAC_RV_TR 0x00000000\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the MAC_IS register.\r
+//\r
+//*****************************************************************************\r
+#define MAC_IS_PHYINT 0x00000040 // PHY Interrupt\r
+#define MAC_IS_MDINT 0x00000020 // MDI Transaction Complete\r
+#define MAC_IS_RXER 0x00000010 // RX Error\r
+#define MAC_IS_FOV 0x00000008 // RX FIFO Overrun\r
+#define MAC_IS_TXEMP 0x00000004 // TX FIFO Empy\r
+#define MAC_IS_TXER 0x00000002 // TX Error\r
+#define MAC_IS_RXINT 0x00000001 // RX Packet Available\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the MAC_IACK register.\r
+//\r
+//*****************************************************************************\r
+#define MAC_IACK_PHYINT 0x00000040 // Clear PHY Interrupt\r
+#define MAC_IACK_MDINT 0x00000020 // Clear MDI Transaction Complete\r
+#define MAC_IACK_RXER 0x00000010 // Clear RX Error\r
+#define MAC_IACK_FOV 0x00000008 // Clear RX FIFO Overrun\r
+#define MAC_IACK_TXEMP 0x00000004 // Clear TX FIFO Empy\r
+#define MAC_IACK_TXER 0x00000002 // Clear TX Error\r
+#define MAC_IACK_RXINT 0x00000001 // Clear RX Packet Available\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the MAC_IM register.\r
+//\r
+//*****************************************************************************\r
+#define MAC_IM_PHYINTM 0x00000040 // Mask PHY Interrupt\r
+#define MAC_IM_MDINTM 0x00000020 // Mask MDI Transaction Complete\r
+#define MAC_IM_RXERM 0x00000010 // Mask RX Error\r
+#define MAC_IM_FOVM 0x00000008 // Mask RX FIFO Overrun\r
+#define MAC_IM_TXEMPM 0x00000004 // Mask TX FIFO Empy\r
+#define MAC_IM_TXERM 0x00000002 // Mask TX Error\r
+#define MAC_IM_RXINTM 0x00000001 // Mask RX Packet Available\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the MAC_RCTL register.\r
+//\r
+//*****************************************************************************\r
+#define MAC_RCTL_RSTFIFO 0x00000010 // Clear the Receive FIFO\r
+#define MAC_RCTL_BADCRC 0x00000008 // Reject Packets With Bad CRC\r
+#define MAC_RCTL_PRMS 0x00000004 // Enable Promiscuous Mode\r
+#define MAC_RCTL_AMUL 0x00000002 // Enable Multicast Packets\r
+#define MAC_RCTL_RXEN 0x00000001 // Enable Ethernet Receiver\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the MAC_TCTL register.\r
+//\r
+//*****************************************************************************\r
+#define MAC_TCTL_DUPLEX 0x00000010 // Enable Duplex mode\r
+#define MAC_TCTL_CRC 0x00000004 // Enable CRC Generation\r
+#define MAC_TCTL_PADEN 0x00000002 // Enable Automatic Padding\r
+#define MAC_TCTL_TXEN 0x00000001 // Enable Ethernet Transmitter\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the MAC_IA0 register.\r
+//\r
+//*****************************************************************************\r
+#define MAC_IA0_MACOCT4 0xFF000000 // 4th Octet of MAC address\r
+#define MAC_IA0_MACOCT3 0x00FF0000 // 3rd Octet of MAC address\r
+#define MAC_IA0_MACOCT2 0x0000FF00 // 2nd Octet of MAC address\r
+#define MAC_IA0_MACOCT1 0x000000FF // 1st Octet of MAC address\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the MAC_IA1 register.\r
+//\r
+//*****************************************************************************\r
+#define MAC_IA1_MACOCT6 0x0000FF00 // 6th Octet of MAC address\r
+#define MAC_IA1_MACOCT5 0x000000FF // 5th Octet of MAC address\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the MAC_TXTH register.\r
+//\r
+//*****************************************************************************\r
+#define MAC_THR_THRESH 0x0000003F // Transmit Threshold Value\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the MAC_MCTL register.\r
+//\r
+//*****************************************************************************\r
+#define MAC_MCTL_REGADR 0x000000F8 // Address for Next MII Transaction\r
+#define MAC_MCTL_WRITE 0x00000002 // Next MII Transaction is Write\r
+#define MAC_MCTL_START 0x00000001 // Start MII Transaction\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the MAC_MDV register.\r
+//\r
+//*****************************************************************************\r
+#define MAC_MDV_DIV 0x000000FF // Clock Divider for MDC for TX\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the MAC_MTXD register.\r
+//\r
+//*****************************************************************************\r
+#define MAC_MTXD_MDTX 0x0000FFFF // Data for Next MII Transaction\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the MAC_MRXD register.\r
+//\r
+//*****************************************************************************\r
+#define MAC_MRXD_MDRX 0x0000FFFF // Data Read from Last MII Trans.\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the MAC_NP register.\r
+//\r
+//*****************************************************************************\r
+#define MAC_NP_NPR 0x0000003F // Number of RX Frames in FIFO\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the MAC_TXRQ register.\r
+//\r
+//*****************************************************************************\r
+#define MAC_TR_NEWTX 0x00000001 // Start an Ethernet Transmission\r
+\r
+#endif // __HW_ETHERNET_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_flash.h - Macros used when accessing the flash controller.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_FLASH_H__\r
+#define __HW_FLASH_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the offsets of the FLASH registers.\r
+//\r
+//*****************************************************************************\r
+#define FLASH_FMA 0x400FD000 // Memory address register\r
+#define FLASH_FMD 0x400FD004 // Memory data register\r
+#define FLASH_FMC 0x400FD008 // Memory control register\r
+#define FLASH_FCRIS 0x400FD00c // Raw interrupt status register\r
+#define FLASH_FCIM 0x400FD010 // Interrupt mask register\r
+#define FLASH_FCMISC 0x400FD014 // Interrupt status register\r
+#define FLASH_FMPRE 0x400FE130 // FLASH read protect register\r
+#define FLASH_FMPPE 0x400FE134 // FLASH program protect register\r
+#define FLASH_USECRL 0x400FE140 // uSec reload register\r
+#define FLASH_FMPRE0 0x400FE200 // FLASH read protect register 0\r
+#define FLASH_FMPRE1 0x400FE204 // FLASH read protect register 1\r
+#define FLASH_FMPRE2 0x400FE208 // FLASH read protect register 2\r
+#define FLASH_FMPRE3 0x400FE20C // FLASH read protect register 3\r
+#define FLASH_FMPPE0 0x400FE400 // FLASH program protect register 0\r
+#define FLASH_FMPPE1 0x400FE404 // FLASH program protect register 1\r
+#define FLASH_FMPPE2 0x400FE408 // FLASH program protect register 2\r
+#define FLASH_FMPPE3 0x400FE40C // FLASH program protect register 3\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the FLASH_FMC register.\r
+//\r
+//*****************************************************************************\r
+#define FLASH_FMC_WRKEY_MASK 0xFFFF0000 // FLASH write key mask\r
+#define FLASH_FMC_WRKEY 0xA4420000 // FLASH write key\r
+#define FLASH_FMC_COMT 0x00000008 // Commit user register\r
+#define FLASH_FMC_MERASE 0x00000004 // Mass erase FLASH\r
+#define FLASH_FMC_ERASE 0x00000002 // Erase FLASH page\r
+#define FLASH_FMC_WRITE 0x00000001 // Write FLASH word\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the FLASH_FCRIS register.\r
+//\r
+//*****************************************************************************\r
+#define FLASH_FCRIS_PROGRAM 0x00000002 // Programming status\r
+#define FLASH_FCRIS_ACCESS 0x00000001 // Invalid access status\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the FLASH_FCIM register.\r
+//\r
+//*****************************************************************************\r
+#define FLASH_FCIM_PROGRAM 0x00000002 // Programming mask\r
+#define FLASH_FCIM_ACCESS 0x00000001 // Invalid access mask\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the FLASH_FMIS register.\r
+//\r
+//*****************************************************************************\r
+#define FLASH_FCMISC_PROGRAM 0x00000002 // Programming status\r
+#define FLASH_FCMISC_ACCESS 0x00000001 // Invalid access status\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the FLASH_FMPRE and FLASH_FMPPE\r
+// registers.\r
+//\r
+//*****************************************************************************\r
+#define FLASH_FMP_BLOCK_31 0x80000000 // Enable for block 31\r
+#define FLASH_FMP_BLOCK_30 0x40000000 // Enable for block 30\r
+#define FLASH_FMP_BLOCK_29 0x20000000 // Enable for block 29\r
+#define FLASH_FMP_BLOCK_28 0x10000000 // Enable for block 28\r
+#define FLASH_FMP_BLOCK_27 0x08000000 // Enable for block 27\r
+#define FLASH_FMP_BLOCK_26 0x04000000 // Enable for block 26\r
+#define FLASH_FMP_BLOCK_25 0x02000000 // Enable for block 25\r
+#define FLASH_FMP_BLOCK_24 0x01000000 // Enable for block 24\r
+#define FLASH_FMP_BLOCK_23 0x00800000 // Enable for block 23\r
+#define FLASH_FMP_BLOCK_22 0x00400000 // Enable for block 22\r
+#define FLASH_FMP_BLOCK_21 0x00200000 // Enable for block 21\r
+#define FLASH_FMP_BLOCK_20 0x00100000 // Enable for block 20\r
+#define FLASH_FMP_BLOCK_19 0x00080000 // Enable for block 19\r
+#define FLASH_FMP_BLOCK_18 0x00040000 // Enable for block 18\r
+#define FLASH_FMP_BLOCK_17 0x00020000 // Enable for block 17\r
+#define FLASH_FMP_BLOCK_16 0x00010000 // Enable for block 16\r
+#define FLASH_FMP_BLOCK_15 0x00008000 // Enable for block 15\r
+#define FLASH_FMP_BLOCK_14 0x00004000 // Enable for block 14\r
+#define FLASH_FMP_BLOCK_13 0x00002000 // Enable for block 13\r
+#define FLASH_FMP_BLOCK_12 0x00001000 // Enable for block 12\r
+#define FLASH_FMP_BLOCK_11 0x00000800 // Enable for block 11\r
+#define FLASH_FMP_BLOCK_10 0x00000400 // Enable for block 10\r
+#define FLASH_FMP_BLOCK_9 0x00000200 // Enable for block 9\r
+#define FLASH_FMP_BLOCK_8 0x00000100 // Enable for block 8\r
+#define FLASH_FMP_BLOCK_7 0x00000080 // Enable for block 7\r
+#define FLASH_FMP_BLOCK_6 0x00000040 // Enable for block 6\r
+#define FLASH_FMP_BLOCK_5 0x00000020 // Enable for block 5\r
+#define FLASH_FMP_BLOCK_4 0x00000010 // Enable for block 4\r
+#define FLASH_FMP_BLOCK_3 0x00000008 // Enable for block 3\r
+#define FLASH_FMP_BLOCK_2 0x00000004 // Enable for block 2\r
+#define FLASH_FMP_BLOCK_1 0x00000002 // Enable for block 1\r
+#define FLASH_FMP_BLOCK_0 0x00000001 // Enable for block 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the FLASH_USECRL register.\r
+//\r
+//*****************************************************************************\r
+#define FLASH_USECRL_MASK 0x000000FF // Clock per uSec\r
+#define FLASH_USECRL_SHIFT 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The erase size is the size of the FLASH block that is erased by an erase\r
+// operation, and the protect size is the size of the FLASH block that is\r
+// protected by each protection register.\r
+//\r
+//*****************************************************************************\r
+#define FLASH_ERASE_SIZE 0x00000400\r
+#define FLASH_PROTECT_SIZE 0x00000800\r
+\r
+#endif // __HW_FLASH_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_gpio.h - Defines and Macros for GPIO hardware.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_GPIO_H__\r
+#define __HW_GPIO_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// GPIO Register Offsets.\r
+//\r
+//*****************************************************************************\r
+#define GPIO_O_DATA 0x00000000 // Data register.\r
+#define GPIO_O_DIR 0x00000400 // Data direction register.\r
+#define GPIO_O_IS 0x00000404 // Interrupt sense register.\r
+#define GPIO_O_IBE 0x00000408 // Interrupt both edges register.\r
+#define GPIO_O_IEV 0x0000040C // Intterupt event register.\r
+#define GPIO_O_IM 0x00000410 // Interrupt mask register.\r
+#define GPIO_O_RIS 0x00000414 // Raw interrupt status register.\r
+#define GPIO_O_MIS 0x00000418 // Masked interrupt status reg.\r
+#define GPIO_O_ICR 0x0000041C // Interrupt clear register.\r
+#define GPIO_O_AFSEL 0x00000420 // Mode control select register.\r
+#define GPIO_O_DR2R 0x00000500 // 2ma drive select register.\r
+#define GPIO_O_DR4R 0x00000504 // 4ma drive select register.\r
+#define GPIO_O_DR8R 0x00000508 // 8ma drive select register.\r
+#define GPIO_O_ODR 0x0000050C // Open drain select register.\r
+#define GPIO_O_PUR 0x00000510 // Pull up select register.\r
+#define GPIO_O_PDR 0x00000514 // Pull down select register.\r
+#define GPIO_O_SLR 0x00000518 // Slew rate control enable reg.\r
+#define GPIO_O_DEN 0x0000051C // Digital input enable register.\r
+#define GPIO_O_LOCK 0x00000520 // Lock register.\r
+#define GPIO_O_CR 0x00000524 // Commit register.\r
+#define GPIO_O_PeriphID4 0x00000FD0 //\r
+#define GPIO_O_PeriphID5 0x00000FD4 //\r
+#define GPIO_O_PeriphID6 0x00000FD8 //\r
+#define GPIO_O_PeriphID7 0x00000FDC //\r
+#define GPIO_O_PeriphID0 0x00000FE0 //\r
+#define GPIO_O_PeriphID1 0x00000FE4 //\r
+#define GPIO_O_PeriphID2 0x00000FE8 //\r
+#define GPIO_O_PeriphID3 0x00000FEC //\r
+#define GPIO_O_PCellID0 0x00000FF0 //\r
+#define GPIO_O_PCellID1 0x00000FF4 //\r
+#define GPIO_O_PCellID2 0x00000FF8 //\r
+#define GPIO_O_PCellID3 0x00000FFC //\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the GPIO_LOCK register.\r
+//\r
+//*****************************************************************************\r
+#define GPIO_LOCK_LOCKED 0x00000001 // GPIO_CR register is locked\r
+#define GPIO_LOCK_UNLOCKED 0x00000000 // GPIO_CR register is unlocked\r
+#define GPIO_LOCK_KEY 0x1ACCE551 // Unlocks the GPIO_CR register\r
+\r
+//*****************************************************************************\r
+//\r
+// GPIO Register reset values.\r
+//\r
+//*****************************************************************************\r
+#define GPIO_RV_DATA 0x00000000 // Data register reset value.\r
+#define GPIO_RV_DIR 0x00000000 // Data direction reg RV.\r
+#define GPIO_RV_IS 0x00000000 // Interrupt sense reg RV.\r
+#define GPIO_RV_IBE 0x00000000 // Interrupt both edges reg RV.\r
+#define GPIO_RV_IEV 0x00000000 // Intterupt event reg RV.\r
+#define GPIO_RV_IM 0x00000000 // Interrupt mask reg RV.\r
+#define GPIO_RV_RIS 0x00000000 // Raw interrupt status reg RV.\r
+#define GPIO_RV_MIS 0x00000000 // Masked interrupt status reg RV.\r
+#define GPIO_RV_IC 0x00000000 // Interrupt clear reg RV.\r
+#define GPIO_RV_AFSEL 0x00000000 // Mode control select reg RV.\r
+#define GPIO_RV_DR2R 0x000000FF // 2ma drive select reg RV.\r
+#define GPIO_RV_DR4R 0x00000000 // 4ma drive select reg RV.\r
+#define GPIO_RV_DR8R 0x00000000 // 8ma drive select reg RV.\r
+#define GPIO_RV_ODR 0x00000000 // Open drain select reg RV.\r
+#define GPIO_RV_PUR 0x000000FF // Pull up select reg RV.\r
+#define GPIO_RV_PDR 0x00000000 // Pull down select reg RV.\r
+#define GPIO_RV_SLR 0x00000000 // Slew rate control enable reg RV.\r
+#define GPIO_RV_DEN 0x000000FF // Digital input enable reg RV.\r
+#define GPIO_RV_LOCK 0x00000001 // Lock register RV.\r
+#define GPIO_RV_PeriphID4 0x00000000 //\r
+#define GPIO_RV_PeriphID5 0x00000000 //\r
+#define GPIO_RV_PeriphID6 0x00000000 //\r
+#define GPIO_RV_PeriphID7 0x00000000 //\r
+#define GPIO_RV_PeriphID0 0x00000061 //\r
+#define GPIO_RV_PeriphID1 0x00000010 //\r
+#define GPIO_RV_PeriphID2 0x00000004 //\r
+#define GPIO_RV_PeriphID3 0x00000000 //\r
+#define GPIO_RV_PCellID0 0x0000000D //\r
+#define GPIO_RV_PCellID1 0x000000F0 //\r
+#define GPIO_RV_PCellID2 0x00000005 //\r
+#define GPIO_RV_PCellID3 0x000000B1 //\r
+\r
+#endif // __HW_GPIO_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_hibernate.h - Defines and Macros for the Hibernation module.\r
+//\r
+// Copyright (c) 2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_HIBERNATE_H__\r
+#define __HW_HIBERNATE_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the addresses of the hibernation module registers.\r
+//\r
+//*****************************************************************************\r
+#define HIB_RTCC 0x400fc000 // Hibernate RTC counter\r
+#define HIB_RTCM0 0x400fc004 // Hibernate RTC match 0\r
+#define HIB_RTCM1 0x400fc008 // Hibernate RTC match 1\r
+#define HIB_RTCLD 0x400fc00C // Hibernate RTC load\r
+#define HIB_CTL 0x400fc010 // Hibernate RTC control\r
+#define HIB_IM 0x400fc014 // Hibernate interrupt mask\r
+#define HIB_RIS 0x400fc018 // Hibernate raw interrupt status\r
+#define HIB_MIS 0x400fc01C // Hibernate masked interrupt stat\r
+#define HIB_IC 0x400fc020 // Hibernate interrupt clear\r
+#define HIB_RTCT 0x400fc024 // Hibernate RTC trim\r
+#define HIB_DATA 0x400fc030 // Hibernate data area\r
+#define HIB_DATA_END 0x400fc130 // end of data area, exclusive\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the Hibernate RTC counter register.\r
+//\r
+//*****************************************************************************\r
+#define HIB_RTCC_MASK 0xffffffff // RTC counter mask\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the Hibernate RTC match 0 register.\r
+//\r
+//*****************************************************************************\r
+#define HIB_RTCM0_MASK 0xffffffff // RTC match 0 mask\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the Hibernate RTC match 1 register.\r
+//\r
+//*****************************************************************************\r
+#define HIB_RTCM1_MASK 0xffffffff // RTC match 1 mask\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the Hibernate RTC load register.\r
+//\r
+//*****************************************************************************\r
+#define HIB_RTCLD_MASK 0xffffffff // RTC load mask\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the Hibernate control register\r
+//\r
+//*****************************************************************************\r
+#define HIB_CTL_VABORT 0x00000080 // low bat abort\r
+#define HIB_CTL_CLK32EN 0x00000040 // enable clock/oscillator\r
+#define HIB_CTL_LOWBATEN 0x00000020 // enable low battery detect\r
+#define HIB_CTL_PINWEN 0x00000010 // enable wake on WAKE pin\r
+#define HIB_CTL_RTCWEN 0x00000008 // enable wake on RTC match\r
+#define HIB_CTL_CLKSEL 0x00000004 // clock input selection\r
+#define HIB_CTL_HIBREQ 0x00000002 // request hibernation\r
+#define HIB_CTL_RTCEN 0x00000001 // RTC enable\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the Hibernate interrupt mask reg.\r
+//\r
+//*****************************************************************************\r
+#define HIB_IM_EXTW 0x00000008 // wake from external pin interrupt\r
+#define HIB_IM_LOWBAT 0x00000004 // low battery interrupt\r
+#define HIB_IM_RTCALT1 0x00000002 // RTC match 1 interrupt\r
+#define HIB_IM_RTCALT0 0x00000001 // RTC match 0 interrupt\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the Hibernate raw interrupt status.\r
+//\r
+//*****************************************************************************\r
+#define HIB_RIS_EXTW 0x00000008 // wake from external pin interrupt\r
+#define HIB_RIS_LOWBAT 0x00000004 // low battery interrupt\r
+#define HIB_RIS_RTCALT1 0x00000002 // RTC match 1 interrupt\r
+#define HIB_RID_RTCALT0 0x00000001 // RTC match 0 interrupt\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the Hibernate masked int status.\r
+//\r
+//*****************************************************************************\r
+#define HIB_MIS_EXTW 0x00000008 // wake from external pin interrupt\r
+#define HIB_MIS_LOWBAT 0x00000004 // low battery interrupt\r
+#define HIB_MIS_RTCALT1 0x00000002 // RTC match 1 interrupt\r
+#define HIB_MID_RTCALT0 0x00000001 // RTC match 0 interrupt\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the Hibernate interrupt clear reg.\r
+//\r
+//*****************************************************************************\r
+#define HIB_IC_EXTW 0x00000008 // wake from external pin interrupt\r
+#define HIB_IC_LOWBAT 0x00000004 // low battery interrupt\r
+#define HIB_IC_RTCALT1 0x00000002 // RTC match 1 interrupt\r
+#define HIB_IC_RTCALT0 0x00000001 // RTC match 0 interrupt\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the Hibernate RTC trim register.\r
+//\r
+//*****************************************************************************\r
+#define HIB_RTCT_MASK 0x0000ffff // RTC trim mask\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the Hibernate data register.\r
+//\r
+//*****************************************************************************\r
+#define HIB_DATA_MASK 0xffffffff // NV memory data mask\r
+\r
+#endif // __HW_HIBERNATE_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_i2c.h - Macros used when accessing the I2C master and slave hardware.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_I2C_H__\r
+#define __HW_I2C_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// The following defines the offset between the I2C master and slave registers.\r
+//\r
+//*****************************************************************************\r
+#define I2C_O_SLAVE 0x00000800 // Offset from master to slave\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the offsets of the I2C master registers.\r
+//\r
+//*****************************************************************************\r
+#define I2C_MASTER_O_SA 0x00000000 // Slave address register\r
+#define I2C_MASTER_O_CS 0x00000004 // Control and Status register\r
+#define I2C_MASTER_O_DR 0x00000008 // Data register\r
+#define I2C_MASTER_O_TPR 0x0000000C // Timer period register\r
+#define I2C_MASTER_O_IMR 0x00000010 // Interrupt mask register\r
+#define I2C_MASTER_O_RIS 0x00000014 // Raw interrupt status register\r
+#define I2C_MASTER_O_MIS 0x00000018 // Masked interrupt status reg\r
+#define I2C_MASTER_O_MICR 0x0000001c // Interrupt clear register\r
+#define I2C_MASTER_O_CR 0x00000020 // Configuration register\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the offsets of the I2C slave registers.\r
+//\r
+//*****************************************************************************\r
+#define I2C_SLAVE_O_OAR 0x00000000 // Own address register\r
+#define I2C_SLAVE_O_CSR 0x00000004 // Control/Status register\r
+#define I2C_SLAVE_O_DR 0x00000008 // Data register\r
+#define I2C_SLAVE_O_IM 0x0000000C // Interrupt mask register\r
+#define I2C_SLAVE_O_RIS 0x00000010 // Raw interrupt status register\r
+#define I2C_SLAVE_O_MIS 0x00000014 // Masked interrupt status reg\r
+#define I2C_SLAVE_O_SICR 0x00000018 // Interrupt clear register\r
+\r
+//*****************************************************************************\r
+//\r
+// The followng define the bit fields in the I2C master slave address register.\r
+//\r
+//*****************************************************************************\r
+#define I2C_MASTER_SA_SA_MASK 0x000000FE // Slave address\r
+#define I2C_MASTER_SA_RS 0x00000001 // Receive/send\r
+#define I2C_MASTER_SA_SA_SHIFT 1\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the I2C Master Control and Status\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define I2C_MASTER_CS_ACK 0x00000008 // Acknowlegde\r
+#define I2C_MASTER_CS_STOP 0x00000004 // Stop\r
+#define I2C_MASTER_CS_START 0x00000002 // Start\r
+#define I2C_MASTER_CS_RUN 0x00000001 // Run\r
+#define I2C_MASTER_CS_BUS_BUSY 0x00000040 // Bus busy\r
+#define I2C_MASTER_CS_IDLE 0x00000020 // Idle\r
+#define I2C_MASTER_CS_ARB_LOST 0x00000010 // Lost arbitration\r
+#define I2C_MASTER_CS_DATA_ACK 0x00000008 // Data byte not acknowledged\r
+#define I2C_MASTER_CS_ADDR_ACK 0x00000004 // Address byte not acknowledged\r
+#define I2C_MASTER_CS_ERROR 0x00000002 // Error occurred\r
+#define I2C_MASTER_CS_BUSY 0x00000001 // Controller is TX/RX data\r
+#define I2C_MASTER_CS_ERR_MASK 0x0000001C\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define values used in determining the contents of the I2C\r
+// Master Timer Period register.\r
+//\r
+//*****************************************************************************\r
+#define I2C_MASTER_TPR_SCL_HP 0x00000004 // SCL high period\r
+#define I2C_MASTER_TPR_SCL_LP 0x00000006 // SCL low period\r
+#define I2C_MASTER_TPR_SCL (I2C_MASTER_TPR_SCL_HP + I2C_MASTER_TPR_SCL_LP)\r
+#define I2C_SCL_STANDARD 100000 // SCL standard frequency\r
+#define I2C_SCL_FAST 400000 // SCL fast frequency\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the I2C Master Interrupt Mask\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define I2C_MASTER_IMR_IM 0x00000001 // Master interrupt mask\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the I2C Master Raw Interrupt Status\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define I2C_MASTER_RIS_RIS 0x00000001 // Master raw interrupt status\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the I2C Master Masked Interrupt\r
+// Status register.\r
+//\r
+//*****************************************************************************\r
+#define I2C_MASTER_MIS_MIS 0x00000001 // Master masked interrupt status\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the I2C Master Interrupt Clear\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define I2C_MASTER_MICR_IC 0x00000001 // Master interrupt clear\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the I2C Master Configuration\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define I2C_MASTER_CR_SFE 0x00000020 // Slave function enable\r
+#define I2C_MASTER_CR_MFE 0x00000010 // Master function enable\r
+#define I2C_MASTER_CR_LPBK 0x00000001 // Loopback enable\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the I2C Slave Own Address register.\r
+//\r
+//*****************************************************************************\r
+#define I2C_SLAVE_SOAR_OAR_MASK 0x0000007F // Slave address\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the I2C Slave Control/Status\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define I2C_SLAVE_CSR_DA 0x00000001 // Enable the device\r
+#define I2C_SLAVE_CSR_TREQ 0x00000002 // Transmit request received\r
+#define I2C_SLAVE_CSR_RREQ 0x00000001 // Receive data from I2C master\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the I2C Slave Interrupt Mask\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define I2C_SLAVE_IMR_IM 0x00000001 // Slave interrupt mask\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the I2C Slave Raw Interrupt Status\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define I2C_SLAVE_RIS_RIS 0x00000001 // Slave raw interrupt status\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the I2C Slave Masked Interrupt\r
+// Status register.\r
+//\r
+//*****************************************************************************\r
+#define I2C_SLAVE_MIS_MIS 0x00000001 // Slave masked interrupt status\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the I2C Slave Interrupt Clear\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define I2C_SLAVE_SICR_IC 0x00000001 // Slave interrupt clear\r
+\r
+#endif // __HW_I2C_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_ints.h - Macros that define the interrupt assignment on Stellaris.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_INTS_H__\r
+#define __HW_INTS_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the fault assignments.\r
+//\r
+//*****************************************************************************\r
+#define FAULT_NMI 2 // NMI fault\r
+#define FAULT_HARD 3 // Hard fault\r
+#define FAULT_MPU 4 // MPU fault\r
+#define FAULT_BUS 5 // Bus fault\r
+#define FAULT_USAGE 6 // Usage fault\r
+#define FAULT_SVCALL 11 // SVCall\r
+#define FAULT_DEBUG 12 // Debug monitor\r
+#define FAULT_PENDSV 14 // PendSV\r
+#define FAULT_SYSTICK 15 // System Tick\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the interrupt assignments.\r
+//\r
+//*****************************************************************************\r
+#define INT_GPIOA 16 // GPIO Port A\r
+#define INT_GPIOB 17 // GPIO Port B\r
+#define INT_GPIOC 18 // GPIO Port C\r
+#define INT_GPIOD 19 // GPIO Port D\r
+#define INT_GPIOE 20 // GPIO Port E\r
+#define INT_UART0 21 // UART0 Rx and Tx\r
+#define INT_UART1 22 // UART1 Rx and Tx\r
+#define INT_SSI 23 // SSI Rx and Tx\r
+#define INT_SSI0 23 // SSI0 Rx and Tx\r
+#define INT_I2C 24 // I2C Master and Slave\r
+#define INT_I2C0 24 // I2C0 Master and Slave\r
+#define INT_PWM_FAULT 25 // PWM Fault\r
+#define INT_PWM0 26 // PWM Generator 0\r
+#define INT_PWM1 27 // PWM Generator 1\r
+#define INT_PWM2 28 // PWM Generator 2\r
+#define INT_QEI 29 // Quadrature Encoder\r
+#define INT_QEI0 29 // Quadrature Encoder 0\r
+#define INT_ADC0 30 // ADC Sequence 0\r
+#define INT_ADC1 31 // ADC Sequence 1\r
+#define INT_ADC2 32 // ADC Sequence 2\r
+#define INT_ADC3 33 // ADC Sequence 3\r
+#define INT_WATCHDOG 34 // Watchdog timer\r
+#define INT_TIMER0A 35 // Timer 0 subtimer A\r
+#define INT_TIMER0B 36 // Timer 0 subtimer B\r
+#define INT_TIMER1A 37 // Timer 1 subtimer A\r
+#define INT_TIMER1B 38 // Timer 1 subtimer B\r
+#define INT_TIMER2A 39 // Timer 2 subtimer A\r
+#define INT_TIMER2B 40 // Timer 2 subtimer B\r
+#define INT_COMP0 41 // Analog Comparator 0\r
+#define INT_COMP1 42 // Analog Comparator 1\r
+#define INT_COMP2 43 // Analog Comparator 2\r
+#define INT_SYSCTL 44 // System Control (PLL, OSC, BO)\r
+#define INT_FLASH 45 // FLASH Control\r
+#define INT_GPIOF 46 // GPIO Port F\r
+#define INT_GPIOG 47 // GPIO Port G\r
+#define INT_GPIOH 48 // GPIO Port H\r
+#define INT_UART2 49 // UART2 Rx and Tx\r
+#define INT_SSI1 50 // SSI1 Rx and Tx\r
+#define INT_TIMER3A 51 // Timer 3 subtimer A\r
+#define INT_TIMER3B 52 // Timer 3 subtimer B\r
+#define INT_I2C1 53 // I2C1 Master and Slave\r
+#define INT_QEI1 54 // Quadrature Encoder 1\r
+#define INT_CAN0 55 // CAN0\r
+#define INT_CAN1 56 // CAN1\r
+#define INT_ETH 58 // Ethernet\r
+#define INT_HIBERNATE 59 // Hibernation module\r
+\r
+//*****************************************************************************\r
+//\r
+// The total number of interrupts.\r
+//\r
+//*****************************************************************************\r
+#define NUM_INTERRUPTS 60\r
+\r
+//*****************************************************************************\r
+//\r
+// The total number of priority levels.\r
+//\r
+//*****************************************************************************\r
+#define NUM_PRIORITY 8\r
+#define NUM_PRIORITY_BITS 3\r
+\r
+#endif // __HW_INTS_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_memmap.h - Macros defining the memory map of Stellaris.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_MEMMAP_H__\r
+#define __HW_MEMMAP_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the base address of the memories and peripherals.\r
+//\r
+//*****************************************************************************\r
+#define FLASH_BASE 0x00000000 // FLASH memory\r
+#define SRAM_BASE 0x20000000 // SRAM memory\r
+#define WATCHDOG_BASE 0x40000000 // Watchdog\r
+#define GPIO_PORTA_BASE 0x40004000 // GPIO Port A\r
+#define GPIO_PORTB_BASE 0x40005000 // GPIO Port B\r
+#define GPIO_PORTC_BASE 0x40006000 // GPIO Port C\r
+#define GPIO_PORTD_BASE 0x40007000 // GPIO Port D\r
+#define SSI_BASE 0x40008000 // SSI\r
+#define SSI0_BASE 0x40008000 // SSI0\r
+#define SSI1_BASE 0x40009000 // SSI1\r
+#define UART0_BASE 0x4000C000 // UART0\r
+#define UART1_BASE 0x4000D000 // UART1\r
+#define UART2_BASE 0x4000E000 // UART2\r
+#define I2C_MASTER_BASE 0x40020000 // I2C Master\r
+#define I2C_SLAVE_BASE 0x40020800 // I2C Slave\r
+#define I2C0_MASTER_BASE 0x40020000 // I2C0 Master\r
+#define I2C0_SLAVE_BASE 0x40020800 // I2C0 Slave\r
+#define I2C1_MASTER_BASE 0x40021000 // I2C1 Master\r
+#define I2C1_SLAVE_BASE 0x40021800 // I2C1 Slave\r
+#define GPIO_PORTE_BASE 0x40024000 // GPIO Port E\r
+#define GPIO_PORTF_BASE 0x40025000 // GPIO Port F\r
+#define GPIO_PORTG_BASE 0x40026000 // GPIO Port G\r
+#define GPIO_PORTH_BASE 0x40027000 // GPIO Port H\r
+#define PWM_BASE 0x40028000 // PWM\r
+#define QEI_BASE 0x4002C000 // QEI\r
+#define QEI0_BASE 0x4002C000 // QEI0\r
+#define QEI1_BASE 0x4002D000 // QEI1\r
+#define TIMER0_BASE 0x40030000 // Timer0\r
+#define TIMER1_BASE 0x40031000 // Timer1\r
+#define TIMER2_BASE 0x40032000 // Timer2\r
+#define TIMER3_BASE 0x40033000 // Timer3\r
+#define ADC_BASE 0x40038000 // ADC\r
+#define COMP_BASE 0x4003C000 // Analog comparators\r
+#define CAN0_BASE 0x40040000 // CAN0\r
+#define CAN1_BASE 0x40041000 // CAN1\r
+#define ETH_BASE 0x40048000 // Ethernet\r
+#define FLASH_CTRL_BASE 0x400FD000 // FLASH Controller\r
+#define SYSCTL_BASE 0x400FE000 // System Control\r
+#define ITM_BASE 0xE0000000 // Instrumentation Trace Macrocell\r
+#define DWT_BASE 0xE0001000 // Data Watchpoint and Trace\r
+#define FPB_BASE 0xE0002000 // FLASH Patch and Breakpoint\r
+#define NVIC_BASE 0xE000E000 // Nested Vectored Interrupt Ctrl\r
+#define TPIU_BASE 0xE0040000 // Trace Port Interface Unit\r
+\r
+#endif // __HW_MEMMAP_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_nvic.h - Macros used when accessing the NVIC hardware.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_NVIC_H__\r
+#define __HW_NVIC_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the addresses of the NVIC registers.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_INT_TYPE 0xE000E004 // Interrupt Controller Type Reg.\r
+#define NVIC_ST_CTRL 0xE000E010 // SysTick Control and Status Reg.\r
+#define NVIC_ST_RELOAD 0xE000E014 // SysTick Reload Value Register\r
+#define NVIC_ST_CURRENT 0xE000E018 // SysTick Current Value Register\r
+#define NVIC_ST_CAL 0xE000E01C // SysTick Calibration Value Reg.\r
+#define NVIC_EN0 0xE000E100 // IRQ 0 to 31 Set Enable Register\r
+#define NVIC_EN1 0xE000E104 // IRQ 32 to 63 Set Enable Register\r
+#define NVIC_DIS0 0xE000E180 // IRQ 0 to 31 Clear Enable Reg.\r
+#define NVIC_DIS1 0xE000E184 // IRQ 32 to 63 Clear Enable Reg.\r
+#define NVIC_PEND0 0xE000E200 // IRQ 0 to 31 Set Pending Register\r
+#define NVIC_PEND1 0xE000E204 // IRQ 32 to 63 Set Pending Reg.\r
+#define NVIC_UNPEND0 0xE000E280 // IRQ 0 to 31 Clear Pending Reg.\r
+#define NVIC_UNPEND1 0xE000E284 // IRQ 32 to 63 Clear Pending Reg.\r
+#define NVIC_ACTIVE0 0xE000E300 // IRQ 0 to 31 Active Register\r
+#define NVIC_ACTIVE1 0xE000E304 // IRQ 32 to 63 Active Register\r
+#define NVIC_PRI0 0xE000E400 // IRQ 0 to 3 Priority Register\r
+#define NVIC_PRI1 0xE000E404 // IRQ 4 to 7 Priority Register\r
+#define NVIC_PRI2 0xE000E408 // IRQ 8 to 11 Priority Register\r
+#define NVIC_PRI3 0xE000E40C // IRQ 12 to 15 Priority Register\r
+#define NVIC_PRI4 0xE000E410 // IRQ 16 to 19 Priority Register\r
+#define NVIC_PRI5 0xE000E414 // IRQ 20 to 23 Priority Register\r
+#define NVIC_PRI6 0xE000E418 // IRQ 24 to 27 Priority Register\r
+#define NVIC_PRI7 0xE000E41C // IRQ 28 to 31 Priority Register\r
+#define NVIC_PRI8 0xE000E420 // IRQ 32 to 35 Priority Register\r
+#define NVIC_PRI9 0xE000E424 // IRQ 36 to 39 Priority Register\r
+#define NVIC_PRI10 0xE000E428 // IRQ 40 to 43 Priority Register\r
+#define NVIC_CPUID 0xE000ED00 // CPUID Base Register\r
+#define NVIC_INT_CTRL 0xE000ED04 // Interrupt Control State Register\r
+#define NVIC_VTABLE 0xE000ED08 // Vector Table Offset Register\r
+#define NVIC_APINT 0xE000ED0C // App. Int & Reset Control Reg.\r
+#define NVIC_SYS_CTRL 0xE000ED10 // System Control Register\r
+#define NVIC_CFG_CTRL 0xE000ED14 // Configuration Control Register\r
+#define NVIC_SYS_PRI1 0xE000ED18 // Sys. Handlers 4 to 7 Priority\r
+#define NVIC_SYS_PRI2 0xE000ED1C // Sys. Handlers 8 to 11 Priority\r
+#define NVIC_SYS_PRI3 0xE000ED20 // Sys. Handlers 12 to 15 Priority\r
+#define NVIC_SYS_HND_CTRL 0xE000ED24 // System Handler Control and State\r
+#define NVIC_FAULT_STAT 0xE000ED28 // Configurable Fault Status Reg.\r
+#define NVIC_HFAULT_STAT 0xE000ED2C // Hard Fault Status Register\r
+#define NVIC_DEBUG_STAT 0xE000ED30 // Debug Status Register\r
+#define NVIC_MM_ADDR 0xE000ED34 // Mem Manage Address Register\r
+#define NVIC_FAULT_ADDR 0xE000ED38 // Bus Fault Address Register\r
+#define NVIC_MPU_TYPE 0xE000ED90 // MPU Type Register\r
+#define NVIC_MPU_CTRL 0xE000ED94 // MPU Control Register\r
+#define NVIC_MPU_NUMBER 0xE000ED98 // MPU Region Number Register\r
+#define NVIC_MPU_BASE 0xE000ED9C // MPU Region Base Address Register\r
+#define NVIC_MPU_ATTR 0xE000EDA0 // MPU Region Attribute & Size Reg.\r
+#define NVIC_DBG_CTRL 0xE000EDF0 // Debug Control and Status Reg.\r
+#define NVIC_DBG_XFER 0xE000EDF4 // Debug Core Reg. Transfer Select\r
+#define NVIC_DBG_DATA 0xE000EDF8 // Debug Core Register Data\r
+#define NVIC_DBG_INT 0xE000EDFC // Debug Reset Interrupt Control\r
+#define NVIC_SW_TRIG 0xE000EF00 // Software Trigger Interrupt Reg.\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_INT_TYPE register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_INT_TYPE_LINES_M 0x0000001F // Number of interrupt lines (x32)\r
+#define NVIC_INT_TYPE_LINES_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_ST_CTRL register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_ST_CTRL_COUNT 0x00010000 // Count flag\r
+#define NVIC_ST_CTRL_CLK_SRC 0x00000004 // Clock Source\r
+#define NVIC_ST_CTRL_INTEN 0x00000002 // Interrupt enable\r
+#define NVIC_ST_CTRL_ENABLE 0x00000001 // Counter mode\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_ST_RELOAD register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_ST_RELOAD_M 0x00FFFFFF // Counter load value\r
+#define NVIC_ST_RELOAD_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_ST_CURRENT register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_ST_CURRENT_M 0x00FFFFFF // Counter current value\r
+#define NVIC_ST_CURRENT_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_ST_CAL register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_ST_CAL_NOREF 0x80000000 // No reference clock\r
+#define NVIC_ST_CAL_SKEW 0x40000000 // Clock skew\r
+#define NVIC_ST_CAL_ONEMS_M 0x00FFFFFF // 1ms reference value\r
+#define NVIC_ST_CAL_ONEMS_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_EN0 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_EN0_INT31 0x80000000 // Interrupt 31 enable\r
+#define NVIC_EN0_INT30 0x40000000 // Interrupt 30 enable\r
+#define NVIC_EN0_INT29 0x20000000 // Interrupt 29 enable\r
+#define NVIC_EN0_INT28 0x10000000 // Interrupt 28 enable\r
+#define NVIC_EN0_INT27 0x08000000 // Interrupt 27 enable\r
+#define NVIC_EN0_INT26 0x04000000 // Interrupt 26 enable\r
+#define NVIC_EN0_INT25 0x02000000 // Interrupt 25 enable\r
+#define NVIC_EN0_INT24 0x01000000 // Interrupt 24 enable\r
+#define NVIC_EN0_INT23 0x00800000 // Interrupt 23 enable\r
+#define NVIC_EN0_INT22 0x00400000 // Interrupt 22 enable\r
+#define NVIC_EN0_INT21 0x00200000 // Interrupt 21 enable\r
+#define NVIC_EN0_INT20 0x00100000 // Interrupt 20 enable\r
+#define NVIC_EN0_INT19 0x00080000 // Interrupt 19 enable\r
+#define NVIC_EN0_INT18 0x00040000 // Interrupt 18 enable\r
+#define NVIC_EN0_INT17 0x00020000 // Interrupt 17 enable\r
+#define NVIC_EN0_INT16 0x00010000 // Interrupt 16 enable\r
+#define NVIC_EN0_INT15 0x00008000 // Interrupt 15 enable\r
+#define NVIC_EN0_INT14 0x00004000 // Interrupt 14 enable\r
+#define NVIC_EN0_INT13 0x00002000 // Interrupt 13 enable\r
+#define NVIC_EN0_INT12 0x00001000 // Interrupt 12 enable\r
+#define NVIC_EN0_INT11 0x00000800 // Interrupt 11 enable\r
+#define NVIC_EN0_INT10 0x00000400 // Interrupt 10 enable\r
+#define NVIC_EN0_INT9 0x00000200 // Interrupt 9 enable\r
+#define NVIC_EN0_INT8 0x00000100 // Interrupt 8 enable\r
+#define NVIC_EN0_INT7 0x00000080 // Interrupt 7 enable\r
+#define NVIC_EN0_INT6 0x00000040 // Interrupt 6 enable\r
+#define NVIC_EN0_INT5 0x00000020 // Interrupt 5 enable\r
+#define NVIC_EN0_INT4 0x00000010 // Interrupt 4 enable\r
+#define NVIC_EN0_INT3 0x00000008 // Interrupt 3 enable\r
+#define NVIC_EN0_INT2 0x00000004 // Interrupt 2 enable\r
+#define NVIC_EN0_INT1 0x00000002 // Interrupt 1 enable\r
+#define NVIC_EN0_INT0 0x00000001 // Interrupt 0 enable\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_EN1 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_EN1_INT59 0x08000000 // Interrupt 59 enable\r
+#define NVIC_EN1_INT58 0x04000000 // Interrupt 58 enable\r
+#define NVIC_EN1_INT57 0x02000000 // Interrupt 57 enable\r
+#define NVIC_EN1_INT56 0x01000000 // Interrupt 56 enable\r
+#define NVIC_EN1_INT55 0x00800000 // Interrupt 55 enable\r
+#define NVIC_EN1_INT54 0x00400000 // Interrupt 54 enable\r
+#define NVIC_EN1_INT53 0x00200000 // Interrupt 53 enable\r
+#define NVIC_EN1_INT52 0x00100000 // Interrupt 52 enable\r
+#define NVIC_EN1_INT51 0x00080000 // Interrupt 51 enable\r
+#define NVIC_EN1_INT50 0x00040000 // Interrupt 50 enable\r
+#define NVIC_EN1_INT49 0x00020000 // Interrupt 49 enable\r
+#define NVIC_EN1_INT48 0x00010000 // Interrupt 48 enable\r
+#define NVIC_EN1_INT47 0x00008000 // Interrupt 47 enable\r
+#define NVIC_EN1_INT46 0x00004000 // Interrupt 46 enable\r
+#define NVIC_EN1_INT45 0x00002000 // Interrupt 45 enable\r
+#define NVIC_EN1_INT44 0x00001000 // Interrupt 44 enable\r
+#define NVIC_EN1_INT43 0x00000800 // Interrupt 43 enable\r
+#define NVIC_EN1_INT42 0x00000400 // Interrupt 42 enable\r
+#define NVIC_EN1_INT41 0x00000200 // Interrupt 41 enable\r
+#define NVIC_EN1_INT40 0x00000100 // Interrupt 40 enable\r
+#define NVIC_EN1_INT39 0x00000080 // Interrupt 39 enable\r
+#define NVIC_EN1_INT38 0x00000040 // Interrupt 38 enable\r
+#define NVIC_EN1_INT37 0x00000020 // Interrupt 37 enable\r
+#define NVIC_EN1_INT36 0x00000010 // Interrupt 36 enable\r
+#define NVIC_EN1_INT35 0x00000008 // Interrupt 35 enable\r
+#define NVIC_EN1_INT34 0x00000004 // Interrupt 34 enable\r
+#define NVIC_EN1_INT33 0x00000002 // Interrupt 33 enable\r
+#define NVIC_EN1_INT32 0x00000001 // Interrupt 32 enable\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_DIS0 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_DIS0_INT31 0x80000000 // Interrupt 31 disable\r
+#define NVIC_DIS0_INT30 0x40000000 // Interrupt 30 disable\r
+#define NVIC_DIS0_INT29 0x20000000 // Interrupt 29 disable\r
+#define NVIC_DIS0_INT28 0x10000000 // Interrupt 28 disable\r
+#define NVIC_DIS0_INT27 0x08000000 // Interrupt 27 disable\r
+#define NVIC_DIS0_INT26 0x04000000 // Interrupt 26 disable\r
+#define NVIC_DIS0_INT25 0x02000000 // Interrupt 25 disable\r
+#define NVIC_DIS0_INT24 0x01000000 // Interrupt 24 disable\r
+#define NVIC_DIS0_INT23 0x00800000 // Interrupt 23 disable\r
+#define NVIC_DIS0_INT22 0x00400000 // Interrupt 22 disable\r
+#define NVIC_DIS0_INT21 0x00200000 // Interrupt 21 disable\r
+#define NVIC_DIS0_INT20 0x00100000 // Interrupt 20 disable\r
+#define NVIC_DIS0_INT19 0x00080000 // Interrupt 19 disable\r
+#define NVIC_DIS0_INT18 0x00040000 // Interrupt 18 disable\r
+#define NVIC_DIS0_INT17 0x00020000 // Interrupt 17 disable\r
+#define NVIC_DIS0_INT16 0x00010000 // Interrupt 16 disable\r
+#define NVIC_DIS0_INT15 0x00008000 // Interrupt 15 disable\r
+#define NVIC_DIS0_INT14 0x00004000 // Interrupt 14 disable\r
+#define NVIC_DIS0_INT13 0x00002000 // Interrupt 13 disable\r
+#define NVIC_DIS0_INT12 0x00001000 // Interrupt 12 disable\r
+#define NVIC_DIS0_INT11 0x00000800 // Interrupt 11 disable\r
+#define NVIC_DIS0_INT10 0x00000400 // Interrupt 10 disable\r
+#define NVIC_DIS0_INT9 0x00000200 // Interrupt 9 disable\r
+#define NVIC_DIS0_INT8 0x00000100 // Interrupt 8 disable\r
+#define NVIC_DIS0_INT7 0x00000080 // Interrupt 7 disable\r
+#define NVIC_DIS0_INT6 0x00000040 // Interrupt 6 disable\r
+#define NVIC_DIS0_INT5 0x00000020 // Interrupt 5 disable\r
+#define NVIC_DIS0_INT4 0x00000010 // Interrupt 4 disable\r
+#define NVIC_DIS0_INT3 0x00000008 // Interrupt 3 disable\r
+#define NVIC_DIS0_INT2 0x00000004 // Interrupt 2 disable\r
+#define NVIC_DIS0_INT1 0x00000002 // Interrupt 1 disable\r
+#define NVIC_DIS0_INT0 0x00000001 // Interrupt 0 disable\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_DIS1 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_DIS1_INT59 0x08000000 // Interrupt 59 disable\r
+#define NVIC_DIS1_INT58 0x04000000 // Interrupt 58 disable\r
+#define NVIC_DIS1_INT57 0x02000000 // Interrupt 57 disable\r
+#define NVIC_DIS1_INT56 0x01000000 // Interrupt 56 disable\r
+#define NVIC_DIS1_INT55 0x00800000 // Interrupt 55 disable\r
+#define NVIC_DIS1_INT54 0x00400000 // Interrupt 54 disable\r
+#define NVIC_DIS1_INT53 0x00200000 // Interrupt 53 disable\r
+#define NVIC_DIS1_INT52 0x00100000 // Interrupt 52 disable\r
+#define NVIC_DIS1_INT51 0x00080000 // Interrupt 51 disable\r
+#define NVIC_DIS1_INT50 0x00040000 // Interrupt 50 disable\r
+#define NVIC_DIS1_INT49 0x00020000 // Interrupt 49 disable\r
+#define NVIC_DIS1_INT48 0x00010000 // Interrupt 48 disable\r
+#define NVIC_DIS1_INT47 0x00008000 // Interrupt 47 disable\r
+#define NVIC_DIS1_INT46 0x00004000 // Interrupt 46 disable\r
+#define NVIC_DIS1_INT45 0x00002000 // Interrupt 45 disable\r
+#define NVIC_DIS1_INT44 0x00001000 // Interrupt 44 disable\r
+#define NVIC_DIS1_INT43 0x00000800 // Interrupt 43 disable\r
+#define NVIC_DIS1_INT42 0x00000400 // Interrupt 42 disable\r
+#define NVIC_DIS1_INT41 0x00000200 // Interrupt 41 disable\r
+#define NVIC_DIS1_INT40 0x00000100 // Interrupt 40 disable\r
+#define NVIC_DIS1_INT39 0x00000080 // Interrupt 39 disable\r
+#define NVIC_DIS1_INT38 0x00000040 // Interrupt 38 disable\r
+#define NVIC_DIS1_INT37 0x00000020 // Interrupt 37 disable\r
+#define NVIC_DIS1_INT36 0x00000010 // Interrupt 36 disable\r
+#define NVIC_DIS1_INT35 0x00000008 // Interrupt 35 disable\r
+#define NVIC_DIS1_INT34 0x00000004 // Interrupt 34 disable\r
+#define NVIC_DIS1_INT33 0x00000002 // Interrupt 33 disable\r
+#define NVIC_DIS1_INT32 0x00000001 // Interrupt 32 disable\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_PEND0 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_PEND0_INT31 0x80000000 // Interrupt 31 pend\r
+#define NVIC_PEND0_INT30 0x40000000 // Interrupt 30 pend\r
+#define NVIC_PEND0_INT29 0x20000000 // Interrupt 29 pend\r
+#define NVIC_PEND0_INT28 0x10000000 // Interrupt 28 pend\r
+#define NVIC_PEND0_INT27 0x08000000 // Interrupt 27 pend\r
+#define NVIC_PEND0_INT26 0x04000000 // Interrupt 26 pend\r
+#define NVIC_PEND0_INT25 0x02000000 // Interrupt 25 pend\r
+#define NVIC_PEND0_INT24 0x01000000 // Interrupt 24 pend\r
+#define NVIC_PEND0_INT23 0x00800000 // Interrupt 23 pend\r
+#define NVIC_PEND0_INT22 0x00400000 // Interrupt 22 pend\r
+#define NVIC_PEND0_INT21 0x00200000 // Interrupt 21 pend\r
+#define NVIC_PEND0_INT20 0x00100000 // Interrupt 20 pend\r
+#define NVIC_PEND0_INT19 0x00080000 // Interrupt 19 pend\r
+#define NVIC_PEND0_INT18 0x00040000 // Interrupt 18 pend\r
+#define NVIC_PEND0_INT17 0x00020000 // Interrupt 17 pend\r
+#define NVIC_PEND0_INT16 0x00010000 // Interrupt 16 pend\r
+#define NVIC_PEND0_INT15 0x00008000 // Interrupt 15 pend\r
+#define NVIC_PEND0_INT14 0x00004000 // Interrupt 14 pend\r
+#define NVIC_PEND0_INT13 0x00002000 // Interrupt 13 pend\r
+#define NVIC_PEND0_INT12 0x00001000 // Interrupt 12 pend\r
+#define NVIC_PEND0_INT11 0x00000800 // Interrupt 11 pend\r
+#define NVIC_PEND0_INT10 0x00000400 // Interrupt 10 pend\r
+#define NVIC_PEND0_INT9 0x00000200 // Interrupt 9 pend\r
+#define NVIC_PEND0_INT8 0x00000100 // Interrupt 8 pend\r
+#define NVIC_PEND0_INT7 0x00000080 // Interrupt 7 pend\r
+#define NVIC_PEND0_INT6 0x00000040 // Interrupt 6 pend\r
+#define NVIC_PEND0_INT5 0x00000020 // Interrupt 5 pend\r
+#define NVIC_PEND0_INT4 0x00000010 // Interrupt 4 pend\r
+#define NVIC_PEND0_INT3 0x00000008 // Interrupt 3 pend\r
+#define NVIC_PEND0_INT2 0x00000004 // Interrupt 2 pend\r
+#define NVIC_PEND0_INT1 0x00000002 // Interrupt 1 pend\r
+#define NVIC_PEND0_INT0 0x00000001 // Interrupt 0 pend\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_PEND1 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_PEND1_INT59 0x08000000 // Interrupt 59 pend\r
+#define NVIC_PEND1_INT58 0x04000000 // Interrupt 58 pend\r
+#define NVIC_PEND1_INT57 0x02000000 // Interrupt 57 pend\r
+#define NVIC_PEND1_INT56 0x01000000 // Interrupt 56 pend\r
+#define NVIC_PEND1_INT55 0x00800000 // Interrupt 55 pend\r
+#define NVIC_PEND1_INT54 0x00400000 // Interrupt 54 pend\r
+#define NVIC_PEND1_INT53 0x00200000 // Interrupt 53 pend\r
+#define NVIC_PEND1_INT52 0x00100000 // Interrupt 52 pend\r
+#define NVIC_PEND1_INT51 0x00080000 // Interrupt 51 pend\r
+#define NVIC_PEND1_INT50 0x00040000 // Interrupt 50 pend\r
+#define NVIC_PEND1_INT49 0x00020000 // Interrupt 49 pend\r
+#define NVIC_PEND1_INT48 0x00010000 // Interrupt 48 pend\r
+#define NVIC_PEND1_INT47 0x00008000 // Interrupt 47 pend\r
+#define NVIC_PEND1_INT46 0x00004000 // Interrupt 46 pend\r
+#define NVIC_PEND1_INT45 0x00002000 // Interrupt 45 pend\r
+#define NVIC_PEND1_INT44 0x00001000 // Interrupt 44 pend\r
+#define NVIC_PEND1_INT43 0x00000800 // Interrupt 43 pend\r
+#define NVIC_PEND1_INT42 0x00000400 // Interrupt 42 pend\r
+#define NVIC_PEND1_INT41 0x00000200 // Interrupt 41 pend\r
+#define NVIC_PEND1_INT40 0x00000100 // Interrupt 40 pend\r
+#define NVIC_PEND1_INT39 0x00000080 // Interrupt 39 pend\r
+#define NVIC_PEND1_INT38 0x00000040 // Interrupt 38 pend\r
+#define NVIC_PEND1_INT37 0x00000020 // Interrupt 37 pend\r
+#define NVIC_PEND1_INT36 0x00000010 // Interrupt 36 pend\r
+#define NVIC_PEND1_INT35 0x00000008 // Interrupt 35 pend\r
+#define NVIC_PEND1_INT34 0x00000004 // Interrupt 34 pend\r
+#define NVIC_PEND1_INT33 0x00000002 // Interrupt 33 pend\r
+#define NVIC_PEND1_INT32 0x00000001 // Interrupt 32 pend\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_UNPEND0 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_UNPEND0_INT31 0x80000000 // Interrupt 31 unpend\r
+#define NVIC_UNPEND0_INT30 0x40000000 // Interrupt 30 unpend\r
+#define NVIC_UNPEND0_INT29 0x20000000 // Interrupt 29 unpend\r
+#define NVIC_UNPEND0_INT28 0x10000000 // Interrupt 28 unpend\r
+#define NVIC_UNPEND0_INT27 0x08000000 // Interrupt 27 unpend\r
+#define NVIC_UNPEND0_INT26 0x04000000 // Interrupt 26 unpend\r
+#define NVIC_UNPEND0_INT25 0x02000000 // Interrupt 25 unpend\r
+#define NVIC_UNPEND0_INT24 0x01000000 // Interrupt 24 unpend\r
+#define NVIC_UNPEND0_INT23 0x00800000 // Interrupt 23 unpend\r
+#define NVIC_UNPEND0_INT22 0x00400000 // Interrupt 22 unpend\r
+#define NVIC_UNPEND0_INT21 0x00200000 // Interrupt 21 unpend\r
+#define NVIC_UNPEND0_INT20 0x00100000 // Interrupt 20 unpend\r
+#define NVIC_UNPEND0_INT19 0x00080000 // Interrupt 19 unpend\r
+#define NVIC_UNPEND0_INT18 0x00040000 // Interrupt 18 unpend\r
+#define NVIC_UNPEND0_INT17 0x00020000 // Interrupt 17 unpend\r
+#define NVIC_UNPEND0_INT16 0x00010000 // Interrupt 16 unpend\r
+#define NVIC_UNPEND0_INT15 0x00008000 // Interrupt 15 unpend\r
+#define NVIC_UNPEND0_INT14 0x00004000 // Interrupt 14 unpend\r
+#define NVIC_UNPEND0_INT13 0x00002000 // Interrupt 13 unpend\r
+#define NVIC_UNPEND0_INT12 0x00001000 // Interrupt 12 unpend\r
+#define NVIC_UNPEND0_INT11 0x00000800 // Interrupt 11 unpend\r
+#define NVIC_UNPEND0_INT10 0x00000400 // Interrupt 10 unpend\r
+#define NVIC_UNPEND0_INT9 0x00000200 // Interrupt 9 unpend\r
+#define NVIC_UNPEND0_INT8 0x00000100 // Interrupt 8 unpend\r
+#define NVIC_UNPEND0_INT7 0x00000080 // Interrupt 7 unpend\r
+#define NVIC_UNPEND0_INT6 0x00000040 // Interrupt 6 unpend\r
+#define NVIC_UNPEND0_INT5 0x00000020 // Interrupt 5 unpend\r
+#define NVIC_UNPEND0_INT4 0x00000010 // Interrupt 4 unpend\r
+#define NVIC_UNPEND0_INT3 0x00000008 // Interrupt 3 unpend\r
+#define NVIC_UNPEND0_INT2 0x00000004 // Interrupt 2 unpend\r
+#define NVIC_UNPEND0_INT1 0x00000002 // Interrupt 1 unpend\r
+#define NVIC_UNPEND0_INT0 0x00000001 // Interrupt 0 unpend\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_UNPEND1 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_UNPEND1_INT59 0x08000000 // Interrupt 59 unpend\r
+#define NVIC_UNPEND1_INT58 0x04000000 // Interrupt 58 unpend\r
+#define NVIC_UNPEND1_INT57 0x02000000 // Interrupt 57 unpend\r
+#define NVIC_UNPEND1_INT56 0x01000000 // Interrupt 56 unpend\r
+#define NVIC_UNPEND1_INT55 0x00800000 // Interrupt 55 unpend\r
+#define NVIC_UNPEND1_INT54 0x00400000 // Interrupt 54 unpend\r
+#define NVIC_UNPEND1_INT53 0x00200000 // Interrupt 53 unpend\r
+#define NVIC_UNPEND1_INT52 0x00100000 // Interrupt 52 unpend\r
+#define NVIC_UNPEND1_INT51 0x00080000 // Interrupt 51 unpend\r
+#define NVIC_UNPEND1_INT50 0x00040000 // Interrupt 50 unpend\r
+#define NVIC_UNPEND1_INT49 0x00020000 // Interrupt 49 unpend\r
+#define NVIC_UNPEND1_INT48 0x00010000 // Interrupt 48 unpend\r
+#define NVIC_UNPEND1_INT47 0x00008000 // Interrupt 47 unpend\r
+#define NVIC_UNPEND1_INT46 0x00004000 // Interrupt 46 unpend\r
+#define NVIC_UNPEND1_INT45 0x00002000 // Interrupt 45 unpend\r
+#define NVIC_UNPEND1_INT44 0x00001000 // Interrupt 44 unpend\r
+#define NVIC_UNPEND1_INT43 0x00000800 // Interrupt 43 unpend\r
+#define NVIC_UNPEND1_INT42 0x00000400 // Interrupt 42 unpend\r
+#define NVIC_UNPEND1_INT41 0x00000200 // Interrupt 41 unpend\r
+#define NVIC_UNPEND1_INT40 0x00000100 // Interrupt 40 unpend\r
+#define NVIC_UNPEND1_INT39 0x00000080 // Interrupt 39 unpend\r
+#define NVIC_UNPEND1_INT38 0x00000040 // Interrupt 38 unpend\r
+#define NVIC_UNPEND1_INT37 0x00000020 // Interrupt 37 unpend\r
+#define NVIC_UNPEND1_INT36 0x00000010 // Interrupt 36 unpend\r
+#define NVIC_UNPEND1_INT35 0x00000008 // Interrupt 35 unpend\r
+#define NVIC_UNPEND1_INT34 0x00000004 // Interrupt 34 unpend\r
+#define NVIC_UNPEND1_INT33 0x00000002 // Interrupt 33 unpend\r
+#define NVIC_UNPEND1_INT32 0x00000001 // Interrupt 32 unpend\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_ACTIVE0 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_ACTIVE0_INT31 0x80000000 // Interrupt 31 active\r
+#define NVIC_ACTIVE0_INT30 0x40000000 // Interrupt 30 active\r
+#define NVIC_ACTIVE0_INT29 0x20000000 // Interrupt 29 active\r
+#define NVIC_ACTIVE0_INT28 0x10000000 // Interrupt 28 active\r
+#define NVIC_ACTIVE0_INT27 0x08000000 // Interrupt 27 active\r
+#define NVIC_ACTIVE0_INT26 0x04000000 // Interrupt 26 active\r
+#define NVIC_ACTIVE0_INT25 0x02000000 // Interrupt 25 active\r
+#define NVIC_ACTIVE0_INT24 0x01000000 // Interrupt 24 active\r
+#define NVIC_ACTIVE0_INT23 0x00800000 // Interrupt 23 active\r
+#define NVIC_ACTIVE0_INT22 0x00400000 // Interrupt 22 active\r
+#define NVIC_ACTIVE0_INT21 0x00200000 // Interrupt 21 active\r
+#define NVIC_ACTIVE0_INT20 0x00100000 // Interrupt 20 active\r
+#define NVIC_ACTIVE0_INT19 0x00080000 // Interrupt 19 active\r
+#define NVIC_ACTIVE0_INT18 0x00040000 // Interrupt 18 active\r
+#define NVIC_ACTIVE0_INT17 0x00020000 // Interrupt 17 active\r
+#define NVIC_ACTIVE0_INT16 0x00010000 // Interrupt 16 active\r
+#define NVIC_ACTIVE0_INT15 0x00008000 // Interrupt 15 active\r
+#define NVIC_ACTIVE0_INT14 0x00004000 // Interrupt 14 active\r
+#define NVIC_ACTIVE0_INT13 0x00002000 // Interrupt 13 active\r
+#define NVIC_ACTIVE0_INT12 0x00001000 // Interrupt 12 active\r
+#define NVIC_ACTIVE0_INT11 0x00000800 // Interrupt 11 active\r
+#define NVIC_ACTIVE0_INT10 0x00000400 // Interrupt 10 active\r
+#define NVIC_ACTIVE0_INT9 0x00000200 // Interrupt 9 active\r
+#define NVIC_ACTIVE0_INT8 0x00000100 // Interrupt 8 active\r
+#define NVIC_ACTIVE0_INT7 0x00000080 // Interrupt 7 active\r
+#define NVIC_ACTIVE0_INT6 0x00000040 // Interrupt 6 active\r
+#define NVIC_ACTIVE0_INT5 0x00000020 // Interrupt 5 active\r
+#define NVIC_ACTIVE0_INT4 0x00000010 // Interrupt 4 active\r
+#define NVIC_ACTIVE0_INT3 0x00000008 // Interrupt 3 active\r
+#define NVIC_ACTIVE0_INT2 0x00000004 // Interrupt 2 active\r
+#define NVIC_ACTIVE0_INT1 0x00000002 // Interrupt 1 active\r
+#define NVIC_ACTIVE0_INT0 0x00000001 // Interrupt 0 active\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_ACTIVE1 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_ACTIVE1_INT59 0x08000000 // Interrupt 59 active\r
+#define NVIC_ACTIVE1_INT58 0x04000000 // Interrupt 58 active\r
+#define NVIC_ACTIVE1_INT57 0x02000000 // Interrupt 57 active\r
+#define NVIC_ACTIVE1_INT56 0x01000000 // Interrupt 56 active\r
+#define NVIC_ACTIVE1_INT55 0x00800000 // Interrupt 55 active\r
+#define NVIC_ACTIVE1_INT54 0x00400000 // Interrupt 54 active\r
+#define NVIC_ACTIVE1_INT53 0x00200000 // Interrupt 53 active\r
+#define NVIC_ACTIVE1_INT52 0x00100000 // Interrupt 52 active\r
+#define NVIC_ACTIVE1_INT51 0x00080000 // Interrupt 51 active\r
+#define NVIC_ACTIVE1_INT50 0x00040000 // Interrupt 50 active\r
+#define NVIC_ACTIVE1_INT49 0x00020000 // Interrupt 49 active\r
+#define NVIC_ACTIVE1_INT48 0x00010000 // Interrupt 48 active\r
+#define NVIC_ACTIVE1_INT47 0x00008000 // Interrupt 47 active\r
+#define NVIC_ACTIVE1_INT46 0x00004000 // Interrupt 46 active\r
+#define NVIC_ACTIVE1_INT45 0x00002000 // Interrupt 45 active\r
+#define NVIC_ACTIVE1_INT44 0x00001000 // Interrupt 44 active\r
+#define NVIC_ACTIVE1_INT43 0x00000800 // Interrupt 43 active\r
+#define NVIC_ACTIVE1_INT42 0x00000400 // Interrupt 42 active\r
+#define NVIC_ACTIVE1_INT41 0x00000200 // Interrupt 41 active\r
+#define NVIC_ACTIVE1_INT40 0x00000100 // Interrupt 40 active\r
+#define NVIC_ACTIVE1_INT39 0x00000080 // Interrupt 39 active\r
+#define NVIC_ACTIVE1_INT38 0x00000040 // Interrupt 38 active\r
+#define NVIC_ACTIVE1_INT37 0x00000020 // Interrupt 37 active\r
+#define NVIC_ACTIVE1_INT36 0x00000010 // Interrupt 36 active\r
+#define NVIC_ACTIVE1_INT35 0x00000008 // Interrupt 35 active\r
+#define NVIC_ACTIVE1_INT34 0x00000004 // Interrupt 34 active\r
+#define NVIC_ACTIVE1_INT33 0x00000002 // Interrupt 33 active\r
+#define NVIC_ACTIVE1_INT32 0x00000001 // Interrupt 32 active\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_PRI0 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_PRI0_INT3_M 0xFF000000 // Interrupt 3 priority mask\r
+#define NVIC_PRI0_INT2_M 0x00FF0000 // Interrupt 2 priority mask\r
+#define NVIC_PRI0_INT1_M 0x0000FF00 // Interrupt 1 priority mask\r
+#define NVIC_PRI0_INT0_M 0x000000FF // Interrupt 0 priority mask\r
+#define NVIC_PRI0_INT3_S 24\r
+#define NVIC_PRI0_INT2_S 16\r
+#define NVIC_PRI0_INT1_S 8\r
+#define NVIC_PRI0_INT0_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_PRI1 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_PRI1_INT7_M 0xFF000000 // Interrupt 7 priority mask\r
+#define NVIC_PRI1_INT6_M 0x00FF0000 // Interrupt 6 priority mask\r
+#define NVIC_PRI1_INT5_M 0x0000FF00 // Interrupt 5 priority mask\r
+#define NVIC_PRI1_INT4_M 0x000000FF // Interrupt 4 priority mask\r
+#define NVIC_PRI1_INT7_S 24\r
+#define NVIC_PRI1_INT6_S 16\r
+#define NVIC_PRI1_INT5_S 8\r
+#define NVIC_PRI1_INT4_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_PRI2 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_PRI2_INT11_M 0xFF000000 // Interrupt 11 priority mask\r
+#define NVIC_PRI2_INT10_M 0x00FF0000 // Interrupt 10 priority mask\r
+#define NVIC_PRI2_INT9_M 0x0000FF00 // Interrupt 9 priority mask\r
+#define NVIC_PRI2_INT8_M 0x000000FF // Interrupt 8 priority mask\r
+#define NVIC_PRI2_INT11_S 24\r
+#define NVIC_PRI2_INT10_S 16\r
+#define NVIC_PRI2_INT9_S 8\r
+#define NVIC_PRI2_INT8_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_PRI3 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_PRI3_INT15_M 0xFF000000 // Interrupt 15 priority mask\r
+#define NVIC_PRI3_INT14_M 0x00FF0000 // Interrupt 14 priority mask\r
+#define NVIC_PRI3_INT13_M 0x0000FF00 // Interrupt 13 priority mask\r
+#define NVIC_PRI3_INT12_M 0x000000FF // Interrupt 12 priority mask\r
+#define NVIC_PRI3_INT15_S 24\r
+#define NVIC_PRI3_INT14_S 16\r
+#define NVIC_PRI3_INT13_S 8\r
+#define NVIC_PRI3_INT12_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_PRI4 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_PRI4_INT19_M 0xFF000000 // Interrupt 19 priority mask\r
+#define NVIC_PRI4_INT18_M 0x00FF0000 // Interrupt 18 priority mask\r
+#define NVIC_PRI4_INT17_M 0x0000FF00 // Interrupt 17 priority mask\r
+#define NVIC_PRI4_INT16_M 0x000000FF // Interrupt 16 priority mask\r
+#define NVIC_PRI4_INT19_S 24\r
+#define NVIC_PRI4_INT18_S 16\r
+#define NVIC_PRI4_INT17_S 8\r
+#define NVIC_PRI4_INT16_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_PRI5 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_PRI5_INT23_M 0xFF000000 // Interrupt 23 priority mask\r
+#define NVIC_PRI5_INT22_M 0x00FF0000 // Interrupt 22 priority mask\r
+#define NVIC_PRI5_INT21_M 0x0000FF00 // Interrupt 21 priority mask\r
+#define NVIC_PRI5_INT20_M 0x000000FF // Interrupt 20 priority mask\r
+#define NVIC_PRI5_INT23_S 24\r
+#define NVIC_PRI5_INT22_S 16\r
+#define NVIC_PRI5_INT21_S 8\r
+#define NVIC_PRI5_INT20_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_PRI6 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_PRI6_INT27_M 0xFF000000 // Interrupt 27 priority mask\r
+#define NVIC_PRI6_INT26_M 0x00FF0000 // Interrupt 26 priority mask\r
+#define NVIC_PRI6_INT25_M 0x0000FF00 // Interrupt 25 priority mask\r
+#define NVIC_PRI6_INT24_M 0x000000FF // Interrupt 24 priority mask\r
+#define NVIC_PRI6_INT27_S 24\r
+#define NVIC_PRI6_INT26_S 16\r
+#define NVIC_PRI6_INT25_S 8\r
+#define NVIC_PRI6_INT24_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_PRI7 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_PRI7_INT31_M 0xFF000000 // Interrupt 31 priority mask\r
+#define NVIC_PRI7_INT30_M 0x00FF0000 // Interrupt 30 priority mask\r
+#define NVIC_PRI7_INT29_M 0x0000FF00 // Interrupt 29 priority mask\r
+#define NVIC_PRI7_INT28_M 0x000000FF // Interrupt 28 priority mask\r
+#define NVIC_PRI7_INT31_S 24\r
+#define NVIC_PRI7_INT30_S 16\r
+#define NVIC_PRI7_INT29_S 8\r
+#define NVIC_PRI7_INT28_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_PRI8 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_PRI8_INT35_M 0xFF000000 // Interrupt 35 priority mask\r
+#define NVIC_PRI8_INT34_M 0x00FF0000 // Interrupt 34 priority mask\r
+#define NVIC_PRI8_INT33_M 0x0000FF00 // Interrupt 33 priority mask\r
+#define NVIC_PRI8_INT32_M 0x000000FF // Interrupt 32 priority mask\r
+#define NVIC_PRI8_INT35_S 24\r
+#define NVIC_PRI8_INT34_S 16\r
+#define NVIC_PRI8_INT33_S 8\r
+#define NVIC_PRI8_INT32_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_PRI9 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_PRI9_INT39_M 0xFF000000 // Interrupt 39 priority mask\r
+#define NVIC_PRI9_INT38_M 0x00FF0000 // Interrupt 38 priority mask\r
+#define NVIC_PRI9_INT37_M 0x0000FF00 // Interrupt 37 priority mask\r
+#define NVIC_PRI9_INT36_M 0x000000FF // Interrupt 36 priority mask\r
+#define NVIC_PRI9_INT39_S 24\r
+#define NVIC_PRI9_INT38_S 16\r
+#define NVIC_PRI9_INT37_S 8\r
+#define NVIC_PRI9_INT36_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_PRI10 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_PRI10_INT43_M 0xFF000000 // Interrupt 43 priority mask\r
+#define NVIC_PRI10_INT42_M 0x00FF0000 // Interrupt 42 priority mask\r
+#define NVIC_PRI10_INT41_M 0x0000FF00 // Interrupt 41 priority mask\r
+#define NVIC_PRI10_INT40_M 0x000000FF // Interrupt 40 priority mask\r
+#define NVIC_PRI10_INT43_S 24\r
+#define NVIC_PRI10_INT42_S 16\r
+#define NVIC_PRI10_INT41_S 8\r
+#define NVIC_PRI10_INT40_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_CPUID register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_CPUID_IMP_M 0xFF000000 // Implementer\r
+#define NVIC_CPUID_VAR_M 0x00F00000 // Variant\r
+#define NVIC_CPUID_PARTNO_M 0x0000FFF0 // Processor part number\r
+#define NVIC_CPUID_REV_M 0x0000000F // Revision\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_INT_CTRL register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_INT_CTRL_NMI_SET 0x80000000 // Pend a NMI\r
+#define NVIC_INT_CTRL_PEND_SV 0x10000000 // Pend a PendSV\r
+#define NVIC_INT_CTRL_UNPEND_SV 0x08000000 // Unpend a PendSV\r
+#define NVIC_INT_CTRL_ISR_PRE 0x00800000 // Debug interrupt handling\r
+#define NVIC_INT_CTRL_ISR_PEND 0x00400000 // Debug interrupt pending\r
+#define NVIC_INT_CTRL_VEC_PEN_M 0x003FF000 // Highest pending exception\r
+#define NVIC_INT_CTRL_RET_BASE 0x00000800 // Return to base\r
+#define NVIC_INT_CTRL_VEC_ACT_M 0x000003FF // Current active exception\r
+#define NVIC_INT_CTRL_VEC_PEN_S 12\r
+#define NVIC_INT_CTRL_VEC_ACT_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_VTABLE register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_VTABLE_BASE 0x20000000 // Vector table base\r
+#define NVIC_VTABLE_OFFSET_M 0x1FFFFF00 // Vector table offset\r
+#define NVIC_VTABLE_OFFSET_S 8\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_APINT register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_APINT_VECTKEY_M 0xFFFF0000 // Vector key mask\r
+#define NVIC_APINT_VECTKEY 0x05FA0000 // Vector key\r
+#define NVIC_APINT_ENDIANESS 0x00008000 // Data endianess\r
+#define NVIC_APINT_PRIGROUP_M 0x00000700 // Priority group\r
+#define NVIC_APINT_PRIGROUP_7_1 0x00000000 // Priority group 7.1 split\r
+#define NVIC_APINT_PRIGROUP_6_2 0x00000100 // Priority group 6.2 split\r
+#define NVIC_APINT_PRIGROUP_5_3 0x00000200 // Priority group 5.3 split\r
+#define NVIC_APINT_PRIGROUP_4_4 0x00000300 // Priority group 4.4 split\r
+#define NVIC_APINT_PRIGROUP_3_5 0x00000400 // Priority group 3.5 split\r
+#define NVIC_APINT_PRIGROUP_2_6 0x00000500 // Priority group 2.6 split\r
+#define NVIC_APINT_PRIGROUP_1_7 0x00000600 // Priority group 1.7 split\r
+#define NVIC_APINT_PRIGROUP_0_8 0x00000700 // Priority group 0.8 split\r
+#define NVIC_APINT_SYSRESETREQ 0x00000004 // System reset request\r
+#define NVIC_APINT_VECT_CLR_ACT 0x00000002 // Clear active NMI/fault info\r
+#define NVIC_APINT_VECT_RESET 0x00000001 // System reset\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_SYS_CTRL register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_SYS_CTRL_SEVONPEND 0x00000010 // Wakeup on pend\r
+#define NVIC_SYS_CTRL_SLEEPDEEP 0x00000004 // Deep sleep enable\r
+#define NVIC_SYS_CTRL_SLEEPEXIT 0x00000002 // Sleep on ISR exit\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_CFG_CTRL register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_CFG_CTRL_BFHFNMIGN 0x00000100 // Ignore bus fault in NMI/fault\r
+#define NVIC_CFG_CTRL_DIV0 0x00000010 // Trap on divide by 0\r
+#define NVIC_CFG_CTRL_UNALIGNED 0x00000008 // Trap on unaligned access\r
+#define NVIC_CFG_CTRL_DEEP_PEND 0x00000004 // Allow deep interrupt trigger\r
+#define NVIC_CFG_CTRL_MAIN_PEND 0x00000002 // Allow main interrupt trigger\r
+#define NVIC_CFG_CTRL_BASE_THR 0x00000001 // Thread state control\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_SYS_PRI1 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_SYS_PRI1_RES_M 0xFF000000 // Priority of reserved handler\r
+#define NVIC_SYS_PRI1_USAGE_M 0x00FF0000 // Priority of usage fault handler\r
+#define NVIC_SYS_PRI1_BUS_M 0x0000FF00 // Priority of bus fault handler\r
+#define NVIC_SYS_PRI1_MEM_M 0x000000FF // Priority of mem manage handler\r
+#define NVIC_SYS_PRI1_USAGE_S 16\r
+#define NVIC_SYS_PRI1_BUS_S 8\r
+#define NVIC_SYS_PRI1_MEM_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_SYS_PRI2 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_SYS_PRI2_SVC_M 0xFF000000 // Priority of SVCall handler\r
+#define NVIC_SYS_PRI2_RES_M 0x00FFFFFF // Priority of reserved handlers\r
+#define NVIC_SYS_PRI2_SVC_S 24\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_SYS_PRI3 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_SYS_PRI3_TICK_M 0xFF000000 // Priority of Sys Tick handler\r
+#define NVIC_SYS_PRI3_PENDSV_M 0x00FF0000 // Priority of PendSV handler\r
+#define NVIC_SYS_PRI3_RES_M 0x0000FF00 // Priority of reserved handler\r
+#define NVIC_SYS_PRI3_DEBUG_M 0x000000FF // Priority of debug handler\r
+#define NVIC_SYS_PRI3_TICK_S 24\r
+#define NVIC_SYS_PRI3_PENDSV_S 16\r
+#define NVIC_SYS_PRI3_DEBUG_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_SYS_HND_CTRL register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_SYS_HND_CTRL_USAGE 0x00040000 // Usage fault enable\r
+#define NVIC_SYS_HND_CTRL_BUS 0x00020000 // Bus fault enable\r
+#define NVIC_SYS_HND_CTRL_MEM 0x00010000 // Mem manage fault enable\r
+#define NVIC_SYS_HND_CTRL_SVC 0x00008000 // SVCall is pended\r
+#define NVIC_SYS_HND_CTRL_BUSP 0x00004000 // Bus fault is pended\r
+#define NVIC_SYS_HND_CTRL_TICK 0x00000800 // Sys tick is active\r
+#define NVIC_SYS_HND_CTRL_PNDSV 0x00000400 // PendSV is active\r
+#define NVIC_SYS_HND_CTRL_MON 0x00000100 // Monitor is active\r
+#define NVIC_SYS_HND_CTRL_SVCA 0x00000080 // SVCall is active\r
+#define NVIC_SYS_HND_CTRL_USGA 0x00000008 // Usage fault is active\r
+#define NVIC_SYS_HND_CTRL_BUSA 0x00000002 // Bus fault is active\r
+#define NVIC_SYS_HND_CTRL_MEMA 0x00000001 // Mem manage is active\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_FAULT_STAT register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_FAULT_STAT_DIV0 0x02000000 // Divide by zero fault\r
+#define NVIC_FAULT_STAT_UNALIGN 0x01000000 // Unaligned access fault\r
+#define NVIC_FAULT_STAT_NOCP 0x00080000 // No coprocessor fault\r
+#define NVIC_FAULT_STAT_INVPC 0x00040000 // Invalid PC fault\r
+#define NVIC_FAULT_STAT_INVSTAT 0x00020000 // Invalid state fault\r
+#define NVIC_FAULT_STAT_UNDEF 0x00010000 // Undefined instruction fault\r
+#define NVIC_FAULT_STAT_BFARV 0x00008000 // BFAR is valid\r
+#define NVIC_FAULT_STAT_BSTKE 0x00001000 // Stack bus fault\r
+#define NVIC_FAULT_STAT_BUSTKE 0x00000800 // Unstack bus fault\r
+#define NVIC_FAULT_STAT_IMPRE 0x00000400 // Imprecise data bus error\r
+#define NVIC_FAULT_STAT_PRECISE 0x00000200 // Precise data bus error\r
+#define NVIC_FAULT_STAT_IBUS 0x00000100 // Instruction bus fault\r
+#define NVIC_FAULT_STAT_MMARV 0x00000080 // MMAR is valid\r
+#define NVIC_FAULT_STAT_MSTKE 0x00000010 // Stack access violation\r
+#define NVIC_FAULT_STAT_MUSTKE 0x00000008 // Unstack access violation\r
+#define NVIC_FAULT_STAT_DERR 0x00000002 // Data access violation\r
+#define NVIC_FAULT_STAT_IERR 0x00000001 // Instruction access violation\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_HFAULT_STAT register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_HFAULT_STAT_DBG 0x80000000 // Debug event\r
+#define NVIC_HFAULT_STAT_FORCED 0x40000000 // Cannot execute fault handler\r
+#define NVIC_HFAULT_STAT_VECT 0x00000002 // Vector table read fault\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_DEBUG_STAT register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_DEBUG_STAT_EXTRNL 0x00000010 // EDBGRQ asserted\r
+#define NVIC_DEBUG_STAT_VCATCH 0x00000008 // Vector catch\r
+#define NVIC_DEBUG_STAT_DWTTRAP 0x00000004 // DWT match\r
+#define NVIC_DEBUG_STAT_BKPT 0x00000002 // Breakpoint instruction\r
+#define NVIC_DEBUG_STAT_HALTED 0x00000001 // Halt request\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_MM_ADDR register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_MM_ADDR_M 0xFFFFFFFF // Data fault address\r
+#define NVIC_MM_ADDR_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_FAULT_ADDR register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_FAULT_ADDR_M 0xFFFFFFFF // Data bus fault address\r
+#define NVIC_FAULT_ADDR_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_EXC_STACK register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_EXC_STACK_DEEP 0x00000001 // Exception stack\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_EXC_NUM register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_EXC_NUM_M 0x000003FF // Exception number\r
+#define NVIC_EXC_NUM_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_COPRO register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_COPRO_15_M 0xC0000000 // Coprocessor 15 access mask\r
+#define NVIC_COPRO_15_DENIED 0x00000000 // Coprocessor 15 access denied\r
+#define NVIC_COPRO_15_PRIV 0x40000000 // Coprocessor 15 privileged addess\r
+#define NVIC_COPRO_15_FULL 0xC0000000 // Coprocessor 15 full access\r
+#define NVIC_COPRO_14_M 0x30000000 // Coprocessor 14 access mask\r
+#define NVIC_COPRO_14_DENIED 0x00000000 // Coprocessor 14 access denied\r
+#define NVIC_COPRO_14_PRIV 0x10000000 // Coprocessor 14 privileged addess\r
+#define NVIC_COPRO_14_FULL 0x30000000 // Coprocessor 14 full access\r
+#define NVIC_COPRO_13_M 0x0C000000 // Coprocessor 13 access mask\r
+#define NVIC_COPRO_13_DENIED 0x00000000 // Coprocessor 13 access denied\r
+#define NVIC_COPRO_13_PRIV 0x04000000 // Coprocessor 13 privileged addess\r
+#define NVIC_COPRO_13_FULL 0x0C000000 // Coprocessor 13 full access\r
+#define NVIC_COPRO_12_M 0x03000000 // Coprocessor 12 access mask\r
+#define NVIC_COPRO_12_DENIED 0x00000000 // Coprocessor 12 access denied\r
+#define NVIC_COPRO_12_PRIV 0x01000000 // Coprocessor 12 privileged addess\r
+#define NVIC_COPRO_12_FULL 0x03000000 // Coprocessor 12 full access\r
+#define NVIC_COPRO_11_M 0x00C00000 // Coprocessor 11 access mask\r
+#define NVIC_COPRO_11_DENIED 0x00000000 // Coprocessor 11 access denied\r
+#define NVIC_COPRO_11_PRIV 0x00400000 // Coprocessor 11 privileged addess\r
+#define NVIC_COPRO_11_FULL 0x00C00000 // Coprocessor 11 full access\r
+#define NVIC_COPRO_10_M 0x00300000 // Coprocessor 10 access mask\r
+#define NVIC_COPRO_10_DENIED 0x00000000 // Coprocessor 10 access denied\r
+#define NVIC_COPRO_10_PRIV 0x00100000 // Coprocessor 10 privileged addess\r
+#define NVIC_COPRO_10_FULL 0x00300000 // Coprocessor 10 full access\r
+#define NVIC_COPRO_9_M 0x000C0000 // Coprocessor 9 access mask\r
+#define NVIC_COPRO_9_DENIED 0x00000000 // Coprocessor 9 access denied\r
+#define NVIC_COPRO_9_PRIV 0x00040000 // Coprocessor 9 privileged addess\r
+#define NVIC_COPRO_9_FULL 0x000C0000 // Coprocessor 9 full access\r
+#define NVIC_COPRO_8_M 0x00030000 // Coprocessor 8 access mask\r
+#define NVIC_COPRO_8_DENIED 0x00000000 // Coprocessor 8 access denied\r
+#define NVIC_COPRO_8_PRIV 0x00010000 // Coprocessor 8 privileged addess\r
+#define NVIC_COPRO_8_FULL 0x00030000 // Coprocessor 8 full access\r
+#define NVIC_COPRO_7_M 0x0000C000 // Coprocessor 7 access mask\r
+#define NVIC_COPRO_7_DENIED 0x00000000 // Coprocessor 7 access denied\r
+#define NVIC_COPRO_7_PRIV 0x00004000 // Coprocessor 7 privileged addess\r
+#define NVIC_COPRO_7_FULL 0x0000C000 // Coprocessor 7 full access\r
+#define NVIC_COPRO_6_M 0x00003000 // Coprocessor 6 access mask\r
+#define NVIC_COPRO_6_DENIED 0x00000000 // Coprocessor 6 access denied\r
+#define NVIC_COPRO_6_PRIV 0x00001000 // Coprocessor 6 privileged addess\r
+#define NVIC_COPRO_6_FULL 0x00003000 // Coprocessor 6 full access\r
+#define NVIC_COPRO_5_M 0x00000C00 // Coprocessor 5 access mask\r
+#define NVIC_COPRO_5_DENIED 0x00000000 // Coprocessor 5 access denied\r
+#define NVIC_COPRO_5_PRIV 0x00000400 // Coprocessor 5 privileged addess\r
+#define NVIC_COPRO_5_FULL 0x00000C00 // Coprocessor 5 full access\r
+#define NVIC_COPRO_4_M 0x00000300 // Coprocessor 4 access mask\r
+#define NVIC_COPRO_4_DENIED 0x00000000 // Coprocessor 4 access denied\r
+#define NVIC_COPRO_4_PRIV 0x00000100 // Coprocessor 4 privileged addess\r
+#define NVIC_COPRO_4_FULL 0x00000300 // Coprocessor 4 full access\r
+#define NVIC_COPRO_3_M 0x000000C0 // Coprocessor 3 access mask\r
+#define NVIC_COPRO_3_DENIED 0x00000000 // Coprocessor 3 access denied\r
+#define NVIC_COPRO_3_PRIV 0x00000040 // Coprocessor 3 privileged addess\r
+#define NVIC_COPRO_3_FULL 0x000000C0 // Coprocessor 3 full access\r
+#define NVIC_COPRO_2_M 0x00000030 // Coprocessor 2 access mask\r
+#define NVIC_COPRO_2_DENIED 0x00000000 // Coprocessor 2 access denied\r
+#define NVIC_COPRO_2_PRIV 0x00000010 // Coprocessor 2 privileged addess\r
+#define NVIC_COPRO_2_FULL 0x00000030 // Coprocessor 2 full access\r
+#define NVIC_COPRO_1_M 0x0000000C // Coprocessor 1 access mask\r
+#define NVIC_COPRO_1_DENIED 0x00000000 // Coprocessor 1 access denied\r
+#define NVIC_COPRO_1_PRIV 0x00000004 // Coprocessor 1 privileged addess\r
+#define NVIC_COPRO_1_FULL 0x0000000C // Coprocessor 1 full access\r
+#define NVIC_COPRO_0_M 0x00000003 // Coprocessor 0 access mask\r
+#define NVIC_COPRO_0_DENIED 0x00000000 // Coprocessor 0 access denied\r
+#define NVIC_COPRO_0_PRIV 0x00000001 // Coprocessor 0 privileged addess\r
+#define NVIC_COPRO_0_FULL 0x00000003 // Coprocessor 0 full access\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_MPU_TYPE register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_MPU_TYPE_IREGION_M 0x00FF0000 // Number of I regions\r
+#define NVIC_MPU_TYPE_DREGION_M 0x0000FF00 // Number of D regions\r
+#define NVIC_MPU_TYPE_SEPARATE 0x00000001 // Separate or unified MPU\r
+#define NVIC_MPU_TYPE_IREGION_S 16\r
+#define NVIC_MPU_TYPE_DREGION_S 8\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_MPU_CTRL register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_MPU_CTRL_HFNMIENA 0x00000002 // MPU enabled during faults\r
+#define NVIC_MPU_CTRL_ENABLE 0x00000001 // MPU enable\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_MPU_NUMBER register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_MPU_NUMBER_M 0x000000FF // MPU region to access\r
+#define NVIC_MPU_NUMBER_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_MPU_BASE register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_MPU_BASE_ADDR_M 0xFFFFFF00 // Base address\r
+#define NVIC_MPU_BASE_VALID 0x00000010 // Region number valid\r
+#define NVIC_MPU_BASE_REGION_M 0x0000000F // Region number\r
+#define NVIC_MPU_BASE_ADDR_S 8\r
+#define NVIC_MPU_BASE_REGION_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_MPU_ATTR register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_MPU_ATTR_ATTRS 0xFFFF0000 // Attributes\r
+#define NVIC_MPU_ATTR_SRD 0x0000FF00 // Sub-region disable\r
+#define NVIC_MPU_ATTR_SZENABLE 0x000000FF // Region size\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_DBG_CTRL register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_DBG_CTRL_DBGKEY_M 0xFFFF0000 // Debug key mask\r
+#define NVIC_DBG_CTRL_DBGKEY 0xA05F0000 // Debug key\r
+#define NVIC_DBG_CTRL_MON_PEND 0x00008000 // Pend the monitor\r
+#define NVIC_DBG_CTRL_MON_REQ 0x00004000 // Monitor request\r
+#define NVIC_DBG_CTRL_MON_EN 0x00002000 // Debug monitor enable\r
+#define NVIC_DBG_CTRL_MONSTEP 0x00001000 // Monitor step the core\r
+#define NVIC_DBG_CTRL_S_SLEEP 0x00000400 // Core is sleeping\r
+#define NVIC_DBG_CTRL_S_HALT 0x00000200 // Core status on halt\r
+#define NVIC_DBG_CTRL_S_REGRDY 0x00000100 // Register read/write available\r
+#define NVIC_DBG_CTRL_S_LOCKUP 0x00000080 // Core is locked up\r
+#define NVIC_DBG_CTRL_C_RESET 0x00000010 // Reset the core\r
+#define NVIC_DBG_CTRL_C_MASKINT 0x00000008 // Mask interrupts when stepping\r
+#define NVIC_DBG_CTRL_C_STEP 0x00000004 // Step the core\r
+#define NVIC_DBG_CTRL_C_HALT 0x00000002 // Halt the core\r
+#define NVIC_DBG_CTRL_C_DEBUGEN 0x00000001 // Enable debug\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_DBG_XFER register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_DBG_XFER_REG_WNR 0x00010000 // Write or not read\r
+#define NVIC_DBG_XFER_REG_SEL_M 0x0000001F // Register\r
+#define NVIC_DBG_XFER_REG_R0 0x00000000 // Register R0\r
+#define NVIC_DBG_XFER_REG_R1 0x00000001 // Register R1\r
+#define NVIC_DBG_XFER_REG_R2 0x00000002 // Register R2\r
+#define NVIC_DBG_XFER_REG_R3 0x00000003 // Register R3\r
+#define NVIC_DBG_XFER_REG_R4 0x00000004 // Register R4\r
+#define NVIC_DBG_XFER_REG_R5 0x00000005 // Register R5\r
+#define NVIC_DBG_XFER_REG_R6 0x00000006 // Register R6\r
+#define NVIC_DBG_XFER_REG_R7 0x00000007 // Register R7\r
+#define NVIC_DBG_XFER_REG_R8 0x00000008 // Register R8\r
+#define NVIC_DBG_XFER_REG_R9 0x00000009 // Register R9\r
+#define NVIC_DBG_XFER_REG_R10 0x0000000A // Register R10\r
+#define NVIC_DBG_XFER_REG_R11 0x0000000B // Register R11\r
+#define NVIC_DBG_XFER_REG_R12 0x0000000C // Register R12\r
+#define NVIC_DBG_XFER_REG_R13 0x0000000D // Register R13\r
+#define NVIC_DBG_XFER_REG_R14 0x0000000E // Register R14\r
+#define NVIC_DBG_XFER_REG_R15 0x0000000F // Register R15\r
+#define NVIC_DBG_XFER_REG_FLAGS 0x00000010 // xPSR/Flags register\r
+#define NVIC_DBG_XFER_REG_MSP 0x00000011 // Main SP\r
+#define NVIC_DBG_XFER_REG_PSP 0x00000012 // Process SP\r
+#define NVIC_DBG_XFER_REG_DSP 0x00000013 // Deep SP\r
+#define NVIC_DBG_XFER_REG_CFBP 0x00000014 // Control/Fault/BasePri/PriMask\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_DBG_DATA register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_DBG_DATA_M 0xFFFFFFFF // Data temporary cache\r
+#define NVIC_DBG_DATA_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_DBG_INT register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_DBG_INT_HARDERR 0x00000400 // Debug trap on hard fault\r
+#define NVIC_DBG_INT_INTERR 0x00000200 // Debug trap on interrupt errors\r
+#define NVIC_DBG_INT_BUSERR 0x00000100 // Debug trap on bus error\r
+#define NVIC_DBG_INT_STATERR 0x00000080 // Debug trap on usage fault state\r
+#define NVIC_DBG_INT_CHKERR 0x00000040 // Debug trap on usage fault check\r
+#define NVIC_DBG_INT_NOCPERR 0x00000020 // Debug trap on coprocessor error\r
+#define NVIC_DBG_INT_MMERR 0x00000010 // Debug trap on mem manage fault\r
+#define NVIC_DBG_INT_RESET 0x00000008 // Core reset status\r
+#define NVIC_DBG_INT_RSTPENDCLR 0x00000004 // Clear pending core reset\r
+#define NVIC_DBG_INT_RSTPENDING 0x00000002 // Core reset is pending\r
+#define NVIC_DBG_INT_RSTVCATCH 0x00000001 // Reset vector catch\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_SW_TRIG register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_SW_TRIG_INTID_M 0x000003FF // Interrupt to trigger\r
+#define NVIC_SW_TRIG_INTID_S 0\r
+\r
+#endif // __HW_NVIC_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_pwm.h - Defines and Macros for Pulse Width Modulation (PWM) ports\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_PWM_H__\r
+#define __HW_PWM_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// PWM Module Register Offsets.\r
+//\r
+//*****************************************************************************\r
+#define PWM_O_CTL 0x00000000 // PWM Master Control register\r
+#define PWM_O_SYNC 0x00000004 // PWM Time Base Sync register\r
+#define PWM_O_ENABLE 0x00000008 // PWM Output Enable register\r
+#define PWM_O_INVERT 0x0000000C // PWM Output Inversion register\r
+#define PWM_O_FAULT 0x00000010 // PWM Output Fault register\r
+#define PWM_O_INTEN 0x00000014 // PWM Interrupt Enable register\r
+#define PWM_O_RIS 0x00000018 // PWM Interrupt Raw Status reg.\r
+#define PWM_O_ISC 0x0000001C // PWM Interrupt Status register\r
+#define PWM_O_STATUS 0x00000020 // PWM Status register\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the PWM Master Control register.\r
+//\r
+//*****************************************************************************\r
+#define PWM_CTL_GLOBAL_SYNC2 0x00000004 // Global sync generator 2\r
+#define PWM_CTL_GLOBAL_SYNC1 0x00000002 // Global sync generator 1\r
+#define PWM_CTL_GLOBAL_SYNC0 0x00000001 // Global sync generator 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the PWM Time Base Sync register.\r
+//\r
+//*****************************************************************************\r
+#define PWM_SYNC_SYNC2 0x00000004 // Reset generator 2 counter\r
+#define PWM_SYNC_SYNC1 0x00000002 // Reset generator 1 counter\r
+#define PWM_SYNC_SYNC0 0x00000001 // Reset generator 0 counter\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the PWM Output Enable register.\r
+//\r
+//*****************************************************************************\r
+#define PWM_ENABLE_PWM5EN 0x00000020 // PWM5 pin enable\r
+#define PWM_ENABLE_PWM4EN 0x00000010 // PWM4 pin enable\r
+#define PWM_ENABLE_PWM3EN 0x00000008 // PWM3 pin enable\r
+#define PWM_ENABLE_PWM2EN 0x00000004 // PWM2 pin enable\r
+#define PWM_ENABLE_PWM1EN 0x00000002 // PWM1 pin enable\r
+#define PWM_ENABLE_PWM0EN 0x00000001 // PWM0 pin enable\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the PWM Inversion register.\r
+//\r
+//*****************************************************************************\r
+#define PWM_INVERT_PWM5INV 0x00000020 // PWM5 pin invert\r
+#define PWM_INVERT_PWM4INV 0x00000010 // PWM4 pin invert\r
+#define PWM_INVERT_PWM3INV 0x00000008 // PWM3 pin invert\r
+#define PWM_INVERT_PWM2INV 0x00000004 // PWM2 pin invert\r
+#define PWM_INVERT_PWM1INV 0x00000002 // PWM1 pin invert\r
+#define PWM_INVERT_PWM0INV 0x00000001 // PWM0 pin invert\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the PWM Fault register.\r
+//\r
+//*****************************************************************************\r
+#define PWM_FAULT_FAULT5 0x00000020 // PWM5 pin fault\r
+#define PWM_FAULT_FAULT4 0x00000010 // PWM5 pin fault\r
+#define PWM_FAULT_FAULT3 0x00000008 // PWM5 pin fault\r
+#define PWM_FAULT_FAULT2 0x00000004 // PWM5 pin fault\r
+#define PWM_FAULT_FAULT1 0x00000002 // PWM5 pin fault\r
+#define PWM_FAULT_FAULT0 0x00000001 // PWM5 pin fault\r
+\r
+//*****************************************************************************\r
+//\r
+// PWM Interrupt Register bit definitions.\r
+//\r
+//*****************************************************************************\r
+#define PWM_INT_INTFAULT 0x00010000 // Fault interrupt pending\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the PWM Status register.\r
+//\r
+//*****************************************************************************\r
+#define PWM_STATUS_FAULT 0x00000001 // Fault status\r
+\r
+//*****************************************************************************\r
+//\r
+// PWM Generator standard offsets.\r
+//\r
+//*****************************************************************************\r
+#define PWM_GEN_0_OFFSET 0x00000040 // PWM0 base\r
+#define PWM_GEN_1_OFFSET 0x00000080 // PWM1 base\r
+#define PWM_GEN_2_OFFSET 0x000000C0 // PWM2 base\r
+\r
+#define PWM_O_X_CTL 0x00000000 // Gen Control Reg\r
+#define PWM_O_X_INTEN 0x00000004 // Gen Int/Trig Enable Reg\r
+#define PWM_O_X_RIS 0x00000008 // Gen Raw Int Status Reg\r
+#define PWM_O_X_ISC 0x0000000C // Gen Int Status Reg\r
+#define PWM_O_X_LOAD 0x00000010 // Gen Load Reg\r
+#define PWM_O_X_COUNT 0x00000014 // Gen Counter Reg\r
+#define PWM_O_X_CMPA 0x00000018 // Gen Compare A Reg\r
+#define PWM_O_X_CMPB 0x0000001C // Gen Compare B Reg\r
+#define PWM_O_X_GENA 0x00000020 // Gen Generator A Ctrl Reg\r
+#define PWM_O_X_GENB 0x00000024 // Gen Generator B Ctrl Reg\r
+#define PWM_O_X_DBCTL 0x00000028 // Gen Dead Band Ctrl Reg\r
+#define PWM_O_X_DBRISE 0x0000002C // Gen DB Rising Edge Delay Reg\r
+#define PWM_O_X_DBFALL 0x00000030 // Gen DB Falling Edge Delay Reg\r
+\r
+//*****************************************************************************\r
+//\r
+// PWM_X Control Register bit definitions.\r
+//\r
+//*****************************************************************************\r
+#define PWM_X_CTL_ENABLE 0x00000001 // Master enable for gen block\r
+#define PWM_X_CTL_MODE 0x00000002 // Counter mode, down or up/down\r
+#define PWM_X_CTL_DEBUG 0x00000004 // Debug mode\r
+#define PWM_X_CTL_LOADUPD 0x00000008 // Update mode for the load reg\r
+#define PWM_X_CTL_CMPAUPD 0x00000010 // Update mode for comp A reg\r
+#define PWM_X_CTL_CMPBUPD 0x00000020 // Update mode for comp B reg\r
+\r
+//*****************************************************************************\r
+//\r
+// PWM_X Interrupt/Trigger Enable Register bit definitions.\r
+//\r
+//*****************************************************************************\r
+#define PWM_X_INTEN_INTCNTZERO 0x00000001 // Int if COUNT = 0\r
+#define PWM_X_INTEN_INTCNTLOAD 0x00000002 // Int if COUNT = LOAD\r
+#define PWM_X_INTEN_INTCMPAU 0x00000004 // Int if COUNT = CMPA U\r
+#define PWM_X_INTEN_INTCMPAD 0x00000008 // Int if COUNT = CMPA D\r
+#define PWM_X_INTEN_INTCMPBU 0x00000010 // Int if COUNT = CMPA U\r
+#define PWM_X_INTEN_INTCMPBD 0x00000020 // Int if COUNT = CMPA D\r
+#define PWM_X_INTEN_TRCNTZERO 0x00000100 // Trig if COUNT = 0\r
+#define PWM_X_INTEN_TRCNTLOAD 0x00000200 // Trig if COUNT = LOAD\r
+#define PWM_X_INTEN_TRCMPAU 0x00000400 // Trig if COUNT = CMPA U\r
+#define PWM_X_INTEN_TRCMPAD 0x00000800 // Trig if COUNT = CMPA D\r
+#define PWM_X_INTEN_TRCMPBU 0x00001000 // Trig if COUNT = CMPA U\r
+#define PWM_X_INTEN_TRCMPBD 0x00002000 // Trig if COUNT = CMPA D\r
+\r
+//*****************************************************************************\r
+//\r
+// PWM_X Raw Interrupt Status Register bit definitions.\r
+//\r
+//*****************************************************************************\r
+#define PWM_X_RIS_INTCNTZERO 0x00000001 // PWM_X_COUNT = 0 int\r
+#define PWM_X_RIS_INTCNTLOAD 0x00000002 // PWM_X_COUNT = PWM_X_LOAD int\r
+#define PWM_X_RIS_INTCMPAU 0x00000004 // PWM_X_COUNT = PWM_X_CMPA U int\r
+#define PWM_X_RIS_INTCMPAD 0x00000008 // PWM_X_COUNT = PWM_X_CMPA D int\r
+#define PWM_X_RIS_INTCMPBU 0x00000010 // PWM_X_COUNT = PWM_X_CMPB U int\r
+#define PWM_X_RIS_INTCMPBD 0x00000020 // PWM_X_COUNT = PWM_X_CMPB D int\r
+\r
+//*****************************************************************************\r
+//\r
+// PWM_X Interrupt Status Register bit definitions.\r
+//\r
+//*****************************************************************************\r
+#define PWM_X_INT_INTCNTZERO 0x00000001 // PWM_X_COUNT = 0 received\r
+#define PWM_X_INT_INTCNTLOAD 0x00000002 // PWM_X_COUNT = PWM_X_LOAD rcvd\r
+#define PWM_X_INT_INTCMPAU 0x00000004 // PWM_X_COUNT = PWM_X_CMPA U rcvd\r
+#define PWM_X_INT_INTCMPAD 0x00000008 // PWM_X_COUNT = PWM_X_CMPA D rcvd\r
+#define PWM_X_INT_INTCMPBU 0x00000010 // PWM_X_COUNT = PWM_X_CMPB U rcvd\r
+#define PWM_X_INT_INTCMPBD 0x00000020 // PWM_X_COUNT = PWM_X_CMPB D rcvd\r
+\r
+//*****************************************************************************\r
+//\r
+// PWM_X Generator A/B Control Register bit definitions.\r
+//\r
+//*****************************************************************************\r
+#define PWM_X_GEN_Y_ACTZERO 0x00000003 // Act PWM_X_COUNT = 0\r
+#define PWM_X_GEN_Y_ACTLOAD 0x0000000C // Act PWM_X_COUNT = PWM_X_LOAD\r
+#define PWM_X_GEN_Y_ACTCMPAU 0x00000030 // Act PWM_X_COUNT = PWM_X_CMPA U\r
+#define PWM_X_GEN_Y_ACTCMPAD 0x000000C0 // Act PWM_X_COUNT = PWM_X_CMPA D\r
+#define PWM_X_GEN_Y_ACTCMPBU 0x00000300 // Act PWM_X_COUNT = PWM_X_CMPB U\r
+#define PWM_X_GEN_Y_ACTCMPBD 0x00000C00 // Act PWM_X_COUNT = PWM_X_CMPB D\r
+\r
+//*****************************************************************************\r
+//\r
+// PWM_X Generator A/B Control Register action definitions.\r
+//\r
+//*****************************************************************************\r
+#define PWM_GEN_ACT_NONE 0x0 // Do nothing\r
+#define PWM_GEN_ACT_INV 0x1 // Invert the output signal\r
+#define PWM_GEN_ACT_ZERO 0x2 // Set the output signal to zero\r
+#define PWM_GEN_ACT_ONE 0x3 // Set the output signal to one\r
+#define PWM_GEN_ACT_ZERO_SHIFT 0 // Shift amount for the zero action\r
+#define PWM_GEN_ACT_LOAD_SHIFT 2 // Shift amount for the load action\r
+#define PWM_GEN_ACT_A_UP_SHIFT 4 // Shift amount for the A up action\r
+#define PWM_GEN_ACT_A_DN_SHIFT 6 // Shift amount for the A dn action\r
+#define PWM_GEN_ACT_B_UP_SHIFT 8 // Shift amount for the B up action\r
+#define PWM_GEN_ACT_B_DN_SHIFT 10 // Shift amount for the B dn action\r
+\r
+//*****************************************************************************\r
+//\r
+// PWM_X Dead Band Control Register bit definitions.\r
+//\r
+//*****************************************************************************\r
+#define PWM_DBCTL_ENABLE 0x00000001 // Enable dead band insertion\r
+\r
+//*****************************************************************************\r
+//\r
+// PWM Register reset values.\r
+//\r
+//*****************************************************************************\r
+#define PWM_RV_CTL 0x00000000 // Master control of the PWM module\r
+#define PWM_RV_SYNC 0x00000000 // Counter synch for PWM generators\r
+#define PWM_RV_ENABLE 0x00000000 // Master enable for the PWM\r
+ // output pins\r
+#define PWM_RV_INVERT 0x00000000 // Inversion control for\r
+ // PWM output pins\r
+#define PWM_RV_FAULT 0x00000000 // Fault handling for the PWM\r
+ // output pins\r
+#define PWM_RV_INTEN 0x00000000 // Interrupt enable\r
+#define PWM_RV_RIS 0x00000000 // Raw interrupt status\r
+#define PWM_RV_ISC 0x00000000 // Interrupt status and clearing\r
+#define PWM_RV_STATUS 0x00000000 // Status\r
+#define PWM_RV_X_CTL 0x00000000 // Master control of the PWM\r
+ // generator block\r
+#define PWM_RV_X_INTEN 0x00000000 // Interrupt and trigger enable\r
+#define PWM_RV_X_RIS 0x00000000 // Raw interrupt status\r
+#define PWM_RV_X_ISC 0x00000000 // Interrupt status and clearing\r
+#define PWM_RV_X_LOAD 0x00000000 // The load value for the counter\r
+#define PWM_RV_X_COUNT 0x00000000 // The current counter value\r
+#define PWM_RV_X_CMPA 0x00000000 // The comparator A value\r
+#define PWM_RV_X_CMPB 0x00000000 // The comparator B value\r
+#define PWM_RV_X_GENA 0x00000000 // Controls PWM generator A\r
+#define PWM_RV_X_GENB 0x00000000 // Controls PWM generator B\r
+#define PWM_RV_X_DBCTL 0x00000000 // Control the dead band generator\r
+#define PWM_RV_X_DBRISE 0x00000000 // The dead band rising edge delay\r
+ // count\r
+#define PWM_RV_X_DBFALL 0x00000000 // The dead band falling edge delay\r
+ // count\r
+\r
+#endif // __HW_PWM_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_qei.h - Macros used when accessing the QEI hardware.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_QEI_H__\r
+#define __HW_QEI_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the offsets of the QEI registers.\r
+//\r
+//*****************************************************************************\r
+#define QEI_O_CTL 0x00000000 // Configuration and control reg.\r
+#define QEI_O_STAT 0x00000004 // Status register\r
+#define QEI_O_POS 0x00000008 // Current position register\r
+#define QEI_O_MAXPOS 0x0000000C // Maximum position register\r
+#define QEI_O_LOAD 0x00000010 // Velocity timer load register\r
+#define QEI_O_TIME 0x00000014 // Velocity timer register\r
+#define QEI_O_COUNT 0x00000018 // Velocity pulse count register\r
+#define QEI_O_SPEED 0x0000001C // Velocity speed register\r
+#define QEI_O_INTEN 0x00000020 // Interrupt enable register\r
+#define QEI_O_RIS 0x00000024 // Raw interrupt status register\r
+#define QEI_O_ISC 0x00000028 // Interrupt status register\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the QEI_CTL register.\r
+//\r
+//*****************************************************************************\r
+#define QEI_CTL_STALLEN 0x00001000 // Stall enable\r
+#define QEI_CTL_INVI 0x00000800 // Invert Index input\r
+#define QEI_CTL_INVB 0x00000400 // Invert PhB input\r
+#define QEI_CTL_INVA 0x00000200 // Invert PhA input\r
+#define QEI_CTL_VELDIV_M 0x000001C0 // Velocity predivider mask\r
+#define QEI_CTL_VELDIV_1 0x00000000 // Predivide by 1\r
+#define QEI_CTL_VELDIV_2 0x00000040 // Predivide by 2\r
+#define QEI_CTL_VELDIV_4 0x00000080 // Predivide by 4\r
+#define QEI_CTL_VELDIV_8 0x000000C0 // Predivide by 8\r
+#define QEI_CTL_VELDIV_16 0x00000100 // Predivide by 16\r
+#define QEI_CTL_VELDIV_32 0x00000140 // Predivide by 32\r
+#define QEI_CTL_VELDIV_64 0x00000180 // Predivide by 64\r
+#define QEI_CTL_VELDIV_128 0x000001C0 // Predivide by 128\r
+#define QEI_CTL_VELEN 0x00000020 // Velocity enable\r
+#define QEI_CTL_RESMODE 0x00000010 // Position counter reset mode\r
+#define QEI_CTL_CAPMODE 0x00000008 // Edge capture mode\r
+#define QEI_CTL_SIGMODE 0x00000004 // Encoder signaling mode\r
+#define QEI_CTL_SWAP 0x00000002 // Swap input signals\r
+#define QEI_CTL_ENABLE 0x00000001 // QEI enable\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the QEI_STAT register.\r
+//\r
+//*****************************************************************************\r
+#define QEI_STAT_DIRECTION 0x00000002 // Direction of rotation\r
+#define QEI_STAT_ERROR 0x00000001 // Signalling error detected\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the QEI_POS register.\r
+//\r
+//*****************************************************************************\r
+#define QEI_POS_M 0xFFFFFFFF // Current encoder position\r
+#define QEI_POS_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the QEI_MAXPOS register.\r
+//\r
+//*****************************************************************************\r
+#define QEI_MAXPOS_M 0xFFFFFFFF // Maximum encoder position\r
+#define QEI_MAXPOS_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the QEI_LOAD register.\r
+//\r
+//*****************************************************************************\r
+#define QEI_LOAD_M 0xFFFFFFFF // Velocity timer load value\r
+#define QEI_LOAD_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the QEI_TIME register.\r
+//\r
+//*****************************************************************************\r
+#define QEI_TIME_M 0xFFFFFFFF // Velocity timer current value\r
+#define QEI_TIME_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the QEI_COUNT register.\r
+//\r
+//*****************************************************************************\r
+#define QEI_COUNT_M 0xFFFFFFFF // Encoder running pulse count\r
+#define QEI_COUNT_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the QEI_SPEED register.\r
+//\r
+//*****************************************************************************\r
+#define QEI_SPEED_M 0xFFFFFFFF // Encoder pulse count\r
+#define QEI_SPEED_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the QEI_INTEN register.\r
+//\r
+//*****************************************************************************\r
+#define QEI_INTEN_ERROR 0x00000008 // Phase error detected\r
+#define QEI_INTEN_DIR 0x00000004 // Direction change\r
+#define QEI_INTEN_TIMER 0x00000002 // Velocity timer expired\r
+#define QEI_INTEN_INDEX 0x00000001 // Index pulse detected\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the QEI_RIS register.\r
+//\r
+//*****************************************************************************\r
+#define QEI_RIS_ERROR 0x00000008 // Phase error detected\r
+#define QEI_RIS_DIR 0x00000004 // Direction change\r
+#define QEI_RIS_TIMER 0x00000002 // Velocity timer expired\r
+#define QEI_RIS_INDEX 0x00000001 // Index pulse detected\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the QEI_ISC register.\r
+//\r
+//*****************************************************************************\r
+#define QEI_INT_ERROR 0x00000008 // Phase error detected\r
+#define QEI_INT_DIR 0x00000004 // Direction change\r
+#define QEI_INT_TIMER 0x00000002 // Velocity timer expired\r
+#define QEI_INT_INDEX 0x00000001 // Index pulse detected\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the reset values for the QEI registers.\r
+//\r
+//*****************************************************************************\r
+#define QEI_RV_CTL 0x00000000 // Configuration and control reg.\r
+#define QEI_RV_STAT 0x00000000 // Status register\r
+#define QEI_RV_POS 0x00000000 // Current position register\r
+#define QEI_RV_MAXPOS 0x00000000 // Maximum position register\r
+#define QEI_RV_LOAD 0x00000000 // Velocity timer load register\r
+#define QEI_RV_TIME 0x00000000 // Velocity timer register\r
+#define QEI_RV_COUNT 0x00000000 // Velocity pulse count register\r
+#define QEI_RV_SPEED 0x00000000 // Velocity speed register\r
+#define QEI_RV_INTEN 0x00000000 // Interrupt enable register\r
+#define QEI_RV_RIS 0x00000000 // Raw interrupt status register\r
+#define QEI_RV_ISC 0x00000000 // Interrupt status register\r
+\r
+#endif // __HW_QEI_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_ssi.h - Macros used when accessing the SSI hardware.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_SSI_H__\r
+#define __HW_SSI_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the offsets of the SSI registers.\r
+//\r
+//*****************************************************************************\r
+#define SSI_O_CR0 0x00000000 // Control register 0\r
+#define SSI_O_CR1 0x00000004 // Control register 1\r
+#define SSI_O_DR 0x00000008 // Data register\r
+#define SSI_O_SR 0x0000000C // Status register\r
+#define SSI_O_CPSR 0x00000010 // Clock prescale register\r
+#define SSI_O_IM 0x00000014 // Int mask set and clear register\r
+#define SSI_O_RIS 0x00000018 // Raw interrupt register\r
+#define SSI_O_MIS 0x0000001C // Masked interrupt register\r
+#define SSI_O_ICR 0x00000020 // Interrupt clear register\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SSI Control register 0.\r
+//\r
+//*****************************************************************************\r
+#define SSI_CR0_SCR 0x0000FF00 // Serial clock rate\r
+#define SSI_CR0_SPH 0x00000080 // SSPCLKOUT phase\r
+#define SSI_CR0_SPO 0x00000040 // SSPCLKOUT polarity\r
+#define SSI_CR0_FRF_MASK 0x00000030 // Frame format mask\r
+#define SSI_CR0_FRF_MOTO 0x00000000 // Motorola SPI frame format\r
+#define SSI_CR0_FRF_TI 0x00000010 // TI sync serial frame format\r
+#define SSI_CR0_FRF_NMW 0x00000020 // National Microwire frame format\r
+#define SSI_CR0_DSS 0x0000000F // Data size select\r
+#define SSI_CR0_DSS_4 0x00000003 // 4 bit data\r
+#define SSI_CR0_DSS_5 0x00000004 // 5 bit data\r
+#define SSI_CR0_DSS_6 0x00000005 // 6 bit data\r
+#define SSI_CR0_DSS_7 0x00000006 // 7 bit data\r
+#define SSI_CR0_DSS_8 0x00000007 // 8 bit data\r
+#define SSI_CR0_DSS_9 0x00000008 // 9 bit data\r
+#define SSI_CR0_DSS_10 0x00000009 // 10 bit data\r
+#define SSI_CR0_DSS_11 0x0000000A // 11 bit data\r
+#define SSI_CR0_DSS_12 0x0000000B // 12 bit data\r
+#define SSI_CR0_DSS_13 0x0000000C // 13 bit data\r
+#define SSI_CR0_DSS_14 0x0000000D // 14 bit data\r
+#define SSI_CR0_DSS_15 0x0000000E // 15 bit data\r
+#define SSI_CR0_DSS_16 0x0000000F // 16 bit data\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SSI Control register 1.\r
+//\r
+//*****************************************************************************\r
+#define SSI_CR1_SOD 0x00000008 // Slave mode output disable\r
+#define SSI_CR1_MS 0x00000004 // Master or slave mode select\r
+#define SSI_CR1_SSE 0x00000002 // Sync serial port enable\r
+#define SSI_CR1_LBM 0x00000001 // Loopback mode\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SSI Status register.\r
+//\r
+//*****************************************************************************\r
+#define SSI_SR_BSY 0x00000010 // SSI busy\r
+#define SSI_SR_RFF 0x00000008 // RX FIFO full\r
+#define SSI_SR_RNE 0x00000004 // RX FIFO not empty\r
+#define SSI_SR_TNF 0x00000002 // TX FIFO not full\r
+#define SSI_SR_TFE 0x00000001 // TX FIFO empty\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SSI clock prescale register.\r
+//\r
+//*****************************************************************************\r
+#define SSI_CPSR_CPSDVSR_MASK 0x000000FF // Clock prescale\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define information concerning the SSI Data register.\r
+//\r
+//*****************************************************************************\r
+#define TX_FIFO_SIZE (8) // Number of entries in the TX FIFO\r
+#define RX_FIFO_SIZE (8) // Number of entries in the RX FIFO\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the interrupt mask set and clear,\r
+// raw interrupt, masked interrupt, and interrupt clear registers.\r
+//\r
+//*****************************************************************************\r
+#define SSI_INT_TXFF 0x00000008 // TX FIFO interrupt\r
+#define SSI_INT_RXFF 0x00000004 // RX FIFO interrupt\r
+#define SSI_INT_RXTO 0x00000002 // RX timeout interrupt\r
+#define SSI_INT_RXOR 0x00000001 // RX overrun interrupt\r
+\r
+#endif // __HW_SSI_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_sysctl.h - Macros used when accessing the system control hardware.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_SYSCTL_H__\r
+#define __HW_SYSCTL_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the addresses of the system control registers.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_DID0 0x400fe000 // Device identification register 0\r
+#define SYSCTL_DID1 0x400fe004 // Device identification register 1\r
+#define SYSCTL_DC0 0x400fe008 // Device capabilities register 0\r
+#define SYSCTL_DC1 0x400fe010 // Device capabilities register 1\r
+#define SYSCTL_DC2 0x400fe014 // Device capabilities register 2\r
+#define SYSCTL_DC3 0x400fe018 // Device capabilities register 3\r
+#define SYSCTL_DC4 0x400fe01C // Device capabilities register 4\r
+#define SYSCTL_PBORCTL 0x400fe030 // POR/BOR reset control register\r
+#define SYSCTL_LDOPCTL 0x400fe034 // LDO power control register\r
+#define SYSCTL_SRCR0 0x400fe040 // Software reset control reg 0\r
+#define SYSCTL_SRCR1 0x400fe044 // Software reset control reg 1\r
+#define SYSCTL_SRCR2 0x400fe048 // Software reset control reg 2\r
+#define SYSCTL_RIS 0x400fe050 // Raw interrupt status register\r
+#define SYSCTL_IMC 0x400fe054 // Interrupt mask/control register\r
+#define SYSCTL_MISC 0x400fe058 // Interrupt status register\r
+#define SYSCTL_RESC 0x400fe05c // Reset cause register\r
+#define SYSCTL_RCC 0x400fe060 // Run-mode clock config register\r
+#define SYSCTL_PLLCFG 0x400fe064 // PLL configuration register\r
+#define SYSCTL_RCC2 0x400fe070 // Run-mode clock config register 2\r
+#define SYSCTL_RCGC0 0x400fe100 // Run-mode clock gating register 0\r
+#define SYSCTL_RCGC1 0x400fe104 // Run-mode clock gating register 1\r
+#define SYSCTL_RCGC2 0x400fe108 // Run-mode clock gating register 2\r
+#define SYSCTL_SCGC0 0x400fe110 // Sleep-mode clock gating reg 0\r
+#define SYSCTL_SCGC1 0x400fe114 // Sleep-mode clock gating reg 1\r
+#define SYSCTL_SCGC2 0x400fe118 // Sleep-mode clock gating reg 2\r
+#define SYSCTL_DCGC0 0x400fe120 // Deep Sleep-mode clock gate reg 0\r
+#define SYSCTL_DCGC1 0x400fe124 // Deep Sleep-mode clock gate reg 1\r
+#define SYSCTL_DCGC2 0x400fe128 // Deep Sleep-mode clock gate reg 2\r
+#define SYSCTL_DSLPCLKCFG 0x400fe144 // Deep Sleep-mode clock config reg\r
+#define SYSCTL_CLKVCLR 0x400fe150 // Clock verifcation clear register\r
+#define SYSCTL_LDOARST 0x400fe160 // LDO reset control register\r
+#define SYSCTL_USER0 0x400fe1e0 // NV User Register 0\r
+#define SYSCTL_USER1 0x400fe1e4 // NV User Register 1\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_DID0 register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_DID0_VER_MASK 0x70000000 // DID0 version mask\r
+#define SYSCTL_DID0_VER_0 0x00000000 // DID0 version 0\r
+#define SYSCTL_DID0_VER_1 0x10000000 // DID0 version 1\r
+#define SYSCTL_DID0_CLASS_MASK 0x00FF0000 // Device Class\r
+#define SYSCTL_DID0_CLASS_SANDSTORM 0x00000000 // LM3Snnn Sandstorm Device\r
+#define SYSCTL_DID0_CLASS_FURY 0x00010000 // LM3Snnnn Fury Device\r
+#define SYSCTL_DID0_MAJ_MASK 0x0000FF00 // Major revision mask\r
+#define SYSCTL_DID0_MAJ_A 0x00000000 // Major revision A\r
+#define SYSCTL_DID0_MAJ_B 0x00000100 // Major revision B\r
+#define SYSCTL_DID0_MAJ_C 0x00000200 // Major revision C\r
+#define SYSCTL_DID0_MIN_MASK 0x000000FF // Minor revision mask\r
+#define SYSCTL_DID0_MIN_0 0x00000000 // Minor revision 0\r
+#define SYSCTL_DID0_MIN_1 0x00000001 // Minor revision 1\r
+#define SYSCTL_DID0_MIN_2 0x00000002 // Minor revision 2\r
+#define SYSCTL_DID0_MIN_3 0x00000003 // Minor revision 3\r
+#define SYSCTL_DID0_MIN_4 0x00000004 // Minor revision 4\r
+#define SYSCTL_DID0_MIN_5 0x00000005 // Minor revision 5\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_DID1 register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_DID1_VER_MASK 0xF0000000 // Register version mask\r
+#define SYSCTL_DID1_FAM_MASK 0x0F000000 // Family mask\r
+#define SYSCTL_DID1_FAM_S 0x00000000 // Stellaris family\r
+#define SYSCTL_DID1_PRTNO_MASK 0x00FF0000 // Part number mask\r
+#define SYSCTL_DID1_PRTNO_101 0x00010000 // LM3S101\r
+#define SYSCTL_DID1_PRTNO_102 0x00020000 // LM3S102\r
+#define SYSCTL_DID1_PRTNO_301 0x00110000 // LM3S301\r
+#define SYSCTL_DID1_PRTNO_310 0x00120000 // LM3S310\r
+#define SYSCTL_DID1_PRTNO_315 0x00130000 // LM3S315\r
+#define SYSCTL_DID1_PRTNO_316 0x00140000 // LM3S316\r
+#define SYSCTL_DID1_PRTNO_317 0x00170000 // LM3S317\r
+#define SYSCTL_DID1_PRTNO_328 0x00150000 // LM3S328\r
+#define SYSCTL_DID1_PRTNO_601 0x00210000 // LM3S601\r
+#define SYSCTL_DID1_PRTNO_610 0x00220000 // LM3S610\r
+#define SYSCTL_DID1_PRTNO_611 0x00230000 // LM3S611\r
+#define SYSCTL_DID1_PRTNO_612 0x00240000 // LM3S612\r
+#define SYSCTL_DID1_PRTNO_613 0x00250000 // LM3S613\r
+#define SYSCTL_DID1_PRTNO_615 0x00260000 // LM3S615\r
+#define SYSCTL_DID1_PRTNO_617 0x00280000 // LM3S617\r
+#define SYSCTL_DID1_PRTNO_618 0x00290000 // LM3S618\r
+#define SYSCTL_DID1_PRTNO_628 0x00270000 // LM3S628\r
+#define SYSCTL_DID1_PRTNO_801 0x00310000 // LM3S801\r
+#define SYSCTL_DID1_PRTNO_811 0x00320000 // LM3S811\r
+#define SYSCTL_DID1_PRTNO_812 0x00330000 // LM3S812\r
+#define SYSCTL_DID1_PRTNO_815 0x00340000 // LM3S815\r
+#define SYSCTL_DID1_PRTNO_817 0x00360000 // LM3S817\r
+#define SYSCTL_DID1_PRTNO_818 0x00370000 // LM3S818\r
+#define SYSCTL_DID1_PRTNO_828 0x00350000 // LM3S828\r
+#define SYSCTL_DID1_PRTNO_2110 0x00510000 // LM3S2110\r
+#define SYSCTL_DID1_PRTNO_2139 0x00840000 // LM3S2139\r
+#define SYSCTL_DID1_PRTNO_2410 0x00A20000 // LM3S2410\r
+#define SYSCTL_DID1_PRTNO_2412 0x00590000 // LM3S2412\r
+#define SYSCTL_DID1_PRTNO_2432 0x00560000 // LM3S2432\r
+#define SYSCTL_DID1_PRTNO_2533 0x005A0000 // LM3S2533\r
+#define SYSCTL_DID1_PRTNO_2620 0x00570000 // LM3S2620\r
+#define SYSCTL_DID1_PRTNO_2637 0x00850000 // LM3S2637\r
+#define SYSCTL_DID1_PRTNO_2651 0x00530000 // LM3S2651\r
+#define SYSCTL_DID1_PRTNO_2730 0x00A40000 // LM3S2730\r
+#define SYSCTL_DID1_PRTNO_2739 0x00520000 // LM3S2739\r
+#define SYSCTL_DID1_PRTNO_2939 0x00540000 // LM3S2939\r
+#define SYSCTL_DID1_PRTNO_2948 0x008F0000 // LM3S2948\r
+#define SYSCTL_DID1_PRTNO_2950 0x00580000 // LM3S2950\r
+#define SYSCTL_DID1_PRTNO_2965 0x00550000 // LM3S2965\r
+#define SYSCTL_DID1_PRTNO_6100 0x00A10000 // LM3S6100\r
+#define SYSCTL_DID1_PRTNO_6110 0x00740000 // LM3S6110\r
+#define SYSCTL_DID1_PRTNO_6420 0x00A50000 // LM3S6420\r
+#define SYSCTL_DID1_PRTNO_6422 0x00820000 // LM3S6422\r
+#define SYSCTL_DID1_PRTNO_6432 0x00750000 // LM3S6432\r
+#define SYSCTL_DID1_PRTNO_6610 0x00710000 // LM3S6610\r
+#define SYSCTL_DID1_PRTNO_6633 0x00830000 // LM3S6633\r
+#define SYSCTL_DID1_PRTNO_6637 0x008B0000 // LM3S6637\r
+#define SYSCTL_DID1_PRTNO_6730 0x00A30000 // LM3S6730\r
+#define SYSCTL_DID1_PRTNO_6938 0x00890000 // LM3S6938\r
+#define SYSCTL_DID1_PRTNO_6952 0x00780000 // LM3S6952\r
+#define SYSCTL_DID1_PRTNO_6965 0x00730000 // LM3S6965\r
+#define SYSCTL_DID1_PINCNT_MASK 0x0000E000 // Pin count\r
+#define SYSCTL_DID1_PINCNT_100 0x00004000 // 100 pin package\r
+#define SYSCTL_DID1_TEMP_MASK 0x000000E0 // Temperature range mask\r
+#define SYSCTL_DID1_TEMP_C 0x00000000 // Commercial temp range (0..70C)\r
+#define SYSCTL_DID1_TEMP_I 0x00000020 // Industrial temp range (-40..85C)\r
+#define SYSCTL_DID1_PKG_MASK 0x00000018 // Package mask\r
+#define SYSCTL_DID1_PKG_28SOIC 0x00000000 // 28-pin SOIC\r
+#define SYSCTL_DID1_PKG_48QFP 0x00000008 // 48-pin QFP\r
+#define SYSCTL_DID1_ROHS 0x00000004 // Part is RoHS compliant\r
+#define SYSCTL_DID1_QUAL_MASK 0x00000003 // Qualification status mask\r
+#define SYSCTL_DID1_QUAL_ES 0x00000000 // Engineering sample (unqualified)\r
+#define SYSCTL_DID1_QUAL_PP 0x00000001 // Pilot production (unqualified)\r
+#define SYSCTL_DID1_QUAL_FQ 0x00000002 // Fully qualified\r
+#define SYSCTL_DID1_PRTNO_SHIFT 16\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_DC0 register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_DC0_SRAMSZ_MASK 0xFFFF0000 // SRAM size mask\r
+#define SYSCTL_DC0_SRAMSZ_2KB 0x00070000 // 2 KB of SRAM\r
+#define SYSCTL_DC0_SRAMSZ_4KB 0x000F0000 // 4 KB of SRAM\r
+#define SYSCTL_DC0_SRAMSZ_8KB 0x001F0000 // 8 KB of SRAM\r
+#define SYSCTL_DC0_SRAMSZ_16KB 0x003F0000 // 16 KB of SRAM\r
+#define SYSCTL_DC0_SRAMSZ_32KB 0x007F0000 // 32 KB of SRAM\r
+#define SYSCTL_DC0_SRAMSZ_64KB 0x00FF0000 // 64 KB of SRAM\r
+#define SYSCTL_DC0_FLASHSZ_MASK 0x0000FFFF // Flash size mask\r
+#define SYSCTL_DC0_FLASHSZ_8KB 0x00000003 // 8 KB of flash\r
+#define SYSCTL_DC0_FLASHSZ_16KB 0x00000007 // 16 KB of flash\r
+#define SYSCTL_DC0_FLASHSZ_32KB 0x0000000F // 32 KB of flash\r
+#define SYSCTL_DC0_FLASHSZ_64KB 0x0000001F // 64 KB of flash\r
+#define SYSCTL_DC0_FLASHSZ_96KB 0x0000002F // 96 KB of flash\r
+#define SYSCTL_DC0_FLASHSZ_128K 0x0000003F // 128 KB of flash\r
+#define SYSCTL_DC0_FLASHSZ_256K 0x0000007F // 256 KB of flash\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_DC1 register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_DC1_CAN1 0x02000000 // CAN1 module present\r
+#define SYSCTL_DC1_CAN0 0x01000000 // CAN0 module present\r
+#define SYSCTL_DC1_PWM 0x00100000 // PWM module present\r
+#define SYSCTL_DC1_ADC 0x00010000 // ADC module present\r
+#define SYSCTL_DC1_SYSDIV_MASK 0x0000F000 // Minimum system divider mask\r
+#define SYSCTL_DC1_ADCSPD_MASK 0x00000F00 // ADC speed mask\r
+#define SYSCTL_DC1_ADCSPD_1M 0x00000300 // 1Msps ADC\r
+#define SYSCTL_DC1_ADCSPD_500K 0x00000200 // 500Ksps ADC\r
+#define SYSCTL_DC1_ADCSPD_250K 0x00000100 // 250Ksps ADC\r
+#define SYSCTL_DC1_ADCSPD_125K 0x00000000 // 125Ksps ADC\r
+#define SYSCTL_DC1_MPU 0x00000080 // Cortex M3 MPU present\r
+#define SYSCTL_DC1_HIB 0x00000040 // Hibernation module present\r
+#define SYSCTL_DC1_TEMP 0x00000020 // Temperature sensor present\r
+#define SYSCTL_DC1_PLL 0x00000010 // PLL present\r
+#define SYSCTL_DC1_WDOG 0x00000008 // Watchdog present\r
+#define SYSCTL_DC1_SWO 0x00000004 // Serial wire output present\r
+#define SYSCTL_DC1_SWD 0x00000002 // Serial wire debug present\r
+#define SYSCTL_DC1_JTAG 0x00000001 // JTAG debug present\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_DC2 register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_DC2_COMP2 0x04000000 // Analog comparator 2 present\r
+#define SYSCTL_DC2_COMP1 0x02000000 // Analog comparator 1 present\r
+#define SYSCTL_DC2_COMP0 0x01000000 // Analog comparator 0 present\r
+#define SYSCTL_DC2_TIMER3 0x00080000 // Timer 3 present\r
+#define SYSCTL_DC2_TIMER2 0x00040000 // Timer 2 present\r
+#define SYSCTL_DC2_TIMER1 0x00020000 // Timer 1 present\r
+#define SYSCTL_DC2_TIMER0 0x00010000 // Timer 0 present\r
+#define SYSCTL_DC2_I2C1 0x00002000 // I2C 1 present\r
+#define SYSCTL_DC2_I2C0 0x00001000 // I2C 0 present\r
+#ifndef DEPRECATED\r
+#define SYSCTL_DC2_I2C 0x00001000 // I2C present\r
+#endif\r
+#define SYSCTL_DC2_QEI1 0x00000200 // QEI 1 present\r
+#define SYSCTL_DC2_QEI0 0x00000100 // QEI 0 present\r
+#ifndef DEPRECATED\r
+#define SYSCTL_DC2_QEI 0x00000100 // QEI present\r
+#endif\r
+#define SYSCTL_DC2_SSI1 0x00000020 // SSI 1 present\r
+#define SYSCTL_DC2_SSI0 0x00000010 // SSI 0 present\r
+#ifndef DEPRECATED\r
+#define SYSCTL_DC2_SSI 0x00000010 // SSI present\r
+#endif\r
+#define SYSCTL_DC2_UART2 0x00000004 // UART 2 present\r
+#define SYSCTL_DC2_UART1 0x00000002 // UART 1 present\r
+#define SYSCTL_DC2_UART0 0x00000001 // UART 0 present\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_DC3 register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_DC3_32KHZ 0x80000000 // 32kHz pin present\r
+#define SYSCTL_DC3_CCP5 0x20000000 // CCP5 pin present\r
+#define SYSCTL_DC3_CCP4 0x10000000 // CCP4 pin present\r
+#define SYSCTL_DC3_CCP3 0x08000000 // CCP3 pin present\r
+#define SYSCTL_DC3_CCP2 0x04000000 // CCP2 pin present\r
+#define SYSCTL_DC3_CCP1 0x02000000 // CCP1 pin present\r
+#define SYSCTL_DC3_CCP0 0x01000000 // CCP0 pin present\r
+#define SYSCTL_DC3_ADC7 0x00800000 // ADC7 pin present\r
+#define SYSCTL_DC3_ADC6 0x00400000 // ADC6 pin present\r
+#define SYSCTL_DC3_ADC5 0x00200000 // ADC5 pin present\r
+#define SYSCTL_DC3_ADC4 0x00100000 // ADC4 pin present\r
+#define SYSCTL_DC3_ADC3 0x00080000 // ADC3 pin present\r
+#define SYSCTL_DC3_ADC2 0x00040000 // ADC2 pin present\r
+#define SYSCTL_DC3_ADC1 0x00020000 // ADC1 pin present\r
+#define SYSCTL_DC3_ADC0 0x00010000 // ADC0 pin present\r
+#define SYSCTL_DC3_MC_FAULT0 0x00008000 // MC0 fault pin present\r
+#define SYSCTL_DC3_C2O 0x00004000 // C2o pin present\r
+#define SYSCTL_DC3_C2PLUS 0x00002000 // C2+ pin present\r
+#define SYSCTL_DC3_C2MINUS 0x00001000 // C2- pin present\r
+#define SYSCTL_DC3_C1O 0x00000800 // C1o pin present\r
+#define SYSCTL_DC3_C1PLUS 0x00000400 // C1+ pin present\r
+#define SYSCTL_DC3_C1MINUS 0x00000200 // C1- pin present\r
+#define SYSCTL_DC3_C0O 0x00000100 // C0o pin present\r
+#define SYSCTL_DC3_C0PLUS 0x00000080 // C0+ pin present\r
+#define SYSCTL_DC3_C0MINUS 0x00000040 // C0- pin present\r
+#define SYSCTL_DC3_PWM5 0x00000020 // PWM5 pin present\r
+#define SYSCTL_DC3_PWM4 0x00000010 // PWM4 pin present\r
+#define SYSCTL_DC3_PWM3 0x00000008 // PWM3 pin present\r
+#define SYSCTL_DC3_PWM2 0x00000004 // PWM2 pin present\r
+#define SYSCTL_DC3_PWM1 0x00000002 // PWM1 pin present\r
+#define SYSCTL_DC3_PWM0 0x00000001 // PWM0 pin present\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_DC4 register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_DC4_ETH 0x50000000 // Ethernet present\r
+#define SYSCTL_DC4_GPIOH 0x00000080 // GPIO port H present\r
+#define SYSCTL_DC4_GPIOG 0x00000040 // GPIO port G present\r
+#define SYSCTL_DC4_GPIOF 0x00000020 // GPIO port F present\r
+#define SYSCTL_DC4_GPIOE 0x00000010 // GPIO port E present\r
+#define SYSCTL_DC4_GPIOD 0x00000008 // GPIO port D present\r
+#define SYSCTL_DC4_GPIOC 0x00000004 // GPIO port C present\r
+#define SYSCTL_DC4_GPIOB 0x00000002 // GPIO port B present\r
+#define SYSCTL_DC4_GPIOA 0x00000001 // GPIO port A present\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_PBORCTL register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_PBORCTL_BOR_MASK 0x0000FFFC // BOR wait timer\r
+#define SYSCTL_PBORCTL_BORIOR 0x00000002 // BOR interrupt or reset\r
+#define SYSCTL_PBORCTL_BORWT 0x00000001 // BOR wait and check for noise\r
+#define SYSCTL_PBORCTL_BOR_SH 2\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_LDOPCTL register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_LDOPCTL_MASK 0x0000003F // Voltage adjust mask\r
+#define SYSCTL_LDOPCTL_2_25V 0x00000005 // LDO output of 2.25V\r
+#define SYSCTL_LDOPCTL_2_30V 0x00000004 // LDO output of 2.30V\r
+#define SYSCTL_LDOPCTL_2_35V 0x00000003 // LDO output of 2.35V\r
+#define SYSCTL_LDOPCTL_2_40V 0x00000002 // LDO output of 2.40V\r
+#define SYSCTL_LDOPCTL_2_45V 0x00000001 // LDO output of 2.45V\r
+#define SYSCTL_LDOPCTL_2_50V 0x00000000 // LDO output of 2.50V\r
+#define SYSCTL_LDOPCTL_2_55V 0x0000001F // LDO output of 2.55V\r
+#define SYSCTL_LDOPCTL_2_60V 0x0000001E // LDO output of 2.60V\r
+#define SYSCTL_LDOPCTL_2_65V 0x0000001D // LDO output of 2.65V\r
+#define SYSCTL_LDOPCTL_2_70V 0x0000001C // LDO output of 2.70V\r
+#define SYSCTL_LDOPCTL_2_75V 0x0000001B // LDO output of 2.75V\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_SRCR0, SYSCTL_RCGC0,\r
+// SYSCTL_SCGC0, and SYSCTL_DCGC0 registers.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_SET0_CAN1 0x02000000 // CAN 1 module\r
+#define SYSCTL_SET0_CAN0 0x01000000 // CAN 0 module\r
+#define SYSCTL_SET0_PWM 0x00100000 // PWM module\r
+#define SYSCTL_SET0_ADC 0x00010000 // ADC module\r
+#define SYSCTL_SET0_ADCSPD_MASK 0x00000F00 // ADC speed mask\r
+#define SYSCTL_SET0_ADCSPD_1M 0x00000300 // 1Msps ADC\r
+#define SYSCTL_SET0_ADCSPD_500K 0x00000200 // 500Ksps ADC\r
+#define SYSCTL_SET0_ADCSPD_250K 0x00000100 // 250Ksps ADC\r
+#define SYSCTL_SET0_ADCSPD_125K 0x00000000 // 125Ksps ADC\r
+#define SYSCTL_SET0_HIB 0x00000040 // Hibernation module\r
+#define SYSCTL_SET0_WDOG 0x00000008 // Watchdog module\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_SRCR1, SYSCTL_RCGC1,\r
+// SYSCTL_SCGC1, and SYSCTL_DCGC1 registers.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_SET1_COMP2 0x04000000 // Analog comparator module 2\r
+#define SYSCTL_SET1_COMP1 0x02000000 // Analog comparator module 1\r
+#define SYSCTL_SET1_COMP0 0x01000000 // Analog comparator module 0\r
+#define SYSCTL_SET1_TIMER3 0x00080000 // Timer module 3\r
+#define SYSCTL_SET1_TIMER2 0x00040000 // Timer module 2\r
+#define SYSCTL_SET1_TIMER1 0x00020000 // Timer module 1\r
+#define SYSCTL_SET1_TIMER0 0x00010000 // Timer module 0\r
+#define SYSCTL_SET1_I2C1 0x00002000 // I2C module 1\r
+#define SYSCTL_SET1_I2C0 0x00001000 // I2C module 0\r
+#ifndef DEPRECATED\r
+#define SYSCTL_SET1_I2C 0x00001000 // I2C module\r
+#endif\r
+#define SYSCTL_SET1_QEI1 0x00000200 // QEI module 1\r
+#define SYSCTL_SET1_QEI0 0x00000100 // QEI module 0\r
+#ifndef DEPRECATED\r
+#define SYSCTL_SET1_QEI 0x00000100 // QEI module\r
+#endif\r
+#define SYSCTL_SET1_SSI1 0x00000020 // SSI module 1\r
+#define SYSCTL_SET1_SSI0 0x00000010 // SSI module 0\r
+#ifndef DEPRECATED\r
+#define SYSCTL_SET1_SSI 0x00000010 // SSI module\r
+#endif\r
+#define SYSCTL_SET1_UART2 0x00000004 // UART module 2\r
+#define SYSCTL_SET1_UART1 0x00000002 // UART module 1\r
+#define SYSCTL_SET1_UART0 0x00000001 // UART module 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_SRCR2, SYSCTL_RCGC2,\r
+// SYSCTL_SCGC2, and SYSCTL_DCGC2 registers.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_SET2_ETH 0x50000000 // ETH module\r
+#define SYSCTL_SET2_GPIOH 0x00000080 // GPIO H module\r
+#define SYSCTL_SET2_GPIOG 0x00000040 // GPIO G module\r
+#define SYSCTL_SET2_GPIOF 0x00000020 // GPIO F module\r
+#define SYSCTL_SET2_GPIOE 0x00000010 // GPIO E module\r
+#define SYSCTL_SET2_GPIOD 0x00000008 // GPIO D module\r
+#define SYSCTL_SET2_GPIOC 0x00000004 // GPIO C module\r
+#define SYSCTL_SET2_GPIOB 0x00000002 // GPIO B module\r
+#define SYSCTL_SET2_GPIOA 0x00000001 // GIPO A module\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_RIS, SYSCTL_IMC, and\r
+// SYSCTL_IMS registers.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_INT_PLL_LOCK 0x00000040 // PLL lock interrupt\r
+#define SYSCTL_INT_CUR_LIMIT 0x00000020 // Current limit interrupt\r
+#define SYSCTL_INT_IOSC_FAIL 0x00000010 // Internal oscillator failure int\r
+#define SYSCTL_INT_MOSC_FAIL 0x00000008 // Main oscillator failure int\r
+#define SYSCTL_INT_POR 0x00000004 // Power on reset interrupt\r
+#define SYSCTL_INT_BOR 0x00000002 // Brown out interrupt\r
+#define SYSCTL_INT_PLL_FAIL 0x00000001 // PLL failure interrupt\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_RESC register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_RESC_LDO 0x00000020 // LDO power OK lost reset\r
+#define SYSCTL_RESC_SW 0x00000010 // Software reset\r
+#define SYSCTL_RESC_WDOG 0x00000008 // Watchdog reset\r
+#define SYSCTL_RESC_BOR 0x00000004 // Brown-out reset\r
+#define SYSCTL_RESC_POR 0x00000002 // Power on reset\r
+#define SYSCTL_RESC_EXT 0x00000001 // External reset\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_RCC register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_RCC_ACG 0x08000000 // Automatic clock gating\r
+#define SYSCTL_RCC_SYSDIV_MASK 0x07800000 // System clock divider\r
+#define SYSCTL_RCC_SYSDIV_2 0x00800000 // System clock /2\r
+#define SYSCTL_RCC_SYSDIV_3 0x01000000 // System clock /3\r
+#define SYSCTL_RCC_SYSDIV_4 0x01800000 // System clock /4\r
+#define SYSCTL_RCC_SYSDIV_5 0x02000000 // System clock /5\r
+#define SYSCTL_RCC_SYSDIV_6 0x02800000 // System clock /6\r
+#define SYSCTL_RCC_SYSDIV_7 0x03000000 // System clock /7\r
+#define SYSCTL_RCC_SYSDIV_8 0x03800000 // System clock /8\r
+#define SYSCTL_RCC_SYSDIV_9 0x04000000 // System clock /9\r
+#define SYSCTL_RCC_SYSDIV_10 0x04800000 // System clock /10\r
+#define SYSCTL_RCC_SYSDIV_11 0x05000000 // System clock /11\r
+#define SYSCTL_RCC_SYSDIV_12 0x05800000 // System clock /12\r
+#define SYSCTL_RCC_SYSDIV_13 0x06000000 // System clock /13\r
+#define SYSCTL_RCC_SYSDIV_14 0x06800000 // System clock /14\r
+#define SYSCTL_RCC_SYSDIV_15 0x07000000 // System clock /15\r
+#define SYSCTL_RCC_SYSDIV_16 0x07800000 // System clock /16\r
+#define SYSCTL_RCC_USE_SYSDIV 0x00400000 // Use sytem clock divider\r
+#define SYSCTL_RCC_USE_PWMDIV 0x00100000 // Use PWM clock divider\r
+#define SYSCTL_RCC_PWMDIV_MASK 0x000E0000 // PWM clock divider\r
+#define SYSCTL_RCC_PWMDIV_2 0x00000000 // PWM clock /2\r
+#define SYSCTL_RCC_PWMDIV_4 0x00020000 // PWM clock /4\r
+#define SYSCTL_RCC_PWMDIV_8 0x00040000 // PWM clock /8\r
+#define SYSCTL_RCC_PWMDIV_16 0x00060000 // PWM clock /16\r
+#define SYSCTL_RCC_PWMDIV_32 0x00080000 // PWM clock /32\r
+#define SYSCTL_RCC_PWMDIV_64 0x000A0000 // PWM clock /64\r
+#define SYSCTL_RCC_PWRDN 0x00002000 // PLL power down\r
+#define SYSCTL_RCC_OE 0x00001000 // PLL output enable\r
+#define SYSCTL_RCC_BYPASS 0x00000800 // PLL bypass\r
+#define SYSCTL_RCC_PLLVER 0x00000400 // PLL verification timer enable\r
+#define SYSCTL_RCC_XTAL_MASK 0x000003C0 // Crystal attached to main osc\r
+#define SYSCTL_RCC_XTAL_3_57MHZ 0x00000100 // Using a 3.579545MHz crystal\r
+#define SYSCTL_RCC_XTAL_3_68MHz 0x00000140 // Using a 3.6864MHz crystal\r
+#define SYSCTL_RCC_XTAL_4MHz 0x00000180 // Using a 4MHz crystal\r
+#define SYSCTL_RCC_XTAL_4_09MHZ 0x000001C0 // Using a 4.096MHz crystal\r
+#define SYSCTL_RCC_XTAL_4_91MHZ 0x00000200 // Using a 4.9152MHz crystal\r
+#define SYSCTL_RCC_XTAL_5MHZ 0x00000240 // Using a 5MHz crystal\r
+#define SYSCTL_RCC_XTAL_5_12MHZ 0x00000280 // Using a 5.12MHz crystal\r
+#define SYSCTL_RCC_XTAL_6MHZ 0x000002C0 // Using a 6MHz crystal\r
+#define SYSCTL_RCC_XTAL_6_14MHZ 0x00000300 // Using a 6.144MHz crystal\r
+#define SYSCTL_RCC_XTAL_7_37MHZ 0x00000340 // Using a 7.3728MHz crystal\r
+#define SYSCTL_RCC_XTAL_8MHZ 0x00000380 // Using a 8MHz crystal\r
+#define SYSCTL_RCC_XTAL_8_19MHZ 0x000003C0 // Using a 8.192MHz crystal\r
+#define SYSCTL_RCC_OSCSRC_MASK 0x00000030 // Oscillator input select\r
+#define SYSCTL_RCC_OSCSRC_MAIN 0x00000000 // Use the main oscillator\r
+#define SYSCTL_RCC_OSCSRC_INT 0x00000010 // Use the internal oscillator\r
+#define SYSCTL_RCC_OSCSRC_INT4 0x00000020 // Use the internal oscillator / 4\r
+#define SYSCTL_RCC_IOSCVER 0x00000008 // Int. osc. verification timer en\r
+#define SYSCTL_RCC_MOSCVER 0x00000004 // Main osc. verification timer en\r
+#define SYSCTL_RCC_IOSCDIS 0x00000002 // Internal oscillator disable\r
+#define SYSCTL_RCC_MOSCDIS 0x00000001 // Main oscillator disable\r
+#define SYSCTL_RCC_SYSDIV_SHIFT 23 // Shift to the SYSDIV field\r
+#define SYSCTL_RCC_PWMDIV_SHIFT 17 // Shift to the PWMDIV field\r
+#define SYSCTL_RCC_XTAL_SHIFT 6 // Shift to the XTAL field\r
+#define SYSCTL_RCC_OSCSRC_SHIFT 4 // Shift to the OSCSRC field\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_PLLCFG register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_PLLCFG_OD_MASK 0x0000C000 // Output divider\r
+#define SYSCTL_PLLCFG_OD_1 0x00000000 // Output divider is 1\r
+#define SYSCTL_PLLCFG_OD_2 0x00004000 // Output divider is 2\r
+#define SYSCTL_PLLCFG_OD_4 0x00008000 // Output divider is 4\r
+#define SYSCTL_PLLCFG_F_MASK 0x00003FE0 // PLL multiplier\r
+#define SYSCTL_PLLCFG_R_MASK 0x0000001F // Input predivider\r
+#define SYSCTL_PLLCFG_F_SHIFT 5\r
+#define SYSCTL_PLLCFG_R_SHIFT 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_RCC2 register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_RCC2_USERCC2 0x80000000 // Use RCC2\r
+#define SYSCTL_RCC2_SYSDIV2_MSK 0x1F800000 // System clock divider\r
+#define SYSCTL_RCC2_SYSDIV2_2 0x00800000 // System clock /2\r
+#define SYSCTL_RCC2_SYSDIV2_3 0x01000000 // System clock /3\r
+#define SYSCTL_RCC2_SYSDIV2_4 0x01800000 // System clock /4\r
+#define SYSCTL_RCC2_SYSDIV2_5 0x02000000 // System clock /5\r
+#define SYSCTL_RCC2_SYSDIV2_6 0x02800000 // System clock /6\r
+#define SYSCTL_RCC2_SYSDIV2_7 0x03000000 // System clock /7\r
+#define SYSCTL_RCC2_SYSDIV2_8 0x03800000 // System clock /8\r
+#define SYSCTL_RCC2_SYSDIV2_9 0x04000000 // System clock /9\r
+#define SYSCTL_RCC2_SYSDIV2_10 0x04800000 // System clock /10\r
+#define SYSCTL_RCC2_SYSDIV2_11 0x05000000 // System clock /11\r
+#define SYSCTL_RCC2_SYSDIV2_12 0x05800000 // System clock /12\r
+#define SYSCTL_RCC2_SYSDIV2_13 0x06000000 // System clock /13\r
+#define SYSCTL_RCC2_SYSDIV2_14 0x06800000 // System clock /14\r
+#define SYSCTL_RCC2_SYSDIV2_15 0x07000000 // System clock /15\r
+#define SYSCTL_RCC2_SYSDIV2_16 0x07800000 // System clock /16\r
+#define SYSCTL_RCC2_SYSDIV2_17 0x08000000 // System clock /17\r
+#define SYSCTL_RCC2_SYSDIV2_18 0x08800000 // System clock /18\r
+#define SYSCTL_RCC2_SYSDIV2_19 0x09000000 // System clock /19\r
+#define SYSCTL_RCC2_SYSDIV2_20 0x09800000 // System clock /20\r
+#define SYSCTL_RCC2_SYSDIV2_21 0x0A000000 // System clock /21\r
+#define SYSCTL_RCC2_SYSDIV2_22 0x0A800000 // System clock /22\r
+#define SYSCTL_RCC2_SYSDIV2_23 0x0B000000 // System clock /23\r
+#define SYSCTL_RCC2_SYSDIV2_24 0x0B800000 // System clock /24\r
+#define SYSCTL_RCC2_SYSDIV2_25 0x0C000000 // System clock /25\r
+#define SYSCTL_RCC2_SYSDIV2_26 0x0C800000 // System clock /26\r
+#define SYSCTL_RCC2_SYSDIV2_27 0x0D000000 // System clock /27\r
+#define SYSCTL_RCC2_SYSDIV2_28 0x0D800000 // System clock /28\r
+#define SYSCTL_RCC2_SYSDIV2_29 0x0E000000 // System clock /29\r
+#define SYSCTL_RCC2_SYSDIV2_30 0x0E800000 // System clock /30\r
+#define SYSCTL_RCC2_SYSDIV2_31 0x0F000000 // System clock /31\r
+#define SYSCTL_RCC2_SYSDIV2_32 0x0F800000 // System clock /32\r
+#define SYSCTL_RCC2_SYSDIV2_33 0x10000000 // System clock /33\r
+#define SYSCTL_RCC2_SYSDIV2_34 0x10800000 // System clock /34\r
+#define SYSCTL_RCC2_SYSDIV2_35 0x11000000 // System clock /35\r
+#define SYSCTL_RCC2_SYSDIV2_36 0x11800000 // System clock /36\r
+#define SYSCTL_RCC2_SYSDIV2_37 0x12000000 // System clock /37\r
+#define SYSCTL_RCC2_SYSDIV2_38 0x12800000 // System clock /38\r
+#define SYSCTL_RCC2_SYSDIV2_39 0x13000000 // System clock /39\r
+#define SYSCTL_RCC2_SYSDIV2_40 0x13800000 // System clock /40\r
+#define SYSCTL_RCC2_SYSDIV2_41 0x14000000 // System clock /41\r
+#define SYSCTL_RCC2_SYSDIV2_42 0x14800000 // System clock /42\r
+#define SYSCTL_RCC2_SYSDIV2_43 0x15000000 // System clock /43\r
+#define SYSCTL_RCC2_SYSDIV2_44 0x15800000 // System clock /44\r
+#define SYSCTL_RCC2_SYSDIV2_45 0x16000000 // System clock /45\r
+#define SYSCTL_RCC2_SYSDIV2_46 0x16800000 // System clock /46\r
+#define SYSCTL_RCC2_SYSDIV2_47 0x17000000 // System clock /47\r
+#define SYSCTL_RCC2_SYSDIV2_48 0x17800000 // System clock /48\r
+#define SYSCTL_RCC2_SYSDIV2_49 0x18000000 // System clock /49\r
+#define SYSCTL_RCC2_SYSDIV2_50 0x18800000 // System clock /50\r
+#define SYSCTL_RCC2_SYSDIV2_51 0x19000000 // System clock /51\r
+#define SYSCTL_RCC2_SYSDIV2_52 0x19800000 // System clock /52\r
+#define SYSCTL_RCC2_SYSDIV2_53 0x1A000000 // System clock /53\r
+#define SYSCTL_RCC2_SYSDIV2_54 0x1A800000 // System clock /54\r
+#define SYSCTL_RCC2_SYSDIV2_55 0x1B000000 // System clock /55\r
+#define SYSCTL_RCC2_SYSDIV2_56 0x1B800000 // System clock /56\r
+#define SYSCTL_RCC2_SYSDIV2_57 0x1C000000 // System clock /57\r
+#define SYSCTL_RCC2_SYSDIV2_58 0x1C800000 // System clock /58\r
+#define SYSCTL_RCC2_SYSDIV2_59 0x1D000000 // System clock /59\r
+#define SYSCTL_RCC2_SYSDIV2_60 0x1D800000 // System clock /60\r
+#define SYSCTL_RCC2_SYSDIV2_61 0x1E000000 // System clock /61\r
+#define SYSCTL_RCC2_SYSDIV2_62 0x1E800000 // System clock /62\r
+#define SYSCTL_RCC2_SYSDIV2_63 0x1F000000 // System clock /63\r
+#define SYSCTL_RCC2_SYSDIV2_64 0x1F800000 // System clock /64\r
+#define SYSCTL_RCC2_PWRDN2 0x00002000 // PLL power down\r
+#define SYSCTL_RCC2_BYPASS2 0x00000800 // PLL bypass\r
+#define SYSCTL_RCC2_OSCSRC2_MSK 0x00000070 // Oscillator input select\r
+#define SYSCTL_RCC2_OSCSRC2_MO 0x00000000 // Use the main oscillator\r
+#define SYSCTL_RCC2_OSCSRC2_IO 0x00000010 // Use the internal oscillator\r
+#define SYSCTL_RCC2_OSCSRC2_IO4 0x00000020 // Use the internal oscillator / 4\r
+#define SYSCTL_RCC2_OSCSRC2_30 0x00000030 // Use the 30 KHz internal osc.\r
+#define SYSCTL_RCC2_OSCSRC2_32 0x00000070 // Use the 32 KHz external osc.\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_DSLPCLKCFG register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_DSLPCLKCFG_D_MSK 0x1f800000 // Deep sleep system clock override\r
+#define SYSCTL_DSLPCLKCFG_D_2 0x00800000 // System clock /2\r
+#define SYSCTL_DSLPCLKCFG_D_3 0x01000000 // System clock /3\r
+#define SYSCTL_DSLPCLKCFG_D_4 0x01800000 // System clock /4\r
+#define SYSCTL_DSLPCLKCFG_D_5 0x02000000 // System clock /5\r
+#define SYSCTL_DSLPCLKCFG_D_6 0x02800000 // System clock /6\r
+#define SYSCTL_DSLPCLKCFG_D_7 0x03000000 // System clock /7\r
+#define SYSCTL_DSLPCLKCFG_D_8 0x03800000 // System clock /8\r
+#define SYSCTL_DSLPCLKCFG_D_9 0x04000000 // System clock /9\r
+#define SYSCTL_DSLPCLKCFG_D_10 0x04800000 // System clock /10\r
+#define SYSCTL_DSLPCLKCFG_D_11 0x05000000 // System clock /11\r
+#define SYSCTL_DSLPCLKCFG_D_12 0x05800000 // System clock /12\r
+#define SYSCTL_DSLPCLKCFG_D_13 0x06000000 // System clock /13\r
+#define SYSCTL_DSLPCLKCFG_D_14 0x06800000 // System clock /14\r
+#define SYSCTL_DSLPCLKCFG_D_15 0x07000000 // System clock /15\r
+#define SYSCTL_DSLPCLKCFG_D_16 0x07800000 // System clock /16\r
+#define SYSCTL_DSLPCLKCFG_D_17 0x08000000 // System clock /17\r
+#define SYSCTL_DSLPCLKCFG_D_18 0x08800000 // System clock /18\r
+#define SYSCTL_DSLPCLKCFG_D_19 0x09000000 // System clock /19\r
+#define SYSCTL_DSLPCLKCFG_D_20 0x09800000 // System clock /20\r
+#define SYSCTL_DSLPCLKCFG_D_21 0x0A000000 // System clock /21\r
+#define SYSCTL_DSLPCLKCFG_D_22 0x0A800000 // System clock /22\r
+#define SYSCTL_DSLPCLKCFG_D_23 0x0B000000 // System clock /23\r
+#define SYSCTL_DSLPCLKCFG_D_24 0x0B800000 // System clock /24\r
+#define SYSCTL_DSLPCLKCFG_D_25 0x0C000000 // System clock /25\r
+#define SYSCTL_DSLPCLKCFG_D_26 0x0C800000 // System clock /26\r
+#define SYSCTL_DSLPCLKCFG_D_27 0x0D000000 // System clock /27\r
+#define SYSCTL_DSLPCLKCFG_D_28 0x0D800000 // System clock /28\r
+#define SYSCTL_DSLPCLKCFG_D_29 0x0E000000 // System clock /29\r
+#define SYSCTL_DSLPCLKCFG_D_30 0x0E800000 // System clock /30\r
+#define SYSCTL_DSLPCLKCFG_D_31 0x0F000000 // System clock /31\r
+#define SYSCTL_DSLPCLKCFG_D_32 0x0F800000 // System clock /32\r
+#define SYSCTL_DSLPCLKCFG_D_33 0x10000000 // System clock /33\r
+#define SYSCTL_DSLPCLKCFG_D_34 0x10800000 // System clock /34\r
+#define SYSCTL_DSLPCLKCFG_D_35 0x11000000 // System clock /35\r
+#define SYSCTL_DSLPCLKCFG_D_36 0x11800000 // System clock /36\r
+#define SYSCTL_DSLPCLKCFG_D_37 0x12000000 // System clock /37\r
+#define SYSCTL_DSLPCLKCFG_D_38 0x12800000 // System clock /38\r
+#define SYSCTL_DSLPCLKCFG_D_39 0x13000000 // System clock /39\r
+#define SYSCTL_DSLPCLKCFG_D_40 0x13800000 // System clock /40\r
+#define SYSCTL_DSLPCLKCFG_D_41 0x14000000 // System clock /41\r
+#define SYSCTL_DSLPCLKCFG_D_42 0x14800000 // System clock /42\r
+#define SYSCTL_DSLPCLKCFG_D_43 0x15000000 // System clock /43\r
+#define SYSCTL_DSLPCLKCFG_D_44 0x15800000 // System clock /44\r
+#define SYSCTL_DSLPCLKCFG_D_45 0x16000000 // System clock /45\r
+#define SYSCTL_DSLPCLKCFG_D_46 0x16800000 // System clock /46\r
+#define SYSCTL_DSLPCLKCFG_D_47 0x17000000 // System clock /47\r
+#define SYSCTL_DSLPCLKCFG_D_48 0x17800000 // System clock /48\r
+#define SYSCTL_DSLPCLKCFG_D_49 0x18000000 // System clock /49\r
+#define SYSCTL_DSLPCLKCFG_D_50 0x18800000 // System clock /50\r
+#define SYSCTL_DSLPCLKCFG_D_51 0x19000000 // System clock /51\r
+#define SYSCTL_DSLPCLKCFG_D_52 0x19800000 // System clock /52\r
+#define SYSCTL_DSLPCLKCFG_D_53 0x1A000000 // System clock /53\r
+#define SYSCTL_DSLPCLKCFG_D_54 0x1A800000 // System clock /54\r
+#define SYSCTL_DSLPCLKCFG_D_55 0x1B000000 // System clock /55\r
+#define SYSCTL_DSLPCLKCFG_D_56 0x1B800000 // System clock /56\r
+#define SYSCTL_DSLPCLKCFG_D_57 0x1C000000 // System clock /57\r
+#define SYSCTL_DSLPCLKCFG_D_58 0x1C800000 // System clock /58\r
+#define SYSCTL_DSLPCLKCFG_D_59 0x1D000000 // System clock /59\r
+#define SYSCTL_DSLPCLKCFG_D_60 0x1D800000 // System clock /60\r
+#define SYSCTL_DSLPCLKCFG_D_61 0x1E000000 // System clock /61\r
+#define SYSCTL_DSLPCLKCFG_D_62 0x1E800000 // System clock /62\r
+#define SYSCTL_DSLPCLKCFG_D_63 0x1F000000 // System clock /63\r
+#define SYSCTL_DSLPCLKCFG_D_64 0x1F800000 // System clock /64\r
+#define SYSCTL_DSLPCLKCFG_O_MSK 0x00000070 // Deep sleep oscillator override\r
+#define SYSCTL_DSLPCLKCFG_O_IGN 0x00000000 // Do not override\r
+#define SYSCTL_DSLPCLKCFG_O_IO 0x00000010 // Use the internal oscillator\r
+#define SYSCTL_DSLPCLKCFG_O_30 0x00000030 // Use the 30 KHz internal osc.\r
+#define SYSCTL_DSLPCLKCFG_O_32 0x00000070 // Use the 32 KHz external osc.\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_CLKVCLR register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_CLKVCLR_CLR 0x00000001 // Clear clock verification fault\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_LDOARST register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_LDOARST_ARST 0x00000001 // Allow LDO to reset device\r
+\r
+#endif // __HW_SYSCTL_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_timer.h - Defines and macros used when accessing the timer.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_TIMER_H__\r
+#define __HW_TIMER_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the offsets of the timer registers.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_O_CFG 0x00000000 // Configuration register\r
+#define TIMER_O_TAMR 0x00000004 // TimerA mode register\r
+#define TIMER_O_TBMR 0x00000008 // TimerB mode register\r
+#define TIMER_O_CTL 0x0000000C // Control register\r
+#define TIMER_O_IMR 0x00000018 // Interrupt mask register\r
+#define TIMER_O_RIS 0x0000001C // Interrupt status register\r
+#define TIMER_O_MIS 0x00000020 // Masked interrupt status reg.\r
+#define TIMER_O_ICR 0x00000024 // Interrupt clear register\r
+#define TIMER_O_TAILR 0x00000028 // TimerA interval load register\r
+#define TIMER_O_TBILR 0x0000002C // TimerB interval load register\r
+#define TIMER_O_TAMATCHR 0x00000030 // TimerA match register\r
+#define TIMER_O_TBMATCHR 0x00000034 // TimerB match register\r
+#define TIMER_O_TAPR 0x00000038 // TimerA prescale register\r
+#define TIMER_O_TBPR 0x0000003C // TimerB prescale register\r
+#define TIMER_O_TAPMR 0x00000040 // TimerA prescale match register\r
+#define TIMER_O_TBPMR 0x00000044 // TimerB prescale match register\r
+#define TIMER_O_TAR 0x00000048 // TimerA register\r
+#define TIMER_O_TBR 0x0000004C // TimerB register\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the reset values of the timer registers.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_RV_CFG 0x00000000 // Configuration register RV\r
+#define TIMER_RV_TAMR 0x00000000 // TimerA mode register RV\r
+#define TIMER_RV_TBMR 0x00000000 // TimerB mode register RV\r
+#define TIMER_RV_CTL 0x00000000 // Control register RV\r
+#define TIMER_RV_IMR 0x00000000 // Interrupt mask register RV\r
+#define TIMER_RV_RIS 0x00000000 // Interrupt status register RV\r
+#define TIMER_RV_MIS 0x00000000 // Masked interrupt status reg RV\r
+#define TIMER_RV_ICR 0x00000000 // Interrupt clear register RV\r
+#define TIMER_RV_TAILR 0xFFFFFFFF // TimerA interval load reg RV\r
+#define TIMER_RV_TBILR 0x0000FFFF // TimerB interval load reg RV\r
+#define TIMER_RV_TAMATCHR 0xFFFFFFFF // TimerA match register RV\r
+#define TIMER_RV_TBMATCHR 0x0000FFFF // TimerB match register RV\r
+#define TIMER_RV_TAPR 0x00000000 // TimerA prescale register RV\r
+#define TIMER_RV_TBPR 0x00000000 // TimerB prescale register RV\r
+#define TIMER_RV_TAPMR 0x00000000 // TimerA prescale match reg RV\r
+#define TIMER_RV_TBPMR 0x00000000 // TimerB prescale match regi RV\r
+#define TIMER_RV_TAR 0xFFFFFFFF // TimerA register RV\r
+#define TIMER_RV_TBR 0x0000FFFF // TimerB register RV\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the TIMER_CFG register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_CFG_CFG_MSK 0x00000007 // Configuration options mask\r
+#define TIMER_CFG_16_BIT 0x00000004 // Two 16 bit timers\r
+#define TIMER_CFG_32_BIT_RTC 0x00000001 // 32 bit RTC\r
+#define TIMER_CFG_32_BIT_TIMER 0x00000000 // 32 bit timer\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the TIMER_TnMR register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_TNMR_TNAMS 0x00000008 // Alternate mode select\r
+#define TIMER_TNMR_TNCMR 0x00000004 // Capture mode - count or time\r
+#define TIMER_TNMR_TNTMR_MSK 0x00000003 // Timer mode mask\r
+#define TIMER_TNMR_TNTMR_CAP 0x00000003 // Mode - capture\r
+#define TIMER_TNMR_TNTMR_PERIOD 0x00000002 // Mode - periodic\r
+#define TIMER_TNMR_TNTMR_1_SHOT 0x00000001 // Mode - one shot\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the TIMER_CTL register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_CTL_TBPWML 0x00004000 // TimerB PWM output level invert\r
+#define TIMER_CTL_TBOTE 0x00002000 // TimerB output trigger enable\r
+#define TIMER_CTL_TBEVENT_MSK 0x00000C00 // TimerB event mode mask\r
+#define TIMER_CTL_TBEVENT_BOTH 0x00000C00 // TimerB event mode - both edges\r
+#define TIMER_CTL_TBEVENT_NEG 0x00000400 // TimerB event mode - neg edge\r
+#define TIMER_CTL_TBEVENT_POS 0x00000000 // TimerB event mode - pos edge\r
+#define TIMER_CTL_TBSTALL 0x00000200 // TimerB stall enable\r
+#define TIMER_CTL_TBEN 0x00000100 // TimerB enable\r
+#define TIMER_CTL_TAPWML 0x00000040 // TimerA PWM output level invert\r
+#define TIMER_CTL_TAOTE 0x00000020 // TimerA output trigger enable\r
+#define TIMER_CTL_RTCEN 0x00000010 // RTC counter enable\r
+#define TIMER_CTL_TAEVENT_MSK 0x0000000C // TimerA event mode mask\r
+#define TIMER_CTL_TAEVENT_BOTH 0x0000000C // TimerA event mode - both edges\r
+#define TIMER_CTL_TAEVENT_NEG 0x00000004 // TimerA event mode - neg edge\r
+#define TIMER_CTL_TAEVENT_POS 0x00000000 // TimerA event mode - pos edge\r
+#define TIMER_CTL_TASTALL 0x00000002 // TimerA stall enable\r
+#define TIMER_CTL_TAEN 0x00000001 // TimerA enable\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the TIMER_IMR register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_IMR_CBEIM 0x00000400 // CaptureB event interrupt mask\r
+#define TIMER_IMR_CBMIM 0x00000200 // CaptureB match interrupt mask\r
+#define TIMER_IMR_TBTOIM 0x00000100 // TimerB time out interrupt mask\r
+#define TIMER_IMR_RTCIM 0x00000008 // RTC interrupt mask\r
+#define TIMER_IMR_CAEIM 0x00000004 // CaptureA event interrupt mask\r
+#define TIMER_IMR_CAMIM 0x00000002 // CaptureA match interrupt mask\r
+#define TIMER_IMR_TATOIM 0x00000001 // TimerA time out interrupt mask\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the TIMER_RIS register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_RIS_CBERIS 0x00000400 // CaptureB event raw int status\r
+#define TIMER_RIS_CBMRIS 0x00000200 // CaptureB match raw int status\r
+#define TIMER_RIS_TBTORIS 0x00000100 // TimerB time out raw int status\r
+#define TIMER_RIS_RTCRIS 0x00000008 // RTC raw int status\r
+#define TIMER_RIS_CAERIS 0x00000004 // CaptureA event raw int status\r
+#define TIMER_RIS_CAMRIS 0x00000002 // CaptureA match raw int status\r
+#define TIMER_RIS_TATORIS 0x00000001 // TimerA time out raw int status\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the TIMER_MIS register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_RIS_CBEMIS 0x00000400 // CaptureB event masked int status\r
+#define TIMER_RIS_CBMMIS 0x00000200 // CaptureB match masked int status\r
+#define TIMER_RIS_TBTOMIS 0x00000100 // TimerB time out masked int stat\r
+#define TIMER_RIS_RTCMIS 0x00000008 // RTC masked int status\r
+#define TIMER_RIS_CAEMIS 0x00000004 // CaptureA event masked int status\r
+#define TIMER_RIS_CAMMIS 0x00000002 // CaptureA match masked int status\r
+#define TIMER_RIS_TATOMIS 0x00000001 // TimerA time out masked int stat\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the TIMER_ICR register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_ICR_CBECINT 0x00000400 // CaptureB event interrupt clear\r
+#define TIMER_ICR_CBMCINT 0x00000200 // CaptureB match interrupt clear\r
+#define TIMER_ICR_TBTOCINT 0x00000100 // TimerB time out interrupt clear\r
+#define TIMER_ICR_RTCCINT 0x00000008 // RTC interrupt clear\r
+#define TIMER_ICR_CAECINT 0x00000004 // CaptureA event interrupt clear\r
+#define TIMER_ICR_CAMCINT 0x00000002 // CaptureA match interrupt clear\r
+#define TIMER_ICR_TATOCINT 0x00000001 // TimerA time out interrupt clear\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the TIMER_TAILR register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_TAILR_TAILRH 0xFFFF0000 // TimerB load val in 32 bit mode\r
+#define TIMER_TAILR_TAILRL 0x0000FFFF // TimerA interval load value\r
+\r
+//*****************************************************************************\r
+//\r
+// The following defines the bit fields in the TIMER_TBILR register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_TBILR_TBILRL 0x0000FFFF // TimerB interval load value\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the TIMER_TAMATCHR register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_TAMATCHR_TAMRH 0xFFFF0000 // TimerB match val in 32 bit mode\r
+#define TIMER_TAMATCHR_TAMRL 0x0000FFFF // TimerA match value\r
+\r
+//*****************************************************************************\r
+//\r
+// The following defines the bit fields in the TIMER_TBMATCHR register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_TBMATCHR_TBMRL 0x0000FFFF // TimerB match load value\r
+\r
+//*****************************************************************************\r
+//\r
+// The following defines the bit fields in the TIMER_TnPR register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_TNPR_TNPSR 0x000000FF // TimerN prescale value\r
+\r
+//*****************************************************************************\r
+//\r
+// The following defines the bit fields in the TIMER_TnPMR register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_TNPMR_TNPSMR 0x000000FF // TimerN prescale match value\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the TIMER_TAR register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_TAR_TARH 0xFFFF0000 // TimerB val in 32 bit mode\r
+#define TIMER_TAR_TARL 0x0000FFFF // TimerA value\r
+\r
+//*****************************************************************************\r
+//\r
+// The following defines the bit fields in the TIMER_TBR register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_TBR_TBRL 0x0000FFFF // TimerB value\r
+\r
+#endif // __HW_TIMER_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_types.h - Common types and macros.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_TYPES_H__\r
+#define __HW_TYPES_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// Define a boolean type, and values for true and false.\r
+//\r
+//*****************************************************************************\r
+typedef unsigned char tBoolean;\r
+\r
+#ifndef true\r
+#define true 1\r
+#endif\r
+\r
+#ifndef false\r
+#define false 0\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Macros for hardware access, both direct and via the bit-band region.\r
+//\r
+//*****************************************************************************\r
+#define HWREG(x) \\r
+ (*((volatile unsigned long *)(x)))\r
+#define HWREGH(x) \\r
+ (*((volatile unsigned short *)(x)))\r
+#define HWREGB(x) \\r
+ (*((volatile unsigned char *)(x)))\r
+#define HWREGBITW(x, b) \\r
+ HWREG(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \\r
+ (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2))\r
+#define HWREGBITH(x, b) \\r
+ HWREGH(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \\r
+ (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2))\r
+#define HWREGBITB(x, b) \\r
+ HWREGB(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \\r
+ (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2))\r
+\r
+//*****************************************************************************\r
+//\r
+// Helper Macros for determining silicon revisions, etc.\r
+//\r
+// These macros will be used by Driverlib at "run-time" to create necessary\r
+// conditional code blocks that will allow a single version of the Driverlib\r
+// "binary" code to support multiple(all) Stellaris silicon revisions.\r
+//\r
+// It is expected that these macros will be used inside of a standard 'C' \r
+// conditional block of code, e.g.\r
+//\r
+// if(DEVICE_IS_SANDSTORM())\r
+// {\r
+// do some Sandstorm specific code here.\r
+// }\r
+//\r
+// By default, these macros will be defined as run-time checks of the\r
+// appropriate register(s) to allow creation of run-time conditional code\r
+// blocks for a common DriverLib across the entire Stellaris family.\r
+//\r
+// However, if code-space optimization is required, these macros can be "hard-\r
+// coded" for a specific version of Stellaris silicon. Many compilers will\r
+// then detect the "hard-coded" conditionals, and appropriately optimize the\r
+// code blocks, eliminating any "unreachable" code. This would result in \r
+// a smaller Driverlib, thus producing a smaller final application size, but\r
+// at the cost of limiting the Driverlib binary to a specific Stellaris\r
+// silicon revision.\r
+//\r
+//*****************************************************************************\r
+#ifndef DEVICE_IS_SANDSTORM\r
+#define DEVICE_IS_SANDSTORM \\r
+ (((HWREG(SYSCTL_DID0) & SYSCTL_DID0_VER_MASK) == SYSCTL_DID0_VER_0) || \\r
+ (((HWREG(SYSCTL_DID0) & SYSCTL_DID0_VER_MASK) == SYSCTL_DID0_VER_1) && \\r
+ ((HWREG(SYSCTL_DID0) & SYSCTL_DID0_CLASS_MASK) == \\r
+ SYSCTL_DID0_CLASS_SANDSTORM)))\r
+#endif\r
+\r
+#ifndef DEVICE_IS_FURY\r
+#define DEVICE_IS_FURY \\r
+ (((HWREG(SYSCTL_DID0) & SYSCTL_DID0_VER_MASK) == SYSCTL_DID0_VER_1) && \\r
+ ((HWREG(SYSCTL_DID0) & SYSCTL_DID0_CLASS_MASK) == \\r
+ SYSCTL_DID0_CLASS_FURY))\r
+#endif\r
+\r
+#ifndef DEVICE_IS_REVA2\r
+#define DEVICE_IS_REVA2 \\r
+ (((HWREG(SYSCTL_DID0) & SYSCTL_DID0_MAJ_MASK) == SYSCTL_DID0_MAJ_A) && \\r
+ ((HWREG(SYSCTL_DID0) & SYSCTL_DID0_MIN_MASK) == SYSCTL_DID0_MIN_2))\r
+#endif\r
+\r
+#ifndef DEVICE_IS_REVC1\r
+#define DEVICE_IS_REVC1 \\r
+ (((HWREG(SYSCTL_DID0) & SYSCTL_DID0_MAJ_MASK) == SYSCTL_DID0_MAJ_C) && \\r
+ ((HWREG(SYSCTL_DID0) & SYSCTL_DID0_MIN_MASK) == SYSCTL_DID0_MIN_1))\r
+#endif\r
+\r
+#ifndef DEVICE_IS_REVC2\r
+#define DEVICE_IS_REVC2 \\r
+ (((HWREG(SYSCTL_DID0) & SYSCTL_DID0_MAJ_MASK) == SYSCTL_DID0_MAJ_C) && \\r
+ ((HWREG(SYSCTL_DID0) & SYSCTL_DID0_MIN_MASK) == SYSCTL_DID0_MIN_2))\r
+#endif\r
+\r
+#endif // __HW_TYPES_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_uart.h - Macros and defines used when accessing the UART hardware\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_UART_H__\r
+#define __HW_UART_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// UART Register Offsets.\r
+//\r
+//*****************************************************************************\r
+#define UART_O_DR 0x00000000 // Data Register\r
+#define UART_O_RSR 0x00000004 // Receive Status Register (read)\r
+#define UART_O_ECR 0x00000004 // Error Clear Register (write)\r
+#define UART_O_FR 0x00000018 // Flag Register (read only)\r
+#define UART_O_IBRD 0x00000024 // Integer Baud Rate Divisor Reg\r
+#define UART_O_FBRD 0x00000028 // Fractional Baud Rate Divisor Reg\r
+#define UART_O_LCR_H 0x0000002C // Line Control Register, HIGH byte\r
+#define UART_O_CTL 0x00000030 // Control Register\r
+#define UART_O_IFLS 0x00000034 // Interrupt FIFO Level Select Reg\r
+#define UART_O_IM 0x00000038 // Interrupt Mask Set/Clear Reg\r
+#define UART_O_RIS 0x0000003C // Raw Interrupt Status Register\r
+#define UART_O_MIS 0x00000040 // Masked Interrupt Status Register\r
+#define UART_O_ICR 0x00000044 // Interrupt Clear Register\r
+#define UART_O_PeriphID4 0x00000FD0 //\r
+#define UART_O_PeriphID5 0x00000FD4 //\r
+#define UART_O_PeriphID6 0x00000FD8 //\r
+#define UART_O_PeriphID7 0x00000FDC //\r
+#define UART_O_PeriphID0 0x00000FE0 //\r
+#define UART_O_PeriphID1 0x00000FE4 //\r
+#define UART_O_PeriphID2 0x00000FE8 //\r
+#define UART_O_PeriphID3 0x00000FEC //\r
+#define UART_O_PCellID0 0x00000FF0 //\r
+#define UART_O_PCellID1 0x00000FF4 //\r
+#define UART_O_PCellID2 0x00000FF8 //\r
+#define UART_O_PCellID3 0x00000FFC //\r
+\r
+//*****************************************************************************\r
+//\r
+// Data Register bits\r
+//\r
+//*****************************************************************************\r
+#define UART_DR_OE 0x00000800 // Overrun Error\r
+#define UART_DR_BE 0x00000400 // Break Error\r
+#define UART_DR_PE 0x00000200 // Parity Error\r
+#define UART_DR_FE 0x00000100 // Framing Error\r
+#define UART_DR_DATA_MASK 0x000000FF // UART data\r
+\r
+//*****************************************************************************\r
+//\r
+// Receive Status Register bits\r
+//\r
+//*****************************************************************************\r
+#define UART_RSR_OE 0x00000008 // Overrun Error\r
+#define UART_RSR_BE 0x00000004 // Break Error\r
+#define UART_RSR_PE 0x00000002 // Parity Error\r
+#define UART_RSR_FE 0x00000001 // Framing Error\r
+\r
+//*****************************************************************************\r
+//\r
+// Flag Register bits\r
+//\r
+//*****************************************************************************\r
+#define UART_FR_TXFE 0x00000080 // TX FIFO Empty\r
+#define UART_FR_RXFF 0x00000040 // RX FIFO Full\r
+#define UART_FR_TXFF 0x00000020 // TX FIFO Full\r
+#define UART_FR_RXFE 0x00000010 // RX FIFO Empty\r
+#define UART_FR_BUSY 0x00000008 // UART Busy\r
+\r
+//*****************************************************************************\r
+//\r
+// Integer baud-rate divisor\r
+//\r
+//*****************************************************************************\r
+#define UART_IBRD_DIVINT_MASK 0x0000FFFF // Integer baud-rate divisor\r
+\r
+//*****************************************************************************\r
+//\r
+// Fractional baud-rate divisor\r
+//\r
+//*****************************************************************************\r
+#define UART_FBRD_DIVFRAC_MASK 0x0000003F // Fractional baud-rate divisor\r
+\r
+//*****************************************************************************\r
+//\r
+// Line Control Register High bits\r
+//\r
+//*****************************************************************************\r
+#define UART_LCR_H_SPS 0x00000080 // Stick Parity Select\r
+#define UART_LCR_H_WLEN 0x00000060 // Word length\r
+#define UART_LCR_H_WLEN_8 0x00000060 // 8 bit data\r
+#define UART_LCR_H_WLEN_7 0x00000040 // 7 bit data\r
+#define UART_LCR_H_WLEN_6 0x00000020 // 6 bit data\r
+#define UART_LCR_H_WLEN_5 0x00000000 // 5 bit data\r
+#define UART_LCR_H_FEN 0x00000010 // Enable FIFO\r
+#define UART_LCR_H_STP2 0x00000008 // Two Stop Bits Select\r
+#define UART_LCR_H_EPS 0x00000004 // Even Parity Select\r
+#define UART_LCR_H_PEN 0x00000002 // Parity Enable\r
+#define UART_LCR_H_BRK 0x00000001 // Send Break\r
+\r
+//*****************************************************************************\r
+//\r
+// Control Register bits\r
+//\r
+//*****************************************************************************\r
+#define UART_CTL_RXE 0x00000200 // Receive Enable\r
+#define UART_CTL_TXE 0x00000100 // Transmit Enable\r
+#define UART_CTL_LBE 0x00000080 // Loopback Enable\r
+#define UART_CTL_SIRLP 0x00000004 // SIR (IrDA) Low Power Enable\r
+#define UART_CTL_SIREN 0x00000002 // SIR (IrDA) Enable\r
+#define UART_CTL_UARTEN 0x00000001 // UART Enable\r
+\r
+//*****************************************************************************\r
+//\r
+// Interrupt FIFO Level Select Register bits\r
+//\r
+//*****************************************************************************\r
+#define UART_IFLS_RX1_8 0x00000000 // 1/8 Full\r
+#define UART_IFLS_RX2_8 0x00000010 // 1/4 Full\r
+#define UART_IFLS_RX4_8 0x00000020 // 1/2 Full\r
+#define UART_IFLS_RX6_8 0x00000030 // 3/4 Full\r
+#define UART_IFLS_RX7_8 0x00000040 // 7/8 Full\r
+#define UART_IFLS_TX1_8 0x00000000 // 1/8 Full\r
+#define UART_IFLS_TX2_8 0x00000001 // 1/4 Full\r
+#define UART_IFLS_TX4_8 0x00000002 // 1/2 Full\r
+#define UART_IFLS_TX6_8 0x00000003 // 3/4 Full\r
+#define UART_IFLS_TX7_8 0x00000004 // 7/8 Full\r
+\r
+//*****************************************************************************\r
+//\r
+// Interrupt Mask Set/Clear Register bits\r
+//\r
+//*****************************************************************************\r
+#define UART_IM_OEIM 0x00000400 // Overrun Error Interrupt Mask\r
+#define UART_IM_BEIM 0x00000200 // Break Error Interrupt Mask\r
+#define UART_IM_PEIM 0x00000100 // Parity Error Interrupt Mask\r
+#define UART_IM_FEIM 0x00000080 // Framing Error Interrupt Mask\r
+#define UART_IM_RTIM 0x00000040 // Receive Timeout Interrupt Mask\r
+#define UART_IM_TXIM 0x00000020 // Transmit Interrupt Mask\r
+#define UART_IM_RXIM 0x00000010 // Receive Interrupt Mask\r
+\r
+//*****************************************************************************\r
+//\r
+// Raw Interrupt Status Register\r
+//\r
+//*****************************************************************************\r
+#define UART_RIS_OERIS 0x00000400 // Overrun Error Interrupt Status\r
+#define UART_RIS_BERIS 0x00000200 // Break Error Interrupt Status\r
+#define UART_RIS_PERIS 0x00000100 // Parity Error Interrupt Status\r
+#define UART_RIS_FERIS 0x00000080 // Framing Error Interrupt Status\r
+#define UART_RIS_RTRIS 0x00000040 // Receive Timeout Interrupt Status\r
+#define UART_RIS_TXRIS 0x00000020 // Transmit Interrupt Status\r
+#define UART_RIS_RXRIS 0x00000010 // Receive Interrupt Status\r
+\r
+//*****************************************************************************\r
+//\r
+// Masked Interrupt Status Register\r
+//\r
+//*****************************************************************************\r
+#define UART_MIS_OEMIS 0x00000400 // Overrun Error Interrupt Status\r
+#define UART_MIS_BEMIS 0x00000200 // Break Error Interrupt Status\r
+#define UART_MIS_PEMIS 0x00000100 // Parity Error Interrupt Status\r
+#define UART_MIS_FEMIS 0x00000080 // Framing Error Interrupt Status\r
+#define UART_MIS_RTMIS 0x00000040 // Receive Timeout Interrupt Status\r
+#define UART_MIS_TXMIS 0x00000020 // Transmit Interrupt Status\r
+#define UART_MIS_RXMIS 0x00000010 // Receive Interrupt Status\r
+\r
+//*****************************************************************************\r
+//\r
+// Interrupt Clear Register bits\r
+//\r
+//*****************************************************************************\r
+#define UART_ICR_OEIC 0x00000400 // Overrun Error Interrupt Clear\r
+#define UART_ICR_BEIC 0x00000200 // Break Error Interrupt Clear\r
+#define UART_ICR_PEIC 0x00000100 // Parity Error Interrupt Clear\r
+#define UART_ICR_FEIC 0x00000080 // Framing Error Interrupt Clear\r
+#define UART_ICR_RTIC 0x00000040 // Receive Timeout Interrupt Clear\r
+#define UART_ICR_TXIC 0x00000020 // Transmit Interrupt Clear\r
+#define UART_ICR_RXIC 0x00000010 // Receive Interrupt Clear\r
+\r
+#define UART_RSR_ANY (UART_RSR_OE | \\r
+ UART_RSR_BE | \\r
+ UART_RSR_PE | \\r
+ UART_RSR_FE)\r
+\r
+//*****************************************************************************\r
+//\r
+// Reset Values for UART Registers.\r
+//\r
+//*****************************************************************************\r
+#define UART_RV_DR 0x00000000\r
+#define UART_RV_RSR 0x00000000\r
+#define UART_RV_ECR 0x00000000\r
+#define UART_RV_FR 0x00000090\r
+#define UART_RV_IBRD 0x00000000\r
+#define UART_RV_FBRD 0x00000000\r
+#define UART_RV_LCR_H 0x00000000\r
+#define UART_RV_CTL 0x00000300\r
+#define UART_RV_IFLS 0x00000012\r
+#define UART_RV_IM 0x00000000\r
+#define UART_RV_RIS 0x00000000\r
+#define UART_RV_MIS 0x00000000\r
+#define UART_RV_ICR 0x00000000\r
+#define UART_RV_PeriphID4 0x00000000\r
+#define UART_RV_PeriphID5 0x00000000\r
+#define UART_RV_PeriphID6 0x00000000\r
+#define UART_RV_PeriphID7 0x00000000\r
+#define UART_RV_PeriphID0 0x00000011\r
+#define UART_RV_PeriphID1 0x00000000\r
+#define UART_RV_PeriphID2 0x00000018\r
+#define UART_RV_PeriphID3 0x00000001\r
+#define UART_RV_PCellID0 0x0000000D\r
+#define UART_RV_PCellID1 0x000000F0\r
+#define UART_RV_PCellID2 0x00000005\r
+#define UART_RV_PCellID3 0x000000B1\r
+\r
+#endif // __HW_UART_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_watchdog.h - Macros used when accessing the Watchdog Timer hardware.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_WATCHDOG_H__\r
+#define __HW_WATCHDOG_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the offsets of the Watchdog Timer registers.\r
+//\r
+//*****************************************************************************\r
+#define WDT_O_LOAD 0x00000000 // Load register\r
+#define WDT_O_VALUE 0x00000004 // Current value register\r
+#define WDT_O_CTL 0x00000008 // Control register\r
+#define WDT_O_ICR 0x0000000C // Interrupt clear register\r
+#define WDT_O_RIS 0x00000010 // Raw interrupt status register\r
+#define WDT_O_MIS 0x00000014 // Masked interrupt status register\r
+#define WDT_O_TEST 0x00000418 // Test register\r
+#define WDT_O_LOCK 0x00000C00 // Lock register\r
+#define WDT_O_PeriphID4 0x00000FD0 //\r
+#define WDT_O_PeriphID5 0x00000FD4 //\r
+#define WDT_O_PeriphID6 0x00000FD8 //\r
+#define WDT_O_PeriphID7 0x00000FDC //\r
+#define WDT_O_PeriphID0 0x00000FE0 //\r
+#define WDT_O_PeriphID1 0x00000FE4 //\r
+#define WDT_O_PeriphID2 0x00000FE8 //\r
+#define WDT_O_PeriphID3 0x00000FEC //\r
+#define WDT_O_PCellID0 0x00000FF0 //\r
+#define WDT_O_PCellID1 0x00000FF4 //\r
+#define WDT_O_PCellID2 0x00000FF8 //\r
+#define WDT_O_PCellID3 0x00000FFC //\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the WDT_CTL register.\r
+//\r
+//*****************************************************************************\r
+#define WDT_CTL_RESEN 0x00000002 // Enable reset output\r
+#define WDT_CTL_INTEN 0x00000001 // Enable the WDT counter and int\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the WDT_ISR, WDT_RIS, and WDT_MIS\r
+// registers.\r
+//\r
+//*****************************************************************************\r
+#define WDT_INT_TIMEOUT 0x00000001 // Watchdog timer expired\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the WDT_TEST register.\r
+//\r
+//*****************************************************************************\r
+#define WDT_TEST_STALL 0x00000100 // Watchdog stall enable\r
+#ifndef DEPRECATED\r
+#define WDT_TEST_STALL_EN 0x00000100 // Watchdog stall enable\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the WDT_LOCK register.\r
+//\r
+//*****************************************************************************\r
+#define WDT_LOCK_LOCKED 0x00000001 // Watchdog timer is locked\r
+#define WDT_LOCK_UNLOCKED 0x00000000 // Watchdog timer is unlocked\r
+#define WDT_LOCK_UNLOCK 0x1ACCE551 // Unlocks the watchdog timer\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the reset values for the WDT registers.\r
+//\r
+//*****************************************************************************\r
+#define WDT_RV_LOAD 0xFFFFFFFF // Load register\r
+#define WDT_RV_VALUE 0xFFFFFFFF // Current value register\r
+#define WDT_RV_CTL 0x00000000 // Control register\r
+#define WDT_RV_RIS 0x00000000 // Raw interrupt status register\r
+#define WDT_RV_MIS 0x00000000 // Masked interrupt status register\r
+#define WDT_RV_LOCK 0x00000000 // Lock register\r
+#define WDT_RV_PeriphID4 0x00000000 //\r
+#define WDT_RV_PeriphID5 0x00000000 //\r
+#define WDT_RV_PeriphID6 0x00000000 //\r
+#define WDT_RV_PeriphID7 0x00000000 //\r
+#define WDT_RV_PeriphID0 0x00000005 //\r
+#define WDT_RV_PeriphID1 0x00000018 //\r
+#define WDT_RV_PeriphID2 0x00000018 //\r
+#define WDT_RV_PeriphID3 0x00000001 //\r
+#define WDT_RV_PCellID0 0x0000000D //\r
+#define WDT_RV_PCellID1 0x000000F0 //\r
+#define WDT_RV_PCellID2 0x00000005 //\r
+#define WDT_RV_PCellID3 0x000000B1 //\r
+\r
+#endif // __HW_WATCHDOG_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// i2c.h - Prototypes for the I2C Driver.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __I2C_H__\r
+#define __I2C_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Defines for the API.\r
+//\r
+//*****************************************************************************\r
+//*****************************************************************************\r
+//\r
+// Interrupt defines.\r
+//\r
+//*****************************************************************************\r
+#define I2C_INT_MASTER 0x00000001\r
+#define I2C_INT_SLAVE 0x00000002\r
+\r
+//*****************************************************************************\r
+//\r
+// I2C Master commands.\r
+//\r
+//*****************************************************************************\r
+#define I2C_MASTER_CMD_SINGLE_SEND \\r
+ (I2C_MASTER_CS_STOP | I2C_MASTER_CS_START | I2C_MASTER_CS_RUN)\r
+#define I2C_MASTER_CMD_SINGLE_RECEIVE \\r
+ (I2C_MASTER_CS_STOP | I2C_MASTER_CS_START | I2C_MASTER_CS_RUN)\r
+#define I2C_MASTER_CMD_BURST_SEND_START \\r
+ (I2C_MASTER_CS_START | I2C_MASTER_CS_RUN)\r
+#define I2C_MASTER_CMD_BURST_SEND_CONT \\r
+ (I2C_MASTER_CS_RUN)\r
+#define I2C_MASTER_CMD_BURST_SEND_FINISH \\r
+ (I2C_MASTER_CS_STOP | I2C_MASTER_CS_RUN)\r
+#define I2C_MASTER_CMD_BURST_SEND_ERROR_STOP \\r
+ (I2C_MASTER_CS_STOP)\r
+#define I2C_MASTER_CMD_BURST_RECEIVE_START \\r
+ (I2C_MASTER_CS_ACK | I2C_MASTER_CS_START | I2C_MASTER_CS_RUN)\r
+#define I2C_MASTER_CMD_BURST_RECEIVE_CONT \\r
+ (I2C_MASTER_CS_ACK | I2C_MASTER_CS_RUN)\r
+#define I2C_MASTER_CMD_BURST_RECEIVE_FINISH \\r
+ (I2C_MASTER_CS_STOP | I2C_MASTER_CS_RUN)\r
+#define I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP \\r
+ (I2C_MASTER_CS_STOP | I2C_MASTER_CS_RUN)\r
+\r
+//*****************************************************************************\r
+//\r
+// I2C Master error status.\r
+//\r
+//*****************************************************************************\r
+#define I2C_MASTER_ERR_NONE 0\r
+#define I2C_MASTER_ERR_ADDR_ACK 0x00000004\r
+#define I2C_MASTER_ERR_DATA_ACK 0x00000008\r
+#define I2C_MASTER_ERR_ARB_LOST 0x00000010\r
+\r
+//*****************************************************************************\r
+//\r
+// I2C Slave action requests\r
+//\r
+//*****************************************************************************\r
+#define I2C_SLAVE_ACT_NONE 0\r
+#define I2C_SLAVE_ACT_RREQ 0x00000001 // Master has sent data\r
+#define I2C_SLAVE_ACT_TREQ 0x00000002 // Master has requested data\r
+\r
+//*****************************************************************************\r
+// Miscellaneous I2C driver definitions.\r
+//*****************************************************************************\r
+#define I2C_MASTER_MAX_RETRIES 1000 // Number of retries\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+extern void I2CIntRegister(unsigned long ulBase, void(fnHandler)(void));\r
+extern void I2CIntUnregister(unsigned long ulBase);\r
+extern tBoolean I2CMasterBusBusy(unsigned long ulBase);\r
+extern tBoolean I2CMasterBusy(unsigned long ulBase);\r
+extern void I2CMasterControl(unsigned long ulBase, unsigned long ulCmd);\r
+extern unsigned long I2CMasterDataGet(unsigned long ulBase);\r
+extern void I2CMasterDataPut(unsigned long ulBase, unsigned char ucData);\r
+extern void I2CMasterDisable(unsigned long ulBase);\r
+extern void I2CMasterEnable(unsigned long ulBase);\r
+extern unsigned long I2CMasterErr(unsigned long ulBase);\r
+extern void I2CMasterInit(unsigned long ulBase, tBoolean bFast);\r
+extern void I2CMasterIntClear(unsigned long ulBase);\r
+extern void I2CMasterIntDisable(unsigned long ulBase);\r
+extern void I2CMasterIntEnable(unsigned long ulBase);\r
+extern tBoolean I2CMasterIntStatus(unsigned long ulBase, tBoolean bMasked);\r
+extern void I2CMasterSlaveAddrSet(unsigned long ulBase,\r
+ unsigned char ucSlaveAddr,\r
+ tBoolean bReceive);\r
+extern unsigned long I2CSlaveDataGet(unsigned long ulBase);\r
+extern void I2CSlaveDataPut(unsigned long ulBase, unsigned char ucData);\r
+extern void I2CSlaveDisable(unsigned long ulBase);\r
+extern void I2CSlaveEnable(unsigned long ulBase);\r
+extern void I2CSlaveInit(unsigned long ulBase, unsigned char ucSlaveAddr);\r
+extern void I2CSlaveIntClear(unsigned long ulBase);\r
+extern void I2CSlaveIntDisable(unsigned long ulBase);\r
+extern void I2CSlaveIntEnable(unsigned long ulBase);\r
+extern tBoolean I2CSlaveIntStatus(unsigned long ulBase, tBoolean bMasked);\r
+extern unsigned long I2CSlaveStatus(unsigned long ulBase);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __I2C_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// interrupt.h - Prototypes for the NVIC Interrupt Controller Driver.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __INTERRUPT_H__\r
+#define __INTERRUPT_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+extern void IntMasterEnable(void);\r
+extern void IntMasterDisable(void);\r
+extern void IntRegister(unsigned long ulInterrupt, void (*pfnHandler)(void));\r
+extern void IntUnregister(unsigned long ulInterrupt);\r
+extern void IntPriorityGroupingSet(unsigned long ulBits);\r
+extern unsigned long IntPriorityGroupingGet(void);\r
+extern void IntPrioritySet(unsigned long ulInterrupt,\r
+ unsigned char ucPriority);\r
+extern long IntPriorityGet(unsigned long ulInterrupt);\r
+extern void IntEnable(unsigned long ulInterrupt);\r
+extern void IntDisable(unsigned long ulInterrupt);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __INTERRUPT_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// flash.h - Prototypes for the flash driver.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __FLASH_H__\r
+#define __FLASH_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to FlashProtectSet(), and returned by\r
+// FlashProtectGet().\r
+//\r
+//*****************************************************************************\r
+typedef enum\r
+{\r
+ FlashReadWrite, // Flash can be read and written\r
+ FlashReadOnly, // Flash can only be read\r
+ FlashExecuteOnly // Flash can only be executed\r
+}\r
+tFlashProtection;\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+extern unsigned long FlashUsecGet(void);\r
+extern void FlashUsecSet(unsigned long ulClocks);\r
+extern long FlashErase(unsigned long ulAddress);\r
+extern long FlashProgram(unsigned long *pulData, unsigned long ulAddress,\r
+ unsigned long ulCount);\r
+extern tFlashProtection FlashProtectGet(unsigned long ulAddress);\r
+extern long FlashProtectSet(unsigned long ulAddress,\r
+ tFlashProtection eProtect);\r
+extern long FlashProtectSave(void);\r
+extern long FlashUserGet(unsigned long *pulUser0, unsigned long *pulUser1);\r
+extern long FlashUserSet(unsigned long ulUser0, unsigned long ulUser1);\r
+extern long FlashUserSave(void);\r
+extern void FlashIntRegister(void (*pfnHandler)(void));\r
+extern void FlashIntUnregister(void);\r
+extern void FlashIntEnable(unsigned long ulIntFlags);\r
+extern void FlashIntDisable(unsigned long ulIntFlags);\r
+extern unsigned long FlashIntGetStatus(tBoolean bMasked);\r
+extern void FlashIntClear(unsigned long ulIntFlags);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __FLASH_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// timer.h - Prototypes for the timer module\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __TIMER_H__\r
+#define __TIMER_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to TimerConfigure as the ulConfig parameter.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_CFG_32_BIT_OS 0x00000001 // 32-bit one-shot timer\r
+#define TIMER_CFG_32_BIT_PER 0x00000002 // 32-bit periodic timer\r
+#define TIMER_CFG_32_RTC 0x01000000 // 32-bit RTC timer\r
+#define TIMER_CFG_16_BIT_PAIR 0x04000000 // Two 16-bit timers\r
+#define TIMER_CFG_A_ONE_SHOT 0x00000001 // Timer A one-shot timer\r
+#define TIMER_CFG_A_PERIODIC 0x00000002 // Timer A periodic timer\r
+#define TIMER_CFG_A_CAP_COUNT 0x00000003 // Timer A event counter\r
+#define TIMER_CFG_A_CAP_TIME 0x00000007 // Timer A event timer\r
+#define TIMER_CFG_A_PWM 0x0000000A // Timer A PWM output\r
+#define TIMER_CFG_B_ONE_SHOT 0x00000100 // Timer B one-shot timer\r
+#define TIMER_CFG_B_PERIODIC 0x00000200 // Timer B periodic timer\r
+#define TIMER_CFG_B_CAP_COUNT 0x00000300 // Timer B event counter\r
+#define TIMER_CFG_B_CAP_TIME 0x00000700 // Timer B event timer\r
+#define TIMER_CFG_B_PWM 0x00000A00 // Timer B PWM output\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to TimerIntEnable, TimerIntDisable, and\r
+// TimerIntClear as the ulIntFlags parameter, and returned from TimerIntStatus.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_CAPB_EVENT 0x00000400 // CaptureB event interrupt\r
+#define TIMER_CAPB_MATCH 0x00000200 // CaptureB match interrupt\r
+#define TIMER_TIMB_TIMEOUT 0x00000100 // TimerB time out interrupt\r
+#define TIMER_RTC_MATCH 0x00000008 // RTC interrupt mask\r
+#define TIMER_CAPA_EVENT 0x00000004 // CaptureA event interrupt\r
+#define TIMER_CAPA_MATCH 0x00000002 // CaptureA match interrupt\r
+#define TIMER_TIMA_TIMEOUT 0x00000001 // TimerA time out interrupt\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to TimerControlEvent as the ulEvent parameter.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_EVENT_POS_EDGE 0x00000000 // Count positive edges\r
+#define TIMER_EVENT_NEG_EDGE 0x00000404 // Count negative edges\r
+#define TIMER_EVENT_BOTH_EDGES 0x00000C0C // Count both edges\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to most of the timer APIs as the ulTimer\r
+// parameter.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_A 0x000000ff // Timer A\r
+#define TIMER_B 0x0000ff00 // Timer B\r
+#define TIMER_BOTH 0x0000ffff // Timer Both\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+extern void TimerEnable(unsigned long ulBase, unsigned long ulTimer);\r
+extern void TimerDisable(unsigned long ulBase, unsigned long ulTimer);\r
+extern void TimerConfigure(unsigned long ulBase, unsigned long ulConfig);\r
+extern void TimerControlLevel(unsigned long ulBase, unsigned long ulTimer,\r
+ tBoolean bInvert);\r
+extern void TimerControlTrigger(unsigned long ulBase, unsigned long ulTimer,\r
+ tBoolean bEnable);\r
+extern void TimerControlEvent(unsigned long ulBase, unsigned long ulTimer,\r
+ unsigned long ulEvent);\r
+extern void TimerControlStall(unsigned long ulBase, unsigned long ulTimer,\r
+ tBoolean bStall);\r
+extern void TimerRTCEnable(unsigned long ulBase);\r
+extern void TimerRTCDisable(unsigned long ulBase);\r
+extern void TimerPrescaleSet(unsigned long ulBase, unsigned long ulTimer,\r
+ unsigned long ulValue);\r
+extern unsigned long TimerPrescaleGet(unsigned long ulBase,\r
+ unsigned long ulTimer);\r
+extern void TimerPrescaleMatchSet(unsigned long ulBase, unsigned long ulTimer,\r
+ unsigned long ulValue);\r
+extern unsigned long TimerPrescaleMatchGet(unsigned long ulBase,\r
+ unsigned long ulTimer);\r
+extern void TimerLoadSet(unsigned long ulBase, unsigned long ulTimer,\r
+ unsigned long ulValue);\r
+extern unsigned long TimerLoadGet(unsigned long ulBase, unsigned long ulTimer);\r
+extern unsigned long TimerValueGet(unsigned long ulBase,\r
+ unsigned long ulTimer);\r
+extern void TimerMatchSet(unsigned long ulBase, unsigned long ulTimer,\r
+ unsigned long ulValue);\r
+extern unsigned long TimerMatchGet(unsigned long ulBase,\r
+ unsigned long ulTimer);\r
+extern void TimerIntRegister(unsigned long ulBase, unsigned long ulTimer,\r
+ void (*pfnHandler)(void));\r
+extern void TimerIntUnregister(unsigned long ulBase, unsigned long ulTimer);\r
+extern void TimerIntEnable(unsigned long ulBase, unsigned long ulIntFlags);\r
+extern void TimerIntDisable(unsigned long ulBase, unsigned long ulIntFlags);\r
+extern unsigned long TimerIntStatus(unsigned long ulBase, tBoolean bMasked);\r
+extern void TimerIntClear(unsigned long ulBase, unsigned long ulIntFlags);\r
+extern void TimerQuiesce(unsigned long ulBase);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __TIMER_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// osram128x64x4.c - Driver for the OSRAM 128x64x4 graphical OLED display.\r
+//\r
+// Copyright (c) 2006-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+//*****************************************************************************\r
+//\r
+//! \addtogroup ek_lm3sx965_api\r
+//! @{\r
+//\r
+//*****************************************************************************\r
+\r
+#include "hw_ssi.h"\r
+#include "hw_memmap.h"\r
+#include "hw_sysctl.h"\r
+#include "hw_types.h"\r
+#include "debug.h"\r
+#include "gpio.h"\r
+#include "ssi.h"\r
+#include "sysctl.h"\r
+#include "osram128x64x4.h"\r
+\r
+//*****************************************************************************\r
+//\r
+// Flag to indicate if SSI port is enabled for OSRAM usage.\r
+//\r
+//*****************************************************************************\r
+static volatile tBoolean g_bSSIEnabled = false;\r
+\r
+//*****************************************************************************\r
+//\r
+// Define the OSRAM 128x64x4 Remap Setting(s). This will be used in\r
+// several places in the code to switch between vertical and horizontal\r
+// address incrementing.\r
+//\r
+// The Remap Command (0xA0) takes one 8-bit parameter. The parameter is\r
+// defined as follows.\r
+//\r
+// Bit 7: Reserved\r
+// Bit 6: Disable(0)/Enable(1) COM Split Odd Even\r
+// When enabled, the COM signals are split Odd on one side, even on\r
+// the other. Otherwise, they are split 0-39 on one side, 40-79 on\r
+// the other.\r
+// Bit 5: Reserved\r
+// Bit 4: Disable(0)/Enable(1) COM Remap\r
+// When Enabled, ROW 0-79 map to COM 79-0 (i.e. reverse row order)\r
+// Bit 3: Reserved\r
+// Bit 2: Horizontal(0)/Vertical(1) Address Increment\r
+// When set, data RAM address will increment along the column rather\r
+// than along the row.\r
+// Bit 1: Disable(0)/Enable(1) Nibble Remap\r
+// When enabled, the upper and lower nibbles in the DATA bus for access\r
+// to the data RAM are swapped.\r
+// Bit 0: Disable(0)/Enable(1) Column Address Remap\r
+// When enabled, DATA RAM columns 0-63 are remapped to Segment Columns\r
+// 127-0.\r
+//\r
+//*****************************************************************************\r
+#define OSRAM_INIT_REMAP 0x52\r
+#define OSRAM_INIT_OFFSET 0x4C\r
+static const unsigned char g_pucOSRAM128x64x4VerticalInc[] = { 0xA0, 0x56 };\r
+static const unsigned char g_pucOSRAM128x64x4HorizontalInc[] = { 0xA0, 0x52 };\r
+\r
+//*****************************************************************************\r
+//\r
+// A 5x7 font (in a 6x8 cell, where the sixth column is omitted from this\r
+// table) for displaying text on the OLED display. The data is organized as\r
+// bytes from the left column to the right column, with each byte containing\r
+// the top row in the LSB and the bottom row in the MSB.\r
+//\r
+// Note: This is the same font data that is used in the EK-LM3S811\r
+// osram96x16x1 driver. The single bit-per-pixel is expaned in the StringDraw\r
+// function to the appropriate four bit-per-pixel gray scale format.\r
+//\r
+//*****************************************************************************\r
+static const unsigned char g_pucFont[96][5] =\r
+{\r
+ { 0x00, 0x00, 0x00, 0x00, 0x00 }, // " "\r
+ { 0x00, 0x00, 0x4f, 0x00, 0x00 }, // !\r
+ { 0x00, 0x07, 0x00, 0x07, 0x00 }, // "\r
+ { 0x14, 0x7f, 0x14, 0x7f, 0x14 }, // #\r
+ { 0x24, 0x2a, 0x7f, 0x2a, 0x12 }, // $\r
+ { 0x23, 0x13, 0x08, 0x64, 0x62 }, // %\r
+ { 0x36, 0x49, 0x55, 0x22, 0x50 }, // &\r
+ { 0x00, 0x05, 0x03, 0x00, 0x00 }, // '\r
+ { 0x00, 0x1c, 0x22, 0x41, 0x00 }, // (\r
+ { 0x00, 0x41, 0x22, 0x1c, 0x00 }, // )\r
+ { 0x14, 0x08, 0x3e, 0x08, 0x14 }, // *\r
+ { 0x08, 0x08, 0x3e, 0x08, 0x08 }, // +\r
+ { 0x00, 0x50, 0x30, 0x00, 0x00 }, // ,\r
+ { 0x08, 0x08, 0x08, 0x08, 0x08 }, // -\r
+ { 0x00, 0x60, 0x60, 0x00, 0x00 }, // .\r
+ { 0x20, 0x10, 0x08, 0x04, 0x02 }, // /\r
+ { 0x3e, 0x51, 0x49, 0x45, 0x3e }, // 0\r
+ { 0x00, 0x42, 0x7f, 0x40, 0x00 }, // 1\r
+ { 0x42, 0x61, 0x51, 0x49, 0x46 }, // 2\r
+ { 0x21, 0x41, 0x45, 0x4b, 0x31 }, // 3\r
+ { 0x18, 0x14, 0x12, 0x7f, 0x10 }, // 4\r
+ { 0x27, 0x45, 0x45, 0x45, 0x39 }, // 5\r
+ { 0x3c, 0x4a, 0x49, 0x49, 0x30 }, // 6\r
+ { 0x01, 0x71, 0x09, 0x05, 0x03 }, // 7\r
+ { 0x36, 0x49, 0x49, 0x49, 0x36 }, // 8\r
+ { 0x06, 0x49, 0x49, 0x29, 0x1e }, // 9\r
+ { 0x00, 0x36, 0x36, 0x00, 0x00 }, // :\r
+ { 0x00, 0x56, 0x36, 0x00, 0x00 }, // ;\r
+ { 0x08, 0x14, 0x22, 0x41, 0x00 }, // <\r
+ { 0x14, 0x14, 0x14, 0x14, 0x14 }, // =\r
+ { 0x00, 0x41, 0x22, 0x14, 0x08 }, // >\r
+ { 0x02, 0x01, 0x51, 0x09, 0x06 }, // ?\r
+ { 0x32, 0x49, 0x79, 0x41, 0x3e }, // @\r
+ { 0x7e, 0x11, 0x11, 0x11, 0x7e }, // A\r
+ { 0x7f, 0x49, 0x49, 0x49, 0x36 }, // B\r
+ { 0x3e, 0x41, 0x41, 0x41, 0x22 }, // C\r
+ { 0x7f, 0x41, 0x41, 0x22, 0x1c }, // D\r
+ { 0x7f, 0x49, 0x49, 0x49, 0x41 }, // E\r
+ { 0x7f, 0x09, 0x09, 0x09, 0x01 }, // F\r
+ { 0x3e, 0x41, 0x49, 0x49, 0x7a }, // G\r
+ { 0x7f, 0x08, 0x08, 0x08, 0x7f }, // H\r
+ { 0x00, 0x41, 0x7f, 0x41, 0x00 }, // I\r
+ { 0x20, 0x40, 0x41, 0x3f, 0x01 }, // J\r
+ { 0x7f, 0x08, 0x14, 0x22, 0x41 }, // K\r
+ { 0x7f, 0x40, 0x40, 0x40, 0x40 }, // L\r
+ { 0x7f, 0x02, 0x0c, 0x02, 0x7f }, // M\r
+ { 0x7f, 0x04, 0x08, 0x10, 0x7f }, // N\r
+ { 0x3e, 0x41, 0x41, 0x41, 0x3e }, // O\r
+ { 0x7f, 0x09, 0x09, 0x09, 0x06 }, // P\r
+ { 0x3e, 0x41, 0x51, 0x21, 0x5e }, // Q\r
+ { 0x7f, 0x09, 0x19, 0x29, 0x46 }, // R\r
+ { 0x46, 0x49, 0x49, 0x49, 0x31 }, // S\r
+ { 0x01, 0x01, 0x7f, 0x01, 0x01 }, // T\r
+ { 0x3f, 0x40, 0x40, 0x40, 0x3f }, // U\r
+ { 0x1f, 0x20, 0x40, 0x20, 0x1f }, // V\r
+ { 0x3f, 0x40, 0x38, 0x40, 0x3f }, // W\r
+ { 0x63, 0x14, 0x08, 0x14, 0x63 }, // X\r
+ { 0x07, 0x08, 0x70, 0x08, 0x07 }, // Y\r
+ { 0x61, 0x51, 0x49, 0x45, 0x43 }, // Z\r
+ { 0x00, 0x7f, 0x41, 0x41, 0x00 }, // [\r
+ { 0x02, 0x04, 0x08, 0x10, 0x20 }, // "\"\r
+ { 0x00, 0x41, 0x41, 0x7f, 0x00 }, // ]\r
+ { 0x04, 0x02, 0x01, 0x02, 0x04 }, // ^\r
+ { 0x40, 0x40, 0x40, 0x40, 0x40 }, // _\r
+ { 0x00, 0x01, 0x02, 0x04, 0x00 }, // `\r
+ { 0x20, 0x54, 0x54, 0x54, 0x78 }, // a\r
+ { 0x7f, 0x48, 0x44, 0x44, 0x38 }, // b\r
+ { 0x38, 0x44, 0x44, 0x44, 0x20 }, // c\r
+ { 0x38, 0x44, 0x44, 0x48, 0x7f }, // d\r
+ { 0x38, 0x54, 0x54, 0x54, 0x18 }, // e\r
+ { 0x08, 0x7e, 0x09, 0x01, 0x02 }, // f\r
+ { 0x0c, 0x52, 0x52, 0x52, 0x3e }, // g\r
+ { 0x7f, 0x08, 0x04, 0x04, 0x78 }, // h\r
+ { 0x00, 0x44, 0x7d, 0x40, 0x00 }, // i\r
+ { 0x20, 0x40, 0x44, 0x3d, 0x00 }, // j\r
+ { 0x7f, 0x10, 0x28, 0x44, 0x00 }, // k\r
+ { 0x00, 0x41, 0x7f, 0x40, 0x00 }, // l\r
+ { 0x7c, 0x04, 0x18, 0x04, 0x78 }, // m\r
+ { 0x7c, 0x08, 0x04, 0x04, 0x78 }, // n\r
+ { 0x38, 0x44, 0x44, 0x44, 0x38 }, // o\r
+ { 0x7c, 0x14, 0x14, 0x14, 0x08 }, // p\r
+ { 0x08, 0x14, 0x14, 0x18, 0x7c }, // q\r
+ { 0x7c, 0x08, 0x04, 0x04, 0x08 }, // r\r
+ { 0x48, 0x54, 0x54, 0x54, 0x20 }, // s\r
+ { 0x04, 0x3f, 0x44, 0x40, 0x20 }, // t\r
+ { 0x3c, 0x40, 0x40, 0x20, 0x7c }, // u\r
+ { 0x1c, 0x20, 0x40, 0x20, 0x1c }, // v\r
+ { 0x3c, 0x40, 0x30, 0x40, 0x3c }, // w\r
+ { 0x44, 0x28, 0x10, 0x28, 0x44 }, // x\r
+ { 0x0c, 0x50, 0x50, 0x50, 0x3c }, // y\r
+ { 0x44, 0x64, 0x54, 0x4c, 0x44 }, // z\r
+ { 0x00, 0x08, 0x36, 0x41, 0x00 }, // {\r
+ { 0x00, 0x00, 0x7f, 0x00, 0x00 }, // |\r
+ { 0x00, 0x41, 0x36, 0x08, 0x00 }, // }\r
+ { 0x02, 0x01, 0x02, 0x04, 0x02 }, // ~\r
+ { 0x02, 0x01, 0x02, 0x04, 0x02 }, // ~\r
+};\r
+\r
+//*****************************************************************************\r
+//\r
+// The sequence of commands used to initialize the SSD0303 controller. Each\r
+// command is described as follows: there is a byte specifying the number of\r
+// bytes in the command sequence, followed by that many bytes of command data.\r
+// Note: This initialization sequence is derived from OSRAM App Note AN018.\r
+//\r
+//*****************************************************************************\r
+static const unsigned char g_pucOSRAM128x64x4Init[] =\r
+{\r
+ //\r
+ // Column Address\r
+ //\r
+ 4, 0x15, 0, 63, 0xe3,\r
+\r
+ //\r
+ // Row Address\r
+ //\r
+ 4, 0x75, 0, 63, 0xe3,\r
+\r
+ //\r
+ // Contrast Control\r
+ //\r
+ 3, 0x81, 50, 0xe3,\r
+\r
+ //\r
+ // Half Current Range\r
+ //\r
+ 2, 0x85, 0xe3,\r
+\r
+ //\r
+ // Display Re-map\r
+ //\r
+ 3, 0xA0, OSRAM_INIT_REMAP, 0xe3,\r
+\r
+ //\r
+ // Display Start Line\r
+ //\r
+ 3, 0xA1, 0, 0xe3,\r
+\r
+ //\r
+ // Display Offset\r
+ //\r
+ 3, 0xA2, OSRAM_INIT_OFFSET, 0xe3,\r
+\r
+ //\r
+ // Display Mode Normal\r
+ //\r
+ 2, 0xA4, 0xe3,\r
+\r
+ //\r
+ // Multiplex Ratio\r
+ //\r
+ 3, 0xA8, 63, 0xe3,\r
+\r
+ //\r
+ // Phase Length\r
+ //\r
+ 3, 0xB1, 0x22, 0xe3,\r
+\r
+ //\r
+ // Row Period\r
+ //\r
+ 3, 0xB2, 70, 0xe3,\r
+\r
+ //\r
+ // Display Clock Divide\r
+ //\r
+ 3, 0xB3, 0xF1, 0xe3,\r
+\r
+ //\r
+ // VSL\r
+ //\r
+ 3, 0xBF, 0x0D, 0xe3,\r
+\r
+ //\r
+ // VCOMH\r
+ //\r
+ 3, 0xBE, 0x02, 0xe3,\r
+\r
+ //\r
+ // VP\r
+ //\r
+ 3, 0xBC, 0x10, 0xe3,\r
+\r
+ //\r
+ // Gamma\r
+ //\r
+ 10, 0xB8, 0x01, 0x11, 0x22, 0x32, 0x43, 0x54, 0x65, 0x76, 0xe3,\r
+\r
+ //\r
+ // Set DC-DC\r
+ 3, 0xAD, 0x03, 0xe3,\r
+\r
+ //\r
+ // Display ON/OFF\r
+ //\r
+ 2, 0xAF, 0xe3,\r
+};\r
+\r
+//*****************************************************************************\r
+//\r
+//! \internal\r
+//!\r
+//! Write a sequence of command bytes to the SSD0323 controller.\r
+//!\r
+//! The data is written in a polled fashion; this function will not return\r
+//! until the entire byte sequence has been written to the controller.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+static void\r
+OSRAMWriteCommand(const unsigned char *pucBuffer, unsigned long ulCount)\r
+{\r
+ unsigned long ulTemp;\r
+\r
+ //\r
+ // Return iff SSI port is not enabled for OSRAM.\r
+ //\r
+ if(!g_bSSIEnabled)\r
+ {\r
+ return;\r
+ }\r
+\r
+ //\r
+ // Clear the command/control bit to enable command mode.\r
+ //\r
+ GPIOPinWrite(GPIO_PORTC_BASE, GPIO_PIN_7, 0);\r
+\r
+ //\r
+ // Loop while there are more bytes left to be transferred.\r
+ //\r
+ while(ulCount != 0)\r
+ {\r
+ //\r
+ // Write the next byte to the controller.\r
+ //\r
+ SSIDataPut(SSI0_BASE, *pucBuffer++);\r
+\r
+ //\r
+ // Dummy read to drain the fifo and time the GPIO signal.\r
+ //\r
+ SSIDataGet(SSI0_BASE, &ulTemp);\r
+\r
+ //\r
+ // Decrement the BYTE counter.\r
+ //\r
+ ulCount--;\r
+ }\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! \internal\r
+//!\r
+//! Write a sequence of data bytes to the SSD0323 controller.\r
+//!\r
+//! The data is written in a polled fashion; this function will not return\r
+//! until the entire byte sequence has been written to the controller.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+static void\r
+OSRAMWriteData(const unsigned char *pucBuffer, unsigned long ulCount)\r
+{\r
+ unsigned long ulTemp;\r
+\r
+ //\r
+ // Return iff SSI port is not enabled for OSRAM.\r
+ //\r
+ if(!g_bSSIEnabled)\r
+ {\r
+ return;\r
+ }\r
+\r
+ //\r
+ // Set the command/control bit to enable data mode.\r
+ //\r
+ GPIOPinWrite(GPIO_PORTC_BASE, GPIO_PIN_7, GPIO_PIN_7);\r
+\r
+ //\r
+ // Loop while there are more bytes left to be transferred.\r
+ //\r
+ while(ulCount != 0)\r
+ {\r
+ //\r
+ // Write the next byte to the controller.\r
+ //\r
+ SSIDataPut(SSI0_BASE, *pucBuffer++);\r
+\r
+ //\r
+ // Dummy read to drain the fifo and time the GPIO signal.\r
+ //\r
+ SSIDataGet(SSI0_BASE, &ulTemp);\r
+\r
+ //\r
+ // Decrement the BYTE counter.\r
+ //\r
+ ulCount--;\r
+ }\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! Clears the OLED display.\r
+//!\r
+//! This function will clear the display RAM. All pixels in the display will\r
+//! be turned off.\r
+//!\r
+//! This function is contained in <tt>osram128x64x4.c</tt>, with\r
+//! <tt>osram128x64x4.h</tt> containing the API definition for use by\r
+//! applications.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+void\r
+OSRAM128x64x4Clear(void)\r
+{\r
+ static const unsigned char pucCommand1[] = { 0x15, 0, 63 };\r
+ static const unsigned char pucCommand2[] = { 0x75, 0, 79 };\r
+ unsigned long ulRow, ulColumn;\r
+ static unsigned char pucZeroBuffer[8] = { 0, 0, 0, 0, 0, 0, 0, 0};\r
+\r
+ //\r
+ // Set the window to fill the entire display.\r
+ //\r
+ OSRAMWriteCommand(pucCommand1, sizeof(pucCommand1));\r
+ OSRAMWriteCommand(pucCommand2, sizeof(pucCommand2));\r
+ OSRAMWriteCommand(g_pucOSRAM128x64x4VerticalInc,\r
+ sizeof(g_pucOSRAM128x64x4VerticalInc));\r
+\r
+ //\r
+ // In vertical address increment mode, loop through each column, filling\r
+ // each row with 0.\r
+ //\r
+ for(ulColumn = 0; ulColumn < (128/2); ulColumn++)\r
+ {\r
+ //\r
+ // 8 rows (bytes) per row of text.\r
+ //\r
+ for(ulRow = 0; ulRow < 80; ulRow += 8)\r
+ {\r
+ OSRAMWriteData(pucZeroBuffer, sizeof(pucZeroBuffer));\r
+ }\r
+ }\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! Displays a string on the OLED display.\r
+//!\r
+//! \param pcStr is a pointer to the string to display.\r
+//! \param ulX is the horizontal position to display the string, specified in\r
+//! columns from the left edge of the display.\r
+//! \param ulY is the vertical position to display the string, specified in\r
+//! rows from the top edge of the display.\r
+//! \param ucLevel is the 4-bit grey scale value to be used for displayed text.\r
+//!\r
+//! This function will draw a string on the display. Only the ASCII characters\r
+//! between 32 (space) and 126 (tilde) are supported; other characters will\r
+//! result in random data being draw on the display (based on whatever appears\r
+//! before/after the font in memory). The font is mono-spaced, so characters\r
+//! such as "i" and "l" have more white space around them than characters such\r
+//! as "m" or "w".\r
+//!\r
+//! If the drawing of the string reaches the right edge of the display, no more\r
+//! characters will be drawn. Therefore, special care is not required to avoid\r
+//! supplying a string that is "too long" to display.\r
+//!\r
+//! This function is contained in <tt>osram128x64x4.c</tt>, with\r
+//! <tt>osram128x64x4.h</tt> containing the API definition for use by\r
+//! applications.\r
+//!\r
+//! \note Because the OLED display packs 2 pixels of data in a single byte, the\r
+//! parameter \e ulX must be an even column number (e.g. 0, 2, 4, etc).\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+void\r
+OSRAM128x64x4StringDraw(const char *pcStr, unsigned long ulX,\r
+ unsigned long ulY, unsigned char ucLevel)\r
+{\r
+ static unsigned char pucBuffer[8];\r
+ unsigned long ulIdx1, ulIdx2;\r
+ unsigned char ucTemp;\r
+\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT(ulX < 128);\r
+ ASSERT((ulX & 1) == 0);\r
+ ASSERT(ulY < 64);\r
+ ASSERT(ucLevel < 16);\r
+\r
+ //\r
+ // Setup a window starting at the specified column and row, ending\r
+ // at the right edge of the display and 8 rows down (single character row).\r
+ //\r
+ pucBuffer[0] = 0x15;\r
+ pucBuffer[1] = ulX / 2;\r
+ pucBuffer[2] = 63;\r
+ OSRAMWriteCommand(pucBuffer, 3);\r
+ pucBuffer[0] = 0x75;\r
+ pucBuffer[1] = ulY;\r
+ pucBuffer[2] = ulY + 7;\r
+ OSRAMWriteCommand(pucBuffer, 3);\r
+ OSRAMWriteCommand(g_pucOSRAM128x64x4VerticalInc,\r
+ sizeof(g_pucOSRAM128x64x4VerticalInc));\r
+\r
+ //\r
+ // Loop while there are more characters in the string.\r
+ //\r
+ while(*pcStr != 0)\r
+ {\r
+ //\r
+ // Get a working copy of the current character and convert to an\r
+ // index into the character bit-map array.\r
+ //\r
+ ucTemp = *pcStr;\r
+ ucTemp &= 0x7F;\r
+ if(ucTemp < ' ')\r
+ {\r
+ ucTemp = ' ';\r
+ }\r
+ else\r
+ {\r
+ ucTemp -= ' ';\r
+ }\r
+\r
+ //\r
+ // Build and display the character buffer.\r
+ //\r
+ for(ulIdx1 = 0; ulIdx1 < 3; ulIdx1++)\r
+ {\r
+ //\r
+ // Convert two columns of 1-bit font data into a single data\r
+ // byte column of 4-bit font data.\r
+ //\r
+ for(ulIdx2 = 0; ulIdx2 < 8; ulIdx2++)\r
+ {\r
+ pucBuffer[ulIdx2] = 0;\r
+ if(g_pucFont[ucTemp][ulIdx1*2] & (1 << ulIdx2))\r
+ {\r
+ pucBuffer[ulIdx2] = ((ucLevel << 4) & 0xf0);\r
+ }\r
+ if((ulIdx1 < 2) &&\r
+ (g_pucFont[ucTemp][ulIdx1*2+1] & (1 << ulIdx2)))\r
+ {\r
+ pucBuffer[ulIdx2] |= ((ucLevel << 0) & 0x0f);\r
+ }\r
+ }\r
+\r
+ //\r
+ // If there is room, dump the single data byte column to the\r
+ // display. Otherwise, bail out.\r
+ //\r
+ if(ulX < 126)\r
+ {\r
+ OSRAMWriteData(pucBuffer, 8);\r
+ ulX += 2;\r
+ }\r
+ else\r
+ {\r
+ return;\r
+ }\r
+ }\r
+\r
+ //\r
+ // Advance to the next character.\r
+ //\r
+ pcStr++;\r
+ }\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! Displays an image on the OLED display.\r
+//!\r
+//! \param pucImage is a pointer to the image data.\r
+//! \param ulX is the horizontal position to display this image, specified in\r
+//! columns from the left edge of the display.\r
+//! \param ulY is the vertical position to display this image, specified in\r
+//! rows from the top of the display.\r
+//! \param ulWidth is the width of the image, specified in columns.\r
+//! \param ulHeight is the height of the image, specified in rows.\r
+//!\r
+//! This function will display a bitmap graphic on the display. Because of the\r
+//! format of the display RAM, the starting column (/e ulX) and the number of\r
+//! columns (/e ulWidth) must be an integer multiple of two.\r
+//!\r
+//! The image data is organized with the first row of image data appearing left\r
+//! to right, followed immediately by the second row of image data. Each byte\r
+//! contains the data for two columns in the current row, with the leftmost\r
+//! column being contained in bits 7:4 and the rightmost column being contained\r
+//! in bits 3:0.\r
+//!\r
+//! For example, an image six columns wide and seven scan lines tall would\r
+//! be arranged as follows (showing how the twenty one bytes of the image would\r
+//! appear on the display):\r
+//!\r
+//! \verbatim\r
+//! +-------------------+-------------------+-------------------+\r
+//! | Byte 0 | Byte 1 | Byte 2 |\r
+//! +---------+---------+---------+---------+---------+---------+\r
+//! | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 |\r
+//! +---------+---------+---------+---------+---------+---------+\r
+//! | Byte 3 | Byte 4 | Byte 5 |\r
+//! +---------+---------+---------+---------+---------+---------+\r
+//! | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 |\r
+//! +---------+---------+---------+---------+---------+---------+\r
+//! | Byte 6 | Byte 7 | Byte 8 |\r
+//! +---------+---------+---------+---------+---------+---------+\r
+//! | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 |\r
+//! +---------+---------+---------+---------+---------+---------+\r
+//! | Byte 9 | Byte 10 | Byte 11 |\r
+//! +---------+---------+---------+---------+---------+---------+\r
+//! | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 |\r
+//! +---------+---------+---------+---------+---------+---------+\r
+//! | Byte 12 | Byte 13 | Byte 14 |\r
+//! +---------+---------+---------+--3------+---------+---------+\r
+//! | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 |\r
+//! +---------+---------+---------+---------+---------+---------+\r
+//! | Byte 15 | Byte 16 | Byte 17 |\r
+//! +---------+---------+---------+---------+---------+---------+\r
+//! | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 |\r
+//! +---------+---------+---------+---------+---------+---------+\r
+//! | Byte 18 | Byte 19 | Byte 20 |\r
+//! +---------+---------+---------+---------+---------+---------+\r
+//! | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 |\r
+//! +---------+---------+---------+---------+---------+---------+\r
+//! \endverbatim\r
+//!\r
+//! This function is contained in <tt>osram128x64x4.c</tt>, with\r
+//! <tt>osram128x64x4.h</tt> containing the API definition for use by`\r
+//! applications.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+void\r
+OSRAM128x64x4ImageDraw(const unsigned char *pucImage, unsigned long ulX,\r
+ unsigned long ulY, unsigned long ulWidth,\r
+ unsigned long ulHeight)\r
+{\r
+ static unsigned char pucBuffer[8];\r
+\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT(ulX < 128);\r
+ ASSERT((ulX & 1) == 0);\r
+ ASSERT(ulY < 64);\r
+ ASSERT((ulX + ulWidth) <= 128);\r
+ ASSERT((ulY + ulHeight) <= 64);\r
+ ASSERT((ulWidth & 1) == 0);\r
+\r
+ //\r
+ // Setup a window starting at the specified column and row, and ending\r
+ // at the column + width and row+height.\r
+ //\r
+ pucBuffer[0] = 0x15;\r
+ pucBuffer[1] = ulX / 2;\r
+ pucBuffer[2] = (ulX + ulWidth - 2) / 2;\r
+ OSRAMWriteCommand(pucBuffer, 3);\r
+ pucBuffer[0] = 0x75;\r
+ pucBuffer[1] = ulY;\r
+ pucBuffer[2] = ulY + ulHeight - 1;\r
+ OSRAMWriteCommand(pucBuffer, 3);\r
+ OSRAMWriteCommand(g_pucOSRAM128x64x4HorizontalInc,\r
+ sizeof(g_pucOSRAM128x64x4HorizontalInc));\r
+\r
+ //\r
+ // Loop while there are more rows to display.\r
+ //\r
+ while(ulHeight--)\r
+ {\r
+ //\r
+ // Write this row of image data.\r
+ //\r
+ OSRAMWriteData(pucImage, (ulWidth / 2));\r
+\r
+ //\r
+ // Advance to the next row of the image.\r
+ //\r
+ pucImage += (ulWidth / 2);\r
+ }\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! Enable the SSI component of the OLED display driver.\r
+//!\r
+//! \param ulFrequency specifies the SSI Clock Frequency to be used.\r
+//!\r
+//! This function initializes the SSI interface to the OLED display.\r
+//!\r
+//! This function is contained in <tt>osram128x64x4.c</tt>, with\r
+//! <tt>osram128x64x4.h</tt> containing the API definition for use by\r
+//! applications.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+void\r
+OSRAM128x64x4Enable(unsigned long ulFrequency)\r
+{\r
+ unsigned long ulTemp;\r
+\r
+ //\r
+ // Disable the SSI port.\r
+ //\r
+ SSIDisable(SSI0_BASE);\r
+\r
+ //\r
+ // Configure the SSI0 port for master mode.\r
+ //\r
+ SSIConfig(SSI0_BASE, SSI_FRF_MOTO_MODE_2, SSI_MODE_MASTER, ulFrequency, 8);\r
+\r
+ //\r
+ // (Re)Enable SSI control of the FSS pin.\r
+ //\r
+ GPIOPinTypeSSI(GPIO_PORTA_BASE, GPIO_PIN_3);\r
+ GPIOPadConfigSet(GPIO_PORTA_BASE, GPIO_PIN_3, GPIO_STRENGTH_8MA,\r
+ GPIO_PIN_TYPE_STD_WPU);\r
+\r
+ //\r
+ // Enable the SSI port.\r
+ //\r
+ SSIEnable(SSI0_BASE);\r
+\r
+ //\r
+ // Drain the receive fifo.\r
+ //\r
+ while(SSIDataNonBlockingGet(SSI0_BASE, &ulTemp) != 0)\r
+ {\r
+ }\r
+\r
+ //\r
+ // Indicate that the OSRAM driver can use the SSI Port.\r
+ //\r
+ g_bSSIEnabled = true;\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! Enable the SSI component of the OLED display driver.\r
+//!\r
+//! \param ulFrequency specifies the SSI Clock Frequency to be used.\r
+//!\r
+//! This function initializes the SSI interface to the OLED display.\r
+//!\r
+//! This function is contained in <tt>osram128x64x4.c</tt>, with\r
+//! <tt>osram128x64x4.h</tt> containing the API definition for use by\r
+//! applications.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+void\r
+OSRAM128x64x4Disable(void)\r
+{\r
+ unsigned long ulTemp;\r
+\r
+ //\r
+ // Indicate that the OSRAM driver can no longer use the SSI Port.\r
+ //\r
+ g_bSSIEnabled = false;\r
+\r
+ //\r
+ // Drain the receive fifo.\r
+ //\r
+ while(SSIDataNonBlockingGet(SSI0_BASE, &ulTemp) != 0)\r
+ {\r
+ }\r
+\r
+ //\r
+ // Disable the SSI port.\r
+ //\r
+ SSIDisable(SSI0_BASE);\r
+\r
+ //\r
+ // Disable SSI control of the FSS pin.\r
+ //\r
+ GPIODirModeSet(GPIO_PORTA_BASE, GPIO_PIN_3, GPIO_DIR_MODE_OUT);\r
+ GPIOPadConfigSet(GPIO_PORTA_BASE, GPIO_PIN_3, GPIO_STRENGTH_8MA,\r
+ GPIO_PIN_TYPE_STD_WPU);\r
+ GPIOPinWrite(GPIO_PORTA_BASE, GPIO_PIN_3, GPIO_PIN_3);\r
+\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! Initialize the OLED display.\r
+//!\r
+//! \param ulFrequency specifies the SSI Clock Frequency to be used.\r
+//!\r
+//! This function initializes the SSI interface to the OLED display and\r
+//! configures the SSD0323 controller on the panel.\r
+//!\r
+//! This function is contained in <tt>osram128x64x4.c</tt>, with\r
+//! <tt>osram128x64x4.h</tt> containing the API definition for use by\r
+//! applications.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+void\r
+OSRAM128x64x4Init(unsigned long ulFrequency)\r
+{\r
+ unsigned long ulIdx;\r
+\r
+ //\r
+ // Enable the SSI0 and GPIO port blocks as they are needed by this driver.\r
+ //\r
+ SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI0);\r
+ SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA);\r
+ SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOC);\r
+\r
+ //\r
+ // Configure the SSI0CLK and SSIOTX pins for SSI operation.\r
+ //\r
+ GPIOPinTypeSSI(GPIO_PORTA_BASE, GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_5);\r
+ GPIOPadConfigSet(GPIO_PORTA_BASE, GPIO_PIN_2, GPIO_STRENGTH_8MA,\r
+ GPIO_PIN_TYPE_STD_WPU);\r
+ GPIOPadConfigSet(GPIO_PORTA_BASE, GPIO_PIN_3, GPIO_STRENGTH_8MA,\r
+ GPIO_PIN_TYPE_STD_WPU);\r
+ GPIOPadConfigSet(GPIO_PORTA_BASE, GPIO_PIN_5, GPIO_STRENGTH_8MA,\r
+ GPIO_PIN_TYPE_STD_WPU);\r
+\r
+ //\r
+ // Configure the PC7 pin as a D/Cn signal for OLED device.\r
+ //\r
+ GPIODirModeSet(GPIO_PORTC_BASE, GPIO_PIN_7, GPIO_DIR_MODE_OUT);\r
+ GPIOPadConfigSet(GPIO_PORTC_BASE, GPIO_PIN_7, GPIO_STRENGTH_8MA,\r
+ GPIO_PIN_TYPE_STD);\r
+ GPIOPinWrite(GPIO_PORTC_BASE, GPIO_PIN_7, GPIO_PIN_7);\r
+\r
+ //\r
+ // Configure and enable the SSI0 port for master mode.\r
+ //\r
+ OSRAM128x64x4Enable(ulFrequency);\r
+\r
+ //\r
+ // Clear the frame buffer.\r
+ //\r
+ OSRAM128x64x4Clear();\r
+\r
+ //\r
+ // Initialize the SSD0323 controller. Loop through the initialization\r
+ // sequence array, sending each command "string" to the controller.\r
+ //\r
+ for(ulIdx = 0; ulIdx < sizeof(g_pucOSRAM128x64x4Init);\r
+ ulIdx += g_pucOSRAM128x64x4Init[ulIdx] + 1)\r
+ {\r
+ //\r
+ // Send this command.\r
+ //\r
+ OSRAMWriteCommand(g_pucOSRAM128x64x4Init + ulIdx + 1,\r
+ g_pucOSRAM128x64x4Init[ulIdx] - 1);\r
+ }\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! Turns on the OLED display.\r
+//!\r
+//! This function will turn on the OLED display, causing it to display the\r
+//! contents of its internal frame buffer.\r
+//!\r
+//! This function is contained in <tt>osram128x64x4.c</tt>, with\r
+//! <tt>osram128x64x4.h</tt> containing the API definition for use by\r
+//! applications.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+void\r
+OSRAM128x64x4DisplayOn(void)\r
+{\r
+ unsigned long ulIdx;\r
+\r
+ //\r
+ // Initialize the SSD0323 controller. Loop through the initialization\r
+ // sequence array, sending each command "string" to the controller.\r
+ //\r
+ for(ulIdx = 0; ulIdx < sizeof(g_pucOSRAM128x64x4Init);\r
+ ulIdx += g_pucOSRAM128x64x4Init[ulIdx] + 1)\r
+ {\r
+ //\r
+ // Send this command.\r
+ //\r
+ OSRAMWriteCommand(g_pucOSRAM128x64x4Init + ulIdx + 1,\r
+ g_pucOSRAM128x64x4Init[ulIdx] - 1);\r
+ }\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! Turns off the OLED display.\r
+//!\r
+//! This function will turn off the OLED display. This will stop the scanning\r
+//! of the panel and turn off the on-chip DC-DC converter, preventing damage to\r
+//! the panel due to burn-in (it has similar characters to a CRT in this\r
+//! respect).\r
+//!\r
+//! This function is contained in <tt>osram128x64x4.c</tt>, with\r
+//! <tt>osram128x64x4.h</tt> containing the API definition for use by\r
+//! applications.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+void\r
+OSRAM128x64x4DisplayOff(void)\r
+{\r
+ static const unsigned char pucCommand1[] =\r
+ {\r
+ 0xAE, 0xAD, 0x02\r
+ };\r
+\r
+ //\r
+ // Turn off the DC-DC converter and the display.\r
+ //\r
+ OSRAMWriteCommand(pucCommand1, sizeof(pucCommand1));\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+// Close the Doxygen group.\r
+//! @}\r
+//\r
+//*****************************************************************************\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// osram128x64x4.h - Prototypes for the driver for the OSRAM 128x64x4 graphical\r
+// OLED display.\r
+//\r
+// Copyright (c) 2006-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __OSRAM128X64X4_H__\r
+#define __OSRAM128X64X4_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the driver APIs.\r
+//\r
+//*****************************************************************************\r
+extern void OSRAM128x64x4Clear(void);\r
+extern void OSRAM128x64x4StringDraw(const char *pcStr,\r
+ unsigned long ulX,\r
+ unsigned long ulY,\r
+ unsigned char ucLevel);\r
+extern void OSRAM128x64x4ImageDraw(const unsigned char *pucImage,\r
+ unsigned long ulX,\r
+ unsigned long ulY,\r
+ unsigned long ulWidth,\r
+ unsigned long ulHeight);\r
+extern void OSRAM128x64x4Init(unsigned long ulFrequency);\r
+extern void OSRAM128x64x4Enable(unsigned long ulFrequency);\r
+extern void OSRAM128x64x4Disable(void);\r
+extern void OSRAM128x64x4DisplayOn(void);\r
+extern void OSRAM128x64x4DisplayOff(void);\r
+\r
+//*****************************************************************************\r
+//\r
+// The following macro(s) map old names for the OSRAM functions to the new\r
+// names. In new code, the new names should be used in favor of the old names.\r
+//\r
+//*****************************************************************************\r
+#ifndef DEPRECATED\r
+#define OSRAM128x64x1InitSSI OSRAM128x64x4Enable\r
+#endif\r
+\r
+#endif // __OSRAM128X64X4_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// pwm.h - API function protoypes for Pulse Width Modulation (PWM) ports\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __PWM_H__\r
+#define __PWM_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// The following defines are passed to PWMGenConfigure() as the ulConfig\r
+// parameter and specify the configuration of the PWM generator.\r
+//\r
+//*****************************************************************************\r
+#define PWM_GEN_MODE_DOWN 0x00000000 // Down count mode\r
+#define PWM_GEN_MODE_UP_DOWN 0x00000002 // Up/Down count mode\r
+#define PWM_GEN_MODE_SYNC 0x00000038 // Synchronous updates\r
+#define PWM_GEN_MODE_NO_SYNC 0x00000000 // Immediate updates\r
+#define PWM_GEN_MODE_DBG_RUN 0x00000004 // Continue running in debug mode\r
+#define PWM_GEN_MODE_DBG_STOP 0x00000000 // Stop running in debug mode\r
+\r
+//*****************************************************************************\r
+//\r
+// Defines for enabling, disabling, and clearing PWM generator interrupts and\r
+// triggers.\r
+//\r
+//*****************************************************************************\r
+#define PWM_INT_CNT_ZERO 0x00000001 // Int if COUNT = 0\r
+#define PWM_INT_CNT_LOAD 0x00000002 // Int if COUNT = LOAD\r
+#define PWM_INT_CNT_AU 0x00000004 // Int if COUNT = CMPA U\r
+#define PWM_INT_CNT_AD 0x00000008 // Int if COUNT = CMPA D\r
+#define PWM_INT_CNT_BU 0x00000010 // Int if COUNT = CMPA U\r
+#define PWM_INT_CNT_BD 0x00000020 // Int if COUNT = CMPA D\r
+#define PWM_TR_CNT_ZERO 0x00000100 // Trig if COUNT = 0\r
+#define PWM_TR_CNT_LOAD 0x00000200 // Trig if COUNT = LOAD\r
+#define PWM_TR_CNT_AU 0x00000400 // Trig if COUNT = CMPA U\r
+#define PWM_TR_CNT_AD 0x00000800 // Trig if COUNT = CMPA D\r
+#define PWM_TR_CNT_BU 0x00001000 // Trig if COUNT = CMPA U\r
+#define PWM_TR_CNT_BD 0x00002000 // Trig if COUNT = CMPA D\r
+\r
+//*****************************************************************************\r
+//\r
+// Defines for enabling, disabling, and clearing PWM interrupts.\r
+//\r
+//*****************************************************************************\r
+#define PWM_INT_GEN_0 0x00000001 // Generator 0 interrupt\r
+#define PWM_INT_GEN_1 0x00000002 // Generator 1 interrupt\r
+#define PWM_INT_GEN_2 0x00000004 // Generator 2 interrupt\r
+#define PWM_INT_FAULT 0x00010000 // Fault interrupt\r
+\r
+//*****************************************************************************\r
+//\r
+// Defines to identify the generators within a module.\r
+//\r
+//*****************************************************************************\r
+#define PWM_GEN_0 0x00000040 // Offset address of Gen0\r
+#define PWM_GEN_1 0x00000080 // Offset address of Gen1\r
+#define PWM_GEN_2 0x000000C0 // Offset address of Gen2\r
+\r
+#define PWM_GEN_0_BIT 0x00000001 // Bit-wise ID for Gen0\r
+#define PWM_GEN_1_BIT 0x00000002 // Bit-wise ID for Gen1\r
+#define PWM_GEN_2_BIT 0x00000004 // Bit-wise ID for Gen2\r
+\r
+//*****************************************************************************\r
+//\r
+// Defines to identify the outputs within a module.\r
+//\r
+//*****************************************************************************\r
+#define PWM_OUT_0 0x00000040 // Encoded offset address of PWM0\r
+#define PWM_OUT_1 0x00000041 // Encoded offset address of PWM1\r
+#define PWM_OUT_2 0x00000082 // Encoded offset address of PWM2\r
+#define PWM_OUT_3 0x00000083 // Encoded offset address of PWM3\r
+#define PWM_OUT_4 0x000000C4 // Encoded offset address of PWM4\r
+#define PWM_OUT_5 0x000000C5 // Encoded offset address of PWM5\r
+\r
+#define PWM_OUT_0_BIT 0x00000001 // Bit-wise ID for PWM0\r
+#define PWM_OUT_1_BIT 0x00000002 // Bit-wise ID for PWM1\r
+#define PWM_OUT_2_BIT 0x00000004 // Bit-wise ID for PWM2\r
+#define PWM_OUT_3_BIT 0x00000008 // Bit-wise ID for PWM3\r
+#define PWM_OUT_4_BIT 0x00000010 // Bit-wise ID for PWM4\r
+#define PWM_OUT_5_BIT 0x00000020 // Bit-wise ID for PWM5\r
+\r
+//*****************************************************************************\r
+//\r
+// API Function prototypes\r
+//\r
+//*****************************************************************************\r
+extern void PWMGenConfigure(unsigned long ulBase, unsigned long ulGen,\r
+ unsigned long ulConfig);\r
+extern void PWMGenPeriodSet(unsigned long ulBase, unsigned long ulGen,\r
+ unsigned long ulPeriod);\r
+extern unsigned long PWMGenPeriodGet(unsigned long ulBase,\r
+ unsigned long ulGen);\r
+extern void PWMGenEnable(unsigned long ulBase, unsigned long ulGen);\r
+extern void PWMGenDisable(unsigned long ulBase, unsigned long ulGen);\r
+extern void PWMPulseWidthSet(unsigned long ulBase, unsigned long ulPWMOut,\r
+ unsigned long ulWidth);\r
+extern unsigned long PWMPulseWidthGet(unsigned long ulBase,\r
+ unsigned long ulPWMOut);\r
+extern void PWMDeadBandEnable(unsigned long ulBase, unsigned long ulGen,\r
+ unsigned short usRise, unsigned short usFall);\r
+extern void PWMDeadBandDisable(unsigned long ulBase, unsigned long ulGen);\r
+extern void PWMSyncUpdate(unsigned long ulBase, unsigned long ulGenBits);\r
+extern void PWMSyncTimeBase(unsigned long ulBase, unsigned long ulGenBits);\r
+extern void PWMOutputState(unsigned long ulBase, unsigned long ulPWMOutBits,\r
+ tBoolean bEnable);\r
+extern void PWMOutputInvert(unsigned long ulBase, unsigned long ulPWMOutBits,\r
+ tBoolean bInvert);\r
+extern void PWMOutputFault(unsigned long ulBase, unsigned long ulPWMOutBits,\r
+ tBoolean bFaultKill);\r
+extern void PWMGenIntRegister(unsigned long ulBase, unsigned long ulGen,\r
+ void (*pfnIntHandler)(void));\r
+extern void PWMGenIntUnregister(unsigned long ulBase, unsigned long ulGen);\r
+extern void PWMFaultIntRegister(unsigned long ulBase,\r
+ void (*pfnIntHandler)(void));\r
+extern void PWMFaultIntUnregister(unsigned long ulBase);\r
+extern void PWMGenIntTrigEnable(unsigned long ulBase, unsigned long ulGen,\r
+ unsigned long ulIntTrig);\r
+extern void PWMGenIntTrigDisable(unsigned long ulBase, unsigned long ulGen,\r
+ unsigned long ulIntTrig);\r
+extern unsigned long PWMGenIntStatus(unsigned long ulBase, unsigned long ulGen,\r
+ tBoolean bMasked);\r
+extern void PWMGenIntClear(unsigned long ulBase, unsigned long ulGen,\r
+ unsigned long ulInts);\r
+extern void PWMIntEnable(unsigned long ulBase, unsigned long ulGenFault);\r
+extern void PWMIntDisable(unsigned long ulBase, unsigned long ulGenFault);\r
+extern void PWMFaultIntClear(unsigned long ulBase);\r
+extern unsigned long PWMIntStatus(unsigned long ulBase, tBoolean bMasked);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __PWM_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// qei.h - Prototypes for the Quadrature Encoder Driver.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __QEI_H__\r
+#define __QEI_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to QEIConfigure as the ulConfig paramater.\r
+//\r
+//*****************************************************************************\r
+#define QEI_CONFIG_CAPTURE_A 0x00000000 // Count on ChA edges only\r
+#define QEI_CONFIG_CAPTURE_A_B 0x00000008 // Count on ChA and ChB edges\r
+#define QEI_CONFIG_NO_RESET 0x00000000 // Do not reset on index pulse\r
+#define QEI_CONFIG_RESET_IDX 0x00000010 // Reset position on index pulse\r
+#define QEI_CONFIG_QUADRATURE 0x00000000 // ChA and ChB are quadrature\r
+#define QEI_CONFIG_CLOCK_DIR 0x00000004 // ChA and ChB are clock and dir\r
+#define QEI_CONFIG_NO_SWAP 0x00000000 // Do not swap ChA and ChB\r
+#define QEI_CONFIG_SWAP 0x00000002 // Swap ChA and ChB\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to QEIVelocityConfigure as the ulPreDiv parameter.\r
+//\r
+//*****************************************************************************\r
+#define QEI_VELDIV_1 0x00000000 // Predivide by 1\r
+#define QEI_VELDIV_2 0x00000040 // Predivide by 2\r
+#define QEI_VELDIV_4 0x00000080 // Predivide by 4\r
+#define QEI_VELDIV_8 0x000000C0 // Predivide by 8\r
+#define QEI_VELDIV_16 0x00000100 // Predivide by 16\r
+#define QEI_VELDIV_32 0x00000140 // Predivide by 32\r
+#define QEI_VELDIV_64 0x00000180 // Predivide by 64\r
+#define QEI_VELDIV_128 0x000001C0 // Predivide by 128\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to QEIEnableInts, QEIDisableInts, and QEIClearInts\r
+// as the ulIntFlags parameter, and returned by QEIGetIntStatus.\r
+//\r
+//*****************************************************************************\r
+#define QEI_INTERROR 0x00000008 // Phase error detected\r
+#define QEI_INTDIR 0x00000004 // Direction change\r
+#define QEI_INTTIMER 0x00000002 // Velocity timer expired\r
+#define QEI_INTINDEX 0x00000001 // Index pulse detected\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+extern void QEIEnable(unsigned long ulBase);\r
+extern void QEIDisable(unsigned long ulBase);\r
+extern void QEIConfigure(unsigned long ulBase, unsigned long ulConfig,\r
+ unsigned long ulMaxPosition);\r
+extern unsigned long QEIPositionGet(unsigned long ulBase);\r
+extern void QEIPositionSet(unsigned long ulBase, unsigned long ulPosition);\r
+extern long QEIDirectionGet(unsigned long ulBase);\r
+extern tBoolean QEIErrorGet(unsigned long ulBase);\r
+extern void QEIVelocityEnable(unsigned long ulBase);\r
+extern void QEIVelocityDisable(unsigned long ulBase);\r
+extern void QEIVelocityConfigure(unsigned long ulBase, unsigned long ulPreDiv,\r
+ unsigned long ulPeriod);\r
+extern unsigned long QEIVelocityGet(unsigned long ulBase);\r
+extern void QEIIntRegister(unsigned long ulBase, void (*pfnHandler)(void));\r
+extern void QEIIntUnregister(unsigned long ulBase);\r
+extern void QEIIntEnable(unsigned long ulBase, unsigned long ulIntFlags);\r
+extern void QEIIntDisable(unsigned long ulBase, unsigned long ulIntFlags);\r
+extern unsigned long QEIIntStatus(unsigned long ulBase, tBoolean bMasked);\r
+extern void QEIIntClear(unsigned long ulBase, unsigned long ulIntFlags);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __QEI_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// ssi.h - Prototypes for the Synchronous Serial Interface Driver.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __SSI_H__\r
+#define __SSI_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to SSIIntEnable, SSIIntDisable, and SSIIntClear\r
+// as the ulIntFlags parameter, and returned by SSIIntStatus.\r
+//\r
+//*****************************************************************************\r
+#define SSI_TXFF 0x00000008 // TX FIFO half empty or less\r
+#define SSI_RXFF 0x00000004 // RX FIFO half full or less\r
+#define SSI_RXTO 0x00000002 // RX timeout\r
+#define SSI_RXOR 0x00000001 // RX overrun\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to SSIConfig.\r
+//\r
+//*****************************************************************************\r
+#define SSI_FRF_MOTO_MODE_0 0x00000000 // Moto fmt, polarity 0, phase 0\r
+#define SSI_FRF_MOTO_MODE_1 0x00000002 // Moto fmt, polarity 0, phase 1\r
+#define SSI_FRF_MOTO_MODE_2 0x00000001 // Moto fmt, polarity 1, phase 0\r
+#define SSI_FRF_MOTO_MODE_3 0x00000003 // Moto fmt, polarity 1, phase 1\r
+#define SSI_FRF_TI 0x00000010 // TI frame format\r
+#define SSI_FRF_NMW 0x00000020 // National MicroWire frame format\r
+\r
+#define SSI_MODE_MASTER 0x00000000 // SSI master\r
+#define SSI_MODE_SLAVE 0x00000001 // SSI slave\r
+#define SSI_MODE_SLAVE_OD 0x00000002 // SSI slave with output disabled\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+extern void SSIConfig(unsigned long ulBase, unsigned long ulProtocol,\r
+ unsigned long ulMode, unsigned long ulBitRate,\r
+ unsigned long ulDataWidth);\r
+extern void SSIDataGet(unsigned long ulBase, unsigned long *pulData);\r
+extern long SSIDataNonBlockingGet(unsigned long ulBase,\r
+ unsigned long *pulData);\r
+extern void SSIDataPut(unsigned long ulBase, unsigned long ulData);\r
+extern long SSIDataNonBlockingPut(unsigned long ulBase, unsigned long ulData);\r
+extern void SSIDisable(unsigned long ulBase);\r
+extern void SSIEnable(unsigned long ulBase);\r
+extern void SSIIntClear(unsigned long ulBase, unsigned long ulIntFlags);\r
+extern void SSIIntDisable(unsigned long ulBase, unsigned long ulIntFlags);\r
+extern void SSIIntEnable(unsigned long ulBase, unsigned long ulIntFlags);\r
+extern void SSIIntRegister(unsigned long ulBase, void(*pfnHandler)(void));\r
+extern unsigned long SSIIntStatus(unsigned long ulBase, tBoolean bMasked);\r
+extern void SSIIntUnregister(unsigned long ulBase);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __SSI_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// sysctl.h - Prototypes for the system control driver.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __SYSCTL_H__\r
+#define __SYSCTL_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the\r
+// SysCtlPeripheralPresent(), SysCtlPeripheralEnable(),\r
+// SysCtlPeripheralDisable(), and SysCtlPeripheralReset() APIs as the\r
+// ulPeripheral parameter. The peripherals in the fourth group (upper nibble\r
+// is 3) can only be used with the SysCtlPeripheralPresent() API.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_PERIPH_PWM 0x00100010 // PWM\r
+#define SYSCTL_PERIPH_ADC 0x00100001 // ADC\r
+#define SYSCTL_PERIPH_HIBERNATE 0x00000040 // Hibernation module\r
+#define SYSCTL_PERIPH_WDOG 0x00000008 // Watchdog\r
+#define SYSCTL_PERIPH_CAN0 0x00100100 // CAN 0\r
+#define SYSCTL_PERIPH_CAN1 0x00100200 // CAN 1\r
+#define SYSCTL_PERIPH_UART0 0x10000001 // UART 0\r
+#define SYSCTL_PERIPH_UART1 0x10000002 // UART 1\r
+#define SYSCTL_PERIPH_UART2 0x10000004 // UART 2\r
+#define SYSCTL_PERIPH_SSI 0x10000010 // SSI\r
+#define SYSCTL_PERIPH_SSI0 0x10000010 // SSI 0\r
+#define SYSCTL_PERIPH_SSI1 0x10000020 // SSI 1\r
+#define SYSCTL_PERIPH_QEI 0x10000100 // QEI\r
+#define SYSCTL_PERIPH_QEI0 0x10000100 // QEI 0\r
+#define SYSCTL_PERIPH_QEI1 0x10000200 // QEI 1\r
+#define SYSCTL_PERIPH_I2C 0x10001000 // I2C\r
+#define SYSCTL_PERIPH_I2C0 0x10001000 // I2C 0\r
+#define SYSCTL_PERIPH_I2C1 0x10004000 // I2C 1\r
+#define SYSCTL_PERIPH_TIMER0 0x10100001 // Timer 0\r
+#define SYSCTL_PERIPH_TIMER1 0x10100002 // Timer 1\r
+#define SYSCTL_PERIPH_TIMER2 0x10100004 // Timer 2\r
+#define SYSCTL_PERIPH_TIMER3 0x10100008 // Timer 3\r
+#define SYSCTL_PERIPH_COMP0 0x10100100 // Analog comparator 0\r
+#define SYSCTL_PERIPH_COMP1 0x10100200 // Analog comparator 1\r
+#define SYSCTL_PERIPH_COMP2 0x10100400 // Analog comparator 2\r
+#define SYSCTL_PERIPH_GPIOA 0x20000001 // GPIO A\r
+#define SYSCTL_PERIPH_GPIOB 0x20000002 // GPIO B\r
+#define SYSCTL_PERIPH_GPIOC 0x20000004 // GPIO C\r
+#define SYSCTL_PERIPH_GPIOD 0x20000008 // GPIO D\r
+#define SYSCTL_PERIPH_GPIOE 0x20000010 // GPIO E\r
+#define SYSCTL_PERIPH_GPIOF 0x20000020 // GPIO F\r
+#define SYSCTL_PERIPH_GPIOG 0x20000040 // GPIO G\r
+#define SYSCTL_PERIPH_GPIOH 0x20000080 // GPIO H\r
+#define SYSCTL_PERIPH_ETH 0x20105000 // ETH\r
+#define SYSCTL_PERIPH_MPU 0x30000080 // Cortex M3 MPU\r
+#define SYSCTL_PERIPH_TEMP 0x30000020 // Temperature sensor\r
+#define SYSCTL_PERIPH_PLL 0x30000010 // PLL\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the SysCtlPinPresent() API\r
+// as the ulPin parameter.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_PIN_PWM0 0x00000001 // PWM0 pin\r
+#define SYSCTL_PIN_PWM1 0x00000002 // PWM1 pin\r
+#define SYSCTL_PIN_PWM2 0x00000004 // PWM2 pin\r
+#define SYSCTL_PIN_PWM3 0x00000008 // PWM3 pin\r
+#define SYSCTL_PIN_PWM4 0x00000010 // PWM4 pin\r
+#define SYSCTL_PIN_PWM5 0x00000020 // PWM5 pin\r
+#define SYSCTL_PIN_C0MINUS 0x00000040 // C0- pin\r
+#define SYSCTL_PIN_C0PLUS 0x00000080 // C0+ pin\r
+#define SYSCTL_PIN_C0O 0x00000100 // C0o pin\r
+#define SYSCTL_PIN_C1MINUS 0x00000200 // C1- pin\r
+#define SYSCTL_PIN_C1PLUS 0x00000400 // C1+ pin\r
+#define SYSCTL_PIN_C1O 0x00000800 // C1o pin\r
+#define SYSCTL_PIN_C2MINUS 0x00001000 // C2- pin\r
+#define SYSCTL_PIN_C2PLUS 0x00002000 // C2+ pin\r
+#define SYSCTL_PIN_C2O 0x00004000 // C2o pin\r
+#define SYSCTL_PIN_MC_FAULT0 0x00008000 // MC0 Fault pin\r
+#define SYSCTL_PIN_ADC0 0x00010000 // ADC0 pin\r
+#define SYSCTL_PIN_ADC1 0x00020000 // ADC1 pin\r
+#define SYSCTL_PIN_ADC2 0x00040000 // ADC2 pin\r
+#define SYSCTL_PIN_ADC3 0x00080000 // ADC3 pin\r
+#define SYSCTL_PIN_ADC4 0x00100000 // ADC4 pin\r
+#define SYSCTL_PIN_ADC5 0x00200000 // ADC5 pin\r
+#define SYSCTL_PIN_ADC6 0x00400000 // ADC6 pin\r
+#define SYSCTL_PIN_ADC7 0x00800000 // ADC7 pin\r
+#define SYSCTL_PIN_CCP0 0x01000000 // CCP0 pin\r
+#define SYSCTL_PIN_CCP1 0x02000000 // CCP1 pin\r
+#define SYSCTL_PIN_CCP2 0x04000000 // CCP2 pin\r
+#define SYSCTL_PIN_CCP3 0x08000000 // CCP3 pin\r
+#define SYSCTL_PIN_CCP4 0x10000000 // CCP4 pin\r
+#define SYSCTL_PIN_CCP5 0x20000000 // CCP5 pin\r
+#define SYSCTL_PIN_32KHZ 0x80000000 // 32kHz pin\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the SysCtlLDOSet() API as\r
+// the ulVoltage value, or returned by the SysCtlLDOGet() API.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_LDO_2_25V 0x00000005 // LDO output of 2.25V\r
+#define SYSCTL_LDO_2_30V 0x00000004 // LDO output of 2.30V\r
+#define SYSCTL_LDO_2_35V 0x00000003 // LDO output of 2.35V\r
+#define SYSCTL_LDO_2_40V 0x00000002 // LDO output of 2.40V\r
+#define SYSCTL_LDO_2_45V 0x00000001 // LDO output of 2.45V\r
+#define SYSCTL_LDO_2_50V 0x00000000 // LDO output of 2.50V\r
+#define SYSCTL_LDO_2_55V 0x0000001f // LDO output of 2.55V\r
+#define SYSCTL_LDO_2_60V 0x0000001e // LDO output of 2.60V\r
+#define SYSCTL_LDO_2_65V 0x0000001d // LDO output of 2.65V\r
+#define SYSCTL_LDO_2_70V 0x0000001c // LDO output of 2.70V\r
+#define SYSCTL_LDO_2_75V 0x0000001b // LDO output of 2.75V\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the SysCtlLDOConfigSet() API.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_LDOCFG_ARST 0x00000001 // Allow LDO failure to reset\r
+#define SYSCTL_LDOCFG_NORST 0x00000000 // Do not reset on LDO failure\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the SysCtlIntEnable(),\r
+// SysCtlIntDisable(), and SysCtlIntClear() APIs, or returned in the bit mask\r
+// by the SysCtlIntStatus() API.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_INT_PLL_LOCK 0x00000040 // PLL lock interrupt\r
+#define SYSCTL_INT_CUR_LIMIT 0x00000020 // Current limit interrupt\r
+#define SYSCTL_INT_IOSC_FAIL 0x00000010 // Internal oscillator failure int\r
+#define SYSCTL_INT_MOSC_FAIL 0x00000008 // Main oscillator failure int\r
+#define SYSCTL_INT_POR 0x00000004 // Power on reset interrupt\r
+#define SYSCTL_INT_BOR 0x00000002 // Brown out interrupt\r
+#define SYSCTL_INT_PLL_FAIL 0x00000001 // PLL failure interrupt\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the SysCtlResetCauseClear()\r
+// API or returned by the SysCtlResetCauseGet() API.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_CAUSE_LDO 0x00000020 // LDO power not OK reset\r
+#define SYSCTL_CAUSE_SW 0x00000010 // Software reset\r
+#define SYSCTL_CAUSE_WDOG 0x00000008 // Watchdog reset\r
+#define SYSCTL_CAUSE_BOR 0x00000004 // Brown-out reset\r
+#define SYSCTL_CAUSE_POR 0x00000002 // Power on reset\r
+#define SYSCTL_CAUSE_EXT 0x00000001 // External reset\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the SysCtlBrownOutConfigSet()\r
+// API as the ulConfig parameter.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_BOR_RESET 0x00000002 // Reset instead of interrupting\r
+#define SYSCTL_BOR_RESAMPLE 0x00000001 // Resample BOR before asserting\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the SysCtlPWMClockSet() API\r
+// as the ulConfig parameter, and can be returned by the SysCtlPWMClockGet()\r
+// API.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_PWMDIV_1 0x00000000 // PWM clock is processor clock /1\r
+#define SYSCTL_PWMDIV_2 0x00100000 // PWM clock is processor clock /2\r
+#define SYSCTL_PWMDIV_4 0x00120000 // PWM clock is processor clock /4\r
+#define SYSCTL_PWMDIV_8 0x00140000 // PWM clock is processor clock /8\r
+#define SYSCTL_PWMDIV_16 0x00160000 // PWM clock is processor clock /16\r
+#define SYSCTL_PWMDIV_32 0x00180000 // PWM clock is processor clock /32\r
+#define SYSCTL_PWMDIV_64 0x001A0000 // PWM clock is processor clock /64\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the SysCtlADCSpeedSet() API\r
+// as the ulSpeed parameter, and can be returned by the SyCtlADCSpeedGet()\r
+// API.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_ADCSPEED_1MSPS 0x00000300 // 1,000,000 samples per second\r
+#define SYSCTL_ADCSPEED_500KSPS 0x00000200 // 500,000 samples per second\r
+#define SYSCTL_ADCSPEED_250KSPS 0x00000100 // 250,000 samples per second\r
+#define SYSCTL_ADCSPEED_125KSPS 0x00000000 // 125,000 samples per second\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the SysCtlClockSet() API as\r
+// the ulConfig parameter.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_SYSDIV_1 0x07800000 // Processor clock is osc/pll /1\r
+#define SYSCTL_SYSDIV_2 0x00C00000 // Processor clock is osc/pll /2\r
+#define SYSCTL_SYSDIV_3 0x01400000 // Processor clock is osc/pll /3\r
+#define SYSCTL_SYSDIV_4 0x01C00000 // Processor clock is osc/pll /4\r
+#define SYSCTL_SYSDIV_5 0x02400000 // Processor clock is osc/pll /5\r
+#define SYSCTL_SYSDIV_6 0x02C00000 // Processor clock is osc/pll /6\r
+#define SYSCTL_SYSDIV_7 0x03400000 // Processor clock is osc/pll /7\r
+#define SYSCTL_SYSDIV_8 0x03C00000 // Processor clock is osc/pll /8\r
+#define SYSCTL_SYSDIV_9 0x04400000 // Processor clock is osc/pll /9\r
+#define SYSCTL_SYSDIV_10 0x04C00000 // Processor clock is osc/pll /10\r
+#define SYSCTL_SYSDIV_11 0x05400000 // Processor clock is osc/pll /11\r
+#define SYSCTL_SYSDIV_12 0x05C00000 // Processor clock is osc/pll /12\r
+#define SYSCTL_SYSDIV_13 0x06400000 // Processor clock is osc/pll /13\r
+#define SYSCTL_SYSDIV_14 0x06C00000 // Processor clock is osc/pll /14\r
+#define SYSCTL_SYSDIV_15 0x07400000 // Processor clock is osc/pll /15\r
+#define SYSCTL_SYSDIV_16 0x07C00000 // Processor clock is osc/pll /16\r
+#define SYSCTL_USE_PLL 0x00000000 // System clock is the PLL clock\r
+#define SYSCTL_USE_OSC 0x00003800 // System clock is the osc clock\r
+#define SYSCTL_XTAL_3_57MHZ 0x00000100 // External crystal is 3.579545MHz\r
+#define SYSCTL_XTAL_3_68MHZ 0x00000140 // External crystal is 3.6864MHz\r
+#define SYSCTL_XTAL_4MHZ 0x00000180 // External crystal is 4MHz\r
+#define SYSCTL_XTAL_4_09MHZ 0x000001C0 // External crystal is 4.096MHz\r
+#define SYSCTL_XTAL_4_91MHZ 0x00000200 // External crystal is 4.9152MHz\r
+#define SYSCTL_XTAL_5MHZ 0x00000240 // External crystal is 5MHz\r
+#define SYSCTL_XTAL_5_12MHZ 0x00000280 // External crystal is 5.12MHz\r
+#define SYSCTL_XTAL_6MHZ 0x000002C0 // External crystal is 6MHz\r
+#define SYSCTL_XTAL_6_14MHZ 0x00000300 // External crystal is 6.144MHz\r
+#define SYSCTL_XTAL_7_37MHZ 0x00000340 // External crystal is 7.3728MHz\r
+#define SYSCTL_XTAL_8MHZ 0x00000380 // External crystal is 8MHz\r
+#define SYSCTL_XTAL_8_19MHZ 0x000003C0 // External crystal is 8.192MHz\r
+#define SYSCTL_OSC_MAIN 0x00000000 // Oscillator source is main osc\r
+#define SYSCTL_OSC_INT 0x00000010 // Oscillator source is int. osc\r
+#define SYSCTL_OSC_INT4 0x00000020 // Oscillator source is int. osc /4\r
+#define SYSCTL_INT_OSC_DIS 0x00000002 // Disable internal oscillator\r
+#define SYSCTL_MAIN_OSC_DIS 0x00000001 // Disable main oscillator\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+extern unsigned long SysCtlSRAMSizeGet(void);\r
+extern unsigned long SysCtlFlashSizeGet(void);\r
+extern tBoolean SysCtlPinPresent(unsigned long ulPin);\r
+extern tBoolean SysCtlPeripheralPresent(unsigned long ulPeripheral);\r
+extern void SysCtlPeripheralReset(unsigned long ulPeripheral);\r
+extern void SysCtlPeripheralEnable(unsigned long ulPeripheral);\r
+extern void SysCtlPeripheralDisable(unsigned long ulPeripheral);\r
+extern void SysCtlPeripheralSleepEnable(unsigned long ulPeripheral);\r
+extern void SysCtlPeripheralSleepDisable(unsigned long ulPeripheral);\r
+extern void SysCtlPeripheralDeepSleepEnable(unsigned long ulPeripheral);\r
+extern void SysCtlPeripheralDeepSleepDisable(unsigned long ulPeripheral);\r
+extern void SysCtlPeripheralClockGating(tBoolean bEnable);\r
+extern void SysCtlIntRegister(void (*pfnHandler)(void));\r
+extern void SysCtlIntUnregister(void);\r
+extern void SysCtlIntEnable(unsigned long ulInts);\r
+extern void SysCtlIntDisable(unsigned long ulInts);\r
+extern void SysCtlIntClear(unsigned long ulInts);\r
+extern unsigned long SysCtlIntStatus(tBoolean bMasked);\r
+extern void SysCtlLDOSet(unsigned long ulVoltage);\r
+extern unsigned long SysCtlLDOGet(void);\r
+extern void SysCtlLDOConfigSet(unsigned long ulConfig);\r
+extern void SysCtlReset(void);\r
+extern void SysCtlSleep(void);\r
+extern void SysCtlDeepSleep(void);\r
+extern unsigned long SysCtlResetCauseGet(void);\r
+extern void SysCtlResetCauseClear(unsigned long ulCauses);\r
+extern void SysCtlBrownOutConfigSet(unsigned long ulConfig,\r
+ unsigned long ulDelay);\r
+extern void SysCtlClockSet(unsigned long ulConfig);\r
+extern unsigned long SysCtlClockGet(void);\r
+extern void SysCtlPWMClockSet(unsigned long ulConfig);\r
+extern unsigned long SysCtlPWMClockGet(void);\r
+extern void SysCtlADCSpeedSet(unsigned long ulSpeed);\r
+extern unsigned long SysCtlADCSpeedGet(void);\r
+extern void SysCtlIOSCVerificationSet(tBoolean bEnable);\r
+extern void SysCtlMOSCVerificationSet(tBoolean bEnable);\r
+extern void SysCtlPLLVerificationSet(tBoolean bEnable);\r
+extern void SysCtlClkVerificationClear(void);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __SYSCTL_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// systick.h - Prototypes for the SysTick driver.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __SYSTICK_H__\r
+#define __SYSTICK_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+extern void SysTickEnable(void);\r
+extern void SysTickDisable(void);\r
+extern void SysTickIntRegister(void (*pfnHandler)(void));\r
+extern void SysTickIntUnregister(void);\r
+extern void SysTickIntEnable(void);\r
+extern void SysTickIntDisable(void);\r
+extern void SysTickPeriodSet(unsigned long ulPeriod);\r
+extern unsigned long SysTickPeriodGet(void);\r
+extern unsigned long SysTickValueGet(void);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __SYSTICK_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// uart.h - Defines and Macros for the UART.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __UART_H__\r
+#define __UART_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to UARTIntEnable, UARTIntDisable, and UARTIntClear\r
+// as the ulIntFlags parameter, and returned from UARTIntStatus.\r
+//\r
+//*****************************************************************************\r
+#define UART_INT_OE 0x400 // Overrun Error Interrupt Mask\r
+#define UART_INT_BE 0x200 // Break Error Interrupt Mask\r
+#define UART_INT_PE 0x100 // Parity Error Interrupt Mask\r
+#define UART_INT_FE 0x080 // Framing Error Interrupt Mask\r
+#define UART_INT_RT 0x040 // Receive Timeout Interrupt Mask\r
+#define UART_INT_TX 0x020 // Transmit Interrupt Mask\r
+#define UART_INT_RX 0x010 // Receive Interrupt Mask\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to UARTConfigSet as the ulConfig parameter and\r
+// returned by UARTConfigGet in the pulConfig parameter. Additionally, the\r
+// UART_CONFIG_PAR_* subset can be passed to UARTParityModeSet as the ulParity\r
+// parameter, and are returned by UARTParityModeGet.\r
+//\r
+//*****************************************************************************\r
+#define UART_CONFIG_WLEN_8 0x00000060 // 8 bit data\r
+#define UART_CONFIG_WLEN_7 0x00000040 // 7 bit data\r
+#define UART_CONFIG_WLEN_6 0x00000020 // 6 bit data\r
+#define UART_CONFIG_WLEN_5 0x00000000 // 5 bit data\r
+#define UART_CONFIG_STOP_ONE 0x00000000 // One stop bit\r
+#define UART_CONFIG_STOP_TWO 0x00000008 // Two stop bits\r
+#define UART_CONFIG_PAR_NONE 0x00000000 // No parity\r
+#define UART_CONFIG_PAR_EVEN 0x00000006 // Even parity\r
+#define UART_CONFIG_PAR_ODD 0x00000002 // Odd parity\r
+#define UART_CONFIG_PAR_ONE 0x00000086 // Parity bit is one\r
+#define UART_CONFIG_PAR_ZERO 0x00000082 // Parity bit is zero\r
+\r
+//*****************************************************************************\r
+//\r
+// API Function prototypes\r
+//\r
+//*****************************************************************************\r
+extern void UARTParityModeSet(unsigned long ulBase, unsigned long ulParity);\r
+extern unsigned long UARTParityModeGet(unsigned long ulBase);\r
+extern void UARTConfigSet(unsigned long ulBase, unsigned long ulBaud,\r
+ unsigned long ulConfig);\r
+extern void UARTConfigGet(unsigned long ulBase, unsigned long *pulBaud,\r
+ unsigned long *pulConfig);\r
+extern void UARTEnable(unsigned long ulBase);\r
+extern void UARTDisable(unsigned long ulBase);\r
+extern void UARTEnableSIR(unsigned long ulBase, tBoolean bLowPower);\r
+extern void UARTDisableSIR(unsigned long ulBase);\r
+extern tBoolean UARTCharsAvail(unsigned long ulBase);\r
+extern tBoolean UARTSpaceAvail(unsigned long ulBase);\r
+extern long UARTCharNonBlockingGet(unsigned long ulBase);\r
+extern long UARTCharGet(unsigned long ulBase);\r
+extern tBoolean UARTCharNonBlockingPut(unsigned long ulBase,\r
+ unsigned char ucData);\r
+extern void UARTCharPut(unsigned long ulBase, unsigned char ucData);\r
+extern void UARTBreakCtl(unsigned long ulBase, tBoolean bBreakState);\r
+extern void UARTIntRegister(unsigned long ulBase, void(*pfnHandler)(void));\r
+extern void UARTIntUnregister(unsigned long ulBase);\r
+extern void UARTIntEnable(unsigned long ulBase, unsigned long ulIntFlags);\r
+extern void UARTIntDisable(unsigned long ulBase, unsigned long ulIntFlags);\r
+extern unsigned long UARTIntStatus(unsigned long ulBase, tBoolean bMasked);\r
+extern void UARTIntClear(unsigned long ulBase, unsigned long ulIntFlags);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __UART_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// watchdog.h - Prototypes for the Watchdog Timer API\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __WATCHDOG_H__\r
+#define __WATCHDOG_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+extern tBoolean WatchdogRunning(unsigned long ulBase);\r
+extern void WatchdogEnable(unsigned long ulBase);\r
+extern void WatchdogResetEnable(unsigned long ulBase);\r
+extern void WatchdogResetDisable(unsigned long ulBase);\r
+extern void WatchdogLock(unsigned long ulBase);\r
+extern void WatchdogUnlock(unsigned long ulBase);\r
+extern tBoolean WatchdogLockState(unsigned long ulBase);\r
+extern void WatchdogReloadSet(unsigned long ulBase, unsigned long ulLoadVal);\r
+extern unsigned long WatchdogReloadGet(unsigned long ulBase);\r
+extern unsigned long WatchdogValueGet(unsigned long ulBase);\r
+extern void WatchdogIntRegister(unsigned long ulBase, void(*pfnHandler)(void));\r
+extern void WatchdogIntUnregister(unsigned long ulBase);\r
+extern void WatchdogIntEnable(unsigned long ulBase);\r
+extern unsigned long WatchdogIntStatus(unsigned long ulBase, tBoolean bMasked);\r
+extern void WatchdogIntClear(unsigned long ulBase);\r
+extern void WatchdogStallDisable(unsigned long ulBase);\r
+extern void WatchdogStallDisable(unsigned long ulBase);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __WATCHDOG_H__\r
--- /dev/null
+/*\r
+ FreeRTOS.org V4.3.0 - Copyright (C) 2003-2007 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS.org distribution.\r
+\r
+ FreeRTOS.org is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS.org is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS.org; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS.org, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section\r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license\r
+ and contact details. Please ensure to read the configuration and relevant\r
+ port sections of the online documentation.\r
+\r
+ Also see http://www.SafeRTOS.com for an IEC 61508 compliant version along\r
+ with commercial development and support options.\r
+ ***************************************************************************\r
+*/\r
+\r
+/*-----------------------------------------------------------\r
+ * Simple parallel port IO routines.\r
+ *-----------------------------------------------------------*/\r
+\r
+/*\r
+*/\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/* Demo includes. */\r
+#include "partest.h"\r
+\r
+/* Library includes. */\r
+#include "hw_types.h"\r
+#include "gpio.h"\r
+#include "hw_memmap.h"\r
+\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestInitialise( void )\r
+{\r
+ GPIODirModeSet( GPIO_PORTF_BASE, GPIO_PIN_0, GPIO_DIR_MODE_OUT );\r
+ GPIOPadConfigSet( GPIO_PORTF_BASE, GPIO_PIN_0, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD );\r
+ GPIOPinWrite( GPIO_PORTF_BASE, GPIO_PIN_0, 0 );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue )\r
+{\r
+ /* There is only one LED. */\r
+ ( void ) uxLED;\r
+ \r
+ GPIOPinWrite( GPIO_PORTF_BASE, GPIO_PIN_0, xValue );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+unsigned portBASE_TYPE uxParTestGetLED( unsigned portBASE_TYPE uxLED )\r
+{\r
+ /* There is only one LED. */\r
+ ( void ) uxLED;\r
+\r
+ return GPIOPinRead( GPIO_PORTF_BASE, GPIO_PIN_0 ); \r
+}\r
+\r
+\r
--- /dev/null
+### uVision2 Project, (C) Keil Software\r
+### Do not modify !\r
+\r
+ cExt (*.c)\r
+ aExt (*.s*; *.src; *.a*)\r
+ oExt (*.obj)\r
+ lExt (*.lib)\r
+ tExt (*.txt; *.h; *.inc)\r
+ pExt (*.plm)\r
+ CppX (*.cpp)\r
+ DaveTm { 0,0,0,0,0,0,0,0 }\r
+\r
+Target (FreeRTOS_Demo), 0x0004 // Tools: 'ARM-ADS'\r
+GRPOPT 1,(Demo_Source),0,0,0\r
+GRPOPT 2,(Libraries),0,0,0\r
+GRPOPT 3,(RTOS_Source),0,0,0\r
+\r
+OPTFFF 1,1,1,0,0,0,0,0,<..\Common\Minimal\BlockQ.c><BlockQ.c> \r
+OPTFFF 1,2,1,0,0,0,0,0,<..\Common\Minimal\blocktim.c><blocktim.c> \r
+OPTFFF 1,3,1,0,0,0,0,0,<..\Common\Minimal\death.c><death.c> \r
+OPTFFF 1,4,1,0,0,0,0,0,<..\Common\Minimal\integer.c><integer.c> \r
+OPTFFF 1,5,1,0,0,0,0,0,<.\main.c><main.c> \r
+OPTFFF 1,6,1,0,0,0,0,0,<.\ParTest\ParTest.c><ParTest.c> \r
+OPTFFF 1,7,1,0,0,0,0,0,<..\Common\Minimal\PollQ.c><PollQ.c> \r
+OPTFFF 1,8,1,0,0,0,0,0,<..\Common\Minimal\semtest.c><semtest.c> \r
+OPTFFF 1,9,2,570425344,0,0,0,0,<.\startup_rvmdk.S><startup_rvmdk.S> \r
+OPTFFF 1,10,1,0,0,0,0,0,<.\timertest.c><timertest.c> \r
+OPTFFF 1,11,5,0,0,0,0,0,<.\FreeRTOSConfig.h><FreeRTOSConfig.h> \r
+OPTFFF 2,12,4,0,0,0,0,0,<.\LuminaryDrivers\driverlib.lib><driverlib.lib> \r
+OPTFFF 2,13,1,0,0,0,0,0,<.\LuminaryDrivers\osram128x64x4.c><osram128x64x4.c> \r
+OPTFFF 3,14,1,0,0,0,0,0,<..\..\Source\tasks.c><tasks.c> \r
+OPTFFF 3,15,1,0,0,0,0,0,<..\..\Source\list.c><list.c> \r
+OPTFFF 3,16,1,0,0,0,0,0,<..\..\Source\queue.c><queue.c> \r
+OPTFFF 3,17,1,0,0,0,0,0,<..\..\Source\portable\RVDS\ARM_CM3\port.c><port.c> \r
+OPTFFF 3,18,1,0,0,0,0,0,<..\..\Source\portable\MemMang\heap_2.c><heap_2.c> \r
+\r
+\r
+TARGOPT 1, (FreeRTOS_Demo)\r
+ ADSCLK=6000000\r
+ OPTTT 1,1,1,0\r
+ OPTHX 1,65535,0,0,0\r
+ OPTLX 79,66,8,<.\rvmdk\>\r
+ OPTOX 16\r
+ OPTLT 1,1,1,0,1,1,0,1,0,0,0,0\r
+ OPTXL 1,1,1,1,1,1,1,0,0\r
+ OPTFL 1,0,1\r
+ OPTAX 255\r
+ OPTBL 0,(Data Sheet)<DATASHTS\Luminary\LM3S2965.PDF>\r
+ OPTDL (SARMCM3.DLL)()(DLM.DLL)(-pLM3S2965)(SARMCM3.DLL)()(TLM.DLL)(-pLM3S2965)\r
+ OPTDBG 48126,3,()()()()()()()()()() (BIN\lmidk-agdi.dll)()()()\r
+ OPTDF 0x0\r
+ OPTLE <>\r
+ OPTLC <>\r
+EndOpt\r
+\r
--- /dev/null
+### uVision2 Project, (C) Keil Software\r
+### Do not modify !\r
+\r
+Target (FreeRTOS_Demo), 0x0004 // Tools: 'ARM-ADS'\r
+\r
+Group (Demo_Source)\r
+Group (Libraries)\r
+Group (RTOS_Source)\r
+\r
+File 1,1,<..\Common\Minimal\BlockQ.c><BlockQ.c> 0x46520544 \r
+File 1,1,<..\Common\Minimal\blocktim.c><blocktim.c> 0x46520544 \r
+File 1,1,<..\Common\Minimal\death.c><death.c> 0x46520544 \r
+File 1,1,<..\Common\Minimal\integer.c><integer.c> 0x46520544 \r
+File 1,1,<.\main.c><main.c> 0x4664B508 \r
+File 1,1,<.\ParTest\ParTest.c><ParTest.c> 0x46520580 \r
+File 1,1,<..\Common\Minimal\PollQ.c><PollQ.c> 0x46520544 \r
+File 1,1,<..\Common\Minimal\semtest.c><semtest.c> 0x46520544 \r
+File 1,2,<.\startup_rvmdk.S><startup_rvmdk.S> 0x4664BAF8 \r
+File 1,1,<.\timertest.c><timertest.c> 0x46520544 \r
+File 1,5,<.\FreeRTOSConfig.h><FreeRTOSConfig.h> 0x46638356 \r
+File 2,4,<.\LuminaryDrivers\driverlib.lib><driverlib.lib> 0x46647F6C \r
+File 2,1,<.\LuminaryDrivers\osram128x64x4.c><osram128x64x4.c> 0x46649D66 \r
+File 3,1,<..\..\Source\tasks.c><tasks.c> 0x46520544 \r
+File 3,1,<..\..\Source\list.c><list.c> 0x46520544 \r
+File 3,1,<..\..\Source\queue.c><queue.c> 0x46520544 \r
+File 3,1,<..\..\Source\portable\RVDS\ARM_CM3\port.c><port.c> 0x44FB69B0 \r
+File 3,1,<..\..\Source\portable\MemMang\heap_2.c><heap_2.c> 0x46520580 \r
+\r
+\r
+Options 1,0,0 // Target 'FreeRTOS_Demo'\r
+ Device (LM3S2965)\r
+ Vendor (Luminary Micro)\r
+ Cpu (IRAM(0x20000000-0x2000FFFF) IROM(0-0x3FFFF) CLOCK(6000000) CPUTYPE("Cortex-M3"))\r
+ FlashUt ()\r
+ StupF ("STARTUP\Luminary\Startup.s" ("Luminary Startup Code"))\r
+ FlashDR (UL2CM3(-UU0101L5E -O14 -S0 -C0 -N00("ARM Cortex-M3") -D00(1BA00477) -L00(4) -FO7 -FD20000000 -FC800 -FN1 -FF0LM3S_256 -FS00 -FL040000))\r
+ DevID (4322)\r
+ Rgf (LM3Sxxxx.H)\r
+ Mem ()\r
+ C ()\r
+ A ()\r
+ RL ()\r
+ OH ()\r
+ DBC_IFX ()\r
+ DBC_CMS ()\r
+ DBC_AMS ()\r
+ DBC_LMS ()\r
+ UseEnv=0\r
+ EnvBin ()\r
+ EnvInc ()\r
+ EnvLib ()\r
+ EnvReg (ÿLuminary\)\r
+ OrgReg (ÿLuminary\)\r
+ TgStat=16\r
+ OutDir (.\rvmdk\)\r
+ OutName (RTOSDemo)\r
+ GenApp=1\r
+ GenLib=0\r
+ GenHex=0\r
+ Debug=1\r
+ Browse=1\r
+ LstDir (.\rvmdk\)\r
+ HexSel=1\r
+ MG32K=0\r
+ TGMORE=0\r
+ RunUsr 0 1 <fromelf --bin --output .\rvmdk\RTOSDemo.bin .\rvmdk\RTOSDemo.axf>\r
+ RunUsr 1 0 <>\r
+ BrunUsr 0 0 <>\r
+ BrunUsr 1 0 <>\r
+ CrunUsr 0 0 <>\r
+ CrunUsr 1 0 <>\r
+ SVCSID <>\r
+ GLFLAGS=1790\r
+ ADSFLGA { 16,3,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }\r
+ ACPUTYP ("Cortex-M3")\r
+ ADSTFLGA { 0,12,0,2,99,0,0,66,0,0,0,0,0,0,0,0,0,0,0,0 }\r
+ OCMADSOCM { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }\r
+ OCMADSIRAM { 0,0,0,0,32,0,0,1,0 }\r
+ OCMADSIROM { 1,0,0,0,0,0,0,4,0 }\r
+ OCMADSXRAM { 0,0,0,0,0,0,0,0,0 }\r
+ OCR_RVCT { 1,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,4,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,32,0,0,1,0,0,0,0,0,0,0,0,0,0 }\r
+ RV_STAVEC ()\r
+ ADSCCFLG { 9,32,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }\r
+ ADSCMISC ()\r
+ ADSCDEFN (RVDS_ARMCM3_LM3S102)\r
+ ADSCUDEF ()\r
+ ADSCINCD (.;.\LuminaryDrivers;..\..\Source\portable\RVDS\ARM_CM3;..\..\Source\include;..\Common\include)\r
+ ADSASFLG { 1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }\r
+ ADSAMISC ()\r
+ ADSADEFN ()\r
+ ADSAUDEF ()\r
+ ADSAINCD ()\r
+ PropFld { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }\r
+ IncBld=1\r
+ AlwaysBuild=0\r
+ GenAsm=0\r
+ AsmAsm=0\r
+ PublicsOnly=0\r
+ StopCode=3\r
+ CustArgs ()\r
+ LibMods ()\r
+ ADSLDFG { 17,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }\r
+ ADSLDTA (0x00000000)\r
+ ADSLDDA (0x20000000)\r
+ ADSLDSC ()\r
+ ADSLDIB ()\r
+ ADSLDIC ()\r
+ ADSLDMC (--entry Reset_Handler)\r
+ ADSLDIF ()\r
+ ADSLDDW ()\r
+ OPTDL (SARMCM3.DLL)()(DLM.DLL)(-pLM3S2965)(SARMCM3.DLL)()(TLM.DLL)(-pLM3S2965)\r
+ OPTDBG 48126,3,()()()()()()()()()() (BIN\lmidk-agdi.dll)()()()\r
+ FLASH1 { 1,0,0,0,1,0,0,0,3,0,0,0,0,0,0,0,0,0,0,0 }\r
+ FLASH2 (BIN\lmidk-agdi.dll)\r
+ FLASH3 ("" ())\r
+ FLASH4 ()\r
+EndOpt\r
+\r
--- /dev/null
+#ifndef BITMAP_H\r
+#define BITMAP_H\r
+\r
+const unsigned char pucImage[] =\r
+{\r
+0x00, 0x0a, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,\r
+0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,\r
+0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,\r
+0xaa, 0xaa, 0xaa, 0x00, 0x0a, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,\r
+0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,\r
+0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,\r
+0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xa0, 0x0a, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,\r
+0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,\r
+0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,\r
+0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xaa, 0xaa, 0xaa, 0xaf, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfa, 0xaa,\r
+0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf7,\r
+0x00, 0x8f, 0xff, 0xff, 0xf8, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0xff, 0xff, 0xff, 0xff, 0xf8, 0x88, 0x88, 0x88,\r
+0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x8f, 0xff, 0xff, 0xff, 0xff, 0xff, 0x88, 0x77, 0x77, 0x78, 0x8f, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xf8, 0x88, 0x77, 0x77, 0x88, 0x8f, 0xff, 0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff,\r
+0xff, 0xff, 0xf0, 0x00, 0x00, 0x8f, 0x00, 0xff, 0x87, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x78, 0xff, 0xff,\r
+0xf7, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x78, 0xff, 0xff, 0xff, 0x87, 0x77, 0x77, 0x77, 0x77, 0x77,\r
+0x77, 0x77, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x7f, 0xff, 0xff, 0xfa, 0xaa,\r
+0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0x70, 0x00, 0x00, 0x8f, 0x00, 0xff, 0x87, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77,\r
+0x77, 0x77, 0xff, 0xff, 0xf7, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x78, 0xff, 0xff, 0xf8, 0x77, 0x77,\r
+0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x78, 0xff, 0xff, 0xff, 0xff, 0x87, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x8f,\r
+0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0x70, 0x08, 0x00, 0x8f, 0x00, 0xff, 0x87, 0x77, 0x77, 0x77,\r
+0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x8f, 0xff, 0xf7, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x78, 0xff,\r
+0xff, 0x87, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x8f, 0xff, 0xff, 0xf8, 0x77, 0x77, 0x77, 0x77, 0x77,\r
+0x77, 0x77, 0x77, 0x8f, 0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0x00, 0x0f, 0x00, 0x8f, 0x00, 0xff,\r
+0x87, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x78, 0xff, 0xf7, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77,\r
+0x77, 0x77, 0x78, 0xff, 0xf8, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x78, 0xff, 0xff, 0xf8, 0x77,\r
+0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x8f, 0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0x70, 0x07,\r
+0x00, 0x70, 0x00, 0xff, 0x87, 0x77, 0x77, 0x77, 0xff, 0xff, 0xf8, 0x77, 0x77, 0x77, 0x77, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0x77, 0x77, 0x77, 0x7f, 0xff, 0xff, 0xff, 0xff, 0x87, 0x77, 0x77, 0x77, 0x78, 0xff, 0xff, 0xf8, 0x77, 0x77, 0x77, 0x77,\r
+0xff, 0xff, 0x87, 0x77, 0x77, 0x77, 0x8f, 0xff, 0xff, 0xff, 0x88, 0x8f, 0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff,\r
+0xff, 0xff, 0x80, 0x00, 0x00, 0x00, 0x07, 0xff, 0x87, 0x77, 0x77, 0x77, 0xff, 0xff, 0xff, 0x87, 0x77, 0x77, 0x77, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0x77, 0x77, 0x77, 0x7f, 0xff, 0xff, 0xff, 0xff, 0x77, 0x77, 0x77, 0x77, 0xff, 0xff, 0xff, 0xff,\r
+0x87, 0x77, 0x77, 0x77, 0xff, 0xff, 0x77, 0x77, 0x77, 0x77, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfa, 0xaa,\r
+0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0xf7, 0x00, 0x00, 0x00, 0x0f, 0xff, 0x87, 0x77, 0x77, 0x77, 0xff, 0xff, 0xff, 0xf8,\r
+0x77, 0x77, 0x77, 0xff, 0xff, 0xff, 0xff, 0xff, 0x77, 0x77, 0x77, 0x7f, 0xff, 0xff, 0xff, 0xff, 0x77, 0x77, 0x77, 0x77,\r
+0xff, 0xff, 0xff, 0xff, 0xf7, 0x77, 0x77, 0x77, 0x8f, 0xff, 0x77, 0x77, 0x77, 0x77, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0xff, 0x70, 0x00, 0x00, 0xff, 0xff, 0x87, 0x77, 0x77, 0x77,\r
+0xff, 0xff, 0xff, 0xf8, 0x77, 0x77, 0x77, 0xff, 0xff, 0xff, 0xff, 0xff, 0x77, 0x77, 0x77, 0x7f, 0xff, 0xff, 0xff, 0xff,\r
+0x77, 0x77, 0x77, 0x78, 0xff, 0xff, 0xff, 0xff, 0xf8, 0x77, 0x77, 0x77, 0x8f, 0xff, 0x77, 0x77, 0x77, 0x77, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0x87, 0x77, 0x77, 0x77, 0xff, 0xff, 0xff, 0xf7, 0x77, 0x77, 0x78, 0xff, 0xff, 0xff, 0xff, 0xff, 0x77, 0x77, 0x77, 0x7f,\r
+0xff, 0xff, 0xff, 0xf8, 0x77, 0x77, 0x77, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xff, 0x87, 0x77, 0x77, 0x78, 0xff, 0x87, 0x77,\r
+0x77, 0x77, 0x78, 0x8f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0x88, 0xff, 0xff, 0xff, 0x87, 0x77, 0x77, 0x77, 0xff, 0xff, 0xf8, 0x87, 0x77, 0x77, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0x77, 0x77, 0x77, 0x7f, 0xff, 0xff, 0xff, 0xf8, 0x77, 0x77, 0x77, 0x8f, 0xff, 0xff, 0xff, 0xff, 0xff, 0x87, 0x77, 0x77,\r
+0x78, 0xff, 0x87, 0x77, 0x77, 0x77, 0x77, 0x77, 0x8f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0x80, 0x00, 0x8f, 0x8f, 0xff, 0x87, 0x77, 0x77, 0x77, 0x88, 0x88, 0x77, 0x77, 0x77, 0x77, 0x8f, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0x77, 0x77, 0x77, 0x7f, 0xff, 0xff, 0xff, 0xf8, 0x77, 0x77, 0x77, 0x8f, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0x87, 0x77, 0x77, 0x78, 0xff, 0xf7, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x88, 0xff, 0xff, 0xff, 0xff, 0xfa, 0xaa,\r
+0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0xf7, 0x00, 0x00, 0x8f, 0x07, 0xff, 0x87, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77,\r
+0x77, 0x77, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x77, 0x77, 0x77, 0x7f, 0xff, 0xff, 0xff, 0xf8, 0x77, 0x77, 0x77, 0x8f,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0x87, 0x77, 0x77, 0x78, 0xff, 0xf8, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x8f, 0xff,\r
+0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0x70, 0x07, 0x00, 0x8f, 0x00, 0xff, 0x87, 0x77, 0x77, 0x77,\r
+0x77, 0x77, 0x77, 0x77, 0x88, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x77, 0x77, 0x77, 0x7f, 0xff, 0xff, 0xff, 0xf8,\r
+0x77, 0x77, 0x77, 0x8f, 0xff, 0xff, 0xff, 0xff, 0xff, 0x87, 0x77, 0x77, 0x78, 0xff, 0xff, 0xf8, 0x77, 0x77, 0x77, 0x77,\r
+0x77, 0x77, 0x77, 0x8f, 0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0x70, 0x0f, 0x00, 0x8f, 0x00, 0xff,\r
+0x87, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x8f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x77, 0x77, 0x77, 0x7f,\r
+0xff, 0xff, 0xff, 0xf8, 0x77, 0x77, 0x77, 0x8f, 0xff, 0xff, 0xff, 0xff, 0xff, 0x87, 0x77, 0x77, 0x78, 0xff, 0xff, 0xff,\r
+0x87, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x78, 0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0x00, 0x0f,\r
+0x00, 0x8f, 0x00, 0xff, 0x87, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x78, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0x77, 0x77, 0x77, 0x7f, 0xff, 0xff, 0xff, 0xf8, 0x77, 0x77, 0x77, 0x8f, 0xff, 0xff, 0xff, 0xff, 0xff, 0x87, 0x77, 0x77,\r
+0x78, 0xff, 0xff, 0xff, 0xff, 0x88, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff,\r
+0xff, 0xff, 0x70, 0x08, 0x00, 0x88, 0x00, 0xff, 0x87, 0x77, 0x77, 0x77, 0x88, 0x88, 0x77, 0x77, 0x77, 0x78, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0x77, 0x77, 0x77, 0x7f, 0xff, 0xff, 0xff, 0xf8, 0x77, 0x77, 0x77, 0x8f, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0x87, 0x77, 0x77, 0x78, 0xff, 0xff, 0xff, 0xff, 0xff, 0x88, 0x77, 0x77, 0x77, 0x77, 0x77, 0xff, 0xff, 0xfa, 0xaa,\r
+0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0x70, 0x00, 0x00, 0x70, 0x07, 0xff, 0x87, 0x77, 0x77, 0x77, 0xff, 0xff, 0x77, 0x77,\r
+0x77, 0x77, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x77, 0x77, 0x77, 0x7f, 0xff, 0xff, 0xff, 0xf8, 0x77, 0x77, 0x77, 0x7f,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0x87, 0x77, 0x77, 0x78, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf8, 0x77, 0x77, 0x77, 0x77,\r
+0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0xf8, 0x00, 0x00, 0x00, 0x7f, 0xff, 0x87, 0x77, 0x77, 0x77,\r
+0xff, 0xff, 0xf7, 0x77, 0x77, 0x77, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x77, 0x77, 0x77, 0x7f, 0xff, 0xff, 0xff, 0xff,\r
+0x77, 0x77, 0x77, 0x78, 0xff, 0xff, 0xff, 0xff, 0xf8, 0x77, 0x77, 0x77, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0x87, 0x77, 0x77, 0x77, 0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0xff, 0x80, 0x00, 0x00, 0xff, 0xff,\r
+0x87, 0x77, 0x77, 0x77, 0xff, 0xff, 0xf8, 0x77, 0x77, 0x77, 0x8f, 0xff, 0xff, 0xff, 0xff, 0xff, 0x77, 0x77, 0x77, 0x7f,\r
+0xff, 0xff, 0xff, 0xff, 0x77, 0x77, 0x77, 0x77, 0xff, 0xff, 0xff, 0xff, 0xf7, 0x77, 0x77, 0x77, 0x8f, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0x87, 0x77, 0x77, 0x77, 0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0x87, 0x88,\r
+0x88, 0x8f, 0xff, 0xff, 0x87, 0x77, 0x77, 0x77, 0xff, 0xff, 0xff, 0x77, 0x77, 0x77, 0x8f, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0x77, 0x77, 0x77, 0x7f, 0xff, 0xff, 0xff, 0xff, 0x77, 0x77, 0x77, 0x77, 0xff, 0xff, 0xff, 0xff, 0x87, 0x77, 0x77, 0x77,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x87, 0x77, 0x77, 0x77, 0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff,\r
+0xff, 0xff, 0x00, 0x07, 0xff, 0xff, 0xff, 0xff, 0x87, 0x77, 0x77, 0x77, 0xff, 0xff, 0xff, 0x87, 0x77, 0x77, 0x7f, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0x77, 0x77, 0x77, 0x7f, 0xff, 0xff, 0xff, 0xff, 0x87, 0x77, 0x77, 0x77, 0x8f, 0xff, 0xff, 0xff,\r
+0x77, 0x77, 0x77, 0x77, 0xff, 0xff, 0xf7, 0x88, 0xff, 0xff, 0xff, 0xff, 0x87, 0x77, 0x77, 0x77, 0xff, 0xff, 0xfa, 0xaa,\r
+0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0x80, 0x00, 0xff, 0xff, 0xff, 0xff, 0x87, 0x77, 0x77, 0x77, 0xff, 0xff, 0xff, 0xf7,\r
+0x77, 0x77, 0x78, 0xff, 0xff, 0xff, 0xff, 0xff, 0x77, 0x77, 0x77, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xf8, 0x77, 0x77, 0x77,\r
+0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x78, 0xff, 0xff, 0x87, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x78,\r
+0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0xf7, 0x00, 0x88, 0x88, 0x88, 0xff, 0x87, 0x77, 0x77, 0x77,\r
+0xff, 0xff, 0xff, 0xf8, 0x77, 0x77, 0x77, 0xff, 0xff, 0xff, 0xff, 0xff, 0x77, 0x77, 0x77, 0x7f, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0x87, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x8f, 0xff, 0xff, 0x87, 0x77, 0x77, 0x77, 0x77, 0x77,\r
+0x77, 0x77, 0x77, 0x7f, 0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0x70, 0x00, 0x00, 0x00, 0x00, 0xff,\r
+0x87, 0x77, 0x77, 0x77, 0xff, 0xff, 0xff, 0xf8, 0x77, 0x77, 0x77, 0x8f, 0xff, 0xff, 0xff, 0xff, 0x77, 0x77, 0x77, 0x7f,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xf8, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x78, 0xff, 0xff, 0xff, 0x87, 0x77,\r
+0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0xff, 0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0x70, 0x00,\r
+0x00, 0x00, 0x00, 0xff, 0x87, 0x77, 0x77, 0x77, 0xff, 0xff, 0xff, 0xff, 0x77, 0x77, 0x77, 0x7f, 0xff, 0xff, 0xff, 0xff,\r
+0x77, 0x77, 0x77, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x87, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x8f, 0xff,\r
+0xff, 0xff, 0x87, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x8f, 0xff, 0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff,\r
+0xff, 0xff, 0x70, 0x00, 0x00, 0x00, 0x07, 0xff, 0x88, 0x88, 0x88, 0x88, 0xff, 0xff, 0xff, 0xff, 0x88, 0x88, 0x88, 0x88,\r
+0xff, 0xff, 0xff, 0xff, 0x88, 0x88, 0x88, 0x8f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf8, 0x87, 0x77, 0x77, 0x77,\r
+0x88, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x88, 0x77, 0x77, 0x77, 0x77, 0x88, 0x8f, 0xff, 0xff, 0xff, 0xff, 0xfa, 0xaa,\r
+0xaa, 0xaf, 0xff, 0xff, 0x00, 0x0f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff, 0x00, 0x0f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff, 0x00, 0x0f, 0x70, 0x08, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff, 0x00, 0x07, 0x70, 0x07,\r
+0x88, 0x88, 0x88, 0xff, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88,\r
+0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88,\r
+0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff,\r
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xfa, 0xaa,\r
+0xaa, 0xaf, 0xff, 0xff, 0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r
+0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff, 0xf7, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x70, 0x00, 0x00, 0x00,\r
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r
+0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0x70, 0x08, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0x70, 0x08,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfa, 0xaa,\r
+0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaa, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,\r
+0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,\r
+0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,\r
+0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x0a, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,\r
+0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,\r
+0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,\r
+0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xa0, 0x00, 0xaa, 0xaa, 0xaa,\r
+0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,\r
+0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,\r
+0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x00,\r
+0x00 };\r
+\r
+#define bmpBITMAP_HEIGHT 50\r
+#define bmpBITMAP_WIDTH 128\r
+\r
+#endif\r
--- /dev/null
+#ifndef LCD_MESSAGE_H\r
+#define LCD_MESSAGE_H\r
+\r
+typedef struct\r
+{\r
+ char *pcMessage;\r
+} xOLEDMessage;\r
+\r
+#endif /* LCD_MESSAGE_H */\r
--- /dev/null
+/*\r
+ FreeRTOS.org V4.3.0 - Copyright (C) 2003-2007 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS.org distribution.\r
+\r
+ FreeRTOS.org is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS.org is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS.org; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS.org, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section\r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license\r
+ and contact details. Please ensure to read the configuration and relevant\r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+\r
+/*\r
+ * Creates all the demo application tasks, then starts the scheduler. The WEB\r
+ * documentation provides more details of the standard demo application tasks.\r
+ * In addition to the standard demo tasks, the following tasks and tests are\r
+ * defined and/or created within this file:\r
+ *\r
+ * "Fast Interrupt Test" - A high frequency periodic interrupt is generated\r
+ * using a free running timer to demonstrate the use of the\r
+ * configKERNEL_INTERRUPT_PRIORITY configuration constant. The interrupt\r
+ * service routine measures the number of processor clocks that occur between\r
+ * each interrupt - and in so doing measures the jitter in the interrupt timing.\r
+ * The maximum measured jitter time is latched in the ulMaxJitter variable, and\r
+ * displayed on the OLED display by the 'Check' task as described below. The\r
+ * fast interrupt is configured and handled in the timertest.c source file.\r
+ *\r
+ * "OLED" task - the OLED task is a 'gatekeeper' task. It is the only task that\r
+ * is permitted to access the display directly. Other tasks wishing to write a\r
+ * message to the OLED send the message on a queue to the OLED task instead of\r
+ * accessing the OLED themselves. The OLED task just blocks on the queue waiting\r
+ * for messages - waking and displaying the messages as they arrive.\r
+ *\r
+ * "Check" task - This only executes every five seconds but has the highest\r
+ * priority so is guaranteed to get processor time. Its main function is to\r
+ * check that all the standard demo tasks are still operational. Should any\r
+ * unexpected behaviour within a demo task be discovered the 'check' task will\r
+ * write an error to the OLED (via the OLED task). If all the demo tasks are\r
+ * executing with their expected behaviour then the check task writes PASS\r
+ * along with the max jitter time to the OLED (again via the OLED task), as\r
+ * described above.\r
+ *\r
+ */\r
+\r
+\r
+\r
+/* Standard includes. */\r
+#include <stdio.h>\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "Task.h"\r
+#include "queue.h"\r
+#include "semphr.h"\r
+\r
+/* Demo app includes. */\r
+#include "BlockQ.h"\r
+#include "death.h"\r
+#include "integer.h"\r
+#include "blocktim.h"\r
+#include "flash.h"\r
+#include "partest.h"\r
+#include "semtest.h"\r
+#include "pollq.h"\r
+#include "lcd_message.h"\r
+#include "bitmap.h"\r
+\r
+/* Hardware library includes. */\r
+#include "hw_memmap.h"\r
+#include "hw_types.h"\r
+#include "sysctl.h"\r
+#include "gpio.h"\r
+#include "osram128x64x4.h"\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* The time between cycles of the 'check' task. */\r
+#define mainCHECK_DELAY ( ( portTickType ) 5000 / portTICK_RATE_MS )\r
+\r
+/* The check task uses the sprintf function so requires a little more stack too. */\r
+#define mainCHECK_TASK_STACK_SIZE ( configMINIMAL_STACK_SIZE + 50 )\r
+\r
+/* Task priorities. */\r
+#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
+#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 )\r
+#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 )\r
+#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
+#define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 )\r
+#define mainINTEGER_TASK_PRIORITY ( tskIDLE_PRIORITY )\r
+\r
+/* The maximum number of message that can be waiting for display at any one\r
+time. */\r
+#define mainOLED_QUEUE_SIZE ( 3 )\r
+\r
+/* Dimensions the buffer into which the jitter time is written. */\r
+#define mainMAX_MSG_LEN 25\r
+\r
+/* The period of the system clock in nano seconds. This is used to calculate\r
+the jitter time in nano seconds. */\r
+#define mainNS_PER_CLOCK ( ( unsigned portLONG ) ( ( 1.0 / ( double ) configCPU_CLOCK_HZ ) * 1000000000.0 ) )\r
+\r
+/* Constants used when writing strings to the display. */\r
+#define mainCHARACTER_HEIGHT ( 9 )\r
+#define mainMAX_ROWS ( mainCHARACTER_HEIGHT * 7 )\r
+#define mainFULL_SCALE ( 15 )\r
+#define ulSSI_FREQUENCY 1000000\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Checks the status of all the demo tasks then prints a message to the\r
+ * display. The message will be either PASS - an include in brackets the\r
+ * maximum measured jitter time (as described at the to of the file), or a\r
+ * message that describes which of the standard demo tasks an error has been\r
+ * discovered in.\r
+ *\r
+ * Messages are not written directly to the terminal, but passed to vOLEDTask\r
+ * via a queue.\r
+ */\r
+static void vCheckTask( void *pvParameters );\r
+\r
+/*\r
+ * The display is written two by more than one task so is controlled by a\r
+ * 'gatekeeper' task. This is the only task that is actually permitted to\r
+ * access the display directly. Other tasks wanting to display a message send\r
+ * the message to the gatekeeper.\r
+ */\r
+static void vOLEDTask( void *pvParameters );\r
+\r
+/*\r
+ * Configure the hardware for the demo.\r
+ */\r
+static void prvSetupHardware( void );\r
+\r
+/*\r
+ * Configures the high frequency timers - those used to measure the timing\r
+ * jitter while the real time kernel is executing.\r
+ */\r
+extern void vSetupTimer( void );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* The queue used to send messages to the OLED task. */\r
+xQueueHandle xOLEDQueue;\r
+\r
+/* The welcome text. */\r
+const portCHAR * const pcWelcomeMessage = " www.FreeRTOS.org";\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+int main( void )\r
+{\r
+ prvSetupHardware();\r
+\r
+ /* Create the queue used by the OLED task. Messages for display on the OLED\r
+ are received via this queue. */\r
+ xOLEDQueue = xQueueCreate( mainOLED_QUEUE_SIZE, sizeof( xOLEDMessage ) );\r
+\r
+ /* Start the standard demo tasks. */\r
+ vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY );\r
+ vCreateBlockTimeTasks();\r
+ vStartSemaphoreTasks( mainSEM_TEST_PRIORITY );\r
+ vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY );\r
+ vStartIntegerMathTasks( mainINTEGER_TASK_PRIORITY );\r
+\r
+ /* Start the tasks defined within this file/specific to this demo. */\r
+ xTaskCreate( vCheckTask, ( signed portCHAR * ) "Check", mainCHECK_TASK_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL );\r
+ xTaskCreate( vOLEDTask, ( signed portCHAR * ) "OLED", configMINIMAL_STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );\r
+\r
+ /* The suicide tasks must be created last as they need to know how many\r
+ tasks were running prior to their creation in order to ascertain whether\r
+ or not the correct/expected number of tasks are running at any given time. */\r
+ vCreateSuicidalTasks( mainCREATOR_TASK_PRIORITY );\r
+\r
+ /* Configure the high frequency interrupt used to measure the interrupt\r
+ jitter time. */\r
+ #ifdef __ICCARM__\r
+ vSetupTimer();\r
+ #endif\r
+ \r
+ /* Start the scheduler. */\r
+ vTaskStartScheduler();\r
+\r
+ /* Will only get here if there was insufficient memory to create the idle\r
+ task. */\r
+ return 0;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void prvSetupHardware( void )\r
+{\r
+ /* Set the clocking to run from the PLL at 50 MHz */\r
+ SysCtlClockSet( SYSCTL_SYSDIV_4 | SYSCTL_USE_PLL | SYSCTL_OSC_MAIN | SYSCTL_XTAL_8MHZ );\r
+ \r
+ /* Enable Port F for Ethernet LEDs\r
+ LED0 Bit 3 Output\r
+ LED1 Bit 2 Output */\r
+ SysCtlPeripheralEnable( SYSCTL_PERIPH_GPIOF );\r
+ GPIODirModeSet( GPIO_PORTF_BASE, (GPIO_PIN_2 | GPIO_PIN_3), GPIO_DIR_MODE_HW );\r
+ GPIOPadConfigSet( GPIO_PORTF_BASE, (GPIO_PIN_2 | GPIO_PIN_3 ), GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD ); \r
+ \r
+ vParTestInitialise();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void vCheckTask( void *pvParameters )\r
+{\r
+portTickType xLastExecutionTime;\r
+xOLEDMessage xMessage;\r
+static portCHAR cPassMessage[ mainMAX_MSG_LEN ];\r
+extern unsigned portLONG ulMaxJitter;\r
+\r
+ xLastExecutionTime = xTaskGetTickCount();\r
+ xMessage.pcMessage = cPassMessage;\r
+ \r
+ for( ;; )\r
+ {\r
+ /* Perform this check every mainCHECK_DELAY milliseconds. */\r
+ vTaskDelayUntil( &xLastExecutionTime, mainCHECK_DELAY );\r
+\r
+ /* Has an error been found in any task? */\r
+\r
+ if( xAreBlockingQueuesStillRunning() != pdTRUE )\r
+ {\r
+ xMessage.pcMessage = "ERROR IN BLOCK Q";\r
+ }\r
+ else if( xAreBlockTimeTestTasksStillRunning() != pdTRUE )\r
+ {\r
+ xMessage.pcMessage = "ERROR IN BLOCK TIME";\r
+ }\r
+ else if( xAreSemaphoreTasksStillRunning() != pdTRUE )\r
+ {\r
+ xMessage.pcMessage = "ERROR IN SEMAPHORE";\r
+ }\r
+ else if( xArePollingQueuesStillRunning() != pdTRUE )\r
+ {\r
+ xMessage.pcMessage = "ERROR IN POLL Q";\r
+ }\r
+ else if( xIsCreateTaskStillRunning() != pdTRUE )\r
+ {\r
+ xMessage.pcMessage = "ERROR IN CREATE";\r
+ }\r
+ else if( xAreIntegerMathsTaskStillRunning() != pdTRUE )\r
+ {\r
+ xMessage.pcMessage = "ERROR IN MATH";\r
+ }\r
+ else\r
+ {\r
+ #ifdef __ICCARM__\r
+ sprintf( cPassMessage, "PASS [%uns]", ulMaxJitter * mainNS_PER_CLOCK );\r
+ #else\r
+ sprintf( cPassMessage, "PASS" );\r
+ #endif\r
+ }\r
+\r
+ /* Send the message to the OLED gatekeeper for display. */\r
+ xQueueSend( xOLEDQueue, &xMessage, portMAX_DELAY );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+\r
+\r
+void vOLEDTask( void *pvParameters )\r
+{\r
+xOLEDMessage xMessage;\r
+unsigned portLONG ulY = mainMAX_ROWS;\r
+\r
+ /* Initialise the OLED and display a startup message. */\r
+ OSRAM128x64x4Init( ulSSI_FREQUENCY ); \r
+ \r
+ OSRAM128x64x4StringDraw( " POWERED BY FreeRTOS", 0, 0, mainFULL_SCALE );\r
+ OSRAM128x64x4ImageDraw( pucImage, 0, mainCHARACTER_HEIGHT + 1, bmpBITMAP_WIDTH, bmpBITMAP_HEIGHT );\r
+ \r
+ for( ;; )\r
+ {\r
+ /* Wait for a message to arrive that requires displaying. */\r
+ xQueueReceive( xOLEDQueue, &xMessage, portMAX_DELAY );\r
+ \r
+ /* Write the message on the next available row. */\r
+ ulY += mainCHARACTER_HEIGHT;\r
+ if( ulY >= mainMAX_ROWS )\r
+ {\r
+ ulY = mainCHARACTER_HEIGHT;\r
+ OSRAM128x64x4Clear();\r
+ OSRAM128x64x4StringDraw( pcWelcomeMessage, 0, 0, mainFULL_SCALE ); \r
+ }\r
+\r
+ /* Display the message. */\r
+ OSRAM128x64x4StringDraw( xMessage.pcMessage, 0, ulY, mainFULL_SCALE );\r
+ }\r
+}\r
--- /dev/null
+; <<< Use Configuration Wizard in Context Menu >>>\r
+;******************************************************************************\r
+;\r
+; startup_rvmdk.S - Startup code for use with Keil's uVision.\r
+;\r
+; Copyright (c) 2007 Luminary Micro, Inc. All rights reserved.\r
+; \r
+; Software License Agreement\r
+; \r
+; Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+; exclusively on LMI's microcontroller products.\r
+; \r
+; The software is owned by LMI and/or its suppliers, and is protected under\r
+; applicable copyright laws. All rights are reserved. Any use in violation\r
+; of the foregoing restrictions may subject the user to criminal sanctions\r
+; under applicable laws, as well as to civil liability for the breach of the\r
+; terms and conditions of this license.\r
+; \r
+; THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+; OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+; MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+; LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+; CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+; \r
+; This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+;\r
+;******************************************************************************\r
+\r
+;******************************************************************************\r
+;\r
+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\r
+;\r
+;******************************************************************************\r
+Stack EQU 0x00000800\r
+\r
+;******************************************************************************\r
+;\r
+; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\r
+;\r
+;******************************************************************************\r
+Heap EQU 0x00000000\r
+\r
+;******************************************************************************\r
+;\r
+; Allocate space for the stack.\r
+;\r
+;******************************************************************************\r
+ AREA STACK, NOINIT, READWRITE, ALIGN=3\r
+StackMem\r
+ SPACE Stack\r
+__initial_sp\r
+\r
+;******************************************************************************\r
+;\r
+; Allocate space for the heap.\r
+;\r
+;******************************************************************************\r
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3\r
+__heap_base\r
+HeapMem\r
+ SPACE Heap\r
+__heap_limit\r
+\r
+;******************************************************************************\r
+;\r
+; Indicate that the code in this file preserves 8-byte alignment of the stack.\r
+;\r
+;******************************************************************************\r
+ PRESERVE8\r
+\r
+;******************************************************************************\r
+;\r
+; Place code into the reset code section.\r
+;\r
+;******************************************************************************\r
+ AREA RESET, CODE, READONLY\r
+ THUMB\r
+\r
+;******************************************************************************\r
+;\r
+; The vector table.\r
+;\r
+;******************************************************************************\r
+ EXPORT __Vectors\r
+__Vectors\r
+ DCD StackMem + Stack ; Top of Stack\r
+ DCD Reset_Handler ; Reset Handler\r
+ DCD NmiSR ; NMI Handler\r
+ DCD FaultISR ; Hard Fault Handler\r
+ DCD IntDefaultHandler ; MPU Fault Handler\r
+ DCD IntDefaultHandler ; Bus Fault Handler\r
+ DCD IntDefaultHandler ; Usage Fault Handler\r
+ DCD 0 ; Reserved\r
+ DCD 0 ; Reserved\r
+ DCD 0 ; Reserved\r
+ DCD 0 ; Reserved\r
+ DCD IntDefaultHandler ; SVCall Handler\r
+ DCD IntDefaultHandler ; Debug Monitor Handler\r
+ DCD 0 ; Reserved\r
+ EXTERN xPortPendSVHandler\r
+ DCD xPortPendSVHandler ; PendSV Handler\r
+ EXTERN xPortSysTickHandler\r
+ DCD xPortSysTickHandler ; SysTick Handler\r
+ DCD IntDefaultHandler ; GPIO Port A\r
+ DCD IntDefaultHandler ; GPIO Port B\r
+ DCD IntDefaultHandler ; GPIO Port C\r
+ DCD IntDefaultHandler ; GPIO Port D\r
+ DCD IntDefaultHandler ; GPIO Port E\r
+ DCD IntDefaultHandler ; UART0\r
+ DCD IntDefaultHandler ; UART1\r
+ DCD IntDefaultHandler ; SSI\r
+ DCD IntDefaultHandler ; I2C\r
+ DCD IntDefaultHandler ; PWM Fault\r
+ DCD IntDefaultHandler ; PWM Generator 0\r
+ DCD IntDefaultHandler ; PWM Generator 1\r
+ DCD IntDefaultHandler ; PWM Generator 2\r
+ DCD IntDefaultHandler ; Quadrature Encoder\r
+ DCD IntDefaultHandler ; ADC Sequence 0\r
+ DCD IntDefaultHandler ; ADC Sequence 1\r
+ DCD IntDefaultHandler ; ADC Sequence 2\r
+ DCD IntDefaultHandler ; ADC Sequence 3\r
+ DCD IntDefaultHandler ; Watchdog\r
+ EXTERN Timer0IntHandler\r
+ DCD Timer0IntHandler ; Timer 0A\r
+ DCD IntDefaultHandler ; Timer 0B\r
+ DCD IntDefaultHandler ; Timer 1A\r
+ DCD IntDefaultHandler ; Timer 1B\r
+ DCD IntDefaultHandler ; Timer 2A\r
+ DCD IntDefaultHandler ; Timer 2B\r
+ DCD IntDefaultHandler ; Comp 0\r
+ DCD IntDefaultHandler ; Comp 1\r
+ DCD IntDefaultHandler ; Comp 2\r
+ DCD IntDefaultHandler ; System Control\r
+ DCD IntDefaultHandler ; Flash Control\r
+ DCD IntDefaultHandler ; GPIO Port F\r
+ DCD IntDefaultHandler ; GPIO Port G\r
+ DCD IntDefaultHandler ; GPIO Port H\r
+ DCD IntDefaultHandler ; UART2 Rx and Tx\r
+ DCD IntDefaultHandler ; SSI1 Rx and Tx\r
+ DCD IntDefaultHandler ; Timer 3 subtimer A\r
+ DCD IntDefaultHandler ; Timer 3 subtimer B\r
+ DCD IntDefaultHandler ; I2C1 Master and Slave\r
+ DCD IntDefaultHandler ; Quadrature Encoder 1\r
+ DCD IntDefaultHandler ; CAN0\r
+ DCD IntDefaultHandler ; CAN1\r
+ DCD 0 ; Reserved\r
+ DCD IntDefaultHandler ; Ethernet\r
+ DCD IntDefaultHandler ; Hibernate\r
+\r
+;******************************************************************************\r
+;\r
+; This is the code that gets called when the processor first starts execution\r
+; following a reset event.\r
+;\r
+;******************************************************************************\r
+ EXPORT Reset_Handler\r
+Reset_Handler\r
+ ;\r
+ ; Call the C library enty point that handles startup. This will copy\r
+ ; the .data section initializers from flash to SRAM and zero fill the\r
+ ; .bss section. It will then call __rt_entry, which will be either the\r
+ ; C library version or the one supplied here depending on the\r
+ ; configured startup type.\r
+ ;\r
+ IMPORT __main\r
+ B __main\r
+\r
+;******************************************************************************\r
+;\r
+; This is the code that gets called when the processor receives a NMI. This\r
+; simply enters an infinite loop, preserving the system state for examination\r
+; by a debugger.\r
+;\r
+;******************************************************************************\r
+NmiSR\r
+ B NmiSR\r
+\r
+;******************************************************************************\r
+;\r
+; This is the code that gets called when the processor receives a fault\r
+; interrupt. This simply enters an infinite loop, preserving the system state\r
+; for examination by a debugger.\r
+;\r
+;******************************************************************************\r
+FaultISR\r
+ B FaultISR\r
+\r
+;******************************************************************************\r
+;\r
+; This is the code that gets called when the processor receives an unexpected\r
+; interrupt. This simply enters an infinite loop, preserving the system state\r
+; for examination by a debugger.\r
+;\r
+;******************************************************************************\r
+IntDefaultHandler\r
+ B IntDefaultHandler\r
+\r
+;******************************************************************************\r
+;\r
+; Make sure the end of this section is aligned.\r
+;\r
+;******************************************************************************\r
+ ALIGN\r
+\r
+;******************************************************************************\r
+;\r
+; Some code in the normal code section for initializing the heap and stack.\r
+;\r
+;******************************************************************************\r
+ AREA |.text|, CODE, READONLY\r
+\r
+;******************************************************************************\r
+;\r
+; The function expected of the C library startup code for defining the stack\r
+; and heap memory locations. For the C library version of the startup code,\r
+; provide this function so that the C library initialization code can find out\r
+; the location of the stack and heap.\r
+;\r
+;******************************************************************************\r
+ IF :DEF: __MICROLIB\r
+ EXPORT __initial_sp\r
+ EXPORT __heap_base\r
+ EXPORT __heap_limit\r
+ ELSE\r
+ IMPORT __use_two_region_memory\r
+ EXPORT __user_initial_stackheap\r
+__user_initial_stackheap\r
+ LDR R0, =HeapMem\r
+ LDR R1, =(StackMem + Stack)\r
+ LDR R2, =(HeapMem + Heap)\r
+ LDR R3, =StackMem\r
+ BX LR\r
+ ENDIF\r
+\r
+;******************************************************************************\r
+;\r
+; Make sure the end of this section is aligned.\r
+;\r
+;******************************************************************************\r
+ ALIGN\r
+\r
+;******************************************************************************\r
+;\r
+; Tell the assembler that we're done.\r
+;\r
+;******************************************************************************\r
+ END\r
--- /dev/null
+/*\r
+ FreeRTOS.org V4.3.0 - Copyright (C) 2003-2007 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS.org distribution.\r
+\r
+ FreeRTOS.org is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS.org is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS.org; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS.org, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section\r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license\r
+ and contact details. Please ensure to read the configuration and relevant\r
+ port sections of the online documentation.\r
+\r
+ Also see http://www.SafeRTOS.com for an IEC 61508 compliant version along\r
+ with commercial development and support options.\r
+ ***************************************************************************\r
+*/\r
+\r
+/* High speed timer test as described in main.c. */\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+\r
+/* Library includes. */\r
+#include "hw_ints.h"\r
+#include "hw_memmap.h"\r
+#include "hw_types.h"\r
+#include "interrupt.h"\r
+#include "sysctl.h"\r
+#include "LMI_timer.h"\r
+\r
+/* The set frequency of the interrupt. Deviations from this are measured as\r
+the jitter. */\r
+#define timerINTERRUPT_FREQUENCY ( 20000UL )\r
+\r
+/* The expected time between each of the timer interrupts - if the jitter was\r
+zero. */\r
+#define timerEXPECTED_DIFFERENCE_VALUE ( configCPU_CLOCK_HZ / timerINTERRUPT_FREQUENCY )\r
+\r
+/* The highest available interrupt priority. */\r
+#define timerHIGHEST_PRIORITY ( 0 )\r
+\r
+/* Misc defines. */\r
+#define timerMAX_32BIT_VALUE ( 0xffffffffUL )\r
+#define timerTIMER_1_COUNT_VALUE ( * ( ( unsigned long * ) ( TIMER1_BASE + 0x48 ) ) )\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Interrupt handler in which the jitter is measured. */\r
+void Timer0IntHandler( void );\r
+\r
+/* Stores the value of the maximum recorded jitter between interrupts. */\r
+unsigned portLONG ulMaxJitter = 0;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void vSetupTimer( void )\r
+{\r
+unsigned long ulFrequency;\r
+\r
+ /* Timer zero is used to generate the interrupts, and timer 1 is used\r
+ to measure the jitter. */\r
+ SysCtlPeripheralEnable( SYSCTL_PERIPH_TIMER0 );\r
+ SysCtlPeripheralEnable( SYSCTL_PERIPH_TIMER1 );\r
+ TimerConfigure( TIMER0_BASE, TIMER_CFG_32_BIT_PER );\r
+ TimerConfigure( TIMER1_BASE, TIMER_CFG_32_BIT_PER );\r
+ \r
+ /* Set the timer interrupt to be above the kernel - highest. */\r
+ IntPrioritySet( INT_TIMER0A, timerHIGHEST_PRIORITY );\r
+\r
+ /* Just used to measure time. */\r
+ TimerLoadSet(TIMER1_BASE, TIMER_A, timerMAX_32BIT_VALUE );\r
+ \r
+ /* The rate at which the timer will interrupt. */\r
+ ulFrequency = configCPU_CLOCK_HZ / timerINTERRUPT_FREQUENCY; \r
+ TimerLoadSet( TIMER0_BASE, TIMER_A, ulFrequency );\r
+ IntEnable( INT_TIMER0A );\r
+ TimerIntEnable( TIMER0_BASE, TIMER_TIMA_TIMEOUT );\r
+\r
+ /* Enable both timers. */ \r
+ TimerEnable( TIMER0_BASE, TIMER_A );\r
+ TimerEnable( TIMER1_BASE, TIMER_A );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void Timer0IntHandler( void )\r
+{\r
+unsigned portLONG ulDifference, ulCurrentCount;\r
+static portLONG ulMaxDifference = 0, ulLastCount = 0;\r
+\r
+ /* We use the timer 1 counter value to measure the clock cycles between\r
+ the timer 0 interrupts. */\r
+ ulCurrentCount = timerTIMER_1_COUNT_VALUE;\r
+\r
+ if( ulCurrentCount < ulLastCount )\r
+ { \r
+ /* How many times has timer 1 counted since the last interrupt? */\r
+ ulDifference = ulLastCount - ulCurrentCount;\r
+ \r
+ /* Is this the largest difference we have measured yet? */\r
+ if( ulDifference > ulMaxDifference )\r
+ {\r
+ ulMaxDifference = ulDifference;\r
+ ulMaxJitter = ulMaxDifference - timerEXPECTED_DIFFERENCE_VALUE;\r
+ }\r
+ }\r
+ \r
+ ulLastCount = ulCurrentCount;\r
+\r
+ TimerIntClear( TIMER0_BASE, TIMER_TIMA_TIMEOUT );\r
+}\r
+\r
+\r
+\r
+\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS.org V4.3.0 - Copyright (C) 2003-2007 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS.org distribution.\r
+\r
+ FreeRTOS.org is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS.org is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS.org; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS.org, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section\r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license\r
+ and contact details. Please ensure to read the configuration and relevant\r
+ port sections of the online documentation.\r
+\r
+ Also see http://www.SafeRTOS.com for an IEC 61508 compliant version along\r
+ with commercial development and support options.\r
+ ***************************************************************************\r
+*/\r
+\r
+#ifndef FREERTOS_CONFIG_H\r
+#define FREERTOS_CONFIG_H\r
+\r
+/*-----------------------------------------------------------\r
+ * Application specific definitions.\r
+ *\r
+ * These definitions should be adjusted for your particular hardware and\r
+ * application requirements.\r
+ *\r
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE\r
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.\r
+ *----------------------------------------------------------*/\r
+\r
+#define configUSE_PREEMPTION 1\r
+#define configUSE_IDLE_HOOK 0\r
+#define configUSE_TICK_HOOK 0\r
+#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 50000000 )\r
+#define configTICK_RATE_HZ ( ( portTickType ) 1000 )\r
+#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 70 )\r
+#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 12000 ) )\r
+#define configMAX_TASK_NAME_LEN ( 12 )\r
+#define configUSE_TRACE_FACILITY 1\r
+#define configUSE_16_BIT_TICKS 0\r
+#define configIDLE_SHOULD_YIELD 0\r
+#define configUSE_CO_ROUTINES 0\r
+\r
+#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 5 )\r
+#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )\r
+\r
+/* Set the following definitions to 1 to include the API function, or zero\r
+to exclude the API function. */\r
+\r
+#define INCLUDE_vTaskPrioritySet 1\r
+#define INCLUDE_uxTaskPriorityGet 0\r
+#define INCLUDE_vTaskDelete 1\r
+#define INCLUDE_vTaskCleanUpResources 0\r
+#define INCLUDE_vTaskSuspend 1\r
+#define INCLUDE_vTaskDelayUntil 1\r
+#define INCLUDE_vTaskDelay 1\r
+\r
+\r
+#define configKERNEL_INTERRUPT_PRIORITY 255\r
+\r
+\r
+#endif /* FREERTOS_CONFIG_H */\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// LM3Sxxx.h - Header file for Luminary Micro LM3Sxxx microcontrollers.\r
+//\r
+// Copyright (c) 2006-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __LM3SXXX_H__\r
+#define __LM3SXXX_H__\r
+\r
+#include "hw_adc.h"\r
+#include "hw_comp.h"\r
+#include "hw_flash.h"\r
+#include "hw_gpio.h"\r
+#include "hw_i2c.h"\r
+#include "hw_ints.h"\r
+#include "hw_memmap.h"\r
+#include "hw_nvic.h"\r
+#include "hw_pwm.h"\r
+#include "hw_qei.h"\r
+#include "hw_ssi.h"\r
+#include "hw_sysctl.h"\r
+#include "hw_timer.h"\r
+#include "hw_types.h"\r
+#include "hw_uart.h"\r
+#include "hw_watchdog.h"\r
+#include "adc.h"\r
+#include "comp.h"\r
+#include "cpu.h"\r
+#include "debug.h"\r
+#include "flash.h"\r
+#include "gpio.h"\r
+#include "i2c.h"\r
+#include "interrupt.h"\r
+#include "pwm.h"\r
+#include "qei.h"\r
+#include "ssi.h"\r
+#include "sysctl.h"\r
+#include "systick.h"\r
+#include "timer.h"\r
+#include "uart.h"\r
+#include "watchdog.h"\r
+\r
+#endif // __LM3SXXX_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// LM3Sxxxx.h - Header file for Luminary Micro LM3Sxxxx microcontrollers.\r
+//\r
+// Copyright (c) 2006-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __LM3SXXXX_H__\r
+#define __LM3SXXXX_H__\r
+\r
+#include "hw_adc.h"\r
+#include "hw_can.h"\r
+#include "hw_comp.h"\r
+#include "hw_ethernet.h"\r
+#include "hw_flash.h"\r
+#include "hw_gpio.h"\r
+#include "hw_hibernate.h"\r
+#include "hw_i2c.h"\r
+#include "hw_ints.h"\r
+#include "hw_memmap.h"\r
+#include "hw_nvic.h"\r
+#include "hw_pwm.h"\r
+#include "hw_qei.h"\r
+#include "hw_ssi.h"\r
+#include "hw_sysctl.h"\r
+#include "hw_timer.h"\r
+#include "hw_types.h"\r
+#include "hw_uart.h"\r
+#include "hw_watchdog.h"\r
+#include "adc.h"\r
+#include "can.h"\r
+#include "comp.h"\r
+#include "cpu.h"\r
+#include "debug.h"\r
+#include "ethernet.h"\r
+#include "flash.h"\r
+#include "gpio.h"\r
+#include "hibernate.h"\r
+#include "i2c.h"\r
+#include "interrupt.h"\r
+#include "pwm.h"\r
+#include "qei.h"\r
+#include "ssi.h"\r
+#include "sysctl.h"\r
+#include "systick.h"\r
+#include "timer.h"\r
+#include "uart.h"\r
+#include "watchdog.h"\r
+\r
+#endif // __LM3SXXXX_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// flash.h - Prototypes for the flash driver.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __FLASH_H__\r
+#define __FLASH_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to FlashProtectSet(), and returned by\r
+// FlashProtectGet().\r
+//\r
+//*****************************************************************************\r
+typedef enum\r
+{\r
+ FlashReadWrite, // Flash can be read and written\r
+ FlashReadOnly, // Flash can only be read\r
+ FlashExecuteOnly // Flash can only be executed\r
+}\r
+tFlashProtection;\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+extern unsigned long FlashUsecGet(void);\r
+extern void FlashUsecSet(unsigned long ulClocks);\r
+extern long FlashErase(unsigned long ulAddress);\r
+extern long FlashProgram(unsigned long *pulData, unsigned long ulAddress,\r
+ unsigned long ulCount);\r
+extern tFlashProtection FlashProtectGet(unsigned long ulAddress);\r
+extern long FlashProtectSet(unsigned long ulAddress,\r
+ tFlashProtection eProtect);\r
+extern long FlashProtectSave(void);\r
+extern long FlashUserGet(unsigned long *pulUser0, unsigned long *pulUser1);\r
+extern long FlashUserSet(unsigned long ulUser0, unsigned long ulUser1);\r
+extern long FlashUserSave(void);\r
+extern void FlashIntRegister(void (*pfnHandler)(void));\r
+extern void FlashIntUnregister(void);\r
+extern void FlashIntEnable(unsigned long ulIntFlags);\r
+extern void FlashIntDisable(unsigned long ulIntFlags);\r
+extern unsigned long FlashIntGetStatus(tBoolean bMasked);\r
+extern void FlashIntClear(unsigned long ulIntFlags);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __FLASH_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// timer.h - Prototypes for the timer module\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __TIMER_H__\r
+#define __TIMER_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to TimerConfigure as the ulConfig parameter.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_CFG_32_BIT_OS 0x00000001 // 32-bit one-shot timer\r
+#define TIMER_CFG_32_BIT_PER 0x00000002 // 32-bit periodic timer\r
+#define TIMER_CFG_32_RTC 0x01000000 // 32-bit RTC timer\r
+#define TIMER_CFG_16_BIT_PAIR 0x04000000 // Two 16-bit timers\r
+#define TIMER_CFG_A_ONE_SHOT 0x00000001 // Timer A one-shot timer\r
+#define TIMER_CFG_A_PERIODIC 0x00000002 // Timer A periodic timer\r
+#define TIMER_CFG_A_CAP_COUNT 0x00000003 // Timer A event counter\r
+#define TIMER_CFG_A_CAP_TIME 0x00000007 // Timer A event timer\r
+#define TIMER_CFG_A_PWM 0x0000000A // Timer A PWM output\r
+#define TIMER_CFG_B_ONE_SHOT 0x00000100 // Timer B one-shot timer\r
+#define TIMER_CFG_B_PERIODIC 0x00000200 // Timer B periodic timer\r
+#define TIMER_CFG_B_CAP_COUNT 0x00000300 // Timer B event counter\r
+#define TIMER_CFG_B_CAP_TIME 0x00000700 // Timer B event timer\r
+#define TIMER_CFG_B_PWM 0x00000A00 // Timer B PWM output\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to TimerIntEnable, TimerIntDisable, and\r
+// TimerIntClear as the ulIntFlags parameter, and returned from TimerIntStatus.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_CAPB_EVENT 0x00000400 // CaptureB event interrupt\r
+#define TIMER_CAPB_MATCH 0x00000200 // CaptureB match interrupt\r
+#define TIMER_TIMB_TIMEOUT 0x00000100 // TimerB time out interrupt\r
+#define TIMER_RTC_MATCH 0x00000008 // RTC interrupt mask\r
+#define TIMER_CAPA_EVENT 0x00000004 // CaptureA event interrupt\r
+#define TIMER_CAPA_MATCH 0x00000002 // CaptureA match interrupt\r
+#define TIMER_TIMA_TIMEOUT 0x00000001 // TimerA time out interrupt\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to TimerControlEvent as the ulEvent parameter.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_EVENT_POS_EDGE 0x00000000 // Count positive edges\r
+#define TIMER_EVENT_NEG_EDGE 0x00000404 // Count negative edges\r
+#define TIMER_EVENT_BOTH_EDGES 0x00000C0C // Count both edges\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to most of the timer APIs as the ulTimer\r
+// parameter.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_A 0x000000ff // Timer A\r
+#define TIMER_B 0x0000ff00 // Timer B\r
+#define TIMER_BOTH 0x0000ffff // Timer Both\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+extern void TimerEnable(unsigned long ulBase, unsigned long ulTimer);\r
+extern void TimerDisable(unsigned long ulBase, unsigned long ulTimer);\r
+extern void TimerConfigure(unsigned long ulBase, unsigned long ulConfig);\r
+extern void TimerControlLevel(unsigned long ulBase, unsigned long ulTimer,\r
+ tBoolean bInvert);\r
+extern void TimerControlTrigger(unsigned long ulBase, unsigned long ulTimer,\r
+ tBoolean bEnable);\r
+extern void TimerControlEvent(unsigned long ulBase, unsigned long ulTimer,\r
+ unsigned long ulEvent);\r
+extern void TimerControlStall(unsigned long ulBase, unsigned long ulTimer,\r
+ tBoolean bStall);\r
+extern void TimerRTCEnable(unsigned long ulBase);\r
+extern void TimerRTCDisable(unsigned long ulBase);\r
+extern void TimerPrescaleSet(unsigned long ulBase, unsigned long ulTimer,\r
+ unsigned long ulValue);\r
+extern unsigned long TimerPrescaleGet(unsigned long ulBase,\r
+ unsigned long ulTimer);\r
+extern void TimerPrescaleMatchSet(unsigned long ulBase, unsigned long ulTimer,\r
+ unsigned long ulValue);\r
+extern unsigned long TimerPrescaleMatchGet(unsigned long ulBase,\r
+ unsigned long ulTimer);\r
+extern void TimerLoadSet(unsigned long ulBase, unsigned long ulTimer,\r
+ unsigned long ulValue);\r
+extern unsigned long TimerLoadGet(unsigned long ulBase, unsigned long ulTimer);\r
+extern unsigned long TimerValueGet(unsigned long ulBase,\r
+ unsigned long ulTimer);\r
+extern void TimerMatchSet(unsigned long ulBase, unsigned long ulTimer,\r
+ unsigned long ulValue);\r
+extern unsigned long TimerMatchGet(unsigned long ulBase,\r
+ unsigned long ulTimer);\r
+extern void TimerIntRegister(unsigned long ulBase, unsigned long ulTimer,\r
+ void (*pfnHandler)(void));\r
+extern void TimerIntUnregister(unsigned long ulBase, unsigned long ulTimer);\r
+extern void TimerIntEnable(unsigned long ulBase, unsigned long ulIntFlags);\r
+extern void TimerIntDisable(unsigned long ulBase, unsigned long ulIntFlags);\r
+extern unsigned long TimerIntStatus(unsigned long ulBase, tBoolean bMasked);\r
+extern void TimerIntClear(unsigned long ulBase, unsigned long ulIntFlags);\r
+extern void TimerQuiesce(unsigned long ulBase);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __TIMER_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// adc.h - ADC headers for using the ADC driver functions.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __ADC_H__\r
+#define __ADC_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to ADCSequenceConfigure as the ulTrigger\r
+// parameter.\r
+//\r
+//*****************************************************************************\r
+#define ADC_TRIGGER_PROCESSOR 0x00000000 // Processor event\r
+#define ADC_TRIGGER_COMP0 0x00000001 // Analog comparator 0 event\r
+#define ADC_TRIGGER_COMP1 0x00000002 // Analog comparator 1 event\r
+#define ADC_TRIGGER_COMP2 0x00000003 // Analog comparator 2 event\r
+#define ADC_TRIGGER_EXTERNAL 0x00000004 // External event\r
+#define ADC_TRIGGER_TIMER 0x00000005 // Timer event\r
+#define ADC_TRIGGER_PWM0 0x00000006 // PWM0 event\r
+#define ADC_TRIGGER_PWM1 0x00000007 // PWM1 event\r
+#define ADC_TRIGGER_PWM2 0x00000008 // PWM2 event\r
+#define ADC_TRIGGER_ALWAYS 0x0000000F // Always event\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to ADCSequenceStepConfigure as the ulConfig\r
+// parameter.\r
+//\r
+//*****************************************************************************\r
+#define ADC_CTL_TS 0x00000080 // Temperature sensor select\r
+#define ADC_CTL_IE 0x00000040 // Interrupt enable\r
+#define ADC_CTL_END 0x00000020 // Sequence end select\r
+#define ADC_CTL_D 0x00000010 // Differential select\r
+#define ADC_CTL_CH0 0x00000000 // Input channel 0\r
+#define ADC_CTL_CH1 0x00000001 // Input channel 1\r
+#define ADC_CTL_CH2 0x00000002 // Input channel 2\r
+#define ADC_CTL_CH3 0x00000003 // Input channel 3\r
+#define ADC_CTL_CH4 0x00000004 // Input channel 4\r
+#define ADC_CTL_CH5 0x00000005 // Input channel 5\r
+#define ADC_CTL_CH6 0x00000006 // Input channel 6\r
+#define ADC_CTL_CH7 0x00000007 // Input channel 7\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+extern void ADCIntRegister(unsigned long ulBase, unsigned long ulSequenceNum,\r
+ void (*pfnHandler)(void));\r
+extern void ADCIntUnregister(unsigned long ulBase,\r
+ unsigned long ulSequenceNum);\r
+extern void ADCIntDisable(unsigned long ulBase, unsigned long ulSequenceNum);\r
+extern void ADCIntEnable(unsigned long ulBase, unsigned long ulSequenceNum);\r
+extern unsigned long ADCIntStatus(unsigned long ulBase,\r
+ unsigned long ulSequenceNum,\r
+ tBoolean bMasked);\r
+extern void ADCIntClear(unsigned long ulBase, unsigned long ulSequenceNum);\r
+extern void ADCSequenceEnable(unsigned long ulBase,\r
+ unsigned long ulSequenceNum);\r
+extern void ADCSequenceDisable(unsigned long ulBase,\r
+ unsigned long ulSequenceNum);\r
+extern void ADCSequenceConfigure(unsigned long ulBase,\r
+ unsigned long ulSequenceNum,\r
+ unsigned long ulTrigger,\r
+ unsigned long ulPriority);\r
+extern void ADCSequenceStepConfigure(unsigned long ulBase,\r
+ unsigned long ulSequenceNum,\r
+ unsigned long ulStep,\r
+ unsigned long ulConfig);\r
+extern long ADCSequenceOverflow(unsigned long ulBase,\r
+ unsigned long ulSequenceNum);\r
+extern void ADCSequenceOverflowClear(unsigned long ulBase,\r
+ unsigned long ulSequenceNum);\r
+extern long ADCSequenceUnderflow(unsigned long ulBase,\r
+ unsigned long ulSequenceNum);\r
+extern void ADCSequenceUnderflowClear(unsigned long ulBase,\r
+ unsigned long ulSequenceNum);\r
+extern long ADCSequenceDataGet(unsigned long ulBase,\r
+ unsigned long ulSequenceNum,\r
+ unsigned long *pulBuffer);\r
+extern void ADCProcessorTrigger(unsigned long ulBase,\r
+ unsigned long ulSequenceNum);\r
+extern void ADCSoftwareOversampleConfigure(unsigned long ulBase,\r
+ unsigned long ulSequenceNum,\r
+ unsigned long ulFactor);\r
+extern void ADCSoftwareOversampleStepConfigure(unsigned long ulBase,\r
+ unsigned long ulSequenceNum,\r
+ unsigned long ulStep,\r
+ unsigned long ulConfig);\r
+extern void ADCSoftwareOversampleDataGet(unsigned long ulBase,\r
+ unsigned long ulSequenceNum,\r
+ unsigned long *pulBuffer,\r
+ unsigned long ulCount);\r
+extern void ADCHardwareOversampleConfigure(unsigned long ulBase,\r
+ unsigned long ulFactor);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __ADC_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// can.h - Defines and Macros for the CAN controller.\r
+//\r
+// Copyright (c) 2006-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __CAN_H__\r
+#define __CAN_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! \addtogroup can_api\r
+//! @{\r
+//\r
+//*****************************************************************************\r
+\r
+//*****************************************************************************\r
+//\r
+// Miscellaneous defines for Message ID Types\r
+//\r
+//*****************************************************************************\r
+\r
+//*****************************************************************************\r
+//\r
+//! These are the flags used by the tCANMsgObject variable when calling the\r
+//! the CANMessageSet() and CANMessageGet() APIs.\r
+//\r
+//*****************************************************************************\r
+typedef enum\r
+{\r
+ //\r
+ //! This indicates that transmit interrupts should be enabled, or are\r
+ //! enabled.\r
+ //\r
+ MSG_OBJ_TX_INT_ENABLE = 0x00000001,\r
+\r
+ //\r
+ //! This indicates that receive interrupts should be enabled or are\r
+ //! enabled.\r
+ //\r
+ MSG_OBJ_RX_INT_ENABLE = 0x00000002,\r
+\r
+ //\r
+ //! This indicates that a message object will use or is using an extended\r
+ //! identifier.\r
+ //\r
+ MSG_OBJ_EXTENDED_ID = 0x00000004,\r
+\r
+ //\r
+ //! This indicates that a message object will use or is using filtering\r
+ //! based on the object's message Identifier.\r
+ //\r
+ MSG_OBJ_USE_ID_FILTER = 0x00000008,\r
+\r
+ //\r
+ //! This indicates that new data was available in the message object.\r
+ //\r
+ MSG_OBJ_NEW_DATA = 0x00000080,\r
+\r
+ //\r
+ //! This indicates that data was lost since this message object was last\r
+ //! read.\r
+ //\r
+ MSG_OBJ_DATA_LOST = 0x00000100,\r
+\r
+ //\r
+ //! This indicates that a message object will use or is using filtering\r
+ //! based on the direction of the transfer. If the direction filtering is\r
+ //! used then ID filtering must also be enabled.\r
+ //\r
+ MSG_OBJ_USE_DIR_FILTER = (0x00000010 | MSG_OBJ_USE_ID_FILTER),\r
+\r
+ //\r
+ //! This indicates that a message object will use or is using message\r
+ //! identifier filtering based of the the extended identifier.\r
+ //! If the extended identifier filtering is used then ID filtering must\r
+ //! also be enabled.\r
+ //\r
+ MSG_OBJ_USE_EXT_FILTER = (0x00000020 | MSG_OBJ_USE_ID_FILTER),\r
+\r
+ //\r
+ //! This indicates that a message object is a remote frame.\r
+ //\r
+ MSG_OBJ_REMOTE_FRAME = 0x00000040,\r
+\r
+ //\r
+ //! This indicates that a message object has no flags set.\r
+ //\r
+ MSG_OBJ_NO_FLAGS = 0x00000000\r
+}\r
+tCANObjFlags;\r
+\r
+//*****************************************************************************\r
+//\r
+//! This define is used with the #tCANObjFlags enumerated values to allow\r
+//! checking only status flags and not configuration flags.\r
+//\r
+//*****************************************************************************\r
+#define MSG_OBJ_STATUS_MASK (MSG_OBJ_NEW_DATA | MSG_OBJ_DATA_LOST)\r
+\r
+//*****************************************************************************\r
+//\r
+//! This structure used for encapsulating all the items associated with a CAN\r
+//! message object in the CAN controller.\r
+//\r
+//*****************************************************************************\r
+typedef struct\r
+{\r
+ //\r
+ //! The CAN message identifier used for 11 or 29 bit identifiers.\r
+ //\r
+ unsigned long ulMsgID;\r
+\r
+ //\r
+ //! The message identifier mask used when identifier filtering is enabled.\r
+ //\r
+ unsigned long ulMsgIDMask;\r
+\r
+ //\r
+ //! This value holds various status flags and settings specified by\r
+ //! tCANObjFlags.\r
+ //\r
+ unsigned long ulFlags;\r
+\r
+ //\r
+ //! This value is the number of bytes of data in the message object.\r
+ //\r
+ unsigned long ulMsgLen;\r
+\r
+ //\r
+ //! This is a pointer to the message object's data.\r
+ //\r
+ unsigned char *pucMsgData;\r
+}\r
+tCANMsgObject;\r
+\r
+//*****************************************************************************\r
+//\r
+//! This structure is used for encapsulating the values associated with setting\r
+//! up the bit timing for a CAN controller. The structure is used when calling\r
+//! the CANGetBitTiming and CANSetBitTiming functions.\r
+//\r
+//*****************************************************************************\r
+typedef struct\r
+{\r
+ //\r
+ //! This value holds the sum of the Synchronization, Propagation, and Phase\r
+ //! Buffer 1 segments, measured in time quanta. The valid values for this\r
+ //! setting range from 2 to 16.\r
+ //\r
+ unsigned int uSyncPropPhase1Seg;\r
+\r
+ //\r
+ //! This value holds the Phase Buffer 2 segment in time quanta. The valid\r
+ //! values for this setting range from 1 to 8.\r
+ //\r
+ unsigned int uPhase2Seg;\r
+\r
+ //\r
+ //! This value holds the Resynchronization Jump Width in time quanta. The\r
+ //! valid values for this setting range from 1 to 4.\r
+ //\r
+ unsigned int uSJW;\r
+\r
+ //\r
+ //! This value holds the CAN_CLK divider used to determine time quanta.\r
+ //! The valid values for this setting range from 1 to 1023.\r
+ //\r
+ unsigned int uQuantumPrescaler;\r
+\r
+}\r
+tCANBitClkParms;\r
+\r
+//*****************************************************************************\r
+//\r
+//! This data type is used to identify the interrupt status register. This is\r
+//! used when calling the a CANIntStatus() function.\r
+//\r
+//*****************************************************************************\r
+typedef enum\r
+{\r
+ //\r
+ //! Read the CAN interrupt status information.\r
+ //\r
+ CAN_INT_STS_CAUSE,\r
+\r
+ //\r
+ //! Read a message object's interrupt status.\r
+ //\r
+ CAN_INT_STS_OBJECT\r
+}\r
+tCANIntStsReg;\r
+\r
+//*****************************************************************************\r
+//\r
+//! This data type is used to identify which of the several status registers\r
+//! to read when calling the CANStatusGet() function.\r
+//\r
+//*****************************************************************************\r
+typedef enum\r
+{\r
+ //\r
+ //! Read the full CAN controller status.\r
+ //\r
+ CAN_STS_CONTROL,\r
+\r
+ //\r
+ //! Read the full 32 bit mask of message objects with a transmit request\r
+ //! set.\r
+ //\r
+ CAN_STS_TXREQUEST,\r
+\r
+ //\r
+ //! Read the full 32 bit mask of message objects with a new data available.\r
+ //\r
+ CAN_STS_NEWDAT,\r
+\r
+ //\r
+ //! Read the full 32 bit mask of message objects that are enabled.\r
+ //\r
+ CAN_STS_MSGVAL\r
+}\r
+tCANStsReg;\r
+\r
+//*****************************************************************************\r
+//\r
+//! These definitions are used to specify interrupt sources to CANIntEnable()\r
+//! and CANIntDisable().\r
+//\r
+//*****************************************************************************\r
+typedef enum\r
+{\r
+ //\r
+ //! This flag is used to allow a CAN controller to generate error\r
+ //! interrupts.\r
+ //\r
+ CAN_INT_ERROR = 0x00000008,\r
+\r
+ //\r
+ //! This flag is used to allow a CAN controller to generate status\r
+ //! interrupts.\r
+ //\r
+ CAN_INT_STATUS = 0x00000004,\r
+\r
+ //\r
+ //! This flag is used to allow a CAN controller to generate any CAN\r
+ //! interrupts. If this is not set then no interrupts will be generated by\r
+ //! the CAN controller.\r
+ //\r
+ CAN_INT_MASTER = 0x00000002\r
+}\r
+tCANIntFlags;\r
+\r
+//*****************************************************************************\r
+//\r
+//! This definition is used to determine the type of message object that will\r
+//! be set up via a call to the CANMessageSet() API.\r
+//\r
+//*****************************************************************************\r
+typedef enum\r
+{\r
+ //\r
+ //! Transmit message object.\r
+ //\r
+ MSG_OBJ_TYPE_TX,\r
+\r
+ //\r
+ //! Transmit remote request message object\r
+ //\r
+ MSG_OBJ_TYPE_TX_REMOTE,\r
+\r
+ //\r
+ //! Receive message object.\r
+ //\r
+ MSG_OBJ_TYPE_RX,\r
+\r
+ //\r
+ //! Receive remote request message object.\r
+ //\r
+ MSG_OBJ_TYPE_RX_REMOTE,\r
+\r
+ //\r
+ //! Remote frame receive remote, with auto-transmit message object.\r
+ //\r
+ MSG_OBJ_TYPE_RXTX_REMOTE\r
+}\r
+tMsgObjType;\r
+\r
+//*****************************************************************************\r
+//\r
+//! The following enumeration contains all error or status indicators that\r
+//! can be returned when calling the CANStatusGet() API.\r
+//\r
+//*****************************************************************************\r
+typedef enum\r
+{\r
+ //\r
+ //! CAN controller has entered a Bus Off state.\r
+ //\r
+ CAN_STATUS_BUS_OFF = 0x00000080,\r
+\r
+ //\r
+ //! CAN controller error level has reached warning level.\r
+ //\r
+ CAN_STATUS_EWARN = 0x00000040,\r
+\r
+ //\r
+ //! CAN controller error level has reached error passive level.\r
+ //\r
+ CAN_STATUS_EPASS = 0x00000020,\r
+\r
+ //\r
+ //! A message was received successfully since the last read of this status.\r
+ //\r
+ CAN_STATUS_RXOK = 0x00000010,\r
+\r
+ //\r
+ //! A message was transmitted successfully since the last read of this\r
+ //! status.\r
+ //\r
+ CAN_STATUS_TXOK = 0x00000008,\r
+\r
+ //\r
+ //! This is the mask for the last error code field.\r
+ //\r
+ CAN_STATUS_LEC_MSK = 0x00000007,\r
+\r
+ //\r
+ //! There was no error.\r
+ //\r
+ CAN_STATUS_LEC_NONE = 0x00000000,\r
+\r
+ //\r
+ //! A bit stuffing error has occurred.\r
+ //\r
+ CAN_STATUS_LEC_STUFF = 0x00000001,\r
+\r
+ //\r
+ //! A formatting error has occurred.\r
+ //\r
+ CAN_STATUS_LEC_FORM = 0x00000002,\r
+\r
+ //\r
+ //! An acknowledge error has occurred.\r
+ //\r
+ CAN_STATUS_LEC_ACK = 0x00000003,\r
+\r
+ //\r
+ //! The bus remained a bit level of 1 for longer than is allowed.\r
+ //\r
+ CAN_STATUS_LEC_BIT1 = 0x00000004,\r
+\r
+ //\r
+ //! The bus remained a bit level of 0 for longer than is allowed.\r
+ //\r
+ CAN_STATUS_LEC_BIT0 = 0x00000005,\r
+\r
+ //\r
+ //! A CRC error has occurred.\r
+ //\r
+ CAN_STATUS_LEC_CRC = 0x00000006,\r
+\r
+ //\r
+ //! This is the mask for the CAN Last Error Code (LEC).\r
+ //\r
+ CAN_STATUS_LEC_MASK = 0x00000007\r
+}\r
+tCANStatusCtrl;\r
+\r
+//*****************************************************************************\r
+//\r
+// API Function prototypes\r
+//\r
+//*****************************************************************************\r
+extern void CANInit(unsigned long ulBase);\r
+extern void CANEnable(unsigned long ulBase);\r
+extern void CANDisable(unsigned long ulBase);\r
+extern void CANSetBitTiming(unsigned long ulBase, tCANBitClkParms *pClkParms);\r
+extern void CANGetBitTiming(unsigned long ulBase, tCANBitClkParms *pClkParms);\r
+extern unsigned long CANReadReg(unsigned long ulRegAddress);\r
+extern void CANWriteReg(unsigned long ulRegAddress, unsigned long ulRegValue);\r
+extern void CANMessageSet(unsigned long ulBase, unsigned long ulObjID,\r
+ tCANMsgObject *pMsgObject, tMsgObjType eMsgType);\r
+extern void CANMessageGet(unsigned long ulBase, unsigned long ulObjID,\r
+ tCANMsgObject *pMsgObject, tBoolean bClrPendingInt);\r
+extern unsigned long CANStatusGet(unsigned long ulBase, tCANStsReg eStatusReg);\r
+extern void CANMessageClear(unsigned long ulBase, unsigned long ulObjID);\r
+extern void CANIntRegister(unsigned long ulBase, void (*pfnHandler)(void));\r
+extern void CANIntEnable(unsigned long ulBase, unsigned long ulIntFlags);\r
+extern void CANIntDisable(unsigned long ulBase, unsigned long ulIntFlags);\r
+extern void CANIntClear(unsigned long ulBase, unsigned long ulIntClr);\r
+extern unsigned long CANIntStatus(unsigned long ulBase,\r
+ tCANIntStsReg eIntStsReg);\r
+extern tBoolean CANRetryGet(unsigned long ulBase);\r
+extern void CANRetrySet(unsigned long ulBase, tBoolean bAutoRetry);\r
+extern tBoolean CANErrCntrGet(unsigned long ulBase, unsigned long *pulRxCount,\r
+ unsigned long *pulTxCount);\r
+extern long CANGetIntNumber(unsigned long ulBase);\r
+extern void CANReadDataReg(unsigned char *pucData, unsigned long *pulRegister,\r
+ int iSize);\r
+extern void CANWriteDataReg(unsigned char *pucData, unsigned long *pulRegister,\r
+ int iSize);\r
+\r
+//*****************************************************************************\r
+//\r
+// Close the Doxygen group.\r
+//! @}\r
+//\r
+//*****************************************************************************\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __CAN_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// comp.h - Prototypes for the analog comparator driver.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __COMP_H__\r
+#define __COMP_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to ComparatorConfigure() as the ulConfig\r
+// parameter. For each group (i.e. COMP_TRIG_xxx, COMP_INT_xxx, etc.), one of\r
+// the values may be selected and ORed together will values from the other\r
+// groups.\r
+//\r
+//*****************************************************************************\r
+#define COMP_TRIG_NONE 0x00000000 // No ADC trigger\r
+#define COMP_TRIG_HIGH 0x00000880 // Trigger when high\r
+#define COMP_TRIG_LOW 0x00000800 // Trigger when low\r
+#define COMP_TRIG_FALL 0x00000820 // Trigger on falling edge\r
+#define COMP_TRIG_RISE 0x00000840 // Trigger on rising edge\r
+#define COMP_TRIG_BOTH 0x00000860 // Trigger on both edges\r
+#define COMP_INT_HIGH 0x00000010 // Interrupt when high\r
+#define COMP_INT_LOW 0x00000000 // Interrupt when low\r
+#define COMP_INT_FALL 0x00000004 // Interrupt on falling edge\r
+#define COMP_INT_RISE 0x00000008 // Interrupt on rising edge\r
+#define COMP_INT_BOTH 0x0000000C // Interrupt on both edges\r
+#define COMP_ASRCP_PIN 0x00000000 // Dedicated Comp+ pin\r
+#define COMP_ASRCP_PIN0 0x00000200 // Comp0+ pin\r
+#define COMP_ASRCP_REF 0x00000400 // Internal voltage reference\r
+#ifndef DEPRECATED\r
+#define COMP_OUTPUT_NONE 0x00000000 // No comparator output\r
+#endif\r
+#define COMP_OUTPUT_NORMAL 0x00000000 // Comparator output normal\r
+#define COMP_OUTPUT_INVERT 0x00000002 // Comparator output inverted\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to ComparatorSetRef() as the ulRef parameter.\r
+//\r
+//*****************************************************************************\r
+#define COMP_REF_OFF 0x00000000 // Turn off the internal reference\r
+#define COMP_REF_0V 0x00000300 // Internal reference of 0V\r
+#define COMP_REF_0_1375V 0x00000301 // Internal reference of 0.1375V\r
+#define COMP_REF_0_275V 0x00000302 // Internal reference of 0.275V\r
+#define COMP_REF_0_4125V 0x00000303 // Internal reference of 0.4125V\r
+#define COMP_REF_0_55V 0x00000304 // Internal reference of 0.55V\r
+#define COMP_REF_0_6875V 0x00000305 // Internal reference of 0.6875V\r
+#define COMP_REF_0_825V 0x00000306 // Internal reference of 0.825V\r
+#define COMP_REF_0_928125V 0x00000201 // Internal reference of 0.928125V\r
+#define COMP_REF_0_9625V 0x00000307 // Internal reference of 0.9625V\r
+#define COMP_REF_1_03125V 0x00000202 // Internal reference of 1.03125V\r
+#define COMP_REF_1_134375V 0x00000203 // Internal reference of 1.134375V\r
+#define COMP_REF_1_1V 0x00000308 // Internal reference of 1.1V\r
+#define COMP_REF_1_2375V 0x00000309 // Internal reference of 1.2375V\r
+#define COMP_REF_1_340625V 0x00000205 // Internal reference of 1.340625V\r
+#define COMP_REF_1_375V 0x0000030A // Internal reference of 1.375V\r
+#define COMP_REF_1_44375V 0x00000206 // Internal reference of 1.44375V\r
+#define COMP_REF_1_5125V 0x0000030B // Internal reference of 1.5125V\r
+#define COMP_REF_1_546875V 0x00000207 // Internal reference of 1.546875V\r
+#define COMP_REF_1_65V 0x0000030C // Internal reference of 1.65V\r
+#define COMP_REF_1_753125V 0x00000209 // Internal reference of 1.753125V\r
+#define COMP_REF_1_7875V 0x0000030D // Internal reference of 1.7875V\r
+#define COMP_REF_1_85625V 0x0000020A // Internal reference of 1.85625V\r
+#define COMP_REF_1_925V 0x0000030E // Internal reference of 1.925V\r
+#define COMP_REF_1_959375V 0x0000020B // Internal reference of 1.959375V\r
+#define COMP_REF_2_0625V 0x0000030F // Internal reference of 2.0625V\r
+#define COMP_REF_2_165625V 0x0000020D // Internal reference of 2.165625V\r
+#define COMP_REF_2_26875V 0x0000020E // Internal reference of 2.26875V\r
+#define COMP_REF_2_371875V 0x0000020F // Internal reference of 2.371875V\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+extern void ComparatorConfigure(unsigned long ulBase, unsigned long ulComp,\r
+ unsigned long ulConfig);\r
+extern void ComparatorRefSet(unsigned long ulBase, unsigned long ulRef);\r
+extern tBoolean ComparatorValueGet(unsigned long ulBase, unsigned long ulComp);\r
+extern void ComparatorIntRegister(unsigned long ulBase, unsigned long ulComp,\r
+ void (*pfnHandler)(void));\r
+extern void ComparatorIntUnregister(unsigned long ulBase,\r
+ unsigned long ulComp);\r
+extern void ComparatorIntEnable(unsigned long ulBase, unsigned long ulComp);\r
+extern void ComparatorIntDisable(unsigned long ulBase, unsigned long ulComp);\r
+extern tBoolean ComparatorIntStatus(unsigned long ulBase, unsigned long ulComp,\r
+ tBoolean bMasked);\r
+extern void ComparatorIntClear(unsigned long ulBase, unsigned long ulComp);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __COMP_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// cpu.h - Prototypes for the CPU instruction wrapper functions.\r
+//\r
+// Copyright (c) 2006-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __CPU_H__\r
+#define __CPU_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes.\r
+//\r
+//*****************************************************************************\r
+extern void CPUcpsid(void);\r
+extern void CPUcpsie(void);\r
+extern void CPUwfi(void);\r
+\r
+#endif // __CPU_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// debug.h - Macros for assisting debug of the driver library.\r
+//\r
+// Copyright (c) 2006-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __DEBUG_H__\r
+#define __DEBUG_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototype for the function that is called when an invalid argument is passed\r
+// to an API. This is only used when doing a DEBUG build.\r
+//\r
+//*****************************************************************************\r
+extern void __error__(char *pcFilename, unsigned long ulLine);\r
+\r
+//*****************************************************************************\r
+//\r
+// The ASSERT macro, which does the actual assertion checking. Typically, this\r
+// will be for procedure arguments.\r
+//\r
+//*****************************************************************************\r
+#ifdef DEBUG\r
+#define ASSERT(expr) { \\r
+ if(!(expr)) \\r
+ { \\r
+ __error__(__FILE__, __LINE__); \\r
+ } \\r
+ }\r
+#else\r
+#define ASSERT(expr)\r
+#endif\r
+\r
+#endif // __DEBUG_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// ethernet.h - Defines and Macros for the ethernet module.\r
+//\r
+// Copyright (c) 2006-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __ETHERNET_H__\r
+#define __ETHERNET_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to EthernetConfigSet as the ulConfig value, and\r
+// returned from EthernetConfigGet.\r
+//\r
+//*****************************************************************************\r
+#define ETH_CFG_RX_BADCRCDIS 0x000800 // Disable RX BAD CRC Packets\r
+#define ETH_CFG_RX_PRMSEN 0x000400 // Enable RX Promiscuous\r
+#define ETH_CFG_RX_AMULEN 0x000200 // Enable RX Multicast\r
+#define ETH_CFG_TX_DPLXEN 0x000010 // Enable TX Duplex Mode\r
+#define ETH_CFG_TX_CRCEN 0x000004 // Enable TX CRC Generation\r
+#define ETH_CFG_TX_PADEN 0x000002 // Enable TX Padding\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to EthernetIntEnable, EthernetIntDisable, and\r
+// EthernetIntClear as the ulIntFlags parameter, and returned from\r
+// EthernetIntStatus.\r
+//\r
+//*****************************************************************************\r
+#define ETH_INT_PHY 0x040 // PHY Event/Interrupt\r
+#define ETH_INT_MDIO 0x020 // Management Transaction\r
+#define ETH_INT_RXER 0x010 // RX Error\r
+#define ETH_INT_RXOF 0x008 // RX FIFO Overrun\r
+#define ETH_INT_TX 0x004 // TX Complete\r
+#define ETH_INT_TXER 0x002 // TX Error\r
+#define ETH_INT_RX 0x001 // RX Complete\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define values that can be passed as register addresses to\r
+// EthernetPHYRead and EthernetPHYWrite.\r
+//\r
+//*****************************************************************************\r
+#define PHY_MR0 0 // Control\r
+#define PHY_MR1 1 // Status\r
+#define PHY_MR2 2 // PHY Identifier 1\r
+#define PHY_MR3 3 // PHY Identifier 2\r
+#define PHY_MR4 4 // Auto-Neg. Advertisement\r
+#define PHY_MR5 5 // Auto-Neg. Link Partner Ability\r
+#define PHY_MR6 6 // Auto-Neg. Expansion\r
+ // 7-15 Reserved/Not Implemented\r
+#define PHY_MR16 16 // Vendor Specific\r
+#define PHY_MR17 17 // Interrupt Control/Status\r
+#define PHY_MR18 18 // Diagnostic Register\r
+#define PHY_MR19 19 // Transceiver Control\r
+ // 20-22 Reserved\r
+#define PHY_MR23 23 // LED Configuration Register\r
+#define PHY_MR24 24 // MDI/MDIX Control Register\r
+ // 25-31 Reserved/Not Implemented\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define bit fields in the ETH_MR0 register\r
+//\r
+//*****************************************************************************\r
+#define PHY_MR0_RESET 0x8000 // Reset the PHY\r
+#define PHY_MR0_LOOPBK 0x4000 // TXD to RXD Loopback\r
+#define PHY_MR0_SPEEDSL 0x2000 // Speed Selection\r
+#define PHY_MR0_SPEEDSL_10 0x0000 // Speed Selection 10BASE-T\r
+#define PHY_MR0_SPEEDSL_100 0x2000 // Speed Selection 100BASE-T\r
+#define PHY_MR0_ANEGEN 0x1000 // Auto-Negotiation Enable\r
+#define PHY_MR0_PWRDN 0x0800 // Power Down\r
+#define PHY_MR0_RANEG 0x0200 // Restart Auto-Negotiation\r
+#define PHY_MR0_DUPLEX 0x0100 // Enable full duplex\r
+#define PHY_MR0_DUPLEX_HALF 0x0000 // Enable half duplex mode\r
+#define PHY_MR0_DUPLEX_FULL 0x0100 // Enable full duplex mode\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define bit fields in the ETH_MR1 register\r
+//\r
+//*****************************************************************************\r
+#define PHY_MR1_ANEGC 0x0020 // Auto-Negotiate Complete\r
+#define PHY_MR1_RFAULT 0x0010 // Remove Fault Detected\r
+#define PHY_MR1_LINK 0x0004 // Link Established\r
+#define PHY_MR1_JAB 0x0002 // Jabber Condition Detected\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define bit fields in the ETH_MR17 register\r
+//\r
+//*****************************************************************************\r
+#define PHY_MR17_RXER_IE 0x4000 // Enable Receive Error Interrupt\r
+#define PHY_MR17_LSCHG_IE 0x0400 // Enable Link Status Change Int.\r
+#define PHY_MR17_ANEGCOMP_IE 0x0100 // Enable Auto-Negotiate Cmpl. Int.\r
+#define PHY_MR17_RXER_INT 0x0040 // Receive Error Interrupt\r
+#define PHY_MR17_LSCHG_INT 0x0004 // Link Status Change Interrupt\r
+#define PHY_MR17_ANEGCOMP_INT 0x0001 // Auto-Negotiate Complete Int.\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define bit fields in the ETH_MR18 register\r
+//\r
+//*****************************************************************************\r
+#define PHY_MR18_ANEGF 0x1000 // Auto-Negotiate Failed\r
+#define PHY_MR18_DPLX 0x0800 // Duplex Mode Negotiated\r
+#define PHY_MR18_DPLX_HALF 0x0000 // Half Duplex Mode Negotiated\r
+#define PHY_MR18_DPLX_FULL 0x0800 // Full Duplex Mode Negotiated\r
+#define PHY_MR18_RATE 0x0400 // Rate Negotiated\r
+#define PHY_MR18_RATE_10 0x0000 // Rate Negotiated is 10BASE-T\r
+#define PHY_MR18_RATE_100 0x0400 // Rate Negotiated is 100BASE-TX\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define bit fields in the ETH_MR23 register\r
+//\r
+//*****************************************************************************\r
+#define PHY_MR23_LED1 0x00f0 // LED1 Configuration\r
+#define PHY_MR23_LED1_LINK 0x0000 // LED1 is Link Status\r
+#define PHY_MR23_LED1_RXTX 0x0010 // LED1 is RX or TX Activity\r
+#define PHY_MR23_LED1_TX 0x0020 // LED1 is TX Activity\r
+#define PHY_MR23_LED1_RX 0x0030 // LED1 is RX Activity\r
+#define PHY_MR23_LED1_COL 0x0040 // LED1 is RX Activity\r
+#define PHY_MR23_LED1_100 0x0050 // LED1 is RX Activity\r
+#define PHY_MR23_LED1_10 0x0060 // LED1 is RX Activity\r
+#define PHY_MR23_LED1_DUPLEX 0x0070 // LED1 is RX Activity\r
+#define PHY_MR23_LED1_LINKACT 0x0080 // LED1 is Link Status + Activity\r
+#define PHY_MR23_LED0 0x000f // LED0 Configuration\r
+#define PHY_MR23_LED0_LINK 0x0000 // LED0 is Link Status\r
+#define PHY_MR23_LED0_RXTX 0x0001 // LED0 is RX or TX Activity\r
+#define PHY_MR23_LED0_TX 0x0002 // LED0 is TX Activity\r
+#define PHY_MR23_LED0_RX 0x0003 // LED0 is RX Activity\r
+#define PHY_MR23_LED0_COL 0x0004 // LED0 is RX Activity\r
+#define PHY_MR23_LED0_100 0x0005 // LED0 is RX Activity\r
+#define PHY_MR23_LED0_10 0x0006 // LED0 is RX Activity\r
+#define PHY_MR23_LED0_DUPLEX 0x0007 // LED0 is RX Activity\r
+#define PHY_MR23_LED0_LINKACT 0x0008 // LED0 is Link Status + Activity\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define bit fields in the ETH_MR24 register\r
+//\r
+//*****************************************************************************\r
+#define PHY_MR24_MDIX 0x0020 // Auto-Switching Configuration\r
+#define PHY_MR24_MDIX_NORMAL 0x0000 // Auto-Switching in passthrough\r
+#define PHY_MR23_MDIX_CROSSOVER 0x0020 // Auto-Switching in crossover\r
+\r
+//*****************************************************************************\r
+//\r
+// Helper Macros for Ethernet Processing\r
+//\r
+//*****************************************************************************\r
+//\r
+// htonl/ntohl - big endian/little endian byte swapping macros for\r
+// 32-bit (long) values\r
+//\r
+//*****************************************************************************\r
+#ifndef htonl\r
+ #define htonl(a) \\r
+ ((((a) >> 24) & 0x000000ff) | \\r
+ (((a) >> 8) & 0x0000ff00) | \\r
+ (((a) << 8) & 0x00ff0000) | \\r
+ (((a) << 24) & 0xff000000))\r
+#endif\r
+\r
+#ifndef ntohl\r
+ #define ntohl(a) htonl((a))\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// htons/ntohs - big endian/little endian byte swapping macros for\r
+// 16-bit (short) values\r
+//\r
+//*****************************************************************************\r
+#ifndef htons\r
+ #define htons(a) \\r
+ ((((a) >> 8) & 0x00ff) | \\r
+ (((a) << 8) & 0xff00))\r
+#endif\r
+\r
+#ifndef ntohs\r
+ #define ntohs(a) htons((a))\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// API Function prototypes\r
+//\r
+//*****************************************************************************\r
+extern void EthernetInit(unsigned long ulBase);\r
+extern void EthernetConfigSet(unsigned long ulBase, unsigned long ulConfig);\r
+extern unsigned long EthernetConfigGet(unsigned long ulBase);\r
+extern void EthernetMACAddrSet(unsigned long ulBase,\r
+ unsigned char *pucMACAddr);\r
+extern void EthernetMACAddrGet(unsigned long ulBase,\r
+ unsigned char *pucMACAddr);\r
+extern void EthernetEnable(unsigned long ulBase);\r
+extern void EthernetDisable(unsigned long ulBase);\r
+extern tBoolean EthernetPacketAvail(unsigned long ulBase);\r
+extern tBoolean EthernetSpaceAvail(unsigned long ulBase);\r
+extern long EthernetPacketNonBlockingGet(unsigned long ulBase,\r
+ unsigned char *pucBuf,\r
+ long lBufLen);\r
+extern long EthernetPacketGet(unsigned long ulBase, unsigned char *pucBuf,\r
+ long lBufLen);\r
+extern long EthernetPacketNonBlockingPut(unsigned long ulBase,\r
+ unsigned char *pucBuf,\r
+ long lBufLen);\r
+extern long EthernetPacketPut(unsigned long ulBase, unsigned char *pucBuf,\r
+ long lBufLen);\r
+extern void EthernetIntRegister(unsigned long ulBase,\r
+ void (*pfnHandler)(void));\r
+extern void EthernetIntUnregister(unsigned long ulBase);\r
+extern void EthernetIntEnable(unsigned long ulBase, unsigned long ulIntFlags);\r
+extern void EthernetIntDisable(unsigned long ulBase, unsigned long ulIntFlags);\r
+extern unsigned long EthernetIntStatus(unsigned long ulBase, tBoolean bMasked);\r
+extern void EthernetIntClear(unsigned long ulBase, unsigned long ulIntFlags);\r
+extern void EthernetPHYWrite(unsigned long ulBase, unsigned char ucRegAddr,\r
+ unsigned long ulData);\r
+extern unsigned long EthernetPHYRead(unsigned long ulBase,\r
+ unsigned char ucRegAddr);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __ETHERNET_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// gpio.h - Defines and Macros for GPIO API.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __GPIO_H__\r
+#define __GPIO_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// The following values define the bit field for the ucPins argument to several\r
+// of the APIs.\r
+//\r
+//*****************************************************************************\r
+#define GPIO_PIN_0 0x00000001 // GPIO pin 0\r
+#define GPIO_PIN_1 0x00000002 // GPIO pin 1\r
+#define GPIO_PIN_2 0x00000004 // GPIO pin 2\r
+#define GPIO_PIN_3 0x00000008 // GPIO pin 3\r
+#define GPIO_PIN_4 0x00000010 // GPIO pin 4\r
+#define GPIO_PIN_5 0x00000020 // GPIO pin 5\r
+#define GPIO_PIN_6 0x00000040 // GPIO pin 6\r
+#define GPIO_PIN_7 0x00000080 // GPIO pin 7\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to GPIODirModeSet as the ulPinIO parameter, and\r
+// returned from GPIODirModeGet.\r
+//\r
+//*****************************************************************************\r
+#define GPIO_DIR_MODE_IN 0x00000000 // Pin is a GPIO input\r
+#define GPIO_DIR_MODE_OUT 0x00000001 // Pin is a GPIO output\r
+#define GPIO_DIR_MODE_HW 0x00000002 // Pin is a peripheral function\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to GPIOIntTypeSet as the ulIntType parameter, and\r
+// returned from GPIOIntTypeGet.\r
+//\r
+//*****************************************************************************\r
+#define GPIO_FALLING_EDGE 0x00000000 // Interrupt on falling edge\r
+#define GPIO_RISING_EDGE 0x00000004 // Interrupt on rising edge\r
+#define GPIO_BOTH_EDGES 0x00000001 // Interrupt on both edges\r
+#define GPIO_LOW_LEVEL 0x00000002 // Interrupt on low level\r
+#define GPIO_HIGH_LEVEL 0x00000007 // Interrupt on high level\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to GPIOPadConfigSet as the ulStrength parameter,\r
+// and returned by GPIOPadConfigGet in the *pulStrength parameter.\r
+//\r
+//*****************************************************************************\r
+#define GPIO_STRENGTH_2MA 0x00000001 // 2mA drive strength\r
+#define GPIO_STRENGTH_4MA 0x00000002 // 4mA drive strength\r
+#define GPIO_STRENGTH_8MA 0x00000004 // 8mA drive strength\r
+#define GPIO_STRENGTH_8MA_SC 0x0000000C // 8mA drive with slew rate control\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to GPIOPadConfigSet as the ulPadType parameter,\r
+// and returned by GPIOPadConfigGet in the *pulPadType parameter.\r
+//\r
+//*****************************************************************************\r
+#define GPIO_PIN_TYPE_STD 0x00000008 // Push-pull\r
+#define GPIO_PIN_TYPE_STD_WPU 0x0000000A // Push-pull with weak pull-up\r
+#define GPIO_PIN_TYPE_STD_WPD 0x0000000C // Push-pull with weak pull-down\r
+#define GPIO_PIN_TYPE_OD 0x00000009 // Open-drain\r
+#define GPIO_PIN_TYPE_OD_WPU 0x0000000B // Open-drain with weak pull-up\r
+#define GPIO_PIN_TYPE_OD_WPD 0x0000000D // Open-drain with weak pull-down\r
+#define GPIO_PIN_TYPE_ANALOG 0x00000000 // Analog comparator\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+extern void GPIODirModeSet(unsigned long ulPort, unsigned char ucPins,\r
+ unsigned long ulPinIO);\r
+extern unsigned long GPIODirModeGet(unsigned long ulPort, unsigned char ucPin);\r
+extern void GPIOIntTypeSet(unsigned long ulPort, unsigned char ucPins,\r
+ unsigned long ulIntType);\r
+extern unsigned long GPIOIntTypeGet(unsigned long ulPort, unsigned char ucPin);\r
+extern void GPIOPadConfigSet(unsigned long ulPort, unsigned char ucPins,\r
+ unsigned long ulStrength,\r
+ unsigned long ulPadType);\r
+extern void GPIOPadConfigGet(unsigned long ulPort, unsigned char ucPin,\r
+ unsigned long *pulStrength,\r
+ unsigned long *pulPadType);\r
+extern void GPIOPinIntEnable(unsigned long ulPort, unsigned char ucPins);\r
+extern void GPIOPinIntDisable(unsigned long ulPort, unsigned char ucPins);\r
+extern long GPIOPinIntStatus(unsigned long ulPort, tBoolean bMasked);\r
+extern void GPIOPinIntClear(unsigned long ulPort, unsigned char ucPins);\r
+extern void GPIOPortIntRegister(unsigned long ulPort,\r
+ void (*pfIntHandler)(void));\r
+extern void GPIOPortIntUnregister(unsigned long ulPort);\r
+extern long GPIOPinRead(unsigned long ulPort, unsigned char ucPins);\r
+extern void GPIOPinWrite(unsigned long ulPort, unsigned char ucPins,\r
+ unsigned char ucVal);\r
+extern void GPIOPinTypeComparator(unsigned long ulPort, unsigned char ucPins);\r
+extern void GPIOPinTypeI2C(unsigned long ulPort, unsigned char ucPins);\r
+extern void GPIOPinTypePWM(unsigned long ulPort, unsigned char ucPins);\r
+extern void GPIOPinTypeQEI(unsigned long ulPort, unsigned char ucPins);\r
+extern void GPIOPinTypeSSI(unsigned long ulPort, unsigned char ucPins);\r
+extern void GPIOPinTypeTimer(unsigned long ulPort, unsigned char ucPins);\r
+extern void GPIOPinTypeUART(unsigned long ulPort, unsigned char ucPins);\r
+extern void GPIOPinTypeCAN(unsigned long ulPort, unsigned char ucPins);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __GPIO_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hibernate.h - API definition for the Hibernation module.\r
+//\r
+// Copyright (c) 2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HIBERNATE_H__\r
+#define __HIBERNATE_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Macros needed for selecting the clock source for HibernateClockSelect()\r
+//\r
+//*****************************************************************************\r
+#define HIBERNATE_CLOCK_SEL_RAW 0x04\r
+#define HIBERNATE_CLOCK_SEL_DIV128 0x00\r
+\r
+//*****************************************************************************\r
+//\r
+// Macros need to configure wake events for HibernateWakeSet()\r
+//\r
+//*****************************************************************************\r
+#define HIBERNATE_WAKE_PIN 0x10\r
+#define HIBERNATE_WAKE_RTC 0x08\r
+\r
+//*****************************************************************************\r
+//\r
+// Macros needed to configure low battery detect for HibernateLowBatSet()\r
+//\r
+//*****************************************************************************\r
+#define HIBERNATE_LOW_BAT_DETECT 0x20\r
+#define HIBERNATE_LOW_BAT_ABORT 0xA0\r
+\r
+//*****************************************************************************\r
+//\r
+// Macros defining interrupt source bits for the interrupt functions.\r
+//\r
+//*****************************************************************************\r
+#define HIBERNATE_INT_PIN_WAKE 0x08\r
+#define HIBERNATE_INT_LOW_BAT 0x04\r
+#define HIBERNATE_INT_RTC_MATCH_0 0x01\r
+#define HIBERNATE_INT_RTC_MATCH_1 0x02\r
+\r
+//*****************************************************************************\r
+//\r
+// API Function prototypes\r
+//\r
+//*****************************************************************************\r
+extern void HibernateEnable(void);\r
+extern void HibernateDisable(void);\r
+extern void HibernateClockSelect(unsigned long ulClockInput);\r
+extern void HibernateRTCEnable(void);\r
+extern void HibernateRTCDisable(void);\r
+extern void HibernateWakeSet(unsigned long ulWakeFlags);\r
+extern unsigned long HibernateWakeGet(void);\r
+extern void HibernateLowBatSet(unsigned long ulLowBatFlags);\r
+extern unsigned long HibernateLowBatGet(void);\r
+extern void HibernateRTCSet(unsigned long ulRTCValue);\r
+extern unsigned long HibernateRTCGet(void);\r
+extern void HibernateRTCMatch0Set(unsigned long ulMatch);\r
+extern unsigned long HibernateRTCMatch0Get(void);\r
+extern void HibernateRTCMatch1Set(unsigned long ulMatch);\r
+extern unsigned long HibernateRTCMatch1Get(void);\r
+extern void HibernateRTCTrimSet(unsigned long ulTrim);\r
+extern unsigned long HibernateRTCTrimGet(void);\r
+extern void HibernateDataSet(unsigned long *pulData, unsigned long ulCount);\r
+extern void HibernateDataGet(unsigned long *pulData, unsigned long ulCount);\r
+extern void HibernateRequest(void);\r
+extern void HibernateIntEnable(unsigned long ulIntFlags);\r
+extern void HibernateIntDisable(unsigned long ulIntFlags);\r
+extern void HibernateIntRegister(void (*pfnHandler)(void));\r
+extern void HibernateIntUnregister(void);\r
+extern unsigned long HibernateIntStatus(tBoolean bMasked);\r
+extern void HibernateIntClear(unsigned long ulIntFlags);\r
+extern unsigned int HibernateIsActive(void);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __HIBERNATE_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_adc.h - Macros used when accessing the ADC hardware.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_ADC_H__\r
+#define __HW_ADC_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the offsets of the ADC registers.\r
+//\r
+//*****************************************************************************\r
+#define ADC_O_ACTSS 0x00000000 // Active sample register\r
+#define ADC_O_RIS 0x00000004 // Raw interrupt status register\r
+#define ADC_O_IM 0x00000008 // Interrupt mask register\r
+#define ADC_O_ISC 0x0000000C // Interrupt status/clear register\r
+#define ADC_O_OSTAT 0x00000010 // Overflow status register\r
+#define ADC_O_EMUX 0x00000014 // Event multiplexer select reg.\r
+#define ADC_O_USTAT 0x00000018 // Underflow status register\r
+#define ADC_O_SSPRI 0x00000020 // Channel priority register\r
+#define ADC_O_PSSI 0x00000028 // Processor sample initiate reg.\r
+#define ADC_O_SAC 0x00000030 // Sample Averaging Control reg.\r
+#define ADC_O_SSMUX0 0x00000040 // Multiplexer select 0 register\r
+#define ADC_O_SSCTL0 0x00000044 // Sample sequence control 0 reg.\r
+#define ADC_O_SSFIFO0 0x00000048 // Result FIFO 0 register\r
+#define ADC_O_SSFSTAT0 0x0000004C // FIFO 0 status register\r
+#define ADC_O_SSMUX1 0x00000060 // Multiplexer select 1 register\r
+#define ADC_O_SSCTL1 0x00000064 // Sample sequence control 1 reg.\r
+#define ADC_O_SSFIFO1 0x00000068 // Result FIFO 1 register\r
+#define ADC_O_SSFSTAT1 0x0000006C // FIFO 1 status register\r
+#define ADC_O_SSMUX2 0x00000080 // Multiplexer select 2 register\r
+#define ADC_O_SSCTL2 0x00000084 // Sample sequence control 2 reg.\r
+#define ADC_O_SSFIFO2 0x00000088 // Result FIFO 2 register\r
+#define ADC_O_SSFSTAT2 0x0000008C // FIFO 2 status register\r
+#define ADC_O_SSMUX3 0x000000A0 // Multiplexer select 3 register\r
+#define ADC_O_SSCTL3 0x000000A4 // Sample sequence control 3 reg.\r
+#define ADC_O_SSFIFO3 0x000000A8 // Result FIFO 3 register\r
+#define ADC_O_SSFSTAT3 0x000000AC // FIFO 3 status register\r
+#define ADC_O_TMLB 0x00000100 // Test mode loopback register\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the offsets of the ADC sequence registers.\r
+//\r
+//*****************************************************************************\r
+#define ADC_O_SEQ 0x00000040 // Offset to the first sequence\r
+#define ADC_O_SEQ_STEP 0x00000020 // Increment to the next sequence\r
+#define ADC_O_X_SSMUX 0x00000000 // Multiplexer select register\r
+#define ADC_O_X_SSCTL 0x00000004 // Sample sequence control register\r
+#define ADC_O_X_SSFIFO 0x00000008 // Result FIFO register\r
+#define ADC_O_X_SSFSTAT 0x0000000C // FIFO status register\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the ADC_ACTSS register.\r
+//\r
+//*****************************************************************************\r
+#define ADC_ACTSS_ASEN3 0x00000008 // Sample sequence 3 enable\r
+#define ADC_ACTSS_ASEN2 0x00000004 // Sample sequence 2 enable\r
+#define ADC_ACTSS_ASEN1 0x00000002 // Sample sequence 1 enable\r
+#define ADC_ACTSS_ASEN0 0x00000001 // Sample sequence 0 enable\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the ADC_RIS register.\r
+//\r
+//*****************************************************************************\r
+#define ADC_RIS_INR3 0x00000008 // Sample sequence 3 interrupt\r
+#define ADC_RIS_INR2 0x00000004 // Sample sequence 2 interrupt\r
+#define ADC_RIS_INR1 0x00000002 // Sample sequence 1 interrupt\r
+#define ADC_RIS_INR0 0x00000001 // Sample sequence 0 interrupt\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the ADC_IM register.\r
+//\r
+//*****************************************************************************\r
+#define ADC_IM_MASK3 0x00000008 // Sample sequence 3 mask\r
+#define ADC_IM_MASK2 0x00000004 // Sample sequence 2 mask\r
+#define ADC_IM_MASK1 0x00000002 // Sample sequence 1 mask\r
+#define ADC_IM_MASK0 0x00000001 // Sample sequence 0 mask\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the ADC_ISC register.\r
+//\r
+//*****************************************************************************\r
+#define ADC_ISC_IN3 0x00000008 // Sample sequence 3 interrupt\r
+#define ADC_ISC_IN2 0x00000004 // Sample sequence 2 interrupt\r
+#define ADC_ISC_IN1 0x00000002 // Sample sequence 1 interrupt\r
+#define ADC_ISC_IN0 0x00000001 // Sample sequence 0 interrupt\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the ADC_OSTAT register.\r
+//\r
+//*****************************************************************************\r
+#define ADC_OSTAT_OV3 0x00000008 // Sample sequence 3 overflow\r
+#define ADC_OSTAT_OV2 0x00000004 // Sample sequence 2 overflow\r
+#define ADC_OSTAT_OV1 0x00000002 // Sample sequence 1 overflow\r
+#define ADC_OSTAT_OV0 0x00000001 // Sample sequence 0 overflow\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the ADC_EMUX register.\r
+//\r
+//*****************************************************************************\r
+#define ADC_EMUX_EM3_MASK 0x0000F000 // Event mux 3 mask\r
+#define ADC_EMUX_EM3_PROCESSOR 0x00000000 // Processor event\r
+#define ADC_EMUX_EM3_COMP0 0x00001000 // Analog comparator 0 event\r
+#define ADC_EMUX_EM3_COMP1 0x00002000 // Analog comparator 1 event\r
+#define ADC_EMUX_EM3_COMP2 0x00003000 // Analog comparator 2 event\r
+#define ADC_EMUX_EM3_EXTERNAL 0x00004000 // External event\r
+#define ADC_EMUX_EM3_TIMER 0x00005000 // Timer event\r
+#define ADC_EMUX_EM3_PWM0 0x00006000 // PWM0 event\r
+#define ADC_EMUX_EM3_PWM1 0x00007000 // PWM1 event\r
+#define ADC_EMUX_EM3_PWM2 0x00008000 // PWM2 event\r
+#define ADC_EMUX_EM3_ALWAYS 0x0000F000 // Always event\r
+#define ADC_EMUX_EM2_MASK 0x00000F00 // Event mux 2 mask\r
+#define ADC_EMUX_EM2_PROCESSOR 0x00000000 // Processor event\r
+#define ADC_EMUX_EM2_COMP0 0x00000100 // Analog comparator 0 event\r
+#define ADC_EMUX_EM2_COMP1 0x00000200 // Analog comparator 1 event\r
+#define ADC_EMUX_EM2_COMP2 0x00000300 // Analog comparator 2 event\r
+#define ADC_EMUX_EM2_EXTERNAL 0x00000400 // External event\r
+#define ADC_EMUX_EM2_TIMER 0x00000500 // Timer event\r
+#define ADC_EMUX_EM2_PWM0 0x00000600 // PWM0 event\r
+#define ADC_EMUX_EM2_PWM1 0x00000700 // PWM1 event\r
+#define ADC_EMUX_EM2_PWM2 0x00000800 // PWM2 event\r
+#define ADC_EMUX_EM2_ALWAYS 0x00000F00 // Always event\r
+#define ADC_EMUX_EM1_MASK 0x000000F0 // Event mux 1 mask\r
+#define ADC_EMUX_EM1_PROCESSOR 0x00000000 // Processor event\r
+#define ADC_EMUX_EM1_COMP0 0x00000010 // Analog comparator 0 event\r
+#define ADC_EMUX_EM1_COMP1 0x00000020 // Analog comparator 1 event\r
+#define ADC_EMUX_EM1_COMP2 0x00000030 // Analog comparator 2 event\r
+#define ADC_EMUX_EM1_EXTERNAL 0x00000040 // External event\r
+#define ADC_EMUX_EM1_TIMER 0x00000050 // Timer event\r
+#define ADC_EMUX_EM1_PWM0 0x00000060 // PWM0 event\r
+#define ADC_EMUX_EM1_PWM1 0x00000070 // PWM1 event\r
+#define ADC_EMUX_EM1_PWM2 0x00000080 // PWM2 event\r
+#define ADC_EMUX_EM1_ALWAYS 0x000000F0 // Always event\r
+#define ADC_EMUX_EM0_MASK 0x0000000F // Event mux 0 mask\r
+#define ADC_EMUX_EM0_PROCESSOR 0x00000000 // Processor event\r
+#define ADC_EMUX_EM0_COMP0 0x00000001 // Analog comparator 0 event\r
+#define ADC_EMUX_EM0_COMP1 0x00000002 // Analog comparator 1 event\r
+#define ADC_EMUX_EM0_COMP2 0x00000003 // Analog comparator 2 event\r
+#define ADC_EMUX_EM0_EXTERNAL 0x00000004 // External event\r
+#define ADC_EMUX_EM0_TIMER 0x00000005 // Timer event\r
+#define ADC_EMUX_EM0_PWM0 0x00000006 // PWM0 event\r
+#define ADC_EMUX_EM0_PWM1 0x00000007 // PWM1 event\r
+#define ADC_EMUX_EM0_PWM2 0x00000008 // PWM2 event\r
+#define ADC_EMUX_EM0_ALWAYS 0x0000000F // Always event\r
+#define ADC_EMUX_EM0_SHIFT 0 // The shift for the first event\r
+#define ADC_EMUX_EM1_SHIFT 4 // The shift for the second event\r
+#define ADC_EMUX_EM2_SHIFT 8 // The shift for the third event\r
+#define ADC_EMUX_EM3_SHIFT 12 // The shift for the fourth event\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the ADC_USTAT register.\r
+//\r
+//*****************************************************************************\r
+#define ADC_USTAT_UV3 0x00000008 // Sample sequence 3 underflow\r
+#define ADC_USTAT_UV2 0x00000004 // Sample sequence 2 underflow\r
+#define ADC_USTAT_UV1 0x00000002 // Sample sequence 1 underflow\r
+#define ADC_USTAT_UV0 0x00000001 // Sample sequence 0 underflow\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the ADC_SSPRI register.\r
+//\r
+//*****************************************************************************\r
+#define ADC_SSPRI_SS3_MASK 0x00003000 // Sequencer 3 priority mask\r
+#define ADC_SSPRI_SS3_1ST 0x00000000 // First priority\r
+#define ADC_SSPRI_SS3_2ND 0x00001000 // Second priority\r
+#define ADC_SSPRI_SS3_3RD 0x00002000 // Third priority\r
+#define ADC_SSPRI_SS3_4TH 0x00003000 // Fourth priority\r
+#define ADC_SSPRI_SS2_MASK 0x00000300 // Sequencer 2 priority mask\r
+#define ADC_SSPRI_SS2_1ST 0x00000000 // First priority\r
+#define ADC_SSPRI_SS2_2ND 0x00000100 // Second priority\r
+#define ADC_SSPRI_SS2_3RD 0x00000200 // Third priority\r
+#define ADC_SSPRI_SS2_4TH 0x00000300 // Fourth priority\r
+#define ADC_SSPRI_SS1_MASK 0x00000030 // Sequencer 1 priority mask\r
+#define ADC_SSPRI_SS1_1ST 0x00000000 // First priority\r
+#define ADC_SSPRI_SS1_2ND 0x00000010 // Second priority\r
+#define ADC_SSPRI_SS1_3RD 0x00000020 // Third priority\r
+#define ADC_SSPRI_SS1_4TH 0x00000030 // Fourth priority\r
+#define ADC_SSPRI_SS0_MASK 0x00000003 // Sequencer 0 priority mask\r
+#define ADC_SSPRI_SS0_1ST 0x00000000 // First priority\r
+#define ADC_SSPRI_SS0_2ND 0x00000001 // Second priority\r
+#define ADC_SSPRI_SS0_3RD 0x00000002 // Third priority\r
+#define ADC_SSPRI_SS0_4TH 0x00000003 // Fourth priority\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the ADC_PSSI register.\r
+//\r
+//*****************************************************************************\r
+#define ADC_PSSI_SS3 0x00000008 // Trigger sample sequencer 3\r
+#define ADC_PSSI_SS2 0x00000004 // Trigger sample sequencer 2\r
+#define ADC_PSSI_SS1 0x00000002 // Trigger sample sequencer 1\r
+#define ADC_PSSI_SS0 0x00000001 // Trigger sample sequencer 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the ADC_SAC register.\r
+//\r
+//*****************************************************************************\r
+#define ADC_SAC_AVG_OFF 0x00000000 // No hardware oversampling\r
+#define ADC_SAC_AVG_2X 0x00000001 // 2x hardware oversampling\r
+#define ADC_SAC_AVG_4X 0x00000002 // 4x hardware oversampling\r
+#define ADC_SAC_AVG_8X 0x00000003 // 8x hardware oversampling\r
+#define ADC_SAC_AVG_16X 0x00000004 // 16x hardware oversampling\r
+#define ADC_SAC_AVG_32X 0x00000005 // 32x hardware oversampling\r
+#define ADC_SAC_AVG_64X 0x00000006 // 64x hardware oversampling\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the ADC_SSMUX0, ADC_SSMUX1,\r
+// ADC_SSMUX2, and ADC_SSMUX3 registers. Not all fields are present in all\r
+// registers.\r
+//\r
+//*****************************************************************************\r
+#define ADC_SSMUX_MUX7_MASK 0x70000000 // 8th mux select mask\r
+#define ADC_SSMUX_MUX6_MASK 0x07000000 // 7th mux select mask\r
+#define ADC_SSMUX_MUX5_MASK 0x00700000 // 6th mux select mask\r
+#define ADC_SSMUX_MUX4_MASK 0x00070000 // 5th mux select mask\r
+#define ADC_SSMUX_MUX3_MASK 0x00007000 // 4th mux select mask\r
+#define ADC_SSMUX_MUX2_MASK 0x00000700 // 3rd mux select mask\r
+#define ADC_SSMUX_MUX1_MASK 0x00000070 // 2nd mux select mask\r
+#define ADC_SSMUX_MUX0_MASK 0x00000007 // 1st mux select mask\r
+#define ADC_SSMUX_MUX7_SHIFT 28\r
+#define ADC_SSMUX_MUX6_SHIFT 24\r
+#define ADC_SSMUX_MUX5_SHIFT 20\r
+#define ADC_SSMUX_MUX4_SHIFT 16\r
+#define ADC_SSMUX_MUX3_SHIFT 12\r
+#define ADC_SSMUX_MUX2_SHIFT 8\r
+#define ADC_SSMUX_MUX1_SHIFT 4\r
+#define ADC_SSMUX_MUX0_SHIFT 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the ADC_SSCTL0, ADC_SSCTL1,\r
+// ADC_SSCTL2, and ADC_SSCTL3 registers. Not all fields are present in all\r
+// registers.\r
+//\r
+//*****************************************************************************\r
+#define ADC_SSCTL_TS7 0x80000000 // 8th temperature sensor select\r
+#define ADC_SSCTL_IE7 0x40000000 // 8th interrupt enable\r
+#define ADC_SSCTL_END7 0x20000000 // 8th sequence end select\r
+#define ADC_SSCTL_D7 0x10000000 // 8th differential select\r
+#define ADC_SSCTL_TS6 0x08000000 // 7th temperature sensor select\r
+#define ADC_SSCTL_IE6 0x04000000 // 7th interrupt enable\r
+#define ADC_SSCTL_END6 0x02000000 // 7th sequence end select\r
+#define ADC_SSCTL_D6 0x01000000 // 7th differential select\r
+#define ADC_SSCTL_TS5 0x00800000 // 6th temperature sensor select\r
+#define ADC_SSCTL_IE5 0x00400000 // 6th interrupt enable\r
+#define ADC_SSCTL_END5 0x00200000 // 6th sequence end select\r
+#define ADC_SSCTL_D5 0x00100000 // 6th differential select\r
+#define ADC_SSCTL_TS4 0x00080000 // 5th temperature sensor select\r
+#define ADC_SSCTL_IE4 0x00040000 // 5th interrupt enable\r
+#define ADC_SSCTL_END4 0x00020000 // 5th sequence end select\r
+#define ADC_SSCTL_D4 0x00010000 // 5th differential select\r
+#define ADC_SSCTL_TS3 0x00008000 // 4th temperature sensor select\r
+#define ADC_SSCTL_IE3 0x00004000 // 4th interrupt enable\r
+#define ADC_SSCTL_END3 0x00002000 // 4th sequence end select\r
+#define ADC_SSCTL_D3 0x00001000 // 4th differential select\r
+#define ADC_SSCTL_TS2 0x00000800 // 3rd temperature sensor select\r
+#define ADC_SSCTL_IE2 0x00000400 // 3rd interrupt enable\r
+#define ADC_SSCTL_END2 0x00000200 // 3rd sequence end select\r
+#define ADC_SSCTL_D2 0x00000100 // 3rd differential select\r
+#define ADC_SSCTL_TS1 0x00000080 // 2nd temperature sensor select\r
+#define ADC_SSCTL_IE1 0x00000040 // 2nd interrupt enable\r
+#define ADC_SSCTL_END1 0x00000020 // 2nd sequence end select\r
+#define ADC_SSCTL_D1 0x00000010 // 2nd differential select\r
+#define ADC_SSCTL_TS0 0x00000008 // 1st temperature sensor select\r
+#define ADC_SSCTL_IE0 0x00000004 // 1st interrupt enable\r
+#define ADC_SSCTL_END0 0x00000002 // 1st sequence end select\r
+#define ADC_SSCTL_D0 0x00000001 // 1st differential select\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the ADC_SSFIFO0, ADC_SSFIFO1,\r
+// ADC_SSFIFO2, and ADC_SSFIFO3 registers.\r
+//\r
+//*****************************************************************************\r
+#define ADC_SSFIFO_DATA_MASK 0x000003FF // Sample data\r
+#define ADC_SSFIFO_DATA_SHIFT 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the ADC_SSFSTAT0, ADC_SSFSTAT1,\r
+// ADC_SSFSTAT2, and ADC_SSFSTAT3 registers.\r
+//\r
+//*****************************************************************************\r
+#define ADC_SSFSTAT_FULL 0x00001000 // FIFO is full\r
+#define ADC_SSFSTAT_EMPTY 0x00000100 // FIFO is empty\r
+#define ADC_SSFSTAT_HPTR 0x000000F0 // FIFO head pointer\r
+#define ADC_SSFSTAT_TPTR 0x0000000F // FIFO tail pointer\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the ADC_TMLB register.\r
+//\r
+//*****************************************************************************\r
+#define ADC_TMLB_LB 0x00000001 // Loopback control signals\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the loopback ADC data.\r
+//\r
+//*****************************************************************************\r
+#define ADC_LB_CNT_MASK 0x000003C0 // Sample counter mask\r
+#define ADC_LB_CONT 0x00000020 // Continuation sample\r
+#define ADC_LB_DIFF 0x00000010 // Differential sample\r
+#define ADC_LB_TS 0x00000008 // Temperature sensor sample\r
+#define ADC_LB_MUX_MASK 0x00000007 // Input channel number mask\r
+#define ADC_LB_CNT_SHIFT 6 // Sample counter shift\r
+#define ADC_LB_MUX_SHIFT 0 // Input channel number shift\r
+\r
+#endif // __HW_ADC_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_can.h - Defines and macros used when accessing the can.\r
+//\r
+// Copyright (c) 2006-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_CAN_H__\r
+#define __HW_CAN_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the offsets of the can registers.\r
+//\r
+//*****************************************************************************\r
+#define CAN_O_CTL 0x00000000 // Control register\r
+#define CAN_O_STS 0x00000004 // Status register\r
+#define CAN_O_ERR 0x00000008 // Error register\r
+#define CAN_O_BIT 0x0000000C // Bit Timing register\r
+#define CAN_O_INT 0x00000010 // Interrupt register\r
+#define CAN_O_TST 0x00000014 // Test register\r
+#define CAN_O_BRPE 0x00000018 // Baud Rate Prescaler register\r
+#define CAN_O_IF1CRQ 0x00000020 // Interface 1 Command Request reg.\r
+#define CAN_O_IF1CMSK 0x00000024 // Interface 1 Command Mask reg.\r
+#define CAN_O_IF1MSK1 0x00000028 // Interface 1 Mask 1 register\r
+#define CAN_O_IF1MSK2 0x0000002C // Interface 1 Mask 2 register\r
+#define CAN_O_IF1ARB1 0x00000030 // Interface 1 Arbitration 1 reg.\r
+#define CAN_O_IF1ARB2 0x00000034 // Interface 1 Arbitration 2 reg.\r
+#define CAN_O_IF1MCTL 0x00000038 // Interface 1 Message Control reg.\r
+#define CAN_O_IF1DA1 0x0000003C // Interface 1 DataA 1 register\r
+#define CAN_O_IF1DA2 0x00000040 // Interface 1 DataA 2 register\r
+#define CAN_O_IF1DB1 0x00000044 // Interface 1 DataB 1 register\r
+#define CAN_O_IF1DB2 0x00000048 // Interface 1 DataB 2 register\r
+#define CAN_O_IF2CRQ 0x00000080 // Interface 2 Command Request reg.\r
+#define CAN_O_IF2CMSK 0x00000084 // Interface 2 Command Mask reg.\r
+#define CAN_O_IF2MSK1 0x00000088 // Interface 2 Mask 1 register\r
+#define CAN_O_IF2MSK2 0x0000008C // Interface 2 Mask 2 register\r
+#define CAN_O_IF2ARB1 0x00000090 // Interface 2 Arbitration 1 reg.\r
+#define CAN_O_IF2ARB2 0x00000094 // Interface 2 Arbitration 2 reg.\r
+#define CAN_O_IF2MCTL 0x00000098 // Interface 2 Message Control reg.\r
+#define CAN_O_IF2DA1 0x0000009C // Interface 2 DataA 1 register\r
+#define CAN_O_IF2DA2 0x000000A0 // Interface 2 DataA 2 register\r
+#define CAN_O_IF2DB1 0x000000A4 // Interface 2 DataB 1 register\r
+#define CAN_O_IF2DB2 0x000000A8 // Interface 2 DataB 2 register\r
+#define CAN_O_TXRQ1 0x00000100 // Transmission Request 1 register\r
+#define CAN_O_TXRQ2 0x00000104 // Transmission Request 2 register\r
+#define CAN_O_NWDA1 0x00000120 // New Data 1 register\r
+#define CAN_O_NWDA2 0x00000124 // New Data 2 register\r
+#define CAN_O_MSGINT1 0x00000140 // Intr. Pending in Msg Obj 1 reg.\r
+#define CAN_O_MSGINT2 0x00000144 // Intr. Pending in Msg Obj 2 reg.\r
+#define CAN_O_MSGVAL1 0x00000160 // Message Valid in Msg Obj 1 reg.\r
+#define CAN_O_MSGVAL2 0x00000164 // Message Valid in Msg Obj 2 reg.\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the reset values of the can registers.\r
+//\r
+//*****************************************************************************\r
+#define CAN_RV_CTL 0x00000001\r
+#define CAN_RV_STS 0x00000000\r
+#define CAN_RV_ERR 0x00000000\r
+#define CAN_RV_BIT 0x00002301\r
+#define CAN_RV_INT 0x00000000\r
+#define CAN_RV_TST 0x00000000\r
+#define CAN_RV_BRPE 0x00000000\r
+#define CAN_RV_IF1CRQ 0x00000001\r
+#define CAN_RV_IF1CMSK 0x00000000\r
+#define CAN_RV_IF1MSK1 0x0000FFFF\r
+#define CAN_RV_IF1MSK2 0x0000FFFF\r
+#define CAN_RV_IF1ARB1 0x00000000\r
+#define CAN_RV_IF1ARB2 0x00000000\r
+#define CAN_RV_IF1MCTL 0x00000000\r
+#define CAN_RV_IF1DA1 0x00000000\r
+#define CAN_RV_IF1DA2 0x00000000\r
+#define CAN_RV_IF1DB1 0x00000000\r
+#define CAN_RV_IF1DB2 0x00000000\r
+#define CAN_RV_IF2CRQ 0x00000001\r
+#define CAN_RV_IF2CMSK 0x00000000\r
+#define CAN_RV_IF2MSK1 0x0000FFFF\r
+#define CAN_RV_IF2MSK2 0x0000FFFF\r
+#define CAN_RV_IF2ARB1 0x00000000\r
+#define CAN_RV_IF2ARB2 0x00000000\r
+#define CAN_RV_IF2MCTL 0x00000000\r
+#define CAN_RV_IF2DA1 0x00000000\r
+#define CAN_RV_IF2DA2 0x00000000\r
+#define CAN_RV_IF2DB1 0x00000000\r
+#define CAN_RV_IF2DB2 0x00000000\r
+#define CAN_RV_TXRQ1 0x00000000\r
+#define CAN_RV_TXRQ2 0x00000000\r
+#define CAN_RV_NWDA1 0x00000000\r
+#define CAN_RV_NWDA2 0x00000000\r
+#define CAN_RV_MSGINT1 0x00000000\r
+#define CAN_RV_MSGINT2 0x00000000\r
+#define CAN_RV_MSGVAL1 0x00000000\r
+#define CAN_RV_MSGVAL2 0x00000000\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the CAN_CTL register.\r
+//\r
+//*****************************************************************************\r
+#define CAN_CTL_TEST 0x00000080 // Test mode enable\r
+#define CAN_CTL_CCE 0x00000040 // Configuration change enable\r
+#define CAN_CTL_DAR 0x00000020 // Disable automatic retransmission\r
+#define CAN_CTL_EIE 0x00000008 // Error interrupt enable\r
+#define CAN_CTL_SIE 0x00000004 // Status change interrupt enable\r
+#define CAN_CTL_IE 0x00000002 // Module interrupt enable\r
+#define CAN_CTL_INIT 0x00000001 // Initialization\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the CAN_STS register.\r
+//\r
+//*****************************************************************************\r
+#define CAN_STS_BOFF 0x00000080 // Bus Off status\r
+#define CAN_STS_EWARN 0x00000040 // Error Warning status\r
+#define CAN_STS_EPASS 0x00000020 // Error Passive status\r
+#define CAN_STS_RXOK 0x00000010 // Received Message Successful\r
+#define CAN_STS_TXOK 0x00000008 // Transmitted Message Successful\r
+#define CAN_STS_LEC_MSK 0x00000007 // Last Error Code\r
+#define CAN_STS_LEC_NONE 0x00000000 // No error\r
+#define CAN_STS_LEC_STUFF 0x00000001 // Stuff error\r
+#define CAN_STS_LEC_FORM 0x00000002 // Form(at) error\r
+#define CAN_STS_LEC_ACK 0x00000003 // Ack error\r
+#define CAN_STS_LEC_BIT1 0x00000004 // Bit 1 error\r
+#define CAN_STS_LEC_BIT0 0x00000005 // Bit 0 error\r
+#define CAN_STS_LEC_CRC 0x00000006 // CRC error\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the CAN_ERR register.\r
+//\r
+//*****************************************************************************\r
+#define CAN_ERR_RP 0x00008000 // Receive error passive status\r
+#define CAN_ERR_REC_MASK 0x00007F00 // Receive error counter status\r
+#define CAN_ERR_REC_SHIFT 8 // Receive error counter bit pos\r
+#define CAN_ERR_TEC_MASK 0x000000FF // Transmit error counter status\r
+#define CAN_ERR_TEC_SHIFT 0 // Transmit error counter bit pos\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the CAN_BIT register.\r
+//\r
+//*****************************************************************************\r
+#define CAN_BIT_TSEG2 0x00007000 // Time segment after sample point\r
+#define CAN_BIT_TSEG1 0x00000F00 // Time segment before sample point\r
+#define CAN_BIT_SJW 0x000000C0 // (Re)Synchronization jump width\r
+#define CAN_BIT_BRP 0x0000003F // Baud rate prescaler\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the CAN_INT register.\r
+//\r
+//*****************************************************************************\r
+#define CAN_INT_INTID_MSK 0x0000FFFF // Interrupt Identifier\r
+#define CAN_INT_INTID_NONE 0x00000000 // No Interrupt Pending\r
+#define CAN_INT_INTID_STATUS 0x00008000 // Status Interrupt\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the CAN_TST register.\r
+//\r
+//*****************************************************************************\r
+#define CAN_TST_RX 0x00000080 // CAN_RX pin status\r
+#define CAN_TST_TX_MSK 0x00000060 // Overide control of CAN_TX pin\r
+#define CAN_TST_TX_CANCTL 0x00000000 // CAN core controls CAN_TX\r
+#define CAN_TST_TX_SAMPLE 0x00000020 // Sample Point on CAN_TX\r
+#define CAN_TST_TX_DOMINANT 0x00000040 // Dominant value on CAN_TX\r
+#define CAN_TST_TX_RECESSIVE 0x00000060 // Recessive value on CAN_TX\r
+#define CAN_TST_LBACK 0x00000010 // Loop back mode\r
+#define CAN_TST_SILENT 0x00000008 // Silent mode\r
+#define CAN_TST_BASIC 0x00000004 // Basic mode\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the CAN_BRPE register.\r
+//\r
+//*****************************************************************************\r
+#define CAN_BRPE_BRPE 0x0000000F // Baud rate prescaler extension\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the CAN_IF1CRQ and CAN_IF1CRQ\r
+// registers.\r
+// Note: All bits may not be available in all registers\r
+//\r
+//*****************************************************************************\r
+#define CAN_IFCRQ_BUSY 0x00008000 // Busy flag status\r
+#define CAN_IFCRQ_MNUM_MSK 0x0000003F // Message Number\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the CAN_IF1CMSK and CAN_IF2CMSK\r
+// registers.\r
+// Note: All bits may not be available in all registers\r
+//\r
+//*****************************************************************************\r
+#define CAN_IFCMSK_WRNRD 0x00000080 // Write, not Read\r
+#define CAN_IFCMSK_MASK 0x00000040 // Access Mask Bits\r
+#define CAN_IFCMSK_ARB 0x00000020 // Access Arbitration Bits\r
+#define CAN_IFCMSK_CONTROL 0x00000010 // Access Control Bits\r
+#define CAN_IFCMSK_CLRINTPND 0x00000008 // Clear interrupt pending Bit\r
+#define CAN_IFCMSK_TXRQST 0x00000004 // Access Tx request bit (WRNRD=1)\r
+#define CAN_IFCMSK_NEWDAT 0x00000004 // Access New Data bit (WRNRD=0)\r
+#define CAN_IFCMSK_DATAA 0x00000002 // DataA access - bytes 0 to 3\r
+#define CAN_IFCMSK_DATAB 0x00000001 // DataB access - bytes 4 to 7\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the CAN_IF1MSK1 and CAN_IF2MSK1\r
+// registers.\r
+// Note: All bits may not be available in all registers\r
+//\r
+//*****************************************************************************\r
+#define CAN_IFMSK1_MSK 0x0000FFFF // Identifier Mask\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the CAN_IF1MSK2 and CAN_IF2MSK2\r
+// registers.\r
+// Note: All bits may not be available in all registers\r
+//\r
+//*****************************************************************************\r
+#define CAN_IFMSK2_MXTD 0x00008000 // Mask extended identifier\r
+#define CAN_IFMSK2_MDIR 0x00004000 // Mask message direction\r
+#define CAN_IFMSK2_MSK 0x00001FFF // Mask identifier\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the CAN_IF1ARB1 and CAN_IF2ARB1\r
+// registers.\r
+// Note: All bits may not be available in all registers\r
+//\r
+//*****************************************************************************\r
+#define CAN_IFARB1_ID 0x0000FFFF // Identifier\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the CAN_IF1ARB2 and CAN_IF2ARB2\r
+// registers.\r
+// Note: All bits may not be available in all registers\r
+//\r
+//*****************************************************************************\r
+#define CAN_IFARB2_MSGVAL 0x00008000 // Message valid\r
+#define CAN_IFARB2_XTD 0x00004000 // Extended identifier\r
+#define CAN_IFARB2_DIR 0x00002000 // Message direction\r
+#define CAN_IFARB2_ID 0x00001FFF // Message identifier\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the CAN_IF1MCTL and CAN_IF2MCTL\r
+// registers.\r
+// Note: All bits may not be available in all registers\r
+//\r
+//*****************************************************************************\r
+#define CAN_IFMCTL_NEWDAT 0x00008000 // New Data\r
+#define CAN_IFMCTL_MSGLST 0x00004000 // Message lost\r
+#define CAN_IFMCTL_INTPND 0x00002000 // Interrupt pending\r
+#define CAN_IFMCTL_UMASK 0x00001000 // Use acceptance mask\r
+#define CAN_IFMCTL_TXIE 0x00000800 // Transmit interrupt enable\r
+#define CAN_IFMCTL_RXIE 0x00000400 // Receive interrupt enable\r
+#define CAN_IFMCTL_RMTEN 0x00000200 // Remote enable\r
+#define CAN_IFMCTL_TXRQST 0x00000100 // Transmit request\r
+#define CAN_IFMCTL_EOB 0x00000080 // End of buffer\r
+#define CAN_IFMCTL_DLC 0x0000000F // Data length code\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the CAN_IF1DA1 and CAN_IF2DA1\r
+// registers.\r
+// Note: All bits may not be available in all registers\r
+//\r
+//*****************************************************************************\r
+#define CAN_IFDA1_DATA 0x0000FFFF // Data - bytes 1 and 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the CAN_IF1DA2 and CAN_IF2DA2\r
+// registers.\r
+// Note: All bits may not be available in all registers\r
+//\r
+//*****************************************************************************\r
+#define CAN_IFDA2_DATA 0x0000FFFF // Data - bytes 3 and 2\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the CAN_IF1DB1 and CAN_IF2DB1\r
+// registers.\r
+// Note: All bits may not be available in all registers\r
+//\r
+//*****************************************************************************\r
+#define CAN_IFDB1_DATA 0x0000FFFF // Data - bytes 5 and 4\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the CAN_IF1DB2 and CAN_IF2DB2\r
+// registers.\r
+// Note: All bits may not be available in all registers\r
+//\r
+//*****************************************************************************\r
+#define CAN_IFDB2_DATA 0x0000FFFF // Data - bytes 7 and 6\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the CAN_TXRQ1 register.\r
+//\r
+//*****************************************************************************\r
+#define CAN_TXRQ1_TXRQST 0x0000FFFF // Transmission Request Bits\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the CAN_TXRQ2 register.\r
+//\r
+//*****************************************************************************\r
+#define CAN_TXRQ2_TXRQST 0x0000FFFF // Transmission Request Bits\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the CAN_NWDA1 register.\r
+//\r
+//*****************************************************************************\r
+#define CAN_NWDA1_NEWDATA 0x0000FFFF // New Data Bits\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the CAN_NWDA2 register.\r
+//\r
+//*****************************************************************************\r
+#define CAN_NWDA2_NEWDATA 0x0000FFFF // New Data Bits\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the CAN_MSGINT1 register.\r
+//\r
+//*****************************************************************************\r
+#define CAN_MSGINT1_INTPND 0x0000FFFF // Interrupt Pending Bits\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the CAN_MSGINT2 register.\r
+//\r
+//*****************************************************************************\r
+#define CAN_MSGINT2_INTPND 0x0000FFFF // Interrupt Pending Bits\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the CAN_MSGVAL1 register.\r
+//\r
+//*****************************************************************************\r
+#define CAN_MSGVAL1_MSGVAL 0x0000FFFF // Message Valid Bits\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the CAN_MSGVAL2 register.\r
+//\r
+//*****************************************************************************\r
+#define CAN_MSGVAL2_MSGVAL 0x0000FFFF // Message Valid Bits\r
+\r
+#endif // __HW_CAN_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_comp.h - Macros used when accessing the comparator hardware.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_COMP_H__\r
+#define __HW_COMP_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the offsets of the comparator registers.\r
+//\r
+//*****************************************************************************\r
+#define COMP_O_MIS 0x00000000 // Interrupt status register\r
+#define COMP_O_RIS 0x00000004 // Raw interrupt status register\r
+#define COMP_O_INTEN 0x00000008 // Interrupt enable register\r
+#define COMP_O_REFCTL 0x00000010 // Reference voltage control reg.\r
+#define COMP_O_ACSTAT0 0x00000020 // Comp0 status register\r
+#define COMP_O_ACCTL0 0x00000024 // Comp0 control register\r
+#define COMP_O_ACSTAT1 0x00000040 // Comp1 status register\r
+#define COMP_O_ACCTL1 0x00000044 // Comp1 control register\r
+#define COMP_O_ACSTAT2 0x00000060 // Comp2 status register\r
+#define COMP_O_ACCTL2 0x00000064 // Comp2 control register\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the COMP_MIS, COMP_RIS, and\r
+// COMP_INTEN registers.\r
+//\r
+//*****************************************************************************\r
+#define COMP_INT_2 0x00000004 // Comp2 interrupt\r
+#define COMP_INT_1 0x00000002 // Comp1 interrupt\r
+#define COMP_INT_0 0x00000001 // Comp0 interrupt\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the COMP_REFCTL register.\r
+//\r
+//*****************************************************************************\r
+#define COMP_REFCTL_EN 0x00000200 // Reference voltage enable\r
+#define COMP_REFCTL_RNG 0x00000100 // Reference voltage range\r
+#define COMP_REFCTL_VREF_MASK 0x0000000F // Reference voltage select mask\r
+#define COMP_REFCTL_VREF_SHIFT 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the COMP_ACSTAT0, COMP_ACSTAT1, and\r
+// COMP_ACSTAT2 registers.\r
+//\r
+//*****************************************************************************\r
+#define COMP_ACSTAT_OVAL 0x00000002 // Comparator output value\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the COMP_ACCTL0, COMP_ACCTL1, and\r
+// COMP_ACCTL2 registers.\r
+//\r
+//*****************************************************************************\r
+#define COMP_ACCTL_TMASK 0x00000800 // Trigger enable\r
+#define COMP_ACCTL_ASRCP_MASK 0x00000600 // Vin+ source select mask\r
+#define COMP_ACCTL_ASRCP_PIN 0x00000000 // Dedicated Comp+ pin\r
+#define COMP_ACCTL_ASRCP_PIN0 0x00000200 // Comp0+ pin\r
+#define COMP_ACCTL_ASRCP_REF 0x00000400 // Internal voltage reference\r
+#define COMP_ACCTL_ASRCP_RES 0x00000600 // Reserved\r
+#define COMP_ACCTL_OEN 0x00000100 // Comparator output enable\r
+#define COMP_ACCTL_TSVAL 0x00000080 // Trigger polarity select\r
+#define COMP_ACCTL_TSEN_MASK 0x00000060 // Trigger sense mask\r
+#define COMP_ACCTL_TSEN_LEVEL 0x00000000 // Trigger is level sense\r
+#define COMP_ACCTL_TSEN_FALL 0x00000020 // Trigger is falling edge\r
+#define COMP_ACCTL_TSEN_RISE 0x00000040 // Trigger is rising edge\r
+#define COMP_ACCTL_TSEN_BOTH 0x00000060 // Trigger is both edges\r
+#define COMP_ACCTL_ISLVAL 0x00000010 // Interrupt polarity select\r
+#define COMP_ACCTL_ISEN_MASK 0x0000000C // Interrupt sense mask\r
+#define COMP_ACCTL_ISEN_LEVEL 0x00000000 // Interrupt is level sense\r
+#define COMP_ACCTL_ISEN_FALL 0x00000004 // Interrupt is falling edge\r
+#define COMP_ACCTL_ISEN_RISE 0x00000008 // Interrupt is rising edge\r
+#define COMP_ACCTL_ISEN_BOTH 0x0000000C // Interrupt is both edges\r
+#define COMP_ACCTL_CINV 0x00000002 // Comparator output invert\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the reset values for the comparator registers.\r
+//\r
+//*****************************************************************************\r
+#define COMP_RV_MIS 0x00000000 // Interrupt status register\r
+#define COMP_RV_RIS 0x00000000 // Raw interrupt status register\r
+#define COMP_RV_INTEN 0x00000000 // Interrupt enable register\r
+#define COMP_RV_REFCTL 0x00000000 // Reference voltage control reg.\r
+#define COMP_RV_ACSTAT0 0x00000000 // Comp0 status register\r
+#define COMP_RV_ACCTL0 0x00000000 // Comp0 control register\r
+#define COMP_RV_ACSTAT1 0x00000000 // Comp1 status register\r
+#define COMP_RV_ACCTL1 0x00000000 // Comp1 control register\r
+#define COMP_RV_ACSTAT2 0x00000000 // Comp2 status register\r
+#define COMP_RV_ACCTL2 0x00000000 // Comp2 control register\r
+\r
+#endif // __HW_COMP_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_ethernet.h - Macros used when accessing the ethernet hardware.\r
+//\r
+// Copyright (c) 2006-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_ETHERNET_H__\r
+#define __HW_ETHERNET_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the offsets of the MAC registers in the Ethernet\r
+// Controller.\r
+//\r
+//*****************************************************************************\r
+#define MAC_O_IS 0x00000000 // Interrupt Status Register\r
+#define MAC_O_IACK 0x00000000 // Interrupt Acknowledge Register\r
+#define MAC_O_IM 0x00000004 // Interrupt Mask Register\r
+#define MAC_O_RCTL 0x00000008 // Receive Control Register\r
+#define MAC_O_TCTL 0x0000000C // Transmit Control Register\r
+#define MAC_O_DATA 0x00000010 // Data Register\r
+#define MAC_O_IA0 0x00000014 // Individual Address Register 0\r
+#define MAC_O_IA1 0x00000018 // Individual Address Register 1\r
+#define MAC_O_THR 0x0000001C // Threshold Register\r
+#define MAC_O_MCTL 0x00000020 // Management Control Register\r
+#define MAC_O_MDV 0x00000024 // Management Divider Register\r
+#define MAC_O_MADD 0x00000028 // Management Address Register\r
+#define MAC_O_MTXD 0x0000002C // Management Transmit Data Reg\r
+#define MAC_O_MRXD 0x00000030 // Management Receive Data Reg\r
+#define MAC_O_NP 0x00000034 // Number of Packets Register\r
+#define MAC_O_TR 0x00000038 // Transmission Request Register\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the reset values of the MAC registers.\r
+//\r
+//*****************************************************************************\r
+#define MAC_RV_IS 0x00000000\r
+#define MAC_RV_IACK 0x00000000\r
+#define MAC_RV_IM 0x0000007F\r
+#define MAC_RV_RCTL 0x00000008\r
+#define MAC_RV_TCTL 0x00000000\r
+#define MAC_RV_DATA 0x00000000\r
+#define MAC_RV_IA0 0x00000000\r
+#define MAC_RV_IA1 0x00000000\r
+#define MAC_RV_THR 0x0000003F\r
+#define MAC_RV_MCTL 0x00000000\r
+#define MAC_RV_MDV 0x00000080\r
+#define MAC_RV_MADD 0x00000000\r
+#define MAC_RV_MTXD 0x00000000\r
+#define MAC_RV_MRXD 0x00000000\r
+#define MAC_RV_NP 0x00000000\r
+#define MAC_RV_TR 0x00000000\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the MAC_IS register.\r
+//\r
+//*****************************************************************************\r
+#define MAC_IS_PHYINT 0x00000040 // PHY Interrupt\r
+#define MAC_IS_MDINT 0x00000020 // MDI Transaction Complete\r
+#define MAC_IS_RXER 0x00000010 // RX Error\r
+#define MAC_IS_FOV 0x00000008 // RX FIFO Overrun\r
+#define MAC_IS_TXEMP 0x00000004 // TX FIFO Empy\r
+#define MAC_IS_TXER 0x00000002 // TX Error\r
+#define MAC_IS_RXINT 0x00000001 // RX Packet Available\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the MAC_IACK register.\r
+//\r
+//*****************************************************************************\r
+#define MAC_IACK_PHYINT 0x00000040 // Clear PHY Interrupt\r
+#define MAC_IACK_MDINT 0x00000020 // Clear MDI Transaction Complete\r
+#define MAC_IACK_RXER 0x00000010 // Clear RX Error\r
+#define MAC_IACK_FOV 0x00000008 // Clear RX FIFO Overrun\r
+#define MAC_IACK_TXEMP 0x00000004 // Clear TX FIFO Empy\r
+#define MAC_IACK_TXER 0x00000002 // Clear TX Error\r
+#define MAC_IACK_RXINT 0x00000001 // Clear RX Packet Available\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the MAC_IM register.\r
+//\r
+//*****************************************************************************\r
+#define MAC_IM_PHYINTM 0x00000040 // Mask PHY Interrupt\r
+#define MAC_IM_MDINTM 0x00000020 // Mask MDI Transaction Complete\r
+#define MAC_IM_RXERM 0x00000010 // Mask RX Error\r
+#define MAC_IM_FOVM 0x00000008 // Mask RX FIFO Overrun\r
+#define MAC_IM_TXEMPM 0x00000004 // Mask TX FIFO Empy\r
+#define MAC_IM_TXERM 0x00000002 // Mask TX Error\r
+#define MAC_IM_RXINTM 0x00000001 // Mask RX Packet Available\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the MAC_RCTL register.\r
+//\r
+//*****************************************************************************\r
+#define MAC_RCTL_RSTFIFO 0x00000010 // Clear the Receive FIFO\r
+#define MAC_RCTL_BADCRC 0x00000008 // Reject Packets With Bad CRC\r
+#define MAC_RCTL_PRMS 0x00000004 // Enable Promiscuous Mode\r
+#define MAC_RCTL_AMUL 0x00000002 // Enable Multicast Packets\r
+#define MAC_RCTL_RXEN 0x00000001 // Enable Ethernet Receiver\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the MAC_TCTL register.\r
+//\r
+//*****************************************************************************\r
+#define MAC_TCTL_DUPLEX 0x00000010 // Enable Duplex mode\r
+#define MAC_TCTL_CRC 0x00000004 // Enable CRC Generation\r
+#define MAC_TCTL_PADEN 0x00000002 // Enable Automatic Padding\r
+#define MAC_TCTL_TXEN 0x00000001 // Enable Ethernet Transmitter\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the MAC_IA0 register.\r
+//\r
+//*****************************************************************************\r
+#define MAC_IA0_MACOCT4 0xFF000000 // 4th Octet of MAC address\r
+#define MAC_IA0_MACOCT3 0x00FF0000 // 3rd Octet of MAC address\r
+#define MAC_IA0_MACOCT2 0x0000FF00 // 2nd Octet of MAC address\r
+#define MAC_IA0_MACOCT1 0x000000FF // 1st Octet of MAC address\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the MAC_IA1 register.\r
+//\r
+//*****************************************************************************\r
+#define MAC_IA1_MACOCT6 0x0000FF00 // 6th Octet of MAC address\r
+#define MAC_IA1_MACOCT5 0x000000FF // 5th Octet of MAC address\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the MAC_TXTH register.\r
+//\r
+//*****************************************************************************\r
+#define MAC_THR_THRESH 0x0000003F // Transmit Threshold Value\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the MAC_MCTL register.\r
+//\r
+//*****************************************************************************\r
+#define MAC_MCTL_REGADR 0x000000F8 // Address for Next MII Transaction\r
+#define MAC_MCTL_WRITE 0x00000002 // Next MII Transaction is Write\r
+#define MAC_MCTL_START 0x00000001 // Start MII Transaction\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the MAC_MDV register.\r
+//\r
+//*****************************************************************************\r
+#define MAC_MDV_DIV 0x000000FF // Clock Divider for MDC for TX\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the MAC_MTXD register.\r
+//\r
+//*****************************************************************************\r
+#define MAC_MTXD_MDTX 0x0000FFFF // Data for Next MII Transaction\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the MAC_MRXD register.\r
+//\r
+//*****************************************************************************\r
+#define MAC_MRXD_MDRX 0x0000FFFF // Data Read from Last MII Trans.\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the MAC_NP register.\r
+//\r
+//*****************************************************************************\r
+#define MAC_NP_NPR 0x0000003F // Number of RX Frames in FIFO\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the MAC_TXRQ register.\r
+//\r
+//*****************************************************************************\r
+#define MAC_TR_NEWTX 0x00000001 // Start an Ethernet Transmission\r
+\r
+#endif // __HW_ETHERNET_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_flash.h - Macros used when accessing the flash controller.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_FLASH_H__\r
+#define __HW_FLASH_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the offsets of the FLASH registers.\r
+//\r
+//*****************************************************************************\r
+#define FLASH_FMA 0x400FD000 // Memory address register\r
+#define FLASH_FMD 0x400FD004 // Memory data register\r
+#define FLASH_FMC 0x400FD008 // Memory control register\r
+#define FLASH_FCRIS 0x400FD00c // Raw interrupt status register\r
+#define FLASH_FCIM 0x400FD010 // Interrupt mask register\r
+#define FLASH_FCMISC 0x400FD014 // Interrupt status register\r
+#define FLASH_FMPRE 0x400FE130 // FLASH read protect register\r
+#define FLASH_FMPPE 0x400FE134 // FLASH program protect register\r
+#define FLASH_USECRL 0x400FE140 // uSec reload register\r
+#define FLASH_FMPRE0 0x400FE200 // FLASH read protect register 0\r
+#define FLASH_FMPRE1 0x400FE204 // FLASH read protect register 1\r
+#define FLASH_FMPRE2 0x400FE208 // FLASH read protect register 2\r
+#define FLASH_FMPRE3 0x400FE20C // FLASH read protect register 3\r
+#define FLASH_FMPPE0 0x400FE400 // FLASH program protect register 0\r
+#define FLASH_FMPPE1 0x400FE404 // FLASH program protect register 1\r
+#define FLASH_FMPPE2 0x400FE408 // FLASH program protect register 2\r
+#define FLASH_FMPPE3 0x400FE40C // FLASH program protect register 3\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the FLASH_FMC register.\r
+//\r
+//*****************************************************************************\r
+#define FLASH_FMC_WRKEY_MASK 0xFFFF0000 // FLASH write key mask\r
+#define FLASH_FMC_WRKEY 0xA4420000 // FLASH write key\r
+#define FLASH_FMC_COMT 0x00000008 // Commit user register\r
+#define FLASH_FMC_MERASE 0x00000004 // Mass erase FLASH\r
+#define FLASH_FMC_ERASE 0x00000002 // Erase FLASH page\r
+#define FLASH_FMC_WRITE 0x00000001 // Write FLASH word\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the FLASH_FCRIS register.\r
+//\r
+//*****************************************************************************\r
+#define FLASH_FCRIS_PROGRAM 0x00000002 // Programming status\r
+#define FLASH_FCRIS_ACCESS 0x00000001 // Invalid access status\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the FLASH_FCIM register.\r
+//\r
+//*****************************************************************************\r
+#define FLASH_FCIM_PROGRAM 0x00000002 // Programming mask\r
+#define FLASH_FCIM_ACCESS 0x00000001 // Invalid access mask\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the FLASH_FMIS register.\r
+//\r
+//*****************************************************************************\r
+#define FLASH_FCMISC_PROGRAM 0x00000002 // Programming status\r
+#define FLASH_FCMISC_ACCESS 0x00000001 // Invalid access status\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the FLASH_FMPRE and FLASH_FMPPE\r
+// registers.\r
+//\r
+//*****************************************************************************\r
+#define FLASH_FMP_BLOCK_31 0x80000000 // Enable for block 31\r
+#define FLASH_FMP_BLOCK_30 0x40000000 // Enable for block 30\r
+#define FLASH_FMP_BLOCK_29 0x20000000 // Enable for block 29\r
+#define FLASH_FMP_BLOCK_28 0x10000000 // Enable for block 28\r
+#define FLASH_FMP_BLOCK_27 0x08000000 // Enable for block 27\r
+#define FLASH_FMP_BLOCK_26 0x04000000 // Enable for block 26\r
+#define FLASH_FMP_BLOCK_25 0x02000000 // Enable for block 25\r
+#define FLASH_FMP_BLOCK_24 0x01000000 // Enable for block 24\r
+#define FLASH_FMP_BLOCK_23 0x00800000 // Enable for block 23\r
+#define FLASH_FMP_BLOCK_22 0x00400000 // Enable for block 22\r
+#define FLASH_FMP_BLOCK_21 0x00200000 // Enable for block 21\r
+#define FLASH_FMP_BLOCK_20 0x00100000 // Enable for block 20\r
+#define FLASH_FMP_BLOCK_19 0x00080000 // Enable for block 19\r
+#define FLASH_FMP_BLOCK_18 0x00040000 // Enable for block 18\r
+#define FLASH_FMP_BLOCK_17 0x00020000 // Enable for block 17\r
+#define FLASH_FMP_BLOCK_16 0x00010000 // Enable for block 16\r
+#define FLASH_FMP_BLOCK_15 0x00008000 // Enable for block 15\r
+#define FLASH_FMP_BLOCK_14 0x00004000 // Enable for block 14\r
+#define FLASH_FMP_BLOCK_13 0x00002000 // Enable for block 13\r
+#define FLASH_FMP_BLOCK_12 0x00001000 // Enable for block 12\r
+#define FLASH_FMP_BLOCK_11 0x00000800 // Enable for block 11\r
+#define FLASH_FMP_BLOCK_10 0x00000400 // Enable for block 10\r
+#define FLASH_FMP_BLOCK_9 0x00000200 // Enable for block 9\r
+#define FLASH_FMP_BLOCK_8 0x00000100 // Enable for block 8\r
+#define FLASH_FMP_BLOCK_7 0x00000080 // Enable for block 7\r
+#define FLASH_FMP_BLOCK_6 0x00000040 // Enable for block 6\r
+#define FLASH_FMP_BLOCK_5 0x00000020 // Enable for block 5\r
+#define FLASH_FMP_BLOCK_4 0x00000010 // Enable for block 4\r
+#define FLASH_FMP_BLOCK_3 0x00000008 // Enable for block 3\r
+#define FLASH_FMP_BLOCK_2 0x00000004 // Enable for block 2\r
+#define FLASH_FMP_BLOCK_1 0x00000002 // Enable for block 1\r
+#define FLASH_FMP_BLOCK_0 0x00000001 // Enable for block 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the FLASH_USECRL register.\r
+//\r
+//*****************************************************************************\r
+#define FLASH_USECRL_MASK 0x000000FF // Clock per uSec\r
+#define FLASH_USECRL_SHIFT 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The erase size is the size of the FLASH block that is erased by an erase\r
+// operation, and the protect size is the size of the FLASH block that is\r
+// protected by each protection register.\r
+//\r
+//*****************************************************************************\r
+#define FLASH_ERASE_SIZE 0x00000400\r
+#define FLASH_PROTECT_SIZE 0x00000800\r
+\r
+#endif // __HW_FLASH_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_gpio.h - Defines and Macros for GPIO hardware.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_GPIO_H__\r
+#define __HW_GPIO_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// GPIO Register Offsets.\r
+//\r
+//*****************************************************************************\r
+#define GPIO_O_DATA 0x00000000 // Data register.\r
+#define GPIO_O_DIR 0x00000400 // Data direction register.\r
+#define GPIO_O_IS 0x00000404 // Interrupt sense register.\r
+#define GPIO_O_IBE 0x00000408 // Interrupt both edges register.\r
+#define GPIO_O_IEV 0x0000040C // Intterupt event register.\r
+#define GPIO_O_IM 0x00000410 // Interrupt mask register.\r
+#define GPIO_O_RIS 0x00000414 // Raw interrupt status register.\r
+#define GPIO_O_MIS 0x00000418 // Masked interrupt status reg.\r
+#define GPIO_O_ICR 0x0000041C // Interrupt clear register.\r
+#define GPIO_O_AFSEL 0x00000420 // Mode control select register.\r
+#define GPIO_O_DR2R 0x00000500 // 2ma drive select register.\r
+#define GPIO_O_DR4R 0x00000504 // 4ma drive select register.\r
+#define GPIO_O_DR8R 0x00000508 // 8ma drive select register.\r
+#define GPIO_O_ODR 0x0000050C // Open drain select register.\r
+#define GPIO_O_PUR 0x00000510 // Pull up select register.\r
+#define GPIO_O_PDR 0x00000514 // Pull down select register.\r
+#define GPIO_O_SLR 0x00000518 // Slew rate control enable reg.\r
+#define GPIO_O_DEN 0x0000051C // Digital input enable register.\r
+#define GPIO_O_LOCK 0x00000520 // Lock register.\r
+#define GPIO_O_CR 0x00000524 // Commit register.\r
+#define GPIO_O_PeriphID4 0x00000FD0 //\r
+#define GPIO_O_PeriphID5 0x00000FD4 //\r
+#define GPIO_O_PeriphID6 0x00000FD8 //\r
+#define GPIO_O_PeriphID7 0x00000FDC //\r
+#define GPIO_O_PeriphID0 0x00000FE0 //\r
+#define GPIO_O_PeriphID1 0x00000FE4 //\r
+#define GPIO_O_PeriphID2 0x00000FE8 //\r
+#define GPIO_O_PeriphID3 0x00000FEC //\r
+#define GPIO_O_PCellID0 0x00000FF0 //\r
+#define GPIO_O_PCellID1 0x00000FF4 //\r
+#define GPIO_O_PCellID2 0x00000FF8 //\r
+#define GPIO_O_PCellID3 0x00000FFC //\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the GPIO_LOCK register.\r
+//\r
+//*****************************************************************************\r
+#define GPIO_LOCK_LOCKED 0x00000001 // GPIO_CR register is locked\r
+#define GPIO_LOCK_UNLOCKED 0x00000000 // GPIO_CR register is unlocked\r
+#define GPIO_LOCK_KEY 0x1ACCE551 // Unlocks the GPIO_CR register\r
+\r
+//*****************************************************************************\r
+//\r
+// GPIO Register reset values.\r
+//\r
+//*****************************************************************************\r
+#define GPIO_RV_DATA 0x00000000 // Data register reset value.\r
+#define GPIO_RV_DIR 0x00000000 // Data direction reg RV.\r
+#define GPIO_RV_IS 0x00000000 // Interrupt sense reg RV.\r
+#define GPIO_RV_IBE 0x00000000 // Interrupt both edges reg RV.\r
+#define GPIO_RV_IEV 0x00000000 // Intterupt event reg RV.\r
+#define GPIO_RV_IM 0x00000000 // Interrupt mask reg RV.\r
+#define GPIO_RV_RIS 0x00000000 // Raw interrupt status reg RV.\r
+#define GPIO_RV_MIS 0x00000000 // Masked interrupt status reg RV.\r
+#define GPIO_RV_IC 0x00000000 // Interrupt clear reg RV.\r
+#define GPIO_RV_AFSEL 0x00000000 // Mode control select reg RV.\r
+#define GPIO_RV_DR2R 0x000000FF // 2ma drive select reg RV.\r
+#define GPIO_RV_DR4R 0x00000000 // 4ma drive select reg RV.\r
+#define GPIO_RV_DR8R 0x00000000 // 8ma drive select reg RV.\r
+#define GPIO_RV_ODR 0x00000000 // Open drain select reg RV.\r
+#define GPIO_RV_PUR 0x000000FF // Pull up select reg RV.\r
+#define GPIO_RV_PDR 0x00000000 // Pull down select reg RV.\r
+#define GPIO_RV_SLR 0x00000000 // Slew rate control enable reg RV.\r
+#define GPIO_RV_DEN 0x000000FF // Digital input enable reg RV.\r
+#define GPIO_RV_LOCK 0x00000001 // Lock register RV.\r
+#define GPIO_RV_PeriphID4 0x00000000 //\r
+#define GPIO_RV_PeriphID5 0x00000000 //\r
+#define GPIO_RV_PeriphID6 0x00000000 //\r
+#define GPIO_RV_PeriphID7 0x00000000 //\r
+#define GPIO_RV_PeriphID0 0x00000061 //\r
+#define GPIO_RV_PeriphID1 0x00000010 //\r
+#define GPIO_RV_PeriphID2 0x00000004 //\r
+#define GPIO_RV_PeriphID3 0x00000000 //\r
+#define GPIO_RV_PCellID0 0x0000000D //\r
+#define GPIO_RV_PCellID1 0x000000F0 //\r
+#define GPIO_RV_PCellID2 0x00000005 //\r
+#define GPIO_RV_PCellID3 0x000000B1 //\r
+\r
+#endif // __HW_GPIO_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_hibernate.h - Defines and Macros for the Hibernation module.\r
+//\r
+// Copyright (c) 2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_HIBERNATE_H__\r
+#define __HW_HIBERNATE_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the addresses of the hibernation module registers.\r
+//\r
+//*****************************************************************************\r
+#define HIB_RTCC 0x400fc000 // Hibernate RTC counter\r
+#define HIB_RTCM0 0x400fc004 // Hibernate RTC match 0\r
+#define HIB_RTCM1 0x400fc008 // Hibernate RTC match 1\r
+#define HIB_RTCLD 0x400fc00C // Hibernate RTC load\r
+#define HIB_CTL 0x400fc010 // Hibernate RTC control\r
+#define HIB_IM 0x400fc014 // Hibernate interrupt mask\r
+#define HIB_RIS 0x400fc018 // Hibernate raw interrupt status\r
+#define HIB_MIS 0x400fc01C // Hibernate masked interrupt stat\r
+#define HIB_IC 0x400fc020 // Hibernate interrupt clear\r
+#define HIB_RTCT 0x400fc024 // Hibernate RTC trim\r
+#define HIB_DATA 0x400fc030 // Hibernate data area\r
+#define HIB_DATA_END 0x400fc130 // end of data area, exclusive\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the Hibernate RTC counter register.\r
+//\r
+//*****************************************************************************\r
+#define HIB_RTCC_MASK 0xffffffff // RTC counter mask\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the Hibernate RTC match 0 register.\r
+//\r
+//*****************************************************************************\r
+#define HIB_RTCM0_MASK 0xffffffff // RTC match 0 mask\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the Hibernate RTC match 1 register.\r
+//\r
+//*****************************************************************************\r
+#define HIB_RTCM1_MASK 0xffffffff // RTC match 1 mask\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the Hibernate RTC load register.\r
+//\r
+//*****************************************************************************\r
+#define HIB_RTCLD_MASK 0xffffffff // RTC load mask\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the Hibernate control register\r
+//\r
+//*****************************************************************************\r
+#define HIB_CTL_VABORT 0x00000080 // low bat abort\r
+#define HIB_CTL_CLK32EN 0x00000040 // enable clock/oscillator\r
+#define HIB_CTL_LOWBATEN 0x00000020 // enable low battery detect\r
+#define HIB_CTL_PINWEN 0x00000010 // enable wake on WAKE pin\r
+#define HIB_CTL_RTCWEN 0x00000008 // enable wake on RTC match\r
+#define HIB_CTL_CLKSEL 0x00000004 // clock input selection\r
+#define HIB_CTL_HIBREQ 0x00000002 // request hibernation\r
+#define HIB_CTL_RTCEN 0x00000001 // RTC enable\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the Hibernate interrupt mask reg.\r
+//\r
+//*****************************************************************************\r
+#define HIB_IM_EXTW 0x00000008 // wake from external pin interrupt\r
+#define HIB_IM_LOWBAT 0x00000004 // low battery interrupt\r
+#define HIB_IM_RTCALT1 0x00000002 // RTC match 1 interrupt\r
+#define HIB_IM_RTCALT0 0x00000001 // RTC match 0 interrupt\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the Hibernate raw interrupt status.\r
+//\r
+//*****************************************************************************\r
+#define HIB_RIS_EXTW 0x00000008 // wake from external pin interrupt\r
+#define HIB_RIS_LOWBAT 0x00000004 // low battery interrupt\r
+#define HIB_RIS_RTCALT1 0x00000002 // RTC match 1 interrupt\r
+#define HIB_RID_RTCALT0 0x00000001 // RTC match 0 interrupt\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the Hibernate masked int status.\r
+//\r
+//*****************************************************************************\r
+#define HIB_MIS_EXTW 0x00000008 // wake from external pin interrupt\r
+#define HIB_MIS_LOWBAT 0x00000004 // low battery interrupt\r
+#define HIB_MIS_RTCALT1 0x00000002 // RTC match 1 interrupt\r
+#define HIB_MID_RTCALT0 0x00000001 // RTC match 0 interrupt\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the Hibernate interrupt clear reg.\r
+//\r
+//*****************************************************************************\r
+#define HIB_IC_EXTW 0x00000008 // wake from external pin interrupt\r
+#define HIB_IC_LOWBAT 0x00000004 // low battery interrupt\r
+#define HIB_IC_RTCALT1 0x00000002 // RTC match 1 interrupt\r
+#define HIB_IC_RTCALT0 0x00000001 // RTC match 0 interrupt\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the Hibernate RTC trim register.\r
+//\r
+//*****************************************************************************\r
+#define HIB_RTCT_MASK 0x0000ffff // RTC trim mask\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the Hibernate data register.\r
+//\r
+//*****************************************************************************\r
+#define HIB_DATA_MASK 0xffffffff // NV memory data mask\r
+\r
+#endif // __HW_HIBERNATE_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_i2c.h - Macros used when accessing the I2C master and slave hardware.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_I2C_H__\r
+#define __HW_I2C_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// The following defines the offset between the I2C master and slave registers.\r
+//\r
+//*****************************************************************************\r
+#define I2C_O_SLAVE 0x00000800 // Offset from master to slave\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the offsets of the I2C master registers.\r
+//\r
+//*****************************************************************************\r
+#define I2C_MASTER_O_SA 0x00000000 // Slave address register\r
+#define I2C_MASTER_O_CS 0x00000004 // Control and Status register\r
+#define I2C_MASTER_O_DR 0x00000008 // Data register\r
+#define I2C_MASTER_O_TPR 0x0000000C // Timer period register\r
+#define I2C_MASTER_O_IMR 0x00000010 // Interrupt mask register\r
+#define I2C_MASTER_O_RIS 0x00000014 // Raw interrupt status register\r
+#define I2C_MASTER_O_MIS 0x00000018 // Masked interrupt status reg\r
+#define I2C_MASTER_O_MICR 0x0000001c // Interrupt clear register\r
+#define I2C_MASTER_O_CR 0x00000020 // Configuration register\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the offsets of the I2C slave registers.\r
+//\r
+//*****************************************************************************\r
+#define I2C_SLAVE_O_OAR 0x00000000 // Own address register\r
+#define I2C_SLAVE_O_CSR 0x00000004 // Control/Status register\r
+#define I2C_SLAVE_O_DR 0x00000008 // Data register\r
+#define I2C_SLAVE_O_IM 0x0000000C // Interrupt mask register\r
+#define I2C_SLAVE_O_RIS 0x00000010 // Raw interrupt status register\r
+#define I2C_SLAVE_O_MIS 0x00000014 // Masked interrupt status reg\r
+#define I2C_SLAVE_O_SICR 0x00000018 // Interrupt clear register\r
+\r
+//*****************************************************************************\r
+//\r
+// The followng define the bit fields in the I2C master slave address register.\r
+//\r
+//*****************************************************************************\r
+#define I2C_MASTER_SA_SA_MASK 0x000000FE // Slave address\r
+#define I2C_MASTER_SA_RS 0x00000001 // Receive/send\r
+#define I2C_MASTER_SA_SA_SHIFT 1\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the I2C Master Control and Status\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define I2C_MASTER_CS_ACK 0x00000008 // Acknowlegde\r
+#define I2C_MASTER_CS_STOP 0x00000004 // Stop\r
+#define I2C_MASTER_CS_START 0x00000002 // Start\r
+#define I2C_MASTER_CS_RUN 0x00000001 // Run\r
+#define I2C_MASTER_CS_BUS_BUSY 0x00000040 // Bus busy\r
+#define I2C_MASTER_CS_IDLE 0x00000020 // Idle\r
+#define I2C_MASTER_CS_ARB_LOST 0x00000010 // Lost arbitration\r
+#define I2C_MASTER_CS_DATA_ACK 0x00000008 // Data byte not acknowledged\r
+#define I2C_MASTER_CS_ADDR_ACK 0x00000004 // Address byte not acknowledged\r
+#define I2C_MASTER_CS_ERROR 0x00000002 // Error occurred\r
+#define I2C_MASTER_CS_BUSY 0x00000001 // Controller is TX/RX data\r
+#define I2C_MASTER_CS_ERR_MASK 0x0000001C\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define values used in determining the contents of the I2C\r
+// Master Timer Period register.\r
+//\r
+//*****************************************************************************\r
+#define I2C_MASTER_TPR_SCL_HP 0x00000004 // SCL high period\r
+#define I2C_MASTER_TPR_SCL_LP 0x00000006 // SCL low period\r
+#define I2C_MASTER_TPR_SCL (I2C_MASTER_TPR_SCL_HP + I2C_MASTER_TPR_SCL_LP)\r
+#define I2C_SCL_STANDARD 100000 // SCL standard frequency\r
+#define I2C_SCL_FAST 400000 // SCL fast frequency\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the I2C Master Interrupt Mask\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define I2C_MASTER_IMR_IM 0x00000001 // Master interrupt mask\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the I2C Master Raw Interrupt Status\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define I2C_MASTER_RIS_RIS 0x00000001 // Master raw interrupt status\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the I2C Master Masked Interrupt\r
+// Status register.\r
+//\r
+//*****************************************************************************\r
+#define I2C_MASTER_MIS_MIS 0x00000001 // Master masked interrupt status\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the I2C Master Interrupt Clear\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define I2C_MASTER_MICR_IC 0x00000001 // Master interrupt clear\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the I2C Master Configuration\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define I2C_MASTER_CR_SFE 0x00000020 // Slave function enable\r
+#define I2C_MASTER_CR_MFE 0x00000010 // Master function enable\r
+#define I2C_MASTER_CR_LPBK 0x00000001 // Loopback enable\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the I2C Slave Own Address register.\r
+//\r
+//*****************************************************************************\r
+#define I2C_SLAVE_SOAR_OAR_MASK 0x0000007F // Slave address\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the I2C Slave Control/Status\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define I2C_SLAVE_CSR_DA 0x00000001 // Enable the device\r
+#define I2C_SLAVE_CSR_TREQ 0x00000002 // Transmit request received\r
+#define I2C_SLAVE_CSR_RREQ 0x00000001 // Receive data from I2C master\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the I2C Slave Interrupt Mask\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define I2C_SLAVE_IMR_IM 0x00000001 // Slave interrupt mask\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the I2C Slave Raw Interrupt Status\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define I2C_SLAVE_RIS_RIS 0x00000001 // Slave raw interrupt status\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the I2C Slave Masked Interrupt\r
+// Status register.\r
+//\r
+//*****************************************************************************\r
+#define I2C_SLAVE_MIS_MIS 0x00000001 // Slave masked interrupt status\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the I2C Slave Interrupt Clear\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define I2C_SLAVE_SICR_IC 0x00000001 // Slave interrupt clear\r
+\r
+#endif // __HW_I2C_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_ints.h - Macros that define the interrupt assignment on Stellaris.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_INTS_H__\r
+#define __HW_INTS_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the fault assignments.\r
+//\r
+//*****************************************************************************\r
+#define FAULT_NMI 2 // NMI fault\r
+#define FAULT_HARD 3 // Hard fault\r
+#define FAULT_MPU 4 // MPU fault\r
+#define FAULT_BUS 5 // Bus fault\r
+#define FAULT_USAGE 6 // Usage fault\r
+#define FAULT_SVCALL 11 // SVCall\r
+#define FAULT_DEBUG 12 // Debug monitor\r
+#define FAULT_PENDSV 14 // PendSV\r
+#define FAULT_SYSTICK 15 // System Tick\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the interrupt assignments.\r
+//\r
+//*****************************************************************************\r
+#define INT_GPIOA 16 // GPIO Port A\r
+#define INT_GPIOB 17 // GPIO Port B\r
+#define INT_GPIOC 18 // GPIO Port C\r
+#define INT_GPIOD 19 // GPIO Port D\r
+#define INT_GPIOE 20 // GPIO Port E\r
+#define INT_UART0 21 // UART0 Rx and Tx\r
+#define INT_UART1 22 // UART1 Rx and Tx\r
+#define INT_SSI 23 // SSI Rx and Tx\r
+#define INT_SSI0 23 // SSI0 Rx and Tx\r
+#define INT_I2C 24 // I2C Master and Slave\r
+#define INT_I2C0 24 // I2C0 Master and Slave\r
+#define INT_PWM_FAULT 25 // PWM Fault\r
+#define INT_PWM0 26 // PWM Generator 0\r
+#define INT_PWM1 27 // PWM Generator 1\r
+#define INT_PWM2 28 // PWM Generator 2\r
+#define INT_QEI 29 // Quadrature Encoder\r
+#define INT_QEI0 29 // Quadrature Encoder 0\r
+#define INT_ADC0 30 // ADC Sequence 0\r
+#define INT_ADC1 31 // ADC Sequence 1\r
+#define INT_ADC2 32 // ADC Sequence 2\r
+#define INT_ADC3 33 // ADC Sequence 3\r
+#define INT_WATCHDOG 34 // Watchdog timer\r
+#define INT_TIMER0A 35 // Timer 0 subtimer A\r
+#define INT_TIMER0B 36 // Timer 0 subtimer B\r
+#define INT_TIMER1A 37 // Timer 1 subtimer A\r
+#define INT_TIMER1B 38 // Timer 1 subtimer B\r
+#define INT_TIMER2A 39 // Timer 2 subtimer A\r
+#define INT_TIMER2B 40 // Timer 2 subtimer B\r
+#define INT_COMP0 41 // Analog Comparator 0\r
+#define INT_COMP1 42 // Analog Comparator 1\r
+#define INT_COMP2 43 // Analog Comparator 2\r
+#define INT_SYSCTL 44 // System Control (PLL, OSC, BO)\r
+#define INT_FLASH 45 // FLASH Control\r
+#define INT_GPIOF 46 // GPIO Port F\r
+#define INT_GPIOG 47 // GPIO Port G\r
+#define INT_GPIOH 48 // GPIO Port H\r
+#define INT_UART2 49 // UART2 Rx and Tx\r
+#define INT_SSI1 50 // SSI1 Rx and Tx\r
+#define INT_TIMER3A 51 // Timer 3 subtimer A\r
+#define INT_TIMER3B 52 // Timer 3 subtimer B\r
+#define INT_I2C1 53 // I2C1 Master and Slave\r
+#define INT_QEI1 54 // Quadrature Encoder 1\r
+#define INT_CAN0 55 // CAN0\r
+#define INT_CAN1 56 // CAN1\r
+#define INT_ETH 58 // Ethernet\r
+#define INT_HIBERNATE 59 // Hibernation module\r
+\r
+//*****************************************************************************\r
+//\r
+// The total number of interrupts.\r
+//\r
+//*****************************************************************************\r
+#define NUM_INTERRUPTS 60\r
+\r
+//*****************************************************************************\r
+//\r
+// The total number of priority levels.\r
+//\r
+//*****************************************************************************\r
+#define NUM_PRIORITY 8\r
+#define NUM_PRIORITY_BITS 3\r
+\r
+#endif // __HW_INTS_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_memmap.h - Macros defining the memory map of Stellaris.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_MEMMAP_H__\r
+#define __HW_MEMMAP_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the base address of the memories and peripherals.\r
+//\r
+//*****************************************************************************\r
+#define FLASH_BASE 0x00000000 // FLASH memory\r
+#define SRAM_BASE 0x20000000 // SRAM memory\r
+#define WATCHDOG_BASE 0x40000000 // Watchdog\r
+#define GPIO_PORTA_BASE 0x40004000 // GPIO Port A\r
+#define GPIO_PORTB_BASE 0x40005000 // GPIO Port B\r
+#define GPIO_PORTC_BASE 0x40006000 // GPIO Port C\r
+#define GPIO_PORTD_BASE 0x40007000 // GPIO Port D\r
+#define SSI_BASE 0x40008000 // SSI\r
+#define SSI0_BASE 0x40008000 // SSI0\r
+#define SSI1_BASE 0x40009000 // SSI1\r
+#define UART0_BASE 0x4000C000 // UART0\r
+#define UART1_BASE 0x4000D000 // UART1\r
+#define UART2_BASE 0x4000E000 // UART2\r
+#define I2C_MASTER_BASE 0x40020000 // I2C Master\r
+#define I2C_SLAVE_BASE 0x40020800 // I2C Slave\r
+#define I2C0_MASTER_BASE 0x40020000 // I2C0 Master\r
+#define I2C0_SLAVE_BASE 0x40020800 // I2C0 Slave\r
+#define I2C1_MASTER_BASE 0x40021000 // I2C1 Master\r
+#define I2C1_SLAVE_BASE 0x40021800 // I2C1 Slave\r
+#define GPIO_PORTE_BASE 0x40024000 // GPIO Port E\r
+#define GPIO_PORTF_BASE 0x40025000 // GPIO Port F\r
+#define GPIO_PORTG_BASE 0x40026000 // GPIO Port G\r
+#define GPIO_PORTH_BASE 0x40027000 // GPIO Port H\r
+#define PWM_BASE 0x40028000 // PWM\r
+#define QEI_BASE 0x4002C000 // QEI\r
+#define QEI0_BASE 0x4002C000 // QEI0\r
+#define QEI1_BASE 0x4002D000 // QEI1\r
+#define TIMER0_BASE 0x40030000 // Timer0\r
+#define TIMER1_BASE 0x40031000 // Timer1\r
+#define TIMER2_BASE 0x40032000 // Timer2\r
+#define TIMER3_BASE 0x40033000 // Timer3\r
+#define ADC_BASE 0x40038000 // ADC\r
+#define COMP_BASE 0x4003C000 // Analog comparators\r
+#define CAN0_BASE 0x40040000 // CAN0\r
+#define CAN1_BASE 0x40041000 // CAN1\r
+#define ETH_BASE 0x40048000 // Ethernet\r
+#define FLASH_CTRL_BASE 0x400FD000 // FLASH Controller\r
+#define SYSCTL_BASE 0x400FE000 // System Control\r
+#define ITM_BASE 0xE0000000 // Instrumentation Trace Macrocell\r
+#define DWT_BASE 0xE0001000 // Data Watchpoint and Trace\r
+#define FPB_BASE 0xE0002000 // FLASH Patch and Breakpoint\r
+#define NVIC_BASE 0xE000E000 // Nested Vectored Interrupt Ctrl\r
+#define TPIU_BASE 0xE0040000 // Trace Port Interface Unit\r
+\r
+#endif // __HW_MEMMAP_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_nvic.h - Macros used when accessing the NVIC hardware.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_NVIC_H__\r
+#define __HW_NVIC_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the addresses of the NVIC registers.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_INT_TYPE 0xE000E004 // Interrupt Controller Type Reg.\r
+#define NVIC_ST_CTRL 0xE000E010 // SysTick Control and Status Reg.\r
+#define NVIC_ST_RELOAD 0xE000E014 // SysTick Reload Value Register\r
+#define NVIC_ST_CURRENT 0xE000E018 // SysTick Current Value Register\r
+#define NVIC_ST_CAL 0xE000E01C // SysTick Calibration Value Reg.\r
+#define NVIC_EN0 0xE000E100 // IRQ 0 to 31 Set Enable Register\r
+#define NVIC_EN1 0xE000E104 // IRQ 32 to 63 Set Enable Register\r
+#define NVIC_DIS0 0xE000E180 // IRQ 0 to 31 Clear Enable Reg.\r
+#define NVIC_DIS1 0xE000E184 // IRQ 32 to 63 Clear Enable Reg.\r
+#define NVIC_PEND0 0xE000E200 // IRQ 0 to 31 Set Pending Register\r
+#define NVIC_PEND1 0xE000E204 // IRQ 32 to 63 Set Pending Reg.\r
+#define NVIC_UNPEND0 0xE000E280 // IRQ 0 to 31 Clear Pending Reg.\r
+#define NVIC_UNPEND1 0xE000E284 // IRQ 32 to 63 Clear Pending Reg.\r
+#define NVIC_ACTIVE0 0xE000E300 // IRQ 0 to 31 Active Register\r
+#define NVIC_ACTIVE1 0xE000E304 // IRQ 32 to 63 Active Register\r
+#define NVIC_PRI0 0xE000E400 // IRQ 0 to 3 Priority Register\r
+#define NVIC_PRI1 0xE000E404 // IRQ 4 to 7 Priority Register\r
+#define NVIC_PRI2 0xE000E408 // IRQ 8 to 11 Priority Register\r
+#define NVIC_PRI3 0xE000E40C // IRQ 12 to 15 Priority Register\r
+#define NVIC_PRI4 0xE000E410 // IRQ 16 to 19 Priority Register\r
+#define NVIC_PRI5 0xE000E414 // IRQ 20 to 23 Priority Register\r
+#define NVIC_PRI6 0xE000E418 // IRQ 24 to 27 Priority Register\r
+#define NVIC_PRI7 0xE000E41C // IRQ 28 to 31 Priority Register\r
+#define NVIC_PRI8 0xE000E420 // IRQ 32 to 35 Priority Register\r
+#define NVIC_PRI9 0xE000E424 // IRQ 36 to 39 Priority Register\r
+#define NVIC_PRI10 0xE000E428 // IRQ 40 to 43 Priority Register\r
+#define NVIC_CPUID 0xE000ED00 // CPUID Base Register\r
+#define NVIC_INT_CTRL 0xE000ED04 // Interrupt Control State Register\r
+#define NVIC_VTABLE 0xE000ED08 // Vector Table Offset Register\r
+#define NVIC_APINT 0xE000ED0C // App. Int & Reset Control Reg.\r
+#define NVIC_SYS_CTRL 0xE000ED10 // System Control Register\r
+#define NVIC_CFG_CTRL 0xE000ED14 // Configuration Control Register\r
+#define NVIC_SYS_PRI1 0xE000ED18 // Sys. Handlers 4 to 7 Priority\r
+#define NVIC_SYS_PRI2 0xE000ED1C // Sys. Handlers 8 to 11 Priority\r
+#define NVIC_SYS_PRI3 0xE000ED20 // Sys. Handlers 12 to 15 Priority\r
+#define NVIC_SYS_HND_CTRL 0xE000ED24 // System Handler Control and State\r
+#define NVIC_FAULT_STAT 0xE000ED28 // Configurable Fault Status Reg.\r
+#define NVIC_HFAULT_STAT 0xE000ED2C // Hard Fault Status Register\r
+#define NVIC_DEBUG_STAT 0xE000ED30 // Debug Status Register\r
+#define NVIC_MM_ADDR 0xE000ED34 // Mem Manage Address Register\r
+#define NVIC_FAULT_ADDR 0xE000ED38 // Bus Fault Address Register\r
+#define NVIC_MPU_TYPE 0xE000ED90 // MPU Type Register\r
+#define NVIC_MPU_CTRL 0xE000ED94 // MPU Control Register\r
+#define NVIC_MPU_NUMBER 0xE000ED98 // MPU Region Number Register\r
+#define NVIC_MPU_BASE 0xE000ED9C // MPU Region Base Address Register\r
+#define NVIC_MPU_ATTR 0xE000EDA0 // MPU Region Attribute & Size Reg.\r
+#define NVIC_DBG_CTRL 0xE000EDF0 // Debug Control and Status Reg.\r
+#define NVIC_DBG_XFER 0xE000EDF4 // Debug Core Reg. Transfer Select\r
+#define NVIC_DBG_DATA 0xE000EDF8 // Debug Core Register Data\r
+#define NVIC_DBG_INT 0xE000EDFC // Debug Reset Interrupt Control\r
+#define NVIC_SW_TRIG 0xE000EF00 // Software Trigger Interrupt Reg.\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_INT_TYPE register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_INT_TYPE_LINES_M 0x0000001F // Number of interrupt lines (x32)\r
+#define NVIC_INT_TYPE_LINES_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_ST_CTRL register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_ST_CTRL_COUNT 0x00010000 // Count flag\r
+#define NVIC_ST_CTRL_CLK_SRC 0x00000004 // Clock Source\r
+#define NVIC_ST_CTRL_INTEN 0x00000002 // Interrupt enable\r
+#define NVIC_ST_CTRL_ENABLE 0x00000001 // Counter mode\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_ST_RELOAD register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_ST_RELOAD_M 0x00FFFFFF // Counter load value\r
+#define NVIC_ST_RELOAD_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_ST_CURRENT register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_ST_CURRENT_M 0x00FFFFFF // Counter current value\r
+#define NVIC_ST_CURRENT_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_ST_CAL register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_ST_CAL_NOREF 0x80000000 // No reference clock\r
+#define NVIC_ST_CAL_SKEW 0x40000000 // Clock skew\r
+#define NVIC_ST_CAL_ONEMS_M 0x00FFFFFF // 1ms reference value\r
+#define NVIC_ST_CAL_ONEMS_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_EN0 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_EN0_INT31 0x80000000 // Interrupt 31 enable\r
+#define NVIC_EN0_INT30 0x40000000 // Interrupt 30 enable\r
+#define NVIC_EN0_INT29 0x20000000 // Interrupt 29 enable\r
+#define NVIC_EN0_INT28 0x10000000 // Interrupt 28 enable\r
+#define NVIC_EN0_INT27 0x08000000 // Interrupt 27 enable\r
+#define NVIC_EN0_INT26 0x04000000 // Interrupt 26 enable\r
+#define NVIC_EN0_INT25 0x02000000 // Interrupt 25 enable\r
+#define NVIC_EN0_INT24 0x01000000 // Interrupt 24 enable\r
+#define NVIC_EN0_INT23 0x00800000 // Interrupt 23 enable\r
+#define NVIC_EN0_INT22 0x00400000 // Interrupt 22 enable\r
+#define NVIC_EN0_INT21 0x00200000 // Interrupt 21 enable\r
+#define NVIC_EN0_INT20 0x00100000 // Interrupt 20 enable\r
+#define NVIC_EN0_INT19 0x00080000 // Interrupt 19 enable\r
+#define NVIC_EN0_INT18 0x00040000 // Interrupt 18 enable\r
+#define NVIC_EN0_INT17 0x00020000 // Interrupt 17 enable\r
+#define NVIC_EN0_INT16 0x00010000 // Interrupt 16 enable\r
+#define NVIC_EN0_INT15 0x00008000 // Interrupt 15 enable\r
+#define NVIC_EN0_INT14 0x00004000 // Interrupt 14 enable\r
+#define NVIC_EN0_INT13 0x00002000 // Interrupt 13 enable\r
+#define NVIC_EN0_INT12 0x00001000 // Interrupt 12 enable\r
+#define NVIC_EN0_INT11 0x00000800 // Interrupt 11 enable\r
+#define NVIC_EN0_INT10 0x00000400 // Interrupt 10 enable\r
+#define NVIC_EN0_INT9 0x00000200 // Interrupt 9 enable\r
+#define NVIC_EN0_INT8 0x00000100 // Interrupt 8 enable\r
+#define NVIC_EN0_INT7 0x00000080 // Interrupt 7 enable\r
+#define NVIC_EN0_INT6 0x00000040 // Interrupt 6 enable\r
+#define NVIC_EN0_INT5 0x00000020 // Interrupt 5 enable\r
+#define NVIC_EN0_INT4 0x00000010 // Interrupt 4 enable\r
+#define NVIC_EN0_INT3 0x00000008 // Interrupt 3 enable\r
+#define NVIC_EN0_INT2 0x00000004 // Interrupt 2 enable\r
+#define NVIC_EN0_INT1 0x00000002 // Interrupt 1 enable\r
+#define NVIC_EN0_INT0 0x00000001 // Interrupt 0 enable\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_EN1 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_EN1_INT59 0x08000000 // Interrupt 59 enable\r
+#define NVIC_EN1_INT58 0x04000000 // Interrupt 58 enable\r
+#define NVIC_EN1_INT57 0x02000000 // Interrupt 57 enable\r
+#define NVIC_EN1_INT56 0x01000000 // Interrupt 56 enable\r
+#define NVIC_EN1_INT55 0x00800000 // Interrupt 55 enable\r
+#define NVIC_EN1_INT54 0x00400000 // Interrupt 54 enable\r
+#define NVIC_EN1_INT53 0x00200000 // Interrupt 53 enable\r
+#define NVIC_EN1_INT52 0x00100000 // Interrupt 52 enable\r
+#define NVIC_EN1_INT51 0x00080000 // Interrupt 51 enable\r
+#define NVIC_EN1_INT50 0x00040000 // Interrupt 50 enable\r
+#define NVIC_EN1_INT49 0x00020000 // Interrupt 49 enable\r
+#define NVIC_EN1_INT48 0x00010000 // Interrupt 48 enable\r
+#define NVIC_EN1_INT47 0x00008000 // Interrupt 47 enable\r
+#define NVIC_EN1_INT46 0x00004000 // Interrupt 46 enable\r
+#define NVIC_EN1_INT45 0x00002000 // Interrupt 45 enable\r
+#define NVIC_EN1_INT44 0x00001000 // Interrupt 44 enable\r
+#define NVIC_EN1_INT43 0x00000800 // Interrupt 43 enable\r
+#define NVIC_EN1_INT42 0x00000400 // Interrupt 42 enable\r
+#define NVIC_EN1_INT41 0x00000200 // Interrupt 41 enable\r
+#define NVIC_EN1_INT40 0x00000100 // Interrupt 40 enable\r
+#define NVIC_EN1_INT39 0x00000080 // Interrupt 39 enable\r
+#define NVIC_EN1_INT38 0x00000040 // Interrupt 38 enable\r
+#define NVIC_EN1_INT37 0x00000020 // Interrupt 37 enable\r
+#define NVIC_EN1_INT36 0x00000010 // Interrupt 36 enable\r
+#define NVIC_EN1_INT35 0x00000008 // Interrupt 35 enable\r
+#define NVIC_EN1_INT34 0x00000004 // Interrupt 34 enable\r
+#define NVIC_EN1_INT33 0x00000002 // Interrupt 33 enable\r
+#define NVIC_EN1_INT32 0x00000001 // Interrupt 32 enable\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_DIS0 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_DIS0_INT31 0x80000000 // Interrupt 31 disable\r
+#define NVIC_DIS0_INT30 0x40000000 // Interrupt 30 disable\r
+#define NVIC_DIS0_INT29 0x20000000 // Interrupt 29 disable\r
+#define NVIC_DIS0_INT28 0x10000000 // Interrupt 28 disable\r
+#define NVIC_DIS0_INT27 0x08000000 // Interrupt 27 disable\r
+#define NVIC_DIS0_INT26 0x04000000 // Interrupt 26 disable\r
+#define NVIC_DIS0_INT25 0x02000000 // Interrupt 25 disable\r
+#define NVIC_DIS0_INT24 0x01000000 // Interrupt 24 disable\r
+#define NVIC_DIS0_INT23 0x00800000 // Interrupt 23 disable\r
+#define NVIC_DIS0_INT22 0x00400000 // Interrupt 22 disable\r
+#define NVIC_DIS0_INT21 0x00200000 // Interrupt 21 disable\r
+#define NVIC_DIS0_INT20 0x00100000 // Interrupt 20 disable\r
+#define NVIC_DIS0_INT19 0x00080000 // Interrupt 19 disable\r
+#define NVIC_DIS0_INT18 0x00040000 // Interrupt 18 disable\r
+#define NVIC_DIS0_INT17 0x00020000 // Interrupt 17 disable\r
+#define NVIC_DIS0_INT16 0x00010000 // Interrupt 16 disable\r
+#define NVIC_DIS0_INT15 0x00008000 // Interrupt 15 disable\r
+#define NVIC_DIS0_INT14 0x00004000 // Interrupt 14 disable\r
+#define NVIC_DIS0_INT13 0x00002000 // Interrupt 13 disable\r
+#define NVIC_DIS0_INT12 0x00001000 // Interrupt 12 disable\r
+#define NVIC_DIS0_INT11 0x00000800 // Interrupt 11 disable\r
+#define NVIC_DIS0_INT10 0x00000400 // Interrupt 10 disable\r
+#define NVIC_DIS0_INT9 0x00000200 // Interrupt 9 disable\r
+#define NVIC_DIS0_INT8 0x00000100 // Interrupt 8 disable\r
+#define NVIC_DIS0_INT7 0x00000080 // Interrupt 7 disable\r
+#define NVIC_DIS0_INT6 0x00000040 // Interrupt 6 disable\r
+#define NVIC_DIS0_INT5 0x00000020 // Interrupt 5 disable\r
+#define NVIC_DIS0_INT4 0x00000010 // Interrupt 4 disable\r
+#define NVIC_DIS0_INT3 0x00000008 // Interrupt 3 disable\r
+#define NVIC_DIS0_INT2 0x00000004 // Interrupt 2 disable\r
+#define NVIC_DIS0_INT1 0x00000002 // Interrupt 1 disable\r
+#define NVIC_DIS0_INT0 0x00000001 // Interrupt 0 disable\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_DIS1 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_DIS1_INT59 0x08000000 // Interrupt 59 disable\r
+#define NVIC_DIS1_INT58 0x04000000 // Interrupt 58 disable\r
+#define NVIC_DIS1_INT57 0x02000000 // Interrupt 57 disable\r
+#define NVIC_DIS1_INT56 0x01000000 // Interrupt 56 disable\r
+#define NVIC_DIS1_INT55 0x00800000 // Interrupt 55 disable\r
+#define NVIC_DIS1_INT54 0x00400000 // Interrupt 54 disable\r
+#define NVIC_DIS1_INT53 0x00200000 // Interrupt 53 disable\r
+#define NVIC_DIS1_INT52 0x00100000 // Interrupt 52 disable\r
+#define NVIC_DIS1_INT51 0x00080000 // Interrupt 51 disable\r
+#define NVIC_DIS1_INT50 0x00040000 // Interrupt 50 disable\r
+#define NVIC_DIS1_INT49 0x00020000 // Interrupt 49 disable\r
+#define NVIC_DIS1_INT48 0x00010000 // Interrupt 48 disable\r
+#define NVIC_DIS1_INT47 0x00008000 // Interrupt 47 disable\r
+#define NVIC_DIS1_INT46 0x00004000 // Interrupt 46 disable\r
+#define NVIC_DIS1_INT45 0x00002000 // Interrupt 45 disable\r
+#define NVIC_DIS1_INT44 0x00001000 // Interrupt 44 disable\r
+#define NVIC_DIS1_INT43 0x00000800 // Interrupt 43 disable\r
+#define NVIC_DIS1_INT42 0x00000400 // Interrupt 42 disable\r
+#define NVIC_DIS1_INT41 0x00000200 // Interrupt 41 disable\r
+#define NVIC_DIS1_INT40 0x00000100 // Interrupt 40 disable\r
+#define NVIC_DIS1_INT39 0x00000080 // Interrupt 39 disable\r
+#define NVIC_DIS1_INT38 0x00000040 // Interrupt 38 disable\r
+#define NVIC_DIS1_INT37 0x00000020 // Interrupt 37 disable\r
+#define NVIC_DIS1_INT36 0x00000010 // Interrupt 36 disable\r
+#define NVIC_DIS1_INT35 0x00000008 // Interrupt 35 disable\r
+#define NVIC_DIS1_INT34 0x00000004 // Interrupt 34 disable\r
+#define NVIC_DIS1_INT33 0x00000002 // Interrupt 33 disable\r
+#define NVIC_DIS1_INT32 0x00000001 // Interrupt 32 disable\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_PEND0 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_PEND0_INT31 0x80000000 // Interrupt 31 pend\r
+#define NVIC_PEND0_INT30 0x40000000 // Interrupt 30 pend\r
+#define NVIC_PEND0_INT29 0x20000000 // Interrupt 29 pend\r
+#define NVIC_PEND0_INT28 0x10000000 // Interrupt 28 pend\r
+#define NVIC_PEND0_INT27 0x08000000 // Interrupt 27 pend\r
+#define NVIC_PEND0_INT26 0x04000000 // Interrupt 26 pend\r
+#define NVIC_PEND0_INT25 0x02000000 // Interrupt 25 pend\r
+#define NVIC_PEND0_INT24 0x01000000 // Interrupt 24 pend\r
+#define NVIC_PEND0_INT23 0x00800000 // Interrupt 23 pend\r
+#define NVIC_PEND0_INT22 0x00400000 // Interrupt 22 pend\r
+#define NVIC_PEND0_INT21 0x00200000 // Interrupt 21 pend\r
+#define NVIC_PEND0_INT20 0x00100000 // Interrupt 20 pend\r
+#define NVIC_PEND0_INT19 0x00080000 // Interrupt 19 pend\r
+#define NVIC_PEND0_INT18 0x00040000 // Interrupt 18 pend\r
+#define NVIC_PEND0_INT17 0x00020000 // Interrupt 17 pend\r
+#define NVIC_PEND0_INT16 0x00010000 // Interrupt 16 pend\r
+#define NVIC_PEND0_INT15 0x00008000 // Interrupt 15 pend\r
+#define NVIC_PEND0_INT14 0x00004000 // Interrupt 14 pend\r
+#define NVIC_PEND0_INT13 0x00002000 // Interrupt 13 pend\r
+#define NVIC_PEND0_INT12 0x00001000 // Interrupt 12 pend\r
+#define NVIC_PEND0_INT11 0x00000800 // Interrupt 11 pend\r
+#define NVIC_PEND0_INT10 0x00000400 // Interrupt 10 pend\r
+#define NVIC_PEND0_INT9 0x00000200 // Interrupt 9 pend\r
+#define NVIC_PEND0_INT8 0x00000100 // Interrupt 8 pend\r
+#define NVIC_PEND0_INT7 0x00000080 // Interrupt 7 pend\r
+#define NVIC_PEND0_INT6 0x00000040 // Interrupt 6 pend\r
+#define NVIC_PEND0_INT5 0x00000020 // Interrupt 5 pend\r
+#define NVIC_PEND0_INT4 0x00000010 // Interrupt 4 pend\r
+#define NVIC_PEND0_INT3 0x00000008 // Interrupt 3 pend\r
+#define NVIC_PEND0_INT2 0x00000004 // Interrupt 2 pend\r
+#define NVIC_PEND0_INT1 0x00000002 // Interrupt 1 pend\r
+#define NVIC_PEND0_INT0 0x00000001 // Interrupt 0 pend\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_PEND1 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_PEND1_INT59 0x08000000 // Interrupt 59 pend\r
+#define NVIC_PEND1_INT58 0x04000000 // Interrupt 58 pend\r
+#define NVIC_PEND1_INT57 0x02000000 // Interrupt 57 pend\r
+#define NVIC_PEND1_INT56 0x01000000 // Interrupt 56 pend\r
+#define NVIC_PEND1_INT55 0x00800000 // Interrupt 55 pend\r
+#define NVIC_PEND1_INT54 0x00400000 // Interrupt 54 pend\r
+#define NVIC_PEND1_INT53 0x00200000 // Interrupt 53 pend\r
+#define NVIC_PEND1_INT52 0x00100000 // Interrupt 52 pend\r
+#define NVIC_PEND1_INT51 0x00080000 // Interrupt 51 pend\r
+#define NVIC_PEND1_INT50 0x00040000 // Interrupt 50 pend\r
+#define NVIC_PEND1_INT49 0x00020000 // Interrupt 49 pend\r
+#define NVIC_PEND1_INT48 0x00010000 // Interrupt 48 pend\r
+#define NVIC_PEND1_INT47 0x00008000 // Interrupt 47 pend\r
+#define NVIC_PEND1_INT46 0x00004000 // Interrupt 46 pend\r
+#define NVIC_PEND1_INT45 0x00002000 // Interrupt 45 pend\r
+#define NVIC_PEND1_INT44 0x00001000 // Interrupt 44 pend\r
+#define NVIC_PEND1_INT43 0x00000800 // Interrupt 43 pend\r
+#define NVIC_PEND1_INT42 0x00000400 // Interrupt 42 pend\r
+#define NVIC_PEND1_INT41 0x00000200 // Interrupt 41 pend\r
+#define NVIC_PEND1_INT40 0x00000100 // Interrupt 40 pend\r
+#define NVIC_PEND1_INT39 0x00000080 // Interrupt 39 pend\r
+#define NVIC_PEND1_INT38 0x00000040 // Interrupt 38 pend\r
+#define NVIC_PEND1_INT37 0x00000020 // Interrupt 37 pend\r
+#define NVIC_PEND1_INT36 0x00000010 // Interrupt 36 pend\r
+#define NVIC_PEND1_INT35 0x00000008 // Interrupt 35 pend\r
+#define NVIC_PEND1_INT34 0x00000004 // Interrupt 34 pend\r
+#define NVIC_PEND1_INT33 0x00000002 // Interrupt 33 pend\r
+#define NVIC_PEND1_INT32 0x00000001 // Interrupt 32 pend\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_UNPEND0 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_UNPEND0_INT31 0x80000000 // Interrupt 31 unpend\r
+#define NVIC_UNPEND0_INT30 0x40000000 // Interrupt 30 unpend\r
+#define NVIC_UNPEND0_INT29 0x20000000 // Interrupt 29 unpend\r
+#define NVIC_UNPEND0_INT28 0x10000000 // Interrupt 28 unpend\r
+#define NVIC_UNPEND0_INT27 0x08000000 // Interrupt 27 unpend\r
+#define NVIC_UNPEND0_INT26 0x04000000 // Interrupt 26 unpend\r
+#define NVIC_UNPEND0_INT25 0x02000000 // Interrupt 25 unpend\r
+#define NVIC_UNPEND0_INT24 0x01000000 // Interrupt 24 unpend\r
+#define NVIC_UNPEND0_INT23 0x00800000 // Interrupt 23 unpend\r
+#define NVIC_UNPEND0_INT22 0x00400000 // Interrupt 22 unpend\r
+#define NVIC_UNPEND0_INT21 0x00200000 // Interrupt 21 unpend\r
+#define NVIC_UNPEND0_INT20 0x00100000 // Interrupt 20 unpend\r
+#define NVIC_UNPEND0_INT19 0x00080000 // Interrupt 19 unpend\r
+#define NVIC_UNPEND0_INT18 0x00040000 // Interrupt 18 unpend\r
+#define NVIC_UNPEND0_INT17 0x00020000 // Interrupt 17 unpend\r
+#define NVIC_UNPEND0_INT16 0x00010000 // Interrupt 16 unpend\r
+#define NVIC_UNPEND0_INT15 0x00008000 // Interrupt 15 unpend\r
+#define NVIC_UNPEND0_INT14 0x00004000 // Interrupt 14 unpend\r
+#define NVIC_UNPEND0_INT13 0x00002000 // Interrupt 13 unpend\r
+#define NVIC_UNPEND0_INT12 0x00001000 // Interrupt 12 unpend\r
+#define NVIC_UNPEND0_INT11 0x00000800 // Interrupt 11 unpend\r
+#define NVIC_UNPEND0_INT10 0x00000400 // Interrupt 10 unpend\r
+#define NVIC_UNPEND0_INT9 0x00000200 // Interrupt 9 unpend\r
+#define NVIC_UNPEND0_INT8 0x00000100 // Interrupt 8 unpend\r
+#define NVIC_UNPEND0_INT7 0x00000080 // Interrupt 7 unpend\r
+#define NVIC_UNPEND0_INT6 0x00000040 // Interrupt 6 unpend\r
+#define NVIC_UNPEND0_INT5 0x00000020 // Interrupt 5 unpend\r
+#define NVIC_UNPEND0_INT4 0x00000010 // Interrupt 4 unpend\r
+#define NVIC_UNPEND0_INT3 0x00000008 // Interrupt 3 unpend\r
+#define NVIC_UNPEND0_INT2 0x00000004 // Interrupt 2 unpend\r
+#define NVIC_UNPEND0_INT1 0x00000002 // Interrupt 1 unpend\r
+#define NVIC_UNPEND0_INT0 0x00000001 // Interrupt 0 unpend\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_UNPEND1 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_UNPEND1_INT59 0x08000000 // Interrupt 59 unpend\r
+#define NVIC_UNPEND1_INT58 0x04000000 // Interrupt 58 unpend\r
+#define NVIC_UNPEND1_INT57 0x02000000 // Interrupt 57 unpend\r
+#define NVIC_UNPEND1_INT56 0x01000000 // Interrupt 56 unpend\r
+#define NVIC_UNPEND1_INT55 0x00800000 // Interrupt 55 unpend\r
+#define NVIC_UNPEND1_INT54 0x00400000 // Interrupt 54 unpend\r
+#define NVIC_UNPEND1_INT53 0x00200000 // Interrupt 53 unpend\r
+#define NVIC_UNPEND1_INT52 0x00100000 // Interrupt 52 unpend\r
+#define NVIC_UNPEND1_INT51 0x00080000 // Interrupt 51 unpend\r
+#define NVIC_UNPEND1_INT50 0x00040000 // Interrupt 50 unpend\r
+#define NVIC_UNPEND1_INT49 0x00020000 // Interrupt 49 unpend\r
+#define NVIC_UNPEND1_INT48 0x00010000 // Interrupt 48 unpend\r
+#define NVIC_UNPEND1_INT47 0x00008000 // Interrupt 47 unpend\r
+#define NVIC_UNPEND1_INT46 0x00004000 // Interrupt 46 unpend\r
+#define NVIC_UNPEND1_INT45 0x00002000 // Interrupt 45 unpend\r
+#define NVIC_UNPEND1_INT44 0x00001000 // Interrupt 44 unpend\r
+#define NVIC_UNPEND1_INT43 0x00000800 // Interrupt 43 unpend\r
+#define NVIC_UNPEND1_INT42 0x00000400 // Interrupt 42 unpend\r
+#define NVIC_UNPEND1_INT41 0x00000200 // Interrupt 41 unpend\r
+#define NVIC_UNPEND1_INT40 0x00000100 // Interrupt 40 unpend\r
+#define NVIC_UNPEND1_INT39 0x00000080 // Interrupt 39 unpend\r
+#define NVIC_UNPEND1_INT38 0x00000040 // Interrupt 38 unpend\r
+#define NVIC_UNPEND1_INT37 0x00000020 // Interrupt 37 unpend\r
+#define NVIC_UNPEND1_INT36 0x00000010 // Interrupt 36 unpend\r
+#define NVIC_UNPEND1_INT35 0x00000008 // Interrupt 35 unpend\r
+#define NVIC_UNPEND1_INT34 0x00000004 // Interrupt 34 unpend\r
+#define NVIC_UNPEND1_INT33 0x00000002 // Interrupt 33 unpend\r
+#define NVIC_UNPEND1_INT32 0x00000001 // Interrupt 32 unpend\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_ACTIVE0 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_ACTIVE0_INT31 0x80000000 // Interrupt 31 active\r
+#define NVIC_ACTIVE0_INT30 0x40000000 // Interrupt 30 active\r
+#define NVIC_ACTIVE0_INT29 0x20000000 // Interrupt 29 active\r
+#define NVIC_ACTIVE0_INT28 0x10000000 // Interrupt 28 active\r
+#define NVIC_ACTIVE0_INT27 0x08000000 // Interrupt 27 active\r
+#define NVIC_ACTIVE0_INT26 0x04000000 // Interrupt 26 active\r
+#define NVIC_ACTIVE0_INT25 0x02000000 // Interrupt 25 active\r
+#define NVIC_ACTIVE0_INT24 0x01000000 // Interrupt 24 active\r
+#define NVIC_ACTIVE0_INT23 0x00800000 // Interrupt 23 active\r
+#define NVIC_ACTIVE0_INT22 0x00400000 // Interrupt 22 active\r
+#define NVIC_ACTIVE0_INT21 0x00200000 // Interrupt 21 active\r
+#define NVIC_ACTIVE0_INT20 0x00100000 // Interrupt 20 active\r
+#define NVIC_ACTIVE0_INT19 0x00080000 // Interrupt 19 active\r
+#define NVIC_ACTIVE0_INT18 0x00040000 // Interrupt 18 active\r
+#define NVIC_ACTIVE0_INT17 0x00020000 // Interrupt 17 active\r
+#define NVIC_ACTIVE0_INT16 0x00010000 // Interrupt 16 active\r
+#define NVIC_ACTIVE0_INT15 0x00008000 // Interrupt 15 active\r
+#define NVIC_ACTIVE0_INT14 0x00004000 // Interrupt 14 active\r
+#define NVIC_ACTIVE0_INT13 0x00002000 // Interrupt 13 active\r
+#define NVIC_ACTIVE0_INT12 0x00001000 // Interrupt 12 active\r
+#define NVIC_ACTIVE0_INT11 0x00000800 // Interrupt 11 active\r
+#define NVIC_ACTIVE0_INT10 0x00000400 // Interrupt 10 active\r
+#define NVIC_ACTIVE0_INT9 0x00000200 // Interrupt 9 active\r
+#define NVIC_ACTIVE0_INT8 0x00000100 // Interrupt 8 active\r
+#define NVIC_ACTIVE0_INT7 0x00000080 // Interrupt 7 active\r
+#define NVIC_ACTIVE0_INT6 0x00000040 // Interrupt 6 active\r
+#define NVIC_ACTIVE0_INT5 0x00000020 // Interrupt 5 active\r
+#define NVIC_ACTIVE0_INT4 0x00000010 // Interrupt 4 active\r
+#define NVIC_ACTIVE0_INT3 0x00000008 // Interrupt 3 active\r
+#define NVIC_ACTIVE0_INT2 0x00000004 // Interrupt 2 active\r
+#define NVIC_ACTIVE0_INT1 0x00000002 // Interrupt 1 active\r
+#define NVIC_ACTIVE0_INT0 0x00000001 // Interrupt 0 active\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_ACTIVE1 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_ACTIVE1_INT59 0x08000000 // Interrupt 59 active\r
+#define NVIC_ACTIVE1_INT58 0x04000000 // Interrupt 58 active\r
+#define NVIC_ACTIVE1_INT57 0x02000000 // Interrupt 57 active\r
+#define NVIC_ACTIVE1_INT56 0x01000000 // Interrupt 56 active\r
+#define NVIC_ACTIVE1_INT55 0x00800000 // Interrupt 55 active\r
+#define NVIC_ACTIVE1_INT54 0x00400000 // Interrupt 54 active\r
+#define NVIC_ACTIVE1_INT53 0x00200000 // Interrupt 53 active\r
+#define NVIC_ACTIVE1_INT52 0x00100000 // Interrupt 52 active\r
+#define NVIC_ACTIVE1_INT51 0x00080000 // Interrupt 51 active\r
+#define NVIC_ACTIVE1_INT50 0x00040000 // Interrupt 50 active\r
+#define NVIC_ACTIVE1_INT49 0x00020000 // Interrupt 49 active\r
+#define NVIC_ACTIVE1_INT48 0x00010000 // Interrupt 48 active\r
+#define NVIC_ACTIVE1_INT47 0x00008000 // Interrupt 47 active\r
+#define NVIC_ACTIVE1_INT46 0x00004000 // Interrupt 46 active\r
+#define NVIC_ACTIVE1_INT45 0x00002000 // Interrupt 45 active\r
+#define NVIC_ACTIVE1_INT44 0x00001000 // Interrupt 44 active\r
+#define NVIC_ACTIVE1_INT43 0x00000800 // Interrupt 43 active\r
+#define NVIC_ACTIVE1_INT42 0x00000400 // Interrupt 42 active\r
+#define NVIC_ACTIVE1_INT41 0x00000200 // Interrupt 41 active\r
+#define NVIC_ACTIVE1_INT40 0x00000100 // Interrupt 40 active\r
+#define NVIC_ACTIVE1_INT39 0x00000080 // Interrupt 39 active\r
+#define NVIC_ACTIVE1_INT38 0x00000040 // Interrupt 38 active\r
+#define NVIC_ACTIVE1_INT37 0x00000020 // Interrupt 37 active\r
+#define NVIC_ACTIVE1_INT36 0x00000010 // Interrupt 36 active\r
+#define NVIC_ACTIVE1_INT35 0x00000008 // Interrupt 35 active\r
+#define NVIC_ACTIVE1_INT34 0x00000004 // Interrupt 34 active\r
+#define NVIC_ACTIVE1_INT33 0x00000002 // Interrupt 33 active\r
+#define NVIC_ACTIVE1_INT32 0x00000001 // Interrupt 32 active\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_PRI0 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_PRI0_INT3_M 0xFF000000 // Interrupt 3 priority mask\r
+#define NVIC_PRI0_INT2_M 0x00FF0000 // Interrupt 2 priority mask\r
+#define NVIC_PRI0_INT1_M 0x0000FF00 // Interrupt 1 priority mask\r
+#define NVIC_PRI0_INT0_M 0x000000FF // Interrupt 0 priority mask\r
+#define NVIC_PRI0_INT3_S 24\r
+#define NVIC_PRI0_INT2_S 16\r
+#define NVIC_PRI0_INT1_S 8\r
+#define NVIC_PRI0_INT0_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_PRI1 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_PRI1_INT7_M 0xFF000000 // Interrupt 7 priority mask\r
+#define NVIC_PRI1_INT6_M 0x00FF0000 // Interrupt 6 priority mask\r
+#define NVIC_PRI1_INT5_M 0x0000FF00 // Interrupt 5 priority mask\r
+#define NVIC_PRI1_INT4_M 0x000000FF // Interrupt 4 priority mask\r
+#define NVIC_PRI1_INT7_S 24\r
+#define NVIC_PRI1_INT6_S 16\r
+#define NVIC_PRI1_INT5_S 8\r
+#define NVIC_PRI1_INT4_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_PRI2 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_PRI2_INT11_M 0xFF000000 // Interrupt 11 priority mask\r
+#define NVIC_PRI2_INT10_M 0x00FF0000 // Interrupt 10 priority mask\r
+#define NVIC_PRI2_INT9_M 0x0000FF00 // Interrupt 9 priority mask\r
+#define NVIC_PRI2_INT8_M 0x000000FF // Interrupt 8 priority mask\r
+#define NVIC_PRI2_INT11_S 24\r
+#define NVIC_PRI2_INT10_S 16\r
+#define NVIC_PRI2_INT9_S 8\r
+#define NVIC_PRI2_INT8_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_PRI3 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_PRI3_INT15_M 0xFF000000 // Interrupt 15 priority mask\r
+#define NVIC_PRI3_INT14_M 0x00FF0000 // Interrupt 14 priority mask\r
+#define NVIC_PRI3_INT13_M 0x0000FF00 // Interrupt 13 priority mask\r
+#define NVIC_PRI3_INT12_M 0x000000FF // Interrupt 12 priority mask\r
+#define NVIC_PRI3_INT15_S 24\r
+#define NVIC_PRI3_INT14_S 16\r
+#define NVIC_PRI3_INT13_S 8\r
+#define NVIC_PRI3_INT12_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_PRI4 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_PRI4_INT19_M 0xFF000000 // Interrupt 19 priority mask\r
+#define NVIC_PRI4_INT18_M 0x00FF0000 // Interrupt 18 priority mask\r
+#define NVIC_PRI4_INT17_M 0x0000FF00 // Interrupt 17 priority mask\r
+#define NVIC_PRI4_INT16_M 0x000000FF // Interrupt 16 priority mask\r
+#define NVIC_PRI4_INT19_S 24\r
+#define NVIC_PRI4_INT18_S 16\r
+#define NVIC_PRI4_INT17_S 8\r
+#define NVIC_PRI4_INT16_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_PRI5 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_PRI5_INT23_M 0xFF000000 // Interrupt 23 priority mask\r
+#define NVIC_PRI5_INT22_M 0x00FF0000 // Interrupt 22 priority mask\r
+#define NVIC_PRI5_INT21_M 0x0000FF00 // Interrupt 21 priority mask\r
+#define NVIC_PRI5_INT20_M 0x000000FF // Interrupt 20 priority mask\r
+#define NVIC_PRI5_INT23_S 24\r
+#define NVIC_PRI5_INT22_S 16\r
+#define NVIC_PRI5_INT21_S 8\r
+#define NVIC_PRI5_INT20_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_PRI6 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_PRI6_INT27_M 0xFF000000 // Interrupt 27 priority mask\r
+#define NVIC_PRI6_INT26_M 0x00FF0000 // Interrupt 26 priority mask\r
+#define NVIC_PRI6_INT25_M 0x0000FF00 // Interrupt 25 priority mask\r
+#define NVIC_PRI6_INT24_M 0x000000FF // Interrupt 24 priority mask\r
+#define NVIC_PRI6_INT27_S 24\r
+#define NVIC_PRI6_INT26_S 16\r
+#define NVIC_PRI6_INT25_S 8\r
+#define NVIC_PRI6_INT24_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_PRI7 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_PRI7_INT31_M 0xFF000000 // Interrupt 31 priority mask\r
+#define NVIC_PRI7_INT30_M 0x00FF0000 // Interrupt 30 priority mask\r
+#define NVIC_PRI7_INT29_M 0x0000FF00 // Interrupt 29 priority mask\r
+#define NVIC_PRI7_INT28_M 0x000000FF // Interrupt 28 priority mask\r
+#define NVIC_PRI7_INT31_S 24\r
+#define NVIC_PRI7_INT30_S 16\r
+#define NVIC_PRI7_INT29_S 8\r
+#define NVIC_PRI7_INT28_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_PRI8 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_PRI8_INT35_M 0xFF000000 // Interrupt 35 priority mask\r
+#define NVIC_PRI8_INT34_M 0x00FF0000 // Interrupt 34 priority mask\r
+#define NVIC_PRI8_INT33_M 0x0000FF00 // Interrupt 33 priority mask\r
+#define NVIC_PRI8_INT32_M 0x000000FF // Interrupt 32 priority mask\r
+#define NVIC_PRI8_INT35_S 24\r
+#define NVIC_PRI8_INT34_S 16\r
+#define NVIC_PRI8_INT33_S 8\r
+#define NVIC_PRI8_INT32_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_PRI9 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_PRI9_INT39_M 0xFF000000 // Interrupt 39 priority mask\r
+#define NVIC_PRI9_INT38_M 0x00FF0000 // Interrupt 38 priority mask\r
+#define NVIC_PRI9_INT37_M 0x0000FF00 // Interrupt 37 priority mask\r
+#define NVIC_PRI9_INT36_M 0x000000FF // Interrupt 36 priority mask\r
+#define NVIC_PRI9_INT39_S 24\r
+#define NVIC_PRI9_INT38_S 16\r
+#define NVIC_PRI9_INT37_S 8\r
+#define NVIC_PRI9_INT36_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_PRI10 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_PRI10_INT43_M 0xFF000000 // Interrupt 43 priority mask\r
+#define NVIC_PRI10_INT42_M 0x00FF0000 // Interrupt 42 priority mask\r
+#define NVIC_PRI10_INT41_M 0x0000FF00 // Interrupt 41 priority mask\r
+#define NVIC_PRI10_INT40_M 0x000000FF // Interrupt 40 priority mask\r
+#define NVIC_PRI10_INT43_S 24\r
+#define NVIC_PRI10_INT42_S 16\r
+#define NVIC_PRI10_INT41_S 8\r
+#define NVIC_PRI10_INT40_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_CPUID register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_CPUID_IMP_M 0xFF000000 // Implementer\r
+#define NVIC_CPUID_VAR_M 0x00F00000 // Variant\r
+#define NVIC_CPUID_PARTNO_M 0x0000FFF0 // Processor part number\r
+#define NVIC_CPUID_REV_M 0x0000000F // Revision\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_INT_CTRL register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_INT_CTRL_NMI_SET 0x80000000 // Pend a NMI\r
+#define NVIC_INT_CTRL_PEND_SV 0x10000000 // Pend a PendSV\r
+#define NVIC_INT_CTRL_UNPEND_SV 0x08000000 // Unpend a PendSV\r
+#define NVIC_INT_CTRL_ISR_PRE 0x00800000 // Debug interrupt handling\r
+#define NVIC_INT_CTRL_ISR_PEND 0x00400000 // Debug interrupt pending\r
+#define NVIC_INT_CTRL_VEC_PEN_M 0x003FF000 // Highest pending exception\r
+#define NVIC_INT_CTRL_RET_BASE 0x00000800 // Return to base\r
+#define NVIC_INT_CTRL_VEC_ACT_M 0x000003FF // Current active exception\r
+#define NVIC_INT_CTRL_VEC_PEN_S 12\r
+#define NVIC_INT_CTRL_VEC_ACT_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_VTABLE register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_VTABLE_BASE 0x20000000 // Vector table base\r
+#define NVIC_VTABLE_OFFSET_M 0x1FFFFF00 // Vector table offset\r
+#define NVIC_VTABLE_OFFSET_S 8\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_APINT register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_APINT_VECTKEY_M 0xFFFF0000 // Vector key mask\r
+#define NVIC_APINT_VECTKEY 0x05FA0000 // Vector key\r
+#define NVIC_APINT_ENDIANESS 0x00008000 // Data endianess\r
+#define NVIC_APINT_PRIGROUP_M 0x00000700 // Priority group\r
+#define NVIC_APINT_PRIGROUP_7_1 0x00000000 // Priority group 7.1 split\r
+#define NVIC_APINT_PRIGROUP_6_2 0x00000100 // Priority group 6.2 split\r
+#define NVIC_APINT_PRIGROUP_5_3 0x00000200 // Priority group 5.3 split\r
+#define NVIC_APINT_PRIGROUP_4_4 0x00000300 // Priority group 4.4 split\r
+#define NVIC_APINT_PRIGROUP_3_5 0x00000400 // Priority group 3.5 split\r
+#define NVIC_APINT_PRIGROUP_2_6 0x00000500 // Priority group 2.6 split\r
+#define NVIC_APINT_PRIGROUP_1_7 0x00000600 // Priority group 1.7 split\r
+#define NVIC_APINT_PRIGROUP_0_8 0x00000700 // Priority group 0.8 split\r
+#define NVIC_APINT_SYSRESETREQ 0x00000004 // System reset request\r
+#define NVIC_APINT_VECT_CLR_ACT 0x00000002 // Clear active NMI/fault info\r
+#define NVIC_APINT_VECT_RESET 0x00000001 // System reset\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_SYS_CTRL register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_SYS_CTRL_SEVONPEND 0x00000010 // Wakeup on pend\r
+#define NVIC_SYS_CTRL_SLEEPDEEP 0x00000004 // Deep sleep enable\r
+#define NVIC_SYS_CTRL_SLEEPEXIT 0x00000002 // Sleep on ISR exit\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_CFG_CTRL register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_CFG_CTRL_BFHFNMIGN 0x00000100 // Ignore bus fault in NMI/fault\r
+#define NVIC_CFG_CTRL_DIV0 0x00000010 // Trap on divide by 0\r
+#define NVIC_CFG_CTRL_UNALIGNED 0x00000008 // Trap on unaligned access\r
+#define NVIC_CFG_CTRL_DEEP_PEND 0x00000004 // Allow deep interrupt trigger\r
+#define NVIC_CFG_CTRL_MAIN_PEND 0x00000002 // Allow main interrupt trigger\r
+#define NVIC_CFG_CTRL_BASE_THR 0x00000001 // Thread state control\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_SYS_PRI1 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_SYS_PRI1_RES_M 0xFF000000 // Priority of reserved handler\r
+#define NVIC_SYS_PRI1_USAGE_M 0x00FF0000 // Priority of usage fault handler\r
+#define NVIC_SYS_PRI1_BUS_M 0x0000FF00 // Priority of bus fault handler\r
+#define NVIC_SYS_PRI1_MEM_M 0x000000FF // Priority of mem manage handler\r
+#define NVIC_SYS_PRI1_USAGE_S 16\r
+#define NVIC_SYS_PRI1_BUS_S 8\r
+#define NVIC_SYS_PRI1_MEM_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_SYS_PRI2 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_SYS_PRI2_SVC_M 0xFF000000 // Priority of SVCall handler\r
+#define NVIC_SYS_PRI2_RES_M 0x00FFFFFF // Priority of reserved handlers\r
+#define NVIC_SYS_PRI2_SVC_S 24\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_SYS_PRI3 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_SYS_PRI3_TICK_M 0xFF000000 // Priority of Sys Tick handler\r
+#define NVIC_SYS_PRI3_PENDSV_M 0x00FF0000 // Priority of PendSV handler\r
+#define NVIC_SYS_PRI3_RES_M 0x0000FF00 // Priority of reserved handler\r
+#define NVIC_SYS_PRI3_DEBUG_M 0x000000FF // Priority of debug handler\r
+#define NVIC_SYS_PRI3_TICK_S 24\r
+#define NVIC_SYS_PRI3_PENDSV_S 16\r
+#define NVIC_SYS_PRI3_DEBUG_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_SYS_HND_CTRL register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_SYS_HND_CTRL_USAGE 0x00040000 // Usage fault enable\r
+#define NVIC_SYS_HND_CTRL_BUS 0x00020000 // Bus fault enable\r
+#define NVIC_SYS_HND_CTRL_MEM 0x00010000 // Mem manage fault enable\r
+#define NVIC_SYS_HND_CTRL_SVC 0x00008000 // SVCall is pended\r
+#define NVIC_SYS_HND_CTRL_BUSP 0x00004000 // Bus fault is pended\r
+#define NVIC_SYS_HND_CTRL_TICK 0x00000800 // Sys tick is active\r
+#define NVIC_SYS_HND_CTRL_PNDSV 0x00000400 // PendSV is active\r
+#define NVIC_SYS_HND_CTRL_MON 0x00000100 // Monitor is active\r
+#define NVIC_SYS_HND_CTRL_SVCA 0x00000080 // SVCall is active\r
+#define NVIC_SYS_HND_CTRL_USGA 0x00000008 // Usage fault is active\r
+#define NVIC_SYS_HND_CTRL_BUSA 0x00000002 // Bus fault is active\r
+#define NVIC_SYS_HND_CTRL_MEMA 0x00000001 // Mem manage is active\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_FAULT_STAT register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_FAULT_STAT_DIV0 0x02000000 // Divide by zero fault\r
+#define NVIC_FAULT_STAT_UNALIGN 0x01000000 // Unaligned access fault\r
+#define NVIC_FAULT_STAT_NOCP 0x00080000 // No coprocessor fault\r
+#define NVIC_FAULT_STAT_INVPC 0x00040000 // Invalid PC fault\r
+#define NVIC_FAULT_STAT_INVSTAT 0x00020000 // Invalid state fault\r
+#define NVIC_FAULT_STAT_UNDEF 0x00010000 // Undefined instruction fault\r
+#define NVIC_FAULT_STAT_BFARV 0x00008000 // BFAR is valid\r
+#define NVIC_FAULT_STAT_BSTKE 0x00001000 // Stack bus fault\r
+#define NVIC_FAULT_STAT_BUSTKE 0x00000800 // Unstack bus fault\r
+#define NVIC_FAULT_STAT_IMPRE 0x00000400 // Imprecise data bus error\r
+#define NVIC_FAULT_STAT_PRECISE 0x00000200 // Precise data bus error\r
+#define NVIC_FAULT_STAT_IBUS 0x00000100 // Instruction bus fault\r
+#define NVIC_FAULT_STAT_MMARV 0x00000080 // MMAR is valid\r
+#define NVIC_FAULT_STAT_MSTKE 0x00000010 // Stack access violation\r
+#define NVIC_FAULT_STAT_MUSTKE 0x00000008 // Unstack access violation\r
+#define NVIC_FAULT_STAT_DERR 0x00000002 // Data access violation\r
+#define NVIC_FAULT_STAT_IERR 0x00000001 // Instruction access violation\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_HFAULT_STAT register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_HFAULT_STAT_DBG 0x80000000 // Debug event\r
+#define NVIC_HFAULT_STAT_FORCED 0x40000000 // Cannot execute fault handler\r
+#define NVIC_HFAULT_STAT_VECT 0x00000002 // Vector table read fault\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_DEBUG_STAT register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_DEBUG_STAT_EXTRNL 0x00000010 // EDBGRQ asserted\r
+#define NVIC_DEBUG_STAT_VCATCH 0x00000008 // Vector catch\r
+#define NVIC_DEBUG_STAT_DWTTRAP 0x00000004 // DWT match\r
+#define NVIC_DEBUG_STAT_BKPT 0x00000002 // Breakpoint instruction\r
+#define NVIC_DEBUG_STAT_HALTED 0x00000001 // Halt request\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_MM_ADDR register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_MM_ADDR_M 0xFFFFFFFF // Data fault address\r
+#define NVIC_MM_ADDR_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_FAULT_ADDR register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_FAULT_ADDR_M 0xFFFFFFFF // Data bus fault address\r
+#define NVIC_FAULT_ADDR_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_EXC_STACK register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_EXC_STACK_DEEP 0x00000001 // Exception stack\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_EXC_NUM register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_EXC_NUM_M 0x000003FF // Exception number\r
+#define NVIC_EXC_NUM_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_COPRO register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_COPRO_15_M 0xC0000000 // Coprocessor 15 access mask\r
+#define NVIC_COPRO_15_DENIED 0x00000000 // Coprocessor 15 access denied\r
+#define NVIC_COPRO_15_PRIV 0x40000000 // Coprocessor 15 privileged addess\r
+#define NVIC_COPRO_15_FULL 0xC0000000 // Coprocessor 15 full access\r
+#define NVIC_COPRO_14_M 0x30000000 // Coprocessor 14 access mask\r
+#define NVIC_COPRO_14_DENIED 0x00000000 // Coprocessor 14 access denied\r
+#define NVIC_COPRO_14_PRIV 0x10000000 // Coprocessor 14 privileged addess\r
+#define NVIC_COPRO_14_FULL 0x30000000 // Coprocessor 14 full access\r
+#define NVIC_COPRO_13_M 0x0C000000 // Coprocessor 13 access mask\r
+#define NVIC_COPRO_13_DENIED 0x00000000 // Coprocessor 13 access denied\r
+#define NVIC_COPRO_13_PRIV 0x04000000 // Coprocessor 13 privileged addess\r
+#define NVIC_COPRO_13_FULL 0x0C000000 // Coprocessor 13 full access\r
+#define NVIC_COPRO_12_M 0x03000000 // Coprocessor 12 access mask\r
+#define NVIC_COPRO_12_DENIED 0x00000000 // Coprocessor 12 access denied\r
+#define NVIC_COPRO_12_PRIV 0x01000000 // Coprocessor 12 privileged addess\r
+#define NVIC_COPRO_12_FULL 0x03000000 // Coprocessor 12 full access\r
+#define NVIC_COPRO_11_M 0x00C00000 // Coprocessor 11 access mask\r
+#define NVIC_COPRO_11_DENIED 0x00000000 // Coprocessor 11 access denied\r
+#define NVIC_COPRO_11_PRIV 0x00400000 // Coprocessor 11 privileged addess\r
+#define NVIC_COPRO_11_FULL 0x00C00000 // Coprocessor 11 full access\r
+#define NVIC_COPRO_10_M 0x00300000 // Coprocessor 10 access mask\r
+#define NVIC_COPRO_10_DENIED 0x00000000 // Coprocessor 10 access denied\r
+#define NVIC_COPRO_10_PRIV 0x00100000 // Coprocessor 10 privileged addess\r
+#define NVIC_COPRO_10_FULL 0x00300000 // Coprocessor 10 full access\r
+#define NVIC_COPRO_9_M 0x000C0000 // Coprocessor 9 access mask\r
+#define NVIC_COPRO_9_DENIED 0x00000000 // Coprocessor 9 access denied\r
+#define NVIC_COPRO_9_PRIV 0x00040000 // Coprocessor 9 privileged addess\r
+#define NVIC_COPRO_9_FULL 0x000C0000 // Coprocessor 9 full access\r
+#define NVIC_COPRO_8_M 0x00030000 // Coprocessor 8 access mask\r
+#define NVIC_COPRO_8_DENIED 0x00000000 // Coprocessor 8 access denied\r
+#define NVIC_COPRO_8_PRIV 0x00010000 // Coprocessor 8 privileged addess\r
+#define NVIC_COPRO_8_FULL 0x00030000 // Coprocessor 8 full access\r
+#define NVIC_COPRO_7_M 0x0000C000 // Coprocessor 7 access mask\r
+#define NVIC_COPRO_7_DENIED 0x00000000 // Coprocessor 7 access denied\r
+#define NVIC_COPRO_7_PRIV 0x00004000 // Coprocessor 7 privileged addess\r
+#define NVIC_COPRO_7_FULL 0x0000C000 // Coprocessor 7 full access\r
+#define NVIC_COPRO_6_M 0x00003000 // Coprocessor 6 access mask\r
+#define NVIC_COPRO_6_DENIED 0x00000000 // Coprocessor 6 access denied\r
+#define NVIC_COPRO_6_PRIV 0x00001000 // Coprocessor 6 privileged addess\r
+#define NVIC_COPRO_6_FULL 0x00003000 // Coprocessor 6 full access\r
+#define NVIC_COPRO_5_M 0x00000C00 // Coprocessor 5 access mask\r
+#define NVIC_COPRO_5_DENIED 0x00000000 // Coprocessor 5 access denied\r
+#define NVIC_COPRO_5_PRIV 0x00000400 // Coprocessor 5 privileged addess\r
+#define NVIC_COPRO_5_FULL 0x00000C00 // Coprocessor 5 full access\r
+#define NVIC_COPRO_4_M 0x00000300 // Coprocessor 4 access mask\r
+#define NVIC_COPRO_4_DENIED 0x00000000 // Coprocessor 4 access denied\r
+#define NVIC_COPRO_4_PRIV 0x00000100 // Coprocessor 4 privileged addess\r
+#define NVIC_COPRO_4_FULL 0x00000300 // Coprocessor 4 full access\r
+#define NVIC_COPRO_3_M 0x000000C0 // Coprocessor 3 access mask\r
+#define NVIC_COPRO_3_DENIED 0x00000000 // Coprocessor 3 access denied\r
+#define NVIC_COPRO_3_PRIV 0x00000040 // Coprocessor 3 privileged addess\r
+#define NVIC_COPRO_3_FULL 0x000000C0 // Coprocessor 3 full access\r
+#define NVIC_COPRO_2_M 0x00000030 // Coprocessor 2 access mask\r
+#define NVIC_COPRO_2_DENIED 0x00000000 // Coprocessor 2 access denied\r
+#define NVIC_COPRO_2_PRIV 0x00000010 // Coprocessor 2 privileged addess\r
+#define NVIC_COPRO_2_FULL 0x00000030 // Coprocessor 2 full access\r
+#define NVIC_COPRO_1_M 0x0000000C // Coprocessor 1 access mask\r
+#define NVIC_COPRO_1_DENIED 0x00000000 // Coprocessor 1 access denied\r
+#define NVIC_COPRO_1_PRIV 0x00000004 // Coprocessor 1 privileged addess\r
+#define NVIC_COPRO_1_FULL 0x0000000C // Coprocessor 1 full access\r
+#define NVIC_COPRO_0_M 0x00000003 // Coprocessor 0 access mask\r
+#define NVIC_COPRO_0_DENIED 0x00000000 // Coprocessor 0 access denied\r
+#define NVIC_COPRO_0_PRIV 0x00000001 // Coprocessor 0 privileged addess\r
+#define NVIC_COPRO_0_FULL 0x00000003 // Coprocessor 0 full access\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_MPU_TYPE register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_MPU_TYPE_IREGION_M 0x00FF0000 // Number of I regions\r
+#define NVIC_MPU_TYPE_DREGION_M 0x0000FF00 // Number of D regions\r
+#define NVIC_MPU_TYPE_SEPARATE 0x00000001 // Separate or unified MPU\r
+#define NVIC_MPU_TYPE_IREGION_S 16\r
+#define NVIC_MPU_TYPE_DREGION_S 8\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_MPU_CTRL register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_MPU_CTRL_HFNMIENA 0x00000002 // MPU enabled during faults\r
+#define NVIC_MPU_CTRL_ENABLE 0x00000001 // MPU enable\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_MPU_NUMBER register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_MPU_NUMBER_M 0x000000FF // MPU region to access\r
+#define NVIC_MPU_NUMBER_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_MPU_BASE register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_MPU_BASE_ADDR_M 0xFFFFFF00 // Base address\r
+#define NVIC_MPU_BASE_VALID 0x00000010 // Region number valid\r
+#define NVIC_MPU_BASE_REGION_M 0x0000000F // Region number\r
+#define NVIC_MPU_BASE_ADDR_S 8\r
+#define NVIC_MPU_BASE_REGION_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_MPU_ATTR register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_MPU_ATTR_ATTRS 0xFFFF0000 // Attributes\r
+#define NVIC_MPU_ATTR_SRD 0x0000FF00 // Sub-region disable\r
+#define NVIC_MPU_ATTR_SZENABLE 0x000000FF // Region size\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_DBG_CTRL register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_DBG_CTRL_DBGKEY_M 0xFFFF0000 // Debug key mask\r
+#define NVIC_DBG_CTRL_DBGKEY 0xA05F0000 // Debug key\r
+#define NVIC_DBG_CTRL_MON_PEND 0x00008000 // Pend the monitor\r
+#define NVIC_DBG_CTRL_MON_REQ 0x00004000 // Monitor request\r
+#define NVIC_DBG_CTRL_MON_EN 0x00002000 // Debug monitor enable\r
+#define NVIC_DBG_CTRL_MONSTEP 0x00001000 // Monitor step the core\r
+#define NVIC_DBG_CTRL_S_SLEEP 0x00000400 // Core is sleeping\r
+#define NVIC_DBG_CTRL_S_HALT 0x00000200 // Core status on halt\r
+#define NVIC_DBG_CTRL_S_REGRDY 0x00000100 // Register read/write available\r
+#define NVIC_DBG_CTRL_S_LOCKUP 0x00000080 // Core is locked up\r
+#define NVIC_DBG_CTRL_C_RESET 0x00000010 // Reset the core\r
+#define NVIC_DBG_CTRL_C_MASKINT 0x00000008 // Mask interrupts when stepping\r
+#define NVIC_DBG_CTRL_C_STEP 0x00000004 // Step the core\r
+#define NVIC_DBG_CTRL_C_HALT 0x00000002 // Halt the core\r
+#define NVIC_DBG_CTRL_C_DEBUGEN 0x00000001 // Enable debug\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_DBG_XFER register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_DBG_XFER_REG_WNR 0x00010000 // Write or not read\r
+#define NVIC_DBG_XFER_REG_SEL_M 0x0000001F // Register\r
+#define NVIC_DBG_XFER_REG_R0 0x00000000 // Register R0\r
+#define NVIC_DBG_XFER_REG_R1 0x00000001 // Register R1\r
+#define NVIC_DBG_XFER_REG_R2 0x00000002 // Register R2\r
+#define NVIC_DBG_XFER_REG_R3 0x00000003 // Register R3\r
+#define NVIC_DBG_XFER_REG_R4 0x00000004 // Register R4\r
+#define NVIC_DBG_XFER_REG_R5 0x00000005 // Register R5\r
+#define NVIC_DBG_XFER_REG_R6 0x00000006 // Register R6\r
+#define NVIC_DBG_XFER_REG_R7 0x00000007 // Register R7\r
+#define NVIC_DBG_XFER_REG_R8 0x00000008 // Register R8\r
+#define NVIC_DBG_XFER_REG_R9 0x00000009 // Register R9\r
+#define NVIC_DBG_XFER_REG_R10 0x0000000A // Register R10\r
+#define NVIC_DBG_XFER_REG_R11 0x0000000B // Register R11\r
+#define NVIC_DBG_XFER_REG_R12 0x0000000C // Register R12\r
+#define NVIC_DBG_XFER_REG_R13 0x0000000D // Register R13\r
+#define NVIC_DBG_XFER_REG_R14 0x0000000E // Register R14\r
+#define NVIC_DBG_XFER_REG_R15 0x0000000F // Register R15\r
+#define NVIC_DBG_XFER_REG_FLAGS 0x00000010 // xPSR/Flags register\r
+#define NVIC_DBG_XFER_REG_MSP 0x00000011 // Main SP\r
+#define NVIC_DBG_XFER_REG_PSP 0x00000012 // Process SP\r
+#define NVIC_DBG_XFER_REG_DSP 0x00000013 // Deep SP\r
+#define NVIC_DBG_XFER_REG_CFBP 0x00000014 // Control/Fault/BasePri/PriMask\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_DBG_DATA register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_DBG_DATA_M 0xFFFFFFFF // Data temporary cache\r
+#define NVIC_DBG_DATA_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_DBG_INT register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_DBG_INT_HARDERR 0x00000400 // Debug trap on hard fault\r
+#define NVIC_DBG_INT_INTERR 0x00000200 // Debug trap on interrupt errors\r
+#define NVIC_DBG_INT_BUSERR 0x00000100 // Debug trap on bus error\r
+#define NVIC_DBG_INT_STATERR 0x00000080 // Debug trap on usage fault state\r
+#define NVIC_DBG_INT_CHKERR 0x00000040 // Debug trap on usage fault check\r
+#define NVIC_DBG_INT_NOCPERR 0x00000020 // Debug trap on coprocessor error\r
+#define NVIC_DBG_INT_MMERR 0x00000010 // Debug trap on mem manage fault\r
+#define NVIC_DBG_INT_RESET 0x00000008 // Core reset status\r
+#define NVIC_DBG_INT_RSTPENDCLR 0x00000004 // Clear pending core reset\r
+#define NVIC_DBG_INT_RSTPENDING 0x00000002 // Core reset is pending\r
+#define NVIC_DBG_INT_RSTVCATCH 0x00000001 // Reset vector catch\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_SW_TRIG register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_SW_TRIG_INTID_M 0x000003FF // Interrupt to trigger\r
+#define NVIC_SW_TRIG_INTID_S 0\r
+\r
+#endif // __HW_NVIC_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_pwm.h - Defines and Macros for Pulse Width Modulation (PWM) ports\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_PWM_H__\r
+#define __HW_PWM_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// PWM Module Register Offsets.\r
+//\r
+//*****************************************************************************\r
+#define PWM_O_CTL 0x00000000 // PWM Master Control register\r
+#define PWM_O_SYNC 0x00000004 // PWM Time Base Sync register\r
+#define PWM_O_ENABLE 0x00000008 // PWM Output Enable register\r
+#define PWM_O_INVERT 0x0000000C // PWM Output Inversion register\r
+#define PWM_O_FAULT 0x00000010 // PWM Output Fault register\r
+#define PWM_O_INTEN 0x00000014 // PWM Interrupt Enable register\r
+#define PWM_O_RIS 0x00000018 // PWM Interrupt Raw Status reg.\r
+#define PWM_O_ISC 0x0000001C // PWM Interrupt Status register\r
+#define PWM_O_STATUS 0x00000020 // PWM Status register\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the PWM Master Control register.\r
+//\r
+//*****************************************************************************\r
+#define PWM_CTL_GLOBAL_SYNC2 0x00000004 // Global sync generator 2\r
+#define PWM_CTL_GLOBAL_SYNC1 0x00000002 // Global sync generator 1\r
+#define PWM_CTL_GLOBAL_SYNC0 0x00000001 // Global sync generator 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the PWM Time Base Sync register.\r
+//\r
+//*****************************************************************************\r
+#define PWM_SYNC_SYNC2 0x00000004 // Reset generator 2 counter\r
+#define PWM_SYNC_SYNC1 0x00000002 // Reset generator 1 counter\r
+#define PWM_SYNC_SYNC0 0x00000001 // Reset generator 0 counter\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the PWM Output Enable register.\r
+//\r
+//*****************************************************************************\r
+#define PWM_ENABLE_PWM5EN 0x00000020 // PWM5 pin enable\r
+#define PWM_ENABLE_PWM4EN 0x00000010 // PWM4 pin enable\r
+#define PWM_ENABLE_PWM3EN 0x00000008 // PWM3 pin enable\r
+#define PWM_ENABLE_PWM2EN 0x00000004 // PWM2 pin enable\r
+#define PWM_ENABLE_PWM1EN 0x00000002 // PWM1 pin enable\r
+#define PWM_ENABLE_PWM0EN 0x00000001 // PWM0 pin enable\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the PWM Inversion register.\r
+//\r
+//*****************************************************************************\r
+#define PWM_INVERT_PWM5INV 0x00000020 // PWM5 pin invert\r
+#define PWM_INVERT_PWM4INV 0x00000010 // PWM4 pin invert\r
+#define PWM_INVERT_PWM3INV 0x00000008 // PWM3 pin invert\r
+#define PWM_INVERT_PWM2INV 0x00000004 // PWM2 pin invert\r
+#define PWM_INVERT_PWM1INV 0x00000002 // PWM1 pin invert\r
+#define PWM_INVERT_PWM0INV 0x00000001 // PWM0 pin invert\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the PWM Fault register.\r
+//\r
+//*****************************************************************************\r
+#define PWM_FAULT_FAULT5 0x00000020 // PWM5 pin fault\r
+#define PWM_FAULT_FAULT4 0x00000010 // PWM5 pin fault\r
+#define PWM_FAULT_FAULT3 0x00000008 // PWM5 pin fault\r
+#define PWM_FAULT_FAULT2 0x00000004 // PWM5 pin fault\r
+#define PWM_FAULT_FAULT1 0x00000002 // PWM5 pin fault\r
+#define PWM_FAULT_FAULT0 0x00000001 // PWM5 pin fault\r
+\r
+//*****************************************************************************\r
+//\r
+// PWM Interrupt Register bit definitions.\r
+//\r
+//*****************************************************************************\r
+#define PWM_INT_INTFAULT 0x00010000 // Fault interrupt pending\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the PWM Status register.\r
+//\r
+//*****************************************************************************\r
+#define PWM_STATUS_FAULT 0x00000001 // Fault status\r
+\r
+//*****************************************************************************\r
+//\r
+// PWM Generator standard offsets.\r
+//\r
+//*****************************************************************************\r
+#define PWM_GEN_0_OFFSET 0x00000040 // PWM0 base\r
+#define PWM_GEN_1_OFFSET 0x00000080 // PWM1 base\r
+#define PWM_GEN_2_OFFSET 0x000000C0 // PWM2 base\r
+\r
+#define PWM_O_X_CTL 0x00000000 // Gen Control Reg\r
+#define PWM_O_X_INTEN 0x00000004 // Gen Int/Trig Enable Reg\r
+#define PWM_O_X_RIS 0x00000008 // Gen Raw Int Status Reg\r
+#define PWM_O_X_ISC 0x0000000C // Gen Int Status Reg\r
+#define PWM_O_X_LOAD 0x00000010 // Gen Load Reg\r
+#define PWM_O_X_COUNT 0x00000014 // Gen Counter Reg\r
+#define PWM_O_X_CMPA 0x00000018 // Gen Compare A Reg\r
+#define PWM_O_X_CMPB 0x0000001C // Gen Compare B Reg\r
+#define PWM_O_X_GENA 0x00000020 // Gen Generator A Ctrl Reg\r
+#define PWM_O_X_GENB 0x00000024 // Gen Generator B Ctrl Reg\r
+#define PWM_O_X_DBCTL 0x00000028 // Gen Dead Band Ctrl Reg\r
+#define PWM_O_X_DBRISE 0x0000002C // Gen DB Rising Edge Delay Reg\r
+#define PWM_O_X_DBFALL 0x00000030 // Gen DB Falling Edge Delay Reg\r
+\r
+//*****************************************************************************\r
+//\r
+// PWM_X Control Register bit definitions.\r
+//\r
+//*****************************************************************************\r
+#define PWM_X_CTL_ENABLE 0x00000001 // Master enable for gen block\r
+#define PWM_X_CTL_MODE 0x00000002 // Counter mode, down or up/down\r
+#define PWM_X_CTL_DEBUG 0x00000004 // Debug mode\r
+#define PWM_X_CTL_LOADUPD 0x00000008 // Update mode for the load reg\r
+#define PWM_X_CTL_CMPAUPD 0x00000010 // Update mode for comp A reg\r
+#define PWM_X_CTL_CMPBUPD 0x00000020 // Update mode for comp B reg\r
+\r
+//*****************************************************************************\r
+//\r
+// PWM_X Interrupt/Trigger Enable Register bit definitions.\r
+//\r
+//*****************************************************************************\r
+#define PWM_X_INTEN_INTCNTZERO 0x00000001 // Int if COUNT = 0\r
+#define PWM_X_INTEN_INTCNTLOAD 0x00000002 // Int if COUNT = LOAD\r
+#define PWM_X_INTEN_INTCMPAU 0x00000004 // Int if COUNT = CMPA U\r
+#define PWM_X_INTEN_INTCMPAD 0x00000008 // Int if COUNT = CMPA D\r
+#define PWM_X_INTEN_INTCMPBU 0x00000010 // Int if COUNT = CMPA U\r
+#define PWM_X_INTEN_INTCMPBD 0x00000020 // Int if COUNT = CMPA D\r
+#define PWM_X_INTEN_TRCNTZERO 0x00000100 // Trig if COUNT = 0\r
+#define PWM_X_INTEN_TRCNTLOAD 0x00000200 // Trig if COUNT = LOAD\r
+#define PWM_X_INTEN_TRCMPAU 0x00000400 // Trig if COUNT = CMPA U\r
+#define PWM_X_INTEN_TRCMPAD 0x00000800 // Trig if COUNT = CMPA D\r
+#define PWM_X_INTEN_TRCMPBU 0x00001000 // Trig if COUNT = CMPA U\r
+#define PWM_X_INTEN_TRCMPBD 0x00002000 // Trig if COUNT = CMPA D\r
+\r
+//*****************************************************************************\r
+//\r
+// PWM_X Raw Interrupt Status Register bit definitions.\r
+//\r
+//*****************************************************************************\r
+#define PWM_X_RIS_INTCNTZERO 0x00000001 // PWM_X_COUNT = 0 int\r
+#define PWM_X_RIS_INTCNTLOAD 0x00000002 // PWM_X_COUNT = PWM_X_LOAD int\r
+#define PWM_X_RIS_INTCMPAU 0x00000004 // PWM_X_COUNT = PWM_X_CMPA U int\r
+#define PWM_X_RIS_INTCMPAD 0x00000008 // PWM_X_COUNT = PWM_X_CMPA D int\r
+#define PWM_X_RIS_INTCMPBU 0x00000010 // PWM_X_COUNT = PWM_X_CMPB U int\r
+#define PWM_X_RIS_INTCMPBD 0x00000020 // PWM_X_COUNT = PWM_X_CMPB D int\r
+\r
+//*****************************************************************************\r
+//\r
+// PWM_X Interrupt Status Register bit definitions.\r
+//\r
+//*****************************************************************************\r
+#define PWM_X_INT_INTCNTZERO 0x00000001 // PWM_X_COUNT = 0 received\r
+#define PWM_X_INT_INTCNTLOAD 0x00000002 // PWM_X_COUNT = PWM_X_LOAD rcvd\r
+#define PWM_X_INT_INTCMPAU 0x00000004 // PWM_X_COUNT = PWM_X_CMPA U rcvd\r
+#define PWM_X_INT_INTCMPAD 0x00000008 // PWM_X_COUNT = PWM_X_CMPA D rcvd\r
+#define PWM_X_INT_INTCMPBU 0x00000010 // PWM_X_COUNT = PWM_X_CMPB U rcvd\r
+#define PWM_X_INT_INTCMPBD 0x00000020 // PWM_X_COUNT = PWM_X_CMPB D rcvd\r
+\r
+//*****************************************************************************\r
+//\r
+// PWM_X Generator A/B Control Register bit definitions.\r
+//\r
+//*****************************************************************************\r
+#define PWM_X_GEN_Y_ACTZERO 0x00000003 // Act PWM_X_COUNT = 0\r
+#define PWM_X_GEN_Y_ACTLOAD 0x0000000C // Act PWM_X_COUNT = PWM_X_LOAD\r
+#define PWM_X_GEN_Y_ACTCMPAU 0x00000030 // Act PWM_X_COUNT = PWM_X_CMPA U\r
+#define PWM_X_GEN_Y_ACTCMPAD 0x000000C0 // Act PWM_X_COUNT = PWM_X_CMPA D\r
+#define PWM_X_GEN_Y_ACTCMPBU 0x00000300 // Act PWM_X_COUNT = PWM_X_CMPB U\r
+#define PWM_X_GEN_Y_ACTCMPBD 0x00000C00 // Act PWM_X_COUNT = PWM_X_CMPB D\r
+\r
+//*****************************************************************************\r
+//\r
+// PWM_X Generator A/B Control Register action definitions.\r
+//\r
+//*****************************************************************************\r
+#define PWM_GEN_ACT_NONE 0x0 // Do nothing\r
+#define PWM_GEN_ACT_INV 0x1 // Invert the output signal\r
+#define PWM_GEN_ACT_ZERO 0x2 // Set the output signal to zero\r
+#define PWM_GEN_ACT_ONE 0x3 // Set the output signal to one\r
+#define PWM_GEN_ACT_ZERO_SHIFT 0 // Shift amount for the zero action\r
+#define PWM_GEN_ACT_LOAD_SHIFT 2 // Shift amount for the load action\r
+#define PWM_GEN_ACT_A_UP_SHIFT 4 // Shift amount for the A up action\r
+#define PWM_GEN_ACT_A_DN_SHIFT 6 // Shift amount for the A dn action\r
+#define PWM_GEN_ACT_B_UP_SHIFT 8 // Shift amount for the B up action\r
+#define PWM_GEN_ACT_B_DN_SHIFT 10 // Shift amount for the B dn action\r
+\r
+//*****************************************************************************\r
+//\r
+// PWM_X Dead Band Control Register bit definitions.\r
+//\r
+//*****************************************************************************\r
+#define PWM_DBCTL_ENABLE 0x00000001 // Enable dead band insertion\r
+\r
+//*****************************************************************************\r
+//\r
+// PWM Register reset values.\r
+//\r
+//*****************************************************************************\r
+#define PWM_RV_CTL 0x00000000 // Master control of the PWM module\r
+#define PWM_RV_SYNC 0x00000000 // Counter synch for PWM generators\r
+#define PWM_RV_ENABLE 0x00000000 // Master enable for the PWM\r
+ // output pins\r
+#define PWM_RV_INVERT 0x00000000 // Inversion control for\r
+ // PWM output pins\r
+#define PWM_RV_FAULT 0x00000000 // Fault handling for the PWM\r
+ // output pins\r
+#define PWM_RV_INTEN 0x00000000 // Interrupt enable\r
+#define PWM_RV_RIS 0x00000000 // Raw interrupt status\r
+#define PWM_RV_ISC 0x00000000 // Interrupt status and clearing\r
+#define PWM_RV_STATUS 0x00000000 // Status\r
+#define PWM_RV_X_CTL 0x00000000 // Master control of the PWM\r
+ // generator block\r
+#define PWM_RV_X_INTEN 0x00000000 // Interrupt and trigger enable\r
+#define PWM_RV_X_RIS 0x00000000 // Raw interrupt status\r
+#define PWM_RV_X_ISC 0x00000000 // Interrupt status and clearing\r
+#define PWM_RV_X_LOAD 0x00000000 // The load value for the counter\r
+#define PWM_RV_X_COUNT 0x00000000 // The current counter value\r
+#define PWM_RV_X_CMPA 0x00000000 // The comparator A value\r
+#define PWM_RV_X_CMPB 0x00000000 // The comparator B value\r
+#define PWM_RV_X_GENA 0x00000000 // Controls PWM generator A\r
+#define PWM_RV_X_GENB 0x00000000 // Controls PWM generator B\r
+#define PWM_RV_X_DBCTL 0x00000000 // Control the dead band generator\r
+#define PWM_RV_X_DBRISE 0x00000000 // The dead band rising edge delay\r
+ // count\r
+#define PWM_RV_X_DBFALL 0x00000000 // The dead band falling edge delay\r
+ // count\r
+\r
+#endif // __HW_PWM_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_qei.h - Macros used when accessing the QEI hardware.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_QEI_H__\r
+#define __HW_QEI_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the offsets of the QEI registers.\r
+//\r
+//*****************************************************************************\r
+#define QEI_O_CTL 0x00000000 // Configuration and control reg.\r
+#define QEI_O_STAT 0x00000004 // Status register\r
+#define QEI_O_POS 0x00000008 // Current position register\r
+#define QEI_O_MAXPOS 0x0000000C // Maximum position register\r
+#define QEI_O_LOAD 0x00000010 // Velocity timer load register\r
+#define QEI_O_TIME 0x00000014 // Velocity timer register\r
+#define QEI_O_COUNT 0x00000018 // Velocity pulse count register\r
+#define QEI_O_SPEED 0x0000001C // Velocity speed register\r
+#define QEI_O_INTEN 0x00000020 // Interrupt enable register\r
+#define QEI_O_RIS 0x00000024 // Raw interrupt status register\r
+#define QEI_O_ISC 0x00000028 // Interrupt status register\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the QEI_CTL register.\r
+//\r
+//*****************************************************************************\r
+#define QEI_CTL_STALLEN 0x00001000 // Stall enable\r
+#define QEI_CTL_INVI 0x00000800 // Invert Index input\r
+#define QEI_CTL_INVB 0x00000400 // Invert PhB input\r
+#define QEI_CTL_INVA 0x00000200 // Invert PhA input\r
+#define QEI_CTL_VELDIV_M 0x000001C0 // Velocity predivider mask\r
+#define QEI_CTL_VELDIV_1 0x00000000 // Predivide by 1\r
+#define QEI_CTL_VELDIV_2 0x00000040 // Predivide by 2\r
+#define QEI_CTL_VELDIV_4 0x00000080 // Predivide by 4\r
+#define QEI_CTL_VELDIV_8 0x000000C0 // Predivide by 8\r
+#define QEI_CTL_VELDIV_16 0x00000100 // Predivide by 16\r
+#define QEI_CTL_VELDIV_32 0x00000140 // Predivide by 32\r
+#define QEI_CTL_VELDIV_64 0x00000180 // Predivide by 64\r
+#define QEI_CTL_VELDIV_128 0x000001C0 // Predivide by 128\r
+#define QEI_CTL_VELEN 0x00000020 // Velocity enable\r
+#define QEI_CTL_RESMODE 0x00000010 // Position counter reset mode\r
+#define QEI_CTL_CAPMODE 0x00000008 // Edge capture mode\r
+#define QEI_CTL_SIGMODE 0x00000004 // Encoder signaling mode\r
+#define QEI_CTL_SWAP 0x00000002 // Swap input signals\r
+#define QEI_CTL_ENABLE 0x00000001 // QEI enable\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the QEI_STAT register.\r
+//\r
+//*****************************************************************************\r
+#define QEI_STAT_DIRECTION 0x00000002 // Direction of rotation\r
+#define QEI_STAT_ERROR 0x00000001 // Signalling error detected\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the QEI_POS register.\r
+//\r
+//*****************************************************************************\r
+#define QEI_POS_M 0xFFFFFFFF // Current encoder position\r
+#define QEI_POS_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the QEI_MAXPOS register.\r
+//\r
+//*****************************************************************************\r
+#define QEI_MAXPOS_M 0xFFFFFFFF // Maximum encoder position\r
+#define QEI_MAXPOS_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the QEI_LOAD register.\r
+//\r
+//*****************************************************************************\r
+#define QEI_LOAD_M 0xFFFFFFFF // Velocity timer load value\r
+#define QEI_LOAD_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the QEI_TIME register.\r
+//\r
+//*****************************************************************************\r
+#define QEI_TIME_M 0xFFFFFFFF // Velocity timer current value\r
+#define QEI_TIME_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the QEI_COUNT register.\r
+//\r
+//*****************************************************************************\r
+#define QEI_COUNT_M 0xFFFFFFFF // Encoder running pulse count\r
+#define QEI_COUNT_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the QEI_SPEED register.\r
+//\r
+//*****************************************************************************\r
+#define QEI_SPEED_M 0xFFFFFFFF // Encoder pulse count\r
+#define QEI_SPEED_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the QEI_INTEN register.\r
+//\r
+//*****************************************************************************\r
+#define QEI_INTEN_ERROR 0x00000008 // Phase error detected\r
+#define QEI_INTEN_DIR 0x00000004 // Direction change\r
+#define QEI_INTEN_TIMER 0x00000002 // Velocity timer expired\r
+#define QEI_INTEN_INDEX 0x00000001 // Index pulse detected\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the QEI_RIS register.\r
+//\r
+//*****************************************************************************\r
+#define QEI_RIS_ERROR 0x00000008 // Phase error detected\r
+#define QEI_RIS_DIR 0x00000004 // Direction change\r
+#define QEI_RIS_TIMER 0x00000002 // Velocity timer expired\r
+#define QEI_RIS_INDEX 0x00000001 // Index pulse detected\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the QEI_ISC register.\r
+//\r
+//*****************************************************************************\r
+#define QEI_INT_ERROR 0x00000008 // Phase error detected\r
+#define QEI_INT_DIR 0x00000004 // Direction change\r
+#define QEI_INT_TIMER 0x00000002 // Velocity timer expired\r
+#define QEI_INT_INDEX 0x00000001 // Index pulse detected\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the reset values for the QEI registers.\r
+//\r
+//*****************************************************************************\r
+#define QEI_RV_CTL 0x00000000 // Configuration and control reg.\r
+#define QEI_RV_STAT 0x00000000 // Status register\r
+#define QEI_RV_POS 0x00000000 // Current position register\r
+#define QEI_RV_MAXPOS 0x00000000 // Maximum position register\r
+#define QEI_RV_LOAD 0x00000000 // Velocity timer load register\r
+#define QEI_RV_TIME 0x00000000 // Velocity timer register\r
+#define QEI_RV_COUNT 0x00000000 // Velocity pulse count register\r
+#define QEI_RV_SPEED 0x00000000 // Velocity speed register\r
+#define QEI_RV_INTEN 0x00000000 // Interrupt enable register\r
+#define QEI_RV_RIS 0x00000000 // Raw interrupt status register\r
+#define QEI_RV_ISC 0x00000000 // Interrupt status register\r
+\r
+#endif // __HW_QEI_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_ssi.h - Macros used when accessing the SSI hardware.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_SSI_H__\r
+#define __HW_SSI_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the offsets of the SSI registers.\r
+//\r
+//*****************************************************************************\r
+#define SSI_O_CR0 0x00000000 // Control register 0\r
+#define SSI_O_CR1 0x00000004 // Control register 1\r
+#define SSI_O_DR 0x00000008 // Data register\r
+#define SSI_O_SR 0x0000000C // Status register\r
+#define SSI_O_CPSR 0x00000010 // Clock prescale register\r
+#define SSI_O_IM 0x00000014 // Int mask set and clear register\r
+#define SSI_O_RIS 0x00000018 // Raw interrupt register\r
+#define SSI_O_MIS 0x0000001C // Masked interrupt register\r
+#define SSI_O_ICR 0x00000020 // Interrupt clear register\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SSI Control register 0.\r
+//\r
+//*****************************************************************************\r
+#define SSI_CR0_SCR 0x0000FF00 // Serial clock rate\r
+#define SSI_CR0_SPH 0x00000080 // SSPCLKOUT phase\r
+#define SSI_CR0_SPO 0x00000040 // SSPCLKOUT polarity\r
+#define SSI_CR0_FRF_MASK 0x00000030 // Frame format mask\r
+#define SSI_CR0_FRF_MOTO 0x00000000 // Motorola SPI frame format\r
+#define SSI_CR0_FRF_TI 0x00000010 // TI sync serial frame format\r
+#define SSI_CR0_FRF_NMW 0x00000020 // National Microwire frame format\r
+#define SSI_CR0_DSS 0x0000000F // Data size select\r
+#define SSI_CR0_DSS_4 0x00000003 // 4 bit data\r
+#define SSI_CR0_DSS_5 0x00000004 // 5 bit data\r
+#define SSI_CR0_DSS_6 0x00000005 // 6 bit data\r
+#define SSI_CR0_DSS_7 0x00000006 // 7 bit data\r
+#define SSI_CR0_DSS_8 0x00000007 // 8 bit data\r
+#define SSI_CR0_DSS_9 0x00000008 // 9 bit data\r
+#define SSI_CR0_DSS_10 0x00000009 // 10 bit data\r
+#define SSI_CR0_DSS_11 0x0000000A // 11 bit data\r
+#define SSI_CR0_DSS_12 0x0000000B // 12 bit data\r
+#define SSI_CR0_DSS_13 0x0000000C // 13 bit data\r
+#define SSI_CR0_DSS_14 0x0000000D // 14 bit data\r
+#define SSI_CR0_DSS_15 0x0000000E // 15 bit data\r
+#define SSI_CR0_DSS_16 0x0000000F // 16 bit data\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SSI Control register 1.\r
+//\r
+//*****************************************************************************\r
+#define SSI_CR1_SOD 0x00000008 // Slave mode output disable\r
+#define SSI_CR1_MS 0x00000004 // Master or slave mode select\r
+#define SSI_CR1_SSE 0x00000002 // Sync serial port enable\r
+#define SSI_CR1_LBM 0x00000001 // Loopback mode\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SSI Status register.\r
+//\r
+//*****************************************************************************\r
+#define SSI_SR_BSY 0x00000010 // SSI busy\r
+#define SSI_SR_RFF 0x00000008 // RX FIFO full\r
+#define SSI_SR_RNE 0x00000004 // RX FIFO not empty\r
+#define SSI_SR_TNF 0x00000002 // TX FIFO not full\r
+#define SSI_SR_TFE 0x00000001 // TX FIFO empty\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SSI clock prescale register.\r
+//\r
+//*****************************************************************************\r
+#define SSI_CPSR_CPSDVSR_MASK 0x000000FF // Clock prescale\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define information concerning the SSI Data register.\r
+//\r
+//*****************************************************************************\r
+#define TX_FIFO_SIZE (8) // Number of entries in the TX FIFO\r
+#define RX_FIFO_SIZE (8) // Number of entries in the RX FIFO\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the interrupt mask set and clear,\r
+// raw interrupt, masked interrupt, and interrupt clear registers.\r
+//\r
+//*****************************************************************************\r
+#define SSI_INT_TXFF 0x00000008 // TX FIFO interrupt\r
+#define SSI_INT_RXFF 0x00000004 // RX FIFO interrupt\r
+#define SSI_INT_RXTO 0x00000002 // RX timeout interrupt\r
+#define SSI_INT_RXOR 0x00000001 // RX overrun interrupt\r
+\r
+#endif // __HW_SSI_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_sysctl.h - Macros used when accessing the system control hardware.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_SYSCTL_H__\r
+#define __HW_SYSCTL_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the addresses of the system control registers.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_DID0 0x400fe000 // Device identification register 0\r
+#define SYSCTL_DID1 0x400fe004 // Device identification register 1\r
+#define SYSCTL_DC0 0x400fe008 // Device capabilities register 0\r
+#define SYSCTL_DC1 0x400fe010 // Device capabilities register 1\r
+#define SYSCTL_DC2 0x400fe014 // Device capabilities register 2\r
+#define SYSCTL_DC3 0x400fe018 // Device capabilities register 3\r
+#define SYSCTL_DC4 0x400fe01C // Device capabilities register 4\r
+#define SYSCTL_PBORCTL 0x400fe030 // POR/BOR reset control register\r
+#define SYSCTL_LDOPCTL 0x400fe034 // LDO power control register\r
+#define SYSCTL_SRCR0 0x400fe040 // Software reset control reg 0\r
+#define SYSCTL_SRCR1 0x400fe044 // Software reset control reg 1\r
+#define SYSCTL_SRCR2 0x400fe048 // Software reset control reg 2\r
+#define SYSCTL_RIS 0x400fe050 // Raw interrupt status register\r
+#define SYSCTL_IMC 0x400fe054 // Interrupt mask/control register\r
+#define SYSCTL_MISC 0x400fe058 // Interrupt status register\r
+#define SYSCTL_RESC 0x400fe05c // Reset cause register\r
+#define SYSCTL_RCC 0x400fe060 // Run-mode clock config register\r
+#define SYSCTL_PLLCFG 0x400fe064 // PLL configuration register\r
+#define SYSCTL_RCC2 0x400fe070 // Run-mode clock config register 2\r
+#define SYSCTL_RCGC0 0x400fe100 // Run-mode clock gating register 0\r
+#define SYSCTL_RCGC1 0x400fe104 // Run-mode clock gating register 1\r
+#define SYSCTL_RCGC2 0x400fe108 // Run-mode clock gating register 2\r
+#define SYSCTL_SCGC0 0x400fe110 // Sleep-mode clock gating reg 0\r
+#define SYSCTL_SCGC1 0x400fe114 // Sleep-mode clock gating reg 1\r
+#define SYSCTL_SCGC2 0x400fe118 // Sleep-mode clock gating reg 2\r
+#define SYSCTL_DCGC0 0x400fe120 // Deep Sleep-mode clock gate reg 0\r
+#define SYSCTL_DCGC1 0x400fe124 // Deep Sleep-mode clock gate reg 1\r
+#define SYSCTL_DCGC2 0x400fe128 // Deep Sleep-mode clock gate reg 2\r
+#define SYSCTL_DSLPCLKCFG 0x400fe144 // Deep Sleep-mode clock config reg\r
+#define SYSCTL_CLKVCLR 0x400fe150 // Clock verifcation clear register\r
+#define SYSCTL_LDOARST 0x400fe160 // LDO reset control register\r
+#define SYSCTL_USER0 0x400fe1e0 // NV User Register 0\r
+#define SYSCTL_USER1 0x400fe1e4 // NV User Register 1\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_DID0 register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_DID0_VER_MASK 0x70000000 // DID0 version mask\r
+#define SYSCTL_DID0_VER_0 0x00000000 // DID0 version 0\r
+#define SYSCTL_DID0_VER_1 0x10000000 // DID0 version 1\r
+#define SYSCTL_DID0_CLASS_MASK 0x00FF0000 // Device Class\r
+#define SYSCTL_DID0_CLASS_SANDSTORM 0x00000000 // LM3Snnn Sandstorm Device\r
+#define SYSCTL_DID0_CLASS_FURY 0x00010000 // LM3Snnnn Fury Device\r
+#define SYSCTL_DID0_MAJ_MASK 0x0000FF00 // Major revision mask\r
+#define SYSCTL_DID0_MAJ_A 0x00000000 // Major revision A\r
+#define SYSCTL_DID0_MAJ_B 0x00000100 // Major revision B\r
+#define SYSCTL_DID0_MAJ_C 0x00000200 // Major revision C\r
+#define SYSCTL_DID0_MIN_MASK 0x000000FF // Minor revision mask\r
+#define SYSCTL_DID0_MIN_0 0x00000000 // Minor revision 0\r
+#define SYSCTL_DID0_MIN_1 0x00000001 // Minor revision 1\r
+#define SYSCTL_DID0_MIN_2 0x00000002 // Minor revision 2\r
+#define SYSCTL_DID0_MIN_3 0x00000003 // Minor revision 3\r
+#define SYSCTL_DID0_MIN_4 0x00000004 // Minor revision 4\r
+#define SYSCTL_DID0_MIN_5 0x00000005 // Minor revision 5\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_DID1 register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_DID1_VER_MASK 0xF0000000 // Register version mask\r
+#define SYSCTL_DID1_FAM_MASK 0x0F000000 // Family mask\r
+#define SYSCTL_DID1_FAM_S 0x00000000 // Stellaris family\r
+#define SYSCTL_DID1_PRTNO_MASK 0x00FF0000 // Part number mask\r
+#define SYSCTL_DID1_PRTNO_101 0x00010000 // LM3S101\r
+#define SYSCTL_DID1_PRTNO_102 0x00020000 // LM3S102\r
+#define SYSCTL_DID1_PRTNO_301 0x00110000 // LM3S301\r
+#define SYSCTL_DID1_PRTNO_310 0x00120000 // LM3S310\r
+#define SYSCTL_DID1_PRTNO_315 0x00130000 // LM3S315\r
+#define SYSCTL_DID1_PRTNO_316 0x00140000 // LM3S316\r
+#define SYSCTL_DID1_PRTNO_317 0x00170000 // LM3S317\r
+#define SYSCTL_DID1_PRTNO_328 0x00150000 // LM3S328\r
+#define SYSCTL_DID1_PRTNO_601 0x00210000 // LM3S601\r
+#define SYSCTL_DID1_PRTNO_610 0x00220000 // LM3S610\r
+#define SYSCTL_DID1_PRTNO_611 0x00230000 // LM3S611\r
+#define SYSCTL_DID1_PRTNO_612 0x00240000 // LM3S612\r
+#define SYSCTL_DID1_PRTNO_613 0x00250000 // LM3S613\r
+#define SYSCTL_DID1_PRTNO_615 0x00260000 // LM3S615\r
+#define SYSCTL_DID1_PRTNO_617 0x00280000 // LM3S617\r
+#define SYSCTL_DID1_PRTNO_618 0x00290000 // LM3S618\r
+#define SYSCTL_DID1_PRTNO_628 0x00270000 // LM3S628\r
+#define SYSCTL_DID1_PRTNO_801 0x00310000 // LM3S801\r
+#define SYSCTL_DID1_PRTNO_811 0x00320000 // LM3S811\r
+#define SYSCTL_DID1_PRTNO_812 0x00330000 // LM3S812\r
+#define SYSCTL_DID1_PRTNO_815 0x00340000 // LM3S815\r
+#define SYSCTL_DID1_PRTNO_817 0x00360000 // LM3S817\r
+#define SYSCTL_DID1_PRTNO_818 0x00370000 // LM3S818\r
+#define SYSCTL_DID1_PRTNO_828 0x00350000 // LM3S828\r
+#define SYSCTL_DID1_PRTNO_2110 0x00510000 // LM3S2110\r
+#define SYSCTL_DID1_PRTNO_2139 0x00840000 // LM3S2139\r
+#define SYSCTL_DID1_PRTNO_2410 0x00A20000 // LM3S2410\r
+#define SYSCTL_DID1_PRTNO_2412 0x00590000 // LM3S2412\r
+#define SYSCTL_DID1_PRTNO_2432 0x00560000 // LM3S2432\r
+#define SYSCTL_DID1_PRTNO_2533 0x005A0000 // LM3S2533\r
+#define SYSCTL_DID1_PRTNO_2620 0x00570000 // LM3S2620\r
+#define SYSCTL_DID1_PRTNO_2637 0x00850000 // LM3S2637\r
+#define SYSCTL_DID1_PRTNO_2651 0x00530000 // LM3S2651\r
+#define SYSCTL_DID1_PRTNO_2730 0x00A40000 // LM3S2730\r
+#define SYSCTL_DID1_PRTNO_2739 0x00520000 // LM3S2739\r
+#define SYSCTL_DID1_PRTNO_2939 0x00540000 // LM3S2939\r
+#define SYSCTL_DID1_PRTNO_2948 0x008F0000 // LM3S2948\r
+#define SYSCTL_DID1_PRTNO_2950 0x00580000 // LM3S2950\r
+#define SYSCTL_DID1_PRTNO_2965 0x00550000 // LM3S2965\r
+#define SYSCTL_DID1_PRTNO_6100 0x00A10000 // LM3S6100\r
+#define SYSCTL_DID1_PRTNO_6110 0x00740000 // LM3S6110\r
+#define SYSCTL_DID1_PRTNO_6420 0x00A50000 // LM3S6420\r
+#define SYSCTL_DID1_PRTNO_6422 0x00820000 // LM3S6422\r
+#define SYSCTL_DID1_PRTNO_6432 0x00750000 // LM3S6432\r
+#define SYSCTL_DID1_PRTNO_6610 0x00710000 // LM3S6610\r
+#define SYSCTL_DID1_PRTNO_6633 0x00830000 // LM3S6633\r
+#define SYSCTL_DID1_PRTNO_6637 0x008B0000 // LM3S6637\r
+#define SYSCTL_DID1_PRTNO_6730 0x00A30000 // LM3S6730\r
+#define SYSCTL_DID1_PRTNO_6938 0x00890000 // LM3S6938\r
+#define SYSCTL_DID1_PRTNO_6952 0x00780000 // LM3S6952\r
+#define SYSCTL_DID1_PRTNO_6965 0x00730000 // LM3S6965\r
+#define SYSCTL_DID1_PINCNT_MASK 0x0000E000 // Pin count\r
+#define SYSCTL_DID1_PINCNT_100 0x00004000 // 100 pin package\r
+#define SYSCTL_DID1_TEMP_MASK 0x000000E0 // Temperature range mask\r
+#define SYSCTL_DID1_TEMP_C 0x00000000 // Commercial temp range (0..70C)\r
+#define SYSCTL_DID1_TEMP_I 0x00000020 // Industrial temp range (-40..85C)\r
+#define SYSCTL_DID1_PKG_MASK 0x00000018 // Package mask\r
+#define SYSCTL_DID1_PKG_28SOIC 0x00000000 // 28-pin SOIC\r
+#define SYSCTL_DID1_PKG_48QFP 0x00000008 // 48-pin QFP\r
+#define SYSCTL_DID1_ROHS 0x00000004 // Part is RoHS compliant\r
+#define SYSCTL_DID1_QUAL_MASK 0x00000003 // Qualification status mask\r
+#define SYSCTL_DID1_QUAL_ES 0x00000000 // Engineering sample (unqualified)\r
+#define SYSCTL_DID1_QUAL_PP 0x00000001 // Pilot production (unqualified)\r
+#define SYSCTL_DID1_QUAL_FQ 0x00000002 // Fully qualified\r
+#define SYSCTL_DID1_PRTNO_SHIFT 16\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_DC0 register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_DC0_SRAMSZ_MASK 0xFFFF0000 // SRAM size mask\r
+#define SYSCTL_DC0_SRAMSZ_2KB 0x00070000 // 2 KB of SRAM\r
+#define SYSCTL_DC0_SRAMSZ_4KB 0x000F0000 // 4 KB of SRAM\r
+#define SYSCTL_DC0_SRAMSZ_8KB 0x001F0000 // 8 KB of SRAM\r
+#define SYSCTL_DC0_SRAMSZ_16KB 0x003F0000 // 16 KB of SRAM\r
+#define SYSCTL_DC0_SRAMSZ_32KB 0x007F0000 // 32 KB of SRAM\r
+#define SYSCTL_DC0_SRAMSZ_64KB 0x00FF0000 // 64 KB of SRAM\r
+#define SYSCTL_DC0_FLASHSZ_MASK 0x0000FFFF // Flash size mask\r
+#define SYSCTL_DC0_FLASHSZ_8KB 0x00000003 // 8 KB of flash\r
+#define SYSCTL_DC0_FLASHSZ_16KB 0x00000007 // 16 KB of flash\r
+#define SYSCTL_DC0_FLASHSZ_32KB 0x0000000F // 32 KB of flash\r
+#define SYSCTL_DC0_FLASHSZ_64KB 0x0000001F // 64 KB of flash\r
+#define SYSCTL_DC0_FLASHSZ_96KB 0x0000002F // 96 KB of flash\r
+#define SYSCTL_DC0_FLASHSZ_128K 0x0000003F // 128 KB of flash\r
+#define SYSCTL_DC0_FLASHSZ_256K 0x0000007F // 256 KB of flash\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_DC1 register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_DC1_CAN1 0x02000000 // CAN1 module present\r
+#define SYSCTL_DC1_CAN0 0x01000000 // CAN0 module present\r
+#define SYSCTL_DC1_PWM 0x00100000 // PWM module present\r
+#define SYSCTL_DC1_ADC 0x00010000 // ADC module present\r
+#define SYSCTL_DC1_SYSDIV_MASK 0x0000F000 // Minimum system divider mask\r
+#define SYSCTL_DC1_ADCSPD_MASK 0x00000F00 // ADC speed mask\r
+#define SYSCTL_DC1_ADCSPD_1M 0x00000300 // 1Msps ADC\r
+#define SYSCTL_DC1_ADCSPD_500K 0x00000200 // 500Ksps ADC\r
+#define SYSCTL_DC1_ADCSPD_250K 0x00000100 // 250Ksps ADC\r
+#define SYSCTL_DC1_ADCSPD_125K 0x00000000 // 125Ksps ADC\r
+#define SYSCTL_DC1_MPU 0x00000080 // Cortex M3 MPU present\r
+#define SYSCTL_DC1_HIB 0x00000040 // Hibernation module present\r
+#define SYSCTL_DC1_TEMP 0x00000020 // Temperature sensor present\r
+#define SYSCTL_DC1_PLL 0x00000010 // PLL present\r
+#define SYSCTL_DC1_WDOG 0x00000008 // Watchdog present\r
+#define SYSCTL_DC1_SWO 0x00000004 // Serial wire output present\r
+#define SYSCTL_DC1_SWD 0x00000002 // Serial wire debug present\r
+#define SYSCTL_DC1_JTAG 0x00000001 // JTAG debug present\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_DC2 register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_DC2_COMP2 0x04000000 // Analog comparator 2 present\r
+#define SYSCTL_DC2_COMP1 0x02000000 // Analog comparator 1 present\r
+#define SYSCTL_DC2_COMP0 0x01000000 // Analog comparator 0 present\r
+#define SYSCTL_DC2_TIMER3 0x00080000 // Timer 3 present\r
+#define SYSCTL_DC2_TIMER2 0x00040000 // Timer 2 present\r
+#define SYSCTL_DC2_TIMER1 0x00020000 // Timer 1 present\r
+#define SYSCTL_DC2_TIMER0 0x00010000 // Timer 0 present\r
+#define SYSCTL_DC2_I2C1 0x00002000 // I2C 1 present\r
+#define SYSCTL_DC2_I2C0 0x00001000 // I2C 0 present\r
+#ifndef DEPRECATED\r
+#define SYSCTL_DC2_I2C 0x00001000 // I2C present\r
+#endif\r
+#define SYSCTL_DC2_QEI1 0x00000200 // QEI 1 present\r
+#define SYSCTL_DC2_QEI0 0x00000100 // QEI 0 present\r
+#ifndef DEPRECATED\r
+#define SYSCTL_DC2_QEI 0x00000100 // QEI present\r
+#endif\r
+#define SYSCTL_DC2_SSI1 0x00000020 // SSI 1 present\r
+#define SYSCTL_DC2_SSI0 0x00000010 // SSI 0 present\r
+#ifndef DEPRECATED\r
+#define SYSCTL_DC2_SSI 0x00000010 // SSI present\r
+#endif\r
+#define SYSCTL_DC2_UART2 0x00000004 // UART 2 present\r
+#define SYSCTL_DC2_UART1 0x00000002 // UART 1 present\r
+#define SYSCTL_DC2_UART0 0x00000001 // UART 0 present\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_DC3 register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_DC3_32KHZ 0x80000000 // 32kHz pin present\r
+#define SYSCTL_DC3_CCP5 0x20000000 // CCP5 pin present\r
+#define SYSCTL_DC3_CCP4 0x10000000 // CCP4 pin present\r
+#define SYSCTL_DC3_CCP3 0x08000000 // CCP3 pin present\r
+#define SYSCTL_DC3_CCP2 0x04000000 // CCP2 pin present\r
+#define SYSCTL_DC3_CCP1 0x02000000 // CCP1 pin present\r
+#define SYSCTL_DC3_CCP0 0x01000000 // CCP0 pin present\r
+#define SYSCTL_DC3_ADC7 0x00800000 // ADC7 pin present\r
+#define SYSCTL_DC3_ADC6 0x00400000 // ADC6 pin present\r
+#define SYSCTL_DC3_ADC5 0x00200000 // ADC5 pin present\r
+#define SYSCTL_DC3_ADC4 0x00100000 // ADC4 pin present\r
+#define SYSCTL_DC3_ADC3 0x00080000 // ADC3 pin present\r
+#define SYSCTL_DC3_ADC2 0x00040000 // ADC2 pin present\r
+#define SYSCTL_DC3_ADC1 0x00020000 // ADC1 pin present\r
+#define SYSCTL_DC3_ADC0 0x00010000 // ADC0 pin present\r
+#define SYSCTL_DC3_MC_FAULT0 0x00008000 // MC0 fault pin present\r
+#define SYSCTL_DC3_C2O 0x00004000 // C2o pin present\r
+#define SYSCTL_DC3_C2PLUS 0x00002000 // C2+ pin present\r
+#define SYSCTL_DC3_C2MINUS 0x00001000 // C2- pin present\r
+#define SYSCTL_DC3_C1O 0x00000800 // C1o pin present\r
+#define SYSCTL_DC3_C1PLUS 0x00000400 // C1+ pin present\r
+#define SYSCTL_DC3_C1MINUS 0x00000200 // C1- pin present\r
+#define SYSCTL_DC3_C0O 0x00000100 // C0o pin present\r
+#define SYSCTL_DC3_C0PLUS 0x00000080 // C0+ pin present\r
+#define SYSCTL_DC3_C0MINUS 0x00000040 // C0- pin present\r
+#define SYSCTL_DC3_PWM5 0x00000020 // PWM5 pin present\r
+#define SYSCTL_DC3_PWM4 0x00000010 // PWM4 pin present\r
+#define SYSCTL_DC3_PWM3 0x00000008 // PWM3 pin present\r
+#define SYSCTL_DC3_PWM2 0x00000004 // PWM2 pin present\r
+#define SYSCTL_DC3_PWM1 0x00000002 // PWM1 pin present\r
+#define SYSCTL_DC3_PWM0 0x00000001 // PWM0 pin present\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_DC4 register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_DC4_ETH 0x50000000 // Ethernet present\r
+#define SYSCTL_DC4_GPIOH 0x00000080 // GPIO port H present\r
+#define SYSCTL_DC4_GPIOG 0x00000040 // GPIO port G present\r
+#define SYSCTL_DC4_GPIOF 0x00000020 // GPIO port F present\r
+#define SYSCTL_DC4_GPIOE 0x00000010 // GPIO port E present\r
+#define SYSCTL_DC4_GPIOD 0x00000008 // GPIO port D present\r
+#define SYSCTL_DC4_GPIOC 0x00000004 // GPIO port C present\r
+#define SYSCTL_DC4_GPIOB 0x00000002 // GPIO port B present\r
+#define SYSCTL_DC4_GPIOA 0x00000001 // GPIO port A present\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_PBORCTL register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_PBORCTL_BOR_MASK 0x0000FFFC // BOR wait timer\r
+#define SYSCTL_PBORCTL_BORIOR 0x00000002 // BOR interrupt or reset\r
+#define SYSCTL_PBORCTL_BORWT 0x00000001 // BOR wait and check for noise\r
+#define SYSCTL_PBORCTL_BOR_SH 2\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_LDOPCTL register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_LDOPCTL_MASK 0x0000003F // Voltage adjust mask\r
+#define SYSCTL_LDOPCTL_2_25V 0x00000005 // LDO output of 2.25V\r
+#define SYSCTL_LDOPCTL_2_30V 0x00000004 // LDO output of 2.30V\r
+#define SYSCTL_LDOPCTL_2_35V 0x00000003 // LDO output of 2.35V\r
+#define SYSCTL_LDOPCTL_2_40V 0x00000002 // LDO output of 2.40V\r
+#define SYSCTL_LDOPCTL_2_45V 0x00000001 // LDO output of 2.45V\r
+#define SYSCTL_LDOPCTL_2_50V 0x00000000 // LDO output of 2.50V\r
+#define SYSCTL_LDOPCTL_2_55V 0x0000001F // LDO output of 2.55V\r
+#define SYSCTL_LDOPCTL_2_60V 0x0000001E // LDO output of 2.60V\r
+#define SYSCTL_LDOPCTL_2_65V 0x0000001D // LDO output of 2.65V\r
+#define SYSCTL_LDOPCTL_2_70V 0x0000001C // LDO output of 2.70V\r
+#define SYSCTL_LDOPCTL_2_75V 0x0000001B // LDO output of 2.75V\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_SRCR0, SYSCTL_RCGC0,\r
+// SYSCTL_SCGC0, and SYSCTL_DCGC0 registers.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_SET0_CAN1 0x02000000 // CAN 1 module\r
+#define SYSCTL_SET0_CAN0 0x01000000 // CAN 0 module\r
+#define SYSCTL_SET0_PWM 0x00100000 // PWM module\r
+#define SYSCTL_SET0_ADC 0x00010000 // ADC module\r
+#define SYSCTL_SET0_ADCSPD_MASK 0x00000F00 // ADC speed mask\r
+#define SYSCTL_SET0_ADCSPD_1M 0x00000300 // 1Msps ADC\r
+#define SYSCTL_SET0_ADCSPD_500K 0x00000200 // 500Ksps ADC\r
+#define SYSCTL_SET0_ADCSPD_250K 0x00000100 // 250Ksps ADC\r
+#define SYSCTL_SET0_ADCSPD_125K 0x00000000 // 125Ksps ADC\r
+#define SYSCTL_SET0_HIB 0x00000040 // Hibernation module\r
+#define SYSCTL_SET0_WDOG 0x00000008 // Watchdog module\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_SRCR1, SYSCTL_RCGC1,\r
+// SYSCTL_SCGC1, and SYSCTL_DCGC1 registers.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_SET1_COMP2 0x04000000 // Analog comparator module 2\r
+#define SYSCTL_SET1_COMP1 0x02000000 // Analog comparator module 1\r
+#define SYSCTL_SET1_COMP0 0x01000000 // Analog comparator module 0\r
+#define SYSCTL_SET1_TIMER3 0x00080000 // Timer module 3\r
+#define SYSCTL_SET1_TIMER2 0x00040000 // Timer module 2\r
+#define SYSCTL_SET1_TIMER1 0x00020000 // Timer module 1\r
+#define SYSCTL_SET1_TIMER0 0x00010000 // Timer module 0\r
+#define SYSCTL_SET1_I2C1 0x00002000 // I2C module 1\r
+#define SYSCTL_SET1_I2C0 0x00001000 // I2C module 0\r
+#ifndef DEPRECATED\r
+#define SYSCTL_SET1_I2C 0x00001000 // I2C module\r
+#endif\r
+#define SYSCTL_SET1_QEI1 0x00000200 // QEI module 1\r
+#define SYSCTL_SET1_QEI0 0x00000100 // QEI module 0\r
+#ifndef DEPRECATED\r
+#define SYSCTL_SET1_QEI 0x00000100 // QEI module\r
+#endif\r
+#define SYSCTL_SET1_SSI1 0x00000020 // SSI module 1\r
+#define SYSCTL_SET1_SSI0 0x00000010 // SSI module 0\r
+#ifndef DEPRECATED\r
+#define SYSCTL_SET1_SSI 0x00000010 // SSI module\r
+#endif\r
+#define SYSCTL_SET1_UART2 0x00000004 // UART module 2\r
+#define SYSCTL_SET1_UART1 0x00000002 // UART module 1\r
+#define SYSCTL_SET1_UART0 0x00000001 // UART module 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_SRCR2, SYSCTL_RCGC2,\r
+// SYSCTL_SCGC2, and SYSCTL_DCGC2 registers.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_SET2_ETH 0x50000000 // ETH module\r
+#define SYSCTL_SET2_GPIOH 0x00000080 // GPIO H module\r
+#define SYSCTL_SET2_GPIOG 0x00000040 // GPIO G module\r
+#define SYSCTL_SET2_GPIOF 0x00000020 // GPIO F module\r
+#define SYSCTL_SET2_GPIOE 0x00000010 // GPIO E module\r
+#define SYSCTL_SET2_GPIOD 0x00000008 // GPIO D module\r
+#define SYSCTL_SET2_GPIOC 0x00000004 // GPIO C module\r
+#define SYSCTL_SET2_GPIOB 0x00000002 // GPIO B module\r
+#define SYSCTL_SET2_GPIOA 0x00000001 // GIPO A module\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_RIS, SYSCTL_IMC, and\r
+// SYSCTL_IMS registers.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_INT_PLL_LOCK 0x00000040 // PLL lock interrupt\r
+#define SYSCTL_INT_CUR_LIMIT 0x00000020 // Current limit interrupt\r
+#define SYSCTL_INT_IOSC_FAIL 0x00000010 // Internal oscillator failure int\r
+#define SYSCTL_INT_MOSC_FAIL 0x00000008 // Main oscillator failure int\r
+#define SYSCTL_INT_POR 0x00000004 // Power on reset interrupt\r
+#define SYSCTL_INT_BOR 0x00000002 // Brown out interrupt\r
+#define SYSCTL_INT_PLL_FAIL 0x00000001 // PLL failure interrupt\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_RESC register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_RESC_LDO 0x00000020 // LDO power OK lost reset\r
+#define SYSCTL_RESC_SW 0x00000010 // Software reset\r
+#define SYSCTL_RESC_WDOG 0x00000008 // Watchdog reset\r
+#define SYSCTL_RESC_BOR 0x00000004 // Brown-out reset\r
+#define SYSCTL_RESC_POR 0x00000002 // Power on reset\r
+#define SYSCTL_RESC_EXT 0x00000001 // External reset\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_RCC register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_RCC_ACG 0x08000000 // Automatic clock gating\r
+#define SYSCTL_RCC_SYSDIV_MASK 0x07800000 // System clock divider\r
+#define SYSCTL_RCC_SYSDIV_2 0x00800000 // System clock /2\r
+#define SYSCTL_RCC_SYSDIV_3 0x01000000 // System clock /3\r
+#define SYSCTL_RCC_SYSDIV_4 0x01800000 // System clock /4\r
+#define SYSCTL_RCC_SYSDIV_5 0x02000000 // System clock /5\r
+#define SYSCTL_RCC_SYSDIV_6 0x02800000 // System clock /6\r
+#define SYSCTL_RCC_SYSDIV_7 0x03000000 // System clock /7\r
+#define SYSCTL_RCC_SYSDIV_8 0x03800000 // System clock /8\r
+#define SYSCTL_RCC_SYSDIV_9 0x04000000 // System clock /9\r
+#define SYSCTL_RCC_SYSDIV_10 0x04800000 // System clock /10\r
+#define SYSCTL_RCC_SYSDIV_11 0x05000000 // System clock /11\r
+#define SYSCTL_RCC_SYSDIV_12 0x05800000 // System clock /12\r
+#define SYSCTL_RCC_SYSDIV_13 0x06000000 // System clock /13\r
+#define SYSCTL_RCC_SYSDIV_14 0x06800000 // System clock /14\r
+#define SYSCTL_RCC_SYSDIV_15 0x07000000 // System clock /15\r
+#define SYSCTL_RCC_SYSDIV_16 0x07800000 // System clock /16\r
+#define SYSCTL_RCC_USE_SYSDIV 0x00400000 // Use sytem clock divider\r
+#define SYSCTL_RCC_USE_PWMDIV 0x00100000 // Use PWM clock divider\r
+#define SYSCTL_RCC_PWMDIV_MASK 0x000E0000 // PWM clock divider\r
+#define SYSCTL_RCC_PWMDIV_2 0x00000000 // PWM clock /2\r
+#define SYSCTL_RCC_PWMDIV_4 0x00020000 // PWM clock /4\r
+#define SYSCTL_RCC_PWMDIV_8 0x00040000 // PWM clock /8\r
+#define SYSCTL_RCC_PWMDIV_16 0x00060000 // PWM clock /16\r
+#define SYSCTL_RCC_PWMDIV_32 0x00080000 // PWM clock /32\r
+#define SYSCTL_RCC_PWMDIV_64 0x000A0000 // PWM clock /64\r
+#define SYSCTL_RCC_PWRDN 0x00002000 // PLL power down\r
+#define SYSCTL_RCC_OE 0x00001000 // PLL output enable\r
+#define SYSCTL_RCC_BYPASS 0x00000800 // PLL bypass\r
+#define SYSCTL_RCC_PLLVER 0x00000400 // PLL verification timer enable\r
+#define SYSCTL_RCC_XTAL_MASK 0x000003C0 // Crystal attached to main osc\r
+#define SYSCTL_RCC_XTAL_3_57MHZ 0x00000100 // Using a 3.579545MHz crystal\r
+#define SYSCTL_RCC_XTAL_3_68MHz 0x00000140 // Using a 3.6864MHz crystal\r
+#define SYSCTL_RCC_XTAL_4MHz 0x00000180 // Using a 4MHz crystal\r
+#define SYSCTL_RCC_XTAL_4_09MHZ 0x000001C0 // Using a 4.096MHz crystal\r
+#define SYSCTL_RCC_XTAL_4_91MHZ 0x00000200 // Using a 4.9152MHz crystal\r
+#define SYSCTL_RCC_XTAL_5MHZ 0x00000240 // Using a 5MHz crystal\r
+#define SYSCTL_RCC_XTAL_5_12MHZ 0x00000280 // Using a 5.12MHz crystal\r
+#define SYSCTL_RCC_XTAL_6MHZ 0x000002C0 // Using a 6MHz crystal\r
+#define SYSCTL_RCC_XTAL_6_14MHZ 0x00000300 // Using a 6.144MHz crystal\r
+#define SYSCTL_RCC_XTAL_7_37MHZ 0x00000340 // Using a 7.3728MHz crystal\r
+#define SYSCTL_RCC_XTAL_8MHZ 0x00000380 // Using a 8MHz crystal\r
+#define SYSCTL_RCC_XTAL_8_19MHZ 0x000003C0 // Using a 8.192MHz crystal\r
+#define SYSCTL_RCC_OSCSRC_MASK 0x00000030 // Oscillator input select\r
+#define SYSCTL_RCC_OSCSRC_MAIN 0x00000000 // Use the main oscillator\r
+#define SYSCTL_RCC_OSCSRC_INT 0x00000010 // Use the internal oscillator\r
+#define SYSCTL_RCC_OSCSRC_INT4 0x00000020 // Use the internal oscillator / 4\r
+#define SYSCTL_RCC_IOSCVER 0x00000008 // Int. osc. verification timer en\r
+#define SYSCTL_RCC_MOSCVER 0x00000004 // Main osc. verification timer en\r
+#define SYSCTL_RCC_IOSCDIS 0x00000002 // Internal oscillator disable\r
+#define SYSCTL_RCC_MOSCDIS 0x00000001 // Main oscillator disable\r
+#define SYSCTL_RCC_SYSDIV_SHIFT 23 // Shift to the SYSDIV field\r
+#define SYSCTL_RCC_PWMDIV_SHIFT 17 // Shift to the PWMDIV field\r
+#define SYSCTL_RCC_XTAL_SHIFT 6 // Shift to the XTAL field\r
+#define SYSCTL_RCC_OSCSRC_SHIFT 4 // Shift to the OSCSRC field\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_PLLCFG register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_PLLCFG_OD_MASK 0x0000C000 // Output divider\r
+#define SYSCTL_PLLCFG_OD_1 0x00000000 // Output divider is 1\r
+#define SYSCTL_PLLCFG_OD_2 0x00004000 // Output divider is 2\r
+#define SYSCTL_PLLCFG_OD_4 0x00008000 // Output divider is 4\r
+#define SYSCTL_PLLCFG_F_MASK 0x00003FE0 // PLL multiplier\r
+#define SYSCTL_PLLCFG_R_MASK 0x0000001F // Input predivider\r
+#define SYSCTL_PLLCFG_F_SHIFT 5\r
+#define SYSCTL_PLLCFG_R_SHIFT 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_RCC2 register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_RCC2_USERCC2 0x80000000 // Use RCC2\r
+#define SYSCTL_RCC2_SYSDIV2_MSK 0x1F800000 // System clock divider\r
+#define SYSCTL_RCC2_SYSDIV2_2 0x00800000 // System clock /2\r
+#define SYSCTL_RCC2_SYSDIV2_3 0x01000000 // System clock /3\r
+#define SYSCTL_RCC2_SYSDIV2_4 0x01800000 // System clock /4\r
+#define SYSCTL_RCC2_SYSDIV2_5 0x02000000 // System clock /5\r
+#define SYSCTL_RCC2_SYSDIV2_6 0x02800000 // System clock /6\r
+#define SYSCTL_RCC2_SYSDIV2_7 0x03000000 // System clock /7\r
+#define SYSCTL_RCC2_SYSDIV2_8 0x03800000 // System clock /8\r
+#define SYSCTL_RCC2_SYSDIV2_9 0x04000000 // System clock /9\r
+#define SYSCTL_RCC2_SYSDIV2_10 0x04800000 // System clock /10\r
+#define SYSCTL_RCC2_SYSDIV2_11 0x05000000 // System clock /11\r
+#define SYSCTL_RCC2_SYSDIV2_12 0x05800000 // System clock /12\r
+#define SYSCTL_RCC2_SYSDIV2_13 0x06000000 // System clock /13\r
+#define SYSCTL_RCC2_SYSDIV2_14 0x06800000 // System clock /14\r
+#define SYSCTL_RCC2_SYSDIV2_15 0x07000000 // System clock /15\r
+#define SYSCTL_RCC2_SYSDIV2_16 0x07800000 // System clock /16\r
+#define SYSCTL_RCC2_SYSDIV2_17 0x08000000 // System clock /17\r
+#define SYSCTL_RCC2_SYSDIV2_18 0x08800000 // System clock /18\r
+#define SYSCTL_RCC2_SYSDIV2_19 0x09000000 // System clock /19\r
+#define SYSCTL_RCC2_SYSDIV2_20 0x09800000 // System clock /20\r
+#define SYSCTL_RCC2_SYSDIV2_21 0x0A000000 // System clock /21\r
+#define SYSCTL_RCC2_SYSDIV2_22 0x0A800000 // System clock /22\r
+#define SYSCTL_RCC2_SYSDIV2_23 0x0B000000 // System clock /23\r
+#define SYSCTL_RCC2_SYSDIV2_24 0x0B800000 // System clock /24\r
+#define SYSCTL_RCC2_SYSDIV2_25 0x0C000000 // System clock /25\r
+#define SYSCTL_RCC2_SYSDIV2_26 0x0C800000 // System clock /26\r
+#define SYSCTL_RCC2_SYSDIV2_27 0x0D000000 // System clock /27\r
+#define SYSCTL_RCC2_SYSDIV2_28 0x0D800000 // System clock /28\r
+#define SYSCTL_RCC2_SYSDIV2_29 0x0E000000 // System clock /29\r
+#define SYSCTL_RCC2_SYSDIV2_30 0x0E800000 // System clock /30\r
+#define SYSCTL_RCC2_SYSDIV2_31 0x0F000000 // System clock /31\r
+#define SYSCTL_RCC2_SYSDIV2_32 0x0F800000 // System clock /32\r
+#define SYSCTL_RCC2_SYSDIV2_33 0x10000000 // System clock /33\r
+#define SYSCTL_RCC2_SYSDIV2_34 0x10800000 // System clock /34\r
+#define SYSCTL_RCC2_SYSDIV2_35 0x11000000 // System clock /35\r
+#define SYSCTL_RCC2_SYSDIV2_36 0x11800000 // System clock /36\r
+#define SYSCTL_RCC2_SYSDIV2_37 0x12000000 // System clock /37\r
+#define SYSCTL_RCC2_SYSDIV2_38 0x12800000 // System clock /38\r
+#define SYSCTL_RCC2_SYSDIV2_39 0x13000000 // System clock /39\r
+#define SYSCTL_RCC2_SYSDIV2_40 0x13800000 // System clock /40\r
+#define SYSCTL_RCC2_SYSDIV2_41 0x14000000 // System clock /41\r
+#define SYSCTL_RCC2_SYSDIV2_42 0x14800000 // System clock /42\r
+#define SYSCTL_RCC2_SYSDIV2_43 0x15000000 // System clock /43\r
+#define SYSCTL_RCC2_SYSDIV2_44 0x15800000 // System clock /44\r
+#define SYSCTL_RCC2_SYSDIV2_45 0x16000000 // System clock /45\r
+#define SYSCTL_RCC2_SYSDIV2_46 0x16800000 // System clock /46\r
+#define SYSCTL_RCC2_SYSDIV2_47 0x17000000 // System clock /47\r
+#define SYSCTL_RCC2_SYSDIV2_48 0x17800000 // System clock /48\r
+#define SYSCTL_RCC2_SYSDIV2_49 0x18000000 // System clock /49\r
+#define SYSCTL_RCC2_SYSDIV2_50 0x18800000 // System clock /50\r
+#define SYSCTL_RCC2_SYSDIV2_51 0x19000000 // System clock /51\r
+#define SYSCTL_RCC2_SYSDIV2_52 0x19800000 // System clock /52\r
+#define SYSCTL_RCC2_SYSDIV2_53 0x1A000000 // System clock /53\r
+#define SYSCTL_RCC2_SYSDIV2_54 0x1A800000 // System clock /54\r
+#define SYSCTL_RCC2_SYSDIV2_55 0x1B000000 // System clock /55\r
+#define SYSCTL_RCC2_SYSDIV2_56 0x1B800000 // System clock /56\r
+#define SYSCTL_RCC2_SYSDIV2_57 0x1C000000 // System clock /57\r
+#define SYSCTL_RCC2_SYSDIV2_58 0x1C800000 // System clock /58\r
+#define SYSCTL_RCC2_SYSDIV2_59 0x1D000000 // System clock /59\r
+#define SYSCTL_RCC2_SYSDIV2_60 0x1D800000 // System clock /60\r
+#define SYSCTL_RCC2_SYSDIV2_61 0x1E000000 // System clock /61\r
+#define SYSCTL_RCC2_SYSDIV2_62 0x1E800000 // System clock /62\r
+#define SYSCTL_RCC2_SYSDIV2_63 0x1F000000 // System clock /63\r
+#define SYSCTL_RCC2_SYSDIV2_64 0x1F800000 // System clock /64\r
+#define SYSCTL_RCC2_PWRDN2 0x00002000 // PLL power down\r
+#define SYSCTL_RCC2_BYPASS2 0x00000800 // PLL bypass\r
+#define SYSCTL_RCC2_OSCSRC2_MSK 0x00000070 // Oscillator input select\r
+#define SYSCTL_RCC2_OSCSRC2_MO 0x00000000 // Use the main oscillator\r
+#define SYSCTL_RCC2_OSCSRC2_IO 0x00000010 // Use the internal oscillator\r
+#define SYSCTL_RCC2_OSCSRC2_IO4 0x00000020 // Use the internal oscillator / 4\r
+#define SYSCTL_RCC2_OSCSRC2_30 0x00000030 // Use the 30 KHz internal osc.\r
+#define SYSCTL_RCC2_OSCSRC2_32 0x00000070 // Use the 32 KHz external osc.\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_DSLPCLKCFG register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_DSLPCLKCFG_D_MSK 0x1f800000 // Deep sleep system clock override\r
+#define SYSCTL_DSLPCLKCFG_D_2 0x00800000 // System clock /2\r
+#define SYSCTL_DSLPCLKCFG_D_3 0x01000000 // System clock /3\r
+#define SYSCTL_DSLPCLKCFG_D_4 0x01800000 // System clock /4\r
+#define SYSCTL_DSLPCLKCFG_D_5 0x02000000 // System clock /5\r
+#define SYSCTL_DSLPCLKCFG_D_6 0x02800000 // System clock /6\r
+#define SYSCTL_DSLPCLKCFG_D_7 0x03000000 // System clock /7\r
+#define SYSCTL_DSLPCLKCFG_D_8 0x03800000 // System clock /8\r
+#define SYSCTL_DSLPCLKCFG_D_9 0x04000000 // System clock /9\r
+#define SYSCTL_DSLPCLKCFG_D_10 0x04800000 // System clock /10\r
+#define SYSCTL_DSLPCLKCFG_D_11 0x05000000 // System clock /11\r
+#define SYSCTL_DSLPCLKCFG_D_12 0x05800000 // System clock /12\r
+#define SYSCTL_DSLPCLKCFG_D_13 0x06000000 // System clock /13\r
+#define SYSCTL_DSLPCLKCFG_D_14 0x06800000 // System clock /14\r
+#define SYSCTL_DSLPCLKCFG_D_15 0x07000000 // System clock /15\r
+#define SYSCTL_DSLPCLKCFG_D_16 0x07800000 // System clock /16\r
+#define SYSCTL_DSLPCLKCFG_D_17 0x08000000 // System clock /17\r
+#define SYSCTL_DSLPCLKCFG_D_18 0x08800000 // System clock /18\r
+#define SYSCTL_DSLPCLKCFG_D_19 0x09000000 // System clock /19\r
+#define SYSCTL_DSLPCLKCFG_D_20 0x09800000 // System clock /20\r
+#define SYSCTL_DSLPCLKCFG_D_21 0x0A000000 // System clock /21\r
+#define SYSCTL_DSLPCLKCFG_D_22 0x0A800000 // System clock /22\r
+#define SYSCTL_DSLPCLKCFG_D_23 0x0B000000 // System clock /23\r
+#define SYSCTL_DSLPCLKCFG_D_24 0x0B800000 // System clock /24\r
+#define SYSCTL_DSLPCLKCFG_D_25 0x0C000000 // System clock /25\r
+#define SYSCTL_DSLPCLKCFG_D_26 0x0C800000 // System clock /26\r
+#define SYSCTL_DSLPCLKCFG_D_27 0x0D000000 // System clock /27\r
+#define SYSCTL_DSLPCLKCFG_D_28 0x0D800000 // System clock /28\r
+#define SYSCTL_DSLPCLKCFG_D_29 0x0E000000 // System clock /29\r
+#define SYSCTL_DSLPCLKCFG_D_30 0x0E800000 // System clock /30\r
+#define SYSCTL_DSLPCLKCFG_D_31 0x0F000000 // System clock /31\r
+#define SYSCTL_DSLPCLKCFG_D_32 0x0F800000 // System clock /32\r
+#define SYSCTL_DSLPCLKCFG_D_33 0x10000000 // System clock /33\r
+#define SYSCTL_DSLPCLKCFG_D_34 0x10800000 // System clock /34\r
+#define SYSCTL_DSLPCLKCFG_D_35 0x11000000 // System clock /35\r
+#define SYSCTL_DSLPCLKCFG_D_36 0x11800000 // System clock /36\r
+#define SYSCTL_DSLPCLKCFG_D_37 0x12000000 // System clock /37\r
+#define SYSCTL_DSLPCLKCFG_D_38 0x12800000 // System clock /38\r
+#define SYSCTL_DSLPCLKCFG_D_39 0x13000000 // System clock /39\r
+#define SYSCTL_DSLPCLKCFG_D_40 0x13800000 // System clock /40\r
+#define SYSCTL_DSLPCLKCFG_D_41 0x14000000 // System clock /41\r
+#define SYSCTL_DSLPCLKCFG_D_42 0x14800000 // System clock /42\r
+#define SYSCTL_DSLPCLKCFG_D_43 0x15000000 // System clock /43\r
+#define SYSCTL_DSLPCLKCFG_D_44 0x15800000 // System clock /44\r
+#define SYSCTL_DSLPCLKCFG_D_45 0x16000000 // System clock /45\r
+#define SYSCTL_DSLPCLKCFG_D_46 0x16800000 // System clock /46\r
+#define SYSCTL_DSLPCLKCFG_D_47 0x17000000 // System clock /47\r
+#define SYSCTL_DSLPCLKCFG_D_48 0x17800000 // System clock /48\r
+#define SYSCTL_DSLPCLKCFG_D_49 0x18000000 // System clock /49\r
+#define SYSCTL_DSLPCLKCFG_D_50 0x18800000 // System clock /50\r
+#define SYSCTL_DSLPCLKCFG_D_51 0x19000000 // System clock /51\r
+#define SYSCTL_DSLPCLKCFG_D_52 0x19800000 // System clock /52\r
+#define SYSCTL_DSLPCLKCFG_D_53 0x1A000000 // System clock /53\r
+#define SYSCTL_DSLPCLKCFG_D_54 0x1A800000 // System clock /54\r
+#define SYSCTL_DSLPCLKCFG_D_55 0x1B000000 // System clock /55\r
+#define SYSCTL_DSLPCLKCFG_D_56 0x1B800000 // System clock /56\r
+#define SYSCTL_DSLPCLKCFG_D_57 0x1C000000 // System clock /57\r
+#define SYSCTL_DSLPCLKCFG_D_58 0x1C800000 // System clock /58\r
+#define SYSCTL_DSLPCLKCFG_D_59 0x1D000000 // System clock /59\r
+#define SYSCTL_DSLPCLKCFG_D_60 0x1D800000 // System clock /60\r
+#define SYSCTL_DSLPCLKCFG_D_61 0x1E000000 // System clock /61\r
+#define SYSCTL_DSLPCLKCFG_D_62 0x1E800000 // System clock /62\r
+#define SYSCTL_DSLPCLKCFG_D_63 0x1F000000 // System clock /63\r
+#define SYSCTL_DSLPCLKCFG_D_64 0x1F800000 // System clock /64\r
+#define SYSCTL_DSLPCLKCFG_O_MSK 0x00000070 // Deep sleep oscillator override\r
+#define SYSCTL_DSLPCLKCFG_O_IGN 0x00000000 // Do not override\r
+#define SYSCTL_DSLPCLKCFG_O_IO 0x00000010 // Use the internal oscillator\r
+#define SYSCTL_DSLPCLKCFG_O_30 0x00000030 // Use the 30 KHz internal osc.\r
+#define SYSCTL_DSLPCLKCFG_O_32 0x00000070 // Use the 32 KHz external osc.\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_CLKVCLR register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_CLKVCLR_CLR 0x00000001 // Clear clock verification fault\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_LDOARST register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_LDOARST_ARST 0x00000001 // Allow LDO to reset device\r
+\r
+#endif // __HW_SYSCTL_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_timer.h - Defines and macros used when accessing the timer.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_TIMER_H__\r
+#define __HW_TIMER_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the offsets of the timer registers.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_O_CFG 0x00000000 // Configuration register\r
+#define TIMER_O_TAMR 0x00000004 // TimerA mode register\r
+#define TIMER_O_TBMR 0x00000008 // TimerB mode register\r
+#define TIMER_O_CTL 0x0000000C // Control register\r
+#define TIMER_O_IMR 0x00000018 // Interrupt mask register\r
+#define TIMER_O_RIS 0x0000001C // Interrupt status register\r
+#define TIMER_O_MIS 0x00000020 // Masked interrupt status reg.\r
+#define TIMER_O_ICR 0x00000024 // Interrupt clear register\r
+#define TIMER_O_TAILR 0x00000028 // TimerA interval load register\r
+#define TIMER_O_TBILR 0x0000002C // TimerB interval load register\r
+#define TIMER_O_TAMATCHR 0x00000030 // TimerA match register\r
+#define TIMER_O_TBMATCHR 0x00000034 // TimerB match register\r
+#define TIMER_O_TAPR 0x00000038 // TimerA prescale register\r
+#define TIMER_O_TBPR 0x0000003C // TimerB prescale register\r
+#define TIMER_O_TAPMR 0x00000040 // TimerA prescale match register\r
+#define TIMER_O_TBPMR 0x00000044 // TimerB prescale match register\r
+#define TIMER_O_TAR 0x00000048 // TimerA register\r
+#define TIMER_O_TBR 0x0000004C // TimerB register\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the reset values of the timer registers.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_RV_CFG 0x00000000 // Configuration register RV\r
+#define TIMER_RV_TAMR 0x00000000 // TimerA mode register RV\r
+#define TIMER_RV_TBMR 0x00000000 // TimerB mode register RV\r
+#define TIMER_RV_CTL 0x00000000 // Control register RV\r
+#define TIMER_RV_IMR 0x00000000 // Interrupt mask register RV\r
+#define TIMER_RV_RIS 0x00000000 // Interrupt status register RV\r
+#define TIMER_RV_MIS 0x00000000 // Masked interrupt status reg RV\r
+#define TIMER_RV_ICR 0x00000000 // Interrupt clear register RV\r
+#define TIMER_RV_TAILR 0xFFFFFFFF // TimerA interval load reg RV\r
+#define TIMER_RV_TBILR 0x0000FFFF // TimerB interval load reg RV\r
+#define TIMER_RV_TAMATCHR 0xFFFFFFFF // TimerA match register RV\r
+#define TIMER_RV_TBMATCHR 0x0000FFFF // TimerB match register RV\r
+#define TIMER_RV_TAPR 0x00000000 // TimerA prescale register RV\r
+#define TIMER_RV_TBPR 0x00000000 // TimerB prescale register RV\r
+#define TIMER_RV_TAPMR 0x00000000 // TimerA prescale match reg RV\r
+#define TIMER_RV_TBPMR 0x00000000 // TimerB prescale match regi RV\r
+#define TIMER_RV_TAR 0xFFFFFFFF // TimerA register RV\r
+#define TIMER_RV_TBR 0x0000FFFF // TimerB register RV\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the TIMER_CFG register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_CFG_CFG_MSK 0x00000007 // Configuration options mask\r
+#define TIMER_CFG_16_BIT 0x00000004 // Two 16 bit timers\r
+#define TIMER_CFG_32_BIT_RTC 0x00000001 // 32 bit RTC\r
+#define TIMER_CFG_32_BIT_TIMER 0x00000000 // 32 bit timer\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the TIMER_TnMR register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_TNMR_TNAMS 0x00000008 // Alternate mode select\r
+#define TIMER_TNMR_TNCMR 0x00000004 // Capture mode - count or time\r
+#define TIMER_TNMR_TNTMR_MSK 0x00000003 // Timer mode mask\r
+#define TIMER_TNMR_TNTMR_CAP 0x00000003 // Mode - capture\r
+#define TIMER_TNMR_TNTMR_PERIOD 0x00000002 // Mode - periodic\r
+#define TIMER_TNMR_TNTMR_1_SHOT 0x00000001 // Mode - one shot\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the TIMER_CTL register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_CTL_TBPWML 0x00004000 // TimerB PWM output level invert\r
+#define TIMER_CTL_TBOTE 0x00002000 // TimerB output trigger enable\r
+#define TIMER_CTL_TBEVENT_MSK 0x00000C00 // TimerB event mode mask\r
+#define TIMER_CTL_TBEVENT_BOTH 0x00000C00 // TimerB event mode - both edges\r
+#define TIMER_CTL_TBEVENT_NEG 0x00000400 // TimerB event mode - neg edge\r
+#define TIMER_CTL_TBEVENT_POS 0x00000000 // TimerB event mode - pos edge\r
+#define TIMER_CTL_TBSTALL 0x00000200 // TimerB stall enable\r
+#define TIMER_CTL_TBEN 0x00000100 // TimerB enable\r
+#define TIMER_CTL_TAPWML 0x00000040 // TimerA PWM output level invert\r
+#define TIMER_CTL_TAOTE 0x00000020 // TimerA output trigger enable\r
+#define TIMER_CTL_RTCEN 0x00000010 // RTC counter enable\r
+#define TIMER_CTL_TAEVENT_MSK 0x0000000C // TimerA event mode mask\r
+#define TIMER_CTL_TAEVENT_BOTH 0x0000000C // TimerA event mode - both edges\r
+#define TIMER_CTL_TAEVENT_NEG 0x00000004 // TimerA event mode - neg edge\r
+#define TIMER_CTL_TAEVENT_POS 0x00000000 // TimerA event mode - pos edge\r
+#define TIMER_CTL_TASTALL 0x00000002 // TimerA stall enable\r
+#define TIMER_CTL_TAEN 0x00000001 // TimerA enable\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the TIMER_IMR register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_IMR_CBEIM 0x00000400 // CaptureB event interrupt mask\r
+#define TIMER_IMR_CBMIM 0x00000200 // CaptureB match interrupt mask\r
+#define TIMER_IMR_TBTOIM 0x00000100 // TimerB time out interrupt mask\r
+#define TIMER_IMR_RTCIM 0x00000008 // RTC interrupt mask\r
+#define TIMER_IMR_CAEIM 0x00000004 // CaptureA event interrupt mask\r
+#define TIMER_IMR_CAMIM 0x00000002 // CaptureA match interrupt mask\r
+#define TIMER_IMR_TATOIM 0x00000001 // TimerA time out interrupt mask\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the TIMER_RIS register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_RIS_CBERIS 0x00000400 // CaptureB event raw int status\r
+#define TIMER_RIS_CBMRIS 0x00000200 // CaptureB match raw int status\r
+#define TIMER_RIS_TBTORIS 0x00000100 // TimerB time out raw int status\r
+#define TIMER_RIS_RTCRIS 0x00000008 // RTC raw int status\r
+#define TIMER_RIS_CAERIS 0x00000004 // CaptureA event raw int status\r
+#define TIMER_RIS_CAMRIS 0x00000002 // CaptureA match raw int status\r
+#define TIMER_RIS_TATORIS 0x00000001 // TimerA time out raw int status\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the TIMER_MIS register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_RIS_CBEMIS 0x00000400 // CaptureB event masked int status\r
+#define TIMER_RIS_CBMMIS 0x00000200 // CaptureB match masked int status\r
+#define TIMER_RIS_TBTOMIS 0x00000100 // TimerB time out masked int stat\r
+#define TIMER_RIS_RTCMIS 0x00000008 // RTC masked int status\r
+#define TIMER_RIS_CAEMIS 0x00000004 // CaptureA event masked int status\r
+#define TIMER_RIS_CAMMIS 0x00000002 // CaptureA match masked int status\r
+#define TIMER_RIS_TATOMIS 0x00000001 // TimerA time out masked int stat\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the TIMER_ICR register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_ICR_CBECINT 0x00000400 // CaptureB event interrupt clear\r
+#define TIMER_ICR_CBMCINT 0x00000200 // CaptureB match interrupt clear\r
+#define TIMER_ICR_TBTOCINT 0x00000100 // TimerB time out interrupt clear\r
+#define TIMER_ICR_RTCCINT 0x00000008 // RTC interrupt clear\r
+#define TIMER_ICR_CAECINT 0x00000004 // CaptureA event interrupt clear\r
+#define TIMER_ICR_CAMCINT 0x00000002 // CaptureA match interrupt clear\r
+#define TIMER_ICR_TATOCINT 0x00000001 // TimerA time out interrupt clear\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the TIMER_TAILR register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_TAILR_TAILRH 0xFFFF0000 // TimerB load val in 32 bit mode\r
+#define TIMER_TAILR_TAILRL 0x0000FFFF // TimerA interval load value\r
+\r
+//*****************************************************************************\r
+//\r
+// The following defines the bit fields in the TIMER_TBILR register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_TBILR_TBILRL 0x0000FFFF // TimerB interval load value\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the TIMER_TAMATCHR register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_TAMATCHR_TAMRH 0xFFFF0000 // TimerB match val in 32 bit mode\r
+#define TIMER_TAMATCHR_TAMRL 0x0000FFFF // TimerA match value\r
+\r
+//*****************************************************************************\r
+//\r
+// The following defines the bit fields in the TIMER_TBMATCHR register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_TBMATCHR_TBMRL 0x0000FFFF // TimerB match load value\r
+\r
+//*****************************************************************************\r
+//\r
+// The following defines the bit fields in the TIMER_TnPR register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_TNPR_TNPSR 0x000000FF // TimerN prescale value\r
+\r
+//*****************************************************************************\r
+//\r
+// The following defines the bit fields in the TIMER_TnPMR register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_TNPMR_TNPSMR 0x000000FF // TimerN prescale match value\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the TIMER_TAR register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_TAR_TARH 0xFFFF0000 // TimerB val in 32 bit mode\r
+#define TIMER_TAR_TARL 0x0000FFFF // TimerA value\r
+\r
+//*****************************************************************************\r
+//\r
+// The following defines the bit fields in the TIMER_TBR register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_TBR_TBRL 0x0000FFFF // TimerB value\r
+\r
+#endif // __HW_TIMER_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_types.h - Common types and macros.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_TYPES_H__\r
+#define __HW_TYPES_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// Define a boolean type, and values for true and false.\r
+//\r
+//*****************************************************************************\r
+typedef unsigned char tBoolean;\r
+\r
+#ifndef true\r
+#define true 1\r
+#endif\r
+\r
+#ifndef false\r
+#define false 0\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Macros for hardware access, both direct and via the bit-band region.\r
+//\r
+//*****************************************************************************\r
+#define HWREG(x) \\r
+ (*((volatile unsigned long *)(x)))\r
+#define HWREGH(x) \\r
+ (*((volatile unsigned short *)(x)))\r
+#define HWREGB(x) \\r
+ (*((volatile unsigned char *)(x)))\r
+#define HWREGBITW(x, b) \\r
+ HWREG(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \\r
+ (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2))\r
+#define HWREGBITH(x, b) \\r
+ HWREGH(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \\r
+ (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2))\r
+#define HWREGBITB(x, b) \\r
+ HWREGB(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \\r
+ (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2))\r
+\r
+//*****************************************************************************\r
+//\r
+// Helper Macros for determining silicon revisions, etc.\r
+//\r
+// These macros will be used by Driverlib at "run-time" to create necessary\r
+// conditional code blocks that will allow a single version of the Driverlib\r
+// "binary" code to support multiple(all) Stellaris silicon revisions.\r
+//\r
+// It is expected that these macros will be used inside of a standard 'C' \r
+// conditional block of code, e.g.\r
+//\r
+// if(DEVICE_IS_SANDSTORM())\r
+// {\r
+// do some Sandstorm specific code here.\r
+// }\r
+//\r
+// By default, these macros will be defined as run-time checks of the\r
+// appropriate register(s) to allow creation of run-time conditional code\r
+// blocks for a common DriverLib across the entire Stellaris family.\r
+//\r
+// However, if code-space optimization is required, these macros can be "hard-\r
+// coded" for a specific version of Stellaris silicon. Many compilers will\r
+// then detect the "hard-coded" conditionals, and appropriately optimize the\r
+// code blocks, eliminating any "unreachable" code. This would result in \r
+// a smaller Driverlib, thus producing a smaller final application size, but\r
+// at the cost of limiting the Driverlib binary to a specific Stellaris\r
+// silicon revision.\r
+//\r
+//*****************************************************************************\r
+#ifndef DEVICE_IS_SANDSTORM\r
+#define DEVICE_IS_SANDSTORM \\r
+ (((HWREG(SYSCTL_DID0) & SYSCTL_DID0_VER_MASK) == SYSCTL_DID0_VER_0) || \\r
+ (((HWREG(SYSCTL_DID0) & SYSCTL_DID0_VER_MASK) == SYSCTL_DID0_VER_1) && \\r
+ ((HWREG(SYSCTL_DID0) & SYSCTL_DID0_CLASS_MASK) == \\r
+ SYSCTL_DID0_CLASS_SANDSTORM)))\r
+#endif\r
+\r
+#ifndef DEVICE_IS_FURY\r
+#define DEVICE_IS_FURY \\r
+ (((HWREG(SYSCTL_DID0) & SYSCTL_DID0_VER_MASK) == SYSCTL_DID0_VER_1) && \\r
+ ((HWREG(SYSCTL_DID0) & SYSCTL_DID0_CLASS_MASK) == \\r
+ SYSCTL_DID0_CLASS_FURY))\r
+#endif\r
+\r
+#ifndef DEVICE_IS_REVA2\r
+#define DEVICE_IS_REVA2 \\r
+ (((HWREG(SYSCTL_DID0) & SYSCTL_DID0_MAJ_MASK) == SYSCTL_DID0_MAJ_A) && \\r
+ ((HWREG(SYSCTL_DID0) & SYSCTL_DID0_MIN_MASK) == SYSCTL_DID0_MIN_2))\r
+#endif\r
+\r
+#ifndef DEVICE_IS_REVC1\r
+#define DEVICE_IS_REVC1 \\r
+ (((HWREG(SYSCTL_DID0) & SYSCTL_DID0_MAJ_MASK) == SYSCTL_DID0_MAJ_C) && \\r
+ ((HWREG(SYSCTL_DID0) & SYSCTL_DID0_MIN_MASK) == SYSCTL_DID0_MIN_1))\r
+#endif\r
+\r
+#ifndef DEVICE_IS_REVC2\r
+#define DEVICE_IS_REVC2 \\r
+ (((HWREG(SYSCTL_DID0) & SYSCTL_DID0_MAJ_MASK) == SYSCTL_DID0_MAJ_C) && \\r
+ ((HWREG(SYSCTL_DID0) & SYSCTL_DID0_MIN_MASK) == SYSCTL_DID0_MIN_2))\r
+#endif\r
+\r
+#endif // __HW_TYPES_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_uart.h - Macros and defines used when accessing the UART hardware\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_UART_H__\r
+#define __HW_UART_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// UART Register Offsets.\r
+//\r
+//*****************************************************************************\r
+#define UART_O_DR 0x00000000 // Data Register\r
+#define UART_O_RSR 0x00000004 // Receive Status Register (read)\r
+#define UART_O_ECR 0x00000004 // Error Clear Register (write)\r
+#define UART_O_FR 0x00000018 // Flag Register (read only)\r
+#define UART_O_IBRD 0x00000024 // Integer Baud Rate Divisor Reg\r
+#define UART_O_FBRD 0x00000028 // Fractional Baud Rate Divisor Reg\r
+#define UART_O_LCR_H 0x0000002C // Line Control Register, HIGH byte\r
+#define UART_O_CTL 0x00000030 // Control Register\r
+#define UART_O_IFLS 0x00000034 // Interrupt FIFO Level Select Reg\r
+#define UART_O_IM 0x00000038 // Interrupt Mask Set/Clear Reg\r
+#define UART_O_RIS 0x0000003C // Raw Interrupt Status Register\r
+#define UART_O_MIS 0x00000040 // Masked Interrupt Status Register\r
+#define UART_O_ICR 0x00000044 // Interrupt Clear Register\r
+#define UART_O_PeriphID4 0x00000FD0 //\r
+#define UART_O_PeriphID5 0x00000FD4 //\r
+#define UART_O_PeriphID6 0x00000FD8 //\r
+#define UART_O_PeriphID7 0x00000FDC //\r
+#define UART_O_PeriphID0 0x00000FE0 //\r
+#define UART_O_PeriphID1 0x00000FE4 //\r
+#define UART_O_PeriphID2 0x00000FE8 //\r
+#define UART_O_PeriphID3 0x00000FEC //\r
+#define UART_O_PCellID0 0x00000FF0 //\r
+#define UART_O_PCellID1 0x00000FF4 //\r
+#define UART_O_PCellID2 0x00000FF8 //\r
+#define UART_O_PCellID3 0x00000FFC //\r
+\r
+//*****************************************************************************\r
+//\r
+// Data Register bits\r
+//\r
+//*****************************************************************************\r
+#define UART_DR_OE 0x00000800 // Overrun Error\r
+#define UART_DR_BE 0x00000400 // Break Error\r
+#define UART_DR_PE 0x00000200 // Parity Error\r
+#define UART_DR_FE 0x00000100 // Framing Error\r
+#define UART_DR_DATA_MASK 0x000000FF // UART data\r
+\r
+//*****************************************************************************\r
+//\r
+// Receive Status Register bits\r
+//\r
+//*****************************************************************************\r
+#define UART_RSR_OE 0x00000008 // Overrun Error\r
+#define UART_RSR_BE 0x00000004 // Break Error\r
+#define UART_RSR_PE 0x00000002 // Parity Error\r
+#define UART_RSR_FE 0x00000001 // Framing Error\r
+\r
+//*****************************************************************************\r
+//\r
+// Flag Register bits\r
+//\r
+//*****************************************************************************\r
+#define UART_FR_TXFE 0x00000080 // TX FIFO Empty\r
+#define UART_FR_RXFF 0x00000040 // RX FIFO Full\r
+#define UART_FR_TXFF 0x00000020 // TX FIFO Full\r
+#define UART_FR_RXFE 0x00000010 // RX FIFO Empty\r
+#define UART_FR_BUSY 0x00000008 // UART Busy\r
+\r
+//*****************************************************************************\r
+//\r
+// Integer baud-rate divisor\r
+//\r
+//*****************************************************************************\r
+#define UART_IBRD_DIVINT_MASK 0x0000FFFF // Integer baud-rate divisor\r
+\r
+//*****************************************************************************\r
+//\r
+// Fractional baud-rate divisor\r
+//\r
+//*****************************************************************************\r
+#define UART_FBRD_DIVFRAC_MASK 0x0000003F // Fractional baud-rate divisor\r
+\r
+//*****************************************************************************\r
+//\r
+// Line Control Register High bits\r
+//\r
+//*****************************************************************************\r
+#define UART_LCR_H_SPS 0x00000080 // Stick Parity Select\r
+#define UART_LCR_H_WLEN 0x00000060 // Word length\r
+#define UART_LCR_H_WLEN_8 0x00000060 // 8 bit data\r
+#define UART_LCR_H_WLEN_7 0x00000040 // 7 bit data\r
+#define UART_LCR_H_WLEN_6 0x00000020 // 6 bit data\r
+#define UART_LCR_H_WLEN_5 0x00000000 // 5 bit data\r
+#define UART_LCR_H_FEN 0x00000010 // Enable FIFO\r
+#define UART_LCR_H_STP2 0x00000008 // Two Stop Bits Select\r
+#define UART_LCR_H_EPS 0x00000004 // Even Parity Select\r
+#define UART_LCR_H_PEN 0x00000002 // Parity Enable\r
+#define UART_LCR_H_BRK 0x00000001 // Send Break\r
+\r
+//*****************************************************************************\r
+//\r
+// Control Register bits\r
+//\r
+//*****************************************************************************\r
+#define UART_CTL_RXE 0x00000200 // Receive Enable\r
+#define UART_CTL_TXE 0x00000100 // Transmit Enable\r
+#define UART_CTL_LBE 0x00000080 // Loopback Enable\r
+#define UART_CTL_SIRLP 0x00000004 // SIR (IrDA) Low Power Enable\r
+#define UART_CTL_SIREN 0x00000002 // SIR (IrDA) Enable\r
+#define UART_CTL_UARTEN 0x00000001 // UART Enable\r
+\r
+//*****************************************************************************\r
+//\r
+// Interrupt FIFO Level Select Register bits\r
+//\r
+//*****************************************************************************\r
+#define UART_IFLS_RX1_8 0x00000000 // 1/8 Full\r
+#define UART_IFLS_RX2_8 0x00000010 // 1/4 Full\r
+#define UART_IFLS_RX4_8 0x00000020 // 1/2 Full\r
+#define UART_IFLS_RX6_8 0x00000030 // 3/4 Full\r
+#define UART_IFLS_RX7_8 0x00000040 // 7/8 Full\r
+#define UART_IFLS_TX1_8 0x00000000 // 1/8 Full\r
+#define UART_IFLS_TX2_8 0x00000001 // 1/4 Full\r
+#define UART_IFLS_TX4_8 0x00000002 // 1/2 Full\r
+#define UART_IFLS_TX6_8 0x00000003 // 3/4 Full\r
+#define UART_IFLS_TX7_8 0x00000004 // 7/8 Full\r
+\r
+//*****************************************************************************\r
+//\r
+// Interrupt Mask Set/Clear Register bits\r
+//\r
+//*****************************************************************************\r
+#define UART_IM_OEIM 0x00000400 // Overrun Error Interrupt Mask\r
+#define UART_IM_BEIM 0x00000200 // Break Error Interrupt Mask\r
+#define UART_IM_PEIM 0x00000100 // Parity Error Interrupt Mask\r
+#define UART_IM_FEIM 0x00000080 // Framing Error Interrupt Mask\r
+#define UART_IM_RTIM 0x00000040 // Receive Timeout Interrupt Mask\r
+#define UART_IM_TXIM 0x00000020 // Transmit Interrupt Mask\r
+#define UART_IM_RXIM 0x00000010 // Receive Interrupt Mask\r
+\r
+//*****************************************************************************\r
+//\r
+// Raw Interrupt Status Register\r
+//\r
+//*****************************************************************************\r
+#define UART_RIS_OERIS 0x00000400 // Overrun Error Interrupt Status\r
+#define UART_RIS_BERIS 0x00000200 // Break Error Interrupt Status\r
+#define UART_RIS_PERIS 0x00000100 // Parity Error Interrupt Status\r
+#define UART_RIS_FERIS 0x00000080 // Framing Error Interrupt Status\r
+#define UART_RIS_RTRIS 0x00000040 // Receive Timeout Interrupt Status\r
+#define UART_RIS_TXRIS 0x00000020 // Transmit Interrupt Status\r
+#define UART_RIS_RXRIS 0x00000010 // Receive Interrupt Status\r
+\r
+//*****************************************************************************\r
+//\r
+// Masked Interrupt Status Register\r
+//\r
+//*****************************************************************************\r
+#define UART_MIS_OEMIS 0x00000400 // Overrun Error Interrupt Status\r
+#define UART_MIS_BEMIS 0x00000200 // Break Error Interrupt Status\r
+#define UART_MIS_PEMIS 0x00000100 // Parity Error Interrupt Status\r
+#define UART_MIS_FEMIS 0x00000080 // Framing Error Interrupt Status\r
+#define UART_MIS_RTMIS 0x00000040 // Receive Timeout Interrupt Status\r
+#define UART_MIS_TXMIS 0x00000020 // Transmit Interrupt Status\r
+#define UART_MIS_RXMIS 0x00000010 // Receive Interrupt Status\r
+\r
+//*****************************************************************************\r
+//\r
+// Interrupt Clear Register bits\r
+//\r
+//*****************************************************************************\r
+#define UART_ICR_OEIC 0x00000400 // Overrun Error Interrupt Clear\r
+#define UART_ICR_BEIC 0x00000200 // Break Error Interrupt Clear\r
+#define UART_ICR_PEIC 0x00000100 // Parity Error Interrupt Clear\r
+#define UART_ICR_FEIC 0x00000080 // Framing Error Interrupt Clear\r
+#define UART_ICR_RTIC 0x00000040 // Receive Timeout Interrupt Clear\r
+#define UART_ICR_TXIC 0x00000020 // Transmit Interrupt Clear\r
+#define UART_ICR_RXIC 0x00000010 // Receive Interrupt Clear\r
+\r
+#define UART_RSR_ANY (UART_RSR_OE | \\r
+ UART_RSR_BE | \\r
+ UART_RSR_PE | \\r
+ UART_RSR_FE)\r
+\r
+//*****************************************************************************\r
+//\r
+// Reset Values for UART Registers.\r
+//\r
+//*****************************************************************************\r
+#define UART_RV_DR 0x00000000\r
+#define UART_RV_RSR 0x00000000\r
+#define UART_RV_ECR 0x00000000\r
+#define UART_RV_FR 0x00000090\r
+#define UART_RV_IBRD 0x00000000\r
+#define UART_RV_FBRD 0x00000000\r
+#define UART_RV_LCR_H 0x00000000\r
+#define UART_RV_CTL 0x00000300\r
+#define UART_RV_IFLS 0x00000012\r
+#define UART_RV_IM 0x00000000\r
+#define UART_RV_RIS 0x00000000\r
+#define UART_RV_MIS 0x00000000\r
+#define UART_RV_ICR 0x00000000\r
+#define UART_RV_PeriphID4 0x00000000\r
+#define UART_RV_PeriphID5 0x00000000\r
+#define UART_RV_PeriphID6 0x00000000\r
+#define UART_RV_PeriphID7 0x00000000\r
+#define UART_RV_PeriphID0 0x00000011\r
+#define UART_RV_PeriphID1 0x00000000\r
+#define UART_RV_PeriphID2 0x00000018\r
+#define UART_RV_PeriphID3 0x00000001\r
+#define UART_RV_PCellID0 0x0000000D\r
+#define UART_RV_PCellID1 0x000000F0\r
+#define UART_RV_PCellID2 0x00000005\r
+#define UART_RV_PCellID3 0x000000B1\r
+\r
+#endif // __HW_UART_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_watchdog.h - Macros used when accessing the Watchdog Timer hardware.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_WATCHDOG_H__\r
+#define __HW_WATCHDOG_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the offsets of the Watchdog Timer registers.\r
+//\r
+//*****************************************************************************\r
+#define WDT_O_LOAD 0x00000000 // Load register\r
+#define WDT_O_VALUE 0x00000004 // Current value register\r
+#define WDT_O_CTL 0x00000008 // Control register\r
+#define WDT_O_ICR 0x0000000C // Interrupt clear register\r
+#define WDT_O_RIS 0x00000010 // Raw interrupt status register\r
+#define WDT_O_MIS 0x00000014 // Masked interrupt status register\r
+#define WDT_O_TEST 0x00000418 // Test register\r
+#define WDT_O_LOCK 0x00000C00 // Lock register\r
+#define WDT_O_PeriphID4 0x00000FD0 //\r
+#define WDT_O_PeriphID5 0x00000FD4 //\r
+#define WDT_O_PeriphID6 0x00000FD8 //\r
+#define WDT_O_PeriphID7 0x00000FDC //\r
+#define WDT_O_PeriphID0 0x00000FE0 //\r
+#define WDT_O_PeriphID1 0x00000FE4 //\r
+#define WDT_O_PeriphID2 0x00000FE8 //\r
+#define WDT_O_PeriphID3 0x00000FEC //\r
+#define WDT_O_PCellID0 0x00000FF0 //\r
+#define WDT_O_PCellID1 0x00000FF4 //\r
+#define WDT_O_PCellID2 0x00000FF8 //\r
+#define WDT_O_PCellID3 0x00000FFC //\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the WDT_CTL register.\r
+//\r
+//*****************************************************************************\r
+#define WDT_CTL_RESEN 0x00000002 // Enable reset output\r
+#define WDT_CTL_INTEN 0x00000001 // Enable the WDT counter and int\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the WDT_ISR, WDT_RIS, and WDT_MIS\r
+// registers.\r
+//\r
+//*****************************************************************************\r
+#define WDT_INT_TIMEOUT 0x00000001 // Watchdog timer expired\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the WDT_TEST register.\r
+//\r
+//*****************************************************************************\r
+#define WDT_TEST_STALL 0x00000100 // Watchdog stall enable\r
+#ifndef DEPRECATED\r
+#define WDT_TEST_STALL_EN 0x00000100 // Watchdog stall enable\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the WDT_LOCK register.\r
+//\r
+//*****************************************************************************\r
+#define WDT_LOCK_LOCKED 0x00000001 // Watchdog timer is locked\r
+#define WDT_LOCK_UNLOCKED 0x00000000 // Watchdog timer is unlocked\r
+#define WDT_LOCK_UNLOCK 0x1ACCE551 // Unlocks the watchdog timer\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the reset values for the WDT registers.\r
+//\r
+//*****************************************************************************\r
+#define WDT_RV_LOAD 0xFFFFFFFF // Load register\r
+#define WDT_RV_VALUE 0xFFFFFFFF // Current value register\r
+#define WDT_RV_CTL 0x00000000 // Control register\r
+#define WDT_RV_RIS 0x00000000 // Raw interrupt status register\r
+#define WDT_RV_MIS 0x00000000 // Masked interrupt status register\r
+#define WDT_RV_LOCK 0x00000000 // Lock register\r
+#define WDT_RV_PeriphID4 0x00000000 //\r
+#define WDT_RV_PeriphID5 0x00000000 //\r
+#define WDT_RV_PeriphID6 0x00000000 //\r
+#define WDT_RV_PeriphID7 0x00000000 //\r
+#define WDT_RV_PeriphID0 0x00000005 //\r
+#define WDT_RV_PeriphID1 0x00000018 //\r
+#define WDT_RV_PeriphID2 0x00000018 //\r
+#define WDT_RV_PeriphID3 0x00000001 //\r
+#define WDT_RV_PCellID0 0x0000000D //\r
+#define WDT_RV_PCellID1 0x000000F0 //\r
+#define WDT_RV_PCellID2 0x00000005 //\r
+#define WDT_RV_PCellID3 0x000000B1 //\r
+\r
+#endif // __HW_WATCHDOG_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// i2c.h - Prototypes for the I2C Driver.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __I2C_H__\r
+#define __I2C_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Defines for the API.\r
+//\r
+//*****************************************************************************\r
+//*****************************************************************************\r
+//\r
+// Interrupt defines.\r
+//\r
+//*****************************************************************************\r
+#define I2C_INT_MASTER 0x00000001\r
+#define I2C_INT_SLAVE 0x00000002\r
+\r
+//*****************************************************************************\r
+//\r
+// I2C Master commands.\r
+//\r
+//*****************************************************************************\r
+#define I2C_MASTER_CMD_SINGLE_SEND \\r
+ (I2C_MASTER_CS_STOP | I2C_MASTER_CS_START | I2C_MASTER_CS_RUN)\r
+#define I2C_MASTER_CMD_SINGLE_RECEIVE \\r
+ (I2C_MASTER_CS_STOP | I2C_MASTER_CS_START | I2C_MASTER_CS_RUN)\r
+#define I2C_MASTER_CMD_BURST_SEND_START \\r
+ (I2C_MASTER_CS_START | I2C_MASTER_CS_RUN)\r
+#define I2C_MASTER_CMD_BURST_SEND_CONT \\r
+ (I2C_MASTER_CS_RUN)\r
+#define I2C_MASTER_CMD_BURST_SEND_FINISH \\r
+ (I2C_MASTER_CS_STOP | I2C_MASTER_CS_RUN)\r
+#define I2C_MASTER_CMD_BURST_SEND_ERROR_STOP \\r
+ (I2C_MASTER_CS_STOP)\r
+#define I2C_MASTER_CMD_BURST_RECEIVE_START \\r
+ (I2C_MASTER_CS_ACK | I2C_MASTER_CS_START | I2C_MASTER_CS_RUN)\r
+#define I2C_MASTER_CMD_BURST_RECEIVE_CONT \\r
+ (I2C_MASTER_CS_ACK | I2C_MASTER_CS_RUN)\r
+#define I2C_MASTER_CMD_BURST_RECEIVE_FINISH \\r
+ (I2C_MASTER_CS_STOP | I2C_MASTER_CS_RUN)\r
+#define I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP \\r
+ (I2C_MASTER_CS_STOP | I2C_MASTER_CS_RUN)\r
+\r
+//*****************************************************************************\r
+//\r
+// I2C Master error status.\r
+//\r
+//*****************************************************************************\r
+#define I2C_MASTER_ERR_NONE 0\r
+#define I2C_MASTER_ERR_ADDR_ACK 0x00000004\r
+#define I2C_MASTER_ERR_DATA_ACK 0x00000008\r
+#define I2C_MASTER_ERR_ARB_LOST 0x00000010\r
+\r
+//*****************************************************************************\r
+//\r
+// I2C Slave action requests\r
+//\r
+//*****************************************************************************\r
+#define I2C_SLAVE_ACT_NONE 0\r
+#define I2C_SLAVE_ACT_RREQ 0x00000001 // Master has sent data\r
+#define I2C_SLAVE_ACT_TREQ 0x00000002 // Master has requested data\r
+\r
+//*****************************************************************************\r
+// Miscellaneous I2C driver definitions.\r
+//*****************************************************************************\r
+#define I2C_MASTER_MAX_RETRIES 1000 // Number of retries\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+extern void I2CIntRegister(unsigned long ulBase, void(fnHandler)(void));\r
+extern void I2CIntUnregister(unsigned long ulBase);\r
+extern tBoolean I2CMasterBusBusy(unsigned long ulBase);\r
+extern tBoolean I2CMasterBusy(unsigned long ulBase);\r
+extern void I2CMasterControl(unsigned long ulBase, unsigned long ulCmd);\r
+extern unsigned long I2CMasterDataGet(unsigned long ulBase);\r
+extern void I2CMasterDataPut(unsigned long ulBase, unsigned char ucData);\r
+extern void I2CMasterDisable(unsigned long ulBase);\r
+extern void I2CMasterEnable(unsigned long ulBase);\r
+extern unsigned long I2CMasterErr(unsigned long ulBase);\r
+extern void I2CMasterInit(unsigned long ulBase, tBoolean bFast);\r
+extern void I2CMasterIntClear(unsigned long ulBase);\r
+extern void I2CMasterIntDisable(unsigned long ulBase);\r
+extern void I2CMasterIntEnable(unsigned long ulBase);\r
+extern tBoolean I2CMasterIntStatus(unsigned long ulBase, tBoolean bMasked);\r
+extern void I2CMasterSlaveAddrSet(unsigned long ulBase,\r
+ unsigned char ucSlaveAddr,\r
+ tBoolean bReceive);\r
+extern unsigned long I2CSlaveDataGet(unsigned long ulBase);\r
+extern void I2CSlaveDataPut(unsigned long ulBase, unsigned char ucData);\r
+extern void I2CSlaveDisable(unsigned long ulBase);\r
+extern void I2CSlaveEnable(unsigned long ulBase);\r
+extern void I2CSlaveInit(unsigned long ulBase, unsigned char ucSlaveAddr);\r
+extern void I2CSlaveIntClear(unsigned long ulBase);\r
+extern void I2CSlaveIntDisable(unsigned long ulBase);\r
+extern void I2CSlaveIntEnable(unsigned long ulBase);\r
+extern tBoolean I2CSlaveIntStatus(unsigned long ulBase, tBoolean bMasked);\r
+extern unsigned long I2CSlaveStatus(unsigned long ulBase);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __I2C_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// interrupt.h - Prototypes for the NVIC Interrupt Controller Driver.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __INTERRUPT_H__\r
+#define __INTERRUPT_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+extern void IntMasterEnable(void);\r
+extern void IntMasterDisable(void);\r
+extern void IntRegister(unsigned long ulInterrupt, void (*pfnHandler)(void));\r
+extern void IntUnregister(unsigned long ulInterrupt);\r
+extern void IntPriorityGroupingSet(unsigned long ulBits);\r
+extern unsigned long IntPriorityGroupingGet(void);\r
+extern void IntPrioritySet(unsigned long ulInterrupt,\r
+ unsigned char ucPriority);\r
+extern long IntPriorityGet(unsigned long ulInterrupt);\r
+extern void IntEnable(unsigned long ulInterrupt);\r
+extern void IntDisable(unsigned long ulInterrupt);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __INTERRUPT_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// flash.h - Prototypes for the flash driver.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __FLASH_H__\r
+#define __FLASH_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to FlashProtectSet(), and returned by\r
+// FlashProtectGet().\r
+//\r
+//*****************************************************************************\r
+typedef enum\r
+{\r
+ FlashReadWrite, // Flash can be read and written\r
+ FlashReadOnly, // Flash can only be read\r
+ FlashExecuteOnly // Flash can only be executed\r
+}\r
+tFlashProtection;\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+extern unsigned long FlashUsecGet(void);\r
+extern void FlashUsecSet(unsigned long ulClocks);\r
+extern long FlashErase(unsigned long ulAddress);\r
+extern long FlashProgram(unsigned long *pulData, unsigned long ulAddress,\r
+ unsigned long ulCount);\r
+extern tFlashProtection FlashProtectGet(unsigned long ulAddress);\r
+extern long FlashProtectSet(unsigned long ulAddress,\r
+ tFlashProtection eProtect);\r
+extern long FlashProtectSave(void);\r
+extern long FlashUserGet(unsigned long *pulUser0, unsigned long *pulUser1);\r
+extern long FlashUserSet(unsigned long ulUser0, unsigned long ulUser1);\r
+extern long FlashUserSave(void);\r
+extern void FlashIntRegister(void (*pfnHandler)(void));\r
+extern void FlashIntUnregister(void);\r
+extern void FlashIntEnable(unsigned long ulIntFlags);\r
+extern void FlashIntDisable(unsigned long ulIntFlags);\r
+extern unsigned long FlashIntGetStatus(tBoolean bMasked);\r
+extern void FlashIntClear(unsigned long ulIntFlags);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __FLASH_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// timer.h - Prototypes for the timer module\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __TIMER_H__\r
+#define __TIMER_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to TimerConfigure as the ulConfig parameter.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_CFG_32_BIT_OS 0x00000001 // 32-bit one-shot timer\r
+#define TIMER_CFG_32_BIT_PER 0x00000002 // 32-bit periodic timer\r
+#define TIMER_CFG_32_RTC 0x01000000 // 32-bit RTC timer\r
+#define TIMER_CFG_16_BIT_PAIR 0x04000000 // Two 16-bit timers\r
+#define TIMER_CFG_A_ONE_SHOT 0x00000001 // Timer A one-shot timer\r
+#define TIMER_CFG_A_PERIODIC 0x00000002 // Timer A periodic timer\r
+#define TIMER_CFG_A_CAP_COUNT 0x00000003 // Timer A event counter\r
+#define TIMER_CFG_A_CAP_TIME 0x00000007 // Timer A event timer\r
+#define TIMER_CFG_A_PWM 0x0000000A // Timer A PWM output\r
+#define TIMER_CFG_B_ONE_SHOT 0x00000100 // Timer B one-shot timer\r
+#define TIMER_CFG_B_PERIODIC 0x00000200 // Timer B periodic timer\r
+#define TIMER_CFG_B_CAP_COUNT 0x00000300 // Timer B event counter\r
+#define TIMER_CFG_B_CAP_TIME 0x00000700 // Timer B event timer\r
+#define TIMER_CFG_B_PWM 0x00000A00 // Timer B PWM output\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to TimerIntEnable, TimerIntDisable, and\r
+// TimerIntClear as the ulIntFlags parameter, and returned from TimerIntStatus.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_CAPB_EVENT 0x00000400 // CaptureB event interrupt\r
+#define TIMER_CAPB_MATCH 0x00000200 // CaptureB match interrupt\r
+#define TIMER_TIMB_TIMEOUT 0x00000100 // TimerB time out interrupt\r
+#define TIMER_RTC_MATCH 0x00000008 // RTC interrupt mask\r
+#define TIMER_CAPA_EVENT 0x00000004 // CaptureA event interrupt\r
+#define TIMER_CAPA_MATCH 0x00000002 // CaptureA match interrupt\r
+#define TIMER_TIMA_TIMEOUT 0x00000001 // TimerA time out interrupt\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to TimerControlEvent as the ulEvent parameter.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_EVENT_POS_EDGE 0x00000000 // Count positive edges\r
+#define TIMER_EVENT_NEG_EDGE 0x00000404 // Count negative edges\r
+#define TIMER_EVENT_BOTH_EDGES 0x00000C0C // Count both edges\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to most of the timer APIs as the ulTimer\r
+// parameter.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_A 0x000000ff // Timer A\r
+#define TIMER_B 0x0000ff00 // Timer B\r
+#define TIMER_BOTH 0x0000ffff // Timer Both\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+extern void TimerEnable(unsigned long ulBase, unsigned long ulTimer);\r
+extern void TimerDisable(unsigned long ulBase, unsigned long ulTimer);\r
+extern void TimerConfigure(unsigned long ulBase, unsigned long ulConfig);\r
+extern void TimerControlLevel(unsigned long ulBase, unsigned long ulTimer,\r
+ tBoolean bInvert);\r
+extern void TimerControlTrigger(unsigned long ulBase, unsigned long ulTimer,\r
+ tBoolean bEnable);\r
+extern void TimerControlEvent(unsigned long ulBase, unsigned long ulTimer,\r
+ unsigned long ulEvent);\r
+extern void TimerControlStall(unsigned long ulBase, unsigned long ulTimer,\r
+ tBoolean bStall);\r
+extern void TimerRTCEnable(unsigned long ulBase);\r
+extern void TimerRTCDisable(unsigned long ulBase);\r
+extern void TimerPrescaleSet(unsigned long ulBase, unsigned long ulTimer,\r
+ unsigned long ulValue);\r
+extern unsigned long TimerPrescaleGet(unsigned long ulBase,\r
+ unsigned long ulTimer);\r
+extern void TimerPrescaleMatchSet(unsigned long ulBase, unsigned long ulTimer,\r
+ unsigned long ulValue);\r
+extern unsigned long TimerPrescaleMatchGet(unsigned long ulBase,\r
+ unsigned long ulTimer);\r
+extern void TimerLoadSet(unsigned long ulBase, unsigned long ulTimer,\r
+ unsigned long ulValue);\r
+extern unsigned long TimerLoadGet(unsigned long ulBase, unsigned long ulTimer);\r
+extern unsigned long TimerValueGet(unsigned long ulBase,\r
+ unsigned long ulTimer);\r
+extern void TimerMatchSet(unsigned long ulBase, unsigned long ulTimer,\r
+ unsigned long ulValue);\r
+extern unsigned long TimerMatchGet(unsigned long ulBase,\r
+ unsigned long ulTimer);\r
+extern void TimerIntRegister(unsigned long ulBase, unsigned long ulTimer,\r
+ void (*pfnHandler)(void));\r
+extern void TimerIntUnregister(unsigned long ulBase, unsigned long ulTimer);\r
+extern void TimerIntEnable(unsigned long ulBase, unsigned long ulIntFlags);\r
+extern void TimerIntDisable(unsigned long ulBase, unsigned long ulIntFlags);\r
+extern unsigned long TimerIntStatus(unsigned long ulBase, tBoolean bMasked);\r
+extern void TimerIntClear(unsigned long ulBase, unsigned long ulIntFlags);\r
+extern void TimerQuiesce(unsigned long ulBase);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __TIMER_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// osram128x64x4.c - Driver for the OSRAM 128x64x4 graphical OLED display.\r
+//\r
+// Copyright (c) 2006-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+//*****************************************************************************\r
+//\r
+//! \addtogroup ek_lm3sx965_api\r
+//! @{\r
+//\r
+//*****************************************************************************\r
+\r
+#include "hw_ssi.h"\r
+#include "hw_memmap.h"\r
+#include "hw_sysctl.h"\r
+#include "hw_types.h"\r
+#include "debug.h"\r
+#include "gpio.h"\r
+#include "ssi.h"\r
+#include "sysctl.h"\r
+#include "osram128x64x4.h"\r
+\r
+//*****************************************************************************\r
+//\r
+// Flag to indicate if SSI port is enabled for OSRAM usage.\r
+//\r
+//*****************************************************************************\r
+static volatile tBoolean g_bSSIEnabled = false;\r
+\r
+//*****************************************************************************\r
+//\r
+// Define the OSRAM 128x64x4 Remap Setting(s). This will be used in\r
+// several places in the code to switch between vertical and horizontal\r
+// address incrementing.\r
+//\r
+// The Remap Command (0xA0) takes one 8-bit parameter. The parameter is\r
+// defined as follows.\r
+//\r
+// Bit 7: Reserved\r
+// Bit 6: Disable(0)/Enable(1) COM Split Odd Even\r
+// When enabled, the COM signals are split Odd on one side, even on\r
+// the other. Otherwise, they are split 0-39 on one side, 40-79 on\r
+// the other.\r
+// Bit 5: Reserved\r
+// Bit 4: Disable(0)/Enable(1) COM Remap\r
+// When Enabled, ROW 0-79 map to COM 79-0 (i.e. reverse row order)\r
+// Bit 3: Reserved\r
+// Bit 2: Horizontal(0)/Vertical(1) Address Increment\r
+// When set, data RAM address will increment along the column rather\r
+// than along the row.\r
+// Bit 1: Disable(0)/Enable(1) Nibble Remap\r
+// When enabled, the upper and lower nibbles in the DATA bus for access\r
+// to the data RAM are swapped.\r
+// Bit 0: Disable(0)/Enable(1) Column Address Remap\r
+// When enabled, DATA RAM columns 0-63 are remapped to Segment Columns\r
+// 127-0.\r
+//\r
+//*****************************************************************************\r
+#define OSRAM_INIT_REMAP 0x52\r
+#define OSRAM_INIT_OFFSET 0x4C\r
+static const unsigned char g_pucOSRAM128x64x4VerticalInc[] = { 0xA0, 0x56 };\r
+static const unsigned char g_pucOSRAM128x64x4HorizontalInc[] = { 0xA0, 0x52 };\r
+\r
+//*****************************************************************************\r
+//\r
+// A 5x7 font (in a 6x8 cell, where the sixth column is omitted from this\r
+// table) for displaying text on the OLED display. The data is organized as\r
+// bytes from the left column to the right column, with each byte containing\r
+// the top row in the LSB and the bottom row in the MSB.\r
+//\r
+// Note: This is the same font data that is used in the EK-LM3S811\r
+// osram96x16x1 driver. The single bit-per-pixel is expaned in the StringDraw\r
+// function to the appropriate four bit-per-pixel gray scale format.\r
+//\r
+//*****************************************************************************\r
+static const unsigned char g_pucFont[96][5] =\r
+{\r
+ { 0x00, 0x00, 0x00, 0x00, 0x00 }, // " "\r
+ { 0x00, 0x00, 0x4f, 0x00, 0x00 }, // !\r
+ { 0x00, 0x07, 0x00, 0x07, 0x00 }, // "\r
+ { 0x14, 0x7f, 0x14, 0x7f, 0x14 }, // #\r
+ { 0x24, 0x2a, 0x7f, 0x2a, 0x12 }, // $\r
+ { 0x23, 0x13, 0x08, 0x64, 0x62 }, // %\r
+ { 0x36, 0x49, 0x55, 0x22, 0x50 }, // &\r
+ { 0x00, 0x05, 0x03, 0x00, 0x00 }, // '\r
+ { 0x00, 0x1c, 0x22, 0x41, 0x00 }, // (\r
+ { 0x00, 0x41, 0x22, 0x1c, 0x00 }, // )\r
+ { 0x14, 0x08, 0x3e, 0x08, 0x14 }, // *\r
+ { 0x08, 0x08, 0x3e, 0x08, 0x08 }, // +\r
+ { 0x00, 0x50, 0x30, 0x00, 0x00 }, // ,\r
+ { 0x08, 0x08, 0x08, 0x08, 0x08 }, // -\r
+ { 0x00, 0x60, 0x60, 0x00, 0x00 }, // .\r
+ { 0x20, 0x10, 0x08, 0x04, 0x02 }, // /\r
+ { 0x3e, 0x51, 0x49, 0x45, 0x3e }, // 0\r
+ { 0x00, 0x42, 0x7f, 0x40, 0x00 }, // 1\r
+ { 0x42, 0x61, 0x51, 0x49, 0x46 }, // 2\r
+ { 0x21, 0x41, 0x45, 0x4b, 0x31 }, // 3\r
+ { 0x18, 0x14, 0x12, 0x7f, 0x10 }, // 4\r
+ { 0x27, 0x45, 0x45, 0x45, 0x39 }, // 5\r
+ { 0x3c, 0x4a, 0x49, 0x49, 0x30 }, // 6\r
+ { 0x01, 0x71, 0x09, 0x05, 0x03 }, // 7\r
+ { 0x36, 0x49, 0x49, 0x49, 0x36 }, // 8\r
+ { 0x06, 0x49, 0x49, 0x29, 0x1e }, // 9\r
+ { 0x00, 0x36, 0x36, 0x00, 0x00 }, // :\r
+ { 0x00, 0x56, 0x36, 0x00, 0x00 }, // ;\r
+ { 0x08, 0x14, 0x22, 0x41, 0x00 }, // <\r
+ { 0x14, 0x14, 0x14, 0x14, 0x14 }, // =\r
+ { 0x00, 0x41, 0x22, 0x14, 0x08 }, // >\r
+ { 0x02, 0x01, 0x51, 0x09, 0x06 }, // ?\r
+ { 0x32, 0x49, 0x79, 0x41, 0x3e }, // @\r
+ { 0x7e, 0x11, 0x11, 0x11, 0x7e }, // A\r
+ { 0x7f, 0x49, 0x49, 0x49, 0x36 }, // B\r
+ { 0x3e, 0x41, 0x41, 0x41, 0x22 }, // C\r
+ { 0x7f, 0x41, 0x41, 0x22, 0x1c }, // D\r
+ { 0x7f, 0x49, 0x49, 0x49, 0x41 }, // E\r
+ { 0x7f, 0x09, 0x09, 0x09, 0x01 }, // F\r
+ { 0x3e, 0x41, 0x49, 0x49, 0x7a }, // G\r
+ { 0x7f, 0x08, 0x08, 0x08, 0x7f }, // H\r
+ { 0x00, 0x41, 0x7f, 0x41, 0x00 }, // I\r
+ { 0x20, 0x40, 0x41, 0x3f, 0x01 }, // J\r
+ { 0x7f, 0x08, 0x14, 0x22, 0x41 }, // K\r
+ { 0x7f, 0x40, 0x40, 0x40, 0x40 }, // L\r
+ { 0x7f, 0x02, 0x0c, 0x02, 0x7f }, // M\r
+ { 0x7f, 0x04, 0x08, 0x10, 0x7f }, // N\r
+ { 0x3e, 0x41, 0x41, 0x41, 0x3e }, // O\r
+ { 0x7f, 0x09, 0x09, 0x09, 0x06 }, // P\r
+ { 0x3e, 0x41, 0x51, 0x21, 0x5e }, // Q\r
+ { 0x7f, 0x09, 0x19, 0x29, 0x46 }, // R\r
+ { 0x46, 0x49, 0x49, 0x49, 0x31 }, // S\r
+ { 0x01, 0x01, 0x7f, 0x01, 0x01 }, // T\r
+ { 0x3f, 0x40, 0x40, 0x40, 0x3f }, // U\r
+ { 0x1f, 0x20, 0x40, 0x20, 0x1f }, // V\r
+ { 0x3f, 0x40, 0x38, 0x40, 0x3f }, // W\r
+ { 0x63, 0x14, 0x08, 0x14, 0x63 }, // X\r
+ { 0x07, 0x08, 0x70, 0x08, 0x07 }, // Y\r
+ { 0x61, 0x51, 0x49, 0x45, 0x43 }, // Z\r
+ { 0x00, 0x7f, 0x41, 0x41, 0x00 }, // [\r
+ { 0x02, 0x04, 0x08, 0x10, 0x20 }, // "\"\r
+ { 0x00, 0x41, 0x41, 0x7f, 0x00 }, // ]\r
+ { 0x04, 0x02, 0x01, 0x02, 0x04 }, // ^\r
+ { 0x40, 0x40, 0x40, 0x40, 0x40 }, // _\r
+ { 0x00, 0x01, 0x02, 0x04, 0x00 }, // `\r
+ { 0x20, 0x54, 0x54, 0x54, 0x78 }, // a\r
+ { 0x7f, 0x48, 0x44, 0x44, 0x38 }, // b\r
+ { 0x38, 0x44, 0x44, 0x44, 0x20 }, // c\r
+ { 0x38, 0x44, 0x44, 0x48, 0x7f }, // d\r
+ { 0x38, 0x54, 0x54, 0x54, 0x18 }, // e\r
+ { 0x08, 0x7e, 0x09, 0x01, 0x02 }, // f\r
+ { 0x0c, 0x52, 0x52, 0x52, 0x3e }, // g\r
+ { 0x7f, 0x08, 0x04, 0x04, 0x78 }, // h\r
+ { 0x00, 0x44, 0x7d, 0x40, 0x00 }, // i\r
+ { 0x20, 0x40, 0x44, 0x3d, 0x00 }, // j\r
+ { 0x7f, 0x10, 0x28, 0x44, 0x00 }, // k\r
+ { 0x00, 0x41, 0x7f, 0x40, 0x00 }, // l\r
+ { 0x7c, 0x04, 0x18, 0x04, 0x78 }, // m\r
+ { 0x7c, 0x08, 0x04, 0x04, 0x78 }, // n\r
+ { 0x38, 0x44, 0x44, 0x44, 0x38 }, // o\r
+ { 0x7c, 0x14, 0x14, 0x14, 0x08 }, // p\r
+ { 0x08, 0x14, 0x14, 0x18, 0x7c }, // q\r
+ { 0x7c, 0x08, 0x04, 0x04, 0x08 }, // r\r
+ { 0x48, 0x54, 0x54, 0x54, 0x20 }, // s\r
+ { 0x04, 0x3f, 0x44, 0x40, 0x20 }, // t\r
+ { 0x3c, 0x40, 0x40, 0x20, 0x7c }, // u\r
+ { 0x1c, 0x20, 0x40, 0x20, 0x1c }, // v\r
+ { 0x3c, 0x40, 0x30, 0x40, 0x3c }, // w\r
+ { 0x44, 0x28, 0x10, 0x28, 0x44 }, // x\r
+ { 0x0c, 0x50, 0x50, 0x50, 0x3c }, // y\r
+ { 0x44, 0x64, 0x54, 0x4c, 0x44 }, // z\r
+ { 0x00, 0x08, 0x36, 0x41, 0x00 }, // {\r
+ { 0x00, 0x00, 0x7f, 0x00, 0x00 }, // |\r
+ { 0x00, 0x41, 0x36, 0x08, 0x00 }, // }\r
+ { 0x02, 0x01, 0x02, 0x04, 0x02 }, // ~\r
+ { 0x02, 0x01, 0x02, 0x04, 0x02 }, // ~\r
+};\r
+\r
+//*****************************************************************************\r
+//\r
+// The sequence of commands used to initialize the SSD0303 controller. Each\r
+// command is described as follows: there is a byte specifying the number of\r
+// bytes in the command sequence, followed by that many bytes of command data.\r
+// Note: This initialization sequence is derived from OSRAM App Note AN018.\r
+//\r
+//*****************************************************************************\r
+static const unsigned char g_pucOSRAM128x64x4Init[] =\r
+{\r
+ //\r
+ // Column Address\r
+ //\r
+ 4, 0x15, 0, 63, 0xe3,\r
+\r
+ //\r
+ // Row Address\r
+ //\r
+ 4, 0x75, 0, 63, 0xe3,\r
+\r
+ //\r
+ // Contrast Control\r
+ //\r
+ 3, 0x81, 50, 0xe3,\r
+\r
+ //\r
+ // Half Current Range\r
+ //\r
+ 2, 0x85, 0xe3,\r
+\r
+ //\r
+ // Display Re-map\r
+ //\r
+ 3, 0xA0, OSRAM_INIT_REMAP, 0xe3,\r
+\r
+ //\r
+ // Display Start Line\r
+ //\r
+ 3, 0xA1, 0, 0xe3,\r
+\r
+ //\r
+ // Display Offset\r
+ //\r
+ 3, 0xA2, OSRAM_INIT_OFFSET, 0xe3,\r
+\r
+ //\r
+ // Display Mode Normal\r
+ //\r
+ 2, 0xA4, 0xe3,\r
+\r
+ //\r
+ // Multiplex Ratio\r
+ //\r
+ 3, 0xA8, 63, 0xe3,\r
+\r
+ //\r
+ // Phase Length\r
+ //\r
+ 3, 0xB1, 0x22, 0xe3,\r
+\r
+ //\r
+ // Row Period\r
+ //\r
+ 3, 0xB2, 70, 0xe3,\r
+\r
+ //\r
+ // Display Clock Divide\r
+ //\r
+ 3, 0xB3, 0xF1, 0xe3,\r
+\r
+ //\r
+ // VSL\r
+ //\r
+ 3, 0xBF, 0x0D, 0xe3,\r
+\r
+ //\r
+ // VCOMH\r
+ //\r
+ 3, 0xBE, 0x02, 0xe3,\r
+\r
+ //\r
+ // VP\r
+ //\r
+ 3, 0xBC, 0x10, 0xe3,\r
+\r
+ //\r
+ // Gamma\r
+ //\r
+ 10, 0xB8, 0x01, 0x11, 0x22, 0x32, 0x43, 0x54, 0x65, 0x76, 0xe3,\r
+\r
+ //\r
+ // Set DC-DC\r
+ 3, 0xAD, 0x03, 0xe3,\r
+\r
+ //\r
+ // Display ON/OFF\r
+ //\r
+ 2, 0xAF, 0xe3,\r
+};\r
+\r
+//*****************************************************************************\r
+//\r
+//! \internal\r
+//!\r
+//! Write a sequence of command bytes to the SSD0323 controller.\r
+//!\r
+//! The data is written in a polled fashion; this function will not return\r
+//! until the entire byte sequence has been written to the controller.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+static void\r
+OSRAMWriteCommand(const unsigned char *pucBuffer, unsigned long ulCount)\r
+{\r
+ unsigned long ulTemp;\r
+\r
+ //\r
+ // Return iff SSI port is not enabled for OSRAM.\r
+ //\r
+ if(!g_bSSIEnabled)\r
+ {\r
+ return;\r
+ }\r
+\r
+ //\r
+ // Clear the command/control bit to enable command mode.\r
+ //\r
+ GPIOPinWrite(GPIO_PORTC_BASE, GPIO_PIN_7, 0);\r
+\r
+ //\r
+ // Loop while there are more bytes left to be transferred.\r
+ //\r
+ while(ulCount != 0)\r
+ {\r
+ //\r
+ // Write the next byte to the controller.\r
+ //\r
+ SSIDataPut(SSI0_BASE, *pucBuffer++);\r
+\r
+ //\r
+ // Dummy read to drain the fifo and time the GPIO signal.\r
+ //\r
+ SSIDataGet(SSI0_BASE, &ulTemp);\r
+\r
+ //\r
+ // Decrement the BYTE counter.\r
+ //\r
+ ulCount--;\r
+ }\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! \internal\r
+//!\r
+//! Write a sequence of data bytes to the SSD0323 controller.\r
+//!\r
+//! The data is written in a polled fashion; this function will not return\r
+//! until the entire byte sequence has been written to the controller.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+static void\r
+OSRAMWriteData(const unsigned char *pucBuffer, unsigned long ulCount)\r
+{\r
+ unsigned long ulTemp;\r
+\r
+ //\r
+ // Return iff SSI port is not enabled for OSRAM.\r
+ //\r
+ if(!g_bSSIEnabled)\r
+ {\r
+ return;\r
+ }\r
+\r
+ //\r
+ // Set the command/control bit to enable data mode.\r
+ //\r
+ GPIOPinWrite(GPIO_PORTC_BASE, GPIO_PIN_7, GPIO_PIN_7);\r
+\r
+ //\r
+ // Loop while there are more bytes left to be transferred.\r
+ //\r
+ while(ulCount != 0)\r
+ {\r
+ //\r
+ // Write the next byte to the controller.\r
+ //\r
+ SSIDataPut(SSI0_BASE, *pucBuffer++);\r
+\r
+ //\r
+ // Dummy read to drain the fifo and time the GPIO signal.\r
+ //\r
+ SSIDataGet(SSI0_BASE, &ulTemp);\r
+\r
+ //\r
+ // Decrement the BYTE counter.\r
+ //\r
+ ulCount--;\r
+ }\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! Clears the OLED display.\r
+//!\r
+//! This function will clear the display RAM. All pixels in the display will\r
+//! be turned off.\r
+//!\r
+//! This function is contained in <tt>osram128x64x4.c</tt>, with\r
+//! <tt>osram128x64x4.h</tt> containing the API definition for use by\r
+//! applications.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+void\r
+OSRAM128x64x4Clear(void)\r
+{\r
+ static const unsigned char pucCommand1[] = { 0x15, 0, 63 };\r
+ static const unsigned char pucCommand2[] = { 0x75, 0, 79 };\r
+ unsigned long ulRow, ulColumn;\r
+ static unsigned char pucZeroBuffer[8] = { 0, 0, 0, 0, 0, 0, 0, 0};\r
+\r
+ //\r
+ // Set the window to fill the entire display.\r
+ //\r
+ OSRAMWriteCommand(pucCommand1, sizeof(pucCommand1));\r
+ OSRAMWriteCommand(pucCommand2, sizeof(pucCommand2));\r
+ OSRAMWriteCommand(g_pucOSRAM128x64x4VerticalInc,\r
+ sizeof(g_pucOSRAM128x64x4VerticalInc));\r
+\r
+ //\r
+ // In vertical address increment mode, loop through each column, filling\r
+ // each row with 0.\r
+ //\r
+ for(ulColumn = 0; ulColumn < (128/2); ulColumn++)\r
+ {\r
+ //\r
+ // 8 rows (bytes) per row of text.\r
+ //\r
+ for(ulRow = 0; ulRow < 80; ulRow += 8)\r
+ {\r
+ OSRAMWriteData(pucZeroBuffer, sizeof(pucZeroBuffer));\r
+ }\r
+ }\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! Displays a string on the OLED display.\r
+//!\r
+//! \param pcStr is a pointer to the string to display.\r
+//! \param ulX is the horizontal position to display the string, specified in\r
+//! columns from the left edge of the display.\r
+//! \param ulY is the vertical position to display the string, specified in\r
+//! rows from the top edge of the display.\r
+//! \param ucLevel is the 4-bit grey scale value to be used for displayed text.\r
+//!\r
+//! This function will draw a string on the display. Only the ASCII characters\r
+//! between 32 (space) and 126 (tilde) are supported; other characters will\r
+//! result in random data being draw on the display (based on whatever appears\r
+//! before/after the font in memory). The font is mono-spaced, so characters\r
+//! such as "i" and "l" have more white space around them than characters such\r
+//! as "m" or "w".\r
+//!\r
+//! If the drawing of the string reaches the right edge of the display, no more\r
+//! characters will be drawn. Therefore, special care is not required to avoid\r
+//! supplying a string that is "too long" to display.\r
+//!\r
+//! This function is contained in <tt>osram128x64x4.c</tt>, with\r
+//! <tt>osram128x64x4.h</tt> containing the API definition for use by\r
+//! applications.\r
+//!\r
+//! \note Because the OLED display packs 2 pixels of data in a single byte, the\r
+//! parameter \e ulX must be an even column number (e.g. 0, 2, 4, etc).\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+void\r
+OSRAM128x64x4StringDraw(const char *pcStr, unsigned long ulX,\r
+ unsigned long ulY, unsigned char ucLevel)\r
+{\r
+ static unsigned char pucBuffer[8];\r
+ unsigned long ulIdx1, ulIdx2;\r
+ unsigned char ucTemp;\r
+\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT(ulX < 128);\r
+ ASSERT((ulX & 1) == 0);\r
+ ASSERT(ulY < 64);\r
+ ASSERT(ucLevel < 16);\r
+\r
+ //\r
+ // Setup a window starting at the specified column and row, ending\r
+ // at the right edge of the display and 8 rows down (single character row).\r
+ //\r
+ pucBuffer[0] = 0x15;\r
+ pucBuffer[1] = ulX / 2;\r
+ pucBuffer[2] = 63;\r
+ OSRAMWriteCommand(pucBuffer, 3);\r
+ pucBuffer[0] = 0x75;\r
+ pucBuffer[1] = ulY;\r
+ pucBuffer[2] = ulY + 7;\r
+ OSRAMWriteCommand(pucBuffer, 3);\r
+ OSRAMWriteCommand(g_pucOSRAM128x64x4VerticalInc,\r
+ sizeof(g_pucOSRAM128x64x4VerticalInc));\r
+\r
+ //\r
+ // Loop while there are more characters in the string.\r
+ //\r
+ while(*pcStr != 0)\r
+ {\r
+ //\r
+ // Get a working copy of the current character and convert to an\r
+ // index into the character bit-map array.\r
+ //\r
+ ucTemp = *pcStr;\r
+ ucTemp &= 0x7F;\r
+ if(ucTemp < ' ')\r
+ {\r
+ ucTemp = ' ';\r
+ }\r
+ else\r
+ {\r
+ ucTemp -= ' ';\r
+ }\r
+\r
+ //\r
+ // Build and display the character buffer.\r
+ //\r
+ for(ulIdx1 = 0; ulIdx1 < 3; ulIdx1++)\r
+ {\r
+ //\r
+ // Convert two columns of 1-bit font data into a single data\r
+ // byte column of 4-bit font data.\r
+ //\r
+ for(ulIdx2 = 0; ulIdx2 < 8; ulIdx2++)\r
+ {\r
+ pucBuffer[ulIdx2] = 0;\r
+ if(g_pucFont[ucTemp][ulIdx1*2] & (1 << ulIdx2))\r
+ {\r
+ pucBuffer[ulIdx2] = ((ucLevel << 4) & 0xf0);\r
+ }\r
+ if((ulIdx1 < 2) &&\r
+ (g_pucFont[ucTemp][ulIdx1*2+1] & (1 << ulIdx2)))\r
+ {\r
+ pucBuffer[ulIdx2] |= ((ucLevel << 0) & 0x0f);\r
+ }\r
+ }\r
+\r
+ //\r
+ // If there is room, dump the single data byte column to the\r
+ // display. Otherwise, bail out.\r
+ //\r
+ if(ulX < 126)\r
+ {\r
+ OSRAMWriteData(pucBuffer, 8);\r
+ ulX += 2;\r
+ }\r
+ else\r
+ {\r
+ return;\r
+ }\r
+ }\r
+\r
+ //\r
+ // Advance to the next character.\r
+ //\r
+ pcStr++;\r
+ }\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! Displays an image on the OLED display.\r
+//!\r
+//! \param pucImage is a pointer to the image data.\r
+//! \param ulX is the horizontal position to display this image, specified in\r
+//! columns from the left edge of the display.\r
+//! \param ulY is the vertical position to display this image, specified in\r
+//! rows from the top of the display.\r
+//! \param ulWidth is the width of the image, specified in columns.\r
+//! \param ulHeight is the height of the image, specified in rows.\r
+//!\r
+//! This function will display a bitmap graphic on the display. Because of the\r
+//! format of the display RAM, the starting column (/e ulX) and the number of\r
+//! columns (/e ulWidth) must be an integer multiple of two.\r
+//!\r
+//! The image data is organized with the first row of image data appearing left\r
+//! to right, followed immediately by the second row of image data. Each byte\r
+//! contains the data for two columns in the current row, with the leftmost\r
+//! column being contained in bits 7:4 and the rightmost column being contained\r
+//! in bits 3:0.\r
+//!\r
+//! For example, an image six columns wide and seven scan lines tall would\r
+//! be arranged as follows (showing how the twenty one bytes of the image would\r
+//! appear on the display):\r
+//!\r
+//! \verbatim\r
+//! +-------------------+-------------------+-------------------+\r
+//! | Byte 0 | Byte 1 | Byte 2 |\r
+//! +---------+---------+---------+---------+---------+---------+\r
+//! | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 |\r
+//! +---------+---------+---------+---------+---------+---------+\r
+//! | Byte 3 | Byte 4 | Byte 5 |\r
+//! +---------+---------+---------+---------+---------+---------+\r
+//! | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 |\r
+//! +---------+---------+---------+---------+---------+---------+\r
+//! | Byte 6 | Byte 7 | Byte 8 |\r
+//! +---------+---------+---------+---------+---------+---------+\r
+//! | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 |\r
+//! +---------+---------+---------+---------+---------+---------+\r
+//! | Byte 9 | Byte 10 | Byte 11 |\r
+//! +---------+---------+---------+---------+---------+---------+\r
+//! | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 |\r
+//! +---------+---------+---------+---------+---------+---------+\r
+//! | Byte 12 | Byte 13 | Byte 14 |\r
+//! +---------+---------+---------+--3------+---------+---------+\r
+//! | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 |\r
+//! +---------+---------+---------+---------+---------+---------+\r
+//! | Byte 15 | Byte 16 | Byte 17 |\r
+//! +---------+---------+---------+---------+---------+---------+\r
+//! | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 |\r
+//! +---------+---------+---------+---------+---------+---------+\r
+//! | Byte 18 | Byte 19 | Byte 20 |\r
+//! +---------+---------+---------+---------+---------+---------+\r
+//! | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 |\r
+//! +---------+---------+---------+---------+---------+---------+\r
+//! \endverbatim\r
+//!\r
+//! This function is contained in <tt>osram128x64x4.c</tt>, with\r
+//! <tt>osram128x64x4.h</tt> containing the API definition for use by`\r
+//! applications.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+void\r
+OSRAM128x64x4ImageDraw(const unsigned char *pucImage, unsigned long ulX,\r
+ unsigned long ulY, unsigned long ulWidth,\r
+ unsigned long ulHeight)\r
+{\r
+ static unsigned char pucBuffer[8];\r
+\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT(ulX < 128);\r
+ ASSERT((ulX & 1) == 0);\r
+ ASSERT(ulY < 64);\r
+ ASSERT((ulX + ulWidth) <= 128);\r
+ ASSERT((ulY + ulHeight) <= 64);\r
+ ASSERT((ulWidth & 1) == 0);\r
+\r
+ //\r
+ // Setup a window starting at the specified column and row, and ending\r
+ // at the column + width and row+height.\r
+ //\r
+ pucBuffer[0] = 0x15;\r
+ pucBuffer[1] = ulX / 2;\r
+ pucBuffer[2] = (ulX + ulWidth - 2) / 2;\r
+ OSRAMWriteCommand(pucBuffer, 3);\r
+ pucBuffer[0] = 0x75;\r
+ pucBuffer[1] = ulY;\r
+ pucBuffer[2] = ulY + ulHeight - 1;\r
+ OSRAMWriteCommand(pucBuffer, 3);\r
+ OSRAMWriteCommand(g_pucOSRAM128x64x4HorizontalInc,\r
+ sizeof(g_pucOSRAM128x64x4HorizontalInc));\r
+\r
+ //\r
+ // Loop while there are more rows to display.\r
+ //\r
+ while(ulHeight--)\r
+ {\r
+ //\r
+ // Write this row of image data.\r
+ //\r
+ OSRAMWriteData(pucImage, (ulWidth / 2));\r
+\r
+ //\r
+ // Advance to the next row of the image.\r
+ //\r
+ pucImage += (ulWidth / 2);\r
+ }\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! Enable the SSI component of the OLED display driver.\r
+//!\r
+//! \param ulFrequency specifies the SSI Clock Frequency to be used.\r
+//!\r
+//! This function initializes the SSI interface to the OLED display.\r
+//!\r
+//! This function is contained in <tt>osram128x64x4.c</tt>, with\r
+//! <tt>osram128x64x4.h</tt> containing the API definition for use by\r
+//! applications.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+void\r
+OSRAM128x64x4Enable(unsigned long ulFrequency)\r
+{\r
+ unsigned long ulTemp;\r
+\r
+ //\r
+ // Disable the SSI port.\r
+ //\r
+ SSIDisable(SSI0_BASE);\r
+\r
+ //\r
+ // Configure the SSI0 port for master mode.\r
+ //\r
+ SSIConfig(SSI0_BASE, SSI_FRF_MOTO_MODE_2, SSI_MODE_MASTER, ulFrequency, 8);\r
+\r
+ //\r
+ // (Re)Enable SSI control of the FSS pin.\r
+ //\r
+ GPIOPinTypeSSI(GPIO_PORTA_BASE, GPIO_PIN_3);\r
+ GPIOPadConfigSet(GPIO_PORTA_BASE, GPIO_PIN_3, GPIO_STRENGTH_8MA,\r
+ GPIO_PIN_TYPE_STD_WPU);\r
+\r
+ //\r
+ // Enable the SSI port.\r
+ //\r
+ SSIEnable(SSI0_BASE);\r
+\r
+ //\r
+ // Drain the receive fifo.\r
+ //\r
+ while(SSIDataNonBlockingGet(SSI0_BASE, &ulTemp) != 0)\r
+ {\r
+ }\r
+\r
+ //\r
+ // Indicate that the OSRAM driver can use the SSI Port.\r
+ //\r
+ g_bSSIEnabled = true;\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! Enable the SSI component of the OLED display driver.\r
+//!\r
+//! \param ulFrequency specifies the SSI Clock Frequency to be used.\r
+//!\r
+//! This function initializes the SSI interface to the OLED display.\r
+//!\r
+//! This function is contained in <tt>osram128x64x4.c</tt>, with\r
+//! <tt>osram128x64x4.h</tt> containing the API definition for use by\r
+//! applications.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+void\r
+OSRAM128x64x4Disable(void)\r
+{\r
+ unsigned long ulTemp;\r
+\r
+ //\r
+ // Indicate that the OSRAM driver can no longer use the SSI Port.\r
+ //\r
+ g_bSSIEnabled = false;\r
+\r
+ //\r
+ // Drain the receive fifo.\r
+ //\r
+ while(SSIDataNonBlockingGet(SSI0_BASE, &ulTemp) != 0)\r
+ {\r
+ }\r
+\r
+ //\r
+ // Disable the SSI port.\r
+ //\r
+ SSIDisable(SSI0_BASE);\r
+\r
+ //\r
+ // Disable SSI control of the FSS pin.\r
+ //\r
+ GPIODirModeSet(GPIO_PORTA_BASE, GPIO_PIN_3, GPIO_DIR_MODE_OUT);\r
+ GPIOPadConfigSet(GPIO_PORTA_BASE, GPIO_PIN_3, GPIO_STRENGTH_8MA,\r
+ GPIO_PIN_TYPE_STD_WPU);\r
+ GPIOPinWrite(GPIO_PORTA_BASE, GPIO_PIN_3, GPIO_PIN_3);\r
+\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! Initialize the OLED display.\r
+//!\r
+//! \param ulFrequency specifies the SSI Clock Frequency to be used.\r
+//!\r
+//! This function initializes the SSI interface to the OLED display and\r
+//! configures the SSD0323 controller on the panel.\r
+//!\r
+//! This function is contained in <tt>osram128x64x4.c</tt>, with\r
+//! <tt>osram128x64x4.h</tt> containing the API definition for use by\r
+//! applications.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+void\r
+OSRAM128x64x4Init(unsigned long ulFrequency)\r
+{\r
+ unsigned long ulIdx;\r
+\r
+ //\r
+ // Enable the SSI0 and GPIO port blocks as they are needed by this driver.\r
+ //\r
+ SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI0);\r
+ SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA);\r
+ SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOC);\r
+\r
+ //\r
+ // Configure the SSI0CLK and SSIOTX pins for SSI operation.\r
+ //\r
+ GPIOPinTypeSSI(GPIO_PORTA_BASE, GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_5);\r
+ GPIOPadConfigSet(GPIO_PORTA_BASE, GPIO_PIN_2, GPIO_STRENGTH_8MA,\r
+ GPIO_PIN_TYPE_STD_WPU);\r
+ GPIOPadConfigSet(GPIO_PORTA_BASE, GPIO_PIN_3, GPIO_STRENGTH_8MA,\r
+ GPIO_PIN_TYPE_STD_WPU);\r
+ GPIOPadConfigSet(GPIO_PORTA_BASE, GPIO_PIN_5, GPIO_STRENGTH_8MA,\r
+ GPIO_PIN_TYPE_STD_WPU);\r
+\r
+ //\r
+ // Configure the PC7 pin as a D/Cn signal for OLED device.\r
+ //\r
+ GPIODirModeSet(GPIO_PORTC_BASE, GPIO_PIN_7, GPIO_DIR_MODE_OUT);\r
+ GPIOPadConfigSet(GPIO_PORTC_BASE, GPIO_PIN_7, GPIO_STRENGTH_8MA,\r
+ GPIO_PIN_TYPE_STD);\r
+ GPIOPinWrite(GPIO_PORTC_BASE, GPIO_PIN_7, GPIO_PIN_7);\r
+\r
+ //\r
+ // Configure and enable the SSI0 port for master mode.\r
+ //\r
+ OSRAM128x64x4Enable(ulFrequency);\r
+\r
+ //\r
+ // Clear the frame buffer.\r
+ //\r
+ OSRAM128x64x4Clear();\r
+\r
+ //\r
+ // Initialize the SSD0323 controller. Loop through the initialization\r
+ // sequence array, sending each command "string" to the controller.\r
+ //\r
+ for(ulIdx = 0; ulIdx < sizeof(g_pucOSRAM128x64x4Init);\r
+ ulIdx += g_pucOSRAM128x64x4Init[ulIdx] + 1)\r
+ {\r
+ //\r
+ // Send this command.\r
+ //\r
+ OSRAMWriteCommand(g_pucOSRAM128x64x4Init + ulIdx + 1,\r
+ g_pucOSRAM128x64x4Init[ulIdx] - 1);\r
+ }\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! Turns on the OLED display.\r
+//!\r
+//! This function will turn on the OLED display, causing it to display the\r
+//! contents of its internal frame buffer.\r
+//!\r
+//! This function is contained in <tt>osram128x64x4.c</tt>, with\r
+//! <tt>osram128x64x4.h</tt> containing the API definition for use by\r
+//! applications.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+void\r
+OSRAM128x64x4DisplayOn(void)\r
+{\r
+ unsigned long ulIdx;\r
+\r
+ //\r
+ // Initialize the SSD0323 controller. Loop through the initialization\r
+ // sequence array, sending each command "string" to the controller.\r
+ //\r
+ for(ulIdx = 0; ulIdx < sizeof(g_pucOSRAM128x64x4Init);\r
+ ulIdx += g_pucOSRAM128x64x4Init[ulIdx] + 1)\r
+ {\r
+ //\r
+ // Send this command.\r
+ //\r
+ OSRAMWriteCommand(g_pucOSRAM128x64x4Init + ulIdx + 1,\r
+ g_pucOSRAM128x64x4Init[ulIdx] - 1);\r
+ }\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! Turns off the OLED display.\r
+//!\r
+//! This function will turn off the OLED display. This will stop the scanning\r
+//! of the panel and turn off the on-chip DC-DC converter, preventing damage to\r
+//! the panel due to burn-in (it has similar characters to a CRT in this\r
+//! respect).\r
+//!\r
+//! This function is contained in <tt>osram128x64x4.c</tt>, with\r
+//! <tt>osram128x64x4.h</tt> containing the API definition for use by\r
+//! applications.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+void\r
+OSRAM128x64x4DisplayOff(void)\r
+{\r
+ static const unsigned char pucCommand1[] =\r
+ {\r
+ 0xAE, 0xAD, 0x02\r
+ };\r
+\r
+ //\r
+ // Turn off the DC-DC converter and the display.\r
+ //\r
+ OSRAMWriteCommand(pucCommand1, sizeof(pucCommand1));\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+// Close the Doxygen group.\r
+//! @}\r
+//\r
+//*****************************************************************************\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// osram128x64x4.h - Prototypes for the driver for the OSRAM 128x64x4 graphical\r
+// OLED display.\r
+//\r
+// Copyright (c) 2006-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __OSRAM128X64X4_H__\r
+#define __OSRAM128X64X4_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the driver APIs.\r
+//\r
+//*****************************************************************************\r
+extern void OSRAM128x64x4Clear(void);\r
+extern void OSRAM128x64x4StringDraw(const char *pcStr,\r
+ unsigned long ulX,\r
+ unsigned long ulY,\r
+ unsigned char ucLevel);\r
+extern void OSRAM128x64x4ImageDraw(const unsigned char *pucImage,\r
+ unsigned long ulX,\r
+ unsigned long ulY,\r
+ unsigned long ulWidth,\r
+ unsigned long ulHeight);\r
+extern void OSRAM128x64x4Init(unsigned long ulFrequency);\r
+extern void OSRAM128x64x4Enable(unsigned long ulFrequency);\r
+extern void OSRAM128x64x4Disable(void);\r
+extern void OSRAM128x64x4DisplayOn(void);\r
+extern void OSRAM128x64x4DisplayOff(void);\r
+\r
+//*****************************************************************************\r
+//\r
+// The following macro(s) map old names for the OSRAM functions to the new\r
+// names. In new code, the new names should be used in favor of the old names.\r
+//\r
+//*****************************************************************************\r
+#ifndef DEPRECATED\r
+#define OSRAM128x64x1InitSSI OSRAM128x64x4Enable\r
+#endif\r
+\r
+#endif // __OSRAM128X64X4_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// pwm.h - API function protoypes for Pulse Width Modulation (PWM) ports\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __PWM_H__\r
+#define __PWM_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// The following defines are passed to PWMGenConfigure() as the ulConfig\r
+// parameter and specify the configuration of the PWM generator.\r
+//\r
+//*****************************************************************************\r
+#define PWM_GEN_MODE_DOWN 0x00000000 // Down count mode\r
+#define PWM_GEN_MODE_UP_DOWN 0x00000002 // Up/Down count mode\r
+#define PWM_GEN_MODE_SYNC 0x00000038 // Synchronous updates\r
+#define PWM_GEN_MODE_NO_SYNC 0x00000000 // Immediate updates\r
+#define PWM_GEN_MODE_DBG_RUN 0x00000004 // Continue running in debug mode\r
+#define PWM_GEN_MODE_DBG_STOP 0x00000000 // Stop running in debug mode\r
+\r
+//*****************************************************************************\r
+//\r
+// Defines for enabling, disabling, and clearing PWM generator interrupts and\r
+// triggers.\r
+//\r
+//*****************************************************************************\r
+#define PWM_INT_CNT_ZERO 0x00000001 // Int if COUNT = 0\r
+#define PWM_INT_CNT_LOAD 0x00000002 // Int if COUNT = LOAD\r
+#define PWM_INT_CNT_AU 0x00000004 // Int if COUNT = CMPA U\r
+#define PWM_INT_CNT_AD 0x00000008 // Int if COUNT = CMPA D\r
+#define PWM_INT_CNT_BU 0x00000010 // Int if COUNT = CMPA U\r
+#define PWM_INT_CNT_BD 0x00000020 // Int if COUNT = CMPA D\r
+#define PWM_TR_CNT_ZERO 0x00000100 // Trig if COUNT = 0\r
+#define PWM_TR_CNT_LOAD 0x00000200 // Trig if COUNT = LOAD\r
+#define PWM_TR_CNT_AU 0x00000400 // Trig if COUNT = CMPA U\r
+#define PWM_TR_CNT_AD 0x00000800 // Trig if COUNT = CMPA D\r
+#define PWM_TR_CNT_BU 0x00001000 // Trig if COUNT = CMPA U\r
+#define PWM_TR_CNT_BD 0x00002000 // Trig if COUNT = CMPA D\r
+\r
+//*****************************************************************************\r
+//\r
+// Defines for enabling, disabling, and clearing PWM interrupts.\r
+//\r
+//*****************************************************************************\r
+#define PWM_INT_GEN_0 0x00000001 // Generator 0 interrupt\r
+#define PWM_INT_GEN_1 0x00000002 // Generator 1 interrupt\r
+#define PWM_INT_GEN_2 0x00000004 // Generator 2 interrupt\r
+#define PWM_INT_FAULT 0x00010000 // Fault interrupt\r
+\r
+//*****************************************************************************\r
+//\r
+// Defines to identify the generators within a module.\r
+//\r
+//*****************************************************************************\r
+#define PWM_GEN_0 0x00000040 // Offset address of Gen0\r
+#define PWM_GEN_1 0x00000080 // Offset address of Gen1\r
+#define PWM_GEN_2 0x000000C0 // Offset address of Gen2\r
+\r
+#define PWM_GEN_0_BIT 0x00000001 // Bit-wise ID for Gen0\r
+#define PWM_GEN_1_BIT 0x00000002 // Bit-wise ID for Gen1\r
+#define PWM_GEN_2_BIT 0x00000004 // Bit-wise ID for Gen2\r
+\r
+//*****************************************************************************\r
+//\r
+// Defines to identify the outputs within a module.\r
+//\r
+//*****************************************************************************\r
+#define PWM_OUT_0 0x00000040 // Encoded offset address of PWM0\r
+#define PWM_OUT_1 0x00000041 // Encoded offset address of PWM1\r
+#define PWM_OUT_2 0x00000082 // Encoded offset address of PWM2\r
+#define PWM_OUT_3 0x00000083 // Encoded offset address of PWM3\r
+#define PWM_OUT_4 0x000000C4 // Encoded offset address of PWM4\r
+#define PWM_OUT_5 0x000000C5 // Encoded offset address of PWM5\r
+\r
+#define PWM_OUT_0_BIT 0x00000001 // Bit-wise ID for PWM0\r
+#define PWM_OUT_1_BIT 0x00000002 // Bit-wise ID for PWM1\r
+#define PWM_OUT_2_BIT 0x00000004 // Bit-wise ID for PWM2\r
+#define PWM_OUT_3_BIT 0x00000008 // Bit-wise ID for PWM3\r
+#define PWM_OUT_4_BIT 0x00000010 // Bit-wise ID for PWM4\r
+#define PWM_OUT_5_BIT 0x00000020 // Bit-wise ID for PWM5\r
+\r
+//*****************************************************************************\r
+//\r
+// API Function prototypes\r
+//\r
+//*****************************************************************************\r
+extern void PWMGenConfigure(unsigned long ulBase, unsigned long ulGen,\r
+ unsigned long ulConfig);\r
+extern void PWMGenPeriodSet(unsigned long ulBase, unsigned long ulGen,\r
+ unsigned long ulPeriod);\r
+extern unsigned long PWMGenPeriodGet(unsigned long ulBase,\r
+ unsigned long ulGen);\r
+extern void PWMGenEnable(unsigned long ulBase, unsigned long ulGen);\r
+extern void PWMGenDisable(unsigned long ulBase, unsigned long ulGen);\r
+extern void PWMPulseWidthSet(unsigned long ulBase, unsigned long ulPWMOut,\r
+ unsigned long ulWidth);\r
+extern unsigned long PWMPulseWidthGet(unsigned long ulBase,\r
+ unsigned long ulPWMOut);\r
+extern void PWMDeadBandEnable(unsigned long ulBase, unsigned long ulGen,\r
+ unsigned short usRise, unsigned short usFall);\r
+extern void PWMDeadBandDisable(unsigned long ulBase, unsigned long ulGen);\r
+extern void PWMSyncUpdate(unsigned long ulBase, unsigned long ulGenBits);\r
+extern void PWMSyncTimeBase(unsigned long ulBase, unsigned long ulGenBits);\r
+extern void PWMOutputState(unsigned long ulBase, unsigned long ulPWMOutBits,\r
+ tBoolean bEnable);\r
+extern void PWMOutputInvert(unsigned long ulBase, unsigned long ulPWMOutBits,\r
+ tBoolean bInvert);\r
+extern void PWMOutputFault(unsigned long ulBase, unsigned long ulPWMOutBits,\r
+ tBoolean bFaultKill);\r
+extern void PWMGenIntRegister(unsigned long ulBase, unsigned long ulGen,\r
+ void (*pfnIntHandler)(void));\r
+extern void PWMGenIntUnregister(unsigned long ulBase, unsigned long ulGen);\r
+extern void PWMFaultIntRegister(unsigned long ulBase,\r
+ void (*pfnIntHandler)(void));\r
+extern void PWMFaultIntUnregister(unsigned long ulBase);\r
+extern void PWMGenIntTrigEnable(unsigned long ulBase, unsigned long ulGen,\r
+ unsigned long ulIntTrig);\r
+extern void PWMGenIntTrigDisable(unsigned long ulBase, unsigned long ulGen,\r
+ unsigned long ulIntTrig);\r
+extern unsigned long PWMGenIntStatus(unsigned long ulBase, unsigned long ulGen,\r
+ tBoolean bMasked);\r
+extern void PWMGenIntClear(unsigned long ulBase, unsigned long ulGen,\r
+ unsigned long ulInts);\r
+extern void PWMIntEnable(unsigned long ulBase, unsigned long ulGenFault);\r
+extern void PWMIntDisable(unsigned long ulBase, unsigned long ulGenFault);\r
+extern void PWMFaultIntClear(unsigned long ulBase);\r
+extern unsigned long PWMIntStatus(unsigned long ulBase, tBoolean bMasked);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __PWM_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// qei.h - Prototypes for the Quadrature Encoder Driver.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __QEI_H__\r
+#define __QEI_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to QEIConfigure as the ulConfig paramater.\r
+//\r
+//*****************************************************************************\r
+#define QEI_CONFIG_CAPTURE_A 0x00000000 // Count on ChA edges only\r
+#define QEI_CONFIG_CAPTURE_A_B 0x00000008 // Count on ChA and ChB edges\r
+#define QEI_CONFIG_NO_RESET 0x00000000 // Do not reset on index pulse\r
+#define QEI_CONFIG_RESET_IDX 0x00000010 // Reset position on index pulse\r
+#define QEI_CONFIG_QUADRATURE 0x00000000 // ChA and ChB are quadrature\r
+#define QEI_CONFIG_CLOCK_DIR 0x00000004 // ChA and ChB are clock and dir\r
+#define QEI_CONFIG_NO_SWAP 0x00000000 // Do not swap ChA and ChB\r
+#define QEI_CONFIG_SWAP 0x00000002 // Swap ChA and ChB\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to QEIVelocityConfigure as the ulPreDiv parameter.\r
+//\r
+//*****************************************************************************\r
+#define QEI_VELDIV_1 0x00000000 // Predivide by 1\r
+#define QEI_VELDIV_2 0x00000040 // Predivide by 2\r
+#define QEI_VELDIV_4 0x00000080 // Predivide by 4\r
+#define QEI_VELDIV_8 0x000000C0 // Predivide by 8\r
+#define QEI_VELDIV_16 0x00000100 // Predivide by 16\r
+#define QEI_VELDIV_32 0x00000140 // Predivide by 32\r
+#define QEI_VELDIV_64 0x00000180 // Predivide by 64\r
+#define QEI_VELDIV_128 0x000001C0 // Predivide by 128\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to QEIEnableInts, QEIDisableInts, and QEIClearInts\r
+// as the ulIntFlags parameter, and returned by QEIGetIntStatus.\r
+//\r
+//*****************************************************************************\r
+#define QEI_INTERROR 0x00000008 // Phase error detected\r
+#define QEI_INTDIR 0x00000004 // Direction change\r
+#define QEI_INTTIMER 0x00000002 // Velocity timer expired\r
+#define QEI_INTINDEX 0x00000001 // Index pulse detected\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+extern void QEIEnable(unsigned long ulBase);\r
+extern void QEIDisable(unsigned long ulBase);\r
+extern void QEIConfigure(unsigned long ulBase, unsigned long ulConfig,\r
+ unsigned long ulMaxPosition);\r
+extern unsigned long QEIPositionGet(unsigned long ulBase);\r
+extern void QEIPositionSet(unsigned long ulBase, unsigned long ulPosition);\r
+extern long QEIDirectionGet(unsigned long ulBase);\r
+extern tBoolean QEIErrorGet(unsigned long ulBase);\r
+extern void QEIVelocityEnable(unsigned long ulBase);\r
+extern void QEIVelocityDisable(unsigned long ulBase);\r
+extern void QEIVelocityConfigure(unsigned long ulBase, unsigned long ulPreDiv,\r
+ unsigned long ulPeriod);\r
+extern unsigned long QEIVelocityGet(unsigned long ulBase);\r
+extern void QEIIntRegister(unsigned long ulBase, void (*pfnHandler)(void));\r
+extern void QEIIntUnregister(unsigned long ulBase);\r
+extern void QEIIntEnable(unsigned long ulBase, unsigned long ulIntFlags);\r
+extern void QEIIntDisable(unsigned long ulBase, unsigned long ulIntFlags);\r
+extern unsigned long QEIIntStatus(unsigned long ulBase, tBoolean bMasked);\r
+extern void QEIIntClear(unsigned long ulBase, unsigned long ulIntFlags);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __QEI_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// ssi.h - Prototypes for the Synchronous Serial Interface Driver.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __SSI_H__\r
+#define __SSI_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to SSIIntEnable, SSIIntDisable, and SSIIntClear\r
+// as the ulIntFlags parameter, and returned by SSIIntStatus.\r
+//\r
+//*****************************************************************************\r
+#define SSI_TXFF 0x00000008 // TX FIFO half empty or less\r
+#define SSI_RXFF 0x00000004 // RX FIFO half full or less\r
+#define SSI_RXTO 0x00000002 // RX timeout\r
+#define SSI_RXOR 0x00000001 // RX overrun\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to SSIConfig.\r
+//\r
+//*****************************************************************************\r
+#define SSI_FRF_MOTO_MODE_0 0x00000000 // Moto fmt, polarity 0, phase 0\r
+#define SSI_FRF_MOTO_MODE_1 0x00000002 // Moto fmt, polarity 0, phase 1\r
+#define SSI_FRF_MOTO_MODE_2 0x00000001 // Moto fmt, polarity 1, phase 0\r
+#define SSI_FRF_MOTO_MODE_3 0x00000003 // Moto fmt, polarity 1, phase 1\r
+#define SSI_FRF_TI 0x00000010 // TI frame format\r
+#define SSI_FRF_NMW 0x00000020 // National MicroWire frame format\r
+\r
+#define SSI_MODE_MASTER 0x00000000 // SSI master\r
+#define SSI_MODE_SLAVE 0x00000001 // SSI slave\r
+#define SSI_MODE_SLAVE_OD 0x00000002 // SSI slave with output disabled\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+extern void SSIConfig(unsigned long ulBase, unsigned long ulProtocol,\r
+ unsigned long ulMode, unsigned long ulBitRate,\r
+ unsigned long ulDataWidth);\r
+extern void SSIDataGet(unsigned long ulBase, unsigned long *pulData);\r
+extern long SSIDataNonBlockingGet(unsigned long ulBase,\r
+ unsigned long *pulData);\r
+extern void SSIDataPut(unsigned long ulBase, unsigned long ulData);\r
+extern long SSIDataNonBlockingPut(unsigned long ulBase, unsigned long ulData);\r
+extern void SSIDisable(unsigned long ulBase);\r
+extern void SSIEnable(unsigned long ulBase);\r
+extern void SSIIntClear(unsigned long ulBase, unsigned long ulIntFlags);\r
+extern void SSIIntDisable(unsigned long ulBase, unsigned long ulIntFlags);\r
+extern void SSIIntEnable(unsigned long ulBase, unsigned long ulIntFlags);\r
+extern void SSIIntRegister(unsigned long ulBase, void(*pfnHandler)(void));\r
+extern unsigned long SSIIntStatus(unsigned long ulBase, tBoolean bMasked);\r
+extern void SSIIntUnregister(unsigned long ulBase);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __SSI_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// sysctl.h - Prototypes for the system control driver.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __SYSCTL_H__\r
+#define __SYSCTL_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the\r
+// SysCtlPeripheralPresent(), SysCtlPeripheralEnable(),\r
+// SysCtlPeripheralDisable(), and SysCtlPeripheralReset() APIs as the\r
+// ulPeripheral parameter. The peripherals in the fourth group (upper nibble\r
+// is 3) can only be used with the SysCtlPeripheralPresent() API.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_PERIPH_PWM 0x00100010 // PWM\r
+#define SYSCTL_PERIPH_ADC 0x00100001 // ADC\r
+#define SYSCTL_PERIPH_HIBERNATE 0x00000040 // Hibernation module\r
+#define SYSCTL_PERIPH_WDOG 0x00000008 // Watchdog\r
+#define SYSCTL_PERIPH_CAN0 0x00100100 // CAN 0\r
+#define SYSCTL_PERIPH_CAN1 0x00100200 // CAN 1\r
+#define SYSCTL_PERIPH_UART0 0x10000001 // UART 0\r
+#define SYSCTL_PERIPH_UART1 0x10000002 // UART 1\r
+#define SYSCTL_PERIPH_UART2 0x10000004 // UART 2\r
+#define SYSCTL_PERIPH_SSI 0x10000010 // SSI\r
+#define SYSCTL_PERIPH_SSI0 0x10000010 // SSI 0\r
+#define SYSCTL_PERIPH_SSI1 0x10000020 // SSI 1\r
+#define SYSCTL_PERIPH_QEI 0x10000100 // QEI\r
+#define SYSCTL_PERIPH_QEI0 0x10000100 // QEI 0\r
+#define SYSCTL_PERIPH_QEI1 0x10000200 // QEI 1\r
+#define SYSCTL_PERIPH_I2C 0x10001000 // I2C\r
+#define SYSCTL_PERIPH_I2C0 0x10001000 // I2C 0\r
+#define SYSCTL_PERIPH_I2C1 0x10004000 // I2C 1\r
+#define SYSCTL_PERIPH_TIMER0 0x10100001 // Timer 0\r
+#define SYSCTL_PERIPH_TIMER1 0x10100002 // Timer 1\r
+#define SYSCTL_PERIPH_TIMER2 0x10100004 // Timer 2\r
+#define SYSCTL_PERIPH_TIMER3 0x10100008 // Timer 3\r
+#define SYSCTL_PERIPH_COMP0 0x10100100 // Analog comparator 0\r
+#define SYSCTL_PERIPH_COMP1 0x10100200 // Analog comparator 1\r
+#define SYSCTL_PERIPH_COMP2 0x10100400 // Analog comparator 2\r
+#define SYSCTL_PERIPH_GPIOA 0x20000001 // GPIO A\r
+#define SYSCTL_PERIPH_GPIOB 0x20000002 // GPIO B\r
+#define SYSCTL_PERIPH_GPIOC 0x20000004 // GPIO C\r
+#define SYSCTL_PERIPH_GPIOD 0x20000008 // GPIO D\r
+#define SYSCTL_PERIPH_GPIOE 0x20000010 // GPIO E\r
+#define SYSCTL_PERIPH_GPIOF 0x20000020 // GPIO F\r
+#define SYSCTL_PERIPH_GPIOG 0x20000040 // GPIO G\r
+#define SYSCTL_PERIPH_GPIOH 0x20000080 // GPIO H\r
+#define SYSCTL_PERIPH_ETH 0x20105000 // ETH\r
+#define SYSCTL_PERIPH_MPU 0x30000080 // Cortex M3 MPU\r
+#define SYSCTL_PERIPH_TEMP 0x30000020 // Temperature sensor\r
+#define SYSCTL_PERIPH_PLL 0x30000010 // PLL\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the SysCtlPinPresent() API\r
+// as the ulPin parameter.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_PIN_PWM0 0x00000001 // PWM0 pin\r
+#define SYSCTL_PIN_PWM1 0x00000002 // PWM1 pin\r
+#define SYSCTL_PIN_PWM2 0x00000004 // PWM2 pin\r
+#define SYSCTL_PIN_PWM3 0x00000008 // PWM3 pin\r
+#define SYSCTL_PIN_PWM4 0x00000010 // PWM4 pin\r
+#define SYSCTL_PIN_PWM5 0x00000020 // PWM5 pin\r
+#define SYSCTL_PIN_C0MINUS 0x00000040 // C0- pin\r
+#define SYSCTL_PIN_C0PLUS 0x00000080 // C0+ pin\r
+#define SYSCTL_PIN_C0O 0x00000100 // C0o pin\r
+#define SYSCTL_PIN_C1MINUS 0x00000200 // C1- pin\r
+#define SYSCTL_PIN_C1PLUS 0x00000400 // C1+ pin\r
+#define SYSCTL_PIN_C1O 0x00000800 // C1o pin\r
+#define SYSCTL_PIN_C2MINUS 0x00001000 // C2- pin\r
+#define SYSCTL_PIN_C2PLUS 0x00002000 // C2+ pin\r
+#define SYSCTL_PIN_C2O 0x00004000 // C2o pin\r
+#define SYSCTL_PIN_MC_FAULT0 0x00008000 // MC0 Fault pin\r
+#define SYSCTL_PIN_ADC0 0x00010000 // ADC0 pin\r
+#define SYSCTL_PIN_ADC1 0x00020000 // ADC1 pin\r
+#define SYSCTL_PIN_ADC2 0x00040000 // ADC2 pin\r
+#define SYSCTL_PIN_ADC3 0x00080000 // ADC3 pin\r
+#define SYSCTL_PIN_ADC4 0x00100000 // ADC4 pin\r
+#define SYSCTL_PIN_ADC5 0x00200000 // ADC5 pin\r
+#define SYSCTL_PIN_ADC6 0x00400000 // ADC6 pin\r
+#define SYSCTL_PIN_ADC7 0x00800000 // ADC7 pin\r
+#define SYSCTL_PIN_CCP0 0x01000000 // CCP0 pin\r
+#define SYSCTL_PIN_CCP1 0x02000000 // CCP1 pin\r
+#define SYSCTL_PIN_CCP2 0x04000000 // CCP2 pin\r
+#define SYSCTL_PIN_CCP3 0x08000000 // CCP3 pin\r
+#define SYSCTL_PIN_CCP4 0x10000000 // CCP4 pin\r
+#define SYSCTL_PIN_CCP5 0x20000000 // CCP5 pin\r
+#define SYSCTL_PIN_32KHZ 0x80000000 // 32kHz pin\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the SysCtlLDOSet() API as\r
+// the ulVoltage value, or returned by the SysCtlLDOGet() API.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_LDO_2_25V 0x00000005 // LDO output of 2.25V\r
+#define SYSCTL_LDO_2_30V 0x00000004 // LDO output of 2.30V\r
+#define SYSCTL_LDO_2_35V 0x00000003 // LDO output of 2.35V\r
+#define SYSCTL_LDO_2_40V 0x00000002 // LDO output of 2.40V\r
+#define SYSCTL_LDO_2_45V 0x00000001 // LDO output of 2.45V\r
+#define SYSCTL_LDO_2_50V 0x00000000 // LDO output of 2.50V\r
+#define SYSCTL_LDO_2_55V 0x0000001f // LDO output of 2.55V\r
+#define SYSCTL_LDO_2_60V 0x0000001e // LDO output of 2.60V\r
+#define SYSCTL_LDO_2_65V 0x0000001d // LDO output of 2.65V\r
+#define SYSCTL_LDO_2_70V 0x0000001c // LDO output of 2.70V\r
+#define SYSCTL_LDO_2_75V 0x0000001b // LDO output of 2.75V\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the SysCtlLDOConfigSet() API.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_LDOCFG_ARST 0x00000001 // Allow LDO failure to reset\r
+#define SYSCTL_LDOCFG_NORST 0x00000000 // Do not reset on LDO failure\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the SysCtlIntEnable(),\r
+// SysCtlIntDisable(), and SysCtlIntClear() APIs, or returned in the bit mask\r
+// by the SysCtlIntStatus() API.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_INT_PLL_LOCK 0x00000040 // PLL lock interrupt\r
+#define SYSCTL_INT_CUR_LIMIT 0x00000020 // Current limit interrupt\r
+#define SYSCTL_INT_IOSC_FAIL 0x00000010 // Internal oscillator failure int\r
+#define SYSCTL_INT_MOSC_FAIL 0x00000008 // Main oscillator failure int\r
+#define SYSCTL_INT_POR 0x00000004 // Power on reset interrupt\r
+#define SYSCTL_INT_BOR 0x00000002 // Brown out interrupt\r
+#define SYSCTL_INT_PLL_FAIL 0x00000001 // PLL failure interrupt\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the SysCtlResetCauseClear()\r
+// API or returned by the SysCtlResetCauseGet() API.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_CAUSE_LDO 0x00000020 // LDO power not OK reset\r
+#define SYSCTL_CAUSE_SW 0x00000010 // Software reset\r
+#define SYSCTL_CAUSE_WDOG 0x00000008 // Watchdog reset\r
+#define SYSCTL_CAUSE_BOR 0x00000004 // Brown-out reset\r
+#define SYSCTL_CAUSE_POR 0x00000002 // Power on reset\r
+#define SYSCTL_CAUSE_EXT 0x00000001 // External reset\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the SysCtlBrownOutConfigSet()\r
+// API as the ulConfig parameter.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_BOR_RESET 0x00000002 // Reset instead of interrupting\r
+#define SYSCTL_BOR_RESAMPLE 0x00000001 // Resample BOR before asserting\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the SysCtlPWMClockSet() API\r
+// as the ulConfig parameter, and can be returned by the SysCtlPWMClockGet()\r
+// API.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_PWMDIV_1 0x00000000 // PWM clock is processor clock /1\r
+#define SYSCTL_PWMDIV_2 0x00100000 // PWM clock is processor clock /2\r
+#define SYSCTL_PWMDIV_4 0x00120000 // PWM clock is processor clock /4\r
+#define SYSCTL_PWMDIV_8 0x00140000 // PWM clock is processor clock /8\r
+#define SYSCTL_PWMDIV_16 0x00160000 // PWM clock is processor clock /16\r
+#define SYSCTL_PWMDIV_32 0x00180000 // PWM clock is processor clock /32\r
+#define SYSCTL_PWMDIV_64 0x001A0000 // PWM clock is processor clock /64\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the SysCtlADCSpeedSet() API\r
+// as the ulSpeed parameter, and can be returned by the SyCtlADCSpeedGet()\r
+// API.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_ADCSPEED_1MSPS 0x00000300 // 1,000,000 samples per second\r
+#define SYSCTL_ADCSPEED_500KSPS 0x00000200 // 500,000 samples per second\r
+#define SYSCTL_ADCSPEED_250KSPS 0x00000100 // 250,000 samples per second\r
+#define SYSCTL_ADCSPEED_125KSPS 0x00000000 // 125,000 samples per second\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the SysCtlClockSet() API as\r
+// the ulConfig parameter.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_SYSDIV_1 0x07800000 // Processor clock is osc/pll /1\r
+#define SYSCTL_SYSDIV_2 0x00C00000 // Processor clock is osc/pll /2\r
+#define SYSCTL_SYSDIV_3 0x01400000 // Processor clock is osc/pll /3\r
+#define SYSCTL_SYSDIV_4 0x01C00000 // Processor clock is osc/pll /4\r
+#define SYSCTL_SYSDIV_5 0x02400000 // Processor clock is osc/pll /5\r
+#define SYSCTL_SYSDIV_6 0x02C00000 // Processor clock is osc/pll /6\r
+#define SYSCTL_SYSDIV_7 0x03400000 // Processor clock is osc/pll /7\r
+#define SYSCTL_SYSDIV_8 0x03C00000 // Processor clock is osc/pll /8\r
+#define SYSCTL_SYSDIV_9 0x04400000 // Processor clock is osc/pll /9\r
+#define SYSCTL_SYSDIV_10 0x04C00000 // Processor clock is osc/pll /10\r
+#define SYSCTL_SYSDIV_11 0x05400000 // Processor clock is osc/pll /11\r
+#define SYSCTL_SYSDIV_12 0x05C00000 // Processor clock is osc/pll /12\r
+#define SYSCTL_SYSDIV_13 0x06400000 // Processor clock is osc/pll /13\r
+#define SYSCTL_SYSDIV_14 0x06C00000 // Processor clock is osc/pll /14\r
+#define SYSCTL_SYSDIV_15 0x07400000 // Processor clock is osc/pll /15\r
+#define SYSCTL_SYSDIV_16 0x07C00000 // Processor clock is osc/pll /16\r
+#define SYSCTL_USE_PLL 0x00000000 // System clock is the PLL clock\r
+#define SYSCTL_USE_OSC 0x00003800 // System clock is the osc clock\r
+#define SYSCTL_XTAL_3_57MHZ 0x00000100 // External crystal is 3.579545MHz\r
+#define SYSCTL_XTAL_3_68MHZ 0x00000140 // External crystal is 3.6864MHz\r
+#define SYSCTL_XTAL_4MHZ 0x00000180 // External crystal is 4MHz\r
+#define SYSCTL_XTAL_4_09MHZ 0x000001C0 // External crystal is 4.096MHz\r
+#define SYSCTL_XTAL_4_91MHZ 0x00000200 // External crystal is 4.9152MHz\r
+#define SYSCTL_XTAL_5MHZ 0x00000240 // External crystal is 5MHz\r
+#define SYSCTL_XTAL_5_12MHZ 0x00000280 // External crystal is 5.12MHz\r
+#define SYSCTL_XTAL_6MHZ 0x000002C0 // External crystal is 6MHz\r
+#define SYSCTL_XTAL_6_14MHZ 0x00000300 // External crystal is 6.144MHz\r
+#define SYSCTL_XTAL_7_37MHZ 0x00000340 // External crystal is 7.3728MHz\r
+#define SYSCTL_XTAL_8MHZ 0x00000380 // External crystal is 8MHz\r
+#define SYSCTL_XTAL_8_19MHZ 0x000003C0 // External crystal is 8.192MHz\r
+#define SYSCTL_OSC_MAIN 0x00000000 // Oscillator source is main osc\r
+#define SYSCTL_OSC_INT 0x00000010 // Oscillator source is int. osc\r
+#define SYSCTL_OSC_INT4 0x00000020 // Oscillator source is int. osc /4\r
+#define SYSCTL_INT_OSC_DIS 0x00000002 // Disable internal oscillator\r
+#define SYSCTL_MAIN_OSC_DIS 0x00000001 // Disable main oscillator\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+extern unsigned long SysCtlSRAMSizeGet(void);\r
+extern unsigned long SysCtlFlashSizeGet(void);\r
+extern tBoolean SysCtlPinPresent(unsigned long ulPin);\r
+extern tBoolean SysCtlPeripheralPresent(unsigned long ulPeripheral);\r
+extern void SysCtlPeripheralReset(unsigned long ulPeripheral);\r
+extern void SysCtlPeripheralEnable(unsigned long ulPeripheral);\r
+extern void SysCtlPeripheralDisable(unsigned long ulPeripheral);\r
+extern void SysCtlPeripheralSleepEnable(unsigned long ulPeripheral);\r
+extern void SysCtlPeripheralSleepDisable(unsigned long ulPeripheral);\r
+extern void SysCtlPeripheralDeepSleepEnable(unsigned long ulPeripheral);\r
+extern void SysCtlPeripheralDeepSleepDisable(unsigned long ulPeripheral);\r
+extern void SysCtlPeripheralClockGating(tBoolean bEnable);\r
+extern void SysCtlIntRegister(void (*pfnHandler)(void));\r
+extern void SysCtlIntUnregister(void);\r
+extern void SysCtlIntEnable(unsigned long ulInts);\r
+extern void SysCtlIntDisable(unsigned long ulInts);\r
+extern void SysCtlIntClear(unsigned long ulInts);\r
+extern unsigned long SysCtlIntStatus(tBoolean bMasked);\r
+extern void SysCtlLDOSet(unsigned long ulVoltage);\r
+extern unsigned long SysCtlLDOGet(void);\r
+extern void SysCtlLDOConfigSet(unsigned long ulConfig);\r
+extern void SysCtlReset(void);\r
+extern void SysCtlSleep(void);\r
+extern void SysCtlDeepSleep(void);\r
+extern unsigned long SysCtlResetCauseGet(void);\r
+extern void SysCtlResetCauseClear(unsigned long ulCauses);\r
+extern void SysCtlBrownOutConfigSet(unsigned long ulConfig,\r
+ unsigned long ulDelay);\r
+extern void SysCtlClockSet(unsigned long ulConfig);\r
+extern unsigned long SysCtlClockGet(void);\r
+extern void SysCtlPWMClockSet(unsigned long ulConfig);\r
+extern unsigned long SysCtlPWMClockGet(void);\r
+extern void SysCtlADCSpeedSet(unsigned long ulSpeed);\r
+extern unsigned long SysCtlADCSpeedGet(void);\r
+extern void SysCtlIOSCVerificationSet(tBoolean bEnable);\r
+extern void SysCtlMOSCVerificationSet(tBoolean bEnable);\r
+extern void SysCtlPLLVerificationSet(tBoolean bEnable);\r
+extern void SysCtlClkVerificationClear(void);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __SYSCTL_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// systick.h - Prototypes for the SysTick driver.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __SYSTICK_H__\r
+#define __SYSTICK_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+extern void SysTickEnable(void);\r
+extern void SysTickDisable(void);\r
+extern void SysTickIntRegister(void (*pfnHandler)(void));\r
+extern void SysTickIntUnregister(void);\r
+extern void SysTickIntEnable(void);\r
+extern void SysTickIntDisable(void);\r
+extern void SysTickPeriodSet(unsigned long ulPeriod);\r
+extern unsigned long SysTickPeriodGet(void);\r
+extern unsigned long SysTickValueGet(void);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __SYSTICK_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// uart.h - Defines and Macros for the UART.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __UART_H__\r
+#define __UART_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to UARTIntEnable, UARTIntDisable, and UARTIntClear\r
+// as the ulIntFlags parameter, and returned from UARTIntStatus.\r
+//\r
+//*****************************************************************************\r
+#define UART_INT_OE 0x400 // Overrun Error Interrupt Mask\r
+#define UART_INT_BE 0x200 // Break Error Interrupt Mask\r
+#define UART_INT_PE 0x100 // Parity Error Interrupt Mask\r
+#define UART_INT_FE 0x080 // Framing Error Interrupt Mask\r
+#define UART_INT_RT 0x040 // Receive Timeout Interrupt Mask\r
+#define UART_INT_TX 0x020 // Transmit Interrupt Mask\r
+#define UART_INT_RX 0x010 // Receive Interrupt Mask\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to UARTConfigSet as the ulConfig parameter and\r
+// returned by UARTConfigGet in the pulConfig parameter. Additionally, the\r
+// UART_CONFIG_PAR_* subset can be passed to UARTParityModeSet as the ulParity\r
+// parameter, and are returned by UARTParityModeGet.\r
+//\r
+//*****************************************************************************\r
+#define UART_CONFIG_WLEN_8 0x00000060 // 8 bit data\r
+#define UART_CONFIG_WLEN_7 0x00000040 // 7 bit data\r
+#define UART_CONFIG_WLEN_6 0x00000020 // 6 bit data\r
+#define UART_CONFIG_WLEN_5 0x00000000 // 5 bit data\r
+#define UART_CONFIG_STOP_ONE 0x00000000 // One stop bit\r
+#define UART_CONFIG_STOP_TWO 0x00000008 // Two stop bits\r
+#define UART_CONFIG_PAR_NONE 0x00000000 // No parity\r
+#define UART_CONFIG_PAR_EVEN 0x00000006 // Even parity\r
+#define UART_CONFIG_PAR_ODD 0x00000002 // Odd parity\r
+#define UART_CONFIG_PAR_ONE 0x00000086 // Parity bit is one\r
+#define UART_CONFIG_PAR_ZERO 0x00000082 // Parity bit is zero\r
+\r
+//*****************************************************************************\r
+//\r
+// API Function prototypes\r
+//\r
+//*****************************************************************************\r
+extern void UARTParityModeSet(unsigned long ulBase, unsigned long ulParity);\r
+extern unsigned long UARTParityModeGet(unsigned long ulBase);\r
+extern void UARTConfigSet(unsigned long ulBase, unsigned long ulBaud,\r
+ unsigned long ulConfig);\r
+extern void UARTConfigGet(unsigned long ulBase, unsigned long *pulBaud,\r
+ unsigned long *pulConfig);\r
+extern void UARTEnable(unsigned long ulBase);\r
+extern void UARTDisable(unsigned long ulBase);\r
+extern void UARTEnableSIR(unsigned long ulBase, tBoolean bLowPower);\r
+extern void UARTDisableSIR(unsigned long ulBase);\r
+extern tBoolean UARTCharsAvail(unsigned long ulBase);\r
+extern tBoolean UARTSpaceAvail(unsigned long ulBase);\r
+extern long UARTCharNonBlockingGet(unsigned long ulBase);\r
+extern long UARTCharGet(unsigned long ulBase);\r
+extern tBoolean UARTCharNonBlockingPut(unsigned long ulBase,\r
+ unsigned char ucData);\r
+extern void UARTCharPut(unsigned long ulBase, unsigned char ucData);\r
+extern void UARTBreakCtl(unsigned long ulBase, tBoolean bBreakState);\r
+extern void UARTIntRegister(unsigned long ulBase, void(*pfnHandler)(void));\r
+extern void UARTIntUnregister(unsigned long ulBase);\r
+extern void UARTIntEnable(unsigned long ulBase, unsigned long ulIntFlags);\r
+extern void UARTIntDisable(unsigned long ulBase, unsigned long ulIntFlags);\r
+extern unsigned long UARTIntStatus(unsigned long ulBase, tBoolean bMasked);\r
+extern void UARTIntClear(unsigned long ulBase, unsigned long ulIntFlags);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __UART_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// ustdlib.c - Simple standard library functions.\r
+//\r
+// Copyright (c) 2007 Luminary Micro, Inc. All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+//*****************************************************************************\r
+\r
+#include <stdarg.h>\r
+#include <string.h>\r
+#include "debug.h"\r
+\r
+//*****************************************************************************\r
+//\r
+//! \addtogroup utilities_api\r
+//! @{\r
+//\r
+//*****************************************************************************\r
+\r
+//*****************************************************************************\r
+//\r
+// A mapping from an integer between 0 and 15 to its ASCII character\r
+// equivalent.\r
+//\r
+//*****************************************************************************\r
+static const char * const g_pcHex = "0123456789abcdef";\r
+\r
+//*****************************************************************************\r
+//\r
+//! A simple sprintf function supporting \%c, \%d, \%s, \%u, \%x, and \%X.\r
+//!\r
+//! \param pcBuf is the buffer where the converted string is stored.\r
+//! \param pcString is the format string.\r
+//! \param ... are the optional arguments, which depend on the contents of the\r
+//! format string.\r
+//!\r
+//! This function is very similar to the C library <tt>sprintf()</tt> function.\r
+//! Only the following formatting characters are supported:\r
+//!\r
+//! - \%c to print a character\r
+//! - \%d to print a decimal value\r
+//! - \%s to print a string\r
+//! - \%u to print an unsigned decimal value\r
+//! - \%x to print a hexadecimal value using lower case letters\r
+//! - \%X to print a hexadecimal value using lower case letters (not upper case\r
+//! letters as would typically be used)\r
+//! - \%\% to print out a \% character\r
+//!\r
+//! For \%d, \%u, \%x, and \%X, an optional number may reside between the \%\r
+//! and the format character, which specifies the minimum number of characters\r
+//! to use for that value; if preceeded by a 0 then the extra characters will\r
+//! be filled with zeros instead of spaces. For example, ``\%8d'' will use\r
+//! eight characters to print the decimal value with spaces added to reach\r
+//! eight; ``\%08d'' will use eight characters as well but will add zeros\r
+//! instead of spaces.\r
+//!\r
+//! The type of the arguments after \b pcString must match the requirements of\r
+//! the format string. For example, if an integer was passed where a string\r
+//! was expected, an error of some kind will most likely occur.\r
+//!\r
+//! The caller must ensure that the buffer pcBuf is large enough to hold the\r
+//! entire converted string, including the null termination character.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+int\r
+uvsnprintf(char *pcBuf, unsigned long ulSize, const char *pcString,\r
+ va_list vaArgP)\r
+{\r
+ unsigned long ulIdx, ulValue, ulPos, ulCount, ulBase;\r
+ char *pcStr, cFill, *pcOriginalBuf = pcBuf;\r
+\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT(pcString != 0);\r
+ ASSERT(pcBuf != 0);\r
+ ASSERT(ulSize != 0);\r
+\r
+ //\r
+ // Adjust buffer size limit to allow one space for null termination.\r
+ //\r
+ if(ulSize)\r
+ {\r
+ ulSize--;\r
+ }\r
+\r
+ //\r
+ // Loop while there are more characters in the string, and\r
+ // there is more room in the destination buffer.\r
+ //\r
+ while(*pcString && ulSize)\r
+ {\r
+ //\r
+ // Find the first non-% character, or the end of the string.\r
+ //\r
+ for(ulIdx = 0; (pcString[ulIdx] != '%') && (pcString[ulIdx] != '\0');\r
+ ulIdx++)\r
+ {\r
+ }\r
+\r
+ //\r
+ // Limit the number of characters that can be copied to the\r
+ // space remaining in the buffer.\r
+ //\r
+ if(ulIdx > ulSize)\r
+ {\r
+ ulIdx = ulSize;\r
+ }\r
+\r
+ //\r
+ // Write this portion of the string and update the buffer pointer.\r
+ //\r
+ strncpy(pcBuf, pcString, ulIdx);\r
+ pcBuf += ulIdx;\r
+\r
+ //\r
+ // Update the size limit, and check to see if the buffer\r
+ // limit is reached.\r
+ //\r
+ ulSize -= ulIdx;\r
+ if(ulSize == 0)\r
+ {\r
+ break;\r
+ }\r
+\r
+ //\r
+ // Skip the portion of the string that was written.\r
+ //\r
+ pcString += ulIdx;\r
+\r
+ //\r
+ // See if the next character is a %.\r
+ //\r
+ if(*pcString == '%')\r
+ {\r
+ //\r
+ // Skip the %.\r
+ //\r
+ pcString++;\r
+\r
+ //\r
+ // Set the digit count to zero, and the fill character to space\r
+ // (i.e. to the defaults).\r
+ //\r
+ ulCount = 0;\r
+ cFill = ' ';\r
+\r
+ //\r
+ // It may be necessary to get back here to process more characters.\r
+ // Goto's aren't pretty, but effective. I feel extremely dirty for\r
+ // using not one but two of the beasts.\r
+ //\r
+again:\r
+\r
+ //\r
+ // Determine how to handle the next character.\r
+ //\r
+ switch(*pcString++)\r
+ {\r
+ //\r
+ // Handle the digit characters.\r
+ //\r
+ case '0':\r
+ case '1':\r
+ case '2':\r
+ case '3':\r
+ case '4':\r
+ case '5':\r
+ case '6':\r
+ case '7':\r
+ case '8':\r
+ case '9':\r
+ {\r
+ //\r
+ // If this is a zero, and it is the first digit, then the\r
+ // fill character is a zero instead of a space.\r
+ //\r
+ if((pcString[-1] == '0') && (ulCount == 0))\r
+ {\r
+ cFill = '0';\r
+ }\r
+\r
+ //\r
+ // Update the digit count.\r
+ //\r
+ ulCount *= 10;\r
+ ulCount += pcString[-1] - '0';\r
+\r
+ //\r
+ // Get the next character.\r
+ //\r
+ goto again;\r
+ }\r
+\r
+ //\r
+ // Handle the %c command.\r
+ //\r
+ case 'c':\r
+ {\r
+ //\r
+ // Get the value from the varargs.\r
+ //\r
+ ulValue = va_arg(vaArgP, unsigned long);\r
+\r
+ //\r
+ // Print out the character.\r
+ //\r
+ *pcBuf++ = (char)ulValue;\r
+\r
+ //\r
+ // Decrement the buffer limit.\r
+ //\r
+ ulSize--;\r
+\r
+ //\r
+ // This command has been handled.\r
+ //\r
+ break;\r
+ }\r
+\r
+ //\r
+ // Handle the %d command.\r
+ //\r
+ case 'd':\r
+ {\r
+ //\r
+ // Get the value from the varargs.\r
+ //\r
+ ulValue = va_arg(vaArgP, unsigned long);\r
+\r
+ //\r
+ // Reset the buffer position.\r
+ //\r
+ ulPos = 0;\r
+\r
+ //\r
+ // If the value is negative, make it positive and stick a\r
+ // minus sign in the beginning of the buffer.\r
+ //\r
+ if((long)ulValue < 0)\r
+ {\r
+ *pcBuf++ = '-';\r
+ ulPos++;\r
+ ulValue = -(long)ulValue;\r
+\r
+ //\r
+ // Decrement the buffer size limit and check\r
+ // if the limit is reached.\r
+ //\r
+ ulSize--;\r
+ if(ulSize == 0)\r
+ {\r
+ break;\r
+ }\r
+ }\r
+\r
+ //\r
+ // Set the base to 10.\r
+ //\r
+ ulBase = 10;\r
+\r
+ //\r
+ // Convert the value to ASCII.\r
+ //\r
+ goto convert;\r
+ }\r
+\r
+ //\r
+ // Handle the %s command.\r
+ //\r
+ case 's':\r
+ {\r
+ //\r
+ // Get the string pointer from the varargs.\r
+ //\r
+ pcStr = va_arg(vaArgP, char *);\r
+\r
+ //\r
+ // Determine the length of the string.\r
+ //\r
+ for(ulIdx = 0; pcStr[ulIdx] != '\0'; ulIdx++)\r
+ {\r
+ }\r
+\r
+ //\r
+ // Limit the number of characters that can be copied to the\r
+ // space remaining in the buffer.\r
+ //\r
+ if(ulIdx > ulSize)\r
+ {\r
+ ulIdx = ulSize;\r
+ }\r
+\r
+ //\r
+ // Write the string and update the buffer pointer.\r
+ //\r
+ strncpy(pcBuf, pcStr, ulIdx);\r
+ pcBuf += ulIdx;\r
+\r
+ //\r
+ // Decrement the buffer size limit.\r
+ //\r
+ ulSize -= ulIdx;\r
+\r
+ //\r
+ //\r
+ // This command has been handled.\r
+ //\r
+ break;\r
+ }\r
+\r
+ //\r
+ // Handle the %u command.\r
+ //\r
+ case 'u':\r
+ {\r
+ //\r
+ // Get the value from the varargs.\r
+ //\r
+ ulValue = va_arg(vaArgP, unsigned long);\r
+\r
+ //\r
+ // Reset the buffer position.\r
+ //\r
+ ulPos = 0;\r
+\r
+ //\r
+ // Set the base to 10.\r
+ //\r
+ ulBase = 10;\r
+\r
+ //\r
+ // Convert the value to ASCII.\r
+ //\r
+ goto convert;\r
+ }\r
+\r
+ //\r
+ // Handle the %x and %X commands. Note that they are treated\r
+ // identically; i.e. %X will use lower case letters for a-f\r
+ // instead of the upper case letters is should use.\r
+ //\r
+ case 'x':\r
+ case 'X':\r
+ {\r
+ //\r
+ // Get the value from the varargs.\r
+ //\r
+ ulValue = va_arg(vaArgP, unsigned long);\r
+\r
+ //\r
+ // Reset the buffer position.\r
+ //\r
+ ulPos = 0;\r
+\r
+ //\r
+ // Set the base to 16.\r
+ //\r
+ ulBase = 16;\r
+\r
+ //\r
+ // Determine the number of digits in the string version of\r
+ // the value.\r
+ //\r
+convert:\r
+ for(ulIdx = 1;\r
+ (((ulIdx * ulBase) <= ulValue) &&\r
+ (((ulIdx * ulBase) / ulBase) == ulIdx));\r
+ ulIdx *= ulBase, ulCount--)\r
+ {\r
+ }\r
+\r
+ //\r
+ // Provide additional padding at the beginning of the\r
+ // string conversion if needed.\r
+ //\r
+ if((ulCount > 1) && (ulCount < 16))\r
+ {\r
+ for(ulCount--; ulCount; ulCount--)\r
+ {\r
+ *pcBuf++ = cFill;\r
+ ulPos++;\r
+\r
+ //\r
+ // Decrement buffer size and check to see if\r
+ // buffer limit is reached.\r
+ //\r
+ ulSize--;\r
+ if(ulSize == 0)\r
+ {\r
+ break;\r
+ }\r
+ }\r
+ }\r
+\r
+ //\r
+ // Convert the value into a string.\r
+ //\r
+ for(; ulIdx; ulIdx /= ulBase)\r
+ {\r
+ *pcBuf++ = g_pcHex[(ulValue / ulIdx) % ulBase];\r
+ ulPos++;\r
+\r
+ //\r
+ // Decrement buffer size and check to see if\r
+ // buffer limit is reached.\r
+ //\r
+ ulSize--;\r
+ if(ulSize == 0)\r
+ {\r
+ break;\r
+ }\r
+ }\r
+\r
+ //\r
+ // This command has been handled.\r
+ //\r
+ break;\r
+ }\r
+\r
+ //\r
+ // Handle the %% command.\r
+ //\r
+ case '%':\r
+ {\r
+ //\r
+ // Simply write a single %.\r
+ //\r
+ *pcBuf++ = pcString[-1];\r
+ ulSize--;\r
+\r
+ //\r
+ // This command has been handled.\r
+ //\r
+ break;\r
+ }\r
+\r
+ //\r
+ // Handle all other commands.\r
+ //\r
+ default:\r
+ {\r
+ //\r
+ // Indicate an error.\r
+ //\r
+ if(ulSize > 5)\r
+ {\r
+ strncpy(pcBuf, "ERROR", 5);\r
+ pcBuf += 5;\r
+ ulSize -= 5;\r
+ }\r
+\r
+ //\r
+ // This command has been handled.\r
+ //\r
+ break;\r
+ }\r
+ }\r
+ }\r
+ }\r
+\r
+ //\r
+ // Null terminate the string in the buffer.\r
+ //\r
+ *pcBuf = 0;\r
+ return ( int ) pcBuf - ( int ) pcOriginalBuf;\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! A simple sprintf function supporting \%c, \%d, \%s, \%u, \%x, and \%X.\r
+//!\r
+//! \param pcBuf is the buffer where the converted string is stored.\r
+//! \param pcString is the format string.\r
+//! \param ... are the optional arguments, which depend on the contents of the\r
+//! format string.\r
+//!\r
+//! This function is very similar to the C library <tt>sprintf()</tt> function.\r
+//! Only the following formatting characters are supported:\r
+//!\r
+//! - \%c to print a character\r
+//! - \%d to print a decimal value\r
+//! - \%s to print a string\r
+//! - \%u to print an unsigned decimal value\r
+//! - \%x to print a hexadecimal value using lower case letters\r
+//! - \%X to print a hexadecimal value using lower case letters (not upper case\r
+//! letters as would typically be used)\r
+//! - \%\% to print out a \% character\r
+//!\r
+//! For \%d, \%u, \%x, and \%X, an optional number may reside between the \%\r
+//! and the format character, which specifies the minimum number of characters\r
+//! to use for that value; if preceeded by a 0 then the extra characters will\r
+//! be filled with zeros instead of spaces. For example, ``\%8d'' will use\r
+//! eight characters to print the decimal value with spaces added to reach\r
+//! eight; ``\%08d'' will use eight characters as well but will add zeros\r
+//! instead of spaces.\r
+//!\r
+//! The type of the arguments after \b pcString must match the requirements of\r
+//! the format string. For example, if an integer was passed where a string\r
+//! was expected, an error of some kind will most likely occur.\r
+//!\r
+//! The caller must ensure that the buffer pcBuf is large enough to hold the\r
+//! entire converted string, including the null termination character.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+void\r
+usprintf(char *pcBuf, const char *pcString, ...)\r
+{\r
+ va_list vaArgP;\r
+\r
+ //\r
+ // Start the varargs processing.\r
+ //\r
+ va_start(vaArgP, pcString);\r
+\r
+ //\r
+ // Call vsnprintf to perform the conversion. Use a\r
+ // large number for the buffer size.\r
+ //\r
+ uvsnprintf(pcBuf, 0xffff, pcString, vaArgP);\r
+\r
+ //\r
+ // End the varargs processing.\r
+ //\r
+ va_end(vaArgP);\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! A simple snprintf function supporting \%c, \%d, \%s, \%u, \%x, and \%X.\r
+//!\r
+//! \param pcBuf is the buffer where the converted string is stored.\r
+//! \param ulSize is the size of the buffer.\r
+//! \param pcString is the format string.\r
+//! \param ... are the optional arguments, which depend on the contents of the\r
+//! format string.\r
+//!\r
+//! This function is very similar to the C library <tt>sprintf()</tt> function.\r
+//! Only the following formatting characters are supported:\r
+//!\r
+//! - \%c to print a character\r
+//! - \%d to print a decimal value\r
+//! - \%s to print a string\r
+//! - \%u to print an unsigned decimal value\r
+//! - \%x to print a hexadecimal value using lower case letters\r
+//! - \%X to print a hexadecimal value using lower case letters (not upper case\r
+//! letters as would typically be used)\r
+//! - \%\% to print out a \% character\r
+//!\r
+//! For \%d, \%u, \%x, and \%X, an optional number may reside between the \%\r
+//! and the format character, which specifies the minimum number of characters\r
+//! to use for that value; if preceeded by a 0 then the extra characters will\r
+//! be filled with zeros instead of spaces. For example, ``\%8d'' will use\r
+//! eight characters to print the decimal value with spaces added to reach\r
+//! eight; ``\%08d'' will use eight characters as well but will add zeros\r
+//! instead of spaces.\r
+//!\r
+//! The type of the arguments after \b pcString must match the requirements of\r
+//! the format string. For example, if an integer was passed where a string\r
+//! was expected, an error of some kind will most likely occur.\r
+//!\r
+//! The function will copy at most \b ulSize - 1 characters into the\r
+//! buffer \b pcBuf. One space is reserved in the buffer for the null\r
+//! termination character.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+int\r
+usnprintf(char *pcBuf, unsigned long ulSize, const char *pcString, ...)\r
+{\r
+int iReturn;\r
+\r
+ va_list vaArgP;\r
+\r
+ //\r
+ // Start the varargs processing.\r
+ //\r
+ va_start(vaArgP, pcString);\r
+\r
+ //\r
+ // Call vsnprintf to perform the conversion.\r
+ //\r
+ iReturn = uvsnprintf(pcBuf, ulSize, pcString, vaArgP);\r
+\r
+ //\r
+ // End the varargs processing.\r
+ //\r
+ va_end(vaArgP);\r
+\r
+ return iReturn;\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+// Close the Doxygen group.\r
+//! @}\r
+//\r
+//*****************************************************************************\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// uartstdlib.h - Prototypes for simple standard library functions.\r
+//\r
+// Copyright (c) 2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __UARTSTDLIB_H__\r
+#define __UARTSTDLIB_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+extern void usprintf(char *, const char *pcString, ...);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __UARTSTDLIB_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// watchdog.h - Prototypes for the Watchdog Timer API\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __WATCHDOG_H__\r
+#define __WATCHDOG_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+extern tBoolean WatchdogRunning(unsigned long ulBase);\r
+extern void WatchdogEnable(unsigned long ulBase);\r
+extern void WatchdogResetEnable(unsigned long ulBase);\r
+extern void WatchdogResetDisable(unsigned long ulBase);\r
+extern void WatchdogLock(unsigned long ulBase);\r
+extern void WatchdogUnlock(unsigned long ulBase);\r
+extern tBoolean WatchdogLockState(unsigned long ulBase);\r
+extern void WatchdogReloadSet(unsigned long ulBase, unsigned long ulLoadVal);\r
+extern unsigned long WatchdogReloadGet(unsigned long ulBase);\r
+extern unsigned long WatchdogValueGet(unsigned long ulBase);\r
+extern void WatchdogIntRegister(unsigned long ulBase, void(*pfnHandler)(void));\r
+extern void WatchdogIntUnregister(unsigned long ulBase);\r
+extern void WatchdogIntEnable(unsigned long ulBase);\r
+extern unsigned long WatchdogIntStatus(unsigned long ulBase, tBoolean bMasked);\r
+extern void WatchdogIntClear(unsigned long ulBase);\r
+extern void WatchdogStallDisable(unsigned long ulBase);\r
+extern void WatchdogStallDisable(unsigned long ulBase);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __WATCHDOG_H__\r
--- /dev/null
+#******************************************************************************
+#
+# Makefile - Rules for building the driver library and examples.
+#
+# Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
+#
+# Software License Agreement
+#
+# Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+# exclusively on LMI's Stellaris Family of microcontroller products.
+#
+# The software is owned by LMI and/or its suppliers, and is protected under
+# applicable copyright laws. All rights are reserved. Any use in violation
+# of the foregoing restrictions may subject the user to criminal sanctions
+# under applicable laws, as well as to civil liability for the breach of the
+# terms and conditions of this license.
+#
+# THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+# OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+# MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+# LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+# CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+#
+#******************************************************************************
+
+include makedefs
+
+RTOS_SOURCE_DIR=../../Source
+DEMO_SOURCE_DIR=../Common/Minimal
+UIP_SOURCE_DIR=../Common/ethernet/uIP/uip-1.0/uip
+
+CFLAGS+=-I LuminaryDrivers -I . -I ${RTOS_SOURCE_DIR}/include -I ${RTOS_SOURCE_DIR}/portable/GCC/ARM_CM3 -I ${UIP_SOURCE_DIR} -I webserver -I ../Common/include -D GCC_ARMCM3_LM3S102 -D inline= -D PACK_STRUCT_END=__attribute\(\(packed\)\) -D ALIGN_STRUCT_END=__attribute\(\(aligned\(4\)\)\) -D sprintf=usprintf -D snprintf=usnprintf -D printf=uipprintf
+
+VPATH=${RTOS_SOURCE_DIR}:${RTOS_SOURCE_DIR}/portable/MemMang:${RTOS_SOURCE_DIR}/portable/GCC/ARM_CM3:${DEMO_SOURCE_DIR}:${UIP_SOURCE_DIR}:init:LuminaryDrivers:ParTest:webserver
+
+OBJS=${COMPILER}/main.o \
+ ${COMPILER}/list.o \
+ ${COMPILER}/queue.o \
+ ${COMPILER}/tasks.o \
+ ${COMPILER}/port.o \
+ ${COMPILER}/heap_2.o \
+ ${COMPILER}/BlockQ.o \
+ ${COMPILER}/PollQ.o \
+ ${COMPILER}/integer.o \
+ ${COMPILER}/semtest.o \
+ ${COMPILER}/osram128x64x4.o \
+ ${COMPILER}/ustdlib.o \
+ ${COMPILER}/blocktim.o \
+ ${COMPILER}/death.o \
+ ${COMPILER}/ParTest.o \
+ ${COMPILER}/timertest.o \
+ ${COMPILER}/emac.o \
+ ${COMPILER}/http-strings.o \
+ ${COMPILER}/httpd-cgi.o \
+ ${COMPILER}/httpd-fs.o \
+ ${COMPILER}/httpd.o \
+ ${COMPILER}/psock.o \
+ ${COMPILER}/timer.o \
+ ${COMPILER}/uip.o \
+ ${COMPILER}/uip_arp.o \
+ ${COMPILER}/uIP_Task.o
+
+INIT_OBJS= ${COMPILER}/startup.o
+
+LIBS= LuminaryDrivers/libdriver.a
+
+
+#
+# The default rule, which causes init to be built.
+#
+all: ${COMPILER} \
+ ${COMPILER}/RTOSDemo.axf \
+
+#
+# The rule to clean out all the build products
+#
+
+clean:
+ @rm -rf ${COMPILER} ${wildcard *.bin} RTOSDemo.axf
+
+#
+# The rule to create the target directory
+#
+${COMPILER}:
+ @mkdir ${COMPILER}
+
+${COMPILER}/RTOSDemo.axf: ${INIT_OBJS} ${OBJS} ${LIBS}
+SCATTER_RTOSDemo=standalone.ld
+ENTRY_RTOSDemo=ResetISR
+
+#
+#
+# Include the automatically generated dependency files.
+#
+-include ${wildcard ${COMPILER}/*.d} __dummy__
+
+
+
+
+
+
--- /dev/null
+/*\r
+ FreeRTOS.org V4.3.0 - Copyright (C) 2003-2007 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS.org distribution.\r
+\r
+ FreeRTOS.org is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS.org is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS.org; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS.org, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section\r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license\r
+ and contact details. Please ensure to read the configuration and relevant\r
+ port sections of the online documentation.\r
+\r
+ Also see http://www.SafeRTOS.com for an IEC 61508 compliant version along\r
+ with commercial development and support options.\r
+ ***************************************************************************\r
+*/\r
+\r
+/*-----------------------------------------------------------\r
+ * Simple parallel port IO routines.\r
+ *-----------------------------------------------------------*/\r
+\r
+/*\r
+*/\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/* Demo includes. */\r
+#include "partest.h"\r
+\r
+/* Library includes. */\r
+#include "hw_types.h"\r
+#include "gpio.h"\r
+#include "hw_memmap.h"\r
+\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestInitialise( void )\r
+{\r
+ GPIODirModeSet( GPIO_PORTF_BASE, GPIO_PIN_0, GPIO_DIR_MODE_OUT );\r
+ GPIOPadConfigSet( GPIO_PORTF_BASE, GPIO_PIN_0, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD );\r
+ GPIOPinWrite( GPIO_PORTF_BASE, GPIO_PIN_0, 0 );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue )\r
+{\r
+ /* There is only one LED. */\r
+ ( void ) uxLED;\r
+ \r
+ GPIOPinWrite( GPIO_PORTF_BASE, GPIO_PIN_0, xValue );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+unsigned portBASE_TYPE uxParTestGetLED( unsigned portBASE_TYPE uxLED )\r
+{\r
+ /* There is only one LED. */\r
+ ( void ) uxLED;\r
+\r
+ return GPIOPinRead( GPIO_PORTF_BASE, GPIO_PIN_0 ); \r
+}\r
+\r
+\r
--- /dev/null
+#ifndef BITMAP_H\r
+#define BITMAP_H\r
+\r
+const unsigned char pucImage[] =\r
+{\r
+0x00, 0x0a, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,\r
+0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,\r
+0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,\r
+0xaa, 0xaa, 0xaa, 0x00, 0x0a, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,\r
+0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,\r
+0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,\r
+0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xa0, 0x0a, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,\r
+0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,\r
+0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,\r
+0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xaa, 0xaa, 0xaa, 0xaf, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfa, 0xaa,\r
+0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf7,\r
+0x00, 0x8f, 0xff, 0xff, 0xf8, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0xff, 0xff, 0xff, 0xff, 0xf8, 0x88, 0x88, 0x88,\r
+0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x8f, 0xff, 0xff, 0xff, 0xff, 0xff, 0x88, 0x77, 0x77, 0x78, 0x8f, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xf8, 0x88, 0x77, 0x77, 0x88, 0x8f, 0xff, 0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff,\r
+0xff, 0xff, 0xf0, 0x00, 0x00, 0x8f, 0x00, 0xff, 0x87, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x78, 0xff, 0xff,\r
+0xf7, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x78, 0xff, 0xff, 0xff, 0x87, 0x77, 0x77, 0x77, 0x77, 0x77,\r
+0x77, 0x77, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x7f, 0xff, 0xff, 0xfa, 0xaa,\r
+0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0x70, 0x00, 0x00, 0x8f, 0x00, 0xff, 0x87, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77,\r
+0x77, 0x77, 0xff, 0xff, 0xf7, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x78, 0xff, 0xff, 0xf8, 0x77, 0x77,\r
+0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x78, 0xff, 0xff, 0xff, 0xff, 0x87, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x8f,\r
+0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0x70, 0x08, 0x00, 0x8f, 0x00, 0xff, 0x87, 0x77, 0x77, 0x77,\r
+0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x8f, 0xff, 0xf7, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x78, 0xff,\r
+0xff, 0x87, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x8f, 0xff, 0xff, 0xf8, 0x77, 0x77, 0x77, 0x77, 0x77,\r
+0x77, 0x77, 0x77, 0x8f, 0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0x00, 0x0f, 0x00, 0x8f, 0x00, 0xff,\r
+0x87, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x78, 0xff, 0xf7, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77,\r
+0x77, 0x77, 0x78, 0xff, 0xf8, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x78, 0xff, 0xff, 0xf8, 0x77,\r
+0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x8f, 0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0x70, 0x07,\r
+0x00, 0x70, 0x00, 0xff, 0x87, 0x77, 0x77, 0x77, 0xff, 0xff, 0xf8, 0x77, 0x77, 0x77, 0x77, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0x77, 0x77, 0x77, 0x7f, 0xff, 0xff, 0xff, 0xff, 0x87, 0x77, 0x77, 0x77, 0x78, 0xff, 0xff, 0xf8, 0x77, 0x77, 0x77, 0x77,\r
+0xff, 0xff, 0x87, 0x77, 0x77, 0x77, 0x8f, 0xff, 0xff, 0xff, 0x88, 0x8f, 0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff,\r
+0xff, 0xff, 0x80, 0x00, 0x00, 0x00, 0x07, 0xff, 0x87, 0x77, 0x77, 0x77, 0xff, 0xff, 0xff, 0x87, 0x77, 0x77, 0x77, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0x77, 0x77, 0x77, 0x7f, 0xff, 0xff, 0xff, 0xff, 0x77, 0x77, 0x77, 0x77, 0xff, 0xff, 0xff, 0xff,\r
+0x87, 0x77, 0x77, 0x77, 0xff, 0xff, 0x77, 0x77, 0x77, 0x77, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfa, 0xaa,\r
+0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0xf7, 0x00, 0x00, 0x00, 0x0f, 0xff, 0x87, 0x77, 0x77, 0x77, 0xff, 0xff, 0xff, 0xf8,\r
+0x77, 0x77, 0x77, 0xff, 0xff, 0xff, 0xff, 0xff, 0x77, 0x77, 0x77, 0x7f, 0xff, 0xff, 0xff, 0xff, 0x77, 0x77, 0x77, 0x77,\r
+0xff, 0xff, 0xff, 0xff, 0xf7, 0x77, 0x77, 0x77, 0x8f, 0xff, 0x77, 0x77, 0x77, 0x77, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0xff, 0x70, 0x00, 0x00, 0xff, 0xff, 0x87, 0x77, 0x77, 0x77,\r
+0xff, 0xff, 0xff, 0xf8, 0x77, 0x77, 0x77, 0xff, 0xff, 0xff, 0xff, 0xff, 0x77, 0x77, 0x77, 0x7f, 0xff, 0xff, 0xff, 0xff,\r
+0x77, 0x77, 0x77, 0x78, 0xff, 0xff, 0xff, 0xff, 0xf8, 0x77, 0x77, 0x77, 0x8f, 0xff, 0x77, 0x77, 0x77, 0x77, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0x87, 0x77, 0x77, 0x77, 0xff, 0xff, 0xff, 0xf7, 0x77, 0x77, 0x78, 0xff, 0xff, 0xff, 0xff, 0xff, 0x77, 0x77, 0x77, 0x7f,\r
+0xff, 0xff, 0xff, 0xf8, 0x77, 0x77, 0x77, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xff, 0x87, 0x77, 0x77, 0x78, 0xff, 0x87, 0x77,\r
+0x77, 0x77, 0x78, 0x8f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0x88, 0xff, 0xff, 0xff, 0x87, 0x77, 0x77, 0x77, 0xff, 0xff, 0xf8, 0x87, 0x77, 0x77, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0x77, 0x77, 0x77, 0x7f, 0xff, 0xff, 0xff, 0xf8, 0x77, 0x77, 0x77, 0x8f, 0xff, 0xff, 0xff, 0xff, 0xff, 0x87, 0x77, 0x77,\r
+0x78, 0xff, 0x87, 0x77, 0x77, 0x77, 0x77, 0x77, 0x8f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0x80, 0x00, 0x8f, 0x8f, 0xff, 0x87, 0x77, 0x77, 0x77, 0x88, 0x88, 0x77, 0x77, 0x77, 0x77, 0x8f, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0x77, 0x77, 0x77, 0x7f, 0xff, 0xff, 0xff, 0xf8, 0x77, 0x77, 0x77, 0x8f, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0x87, 0x77, 0x77, 0x78, 0xff, 0xf7, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x88, 0xff, 0xff, 0xff, 0xff, 0xfa, 0xaa,\r
+0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0xf7, 0x00, 0x00, 0x8f, 0x07, 0xff, 0x87, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77,\r
+0x77, 0x77, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x77, 0x77, 0x77, 0x7f, 0xff, 0xff, 0xff, 0xf8, 0x77, 0x77, 0x77, 0x8f,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0x87, 0x77, 0x77, 0x78, 0xff, 0xf8, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x8f, 0xff,\r
+0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0x70, 0x07, 0x00, 0x8f, 0x00, 0xff, 0x87, 0x77, 0x77, 0x77,\r
+0x77, 0x77, 0x77, 0x77, 0x88, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x77, 0x77, 0x77, 0x7f, 0xff, 0xff, 0xff, 0xf8,\r
+0x77, 0x77, 0x77, 0x8f, 0xff, 0xff, 0xff, 0xff, 0xff, 0x87, 0x77, 0x77, 0x78, 0xff, 0xff, 0xf8, 0x77, 0x77, 0x77, 0x77,\r
+0x77, 0x77, 0x77, 0x8f, 0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0x70, 0x0f, 0x00, 0x8f, 0x00, 0xff,\r
+0x87, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x8f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x77, 0x77, 0x77, 0x7f,\r
+0xff, 0xff, 0xff, 0xf8, 0x77, 0x77, 0x77, 0x8f, 0xff, 0xff, 0xff, 0xff, 0xff, 0x87, 0x77, 0x77, 0x78, 0xff, 0xff, 0xff,\r
+0x87, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x78, 0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0x00, 0x0f,\r
+0x00, 0x8f, 0x00, 0xff, 0x87, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x78, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0x77, 0x77, 0x77, 0x7f, 0xff, 0xff, 0xff, 0xf8, 0x77, 0x77, 0x77, 0x8f, 0xff, 0xff, 0xff, 0xff, 0xff, 0x87, 0x77, 0x77,\r
+0x78, 0xff, 0xff, 0xff, 0xff, 0x88, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff,\r
+0xff, 0xff, 0x70, 0x08, 0x00, 0x88, 0x00, 0xff, 0x87, 0x77, 0x77, 0x77, 0x88, 0x88, 0x77, 0x77, 0x77, 0x78, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0x77, 0x77, 0x77, 0x7f, 0xff, 0xff, 0xff, 0xf8, 0x77, 0x77, 0x77, 0x8f, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0x87, 0x77, 0x77, 0x78, 0xff, 0xff, 0xff, 0xff, 0xff, 0x88, 0x77, 0x77, 0x77, 0x77, 0x77, 0xff, 0xff, 0xfa, 0xaa,\r
+0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0x70, 0x00, 0x00, 0x70, 0x07, 0xff, 0x87, 0x77, 0x77, 0x77, 0xff, 0xff, 0x77, 0x77,\r
+0x77, 0x77, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x77, 0x77, 0x77, 0x7f, 0xff, 0xff, 0xff, 0xf8, 0x77, 0x77, 0x77, 0x7f,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0x87, 0x77, 0x77, 0x78, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf8, 0x77, 0x77, 0x77, 0x77,\r
+0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0xf8, 0x00, 0x00, 0x00, 0x7f, 0xff, 0x87, 0x77, 0x77, 0x77,\r
+0xff, 0xff, 0xf7, 0x77, 0x77, 0x77, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x77, 0x77, 0x77, 0x7f, 0xff, 0xff, 0xff, 0xff,\r
+0x77, 0x77, 0x77, 0x78, 0xff, 0xff, 0xff, 0xff, 0xf8, 0x77, 0x77, 0x77, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0x87, 0x77, 0x77, 0x77, 0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0xff, 0x80, 0x00, 0x00, 0xff, 0xff,\r
+0x87, 0x77, 0x77, 0x77, 0xff, 0xff, 0xf8, 0x77, 0x77, 0x77, 0x8f, 0xff, 0xff, 0xff, 0xff, 0xff, 0x77, 0x77, 0x77, 0x7f,\r
+0xff, 0xff, 0xff, 0xff, 0x77, 0x77, 0x77, 0x77, 0xff, 0xff, 0xff, 0xff, 0xf7, 0x77, 0x77, 0x77, 0x8f, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0x87, 0x77, 0x77, 0x77, 0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0x87, 0x88,\r
+0x88, 0x8f, 0xff, 0xff, 0x87, 0x77, 0x77, 0x77, 0xff, 0xff, 0xff, 0x77, 0x77, 0x77, 0x8f, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0x77, 0x77, 0x77, 0x7f, 0xff, 0xff, 0xff, 0xff, 0x77, 0x77, 0x77, 0x77, 0xff, 0xff, 0xff, 0xff, 0x87, 0x77, 0x77, 0x77,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x87, 0x77, 0x77, 0x77, 0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff,\r
+0xff, 0xff, 0x00, 0x07, 0xff, 0xff, 0xff, 0xff, 0x87, 0x77, 0x77, 0x77, 0xff, 0xff, 0xff, 0x87, 0x77, 0x77, 0x7f, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0x77, 0x77, 0x77, 0x7f, 0xff, 0xff, 0xff, 0xff, 0x87, 0x77, 0x77, 0x77, 0x8f, 0xff, 0xff, 0xff,\r
+0x77, 0x77, 0x77, 0x77, 0xff, 0xff, 0xf7, 0x88, 0xff, 0xff, 0xff, 0xff, 0x87, 0x77, 0x77, 0x77, 0xff, 0xff, 0xfa, 0xaa,\r
+0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0x80, 0x00, 0xff, 0xff, 0xff, 0xff, 0x87, 0x77, 0x77, 0x77, 0xff, 0xff, 0xff, 0xf7,\r
+0x77, 0x77, 0x78, 0xff, 0xff, 0xff, 0xff, 0xff, 0x77, 0x77, 0x77, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xf8, 0x77, 0x77, 0x77,\r
+0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x78, 0xff, 0xff, 0x87, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x78,\r
+0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0xf7, 0x00, 0x88, 0x88, 0x88, 0xff, 0x87, 0x77, 0x77, 0x77,\r
+0xff, 0xff, 0xff, 0xf8, 0x77, 0x77, 0x77, 0xff, 0xff, 0xff, 0xff, 0xff, 0x77, 0x77, 0x77, 0x7f, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0x87, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x8f, 0xff, 0xff, 0x87, 0x77, 0x77, 0x77, 0x77, 0x77,\r
+0x77, 0x77, 0x77, 0x7f, 0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0x70, 0x00, 0x00, 0x00, 0x00, 0xff,\r
+0x87, 0x77, 0x77, 0x77, 0xff, 0xff, 0xff, 0xf8, 0x77, 0x77, 0x77, 0x8f, 0xff, 0xff, 0xff, 0xff, 0x77, 0x77, 0x77, 0x7f,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xf8, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x78, 0xff, 0xff, 0xff, 0x87, 0x77,\r
+0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0xff, 0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0x70, 0x00,\r
+0x00, 0x00, 0x00, 0xff, 0x87, 0x77, 0x77, 0x77, 0xff, 0xff, 0xff, 0xff, 0x77, 0x77, 0x77, 0x7f, 0xff, 0xff, 0xff, 0xff,\r
+0x77, 0x77, 0x77, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x87, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x8f, 0xff,\r
+0xff, 0xff, 0x87, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x8f, 0xff, 0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff,\r
+0xff, 0xff, 0x70, 0x00, 0x00, 0x00, 0x07, 0xff, 0x88, 0x88, 0x88, 0x88, 0xff, 0xff, 0xff, 0xff, 0x88, 0x88, 0x88, 0x88,\r
+0xff, 0xff, 0xff, 0xff, 0x88, 0x88, 0x88, 0x8f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf8, 0x87, 0x77, 0x77, 0x77,\r
+0x88, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x88, 0x77, 0x77, 0x77, 0x77, 0x88, 0x8f, 0xff, 0xff, 0xff, 0xff, 0xfa, 0xaa,\r
+0xaa, 0xaf, 0xff, 0xff, 0x00, 0x0f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff, 0x00, 0x0f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff, 0x00, 0x0f, 0x70, 0x08, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff, 0x00, 0x07, 0x70, 0x07,\r
+0x88, 0x88, 0x88, 0xff, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88,\r
+0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88,\r
+0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff,\r
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xfa, 0xaa,\r
+0xaa, 0xaf, 0xff, 0xff, 0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r
+0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff, 0xf7, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x70, 0x00, 0x00, 0x00,\r
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r
+0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0x70, 0x08, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0x70, 0x08,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfa, 0xaa,\r
+0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaa, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,\r
+0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,\r
+0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,\r
+0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x0a, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,\r
+0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,\r
+0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,\r
+0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xa0, 0x00, 0xaa, 0xaa, 0xaa,\r
+0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,\r
+0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,\r
+0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x00,\r
+0x00 };\r
+\r
+#define bmpBITMAP_HEIGHT 50\r
+#define bmpBITMAP_WIDTH 128\r
+\r
+#endif\r
--- /dev/null
+#ifndef LCD_MESSAGE_H\r
+#define LCD_MESSAGE_H\r
+\r
+typedef struct\r
+{\r
+ char *pcMessage;\r
+} xOLEDMessage;\r
+\r
+#endif /* LCD_MESSAGE_H */\r
--- /dev/null
+/*\r
+ FreeRTOS.org V4.3.0 - Copyright (C) 2003-2007 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS.org distribution.\r
+\r
+ FreeRTOS.org is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS.org is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS.org; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS.org, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section\r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license\r
+ and contact details. Please ensure to read the configuration and relevant\r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+\r
+/*\r
+ * Creates all the demo application tasks, then starts the scheduler. The WEB\r
+ * documentation provides more details of the standard demo application tasks.\r
+ * In addition to the standard demo tasks, the following tasks and tests are\r
+ * defined and/or created within this file:\r
+ *\r
+ * "Fast Interrupt Test" - A high frequency periodic interrupt is generated\r
+ * using a free running timer to demonstrate the use of the\r
+ * configKERNEL_INTERRUPT_PRIORITY configuration constant. The interrupt\r
+ * service routine measures the number of processor clocks that occur between\r
+ * each interrupt - and in so doing measures the jitter in the interrupt timing.\r
+ * The maximum measured jitter time is latched in the ulMaxJitter variable, and\r
+ * displayed on the OLED display by the 'Check' task as described below. The\r
+ * fast interrupt is configured and handled in the timertest.c source file.\r
+ *\r
+ * "OLED" task - the OLED task is a 'gatekeeper' task. It is the only task that\r
+ * is permitted to access the display directly. Other tasks wishing to write a\r
+ * message to the OLED send the message on a queue to the OLED task instead of\r
+ * accessing the OLED themselves. The OLED task just blocks on the queue waiting\r
+ * for messages - waking and displaying the messages as they arrive.\r
+ *\r
+ * "Check" task - This only executes every five seconds but has the highest\r
+ * priority so is guaranteed to get processor time. Its main function is to\r
+ * check that all the standard demo tasks are still operational. Should any\r
+ * unexpected behaviour within a demo task be discovered the 'check' task will\r
+ * write an error to the OLED (via the OLED task). If all the demo tasks are\r
+ * executing with their expected behaviour then the check task writes PASS\r
+ * along with the max jitter time to the OLED (again via the OLED task), as\r
+ * described above.\r
+ *\r
+ * "uIP" task - This is the task that handles the uIP stack. All TCP/IP\r
+ * processing is performed in this task.\r
+ */\r
+\r
+\r
+\r
+/* Standard includes. */\r
+#include <stdio.h>\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "Task.h"\r
+#include "queue.h"\r
+#include "semphr.h"\r
+\r
+/* Demo app includes. */\r
+#include "BlockQ.h"\r
+#include "death.h"\r
+#include "integer.h"\r
+#include "blocktim.h"\r
+#include "flash.h"\r
+#include "partest.h"\r
+#include "semtest.h"\r
+#include "pollq.h"\r
+#include "lcd_message.h"\r
+#include "bitmap.h"\r
+\r
+/* Hardware library includes. */\r
+#include "hw_memmap.h"\r
+#include "hw_types.h"\r
+#include "sysctl.h"\r
+#include "gpio.h"\r
+#include "osram128x64x4.h"\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* The time between cycles of the 'check' task. */\r
+#define mainCHECK_DELAY ( ( portTickType ) 5000 / portTICK_RATE_MS )\r
+\r
+/* Size of the stack allocated to the uIP task. */\r
+#define mainBASIC_WEB_STACK_SIZE ( configMINIMAL_STACK_SIZE * 2 )\r
+\r
+/* The check task uses the sprintf function so requires a little more stack too. */\r
+#define mainCHECK_TASK_STACK_SIZE ( configMINIMAL_STACK_SIZE + 50 )\r
+\r
+/* Task priorities. */\r
+#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
+#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 )\r
+#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 )\r
+#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
+#define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 )\r
+#define mainINTEGER_TASK_PRIORITY ( tskIDLE_PRIORITY )\r
+\r
+/* The maximum number of message that can be waiting for display at any one\r
+time. */\r
+#define mainOLED_QUEUE_SIZE ( 3 )\r
+\r
+/* Dimensions the buffer into which the jitter time is written. */\r
+#define mainMAX_MSG_LEN 25\r
+\r
+/* The period of the system clock in nano seconds. This is used to calculate\r
+the jitter time in nano seconds. */\r
+#define mainNS_PER_CLOCK ( ( unsigned portLONG ) ( ( 1.0 / ( double ) configCPU_CLOCK_HZ ) * 1000000000.0 ) )\r
+\r
+/* Constants used when writing strings to the display. */\r
+#define mainCHARACTER_HEIGHT ( 9 )\r
+#define mainMAX_ROWS ( mainCHARACTER_HEIGHT * 7 )\r
+#define mainFULL_SCALE ( 15 )\r
+#define ulSSI_FREQUENCY 1000000\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Checks the status of all the demo tasks then prints a message to the\r
+ * display. The message will be either PASS - an include in brackets the\r
+ * maximum measured jitter time (as described at the to of the file), or a\r
+ * message that describes which of the standard demo tasks an error has been\r
+ * discovered in.\r
+ *\r
+ * Messages are not written directly to the terminal, but passed to vOLEDTask\r
+ * via a queue.\r
+ */\r
+static void vCheckTask( void *pvParameters );\r
+\r
+/*\r
+ * The task that handles the uIP stack. All TCP/IP processing is performed in\r
+ * this task.\r
+ */\r
+extern void vuIP_Task( void *pvParameters );\r
+\r
+/*\r
+ * The display is written two by more than one task so is controlled by a\r
+ * 'gatekeeper' task. This is the only task that is actually permitted to\r
+ * access the display directly. Other tasks wanting to display a message send\r
+ * the message to the gatekeeper.\r
+ */\r
+static void vOLEDTask( void *pvParameters );\r
+\r
+/*\r
+ * Configure the hardware for the demo.\r
+ */\r
+static void prvSetupHardware( void );\r
+\r
+/*\r
+ * Configures the high frequency timers - those used to measure the timing\r
+ * jitter while the real time kernel is executing.\r
+ */\r
+extern void vSetupTimer( void );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* The queue used to send messages to the OLED task. */\r
+xQueueHandle xOLEDQueue;\r
+\r
+/* The welcome text. */\r
+const portCHAR * const pcWelcomeMessage = " www.FreeRTOS.org";\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+int main( void )\r
+{\r
+ prvSetupHardware();\r
+\r
+ /* Create the queue used by the OLED task. Messages for display on the OLED\r
+ are received via this queue. */\r
+ xOLEDQueue = xQueueCreate( mainOLED_QUEUE_SIZE, sizeof( xOLEDMessage ) );\r
+\r
+ /* Create the uIP task. */\r
+ xTaskCreate( vuIP_Task, ( signed portCHAR * ) "uIP", mainBASIC_WEB_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY - 1, NULL );\r
+\r
+ /* Start the standard demo tasks. */\r
+ vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY );\r
+ vCreateBlockTimeTasks();\r
+ vStartSemaphoreTasks( mainSEM_TEST_PRIORITY );\r
+ vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY );\r
+ vStartIntegerMathTasks( mainINTEGER_TASK_PRIORITY );\r
+\r
+ /* Start the tasks defined within this file/specific to this demo. */\r
+ xTaskCreate( vCheckTask, ( signed portCHAR * ) "Check", mainCHECK_TASK_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL );\r
+ xTaskCreate( vOLEDTask, ( signed portCHAR * ) "OLED", configMINIMAL_STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );\r
+\r
+ /* The suicide tasks must be created last as they need to know how many\r
+ tasks were running prior to their creation in order to ascertain whether\r
+ or not the correct/expected number of tasks are running at any given time. */\r
+ vCreateSuicidalTasks( mainCREATOR_TASK_PRIORITY );\r
+\r
+ /* Configure the high frequency interrupt used to measure the interrupt\r
+ jitter time. */\r
+ #ifdef __ICCARM__\r
+ vSetupTimer();\r
+ #endif\r
+ \r
+ /* Start the scheduler. */\r
+ vTaskStartScheduler();\r
+\r
+ /* Will only get here if there was insufficient memory to create the idle\r
+ task. */\r
+ return 0;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void prvSetupHardware( void )\r
+{\r
+ /* Set the clocking to run from the PLL at 50 MHz */\r
+ SysCtlClockSet( SYSCTL_SYSDIV_4 | SYSCTL_USE_PLL | SYSCTL_OSC_MAIN | SYSCTL_XTAL_8MHZ );\r
+ \r
+ /* Enable/Reset the Ethernet Controller */\r
+ SysCtlPeripheralEnable( SYSCTL_PERIPH_ETH );\r
+ SysCtlPeripheralReset( SYSCTL_PERIPH_ETH );\r
+ \r
+ /* Enable Port F for Ethernet LEDs\r
+ LED0 Bit 3 Output\r
+ LED1 Bit 2 Output */\r
+ SysCtlPeripheralEnable( SYSCTL_PERIPH_GPIOF );\r
+ GPIODirModeSet( GPIO_PORTF_BASE, (GPIO_PIN_2 | GPIO_PIN_3), GPIO_DIR_MODE_HW );\r
+ GPIOPadConfigSet( GPIO_PORTF_BASE, (GPIO_PIN_2 | GPIO_PIN_3 ), GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD ); \r
+ \r
+ vParTestInitialise();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void vCheckTask( void *pvParameters )\r
+{\r
+portTickType xLastExecutionTime;\r
+xOLEDMessage xMessage;\r
+static portCHAR cPassMessage[ mainMAX_MSG_LEN ];\r
+extern unsigned portLONG ulMaxJitter;\r
+\r
+ xLastExecutionTime = xTaskGetTickCount();\r
+ xMessage.pcMessage = cPassMessage;\r
+ \r
+ for( ;; )\r
+ {\r
+ /* Perform this check every mainCHECK_DELAY milliseconds. */\r
+ vTaskDelayUntil( &xLastExecutionTime, mainCHECK_DELAY );\r
+\r
+ /* Has an error been found in any task? */\r
+\r
+ if( xAreBlockingQueuesStillRunning() != pdTRUE )\r
+ {\r
+ xMessage.pcMessage = "ERROR IN BLOCK Q";\r
+ }\r
+ else if( xAreBlockTimeTestTasksStillRunning() != pdTRUE )\r
+ {\r
+ xMessage.pcMessage = "ERROR IN BLOCK TIME";\r
+ }\r
+ else if( xAreSemaphoreTasksStillRunning() != pdTRUE )\r
+ {\r
+ xMessage.pcMessage = "ERROR IN SEMAPHORE";\r
+ }\r
+ else if( xArePollingQueuesStillRunning() != pdTRUE )\r
+ {\r
+ xMessage.pcMessage = "ERROR IN POLL Q";\r
+ }\r
+ else if( xIsCreateTaskStillRunning() != pdTRUE )\r
+ {\r
+ xMessage.pcMessage = "ERROR IN CREATE";\r
+ }\r
+ else if( xAreIntegerMathsTaskStillRunning() != pdTRUE )\r
+ {\r
+ xMessage.pcMessage = "ERROR IN MATH";\r
+ }\r
+ else\r
+ {\r
+ #ifdef __ICCARM__\r
+ sprintf( cPassMessage, "PASS [%uns]", ulMaxJitter * mainNS_PER_CLOCK );\r
+ #else\r
+ sprintf( cPassMessage, "PASS" );\r
+ #endif\r
+ }\r
+\r
+ /* Send the message to the OLED gatekeeper for display. */\r
+ xQueueSend( xOLEDQueue, &xMessage, portMAX_DELAY );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+\r
+\r
+void vOLEDTask( void *pvParameters )\r
+{\r
+xOLEDMessage xMessage;\r
+unsigned portLONG ulY = mainMAX_ROWS;\r
+\r
+ /* Initialise the OLED and display a startup message. */\r
+ OSRAM128x64x4Init( ulSSI_FREQUENCY ); \r
+ \r
+ OSRAM128x64x4StringDraw( " POWERED BY FreeRTOS", 0, 0, mainFULL_SCALE );\r
+ OSRAM128x64x4ImageDraw( pucImage, 0, mainCHARACTER_HEIGHT + 1, bmpBITMAP_WIDTH, bmpBITMAP_HEIGHT );\r
+ \r
+ for( ;; )\r
+ {\r
+ /* Wait for a message to arrive that requires displaying. */\r
+ xQueueReceive( xOLEDQueue, &xMessage, portMAX_DELAY );\r
+ \r
+ /* Write the message on the next available row. */\r
+ ulY += mainCHARACTER_HEIGHT;\r
+ if( ulY >= mainMAX_ROWS )\r
+ {\r
+ ulY = mainCHARACTER_HEIGHT;\r
+ OSRAM128x64x4Clear();\r
+ OSRAM128x64x4StringDraw( pcWelcomeMessage, 0, 0, mainFULL_SCALE ); \r
+ }\r
+\r
+ /* Display the message. */\r
+ OSRAM128x64x4StringDraw( xMessage.pcMessage, 0, ulY, mainFULL_SCALE );\r
+ }\r
+}\r
--- /dev/null
+#******************************************************************************
+#
+# makedefs - Definitions common to all makefiles.
+#
+# Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
+#
+# Software License Agreement
+#
+# Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+# exclusively on LMI's Stellaris Family of microcontroller products.
+#
+# The software is owned by LMI and/or its suppliers, and is protected under
+# applicable copyright laws. All rights are reserved. Any use in violation
+# of the foregoing restrictions may subject the user to criminal sanctions
+# under applicable laws, as well as to civil liability for the breach of the
+# terms and conditions of this license.
+#
+# THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+# OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+# MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+# LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+# CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+#
+#******************************************************************************
+
+#******************************************************************************
+#
+# Get the operating system name. If this is Cygwin, the .d files will be
+# munged to convert c: into /cygdrive/c so that "make" will be happy with the
+# auto-generated dependencies.
+#
+#******************************************************************************
+os:=${shell uname -s}
+
+#******************************************************************************
+#
+# The compiler to be used.
+#
+#******************************************************************************
+ifndef COMPILER
+COMPILER=gcc
+endif
+
+#******************************************************************************
+#
+# The debugger to be used.
+#
+#******************************************************************************
+ifndef DEBUGGER
+DEBUGGER=gdb
+endif
+
+#******************************************************************************
+#
+# Definitions for using GCC.
+#
+#******************************************************************************
+ifeq (${COMPILER}, gcc)
+
+#
+# The command for calling the compiler.
+#
+CC=arm-stellaris-eabi-gcc
+
+#
+# The flags passed to the assembler.
+#
+AFLAGS=-mthumb \
+ -mcpu=cortex-m3 \
+ -MD
+
+#
+# The flags passed to the compiler.
+#
+CFLAGS=-mthumb \
+ -mcpu=cortex-m3 \
+ -O2 \
+ -MD
+
+#
+# The command for calling the library archiver.
+#
+AR=arm-stellaris-eabi-ar
+
+#
+# The command for calling the linker.
+#
+LD=arm-stellaris-eabi-ld
+
+#
+# The flags passed to the linker.
+#
+LDFLAGS= -Map gcc/out.map
+
+#
+# Get the location of libgcc.a from the GCC front-end.
+#
+LIBGCC=${shell ${CC} -mthumb -march=armv6t2 -print-libgcc-file-name}
+
+#
+# Get the location of libc.a from the GCC front-end.
+#
+LIBC=${shell ${CC} -mthumb -march=armv6t2 -print-file-name=libc.a}
+
+#
+# The command for extracting images from the linked executables.
+#
+OBJCOPY=arm-stellaris-eabi-objcopy
+
+endif
+
+#******************************************************************************
+#
+# Tell the compiler to include debugging information if the DEBUG environment
+# variable is set.
+#
+#******************************************************************************
+ifdef DEBUG
+CFLAGS += -g
+endif
+
+#******************************************************************************
+#
+# The rule for building the object file from each C source file.
+#
+#******************************************************************************
+${COMPILER}/%.o: %.c
+ @if [ 'x${VERBOSE}' = x ]; \
+ then \
+ echo " CC ${<}"; \
+ else \
+ echo ${CC} ${CFLAGS} -D${COMPILER} -o ${@} -c ${<}; \
+ fi
+ @${CC} ${CFLAGS} -D${COMPILER} -o ${@} -c ${<}
+ifeq (${COMPILER}, rvds)
+ @mv -f ${notdir ${@:.o=.d}} ${COMPILER}
+endif
+ifneq ($(findstring CYGWIN, ${os}), )
+ @perl -i.bak -p -e 's/[Cc]:/\/cygdrive\/c/g' ${@:.o=.d}
+endif
+
+#******************************************************************************
+#
+# The rule for building the object file from each assembly source file.
+#
+#******************************************************************************
+${COMPILER}/%.o: %.S
+ @if [ 'x${VERBOSE}' = x ]; \
+ then \
+ echo " CC ${<}"; \
+ else \
+ echo ${CC} ${AFLAGS} -D${COMPILER} -o ${@} -c ${<}; \
+ fi
+ifeq (${COMPILER}, rvds)
+ @${CC} ${AFLAGS} -D${COMPILER} -E ${<} > ${@:.o=_.S}
+ @${CC} ${AFLAGS} -o ${@} -c ${@:.o=_.S}
+ @rm ${@:.o=_.S}
+ @${CC} ${AFLAGS} -D${COMPILER} --md -E ${<}
+ @sed 's,<stdout>,${@},g' ${notdir ${<:.S=.d}} > ${@:.o=.d}
+ @rm ${notdir ${<:.S=.d}}
+endif
+ifeq (${COMPILER}, gcc)
+ @${CC} ${AFLAGS} -D${COMPILER} -o ${@} -c ${<}
+endif
+ifneq ($(findstring CYGWIN, ${os}), )
+ @perl -i.bak -p -e 's/[Cc]:/\/cygdrive\/c/g' ${@:.o=.d}
+endif
+
+#******************************************************************************
+#
+# The rule for creating an object library.
+#
+#******************************************************************************
+${COMPILER}/%.a:
+ @if [ 'x${VERBOSE}' = x ]; \
+ then \
+ echo " AR ${@}"; \
+ else \
+ echo ${AR} -cr ${@} ${^}; \
+ fi
+ @${AR} -cr ${@} ${^}
+
+#******************************************************************************
+#
+# The rule for linking the application.
+#
+#******************************************************************************
+${COMPILER}/%.axf:
+ @if [ 'x${VERBOSE}' = x ]; \
+ then \
+ echo " LD ${@}"; \
+ fi
+ifeq (${COMPILER}, gcc)
+ @if [ 'x${VERBOSE}' != x ]; \
+ then \
+ echo ${LD} -T ${SCATTER_${notdir ${@:.axf=}}} \
+ --entry ${ENTRY_${notdir ${@:.axf=}}} \
+ ${LDFLAGSgcc_${notdir ${@:.axf=}}} \
+ ${LDFLAGS} -o ${@} ${^} \
+ '${LIBC}' '${LIBGCC}'; \
+ fi
+ @${LD} -T ${SCATTER_${notdir ${@:.axf=}}} \
+ --entry ${ENTRY_${notdir ${@:.axf=}}} \
+ ${LDFLAGSgcc_${notdir ${@:.axf=}}} \
+ ${LDFLAGS} -o ${@} ${^} \
+ '${LIBC}' '${LIBGCC}'
+ @${OBJCOPY} -O binary ${@} ${@:.axf=.bin}
+endif
--- /dev/null
+/******************************************************************************\r
+ *\r
+ * standalone.ld - Linker script for applications using startup.c and\r
+ * DriverLib.\r
+ *\r
+ * Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+ * \r
+ * Software License Agreement\r
+ * \r
+ * Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+ * exclusively on LMI's microcontroller products.\r
+ * \r
+ * The software is owned by LMI and/or its suppliers, and is protected under\r
+ * applicable copyright laws. All rights are reserved. Any use in violation\r
+ * of the foregoing restrictions may subject the user to criminal sanctions\r
+ * under applicable laws, as well as to civil liability for the breach of the\r
+ * terms and conditions of this license.\r
+ * \r
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+ * LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+ * \r
+ * This is part of revision 1392 of the Stellaris Peripheral Driver Library.\r
+ *\r
+ *****************************************************************************/\r
+\r
+MEMORY\r
+{\r
+ FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 256K\r
+ SRAM (rwx) : ORIGIN = 0x20000000, LENGTH = 64K\r
+}\r
+\r
+SECTIONS\r
+{\r
+ .text :\r
+ {\r
+ KEEP(*(.isr_vector))\r
+ *(.text*)\r
+ *(.rodata*)\r
+ _etext = .;\r
+ } > FLASH\r
+\r
+ .data : AT (ADDR(.text) + SIZEOF(.text))\r
+ {\r
+ _data = .;\r
+ *(vtable)\r
+ *(.data*)\r
+ _edata = .;\r
+ } > SRAM\r
+\r
+ .bss :\r
+ {\r
+ _bss = .;\r
+ *(.bss*)\r
+ *(COMMON)\r
+ _ebss = .;\r
+ } > SRAM\r
+}\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// startup.c - Boot code for Stellaris.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1392 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+//*****************************************************************************\r
+//\r
+// Forward declaration of the default fault handlers.\r
+//\r
+//*****************************************************************************\r
+void ResetISR(void);\r
+static void NmiSR(void);\r
+static void FaultISR(void);\r
+static void IntDefaultHandler(void);\r
+\r
+//*****************************************************************************\r
+//\r
+// The entry point for the application.\r
+//\r
+//*****************************************************************************\r
+extern int main(void);\r
+extern void xPortPendSVHandler(void);\r
+extern void xPortSysTickHandler(void);\r
+extern void vEMAC_ISR(void);\r
+extern void Timer0IntHandler(void);\r
+\r
+//*****************************************************************************\r
+//\r
+// Reserve space for the system stack.\r
+//\r
+//*****************************************************************************\r
+#ifndef STACK_SIZE\r
+#define STACK_SIZE 64\r
+#endif\r
+static unsigned long pulStack[STACK_SIZE];\r
+\r
+//*****************************************************************************\r
+//\r
+// The minimal vector table for a Cortex M3. Note that the proper constructs\r
+// must be placed on this to ensure that it ends up at physical address\r
+// 0x0000.0000.\r
+//\r
+//*****************************************************************************\r
+__attribute__ ((section(".isr_vector")))\r
+void (* const g_pfnVectors[])(void) =\r
+{\r
+ (void (*)(void))((unsigned long)pulStack + sizeof(pulStack)),\r
+ // The initial stack pointer\r
+ ResetISR, // The reset handler\r
+ NmiSR, // The NMI handler\r
+ FaultISR, // The hard fault handler\r
+ IntDefaultHandler, // The MPU fault handler\r
+ IntDefaultHandler, // The bus fault handler\r
+ IntDefaultHandler, // The usage fault handler\r
+ 0, // Reserved\r
+ 0, // Reserved\r
+ 0, // Reserved\r
+ 0, // Reserved\r
+ IntDefaultHandler, // SVCall handler\r
+ IntDefaultHandler, // Debug monitor handler\r
+ 0, // Reserved\r
+ xPortPendSVHandler, // The PendSV handler\r
+ xPortSysTickHandler, // The SysTick handler\r
+ IntDefaultHandler, // GPIO Port A\r
+ IntDefaultHandler, // GPIO Port B\r
+ IntDefaultHandler, // GPIO Port C\r
+ IntDefaultHandler, // GPIO Port D\r
+ IntDefaultHandler, // GPIO Port E\r
+ IntDefaultHandler, // UART0 Rx and Tx\r
+ IntDefaultHandler, // UART1 Rx and Tx\r
+ IntDefaultHandler, // SSI Rx and Tx\r
+ IntDefaultHandler, // I2C Master and Slave\r
+ IntDefaultHandler, // PWM Fault\r
+ IntDefaultHandler, // PWM Generator 0\r
+ IntDefaultHandler, // PWM Generator 1\r
+ IntDefaultHandler, // PWM Generator 2\r
+ IntDefaultHandler, // Quadrature Encoder\r
+ IntDefaultHandler, // ADC Sequence 0\r
+ IntDefaultHandler, // ADC Sequence 1\r
+ IntDefaultHandler, // ADC Sequence 2\r
+ IntDefaultHandler, // ADC Sequence 3\r
+ IntDefaultHandler, // Watchdog timer\r
+ Timer0IntHandler, // Timer 0 subtimer A\r
+ IntDefaultHandler, // Timer 0 subtimer B\r
+ IntDefaultHandler, // Timer 1 subtimer A\r
+ IntDefaultHandler, // Timer 1 subtimer B\r
+ IntDefaultHandler, // Timer 2 subtimer A\r
+ IntDefaultHandler, // Timer 2 subtimer B\r
+ IntDefaultHandler, // Analog Comparator 0\r
+ IntDefaultHandler, // Analog Comparator 1\r
+ IntDefaultHandler, // Analog Comparator 2\r
+ IntDefaultHandler, // System Control (PLL, OSC, BO)\r
+ IntDefaultHandler, // FLASH Control\r
+ IntDefaultHandler, // GPIO Port F\r
+ IntDefaultHandler, // GPIO Port G\r
+ IntDefaultHandler, // GPIO Port H\r
+ IntDefaultHandler, // UART2 Rx and Tx\r
+ IntDefaultHandler, // SSI1 Rx and Tx\r
+ IntDefaultHandler, // Timer 3 subtimer A\r
+ IntDefaultHandler, // Timer 3 subtimer B\r
+ IntDefaultHandler, // I2C1 Master and Slave\r
+ IntDefaultHandler, // Quadrature Encoder 1\r
+ IntDefaultHandler, // CAN0\r
+ IntDefaultHandler, // CAN1\r
+ 0, // Reserved\r
+ vEMAC_ISR, // Ethernet\r
+ IntDefaultHandler // Hibernate\r
+};\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are constructs created by the linker, indicating where the\r
+// the "data" and "bss" segments reside in memory. The initializers for the\r
+// for the "data" segment resides immediately following the "text" segment.\r
+//\r
+//*****************************************************************************\r
+extern unsigned long _etext;\r
+extern unsigned long _data;\r
+extern unsigned long _edata;\r
+extern unsigned long _bss;\r
+extern unsigned long _ebss;\r
+\r
+//*****************************************************************************\r
+//\r
+// This is the code that gets called when the processor first starts execution\r
+// following a reset event. Only the absolutely necessary set is performed,\r
+// after which the application supplied main() routine is called. Any fancy\r
+// actions (such as making decisions based on the reset cause register, and\r
+// resetting the bits in that register) are left solely in the hands of the\r
+// application.\r
+//\r
+//*****************************************************************************\r
+void\r
+ResetISR(void)\r
+{\r
+ unsigned long *pulSrc, *pulDest;\r
+\r
+ //\r
+ // Copy the data segment initializers from flash to SRAM.\r
+ //\r
+ pulSrc = &_etext;\r
+ for(pulDest = &_data; pulDest < &_edata; )\r
+ {\r
+ *pulDest++ = *pulSrc++;\r
+ }\r
+\r
+ //\r
+ // Zero fill the bss segment.\r
+ //\r
+ for(pulDest = &_bss; pulDest < &_ebss; )\r
+ {\r
+ *pulDest++ = 0;\r
+ }\r
+\r
+ //\r
+ // Call the application's entry point.\r
+ //\r
+ main();\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+// This is the code that gets called when the processor receives a NMI. This\r
+// simply enters an infinite loop, preserving the system state for examination\r
+// by a debugger.\r
+//\r
+//*****************************************************************************\r
+static void\r
+NmiSR(void)\r
+{\r
+ //\r
+ // Enter an infinite loop.\r
+ //\r
+ while(1)\r
+ {\r
+ }\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+// This is the code that gets called when the processor receives a fault\r
+// interrupt. This simply enters an infinite loop, preserving the system state\r
+// for examination by a debugger.\r
+//\r
+//*****************************************************************************\r
+static void\r
+FaultISR(void)\r
+{\r
+ //\r
+ // Enter an infinite loop.\r
+ //\r
+ while(1)\r
+ {\r
+ }\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+// This is the code that gets called when the processor receives an unexpected\r
+// interrupt. This simply enters an infinite loop, preserving the system state\r
+// for examination by a debugger.\r
+//\r
+//*****************************************************************************\r
+static void\r
+IntDefaultHandler(void)\r
+{\r
+ //\r
+ // Go into an infinite loop.\r
+ //\r
+ while(1)\r
+ {\r
+ }\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+// A dummy printf function to satisfy the calls to printf from uip. This\r
+// avoids pulling in the run-time library.\r
+//\r
+//*****************************************************************************\r
+int\r
+uipprintf(const char *fmt, ...)\r
+{\r
+ return(0);\r
+}\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS.org V4.3.0 - Copyright (C) 2003-2007 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS.org distribution.\r
+\r
+ FreeRTOS.org is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS.org is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS.org; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS.org, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section\r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license\r
+ and contact details. Please ensure to read the configuration and relevant\r
+ port sections of the online documentation.\r
+\r
+ Also see http://www.SafeRTOS.com for an IEC 61508 compliant version along\r
+ with commercial development and support options.\r
+ ***************************************************************************\r
+*/\r
+\r
+/* High speed timer test as described in main.c. */\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+\r
+/* Library includes. */\r
+#include "hw_ints.h"\r
+#include "hw_memmap.h"\r
+#include "hw_types.h"\r
+#include "interrupt.h"\r
+#include "sysctl.h"\r
+#include "LMI_timer.h"\r
+\r
+/* The set frequency of the interrupt. Deviations from this are measured as\r
+the jitter. */\r
+#define timerINTERRUPT_FREQUENCY ( 20000UL )\r
+\r
+/* The expected time between each of the timer interrupts - if the jitter was\r
+zero. */\r
+#define timerEXPECTED_DIFFERENCE_VALUE ( configCPU_CLOCK_HZ / timerINTERRUPT_FREQUENCY )\r
+\r
+/* The highest available interrupt priority. */\r
+#define timerHIGHEST_PRIORITY ( 0 )\r
+\r
+/* Misc defines. */\r
+#define timerMAX_32BIT_VALUE ( 0xffffffffUL )\r
+#define timerTIMER_1_COUNT_VALUE ( * ( ( unsigned long * ) ( TIMER1_BASE + 0x48 ) ) )\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Interrupt handler in which the jitter is measured. */\r
+void Timer0IntHandler( void );\r
+\r
+/* Stores the value of the maximum recorded jitter between interrupts. */\r
+unsigned portLONG ulMaxJitter = 0;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void vSetupTimer( void )\r
+{\r
+unsigned long ulFrequency;\r
+\r
+ /* Timer zero is used to generate the interrupts, and timer 1 is used\r
+ to measure the jitter. */\r
+ SysCtlPeripheralEnable( SYSCTL_PERIPH_TIMER0 );\r
+ SysCtlPeripheralEnable( SYSCTL_PERIPH_TIMER1 );\r
+ TimerConfigure( TIMER0_BASE, TIMER_CFG_32_BIT_PER );\r
+ TimerConfigure( TIMER1_BASE, TIMER_CFG_32_BIT_PER );\r
+ \r
+ /* Set the timer interrupt to be above the kernel - highest. */\r
+ IntPrioritySet( INT_TIMER0A, timerHIGHEST_PRIORITY );\r
+\r
+ /* Just used to measure time. */\r
+ TimerLoadSet(TIMER1_BASE, TIMER_A, timerMAX_32BIT_VALUE );\r
+ \r
+ /* The rate at which the timer will interrupt. */\r
+ ulFrequency = configCPU_CLOCK_HZ / timerINTERRUPT_FREQUENCY; \r
+ TimerLoadSet( TIMER0_BASE, TIMER_A, ulFrequency );\r
+ IntEnable( INT_TIMER0A );\r
+ TimerIntEnable( TIMER0_BASE, TIMER_TIMA_TIMEOUT );\r
+\r
+ /* Enable both timers. */ \r
+ TimerEnable( TIMER0_BASE, TIMER_A );\r
+ TimerEnable( TIMER1_BASE, TIMER_A );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void Timer0IntHandler( void )\r
+{\r
+unsigned portLONG ulDifference, ulCurrentCount;\r
+static portLONG ulMaxDifference = 0, ulLastCount = 0;\r
+\r
+ /* We use the timer 1 counter value to measure the clock cycles between\r
+ the timer 0 interrupts. */\r
+ ulCurrentCount = timerTIMER_1_COUNT_VALUE;\r
+\r
+ if( ulCurrentCount < ulLastCount )\r
+ { \r
+ /* How many times has timer 1 counted since the last interrupt? */\r
+ ulDifference = ulLastCount - ulCurrentCount;\r
+ \r
+ /* Is this the largest difference we have measured yet? */\r
+ if( ulDifference > ulMaxDifference )\r
+ {\r
+ ulMaxDifference = ulDifference;\r
+ ulMaxJitter = ulMaxDifference - timerEXPECTED_DIFFERENCE_VALUE;\r
+ }\r
+ }\r
+ \r
+ ulLastCount = ulCurrentCount;\r
+\r
+ TimerIntClear( TIMER0_BASE, TIMER_TIMA_TIMEOUT );\r
+}\r
+\r
+\r
+\r
+\r
+\r
--- /dev/null
+APP_SOURCES += httpd.c http-strings.c httpd-fs.c httpd-cgi.c\r
--- /dev/null
+/*\r
+ * Copyright (c) 2006, Swedish Institute of Computer Science.\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ * 1. Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the\r
+ * documentation and/or other materials provided with the distribution.\r
+ * 3. Neither the name of the Institute nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND\r
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\r
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\r
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\r
+ * SUCH DAMAGE.\r
+ *\r
+ * This file is part of the uIP TCP/IP stack\r
+ *\r
+ * $Id: clock-arch.h,v 1.2 2006/06/12 08:00:31 adam Exp $\r
+ */\r
+\r
+#ifndef __CLOCK_ARCH_H__\r
+#define __CLOCK_ARCH_H__\r
+\r
+#include "FreeRTOS.h"\r
+\r
+typedef unsigned long clock_time_t;\r
+#define CLOCK_CONF_SECOND configTICK_RATE_HZ\r
+\r
+#endif /* __CLOCK_ARCH_H__ */\r
--- /dev/null
+/*\r
+ FreeRTOS.org V4.3.0 - Copyright (C) 2003-2007 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS.org distribution.\r
+\r
+ FreeRTOS.org is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS.org is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS.org; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS.org, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section\r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license\r
+ and contact details. Please ensure to read the configuration and relevant\r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/* Kernel includes. */\r
+#include "FreeRTOS.h"\r
+#include "Semphr.h"\r
+#include "task.h"\r
+\r
+/* Demo includes. */\r
+#include "EMAC.h"\r
+\r
+/* uIP includes. */\r
+#include "uip.h"\r
+\r
+/* Hardware library includes. */\r
+#include "hw_types.h"\r
+#include "hw_memmap.h"\r
+#include "hw_ints.h"\r
+#include "hw_ethernet.h"\r
+#include "ethernet.h"\r
+#include "interrupt.h"\r
+\r
+#define emacNUM_RX_BUFFERS 5\r
+#define emacFRAM_SIZE_BYTES 2\r
+#define macNEGOTIATE_DELAY 2000\r
+#define macWAIT_SEND_TIME ( 10 )\r
+\r
+/* The task that handles the MAC peripheral. This is created at a high\r
+priority and is effectively a deferred interrupt handler. The peripheral\r
+handling is deferred to a task to prevent the entire FIFO having to be read\r
+from within an ISR. */\r
+void vMACHandleTask( void *pvParameters );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* The semaphore used to wake the uIP task when data arrives. */\r
+xSemaphoreHandle xEMACSemaphore = NULL;\r
+\r
+/* The semaphore used to wake the interrupt handler task. The peripheral\r
+is processed at the task level to prevent the need to read the entire FIFO from\r
+within the ISR itself. */\r
+xSemaphoreHandle xMACInterruptSemaphore = NULL;\r
+\r
+/* The buffer used by the uIP stack. In this case the pointer is used to\r
+point to one of the Rx buffers. */\r
+unsigned portCHAR *uip_buf;\r
+\r
+/* Buffers into which Rx data is placed. */\r
+static unsigned portCHAR ucRxBuffers[ emacNUM_RX_BUFFERS ][ UIP_BUFSIZE + ( 4 * emacFRAM_SIZE_BYTES ) ];\r
+\r
+/* The length of the data within each of the Rx buffers. */\r
+static unsigned portLONG ulRxLength[ emacNUM_RX_BUFFERS ];\r
+\r
+/* Used to keep a track of the number of bytes to transmit. */\r
+static unsigned portLONG ulNextTxSpace;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+portBASE_TYPE vInitEMAC( void )\r
+{\r
+unsigned long ulTemp;\r
+portBASE_TYPE xReturn;\r
+\r
+ /* Ensure all interrupts are disabled. */\r
+ EthernetIntDisable( ETH_BASE, ( ETH_INT_PHY | ETH_INT_MDIO | ETH_INT_RXER | ETH_INT_RXOF | ETH_INT_TX | ETH_INT_TXER | ETH_INT_RX));\r
+\r
+ /* Clear any interrupts that were already pending. */\r
+ ulTemp = EthernetIntStatus( ETH_BASE, pdFALSE );\r
+ EthernetIntClear( ETH_BASE, ulTemp );\r
+\r
+ /* Initialise the MAC and connect. */\r
+ EthernetInit( ETH_BASE );\r
+ EthernetConfigSet( ETH_BASE, ( ETH_CFG_TX_DPLXEN | ETH_CFG_TX_CRCEN | ETH_CFG_TX_PADEN ) );\r
+ EthernetEnable( ETH_BASE );\r
+\r
+ /* Mark each Rx buffer as empty. */\r
+ for( ulTemp = 0; ulTemp < emacNUM_RX_BUFFERS; ulTemp++ )\r
+ {\r
+ ulRxLength[ ulTemp ] = 0;\r
+ }\r
+ \r
+ /* Create the queue and task used to defer the MAC processing to the\r
+ task level. */\r
+ vSemaphoreCreateBinary( xMACInterruptSemaphore );\r
+ xSemaphoreTake( xMACInterruptSemaphore, 0 );\r
+ xReturn = xTaskCreate( vMACHandleTask, ( signed portCHAR * ) "MAC", configMINIMAL_STACK_SIZE, NULL, configMAX_PRIORITIES - 1, NULL );\r
+ vTaskDelay( macNEGOTIATE_DELAY );\r
+ \r
+ /* We are only interested in Rx interrupts. */\r
+ IntPrioritySet( INT_ETH, configKERNEL_INTERRUPT_PRIORITY );\r
+ IntEnable( INT_ETH );\r
+ EthernetIntEnable(ETH_BASE, ETH_INT_RX);\r
+\r
+ return xReturn;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+unsigned int uiGetEMACRxData( unsigned char *ucBuffer )\r
+{\r
+static unsigned long ulNextRxBuffer = 0;\r
+unsigned int iLen;\r
+\r
+ iLen = ulRxLength[ ulNextRxBuffer ];\r
+\r
+ if( iLen != 0 )\r
+ {\r
+ /* Leave room for the size at the start of the buffer. */\r
+ uip_buf = &( ucRxBuffers[ ulNextRxBuffer ][ 2 ] );\r
+ \r
+ ulRxLength[ ulNextRxBuffer ] = 0;\r
+ \r
+ ulNextRxBuffer++;\r
+ if( ulNextRxBuffer >= emacNUM_RX_BUFFERS )\r
+ {\r
+ ulNextRxBuffer = 0;\r
+ }\r
+ }\r
+\r
+ return iLen;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vInitialiseSend( void )\r
+{\r
+ /* Set the index to the first byte to send - skipping over the size\r
+ bytes. */\r
+ ulNextTxSpace = 2;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vIncrementTxLength( unsigned portLONG ulLength )\r
+{\r
+ ulNextTxSpace += ulLength;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vSendBufferToMAC( void )\r
+{\r
+unsigned long *pulSource;\r
+unsigned portSHORT * pus;\r
+unsigned portLONG ulNextWord;\r
+\r
+ /* Locate the data to be send. */\r
+ pus = ( unsigned portSHORT * ) uip_buf;\r
+\r
+ /* Add in the size of the data. */\r
+ pus--;\r
+ *pus = ulNextTxSpace;\r
+\r
+ /* Wait for data to be sent if there is no space immediately. */\r
+ while( !EthernetSpaceAvail( ETH_BASE ) )\r
+ {\r
+ vTaskDelay( macWAIT_SEND_TIME );\r
+ }\r
+ \r
+ pulSource = ( unsigned portLONG * ) pus; \r
+ \r
+ for( ulNextWord = 0; ulNextWord < ulNextTxSpace; ulNextWord += sizeof( unsigned portLONG ) )\r
+ {\r
+ HWREG(ETH_BASE + MAC_O_DATA) = *pulSource;\r
+ pulSource++;\r
+ }\r
+\r
+ /* Go. */\r
+ HWREG( ETH_BASE + MAC_O_TR ) = MAC_TR_NEWTX;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vEMAC_ISR( void )\r
+{\r
+portBASE_TYPE xSwitchRequired = pdFALSE;\r
+unsigned portLONG ulTemp;\r
+\r
+ /* Clear the interrupt. */\r
+ ulTemp = EthernetIntStatus( ETH_BASE, pdFALSE );\r
+ EthernetIntClear( ETH_BASE, ulTemp );\r
+ \r
+ /* Was it an Rx interrupt? */\r
+ if( ulTemp & ETH_INT_RX )\r
+ {\r
+ xSwitchRequired = pdTRUE;\r
+ xSemaphoreGiveFromISR( xMACInterruptSemaphore, pdFALSE );\r
+ EthernetIntDisable( ETH_BASE, ETH_INT_RX );\r
+ }\r
+ \r
+ /* Switch to the uIP task. */\r
+ portEND_SWITCHING_ISR( xSwitchRequired );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vMACHandleTask( void *pvParameters )\r
+{\r
+unsigned long ulLen = 0, i;\r
+unsigned portLONG ulLength, ulInt;\r
+unsigned long *pulBuffer;\r
+static unsigned portLONG ulNextRxBuffer = 0;\r
+portBASE_TYPE xSwitchRequired = pdFALSE;\r
+\r
+ for( ;; )\r
+ {\r
+ /* Wait for something to do. */\r
+ xSemaphoreTake( xMACInterruptSemaphore, portMAX_DELAY );\r
+ \r
+ while( ( ulInt = ( EthernetIntStatus( ETH_BASE, pdFALSE ) & ETH_INT_RX ) ) != 0 )\r
+ { \r
+ ulLength = HWREG( ETH_BASE + MAC_O_DATA );\r
+ \r
+ /* Leave room at the start of the buffer for the size. */\r
+ pulBuffer = ( unsigned long * ) &( ucRxBuffers[ ulNextRxBuffer ][ 2 ] ); \r
+ *pulBuffer = ( ulLength >> 16 );\r
+\r
+ /* Get the size of the data. */ \r
+ pulBuffer = ( unsigned long * ) &( ucRxBuffers[ ulNextRxBuffer ][ 4 ] ); \r
+ ulLength &= 0xFFFF;\r
+ \r
+ if( ulLength > 4 )\r
+ {\r
+ ulLength -= 4;\r
+ \r
+ if( ulLength >= UIP_BUFSIZE )\r
+ {\r
+ /* The data won't fit in our buffer. Ensure we don't\r
+ try to write into the buffer. */\r
+ ulLength = 0;\r
+ }\r
+\r
+ /* Read out the data into our buffer. */\r
+ for( i = 0; i < ulLength; i += sizeof( unsigned portLONG ) )\r
+ {\r
+ *pulBuffer = HWREG( ETH_BASE + MAC_O_DATA );\r
+ pulBuffer++;\r
+ }\r
+ \r
+ /* Store the length of the data into the separate array. */\r
+ ulRxLength[ ulNextRxBuffer ] = ulLength;\r
+ \r
+ /* Use the next buffer the next time through. */\r
+ ulNextRxBuffer++;\r
+ if( ulNextRxBuffer >= emacNUM_RX_BUFFERS )\r
+ {\r
+ ulNextRxBuffer = 0;\r
+ }\r
+ \r
+ /* Ensure the uIP task is not blocked as data has arrived. */\r
+ xSemaphoreGive( xEMACSemaphore );\r
+ }\r
+ }\r
+ \r
+ EthernetIntEnable( ETH_BASE, ETH_INT_RX );\r
+ }\r
+}\r
+\r
--- /dev/null
+/*----------------------------------------------------------------------------\r
+ * LPC2378 Ethernet Definitions\r
+ *----------------------------------------------------------------------------\r
+ * Name: EMAC.H\r
+ * Purpose: Philips LPC2378 EMAC hardware definitions\r
+ *----------------------------------------------------------------------------\r
+ * Copyright (c) 2006 KEIL - An ARM Company. All rights reserved.\r
+ *---------------------------------------------------------------------------*/\r
+#ifndef __EMAC_H\r
+#define __EMAC_H\r
+\r
+/* MAC address definition. The MAC address must be unique on the network. */\r
+#define emacETHADDR0 0\r
+#define emacETHADDR1 0xbd\r
+#define emacETHADDR2 0x33\r
+#define emacETHADDR3 0x02\r
+#define emacETHADDR4 0x64\r
+#define emacETHADDR5 0x24\r
+\r
+\r
+/* EMAC Memory Buffer configuration for 16K Ethernet RAM. */\r
+#define NUM_RX_FRAG 4 /* Num.of RX Fragments 4*1536= 6.0kB */\r
+#define NUM_TX_FRAG 2 /* Num.of TX Fragments 2*1536= 3.0kB */\r
+#define ETH_FRAG_SIZE 1536 /* Packet Fragment size 1536 Bytes */\r
+\r
+#define ETH_MAX_FLEN 1536 /* Max. Ethernet Frame Size */\r
+\r
+/* EMAC variables located in 16K Ethernet SRAM */\r
+#define RX_DESC_BASE 0x7FE00000\r
+#define RX_STAT_BASE (RX_DESC_BASE + NUM_RX_FRAG*8)\r
+#define TX_DESC_BASE (RX_STAT_BASE + NUM_RX_FRAG*8)\r
+#define TX_STAT_BASE (TX_DESC_BASE + NUM_TX_FRAG*8)\r
+#define RX_BUF_BASE (TX_STAT_BASE + NUM_TX_FRAG*4)\r
+#define TX_BUF_BASE (RX_BUF_BASE + NUM_RX_FRAG*ETH_FRAG_SIZE)\r
+\r
+/* RX and TX descriptor and status definitions. */\r
+#define RX_DESC_PACKET(i) (*(unsigned int *)(RX_DESC_BASE + 8*i))\r
+#define RX_DESC_CTRL(i) (*(unsigned int *)(RX_DESC_BASE+4 + 8*i))\r
+#define RX_STAT_INFO(i) (*(unsigned int *)(RX_STAT_BASE + 8*i))\r
+#define RX_STAT_HASHCRC(i) (*(unsigned int *)(RX_STAT_BASE+4 + 8*i))\r
+#define TX_DESC_PACKET(i) (*(unsigned int *)(TX_DESC_BASE + 8*i))\r
+#define TX_DESC_CTRL(i) (*(unsigned int *)(TX_DESC_BASE+4 + 8*i))\r
+#define TX_STAT_INFO(i) (*(unsigned int *)(TX_STAT_BASE + 4*i))\r
+#define RX_BUF(i) (RX_BUF_BASE + ETH_FRAG_SIZE*i)\r
+#define TX_BUF(i) (TX_BUF_BASE + ETH_FRAG_SIZE*i)\r
+\r
+/* MAC Configuration Register 1 */\r
+#define MAC1_REC_EN 0x00000001 /* Receive Enable */\r
+#define MAC1_PASS_ALL 0x00000002 /* Pass All Receive Frames */\r
+#define MAC1_RX_FLOWC 0x00000004 /* RX Flow Control */\r
+#define MAC1_TX_FLOWC 0x00000008 /* TX Flow Control */\r
+#define MAC1_LOOPB 0x00000010 /* Loop Back Mode */\r
+#define MAC1_RES_TX 0x00000100 /* Reset TX Logic */\r
+#define MAC1_RES_MCS_TX 0x00000200 /* Reset MAC TX Control Sublayer */\r
+#define MAC1_RES_RX 0x00000400 /* Reset RX Logic */\r
+#define MAC1_RES_MCS_RX 0x00000800 /* Reset MAC RX Control Sublayer */\r
+#define MAC1_SIM_RES 0x00004000 /* Simulation Reset */\r
+#define MAC1_SOFT_RES 0x00008000 /* Soft Reset MAC */\r
+\r
+/* MAC Configuration Register 2 */\r
+#define MAC2_FULL_DUP 0x00000001 /* Full Duplex Mode */\r
+#define MAC2_FRM_LEN_CHK 0x00000002 /* Frame Length Checking */\r
+#define MAC2_HUGE_FRM_EN 0x00000004 /* Huge Frame Enable */\r
+#define MAC2_DLY_CRC 0x00000008 /* Delayed CRC Mode */\r
+#define MAC2_CRC_EN 0x00000010 /* Append CRC to every Frame */\r
+#define MAC2_PAD_EN 0x00000020 /* Pad all Short Frames */\r
+#define MAC2_VLAN_PAD_EN 0x00000040 /* VLAN Pad Enable */\r
+#define MAC2_ADET_PAD_EN 0x00000080 /* Auto Detect Pad Enable */\r
+#define MAC2_PPREAM_ENF 0x00000100 /* Pure Preamble Enforcement */\r
+#define MAC2_LPREAM_ENF 0x00000200 /* Long Preamble Enforcement */\r
+#undef MAC2_NO_BACKOFF /* Remove compiler warning. */\r
+#define MAC2_NO_BACKOFF 0x00001000 /* No Backoff Algorithm */\r
+#define MAC2_BACK_PRESSURE 0x00002000 /* Backoff Presurre / No Backoff */\r
+#define MAC2_EXCESS_DEF 0x00004000 /* Excess Defer */\r
+\r
+/* Back-to-Back Inter-Packet-Gap Register */\r
+#define IPGT_FULL_DUP 0x00000015 /* Recommended value for Full Duplex */\r
+#define IPGT_HALF_DUP 0x00000012 /* Recommended value for Half Duplex */\r
+\r
+/* Non Back-to-Back Inter-Packet-Gap Register */\r
+#define IPGR_DEF 0x00000012 /* Recommended value */\r
+\r
+/* Collision Window/Retry Register */\r
+#define CLRT_DEF 0x0000370F /* Default value */\r
+\r
+/* PHY Support Register */\r
+#undef SUPP_SPEED /* Remove compiler warning. */\r
+#define SUPP_SPEED 0x00000100 /* Reduced MII Logic Current Speed */\r
+#define SUPP_RES_RMII 0x00000800 /* Reset Reduced MII Logic */\r
+\r
+/* Test Register */\r
+#define TEST_SHCUT_PQUANTA 0x00000001 /* Shortcut Pause Quanta */\r
+#define TEST_TST_PAUSE 0x00000002 /* Test Pause */\r
+#define TEST_TST_BACKP 0x00000004 /* Test Back Pressure */\r
+\r
+/* MII Management Configuration Register */\r
+#define MCFG_SCAN_INC 0x00000001 /* Scan Increment PHY Address */\r
+#define MCFG_SUPP_PREAM 0x00000002 /* Suppress Preamble */\r
+#define MCFG_CLK_SEL 0x0000001C /* Clock Select Mask */\r
+#define MCFG_RES_MII 0x00008000 /* Reset MII Management Hardware */\r
+\r
+/* MII Management Command Register */\r
+#undef MCMD_READ /* Remove compiler warning. */\r
+#define MCMD_READ 0x00000001 /* MII Read */\r
+#undef MCMD_SCAN /* Remove compiler warning. */\r
+#define MCMD_SCAN 0x00000002 /* MII Scan continuously */\r
+\r
+#define MII_WR_TOUT 0x00050000 /* MII Write timeout count */\r
+#define MII_RD_TOUT 0x00050000 /* MII Read timeout count */\r
+\r
+/* MII Management Address Register */\r
+#define MADR_REG_ADR 0x0000001F /* MII Register Address Mask */\r
+#define MADR_PHY_ADR 0x00001F00 /* PHY Address Mask */\r
+\r
+/* MII Management Indicators Register */\r
+#undef MIND_BUSY /* Remove compiler warning. */\r
+#define MIND_BUSY 0x00000001 /* MII is Busy */\r
+#define MIND_SCAN 0x00000002 /* MII Scanning in Progress */\r
+#define MIND_NOT_VAL 0x00000004 /* MII Read Data not valid */\r
+#define MIND_MII_LINK_FAIL 0x00000008 /* MII Link Failed */\r
+\r
+/* Command Register */\r
+#define CR_RX_EN 0x00000001 /* Enable Receive */\r
+#define CR_TX_EN 0x00000002 /* Enable Transmit */\r
+#define CR_REG_RES 0x00000008 /* Reset Host Registers */\r
+#define CR_TX_RES 0x00000010 /* Reset Transmit Datapath */\r
+#define CR_RX_RES 0x00000020 /* Reset Receive Datapath */\r
+#define CR_PASS_RUNT_FRM 0x00000040 /* Pass Runt Frames */\r
+#define CR_PASS_RX_FILT 0x00000080 /* Pass RX Filter */\r
+#define CR_TX_FLOW_CTRL 0x00000100 /* TX Flow Control */\r
+#define CR_RMII 0x00000200 /* Reduced MII Interface */\r
+#define CR_FULL_DUP 0x00000400 /* Full Duplex */\r
+\r
+/* Status Register */\r
+#define SR_RX_EN 0x00000001 /* Enable Receive */\r
+#define SR_TX_EN 0x00000002 /* Enable Transmit */\r
+\r
+/* Transmit Status Vector 0 Register */\r
+#define TSV0_CRC_ERR 0x00000001 /* CRC error */\r
+#define TSV0_LEN_CHKERR 0x00000002 /* Length Check Error */\r
+#define TSV0_LEN_OUTRNG 0x00000004 /* Length Out of Range */\r
+#define TSV0_DONE 0x00000008 /* Tramsmission Completed */\r
+#define TSV0_MCAST 0x00000010 /* Multicast Destination */\r
+#define TSV0_BCAST 0x00000020 /* Broadcast Destination */\r
+#define TSV0_PKT_DEFER 0x00000040 /* Packet Deferred */\r
+#define TSV0_EXC_DEFER 0x00000080 /* Excessive Packet Deferral */\r
+#define TSV0_EXC_COLL 0x00000100 /* Excessive Collision */\r
+#define TSV0_LATE_COLL 0x00000200 /* Late Collision Occured */\r
+#define TSV0_GIANT 0x00000400 /* Giant Frame */\r
+#define TSV0_UNDERRUN 0x00000800 /* Buffer Underrun */\r
+#define TSV0_BYTES 0x0FFFF000 /* Total Bytes Transferred */\r
+#define TSV0_CTRL_FRAME 0x10000000 /* Control Frame */\r
+#define TSV0_PAUSE 0x20000000 /* Pause Frame */\r
+#define TSV0_BACK_PRESS 0x40000000 /* Backpressure Method Applied */\r
+#define TSV0_VLAN 0x80000000 /* VLAN Frame */\r
+\r
+/* Transmit Status Vector 1 Register */\r
+#define TSV1_BYTE_CNT 0x0000FFFF /* Transmit Byte Count */\r
+#define TSV1_COLL_CNT 0x000F0000 /* Transmit Collision Count */\r
+\r
+/* Receive Status Vector Register */\r
+#define RSV_BYTE_CNT 0x0000FFFF /* Receive Byte Count */\r
+#define RSV_PKT_IGNORED 0x00010000 /* Packet Previously Ignored */\r
+#define RSV_RXDV_SEEN 0x00020000 /* RXDV Event Previously Seen */\r
+#define RSV_CARR_SEEN 0x00040000 /* Carrier Event Previously Seen */\r
+#define RSV_REC_CODEV 0x00080000 /* Receive Code Violation */\r
+#define RSV_CRC_ERR 0x00100000 /* CRC Error */\r
+#define RSV_LEN_CHKERR 0x00200000 /* Length Check Error */\r
+#define RSV_LEN_OUTRNG 0x00400000 /* Length Out of Range */\r
+#define RSV_REC_OK 0x00800000 /* Frame Received OK */\r
+#define RSV_MCAST 0x01000000 /* Multicast Frame */\r
+#define RSV_BCAST 0x02000000 /* Broadcast Frame */\r
+#define RSV_DRIB_NIBB 0x04000000 /* Dribble Nibble */\r
+#define RSV_CTRL_FRAME 0x08000000 /* Control Frame */\r
+#define RSV_PAUSE 0x10000000 /* Pause Frame */\r
+#define RSV_UNSUPP_OPC 0x20000000 /* Unsupported Opcode */\r
+#define RSV_VLAN 0x40000000 /* VLAN Frame */\r
+\r
+/* Flow Control Counter Register */\r
+#define FCC_MIRR_CNT 0x0000FFFF /* Mirror Counter */\r
+#define FCC_PAUSE_TIM 0xFFFF0000 /* Pause Timer */\r
+\r
+/* Flow Control Status Register */\r
+#define FCS_MIRR_CNT 0x0000FFFF /* Mirror Counter Current */\r
+\r
+/* Receive Filter Control Register */\r
+#define RFC_UCAST_EN 0x00000001 /* Accept Unicast Frames Enable */\r
+#define RFC_BCAST_EN 0x00000002 /* Accept Broadcast Frames Enable */\r
+#define RFC_MCAST_EN 0x00000004 /* Accept Multicast Frames Enable */\r
+#define RFC_UCAST_HASH_EN 0x00000008 /* Accept Unicast Hash Filter Frames */\r
+#define RFC_MCAST_HASH_EN 0x00000010 /* Accept Multicast Hash Filter Fram.*/\r
+#define RFC_PERFECT_EN 0x00000020 /* Accept Perfect Match Enable */\r
+#define RFC_MAGP_WOL_EN 0x00001000 /* Magic Packet Filter WoL Enable */\r
+#define RFC_PFILT_WOL_EN 0x00002000 /* Perfect Filter WoL Enable */\r
+\r
+/* Receive Filter WoL Status/Clear Registers */\r
+#define WOL_UCAST 0x00000001 /* Unicast Frame caused WoL */\r
+#define WOL_BCAST 0x00000002 /* Broadcast Frame caused WoL */\r
+#define WOL_MCAST 0x00000004 /* Multicast Frame caused WoL */\r
+#define WOL_UCAST_HASH 0x00000008 /* Unicast Hash Filter Frame WoL */\r
+#define WOL_MCAST_HASH 0x00000010 /* Multicast Hash Filter Frame WoL */\r
+#define WOL_PERFECT 0x00000020 /* Perfect Filter WoL */\r
+#define WOL_RX_FILTER 0x00000080 /* RX Filter caused WoL */\r
+#define WOL_MAG_PACKET 0x00000100 /* Magic Packet Filter caused WoL */\r
+\r
+/* Interrupt Status/Enable/Clear/Set Registers */\r
+#define INT_RX_OVERRUN 0x00000001 /* Overrun Error in RX Queue */\r
+#define INT_RX_ERR 0x00000002 /* Receive Error */\r
+#define INT_RX_FIN 0x00000004 /* RX Finished Process Descriptors */\r
+#define INT_RX_DONE 0x00000008 /* Receive Done */\r
+#define INT_TX_UNDERRUN 0x00000010 /* Transmit Underrun */\r
+#define INT_TX_ERR 0x00000020 /* Transmit Error */\r
+#define INT_TX_FIN 0x00000040 /* TX Finished Process Descriptors */\r
+#define INT_TX_DONE 0x00000080 /* Transmit Done */\r
+#define INT_SOFT_INT 0x00001000 /* Software Triggered Interrupt */\r
+#define INT_WAKEUP 0x00002000 /* Wakeup Event Interrupt */\r
+\r
+/* Power Down Register */\r
+#define PD_POWER_DOWN 0x80000000 /* Power Down MAC */\r
+\r
+/* RX Descriptor Control Word */\r
+#define RCTRL_SIZE 0x000007FF /* Buffer size mask */\r
+#define RCTRL_INT 0x80000000 /* Generate RxDone Interrupt */\r
+\r
+/* RX Status Hash CRC Word */\r
+#define RHASH_SA 0x000001FF /* Hash CRC for Source Address */\r
+#define RHASH_DA 0x001FF000 /* Hash CRC for Destination Address */\r
+\r
+/* RX Status Information Word */\r
+#define RINFO_SIZE 0x000007FF /* Data size in bytes */\r
+#define RINFO_CTRL_FRAME 0x00040000 /* Control Frame */\r
+#define RINFO_VLAN 0x00080000 /* VLAN Frame */\r
+#define RINFO_FAIL_FILT 0x00100000 /* RX Filter Failed */\r
+#define RINFO_MCAST 0x00200000 /* Multicast Frame */\r
+#define RINFO_BCAST 0x00400000 /* Broadcast Frame */\r
+#define RINFO_CRC_ERR 0x00800000 /* CRC Error in Frame */\r
+#define RINFO_SYM_ERR 0x01000000 /* Symbol Error from PHY */\r
+#define RINFO_LEN_ERR 0x02000000 /* Length Error */\r
+#define RINFO_RANGE_ERR 0x04000000 /* Range Error (exceeded max. size) */\r
+#define RINFO_ALIGN_ERR 0x08000000 /* Alignment Error */\r
+#define RINFO_OVERRUN 0x10000000 /* Receive overrun */\r
+#define RINFO_NO_DESCR 0x20000000 /* No new Descriptor available */\r
+#define RINFO_LAST_FLAG 0x40000000 /* Last Fragment in Frame */\r
+#define RINFO_ERR 0x80000000 /* Error Occured (OR of all errors) */\r
+\r
+#define RINFO_ERR_MASK (RINFO_FAIL_FILT | RINFO_CRC_ERR | RINFO_SYM_ERR | \\r
+ RINFO_LEN_ERR | RINFO_ALIGN_ERR | RINFO_OVERRUN)\r
+\r
+/* TX Descriptor Control Word */\r
+#define TCTRL_SIZE 0x000007FF /* Size of data buffer in bytes */\r
+#define TCTRL_OVERRIDE 0x04000000 /* Override Default MAC Registers */\r
+#define TCTRL_HUGE 0x08000000 /* Enable Huge Frame */\r
+#define TCTRL_PAD 0x10000000 /* Pad short Frames to 64 bytes */\r
+#define TCTRL_CRC 0x20000000 /* Append a hardware CRC to Frame */\r
+#define TCTRL_LAST 0x40000000 /* Last Descriptor for TX Frame */\r
+#define TCTRL_INT 0x80000000 /* Generate TxDone Interrupt */\r
+\r
+/* TX Status Information Word */\r
+#define TINFO_COL_CNT 0x01E00000 /* Collision Count */\r
+#define TINFO_DEFER 0x02000000 /* Packet Deferred (not an error) */\r
+#define TINFO_EXCESS_DEF 0x04000000 /* Excessive Deferral */\r
+#define TINFO_EXCESS_COL 0x08000000 /* Excessive Collision */\r
+#define TINFO_LATE_COL 0x10000000 /* Late Collision Occured */\r
+#define TINFO_UNDERRUN 0x20000000 /* Transmit Underrun */\r
+#define TINFO_NO_DESCR 0x40000000 /* No new Descriptor available */\r
+#define TINFO_ERR 0x80000000 /* Error Occured (OR of all errors) */\r
+\r
+/* DP83848C PHY Registers */\r
+#define PHY_REG_BMCR 0x00 /* Basic Mode Control Register */\r
+#define PHY_REG_BMSR 0x01 /* Basic Mode Status Register */\r
+#define PHY_REG_IDR1 0x02 /* PHY Identifier 1 */\r
+#define PHY_REG_IDR2 0x03 /* PHY Identifier 2 */\r
+#define PHY_REG_ANAR 0x04 /* Auto-Negotiation Advertisement */\r
+#define PHY_REG_ANLPAR 0x05 /* Auto-Neg. Link Partner Abitily */\r
+#define PHY_REG_ANER 0x06 /* Auto-Neg. Expansion Register */\r
+#define PHY_REG_ANNPTR 0x07 /* Auto-Neg. Next Page TX */\r
+\r
+/* PHY Extended Registers */\r
+#define PHY_REG_STS 0x10 /* Status Register */\r
+#define PHY_REG_MICR 0x11 /* MII Interrupt Control Register */\r
+#define PHY_REG_MISR 0x12 /* MII Interrupt Status Register */\r
+#define PHY_REG_FCSCR 0x14 /* False Carrier Sense Counter */\r
+#define PHY_REG_RECR 0x15 /* Receive Error Counter */\r
+#define PHY_REG_PCSR 0x16 /* PCS Sublayer Config. and Status */\r
+#define PHY_REG_RBR 0x17 /* RMII and Bypass Register */\r
+#define PHY_REG_LEDCR 0x18 /* LED Direct Control Register */\r
+#define PHY_REG_PHYCR 0x19 /* PHY Control Register */\r
+#define PHY_REG_10BTSCR 0x1A /* 10Base-T Status/Control Register */\r
+#define PHY_REG_CDCTRL1 0x1B /* CD Test Control and BIST Extens. */\r
+#define PHY_REG_EDCR 0x1D /* Energy Detect Control Register */\r
+\r
+#define PHY_FULLD_100M 0x2100 /* Full Duplex 100Mbit */\r
+#define PHY_HALFD_100M 0x2000 /* Half Duplex 100Mbit */\r
+#define PHY_FULLD_10M 0x0100 /* Full Duplex 10Mbit */\r
+#define PHY_HALFD_10M 0x0000 /* Half Duplex 10MBit */\r
+#define PHY_AUTO_NEG 0x3000 /* Select Auto Negotiation */\r
+\r
+#define DP83848C_DEF_ADR 0x0100 /* Default PHY device address */\r
+#define DP83848C_ID 0x20005C90 /* PHY Identifier */\r
+\r
+// prototypes\r
+portBASE_TYPE vInitEMAC(void);\r
+unsigned short ReadFrameBE_EMAC(void);\r
+void vIncrementTxLength(unsigned long ulLength);\r
+void CopyFromFrame_EMAC(void *Dest, unsigned short Size);\r
+void DummyReadFrame_EMAC(unsigned short Size);\r
+unsigned short StartReadFrame(void);\r
+void EndReadFrame(void);\r
+unsigned int CheckFrameReceived(void);\r
+void vInitialiseSend(void);\r
+unsigned int Rdy4Tx(void);\r
+void vSendBufferToMAC(void);\r
+void vEMACWaitForInput( void );\r
+unsigned int uiGetEMACRxData( unsigned char *ucBuffer );\r
+\r
+\r
+#endif\r
+\r
+/*----------------------------------------------------------------------------\r
+ * end of file\r
+ *---------------------------------------------------------------------------*/\r
+\r
--- /dev/null
+http_http "http://"\r
+http_200 "200 "\r
+http_301 "301 "\r
+http_302 "302 "\r
+http_get "GET "\r
+http_10 "HTTP/1.0"\r
+http_11 "HTTP/1.1"\r
+http_content_type "content-type: "\r
+http_texthtml "text/html"\r
+http_location "location: "\r
+http_host "host: "\r
+http_crnl "\r\n"\r
+http_index_html "/index.html"\r
+http_404_html "/404.html"\r
+http_referer "Referer:"\r
+http_header_200 "HTTP/1.0 200 OK\r\nServer: uIP/1.0 http://www.sics.se/~adam/uip/\r\nConnection: close\r\n"\r
+http_header_404 "HTTP/1.0 404 Not found\r\nServer: uIP/1.0 http://www.sics.se/~adam/uip/\r\nConnection: close\r\n"\r
+http_content_type_plain "Content-type: text/plain\r\n\r\n"\r
+http_content_type_html "Content-type: text/html\r\n\r\n"\r
+http_content_type_css "Content-type: text/css\r\n\r\n"\r
+http_content_type_text "Content-type: text/text\r\n\r\n"\r
+http_content_type_png "Content-type: image/png\r\n\r\n"\r
+http_content_type_gif "Content-type: image/gif\r\n\r\n"\r
+http_content_type_jpg "Content-type: image/jpeg\r\n\r\n"\r
+http_content_type_binary "Content-type: application/octet-stream\r\n\r\n"\r
+http_html ".html"\r
+http_shtml ".shtml"\r
+http_htm ".htm"\r
+http_css ".css"\r
+http_png ".png"\r
+http_gif ".gif"\r
+http_jpg ".jpg"\r
+http_text ".txt"\r
+http_txt ".txt"\r
+\r
--- /dev/null
+const char http_http[8] = \r
+/* "http://" */\r
+{0x68, 0x74, 0x74, 0x70, 0x3a, 0x2f, 0x2f, };\r
+const char http_200[5] = \r
+/* "200 " */\r
+{0x32, 0x30, 0x30, 0x20, };\r
+const char http_301[5] = \r
+/* "301 " */\r
+{0x33, 0x30, 0x31, 0x20, };\r
+const char http_302[5] = \r
+/* "302 " */\r
+{0x33, 0x30, 0x32, 0x20, };\r
+const char http_get[5] = \r
+/* "GET " */\r
+{0x47, 0x45, 0x54, 0x20, };\r
+const char http_10[9] = \r
+/* "HTTP/1.0" */\r
+{0x48, 0x54, 0x54, 0x50, 0x2f, 0x31, 0x2e, 0x30, };\r
+const char http_11[9] = \r
+/* "HTTP/1.1" */\r
+{0x48, 0x54, 0x54, 0x50, 0x2f, 0x31, 0x2e, 0x31, };\r
+const char http_content_type[15] = \r
+/* "content-type: " */\r
+{0x63, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, };\r
+const char http_texthtml[10] = \r
+/* "text/html" */\r
+{0x74, 0x65, 0x78, 0x74, 0x2f, 0x68, 0x74, 0x6d, 0x6c, };\r
+const char http_location[11] = \r
+/* "location: " */\r
+{0x6c, 0x6f, 0x63, 0x61, 0x74, 0x69, 0x6f, 0x6e, 0x3a, 0x20, };\r
+const char http_host[7] = \r
+/* "host: " */\r
+{0x68, 0x6f, 0x73, 0x74, 0x3a, 0x20, };\r
+const char http_crnl[3] = \r
+/* "\r\n" */\r
+{0xd, 0xa, };\r
+const char http_index_html[12] = \r
+/* "/index.html" */\r
+{0x2f, 0x69, 0x6e, 0x64, 0x65, 0x78, 0x2e, 0x68, 0x74, 0x6d, 0x6c, };\r
+const char http_404_html[10] = \r
+/* "/404.html" */\r
+{0x2f, 0x34, 0x30, 0x34, 0x2e, 0x68, 0x74, 0x6d, 0x6c, };\r
+const char http_referer[9] = \r
+/* "Referer:" */\r
+{0x52, 0x65, 0x66, 0x65, 0x72, 0x65, 0x72, 0x3a, };\r
+const char http_header_200[84] = \r
+/* "HTTP/1.0 200 OK\r\nServer: uIP/1.0 http://www.sics.se/~adam/uip/\r\nConnection: close\r\n" */\r
+{0x48, 0x54, 0x54, 0x50, 0x2f, 0x31, 0x2e, 0x30, 0x20, 0x32, 0x30, 0x30, 0x20, 0x4f, 0x4b, 0xd, 0xa, 0x53, 0x65, 0x72, 0x76, 0x65, 0x72, 0x3a, 0x20, 0x75, 0x49, 0x50, 0x2f, 0x31, 0x2e, 0x30, 0x20, 0x68, 0x74, 0x74, 0x70, 0x3a, 0x2f, 0x2f, 0x77, 0x77, 0x77, 0x2e, 0x73, 0x69, 0x63, 0x73, 0x2e, 0x73, 0x65, 0x2f, 0x7e, 0x61, 0x64, 0x61, 0x6d, 0x2f, 0x75, 0x69, 0x70, 0x2f, 0xd, 0xa, 0x43, 0x6f, 0x6e, 0x6e, 0x65, 0x63, 0x74, 0x69, 0x6f, 0x6e, 0x3a, 0x20, 0x63, 0x6c, 0x6f, 0x73, 0x65, 0xd, 0xa, };\r
+const char http_header_404[91] = \r
+/* "HTTP/1.0 404 Not found\r\nServer: uIP/1.0 http://www.sics.se/~adam/uip/\r\nConnection: close\r\n" */\r
+{0x48, 0x54, 0x54, 0x50, 0x2f, 0x31, 0x2e, 0x30, 0x20, 0x34, 0x30, 0x34, 0x20, 0x4e, 0x6f, 0x74, 0x20, 0x66, 0x6f, 0x75, 0x6e, 0x64, 0xd, 0xa, 0x53, 0x65, 0x72, 0x76, 0x65, 0x72, 0x3a, 0x20, 0x75, 0x49, 0x50, 0x2f, 0x31, 0x2e, 0x30, 0x20, 0x68, 0x74, 0x74, 0x70, 0x3a, 0x2f, 0x2f, 0x77, 0x77, 0x77, 0x2e, 0x73, 0x69, 0x63, 0x73, 0x2e, 0x73, 0x65, 0x2f, 0x7e, 0x61, 0x64, 0x61, 0x6d, 0x2f, 0x75, 0x69, 0x70, 0x2f, 0xd, 0xa, 0x43, 0x6f, 0x6e, 0x6e, 0x65, 0x63, 0x74, 0x69, 0x6f, 0x6e, 0x3a, 0x20, 0x63, 0x6c, 0x6f, 0x73, 0x65, 0xd, 0xa, };\r
+const char http_content_type_plain[29] = \r
+/* "Content-type: text/plain\r\n\r\n" */\r
+{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x74, 0x65, 0x78, 0x74, 0x2f, 0x70, 0x6c, 0x61, 0x69, 0x6e, 0xd, 0xa, 0xd, 0xa, };\r
+const char http_content_type_html[28] = \r
+/* "Content-type: text/html\r\n\r\n" */\r
+{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x74, 0x65, 0x78, 0x74, 0x2f, 0x68, 0x74, 0x6d, 0x6c, 0xd, 0xa, 0xd, 0xa, };\r
+const char http_content_type_css [27] = \r
+/* "Content-type: text/css\r\n\r\n" */\r
+{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x74, 0x65, 0x78, 0x74, 0x2f, 0x63, 0x73, 0x73, 0xd, 0xa, 0xd, 0xa, };\r
+const char http_content_type_text[28] = \r
+/* "Content-type: text/text\r\n\r\n" */\r
+{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x74, 0x65, 0x78, 0x74, 0x2f, 0x74, 0x65, 0x78, 0x74, 0xd, 0xa, 0xd, 0xa, };\r
+const char http_content_type_png [28] = \r
+/* "Content-type: image/png\r\n\r\n" */\r
+{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x69, 0x6d, 0x61, 0x67, 0x65, 0x2f, 0x70, 0x6e, 0x67, 0xd, 0xa, 0xd, 0xa, };\r
+const char http_content_type_gif [28] = \r
+/* "Content-type: image/gif\r\n\r\n" */\r
+{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x69, 0x6d, 0x61, 0x67, 0x65, 0x2f, 0x67, 0x69, 0x66, 0xd, 0xa, 0xd, 0xa, };\r
+const char http_content_type_jpg [29] = \r
+/* "Content-type: image/jpeg\r\n\r\n" */\r
+{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x69, 0x6d, 0x61, 0x67, 0x65, 0x2f, 0x6a, 0x70, 0x65, 0x67, 0xd, 0xa, 0xd, 0xa, };\r
+const char http_content_type_binary[43] = \r
+/* "Content-type: application/octet-stream\r\n\r\n" */\r
+{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x61, 0x70, 0x70, 0x6c, 0x69, 0x63, 0x61, 0x74, 0x69, 0x6f, 0x6e, 0x2f, 0x6f, 0x63, 0x74, 0x65, 0x74, 0x2d, 0x73, 0x74, 0x72, 0x65, 0x61, 0x6d, 0xd, 0xa, 0xd, 0xa, };\r
+const char http_html[6] = \r
+/* ".html" */\r
+{0x2e, 0x68, 0x74, 0x6d, 0x6c, };\r
+const char http_shtml[7] = \r
+/* ".shtml" */\r
+{0x2e, 0x73, 0x68, 0x74, 0x6d, 0x6c, };\r
+const char http_htm[5] = \r
+/* ".htm" */\r
+{0x2e, 0x68, 0x74, 0x6d, };\r
+const char http_css[5] = \r
+/* ".css" */\r
+{0x2e, 0x63, 0x73, 0x73, };\r
+const char http_png[5] = \r
+/* ".png" */\r
+{0x2e, 0x70, 0x6e, 0x67, };\r
+const char http_gif[5] = \r
+/* ".gif" */\r
+{0x2e, 0x67, 0x69, 0x66, };\r
+const char http_jpg[5] = \r
+/* ".jpg" */\r
+{0x2e, 0x6a, 0x70, 0x67, };\r
+const char http_text[5] = \r
+/* ".txt" */\r
+{0x2e, 0x74, 0x78, 0x74, };\r
+const char http_txt[5] = \r
+/* ".txt" */\r
+{0x2e, 0x74, 0x78, 0x74, };\r
--- /dev/null
+extern const char http_http[8];\r
+extern const char http_200[5];\r
+extern const char http_301[5];\r
+extern const char http_302[5];\r
+extern const char http_get[5];\r
+extern const char http_10[9];\r
+extern const char http_11[9];\r
+extern const char http_content_type[15];\r
+extern const char http_texthtml[10];\r
+extern const char http_location[11];\r
+extern const char http_host[7];\r
+extern const char http_crnl[3];\r
+extern const char http_index_html[12];\r
+extern const char http_404_html[10];\r
+extern const char http_referer[9];\r
+extern const char http_header_200[84];\r
+extern const char http_header_404[91];\r
+extern const char http_content_type_plain[29];\r
+extern const char http_content_type_html[28];\r
+extern const char http_content_type_css [27];\r
+extern const char http_content_type_text[28];\r
+extern const char http_content_type_png [28];\r
+extern const char http_content_type_gif [28];\r
+extern const char http_content_type_jpg [29];\r
+extern const char http_content_type_binary[43];\r
+extern const char http_html[6];\r
+extern const char http_shtml[7];\r
+extern const char http_htm[5];\r
+extern const char http_css[5];\r
+extern const char http_png[5];\r
+extern const char http_gif[5];\r
+extern const char http_jpg[5];\r
+extern const char http_text[5];\r
+extern const char http_txt[5];\r
--- /dev/null
+/**\r
+ * \addtogroup httpd\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * \file\r
+ * Web server script interface\r
+ * \author\r
+ * Adam Dunkels <adam@sics.se>\r
+ *\r
+ */\r
+\r
+/*\r
+ * Copyright (c) 2001-2006, Adam Dunkels.\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ * 1. Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the\r
+ * documentation and/or other materials provided with the distribution.\r
+ * 3. The name of the author may not be used to endorse or promote\r
+ * products derived from this software without specific prior\r
+ * written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS\r
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\r
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY\r
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE\r
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\r
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\r
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * This file is part of the uIP TCP/IP stack.\r
+ *\r
+ * $Id: httpd-cgi.c,v 1.2 2006/06/11 21:46:37 adam Exp $\r
+ *\r
+ */\r
+\r
+#include "uip.h"\r
+#include "psock.h"\r
+#include "httpd.h"\r
+#include "httpd-cgi.h"\r
+#include "httpd-fs.h"\r
+\r
+#include <stdio.h>\r
+#include <string.h>\r
+\r
+HTTPD_CGI_CALL(file, "file-stats", file_stats);\r
+HTTPD_CGI_CALL(tcp, "tcp-connections", tcp_stats);\r
+HTTPD_CGI_CALL(net, "net-stats", net_stats);\r
+HTTPD_CGI_CALL(rtos, "rtos-stats", rtos_stats );\r
+HTTPD_CGI_CALL(io, "led-io", led_io );\r
+\r
+\r
+static const struct httpd_cgi_call *calls[] = { &file, &tcp, &net, &rtos, &io, NULL };\r
+\r
+/*---------------------------------------------------------------------------*/\r
+static\r
+PT_THREAD(nullfunction(struct httpd_state *s, char *ptr))\r
+{\r
+ PSOCK_BEGIN(&s->sout);\r
+ PSOCK_END(&s->sout);\r
+}\r
+/*---------------------------------------------------------------------------*/\r
+httpd_cgifunction\r
+httpd_cgi(char *name)\r
+{\r
+ const struct httpd_cgi_call **f;\r
+\r
+ /* Find the matching name in the table, return the function. */\r
+ for(f = calls; *f != NULL; ++f) {\r
+ if(strncmp((*f)->name, name, strlen((*f)->name)) == 0) {\r
+ return (*f)->function;\r
+ }\r
+ }\r
+ return nullfunction;\r
+}\r
+/*---------------------------------------------------------------------------*/\r
+static unsigned short\r
+generate_file_stats(void *arg)\r
+{\r
+ char *f = (char *)arg;\r
+ return snprintf((char *)uip_appdata, UIP_APPDATA_SIZE, "%5u", httpd_fs_count(f));\r
+}\r
+/*---------------------------------------------------------------------------*/\r
+static\r
+PT_THREAD(file_stats(struct httpd_state *s, char *ptr))\r
+{\r
+ PSOCK_BEGIN(&s->sout);\r
+\r
+ PSOCK_GENERATOR_SEND(&s->sout, generate_file_stats, strchr(ptr, ' ') + 1);\r
+\r
+ PSOCK_END(&s->sout);\r
+}\r
+/*---------------------------------------------------------------------------*/\r
+static const char closed[] = /* "CLOSED",*/\r
+{0x43, 0x4c, 0x4f, 0x53, 0x45, 0x44, 0};\r
+static const char syn_rcvd[] = /* "SYN-RCVD",*/\r
+{0x53, 0x59, 0x4e, 0x2d, 0x52, 0x43, 0x56,\r
+ 0x44, 0};\r
+static const char syn_sent[] = /* "SYN-SENT",*/\r
+{0x53, 0x59, 0x4e, 0x2d, 0x53, 0x45, 0x4e,\r
+ 0x54, 0};\r
+static const char established[] = /* "ESTABLISHED",*/\r
+{0x45, 0x53, 0x54, 0x41, 0x42, 0x4c, 0x49, 0x53, 0x48,\r
+ 0x45, 0x44, 0};\r
+static const char fin_wait_1[] = /* "FIN-WAIT-1",*/\r
+{0x46, 0x49, 0x4e, 0x2d, 0x57, 0x41, 0x49,\r
+ 0x54, 0x2d, 0x31, 0};\r
+static const char fin_wait_2[] = /* "FIN-WAIT-2",*/\r
+{0x46, 0x49, 0x4e, 0x2d, 0x57, 0x41, 0x49,\r
+ 0x54, 0x2d, 0x32, 0};\r
+static const char closing[] = /* "CLOSING",*/\r
+{0x43, 0x4c, 0x4f, 0x53, 0x49,\r
+ 0x4e, 0x47, 0};\r
+static const char time_wait[] = /* "TIME-WAIT,"*/\r
+{0x54, 0x49, 0x4d, 0x45, 0x2d, 0x57, 0x41,\r
+ 0x49, 0x54, 0};\r
+static const char last_ack[] = /* "LAST-ACK"*/\r
+{0x4c, 0x41, 0x53, 0x54, 0x2d, 0x41, 0x43,\r
+ 0x4b, 0};\r
+\r
+static const char *states[] = {\r
+ closed,\r
+ syn_rcvd,\r
+ syn_sent,\r
+ established,\r
+ fin_wait_1,\r
+ fin_wait_2,\r
+ closing,\r
+ time_wait,\r
+ last_ack};\r
+\r
+\r
+static unsigned short\r
+generate_tcp_stats(void *arg)\r
+{\r
+ struct uip_conn *conn;\r
+ struct httpd_state *s = (struct httpd_state *)arg;\r
+\r
+ conn = &uip_conns[s->count];\r
+ return snprintf((char *)uip_appdata, UIP_APPDATA_SIZE,\r
+ "<tr><td>%d</td><td>%u.%u.%u.%u:%u</td><td>%s</td><td>%u</td><td>%u</td><td>%c %c</td></tr>\r\n",\r
+ htons(conn->lport),\r
+ htons(conn->ripaddr[0]) >> 8,\r
+ htons(conn->ripaddr[0]) & 0xff,\r
+ htons(conn->ripaddr[1]) >> 8,\r
+ htons(conn->ripaddr[1]) & 0xff,\r
+ htons(conn->rport),\r
+ states[conn->tcpstateflags & UIP_TS_MASK],\r
+ conn->nrtx,\r
+ conn->timer,\r
+ (uip_outstanding(conn))? '*':' ',\r
+ (uip_stopped(conn))? '!':' ');\r
+}\r
+/*---------------------------------------------------------------------------*/\r
+static\r
+PT_THREAD(tcp_stats(struct httpd_state *s, char *ptr))\r
+{\r
+\r
+ PSOCK_BEGIN(&s->sout);\r
+\r
+ for(s->count = 0; s->count < UIP_CONNS; ++s->count) {\r
+ if((uip_conns[s->count].tcpstateflags & UIP_TS_MASK) != UIP_CLOSED) {\r
+ PSOCK_GENERATOR_SEND(&s->sout, generate_tcp_stats, s);\r
+ }\r
+ }\r
+\r
+ PSOCK_END(&s->sout);\r
+}\r
+/*---------------------------------------------------------------------------*/\r
+static unsigned short\r
+generate_net_stats(void *arg)\r
+{\r
+ struct httpd_state *s = (struct httpd_state *)arg;\r
+ return snprintf((char *)uip_appdata, UIP_APPDATA_SIZE,\r
+ "%5u\n", ((uip_stats_t *)&uip_stat)[s->count]);\r
+}\r
+\r
+static\r
+PT_THREAD(net_stats(struct httpd_state *s, char *ptr))\r
+{\r
+ PSOCK_BEGIN(&s->sout);\r
+\r
+#if UIP_STATISTICS\r
+\r
+ for(s->count = 0; s->count < sizeof(uip_stat) / sizeof(uip_stats_t);\r
+ ++s->count) {\r
+ PSOCK_GENERATOR_SEND(&s->sout, generate_net_stats, s);\r
+ }\r
+\r
+#endif /* UIP_STATISTICS */\r
+\r
+ PSOCK_END(&s->sout);\r
+}\r
+/*---------------------------------------------------------------------------*/\r
+\r
+extern void vTaskList( signed char *pcWriteBuffer );\r
+static char cCountBuf[ 32 ];\r
+long lRefreshCount = 0;\r
+static unsigned short\r
+generate_rtos_stats(void *arg)\r
+{\r
+ lRefreshCount++;\r
+ sprintf( cCountBuf, "<p><br>Refresh count = %d", lRefreshCount );\r
+ vTaskList( uip_appdata );\r
+ strcat( uip_appdata, cCountBuf );\r
+\r
+ return strlen( uip_appdata );\r
+}\r
+/*---------------------------------------------------------------------------*/\r
+\r
+\r
+static\r
+PT_THREAD(rtos_stats(struct httpd_state *s, char *ptr))\r
+{\r
+ PSOCK_BEGIN(&s->sout);\r
+ PSOCK_GENERATOR_SEND(&s->sout, generate_rtos_stats, NULL);\r
+ PSOCK_END(&s->sout);\r
+}\r
+/*---------------------------------------------------------------------------*/\r
+\r
+char *pcStatus;\r
+extern unsigned long uxParTestGetLED( unsigned long uxLED );\r
+\r
+static unsigned short generate_io_state( void *arg )\r
+{\r
+ if( uxParTestGetLED( 0 ) )\r
+ {\r
+ pcStatus = "checked";\r
+ }\r
+ else\r
+ {\r
+ pcStatus = "";\r
+ }\r
+\r
+ sprintf( uip_appdata,\r
+ "<input type=\"checkbox\" name=\"LED0\" value=\"1\" %s>LED"\\r
+ "<p>"\\r
+ "<input type=\"text\" name=\"LCD\" value=\"Enter LCD text\" size=\"16\">",\r
+ pcStatus );\r
+\r
+ return strlen( uip_appdata );\r
+}\r
+/*---------------------------------------------------------------------------*/\r
+\r
+static PT_THREAD(led_io(struct httpd_state *s, char *ptr))\r
+{\r
+ PSOCK_BEGIN(&s->sout);\r
+ PSOCK_GENERATOR_SEND(&s->sout, generate_io_state, NULL);\r
+ PSOCK_END(&s->sout);\r
+}\r
+\r
+/** @} */\r
+\r
+\r
+\r
+\r
+\r
+\r
--- /dev/null
+/**\r
+ * \addtogroup httpd\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * \file\r
+ * Web server script interface header file\r
+ * \author\r
+ * Adam Dunkels <adam@sics.se>\r
+ *\r
+ */\r
+\r
+\r
+\r
+/*\r
+ * Copyright (c) 2001, Adam Dunkels.\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ * 1. Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the\r
+ * documentation and/or other materials provided with the distribution.\r
+ * 3. The name of the author may not be used to endorse or promote\r
+ * products derived from this software without specific prior\r
+ * written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS\r
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\r
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY\r
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE\r
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\r
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\r
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * This file is part of the uIP TCP/IP stack.\r
+ *\r
+ * $Id: httpd-cgi.h,v 1.2 2006/06/11 21:46:38 adam Exp $\r
+ *\r
+ */\r
+\r
+#ifndef __HTTPD_CGI_H__\r
+#define __HTTPD_CGI_H__\r
+\r
+#include "psock.h"\r
+#include "httpd.h"\r
+\r
+typedef PT_THREAD((* httpd_cgifunction)(struct httpd_state *, char *));\r
+\r
+httpd_cgifunction httpd_cgi(char *name);\r
+\r
+struct httpd_cgi_call {\r
+ const char *name;\r
+ const httpd_cgifunction function;\r
+};\r
+\r
+/**\r
+ * \brief HTTPD CGI function declaration\r
+ * \param name The C variable name of the function\r
+ * \param str The string name of the function, used in the script file\r
+ * \param function A pointer to the function that implements it\r
+ *\r
+ * This macro is used for declaring a HTTPD CGI\r
+ * function. This function is then added to the list of\r
+ * HTTPD CGI functions with the httpd_cgi_add() function.\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define HTTPD_CGI_CALL(name, str, function) \\r
+static PT_THREAD(function(struct httpd_state *, char *)); \\r
+static const struct httpd_cgi_call name = {str, function}\r
+\r
+void httpd_cgi_init(void);\r
+#endif /* __HTTPD_CGI_H__ */\r
+\r
+/** @} */\r
--- /dev/null
+/*\r
+ * Copyright (c) 2001, Swedish Institute of Computer Science.\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ * 1. Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the\r
+ * documentation and/or other materials provided with the distribution.\r
+ * 3. Neither the name of the Institute nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND\r
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\r
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\r
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\r
+ * SUCH DAMAGE.\r
+ *\r
+ * This file is part of the lwIP TCP/IP stack.\r
+ *\r
+ * Author: Adam Dunkels <adam@sics.se>\r
+ *\r
+ * $Id: httpd-fs.c,v 1.1 2006/06/07 09:13:08 adam Exp $\r
+ */\r
+\r
+#include "httpd.h"\r
+#include "httpd-fs.h"\r
+#include "httpd-fsdata.h"\r
+\r
+#ifndef NULL\r
+#define NULL 0\r
+#endif /* NULL */\r
+\r
+#include "httpd-fsdata.c"\r
+\r
+#if HTTPD_FS_STATISTICS\r
+static u16_t count[HTTPD_FS_NUMFILES];\r
+#endif /* HTTPD_FS_STATISTICS */\r
+\r
+/*-----------------------------------------------------------------------------------*/\r
+static u8_t\r
+httpd_fs_strcmp(const char *str1, const char *str2)\r
+{\r
+ u8_t i;\r
+ i = 0;\r
+ loop:\r
+\r
+ if(str2[i] == 0 ||\r
+ str1[i] == '\r' ||\r
+ str1[i] == '\n') {\r
+ return 0;\r
+ }\r
+\r
+ if(str1[i] != str2[i]) {\r
+ return 1;\r
+ }\r
+\r
+\r
+ ++i;\r
+ goto loop;\r
+}\r
+/*-----------------------------------------------------------------------------------*/\r
+int\r
+httpd_fs_open(const char *name, struct httpd_fs_file *file)\r
+{\r
+#if HTTPD_FS_STATISTICS\r
+ u16_t i = 0;\r
+#endif /* HTTPD_FS_STATISTICS */\r
+ struct httpd_fsdata_file_noconst *f;\r
+\r
+ for(f = (struct httpd_fsdata_file_noconst *)HTTPD_FS_ROOT;\r
+ f != NULL;\r
+ f = (struct httpd_fsdata_file_noconst *)f->next) {\r
+\r
+ if(httpd_fs_strcmp(name, f->name) == 0) {\r
+ file->data = f->data;\r
+ file->len = f->len;\r
+#if HTTPD_FS_STATISTICS\r
+ ++count[i];\r
+#endif /* HTTPD_FS_STATISTICS */\r
+ return 1;\r
+ }\r
+#if HTTPD_FS_STATISTICS\r
+ ++i;\r
+#endif /* HTTPD_FS_STATISTICS */\r
+\r
+ }\r
+ return 0;\r
+}\r
+/*-----------------------------------------------------------------------------------*/\r
+void\r
+httpd_fs_init(void)\r
+{\r
+#if HTTPD_FS_STATISTICS\r
+ u16_t i;\r
+ for(i = 0; i < HTTPD_FS_NUMFILES; i++) {\r
+ count[i] = 0;\r
+ }\r
+#endif /* HTTPD_FS_STATISTICS */\r
+}\r
+/*-----------------------------------------------------------------------------------*/\r
+#if HTTPD_FS_STATISTICS\r
+u16_t httpd_fs_count\r
+(char *name)\r
+{\r
+ struct httpd_fsdata_file_noconst *f;\r
+ u16_t i;\r
+\r
+ i = 0;\r
+ for(f = (struct httpd_fsdata_file_noconst *)HTTPD_FS_ROOT;\r
+ f != NULL;\r
+ f = (struct httpd_fsdata_file_noconst *)f->next) {\r
+\r
+ if(httpd_fs_strcmp(name, f->name) == 0) {\r
+ return count[i];\r
+ }\r
+ ++i;\r
+ }\r
+ return 0;\r
+}\r
+#endif /* HTTPD_FS_STATISTICS */\r
+/*-----------------------------------------------------------------------------------*/\r
--- /dev/null
+/*\r
+ * Copyright (c) 2001, Swedish Institute of Computer Science.\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ * 1. Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the\r
+ * documentation and/or other materials provided with the distribution.\r
+ * 3. Neither the name of the Institute nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND\r
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\r
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\r
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\r
+ * SUCH DAMAGE.\r
+ *\r
+ * This file is part of the lwIP TCP/IP stack.\r
+ *\r
+ * Author: Adam Dunkels <adam@sics.se>\r
+ *\r
+ * $Id: httpd-fs.h,v 1.1 2006/06/07 09:13:08 adam Exp $\r
+ */\r
+#ifndef __HTTPD_FS_H__\r
+#define __HTTPD_FS_H__\r
+\r
+#define HTTPD_FS_STATISTICS 1\r
+\r
+struct httpd_fs_file {\r
+ char *data;\r
+ int len;\r
+};\r
+\r
+/* file must be allocated by caller and will be filled in\r
+ by the function. */\r
+int httpd_fs_open(const char *name, struct httpd_fs_file *file);\r
+\r
+#ifdef HTTPD_FS_STATISTICS\r
+#if HTTPD_FS_STATISTICS == 1\r
+u16_t httpd_fs_count(char *name);\r
+#endif /* HTTPD_FS_STATISTICS */\r
+#endif /* HTTPD_FS_STATISTICS */\r
+\r
+void httpd_fs_init(void);\r
+\r
+#endif /* __HTTPD_FS_H__ */\r
--- /dev/null
+<html>\r
+ <body bgcolor="white">\r
+ <center>\r
+ <h1>404 - file not found</h1>\r
+ <h3>Go <a href="/">here</a> instead.</h3>\r
+ </center>\r
+ </body>\r
+</html>
\ No newline at end of file
--- /dev/null
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">\r
+<html>\r
+ <head>\r
+ <title>FreeRTOS.org uIP WEB server demo</title>\r
+ </head>\r
+ <BODY onLoad="window.setTimeout("location.href='index.shtml'",100)"bgcolor="#CCCCff">\r
+<font face="arial">\r
+Loading index.shtml. Click <a href="index.shtml">here</a> if not automatically redirected.\r
+</font>\r
+</font>\r
+</body>\r
+</html>\r
+\r
--- /dev/null
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">\r
+<html>\r
+ <head>\r
+ <title>FreeRTOS.org uIP WEB server demo</title>\r
+ </head>\r
+ <BODY onLoad="window.setTimeout("location.href='index.shtml'",2000)"bgcolor="#CCCCff">\r
+<font face="arial">\r
+<a href="index.shtml">RTOS Stats</a> <b>|</b> <a href="stats.shtml">TCP Stats</a> <b>|</b> <a href="tcp.shtml">Connections</a> <b>|</b> <a href="http://www.freertos.org/">FreeRTOS.org Homepage</a> <b>|</b> <a href="io.shtml">IO</a>\r
+<br><p>\r
+<hr>\r
+<br><p>\r
+<h2>Task statistics</h2>\r
+Page will refresh every 2 seconds.<p>\r
+<font face="courier"><pre>Task State Priority Stack #<br>************************************************<br>\r
+%! rtos-stats\r
+</pre></font>\r
+</font>\r
+</body>\r
+</html>\r
+\r
--- /dev/null
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">\r
+<html>\r
+ <head>\r
+ <title>FreeRTOS.org uIP WEB server demo</title>\r
+ </head>\r
+ <BODY bgcolor="#CCCCff">\r
+<font face="arial">\r
+<a href="index.shtml">RTOS Stats</a> <b>|</b> <a href="stats.shtml">TCP Stats</a> <b>|</b> <a href="tcp.shtml">Connections</a> <b>|</b> <a href="http://www.freertos.org/">FreeRTOS.org Homepage</a> <b>|</b> <a href="io.shtml">IO</a>\r
+<br><p>\r
+<hr>\r
+<b>LED and LCD IO</b><br>\r
+\r
+<p>\r
+\r
+Use the check box to turn on or off the LED, enter text to display on the OLED display, then click "Update IO".\r
+\r
+\r
+<p>\r
+<form name="aForm" action="/io.shtml" method="get">\r
+%! led-io\r
+<p>\r
+<input type="submit" value="Update IO">\r
+</form>\r
+<br><p>\r
+</font>\r
+</body>\r
+</html>\r
+\r
--- /dev/null
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">\r
+<html>\r
+ <head>\r
+ <title>FreeRTOS.org uIP WEB server demo</title>\r
+ </head>\r
+ <BODY bgcolor="#CCCCff">\r
+<font face="arial">\r
+<a href="index.shtml">RTOS Stats</a> <b>|</b> <a href="stats.shtml">TCP Stats</a> <b>|</b> <a href="tcp.shtml">Connections</a> <b>|</b> <a href="http://www.freertos.org/">FreeRTOS.org Homepage</a> <b>|</b> <a href="io.shtml">IO</a>\r
+<br><p>\r
+<hr>\r
+<br><p>\r
+<h2>Network statistics</h2>\r
+<table width="300" border="0">\r
+<tr><td align="left"><font face="courier"><pre>\r
+IP Packets dropped\r
+ Packets received\r
+ Packets sent\r
+IP errors IP version/header length\r
+ IP length, high byte\r
+ IP length, low byte\r
+ IP fragments\r
+ Header checksum\r
+ Wrong protocol\r
+ICMP Packets dropped\r
+ Packets received\r
+ Packets sent\r
+ Type errors\r
+TCP Packets dropped\r
+ Packets received\r
+ Packets sent\r
+ Checksum errors\r
+ Data packets without ACKs\r
+ Resets\r
+ Retransmissions\r
+ No connection avaliable\r
+ Connection attempts to closed ports\r
+</pre></font></td><td><pre>%! net-stats\r
+</pre></table>\r
+</font>\r
+</body>\r
+</html>\r
--- /dev/null
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">\r
+<html>\r
+ <head>\r
+ <title>FreeRTOS.org uIP WEB server demo</title>\r
+ </head>\r
+ <BODY bgcolor="#CCCCff">\r
+<font face="arial">\r
+<a href="index.shtml">RTOS Stats</a> <b>|</b> <a href="stats.shtml">TCP Stats</a> <b>|</b> <a href="tcp.shtml">Connections</a> <b>|</b> <a href="http://www.freertos.org/">FreeRTOS.org Homepage</a> <b>|</b> <a href="io.shtml">IO</a>\r
+<br><p>\r
+<hr>\r
+<br>\r
+<h2>Network connections</h2>\r
+<p>\r
+<table>\r
+<tr><th>Local</th><th>Remote</th><th>State</th><th>Retransmissions</th><th>Timer</th><th>Flags</th></tr>\r
+%! tcp-connections\r
+</pre></font>\r
+</font>\r
+</body>\r
+</html>\r
+\r
--- /dev/null
+static const unsigned char data_404_html[] = {\r
+ /* /404.html */\r
+ 0x2f, 0x34, 0x30, 0x34, 0x2e, 0x68, 0x74, 0x6d, 0x6c, 0,\r
+ 0x3c, 0x68, 0x74, 0x6d, 0x6c, 0x3e, 0xd, 0xa, 0x20, 0x20, \r
+ 0x3c, 0x62, 0x6f, 0x64, 0x79, 0x20, 0x62, 0x67, 0x63, 0x6f, \r
+ 0x6c, 0x6f, 0x72, 0x3d, 0x22, 0x77, 0x68, 0x69, 0x74, 0x65, \r
+ 0x22, 0x3e, 0xd, 0xa, 0x20, 0x20, 0x20, 0x20, 0x3c, 0x63, \r
+ 0x65, 0x6e, 0x74, 0x65, 0x72, 0x3e, 0xd, 0xa, 0x20, 0x20, \r
+ 0x20, 0x20, 0x20, 0x20, 0x3c, 0x68, 0x31, 0x3e, 0x34, 0x30, \r
+ 0x34, 0x20, 0x2d, 0x20, 0x66, 0x69, 0x6c, 0x65, 0x20, 0x6e, \r
+ 0x6f, 0x74, 0x20, 0x66, 0x6f, 0x75, 0x6e, 0x64, 0x3c, 0x2f, \r
+ 0x68, 0x31, 0x3e, 0xd, 0xa, 0x20, 0x20, 0x20, 0x20, 0x20, \r
+ 0x20, 0x3c, 0x68, 0x33, 0x3e, 0x47, 0x6f, 0x20, 0x3c, 0x61, \r
+ 0x20, 0x68, 0x72, 0x65, 0x66, 0x3d, 0x22, 0x2f, 0x22, 0x3e, \r
+ 0x68, 0x65, 0x72, 0x65, 0x3c, 0x2f, 0x61, 0x3e, 0x20, 0x69, \r
+ 0x6e, 0x73, 0x74, 0x65, 0x61, 0x64, 0x2e, 0x3c, 0x2f, 0x68, \r
+ 0x33, 0x3e, 0xd, 0xa, 0x20, 0x20, 0x20, 0x20, 0x3c, 0x2f, \r
+ 0x63, 0x65, 0x6e, 0x74, 0x65, 0x72, 0x3e, 0xd, 0xa, 0x20, \r
+ 0x20, 0x3c, 0x2f, 0x62, 0x6f, 0x64, 0x79, 0x3e, 0xd, 0xa, \r
+ 0x3c, 0x2f, 0x68, 0x74, 0x6d, 0x6c, 0x3e, 0};\r
+\r
+static const unsigned char data_index_html[] = {\r
+ /* /index.html */\r
+ 0x2f, 0x69, 0x6e, 0x64, 0x65, 0x78, 0x2e, 0x68, 0x74, 0x6d, 0x6c, 0,\r
+ 0x3c, 0x21, 0x44, 0x4f, 0x43, 0x54, 0x59, 0x50, 0x45, 0x20, \r
+ 0x48, 0x54, 0x4d, 0x4c, 0x20, 0x50, 0x55, 0x42, 0x4c, 0x49, \r
+ 0x43, 0x20, 0x22, 0x2d, 0x2f, 0x2f, 0x57, 0x33, 0x43, 0x2f, \r
+ 0x2f, 0x44, 0x54, 0x44, 0x20, 0x48, 0x54, 0x4d, 0x4c, 0x20, \r
+ 0x34, 0x2e, 0x30, 0x31, 0x20, 0x54, 0x72, 0x61, 0x6e, 0x73, \r
+ 0x69, 0x74, 0x69, 0x6f, 0x6e, 0x61, 0x6c, 0x2f, 0x2f, 0x45, \r
+ 0x4e, 0x22, 0x20, 0x22, 0x68, 0x74, 0x74, 0x70, 0x3a, 0x2f, \r
+ 0x2f, 0x77, 0x77, 0x77, 0x2e, 0x77, 0x33, 0x2e, 0x6f, 0x72, \r
+ 0x67, 0x2f, 0x54, 0x52, 0x2f, 0x68, 0x74, 0x6d, 0x6c, 0x34, \r
+ 0x2f, 0x6c, 0x6f, 0x6f, 0x73, 0x65, 0x2e, 0x64, 0x74, 0x64, \r
+ 0x22, 0x3e, 0xd, 0xa, 0x3c, 0x68, 0x74, 0x6d, 0x6c, 0x3e, \r
+ 0xd, 0xa, 0x20, 0x20, 0x3c, 0x68, 0x65, 0x61, 0x64, 0x3e, \r
+ 0xd, 0xa, 0x20, 0x20, 0x20, 0x20, 0x3c, 0x74, 0x69, 0x74, \r
+ 0x6c, 0x65, 0x3e, 0x46, 0x72, 0x65, 0x65, 0x52, 0x54, 0x4f, \r
+ 0x53, 0x2e, 0x6f, 0x72, 0x67, 0x20, 0x75, 0x49, 0x50, 0x20, \r
+ 0x57, 0x45, 0x42, 0x20, 0x73, 0x65, 0x72, 0x76, 0x65, 0x72, \r
+ 0x20, 0x64, 0x65, 0x6d, 0x6f, 0x3c, 0x2f, 0x74, 0x69, 0x74, \r
+ 0x6c, 0x65, 0x3e, 0xd, 0xa, 0x20, 0x20, 0x3c, 0x2f, 0x68, \r
+ 0x65, 0x61, 0x64, 0x3e, 0xd, 0xa, 0x20, 0x20, 0x3c, 0x42, \r
+ 0x4f, 0x44, 0x59, 0x20, 0x6f, 0x6e, 0x4c, 0x6f, 0x61, 0x64, \r
+ 0x3d, 0x22, 0x77, 0x69, 0x6e, 0x64, 0x6f, 0x77, 0x2e, 0x73, \r
+ 0x65, 0x74, 0x54, 0x69, 0x6d, 0x65, 0x6f, 0x75, 0x74, 0x28, \r
+ 0x26, 0x71, 0x75, 0x6f, 0x74, 0x3b, 0x6c, 0x6f, 0x63, 0x61, \r
+ 0x74, 0x69, 0x6f, 0x6e, 0x2e, 0x68, 0x72, 0x65, 0x66, 0x3d, \r
+ 0x27, 0x69, 0x6e, 0x64, 0x65, 0x78, 0x2e, 0x73, 0x68, 0x74, \r
+ 0x6d, 0x6c, 0x27, 0x26, 0x71, 0x75, 0x6f, 0x74, 0x3b, 0x2c, \r
+ 0x31, 0x30, 0x30, 0x29, 0x22, 0x62, 0x67, 0x63, 0x6f, 0x6c, \r
+ 0x6f, 0x72, 0x3d, 0x22, 0x23, 0x43, 0x43, 0x43, 0x43, 0x66, \r
+ 0x66, 0x22, 0x3e, 0xd, 0xa, 0x3c, 0x66, 0x6f, 0x6e, 0x74, \r
+ 0x20, 0x66, 0x61, 0x63, 0x65, 0x3d, 0x22, 0x61, 0x72, 0x69, \r
+ 0x61, 0x6c, 0x22, 0x3e, 0xd, 0xa, 0x4c, 0x6f, 0x61, 0x64, \r
+ 0x69, 0x6e, 0x67, 0x20, 0x69, 0x6e, 0x64, 0x65, 0x78, 0x2e, \r
+ 0x73, 0x68, 0x74, 0x6d, 0x6c, 0x2e, 0x20, 0x20, 0x43, 0x6c, \r
+ 0x69, 0x63, 0x6b, 0x20, 0x3c, 0x61, 0x20, 0x68, 0x72, 0x65, \r
+ 0x66, 0x3d, 0x22, 0x69, 0x6e, 0x64, 0x65, 0x78, 0x2e, 0x73, \r
+ 0x68, 0x74, 0x6d, 0x6c, 0x22, 0x3e, 0x68, 0x65, 0x72, 0x65, \r
+ 0x3c, 0x2f, 0x61, 0x3e, 0x20, 0x69, 0x66, 0x20, 0x6e, 0x6f, \r
+ 0x74, 0x20, 0x61, 0x75, 0x74, 0x6f, 0x6d, 0x61, 0x74, 0x69, \r
+ 0x63, 0x61, 0x6c, 0x6c, 0x79, 0x20, 0x72, 0x65, 0x64, 0x69, \r
+ 0x72, 0x65, 0x63, 0x74, 0x65, 0x64, 0x2e, 0xd, 0xa, 0x3c, \r
+ 0x2f, 0x66, 0x6f, 0x6e, 0x74, 0x3e, 0xd, 0xa, 0x3c, 0x2f, \r
+ 0x66, 0x6f, 0x6e, 0x74, 0x3e, 0xd, 0xa, 0x3c, 0x2f, 0x62, \r
+ 0x6f, 0x64, 0x79, 0x3e, 0xd, 0xa, 0x3c, 0x2f, 0x68, 0x74, \r
+ 0x6d, 0x6c, 0x3e, 0xd, 0xa, 0xd, 0xa, 0};\r
+\r
+static const unsigned char data_index_shtml[] = {\r
+ /* /index.shtml */\r
+ 0x2f, 0x69, 0x6e, 0x64, 0x65, 0x78, 0x2e, 0x73, 0x68, 0x74, 0x6d, 0x6c, 0,\r
+ 0x3c, 0x21, 0x44, 0x4f, 0x43, 0x54, 0x59, 0x50, 0x45, 0x20, \r
+ 0x48, 0x54, 0x4d, 0x4c, 0x20, 0x50, 0x55, 0x42, 0x4c, 0x49, \r
+ 0x43, 0x20, 0x22, 0x2d, 0x2f, 0x2f, 0x57, 0x33, 0x43, 0x2f, \r
+ 0x2f, 0x44, 0x54, 0x44, 0x20, 0x48, 0x54, 0x4d, 0x4c, 0x20, \r
+ 0x34, 0x2e, 0x30, 0x31, 0x20, 0x54, 0x72, 0x61, 0x6e, 0x73, \r
+ 0x69, 0x74, 0x69, 0x6f, 0x6e, 0x61, 0x6c, 0x2f, 0x2f, 0x45, \r
+ 0x4e, 0x22, 0x20, 0x22, 0x68, 0x74, 0x74, 0x70, 0x3a, 0x2f, \r
+ 0x2f, 0x77, 0x77, 0x77, 0x2e, 0x77, 0x33, 0x2e, 0x6f, 0x72, \r
+ 0x67, 0x2f, 0x54, 0x52, 0x2f, 0x68, 0x74, 0x6d, 0x6c, 0x34, \r
+ 0x2f, 0x6c, 0x6f, 0x6f, 0x73, 0x65, 0x2e, 0x64, 0x74, 0x64, \r
+ 0x22, 0x3e, 0xd, 0xa, 0x3c, 0x68, 0x74, 0x6d, 0x6c, 0x3e, \r
+ 0xd, 0xa, 0x20, 0x20, 0x3c, 0x68, 0x65, 0x61, 0x64, 0x3e, \r
+ 0xd, 0xa, 0x20, 0x20, 0x20, 0x20, 0x3c, 0x74, 0x69, 0x74, \r
+ 0x6c, 0x65, 0x3e, 0x46, 0x72, 0x65, 0x65, 0x52, 0x54, 0x4f, \r
+ 0x53, 0x2e, 0x6f, 0x72, 0x67, 0x20, 0x75, 0x49, 0x50, 0x20, \r
+ 0x57, 0x45, 0x42, 0x20, 0x73, 0x65, 0x72, 0x76, 0x65, 0x72, \r
+ 0x20, 0x64, 0x65, 0x6d, 0x6f, 0x3c, 0x2f, 0x74, 0x69, 0x74, \r
+ 0x6c, 0x65, 0x3e, 0xd, 0xa, 0x20, 0x20, 0x3c, 0x2f, 0x68, \r
+ 0x65, 0x61, 0x64, 0x3e, 0xd, 0xa, 0x20, 0x20, 0x3c, 0x42, \r
+ 0x4f, 0x44, 0x59, 0x20, 0x6f, 0x6e, 0x4c, 0x6f, 0x61, 0x64, \r
+ 0x3d, 0x22, 0x77, 0x69, 0x6e, 0x64, 0x6f, 0x77, 0x2e, 0x73, \r
+ 0x65, 0x74, 0x54, 0x69, 0x6d, 0x65, 0x6f, 0x75, 0x74, 0x28, \r
+ 0x26, 0x71, 0x75, 0x6f, 0x74, 0x3b, 0x6c, 0x6f, 0x63, 0x61, \r
+ 0x74, 0x69, 0x6f, 0x6e, 0x2e, 0x68, 0x72, 0x65, 0x66, 0x3d, \r
+ 0x27, 0x69, 0x6e, 0x64, 0x65, 0x78, 0x2e, 0x73, 0x68, 0x74, \r
+ 0x6d, 0x6c, 0x27, 0x26, 0x71, 0x75, 0x6f, 0x74, 0x3b, 0x2c, \r
+ 0x32, 0x30, 0x30, 0x30, 0x29, 0x22, 0x62, 0x67, 0x63, 0x6f, \r
+ 0x6c, 0x6f, 0x72, 0x3d, 0x22, 0x23, 0x43, 0x43, 0x43, 0x43, \r
+ 0x66, 0x66, 0x22, 0x3e, 0xd, 0xa, 0x3c, 0x66, 0x6f, 0x6e, \r
+ 0x74, 0x20, 0x66, 0x61, 0x63, 0x65, 0x3d, 0x22, 0x61, 0x72, \r
+ 0x69, 0x61, 0x6c, 0x22, 0x3e, 0xd, 0xa, 0x3c, 0x61, 0x20, \r
+ 0x68, 0x72, 0x65, 0x66, 0x3d, 0x22, 0x69, 0x6e, 0x64, 0x65, \r
+ 0x78, 0x2e, 0x73, 0x68, 0x74, 0x6d, 0x6c, 0x22, 0x3e, 0x52, \r
+ 0x54, 0x4f, 0x53, 0x20, 0x53, 0x74, 0x61, 0x74, 0x73, 0x3c, \r
+ 0x2f, 0x61, 0x3e, 0x20, 0x3c, 0x62, 0x3e, 0x7c, 0x3c, 0x2f, \r
+ 0x62, 0x3e, 0x20, 0x3c, 0x61, 0x20, 0x68, 0x72, 0x65, 0x66, \r
+ 0x3d, 0x22, 0x73, 0x74, 0x61, 0x74, 0x73, 0x2e, 0x73, 0x68, \r
+ 0x74, 0x6d, 0x6c, 0x22, 0x3e, 0x54, 0x43, 0x50, 0x20, 0x53, \r
+ 0x74, 0x61, 0x74, 0x73, 0x3c, 0x2f, 0x61, 0x3e, 0x20, 0x3c, \r
+ 0x62, 0x3e, 0x7c, 0x3c, 0x2f, 0x62, 0x3e, 0x20, 0x3c, 0x61, \r
+ 0x20, 0x68, 0x72, 0x65, 0x66, 0x3d, 0x22, 0x74, 0x63, 0x70, \r
+ 0x2e, 0x73, 0x68, 0x74, 0x6d, 0x6c, 0x22, 0x3e, 0x43, 0x6f, \r
+ 0x6e, 0x6e, 0x65, 0x63, 0x74, 0x69, 0x6f, 0x6e, 0x73, 0x3c, \r
+ 0x2f, 0x61, 0x3e, 0x20, 0x3c, 0x62, 0x3e, 0x7c, 0x3c, 0x2f, \r
+ 0x62, 0x3e, 0x20, 0x3c, 0x61, 0x20, 0x68, 0x72, 0x65, 0x66, \r
+ 0x3d, 0x22, 0x68, 0x74, 0x74, 0x70, 0x3a, 0x2f, 0x2f, 0x77, \r
+ 0x77, 0x77, 0x2e, 0x66, 0x72, 0x65, 0x65, 0x72, 0x74, 0x6f, \r
+ 0x73, 0x2e, 0x6f, 0x72, 0x67, 0x2f, 0x22, 0x3e, 0x46, 0x72, \r
+ 0x65, 0x65, 0x52, 0x54, 0x4f, 0x53, 0x2e, 0x6f, 0x72, 0x67, \r
+ 0x20, 0x48, 0x6f, 0x6d, 0x65, 0x70, 0x61, 0x67, 0x65, 0x3c, \r
+ 0x2f, 0x61, 0x3e, 0x20, 0x3c, 0x62, 0x3e, 0x7c, 0x3c, 0x2f, \r
+ 0x62, 0x3e, 0x20, 0x3c, 0x61, 0x20, 0x68, 0x72, 0x65, 0x66, \r
+ 0x3d, 0x22, 0x69, 0x6f, 0x2e, 0x73, 0x68, 0x74, 0x6d, 0x6c, \r
+ 0x22, 0x3e, 0x49, 0x4f, 0x3c, 0x2f, 0x61, 0x3e, 0xd, 0xa, \r
+ 0x3c, 0x62, 0x72, 0x3e, 0x3c, 0x70, 0x3e, 0xd, 0xa, 0x3c, \r
+ 0x68, 0x72, 0x3e, 0xd, 0xa, 0x3c, 0x62, 0x72, 0x3e, 0x3c, \r
+ 0x70, 0x3e, 0xd, 0xa, 0x3c, 0x68, 0x32, 0x3e, 0x54, 0x61, \r
+ 0x73, 0x6b, 0x20, 0x73, 0x74, 0x61, 0x74, 0x69, 0x73, 0x74, \r
+ 0x69, 0x63, 0x73, 0x3c, 0x2f, 0x68, 0x32, 0x3e, 0xd, 0xa, \r
+ 0x50, 0x61, 0x67, 0x65, 0x20, 0x77, 0x69, 0x6c, 0x6c, 0x20, \r
+ 0x72, 0x65, 0x66, 0x72, 0x65, 0x73, 0x68, 0x20, 0x65, 0x76, \r
+ 0x65, 0x72, 0x79, 0x20, 0x32, 0x20, 0x73, 0x65, 0x63, 0x6f, \r
+ 0x6e, 0x64, 0x73, 0x2e, 0x3c, 0x70, 0x3e, 0xd, 0xa, 0x3c, \r
+ 0x66, 0x6f, 0x6e, 0x74, 0x20, 0x66, 0x61, 0x63, 0x65, 0x3d, \r
+ 0x22, 0x63, 0x6f, 0x75, 0x72, 0x69, 0x65, 0x72, 0x22, 0x3e, \r
+ 0x3c, 0x70, 0x72, 0x65, 0x3e, 0x54, 0x61, 0x73, 0x6b, 0x20, \r
+ 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x53, \r
+ 0x74, 0x61, 0x74, 0x65, 0x20, 0x20, 0x50, 0x72, 0x69, 0x6f, \r
+ 0x72, 0x69, 0x74, 0x79, 0x20, 0x20, 0x53, 0x74, 0x61, 0x63, \r
+ 0x6b, 0x9, 0x23, 0x3c, 0x62, 0x72, 0x3e, 0x2a, 0x2a, 0x2a, \r
+ 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, \r
+ 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, \r
+ 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, \r
+ 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, \r
+ 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x3c, 0x62, 0x72, 0x3e, 0xd, \r
+ 0xa, 0x25, 0x21, 0x20, 0x72, 0x74, 0x6f, 0x73, 0x2d, 0x73, \r
+ 0x74, 0x61, 0x74, 0x73, 0xd, 0xa, 0x3c, 0x2f, 0x70, 0x72, \r
+ 0x65, 0x3e, 0x3c, 0x2f, 0x66, 0x6f, 0x6e, 0x74, 0x3e, 0xd, \r
+ 0xa, 0x3c, 0x2f, 0x66, 0x6f, 0x6e, 0x74, 0x3e, 0xd, 0xa, \r
+ 0x3c, 0x2f, 0x62, 0x6f, 0x64, 0x79, 0x3e, 0xd, 0xa, 0x3c, \r
+ 0x2f, 0x68, 0x74, 0x6d, 0x6c, 0x3e, 0xd, 0xa, 0xd, 0xa, \r
+0};\r
+\r
+static const unsigned char data_io_shtml[] = {\r
+ /* /io.shtml */\r
+ 0x2f, 0x69, 0x6f, 0x2e, 0x73, 0x68, 0x74, 0x6d, 0x6c, 0,\r
+ 0x3c, 0x21, 0x44, 0x4f, 0x43, 0x54, 0x59, 0x50, 0x45, 0x20, \r
+ 0x48, 0x54, 0x4d, 0x4c, 0x20, 0x50, 0x55, 0x42, 0x4c, 0x49, \r
+ 0x43, 0x20, 0x22, 0x2d, 0x2f, 0x2f, 0x57, 0x33, 0x43, 0x2f, \r
+ 0x2f, 0x44, 0x54, 0x44, 0x20, 0x48, 0x54, 0x4d, 0x4c, 0x20, \r
+ 0x34, 0x2e, 0x30, 0x31, 0x20, 0x54, 0x72, 0x61, 0x6e, 0x73, \r
+ 0x69, 0x74, 0x69, 0x6f, 0x6e, 0x61, 0x6c, 0x2f, 0x2f, 0x45, \r
+ 0x4e, 0x22, 0x20, 0x22, 0x68, 0x74, 0x74, 0x70, 0x3a, 0x2f, \r
+ 0x2f, 0x77, 0x77, 0x77, 0x2e, 0x77, 0x33, 0x2e, 0x6f, 0x72, \r
+ 0x67, 0x2f, 0x54, 0x52, 0x2f, 0x68, 0x74, 0x6d, 0x6c, 0x34, \r
+ 0x2f, 0x6c, 0x6f, 0x6f, 0x73, 0x65, 0x2e, 0x64, 0x74, 0x64, \r
+ 0x22, 0x3e, 0xd, 0xa, 0x3c, 0x68, 0x74, 0x6d, 0x6c, 0x3e, \r
+ 0xd, 0xa, 0x20, 0x20, 0x3c, 0x68, 0x65, 0x61, 0x64, 0x3e, \r
+ 0xd, 0xa, 0x20, 0x20, 0x20, 0x20, 0x3c, 0x74, 0x69, 0x74, \r
+ 0x6c, 0x65, 0x3e, 0x46, 0x72, 0x65, 0x65, 0x52, 0x54, 0x4f, \r
+ 0x53, 0x2e, 0x6f, 0x72, 0x67, 0x20, 0x75, 0x49, 0x50, 0x20, \r
+ 0x57, 0x45, 0x42, 0x20, 0x73, 0x65, 0x72, 0x76, 0x65, 0x72, \r
+ 0x20, 0x64, 0x65, 0x6d, 0x6f, 0x3c, 0x2f, 0x74, 0x69, 0x74, \r
+ 0x6c, 0x65, 0x3e, 0xd, 0xa, 0x20, 0x20, 0x3c, 0x2f, 0x68, \r
+ 0x65, 0x61, 0x64, 0x3e, 0xd, 0xa, 0x20, 0x20, 0x3c, 0x42, \r
+ 0x4f, 0x44, 0x59, 0x20, 0x62, 0x67, 0x63, 0x6f, 0x6c, 0x6f, \r
+ 0x72, 0x3d, 0x22, 0x23, 0x43, 0x43, 0x43, 0x43, 0x66, 0x66, \r
+ 0x22, 0x3e, 0xd, 0xa, 0x3c, 0x66, 0x6f, 0x6e, 0x74, 0x20, \r
+ 0x66, 0x61, 0x63, 0x65, 0x3d, 0x22, 0x61, 0x72, 0x69, 0x61, \r
+ 0x6c, 0x22, 0x3e, 0xd, 0xa, 0x3c, 0x61, 0x20, 0x68, 0x72, \r
+ 0x65, 0x66, 0x3d, 0x22, 0x69, 0x6e, 0x64, 0x65, 0x78, 0x2e, \r
+ 0x73, 0x68, 0x74, 0x6d, 0x6c, 0x22, 0x3e, 0x52, 0x54, 0x4f, \r
+ 0x53, 0x20, 0x53, 0x74, 0x61, 0x74, 0x73, 0x3c, 0x2f, 0x61, \r
+ 0x3e, 0x20, 0x3c, 0x62, 0x3e, 0x7c, 0x3c, 0x2f, 0x62, 0x3e, \r
+ 0x20, 0x3c, 0x61, 0x20, 0x68, 0x72, 0x65, 0x66, 0x3d, 0x22, \r
+ 0x73, 0x74, 0x61, 0x74, 0x73, 0x2e, 0x73, 0x68, 0x74, 0x6d, \r
+ 0x6c, 0x22, 0x3e, 0x54, 0x43, 0x50, 0x20, 0x53, 0x74, 0x61, \r
+ 0x74, 0x73, 0x3c, 0x2f, 0x61, 0x3e, 0x20, 0x3c, 0x62, 0x3e, \r
+ 0x7c, 0x3c, 0x2f, 0x62, 0x3e, 0x20, 0x3c, 0x61, 0x20, 0x68, \r
+ 0x72, 0x65, 0x66, 0x3d, 0x22, 0x74, 0x63, 0x70, 0x2e, 0x73, \r
+ 0x68, 0x74, 0x6d, 0x6c, 0x22, 0x3e, 0x43, 0x6f, 0x6e, 0x6e, \r
+ 0x65, 0x63, 0x74, 0x69, 0x6f, 0x6e, 0x73, 0x3c, 0x2f, 0x61, \r
+ 0x3e, 0x20, 0x3c, 0x62, 0x3e, 0x7c, 0x3c, 0x2f, 0x62, 0x3e, \r
+ 0x20, 0x3c, 0x61, 0x20, 0x68, 0x72, 0x65, 0x66, 0x3d, 0x22, \r
+ 0x68, 0x74, 0x74, 0x70, 0x3a, 0x2f, 0x2f, 0x77, 0x77, 0x77, \r
+ 0x2e, 0x66, 0x72, 0x65, 0x65, 0x72, 0x74, 0x6f, 0x73, 0x2e, \r
+ 0x6f, 0x72, 0x67, 0x2f, 0x22, 0x3e, 0x46, 0x72, 0x65, 0x65, \r
+ 0x52, 0x54, 0x4f, 0x53, 0x2e, 0x6f, 0x72, 0x67, 0x20, 0x48, \r
+ 0x6f, 0x6d, 0x65, 0x70, 0x61, 0x67, 0x65, 0x3c, 0x2f, 0x61, \r
+ 0x3e, 0x20, 0x3c, 0x62, 0x3e, 0x7c, 0x3c, 0x2f, 0x62, 0x3e, \r
+ 0x20, 0x3c, 0x61, 0x20, 0x68, 0x72, 0x65, 0x66, 0x3d, 0x22, \r
+ 0x69, 0x6f, 0x2e, 0x73, 0x68, 0x74, 0x6d, 0x6c, 0x22, 0x3e, \r
+ 0x49, 0x4f, 0x3c, 0x2f, 0x61, 0x3e, 0xd, 0xa, 0x3c, 0x62, \r
+ 0x72, 0x3e, 0x3c, 0x70, 0x3e, 0xd, 0xa, 0x3c, 0x68, 0x72, \r
+ 0x3e, 0xd, 0xa, 0x3c, 0x62, 0x3e, 0x4c, 0x45, 0x44, 0x20, \r
+ 0x61, 0x6e, 0x64, 0x20, 0x4c, 0x43, 0x44, 0x20, 0x49, 0x4f, \r
+ 0x3c, 0x2f, 0x62, 0x3e, 0x3c, 0x62, 0x72, 0x3e, 0xd, 0xa, \r
+ 0xd, 0xa, 0x3c, 0x70, 0x3e, 0xd, 0xa, 0xd, 0xa, 0x55, \r
+ 0x73, 0x65, 0x20, 0x74, 0x68, 0x65, 0x20, 0x63, 0x68, 0x65, \r
+ 0x63, 0x6b, 0x20, 0x62, 0x6f, 0x78, 0x20, 0x74, 0x6f, 0x20, \r
+ 0x74, 0x75, 0x72, 0x6e, 0x20, 0x6f, 0x6e, 0x20, 0x6f, 0x72, \r
+ 0x20, 0x6f, 0x66, 0x66, 0x20, 0x74, 0x68, 0x65, 0x20, 0x4c, \r
+ 0x45, 0x44, 0x2c, 0x20, 0x65, 0x6e, 0x74, 0x65, 0x72, 0x20, \r
+ 0x74, 0x65, 0x78, 0x74, 0x20, 0x74, 0x6f, 0x20, 0x64, 0x69, \r
+ 0x73, 0x70, 0x6c, 0x61, 0x79, 0x20, 0x6f, 0x6e, 0x20, 0x74, \r
+ 0x68, 0x65, 0x20, 0x4f, 0x4c, 0x45, 0x44, 0x20, 0x64, 0x69, \r
+ 0x73, 0x70, 0x6c, 0x61, 0x79, 0x2c, 0x20, 0x74, 0x68, 0x65, \r
+ 0x6e, 0x20, 0x63, 0x6c, 0x69, 0x63, 0x6b, 0x20, 0x22, 0x55, \r
+ 0x70, 0x64, 0x61, 0x74, 0x65, 0x20, 0x49, 0x4f, 0x22, 0x2e, \r
+ 0xd, 0xa, 0xd, 0xa, 0xd, 0xa, 0x3c, 0x70, 0x3e, 0xd, \r
+ 0xa, 0x3c, 0x66, 0x6f, 0x72, 0x6d, 0x20, 0x6e, 0x61, 0x6d, \r
+ 0x65, 0x3d, 0x22, 0x61, 0x46, 0x6f, 0x72, 0x6d, 0x22, 0x20, \r
+ 0x61, 0x63, 0x74, 0x69, 0x6f, 0x6e, 0x3d, 0x22, 0x2f, 0x69, \r
+ 0x6f, 0x2e, 0x73, 0x68, 0x74, 0x6d, 0x6c, 0x22, 0x20, 0x6d, \r
+ 0x65, 0x74, 0x68, 0x6f, 0x64, 0x3d, 0x22, 0x67, 0x65, 0x74, \r
+ 0x22, 0x3e, 0xd, 0xa, 0x25, 0x21, 0x20, 0x6c, 0x65, 0x64, \r
+ 0x2d, 0x69, 0x6f, 0xd, 0xa, 0x3c, 0x70, 0x3e, 0xd, 0xa, \r
+ 0x3c, 0x69, 0x6e, 0x70, 0x75, 0x74, 0x20, 0x74, 0x79, 0x70, \r
+ 0x65, 0x3d, 0x22, 0x73, 0x75, 0x62, 0x6d, 0x69, 0x74, 0x22, \r
+ 0x20, 0x76, 0x61, 0x6c, 0x75, 0x65, 0x3d, 0x22, 0x55, 0x70, \r
+ 0x64, 0x61, 0x74, 0x65, 0x20, 0x49, 0x4f, 0x22, 0x3e, 0xd, \r
+ 0xa, 0x3c, 0x2f, 0x66, 0x6f, 0x72, 0x6d, 0x3e, 0xd, 0xa, \r
+ 0x3c, 0x62, 0x72, 0x3e, 0x3c, 0x70, 0x3e, 0xd, 0xa, 0x3c, \r
+ 0x2f, 0x66, 0x6f, 0x6e, 0x74, 0x3e, 0xd, 0xa, 0x3c, 0x2f, \r
+ 0x62, 0x6f, 0x64, 0x79, 0x3e, 0xd, 0xa, 0x3c, 0x2f, 0x68, \r
+ 0x74, 0x6d, 0x6c, 0x3e, 0xd, 0xa, 0xd, 0xa, 0};\r
+\r
+static const unsigned char data_stats_shtml[] = {\r
+ /* /stats.shtml */\r
+ 0x2f, 0x73, 0x74, 0x61, 0x74, 0x73, 0x2e, 0x73, 0x68, 0x74, 0x6d, 0x6c, 0,\r
+ 0x3c, 0x21, 0x44, 0x4f, 0x43, 0x54, 0x59, 0x50, 0x45, 0x20, \r
+ 0x48, 0x54, 0x4d, 0x4c, 0x20, 0x50, 0x55, 0x42, 0x4c, 0x49, \r
+ 0x43, 0x20, 0x22, 0x2d, 0x2f, 0x2f, 0x57, 0x33, 0x43, 0x2f, \r
+ 0x2f, 0x44, 0x54, 0x44, 0x20, 0x48, 0x54, 0x4d, 0x4c, 0x20, \r
+ 0x34, 0x2e, 0x30, 0x31, 0x20, 0x54, 0x72, 0x61, 0x6e, 0x73, \r
+ 0x69, 0x74, 0x69, 0x6f, 0x6e, 0x61, 0x6c, 0x2f, 0x2f, 0x45, \r
+ 0x4e, 0x22, 0x20, 0x22, 0x68, 0x74, 0x74, 0x70, 0x3a, 0x2f, \r
+ 0x2f, 0x77, 0x77, 0x77, 0x2e, 0x77, 0x33, 0x2e, 0x6f, 0x72, \r
+ 0x67, 0x2f, 0x54, 0x52, 0x2f, 0x68, 0x74, 0x6d, 0x6c, 0x34, \r
+ 0x2f, 0x6c, 0x6f, 0x6f, 0x73, 0x65, 0x2e, 0x64, 0x74, 0x64, \r
+ 0x22, 0x3e, 0xd, 0xa, 0x3c, 0x68, 0x74, 0x6d, 0x6c, 0x3e, \r
+ 0xd, 0xa, 0x20, 0x20, 0x3c, 0x68, 0x65, 0x61, 0x64, 0x3e, \r
+ 0xd, 0xa, 0x20, 0x20, 0x20, 0x20, 0x3c, 0x74, 0x69, 0x74, \r
+ 0x6c, 0x65, 0x3e, 0x46, 0x72, 0x65, 0x65, 0x52, 0x54, 0x4f, \r
+ 0x53, 0x2e, 0x6f, 0x72, 0x67, 0x20, 0x75, 0x49, 0x50, 0x20, \r
+ 0x57, 0x45, 0x42, 0x20, 0x73, 0x65, 0x72, 0x76, 0x65, 0x72, \r
+ 0x20, 0x64, 0x65, 0x6d, 0x6f, 0x3c, 0x2f, 0x74, 0x69, 0x74, \r
+ 0x6c, 0x65, 0x3e, 0xd, 0xa, 0x20, 0x20, 0x3c, 0x2f, 0x68, \r
+ 0x65, 0x61, 0x64, 0x3e, 0xd, 0xa, 0x20, 0x20, 0x3c, 0x42, \r
+ 0x4f, 0x44, 0x59, 0x20, 0x62, 0x67, 0x63, 0x6f, 0x6c, 0x6f, \r
+ 0x72, 0x3d, 0x22, 0x23, 0x43, 0x43, 0x43, 0x43, 0x66, 0x66, \r
+ 0x22, 0x3e, 0xd, 0xa, 0x3c, 0x66, 0x6f, 0x6e, 0x74, 0x20, \r
+ 0x66, 0x61, 0x63, 0x65, 0x3d, 0x22, 0x61, 0x72, 0x69, 0x61, \r
+ 0x6c, 0x22, 0x3e, 0xd, 0xa, 0x3c, 0x61, 0x20, 0x68, 0x72, \r
+ 0x65, 0x66, 0x3d, 0x22, 0x69, 0x6e, 0x64, 0x65, 0x78, 0x2e, \r
+ 0x73, 0x68, 0x74, 0x6d, 0x6c, 0x22, 0x3e, 0x52, 0x54, 0x4f, \r
+ 0x53, 0x20, 0x53, 0x74, 0x61, 0x74, 0x73, 0x3c, 0x2f, 0x61, \r
+ 0x3e, 0x20, 0x3c, 0x62, 0x3e, 0x7c, 0x3c, 0x2f, 0x62, 0x3e, \r
+ 0x20, 0x3c, 0x61, 0x20, 0x68, 0x72, 0x65, 0x66, 0x3d, 0x22, \r
+ 0x73, 0x74, 0x61, 0x74, 0x73, 0x2e, 0x73, 0x68, 0x74, 0x6d, \r
+ 0x6c, 0x22, 0x3e, 0x54, 0x43, 0x50, 0x20, 0x53, 0x74, 0x61, \r
+ 0x74, 0x73, 0x3c, 0x2f, 0x61, 0x3e, 0x20, 0x3c, 0x62, 0x3e, \r
+ 0x7c, 0x3c, 0x2f, 0x62, 0x3e, 0x20, 0x3c, 0x61, 0x20, 0x68, \r
+ 0x72, 0x65, 0x66, 0x3d, 0x22, 0x74, 0x63, 0x70, 0x2e, 0x73, \r
+ 0x68, 0x74, 0x6d, 0x6c, 0x22, 0x3e, 0x43, 0x6f, 0x6e, 0x6e, \r
+ 0x65, 0x63, 0x74, 0x69, 0x6f, 0x6e, 0x73, 0x3c, 0x2f, 0x61, \r
+ 0x3e, 0x20, 0x3c, 0x62, 0x3e, 0x7c, 0x3c, 0x2f, 0x62, 0x3e, \r
+ 0x20, 0x3c, 0x61, 0x20, 0x68, 0x72, 0x65, 0x66, 0x3d, 0x22, \r
+ 0x68, 0x74, 0x74, 0x70, 0x3a, 0x2f, 0x2f, 0x77, 0x77, 0x77, \r
+ 0x2e, 0x66, 0x72, 0x65, 0x65, 0x72, 0x74, 0x6f, 0x73, 0x2e, \r
+ 0x6f, 0x72, 0x67, 0x2f, 0x22, 0x3e, 0x46, 0x72, 0x65, 0x65, \r
+ 0x52, 0x54, 0x4f, 0x53, 0x2e, 0x6f, 0x72, 0x67, 0x20, 0x48, \r
+ 0x6f, 0x6d, 0x65, 0x70, 0x61, 0x67, 0x65, 0x3c, 0x2f, 0x61, \r
+ 0x3e, 0x20, 0x3c, 0x62, 0x3e, 0x7c, 0x3c, 0x2f, 0x62, 0x3e, \r
+ 0x20, 0x3c, 0x61, 0x20, 0x68, 0x72, 0x65, 0x66, 0x3d, 0x22, \r
+ 0x69, 0x6f, 0x2e, 0x73, 0x68, 0x74, 0x6d, 0x6c, 0x22, 0x3e, \r
+ 0x49, 0x4f, 0x3c, 0x2f, 0x61, 0x3e, 0xd, 0xa, 0x3c, 0x62, \r
+ 0x72, 0x3e, 0x3c, 0x70, 0x3e, 0xd, 0xa, 0x3c, 0x68, 0x72, \r
+ 0x3e, 0xd, 0xa, 0x3c, 0x62, 0x72, 0x3e, 0x3c, 0x70, 0x3e, \r
+ 0xd, 0xa, 0x3c, 0x68, 0x32, 0x3e, 0x4e, 0x65, 0x74, 0x77, \r
+ 0x6f, 0x72, 0x6b, 0x20, 0x73, 0x74, 0x61, 0x74, 0x69, 0x73, \r
+ 0x74, 0x69, 0x63, 0x73, 0x3c, 0x2f, 0x68, 0x32, 0x3e, 0xd, \r
+ 0xa, 0x3c, 0x74, 0x61, 0x62, 0x6c, 0x65, 0x20, 0x77, 0x69, \r
+ 0x64, 0x74, 0x68, 0x3d, 0x22, 0x33, 0x30, 0x30, 0x22, 0x20, \r
+ 0x62, 0x6f, 0x72, 0x64, 0x65, 0x72, 0x3d, 0x22, 0x30, 0x22, \r
+ 0x3e, 0xd, 0xa, 0x3c, 0x74, 0x72, 0x3e, 0x3c, 0x74, 0x64, \r
+ 0x20, 0x61, 0x6c, 0x69, 0x67, 0x6e, 0x3d, 0x22, 0x6c, 0x65, \r
+ 0x66, 0x74, 0x22, 0x3e, 0x3c, 0x66, 0x6f, 0x6e, 0x74, 0x20, \r
+ 0x66, 0x61, 0x63, 0x65, 0x3d, 0x22, 0x63, 0x6f, 0x75, 0x72, \r
+ 0x69, 0x65, 0x72, 0x22, 0x3e, 0x3c, 0x70, 0x72, 0x65, 0x3e, \r
+ 0xd, 0xa, 0x49, 0x50, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, \r
+ 0x20, 0x20, 0x20, 0x20, 0x20, 0x50, 0x61, 0x63, 0x6b, 0x65, \r
+ 0x74, 0x73, 0x20, 0x64, 0x72, 0x6f, 0x70, 0x70, 0x65, 0x64, \r
+ 0xd, 0xa, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, \r
+ 0x20, 0x20, 0x20, 0x20, 0x20, 0x50, 0x61, 0x63, 0x6b, 0x65, \r
+ 0x74, 0x73, 0x20, 0x72, 0x65, 0x63, 0x65, 0x69, 0x76, 0x65, \r
+ 0x64, 0xd, 0xa, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, \r
+ 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x50, 0x61, 0x63, 0x6b, \r
+ 0x65, 0x74, 0x73, 0x20, 0x73, 0x65, 0x6e, 0x74, 0xd, 0xa, \r
+ 0x49, 0x50, 0x20, 0x65, 0x72, 0x72, 0x6f, 0x72, 0x73, 0x20, \r
+ 0x20, 0x20, 0x20, 0x49, 0x50, 0x20, 0x76, 0x65, 0x72, 0x73, \r
+ 0x69, 0x6f, 0x6e, 0x2f, 0x68, 0x65, 0x61, 0x64, 0x65, 0x72, \r
+ 0x20, 0x6c, 0x65, 0x6e, 0x67, 0x74, 0x68, 0xd, 0xa, 0x20, \r
+ 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, \r
+ 0x20, 0x20, 0x49, 0x50, 0x20, 0x6c, 0x65, 0x6e, 0x67, 0x74, \r
+ 0x68, 0x2c, 0x20, 0x68, 0x69, 0x67, 0x68, 0x20, 0x62, 0x79, \r
+ 0x74, 0x65, 0xd, 0xa, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, \r
+ 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x49, 0x50, 0x20, \r
+ 0x6c, 0x65, 0x6e, 0x67, 0x74, 0x68, 0x2c, 0x20, 0x6c, 0x6f, \r
+ 0x77, 0x20, 0x62, 0x79, 0x74, 0x65, 0xd, 0xa, 0x20, 0x20, \r
+ 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, \r
+ 0x20, 0x49, 0x50, 0x20, 0x66, 0x72, 0x61, 0x67, 0x6d, 0x65, \r
+ 0x6e, 0x74, 0x73, 0xd, 0xa, 0x20, 0x20, 0x20, 0x20, 0x20, \r
+ 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x48, 0x65, \r
+ 0x61, 0x64, 0x65, 0x72, 0x20, 0x63, 0x68, 0x65, 0x63, 0x6b, \r
+ 0x73, 0x75, 0x6d, 0xd, 0xa, 0x20, 0x20, 0x20, 0x20, 0x20, \r
+ 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x57, 0x72, \r
+ 0x6f, 0x6e, 0x67, 0x20, 0x70, 0x72, 0x6f, 0x74, 0x6f, 0x63, \r
+ 0x6f, 0x6c, 0xd, 0xa, 0x49, 0x43, 0x4d, 0x50, 0x9, 0x20, \r
+ 0x20, 0x20, 0x20, 0x20, 0x50, 0x61, 0x63, 0x6b, 0x65, 0x74, \r
+ 0x73, 0x20, 0x64, 0x72, 0x6f, 0x70, 0x70, 0x65, 0x64, 0xd, \r
+ 0xa, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, \r
+ 0x20, 0x20, 0x20, 0x20, 0x50, 0x61, 0x63, 0x6b, 0x65, 0x74, \r
+ 0x73, 0x20, 0x72, 0x65, 0x63, 0x65, 0x69, 0x76, 0x65, 0x64, \r
+ 0xd, 0xa, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, \r
+ 0x20, 0x20, 0x20, 0x20, 0x20, 0x50, 0x61, 0x63, 0x6b, 0x65, \r
+ 0x74, 0x73, 0x20, 0x73, 0x65, 0x6e, 0x74, 0xd, 0xa, 0x20, \r
+ 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, \r
+ 0x20, 0x20, 0x54, 0x79, 0x70, 0x65, 0x20, 0x65, 0x72, 0x72, \r
+ 0x6f, 0x72, 0x73, 0xd, 0xa, 0x54, 0x43, 0x50, 0x20, 0x20, \r
+ 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x50, 0x61, \r
+ 0x63, 0x6b, 0x65, 0x74, 0x73, 0x20, 0x64, 0x72, 0x6f, 0x70, \r
+ 0x70, 0x65, 0x64, 0xd, 0xa, 0x20, 0x20, 0x20, 0x20, 0x20, \r
+ 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x50, 0x61, \r
+ 0x63, 0x6b, 0x65, 0x74, 0x73, 0x20, 0x72, 0x65, 0x63, 0x65, \r
+ 0x69, 0x76, 0x65, 0x64, 0xd, 0xa, 0x20, 0x20, 0x20, 0x20, \r
+ 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x50, \r
+ 0x61, 0x63, 0x6b, 0x65, 0x74, 0x73, 0x20, 0x73, 0x65, 0x6e, \r
+ 0x74, 0xd, 0xa, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, \r
+ 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x43, 0x68, 0x65, 0x63, \r
+ 0x6b, 0x73, 0x75, 0x6d, 0x20, 0x65, 0x72, 0x72, 0x6f, 0x72, \r
+ 0x73, 0xd, 0xa, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, \r
+ 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x44, 0x61, 0x74, 0x61, \r
+ 0x20, 0x70, 0x61, 0x63, 0x6b, 0x65, 0x74, 0x73, 0x20, 0x77, \r
+ 0x69, 0x74, 0x68, 0x6f, 0x75, 0x74, 0x20, 0x41, 0x43, 0x4b, \r
+ 0x73, 0xd, 0xa, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, \r
+ 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x52, 0x65, 0x73, 0x65, \r
+ 0x74, 0x73, 0xd, 0xa, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, \r
+ 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x52, 0x65, 0x74, \r
+ 0x72, 0x61, 0x6e, 0x73, 0x6d, 0x69, 0x73, 0x73, 0x69, 0x6f, \r
+ 0x6e, 0x73, 0xd, 0xa, 0x9, 0x20, 0x20, 0x20, 0x20, 0x20, \r
+ 0x4e, 0x6f, 0x20, 0x63, 0x6f, 0x6e, 0x6e, 0x65, 0x63, 0x74, \r
+ 0x69, 0x6f, 0x6e, 0x20, 0x61, 0x76, 0x61, 0x6c, 0x69, 0x61, \r
+ 0x62, 0x6c, 0x65, 0xd, 0xa, 0x9, 0x20, 0x20, 0x20, 0x20, \r
+ 0x20, 0x43, 0x6f, 0x6e, 0x6e, 0x65, 0x63, 0x74, 0x69, 0x6f, \r
+ 0x6e, 0x20, 0x61, 0x74, 0x74, 0x65, 0x6d, 0x70, 0x74, 0x73, \r
+ 0x20, 0x74, 0x6f, 0x20, 0x63, 0x6c, 0x6f, 0x73, 0x65, 0x64, \r
+ 0x20, 0x70, 0x6f, 0x72, 0x74, 0x73, 0xd, 0xa, 0x3c, 0x2f, \r
+ 0x70, 0x72, 0x65, 0x3e, 0x3c, 0x2f, 0x66, 0x6f, 0x6e, 0x74, \r
+ 0x3e, 0x3c, 0x2f, 0x74, 0x64, 0x3e, 0x3c, 0x74, 0x64, 0x3e, \r
+ 0x3c, 0x70, 0x72, 0x65, 0x3e, 0x25, 0x21, 0x20, 0x6e, 0x65, \r
+ 0x74, 0x2d, 0x73, 0x74, 0x61, 0x74, 0x73, 0xd, 0xa, 0x3c, \r
+ 0x2f, 0x70, 0x72, 0x65, 0x3e, 0x3c, 0x2f, 0x74, 0x61, 0x62, \r
+ 0x6c, 0x65, 0x3e, 0xd, 0xa, 0x3c, 0x2f, 0x66, 0x6f, 0x6e, \r
+ 0x74, 0x3e, 0xd, 0xa, 0x3c, 0x2f, 0x62, 0x6f, 0x64, 0x79, \r
+ 0x3e, 0xd, 0xa, 0x3c, 0x2f, 0x68, 0x74, 0x6d, 0x6c, 0x3e, \r
+ 0xd, 0xa, 0};\r
+\r
+static const unsigned char data_tcp_shtml[] = {\r
+ /* /tcp.shtml */\r
+ 0x2f, 0x74, 0x63, 0x70, 0x2e, 0x73, 0x68, 0x74, 0x6d, 0x6c, 0,\r
+ 0x3c, 0x21, 0x44, 0x4f, 0x43, 0x54, 0x59, 0x50, 0x45, 0x20, \r
+ 0x48, 0x54, 0x4d, 0x4c, 0x20, 0x50, 0x55, 0x42, 0x4c, 0x49, \r
+ 0x43, 0x20, 0x22, 0x2d, 0x2f, 0x2f, 0x57, 0x33, 0x43, 0x2f, \r
+ 0x2f, 0x44, 0x54, 0x44, 0x20, 0x48, 0x54, 0x4d, 0x4c, 0x20, \r
+ 0x34, 0x2e, 0x30, 0x31, 0x20, 0x54, 0x72, 0x61, 0x6e, 0x73, \r
+ 0x69, 0x74, 0x69, 0x6f, 0x6e, 0x61, 0x6c, 0x2f, 0x2f, 0x45, \r
+ 0x4e, 0x22, 0x20, 0x22, 0x68, 0x74, 0x74, 0x70, 0x3a, 0x2f, \r
+ 0x2f, 0x77, 0x77, 0x77, 0x2e, 0x77, 0x33, 0x2e, 0x6f, 0x72, \r
+ 0x67, 0x2f, 0x54, 0x52, 0x2f, 0x68, 0x74, 0x6d, 0x6c, 0x34, \r
+ 0x2f, 0x6c, 0x6f, 0x6f, 0x73, 0x65, 0x2e, 0x64, 0x74, 0x64, \r
+ 0x22, 0x3e, 0xd, 0xa, 0x3c, 0x68, 0x74, 0x6d, 0x6c, 0x3e, \r
+ 0xd, 0xa, 0x20, 0x20, 0x3c, 0x68, 0x65, 0x61, 0x64, 0x3e, \r
+ 0xd, 0xa, 0x20, 0x20, 0x20, 0x20, 0x3c, 0x74, 0x69, 0x74, \r
+ 0x6c, 0x65, 0x3e, 0x46, 0x72, 0x65, 0x65, 0x52, 0x54, 0x4f, \r
+ 0x53, 0x2e, 0x6f, 0x72, 0x67, 0x20, 0x75, 0x49, 0x50, 0x20, \r
+ 0x57, 0x45, 0x42, 0x20, 0x73, 0x65, 0x72, 0x76, 0x65, 0x72, \r
+ 0x20, 0x64, 0x65, 0x6d, 0x6f, 0x3c, 0x2f, 0x74, 0x69, 0x74, \r
+ 0x6c, 0x65, 0x3e, 0xd, 0xa, 0x20, 0x20, 0x3c, 0x2f, 0x68, \r
+ 0x65, 0x61, 0x64, 0x3e, 0xd, 0xa, 0x20, 0x20, 0x3c, 0x42, \r
+ 0x4f, 0x44, 0x59, 0x20, 0x62, 0x67, 0x63, 0x6f, 0x6c, 0x6f, \r
+ 0x72, 0x3d, 0x22, 0x23, 0x43, 0x43, 0x43, 0x43, 0x66, 0x66, \r
+ 0x22, 0x3e, 0xd, 0xa, 0x3c, 0x66, 0x6f, 0x6e, 0x74, 0x20, \r
+ 0x66, 0x61, 0x63, 0x65, 0x3d, 0x22, 0x61, 0x72, 0x69, 0x61, \r
+ 0x6c, 0x22, 0x3e, 0xd, 0xa, 0x3c, 0x61, 0x20, 0x68, 0x72, \r
+ 0x65, 0x66, 0x3d, 0x22, 0x69, 0x6e, 0x64, 0x65, 0x78, 0x2e, \r
+ 0x73, 0x68, 0x74, 0x6d, 0x6c, 0x22, 0x3e, 0x52, 0x54, 0x4f, \r
+ 0x53, 0x20, 0x53, 0x74, 0x61, 0x74, 0x73, 0x3c, 0x2f, 0x61, \r
+ 0x3e, 0x20, 0x3c, 0x62, 0x3e, 0x7c, 0x3c, 0x2f, 0x62, 0x3e, \r
+ 0x20, 0x3c, 0x61, 0x20, 0x68, 0x72, 0x65, 0x66, 0x3d, 0x22, \r
+ 0x73, 0x74, 0x61, 0x74, 0x73, 0x2e, 0x73, 0x68, 0x74, 0x6d, \r
+ 0x6c, 0x22, 0x3e, 0x54, 0x43, 0x50, 0x20, 0x53, 0x74, 0x61, \r
+ 0x74, 0x73, 0x3c, 0x2f, 0x61, 0x3e, 0x20, 0x3c, 0x62, 0x3e, \r
+ 0x7c, 0x3c, 0x2f, 0x62, 0x3e, 0x20, 0x3c, 0x61, 0x20, 0x68, \r
+ 0x72, 0x65, 0x66, 0x3d, 0x22, 0x74, 0x63, 0x70, 0x2e, 0x73, \r
+ 0x68, 0x74, 0x6d, 0x6c, 0x22, 0x3e, 0x43, 0x6f, 0x6e, 0x6e, \r
+ 0x65, 0x63, 0x74, 0x69, 0x6f, 0x6e, 0x73, 0x3c, 0x2f, 0x61, \r
+ 0x3e, 0x20, 0x3c, 0x62, 0x3e, 0x7c, 0x3c, 0x2f, 0x62, 0x3e, \r
+ 0x20, 0x3c, 0x61, 0x20, 0x68, 0x72, 0x65, 0x66, 0x3d, 0x22, \r
+ 0x68, 0x74, 0x74, 0x70, 0x3a, 0x2f, 0x2f, 0x77, 0x77, 0x77, \r
+ 0x2e, 0x66, 0x72, 0x65, 0x65, 0x72, 0x74, 0x6f, 0x73, 0x2e, \r
+ 0x6f, 0x72, 0x67, 0x2f, 0x22, 0x3e, 0x46, 0x72, 0x65, 0x65, \r
+ 0x52, 0x54, 0x4f, 0x53, 0x2e, 0x6f, 0x72, 0x67, 0x20, 0x48, \r
+ 0x6f, 0x6d, 0x65, 0x70, 0x61, 0x67, 0x65, 0x3c, 0x2f, 0x61, \r
+ 0x3e, 0x20, 0x3c, 0x62, 0x3e, 0x7c, 0x3c, 0x2f, 0x62, 0x3e, \r
+ 0x20, 0x3c, 0x61, 0x20, 0x68, 0x72, 0x65, 0x66, 0x3d, 0x22, \r
+ 0x69, 0x6f, 0x2e, 0x73, 0x68, 0x74, 0x6d, 0x6c, 0x22, 0x3e, \r
+ 0x49, 0x4f, 0x3c, 0x2f, 0x61, 0x3e, 0xd, 0xa, 0x3c, 0x62, \r
+ 0x72, 0x3e, 0x3c, 0x70, 0x3e, 0xd, 0xa, 0x3c, 0x68, 0x72, \r
+ 0x3e, 0xd, 0xa, 0x3c, 0x62, 0x72, 0x3e, 0xd, 0xa, 0x3c, \r
+ 0x68, 0x32, 0x3e, 0x4e, 0x65, 0x74, 0x77, 0x6f, 0x72, 0x6b, \r
+ 0x20, 0x63, 0x6f, 0x6e, 0x6e, 0x65, 0x63, 0x74, 0x69, 0x6f, \r
+ 0x6e, 0x73, 0x3c, 0x2f, 0x68, 0x32, 0x3e, 0xd, 0xa, 0x3c, \r
+ 0x70, 0x3e, 0xd, 0xa, 0x3c, 0x74, 0x61, 0x62, 0x6c, 0x65, \r
+ 0x3e, 0xd, 0xa, 0x3c, 0x74, 0x72, 0x3e, 0x3c, 0x74, 0x68, \r
+ 0x3e, 0x4c, 0x6f, 0x63, 0x61, 0x6c, 0x3c, 0x2f, 0x74, 0x68, \r
+ 0x3e, 0x3c, 0x74, 0x68, 0x3e, 0x52, 0x65, 0x6d, 0x6f, 0x74, \r
+ 0x65, 0x3c, 0x2f, 0x74, 0x68, 0x3e, 0x3c, 0x74, 0x68, 0x3e, \r
+ 0x53, 0x74, 0x61, 0x74, 0x65, 0x3c, 0x2f, 0x74, 0x68, 0x3e, \r
+ 0x3c, 0x74, 0x68, 0x3e, 0x52, 0x65, 0x74, 0x72, 0x61, 0x6e, \r
+ 0x73, 0x6d, 0x69, 0x73, 0x73, 0x69, 0x6f, 0x6e, 0x73, 0x3c, \r
+ 0x2f, 0x74, 0x68, 0x3e, 0x3c, 0x74, 0x68, 0x3e, 0x54, 0x69, \r
+ 0x6d, 0x65, 0x72, 0x3c, 0x2f, 0x74, 0x68, 0x3e, 0x3c, 0x74, \r
+ 0x68, 0x3e, 0x46, 0x6c, 0x61, 0x67, 0x73, 0x3c, 0x2f, 0x74, \r
+ 0x68, 0x3e, 0x3c, 0x2f, 0x74, 0x72, 0x3e, 0xd, 0xa, 0x25, \r
+ 0x21, 0x20, 0x74, 0x63, 0x70, 0x2d, 0x63, 0x6f, 0x6e, 0x6e, \r
+ 0x65, 0x63, 0x74, 0x69, 0x6f, 0x6e, 0x73, 0xd, 0xa, 0x3c, \r
+ 0x2f, 0x70, 0x72, 0x65, 0x3e, 0x3c, 0x2f, 0x66, 0x6f, 0x6e, \r
+ 0x74, 0x3e, 0xd, 0xa, 0x3c, 0x2f, 0x66, 0x6f, 0x6e, 0x74, \r
+ 0x3e, 0xd, 0xa, 0x3c, 0x2f, 0x62, 0x6f, 0x64, 0x79, 0x3e, \r
+ 0xd, 0xa, 0x3c, 0x2f, 0x68, 0x74, 0x6d, 0x6c, 0x3e, 0xd, \r
+ 0xa, 0xd, 0xa, 0};\r
+\r
+const struct httpd_fsdata_file file_404_html[] = {{NULL, data_404_html, data_404_html + 10, sizeof(data_404_html) - 10}};\r
+\r
+const struct httpd_fsdata_file file_index_html[] = {{file_404_html, data_index_html, data_index_html + 12, sizeof(data_index_html) - 12}};\r
+\r
+const struct httpd_fsdata_file file_index_shtml[] = {{file_index_html, data_index_shtml, data_index_shtml + 13, sizeof(data_index_shtml) - 13}};\r
+\r
+const struct httpd_fsdata_file file_io_shtml[] = {{file_index_shtml, data_io_shtml, data_io_shtml + 10, sizeof(data_io_shtml) - 10}};\r
+\r
+const struct httpd_fsdata_file file_stats_shtml[] = {{file_io_shtml, data_stats_shtml, data_stats_shtml + 13, sizeof(data_stats_shtml) - 13}};\r
+\r
+const struct httpd_fsdata_file file_tcp_shtml[] = {{file_stats_shtml, data_tcp_shtml, data_tcp_shtml + 11, sizeof(data_tcp_shtml) - 11}};\r
+\r
+#define HTTPD_FS_ROOT file_tcp_shtml\r
+\r
+#define HTTPD_FS_NUMFILES 6\r
--- /dev/null
+/*\r
+ * Copyright (c) 2001, Swedish Institute of Computer Science.\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ * 1. Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the\r
+ * documentation and/or other materials provided with the distribution.\r
+ * 3. Neither the name of the Institute nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND\r
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\r
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\r
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\r
+ * SUCH DAMAGE.\r
+ *\r
+ * This file is part of the lwIP TCP/IP stack.\r
+ *\r
+ * Author: Adam Dunkels <adam@sics.se>\r
+ *\r
+ * $Id: httpd-fsdata.h,v 1.1 2006/06/07 09:13:08 adam Exp $\r
+ */\r
+#ifndef __HTTPD_FSDATA_H__\r
+#define __HTTPD_FSDATA_H__\r
+\r
+#include "uip.h"\r
+\r
+struct httpd_fsdata_file {\r
+ const struct httpd_fsdata_file *next;\r
+ const char *name;\r
+ const char *data;\r
+ const int len;\r
+#ifdef HTTPD_FS_STATISTICS\r
+#if HTTPD_FS_STATISTICS == 1\r
+ u16_t count;\r
+#endif /* HTTPD_FS_STATISTICS */\r
+#endif /* HTTPD_FS_STATISTICS */\r
+};\r
+\r
+struct httpd_fsdata_file_noconst {\r
+ struct httpd_fsdata_file *next;\r
+ char *name;\r
+ char *data;\r
+ int len;\r
+#ifdef HTTPD_FS_STATISTICS\r
+#if HTTPD_FS_STATISTICS == 1\r
+ u16_t count;\r
+#endif /* HTTPD_FS_STATISTICS */\r
+#endif /* HTTPD_FS_STATISTICS */\r
+};\r
+\r
+#endif /* __HTTPD_FSDATA_H__ */\r
--- /dev/null
+/**\r
+ * \addtogroup apps\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * \defgroup httpd Web server\r
+ * @{\r
+ * The uIP web server is a very simplistic implementation of an HTTP\r
+ * server. It can serve web pages and files from a read-only ROM\r
+ * filesystem, and provides a very small scripting language.\r
+\r
+ */\r
+\r
+/**\r
+ * \file\r
+ * Web server\r
+ * \author\r
+ * Adam Dunkels <adam@sics.se>\r
+ */\r
+\r
+\r
+/*\r
+ * Copyright (c) 2004, Adam Dunkels.\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ * 1. Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the\r
+ * documentation and/or other materials provided with the distribution.\r
+ * 3. Neither the name of the Institute nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND\r
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\r
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\r
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\r
+ * SUCH DAMAGE.\r
+ *\r
+ * This file is part of the uIP TCP/IP stack.\r
+ *\r
+ * Author: Adam Dunkels <adam@sics.se>\r
+ *\r
+ * $Id: httpd.c,v 1.2 2006/06/11 21:46:38 adam Exp $\r
+ */\r
+\r
+#include "uip.h"\r
+#include "httpd.h"\r
+#include "httpd-fs.h"\r
+#include "httpd-cgi.h"\r
+#include "http-strings.h"\r
+\r
+#include <string.h>\r
+\r
+#define STATE_WAITING 0\r
+#define STATE_OUTPUT 1\r
+\r
+#define ISO_nl 0x0a\r
+#define ISO_space 0x20\r
+#define ISO_bang 0x21\r
+#define ISO_percent 0x25\r
+#define ISO_period 0x2e\r
+#define ISO_slash 0x2f\r
+#define ISO_colon 0x3a\r
+\r
+\r
+/*---------------------------------------------------------------------------*/\r
+static unsigned short\r
+generate_part_of_file(void *state)\r
+{\r
+ struct httpd_state *s = (struct httpd_state *)state;\r
+\r
+ if(s->file.len > uip_mss()) {\r
+ s->len = uip_mss();\r
+ } else {\r
+ s->len = s->file.len;\r
+ }\r
+ memcpy(uip_appdata, s->file.data, s->len);\r
+ \r
+ return s->len;\r
+}\r
+/*---------------------------------------------------------------------------*/\r
+static\r
+PT_THREAD(send_file(struct httpd_state *s))\r
+{\r
+ PSOCK_BEGIN(&s->sout);\r
+ \r
+ do {\r
+ PSOCK_GENERATOR_SEND(&s->sout, generate_part_of_file, s);\r
+ s->file.len -= s->len;\r
+ s->file.data += s->len;\r
+ } while(s->file.len > 0);\r
+ \r
+ PSOCK_END(&s->sout);\r
+}\r
+/*---------------------------------------------------------------------------*/\r
+static\r
+PT_THREAD(send_part_of_file(struct httpd_state *s))\r
+{\r
+ PSOCK_BEGIN(&s->sout);\r
+\r
+ PSOCK_SEND(&s->sout, s->file.data, s->len);\r
+ \r
+ PSOCK_END(&s->sout);\r
+}\r
+/*---------------------------------------------------------------------------*/\r
+static void\r
+next_scriptstate(struct httpd_state *s)\r
+{\r
+ char *p;\r
+ p = strchr(s->scriptptr, ISO_nl) + 1;\r
+ s->scriptlen -= (unsigned short)(p - s->scriptptr);\r
+ s->scriptptr = p;\r
+}\r
+/*---------------------------------------------------------------------------*/\r
+static\r
+PT_THREAD(handle_script(struct httpd_state *s))\r
+{\r
+ char *ptr;\r
+ \r
+ PT_BEGIN(&s->scriptpt);\r
+\r
+\r
+ while(s->file.len > 0) {\r
+\r
+ /* Check if we should start executing a script. */\r
+ if(*s->file.data == ISO_percent &&\r
+ *(s->file.data + 1) == ISO_bang) {\r
+ s->scriptptr = s->file.data + 3;\r
+ s->scriptlen = s->file.len - 3;\r
+ if(*(s->scriptptr - 1) == ISO_colon) {\r
+ httpd_fs_open(s->scriptptr + 1, &s->file);\r
+ PT_WAIT_THREAD(&s->scriptpt, send_file(s));\r
+ } else {\r
+ PT_WAIT_THREAD(&s->scriptpt,\r
+ httpd_cgi(s->scriptptr)(s, s->scriptptr));\r
+ }\r
+ next_scriptstate(s);\r
+ \r
+ /* The script is over, so we reset the pointers and continue\r
+ sending the rest of the file. */\r
+ s->file.data = s->scriptptr;\r
+ s->file.len = s->scriptlen;\r
+ } else {\r
+ /* See if we find the start of script marker in the block of HTML\r
+ to be sent. */\r
+\r
+ if(s->file.len > uip_mss()) {\r
+ s->len = uip_mss();\r
+ } else {\r
+ s->len = s->file.len;\r
+ }\r
+\r
+ if(*s->file.data == ISO_percent) {\r
+ ptr = strchr(s->file.data + 1, ISO_percent);\r
+ } else {\r
+ ptr = strchr(s->file.data, ISO_percent);\r
+ }\r
+ if(ptr != NULL &&\r
+ ptr != s->file.data) {\r
+ s->len = (int)(ptr - s->file.data);\r
+ if(s->len >= uip_mss()) {\r
+ s->len = uip_mss();\r
+ }\r
+ }\r
+ PT_WAIT_THREAD(&s->scriptpt, send_part_of_file(s));\r
+ s->file.data += s->len;\r
+ s->file.len -= s->len;\r
+ \r
+ }\r
+ }\r
+ \r
+ PT_END(&s->scriptpt);\r
+}\r
+/*---------------------------------------------------------------------------*/\r
+static\r
+PT_THREAD(send_headers(struct httpd_state *s, const char *statushdr))\r
+{\r
+ char *ptr;\r
+\r
+ PSOCK_BEGIN(&s->sout);\r
+\r
+ PSOCK_SEND_STR(&s->sout, statushdr);\r
+\r
+ ptr = strrchr(s->filename, ISO_period);\r
+ if(ptr == NULL) {\r
+ PSOCK_SEND_STR(&s->sout, http_content_type_binary);\r
+ } else if(strncmp(http_html, ptr, 5) == 0 ||\r
+ strncmp(http_shtml, ptr, 6) == 0) {\r
+ PSOCK_SEND_STR(&s->sout, http_content_type_html);\r
+ } else if(strncmp(http_css, ptr, 4) == 0) {\r
+ PSOCK_SEND_STR(&s->sout, http_content_type_css);\r
+ } else if(strncmp(http_png, ptr, 4) == 0) {\r
+ PSOCK_SEND_STR(&s->sout, http_content_type_png);\r
+ } else if(strncmp(http_gif, ptr, 4) == 0) {\r
+ PSOCK_SEND_STR(&s->sout, http_content_type_gif);\r
+ } else if(strncmp(http_jpg, ptr, 4) == 0) {\r
+ PSOCK_SEND_STR(&s->sout, http_content_type_jpg);\r
+ } else {\r
+ PSOCK_SEND_STR(&s->sout, http_content_type_plain);\r
+ }\r
+ PSOCK_END(&s->sout);\r
+}\r
+/*---------------------------------------------------------------------------*/\r
+static\r
+PT_THREAD(handle_output(struct httpd_state *s))\r
+{\r
+ char *ptr;\r
+ \r
+ PT_BEGIN(&s->outputpt);\r
+ \r
+ if(!httpd_fs_open(s->filename, &s->file)) {\r
+ httpd_fs_open(http_404_html, &s->file);\r
+ strcpy(s->filename, http_404_html);\r
+ PT_WAIT_THREAD(&s->outputpt,\r
+ send_headers(s,\r
+ http_header_404));\r
+ PT_WAIT_THREAD(&s->outputpt,\r
+ send_file(s));\r
+ } else {\r
+ PT_WAIT_THREAD(&s->outputpt,\r
+ send_headers(s,\r
+ http_header_200));\r
+ ptr = strchr(s->filename, ISO_period);\r
+ if(ptr != NULL && strncmp(ptr, http_shtml, 6) == 0) {\r
+ PT_INIT(&s->scriptpt);\r
+ PT_WAIT_THREAD(&s->outputpt, handle_script(s));\r
+ } else {\r
+ PT_WAIT_THREAD(&s->outputpt,\r
+ send_file(s));\r
+ }\r
+ }\r
+ PSOCK_CLOSE(&s->sout);\r
+ PT_END(&s->outputpt);\r
+}\r
+/*---------------------------------------------------------------------------*/\r
+static\r
+PT_THREAD(handle_input(struct httpd_state *s))\r
+{\r
+ PSOCK_BEGIN(&s->sin);\r
+\r
+ PSOCK_READTO(&s->sin, ISO_space);\r
+\r
+ \r
+ if(strncmp(s->inputbuf, http_get, 4) != 0) {\r
+ PSOCK_CLOSE_EXIT(&s->sin);\r
+ }\r
+ PSOCK_READTO(&s->sin, ISO_space);\r
+\r
+ if(s->inputbuf[0] != ISO_slash) {\r
+ PSOCK_CLOSE_EXIT(&s->sin);\r
+ }\r
+\r
+ if(s->inputbuf[1] == ISO_space) {\r
+ strncpy(s->filename, http_index_html, sizeof(s->filename));\r
+ } else {\r
+\r
+ s->inputbuf[PSOCK_DATALEN(&s->sin) - 1] = 0;\r
+\r
+ /* Process any form input being sent to the server. */\r
+ {\r
+ extern void vApplicationProcessFormInput( char *pcInputString, long xInputLength );\r
+ vApplicationProcessFormInput( s->inputbuf, PSOCK_DATALEN(&s->sin) );\r
+ }\r
+\r
+ strncpy(s->filename, &s->inputbuf[0], sizeof(s->filename));\r
+ }\r
+\r
+ /* httpd_log_file(uip_conn->ripaddr, s->filename);*/\r
+ \r
+ s->state = STATE_OUTPUT;\r
+\r
+ while(1) {\r
+ PSOCK_READTO(&s->sin, ISO_nl);\r
+\r
+ if(strncmp(s->inputbuf, http_referer, 8) == 0) {\r
+ s->inputbuf[PSOCK_DATALEN(&s->sin) - 2] = 0;\r
+ /* httpd_log(&s->inputbuf[9]);*/\r
+ }\r
+ }\r
+ \r
+ PSOCK_END(&s->sin);\r
+}\r
+/*---------------------------------------------------------------------------*/\r
+static void\r
+handle_connection(struct httpd_state *s)\r
+{\r
+ handle_input(s);\r
+ if(s->state == STATE_OUTPUT) {\r
+ handle_output(s);\r
+ }\r
+}\r
+/*---------------------------------------------------------------------------*/\r
+void\r
+httpd_appcall(void)\r
+{\r
+ struct httpd_state *s = (struct httpd_state *)&(uip_conn->appstate);\r
+\r
+ if(uip_closed() || uip_aborted() || uip_timedout()) {\r
+ } else if(uip_connected()) {\r
+ PSOCK_INIT(&s->sin, s->inputbuf, sizeof(s->inputbuf) - 1);\r
+ PSOCK_INIT(&s->sout, s->inputbuf, sizeof(s->inputbuf) - 1);\r
+ PT_INIT(&s->outputpt);\r
+ s->state = STATE_WAITING;\r
+ /* timer_set(&s->timer, CLOCK_SECOND * 100);*/\r
+ s->timer = 0;\r
+ handle_connection(s);\r
+ } else if(s != NULL) {\r
+ if(uip_poll()) {\r
+ ++s->timer;\r
+ if(s->timer >= 20) {\r
+ uip_abort();\r
+ }\r
+ } else {\r
+ s->timer = 0;\r
+ }\r
+ handle_connection(s);\r
+ } else {\r
+ uip_abort();\r
+ }\r
+}\r
+/*---------------------------------------------------------------------------*/\r
+/**\r
+ * \brief Initialize the web server\r
+ *\r
+ * This function initializes the web server and should be\r
+ * called at system boot-up.\r
+ */\r
+void\r
+httpd_init(void)\r
+{\r
+ uip_listen(HTONS(80));\r
+}\r
+/*---------------------------------------------------------------------------*/\r
+/** @} */\r
--- /dev/null
+/*\r
+ * Copyright (c) 2001-2005, Adam Dunkels.\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ * 1. Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the\r
+ * documentation and/or other materials provided with the distribution.\r
+ * 3. The name of the author may not be used to endorse or promote\r
+ * products derived from this software without specific prior\r
+ * written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS\r
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\r
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY\r
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE\r
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\r
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\r
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * This file is part of the uIP TCP/IP stack.\r
+ *\r
+ * $Id: httpd.h,v 1.2 2006/06/11 21:46:38 adam Exp $\r
+ *\r
+ */\r
+\r
+#ifndef __HTTPD_H__\r
+#define __HTTPD_H__\r
+\r
+#include "psock.h"\r
+#include "httpd-fs.h"\r
+\r
+struct httpd_state {\r
+ unsigned char timer;\r
+ struct psock sin, sout;\r
+ struct pt outputpt, scriptpt;\r
+ char inputbuf[50];\r
+ char filename[20];\r
+ char state;\r
+ struct httpd_fs_file file;\r
+ int len;\r
+ char *scriptptr;\r
+ int scriptlen;\r
+ \r
+ unsigned short count;\r
+};\r
+\r
+void httpd_init(void);\r
+void httpd_appcall(void);\r
+\r
+void httpd_log(char *msg);\r
+void httpd_log_file(u16_t *requester, char *file);\r
+\r
+#endif /* __HTTPD_H__ */\r
--- /dev/null
+#!/usr/bin/perl\r
+\r
+open(OUTPUT, "> httpd-fsdata.c");\r
+\r
+chdir("httpd-fs");\r
+\r
+opendir(DIR, ".");\r
+@files = grep { !/^\./ && !/(CVS|~)/ } readdir(DIR);\r
+closedir(DIR);\r
+\r
+foreach $file (@files) { \r
+ \r
+ if(-d $file && $file !~ /^\./) {\r
+ print "Processing directory $file\n";\r
+ opendir(DIR, $file);\r
+ @newfiles = grep { !/^\./ && !/(CVS|~)/ } readdir(DIR);\r
+ closedir(DIR);\r
+ printf "Adding files @newfiles\n";\r
+ @files = (@files, map { $_ = "$file/$_" } @newfiles);\r
+ next;\r
+ }\r
+}\r
+\r
+foreach $file (@files) {\r
+ if(-f $file) {\r
+ \r
+ print "Adding file $file\n";\r
+ \r
+ open(FILE, $file) || die "Could not open file $file\n";\r
+\r
+ $file =~ s-^-/-;\r
+ $fvar = $file;\r
+ $fvar =~ s-/-_-g;\r
+ $fvar =~ s-\.-_-g;\r
+ # for AVR, add PROGMEM here\r
+ print(OUTPUT "static const unsigned char data".$fvar."[] = {\n");\r
+ print(OUTPUT "\t/* $file */\n\t");\r
+ for($j = 0; $j < length($file); $j++) {\r
+ printf(OUTPUT "%#02x, ", unpack("C", substr($file, $j, 1)));\r
+ }\r
+ printf(OUTPUT "0,\n");\r
+ \r
+ \r
+ $i = 0; \r
+ while(read(FILE, $data, 1)) {\r
+ if($i == 0) {\r
+ print(OUTPUT "\t");\r
+ }\r
+ printf(OUTPUT "%#02x, ", unpack("C", $data));\r
+ $i++;\r
+ if($i == 10) {\r
+ print(OUTPUT "\n");\r
+ $i = 0;\r
+ }\r
+ }\r
+ print(OUTPUT "0};\n\n");\r
+ close(FILE);\r
+ push(@fvars, $fvar);\r
+ push(@pfiles, $file);\r
+ }\r
+}\r
+\r
+for($i = 0; $i < @fvars; $i++) {\r
+ $file = $pfiles[$i];\r
+ $fvar = $fvars[$i];\r
+\r
+ if($i == 0) {\r
+ $prevfile = "NULL";\r
+ } else {\r
+ $prevfile = "file" . $fvars[$i - 1];\r
+ }\r
+ print(OUTPUT "const struct httpd_fsdata_file file".$fvar."[] = {{$prevfile, data$fvar, ");\r
+ print(OUTPUT "data$fvar + ". (length($file) + 1) .", ");\r
+ print(OUTPUT "sizeof(data$fvar) - ". (length($file) + 1) ."}};\n\n");\r
+}\r
+\r
+print(OUTPUT "#define HTTPD_FS_ROOT file$fvars[$i - 1]\n\n");\r
+print(OUTPUT "#define HTTPD_FS_NUMFILES $i\n");\r
--- /dev/null
+#!/usr/bin/perl\r
+\r
+\r
+sub stringify {\r
+ my $name = shift(@_);\r
+ open(OUTPUTC, "> $name.c");\r
+ open(OUTPUTH, "> $name.h");\r
+ \r
+ open(FILE, "$name");\r
+ \r
+ while(<FILE>) {\r
+ if(/(.+) "(.+)"/) {\r
+ $var = $1;\r
+ $data = $2;\r
+ \r
+ $datan = $data;\r
+ $datan =~ s/\\r/\r/g;\r
+ $datan =~ s/\\n/\n/g;\r
+ $datan =~ s/\\01/\01/g; \r
+ $datan =~ s/\\0/\0/g;\r
+ \r
+ printf(OUTPUTC "const char $var\[%d] = \n", length($datan) + 1);\r
+ printf(OUTPUTC "/* \"$data\" */\n");\r
+ printf(OUTPUTC "{");\r
+ for($j = 0; $j < length($datan); $j++) {\r
+ printf(OUTPUTC "%#02x, ", unpack("C", substr($datan, $j, 1)));\r
+ }\r
+ printf(OUTPUTC "};\n");\r
+ \r
+ printf(OUTPUTH "extern const char $var\[%d];\n", length($datan) + 1);\r
+ \r
+ }\r
+ }\r
+ close(OUTPUTC);\r
+ close(OUTPUTH);\r
+}\r
+stringify("http-strings");\r
+\r
+exit 0;\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS.org V4.3.0 - Copyright (C) 2003-2007 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS.org distribution.\r
+\r
+ FreeRTOS.org is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS.org is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS.org; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS.org, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section\r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license\r
+ and contact details. Please ensure to read the configuration and relevant\r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+/* Standard includes. */\r
+#include <string.h>\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "semphr.h"\r
+\r
+#include "lcd_message.h"\r
+\r
+/* uip includes. */\r
+#include "hw_types.h"\r
+\r
+#include "uip.h"\r
+#include "uip_arp.h"\r
+#include "httpd.h"\r
+#include "timer.h"\r
+#include "clock-arch.h"\r
+#include "hw_ethernet.h"\r
+#include "ethernet.h"\r
+#include "hw_memmap.h"\r
+#include "lmi_flash.h"\r
+\r
+/* Demo includes. */\r
+#include "emac.h"\r
+#include "partest.h"\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* IP address configuration. */\r
+#define uipIP_ADDR0 172\r
+#define uipIP_ADDR1 25\r
+#define uipIP_ADDR2 218\r
+#define uipIP_ADDR3 9 \r
+\r
+/* How long to wait before attempting to connect the MAC again. */\r
+#define uipINIT_WAIT 100\r
+\r
+/* Shortcut to the header within the Rx buffer. */\r
+#define xHeader ((struct uip_eth_hdr *) &uip_buf[ 0 ])\r
+\r
+/* Standard constant. */\r
+#define uipTOTAL_FRAME_HEADER_SIZE 54\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Send the uIP buffer to the MAC.\r
+ */\r
+static void prvENET_Send(void);\r
+\r
+/*\r
+ * Setup the MAC address in the MAC itself, and in the uIP stack.\r
+ */\r
+static void prvSetMACAddress( void );\r
+\r
+/*\r
+ * Port functions required by the uIP stack.\r
+ */\r
+void clock_init( void );\r
+clock_time_t clock_time( void );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* The semaphore used by the ISR to wake the uIP task. */\r
+extern xSemaphoreHandle xEMACSemaphore;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void clock_init(void)\r
+{\r
+ /* This is done when the scheduler starts. */\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+clock_time_t clock_time( void )\r
+{\r
+ return xTaskGetTickCount();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vuIP_Task( void *pvParameters )\r
+{\r
+portBASE_TYPE i;\r
+uip_ipaddr_t xIPAddr;\r
+struct timer periodic_timer, arp_timer;\r
+extern void ( vEMAC_ISR )( void );\r
+\r
+ /* Create the semaphore used by the ISR to wake this task. */\r
+ vSemaphoreCreateBinary( xEMACSemaphore );\r
+ \r
+ /* Initialise the uIP stack. */\r
+ timer_set( &periodic_timer, configTICK_RATE_HZ / 2 );\r
+ timer_set( &arp_timer, configTICK_RATE_HZ * 10 );\r
+ uip_init();\r
+ uip_ipaddr( xIPAddr, uipIP_ADDR0, uipIP_ADDR1, uipIP_ADDR2, uipIP_ADDR3 );\r
+ uip_sethostaddr( xIPAddr );\r
+ httpd_init();\r
+\r
+ while( vInitEMAC() != pdPASS )\r
+ {\r
+ vTaskDelay( uipINIT_WAIT );\r
+ }\r
+ prvSetMACAddress(); \r
+ \r
+\r
+ for( ;; )\r
+ {\r
+ /* Is there received data ready to be processed? */\r
+ uip_len = uiGetEMACRxData( uip_buf );\r
+ \r
+ if( uip_len > 0 )\r
+ {\r
+ /* Standard uIP loop taken from the uIP manual. */\r
+\r
+ if( xHeader->type == htons( UIP_ETHTYPE_IP ) )\r
+ {\r
+ uip_arp_ipin();\r
+ uip_input();\r
+\r
+ /* If the above function invocation resulted in data that\r
+ should be sent out on the network, the global variable\r
+ uip_len is set to a value > 0. */\r
+ if( uip_len > 0 )\r
+ {\r
+ uip_arp_out();\r
+ prvENET_Send();\r
+ }\r
+ }\r
+ else if( xHeader->type == htons( UIP_ETHTYPE_ARP ) )\r
+ {\r
+ uip_arp_arpin();\r
+\r
+ /* If the above function invocation resulted in data that\r
+ should be sent out on the network, the global variable\r
+ uip_len is set to a value > 0. */\r
+ if( uip_len > 0 )\r
+ {\r
+ prvENET_Send();\r
+ }\r
+ }\r
+ }\r
+ else\r
+ {\r
+ if( timer_expired( &periodic_timer ) )\r
+ {\r
+ timer_reset( &periodic_timer );\r
+ for( i = 0; i < UIP_CONNS; i++ )\r
+ {\r
+ uip_periodic( i );\r
+ \r
+ /* If the above function invocation resulted in data that\r
+ should be sent out on the network, the global variable\r
+ uip_len is set to a value > 0. */\r
+ if( uip_len > 0 )\r
+ {\r
+ uip_arp_out();\r
+ prvENET_Send();\r
+ }\r
+ } \r
+ \r
+ /* Call the ARP timer function every 10 seconds. */\r
+ if( timer_expired( &arp_timer ) )\r
+ {\r
+ timer_reset( &arp_timer );\r
+ uip_arp_timer();\r
+ }\r
+ }\r
+ else\r
+ { \r
+ /* We did not receive a packet, and there was no periodic\r
+ processing to perform. Block for a fixed period. If a packet\r
+ is received during this period we will be woken by the ISR\r
+ giving us the Semaphore. */\r
+ xSemaphoreTake( xEMACSemaphore, configTICK_RATE_HZ / 2 ); \r
+ }\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvENET_Send(void)\r
+{\r
+ vInitialiseSend();\r
+ vIncrementTxLength( uip_len );\r
+ vSendBufferToMAC();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvSetMACAddress( void )\r
+{\r
+unsigned portLONG ulUser0, ulUser1;\r
+unsigned char pucMACArray[8];\r
+struct uip_eth_addr xAddr;\r
+\r
+ /* Get the device MAC address from flash */\r
+ FlashUserGet(&ulUser0, &ulUser1);\r
+\r
+ /* Convert the MAC address from flash into sequence of bytes. */\r
+ pucMACArray[0] = ((ulUser0 >> 0) & 0xff);\r
+ pucMACArray[1] = ((ulUser0 >> 8) & 0xff);\r
+ pucMACArray[2] = ((ulUser0 >> 16) & 0xff);\r
+ pucMACArray[3] = ((ulUser1 >> 0) & 0xff);\r
+ pucMACArray[4] = ((ulUser1 >> 8) & 0xff);\r
+ pucMACArray[5] = ((ulUser1 >> 16) & 0xff);\r
+\r
+ /* Program the MAC address. */\r
+ EthernetMACAddrSet(ETH_BASE, pucMACArray);\r
+\r
+ xAddr.addr[ 0 ] = pucMACArray[0];\r
+ xAddr.addr[ 1 ] = pucMACArray[1];\r
+ xAddr.addr[ 2 ] = pucMACArray[2];\r
+ xAddr.addr[ 3 ] = pucMACArray[3];\r
+ xAddr.addr[ 4 ] = pucMACArray[4];\r
+ xAddr.addr[ 5 ] = pucMACArray[5];\r
+ uip_setethaddr( xAddr );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationProcessFormInput( portCHAR *pcInputString, portBASE_TYPE xInputLength )\r
+{\r
+char *c, *pcText;\r
+static portCHAR cMessageForDisplay[ 32 ];\r
+extern xQueueHandle xOLEDQueue;\r
+xOLEDMessage xOLEDMessage;\r
+\r
+ /* Process the form input sent by the IO page of the served HTML. */\r
+\r
+ c = strstr( pcInputString, "?" );\r
+\r
+ if( c )\r
+ {\r
+ /* Turn LED's on or off in accordance with the check box status. */\r
+ if( strstr( c, "LED0=1" ) != NULL )\r
+ {\r
+ vParTestSetLED( 0, 1 );\r
+ }\r
+ else\r
+ {\r
+ vParTestSetLED( 0, 0 );\r
+ } \r
+ \r
+ /* Find the start of the text to be displayed on the LCD. */\r
+ pcText = strstr( c, "LCD=" );\r
+ pcText += strlen( "LCD=" );\r
+\r
+ /* Terminate the file name for further processing within uIP. */\r
+ *c = 0x00;\r
+\r
+ /* Terminate the LCD string. */\r
+ c = strstr( pcText, " " );\r
+ if( c != NULL )\r
+ {\r
+ *c = 0x00;\r
+ }\r
+\r
+ /* Add required spaces. */\r
+ while( ( c = strstr( pcText, "+" ) ) != NULL )\r
+ {\r
+ *c = ' ';\r
+ }\r
+\r
+ /* Write the message to the LCD. */\r
+ strcpy( cMessageForDisplay, pcText );\r
+ xOLEDMessage.pcMessage = cMessageForDisplay;\r
+ xQueueSend( xOLEDQueue, &xOLEDMessage, portMAX_DELAY );\r
+ }\r
+}\r
+\r
--- /dev/null
+/**\r
+ * \addtogroup uipopt\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * \name Project-specific configuration options\r
+ * @{\r
+ *\r
+ * uIP has a number of configuration options that can be overridden\r
+ * for each project. These are kept in a project-specific uip-conf.h\r
+ * file and all configuration names have the prefix UIP_CONF.\r
+ */\r
+\r
+/*\r
+ * Copyright (c) 2006, Swedish Institute of Computer Science.\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ * 1. Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the\r
+ * documentation and/or other materials provided with the distribution.\r
+ * 3. Neither the name of the Institute nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND\r
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\r
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\r
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\r
+ * SUCH DAMAGE.\r
+ *\r
+ * This file is part of the uIP TCP/IP stack\r
+ *\r
+ * $Id: uip-conf.h,v 1.6 2006/06/12 08:00:31 adam Exp $\r
+ */\r
+\r
+/**\r
+ * \file\r
+ * An example uIP configuration file\r
+ * \author\r
+ * Adam Dunkels <adam@sics.se>\r
+ */\r
+\r
+#ifndef __UIP_CONF_H__\r
+#define __UIP_CONF_H__\r
+\r
+#include <stdint.h>\r
+\r
+/**\r
+ * 8 bit datatype\r
+ *\r
+ * This typedef defines the 8-bit type used throughout uIP.\r
+ *\r
+ * \hideinitializer\r
+ */\r
+typedef uint8_t u8_t;\r
+\r
+/**\r
+ * 16 bit datatype\r
+ *\r
+ * This typedef defines the 16-bit type used throughout uIP.\r
+ *\r
+ * \hideinitializer\r
+ */\r
+typedef uint16_t u16_t;\r
+\r
+/**\r
+ * Statistics datatype\r
+ *\r
+ * This typedef defines the dataype used for keeping statistics in\r
+ * uIP.\r
+ *\r
+ * \hideinitializer\r
+ */\r
+typedef unsigned short uip_stats_t;\r
+\r
+/**\r
+ * Maximum number of TCP connections.\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define UIP_CONF_MAX_CONNECTIONS 40\r
+\r
+/**\r
+ * Maximum number of listening TCP ports.\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define UIP_CONF_MAX_LISTENPORTS 40\r
+\r
+/**\r
+ * uIP buffer size.\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define UIP_CONF_BUFFER_SIZE 1500\r
+\r
+/**\r
+ * CPU byte order.\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define UIP_CONF_BYTE_ORDER LITTLE_ENDIAN\r
+\r
+/**\r
+ * Logging on or off\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define UIP_CONF_LOGGING 0\r
+\r
+/**\r
+ * UDP support on or off\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define UIP_CONF_UDP 0\r
+\r
+/**\r
+ * UDP checksums on or off\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define UIP_CONF_UDP_CHECKSUMS 1\r
+\r
+/**\r
+ * uIP statistics on or off\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define UIP_CONF_STATISTICS 1\r
+\r
+/* Here we include the header file for the application(s) we use in\r
+ our project. */\r
+/*#include "smtp.h"*/\r
+/*#include "hello-world.h"*/\r
+/*#include "telnetd.h"*/\r
+#include "webserver.h"\r
+/*#include "dhcpc.h"*/\r
+/*#include "resolv.h"*/\r
+/*#include "webclient.h"*/\r
+\r
+#define UIP_CONF_EXTERNAL_BUFFER\r
+\r
+#endif /* __UIP_CONF_H__ */\r
+\r
+/** @} */\r
+/** @} */\r
--- /dev/null
+/*\r
+ * Copyright (c) 2002, Adam Dunkels.\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ * 1. Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above\r
+ * copyright notice, this list of conditions and the following\r
+ * disclaimer in the documentation and/or other materials provided\r
+ * with the distribution.\r
+ * 3. The name of the author may not be used to endorse or promote\r
+ * products derived from this software without specific prior\r
+ * written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS\r
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\r
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY\r
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE\r
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\r
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\r
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * This file is part of the uIP TCP/IP stack\r
+ *\r
+ * $Id: webserver.h,v 1.2 2006/06/11 21:46:38 adam Exp $\r
+ *\r
+ */\r
+#ifndef __WEBSERVER_H__\r
+#define __WEBSERVER_H__\r
+\r
+#include "httpd.h"\r
+\r
+typedef struct httpd_state uip_tcp_appstate_t;\r
+/* UIP_APPCALL: the name of the application function. This function\r
+ must return void and take no arguments (i.e., C type "void\r
+ appfunc(void)"). */\r
+#ifndef UIP_APPCALL\r
+#define UIP_APPCALL httpd_appcall\r
+#endif\r
+\r
+\r
+#endif /* __WEBSERVER_H__ */\r
--- /dev/null
+/*\r
+ FreeRTOS.org V4.3.0 - Copyright (C) 2003-2007 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS.org distribution.\r
+\r
+ FreeRTOS.org is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS.org is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS.org; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS.org, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section\r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license\r
+ and contact details. Please ensure to read the configuration and relevant\r
+ port sections of the online documentation.\r
+\r
+ Also see http://www.SafeRTOS.com for an IEC 61508 compliant version along\r
+ with commercial development and support options.\r
+ ***************************************************************************\r
+*/\r
+\r
+#ifndef FREERTOS_CONFIG_H\r
+#define FREERTOS_CONFIG_H\r
+\r
+/*-----------------------------------------------------------\r
+ * Application specific definitions.\r
+ *\r
+ * These definitions should be adjusted for your particular hardware and\r
+ * application requirements.\r
+ *\r
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE\r
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.\r
+ *----------------------------------------------------------*/\r
+\r
+#define configUSE_PREEMPTION 1\r
+#define configUSE_IDLE_HOOK 0\r
+#define configUSE_TICK_HOOK 0\r
+#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 50000000 )\r
+#define configTICK_RATE_HZ ( ( portTickType ) 1000 )\r
+#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 70 )\r
+#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 12000 ) )\r
+#define configMAX_TASK_NAME_LEN ( 12 )\r
+#define configUSE_TRACE_FACILITY 1\r
+#define configUSE_16_BIT_TICKS 0\r
+#define configIDLE_SHOULD_YIELD 0\r
+#define configUSE_CO_ROUTINES 1\r
+\r
+#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 5 )\r
+#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )\r
+\r
+/* Set the following definitions to 1 to include the API function, or zero\r
+to exclude the API function. */\r
+\r
+#define INCLUDE_vTaskPrioritySet 1\r
+#define INCLUDE_uxTaskPriorityGet 0\r
+#define INCLUDE_vTaskDelete 1\r
+#define INCLUDE_vTaskCleanUpResources 0\r
+#define INCLUDE_vTaskSuspend 1\r
+#define INCLUDE_vTaskDelayUntil 1\r
+#define INCLUDE_vTaskDelay 1\r
+\r
+\r
+#define configKERNEL_INTERRUPT_PRIORITY 255\r
+\r
+\r
+#endif /* FREERTOS_CONFIG_H */\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// LM3Sxxx.h - Header file for Luminary Micro LM3Sxxx microcontrollers.\r
+//\r
+// Copyright (c) 2006-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __LM3SXXX_H__\r
+#define __LM3SXXX_H__\r
+\r
+#include "hw_adc.h"\r
+#include "hw_comp.h"\r
+#include "hw_flash.h"\r
+#include "hw_gpio.h"\r
+#include "hw_i2c.h"\r
+#include "hw_ints.h"\r
+#include "hw_memmap.h"\r
+#include "hw_nvic.h"\r
+#include "hw_pwm.h"\r
+#include "hw_qei.h"\r
+#include "hw_ssi.h"\r
+#include "hw_sysctl.h"\r
+#include "hw_timer.h"\r
+#include "hw_types.h"\r
+#include "hw_uart.h"\r
+#include "hw_watchdog.h"\r
+#include "adc.h"\r
+#include "comp.h"\r
+#include "cpu.h"\r
+#include "debug.h"\r
+#include "flash.h"\r
+#include "gpio.h"\r
+#include "i2c.h"\r
+#include "interrupt.h"\r
+#include "pwm.h"\r
+#include "qei.h"\r
+#include "ssi.h"\r
+#include "sysctl.h"\r
+#include "systick.h"\r
+#include "timer.h"\r
+#include "uart.h"\r
+#include "watchdog.h"\r
+\r
+#endif // __LM3SXXX_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// LM3Sxxxx.h - Header file for Luminary Micro LM3Sxxxx microcontrollers.\r
+//\r
+// Copyright (c) 2006-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __LM3SXXXX_H__\r
+#define __LM3SXXXX_H__\r
+\r
+#include "hw_adc.h"\r
+#include "hw_can.h"\r
+#include "hw_comp.h"\r
+#include "hw_ethernet.h"\r
+#include "hw_flash.h"\r
+#include "hw_gpio.h"\r
+#include "hw_hibernate.h"\r
+#include "hw_i2c.h"\r
+#include "hw_ints.h"\r
+#include "hw_memmap.h"\r
+#include "hw_nvic.h"\r
+#include "hw_pwm.h"\r
+#include "hw_qei.h"\r
+#include "hw_ssi.h"\r
+#include "hw_sysctl.h"\r
+#include "hw_timer.h"\r
+#include "hw_types.h"\r
+#include "hw_uart.h"\r
+#include "hw_watchdog.h"\r
+#include "adc.h"\r
+#include "can.h"\r
+#include "comp.h"\r
+#include "cpu.h"\r
+#include "debug.h"\r
+#include "ethernet.h"\r
+#include "flash.h"\r
+#include "gpio.h"\r
+#include "hibernate.h"\r
+#include "i2c.h"\r
+#include "interrupt.h"\r
+#include "pwm.h"\r
+#include "qei.h"\r
+#include "ssi.h"\r
+#include "sysctl.h"\r
+#include "systick.h"\r
+#include "timer.h"\r
+#include "uart.h"\r
+#include "watchdog.h"\r
+\r
+#endif // __LM3SXXXX_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// flash.h - Prototypes for the flash driver.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __FLASH_H__\r
+#define __FLASH_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to FlashProtectSet(), and returned by\r
+// FlashProtectGet().\r
+//\r
+//*****************************************************************************\r
+typedef enum\r
+{\r
+ FlashReadWrite, // Flash can be read and written\r
+ FlashReadOnly, // Flash can only be read\r
+ FlashExecuteOnly // Flash can only be executed\r
+}\r
+tFlashProtection;\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+extern unsigned long FlashUsecGet(void);\r
+extern void FlashUsecSet(unsigned long ulClocks);\r
+extern long FlashErase(unsigned long ulAddress);\r
+extern long FlashProgram(unsigned long *pulData, unsigned long ulAddress,\r
+ unsigned long ulCount);\r
+extern tFlashProtection FlashProtectGet(unsigned long ulAddress);\r
+extern long FlashProtectSet(unsigned long ulAddress,\r
+ tFlashProtection eProtect);\r
+extern long FlashProtectSave(void);\r
+extern long FlashUserGet(unsigned long *pulUser0, unsigned long *pulUser1);\r
+extern long FlashUserSet(unsigned long ulUser0, unsigned long ulUser1);\r
+extern long FlashUserSave(void);\r
+extern void FlashIntRegister(void (*pfnHandler)(void));\r
+extern void FlashIntUnregister(void);\r
+extern void FlashIntEnable(unsigned long ulIntFlags);\r
+extern void FlashIntDisable(unsigned long ulIntFlags);\r
+extern unsigned long FlashIntGetStatus(tBoolean bMasked);\r
+extern void FlashIntClear(unsigned long ulIntFlags);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __FLASH_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// timer.h - Prototypes for the timer module\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __TIMER_H__\r
+#define __TIMER_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to TimerConfigure as the ulConfig parameter.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_CFG_32_BIT_OS 0x00000001 // 32-bit one-shot timer\r
+#define TIMER_CFG_32_BIT_PER 0x00000002 // 32-bit periodic timer\r
+#define TIMER_CFG_32_RTC 0x01000000 // 32-bit RTC timer\r
+#define TIMER_CFG_16_BIT_PAIR 0x04000000 // Two 16-bit timers\r
+#define TIMER_CFG_A_ONE_SHOT 0x00000001 // Timer A one-shot timer\r
+#define TIMER_CFG_A_PERIODIC 0x00000002 // Timer A periodic timer\r
+#define TIMER_CFG_A_CAP_COUNT 0x00000003 // Timer A event counter\r
+#define TIMER_CFG_A_CAP_TIME 0x00000007 // Timer A event timer\r
+#define TIMER_CFG_A_PWM 0x0000000A // Timer A PWM output\r
+#define TIMER_CFG_B_ONE_SHOT 0x00000100 // Timer B one-shot timer\r
+#define TIMER_CFG_B_PERIODIC 0x00000200 // Timer B periodic timer\r
+#define TIMER_CFG_B_CAP_COUNT 0x00000300 // Timer B event counter\r
+#define TIMER_CFG_B_CAP_TIME 0x00000700 // Timer B event timer\r
+#define TIMER_CFG_B_PWM 0x00000A00 // Timer B PWM output\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to TimerIntEnable, TimerIntDisable, and\r
+// TimerIntClear as the ulIntFlags parameter, and returned from TimerIntStatus.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_CAPB_EVENT 0x00000400 // CaptureB event interrupt\r
+#define TIMER_CAPB_MATCH 0x00000200 // CaptureB match interrupt\r
+#define TIMER_TIMB_TIMEOUT 0x00000100 // TimerB time out interrupt\r
+#define TIMER_RTC_MATCH 0x00000008 // RTC interrupt mask\r
+#define TIMER_CAPA_EVENT 0x00000004 // CaptureA event interrupt\r
+#define TIMER_CAPA_MATCH 0x00000002 // CaptureA match interrupt\r
+#define TIMER_TIMA_TIMEOUT 0x00000001 // TimerA time out interrupt\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to TimerControlEvent as the ulEvent parameter.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_EVENT_POS_EDGE 0x00000000 // Count positive edges\r
+#define TIMER_EVENT_NEG_EDGE 0x00000404 // Count negative edges\r
+#define TIMER_EVENT_BOTH_EDGES 0x00000C0C // Count both edges\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to most of the timer APIs as the ulTimer\r
+// parameter.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_A 0x000000ff // Timer A\r
+#define TIMER_B 0x0000ff00 // Timer B\r
+#define TIMER_BOTH 0x0000ffff // Timer Both\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+extern void TimerEnable(unsigned long ulBase, unsigned long ulTimer);\r
+extern void TimerDisable(unsigned long ulBase, unsigned long ulTimer);\r
+extern void TimerConfigure(unsigned long ulBase, unsigned long ulConfig);\r
+extern void TimerControlLevel(unsigned long ulBase, unsigned long ulTimer,\r
+ tBoolean bInvert);\r
+extern void TimerControlTrigger(unsigned long ulBase, unsigned long ulTimer,\r
+ tBoolean bEnable);\r
+extern void TimerControlEvent(unsigned long ulBase, unsigned long ulTimer,\r
+ unsigned long ulEvent);\r
+extern void TimerControlStall(unsigned long ulBase, unsigned long ulTimer,\r
+ tBoolean bStall);\r
+extern void TimerRTCEnable(unsigned long ulBase);\r
+extern void TimerRTCDisable(unsigned long ulBase);\r
+extern void TimerPrescaleSet(unsigned long ulBase, unsigned long ulTimer,\r
+ unsigned long ulValue);\r
+extern unsigned long TimerPrescaleGet(unsigned long ulBase,\r
+ unsigned long ulTimer);\r
+extern void TimerPrescaleMatchSet(unsigned long ulBase, unsigned long ulTimer,\r
+ unsigned long ulValue);\r
+extern unsigned long TimerPrescaleMatchGet(unsigned long ulBase,\r
+ unsigned long ulTimer);\r
+extern void TimerLoadSet(unsigned long ulBase, unsigned long ulTimer,\r
+ unsigned long ulValue);\r
+extern unsigned long TimerLoadGet(unsigned long ulBase, unsigned long ulTimer);\r
+extern unsigned long TimerValueGet(unsigned long ulBase,\r
+ unsigned long ulTimer);\r
+extern void TimerMatchSet(unsigned long ulBase, unsigned long ulTimer,\r
+ unsigned long ulValue);\r
+extern unsigned long TimerMatchGet(unsigned long ulBase,\r
+ unsigned long ulTimer);\r
+extern void TimerIntRegister(unsigned long ulBase, unsigned long ulTimer,\r
+ void (*pfnHandler)(void));\r
+extern void TimerIntUnregister(unsigned long ulBase, unsigned long ulTimer);\r
+extern void TimerIntEnable(unsigned long ulBase, unsigned long ulIntFlags);\r
+extern void TimerIntDisable(unsigned long ulBase, unsigned long ulIntFlags);\r
+extern unsigned long TimerIntStatus(unsigned long ulBase, tBoolean bMasked);\r
+extern void TimerIntClear(unsigned long ulBase, unsigned long ulIntFlags);\r
+extern void TimerQuiesce(unsigned long ulBase);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __TIMER_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// adc.h - ADC headers for using the ADC driver functions.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __ADC_H__\r
+#define __ADC_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to ADCSequenceConfigure as the ulTrigger\r
+// parameter.\r
+//\r
+//*****************************************************************************\r
+#define ADC_TRIGGER_PROCESSOR 0x00000000 // Processor event\r
+#define ADC_TRIGGER_COMP0 0x00000001 // Analog comparator 0 event\r
+#define ADC_TRIGGER_COMP1 0x00000002 // Analog comparator 1 event\r
+#define ADC_TRIGGER_COMP2 0x00000003 // Analog comparator 2 event\r
+#define ADC_TRIGGER_EXTERNAL 0x00000004 // External event\r
+#define ADC_TRIGGER_TIMER 0x00000005 // Timer event\r
+#define ADC_TRIGGER_PWM0 0x00000006 // PWM0 event\r
+#define ADC_TRIGGER_PWM1 0x00000007 // PWM1 event\r
+#define ADC_TRIGGER_PWM2 0x00000008 // PWM2 event\r
+#define ADC_TRIGGER_ALWAYS 0x0000000F // Always event\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to ADCSequenceStepConfigure as the ulConfig\r
+// parameter.\r
+//\r
+//*****************************************************************************\r
+#define ADC_CTL_TS 0x00000080 // Temperature sensor select\r
+#define ADC_CTL_IE 0x00000040 // Interrupt enable\r
+#define ADC_CTL_END 0x00000020 // Sequence end select\r
+#define ADC_CTL_D 0x00000010 // Differential select\r
+#define ADC_CTL_CH0 0x00000000 // Input channel 0\r
+#define ADC_CTL_CH1 0x00000001 // Input channel 1\r
+#define ADC_CTL_CH2 0x00000002 // Input channel 2\r
+#define ADC_CTL_CH3 0x00000003 // Input channel 3\r
+#define ADC_CTL_CH4 0x00000004 // Input channel 4\r
+#define ADC_CTL_CH5 0x00000005 // Input channel 5\r
+#define ADC_CTL_CH6 0x00000006 // Input channel 6\r
+#define ADC_CTL_CH7 0x00000007 // Input channel 7\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+extern void ADCIntRegister(unsigned long ulBase, unsigned long ulSequenceNum,\r
+ void (*pfnHandler)(void));\r
+extern void ADCIntUnregister(unsigned long ulBase,\r
+ unsigned long ulSequenceNum);\r
+extern void ADCIntDisable(unsigned long ulBase, unsigned long ulSequenceNum);\r
+extern void ADCIntEnable(unsigned long ulBase, unsigned long ulSequenceNum);\r
+extern unsigned long ADCIntStatus(unsigned long ulBase,\r
+ unsigned long ulSequenceNum,\r
+ tBoolean bMasked);\r
+extern void ADCIntClear(unsigned long ulBase, unsigned long ulSequenceNum);\r
+extern void ADCSequenceEnable(unsigned long ulBase,\r
+ unsigned long ulSequenceNum);\r
+extern void ADCSequenceDisable(unsigned long ulBase,\r
+ unsigned long ulSequenceNum);\r
+extern void ADCSequenceConfigure(unsigned long ulBase,\r
+ unsigned long ulSequenceNum,\r
+ unsigned long ulTrigger,\r
+ unsigned long ulPriority);\r
+extern void ADCSequenceStepConfigure(unsigned long ulBase,\r
+ unsigned long ulSequenceNum,\r
+ unsigned long ulStep,\r
+ unsigned long ulConfig);\r
+extern long ADCSequenceOverflow(unsigned long ulBase,\r
+ unsigned long ulSequenceNum);\r
+extern void ADCSequenceOverflowClear(unsigned long ulBase,\r
+ unsigned long ulSequenceNum);\r
+extern long ADCSequenceUnderflow(unsigned long ulBase,\r
+ unsigned long ulSequenceNum);\r
+extern void ADCSequenceUnderflowClear(unsigned long ulBase,\r
+ unsigned long ulSequenceNum);\r
+extern long ADCSequenceDataGet(unsigned long ulBase,\r
+ unsigned long ulSequenceNum,\r
+ unsigned long *pulBuffer);\r
+extern void ADCProcessorTrigger(unsigned long ulBase,\r
+ unsigned long ulSequenceNum);\r
+extern void ADCSoftwareOversampleConfigure(unsigned long ulBase,\r
+ unsigned long ulSequenceNum,\r
+ unsigned long ulFactor);\r
+extern void ADCSoftwareOversampleStepConfigure(unsigned long ulBase,\r
+ unsigned long ulSequenceNum,\r
+ unsigned long ulStep,\r
+ unsigned long ulConfig);\r
+extern void ADCSoftwareOversampleDataGet(unsigned long ulBase,\r
+ unsigned long ulSequenceNum,\r
+ unsigned long *pulBuffer,\r
+ unsigned long ulCount);\r
+extern void ADCHardwareOversampleConfigure(unsigned long ulBase,\r
+ unsigned long ulFactor);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __ADC_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// can.h - Defines and Macros for the CAN controller.\r
+//\r
+// Copyright (c) 2006-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __CAN_H__\r
+#define __CAN_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! \addtogroup can_api\r
+//! @{\r
+//\r
+//*****************************************************************************\r
+\r
+//*****************************************************************************\r
+//\r
+// Miscellaneous defines for Message ID Types\r
+//\r
+//*****************************************************************************\r
+\r
+//*****************************************************************************\r
+//\r
+//! These are the flags used by the tCANMsgObject variable when calling the\r
+//! the CANMessageSet() and CANMessageGet() APIs.\r
+//\r
+//*****************************************************************************\r
+typedef enum\r
+{\r
+ //\r
+ //! This indicates that transmit interrupts should be enabled, or are\r
+ //! enabled.\r
+ //\r
+ MSG_OBJ_TX_INT_ENABLE = 0x00000001,\r
+\r
+ //\r
+ //! This indicates that receive interrupts should be enabled or are\r
+ //! enabled.\r
+ //\r
+ MSG_OBJ_RX_INT_ENABLE = 0x00000002,\r
+\r
+ //\r
+ //! This indicates that a message object will use or is using an extended\r
+ //! identifier.\r
+ //\r
+ MSG_OBJ_EXTENDED_ID = 0x00000004,\r
+\r
+ //\r
+ //! This indicates that a message object will use or is using filtering\r
+ //! based on the object's message Identifier.\r
+ //\r
+ MSG_OBJ_USE_ID_FILTER = 0x00000008,\r
+\r
+ //\r
+ //! This indicates that new data was available in the message object.\r
+ //\r
+ MSG_OBJ_NEW_DATA = 0x00000080,\r
+\r
+ //\r
+ //! This indicates that data was lost since this message object was last\r
+ //! read.\r
+ //\r
+ MSG_OBJ_DATA_LOST = 0x00000100,\r
+\r
+ //\r
+ //! This indicates that a message object will use or is using filtering\r
+ //! based on the direction of the transfer. If the direction filtering is\r
+ //! used then ID filtering must also be enabled.\r
+ //\r
+ MSG_OBJ_USE_DIR_FILTER = (0x00000010 | MSG_OBJ_USE_ID_FILTER),\r
+\r
+ //\r
+ //! This indicates that a message object will use or is using message\r
+ //! identifier filtering based of the the extended identifier.\r
+ //! If the extended identifier filtering is used then ID filtering must\r
+ //! also be enabled.\r
+ //\r
+ MSG_OBJ_USE_EXT_FILTER = (0x00000020 | MSG_OBJ_USE_ID_FILTER),\r
+\r
+ //\r
+ //! This indicates that a message object is a remote frame.\r
+ //\r
+ MSG_OBJ_REMOTE_FRAME = 0x00000040,\r
+\r
+ //\r
+ //! This indicates that a message object has no flags set.\r
+ //\r
+ MSG_OBJ_NO_FLAGS = 0x00000000\r
+}\r
+tCANObjFlags;\r
+\r
+//*****************************************************************************\r
+//\r
+//! This define is used with the #tCANObjFlags enumerated values to allow\r
+//! checking only status flags and not configuration flags.\r
+//\r
+//*****************************************************************************\r
+#define MSG_OBJ_STATUS_MASK (MSG_OBJ_NEW_DATA | MSG_OBJ_DATA_LOST)\r
+\r
+//*****************************************************************************\r
+//\r
+//! This structure used for encapsulating all the items associated with a CAN\r
+//! message object in the CAN controller.\r
+//\r
+//*****************************************************************************\r
+typedef struct\r
+{\r
+ //\r
+ //! The CAN message identifier used for 11 or 29 bit identifiers.\r
+ //\r
+ unsigned long ulMsgID;\r
+\r
+ //\r
+ //! The message identifier mask used when identifier filtering is enabled.\r
+ //\r
+ unsigned long ulMsgIDMask;\r
+\r
+ //\r
+ //! This value holds various status flags and settings specified by\r
+ //! tCANObjFlags.\r
+ //\r
+ unsigned long ulFlags;\r
+\r
+ //\r
+ //! This value is the number of bytes of data in the message object.\r
+ //\r
+ unsigned long ulMsgLen;\r
+\r
+ //\r
+ //! This is a pointer to the message object's data.\r
+ //\r
+ unsigned char *pucMsgData;\r
+}\r
+tCANMsgObject;\r
+\r
+//*****************************************************************************\r
+//\r
+//! This structure is used for encapsulating the values associated with setting\r
+//! up the bit timing for a CAN controller. The structure is used when calling\r
+//! the CANGetBitTiming and CANSetBitTiming functions.\r
+//\r
+//*****************************************************************************\r
+typedef struct\r
+{\r
+ //\r
+ //! This value holds the sum of the Synchronization, Propagation, and Phase\r
+ //! Buffer 1 segments, measured in time quanta. The valid values for this\r
+ //! setting range from 2 to 16.\r
+ //\r
+ unsigned int uSyncPropPhase1Seg;\r
+\r
+ //\r
+ //! This value holds the Phase Buffer 2 segment in time quanta. The valid\r
+ //! values for this setting range from 1 to 8.\r
+ //\r
+ unsigned int uPhase2Seg;\r
+\r
+ //\r
+ //! This value holds the Resynchronization Jump Width in time quanta. The\r
+ //! valid values for this setting range from 1 to 4.\r
+ //\r
+ unsigned int uSJW;\r
+\r
+ //\r
+ //! This value holds the CAN_CLK divider used to determine time quanta.\r
+ //! The valid values for this setting range from 1 to 1023.\r
+ //\r
+ unsigned int uQuantumPrescaler;\r
+\r
+}\r
+tCANBitClkParms;\r
+\r
+//*****************************************************************************\r
+//\r
+//! This data type is used to identify the interrupt status register. This is\r
+//! used when calling the a CANIntStatus() function.\r
+//\r
+//*****************************************************************************\r
+typedef enum\r
+{\r
+ //\r
+ //! Read the CAN interrupt status information.\r
+ //\r
+ CAN_INT_STS_CAUSE,\r
+\r
+ //\r
+ //! Read a message object's interrupt status.\r
+ //\r
+ CAN_INT_STS_OBJECT\r
+}\r
+tCANIntStsReg;\r
+\r
+//*****************************************************************************\r
+//\r
+//! This data type is used to identify which of the several status registers\r
+//! to read when calling the CANStatusGet() function.\r
+//\r
+//*****************************************************************************\r
+typedef enum\r
+{\r
+ //\r
+ //! Read the full CAN controller status.\r
+ //\r
+ CAN_STS_CONTROL,\r
+\r
+ //\r
+ //! Read the full 32 bit mask of message objects with a transmit request\r
+ //! set.\r
+ //\r
+ CAN_STS_TXREQUEST,\r
+\r
+ //\r
+ //! Read the full 32 bit mask of message objects with a new data available.\r
+ //\r
+ CAN_STS_NEWDAT,\r
+\r
+ //\r
+ //! Read the full 32 bit mask of message objects that are enabled.\r
+ //\r
+ CAN_STS_MSGVAL\r
+}\r
+tCANStsReg;\r
+\r
+//*****************************************************************************\r
+//\r
+//! These definitions are used to specify interrupt sources to CANIntEnable()\r
+//! and CANIntDisable().\r
+//\r
+//*****************************************************************************\r
+typedef enum\r
+{\r
+ //\r
+ //! This flag is used to allow a CAN controller to generate error\r
+ //! interrupts.\r
+ //\r
+ CAN_INT_ERROR = 0x00000008,\r
+\r
+ //\r
+ //! This flag is used to allow a CAN controller to generate status\r
+ //! interrupts.\r
+ //\r
+ CAN_INT_STATUS = 0x00000004,\r
+\r
+ //\r
+ //! This flag is used to allow a CAN controller to generate any CAN\r
+ //! interrupts. If this is not set then no interrupts will be generated by\r
+ //! the CAN controller.\r
+ //\r
+ CAN_INT_MASTER = 0x00000002\r
+}\r
+tCANIntFlags;\r
+\r
+//*****************************************************************************\r
+//\r
+//! This definition is used to determine the type of message object that will\r
+//! be set up via a call to the CANMessageSet() API.\r
+//\r
+//*****************************************************************************\r
+typedef enum\r
+{\r
+ //\r
+ //! Transmit message object.\r
+ //\r
+ MSG_OBJ_TYPE_TX,\r
+\r
+ //\r
+ //! Transmit remote request message object\r
+ //\r
+ MSG_OBJ_TYPE_TX_REMOTE,\r
+\r
+ //\r
+ //! Receive message object.\r
+ //\r
+ MSG_OBJ_TYPE_RX,\r
+\r
+ //\r
+ //! Receive remote request message object.\r
+ //\r
+ MSG_OBJ_TYPE_RX_REMOTE,\r
+\r
+ //\r
+ //! Remote frame receive remote, with auto-transmit message object.\r
+ //\r
+ MSG_OBJ_TYPE_RXTX_REMOTE\r
+}\r
+tMsgObjType;\r
+\r
+//*****************************************************************************\r
+//\r
+//! The following enumeration contains all error or status indicators that\r
+//! can be returned when calling the CANStatusGet() API.\r
+//\r
+//*****************************************************************************\r
+typedef enum\r
+{\r
+ //\r
+ //! CAN controller has entered a Bus Off state.\r
+ //\r
+ CAN_STATUS_BUS_OFF = 0x00000080,\r
+\r
+ //\r
+ //! CAN controller error level has reached warning level.\r
+ //\r
+ CAN_STATUS_EWARN = 0x00000040,\r
+\r
+ //\r
+ //! CAN controller error level has reached error passive level.\r
+ //\r
+ CAN_STATUS_EPASS = 0x00000020,\r
+\r
+ //\r
+ //! A message was received successfully since the last read of this status.\r
+ //\r
+ CAN_STATUS_RXOK = 0x00000010,\r
+\r
+ //\r
+ //! A message was transmitted successfully since the last read of this\r
+ //! status.\r
+ //\r
+ CAN_STATUS_TXOK = 0x00000008,\r
+\r
+ //\r
+ //! This is the mask for the last error code field.\r
+ //\r
+ CAN_STATUS_LEC_MSK = 0x00000007,\r
+\r
+ //\r
+ //! There was no error.\r
+ //\r
+ CAN_STATUS_LEC_NONE = 0x00000000,\r
+\r
+ //\r
+ //! A bit stuffing error has occurred.\r
+ //\r
+ CAN_STATUS_LEC_STUFF = 0x00000001,\r
+\r
+ //\r
+ //! A formatting error has occurred.\r
+ //\r
+ CAN_STATUS_LEC_FORM = 0x00000002,\r
+\r
+ //\r
+ //! An acknowledge error has occurred.\r
+ //\r
+ CAN_STATUS_LEC_ACK = 0x00000003,\r
+\r
+ //\r
+ //! The bus remained a bit level of 1 for longer than is allowed.\r
+ //\r
+ CAN_STATUS_LEC_BIT1 = 0x00000004,\r
+\r
+ //\r
+ //! The bus remained a bit level of 0 for longer than is allowed.\r
+ //\r
+ CAN_STATUS_LEC_BIT0 = 0x00000005,\r
+\r
+ //\r
+ //! A CRC error has occurred.\r
+ //\r
+ CAN_STATUS_LEC_CRC = 0x00000006,\r
+\r
+ //\r
+ //! This is the mask for the CAN Last Error Code (LEC).\r
+ //\r
+ CAN_STATUS_LEC_MASK = 0x00000007\r
+}\r
+tCANStatusCtrl;\r
+\r
+//*****************************************************************************\r
+//\r
+// API Function prototypes\r
+//\r
+//*****************************************************************************\r
+extern void CANInit(unsigned long ulBase);\r
+extern void CANEnable(unsigned long ulBase);\r
+extern void CANDisable(unsigned long ulBase);\r
+extern void CANSetBitTiming(unsigned long ulBase, tCANBitClkParms *pClkParms);\r
+extern void CANGetBitTiming(unsigned long ulBase, tCANBitClkParms *pClkParms);\r
+extern unsigned long CANReadReg(unsigned long ulRegAddress);\r
+extern void CANWriteReg(unsigned long ulRegAddress, unsigned long ulRegValue);\r
+extern void CANMessageSet(unsigned long ulBase, unsigned long ulObjID,\r
+ tCANMsgObject *pMsgObject, tMsgObjType eMsgType);\r
+extern void CANMessageGet(unsigned long ulBase, unsigned long ulObjID,\r
+ tCANMsgObject *pMsgObject, tBoolean bClrPendingInt);\r
+extern unsigned long CANStatusGet(unsigned long ulBase, tCANStsReg eStatusReg);\r
+extern void CANMessageClear(unsigned long ulBase, unsigned long ulObjID);\r
+extern void CANIntRegister(unsigned long ulBase, void (*pfnHandler)(void));\r
+extern void CANIntEnable(unsigned long ulBase, unsigned long ulIntFlags);\r
+extern void CANIntDisable(unsigned long ulBase, unsigned long ulIntFlags);\r
+extern void CANIntClear(unsigned long ulBase, unsigned long ulIntClr);\r
+extern unsigned long CANIntStatus(unsigned long ulBase,\r
+ tCANIntStsReg eIntStsReg);\r
+extern tBoolean CANRetryGet(unsigned long ulBase);\r
+extern void CANRetrySet(unsigned long ulBase, tBoolean bAutoRetry);\r
+extern tBoolean CANErrCntrGet(unsigned long ulBase, unsigned long *pulRxCount,\r
+ unsigned long *pulTxCount);\r
+extern long CANGetIntNumber(unsigned long ulBase);\r
+extern void CANReadDataReg(unsigned char *pucData, unsigned long *pulRegister,\r
+ int iSize);\r
+extern void CANWriteDataReg(unsigned char *pucData, unsigned long *pulRegister,\r
+ int iSize);\r
+\r
+//*****************************************************************************\r
+//\r
+// Close the Doxygen group.\r
+//! @}\r
+//\r
+//*****************************************************************************\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __CAN_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// comp.h - Prototypes for the analog comparator driver.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __COMP_H__\r
+#define __COMP_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to ComparatorConfigure() as the ulConfig\r
+// parameter. For each group (i.e. COMP_TRIG_xxx, COMP_INT_xxx, etc.), one of\r
+// the values may be selected and ORed together will values from the other\r
+// groups.\r
+//\r
+//*****************************************************************************\r
+#define COMP_TRIG_NONE 0x00000000 // No ADC trigger\r
+#define COMP_TRIG_HIGH 0x00000880 // Trigger when high\r
+#define COMP_TRIG_LOW 0x00000800 // Trigger when low\r
+#define COMP_TRIG_FALL 0x00000820 // Trigger on falling edge\r
+#define COMP_TRIG_RISE 0x00000840 // Trigger on rising edge\r
+#define COMP_TRIG_BOTH 0x00000860 // Trigger on both edges\r
+#define COMP_INT_HIGH 0x00000010 // Interrupt when high\r
+#define COMP_INT_LOW 0x00000000 // Interrupt when low\r
+#define COMP_INT_FALL 0x00000004 // Interrupt on falling edge\r
+#define COMP_INT_RISE 0x00000008 // Interrupt on rising edge\r
+#define COMP_INT_BOTH 0x0000000C // Interrupt on both edges\r
+#define COMP_ASRCP_PIN 0x00000000 // Dedicated Comp+ pin\r
+#define COMP_ASRCP_PIN0 0x00000200 // Comp0+ pin\r
+#define COMP_ASRCP_REF 0x00000400 // Internal voltage reference\r
+#ifndef DEPRECATED\r
+#define COMP_OUTPUT_NONE 0x00000000 // No comparator output\r
+#endif\r
+#define COMP_OUTPUT_NORMAL 0x00000000 // Comparator output normal\r
+#define COMP_OUTPUT_INVERT 0x00000002 // Comparator output inverted\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to ComparatorSetRef() as the ulRef parameter.\r
+//\r
+//*****************************************************************************\r
+#define COMP_REF_OFF 0x00000000 // Turn off the internal reference\r
+#define COMP_REF_0V 0x00000300 // Internal reference of 0V\r
+#define COMP_REF_0_1375V 0x00000301 // Internal reference of 0.1375V\r
+#define COMP_REF_0_275V 0x00000302 // Internal reference of 0.275V\r
+#define COMP_REF_0_4125V 0x00000303 // Internal reference of 0.4125V\r
+#define COMP_REF_0_55V 0x00000304 // Internal reference of 0.55V\r
+#define COMP_REF_0_6875V 0x00000305 // Internal reference of 0.6875V\r
+#define COMP_REF_0_825V 0x00000306 // Internal reference of 0.825V\r
+#define COMP_REF_0_928125V 0x00000201 // Internal reference of 0.928125V\r
+#define COMP_REF_0_9625V 0x00000307 // Internal reference of 0.9625V\r
+#define COMP_REF_1_03125V 0x00000202 // Internal reference of 1.03125V\r
+#define COMP_REF_1_134375V 0x00000203 // Internal reference of 1.134375V\r
+#define COMP_REF_1_1V 0x00000308 // Internal reference of 1.1V\r
+#define COMP_REF_1_2375V 0x00000309 // Internal reference of 1.2375V\r
+#define COMP_REF_1_340625V 0x00000205 // Internal reference of 1.340625V\r
+#define COMP_REF_1_375V 0x0000030A // Internal reference of 1.375V\r
+#define COMP_REF_1_44375V 0x00000206 // Internal reference of 1.44375V\r
+#define COMP_REF_1_5125V 0x0000030B // Internal reference of 1.5125V\r
+#define COMP_REF_1_546875V 0x00000207 // Internal reference of 1.546875V\r
+#define COMP_REF_1_65V 0x0000030C // Internal reference of 1.65V\r
+#define COMP_REF_1_753125V 0x00000209 // Internal reference of 1.753125V\r
+#define COMP_REF_1_7875V 0x0000030D // Internal reference of 1.7875V\r
+#define COMP_REF_1_85625V 0x0000020A // Internal reference of 1.85625V\r
+#define COMP_REF_1_925V 0x0000030E // Internal reference of 1.925V\r
+#define COMP_REF_1_959375V 0x0000020B // Internal reference of 1.959375V\r
+#define COMP_REF_2_0625V 0x0000030F // Internal reference of 2.0625V\r
+#define COMP_REF_2_165625V 0x0000020D // Internal reference of 2.165625V\r
+#define COMP_REF_2_26875V 0x0000020E // Internal reference of 2.26875V\r
+#define COMP_REF_2_371875V 0x0000020F // Internal reference of 2.371875V\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+extern void ComparatorConfigure(unsigned long ulBase, unsigned long ulComp,\r
+ unsigned long ulConfig);\r
+extern void ComparatorRefSet(unsigned long ulBase, unsigned long ulRef);\r
+extern tBoolean ComparatorValueGet(unsigned long ulBase, unsigned long ulComp);\r
+extern void ComparatorIntRegister(unsigned long ulBase, unsigned long ulComp,\r
+ void (*pfnHandler)(void));\r
+extern void ComparatorIntUnregister(unsigned long ulBase,\r
+ unsigned long ulComp);\r
+extern void ComparatorIntEnable(unsigned long ulBase, unsigned long ulComp);\r
+extern void ComparatorIntDisable(unsigned long ulBase, unsigned long ulComp);\r
+extern tBoolean ComparatorIntStatus(unsigned long ulBase, unsigned long ulComp,\r
+ tBoolean bMasked);\r
+extern void ComparatorIntClear(unsigned long ulBase, unsigned long ulComp);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __COMP_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// cpu.h - Prototypes for the CPU instruction wrapper functions.\r
+//\r
+// Copyright (c) 2006-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __CPU_H__\r
+#define __CPU_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes.\r
+//\r
+//*****************************************************************************\r
+extern void CPUcpsid(void);\r
+extern void CPUcpsie(void);\r
+extern void CPUwfi(void);\r
+\r
+#endif // __CPU_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// debug.h - Macros for assisting debug of the driver library.\r
+//\r
+// Copyright (c) 2006-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __DEBUG_H__\r
+#define __DEBUG_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototype for the function that is called when an invalid argument is passed\r
+// to an API. This is only used when doing a DEBUG build.\r
+//\r
+//*****************************************************************************\r
+extern void __error__(char *pcFilename, unsigned long ulLine);\r
+\r
+//*****************************************************************************\r
+//\r
+// The ASSERT macro, which does the actual assertion checking. Typically, this\r
+// will be for procedure arguments.\r
+//\r
+//*****************************************************************************\r
+#ifdef DEBUG\r
+#define ASSERT(expr) { \\r
+ if(!(expr)) \\r
+ { \\r
+ __error__(__FILE__, __LINE__); \\r
+ } \\r
+ }\r
+#else\r
+#define ASSERT(expr)\r
+#endif\r
+\r
+#endif // __DEBUG_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// ethernet.h - Defines and Macros for the ethernet module.\r
+//\r
+// Copyright (c) 2006-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __ETHERNET_H__\r
+#define __ETHERNET_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to EthernetConfigSet as the ulConfig value, and\r
+// returned from EthernetConfigGet.\r
+//\r
+//*****************************************************************************\r
+#define ETH_CFG_RX_BADCRCDIS 0x000800 // Disable RX BAD CRC Packets\r
+#define ETH_CFG_RX_PRMSEN 0x000400 // Enable RX Promiscuous\r
+#define ETH_CFG_RX_AMULEN 0x000200 // Enable RX Multicast\r
+#define ETH_CFG_TX_DPLXEN 0x000010 // Enable TX Duplex Mode\r
+#define ETH_CFG_TX_CRCEN 0x000004 // Enable TX CRC Generation\r
+#define ETH_CFG_TX_PADEN 0x000002 // Enable TX Padding\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to EthernetIntEnable, EthernetIntDisable, and\r
+// EthernetIntClear as the ulIntFlags parameter, and returned from\r
+// EthernetIntStatus.\r
+//\r
+//*****************************************************************************\r
+#define ETH_INT_PHY 0x040 // PHY Event/Interrupt\r
+#define ETH_INT_MDIO 0x020 // Management Transaction\r
+#define ETH_INT_RXER 0x010 // RX Error\r
+#define ETH_INT_RXOF 0x008 // RX FIFO Overrun\r
+#define ETH_INT_TX 0x004 // TX Complete\r
+#define ETH_INT_TXER 0x002 // TX Error\r
+#define ETH_INT_RX 0x001 // RX Complete\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define values that can be passed as register addresses to\r
+// EthernetPHYRead and EthernetPHYWrite.\r
+//\r
+//*****************************************************************************\r
+#define PHY_MR0 0 // Control\r
+#define PHY_MR1 1 // Status\r
+#define PHY_MR2 2 // PHY Identifier 1\r
+#define PHY_MR3 3 // PHY Identifier 2\r
+#define PHY_MR4 4 // Auto-Neg. Advertisement\r
+#define PHY_MR5 5 // Auto-Neg. Link Partner Ability\r
+#define PHY_MR6 6 // Auto-Neg. Expansion\r
+ // 7-15 Reserved/Not Implemented\r
+#define PHY_MR16 16 // Vendor Specific\r
+#define PHY_MR17 17 // Interrupt Control/Status\r
+#define PHY_MR18 18 // Diagnostic Register\r
+#define PHY_MR19 19 // Transceiver Control\r
+ // 20-22 Reserved\r
+#define PHY_MR23 23 // LED Configuration Register\r
+#define PHY_MR24 24 // MDI/MDIX Control Register\r
+ // 25-31 Reserved/Not Implemented\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define bit fields in the ETH_MR0 register\r
+//\r
+//*****************************************************************************\r
+#define PHY_MR0_RESET 0x8000 // Reset the PHY\r
+#define PHY_MR0_LOOPBK 0x4000 // TXD to RXD Loopback\r
+#define PHY_MR0_SPEEDSL 0x2000 // Speed Selection\r
+#define PHY_MR0_SPEEDSL_10 0x0000 // Speed Selection 10BASE-T\r
+#define PHY_MR0_SPEEDSL_100 0x2000 // Speed Selection 100BASE-T\r
+#define PHY_MR0_ANEGEN 0x1000 // Auto-Negotiation Enable\r
+#define PHY_MR0_PWRDN 0x0800 // Power Down\r
+#define PHY_MR0_RANEG 0x0200 // Restart Auto-Negotiation\r
+#define PHY_MR0_DUPLEX 0x0100 // Enable full duplex\r
+#define PHY_MR0_DUPLEX_HALF 0x0000 // Enable half duplex mode\r
+#define PHY_MR0_DUPLEX_FULL 0x0100 // Enable full duplex mode\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define bit fields in the ETH_MR1 register\r
+//\r
+//*****************************************************************************\r
+#define PHY_MR1_ANEGC 0x0020 // Auto-Negotiate Complete\r
+#define PHY_MR1_RFAULT 0x0010 // Remove Fault Detected\r
+#define PHY_MR1_LINK 0x0004 // Link Established\r
+#define PHY_MR1_JAB 0x0002 // Jabber Condition Detected\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define bit fields in the ETH_MR17 register\r
+//\r
+//*****************************************************************************\r
+#define PHY_MR17_RXER_IE 0x4000 // Enable Receive Error Interrupt\r
+#define PHY_MR17_LSCHG_IE 0x0400 // Enable Link Status Change Int.\r
+#define PHY_MR17_ANEGCOMP_IE 0x0100 // Enable Auto-Negotiate Cmpl. Int.\r
+#define PHY_MR17_RXER_INT 0x0040 // Receive Error Interrupt\r
+#define PHY_MR17_LSCHG_INT 0x0004 // Link Status Change Interrupt\r
+#define PHY_MR17_ANEGCOMP_INT 0x0001 // Auto-Negotiate Complete Int.\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define bit fields in the ETH_MR18 register\r
+//\r
+//*****************************************************************************\r
+#define PHY_MR18_ANEGF 0x1000 // Auto-Negotiate Failed\r
+#define PHY_MR18_DPLX 0x0800 // Duplex Mode Negotiated\r
+#define PHY_MR18_DPLX_HALF 0x0000 // Half Duplex Mode Negotiated\r
+#define PHY_MR18_DPLX_FULL 0x0800 // Full Duplex Mode Negotiated\r
+#define PHY_MR18_RATE 0x0400 // Rate Negotiated\r
+#define PHY_MR18_RATE_10 0x0000 // Rate Negotiated is 10BASE-T\r
+#define PHY_MR18_RATE_100 0x0400 // Rate Negotiated is 100BASE-TX\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define bit fields in the ETH_MR23 register\r
+//\r
+//*****************************************************************************\r
+#define PHY_MR23_LED1 0x00f0 // LED1 Configuration\r
+#define PHY_MR23_LED1_LINK 0x0000 // LED1 is Link Status\r
+#define PHY_MR23_LED1_RXTX 0x0010 // LED1 is RX or TX Activity\r
+#define PHY_MR23_LED1_TX 0x0020 // LED1 is TX Activity\r
+#define PHY_MR23_LED1_RX 0x0030 // LED1 is RX Activity\r
+#define PHY_MR23_LED1_COL 0x0040 // LED1 is RX Activity\r
+#define PHY_MR23_LED1_100 0x0050 // LED1 is RX Activity\r
+#define PHY_MR23_LED1_10 0x0060 // LED1 is RX Activity\r
+#define PHY_MR23_LED1_DUPLEX 0x0070 // LED1 is RX Activity\r
+#define PHY_MR23_LED1_LINKACT 0x0080 // LED1 is Link Status + Activity\r
+#define PHY_MR23_LED0 0x000f // LED0 Configuration\r
+#define PHY_MR23_LED0_LINK 0x0000 // LED0 is Link Status\r
+#define PHY_MR23_LED0_RXTX 0x0001 // LED0 is RX or TX Activity\r
+#define PHY_MR23_LED0_TX 0x0002 // LED0 is TX Activity\r
+#define PHY_MR23_LED0_RX 0x0003 // LED0 is RX Activity\r
+#define PHY_MR23_LED0_COL 0x0004 // LED0 is RX Activity\r
+#define PHY_MR23_LED0_100 0x0005 // LED0 is RX Activity\r
+#define PHY_MR23_LED0_10 0x0006 // LED0 is RX Activity\r
+#define PHY_MR23_LED0_DUPLEX 0x0007 // LED0 is RX Activity\r
+#define PHY_MR23_LED0_LINKACT 0x0008 // LED0 is Link Status + Activity\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define bit fields in the ETH_MR24 register\r
+//\r
+//*****************************************************************************\r
+#define PHY_MR24_MDIX 0x0020 // Auto-Switching Configuration\r
+#define PHY_MR24_MDIX_NORMAL 0x0000 // Auto-Switching in passthrough\r
+#define PHY_MR23_MDIX_CROSSOVER 0x0020 // Auto-Switching in crossover\r
+\r
+//*****************************************************************************\r
+//\r
+// Helper Macros for Ethernet Processing\r
+//\r
+//*****************************************************************************\r
+//\r
+// htonl/ntohl - big endian/little endian byte swapping macros for\r
+// 32-bit (long) values\r
+//\r
+//*****************************************************************************\r
+#ifndef htonl\r
+ #define htonl(a) \\r
+ ((((a) >> 24) & 0x000000ff) | \\r
+ (((a) >> 8) & 0x0000ff00) | \\r
+ (((a) << 8) & 0x00ff0000) | \\r
+ (((a) << 24) & 0xff000000))\r
+#endif\r
+\r
+#ifndef ntohl\r
+ #define ntohl(a) htonl((a))\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// htons/ntohs - big endian/little endian byte swapping macros for\r
+// 16-bit (short) values\r
+//\r
+//*****************************************************************************\r
+#ifndef htons\r
+ #define htons(a) \\r
+ ((((a) >> 8) & 0x00ff) | \\r
+ (((a) << 8) & 0xff00))\r
+#endif\r
+\r
+#ifndef ntohs\r
+ #define ntohs(a) htons((a))\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// API Function prototypes\r
+//\r
+//*****************************************************************************\r
+extern void EthernetInit(unsigned long ulBase);\r
+extern void EthernetConfigSet(unsigned long ulBase, unsigned long ulConfig);\r
+extern unsigned long EthernetConfigGet(unsigned long ulBase);\r
+extern void EthernetMACAddrSet(unsigned long ulBase,\r
+ unsigned char *pucMACAddr);\r
+extern void EthernetMACAddrGet(unsigned long ulBase,\r
+ unsigned char *pucMACAddr);\r
+extern void EthernetEnable(unsigned long ulBase);\r
+extern void EthernetDisable(unsigned long ulBase);\r
+extern tBoolean EthernetPacketAvail(unsigned long ulBase);\r
+extern tBoolean EthernetSpaceAvail(unsigned long ulBase);\r
+extern long EthernetPacketNonBlockingGet(unsigned long ulBase,\r
+ unsigned char *pucBuf,\r
+ long lBufLen);\r
+extern long EthernetPacketGet(unsigned long ulBase, unsigned char *pucBuf,\r
+ long lBufLen);\r
+extern long EthernetPacketNonBlockingPut(unsigned long ulBase,\r
+ unsigned char *pucBuf,\r
+ long lBufLen);\r
+extern long EthernetPacketPut(unsigned long ulBase, unsigned char *pucBuf,\r
+ long lBufLen);\r
+extern void EthernetIntRegister(unsigned long ulBase,\r
+ void (*pfnHandler)(void));\r
+extern void EthernetIntUnregister(unsigned long ulBase);\r
+extern void EthernetIntEnable(unsigned long ulBase, unsigned long ulIntFlags);\r
+extern void EthernetIntDisable(unsigned long ulBase, unsigned long ulIntFlags);\r
+extern unsigned long EthernetIntStatus(unsigned long ulBase, tBoolean bMasked);\r
+extern void EthernetIntClear(unsigned long ulBase, unsigned long ulIntFlags);\r
+extern void EthernetPHYWrite(unsigned long ulBase, unsigned char ucRegAddr,\r
+ unsigned long ulData);\r
+extern unsigned long EthernetPHYRead(unsigned long ulBase,\r
+ unsigned char ucRegAddr);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __ETHERNET_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// gpio.h - Defines and Macros for GPIO API.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __GPIO_H__\r
+#define __GPIO_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// The following values define the bit field for the ucPins argument to several\r
+// of the APIs.\r
+//\r
+//*****************************************************************************\r
+#define GPIO_PIN_0 0x00000001 // GPIO pin 0\r
+#define GPIO_PIN_1 0x00000002 // GPIO pin 1\r
+#define GPIO_PIN_2 0x00000004 // GPIO pin 2\r
+#define GPIO_PIN_3 0x00000008 // GPIO pin 3\r
+#define GPIO_PIN_4 0x00000010 // GPIO pin 4\r
+#define GPIO_PIN_5 0x00000020 // GPIO pin 5\r
+#define GPIO_PIN_6 0x00000040 // GPIO pin 6\r
+#define GPIO_PIN_7 0x00000080 // GPIO pin 7\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to GPIODirModeSet as the ulPinIO parameter, and\r
+// returned from GPIODirModeGet.\r
+//\r
+//*****************************************************************************\r
+#define GPIO_DIR_MODE_IN 0x00000000 // Pin is a GPIO input\r
+#define GPIO_DIR_MODE_OUT 0x00000001 // Pin is a GPIO output\r
+#define GPIO_DIR_MODE_HW 0x00000002 // Pin is a peripheral function\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to GPIOIntTypeSet as the ulIntType parameter, and\r
+// returned from GPIOIntTypeGet.\r
+//\r
+//*****************************************************************************\r
+#define GPIO_FALLING_EDGE 0x00000000 // Interrupt on falling edge\r
+#define GPIO_RISING_EDGE 0x00000004 // Interrupt on rising edge\r
+#define GPIO_BOTH_EDGES 0x00000001 // Interrupt on both edges\r
+#define GPIO_LOW_LEVEL 0x00000002 // Interrupt on low level\r
+#define GPIO_HIGH_LEVEL 0x00000007 // Interrupt on high level\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to GPIOPadConfigSet as the ulStrength parameter,\r
+// and returned by GPIOPadConfigGet in the *pulStrength parameter.\r
+//\r
+//*****************************************************************************\r
+#define GPIO_STRENGTH_2MA 0x00000001 // 2mA drive strength\r
+#define GPIO_STRENGTH_4MA 0x00000002 // 4mA drive strength\r
+#define GPIO_STRENGTH_8MA 0x00000004 // 8mA drive strength\r
+#define GPIO_STRENGTH_8MA_SC 0x0000000C // 8mA drive with slew rate control\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to GPIOPadConfigSet as the ulPadType parameter,\r
+// and returned by GPIOPadConfigGet in the *pulPadType parameter.\r
+//\r
+//*****************************************************************************\r
+#define GPIO_PIN_TYPE_STD 0x00000008 // Push-pull\r
+#define GPIO_PIN_TYPE_STD_WPU 0x0000000A // Push-pull with weak pull-up\r
+#define GPIO_PIN_TYPE_STD_WPD 0x0000000C // Push-pull with weak pull-down\r
+#define GPIO_PIN_TYPE_OD 0x00000009 // Open-drain\r
+#define GPIO_PIN_TYPE_OD_WPU 0x0000000B // Open-drain with weak pull-up\r
+#define GPIO_PIN_TYPE_OD_WPD 0x0000000D // Open-drain with weak pull-down\r
+#define GPIO_PIN_TYPE_ANALOG 0x00000000 // Analog comparator\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+extern void GPIODirModeSet(unsigned long ulPort, unsigned char ucPins,\r
+ unsigned long ulPinIO);\r
+extern unsigned long GPIODirModeGet(unsigned long ulPort, unsigned char ucPin);\r
+extern void GPIOIntTypeSet(unsigned long ulPort, unsigned char ucPins,\r
+ unsigned long ulIntType);\r
+extern unsigned long GPIOIntTypeGet(unsigned long ulPort, unsigned char ucPin);\r
+extern void GPIOPadConfigSet(unsigned long ulPort, unsigned char ucPins,\r
+ unsigned long ulStrength,\r
+ unsigned long ulPadType);\r
+extern void GPIOPadConfigGet(unsigned long ulPort, unsigned char ucPin,\r
+ unsigned long *pulStrength,\r
+ unsigned long *pulPadType);\r
+extern void GPIOPinIntEnable(unsigned long ulPort, unsigned char ucPins);\r
+extern void GPIOPinIntDisable(unsigned long ulPort, unsigned char ucPins);\r
+extern long GPIOPinIntStatus(unsigned long ulPort, tBoolean bMasked);\r
+extern void GPIOPinIntClear(unsigned long ulPort, unsigned char ucPins);\r
+extern void GPIOPortIntRegister(unsigned long ulPort,\r
+ void (*pfIntHandler)(void));\r
+extern void GPIOPortIntUnregister(unsigned long ulPort);\r
+extern long GPIOPinRead(unsigned long ulPort, unsigned char ucPins);\r
+extern void GPIOPinWrite(unsigned long ulPort, unsigned char ucPins,\r
+ unsigned char ucVal);\r
+extern void GPIOPinTypeComparator(unsigned long ulPort, unsigned char ucPins);\r
+extern void GPIOPinTypeI2C(unsigned long ulPort, unsigned char ucPins);\r
+extern void GPIOPinTypePWM(unsigned long ulPort, unsigned char ucPins);\r
+extern void GPIOPinTypeQEI(unsigned long ulPort, unsigned char ucPins);\r
+extern void GPIOPinTypeSSI(unsigned long ulPort, unsigned char ucPins);\r
+extern void GPIOPinTypeTimer(unsigned long ulPort, unsigned char ucPins);\r
+extern void GPIOPinTypeUART(unsigned long ulPort, unsigned char ucPins);\r
+extern void GPIOPinTypeCAN(unsigned long ulPort, unsigned char ucPins);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __GPIO_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hibernate.h - API definition for the Hibernation module.\r
+//\r
+// Copyright (c) 2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HIBERNATE_H__\r
+#define __HIBERNATE_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Macros needed for selecting the clock source for HibernateClockSelect()\r
+//\r
+//*****************************************************************************\r
+#define HIBERNATE_CLOCK_SEL_RAW 0x04\r
+#define HIBERNATE_CLOCK_SEL_DIV128 0x00\r
+\r
+//*****************************************************************************\r
+//\r
+// Macros need to configure wake events for HibernateWakeSet()\r
+//\r
+//*****************************************************************************\r
+#define HIBERNATE_WAKE_PIN 0x10\r
+#define HIBERNATE_WAKE_RTC 0x08\r
+\r
+//*****************************************************************************\r
+//\r
+// Macros needed to configure low battery detect for HibernateLowBatSet()\r
+//\r
+//*****************************************************************************\r
+#define HIBERNATE_LOW_BAT_DETECT 0x20\r
+#define HIBERNATE_LOW_BAT_ABORT 0xA0\r
+\r
+//*****************************************************************************\r
+//\r
+// Macros defining interrupt source bits for the interrupt functions.\r
+//\r
+//*****************************************************************************\r
+#define HIBERNATE_INT_PIN_WAKE 0x08\r
+#define HIBERNATE_INT_LOW_BAT 0x04\r
+#define HIBERNATE_INT_RTC_MATCH_0 0x01\r
+#define HIBERNATE_INT_RTC_MATCH_1 0x02\r
+\r
+//*****************************************************************************\r
+//\r
+// API Function prototypes\r
+//\r
+//*****************************************************************************\r
+extern void HibernateEnable(void);\r
+extern void HibernateDisable(void);\r
+extern void HibernateClockSelect(unsigned long ulClockInput);\r
+extern void HibernateRTCEnable(void);\r
+extern void HibernateRTCDisable(void);\r
+extern void HibernateWakeSet(unsigned long ulWakeFlags);\r
+extern unsigned long HibernateWakeGet(void);\r
+extern void HibernateLowBatSet(unsigned long ulLowBatFlags);\r
+extern unsigned long HibernateLowBatGet(void);\r
+extern void HibernateRTCSet(unsigned long ulRTCValue);\r
+extern unsigned long HibernateRTCGet(void);\r
+extern void HibernateRTCMatch0Set(unsigned long ulMatch);\r
+extern unsigned long HibernateRTCMatch0Get(void);\r
+extern void HibernateRTCMatch1Set(unsigned long ulMatch);\r
+extern unsigned long HibernateRTCMatch1Get(void);\r
+extern void HibernateRTCTrimSet(unsigned long ulTrim);\r
+extern unsigned long HibernateRTCTrimGet(void);\r
+extern void HibernateDataSet(unsigned long *pulData, unsigned long ulCount);\r
+extern void HibernateDataGet(unsigned long *pulData, unsigned long ulCount);\r
+extern void HibernateRequest(void);\r
+extern void HibernateIntEnable(unsigned long ulIntFlags);\r
+extern void HibernateIntDisable(unsigned long ulIntFlags);\r
+extern void HibernateIntRegister(void (*pfnHandler)(void));\r
+extern void HibernateIntUnregister(void);\r
+extern unsigned long HibernateIntStatus(tBoolean bMasked);\r
+extern void HibernateIntClear(unsigned long ulIntFlags);\r
+extern unsigned int HibernateIsActive(void);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __HIBERNATE_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_adc.h - Macros used when accessing the ADC hardware.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_ADC_H__\r
+#define __HW_ADC_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the offsets of the ADC registers.\r
+//\r
+//*****************************************************************************\r
+#define ADC_O_ACTSS 0x00000000 // Active sample register\r
+#define ADC_O_RIS 0x00000004 // Raw interrupt status register\r
+#define ADC_O_IM 0x00000008 // Interrupt mask register\r
+#define ADC_O_ISC 0x0000000C // Interrupt status/clear register\r
+#define ADC_O_OSTAT 0x00000010 // Overflow status register\r
+#define ADC_O_EMUX 0x00000014 // Event multiplexer select reg.\r
+#define ADC_O_USTAT 0x00000018 // Underflow status register\r
+#define ADC_O_SSPRI 0x00000020 // Channel priority register\r
+#define ADC_O_PSSI 0x00000028 // Processor sample initiate reg.\r
+#define ADC_O_SAC 0x00000030 // Sample Averaging Control reg.\r
+#define ADC_O_SSMUX0 0x00000040 // Multiplexer select 0 register\r
+#define ADC_O_SSCTL0 0x00000044 // Sample sequence control 0 reg.\r
+#define ADC_O_SSFIFO0 0x00000048 // Result FIFO 0 register\r
+#define ADC_O_SSFSTAT0 0x0000004C // FIFO 0 status register\r
+#define ADC_O_SSMUX1 0x00000060 // Multiplexer select 1 register\r
+#define ADC_O_SSCTL1 0x00000064 // Sample sequence control 1 reg.\r
+#define ADC_O_SSFIFO1 0x00000068 // Result FIFO 1 register\r
+#define ADC_O_SSFSTAT1 0x0000006C // FIFO 1 status register\r
+#define ADC_O_SSMUX2 0x00000080 // Multiplexer select 2 register\r
+#define ADC_O_SSCTL2 0x00000084 // Sample sequence control 2 reg.\r
+#define ADC_O_SSFIFO2 0x00000088 // Result FIFO 2 register\r
+#define ADC_O_SSFSTAT2 0x0000008C // FIFO 2 status register\r
+#define ADC_O_SSMUX3 0x000000A0 // Multiplexer select 3 register\r
+#define ADC_O_SSCTL3 0x000000A4 // Sample sequence control 3 reg.\r
+#define ADC_O_SSFIFO3 0x000000A8 // Result FIFO 3 register\r
+#define ADC_O_SSFSTAT3 0x000000AC // FIFO 3 status register\r
+#define ADC_O_TMLB 0x00000100 // Test mode loopback register\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the offsets of the ADC sequence registers.\r
+//\r
+//*****************************************************************************\r
+#define ADC_O_SEQ 0x00000040 // Offset to the first sequence\r
+#define ADC_O_SEQ_STEP 0x00000020 // Increment to the next sequence\r
+#define ADC_O_X_SSMUX 0x00000000 // Multiplexer select register\r
+#define ADC_O_X_SSCTL 0x00000004 // Sample sequence control register\r
+#define ADC_O_X_SSFIFO 0x00000008 // Result FIFO register\r
+#define ADC_O_X_SSFSTAT 0x0000000C // FIFO status register\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the ADC_ACTSS register.\r
+//\r
+//*****************************************************************************\r
+#define ADC_ACTSS_ASEN3 0x00000008 // Sample sequence 3 enable\r
+#define ADC_ACTSS_ASEN2 0x00000004 // Sample sequence 2 enable\r
+#define ADC_ACTSS_ASEN1 0x00000002 // Sample sequence 1 enable\r
+#define ADC_ACTSS_ASEN0 0x00000001 // Sample sequence 0 enable\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the ADC_RIS register.\r
+//\r
+//*****************************************************************************\r
+#define ADC_RIS_INR3 0x00000008 // Sample sequence 3 interrupt\r
+#define ADC_RIS_INR2 0x00000004 // Sample sequence 2 interrupt\r
+#define ADC_RIS_INR1 0x00000002 // Sample sequence 1 interrupt\r
+#define ADC_RIS_INR0 0x00000001 // Sample sequence 0 interrupt\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the ADC_IM register.\r
+//\r
+//*****************************************************************************\r
+#define ADC_IM_MASK3 0x00000008 // Sample sequence 3 mask\r
+#define ADC_IM_MASK2 0x00000004 // Sample sequence 2 mask\r
+#define ADC_IM_MASK1 0x00000002 // Sample sequence 1 mask\r
+#define ADC_IM_MASK0 0x00000001 // Sample sequence 0 mask\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the ADC_ISC register.\r
+//\r
+//*****************************************************************************\r
+#define ADC_ISC_IN3 0x00000008 // Sample sequence 3 interrupt\r
+#define ADC_ISC_IN2 0x00000004 // Sample sequence 2 interrupt\r
+#define ADC_ISC_IN1 0x00000002 // Sample sequence 1 interrupt\r
+#define ADC_ISC_IN0 0x00000001 // Sample sequence 0 interrupt\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the ADC_OSTAT register.\r
+//\r
+//*****************************************************************************\r
+#define ADC_OSTAT_OV3 0x00000008 // Sample sequence 3 overflow\r
+#define ADC_OSTAT_OV2 0x00000004 // Sample sequence 2 overflow\r
+#define ADC_OSTAT_OV1 0x00000002 // Sample sequence 1 overflow\r
+#define ADC_OSTAT_OV0 0x00000001 // Sample sequence 0 overflow\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the ADC_EMUX register.\r
+//\r
+//*****************************************************************************\r
+#define ADC_EMUX_EM3_MASK 0x0000F000 // Event mux 3 mask\r
+#define ADC_EMUX_EM3_PROCESSOR 0x00000000 // Processor event\r
+#define ADC_EMUX_EM3_COMP0 0x00001000 // Analog comparator 0 event\r
+#define ADC_EMUX_EM3_COMP1 0x00002000 // Analog comparator 1 event\r
+#define ADC_EMUX_EM3_COMP2 0x00003000 // Analog comparator 2 event\r
+#define ADC_EMUX_EM3_EXTERNAL 0x00004000 // External event\r
+#define ADC_EMUX_EM3_TIMER 0x00005000 // Timer event\r
+#define ADC_EMUX_EM3_PWM0 0x00006000 // PWM0 event\r
+#define ADC_EMUX_EM3_PWM1 0x00007000 // PWM1 event\r
+#define ADC_EMUX_EM3_PWM2 0x00008000 // PWM2 event\r
+#define ADC_EMUX_EM3_ALWAYS 0x0000F000 // Always event\r
+#define ADC_EMUX_EM2_MASK 0x00000F00 // Event mux 2 mask\r
+#define ADC_EMUX_EM2_PROCESSOR 0x00000000 // Processor event\r
+#define ADC_EMUX_EM2_COMP0 0x00000100 // Analog comparator 0 event\r
+#define ADC_EMUX_EM2_COMP1 0x00000200 // Analog comparator 1 event\r
+#define ADC_EMUX_EM2_COMP2 0x00000300 // Analog comparator 2 event\r
+#define ADC_EMUX_EM2_EXTERNAL 0x00000400 // External event\r
+#define ADC_EMUX_EM2_TIMER 0x00000500 // Timer event\r
+#define ADC_EMUX_EM2_PWM0 0x00000600 // PWM0 event\r
+#define ADC_EMUX_EM2_PWM1 0x00000700 // PWM1 event\r
+#define ADC_EMUX_EM2_PWM2 0x00000800 // PWM2 event\r
+#define ADC_EMUX_EM2_ALWAYS 0x00000F00 // Always event\r
+#define ADC_EMUX_EM1_MASK 0x000000F0 // Event mux 1 mask\r
+#define ADC_EMUX_EM1_PROCESSOR 0x00000000 // Processor event\r
+#define ADC_EMUX_EM1_COMP0 0x00000010 // Analog comparator 0 event\r
+#define ADC_EMUX_EM1_COMP1 0x00000020 // Analog comparator 1 event\r
+#define ADC_EMUX_EM1_COMP2 0x00000030 // Analog comparator 2 event\r
+#define ADC_EMUX_EM1_EXTERNAL 0x00000040 // External event\r
+#define ADC_EMUX_EM1_TIMER 0x00000050 // Timer event\r
+#define ADC_EMUX_EM1_PWM0 0x00000060 // PWM0 event\r
+#define ADC_EMUX_EM1_PWM1 0x00000070 // PWM1 event\r
+#define ADC_EMUX_EM1_PWM2 0x00000080 // PWM2 event\r
+#define ADC_EMUX_EM1_ALWAYS 0x000000F0 // Always event\r
+#define ADC_EMUX_EM0_MASK 0x0000000F // Event mux 0 mask\r
+#define ADC_EMUX_EM0_PROCESSOR 0x00000000 // Processor event\r
+#define ADC_EMUX_EM0_COMP0 0x00000001 // Analog comparator 0 event\r
+#define ADC_EMUX_EM0_COMP1 0x00000002 // Analog comparator 1 event\r
+#define ADC_EMUX_EM0_COMP2 0x00000003 // Analog comparator 2 event\r
+#define ADC_EMUX_EM0_EXTERNAL 0x00000004 // External event\r
+#define ADC_EMUX_EM0_TIMER 0x00000005 // Timer event\r
+#define ADC_EMUX_EM0_PWM0 0x00000006 // PWM0 event\r
+#define ADC_EMUX_EM0_PWM1 0x00000007 // PWM1 event\r
+#define ADC_EMUX_EM0_PWM2 0x00000008 // PWM2 event\r
+#define ADC_EMUX_EM0_ALWAYS 0x0000000F // Always event\r
+#define ADC_EMUX_EM0_SHIFT 0 // The shift for the first event\r
+#define ADC_EMUX_EM1_SHIFT 4 // The shift for the second event\r
+#define ADC_EMUX_EM2_SHIFT 8 // The shift for the third event\r
+#define ADC_EMUX_EM3_SHIFT 12 // The shift for the fourth event\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the ADC_USTAT register.\r
+//\r
+//*****************************************************************************\r
+#define ADC_USTAT_UV3 0x00000008 // Sample sequence 3 underflow\r
+#define ADC_USTAT_UV2 0x00000004 // Sample sequence 2 underflow\r
+#define ADC_USTAT_UV1 0x00000002 // Sample sequence 1 underflow\r
+#define ADC_USTAT_UV0 0x00000001 // Sample sequence 0 underflow\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the ADC_SSPRI register.\r
+//\r
+//*****************************************************************************\r
+#define ADC_SSPRI_SS3_MASK 0x00003000 // Sequencer 3 priority mask\r
+#define ADC_SSPRI_SS3_1ST 0x00000000 // First priority\r
+#define ADC_SSPRI_SS3_2ND 0x00001000 // Second priority\r
+#define ADC_SSPRI_SS3_3RD 0x00002000 // Third priority\r
+#define ADC_SSPRI_SS3_4TH 0x00003000 // Fourth priority\r
+#define ADC_SSPRI_SS2_MASK 0x00000300 // Sequencer 2 priority mask\r
+#define ADC_SSPRI_SS2_1ST 0x00000000 // First priority\r
+#define ADC_SSPRI_SS2_2ND 0x00000100 // Second priority\r
+#define ADC_SSPRI_SS2_3RD 0x00000200 // Third priority\r
+#define ADC_SSPRI_SS2_4TH 0x00000300 // Fourth priority\r
+#define ADC_SSPRI_SS1_MASK 0x00000030 // Sequencer 1 priority mask\r
+#define ADC_SSPRI_SS1_1ST 0x00000000 // First priority\r
+#define ADC_SSPRI_SS1_2ND 0x00000010 // Second priority\r
+#define ADC_SSPRI_SS1_3RD 0x00000020 // Third priority\r
+#define ADC_SSPRI_SS1_4TH 0x00000030 // Fourth priority\r
+#define ADC_SSPRI_SS0_MASK 0x00000003 // Sequencer 0 priority mask\r
+#define ADC_SSPRI_SS0_1ST 0x00000000 // First priority\r
+#define ADC_SSPRI_SS0_2ND 0x00000001 // Second priority\r
+#define ADC_SSPRI_SS0_3RD 0x00000002 // Third priority\r
+#define ADC_SSPRI_SS0_4TH 0x00000003 // Fourth priority\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the ADC_PSSI register.\r
+//\r
+//*****************************************************************************\r
+#define ADC_PSSI_SS3 0x00000008 // Trigger sample sequencer 3\r
+#define ADC_PSSI_SS2 0x00000004 // Trigger sample sequencer 2\r
+#define ADC_PSSI_SS1 0x00000002 // Trigger sample sequencer 1\r
+#define ADC_PSSI_SS0 0x00000001 // Trigger sample sequencer 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the ADC_SAC register.\r
+//\r
+//*****************************************************************************\r
+#define ADC_SAC_AVG_OFF 0x00000000 // No hardware oversampling\r
+#define ADC_SAC_AVG_2X 0x00000001 // 2x hardware oversampling\r
+#define ADC_SAC_AVG_4X 0x00000002 // 4x hardware oversampling\r
+#define ADC_SAC_AVG_8X 0x00000003 // 8x hardware oversampling\r
+#define ADC_SAC_AVG_16X 0x00000004 // 16x hardware oversampling\r
+#define ADC_SAC_AVG_32X 0x00000005 // 32x hardware oversampling\r
+#define ADC_SAC_AVG_64X 0x00000006 // 64x hardware oversampling\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the ADC_SSMUX0, ADC_SSMUX1,\r
+// ADC_SSMUX2, and ADC_SSMUX3 registers. Not all fields are present in all\r
+// registers.\r
+//\r
+//*****************************************************************************\r
+#define ADC_SSMUX_MUX7_MASK 0x70000000 // 8th mux select mask\r
+#define ADC_SSMUX_MUX6_MASK 0x07000000 // 7th mux select mask\r
+#define ADC_SSMUX_MUX5_MASK 0x00700000 // 6th mux select mask\r
+#define ADC_SSMUX_MUX4_MASK 0x00070000 // 5th mux select mask\r
+#define ADC_SSMUX_MUX3_MASK 0x00007000 // 4th mux select mask\r
+#define ADC_SSMUX_MUX2_MASK 0x00000700 // 3rd mux select mask\r
+#define ADC_SSMUX_MUX1_MASK 0x00000070 // 2nd mux select mask\r
+#define ADC_SSMUX_MUX0_MASK 0x00000007 // 1st mux select mask\r
+#define ADC_SSMUX_MUX7_SHIFT 28\r
+#define ADC_SSMUX_MUX6_SHIFT 24\r
+#define ADC_SSMUX_MUX5_SHIFT 20\r
+#define ADC_SSMUX_MUX4_SHIFT 16\r
+#define ADC_SSMUX_MUX3_SHIFT 12\r
+#define ADC_SSMUX_MUX2_SHIFT 8\r
+#define ADC_SSMUX_MUX1_SHIFT 4\r
+#define ADC_SSMUX_MUX0_SHIFT 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the ADC_SSCTL0, ADC_SSCTL1,\r
+// ADC_SSCTL2, and ADC_SSCTL3 registers. Not all fields are present in all\r
+// registers.\r
+//\r
+//*****************************************************************************\r
+#define ADC_SSCTL_TS7 0x80000000 // 8th temperature sensor select\r
+#define ADC_SSCTL_IE7 0x40000000 // 8th interrupt enable\r
+#define ADC_SSCTL_END7 0x20000000 // 8th sequence end select\r
+#define ADC_SSCTL_D7 0x10000000 // 8th differential select\r
+#define ADC_SSCTL_TS6 0x08000000 // 7th temperature sensor select\r
+#define ADC_SSCTL_IE6 0x04000000 // 7th interrupt enable\r
+#define ADC_SSCTL_END6 0x02000000 // 7th sequence end select\r
+#define ADC_SSCTL_D6 0x01000000 // 7th differential select\r
+#define ADC_SSCTL_TS5 0x00800000 // 6th temperature sensor select\r
+#define ADC_SSCTL_IE5 0x00400000 // 6th interrupt enable\r
+#define ADC_SSCTL_END5 0x00200000 // 6th sequence end select\r
+#define ADC_SSCTL_D5 0x00100000 // 6th differential select\r
+#define ADC_SSCTL_TS4 0x00080000 // 5th temperature sensor select\r
+#define ADC_SSCTL_IE4 0x00040000 // 5th interrupt enable\r
+#define ADC_SSCTL_END4 0x00020000 // 5th sequence end select\r
+#define ADC_SSCTL_D4 0x00010000 // 5th differential select\r
+#define ADC_SSCTL_TS3 0x00008000 // 4th temperature sensor select\r
+#define ADC_SSCTL_IE3 0x00004000 // 4th interrupt enable\r
+#define ADC_SSCTL_END3 0x00002000 // 4th sequence end select\r
+#define ADC_SSCTL_D3 0x00001000 // 4th differential select\r
+#define ADC_SSCTL_TS2 0x00000800 // 3rd temperature sensor select\r
+#define ADC_SSCTL_IE2 0x00000400 // 3rd interrupt enable\r
+#define ADC_SSCTL_END2 0x00000200 // 3rd sequence end select\r
+#define ADC_SSCTL_D2 0x00000100 // 3rd differential select\r
+#define ADC_SSCTL_TS1 0x00000080 // 2nd temperature sensor select\r
+#define ADC_SSCTL_IE1 0x00000040 // 2nd interrupt enable\r
+#define ADC_SSCTL_END1 0x00000020 // 2nd sequence end select\r
+#define ADC_SSCTL_D1 0x00000010 // 2nd differential select\r
+#define ADC_SSCTL_TS0 0x00000008 // 1st temperature sensor select\r
+#define ADC_SSCTL_IE0 0x00000004 // 1st interrupt enable\r
+#define ADC_SSCTL_END0 0x00000002 // 1st sequence end select\r
+#define ADC_SSCTL_D0 0x00000001 // 1st differential select\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the ADC_SSFIFO0, ADC_SSFIFO1,\r
+// ADC_SSFIFO2, and ADC_SSFIFO3 registers.\r
+//\r
+//*****************************************************************************\r
+#define ADC_SSFIFO_DATA_MASK 0x000003FF // Sample data\r
+#define ADC_SSFIFO_DATA_SHIFT 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the ADC_SSFSTAT0, ADC_SSFSTAT1,\r
+// ADC_SSFSTAT2, and ADC_SSFSTAT3 registers.\r
+//\r
+//*****************************************************************************\r
+#define ADC_SSFSTAT_FULL 0x00001000 // FIFO is full\r
+#define ADC_SSFSTAT_EMPTY 0x00000100 // FIFO is empty\r
+#define ADC_SSFSTAT_HPTR 0x000000F0 // FIFO head pointer\r
+#define ADC_SSFSTAT_TPTR 0x0000000F // FIFO tail pointer\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the ADC_TMLB register.\r
+//\r
+//*****************************************************************************\r
+#define ADC_TMLB_LB 0x00000001 // Loopback control signals\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the loopback ADC data.\r
+//\r
+//*****************************************************************************\r
+#define ADC_LB_CNT_MASK 0x000003C0 // Sample counter mask\r
+#define ADC_LB_CONT 0x00000020 // Continuation sample\r
+#define ADC_LB_DIFF 0x00000010 // Differential sample\r
+#define ADC_LB_TS 0x00000008 // Temperature sensor sample\r
+#define ADC_LB_MUX_MASK 0x00000007 // Input channel number mask\r
+#define ADC_LB_CNT_SHIFT 6 // Sample counter shift\r
+#define ADC_LB_MUX_SHIFT 0 // Input channel number shift\r
+\r
+#endif // __HW_ADC_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_can.h - Defines and macros used when accessing the can.\r
+//\r
+// Copyright (c) 2006-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_CAN_H__\r
+#define __HW_CAN_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the offsets of the can registers.\r
+//\r
+//*****************************************************************************\r
+#define CAN_O_CTL 0x00000000 // Control register\r
+#define CAN_O_STS 0x00000004 // Status register\r
+#define CAN_O_ERR 0x00000008 // Error register\r
+#define CAN_O_BIT 0x0000000C // Bit Timing register\r
+#define CAN_O_INT 0x00000010 // Interrupt register\r
+#define CAN_O_TST 0x00000014 // Test register\r
+#define CAN_O_BRPE 0x00000018 // Baud Rate Prescaler register\r
+#define CAN_O_IF1CRQ 0x00000020 // Interface 1 Command Request reg.\r
+#define CAN_O_IF1CMSK 0x00000024 // Interface 1 Command Mask reg.\r
+#define CAN_O_IF1MSK1 0x00000028 // Interface 1 Mask 1 register\r
+#define CAN_O_IF1MSK2 0x0000002C // Interface 1 Mask 2 register\r
+#define CAN_O_IF1ARB1 0x00000030 // Interface 1 Arbitration 1 reg.\r
+#define CAN_O_IF1ARB2 0x00000034 // Interface 1 Arbitration 2 reg.\r
+#define CAN_O_IF1MCTL 0x00000038 // Interface 1 Message Control reg.\r
+#define CAN_O_IF1DA1 0x0000003C // Interface 1 DataA 1 register\r
+#define CAN_O_IF1DA2 0x00000040 // Interface 1 DataA 2 register\r
+#define CAN_O_IF1DB1 0x00000044 // Interface 1 DataB 1 register\r
+#define CAN_O_IF1DB2 0x00000048 // Interface 1 DataB 2 register\r
+#define CAN_O_IF2CRQ 0x00000080 // Interface 2 Command Request reg.\r
+#define CAN_O_IF2CMSK 0x00000084 // Interface 2 Command Mask reg.\r
+#define CAN_O_IF2MSK1 0x00000088 // Interface 2 Mask 1 register\r
+#define CAN_O_IF2MSK2 0x0000008C // Interface 2 Mask 2 register\r
+#define CAN_O_IF2ARB1 0x00000090 // Interface 2 Arbitration 1 reg.\r
+#define CAN_O_IF2ARB2 0x00000094 // Interface 2 Arbitration 2 reg.\r
+#define CAN_O_IF2MCTL 0x00000098 // Interface 2 Message Control reg.\r
+#define CAN_O_IF2DA1 0x0000009C // Interface 2 DataA 1 register\r
+#define CAN_O_IF2DA2 0x000000A0 // Interface 2 DataA 2 register\r
+#define CAN_O_IF2DB1 0x000000A4 // Interface 2 DataB 1 register\r
+#define CAN_O_IF2DB2 0x000000A8 // Interface 2 DataB 2 register\r
+#define CAN_O_TXRQ1 0x00000100 // Transmission Request 1 register\r
+#define CAN_O_TXRQ2 0x00000104 // Transmission Request 2 register\r
+#define CAN_O_NWDA1 0x00000120 // New Data 1 register\r
+#define CAN_O_NWDA2 0x00000124 // New Data 2 register\r
+#define CAN_O_MSGINT1 0x00000140 // Intr. Pending in Msg Obj 1 reg.\r
+#define CAN_O_MSGINT2 0x00000144 // Intr. Pending in Msg Obj 2 reg.\r
+#define CAN_O_MSGVAL1 0x00000160 // Message Valid in Msg Obj 1 reg.\r
+#define CAN_O_MSGVAL2 0x00000164 // Message Valid in Msg Obj 2 reg.\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the reset values of the can registers.\r
+//\r
+//*****************************************************************************\r
+#define CAN_RV_CTL 0x00000001\r
+#define CAN_RV_STS 0x00000000\r
+#define CAN_RV_ERR 0x00000000\r
+#define CAN_RV_BIT 0x00002301\r
+#define CAN_RV_INT 0x00000000\r
+#define CAN_RV_TST 0x00000000\r
+#define CAN_RV_BRPE 0x00000000\r
+#define CAN_RV_IF1CRQ 0x00000001\r
+#define CAN_RV_IF1CMSK 0x00000000\r
+#define CAN_RV_IF1MSK1 0x0000FFFF\r
+#define CAN_RV_IF1MSK2 0x0000FFFF\r
+#define CAN_RV_IF1ARB1 0x00000000\r
+#define CAN_RV_IF1ARB2 0x00000000\r
+#define CAN_RV_IF1MCTL 0x00000000\r
+#define CAN_RV_IF1DA1 0x00000000\r
+#define CAN_RV_IF1DA2 0x00000000\r
+#define CAN_RV_IF1DB1 0x00000000\r
+#define CAN_RV_IF1DB2 0x00000000\r
+#define CAN_RV_IF2CRQ 0x00000001\r
+#define CAN_RV_IF2CMSK 0x00000000\r
+#define CAN_RV_IF2MSK1 0x0000FFFF\r
+#define CAN_RV_IF2MSK2 0x0000FFFF\r
+#define CAN_RV_IF2ARB1 0x00000000\r
+#define CAN_RV_IF2ARB2 0x00000000\r
+#define CAN_RV_IF2MCTL 0x00000000\r
+#define CAN_RV_IF2DA1 0x00000000\r
+#define CAN_RV_IF2DA2 0x00000000\r
+#define CAN_RV_IF2DB1 0x00000000\r
+#define CAN_RV_IF2DB2 0x00000000\r
+#define CAN_RV_TXRQ1 0x00000000\r
+#define CAN_RV_TXRQ2 0x00000000\r
+#define CAN_RV_NWDA1 0x00000000\r
+#define CAN_RV_NWDA2 0x00000000\r
+#define CAN_RV_MSGINT1 0x00000000\r
+#define CAN_RV_MSGINT2 0x00000000\r
+#define CAN_RV_MSGVAL1 0x00000000\r
+#define CAN_RV_MSGVAL2 0x00000000\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the CAN_CTL register.\r
+//\r
+//*****************************************************************************\r
+#define CAN_CTL_TEST 0x00000080 // Test mode enable\r
+#define CAN_CTL_CCE 0x00000040 // Configuration change enable\r
+#define CAN_CTL_DAR 0x00000020 // Disable automatic retransmission\r
+#define CAN_CTL_EIE 0x00000008 // Error interrupt enable\r
+#define CAN_CTL_SIE 0x00000004 // Status change interrupt enable\r
+#define CAN_CTL_IE 0x00000002 // Module interrupt enable\r
+#define CAN_CTL_INIT 0x00000001 // Initialization\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the CAN_STS register.\r
+//\r
+//*****************************************************************************\r
+#define CAN_STS_BOFF 0x00000080 // Bus Off status\r
+#define CAN_STS_EWARN 0x00000040 // Error Warning status\r
+#define CAN_STS_EPASS 0x00000020 // Error Passive status\r
+#define CAN_STS_RXOK 0x00000010 // Received Message Successful\r
+#define CAN_STS_TXOK 0x00000008 // Transmitted Message Successful\r
+#define CAN_STS_LEC_MSK 0x00000007 // Last Error Code\r
+#define CAN_STS_LEC_NONE 0x00000000 // No error\r
+#define CAN_STS_LEC_STUFF 0x00000001 // Stuff error\r
+#define CAN_STS_LEC_FORM 0x00000002 // Form(at) error\r
+#define CAN_STS_LEC_ACK 0x00000003 // Ack error\r
+#define CAN_STS_LEC_BIT1 0x00000004 // Bit 1 error\r
+#define CAN_STS_LEC_BIT0 0x00000005 // Bit 0 error\r
+#define CAN_STS_LEC_CRC 0x00000006 // CRC error\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the CAN_ERR register.\r
+//\r
+//*****************************************************************************\r
+#define CAN_ERR_RP 0x00008000 // Receive error passive status\r
+#define CAN_ERR_REC_MASK 0x00007F00 // Receive error counter status\r
+#define CAN_ERR_REC_SHIFT 8 // Receive error counter bit pos\r
+#define CAN_ERR_TEC_MASK 0x000000FF // Transmit error counter status\r
+#define CAN_ERR_TEC_SHIFT 0 // Transmit error counter bit pos\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the CAN_BIT register.\r
+//\r
+//*****************************************************************************\r
+#define CAN_BIT_TSEG2 0x00007000 // Time segment after sample point\r
+#define CAN_BIT_TSEG1 0x00000F00 // Time segment before sample point\r
+#define CAN_BIT_SJW 0x000000C0 // (Re)Synchronization jump width\r
+#define CAN_BIT_BRP 0x0000003F // Baud rate prescaler\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the CAN_INT register.\r
+//\r
+//*****************************************************************************\r
+#define CAN_INT_INTID_MSK 0x0000FFFF // Interrupt Identifier\r
+#define CAN_INT_INTID_NONE 0x00000000 // No Interrupt Pending\r
+#define CAN_INT_INTID_STATUS 0x00008000 // Status Interrupt\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the CAN_TST register.\r
+//\r
+//*****************************************************************************\r
+#define CAN_TST_RX 0x00000080 // CAN_RX pin status\r
+#define CAN_TST_TX_MSK 0x00000060 // Overide control of CAN_TX pin\r
+#define CAN_TST_TX_CANCTL 0x00000000 // CAN core controls CAN_TX\r
+#define CAN_TST_TX_SAMPLE 0x00000020 // Sample Point on CAN_TX\r
+#define CAN_TST_TX_DOMINANT 0x00000040 // Dominant value on CAN_TX\r
+#define CAN_TST_TX_RECESSIVE 0x00000060 // Recessive value on CAN_TX\r
+#define CAN_TST_LBACK 0x00000010 // Loop back mode\r
+#define CAN_TST_SILENT 0x00000008 // Silent mode\r
+#define CAN_TST_BASIC 0x00000004 // Basic mode\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the CAN_BRPE register.\r
+//\r
+//*****************************************************************************\r
+#define CAN_BRPE_BRPE 0x0000000F // Baud rate prescaler extension\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the CAN_IF1CRQ and CAN_IF1CRQ\r
+// registers.\r
+// Note: All bits may not be available in all registers\r
+//\r
+//*****************************************************************************\r
+#define CAN_IFCRQ_BUSY 0x00008000 // Busy flag status\r
+#define CAN_IFCRQ_MNUM_MSK 0x0000003F // Message Number\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the CAN_IF1CMSK and CAN_IF2CMSK\r
+// registers.\r
+// Note: All bits may not be available in all registers\r
+//\r
+//*****************************************************************************\r
+#define CAN_IFCMSK_WRNRD 0x00000080 // Write, not Read\r
+#define CAN_IFCMSK_MASK 0x00000040 // Access Mask Bits\r
+#define CAN_IFCMSK_ARB 0x00000020 // Access Arbitration Bits\r
+#define CAN_IFCMSK_CONTROL 0x00000010 // Access Control Bits\r
+#define CAN_IFCMSK_CLRINTPND 0x00000008 // Clear interrupt pending Bit\r
+#define CAN_IFCMSK_TXRQST 0x00000004 // Access Tx request bit (WRNRD=1)\r
+#define CAN_IFCMSK_NEWDAT 0x00000004 // Access New Data bit (WRNRD=0)\r
+#define CAN_IFCMSK_DATAA 0x00000002 // DataA access - bytes 0 to 3\r
+#define CAN_IFCMSK_DATAB 0x00000001 // DataB access - bytes 4 to 7\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the CAN_IF1MSK1 and CAN_IF2MSK1\r
+// registers.\r
+// Note: All bits may not be available in all registers\r
+//\r
+//*****************************************************************************\r
+#define CAN_IFMSK1_MSK 0x0000FFFF // Identifier Mask\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the CAN_IF1MSK2 and CAN_IF2MSK2\r
+// registers.\r
+// Note: All bits may not be available in all registers\r
+//\r
+//*****************************************************************************\r
+#define CAN_IFMSK2_MXTD 0x00008000 // Mask extended identifier\r
+#define CAN_IFMSK2_MDIR 0x00004000 // Mask message direction\r
+#define CAN_IFMSK2_MSK 0x00001FFF // Mask identifier\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the CAN_IF1ARB1 and CAN_IF2ARB1\r
+// registers.\r
+// Note: All bits may not be available in all registers\r
+//\r
+//*****************************************************************************\r
+#define CAN_IFARB1_ID 0x0000FFFF // Identifier\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the CAN_IF1ARB2 and CAN_IF2ARB2\r
+// registers.\r
+// Note: All bits may not be available in all registers\r
+//\r
+//*****************************************************************************\r
+#define CAN_IFARB2_MSGVAL 0x00008000 // Message valid\r
+#define CAN_IFARB2_XTD 0x00004000 // Extended identifier\r
+#define CAN_IFARB2_DIR 0x00002000 // Message direction\r
+#define CAN_IFARB2_ID 0x00001FFF // Message identifier\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the CAN_IF1MCTL and CAN_IF2MCTL\r
+// registers.\r
+// Note: All bits may not be available in all registers\r
+//\r
+//*****************************************************************************\r
+#define CAN_IFMCTL_NEWDAT 0x00008000 // New Data\r
+#define CAN_IFMCTL_MSGLST 0x00004000 // Message lost\r
+#define CAN_IFMCTL_INTPND 0x00002000 // Interrupt pending\r
+#define CAN_IFMCTL_UMASK 0x00001000 // Use acceptance mask\r
+#define CAN_IFMCTL_TXIE 0x00000800 // Transmit interrupt enable\r
+#define CAN_IFMCTL_RXIE 0x00000400 // Receive interrupt enable\r
+#define CAN_IFMCTL_RMTEN 0x00000200 // Remote enable\r
+#define CAN_IFMCTL_TXRQST 0x00000100 // Transmit request\r
+#define CAN_IFMCTL_EOB 0x00000080 // End of buffer\r
+#define CAN_IFMCTL_DLC 0x0000000F // Data length code\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the CAN_IF1DA1 and CAN_IF2DA1\r
+// registers.\r
+// Note: All bits may not be available in all registers\r
+//\r
+//*****************************************************************************\r
+#define CAN_IFDA1_DATA 0x0000FFFF // Data - bytes 1 and 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the CAN_IF1DA2 and CAN_IF2DA2\r
+// registers.\r
+// Note: All bits may not be available in all registers\r
+//\r
+//*****************************************************************************\r
+#define CAN_IFDA2_DATA 0x0000FFFF // Data - bytes 3 and 2\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the CAN_IF1DB1 and CAN_IF2DB1\r
+// registers.\r
+// Note: All bits may not be available in all registers\r
+//\r
+//*****************************************************************************\r
+#define CAN_IFDB1_DATA 0x0000FFFF // Data - bytes 5 and 4\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the CAN_IF1DB2 and CAN_IF2DB2\r
+// registers.\r
+// Note: All bits may not be available in all registers\r
+//\r
+//*****************************************************************************\r
+#define CAN_IFDB2_DATA 0x0000FFFF // Data - bytes 7 and 6\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the CAN_TXRQ1 register.\r
+//\r
+//*****************************************************************************\r
+#define CAN_TXRQ1_TXRQST 0x0000FFFF // Transmission Request Bits\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the CAN_TXRQ2 register.\r
+//\r
+//*****************************************************************************\r
+#define CAN_TXRQ2_TXRQST 0x0000FFFF // Transmission Request Bits\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the CAN_NWDA1 register.\r
+//\r
+//*****************************************************************************\r
+#define CAN_NWDA1_NEWDATA 0x0000FFFF // New Data Bits\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the CAN_NWDA2 register.\r
+//\r
+//*****************************************************************************\r
+#define CAN_NWDA2_NEWDATA 0x0000FFFF // New Data Bits\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the CAN_MSGINT1 register.\r
+//\r
+//*****************************************************************************\r
+#define CAN_MSGINT1_INTPND 0x0000FFFF // Interrupt Pending Bits\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the CAN_MSGINT2 register.\r
+//\r
+//*****************************************************************************\r
+#define CAN_MSGINT2_INTPND 0x0000FFFF // Interrupt Pending Bits\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the CAN_MSGVAL1 register.\r
+//\r
+//*****************************************************************************\r
+#define CAN_MSGVAL1_MSGVAL 0x0000FFFF // Message Valid Bits\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the CAN_MSGVAL2 register.\r
+//\r
+//*****************************************************************************\r
+#define CAN_MSGVAL2_MSGVAL 0x0000FFFF // Message Valid Bits\r
+\r
+#endif // __HW_CAN_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_comp.h - Macros used when accessing the comparator hardware.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_COMP_H__\r
+#define __HW_COMP_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the offsets of the comparator registers.\r
+//\r
+//*****************************************************************************\r
+#define COMP_O_MIS 0x00000000 // Interrupt status register\r
+#define COMP_O_RIS 0x00000004 // Raw interrupt status register\r
+#define COMP_O_INTEN 0x00000008 // Interrupt enable register\r
+#define COMP_O_REFCTL 0x00000010 // Reference voltage control reg.\r
+#define COMP_O_ACSTAT0 0x00000020 // Comp0 status register\r
+#define COMP_O_ACCTL0 0x00000024 // Comp0 control register\r
+#define COMP_O_ACSTAT1 0x00000040 // Comp1 status register\r
+#define COMP_O_ACCTL1 0x00000044 // Comp1 control register\r
+#define COMP_O_ACSTAT2 0x00000060 // Comp2 status register\r
+#define COMP_O_ACCTL2 0x00000064 // Comp2 control register\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the COMP_MIS, COMP_RIS, and\r
+// COMP_INTEN registers.\r
+//\r
+//*****************************************************************************\r
+#define COMP_INT_2 0x00000004 // Comp2 interrupt\r
+#define COMP_INT_1 0x00000002 // Comp1 interrupt\r
+#define COMP_INT_0 0x00000001 // Comp0 interrupt\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the COMP_REFCTL register.\r
+//\r
+//*****************************************************************************\r
+#define COMP_REFCTL_EN 0x00000200 // Reference voltage enable\r
+#define COMP_REFCTL_RNG 0x00000100 // Reference voltage range\r
+#define COMP_REFCTL_VREF_MASK 0x0000000F // Reference voltage select mask\r
+#define COMP_REFCTL_VREF_SHIFT 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the COMP_ACSTAT0, COMP_ACSTAT1, and\r
+// COMP_ACSTAT2 registers.\r
+//\r
+//*****************************************************************************\r
+#define COMP_ACSTAT_OVAL 0x00000002 // Comparator output value\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the COMP_ACCTL0, COMP_ACCTL1, and\r
+// COMP_ACCTL2 registers.\r
+//\r
+//*****************************************************************************\r
+#define COMP_ACCTL_TMASK 0x00000800 // Trigger enable\r
+#define COMP_ACCTL_ASRCP_MASK 0x00000600 // Vin+ source select mask\r
+#define COMP_ACCTL_ASRCP_PIN 0x00000000 // Dedicated Comp+ pin\r
+#define COMP_ACCTL_ASRCP_PIN0 0x00000200 // Comp0+ pin\r
+#define COMP_ACCTL_ASRCP_REF 0x00000400 // Internal voltage reference\r
+#define COMP_ACCTL_ASRCP_RES 0x00000600 // Reserved\r
+#define COMP_ACCTL_OEN 0x00000100 // Comparator output enable\r
+#define COMP_ACCTL_TSVAL 0x00000080 // Trigger polarity select\r
+#define COMP_ACCTL_TSEN_MASK 0x00000060 // Trigger sense mask\r
+#define COMP_ACCTL_TSEN_LEVEL 0x00000000 // Trigger is level sense\r
+#define COMP_ACCTL_TSEN_FALL 0x00000020 // Trigger is falling edge\r
+#define COMP_ACCTL_TSEN_RISE 0x00000040 // Trigger is rising edge\r
+#define COMP_ACCTL_TSEN_BOTH 0x00000060 // Trigger is both edges\r
+#define COMP_ACCTL_ISLVAL 0x00000010 // Interrupt polarity select\r
+#define COMP_ACCTL_ISEN_MASK 0x0000000C // Interrupt sense mask\r
+#define COMP_ACCTL_ISEN_LEVEL 0x00000000 // Interrupt is level sense\r
+#define COMP_ACCTL_ISEN_FALL 0x00000004 // Interrupt is falling edge\r
+#define COMP_ACCTL_ISEN_RISE 0x00000008 // Interrupt is rising edge\r
+#define COMP_ACCTL_ISEN_BOTH 0x0000000C // Interrupt is both edges\r
+#define COMP_ACCTL_CINV 0x00000002 // Comparator output invert\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the reset values for the comparator registers.\r
+//\r
+//*****************************************************************************\r
+#define COMP_RV_MIS 0x00000000 // Interrupt status register\r
+#define COMP_RV_RIS 0x00000000 // Raw interrupt status register\r
+#define COMP_RV_INTEN 0x00000000 // Interrupt enable register\r
+#define COMP_RV_REFCTL 0x00000000 // Reference voltage control reg.\r
+#define COMP_RV_ACSTAT0 0x00000000 // Comp0 status register\r
+#define COMP_RV_ACCTL0 0x00000000 // Comp0 control register\r
+#define COMP_RV_ACSTAT1 0x00000000 // Comp1 status register\r
+#define COMP_RV_ACCTL1 0x00000000 // Comp1 control register\r
+#define COMP_RV_ACSTAT2 0x00000000 // Comp2 status register\r
+#define COMP_RV_ACCTL2 0x00000000 // Comp2 control register\r
+\r
+#endif // __HW_COMP_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_ethernet.h - Macros used when accessing the ethernet hardware.\r
+//\r
+// Copyright (c) 2006-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_ETHERNET_H__\r
+#define __HW_ETHERNET_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the offsets of the MAC registers in the Ethernet\r
+// Controller.\r
+//\r
+//*****************************************************************************\r
+#define MAC_O_IS 0x00000000 // Interrupt Status Register\r
+#define MAC_O_IACK 0x00000000 // Interrupt Acknowledge Register\r
+#define MAC_O_IM 0x00000004 // Interrupt Mask Register\r
+#define MAC_O_RCTL 0x00000008 // Receive Control Register\r
+#define MAC_O_TCTL 0x0000000C // Transmit Control Register\r
+#define MAC_O_DATA 0x00000010 // Data Register\r
+#define MAC_O_IA0 0x00000014 // Individual Address Register 0\r
+#define MAC_O_IA1 0x00000018 // Individual Address Register 1\r
+#define MAC_O_THR 0x0000001C // Threshold Register\r
+#define MAC_O_MCTL 0x00000020 // Management Control Register\r
+#define MAC_O_MDV 0x00000024 // Management Divider Register\r
+#define MAC_O_MADD 0x00000028 // Management Address Register\r
+#define MAC_O_MTXD 0x0000002C // Management Transmit Data Reg\r
+#define MAC_O_MRXD 0x00000030 // Management Receive Data Reg\r
+#define MAC_O_NP 0x00000034 // Number of Packets Register\r
+#define MAC_O_TR 0x00000038 // Transmission Request Register\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the reset values of the MAC registers.\r
+//\r
+//*****************************************************************************\r
+#define MAC_RV_IS 0x00000000\r
+#define MAC_RV_IACK 0x00000000\r
+#define MAC_RV_IM 0x0000007F\r
+#define MAC_RV_RCTL 0x00000008\r
+#define MAC_RV_TCTL 0x00000000\r
+#define MAC_RV_DATA 0x00000000\r
+#define MAC_RV_IA0 0x00000000\r
+#define MAC_RV_IA1 0x00000000\r
+#define MAC_RV_THR 0x0000003F\r
+#define MAC_RV_MCTL 0x00000000\r
+#define MAC_RV_MDV 0x00000080\r
+#define MAC_RV_MADD 0x00000000\r
+#define MAC_RV_MTXD 0x00000000\r
+#define MAC_RV_MRXD 0x00000000\r
+#define MAC_RV_NP 0x00000000\r
+#define MAC_RV_TR 0x00000000\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the MAC_IS register.\r
+//\r
+//*****************************************************************************\r
+#define MAC_IS_PHYINT 0x00000040 // PHY Interrupt\r
+#define MAC_IS_MDINT 0x00000020 // MDI Transaction Complete\r
+#define MAC_IS_RXER 0x00000010 // RX Error\r
+#define MAC_IS_FOV 0x00000008 // RX FIFO Overrun\r
+#define MAC_IS_TXEMP 0x00000004 // TX FIFO Empy\r
+#define MAC_IS_TXER 0x00000002 // TX Error\r
+#define MAC_IS_RXINT 0x00000001 // RX Packet Available\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the MAC_IACK register.\r
+//\r
+//*****************************************************************************\r
+#define MAC_IACK_PHYINT 0x00000040 // Clear PHY Interrupt\r
+#define MAC_IACK_MDINT 0x00000020 // Clear MDI Transaction Complete\r
+#define MAC_IACK_RXER 0x00000010 // Clear RX Error\r
+#define MAC_IACK_FOV 0x00000008 // Clear RX FIFO Overrun\r
+#define MAC_IACK_TXEMP 0x00000004 // Clear TX FIFO Empy\r
+#define MAC_IACK_TXER 0x00000002 // Clear TX Error\r
+#define MAC_IACK_RXINT 0x00000001 // Clear RX Packet Available\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the MAC_IM register.\r
+//\r
+//*****************************************************************************\r
+#define MAC_IM_PHYINTM 0x00000040 // Mask PHY Interrupt\r
+#define MAC_IM_MDINTM 0x00000020 // Mask MDI Transaction Complete\r
+#define MAC_IM_RXERM 0x00000010 // Mask RX Error\r
+#define MAC_IM_FOVM 0x00000008 // Mask RX FIFO Overrun\r
+#define MAC_IM_TXEMPM 0x00000004 // Mask TX FIFO Empy\r
+#define MAC_IM_TXERM 0x00000002 // Mask TX Error\r
+#define MAC_IM_RXINTM 0x00000001 // Mask RX Packet Available\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the MAC_RCTL register.\r
+//\r
+//*****************************************************************************\r
+#define MAC_RCTL_RSTFIFO 0x00000010 // Clear the Receive FIFO\r
+#define MAC_RCTL_BADCRC 0x00000008 // Reject Packets With Bad CRC\r
+#define MAC_RCTL_PRMS 0x00000004 // Enable Promiscuous Mode\r
+#define MAC_RCTL_AMUL 0x00000002 // Enable Multicast Packets\r
+#define MAC_RCTL_RXEN 0x00000001 // Enable Ethernet Receiver\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the MAC_TCTL register.\r
+//\r
+//*****************************************************************************\r
+#define MAC_TCTL_DUPLEX 0x00000010 // Enable Duplex mode\r
+#define MAC_TCTL_CRC 0x00000004 // Enable CRC Generation\r
+#define MAC_TCTL_PADEN 0x00000002 // Enable Automatic Padding\r
+#define MAC_TCTL_TXEN 0x00000001 // Enable Ethernet Transmitter\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the MAC_IA0 register.\r
+//\r
+//*****************************************************************************\r
+#define MAC_IA0_MACOCT4 0xFF000000 // 4th Octet of MAC address\r
+#define MAC_IA0_MACOCT3 0x00FF0000 // 3rd Octet of MAC address\r
+#define MAC_IA0_MACOCT2 0x0000FF00 // 2nd Octet of MAC address\r
+#define MAC_IA0_MACOCT1 0x000000FF // 1st Octet of MAC address\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the MAC_IA1 register.\r
+//\r
+//*****************************************************************************\r
+#define MAC_IA1_MACOCT6 0x0000FF00 // 6th Octet of MAC address\r
+#define MAC_IA1_MACOCT5 0x000000FF // 5th Octet of MAC address\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the MAC_TXTH register.\r
+//\r
+//*****************************************************************************\r
+#define MAC_THR_THRESH 0x0000003F // Transmit Threshold Value\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the MAC_MCTL register.\r
+//\r
+//*****************************************************************************\r
+#define MAC_MCTL_REGADR 0x000000F8 // Address for Next MII Transaction\r
+#define MAC_MCTL_WRITE 0x00000002 // Next MII Transaction is Write\r
+#define MAC_MCTL_START 0x00000001 // Start MII Transaction\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the MAC_MDV register.\r
+//\r
+//*****************************************************************************\r
+#define MAC_MDV_DIV 0x000000FF // Clock Divider for MDC for TX\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the MAC_MTXD register.\r
+//\r
+//*****************************************************************************\r
+#define MAC_MTXD_MDTX 0x0000FFFF // Data for Next MII Transaction\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the MAC_MRXD register.\r
+//\r
+//*****************************************************************************\r
+#define MAC_MRXD_MDRX 0x0000FFFF // Data Read from Last MII Trans.\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the MAC_NP register.\r
+//\r
+//*****************************************************************************\r
+#define MAC_NP_NPR 0x0000003F // Number of RX Frames in FIFO\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the MAC_TXRQ register.\r
+//\r
+//*****************************************************************************\r
+#define MAC_TR_NEWTX 0x00000001 // Start an Ethernet Transmission\r
+\r
+#endif // __HW_ETHERNET_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_flash.h - Macros used when accessing the flash controller.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_FLASH_H__\r
+#define __HW_FLASH_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the offsets of the FLASH registers.\r
+//\r
+//*****************************************************************************\r
+#define FLASH_FMA 0x400FD000 // Memory address register\r
+#define FLASH_FMD 0x400FD004 // Memory data register\r
+#define FLASH_FMC 0x400FD008 // Memory control register\r
+#define FLASH_FCRIS 0x400FD00c // Raw interrupt status register\r
+#define FLASH_FCIM 0x400FD010 // Interrupt mask register\r
+#define FLASH_FCMISC 0x400FD014 // Interrupt status register\r
+#define FLASH_FMPRE 0x400FE130 // FLASH read protect register\r
+#define FLASH_FMPPE 0x400FE134 // FLASH program protect register\r
+#define FLASH_USECRL 0x400FE140 // uSec reload register\r
+#define FLASH_FMPRE0 0x400FE200 // FLASH read protect register 0\r
+#define FLASH_FMPRE1 0x400FE204 // FLASH read protect register 1\r
+#define FLASH_FMPRE2 0x400FE208 // FLASH read protect register 2\r
+#define FLASH_FMPRE3 0x400FE20C // FLASH read protect register 3\r
+#define FLASH_FMPPE0 0x400FE400 // FLASH program protect register 0\r
+#define FLASH_FMPPE1 0x400FE404 // FLASH program protect register 1\r
+#define FLASH_FMPPE2 0x400FE408 // FLASH program protect register 2\r
+#define FLASH_FMPPE3 0x400FE40C // FLASH program protect register 3\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the FLASH_FMC register.\r
+//\r
+//*****************************************************************************\r
+#define FLASH_FMC_WRKEY_MASK 0xFFFF0000 // FLASH write key mask\r
+#define FLASH_FMC_WRKEY 0xA4420000 // FLASH write key\r
+#define FLASH_FMC_COMT 0x00000008 // Commit user register\r
+#define FLASH_FMC_MERASE 0x00000004 // Mass erase FLASH\r
+#define FLASH_FMC_ERASE 0x00000002 // Erase FLASH page\r
+#define FLASH_FMC_WRITE 0x00000001 // Write FLASH word\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the FLASH_FCRIS register.\r
+//\r
+//*****************************************************************************\r
+#define FLASH_FCRIS_PROGRAM 0x00000002 // Programming status\r
+#define FLASH_FCRIS_ACCESS 0x00000001 // Invalid access status\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the FLASH_FCIM register.\r
+//\r
+//*****************************************************************************\r
+#define FLASH_FCIM_PROGRAM 0x00000002 // Programming mask\r
+#define FLASH_FCIM_ACCESS 0x00000001 // Invalid access mask\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the FLASH_FMIS register.\r
+//\r
+//*****************************************************************************\r
+#define FLASH_FCMISC_PROGRAM 0x00000002 // Programming status\r
+#define FLASH_FCMISC_ACCESS 0x00000001 // Invalid access status\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the FLASH_FMPRE and FLASH_FMPPE\r
+// registers.\r
+//\r
+//*****************************************************************************\r
+#define FLASH_FMP_BLOCK_31 0x80000000 // Enable for block 31\r
+#define FLASH_FMP_BLOCK_30 0x40000000 // Enable for block 30\r
+#define FLASH_FMP_BLOCK_29 0x20000000 // Enable for block 29\r
+#define FLASH_FMP_BLOCK_28 0x10000000 // Enable for block 28\r
+#define FLASH_FMP_BLOCK_27 0x08000000 // Enable for block 27\r
+#define FLASH_FMP_BLOCK_26 0x04000000 // Enable for block 26\r
+#define FLASH_FMP_BLOCK_25 0x02000000 // Enable for block 25\r
+#define FLASH_FMP_BLOCK_24 0x01000000 // Enable for block 24\r
+#define FLASH_FMP_BLOCK_23 0x00800000 // Enable for block 23\r
+#define FLASH_FMP_BLOCK_22 0x00400000 // Enable for block 22\r
+#define FLASH_FMP_BLOCK_21 0x00200000 // Enable for block 21\r
+#define FLASH_FMP_BLOCK_20 0x00100000 // Enable for block 20\r
+#define FLASH_FMP_BLOCK_19 0x00080000 // Enable for block 19\r
+#define FLASH_FMP_BLOCK_18 0x00040000 // Enable for block 18\r
+#define FLASH_FMP_BLOCK_17 0x00020000 // Enable for block 17\r
+#define FLASH_FMP_BLOCK_16 0x00010000 // Enable for block 16\r
+#define FLASH_FMP_BLOCK_15 0x00008000 // Enable for block 15\r
+#define FLASH_FMP_BLOCK_14 0x00004000 // Enable for block 14\r
+#define FLASH_FMP_BLOCK_13 0x00002000 // Enable for block 13\r
+#define FLASH_FMP_BLOCK_12 0x00001000 // Enable for block 12\r
+#define FLASH_FMP_BLOCK_11 0x00000800 // Enable for block 11\r
+#define FLASH_FMP_BLOCK_10 0x00000400 // Enable for block 10\r
+#define FLASH_FMP_BLOCK_9 0x00000200 // Enable for block 9\r
+#define FLASH_FMP_BLOCK_8 0x00000100 // Enable for block 8\r
+#define FLASH_FMP_BLOCK_7 0x00000080 // Enable for block 7\r
+#define FLASH_FMP_BLOCK_6 0x00000040 // Enable for block 6\r
+#define FLASH_FMP_BLOCK_5 0x00000020 // Enable for block 5\r
+#define FLASH_FMP_BLOCK_4 0x00000010 // Enable for block 4\r
+#define FLASH_FMP_BLOCK_3 0x00000008 // Enable for block 3\r
+#define FLASH_FMP_BLOCK_2 0x00000004 // Enable for block 2\r
+#define FLASH_FMP_BLOCK_1 0x00000002 // Enable for block 1\r
+#define FLASH_FMP_BLOCK_0 0x00000001 // Enable for block 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the FLASH_USECRL register.\r
+//\r
+//*****************************************************************************\r
+#define FLASH_USECRL_MASK 0x000000FF // Clock per uSec\r
+#define FLASH_USECRL_SHIFT 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The erase size is the size of the FLASH block that is erased by an erase\r
+// operation, and the protect size is the size of the FLASH block that is\r
+// protected by each protection register.\r
+//\r
+//*****************************************************************************\r
+#define FLASH_ERASE_SIZE 0x00000400\r
+#define FLASH_PROTECT_SIZE 0x00000800\r
+\r
+#endif // __HW_FLASH_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_gpio.h - Defines and Macros for GPIO hardware.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_GPIO_H__\r
+#define __HW_GPIO_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// GPIO Register Offsets.\r
+//\r
+//*****************************************************************************\r
+#define GPIO_O_DATA 0x00000000 // Data register.\r
+#define GPIO_O_DIR 0x00000400 // Data direction register.\r
+#define GPIO_O_IS 0x00000404 // Interrupt sense register.\r
+#define GPIO_O_IBE 0x00000408 // Interrupt both edges register.\r
+#define GPIO_O_IEV 0x0000040C // Intterupt event register.\r
+#define GPIO_O_IM 0x00000410 // Interrupt mask register.\r
+#define GPIO_O_RIS 0x00000414 // Raw interrupt status register.\r
+#define GPIO_O_MIS 0x00000418 // Masked interrupt status reg.\r
+#define GPIO_O_ICR 0x0000041C // Interrupt clear register.\r
+#define GPIO_O_AFSEL 0x00000420 // Mode control select register.\r
+#define GPIO_O_DR2R 0x00000500 // 2ma drive select register.\r
+#define GPIO_O_DR4R 0x00000504 // 4ma drive select register.\r
+#define GPIO_O_DR8R 0x00000508 // 8ma drive select register.\r
+#define GPIO_O_ODR 0x0000050C // Open drain select register.\r
+#define GPIO_O_PUR 0x00000510 // Pull up select register.\r
+#define GPIO_O_PDR 0x00000514 // Pull down select register.\r
+#define GPIO_O_SLR 0x00000518 // Slew rate control enable reg.\r
+#define GPIO_O_DEN 0x0000051C // Digital input enable register.\r
+#define GPIO_O_LOCK 0x00000520 // Lock register.\r
+#define GPIO_O_CR 0x00000524 // Commit register.\r
+#define GPIO_O_PeriphID4 0x00000FD0 //\r
+#define GPIO_O_PeriphID5 0x00000FD4 //\r
+#define GPIO_O_PeriphID6 0x00000FD8 //\r
+#define GPIO_O_PeriphID7 0x00000FDC //\r
+#define GPIO_O_PeriphID0 0x00000FE0 //\r
+#define GPIO_O_PeriphID1 0x00000FE4 //\r
+#define GPIO_O_PeriphID2 0x00000FE8 //\r
+#define GPIO_O_PeriphID3 0x00000FEC //\r
+#define GPIO_O_PCellID0 0x00000FF0 //\r
+#define GPIO_O_PCellID1 0x00000FF4 //\r
+#define GPIO_O_PCellID2 0x00000FF8 //\r
+#define GPIO_O_PCellID3 0x00000FFC //\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the GPIO_LOCK register.\r
+//\r
+//*****************************************************************************\r
+#define GPIO_LOCK_LOCKED 0x00000001 // GPIO_CR register is locked\r
+#define GPIO_LOCK_UNLOCKED 0x00000000 // GPIO_CR register is unlocked\r
+#define GPIO_LOCK_KEY 0x1ACCE551 // Unlocks the GPIO_CR register\r
+\r
+//*****************************************************************************\r
+//\r
+// GPIO Register reset values.\r
+//\r
+//*****************************************************************************\r
+#define GPIO_RV_DATA 0x00000000 // Data register reset value.\r
+#define GPIO_RV_DIR 0x00000000 // Data direction reg RV.\r
+#define GPIO_RV_IS 0x00000000 // Interrupt sense reg RV.\r
+#define GPIO_RV_IBE 0x00000000 // Interrupt both edges reg RV.\r
+#define GPIO_RV_IEV 0x00000000 // Intterupt event reg RV.\r
+#define GPIO_RV_IM 0x00000000 // Interrupt mask reg RV.\r
+#define GPIO_RV_RIS 0x00000000 // Raw interrupt status reg RV.\r
+#define GPIO_RV_MIS 0x00000000 // Masked interrupt status reg RV.\r
+#define GPIO_RV_IC 0x00000000 // Interrupt clear reg RV.\r
+#define GPIO_RV_AFSEL 0x00000000 // Mode control select reg RV.\r
+#define GPIO_RV_DR2R 0x000000FF // 2ma drive select reg RV.\r
+#define GPIO_RV_DR4R 0x00000000 // 4ma drive select reg RV.\r
+#define GPIO_RV_DR8R 0x00000000 // 8ma drive select reg RV.\r
+#define GPIO_RV_ODR 0x00000000 // Open drain select reg RV.\r
+#define GPIO_RV_PUR 0x000000FF // Pull up select reg RV.\r
+#define GPIO_RV_PDR 0x00000000 // Pull down select reg RV.\r
+#define GPIO_RV_SLR 0x00000000 // Slew rate control enable reg RV.\r
+#define GPIO_RV_DEN 0x000000FF // Digital input enable reg RV.\r
+#define GPIO_RV_LOCK 0x00000001 // Lock register RV.\r
+#define GPIO_RV_PeriphID4 0x00000000 //\r
+#define GPIO_RV_PeriphID5 0x00000000 //\r
+#define GPIO_RV_PeriphID6 0x00000000 //\r
+#define GPIO_RV_PeriphID7 0x00000000 //\r
+#define GPIO_RV_PeriphID0 0x00000061 //\r
+#define GPIO_RV_PeriphID1 0x00000010 //\r
+#define GPIO_RV_PeriphID2 0x00000004 //\r
+#define GPIO_RV_PeriphID3 0x00000000 //\r
+#define GPIO_RV_PCellID0 0x0000000D //\r
+#define GPIO_RV_PCellID1 0x000000F0 //\r
+#define GPIO_RV_PCellID2 0x00000005 //\r
+#define GPIO_RV_PCellID3 0x000000B1 //\r
+\r
+#endif // __HW_GPIO_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_hibernate.h - Defines and Macros for the Hibernation module.\r
+//\r
+// Copyright (c) 2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_HIBERNATE_H__\r
+#define __HW_HIBERNATE_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the addresses of the hibernation module registers.\r
+//\r
+//*****************************************************************************\r
+#define HIB_RTCC 0x400fc000 // Hibernate RTC counter\r
+#define HIB_RTCM0 0x400fc004 // Hibernate RTC match 0\r
+#define HIB_RTCM1 0x400fc008 // Hibernate RTC match 1\r
+#define HIB_RTCLD 0x400fc00C // Hibernate RTC load\r
+#define HIB_CTL 0x400fc010 // Hibernate RTC control\r
+#define HIB_IM 0x400fc014 // Hibernate interrupt mask\r
+#define HIB_RIS 0x400fc018 // Hibernate raw interrupt status\r
+#define HIB_MIS 0x400fc01C // Hibernate masked interrupt stat\r
+#define HIB_IC 0x400fc020 // Hibernate interrupt clear\r
+#define HIB_RTCT 0x400fc024 // Hibernate RTC trim\r
+#define HIB_DATA 0x400fc030 // Hibernate data area\r
+#define HIB_DATA_END 0x400fc130 // end of data area, exclusive\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the Hibernate RTC counter register.\r
+//\r
+//*****************************************************************************\r
+#define HIB_RTCC_MASK 0xffffffff // RTC counter mask\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the Hibernate RTC match 0 register.\r
+//\r
+//*****************************************************************************\r
+#define HIB_RTCM0_MASK 0xffffffff // RTC match 0 mask\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the Hibernate RTC match 1 register.\r
+//\r
+//*****************************************************************************\r
+#define HIB_RTCM1_MASK 0xffffffff // RTC match 1 mask\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the Hibernate RTC load register.\r
+//\r
+//*****************************************************************************\r
+#define HIB_RTCLD_MASK 0xffffffff // RTC load mask\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the Hibernate control register\r
+//\r
+//*****************************************************************************\r
+#define HIB_CTL_VABORT 0x00000080 // low bat abort\r
+#define HIB_CTL_CLK32EN 0x00000040 // enable clock/oscillator\r
+#define HIB_CTL_LOWBATEN 0x00000020 // enable low battery detect\r
+#define HIB_CTL_PINWEN 0x00000010 // enable wake on WAKE pin\r
+#define HIB_CTL_RTCWEN 0x00000008 // enable wake on RTC match\r
+#define HIB_CTL_CLKSEL 0x00000004 // clock input selection\r
+#define HIB_CTL_HIBREQ 0x00000002 // request hibernation\r
+#define HIB_CTL_RTCEN 0x00000001 // RTC enable\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the Hibernate interrupt mask reg.\r
+//\r
+//*****************************************************************************\r
+#define HIB_IM_EXTW 0x00000008 // wake from external pin interrupt\r
+#define HIB_IM_LOWBAT 0x00000004 // low battery interrupt\r
+#define HIB_IM_RTCALT1 0x00000002 // RTC match 1 interrupt\r
+#define HIB_IM_RTCALT0 0x00000001 // RTC match 0 interrupt\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the Hibernate raw interrupt status.\r
+//\r
+//*****************************************************************************\r
+#define HIB_RIS_EXTW 0x00000008 // wake from external pin interrupt\r
+#define HIB_RIS_LOWBAT 0x00000004 // low battery interrupt\r
+#define HIB_RIS_RTCALT1 0x00000002 // RTC match 1 interrupt\r
+#define HIB_RID_RTCALT0 0x00000001 // RTC match 0 interrupt\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the Hibernate masked int status.\r
+//\r
+//*****************************************************************************\r
+#define HIB_MIS_EXTW 0x00000008 // wake from external pin interrupt\r
+#define HIB_MIS_LOWBAT 0x00000004 // low battery interrupt\r
+#define HIB_MIS_RTCALT1 0x00000002 // RTC match 1 interrupt\r
+#define HIB_MID_RTCALT0 0x00000001 // RTC match 0 interrupt\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the Hibernate interrupt clear reg.\r
+//\r
+//*****************************************************************************\r
+#define HIB_IC_EXTW 0x00000008 // wake from external pin interrupt\r
+#define HIB_IC_LOWBAT 0x00000004 // low battery interrupt\r
+#define HIB_IC_RTCALT1 0x00000002 // RTC match 1 interrupt\r
+#define HIB_IC_RTCALT0 0x00000001 // RTC match 0 interrupt\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the Hibernate RTC trim register.\r
+//\r
+//*****************************************************************************\r
+#define HIB_RTCT_MASK 0x0000ffff // RTC trim mask\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the Hibernate data register.\r
+//\r
+//*****************************************************************************\r
+#define HIB_DATA_MASK 0xffffffff // NV memory data mask\r
+\r
+#endif // __HW_HIBERNATE_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_i2c.h - Macros used when accessing the I2C master and slave hardware.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_I2C_H__\r
+#define __HW_I2C_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// The following defines the offset between the I2C master and slave registers.\r
+//\r
+//*****************************************************************************\r
+#define I2C_O_SLAVE 0x00000800 // Offset from master to slave\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the offsets of the I2C master registers.\r
+//\r
+//*****************************************************************************\r
+#define I2C_MASTER_O_SA 0x00000000 // Slave address register\r
+#define I2C_MASTER_O_CS 0x00000004 // Control and Status register\r
+#define I2C_MASTER_O_DR 0x00000008 // Data register\r
+#define I2C_MASTER_O_TPR 0x0000000C // Timer period register\r
+#define I2C_MASTER_O_IMR 0x00000010 // Interrupt mask register\r
+#define I2C_MASTER_O_RIS 0x00000014 // Raw interrupt status register\r
+#define I2C_MASTER_O_MIS 0x00000018 // Masked interrupt status reg\r
+#define I2C_MASTER_O_MICR 0x0000001c // Interrupt clear register\r
+#define I2C_MASTER_O_CR 0x00000020 // Configuration register\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the offsets of the I2C slave registers.\r
+//\r
+//*****************************************************************************\r
+#define I2C_SLAVE_O_OAR 0x00000000 // Own address register\r
+#define I2C_SLAVE_O_CSR 0x00000004 // Control/Status register\r
+#define I2C_SLAVE_O_DR 0x00000008 // Data register\r
+#define I2C_SLAVE_O_IM 0x0000000C // Interrupt mask register\r
+#define I2C_SLAVE_O_RIS 0x00000010 // Raw interrupt status register\r
+#define I2C_SLAVE_O_MIS 0x00000014 // Masked interrupt status reg\r
+#define I2C_SLAVE_O_SICR 0x00000018 // Interrupt clear register\r
+\r
+//*****************************************************************************\r
+//\r
+// The followng define the bit fields in the I2C master slave address register.\r
+//\r
+//*****************************************************************************\r
+#define I2C_MASTER_SA_SA_MASK 0x000000FE // Slave address\r
+#define I2C_MASTER_SA_RS 0x00000001 // Receive/send\r
+#define I2C_MASTER_SA_SA_SHIFT 1\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the I2C Master Control and Status\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define I2C_MASTER_CS_ACK 0x00000008 // Acknowlegde\r
+#define I2C_MASTER_CS_STOP 0x00000004 // Stop\r
+#define I2C_MASTER_CS_START 0x00000002 // Start\r
+#define I2C_MASTER_CS_RUN 0x00000001 // Run\r
+#define I2C_MASTER_CS_BUS_BUSY 0x00000040 // Bus busy\r
+#define I2C_MASTER_CS_IDLE 0x00000020 // Idle\r
+#define I2C_MASTER_CS_ARB_LOST 0x00000010 // Lost arbitration\r
+#define I2C_MASTER_CS_DATA_ACK 0x00000008 // Data byte not acknowledged\r
+#define I2C_MASTER_CS_ADDR_ACK 0x00000004 // Address byte not acknowledged\r
+#define I2C_MASTER_CS_ERROR 0x00000002 // Error occurred\r
+#define I2C_MASTER_CS_BUSY 0x00000001 // Controller is TX/RX data\r
+#define I2C_MASTER_CS_ERR_MASK 0x0000001C\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define values used in determining the contents of the I2C\r
+// Master Timer Period register.\r
+//\r
+//*****************************************************************************\r
+#define I2C_MASTER_TPR_SCL_HP 0x00000004 // SCL high period\r
+#define I2C_MASTER_TPR_SCL_LP 0x00000006 // SCL low period\r
+#define I2C_MASTER_TPR_SCL (I2C_MASTER_TPR_SCL_HP + I2C_MASTER_TPR_SCL_LP)\r
+#define I2C_SCL_STANDARD 100000 // SCL standard frequency\r
+#define I2C_SCL_FAST 400000 // SCL fast frequency\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the I2C Master Interrupt Mask\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define I2C_MASTER_IMR_IM 0x00000001 // Master interrupt mask\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the I2C Master Raw Interrupt Status\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define I2C_MASTER_RIS_RIS 0x00000001 // Master raw interrupt status\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the I2C Master Masked Interrupt\r
+// Status register.\r
+//\r
+//*****************************************************************************\r
+#define I2C_MASTER_MIS_MIS 0x00000001 // Master masked interrupt status\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the I2C Master Interrupt Clear\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define I2C_MASTER_MICR_IC 0x00000001 // Master interrupt clear\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the I2C Master Configuration\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define I2C_MASTER_CR_SFE 0x00000020 // Slave function enable\r
+#define I2C_MASTER_CR_MFE 0x00000010 // Master function enable\r
+#define I2C_MASTER_CR_LPBK 0x00000001 // Loopback enable\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the I2C Slave Own Address register.\r
+//\r
+//*****************************************************************************\r
+#define I2C_SLAVE_SOAR_OAR_MASK 0x0000007F // Slave address\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the I2C Slave Control/Status\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define I2C_SLAVE_CSR_DA 0x00000001 // Enable the device\r
+#define I2C_SLAVE_CSR_TREQ 0x00000002 // Transmit request received\r
+#define I2C_SLAVE_CSR_RREQ 0x00000001 // Receive data from I2C master\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the I2C Slave Interrupt Mask\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define I2C_SLAVE_IMR_IM 0x00000001 // Slave interrupt mask\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the I2C Slave Raw Interrupt Status\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define I2C_SLAVE_RIS_RIS 0x00000001 // Slave raw interrupt status\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the I2C Slave Masked Interrupt\r
+// Status register.\r
+//\r
+//*****************************************************************************\r
+#define I2C_SLAVE_MIS_MIS 0x00000001 // Slave masked interrupt status\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the I2C Slave Interrupt Clear\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define I2C_SLAVE_SICR_IC 0x00000001 // Slave interrupt clear\r
+\r
+#endif // __HW_I2C_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_ints.h - Macros that define the interrupt assignment on Stellaris.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_INTS_H__\r
+#define __HW_INTS_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the fault assignments.\r
+//\r
+//*****************************************************************************\r
+#define FAULT_NMI 2 // NMI fault\r
+#define FAULT_HARD 3 // Hard fault\r
+#define FAULT_MPU 4 // MPU fault\r
+#define FAULT_BUS 5 // Bus fault\r
+#define FAULT_USAGE 6 // Usage fault\r
+#define FAULT_SVCALL 11 // SVCall\r
+#define FAULT_DEBUG 12 // Debug monitor\r
+#define FAULT_PENDSV 14 // PendSV\r
+#define FAULT_SYSTICK 15 // System Tick\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the interrupt assignments.\r
+//\r
+//*****************************************************************************\r
+#define INT_GPIOA 16 // GPIO Port A\r
+#define INT_GPIOB 17 // GPIO Port B\r
+#define INT_GPIOC 18 // GPIO Port C\r
+#define INT_GPIOD 19 // GPIO Port D\r
+#define INT_GPIOE 20 // GPIO Port E\r
+#define INT_UART0 21 // UART0 Rx and Tx\r
+#define INT_UART1 22 // UART1 Rx and Tx\r
+#define INT_SSI 23 // SSI Rx and Tx\r
+#define INT_SSI0 23 // SSI0 Rx and Tx\r
+#define INT_I2C 24 // I2C Master and Slave\r
+#define INT_I2C0 24 // I2C0 Master and Slave\r
+#define INT_PWM_FAULT 25 // PWM Fault\r
+#define INT_PWM0 26 // PWM Generator 0\r
+#define INT_PWM1 27 // PWM Generator 1\r
+#define INT_PWM2 28 // PWM Generator 2\r
+#define INT_QEI 29 // Quadrature Encoder\r
+#define INT_QEI0 29 // Quadrature Encoder 0\r
+#define INT_ADC0 30 // ADC Sequence 0\r
+#define INT_ADC1 31 // ADC Sequence 1\r
+#define INT_ADC2 32 // ADC Sequence 2\r
+#define INT_ADC3 33 // ADC Sequence 3\r
+#define INT_WATCHDOG 34 // Watchdog timer\r
+#define INT_TIMER0A 35 // Timer 0 subtimer A\r
+#define INT_TIMER0B 36 // Timer 0 subtimer B\r
+#define INT_TIMER1A 37 // Timer 1 subtimer A\r
+#define INT_TIMER1B 38 // Timer 1 subtimer B\r
+#define INT_TIMER2A 39 // Timer 2 subtimer A\r
+#define INT_TIMER2B 40 // Timer 2 subtimer B\r
+#define INT_COMP0 41 // Analog Comparator 0\r
+#define INT_COMP1 42 // Analog Comparator 1\r
+#define INT_COMP2 43 // Analog Comparator 2\r
+#define INT_SYSCTL 44 // System Control (PLL, OSC, BO)\r
+#define INT_FLASH 45 // FLASH Control\r
+#define INT_GPIOF 46 // GPIO Port F\r
+#define INT_GPIOG 47 // GPIO Port G\r
+#define INT_GPIOH 48 // GPIO Port H\r
+#define INT_UART2 49 // UART2 Rx and Tx\r
+#define INT_SSI1 50 // SSI1 Rx and Tx\r
+#define INT_TIMER3A 51 // Timer 3 subtimer A\r
+#define INT_TIMER3B 52 // Timer 3 subtimer B\r
+#define INT_I2C1 53 // I2C1 Master and Slave\r
+#define INT_QEI1 54 // Quadrature Encoder 1\r
+#define INT_CAN0 55 // CAN0\r
+#define INT_CAN1 56 // CAN1\r
+#define INT_ETH 58 // Ethernet\r
+#define INT_HIBERNATE 59 // Hibernation module\r
+\r
+//*****************************************************************************\r
+//\r
+// The total number of interrupts.\r
+//\r
+//*****************************************************************************\r
+#define NUM_INTERRUPTS 60\r
+\r
+//*****************************************************************************\r
+//\r
+// The total number of priority levels.\r
+//\r
+//*****************************************************************************\r
+#define NUM_PRIORITY 8\r
+#define NUM_PRIORITY_BITS 3\r
+\r
+#endif // __HW_INTS_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_memmap.h - Macros defining the memory map of Stellaris.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_MEMMAP_H__\r
+#define __HW_MEMMAP_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the base address of the memories and peripherals.\r
+//\r
+//*****************************************************************************\r
+#define FLASH_BASE 0x00000000 // FLASH memory\r
+#define SRAM_BASE 0x20000000 // SRAM memory\r
+#define WATCHDOG_BASE 0x40000000 // Watchdog\r
+#define GPIO_PORTA_BASE 0x40004000 // GPIO Port A\r
+#define GPIO_PORTB_BASE 0x40005000 // GPIO Port B\r
+#define GPIO_PORTC_BASE 0x40006000 // GPIO Port C\r
+#define GPIO_PORTD_BASE 0x40007000 // GPIO Port D\r
+#define SSI_BASE 0x40008000 // SSI\r
+#define SSI0_BASE 0x40008000 // SSI0\r
+#define SSI1_BASE 0x40009000 // SSI1\r
+#define UART0_BASE 0x4000C000 // UART0\r
+#define UART1_BASE 0x4000D000 // UART1\r
+#define UART2_BASE 0x4000E000 // UART2\r
+#define I2C_MASTER_BASE 0x40020000 // I2C Master\r
+#define I2C_SLAVE_BASE 0x40020800 // I2C Slave\r
+#define I2C0_MASTER_BASE 0x40020000 // I2C0 Master\r
+#define I2C0_SLAVE_BASE 0x40020800 // I2C0 Slave\r
+#define I2C1_MASTER_BASE 0x40021000 // I2C1 Master\r
+#define I2C1_SLAVE_BASE 0x40021800 // I2C1 Slave\r
+#define GPIO_PORTE_BASE 0x40024000 // GPIO Port E\r
+#define GPIO_PORTF_BASE 0x40025000 // GPIO Port F\r
+#define GPIO_PORTG_BASE 0x40026000 // GPIO Port G\r
+#define GPIO_PORTH_BASE 0x40027000 // GPIO Port H\r
+#define PWM_BASE 0x40028000 // PWM\r
+#define QEI_BASE 0x4002C000 // QEI\r
+#define QEI0_BASE 0x4002C000 // QEI0\r
+#define QEI1_BASE 0x4002D000 // QEI1\r
+#define TIMER0_BASE 0x40030000 // Timer0\r
+#define TIMER1_BASE 0x40031000 // Timer1\r
+#define TIMER2_BASE 0x40032000 // Timer2\r
+#define TIMER3_BASE 0x40033000 // Timer3\r
+#define ADC_BASE 0x40038000 // ADC\r
+#define COMP_BASE 0x4003C000 // Analog comparators\r
+#define CAN0_BASE 0x40040000 // CAN0\r
+#define CAN1_BASE 0x40041000 // CAN1\r
+#define ETH_BASE 0x40048000 // Ethernet\r
+#define FLASH_CTRL_BASE 0x400FD000 // FLASH Controller\r
+#define SYSCTL_BASE 0x400FE000 // System Control\r
+#define ITM_BASE 0xE0000000 // Instrumentation Trace Macrocell\r
+#define DWT_BASE 0xE0001000 // Data Watchpoint and Trace\r
+#define FPB_BASE 0xE0002000 // FLASH Patch and Breakpoint\r
+#define NVIC_BASE 0xE000E000 // Nested Vectored Interrupt Ctrl\r
+#define TPIU_BASE 0xE0040000 // Trace Port Interface Unit\r
+\r
+#endif // __HW_MEMMAP_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_nvic.h - Macros used when accessing the NVIC hardware.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_NVIC_H__\r
+#define __HW_NVIC_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the addresses of the NVIC registers.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_INT_TYPE 0xE000E004 // Interrupt Controller Type Reg.\r
+#define NVIC_ST_CTRL 0xE000E010 // SysTick Control and Status Reg.\r
+#define NVIC_ST_RELOAD 0xE000E014 // SysTick Reload Value Register\r
+#define NVIC_ST_CURRENT 0xE000E018 // SysTick Current Value Register\r
+#define NVIC_ST_CAL 0xE000E01C // SysTick Calibration Value Reg.\r
+#define NVIC_EN0 0xE000E100 // IRQ 0 to 31 Set Enable Register\r
+#define NVIC_EN1 0xE000E104 // IRQ 32 to 63 Set Enable Register\r
+#define NVIC_DIS0 0xE000E180 // IRQ 0 to 31 Clear Enable Reg.\r
+#define NVIC_DIS1 0xE000E184 // IRQ 32 to 63 Clear Enable Reg.\r
+#define NVIC_PEND0 0xE000E200 // IRQ 0 to 31 Set Pending Register\r
+#define NVIC_PEND1 0xE000E204 // IRQ 32 to 63 Set Pending Reg.\r
+#define NVIC_UNPEND0 0xE000E280 // IRQ 0 to 31 Clear Pending Reg.\r
+#define NVIC_UNPEND1 0xE000E284 // IRQ 32 to 63 Clear Pending Reg.\r
+#define NVIC_ACTIVE0 0xE000E300 // IRQ 0 to 31 Active Register\r
+#define NVIC_ACTIVE1 0xE000E304 // IRQ 32 to 63 Active Register\r
+#define NVIC_PRI0 0xE000E400 // IRQ 0 to 3 Priority Register\r
+#define NVIC_PRI1 0xE000E404 // IRQ 4 to 7 Priority Register\r
+#define NVIC_PRI2 0xE000E408 // IRQ 8 to 11 Priority Register\r
+#define NVIC_PRI3 0xE000E40C // IRQ 12 to 15 Priority Register\r
+#define NVIC_PRI4 0xE000E410 // IRQ 16 to 19 Priority Register\r
+#define NVIC_PRI5 0xE000E414 // IRQ 20 to 23 Priority Register\r
+#define NVIC_PRI6 0xE000E418 // IRQ 24 to 27 Priority Register\r
+#define NVIC_PRI7 0xE000E41C // IRQ 28 to 31 Priority Register\r
+#define NVIC_PRI8 0xE000E420 // IRQ 32 to 35 Priority Register\r
+#define NVIC_PRI9 0xE000E424 // IRQ 36 to 39 Priority Register\r
+#define NVIC_PRI10 0xE000E428 // IRQ 40 to 43 Priority Register\r
+#define NVIC_CPUID 0xE000ED00 // CPUID Base Register\r
+#define NVIC_INT_CTRL 0xE000ED04 // Interrupt Control State Register\r
+#define NVIC_VTABLE 0xE000ED08 // Vector Table Offset Register\r
+#define NVIC_APINT 0xE000ED0C // App. Int & Reset Control Reg.\r
+#define NVIC_SYS_CTRL 0xE000ED10 // System Control Register\r
+#define NVIC_CFG_CTRL 0xE000ED14 // Configuration Control Register\r
+#define NVIC_SYS_PRI1 0xE000ED18 // Sys. Handlers 4 to 7 Priority\r
+#define NVIC_SYS_PRI2 0xE000ED1C // Sys. Handlers 8 to 11 Priority\r
+#define NVIC_SYS_PRI3 0xE000ED20 // Sys. Handlers 12 to 15 Priority\r
+#define NVIC_SYS_HND_CTRL 0xE000ED24 // System Handler Control and State\r
+#define NVIC_FAULT_STAT 0xE000ED28 // Configurable Fault Status Reg.\r
+#define NVIC_HFAULT_STAT 0xE000ED2C // Hard Fault Status Register\r
+#define NVIC_DEBUG_STAT 0xE000ED30 // Debug Status Register\r
+#define NVIC_MM_ADDR 0xE000ED34 // Mem Manage Address Register\r
+#define NVIC_FAULT_ADDR 0xE000ED38 // Bus Fault Address Register\r
+#define NVIC_MPU_TYPE 0xE000ED90 // MPU Type Register\r
+#define NVIC_MPU_CTRL 0xE000ED94 // MPU Control Register\r
+#define NVIC_MPU_NUMBER 0xE000ED98 // MPU Region Number Register\r
+#define NVIC_MPU_BASE 0xE000ED9C // MPU Region Base Address Register\r
+#define NVIC_MPU_ATTR 0xE000EDA0 // MPU Region Attribute & Size Reg.\r
+#define NVIC_DBG_CTRL 0xE000EDF0 // Debug Control and Status Reg.\r
+#define NVIC_DBG_XFER 0xE000EDF4 // Debug Core Reg. Transfer Select\r
+#define NVIC_DBG_DATA 0xE000EDF8 // Debug Core Register Data\r
+#define NVIC_DBG_INT 0xE000EDFC // Debug Reset Interrupt Control\r
+#define NVIC_SW_TRIG 0xE000EF00 // Software Trigger Interrupt Reg.\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_INT_TYPE register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_INT_TYPE_LINES_M 0x0000001F // Number of interrupt lines (x32)\r
+#define NVIC_INT_TYPE_LINES_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_ST_CTRL register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_ST_CTRL_COUNT 0x00010000 // Count flag\r
+#define NVIC_ST_CTRL_CLK_SRC 0x00000004 // Clock Source\r
+#define NVIC_ST_CTRL_INTEN 0x00000002 // Interrupt enable\r
+#define NVIC_ST_CTRL_ENABLE 0x00000001 // Counter mode\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_ST_RELOAD register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_ST_RELOAD_M 0x00FFFFFF // Counter load value\r
+#define NVIC_ST_RELOAD_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_ST_CURRENT register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_ST_CURRENT_M 0x00FFFFFF // Counter current value\r
+#define NVIC_ST_CURRENT_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_ST_CAL register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_ST_CAL_NOREF 0x80000000 // No reference clock\r
+#define NVIC_ST_CAL_SKEW 0x40000000 // Clock skew\r
+#define NVIC_ST_CAL_ONEMS_M 0x00FFFFFF // 1ms reference value\r
+#define NVIC_ST_CAL_ONEMS_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_EN0 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_EN0_INT31 0x80000000 // Interrupt 31 enable\r
+#define NVIC_EN0_INT30 0x40000000 // Interrupt 30 enable\r
+#define NVIC_EN0_INT29 0x20000000 // Interrupt 29 enable\r
+#define NVIC_EN0_INT28 0x10000000 // Interrupt 28 enable\r
+#define NVIC_EN0_INT27 0x08000000 // Interrupt 27 enable\r
+#define NVIC_EN0_INT26 0x04000000 // Interrupt 26 enable\r
+#define NVIC_EN0_INT25 0x02000000 // Interrupt 25 enable\r
+#define NVIC_EN0_INT24 0x01000000 // Interrupt 24 enable\r
+#define NVIC_EN0_INT23 0x00800000 // Interrupt 23 enable\r
+#define NVIC_EN0_INT22 0x00400000 // Interrupt 22 enable\r
+#define NVIC_EN0_INT21 0x00200000 // Interrupt 21 enable\r
+#define NVIC_EN0_INT20 0x00100000 // Interrupt 20 enable\r
+#define NVIC_EN0_INT19 0x00080000 // Interrupt 19 enable\r
+#define NVIC_EN0_INT18 0x00040000 // Interrupt 18 enable\r
+#define NVIC_EN0_INT17 0x00020000 // Interrupt 17 enable\r
+#define NVIC_EN0_INT16 0x00010000 // Interrupt 16 enable\r
+#define NVIC_EN0_INT15 0x00008000 // Interrupt 15 enable\r
+#define NVIC_EN0_INT14 0x00004000 // Interrupt 14 enable\r
+#define NVIC_EN0_INT13 0x00002000 // Interrupt 13 enable\r
+#define NVIC_EN0_INT12 0x00001000 // Interrupt 12 enable\r
+#define NVIC_EN0_INT11 0x00000800 // Interrupt 11 enable\r
+#define NVIC_EN0_INT10 0x00000400 // Interrupt 10 enable\r
+#define NVIC_EN0_INT9 0x00000200 // Interrupt 9 enable\r
+#define NVIC_EN0_INT8 0x00000100 // Interrupt 8 enable\r
+#define NVIC_EN0_INT7 0x00000080 // Interrupt 7 enable\r
+#define NVIC_EN0_INT6 0x00000040 // Interrupt 6 enable\r
+#define NVIC_EN0_INT5 0x00000020 // Interrupt 5 enable\r
+#define NVIC_EN0_INT4 0x00000010 // Interrupt 4 enable\r
+#define NVIC_EN0_INT3 0x00000008 // Interrupt 3 enable\r
+#define NVIC_EN0_INT2 0x00000004 // Interrupt 2 enable\r
+#define NVIC_EN0_INT1 0x00000002 // Interrupt 1 enable\r
+#define NVIC_EN0_INT0 0x00000001 // Interrupt 0 enable\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_EN1 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_EN1_INT59 0x08000000 // Interrupt 59 enable\r
+#define NVIC_EN1_INT58 0x04000000 // Interrupt 58 enable\r
+#define NVIC_EN1_INT57 0x02000000 // Interrupt 57 enable\r
+#define NVIC_EN1_INT56 0x01000000 // Interrupt 56 enable\r
+#define NVIC_EN1_INT55 0x00800000 // Interrupt 55 enable\r
+#define NVIC_EN1_INT54 0x00400000 // Interrupt 54 enable\r
+#define NVIC_EN1_INT53 0x00200000 // Interrupt 53 enable\r
+#define NVIC_EN1_INT52 0x00100000 // Interrupt 52 enable\r
+#define NVIC_EN1_INT51 0x00080000 // Interrupt 51 enable\r
+#define NVIC_EN1_INT50 0x00040000 // Interrupt 50 enable\r
+#define NVIC_EN1_INT49 0x00020000 // Interrupt 49 enable\r
+#define NVIC_EN1_INT48 0x00010000 // Interrupt 48 enable\r
+#define NVIC_EN1_INT47 0x00008000 // Interrupt 47 enable\r
+#define NVIC_EN1_INT46 0x00004000 // Interrupt 46 enable\r
+#define NVIC_EN1_INT45 0x00002000 // Interrupt 45 enable\r
+#define NVIC_EN1_INT44 0x00001000 // Interrupt 44 enable\r
+#define NVIC_EN1_INT43 0x00000800 // Interrupt 43 enable\r
+#define NVIC_EN1_INT42 0x00000400 // Interrupt 42 enable\r
+#define NVIC_EN1_INT41 0x00000200 // Interrupt 41 enable\r
+#define NVIC_EN1_INT40 0x00000100 // Interrupt 40 enable\r
+#define NVIC_EN1_INT39 0x00000080 // Interrupt 39 enable\r
+#define NVIC_EN1_INT38 0x00000040 // Interrupt 38 enable\r
+#define NVIC_EN1_INT37 0x00000020 // Interrupt 37 enable\r
+#define NVIC_EN1_INT36 0x00000010 // Interrupt 36 enable\r
+#define NVIC_EN1_INT35 0x00000008 // Interrupt 35 enable\r
+#define NVIC_EN1_INT34 0x00000004 // Interrupt 34 enable\r
+#define NVIC_EN1_INT33 0x00000002 // Interrupt 33 enable\r
+#define NVIC_EN1_INT32 0x00000001 // Interrupt 32 enable\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_DIS0 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_DIS0_INT31 0x80000000 // Interrupt 31 disable\r
+#define NVIC_DIS0_INT30 0x40000000 // Interrupt 30 disable\r
+#define NVIC_DIS0_INT29 0x20000000 // Interrupt 29 disable\r
+#define NVIC_DIS0_INT28 0x10000000 // Interrupt 28 disable\r
+#define NVIC_DIS0_INT27 0x08000000 // Interrupt 27 disable\r
+#define NVIC_DIS0_INT26 0x04000000 // Interrupt 26 disable\r
+#define NVIC_DIS0_INT25 0x02000000 // Interrupt 25 disable\r
+#define NVIC_DIS0_INT24 0x01000000 // Interrupt 24 disable\r
+#define NVIC_DIS0_INT23 0x00800000 // Interrupt 23 disable\r
+#define NVIC_DIS0_INT22 0x00400000 // Interrupt 22 disable\r
+#define NVIC_DIS0_INT21 0x00200000 // Interrupt 21 disable\r
+#define NVIC_DIS0_INT20 0x00100000 // Interrupt 20 disable\r
+#define NVIC_DIS0_INT19 0x00080000 // Interrupt 19 disable\r
+#define NVIC_DIS0_INT18 0x00040000 // Interrupt 18 disable\r
+#define NVIC_DIS0_INT17 0x00020000 // Interrupt 17 disable\r
+#define NVIC_DIS0_INT16 0x00010000 // Interrupt 16 disable\r
+#define NVIC_DIS0_INT15 0x00008000 // Interrupt 15 disable\r
+#define NVIC_DIS0_INT14 0x00004000 // Interrupt 14 disable\r
+#define NVIC_DIS0_INT13 0x00002000 // Interrupt 13 disable\r
+#define NVIC_DIS0_INT12 0x00001000 // Interrupt 12 disable\r
+#define NVIC_DIS0_INT11 0x00000800 // Interrupt 11 disable\r
+#define NVIC_DIS0_INT10 0x00000400 // Interrupt 10 disable\r
+#define NVIC_DIS0_INT9 0x00000200 // Interrupt 9 disable\r
+#define NVIC_DIS0_INT8 0x00000100 // Interrupt 8 disable\r
+#define NVIC_DIS0_INT7 0x00000080 // Interrupt 7 disable\r
+#define NVIC_DIS0_INT6 0x00000040 // Interrupt 6 disable\r
+#define NVIC_DIS0_INT5 0x00000020 // Interrupt 5 disable\r
+#define NVIC_DIS0_INT4 0x00000010 // Interrupt 4 disable\r
+#define NVIC_DIS0_INT3 0x00000008 // Interrupt 3 disable\r
+#define NVIC_DIS0_INT2 0x00000004 // Interrupt 2 disable\r
+#define NVIC_DIS0_INT1 0x00000002 // Interrupt 1 disable\r
+#define NVIC_DIS0_INT0 0x00000001 // Interrupt 0 disable\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_DIS1 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_DIS1_INT59 0x08000000 // Interrupt 59 disable\r
+#define NVIC_DIS1_INT58 0x04000000 // Interrupt 58 disable\r
+#define NVIC_DIS1_INT57 0x02000000 // Interrupt 57 disable\r
+#define NVIC_DIS1_INT56 0x01000000 // Interrupt 56 disable\r
+#define NVIC_DIS1_INT55 0x00800000 // Interrupt 55 disable\r
+#define NVIC_DIS1_INT54 0x00400000 // Interrupt 54 disable\r
+#define NVIC_DIS1_INT53 0x00200000 // Interrupt 53 disable\r
+#define NVIC_DIS1_INT52 0x00100000 // Interrupt 52 disable\r
+#define NVIC_DIS1_INT51 0x00080000 // Interrupt 51 disable\r
+#define NVIC_DIS1_INT50 0x00040000 // Interrupt 50 disable\r
+#define NVIC_DIS1_INT49 0x00020000 // Interrupt 49 disable\r
+#define NVIC_DIS1_INT48 0x00010000 // Interrupt 48 disable\r
+#define NVIC_DIS1_INT47 0x00008000 // Interrupt 47 disable\r
+#define NVIC_DIS1_INT46 0x00004000 // Interrupt 46 disable\r
+#define NVIC_DIS1_INT45 0x00002000 // Interrupt 45 disable\r
+#define NVIC_DIS1_INT44 0x00001000 // Interrupt 44 disable\r
+#define NVIC_DIS1_INT43 0x00000800 // Interrupt 43 disable\r
+#define NVIC_DIS1_INT42 0x00000400 // Interrupt 42 disable\r
+#define NVIC_DIS1_INT41 0x00000200 // Interrupt 41 disable\r
+#define NVIC_DIS1_INT40 0x00000100 // Interrupt 40 disable\r
+#define NVIC_DIS1_INT39 0x00000080 // Interrupt 39 disable\r
+#define NVIC_DIS1_INT38 0x00000040 // Interrupt 38 disable\r
+#define NVIC_DIS1_INT37 0x00000020 // Interrupt 37 disable\r
+#define NVIC_DIS1_INT36 0x00000010 // Interrupt 36 disable\r
+#define NVIC_DIS1_INT35 0x00000008 // Interrupt 35 disable\r
+#define NVIC_DIS1_INT34 0x00000004 // Interrupt 34 disable\r
+#define NVIC_DIS1_INT33 0x00000002 // Interrupt 33 disable\r
+#define NVIC_DIS1_INT32 0x00000001 // Interrupt 32 disable\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_PEND0 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_PEND0_INT31 0x80000000 // Interrupt 31 pend\r
+#define NVIC_PEND0_INT30 0x40000000 // Interrupt 30 pend\r
+#define NVIC_PEND0_INT29 0x20000000 // Interrupt 29 pend\r
+#define NVIC_PEND0_INT28 0x10000000 // Interrupt 28 pend\r
+#define NVIC_PEND0_INT27 0x08000000 // Interrupt 27 pend\r
+#define NVIC_PEND0_INT26 0x04000000 // Interrupt 26 pend\r
+#define NVIC_PEND0_INT25 0x02000000 // Interrupt 25 pend\r
+#define NVIC_PEND0_INT24 0x01000000 // Interrupt 24 pend\r
+#define NVIC_PEND0_INT23 0x00800000 // Interrupt 23 pend\r
+#define NVIC_PEND0_INT22 0x00400000 // Interrupt 22 pend\r
+#define NVIC_PEND0_INT21 0x00200000 // Interrupt 21 pend\r
+#define NVIC_PEND0_INT20 0x00100000 // Interrupt 20 pend\r
+#define NVIC_PEND0_INT19 0x00080000 // Interrupt 19 pend\r
+#define NVIC_PEND0_INT18 0x00040000 // Interrupt 18 pend\r
+#define NVIC_PEND0_INT17 0x00020000 // Interrupt 17 pend\r
+#define NVIC_PEND0_INT16 0x00010000 // Interrupt 16 pend\r
+#define NVIC_PEND0_INT15 0x00008000 // Interrupt 15 pend\r
+#define NVIC_PEND0_INT14 0x00004000 // Interrupt 14 pend\r
+#define NVIC_PEND0_INT13 0x00002000 // Interrupt 13 pend\r
+#define NVIC_PEND0_INT12 0x00001000 // Interrupt 12 pend\r
+#define NVIC_PEND0_INT11 0x00000800 // Interrupt 11 pend\r
+#define NVIC_PEND0_INT10 0x00000400 // Interrupt 10 pend\r
+#define NVIC_PEND0_INT9 0x00000200 // Interrupt 9 pend\r
+#define NVIC_PEND0_INT8 0x00000100 // Interrupt 8 pend\r
+#define NVIC_PEND0_INT7 0x00000080 // Interrupt 7 pend\r
+#define NVIC_PEND0_INT6 0x00000040 // Interrupt 6 pend\r
+#define NVIC_PEND0_INT5 0x00000020 // Interrupt 5 pend\r
+#define NVIC_PEND0_INT4 0x00000010 // Interrupt 4 pend\r
+#define NVIC_PEND0_INT3 0x00000008 // Interrupt 3 pend\r
+#define NVIC_PEND0_INT2 0x00000004 // Interrupt 2 pend\r
+#define NVIC_PEND0_INT1 0x00000002 // Interrupt 1 pend\r
+#define NVIC_PEND0_INT0 0x00000001 // Interrupt 0 pend\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_PEND1 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_PEND1_INT59 0x08000000 // Interrupt 59 pend\r
+#define NVIC_PEND1_INT58 0x04000000 // Interrupt 58 pend\r
+#define NVIC_PEND1_INT57 0x02000000 // Interrupt 57 pend\r
+#define NVIC_PEND1_INT56 0x01000000 // Interrupt 56 pend\r
+#define NVIC_PEND1_INT55 0x00800000 // Interrupt 55 pend\r
+#define NVIC_PEND1_INT54 0x00400000 // Interrupt 54 pend\r
+#define NVIC_PEND1_INT53 0x00200000 // Interrupt 53 pend\r
+#define NVIC_PEND1_INT52 0x00100000 // Interrupt 52 pend\r
+#define NVIC_PEND1_INT51 0x00080000 // Interrupt 51 pend\r
+#define NVIC_PEND1_INT50 0x00040000 // Interrupt 50 pend\r
+#define NVIC_PEND1_INT49 0x00020000 // Interrupt 49 pend\r
+#define NVIC_PEND1_INT48 0x00010000 // Interrupt 48 pend\r
+#define NVIC_PEND1_INT47 0x00008000 // Interrupt 47 pend\r
+#define NVIC_PEND1_INT46 0x00004000 // Interrupt 46 pend\r
+#define NVIC_PEND1_INT45 0x00002000 // Interrupt 45 pend\r
+#define NVIC_PEND1_INT44 0x00001000 // Interrupt 44 pend\r
+#define NVIC_PEND1_INT43 0x00000800 // Interrupt 43 pend\r
+#define NVIC_PEND1_INT42 0x00000400 // Interrupt 42 pend\r
+#define NVIC_PEND1_INT41 0x00000200 // Interrupt 41 pend\r
+#define NVIC_PEND1_INT40 0x00000100 // Interrupt 40 pend\r
+#define NVIC_PEND1_INT39 0x00000080 // Interrupt 39 pend\r
+#define NVIC_PEND1_INT38 0x00000040 // Interrupt 38 pend\r
+#define NVIC_PEND1_INT37 0x00000020 // Interrupt 37 pend\r
+#define NVIC_PEND1_INT36 0x00000010 // Interrupt 36 pend\r
+#define NVIC_PEND1_INT35 0x00000008 // Interrupt 35 pend\r
+#define NVIC_PEND1_INT34 0x00000004 // Interrupt 34 pend\r
+#define NVIC_PEND1_INT33 0x00000002 // Interrupt 33 pend\r
+#define NVIC_PEND1_INT32 0x00000001 // Interrupt 32 pend\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_UNPEND0 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_UNPEND0_INT31 0x80000000 // Interrupt 31 unpend\r
+#define NVIC_UNPEND0_INT30 0x40000000 // Interrupt 30 unpend\r
+#define NVIC_UNPEND0_INT29 0x20000000 // Interrupt 29 unpend\r
+#define NVIC_UNPEND0_INT28 0x10000000 // Interrupt 28 unpend\r
+#define NVIC_UNPEND0_INT27 0x08000000 // Interrupt 27 unpend\r
+#define NVIC_UNPEND0_INT26 0x04000000 // Interrupt 26 unpend\r
+#define NVIC_UNPEND0_INT25 0x02000000 // Interrupt 25 unpend\r
+#define NVIC_UNPEND0_INT24 0x01000000 // Interrupt 24 unpend\r
+#define NVIC_UNPEND0_INT23 0x00800000 // Interrupt 23 unpend\r
+#define NVIC_UNPEND0_INT22 0x00400000 // Interrupt 22 unpend\r
+#define NVIC_UNPEND0_INT21 0x00200000 // Interrupt 21 unpend\r
+#define NVIC_UNPEND0_INT20 0x00100000 // Interrupt 20 unpend\r
+#define NVIC_UNPEND0_INT19 0x00080000 // Interrupt 19 unpend\r
+#define NVIC_UNPEND0_INT18 0x00040000 // Interrupt 18 unpend\r
+#define NVIC_UNPEND0_INT17 0x00020000 // Interrupt 17 unpend\r
+#define NVIC_UNPEND0_INT16 0x00010000 // Interrupt 16 unpend\r
+#define NVIC_UNPEND0_INT15 0x00008000 // Interrupt 15 unpend\r
+#define NVIC_UNPEND0_INT14 0x00004000 // Interrupt 14 unpend\r
+#define NVIC_UNPEND0_INT13 0x00002000 // Interrupt 13 unpend\r
+#define NVIC_UNPEND0_INT12 0x00001000 // Interrupt 12 unpend\r
+#define NVIC_UNPEND0_INT11 0x00000800 // Interrupt 11 unpend\r
+#define NVIC_UNPEND0_INT10 0x00000400 // Interrupt 10 unpend\r
+#define NVIC_UNPEND0_INT9 0x00000200 // Interrupt 9 unpend\r
+#define NVIC_UNPEND0_INT8 0x00000100 // Interrupt 8 unpend\r
+#define NVIC_UNPEND0_INT7 0x00000080 // Interrupt 7 unpend\r
+#define NVIC_UNPEND0_INT6 0x00000040 // Interrupt 6 unpend\r
+#define NVIC_UNPEND0_INT5 0x00000020 // Interrupt 5 unpend\r
+#define NVIC_UNPEND0_INT4 0x00000010 // Interrupt 4 unpend\r
+#define NVIC_UNPEND0_INT3 0x00000008 // Interrupt 3 unpend\r
+#define NVIC_UNPEND0_INT2 0x00000004 // Interrupt 2 unpend\r
+#define NVIC_UNPEND0_INT1 0x00000002 // Interrupt 1 unpend\r
+#define NVIC_UNPEND0_INT0 0x00000001 // Interrupt 0 unpend\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_UNPEND1 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_UNPEND1_INT59 0x08000000 // Interrupt 59 unpend\r
+#define NVIC_UNPEND1_INT58 0x04000000 // Interrupt 58 unpend\r
+#define NVIC_UNPEND1_INT57 0x02000000 // Interrupt 57 unpend\r
+#define NVIC_UNPEND1_INT56 0x01000000 // Interrupt 56 unpend\r
+#define NVIC_UNPEND1_INT55 0x00800000 // Interrupt 55 unpend\r
+#define NVIC_UNPEND1_INT54 0x00400000 // Interrupt 54 unpend\r
+#define NVIC_UNPEND1_INT53 0x00200000 // Interrupt 53 unpend\r
+#define NVIC_UNPEND1_INT52 0x00100000 // Interrupt 52 unpend\r
+#define NVIC_UNPEND1_INT51 0x00080000 // Interrupt 51 unpend\r
+#define NVIC_UNPEND1_INT50 0x00040000 // Interrupt 50 unpend\r
+#define NVIC_UNPEND1_INT49 0x00020000 // Interrupt 49 unpend\r
+#define NVIC_UNPEND1_INT48 0x00010000 // Interrupt 48 unpend\r
+#define NVIC_UNPEND1_INT47 0x00008000 // Interrupt 47 unpend\r
+#define NVIC_UNPEND1_INT46 0x00004000 // Interrupt 46 unpend\r
+#define NVIC_UNPEND1_INT45 0x00002000 // Interrupt 45 unpend\r
+#define NVIC_UNPEND1_INT44 0x00001000 // Interrupt 44 unpend\r
+#define NVIC_UNPEND1_INT43 0x00000800 // Interrupt 43 unpend\r
+#define NVIC_UNPEND1_INT42 0x00000400 // Interrupt 42 unpend\r
+#define NVIC_UNPEND1_INT41 0x00000200 // Interrupt 41 unpend\r
+#define NVIC_UNPEND1_INT40 0x00000100 // Interrupt 40 unpend\r
+#define NVIC_UNPEND1_INT39 0x00000080 // Interrupt 39 unpend\r
+#define NVIC_UNPEND1_INT38 0x00000040 // Interrupt 38 unpend\r
+#define NVIC_UNPEND1_INT37 0x00000020 // Interrupt 37 unpend\r
+#define NVIC_UNPEND1_INT36 0x00000010 // Interrupt 36 unpend\r
+#define NVIC_UNPEND1_INT35 0x00000008 // Interrupt 35 unpend\r
+#define NVIC_UNPEND1_INT34 0x00000004 // Interrupt 34 unpend\r
+#define NVIC_UNPEND1_INT33 0x00000002 // Interrupt 33 unpend\r
+#define NVIC_UNPEND1_INT32 0x00000001 // Interrupt 32 unpend\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_ACTIVE0 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_ACTIVE0_INT31 0x80000000 // Interrupt 31 active\r
+#define NVIC_ACTIVE0_INT30 0x40000000 // Interrupt 30 active\r
+#define NVIC_ACTIVE0_INT29 0x20000000 // Interrupt 29 active\r
+#define NVIC_ACTIVE0_INT28 0x10000000 // Interrupt 28 active\r
+#define NVIC_ACTIVE0_INT27 0x08000000 // Interrupt 27 active\r
+#define NVIC_ACTIVE0_INT26 0x04000000 // Interrupt 26 active\r
+#define NVIC_ACTIVE0_INT25 0x02000000 // Interrupt 25 active\r
+#define NVIC_ACTIVE0_INT24 0x01000000 // Interrupt 24 active\r
+#define NVIC_ACTIVE0_INT23 0x00800000 // Interrupt 23 active\r
+#define NVIC_ACTIVE0_INT22 0x00400000 // Interrupt 22 active\r
+#define NVIC_ACTIVE0_INT21 0x00200000 // Interrupt 21 active\r
+#define NVIC_ACTIVE0_INT20 0x00100000 // Interrupt 20 active\r
+#define NVIC_ACTIVE0_INT19 0x00080000 // Interrupt 19 active\r
+#define NVIC_ACTIVE0_INT18 0x00040000 // Interrupt 18 active\r
+#define NVIC_ACTIVE0_INT17 0x00020000 // Interrupt 17 active\r
+#define NVIC_ACTIVE0_INT16 0x00010000 // Interrupt 16 active\r
+#define NVIC_ACTIVE0_INT15 0x00008000 // Interrupt 15 active\r
+#define NVIC_ACTIVE0_INT14 0x00004000 // Interrupt 14 active\r
+#define NVIC_ACTIVE0_INT13 0x00002000 // Interrupt 13 active\r
+#define NVIC_ACTIVE0_INT12 0x00001000 // Interrupt 12 active\r
+#define NVIC_ACTIVE0_INT11 0x00000800 // Interrupt 11 active\r
+#define NVIC_ACTIVE0_INT10 0x00000400 // Interrupt 10 active\r
+#define NVIC_ACTIVE0_INT9 0x00000200 // Interrupt 9 active\r
+#define NVIC_ACTIVE0_INT8 0x00000100 // Interrupt 8 active\r
+#define NVIC_ACTIVE0_INT7 0x00000080 // Interrupt 7 active\r
+#define NVIC_ACTIVE0_INT6 0x00000040 // Interrupt 6 active\r
+#define NVIC_ACTIVE0_INT5 0x00000020 // Interrupt 5 active\r
+#define NVIC_ACTIVE0_INT4 0x00000010 // Interrupt 4 active\r
+#define NVIC_ACTIVE0_INT3 0x00000008 // Interrupt 3 active\r
+#define NVIC_ACTIVE0_INT2 0x00000004 // Interrupt 2 active\r
+#define NVIC_ACTIVE0_INT1 0x00000002 // Interrupt 1 active\r
+#define NVIC_ACTIVE0_INT0 0x00000001 // Interrupt 0 active\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_ACTIVE1 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_ACTIVE1_INT59 0x08000000 // Interrupt 59 active\r
+#define NVIC_ACTIVE1_INT58 0x04000000 // Interrupt 58 active\r
+#define NVIC_ACTIVE1_INT57 0x02000000 // Interrupt 57 active\r
+#define NVIC_ACTIVE1_INT56 0x01000000 // Interrupt 56 active\r
+#define NVIC_ACTIVE1_INT55 0x00800000 // Interrupt 55 active\r
+#define NVIC_ACTIVE1_INT54 0x00400000 // Interrupt 54 active\r
+#define NVIC_ACTIVE1_INT53 0x00200000 // Interrupt 53 active\r
+#define NVIC_ACTIVE1_INT52 0x00100000 // Interrupt 52 active\r
+#define NVIC_ACTIVE1_INT51 0x00080000 // Interrupt 51 active\r
+#define NVIC_ACTIVE1_INT50 0x00040000 // Interrupt 50 active\r
+#define NVIC_ACTIVE1_INT49 0x00020000 // Interrupt 49 active\r
+#define NVIC_ACTIVE1_INT48 0x00010000 // Interrupt 48 active\r
+#define NVIC_ACTIVE1_INT47 0x00008000 // Interrupt 47 active\r
+#define NVIC_ACTIVE1_INT46 0x00004000 // Interrupt 46 active\r
+#define NVIC_ACTIVE1_INT45 0x00002000 // Interrupt 45 active\r
+#define NVIC_ACTIVE1_INT44 0x00001000 // Interrupt 44 active\r
+#define NVIC_ACTIVE1_INT43 0x00000800 // Interrupt 43 active\r
+#define NVIC_ACTIVE1_INT42 0x00000400 // Interrupt 42 active\r
+#define NVIC_ACTIVE1_INT41 0x00000200 // Interrupt 41 active\r
+#define NVIC_ACTIVE1_INT40 0x00000100 // Interrupt 40 active\r
+#define NVIC_ACTIVE1_INT39 0x00000080 // Interrupt 39 active\r
+#define NVIC_ACTIVE1_INT38 0x00000040 // Interrupt 38 active\r
+#define NVIC_ACTIVE1_INT37 0x00000020 // Interrupt 37 active\r
+#define NVIC_ACTIVE1_INT36 0x00000010 // Interrupt 36 active\r
+#define NVIC_ACTIVE1_INT35 0x00000008 // Interrupt 35 active\r
+#define NVIC_ACTIVE1_INT34 0x00000004 // Interrupt 34 active\r
+#define NVIC_ACTIVE1_INT33 0x00000002 // Interrupt 33 active\r
+#define NVIC_ACTIVE1_INT32 0x00000001 // Interrupt 32 active\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_PRI0 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_PRI0_INT3_M 0xFF000000 // Interrupt 3 priority mask\r
+#define NVIC_PRI0_INT2_M 0x00FF0000 // Interrupt 2 priority mask\r
+#define NVIC_PRI0_INT1_M 0x0000FF00 // Interrupt 1 priority mask\r
+#define NVIC_PRI0_INT0_M 0x000000FF // Interrupt 0 priority mask\r
+#define NVIC_PRI0_INT3_S 24\r
+#define NVIC_PRI0_INT2_S 16\r
+#define NVIC_PRI0_INT1_S 8\r
+#define NVIC_PRI0_INT0_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_PRI1 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_PRI1_INT7_M 0xFF000000 // Interrupt 7 priority mask\r
+#define NVIC_PRI1_INT6_M 0x00FF0000 // Interrupt 6 priority mask\r
+#define NVIC_PRI1_INT5_M 0x0000FF00 // Interrupt 5 priority mask\r
+#define NVIC_PRI1_INT4_M 0x000000FF // Interrupt 4 priority mask\r
+#define NVIC_PRI1_INT7_S 24\r
+#define NVIC_PRI1_INT6_S 16\r
+#define NVIC_PRI1_INT5_S 8\r
+#define NVIC_PRI1_INT4_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_PRI2 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_PRI2_INT11_M 0xFF000000 // Interrupt 11 priority mask\r
+#define NVIC_PRI2_INT10_M 0x00FF0000 // Interrupt 10 priority mask\r
+#define NVIC_PRI2_INT9_M 0x0000FF00 // Interrupt 9 priority mask\r
+#define NVIC_PRI2_INT8_M 0x000000FF // Interrupt 8 priority mask\r
+#define NVIC_PRI2_INT11_S 24\r
+#define NVIC_PRI2_INT10_S 16\r
+#define NVIC_PRI2_INT9_S 8\r
+#define NVIC_PRI2_INT8_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_PRI3 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_PRI3_INT15_M 0xFF000000 // Interrupt 15 priority mask\r
+#define NVIC_PRI3_INT14_M 0x00FF0000 // Interrupt 14 priority mask\r
+#define NVIC_PRI3_INT13_M 0x0000FF00 // Interrupt 13 priority mask\r
+#define NVIC_PRI3_INT12_M 0x000000FF // Interrupt 12 priority mask\r
+#define NVIC_PRI3_INT15_S 24\r
+#define NVIC_PRI3_INT14_S 16\r
+#define NVIC_PRI3_INT13_S 8\r
+#define NVIC_PRI3_INT12_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_PRI4 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_PRI4_INT19_M 0xFF000000 // Interrupt 19 priority mask\r
+#define NVIC_PRI4_INT18_M 0x00FF0000 // Interrupt 18 priority mask\r
+#define NVIC_PRI4_INT17_M 0x0000FF00 // Interrupt 17 priority mask\r
+#define NVIC_PRI4_INT16_M 0x000000FF // Interrupt 16 priority mask\r
+#define NVIC_PRI4_INT19_S 24\r
+#define NVIC_PRI4_INT18_S 16\r
+#define NVIC_PRI4_INT17_S 8\r
+#define NVIC_PRI4_INT16_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_PRI5 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_PRI5_INT23_M 0xFF000000 // Interrupt 23 priority mask\r
+#define NVIC_PRI5_INT22_M 0x00FF0000 // Interrupt 22 priority mask\r
+#define NVIC_PRI5_INT21_M 0x0000FF00 // Interrupt 21 priority mask\r
+#define NVIC_PRI5_INT20_M 0x000000FF // Interrupt 20 priority mask\r
+#define NVIC_PRI5_INT23_S 24\r
+#define NVIC_PRI5_INT22_S 16\r
+#define NVIC_PRI5_INT21_S 8\r
+#define NVIC_PRI5_INT20_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_PRI6 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_PRI6_INT27_M 0xFF000000 // Interrupt 27 priority mask\r
+#define NVIC_PRI6_INT26_M 0x00FF0000 // Interrupt 26 priority mask\r
+#define NVIC_PRI6_INT25_M 0x0000FF00 // Interrupt 25 priority mask\r
+#define NVIC_PRI6_INT24_M 0x000000FF // Interrupt 24 priority mask\r
+#define NVIC_PRI6_INT27_S 24\r
+#define NVIC_PRI6_INT26_S 16\r
+#define NVIC_PRI6_INT25_S 8\r
+#define NVIC_PRI6_INT24_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_PRI7 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_PRI7_INT31_M 0xFF000000 // Interrupt 31 priority mask\r
+#define NVIC_PRI7_INT30_M 0x00FF0000 // Interrupt 30 priority mask\r
+#define NVIC_PRI7_INT29_M 0x0000FF00 // Interrupt 29 priority mask\r
+#define NVIC_PRI7_INT28_M 0x000000FF // Interrupt 28 priority mask\r
+#define NVIC_PRI7_INT31_S 24\r
+#define NVIC_PRI7_INT30_S 16\r
+#define NVIC_PRI7_INT29_S 8\r
+#define NVIC_PRI7_INT28_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_PRI8 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_PRI8_INT35_M 0xFF000000 // Interrupt 35 priority mask\r
+#define NVIC_PRI8_INT34_M 0x00FF0000 // Interrupt 34 priority mask\r
+#define NVIC_PRI8_INT33_M 0x0000FF00 // Interrupt 33 priority mask\r
+#define NVIC_PRI8_INT32_M 0x000000FF // Interrupt 32 priority mask\r
+#define NVIC_PRI8_INT35_S 24\r
+#define NVIC_PRI8_INT34_S 16\r
+#define NVIC_PRI8_INT33_S 8\r
+#define NVIC_PRI8_INT32_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_PRI9 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_PRI9_INT39_M 0xFF000000 // Interrupt 39 priority mask\r
+#define NVIC_PRI9_INT38_M 0x00FF0000 // Interrupt 38 priority mask\r
+#define NVIC_PRI9_INT37_M 0x0000FF00 // Interrupt 37 priority mask\r
+#define NVIC_PRI9_INT36_M 0x000000FF // Interrupt 36 priority mask\r
+#define NVIC_PRI9_INT39_S 24\r
+#define NVIC_PRI9_INT38_S 16\r
+#define NVIC_PRI9_INT37_S 8\r
+#define NVIC_PRI9_INT36_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_PRI10 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_PRI10_INT43_M 0xFF000000 // Interrupt 43 priority mask\r
+#define NVIC_PRI10_INT42_M 0x00FF0000 // Interrupt 42 priority mask\r
+#define NVIC_PRI10_INT41_M 0x0000FF00 // Interrupt 41 priority mask\r
+#define NVIC_PRI10_INT40_M 0x000000FF // Interrupt 40 priority mask\r
+#define NVIC_PRI10_INT43_S 24\r
+#define NVIC_PRI10_INT42_S 16\r
+#define NVIC_PRI10_INT41_S 8\r
+#define NVIC_PRI10_INT40_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_CPUID register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_CPUID_IMP_M 0xFF000000 // Implementer\r
+#define NVIC_CPUID_VAR_M 0x00F00000 // Variant\r
+#define NVIC_CPUID_PARTNO_M 0x0000FFF0 // Processor part number\r
+#define NVIC_CPUID_REV_M 0x0000000F // Revision\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_INT_CTRL register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_INT_CTRL_NMI_SET 0x80000000 // Pend a NMI\r
+#define NVIC_INT_CTRL_PEND_SV 0x10000000 // Pend a PendSV\r
+#define NVIC_INT_CTRL_UNPEND_SV 0x08000000 // Unpend a PendSV\r
+#define NVIC_INT_CTRL_ISR_PRE 0x00800000 // Debug interrupt handling\r
+#define NVIC_INT_CTRL_ISR_PEND 0x00400000 // Debug interrupt pending\r
+#define NVIC_INT_CTRL_VEC_PEN_M 0x003FF000 // Highest pending exception\r
+#define NVIC_INT_CTRL_RET_BASE 0x00000800 // Return to base\r
+#define NVIC_INT_CTRL_VEC_ACT_M 0x000003FF // Current active exception\r
+#define NVIC_INT_CTRL_VEC_PEN_S 12\r
+#define NVIC_INT_CTRL_VEC_ACT_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_VTABLE register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_VTABLE_BASE 0x20000000 // Vector table base\r
+#define NVIC_VTABLE_OFFSET_M 0x1FFFFF00 // Vector table offset\r
+#define NVIC_VTABLE_OFFSET_S 8\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_APINT register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_APINT_VECTKEY_M 0xFFFF0000 // Vector key mask\r
+#define NVIC_APINT_VECTKEY 0x05FA0000 // Vector key\r
+#define NVIC_APINT_ENDIANESS 0x00008000 // Data endianess\r
+#define NVIC_APINT_PRIGROUP_M 0x00000700 // Priority group\r
+#define NVIC_APINT_PRIGROUP_7_1 0x00000000 // Priority group 7.1 split\r
+#define NVIC_APINT_PRIGROUP_6_2 0x00000100 // Priority group 6.2 split\r
+#define NVIC_APINT_PRIGROUP_5_3 0x00000200 // Priority group 5.3 split\r
+#define NVIC_APINT_PRIGROUP_4_4 0x00000300 // Priority group 4.4 split\r
+#define NVIC_APINT_PRIGROUP_3_5 0x00000400 // Priority group 3.5 split\r
+#define NVIC_APINT_PRIGROUP_2_6 0x00000500 // Priority group 2.6 split\r
+#define NVIC_APINT_PRIGROUP_1_7 0x00000600 // Priority group 1.7 split\r
+#define NVIC_APINT_PRIGROUP_0_8 0x00000700 // Priority group 0.8 split\r
+#define NVIC_APINT_SYSRESETREQ 0x00000004 // System reset request\r
+#define NVIC_APINT_VECT_CLR_ACT 0x00000002 // Clear active NMI/fault info\r
+#define NVIC_APINT_VECT_RESET 0x00000001 // System reset\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_SYS_CTRL register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_SYS_CTRL_SEVONPEND 0x00000010 // Wakeup on pend\r
+#define NVIC_SYS_CTRL_SLEEPDEEP 0x00000004 // Deep sleep enable\r
+#define NVIC_SYS_CTRL_SLEEPEXIT 0x00000002 // Sleep on ISR exit\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_CFG_CTRL register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_CFG_CTRL_BFHFNMIGN 0x00000100 // Ignore bus fault in NMI/fault\r
+#define NVIC_CFG_CTRL_DIV0 0x00000010 // Trap on divide by 0\r
+#define NVIC_CFG_CTRL_UNALIGNED 0x00000008 // Trap on unaligned access\r
+#define NVIC_CFG_CTRL_DEEP_PEND 0x00000004 // Allow deep interrupt trigger\r
+#define NVIC_CFG_CTRL_MAIN_PEND 0x00000002 // Allow main interrupt trigger\r
+#define NVIC_CFG_CTRL_BASE_THR 0x00000001 // Thread state control\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_SYS_PRI1 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_SYS_PRI1_RES_M 0xFF000000 // Priority of reserved handler\r
+#define NVIC_SYS_PRI1_USAGE_M 0x00FF0000 // Priority of usage fault handler\r
+#define NVIC_SYS_PRI1_BUS_M 0x0000FF00 // Priority of bus fault handler\r
+#define NVIC_SYS_PRI1_MEM_M 0x000000FF // Priority of mem manage handler\r
+#define NVIC_SYS_PRI1_USAGE_S 16\r
+#define NVIC_SYS_PRI1_BUS_S 8\r
+#define NVIC_SYS_PRI1_MEM_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_SYS_PRI2 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_SYS_PRI2_SVC_M 0xFF000000 // Priority of SVCall handler\r
+#define NVIC_SYS_PRI2_RES_M 0x00FFFFFF // Priority of reserved handlers\r
+#define NVIC_SYS_PRI2_SVC_S 24\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_SYS_PRI3 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_SYS_PRI3_TICK_M 0xFF000000 // Priority of Sys Tick handler\r
+#define NVIC_SYS_PRI3_PENDSV_M 0x00FF0000 // Priority of PendSV handler\r
+#define NVIC_SYS_PRI3_RES_M 0x0000FF00 // Priority of reserved handler\r
+#define NVIC_SYS_PRI3_DEBUG_M 0x000000FF // Priority of debug handler\r
+#define NVIC_SYS_PRI3_TICK_S 24\r
+#define NVIC_SYS_PRI3_PENDSV_S 16\r
+#define NVIC_SYS_PRI3_DEBUG_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_SYS_HND_CTRL register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_SYS_HND_CTRL_USAGE 0x00040000 // Usage fault enable\r
+#define NVIC_SYS_HND_CTRL_BUS 0x00020000 // Bus fault enable\r
+#define NVIC_SYS_HND_CTRL_MEM 0x00010000 // Mem manage fault enable\r
+#define NVIC_SYS_HND_CTRL_SVC 0x00008000 // SVCall is pended\r
+#define NVIC_SYS_HND_CTRL_BUSP 0x00004000 // Bus fault is pended\r
+#define NVIC_SYS_HND_CTRL_TICK 0x00000800 // Sys tick is active\r
+#define NVIC_SYS_HND_CTRL_PNDSV 0x00000400 // PendSV is active\r
+#define NVIC_SYS_HND_CTRL_MON 0x00000100 // Monitor is active\r
+#define NVIC_SYS_HND_CTRL_SVCA 0x00000080 // SVCall is active\r
+#define NVIC_SYS_HND_CTRL_USGA 0x00000008 // Usage fault is active\r
+#define NVIC_SYS_HND_CTRL_BUSA 0x00000002 // Bus fault is active\r
+#define NVIC_SYS_HND_CTRL_MEMA 0x00000001 // Mem manage is active\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_FAULT_STAT register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_FAULT_STAT_DIV0 0x02000000 // Divide by zero fault\r
+#define NVIC_FAULT_STAT_UNALIGN 0x01000000 // Unaligned access fault\r
+#define NVIC_FAULT_STAT_NOCP 0x00080000 // No coprocessor fault\r
+#define NVIC_FAULT_STAT_INVPC 0x00040000 // Invalid PC fault\r
+#define NVIC_FAULT_STAT_INVSTAT 0x00020000 // Invalid state fault\r
+#define NVIC_FAULT_STAT_UNDEF 0x00010000 // Undefined instruction fault\r
+#define NVIC_FAULT_STAT_BFARV 0x00008000 // BFAR is valid\r
+#define NVIC_FAULT_STAT_BSTKE 0x00001000 // Stack bus fault\r
+#define NVIC_FAULT_STAT_BUSTKE 0x00000800 // Unstack bus fault\r
+#define NVIC_FAULT_STAT_IMPRE 0x00000400 // Imprecise data bus error\r
+#define NVIC_FAULT_STAT_PRECISE 0x00000200 // Precise data bus error\r
+#define NVIC_FAULT_STAT_IBUS 0x00000100 // Instruction bus fault\r
+#define NVIC_FAULT_STAT_MMARV 0x00000080 // MMAR is valid\r
+#define NVIC_FAULT_STAT_MSTKE 0x00000010 // Stack access violation\r
+#define NVIC_FAULT_STAT_MUSTKE 0x00000008 // Unstack access violation\r
+#define NVIC_FAULT_STAT_DERR 0x00000002 // Data access violation\r
+#define NVIC_FAULT_STAT_IERR 0x00000001 // Instruction access violation\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_HFAULT_STAT register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_HFAULT_STAT_DBG 0x80000000 // Debug event\r
+#define NVIC_HFAULT_STAT_FORCED 0x40000000 // Cannot execute fault handler\r
+#define NVIC_HFAULT_STAT_VECT 0x00000002 // Vector table read fault\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_DEBUG_STAT register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_DEBUG_STAT_EXTRNL 0x00000010 // EDBGRQ asserted\r
+#define NVIC_DEBUG_STAT_VCATCH 0x00000008 // Vector catch\r
+#define NVIC_DEBUG_STAT_DWTTRAP 0x00000004 // DWT match\r
+#define NVIC_DEBUG_STAT_BKPT 0x00000002 // Breakpoint instruction\r
+#define NVIC_DEBUG_STAT_HALTED 0x00000001 // Halt request\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_MM_ADDR register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_MM_ADDR_M 0xFFFFFFFF // Data fault address\r
+#define NVIC_MM_ADDR_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_FAULT_ADDR register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_FAULT_ADDR_M 0xFFFFFFFF // Data bus fault address\r
+#define NVIC_FAULT_ADDR_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_EXC_STACK register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_EXC_STACK_DEEP 0x00000001 // Exception stack\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_EXC_NUM register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_EXC_NUM_M 0x000003FF // Exception number\r
+#define NVIC_EXC_NUM_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_COPRO register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_COPRO_15_M 0xC0000000 // Coprocessor 15 access mask\r
+#define NVIC_COPRO_15_DENIED 0x00000000 // Coprocessor 15 access denied\r
+#define NVIC_COPRO_15_PRIV 0x40000000 // Coprocessor 15 privileged addess\r
+#define NVIC_COPRO_15_FULL 0xC0000000 // Coprocessor 15 full access\r
+#define NVIC_COPRO_14_M 0x30000000 // Coprocessor 14 access mask\r
+#define NVIC_COPRO_14_DENIED 0x00000000 // Coprocessor 14 access denied\r
+#define NVIC_COPRO_14_PRIV 0x10000000 // Coprocessor 14 privileged addess\r
+#define NVIC_COPRO_14_FULL 0x30000000 // Coprocessor 14 full access\r
+#define NVIC_COPRO_13_M 0x0C000000 // Coprocessor 13 access mask\r
+#define NVIC_COPRO_13_DENIED 0x00000000 // Coprocessor 13 access denied\r
+#define NVIC_COPRO_13_PRIV 0x04000000 // Coprocessor 13 privileged addess\r
+#define NVIC_COPRO_13_FULL 0x0C000000 // Coprocessor 13 full access\r
+#define NVIC_COPRO_12_M 0x03000000 // Coprocessor 12 access mask\r
+#define NVIC_COPRO_12_DENIED 0x00000000 // Coprocessor 12 access denied\r
+#define NVIC_COPRO_12_PRIV 0x01000000 // Coprocessor 12 privileged addess\r
+#define NVIC_COPRO_12_FULL 0x03000000 // Coprocessor 12 full access\r
+#define NVIC_COPRO_11_M 0x00C00000 // Coprocessor 11 access mask\r
+#define NVIC_COPRO_11_DENIED 0x00000000 // Coprocessor 11 access denied\r
+#define NVIC_COPRO_11_PRIV 0x00400000 // Coprocessor 11 privileged addess\r
+#define NVIC_COPRO_11_FULL 0x00C00000 // Coprocessor 11 full access\r
+#define NVIC_COPRO_10_M 0x00300000 // Coprocessor 10 access mask\r
+#define NVIC_COPRO_10_DENIED 0x00000000 // Coprocessor 10 access denied\r
+#define NVIC_COPRO_10_PRIV 0x00100000 // Coprocessor 10 privileged addess\r
+#define NVIC_COPRO_10_FULL 0x00300000 // Coprocessor 10 full access\r
+#define NVIC_COPRO_9_M 0x000C0000 // Coprocessor 9 access mask\r
+#define NVIC_COPRO_9_DENIED 0x00000000 // Coprocessor 9 access denied\r
+#define NVIC_COPRO_9_PRIV 0x00040000 // Coprocessor 9 privileged addess\r
+#define NVIC_COPRO_9_FULL 0x000C0000 // Coprocessor 9 full access\r
+#define NVIC_COPRO_8_M 0x00030000 // Coprocessor 8 access mask\r
+#define NVIC_COPRO_8_DENIED 0x00000000 // Coprocessor 8 access denied\r
+#define NVIC_COPRO_8_PRIV 0x00010000 // Coprocessor 8 privileged addess\r
+#define NVIC_COPRO_8_FULL 0x00030000 // Coprocessor 8 full access\r
+#define NVIC_COPRO_7_M 0x0000C000 // Coprocessor 7 access mask\r
+#define NVIC_COPRO_7_DENIED 0x00000000 // Coprocessor 7 access denied\r
+#define NVIC_COPRO_7_PRIV 0x00004000 // Coprocessor 7 privileged addess\r
+#define NVIC_COPRO_7_FULL 0x0000C000 // Coprocessor 7 full access\r
+#define NVIC_COPRO_6_M 0x00003000 // Coprocessor 6 access mask\r
+#define NVIC_COPRO_6_DENIED 0x00000000 // Coprocessor 6 access denied\r
+#define NVIC_COPRO_6_PRIV 0x00001000 // Coprocessor 6 privileged addess\r
+#define NVIC_COPRO_6_FULL 0x00003000 // Coprocessor 6 full access\r
+#define NVIC_COPRO_5_M 0x00000C00 // Coprocessor 5 access mask\r
+#define NVIC_COPRO_5_DENIED 0x00000000 // Coprocessor 5 access denied\r
+#define NVIC_COPRO_5_PRIV 0x00000400 // Coprocessor 5 privileged addess\r
+#define NVIC_COPRO_5_FULL 0x00000C00 // Coprocessor 5 full access\r
+#define NVIC_COPRO_4_M 0x00000300 // Coprocessor 4 access mask\r
+#define NVIC_COPRO_4_DENIED 0x00000000 // Coprocessor 4 access denied\r
+#define NVIC_COPRO_4_PRIV 0x00000100 // Coprocessor 4 privileged addess\r
+#define NVIC_COPRO_4_FULL 0x00000300 // Coprocessor 4 full access\r
+#define NVIC_COPRO_3_M 0x000000C0 // Coprocessor 3 access mask\r
+#define NVIC_COPRO_3_DENIED 0x00000000 // Coprocessor 3 access denied\r
+#define NVIC_COPRO_3_PRIV 0x00000040 // Coprocessor 3 privileged addess\r
+#define NVIC_COPRO_3_FULL 0x000000C0 // Coprocessor 3 full access\r
+#define NVIC_COPRO_2_M 0x00000030 // Coprocessor 2 access mask\r
+#define NVIC_COPRO_2_DENIED 0x00000000 // Coprocessor 2 access denied\r
+#define NVIC_COPRO_2_PRIV 0x00000010 // Coprocessor 2 privileged addess\r
+#define NVIC_COPRO_2_FULL 0x00000030 // Coprocessor 2 full access\r
+#define NVIC_COPRO_1_M 0x0000000C // Coprocessor 1 access mask\r
+#define NVIC_COPRO_1_DENIED 0x00000000 // Coprocessor 1 access denied\r
+#define NVIC_COPRO_1_PRIV 0x00000004 // Coprocessor 1 privileged addess\r
+#define NVIC_COPRO_1_FULL 0x0000000C // Coprocessor 1 full access\r
+#define NVIC_COPRO_0_M 0x00000003 // Coprocessor 0 access mask\r
+#define NVIC_COPRO_0_DENIED 0x00000000 // Coprocessor 0 access denied\r
+#define NVIC_COPRO_0_PRIV 0x00000001 // Coprocessor 0 privileged addess\r
+#define NVIC_COPRO_0_FULL 0x00000003 // Coprocessor 0 full access\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_MPU_TYPE register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_MPU_TYPE_IREGION_M 0x00FF0000 // Number of I regions\r
+#define NVIC_MPU_TYPE_DREGION_M 0x0000FF00 // Number of D regions\r
+#define NVIC_MPU_TYPE_SEPARATE 0x00000001 // Separate or unified MPU\r
+#define NVIC_MPU_TYPE_IREGION_S 16\r
+#define NVIC_MPU_TYPE_DREGION_S 8\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_MPU_CTRL register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_MPU_CTRL_HFNMIENA 0x00000002 // MPU enabled during faults\r
+#define NVIC_MPU_CTRL_ENABLE 0x00000001 // MPU enable\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_MPU_NUMBER register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_MPU_NUMBER_M 0x000000FF // MPU region to access\r
+#define NVIC_MPU_NUMBER_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_MPU_BASE register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_MPU_BASE_ADDR_M 0xFFFFFF00 // Base address\r
+#define NVIC_MPU_BASE_VALID 0x00000010 // Region number valid\r
+#define NVIC_MPU_BASE_REGION_M 0x0000000F // Region number\r
+#define NVIC_MPU_BASE_ADDR_S 8\r
+#define NVIC_MPU_BASE_REGION_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_MPU_ATTR register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_MPU_ATTR_ATTRS 0xFFFF0000 // Attributes\r
+#define NVIC_MPU_ATTR_SRD 0x0000FF00 // Sub-region disable\r
+#define NVIC_MPU_ATTR_SZENABLE 0x000000FF // Region size\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_DBG_CTRL register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_DBG_CTRL_DBGKEY_M 0xFFFF0000 // Debug key mask\r
+#define NVIC_DBG_CTRL_DBGKEY 0xA05F0000 // Debug key\r
+#define NVIC_DBG_CTRL_MON_PEND 0x00008000 // Pend the monitor\r
+#define NVIC_DBG_CTRL_MON_REQ 0x00004000 // Monitor request\r
+#define NVIC_DBG_CTRL_MON_EN 0x00002000 // Debug monitor enable\r
+#define NVIC_DBG_CTRL_MONSTEP 0x00001000 // Monitor step the core\r
+#define NVIC_DBG_CTRL_S_SLEEP 0x00000400 // Core is sleeping\r
+#define NVIC_DBG_CTRL_S_HALT 0x00000200 // Core status on halt\r
+#define NVIC_DBG_CTRL_S_REGRDY 0x00000100 // Register read/write available\r
+#define NVIC_DBG_CTRL_S_LOCKUP 0x00000080 // Core is locked up\r
+#define NVIC_DBG_CTRL_C_RESET 0x00000010 // Reset the core\r
+#define NVIC_DBG_CTRL_C_MASKINT 0x00000008 // Mask interrupts when stepping\r
+#define NVIC_DBG_CTRL_C_STEP 0x00000004 // Step the core\r
+#define NVIC_DBG_CTRL_C_HALT 0x00000002 // Halt the core\r
+#define NVIC_DBG_CTRL_C_DEBUGEN 0x00000001 // Enable debug\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_DBG_XFER register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_DBG_XFER_REG_WNR 0x00010000 // Write or not read\r
+#define NVIC_DBG_XFER_REG_SEL_M 0x0000001F // Register\r
+#define NVIC_DBG_XFER_REG_R0 0x00000000 // Register R0\r
+#define NVIC_DBG_XFER_REG_R1 0x00000001 // Register R1\r
+#define NVIC_DBG_XFER_REG_R2 0x00000002 // Register R2\r
+#define NVIC_DBG_XFER_REG_R3 0x00000003 // Register R3\r
+#define NVIC_DBG_XFER_REG_R4 0x00000004 // Register R4\r
+#define NVIC_DBG_XFER_REG_R5 0x00000005 // Register R5\r
+#define NVIC_DBG_XFER_REG_R6 0x00000006 // Register R6\r
+#define NVIC_DBG_XFER_REG_R7 0x00000007 // Register R7\r
+#define NVIC_DBG_XFER_REG_R8 0x00000008 // Register R8\r
+#define NVIC_DBG_XFER_REG_R9 0x00000009 // Register R9\r
+#define NVIC_DBG_XFER_REG_R10 0x0000000A // Register R10\r
+#define NVIC_DBG_XFER_REG_R11 0x0000000B // Register R11\r
+#define NVIC_DBG_XFER_REG_R12 0x0000000C // Register R12\r
+#define NVIC_DBG_XFER_REG_R13 0x0000000D // Register R13\r
+#define NVIC_DBG_XFER_REG_R14 0x0000000E // Register R14\r
+#define NVIC_DBG_XFER_REG_R15 0x0000000F // Register R15\r
+#define NVIC_DBG_XFER_REG_FLAGS 0x00000010 // xPSR/Flags register\r
+#define NVIC_DBG_XFER_REG_MSP 0x00000011 // Main SP\r
+#define NVIC_DBG_XFER_REG_PSP 0x00000012 // Process SP\r
+#define NVIC_DBG_XFER_REG_DSP 0x00000013 // Deep SP\r
+#define NVIC_DBG_XFER_REG_CFBP 0x00000014 // Control/Fault/BasePri/PriMask\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_DBG_DATA register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_DBG_DATA_M 0xFFFFFFFF // Data temporary cache\r
+#define NVIC_DBG_DATA_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_DBG_INT register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_DBG_INT_HARDERR 0x00000400 // Debug trap on hard fault\r
+#define NVIC_DBG_INT_INTERR 0x00000200 // Debug trap on interrupt errors\r
+#define NVIC_DBG_INT_BUSERR 0x00000100 // Debug trap on bus error\r
+#define NVIC_DBG_INT_STATERR 0x00000080 // Debug trap on usage fault state\r
+#define NVIC_DBG_INT_CHKERR 0x00000040 // Debug trap on usage fault check\r
+#define NVIC_DBG_INT_NOCPERR 0x00000020 // Debug trap on coprocessor error\r
+#define NVIC_DBG_INT_MMERR 0x00000010 // Debug trap on mem manage fault\r
+#define NVIC_DBG_INT_RESET 0x00000008 // Core reset status\r
+#define NVIC_DBG_INT_RSTPENDCLR 0x00000004 // Clear pending core reset\r
+#define NVIC_DBG_INT_RSTPENDING 0x00000002 // Core reset is pending\r
+#define NVIC_DBG_INT_RSTVCATCH 0x00000001 // Reset vector catch\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_SW_TRIG register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_SW_TRIG_INTID_M 0x000003FF // Interrupt to trigger\r
+#define NVIC_SW_TRIG_INTID_S 0\r
+\r
+#endif // __HW_NVIC_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_pwm.h - Defines and Macros for Pulse Width Modulation (PWM) ports\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_PWM_H__\r
+#define __HW_PWM_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// PWM Module Register Offsets.\r
+//\r
+//*****************************************************************************\r
+#define PWM_O_CTL 0x00000000 // PWM Master Control register\r
+#define PWM_O_SYNC 0x00000004 // PWM Time Base Sync register\r
+#define PWM_O_ENABLE 0x00000008 // PWM Output Enable register\r
+#define PWM_O_INVERT 0x0000000C // PWM Output Inversion register\r
+#define PWM_O_FAULT 0x00000010 // PWM Output Fault register\r
+#define PWM_O_INTEN 0x00000014 // PWM Interrupt Enable register\r
+#define PWM_O_RIS 0x00000018 // PWM Interrupt Raw Status reg.\r
+#define PWM_O_ISC 0x0000001C // PWM Interrupt Status register\r
+#define PWM_O_STATUS 0x00000020 // PWM Status register\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the PWM Master Control register.\r
+//\r
+//*****************************************************************************\r
+#define PWM_CTL_GLOBAL_SYNC2 0x00000004 // Global sync generator 2\r
+#define PWM_CTL_GLOBAL_SYNC1 0x00000002 // Global sync generator 1\r
+#define PWM_CTL_GLOBAL_SYNC0 0x00000001 // Global sync generator 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the PWM Time Base Sync register.\r
+//\r
+//*****************************************************************************\r
+#define PWM_SYNC_SYNC2 0x00000004 // Reset generator 2 counter\r
+#define PWM_SYNC_SYNC1 0x00000002 // Reset generator 1 counter\r
+#define PWM_SYNC_SYNC0 0x00000001 // Reset generator 0 counter\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the PWM Output Enable register.\r
+//\r
+//*****************************************************************************\r
+#define PWM_ENABLE_PWM5EN 0x00000020 // PWM5 pin enable\r
+#define PWM_ENABLE_PWM4EN 0x00000010 // PWM4 pin enable\r
+#define PWM_ENABLE_PWM3EN 0x00000008 // PWM3 pin enable\r
+#define PWM_ENABLE_PWM2EN 0x00000004 // PWM2 pin enable\r
+#define PWM_ENABLE_PWM1EN 0x00000002 // PWM1 pin enable\r
+#define PWM_ENABLE_PWM0EN 0x00000001 // PWM0 pin enable\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the PWM Inversion register.\r
+//\r
+//*****************************************************************************\r
+#define PWM_INVERT_PWM5INV 0x00000020 // PWM5 pin invert\r
+#define PWM_INVERT_PWM4INV 0x00000010 // PWM4 pin invert\r
+#define PWM_INVERT_PWM3INV 0x00000008 // PWM3 pin invert\r
+#define PWM_INVERT_PWM2INV 0x00000004 // PWM2 pin invert\r
+#define PWM_INVERT_PWM1INV 0x00000002 // PWM1 pin invert\r
+#define PWM_INVERT_PWM0INV 0x00000001 // PWM0 pin invert\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the PWM Fault register.\r
+//\r
+//*****************************************************************************\r
+#define PWM_FAULT_FAULT5 0x00000020 // PWM5 pin fault\r
+#define PWM_FAULT_FAULT4 0x00000010 // PWM5 pin fault\r
+#define PWM_FAULT_FAULT3 0x00000008 // PWM5 pin fault\r
+#define PWM_FAULT_FAULT2 0x00000004 // PWM5 pin fault\r
+#define PWM_FAULT_FAULT1 0x00000002 // PWM5 pin fault\r
+#define PWM_FAULT_FAULT0 0x00000001 // PWM5 pin fault\r
+\r
+//*****************************************************************************\r
+//\r
+// PWM Interrupt Register bit definitions.\r
+//\r
+//*****************************************************************************\r
+#define PWM_INT_INTFAULT 0x00010000 // Fault interrupt pending\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the PWM Status register.\r
+//\r
+//*****************************************************************************\r
+#define PWM_STATUS_FAULT 0x00000001 // Fault status\r
+\r
+//*****************************************************************************\r
+//\r
+// PWM Generator standard offsets.\r
+//\r
+//*****************************************************************************\r
+#define PWM_GEN_0_OFFSET 0x00000040 // PWM0 base\r
+#define PWM_GEN_1_OFFSET 0x00000080 // PWM1 base\r
+#define PWM_GEN_2_OFFSET 0x000000C0 // PWM2 base\r
+\r
+#define PWM_O_X_CTL 0x00000000 // Gen Control Reg\r
+#define PWM_O_X_INTEN 0x00000004 // Gen Int/Trig Enable Reg\r
+#define PWM_O_X_RIS 0x00000008 // Gen Raw Int Status Reg\r
+#define PWM_O_X_ISC 0x0000000C // Gen Int Status Reg\r
+#define PWM_O_X_LOAD 0x00000010 // Gen Load Reg\r
+#define PWM_O_X_COUNT 0x00000014 // Gen Counter Reg\r
+#define PWM_O_X_CMPA 0x00000018 // Gen Compare A Reg\r
+#define PWM_O_X_CMPB 0x0000001C // Gen Compare B Reg\r
+#define PWM_O_X_GENA 0x00000020 // Gen Generator A Ctrl Reg\r
+#define PWM_O_X_GENB 0x00000024 // Gen Generator B Ctrl Reg\r
+#define PWM_O_X_DBCTL 0x00000028 // Gen Dead Band Ctrl Reg\r
+#define PWM_O_X_DBRISE 0x0000002C // Gen DB Rising Edge Delay Reg\r
+#define PWM_O_X_DBFALL 0x00000030 // Gen DB Falling Edge Delay Reg\r
+\r
+//*****************************************************************************\r
+//\r
+// PWM_X Control Register bit definitions.\r
+//\r
+//*****************************************************************************\r
+#define PWM_X_CTL_ENABLE 0x00000001 // Master enable for gen block\r
+#define PWM_X_CTL_MODE 0x00000002 // Counter mode, down or up/down\r
+#define PWM_X_CTL_DEBUG 0x00000004 // Debug mode\r
+#define PWM_X_CTL_LOADUPD 0x00000008 // Update mode for the load reg\r
+#define PWM_X_CTL_CMPAUPD 0x00000010 // Update mode for comp A reg\r
+#define PWM_X_CTL_CMPBUPD 0x00000020 // Update mode for comp B reg\r
+\r
+//*****************************************************************************\r
+//\r
+// PWM_X Interrupt/Trigger Enable Register bit definitions.\r
+//\r
+//*****************************************************************************\r
+#define PWM_X_INTEN_INTCNTZERO 0x00000001 // Int if COUNT = 0\r
+#define PWM_X_INTEN_INTCNTLOAD 0x00000002 // Int if COUNT = LOAD\r
+#define PWM_X_INTEN_INTCMPAU 0x00000004 // Int if COUNT = CMPA U\r
+#define PWM_X_INTEN_INTCMPAD 0x00000008 // Int if COUNT = CMPA D\r
+#define PWM_X_INTEN_INTCMPBU 0x00000010 // Int if COUNT = CMPA U\r
+#define PWM_X_INTEN_INTCMPBD 0x00000020 // Int if COUNT = CMPA D\r
+#define PWM_X_INTEN_TRCNTZERO 0x00000100 // Trig if COUNT = 0\r
+#define PWM_X_INTEN_TRCNTLOAD 0x00000200 // Trig if COUNT = LOAD\r
+#define PWM_X_INTEN_TRCMPAU 0x00000400 // Trig if COUNT = CMPA U\r
+#define PWM_X_INTEN_TRCMPAD 0x00000800 // Trig if COUNT = CMPA D\r
+#define PWM_X_INTEN_TRCMPBU 0x00001000 // Trig if COUNT = CMPA U\r
+#define PWM_X_INTEN_TRCMPBD 0x00002000 // Trig if COUNT = CMPA D\r
+\r
+//*****************************************************************************\r
+//\r
+// PWM_X Raw Interrupt Status Register bit definitions.\r
+//\r
+//*****************************************************************************\r
+#define PWM_X_RIS_INTCNTZERO 0x00000001 // PWM_X_COUNT = 0 int\r
+#define PWM_X_RIS_INTCNTLOAD 0x00000002 // PWM_X_COUNT = PWM_X_LOAD int\r
+#define PWM_X_RIS_INTCMPAU 0x00000004 // PWM_X_COUNT = PWM_X_CMPA U int\r
+#define PWM_X_RIS_INTCMPAD 0x00000008 // PWM_X_COUNT = PWM_X_CMPA D int\r
+#define PWM_X_RIS_INTCMPBU 0x00000010 // PWM_X_COUNT = PWM_X_CMPB U int\r
+#define PWM_X_RIS_INTCMPBD 0x00000020 // PWM_X_COUNT = PWM_X_CMPB D int\r
+\r
+//*****************************************************************************\r
+//\r
+// PWM_X Interrupt Status Register bit definitions.\r
+//\r
+//*****************************************************************************\r
+#define PWM_X_INT_INTCNTZERO 0x00000001 // PWM_X_COUNT = 0 received\r
+#define PWM_X_INT_INTCNTLOAD 0x00000002 // PWM_X_COUNT = PWM_X_LOAD rcvd\r
+#define PWM_X_INT_INTCMPAU 0x00000004 // PWM_X_COUNT = PWM_X_CMPA U rcvd\r
+#define PWM_X_INT_INTCMPAD 0x00000008 // PWM_X_COUNT = PWM_X_CMPA D rcvd\r
+#define PWM_X_INT_INTCMPBU 0x00000010 // PWM_X_COUNT = PWM_X_CMPB U rcvd\r
+#define PWM_X_INT_INTCMPBD 0x00000020 // PWM_X_COUNT = PWM_X_CMPB D rcvd\r
+\r
+//*****************************************************************************\r
+//\r
+// PWM_X Generator A/B Control Register bit definitions.\r
+//\r
+//*****************************************************************************\r
+#define PWM_X_GEN_Y_ACTZERO 0x00000003 // Act PWM_X_COUNT = 0\r
+#define PWM_X_GEN_Y_ACTLOAD 0x0000000C // Act PWM_X_COUNT = PWM_X_LOAD\r
+#define PWM_X_GEN_Y_ACTCMPAU 0x00000030 // Act PWM_X_COUNT = PWM_X_CMPA U\r
+#define PWM_X_GEN_Y_ACTCMPAD 0x000000C0 // Act PWM_X_COUNT = PWM_X_CMPA D\r
+#define PWM_X_GEN_Y_ACTCMPBU 0x00000300 // Act PWM_X_COUNT = PWM_X_CMPB U\r
+#define PWM_X_GEN_Y_ACTCMPBD 0x00000C00 // Act PWM_X_COUNT = PWM_X_CMPB D\r
+\r
+//*****************************************************************************\r
+//\r
+// PWM_X Generator A/B Control Register action definitions.\r
+//\r
+//*****************************************************************************\r
+#define PWM_GEN_ACT_NONE 0x0 // Do nothing\r
+#define PWM_GEN_ACT_INV 0x1 // Invert the output signal\r
+#define PWM_GEN_ACT_ZERO 0x2 // Set the output signal to zero\r
+#define PWM_GEN_ACT_ONE 0x3 // Set the output signal to one\r
+#define PWM_GEN_ACT_ZERO_SHIFT 0 // Shift amount for the zero action\r
+#define PWM_GEN_ACT_LOAD_SHIFT 2 // Shift amount for the load action\r
+#define PWM_GEN_ACT_A_UP_SHIFT 4 // Shift amount for the A up action\r
+#define PWM_GEN_ACT_A_DN_SHIFT 6 // Shift amount for the A dn action\r
+#define PWM_GEN_ACT_B_UP_SHIFT 8 // Shift amount for the B up action\r
+#define PWM_GEN_ACT_B_DN_SHIFT 10 // Shift amount for the B dn action\r
+\r
+//*****************************************************************************\r
+//\r
+// PWM_X Dead Band Control Register bit definitions.\r
+//\r
+//*****************************************************************************\r
+#define PWM_DBCTL_ENABLE 0x00000001 // Enable dead band insertion\r
+\r
+//*****************************************************************************\r
+//\r
+// PWM Register reset values.\r
+//\r
+//*****************************************************************************\r
+#define PWM_RV_CTL 0x00000000 // Master control of the PWM module\r
+#define PWM_RV_SYNC 0x00000000 // Counter synch for PWM generators\r
+#define PWM_RV_ENABLE 0x00000000 // Master enable for the PWM\r
+ // output pins\r
+#define PWM_RV_INVERT 0x00000000 // Inversion control for\r
+ // PWM output pins\r
+#define PWM_RV_FAULT 0x00000000 // Fault handling for the PWM\r
+ // output pins\r
+#define PWM_RV_INTEN 0x00000000 // Interrupt enable\r
+#define PWM_RV_RIS 0x00000000 // Raw interrupt status\r
+#define PWM_RV_ISC 0x00000000 // Interrupt status and clearing\r
+#define PWM_RV_STATUS 0x00000000 // Status\r
+#define PWM_RV_X_CTL 0x00000000 // Master control of the PWM\r
+ // generator block\r
+#define PWM_RV_X_INTEN 0x00000000 // Interrupt and trigger enable\r
+#define PWM_RV_X_RIS 0x00000000 // Raw interrupt status\r
+#define PWM_RV_X_ISC 0x00000000 // Interrupt status and clearing\r
+#define PWM_RV_X_LOAD 0x00000000 // The load value for the counter\r
+#define PWM_RV_X_COUNT 0x00000000 // The current counter value\r
+#define PWM_RV_X_CMPA 0x00000000 // The comparator A value\r
+#define PWM_RV_X_CMPB 0x00000000 // The comparator B value\r
+#define PWM_RV_X_GENA 0x00000000 // Controls PWM generator A\r
+#define PWM_RV_X_GENB 0x00000000 // Controls PWM generator B\r
+#define PWM_RV_X_DBCTL 0x00000000 // Control the dead band generator\r
+#define PWM_RV_X_DBRISE 0x00000000 // The dead band rising edge delay\r
+ // count\r
+#define PWM_RV_X_DBFALL 0x00000000 // The dead band falling edge delay\r
+ // count\r
+\r
+#endif // __HW_PWM_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_qei.h - Macros used when accessing the QEI hardware.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_QEI_H__\r
+#define __HW_QEI_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the offsets of the QEI registers.\r
+//\r
+//*****************************************************************************\r
+#define QEI_O_CTL 0x00000000 // Configuration and control reg.\r
+#define QEI_O_STAT 0x00000004 // Status register\r
+#define QEI_O_POS 0x00000008 // Current position register\r
+#define QEI_O_MAXPOS 0x0000000C // Maximum position register\r
+#define QEI_O_LOAD 0x00000010 // Velocity timer load register\r
+#define QEI_O_TIME 0x00000014 // Velocity timer register\r
+#define QEI_O_COUNT 0x00000018 // Velocity pulse count register\r
+#define QEI_O_SPEED 0x0000001C // Velocity speed register\r
+#define QEI_O_INTEN 0x00000020 // Interrupt enable register\r
+#define QEI_O_RIS 0x00000024 // Raw interrupt status register\r
+#define QEI_O_ISC 0x00000028 // Interrupt status register\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the QEI_CTL register.\r
+//\r
+//*****************************************************************************\r
+#define QEI_CTL_STALLEN 0x00001000 // Stall enable\r
+#define QEI_CTL_INVI 0x00000800 // Invert Index input\r
+#define QEI_CTL_INVB 0x00000400 // Invert PhB input\r
+#define QEI_CTL_INVA 0x00000200 // Invert PhA input\r
+#define QEI_CTL_VELDIV_M 0x000001C0 // Velocity predivider mask\r
+#define QEI_CTL_VELDIV_1 0x00000000 // Predivide by 1\r
+#define QEI_CTL_VELDIV_2 0x00000040 // Predivide by 2\r
+#define QEI_CTL_VELDIV_4 0x00000080 // Predivide by 4\r
+#define QEI_CTL_VELDIV_8 0x000000C0 // Predivide by 8\r
+#define QEI_CTL_VELDIV_16 0x00000100 // Predivide by 16\r
+#define QEI_CTL_VELDIV_32 0x00000140 // Predivide by 32\r
+#define QEI_CTL_VELDIV_64 0x00000180 // Predivide by 64\r
+#define QEI_CTL_VELDIV_128 0x000001C0 // Predivide by 128\r
+#define QEI_CTL_VELEN 0x00000020 // Velocity enable\r
+#define QEI_CTL_RESMODE 0x00000010 // Position counter reset mode\r
+#define QEI_CTL_CAPMODE 0x00000008 // Edge capture mode\r
+#define QEI_CTL_SIGMODE 0x00000004 // Encoder signaling mode\r
+#define QEI_CTL_SWAP 0x00000002 // Swap input signals\r
+#define QEI_CTL_ENABLE 0x00000001 // QEI enable\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the QEI_STAT register.\r
+//\r
+//*****************************************************************************\r
+#define QEI_STAT_DIRECTION 0x00000002 // Direction of rotation\r
+#define QEI_STAT_ERROR 0x00000001 // Signalling error detected\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the QEI_POS register.\r
+//\r
+//*****************************************************************************\r
+#define QEI_POS_M 0xFFFFFFFF // Current encoder position\r
+#define QEI_POS_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the QEI_MAXPOS register.\r
+//\r
+//*****************************************************************************\r
+#define QEI_MAXPOS_M 0xFFFFFFFF // Maximum encoder position\r
+#define QEI_MAXPOS_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the QEI_LOAD register.\r
+//\r
+//*****************************************************************************\r
+#define QEI_LOAD_M 0xFFFFFFFF // Velocity timer load value\r
+#define QEI_LOAD_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the QEI_TIME register.\r
+//\r
+//*****************************************************************************\r
+#define QEI_TIME_M 0xFFFFFFFF // Velocity timer current value\r
+#define QEI_TIME_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the QEI_COUNT register.\r
+//\r
+//*****************************************************************************\r
+#define QEI_COUNT_M 0xFFFFFFFF // Encoder running pulse count\r
+#define QEI_COUNT_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the QEI_SPEED register.\r
+//\r
+//*****************************************************************************\r
+#define QEI_SPEED_M 0xFFFFFFFF // Encoder pulse count\r
+#define QEI_SPEED_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the QEI_INTEN register.\r
+//\r
+//*****************************************************************************\r
+#define QEI_INTEN_ERROR 0x00000008 // Phase error detected\r
+#define QEI_INTEN_DIR 0x00000004 // Direction change\r
+#define QEI_INTEN_TIMER 0x00000002 // Velocity timer expired\r
+#define QEI_INTEN_INDEX 0x00000001 // Index pulse detected\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the QEI_RIS register.\r
+//\r
+//*****************************************************************************\r
+#define QEI_RIS_ERROR 0x00000008 // Phase error detected\r
+#define QEI_RIS_DIR 0x00000004 // Direction change\r
+#define QEI_RIS_TIMER 0x00000002 // Velocity timer expired\r
+#define QEI_RIS_INDEX 0x00000001 // Index pulse detected\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the QEI_ISC register.\r
+//\r
+//*****************************************************************************\r
+#define QEI_INT_ERROR 0x00000008 // Phase error detected\r
+#define QEI_INT_DIR 0x00000004 // Direction change\r
+#define QEI_INT_TIMER 0x00000002 // Velocity timer expired\r
+#define QEI_INT_INDEX 0x00000001 // Index pulse detected\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the reset values for the QEI registers.\r
+//\r
+//*****************************************************************************\r
+#define QEI_RV_CTL 0x00000000 // Configuration and control reg.\r
+#define QEI_RV_STAT 0x00000000 // Status register\r
+#define QEI_RV_POS 0x00000000 // Current position register\r
+#define QEI_RV_MAXPOS 0x00000000 // Maximum position register\r
+#define QEI_RV_LOAD 0x00000000 // Velocity timer load register\r
+#define QEI_RV_TIME 0x00000000 // Velocity timer register\r
+#define QEI_RV_COUNT 0x00000000 // Velocity pulse count register\r
+#define QEI_RV_SPEED 0x00000000 // Velocity speed register\r
+#define QEI_RV_INTEN 0x00000000 // Interrupt enable register\r
+#define QEI_RV_RIS 0x00000000 // Raw interrupt status register\r
+#define QEI_RV_ISC 0x00000000 // Interrupt status register\r
+\r
+#endif // __HW_QEI_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_ssi.h - Macros used when accessing the SSI hardware.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_SSI_H__\r
+#define __HW_SSI_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the offsets of the SSI registers.\r
+//\r
+//*****************************************************************************\r
+#define SSI_O_CR0 0x00000000 // Control register 0\r
+#define SSI_O_CR1 0x00000004 // Control register 1\r
+#define SSI_O_DR 0x00000008 // Data register\r
+#define SSI_O_SR 0x0000000C // Status register\r
+#define SSI_O_CPSR 0x00000010 // Clock prescale register\r
+#define SSI_O_IM 0x00000014 // Int mask set and clear register\r
+#define SSI_O_RIS 0x00000018 // Raw interrupt register\r
+#define SSI_O_MIS 0x0000001C // Masked interrupt register\r
+#define SSI_O_ICR 0x00000020 // Interrupt clear register\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SSI Control register 0.\r
+//\r
+//*****************************************************************************\r
+#define SSI_CR0_SCR 0x0000FF00 // Serial clock rate\r
+#define SSI_CR0_SPH 0x00000080 // SSPCLKOUT phase\r
+#define SSI_CR0_SPO 0x00000040 // SSPCLKOUT polarity\r
+#define SSI_CR0_FRF_MASK 0x00000030 // Frame format mask\r
+#define SSI_CR0_FRF_MOTO 0x00000000 // Motorola SPI frame format\r
+#define SSI_CR0_FRF_TI 0x00000010 // TI sync serial frame format\r
+#define SSI_CR0_FRF_NMW 0x00000020 // National Microwire frame format\r
+#define SSI_CR0_DSS 0x0000000F // Data size select\r
+#define SSI_CR0_DSS_4 0x00000003 // 4 bit data\r
+#define SSI_CR0_DSS_5 0x00000004 // 5 bit data\r
+#define SSI_CR0_DSS_6 0x00000005 // 6 bit data\r
+#define SSI_CR0_DSS_7 0x00000006 // 7 bit data\r
+#define SSI_CR0_DSS_8 0x00000007 // 8 bit data\r
+#define SSI_CR0_DSS_9 0x00000008 // 9 bit data\r
+#define SSI_CR0_DSS_10 0x00000009 // 10 bit data\r
+#define SSI_CR0_DSS_11 0x0000000A // 11 bit data\r
+#define SSI_CR0_DSS_12 0x0000000B // 12 bit data\r
+#define SSI_CR0_DSS_13 0x0000000C // 13 bit data\r
+#define SSI_CR0_DSS_14 0x0000000D // 14 bit data\r
+#define SSI_CR0_DSS_15 0x0000000E // 15 bit data\r
+#define SSI_CR0_DSS_16 0x0000000F // 16 bit data\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SSI Control register 1.\r
+//\r
+//*****************************************************************************\r
+#define SSI_CR1_SOD 0x00000008 // Slave mode output disable\r
+#define SSI_CR1_MS 0x00000004 // Master or slave mode select\r
+#define SSI_CR1_SSE 0x00000002 // Sync serial port enable\r
+#define SSI_CR1_LBM 0x00000001 // Loopback mode\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SSI Status register.\r
+//\r
+//*****************************************************************************\r
+#define SSI_SR_BSY 0x00000010 // SSI busy\r
+#define SSI_SR_RFF 0x00000008 // RX FIFO full\r
+#define SSI_SR_RNE 0x00000004 // RX FIFO not empty\r
+#define SSI_SR_TNF 0x00000002 // TX FIFO not full\r
+#define SSI_SR_TFE 0x00000001 // TX FIFO empty\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SSI clock prescale register.\r
+//\r
+//*****************************************************************************\r
+#define SSI_CPSR_CPSDVSR_MASK 0x000000FF // Clock prescale\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define information concerning the SSI Data register.\r
+//\r
+//*****************************************************************************\r
+#define TX_FIFO_SIZE (8) // Number of entries in the TX FIFO\r
+#define RX_FIFO_SIZE (8) // Number of entries in the RX FIFO\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the interrupt mask set and clear,\r
+// raw interrupt, masked interrupt, and interrupt clear registers.\r
+//\r
+//*****************************************************************************\r
+#define SSI_INT_TXFF 0x00000008 // TX FIFO interrupt\r
+#define SSI_INT_RXFF 0x00000004 // RX FIFO interrupt\r
+#define SSI_INT_RXTO 0x00000002 // RX timeout interrupt\r
+#define SSI_INT_RXOR 0x00000001 // RX overrun interrupt\r
+\r
+#endif // __HW_SSI_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_sysctl.h - Macros used when accessing the system control hardware.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_SYSCTL_H__\r
+#define __HW_SYSCTL_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the addresses of the system control registers.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_DID0 0x400fe000 // Device identification register 0\r
+#define SYSCTL_DID1 0x400fe004 // Device identification register 1\r
+#define SYSCTL_DC0 0x400fe008 // Device capabilities register 0\r
+#define SYSCTL_DC1 0x400fe010 // Device capabilities register 1\r
+#define SYSCTL_DC2 0x400fe014 // Device capabilities register 2\r
+#define SYSCTL_DC3 0x400fe018 // Device capabilities register 3\r
+#define SYSCTL_DC4 0x400fe01C // Device capabilities register 4\r
+#define SYSCTL_PBORCTL 0x400fe030 // POR/BOR reset control register\r
+#define SYSCTL_LDOPCTL 0x400fe034 // LDO power control register\r
+#define SYSCTL_SRCR0 0x400fe040 // Software reset control reg 0\r
+#define SYSCTL_SRCR1 0x400fe044 // Software reset control reg 1\r
+#define SYSCTL_SRCR2 0x400fe048 // Software reset control reg 2\r
+#define SYSCTL_RIS 0x400fe050 // Raw interrupt status register\r
+#define SYSCTL_IMC 0x400fe054 // Interrupt mask/control register\r
+#define SYSCTL_MISC 0x400fe058 // Interrupt status register\r
+#define SYSCTL_RESC 0x400fe05c // Reset cause register\r
+#define SYSCTL_RCC 0x400fe060 // Run-mode clock config register\r
+#define SYSCTL_PLLCFG 0x400fe064 // PLL configuration register\r
+#define SYSCTL_RCC2 0x400fe070 // Run-mode clock config register 2\r
+#define SYSCTL_RCGC0 0x400fe100 // Run-mode clock gating register 0\r
+#define SYSCTL_RCGC1 0x400fe104 // Run-mode clock gating register 1\r
+#define SYSCTL_RCGC2 0x400fe108 // Run-mode clock gating register 2\r
+#define SYSCTL_SCGC0 0x400fe110 // Sleep-mode clock gating reg 0\r
+#define SYSCTL_SCGC1 0x400fe114 // Sleep-mode clock gating reg 1\r
+#define SYSCTL_SCGC2 0x400fe118 // Sleep-mode clock gating reg 2\r
+#define SYSCTL_DCGC0 0x400fe120 // Deep Sleep-mode clock gate reg 0\r
+#define SYSCTL_DCGC1 0x400fe124 // Deep Sleep-mode clock gate reg 1\r
+#define SYSCTL_DCGC2 0x400fe128 // Deep Sleep-mode clock gate reg 2\r
+#define SYSCTL_DSLPCLKCFG 0x400fe144 // Deep Sleep-mode clock config reg\r
+#define SYSCTL_CLKVCLR 0x400fe150 // Clock verifcation clear register\r
+#define SYSCTL_LDOARST 0x400fe160 // LDO reset control register\r
+#define SYSCTL_USER0 0x400fe1e0 // NV User Register 0\r
+#define SYSCTL_USER1 0x400fe1e4 // NV User Register 1\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_DID0 register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_DID0_VER_MASK 0x70000000 // DID0 version mask\r
+#define SYSCTL_DID0_VER_0 0x00000000 // DID0 version 0\r
+#define SYSCTL_DID0_VER_1 0x10000000 // DID0 version 1\r
+#define SYSCTL_DID0_CLASS_MASK 0x00FF0000 // Device Class\r
+#define SYSCTL_DID0_CLASS_SANDSTORM 0x00000000 // LM3Snnn Sandstorm Device\r
+#define SYSCTL_DID0_CLASS_FURY 0x00010000 // LM3Snnnn Fury Device\r
+#define SYSCTL_DID0_MAJ_MASK 0x0000FF00 // Major revision mask\r
+#define SYSCTL_DID0_MAJ_A 0x00000000 // Major revision A\r
+#define SYSCTL_DID0_MAJ_B 0x00000100 // Major revision B\r
+#define SYSCTL_DID0_MAJ_C 0x00000200 // Major revision C\r
+#define SYSCTL_DID0_MIN_MASK 0x000000FF // Minor revision mask\r
+#define SYSCTL_DID0_MIN_0 0x00000000 // Minor revision 0\r
+#define SYSCTL_DID0_MIN_1 0x00000001 // Minor revision 1\r
+#define SYSCTL_DID0_MIN_2 0x00000002 // Minor revision 2\r
+#define SYSCTL_DID0_MIN_3 0x00000003 // Minor revision 3\r
+#define SYSCTL_DID0_MIN_4 0x00000004 // Minor revision 4\r
+#define SYSCTL_DID0_MIN_5 0x00000005 // Minor revision 5\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_DID1 register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_DID1_VER_MASK 0xF0000000 // Register version mask\r
+#define SYSCTL_DID1_FAM_MASK 0x0F000000 // Family mask\r
+#define SYSCTL_DID1_FAM_S 0x00000000 // Stellaris family\r
+#define SYSCTL_DID1_PRTNO_MASK 0x00FF0000 // Part number mask\r
+#define SYSCTL_DID1_PRTNO_101 0x00010000 // LM3S101\r
+#define SYSCTL_DID1_PRTNO_102 0x00020000 // LM3S102\r
+#define SYSCTL_DID1_PRTNO_301 0x00110000 // LM3S301\r
+#define SYSCTL_DID1_PRTNO_310 0x00120000 // LM3S310\r
+#define SYSCTL_DID1_PRTNO_315 0x00130000 // LM3S315\r
+#define SYSCTL_DID1_PRTNO_316 0x00140000 // LM3S316\r
+#define SYSCTL_DID1_PRTNO_317 0x00170000 // LM3S317\r
+#define SYSCTL_DID1_PRTNO_328 0x00150000 // LM3S328\r
+#define SYSCTL_DID1_PRTNO_601 0x00210000 // LM3S601\r
+#define SYSCTL_DID1_PRTNO_610 0x00220000 // LM3S610\r
+#define SYSCTL_DID1_PRTNO_611 0x00230000 // LM3S611\r
+#define SYSCTL_DID1_PRTNO_612 0x00240000 // LM3S612\r
+#define SYSCTL_DID1_PRTNO_613 0x00250000 // LM3S613\r
+#define SYSCTL_DID1_PRTNO_615 0x00260000 // LM3S615\r
+#define SYSCTL_DID1_PRTNO_617 0x00280000 // LM3S617\r
+#define SYSCTL_DID1_PRTNO_618 0x00290000 // LM3S618\r
+#define SYSCTL_DID1_PRTNO_628 0x00270000 // LM3S628\r
+#define SYSCTL_DID1_PRTNO_801 0x00310000 // LM3S801\r
+#define SYSCTL_DID1_PRTNO_811 0x00320000 // LM3S811\r
+#define SYSCTL_DID1_PRTNO_812 0x00330000 // LM3S812\r
+#define SYSCTL_DID1_PRTNO_815 0x00340000 // LM3S815\r
+#define SYSCTL_DID1_PRTNO_817 0x00360000 // LM3S817\r
+#define SYSCTL_DID1_PRTNO_818 0x00370000 // LM3S818\r
+#define SYSCTL_DID1_PRTNO_828 0x00350000 // LM3S828\r
+#define SYSCTL_DID1_PRTNO_2110 0x00510000 // LM3S2110\r
+#define SYSCTL_DID1_PRTNO_2139 0x00840000 // LM3S2139\r
+#define SYSCTL_DID1_PRTNO_2410 0x00A20000 // LM3S2410\r
+#define SYSCTL_DID1_PRTNO_2412 0x00590000 // LM3S2412\r
+#define SYSCTL_DID1_PRTNO_2432 0x00560000 // LM3S2432\r
+#define SYSCTL_DID1_PRTNO_2533 0x005A0000 // LM3S2533\r
+#define SYSCTL_DID1_PRTNO_2620 0x00570000 // LM3S2620\r
+#define SYSCTL_DID1_PRTNO_2637 0x00850000 // LM3S2637\r
+#define SYSCTL_DID1_PRTNO_2651 0x00530000 // LM3S2651\r
+#define SYSCTL_DID1_PRTNO_2730 0x00A40000 // LM3S2730\r
+#define SYSCTL_DID1_PRTNO_2739 0x00520000 // LM3S2739\r
+#define SYSCTL_DID1_PRTNO_2939 0x00540000 // LM3S2939\r
+#define SYSCTL_DID1_PRTNO_2948 0x008F0000 // LM3S2948\r
+#define SYSCTL_DID1_PRTNO_2950 0x00580000 // LM3S2950\r
+#define SYSCTL_DID1_PRTNO_2965 0x00550000 // LM3S2965\r
+#define SYSCTL_DID1_PRTNO_6100 0x00A10000 // LM3S6100\r
+#define SYSCTL_DID1_PRTNO_6110 0x00740000 // LM3S6110\r
+#define SYSCTL_DID1_PRTNO_6420 0x00A50000 // LM3S6420\r
+#define SYSCTL_DID1_PRTNO_6422 0x00820000 // LM3S6422\r
+#define SYSCTL_DID1_PRTNO_6432 0x00750000 // LM3S6432\r
+#define SYSCTL_DID1_PRTNO_6610 0x00710000 // LM3S6610\r
+#define SYSCTL_DID1_PRTNO_6633 0x00830000 // LM3S6633\r
+#define SYSCTL_DID1_PRTNO_6637 0x008B0000 // LM3S6637\r
+#define SYSCTL_DID1_PRTNO_6730 0x00A30000 // LM3S6730\r
+#define SYSCTL_DID1_PRTNO_6938 0x00890000 // LM3S6938\r
+#define SYSCTL_DID1_PRTNO_6952 0x00780000 // LM3S6952\r
+#define SYSCTL_DID1_PRTNO_6965 0x00730000 // LM3S6965\r
+#define SYSCTL_DID1_PINCNT_MASK 0x0000E000 // Pin count\r
+#define SYSCTL_DID1_PINCNT_100 0x00004000 // 100 pin package\r
+#define SYSCTL_DID1_TEMP_MASK 0x000000E0 // Temperature range mask\r
+#define SYSCTL_DID1_TEMP_C 0x00000000 // Commercial temp range (0..70C)\r
+#define SYSCTL_DID1_TEMP_I 0x00000020 // Industrial temp range (-40..85C)\r
+#define SYSCTL_DID1_PKG_MASK 0x00000018 // Package mask\r
+#define SYSCTL_DID1_PKG_28SOIC 0x00000000 // 28-pin SOIC\r
+#define SYSCTL_DID1_PKG_48QFP 0x00000008 // 48-pin QFP\r
+#define SYSCTL_DID1_ROHS 0x00000004 // Part is RoHS compliant\r
+#define SYSCTL_DID1_QUAL_MASK 0x00000003 // Qualification status mask\r
+#define SYSCTL_DID1_QUAL_ES 0x00000000 // Engineering sample (unqualified)\r
+#define SYSCTL_DID1_QUAL_PP 0x00000001 // Pilot production (unqualified)\r
+#define SYSCTL_DID1_QUAL_FQ 0x00000002 // Fully qualified\r
+#define SYSCTL_DID1_PRTNO_SHIFT 16\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_DC0 register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_DC0_SRAMSZ_MASK 0xFFFF0000 // SRAM size mask\r
+#define SYSCTL_DC0_SRAMSZ_2KB 0x00070000 // 2 KB of SRAM\r
+#define SYSCTL_DC0_SRAMSZ_4KB 0x000F0000 // 4 KB of SRAM\r
+#define SYSCTL_DC0_SRAMSZ_8KB 0x001F0000 // 8 KB of SRAM\r
+#define SYSCTL_DC0_SRAMSZ_16KB 0x003F0000 // 16 KB of SRAM\r
+#define SYSCTL_DC0_SRAMSZ_32KB 0x007F0000 // 32 KB of SRAM\r
+#define SYSCTL_DC0_SRAMSZ_64KB 0x00FF0000 // 64 KB of SRAM\r
+#define SYSCTL_DC0_FLASHSZ_MASK 0x0000FFFF // Flash size mask\r
+#define SYSCTL_DC0_FLASHSZ_8KB 0x00000003 // 8 KB of flash\r
+#define SYSCTL_DC0_FLASHSZ_16KB 0x00000007 // 16 KB of flash\r
+#define SYSCTL_DC0_FLASHSZ_32KB 0x0000000F // 32 KB of flash\r
+#define SYSCTL_DC0_FLASHSZ_64KB 0x0000001F // 64 KB of flash\r
+#define SYSCTL_DC0_FLASHSZ_96KB 0x0000002F // 96 KB of flash\r
+#define SYSCTL_DC0_FLASHSZ_128K 0x0000003F // 128 KB of flash\r
+#define SYSCTL_DC0_FLASHSZ_256K 0x0000007F // 256 KB of flash\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_DC1 register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_DC1_CAN1 0x02000000 // CAN1 module present\r
+#define SYSCTL_DC1_CAN0 0x01000000 // CAN0 module present\r
+#define SYSCTL_DC1_PWM 0x00100000 // PWM module present\r
+#define SYSCTL_DC1_ADC 0x00010000 // ADC module present\r
+#define SYSCTL_DC1_SYSDIV_MASK 0x0000F000 // Minimum system divider mask\r
+#define SYSCTL_DC1_ADCSPD_MASK 0x00000F00 // ADC speed mask\r
+#define SYSCTL_DC1_ADCSPD_1M 0x00000300 // 1Msps ADC\r
+#define SYSCTL_DC1_ADCSPD_500K 0x00000200 // 500Ksps ADC\r
+#define SYSCTL_DC1_ADCSPD_250K 0x00000100 // 250Ksps ADC\r
+#define SYSCTL_DC1_ADCSPD_125K 0x00000000 // 125Ksps ADC\r
+#define SYSCTL_DC1_MPU 0x00000080 // Cortex M3 MPU present\r
+#define SYSCTL_DC1_HIB 0x00000040 // Hibernation module present\r
+#define SYSCTL_DC1_TEMP 0x00000020 // Temperature sensor present\r
+#define SYSCTL_DC1_PLL 0x00000010 // PLL present\r
+#define SYSCTL_DC1_WDOG 0x00000008 // Watchdog present\r
+#define SYSCTL_DC1_SWO 0x00000004 // Serial wire output present\r
+#define SYSCTL_DC1_SWD 0x00000002 // Serial wire debug present\r
+#define SYSCTL_DC1_JTAG 0x00000001 // JTAG debug present\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_DC2 register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_DC2_COMP2 0x04000000 // Analog comparator 2 present\r
+#define SYSCTL_DC2_COMP1 0x02000000 // Analog comparator 1 present\r
+#define SYSCTL_DC2_COMP0 0x01000000 // Analog comparator 0 present\r
+#define SYSCTL_DC2_TIMER3 0x00080000 // Timer 3 present\r
+#define SYSCTL_DC2_TIMER2 0x00040000 // Timer 2 present\r
+#define SYSCTL_DC2_TIMER1 0x00020000 // Timer 1 present\r
+#define SYSCTL_DC2_TIMER0 0x00010000 // Timer 0 present\r
+#define SYSCTL_DC2_I2C1 0x00002000 // I2C 1 present\r
+#define SYSCTL_DC2_I2C0 0x00001000 // I2C 0 present\r
+#ifndef DEPRECATED\r
+#define SYSCTL_DC2_I2C 0x00001000 // I2C present\r
+#endif\r
+#define SYSCTL_DC2_QEI1 0x00000200 // QEI 1 present\r
+#define SYSCTL_DC2_QEI0 0x00000100 // QEI 0 present\r
+#ifndef DEPRECATED\r
+#define SYSCTL_DC2_QEI 0x00000100 // QEI present\r
+#endif\r
+#define SYSCTL_DC2_SSI1 0x00000020 // SSI 1 present\r
+#define SYSCTL_DC2_SSI0 0x00000010 // SSI 0 present\r
+#ifndef DEPRECATED\r
+#define SYSCTL_DC2_SSI 0x00000010 // SSI present\r
+#endif\r
+#define SYSCTL_DC2_UART2 0x00000004 // UART 2 present\r
+#define SYSCTL_DC2_UART1 0x00000002 // UART 1 present\r
+#define SYSCTL_DC2_UART0 0x00000001 // UART 0 present\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_DC3 register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_DC3_32KHZ 0x80000000 // 32kHz pin present\r
+#define SYSCTL_DC3_CCP5 0x20000000 // CCP5 pin present\r
+#define SYSCTL_DC3_CCP4 0x10000000 // CCP4 pin present\r
+#define SYSCTL_DC3_CCP3 0x08000000 // CCP3 pin present\r
+#define SYSCTL_DC3_CCP2 0x04000000 // CCP2 pin present\r
+#define SYSCTL_DC3_CCP1 0x02000000 // CCP1 pin present\r
+#define SYSCTL_DC3_CCP0 0x01000000 // CCP0 pin present\r
+#define SYSCTL_DC3_ADC7 0x00800000 // ADC7 pin present\r
+#define SYSCTL_DC3_ADC6 0x00400000 // ADC6 pin present\r
+#define SYSCTL_DC3_ADC5 0x00200000 // ADC5 pin present\r
+#define SYSCTL_DC3_ADC4 0x00100000 // ADC4 pin present\r
+#define SYSCTL_DC3_ADC3 0x00080000 // ADC3 pin present\r
+#define SYSCTL_DC3_ADC2 0x00040000 // ADC2 pin present\r
+#define SYSCTL_DC3_ADC1 0x00020000 // ADC1 pin present\r
+#define SYSCTL_DC3_ADC0 0x00010000 // ADC0 pin present\r
+#define SYSCTL_DC3_MC_FAULT0 0x00008000 // MC0 fault pin present\r
+#define SYSCTL_DC3_C2O 0x00004000 // C2o pin present\r
+#define SYSCTL_DC3_C2PLUS 0x00002000 // C2+ pin present\r
+#define SYSCTL_DC3_C2MINUS 0x00001000 // C2- pin present\r
+#define SYSCTL_DC3_C1O 0x00000800 // C1o pin present\r
+#define SYSCTL_DC3_C1PLUS 0x00000400 // C1+ pin present\r
+#define SYSCTL_DC3_C1MINUS 0x00000200 // C1- pin present\r
+#define SYSCTL_DC3_C0O 0x00000100 // C0o pin present\r
+#define SYSCTL_DC3_C0PLUS 0x00000080 // C0+ pin present\r
+#define SYSCTL_DC3_C0MINUS 0x00000040 // C0- pin present\r
+#define SYSCTL_DC3_PWM5 0x00000020 // PWM5 pin present\r
+#define SYSCTL_DC3_PWM4 0x00000010 // PWM4 pin present\r
+#define SYSCTL_DC3_PWM3 0x00000008 // PWM3 pin present\r
+#define SYSCTL_DC3_PWM2 0x00000004 // PWM2 pin present\r
+#define SYSCTL_DC3_PWM1 0x00000002 // PWM1 pin present\r
+#define SYSCTL_DC3_PWM0 0x00000001 // PWM0 pin present\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_DC4 register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_DC4_ETH 0x50000000 // Ethernet present\r
+#define SYSCTL_DC4_GPIOH 0x00000080 // GPIO port H present\r
+#define SYSCTL_DC4_GPIOG 0x00000040 // GPIO port G present\r
+#define SYSCTL_DC4_GPIOF 0x00000020 // GPIO port F present\r
+#define SYSCTL_DC4_GPIOE 0x00000010 // GPIO port E present\r
+#define SYSCTL_DC4_GPIOD 0x00000008 // GPIO port D present\r
+#define SYSCTL_DC4_GPIOC 0x00000004 // GPIO port C present\r
+#define SYSCTL_DC4_GPIOB 0x00000002 // GPIO port B present\r
+#define SYSCTL_DC4_GPIOA 0x00000001 // GPIO port A present\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_PBORCTL register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_PBORCTL_BOR_MASK 0x0000FFFC // BOR wait timer\r
+#define SYSCTL_PBORCTL_BORIOR 0x00000002 // BOR interrupt or reset\r
+#define SYSCTL_PBORCTL_BORWT 0x00000001 // BOR wait and check for noise\r
+#define SYSCTL_PBORCTL_BOR_SH 2\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_LDOPCTL register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_LDOPCTL_MASK 0x0000003F // Voltage adjust mask\r
+#define SYSCTL_LDOPCTL_2_25V 0x00000005 // LDO output of 2.25V\r
+#define SYSCTL_LDOPCTL_2_30V 0x00000004 // LDO output of 2.30V\r
+#define SYSCTL_LDOPCTL_2_35V 0x00000003 // LDO output of 2.35V\r
+#define SYSCTL_LDOPCTL_2_40V 0x00000002 // LDO output of 2.40V\r
+#define SYSCTL_LDOPCTL_2_45V 0x00000001 // LDO output of 2.45V\r
+#define SYSCTL_LDOPCTL_2_50V 0x00000000 // LDO output of 2.50V\r
+#define SYSCTL_LDOPCTL_2_55V 0x0000001F // LDO output of 2.55V\r
+#define SYSCTL_LDOPCTL_2_60V 0x0000001E // LDO output of 2.60V\r
+#define SYSCTL_LDOPCTL_2_65V 0x0000001D // LDO output of 2.65V\r
+#define SYSCTL_LDOPCTL_2_70V 0x0000001C // LDO output of 2.70V\r
+#define SYSCTL_LDOPCTL_2_75V 0x0000001B // LDO output of 2.75V\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_SRCR0, SYSCTL_RCGC0,\r
+// SYSCTL_SCGC0, and SYSCTL_DCGC0 registers.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_SET0_CAN1 0x02000000 // CAN 1 module\r
+#define SYSCTL_SET0_CAN0 0x01000000 // CAN 0 module\r
+#define SYSCTL_SET0_PWM 0x00100000 // PWM module\r
+#define SYSCTL_SET0_ADC 0x00010000 // ADC module\r
+#define SYSCTL_SET0_ADCSPD_MASK 0x00000F00 // ADC speed mask\r
+#define SYSCTL_SET0_ADCSPD_1M 0x00000300 // 1Msps ADC\r
+#define SYSCTL_SET0_ADCSPD_500K 0x00000200 // 500Ksps ADC\r
+#define SYSCTL_SET0_ADCSPD_250K 0x00000100 // 250Ksps ADC\r
+#define SYSCTL_SET0_ADCSPD_125K 0x00000000 // 125Ksps ADC\r
+#define SYSCTL_SET0_HIB 0x00000040 // Hibernation module\r
+#define SYSCTL_SET0_WDOG 0x00000008 // Watchdog module\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_SRCR1, SYSCTL_RCGC1,\r
+// SYSCTL_SCGC1, and SYSCTL_DCGC1 registers.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_SET1_COMP2 0x04000000 // Analog comparator module 2\r
+#define SYSCTL_SET1_COMP1 0x02000000 // Analog comparator module 1\r
+#define SYSCTL_SET1_COMP0 0x01000000 // Analog comparator module 0\r
+#define SYSCTL_SET1_TIMER3 0x00080000 // Timer module 3\r
+#define SYSCTL_SET1_TIMER2 0x00040000 // Timer module 2\r
+#define SYSCTL_SET1_TIMER1 0x00020000 // Timer module 1\r
+#define SYSCTL_SET1_TIMER0 0x00010000 // Timer module 0\r
+#define SYSCTL_SET1_I2C1 0x00002000 // I2C module 1\r
+#define SYSCTL_SET1_I2C0 0x00001000 // I2C module 0\r
+#ifndef DEPRECATED\r
+#define SYSCTL_SET1_I2C 0x00001000 // I2C module\r
+#endif\r
+#define SYSCTL_SET1_QEI1 0x00000200 // QEI module 1\r
+#define SYSCTL_SET1_QEI0 0x00000100 // QEI module 0\r
+#ifndef DEPRECATED\r
+#define SYSCTL_SET1_QEI 0x00000100 // QEI module\r
+#endif\r
+#define SYSCTL_SET1_SSI1 0x00000020 // SSI module 1\r
+#define SYSCTL_SET1_SSI0 0x00000010 // SSI module 0\r
+#ifndef DEPRECATED\r
+#define SYSCTL_SET1_SSI 0x00000010 // SSI module\r
+#endif\r
+#define SYSCTL_SET1_UART2 0x00000004 // UART module 2\r
+#define SYSCTL_SET1_UART1 0x00000002 // UART module 1\r
+#define SYSCTL_SET1_UART0 0x00000001 // UART module 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_SRCR2, SYSCTL_RCGC2,\r
+// SYSCTL_SCGC2, and SYSCTL_DCGC2 registers.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_SET2_ETH 0x50000000 // ETH module\r
+#define SYSCTL_SET2_GPIOH 0x00000080 // GPIO H module\r
+#define SYSCTL_SET2_GPIOG 0x00000040 // GPIO G module\r
+#define SYSCTL_SET2_GPIOF 0x00000020 // GPIO F module\r
+#define SYSCTL_SET2_GPIOE 0x00000010 // GPIO E module\r
+#define SYSCTL_SET2_GPIOD 0x00000008 // GPIO D module\r
+#define SYSCTL_SET2_GPIOC 0x00000004 // GPIO C module\r
+#define SYSCTL_SET2_GPIOB 0x00000002 // GPIO B module\r
+#define SYSCTL_SET2_GPIOA 0x00000001 // GIPO A module\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_RIS, SYSCTL_IMC, and\r
+// SYSCTL_IMS registers.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_INT_PLL_LOCK 0x00000040 // PLL lock interrupt\r
+#define SYSCTL_INT_CUR_LIMIT 0x00000020 // Current limit interrupt\r
+#define SYSCTL_INT_IOSC_FAIL 0x00000010 // Internal oscillator failure int\r
+#define SYSCTL_INT_MOSC_FAIL 0x00000008 // Main oscillator failure int\r
+#define SYSCTL_INT_POR 0x00000004 // Power on reset interrupt\r
+#define SYSCTL_INT_BOR 0x00000002 // Brown out interrupt\r
+#define SYSCTL_INT_PLL_FAIL 0x00000001 // PLL failure interrupt\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_RESC register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_RESC_LDO 0x00000020 // LDO power OK lost reset\r
+#define SYSCTL_RESC_SW 0x00000010 // Software reset\r
+#define SYSCTL_RESC_WDOG 0x00000008 // Watchdog reset\r
+#define SYSCTL_RESC_BOR 0x00000004 // Brown-out reset\r
+#define SYSCTL_RESC_POR 0x00000002 // Power on reset\r
+#define SYSCTL_RESC_EXT 0x00000001 // External reset\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_RCC register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_RCC_ACG 0x08000000 // Automatic clock gating\r
+#define SYSCTL_RCC_SYSDIV_MASK 0x07800000 // System clock divider\r
+#define SYSCTL_RCC_SYSDIV_2 0x00800000 // System clock /2\r
+#define SYSCTL_RCC_SYSDIV_3 0x01000000 // System clock /3\r
+#define SYSCTL_RCC_SYSDIV_4 0x01800000 // System clock /4\r
+#define SYSCTL_RCC_SYSDIV_5 0x02000000 // System clock /5\r
+#define SYSCTL_RCC_SYSDIV_6 0x02800000 // System clock /6\r
+#define SYSCTL_RCC_SYSDIV_7 0x03000000 // System clock /7\r
+#define SYSCTL_RCC_SYSDIV_8 0x03800000 // System clock /8\r
+#define SYSCTL_RCC_SYSDIV_9 0x04000000 // System clock /9\r
+#define SYSCTL_RCC_SYSDIV_10 0x04800000 // System clock /10\r
+#define SYSCTL_RCC_SYSDIV_11 0x05000000 // System clock /11\r
+#define SYSCTL_RCC_SYSDIV_12 0x05800000 // System clock /12\r
+#define SYSCTL_RCC_SYSDIV_13 0x06000000 // System clock /13\r
+#define SYSCTL_RCC_SYSDIV_14 0x06800000 // System clock /14\r
+#define SYSCTL_RCC_SYSDIV_15 0x07000000 // System clock /15\r
+#define SYSCTL_RCC_SYSDIV_16 0x07800000 // System clock /16\r
+#define SYSCTL_RCC_USE_SYSDIV 0x00400000 // Use sytem clock divider\r
+#define SYSCTL_RCC_USE_PWMDIV 0x00100000 // Use PWM clock divider\r
+#define SYSCTL_RCC_PWMDIV_MASK 0x000E0000 // PWM clock divider\r
+#define SYSCTL_RCC_PWMDIV_2 0x00000000 // PWM clock /2\r
+#define SYSCTL_RCC_PWMDIV_4 0x00020000 // PWM clock /4\r
+#define SYSCTL_RCC_PWMDIV_8 0x00040000 // PWM clock /8\r
+#define SYSCTL_RCC_PWMDIV_16 0x00060000 // PWM clock /16\r
+#define SYSCTL_RCC_PWMDIV_32 0x00080000 // PWM clock /32\r
+#define SYSCTL_RCC_PWMDIV_64 0x000A0000 // PWM clock /64\r
+#define SYSCTL_RCC_PWRDN 0x00002000 // PLL power down\r
+#define SYSCTL_RCC_OE 0x00001000 // PLL output enable\r
+#define SYSCTL_RCC_BYPASS 0x00000800 // PLL bypass\r
+#define SYSCTL_RCC_PLLVER 0x00000400 // PLL verification timer enable\r
+#define SYSCTL_RCC_XTAL_MASK 0x000003C0 // Crystal attached to main osc\r
+#define SYSCTL_RCC_XTAL_3_57MHZ 0x00000100 // Using a 3.579545MHz crystal\r
+#define SYSCTL_RCC_XTAL_3_68MHz 0x00000140 // Using a 3.6864MHz crystal\r
+#define SYSCTL_RCC_XTAL_4MHz 0x00000180 // Using a 4MHz crystal\r
+#define SYSCTL_RCC_XTAL_4_09MHZ 0x000001C0 // Using a 4.096MHz crystal\r
+#define SYSCTL_RCC_XTAL_4_91MHZ 0x00000200 // Using a 4.9152MHz crystal\r
+#define SYSCTL_RCC_XTAL_5MHZ 0x00000240 // Using a 5MHz crystal\r
+#define SYSCTL_RCC_XTAL_5_12MHZ 0x00000280 // Using a 5.12MHz crystal\r
+#define SYSCTL_RCC_XTAL_6MHZ 0x000002C0 // Using a 6MHz crystal\r
+#define SYSCTL_RCC_XTAL_6_14MHZ 0x00000300 // Using a 6.144MHz crystal\r
+#define SYSCTL_RCC_XTAL_7_37MHZ 0x00000340 // Using a 7.3728MHz crystal\r
+#define SYSCTL_RCC_XTAL_8MHZ 0x00000380 // Using a 8MHz crystal\r
+#define SYSCTL_RCC_XTAL_8_19MHZ 0x000003C0 // Using a 8.192MHz crystal\r
+#define SYSCTL_RCC_OSCSRC_MASK 0x00000030 // Oscillator input select\r
+#define SYSCTL_RCC_OSCSRC_MAIN 0x00000000 // Use the main oscillator\r
+#define SYSCTL_RCC_OSCSRC_INT 0x00000010 // Use the internal oscillator\r
+#define SYSCTL_RCC_OSCSRC_INT4 0x00000020 // Use the internal oscillator / 4\r
+#define SYSCTL_RCC_IOSCVER 0x00000008 // Int. osc. verification timer en\r
+#define SYSCTL_RCC_MOSCVER 0x00000004 // Main osc. verification timer en\r
+#define SYSCTL_RCC_IOSCDIS 0x00000002 // Internal oscillator disable\r
+#define SYSCTL_RCC_MOSCDIS 0x00000001 // Main oscillator disable\r
+#define SYSCTL_RCC_SYSDIV_SHIFT 23 // Shift to the SYSDIV field\r
+#define SYSCTL_RCC_PWMDIV_SHIFT 17 // Shift to the PWMDIV field\r
+#define SYSCTL_RCC_XTAL_SHIFT 6 // Shift to the XTAL field\r
+#define SYSCTL_RCC_OSCSRC_SHIFT 4 // Shift to the OSCSRC field\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_PLLCFG register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_PLLCFG_OD_MASK 0x0000C000 // Output divider\r
+#define SYSCTL_PLLCFG_OD_1 0x00000000 // Output divider is 1\r
+#define SYSCTL_PLLCFG_OD_2 0x00004000 // Output divider is 2\r
+#define SYSCTL_PLLCFG_OD_4 0x00008000 // Output divider is 4\r
+#define SYSCTL_PLLCFG_F_MASK 0x00003FE0 // PLL multiplier\r
+#define SYSCTL_PLLCFG_R_MASK 0x0000001F // Input predivider\r
+#define SYSCTL_PLLCFG_F_SHIFT 5\r
+#define SYSCTL_PLLCFG_R_SHIFT 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_RCC2 register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_RCC2_USERCC2 0x80000000 // Use RCC2\r
+#define SYSCTL_RCC2_SYSDIV2_MSK 0x1F800000 // System clock divider\r
+#define SYSCTL_RCC2_SYSDIV2_2 0x00800000 // System clock /2\r
+#define SYSCTL_RCC2_SYSDIV2_3 0x01000000 // System clock /3\r
+#define SYSCTL_RCC2_SYSDIV2_4 0x01800000 // System clock /4\r
+#define SYSCTL_RCC2_SYSDIV2_5 0x02000000 // System clock /5\r
+#define SYSCTL_RCC2_SYSDIV2_6 0x02800000 // System clock /6\r
+#define SYSCTL_RCC2_SYSDIV2_7 0x03000000 // System clock /7\r
+#define SYSCTL_RCC2_SYSDIV2_8 0x03800000 // System clock /8\r
+#define SYSCTL_RCC2_SYSDIV2_9 0x04000000 // System clock /9\r
+#define SYSCTL_RCC2_SYSDIV2_10 0x04800000 // System clock /10\r
+#define SYSCTL_RCC2_SYSDIV2_11 0x05000000 // System clock /11\r
+#define SYSCTL_RCC2_SYSDIV2_12 0x05800000 // System clock /12\r
+#define SYSCTL_RCC2_SYSDIV2_13 0x06000000 // System clock /13\r
+#define SYSCTL_RCC2_SYSDIV2_14 0x06800000 // System clock /14\r
+#define SYSCTL_RCC2_SYSDIV2_15 0x07000000 // System clock /15\r
+#define SYSCTL_RCC2_SYSDIV2_16 0x07800000 // System clock /16\r
+#define SYSCTL_RCC2_SYSDIV2_17 0x08000000 // System clock /17\r
+#define SYSCTL_RCC2_SYSDIV2_18 0x08800000 // System clock /18\r
+#define SYSCTL_RCC2_SYSDIV2_19 0x09000000 // System clock /19\r
+#define SYSCTL_RCC2_SYSDIV2_20 0x09800000 // System clock /20\r
+#define SYSCTL_RCC2_SYSDIV2_21 0x0A000000 // System clock /21\r
+#define SYSCTL_RCC2_SYSDIV2_22 0x0A800000 // System clock /22\r
+#define SYSCTL_RCC2_SYSDIV2_23 0x0B000000 // System clock /23\r
+#define SYSCTL_RCC2_SYSDIV2_24 0x0B800000 // System clock /24\r
+#define SYSCTL_RCC2_SYSDIV2_25 0x0C000000 // System clock /25\r
+#define SYSCTL_RCC2_SYSDIV2_26 0x0C800000 // System clock /26\r
+#define SYSCTL_RCC2_SYSDIV2_27 0x0D000000 // System clock /27\r
+#define SYSCTL_RCC2_SYSDIV2_28 0x0D800000 // System clock /28\r
+#define SYSCTL_RCC2_SYSDIV2_29 0x0E000000 // System clock /29\r
+#define SYSCTL_RCC2_SYSDIV2_30 0x0E800000 // System clock /30\r
+#define SYSCTL_RCC2_SYSDIV2_31 0x0F000000 // System clock /31\r
+#define SYSCTL_RCC2_SYSDIV2_32 0x0F800000 // System clock /32\r
+#define SYSCTL_RCC2_SYSDIV2_33 0x10000000 // System clock /33\r
+#define SYSCTL_RCC2_SYSDIV2_34 0x10800000 // System clock /34\r
+#define SYSCTL_RCC2_SYSDIV2_35 0x11000000 // System clock /35\r
+#define SYSCTL_RCC2_SYSDIV2_36 0x11800000 // System clock /36\r
+#define SYSCTL_RCC2_SYSDIV2_37 0x12000000 // System clock /37\r
+#define SYSCTL_RCC2_SYSDIV2_38 0x12800000 // System clock /38\r
+#define SYSCTL_RCC2_SYSDIV2_39 0x13000000 // System clock /39\r
+#define SYSCTL_RCC2_SYSDIV2_40 0x13800000 // System clock /40\r
+#define SYSCTL_RCC2_SYSDIV2_41 0x14000000 // System clock /41\r
+#define SYSCTL_RCC2_SYSDIV2_42 0x14800000 // System clock /42\r
+#define SYSCTL_RCC2_SYSDIV2_43 0x15000000 // System clock /43\r
+#define SYSCTL_RCC2_SYSDIV2_44 0x15800000 // System clock /44\r
+#define SYSCTL_RCC2_SYSDIV2_45 0x16000000 // System clock /45\r
+#define SYSCTL_RCC2_SYSDIV2_46 0x16800000 // System clock /46\r
+#define SYSCTL_RCC2_SYSDIV2_47 0x17000000 // System clock /47\r
+#define SYSCTL_RCC2_SYSDIV2_48 0x17800000 // System clock /48\r
+#define SYSCTL_RCC2_SYSDIV2_49 0x18000000 // System clock /49\r
+#define SYSCTL_RCC2_SYSDIV2_50 0x18800000 // System clock /50\r
+#define SYSCTL_RCC2_SYSDIV2_51 0x19000000 // System clock /51\r
+#define SYSCTL_RCC2_SYSDIV2_52 0x19800000 // System clock /52\r
+#define SYSCTL_RCC2_SYSDIV2_53 0x1A000000 // System clock /53\r
+#define SYSCTL_RCC2_SYSDIV2_54 0x1A800000 // System clock /54\r
+#define SYSCTL_RCC2_SYSDIV2_55 0x1B000000 // System clock /55\r
+#define SYSCTL_RCC2_SYSDIV2_56 0x1B800000 // System clock /56\r
+#define SYSCTL_RCC2_SYSDIV2_57 0x1C000000 // System clock /57\r
+#define SYSCTL_RCC2_SYSDIV2_58 0x1C800000 // System clock /58\r
+#define SYSCTL_RCC2_SYSDIV2_59 0x1D000000 // System clock /59\r
+#define SYSCTL_RCC2_SYSDIV2_60 0x1D800000 // System clock /60\r
+#define SYSCTL_RCC2_SYSDIV2_61 0x1E000000 // System clock /61\r
+#define SYSCTL_RCC2_SYSDIV2_62 0x1E800000 // System clock /62\r
+#define SYSCTL_RCC2_SYSDIV2_63 0x1F000000 // System clock /63\r
+#define SYSCTL_RCC2_SYSDIV2_64 0x1F800000 // System clock /64\r
+#define SYSCTL_RCC2_PWRDN2 0x00002000 // PLL power down\r
+#define SYSCTL_RCC2_BYPASS2 0x00000800 // PLL bypass\r
+#define SYSCTL_RCC2_OSCSRC2_MSK 0x00000070 // Oscillator input select\r
+#define SYSCTL_RCC2_OSCSRC2_MO 0x00000000 // Use the main oscillator\r
+#define SYSCTL_RCC2_OSCSRC2_IO 0x00000010 // Use the internal oscillator\r
+#define SYSCTL_RCC2_OSCSRC2_IO4 0x00000020 // Use the internal oscillator / 4\r
+#define SYSCTL_RCC2_OSCSRC2_30 0x00000030 // Use the 30 KHz internal osc.\r
+#define SYSCTL_RCC2_OSCSRC2_32 0x00000070 // Use the 32 KHz external osc.\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_DSLPCLKCFG register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_DSLPCLKCFG_D_MSK 0x1f800000 // Deep sleep system clock override\r
+#define SYSCTL_DSLPCLKCFG_D_2 0x00800000 // System clock /2\r
+#define SYSCTL_DSLPCLKCFG_D_3 0x01000000 // System clock /3\r
+#define SYSCTL_DSLPCLKCFG_D_4 0x01800000 // System clock /4\r
+#define SYSCTL_DSLPCLKCFG_D_5 0x02000000 // System clock /5\r
+#define SYSCTL_DSLPCLKCFG_D_6 0x02800000 // System clock /6\r
+#define SYSCTL_DSLPCLKCFG_D_7 0x03000000 // System clock /7\r
+#define SYSCTL_DSLPCLKCFG_D_8 0x03800000 // System clock /8\r
+#define SYSCTL_DSLPCLKCFG_D_9 0x04000000 // System clock /9\r
+#define SYSCTL_DSLPCLKCFG_D_10 0x04800000 // System clock /10\r
+#define SYSCTL_DSLPCLKCFG_D_11 0x05000000 // System clock /11\r
+#define SYSCTL_DSLPCLKCFG_D_12 0x05800000 // System clock /12\r
+#define SYSCTL_DSLPCLKCFG_D_13 0x06000000 // System clock /13\r
+#define SYSCTL_DSLPCLKCFG_D_14 0x06800000 // System clock /14\r
+#define SYSCTL_DSLPCLKCFG_D_15 0x07000000 // System clock /15\r
+#define SYSCTL_DSLPCLKCFG_D_16 0x07800000 // System clock /16\r
+#define SYSCTL_DSLPCLKCFG_D_17 0x08000000 // System clock /17\r
+#define SYSCTL_DSLPCLKCFG_D_18 0x08800000 // System clock /18\r
+#define SYSCTL_DSLPCLKCFG_D_19 0x09000000 // System clock /19\r
+#define SYSCTL_DSLPCLKCFG_D_20 0x09800000 // System clock /20\r
+#define SYSCTL_DSLPCLKCFG_D_21 0x0A000000 // System clock /21\r
+#define SYSCTL_DSLPCLKCFG_D_22 0x0A800000 // System clock /22\r
+#define SYSCTL_DSLPCLKCFG_D_23 0x0B000000 // System clock /23\r
+#define SYSCTL_DSLPCLKCFG_D_24 0x0B800000 // System clock /24\r
+#define SYSCTL_DSLPCLKCFG_D_25 0x0C000000 // System clock /25\r
+#define SYSCTL_DSLPCLKCFG_D_26 0x0C800000 // System clock /26\r
+#define SYSCTL_DSLPCLKCFG_D_27 0x0D000000 // System clock /27\r
+#define SYSCTL_DSLPCLKCFG_D_28 0x0D800000 // System clock /28\r
+#define SYSCTL_DSLPCLKCFG_D_29 0x0E000000 // System clock /29\r
+#define SYSCTL_DSLPCLKCFG_D_30 0x0E800000 // System clock /30\r
+#define SYSCTL_DSLPCLKCFG_D_31 0x0F000000 // System clock /31\r
+#define SYSCTL_DSLPCLKCFG_D_32 0x0F800000 // System clock /32\r
+#define SYSCTL_DSLPCLKCFG_D_33 0x10000000 // System clock /33\r
+#define SYSCTL_DSLPCLKCFG_D_34 0x10800000 // System clock /34\r
+#define SYSCTL_DSLPCLKCFG_D_35 0x11000000 // System clock /35\r
+#define SYSCTL_DSLPCLKCFG_D_36 0x11800000 // System clock /36\r
+#define SYSCTL_DSLPCLKCFG_D_37 0x12000000 // System clock /37\r
+#define SYSCTL_DSLPCLKCFG_D_38 0x12800000 // System clock /38\r
+#define SYSCTL_DSLPCLKCFG_D_39 0x13000000 // System clock /39\r
+#define SYSCTL_DSLPCLKCFG_D_40 0x13800000 // System clock /40\r
+#define SYSCTL_DSLPCLKCFG_D_41 0x14000000 // System clock /41\r
+#define SYSCTL_DSLPCLKCFG_D_42 0x14800000 // System clock /42\r
+#define SYSCTL_DSLPCLKCFG_D_43 0x15000000 // System clock /43\r
+#define SYSCTL_DSLPCLKCFG_D_44 0x15800000 // System clock /44\r
+#define SYSCTL_DSLPCLKCFG_D_45 0x16000000 // System clock /45\r
+#define SYSCTL_DSLPCLKCFG_D_46 0x16800000 // System clock /46\r
+#define SYSCTL_DSLPCLKCFG_D_47 0x17000000 // System clock /47\r
+#define SYSCTL_DSLPCLKCFG_D_48 0x17800000 // System clock /48\r
+#define SYSCTL_DSLPCLKCFG_D_49 0x18000000 // System clock /49\r
+#define SYSCTL_DSLPCLKCFG_D_50 0x18800000 // System clock /50\r
+#define SYSCTL_DSLPCLKCFG_D_51 0x19000000 // System clock /51\r
+#define SYSCTL_DSLPCLKCFG_D_52 0x19800000 // System clock /52\r
+#define SYSCTL_DSLPCLKCFG_D_53 0x1A000000 // System clock /53\r
+#define SYSCTL_DSLPCLKCFG_D_54 0x1A800000 // System clock /54\r
+#define SYSCTL_DSLPCLKCFG_D_55 0x1B000000 // System clock /55\r
+#define SYSCTL_DSLPCLKCFG_D_56 0x1B800000 // System clock /56\r
+#define SYSCTL_DSLPCLKCFG_D_57 0x1C000000 // System clock /57\r
+#define SYSCTL_DSLPCLKCFG_D_58 0x1C800000 // System clock /58\r
+#define SYSCTL_DSLPCLKCFG_D_59 0x1D000000 // System clock /59\r
+#define SYSCTL_DSLPCLKCFG_D_60 0x1D800000 // System clock /60\r
+#define SYSCTL_DSLPCLKCFG_D_61 0x1E000000 // System clock /61\r
+#define SYSCTL_DSLPCLKCFG_D_62 0x1E800000 // System clock /62\r
+#define SYSCTL_DSLPCLKCFG_D_63 0x1F000000 // System clock /63\r
+#define SYSCTL_DSLPCLKCFG_D_64 0x1F800000 // System clock /64\r
+#define SYSCTL_DSLPCLKCFG_O_MSK 0x00000070 // Deep sleep oscillator override\r
+#define SYSCTL_DSLPCLKCFG_O_IGN 0x00000000 // Do not override\r
+#define SYSCTL_DSLPCLKCFG_O_IO 0x00000010 // Use the internal oscillator\r
+#define SYSCTL_DSLPCLKCFG_O_30 0x00000030 // Use the 30 KHz internal osc.\r
+#define SYSCTL_DSLPCLKCFG_O_32 0x00000070 // Use the 32 KHz external osc.\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_CLKVCLR register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_CLKVCLR_CLR 0x00000001 // Clear clock verification fault\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_LDOARST register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_LDOARST_ARST 0x00000001 // Allow LDO to reset device\r
+\r
+#endif // __HW_SYSCTL_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_timer.h - Defines and macros used when accessing the timer.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_TIMER_H__\r
+#define __HW_TIMER_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the offsets of the timer registers.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_O_CFG 0x00000000 // Configuration register\r
+#define TIMER_O_TAMR 0x00000004 // TimerA mode register\r
+#define TIMER_O_TBMR 0x00000008 // TimerB mode register\r
+#define TIMER_O_CTL 0x0000000C // Control register\r
+#define TIMER_O_IMR 0x00000018 // Interrupt mask register\r
+#define TIMER_O_RIS 0x0000001C // Interrupt status register\r
+#define TIMER_O_MIS 0x00000020 // Masked interrupt status reg.\r
+#define TIMER_O_ICR 0x00000024 // Interrupt clear register\r
+#define TIMER_O_TAILR 0x00000028 // TimerA interval load register\r
+#define TIMER_O_TBILR 0x0000002C // TimerB interval load register\r
+#define TIMER_O_TAMATCHR 0x00000030 // TimerA match register\r
+#define TIMER_O_TBMATCHR 0x00000034 // TimerB match register\r
+#define TIMER_O_TAPR 0x00000038 // TimerA prescale register\r
+#define TIMER_O_TBPR 0x0000003C // TimerB prescale register\r
+#define TIMER_O_TAPMR 0x00000040 // TimerA prescale match register\r
+#define TIMER_O_TBPMR 0x00000044 // TimerB prescale match register\r
+#define TIMER_O_TAR 0x00000048 // TimerA register\r
+#define TIMER_O_TBR 0x0000004C // TimerB register\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the reset values of the timer registers.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_RV_CFG 0x00000000 // Configuration register RV\r
+#define TIMER_RV_TAMR 0x00000000 // TimerA mode register RV\r
+#define TIMER_RV_TBMR 0x00000000 // TimerB mode register RV\r
+#define TIMER_RV_CTL 0x00000000 // Control register RV\r
+#define TIMER_RV_IMR 0x00000000 // Interrupt mask register RV\r
+#define TIMER_RV_RIS 0x00000000 // Interrupt status register RV\r
+#define TIMER_RV_MIS 0x00000000 // Masked interrupt status reg RV\r
+#define TIMER_RV_ICR 0x00000000 // Interrupt clear register RV\r
+#define TIMER_RV_TAILR 0xFFFFFFFF // TimerA interval load reg RV\r
+#define TIMER_RV_TBILR 0x0000FFFF // TimerB interval load reg RV\r
+#define TIMER_RV_TAMATCHR 0xFFFFFFFF // TimerA match register RV\r
+#define TIMER_RV_TBMATCHR 0x0000FFFF // TimerB match register RV\r
+#define TIMER_RV_TAPR 0x00000000 // TimerA prescale register RV\r
+#define TIMER_RV_TBPR 0x00000000 // TimerB prescale register RV\r
+#define TIMER_RV_TAPMR 0x00000000 // TimerA prescale match reg RV\r
+#define TIMER_RV_TBPMR 0x00000000 // TimerB prescale match regi RV\r
+#define TIMER_RV_TAR 0xFFFFFFFF // TimerA register RV\r
+#define TIMER_RV_TBR 0x0000FFFF // TimerB register RV\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the TIMER_CFG register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_CFG_CFG_MSK 0x00000007 // Configuration options mask\r
+#define TIMER_CFG_16_BIT 0x00000004 // Two 16 bit timers\r
+#define TIMER_CFG_32_BIT_RTC 0x00000001 // 32 bit RTC\r
+#define TIMER_CFG_32_BIT_TIMER 0x00000000 // 32 bit timer\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the TIMER_TnMR register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_TNMR_TNAMS 0x00000008 // Alternate mode select\r
+#define TIMER_TNMR_TNCMR 0x00000004 // Capture mode - count or time\r
+#define TIMER_TNMR_TNTMR_MSK 0x00000003 // Timer mode mask\r
+#define TIMER_TNMR_TNTMR_CAP 0x00000003 // Mode - capture\r
+#define TIMER_TNMR_TNTMR_PERIOD 0x00000002 // Mode - periodic\r
+#define TIMER_TNMR_TNTMR_1_SHOT 0x00000001 // Mode - one shot\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the TIMER_CTL register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_CTL_TBPWML 0x00004000 // TimerB PWM output level invert\r
+#define TIMER_CTL_TBOTE 0x00002000 // TimerB output trigger enable\r
+#define TIMER_CTL_TBEVENT_MSK 0x00000C00 // TimerB event mode mask\r
+#define TIMER_CTL_TBEVENT_BOTH 0x00000C00 // TimerB event mode - both edges\r
+#define TIMER_CTL_TBEVENT_NEG 0x00000400 // TimerB event mode - neg edge\r
+#define TIMER_CTL_TBEVENT_POS 0x00000000 // TimerB event mode - pos edge\r
+#define TIMER_CTL_TBSTALL 0x00000200 // TimerB stall enable\r
+#define TIMER_CTL_TBEN 0x00000100 // TimerB enable\r
+#define TIMER_CTL_TAPWML 0x00000040 // TimerA PWM output level invert\r
+#define TIMER_CTL_TAOTE 0x00000020 // TimerA output trigger enable\r
+#define TIMER_CTL_RTCEN 0x00000010 // RTC counter enable\r
+#define TIMER_CTL_TAEVENT_MSK 0x0000000C // TimerA event mode mask\r
+#define TIMER_CTL_TAEVENT_BOTH 0x0000000C // TimerA event mode - both edges\r
+#define TIMER_CTL_TAEVENT_NEG 0x00000004 // TimerA event mode - neg edge\r
+#define TIMER_CTL_TAEVENT_POS 0x00000000 // TimerA event mode - pos edge\r
+#define TIMER_CTL_TASTALL 0x00000002 // TimerA stall enable\r
+#define TIMER_CTL_TAEN 0x00000001 // TimerA enable\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the TIMER_IMR register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_IMR_CBEIM 0x00000400 // CaptureB event interrupt mask\r
+#define TIMER_IMR_CBMIM 0x00000200 // CaptureB match interrupt mask\r
+#define TIMER_IMR_TBTOIM 0x00000100 // TimerB time out interrupt mask\r
+#define TIMER_IMR_RTCIM 0x00000008 // RTC interrupt mask\r
+#define TIMER_IMR_CAEIM 0x00000004 // CaptureA event interrupt mask\r
+#define TIMER_IMR_CAMIM 0x00000002 // CaptureA match interrupt mask\r
+#define TIMER_IMR_TATOIM 0x00000001 // TimerA time out interrupt mask\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the TIMER_RIS register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_RIS_CBERIS 0x00000400 // CaptureB event raw int status\r
+#define TIMER_RIS_CBMRIS 0x00000200 // CaptureB match raw int status\r
+#define TIMER_RIS_TBTORIS 0x00000100 // TimerB time out raw int status\r
+#define TIMER_RIS_RTCRIS 0x00000008 // RTC raw int status\r
+#define TIMER_RIS_CAERIS 0x00000004 // CaptureA event raw int status\r
+#define TIMER_RIS_CAMRIS 0x00000002 // CaptureA match raw int status\r
+#define TIMER_RIS_TATORIS 0x00000001 // TimerA time out raw int status\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the TIMER_MIS register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_RIS_CBEMIS 0x00000400 // CaptureB event masked int status\r
+#define TIMER_RIS_CBMMIS 0x00000200 // CaptureB match masked int status\r
+#define TIMER_RIS_TBTOMIS 0x00000100 // TimerB time out masked int stat\r
+#define TIMER_RIS_RTCMIS 0x00000008 // RTC masked int status\r
+#define TIMER_RIS_CAEMIS 0x00000004 // CaptureA event masked int status\r
+#define TIMER_RIS_CAMMIS 0x00000002 // CaptureA match masked int status\r
+#define TIMER_RIS_TATOMIS 0x00000001 // TimerA time out masked int stat\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the TIMER_ICR register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_ICR_CBECINT 0x00000400 // CaptureB event interrupt clear\r
+#define TIMER_ICR_CBMCINT 0x00000200 // CaptureB match interrupt clear\r
+#define TIMER_ICR_TBTOCINT 0x00000100 // TimerB time out interrupt clear\r
+#define TIMER_ICR_RTCCINT 0x00000008 // RTC interrupt clear\r
+#define TIMER_ICR_CAECINT 0x00000004 // CaptureA event interrupt clear\r
+#define TIMER_ICR_CAMCINT 0x00000002 // CaptureA match interrupt clear\r
+#define TIMER_ICR_TATOCINT 0x00000001 // TimerA time out interrupt clear\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the TIMER_TAILR register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_TAILR_TAILRH 0xFFFF0000 // TimerB load val in 32 bit mode\r
+#define TIMER_TAILR_TAILRL 0x0000FFFF // TimerA interval load value\r
+\r
+//*****************************************************************************\r
+//\r
+// The following defines the bit fields in the TIMER_TBILR register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_TBILR_TBILRL 0x0000FFFF // TimerB interval load value\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the TIMER_TAMATCHR register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_TAMATCHR_TAMRH 0xFFFF0000 // TimerB match val in 32 bit mode\r
+#define TIMER_TAMATCHR_TAMRL 0x0000FFFF // TimerA match value\r
+\r
+//*****************************************************************************\r
+//\r
+// The following defines the bit fields in the TIMER_TBMATCHR register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_TBMATCHR_TBMRL 0x0000FFFF // TimerB match load value\r
+\r
+//*****************************************************************************\r
+//\r
+// The following defines the bit fields in the TIMER_TnPR register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_TNPR_TNPSR 0x000000FF // TimerN prescale value\r
+\r
+//*****************************************************************************\r
+//\r
+// The following defines the bit fields in the TIMER_TnPMR register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_TNPMR_TNPSMR 0x000000FF // TimerN prescale match value\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the TIMER_TAR register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_TAR_TARH 0xFFFF0000 // TimerB val in 32 bit mode\r
+#define TIMER_TAR_TARL 0x0000FFFF // TimerA value\r
+\r
+//*****************************************************************************\r
+//\r
+// The following defines the bit fields in the TIMER_TBR register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_TBR_TBRL 0x0000FFFF // TimerB value\r
+\r
+#endif // __HW_TIMER_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_types.h - Common types and macros.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_TYPES_H__\r
+#define __HW_TYPES_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// Define a boolean type, and values for true and false.\r
+//\r
+//*****************************************************************************\r
+typedef unsigned char tBoolean;\r
+\r
+#ifndef true\r
+#define true 1\r
+#endif\r
+\r
+#ifndef false\r
+#define false 0\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Macros for hardware access, both direct and via the bit-band region.\r
+//\r
+//*****************************************************************************\r
+#define HWREG(x) \\r
+ (*((volatile unsigned long *)(x)))\r
+#define HWREGH(x) \\r
+ (*((volatile unsigned short *)(x)))\r
+#define HWREGB(x) \\r
+ (*((volatile unsigned char *)(x)))\r
+#define HWREGBITW(x, b) \\r
+ HWREG(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \\r
+ (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2))\r
+#define HWREGBITH(x, b) \\r
+ HWREGH(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \\r
+ (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2))\r
+#define HWREGBITB(x, b) \\r
+ HWREGB(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \\r
+ (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2))\r
+\r
+//*****************************************************************************\r
+//\r
+// Helper Macros for determining silicon revisions, etc.\r
+//\r
+// These macros will be used by Driverlib at "run-time" to create necessary\r
+// conditional code blocks that will allow a single version of the Driverlib\r
+// "binary" code to support multiple(all) Stellaris silicon revisions.\r
+//\r
+// It is expected that these macros will be used inside of a standard 'C' \r
+// conditional block of code, e.g.\r
+//\r
+// if(DEVICE_IS_SANDSTORM())\r
+// {\r
+// do some Sandstorm specific code here.\r
+// }\r
+//\r
+// By default, these macros will be defined as run-time checks of the\r
+// appropriate register(s) to allow creation of run-time conditional code\r
+// blocks for a common DriverLib across the entire Stellaris family.\r
+//\r
+// However, if code-space optimization is required, these macros can be "hard-\r
+// coded" for a specific version of Stellaris silicon. Many compilers will\r
+// then detect the "hard-coded" conditionals, and appropriately optimize the\r
+// code blocks, eliminating any "unreachable" code. This would result in \r
+// a smaller Driverlib, thus producing a smaller final application size, but\r
+// at the cost of limiting the Driverlib binary to a specific Stellaris\r
+// silicon revision.\r
+//\r
+//*****************************************************************************\r
+#ifndef DEVICE_IS_SANDSTORM\r
+#define DEVICE_IS_SANDSTORM \\r
+ (((HWREG(SYSCTL_DID0) & SYSCTL_DID0_VER_MASK) == SYSCTL_DID0_VER_0) || \\r
+ (((HWREG(SYSCTL_DID0) & SYSCTL_DID0_VER_MASK) == SYSCTL_DID0_VER_1) && \\r
+ ((HWREG(SYSCTL_DID0) & SYSCTL_DID0_CLASS_MASK) == \\r
+ SYSCTL_DID0_CLASS_SANDSTORM)))\r
+#endif\r
+\r
+#ifndef DEVICE_IS_FURY\r
+#define DEVICE_IS_FURY \\r
+ (((HWREG(SYSCTL_DID0) & SYSCTL_DID0_VER_MASK) == SYSCTL_DID0_VER_1) && \\r
+ ((HWREG(SYSCTL_DID0) & SYSCTL_DID0_CLASS_MASK) == \\r
+ SYSCTL_DID0_CLASS_FURY))\r
+#endif\r
+\r
+#ifndef DEVICE_IS_REVA2\r
+#define DEVICE_IS_REVA2 \\r
+ (((HWREG(SYSCTL_DID0) & SYSCTL_DID0_MAJ_MASK) == SYSCTL_DID0_MAJ_A) && \\r
+ ((HWREG(SYSCTL_DID0) & SYSCTL_DID0_MIN_MASK) == SYSCTL_DID0_MIN_2))\r
+#endif\r
+\r
+#ifndef DEVICE_IS_REVC1\r
+#define DEVICE_IS_REVC1 \\r
+ (((HWREG(SYSCTL_DID0) & SYSCTL_DID0_MAJ_MASK) == SYSCTL_DID0_MAJ_C) && \\r
+ ((HWREG(SYSCTL_DID0) & SYSCTL_DID0_MIN_MASK) == SYSCTL_DID0_MIN_1))\r
+#endif\r
+\r
+#ifndef DEVICE_IS_REVC2\r
+#define DEVICE_IS_REVC2 \\r
+ (((HWREG(SYSCTL_DID0) & SYSCTL_DID0_MAJ_MASK) == SYSCTL_DID0_MAJ_C) && \\r
+ ((HWREG(SYSCTL_DID0) & SYSCTL_DID0_MIN_MASK) == SYSCTL_DID0_MIN_2))\r
+#endif\r
+\r
+#endif // __HW_TYPES_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_uart.h - Macros and defines used when accessing the UART hardware\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_UART_H__\r
+#define __HW_UART_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// UART Register Offsets.\r
+//\r
+//*****************************************************************************\r
+#define UART_O_DR 0x00000000 // Data Register\r
+#define UART_O_RSR 0x00000004 // Receive Status Register (read)\r
+#define UART_O_ECR 0x00000004 // Error Clear Register (write)\r
+#define UART_O_FR 0x00000018 // Flag Register (read only)\r
+#define UART_O_IBRD 0x00000024 // Integer Baud Rate Divisor Reg\r
+#define UART_O_FBRD 0x00000028 // Fractional Baud Rate Divisor Reg\r
+#define UART_O_LCR_H 0x0000002C // Line Control Register, HIGH byte\r
+#define UART_O_CTL 0x00000030 // Control Register\r
+#define UART_O_IFLS 0x00000034 // Interrupt FIFO Level Select Reg\r
+#define UART_O_IM 0x00000038 // Interrupt Mask Set/Clear Reg\r
+#define UART_O_RIS 0x0000003C // Raw Interrupt Status Register\r
+#define UART_O_MIS 0x00000040 // Masked Interrupt Status Register\r
+#define UART_O_ICR 0x00000044 // Interrupt Clear Register\r
+#define UART_O_PeriphID4 0x00000FD0 //\r
+#define UART_O_PeriphID5 0x00000FD4 //\r
+#define UART_O_PeriphID6 0x00000FD8 //\r
+#define UART_O_PeriphID7 0x00000FDC //\r
+#define UART_O_PeriphID0 0x00000FE0 //\r
+#define UART_O_PeriphID1 0x00000FE4 //\r
+#define UART_O_PeriphID2 0x00000FE8 //\r
+#define UART_O_PeriphID3 0x00000FEC //\r
+#define UART_O_PCellID0 0x00000FF0 //\r
+#define UART_O_PCellID1 0x00000FF4 //\r
+#define UART_O_PCellID2 0x00000FF8 //\r
+#define UART_O_PCellID3 0x00000FFC //\r
+\r
+//*****************************************************************************\r
+//\r
+// Data Register bits\r
+//\r
+//*****************************************************************************\r
+#define UART_DR_OE 0x00000800 // Overrun Error\r
+#define UART_DR_BE 0x00000400 // Break Error\r
+#define UART_DR_PE 0x00000200 // Parity Error\r
+#define UART_DR_FE 0x00000100 // Framing Error\r
+#define UART_DR_DATA_MASK 0x000000FF // UART data\r
+\r
+//*****************************************************************************\r
+//\r
+// Receive Status Register bits\r
+//\r
+//*****************************************************************************\r
+#define UART_RSR_OE 0x00000008 // Overrun Error\r
+#define UART_RSR_BE 0x00000004 // Break Error\r
+#define UART_RSR_PE 0x00000002 // Parity Error\r
+#define UART_RSR_FE 0x00000001 // Framing Error\r
+\r
+//*****************************************************************************\r
+//\r
+// Flag Register bits\r
+//\r
+//*****************************************************************************\r
+#define UART_FR_TXFE 0x00000080 // TX FIFO Empty\r
+#define UART_FR_RXFF 0x00000040 // RX FIFO Full\r
+#define UART_FR_TXFF 0x00000020 // TX FIFO Full\r
+#define UART_FR_RXFE 0x00000010 // RX FIFO Empty\r
+#define UART_FR_BUSY 0x00000008 // UART Busy\r
+\r
+//*****************************************************************************\r
+//\r
+// Integer baud-rate divisor\r
+//\r
+//*****************************************************************************\r
+#define UART_IBRD_DIVINT_MASK 0x0000FFFF // Integer baud-rate divisor\r
+\r
+//*****************************************************************************\r
+//\r
+// Fractional baud-rate divisor\r
+//\r
+//*****************************************************************************\r
+#define UART_FBRD_DIVFRAC_MASK 0x0000003F // Fractional baud-rate divisor\r
+\r
+//*****************************************************************************\r
+//\r
+// Line Control Register High bits\r
+//\r
+//*****************************************************************************\r
+#define UART_LCR_H_SPS 0x00000080 // Stick Parity Select\r
+#define UART_LCR_H_WLEN 0x00000060 // Word length\r
+#define UART_LCR_H_WLEN_8 0x00000060 // 8 bit data\r
+#define UART_LCR_H_WLEN_7 0x00000040 // 7 bit data\r
+#define UART_LCR_H_WLEN_6 0x00000020 // 6 bit data\r
+#define UART_LCR_H_WLEN_5 0x00000000 // 5 bit data\r
+#define UART_LCR_H_FEN 0x00000010 // Enable FIFO\r
+#define UART_LCR_H_STP2 0x00000008 // Two Stop Bits Select\r
+#define UART_LCR_H_EPS 0x00000004 // Even Parity Select\r
+#define UART_LCR_H_PEN 0x00000002 // Parity Enable\r
+#define UART_LCR_H_BRK 0x00000001 // Send Break\r
+\r
+//*****************************************************************************\r
+//\r
+// Control Register bits\r
+//\r
+//*****************************************************************************\r
+#define UART_CTL_RXE 0x00000200 // Receive Enable\r
+#define UART_CTL_TXE 0x00000100 // Transmit Enable\r
+#define UART_CTL_LBE 0x00000080 // Loopback Enable\r
+#define UART_CTL_SIRLP 0x00000004 // SIR (IrDA) Low Power Enable\r
+#define UART_CTL_SIREN 0x00000002 // SIR (IrDA) Enable\r
+#define UART_CTL_UARTEN 0x00000001 // UART Enable\r
+\r
+//*****************************************************************************\r
+//\r
+// Interrupt FIFO Level Select Register bits\r
+//\r
+//*****************************************************************************\r
+#define UART_IFLS_RX1_8 0x00000000 // 1/8 Full\r
+#define UART_IFLS_RX2_8 0x00000010 // 1/4 Full\r
+#define UART_IFLS_RX4_8 0x00000020 // 1/2 Full\r
+#define UART_IFLS_RX6_8 0x00000030 // 3/4 Full\r
+#define UART_IFLS_RX7_8 0x00000040 // 7/8 Full\r
+#define UART_IFLS_TX1_8 0x00000000 // 1/8 Full\r
+#define UART_IFLS_TX2_8 0x00000001 // 1/4 Full\r
+#define UART_IFLS_TX4_8 0x00000002 // 1/2 Full\r
+#define UART_IFLS_TX6_8 0x00000003 // 3/4 Full\r
+#define UART_IFLS_TX7_8 0x00000004 // 7/8 Full\r
+\r
+//*****************************************************************************\r
+//\r
+// Interrupt Mask Set/Clear Register bits\r
+//\r
+//*****************************************************************************\r
+#define UART_IM_OEIM 0x00000400 // Overrun Error Interrupt Mask\r
+#define UART_IM_BEIM 0x00000200 // Break Error Interrupt Mask\r
+#define UART_IM_PEIM 0x00000100 // Parity Error Interrupt Mask\r
+#define UART_IM_FEIM 0x00000080 // Framing Error Interrupt Mask\r
+#define UART_IM_RTIM 0x00000040 // Receive Timeout Interrupt Mask\r
+#define UART_IM_TXIM 0x00000020 // Transmit Interrupt Mask\r
+#define UART_IM_RXIM 0x00000010 // Receive Interrupt Mask\r
+\r
+//*****************************************************************************\r
+//\r
+// Raw Interrupt Status Register\r
+//\r
+//*****************************************************************************\r
+#define UART_RIS_OERIS 0x00000400 // Overrun Error Interrupt Status\r
+#define UART_RIS_BERIS 0x00000200 // Break Error Interrupt Status\r
+#define UART_RIS_PERIS 0x00000100 // Parity Error Interrupt Status\r
+#define UART_RIS_FERIS 0x00000080 // Framing Error Interrupt Status\r
+#define UART_RIS_RTRIS 0x00000040 // Receive Timeout Interrupt Status\r
+#define UART_RIS_TXRIS 0x00000020 // Transmit Interrupt Status\r
+#define UART_RIS_RXRIS 0x00000010 // Receive Interrupt Status\r
+\r
+//*****************************************************************************\r
+//\r
+// Masked Interrupt Status Register\r
+//\r
+//*****************************************************************************\r
+#define UART_MIS_OEMIS 0x00000400 // Overrun Error Interrupt Status\r
+#define UART_MIS_BEMIS 0x00000200 // Break Error Interrupt Status\r
+#define UART_MIS_PEMIS 0x00000100 // Parity Error Interrupt Status\r
+#define UART_MIS_FEMIS 0x00000080 // Framing Error Interrupt Status\r
+#define UART_MIS_RTMIS 0x00000040 // Receive Timeout Interrupt Status\r
+#define UART_MIS_TXMIS 0x00000020 // Transmit Interrupt Status\r
+#define UART_MIS_RXMIS 0x00000010 // Receive Interrupt Status\r
+\r
+//*****************************************************************************\r
+//\r
+// Interrupt Clear Register bits\r
+//\r
+//*****************************************************************************\r
+#define UART_ICR_OEIC 0x00000400 // Overrun Error Interrupt Clear\r
+#define UART_ICR_BEIC 0x00000200 // Break Error Interrupt Clear\r
+#define UART_ICR_PEIC 0x00000100 // Parity Error Interrupt Clear\r
+#define UART_ICR_FEIC 0x00000080 // Framing Error Interrupt Clear\r
+#define UART_ICR_RTIC 0x00000040 // Receive Timeout Interrupt Clear\r
+#define UART_ICR_TXIC 0x00000020 // Transmit Interrupt Clear\r
+#define UART_ICR_RXIC 0x00000010 // Receive Interrupt Clear\r
+\r
+#define UART_RSR_ANY (UART_RSR_OE | \\r
+ UART_RSR_BE | \\r
+ UART_RSR_PE | \\r
+ UART_RSR_FE)\r
+\r
+//*****************************************************************************\r
+//\r
+// Reset Values for UART Registers.\r
+//\r
+//*****************************************************************************\r
+#define UART_RV_DR 0x00000000\r
+#define UART_RV_RSR 0x00000000\r
+#define UART_RV_ECR 0x00000000\r
+#define UART_RV_FR 0x00000090\r
+#define UART_RV_IBRD 0x00000000\r
+#define UART_RV_FBRD 0x00000000\r
+#define UART_RV_LCR_H 0x00000000\r
+#define UART_RV_CTL 0x00000300\r
+#define UART_RV_IFLS 0x00000012\r
+#define UART_RV_IM 0x00000000\r
+#define UART_RV_RIS 0x00000000\r
+#define UART_RV_MIS 0x00000000\r
+#define UART_RV_ICR 0x00000000\r
+#define UART_RV_PeriphID4 0x00000000\r
+#define UART_RV_PeriphID5 0x00000000\r
+#define UART_RV_PeriphID6 0x00000000\r
+#define UART_RV_PeriphID7 0x00000000\r
+#define UART_RV_PeriphID0 0x00000011\r
+#define UART_RV_PeriphID1 0x00000000\r
+#define UART_RV_PeriphID2 0x00000018\r
+#define UART_RV_PeriphID3 0x00000001\r
+#define UART_RV_PCellID0 0x0000000D\r
+#define UART_RV_PCellID1 0x000000F0\r
+#define UART_RV_PCellID2 0x00000005\r
+#define UART_RV_PCellID3 0x000000B1\r
+\r
+#endif // __HW_UART_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_watchdog.h - Macros used when accessing the Watchdog Timer hardware.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_WATCHDOG_H__\r
+#define __HW_WATCHDOG_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the offsets of the Watchdog Timer registers.\r
+//\r
+//*****************************************************************************\r
+#define WDT_O_LOAD 0x00000000 // Load register\r
+#define WDT_O_VALUE 0x00000004 // Current value register\r
+#define WDT_O_CTL 0x00000008 // Control register\r
+#define WDT_O_ICR 0x0000000C // Interrupt clear register\r
+#define WDT_O_RIS 0x00000010 // Raw interrupt status register\r
+#define WDT_O_MIS 0x00000014 // Masked interrupt status register\r
+#define WDT_O_TEST 0x00000418 // Test register\r
+#define WDT_O_LOCK 0x00000C00 // Lock register\r
+#define WDT_O_PeriphID4 0x00000FD0 //\r
+#define WDT_O_PeriphID5 0x00000FD4 //\r
+#define WDT_O_PeriphID6 0x00000FD8 //\r
+#define WDT_O_PeriphID7 0x00000FDC //\r
+#define WDT_O_PeriphID0 0x00000FE0 //\r
+#define WDT_O_PeriphID1 0x00000FE4 //\r
+#define WDT_O_PeriphID2 0x00000FE8 //\r
+#define WDT_O_PeriphID3 0x00000FEC //\r
+#define WDT_O_PCellID0 0x00000FF0 //\r
+#define WDT_O_PCellID1 0x00000FF4 //\r
+#define WDT_O_PCellID2 0x00000FF8 //\r
+#define WDT_O_PCellID3 0x00000FFC //\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the WDT_CTL register.\r
+//\r
+//*****************************************************************************\r
+#define WDT_CTL_RESEN 0x00000002 // Enable reset output\r
+#define WDT_CTL_INTEN 0x00000001 // Enable the WDT counter and int\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the WDT_ISR, WDT_RIS, and WDT_MIS\r
+// registers.\r
+//\r
+//*****************************************************************************\r
+#define WDT_INT_TIMEOUT 0x00000001 // Watchdog timer expired\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the WDT_TEST register.\r
+//\r
+//*****************************************************************************\r
+#define WDT_TEST_STALL 0x00000100 // Watchdog stall enable\r
+#ifndef DEPRECATED\r
+#define WDT_TEST_STALL_EN 0x00000100 // Watchdog stall enable\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the WDT_LOCK register.\r
+//\r
+//*****************************************************************************\r
+#define WDT_LOCK_LOCKED 0x00000001 // Watchdog timer is locked\r
+#define WDT_LOCK_UNLOCKED 0x00000000 // Watchdog timer is unlocked\r
+#define WDT_LOCK_UNLOCK 0x1ACCE551 // Unlocks the watchdog timer\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the reset values for the WDT registers.\r
+//\r
+//*****************************************************************************\r
+#define WDT_RV_LOAD 0xFFFFFFFF // Load register\r
+#define WDT_RV_VALUE 0xFFFFFFFF // Current value register\r
+#define WDT_RV_CTL 0x00000000 // Control register\r
+#define WDT_RV_RIS 0x00000000 // Raw interrupt status register\r
+#define WDT_RV_MIS 0x00000000 // Masked interrupt status register\r
+#define WDT_RV_LOCK 0x00000000 // Lock register\r
+#define WDT_RV_PeriphID4 0x00000000 //\r
+#define WDT_RV_PeriphID5 0x00000000 //\r
+#define WDT_RV_PeriphID6 0x00000000 //\r
+#define WDT_RV_PeriphID7 0x00000000 //\r
+#define WDT_RV_PeriphID0 0x00000005 //\r
+#define WDT_RV_PeriphID1 0x00000018 //\r
+#define WDT_RV_PeriphID2 0x00000018 //\r
+#define WDT_RV_PeriphID3 0x00000001 //\r
+#define WDT_RV_PCellID0 0x0000000D //\r
+#define WDT_RV_PCellID1 0x000000F0 //\r
+#define WDT_RV_PCellID2 0x00000005 //\r
+#define WDT_RV_PCellID3 0x000000B1 //\r
+\r
+#endif // __HW_WATCHDOG_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// i2c.h - Prototypes for the I2C Driver.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __I2C_H__\r
+#define __I2C_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Defines for the API.\r
+//\r
+//*****************************************************************************\r
+//*****************************************************************************\r
+//\r
+// Interrupt defines.\r
+//\r
+//*****************************************************************************\r
+#define I2C_INT_MASTER 0x00000001\r
+#define I2C_INT_SLAVE 0x00000002\r
+\r
+//*****************************************************************************\r
+//\r
+// I2C Master commands.\r
+//\r
+//*****************************************************************************\r
+#define I2C_MASTER_CMD_SINGLE_SEND \\r
+ (I2C_MASTER_CS_STOP | I2C_MASTER_CS_START | I2C_MASTER_CS_RUN)\r
+#define I2C_MASTER_CMD_SINGLE_RECEIVE \\r
+ (I2C_MASTER_CS_STOP | I2C_MASTER_CS_START | I2C_MASTER_CS_RUN)\r
+#define I2C_MASTER_CMD_BURST_SEND_START \\r
+ (I2C_MASTER_CS_START | I2C_MASTER_CS_RUN)\r
+#define I2C_MASTER_CMD_BURST_SEND_CONT \\r
+ (I2C_MASTER_CS_RUN)\r
+#define I2C_MASTER_CMD_BURST_SEND_FINISH \\r
+ (I2C_MASTER_CS_STOP | I2C_MASTER_CS_RUN)\r
+#define I2C_MASTER_CMD_BURST_SEND_ERROR_STOP \\r
+ (I2C_MASTER_CS_STOP)\r
+#define I2C_MASTER_CMD_BURST_RECEIVE_START \\r
+ (I2C_MASTER_CS_ACK | I2C_MASTER_CS_START | I2C_MASTER_CS_RUN)\r
+#define I2C_MASTER_CMD_BURST_RECEIVE_CONT \\r
+ (I2C_MASTER_CS_ACK | I2C_MASTER_CS_RUN)\r
+#define I2C_MASTER_CMD_BURST_RECEIVE_FINISH \\r
+ (I2C_MASTER_CS_STOP | I2C_MASTER_CS_RUN)\r
+#define I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP \\r
+ (I2C_MASTER_CS_STOP | I2C_MASTER_CS_RUN)\r
+\r
+//*****************************************************************************\r
+//\r
+// I2C Master error status.\r
+//\r
+//*****************************************************************************\r
+#define I2C_MASTER_ERR_NONE 0\r
+#define I2C_MASTER_ERR_ADDR_ACK 0x00000004\r
+#define I2C_MASTER_ERR_DATA_ACK 0x00000008\r
+#define I2C_MASTER_ERR_ARB_LOST 0x00000010\r
+\r
+//*****************************************************************************\r
+//\r
+// I2C Slave action requests\r
+//\r
+//*****************************************************************************\r
+#define I2C_SLAVE_ACT_NONE 0\r
+#define I2C_SLAVE_ACT_RREQ 0x00000001 // Master has sent data\r
+#define I2C_SLAVE_ACT_TREQ 0x00000002 // Master has requested data\r
+\r
+//*****************************************************************************\r
+// Miscellaneous I2C driver definitions.\r
+//*****************************************************************************\r
+#define I2C_MASTER_MAX_RETRIES 1000 // Number of retries\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+extern void I2CIntRegister(unsigned long ulBase, void(fnHandler)(void));\r
+extern void I2CIntUnregister(unsigned long ulBase);\r
+extern tBoolean I2CMasterBusBusy(unsigned long ulBase);\r
+extern tBoolean I2CMasterBusy(unsigned long ulBase);\r
+extern void I2CMasterControl(unsigned long ulBase, unsigned long ulCmd);\r
+extern unsigned long I2CMasterDataGet(unsigned long ulBase);\r
+extern void I2CMasterDataPut(unsigned long ulBase, unsigned char ucData);\r
+extern void I2CMasterDisable(unsigned long ulBase);\r
+extern void I2CMasterEnable(unsigned long ulBase);\r
+extern unsigned long I2CMasterErr(unsigned long ulBase);\r
+extern void I2CMasterInit(unsigned long ulBase, tBoolean bFast);\r
+extern void I2CMasterIntClear(unsigned long ulBase);\r
+extern void I2CMasterIntDisable(unsigned long ulBase);\r
+extern void I2CMasterIntEnable(unsigned long ulBase);\r
+extern tBoolean I2CMasterIntStatus(unsigned long ulBase, tBoolean bMasked);\r
+extern void I2CMasterSlaveAddrSet(unsigned long ulBase,\r
+ unsigned char ucSlaveAddr,\r
+ tBoolean bReceive);\r
+extern unsigned long I2CSlaveDataGet(unsigned long ulBase);\r
+extern void I2CSlaveDataPut(unsigned long ulBase, unsigned char ucData);\r
+extern void I2CSlaveDisable(unsigned long ulBase);\r
+extern void I2CSlaveEnable(unsigned long ulBase);\r
+extern void I2CSlaveInit(unsigned long ulBase, unsigned char ucSlaveAddr);\r
+extern void I2CSlaveIntClear(unsigned long ulBase);\r
+extern void I2CSlaveIntDisable(unsigned long ulBase);\r
+extern void I2CSlaveIntEnable(unsigned long ulBase);\r
+extern tBoolean I2CSlaveIntStatus(unsigned long ulBase, tBoolean bMasked);\r
+extern unsigned long I2CSlaveStatus(unsigned long ulBase);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __I2C_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// interrupt.h - Prototypes for the NVIC Interrupt Controller Driver.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __INTERRUPT_H__\r
+#define __INTERRUPT_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+extern void IntMasterEnable(void);\r
+extern void IntMasterDisable(void);\r
+extern void IntRegister(unsigned long ulInterrupt, void (*pfnHandler)(void));\r
+extern void IntUnregister(unsigned long ulInterrupt);\r
+extern void IntPriorityGroupingSet(unsigned long ulBits);\r
+extern unsigned long IntPriorityGroupingGet(void);\r
+extern void IntPrioritySet(unsigned long ulInterrupt,\r
+ unsigned char ucPriority);\r
+extern long IntPriorityGet(unsigned long ulInterrupt);\r
+extern void IntEnable(unsigned long ulInterrupt);\r
+extern void IntDisable(unsigned long ulInterrupt);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __INTERRUPT_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// flash.h - Prototypes for the flash driver.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __FLASH_H__\r
+#define __FLASH_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to FlashProtectSet(), and returned by\r
+// FlashProtectGet().\r
+//\r
+//*****************************************************************************\r
+typedef enum\r
+{\r
+ FlashReadWrite, // Flash can be read and written\r
+ FlashReadOnly, // Flash can only be read\r
+ FlashExecuteOnly // Flash can only be executed\r
+}\r
+tFlashProtection;\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+extern unsigned long FlashUsecGet(void);\r
+extern void FlashUsecSet(unsigned long ulClocks);\r
+extern long FlashErase(unsigned long ulAddress);\r
+extern long FlashProgram(unsigned long *pulData, unsigned long ulAddress,\r
+ unsigned long ulCount);\r
+extern tFlashProtection FlashProtectGet(unsigned long ulAddress);\r
+extern long FlashProtectSet(unsigned long ulAddress,\r
+ tFlashProtection eProtect);\r
+extern long FlashProtectSave(void);\r
+extern long FlashUserGet(unsigned long *pulUser0, unsigned long *pulUser1);\r
+extern long FlashUserSet(unsigned long ulUser0, unsigned long ulUser1);\r
+extern long FlashUserSave(void);\r
+extern void FlashIntRegister(void (*pfnHandler)(void));\r
+extern void FlashIntUnregister(void);\r
+extern void FlashIntEnable(unsigned long ulIntFlags);\r
+extern void FlashIntDisable(unsigned long ulIntFlags);\r
+extern unsigned long FlashIntGetStatus(tBoolean bMasked);\r
+extern void FlashIntClear(unsigned long ulIntFlags);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __FLASH_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// timer.h - Prototypes for the timer module\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __TIMER_H__\r
+#define __TIMER_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to TimerConfigure as the ulConfig parameter.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_CFG_32_BIT_OS 0x00000001 // 32-bit one-shot timer\r
+#define TIMER_CFG_32_BIT_PER 0x00000002 // 32-bit periodic timer\r
+#define TIMER_CFG_32_RTC 0x01000000 // 32-bit RTC timer\r
+#define TIMER_CFG_16_BIT_PAIR 0x04000000 // Two 16-bit timers\r
+#define TIMER_CFG_A_ONE_SHOT 0x00000001 // Timer A one-shot timer\r
+#define TIMER_CFG_A_PERIODIC 0x00000002 // Timer A periodic timer\r
+#define TIMER_CFG_A_CAP_COUNT 0x00000003 // Timer A event counter\r
+#define TIMER_CFG_A_CAP_TIME 0x00000007 // Timer A event timer\r
+#define TIMER_CFG_A_PWM 0x0000000A // Timer A PWM output\r
+#define TIMER_CFG_B_ONE_SHOT 0x00000100 // Timer B one-shot timer\r
+#define TIMER_CFG_B_PERIODIC 0x00000200 // Timer B periodic timer\r
+#define TIMER_CFG_B_CAP_COUNT 0x00000300 // Timer B event counter\r
+#define TIMER_CFG_B_CAP_TIME 0x00000700 // Timer B event timer\r
+#define TIMER_CFG_B_PWM 0x00000A00 // Timer B PWM output\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to TimerIntEnable, TimerIntDisable, and\r
+// TimerIntClear as the ulIntFlags parameter, and returned from TimerIntStatus.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_CAPB_EVENT 0x00000400 // CaptureB event interrupt\r
+#define TIMER_CAPB_MATCH 0x00000200 // CaptureB match interrupt\r
+#define TIMER_TIMB_TIMEOUT 0x00000100 // TimerB time out interrupt\r
+#define TIMER_RTC_MATCH 0x00000008 // RTC interrupt mask\r
+#define TIMER_CAPA_EVENT 0x00000004 // CaptureA event interrupt\r
+#define TIMER_CAPA_MATCH 0x00000002 // CaptureA match interrupt\r
+#define TIMER_TIMA_TIMEOUT 0x00000001 // TimerA time out interrupt\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to TimerControlEvent as the ulEvent parameter.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_EVENT_POS_EDGE 0x00000000 // Count positive edges\r
+#define TIMER_EVENT_NEG_EDGE 0x00000404 // Count negative edges\r
+#define TIMER_EVENT_BOTH_EDGES 0x00000C0C // Count both edges\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to most of the timer APIs as the ulTimer\r
+// parameter.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_A 0x000000ff // Timer A\r
+#define TIMER_B 0x0000ff00 // Timer B\r
+#define TIMER_BOTH 0x0000ffff // Timer Both\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+extern void TimerEnable(unsigned long ulBase, unsigned long ulTimer);\r
+extern void TimerDisable(unsigned long ulBase, unsigned long ulTimer);\r
+extern void TimerConfigure(unsigned long ulBase, unsigned long ulConfig);\r
+extern void TimerControlLevel(unsigned long ulBase, unsigned long ulTimer,\r
+ tBoolean bInvert);\r
+extern void TimerControlTrigger(unsigned long ulBase, unsigned long ulTimer,\r
+ tBoolean bEnable);\r
+extern void TimerControlEvent(unsigned long ulBase, unsigned long ulTimer,\r
+ unsigned long ulEvent);\r
+extern void TimerControlStall(unsigned long ulBase, unsigned long ulTimer,\r
+ tBoolean bStall);\r
+extern void TimerRTCEnable(unsigned long ulBase);\r
+extern void TimerRTCDisable(unsigned long ulBase);\r
+extern void TimerPrescaleSet(unsigned long ulBase, unsigned long ulTimer,\r
+ unsigned long ulValue);\r
+extern unsigned long TimerPrescaleGet(unsigned long ulBase,\r
+ unsigned long ulTimer);\r
+extern void TimerPrescaleMatchSet(unsigned long ulBase, unsigned long ulTimer,\r
+ unsigned long ulValue);\r
+extern unsigned long TimerPrescaleMatchGet(unsigned long ulBase,\r
+ unsigned long ulTimer);\r
+extern void TimerLoadSet(unsigned long ulBase, unsigned long ulTimer,\r
+ unsigned long ulValue);\r
+extern unsigned long TimerLoadGet(unsigned long ulBase, unsigned long ulTimer);\r
+extern unsigned long TimerValueGet(unsigned long ulBase,\r
+ unsigned long ulTimer);\r
+extern void TimerMatchSet(unsigned long ulBase, unsigned long ulTimer,\r
+ unsigned long ulValue);\r
+extern unsigned long TimerMatchGet(unsigned long ulBase,\r
+ unsigned long ulTimer);\r
+extern void TimerIntRegister(unsigned long ulBase, unsigned long ulTimer,\r
+ void (*pfnHandler)(void));\r
+extern void TimerIntUnregister(unsigned long ulBase, unsigned long ulTimer);\r
+extern void TimerIntEnable(unsigned long ulBase, unsigned long ulIntFlags);\r
+extern void TimerIntDisable(unsigned long ulBase, unsigned long ulIntFlags);\r
+extern unsigned long TimerIntStatus(unsigned long ulBase, tBoolean bMasked);\r
+extern void TimerIntClear(unsigned long ulBase, unsigned long ulIntFlags);\r
+extern void TimerQuiesce(unsigned long ulBase);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __TIMER_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// osram128x64x4.c - Driver for the OSRAM 128x64x4 graphical OLED display.\r
+//\r
+// Copyright (c) 2006-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+//*****************************************************************************\r
+//\r
+//! \addtogroup ek_lm3sx965_api\r
+//! @{\r
+//\r
+//*****************************************************************************\r
+\r
+#include "hw_ssi.h"\r
+#include "hw_memmap.h"\r
+#include "hw_sysctl.h"\r
+#include "hw_types.h"\r
+#include "debug.h"\r
+#include "gpio.h"\r
+#include "ssi.h"\r
+#include "sysctl.h"\r
+#include "osram128x64x4.h"\r
+\r
+//*****************************************************************************\r
+//\r
+// Flag to indicate if SSI port is enabled for OSRAM usage.\r
+//\r
+//*****************************************************************************\r
+static volatile tBoolean g_bSSIEnabled = false;\r
+\r
+//*****************************************************************************\r
+//\r
+// Define the OSRAM 128x64x4 Remap Setting(s). This will be used in\r
+// several places in the code to switch between vertical and horizontal\r
+// address incrementing.\r
+//\r
+// The Remap Command (0xA0) takes one 8-bit parameter. The parameter is\r
+// defined as follows.\r
+//\r
+// Bit 7: Reserved\r
+// Bit 6: Disable(0)/Enable(1) COM Split Odd Even\r
+// When enabled, the COM signals are split Odd on one side, even on\r
+// the other. Otherwise, they are split 0-39 on one side, 40-79 on\r
+// the other.\r
+// Bit 5: Reserved\r
+// Bit 4: Disable(0)/Enable(1) COM Remap\r
+// When Enabled, ROW 0-79 map to COM 79-0 (i.e. reverse row order)\r
+// Bit 3: Reserved\r
+// Bit 2: Horizontal(0)/Vertical(1) Address Increment\r
+// When set, data RAM address will increment along the column rather\r
+// than along the row.\r
+// Bit 1: Disable(0)/Enable(1) Nibble Remap\r
+// When enabled, the upper and lower nibbles in the DATA bus for access\r
+// to the data RAM are swapped.\r
+// Bit 0: Disable(0)/Enable(1) Column Address Remap\r
+// When enabled, DATA RAM columns 0-63 are remapped to Segment Columns\r
+// 127-0.\r
+//\r
+//*****************************************************************************\r
+#define OSRAM_INIT_REMAP 0x52\r
+#define OSRAM_INIT_OFFSET 0x4C\r
+static const unsigned char g_pucOSRAM128x64x4VerticalInc[] = { 0xA0, 0x56 };\r
+static const unsigned char g_pucOSRAM128x64x4HorizontalInc[] = { 0xA0, 0x52 };\r
+\r
+//*****************************************************************************\r
+//\r
+// A 5x7 font (in a 6x8 cell, where the sixth column is omitted from this\r
+// table) for displaying text on the OLED display. The data is organized as\r
+// bytes from the left column to the right column, with each byte containing\r
+// the top row in the LSB and the bottom row in the MSB.\r
+//\r
+// Note: This is the same font data that is used in the EK-LM3S811\r
+// osram96x16x1 driver. The single bit-per-pixel is expaned in the StringDraw\r
+// function to the appropriate four bit-per-pixel gray scale format.\r
+//\r
+//*****************************************************************************\r
+static const unsigned char g_pucFont[96][5] =\r
+{\r
+ { 0x00, 0x00, 0x00, 0x00, 0x00 }, // " "\r
+ { 0x00, 0x00, 0x4f, 0x00, 0x00 }, // !\r
+ { 0x00, 0x07, 0x00, 0x07, 0x00 }, // "\r
+ { 0x14, 0x7f, 0x14, 0x7f, 0x14 }, // #\r
+ { 0x24, 0x2a, 0x7f, 0x2a, 0x12 }, // $\r
+ { 0x23, 0x13, 0x08, 0x64, 0x62 }, // %\r
+ { 0x36, 0x49, 0x55, 0x22, 0x50 }, // &\r
+ { 0x00, 0x05, 0x03, 0x00, 0x00 }, // '\r
+ { 0x00, 0x1c, 0x22, 0x41, 0x00 }, // (\r
+ { 0x00, 0x41, 0x22, 0x1c, 0x00 }, // )\r
+ { 0x14, 0x08, 0x3e, 0x08, 0x14 }, // *\r
+ { 0x08, 0x08, 0x3e, 0x08, 0x08 }, // +\r
+ { 0x00, 0x50, 0x30, 0x00, 0x00 }, // ,\r
+ { 0x08, 0x08, 0x08, 0x08, 0x08 }, // -\r
+ { 0x00, 0x60, 0x60, 0x00, 0x00 }, // .\r
+ { 0x20, 0x10, 0x08, 0x04, 0x02 }, // /\r
+ { 0x3e, 0x51, 0x49, 0x45, 0x3e }, // 0\r
+ { 0x00, 0x42, 0x7f, 0x40, 0x00 }, // 1\r
+ { 0x42, 0x61, 0x51, 0x49, 0x46 }, // 2\r
+ { 0x21, 0x41, 0x45, 0x4b, 0x31 }, // 3\r
+ { 0x18, 0x14, 0x12, 0x7f, 0x10 }, // 4\r
+ { 0x27, 0x45, 0x45, 0x45, 0x39 }, // 5\r
+ { 0x3c, 0x4a, 0x49, 0x49, 0x30 }, // 6\r
+ { 0x01, 0x71, 0x09, 0x05, 0x03 }, // 7\r
+ { 0x36, 0x49, 0x49, 0x49, 0x36 }, // 8\r
+ { 0x06, 0x49, 0x49, 0x29, 0x1e }, // 9\r
+ { 0x00, 0x36, 0x36, 0x00, 0x00 }, // :\r
+ { 0x00, 0x56, 0x36, 0x00, 0x00 }, // ;\r
+ { 0x08, 0x14, 0x22, 0x41, 0x00 }, // <\r
+ { 0x14, 0x14, 0x14, 0x14, 0x14 }, // =\r
+ { 0x00, 0x41, 0x22, 0x14, 0x08 }, // >\r
+ { 0x02, 0x01, 0x51, 0x09, 0x06 }, // ?\r
+ { 0x32, 0x49, 0x79, 0x41, 0x3e }, // @\r
+ { 0x7e, 0x11, 0x11, 0x11, 0x7e }, // A\r
+ { 0x7f, 0x49, 0x49, 0x49, 0x36 }, // B\r
+ { 0x3e, 0x41, 0x41, 0x41, 0x22 }, // C\r
+ { 0x7f, 0x41, 0x41, 0x22, 0x1c }, // D\r
+ { 0x7f, 0x49, 0x49, 0x49, 0x41 }, // E\r
+ { 0x7f, 0x09, 0x09, 0x09, 0x01 }, // F\r
+ { 0x3e, 0x41, 0x49, 0x49, 0x7a }, // G\r
+ { 0x7f, 0x08, 0x08, 0x08, 0x7f }, // H\r
+ { 0x00, 0x41, 0x7f, 0x41, 0x00 }, // I\r
+ { 0x20, 0x40, 0x41, 0x3f, 0x01 }, // J\r
+ { 0x7f, 0x08, 0x14, 0x22, 0x41 }, // K\r
+ { 0x7f, 0x40, 0x40, 0x40, 0x40 }, // L\r
+ { 0x7f, 0x02, 0x0c, 0x02, 0x7f }, // M\r
+ { 0x7f, 0x04, 0x08, 0x10, 0x7f }, // N\r
+ { 0x3e, 0x41, 0x41, 0x41, 0x3e }, // O\r
+ { 0x7f, 0x09, 0x09, 0x09, 0x06 }, // P\r
+ { 0x3e, 0x41, 0x51, 0x21, 0x5e }, // Q\r
+ { 0x7f, 0x09, 0x19, 0x29, 0x46 }, // R\r
+ { 0x46, 0x49, 0x49, 0x49, 0x31 }, // S\r
+ { 0x01, 0x01, 0x7f, 0x01, 0x01 }, // T\r
+ { 0x3f, 0x40, 0x40, 0x40, 0x3f }, // U\r
+ { 0x1f, 0x20, 0x40, 0x20, 0x1f }, // V\r
+ { 0x3f, 0x40, 0x38, 0x40, 0x3f }, // W\r
+ { 0x63, 0x14, 0x08, 0x14, 0x63 }, // X\r
+ { 0x07, 0x08, 0x70, 0x08, 0x07 }, // Y\r
+ { 0x61, 0x51, 0x49, 0x45, 0x43 }, // Z\r
+ { 0x00, 0x7f, 0x41, 0x41, 0x00 }, // [\r
+ { 0x02, 0x04, 0x08, 0x10, 0x20 }, // "\"\r
+ { 0x00, 0x41, 0x41, 0x7f, 0x00 }, // ]\r
+ { 0x04, 0x02, 0x01, 0x02, 0x04 }, // ^\r
+ { 0x40, 0x40, 0x40, 0x40, 0x40 }, // _\r
+ { 0x00, 0x01, 0x02, 0x04, 0x00 }, // `\r
+ { 0x20, 0x54, 0x54, 0x54, 0x78 }, // a\r
+ { 0x7f, 0x48, 0x44, 0x44, 0x38 }, // b\r
+ { 0x38, 0x44, 0x44, 0x44, 0x20 }, // c\r
+ { 0x38, 0x44, 0x44, 0x48, 0x7f }, // d\r
+ { 0x38, 0x54, 0x54, 0x54, 0x18 }, // e\r
+ { 0x08, 0x7e, 0x09, 0x01, 0x02 }, // f\r
+ { 0x0c, 0x52, 0x52, 0x52, 0x3e }, // g\r
+ { 0x7f, 0x08, 0x04, 0x04, 0x78 }, // h\r
+ { 0x00, 0x44, 0x7d, 0x40, 0x00 }, // i\r
+ { 0x20, 0x40, 0x44, 0x3d, 0x00 }, // j\r
+ { 0x7f, 0x10, 0x28, 0x44, 0x00 }, // k\r
+ { 0x00, 0x41, 0x7f, 0x40, 0x00 }, // l\r
+ { 0x7c, 0x04, 0x18, 0x04, 0x78 }, // m\r
+ { 0x7c, 0x08, 0x04, 0x04, 0x78 }, // n\r
+ { 0x38, 0x44, 0x44, 0x44, 0x38 }, // o\r
+ { 0x7c, 0x14, 0x14, 0x14, 0x08 }, // p\r
+ { 0x08, 0x14, 0x14, 0x18, 0x7c }, // q\r
+ { 0x7c, 0x08, 0x04, 0x04, 0x08 }, // r\r
+ { 0x48, 0x54, 0x54, 0x54, 0x20 }, // s\r
+ { 0x04, 0x3f, 0x44, 0x40, 0x20 }, // t\r
+ { 0x3c, 0x40, 0x40, 0x20, 0x7c }, // u\r
+ { 0x1c, 0x20, 0x40, 0x20, 0x1c }, // v\r
+ { 0x3c, 0x40, 0x30, 0x40, 0x3c }, // w\r
+ { 0x44, 0x28, 0x10, 0x28, 0x44 }, // x\r
+ { 0x0c, 0x50, 0x50, 0x50, 0x3c }, // y\r
+ { 0x44, 0x64, 0x54, 0x4c, 0x44 }, // z\r
+ { 0x00, 0x08, 0x36, 0x41, 0x00 }, // {\r
+ { 0x00, 0x00, 0x7f, 0x00, 0x00 }, // |\r
+ { 0x00, 0x41, 0x36, 0x08, 0x00 }, // }\r
+ { 0x02, 0x01, 0x02, 0x04, 0x02 }, // ~\r
+ { 0x02, 0x01, 0x02, 0x04, 0x02 }, // ~\r
+};\r
+\r
+//*****************************************************************************\r
+//\r
+// The sequence of commands used to initialize the SSD0303 controller. Each\r
+// command is described as follows: there is a byte specifying the number of\r
+// bytes in the command sequence, followed by that many bytes of command data.\r
+// Note: This initialization sequence is derived from OSRAM App Note AN018.\r
+//\r
+//*****************************************************************************\r
+static const unsigned char g_pucOSRAM128x64x4Init[] =\r
+{\r
+ //\r
+ // Column Address\r
+ //\r
+ 4, 0x15, 0, 63, 0xe3,\r
+\r
+ //\r
+ // Row Address\r
+ //\r
+ 4, 0x75, 0, 63, 0xe3,\r
+\r
+ //\r
+ // Contrast Control\r
+ //\r
+ 3, 0x81, 50, 0xe3,\r
+\r
+ //\r
+ // Half Current Range\r
+ //\r
+ 2, 0x85, 0xe3,\r
+\r
+ //\r
+ // Display Re-map\r
+ //\r
+ 3, 0xA0, OSRAM_INIT_REMAP, 0xe3,\r
+\r
+ //\r
+ // Display Start Line\r
+ //\r
+ 3, 0xA1, 0, 0xe3,\r
+\r
+ //\r
+ // Display Offset\r
+ //\r
+ 3, 0xA2, OSRAM_INIT_OFFSET, 0xe3,\r
+\r
+ //\r
+ // Display Mode Normal\r
+ //\r
+ 2, 0xA4, 0xe3,\r
+\r
+ //\r
+ // Multiplex Ratio\r
+ //\r
+ 3, 0xA8, 63, 0xe3,\r
+\r
+ //\r
+ // Phase Length\r
+ //\r
+ 3, 0xB1, 0x22, 0xe3,\r
+\r
+ //\r
+ // Row Period\r
+ //\r
+ 3, 0xB2, 70, 0xe3,\r
+\r
+ //\r
+ // Display Clock Divide\r
+ //\r
+ 3, 0xB3, 0xF1, 0xe3,\r
+\r
+ //\r
+ // VSL\r
+ //\r
+ 3, 0xBF, 0x0D, 0xe3,\r
+\r
+ //\r
+ // VCOMH\r
+ //\r
+ 3, 0xBE, 0x02, 0xe3,\r
+\r
+ //\r
+ // VP\r
+ //\r
+ 3, 0xBC, 0x10, 0xe3,\r
+\r
+ //\r
+ // Gamma\r
+ //\r
+ 10, 0xB8, 0x01, 0x11, 0x22, 0x32, 0x43, 0x54, 0x65, 0x76, 0xe3,\r
+\r
+ //\r
+ // Set DC-DC\r
+ 3, 0xAD, 0x03, 0xe3,\r
+\r
+ //\r
+ // Display ON/OFF\r
+ //\r
+ 2, 0xAF, 0xe3,\r
+};\r
+\r
+//*****************************************************************************\r
+//\r
+//! \internal\r
+//!\r
+//! Write a sequence of command bytes to the SSD0323 controller.\r
+//!\r
+//! The data is written in a polled fashion; this function will not return\r
+//! until the entire byte sequence has been written to the controller.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+static void\r
+OSRAMWriteCommand(const unsigned char *pucBuffer, unsigned long ulCount)\r
+{\r
+ unsigned long ulTemp;\r
+\r
+ //\r
+ // Return iff SSI port is not enabled for OSRAM.\r
+ //\r
+ if(!g_bSSIEnabled)\r
+ {\r
+ return;\r
+ }\r
+\r
+ //\r
+ // Clear the command/control bit to enable command mode.\r
+ //\r
+ GPIOPinWrite(GPIO_PORTC_BASE, GPIO_PIN_7, 0);\r
+\r
+ //\r
+ // Loop while there are more bytes left to be transferred.\r
+ //\r
+ while(ulCount != 0)\r
+ {\r
+ //\r
+ // Write the next byte to the controller.\r
+ //\r
+ SSIDataPut(SSI0_BASE, *pucBuffer++);\r
+\r
+ //\r
+ // Dummy read to drain the fifo and time the GPIO signal.\r
+ //\r
+ SSIDataGet(SSI0_BASE, &ulTemp);\r
+\r
+ //\r
+ // Decrement the BYTE counter.\r
+ //\r
+ ulCount--;\r
+ }\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! \internal\r
+//!\r
+//! Write a sequence of data bytes to the SSD0323 controller.\r
+//!\r
+//! The data is written in a polled fashion; this function will not return\r
+//! until the entire byte sequence has been written to the controller.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+static void\r
+OSRAMWriteData(const unsigned char *pucBuffer, unsigned long ulCount)\r
+{\r
+ unsigned long ulTemp;\r
+\r
+ //\r
+ // Return iff SSI port is not enabled for OSRAM.\r
+ //\r
+ if(!g_bSSIEnabled)\r
+ {\r
+ return;\r
+ }\r
+\r
+ //\r
+ // Set the command/control bit to enable data mode.\r
+ //\r
+ GPIOPinWrite(GPIO_PORTC_BASE, GPIO_PIN_7, GPIO_PIN_7);\r
+\r
+ //\r
+ // Loop while there are more bytes left to be transferred.\r
+ //\r
+ while(ulCount != 0)\r
+ {\r
+ //\r
+ // Write the next byte to the controller.\r
+ //\r
+ SSIDataPut(SSI0_BASE, *pucBuffer++);\r
+\r
+ //\r
+ // Dummy read to drain the fifo and time the GPIO signal.\r
+ //\r
+ SSIDataGet(SSI0_BASE, &ulTemp);\r
+\r
+ //\r
+ // Decrement the BYTE counter.\r
+ //\r
+ ulCount--;\r
+ }\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! Clears the OLED display.\r
+//!\r
+//! This function will clear the display RAM. All pixels in the display will\r
+//! be turned off.\r
+//!\r
+//! This function is contained in <tt>osram128x64x4.c</tt>, with\r
+//! <tt>osram128x64x4.h</tt> containing the API definition for use by\r
+//! applications.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+void\r
+OSRAM128x64x4Clear(void)\r
+{\r
+ static const unsigned char pucCommand1[] = { 0x15, 0, 63 };\r
+ static const unsigned char pucCommand2[] = { 0x75, 0, 79 };\r
+ unsigned long ulRow, ulColumn;\r
+ static unsigned char pucZeroBuffer[8] = { 0, 0, 0, 0, 0, 0, 0, 0};\r
+\r
+ //\r
+ // Set the window to fill the entire display.\r
+ //\r
+ OSRAMWriteCommand(pucCommand1, sizeof(pucCommand1));\r
+ OSRAMWriteCommand(pucCommand2, sizeof(pucCommand2));\r
+ OSRAMWriteCommand(g_pucOSRAM128x64x4VerticalInc,\r
+ sizeof(g_pucOSRAM128x64x4VerticalInc));\r
+\r
+ //\r
+ // In vertical address increment mode, loop through each column, filling\r
+ // each row with 0.\r
+ //\r
+ for(ulColumn = 0; ulColumn < (128/2); ulColumn++)\r
+ {\r
+ //\r
+ // 8 rows (bytes) per row of text.\r
+ //\r
+ for(ulRow = 0; ulRow < 80; ulRow += 8)\r
+ {\r
+ OSRAMWriteData(pucZeroBuffer, sizeof(pucZeroBuffer));\r
+ }\r
+ }\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! Displays a string on the OLED display.\r
+//!\r
+//! \param pcStr is a pointer to the string to display.\r
+//! \param ulX is the horizontal position to display the string, specified in\r
+//! columns from the left edge of the display.\r
+//! \param ulY is the vertical position to display the string, specified in\r
+//! rows from the top edge of the display.\r
+//! \param ucLevel is the 4-bit grey scale value to be used for displayed text.\r
+//!\r
+//! This function will draw a string on the display. Only the ASCII characters\r
+//! between 32 (space) and 126 (tilde) are supported; other characters will\r
+//! result in random data being draw on the display (based on whatever appears\r
+//! before/after the font in memory). The font is mono-spaced, so characters\r
+//! such as "i" and "l" have more white space around them than characters such\r
+//! as "m" or "w".\r
+//!\r
+//! If the drawing of the string reaches the right edge of the display, no more\r
+//! characters will be drawn. Therefore, special care is not required to avoid\r
+//! supplying a string that is "too long" to display.\r
+//!\r
+//! This function is contained in <tt>osram128x64x4.c</tt>, with\r
+//! <tt>osram128x64x4.h</tt> containing the API definition for use by\r
+//! applications.\r
+//!\r
+//! \note Because the OLED display packs 2 pixels of data in a single byte, the\r
+//! parameter \e ulX must be an even column number (e.g. 0, 2, 4, etc).\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+void\r
+OSRAM128x64x4StringDraw(const char *pcStr, unsigned long ulX,\r
+ unsigned long ulY, unsigned char ucLevel)\r
+{\r
+ static unsigned char pucBuffer[8];\r
+ unsigned long ulIdx1, ulIdx2;\r
+ unsigned char ucTemp;\r
+\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT(ulX < 128);\r
+ ASSERT((ulX & 1) == 0);\r
+ ASSERT(ulY < 64);\r
+ ASSERT(ucLevel < 16);\r
+\r
+ //\r
+ // Setup a window starting at the specified column and row, ending\r
+ // at the right edge of the display and 8 rows down (single character row).\r
+ //\r
+ pucBuffer[0] = 0x15;\r
+ pucBuffer[1] = ulX / 2;\r
+ pucBuffer[2] = 63;\r
+ OSRAMWriteCommand(pucBuffer, 3);\r
+ pucBuffer[0] = 0x75;\r
+ pucBuffer[1] = ulY;\r
+ pucBuffer[2] = ulY + 7;\r
+ OSRAMWriteCommand(pucBuffer, 3);\r
+ OSRAMWriteCommand(g_pucOSRAM128x64x4VerticalInc,\r
+ sizeof(g_pucOSRAM128x64x4VerticalInc));\r
+\r
+ //\r
+ // Loop while there are more characters in the string.\r
+ //\r
+ while(*pcStr != 0)\r
+ {\r
+ //\r
+ // Get a working copy of the current character and convert to an\r
+ // index into the character bit-map array.\r
+ //\r
+ ucTemp = *pcStr;\r
+ ucTemp &= 0x7F;\r
+ if(ucTemp < ' ')\r
+ {\r
+ ucTemp = ' ';\r
+ }\r
+ else\r
+ {\r
+ ucTemp -= ' ';\r
+ }\r
+\r
+ //\r
+ // Build and display the character buffer.\r
+ //\r
+ for(ulIdx1 = 0; ulIdx1 < 3; ulIdx1++)\r
+ {\r
+ //\r
+ // Convert two columns of 1-bit font data into a single data\r
+ // byte column of 4-bit font data.\r
+ //\r
+ for(ulIdx2 = 0; ulIdx2 < 8; ulIdx2++)\r
+ {\r
+ pucBuffer[ulIdx2] = 0;\r
+ if(g_pucFont[ucTemp][ulIdx1*2] & (1 << ulIdx2))\r
+ {\r
+ pucBuffer[ulIdx2] = ((ucLevel << 4) & 0xf0);\r
+ }\r
+ if((ulIdx1 < 2) &&\r
+ (g_pucFont[ucTemp][ulIdx1*2+1] & (1 << ulIdx2)))\r
+ {\r
+ pucBuffer[ulIdx2] |= ((ucLevel << 0) & 0x0f);\r
+ }\r
+ }\r
+\r
+ //\r
+ // If there is room, dump the single data byte column to the\r
+ // display. Otherwise, bail out.\r
+ //\r
+ if(ulX < 126)\r
+ {\r
+ OSRAMWriteData(pucBuffer, 8);\r
+ ulX += 2;\r
+ }\r
+ else\r
+ {\r
+ return;\r
+ }\r
+ }\r
+\r
+ //\r
+ // Advance to the next character.\r
+ //\r
+ pcStr++;\r
+ }\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! Displays an image on the OLED display.\r
+//!\r
+//! \param pucImage is a pointer to the image data.\r
+//! \param ulX is the horizontal position to display this image, specified in\r
+//! columns from the left edge of the display.\r
+//! \param ulY is the vertical position to display this image, specified in\r
+//! rows from the top of the display.\r
+//! \param ulWidth is the width of the image, specified in columns.\r
+//! \param ulHeight is the height of the image, specified in rows.\r
+//!\r
+//! This function will display a bitmap graphic on the display. Because of the\r
+//! format of the display RAM, the starting column (/e ulX) and the number of\r
+//! columns (/e ulWidth) must be an integer multiple of two.\r
+//!\r
+//! The image data is organized with the first row of image data appearing left\r
+//! to right, followed immediately by the second row of image data. Each byte\r
+//! contains the data for two columns in the current row, with the leftmost\r
+//! column being contained in bits 7:4 and the rightmost column being contained\r
+//! in bits 3:0.\r
+//!\r
+//! For example, an image six columns wide and seven scan lines tall would\r
+//! be arranged as follows (showing how the twenty one bytes of the image would\r
+//! appear on the display):\r
+//!\r
+//! \verbatim\r
+//! +-------------------+-------------------+-------------------+\r
+//! | Byte 0 | Byte 1 | Byte 2 |\r
+//! +---------+---------+---------+---------+---------+---------+\r
+//! | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 |\r
+//! +---------+---------+---------+---------+---------+---------+\r
+//! | Byte 3 | Byte 4 | Byte 5 |\r
+//! +---------+---------+---------+---------+---------+---------+\r
+//! | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 |\r
+//! +---------+---------+---------+---------+---------+---------+\r
+//! | Byte 6 | Byte 7 | Byte 8 |\r
+//! +---------+---------+---------+---------+---------+---------+\r
+//! | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 |\r
+//! +---------+---------+---------+---------+---------+---------+\r
+//! | Byte 9 | Byte 10 | Byte 11 |\r
+//! +---------+---------+---------+---------+---------+---------+\r
+//! | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 |\r
+//! +---------+---------+---------+---------+---------+---------+\r
+//! | Byte 12 | Byte 13 | Byte 14 |\r
+//! +---------+---------+---------+--3------+---------+---------+\r
+//! | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 |\r
+//! +---------+---------+---------+---------+---------+---------+\r
+//! | Byte 15 | Byte 16 | Byte 17 |\r
+//! +---------+---------+---------+---------+---------+---------+\r
+//! | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 |\r
+//! +---------+---------+---------+---------+---------+---------+\r
+//! | Byte 18 | Byte 19 | Byte 20 |\r
+//! +---------+---------+---------+---------+---------+---------+\r
+//! | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 |\r
+//! +---------+---------+---------+---------+---------+---------+\r
+//! \endverbatim\r
+//!\r
+//! This function is contained in <tt>osram128x64x4.c</tt>, with\r
+//! <tt>osram128x64x4.h</tt> containing the API definition for use by`\r
+//! applications.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+void\r
+OSRAM128x64x4ImageDraw(const unsigned char *pucImage, unsigned long ulX,\r
+ unsigned long ulY, unsigned long ulWidth,\r
+ unsigned long ulHeight)\r
+{\r
+ static unsigned char pucBuffer[8];\r
+\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT(ulX < 128);\r
+ ASSERT((ulX & 1) == 0);\r
+ ASSERT(ulY < 64);\r
+ ASSERT((ulX + ulWidth) <= 128);\r
+ ASSERT((ulY + ulHeight) <= 64);\r
+ ASSERT((ulWidth & 1) == 0);\r
+\r
+ //\r
+ // Setup a window starting at the specified column and row, and ending\r
+ // at the column + width and row+height.\r
+ //\r
+ pucBuffer[0] = 0x15;\r
+ pucBuffer[1] = ulX / 2;\r
+ pucBuffer[2] = (ulX + ulWidth - 2) / 2;\r
+ OSRAMWriteCommand(pucBuffer, 3);\r
+ pucBuffer[0] = 0x75;\r
+ pucBuffer[1] = ulY;\r
+ pucBuffer[2] = ulY + ulHeight - 1;\r
+ OSRAMWriteCommand(pucBuffer, 3);\r
+ OSRAMWriteCommand(g_pucOSRAM128x64x4HorizontalInc,\r
+ sizeof(g_pucOSRAM128x64x4HorizontalInc));\r
+\r
+ //\r
+ // Loop while there are more rows to display.\r
+ //\r
+ while(ulHeight--)\r
+ {\r
+ //\r
+ // Write this row of image data.\r
+ //\r
+ OSRAMWriteData(pucImage, (ulWidth / 2));\r
+\r
+ //\r
+ // Advance to the next row of the image.\r
+ //\r
+ pucImage += (ulWidth / 2);\r
+ }\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! Enable the SSI component of the OLED display driver.\r
+//!\r
+//! \param ulFrequency specifies the SSI Clock Frequency to be used.\r
+//!\r
+//! This function initializes the SSI interface to the OLED display.\r
+//!\r
+//! This function is contained in <tt>osram128x64x4.c</tt>, with\r
+//! <tt>osram128x64x4.h</tt> containing the API definition for use by\r
+//! applications.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+void\r
+OSRAM128x64x4Enable(unsigned long ulFrequency)\r
+{\r
+ unsigned long ulTemp;\r
+\r
+ //\r
+ // Disable the SSI port.\r
+ //\r
+ SSIDisable(SSI0_BASE);\r
+\r
+ //\r
+ // Configure the SSI0 port for master mode.\r
+ //\r
+ SSIConfig(SSI0_BASE, SSI_FRF_MOTO_MODE_2, SSI_MODE_MASTER, ulFrequency, 8);\r
+\r
+ //\r
+ // (Re)Enable SSI control of the FSS pin.\r
+ //\r
+ GPIOPinTypeSSI(GPIO_PORTA_BASE, GPIO_PIN_3);\r
+ GPIOPadConfigSet(GPIO_PORTA_BASE, GPIO_PIN_3, GPIO_STRENGTH_8MA,\r
+ GPIO_PIN_TYPE_STD_WPU);\r
+\r
+ //\r
+ // Enable the SSI port.\r
+ //\r
+ SSIEnable(SSI0_BASE);\r
+\r
+ //\r
+ // Drain the receive fifo.\r
+ //\r
+ while(SSIDataNonBlockingGet(SSI0_BASE, &ulTemp) != 0)\r
+ {\r
+ }\r
+\r
+ //\r
+ // Indicate that the OSRAM driver can use the SSI Port.\r
+ //\r
+ g_bSSIEnabled = true;\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! Enable the SSI component of the OLED display driver.\r
+//!\r
+//! \param ulFrequency specifies the SSI Clock Frequency to be used.\r
+//!\r
+//! This function initializes the SSI interface to the OLED display.\r
+//!\r
+//! This function is contained in <tt>osram128x64x4.c</tt>, with\r
+//! <tt>osram128x64x4.h</tt> containing the API definition for use by\r
+//! applications.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+void\r
+OSRAM128x64x4Disable(void)\r
+{\r
+ unsigned long ulTemp;\r
+\r
+ //\r
+ // Indicate that the OSRAM driver can no longer use the SSI Port.\r
+ //\r
+ g_bSSIEnabled = false;\r
+\r
+ //\r
+ // Drain the receive fifo.\r
+ //\r
+ while(SSIDataNonBlockingGet(SSI0_BASE, &ulTemp) != 0)\r
+ {\r
+ }\r
+\r
+ //\r
+ // Disable the SSI port.\r
+ //\r
+ SSIDisable(SSI0_BASE);\r
+\r
+ //\r
+ // Disable SSI control of the FSS pin.\r
+ //\r
+ GPIODirModeSet(GPIO_PORTA_BASE, GPIO_PIN_3, GPIO_DIR_MODE_OUT);\r
+ GPIOPadConfigSet(GPIO_PORTA_BASE, GPIO_PIN_3, GPIO_STRENGTH_8MA,\r
+ GPIO_PIN_TYPE_STD_WPU);\r
+ GPIOPinWrite(GPIO_PORTA_BASE, GPIO_PIN_3, GPIO_PIN_3);\r
+\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! Initialize the OLED display.\r
+//!\r
+//! \param ulFrequency specifies the SSI Clock Frequency to be used.\r
+//!\r
+//! This function initializes the SSI interface to the OLED display and\r
+//! configures the SSD0323 controller on the panel.\r
+//!\r
+//! This function is contained in <tt>osram128x64x4.c</tt>, with\r
+//! <tt>osram128x64x4.h</tt> containing the API definition for use by\r
+//! applications.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+void\r
+OSRAM128x64x4Init(unsigned long ulFrequency)\r
+{\r
+ unsigned long ulIdx;\r
+\r
+ //\r
+ // Enable the SSI0 and GPIO port blocks as they are needed by this driver.\r
+ //\r
+ SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI0);\r
+ SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA);\r
+ SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOC);\r
+\r
+ //\r
+ // Configure the SSI0CLK and SSIOTX pins for SSI operation.\r
+ //\r
+ GPIOPinTypeSSI(GPIO_PORTA_BASE, GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_5);\r
+ GPIOPadConfigSet(GPIO_PORTA_BASE, GPIO_PIN_2, GPIO_STRENGTH_8MA,\r
+ GPIO_PIN_TYPE_STD_WPU);\r
+ GPIOPadConfigSet(GPIO_PORTA_BASE, GPIO_PIN_3, GPIO_STRENGTH_8MA,\r
+ GPIO_PIN_TYPE_STD_WPU);\r
+ GPIOPadConfigSet(GPIO_PORTA_BASE, GPIO_PIN_5, GPIO_STRENGTH_8MA,\r
+ GPIO_PIN_TYPE_STD_WPU);\r
+\r
+ //\r
+ // Configure the PC7 pin as a D/Cn signal for OLED device.\r
+ //\r
+ GPIODirModeSet(GPIO_PORTC_BASE, GPIO_PIN_7, GPIO_DIR_MODE_OUT);\r
+ GPIOPadConfigSet(GPIO_PORTC_BASE, GPIO_PIN_7, GPIO_STRENGTH_8MA,\r
+ GPIO_PIN_TYPE_STD);\r
+ GPIOPinWrite(GPIO_PORTC_BASE, GPIO_PIN_7, GPIO_PIN_7);\r
+\r
+ //\r
+ // Configure and enable the SSI0 port for master mode.\r
+ //\r
+ OSRAM128x64x4Enable(ulFrequency);\r
+\r
+ //\r
+ // Clear the frame buffer.\r
+ //\r
+ OSRAM128x64x4Clear();\r
+\r
+ //\r
+ // Initialize the SSD0323 controller. Loop through the initialization\r
+ // sequence array, sending each command "string" to the controller.\r
+ //\r
+ for(ulIdx = 0; ulIdx < sizeof(g_pucOSRAM128x64x4Init);\r
+ ulIdx += g_pucOSRAM128x64x4Init[ulIdx] + 1)\r
+ {\r
+ //\r
+ // Send this command.\r
+ //\r
+ OSRAMWriteCommand(g_pucOSRAM128x64x4Init + ulIdx + 1,\r
+ g_pucOSRAM128x64x4Init[ulIdx] - 1);\r
+ }\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! Turns on the OLED display.\r
+//!\r
+//! This function will turn on the OLED display, causing it to display the\r
+//! contents of its internal frame buffer.\r
+//!\r
+//! This function is contained in <tt>osram128x64x4.c</tt>, with\r
+//! <tt>osram128x64x4.h</tt> containing the API definition for use by\r
+//! applications.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+void\r
+OSRAM128x64x4DisplayOn(void)\r
+{\r
+ unsigned long ulIdx;\r
+\r
+ //\r
+ // Initialize the SSD0323 controller. Loop through the initialization\r
+ // sequence array, sending each command "string" to the controller.\r
+ //\r
+ for(ulIdx = 0; ulIdx < sizeof(g_pucOSRAM128x64x4Init);\r
+ ulIdx += g_pucOSRAM128x64x4Init[ulIdx] + 1)\r
+ {\r
+ //\r
+ // Send this command.\r
+ //\r
+ OSRAMWriteCommand(g_pucOSRAM128x64x4Init + ulIdx + 1,\r
+ g_pucOSRAM128x64x4Init[ulIdx] - 1);\r
+ }\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! Turns off the OLED display.\r
+//!\r
+//! This function will turn off the OLED display. This will stop the scanning\r
+//! of the panel and turn off the on-chip DC-DC converter, preventing damage to\r
+//! the panel due to burn-in (it has similar characters to a CRT in this\r
+//! respect).\r
+//!\r
+//! This function is contained in <tt>osram128x64x4.c</tt>, with\r
+//! <tt>osram128x64x4.h</tt> containing the API definition for use by\r
+//! applications.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+void\r
+OSRAM128x64x4DisplayOff(void)\r
+{\r
+ static const unsigned char pucCommand1[] =\r
+ {\r
+ 0xAE, 0xAD, 0x02\r
+ };\r
+\r
+ //\r
+ // Turn off the DC-DC converter and the display.\r
+ //\r
+ OSRAMWriteCommand(pucCommand1, sizeof(pucCommand1));\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+// Close the Doxygen group.\r
+//! @}\r
+//\r
+//*****************************************************************************\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// osram128x64x4.h - Prototypes for the driver for the OSRAM 128x64x4 graphical\r
+// OLED display.\r
+//\r
+// Copyright (c) 2006-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __OSRAM128X64X4_H__\r
+#define __OSRAM128X64X4_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the driver APIs.\r
+//\r
+//*****************************************************************************\r
+extern void OSRAM128x64x4Clear(void);\r
+extern void OSRAM128x64x4StringDraw(const char *pcStr,\r
+ unsigned long ulX,\r
+ unsigned long ulY,\r
+ unsigned char ucLevel);\r
+extern void OSRAM128x64x4ImageDraw(const unsigned char *pucImage,\r
+ unsigned long ulX,\r
+ unsigned long ulY,\r
+ unsigned long ulWidth,\r
+ unsigned long ulHeight);\r
+extern void OSRAM128x64x4Init(unsigned long ulFrequency);\r
+extern void OSRAM128x64x4Enable(unsigned long ulFrequency);\r
+extern void OSRAM128x64x4Disable(void);\r
+extern void OSRAM128x64x4DisplayOn(void);\r
+extern void OSRAM128x64x4DisplayOff(void);\r
+\r
+//*****************************************************************************\r
+//\r
+// The following macro(s) map old names for the OSRAM functions to the new\r
+// names. In new code, the new names should be used in favor of the old names.\r
+//\r
+//*****************************************************************************\r
+#ifndef DEPRECATED\r
+#define OSRAM128x64x1InitSSI OSRAM128x64x4Enable\r
+#endif\r
+\r
+#endif // __OSRAM128X64X4_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// pwm.h - API function protoypes for Pulse Width Modulation (PWM) ports\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __PWM_H__\r
+#define __PWM_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// The following defines are passed to PWMGenConfigure() as the ulConfig\r
+// parameter and specify the configuration of the PWM generator.\r
+//\r
+//*****************************************************************************\r
+#define PWM_GEN_MODE_DOWN 0x00000000 // Down count mode\r
+#define PWM_GEN_MODE_UP_DOWN 0x00000002 // Up/Down count mode\r
+#define PWM_GEN_MODE_SYNC 0x00000038 // Synchronous updates\r
+#define PWM_GEN_MODE_NO_SYNC 0x00000000 // Immediate updates\r
+#define PWM_GEN_MODE_DBG_RUN 0x00000004 // Continue running in debug mode\r
+#define PWM_GEN_MODE_DBG_STOP 0x00000000 // Stop running in debug mode\r
+\r
+//*****************************************************************************\r
+//\r
+// Defines for enabling, disabling, and clearing PWM generator interrupts and\r
+// triggers.\r
+//\r
+//*****************************************************************************\r
+#define PWM_INT_CNT_ZERO 0x00000001 // Int if COUNT = 0\r
+#define PWM_INT_CNT_LOAD 0x00000002 // Int if COUNT = LOAD\r
+#define PWM_INT_CNT_AU 0x00000004 // Int if COUNT = CMPA U\r
+#define PWM_INT_CNT_AD 0x00000008 // Int if COUNT = CMPA D\r
+#define PWM_INT_CNT_BU 0x00000010 // Int if COUNT = CMPA U\r
+#define PWM_INT_CNT_BD 0x00000020 // Int if COUNT = CMPA D\r
+#define PWM_TR_CNT_ZERO 0x00000100 // Trig if COUNT = 0\r
+#define PWM_TR_CNT_LOAD 0x00000200 // Trig if COUNT = LOAD\r
+#define PWM_TR_CNT_AU 0x00000400 // Trig if COUNT = CMPA U\r
+#define PWM_TR_CNT_AD 0x00000800 // Trig if COUNT = CMPA D\r
+#define PWM_TR_CNT_BU 0x00001000 // Trig if COUNT = CMPA U\r
+#define PWM_TR_CNT_BD 0x00002000 // Trig if COUNT = CMPA D\r
+\r
+//*****************************************************************************\r
+//\r
+// Defines for enabling, disabling, and clearing PWM interrupts.\r
+//\r
+//*****************************************************************************\r
+#define PWM_INT_GEN_0 0x00000001 // Generator 0 interrupt\r
+#define PWM_INT_GEN_1 0x00000002 // Generator 1 interrupt\r
+#define PWM_INT_GEN_2 0x00000004 // Generator 2 interrupt\r
+#define PWM_INT_FAULT 0x00010000 // Fault interrupt\r
+\r
+//*****************************************************************************\r
+//\r
+// Defines to identify the generators within a module.\r
+//\r
+//*****************************************************************************\r
+#define PWM_GEN_0 0x00000040 // Offset address of Gen0\r
+#define PWM_GEN_1 0x00000080 // Offset address of Gen1\r
+#define PWM_GEN_2 0x000000C0 // Offset address of Gen2\r
+\r
+#define PWM_GEN_0_BIT 0x00000001 // Bit-wise ID for Gen0\r
+#define PWM_GEN_1_BIT 0x00000002 // Bit-wise ID for Gen1\r
+#define PWM_GEN_2_BIT 0x00000004 // Bit-wise ID for Gen2\r
+\r
+//*****************************************************************************\r
+//\r
+// Defines to identify the outputs within a module.\r
+//\r
+//*****************************************************************************\r
+#define PWM_OUT_0 0x00000040 // Encoded offset address of PWM0\r
+#define PWM_OUT_1 0x00000041 // Encoded offset address of PWM1\r
+#define PWM_OUT_2 0x00000082 // Encoded offset address of PWM2\r
+#define PWM_OUT_3 0x00000083 // Encoded offset address of PWM3\r
+#define PWM_OUT_4 0x000000C4 // Encoded offset address of PWM4\r
+#define PWM_OUT_5 0x000000C5 // Encoded offset address of PWM5\r
+\r
+#define PWM_OUT_0_BIT 0x00000001 // Bit-wise ID for PWM0\r
+#define PWM_OUT_1_BIT 0x00000002 // Bit-wise ID for PWM1\r
+#define PWM_OUT_2_BIT 0x00000004 // Bit-wise ID for PWM2\r
+#define PWM_OUT_3_BIT 0x00000008 // Bit-wise ID for PWM3\r
+#define PWM_OUT_4_BIT 0x00000010 // Bit-wise ID for PWM4\r
+#define PWM_OUT_5_BIT 0x00000020 // Bit-wise ID for PWM5\r
+\r
+//*****************************************************************************\r
+//\r
+// API Function prototypes\r
+//\r
+//*****************************************************************************\r
+extern void PWMGenConfigure(unsigned long ulBase, unsigned long ulGen,\r
+ unsigned long ulConfig);\r
+extern void PWMGenPeriodSet(unsigned long ulBase, unsigned long ulGen,\r
+ unsigned long ulPeriod);\r
+extern unsigned long PWMGenPeriodGet(unsigned long ulBase,\r
+ unsigned long ulGen);\r
+extern void PWMGenEnable(unsigned long ulBase, unsigned long ulGen);\r
+extern void PWMGenDisable(unsigned long ulBase, unsigned long ulGen);\r
+extern void PWMPulseWidthSet(unsigned long ulBase, unsigned long ulPWMOut,\r
+ unsigned long ulWidth);\r
+extern unsigned long PWMPulseWidthGet(unsigned long ulBase,\r
+ unsigned long ulPWMOut);\r
+extern void PWMDeadBandEnable(unsigned long ulBase, unsigned long ulGen,\r
+ unsigned short usRise, unsigned short usFall);\r
+extern void PWMDeadBandDisable(unsigned long ulBase, unsigned long ulGen);\r
+extern void PWMSyncUpdate(unsigned long ulBase, unsigned long ulGenBits);\r
+extern void PWMSyncTimeBase(unsigned long ulBase, unsigned long ulGenBits);\r
+extern void PWMOutputState(unsigned long ulBase, unsigned long ulPWMOutBits,\r
+ tBoolean bEnable);\r
+extern void PWMOutputInvert(unsigned long ulBase, unsigned long ulPWMOutBits,\r
+ tBoolean bInvert);\r
+extern void PWMOutputFault(unsigned long ulBase, unsigned long ulPWMOutBits,\r
+ tBoolean bFaultKill);\r
+extern void PWMGenIntRegister(unsigned long ulBase, unsigned long ulGen,\r
+ void (*pfnIntHandler)(void));\r
+extern void PWMGenIntUnregister(unsigned long ulBase, unsigned long ulGen);\r
+extern void PWMFaultIntRegister(unsigned long ulBase,\r
+ void (*pfnIntHandler)(void));\r
+extern void PWMFaultIntUnregister(unsigned long ulBase);\r
+extern void PWMGenIntTrigEnable(unsigned long ulBase, unsigned long ulGen,\r
+ unsigned long ulIntTrig);\r
+extern void PWMGenIntTrigDisable(unsigned long ulBase, unsigned long ulGen,\r
+ unsigned long ulIntTrig);\r
+extern unsigned long PWMGenIntStatus(unsigned long ulBase, unsigned long ulGen,\r
+ tBoolean bMasked);\r
+extern void PWMGenIntClear(unsigned long ulBase, unsigned long ulGen,\r
+ unsigned long ulInts);\r
+extern void PWMIntEnable(unsigned long ulBase, unsigned long ulGenFault);\r
+extern void PWMIntDisable(unsigned long ulBase, unsigned long ulGenFault);\r
+extern void PWMFaultIntClear(unsigned long ulBase);\r
+extern unsigned long PWMIntStatus(unsigned long ulBase, tBoolean bMasked);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __PWM_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// qei.h - Prototypes for the Quadrature Encoder Driver.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __QEI_H__\r
+#define __QEI_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to QEIConfigure as the ulConfig paramater.\r
+//\r
+//*****************************************************************************\r
+#define QEI_CONFIG_CAPTURE_A 0x00000000 // Count on ChA edges only\r
+#define QEI_CONFIG_CAPTURE_A_B 0x00000008 // Count on ChA and ChB edges\r
+#define QEI_CONFIG_NO_RESET 0x00000000 // Do not reset on index pulse\r
+#define QEI_CONFIG_RESET_IDX 0x00000010 // Reset position on index pulse\r
+#define QEI_CONFIG_QUADRATURE 0x00000000 // ChA and ChB are quadrature\r
+#define QEI_CONFIG_CLOCK_DIR 0x00000004 // ChA and ChB are clock and dir\r
+#define QEI_CONFIG_NO_SWAP 0x00000000 // Do not swap ChA and ChB\r
+#define QEI_CONFIG_SWAP 0x00000002 // Swap ChA and ChB\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to QEIVelocityConfigure as the ulPreDiv parameter.\r
+//\r
+//*****************************************************************************\r
+#define QEI_VELDIV_1 0x00000000 // Predivide by 1\r
+#define QEI_VELDIV_2 0x00000040 // Predivide by 2\r
+#define QEI_VELDIV_4 0x00000080 // Predivide by 4\r
+#define QEI_VELDIV_8 0x000000C0 // Predivide by 8\r
+#define QEI_VELDIV_16 0x00000100 // Predivide by 16\r
+#define QEI_VELDIV_32 0x00000140 // Predivide by 32\r
+#define QEI_VELDIV_64 0x00000180 // Predivide by 64\r
+#define QEI_VELDIV_128 0x000001C0 // Predivide by 128\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to QEIEnableInts, QEIDisableInts, and QEIClearInts\r
+// as the ulIntFlags parameter, and returned by QEIGetIntStatus.\r
+//\r
+//*****************************************************************************\r
+#define QEI_INTERROR 0x00000008 // Phase error detected\r
+#define QEI_INTDIR 0x00000004 // Direction change\r
+#define QEI_INTTIMER 0x00000002 // Velocity timer expired\r
+#define QEI_INTINDEX 0x00000001 // Index pulse detected\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+extern void QEIEnable(unsigned long ulBase);\r
+extern void QEIDisable(unsigned long ulBase);\r
+extern void QEIConfigure(unsigned long ulBase, unsigned long ulConfig,\r
+ unsigned long ulMaxPosition);\r
+extern unsigned long QEIPositionGet(unsigned long ulBase);\r
+extern void QEIPositionSet(unsigned long ulBase, unsigned long ulPosition);\r
+extern long QEIDirectionGet(unsigned long ulBase);\r
+extern tBoolean QEIErrorGet(unsigned long ulBase);\r
+extern void QEIVelocityEnable(unsigned long ulBase);\r
+extern void QEIVelocityDisable(unsigned long ulBase);\r
+extern void QEIVelocityConfigure(unsigned long ulBase, unsigned long ulPreDiv,\r
+ unsigned long ulPeriod);\r
+extern unsigned long QEIVelocityGet(unsigned long ulBase);\r
+extern void QEIIntRegister(unsigned long ulBase, void (*pfnHandler)(void));\r
+extern void QEIIntUnregister(unsigned long ulBase);\r
+extern void QEIIntEnable(unsigned long ulBase, unsigned long ulIntFlags);\r
+extern void QEIIntDisable(unsigned long ulBase, unsigned long ulIntFlags);\r
+extern unsigned long QEIIntStatus(unsigned long ulBase, tBoolean bMasked);\r
+extern void QEIIntClear(unsigned long ulBase, unsigned long ulIntFlags);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __QEI_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// ssi.h - Prototypes for the Synchronous Serial Interface Driver.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __SSI_H__\r
+#define __SSI_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to SSIIntEnable, SSIIntDisable, and SSIIntClear\r
+// as the ulIntFlags parameter, and returned by SSIIntStatus.\r
+//\r
+//*****************************************************************************\r
+#define SSI_TXFF 0x00000008 // TX FIFO half empty or less\r
+#define SSI_RXFF 0x00000004 // RX FIFO half full or less\r
+#define SSI_RXTO 0x00000002 // RX timeout\r
+#define SSI_RXOR 0x00000001 // RX overrun\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to SSIConfig.\r
+//\r
+//*****************************************************************************\r
+#define SSI_FRF_MOTO_MODE_0 0x00000000 // Moto fmt, polarity 0, phase 0\r
+#define SSI_FRF_MOTO_MODE_1 0x00000002 // Moto fmt, polarity 0, phase 1\r
+#define SSI_FRF_MOTO_MODE_2 0x00000001 // Moto fmt, polarity 1, phase 0\r
+#define SSI_FRF_MOTO_MODE_3 0x00000003 // Moto fmt, polarity 1, phase 1\r
+#define SSI_FRF_TI 0x00000010 // TI frame format\r
+#define SSI_FRF_NMW 0x00000020 // National MicroWire frame format\r
+\r
+#define SSI_MODE_MASTER 0x00000000 // SSI master\r
+#define SSI_MODE_SLAVE 0x00000001 // SSI slave\r
+#define SSI_MODE_SLAVE_OD 0x00000002 // SSI slave with output disabled\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+extern void SSIConfig(unsigned long ulBase, unsigned long ulProtocol,\r
+ unsigned long ulMode, unsigned long ulBitRate,\r
+ unsigned long ulDataWidth);\r
+extern void SSIDataGet(unsigned long ulBase, unsigned long *pulData);\r
+extern long SSIDataNonBlockingGet(unsigned long ulBase,\r
+ unsigned long *pulData);\r
+extern void SSIDataPut(unsigned long ulBase, unsigned long ulData);\r
+extern long SSIDataNonBlockingPut(unsigned long ulBase, unsigned long ulData);\r
+extern void SSIDisable(unsigned long ulBase);\r
+extern void SSIEnable(unsigned long ulBase);\r
+extern void SSIIntClear(unsigned long ulBase, unsigned long ulIntFlags);\r
+extern void SSIIntDisable(unsigned long ulBase, unsigned long ulIntFlags);\r
+extern void SSIIntEnable(unsigned long ulBase, unsigned long ulIntFlags);\r
+extern void SSIIntRegister(unsigned long ulBase, void(*pfnHandler)(void));\r
+extern unsigned long SSIIntStatus(unsigned long ulBase, tBoolean bMasked);\r
+extern void SSIIntUnregister(unsigned long ulBase);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __SSI_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// sysctl.h - Prototypes for the system control driver.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __SYSCTL_H__\r
+#define __SYSCTL_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the\r
+// SysCtlPeripheralPresent(), SysCtlPeripheralEnable(),\r
+// SysCtlPeripheralDisable(), and SysCtlPeripheralReset() APIs as the\r
+// ulPeripheral parameter. The peripherals in the fourth group (upper nibble\r
+// is 3) can only be used with the SysCtlPeripheralPresent() API.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_PERIPH_PWM 0x00100010 // PWM\r
+#define SYSCTL_PERIPH_ADC 0x00100001 // ADC\r
+#define SYSCTL_PERIPH_HIBERNATE 0x00000040 // Hibernation module\r
+#define SYSCTL_PERIPH_WDOG 0x00000008 // Watchdog\r
+#define SYSCTL_PERIPH_CAN0 0x00100100 // CAN 0\r
+#define SYSCTL_PERIPH_CAN1 0x00100200 // CAN 1\r
+#define SYSCTL_PERIPH_UART0 0x10000001 // UART 0\r
+#define SYSCTL_PERIPH_UART1 0x10000002 // UART 1\r
+#define SYSCTL_PERIPH_UART2 0x10000004 // UART 2\r
+#define SYSCTL_PERIPH_SSI 0x10000010 // SSI\r
+#define SYSCTL_PERIPH_SSI0 0x10000010 // SSI 0\r
+#define SYSCTL_PERIPH_SSI1 0x10000020 // SSI 1\r
+#define SYSCTL_PERIPH_QEI 0x10000100 // QEI\r
+#define SYSCTL_PERIPH_QEI0 0x10000100 // QEI 0\r
+#define SYSCTL_PERIPH_QEI1 0x10000200 // QEI 1\r
+#define SYSCTL_PERIPH_I2C 0x10001000 // I2C\r
+#define SYSCTL_PERIPH_I2C0 0x10001000 // I2C 0\r
+#define SYSCTL_PERIPH_I2C1 0x10004000 // I2C 1\r
+#define SYSCTL_PERIPH_TIMER0 0x10100001 // Timer 0\r
+#define SYSCTL_PERIPH_TIMER1 0x10100002 // Timer 1\r
+#define SYSCTL_PERIPH_TIMER2 0x10100004 // Timer 2\r
+#define SYSCTL_PERIPH_TIMER3 0x10100008 // Timer 3\r
+#define SYSCTL_PERIPH_COMP0 0x10100100 // Analog comparator 0\r
+#define SYSCTL_PERIPH_COMP1 0x10100200 // Analog comparator 1\r
+#define SYSCTL_PERIPH_COMP2 0x10100400 // Analog comparator 2\r
+#define SYSCTL_PERIPH_GPIOA 0x20000001 // GPIO A\r
+#define SYSCTL_PERIPH_GPIOB 0x20000002 // GPIO B\r
+#define SYSCTL_PERIPH_GPIOC 0x20000004 // GPIO C\r
+#define SYSCTL_PERIPH_GPIOD 0x20000008 // GPIO D\r
+#define SYSCTL_PERIPH_GPIOE 0x20000010 // GPIO E\r
+#define SYSCTL_PERIPH_GPIOF 0x20000020 // GPIO F\r
+#define SYSCTL_PERIPH_GPIOG 0x20000040 // GPIO G\r
+#define SYSCTL_PERIPH_GPIOH 0x20000080 // GPIO H\r
+#define SYSCTL_PERIPH_ETH 0x20105000 // ETH\r
+#define SYSCTL_PERIPH_MPU 0x30000080 // Cortex M3 MPU\r
+#define SYSCTL_PERIPH_TEMP 0x30000020 // Temperature sensor\r
+#define SYSCTL_PERIPH_PLL 0x30000010 // PLL\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the SysCtlPinPresent() API\r
+// as the ulPin parameter.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_PIN_PWM0 0x00000001 // PWM0 pin\r
+#define SYSCTL_PIN_PWM1 0x00000002 // PWM1 pin\r
+#define SYSCTL_PIN_PWM2 0x00000004 // PWM2 pin\r
+#define SYSCTL_PIN_PWM3 0x00000008 // PWM3 pin\r
+#define SYSCTL_PIN_PWM4 0x00000010 // PWM4 pin\r
+#define SYSCTL_PIN_PWM5 0x00000020 // PWM5 pin\r
+#define SYSCTL_PIN_C0MINUS 0x00000040 // C0- pin\r
+#define SYSCTL_PIN_C0PLUS 0x00000080 // C0+ pin\r
+#define SYSCTL_PIN_C0O 0x00000100 // C0o pin\r
+#define SYSCTL_PIN_C1MINUS 0x00000200 // C1- pin\r
+#define SYSCTL_PIN_C1PLUS 0x00000400 // C1+ pin\r
+#define SYSCTL_PIN_C1O 0x00000800 // C1o pin\r
+#define SYSCTL_PIN_C2MINUS 0x00001000 // C2- pin\r
+#define SYSCTL_PIN_C2PLUS 0x00002000 // C2+ pin\r
+#define SYSCTL_PIN_C2O 0x00004000 // C2o pin\r
+#define SYSCTL_PIN_MC_FAULT0 0x00008000 // MC0 Fault pin\r
+#define SYSCTL_PIN_ADC0 0x00010000 // ADC0 pin\r
+#define SYSCTL_PIN_ADC1 0x00020000 // ADC1 pin\r
+#define SYSCTL_PIN_ADC2 0x00040000 // ADC2 pin\r
+#define SYSCTL_PIN_ADC3 0x00080000 // ADC3 pin\r
+#define SYSCTL_PIN_ADC4 0x00100000 // ADC4 pin\r
+#define SYSCTL_PIN_ADC5 0x00200000 // ADC5 pin\r
+#define SYSCTL_PIN_ADC6 0x00400000 // ADC6 pin\r
+#define SYSCTL_PIN_ADC7 0x00800000 // ADC7 pin\r
+#define SYSCTL_PIN_CCP0 0x01000000 // CCP0 pin\r
+#define SYSCTL_PIN_CCP1 0x02000000 // CCP1 pin\r
+#define SYSCTL_PIN_CCP2 0x04000000 // CCP2 pin\r
+#define SYSCTL_PIN_CCP3 0x08000000 // CCP3 pin\r
+#define SYSCTL_PIN_CCP4 0x10000000 // CCP4 pin\r
+#define SYSCTL_PIN_CCP5 0x20000000 // CCP5 pin\r
+#define SYSCTL_PIN_32KHZ 0x80000000 // 32kHz pin\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the SysCtlLDOSet() API as\r
+// the ulVoltage value, or returned by the SysCtlLDOGet() API.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_LDO_2_25V 0x00000005 // LDO output of 2.25V\r
+#define SYSCTL_LDO_2_30V 0x00000004 // LDO output of 2.30V\r
+#define SYSCTL_LDO_2_35V 0x00000003 // LDO output of 2.35V\r
+#define SYSCTL_LDO_2_40V 0x00000002 // LDO output of 2.40V\r
+#define SYSCTL_LDO_2_45V 0x00000001 // LDO output of 2.45V\r
+#define SYSCTL_LDO_2_50V 0x00000000 // LDO output of 2.50V\r
+#define SYSCTL_LDO_2_55V 0x0000001f // LDO output of 2.55V\r
+#define SYSCTL_LDO_2_60V 0x0000001e // LDO output of 2.60V\r
+#define SYSCTL_LDO_2_65V 0x0000001d // LDO output of 2.65V\r
+#define SYSCTL_LDO_2_70V 0x0000001c // LDO output of 2.70V\r
+#define SYSCTL_LDO_2_75V 0x0000001b // LDO output of 2.75V\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the SysCtlLDOConfigSet() API.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_LDOCFG_ARST 0x00000001 // Allow LDO failure to reset\r
+#define SYSCTL_LDOCFG_NORST 0x00000000 // Do not reset on LDO failure\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the SysCtlIntEnable(),\r
+// SysCtlIntDisable(), and SysCtlIntClear() APIs, or returned in the bit mask\r
+// by the SysCtlIntStatus() API.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_INT_PLL_LOCK 0x00000040 // PLL lock interrupt\r
+#define SYSCTL_INT_CUR_LIMIT 0x00000020 // Current limit interrupt\r
+#define SYSCTL_INT_IOSC_FAIL 0x00000010 // Internal oscillator failure int\r
+#define SYSCTL_INT_MOSC_FAIL 0x00000008 // Main oscillator failure int\r
+#define SYSCTL_INT_POR 0x00000004 // Power on reset interrupt\r
+#define SYSCTL_INT_BOR 0x00000002 // Brown out interrupt\r
+#define SYSCTL_INT_PLL_FAIL 0x00000001 // PLL failure interrupt\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the SysCtlResetCauseClear()\r
+// API or returned by the SysCtlResetCauseGet() API.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_CAUSE_LDO 0x00000020 // LDO power not OK reset\r
+#define SYSCTL_CAUSE_SW 0x00000010 // Software reset\r
+#define SYSCTL_CAUSE_WDOG 0x00000008 // Watchdog reset\r
+#define SYSCTL_CAUSE_BOR 0x00000004 // Brown-out reset\r
+#define SYSCTL_CAUSE_POR 0x00000002 // Power on reset\r
+#define SYSCTL_CAUSE_EXT 0x00000001 // External reset\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the SysCtlBrownOutConfigSet()\r
+// API as the ulConfig parameter.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_BOR_RESET 0x00000002 // Reset instead of interrupting\r
+#define SYSCTL_BOR_RESAMPLE 0x00000001 // Resample BOR before asserting\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the SysCtlPWMClockSet() API\r
+// as the ulConfig parameter, and can be returned by the SysCtlPWMClockGet()\r
+// API.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_PWMDIV_1 0x00000000 // PWM clock is processor clock /1\r
+#define SYSCTL_PWMDIV_2 0x00100000 // PWM clock is processor clock /2\r
+#define SYSCTL_PWMDIV_4 0x00120000 // PWM clock is processor clock /4\r
+#define SYSCTL_PWMDIV_8 0x00140000 // PWM clock is processor clock /8\r
+#define SYSCTL_PWMDIV_16 0x00160000 // PWM clock is processor clock /16\r
+#define SYSCTL_PWMDIV_32 0x00180000 // PWM clock is processor clock /32\r
+#define SYSCTL_PWMDIV_64 0x001A0000 // PWM clock is processor clock /64\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the SysCtlADCSpeedSet() API\r
+// as the ulSpeed parameter, and can be returned by the SyCtlADCSpeedGet()\r
+// API.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_ADCSPEED_1MSPS 0x00000300 // 1,000,000 samples per second\r
+#define SYSCTL_ADCSPEED_500KSPS 0x00000200 // 500,000 samples per second\r
+#define SYSCTL_ADCSPEED_250KSPS 0x00000100 // 250,000 samples per second\r
+#define SYSCTL_ADCSPEED_125KSPS 0x00000000 // 125,000 samples per second\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the SysCtlClockSet() API as\r
+// the ulConfig parameter.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_SYSDIV_1 0x07800000 // Processor clock is osc/pll /1\r
+#define SYSCTL_SYSDIV_2 0x00C00000 // Processor clock is osc/pll /2\r
+#define SYSCTL_SYSDIV_3 0x01400000 // Processor clock is osc/pll /3\r
+#define SYSCTL_SYSDIV_4 0x01C00000 // Processor clock is osc/pll /4\r
+#define SYSCTL_SYSDIV_5 0x02400000 // Processor clock is osc/pll /5\r
+#define SYSCTL_SYSDIV_6 0x02C00000 // Processor clock is osc/pll /6\r
+#define SYSCTL_SYSDIV_7 0x03400000 // Processor clock is osc/pll /7\r
+#define SYSCTL_SYSDIV_8 0x03C00000 // Processor clock is osc/pll /8\r
+#define SYSCTL_SYSDIV_9 0x04400000 // Processor clock is osc/pll /9\r
+#define SYSCTL_SYSDIV_10 0x04C00000 // Processor clock is osc/pll /10\r
+#define SYSCTL_SYSDIV_11 0x05400000 // Processor clock is osc/pll /11\r
+#define SYSCTL_SYSDIV_12 0x05C00000 // Processor clock is osc/pll /12\r
+#define SYSCTL_SYSDIV_13 0x06400000 // Processor clock is osc/pll /13\r
+#define SYSCTL_SYSDIV_14 0x06C00000 // Processor clock is osc/pll /14\r
+#define SYSCTL_SYSDIV_15 0x07400000 // Processor clock is osc/pll /15\r
+#define SYSCTL_SYSDIV_16 0x07C00000 // Processor clock is osc/pll /16\r
+#define SYSCTL_USE_PLL 0x00000000 // System clock is the PLL clock\r
+#define SYSCTL_USE_OSC 0x00003800 // System clock is the osc clock\r
+#define SYSCTL_XTAL_3_57MHZ 0x00000100 // External crystal is 3.579545MHz\r
+#define SYSCTL_XTAL_3_68MHZ 0x00000140 // External crystal is 3.6864MHz\r
+#define SYSCTL_XTAL_4MHZ 0x00000180 // External crystal is 4MHz\r
+#define SYSCTL_XTAL_4_09MHZ 0x000001C0 // External crystal is 4.096MHz\r
+#define SYSCTL_XTAL_4_91MHZ 0x00000200 // External crystal is 4.9152MHz\r
+#define SYSCTL_XTAL_5MHZ 0x00000240 // External crystal is 5MHz\r
+#define SYSCTL_XTAL_5_12MHZ 0x00000280 // External crystal is 5.12MHz\r
+#define SYSCTL_XTAL_6MHZ 0x000002C0 // External crystal is 6MHz\r
+#define SYSCTL_XTAL_6_14MHZ 0x00000300 // External crystal is 6.144MHz\r
+#define SYSCTL_XTAL_7_37MHZ 0x00000340 // External crystal is 7.3728MHz\r
+#define SYSCTL_XTAL_8MHZ 0x00000380 // External crystal is 8MHz\r
+#define SYSCTL_XTAL_8_19MHZ 0x000003C0 // External crystal is 8.192MHz\r
+#define SYSCTL_OSC_MAIN 0x00000000 // Oscillator source is main osc\r
+#define SYSCTL_OSC_INT 0x00000010 // Oscillator source is int. osc\r
+#define SYSCTL_OSC_INT4 0x00000020 // Oscillator source is int. osc /4\r
+#define SYSCTL_INT_OSC_DIS 0x00000002 // Disable internal oscillator\r
+#define SYSCTL_MAIN_OSC_DIS 0x00000001 // Disable main oscillator\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+extern unsigned long SysCtlSRAMSizeGet(void);\r
+extern unsigned long SysCtlFlashSizeGet(void);\r
+extern tBoolean SysCtlPinPresent(unsigned long ulPin);\r
+extern tBoolean SysCtlPeripheralPresent(unsigned long ulPeripheral);\r
+extern void SysCtlPeripheralReset(unsigned long ulPeripheral);\r
+extern void SysCtlPeripheralEnable(unsigned long ulPeripheral);\r
+extern void SysCtlPeripheralDisable(unsigned long ulPeripheral);\r
+extern void SysCtlPeripheralSleepEnable(unsigned long ulPeripheral);\r
+extern void SysCtlPeripheralSleepDisable(unsigned long ulPeripheral);\r
+extern void SysCtlPeripheralDeepSleepEnable(unsigned long ulPeripheral);\r
+extern void SysCtlPeripheralDeepSleepDisable(unsigned long ulPeripheral);\r
+extern void SysCtlPeripheralClockGating(tBoolean bEnable);\r
+extern void SysCtlIntRegister(void (*pfnHandler)(void));\r
+extern void SysCtlIntUnregister(void);\r
+extern void SysCtlIntEnable(unsigned long ulInts);\r
+extern void SysCtlIntDisable(unsigned long ulInts);\r
+extern void SysCtlIntClear(unsigned long ulInts);\r
+extern unsigned long SysCtlIntStatus(tBoolean bMasked);\r
+extern void SysCtlLDOSet(unsigned long ulVoltage);\r
+extern unsigned long SysCtlLDOGet(void);\r
+extern void SysCtlLDOConfigSet(unsigned long ulConfig);\r
+extern void SysCtlReset(void);\r
+extern void SysCtlSleep(void);\r
+extern void SysCtlDeepSleep(void);\r
+extern unsigned long SysCtlResetCauseGet(void);\r
+extern void SysCtlResetCauseClear(unsigned long ulCauses);\r
+extern void SysCtlBrownOutConfigSet(unsigned long ulConfig,\r
+ unsigned long ulDelay);\r
+extern void SysCtlClockSet(unsigned long ulConfig);\r
+extern unsigned long SysCtlClockGet(void);\r
+extern void SysCtlPWMClockSet(unsigned long ulConfig);\r
+extern unsigned long SysCtlPWMClockGet(void);\r
+extern void SysCtlADCSpeedSet(unsigned long ulSpeed);\r
+extern unsigned long SysCtlADCSpeedGet(void);\r
+extern void SysCtlIOSCVerificationSet(tBoolean bEnable);\r
+extern void SysCtlMOSCVerificationSet(tBoolean bEnable);\r
+extern void SysCtlPLLVerificationSet(tBoolean bEnable);\r
+extern void SysCtlClkVerificationClear(void);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __SYSCTL_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// systick.h - Prototypes for the SysTick driver.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __SYSTICK_H__\r
+#define __SYSTICK_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+extern void SysTickEnable(void);\r
+extern void SysTickDisable(void);\r
+extern void SysTickIntRegister(void (*pfnHandler)(void));\r
+extern void SysTickIntUnregister(void);\r
+extern void SysTickIntEnable(void);\r
+extern void SysTickIntDisable(void);\r
+extern void SysTickPeriodSet(unsigned long ulPeriod);\r
+extern unsigned long SysTickPeriodGet(void);\r
+extern unsigned long SysTickValueGet(void);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __SYSTICK_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// uart.h - Defines and Macros for the UART.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __UART_H__\r
+#define __UART_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to UARTIntEnable, UARTIntDisable, and UARTIntClear\r
+// as the ulIntFlags parameter, and returned from UARTIntStatus.\r
+//\r
+//*****************************************************************************\r
+#define UART_INT_OE 0x400 // Overrun Error Interrupt Mask\r
+#define UART_INT_BE 0x200 // Break Error Interrupt Mask\r
+#define UART_INT_PE 0x100 // Parity Error Interrupt Mask\r
+#define UART_INT_FE 0x080 // Framing Error Interrupt Mask\r
+#define UART_INT_RT 0x040 // Receive Timeout Interrupt Mask\r
+#define UART_INT_TX 0x020 // Transmit Interrupt Mask\r
+#define UART_INT_RX 0x010 // Receive Interrupt Mask\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to UARTConfigSet as the ulConfig parameter and\r
+// returned by UARTConfigGet in the pulConfig parameter. Additionally, the\r
+// UART_CONFIG_PAR_* subset can be passed to UARTParityModeSet as the ulParity\r
+// parameter, and are returned by UARTParityModeGet.\r
+//\r
+//*****************************************************************************\r
+#define UART_CONFIG_WLEN_8 0x00000060 // 8 bit data\r
+#define UART_CONFIG_WLEN_7 0x00000040 // 7 bit data\r
+#define UART_CONFIG_WLEN_6 0x00000020 // 6 bit data\r
+#define UART_CONFIG_WLEN_5 0x00000000 // 5 bit data\r
+#define UART_CONFIG_STOP_ONE 0x00000000 // One stop bit\r
+#define UART_CONFIG_STOP_TWO 0x00000008 // Two stop bits\r
+#define UART_CONFIG_PAR_NONE 0x00000000 // No parity\r
+#define UART_CONFIG_PAR_EVEN 0x00000006 // Even parity\r
+#define UART_CONFIG_PAR_ODD 0x00000002 // Odd parity\r
+#define UART_CONFIG_PAR_ONE 0x00000086 // Parity bit is one\r
+#define UART_CONFIG_PAR_ZERO 0x00000082 // Parity bit is zero\r
+\r
+//*****************************************************************************\r
+//\r
+// API Function prototypes\r
+//\r
+//*****************************************************************************\r
+extern void UARTParityModeSet(unsigned long ulBase, unsigned long ulParity);\r
+extern unsigned long UARTParityModeGet(unsigned long ulBase);\r
+extern void UARTConfigSet(unsigned long ulBase, unsigned long ulBaud,\r
+ unsigned long ulConfig);\r
+extern void UARTConfigGet(unsigned long ulBase, unsigned long *pulBaud,\r
+ unsigned long *pulConfig);\r
+extern void UARTEnable(unsigned long ulBase);\r
+extern void UARTDisable(unsigned long ulBase);\r
+extern void UARTEnableSIR(unsigned long ulBase, tBoolean bLowPower);\r
+extern void UARTDisableSIR(unsigned long ulBase);\r
+extern tBoolean UARTCharsAvail(unsigned long ulBase);\r
+extern tBoolean UARTSpaceAvail(unsigned long ulBase);\r
+extern long UARTCharNonBlockingGet(unsigned long ulBase);\r
+extern long UARTCharGet(unsigned long ulBase);\r
+extern tBoolean UARTCharNonBlockingPut(unsigned long ulBase,\r
+ unsigned char ucData);\r
+extern void UARTCharPut(unsigned long ulBase, unsigned char ucData);\r
+extern void UARTBreakCtl(unsigned long ulBase, tBoolean bBreakState);\r
+extern void UARTIntRegister(unsigned long ulBase, void(*pfnHandler)(void));\r
+extern void UARTIntUnregister(unsigned long ulBase);\r
+extern void UARTIntEnable(unsigned long ulBase, unsigned long ulIntFlags);\r
+extern void UARTIntDisable(unsigned long ulBase, unsigned long ulIntFlags);\r
+extern unsigned long UARTIntStatus(unsigned long ulBase, tBoolean bMasked);\r
+extern void UARTIntClear(unsigned long ulBase, unsigned long ulIntFlags);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __UART_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// watchdog.h - Prototypes for the Watchdog Timer API\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __WATCHDOG_H__\r
+#define __WATCHDOG_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+extern tBoolean WatchdogRunning(unsigned long ulBase);\r
+extern void WatchdogEnable(unsigned long ulBase);\r
+extern void WatchdogResetEnable(unsigned long ulBase);\r
+extern void WatchdogResetDisable(unsigned long ulBase);\r
+extern void WatchdogLock(unsigned long ulBase);\r
+extern void WatchdogUnlock(unsigned long ulBase);\r
+extern tBoolean WatchdogLockState(unsigned long ulBase);\r
+extern void WatchdogReloadSet(unsigned long ulBase, unsigned long ulLoadVal);\r
+extern unsigned long WatchdogReloadGet(unsigned long ulBase);\r
+extern unsigned long WatchdogValueGet(unsigned long ulBase);\r
+extern void WatchdogIntRegister(unsigned long ulBase, void(*pfnHandler)(void));\r
+extern void WatchdogIntUnregister(unsigned long ulBase);\r
+extern void WatchdogIntEnable(unsigned long ulBase);\r
+extern unsigned long WatchdogIntStatus(unsigned long ulBase, tBoolean bMasked);\r
+extern void WatchdogIntClear(unsigned long ulBase);\r
+extern void WatchdogStallDisable(unsigned long ulBase);\r
+extern void WatchdogStallDisable(unsigned long ulBase);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __WATCHDOG_H__\r
--- /dev/null
+/*\r
+ FreeRTOS.org V4.3.0 - Copyright (C) 2003-2007 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS.org distribution.\r
+\r
+ FreeRTOS.org is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS.org is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS.org; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS.org, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section\r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license\r
+ and contact details. Please ensure to read the configuration and relevant\r
+ port sections of the online documentation.\r
+\r
+ Also see http://www.SafeRTOS.com for an IEC 61508 compliant version along\r
+ with commercial development and support options.\r
+ ***************************************************************************\r
+*/\r
+\r
+/*-----------------------------------------------------------\r
+ * Simple parallel port IO routines.\r
+ *-----------------------------------------------------------*/\r
+\r
+/*\r
+*/\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/* Demo includes. */\r
+#include "partest.h"\r
+\r
+/* Library includes. */\r
+#include "hw_types.h"\r
+#include "gpio.h"\r
+#include "hw_memmap.h"\r
+\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestInitialise( void )\r
+{\r
+ GPIODirModeSet( GPIO_PORTF_BASE, GPIO_PIN_0, GPIO_DIR_MODE_OUT );\r
+ GPIOPadConfigSet( GPIO_PORTF_BASE, GPIO_PIN_0, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD );\r
+ GPIOPinWrite( GPIO_PORTF_BASE, GPIO_PIN_0, 0 );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue )\r
+{\r
+ /* There is only one LED. */\r
+ ( void ) uxLED;\r
+ \r
+ GPIOPinWrite( GPIO_PORTF_BASE, GPIO_PIN_0, xValue );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+unsigned portBASE_TYPE uxParTestGetLED( unsigned portBASE_TYPE uxLED )\r
+{\r
+ /* There is only one LED. */\r
+ ( void ) uxLED;\r
+\r
+ return GPIOPinRead( GPIO_PORTF_BASE, GPIO_PIN_0 ); \r
+}\r
+\r
+\r
--- /dev/null
+<?xml version="1.0" encoding="iso-8859-1"?>\r
+\r
+<project>\r
+ <fileVersion>2</fileVersion>\r
+ <configuration>\r
+ <name>Debug</name>\r
+ <outputs>\r
+ <file>$PROJ_DIR$\timertest.c</file>\r
+ <file>$PROJ_DIR$\..\..\Source\portable\IAR\ARM_CM3\portasm.s</file>\r
+ <file>$PROJ_DIR$\..\..\Source\queue.c</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\heap_2.r79</file>\r
+ <file>$PROJ_DIR$\..\..\Source\list.c</file>\r
+ <file>$PROJ_DIR$\..\..\Source\portable\MemMang\heap_2.c</file>\r
+ <file>$PROJ_DIR$\LuminaryDrivers\osram128x64x4.c</file>\r
+ <file>$PROJ_DIR$\..\Common\Minimal\BlockQ.c</file>\r
+ <file>$PROJ_DIR$\..\Common\ethernet\uIP\uip-1.0\uip\uip.c</file>\r
+ <file>$PROJ_DIR$\..\Common\ethernet\uIP\uip-1.0\uip\uip_arp.c</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\integer.r79</file>\r
+ <file>$PROJ_DIR$\webserver\uIP_Task.c</file>\r
+ <file>$PROJ_DIR$\LuminaryDrivers\osram128x64x4.h</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\uIP_Task.r79</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\port.pbi</file>\r
+ <file>$PROJ_DIR$\..\..\..\..\..\Demo\CORTEX_LM3S6965_IAR\main.c</file>\r
+ <file>$PROJ_DIR$\..\..\Source\include\list.h</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\PollQ.r79</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\httpd.pbi</file>\r
+ <file>$PROJ_DIR$\..\Common\ethernet\uIP\uip-1.0\uip\lc.h</file>\r
+ <file>$PROJ_DIR$\..\..\Source\tasks.c</file>\r
+ <file>$PROJ_DIR$\startup_ewarm.c</file>\r
+ <file>$PROJ_DIR$\..\Common\Minimal\blocktim.c</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\startup_ewarm.r79</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\flash.r79</file>\r
+ <file>$PROJ_DIR$\LuminaryDrivers\sysctl.h</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\tasks.r79</file>\r
+ <file>$PROJ_DIR$\webserver\http-strings.h</file>\r
+ <file>$PROJ_DIR$\..\Common\include\integer.h</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\queue.r79</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\port.r79</file>\r
+ <file>$PROJ_DIR$\..\..\Source\portable\IAR\ARM_CM3\port.c</file>\r
+ <file>$PROJ_DIR$\Debug\Exe\RTOSDemo.d79</file>\r
+ <file>$PROJ_DIR$\LuminaryDrivers\LMI_timer.h</file>\r
+ <file>$PROJ_DIR$\LuminaryDrivers\debug.h</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\ParTest.r79</file>\r
+ <file>$TOOLKIT_DIR$\inc\DLib_Product.h</file>\r
+ <file>$PROJ_DIR$\Debug\Exe\RTOSDemo.sim</file>\r
+ <file>$PROJ_DIR$\LuminaryDrivers\pdc.h</file>\r
+ <file>$PROJ_DIR$\webserver\emac.h</file>\r
+ <file>$PROJ_DIR$\webserver\httpd.c</file>\r
+ <file>$PROJ_DIR$\..\Common\ethernet\uIP\uip-1.0\uip\psock.c</file>\r
+ <file>$PROJ_DIR$\..\Common\ethernet\uIP\uip-1.0\uip\timer.c</file>\r
+ <file>$PROJ_DIR$\LuminaryDrivers\hw_ethernet.h</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\httpd-fs.r79</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\ParTest.pbi</file>\r
+ <file>$PROJ_DIR$\..\Common\ethernet\uIP\uip-1.0\uip\timer.h</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\psock.r79</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\http-strings.r79</file>\r
+ <file>$PROJ_DIR$\..\Common\include\partest.h</file>\r
+ <file>$PROJ_DIR$\..\Common\Minimal\integer.c</file>\r
+ <file>$PROJ_DIR$\..\Common\ethernet\uIP\uip-1.0\uip\pt.h</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\list.pbi</file>\r
+ <file>$PROJ_DIR$\..\..\Source\include\croutine.h</file>\r
+ <file>$PROJ_DIR$\LuminaryDrivers\ethernet.h</file>\r
+ <file>$TOOLKIT_DIR$\inc\stdio.h</file>\r
+ <file>$PROJ_DIR$\..\Common\Minimal\flash.c</file>\r
+ <file>$PROJ_DIR$\..\Common\include\flash.h</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\psock.pbi</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\emac.pbi</file>\r
+ <file>$PROJ_DIR$\LuminaryDrivers\driverlib.r79</file>\r
+ <file>$PROJ_DIR$\..\Common\Minimal\PollQ.c</file>\r
+ <file>$PROJ_DIR$\webserver\httpd.h</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\integer.pbi</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\RTOSDemo.pbd</file>\r
+ <file>$PROJ_DIR$\..\Common\include\PollQ.h</file>\r
+ <file>$PROJ_DIR$\..\Common\ethernet\uIP\uip-1.0\uip\uip.h</file>\r
+ <file>$PROJ_DIR$\webserver\uip-conf.h</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\semtest.pbi</file>\r
+ <file>$PROJ_DIR$\RTOSDemo.xcl</file>\r
+ <file>$TOOLKIT_DIR$\inc\string.h</file>\r
+ <file>$PROJ_DIR$\..\Common\include\semtest.h</file>\r
+ <file>$TOOLKIT_DIR$\inc\DLib_Threads.h</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\uip_arp.r79</file>\r
+ <file>$PROJ_DIR$\webserver\clock-arch.h</file>\r
+ <file>$PROJ_DIR$\..\Common\ethernet\uIP\uip-1.0\uip\lc-switch.h</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\death.r79</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\httpd.r79</file>\r
+ <file>$PROJ_DIR$\webserver\httpd-cgi.c</file>\r
+ <file>$PROJ_DIR$\webserver\httpd-fs.c</file>\r
+ <file>$PROJ_DIR$\LuminaryDrivers\hw_ssi.h</file>\r
+ <file>$PROJ_DIR$\FreeRTOSConfig.h</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\heap_2.pbi</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\queue.pbi</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\httpd-fs.pbi</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\osram128x64x4.r79</file>\r
+ <file>$PROJ_DIR$\LuminaryDrivers\hw_sysctl.h</file>\r
+ <file>$PROJ_DIR$\webserver\httpd-cgi.h</file>\r
+ <file>$PROJ_DIR$\..\..\Source\include\task.h</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\list.r79</file>\r
+ <file>$PROJ_DIR$\webserver\emac.c</file>\r
+ <file>$PROJ_DIR$\webserver\http-strings.c</file>\r
+ <file>$PROJ_DIR$\..\Common\ethernet\uIP\uip-1.0\uip\psock.h</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\BlockQ.pbi</file>\r
+ <file>$PROJ_DIR$\LuminaryDrivers\ssi.h</file>\r
+ <file>$PROJ_DIR$\..\..\Source\include\FreeRTOS.h</file>\r
+ <file>$PROJ_DIR$\..\..\Source\include\semphr.h</file>\r
+ <file>$PROJ_DIR$\..\Common\ethernet\uIP\uip-1.0\uip\clock.h</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\startup_ewarm.pbi</file>\r
+ <file>$PROJ_DIR$\..\..\Source\portable\IAR\ARM_CM3\portmacro.h</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\death.pbi</file>\r
+ <file>$PROJ_DIR$\LuminaryDrivers\gpio.h</file>\r
+ <file>$TOOLKIT_DIR$\inc\xencoding_limits.h</file>\r
+ <file>$PROJ_DIR$\LuminaryDrivers\hw_types.h</file>\r
+ <file>$TOOLKIT_DIR$\lib\dl7mptnnl8n.r79</file>\r
+ <file>$TOOLKIT_DIR$\inc\stdint.h</file>\r
+ <file>$PROJ_DIR$\ParTest\ParTest.c</file>\r
+ <file>$PROJ_DIR$\..\Common\Minimal\semtest.c</file>\r
+ <file>$PROJ_DIR$\main.c</file>\r
+ <file>$PROJ_DIR$\..\Common\Minimal\death.c</file>\r
+ <file>$TOOLKIT_DIR$\inc\stddef.h</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\timertest.r79</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\uip.r79</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\http-strings.pbi</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\timertest.pbi</file>\r
+ <file>$PROJ_DIR$\LuminaryDrivers\pdc.c</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\uip.pbi</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\main.pbi</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\pdc.r79</file>\r
+ <file>$PROJ_DIR$\webserver\httpd-fsdata.h</file>\r
+ <file>$PROJ_DIR$\LuminaryDrivers\interrupt.h</file>\r
+ <file>$PROJ_DIR$\..\Common\include\BlockQ.h</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\timer.pbi</file>\r
+ <file>$PROJ_DIR$\LuminaryDrivers\hw_memmap.h</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\main.r79</file>\r
+ <file>$TOOLKIT_DIR$\inc\ysizet.h</file>\r
+ <file>$PROJ_DIR$\webserver\httpd-fsdata.c</file>\r
+ <file>$PROJ_DIR$\bitmap.h</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\BlockQ.r79</file>\r
+ <file>$PROJ_DIR$\..\..\Source\include\portable.h</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\portasm.r79</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\osram128x64x4.pbi</file>\r
+ <file>$TOOLKIT_DIR$\inc\yvals.h</file>\r
+ <file>$PROJ_DIR$\..\Common\ethernet\uIP\uip-1.0\uip\uip_arp.h</file>\r
+ <file>$PROJ_DIR$\webserver\httpd-fs.h</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\PollQ.pbi</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\blocktim.pbi</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\timer.r79</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\semtest.r79</file>\r
+ <file>$PROJ_DIR$\..\Common\ethernet\uIP\uip-1.0\uip\uip_arch.h</file>\r
+ <file>$PROJ_DIR$\lcd_message.h</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\httpd-cgi.pbi</file>\r
+ <file>$PROJ_DIR$\webserver\webserver.h</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\httpd-cgi.r79</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\emac.r79</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\uip_arp.pbi</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\tasks.pbi</file>\r
+ <file>$PROJ_DIR$\..\Common\ethernet\uIP\uip-1.0\uip\uipopt.h</file>\r
+ <file>$PROJ_DIR$\LuminaryDrivers\hw_ints.h</file>\r
+ <file>$TOOLKIT_DIR$\inc\DLib_Defaults.h</file>\r
+ <file>$TOOLKIT_DIR$\lib\dl7mptnnl8n.h</file>\r
+ <file>$PROJ_DIR$\..\Common\include\blocktim.h</file>\r
+ <file>$PROJ_DIR$\..\Common\include\death.h</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\flash.pbi</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\uIP_Task.pbi</file>\r
+ <file>$PROJ_DIR$\..\..\Source\include\projdefs.h</file>\r
+ <file>$TOOLKIT_DIR$\inc\stdlib.h</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\blocktim.r79</file>\r
+ <file>$PROJ_DIR$\..\..\Source\include\queue.h</file>\r
+ <file>$PROJ_DIR$\Debug\Obj\pdc.pbi</file>\r
+ </outputs>\r
+ <file>\r
+ <name>$PROJ_DIR$\timertest.c</name>\r
+ <outputs>\r
+ <tool>\r
+ <name>ICCARM</name>\r
+ <file> 111</file>\r
+ </tool>\r
+ <tool>\r
+ <name>BICOMP</name>\r
+ <file> 114</file>\r
+ </tool>\r
+ </outputs>\r
+ <inputs>\r
+ <tool>\r
+ <name>ICCARM</name>\r
+ <file> 95 110 132 149 150 36 102 72 125 155 81 129 99 148 123 103 120 25 33</file>\r
+ </tool>\r
+ <tool>\r
+ <name>BICOMP</name>\r
+ <file> 95 110 132 149 36 102 72 125 155 81 129 99 148 123 103 120 25 33</file>\r
+ </tool>\r
+ </inputs>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Source\portable\IAR\ARM_CM3\portasm.s</name>\r
+ <outputs>\r
+ <tool>\r
+ <name>AARM</name>\r
+ <file> 130</file>\r
+ </tool>\r
+ </outputs>\r
+ <inputs>\r
+ <tool>\r
+ <name>AARM</name>\r
+ <file> 81</file>\r
+ </tool>\r
+ </inputs>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Source\queue.c</name>\r
+ <outputs>\r
+ <tool>\r
+ <name>ICCARM</name>\r
+ <file> 29</file>\r
+ </tool>\r
+ <tool>\r
+ <name>BICOMP</name>\r
+ <file> 83</file>\r
+ </tool>\r
+ </outputs>\r
+ <inputs>\r
+ <tool>\r
+ <name>ICCARM</name>\r
+ <file> 156 132 149 150 36 102 72 125 70 95 110 155 81 129 99 88 16 53</file>\r
+ </tool>\r
+ <tool>\r
+ <name>BICOMP</name>\r
+ <file> 156 132 149 36 102 72 125 70 95 110 155 81 129 99 88 16 53</file>\r
+ </tool>\r
+ </inputs>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Source\list.c</name>\r
+ <outputs>\r
+ <tool>\r
+ <name>ICCARM</name>\r
+ <file> 89</file>\r
+ </tool>\r
+ <tool>\r
+ <name>BICOMP</name>\r
+ <file> 52</file>\r
+ </tool>\r
+ </outputs>\r
+ <inputs>\r
+ <tool>\r
+ <name>ICCARM</name>\r
+ <file> 156 132 149 150 36 102 72 125 95 110 155 81 129 99 16</file>\r
+ </tool>\r
+ <tool>\r
+ <name>BICOMP</name>\r
+ <file> 156 132 149 36 102 72 125 95 110 155 81 129 99 16</file>\r
+ </tool>\r
+ </inputs>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Source\portable\MemMang\heap_2.c</name>\r
+ <outputs>\r
+ <tool>\r
+ <name>ICCARM</name>\r
+ <file> 3</file>\r
+ </tool>\r
+ <tool>\r
+ <name>BICOMP</name>\r
+ <file> 82</file>\r
+ </tool>\r
+ </outputs>\r
+ <inputs>\r
+ <tool>\r
+ <name>ICCARM</name>\r
+ <file> 156 132 149 150 36 102 72 125 95 110 155 81 129 99 88 16</file>\r
+ </tool>\r
+ <tool>\r
+ <name>BICOMP</name>\r
+ <file> 156 132 149 36 102 72 125 95 110 155 81 129 99 88 16</file>\r
+ </tool>\r
+ </inputs>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\LuminaryDrivers\osram128x64x4.c</name>\r
+ <outputs>\r
+ <tool>\r
+ <name>ICCARM</name>\r
+ <file> 85</file>\r
+ </tool>\r
+ <tool>\r
+ <name>BICOMP</name>\r
+ <file> 131</file>\r
+ </tool>\r
+ </outputs>\r
+ <inputs>\r
+ <tool>\r
+ <name>ICCARM</name>\r
+ <file> 80 123 86 103 34 101 94 25 12</file>\r
+ </tool>\r
+ <tool>\r
+ <name>BICOMP</name>\r
+ <file> 80 123 86 103 34 101 94 25 12</file>\r
+ </tool>\r
+ </inputs>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\Common\Minimal\BlockQ.c</name>\r
+ <outputs>\r
+ <tool>\r
+ <name>ICCARM</name>\r
+ <file> 128</file>\r
+ </tool>\r
+ <tool>\r
+ <name>BICOMP</name>\r
+ <file> 93</file>\r
+ </tool>\r
+ </outputs>\r
+ <inputs>\r
+ <tool>\r
+ <name>ICCARM</name>\r
+ <file> 156 132 149 150 36 102 72 125 95 110 155 81 129 99 88 16 158 121</file>\r
+ </tool>\r
+ <tool>\r
+ <name>BICOMP</name>\r
+ <file> 156 132 149 36 102 72 125 95 110 155 81 129 99 88 16 158 121</file>\r
+ </tool>\r
+ </inputs>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\Common\ethernet\uIP\uip-1.0\uip\uip.c</name>\r
+ <outputs>\r
+ <tool>\r
+ <name>ICCARM</name>\r
+ <file> 112</file>\r
+ </tool>\r
+ <tool>\r
+ <name>BICOMP</name>\r
+ <file> 116</file>\r
+ </tool>\r
+ </outputs>\r
+ <inputs>\r
+ <tool>\r
+ <name>ICCARM</name>\r
+ <file> 66 147 67 105 132 149 150 36 102 72 142 62 92 51 19 75 134 139 70 125</file>\r
+ </tool>\r
+ <tool>\r
+ <name>BICOMP</name>\r
+ <file> 66 147 67 105 132 149 36 102 72 142 62 92 51 19 75 134 139 70 125</file>\r
+ </tool>\r
+ </inputs>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\Common\ethernet\uIP\uip-1.0\uip\uip_arp.c</name>\r
+ <outputs>\r
+ <tool>\r
+ <name>ICCARM</name>\r
+ <file> 73</file>\r
+ </tool>\r
+ <tool>\r
+ <name>BICOMP</name>\r
+ <file> 145</file>\r
+ </tool>\r
+ </outputs>\r
+ <inputs>\r
+ <tool>\r
+ <name>ICCARM</name>\r
+ <file> 133 66 147 67 105 132 149 150 36 102 72 142 62 92 51 19 75 134 70 125</file>\r
+ </tool>\r
+ <tool>\r
+ <name>BICOMP</name>\r
+ <file> 133 66 147 67 105 132 149 36 102 72 142 62 92 51 19 75 134 70 125</file>\r
+ </tool>\r
+ </inputs>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\webserver\uIP_Task.c</name>\r
+ <outputs>\r
+ <tool>\r
+ <name>ICCARM</name>\r
+ <file> 13</file>\r
+ </tool>\r
+ <tool>\r
+ <name>BICOMP</name>\r
+ <file> 154</file>\r
+ </tool>\r
+ </outputs>\r
+ <inputs>\r
+ <tool>\r
+ <name>ICCARM</name>\r
+ <file> 70 132 149 150 36 102 72 125 95 110 155 81 129 99 88 16 96 158 140 103 66 147 67 105 142 62 92 51 19 75 134 133 46 97 74 43 54 123 39 49</file>\r
+ </tool>\r
+ <tool>\r
+ <name>BICOMP</name>\r
+ <file> 70 132 149 36 102 72 125 95 110 155 81 129 99 88 16 96 158 140 103 66 147 67 105 142 62 92 51 19 75 134 133 46 97 74 43 54 123 39 49</file>\r
+ </tool>\r
+ </inputs>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Source\tasks.c</name>\r
+ <outputs>\r
+ <tool>\r
+ <name>ICCARM</name>\r
+ <file> 26</file>\r
+ </tool>\r
+ <tool>\r
+ <name>BICOMP</name>\r
+ <file> 146</file>\r
+ </tool>\r
+ </outputs>\r
+ <inputs>\r
+ <tool>\r
+ <name>ICCARM</name>\r
+ <file> 55 132 149 150 36 102 72 125 156 70 95 110 155 81 129 99 88 16</file>\r
+ </tool>\r
+ <tool>\r
+ <name>BICOMP</name>\r
+ <file> 55 132 149 36 102 72 125 156 70 95 110 155 81 129 99 88 16</file>\r
+ </tool>\r
+ </inputs>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\startup_ewarm.c</name>\r
+ <outputs>\r
+ <tool>\r
+ <name>ICCARM</name>\r
+ <file> 23</file>\r
+ </tool>\r
+ <tool>\r
+ <name>BICOMP</name>\r
+ <file> 98</file>\r
+ </tool>\r
+ </outputs>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\Common\Minimal\blocktim.c</name>\r
+ <outputs>\r
+ <tool>\r
+ <name>ICCARM</name>\r
+ <file> 157</file>\r
+ </tool>\r
+ <tool>\r
+ <name>BICOMP</name>\r
+ <file> 136</file>\r
+ </tool>\r
+ </outputs>\r
+ <inputs>\r
+ <tool>\r
+ <name>ICCARM</name>\r
+ <file> 95 110 132 149 150 36 102 72 125 155 81 129 99 88 16 158</file>\r
+ </tool>\r
+ <tool>\r
+ <name>BICOMP</name>\r
+ <file> 95 110 132 149 36 102 72 125 155 81 129 99 88 16 158</file>\r
+ </tool>\r
+ </inputs>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Source\portable\IAR\ARM_CM3\port.c</name>\r
+ <outputs>\r
+ <tool>\r
+ <name>ICCARM</name>\r
+ <file> 30</file>\r
+ </tool>\r
+ <tool>\r
+ <name>BICOMP</name>\r
+ <file> 14</file>\r
+ </tool>\r
+ </outputs>\r
+ <inputs>\r
+ <tool>\r
+ <name>ICCARM</name>\r
+ <file> 95 110 132 149 150 36 102 72 125 155 81 129 99 88 16</file>\r
+ </tool>\r
+ <tool>\r
+ <name>BICOMP</name>\r
+ <file> 95 110 132 149 36 102 72 125 155 81 129 99 88 16</file>\r
+ </tool>\r
+ </inputs>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\Debug\Exe\RTOSDemo.d79</name>\r
+ <outputs>\r
+ <tool>\r
+ <name>XLINK</name>\r
+ <file> 37</file>\r
+ </tool>\r
+ </outputs>\r
+ <inputs>\r
+ <tool>\r
+ <name>XLINK</name>\r
+ <file> 69 128 35 17 157 76 144 24 3 48 143 44 77 10 89 124 85 30 130 47 29 138 23 26 137 111 13 112 73 60 104</file>\r
+ </tool>\r
+ </inputs>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\webserver\httpd.c</name>\r
+ <outputs>\r
+ <tool>\r
+ <name>ICCARM</name>\r
+ <file> 77</file>\r
+ </tool>\r
+ <tool>\r
+ <name>BICOMP</name>\r
+ <file> 18</file>\r
+ </tool>\r
+ </outputs>\r
+ <inputs>\r
+ <tool>\r
+ <name>ICCARM</name>\r
+ <file> 66 147 67 105 132 149 150 36 102 72 142 62 92 51 19 75 134 87 27 70 125</file>\r
+ </tool>\r
+ <tool>\r
+ <name>BICOMP</name>\r
+ <file> 66 147 67 105 132 149 36 102 72 142 62 92 51 19 75 134 87 27 70 125</file>\r
+ </tool>\r
+ </inputs>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\Common\ethernet\uIP\uip-1.0\uip\psock.c</name>\r
+ <outputs>\r
+ <tool>\r
+ <name>ICCARM</name>\r
+ <file> 47</file>\r
+ </tool>\r
+ <tool>\r
+ <name>BICOMP</name>\r
+ <file> 58</file>\r
+ </tool>\r
+ </outputs>\r
+ <inputs>\r
+ <tool>\r
+ <name>ICCARM</name>\r
+ <file> 55 132 149 150 36 102 72 125 70 147 67 105 142 62 92 51 19 75 134 66</file>\r
+ </tool>\r
+ <tool>\r
+ <name>BICOMP</name>\r
+ <file> 55 132 149 36 102 72 125 70 147 67 105 142 62 92 51 19 75 134 66</file>\r
+ </tool>\r
+ </inputs>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\Common\ethernet\uIP\uip-1.0\uip\timer.c</name>\r
+ <outputs>\r
+ <tool>\r
+ <name>ICCARM</name>\r
+ <file> 137</file>\r
+ </tool>\r
+ <tool>\r
+ <name>BICOMP</name>\r
+ <file> 122</file>\r
+ </tool>\r
+ </outputs>\r
+ <inputs>\r
+ <tool>\r
+ <name>ICCARM</name>\r
+ <file> 97 74 95 110 132 149 150 36 102 72 125 155 81 129 99 46</file>\r
+ </tool>\r
+ <tool>\r
+ <name>BICOMP</name>\r
+ <file> 97 74 95 110 132 149 36 102 72 125 155 81 129 99 46</file>\r
+ </tool>\r
+ </inputs>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\Common\Minimal\integer.c</name>\r
+ <outputs>\r
+ <tool>\r
+ <name>ICCARM</name>\r
+ <file> 10</file>\r
+ </tool>\r
+ <tool>\r
+ <name>BICOMP</name>\r
+ <file> 63</file>\r
+ </tool>\r
+ </outputs>\r
+ <inputs>\r
+ <tool>\r
+ <name>ICCARM</name>\r
+ <file> 156 132 149 150 36 102 72 125 95 110 155 81 129 99 88 16 28</file>\r
+ </tool>\r
+ <tool>\r
+ <name>BICOMP</name>\r
+ <file> 156 132 149 36 102 72 125 95 110 155 81 129 99 88 16 28</file>\r
+ </tool>\r
+ </inputs>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\Common\Minimal\flash.c</name>\r
+ <outputs>\r
+ <tool>\r
+ <name>ICCARM</name>\r
+ <file> 24</file>\r
+ </tool>\r
+ <tool>\r
+ <name>BICOMP</name>\r
+ <file> 153</file>\r
+ </tool>\r
+ </outputs>\r
+ <inputs>\r
+ <tool>\r
+ <name>ICCARM</name>\r
+ <file> 156 132 149 150 36 102 72 125 95 110 155 81 129 99 88 16 49 57</file>\r
+ </tool>\r
+ <tool>\r
+ <name>BICOMP</name>\r
+ <file> 156 132 149 36 102 72 125 95 110 155 81 129 99 88 16 49 57</file>\r
+ </tool>\r
+ </inputs>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\Common\Minimal\PollQ.c</name>\r
+ <outputs>\r
+ <tool>\r
+ <name>ICCARM</name>\r
+ <file> 17</file>\r
+ </tool>\r
+ <tool>\r
+ <name>BICOMP</name>\r
+ <file> 135</file>\r
+ </tool>\r
+ </outputs>\r
+ <inputs>\r
+ <tool>\r
+ <name>ICCARM</name>\r
+ <file> 156 132 149 150 36 102 72 125 95 110 155 81 129 99 88 16 158 65</file>\r
+ </tool>\r
+ <tool>\r
+ <name>BICOMP</name>\r
+ <file> 156 132 149 36 102 72 125 95 110 155 81 129 99 88 16 158 65</file>\r
+ </tool>\r
+ </inputs>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\Debug\Obj\RTOSDemo.pbd</name>\r
+ <inputs>\r
+ <tool>\r
+ <name>BILINK</name>\r
+ <file> 93 45 135 136 100 59 153 82 113 141 84 18 63 52 117 131 14 58 83 68 98 146 122 114 154 116 145</file>\r
+ </tool>\r
+ </inputs>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\webserver\httpd-cgi.c</name>\r
+ <outputs>\r
+ <tool>\r
+ <name>ICCARM</name>\r
+ <file> 143</file>\r
+ </tool>\r
+ <tool>\r
+ <name>BICOMP</name>\r
+ <file> 141</file>\r
+ </tool>\r
+ </outputs>\r
+ <inputs>\r
+ <tool>\r
+ <name>ICCARM</name>\r
+ <file> 66 147 67 105 132 149 150 36 102 72 142 62 92 51 19 75 134 87 55 125 70</file>\r
+ </tool>\r
+ <tool>\r
+ <name>BICOMP</name>\r
+ <file> 66 147 67 105 132 149 36 102 72 142 62 92 51 19 75 134 87 55 125 70</file>\r
+ </tool>\r
+ </inputs>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\webserver\httpd-fs.c</name>\r
+ <outputs>\r
+ <tool>\r
+ <name>ICCARM</name>\r
+ <file> 44</file>\r
+ </tool>\r
+ <tool>\r
+ <name>BICOMP</name>\r
+ <file> 84</file>\r
+ </tool>\r
+ </outputs>\r
+ <inputs>\r
+ <tool>\r
+ <name>ICCARM</name>\r
+ <file> 62 92 147 67 105 132 149 150 36 102 72 142 51 19 75 134 119 66 126</file>\r
+ </tool>\r
+ <tool>\r
+ <name>BICOMP</name>\r
+ <file> 62 92 147 67 105 132 149 36 102 72 142 51 19 75 134 119 66 126</file>\r
+ </tool>\r
+ </inputs>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\webserver\emac.c</name>\r
+ <outputs>\r
+ <tool>\r
+ <name>ICCARM</name>\r
+ <file> 144</file>\r
+ </tool>\r
+ <tool>\r
+ <name>BICOMP</name>\r
+ <file> 59</file>\r
+ </tool>\r
+ </outputs>\r
+ <inputs>\r
+ <tool>\r
+ <name>ICCARM</name>\r
+ <file> 95 110 132 149 150 36 102 72 125 155 81 129 99 96 158 88 16 39 66 147 67 105 142 62 92 51 19 75 134 103 123 148 43 54 120</file>\r
+ </tool>\r
+ <tool>\r
+ <name>BICOMP</name>\r
+ <file> 95 110 132 149 36 102 72 125 155 81 129 99 96 158 88 16 39 66 147 67 105 142 62 92 51 19 75 134 103 123 148 43 54 120</file>\r
+ </tool>\r
+ </inputs>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\webserver\http-strings.c</name>\r
+ <outputs>\r
+ <tool>\r
+ <name>ICCARM</name>\r
+ <file> 48</file>\r
+ </tool>\r
+ <tool>\r
+ <name>BICOMP</name>\r
+ <file> 113</file>\r
+ </tool>\r
+ </outputs>\r
+ </file>\r
+ <file>\r
+ <name>[ROOT_NODE]</name>\r
+ <outputs>\r
+ <tool>\r
+ <name>XLINK</name>\r
+ <file> 37 32</file>\r
+ </tool>\r
+ </outputs>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\ParTest\ParTest.c</name>\r
+ <outputs>\r
+ <tool>\r
+ <name>ICCARM</name>\r
+ <file> 35</file>\r
+ </tool>\r
+ <tool>\r
+ <name>BICOMP</name>\r
+ <file> 45</file>\r
+ </tool>\r
+ </outputs>\r
+ <inputs>\r
+ <tool>\r
+ <name>ICCARM</name>\r
+ <file> 95 110 132 149 150 36 102 72 125 155 81 129 99 88 16 49 103 101 123</file>\r
+ </tool>\r
+ <tool>\r
+ <name>BICOMP</name>\r
+ <file> 95 110 132 149 36 102 72 125 155 81 129 99 88 16 49 103 101 123</file>\r
+ </tool>\r
+ </inputs>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\Common\Minimal\semtest.c</name>\r
+ <outputs>\r
+ <tool>\r
+ <name>ICCARM</name>\r
+ <file> 138</file>\r
+ </tool>\r
+ <tool>\r
+ <name>BICOMP</name>\r
+ <file> 68</file>\r
+ </tool>\r
+ </outputs>\r
+ <inputs>\r
+ <tool>\r
+ <name>ICCARM</name>\r
+ <file> 156 132 149 150 36 102 72 125 95 110 155 81 129 99 88 16 96 158 71</file>\r
+ </tool>\r
+ <tool>\r
+ <name>BICOMP</name>\r
+ <file> 156 132 149 36 102 72 125 95 110 155 81 129 99 88 16 96 158 71</file>\r
+ </tool>\r
+ </inputs>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\main.c</name>\r
+ <outputs>\r
+ <tool>\r
+ <name>ICCARM</name>\r
+ <file> 124</file>\r
+ </tool>\r
+ <tool>\r
+ <name>BICOMP</name>\r
+ <file> 117</file>\r
+ </tool>\r
+ </outputs>\r
+ <inputs>\r
+ <tool>\r
+ <name>ICCARM</name>\r
+ <file> 55 132 149 150 36 102 72 125 95 110 155 81 129 99 88 16 158 96 121 152 28 151 57 49 71 65 140 127 123 103 25 101 12</file>\r
+ </tool>\r
+ <tool>\r
+ <name>BICOMP</name>\r
+ <file> 55 132 149 36 102 72 125 95 110 155 81 129 99 88 16 158 96 121 152 28 151 57 49 71 65 140 127 123 103 25 101 12</file>\r
+ </tool>\r
+ </inputs>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\Common\Minimal\death.c</name>\r
+ <outputs>\r
+ <tool>\r
+ <name>ICCARM</name>\r
+ <file> 76</file>\r
+ </tool>\r
+ <tool>\r
+ <name>BICOMP</name>\r
+ <file> 100</file>\r
+ </tool>\r
+ </outputs>\r
+ <inputs>\r
+ <tool>\r
+ <name>ICCARM</name>\r
+ <file> 156 132 149 150 36 102 72 125 95 110 155 81 129 99 88 16 152</file>\r
+ </tool>\r
+ <tool>\r
+ <name>BICOMP</name>\r
+ <file> 156 132 149 36 102 72 125 95 110 155 81 129 99 88 16 152</file>\r
+ </tool>\r
+ </inputs>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\LuminaryDrivers\pdc.c</name>\r
+ <outputs>\r
+ <tool>\r
+ <name>ICCARM</name>\r
+ <file> 118</file>\r
+ </tool>\r
+ <tool>\r
+ <name>BICOMP</name>\r
+ <file> 159</file>\r
+ </tool>\r
+ </outputs>\r
+ <inputs>\r
+ <tool>\r
+ <name>ICCARM</name>\r
+ <file> 123 103 34 101 94 25 38</file>\r
+ </tool>\r
+ <tool>\r
+ <name>BICOMP</name>\r
+ <file> 123 103 34 101 94 25 38</file>\r
+ </tool>\r
+ </inputs>\r
+ </file>\r
+ <forcedrebuild>\r
+ <name>[MULTI_TOOL]</name>\r
+ <tool>XLINK</tool>\r
+ </forcedrebuild>\r
+ </configuration>\r
+ <configuration>\r
+ <name>Release</name>\r
+ <outputs/>\r
+ <forcedrebuild>\r
+ <name>[MULTI_TOOL]</name>\r
+ <tool>XLINK</tool>\r
+ </forcedrebuild>\r
+ </configuration>\r
+</project>\r
+\r
+\r
--- /dev/null
+<?xml version="1.0" encoding="iso-8859-1"?>\r
+\r
+<project>\r
+ <fileVersion>1</fileVersion>\r
+ <configuration>\r
+ <name>Debug</name>\r
+ <toolchain>\r
+ <name>ARM</name>\r
+ </toolchain>\r
+ <debug>1</debug>\r
+ <settings>\r
+ <name>C-SPY</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>13</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>CInput</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CEndian</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CProcessor</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OCVariant</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>MacOverride</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>MacFile</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>MemOverride</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>MemFile</name>\r
+ <state>$TOOLKIT_DIR$\CONFIG\iolm3s828.ddf</state>\r
+ </option>\r
+ <option>\r
+ <name>RunToEnable</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>RunToName</name>\r
+ <state>main</state>\r
+ </option>\r
+ <option>\r
+ <name>CExtraOptionsCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CExtraOptions</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CFpuProcessor</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDDFArgumentProducer</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OCDownloadSuppressDownload</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDownloadVerifyAll</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OCProductVersion</name>\r
+ <state>4.41A</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDynDriverList</name>\r
+ <state>LMIFTDI_ID</state>\r
+ </option>\r
+ <option>\r
+ <name>OCLastSavedByProductVersion</name>\r
+ <state>4.41A</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDownloadAttachToProgram</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>FlashLoaders</name>\r
+ <state>,,,,(default),</state>\r
+ </option>\r
+ <option>\r
+ <name>UseFlashLoader</name>\r
+ <state>1</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>ARMSIM_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>0</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>OCSimDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>ANGEL_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>0</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>CCAngelHeartbeat</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CAngelCommunication</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CAngelCommBaud</name>\r
+ <version>0</version>\r
+ <state>3</state>\r
+ </option>\r
+ <option>\r
+ <name>CAngelCommPort</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>ANGELTCPIP</name>\r
+ <state>aaa.bbb.ccc.ddd</state>\r
+ </option>\r
+ <option>\r
+ <name>DoAngelLogfile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AngelLogFile</name>\r
+ <state>$TOOLKIT_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>IARROM_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>0</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>CRomLogFileCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CRomLogFileEditB</name>\r
+ <state>$TOOLKIT_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>CRomCommunication</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CRomCommPort</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CRomCommBaud</name>\r
+ <version>0</version>\r
+ <state>7</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>JLINK_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>6</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>JLinkSpeed</name>\r
+ <state>32</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkDoLogfile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkLogFile</name>\r
+ <state>$TOOLKIT_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkHWResetDelay</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>JLinkInitialSpeed</name>\r
+ <state>32</state>\r
+ </option>\r
+ <option>\r
+ <name>CCDoJlinkMultiTarget</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCScanChainNonARMDevices</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkMultiTarget</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkIRLength</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkCommRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkTCPIP</name>\r
+ <state>aaa.bbb.ccc.ddd</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkResetRadio</name>\r
+ <state>2</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkResetInitSeq</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkSpeedRadioV2</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCUSBDevice</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchReset</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchUndef</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchSWI</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchData</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchPrefetch</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchIRQ</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchFIQ</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkBreakpointRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkDoUpdateBreakpoints</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkUpdateBreakpoints</name>\r
+ <state>main</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>LMIFTDI_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>0</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>LmiftdiSpeed</name>\r
+ <state>500</state>\r
+ </option>\r
+ <option>\r
+ <name>CCLmiftdiResetRadio</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCLmiftdiDoLogfile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCLmiftdiLogFile</name>\r
+ <state>$TOOLKIT_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>CCLmiftdiBreakpointRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCLmiftdiDoUpdateBreakpoints</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCLmiftdiUpdateBreakpoints</name>\r
+ <state>main</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>MACRAIGOR_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>2</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>jtag</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>EmuSpeed</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>TCPIP</name>\r
+ <state>aaa.bbb.ccc.ddd</state>\r
+ </option>\r
+ <option>\r
+ <name>DoLogfile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>LogFile</name>\r
+ <state>$TOOLKIT_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>DoEmuMultiTarget</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>EmuMultiTarget</name>\r
+ <state>0@ARM7TDMI</state>\r
+ </option>\r
+ <option>\r
+ <name>EmuHWReset</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CEmuCommBaud</name>\r
+ <version>0</version>\r
+ <state>4</state>\r
+ </option>\r
+ <option>\r
+ <name>CEmuCommPort</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>jtago</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>UnusedAddr</name>\r
+ <state>0x00800000</state>\r
+ </option>\r
+ <option>\r
+ <name>CCMacraigorHWResetDelay</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCJTagBreakpointRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJTagDoUpdateBreakpoints</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJTagUpdateBreakpoints</name>\r
+ <state>main</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>RDI_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>1</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>CRDIDriverDll</name>\r
+ <state>Browse to your RDI driver</state>\r
+ </option>\r
+ <option>\r
+ <name>CRDILogFileCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CRDILogFileEdit</name>\r
+ <state>$TOOLKIT_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDIHWReset</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchReset</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchUndef</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchSWI</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchData</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchPrefetch</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchIRQ</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchFIQ</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDIUseETM</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>THIRDPARTY_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>0</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>CThirdPartyDriverDll</name>\r
+ <state>Browse to your third-party driver</state>\r
+ </option>\r
+ <option>\r
+ <name>CThirdPartyLogFileCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CThirdPartyLogFileEditB</name>\r
+ <state>$TOOLKIT_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <debuggerPlugins>\r
+ <plugin>\r
+ <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ewplugin</file>\r
+ <loadFlag>1</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$EW_DIR$\common\plugins\Orti\Orti.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$EW_DIR$\common\plugins\Profiling\Profiling.ewplugin</file>\r
+ <loadFlag>1</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$EW_DIR$\common\plugins\Stack\Stack.ewplugin</file>\r
+ <loadFlag>1</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CMXArmPlugin.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CMXTinyArmPlugin.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\OSE\OseEpsilonPlugin.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\PowerPac\PowerPacRTOS.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ </debuggerPlugins>\r
+ </configuration>\r
+ <configuration>\r
+ <name>Release</name>\r
+ <toolchain>\r
+ <name>ARM</name>\r
+ </toolchain>\r
+ <debug>0</debug>\r
+ <settings>\r
+ <name>C-SPY</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>13</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>0</debug>\r
+ <option>\r
+ <name>CInput</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CEndian</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CProcessor</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OCVariant</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>MacOverride</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>MacFile</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>MemOverride</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>MemFile</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>RunToEnable</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>RunToName</name>\r
+ <state>main</state>\r
+ </option>\r
+ <option>\r
+ <name>CExtraOptionsCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CExtraOptions</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CFpuProcessor</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDDFArgumentProducer</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OCDownloadSuppressDownload</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDownloadVerifyAll</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCProductVersion</name>\r
+ <state>4.41A</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDynDriverList</name>\r
+ <state>ARMSIM_ID</state>\r
+ </option>\r
+ <option>\r
+ <name>OCLastSavedByProductVersion</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OCDownloadAttachToProgram</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>FlashLoaders</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>UseFlashLoader</name>\r
+ <state>0</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>ARMSIM_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>0</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>0</debug>\r
+ <option>\r
+ <name>OCSimDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>ANGEL_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>0</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>0</debug>\r
+ <option>\r
+ <name>CCAngelHeartbeat</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CAngelCommunication</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CAngelCommBaud</name>\r
+ <version>0</version>\r
+ <state>3</state>\r
+ </option>\r
+ <option>\r
+ <name>CAngelCommPort</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>ANGELTCPIP</name>\r
+ <state>aaa.bbb.ccc.ddd</state>\r
+ </option>\r
+ <option>\r
+ <name>DoAngelLogfile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AngelLogFile</name>\r
+ <state>$TOOLKIT_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>IARROM_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>0</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>0</debug>\r
+ <option>\r
+ <name>CRomLogFileCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CRomLogFileEditB</name>\r
+ <state>$TOOLKIT_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>CRomCommunication</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CRomCommPort</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CRomCommBaud</name>\r
+ <version>0</version>\r
+ <state>7</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>JLINK_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>6</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>0</debug>\r
+ <option>\r
+ <name>JLinkSpeed</name>\r
+ <state>32</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkDoLogfile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkLogFile</name>\r
+ <state>$TOOLKIT_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkHWResetDelay</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>JLinkInitialSpeed</name>\r
+ <state>32</state>\r
+ </option>\r
+ <option>\r
+ <name>CCDoJlinkMultiTarget</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCScanChainNonARMDevices</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkMultiTarget</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkIRLength</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkCommRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkTCPIP</name>\r
+ <state>aaa.bbb.ccc.ddd</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkResetRadio</name>\r
+ <state>2</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkResetInitSeq</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkSpeedRadioV2</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCUSBDevice</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchReset</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchUndef</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchSWI</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchData</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchPrefetch</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchIRQ</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchFIQ</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkBreakpointRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkDoUpdateBreakpoints</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkUpdateBreakpoints</name>\r
+ <state>main</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>LMIFTDI_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>0</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>0</debug>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>LmiftdiSpeed</name>\r
+ <state>500</state>\r
+ </option>\r
+ <option>\r
+ <name>CCLmiftdiResetRadio</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCLmiftdiDoLogfile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCLmiftdiLogFile</name>\r
+ <state>$TOOLKIT_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>CCLmiftdiBreakpointRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCLmiftdiDoUpdateBreakpoints</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCLmiftdiUpdateBreakpoints</name>\r
+ <state>main</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>MACRAIGOR_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>2</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>0</debug>\r
+ <option>\r
+ <name>jtag</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>EmuSpeed</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>TCPIP</name>\r
+ <state>aaa.bbb.ccc.ddd</state>\r
+ </option>\r
+ <option>\r
+ <name>DoLogfile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>LogFile</name>\r
+ <state>$TOOLKIT_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>DoEmuMultiTarget</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>EmuMultiTarget</name>\r
+ <state>0@ARM7TDMI</state>\r
+ </option>\r
+ <option>\r
+ <name>EmuHWReset</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CEmuCommBaud</name>\r
+ <version>0</version>\r
+ <state>4</state>\r
+ </option>\r
+ <option>\r
+ <name>CEmuCommPort</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>jtago</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>UnusedAddr</name>\r
+ <state>0x00800000</state>\r
+ </option>\r
+ <option>\r
+ <name>CCMacraigorHWResetDelay</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCJTagBreakpointRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJTagDoUpdateBreakpoints</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJTagUpdateBreakpoints</name>\r
+ <state>main</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>RDI_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>1</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>0</debug>\r
+ <option>\r
+ <name>CRDIDriverDll</name>\r
+ <state>Browse to your RDI driver</state>\r
+ </option>\r
+ <option>\r
+ <name>CRDILogFileCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CRDILogFileEdit</name>\r
+ <state>$TOOLKIT_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDIHWReset</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchReset</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchUndef</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchSWI</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchData</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchPrefetch</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchIRQ</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchFIQ</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDIUseETM</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>THIRDPARTY_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>0</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>0</debug>\r
+ <option>\r
+ <name>CThirdPartyDriverDll</name>\r
+ <state>Browse to your third-party driver</state>\r
+ </option>\r
+ <option>\r
+ <name>CThirdPartyLogFileCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CThirdPartyLogFileEditB</name>\r
+ <state>$TOOLKIT_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <debuggerPlugins>\r
+ <plugin>\r
+ <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ewplugin</file>\r
+ <loadFlag>1</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$EW_DIR$\common\plugins\Orti\Orti.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$EW_DIR$\common\plugins\Profiling\Profiling.ewplugin</file>\r
+ <loadFlag>1</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$EW_DIR$\common\plugins\Stack\Stack.ewplugin</file>\r
+ <loadFlag>1</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CMXArmPlugin.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CMXTinyArmPlugin.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\OSE\OseEpsilonPlugin.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\PowerPac\PowerPacRTOS.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ </debuggerPlugins>\r
+ </configuration>\r
+</project>\r
+\r
+\r
--- /dev/null
+<?xml version="1.0" encoding="iso-8859-1"?>\r
+\r
+<project>\r
+ <fileVersion>1</fileVersion>\r
+ <configuration>\r
+ <name>Debug</name>\r
+ <toolchain>\r
+ <name>ARM</name>\r
+ </toolchain>\r
+ <debug>1</debug>\r
+ <settings>\r
+ <name>General</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>9</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>OGProductVersion</name>\r
+ <state>4.41A</state>\r
+ </option>\r
+ <option>\r
+ <name>GProcessorMode</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>ExePath</name>\r
+ <state>Debug\Exe</state>\r
+ </option>\r
+ <option>\r
+ <name>ObjPath</name>\r
+ <state>Debug\Obj</state>\r
+ </option>\r
+ <option>\r
+ <name>ListPath</name>\r
+ <state>Debug\List</state>\r
+ </option>\r
+ <option>\r
+ <name>Variant</name>\r
+ <version>5</version>\r
+ <state>25</state>\r
+ </option>\r
+ <option>\r
+ <name>GEndianMode</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>GInterwork</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>GStackAlign</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>Input variant</name>\r
+ <version>1</version>\r
+ <state>3</state>\r
+ </option>\r
+ <option>\r
+ <name>Input description</name>\r
+ <state>No specifier n, no float nor long long, no scan set, no assignment suppressing.</state>\r
+ </option>\r
+ <option>\r
+ <name>Output variant</name>\r
+ <version>0</version>\r
+ <state>2</state>\r
+ </option>\r
+ <option>\r
+ <name>Output description</name>\r
+ <state>No specifier a, A, no specifier n, no float nor long long.</state>\r
+ </option>\r
+ <option>\r
+ <name>GOutputBinary</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>FPU</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OGCoreOrChip</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>GRuntimeLibSelect</name>\r
+ <version>0</version>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>GRuntimeLibSelectSlave</name>\r
+ <version>0</version>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>RTDescription</name>\r
+ <state>Use the normal configuration of the C/C++ runtime library. No locale interface, C locale, no file descriptor support, no multibytes in printf and scanf, and no hex floats in strtod.</state>\r
+ </option>\r
+ <option>\r
+ <name>RTConfigPath</name>\r
+ <state>$TOOLKIT_DIR$\LIB\dl7mptnnl8n.h</state>\r
+ </option>\r
+ <option>\r
+ <name>RTLibraryPath</name>\r
+ <state>$TOOLKIT_DIR$\LIB\dl7mptnnl8n.r79</state>\r
+ </option>\r
+ <option>\r
+ <name>OGLastSavedByProductVersion</name>\r
+ <state>4.41A</state>\r
+ </option>\r
+ <option>\r
+ <name>GeneralMisraRules</name>\r
+ <version>0</version>\r
+ <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>\r
+ </option>\r
+ <option>\r
+ <name>GeneralEnableMisra</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>GeneralMisraVerbose</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OGChipSelectEditMenu</name>\r
+ <state>LM3Sx9xx Luminary LM3Sx9xx</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>ICCARM</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>14</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>CCDefines</name>\r
+ <state>IAR_ARMCM3_LM</state>\r
+ <state>PACK_STRUCT_END=</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPreprocFile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPreprocComments</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPreprocLine</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCListCFile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCListCMnemonics</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCListCMessages</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCListAssFile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCListAssSource</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCEnableRemarks</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCDiagSuppress</name>\r
+ <state>pa082, pe513, pe167, pe550, pe144, pe191, pe177, pa039, pa050</state>\r
+ </option>\r
+ <option>\r
+ <name>CCDiagRemark</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCDiagWarning</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCDiagError</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCObjPrefix</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCOptSizeSpeed</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCOptimization</name>\r
+ <version>0</version>\r
+ <state>2</state>\r
+ </option>\r
+ <option>\r
+ <name>CCAllowList</name>\r
+ <version>1</version>\r
+ <state>1001000</state>\r
+ </option>\r
+ <option>\r
+ <name>CCObjUseModuleName</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCObjModuleName</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCDebugInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IProcessorMode</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IEndianMode</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IProcessor</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IStackAlign</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IInterwork</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IExtraOptionsCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IExtraOptions</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCLangConformance</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSignedPlainChar</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRequirePrototypes</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCMultibyteSupport</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCDiagWarnAreErr</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCompilerRuntimeInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IFpuProcessor</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OutputFile</name>\r
+ <state>$FILE_BNAME$.r79</state>\r
+ </option>\r
+ <option>\r
+ <name>CCLangSelect</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCLibConfigHeader</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCOptSizeSpeedSlave</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCOptimizationSlave</name>\r
+ <version>0</version>\r
+ <state>2</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCodeFunctions</name>\r
+ <state>CODE</state>\r
+ </option>\r
+ <option>\r
+ <name>CCData</name>\r
+ <state>DATA</state>\r
+ </option>\r
+ <option>\r
+ <name>PreInclude</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CompilerMisraRules</name>\r
+ <version>0</version>\r
+ <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>\r
+ </option>\r
+ <option>\r
+ <name>CompilerMisraOverride</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCModuleTypeOverride</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCModuleType</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCModuleTypeCmdlineProducer</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCIncludePath2</name>\r
+ <state>$PROJ_DIR$\</state>\r
+ <state>$PROJ_DIR$\LuminaryDrivers</state>\r
+ <state>$PROJ_DIR$\..\common\include</state>\r
+ <state>$PROJ_DIR$\..\..\source\include</state>\r
+ <state>$PROJ_DIR$\webserver</state>\r
+ <state>$PROJ_DIR$\..\Common\ethernet\uIP\uip-1.0\uip</state>\r
+ </option>\r
+ <option>\r
+ <name>CCStdIncCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCStdIncludePath</name>\r
+ <state>$TOOLKIT_DIR$\INC\</state>\r
+ </option>\r
+ <option>\r
+ <name>CCInlineThreshold</name>\r
+ <version>0</version>\r
+ <state>1</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>AARM</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>7</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>AObjPrefix</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>AEndian</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>ACaseSensitivity</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>MacroChars</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AWarnEnable</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AWarnWhat</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AWarnOne</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>AWarnRange1</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>AWarnRange2</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>ADebug</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>AltRegisterNames</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>ADefines</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>AList</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AListHeader</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>AListing</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>Includes</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>MacDefs</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>MacExps</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>MacExec</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OnlyAssed</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>MultiLine</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>PageLengthCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>PageLength</name>\r
+ <state>80</state>\r
+ </option>\r
+ <option>\r
+ <name>TabSpacing</name>\r
+ <state>8</state>\r
+ </option>\r
+ <option>\r
+ <name>AXRef</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AXRefDefines</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AXRefInternal</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AXRefDual</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AProcessor</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>AFpuProcessor</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>AOutputFile</name>\r
+ <state>$FILE_BNAME$.r79</state>\r
+ </option>\r
+ <option>\r
+ <name>AMultibyteSupport</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>ALimitErrorsCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>ALimitErrorsEdit</name>\r
+ <state>100</state>\r
+ </option>\r
+ <option>\r
+ <name>AIgnoreStdInclude</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AStdIncludes</name>\r
+ <state>$TOOLKIT_DIR$\INC\</state>\r
+ </option>\r
+ <option>\r
+ <name>AUserIncludes</name>\r
+ <state>$PROJ_DIR$\</state>\r
+ </option>\r
+ <option>\r
+ <name>AExtraOptionsCheckV2</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AExtraOptionsV2</name>\r
+ <state></state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>CUSTOM</name>\r
+ <archiveVersion>3</archiveVersion>\r
+ <data>\r
+ <extensions></extensions>\r
+ <cmdline></cmdline>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>BICOMP</name>\r
+ <archiveVersion>0</archiveVersion>\r
+ <data/>\r
+ </settings>\r
+ <settings>\r
+ <name>BUILDACTION</name>\r
+ <archiveVersion>1</archiveVersion>\r
+ <data>\r
+ <prebuild></prebuild>\r
+ <postbuild></postbuild>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>XLINK</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>18</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>XOutOverride</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OutputFile</name>\r
+ <state>RTOSDemo.d79</state>\r
+ </option>\r
+ <option>\r
+ <name>OutputFormat</name>\r
+ <version>11</version>\r
+ <state>16</state>\r
+ </option>\r
+ <option>\r
+ <name>FormatVariant</name>\r
+ <version>7</version>\r
+ <state>16</state>\r
+ </option>\r
+ <option>\r
+ <name>SecondaryOutputFile</name>\r
+ <state>(None for the selected format)</state>\r
+ </option>\r
+ <option>\r
+ <name>XDefines</name>\r
+ <state>__vector_table=0</state>\r
+ </option>\r
+ <option>\r
+ <name>AlwaysOutput</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OverlapWarnings</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>NoGlobalCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>XList</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>SegmentMap</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>ListSymbols</name>\r
+ <state>2</state>\r
+ </option>\r
+ <option>\r
+ <name>PageLengthCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>PageLength</name>\r
+ <state>80</state>\r
+ </option>\r
+ <option>\r
+ <name>XIncludes</name>\r
+ <state>$TOOLKIT_DIR$\LIB\</state>\r
+ </option>\r
+ <option>\r
+ <name>ModuleStatus</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>XclOverride</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>XclFile</name>\r
+ <state>$PROJ_DIR$\RTOSDemo.xcl</state>\r
+ </option>\r
+ <option>\r
+ <name>XclFileSlave</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>DoFill</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>FillerByte</name>\r
+ <state>0xFF</state>\r
+ </option>\r
+ <option>\r
+ <name>DoCrc</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CrcSize</name>\r
+ <version>0</version>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CrcAlgo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CrcPoly</name>\r
+ <state>0x11021</state>\r
+ </option>\r
+ <option>\r
+ <name>CrcCompl</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>RangeCheckAlternatives</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>SuppressAllWarn</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>SuppressDiags</name>\r
+ <state>w6</state>\r
+ </option>\r
+ <option>\r
+ <name>TreatAsWarn</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>TreatAsErr</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>ModuleLocalSym</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CrcBitOrder</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>XExtraOptionsCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>XExtraOptions</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>IncludeSuppressed</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OXLibIOConfig</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>ModuleSummary</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>xcProgramEntryLabel</name>\r
+ <state>ResetISR</state>\r
+ </option>\r
+ <option>\r
+ <name>DebugInformation</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>RuntimeControl</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IoEmulation</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>XcRTLibraryFile</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>AllowExtraOutput</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>GenerateExtraOutput</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>XExtraOutOverride</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>ExtraOutputFile</name>\r
+ <state>RTOSDemo.sim</state>\r
+ </option>\r
+ <option>\r
+ <name>ExtraOutputFormat</name>\r
+ <version>11</version>\r
+ <state>60</state>\r
+ </option>\r
+ <option>\r
+ <name>ExtraFormatVariant</name>\r
+ <version>7</version>\r
+ <state>2</state>\r
+ </option>\r
+ <option>\r
+ <name>xcOverrideProgramEntryLabel</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>xcProgramEntryLabelSelect</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>ListOutputFormat</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>BufferedTermOutput</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OverlaySystemMap</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>RawBinaryFile</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>RawBinarySymbol</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>RawBinarySegment</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>RawBinaryAlign</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>XLinkMisraHandler</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CrcAlign</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CrcInitialValue</name>\r
+ <state>0x0</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>XAR</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>0</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>XARInputs</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>XAROverride</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>XAROutput</name>\r
+ <state>###Unitialized###</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>BILINK</name>\r
+ <archiveVersion>0</archiveVersion>\r
+ <data/>\r
+ </settings>\r
+ </configuration>\r
+ <configuration>\r
+ <name>Release</name>\r
+ <toolchain>\r
+ <name>ARM</name>\r
+ </toolchain>\r
+ <debug>0</debug>\r
+ <settings>\r
+ <name>General</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>9</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>0</debug>\r
+ <option>\r
+ <name>OGProductVersion</name>\r
+ <state>4.41A</state>\r
+ </option>\r
+ <option>\r
+ <name>GProcessorMode</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>ExePath</name>\r
+ <state>Release\Exe</state>\r
+ </option>\r
+ <option>\r
+ <name>ObjPath</name>\r
+ <state>Release\Obj</state>\r
+ </option>\r
+ <option>\r
+ <name>ListPath</name>\r
+ <state>Release\List</state>\r
+ </option>\r
+ <option>\r
+ <name>Variant</name>\r
+ <version>5</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>GEndianMode</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>GInterwork</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>GStackAlign</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>Input variant</name>\r
+ <version>1</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>Input description</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>Output variant</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>Output description</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>GOutputBinary</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>FPU</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OGCoreOrChip</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>GRuntimeLibSelect</name>\r
+ <version>0</version>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>GRuntimeLibSelectSlave</name>\r
+ <version>0</version>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>RTDescription</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>RTConfigPath</name>\r
+ <state>dl-stnl0.r79</state>\r
+ </option>\r
+ <option>\r
+ <name>RTLibraryPath</name>\r
+ <state>dl-stnl0.r79</state>\r
+ </option>\r
+ <option>\r
+ <name>OGLastSavedByProductVersion</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>GeneralMisraRules</name>\r
+ <version>0</version>\r
+ <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>\r
+ </option>\r
+ <option>\r
+ <name>GeneralEnableMisra</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>GeneralMisraVerbose</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OGChipSelectEditMenu</name>\r
+ <state>LPC2106 NXP LPC2106</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>ICCARM</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>14</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>0</debug>\r
+ <option>\r
+ <name>CCDefines</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCPreprocFile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPreprocComments</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPreprocLine</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCListCFile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCListCMnemonics</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCListCMessages</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCListAssFile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCListAssSource</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCEnableRemarks</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCDiagSuppress</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCDiagRemark</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCDiagWarning</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCDiagError</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCObjPrefix</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCOptSizeSpeed</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCOptimization</name>\r
+ <version>0</version>\r
+ <state>3</state>\r
+ </option>\r
+ <option>\r
+ <name>CCAllowList</name>\r
+ <version>1</version>\r
+ <state>1111111</state>\r
+ </option>\r
+ <option>\r
+ <name>CCObjUseModuleName</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCObjModuleName</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCDebugInfo</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IProcessorMode</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IEndianMode</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IProcessor</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IStackAlign</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IInterwork</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IExtraOptionsCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IExtraOptions</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCLangConformance</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSignedPlainChar</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRequirePrototypes</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCMultibyteSupport</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCDiagWarnAreErr</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCompilerRuntimeInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IFpuProcessor</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OutputFile</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCLangSelect</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCLibConfigHeader</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCOptSizeSpeedSlave</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCOptimizationSlave</name>\r
+ <version>0</version>\r
+ <state>3</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCodeFunctions</name>\r
+ <state>CODE</state>\r
+ </option>\r
+ <option>\r
+ <name>CCData</name>\r
+ <state>DATA</state>\r
+ </option>\r
+ <option>\r
+ <name>PreInclude</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CompilerMisraRules</name>\r
+ <version>0</version>\r
+ <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>\r
+ </option>\r
+ <option>\r
+ <name>CompilerMisraOverride</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCModuleTypeOverride</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCModuleType</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCModuleTypeCmdlineProducer</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCIncludePath2</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCStdIncCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCStdIncludePath</name>\r
+ <state>###Uninitialized###</state>\r
+ </option>\r
+ <option>\r
+ <name>CCInlineThreshold</name>\r
+ <version>0</version>\r
+ <state>1</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>AARM</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>7</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>0</debug>\r
+ <option>\r
+ <name>AObjPrefix</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>AEndian</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>ACaseSensitivity</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>MacroChars</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AWarnEnable</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AWarnWhat</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AWarnOne</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>AWarnRange1</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>AWarnRange2</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>ADebug</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AltRegisterNames</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>ADefines</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>AList</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AListHeader</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>AListing</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>Includes</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>MacDefs</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>MacExps</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>MacExec</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OnlyAssed</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>MultiLine</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>PageLengthCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>PageLength</name>\r
+ <state>80</state>\r
+ </option>\r
+ <option>\r
+ <name>TabSpacing</name>\r
+ <state>8</state>\r
+ </option>\r
+ <option>\r
+ <name>AXRef</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AXRefDefines</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AXRefInternal</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AXRefDual</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AProcessor</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>AFpuProcessor</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>AOutputFile</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>AMultibyteSupport</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>ALimitErrorsCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>ALimitErrorsEdit</name>\r
+ <state>100</state>\r
+ </option>\r
+ <option>\r
+ <name>AIgnoreStdInclude</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AStdIncludes</name>\r
+ <state>$TOOLKIT_DIR$\INC\</state>\r
+ </option>\r
+ <option>\r
+ <name>AUserIncludes</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>AExtraOptionsCheckV2</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AExtraOptionsV2</name>\r
+ <state></state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>CUSTOM</name>\r
+ <archiveVersion>3</archiveVersion>\r
+ <data>\r
+ <extensions></extensions>\r
+ <cmdline></cmdline>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>BICOMP</name>\r
+ <archiveVersion>0</archiveVersion>\r
+ <data/>\r
+ </settings>\r
+ <settings>\r
+ <name>BUILDACTION</name>\r
+ <archiveVersion>1</archiveVersion>\r
+ <data>\r
+ <prebuild></prebuild>\r
+ <postbuild></postbuild>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>XLINK</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>18</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>0</debug>\r
+ <option>\r
+ <name>XOutOverride</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OutputFile</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OutputFormat</name>\r
+ <version>11</version>\r
+ <state>16</state>\r
+ </option>\r
+ <option>\r
+ <name>FormatVariant</name>\r
+ <version>7</version>\r
+ <state>16</state>\r
+ </option>\r
+ <option>\r
+ <name>SecondaryOutputFile</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>XDefines</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>AlwaysOutput</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OverlapWarnings</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>NoGlobalCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>XList</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>SegmentMap</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>ListSymbols</name>\r
+ <state>2</state>\r
+ </option>\r
+ <option>\r
+ <name>PageLengthCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>PageLength</name>\r
+ <state>80</state>\r
+ </option>\r
+ <option>\r
+ <name>XIncludes</name>\r
+ <state>###Uninitialized###</state>\r
+ </option>\r
+ <option>\r
+ <name>ModuleStatus</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>XclOverride</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>XclFile</name>\r
+ <state>lnk0t.xcl</state>\r
+ </option>\r
+ <option>\r
+ <name>XclFileSlave</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>DoFill</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>FillerByte</name>\r
+ <state>0xFF</state>\r
+ </option>\r
+ <option>\r
+ <name>DoCrc</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CrcSize</name>\r
+ <version>0</version>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CrcAlgo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CrcPoly</name>\r
+ <state>0x11021</state>\r
+ </option>\r
+ <option>\r
+ <name>CrcCompl</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>RangeCheckAlternatives</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>SuppressAllWarn</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>SuppressDiags</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>TreatAsWarn</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>TreatAsErr</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>ModuleLocalSym</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CrcBitOrder</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>XExtraOptionsCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>XExtraOptions</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>IncludeSuppressed</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OXLibIOConfig</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>ModuleSummary</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>xcProgramEntryLabel</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>DebugInformation</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>RuntimeControl</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IoEmulation</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>XcRTLibraryFile</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>AllowExtraOutput</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>GenerateExtraOutput</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>XExtraOutOverride</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>ExtraOutputFile</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>ExtraOutputFormat</name>\r
+ <version>11</version>\r
+ <state>23</state>\r
+ </option>\r
+ <option>\r
+ <name>ExtraFormatVariant</name>\r
+ <version>7</version>\r
+ <state>2</state>\r
+ </option>\r
+ <option>\r
+ <name>xcOverrideProgramEntryLabel</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>xcProgramEntryLabelSelect</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>ListOutputFormat</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>BufferedTermOutput</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OverlaySystemMap</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>RawBinaryFile</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>RawBinarySymbol</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>RawBinarySegment</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>RawBinaryAlign</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>XLinkMisraHandler</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CrcAlign</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CrcInitialValue</name>\r
+ <state>0x0</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>XAR</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>0</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>0</debug>\r
+ <option>\r
+ <name>XARInputs</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>XAROverride</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>XAROutput</name>\r
+ <state>###Unitialized###</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>BILINK</name>\r
+ <archiveVersion>0</archiveVersion>\r
+ <data/>\r
+ </settings>\r
+ </configuration>\r
+ <group>\r
+ <name>Demo files</name>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\Common\Minimal\BlockQ.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\Common\Minimal\blocktim.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\Common\Minimal\death.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\Common\Minimal\flash.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\Common\Minimal\integer.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\main.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\ParTest\ParTest.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\Common\Minimal\PollQ.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\Common\Minimal\semtest.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\timertest.c</name>\r
+ </file>\r
+ </group>\r
+ <group>\r
+ <name>Library files</name>\r
+ <file>\r
+ <name>$PROJ_DIR$\LuminaryDrivers\driverlib.r79</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\LuminaryDrivers\osram128x64x4.c</name>\r
+ </file>\r
+ </group>\r
+ <group>\r
+ <name>Scheduler files</name>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Source\portable\MemMang\heap_2.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Source\list.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Source\portable\IAR\ARM_CM3\port.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Source\portable\IAR\ARM_CM3\portasm.s</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Source\queue.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Source\tasks.c</name>\r
+ </file>\r
+ </group>\r
+ <group>\r
+ <name>System files</name>\r
+ <file>\r
+ <name>$PROJ_DIR$\startup_ewarm.c</name>\r
+ </file>\r
+ </group>\r
+ <group>\r
+ <name>uIP files</name>\r
+ <file>\r
+ <name>$PROJ_DIR$\webserver\emac.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\webserver\http-strings.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\webserver\httpd-cgi.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\webserver\httpd-fs.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\webserver\httpd.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\Common\ethernet\uIP\uip-1.0\uip\psock.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\Common\ethernet\uIP\uip-1.0\uip\timer.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\Common\ethernet\uIP\uip-1.0\uip\uip.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\Common\ethernet\uIP\uip-1.0\uip\uip_arp.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\webserver\uIP_Task.c</name>\r
+ </file>\r
+ </group>\r
+</project>\r
+\r
+\r
--- /dev/null
+<?xml version="1.0" encoding="iso-8859-1"?>\r
+\r
+<workspace>\r
+ <project>\r
+ <path>$WS_DIR$\RTOSDemo.ewp</path>\r
+ </project>\r
+ <batchBuild/>\r
+</workspace>\r
+\r
+\r
--- /dev/null
+//*****************************************************************************
+//
+// webserver-lwip.xcl - Linker script for EW-ARM.
+//
+// Copyright (c) 2006-2007 Luminary Micro, Inc. All rights reserved.
+//
+// Software License Agreement
+//
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
+// exclusively on LMI's microcontroller products.
+//
+// The software is owned by LMI and/or its suppliers, and is protected under
+// applicable copyright laws. All rights are reserved. Any use in violation
+// of the foregoing restrictions may subject the user to criminal sanctions
+// under applicable laws, as well as to civil liability for the breach of the
+// terms and conditions of this license.
+//
+// THIS SOFTWARE IS PROVIDED AS IS. NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+//*****************************************************************************
+
+//
+// Set the CPU type to ARM.
+//
+-carm
+
+//
+// Define the size of flash and SRAM.
+//
+-DROMSTART=00000000
+-DROMEND=00040000
+-DRAMSTART=20000000
+-DRAMEND=20010000\r
+\r
+
+
+//
+// Define the sections to place into flash, and the order to place them.
+//
+-Z(CODE)INTVEC=ROMSTART-ROMEND
+-Z(CODE)ICODE,DIFUNCT=ROMSTART-ROMEND
+-Z(CODE)CODE=ROMSTART-ROMEND
+-Z(CONST)CODE_ID=ROMSTART-ROMEND
+-Z(CONST)INITTAB,DATA_ID,DATA_C=ROMSTART-ROMEND
+-Z(CONST)CHECKSUM=ROMSTART-ROMEND
+
+//
+// Define the sections to place into SRAM, and the order to place them.
+//
+-Z(DATA)VTABLE=RAMSTART-RAMEND
+-Z(DATA)DATA_I,DATA_Z,DATA_N=RAMSTART-RAMEND
+-Z(DATA)CODE_I=RAMSTART-RAMEND
--- /dev/null
+#ifndef BITMAP_H\r
+#define BITMAP_H\r
+\r
+const unsigned char pucImage[] =\r
+{\r
+0x00, 0x0a, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,\r
+0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,\r
+0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,\r
+0xaa, 0xaa, 0xaa, 0x00, 0x0a, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,\r
+0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,\r
+0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,\r
+0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xa0, 0x0a, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,\r
+0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,\r
+0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,\r
+0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xaa, 0xaa, 0xaa, 0xaf, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfa, 0xaa,\r
+0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf7,\r
+0x00, 0x8f, 0xff, 0xff, 0xf8, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0xff, 0xff, 0xff, 0xff, 0xf8, 0x88, 0x88, 0x88,\r
+0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x8f, 0xff, 0xff, 0xff, 0xff, 0xff, 0x88, 0x77, 0x77, 0x78, 0x8f, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xf8, 0x88, 0x77, 0x77, 0x88, 0x8f, 0xff, 0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff,\r
+0xff, 0xff, 0xf0, 0x00, 0x00, 0x8f, 0x00, 0xff, 0x87, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x78, 0xff, 0xff,\r
+0xf7, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x78, 0xff, 0xff, 0xff, 0x87, 0x77, 0x77, 0x77, 0x77, 0x77,\r
+0x77, 0x77, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x7f, 0xff, 0xff, 0xfa, 0xaa,\r
+0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0x70, 0x00, 0x00, 0x8f, 0x00, 0xff, 0x87, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77,\r
+0x77, 0x77, 0xff, 0xff, 0xf7, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x78, 0xff, 0xff, 0xf8, 0x77, 0x77,\r
+0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x78, 0xff, 0xff, 0xff, 0xff, 0x87, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x8f,\r
+0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0x70, 0x08, 0x00, 0x8f, 0x00, 0xff, 0x87, 0x77, 0x77, 0x77,\r
+0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x8f, 0xff, 0xf7, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x78, 0xff,\r
+0xff, 0x87, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x8f, 0xff, 0xff, 0xf8, 0x77, 0x77, 0x77, 0x77, 0x77,\r
+0x77, 0x77, 0x77, 0x8f, 0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0x00, 0x0f, 0x00, 0x8f, 0x00, 0xff,\r
+0x87, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x78, 0xff, 0xf7, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77,\r
+0x77, 0x77, 0x78, 0xff, 0xf8, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x78, 0xff, 0xff, 0xf8, 0x77,\r
+0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x8f, 0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0x70, 0x07,\r
+0x00, 0x70, 0x00, 0xff, 0x87, 0x77, 0x77, 0x77, 0xff, 0xff, 0xf8, 0x77, 0x77, 0x77, 0x77, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0x77, 0x77, 0x77, 0x7f, 0xff, 0xff, 0xff, 0xff, 0x87, 0x77, 0x77, 0x77, 0x78, 0xff, 0xff, 0xf8, 0x77, 0x77, 0x77, 0x77,\r
+0xff, 0xff, 0x87, 0x77, 0x77, 0x77, 0x8f, 0xff, 0xff, 0xff, 0x88, 0x8f, 0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff,\r
+0xff, 0xff, 0x80, 0x00, 0x00, 0x00, 0x07, 0xff, 0x87, 0x77, 0x77, 0x77, 0xff, 0xff, 0xff, 0x87, 0x77, 0x77, 0x77, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0x77, 0x77, 0x77, 0x7f, 0xff, 0xff, 0xff, 0xff, 0x77, 0x77, 0x77, 0x77, 0xff, 0xff, 0xff, 0xff,\r
+0x87, 0x77, 0x77, 0x77, 0xff, 0xff, 0x77, 0x77, 0x77, 0x77, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfa, 0xaa,\r
+0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0xf7, 0x00, 0x00, 0x00, 0x0f, 0xff, 0x87, 0x77, 0x77, 0x77, 0xff, 0xff, 0xff, 0xf8,\r
+0x77, 0x77, 0x77, 0xff, 0xff, 0xff, 0xff, 0xff, 0x77, 0x77, 0x77, 0x7f, 0xff, 0xff, 0xff, 0xff, 0x77, 0x77, 0x77, 0x77,\r
+0xff, 0xff, 0xff, 0xff, 0xf7, 0x77, 0x77, 0x77, 0x8f, 0xff, 0x77, 0x77, 0x77, 0x77, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0xff, 0x70, 0x00, 0x00, 0xff, 0xff, 0x87, 0x77, 0x77, 0x77,\r
+0xff, 0xff, 0xff, 0xf8, 0x77, 0x77, 0x77, 0xff, 0xff, 0xff, 0xff, 0xff, 0x77, 0x77, 0x77, 0x7f, 0xff, 0xff, 0xff, 0xff,\r
+0x77, 0x77, 0x77, 0x78, 0xff, 0xff, 0xff, 0xff, 0xf8, 0x77, 0x77, 0x77, 0x8f, 0xff, 0x77, 0x77, 0x77, 0x77, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0x87, 0x77, 0x77, 0x77, 0xff, 0xff, 0xff, 0xf7, 0x77, 0x77, 0x78, 0xff, 0xff, 0xff, 0xff, 0xff, 0x77, 0x77, 0x77, 0x7f,\r
+0xff, 0xff, 0xff, 0xf8, 0x77, 0x77, 0x77, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xff, 0x87, 0x77, 0x77, 0x78, 0xff, 0x87, 0x77,\r
+0x77, 0x77, 0x78, 0x8f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0x88, 0xff, 0xff, 0xff, 0x87, 0x77, 0x77, 0x77, 0xff, 0xff, 0xf8, 0x87, 0x77, 0x77, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0x77, 0x77, 0x77, 0x7f, 0xff, 0xff, 0xff, 0xf8, 0x77, 0x77, 0x77, 0x8f, 0xff, 0xff, 0xff, 0xff, 0xff, 0x87, 0x77, 0x77,\r
+0x78, 0xff, 0x87, 0x77, 0x77, 0x77, 0x77, 0x77, 0x8f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0x80, 0x00, 0x8f, 0x8f, 0xff, 0x87, 0x77, 0x77, 0x77, 0x88, 0x88, 0x77, 0x77, 0x77, 0x77, 0x8f, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0x77, 0x77, 0x77, 0x7f, 0xff, 0xff, 0xff, 0xf8, 0x77, 0x77, 0x77, 0x8f, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0x87, 0x77, 0x77, 0x78, 0xff, 0xf7, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x88, 0xff, 0xff, 0xff, 0xff, 0xfa, 0xaa,\r
+0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0xf7, 0x00, 0x00, 0x8f, 0x07, 0xff, 0x87, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77,\r
+0x77, 0x77, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x77, 0x77, 0x77, 0x7f, 0xff, 0xff, 0xff, 0xf8, 0x77, 0x77, 0x77, 0x8f,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0x87, 0x77, 0x77, 0x78, 0xff, 0xf8, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x8f, 0xff,\r
+0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0x70, 0x07, 0x00, 0x8f, 0x00, 0xff, 0x87, 0x77, 0x77, 0x77,\r
+0x77, 0x77, 0x77, 0x77, 0x88, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x77, 0x77, 0x77, 0x7f, 0xff, 0xff, 0xff, 0xf8,\r
+0x77, 0x77, 0x77, 0x8f, 0xff, 0xff, 0xff, 0xff, 0xff, 0x87, 0x77, 0x77, 0x78, 0xff, 0xff, 0xf8, 0x77, 0x77, 0x77, 0x77,\r
+0x77, 0x77, 0x77, 0x8f, 0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0x70, 0x0f, 0x00, 0x8f, 0x00, 0xff,\r
+0x87, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x8f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x77, 0x77, 0x77, 0x7f,\r
+0xff, 0xff, 0xff, 0xf8, 0x77, 0x77, 0x77, 0x8f, 0xff, 0xff, 0xff, 0xff, 0xff, 0x87, 0x77, 0x77, 0x78, 0xff, 0xff, 0xff,\r
+0x87, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x78, 0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0x00, 0x0f,\r
+0x00, 0x8f, 0x00, 0xff, 0x87, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x78, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0x77, 0x77, 0x77, 0x7f, 0xff, 0xff, 0xff, 0xf8, 0x77, 0x77, 0x77, 0x8f, 0xff, 0xff, 0xff, 0xff, 0xff, 0x87, 0x77, 0x77,\r
+0x78, 0xff, 0xff, 0xff, 0xff, 0x88, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff,\r
+0xff, 0xff, 0x70, 0x08, 0x00, 0x88, 0x00, 0xff, 0x87, 0x77, 0x77, 0x77, 0x88, 0x88, 0x77, 0x77, 0x77, 0x78, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0x77, 0x77, 0x77, 0x7f, 0xff, 0xff, 0xff, 0xf8, 0x77, 0x77, 0x77, 0x8f, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0x87, 0x77, 0x77, 0x78, 0xff, 0xff, 0xff, 0xff, 0xff, 0x88, 0x77, 0x77, 0x77, 0x77, 0x77, 0xff, 0xff, 0xfa, 0xaa,\r
+0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0x70, 0x00, 0x00, 0x70, 0x07, 0xff, 0x87, 0x77, 0x77, 0x77, 0xff, 0xff, 0x77, 0x77,\r
+0x77, 0x77, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x77, 0x77, 0x77, 0x7f, 0xff, 0xff, 0xff, 0xf8, 0x77, 0x77, 0x77, 0x7f,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0x87, 0x77, 0x77, 0x78, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf8, 0x77, 0x77, 0x77, 0x77,\r
+0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0xf8, 0x00, 0x00, 0x00, 0x7f, 0xff, 0x87, 0x77, 0x77, 0x77,\r
+0xff, 0xff, 0xf7, 0x77, 0x77, 0x77, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x77, 0x77, 0x77, 0x7f, 0xff, 0xff, 0xff, 0xff,\r
+0x77, 0x77, 0x77, 0x78, 0xff, 0xff, 0xff, 0xff, 0xf8, 0x77, 0x77, 0x77, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0x87, 0x77, 0x77, 0x77, 0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0xff, 0x80, 0x00, 0x00, 0xff, 0xff,\r
+0x87, 0x77, 0x77, 0x77, 0xff, 0xff, 0xf8, 0x77, 0x77, 0x77, 0x8f, 0xff, 0xff, 0xff, 0xff, 0xff, 0x77, 0x77, 0x77, 0x7f,\r
+0xff, 0xff, 0xff, 0xff, 0x77, 0x77, 0x77, 0x77, 0xff, 0xff, 0xff, 0xff, 0xf7, 0x77, 0x77, 0x77, 0x8f, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0x87, 0x77, 0x77, 0x77, 0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0x87, 0x88,\r
+0x88, 0x8f, 0xff, 0xff, 0x87, 0x77, 0x77, 0x77, 0xff, 0xff, 0xff, 0x77, 0x77, 0x77, 0x8f, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0x77, 0x77, 0x77, 0x7f, 0xff, 0xff, 0xff, 0xff, 0x77, 0x77, 0x77, 0x77, 0xff, 0xff, 0xff, 0xff, 0x87, 0x77, 0x77, 0x77,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x87, 0x77, 0x77, 0x77, 0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff,\r
+0xff, 0xff, 0x00, 0x07, 0xff, 0xff, 0xff, 0xff, 0x87, 0x77, 0x77, 0x77, 0xff, 0xff, 0xff, 0x87, 0x77, 0x77, 0x7f, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0x77, 0x77, 0x77, 0x7f, 0xff, 0xff, 0xff, 0xff, 0x87, 0x77, 0x77, 0x77, 0x8f, 0xff, 0xff, 0xff,\r
+0x77, 0x77, 0x77, 0x77, 0xff, 0xff, 0xf7, 0x88, 0xff, 0xff, 0xff, 0xff, 0x87, 0x77, 0x77, 0x77, 0xff, 0xff, 0xfa, 0xaa,\r
+0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0x80, 0x00, 0xff, 0xff, 0xff, 0xff, 0x87, 0x77, 0x77, 0x77, 0xff, 0xff, 0xff, 0xf7,\r
+0x77, 0x77, 0x78, 0xff, 0xff, 0xff, 0xff, 0xff, 0x77, 0x77, 0x77, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xf8, 0x77, 0x77, 0x77,\r
+0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x78, 0xff, 0xff, 0x87, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x78,\r
+0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0xf7, 0x00, 0x88, 0x88, 0x88, 0xff, 0x87, 0x77, 0x77, 0x77,\r
+0xff, 0xff, 0xff, 0xf8, 0x77, 0x77, 0x77, 0xff, 0xff, 0xff, 0xff, 0xff, 0x77, 0x77, 0x77, 0x7f, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0x87, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x8f, 0xff, 0xff, 0x87, 0x77, 0x77, 0x77, 0x77, 0x77,\r
+0x77, 0x77, 0x77, 0x7f, 0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0x70, 0x00, 0x00, 0x00, 0x00, 0xff,\r
+0x87, 0x77, 0x77, 0x77, 0xff, 0xff, 0xff, 0xf8, 0x77, 0x77, 0x77, 0x8f, 0xff, 0xff, 0xff, 0xff, 0x77, 0x77, 0x77, 0x7f,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xf8, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x78, 0xff, 0xff, 0xff, 0x87, 0x77,\r
+0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0xff, 0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0x70, 0x00,\r
+0x00, 0x00, 0x00, 0xff, 0x87, 0x77, 0x77, 0x77, 0xff, 0xff, 0xff, 0xff, 0x77, 0x77, 0x77, 0x7f, 0xff, 0xff, 0xff, 0xff,\r
+0x77, 0x77, 0x77, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x87, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x8f, 0xff,\r
+0xff, 0xff, 0x87, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x8f, 0xff, 0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff,\r
+0xff, 0xff, 0x70, 0x00, 0x00, 0x00, 0x07, 0xff, 0x88, 0x88, 0x88, 0x88, 0xff, 0xff, 0xff, 0xff, 0x88, 0x88, 0x88, 0x88,\r
+0xff, 0xff, 0xff, 0xff, 0x88, 0x88, 0x88, 0x8f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf8, 0x87, 0x77, 0x77, 0x77,\r
+0x88, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x88, 0x77, 0x77, 0x77, 0x77, 0x88, 0x8f, 0xff, 0xff, 0xff, 0xff, 0xfa, 0xaa,\r
+0xaa, 0xaf, 0xff, 0xff, 0x00, 0x0f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff, 0x00, 0x0f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff, 0x00, 0x0f, 0x70, 0x08, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff, 0x00, 0x07, 0x70, 0x07,\r
+0x88, 0x88, 0x88, 0xff, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88,\r
+0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88,\r
+0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff,\r
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xfa, 0xaa,\r
+0xaa, 0xaf, 0xff, 0xff, 0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r
+0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff, 0xf7, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x70, 0x00, 0x00, 0x00,\r
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r
+0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0x70, 0x08, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0x70, 0x08,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfa, 0xaa,\r
+0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaa, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,\r
+0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,\r
+0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,\r
+0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x0a, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,\r
+0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,\r
+0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,\r
+0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xa0, 0x00, 0xaa, 0xaa, 0xaa,\r
+0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,\r
+0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,\r
+0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x00,\r
+0x00 };\r
+\r
+#define bmpBITMAP_HEIGHT 50\r
+#define bmpBITMAP_WIDTH 128\r
+\r
+#endif\r
--- /dev/null
+#ifndef LCD_MESSAGE_H\r
+#define LCD_MESSAGE_H\r
+\r
+typedef struct\r
+{\r
+ signed char *pcMessage;\r
+} xOLEDMessage;\r
+\r
+#endif /* LCD_MESSAGE_H */\r
--- /dev/null
+/*\r
+ FreeRTOS.org V4.3.0 - Copyright (C) 2003-2007 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS.org distribution.\r
+\r
+ FreeRTOS.org is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS.org is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS.org; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS.org, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section\r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license\r
+ and contact details. Please ensure to read the configuration and relevant\r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+\r
+/*\r
+ * Creates all the demo application tasks, then starts the scheduler. The WEB\r
+ * documentation provides more details of the standard demo application tasks.\r
+ * In addition to the standard demo tasks, the following tasks and tests are\r
+ * defined and/or created within this file:\r
+ *\r
+ * "Fast Interrupt Test" - A high frequency periodic interrupt is generated\r
+ * using a free running timer to demonstrate the use of the\r
+ * configKERNEL_INTERRUPT_PRIORITY configuration constant. The interrupt\r
+ * service routine measures the number of processor clocks that occur between\r
+ * each interrupt - and in so doing measures the jitter in the interrupt timing.\r
+ * The maximum measured jitter time is latched in the ulMaxJitter variable, and\r
+ * displayed on the OLED display by the 'Check' task as described below. The\r
+ * fast interrupt is configured and handled in the timertest.c source file.\r
+ *\r
+ * "OLED" task - the OLED task is a 'gatekeeper' task. It is the only task that\r
+ * is permitted to access the display directly. Other tasks wishing to write a\r
+ * message to the OLED send the message on a queue to the OLED task instead of\r
+ * accessing the OLED themselves. The OLED task just blocks on the queue waiting\r
+ * for messages - waking and displaying the messages as they arrive.\r
+ *\r
+ * "Check" task - This only executes every five seconds but has the highest\r
+ * priority so is guaranteed to get processor time. Its main function is to\r
+ * check that all the standard demo tasks are still operational. Should any\r
+ * unexpected behaviour within a demo task be discovered the 'check' task will\r
+ * write an error to the OLED (via the OLED task). If all the demo tasks are\r
+ * executing with their expected behaviour then the check task writes PASS\r
+ * along with the max jitter time to the OLED (again via the OLED task), as\r
+ * described above.\r
+ *\r
+ * "uIP" task - This is the task that handles the uIP stack. All TCP/IP\r
+ * processing is performed in this task.\r
+ */\r
+\r
+\r
+\r
+/* Standard includes. */\r
+#include <stdio.h>\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "Task.h"\r
+#include "queue.h"\r
+#include "semphr.h"\r
+\r
+/* Demo app includes. */\r
+#include "BlockQ.h"\r
+#include "death.h"\r
+#include "integer.h"\r
+#include "blocktim.h"\r
+#include "flash.h"\r
+#include "partest.h"\r
+#include "semtest.h"\r
+#include "pollq.h"\r
+#include "lcd_message.h"\r
+#include "bitmap.h"\r
+\r
+/* Hardware library includes. */\r
+#include "hw_memmap.h"\r
+#include "hw_types.h"\r
+#include "sysctl.h"\r
+#include "gpio.h"\r
+#include "osram128x64x4.h"\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* The time between cycles of the 'check' task. */\r
+#define mainCHECK_DELAY ( ( portTickType ) 5000 / portTICK_RATE_MS )\r
+\r
+/* Size of the stack allocated to the uIP task. */\r
+#define mainBASIC_WEB_STACK_SIZE ( configMINIMAL_STACK_SIZE * 2 )\r
+\r
+/* The check task uses the sprintf function so requires a little more stack too. */\r
+#define mainCHECK_TASK_STACK_SIZE ( configMINIMAL_STACK_SIZE + 50 )\r
+\r
+/* Task priorities. */\r
+#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
+#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 )\r
+#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 )\r
+#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
+#define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 )\r
+#define mainINTEGER_TASK_PRIORITY ( tskIDLE_PRIORITY )\r
+\r
+/* The maximum number of message that can be waiting for display at any one\r
+time. */\r
+#define mainOLED_QUEUE_SIZE ( 3 )\r
+\r
+/* Dimensions the buffer into which the jitter time is written. */\r
+#define mainMAX_MSG_LEN 25\r
+\r
+/* The period of the system clock in nano seconds. This is used to calculate\r
+the jitter time in nano seconds. */\r
+#define mainNS_PER_CLOCK ( ( unsigned portLONG ) ( ( 1.0 / ( double ) configCPU_CLOCK_HZ ) * 1000000000.0 ) )\r
+\r
+/* Constants used when writing strings to the display. */\r
+#define mainCHARACTER_HEIGHT ( 9 )\r
+#define mainMAX_ROWS ( mainCHARACTER_HEIGHT * 7 )\r
+#define mainFULL_SCALE ( 15 )\r
+#define ulSSI_FREQUENCY 1000000\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Checks the status of all the demo tasks then prints a message to the\r
+ * display. The message will be either PASS - an include in brackets the\r
+ * maximum measured jitter time (as described at the to of the file), or a\r
+ * message that describes which of the standard demo tasks an error has been\r
+ * discovered in.\r
+ *\r
+ * Messages are not written directly to the terminal, but passed to vOLEDTask\r
+ * via a queue.\r
+ */\r
+static void vCheckTask( void *pvParameters );\r
+\r
+/*\r
+ * The task that handles the uIP stack. All TCP/IP processing is performed in\r
+ * this task.\r
+ */\r
+extern void vuIP_Task( void *pvParameters );\r
+\r
+/*\r
+ * The display is written two by more than one task so is controlled by a\r
+ * 'gatekeeper' task. This is the only task that is actually permitted to\r
+ * access the display directly. Other tasks wanting to display a message send\r
+ * the message to the gatekeeper.\r
+ */\r
+static void vOLEDTask( void *pvParameters );\r
+\r
+/*\r
+ * Configure the hardware for the demo.\r
+ */\r
+static void prvSetupHardware( void );\r
+\r
+/*\r
+ * Configures the high frequency timers - those used to measure the timing\r
+ * jitter while the real time kernel is executing.\r
+ */\r
+extern void vSetupTimer( void );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* The queue used to send messages to the OLED task. */\r
+xQueueHandle xOLEDQueue;\r
+\r
+/* The welcome text. */\r
+const portCHAR * const pcWelcomeMessage = " www.FreeRTOS.org";\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+int main( void )\r
+{\r
+ prvSetupHardware();\r
+\r
+ /* Create the queue used by the OLED task. Messages for display on the OLED\r
+ are received via this queue. */\r
+ xOLEDQueue = xQueueCreate( mainOLED_QUEUE_SIZE, sizeof( xOLEDMessage ) );\r
+\r
+ /* Create the uIP task. */\r
+ xTaskCreate( vuIP_Task, ( signed portCHAR * ) "uIP", mainBASIC_WEB_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY - 1, NULL );\r
+\r
+ /* Start the standard demo tasks. */\r
+ vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY );\r
+ vCreateBlockTimeTasks();\r
+ vStartSemaphoreTasks( mainSEM_TEST_PRIORITY );\r
+ vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY );\r
+ vStartIntegerMathTasks( mainINTEGER_TASK_PRIORITY );\r
+\r
+ /* Start the tasks defined within this file/specific to this demo. */\r
+ xTaskCreate( vCheckTask, ( signed portCHAR * ) "Check", mainCHECK_TASK_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL );\r
+ xTaskCreate( vOLEDTask, ( signed portCHAR * ) "OLED", configMINIMAL_STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );\r
+\r
+ /* The suicide tasks must be created last as they need to know how many\r
+ tasks were running prior to their creation in order to ascertain whether\r
+ or not the correct/expected number of tasks are running at any given time. */\r
+ vCreateSuicidalTasks( mainCREATOR_TASK_PRIORITY );\r
+\r
+ /* Configure the high frequency interrupt used to measure the interrupt\r
+ jitter time. */\r
+ vSetupTimer();\r
+ \r
+ /* Start the scheduler. */\r
+ vTaskStartScheduler();\r
+\r
+ /* Will only get here if there was insufficient memory to create the idle\r
+ task. */\r
+ return 0;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void prvSetupHardware( void )\r
+{\r
+ /* Set the clocking to run from the PLL at 50 MHz */\r
+ SysCtlClockSet( SYSCTL_SYSDIV_4 | SYSCTL_USE_PLL | SYSCTL_OSC_MAIN | SYSCTL_XTAL_8MHZ );\r
+ \r
+ /* Enable/Reset the Ethernet Controller */\r
+ SysCtlPeripheralEnable( SYSCTL_PERIPH_ETH );\r
+ SysCtlPeripheralReset( SYSCTL_PERIPH_ETH );\r
+ \r
+ /* Enable Port F for Ethernet LEDs\r
+ LED0 Bit 3 Output\r
+ LED1 Bit 2 Output */\r
+ SysCtlPeripheralEnable( SYSCTL_PERIPH_GPIOF );\r
+ GPIODirModeSet( GPIO_PORTF_BASE, (GPIO_PIN_2 | GPIO_PIN_3), GPIO_DIR_MODE_HW );\r
+ GPIOPadConfigSet( GPIO_PORTF_BASE, (GPIO_PIN_2 | GPIO_PIN_3 ), GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD ); \r
+ \r
+ vParTestInitialise();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void vCheckTask( void *pvParameters )\r
+{\r
+portTickType xLastExecutionTime;\r
+xOLEDMessage xMessage;\r
+static portCHAR cPassMessage[ mainMAX_MSG_LEN ];\r
+extern unsigned portLONG ulMaxJitter;\r
+\r
+ xLastExecutionTime = xTaskGetTickCount();\r
+ xMessage.pcMessage = cPassMessage;\r
+ \r
+ for( ;; )\r
+ {\r
+ /* Perform this check every mainCHECK_DELAY milliseconds. */\r
+ vTaskDelayUntil( &xLastExecutionTime, mainCHECK_DELAY );\r
+\r
+ /* Has an error been found in any task? */\r
+\r
+ if( xAreBlockingQueuesStillRunning() != pdTRUE )\r
+ {\r
+ xMessage.pcMessage = "ERROR IN BLOCK Q";\r
+ }\r
+ else if( xAreBlockTimeTestTasksStillRunning() != pdTRUE )\r
+ {\r
+ xMessage.pcMessage = "ERROR IN BLOCK TIME";\r
+ }\r
+ else if( xAreSemaphoreTasksStillRunning() != pdTRUE )\r
+ {\r
+ xMessage.pcMessage = "ERROR IN SEMAPHORE";\r
+ }\r
+ else if( xArePollingQueuesStillRunning() != pdTRUE )\r
+ {\r
+ xMessage.pcMessage = "ERROR IN POLL Q";\r
+ }\r
+ else if( xIsCreateTaskStillRunning() != pdTRUE )\r
+ {\r
+ xMessage.pcMessage = "ERROR IN CREATE";\r
+ }\r
+ else if( xAreIntegerMathsTaskStillRunning() != pdTRUE )\r
+ {\r
+ xMessage.pcMessage = "ERROR IN MATH";\r
+ }\r
+ else\r
+ {\r
+ sprintf( cPassMessage, "PASS [%uns]", ulMaxJitter * mainNS_PER_CLOCK );\r
+ }\r
+\r
+ /* Send the message to the OLED gatekeeper for display. */\r
+ xQueueSend( xOLEDQueue, &xMessage, portMAX_DELAY );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+\r
+\r
+void vOLEDTask( void *pvParameters )\r
+{\r
+xOLEDMessage xMessage;\r
+unsigned portLONG ulY = mainMAX_ROWS;\r
+\r
+ /* Initialise the OLED and display a startup message. */\r
+ OSRAM128x64x4Init( ulSSI_FREQUENCY ); \r
+ \r
+ OSRAM128x64x4StringDraw( " POWERED BY FreeRTOS", 0, 0, mainFULL_SCALE );\r
+ OSRAM128x64x4ImageDraw( pucImage, 0, mainCHARACTER_HEIGHT + 1, bmpBITMAP_WIDTH, bmpBITMAP_HEIGHT );\r
+ \r
+ for( ;; )\r
+ {\r
+ /* Wait for a message to arrive that requires displaying. */\r
+ xQueueReceive( xOLEDQueue, &xMessage, portMAX_DELAY );\r
+ \r
+ /* Write the message on the next available row. */\r
+ ulY += mainCHARACTER_HEIGHT;\r
+ if( ulY >= mainMAX_ROWS )\r
+ {\r
+ ulY = mainCHARACTER_HEIGHT;\r
+ OSRAM128x64x4Clear();\r
+ OSRAM128x64x4StringDraw( pcWelcomeMessage, 0, 0, mainFULL_SCALE ); \r
+ }\r
+\r
+ /* Display the message. */\r
+ OSRAM128x64x4StringDraw( xMessage.pcMessage, 0, ulY, mainFULL_SCALE );\r
+ }\r
+}\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// startup_ewarm.c - Boot code for Stellaris.\r
+//\r
+// Copyright (c) 2006-2007 Luminary Micro, Inc. All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 100 of the Stellaris Ethernet\r
+// Applications Library.\r
+//\r
+//*****************************************************************************\r
+\r
+//*****************************************************************************\r
+//\r
+// Enable the IAR extensions for this source file.\r
+//\r
+//*****************************************************************************\r
+#pragma language=extended\r
+\r
+//*****************************************************************************\r
+//\r
+// Forward declaration of the default fault handlers.\r
+//\r
+//*****************************************************************************\r
+void ResetISR(void);\r
+static void NmiSR(void);\r
+static void FaultISR(void);\r
+static void IntDefaultHandler(void);\r
+\r
+//*****************************************************************************\r
+//\r
+// External declaration for the interrupt handler used by the application.\r
+//\r
+//*****************************************************************************\r
+\r
+\r
+//*****************************************************************************\r
+//\r
+// The entry point for the application.\r
+//\r
+//*****************************************************************************\r
+extern int main(void);\r
+extern void xPortPendSVHandler(void);\r
+extern void xPortSysTickHandler(void);\r
+extern void vEMAC_ISR( void );\r
+extern Timer0IntHandler( void );\r
+\r
+//*****************************************************************************\r
+//\r
+// Reserve space for the system stack.\r
+//\r
+//*****************************************************************************\r
+#ifndef STACK_SIZE\r
+#define STACK_SIZE 64\r
+#endif\r
+static unsigned long pulStack[STACK_SIZE];\r
+\r
+//*****************************************************************************\r
+//\r
+// A union that describes the entries of the vector table. The union is needed\r
+// since the first entry is the stack pointer and the remainder are function\r
+// pointers.\r
+//\r
+//*****************************************************************************\r
+typedef union\r
+{\r
+ void (*pfnHandler)(void);\r
+ unsigned long ulPtr;\r
+}\r
+uVectorEntry;\r
+\r
+//*****************************************************************************\r
+//\r
+// The minimal vector table for a Cortex M3. Note that the proper constructs\r
+// must be placed on this to ensure that it ends up at physical address\r
+// 0x0000.0000.\r
+//\r
+//*****************************************************************************\r
+__root const uVectorEntry g_pfnVectors[] @ "INTVEC" =\r
+{\r
+ { .ulPtr = (unsigned long)pulStack + sizeof(pulStack) },\r
+ // The initial stack pointer\r
+ ResetISR, // The reset handler\r
+ NmiSR, // The NMI handler\r
+ FaultISR, // The hard fault handler\r
+ IntDefaultHandler, // The MPU fault handler\r
+ IntDefaultHandler, // The bus fault handler\r
+ IntDefaultHandler, // The usage fault handler\r
+ 0, // Reserved\r
+ 0, // Reserved\r
+ 0, // Reserved\r
+ 0, // Reserved\r
+ IntDefaultHandler, // SVCall handler\r
+ IntDefaultHandler, // Debug monitor handler\r
+ 0, // Reserved\r
+ xPortPendSVHandler, // The PendSV handler\r
+ xPortSysTickHandler, // The SysTick handler\r
+ IntDefaultHandler, // GPIO Port A\r
+ IntDefaultHandler, // GPIO Port B\r
+ IntDefaultHandler, // GPIO Port C\r
+ IntDefaultHandler, // GPIO Port D\r
+ IntDefaultHandler, // GPIO Port E\r
+ IntDefaultHandler, // UART0 Rx and Tx\r
+ IntDefaultHandler, // UART1 Rx and Tx\r
+ IntDefaultHandler, // SSI Rx and Tx\r
+ IntDefaultHandler, // I2C Master and Slave\r
+ IntDefaultHandler, // PWM Fault\r
+ IntDefaultHandler, // PWM Generator 0\r
+ IntDefaultHandler, // PWM Generator 1\r
+ IntDefaultHandler, // PWM Generator 2\r
+ IntDefaultHandler, // Quadrature Encoder\r
+ IntDefaultHandler, // ADC Sequence 0\r
+ IntDefaultHandler, // ADC Sequence 1\r
+ IntDefaultHandler, // ADC Sequence 2\r
+ IntDefaultHandler, // ADC Sequence 3\r
+ IntDefaultHandler, // Watchdog timer\r
+ Timer0IntHandler, // Timer 0 subtimer A\r
+ IntDefaultHandler, // Timer 0 subtimer B\r
+ IntDefaultHandler, // Timer 1 subtimer A\r
+ IntDefaultHandler, // Timer 1 subtimer B\r
+ IntDefaultHandler, // Timer 2 subtimer A\r
+ IntDefaultHandler, // Timer 2 subtimer B\r
+ IntDefaultHandler, // Analog Comparator 0\r
+ IntDefaultHandler, // Analog Comparator 1\r
+ IntDefaultHandler, // Analog Comparator 2\r
+ IntDefaultHandler, // System Control (PLL, OSC, BO)\r
+ IntDefaultHandler, // FLASH Control\r
+ IntDefaultHandler, // GPIO Port F\r
+ IntDefaultHandler, // GPIO Port G\r
+ IntDefaultHandler, // GPIO Port H\r
+ IntDefaultHandler, // UART2 Rx and Tx\r
+ IntDefaultHandler, // SSI1 Rx and Tx\r
+ IntDefaultHandler, // Timer 3 subtimer A\r
+ IntDefaultHandler, // Timer 3 subtimer B\r
+ IntDefaultHandler, // I2C1 Master and Slave\r
+ IntDefaultHandler, // Quadrature Encoder 1\r
+ IntDefaultHandler, // CAN0\r
+ IntDefaultHandler, // CAN1\r
+ IntDefaultHandler, // CAN2\r
+ vEMAC_ISR, // Ethernet\r
+ IntDefaultHandler // Power Island\r
+};\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are constructs created by the linker, indicating where the\r
+// the "data" and "bss" segments reside in memory. The initializers for the\r
+// for the "data" segment resides immediately following the "text" segment.\r
+//\r
+//*****************************************************************************\r
+#pragma segment="DATA_ID"\r
+#pragma segment="DATA_I"\r
+#pragma segment="DATA_Z"\r
+\r
+//*****************************************************************************\r
+//\r
+// This is the code that gets called when the processor first starts execution\r
+// following a reset event. Only the absolutely necessary set is performed,\r
+// after which the application supplied entry() routine is called. Any fancy\r
+// actions (such as making decisions based on the reset cause register, and\r
+// resetting the bits in that register) are left solely in the hands of the\r
+// application.\r
+//\r
+//*****************************************************************************\r
+void\r
+ResetISR(void)\r
+{\r
+ unsigned long *pulSrc, *pulDest, *pulEnd;\r
+\r
+ //\r
+ // Copy the data segment initializers from flash to SRAM.\r
+ //\r
+ pulSrc = __segment_begin("DATA_ID");\r
+ pulDest = __segment_begin("DATA_I");\r
+ pulEnd = __segment_end("DATA_I");\r
+ while(pulDest < pulEnd)\r
+ {\r
+ *pulDest++ = *pulSrc++;\r
+ }\r
+\r
+ //\r
+ // Zero fill the bss segment.\r
+ //\r
+ pulDest = __segment_begin("DATA_Z");\r
+ pulEnd = __segment_end("DATA_Z");\r
+ while(pulDest < pulEnd)\r
+ {\r
+ *pulDest++ = 0;\r
+ }\r
+\r
+ //\r
+ // Call the application's entry point.\r
+ //\r
+ main();\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+// This is the code that gets called when the processor receives a NMI. This\r
+// simply enters an infinite loop, preserving the system state for examination\r
+// by a debugger.\r
+//\r
+//*****************************************************************************\r
+static void\r
+NmiSR(void)\r
+{\r
+ //\r
+ // Enter an infinite loop.\r
+ //\r
+ while(1)\r
+ {\r
+ }\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+// This is the code that gets called when the processor receives a fault\r
+// interrupt. This simply enters an infinite loop, preserving the system state\r
+// for examination by a debugger.\r
+//\r
+//*****************************************************************************\r
+static void\r
+FaultISR(void)\r
+{\r
+ //\r
+ // Enter an infinite loop.\r
+ //\r
+ while(1)\r
+ {\r
+ }\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+// This is the code that gets called when the processor receives an unexpected\r
+// interrupt. This simply enters an infinite loop, preserving the system state\r
+// for examination by a debugger.\r
+//\r
+//*****************************************************************************\r
+static void\r
+IntDefaultHandler(void)\r
+{\r
+ //\r
+ // Go into an infinite loop.\r
+ //\r
+ while(1)\r
+ {\r
+ }\r
+}\r
--- /dev/null
+/*\r
+ FreeRTOS.org V4.3.0 - Copyright (C) 2003-2007 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS.org distribution.\r
+\r
+ FreeRTOS.org is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS.org is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS.org; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS.org, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section\r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license\r
+ and contact details. Please ensure to read the configuration and relevant\r
+ port sections of the online documentation.\r
+\r
+ Also see http://www.SafeRTOS.com for an IEC 61508 compliant version along\r
+ with commercial development and support options.\r
+ ***************************************************************************\r
+*/\r
+\r
+/* High speed timer test as described in main.c. */\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+\r
+/* Library includes. */\r
+#include "hw_ints.h"\r
+#include "hw_memmap.h"\r
+#include "hw_types.h"\r
+#include "interrupt.h"\r
+#include "sysctl.h"\r
+#include "LMI_timer.h"\r
+\r
+/* The set frequency of the interrupt. Deviations from this are measured as\r
+the jitter. */\r
+#define timerINTERRUPT_FREQUENCY ( 20000UL )\r
+\r
+/* The expected time between each of the timer interrupts - if the jitter was\r
+zero. */\r
+#define timerEXPECTED_DIFFERENCE_VALUE ( configCPU_CLOCK_HZ / timerINTERRUPT_FREQUENCY )\r
+\r
+/* The highest available interrupt priority. */\r
+#define timerHIGHEST_PRIORITY ( 0 )\r
+\r
+/* Misc defines. */\r
+#define timerMAX_32BIT_VALUE ( 0xffffffffUL )\r
+#define timerTIMER_1_COUNT_VALUE ( * ( ( unsigned long * ) ( TIMER1_BASE + 0x48 ) ) )\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Interrupt handler in which the jitter is measured. */\r
+void Timer0IntHandler( void );\r
+\r
+/* Stores the value of the maximum recorded jitter between interrupts. */\r
+unsigned portLONG ulMaxJitter = 0;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void vSetupTimer( void )\r
+{\r
+unsigned long ulFrequency;\r
+\r
+ /* Timer zero is used to generate the interrupts, and timer 1 is used\r
+ to measure the jitter. */\r
+ SysCtlPeripheralEnable( SYSCTL_PERIPH_TIMER0 );\r
+ SysCtlPeripheralEnable( SYSCTL_PERIPH_TIMER1 );\r
+ TimerConfigure( TIMER0_BASE, TIMER_CFG_32_BIT_PER );\r
+ TimerConfigure( TIMER1_BASE, TIMER_CFG_32_BIT_PER );\r
+ \r
+ /* Set the timer interrupt to be above the kernel - highest. */\r
+ IntPrioritySet( INT_TIMER0A, timerHIGHEST_PRIORITY );\r
+\r
+ /* Just used to measure time. */\r
+ TimerLoadSet(TIMER1_BASE, TIMER_A, timerMAX_32BIT_VALUE );\r
+ \r
+ /* The rate at which the timer will interrupt. */\r
+ ulFrequency = configCPU_CLOCK_HZ / timerINTERRUPT_FREQUENCY; \r
+ TimerLoadSet( TIMER0_BASE, TIMER_A, ulFrequency );\r
+ IntEnable( INT_TIMER0A );\r
+ TimerIntEnable( TIMER0_BASE, TIMER_TIMA_TIMEOUT );\r
+\r
+ /* Enable both timers. */ \r
+ TimerEnable( TIMER0_BASE, TIMER_A );\r
+ TimerEnable( TIMER1_BASE, TIMER_A );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void Timer0IntHandler( void )\r
+{\r
+unsigned portLONG ulDifference, ulCurrentCount;\r
+static portLONG ulMaxDifference = 0, ulLastCount = 0;\r
+\r
+ /* We use the timer 1 counter value to measure the clock cycles between\r
+ the timer 0 interrupts. */\r
+ ulCurrentCount = timerTIMER_1_COUNT_VALUE;\r
+\r
+ if( ulCurrentCount < ulLastCount )\r
+ { \r
+ /* How many times has timer 1 counted since the last interrupt? */\r
+ ulDifference = ulLastCount - ulCurrentCount;\r
+ \r
+ /* Is this the largest difference we have measured yet? */\r
+ if( ulDifference > ulMaxDifference )\r
+ {\r
+ ulMaxDifference = ulDifference;\r
+ ulMaxJitter = ulMaxDifference - timerEXPECTED_DIFFERENCE_VALUE;\r
+ }\r
+ }\r
+ \r
+ ulLastCount = ulCurrentCount;\r
+\r
+ TimerIntClear( TIMER0_BASE, TIMER_TIMA_TIMEOUT );\r
+}\r
+\r
+\r
+\r
+\r
+\r
--- /dev/null
+APP_SOURCES += httpd.c http-strings.c httpd-fs.c httpd-cgi.c\r
--- /dev/null
+/*\r
+ * Copyright (c) 2006, Swedish Institute of Computer Science.\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ * 1. Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the\r
+ * documentation and/or other materials provided with the distribution.\r
+ * 3. Neither the name of the Institute nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND\r
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\r
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\r
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\r
+ * SUCH DAMAGE.\r
+ *\r
+ * This file is part of the uIP TCP/IP stack\r
+ *\r
+ * $Id: clock-arch.h,v 1.2 2006/06/12 08:00:31 adam Exp $\r
+ */\r
+\r
+#ifndef __CLOCK_ARCH_H__\r
+#define __CLOCK_ARCH_H__\r
+\r
+#include "FreeRTOS.h"\r
+\r
+typedef unsigned long clock_time_t;\r
+#define CLOCK_CONF_SECOND configTICK_RATE_HZ\r
+\r
+#endif /* __CLOCK_ARCH_H__ */\r
--- /dev/null
+/*\r
+ FreeRTOS.org V4.3.0 - Copyright (C) 2003-2007 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS.org distribution.\r
+\r
+ FreeRTOS.org is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS.org is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS.org; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS.org, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section\r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license\r
+ and contact details. Please ensure to read the configuration and relevant\r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/* Kernel includes. */\r
+#include "FreeRTOS.h"\r
+#include "Semphr.h"\r
+#include "task.h"\r
+\r
+/* Demo includes. */\r
+#include "EMAC.h"\r
+\r
+/* uIP includes. */\r
+#include "uip.h"\r
+\r
+/* Hardware library includes. */\r
+#include "hw_types.h"\r
+#include "hw_memmap.h"\r
+#include "hw_ints.h"\r
+#include "hw_ethernet.h"\r
+#include "ethernet.h"\r
+#include "interrupt.h"\r
+\r
+#define emacNUM_RX_BUFFERS 5\r
+#define emacFRAM_SIZE_BYTES 2\r
+#define macNEGOTIATE_DELAY 2000\r
+#define macWAIT_SEND_TIME ( 10 )\r
+\r
+/* The task that handles the MAC peripheral. This is created at a high\r
+priority and is effectively a deferred interrupt handler. The peripheral\r
+handling is deferred to a task to prevent the entire FIFO having to be read\r
+from within an ISR. */\r
+void vMACHandleTask( void *pvParameters );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* The semaphore used to wake the uIP task when data arrives. */\r
+xSemaphoreHandle xEMACSemaphore = NULL;\r
+\r
+/* The semaphore used to wake the interrupt handler task. The peripheral\r
+is processed at the task level to prevent the need to read the entire FIFO from\r
+within the ISR itself. */\r
+xSemaphoreHandle xMACInterruptSemaphore = NULL;\r
+\r
+/* The buffer used by the uIP stack. In this case the pointer is used to\r
+point to one of the Rx buffers. */\r
+unsigned portCHAR *uip_buf;\r
+\r
+/* Buffers into which Rx data is placed. */\r
+static unsigned portCHAR ucRxBuffers[ emacNUM_RX_BUFFERS ][ UIP_BUFSIZE + ( 4 * emacFRAM_SIZE_BYTES ) ];\r
+\r
+/* The length of the data within each of the Rx buffers. */\r
+static unsigned portLONG ulRxLength[ emacNUM_RX_BUFFERS ];\r
+\r
+/* Used to keep a track of the number of bytes to transmit. */\r
+static unsigned portLONG ulNextTxSpace;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+portBASE_TYPE vInitEMAC( void )\r
+{\r
+unsigned long ulTemp;\r
+portBASE_TYPE xReturn;\r
+\r
+ /* Ensure all interrupts are disabled. */\r
+ EthernetIntDisable( ETH_BASE, ( ETH_INT_PHY | ETH_INT_MDIO | ETH_INT_RXER | ETH_INT_RXOF | ETH_INT_TX | ETH_INT_TXER | ETH_INT_RX));\r
+\r
+ /* Clear any interrupts that were already pending. */\r
+ ulTemp = EthernetIntStatus( ETH_BASE, pdFALSE );\r
+ EthernetIntClear( ETH_BASE, ulTemp );\r
+\r
+ /* Initialise the MAC and connect. */\r
+ EthernetInit( ETH_BASE );\r
+ EthernetConfigSet( ETH_BASE, ( ETH_CFG_TX_DPLXEN | ETH_CFG_TX_CRCEN | ETH_CFG_TX_PADEN ) );\r
+ EthernetEnable( ETH_BASE );\r
+\r
+ /* Mark each Rx buffer as empty. */\r
+ for( ulTemp = 0; ulTemp < emacNUM_RX_BUFFERS; ulTemp++ )\r
+ {\r
+ ulRxLength[ ulTemp ] = 0;\r
+ }\r
+ \r
+ /* Create the queue and task used to defer the MAC processing to the\r
+ task level. */\r
+ vSemaphoreCreateBinary( xMACInterruptSemaphore );\r
+ xSemaphoreTake( xMACInterruptSemaphore, 0 );\r
+ xReturn = xTaskCreate( vMACHandleTask, ( signed portCHAR * ) "MAC", configMINIMAL_STACK_SIZE, NULL, configMAX_PRIORITIES - 1, NULL );\r
+ vTaskDelay( macNEGOTIATE_DELAY );\r
+ \r
+ /* We are only interested in Rx interrupts. */\r
+ IntPrioritySet( INT_ETH, configKERNEL_INTERRUPT_PRIORITY );\r
+ IntEnable( INT_ETH );\r
+ EthernetIntEnable(ETH_BASE, ETH_INT_RX);\r
+\r
+ return xReturn;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+unsigned int uiGetEMACRxData( unsigned char *ucBuffer )\r
+{\r
+static unsigned long ulNextRxBuffer = 0;\r
+unsigned int iLen;\r
+\r
+ iLen = ulRxLength[ ulNextRxBuffer ];\r
+\r
+ if( iLen != 0 )\r
+ {\r
+ /* Leave room for the size at the start of the buffer. */\r
+ uip_buf = &( ucRxBuffers[ ulNextRxBuffer ][ 2 ] );\r
+ \r
+ ulRxLength[ ulNextRxBuffer ] = 0;\r
+ \r
+ ulNextRxBuffer++;\r
+ if( ulNextRxBuffer >= emacNUM_RX_BUFFERS )\r
+ {\r
+ ulNextRxBuffer = 0;\r
+ }\r
+ }\r
+\r
+ return iLen;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vInitialiseSend( void )\r
+{\r
+ /* Set the index to the first byte to send - skipping over the size\r
+ bytes. */\r
+ ulNextTxSpace = 2;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vIncrementTxLength( unsigned portLONG ulLength )\r
+{\r
+ ulNextTxSpace += ulLength;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vSendBufferToMAC( void )\r
+{\r
+unsigned long *pulSource;\r
+unsigned portSHORT * pus;\r
+unsigned portLONG ulNextWord;\r
+\r
+ /* Locate the data to be send. */\r
+ pus = ( unsigned portSHORT * ) uip_buf;\r
+\r
+ /* Add in the size of the data. */\r
+ pus--;\r
+ *pus = ulNextTxSpace;\r
+\r
+ /* Wait for data to be sent if there is no space immediately. */\r
+ while( !EthernetSpaceAvail( ETH_BASE ) )\r
+ {\r
+ vTaskDelay( macWAIT_SEND_TIME );\r
+ }\r
+ \r
+ pulSource = ( unsigned portLONG * ) pus; \r
+ \r
+ for( ulNextWord = 0; ulNextWord < ulNextTxSpace; ulNextWord += sizeof( unsigned portLONG ) )\r
+ {\r
+ HWREG(ETH_BASE + MAC_O_DATA) = *pulSource;\r
+ pulSource++;\r
+ }\r
+\r
+ /* Go. */\r
+ HWREG( ETH_BASE + MAC_O_TR ) = MAC_TR_NEWTX;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vEMAC_ISR( void )\r
+{\r
+portBASE_TYPE xSwitchRequired = pdFALSE;\r
+unsigned portLONG ulTemp;\r
+\r
+ /* Clear the interrupt. */\r
+ ulTemp = EthernetIntStatus( ETH_BASE, pdFALSE );\r
+ EthernetIntClear( ETH_BASE, ulTemp );\r
+ \r
+ /* Was it an Rx interrupt? */\r
+ if( ulTemp & ETH_INT_RX )\r
+ {\r
+ xSwitchRequired = pdTRUE;\r
+ xSemaphoreGiveFromISR( xMACInterruptSemaphore, pdFALSE );\r
+ EthernetIntDisable( ETH_BASE, ETH_INT_RX );\r
+ }\r
+ \r
+ /* Switch to the uIP task. */\r
+ portEND_SWITCHING_ISR( xSwitchRequired );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vMACHandleTask( void *pvParameters )\r
+{\r
+unsigned long ulLen = 0, i;\r
+unsigned portLONG ulLength, ulInt;\r
+unsigned long *pulBuffer;\r
+static unsigned portLONG ulNextRxBuffer = 0;\r
+portBASE_TYPE xSwitchRequired = pdFALSE;\r
+\r
+ for( ;; )\r
+ {\r
+ /* Wait for something to do. */\r
+ xSemaphoreTake( xMACInterruptSemaphore, portMAX_DELAY );\r
+ \r
+ while( ( ulInt = ( EthernetIntStatus( ETH_BASE, pdFALSE ) & ETH_INT_RX ) ) != 0 )\r
+ { \r
+ ulLength = HWREG( ETH_BASE + MAC_O_DATA );\r
+ \r
+ /* Leave room at the start of the buffer for the size. */\r
+ pulBuffer = ( unsigned long * ) &( ucRxBuffers[ ulNextRxBuffer ][ 2 ] ); \r
+ *pulBuffer = ( ulLength >> 16 );\r
+\r
+ /* Get the size of the data. */ \r
+ pulBuffer = ( unsigned long * ) &( ucRxBuffers[ ulNextRxBuffer ][ 4 ] ); \r
+ ulLength &= 0xFFFF;\r
+ \r
+ if( ulLength > 4 )\r
+ {\r
+ ulLength -= 4;\r
+ \r
+ if( ulLength >= UIP_BUFSIZE )\r
+ {\r
+ /* The data won't fit in our buffer. Ensure we don't\r
+ try to write into the buffer. */\r
+ ulLength = 0;\r
+ }\r
+\r
+ /* Read out the data into our buffer. */\r
+ for( i = 0; i < ulLength; i += sizeof( unsigned portLONG ) )\r
+ {\r
+ *pulBuffer = HWREG( ETH_BASE + MAC_O_DATA );\r
+ pulBuffer++;\r
+ }\r
+ \r
+ /* Store the length of the data into the separate array. */\r
+ ulRxLength[ ulNextRxBuffer ] = ulLength;\r
+ \r
+ /* Use the next buffer the next time through. */\r
+ ulNextRxBuffer++;\r
+ if( ulNextRxBuffer >= emacNUM_RX_BUFFERS )\r
+ {\r
+ ulNextRxBuffer = 0;\r
+ }\r
+ \r
+ /* Ensure the uIP task is not blocked as data has arrived. */\r
+ xSemaphoreGive( xEMACSemaphore );\r
+ }\r
+ }\r
+ \r
+ EthernetIntEnable( ETH_BASE, ETH_INT_RX );\r
+ }\r
+}\r
+\r
--- /dev/null
+/*----------------------------------------------------------------------------\r
+ * LPC2378 Ethernet Definitions\r
+ *----------------------------------------------------------------------------\r
+ * Name: EMAC.H\r
+ * Purpose: Philips LPC2378 EMAC hardware definitions\r
+ *----------------------------------------------------------------------------\r
+ * Copyright (c) 2006 KEIL - An ARM Company. All rights reserved.\r
+ *---------------------------------------------------------------------------*/\r
+#ifndef __EMAC_H\r
+#define __EMAC_H\r
+\r
+/* MAC address definition. The MAC address must be unique on the network. */\r
+#define emacETHADDR0 0\r
+#define emacETHADDR1 0xbd\r
+#define emacETHADDR2 0x33\r
+#define emacETHADDR3 0x02\r
+#define emacETHADDR4 0x64\r
+#define emacETHADDR5 0x24\r
+\r
+\r
+/* EMAC Memory Buffer configuration for 16K Ethernet RAM. */\r
+#define NUM_RX_FRAG 4 /* Num.of RX Fragments 4*1536= 6.0kB */\r
+#define NUM_TX_FRAG 2 /* Num.of TX Fragments 2*1536= 3.0kB */\r
+#define ETH_FRAG_SIZE 1536 /* Packet Fragment size 1536 Bytes */\r
+\r
+#define ETH_MAX_FLEN 1536 /* Max. Ethernet Frame Size */\r
+\r
+/* EMAC variables located in 16K Ethernet SRAM */\r
+#define RX_DESC_BASE 0x7FE00000\r
+#define RX_STAT_BASE (RX_DESC_BASE + NUM_RX_FRAG*8)\r
+#define TX_DESC_BASE (RX_STAT_BASE + NUM_RX_FRAG*8)\r
+#define TX_STAT_BASE (TX_DESC_BASE + NUM_TX_FRAG*8)\r
+#define RX_BUF_BASE (TX_STAT_BASE + NUM_TX_FRAG*4)\r
+#define TX_BUF_BASE (RX_BUF_BASE + NUM_RX_FRAG*ETH_FRAG_SIZE)\r
+\r
+/* RX and TX descriptor and status definitions. */\r
+#define RX_DESC_PACKET(i) (*(unsigned int *)(RX_DESC_BASE + 8*i))\r
+#define RX_DESC_CTRL(i) (*(unsigned int *)(RX_DESC_BASE+4 + 8*i))\r
+#define RX_STAT_INFO(i) (*(unsigned int *)(RX_STAT_BASE + 8*i))\r
+#define RX_STAT_HASHCRC(i) (*(unsigned int *)(RX_STAT_BASE+4 + 8*i))\r
+#define TX_DESC_PACKET(i) (*(unsigned int *)(TX_DESC_BASE + 8*i))\r
+#define TX_DESC_CTRL(i) (*(unsigned int *)(TX_DESC_BASE+4 + 8*i))\r
+#define TX_STAT_INFO(i) (*(unsigned int *)(TX_STAT_BASE + 4*i))\r
+#define RX_BUF(i) (RX_BUF_BASE + ETH_FRAG_SIZE*i)\r
+#define TX_BUF(i) (TX_BUF_BASE + ETH_FRAG_SIZE*i)\r
+\r
+/* MAC Configuration Register 1 */\r
+#define MAC1_REC_EN 0x00000001 /* Receive Enable */\r
+#define MAC1_PASS_ALL 0x00000002 /* Pass All Receive Frames */\r
+#define MAC1_RX_FLOWC 0x00000004 /* RX Flow Control */\r
+#define MAC1_TX_FLOWC 0x00000008 /* TX Flow Control */\r
+#define MAC1_LOOPB 0x00000010 /* Loop Back Mode */\r
+#define MAC1_RES_TX 0x00000100 /* Reset TX Logic */\r
+#define MAC1_RES_MCS_TX 0x00000200 /* Reset MAC TX Control Sublayer */\r
+#define MAC1_RES_RX 0x00000400 /* Reset RX Logic */\r
+#define MAC1_RES_MCS_RX 0x00000800 /* Reset MAC RX Control Sublayer */\r
+#define MAC1_SIM_RES 0x00004000 /* Simulation Reset */\r
+#define MAC1_SOFT_RES 0x00008000 /* Soft Reset MAC */\r
+\r
+/* MAC Configuration Register 2 */\r
+#define MAC2_FULL_DUP 0x00000001 /* Full Duplex Mode */\r
+#define MAC2_FRM_LEN_CHK 0x00000002 /* Frame Length Checking */\r
+#define MAC2_HUGE_FRM_EN 0x00000004 /* Huge Frame Enable */\r
+#define MAC2_DLY_CRC 0x00000008 /* Delayed CRC Mode */\r
+#define MAC2_CRC_EN 0x00000010 /* Append CRC to every Frame */\r
+#define MAC2_PAD_EN 0x00000020 /* Pad all Short Frames */\r
+#define MAC2_VLAN_PAD_EN 0x00000040 /* VLAN Pad Enable */\r
+#define MAC2_ADET_PAD_EN 0x00000080 /* Auto Detect Pad Enable */\r
+#define MAC2_PPREAM_ENF 0x00000100 /* Pure Preamble Enforcement */\r
+#define MAC2_LPREAM_ENF 0x00000200 /* Long Preamble Enforcement */\r
+#undef MAC2_NO_BACKOFF /* Remove compiler warning. */\r
+#define MAC2_NO_BACKOFF 0x00001000 /* No Backoff Algorithm */\r
+#define MAC2_BACK_PRESSURE 0x00002000 /* Backoff Presurre / No Backoff */\r
+#define MAC2_EXCESS_DEF 0x00004000 /* Excess Defer */\r
+\r
+/* Back-to-Back Inter-Packet-Gap Register */\r
+#define IPGT_FULL_DUP 0x00000015 /* Recommended value for Full Duplex */\r
+#define IPGT_HALF_DUP 0x00000012 /* Recommended value for Half Duplex */\r
+\r
+/* Non Back-to-Back Inter-Packet-Gap Register */\r
+#define IPGR_DEF 0x00000012 /* Recommended value */\r
+\r
+/* Collision Window/Retry Register */\r
+#define CLRT_DEF 0x0000370F /* Default value */\r
+\r
+/* PHY Support Register */\r
+#undef SUPP_SPEED /* Remove compiler warning. */\r
+#define SUPP_SPEED 0x00000100 /* Reduced MII Logic Current Speed */\r
+#define SUPP_RES_RMII 0x00000800 /* Reset Reduced MII Logic */\r
+\r
+/* Test Register */\r
+#define TEST_SHCUT_PQUANTA 0x00000001 /* Shortcut Pause Quanta */\r
+#define TEST_TST_PAUSE 0x00000002 /* Test Pause */\r
+#define TEST_TST_BACKP 0x00000004 /* Test Back Pressure */\r
+\r
+/* MII Management Configuration Register */\r
+#define MCFG_SCAN_INC 0x00000001 /* Scan Increment PHY Address */\r
+#define MCFG_SUPP_PREAM 0x00000002 /* Suppress Preamble */\r
+#define MCFG_CLK_SEL 0x0000001C /* Clock Select Mask */\r
+#define MCFG_RES_MII 0x00008000 /* Reset MII Management Hardware */\r
+\r
+/* MII Management Command Register */\r
+#undef MCMD_READ /* Remove compiler warning. */\r
+#define MCMD_READ 0x00000001 /* MII Read */\r
+#undef MCMD_SCAN /* Remove compiler warning. */\r
+#define MCMD_SCAN 0x00000002 /* MII Scan continuously */\r
+\r
+#define MII_WR_TOUT 0x00050000 /* MII Write timeout count */\r
+#define MII_RD_TOUT 0x00050000 /* MII Read timeout count */\r
+\r
+/* MII Management Address Register */\r
+#define MADR_REG_ADR 0x0000001F /* MII Register Address Mask */\r
+#define MADR_PHY_ADR 0x00001F00 /* PHY Address Mask */\r
+\r
+/* MII Management Indicators Register */\r
+#undef MIND_BUSY /* Remove compiler warning. */\r
+#define MIND_BUSY 0x00000001 /* MII is Busy */\r
+#define MIND_SCAN 0x00000002 /* MII Scanning in Progress */\r
+#define MIND_NOT_VAL 0x00000004 /* MII Read Data not valid */\r
+#define MIND_MII_LINK_FAIL 0x00000008 /* MII Link Failed */\r
+\r
+/* Command Register */\r
+#define CR_RX_EN 0x00000001 /* Enable Receive */\r
+#define CR_TX_EN 0x00000002 /* Enable Transmit */\r
+#define CR_REG_RES 0x00000008 /* Reset Host Registers */\r
+#define CR_TX_RES 0x00000010 /* Reset Transmit Datapath */\r
+#define CR_RX_RES 0x00000020 /* Reset Receive Datapath */\r
+#define CR_PASS_RUNT_FRM 0x00000040 /* Pass Runt Frames */\r
+#define CR_PASS_RX_FILT 0x00000080 /* Pass RX Filter */\r
+#define CR_TX_FLOW_CTRL 0x00000100 /* TX Flow Control */\r
+#define CR_RMII 0x00000200 /* Reduced MII Interface */\r
+#define CR_FULL_DUP 0x00000400 /* Full Duplex */\r
+\r
+/* Status Register */\r
+#define SR_RX_EN 0x00000001 /* Enable Receive */\r
+#define SR_TX_EN 0x00000002 /* Enable Transmit */\r
+\r
+/* Transmit Status Vector 0 Register */\r
+#define TSV0_CRC_ERR 0x00000001 /* CRC error */\r
+#define TSV0_LEN_CHKERR 0x00000002 /* Length Check Error */\r
+#define TSV0_LEN_OUTRNG 0x00000004 /* Length Out of Range */\r
+#define TSV0_DONE 0x00000008 /* Tramsmission Completed */\r
+#define TSV0_MCAST 0x00000010 /* Multicast Destination */\r
+#define TSV0_BCAST 0x00000020 /* Broadcast Destination */\r
+#define TSV0_PKT_DEFER 0x00000040 /* Packet Deferred */\r
+#define TSV0_EXC_DEFER 0x00000080 /* Excessive Packet Deferral */\r
+#define TSV0_EXC_COLL 0x00000100 /* Excessive Collision */\r
+#define TSV0_LATE_COLL 0x00000200 /* Late Collision Occured */\r
+#define TSV0_GIANT 0x00000400 /* Giant Frame */\r
+#define TSV0_UNDERRUN 0x00000800 /* Buffer Underrun */\r
+#define TSV0_BYTES 0x0FFFF000 /* Total Bytes Transferred */\r
+#define TSV0_CTRL_FRAME 0x10000000 /* Control Frame */\r
+#define TSV0_PAUSE 0x20000000 /* Pause Frame */\r
+#define TSV0_BACK_PRESS 0x40000000 /* Backpressure Method Applied */\r
+#define TSV0_VLAN 0x80000000 /* VLAN Frame */\r
+\r
+/* Transmit Status Vector 1 Register */\r
+#define TSV1_BYTE_CNT 0x0000FFFF /* Transmit Byte Count */\r
+#define TSV1_COLL_CNT 0x000F0000 /* Transmit Collision Count */\r
+\r
+/* Receive Status Vector Register */\r
+#define RSV_BYTE_CNT 0x0000FFFF /* Receive Byte Count */\r
+#define RSV_PKT_IGNORED 0x00010000 /* Packet Previously Ignored */\r
+#define RSV_RXDV_SEEN 0x00020000 /* RXDV Event Previously Seen */\r
+#define RSV_CARR_SEEN 0x00040000 /* Carrier Event Previously Seen */\r
+#define RSV_REC_CODEV 0x00080000 /* Receive Code Violation */\r
+#define RSV_CRC_ERR 0x00100000 /* CRC Error */\r
+#define RSV_LEN_CHKERR 0x00200000 /* Length Check Error */\r
+#define RSV_LEN_OUTRNG 0x00400000 /* Length Out of Range */\r
+#define RSV_REC_OK 0x00800000 /* Frame Received OK */\r
+#define RSV_MCAST 0x01000000 /* Multicast Frame */\r
+#define RSV_BCAST 0x02000000 /* Broadcast Frame */\r
+#define RSV_DRIB_NIBB 0x04000000 /* Dribble Nibble */\r
+#define RSV_CTRL_FRAME 0x08000000 /* Control Frame */\r
+#define RSV_PAUSE 0x10000000 /* Pause Frame */\r
+#define RSV_UNSUPP_OPC 0x20000000 /* Unsupported Opcode */\r
+#define RSV_VLAN 0x40000000 /* VLAN Frame */\r
+\r
+/* Flow Control Counter Register */\r
+#define FCC_MIRR_CNT 0x0000FFFF /* Mirror Counter */\r
+#define FCC_PAUSE_TIM 0xFFFF0000 /* Pause Timer */\r
+\r
+/* Flow Control Status Register */\r
+#define FCS_MIRR_CNT 0x0000FFFF /* Mirror Counter Current */\r
+\r
+/* Receive Filter Control Register */\r
+#define RFC_UCAST_EN 0x00000001 /* Accept Unicast Frames Enable */\r
+#define RFC_BCAST_EN 0x00000002 /* Accept Broadcast Frames Enable */\r
+#define RFC_MCAST_EN 0x00000004 /* Accept Multicast Frames Enable */\r
+#define RFC_UCAST_HASH_EN 0x00000008 /* Accept Unicast Hash Filter Frames */\r
+#define RFC_MCAST_HASH_EN 0x00000010 /* Accept Multicast Hash Filter Fram.*/\r
+#define RFC_PERFECT_EN 0x00000020 /* Accept Perfect Match Enable */\r
+#define RFC_MAGP_WOL_EN 0x00001000 /* Magic Packet Filter WoL Enable */\r
+#define RFC_PFILT_WOL_EN 0x00002000 /* Perfect Filter WoL Enable */\r
+\r
+/* Receive Filter WoL Status/Clear Registers */\r
+#define WOL_UCAST 0x00000001 /* Unicast Frame caused WoL */\r
+#define WOL_BCAST 0x00000002 /* Broadcast Frame caused WoL */\r
+#define WOL_MCAST 0x00000004 /* Multicast Frame caused WoL */\r
+#define WOL_UCAST_HASH 0x00000008 /* Unicast Hash Filter Frame WoL */\r
+#define WOL_MCAST_HASH 0x00000010 /* Multicast Hash Filter Frame WoL */\r
+#define WOL_PERFECT 0x00000020 /* Perfect Filter WoL */\r
+#define WOL_RX_FILTER 0x00000080 /* RX Filter caused WoL */\r
+#define WOL_MAG_PACKET 0x00000100 /* Magic Packet Filter caused WoL */\r
+\r
+/* Interrupt Status/Enable/Clear/Set Registers */\r
+#define INT_RX_OVERRUN 0x00000001 /* Overrun Error in RX Queue */\r
+#define INT_RX_ERR 0x00000002 /* Receive Error */\r
+#define INT_RX_FIN 0x00000004 /* RX Finished Process Descriptors */\r
+#define INT_RX_DONE 0x00000008 /* Receive Done */\r
+#define INT_TX_UNDERRUN 0x00000010 /* Transmit Underrun */\r
+#define INT_TX_ERR 0x00000020 /* Transmit Error */\r
+#define INT_TX_FIN 0x00000040 /* TX Finished Process Descriptors */\r
+#define INT_TX_DONE 0x00000080 /* Transmit Done */\r
+#define INT_SOFT_INT 0x00001000 /* Software Triggered Interrupt */\r
+#define INT_WAKEUP 0x00002000 /* Wakeup Event Interrupt */\r
+\r
+/* Power Down Register */\r
+#define PD_POWER_DOWN 0x80000000 /* Power Down MAC */\r
+\r
+/* RX Descriptor Control Word */\r
+#define RCTRL_SIZE 0x000007FF /* Buffer size mask */\r
+#define RCTRL_INT 0x80000000 /* Generate RxDone Interrupt */\r
+\r
+/* RX Status Hash CRC Word */\r
+#define RHASH_SA 0x000001FF /* Hash CRC for Source Address */\r
+#define RHASH_DA 0x001FF000 /* Hash CRC for Destination Address */\r
+\r
+/* RX Status Information Word */\r
+#define RINFO_SIZE 0x000007FF /* Data size in bytes */\r
+#define RINFO_CTRL_FRAME 0x00040000 /* Control Frame */\r
+#define RINFO_VLAN 0x00080000 /* VLAN Frame */\r
+#define RINFO_FAIL_FILT 0x00100000 /* RX Filter Failed */\r
+#define RINFO_MCAST 0x00200000 /* Multicast Frame */\r
+#define RINFO_BCAST 0x00400000 /* Broadcast Frame */\r
+#define RINFO_CRC_ERR 0x00800000 /* CRC Error in Frame */\r
+#define RINFO_SYM_ERR 0x01000000 /* Symbol Error from PHY */\r
+#define RINFO_LEN_ERR 0x02000000 /* Length Error */\r
+#define RINFO_RANGE_ERR 0x04000000 /* Range Error (exceeded max. size) */\r
+#define RINFO_ALIGN_ERR 0x08000000 /* Alignment Error */\r
+#define RINFO_OVERRUN 0x10000000 /* Receive overrun */\r
+#define RINFO_NO_DESCR 0x20000000 /* No new Descriptor available */\r
+#define RINFO_LAST_FLAG 0x40000000 /* Last Fragment in Frame */\r
+#define RINFO_ERR 0x80000000 /* Error Occured (OR of all errors) */\r
+\r
+#define RINFO_ERR_MASK (RINFO_FAIL_FILT | RINFO_CRC_ERR | RINFO_SYM_ERR | \\r
+ RINFO_LEN_ERR | RINFO_ALIGN_ERR | RINFO_OVERRUN)\r
+\r
+/* TX Descriptor Control Word */\r
+#define TCTRL_SIZE 0x000007FF /* Size of data buffer in bytes */\r
+#define TCTRL_OVERRIDE 0x04000000 /* Override Default MAC Registers */\r
+#define TCTRL_HUGE 0x08000000 /* Enable Huge Frame */\r
+#define TCTRL_PAD 0x10000000 /* Pad short Frames to 64 bytes */\r
+#define TCTRL_CRC 0x20000000 /* Append a hardware CRC to Frame */\r
+#define TCTRL_LAST 0x40000000 /* Last Descriptor for TX Frame */\r
+#define TCTRL_INT 0x80000000 /* Generate TxDone Interrupt */\r
+\r
+/* TX Status Information Word */\r
+#define TINFO_COL_CNT 0x01E00000 /* Collision Count */\r
+#define TINFO_DEFER 0x02000000 /* Packet Deferred (not an error) */\r
+#define TINFO_EXCESS_DEF 0x04000000 /* Excessive Deferral */\r
+#define TINFO_EXCESS_COL 0x08000000 /* Excessive Collision */\r
+#define TINFO_LATE_COL 0x10000000 /* Late Collision Occured */\r
+#define TINFO_UNDERRUN 0x20000000 /* Transmit Underrun */\r
+#define TINFO_NO_DESCR 0x40000000 /* No new Descriptor available */\r
+#define TINFO_ERR 0x80000000 /* Error Occured (OR of all errors) */\r
+\r
+/* DP83848C PHY Registers */\r
+#define PHY_REG_BMCR 0x00 /* Basic Mode Control Register */\r
+#define PHY_REG_BMSR 0x01 /* Basic Mode Status Register */\r
+#define PHY_REG_IDR1 0x02 /* PHY Identifier 1 */\r
+#define PHY_REG_IDR2 0x03 /* PHY Identifier 2 */\r
+#define PHY_REG_ANAR 0x04 /* Auto-Negotiation Advertisement */\r
+#define PHY_REG_ANLPAR 0x05 /* Auto-Neg. Link Partner Abitily */\r
+#define PHY_REG_ANER 0x06 /* Auto-Neg. Expansion Register */\r
+#define PHY_REG_ANNPTR 0x07 /* Auto-Neg. Next Page TX */\r
+\r
+/* PHY Extended Registers */\r
+#define PHY_REG_STS 0x10 /* Status Register */\r
+#define PHY_REG_MICR 0x11 /* MII Interrupt Control Register */\r
+#define PHY_REG_MISR 0x12 /* MII Interrupt Status Register */\r
+#define PHY_REG_FCSCR 0x14 /* False Carrier Sense Counter */\r
+#define PHY_REG_RECR 0x15 /* Receive Error Counter */\r
+#define PHY_REG_PCSR 0x16 /* PCS Sublayer Config. and Status */\r
+#define PHY_REG_RBR 0x17 /* RMII and Bypass Register */\r
+#define PHY_REG_LEDCR 0x18 /* LED Direct Control Register */\r
+#define PHY_REG_PHYCR 0x19 /* PHY Control Register */\r
+#define PHY_REG_10BTSCR 0x1A /* 10Base-T Status/Control Register */\r
+#define PHY_REG_CDCTRL1 0x1B /* CD Test Control and BIST Extens. */\r
+#define PHY_REG_EDCR 0x1D /* Energy Detect Control Register */\r
+\r
+#define PHY_FULLD_100M 0x2100 /* Full Duplex 100Mbit */\r
+#define PHY_HALFD_100M 0x2000 /* Half Duplex 100Mbit */\r
+#define PHY_FULLD_10M 0x0100 /* Full Duplex 10Mbit */\r
+#define PHY_HALFD_10M 0x0000 /* Half Duplex 10MBit */\r
+#define PHY_AUTO_NEG 0x3000 /* Select Auto Negotiation */\r
+\r
+#define DP83848C_DEF_ADR 0x0100 /* Default PHY device address */\r
+#define DP83848C_ID 0x20005C90 /* PHY Identifier */\r
+\r
+// prototypes\r
+portBASE_TYPE vInitEMAC(void);\r
+unsigned short ReadFrameBE_EMAC(void);\r
+void vIncrementTxLength(unsigned long ulLength);\r
+void CopyFromFrame_EMAC(void *Dest, unsigned short Size);\r
+void DummyReadFrame_EMAC(unsigned short Size);\r
+unsigned short StartReadFrame(void);\r
+void EndReadFrame(void);\r
+unsigned int CheckFrameReceived(void);\r
+void vInitialiseSend(void);\r
+unsigned int Rdy4Tx(void);\r
+void vSendBufferToMAC(void);\r
+void vEMACWaitForInput( void );\r
+unsigned int uiGetEMACRxData( unsigned char *ucBuffer );\r
+\r
+\r
+#endif\r
+\r
+/*----------------------------------------------------------------------------\r
+ * end of file\r
+ *---------------------------------------------------------------------------*/\r
+\r
--- /dev/null
+http_http "http://"\r
+http_200 "200 "\r
+http_301 "301 "\r
+http_302 "302 "\r
+http_get "GET "\r
+http_10 "HTTP/1.0"\r
+http_11 "HTTP/1.1"\r
+http_content_type "content-type: "\r
+http_texthtml "text/html"\r
+http_location "location: "\r
+http_host "host: "\r
+http_crnl "\r\n"\r
+http_index_html "/index.html"\r
+http_404_html "/404.html"\r
+http_referer "Referer:"\r
+http_header_200 "HTTP/1.0 200 OK\r\nServer: uIP/1.0 http://www.sics.se/~adam/uip/\r\nConnection: close\r\n"\r
+http_header_404 "HTTP/1.0 404 Not found\r\nServer: uIP/1.0 http://www.sics.se/~adam/uip/\r\nConnection: close\r\n"\r
+http_content_type_plain "Content-type: text/plain\r\n\r\n"\r
+http_content_type_html "Content-type: text/html\r\n\r\n"\r
+http_content_type_css "Content-type: text/css\r\n\r\n"\r
+http_content_type_text "Content-type: text/text\r\n\r\n"\r
+http_content_type_png "Content-type: image/png\r\n\r\n"\r
+http_content_type_gif "Content-type: image/gif\r\n\r\n"\r
+http_content_type_jpg "Content-type: image/jpeg\r\n\r\n"\r
+http_content_type_binary "Content-type: application/octet-stream\r\n\r\n"\r
+http_html ".html"\r
+http_shtml ".shtml"\r
+http_htm ".htm"\r
+http_css ".css"\r
+http_png ".png"\r
+http_gif ".gif"\r
+http_jpg ".jpg"\r
+http_text ".txt"\r
+http_txt ".txt"\r
+\r
--- /dev/null
+const char http_http[8] = \r
+/* "http://" */\r
+{0x68, 0x74, 0x74, 0x70, 0x3a, 0x2f, 0x2f, };\r
+const char http_200[5] = \r
+/* "200 " */\r
+{0x32, 0x30, 0x30, 0x20, };\r
+const char http_301[5] = \r
+/* "301 " */\r
+{0x33, 0x30, 0x31, 0x20, };\r
+const char http_302[5] = \r
+/* "302 " */\r
+{0x33, 0x30, 0x32, 0x20, };\r
+const char http_get[5] = \r
+/* "GET " */\r
+{0x47, 0x45, 0x54, 0x20, };\r
+const char http_10[9] = \r
+/* "HTTP/1.0" */\r
+{0x48, 0x54, 0x54, 0x50, 0x2f, 0x31, 0x2e, 0x30, };\r
+const char http_11[9] = \r
+/* "HTTP/1.1" */\r
+{0x48, 0x54, 0x54, 0x50, 0x2f, 0x31, 0x2e, 0x31, };\r
+const char http_content_type[15] = \r
+/* "content-type: " */\r
+{0x63, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, };\r
+const char http_texthtml[10] = \r
+/* "text/html" */\r
+{0x74, 0x65, 0x78, 0x74, 0x2f, 0x68, 0x74, 0x6d, 0x6c, };\r
+const char http_location[11] = \r
+/* "location: " */\r
+{0x6c, 0x6f, 0x63, 0x61, 0x74, 0x69, 0x6f, 0x6e, 0x3a, 0x20, };\r
+const char http_host[7] = \r
+/* "host: " */\r
+{0x68, 0x6f, 0x73, 0x74, 0x3a, 0x20, };\r
+const char http_crnl[3] = \r
+/* "\r\n" */\r
+{0xd, 0xa, };\r
+const char http_index_html[12] = \r
+/* "/index.html" */\r
+{0x2f, 0x69, 0x6e, 0x64, 0x65, 0x78, 0x2e, 0x68, 0x74, 0x6d, 0x6c, };\r
+const char http_404_html[10] = \r
+/* "/404.html" */\r
+{0x2f, 0x34, 0x30, 0x34, 0x2e, 0x68, 0x74, 0x6d, 0x6c, };\r
+const char http_referer[9] = \r
+/* "Referer:" */\r
+{0x52, 0x65, 0x66, 0x65, 0x72, 0x65, 0x72, 0x3a, };\r
+const char http_header_200[84] = \r
+/* "HTTP/1.0 200 OK\r\nServer: uIP/1.0 http://www.sics.se/~adam/uip/\r\nConnection: close\r\n" */\r
+{0x48, 0x54, 0x54, 0x50, 0x2f, 0x31, 0x2e, 0x30, 0x20, 0x32, 0x30, 0x30, 0x20, 0x4f, 0x4b, 0xd, 0xa, 0x53, 0x65, 0x72, 0x76, 0x65, 0x72, 0x3a, 0x20, 0x75, 0x49, 0x50, 0x2f, 0x31, 0x2e, 0x30, 0x20, 0x68, 0x74, 0x74, 0x70, 0x3a, 0x2f, 0x2f, 0x77, 0x77, 0x77, 0x2e, 0x73, 0x69, 0x63, 0x73, 0x2e, 0x73, 0x65, 0x2f, 0x7e, 0x61, 0x64, 0x61, 0x6d, 0x2f, 0x75, 0x69, 0x70, 0x2f, 0xd, 0xa, 0x43, 0x6f, 0x6e, 0x6e, 0x65, 0x63, 0x74, 0x69, 0x6f, 0x6e, 0x3a, 0x20, 0x63, 0x6c, 0x6f, 0x73, 0x65, 0xd, 0xa, };\r
+const char http_header_404[91] = \r
+/* "HTTP/1.0 404 Not found\r\nServer: uIP/1.0 http://www.sics.se/~adam/uip/\r\nConnection: close\r\n" */\r
+{0x48, 0x54, 0x54, 0x50, 0x2f, 0x31, 0x2e, 0x30, 0x20, 0x34, 0x30, 0x34, 0x20, 0x4e, 0x6f, 0x74, 0x20, 0x66, 0x6f, 0x75, 0x6e, 0x64, 0xd, 0xa, 0x53, 0x65, 0x72, 0x76, 0x65, 0x72, 0x3a, 0x20, 0x75, 0x49, 0x50, 0x2f, 0x31, 0x2e, 0x30, 0x20, 0x68, 0x74, 0x74, 0x70, 0x3a, 0x2f, 0x2f, 0x77, 0x77, 0x77, 0x2e, 0x73, 0x69, 0x63, 0x73, 0x2e, 0x73, 0x65, 0x2f, 0x7e, 0x61, 0x64, 0x61, 0x6d, 0x2f, 0x75, 0x69, 0x70, 0x2f, 0xd, 0xa, 0x43, 0x6f, 0x6e, 0x6e, 0x65, 0x63, 0x74, 0x69, 0x6f, 0x6e, 0x3a, 0x20, 0x63, 0x6c, 0x6f, 0x73, 0x65, 0xd, 0xa, };\r
+const char http_content_type_plain[29] = \r
+/* "Content-type: text/plain\r\n\r\n" */\r
+{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x74, 0x65, 0x78, 0x74, 0x2f, 0x70, 0x6c, 0x61, 0x69, 0x6e, 0xd, 0xa, 0xd, 0xa, };\r
+const char http_content_type_html[28] = \r
+/* "Content-type: text/html\r\n\r\n" */\r
+{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x74, 0x65, 0x78, 0x74, 0x2f, 0x68, 0x74, 0x6d, 0x6c, 0xd, 0xa, 0xd, 0xa, };\r
+const char http_content_type_css [27] = \r
+/* "Content-type: text/css\r\n\r\n" */\r
+{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x74, 0x65, 0x78, 0x74, 0x2f, 0x63, 0x73, 0x73, 0xd, 0xa, 0xd, 0xa, };\r
+const char http_content_type_text[28] = \r
+/* "Content-type: text/text\r\n\r\n" */\r
+{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x74, 0x65, 0x78, 0x74, 0x2f, 0x74, 0x65, 0x78, 0x74, 0xd, 0xa, 0xd, 0xa, };\r
+const char http_content_type_png [28] = \r
+/* "Content-type: image/png\r\n\r\n" */\r
+{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x69, 0x6d, 0x61, 0x67, 0x65, 0x2f, 0x70, 0x6e, 0x67, 0xd, 0xa, 0xd, 0xa, };\r
+const char http_content_type_gif [28] = \r
+/* "Content-type: image/gif\r\n\r\n" */\r
+{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x69, 0x6d, 0x61, 0x67, 0x65, 0x2f, 0x67, 0x69, 0x66, 0xd, 0xa, 0xd, 0xa, };\r
+const char http_content_type_jpg [29] = \r
+/* "Content-type: image/jpeg\r\n\r\n" */\r
+{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x69, 0x6d, 0x61, 0x67, 0x65, 0x2f, 0x6a, 0x70, 0x65, 0x67, 0xd, 0xa, 0xd, 0xa, };\r
+const char http_content_type_binary[43] = \r
+/* "Content-type: application/octet-stream\r\n\r\n" */\r
+{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x61, 0x70, 0x70, 0x6c, 0x69, 0x63, 0x61, 0x74, 0x69, 0x6f, 0x6e, 0x2f, 0x6f, 0x63, 0x74, 0x65, 0x74, 0x2d, 0x73, 0x74, 0x72, 0x65, 0x61, 0x6d, 0xd, 0xa, 0xd, 0xa, };\r
+const char http_html[6] = \r
+/* ".html" */\r
+{0x2e, 0x68, 0x74, 0x6d, 0x6c, };\r
+const char http_shtml[7] = \r
+/* ".shtml" */\r
+{0x2e, 0x73, 0x68, 0x74, 0x6d, 0x6c, };\r
+const char http_htm[5] = \r
+/* ".htm" */\r
+{0x2e, 0x68, 0x74, 0x6d, };\r
+const char http_css[5] = \r
+/* ".css" */\r
+{0x2e, 0x63, 0x73, 0x73, };\r
+const char http_png[5] = \r
+/* ".png" */\r
+{0x2e, 0x70, 0x6e, 0x67, };\r
+const char http_gif[5] = \r
+/* ".gif" */\r
+{0x2e, 0x67, 0x69, 0x66, };\r
+const char http_jpg[5] = \r
+/* ".jpg" */\r
+{0x2e, 0x6a, 0x70, 0x67, };\r
+const char http_text[5] = \r
+/* ".txt" */\r
+{0x2e, 0x74, 0x78, 0x74, };\r
+const char http_txt[5] = \r
+/* ".txt" */\r
+{0x2e, 0x74, 0x78, 0x74, };\r
--- /dev/null
+extern const char http_http[8];\r
+extern const char http_200[5];\r
+extern const char http_301[5];\r
+extern const char http_302[5];\r
+extern const char http_get[5];\r
+extern const char http_10[9];\r
+extern const char http_11[9];\r
+extern const char http_content_type[15];\r
+extern const char http_texthtml[10];\r
+extern const char http_location[11];\r
+extern const char http_host[7];\r
+extern const char http_crnl[3];\r
+extern const char http_index_html[12];\r
+extern const char http_404_html[10];\r
+extern const char http_referer[9];\r
+extern const char http_header_200[84];\r
+extern const char http_header_404[91];\r
+extern const char http_content_type_plain[29];\r
+extern const char http_content_type_html[28];\r
+extern const char http_content_type_css [27];\r
+extern const char http_content_type_text[28];\r
+extern const char http_content_type_png [28];\r
+extern const char http_content_type_gif [28];\r
+extern const char http_content_type_jpg [29];\r
+extern const char http_content_type_binary[43];\r
+extern const char http_html[6];\r
+extern const char http_shtml[7];\r
+extern const char http_htm[5];\r
+extern const char http_css[5];\r
+extern const char http_png[5];\r
+extern const char http_gif[5];\r
+extern const char http_jpg[5];\r
+extern const char http_text[5];\r
+extern const char http_txt[5];\r
--- /dev/null
+/**\r
+ * \addtogroup httpd\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * \file\r
+ * Web server script interface\r
+ * \author\r
+ * Adam Dunkels <adam@sics.se>\r
+ *\r
+ */\r
+\r
+/*\r
+ * Copyright (c) 2001-2006, Adam Dunkels.\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ * 1. Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the\r
+ * documentation and/or other materials provided with the distribution.\r
+ * 3. The name of the author may not be used to endorse or promote\r
+ * products derived from this software without specific prior\r
+ * written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS\r
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\r
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY\r
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE\r
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\r
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\r
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * This file is part of the uIP TCP/IP stack.\r
+ *\r
+ * $Id: httpd-cgi.c,v 1.2 2006/06/11 21:46:37 adam Exp $\r
+ *\r
+ */\r
+\r
+#include "uip.h"\r
+#include "psock.h"\r
+#include "httpd.h"\r
+#include "httpd-cgi.h"\r
+#include "httpd-fs.h"\r
+\r
+#include <stdio.h>\r
+#include <string.h>\r
+\r
+HTTPD_CGI_CALL(file, "file-stats", file_stats);\r
+HTTPD_CGI_CALL(tcp, "tcp-connections", tcp_stats);\r
+HTTPD_CGI_CALL(net, "net-stats", net_stats);\r
+HTTPD_CGI_CALL(rtos, "rtos-stats", rtos_stats );\r
+HTTPD_CGI_CALL(io, "led-io", led_io );\r
+\r
+\r
+static const struct httpd_cgi_call *calls[] = { &file, &tcp, &net, &rtos, &io, NULL };\r
+\r
+/*---------------------------------------------------------------------------*/\r
+static\r
+PT_THREAD(nullfunction(struct httpd_state *s, char *ptr))\r
+{\r
+ PSOCK_BEGIN(&s->sout);\r
+ PSOCK_END(&s->sout);\r
+}\r
+/*---------------------------------------------------------------------------*/\r
+httpd_cgifunction\r
+httpd_cgi(char *name)\r
+{\r
+ const struct httpd_cgi_call **f;\r
+\r
+ /* Find the matching name in the table, return the function. */\r
+ for(f = calls; *f != NULL; ++f) {\r
+ if(strncmp((*f)->name, name, strlen((*f)->name)) == 0) {\r
+ return (*f)->function;\r
+ }\r
+ }\r
+ return nullfunction;\r
+}\r
+/*---------------------------------------------------------------------------*/\r
+static unsigned short\r
+generate_file_stats(void *arg)\r
+{\r
+ char *f = (char *)arg;\r
+ return snprintf((char *)uip_appdata, UIP_APPDATA_SIZE, "%5u", httpd_fs_count(f));\r
+}\r
+/*---------------------------------------------------------------------------*/\r
+static\r
+PT_THREAD(file_stats(struct httpd_state *s, char *ptr))\r
+{\r
+ PSOCK_BEGIN(&s->sout);\r
+\r
+ PSOCK_GENERATOR_SEND(&s->sout, generate_file_stats, strchr(ptr, ' ') + 1);\r
+\r
+ PSOCK_END(&s->sout);\r
+}\r
+/*---------------------------------------------------------------------------*/\r
+static const char closed[] = /* "CLOSED",*/\r
+{0x43, 0x4c, 0x4f, 0x53, 0x45, 0x44, 0};\r
+static const char syn_rcvd[] = /* "SYN-RCVD",*/\r
+{0x53, 0x59, 0x4e, 0x2d, 0x52, 0x43, 0x56,\r
+ 0x44, 0};\r
+static const char syn_sent[] = /* "SYN-SENT",*/\r
+{0x53, 0x59, 0x4e, 0x2d, 0x53, 0x45, 0x4e,\r
+ 0x54, 0};\r
+static const char established[] = /* "ESTABLISHED",*/\r
+{0x45, 0x53, 0x54, 0x41, 0x42, 0x4c, 0x49, 0x53, 0x48,\r
+ 0x45, 0x44, 0};\r
+static const char fin_wait_1[] = /* "FIN-WAIT-1",*/\r
+{0x46, 0x49, 0x4e, 0x2d, 0x57, 0x41, 0x49,\r
+ 0x54, 0x2d, 0x31, 0};\r
+static const char fin_wait_2[] = /* "FIN-WAIT-2",*/\r
+{0x46, 0x49, 0x4e, 0x2d, 0x57, 0x41, 0x49,\r
+ 0x54, 0x2d, 0x32, 0};\r
+static const char closing[] = /* "CLOSING",*/\r
+{0x43, 0x4c, 0x4f, 0x53, 0x49,\r
+ 0x4e, 0x47, 0};\r
+static const char time_wait[] = /* "TIME-WAIT,"*/\r
+{0x54, 0x49, 0x4d, 0x45, 0x2d, 0x57, 0x41,\r
+ 0x49, 0x54, 0};\r
+static const char last_ack[] = /* "LAST-ACK"*/\r
+{0x4c, 0x41, 0x53, 0x54, 0x2d, 0x41, 0x43,\r
+ 0x4b, 0};\r
+\r
+static const char *states[] = {\r
+ closed,\r
+ syn_rcvd,\r
+ syn_sent,\r
+ established,\r
+ fin_wait_1,\r
+ fin_wait_2,\r
+ closing,\r
+ time_wait,\r
+ last_ack};\r
+\r
+\r
+static unsigned short\r
+generate_tcp_stats(void *arg)\r
+{\r
+ struct uip_conn *conn;\r
+ struct httpd_state *s = (struct httpd_state *)arg;\r
+\r
+ conn = &uip_conns[s->count];\r
+ return snprintf((char *)uip_appdata, UIP_APPDATA_SIZE,\r
+ "<tr><td>%d</td><td>%u.%u.%u.%u:%u</td><td>%s</td><td>%u</td><td>%u</td><td>%c %c</td></tr>\r\n",\r
+ htons(conn->lport),\r
+ htons(conn->ripaddr[0]) >> 8,\r
+ htons(conn->ripaddr[0]) & 0xff,\r
+ htons(conn->ripaddr[1]) >> 8,\r
+ htons(conn->ripaddr[1]) & 0xff,\r
+ htons(conn->rport),\r
+ states[conn->tcpstateflags & UIP_TS_MASK],\r
+ conn->nrtx,\r
+ conn->timer,\r
+ (uip_outstanding(conn))? '*':' ',\r
+ (uip_stopped(conn))? '!':' ');\r
+}\r
+/*---------------------------------------------------------------------------*/\r
+static\r
+PT_THREAD(tcp_stats(struct httpd_state *s, char *ptr))\r
+{\r
+\r
+ PSOCK_BEGIN(&s->sout);\r
+\r
+ for(s->count = 0; s->count < UIP_CONNS; ++s->count) {\r
+ if((uip_conns[s->count].tcpstateflags & UIP_TS_MASK) != UIP_CLOSED) {\r
+ PSOCK_GENERATOR_SEND(&s->sout, generate_tcp_stats, s);\r
+ }\r
+ }\r
+\r
+ PSOCK_END(&s->sout);\r
+}\r
+/*---------------------------------------------------------------------------*/\r
+static unsigned short\r
+generate_net_stats(void *arg)\r
+{\r
+ struct httpd_state *s = (struct httpd_state *)arg;\r
+ return snprintf((char *)uip_appdata, UIP_APPDATA_SIZE,\r
+ "%5u\n", ((uip_stats_t *)&uip_stat)[s->count]);\r
+}\r
+\r
+static\r
+PT_THREAD(net_stats(struct httpd_state *s, char *ptr))\r
+{\r
+ PSOCK_BEGIN(&s->sout);\r
+\r
+#if UIP_STATISTICS\r
+\r
+ for(s->count = 0; s->count < sizeof(uip_stat) / sizeof(uip_stats_t);\r
+ ++s->count) {\r
+ PSOCK_GENERATOR_SEND(&s->sout, generate_net_stats, s);\r
+ }\r
+\r
+#endif /* UIP_STATISTICS */\r
+\r
+ PSOCK_END(&s->sout);\r
+}\r
+/*---------------------------------------------------------------------------*/\r
+\r
+extern void vTaskList( signed char *pcWriteBuffer );\r
+static char cCountBuf[ 32 ];\r
+long lRefreshCount = 0;\r
+static unsigned short\r
+generate_rtos_stats(void *arg)\r
+{\r
+ lRefreshCount++;\r
+ sprintf( cCountBuf, "<p><br>Refresh count = %d", lRefreshCount );\r
+ vTaskList( uip_appdata );\r
+ strcat( uip_appdata, cCountBuf );\r
+\r
+ return strlen( uip_appdata );\r
+}\r
+/*---------------------------------------------------------------------------*/\r
+\r
+\r
+static\r
+PT_THREAD(rtos_stats(struct httpd_state *s, char *ptr))\r
+{\r
+ PSOCK_BEGIN(&s->sout);\r
+ PSOCK_GENERATOR_SEND(&s->sout, generate_rtos_stats, NULL);\r
+ PSOCK_END(&s->sout);\r
+}\r
+/*---------------------------------------------------------------------------*/\r
+\r
+char *pcStatus;\r
+extern unsigned long uxParTestGetLED( unsigned long uxLED );\r
+\r
+static unsigned short generate_io_state( void *arg )\r
+{\r
+ if( uxParTestGetLED( 0 ) )\r
+ {\r
+ pcStatus = "checked";\r
+ }\r
+ else\r
+ {\r
+ pcStatus = "";\r
+ }\r
+\r
+ sprintf( uip_appdata,\r
+ "<input type=\"checkbox\" name=\"LED0\" value=\"1\" %s>LED"\\r
+ "<p>"\\r
+ "<input type=\"text\" name=\"LCD\" value=\"Enter LCD text\" size=\"16\">",\r
+ pcStatus );\r
+\r
+ return strlen( uip_appdata );\r
+}\r
+/*---------------------------------------------------------------------------*/\r
+\r
+static PT_THREAD(led_io(struct httpd_state *s, char *ptr))\r
+{\r
+ PSOCK_BEGIN(&s->sout);\r
+ PSOCK_GENERATOR_SEND(&s->sout, generate_io_state, NULL);\r
+ PSOCK_END(&s->sout);\r
+}\r
+\r
+/** @} */\r
+\r
+\r
+\r
+\r
+\r
+\r
--- /dev/null
+/**\r
+ * \addtogroup httpd\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * \file\r
+ * Web server script interface header file\r
+ * \author\r
+ * Adam Dunkels <adam@sics.se>\r
+ *\r
+ */\r
+\r
+\r
+\r
+/*\r
+ * Copyright (c) 2001, Adam Dunkels.\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ * 1. Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the\r
+ * documentation and/or other materials provided with the distribution.\r
+ * 3. The name of the author may not be used to endorse or promote\r
+ * products derived from this software without specific prior\r
+ * written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS\r
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\r
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY\r
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE\r
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\r
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\r
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * This file is part of the uIP TCP/IP stack.\r
+ *\r
+ * $Id: httpd-cgi.h,v 1.2 2006/06/11 21:46:38 adam Exp $\r
+ *\r
+ */\r
+\r
+#ifndef __HTTPD_CGI_H__\r
+#define __HTTPD_CGI_H__\r
+\r
+#include "psock.h"\r
+#include "httpd.h"\r
+\r
+typedef PT_THREAD((* httpd_cgifunction)(struct httpd_state *, char *));\r
+\r
+httpd_cgifunction httpd_cgi(char *name);\r
+\r
+struct httpd_cgi_call {\r
+ const char *name;\r
+ const httpd_cgifunction function;\r
+};\r
+\r
+/**\r
+ * \brief HTTPD CGI function declaration\r
+ * \param name The C variable name of the function\r
+ * \param str The string name of the function, used in the script file\r
+ * \param function A pointer to the function that implements it\r
+ *\r
+ * This macro is used for declaring a HTTPD CGI\r
+ * function. This function is then added to the list of\r
+ * HTTPD CGI functions with the httpd_cgi_add() function.\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define HTTPD_CGI_CALL(name, str, function) \\r
+static PT_THREAD(function(struct httpd_state *, char *)); \\r
+static const struct httpd_cgi_call name = {str, function}\r
+\r
+void httpd_cgi_init(void);\r
+#endif /* __HTTPD_CGI_H__ */\r
+\r
+/** @} */\r
--- /dev/null
+/*\r
+ * Copyright (c) 2001, Swedish Institute of Computer Science.\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ * 1. Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the\r
+ * documentation and/or other materials provided with the distribution.\r
+ * 3. Neither the name of the Institute nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND\r
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\r
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\r
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\r
+ * SUCH DAMAGE.\r
+ *\r
+ * This file is part of the lwIP TCP/IP stack.\r
+ *\r
+ * Author: Adam Dunkels <adam@sics.se>\r
+ *\r
+ * $Id: httpd-fs.c,v 1.1 2006/06/07 09:13:08 adam Exp $\r
+ */\r
+\r
+#include "httpd.h"\r
+#include "httpd-fs.h"\r
+#include "httpd-fsdata.h"\r
+\r
+#ifndef NULL\r
+#define NULL 0\r
+#endif /* NULL */\r
+\r
+#include "httpd-fsdata.c"\r
+\r
+#if HTTPD_FS_STATISTICS\r
+static u16_t count[HTTPD_FS_NUMFILES];\r
+#endif /* HTTPD_FS_STATISTICS */\r
+\r
+/*-----------------------------------------------------------------------------------*/\r
+static u8_t\r
+httpd_fs_strcmp(const char *str1, const char *str2)\r
+{\r
+ u8_t i;\r
+ i = 0;\r
+ loop:\r
+\r
+ if(str2[i] == 0 ||\r
+ str1[i] == '\r' ||\r
+ str1[i] == '\n') {\r
+ return 0;\r
+ }\r
+\r
+ if(str1[i] != str2[i]) {\r
+ return 1;\r
+ }\r
+\r
+\r
+ ++i;\r
+ goto loop;\r
+}\r
+/*-----------------------------------------------------------------------------------*/\r
+int\r
+httpd_fs_open(const char *name, struct httpd_fs_file *file)\r
+{\r
+#if HTTPD_FS_STATISTICS\r
+ u16_t i = 0;\r
+#endif /* HTTPD_FS_STATISTICS */\r
+ struct httpd_fsdata_file_noconst *f;\r
+\r
+ for(f = (struct httpd_fsdata_file_noconst *)HTTPD_FS_ROOT;\r
+ f != NULL;\r
+ f = (struct httpd_fsdata_file_noconst *)f->next) {\r
+\r
+ if(httpd_fs_strcmp(name, f->name) == 0) {\r
+ file->data = f->data;\r
+ file->len = f->len;\r
+#if HTTPD_FS_STATISTICS\r
+ ++count[i];\r
+#endif /* HTTPD_FS_STATISTICS */\r
+ return 1;\r
+ }\r
+#if HTTPD_FS_STATISTICS\r
+ ++i;\r
+#endif /* HTTPD_FS_STATISTICS */\r
+\r
+ }\r
+ return 0;\r
+}\r
+/*-----------------------------------------------------------------------------------*/\r
+void\r
+httpd_fs_init(void)\r
+{\r
+#if HTTPD_FS_STATISTICS\r
+ u16_t i;\r
+ for(i = 0; i < HTTPD_FS_NUMFILES; i++) {\r
+ count[i] = 0;\r
+ }\r
+#endif /* HTTPD_FS_STATISTICS */\r
+}\r
+/*-----------------------------------------------------------------------------------*/\r
+#if HTTPD_FS_STATISTICS\r
+u16_t httpd_fs_count\r
+(char *name)\r
+{\r
+ struct httpd_fsdata_file_noconst *f;\r
+ u16_t i;\r
+\r
+ i = 0;\r
+ for(f = (struct httpd_fsdata_file_noconst *)HTTPD_FS_ROOT;\r
+ f != NULL;\r
+ f = (struct httpd_fsdata_file_noconst *)f->next) {\r
+\r
+ if(httpd_fs_strcmp(name, f->name) == 0) {\r
+ return count[i];\r
+ }\r
+ ++i;\r
+ }\r
+ return 0;\r
+}\r
+#endif /* HTTPD_FS_STATISTICS */\r
+/*-----------------------------------------------------------------------------------*/\r
--- /dev/null
+/*\r
+ * Copyright (c) 2001, Swedish Institute of Computer Science.\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ * 1. Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the\r
+ * documentation and/or other materials provided with the distribution.\r
+ * 3. Neither the name of the Institute nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND\r
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\r
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\r
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\r
+ * SUCH DAMAGE.\r
+ *\r
+ * This file is part of the lwIP TCP/IP stack.\r
+ *\r
+ * Author: Adam Dunkels <adam@sics.se>\r
+ *\r
+ * $Id: httpd-fs.h,v 1.1 2006/06/07 09:13:08 adam Exp $\r
+ */\r
+#ifndef __HTTPD_FS_H__\r
+#define __HTTPD_FS_H__\r
+\r
+#define HTTPD_FS_STATISTICS 1\r
+\r
+struct httpd_fs_file {\r
+ char *data;\r
+ int len;\r
+};\r
+\r
+/* file must be allocated by caller and will be filled in\r
+ by the function. */\r
+int httpd_fs_open(const char *name, struct httpd_fs_file *file);\r
+\r
+#ifdef HTTPD_FS_STATISTICS\r
+#if HTTPD_FS_STATISTICS == 1\r
+u16_t httpd_fs_count(char *name);\r
+#endif /* HTTPD_FS_STATISTICS */\r
+#endif /* HTTPD_FS_STATISTICS */\r
+\r
+void httpd_fs_init(void);\r
+\r
+#endif /* __HTTPD_FS_H__ */\r
--- /dev/null
+<html>\r
+ <body bgcolor="white">\r
+ <center>\r
+ <h1>404 - file not found</h1>\r
+ <h3>Go <a href="/">here</a> instead.</h3>\r
+ </center>\r
+ </body>\r
+</html>
\ No newline at end of file
--- /dev/null
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">\r
+<html>\r
+ <head>\r
+ <title>FreeRTOS.org uIP WEB server demo</title>\r
+ </head>\r
+ <BODY onLoad="window.setTimeout("location.href='index.shtml'",100)"bgcolor="#CCCCff">\r
+<font face="arial">\r
+Loading index.shtml. Click <a href="index.shtml">here</a> if not automatically redirected.\r
+</font>\r
+</font>\r
+</body>\r
+</html>\r
+\r
--- /dev/null
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">\r
+<html>\r
+ <head>\r
+ <title>FreeRTOS.org uIP WEB server demo</title>\r
+ </head>\r
+ <BODY onLoad="window.setTimeout("location.href='index.shtml'",2000)"bgcolor="#CCCCff">\r
+<font face="arial">\r
+<a href="index.shtml">RTOS Stats</a> <b>|</b> <a href="stats.shtml">TCP Stats</a> <b>|</b> <a href="tcp.shtml">Connections</a> <b>|</b> <a href="http://www.freertos.org/">FreeRTOS.org Homepage</a> <b>|</b> <a href="io.shtml">IO</a>\r
+<br><p>\r
+<hr>\r
+<br><p>\r
+<h2>Task statistics</h2>\r
+Page will refresh every 2 seconds.<p>\r
+<font face="courier"><pre>Task State Priority Stack #<br>************************************************<br>\r
+%! rtos-stats\r
+</pre></font>\r
+</font>\r
+</body>\r
+</html>\r
+\r
--- /dev/null
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">\r
+<html>\r
+ <head>\r
+ <title>FreeRTOS.org uIP WEB server demo</title>\r
+ </head>\r
+ <BODY bgcolor="#CCCCff">\r
+<font face="arial">\r
+<a href="index.shtml">RTOS Stats</a> <b>|</b> <a href="stats.shtml">TCP Stats</a> <b>|</b> <a href="tcp.shtml">Connections</a> <b>|</b> <a href="http://www.freertos.org/">FreeRTOS.org Homepage</a> <b>|</b> <a href="io.shtml">IO</a>\r
+<br><p>\r
+<hr>\r
+<b>LED and LCD IO</b><br>\r
+\r
+<p>\r
+\r
+Use the check box to turn on or off the LED, enter text to display on the OLED display, then click "Update IO".\r
+\r
+\r
+<p>\r
+<form name="aForm" action="/io.shtml" method="get">\r
+%! led-io\r
+<p>\r
+<input type="submit" value="Update IO">\r
+</form>\r
+<br><p>\r
+</font>\r
+</body>\r
+</html>\r
+\r
--- /dev/null
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">\r
+<html>\r
+ <head>\r
+ <title>FreeRTOS.org uIP WEB server demo</title>\r
+ </head>\r
+ <BODY bgcolor="#CCCCff">\r
+<font face="arial">\r
+<a href="index.shtml">RTOS Stats</a> <b>|</b> <a href="stats.shtml">TCP Stats</a> <b>|</b> <a href="tcp.shtml">Connections</a> <b>|</b> <a href="http://www.freertos.org/">FreeRTOS.org Homepage</a> <b>|</b> <a href="io.shtml">IO</a>\r
+<br><p>\r
+<hr>\r
+<br><p>\r
+<h2>Network statistics</h2>\r
+<table width="300" border="0">\r
+<tr><td align="left"><font face="courier"><pre>\r
+IP Packets dropped\r
+ Packets received\r
+ Packets sent\r
+IP errors IP version/header length\r
+ IP length, high byte\r
+ IP length, low byte\r
+ IP fragments\r
+ Header checksum\r
+ Wrong protocol\r
+ICMP Packets dropped\r
+ Packets received\r
+ Packets sent\r
+ Type errors\r
+TCP Packets dropped\r
+ Packets received\r
+ Packets sent\r
+ Checksum errors\r
+ Data packets without ACKs\r
+ Resets\r
+ Retransmissions\r
+ No connection avaliable\r
+ Connection attempts to closed ports\r
+</pre></font></td><td><pre>%! net-stats\r
+</pre></table>\r
+</font>\r
+</body>\r
+</html>\r
--- /dev/null
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">\r
+<html>\r
+ <head>\r
+ <title>FreeRTOS.org uIP WEB server demo</title>\r
+ </head>\r
+ <BODY bgcolor="#CCCCff">\r
+<font face="arial">\r
+<a href="index.shtml">RTOS Stats</a> <b>|</b> <a href="stats.shtml">TCP Stats</a> <b>|</b> <a href="tcp.shtml">Connections</a> <b>|</b> <a href="http://www.freertos.org/">FreeRTOS.org Homepage</a> <b>|</b> <a href="io.shtml">IO</a>\r
+<br><p>\r
+<hr>\r
+<br>\r
+<h2>Network connections</h2>\r
+<p>\r
+<table>\r
+<tr><th>Local</th><th>Remote</th><th>State</th><th>Retransmissions</th><th>Timer</th><th>Flags</th></tr>\r
+%! tcp-connections\r
+</pre></font>\r
+</font>\r
+</body>\r
+</html>\r
+\r
--- /dev/null
+static const unsigned char data_404_html[] = {\r
+ /* /404.html */\r
+ 0x2f, 0x34, 0x30, 0x34, 0x2e, 0x68, 0x74, 0x6d, 0x6c, 0,\r
+ 0x3c, 0x68, 0x74, 0x6d, 0x6c, 0x3e, 0xd, 0xa, 0x20, 0x20, \r
+ 0x3c, 0x62, 0x6f, 0x64, 0x79, 0x20, 0x62, 0x67, 0x63, 0x6f, \r
+ 0x6c, 0x6f, 0x72, 0x3d, 0x22, 0x77, 0x68, 0x69, 0x74, 0x65, \r
+ 0x22, 0x3e, 0xd, 0xa, 0x20, 0x20, 0x20, 0x20, 0x3c, 0x63, \r
+ 0x65, 0x6e, 0x74, 0x65, 0x72, 0x3e, 0xd, 0xa, 0x20, 0x20, \r
+ 0x20, 0x20, 0x20, 0x20, 0x3c, 0x68, 0x31, 0x3e, 0x34, 0x30, \r
+ 0x34, 0x20, 0x2d, 0x20, 0x66, 0x69, 0x6c, 0x65, 0x20, 0x6e, \r
+ 0x6f, 0x74, 0x20, 0x66, 0x6f, 0x75, 0x6e, 0x64, 0x3c, 0x2f, \r
+ 0x68, 0x31, 0x3e, 0xd, 0xa, 0x20, 0x20, 0x20, 0x20, 0x20, \r
+ 0x20, 0x3c, 0x68, 0x33, 0x3e, 0x47, 0x6f, 0x20, 0x3c, 0x61, \r
+ 0x20, 0x68, 0x72, 0x65, 0x66, 0x3d, 0x22, 0x2f, 0x22, 0x3e, \r
+ 0x68, 0x65, 0x72, 0x65, 0x3c, 0x2f, 0x61, 0x3e, 0x20, 0x69, \r
+ 0x6e, 0x73, 0x74, 0x65, 0x61, 0x64, 0x2e, 0x3c, 0x2f, 0x68, \r
+ 0x33, 0x3e, 0xd, 0xa, 0x20, 0x20, 0x20, 0x20, 0x3c, 0x2f, \r
+ 0x63, 0x65, 0x6e, 0x74, 0x65, 0x72, 0x3e, 0xd, 0xa, 0x20, \r
+ 0x20, 0x3c, 0x2f, 0x62, 0x6f, 0x64, 0x79, 0x3e, 0xd, 0xa, \r
+ 0x3c, 0x2f, 0x68, 0x74, 0x6d, 0x6c, 0x3e, 0};\r
+\r
+static const unsigned char data_index_html[] = {\r
+ /* /index.html */\r
+ 0x2f, 0x69, 0x6e, 0x64, 0x65, 0x78, 0x2e, 0x68, 0x74, 0x6d, 0x6c, 0,\r
+ 0x3c, 0x21, 0x44, 0x4f, 0x43, 0x54, 0x59, 0x50, 0x45, 0x20, \r
+ 0x48, 0x54, 0x4d, 0x4c, 0x20, 0x50, 0x55, 0x42, 0x4c, 0x49, \r
+ 0x43, 0x20, 0x22, 0x2d, 0x2f, 0x2f, 0x57, 0x33, 0x43, 0x2f, \r
+ 0x2f, 0x44, 0x54, 0x44, 0x20, 0x48, 0x54, 0x4d, 0x4c, 0x20, \r
+ 0x34, 0x2e, 0x30, 0x31, 0x20, 0x54, 0x72, 0x61, 0x6e, 0x73, \r
+ 0x69, 0x74, 0x69, 0x6f, 0x6e, 0x61, 0x6c, 0x2f, 0x2f, 0x45, \r
+ 0x4e, 0x22, 0x20, 0x22, 0x68, 0x74, 0x74, 0x70, 0x3a, 0x2f, \r
+ 0x2f, 0x77, 0x77, 0x77, 0x2e, 0x77, 0x33, 0x2e, 0x6f, 0x72, \r
+ 0x67, 0x2f, 0x54, 0x52, 0x2f, 0x68, 0x74, 0x6d, 0x6c, 0x34, \r
+ 0x2f, 0x6c, 0x6f, 0x6f, 0x73, 0x65, 0x2e, 0x64, 0x74, 0x64, \r
+ 0x22, 0x3e, 0xd, 0xa, 0x3c, 0x68, 0x74, 0x6d, 0x6c, 0x3e, \r
+ 0xd, 0xa, 0x20, 0x20, 0x3c, 0x68, 0x65, 0x61, 0x64, 0x3e, \r
+ 0xd, 0xa, 0x20, 0x20, 0x20, 0x20, 0x3c, 0x74, 0x69, 0x74, \r
+ 0x6c, 0x65, 0x3e, 0x46, 0x72, 0x65, 0x65, 0x52, 0x54, 0x4f, \r
+ 0x53, 0x2e, 0x6f, 0x72, 0x67, 0x20, 0x75, 0x49, 0x50, 0x20, \r
+ 0x57, 0x45, 0x42, 0x20, 0x73, 0x65, 0x72, 0x76, 0x65, 0x72, \r
+ 0x20, 0x64, 0x65, 0x6d, 0x6f, 0x3c, 0x2f, 0x74, 0x69, 0x74, \r
+ 0x6c, 0x65, 0x3e, 0xd, 0xa, 0x20, 0x20, 0x3c, 0x2f, 0x68, \r
+ 0x65, 0x61, 0x64, 0x3e, 0xd, 0xa, 0x20, 0x20, 0x3c, 0x42, \r
+ 0x4f, 0x44, 0x59, 0x20, 0x6f, 0x6e, 0x4c, 0x6f, 0x61, 0x64, \r
+ 0x3d, 0x22, 0x77, 0x69, 0x6e, 0x64, 0x6f, 0x77, 0x2e, 0x73, \r
+ 0x65, 0x74, 0x54, 0x69, 0x6d, 0x65, 0x6f, 0x75, 0x74, 0x28, \r
+ 0x26, 0x71, 0x75, 0x6f, 0x74, 0x3b, 0x6c, 0x6f, 0x63, 0x61, \r
+ 0x74, 0x69, 0x6f, 0x6e, 0x2e, 0x68, 0x72, 0x65, 0x66, 0x3d, \r
+ 0x27, 0x69, 0x6e, 0x64, 0x65, 0x78, 0x2e, 0x73, 0x68, 0x74, \r
+ 0x6d, 0x6c, 0x27, 0x26, 0x71, 0x75, 0x6f, 0x74, 0x3b, 0x2c, \r
+ 0x31, 0x30, 0x30, 0x29, 0x22, 0x62, 0x67, 0x63, 0x6f, 0x6c, \r
+ 0x6f, 0x72, 0x3d, 0x22, 0x23, 0x43, 0x43, 0x43, 0x43, 0x66, \r
+ 0x66, 0x22, 0x3e, 0xd, 0xa, 0x3c, 0x66, 0x6f, 0x6e, 0x74, \r
+ 0x20, 0x66, 0x61, 0x63, 0x65, 0x3d, 0x22, 0x61, 0x72, 0x69, \r
+ 0x61, 0x6c, 0x22, 0x3e, 0xd, 0xa, 0x4c, 0x6f, 0x61, 0x64, \r
+ 0x69, 0x6e, 0x67, 0x20, 0x69, 0x6e, 0x64, 0x65, 0x78, 0x2e, \r
+ 0x73, 0x68, 0x74, 0x6d, 0x6c, 0x2e, 0x20, 0x20, 0x43, 0x6c, \r
+ 0x69, 0x63, 0x6b, 0x20, 0x3c, 0x61, 0x20, 0x68, 0x72, 0x65, \r
+ 0x66, 0x3d, 0x22, 0x69, 0x6e, 0x64, 0x65, 0x78, 0x2e, 0x73, \r
+ 0x68, 0x74, 0x6d, 0x6c, 0x22, 0x3e, 0x68, 0x65, 0x72, 0x65, \r
+ 0x3c, 0x2f, 0x61, 0x3e, 0x20, 0x69, 0x66, 0x20, 0x6e, 0x6f, \r
+ 0x74, 0x20, 0x61, 0x75, 0x74, 0x6f, 0x6d, 0x61, 0x74, 0x69, \r
+ 0x63, 0x61, 0x6c, 0x6c, 0x79, 0x20, 0x72, 0x65, 0x64, 0x69, \r
+ 0x72, 0x65, 0x63, 0x74, 0x65, 0x64, 0x2e, 0xd, 0xa, 0x3c, \r
+ 0x2f, 0x66, 0x6f, 0x6e, 0x74, 0x3e, 0xd, 0xa, 0x3c, 0x2f, \r
+ 0x66, 0x6f, 0x6e, 0x74, 0x3e, 0xd, 0xa, 0x3c, 0x2f, 0x62, \r
+ 0x6f, 0x64, 0x79, 0x3e, 0xd, 0xa, 0x3c, 0x2f, 0x68, 0x74, \r
+ 0x6d, 0x6c, 0x3e, 0xd, 0xa, 0xd, 0xa, 0};\r
+\r
+static const unsigned char data_index_shtml[] = {\r
+ /* /index.shtml */\r
+ 0x2f, 0x69, 0x6e, 0x64, 0x65, 0x78, 0x2e, 0x73, 0x68, 0x74, 0x6d, 0x6c, 0,\r
+ 0x3c, 0x21, 0x44, 0x4f, 0x43, 0x54, 0x59, 0x50, 0x45, 0x20, \r
+ 0x48, 0x54, 0x4d, 0x4c, 0x20, 0x50, 0x55, 0x42, 0x4c, 0x49, \r
+ 0x43, 0x20, 0x22, 0x2d, 0x2f, 0x2f, 0x57, 0x33, 0x43, 0x2f, \r
+ 0x2f, 0x44, 0x54, 0x44, 0x20, 0x48, 0x54, 0x4d, 0x4c, 0x20, \r
+ 0x34, 0x2e, 0x30, 0x31, 0x20, 0x54, 0x72, 0x61, 0x6e, 0x73, \r
+ 0x69, 0x74, 0x69, 0x6f, 0x6e, 0x61, 0x6c, 0x2f, 0x2f, 0x45, \r
+ 0x4e, 0x22, 0x20, 0x22, 0x68, 0x74, 0x74, 0x70, 0x3a, 0x2f, \r
+ 0x2f, 0x77, 0x77, 0x77, 0x2e, 0x77, 0x33, 0x2e, 0x6f, 0x72, \r
+ 0x67, 0x2f, 0x54, 0x52, 0x2f, 0x68, 0x74, 0x6d, 0x6c, 0x34, \r
+ 0x2f, 0x6c, 0x6f, 0x6f, 0x73, 0x65, 0x2e, 0x64, 0x74, 0x64, \r
+ 0x22, 0x3e, 0xd, 0xa, 0x3c, 0x68, 0x74, 0x6d, 0x6c, 0x3e, \r
+ 0xd, 0xa, 0x20, 0x20, 0x3c, 0x68, 0x65, 0x61, 0x64, 0x3e, \r
+ 0xd, 0xa, 0x20, 0x20, 0x20, 0x20, 0x3c, 0x74, 0x69, 0x74, \r
+ 0x6c, 0x65, 0x3e, 0x46, 0x72, 0x65, 0x65, 0x52, 0x54, 0x4f, \r
+ 0x53, 0x2e, 0x6f, 0x72, 0x67, 0x20, 0x75, 0x49, 0x50, 0x20, \r
+ 0x57, 0x45, 0x42, 0x20, 0x73, 0x65, 0x72, 0x76, 0x65, 0x72, \r
+ 0x20, 0x64, 0x65, 0x6d, 0x6f, 0x3c, 0x2f, 0x74, 0x69, 0x74, \r
+ 0x6c, 0x65, 0x3e, 0xd, 0xa, 0x20, 0x20, 0x3c, 0x2f, 0x68, \r
+ 0x65, 0x61, 0x64, 0x3e, 0xd, 0xa, 0x20, 0x20, 0x3c, 0x42, \r
+ 0x4f, 0x44, 0x59, 0x20, 0x6f, 0x6e, 0x4c, 0x6f, 0x61, 0x64, \r
+ 0x3d, 0x22, 0x77, 0x69, 0x6e, 0x64, 0x6f, 0x77, 0x2e, 0x73, \r
+ 0x65, 0x74, 0x54, 0x69, 0x6d, 0x65, 0x6f, 0x75, 0x74, 0x28, \r
+ 0x26, 0x71, 0x75, 0x6f, 0x74, 0x3b, 0x6c, 0x6f, 0x63, 0x61, \r
+ 0x74, 0x69, 0x6f, 0x6e, 0x2e, 0x68, 0x72, 0x65, 0x66, 0x3d, \r
+ 0x27, 0x69, 0x6e, 0x64, 0x65, 0x78, 0x2e, 0x73, 0x68, 0x74, \r
+ 0x6d, 0x6c, 0x27, 0x26, 0x71, 0x75, 0x6f, 0x74, 0x3b, 0x2c, \r
+ 0x32, 0x30, 0x30, 0x30, 0x29, 0x22, 0x62, 0x67, 0x63, 0x6f, \r
+ 0x6c, 0x6f, 0x72, 0x3d, 0x22, 0x23, 0x43, 0x43, 0x43, 0x43, \r
+ 0x66, 0x66, 0x22, 0x3e, 0xd, 0xa, 0x3c, 0x66, 0x6f, 0x6e, \r
+ 0x74, 0x20, 0x66, 0x61, 0x63, 0x65, 0x3d, 0x22, 0x61, 0x72, \r
+ 0x69, 0x61, 0x6c, 0x22, 0x3e, 0xd, 0xa, 0x3c, 0x61, 0x20, \r
+ 0x68, 0x72, 0x65, 0x66, 0x3d, 0x22, 0x69, 0x6e, 0x64, 0x65, \r
+ 0x78, 0x2e, 0x73, 0x68, 0x74, 0x6d, 0x6c, 0x22, 0x3e, 0x52, \r
+ 0x54, 0x4f, 0x53, 0x20, 0x53, 0x74, 0x61, 0x74, 0x73, 0x3c, \r
+ 0x2f, 0x61, 0x3e, 0x20, 0x3c, 0x62, 0x3e, 0x7c, 0x3c, 0x2f, \r
+ 0x62, 0x3e, 0x20, 0x3c, 0x61, 0x20, 0x68, 0x72, 0x65, 0x66, \r
+ 0x3d, 0x22, 0x73, 0x74, 0x61, 0x74, 0x73, 0x2e, 0x73, 0x68, \r
+ 0x74, 0x6d, 0x6c, 0x22, 0x3e, 0x54, 0x43, 0x50, 0x20, 0x53, \r
+ 0x74, 0x61, 0x74, 0x73, 0x3c, 0x2f, 0x61, 0x3e, 0x20, 0x3c, \r
+ 0x62, 0x3e, 0x7c, 0x3c, 0x2f, 0x62, 0x3e, 0x20, 0x3c, 0x61, \r
+ 0x20, 0x68, 0x72, 0x65, 0x66, 0x3d, 0x22, 0x74, 0x63, 0x70, \r
+ 0x2e, 0x73, 0x68, 0x74, 0x6d, 0x6c, 0x22, 0x3e, 0x43, 0x6f, \r
+ 0x6e, 0x6e, 0x65, 0x63, 0x74, 0x69, 0x6f, 0x6e, 0x73, 0x3c, \r
+ 0x2f, 0x61, 0x3e, 0x20, 0x3c, 0x62, 0x3e, 0x7c, 0x3c, 0x2f, \r
+ 0x62, 0x3e, 0x20, 0x3c, 0x61, 0x20, 0x68, 0x72, 0x65, 0x66, \r
+ 0x3d, 0x22, 0x68, 0x74, 0x74, 0x70, 0x3a, 0x2f, 0x2f, 0x77, \r
+ 0x77, 0x77, 0x2e, 0x66, 0x72, 0x65, 0x65, 0x72, 0x74, 0x6f, \r
+ 0x73, 0x2e, 0x6f, 0x72, 0x67, 0x2f, 0x22, 0x3e, 0x46, 0x72, \r
+ 0x65, 0x65, 0x52, 0x54, 0x4f, 0x53, 0x2e, 0x6f, 0x72, 0x67, \r
+ 0x20, 0x48, 0x6f, 0x6d, 0x65, 0x70, 0x61, 0x67, 0x65, 0x3c, \r
+ 0x2f, 0x61, 0x3e, 0x20, 0x3c, 0x62, 0x3e, 0x7c, 0x3c, 0x2f, \r
+ 0x62, 0x3e, 0x20, 0x3c, 0x61, 0x20, 0x68, 0x72, 0x65, 0x66, \r
+ 0x3d, 0x22, 0x69, 0x6f, 0x2e, 0x73, 0x68, 0x74, 0x6d, 0x6c, \r
+ 0x22, 0x3e, 0x49, 0x4f, 0x3c, 0x2f, 0x61, 0x3e, 0xd, 0xa, \r
+ 0x3c, 0x62, 0x72, 0x3e, 0x3c, 0x70, 0x3e, 0xd, 0xa, 0x3c, \r
+ 0x68, 0x72, 0x3e, 0xd, 0xa, 0x3c, 0x62, 0x72, 0x3e, 0x3c, \r
+ 0x70, 0x3e, 0xd, 0xa, 0x3c, 0x68, 0x32, 0x3e, 0x54, 0x61, \r
+ 0x73, 0x6b, 0x20, 0x73, 0x74, 0x61, 0x74, 0x69, 0x73, 0x74, \r
+ 0x69, 0x63, 0x73, 0x3c, 0x2f, 0x68, 0x32, 0x3e, 0xd, 0xa, \r
+ 0x50, 0x61, 0x67, 0x65, 0x20, 0x77, 0x69, 0x6c, 0x6c, 0x20, \r
+ 0x72, 0x65, 0x66, 0x72, 0x65, 0x73, 0x68, 0x20, 0x65, 0x76, \r
+ 0x65, 0x72, 0x79, 0x20, 0x32, 0x20, 0x73, 0x65, 0x63, 0x6f, \r
+ 0x6e, 0x64, 0x73, 0x2e, 0x3c, 0x70, 0x3e, 0xd, 0xa, 0x3c, \r
+ 0x66, 0x6f, 0x6e, 0x74, 0x20, 0x66, 0x61, 0x63, 0x65, 0x3d, \r
+ 0x22, 0x63, 0x6f, 0x75, 0x72, 0x69, 0x65, 0x72, 0x22, 0x3e, \r
+ 0x3c, 0x70, 0x72, 0x65, 0x3e, 0x54, 0x61, 0x73, 0x6b, 0x20, \r
+ 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x53, \r
+ 0x74, 0x61, 0x74, 0x65, 0x20, 0x20, 0x50, 0x72, 0x69, 0x6f, \r
+ 0x72, 0x69, 0x74, 0x79, 0x20, 0x20, 0x53, 0x74, 0x61, 0x63, \r
+ 0x6b, 0x9, 0x23, 0x3c, 0x62, 0x72, 0x3e, 0x2a, 0x2a, 0x2a, \r
+ 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, \r
+ 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, \r
+ 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, \r
+ 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, \r
+ 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x3c, 0x62, 0x72, 0x3e, 0xd, \r
+ 0xa, 0x25, 0x21, 0x20, 0x72, 0x74, 0x6f, 0x73, 0x2d, 0x73, \r
+ 0x74, 0x61, 0x74, 0x73, 0xd, 0xa, 0x3c, 0x2f, 0x70, 0x72, \r
+ 0x65, 0x3e, 0x3c, 0x2f, 0x66, 0x6f, 0x6e, 0x74, 0x3e, 0xd, \r
+ 0xa, 0x3c, 0x2f, 0x66, 0x6f, 0x6e, 0x74, 0x3e, 0xd, 0xa, \r
+ 0x3c, 0x2f, 0x62, 0x6f, 0x64, 0x79, 0x3e, 0xd, 0xa, 0x3c, \r
+ 0x2f, 0x68, 0x74, 0x6d, 0x6c, 0x3e, 0xd, 0xa, 0xd, 0xa, \r
+0};\r
+\r
+static const unsigned char data_io_shtml[] = {\r
+ /* /io.shtml */\r
+ 0x2f, 0x69, 0x6f, 0x2e, 0x73, 0x68, 0x74, 0x6d, 0x6c, 0,\r
+ 0x3c, 0x21, 0x44, 0x4f, 0x43, 0x54, 0x59, 0x50, 0x45, 0x20, \r
+ 0x48, 0x54, 0x4d, 0x4c, 0x20, 0x50, 0x55, 0x42, 0x4c, 0x49, \r
+ 0x43, 0x20, 0x22, 0x2d, 0x2f, 0x2f, 0x57, 0x33, 0x43, 0x2f, \r
+ 0x2f, 0x44, 0x54, 0x44, 0x20, 0x48, 0x54, 0x4d, 0x4c, 0x20, \r
+ 0x34, 0x2e, 0x30, 0x31, 0x20, 0x54, 0x72, 0x61, 0x6e, 0x73, \r
+ 0x69, 0x74, 0x69, 0x6f, 0x6e, 0x61, 0x6c, 0x2f, 0x2f, 0x45, \r
+ 0x4e, 0x22, 0x20, 0x22, 0x68, 0x74, 0x74, 0x70, 0x3a, 0x2f, \r
+ 0x2f, 0x77, 0x77, 0x77, 0x2e, 0x77, 0x33, 0x2e, 0x6f, 0x72, \r
+ 0x67, 0x2f, 0x54, 0x52, 0x2f, 0x68, 0x74, 0x6d, 0x6c, 0x34, \r
+ 0x2f, 0x6c, 0x6f, 0x6f, 0x73, 0x65, 0x2e, 0x64, 0x74, 0x64, \r
+ 0x22, 0x3e, 0xd, 0xa, 0x3c, 0x68, 0x74, 0x6d, 0x6c, 0x3e, \r
+ 0xd, 0xa, 0x20, 0x20, 0x3c, 0x68, 0x65, 0x61, 0x64, 0x3e, \r
+ 0xd, 0xa, 0x20, 0x20, 0x20, 0x20, 0x3c, 0x74, 0x69, 0x74, \r
+ 0x6c, 0x65, 0x3e, 0x46, 0x72, 0x65, 0x65, 0x52, 0x54, 0x4f, \r
+ 0x53, 0x2e, 0x6f, 0x72, 0x67, 0x20, 0x75, 0x49, 0x50, 0x20, \r
+ 0x57, 0x45, 0x42, 0x20, 0x73, 0x65, 0x72, 0x76, 0x65, 0x72, \r
+ 0x20, 0x64, 0x65, 0x6d, 0x6f, 0x3c, 0x2f, 0x74, 0x69, 0x74, \r
+ 0x6c, 0x65, 0x3e, 0xd, 0xa, 0x20, 0x20, 0x3c, 0x2f, 0x68, \r
+ 0x65, 0x61, 0x64, 0x3e, 0xd, 0xa, 0x20, 0x20, 0x3c, 0x42, \r
+ 0x4f, 0x44, 0x59, 0x20, 0x62, 0x67, 0x63, 0x6f, 0x6c, 0x6f, \r
+ 0x72, 0x3d, 0x22, 0x23, 0x43, 0x43, 0x43, 0x43, 0x66, 0x66, \r
+ 0x22, 0x3e, 0xd, 0xa, 0x3c, 0x66, 0x6f, 0x6e, 0x74, 0x20, \r
+ 0x66, 0x61, 0x63, 0x65, 0x3d, 0x22, 0x61, 0x72, 0x69, 0x61, \r
+ 0x6c, 0x22, 0x3e, 0xd, 0xa, 0x3c, 0x61, 0x20, 0x68, 0x72, \r
+ 0x65, 0x66, 0x3d, 0x22, 0x69, 0x6e, 0x64, 0x65, 0x78, 0x2e, \r
+ 0x73, 0x68, 0x74, 0x6d, 0x6c, 0x22, 0x3e, 0x52, 0x54, 0x4f, \r
+ 0x53, 0x20, 0x53, 0x74, 0x61, 0x74, 0x73, 0x3c, 0x2f, 0x61, \r
+ 0x3e, 0x20, 0x3c, 0x62, 0x3e, 0x7c, 0x3c, 0x2f, 0x62, 0x3e, \r
+ 0x20, 0x3c, 0x61, 0x20, 0x68, 0x72, 0x65, 0x66, 0x3d, 0x22, \r
+ 0x73, 0x74, 0x61, 0x74, 0x73, 0x2e, 0x73, 0x68, 0x74, 0x6d, \r
+ 0x6c, 0x22, 0x3e, 0x54, 0x43, 0x50, 0x20, 0x53, 0x74, 0x61, \r
+ 0x74, 0x73, 0x3c, 0x2f, 0x61, 0x3e, 0x20, 0x3c, 0x62, 0x3e, \r
+ 0x7c, 0x3c, 0x2f, 0x62, 0x3e, 0x20, 0x3c, 0x61, 0x20, 0x68, \r
+ 0x72, 0x65, 0x66, 0x3d, 0x22, 0x74, 0x63, 0x70, 0x2e, 0x73, \r
+ 0x68, 0x74, 0x6d, 0x6c, 0x22, 0x3e, 0x43, 0x6f, 0x6e, 0x6e, \r
+ 0x65, 0x63, 0x74, 0x69, 0x6f, 0x6e, 0x73, 0x3c, 0x2f, 0x61, \r
+ 0x3e, 0x20, 0x3c, 0x62, 0x3e, 0x7c, 0x3c, 0x2f, 0x62, 0x3e, \r
+ 0x20, 0x3c, 0x61, 0x20, 0x68, 0x72, 0x65, 0x66, 0x3d, 0x22, \r
+ 0x68, 0x74, 0x74, 0x70, 0x3a, 0x2f, 0x2f, 0x77, 0x77, 0x77, \r
+ 0x2e, 0x66, 0x72, 0x65, 0x65, 0x72, 0x74, 0x6f, 0x73, 0x2e, \r
+ 0x6f, 0x72, 0x67, 0x2f, 0x22, 0x3e, 0x46, 0x72, 0x65, 0x65, \r
+ 0x52, 0x54, 0x4f, 0x53, 0x2e, 0x6f, 0x72, 0x67, 0x20, 0x48, \r
+ 0x6f, 0x6d, 0x65, 0x70, 0x61, 0x67, 0x65, 0x3c, 0x2f, 0x61, \r
+ 0x3e, 0x20, 0x3c, 0x62, 0x3e, 0x7c, 0x3c, 0x2f, 0x62, 0x3e, \r
+ 0x20, 0x3c, 0x61, 0x20, 0x68, 0x72, 0x65, 0x66, 0x3d, 0x22, \r
+ 0x69, 0x6f, 0x2e, 0x73, 0x68, 0x74, 0x6d, 0x6c, 0x22, 0x3e, \r
+ 0x49, 0x4f, 0x3c, 0x2f, 0x61, 0x3e, 0xd, 0xa, 0x3c, 0x62, \r
+ 0x72, 0x3e, 0x3c, 0x70, 0x3e, 0xd, 0xa, 0x3c, 0x68, 0x72, \r
+ 0x3e, 0xd, 0xa, 0x3c, 0x62, 0x3e, 0x4c, 0x45, 0x44, 0x20, \r
+ 0x61, 0x6e, 0x64, 0x20, 0x4c, 0x43, 0x44, 0x20, 0x49, 0x4f, \r
+ 0x3c, 0x2f, 0x62, 0x3e, 0x3c, 0x62, 0x72, 0x3e, 0xd, 0xa, \r
+ 0xd, 0xa, 0x3c, 0x70, 0x3e, 0xd, 0xa, 0xd, 0xa, 0x55, \r
+ 0x73, 0x65, 0x20, 0x74, 0x68, 0x65, 0x20, 0x63, 0x68, 0x65, \r
+ 0x63, 0x6b, 0x20, 0x62, 0x6f, 0x78, 0x20, 0x74, 0x6f, 0x20, \r
+ 0x74, 0x75, 0x72, 0x6e, 0x20, 0x6f, 0x6e, 0x20, 0x6f, 0x72, \r
+ 0x20, 0x6f, 0x66, 0x66, 0x20, 0x74, 0x68, 0x65, 0x20, 0x4c, \r
+ 0x45, 0x44, 0x2c, 0x20, 0x65, 0x6e, 0x74, 0x65, 0x72, 0x20, \r
+ 0x74, 0x65, 0x78, 0x74, 0x20, 0x74, 0x6f, 0x20, 0x64, 0x69, \r
+ 0x73, 0x70, 0x6c, 0x61, 0x79, 0x20, 0x6f, 0x6e, 0x20, 0x74, \r
+ 0x68, 0x65, 0x20, 0x4f, 0x4c, 0x45, 0x44, 0x20, 0x64, 0x69, \r
+ 0x73, 0x70, 0x6c, 0x61, 0x79, 0x2c, 0x20, 0x74, 0x68, 0x65, \r
+ 0x6e, 0x20, 0x63, 0x6c, 0x69, 0x63, 0x6b, 0x20, 0x22, 0x55, \r
+ 0x70, 0x64, 0x61, 0x74, 0x65, 0x20, 0x49, 0x4f, 0x22, 0x2e, \r
+ 0xd, 0xa, 0xd, 0xa, 0xd, 0xa, 0x3c, 0x70, 0x3e, 0xd, \r
+ 0xa, 0x3c, 0x66, 0x6f, 0x72, 0x6d, 0x20, 0x6e, 0x61, 0x6d, \r
+ 0x65, 0x3d, 0x22, 0x61, 0x46, 0x6f, 0x72, 0x6d, 0x22, 0x20, \r
+ 0x61, 0x63, 0x74, 0x69, 0x6f, 0x6e, 0x3d, 0x22, 0x2f, 0x69, \r
+ 0x6f, 0x2e, 0x73, 0x68, 0x74, 0x6d, 0x6c, 0x22, 0x20, 0x6d, \r
+ 0x65, 0x74, 0x68, 0x6f, 0x64, 0x3d, 0x22, 0x67, 0x65, 0x74, \r
+ 0x22, 0x3e, 0xd, 0xa, 0x25, 0x21, 0x20, 0x6c, 0x65, 0x64, \r
+ 0x2d, 0x69, 0x6f, 0xd, 0xa, 0x3c, 0x70, 0x3e, 0xd, 0xa, \r
+ 0x3c, 0x69, 0x6e, 0x70, 0x75, 0x74, 0x20, 0x74, 0x79, 0x70, \r
+ 0x65, 0x3d, 0x22, 0x73, 0x75, 0x62, 0x6d, 0x69, 0x74, 0x22, \r
+ 0x20, 0x76, 0x61, 0x6c, 0x75, 0x65, 0x3d, 0x22, 0x55, 0x70, \r
+ 0x64, 0x61, 0x74, 0x65, 0x20, 0x49, 0x4f, 0x22, 0x3e, 0xd, \r
+ 0xa, 0x3c, 0x2f, 0x66, 0x6f, 0x72, 0x6d, 0x3e, 0xd, 0xa, \r
+ 0x3c, 0x62, 0x72, 0x3e, 0x3c, 0x70, 0x3e, 0xd, 0xa, 0x3c, \r
+ 0x2f, 0x66, 0x6f, 0x6e, 0x74, 0x3e, 0xd, 0xa, 0x3c, 0x2f, \r
+ 0x62, 0x6f, 0x64, 0x79, 0x3e, 0xd, 0xa, 0x3c, 0x2f, 0x68, \r
+ 0x74, 0x6d, 0x6c, 0x3e, 0xd, 0xa, 0xd, 0xa, 0};\r
+\r
+static const unsigned char data_stats_shtml[] = {\r
+ /* /stats.shtml */\r
+ 0x2f, 0x73, 0x74, 0x61, 0x74, 0x73, 0x2e, 0x73, 0x68, 0x74, 0x6d, 0x6c, 0,\r
+ 0x3c, 0x21, 0x44, 0x4f, 0x43, 0x54, 0x59, 0x50, 0x45, 0x20, \r
+ 0x48, 0x54, 0x4d, 0x4c, 0x20, 0x50, 0x55, 0x42, 0x4c, 0x49, \r
+ 0x43, 0x20, 0x22, 0x2d, 0x2f, 0x2f, 0x57, 0x33, 0x43, 0x2f, \r
+ 0x2f, 0x44, 0x54, 0x44, 0x20, 0x48, 0x54, 0x4d, 0x4c, 0x20, \r
+ 0x34, 0x2e, 0x30, 0x31, 0x20, 0x54, 0x72, 0x61, 0x6e, 0x73, \r
+ 0x69, 0x74, 0x69, 0x6f, 0x6e, 0x61, 0x6c, 0x2f, 0x2f, 0x45, \r
+ 0x4e, 0x22, 0x20, 0x22, 0x68, 0x74, 0x74, 0x70, 0x3a, 0x2f, \r
+ 0x2f, 0x77, 0x77, 0x77, 0x2e, 0x77, 0x33, 0x2e, 0x6f, 0x72, \r
+ 0x67, 0x2f, 0x54, 0x52, 0x2f, 0x68, 0x74, 0x6d, 0x6c, 0x34, \r
+ 0x2f, 0x6c, 0x6f, 0x6f, 0x73, 0x65, 0x2e, 0x64, 0x74, 0x64, \r
+ 0x22, 0x3e, 0xd, 0xa, 0x3c, 0x68, 0x74, 0x6d, 0x6c, 0x3e, \r
+ 0xd, 0xa, 0x20, 0x20, 0x3c, 0x68, 0x65, 0x61, 0x64, 0x3e, \r
+ 0xd, 0xa, 0x20, 0x20, 0x20, 0x20, 0x3c, 0x74, 0x69, 0x74, \r
+ 0x6c, 0x65, 0x3e, 0x46, 0x72, 0x65, 0x65, 0x52, 0x54, 0x4f, \r
+ 0x53, 0x2e, 0x6f, 0x72, 0x67, 0x20, 0x75, 0x49, 0x50, 0x20, \r
+ 0x57, 0x45, 0x42, 0x20, 0x73, 0x65, 0x72, 0x76, 0x65, 0x72, \r
+ 0x20, 0x64, 0x65, 0x6d, 0x6f, 0x3c, 0x2f, 0x74, 0x69, 0x74, \r
+ 0x6c, 0x65, 0x3e, 0xd, 0xa, 0x20, 0x20, 0x3c, 0x2f, 0x68, \r
+ 0x65, 0x61, 0x64, 0x3e, 0xd, 0xa, 0x20, 0x20, 0x3c, 0x42, \r
+ 0x4f, 0x44, 0x59, 0x20, 0x62, 0x67, 0x63, 0x6f, 0x6c, 0x6f, \r
+ 0x72, 0x3d, 0x22, 0x23, 0x43, 0x43, 0x43, 0x43, 0x66, 0x66, \r
+ 0x22, 0x3e, 0xd, 0xa, 0x3c, 0x66, 0x6f, 0x6e, 0x74, 0x20, \r
+ 0x66, 0x61, 0x63, 0x65, 0x3d, 0x22, 0x61, 0x72, 0x69, 0x61, \r
+ 0x6c, 0x22, 0x3e, 0xd, 0xa, 0x3c, 0x61, 0x20, 0x68, 0x72, \r
+ 0x65, 0x66, 0x3d, 0x22, 0x69, 0x6e, 0x64, 0x65, 0x78, 0x2e, \r
+ 0x73, 0x68, 0x74, 0x6d, 0x6c, 0x22, 0x3e, 0x52, 0x54, 0x4f, \r
+ 0x53, 0x20, 0x53, 0x74, 0x61, 0x74, 0x73, 0x3c, 0x2f, 0x61, \r
+ 0x3e, 0x20, 0x3c, 0x62, 0x3e, 0x7c, 0x3c, 0x2f, 0x62, 0x3e, \r
+ 0x20, 0x3c, 0x61, 0x20, 0x68, 0x72, 0x65, 0x66, 0x3d, 0x22, \r
+ 0x73, 0x74, 0x61, 0x74, 0x73, 0x2e, 0x73, 0x68, 0x74, 0x6d, \r
+ 0x6c, 0x22, 0x3e, 0x54, 0x43, 0x50, 0x20, 0x53, 0x74, 0x61, \r
+ 0x74, 0x73, 0x3c, 0x2f, 0x61, 0x3e, 0x20, 0x3c, 0x62, 0x3e, \r
+ 0x7c, 0x3c, 0x2f, 0x62, 0x3e, 0x20, 0x3c, 0x61, 0x20, 0x68, \r
+ 0x72, 0x65, 0x66, 0x3d, 0x22, 0x74, 0x63, 0x70, 0x2e, 0x73, \r
+ 0x68, 0x74, 0x6d, 0x6c, 0x22, 0x3e, 0x43, 0x6f, 0x6e, 0x6e, \r
+ 0x65, 0x63, 0x74, 0x69, 0x6f, 0x6e, 0x73, 0x3c, 0x2f, 0x61, \r
+ 0x3e, 0x20, 0x3c, 0x62, 0x3e, 0x7c, 0x3c, 0x2f, 0x62, 0x3e, \r
+ 0x20, 0x3c, 0x61, 0x20, 0x68, 0x72, 0x65, 0x66, 0x3d, 0x22, \r
+ 0x68, 0x74, 0x74, 0x70, 0x3a, 0x2f, 0x2f, 0x77, 0x77, 0x77, \r
+ 0x2e, 0x66, 0x72, 0x65, 0x65, 0x72, 0x74, 0x6f, 0x73, 0x2e, \r
+ 0x6f, 0x72, 0x67, 0x2f, 0x22, 0x3e, 0x46, 0x72, 0x65, 0x65, \r
+ 0x52, 0x54, 0x4f, 0x53, 0x2e, 0x6f, 0x72, 0x67, 0x20, 0x48, \r
+ 0x6f, 0x6d, 0x65, 0x70, 0x61, 0x67, 0x65, 0x3c, 0x2f, 0x61, \r
+ 0x3e, 0x20, 0x3c, 0x62, 0x3e, 0x7c, 0x3c, 0x2f, 0x62, 0x3e, \r
+ 0x20, 0x3c, 0x61, 0x20, 0x68, 0x72, 0x65, 0x66, 0x3d, 0x22, \r
+ 0x69, 0x6f, 0x2e, 0x73, 0x68, 0x74, 0x6d, 0x6c, 0x22, 0x3e, \r
+ 0x49, 0x4f, 0x3c, 0x2f, 0x61, 0x3e, 0xd, 0xa, 0x3c, 0x62, \r
+ 0x72, 0x3e, 0x3c, 0x70, 0x3e, 0xd, 0xa, 0x3c, 0x68, 0x72, \r
+ 0x3e, 0xd, 0xa, 0x3c, 0x62, 0x72, 0x3e, 0x3c, 0x70, 0x3e, \r
+ 0xd, 0xa, 0x3c, 0x68, 0x32, 0x3e, 0x4e, 0x65, 0x74, 0x77, \r
+ 0x6f, 0x72, 0x6b, 0x20, 0x73, 0x74, 0x61, 0x74, 0x69, 0x73, \r
+ 0x74, 0x69, 0x63, 0x73, 0x3c, 0x2f, 0x68, 0x32, 0x3e, 0xd, \r
+ 0xa, 0x3c, 0x74, 0x61, 0x62, 0x6c, 0x65, 0x20, 0x77, 0x69, \r
+ 0x64, 0x74, 0x68, 0x3d, 0x22, 0x33, 0x30, 0x30, 0x22, 0x20, \r
+ 0x62, 0x6f, 0x72, 0x64, 0x65, 0x72, 0x3d, 0x22, 0x30, 0x22, \r
+ 0x3e, 0xd, 0xa, 0x3c, 0x74, 0x72, 0x3e, 0x3c, 0x74, 0x64, \r
+ 0x20, 0x61, 0x6c, 0x69, 0x67, 0x6e, 0x3d, 0x22, 0x6c, 0x65, \r
+ 0x66, 0x74, 0x22, 0x3e, 0x3c, 0x66, 0x6f, 0x6e, 0x74, 0x20, \r
+ 0x66, 0x61, 0x63, 0x65, 0x3d, 0x22, 0x63, 0x6f, 0x75, 0x72, \r
+ 0x69, 0x65, 0x72, 0x22, 0x3e, 0x3c, 0x70, 0x72, 0x65, 0x3e, \r
+ 0xd, 0xa, 0x49, 0x50, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, \r
+ 0x20, 0x20, 0x20, 0x20, 0x20, 0x50, 0x61, 0x63, 0x6b, 0x65, \r
+ 0x74, 0x73, 0x20, 0x64, 0x72, 0x6f, 0x70, 0x70, 0x65, 0x64, \r
+ 0xd, 0xa, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, \r
+ 0x20, 0x20, 0x20, 0x20, 0x20, 0x50, 0x61, 0x63, 0x6b, 0x65, \r
+ 0x74, 0x73, 0x20, 0x72, 0x65, 0x63, 0x65, 0x69, 0x76, 0x65, \r
+ 0x64, 0xd, 0xa, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, \r
+ 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x50, 0x61, 0x63, 0x6b, \r
+ 0x65, 0x74, 0x73, 0x20, 0x73, 0x65, 0x6e, 0x74, 0xd, 0xa, \r
+ 0x49, 0x50, 0x20, 0x65, 0x72, 0x72, 0x6f, 0x72, 0x73, 0x20, \r
+ 0x20, 0x20, 0x20, 0x49, 0x50, 0x20, 0x76, 0x65, 0x72, 0x73, \r
+ 0x69, 0x6f, 0x6e, 0x2f, 0x68, 0x65, 0x61, 0x64, 0x65, 0x72, \r
+ 0x20, 0x6c, 0x65, 0x6e, 0x67, 0x74, 0x68, 0xd, 0xa, 0x20, \r
+ 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, \r
+ 0x20, 0x20, 0x49, 0x50, 0x20, 0x6c, 0x65, 0x6e, 0x67, 0x74, \r
+ 0x68, 0x2c, 0x20, 0x68, 0x69, 0x67, 0x68, 0x20, 0x62, 0x79, \r
+ 0x74, 0x65, 0xd, 0xa, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, \r
+ 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x49, 0x50, 0x20, \r
+ 0x6c, 0x65, 0x6e, 0x67, 0x74, 0x68, 0x2c, 0x20, 0x6c, 0x6f, \r
+ 0x77, 0x20, 0x62, 0x79, 0x74, 0x65, 0xd, 0xa, 0x20, 0x20, \r
+ 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, \r
+ 0x20, 0x49, 0x50, 0x20, 0x66, 0x72, 0x61, 0x67, 0x6d, 0x65, \r
+ 0x6e, 0x74, 0x73, 0xd, 0xa, 0x20, 0x20, 0x20, 0x20, 0x20, \r
+ 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x48, 0x65, \r
+ 0x61, 0x64, 0x65, 0x72, 0x20, 0x63, 0x68, 0x65, 0x63, 0x6b, \r
+ 0x73, 0x75, 0x6d, 0xd, 0xa, 0x20, 0x20, 0x20, 0x20, 0x20, \r
+ 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x57, 0x72, \r
+ 0x6f, 0x6e, 0x67, 0x20, 0x70, 0x72, 0x6f, 0x74, 0x6f, 0x63, \r
+ 0x6f, 0x6c, 0xd, 0xa, 0x49, 0x43, 0x4d, 0x50, 0x9, 0x20, \r
+ 0x20, 0x20, 0x20, 0x20, 0x50, 0x61, 0x63, 0x6b, 0x65, 0x74, \r
+ 0x73, 0x20, 0x64, 0x72, 0x6f, 0x70, 0x70, 0x65, 0x64, 0xd, \r
+ 0xa, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, \r
+ 0x20, 0x20, 0x20, 0x20, 0x50, 0x61, 0x63, 0x6b, 0x65, 0x74, \r
+ 0x73, 0x20, 0x72, 0x65, 0x63, 0x65, 0x69, 0x76, 0x65, 0x64, \r
+ 0xd, 0xa, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, \r
+ 0x20, 0x20, 0x20, 0x20, 0x20, 0x50, 0x61, 0x63, 0x6b, 0x65, \r
+ 0x74, 0x73, 0x20, 0x73, 0x65, 0x6e, 0x74, 0xd, 0xa, 0x20, \r
+ 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, \r
+ 0x20, 0x20, 0x54, 0x79, 0x70, 0x65, 0x20, 0x65, 0x72, 0x72, \r
+ 0x6f, 0x72, 0x73, 0xd, 0xa, 0x54, 0x43, 0x50, 0x20, 0x20, \r
+ 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x50, 0x61, \r
+ 0x63, 0x6b, 0x65, 0x74, 0x73, 0x20, 0x64, 0x72, 0x6f, 0x70, \r
+ 0x70, 0x65, 0x64, 0xd, 0xa, 0x20, 0x20, 0x20, 0x20, 0x20, \r
+ 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x50, 0x61, \r
+ 0x63, 0x6b, 0x65, 0x74, 0x73, 0x20, 0x72, 0x65, 0x63, 0x65, \r
+ 0x69, 0x76, 0x65, 0x64, 0xd, 0xa, 0x20, 0x20, 0x20, 0x20, \r
+ 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x50, \r
+ 0x61, 0x63, 0x6b, 0x65, 0x74, 0x73, 0x20, 0x73, 0x65, 0x6e, \r
+ 0x74, 0xd, 0xa, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, \r
+ 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x43, 0x68, 0x65, 0x63, \r
+ 0x6b, 0x73, 0x75, 0x6d, 0x20, 0x65, 0x72, 0x72, 0x6f, 0x72, \r
+ 0x73, 0xd, 0xa, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, \r
+ 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x44, 0x61, 0x74, 0x61, \r
+ 0x20, 0x70, 0x61, 0x63, 0x6b, 0x65, 0x74, 0x73, 0x20, 0x77, \r
+ 0x69, 0x74, 0x68, 0x6f, 0x75, 0x74, 0x20, 0x41, 0x43, 0x4b, \r
+ 0x73, 0xd, 0xa, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, \r
+ 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x52, 0x65, 0x73, 0x65, \r
+ 0x74, 0x73, 0xd, 0xa, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, \r
+ 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x52, 0x65, 0x74, \r
+ 0x72, 0x61, 0x6e, 0x73, 0x6d, 0x69, 0x73, 0x73, 0x69, 0x6f, \r
+ 0x6e, 0x73, 0xd, 0xa, 0x9, 0x20, 0x20, 0x20, 0x20, 0x20, \r
+ 0x4e, 0x6f, 0x20, 0x63, 0x6f, 0x6e, 0x6e, 0x65, 0x63, 0x74, \r
+ 0x69, 0x6f, 0x6e, 0x20, 0x61, 0x76, 0x61, 0x6c, 0x69, 0x61, \r
+ 0x62, 0x6c, 0x65, 0xd, 0xa, 0x9, 0x20, 0x20, 0x20, 0x20, \r
+ 0x20, 0x43, 0x6f, 0x6e, 0x6e, 0x65, 0x63, 0x74, 0x69, 0x6f, \r
+ 0x6e, 0x20, 0x61, 0x74, 0x74, 0x65, 0x6d, 0x70, 0x74, 0x73, \r
+ 0x20, 0x74, 0x6f, 0x20, 0x63, 0x6c, 0x6f, 0x73, 0x65, 0x64, \r
+ 0x20, 0x70, 0x6f, 0x72, 0x74, 0x73, 0xd, 0xa, 0x3c, 0x2f, \r
+ 0x70, 0x72, 0x65, 0x3e, 0x3c, 0x2f, 0x66, 0x6f, 0x6e, 0x74, \r
+ 0x3e, 0x3c, 0x2f, 0x74, 0x64, 0x3e, 0x3c, 0x74, 0x64, 0x3e, \r
+ 0x3c, 0x70, 0x72, 0x65, 0x3e, 0x25, 0x21, 0x20, 0x6e, 0x65, \r
+ 0x74, 0x2d, 0x73, 0x74, 0x61, 0x74, 0x73, 0xd, 0xa, 0x3c, \r
+ 0x2f, 0x70, 0x72, 0x65, 0x3e, 0x3c, 0x2f, 0x74, 0x61, 0x62, \r
+ 0x6c, 0x65, 0x3e, 0xd, 0xa, 0x3c, 0x2f, 0x66, 0x6f, 0x6e, \r
+ 0x74, 0x3e, 0xd, 0xa, 0x3c, 0x2f, 0x62, 0x6f, 0x64, 0x79, \r
+ 0x3e, 0xd, 0xa, 0x3c, 0x2f, 0x68, 0x74, 0x6d, 0x6c, 0x3e, \r
+ 0xd, 0xa, 0};\r
+\r
+static const unsigned char data_tcp_shtml[] = {\r
+ /* /tcp.shtml */\r
+ 0x2f, 0x74, 0x63, 0x70, 0x2e, 0x73, 0x68, 0x74, 0x6d, 0x6c, 0,\r
+ 0x3c, 0x21, 0x44, 0x4f, 0x43, 0x54, 0x59, 0x50, 0x45, 0x20, \r
+ 0x48, 0x54, 0x4d, 0x4c, 0x20, 0x50, 0x55, 0x42, 0x4c, 0x49, \r
+ 0x43, 0x20, 0x22, 0x2d, 0x2f, 0x2f, 0x57, 0x33, 0x43, 0x2f, \r
+ 0x2f, 0x44, 0x54, 0x44, 0x20, 0x48, 0x54, 0x4d, 0x4c, 0x20, \r
+ 0x34, 0x2e, 0x30, 0x31, 0x20, 0x54, 0x72, 0x61, 0x6e, 0x73, \r
+ 0x69, 0x74, 0x69, 0x6f, 0x6e, 0x61, 0x6c, 0x2f, 0x2f, 0x45, \r
+ 0x4e, 0x22, 0x20, 0x22, 0x68, 0x74, 0x74, 0x70, 0x3a, 0x2f, \r
+ 0x2f, 0x77, 0x77, 0x77, 0x2e, 0x77, 0x33, 0x2e, 0x6f, 0x72, \r
+ 0x67, 0x2f, 0x54, 0x52, 0x2f, 0x68, 0x74, 0x6d, 0x6c, 0x34, \r
+ 0x2f, 0x6c, 0x6f, 0x6f, 0x73, 0x65, 0x2e, 0x64, 0x74, 0x64, \r
+ 0x22, 0x3e, 0xd, 0xa, 0x3c, 0x68, 0x74, 0x6d, 0x6c, 0x3e, \r
+ 0xd, 0xa, 0x20, 0x20, 0x3c, 0x68, 0x65, 0x61, 0x64, 0x3e, \r
+ 0xd, 0xa, 0x20, 0x20, 0x20, 0x20, 0x3c, 0x74, 0x69, 0x74, \r
+ 0x6c, 0x65, 0x3e, 0x46, 0x72, 0x65, 0x65, 0x52, 0x54, 0x4f, \r
+ 0x53, 0x2e, 0x6f, 0x72, 0x67, 0x20, 0x75, 0x49, 0x50, 0x20, \r
+ 0x57, 0x45, 0x42, 0x20, 0x73, 0x65, 0x72, 0x76, 0x65, 0x72, \r
+ 0x20, 0x64, 0x65, 0x6d, 0x6f, 0x3c, 0x2f, 0x74, 0x69, 0x74, \r
+ 0x6c, 0x65, 0x3e, 0xd, 0xa, 0x20, 0x20, 0x3c, 0x2f, 0x68, \r
+ 0x65, 0x61, 0x64, 0x3e, 0xd, 0xa, 0x20, 0x20, 0x3c, 0x42, \r
+ 0x4f, 0x44, 0x59, 0x20, 0x62, 0x67, 0x63, 0x6f, 0x6c, 0x6f, \r
+ 0x72, 0x3d, 0x22, 0x23, 0x43, 0x43, 0x43, 0x43, 0x66, 0x66, \r
+ 0x22, 0x3e, 0xd, 0xa, 0x3c, 0x66, 0x6f, 0x6e, 0x74, 0x20, \r
+ 0x66, 0x61, 0x63, 0x65, 0x3d, 0x22, 0x61, 0x72, 0x69, 0x61, \r
+ 0x6c, 0x22, 0x3e, 0xd, 0xa, 0x3c, 0x61, 0x20, 0x68, 0x72, \r
+ 0x65, 0x66, 0x3d, 0x22, 0x69, 0x6e, 0x64, 0x65, 0x78, 0x2e, \r
+ 0x73, 0x68, 0x74, 0x6d, 0x6c, 0x22, 0x3e, 0x52, 0x54, 0x4f, \r
+ 0x53, 0x20, 0x53, 0x74, 0x61, 0x74, 0x73, 0x3c, 0x2f, 0x61, \r
+ 0x3e, 0x20, 0x3c, 0x62, 0x3e, 0x7c, 0x3c, 0x2f, 0x62, 0x3e, \r
+ 0x20, 0x3c, 0x61, 0x20, 0x68, 0x72, 0x65, 0x66, 0x3d, 0x22, \r
+ 0x73, 0x74, 0x61, 0x74, 0x73, 0x2e, 0x73, 0x68, 0x74, 0x6d, \r
+ 0x6c, 0x22, 0x3e, 0x54, 0x43, 0x50, 0x20, 0x53, 0x74, 0x61, \r
+ 0x74, 0x73, 0x3c, 0x2f, 0x61, 0x3e, 0x20, 0x3c, 0x62, 0x3e, \r
+ 0x7c, 0x3c, 0x2f, 0x62, 0x3e, 0x20, 0x3c, 0x61, 0x20, 0x68, \r
+ 0x72, 0x65, 0x66, 0x3d, 0x22, 0x74, 0x63, 0x70, 0x2e, 0x73, \r
+ 0x68, 0x74, 0x6d, 0x6c, 0x22, 0x3e, 0x43, 0x6f, 0x6e, 0x6e, \r
+ 0x65, 0x63, 0x74, 0x69, 0x6f, 0x6e, 0x73, 0x3c, 0x2f, 0x61, \r
+ 0x3e, 0x20, 0x3c, 0x62, 0x3e, 0x7c, 0x3c, 0x2f, 0x62, 0x3e, \r
+ 0x20, 0x3c, 0x61, 0x20, 0x68, 0x72, 0x65, 0x66, 0x3d, 0x22, \r
+ 0x68, 0x74, 0x74, 0x70, 0x3a, 0x2f, 0x2f, 0x77, 0x77, 0x77, \r
+ 0x2e, 0x66, 0x72, 0x65, 0x65, 0x72, 0x74, 0x6f, 0x73, 0x2e, \r
+ 0x6f, 0x72, 0x67, 0x2f, 0x22, 0x3e, 0x46, 0x72, 0x65, 0x65, \r
+ 0x52, 0x54, 0x4f, 0x53, 0x2e, 0x6f, 0x72, 0x67, 0x20, 0x48, \r
+ 0x6f, 0x6d, 0x65, 0x70, 0x61, 0x67, 0x65, 0x3c, 0x2f, 0x61, \r
+ 0x3e, 0x20, 0x3c, 0x62, 0x3e, 0x7c, 0x3c, 0x2f, 0x62, 0x3e, \r
+ 0x20, 0x3c, 0x61, 0x20, 0x68, 0x72, 0x65, 0x66, 0x3d, 0x22, \r
+ 0x69, 0x6f, 0x2e, 0x73, 0x68, 0x74, 0x6d, 0x6c, 0x22, 0x3e, \r
+ 0x49, 0x4f, 0x3c, 0x2f, 0x61, 0x3e, 0xd, 0xa, 0x3c, 0x62, \r
+ 0x72, 0x3e, 0x3c, 0x70, 0x3e, 0xd, 0xa, 0x3c, 0x68, 0x72, \r
+ 0x3e, 0xd, 0xa, 0x3c, 0x62, 0x72, 0x3e, 0xd, 0xa, 0x3c, \r
+ 0x68, 0x32, 0x3e, 0x4e, 0x65, 0x74, 0x77, 0x6f, 0x72, 0x6b, \r
+ 0x20, 0x63, 0x6f, 0x6e, 0x6e, 0x65, 0x63, 0x74, 0x69, 0x6f, \r
+ 0x6e, 0x73, 0x3c, 0x2f, 0x68, 0x32, 0x3e, 0xd, 0xa, 0x3c, \r
+ 0x70, 0x3e, 0xd, 0xa, 0x3c, 0x74, 0x61, 0x62, 0x6c, 0x65, \r
+ 0x3e, 0xd, 0xa, 0x3c, 0x74, 0x72, 0x3e, 0x3c, 0x74, 0x68, \r
+ 0x3e, 0x4c, 0x6f, 0x63, 0x61, 0x6c, 0x3c, 0x2f, 0x74, 0x68, \r
+ 0x3e, 0x3c, 0x74, 0x68, 0x3e, 0x52, 0x65, 0x6d, 0x6f, 0x74, \r
+ 0x65, 0x3c, 0x2f, 0x74, 0x68, 0x3e, 0x3c, 0x74, 0x68, 0x3e, \r
+ 0x53, 0x74, 0x61, 0x74, 0x65, 0x3c, 0x2f, 0x74, 0x68, 0x3e, \r
+ 0x3c, 0x74, 0x68, 0x3e, 0x52, 0x65, 0x74, 0x72, 0x61, 0x6e, \r
+ 0x73, 0x6d, 0x69, 0x73, 0x73, 0x69, 0x6f, 0x6e, 0x73, 0x3c, \r
+ 0x2f, 0x74, 0x68, 0x3e, 0x3c, 0x74, 0x68, 0x3e, 0x54, 0x69, \r
+ 0x6d, 0x65, 0x72, 0x3c, 0x2f, 0x74, 0x68, 0x3e, 0x3c, 0x74, \r
+ 0x68, 0x3e, 0x46, 0x6c, 0x61, 0x67, 0x73, 0x3c, 0x2f, 0x74, \r
+ 0x68, 0x3e, 0x3c, 0x2f, 0x74, 0x72, 0x3e, 0xd, 0xa, 0x25, \r
+ 0x21, 0x20, 0x74, 0x63, 0x70, 0x2d, 0x63, 0x6f, 0x6e, 0x6e, \r
+ 0x65, 0x63, 0x74, 0x69, 0x6f, 0x6e, 0x73, 0xd, 0xa, 0x3c, \r
+ 0x2f, 0x70, 0x72, 0x65, 0x3e, 0x3c, 0x2f, 0x66, 0x6f, 0x6e, \r
+ 0x74, 0x3e, 0xd, 0xa, 0x3c, 0x2f, 0x66, 0x6f, 0x6e, 0x74, \r
+ 0x3e, 0xd, 0xa, 0x3c, 0x2f, 0x62, 0x6f, 0x64, 0x79, 0x3e, \r
+ 0xd, 0xa, 0x3c, 0x2f, 0x68, 0x74, 0x6d, 0x6c, 0x3e, 0xd, \r
+ 0xa, 0xd, 0xa, 0};\r
+\r
+const struct httpd_fsdata_file file_404_html[] = {{NULL, data_404_html, data_404_html + 10, sizeof(data_404_html) - 10}};\r
+\r
+const struct httpd_fsdata_file file_index_html[] = {{file_404_html, data_index_html, data_index_html + 12, sizeof(data_index_html) - 12}};\r
+\r
+const struct httpd_fsdata_file file_index_shtml[] = {{file_index_html, data_index_shtml, data_index_shtml + 13, sizeof(data_index_shtml) - 13}};\r
+\r
+const struct httpd_fsdata_file file_io_shtml[] = {{file_index_shtml, data_io_shtml, data_io_shtml + 10, sizeof(data_io_shtml) - 10}};\r
+\r
+const struct httpd_fsdata_file file_stats_shtml[] = {{file_io_shtml, data_stats_shtml, data_stats_shtml + 13, sizeof(data_stats_shtml) - 13}};\r
+\r
+const struct httpd_fsdata_file file_tcp_shtml[] = {{file_stats_shtml, data_tcp_shtml, data_tcp_shtml + 11, sizeof(data_tcp_shtml) - 11}};\r
+\r
+#define HTTPD_FS_ROOT file_tcp_shtml\r
+\r
+#define HTTPD_FS_NUMFILES 6\r
--- /dev/null
+/*\r
+ * Copyright (c) 2001, Swedish Institute of Computer Science.\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ * 1. Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the\r
+ * documentation and/or other materials provided with the distribution.\r
+ * 3. Neither the name of the Institute nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND\r
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\r
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\r
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\r
+ * SUCH DAMAGE.\r
+ *\r
+ * This file is part of the lwIP TCP/IP stack.\r
+ *\r
+ * Author: Adam Dunkels <adam@sics.se>\r
+ *\r
+ * $Id: httpd-fsdata.h,v 1.1 2006/06/07 09:13:08 adam Exp $\r
+ */\r
+#ifndef __HTTPD_FSDATA_H__\r
+#define __HTTPD_FSDATA_H__\r
+\r
+#include "uip.h"\r
+\r
+struct httpd_fsdata_file {\r
+ const struct httpd_fsdata_file *next;\r
+ const char *name;\r
+ const char *data;\r
+ const int len;\r
+#ifdef HTTPD_FS_STATISTICS\r
+#if HTTPD_FS_STATISTICS == 1\r
+ u16_t count;\r
+#endif /* HTTPD_FS_STATISTICS */\r
+#endif /* HTTPD_FS_STATISTICS */\r
+};\r
+\r
+struct httpd_fsdata_file_noconst {\r
+ struct httpd_fsdata_file *next;\r
+ char *name;\r
+ char *data;\r
+ int len;\r
+#ifdef HTTPD_FS_STATISTICS\r
+#if HTTPD_FS_STATISTICS == 1\r
+ u16_t count;\r
+#endif /* HTTPD_FS_STATISTICS */\r
+#endif /* HTTPD_FS_STATISTICS */\r
+};\r
+\r
+#endif /* __HTTPD_FSDATA_H__ */\r
--- /dev/null
+/**\r
+ * \addtogroup apps\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * \defgroup httpd Web server\r
+ * @{\r
+ * The uIP web server is a very simplistic implementation of an HTTP\r
+ * server. It can serve web pages and files from a read-only ROM\r
+ * filesystem, and provides a very small scripting language.\r
+\r
+ */\r
+\r
+/**\r
+ * \file\r
+ * Web server\r
+ * \author\r
+ * Adam Dunkels <adam@sics.se>\r
+ */\r
+\r
+\r
+/*\r
+ * Copyright (c) 2004, Adam Dunkels.\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ * 1. Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the\r
+ * documentation and/or other materials provided with the distribution.\r
+ * 3. Neither the name of the Institute nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND\r
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\r
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\r
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\r
+ * SUCH DAMAGE.\r
+ *\r
+ * This file is part of the uIP TCP/IP stack.\r
+ *\r
+ * Author: Adam Dunkels <adam@sics.se>\r
+ *\r
+ * $Id: httpd.c,v 1.2 2006/06/11 21:46:38 adam Exp $\r
+ */\r
+\r
+#include "uip.h"\r
+#include "httpd.h"\r
+#include "httpd-fs.h"\r
+#include "httpd-cgi.h"\r
+#include "http-strings.h"\r
+\r
+#include <string.h>\r
+\r
+#define STATE_WAITING 0\r
+#define STATE_OUTPUT 1\r
+\r
+#define ISO_nl 0x0a\r
+#define ISO_space 0x20\r
+#define ISO_bang 0x21\r
+#define ISO_percent 0x25\r
+#define ISO_period 0x2e\r
+#define ISO_slash 0x2f\r
+#define ISO_colon 0x3a\r
+\r
+\r
+/*---------------------------------------------------------------------------*/\r
+static unsigned short\r
+generate_part_of_file(void *state)\r
+{\r
+ struct httpd_state *s = (struct httpd_state *)state;\r
+\r
+ if(s->file.len > uip_mss()) {\r
+ s->len = uip_mss();\r
+ } else {\r
+ s->len = s->file.len;\r
+ }\r
+ memcpy(uip_appdata, s->file.data, s->len);\r
+ \r
+ return s->len;\r
+}\r
+/*---------------------------------------------------------------------------*/\r
+static\r
+PT_THREAD(send_file(struct httpd_state *s))\r
+{\r
+ PSOCK_BEGIN(&s->sout);\r
+ \r
+ do {\r
+ PSOCK_GENERATOR_SEND(&s->sout, generate_part_of_file, s);\r
+ s->file.len -= s->len;\r
+ s->file.data += s->len;\r
+ } while(s->file.len > 0);\r
+ \r
+ PSOCK_END(&s->sout);\r
+}\r
+/*---------------------------------------------------------------------------*/\r
+static\r
+PT_THREAD(send_part_of_file(struct httpd_state *s))\r
+{\r
+ PSOCK_BEGIN(&s->sout);\r
+\r
+ PSOCK_SEND(&s->sout, s->file.data, s->len);\r
+ \r
+ PSOCK_END(&s->sout);\r
+}\r
+/*---------------------------------------------------------------------------*/\r
+static void\r
+next_scriptstate(struct httpd_state *s)\r
+{\r
+ char *p;\r
+ p = strchr(s->scriptptr, ISO_nl) + 1;\r
+ s->scriptlen -= (unsigned short)(p - s->scriptptr);\r
+ s->scriptptr = p;\r
+}\r
+/*---------------------------------------------------------------------------*/\r
+static\r
+PT_THREAD(handle_script(struct httpd_state *s))\r
+{\r
+ char *ptr;\r
+ \r
+ PT_BEGIN(&s->scriptpt);\r
+\r
+\r
+ while(s->file.len > 0) {\r
+\r
+ /* Check if we should start executing a script. */\r
+ if(*s->file.data == ISO_percent &&\r
+ *(s->file.data + 1) == ISO_bang) {\r
+ s->scriptptr = s->file.data + 3;\r
+ s->scriptlen = s->file.len - 3;\r
+ if(*(s->scriptptr - 1) == ISO_colon) {\r
+ httpd_fs_open(s->scriptptr + 1, &s->file);\r
+ PT_WAIT_THREAD(&s->scriptpt, send_file(s));\r
+ } else {\r
+ PT_WAIT_THREAD(&s->scriptpt,\r
+ httpd_cgi(s->scriptptr)(s, s->scriptptr));\r
+ }\r
+ next_scriptstate(s);\r
+ \r
+ /* The script is over, so we reset the pointers and continue\r
+ sending the rest of the file. */\r
+ s->file.data = s->scriptptr;\r
+ s->file.len = s->scriptlen;\r
+ } else {\r
+ /* See if we find the start of script marker in the block of HTML\r
+ to be sent. */\r
+\r
+ if(s->file.len > uip_mss()) {\r
+ s->len = uip_mss();\r
+ } else {\r
+ s->len = s->file.len;\r
+ }\r
+\r
+ if(*s->file.data == ISO_percent) {\r
+ ptr = strchr(s->file.data + 1, ISO_percent);\r
+ } else {\r
+ ptr = strchr(s->file.data, ISO_percent);\r
+ }\r
+ if(ptr != NULL &&\r
+ ptr != s->file.data) {\r
+ s->len = (int)(ptr - s->file.data);\r
+ if(s->len >= uip_mss()) {\r
+ s->len = uip_mss();\r
+ }\r
+ }\r
+ PT_WAIT_THREAD(&s->scriptpt, send_part_of_file(s));\r
+ s->file.data += s->len;\r
+ s->file.len -= s->len;\r
+ \r
+ }\r
+ }\r
+ \r
+ PT_END(&s->scriptpt);\r
+}\r
+/*---------------------------------------------------------------------------*/\r
+static\r
+PT_THREAD(send_headers(struct httpd_state *s, const char *statushdr))\r
+{\r
+ char *ptr;\r
+\r
+ PSOCK_BEGIN(&s->sout);\r
+\r
+ PSOCK_SEND_STR(&s->sout, statushdr);\r
+\r
+ ptr = strrchr(s->filename, ISO_period);\r
+ if(ptr == NULL) {\r
+ PSOCK_SEND_STR(&s->sout, http_content_type_binary);\r
+ } else if(strncmp(http_html, ptr, 5) == 0 ||\r
+ strncmp(http_shtml, ptr, 6) == 0) {\r
+ PSOCK_SEND_STR(&s->sout, http_content_type_html);\r
+ } else if(strncmp(http_css, ptr, 4) == 0) {\r
+ PSOCK_SEND_STR(&s->sout, http_content_type_css);\r
+ } else if(strncmp(http_png, ptr, 4) == 0) {\r
+ PSOCK_SEND_STR(&s->sout, http_content_type_png);\r
+ } else if(strncmp(http_gif, ptr, 4) == 0) {\r
+ PSOCK_SEND_STR(&s->sout, http_content_type_gif);\r
+ } else if(strncmp(http_jpg, ptr, 4) == 0) {\r
+ PSOCK_SEND_STR(&s->sout, http_content_type_jpg);\r
+ } else {\r
+ PSOCK_SEND_STR(&s->sout, http_content_type_plain);\r
+ }\r
+ PSOCK_END(&s->sout);\r
+}\r
+/*---------------------------------------------------------------------------*/\r
+static\r
+PT_THREAD(handle_output(struct httpd_state *s))\r
+{\r
+ char *ptr;\r
+ \r
+ PT_BEGIN(&s->outputpt);\r
+ \r
+ if(!httpd_fs_open(s->filename, &s->file)) {\r
+ httpd_fs_open(http_404_html, &s->file);\r
+ strcpy(s->filename, http_404_html);\r
+ PT_WAIT_THREAD(&s->outputpt,\r
+ send_headers(s,\r
+ http_header_404));\r
+ PT_WAIT_THREAD(&s->outputpt,\r
+ send_file(s));\r
+ } else {\r
+ PT_WAIT_THREAD(&s->outputpt,\r
+ send_headers(s,\r
+ http_header_200));\r
+ ptr = strchr(s->filename, ISO_period);\r
+ if(ptr != NULL && strncmp(ptr, http_shtml, 6) == 0) {\r
+ PT_INIT(&s->scriptpt);\r
+ PT_WAIT_THREAD(&s->outputpt, handle_script(s));\r
+ } else {\r
+ PT_WAIT_THREAD(&s->outputpt,\r
+ send_file(s));\r
+ }\r
+ }\r
+ PSOCK_CLOSE(&s->sout);\r
+ PT_END(&s->outputpt);\r
+}\r
+/*---------------------------------------------------------------------------*/\r
+static\r
+PT_THREAD(handle_input(struct httpd_state *s))\r
+{\r
+ PSOCK_BEGIN(&s->sin);\r
+\r
+ PSOCK_READTO(&s->sin, ISO_space);\r
+\r
+ \r
+ if(strncmp(s->inputbuf, http_get, 4) != 0) {\r
+ PSOCK_CLOSE_EXIT(&s->sin);\r
+ }\r
+ PSOCK_READTO(&s->sin, ISO_space);\r
+\r
+ if(s->inputbuf[0] != ISO_slash) {\r
+ PSOCK_CLOSE_EXIT(&s->sin);\r
+ }\r
+\r
+ if(s->inputbuf[1] == ISO_space) {\r
+ strncpy(s->filename, http_index_html, sizeof(s->filename));\r
+ } else {\r
+\r
+ s->inputbuf[PSOCK_DATALEN(&s->sin) - 1] = 0;\r
+\r
+ /* Process any form input being sent to the server. */\r
+ {\r
+ extern void vApplicationProcessFormInput( char *pcInputString, long xInputLength );\r
+ vApplicationProcessFormInput( s->inputbuf, PSOCK_DATALEN(&s->sin) );\r
+ }\r
+\r
+ strncpy(s->filename, &s->inputbuf[0], sizeof(s->filename));\r
+ }\r
+\r
+ /* httpd_log_file(uip_conn->ripaddr, s->filename);*/\r
+ \r
+ s->state = STATE_OUTPUT;\r
+\r
+ while(1) {\r
+ PSOCK_READTO(&s->sin, ISO_nl);\r
+\r
+ if(strncmp(s->inputbuf, http_referer, 8) == 0) {\r
+ s->inputbuf[PSOCK_DATALEN(&s->sin) - 2] = 0;\r
+ /* httpd_log(&s->inputbuf[9]);*/\r
+ }\r
+ }\r
+ \r
+ PSOCK_END(&s->sin);\r
+}\r
+/*---------------------------------------------------------------------------*/\r
+static void\r
+handle_connection(struct httpd_state *s)\r
+{\r
+ handle_input(s);\r
+ if(s->state == STATE_OUTPUT) {\r
+ handle_output(s);\r
+ }\r
+}\r
+/*---------------------------------------------------------------------------*/\r
+void\r
+httpd_appcall(void)\r
+{\r
+ struct httpd_state *s = (struct httpd_state *)&(uip_conn->appstate);\r
+\r
+ if(uip_closed() || uip_aborted() || uip_timedout()) {\r
+ } else if(uip_connected()) {\r
+ PSOCK_INIT(&s->sin, s->inputbuf, sizeof(s->inputbuf) - 1);\r
+ PSOCK_INIT(&s->sout, s->inputbuf, sizeof(s->inputbuf) - 1);\r
+ PT_INIT(&s->outputpt);\r
+ s->state = STATE_WAITING;\r
+ /* timer_set(&s->timer, CLOCK_SECOND * 100);*/\r
+ s->timer = 0;\r
+ handle_connection(s);\r
+ } else if(s != NULL) {\r
+ if(uip_poll()) {\r
+ ++s->timer;\r
+ if(s->timer >= 20) {\r
+ uip_abort();\r
+ }\r
+ } else {\r
+ s->timer = 0;\r
+ }\r
+ handle_connection(s);\r
+ } else {\r
+ uip_abort();\r
+ }\r
+}\r
+/*---------------------------------------------------------------------------*/\r
+/**\r
+ * \brief Initialize the web server\r
+ *\r
+ * This function initializes the web server and should be\r
+ * called at system boot-up.\r
+ */\r
+void\r
+httpd_init(void)\r
+{\r
+ uip_listen(HTONS(80));\r
+}\r
+/*---------------------------------------------------------------------------*/\r
+/** @} */\r
--- /dev/null
+/*\r
+ * Copyright (c) 2001-2005, Adam Dunkels.\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ * 1. Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the\r
+ * documentation and/or other materials provided with the distribution.\r
+ * 3. The name of the author may not be used to endorse or promote\r
+ * products derived from this software without specific prior\r
+ * written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS\r
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\r
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY\r
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE\r
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\r
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\r
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * This file is part of the uIP TCP/IP stack.\r
+ *\r
+ * $Id: httpd.h,v 1.2 2006/06/11 21:46:38 adam Exp $\r
+ *\r
+ */\r
+\r
+#ifndef __HTTPD_H__\r
+#define __HTTPD_H__\r
+\r
+#include "psock.h"\r
+#include "httpd-fs.h"\r
+\r
+struct httpd_state {\r
+ unsigned char timer;\r
+ struct psock sin, sout;\r
+ struct pt outputpt, scriptpt;\r
+ char inputbuf[50];\r
+ char filename[20];\r
+ char state;\r
+ struct httpd_fs_file file;\r
+ int len;\r
+ char *scriptptr;\r
+ int scriptlen;\r
+ \r
+ unsigned short count;\r
+};\r
+\r
+void httpd_init(void);\r
+void httpd_appcall(void);\r
+\r
+void httpd_log(char *msg);\r
+void httpd_log_file(u16_t *requester, char *file);\r
+\r
+#endif /* __HTTPD_H__ */\r
--- /dev/null
+#!/usr/bin/perl\r
+\r
+open(OUTPUT, "> httpd-fsdata.c");\r
+\r
+chdir("httpd-fs");\r
+\r
+opendir(DIR, ".");\r
+@files = grep { !/^\./ && !/(CVS|~)/ } readdir(DIR);\r
+closedir(DIR);\r
+\r
+foreach $file (@files) { \r
+ \r
+ if(-d $file && $file !~ /^\./) {\r
+ print "Processing directory $file\n";\r
+ opendir(DIR, $file);\r
+ @newfiles = grep { !/^\./ && !/(CVS|~)/ } readdir(DIR);\r
+ closedir(DIR);\r
+ printf "Adding files @newfiles\n";\r
+ @files = (@files, map { $_ = "$file/$_" } @newfiles);\r
+ next;\r
+ }\r
+}\r
+\r
+foreach $file (@files) {\r
+ if(-f $file) {\r
+ \r
+ print "Adding file $file\n";\r
+ \r
+ open(FILE, $file) || die "Could not open file $file\n";\r
+\r
+ $file =~ s-^-/-;\r
+ $fvar = $file;\r
+ $fvar =~ s-/-_-g;\r
+ $fvar =~ s-\.-_-g;\r
+ # for AVR, add PROGMEM here\r
+ print(OUTPUT "static const unsigned char data".$fvar."[] = {\n");\r
+ print(OUTPUT "\t/* $file */\n\t");\r
+ for($j = 0; $j < length($file); $j++) {\r
+ printf(OUTPUT "%#02x, ", unpack("C", substr($file, $j, 1)));\r
+ }\r
+ printf(OUTPUT "0,\n");\r
+ \r
+ \r
+ $i = 0; \r
+ while(read(FILE, $data, 1)) {\r
+ if($i == 0) {\r
+ print(OUTPUT "\t");\r
+ }\r
+ printf(OUTPUT "%#02x, ", unpack("C", $data));\r
+ $i++;\r
+ if($i == 10) {\r
+ print(OUTPUT "\n");\r
+ $i = 0;\r
+ }\r
+ }\r
+ print(OUTPUT "0};\n\n");\r
+ close(FILE);\r
+ push(@fvars, $fvar);\r
+ push(@pfiles, $file);\r
+ }\r
+}\r
+\r
+for($i = 0; $i < @fvars; $i++) {\r
+ $file = $pfiles[$i];\r
+ $fvar = $fvars[$i];\r
+\r
+ if($i == 0) {\r
+ $prevfile = "NULL";\r
+ } else {\r
+ $prevfile = "file" . $fvars[$i - 1];\r
+ }\r
+ print(OUTPUT "const struct httpd_fsdata_file file".$fvar."[] = {{$prevfile, data$fvar, ");\r
+ print(OUTPUT "data$fvar + ". (length($file) + 1) .", ");\r
+ print(OUTPUT "sizeof(data$fvar) - ". (length($file) + 1) ."}};\n\n");\r
+}\r
+\r
+print(OUTPUT "#define HTTPD_FS_ROOT file$fvars[$i - 1]\n\n");\r
+print(OUTPUT "#define HTTPD_FS_NUMFILES $i\n");\r
--- /dev/null
+#!/usr/bin/perl\r
+\r
+\r
+sub stringify {\r
+ my $name = shift(@_);\r
+ open(OUTPUTC, "> $name.c");\r
+ open(OUTPUTH, "> $name.h");\r
+ \r
+ open(FILE, "$name");\r
+ \r
+ while(<FILE>) {\r
+ if(/(.+) "(.+)"/) {\r
+ $var = $1;\r
+ $data = $2;\r
+ \r
+ $datan = $data;\r
+ $datan =~ s/\\r/\r/g;\r
+ $datan =~ s/\\n/\n/g;\r
+ $datan =~ s/\\01/\01/g; \r
+ $datan =~ s/\\0/\0/g;\r
+ \r
+ printf(OUTPUTC "const char $var\[%d] = \n", length($datan) + 1);\r
+ printf(OUTPUTC "/* \"$data\" */\n");\r
+ printf(OUTPUTC "{");\r
+ for($j = 0; $j < length($datan); $j++) {\r
+ printf(OUTPUTC "%#02x, ", unpack("C", substr($datan, $j, 1)));\r
+ }\r
+ printf(OUTPUTC "};\n");\r
+ \r
+ printf(OUTPUTH "extern const char $var\[%d];\n", length($datan) + 1);\r
+ \r
+ }\r
+ }\r
+ close(OUTPUTC);\r
+ close(OUTPUTH);\r
+}\r
+stringify("http-strings");\r
+\r
+exit 0;\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS.org V4.3.0 - Copyright (C) 2003-2007 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS.org distribution.\r
+\r
+ FreeRTOS.org is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS.org is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS.org; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS.org, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section\r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license\r
+ and contact details. Please ensure to read the configuration and relevant\r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+/* Standard includes. */\r
+#include <string.h>\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "semphr.h"\r
+\r
+#include "lcd_message.h"\r
+\r
+/* uip includes. */\r
+#include "hw_types.h"\r
+\r
+#include "uip.h"\r
+#include "uip_arp.h"\r
+#include "httpd.h"\r
+#include "timer.h"\r
+#include "clock-arch.h"\r
+#include "hw_ethernet.h"\r
+#include "ethernet.h"\r
+#include "hw_memmap.h"\r
+#include "lmi_flash.h"\r
+\r
+/* Demo includes. */\r
+#include "emac.h"\r
+#include "partest.h"\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* IP address configuration. */\r
+#define uipIP_ADDR0 172\r
+#define uipIP_ADDR1 25\r
+#define uipIP_ADDR2 218\r
+#define uipIP_ADDR3 9 \r
+\r
+/* How long to wait before attempting to connect the MAC again. */\r
+#define uipINIT_WAIT 100\r
+\r
+/* Shortcut to the header within the Rx buffer. */\r
+#define xHeader ((struct uip_eth_hdr *) &uip_buf[ 0 ])\r
+\r
+/* Standard constant. */\r
+#define uipTOTAL_FRAME_HEADER_SIZE 54\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Send the uIP buffer to the MAC.\r
+ */\r
+static void prvENET_Send(void);\r
+\r
+/*\r
+ * Setup the MAC address in the MAC itself, and in the uIP stack.\r
+ */\r
+static void prvSetMACAddress( void );\r
+\r
+/*\r
+ * Port functions required by the uIP stack.\r
+ */\r
+void clock_init( void );\r
+clock_time_t clock_time( void );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* The semaphore used by the ISR to wake the uIP task. */\r
+extern xSemaphoreHandle xEMACSemaphore;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void clock_init(void)\r
+{\r
+ /* This is done when the scheduler starts. */\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+clock_time_t clock_time( void )\r
+{\r
+ return xTaskGetTickCount();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vuIP_Task( void *pvParameters )\r
+{\r
+portBASE_TYPE i;\r
+uip_ipaddr_t xIPAddr;\r
+struct timer periodic_timer, arp_timer;\r
+extern void ( vEMAC_ISR )( void );\r
+\r
+ /* Create the semaphore used by the ISR to wake this task. */\r
+ vSemaphoreCreateBinary( xEMACSemaphore );\r
+ \r
+ /* Initialise the uIP stack. */\r
+ timer_set( &periodic_timer, configTICK_RATE_HZ / 2 );\r
+ timer_set( &arp_timer, configTICK_RATE_HZ * 10 );\r
+ uip_init();\r
+ uip_ipaddr( xIPAddr, uipIP_ADDR0, uipIP_ADDR1, uipIP_ADDR2, uipIP_ADDR3 );\r
+ uip_sethostaddr( xIPAddr );\r
+ httpd_init();\r
+\r
+ while( vInitEMAC() != pdPASS )\r
+ {\r
+ vTaskDelay( uipINIT_WAIT );\r
+ }\r
+ prvSetMACAddress(); \r
+ \r
+\r
+ for( ;; )\r
+ {\r
+ /* Is there received data ready to be processed? */\r
+ uip_len = uiGetEMACRxData( uip_buf );\r
+ \r
+ if( uip_len > 0 )\r
+ {\r
+ /* Standard uIP loop taken from the uIP manual. */\r
+\r
+ if( xHeader->type == htons( UIP_ETHTYPE_IP ) )\r
+ {\r
+ uip_arp_ipin();\r
+ uip_input();\r
+\r
+ /* If the above function invocation resulted in data that\r
+ should be sent out on the network, the global variable\r
+ uip_len is set to a value > 0. */\r
+ if( uip_len > 0 )\r
+ {\r
+ uip_arp_out();\r
+ prvENET_Send();\r
+ }\r
+ }\r
+ else if( xHeader->type == htons( UIP_ETHTYPE_ARP ) )\r
+ {\r
+ uip_arp_arpin();\r
+\r
+ /* If the above function invocation resulted in data that\r
+ should be sent out on the network, the global variable\r
+ uip_len is set to a value > 0. */\r
+ if( uip_len > 0 )\r
+ {\r
+ prvENET_Send();\r
+ }\r
+ }\r
+ }\r
+ else\r
+ {\r
+ if( timer_expired( &periodic_timer ) )\r
+ {\r
+ timer_reset( &periodic_timer );\r
+ for( i = 0; i < UIP_CONNS; i++ )\r
+ {\r
+ uip_periodic( i );\r
+ \r
+ /* If the above function invocation resulted in data that\r
+ should be sent out on the network, the global variable\r
+ uip_len is set to a value > 0. */\r
+ if( uip_len > 0 )\r
+ {\r
+ uip_arp_out();\r
+ prvENET_Send();\r
+ }\r
+ } \r
+ \r
+ /* Call the ARP timer function every 10 seconds. */\r
+ if( timer_expired( &arp_timer ) )\r
+ {\r
+ timer_reset( &arp_timer );\r
+ uip_arp_timer();\r
+ }\r
+ }\r
+ else\r
+ { \r
+ /* We did not receive a packet, and there was no periodic\r
+ processing to perform. Block for a fixed period. If a packet\r
+ is received during this period we will be woken by the ISR\r
+ giving us the Semaphore. */\r
+ xSemaphoreTake( xEMACSemaphore, configTICK_RATE_HZ / 2 ); \r
+ }\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvENET_Send(void)\r
+{\r
+ vInitialiseSend();\r
+ vIncrementTxLength( uip_len );\r
+ vSendBufferToMAC();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvSetMACAddress( void )\r
+{\r
+unsigned portLONG ulUser0, ulUser1;\r
+unsigned char pucMACArray[8];\r
+struct uip_eth_addr xAddr;\r
+\r
+ /* Get the device MAC address from flash */\r
+ FlashUserGet(&ulUser0, &ulUser1);\r
+\r
+ /* Convert the MAC address from flash into sequence of bytes. */\r
+ pucMACArray[0] = ((ulUser0 >> 0) & 0xff);\r
+ pucMACArray[1] = ((ulUser0 >> 8) & 0xff);\r
+ pucMACArray[2] = ((ulUser0 >> 16) & 0xff);\r
+ pucMACArray[3] = ((ulUser1 >> 0) & 0xff);\r
+ pucMACArray[4] = ((ulUser1 >> 8) & 0xff);\r
+ pucMACArray[5] = ((ulUser1 >> 16) & 0xff);\r
+\r
+ /* Program the MAC address. */\r
+ EthernetMACAddrSet(ETH_BASE, pucMACArray);\r
+\r
+ xAddr.addr[ 0 ] = pucMACArray[0];\r
+ xAddr.addr[ 1 ] = pucMACArray[1];\r
+ xAddr.addr[ 2 ] = pucMACArray[2];\r
+ xAddr.addr[ 3 ] = pucMACArray[3];\r
+ xAddr.addr[ 4 ] = pucMACArray[4];\r
+ xAddr.addr[ 5 ] = pucMACArray[5];\r
+ uip_setethaddr( xAddr );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationProcessFormInput( portCHAR *pcInputString, portBASE_TYPE xInputLength )\r
+{\r
+char *c, *pcText;\r
+static portCHAR cMessageForDisplay[ 32 ];\r
+extern xQueueHandle xOLEDQueue;\r
+xOLEDMessage xOLEDMessage;\r
+\r
+ /* Process the form input sent by the IO page of the served HTML. */\r
+\r
+ c = strstr( pcInputString, "?" );\r
+\r
+ if( c )\r
+ {\r
+ /* Turn LED's on or off in accordance with the check box status. */\r
+ if( strstr( c, "LED0=1" ) != NULL )\r
+ {\r
+ vParTestSetLED( 0, 1 );\r
+ }\r
+ else\r
+ {\r
+ vParTestSetLED( 0, 0 );\r
+ } \r
+ \r
+ /* Find the start of the text to be displayed on the LCD. */\r
+ pcText = strstr( c, "LCD=" );\r
+ pcText += strlen( "LCD=" );\r
+\r
+ /* Terminate the file name for further processing within uIP. */\r
+ *c = 0x00;\r
+\r
+ /* Terminate the LCD string. */\r
+ c = strstr( pcText, " " );\r
+ if( c != NULL )\r
+ {\r
+ *c = 0x00;\r
+ }\r
+\r
+ /* Add required spaces. */\r
+ while( ( c = strstr( pcText, "+" ) ) != NULL )\r
+ {\r
+ *c = ' ';\r
+ }\r
+\r
+ /* Write the message to the LCD. */\r
+ strcpy( cMessageForDisplay, pcText );\r
+ xOLEDMessage.pcMessage = cMessageForDisplay;\r
+ xQueueSend( xOLEDQueue, &xOLEDMessage, portMAX_DELAY );\r
+ }\r
+}\r
+\r
--- /dev/null
+/**\r
+ * \addtogroup uipopt\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * \name Project-specific configuration options\r
+ * @{\r
+ *\r
+ * uIP has a number of configuration options that can be overridden\r
+ * for each project. These are kept in a project-specific uip-conf.h\r
+ * file and all configuration names have the prefix UIP_CONF.\r
+ */\r
+\r
+/*\r
+ * Copyright (c) 2006, Swedish Institute of Computer Science.\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ * 1. Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the\r
+ * documentation and/or other materials provided with the distribution.\r
+ * 3. Neither the name of the Institute nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND\r
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\r
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\r
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\r
+ * SUCH DAMAGE.\r
+ *\r
+ * This file is part of the uIP TCP/IP stack\r
+ *\r
+ * $Id: uip-conf.h,v 1.6 2006/06/12 08:00:31 adam Exp $\r
+ */\r
+\r
+/**\r
+ * \file\r
+ * An example uIP configuration file\r
+ * \author\r
+ * Adam Dunkels <adam@sics.se>\r
+ */\r
+\r
+#ifndef __UIP_CONF_H__\r
+#define __UIP_CONF_H__\r
+\r
+#include <stdint.h>\r
+\r
+/**\r
+ * 8 bit datatype\r
+ *\r
+ * This typedef defines the 8-bit type used throughout uIP.\r
+ *\r
+ * \hideinitializer\r
+ */\r
+typedef uint8_t u8_t;\r
+\r
+/**\r
+ * 16 bit datatype\r
+ *\r
+ * This typedef defines the 16-bit type used throughout uIP.\r
+ *\r
+ * \hideinitializer\r
+ */\r
+typedef uint16_t u16_t;\r
+\r
+/**\r
+ * Statistics datatype\r
+ *\r
+ * This typedef defines the dataype used for keeping statistics in\r
+ * uIP.\r
+ *\r
+ * \hideinitializer\r
+ */\r
+typedef unsigned short uip_stats_t;\r
+\r
+/**\r
+ * Maximum number of TCP connections.\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define UIP_CONF_MAX_CONNECTIONS 40\r
+\r
+/**\r
+ * Maximum number of listening TCP ports.\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define UIP_CONF_MAX_LISTENPORTS 40\r
+\r
+/**\r
+ * uIP buffer size.\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define UIP_CONF_BUFFER_SIZE 1480\r
+\r
+/**\r
+ * CPU byte order.\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define UIP_CONF_BYTE_ORDER LITTLE_ENDIAN\r
+\r
+/**\r
+ * Logging on or off\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define UIP_CONF_LOGGING 0\r
+\r
+/**\r
+ * UDP support on or off\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define UIP_CONF_UDP 0\r
+\r
+/**\r
+ * UDP checksums on or off\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define UIP_CONF_UDP_CHECKSUMS 1\r
+\r
+/**\r
+ * uIP statistics on or off\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define UIP_CONF_STATISTICS 1\r
+\r
+/* Here we include the header file for the application(s) we use in\r
+ our project. */\r
+/*#include "smtp.h"*/\r
+/*#include "hello-world.h"*/\r
+/*#include "telnetd.h"*/\r
+#include "webserver.h"\r
+/*#include "dhcpc.h"*/\r
+/*#include "resolv.h"*/\r
+/*#include "webclient.h"*/\r
+\r
+#define UIP_CONF_EXTERNAL_BUFFER\r
+\r
+#endif /* __UIP_CONF_H__ */\r
+\r
+/** @} */\r
+/** @} */\r
--- /dev/null
+/*\r
+ * Copyright (c) 2002, Adam Dunkels.\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ * 1. Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above\r
+ * copyright notice, this list of conditions and the following\r
+ * disclaimer in the documentation and/or other materials provided\r
+ * with the distribution.\r
+ * 3. The name of the author may not be used to endorse or promote\r
+ * products derived from this software without specific prior\r
+ * written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS\r
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\r
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY\r
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE\r
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\r
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\r
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * This file is part of the uIP TCP/IP stack\r
+ *\r
+ * $Id: webserver.h,v 1.2 2006/06/11 21:46:38 adam Exp $\r
+ *\r
+ */\r
+#ifndef __WEBSERVER_H__\r
+#define __WEBSERVER_H__\r
+\r
+#include "httpd.h"\r
+\r
+typedef struct httpd_state uip_tcp_appstate_t;\r
+/* UIP_APPCALL: the name of the application function. This function\r
+ must return void and take no arguments (i.e., C type "void\r
+ appfunc(void)"). */\r
+#ifndef UIP_APPCALL\r
+#define UIP_APPCALL httpd_appcall\r
+#endif\r
+\r
+\r
+#endif /* __WEBSERVER_H__ */\r
--- /dev/null
+/*\r
+ FreeRTOS.org V4.3.0 - Copyright (C) 2003-2007 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS.org distribution.\r
+\r
+ FreeRTOS.org is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS.org is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS.org; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS.org, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section\r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license\r
+ and contact details. Please ensure to read the configuration and relevant\r
+ port sections of the online documentation.\r
+\r
+ Also see http://www.SafeRTOS.com for an IEC 61508 compliant version along\r
+ with commercial development and support options.\r
+ ***************************************************************************\r
+*/\r
+\r
+#ifndef FREERTOS_CONFIG_H\r
+#define FREERTOS_CONFIG_H\r
+\r
+/*-----------------------------------------------------------\r
+ * Application specific definitions.\r
+ *\r
+ * These definitions should be adjusted for your particular hardware and\r
+ * application requirements.\r
+ *\r
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE\r
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.\r
+ *----------------------------------------------------------*/\r
+\r
+#define configUSE_PREEMPTION 1\r
+#define configUSE_IDLE_HOOK 0\r
+#define configUSE_TICK_HOOK 0\r
+#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 50000000 )\r
+#define configTICK_RATE_HZ ( ( portTickType ) 1000 )\r
+#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 70 )\r
+#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 12000 ) )\r
+#define configMAX_TASK_NAME_LEN ( 12 )\r
+#define configUSE_TRACE_FACILITY 1\r
+#define configUSE_16_BIT_TICKS 0\r
+#define configIDLE_SHOULD_YIELD 0\r
+#define configUSE_CO_ROUTINES 0\r
+\r
+#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 5 )\r
+#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )\r
+\r
+/* Set the following definitions to 1 to include the API function, or zero\r
+to exclude the API function. */\r
+\r
+#define INCLUDE_vTaskPrioritySet 1\r
+#define INCLUDE_uxTaskPriorityGet 0\r
+#define INCLUDE_vTaskDelete 1\r
+#define INCLUDE_vTaskCleanUpResources 0\r
+#define INCLUDE_vTaskSuspend 1\r
+#define INCLUDE_vTaskDelayUntil 1\r
+#define INCLUDE_vTaskDelay 1\r
+\r
+\r
+#define configKERNEL_INTERRUPT_PRIORITY 255\r
+\r
+\r
+#endif /* FREERTOS_CONFIG_H */\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// LM3Sxxx.h - Header file for Luminary Micro LM3Sxxx microcontrollers.\r
+//\r
+// Copyright (c) 2006-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __LM3SXXX_H__\r
+#define __LM3SXXX_H__\r
+\r
+#include "hw_adc.h"\r
+#include "hw_comp.h"\r
+#include "hw_flash.h"\r
+#include "hw_gpio.h"\r
+#include "hw_i2c.h"\r
+#include "hw_ints.h"\r
+#include "hw_memmap.h"\r
+#include "hw_nvic.h"\r
+#include "hw_pwm.h"\r
+#include "hw_qei.h"\r
+#include "hw_ssi.h"\r
+#include "hw_sysctl.h"\r
+#include "hw_timer.h"\r
+#include "hw_types.h"\r
+#include "hw_uart.h"\r
+#include "hw_watchdog.h"\r
+#include "adc.h"\r
+#include "comp.h"\r
+#include "cpu.h"\r
+#include "debug.h"\r
+#include "flash.h"\r
+#include "gpio.h"\r
+#include "i2c.h"\r
+#include "interrupt.h"\r
+#include "pwm.h"\r
+#include "qei.h"\r
+#include "ssi.h"\r
+#include "sysctl.h"\r
+#include "systick.h"\r
+#include "timer.h"\r
+#include "uart.h"\r
+#include "watchdog.h"\r
+\r
+#endif // __LM3SXXX_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// LM3Sxxxx.h - Header file for Luminary Micro LM3Sxxxx microcontrollers.\r
+//\r
+// Copyright (c) 2006-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __LM3SXXXX_H__\r
+#define __LM3SXXXX_H__\r
+\r
+#include "hw_adc.h"\r
+#include "hw_can.h"\r
+#include "hw_comp.h"\r
+#include "hw_ethernet.h"\r
+#include "hw_flash.h"\r
+#include "hw_gpio.h"\r
+#include "hw_hibernate.h"\r
+#include "hw_i2c.h"\r
+#include "hw_ints.h"\r
+#include "hw_memmap.h"\r
+#include "hw_nvic.h"\r
+#include "hw_pwm.h"\r
+#include "hw_qei.h"\r
+#include "hw_ssi.h"\r
+#include "hw_sysctl.h"\r
+#include "hw_timer.h"\r
+#include "hw_types.h"\r
+#include "hw_uart.h"\r
+#include "hw_watchdog.h"\r
+#include "adc.h"\r
+#include "can.h"\r
+#include "comp.h"\r
+#include "cpu.h"\r
+#include "debug.h"\r
+#include "ethernet.h"\r
+#include "flash.h"\r
+#include "gpio.h"\r
+#include "hibernate.h"\r
+#include "i2c.h"\r
+#include "interrupt.h"\r
+#include "pwm.h"\r
+#include "qei.h"\r
+#include "ssi.h"\r
+#include "sysctl.h"\r
+#include "systick.h"\r
+#include "timer.h"\r
+#include "uart.h"\r
+#include "watchdog.h"\r
+\r
+#endif // __LM3SXXXX_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// flash.h - Prototypes for the flash driver.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __FLASH_H__\r
+#define __FLASH_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to FlashProtectSet(), and returned by\r
+// FlashProtectGet().\r
+//\r
+//*****************************************************************************\r
+typedef enum\r
+{\r
+ FlashReadWrite, // Flash can be read and written\r
+ FlashReadOnly, // Flash can only be read\r
+ FlashExecuteOnly // Flash can only be executed\r
+}\r
+tFlashProtection;\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+extern unsigned long FlashUsecGet(void);\r
+extern void FlashUsecSet(unsigned long ulClocks);\r
+extern long FlashErase(unsigned long ulAddress);\r
+extern long FlashProgram(unsigned long *pulData, unsigned long ulAddress,\r
+ unsigned long ulCount);\r
+extern tFlashProtection FlashProtectGet(unsigned long ulAddress);\r
+extern long FlashProtectSet(unsigned long ulAddress,\r
+ tFlashProtection eProtect);\r
+extern long FlashProtectSave(void);\r
+extern long FlashUserGet(unsigned long *pulUser0, unsigned long *pulUser1);\r
+extern long FlashUserSet(unsigned long ulUser0, unsigned long ulUser1);\r
+extern long FlashUserSave(void);\r
+extern void FlashIntRegister(void (*pfnHandler)(void));\r
+extern void FlashIntUnregister(void);\r
+extern void FlashIntEnable(unsigned long ulIntFlags);\r
+extern void FlashIntDisable(unsigned long ulIntFlags);\r
+extern unsigned long FlashIntGetStatus(tBoolean bMasked);\r
+extern void FlashIntClear(unsigned long ulIntFlags);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __FLASH_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// timer.h - Prototypes for the timer module\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __TIMER_H__\r
+#define __TIMER_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to TimerConfigure as the ulConfig parameter.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_CFG_32_BIT_OS 0x00000001 // 32-bit one-shot timer\r
+#define TIMER_CFG_32_BIT_PER 0x00000002 // 32-bit periodic timer\r
+#define TIMER_CFG_32_RTC 0x01000000 // 32-bit RTC timer\r
+#define TIMER_CFG_16_BIT_PAIR 0x04000000 // Two 16-bit timers\r
+#define TIMER_CFG_A_ONE_SHOT 0x00000001 // Timer A one-shot timer\r
+#define TIMER_CFG_A_PERIODIC 0x00000002 // Timer A periodic timer\r
+#define TIMER_CFG_A_CAP_COUNT 0x00000003 // Timer A event counter\r
+#define TIMER_CFG_A_CAP_TIME 0x00000007 // Timer A event timer\r
+#define TIMER_CFG_A_PWM 0x0000000A // Timer A PWM output\r
+#define TIMER_CFG_B_ONE_SHOT 0x00000100 // Timer B one-shot timer\r
+#define TIMER_CFG_B_PERIODIC 0x00000200 // Timer B periodic timer\r
+#define TIMER_CFG_B_CAP_COUNT 0x00000300 // Timer B event counter\r
+#define TIMER_CFG_B_CAP_TIME 0x00000700 // Timer B event timer\r
+#define TIMER_CFG_B_PWM 0x00000A00 // Timer B PWM output\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to TimerIntEnable, TimerIntDisable, and\r
+// TimerIntClear as the ulIntFlags parameter, and returned from TimerIntStatus.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_CAPB_EVENT 0x00000400 // CaptureB event interrupt\r
+#define TIMER_CAPB_MATCH 0x00000200 // CaptureB match interrupt\r
+#define TIMER_TIMB_TIMEOUT 0x00000100 // TimerB time out interrupt\r
+#define TIMER_RTC_MATCH 0x00000008 // RTC interrupt mask\r
+#define TIMER_CAPA_EVENT 0x00000004 // CaptureA event interrupt\r
+#define TIMER_CAPA_MATCH 0x00000002 // CaptureA match interrupt\r
+#define TIMER_TIMA_TIMEOUT 0x00000001 // TimerA time out interrupt\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to TimerControlEvent as the ulEvent parameter.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_EVENT_POS_EDGE 0x00000000 // Count positive edges\r
+#define TIMER_EVENT_NEG_EDGE 0x00000404 // Count negative edges\r
+#define TIMER_EVENT_BOTH_EDGES 0x00000C0C // Count both edges\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to most of the timer APIs as the ulTimer\r
+// parameter.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_A 0x000000ff // Timer A\r
+#define TIMER_B 0x0000ff00 // Timer B\r
+#define TIMER_BOTH 0x0000ffff // Timer Both\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+extern void TimerEnable(unsigned long ulBase, unsigned long ulTimer);\r
+extern void TimerDisable(unsigned long ulBase, unsigned long ulTimer);\r
+extern void TimerConfigure(unsigned long ulBase, unsigned long ulConfig);\r
+extern void TimerControlLevel(unsigned long ulBase, unsigned long ulTimer,\r
+ tBoolean bInvert);\r
+extern void TimerControlTrigger(unsigned long ulBase, unsigned long ulTimer,\r
+ tBoolean bEnable);\r
+extern void TimerControlEvent(unsigned long ulBase, unsigned long ulTimer,\r
+ unsigned long ulEvent);\r
+extern void TimerControlStall(unsigned long ulBase, unsigned long ulTimer,\r
+ tBoolean bStall);\r
+extern void TimerRTCEnable(unsigned long ulBase);\r
+extern void TimerRTCDisable(unsigned long ulBase);\r
+extern void TimerPrescaleSet(unsigned long ulBase, unsigned long ulTimer,\r
+ unsigned long ulValue);\r
+extern unsigned long TimerPrescaleGet(unsigned long ulBase,\r
+ unsigned long ulTimer);\r
+extern void TimerPrescaleMatchSet(unsigned long ulBase, unsigned long ulTimer,\r
+ unsigned long ulValue);\r
+extern unsigned long TimerPrescaleMatchGet(unsigned long ulBase,\r
+ unsigned long ulTimer);\r
+extern void TimerLoadSet(unsigned long ulBase, unsigned long ulTimer,\r
+ unsigned long ulValue);\r
+extern unsigned long TimerLoadGet(unsigned long ulBase, unsigned long ulTimer);\r
+extern unsigned long TimerValueGet(unsigned long ulBase,\r
+ unsigned long ulTimer);\r
+extern void TimerMatchSet(unsigned long ulBase, unsigned long ulTimer,\r
+ unsigned long ulValue);\r
+extern unsigned long TimerMatchGet(unsigned long ulBase,\r
+ unsigned long ulTimer);\r
+extern void TimerIntRegister(unsigned long ulBase, unsigned long ulTimer,\r
+ void (*pfnHandler)(void));\r
+extern void TimerIntUnregister(unsigned long ulBase, unsigned long ulTimer);\r
+extern void TimerIntEnable(unsigned long ulBase, unsigned long ulIntFlags);\r
+extern void TimerIntDisable(unsigned long ulBase, unsigned long ulIntFlags);\r
+extern unsigned long TimerIntStatus(unsigned long ulBase, tBoolean bMasked);\r
+extern void TimerIntClear(unsigned long ulBase, unsigned long ulIntFlags);\r
+extern void TimerQuiesce(unsigned long ulBase);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __TIMER_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// adc.h - ADC headers for using the ADC driver functions.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __ADC_H__\r
+#define __ADC_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to ADCSequenceConfigure as the ulTrigger\r
+// parameter.\r
+//\r
+//*****************************************************************************\r
+#define ADC_TRIGGER_PROCESSOR 0x00000000 // Processor event\r
+#define ADC_TRIGGER_COMP0 0x00000001 // Analog comparator 0 event\r
+#define ADC_TRIGGER_COMP1 0x00000002 // Analog comparator 1 event\r
+#define ADC_TRIGGER_COMP2 0x00000003 // Analog comparator 2 event\r
+#define ADC_TRIGGER_EXTERNAL 0x00000004 // External event\r
+#define ADC_TRIGGER_TIMER 0x00000005 // Timer event\r
+#define ADC_TRIGGER_PWM0 0x00000006 // PWM0 event\r
+#define ADC_TRIGGER_PWM1 0x00000007 // PWM1 event\r
+#define ADC_TRIGGER_PWM2 0x00000008 // PWM2 event\r
+#define ADC_TRIGGER_ALWAYS 0x0000000F // Always event\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to ADCSequenceStepConfigure as the ulConfig\r
+// parameter.\r
+//\r
+//*****************************************************************************\r
+#define ADC_CTL_TS 0x00000080 // Temperature sensor select\r
+#define ADC_CTL_IE 0x00000040 // Interrupt enable\r
+#define ADC_CTL_END 0x00000020 // Sequence end select\r
+#define ADC_CTL_D 0x00000010 // Differential select\r
+#define ADC_CTL_CH0 0x00000000 // Input channel 0\r
+#define ADC_CTL_CH1 0x00000001 // Input channel 1\r
+#define ADC_CTL_CH2 0x00000002 // Input channel 2\r
+#define ADC_CTL_CH3 0x00000003 // Input channel 3\r
+#define ADC_CTL_CH4 0x00000004 // Input channel 4\r
+#define ADC_CTL_CH5 0x00000005 // Input channel 5\r
+#define ADC_CTL_CH6 0x00000006 // Input channel 6\r
+#define ADC_CTL_CH7 0x00000007 // Input channel 7\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+extern void ADCIntRegister(unsigned long ulBase, unsigned long ulSequenceNum,\r
+ void (*pfnHandler)(void));\r
+extern void ADCIntUnregister(unsigned long ulBase,\r
+ unsigned long ulSequenceNum);\r
+extern void ADCIntDisable(unsigned long ulBase, unsigned long ulSequenceNum);\r
+extern void ADCIntEnable(unsigned long ulBase, unsigned long ulSequenceNum);\r
+extern unsigned long ADCIntStatus(unsigned long ulBase,\r
+ unsigned long ulSequenceNum,\r
+ tBoolean bMasked);\r
+extern void ADCIntClear(unsigned long ulBase, unsigned long ulSequenceNum);\r
+extern void ADCSequenceEnable(unsigned long ulBase,\r
+ unsigned long ulSequenceNum);\r
+extern void ADCSequenceDisable(unsigned long ulBase,\r
+ unsigned long ulSequenceNum);\r
+extern void ADCSequenceConfigure(unsigned long ulBase,\r
+ unsigned long ulSequenceNum,\r
+ unsigned long ulTrigger,\r
+ unsigned long ulPriority);\r
+extern void ADCSequenceStepConfigure(unsigned long ulBase,\r
+ unsigned long ulSequenceNum,\r
+ unsigned long ulStep,\r
+ unsigned long ulConfig);\r
+extern long ADCSequenceOverflow(unsigned long ulBase,\r
+ unsigned long ulSequenceNum);\r
+extern void ADCSequenceOverflowClear(unsigned long ulBase,\r
+ unsigned long ulSequenceNum);\r
+extern long ADCSequenceUnderflow(unsigned long ulBase,\r
+ unsigned long ulSequenceNum);\r
+extern void ADCSequenceUnderflowClear(unsigned long ulBase,\r
+ unsigned long ulSequenceNum);\r
+extern long ADCSequenceDataGet(unsigned long ulBase,\r
+ unsigned long ulSequenceNum,\r
+ unsigned long *pulBuffer);\r
+extern void ADCProcessorTrigger(unsigned long ulBase,\r
+ unsigned long ulSequenceNum);\r
+extern void ADCSoftwareOversampleConfigure(unsigned long ulBase,\r
+ unsigned long ulSequenceNum,\r
+ unsigned long ulFactor);\r
+extern void ADCSoftwareOversampleStepConfigure(unsigned long ulBase,\r
+ unsigned long ulSequenceNum,\r
+ unsigned long ulStep,\r
+ unsigned long ulConfig);\r
+extern void ADCSoftwareOversampleDataGet(unsigned long ulBase,\r
+ unsigned long ulSequenceNum,\r
+ unsigned long *pulBuffer,\r
+ unsigned long ulCount);\r
+extern void ADCHardwareOversampleConfigure(unsigned long ulBase,\r
+ unsigned long ulFactor);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __ADC_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// can.h - Defines and Macros for the CAN controller.\r
+//\r
+// Copyright (c) 2006-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __CAN_H__\r
+#define __CAN_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! \addtogroup can_api\r
+//! @{\r
+//\r
+//*****************************************************************************\r
+\r
+//*****************************************************************************\r
+//\r
+// Miscellaneous defines for Message ID Types\r
+//\r
+//*****************************************************************************\r
+\r
+//*****************************************************************************\r
+//\r
+//! These are the flags used by the tCANMsgObject variable when calling the\r
+//! the CANMessageSet() and CANMessageGet() APIs.\r
+//\r
+//*****************************************************************************\r
+typedef enum\r
+{\r
+ //\r
+ //! This indicates that transmit interrupts should be enabled, or are\r
+ //! enabled.\r
+ //\r
+ MSG_OBJ_TX_INT_ENABLE = 0x00000001,\r
+\r
+ //\r
+ //! This indicates that receive interrupts should be enabled or are\r
+ //! enabled.\r
+ //\r
+ MSG_OBJ_RX_INT_ENABLE = 0x00000002,\r
+\r
+ //\r
+ //! This indicates that a message object will use or is using an extended\r
+ //! identifier.\r
+ //\r
+ MSG_OBJ_EXTENDED_ID = 0x00000004,\r
+\r
+ //\r
+ //! This indicates that a message object will use or is using filtering\r
+ //! based on the object's message Identifier.\r
+ //\r
+ MSG_OBJ_USE_ID_FILTER = 0x00000008,\r
+\r
+ //\r
+ //! This indicates that new data was available in the message object.\r
+ //\r
+ MSG_OBJ_NEW_DATA = 0x00000080,\r
+\r
+ //\r
+ //! This indicates that data was lost since this message object was last\r
+ //! read.\r
+ //\r
+ MSG_OBJ_DATA_LOST = 0x00000100,\r
+\r
+ //\r
+ //! This indicates that a message object will use or is using filtering\r
+ //! based on the direction of the transfer. If the direction filtering is\r
+ //! used then ID filtering must also be enabled.\r
+ //\r
+ MSG_OBJ_USE_DIR_FILTER = (0x00000010 | MSG_OBJ_USE_ID_FILTER),\r
+\r
+ //\r
+ //! This indicates that a message object will use or is using message\r
+ //! identifier filtering based of the the extended identifier.\r
+ //! If the extended identifier filtering is used then ID filtering must\r
+ //! also be enabled.\r
+ //\r
+ MSG_OBJ_USE_EXT_FILTER = (0x00000020 | MSG_OBJ_USE_ID_FILTER),\r
+\r
+ //\r
+ //! This indicates that a message object is a remote frame.\r
+ //\r
+ MSG_OBJ_REMOTE_FRAME = 0x00000040,\r
+\r
+ //\r
+ //! This indicates that a message object has no flags set.\r
+ //\r
+ MSG_OBJ_NO_FLAGS = 0x00000000\r
+}\r
+tCANObjFlags;\r
+\r
+//*****************************************************************************\r
+//\r
+//! This define is used with the #tCANObjFlags enumerated values to allow\r
+//! checking only status flags and not configuration flags.\r
+//\r
+//*****************************************************************************\r
+#define MSG_OBJ_STATUS_MASK (MSG_OBJ_NEW_DATA | MSG_OBJ_DATA_LOST)\r
+\r
+//*****************************************************************************\r
+//\r
+//! This structure used for encapsulating all the items associated with a CAN\r
+//! message object in the CAN controller.\r
+//\r
+//*****************************************************************************\r
+typedef struct\r
+{\r
+ //\r
+ //! The CAN message identifier used for 11 or 29 bit identifiers.\r
+ //\r
+ unsigned long ulMsgID;\r
+\r
+ //\r
+ //! The message identifier mask used when identifier filtering is enabled.\r
+ //\r
+ unsigned long ulMsgIDMask;\r
+\r
+ //\r
+ //! This value holds various status flags and settings specified by\r
+ //! tCANObjFlags.\r
+ //\r
+ unsigned long ulFlags;\r
+\r
+ //\r
+ //! This value is the number of bytes of data in the message object.\r
+ //\r
+ unsigned long ulMsgLen;\r
+\r
+ //\r
+ //! This is a pointer to the message object's data.\r
+ //\r
+ unsigned char *pucMsgData;\r
+}\r
+tCANMsgObject;\r
+\r
+//*****************************************************************************\r
+//\r
+//! This structure is used for encapsulating the values associated with setting\r
+//! up the bit timing for a CAN controller. The structure is used when calling\r
+//! the CANGetBitTiming and CANSetBitTiming functions.\r
+//\r
+//*****************************************************************************\r
+typedef struct\r
+{\r
+ //\r
+ //! This value holds the sum of the Synchronization, Propagation, and Phase\r
+ //! Buffer 1 segments, measured in time quanta. The valid values for this\r
+ //! setting range from 2 to 16.\r
+ //\r
+ unsigned int uSyncPropPhase1Seg;\r
+\r
+ //\r
+ //! This value holds the Phase Buffer 2 segment in time quanta. The valid\r
+ //! values for this setting range from 1 to 8.\r
+ //\r
+ unsigned int uPhase2Seg;\r
+\r
+ //\r
+ //! This value holds the Resynchronization Jump Width in time quanta. The\r
+ //! valid values for this setting range from 1 to 4.\r
+ //\r
+ unsigned int uSJW;\r
+\r
+ //\r
+ //! This value holds the CAN_CLK divider used to determine time quanta.\r
+ //! The valid values for this setting range from 1 to 1023.\r
+ //\r
+ unsigned int uQuantumPrescaler;\r
+\r
+}\r
+tCANBitClkParms;\r
+\r
+//*****************************************************************************\r
+//\r
+//! This data type is used to identify the interrupt status register. This is\r
+//! used when calling the a CANIntStatus() function.\r
+//\r
+//*****************************************************************************\r
+typedef enum\r
+{\r
+ //\r
+ //! Read the CAN interrupt status information.\r
+ //\r
+ CAN_INT_STS_CAUSE,\r
+\r
+ //\r
+ //! Read a message object's interrupt status.\r
+ //\r
+ CAN_INT_STS_OBJECT\r
+}\r
+tCANIntStsReg;\r
+\r
+//*****************************************************************************\r
+//\r
+//! This data type is used to identify which of the several status registers\r
+//! to read when calling the CANStatusGet() function.\r
+//\r
+//*****************************************************************************\r
+typedef enum\r
+{\r
+ //\r
+ //! Read the full CAN controller status.\r
+ //\r
+ CAN_STS_CONTROL,\r
+\r
+ //\r
+ //! Read the full 32 bit mask of message objects with a transmit request\r
+ //! set.\r
+ //\r
+ CAN_STS_TXREQUEST,\r
+\r
+ //\r
+ //! Read the full 32 bit mask of message objects with a new data available.\r
+ //\r
+ CAN_STS_NEWDAT,\r
+\r
+ //\r
+ //! Read the full 32 bit mask of message objects that are enabled.\r
+ //\r
+ CAN_STS_MSGVAL\r
+}\r
+tCANStsReg;\r
+\r
+//*****************************************************************************\r
+//\r
+//! These definitions are used to specify interrupt sources to CANIntEnable()\r
+//! and CANIntDisable().\r
+//\r
+//*****************************************************************************\r
+typedef enum\r
+{\r
+ //\r
+ //! This flag is used to allow a CAN controller to generate error\r
+ //! interrupts.\r
+ //\r
+ CAN_INT_ERROR = 0x00000008,\r
+\r
+ //\r
+ //! This flag is used to allow a CAN controller to generate status\r
+ //! interrupts.\r
+ //\r
+ CAN_INT_STATUS = 0x00000004,\r
+\r
+ //\r
+ //! This flag is used to allow a CAN controller to generate any CAN\r
+ //! interrupts. If this is not set then no interrupts will be generated by\r
+ //! the CAN controller.\r
+ //\r
+ CAN_INT_MASTER = 0x00000002\r
+}\r
+tCANIntFlags;\r
+\r
+//*****************************************************************************\r
+//\r
+//! This definition is used to determine the type of message object that will\r
+//! be set up via a call to the CANMessageSet() API.\r
+//\r
+//*****************************************************************************\r
+typedef enum\r
+{\r
+ //\r
+ //! Transmit message object.\r
+ //\r
+ MSG_OBJ_TYPE_TX,\r
+\r
+ //\r
+ //! Transmit remote request message object\r
+ //\r
+ MSG_OBJ_TYPE_TX_REMOTE,\r
+\r
+ //\r
+ //! Receive message object.\r
+ //\r
+ MSG_OBJ_TYPE_RX,\r
+\r
+ //\r
+ //! Receive remote request message object.\r
+ //\r
+ MSG_OBJ_TYPE_RX_REMOTE,\r
+\r
+ //\r
+ //! Remote frame receive remote, with auto-transmit message object.\r
+ //\r
+ MSG_OBJ_TYPE_RXTX_REMOTE\r
+}\r
+tMsgObjType;\r
+\r
+//*****************************************************************************\r
+//\r
+//! The following enumeration contains all error or status indicators that\r
+//! can be returned when calling the CANStatusGet() API.\r
+//\r
+//*****************************************************************************\r
+typedef enum\r
+{\r
+ //\r
+ //! CAN controller has entered a Bus Off state.\r
+ //\r
+ CAN_STATUS_BUS_OFF = 0x00000080,\r
+\r
+ //\r
+ //! CAN controller error level has reached warning level.\r
+ //\r
+ CAN_STATUS_EWARN = 0x00000040,\r
+\r
+ //\r
+ //! CAN controller error level has reached error passive level.\r
+ //\r
+ CAN_STATUS_EPASS = 0x00000020,\r
+\r
+ //\r
+ //! A message was received successfully since the last read of this status.\r
+ //\r
+ CAN_STATUS_RXOK = 0x00000010,\r
+\r
+ //\r
+ //! A message was transmitted successfully since the last read of this\r
+ //! status.\r
+ //\r
+ CAN_STATUS_TXOK = 0x00000008,\r
+\r
+ //\r
+ //! This is the mask for the last error code field.\r
+ //\r
+ CAN_STATUS_LEC_MSK = 0x00000007,\r
+\r
+ //\r
+ //! There was no error.\r
+ //\r
+ CAN_STATUS_LEC_NONE = 0x00000000,\r
+\r
+ //\r
+ //! A bit stuffing error has occurred.\r
+ //\r
+ CAN_STATUS_LEC_STUFF = 0x00000001,\r
+\r
+ //\r
+ //! A formatting error has occurred.\r
+ //\r
+ CAN_STATUS_LEC_FORM = 0x00000002,\r
+\r
+ //\r
+ //! An acknowledge error has occurred.\r
+ //\r
+ CAN_STATUS_LEC_ACK = 0x00000003,\r
+\r
+ //\r
+ //! The bus remained a bit level of 1 for longer than is allowed.\r
+ //\r
+ CAN_STATUS_LEC_BIT1 = 0x00000004,\r
+\r
+ //\r
+ //! The bus remained a bit level of 0 for longer than is allowed.\r
+ //\r
+ CAN_STATUS_LEC_BIT0 = 0x00000005,\r
+\r
+ //\r
+ //! A CRC error has occurred.\r
+ //\r
+ CAN_STATUS_LEC_CRC = 0x00000006,\r
+\r
+ //\r
+ //! This is the mask for the CAN Last Error Code (LEC).\r
+ //\r
+ CAN_STATUS_LEC_MASK = 0x00000007\r
+}\r
+tCANStatusCtrl;\r
+\r
+//*****************************************************************************\r
+//\r
+// API Function prototypes\r
+//\r
+//*****************************************************************************\r
+extern void CANInit(unsigned long ulBase);\r
+extern void CANEnable(unsigned long ulBase);\r
+extern void CANDisable(unsigned long ulBase);\r
+extern void CANSetBitTiming(unsigned long ulBase, tCANBitClkParms *pClkParms);\r
+extern void CANGetBitTiming(unsigned long ulBase, tCANBitClkParms *pClkParms);\r
+extern unsigned long CANReadReg(unsigned long ulRegAddress);\r
+extern void CANWriteReg(unsigned long ulRegAddress, unsigned long ulRegValue);\r
+extern void CANMessageSet(unsigned long ulBase, unsigned long ulObjID,\r
+ tCANMsgObject *pMsgObject, tMsgObjType eMsgType);\r
+extern void CANMessageGet(unsigned long ulBase, unsigned long ulObjID,\r
+ tCANMsgObject *pMsgObject, tBoolean bClrPendingInt);\r
+extern unsigned long CANStatusGet(unsigned long ulBase, tCANStsReg eStatusReg);\r
+extern void CANMessageClear(unsigned long ulBase, unsigned long ulObjID);\r
+extern void CANIntRegister(unsigned long ulBase, void (*pfnHandler)(void));\r
+extern void CANIntEnable(unsigned long ulBase, unsigned long ulIntFlags);\r
+extern void CANIntDisable(unsigned long ulBase, unsigned long ulIntFlags);\r
+extern void CANIntClear(unsigned long ulBase, unsigned long ulIntClr);\r
+extern unsigned long CANIntStatus(unsigned long ulBase,\r
+ tCANIntStsReg eIntStsReg);\r
+extern tBoolean CANRetryGet(unsigned long ulBase);\r
+extern void CANRetrySet(unsigned long ulBase, tBoolean bAutoRetry);\r
+extern tBoolean CANErrCntrGet(unsigned long ulBase, unsigned long *pulRxCount,\r
+ unsigned long *pulTxCount);\r
+extern long CANGetIntNumber(unsigned long ulBase);\r
+extern void CANReadDataReg(unsigned char *pucData, unsigned long *pulRegister,\r
+ int iSize);\r
+extern void CANWriteDataReg(unsigned char *pucData, unsigned long *pulRegister,\r
+ int iSize);\r
+\r
+//*****************************************************************************\r
+//\r
+// Close the Doxygen group.\r
+//! @}\r
+//\r
+//*****************************************************************************\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __CAN_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// comp.h - Prototypes for the analog comparator driver.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __COMP_H__\r
+#define __COMP_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to ComparatorConfigure() as the ulConfig\r
+// parameter. For each group (i.e. COMP_TRIG_xxx, COMP_INT_xxx, etc.), one of\r
+// the values may be selected and ORed together will values from the other\r
+// groups.\r
+//\r
+//*****************************************************************************\r
+#define COMP_TRIG_NONE 0x00000000 // No ADC trigger\r
+#define COMP_TRIG_HIGH 0x00000880 // Trigger when high\r
+#define COMP_TRIG_LOW 0x00000800 // Trigger when low\r
+#define COMP_TRIG_FALL 0x00000820 // Trigger on falling edge\r
+#define COMP_TRIG_RISE 0x00000840 // Trigger on rising edge\r
+#define COMP_TRIG_BOTH 0x00000860 // Trigger on both edges\r
+#define COMP_INT_HIGH 0x00000010 // Interrupt when high\r
+#define COMP_INT_LOW 0x00000000 // Interrupt when low\r
+#define COMP_INT_FALL 0x00000004 // Interrupt on falling edge\r
+#define COMP_INT_RISE 0x00000008 // Interrupt on rising edge\r
+#define COMP_INT_BOTH 0x0000000C // Interrupt on both edges\r
+#define COMP_ASRCP_PIN 0x00000000 // Dedicated Comp+ pin\r
+#define COMP_ASRCP_PIN0 0x00000200 // Comp0+ pin\r
+#define COMP_ASRCP_REF 0x00000400 // Internal voltage reference\r
+#ifndef DEPRECATED\r
+#define COMP_OUTPUT_NONE 0x00000000 // No comparator output\r
+#endif\r
+#define COMP_OUTPUT_NORMAL 0x00000000 // Comparator output normal\r
+#define COMP_OUTPUT_INVERT 0x00000002 // Comparator output inverted\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to ComparatorSetRef() as the ulRef parameter.\r
+//\r
+//*****************************************************************************\r
+#define COMP_REF_OFF 0x00000000 // Turn off the internal reference\r
+#define COMP_REF_0V 0x00000300 // Internal reference of 0V\r
+#define COMP_REF_0_1375V 0x00000301 // Internal reference of 0.1375V\r
+#define COMP_REF_0_275V 0x00000302 // Internal reference of 0.275V\r
+#define COMP_REF_0_4125V 0x00000303 // Internal reference of 0.4125V\r
+#define COMP_REF_0_55V 0x00000304 // Internal reference of 0.55V\r
+#define COMP_REF_0_6875V 0x00000305 // Internal reference of 0.6875V\r
+#define COMP_REF_0_825V 0x00000306 // Internal reference of 0.825V\r
+#define COMP_REF_0_928125V 0x00000201 // Internal reference of 0.928125V\r
+#define COMP_REF_0_9625V 0x00000307 // Internal reference of 0.9625V\r
+#define COMP_REF_1_03125V 0x00000202 // Internal reference of 1.03125V\r
+#define COMP_REF_1_134375V 0x00000203 // Internal reference of 1.134375V\r
+#define COMP_REF_1_1V 0x00000308 // Internal reference of 1.1V\r
+#define COMP_REF_1_2375V 0x00000309 // Internal reference of 1.2375V\r
+#define COMP_REF_1_340625V 0x00000205 // Internal reference of 1.340625V\r
+#define COMP_REF_1_375V 0x0000030A // Internal reference of 1.375V\r
+#define COMP_REF_1_44375V 0x00000206 // Internal reference of 1.44375V\r
+#define COMP_REF_1_5125V 0x0000030B // Internal reference of 1.5125V\r
+#define COMP_REF_1_546875V 0x00000207 // Internal reference of 1.546875V\r
+#define COMP_REF_1_65V 0x0000030C // Internal reference of 1.65V\r
+#define COMP_REF_1_753125V 0x00000209 // Internal reference of 1.753125V\r
+#define COMP_REF_1_7875V 0x0000030D // Internal reference of 1.7875V\r
+#define COMP_REF_1_85625V 0x0000020A // Internal reference of 1.85625V\r
+#define COMP_REF_1_925V 0x0000030E // Internal reference of 1.925V\r
+#define COMP_REF_1_959375V 0x0000020B // Internal reference of 1.959375V\r
+#define COMP_REF_2_0625V 0x0000030F // Internal reference of 2.0625V\r
+#define COMP_REF_2_165625V 0x0000020D // Internal reference of 2.165625V\r
+#define COMP_REF_2_26875V 0x0000020E // Internal reference of 2.26875V\r
+#define COMP_REF_2_371875V 0x0000020F // Internal reference of 2.371875V\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+extern void ComparatorConfigure(unsigned long ulBase, unsigned long ulComp,\r
+ unsigned long ulConfig);\r
+extern void ComparatorRefSet(unsigned long ulBase, unsigned long ulRef);\r
+extern tBoolean ComparatorValueGet(unsigned long ulBase, unsigned long ulComp);\r
+extern void ComparatorIntRegister(unsigned long ulBase, unsigned long ulComp,\r
+ void (*pfnHandler)(void));\r
+extern void ComparatorIntUnregister(unsigned long ulBase,\r
+ unsigned long ulComp);\r
+extern void ComparatorIntEnable(unsigned long ulBase, unsigned long ulComp);\r
+extern void ComparatorIntDisable(unsigned long ulBase, unsigned long ulComp);\r
+extern tBoolean ComparatorIntStatus(unsigned long ulBase, unsigned long ulComp,\r
+ tBoolean bMasked);\r
+extern void ComparatorIntClear(unsigned long ulBase, unsigned long ulComp);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __COMP_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// cpu.h - Prototypes for the CPU instruction wrapper functions.\r
+//\r
+// Copyright (c) 2006-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __CPU_H__\r
+#define __CPU_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes.\r
+//\r
+//*****************************************************************************\r
+extern void CPUcpsid(void);\r
+extern void CPUcpsie(void);\r
+extern void CPUwfi(void);\r
+\r
+#endif // __CPU_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// debug.h - Macros for assisting debug of the driver library.\r
+//\r
+// Copyright (c) 2006-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __DEBUG_H__\r
+#define __DEBUG_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototype for the function that is called when an invalid argument is passed\r
+// to an API. This is only used when doing a DEBUG build.\r
+//\r
+//*****************************************************************************\r
+extern void __error__(char *pcFilename, unsigned long ulLine);\r
+\r
+//*****************************************************************************\r
+//\r
+// The ASSERT macro, which does the actual assertion checking. Typically, this\r
+// will be for procedure arguments.\r
+//\r
+//*****************************************************************************\r
+#ifdef DEBUG\r
+#define ASSERT(expr) { \\r
+ if(!(expr)) \\r
+ { \\r
+ __error__(__FILE__, __LINE__); \\r
+ } \\r
+ }\r
+#else\r
+#define ASSERT(expr)\r
+#endif\r
+\r
+#endif // __DEBUG_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// ethernet.h - Defines and Macros for the ethernet module.\r
+//\r
+// Copyright (c) 2006-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __ETHERNET_H__\r
+#define __ETHERNET_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to EthernetConfigSet as the ulConfig value, and\r
+// returned from EthernetConfigGet.\r
+//\r
+//*****************************************************************************\r
+#define ETH_CFG_RX_BADCRCDIS 0x000800 // Disable RX BAD CRC Packets\r
+#define ETH_CFG_RX_PRMSEN 0x000400 // Enable RX Promiscuous\r
+#define ETH_CFG_RX_AMULEN 0x000200 // Enable RX Multicast\r
+#define ETH_CFG_TX_DPLXEN 0x000010 // Enable TX Duplex Mode\r
+#define ETH_CFG_TX_CRCEN 0x000004 // Enable TX CRC Generation\r
+#define ETH_CFG_TX_PADEN 0x000002 // Enable TX Padding\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to EthernetIntEnable, EthernetIntDisable, and\r
+// EthernetIntClear as the ulIntFlags parameter, and returned from\r
+// EthernetIntStatus.\r
+//\r
+//*****************************************************************************\r
+#define ETH_INT_PHY 0x040 // PHY Event/Interrupt\r
+#define ETH_INT_MDIO 0x020 // Management Transaction\r
+#define ETH_INT_RXER 0x010 // RX Error\r
+#define ETH_INT_RXOF 0x008 // RX FIFO Overrun\r
+#define ETH_INT_TX 0x004 // TX Complete\r
+#define ETH_INT_TXER 0x002 // TX Error\r
+#define ETH_INT_RX 0x001 // RX Complete\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define values that can be passed as register addresses to\r
+// EthernetPHYRead and EthernetPHYWrite.\r
+//\r
+//*****************************************************************************\r
+#define PHY_MR0 0 // Control\r
+#define PHY_MR1 1 // Status\r
+#define PHY_MR2 2 // PHY Identifier 1\r
+#define PHY_MR3 3 // PHY Identifier 2\r
+#define PHY_MR4 4 // Auto-Neg. Advertisement\r
+#define PHY_MR5 5 // Auto-Neg. Link Partner Ability\r
+#define PHY_MR6 6 // Auto-Neg. Expansion\r
+ // 7-15 Reserved/Not Implemented\r
+#define PHY_MR16 16 // Vendor Specific\r
+#define PHY_MR17 17 // Interrupt Control/Status\r
+#define PHY_MR18 18 // Diagnostic Register\r
+#define PHY_MR19 19 // Transceiver Control\r
+ // 20-22 Reserved\r
+#define PHY_MR23 23 // LED Configuration Register\r
+#define PHY_MR24 24 // MDI/MDIX Control Register\r
+ // 25-31 Reserved/Not Implemented\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define bit fields in the ETH_MR0 register\r
+//\r
+//*****************************************************************************\r
+#define PHY_MR0_RESET 0x8000 // Reset the PHY\r
+#define PHY_MR0_LOOPBK 0x4000 // TXD to RXD Loopback\r
+#define PHY_MR0_SPEEDSL 0x2000 // Speed Selection\r
+#define PHY_MR0_SPEEDSL_10 0x0000 // Speed Selection 10BASE-T\r
+#define PHY_MR0_SPEEDSL_100 0x2000 // Speed Selection 100BASE-T\r
+#define PHY_MR0_ANEGEN 0x1000 // Auto-Negotiation Enable\r
+#define PHY_MR0_PWRDN 0x0800 // Power Down\r
+#define PHY_MR0_RANEG 0x0200 // Restart Auto-Negotiation\r
+#define PHY_MR0_DUPLEX 0x0100 // Enable full duplex\r
+#define PHY_MR0_DUPLEX_HALF 0x0000 // Enable half duplex mode\r
+#define PHY_MR0_DUPLEX_FULL 0x0100 // Enable full duplex mode\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define bit fields in the ETH_MR1 register\r
+//\r
+//*****************************************************************************\r
+#define PHY_MR1_ANEGC 0x0020 // Auto-Negotiate Complete\r
+#define PHY_MR1_RFAULT 0x0010 // Remove Fault Detected\r
+#define PHY_MR1_LINK 0x0004 // Link Established\r
+#define PHY_MR1_JAB 0x0002 // Jabber Condition Detected\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define bit fields in the ETH_MR17 register\r
+//\r
+//*****************************************************************************\r
+#define PHY_MR17_RXER_IE 0x4000 // Enable Receive Error Interrupt\r
+#define PHY_MR17_LSCHG_IE 0x0400 // Enable Link Status Change Int.\r
+#define PHY_MR17_ANEGCOMP_IE 0x0100 // Enable Auto-Negotiate Cmpl. Int.\r
+#define PHY_MR17_RXER_INT 0x0040 // Receive Error Interrupt\r
+#define PHY_MR17_LSCHG_INT 0x0004 // Link Status Change Interrupt\r
+#define PHY_MR17_ANEGCOMP_INT 0x0001 // Auto-Negotiate Complete Int.\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define bit fields in the ETH_MR18 register\r
+//\r
+//*****************************************************************************\r
+#define PHY_MR18_ANEGF 0x1000 // Auto-Negotiate Failed\r
+#define PHY_MR18_DPLX 0x0800 // Duplex Mode Negotiated\r
+#define PHY_MR18_DPLX_HALF 0x0000 // Half Duplex Mode Negotiated\r
+#define PHY_MR18_DPLX_FULL 0x0800 // Full Duplex Mode Negotiated\r
+#define PHY_MR18_RATE 0x0400 // Rate Negotiated\r
+#define PHY_MR18_RATE_10 0x0000 // Rate Negotiated is 10BASE-T\r
+#define PHY_MR18_RATE_100 0x0400 // Rate Negotiated is 100BASE-TX\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define bit fields in the ETH_MR23 register\r
+//\r
+//*****************************************************************************\r
+#define PHY_MR23_LED1 0x00f0 // LED1 Configuration\r
+#define PHY_MR23_LED1_LINK 0x0000 // LED1 is Link Status\r
+#define PHY_MR23_LED1_RXTX 0x0010 // LED1 is RX or TX Activity\r
+#define PHY_MR23_LED1_TX 0x0020 // LED1 is TX Activity\r
+#define PHY_MR23_LED1_RX 0x0030 // LED1 is RX Activity\r
+#define PHY_MR23_LED1_COL 0x0040 // LED1 is RX Activity\r
+#define PHY_MR23_LED1_100 0x0050 // LED1 is RX Activity\r
+#define PHY_MR23_LED1_10 0x0060 // LED1 is RX Activity\r
+#define PHY_MR23_LED1_DUPLEX 0x0070 // LED1 is RX Activity\r
+#define PHY_MR23_LED1_LINKACT 0x0080 // LED1 is Link Status + Activity\r
+#define PHY_MR23_LED0 0x000f // LED0 Configuration\r
+#define PHY_MR23_LED0_LINK 0x0000 // LED0 is Link Status\r
+#define PHY_MR23_LED0_RXTX 0x0001 // LED0 is RX or TX Activity\r
+#define PHY_MR23_LED0_TX 0x0002 // LED0 is TX Activity\r
+#define PHY_MR23_LED0_RX 0x0003 // LED0 is RX Activity\r
+#define PHY_MR23_LED0_COL 0x0004 // LED0 is RX Activity\r
+#define PHY_MR23_LED0_100 0x0005 // LED0 is RX Activity\r
+#define PHY_MR23_LED0_10 0x0006 // LED0 is RX Activity\r
+#define PHY_MR23_LED0_DUPLEX 0x0007 // LED0 is RX Activity\r
+#define PHY_MR23_LED0_LINKACT 0x0008 // LED0 is Link Status + Activity\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define bit fields in the ETH_MR24 register\r
+//\r
+//*****************************************************************************\r
+#define PHY_MR24_MDIX 0x0020 // Auto-Switching Configuration\r
+#define PHY_MR24_MDIX_NORMAL 0x0000 // Auto-Switching in passthrough\r
+#define PHY_MR23_MDIX_CROSSOVER 0x0020 // Auto-Switching in crossover\r
+\r
+//*****************************************************************************\r
+//\r
+// Helper Macros for Ethernet Processing\r
+//\r
+//*****************************************************************************\r
+//\r
+// htonl/ntohl - big endian/little endian byte swapping macros for\r
+// 32-bit (long) values\r
+//\r
+//*****************************************************************************\r
+#ifndef htonl\r
+ #define htonl(a) \\r
+ ((((a) >> 24) & 0x000000ff) | \\r
+ (((a) >> 8) & 0x0000ff00) | \\r
+ (((a) << 8) & 0x00ff0000) | \\r
+ (((a) << 24) & 0xff000000))\r
+#endif\r
+\r
+#ifndef ntohl\r
+ #define ntohl(a) htonl((a))\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// htons/ntohs - big endian/little endian byte swapping macros for\r
+// 16-bit (short) values\r
+//\r
+//*****************************************************************************\r
+#ifndef htons\r
+ #define htons(a) \\r
+ ((((a) >> 8) & 0x00ff) | \\r
+ (((a) << 8) & 0xff00))\r
+#endif\r
+\r
+#ifndef ntohs\r
+ #define ntohs(a) htons((a))\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// API Function prototypes\r
+//\r
+//*****************************************************************************\r
+extern void EthernetInit(unsigned long ulBase);\r
+extern void EthernetConfigSet(unsigned long ulBase, unsigned long ulConfig);\r
+extern unsigned long EthernetConfigGet(unsigned long ulBase);\r
+extern void EthernetMACAddrSet(unsigned long ulBase,\r
+ unsigned char *pucMACAddr);\r
+extern void EthernetMACAddrGet(unsigned long ulBase,\r
+ unsigned char *pucMACAddr);\r
+extern void EthernetEnable(unsigned long ulBase);\r
+extern void EthernetDisable(unsigned long ulBase);\r
+extern tBoolean EthernetPacketAvail(unsigned long ulBase);\r
+extern tBoolean EthernetSpaceAvail(unsigned long ulBase);\r
+extern long EthernetPacketNonBlockingGet(unsigned long ulBase,\r
+ unsigned char *pucBuf,\r
+ long lBufLen);\r
+extern long EthernetPacketGet(unsigned long ulBase, unsigned char *pucBuf,\r
+ long lBufLen);\r
+extern long EthernetPacketNonBlockingPut(unsigned long ulBase,\r
+ unsigned char *pucBuf,\r
+ long lBufLen);\r
+extern long EthernetPacketPut(unsigned long ulBase, unsigned char *pucBuf,\r
+ long lBufLen);\r
+extern void EthernetIntRegister(unsigned long ulBase,\r
+ void (*pfnHandler)(void));\r
+extern void EthernetIntUnregister(unsigned long ulBase);\r
+extern void EthernetIntEnable(unsigned long ulBase, unsigned long ulIntFlags);\r
+extern void EthernetIntDisable(unsigned long ulBase, unsigned long ulIntFlags);\r
+extern unsigned long EthernetIntStatus(unsigned long ulBase, tBoolean bMasked);\r
+extern void EthernetIntClear(unsigned long ulBase, unsigned long ulIntFlags);\r
+extern void EthernetPHYWrite(unsigned long ulBase, unsigned char ucRegAddr,\r
+ unsigned long ulData);\r
+extern unsigned long EthernetPHYRead(unsigned long ulBase,\r
+ unsigned char ucRegAddr);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __ETHERNET_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// gpio.h - Defines and Macros for GPIO API.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __GPIO_H__\r
+#define __GPIO_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// The following values define the bit field for the ucPins argument to several\r
+// of the APIs.\r
+//\r
+//*****************************************************************************\r
+#define GPIO_PIN_0 0x00000001 // GPIO pin 0\r
+#define GPIO_PIN_1 0x00000002 // GPIO pin 1\r
+#define GPIO_PIN_2 0x00000004 // GPIO pin 2\r
+#define GPIO_PIN_3 0x00000008 // GPIO pin 3\r
+#define GPIO_PIN_4 0x00000010 // GPIO pin 4\r
+#define GPIO_PIN_5 0x00000020 // GPIO pin 5\r
+#define GPIO_PIN_6 0x00000040 // GPIO pin 6\r
+#define GPIO_PIN_7 0x00000080 // GPIO pin 7\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to GPIODirModeSet as the ulPinIO parameter, and\r
+// returned from GPIODirModeGet.\r
+//\r
+//*****************************************************************************\r
+#define GPIO_DIR_MODE_IN 0x00000000 // Pin is a GPIO input\r
+#define GPIO_DIR_MODE_OUT 0x00000001 // Pin is a GPIO output\r
+#define GPIO_DIR_MODE_HW 0x00000002 // Pin is a peripheral function\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to GPIOIntTypeSet as the ulIntType parameter, and\r
+// returned from GPIOIntTypeGet.\r
+//\r
+//*****************************************************************************\r
+#define GPIO_FALLING_EDGE 0x00000000 // Interrupt on falling edge\r
+#define GPIO_RISING_EDGE 0x00000004 // Interrupt on rising edge\r
+#define GPIO_BOTH_EDGES 0x00000001 // Interrupt on both edges\r
+#define GPIO_LOW_LEVEL 0x00000002 // Interrupt on low level\r
+#define GPIO_HIGH_LEVEL 0x00000007 // Interrupt on high level\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to GPIOPadConfigSet as the ulStrength parameter,\r
+// and returned by GPIOPadConfigGet in the *pulStrength parameter.\r
+//\r
+//*****************************************************************************\r
+#define GPIO_STRENGTH_2MA 0x00000001 // 2mA drive strength\r
+#define GPIO_STRENGTH_4MA 0x00000002 // 4mA drive strength\r
+#define GPIO_STRENGTH_8MA 0x00000004 // 8mA drive strength\r
+#define GPIO_STRENGTH_8MA_SC 0x0000000C // 8mA drive with slew rate control\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to GPIOPadConfigSet as the ulPadType parameter,\r
+// and returned by GPIOPadConfigGet in the *pulPadType parameter.\r
+//\r
+//*****************************************************************************\r
+#define GPIO_PIN_TYPE_STD 0x00000008 // Push-pull\r
+#define GPIO_PIN_TYPE_STD_WPU 0x0000000A // Push-pull with weak pull-up\r
+#define GPIO_PIN_TYPE_STD_WPD 0x0000000C // Push-pull with weak pull-down\r
+#define GPIO_PIN_TYPE_OD 0x00000009 // Open-drain\r
+#define GPIO_PIN_TYPE_OD_WPU 0x0000000B // Open-drain with weak pull-up\r
+#define GPIO_PIN_TYPE_OD_WPD 0x0000000D // Open-drain with weak pull-down\r
+#define GPIO_PIN_TYPE_ANALOG 0x00000000 // Analog comparator\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+extern void GPIODirModeSet(unsigned long ulPort, unsigned char ucPins,\r
+ unsigned long ulPinIO);\r
+extern unsigned long GPIODirModeGet(unsigned long ulPort, unsigned char ucPin);\r
+extern void GPIOIntTypeSet(unsigned long ulPort, unsigned char ucPins,\r
+ unsigned long ulIntType);\r
+extern unsigned long GPIOIntTypeGet(unsigned long ulPort, unsigned char ucPin);\r
+extern void GPIOPadConfigSet(unsigned long ulPort, unsigned char ucPins,\r
+ unsigned long ulStrength,\r
+ unsigned long ulPadType);\r
+extern void GPIOPadConfigGet(unsigned long ulPort, unsigned char ucPin,\r
+ unsigned long *pulStrength,\r
+ unsigned long *pulPadType);\r
+extern void GPIOPinIntEnable(unsigned long ulPort, unsigned char ucPins);\r
+extern void GPIOPinIntDisable(unsigned long ulPort, unsigned char ucPins);\r
+extern long GPIOPinIntStatus(unsigned long ulPort, tBoolean bMasked);\r
+extern void GPIOPinIntClear(unsigned long ulPort, unsigned char ucPins);\r
+extern void GPIOPortIntRegister(unsigned long ulPort,\r
+ void (*pfIntHandler)(void));\r
+extern void GPIOPortIntUnregister(unsigned long ulPort);\r
+extern long GPIOPinRead(unsigned long ulPort, unsigned char ucPins);\r
+extern void GPIOPinWrite(unsigned long ulPort, unsigned char ucPins,\r
+ unsigned char ucVal);\r
+extern void GPIOPinTypeComparator(unsigned long ulPort, unsigned char ucPins);\r
+extern void GPIOPinTypeI2C(unsigned long ulPort, unsigned char ucPins);\r
+extern void GPIOPinTypePWM(unsigned long ulPort, unsigned char ucPins);\r
+extern void GPIOPinTypeQEI(unsigned long ulPort, unsigned char ucPins);\r
+extern void GPIOPinTypeSSI(unsigned long ulPort, unsigned char ucPins);\r
+extern void GPIOPinTypeTimer(unsigned long ulPort, unsigned char ucPins);\r
+extern void GPIOPinTypeUART(unsigned long ulPort, unsigned char ucPins);\r
+extern void GPIOPinTypeCAN(unsigned long ulPort, unsigned char ucPins);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __GPIO_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hibernate.h - API definition for the Hibernation module.\r
+//\r
+// Copyright (c) 2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HIBERNATE_H__\r
+#define __HIBERNATE_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Macros needed for selecting the clock source for HibernateClockSelect()\r
+//\r
+//*****************************************************************************\r
+#define HIBERNATE_CLOCK_SEL_RAW 0x04\r
+#define HIBERNATE_CLOCK_SEL_DIV128 0x00\r
+\r
+//*****************************************************************************\r
+//\r
+// Macros need to configure wake events for HibernateWakeSet()\r
+//\r
+//*****************************************************************************\r
+#define HIBERNATE_WAKE_PIN 0x10\r
+#define HIBERNATE_WAKE_RTC 0x08\r
+\r
+//*****************************************************************************\r
+//\r
+// Macros needed to configure low battery detect for HibernateLowBatSet()\r
+//\r
+//*****************************************************************************\r
+#define HIBERNATE_LOW_BAT_DETECT 0x20\r
+#define HIBERNATE_LOW_BAT_ABORT 0xA0\r
+\r
+//*****************************************************************************\r
+//\r
+// Macros defining interrupt source bits for the interrupt functions.\r
+//\r
+//*****************************************************************************\r
+#define HIBERNATE_INT_PIN_WAKE 0x08\r
+#define HIBERNATE_INT_LOW_BAT 0x04\r
+#define HIBERNATE_INT_RTC_MATCH_0 0x01\r
+#define HIBERNATE_INT_RTC_MATCH_1 0x02\r
+\r
+//*****************************************************************************\r
+//\r
+// API Function prototypes\r
+//\r
+//*****************************************************************************\r
+extern void HibernateEnable(void);\r
+extern void HibernateDisable(void);\r
+extern void HibernateClockSelect(unsigned long ulClockInput);\r
+extern void HibernateRTCEnable(void);\r
+extern void HibernateRTCDisable(void);\r
+extern void HibernateWakeSet(unsigned long ulWakeFlags);\r
+extern unsigned long HibernateWakeGet(void);\r
+extern void HibernateLowBatSet(unsigned long ulLowBatFlags);\r
+extern unsigned long HibernateLowBatGet(void);\r
+extern void HibernateRTCSet(unsigned long ulRTCValue);\r
+extern unsigned long HibernateRTCGet(void);\r
+extern void HibernateRTCMatch0Set(unsigned long ulMatch);\r
+extern unsigned long HibernateRTCMatch0Get(void);\r
+extern void HibernateRTCMatch1Set(unsigned long ulMatch);\r
+extern unsigned long HibernateRTCMatch1Get(void);\r
+extern void HibernateRTCTrimSet(unsigned long ulTrim);\r
+extern unsigned long HibernateRTCTrimGet(void);\r
+extern void HibernateDataSet(unsigned long *pulData, unsigned long ulCount);\r
+extern void HibernateDataGet(unsigned long *pulData, unsigned long ulCount);\r
+extern void HibernateRequest(void);\r
+extern void HibernateIntEnable(unsigned long ulIntFlags);\r
+extern void HibernateIntDisable(unsigned long ulIntFlags);\r
+extern void HibernateIntRegister(void (*pfnHandler)(void));\r
+extern void HibernateIntUnregister(void);\r
+extern unsigned long HibernateIntStatus(tBoolean bMasked);\r
+extern void HibernateIntClear(unsigned long ulIntFlags);\r
+extern unsigned int HibernateIsActive(void);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __HIBERNATE_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_adc.h - Macros used when accessing the ADC hardware.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_ADC_H__\r
+#define __HW_ADC_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the offsets of the ADC registers.\r
+//\r
+//*****************************************************************************\r
+#define ADC_O_ACTSS 0x00000000 // Active sample register\r
+#define ADC_O_RIS 0x00000004 // Raw interrupt status register\r
+#define ADC_O_IM 0x00000008 // Interrupt mask register\r
+#define ADC_O_ISC 0x0000000C // Interrupt status/clear register\r
+#define ADC_O_OSTAT 0x00000010 // Overflow status register\r
+#define ADC_O_EMUX 0x00000014 // Event multiplexer select reg.\r
+#define ADC_O_USTAT 0x00000018 // Underflow status register\r
+#define ADC_O_SSPRI 0x00000020 // Channel priority register\r
+#define ADC_O_PSSI 0x00000028 // Processor sample initiate reg.\r
+#define ADC_O_SAC 0x00000030 // Sample Averaging Control reg.\r
+#define ADC_O_SSMUX0 0x00000040 // Multiplexer select 0 register\r
+#define ADC_O_SSCTL0 0x00000044 // Sample sequence control 0 reg.\r
+#define ADC_O_SSFIFO0 0x00000048 // Result FIFO 0 register\r
+#define ADC_O_SSFSTAT0 0x0000004C // FIFO 0 status register\r
+#define ADC_O_SSMUX1 0x00000060 // Multiplexer select 1 register\r
+#define ADC_O_SSCTL1 0x00000064 // Sample sequence control 1 reg.\r
+#define ADC_O_SSFIFO1 0x00000068 // Result FIFO 1 register\r
+#define ADC_O_SSFSTAT1 0x0000006C // FIFO 1 status register\r
+#define ADC_O_SSMUX2 0x00000080 // Multiplexer select 2 register\r
+#define ADC_O_SSCTL2 0x00000084 // Sample sequence control 2 reg.\r
+#define ADC_O_SSFIFO2 0x00000088 // Result FIFO 2 register\r
+#define ADC_O_SSFSTAT2 0x0000008C // FIFO 2 status register\r
+#define ADC_O_SSMUX3 0x000000A0 // Multiplexer select 3 register\r
+#define ADC_O_SSCTL3 0x000000A4 // Sample sequence control 3 reg.\r
+#define ADC_O_SSFIFO3 0x000000A8 // Result FIFO 3 register\r
+#define ADC_O_SSFSTAT3 0x000000AC // FIFO 3 status register\r
+#define ADC_O_TMLB 0x00000100 // Test mode loopback register\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the offsets of the ADC sequence registers.\r
+//\r
+//*****************************************************************************\r
+#define ADC_O_SEQ 0x00000040 // Offset to the first sequence\r
+#define ADC_O_SEQ_STEP 0x00000020 // Increment to the next sequence\r
+#define ADC_O_X_SSMUX 0x00000000 // Multiplexer select register\r
+#define ADC_O_X_SSCTL 0x00000004 // Sample sequence control register\r
+#define ADC_O_X_SSFIFO 0x00000008 // Result FIFO register\r
+#define ADC_O_X_SSFSTAT 0x0000000C // FIFO status register\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the ADC_ACTSS register.\r
+//\r
+//*****************************************************************************\r
+#define ADC_ACTSS_ASEN3 0x00000008 // Sample sequence 3 enable\r
+#define ADC_ACTSS_ASEN2 0x00000004 // Sample sequence 2 enable\r
+#define ADC_ACTSS_ASEN1 0x00000002 // Sample sequence 1 enable\r
+#define ADC_ACTSS_ASEN0 0x00000001 // Sample sequence 0 enable\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the ADC_RIS register.\r
+//\r
+//*****************************************************************************\r
+#define ADC_RIS_INR3 0x00000008 // Sample sequence 3 interrupt\r
+#define ADC_RIS_INR2 0x00000004 // Sample sequence 2 interrupt\r
+#define ADC_RIS_INR1 0x00000002 // Sample sequence 1 interrupt\r
+#define ADC_RIS_INR0 0x00000001 // Sample sequence 0 interrupt\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the ADC_IM register.\r
+//\r
+//*****************************************************************************\r
+#define ADC_IM_MASK3 0x00000008 // Sample sequence 3 mask\r
+#define ADC_IM_MASK2 0x00000004 // Sample sequence 2 mask\r
+#define ADC_IM_MASK1 0x00000002 // Sample sequence 1 mask\r
+#define ADC_IM_MASK0 0x00000001 // Sample sequence 0 mask\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the ADC_ISC register.\r
+//\r
+//*****************************************************************************\r
+#define ADC_ISC_IN3 0x00000008 // Sample sequence 3 interrupt\r
+#define ADC_ISC_IN2 0x00000004 // Sample sequence 2 interrupt\r
+#define ADC_ISC_IN1 0x00000002 // Sample sequence 1 interrupt\r
+#define ADC_ISC_IN0 0x00000001 // Sample sequence 0 interrupt\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the ADC_OSTAT register.\r
+//\r
+//*****************************************************************************\r
+#define ADC_OSTAT_OV3 0x00000008 // Sample sequence 3 overflow\r
+#define ADC_OSTAT_OV2 0x00000004 // Sample sequence 2 overflow\r
+#define ADC_OSTAT_OV1 0x00000002 // Sample sequence 1 overflow\r
+#define ADC_OSTAT_OV0 0x00000001 // Sample sequence 0 overflow\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the ADC_EMUX register.\r
+//\r
+//*****************************************************************************\r
+#define ADC_EMUX_EM3_MASK 0x0000F000 // Event mux 3 mask\r
+#define ADC_EMUX_EM3_PROCESSOR 0x00000000 // Processor event\r
+#define ADC_EMUX_EM3_COMP0 0x00001000 // Analog comparator 0 event\r
+#define ADC_EMUX_EM3_COMP1 0x00002000 // Analog comparator 1 event\r
+#define ADC_EMUX_EM3_COMP2 0x00003000 // Analog comparator 2 event\r
+#define ADC_EMUX_EM3_EXTERNAL 0x00004000 // External event\r
+#define ADC_EMUX_EM3_TIMER 0x00005000 // Timer event\r
+#define ADC_EMUX_EM3_PWM0 0x00006000 // PWM0 event\r
+#define ADC_EMUX_EM3_PWM1 0x00007000 // PWM1 event\r
+#define ADC_EMUX_EM3_PWM2 0x00008000 // PWM2 event\r
+#define ADC_EMUX_EM3_ALWAYS 0x0000F000 // Always event\r
+#define ADC_EMUX_EM2_MASK 0x00000F00 // Event mux 2 mask\r
+#define ADC_EMUX_EM2_PROCESSOR 0x00000000 // Processor event\r
+#define ADC_EMUX_EM2_COMP0 0x00000100 // Analog comparator 0 event\r
+#define ADC_EMUX_EM2_COMP1 0x00000200 // Analog comparator 1 event\r
+#define ADC_EMUX_EM2_COMP2 0x00000300 // Analog comparator 2 event\r
+#define ADC_EMUX_EM2_EXTERNAL 0x00000400 // External event\r
+#define ADC_EMUX_EM2_TIMER 0x00000500 // Timer event\r
+#define ADC_EMUX_EM2_PWM0 0x00000600 // PWM0 event\r
+#define ADC_EMUX_EM2_PWM1 0x00000700 // PWM1 event\r
+#define ADC_EMUX_EM2_PWM2 0x00000800 // PWM2 event\r
+#define ADC_EMUX_EM2_ALWAYS 0x00000F00 // Always event\r
+#define ADC_EMUX_EM1_MASK 0x000000F0 // Event mux 1 mask\r
+#define ADC_EMUX_EM1_PROCESSOR 0x00000000 // Processor event\r
+#define ADC_EMUX_EM1_COMP0 0x00000010 // Analog comparator 0 event\r
+#define ADC_EMUX_EM1_COMP1 0x00000020 // Analog comparator 1 event\r
+#define ADC_EMUX_EM1_COMP2 0x00000030 // Analog comparator 2 event\r
+#define ADC_EMUX_EM1_EXTERNAL 0x00000040 // External event\r
+#define ADC_EMUX_EM1_TIMER 0x00000050 // Timer event\r
+#define ADC_EMUX_EM1_PWM0 0x00000060 // PWM0 event\r
+#define ADC_EMUX_EM1_PWM1 0x00000070 // PWM1 event\r
+#define ADC_EMUX_EM1_PWM2 0x00000080 // PWM2 event\r
+#define ADC_EMUX_EM1_ALWAYS 0x000000F0 // Always event\r
+#define ADC_EMUX_EM0_MASK 0x0000000F // Event mux 0 mask\r
+#define ADC_EMUX_EM0_PROCESSOR 0x00000000 // Processor event\r
+#define ADC_EMUX_EM0_COMP0 0x00000001 // Analog comparator 0 event\r
+#define ADC_EMUX_EM0_COMP1 0x00000002 // Analog comparator 1 event\r
+#define ADC_EMUX_EM0_COMP2 0x00000003 // Analog comparator 2 event\r
+#define ADC_EMUX_EM0_EXTERNAL 0x00000004 // External event\r
+#define ADC_EMUX_EM0_TIMER 0x00000005 // Timer event\r
+#define ADC_EMUX_EM0_PWM0 0x00000006 // PWM0 event\r
+#define ADC_EMUX_EM0_PWM1 0x00000007 // PWM1 event\r
+#define ADC_EMUX_EM0_PWM2 0x00000008 // PWM2 event\r
+#define ADC_EMUX_EM0_ALWAYS 0x0000000F // Always event\r
+#define ADC_EMUX_EM0_SHIFT 0 // The shift for the first event\r
+#define ADC_EMUX_EM1_SHIFT 4 // The shift for the second event\r
+#define ADC_EMUX_EM2_SHIFT 8 // The shift for the third event\r
+#define ADC_EMUX_EM3_SHIFT 12 // The shift for the fourth event\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the ADC_USTAT register.\r
+//\r
+//*****************************************************************************\r
+#define ADC_USTAT_UV3 0x00000008 // Sample sequence 3 underflow\r
+#define ADC_USTAT_UV2 0x00000004 // Sample sequence 2 underflow\r
+#define ADC_USTAT_UV1 0x00000002 // Sample sequence 1 underflow\r
+#define ADC_USTAT_UV0 0x00000001 // Sample sequence 0 underflow\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the ADC_SSPRI register.\r
+//\r
+//*****************************************************************************\r
+#define ADC_SSPRI_SS3_MASK 0x00003000 // Sequencer 3 priority mask\r
+#define ADC_SSPRI_SS3_1ST 0x00000000 // First priority\r
+#define ADC_SSPRI_SS3_2ND 0x00001000 // Second priority\r
+#define ADC_SSPRI_SS3_3RD 0x00002000 // Third priority\r
+#define ADC_SSPRI_SS3_4TH 0x00003000 // Fourth priority\r
+#define ADC_SSPRI_SS2_MASK 0x00000300 // Sequencer 2 priority mask\r
+#define ADC_SSPRI_SS2_1ST 0x00000000 // First priority\r
+#define ADC_SSPRI_SS2_2ND 0x00000100 // Second priority\r
+#define ADC_SSPRI_SS2_3RD 0x00000200 // Third priority\r
+#define ADC_SSPRI_SS2_4TH 0x00000300 // Fourth priority\r
+#define ADC_SSPRI_SS1_MASK 0x00000030 // Sequencer 1 priority mask\r
+#define ADC_SSPRI_SS1_1ST 0x00000000 // First priority\r
+#define ADC_SSPRI_SS1_2ND 0x00000010 // Second priority\r
+#define ADC_SSPRI_SS1_3RD 0x00000020 // Third priority\r
+#define ADC_SSPRI_SS1_4TH 0x00000030 // Fourth priority\r
+#define ADC_SSPRI_SS0_MASK 0x00000003 // Sequencer 0 priority mask\r
+#define ADC_SSPRI_SS0_1ST 0x00000000 // First priority\r
+#define ADC_SSPRI_SS0_2ND 0x00000001 // Second priority\r
+#define ADC_SSPRI_SS0_3RD 0x00000002 // Third priority\r
+#define ADC_SSPRI_SS0_4TH 0x00000003 // Fourth priority\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the ADC_PSSI register.\r
+//\r
+//*****************************************************************************\r
+#define ADC_PSSI_SS3 0x00000008 // Trigger sample sequencer 3\r
+#define ADC_PSSI_SS2 0x00000004 // Trigger sample sequencer 2\r
+#define ADC_PSSI_SS1 0x00000002 // Trigger sample sequencer 1\r
+#define ADC_PSSI_SS0 0x00000001 // Trigger sample sequencer 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the ADC_SAC register.\r
+//\r
+//*****************************************************************************\r
+#define ADC_SAC_AVG_OFF 0x00000000 // No hardware oversampling\r
+#define ADC_SAC_AVG_2X 0x00000001 // 2x hardware oversampling\r
+#define ADC_SAC_AVG_4X 0x00000002 // 4x hardware oversampling\r
+#define ADC_SAC_AVG_8X 0x00000003 // 8x hardware oversampling\r
+#define ADC_SAC_AVG_16X 0x00000004 // 16x hardware oversampling\r
+#define ADC_SAC_AVG_32X 0x00000005 // 32x hardware oversampling\r
+#define ADC_SAC_AVG_64X 0x00000006 // 64x hardware oversampling\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the ADC_SSMUX0, ADC_SSMUX1,\r
+// ADC_SSMUX2, and ADC_SSMUX3 registers. Not all fields are present in all\r
+// registers.\r
+//\r
+//*****************************************************************************\r
+#define ADC_SSMUX_MUX7_MASK 0x70000000 // 8th mux select mask\r
+#define ADC_SSMUX_MUX6_MASK 0x07000000 // 7th mux select mask\r
+#define ADC_SSMUX_MUX5_MASK 0x00700000 // 6th mux select mask\r
+#define ADC_SSMUX_MUX4_MASK 0x00070000 // 5th mux select mask\r
+#define ADC_SSMUX_MUX3_MASK 0x00007000 // 4th mux select mask\r
+#define ADC_SSMUX_MUX2_MASK 0x00000700 // 3rd mux select mask\r
+#define ADC_SSMUX_MUX1_MASK 0x00000070 // 2nd mux select mask\r
+#define ADC_SSMUX_MUX0_MASK 0x00000007 // 1st mux select mask\r
+#define ADC_SSMUX_MUX7_SHIFT 28\r
+#define ADC_SSMUX_MUX6_SHIFT 24\r
+#define ADC_SSMUX_MUX5_SHIFT 20\r
+#define ADC_SSMUX_MUX4_SHIFT 16\r
+#define ADC_SSMUX_MUX3_SHIFT 12\r
+#define ADC_SSMUX_MUX2_SHIFT 8\r
+#define ADC_SSMUX_MUX1_SHIFT 4\r
+#define ADC_SSMUX_MUX0_SHIFT 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the ADC_SSCTL0, ADC_SSCTL1,\r
+// ADC_SSCTL2, and ADC_SSCTL3 registers. Not all fields are present in all\r
+// registers.\r
+//\r
+//*****************************************************************************\r
+#define ADC_SSCTL_TS7 0x80000000 // 8th temperature sensor select\r
+#define ADC_SSCTL_IE7 0x40000000 // 8th interrupt enable\r
+#define ADC_SSCTL_END7 0x20000000 // 8th sequence end select\r
+#define ADC_SSCTL_D7 0x10000000 // 8th differential select\r
+#define ADC_SSCTL_TS6 0x08000000 // 7th temperature sensor select\r
+#define ADC_SSCTL_IE6 0x04000000 // 7th interrupt enable\r
+#define ADC_SSCTL_END6 0x02000000 // 7th sequence end select\r
+#define ADC_SSCTL_D6 0x01000000 // 7th differential select\r
+#define ADC_SSCTL_TS5 0x00800000 // 6th temperature sensor select\r
+#define ADC_SSCTL_IE5 0x00400000 // 6th interrupt enable\r
+#define ADC_SSCTL_END5 0x00200000 // 6th sequence end select\r
+#define ADC_SSCTL_D5 0x00100000 // 6th differential select\r
+#define ADC_SSCTL_TS4 0x00080000 // 5th temperature sensor select\r
+#define ADC_SSCTL_IE4 0x00040000 // 5th interrupt enable\r
+#define ADC_SSCTL_END4 0x00020000 // 5th sequence end select\r
+#define ADC_SSCTL_D4 0x00010000 // 5th differential select\r
+#define ADC_SSCTL_TS3 0x00008000 // 4th temperature sensor select\r
+#define ADC_SSCTL_IE3 0x00004000 // 4th interrupt enable\r
+#define ADC_SSCTL_END3 0x00002000 // 4th sequence end select\r
+#define ADC_SSCTL_D3 0x00001000 // 4th differential select\r
+#define ADC_SSCTL_TS2 0x00000800 // 3rd temperature sensor select\r
+#define ADC_SSCTL_IE2 0x00000400 // 3rd interrupt enable\r
+#define ADC_SSCTL_END2 0x00000200 // 3rd sequence end select\r
+#define ADC_SSCTL_D2 0x00000100 // 3rd differential select\r
+#define ADC_SSCTL_TS1 0x00000080 // 2nd temperature sensor select\r
+#define ADC_SSCTL_IE1 0x00000040 // 2nd interrupt enable\r
+#define ADC_SSCTL_END1 0x00000020 // 2nd sequence end select\r
+#define ADC_SSCTL_D1 0x00000010 // 2nd differential select\r
+#define ADC_SSCTL_TS0 0x00000008 // 1st temperature sensor select\r
+#define ADC_SSCTL_IE0 0x00000004 // 1st interrupt enable\r
+#define ADC_SSCTL_END0 0x00000002 // 1st sequence end select\r
+#define ADC_SSCTL_D0 0x00000001 // 1st differential select\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the ADC_SSFIFO0, ADC_SSFIFO1,\r
+// ADC_SSFIFO2, and ADC_SSFIFO3 registers.\r
+//\r
+//*****************************************************************************\r
+#define ADC_SSFIFO_DATA_MASK 0x000003FF // Sample data\r
+#define ADC_SSFIFO_DATA_SHIFT 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the ADC_SSFSTAT0, ADC_SSFSTAT1,\r
+// ADC_SSFSTAT2, and ADC_SSFSTAT3 registers.\r
+//\r
+//*****************************************************************************\r
+#define ADC_SSFSTAT_FULL 0x00001000 // FIFO is full\r
+#define ADC_SSFSTAT_EMPTY 0x00000100 // FIFO is empty\r
+#define ADC_SSFSTAT_HPTR 0x000000F0 // FIFO head pointer\r
+#define ADC_SSFSTAT_TPTR 0x0000000F // FIFO tail pointer\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the ADC_TMLB register.\r
+//\r
+//*****************************************************************************\r
+#define ADC_TMLB_LB 0x00000001 // Loopback control signals\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the loopback ADC data.\r
+//\r
+//*****************************************************************************\r
+#define ADC_LB_CNT_MASK 0x000003C0 // Sample counter mask\r
+#define ADC_LB_CONT 0x00000020 // Continuation sample\r
+#define ADC_LB_DIFF 0x00000010 // Differential sample\r
+#define ADC_LB_TS 0x00000008 // Temperature sensor sample\r
+#define ADC_LB_MUX_MASK 0x00000007 // Input channel number mask\r
+#define ADC_LB_CNT_SHIFT 6 // Sample counter shift\r
+#define ADC_LB_MUX_SHIFT 0 // Input channel number shift\r
+\r
+#endif // __HW_ADC_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_can.h - Defines and macros used when accessing the can.\r
+//\r
+// Copyright (c) 2006-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_CAN_H__\r
+#define __HW_CAN_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the offsets of the can registers.\r
+//\r
+//*****************************************************************************\r
+#define CAN_O_CTL 0x00000000 // Control register\r
+#define CAN_O_STS 0x00000004 // Status register\r
+#define CAN_O_ERR 0x00000008 // Error register\r
+#define CAN_O_BIT 0x0000000C // Bit Timing register\r
+#define CAN_O_INT 0x00000010 // Interrupt register\r
+#define CAN_O_TST 0x00000014 // Test register\r
+#define CAN_O_BRPE 0x00000018 // Baud Rate Prescaler register\r
+#define CAN_O_IF1CRQ 0x00000020 // Interface 1 Command Request reg.\r
+#define CAN_O_IF1CMSK 0x00000024 // Interface 1 Command Mask reg.\r
+#define CAN_O_IF1MSK1 0x00000028 // Interface 1 Mask 1 register\r
+#define CAN_O_IF1MSK2 0x0000002C // Interface 1 Mask 2 register\r
+#define CAN_O_IF1ARB1 0x00000030 // Interface 1 Arbitration 1 reg.\r
+#define CAN_O_IF1ARB2 0x00000034 // Interface 1 Arbitration 2 reg.\r
+#define CAN_O_IF1MCTL 0x00000038 // Interface 1 Message Control reg.\r
+#define CAN_O_IF1DA1 0x0000003C // Interface 1 DataA 1 register\r
+#define CAN_O_IF1DA2 0x00000040 // Interface 1 DataA 2 register\r
+#define CAN_O_IF1DB1 0x00000044 // Interface 1 DataB 1 register\r
+#define CAN_O_IF1DB2 0x00000048 // Interface 1 DataB 2 register\r
+#define CAN_O_IF2CRQ 0x00000080 // Interface 2 Command Request reg.\r
+#define CAN_O_IF2CMSK 0x00000084 // Interface 2 Command Mask reg.\r
+#define CAN_O_IF2MSK1 0x00000088 // Interface 2 Mask 1 register\r
+#define CAN_O_IF2MSK2 0x0000008C // Interface 2 Mask 2 register\r
+#define CAN_O_IF2ARB1 0x00000090 // Interface 2 Arbitration 1 reg.\r
+#define CAN_O_IF2ARB2 0x00000094 // Interface 2 Arbitration 2 reg.\r
+#define CAN_O_IF2MCTL 0x00000098 // Interface 2 Message Control reg.\r
+#define CAN_O_IF2DA1 0x0000009C // Interface 2 DataA 1 register\r
+#define CAN_O_IF2DA2 0x000000A0 // Interface 2 DataA 2 register\r
+#define CAN_O_IF2DB1 0x000000A4 // Interface 2 DataB 1 register\r
+#define CAN_O_IF2DB2 0x000000A8 // Interface 2 DataB 2 register\r
+#define CAN_O_TXRQ1 0x00000100 // Transmission Request 1 register\r
+#define CAN_O_TXRQ2 0x00000104 // Transmission Request 2 register\r
+#define CAN_O_NWDA1 0x00000120 // New Data 1 register\r
+#define CAN_O_NWDA2 0x00000124 // New Data 2 register\r
+#define CAN_O_MSGINT1 0x00000140 // Intr. Pending in Msg Obj 1 reg.\r
+#define CAN_O_MSGINT2 0x00000144 // Intr. Pending in Msg Obj 2 reg.\r
+#define CAN_O_MSGVAL1 0x00000160 // Message Valid in Msg Obj 1 reg.\r
+#define CAN_O_MSGVAL2 0x00000164 // Message Valid in Msg Obj 2 reg.\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the reset values of the can registers.\r
+//\r
+//*****************************************************************************\r
+#define CAN_RV_CTL 0x00000001\r
+#define CAN_RV_STS 0x00000000\r
+#define CAN_RV_ERR 0x00000000\r
+#define CAN_RV_BIT 0x00002301\r
+#define CAN_RV_INT 0x00000000\r
+#define CAN_RV_TST 0x00000000\r
+#define CAN_RV_BRPE 0x00000000\r
+#define CAN_RV_IF1CRQ 0x00000001\r
+#define CAN_RV_IF1CMSK 0x00000000\r
+#define CAN_RV_IF1MSK1 0x0000FFFF\r
+#define CAN_RV_IF1MSK2 0x0000FFFF\r
+#define CAN_RV_IF1ARB1 0x00000000\r
+#define CAN_RV_IF1ARB2 0x00000000\r
+#define CAN_RV_IF1MCTL 0x00000000\r
+#define CAN_RV_IF1DA1 0x00000000\r
+#define CAN_RV_IF1DA2 0x00000000\r
+#define CAN_RV_IF1DB1 0x00000000\r
+#define CAN_RV_IF1DB2 0x00000000\r
+#define CAN_RV_IF2CRQ 0x00000001\r
+#define CAN_RV_IF2CMSK 0x00000000\r
+#define CAN_RV_IF2MSK1 0x0000FFFF\r
+#define CAN_RV_IF2MSK2 0x0000FFFF\r
+#define CAN_RV_IF2ARB1 0x00000000\r
+#define CAN_RV_IF2ARB2 0x00000000\r
+#define CAN_RV_IF2MCTL 0x00000000\r
+#define CAN_RV_IF2DA1 0x00000000\r
+#define CAN_RV_IF2DA2 0x00000000\r
+#define CAN_RV_IF2DB1 0x00000000\r
+#define CAN_RV_IF2DB2 0x00000000\r
+#define CAN_RV_TXRQ1 0x00000000\r
+#define CAN_RV_TXRQ2 0x00000000\r
+#define CAN_RV_NWDA1 0x00000000\r
+#define CAN_RV_NWDA2 0x00000000\r
+#define CAN_RV_MSGINT1 0x00000000\r
+#define CAN_RV_MSGINT2 0x00000000\r
+#define CAN_RV_MSGVAL1 0x00000000\r
+#define CAN_RV_MSGVAL2 0x00000000\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the CAN_CTL register.\r
+//\r
+//*****************************************************************************\r
+#define CAN_CTL_TEST 0x00000080 // Test mode enable\r
+#define CAN_CTL_CCE 0x00000040 // Configuration change enable\r
+#define CAN_CTL_DAR 0x00000020 // Disable automatic retransmission\r
+#define CAN_CTL_EIE 0x00000008 // Error interrupt enable\r
+#define CAN_CTL_SIE 0x00000004 // Status change interrupt enable\r
+#define CAN_CTL_IE 0x00000002 // Module interrupt enable\r
+#define CAN_CTL_INIT 0x00000001 // Initialization\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the CAN_STS register.\r
+//\r
+//*****************************************************************************\r
+#define CAN_STS_BOFF 0x00000080 // Bus Off status\r
+#define CAN_STS_EWARN 0x00000040 // Error Warning status\r
+#define CAN_STS_EPASS 0x00000020 // Error Passive status\r
+#define CAN_STS_RXOK 0x00000010 // Received Message Successful\r
+#define CAN_STS_TXOK 0x00000008 // Transmitted Message Successful\r
+#define CAN_STS_LEC_MSK 0x00000007 // Last Error Code\r
+#define CAN_STS_LEC_NONE 0x00000000 // No error\r
+#define CAN_STS_LEC_STUFF 0x00000001 // Stuff error\r
+#define CAN_STS_LEC_FORM 0x00000002 // Form(at) error\r
+#define CAN_STS_LEC_ACK 0x00000003 // Ack error\r
+#define CAN_STS_LEC_BIT1 0x00000004 // Bit 1 error\r
+#define CAN_STS_LEC_BIT0 0x00000005 // Bit 0 error\r
+#define CAN_STS_LEC_CRC 0x00000006 // CRC error\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the CAN_ERR register.\r
+//\r
+//*****************************************************************************\r
+#define CAN_ERR_RP 0x00008000 // Receive error passive status\r
+#define CAN_ERR_REC_MASK 0x00007F00 // Receive error counter status\r
+#define CAN_ERR_REC_SHIFT 8 // Receive error counter bit pos\r
+#define CAN_ERR_TEC_MASK 0x000000FF // Transmit error counter status\r
+#define CAN_ERR_TEC_SHIFT 0 // Transmit error counter bit pos\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the CAN_BIT register.\r
+//\r
+//*****************************************************************************\r
+#define CAN_BIT_TSEG2 0x00007000 // Time segment after sample point\r
+#define CAN_BIT_TSEG1 0x00000F00 // Time segment before sample point\r
+#define CAN_BIT_SJW 0x000000C0 // (Re)Synchronization jump width\r
+#define CAN_BIT_BRP 0x0000003F // Baud rate prescaler\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the CAN_INT register.\r
+//\r
+//*****************************************************************************\r
+#define CAN_INT_INTID_MSK 0x0000FFFF // Interrupt Identifier\r
+#define CAN_INT_INTID_NONE 0x00000000 // No Interrupt Pending\r
+#define CAN_INT_INTID_STATUS 0x00008000 // Status Interrupt\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the CAN_TST register.\r
+//\r
+//*****************************************************************************\r
+#define CAN_TST_RX 0x00000080 // CAN_RX pin status\r
+#define CAN_TST_TX_MSK 0x00000060 // Overide control of CAN_TX pin\r
+#define CAN_TST_TX_CANCTL 0x00000000 // CAN core controls CAN_TX\r
+#define CAN_TST_TX_SAMPLE 0x00000020 // Sample Point on CAN_TX\r
+#define CAN_TST_TX_DOMINANT 0x00000040 // Dominant value on CAN_TX\r
+#define CAN_TST_TX_RECESSIVE 0x00000060 // Recessive value on CAN_TX\r
+#define CAN_TST_LBACK 0x00000010 // Loop back mode\r
+#define CAN_TST_SILENT 0x00000008 // Silent mode\r
+#define CAN_TST_BASIC 0x00000004 // Basic mode\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the CAN_BRPE register.\r
+//\r
+//*****************************************************************************\r
+#define CAN_BRPE_BRPE 0x0000000F // Baud rate prescaler extension\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the CAN_IF1CRQ and CAN_IF1CRQ\r
+// registers.\r
+// Note: All bits may not be available in all registers\r
+//\r
+//*****************************************************************************\r
+#define CAN_IFCRQ_BUSY 0x00008000 // Busy flag status\r
+#define CAN_IFCRQ_MNUM_MSK 0x0000003F // Message Number\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the CAN_IF1CMSK and CAN_IF2CMSK\r
+// registers.\r
+// Note: All bits may not be available in all registers\r
+//\r
+//*****************************************************************************\r
+#define CAN_IFCMSK_WRNRD 0x00000080 // Write, not Read\r
+#define CAN_IFCMSK_MASK 0x00000040 // Access Mask Bits\r
+#define CAN_IFCMSK_ARB 0x00000020 // Access Arbitration Bits\r
+#define CAN_IFCMSK_CONTROL 0x00000010 // Access Control Bits\r
+#define CAN_IFCMSK_CLRINTPND 0x00000008 // Clear interrupt pending Bit\r
+#define CAN_IFCMSK_TXRQST 0x00000004 // Access Tx request bit (WRNRD=1)\r
+#define CAN_IFCMSK_NEWDAT 0x00000004 // Access New Data bit (WRNRD=0)\r
+#define CAN_IFCMSK_DATAA 0x00000002 // DataA access - bytes 0 to 3\r
+#define CAN_IFCMSK_DATAB 0x00000001 // DataB access - bytes 4 to 7\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the CAN_IF1MSK1 and CAN_IF2MSK1\r
+// registers.\r
+// Note: All bits may not be available in all registers\r
+//\r
+//*****************************************************************************\r
+#define CAN_IFMSK1_MSK 0x0000FFFF // Identifier Mask\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the CAN_IF1MSK2 and CAN_IF2MSK2\r
+// registers.\r
+// Note: All bits may not be available in all registers\r
+//\r
+//*****************************************************************************\r
+#define CAN_IFMSK2_MXTD 0x00008000 // Mask extended identifier\r
+#define CAN_IFMSK2_MDIR 0x00004000 // Mask message direction\r
+#define CAN_IFMSK2_MSK 0x00001FFF // Mask identifier\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the CAN_IF1ARB1 and CAN_IF2ARB1\r
+// registers.\r
+// Note: All bits may not be available in all registers\r
+//\r
+//*****************************************************************************\r
+#define CAN_IFARB1_ID 0x0000FFFF // Identifier\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the CAN_IF1ARB2 and CAN_IF2ARB2\r
+// registers.\r
+// Note: All bits may not be available in all registers\r
+//\r
+//*****************************************************************************\r
+#define CAN_IFARB2_MSGVAL 0x00008000 // Message valid\r
+#define CAN_IFARB2_XTD 0x00004000 // Extended identifier\r
+#define CAN_IFARB2_DIR 0x00002000 // Message direction\r
+#define CAN_IFARB2_ID 0x00001FFF // Message identifier\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the CAN_IF1MCTL and CAN_IF2MCTL\r
+// registers.\r
+// Note: All bits may not be available in all registers\r
+//\r
+//*****************************************************************************\r
+#define CAN_IFMCTL_NEWDAT 0x00008000 // New Data\r
+#define CAN_IFMCTL_MSGLST 0x00004000 // Message lost\r
+#define CAN_IFMCTL_INTPND 0x00002000 // Interrupt pending\r
+#define CAN_IFMCTL_UMASK 0x00001000 // Use acceptance mask\r
+#define CAN_IFMCTL_TXIE 0x00000800 // Transmit interrupt enable\r
+#define CAN_IFMCTL_RXIE 0x00000400 // Receive interrupt enable\r
+#define CAN_IFMCTL_RMTEN 0x00000200 // Remote enable\r
+#define CAN_IFMCTL_TXRQST 0x00000100 // Transmit request\r
+#define CAN_IFMCTL_EOB 0x00000080 // End of buffer\r
+#define CAN_IFMCTL_DLC 0x0000000F // Data length code\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the CAN_IF1DA1 and CAN_IF2DA1\r
+// registers.\r
+// Note: All bits may not be available in all registers\r
+//\r
+//*****************************************************************************\r
+#define CAN_IFDA1_DATA 0x0000FFFF // Data - bytes 1 and 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the CAN_IF1DA2 and CAN_IF2DA2\r
+// registers.\r
+// Note: All bits may not be available in all registers\r
+//\r
+//*****************************************************************************\r
+#define CAN_IFDA2_DATA 0x0000FFFF // Data - bytes 3 and 2\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the CAN_IF1DB1 and CAN_IF2DB1\r
+// registers.\r
+// Note: All bits may not be available in all registers\r
+//\r
+//*****************************************************************************\r
+#define CAN_IFDB1_DATA 0x0000FFFF // Data - bytes 5 and 4\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the CAN_IF1DB2 and CAN_IF2DB2\r
+// registers.\r
+// Note: All bits may not be available in all registers\r
+//\r
+//*****************************************************************************\r
+#define CAN_IFDB2_DATA 0x0000FFFF // Data - bytes 7 and 6\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the CAN_TXRQ1 register.\r
+//\r
+//*****************************************************************************\r
+#define CAN_TXRQ1_TXRQST 0x0000FFFF // Transmission Request Bits\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the CAN_TXRQ2 register.\r
+//\r
+//*****************************************************************************\r
+#define CAN_TXRQ2_TXRQST 0x0000FFFF // Transmission Request Bits\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the CAN_NWDA1 register.\r
+//\r
+//*****************************************************************************\r
+#define CAN_NWDA1_NEWDATA 0x0000FFFF // New Data Bits\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the CAN_NWDA2 register.\r
+//\r
+//*****************************************************************************\r
+#define CAN_NWDA2_NEWDATA 0x0000FFFF // New Data Bits\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the CAN_MSGINT1 register.\r
+//\r
+//*****************************************************************************\r
+#define CAN_MSGINT1_INTPND 0x0000FFFF // Interrupt Pending Bits\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the CAN_MSGINT2 register.\r
+//\r
+//*****************************************************************************\r
+#define CAN_MSGINT2_INTPND 0x0000FFFF // Interrupt Pending Bits\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the CAN_MSGVAL1 register.\r
+//\r
+//*****************************************************************************\r
+#define CAN_MSGVAL1_MSGVAL 0x0000FFFF // Message Valid Bits\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the CAN_MSGVAL2 register.\r
+//\r
+//*****************************************************************************\r
+#define CAN_MSGVAL2_MSGVAL 0x0000FFFF // Message Valid Bits\r
+\r
+#endif // __HW_CAN_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_comp.h - Macros used when accessing the comparator hardware.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_COMP_H__\r
+#define __HW_COMP_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the offsets of the comparator registers.\r
+//\r
+//*****************************************************************************\r
+#define COMP_O_MIS 0x00000000 // Interrupt status register\r
+#define COMP_O_RIS 0x00000004 // Raw interrupt status register\r
+#define COMP_O_INTEN 0x00000008 // Interrupt enable register\r
+#define COMP_O_REFCTL 0x00000010 // Reference voltage control reg.\r
+#define COMP_O_ACSTAT0 0x00000020 // Comp0 status register\r
+#define COMP_O_ACCTL0 0x00000024 // Comp0 control register\r
+#define COMP_O_ACSTAT1 0x00000040 // Comp1 status register\r
+#define COMP_O_ACCTL1 0x00000044 // Comp1 control register\r
+#define COMP_O_ACSTAT2 0x00000060 // Comp2 status register\r
+#define COMP_O_ACCTL2 0x00000064 // Comp2 control register\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the COMP_MIS, COMP_RIS, and\r
+// COMP_INTEN registers.\r
+//\r
+//*****************************************************************************\r
+#define COMP_INT_2 0x00000004 // Comp2 interrupt\r
+#define COMP_INT_1 0x00000002 // Comp1 interrupt\r
+#define COMP_INT_0 0x00000001 // Comp0 interrupt\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the COMP_REFCTL register.\r
+//\r
+//*****************************************************************************\r
+#define COMP_REFCTL_EN 0x00000200 // Reference voltage enable\r
+#define COMP_REFCTL_RNG 0x00000100 // Reference voltage range\r
+#define COMP_REFCTL_VREF_MASK 0x0000000F // Reference voltage select mask\r
+#define COMP_REFCTL_VREF_SHIFT 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the COMP_ACSTAT0, COMP_ACSTAT1, and\r
+// COMP_ACSTAT2 registers.\r
+//\r
+//*****************************************************************************\r
+#define COMP_ACSTAT_OVAL 0x00000002 // Comparator output value\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the COMP_ACCTL0, COMP_ACCTL1, and\r
+// COMP_ACCTL2 registers.\r
+//\r
+//*****************************************************************************\r
+#define COMP_ACCTL_TMASK 0x00000800 // Trigger enable\r
+#define COMP_ACCTL_ASRCP_MASK 0x00000600 // Vin+ source select mask\r
+#define COMP_ACCTL_ASRCP_PIN 0x00000000 // Dedicated Comp+ pin\r
+#define COMP_ACCTL_ASRCP_PIN0 0x00000200 // Comp0+ pin\r
+#define COMP_ACCTL_ASRCP_REF 0x00000400 // Internal voltage reference\r
+#define COMP_ACCTL_ASRCP_RES 0x00000600 // Reserved\r
+#define COMP_ACCTL_OEN 0x00000100 // Comparator output enable\r
+#define COMP_ACCTL_TSVAL 0x00000080 // Trigger polarity select\r
+#define COMP_ACCTL_TSEN_MASK 0x00000060 // Trigger sense mask\r
+#define COMP_ACCTL_TSEN_LEVEL 0x00000000 // Trigger is level sense\r
+#define COMP_ACCTL_TSEN_FALL 0x00000020 // Trigger is falling edge\r
+#define COMP_ACCTL_TSEN_RISE 0x00000040 // Trigger is rising edge\r
+#define COMP_ACCTL_TSEN_BOTH 0x00000060 // Trigger is both edges\r
+#define COMP_ACCTL_ISLVAL 0x00000010 // Interrupt polarity select\r
+#define COMP_ACCTL_ISEN_MASK 0x0000000C // Interrupt sense mask\r
+#define COMP_ACCTL_ISEN_LEVEL 0x00000000 // Interrupt is level sense\r
+#define COMP_ACCTL_ISEN_FALL 0x00000004 // Interrupt is falling edge\r
+#define COMP_ACCTL_ISEN_RISE 0x00000008 // Interrupt is rising edge\r
+#define COMP_ACCTL_ISEN_BOTH 0x0000000C // Interrupt is both edges\r
+#define COMP_ACCTL_CINV 0x00000002 // Comparator output invert\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the reset values for the comparator registers.\r
+//\r
+//*****************************************************************************\r
+#define COMP_RV_MIS 0x00000000 // Interrupt status register\r
+#define COMP_RV_RIS 0x00000000 // Raw interrupt status register\r
+#define COMP_RV_INTEN 0x00000000 // Interrupt enable register\r
+#define COMP_RV_REFCTL 0x00000000 // Reference voltage control reg.\r
+#define COMP_RV_ACSTAT0 0x00000000 // Comp0 status register\r
+#define COMP_RV_ACCTL0 0x00000000 // Comp0 control register\r
+#define COMP_RV_ACSTAT1 0x00000000 // Comp1 status register\r
+#define COMP_RV_ACCTL1 0x00000000 // Comp1 control register\r
+#define COMP_RV_ACSTAT2 0x00000000 // Comp2 status register\r
+#define COMP_RV_ACCTL2 0x00000000 // Comp2 control register\r
+\r
+#endif // __HW_COMP_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_ethernet.h - Macros used when accessing the ethernet hardware.\r
+//\r
+// Copyright (c) 2006-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_ETHERNET_H__\r
+#define __HW_ETHERNET_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the offsets of the MAC registers in the Ethernet\r
+// Controller.\r
+//\r
+//*****************************************************************************\r
+#define MAC_O_IS 0x00000000 // Interrupt Status Register\r
+#define MAC_O_IACK 0x00000000 // Interrupt Acknowledge Register\r
+#define MAC_O_IM 0x00000004 // Interrupt Mask Register\r
+#define MAC_O_RCTL 0x00000008 // Receive Control Register\r
+#define MAC_O_TCTL 0x0000000C // Transmit Control Register\r
+#define MAC_O_DATA 0x00000010 // Data Register\r
+#define MAC_O_IA0 0x00000014 // Individual Address Register 0\r
+#define MAC_O_IA1 0x00000018 // Individual Address Register 1\r
+#define MAC_O_THR 0x0000001C // Threshold Register\r
+#define MAC_O_MCTL 0x00000020 // Management Control Register\r
+#define MAC_O_MDV 0x00000024 // Management Divider Register\r
+#define MAC_O_MADD 0x00000028 // Management Address Register\r
+#define MAC_O_MTXD 0x0000002C // Management Transmit Data Reg\r
+#define MAC_O_MRXD 0x00000030 // Management Receive Data Reg\r
+#define MAC_O_NP 0x00000034 // Number of Packets Register\r
+#define MAC_O_TR 0x00000038 // Transmission Request Register\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the reset values of the MAC registers.\r
+//\r
+//*****************************************************************************\r
+#define MAC_RV_IS 0x00000000\r
+#define MAC_RV_IACK 0x00000000\r
+#define MAC_RV_IM 0x0000007F\r
+#define MAC_RV_RCTL 0x00000008\r
+#define MAC_RV_TCTL 0x00000000\r
+#define MAC_RV_DATA 0x00000000\r
+#define MAC_RV_IA0 0x00000000\r
+#define MAC_RV_IA1 0x00000000\r
+#define MAC_RV_THR 0x0000003F\r
+#define MAC_RV_MCTL 0x00000000\r
+#define MAC_RV_MDV 0x00000080\r
+#define MAC_RV_MADD 0x00000000\r
+#define MAC_RV_MTXD 0x00000000\r
+#define MAC_RV_MRXD 0x00000000\r
+#define MAC_RV_NP 0x00000000\r
+#define MAC_RV_TR 0x00000000\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the MAC_IS register.\r
+//\r
+//*****************************************************************************\r
+#define MAC_IS_PHYINT 0x00000040 // PHY Interrupt\r
+#define MAC_IS_MDINT 0x00000020 // MDI Transaction Complete\r
+#define MAC_IS_RXER 0x00000010 // RX Error\r
+#define MAC_IS_FOV 0x00000008 // RX FIFO Overrun\r
+#define MAC_IS_TXEMP 0x00000004 // TX FIFO Empy\r
+#define MAC_IS_TXER 0x00000002 // TX Error\r
+#define MAC_IS_RXINT 0x00000001 // RX Packet Available\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the MAC_IACK register.\r
+//\r
+//*****************************************************************************\r
+#define MAC_IACK_PHYINT 0x00000040 // Clear PHY Interrupt\r
+#define MAC_IACK_MDINT 0x00000020 // Clear MDI Transaction Complete\r
+#define MAC_IACK_RXER 0x00000010 // Clear RX Error\r
+#define MAC_IACK_FOV 0x00000008 // Clear RX FIFO Overrun\r
+#define MAC_IACK_TXEMP 0x00000004 // Clear TX FIFO Empy\r
+#define MAC_IACK_TXER 0x00000002 // Clear TX Error\r
+#define MAC_IACK_RXINT 0x00000001 // Clear RX Packet Available\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the MAC_IM register.\r
+//\r
+//*****************************************************************************\r
+#define MAC_IM_PHYINTM 0x00000040 // Mask PHY Interrupt\r
+#define MAC_IM_MDINTM 0x00000020 // Mask MDI Transaction Complete\r
+#define MAC_IM_RXERM 0x00000010 // Mask RX Error\r
+#define MAC_IM_FOVM 0x00000008 // Mask RX FIFO Overrun\r
+#define MAC_IM_TXEMPM 0x00000004 // Mask TX FIFO Empy\r
+#define MAC_IM_TXERM 0x00000002 // Mask TX Error\r
+#define MAC_IM_RXINTM 0x00000001 // Mask RX Packet Available\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the MAC_RCTL register.\r
+//\r
+//*****************************************************************************\r
+#define MAC_RCTL_RSTFIFO 0x00000010 // Clear the Receive FIFO\r
+#define MAC_RCTL_BADCRC 0x00000008 // Reject Packets With Bad CRC\r
+#define MAC_RCTL_PRMS 0x00000004 // Enable Promiscuous Mode\r
+#define MAC_RCTL_AMUL 0x00000002 // Enable Multicast Packets\r
+#define MAC_RCTL_RXEN 0x00000001 // Enable Ethernet Receiver\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the MAC_TCTL register.\r
+//\r
+//*****************************************************************************\r
+#define MAC_TCTL_DUPLEX 0x00000010 // Enable Duplex mode\r
+#define MAC_TCTL_CRC 0x00000004 // Enable CRC Generation\r
+#define MAC_TCTL_PADEN 0x00000002 // Enable Automatic Padding\r
+#define MAC_TCTL_TXEN 0x00000001 // Enable Ethernet Transmitter\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the MAC_IA0 register.\r
+//\r
+//*****************************************************************************\r
+#define MAC_IA0_MACOCT4 0xFF000000 // 4th Octet of MAC address\r
+#define MAC_IA0_MACOCT3 0x00FF0000 // 3rd Octet of MAC address\r
+#define MAC_IA0_MACOCT2 0x0000FF00 // 2nd Octet of MAC address\r
+#define MAC_IA0_MACOCT1 0x000000FF // 1st Octet of MAC address\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the MAC_IA1 register.\r
+//\r
+//*****************************************************************************\r
+#define MAC_IA1_MACOCT6 0x0000FF00 // 6th Octet of MAC address\r
+#define MAC_IA1_MACOCT5 0x000000FF // 5th Octet of MAC address\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the MAC_TXTH register.\r
+//\r
+//*****************************************************************************\r
+#define MAC_THR_THRESH 0x0000003F // Transmit Threshold Value\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the MAC_MCTL register.\r
+//\r
+//*****************************************************************************\r
+#define MAC_MCTL_REGADR 0x000000F8 // Address for Next MII Transaction\r
+#define MAC_MCTL_WRITE 0x00000002 // Next MII Transaction is Write\r
+#define MAC_MCTL_START 0x00000001 // Start MII Transaction\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the MAC_MDV register.\r
+//\r
+//*****************************************************************************\r
+#define MAC_MDV_DIV 0x000000FF // Clock Divider for MDC for TX\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the MAC_MTXD register.\r
+//\r
+//*****************************************************************************\r
+#define MAC_MTXD_MDTX 0x0000FFFF // Data for Next MII Transaction\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the MAC_MRXD register.\r
+//\r
+//*****************************************************************************\r
+#define MAC_MRXD_MDRX 0x0000FFFF // Data Read from Last MII Trans.\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the MAC_NP register.\r
+//\r
+//*****************************************************************************\r
+#define MAC_NP_NPR 0x0000003F // Number of RX Frames in FIFO\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the MAC_TXRQ register.\r
+//\r
+//*****************************************************************************\r
+#define MAC_TR_NEWTX 0x00000001 // Start an Ethernet Transmission\r
+\r
+#endif // __HW_ETHERNET_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_flash.h - Macros used when accessing the flash controller.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_FLASH_H__\r
+#define __HW_FLASH_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the offsets of the FLASH registers.\r
+//\r
+//*****************************************************************************\r
+#define FLASH_FMA 0x400FD000 // Memory address register\r
+#define FLASH_FMD 0x400FD004 // Memory data register\r
+#define FLASH_FMC 0x400FD008 // Memory control register\r
+#define FLASH_FCRIS 0x400FD00c // Raw interrupt status register\r
+#define FLASH_FCIM 0x400FD010 // Interrupt mask register\r
+#define FLASH_FCMISC 0x400FD014 // Interrupt status register\r
+#define FLASH_FMPRE 0x400FE130 // FLASH read protect register\r
+#define FLASH_FMPPE 0x400FE134 // FLASH program protect register\r
+#define FLASH_USECRL 0x400FE140 // uSec reload register\r
+#define FLASH_FMPRE0 0x400FE200 // FLASH read protect register 0\r
+#define FLASH_FMPRE1 0x400FE204 // FLASH read protect register 1\r
+#define FLASH_FMPRE2 0x400FE208 // FLASH read protect register 2\r
+#define FLASH_FMPRE3 0x400FE20C // FLASH read protect register 3\r
+#define FLASH_FMPPE0 0x400FE400 // FLASH program protect register 0\r
+#define FLASH_FMPPE1 0x400FE404 // FLASH program protect register 1\r
+#define FLASH_FMPPE2 0x400FE408 // FLASH program protect register 2\r
+#define FLASH_FMPPE3 0x400FE40C // FLASH program protect register 3\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the FLASH_FMC register.\r
+//\r
+//*****************************************************************************\r
+#define FLASH_FMC_WRKEY_MASK 0xFFFF0000 // FLASH write key mask\r
+#define FLASH_FMC_WRKEY 0xA4420000 // FLASH write key\r
+#define FLASH_FMC_COMT 0x00000008 // Commit user register\r
+#define FLASH_FMC_MERASE 0x00000004 // Mass erase FLASH\r
+#define FLASH_FMC_ERASE 0x00000002 // Erase FLASH page\r
+#define FLASH_FMC_WRITE 0x00000001 // Write FLASH word\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the FLASH_FCRIS register.\r
+//\r
+//*****************************************************************************\r
+#define FLASH_FCRIS_PROGRAM 0x00000002 // Programming status\r
+#define FLASH_FCRIS_ACCESS 0x00000001 // Invalid access status\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the FLASH_FCIM register.\r
+//\r
+//*****************************************************************************\r
+#define FLASH_FCIM_PROGRAM 0x00000002 // Programming mask\r
+#define FLASH_FCIM_ACCESS 0x00000001 // Invalid access mask\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the FLASH_FMIS register.\r
+//\r
+//*****************************************************************************\r
+#define FLASH_FCMISC_PROGRAM 0x00000002 // Programming status\r
+#define FLASH_FCMISC_ACCESS 0x00000001 // Invalid access status\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the FLASH_FMPRE and FLASH_FMPPE\r
+// registers.\r
+//\r
+//*****************************************************************************\r
+#define FLASH_FMP_BLOCK_31 0x80000000 // Enable for block 31\r
+#define FLASH_FMP_BLOCK_30 0x40000000 // Enable for block 30\r
+#define FLASH_FMP_BLOCK_29 0x20000000 // Enable for block 29\r
+#define FLASH_FMP_BLOCK_28 0x10000000 // Enable for block 28\r
+#define FLASH_FMP_BLOCK_27 0x08000000 // Enable for block 27\r
+#define FLASH_FMP_BLOCK_26 0x04000000 // Enable for block 26\r
+#define FLASH_FMP_BLOCK_25 0x02000000 // Enable for block 25\r
+#define FLASH_FMP_BLOCK_24 0x01000000 // Enable for block 24\r
+#define FLASH_FMP_BLOCK_23 0x00800000 // Enable for block 23\r
+#define FLASH_FMP_BLOCK_22 0x00400000 // Enable for block 22\r
+#define FLASH_FMP_BLOCK_21 0x00200000 // Enable for block 21\r
+#define FLASH_FMP_BLOCK_20 0x00100000 // Enable for block 20\r
+#define FLASH_FMP_BLOCK_19 0x00080000 // Enable for block 19\r
+#define FLASH_FMP_BLOCK_18 0x00040000 // Enable for block 18\r
+#define FLASH_FMP_BLOCK_17 0x00020000 // Enable for block 17\r
+#define FLASH_FMP_BLOCK_16 0x00010000 // Enable for block 16\r
+#define FLASH_FMP_BLOCK_15 0x00008000 // Enable for block 15\r
+#define FLASH_FMP_BLOCK_14 0x00004000 // Enable for block 14\r
+#define FLASH_FMP_BLOCK_13 0x00002000 // Enable for block 13\r
+#define FLASH_FMP_BLOCK_12 0x00001000 // Enable for block 12\r
+#define FLASH_FMP_BLOCK_11 0x00000800 // Enable for block 11\r
+#define FLASH_FMP_BLOCK_10 0x00000400 // Enable for block 10\r
+#define FLASH_FMP_BLOCK_9 0x00000200 // Enable for block 9\r
+#define FLASH_FMP_BLOCK_8 0x00000100 // Enable for block 8\r
+#define FLASH_FMP_BLOCK_7 0x00000080 // Enable for block 7\r
+#define FLASH_FMP_BLOCK_6 0x00000040 // Enable for block 6\r
+#define FLASH_FMP_BLOCK_5 0x00000020 // Enable for block 5\r
+#define FLASH_FMP_BLOCK_4 0x00000010 // Enable for block 4\r
+#define FLASH_FMP_BLOCK_3 0x00000008 // Enable for block 3\r
+#define FLASH_FMP_BLOCK_2 0x00000004 // Enable for block 2\r
+#define FLASH_FMP_BLOCK_1 0x00000002 // Enable for block 1\r
+#define FLASH_FMP_BLOCK_0 0x00000001 // Enable for block 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the FLASH_USECRL register.\r
+//\r
+//*****************************************************************************\r
+#define FLASH_USECRL_MASK 0x000000FF // Clock per uSec\r
+#define FLASH_USECRL_SHIFT 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The erase size is the size of the FLASH block that is erased by an erase\r
+// operation, and the protect size is the size of the FLASH block that is\r
+// protected by each protection register.\r
+//\r
+//*****************************************************************************\r
+#define FLASH_ERASE_SIZE 0x00000400\r
+#define FLASH_PROTECT_SIZE 0x00000800\r
+\r
+#endif // __HW_FLASH_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_gpio.h - Defines and Macros for GPIO hardware.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_GPIO_H__\r
+#define __HW_GPIO_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// GPIO Register Offsets.\r
+//\r
+//*****************************************************************************\r
+#define GPIO_O_DATA 0x00000000 // Data register.\r
+#define GPIO_O_DIR 0x00000400 // Data direction register.\r
+#define GPIO_O_IS 0x00000404 // Interrupt sense register.\r
+#define GPIO_O_IBE 0x00000408 // Interrupt both edges register.\r
+#define GPIO_O_IEV 0x0000040C // Intterupt event register.\r
+#define GPIO_O_IM 0x00000410 // Interrupt mask register.\r
+#define GPIO_O_RIS 0x00000414 // Raw interrupt status register.\r
+#define GPIO_O_MIS 0x00000418 // Masked interrupt status reg.\r
+#define GPIO_O_ICR 0x0000041C // Interrupt clear register.\r
+#define GPIO_O_AFSEL 0x00000420 // Mode control select register.\r
+#define GPIO_O_DR2R 0x00000500 // 2ma drive select register.\r
+#define GPIO_O_DR4R 0x00000504 // 4ma drive select register.\r
+#define GPIO_O_DR8R 0x00000508 // 8ma drive select register.\r
+#define GPIO_O_ODR 0x0000050C // Open drain select register.\r
+#define GPIO_O_PUR 0x00000510 // Pull up select register.\r
+#define GPIO_O_PDR 0x00000514 // Pull down select register.\r
+#define GPIO_O_SLR 0x00000518 // Slew rate control enable reg.\r
+#define GPIO_O_DEN 0x0000051C // Digital input enable register.\r
+#define GPIO_O_LOCK 0x00000520 // Lock register.\r
+#define GPIO_O_CR 0x00000524 // Commit register.\r
+#define GPIO_O_PeriphID4 0x00000FD0 //\r
+#define GPIO_O_PeriphID5 0x00000FD4 //\r
+#define GPIO_O_PeriphID6 0x00000FD8 //\r
+#define GPIO_O_PeriphID7 0x00000FDC //\r
+#define GPIO_O_PeriphID0 0x00000FE0 //\r
+#define GPIO_O_PeriphID1 0x00000FE4 //\r
+#define GPIO_O_PeriphID2 0x00000FE8 //\r
+#define GPIO_O_PeriphID3 0x00000FEC //\r
+#define GPIO_O_PCellID0 0x00000FF0 //\r
+#define GPIO_O_PCellID1 0x00000FF4 //\r
+#define GPIO_O_PCellID2 0x00000FF8 //\r
+#define GPIO_O_PCellID3 0x00000FFC //\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the GPIO_LOCK register.\r
+//\r
+//*****************************************************************************\r
+#define GPIO_LOCK_LOCKED 0x00000001 // GPIO_CR register is locked\r
+#define GPIO_LOCK_UNLOCKED 0x00000000 // GPIO_CR register is unlocked\r
+#define GPIO_LOCK_KEY 0x1ACCE551 // Unlocks the GPIO_CR register\r
+\r
+//*****************************************************************************\r
+//\r
+// GPIO Register reset values.\r
+//\r
+//*****************************************************************************\r
+#define GPIO_RV_DATA 0x00000000 // Data register reset value.\r
+#define GPIO_RV_DIR 0x00000000 // Data direction reg RV.\r
+#define GPIO_RV_IS 0x00000000 // Interrupt sense reg RV.\r
+#define GPIO_RV_IBE 0x00000000 // Interrupt both edges reg RV.\r
+#define GPIO_RV_IEV 0x00000000 // Intterupt event reg RV.\r
+#define GPIO_RV_IM 0x00000000 // Interrupt mask reg RV.\r
+#define GPIO_RV_RIS 0x00000000 // Raw interrupt status reg RV.\r
+#define GPIO_RV_MIS 0x00000000 // Masked interrupt status reg RV.\r
+#define GPIO_RV_IC 0x00000000 // Interrupt clear reg RV.\r
+#define GPIO_RV_AFSEL 0x00000000 // Mode control select reg RV.\r
+#define GPIO_RV_DR2R 0x000000FF // 2ma drive select reg RV.\r
+#define GPIO_RV_DR4R 0x00000000 // 4ma drive select reg RV.\r
+#define GPIO_RV_DR8R 0x00000000 // 8ma drive select reg RV.\r
+#define GPIO_RV_ODR 0x00000000 // Open drain select reg RV.\r
+#define GPIO_RV_PUR 0x000000FF // Pull up select reg RV.\r
+#define GPIO_RV_PDR 0x00000000 // Pull down select reg RV.\r
+#define GPIO_RV_SLR 0x00000000 // Slew rate control enable reg RV.\r
+#define GPIO_RV_DEN 0x000000FF // Digital input enable reg RV.\r
+#define GPIO_RV_LOCK 0x00000001 // Lock register RV.\r
+#define GPIO_RV_PeriphID4 0x00000000 //\r
+#define GPIO_RV_PeriphID5 0x00000000 //\r
+#define GPIO_RV_PeriphID6 0x00000000 //\r
+#define GPIO_RV_PeriphID7 0x00000000 //\r
+#define GPIO_RV_PeriphID0 0x00000061 //\r
+#define GPIO_RV_PeriphID1 0x00000010 //\r
+#define GPIO_RV_PeriphID2 0x00000004 //\r
+#define GPIO_RV_PeriphID3 0x00000000 //\r
+#define GPIO_RV_PCellID0 0x0000000D //\r
+#define GPIO_RV_PCellID1 0x000000F0 //\r
+#define GPIO_RV_PCellID2 0x00000005 //\r
+#define GPIO_RV_PCellID3 0x000000B1 //\r
+\r
+#endif // __HW_GPIO_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_hibernate.h - Defines and Macros for the Hibernation module.\r
+//\r
+// Copyright (c) 2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_HIBERNATE_H__\r
+#define __HW_HIBERNATE_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the addresses of the hibernation module registers.\r
+//\r
+//*****************************************************************************\r
+#define HIB_RTCC 0x400fc000 // Hibernate RTC counter\r
+#define HIB_RTCM0 0x400fc004 // Hibernate RTC match 0\r
+#define HIB_RTCM1 0x400fc008 // Hibernate RTC match 1\r
+#define HIB_RTCLD 0x400fc00C // Hibernate RTC load\r
+#define HIB_CTL 0x400fc010 // Hibernate RTC control\r
+#define HIB_IM 0x400fc014 // Hibernate interrupt mask\r
+#define HIB_RIS 0x400fc018 // Hibernate raw interrupt status\r
+#define HIB_MIS 0x400fc01C // Hibernate masked interrupt stat\r
+#define HIB_IC 0x400fc020 // Hibernate interrupt clear\r
+#define HIB_RTCT 0x400fc024 // Hibernate RTC trim\r
+#define HIB_DATA 0x400fc030 // Hibernate data area\r
+#define HIB_DATA_END 0x400fc130 // end of data area, exclusive\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the Hibernate RTC counter register.\r
+//\r
+//*****************************************************************************\r
+#define HIB_RTCC_MASK 0xffffffff // RTC counter mask\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the Hibernate RTC match 0 register.\r
+//\r
+//*****************************************************************************\r
+#define HIB_RTCM0_MASK 0xffffffff // RTC match 0 mask\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the Hibernate RTC match 1 register.\r
+//\r
+//*****************************************************************************\r
+#define HIB_RTCM1_MASK 0xffffffff // RTC match 1 mask\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the Hibernate RTC load register.\r
+//\r
+//*****************************************************************************\r
+#define HIB_RTCLD_MASK 0xffffffff // RTC load mask\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the Hibernate control register\r
+//\r
+//*****************************************************************************\r
+#define HIB_CTL_VABORT 0x00000080 // low bat abort\r
+#define HIB_CTL_CLK32EN 0x00000040 // enable clock/oscillator\r
+#define HIB_CTL_LOWBATEN 0x00000020 // enable low battery detect\r
+#define HIB_CTL_PINWEN 0x00000010 // enable wake on WAKE pin\r
+#define HIB_CTL_RTCWEN 0x00000008 // enable wake on RTC match\r
+#define HIB_CTL_CLKSEL 0x00000004 // clock input selection\r
+#define HIB_CTL_HIBREQ 0x00000002 // request hibernation\r
+#define HIB_CTL_RTCEN 0x00000001 // RTC enable\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the Hibernate interrupt mask reg.\r
+//\r
+//*****************************************************************************\r
+#define HIB_IM_EXTW 0x00000008 // wake from external pin interrupt\r
+#define HIB_IM_LOWBAT 0x00000004 // low battery interrupt\r
+#define HIB_IM_RTCALT1 0x00000002 // RTC match 1 interrupt\r
+#define HIB_IM_RTCALT0 0x00000001 // RTC match 0 interrupt\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the Hibernate raw interrupt status.\r
+//\r
+//*****************************************************************************\r
+#define HIB_RIS_EXTW 0x00000008 // wake from external pin interrupt\r
+#define HIB_RIS_LOWBAT 0x00000004 // low battery interrupt\r
+#define HIB_RIS_RTCALT1 0x00000002 // RTC match 1 interrupt\r
+#define HIB_RID_RTCALT0 0x00000001 // RTC match 0 interrupt\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the Hibernate masked int status.\r
+//\r
+//*****************************************************************************\r
+#define HIB_MIS_EXTW 0x00000008 // wake from external pin interrupt\r
+#define HIB_MIS_LOWBAT 0x00000004 // low battery interrupt\r
+#define HIB_MIS_RTCALT1 0x00000002 // RTC match 1 interrupt\r
+#define HIB_MID_RTCALT0 0x00000001 // RTC match 0 interrupt\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the Hibernate interrupt clear reg.\r
+//\r
+//*****************************************************************************\r
+#define HIB_IC_EXTW 0x00000008 // wake from external pin interrupt\r
+#define HIB_IC_LOWBAT 0x00000004 // low battery interrupt\r
+#define HIB_IC_RTCALT1 0x00000002 // RTC match 1 interrupt\r
+#define HIB_IC_RTCALT0 0x00000001 // RTC match 0 interrupt\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the Hibernate RTC trim register.\r
+//\r
+//*****************************************************************************\r
+#define HIB_RTCT_MASK 0x0000ffff // RTC trim mask\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the Hibernate data register.\r
+//\r
+//*****************************************************************************\r
+#define HIB_DATA_MASK 0xffffffff // NV memory data mask\r
+\r
+#endif // __HW_HIBERNATE_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_i2c.h - Macros used when accessing the I2C master and slave hardware.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_I2C_H__\r
+#define __HW_I2C_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// The following defines the offset between the I2C master and slave registers.\r
+//\r
+//*****************************************************************************\r
+#define I2C_O_SLAVE 0x00000800 // Offset from master to slave\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the offsets of the I2C master registers.\r
+//\r
+//*****************************************************************************\r
+#define I2C_MASTER_O_SA 0x00000000 // Slave address register\r
+#define I2C_MASTER_O_CS 0x00000004 // Control and Status register\r
+#define I2C_MASTER_O_DR 0x00000008 // Data register\r
+#define I2C_MASTER_O_TPR 0x0000000C // Timer period register\r
+#define I2C_MASTER_O_IMR 0x00000010 // Interrupt mask register\r
+#define I2C_MASTER_O_RIS 0x00000014 // Raw interrupt status register\r
+#define I2C_MASTER_O_MIS 0x00000018 // Masked interrupt status reg\r
+#define I2C_MASTER_O_MICR 0x0000001c // Interrupt clear register\r
+#define I2C_MASTER_O_CR 0x00000020 // Configuration register\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the offsets of the I2C slave registers.\r
+//\r
+//*****************************************************************************\r
+#define I2C_SLAVE_O_OAR 0x00000000 // Own address register\r
+#define I2C_SLAVE_O_CSR 0x00000004 // Control/Status register\r
+#define I2C_SLAVE_O_DR 0x00000008 // Data register\r
+#define I2C_SLAVE_O_IM 0x0000000C // Interrupt mask register\r
+#define I2C_SLAVE_O_RIS 0x00000010 // Raw interrupt status register\r
+#define I2C_SLAVE_O_MIS 0x00000014 // Masked interrupt status reg\r
+#define I2C_SLAVE_O_SICR 0x00000018 // Interrupt clear register\r
+\r
+//*****************************************************************************\r
+//\r
+// The followng define the bit fields in the I2C master slave address register.\r
+//\r
+//*****************************************************************************\r
+#define I2C_MASTER_SA_SA_MASK 0x000000FE // Slave address\r
+#define I2C_MASTER_SA_RS 0x00000001 // Receive/send\r
+#define I2C_MASTER_SA_SA_SHIFT 1\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the I2C Master Control and Status\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define I2C_MASTER_CS_ACK 0x00000008 // Acknowlegde\r
+#define I2C_MASTER_CS_STOP 0x00000004 // Stop\r
+#define I2C_MASTER_CS_START 0x00000002 // Start\r
+#define I2C_MASTER_CS_RUN 0x00000001 // Run\r
+#define I2C_MASTER_CS_BUS_BUSY 0x00000040 // Bus busy\r
+#define I2C_MASTER_CS_IDLE 0x00000020 // Idle\r
+#define I2C_MASTER_CS_ARB_LOST 0x00000010 // Lost arbitration\r
+#define I2C_MASTER_CS_DATA_ACK 0x00000008 // Data byte not acknowledged\r
+#define I2C_MASTER_CS_ADDR_ACK 0x00000004 // Address byte not acknowledged\r
+#define I2C_MASTER_CS_ERROR 0x00000002 // Error occurred\r
+#define I2C_MASTER_CS_BUSY 0x00000001 // Controller is TX/RX data\r
+#define I2C_MASTER_CS_ERR_MASK 0x0000001C\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define values used in determining the contents of the I2C\r
+// Master Timer Period register.\r
+//\r
+//*****************************************************************************\r
+#define I2C_MASTER_TPR_SCL_HP 0x00000004 // SCL high period\r
+#define I2C_MASTER_TPR_SCL_LP 0x00000006 // SCL low period\r
+#define I2C_MASTER_TPR_SCL (I2C_MASTER_TPR_SCL_HP + I2C_MASTER_TPR_SCL_LP)\r
+#define I2C_SCL_STANDARD 100000 // SCL standard frequency\r
+#define I2C_SCL_FAST 400000 // SCL fast frequency\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the I2C Master Interrupt Mask\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define I2C_MASTER_IMR_IM 0x00000001 // Master interrupt mask\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the I2C Master Raw Interrupt Status\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define I2C_MASTER_RIS_RIS 0x00000001 // Master raw interrupt status\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the I2C Master Masked Interrupt\r
+// Status register.\r
+//\r
+//*****************************************************************************\r
+#define I2C_MASTER_MIS_MIS 0x00000001 // Master masked interrupt status\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the I2C Master Interrupt Clear\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define I2C_MASTER_MICR_IC 0x00000001 // Master interrupt clear\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the I2C Master Configuration\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define I2C_MASTER_CR_SFE 0x00000020 // Slave function enable\r
+#define I2C_MASTER_CR_MFE 0x00000010 // Master function enable\r
+#define I2C_MASTER_CR_LPBK 0x00000001 // Loopback enable\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the I2C Slave Own Address register.\r
+//\r
+//*****************************************************************************\r
+#define I2C_SLAVE_SOAR_OAR_MASK 0x0000007F // Slave address\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the I2C Slave Control/Status\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define I2C_SLAVE_CSR_DA 0x00000001 // Enable the device\r
+#define I2C_SLAVE_CSR_TREQ 0x00000002 // Transmit request received\r
+#define I2C_SLAVE_CSR_RREQ 0x00000001 // Receive data from I2C master\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the I2C Slave Interrupt Mask\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define I2C_SLAVE_IMR_IM 0x00000001 // Slave interrupt mask\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the I2C Slave Raw Interrupt Status\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define I2C_SLAVE_RIS_RIS 0x00000001 // Slave raw interrupt status\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the I2C Slave Masked Interrupt\r
+// Status register.\r
+//\r
+//*****************************************************************************\r
+#define I2C_SLAVE_MIS_MIS 0x00000001 // Slave masked interrupt status\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the I2C Slave Interrupt Clear\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define I2C_SLAVE_SICR_IC 0x00000001 // Slave interrupt clear\r
+\r
+#endif // __HW_I2C_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_ints.h - Macros that define the interrupt assignment on Stellaris.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_INTS_H__\r
+#define __HW_INTS_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the fault assignments.\r
+//\r
+//*****************************************************************************\r
+#define FAULT_NMI 2 // NMI fault\r
+#define FAULT_HARD 3 // Hard fault\r
+#define FAULT_MPU 4 // MPU fault\r
+#define FAULT_BUS 5 // Bus fault\r
+#define FAULT_USAGE 6 // Usage fault\r
+#define FAULT_SVCALL 11 // SVCall\r
+#define FAULT_DEBUG 12 // Debug monitor\r
+#define FAULT_PENDSV 14 // PendSV\r
+#define FAULT_SYSTICK 15 // System Tick\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the interrupt assignments.\r
+//\r
+//*****************************************************************************\r
+#define INT_GPIOA 16 // GPIO Port A\r
+#define INT_GPIOB 17 // GPIO Port B\r
+#define INT_GPIOC 18 // GPIO Port C\r
+#define INT_GPIOD 19 // GPIO Port D\r
+#define INT_GPIOE 20 // GPIO Port E\r
+#define INT_UART0 21 // UART0 Rx and Tx\r
+#define INT_UART1 22 // UART1 Rx and Tx\r
+#define INT_SSI 23 // SSI Rx and Tx\r
+#define INT_SSI0 23 // SSI0 Rx and Tx\r
+#define INT_I2C 24 // I2C Master and Slave\r
+#define INT_I2C0 24 // I2C0 Master and Slave\r
+#define INT_PWM_FAULT 25 // PWM Fault\r
+#define INT_PWM0 26 // PWM Generator 0\r
+#define INT_PWM1 27 // PWM Generator 1\r
+#define INT_PWM2 28 // PWM Generator 2\r
+#define INT_QEI 29 // Quadrature Encoder\r
+#define INT_QEI0 29 // Quadrature Encoder 0\r
+#define INT_ADC0 30 // ADC Sequence 0\r
+#define INT_ADC1 31 // ADC Sequence 1\r
+#define INT_ADC2 32 // ADC Sequence 2\r
+#define INT_ADC3 33 // ADC Sequence 3\r
+#define INT_WATCHDOG 34 // Watchdog timer\r
+#define INT_TIMER0A 35 // Timer 0 subtimer A\r
+#define INT_TIMER0B 36 // Timer 0 subtimer B\r
+#define INT_TIMER1A 37 // Timer 1 subtimer A\r
+#define INT_TIMER1B 38 // Timer 1 subtimer B\r
+#define INT_TIMER2A 39 // Timer 2 subtimer A\r
+#define INT_TIMER2B 40 // Timer 2 subtimer B\r
+#define INT_COMP0 41 // Analog Comparator 0\r
+#define INT_COMP1 42 // Analog Comparator 1\r
+#define INT_COMP2 43 // Analog Comparator 2\r
+#define INT_SYSCTL 44 // System Control (PLL, OSC, BO)\r
+#define INT_FLASH 45 // FLASH Control\r
+#define INT_GPIOF 46 // GPIO Port F\r
+#define INT_GPIOG 47 // GPIO Port G\r
+#define INT_GPIOH 48 // GPIO Port H\r
+#define INT_UART2 49 // UART2 Rx and Tx\r
+#define INT_SSI1 50 // SSI1 Rx and Tx\r
+#define INT_TIMER3A 51 // Timer 3 subtimer A\r
+#define INT_TIMER3B 52 // Timer 3 subtimer B\r
+#define INT_I2C1 53 // I2C1 Master and Slave\r
+#define INT_QEI1 54 // Quadrature Encoder 1\r
+#define INT_CAN0 55 // CAN0\r
+#define INT_CAN1 56 // CAN1\r
+#define INT_ETH 58 // Ethernet\r
+#define INT_HIBERNATE 59 // Hibernation module\r
+\r
+//*****************************************************************************\r
+//\r
+// The total number of interrupts.\r
+//\r
+//*****************************************************************************\r
+#define NUM_INTERRUPTS 60\r
+\r
+//*****************************************************************************\r
+//\r
+// The total number of priority levels.\r
+//\r
+//*****************************************************************************\r
+#define NUM_PRIORITY 8\r
+#define NUM_PRIORITY_BITS 3\r
+\r
+#endif // __HW_INTS_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_memmap.h - Macros defining the memory map of Stellaris.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_MEMMAP_H__\r
+#define __HW_MEMMAP_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the base address of the memories and peripherals.\r
+//\r
+//*****************************************************************************\r
+#define FLASH_BASE 0x00000000 // FLASH memory\r
+#define SRAM_BASE 0x20000000 // SRAM memory\r
+#define WATCHDOG_BASE 0x40000000 // Watchdog\r
+#define GPIO_PORTA_BASE 0x40004000 // GPIO Port A\r
+#define GPIO_PORTB_BASE 0x40005000 // GPIO Port B\r
+#define GPIO_PORTC_BASE 0x40006000 // GPIO Port C\r
+#define GPIO_PORTD_BASE 0x40007000 // GPIO Port D\r
+#define SSI_BASE 0x40008000 // SSI\r
+#define SSI0_BASE 0x40008000 // SSI0\r
+#define SSI1_BASE 0x40009000 // SSI1\r
+#define UART0_BASE 0x4000C000 // UART0\r
+#define UART1_BASE 0x4000D000 // UART1\r
+#define UART2_BASE 0x4000E000 // UART2\r
+#define I2C_MASTER_BASE 0x40020000 // I2C Master\r
+#define I2C_SLAVE_BASE 0x40020800 // I2C Slave\r
+#define I2C0_MASTER_BASE 0x40020000 // I2C0 Master\r
+#define I2C0_SLAVE_BASE 0x40020800 // I2C0 Slave\r
+#define I2C1_MASTER_BASE 0x40021000 // I2C1 Master\r
+#define I2C1_SLAVE_BASE 0x40021800 // I2C1 Slave\r
+#define GPIO_PORTE_BASE 0x40024000 // GPIO Port E\r
+#define GPIO_PORTF_BASE 0x40025000 // GPIO Port F\r
+#define GPIO_PORTG_BASE 0x40026000 // GPIO Port G\r
+#define GPIO_PORTH_BASE 0x40027000 // GPIO Port H\r
+#define PWM_BASE 0x40028000 // PWM\r
+#define QEI_BASE 0x4002C000 // QEI\r
+#define QEI0_BASE 0x4002C000 // QEI0\r
+#define QEI1_BASE 0x4002D000 // QEI1\r
+#define TIMER0_BASE 0x40030000 // Timer0\r
+#define TIMER1_BASE 0x40031000 // Timer1\r
+#define TIMER2_BASE 0x40032000 // Timer2\r
+#define TIMER3_BASE 0x40033000 // Timer3\r
+#define ADC_BASE 0x40038000 // ADC\r
+#define COMP_BASE 0x4003C000 // Analog comparators\r
+#define CAN0_BASE 0x40040000 // CAN0\r
+#define CAN1_BASE 0x40041000 // CAN1\r
+#define ETH_BASE 0x40048000 // Ethernet\r
+#define FLASH_CTRL_BASE 0x400FD000 // FLASH Controller\r
+#define SYSCTL_BASE 0x400FE000 // System Control\r
+#define ITM_BASE 0xE0000000 // Instrumentation Trace Macrocell\r
+#define DWT_BASE 0xE0001000 // Data Watchpoint and Trace\r
+#define FPB_BASE 0xE0002000 // FLASH Patch and Breakpoint\r
+#define NVIC_BASE 0xE000E000 // Nested Vectored Interrupt Ctrl\r
+#define TPIU_BASE 0xE0040000 // Trace Port Interface Unit\r
+\r
+#endif // __HW_MEMMAP_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_nvic.h - Macros used when accessing the NVIC hardware.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_NVIC_H__\r
+#define __HW_NVIC_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the addresses of the NVIC registers.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_INT_TYPE 0xE000E004 // Interrupt Controller Type Reg.\r
+#define NVIC_ST_CTRL 0xE000E010 // SysTick Control and Status Reg.\r
+#define NVIC_ST_RELOAD 0xE000E014 // SysTick Reload Value Register\r
+#define NVIC_ST_CURRENT 0xE000E018 // SysTick Current Value Register\r
+#define NVIC_ST_CAL 0xE000E01C // SysTick Calibration Value Reg.\r
+#define NVIC_EN0 0xE000E100 // IRQ 0 to 31 Set Enable Register\r
+#define NVIC_EN1 0xE000E104 // IRQ 32 to 63 Set Enable Register\r
+#define NVIC_DIS0 0xE000E180 // IRQ 0 to 31 Clear Enable Reg.\r
+#define NVIC_DIS1 0xE000E184 // IRQ 32 to 63 Clear Enable Reg.\r
+#define NVIC_PEND0 0xE000E200 // IRQ 0 to 31 Set Pending Register\r
+#define NVIC_PEND1 0xE000E204 // IRQ 32 to 63 Set Pending Reg.\r
+#define NVIC_UNPEND0 0xE000E280 // IRQ 0 to 31 Clear Pending Reg.\r
+#define NVIC_UNPEND1 0xE000E284 // IRQ 32 to 63 Clear Pending Reg.\r
+#define NVIC_ACTIVE0 0xE000E300 // IRQ 0 to 31 Active Register\r
+#define NVIC_ACTIVE1 0xE000E304 // IRQ 32 to 63 Active Register\r
+#define NVIC_PRI0 0xE000E400 // IRQ 0 to 3 Priority Register\r
+#define NVIC_PRI1 0xE000E404 // IRQ 4 to 7 Priority Register\r
+#define NVIC_PRI2 0xE000E408 // IRQ 8 to 11 Priority Register\r
+#define NVIC_PRI3 0xE000E40C // IRQ 12 to 15 Priority Register\r
+#define NVIC_PRI4 0xE000E410 // IRQ 16 to 19 Priority Register\r
+#define NVIC_PRI5 0xE000E414 // IRQ 20 to 23 Priority Register\r
+#define NVIC_PRI6 0xE000E418 // IRQ 24 to 27 Priority Register\r
+#define NVIC_PRI7 0xE000E41C // IRQ 28 to 31 Priority Register\r
+#define NVIC_PRI8 0xE000E420 // IRQ 32 to 35 Priority Register\r
+#define NVIC_PRI9 0xE000E424 // IRQ 36 to 39 Priority Register\r
+#define NVIC_PRI10 0xE000E428 // IRQ 40 to 43 Priority Register\r
+#define NVIC_CPUID 0xE000ED00 // CPUID Base Register\r
+#define NVIC_INT_CTRL 0xE000ED04 // Interrupt Control State Register\r
+#define NVIC_VTABLE 0xE000ED08 // Vector Table Offset Register\r
+#define NVIC_APINT 0xE000ED0C // App. Int & Reset Control Reg.\r
+#define NVIC_SYS_CTRL 0xE000ED10 // System Control Register\r
+#define NVIC_CFG_CTRL 0xE000ED14 // Configuration Control Register\r
+#define NVIC_SYS_PRI1 0xE000ED18 // Sys. Handlers 4 to 7 Priority\r
+#define NVIC_SYS_PRI2 0xE000ED1C // Sys. Handlers 8 to 11 Priority\r
+#define NVIC_SYS_PRI3 0xE000ED20 // Sys. Handlers 12 to 15 Priority\r
+#define NVIC_SYS_HND_CTRL 0xE000ED24 // System Handler Control and State\r
+#define NVIC_FAULT_STAT 0xE000ED28 // Configurable Fault Status Reg.\r
+#define NVIC_HFAULT_STAT 0xE000ED2C // Hard Fault Status Register\r
+#define NVIC_DEBUG_STAT 0xE000ED30 // Debug Status Register\r
+#define NVIC_MM_ADDR 0xE000ED34 // Mem Manage Address Register\r
+#define NVIC_FAULT_ADDR 0xE000ED38 // Bus Fault Address Register\r
+#define NVIC_MPU_TYPE 0xE000ED90 // MPU Type Register\r
+#define NVIC_MPU_CTRL 0xE000ED94 // MPU Control Register\r
+#define NVIC_MPU_NUMBER 0xE000ED98 // MPU Region Number Register\r
+#define NVIC_MPU_BASE 0xE000ED9C // MPU Region Base Address Register\r
+#define NVIC_MPU_ATTR 0xE000EDA0 // MPU Region Attribute & Size Reg.\r
+#define NVIC_DBG_CTRL 0xE000EDF0 // Debug Control and Status Reg.\r
+#define NVIC_DBG_XFER 0xE000EDF4 // Debug Core Reg. Transfer Select\r
+#define NVIC_DBG_DATA 0xE000EDF8 // Debug Core Register Data\r
+#define NVIC_DBG_INT 0xE000EDFC // Debug Reset Interrupt Control\r
+#define NVIC_SW_TRIG 0xE000EF00 // Software Trigger Interrupt Reg.\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_INT_TYPE register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_INT_TYPE_LINES_M 0x0000001F // Number of interrupt lines (x32)\r
+#define NVIC_INT_TYPE_LINES_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_ST_CTRL register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_ST_CTRL_COUNT 0x00010000 // Count flag\r
+#define NVIC_ST_CTRL_CLK_SRC 0x00000004 // Clock Source\r
+#define NVIC_ST_CTRL_INTEN 0x00000002 // Interrupt enable\r
+#define NVIC_ST_CTRL_ENABLE 0x00000001 // Counter mode\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_ST_RELOAD register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_ST_RELOAD_M 0x00FFFFFF // Counter load value\r
+#define NVIC_ST_RELOAD_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_ST_CURRENT register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_ST_CURRENT_M 0x00FFFFFF // Counter current value\r
+#define NVIC_ST_CURRENT_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_ST_CAL register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_ST_CAL_NOREF 0x80000000 // No reference clock\r
+#define NVIC_ST_CAL_SKEW 0x40000000 // Clock skew\r
+#define NVIC_ST_CAL_ONEMS_M 0x00FFFFFF // 1ms reference value\r
+#define NVIC_ST_CAL_ONEMS_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_EN0 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_EN0_INT31 0x80000000 // Interrupt 31 enable\r
+#define NVIC_EN0_INT30 0x40000000 // Interrupt 30 enable\r
+#define NVIC_EN0_INT29 0x20000000 // Interrupt 29 enable\r
+#define NVIC_EN0_INT28 0x10000000 // Interrupt 28 enable\r
+#define NVIC_EN0_INT27 0x08000000 // Interrupt 27 enable\r
+#define NVIC_EN0_INT26 0x04000000 // Interrupt 26 enable\r
+#define NVIC_EN0_INT25 0x02000000 // Interrupt 25 enable\r
+#define NVIC_EN0_INT24 0x01000000 // Interrupt 24 enable\r
+#define NVIC_EN0_INT23 0x00800000 // Interrupt 23 enable\r
+#define NVIC_EN0_INT22 0x00400000 // Interrupt 22 enable\r
+#define NVIC_EN0_INT21 0x00200000 // Interrupt 21 enable\r
+#define NVIC_EN0_INT20 0x00100000 // Interrupt 20 enable\r
+#define NVIC_EN0_INT19 0x00080000 // Interrupt 19 enable\r
+#define NVIC_EN0_INT18 0x00040000 // Interrupt 18 enable\r
+#define NVIC_EN0_INT17 0x00020000 // Interrupt 17 enable\r
+#define NVIC_EN0_INT16 0x00010000 // Interrupt 16 enable\r
+#define NVIC_EN0_INT15 0x00008000 // Interrupt 15 enable\r
+#define NVIC_EN0_INT14 0x00004000 // Interrupt 14 enable\r
+#define NVIC_EN0_INT13 0x00002000 // Interrupt 13 enable\r
+#define NVIC_EN0_INT12 0x00001000 // Interrupt 12 enable\r
+#define NVIC_EN0_INT11 0x00000800 // Interrupt 11 enable\r
+#define NVIC_EN0_INT10 0x00000400 // Interrupt 10 enable\r
+#define NVIC_EN0_INT9 0x00000200 // Interrupt 9 enable\r
+#define NVIC_EN0_INT8 0x00000100 // Interrupt 8 enable\r
+#define NVIC_EN0_INT7 0x00000080 // Interrupt 7 enable\r
+#define NVIC_EN0_INT6 0x00000040 // Interrupt 6 enable\r
+#define NVIC_EN0_INT5 0x00000020 // Interrupt 5 enable\r
+#define NVIC_EN0_INT4 0x00000010 // Interrupt 4 enable\r
+#define NVIC_EN0_INT3 0x00000008 // Interrupt 3 enable\r
+#define NVIC_EN0_INT2 0x00000004 // Interrupt 2 enable\r
+#define NVIC_EN0_INT1 0x00000002 // Interrupt 1 enable\r
+#define NVIC_EN0_INT0 0x00000001 // Interrupt 0 enable\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_EN1 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_EN1_INT59 0x08000000 // Interrupt 59 enable\r
+#define NVIC_EN1_INT58 0x04000000 // Interrupt 58 enable\r
+#define NVIC_EN1_INT57 0x02000000 // Interrupt 57 enable\r
+#define NVIC_EN1_INT56 0x01000000 // Interrupt 56 enable\r
+#define NVIC_EN1_INT55 0x00800000 // Interrupt 55 enable\r
+#define NVIC_EN1_INT54 0x00400000 // Interrupt 54 enable\r
+#define NVIC_EN1_INT53 0x00200000 // Interrupt 53 enable\r
+#define NVIC_EN1_INT52 0x00100000 // Interrupt 52 enable\r
+#define NVIC_EN1_INT51 0x00080000 // Interrupt 51 enable\r
+#define NVIC_EN1_INT50 0x00040000 // Interrupt 50 enable\r
+#define NVIC_EN1_INT49 0x00020000 // Interrupt 49 enable\r
+#define NVIC_EN1_INT48 0x00010000 // Interrupt 48 enable\r
+#define NVIC_EN1_INT47 0x00008000 // Interrupt 47 enable\r
+#define NVIC_EN1_INT46 0x00004000 // Interrupt 46 enable\r
+#define NVIC_EN1_INT45 0x00002000 // Interrupt 45 enable\r
+#define NVIC_EN1_INT44 0x00001000 // Interrupt 44 enable\r
+#define NVIC_EN1_INT43 0x00000800 // Interrupt 43 enable\r
+#define NVIC_EN1_INT42 0x00000400 // Interrupt 42 enable\r
+#define NVIC_EN1_INT41 0x00000200 // Interrupt 41 enable\r
+#define NVIC_EN1_INT40 0x00000100 // Interrupt 40 enable\r
+#define NVIC_EN1_INT39 0x00000080 // Interrupt 39 enable\r
+#define NVIC_EN1_INT38 0x00000040 // Interrupt 38 enable\r
+#define NVIC_EN1_INT37 0x00000020 // Interrupt 37 enable\r
+#define NVIC_EN1_INT36 0x00000010 // Interrupt 36 enable\r
+#define NVIC_EN1_INT35 0x00000008 // Interrupt 35 enable\r
+#define NVIC_EN1_INT34 0x00000004 // Interrupt 34 enable\r
+#define NVIC_EN1_INT33 0x00000002 // Interrupt 33 enable\r
+#define NVIC_EN1_INT32 0x00000001 // Interrupt 32 enable\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_DIS0 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_DIS0_INT31 0x80000000 // Interrupt 31 disable\r
+#define NVIC_DIS0_INT30 0x40000000 // Interrupt 30 disable\r
+#define NVIC_DIS0_INT29 0x20000000 // Interrupt 29 disable\r
+#define NVIC_DIS0_INT28 0x10000000 // Interrupt 28 disable\r
+#define NVIC_DIS0_INT27 0x08000000 // Interrupt 27 disable\r
+#define NVIC_DIS0_INT26 0x04000000 // Interrupt 26 disable\r
+#define NVIC_DIS0_INT25 0x02000000 // Interrupt 25 disable\r
+#define NVIC_DIS0_INT24 0x01000000 // Interrupt 24 disable\r
+#define NVIC_DIS0_INT23 0x00800000 // Interrupt 23 disable\r
+#define NVIC_DIS0_INT22 0x00400000 // Interrupt 22 disable\r
+#define NVIC_DIS0_INT21 0x00200000 // Interrupt 21 disable\r
+#define NVIC_DIS0_INT20 0x00100000 // Interrupt 20 disable\r
+#define NVIC_DIS0_INT19 0x00080000 // Interrupt 19 disable\r
+#define NVIC_DIS0_INT18 0x00040000 // Interrupt 18 disable\r
+#define NVIC_DIS0_INT17 0x00020000 // Interrupt 17 disable\r
+#define NVIC_DIS0_INT16 0x00010000 // Interrupt 16 disable\r
+#define NVIC_DIS0_INT15 0x00008000 // Interrupt 15 disable\r
+#define NVIC_DIS0_INT14 0x00004000 // Interrupt 14 disable\r
+#define NVIC_DIS0_INT13 0x00002000 // Interrupt 13 disable\r
+#define NVIC_DIS0_INT12 0x00001000 // Interrupt 12 disable\r
+#define NVIC_DIS0_INT11 0x00000800 // Interrupt 11 disable\r
+#define NVIC_DIS0_INT10 0x00000400 // Interrupt 10 disable\r
+#define NVIC_DIS0_INT9 0x00000200 // Interrupt 9 disable\r
+#define NVIC_DIS0_INT8 0x00000100 // Interrupt 8 disable\r
+#define NVIC_DIS0_INT7 0x00000080 // Interrupt 7 disable\r
+#define NVIC_DIS0_INT6 0x00000040 // Interrupt 6 disable\r
+#define NVIC_DIS0_INT5 0x00000020 // Interrupt 5 disable\r
+#define NVIC_DIS0_INT4 0x00000010 // Interrupt 4 disable\r
+#define NVIC_DIS0_INT3 0x00000008 // Interrupt 3 disable\r
+#define NVIC_DIS0_INT2 0x00000004 // Interrupt 2 disable\r
+#define NVIC_DIS0_INT1 0x00000002 // Interrupt 1 disable\r
+#define NVIC_DIS0_INT0 0x00000001 // Interrupt 0 disable\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_DIS1 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_DIS1_INT59 0x08000000 // Interrupt 59 disable\r
+#define NVIC_DIS1_INT58 0x04000000 // Interrupt 58 disable\r
+#define NVIC_DIS1_INT57 0x02000000 // Interrupt 57 disable\r
+#define NVIC_DIS1_INT56 0x01000000 // Interrupt 56 disable\r
+#define NVIC_DIS1_INT55 0x00800000 // Interrupt 55 disable\r
+#define NVIC_DIS1_INT54 0x00400000 // Interrupt 54 disable\r
+#define NVIC_DIS1_INT53 0x00200000 // Interrupt 53 disable\r
+#define NVIC_DIS1_INT52 0x00100000 // Interrupt 52 disable\r
+#define NVIC_DIS1_INT51 0x00080000 // Interrupt 51 disable\r
+#define NVIC_DIS1_INT50 0x00040000 // Interrupt 50 disable\r
+#define NVIC_DIS1_INT49 0x00020000 // Interrupt 49 disable\r
+#define NVIC_DIS1_INT48 0x00010000 // Interrupt 48 disable\r
+#define NVIC_DIS1_INT47 0x00008000 // Interrupt 47 disable\r
+#define NVIC_DIS1_INT46 0x00004000 // Interrupt 46 disable\r
+#define NVIC_DIS1_INT45 0x00002000 // Interrupt 45 disable\r
+#define NVIC_DIS1_INT44 0x00001000 // Interrupt 44 disable\r
+#define NVIC_DIS1_INT43 0x00000800 // Interrupt 43 disable\r
+#define NVIC_DIS1_INT42 0x00000400 // Interrupt 42 disable\r
+#define NVIC_DIS1_INT41 0x00000200 // Interrupt 41 disable\r
+#define NVIC_DIS1_INT40 0x00000100 // Interrupt 40 disable\r
+#define NVIC_DIS1_INT39 0x00000080 // Interrupt 39 disable\r
+#define NVIC_DIS1_INT38 0x00000040 // Interrupt 38 disable\r
+#define NVIC_DIS1_INT37 0x00000020 // Interrupt 37 disable\r
+#define NVIC_DIS1_INT36 0x00000010 // Interrupt 36 disable\r
+#define NVIC_DIS1_INT35 0x00000008 // Interrupt 35 disable\r
+#define NVIC_DIS1_INT34 0x00000004 // Interrupt 34 disable\r
+#define NVIC_DIS1_INT33 0x00000002 // Interrupt 33 disable\r
+#define NVIC_DIS1_INT32 0x00000001 // Interrupt 32 disable\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_PEND0 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_PEND0_INT31 0x80000000 // Interrupt 31 pend\r
+#define NVIC_PEND0_INT30 0x40000000 // Interrupt 30 pend\r
+#define NVIC_PEND0_INT29 0x20000000 // Interrupt 29 pend\r
+#define NVIC_PEND0_INT28 0x10000000 // Interrupt 28 pend\r
+#define NVIC_PEND0_INT27 0x08000000 // Interrupt 27 pend\r
+#define NVIC_PEND0_INT26 0x04000000 // Interrupt 26 pend\r
+#define NVIC_PEND0_INT25 0x02000000 // Interrupt 25 pend\r
+#define NVIC_PEND0_INT24 0x01000000 // Interrupt 24 pend\r
+#define NVIC_PEND0_INT23 0x00800000 // Interrupt 23 pend\r
+#define NVIC_PEND0_INT22 0x00400000 // Interrupt 22 pend\r
+#define NVIC_PEND0_INT21 0x00200000 // Interrupt 21 pend\r
+#define NVIC_PEND0_INT20 0x00100000 // Interrupt 20 pend\r
+#define NVIC_PEND0_INT19 0x00080000 // Interrupt 19 pend\r
+#define NVIC_PEND0_INT18 0x00040000 // Interrupt 18 pend\r
+#define NVIC_PEND0_INT17 0x00020000 // Interrupt 17 pend\r
+#define NVIC_PEND0_INT16 0x00010000 // Interrupt 16 pend\r
+#define NVIC_PEND0_INT15 0x00008000 // Interrupt 15 pend\r
+#define NVIC_PEND0_INT14 0x00004000 // Interrupt 14 pend\r
+#define NVIC_PEND0_INT13 0x00002000 // Interrupt 13 pend\r
+#define NVIC_PEND0_INT12 0x00001000 // Interrupt 12 pend\r
+#define NVIC_PEND0_INT11 0x00000800 // Interrupt 11 pend\r
+#define NVIC_PEND0_INT10 0x00000400 // Interrupt 10 pend\r
+#define NVIC_PEND0_INT9 0x00000200 // Interrupt 9 pend\r
+#define NVIC_PEND0_INT8 0x00000100 // Interrupt 8 pend\r
+#define NVIC_PEND0_INT7 0x00000080 // Interrupt 7 pend\r
+#define NVIC_PEND0_INT6 0x00000040 // Interrupt 6 pend\r
+#define NVIC_PEND0_INT5 0x00000020 // Interrupt 5 pend\r
+#define NVIC_PEND0_INT4 0x00000010 // Interrupt 4 pend\r
+#define NVIC_PEND0_INT3 0x00000008 // Interrupt 3 pend\r
+#define NVIC_PEND0_INT2 0x00000004 // Interrupt 2 pend\r
+#define NVIC_PEND0_INT1 0x00000002 // Interrupt 1 pend\r
+#define NVIC_PEND0_INT0 0x00000001 // Interrupt 0 pend\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_PEND1 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_PEND1_INT59 0x08000000 // Interrupt 59 pend\r
+#define NVIC_PEND1_INT58 0x04000000 // Interrupt 58 pend\r
+#define NVIC_PEND1_INT57 0x02000000 // Interrupt 57 pend\r
+#define NVIC_PEND1_INT56 0x01000000 // Interrupt 56 pend\r
+#define NVIC_PEND1_INT55 0x00800000 // Interrupt 55 pend\r
+#define NVIC_PEND1_INT54 0x00400000 // Interrupt 54 pend\r
+#define NVIC_PEND1_INT53 0x00200000 // Interrupt 53 pend\r
+#define NVIC_PEND1_INT52 0x00100000 // Interrupt 52 pend\r
+#define NVIC_PEND1_INT51 0x00080000 // Interrupt 51 pend\r
+#define NVIC_PEND1_INT50 0x00040000 // Interrupt 50 pend\r
+#define NVIC_PEND1_INT49 0x00020000 // Interrupt 49 pend\r
+#define NVIC_PEND1_INT48 0x00010000 // Interrupt 48 pend\r
+#define NVIC_PEND1_INT47 0x00008000 // Interrupt 47 pend\r
+#define NVIC_PEND1_INT46 0x00004000 // Interrupt 46 pend\r
+#define NVIC_PEND1_INT45 0x00002000 // Interrupt 45 pend\r
+#define NVIC_PEND1_INT44 0x00001000 // Interrupt 44 pend\r
+#define NVIC_PEND1_INT43 0x00000800 // Interrupt 43 pend\r
+#define NVIC_PEND1_INT42 0x00000400 // Interrupt 42 pend\r
+#define NVIC_PEND1_INT41 0x00000200 // Interrupt 41 pend\r
+#define NVIC_PEND1_INT40 0x00000100 // Interrupt 40 pend\r
+#define NVIC_PEND1_INT39 0x00000080 // Interrupt 39 pend\r
+#define NVIC_PEND1_INT38 0x00000040 // Interrupt 38 pend\r
+#define NVIC_PEND1_INT37 0x00000020 // Interrupt 37 pend\r
+#define NVIC_PEND1_INT36 0x00000010 // Interrupt 36 pend\r
+#define NVIC_PEND1_INT35 0x00000008 // Interrupt 35 pend\r
+#define NVIC_PEND1_INT34 0x00000004 // Interrupt 34 pend\r
+#define NVIC_PEND1_INT33 0x00000002 // Interrupt 33 pend\r
+#define NVIC_PEND1_INT32 0x00000001 // Interrupt 32 pend\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_UNPEND0 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_UNPEND0_INT31 0x80000000 // Interrupt 31 unpend\r
+#define NVIC_UNPEND0_INT30 0x40000000 // Interrupt 30 unpend\r
+#define NVIC_UNPEND0_INT29 0x20000000 // Interrupt 29 unpend\r
+#define NVIC_UNPEND0_INT28 0x10000000 // Interrupt 28 unpend\r
+#define NVIC_UNPEND0_INT27 0x08000000 // Interrupt 27 unpend\r
+#define NVIC_UNPEND0_INT26 0x04000000 // Interrupt 26 unpend\r
+#define NVIC_UNPEND0_INT25 0x02000000 // Interrupt 25 unpend\r
+#define NVIC_UNPEND0_INT24 0x01000000 // Interrupt 24 unpend\r
+#define NVIC_UNPEND0_INT23 0x00800000 // Interrupt 23 unpend\r
+#define NVIC_UNPEND0_INT22 0x00400000 // Interrupt 22 unpend\r
+#define NVIC_UNPEND0_INT21 0x00200000 // Interrupt 21 unpend\r
+#define NVIC_UNPEND0_INT20 0x00100000 // Interrupt 20 unpend\r
+#define NVIC_UNPEND0_INT19 0x00080000 // Interrupt 19 unpend\r
+#define NVIC_UNPEND0_INT18 0x00040000 // Interrupt 18 unpend\r
+#define NVIC_UNPEND0_INT17 0x00020000 // Interrupt 17 unpend\r
+#define NVIC_UNPEND0_INT16 0x00010000 // Interrupt 16 unpend\r
+#define NVIC_UNPEND0_INT15 0x00008000 // Interrupt 15 unpend\r
+#define NVIC_UNPEND0_INT14 0x00004000 // Interrupt 14 unpend\r
+#define NVIC_UNPEND0_INT13 0x00002000 // Interrupt 13 unpend\r
+#define NVIC_UNPEND0_INT12 0x00001000 // Interrupt 12 unpend\r
+#define NVIC_UNPEND0_INT11 0x00000800 // Interrupt 11 unpend\r
+#define NVIC_UNPEND0_INT10 0x00000400 // Interrupt 10 unpend\r
+#define NVIC_UNPEND0_INT9 0x00000200 // Interrupt 9 unpend\r
+#define NVIC_UNPEND0_INT8 0x00000100 // Interrupt 8 unpend\r
+#define NVIC_UNPEND0_INT7 0x00000080 // Interrupt 7 unpend\r
+#define NVIC_UNPEND0_INT6 0x00000040 // Interrupt 6 unpend\r
+#define NVIC_UNPEND0_INT5 0x00000020 // Interrupt 5 unpend\r
+#define NVIC_UNPEND0_INT4 0x00000010 // Interrupt 4 unpend\r
+#define NVIC_UNPEND0_INT3 0x00000008 // Interrupt 3 unpend\r
+#define NVIC_UNPEND0_INT2 0x00000004 // Interrupt 2 unpend\r
+#define NVIC_UNPEND0_INT1 0x00000002 // Interrupt 1 unpend\r
+#define NVIC_UNPEND0_INT0 0x00000001 // Interrupt 0 unpend\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_UNPEND1 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_UNPEND1_INT59 0x08000000 // Interrupt 59 unpend\r
+#define NVIC_UNPEND1_INT58 0x04000000 // Interrupt 58 unpend\r
+#define NVIC_UNPEND1_INT57 0x02000000 // Interrupt 57 unpend\r
+#define NVIC_UNPEND1_INT56 0x01000000 // Interrupt 56 unpend\r
+#define NVIC_UNPEND1_INT55 0x00800000 // Interrupt 55 unpend\r
+#define NVIC_UNPEND1_INT54 0x00400000 // Interrupt 54 unpend\r
+#define NVIC_UNPEND1_INT53 0x00200000 // Interrupt 53 unpend\r
+#define NVIC_UNPEND1_INT52 0x00100000 // Interrupt 52 unpend\r
+#define NVIC_UNPEND1_INT51 0x00080000 // Interrupt 51 unpend\r
+#define NVIC_UNPEND1_INT50 0x00040000 // Interrupt 50 unpend\r
+#define NVIC_UNPEND1_INT49 0x00020000 // Interrupt 49 unpend\r
+#define NVIC_UNPEND1_INT48 0x00010000 // Interrupt 48 unpend\r
+#define NVIC_UNPEND1_INT47 0x00008000 // Interrupt 47 unpend\r
+#define NVIC_UNPEND1_INT46 0x00004000 // Interrupt 46 unpend\r
+#define NVIC_UNPEND1_INT45 0x00002000 // Interrupt 45 unpend\r
+#define NVIC_UNPEND1_INT44 0x00001000 // Interrupt 44 unpend\r
+#define NVIC_UNPEND1_INT43 0x00000800 // Interrupt 43 unpend\r
+#define NVIC_UNPEND1_INT42 0x00000400 // Interrupt 42 unpend\r
+#define NVIC_UNPEND1_INT41 0x00000200 // Interrupt 41 unpend\r
+#define NVIC_UNPEND1_INT40 0x00000100 // Interrupt 40 unpend\r
+#define NVIC_UNPEND1_INT39 0x00000080 // Interrupt 39 unpend\r
+#define NVIC_UNPEND1_INT38 0x00000040 // Interrupt 38 unpend\r
+#define NVIC_UNPEND1_INT37 0x00000020 // Interrupt 37 unpend\r
+#define NVIC_UNPEND1_INT36 0x00000010 // Interrupt 36 unpend\r
+#define NVIC_UNPEND1_INT35 0x00000008 // Interrupt 35 unpend\r
+#define NVIC_UNPEND1_INT34 0x00000004 // Interrupt 34 unpend\r
+#define NVIC_UNPEND1_INT33 0x00000002 // Interrupt 33 unpend\r
+#define NVIC_UNPEND1_INT32 0x00000001 // Interrupt 32 unpend\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_ACTIVE0 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_ACTIVE0_INT31 0x80000000 // Interrupt 31 active\r
+#define NVIC_ACTIVE0_INT30 0x40000000 // Interrupt 30 active\r
+#define NVIC_ACTIVE0_INT29 0x20000000 // Interrupt 29 active\r
+#define NVIC_ACTIVE0_INT28 0x10000000 // Interrupt 28 active\r
+#define NVIC_ACTIVE0_INT27 0x08000000 // Interrupt 27 active\r
+#define NVIC_ACTIVE0_INT26 0x04000000 // Interrupt 26 active\r
+#define NVIC_ACTIVE0_INT25 0x02000000 // Interrupt 25 active\r
+#define NVIC_ACTIVE0_INT24 0x01000000 // Interrupt 24 active\r
+#define NVIC_ACTIVE0_INT23 0x00800000 // Interrupt 23 active\r
+#define NVIC_ACTIVE0_INT22 0x00400000 // Interrupt 22 active\r
+#define NVIC_ACTIVE0_INT21 0x00200000 // Interrupt 21 active\r
+#define NVIC_ACTIVE0_INT20 0x00100000 // Interrupt 20 active\r
+#define NVIC_ACTIVE0_INT19 0x00080000 // Interrupt 19 active\r
+#define NVIC_ACTIVE0_INT18 0x00040000 // Interrupt 18 active\r
+#define NVIC_ACTIVE0_INT17 0x00020000 // Interrupt 17 active\r
+#define NVIC_ACTIVE0_INT16 0x00010000 // Interrupt 16 active\r
+#define NVIC_ACTIVE0_INT15 0x00008000 // Interrupt 15 active\r
+#define NVIC_ACTIVE0_INT14 0x00004000 // Interrupt 14 active\r
+#define NVIC_ACTIVE0_INT13 0x00002000 // Interrupt 13 active\r
+#define NVIC_ACTIVE0_INT12 0x00001000 // Interrupt 12 active\r
+#define NVIC_ACTIVE0_INT11 0x00000800 // Interrupt 11 active\r
+#define NVIC_ACTIVE0_INT10 0x00000400 // Interrupt 10 active\r
+#define NVIC_ACTIVE0_INT9 0x00000200 // Interrupt 9 active\r
+#define NVIC_ACTIVE0_INT8 0x00000100 // Interrupt 8 active\r
+#define NVIC_ACTIVE0_INT7 0x00000080 // Interrupt 7 active\r
+#define NVIC_ACTIVE0_INT6 0x00000040 // Interrupt 6 active\r
+#define NVIC_ACTIVE0_INT5 0x00000020 // Interrupt 5 active\r
+#define NVIC_ACTIVE0_INT4 0x00000010 // Interrupt 4 active\r
+#define NVIC_ACTIVE0_INT3 0x00000008 // Interrupt 3 active\r
+#define NVIC_ACTIVE0_INT2 0x00000004 // Interrupt 2 active\r
+#define NVIC_ACTIVE0_INT1 0x00000002 // Interrupt 1 active\r
+#define NVIC_ACTIVE0_INT0 0x00000001 // Interrupt 0 active\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_ACTIVE1 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_ACTIVE1_INT59 0x08000000 // Interrupt 59 active\r
+#define NVIC_ACTIVE1_INT58 0x04000000 // Interrupt 58 active\r
+#define NVIC_ACTIVE1_INT57 0x02000000 // Interrupt 57 active\r
+#define NVIC_ACTIVE1_INT56 0x01000000 // Interrupt 56 active\r
+#define NVIC_ACTIVE1_INT55 0x00800000 // Interrupt 55 active\r
+#define NVIC_ACTIVE1_INT54 0x00400000 // Interrupt 54 active\r
+#define NVIC_ACTIVE1_INT53 0x00200000 // Interrupt 53 active\r
+#define NVIC_ACTIVE1_INT52 0x00100000 // Interrupt 52 active\r
+#define NVIC_ACTIVE1_INT51 0x00080000 // Interrupt 51 active\r
+#define NVIC_ACTIVE1_INT50 0x00040000 // Interrupt 50 active\r
+#define NVIC_ACTIVE1_INT49 0x00020000 // Interrupt 49 active\r
+#define NVIC_ACTIVE1_INT48 0x00010000 // Interrupt 48 active\r
+#define NVIC_ACTIVE1_INT47 0x00008000 // Interrupt 47 active\r
+#define NVIC_ACTIVE1_INT46 0x00004000 // Interrupt 46 active\r
+#define NVIC_ACTIVE1_INT45 0x00002000 // Interrupt 45 active\r
+#define NVIC_ACTIVE1_INT44 0x00001000 // Interrupt 44 active\r
+#define NVIC_ACTIVE1_INT43 0x00000800 // Interrupt 43 active\r
+#define NVIC_ACTIVE1_INT42 0x00000400 // Interrupt 42 active\r
+#define NVIC_ACTIVE1_INT41 0x00000200 // Interrupt 41 active\r
+#define NVIC_ACTIVE1_INT40 0x00000100 // Interrupt 40 active\r
+#define NVIC_ACTIVE1_INT39 0x00000080 // Interrupt 39 active\r
+#define NVIC_ACTIVE1_INT38 0x00000040 // Interrupt 38 active\r
+#define NVIC_ACTIVE1_INT37 0x00000020 // Interrupt 37 active\r
+#define NVIC_ACTIVE1_INT36 0x00000010 // Interrupt 36 active\r
+#define NVIC_ACTIVE1_INT35 0x00000008 // Interrupt 35 active\r
+#define NVIC_ACTIVE1_INT34 0x00000004 // Interrupt 34 active\r
+#define NVIC_ACTIVE1_INT33 0x00000002 // Interrupt 33 active\r
+#define NVIC_ACTIVE1_INT32 0x00000001 // Interrupt 32 active\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_PRI0 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_PRI0_INT3_M 0xFF000000 // Interrupt 3 priority mask\r
+#define NVIC_PRI0_INT2_M 0x00FF0000 // Interrupt 2 priority mask\r
+#define NVIC_PRI0_INT1_M 0x0000FF00 // Interrupt 1 priority mask\r
+#define NVIC_PRI0_INT0_M 0x000000FF // Interrupt 0 priority mask\r
+#define NVIC_PRI0_INT3_S 24\r
+#define NVIC_PRI0_INT2_S 16\r
+#define NVIC_PRI0_INT1_S 8\r
+#define NVIC_PRI0_INT0_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_PRI1 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_PRI1_INT7_M 0xFF000000 // Interrupt 7 priority mask\r
+#define NVIC_PRI1_INT6_M 0x00FF0000 // Interrupt 6 priority mask\r
+#define NVIC_PRI1_INT5_M 0x0000FF00 // Interrupt 5 priority mask\r
+#define NVIC_PRI1_INT4_M 0x000000FF // Interrupt 4 priority mask\r
+#define NVIC_PRI1_INT7_S 24\r
+#define NVIC_PRI1_INT6_S 16\r
+#define NVIC_PRI1_INT5_S 8\r
+#define NVIC_PRI1_INT4_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_PRI2 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_PRI2_INT11_M 0xFF000000 // Interrupt 11 priority mask\r
+#define NVIC_PRI2_INT10_M 0x00FF0000 // Interrupt 10 priority mask\r
+#define NVIC_PRI2_INT9_M 0x0000FF00 // Interrupt 9 priority mask\r
+#define NVIC_PRI2_INT8_M 0x000000FF // Interrupt 8 priority mask\r
+#define NVIC_PRI2_INT11_S 24\r
+#define NVIC_PRI2_INT10_S 16\r
+#define NVIC_PRI2_INT9_S 8\r
+#define NVIC_PRI2_INT8_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_PRI3 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_PRI3_INT15_M 0xFF000000 // Interrupt 15 priority mask\r
+#define NVIC_PRI3_INT14_M 0x00FF0000 // Interrupt 14 priority mask\r
+#define NVIC_PRI3_INT13_M 0x0000FF00 // Interrupt 13 priority mask\r
+#define NVIC_PRI3_INT12_M 0x000000FF // Interrupt 12 priority mask\r
+#define NVIC_PRI3_INT15_S 24\r
+#define NVIC_PRI3_INT14_S 16\r
+#define NVIC_PRI3_INT13_S 8\r
+#define NVIC_PRI3_INT12_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_PRI4 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_PRI4_INT19_M 0xFF000000 // Interrupt 19 priority mask\r
+#define NVIC_PRI4_INT18_M 0x00FF0000 // Interrupt 18 priority mask\r
+#define NVIC_PRI4_INT17_M 0x0000FF00 // Interrupt 17 priority mask\r
+#define NVIC_PRI4_INT16_M 0x000000FF // Interrupt 16 priority mask\r
+#define NVIC_PRI4_INT19_S 24\r
+#define NVIC_PRI4_INT18_S 16\r
+#define NVIC_PRI4_INT17_S 8\r
+#define NVIC_PRI4_INT16_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_PRI5 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_PRI5_INT23_M 0xFF000000 // Interrupt 23 priority mask\r
+#define NVIC_PRI5_INT22_M 0x00FF0000 // Interrupt 22 priority mask\r
+#define NVIC_PRI5_INT21_M 0x0000FF00 // Interrupt 21 priority mask\r
+#define NVIC_PRI5_INT20_M 0x000000FF // Interrupt 20 priority mask\r
+#define NVIC_PRI5_INT23_S 24\r
+#define NVIC_PRI5_INT22_S 16\r
+#define NVIC_PRI5_INT21_S 8\r
+#define NVIC_PRI5_INT20_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_PRI6 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_PRI6_INT27_M 0xFF000000 // Interrupt 27 priority mask\r
+#define NVIC_PRI6_INT26_M 0x00FF0000 // Interrupt 26 priority mask\r
+#define NVIC_PRI6_INT25_M 0x0000FF00 // Interrupt 25 priority mask\r
+#define NVIC_PRI6_INT24_M 0x000000FF // Interrupt 24 priority mask\r
+#define NVIC_PRI6_INT27_S 24\r
+#define NVIC_PRI6_INT26_S 16\r
+#define NVIC_PRI6_INT25_S 8\r
+#define NVIC_PRI6_INT24_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_PRI7 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_PRI7_INT31_M 0xFF000000 // Interrupt 31 priority mask\r
+#define NVIC_PRI7_INT30_M 0x00FF0000 // Interrupt 30 priority mask\r
+#define NVIC_PRI7_INT29_M 0x0000FF00 // Interrupt 29 priority mask\r
+#define NVIC_PRI7_INT28_M 0x000000FF // Interrupt 28 priority mask\r
+#define NVIC_PRI7_INT31_S 24\r
+#define NVIC_PRI7_INT30_S 16\r
+#define NVIC_PRI7_INT29_S 8\r
+#define NVIC_PRI7_INT28_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_PRI8 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_PRI8_INT35_M 0xFF000000 // Interrupt 35 priority mask\r
+#define NVIC_PRI8_INT34_M 0x00FF0000 // Interrupt 34 priority mask\r
+#define NVIC_PRI8_INT33_M 0x0000FF00 // Interrupt 33 priority mask\r
+#define NVIC_PRI8_INT32_M 0x000000FF // Interrupt 32 priority mask\r
+#define NVIC_PRI8_INT35_S 24\r
+#define NVIC_PRI8_INT34_S 16\r
+#define NVIC_PRI8_INT33_S 8\r
+#define NVIC_PRI8_INT32_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_PRI9 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_PRI9_INT39_M 0xFF000000 // Interrupt 39 priority mask\r
+#define NVIC_PRI9_INT38_M 0x00FF0000 // Interrupt 38 priority mask\r
+#define NVIC_PRI9_INT37_M 0x0000FF00 // Interrupt 37 priority mask\r
+#define NVIC_PRI9_INT36_M 0x000000FF // Interrupt 36 priority mask\r
+#define NVIC_PRI9_INT39_S 24\r
+#define NVIC_PRI9_INT38_S 16\r
+#define NVIC_PRI9_INT37_S 8\r
+#define NVIC_PRI9_INT36_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_PRI10 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_PRI10_INT43_M 0xFF000000 // Interrupt 43 priority mask\r
+#define NVIC_PRI10_INT42_M 0x00FF0000 // Interrupt 42 priority mask\r
+#define NVIC_PRI10_INT41_M 0x0000FF00 // Interrupt 41 priority mask\r
+#define NVIC_PRI10_INT40_M 0x000000FF // Interrupt 40 priority mask\r
+#define NVIC_PRI10_INT43_S 24\r
+#define NVIC_PRI10_INT42_S 16\r
+#define NVIC_PRI10_INT41_S 8\r
+#define NVIC_PRI10_INT40_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_CPUID register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_CPUID_IMP_M 0xFF000000 // Implementer\r
+#define NVIC_CPUID_VAR_M 0x00F00000 // Variant\r
+#define NVIC_CPUID_PARTNO_M 0x0000FFF0 // Processor part number\r
+#define NVIC_CPUID_REV_M 0x0000000F // Revision\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_INT_CTRL register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_INT_CTRL_NMI_SET 0x80000000 // Pend a NMI\r
+#define NVIC_INT_CTRL_PEND_SV 0x10000000 // Pend a PendSV\r
+#define NVIC_INT_CTRL_UNPEND_SV 0x08000000 // Unpend a PendSV\r
+#define NVIC_INT_CTRL_ISR_PRE 0x00800000 // Debug interrupt handling\r
+#define NVIC_INT_CTRL_ISR_PEND 0x00400000 // Debug interrupt pending\r
+#define NVIC_INT_CTRL_VEC_PEN_M 0x003FF000 // Highest pending exception\r
+#define NVIC_INT_CTRL_RET_BASE 0x00000800 // Return to base\r
+#define NVIC_INT_CTRL_VEC_ACT_M 0x000003FF // Current active exception\r
+#define NVIC_INT_CTRL_VEC_PEN_S 12\r
+#define NVIC_INT_CTRL_VEC_ACT_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_VTABLE register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_VTABLE_BASE 0x20000000 // Vector table base\r
+#define NVIC_VTABLE_OFFSET_M 0x1FFFFF00 // Vector table offset\r
+#define NVIC_VTABLE_OFFSET_S 8\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_APINT register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_APINT_VECTKEY_M 0xFFFF0000 // Vector key mask\r
+#define NVIC_APINT_VECTKEY 0x05FA0000 // Vector key\r
+#define NVIC_APINT_ENDIANESS 0x00008000 // Data endianess\r
+#define NVIC_APINT_PRIGROUP_M 0x00000700 // Priority group\r
+#define NVIC_APINT_PRIGROUP_7_1 0x00000000 // Priority group 7.1 split\r
+#define NVIC_APINT_PRIGROUP_6_2 0x00000100 // Priority group 6.2 split\r
+#define NVIC_APINT_PRIGROUP_5_3 0x00000200 // Priority group 5.3 split\r
+#define NVIC_APINT_PRIGROUP_4_4 0x00000300 // Priority group 4.4 split\r
+#define NVIC_APINT_PRIGROUP_3_5 0x00000400 // Priority group 3.5 split\r
+#define NVIC_APINT_PRIGROUP_2_6 0x00000500 // Priority group 2.6 split\r
+#define NVIC_APINT_PRIGROUP_1_7 0x00000600 // Priority group 1.7 split\r
+#define NVIC_APINT_PRIGROUP_0_8 0x00000700 // Priority group 0.8 split\r
+#define NVIC_APINT_SYSRESETREQ 0x00000004 // System reset request\r
+#define NVIC_APINT_VECT_CLR_ACT 0x00000002 // Clear active NMI/fault info\r
+#define NVIC_APINT_VECT_RESET 0x00000001 // System reset\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_SYS_CTRL register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_SYS_CTRL_SEVONPEND 0x00000010 // Wakeup on pend\r
+#define NVIC_SYS_CTRL_SLEEPDEEP 0x00000004 // Deep sleep enable\r
+#define NVIC_SYS_CTRL_SLEEPEXIT 0x00000002 // Sleep on ISR exit\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_CFG_CTRL register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_CFG_CTRL_BFHFNMIGN 0x00000100 // Ignore bus fault in NMI/fault\r
+#define NVIC_CFG_CTRL_DIV0 0x00000010 // Trap on divide by 0\r
+#define NVIC_CFG_CTRL_UNALIGNED 0x00000008 // Trap on unaligned access\r
+#define NVIC_CFG_CTRL_DEEP_PEND 0x00000004 // Allow deep interrupt trigger\r
+#define NVIC_CFG_CTRL_MAIN_PEND 0x00000002 // Allow main interrupt trigger\r
+#define NVIC_CFG_CTRL_BASE_THR 0x00000001 // Thread state control\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_SYS_PRI1 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_SYS_PRI1_RES_M 0xFF000000 // Priority of reserved handler\r
+#define NVIC_SYS_PRI1_USAGE_M 0x00FF0000 // Priority of usage fault handler\r
+#define NVIC_SYS_PRI1_BUS_M 0x0000FF00 // Priority of bus fault handler\r
+#define NVIC_SYS_PRI1_MEM_M 0x000000FF // Priority of mem manage handler\r
+#define NVIC_SYS_PRI1_USAGE_S 16\r
+#define NVIC_SYS_PRI1_BUS_S 8\r
+#define NVIC_SYS_PRI1_MEM_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_SYS_PRI2 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_SYS_PRI2_SVC_M 0xFF000000 // Priority of SVCall handler\r
+#define NVIC_SYS_PRI2_RES_M 0x00FFFFFF // Priority of reserved handlers\r
+#define NVIC_SYS_PRI2_SVC_S 24\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_SYS_PRI3 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_SYS_PRI3_TICK_M 0xFF000000 // Priority of Sys Tick handler\r
+#define NVIC_SYS_PRI3_PENDSV_M 0x00FF0000 // Priority of PendSV handler\r
+#define NVIC_SYS_PRI3_RES_M 0x0000FF00 // Priority of reserved handler\r
+#define NVIC_SYS_PRI3_DEBUG_M 0x000000FF // Priority of debug handler\r
+#define NVIC_SYS_PRI3_TICK_S 24\r
+#define NVIC_SYS_PRI3_PENDSV_S 16\r
+#define NVIC_SYS_PRI3_DEBUG_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_SYS_HND_CTRL register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_SYS_HND_CTRL_USAGE 0x00040000 // Usage fault enable\r
+#define NVIC_SYS_HND_CTRL_BUS 0x00020000 // Bus fault enable\r
+#define NVIC_SYS_HND_CTRL_MEM 0x00010000 // Mem manage fault enable\r
+#define NVIC_SYS_HND_CTRL_SVC 0x00008000 // SVCall is pended\r
+#define NVIC_SYS_HND_CTRL_BUSP 0x00004000 // Bus fault is pended\r
+#define NVIC_SYS_HND_CTRL_TICK 0x00000800 // Sys tick is active\r
+#define NVIC_SYS_HND_CTRL_PNDSV 0x00000400 // PendSV is active\r
+#define NVIC_SYS_HND_CTRL_MON 0x00000100 // Monitor is active\r
+#define NVIC_SYS_HND_CTRL_SVCA 0x00000080 // SVCall is active\r
+#define NVIC_SYS_HND_CTRL_USGA 0x00000008 // Usage fault is active\r
+#define NVIC_SYS_HND_CTRL_BUSA 0x00000002 // Bus fault is active\r
+#define NVIC_SYS_HND_CTRL_MEMA 0x00000001 // Mem manage is active\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_FAULT_STAT register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_FAULT_STAT_DIV0 0x02000000 // Divide by zero fault\r
+#define NVIC_FAULT_STAT_UNALIGN 0x01000000 // Unaligned access fault\r
+#define NVIC_FAULT_STAT_NOCP 0x00080000 // No coprocessor fault\r
+#define NVIC_FAULT_STAT_INVPC 0x00040000 // Invalid PC fault\r
+#define NVIC_FAULT_STAT_INVSTAT 0x00020000 // Invalid state fault\r
+#define NVIC_FAULT_STAT_UNDEF 0x00010000 // Undefined instruction fault\r
+#define NVIC_FAULT_STAT_BFARV 0x00008000 // BFAR is valid\r
+#define NVIC_FAULT_STAT_BSTKE 0x00001000 // Stack bus fault\r
+#define NVIC_FAULT_STAT_BUSTKE 0x00000800 // Unstack bus fault\r
+#define NVIC_FAULT_STAT_IMPRE 0x00000400 // Imprecise data bus error\r
+#define NVIC_FAULT_STAT_PRECISE 0x00000200 // Precise data bus error\r
+#define NVIC_FAULT_STAT_IBUS 0x00000100 // Instruction bus fault\r
+#define NVIC_FAULT_STAT_MMARV 0x00000080 // MMAR is valid\r
+#define NVIC_FAULT_STAT_MSTKE 0x00000010 // Stack access violation\r
+#define NVIC_FAULT_STAT_MUSTKE 0x00000008 // Unstack access violation\r
+#define NVIC_FAULT_STAT_DERR 0x00000002 // Data access violation\r
+#define NVIC_FAULT_STAT_IERR 0x00000001 // Instruction access violation\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_HFAULT_STAT register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_HFAULT_STAT_DBG 0x80000000 // Debug event\r
+#define NVIC_HFAULT_STAT_FORCED 0x40000000 // Cannot execute fault handler\r
+#define NVIC_HFAULT_STAT_VECT 0x00000002 // Vector table read fault\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_DEBUG_STAT register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_DEBUG_STAT_EXTRNL 0x00000010 // EDBGRQ asserted\r
+#define NVIC_DEBUG_STAT_VCATCH 0x00000008 // Vector catch\r
+#define NVIC_DEBUG_STAT_DWTTRAP 0x00000004 // DWT match\r
+#define NVIC_DEBUG_STAT_BKPT 0x00000002 // Breakpoint instruction\r
+#define NVIC_DEBUG_STAT_HALTED 0x00000001 // Halt request\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_MM_ADDR register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_MM_ADDR_M 0xFFFFFFFF // Data fault address\r
+#define NVIC_MM_ADDR_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_FAULT_ADDR register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_FAULT_ADDR_M 0xFFFFFFFF // Data bus fault address\r
+#define NVIC_FAULT_ADDR_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_EXC_STACK register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_EXC_STACK_DEEP 0x00000001 // Exception stack\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_EXC_NUM register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_EXC_NUM_M 0x000003FF // Exception number\r
+#define NVIC_EXC_NUM_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_COPRO register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_COPRO_15_M 0xC0000000 // Coprocessor 15 access mask\r
+#define NVIC_COPRO_15_DENIED 0x00000000 // Coprocessor 15 access denied\r
+#define NVIC_COPRO_15_PRIV 0x40000000 // Coprocessor 15 privileged addess\r
+#define NVIC_COPRO_15_FULL 0xC0000000 // Coprocessor 15 full access\r
+#define NVIC_COPRO_14_M 0x30000000 // Coprocessor 14 access mask\r
+#define NVIC_COPRO_14_DENIED 0x00000000 // Coprocessor 14 access denied\r
+#define NVIC_COPRO_14_PRIV 0x10000000 // Coprocessor 14 privileged addess\r
+#define NVIC_COPRO_14_FULL 0x30000000 // Coprocessor 14 full access\r
+#define NVIC_COPRO_13_M 0x0C000000 // Coprocessor 13 access mask\r
+#define NVIC_COPRO_13_DENIED 0x00000000 // Coprocessor 13 access denied\r
+#define NVIC_COPRO_13_PRIV 0x04000000 // Coprocessor 13 privileged addess\r
+#define NVIC_COPRO_13_FULL 0x0C000000 // Coprocessor 13 full access\r
+#define NVIC_COPRO_12_M 0x03000000 // Coprocessor 12 access mask\r
+#define NVIC_COPRO_12_DENIED 0x00000000 // Coprocessor 12 access denied\r
+#define NVIC_COPRO_12_PRIV 0x01000000 // Coprocessor 12 privileged addess\r
+#define NVIC_COPRO_12_FULL 0x03000000 // Coprocessor 12 full access\r
+#define NVIC_COPRO_11_M 0x00C00000 // Coprocessor 11 access mask\r
+#define NVIC_COPRO_11_DENIED 0x00000000 // Coprocessor 11 access denied\r
+#define NVIC_COPRO_11_PRIV 0x00400000 // Coprocessor 11 privileged addess\r
+#define NVIC_COPRO_11_FULL 0x00C00000 // Coprocessor 11 full access\r
+#define NVIC_COPRO_10_M 0x00300000 // Coprocessor 10 access mask\r
+#define NVIC_COPRO_10_DENIED 0x00000000 // Coprocessor 10 access denied\r
+#define NVIC_COPRO_10_PRIV 0x00100000 // Coprocessor 10 privileged addess\r
+#define NVIC_COPRO_10_FULL 0x00300000 // Coprocessor 10 full access\r
+#define NVIC_COPRO_9_M 0x000C0000 // Coprocessor 9 access mask\r
+#define NVIC_COPRO_9_DENIED 0x00000000 // Coprocessor 9 access denied\r
+#define NVIC_COPRO_9_PRIV 0x00040000 // Coprocessor 9 privileged addess\r
+#define NVIC_COPRO_9_FULL 0x000C0000 // Coprocessor 9 full access\r
+#define NVIC_COPRO_8_M 0x00030000 // Coprocessor 8 access mask\r
+#define NVIC_COPRO_8_DENIED 0x00000000 // Coprocessor 8 access denied\r
+#define NVIC_COPRO_8_PRIV 0x00010000 // Coprocessor 8 privileged addess\r
+#define NVIC_COPRO_8_FULL 0x00030000 // Coprocessor 8 full access\r
+#define NVIC_COPRO_7_M 0x0000C000 // Coprocessor 7 access mask\r
+#define NVIC_COPRO_7_DENIED 0x00000000 // Coprocessor 7 access denied\r
+#define NVIC_COPRO_7_PRIV 0x00004000 // Coprocessor 7 privileged addess\r
+#define NVIC_COPRO_7_FULL 0x0000C000 // Coprocessor 7 full access\r
+#define NVIC_COPRO_6_M 0x00003000 // Coprocessor 6 access mask\r
+#define NVIC_COPRO_6_DENIED 0x00000000 // Coprocessor 6 access denied\r
+#define NVIC_COPRO_6_PRIV 0x00001000 // Coprocessor 6 privileged addess\r
+#define NVIC_COPRO_6_FULL 0x00003000 // Coprocessor 6 full access\r
+#define NVIC_COPRO_5_M 0x00000C00 // Coprocessor 5 access mask\r
+#define NVIC_COPRO_5_DENIED 0x00000000 // Coprocessor 5 access denied\r
+#define NVIC_COPRO_5_PRIV 0x00000400 // Coprocessor 5 privileged addess\r
+#define NVIC_COPRO_5_FULL 0x00000C00 // Coprocessor 5 full access\r
+#define NVIC_COPRO_4_M 0x00000300 // Coprocessor 4 access mask\r
+#define NVIC_COPRO_4_DENIED 0x00000000 // Coprocessor 4 access denied\r
+#define NVIC_COPRO_4_PRIV 0x00000100 // Coprocessor 4 privileged addess\r
+#define NVIC_COPRO_4_FULL 0x00000300 // Coprocessor 4 full access\r
+#define NVIC_COPRO_3_M 0x000000C0 // Coprocessor 3 access mask\r
+#define NVIC_COPRO_3_DENIED 0x00000000 // Coprocessor 3 access denied\r
+#define NVIC_COPRO_3_PRIV 0x00000040 // Coprocessor 3 privileged addess\r
+#define NVIC_COPRO_3_FULL 0x000000C0 // Coprocessor 3 full access\r
+#define NVIC_COPRO_2_M 0x00000030 // Coprocessor 2 access mask\r
+#define NVIC_COPRO_2_DENIED 0x00000000 // Coprocessor 2 access denied\r
+#define NVIC_COPRO_2_PRIV 0x00000010 // Coprocessor 2 privileged addess\r
+#define NVIC_COPRO_2_FULL 0x00000030 // Coprocessor 2 full access\r
+#define NVIC_COPRO_1_M 0x0000000C // Coprocessor 1 access mask\r
+#define NVIC_COPRO_1_DENIED 0x00000000 // Coprocessor 1 access denied\r
+#define NVIC_COPRO_1_PRIV 0x00000004 // Coprocessor 1 privileged addess\r
+#define NVIC_COPRO_1_FULL 0x0000000C // Coprocessor 1 full access\r
+#define NVIC_COPRO_0_M 0x00000003 // Coprocessor 0 access mask\r
+#define NVIC_COPRO_0_DENIED 0x00000000 // Coprocessor 0 access denied\r
+#define NVIC_COPRO_0_PRIV 0x00000001 // Coprocessor 0 privileged addess\r
+#define NVIC_COPRO_0_FULL 0x00000003 // Coprocessor 0 full access\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_MPU_TYPE register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_MPU_TYPE_IREGION_M 0x00FF0000 // Number of I regions\r
+#define NVIC_MPU_TYPE_DREGION_M 0x0000FF00 // Number of D regions\r
+#define NVIC_MPU_TYPE_SEPARATE 0x00000001 // Separate or unified MPU\r
+#define NVIC_MPU_TYPE_IREGION_S 16\r
+#define NVIC_MPU_TYPE_DREGION_S 8\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_MPU_CTRL register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_MPU_CTRL_HFNMIENA 0x00000002 // MPU enabled during faults\r
+#define NVIC_MPU_CTRL_ENABLE 0x00000001 // MPU enable\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_MPU_NUMBER register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_MPU_NUMBER_M 0x000000FF // MPU region to access\r
+#define NVIC_MPU_NUMBER_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_MPU_BASE register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_MPU_BASE_ADDR_M 0xFFFFFF00 // Base address\r
+#define NVIC_MPU_BASE_VALID 0x00000010 // Region number valid\r
+#define NVIC_MPU_BASE_REGION_M 0x0000000F // Region number\r
+#define NVIC_MPU_BASE_ADDR_S 8\r
+#define NVIC_MPU_BASE_REGION_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_MPU_ATTR register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_MPU_ATTR_ATTRS 0xFFFF0000 // Attributes\r
+#define NVIC_MPU_ATTR_SRD 0x0000FF00 // Sub-region disable\r
+#define NVIC_MPU_ATTR_SZENABLE 0x000000FF // Region size\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_DBG_CTRL register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_DBG_CTRL_DBGKEY_M 0xFFFF0000 // Debug key mask\r
+#define NVIC_DBG_CTRL_DBGKEY 0xA05F0000 // Debug key\r
+#define NVIC_DBG_CTRL_MON_PEND 0x00008000 // Pend the monitor\r
+#define NVIC_DBG_CTRL_MON_REQ 0x00004000 // Monitor request\r
+#define NVIC_DBG_CTRL_MON_EN 0x00002000 // Debug monitor enable\r
+#define NVIC_DBG_CTRL_MONSTEP 0x00001000 // Monitor step the core\r
+#define NVIC_DBG_CTRL_S_SLEEP 0x00000400 // Core is sleeping\r
+#define NVIC_DBG_CTRL_S_HALT 0x00000200 // Core status on halt\r
+#define NVIC_DBG_CTRL_S_REGRDY 0x00000100 // Register read/write available\r
+#define NVIC_DBG_CTRL_S_LOCKUP 0x00000080 // Core is locked up\r
+#define NVIC_DBG_CTRL_C_RESET 0x00000010 // Reset the core\r
+#define NVIC_DBG_CTRL_C_MASKINT 0x00000008 // Mask interrupts when stepping\r
+#define NVIC_DBG_CTRL_C_STEP 0x00000004 // Step the core\r
+#define NVIC_DBG_CTRL_C_HALT 0x00000002 // Halt the core\r
+#define NVIC_DBG_CTRL_C_DEBUGEN 0x00000001 // Enable debug\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_DBG_XFER register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_DBG_XFER_REG_WNR 0x00010000 // Write or not read\r
+#define NVIC_DBG_XFER_REG_SEL_M 0x0000001F // Register\r
+#define NVIC_DBG_XFER_REG_R0 0x00000000 // Register R0\r
+#define NVIC_DBG_XFER_REG_R1 0x00000001 // Register R1\r
+#define NVIC_DBG_XFER_REG_R2 0x00000002 // Register R2\r
+#define NVIC_DBG_XFER_REG_R3 0x00000003 // Register R3\r
+#define NVIC_DBG_XFER_REG_R4 0x00000004 // Register R4\r
+#define NVIC_DBG_XFER_REG_R5 0x00000005 // Register R5\r
+#define NVIC_DBG_XFER_REG_R6 0x00000006 // Register R6\r
+#define NVIC_DBG_XFER_REG_R7 0x00000007 // Register R7\r
+#define NVIC_DBG_XFER_REG_R8 0x00000008 // Register R8\r
+#define NVIC_DBG_XFER_REG_R9 0x00000009 // Register R9\r
+#define NVIC_DBG_XFER_REG_R10 0x0000000A // Register R10\r
+#define NVIC_DBG_XFER_REG_R11 0x0000000B // Register R11\r
+#define NVIC_DBG_XFER_REG_R12 0x0000000C // Register R12\r
+#define NVIC_DBG_XFER_REG_R13 0x0000000D // Register R13\r
+#define NVIC_DBG_XFER_REG_R14 0x0000000E // Register R14\r
+#define NVIC_DBG_XFER_REG_R15 0x0000000F // Register R15\r
+#define NVIC_DBG_XFER_REG_FLAGS 0x00000010 // xPSR/Flags register\r
+#define NVIC_DBG_XFER_REG_MSP 0x00000011 // Main SP\r
+#define NVIC_DBG_XFER_REG_PSP 0x00000012 // Process SP\r
+#define NVIC_DBG_XFER_REG_DSP 0x00000013 // Deep SP\r
+#define NVIC_DBG_XFER_REG_CFBP 0x00000014 // Control/Fault/BasePri/PriMask\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_DBG_DATA register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_DBG_DATA_M 0xFFFFFFFF // Data temporary cache\r
+#define NVIC_DBG_DATA_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_DBG_INT register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_DBG_INT_HARDERR 0x00000400 // Debug trap on hard fault\r
+#define NVIC_DBG_INT_INTERR 0x00000200 // Debug trap on interrupt errors\r
+#define NVIC_DBG_INT_BUSERR 0x00000100 // Debug trap on bus error\r
+#define NVIC_DBG_INT_STATERR 0x00000080 // Debug trap on usage fault state\r
+#define NVIC_DBG_INT_CHKERR 0x00000040 // Debug trap on usage fault check\r
+#define NVIC_DBG_INT_NOCPERR 0x00000020 // Debug trap on coprocessor error\r
+#define NVIC_DBG_INT_MMERR 0x00000010 // Debug trap on mem manage fault\r
+#define NVIC_DBG_INT_RESET 0x00000008 // Core reset status\r
+#define NVIC_DBG_INT_RSTPENDCLR 0x00000004 // Clear pending core reset\r
+#define NVIC_DBG_INT_RSTPENDING 0x00000002 // Core reset is pending\r
+#define NVIC_DBG_INT_RSTVCATCH 0x00000001 // Reset vector catch\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_SW_TRIG register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_SW_TRIG_INTID_M 0x000003FF // Interrupt to trigger\r
+#define NVIC_SW_TRIG_INTID_S 0\r
+\r
+#endif // __HW_NVIC_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_pwm.h - Defines and Macros for Pulse Width Modulation (PWM) ports\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_PWM_H__\r
+#define __HW_PWM_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// PWM Module Register Offsets.\r
+//\r
+//*****************************************************************************\r
+#define PWM_O_CTL 0x00000000 // PWM Master Control register\r
+#define PWM_O_SYNC 0x00000004 // PWM Time Base Sync register\r
+#define PWM_O_ENABLE 0x00000008 // PWM Output Enable register\r
+#define PWM_O_INVERT 0x0000000C // PWM Output Inversion register\r
+#define PWM_O_FAULT 0x00000010 // PWM Output Fault register\r
+#define PWM_O_INTEN 0x00000014 // PWM Interrupt Enable register\r
+#define PWM_O_RIS 0x00000018 // PWM Interrupt Raw Status reg.\r
+#define PWM_O_ISC 0x0000001C // PWM Interrupt Status register\r
+#define PWM_O_STATUS 0x00000020 // PWM Status register\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the PWM Master Control register.\r
+//\r
+//*****************************************************************************\r
+#define PWM_CTL_GLOBAL_SYNC2 0x00000004 // Global sync generator 2\r
+#define PWM_CTL_GLOBAL_SYNC1 0x00000002 // Global sync generator 1\r
+#define PWM_CTL_GLOBAL_SYNC0 0x00000001 // Global sync generator 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the PWM Time Base Sync register.\r
+//\r
+//*****************************************************************************\r
+#define PWM_SYNC_SYNC2 0x00000004 // Reset generator 2 counter\r
+#define PWM_SYNC_SYNC1 0x00000002 // Reset generator 1 counter\r
+#define PWM_SYNC_SYNC0 0x00000001 // Reset generator 0 counter\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the PWM Output Enable register.\r
+//\r
+//*****************************************************************************\r
+#define PWM_ENABLE_PWM5EN 0x00000020 // PWM5 pin enable\r
+#define PWM_ENABLE_PWM4EN 0x00000010 // PWM4 pin enable\r
+#define PWM_ENABLE_PWM3EN 0x00000008 // PWM3 pin enable\r
+#define PWM_ENABLE_PWM2EN 0x00000004 // PWM2 pin enable\r
+#define PWM_ENABLE_PWM1EN 0x00000002 // PWM1 pin enable\r
+#define PWM_ENABLE_PWM0EN 0x00000001 // PWM0 pin enable\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the PWM Inversion register.\r
+//\r
+//*****************************************************************************\r
+#define PWM_INVERT_PWM5INV 0x00000020 // PWM5 pin invert\r
+#define PWM_INVERT_PWM4INV 0x00000010 // PWM4 pin invert\r
+#define PWM_INVERT_PWM3INV 0x00000008 // PWM3 pin invert\r
+#define PWM_INVERT_PWM2INV 0x00000004 // PWM2 pin invert\r
+#define PWM_INVERT_PWM1INV 0x00000002 // PWM1 pin invert\r
+#define PWM_INVERT_PWM0INV 0x00000001 // PWM0 pin invert\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the PWM Fault register.\r
+//\r
+//*****************************************************************************\r
+#define PWM_FAULT_FAULT5 0x00000020 // PWM5 pin fault\r
+#define PWM_FAULT_FAULT4 0x00000010 // PWM5 pin fault\r
+#define PWM_FAULT_FAULT3 0x00000008 // PWM5 pin fault\r
+#define PWM_FAULT_FAULT2 0x00000004 // PWM5 pin fault\r
+#define PWM_FAULT_FAULT1 0x00000002 // PWM5 pin fault\r
+#define PWM_FAULT_FAULT0 0x00000001 // PWM5 pin fault\r
+\r
+//*****************************************************************************\r
+//\r
+// PWM Interrupt Register bit definitions.\r
+//\r
+//*****************************************************************************\r
+#define PWM_INT_INTFAULT 0x00010000 // Fault interrupt pending\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the PWM Status register.\r
+//\r
+//*****************************************************************************\r
+#define PWM_STATUS_FAULT 0x00000001 // Fault status\r
+\r
+//*****************************************************************************\r
+//\r
+// PWM Generator standard offsets.\r
+//\r
+//*****************************************************************************\r
+#define PWM_GEN_0_OFFSET 0x00000040 // PWM0 base\r
+#define PWM_GEN_1_OFFSET 0x00000080 // PWM1 base\r
+#define PWM_GEN_2_OFFSET 0x000000C0 // PWM2 base\r
+\r
+#define PWM_O_X_CTL 0x00000000 // Gen Control Reg\r
+#define PWM_O_X_INTEN 0x00000004 // Gen Int/Trig Enable Reg\r
+#define PWM_O_X_RIS 0x00000008 // Gen Raw Int Status Reg\r
+#define PWM_O_X_ISC 0x0000000C // Gen Int Status Reg\r
+#define PWM_O_X_LOAD 0x00000010 // Gen Load Reg\r
+#define PWM_O_X_COUNT 0x00000014 // Gen Counter Reg\r
+#define PWM_O_X_CMPA 0x00000018 // Gen Compare A Reg\r
+#define PWM_O_X_CMPB 0x0000001C // Gen Compare B Reg\r
+#define PWM_O_X_GENA 0x00000020 // Gen Generator A Ctrl Reg\r
+#define PWM_O_X_GENB 0x00000024 // Gen Generator B Ctrl Reg\r
+#define PWM_O_X_DBCTL 0x00000028 // Gen Dead Band Ctrl Reg\r
+#define PWM_O_X_DBRISE 0x0000002C // Gen DB Rising Edge Delay Reg\r
+#define PWM_O_X_DBFALL 0x00000030 // Gen DB Falling Edge Delay Reg\r
+\r
+//*****************************************************************************\r
+//\r
+// PWM_X Control Register bit definitions.\r
+//\r
+//*****************************************************************************\r
+#define PWM_X_CTL_ENABLE 0x00000001 // Master enable for gen block\r
+#define PWM_X_CTL_MODE 0x00000002 // Counter mode, down or up/down\r
+#define PWM_X_CTL_DEBUG 0x00000004 // Debug mode\r
+#define PWM_X_CTL_LOADUPD 0x00000008 // Update mode for the load reg\r
+#define PWM_X_CTL_CMPAUPD 0x00000010 // Update mode for comp A reg\r
+#define PWM_X_CTL_CMPBUPD 0x00000020 // Update mode for comp B reg\r
+\r
+//*****************************************************************************\r
+//\r
+// PWM_X Interrupt/Trigger Enable Register bit definitions.\r
+//\r
+//*****************************************************************************\r
+#define PWM_X_INTEN_INTCNTZERO 0x00000001 // Int if COUNT = 0\r
+#define PWM_X_INTEN_INTCNTLOAD 0x00000002 // Int if COUNT = LOAD\r
+#define PWM_X_INTEN_INTCMPAU 0x00000004 // Int if COUNT = CMPA U\r
+#define PWM_X_INTEN_INTCMPAD 0x00000008 // Int if COUNT = CMPA D\r
+#define PWM_X_INTEN_INTCMPBU 0x00000010 // Int if COUNT = CMPA U\r
+#define PWM_X_INTEN_INTCMPBD 0x00000020 // Int if COUNT = CMPA D\r
+#define PWM_X_INTEN_TRCNTZERO 0x00000100 // Trig if COUNT = 0\r
+#define PWM_X_INTEN_TRCNTLOAD 0x00000200 // Trig if COUNT = LOAD\r
+#define PWM_X_INTEN_TRCMPAU 0x00000400 // Trig if COUNT = CMPA U\r
+#define PWM_X_INTEN_TRCMPAD 0x00000800 // Trig if COUNT = CMPA D\r
+#define PWM_X_INTEN_TRCMPBU 0x00001000 // Trig if COUNT = CMPA U\r
+#define PWM_X_INTEN_TRCMPBD 0x00002000 // Trig if COUNT = CMPA D\r
+\r
+//*****************************************************************************\r
+//\r
+// PWM_X Raw Interrupt Status Register bit definitions.\r
+//\r
+//*****************************************************************************\r
+#define PWM_X_RIS_INTCNTZERO 0x00000001 // PWM_X_COUNT = 0 int\r
+#define PWM_X_RIS_INTCNTLOAD 0x00000002 // PWM_X_COUNT = PWM_X_LOAD int\r
+#define PWM_X_RIS_INTCMPAU 0x00000004 // PWM_X_COUNT = PWM_X_CMPA U int\r
+#define PWM_X_RIS_INTCMPAD 0x00000008 // PWM_X_COUNT = PWM_X_CMPA D int\r
+#define PWM_X_RIS_INTCMPBU 0x00000010 // PWM_X_COUNT = PWM_X_CMPB U int\r
+#define PWM_X_RIS_INTCMPBD 0x00000020 // PWM_X_COUNT = PWM_X_CMPB D int\r
+\r
+//*****************************************************************************\r
+//\r
+// PWM_X Interrupt Status Register bit definitions.\r
+//\r
+//*****************************************************************************\r
+#define PWM_X_INT_INTCNTZERO 0x00000001 // PWM_X_COUNT = 0 received\r
+#define PWM_X_INT_INTCNTLOAD 0x00000002 // PWM_X_COUNT = PWM_X_LOAD rcvd\r
+#define PWM_X_INT_INTCMPAU 0x00000004 // PWM_X_COUNT = PWM_X_CMPA U rcvd\r
+#define PWM_X_INT_INTCMPAD 0x00000008 // PWM_X_COUNT = PWM_X_CMPA D rcvd\r
+#define PWM_X_INT_INTCMPBU 0x00000010 // PWM_X_COUNT = PWM_X_CMPB U rcvd\r
+#define PWM_X_INT_INTCMPBD 0x00000020 // PWM_X_COUNT = PWM_X_CMPB D rcvd\r
+\r
+//*****************************************************************************\r
+//\r
+// PWM_X Generator A/B Control Register bit definitions.\r
+//\r
+//*****************************************************************************\r
+#define PWM_X_GEN_Y_ACTZERO 0x00000003 // Act PWM_X_COUNT = 0\r
+#define PWM_X_GEN_Y_ACTLOAD 0x0000000C // Act PWM_X_COUNT = PWM_X_LOAD\r
+#define PWM_X_GEN_Y_ACTCMPAU 0x00000030 // Act PWM_X_COUNT = PWM_X_CMPA U\r
+#define PWM_X_GEN_Y_ACTCMPAD 0x000000C0 // Act PWM_X_COUNT = PWM_X_CMPA D\r
+#define PWM_X_GEN_Y_ACTCMPBU 0x00000300 // Act PWM_X_COUNT = PWM_X_CMPB U\r
+#define PWM_X_GEN_Y_ACTCMPBD 0x00000C00 // Act PWM_X_COUNT = PWM_X_CMPB D\r
+\r
+//*****************************************************************************\r
+//\r
+// PWM_X Generator A/B Control Register action definitions.\r
+//\r
+//*****************************************************************************\r
+#define PWM_GEN_ACT_NONE 0x0 // Do nothing\r
+#define PWM_GEN_ACT_INV 0x1 // Invert the output signal\r
+#define PWM_GEN_ACT_ZERO 0x2 // Set the output signal to zero\r
+#define PWM_GEN_ACT_ONE 0x3 // Set the output signal to one\r
+#define PWM_GEN_ACT_ZERO_SHIFT 0 // Shift amount for the zero action\r
+#define PWM_GEN_ACT_LOAD_SHIFT 2 // Shift amount for the load action\r
+#define PWM_GEN_ACT_A_UP_SHIFT 4 // Shift amount for the A up action\r
+#define PWM_GEN_ACT_A_DN_SHIFT 6 // Shift amount for the A dn action\r
+#define PWM_GEN_ACT_B_UP_SHIFT 8 // Shift amount for the B up action\r
+#define PWM_GEN_ACT_B_DN_SHIFT 10 // Shift amount for the B dn action\r
+\r
+//*****************************************************************************\r
+//\r
+// PWM_X Dead Band Control Register bit definitions.\r
+//\r
+//*****************************************************************************\r
+#define PWM_DBCTL_ENABLE 0x00000001 // Enable dead band insertion\r
+\r
+//*****************************************************************************\r
+//\r
+// PWM Register reset values.\r
+//\r
+//*****************************************************************************\r
+#define PWM_RV_CTL 0x00000000 // Master control of the PWM module\r
+#define PWM_RV_SYNC 0x00000000 // Counter synch for PWM generators\r
+#define PWM_RV_ENABLE 0x00000000 // Master enable for the PWM\r
+ // output pins\r
+#define PWM_RV_INVERT 0x00000000 // Inversion control for\r
+ // PWM output pins\r
+#define PWM_RV_FAULT 0x00000000 // Fault handling for the PWM\r
+ // output pins\r
+#define PWM_RV_INTEN 0x00000000 // Interrupt enable\r
+#define PWM_RV_RIS 0x00000000 // Raw interrupt status\r
+#define PWM_RV_ISC 0x00000000 // Interrupt status and clearing\r
+#define PWM_RV_STATUS 0x00000000 // Status\r
+#define PWM_RV_X_CTL 0x00000000 // Master control of the PWM\r
+ // generator block\r
+#define PWM_RV_X_INTEN 0x00000000 // Interrupt and trigger enable\r
+#define PWM_RV_X_RIS 0x00000000 // Raw interrupt status\r
+#define PWM_RV_X_ISC 0x00000000 // Interrupt status and clearing\r
+#define PWM_RV_X_LOAD 0x00000000 // The load value for the counter\r
+#define PWM_RV_X_COUNT 0x00000000 // The current counter value\r
+#define PWM_RV_X_CMPA 0x00000000 // The comparator A value\r
+#define PWM_RV_X_CMPB 0x00000000 // The comparator B value\r
+#define PWM_RV_X_GENA 0x00000000 // Controls PWM generator A\r
+#define PWM_RV_X_GENB 0x00000000 // Controls PWM generator B\r
+#define PWM_RV_X_DBCTL 0x00000000 // Control the dead band generator\r
+#define PWM_RV_X_DBRISE 0x00000000 // The dead band rising edge delay\r
+ // count\r
+#define PWM_RV_X_DBFALL 0x00000000 // The dead band falling edge delay\r
+ // count\r
+\r
+#endif // __HW_PWM_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_qei.h - Macros used when accessing the QEI hardware.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_QEI_H__\r
+#define __HW_QEI_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the offsets of the QEI registers.\r
+//\r
+//*****************************************************************************\r
+#define QEI_O_CTL 0x00000000 // Configuration and control reg.\r
+#define QEI_O_STAT 0x00000004 // Status register\r
+#define QEI_O_POS 0x00000008 // Current position register\r
+#define QEI_O_MAXPOS 0x0000000C // Maximum position register\r
+#define QEI_O_LOAD 0x00000010 // Velocity timer load register\r
+#define QEI_O_TIME 0x00000014 // Velocity timer register\r
+#define QEI_O_COUNT 0x00000018 // Velocity pulse count register\r
+#define QEI_O_SPEED 0x0000001C // Velocity speed register\r
+#define QEI_O_INTEN 0x00000020 // Interrupt enable register\r
+#define QEI_O_RIS 0x00000024 // Raw interrupt status register\r
+#define QEI_O_ISC 0x00000028 // Interrupt status register\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the QEI_CTL register.\r
+//\r
+//*****************************************************************************\r
+#define QEI_CTL_STALLEN 0x00001000 // Stall enable\r
+#define QEI_CTL_INVI 0x00000800 // Invert Index input\r
+#define QEI_CTL_INVB 0x00000400 // Invert PhB input\r
+#define QEI_CTL_INVA 0x00000200 // Invert PhA input\r
+#define QEI_CTL_VELDIV_M 0x000001C0 // Velocity predivider mask\r
+#define QEI_CTL_VELDIV_1 0x00000000 // Predivide by 1\r
+#define QEI_CTL_VELDIV_2 0x00000040 // Predivide by 2\r
+#define QEI_CTL_VELDIV_4 0x00000080 // Predivide by 4\r
+#define QEI_CTL_VELDIV_8 0x000000C0 // Predivide by 8\r
+#define QEI_CTL_VELDIV_16 0x00000100 // Predivide by 16\r
+#define QEI_CTL_VELDIV_32 0x00000140 // Predivide by 32\r
+#define QEI_CTL_VELDIV_64 0x00000180 // Predivide by 64\r
+#define QEI_CTL_VELDIV_128 0x000001C0 // Predivide by 128\r
+#define QEI_CTL_VELEN 0x00000020 // Velocity enable\r
+#define QEI_CTL_RESMODE 0x00000010 // Position counter reset mode\r
+#define QEI_CTL_CAPMODE 0x00000008 // Edge capture mode\r
+#define QEI_CTL_SIGMODE 0x00000004 // Encoder signaling mode\r
+#define QEI_CTL_SWAP 0x00000002 // Swap input signals\r
+#define QEI_CTL_ENABLE 0x00000001 // QEI enable\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the QEI_STAT register.\r
+//\r
+//*****************************************************************************\r
+#define QEI_STAT_DIRECTION 0x00000002 // Direction of rotation\r
+#define QEI_STAT_ERROR 0x00000001 // Signalling error detected\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the QEI_POS register.\r
+//\r
+//*****************************************************************************\r
+#define QEI_POS_M 0xFFFFFFFF // Current encoder position\r
+#define QEI_POS_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the QEI_MAXPOS register.\r
+//\r
+//*****************************************************************************\r
+#define QEI_MAXPOS_M 0xFFFFFFFF // Maximum encoder position\r
+#define QEI_MAXPOS_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the QEI_LOAD register.\r
+//\r
+//*****************************************************************************\r
+#define QEI_LOAD_M 0xFFFFFFFF // Velocity timer load value\r
+#define QEI_LOAD_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the QEI_TIME register.\r
+//\r
+//*****************************************************************************\r
+#define QEI_TIME_M 0xFFFFFFFF // Velocity timer current value\r
+#define QEI_TIME_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the QEI_COUNT register.\r
+//\r
+//*****************************************************************************\r
+#define QEI_COUNT_M 0xFFFFFFFF // Encoder running pulse count\r
+#define QEI_COUNT_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the QEI_SPEED register.\r
+//\r
+//*****************************************************************************\r
+#define QEI_SPEED_M 0xFFFFFFFF // Encoder pulse count\r
+#define QEI_SPEED_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the QEI_INTEN register.\r
+//\r
+//*****************************************************************************\r
+#define QEI_INTEN_ERROR 0x00000008 // Phase error detected\r
+#define QEI_INTEN_DIR 0x00000004 // Direction change\r
+#define QEI_INTEN_TIMER 0x00000002 // Velocity timer expired\r
+#define QEI_INTEN_INDEX 0x00000001 // Index pulse detected\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the QEI_RIS register.\r
+//\r
+//*****************************************************************************\r
+#define QEI_RIS_ERROR 0x00000008 // Phase error detected\r
+#define QEI_RIS_DIR 0x00000004 // Direction change\r
+#define QEI_RIS_TIMER 0x00000002 // Velocity timer expired\r
+#define QEI_RIS_INDEX 0x00000001 // Index pulse detected\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the QEI_ISC register.\r
+//\r
+//*****************************************************************************\r
+#define QEI_INT_ERROR 0x00000008 // Phase error detected\r
+#define QEI_INT_DIR 0x00000004 // Direction change\r
+#define QEI_INT_TIMER 0x00000002 // Velocity timer expired\r
+#define QEI_INT_INDEX 0x00000001 // Index pulse detected\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the reset values for the QEI registers.\r
+//\r
+//*****************************************************************************\r
+#define QEI_RV_CTL 0x00000000 // Configuration and control reg.\r
+#define QEI_RV_STAT 0x00000000 // Status register\r
+#define QEI_RV_POS 0x00000000 // Current position register\r
+#define QEI_RV_MAXPOS 0x00000000 // Maximum position register\r
+#define QEI_RV_LOAD 0x00000000 // Velocity timer load register\r
+#define QEI_RV_TIME 0x00000000 // Velocity timer register\r
+#define QEI_RV_COUNT 0x00000000 // Velocity pulse count register\r
+#define QEI_RV_SPEED 0x00000000 // Velocity speed register\r
+#define QEI_RV_INTEN 0x00000000 // Interrupt enable register\r
+#define QEI_RV_RIS 0x00000000 // Raw interrupt status register\r
+#define QEI_RV_ISC 0x00000000 // Interrupt status register\r
+\r
+#endif // __HW_QEI_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_ssi.h - Macros used when accessing the SSI hardware.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_SSI_H__\r
+#define __HW_SSI_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the offsets of the SSI registers.\r
+//\r
+//*****************************************************************************\r
+#define SSI_O_CR0 0x00000000 // Control register 0\r
+#define SSI_O_CR1 0x00000004 // Control register 1\r
+#define SSI_O_DR 0x00000008 // Data register\r
+#define SSI_O_SR 0x0000000C // Status register\r
+#define SSI_O_CPSR 0x00000010 // Clock prescale register\r
+#define SSI_O_IM 0x00000014 // Int mask set and clear register\r
+#define SSI_O_RIS 0x00000018 // Raw interrupt register\r
+#define SSI_O_MIS 0x0000001C // Masked interrupt register\r
+#define SSI_O_ICR 0x00000020 // Interrupt clear register\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SSI Control register 0.\r
+//\r
+//*****************************************************************************\r
+#define SSI_CR0_SCR 0x0000FF00 // Serial clock rate\r
+#define SSI_CR0_SPH 0x00000080 // SSPCLKOUT phase\r
+#define SSI_CR0_SPO 0x00000040 // SSPCLKOUT polarity\r
+#define SSI_CR0_FRF_MASK 0x00000030 // Frame format mask\r
+#define SSI_CR0_FRF_MOTO 0x00000000 // Motorola SPI frame format\r
+#define SSI_CR0_FRF_TI 0x00000010 // TI sync serial frame format\r
+#define SSI_CR0_FRF_NMW 0x00000020 // National Microwire frame format\r
+#define SSI_CR0_DSS 0x0000000F // Data size select\r
+#define SSI_CR0_DSS_4 0x00000003 // 4 bit data\r
+#define SSI_CR0_DSS_5 0x00000004 // 5 bit data\r
+#define SSI_CR0_DSS_6 0x00000005 // 6 bit data\r
+#define SSI_CR0_DSS_7 0x00000006 // 7 bit data\r
+#define SSI_CR0_DSS_8 0x00000007 // 8 bit data\r
+#define SSI_CR0_DSS_9 0x00000008 // 9 bit data\r
+#define SSI_CR0_DSS_10 0x00000009 // 10 bit data\r
+#define SSI_CR0_DSS_11 0x0000000A // 11 bit data\r
+#define SSI_CR0_DSS_12 0x0000000B // 12 bit data\r
+#define SSI_CR0_DSS_13 0x0000000C // 13 bit data\r
+#define SSI_CR0_DSS_14 0x0000000D // 14 bit data\r
+#define SSI_CR0_DSS_15 0x0000000E // 15 bit data\r
+#define SSI_CR0_DSS_16 0x0000000F // 16 bit data\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SSI Control register 1.\r
+//\r
+//*****************************************************************************\r
+#define SSI_CR1_SOD 0x00000008 // Slave mode output disable\r
+#define SSI_CR1_MS 0x00000004 // Master or slave mode select\r
+#define SSI_CR1_SSE 0x00000002 // Sync serial port enable\r
+#define SSI_CR1_LBM 0x00000001 // Loopback mode\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SSI Status register.\r
+//\r
+//*****************************************************************************\r
+#define SSI_SR_BSY 0x00000010 // SSI busy\r
+#define SSI_SR_RFF 0x00000008 // RX FIFO full\r
+#define SSI_SR_RNE 0x00000004 // RX FIFO not empty\r
+#define SSI_SR_TNF 0x00000002 // TX FIFO not full\r
+#define SSI_SR_TFE 0x00000001 // TX FIFO empty\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SSI clock prescale register.\r
+//\r
+//*****************************************************************************\r
+#define SSI_CPSR_CPSDVSR_MASK 0x000000FF // Clock prescale\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define information concerning the SSI Data register.\r
+//\r
+//*****************************************************************************\r
+#define TX_FIFO_SIZE (8) // Number of entries in the TX FIFO\r
+#define RX_FIFO_SIZE (8) // Number of entries in the RX FIFO\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the interrupt mask set and clear,\r
+// raw interrupt, masked interrupt, and interrupt clear registers.\r
+//\r
+//*****************************************************************************\r
+#define SSI_INT_TXFF 0x00000008 // TX FIFO interrupt\r
+#define SSI_INT_RXFF 0x00000004 // RX FIFO interrupt\r
+#define SSI_INT_RXTO 0x00000002 // RX timeout interrupt\r
+#define SSI_INT_RXOR 0x00000001 // RX overrun interrupt\r
+\r
+#endif // __HW_SSI_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_sysctl.h - Macros used when accessing the system control hardware.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_SYSCTL_H__\r
+#define __HW_SYSCTL_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the addresses of the system control registers.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_DID0 0x400fe000 // Device identification register 0\r
+#define SYSCTL_DID1 0x400fe004 // Device identification register 1\r
+#define SYSCTL_DC0 0x400fe008 // Device capabilities register 0\r
+#define SYSCTL_DC1 0x400fe010 // Device capabilities register 1\r
+#define SYSCTL_DC2 0x400fe014 // Device capabilities register 2\r
+#define SYSCTL_DC3 0x400fe018 // Device capabilities register 3\r
+#define SYSCTL_DC4 0x400fe01C // Device capabilities register 4\r
+#define SYSCTL_PBORCTL 0x400fe030 // POR/BOR reset control register\r
+#define SYSCTL_LDOPCTL 0x400fe034 // LDO power control register\r
+#define SYSCTL_SRCR0 0x400fe040 // Software reset control reg 0\r
+#define SYSCTL_SRCR1 0x400fe044 // Software reset control reg 1\r
+#define SYSCTL_SRCR2 0x400fe048 // Software reset control reg 2\r
+#define SYSCTL_RIS 0x400fe050 // Raw interrupt status register\r
+#define SYSCTL_IMC 0x400fe054 // Interrupt mask/control register\r
+#define SYSCTL_MISC 0x400fe058 // Interrupt status register\r
+#define SYSCTL_RESC 0x400fe05c // Reset cause register\r
+#define SYSCTL_RCC 0x400fe060 // Run-mode clock config register\r
+#define SYSCTL_PLLCFG 0x400fe064 // PLL configuration register\r
+#define SYSCTL_RCC2 0x400fe070 // Run-mode clock config register 2\r
+#define SYSCTL_RCGC0 0x400fe100 // Run-mode clock gating register 0\r
+#define SYSCTL_RCGC1 0x400fe104 // Run-mode clock gating register 1\r
+#define SYSCTL_RCGC2 0x400fe108 // Run-mode clock gating register 2\r
+#define SYSCTL_SCGC0 0x400fe110 // Sleep-mode clock gating reg 0\r
+#define SYSCTL_SCGC1 0x400fe114 // Sleep-mode clock gating reg 1\r
+#define SYSCTL_SCGC2 0x400fe118 // Sleep-mode clock gating reg 2\r
+#define SYSCTL_DCGC0 0x400fe120 // Deep Sleep-mode clock gate reg 0\r
+#define SYSCTL_DCGC1 0x400fe124 // Deep Sleep-mode clock gate reg 1\r
+#define SYSCTL_DCGC2 0x400fe128 // Deep Sleep-mode clock gate reg 2\r
+#define SYSCTL_DSLPCLKCFG 0x400fe144 // Deep Sleep-mode clock config reg\r
+#define SYSCTL_CLKVCLR 0x400fe150 // Clock verifcation clear register\r
+#define SYSCTL_LDOARST 0x400fe160 // LDO reset control register\r
+#define SYSCTL_USER0 0x400fe1e0 // NV User Register 0\r
+#define SYSCTL_USER1 0x400fe1e4 // NV User Register 1\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_DID0 register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_DID0_VER_MASK 0x70000000 // DID0 version mask\r
+#define SYSCTL_DID0_VER_0 0x00000000 // DID0 version 0\r
+#define SYSCTL_DID0_VER_1 0x10000000 // DID0 version 1\r
+#define SYSCTL_DID0_CLASS_MASK 0x00FF0000 // Device Class\r
+#define SYSCTL_DID0_CLASS_SANDSTORM 0x00000000 // LM3Snnn Sandstorm Device\r
+#define SYSCTL_DID0_CLASS_FURY 0x00010000 // LM3Snnnn Fury Device\r
+#define SYSCTL_DID0_MAJ_MASK 0x0000FF00 // Major revision mask\r
+#define SYSCTL_DID0_MAJ_A 0x00000000 // Major revision A\r
+#define SYSCTL_DID0_MAJ_B 0x00000100 // Major revision B\r
+#define SYSCTL_DID0_MAJ_C 0x00000200 // Major revision C\r
+#define SYSCTL_DID0_MIN_MASK 0x000000FF // Minor revision mask\r
+#define SYSCTL_DID0_MIN_0 0x00000000 // Minor revision 0\r
+#define SYSCTL_DID0_MIN_1 0x00000001 // Minor revision 1\r
+#define SYSCTL_DID0_MIN_2 0x00000002 // Minor revision 2\r
+#define SYSCTL_DID0_MIN_3 0x00000003 // Minor revision 3\r
+#define SYSCTL_DID0_MIN_4 0x00000004 // Minor revision 4\r
+#define SYSCTL_DID0_MIN_5 0x00000005 // Minor revision 5\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_DID1 register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_DID1_VER_MASK 0xF0000000 // Register version mask\r
+#define SYSCTL_DID1_FAM_MASK 0x0F000000 // Family mask\r
+#define SYSCTL_DID1_FAM_S 0x00000000 // Stellaris family\r
+#define SYSCTL_DID1_PRTNO_MASK 0x00FF0000 // Part number mask\r
+#define SYSCTL_DID1_PRTNO_101 0x00010000 // LM3S101\r
+#define SYSCTL_DID1_PRTNO_102 0x00020000 // LM3S102\r
+#define SYSCTL_DID1_PRTNO_301 0x00110000 // LM3S301\r
+#define SYSCTL_DID1_PRTNO_310 0x00120000 // LM3S310\r
+#define SYSCTL_DID1_PRTNO_315 0x00130000 // LM3S315\r
+#define SYSCTL_DID1_PRTNO_316 0x00140000 // LM3S316\r
+#define SYSCTL_DID1_PRTNO_317 0x00170000 // LM3S317\r
+#define SYSCTL_DID1_PRTNO_328 0x00150000 // LM3S328\r
+#define SYSCTL_DID1_PRTNO_601 0x00210000 // LM3S601\r
+#define SYSCTL_DID1_PRTNO_610 0x00220000 // LM3S610\r
+#define SYSCTL_DID1_PRTNO_611 0x00230000 // LM3S611\r
+#define SYSCTL_DID1_PRTNO_612 0x00240000 // LM3S612\r
+#define SYSCTL_DID1_PRTNO_613 0x00250000 // LM3S613\r
+#define SYSCTL_DID1_PRTNO_615 0x00260000 // LM3S615\r
+#define SYSCTL_DID1_PRTNO_617 0x00280000 // LM3S617\r
+#define SYSCTL_DID1_PRTNO_618 0x00290000 // LM3S618\r
+#define SYSCTL_DID1_PRTNO_628 0x00270000 // LM3S628\r
+#define SYSCTL_DID1_PRTNO_801 0x00310000 // LM3S801\r
+#define SYSCTL_DID1_PRTNO_811 0x00320000 // LM3S811\r
+#define SYSCTL_DID1_PRTNO_812 0x00330000 // LM3S812\r
+#define SYSCTL_DID1_PRTNO_815 0x00340000 // LM3S815\r
+#define SYSCTL_DID1_PRTNO_817 0x00360000 // LM3S817\r
+#define SYSCTL_DID1_PRTNO_818 0x00370000 // LM3S818\r
+#define SYSCTL_DID1_PRTNO_828 0x00350000 // LM3S828\r
+#define SYSCTL_DID1_PRTNO_2110 0x00510000 // LM3S2110\r
+#define SYSCTL_DID1_PRTNO_2139 0x00840000 // LM3S2139\r
+#define SYSCTL_DID1_PRTNO_2410 0x00A20000 // LM3S2410\r
+#define SYSCTL_DID1_PRTNO_2412 0x00590000 // LM3S2412\r
+#define SYSCTL_DID1_PRTNO_2432 0x00560000 // LM3S2432\r
+#define SYSCTL_DID1_PRTNO_2533 0x005A0000 // LM3S2533\r
+#define SYSCTL_DID1_PRTNO_2620 0x00570000 // LM3S2620\r
+#define SYSCTL_DID1_PRTNO_2637 0x00850000 // LM3S2637\r
+#define SYSCTL_DID1_PRTNO_2651 0x00530000 // LM3S2651\r
+#define SYSCTL_DID1_PRTNO_2730 0x00A40000 // LM3S2730\r
+#define SYSCTL_DID1_PRTNO_2739 0x00520000 // LM3S2739\r
+#define SYSCTL_DID1_PRTNO_2939 0x00540000 // LM3S2939\r
+#define SYSCTL_DID1_PRTNO_2948 0x008F0000 // LM3S2948\r
+#define SYSCTL_DID1_PRTNO_2950 0x00580000 // LM3S2950\r
+#define SYSCTL_DID1_PRTNO_2965 0x00550000 // LM3S2965\r
+#define SYSCTL_DID1_PRTNO_6100 0x00A10000 // LM3S6100\r
+#define SYSCTL_DID1_PRTNO_6110 0x00740000 // LM3S6110\r
+#define SYSCTL_DID1_PRTNO_6420 0x00A50000 // LM3S6420\r
+#define SYSCTL_DID1_PRTNO_6422 0x00820000 // LM3S6422\r
+#define SYSCTL_DID1_PRTNO_6432 0x00750000 // LM3S6432\r
+#define SYSCTL_DID1_PRTNO_6610 0x00710000 // LM3S6610\r
+#define SYSCTL_DID1_PRTNO_6633 0x00830000 // LM3S6633\r
+#define SYSCTL_DID1_PRTNO_6637 0x008B0000 // LM3S6637\r
+#define SYSCTL_DID1_PRTNO_6730 0x00A30000 // LM3S6730\r
+#define SYSCTL_DID1_PRTNO_6938 0x00890000 // LM3S6938\r
+#define SYSCTL_DID1_PRTNO_6952 0x00780000 // LM3S6952\r
+#define SYSCTL_DID1_PRTNO_6965 0x00730000 // LM3S6965\r
+#define SYSCTL_DID1_PINCNT_MASK 0x0000E000 // Pin count\r
+#define SYSCTL_DID1_PINCNT_100 0x00004000 // 100 pin package\r
+#define SYSCTL_DID1_TEMP_MASK 0x000000E0 // Temperature range mask\r
+#define SYSCTL_DID1_TEMP_C 0x00000000 // Commercial temp range (0..70C)\r
+#define SYSCTL_DID1_TEMP_I 0x00000020 // Industrial temp range (-40..85C)\r
+#define SYSCTL_DID1_PKG_MASK 0x00000018 // Package mask\r
+#define SYSCTL_DID1_PKG_28SOIC 0x00000000 // 28-pin SOIC\r
+#define SYSCTL_DID1_PKG_48QFP 0x00000008 // 48-pin QFP\r
+#define SYSCTL_DID1_ROHS 0x00000004 // Part is RoHS compliant\r
+#define SYSCTL_DID1_QUAL_MASK 0x00000003 // Qualification status mask\r
+#define SYSCTL_DID1_QUAL_ES 0x00000000 // Engineering sample (unqualified)\r
+#define SYSCTL_DID1_QUAL_PP 0x00000001 // Pilot production (unqualified)\r
+#define SYSCTL_DID1_QUAL_FQ 0x00000002 // Fully qualified\r
+#define SYSCTL_DID1_PRTNO_SHIFT 16\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_DC0 register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_DC0_SRAMSZ_MASK 0xFFFF0000 // SRAM size mask\r
+#define SYSCTL_DC0_SRAMSZ_2KB 0x00070000 // 2 KB of SRAM\r
+#define SYSCTL_DC0_SRAMSZ_4KB 0x000F0000 // 4 KB of SRAM\r
+#define SYSCTL_DC0_SRAMSZ_8KB 0x001F0000 // 8 KB of SRAM\r
+#define SYSCTL_DC0_SRAMSZ_16KB 0x003F0000 // 16 KB of SRAM\r
+#define SYSCTL_DC0_SRAMSZ_32KB 0x007F0000 // 32 KB of SRAM\r
+#define SYSCTL_DC0_SRAMSZ_64KB 0x00FF0000 // 64 KB of SRAM\r
+#define SYSCTL_DC0_FLASHSZ_MASK 0x0000FFFF // Flash size mask\r
+#define SYSCTL_DC0_FLASHSZ_8KB 0x00000003 // 8 KB of flash\r
+#define SYSCTL_DC0_FLASHSZ_16KB 0x00000007 // 16 KB of flash\r
+#define SYSCTL_DC0_FLASHSZ_32KB 0x0000000F // 32 KB of flash\r
+#define SYSCTL_DC0_FLASHSZ_64KB 0x0000001F // 64 KB of flash\r
+#define SYSCTL_DC0_FLASHSZ_96KB 0x0000002F // 96 KB of flash\r
+#define SYSCTL_DC0_FLASHSZ_128K 0x0000003F // 128 KB of flash\r
+#define SYSCTL_DC0_FLASHSZ_256K 0x0000007F // 256 KB of flash\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_DC1 register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_DC1_CAN1 0x02000000 // CAN1 module present\r
+#define SYSCTL_DC1_CAN0 0x01000000 // CAN0 module present\r
+#define SYSCTL_DC1_PWM 0x00100000 // PWM module present\r
+#define SYSCTL_DC1_ADC 0x00010000 // ADC module present\r
+#define SYSCTL_DC1_SYSDIV_MASK 0x0000F000 // Minimum system divider mask\r
+#define SYSCTL_DC1_ADCSPD_MASK 0x00000F00 // ADC speed mask\r
+#define SYSCTL_DC1_ADCSPD_1M 0x00000300 // 1Msps ADC\r
+#define SYSCTL_DC1_ADCSPD_500K 0x00000200 // 500Ksps ADC\r
+#define SYSCTL_DC1_ADCSPD_250K 0x00000100 // 250Ksps ADC\r
+#define SYSCTL_DC1_ADCSPD_125K 0x00000000 // 125Ksps ADC\r
+#define SYSCTL_DC1_MPU 0x00000080 // Cortex M3 MPU present\r
+#define SYSCTL_DC1_HIB 0x00000040 // Hibernation module present\r
+#define SYSCTL_DC1_TEMP 0x00000020 // Temperature sensor present\r
+#define SYSCTL_DC1_PLL 0x00000010 // PLL present\r
+#define SYSCTL_DC1_WDOG 0x00000008 // Watchdog present\r
+#define SYSCTL_DC1_SWO 0x00000004 // Serial wire output present\r
+#define SYSCTL_DC1_SWD 0x00000002 // Serial wire debug present\r
+#define SYSCTL_DC1_JTAG 0x00000001 // JTAG debug present\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_DC2 register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_DC2_COMP2 0x04000000 // Analog comparator 2 present\r
+#define SYSCTL_DC2_COMP1 0x02000000 // Analog comparator 1 present\r
+#define SYSCTL_DC2_COMP0 0x01000000 // Analog comparator 0 present\r
+#define SYSCTL_DC2_TIMER3 0x00080000 // Timer 3 present\r
+#define SYSCTL_DC2_TIMER2 0x00040000 // Timer 2 present\r
+#define SYSCTL_DC2_TIMER1 0x00020000 // Timer 1 present\r
+#define SYSCTL_DC2_TIMER0 0x00010000 // Timer 0 present\r
+#define SYSCTL_DC2_I2C1 0x00002000 // I2C 1 present\r
+#define SYSCTL_DC2_I2C0 0x00001000 // I2C 0 present\r
+#ifndef DEPRECATED\r
+#define SYSCTL_DC2_I2C 0x00001000 // I2C present\r
+#endif\r
+#define SYSCTL_DC2_QEI1 0x00000200 // QEI 1 present\r
+#define SYSCTL_DC2_QEI0 0x00000100 // QEI 0 present\r
+#ifndef DEPRECATED\r
+#define SYSCTL_DC2_QEI 0x00000100 // QEI present\r
+#endif\r
+#define SYSCTL_DC2_SSI1 0x00000020 // SSI 1 present\r
+#define SYSCTL_DC2_SSI0 0x00000010 // SSI 0 present\r
+#ifndef DEPRECATED\r
+#define SYSCTL_DC2_SSI 0x00000010 // SSI present\r
+#endif\r
+#define SYSCTL_DC2_UART2 0x00000004 // UART 2 present\r
+#define SYSCTL_DC2_UART1 0x00000002 // UART 1 present\r
+#define SYSCTL_DC2_UART0 0x00000001 // UART 0 present\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_DC3 register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_DC3_32KHZ 0x80000000 // 32kHz pin present\r
+#define SYSCTL_DC3_CCP5 0x20000000 // CCP5 pin present\r
+#define SYSCTL_DC3_CCP4 0x10000000 // CCP4 pin present\r
+#define SYSCTL_DC3_CCP3 0x08000000 // CCP3 pin present\r
+#define SYSCTL_DC3_CCP2 0x04000000 // CCP2 pin present\r
+#define SYSCTL_DC3_CCP1 0x02000000 // CCP1 pin present\r
+#define SYSCTL_DC3_CCP0 0x01000000 // CCP0 pin present\r
+#define SYSCTL_DC3_ADC7 0x00800000 // ADC7 pin present\r
+#define SYSCTL_DC3_ADC6 0x00400000 // ADC6 pin present\r
+#define SYSCTL_DC3_ADC5 0x00200000 // ADC5 pin present\r
+#define SYSCTL_DC3_ADC4 0x00100000 // ADC4 pin present\r
+#define SYSCTL_DC3_ADC3 0x00080000 // ADC3 pin present\r
+#define SYSCTL_DC3_ADC2 0x00040000 // ADC2 pin present\r
+#define SYSCTL_DC3_ADC1 0x00020000 // ADC1 pin present\r
+#define SYSCTL_DC3_ADC0 0x00010000 // ADC0 pin present\r
+#define SYSCTL_DC3_MC_FAULT0 0x00008000 // MC0 fault pin present\r
+#define SYSCTL_DC3_C2O 0x00004000 // C2o pin present\r
+#define SYSCTL_DC3_C2PLUS 0x00002000 // C2+ pin present\r
+#define SYSCTL_DC3_C2MINUS 0x00001000 // C2- pin present\r
+#define SYSCTL_DC3_C1O 0x00000800 // C1o pin present\r
+#define SYSCTL_DC3_C1PLUS 0x00000400 // C1+ pin present\r
+#define SYSCTL_DC3_C1MINUS 0x00000200 // C1- pin present\r
+#define SYSCTL_DC3_C0O 0x00000100 // C0o pin present\r
+#define SYSCTL_DC3_C0PLUS 0x00000080 // C0+ pin present\r
+#define SYSCTL_DC3_C0MINUS 0x00000040 // C0- pin present\r
+#define SYSCTL_DC3_PWM5 0x00000020 // PWM5 pin present\r
+#define SYSCTL_DC3_PWM4 0x00000010 // PWM4 pin present\r
+#define SYSCTL_DC3_PWM3 0x00000008 // PWM3 pin present\r
+#define SYSCTL_DC3_PWM2 0x00000004 // PWM2 pin present\r
+#define SYSCTL_DC3_PWM1 0x00000002 // PWM1 pin present\r
+#define SYSCTL_DC3_PWM0 0x00000001 // PWM0 pin present\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_DC4 register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_DC4_ETH 0x50000000 // Ethernet present\r
+#define SYSCTL_DC4_GPIOH 0x00000080 // GPIO port H present\r
+#define SYSCTL_DC4_GPIOG 0x00000040 // GPIO port G present\r
+#define SYSCTL_DC4_GPIOF 0x00000020 // GPIO port F present\r
+#define SYSCTL_DC4_GPIOE 0x00000010 // GPIO port E present\r
+#define SYSCTL_DC4_GPIOD 0x00000008 // GPIO port D present\r
+#define SYSCTL_DC4_GPIOC 0x00000004 // GPIO port C present\r
+#define SYSCTL_DC4_GPIOB 0x00000002 // GPIO port B present\r
+#define SYSCTL_DC4_GPIOA 0x00000001 // GPIO port A present\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_PBORCTL register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_PBORCTL_BOR_MASK 0x0000FFFC // BOR wait timer\r
+#define SYSCTL_PBORCTL_BORIOR 0x00000002 // BOR interrupt or reset\r
+#define SYSCTL_PBORCTL_BORWT 0x00000001 // BOR wait and check for noise\r
+#define SYSCTL_PBORCTL_BOR_SH 2\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_LDOPCTL register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_LDOPCTL_MASK 0x0000003F // Voltage adjust mask\r
+#define SYSCTL_LDOPCTL_2_25V 0x00000005 // LDO output of 2.25V\r
+#define SYSCTL_LDOPCTL_2_30V 0x00000004 // LDO output of 2.30V\r
+#define SYSCTL_LDOPCTL_2_35V 0x00000003 // LDO output of 2.35V\r
+#define SYSCTL_LDOPCTL_2_40V 0x00000002 // LDO output of 2.40V\r
+#define SYSCTL_LDOPCTL_2_45V 0x00000001 // LDO output of 2.45V\r
+#define SYSCTL_LDOPCTL_2_50V 0x00000000 // LDO output of 2.50V\r
+#define SYSCTL_LDOPCTL_2_55V 0x0000001F // LDO output of 2.55V\r
+#define SYSCTL_LDOPCTL_2_60V 0x0000001E // LDO output of 2.60V\r
+#define SYSCTL_LDOPCTL_2_65V 0x0000001D // LDO output of 2.65V\r
+#define SYSCTL_LDOPCTL_2_70V 0x0000001C // LDO output of 2.70V\r
+#define SYSCTL_LDOPCTL_2_75V 0x0000001B // LDO output of 2.75V\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_SRCR0, SYSCTL_RCGC0,\r
+// SYSCTL_SCGC0, and SYSCTL_DCGC0 registers.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_SET0_CAN1 0x02000000 // CAN 1 module\r
+#define SYSCTL_SET0_CAN0 0x01000000 // CAN 0 module\r
+#define SYSCTL_SET0_PWM 0x00100000 // PWM module\r
+#define SYSCTL_SET0_ADC 0x00010000 // ADC module\r
+#define SYSCTL_SET0_ADCSPD_MASK 0x00000F00 // ADC speed mask\r
+#define SYSCTL_SET0_ADCSPD_1M 0x00000300 // 1Msps ADC\r
+#define SYSCTL_SET0_ADCSPD_500K 0x00000200 // 500Ksps ADC\r
+#define SYSCTL_SET0_ADCSPD_250K 0x00000100 // 250Ksps ADC\r
+#define SYSCTL_SET0_ADCSPD_125K 0x00000000 // 125Ksps ADC\r
+#define SYSCTL_SET0_HIB 0x00000040 // Hibernation module\r
+#define SYSCTL_SET0_WDOG 0x00000008 // Watchdog module\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_SRCR1, SYSCTL_RCGC1,\r
+// SYSCTL_SCGC1, and SYSCTL_DCGC1 registers.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_SET1_COMP2 0x04000000 // Analog comparator module 2\r
+#define SYSCTL_SET1_COMP1 0x02000000 // Analog comparator module 1\r
+#define SYSCTL_SET1_COMP0 0x01000000 // Analog comparator module 0\r
+#define SYSCTL_SET1_TIMER3 0x00080000 // Timer module 3\r
+#define SYSCTL_SET1_TIMER2 0x00040000 // Timer module 2\r
+#define SYSCTL_SET1_TIMER1 0x00020000 // Timer module 1\r
+#define SYSCTL_SET1_TIMER0 0x00010000 // Timer module 0\r
+#define SYSCTL_SET1_I2C1 0x00002000 // I2C module 1\r
+#define SYSCTL_SET1_I2C0 0x00001000 // I2C module 0\r
+#ifndef DEPRECATED\r
+#define SYSCTL_SET1_I2C 0x00001000 // I2C module\r
+#endif\r
+#define SYSCTL_SET1_QEI1 0x00000200 // QEI module 1\r
+#define SYSCTL_SET1_QEI0 0x00000100 // QEI module 0\r
+#ifndef DEPRECATED\r
+#define SYSCTL_SET1_QEI 0x00000100 // QEI module\r
+#endif\r
+#define SYSCTL_SET1_SSI1 0x00000020 // SSI module 1\r
+#define SYSCTL_SET1_SSI0 0x00000010 // SSI module 0\r
+#ifndef DEPRECATED\r
+#define SYSCTL_SET1_SSI 0x00000010 // SSI module\r
+#endif\r
+#define SYSCTL_SET1_UART2 0x00000004 // UART module 2\r
+#define SYSCTL_SET1_UART1 0x00000002 // UART module 1\r
+#define SYSCTL_SET1_UART0 0x00000001 // UART module 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_SRCR2, SYSCTL_RCGC2,\r
+// SYSCTL_SCGC2, and SYSCTL_DCGC2 registers.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_SET2_ETH 0x50000000 // ETH module\r
+#define SYSCTL_SET2_GPIOH 0x00000080 // GPIO H module\r
+#define SYSCTL_SET2_GPIOG 0x00000040 // GPIO G module\r
+#define SYSCTL_SET2_GPIOF 0x00000020 // GPIO F module\r
+#define SYSCTL_SET2_GPIOE 0x00000010 // GPIO E module\r
+#define SYSCTL_SET2_GPIOD 0x00000008 // GPIO D module\r
+#define SYSCTL_SET2_GPIOC 0x00000004 // GPIO C module\r
+#define SYSCTL_SET2_GPIOB 0x00000002 // GPIO B module\r
+#define SYSCTL_SET2_GPIOA 0x00000001 // GIPO A module\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_RIS, SYSCTL_IMC, and\r
+// SYSCTL_IMS registers.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_INT_PLL_LOCK 0x00000040 // PLL lock interrupt\r
+#define SYSCTL_INT_CUR_LIMIT 0x00000020 // Current limit interrupt\r
+#define SYSCTL_INT_IOSC_FAIL 0x00000010 // Internal oscillator failure int\r
+#define SYSCTL_INT_MOSC_FAIL 0x00000008 // Main oscillator failure int\r
+#define SYSCTL_INT_POR 0x00000004 // Power on reset interrupt\r
+#define SYSCTL_INT_BOR 0x00000002 // Brown out interrupt\r
+#define SYSCTL_INT_PLL_FAIL 0x00000001 // PLL failure interrupt\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_RESC register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_RESC_LDO 0x00000020 // LDO power OK lost reset\r
+#define SYSCTL_RESC_SW 0x00000010 // Software reset\r
+#define SYSCTL_RESC_WDOG 0x00000008 // Watchdog reset\r
+#define SYSCTL_RESC_BOR 0x00000004 // Brown-out reset\r
+#define SYSCTL_RESC_POR 0x00000002 // Power on reset\r
+#define SYSCTL_RESC_EXT 0x00000001 // External reset\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_RCC register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_RCC_ACG 0x08000000 // Automatic clock gating\r
+#define SYSCTL_RCC_SYSDIV_MASK 0x07800000 // System clock divider\r
+#define SYSCTL_RCC_SYSDIV_2 0x00800000 // System clock /2\r
+#define SYSCTL_RCC_SYSDIV_3 0x01000000 // System clock /3\r
+#define SYSCTL_RCC_SYSDIV_4 0x01800000 // System clock /4\r
+#define SYSCTL_RCC_SYSDIV_5 0x02000000 // System clock /5\r
+#define SYSCTL_RCC_SYSDIV_6 0x02800000 // System clock /6\r
+#define SYSCTL_RCC_SYSDIV_7 0x03000000 // System clock /7\r
+#define SYSCTL_RCC_SYSDIV_8 0x03800000 // System clock /8\r
+#define SYSCTL_RCC_SYSDIV_9 0x04000000 // System clock /9\r
+#define SYSCTL_RCC_SYSDIV_10 0x04800000 // System clock /10\r
+#define SYSCTL_RCC_SYSDIV_11 0x05000000 // System clock /11\r
+#define SYSCTL_RCC_SYSDIV_12 0x05800000 // System clock /12\r
+#define SYSCTL_RCC_SYSDIV_13 0x06000000 // System clock /13\r
+#define SYSCTL_RCC_SYSDIV_14 0x06800000 // System clock /14\r
+#define SYSCTL_RCC_SYSDIV_15 0x07000000 // System clock /15\r
+#define SYSCTL_RCC_SYSDIV_16 0x07800000 // System clock /16\r
+#define SYSCTL_RCC_USE_SYSDIV 0x00400000 // Use sytem clock divider\r
+#define SYSCTL_RCC_USE_PWMDIV 0x00100000 // Use PWM clock divider\r
+#define SYSCTL_RCC_PWMDIV_MASK 0x000E0000 // PWM clock divider\r
+#define SYSCTL_RCC_PWMDIV_2 0x00000000 // PWM clock /2\r
+#define SYSCTL_RCC_PWMDIV_4 0x00020000 // PWM clock /4\r
+#define SYSCTL_RCC_PWMDIV_8 0x00040000 // PWM clock /8\r
+#define SYSCTL_RCC_PWMDIV_16 0x00060000 // PWM clock /16\r
+#define SYSCTL_RCC_PWMDIV_32 0x00080000 // PWM clock /32\r
+#define SYSCTL_RCC_PWMDIV_64 0x000A0000 // PWM clock /64\r
+#define SYSCTL_RCC_PWRDN 0x00002000 // PLL power down\r
+#define SYSCTL_RCC_OE 0x00001000 // PLL output enable\r
+#define SYSCTL_RCC_BYPASS 0x00000800 // PLL bypass\r
+#define SYSCTL_RCC_PLLVER 0x00000400 // PLL verification timer enable\r
+#define SYSCTL_RCC_XTAL_MASK 0x000003C0 // Crystal attached to main osc\r
+#define SYSCTL_RCC_XTAL_3_57MHZ 0x00000100 // Using a 3.579545MHz crystal\r
+#define SYSCTL_RCC_XTAL_3_68MHz 0x00000140 // Using a 3.6864MHz crystal\r
+#define SYSCTL_RCC_XTAL_4MHz 0x00000180 // Using a 4MHz crystal\r
+#define SYSCTL_RCC_XTAL_4_09MHZ 0x000001C0 // Using a 4.096MHz crystal\r
+#define SYSCTL_RCC_XTAL_4_91MHZ 0x00000200 // Using a 4.9152MHz crystal\r
+#define SYSCTL_RCC_XTAL_5MHZ 0x00000240 // Using a 5MHz crystal\r
+#define SYSCTL_RCC_XTAL_5_12MHZ 0x00000280 // Using a 5.12MHz crystal\r
+#define SYSCTL_RCC_XTAL_6MHZ 0x000002C0 // Using a 6MHz crystal\r
+#define SYSCTL_RCC_XTAL_6_14MHZ 0x00000300 // Using a 6.144MHz crystal\r
+#define SYSCTL_RCC_XTAL_7_37MHZ 0x00000340 // Using a 7.3728MHz crystal\r
+#define SYSCTL_RCC_XTAL_8MHZ 0x00000380 // Using a 8MHz crystal\r
+#define SYSCTL_RCC_XTAL_8_19MHZ 0x000003C0 // Using a 8.192MHz crystal\r
+#define SYSCTL_RCC_OSCSRC_MASK 0x00000030 // Oscillator input select\r
+#define SYSCTL_RCC_OSCSRC_MAIN 0x00000000 // Use the main oscillator\r
+#define SYSCTL_RCC_OSCSRC_INT 0x00000010 // Use the internal oscillator\r
+#define SYSCTL_RCC_OSCSRC_INT4 0x00000020 // Use the internal oscillator / 4\r
+#define SYSCTL_RCC_IOSCVER 0x00000008 // Int. osc. verification timer en\r
+#define SYSCTL_RCC_MOSCVER 0x00000004 // Main osc. verification timer en\r
+#define SYSCTL_RCC_IOSCDIS 0x00000002 // Internal oscillator disable\r
+#define SYSCTL_RCC_MOSCDIS 0x00000001 // Main oscillator disable\r
+#define SYSCTL_RCC_SYSDIV_SHIFT 23 // Shift to the SYSDIV field\r
+#define SYSCTL_RCC_PWMDIV_SHIFT 17 // Shift to the PWMDIV field\r
+#define SYSCTL_RCC_XTAL_SHIFT 6 // Shift to the XTAL field\r
+#define SYSCTL_RCC_OSCSRC_SHIFT 4 // Shift to the OSCSRC field\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_PLLCFG register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_PLLCFG_OD_MASK 0x0000C000 // Output divider\r
+#define SYSCTL_PLLCFG_OD_1 0x00000000 // Output divider is 1\r
+#define SYSCTL_PLLCFG_OD_2 0x00004000 // Output divider is 2\r
+#define SYSCTL_PLLCFG_OD_4 0x00008000 // Output divider is 4\r
+#define SYSCTL_PLLCFG_F_MASK 0x00003FE0 // PLL multiplier\r
+#define SYSCTL_PLLCFG_R_MASK 0x0000001F // Input predivider\r
+#define SYSCTL_PLLCFG_F_SHIFT 5\r
+#define SYSCTL_PLLCFG_R_SHIFT 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_RCC2 register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_RCC2_USERCC2 0x80000000 // Use RCC2\r
+#define SYSCTL_RCC2_SYSDIV2_MSK 0x1F800000 // System clock divider\r
+#define SYSCTL_RCC2_SYSDIV2_2 0x00800000 // System clock /2\r
+#define SYSCTL_RCC2_SYSDIV2_3 0x01000000 // System clock /3\r
+#define SYSCTL_RCC2_SYSDIV2_4 0x01800000 // System clock /4\r
+#define SYSCTL_RCC2_SYSDIV2_5 0x02000000 // System clock /5\r
+#define SYSCTL_RCC2_SYSDIV2_6 0x02800000 // System clock /6\r
+#define SYSCTL_RCC2_SYSDIV2_7 0x03000000 // System clock /7\r
+#define SYSCTL_RCC2_SYSDIV2_8 0x03800000 // System clock /8\r
+#define SYSCTL_RCC2_SYSDIV2_9 0x04000000 // System clock /9\r
+#define SYSCTL_RCC2_SYSDIV2_10 0x04800000 // System clock /10\r
+#define SYSCTL_RCC2_SYSDIV2_11 0x05000000 // System clock /11\r
+#define SYSCTL_RCC2_SYSDIV2_12 0x05800000 // System clock /12\r
+#define SYSCTL_RCC2_SYSDIV2_13 0x06000000 // System clock /13\r
+#define SYSCTL_RCC2_SYSDIV2_14 0x06800000 // System clock /14\r
+#define SYSCTL_RCC2_SYSDIV2_15 0x07000000 // System clock /15\r
+#define SYSCTL_RCC2_SYSDIV2_16 0x07800000 // System clock /16\r
+#define SYSCTL_RCC2_SYSDIV2_17 0x08000000 // System clock /17\r
+#define SYSCTL_RCC2_SYSDIV2_18 0x08800000 // System clock /18\r
+#define SYSCTL_RCC2_SYSDIV2_19 0x09000000 // System clock /19\r
+#define SYSCTL_RCC2_SYSDIV2_20 0x09800000 // System clock /20\r
+#define SYSCTL_RCC2_SYSDIV2_21 0x0A000000 // System clock /21\r
+#define SYSCTL_RCC2_SYSDIV2_22 0x0A800000 // System clock /22\r
+#define SYSCTL_RCC2_SYSDIV2_23 0x0B000000 // System clock /23\r
+#define SYSCTL_RCC2_SYSDIV2_24 0x0B800000 // System clock /24\r
+#define SYSCTL_RCC2_SYSDIV2_25 0x0C000000 // System clock /25\r
+#define SYSCTL_RCC2_SYSDIV2_26 0x0C800000 // System clock /26\r
+#define SYSCTL_RCC2_SYSDIV2_27 0x0D000000 // System clock /27\r
+#define SYSCTL_RCC2_SYSDIV2_28 0x0D800000 // System clock /28\r
+#define SYSCTL_RCC2_SYSDIV2_29 0x0E000000 // System clock /29\r
+#define SYSCTL_RCC2_SYSDIV2_30 0x0E800000 // System clock /30\r
+#define SYSCTL_RCC2_SYSDIV2_31 0x0F000000 // System clock /31\r
+#define SYSCTL_RCC2_SYSDIV2_32 0x0F800000 // System clock /32\r
+#define SYSCTL_RCC2_SYSDIV2_33 0x10000000 // System clock /33\r
+#define SYSCTL_RCC2_SYSDIV2_34 0x10800000 // System clock /34\r
+#define SYSCTL_RCC2_SYSDIV2_35 0x11000000 // System clock /35\r
+#define SYSCTL_RCC2_SYSDIV2_36 0x11800000 // System clock /36\r
+#define SYSCTL_RCC2_SYSDIV2_37 0x12000000 // System clock /37\r
+#define SYSCTL_RCC2_SYSDIV2_38 0x12800000 // System clock /38\r
+#define SYSCTL_RCC2_SYSDIV2_39 0x13000000 // System clock /39\r
+#define SYSCTL_RCC2_SYSDIV2_40 0x13800000 // System clock /40\r
+#define SYSCTL_RCC2_SYSDIV2_41 0x14000000 // System clock /41\r
+#define SYSCTL_RCC2_SYSDIV2_42 0x14800000 // System clock /42\r
+#define SYSCTL_RCC2_SYSDIV2_43 0x15000000 // System clock /43\r
+#define SYSCTL_RCC2_SYSDIV2_44 0x15800000 // System clock /44\r
+#define SYSCTL_RCC2_SYSDIV2_45 0x16000000 // System clock /45\r
+#define SYSCTL_RCC2_SYSDIV2_46 0x16800000 // System clock /46\r
+#define SYSCTL_RCC2_SYSDIV2_47 0x17000000 // System clock /47\r
+#define SYSCTL_RCC2_SYSDIV2_48 0x17800000 // System clock /48\r
+#define SYSCTL_RCC2_SYSDIV2_49 0x18000000 // System clock /49\r
+#define SYSCTL_RCC2_SYSDIV2_50 0x18800000 // System clock /50\r
+#define SYSCTL_RCC2_SYSDIV2_51 0x19000000 // System clock /51\r
+#define SYSCTL_RCC2_SYSDIV2_52 0x19800000 // System clock /52\r
+#define SYSCTL_RCC2_SYSDIV2_53 0x1A000000 // System clock /53\r
+#define SYSCTL_RCC2_SYSDIV2_54 0x1A800000 // System clock /54\r
+#define SYSCTL_RCC2_SYSDIV2_55 0x1B000000 // System clock /55\r
+#define SYSCTL_RCC2_SYSDIV2_56 0x1B800000 // System clock /56\r
+#define SYSCTL_RCC2_SYSDIV2_57 0x1C000000 // System clock /57\r
+#define SYSCTL_RCC2_SYSDIV2_58 0x1C800000 // System clock /58\r
+#define SYSCTL_RCC2_SYSDIV2_59 0x1D000000 // System clock /59\r
+#define SYSCTL_RCC2_SYSDIV2_60 0x1D800000 // System clock /60\r
+#define SYSCTL_RCC2_SYSDIV2_61 0x1E000000 // System clock /61\r
+#define SYSCTL_RCC2_SYSDIV2_62 0x1E800000 // System clock /62\r
+#define SYSCTL_RCC2_SYSDIV2_63 0x1F000000 // System clock /63\r
+#define SYSCTL_RCC2_SYSDIV2_64 0x1F800000 // System clock /64\r
+#define SYSCTL_RCC2_PWRDN2 0x00002000 // PLL power down\r
+#define SYSCTL_RCC2_BYPASS2 0x00000800 // PLL bypass\r
+#define SYSCTL_RCC2_OSCSRC2_MSK 0x00000070 // Oscillator input select\r
+#define SYSCTL_RCC2_OSCSRC2_MO 0x00000000 // Use the main oscillator\r
+#define SYSCTL_RCC2_OSCSRC2_IO 0x00000010 // Use the internal oscillator\r
+#define SYSCTL_RCC2_OSCSRC2_IO4 0x00000020 // Use the internal oscillator / 4\r
+#define SYSCTL_RCC2_OSCSRC2_30 0x00000030 // Use the 30 KHz internal osc.\r
+#define SYSCTL_RCC2_OSCSRC2_32 0x00000070 // Use the 32 KHz external osc.\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_DSLPCLKCFG register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_DSLPCLKCFG_D_MSK 0x1f800000 // Deep sleep system clock override\r
+#define SYSCTL_DSLPCLKCFG_D_2 0x00800000 // System clock /2\r
+#define SYSCTL_DSLPCLKCFG_D_3 0x01000000 // System clock /3\r
+#define SYSCTL_DSLPCLKCFG_D_4 0x01800000 // System clock /4\r
+#define SYSCTL_DSLPCLKCFG_D_5 0x02000000 // System clock /5\r
+#define SYSCTL_DSLPCLKCFG_D_6 0x02800000 // System clock /6\r
+#define SYSCTL_DSLPCLKCFG_D_7 0x03000000 // System clock /7\r
+#define SYSCTL_DSLPCLKCFG_D_8 0x03800000 // System clock /8\r
+#define SYSCTL_DSLPCLKCFG_D_9 0x04000000 // System clock /9\r
+#define SYSCTL_DSLPCLKCFG_D_10 0x04800000 // System clock /10\r
+#define SYSCTL_DSLPCLKCFG_D_11 0x05000000 // System clock /11\r
+#define SYSCTL_DSLPCLKCFG_D_12 0x05800000 // System clock /12\r
+#define SYSCTL_DSLPCLKCFG_D_13 0x06000000 // System clock /13\r
+#define SYSCTL_DSLPCLKCFG_D_14 0x06800000 // System clock /14\r
+#define SYSCTL_DSLPCLKCFG_D_15 0x07000000 // System clock /15\r
+#define SYSCTL_DSLPCLKCFG_D_16 0x07800000 // System clock /16\r
+#define SYSCTL_DSLPCLKCFG_D_17 0x08000000 // System clock /17\r
+#define SYSCTL_DSLPCLKCFG_D_18 0x08800000 // System clock /18\r
+#define SYSCTL_DSLPCLKCFG_D_19 0x09000000 // System clock /19\r
+#define SYSCTL_DSLPCLKCFG_D_20 0x09800000 // System clock /20\r
+#define SYSCTL_DSLPCLKCFG_D_21 0x0A000000 // System clock /21\r
+#define SYSCTL_DSLPCLKCFG_D_22 0x0A800000 // System clock /22\r
+#define SYSCTL_DSLPCLKCFG_D_23 0x0B000000 // System clock /23\r
+#define SYSCTL_DSLPCLKCFG_D_24 0x0B800000 // System clock /24\r
+#define SYSCTL_DSLPCLKCFG_D_25 0x0C000000 // System clock /25\r
+#define SYSCTL_DSLPCLKCFG_D_26 0x0C800000 // System clock /26\r
+#define SYSCTL_DSLPCLKCFG_D_27 0x0D000000 // System clock /27\r
+#define SYSCTL_DSLPCLKCFG_D_28 0x0D800000 // System clock /28\r
+#define SYSCTL_DSLPCLKCFG_D_29 0x0E000000 // System clock /29\r
+#define SYSCTL_DSLPCLKCFG_D_30 0x0E800000 // System clock /30\r
+#define SYSCTL_DSLPCLKCFG_D_31 0x0F000000 // System clock /31\r
+#define SYSCTL_DSLPCLKCFG_D_32 0x0F800000 // System clock /32\r
+#define SYSCTL_DSLPCLKCFG_D_33 0x10000000 // System clock /33\r
+#define SYSCTL_DSLPCLKCFG_D_34 0x10800000 // System clock /34\r
+#define SYSCTL_DSLPCLKCFG_D_35 0x11000000 // System clock /35\r
+#define SYSCTL_DSLPCLKCFG_D_36 0x11800000 // System clock /36\r
+#define SYSCTL_DSLPCLKCFG_D_37 0x12000000 // System clock /37\r
+#define SYSCTL_DSLPCLKCFG_D_38 0x12800000 // System clock /38\r
+#define SYSCTL_DSLPCLKCFG_D_39 0x13000000 // System clock /39\r
+#define SYSCTL_DSLPCLKCFG_D_40 0x13800000 // System clock /40\r
+#define SYSCTL_DSLPCLKCFG_D_41 0x14000000 // System clock /41\r
+#define SYSCTL_DSLPCLKCFG_D_42 0x14800000 // System clock /42\r
+#define SYSCTL_DSLPCLKCFG_D_43 0x15000000 // System clock /43\r
+#define SYSCTL_DSLPCLKCFG_D_44 0x15800000 // System clock /44\r
+#define SYSCTL_DSLPCLKCFG_D_45 0x16000000 // System clock /45\r
+#define SYSCTL_DSLPCLKCFG_D_46 0x16800000 // System clock /46\r
+#define SYSCTL_DSLPCLKCFG_D_47 0x17000000 // System clock /47\r
+#define SYSCTL_DSLPCLKCFG_D_48 0x17800000 // System clock /48\r
+#define SYSCTL_DSLPCLKCFG_D_49 0x18000000 // System clock /49\r
+#define SYSCTL_DSLPCLKCFG_D_50 0x18800000 // System clock /50\r
+#define SYSCTL_DSLPCLKCFG_D_51 0x19000000 // System clock /51\r
+#define SYSCTL_DSLPCLKCFG_D_52 0x19800000 // System clock /52\r
+#define SYSCTL_DSLPCLKCFG_D_53 0x1A000000 // System clock /53\r
+#define SYSCTL_DSLPCLKCFG_D_54 0x1A800000 // System clock /54\r
+#define SYSCTL_DSLPCLKCFG_D_55 0x1B000000 // System clock /55\r
+#define SYSCTL_DSLPCLKCFG_D_56 0x1B800000 // System clock /56\r
+#define SYSCTL_DSLPCLKCFG_D_57 0x1C000000 // System clock /57\r
+#define SYSCTL_DSLPCLKCFG_D_58 0x1C800000 // System clock /58\r
+#define SYSCTL_DSLPCLKCFG_D_59 0x1D000000 // System clock /59\r
+#define SYSCTL_DSLPCLKCFG_D_60 0x1D800000 // System clock /60\r
+#define SYSCTL_DSLPCLKCFG_D_61 0x1E000000 // System clock /61\r
+#define SYSCTL_DSLPCLKCFG_D_62 0x1E800000 // System clock /62\r
+#define SYSCTL_DSLPCLKCFG_D_63 0x1F000000 // System clock /63\r
+#define SYSCTL_DSLPCLKCFG_D_64 0x1F800000 // System clock /64\r
+#define SYSCTL_DSLPCLKCFG_O_MSK 0x00000070 // Deep sleep oscillator override\r
+#define SYSCTL_DSLPCLKCFG_O_IGN 0x00000000 // Do not override\r
+#define SYSCTL_DSLPCLKCFG_O_IO 0x00000010 // Use the internal oscillator\r
+#define SYSCTL_DSLPCLKCFG_O_30 0x00000030 // Use the 30 KHz internal osc.\r
+#define SYSCTL_DSLPCLKCFG_O_32 0x00000070 // Use the 32 KHz external osc.\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_CLKVCLR register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_CLKVCLR_CLR 0x00000001 // Clear clock verification fault\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_LDOARST register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_LDOARST_ARST 0x00000001 // Allow LDO to reset device\r
+\r
+#endif // __HW_SYSCTL_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_timer.h - Defines and macros used when accessing the timer.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_TIMER_H__\r
+#define __HW_TIMER_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the offsets of the timer registers.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_O_CFG 0x00000000 // Configuration register\r
+#define TIMER_O_TAMR 0x00000004 // TimerA mode register\r
+#define TIMER_O_TBMR 0x00000008 // TimerB mode register\r
+#define TIMER_O_CTL 0x0000000C // Control register\r
+#define TIMER_O_IMR 0x00000018 // Interrupt mask register\r
+#define TIMER_O_RIS 0x0000001C // Interrupt status register\r
+#define TIMER_O_MIS 0x00000020 // Masked interrupt status reg.\r
+#define TIMER_O_ICR 0x00000024 // Interrupt clear register\r
+#define TIMER_O_TAILR 0x00000028 // TimerA interval load register\r
+#define TIMER_O_TBILR 0x0000002C // TimerB interval load register\r
+#define TIMER_O_TAMATCHR 0x00000030 // TimerA match register\r
+#define TIMER_O_TBMATCHR 0x00000034 // TimerB match register\r
+#define TIMER_O_TAPR 0x00000038 // TimerA prescale register\r
+#define TIMER_O_TBPR 0x0000003C // TimerB prescale register\r
+#define TIMER_O_TAPMR 0x00000040 // TimerA prescale match register\r
+#define TIMER_O_TBPMR 0x00000044 // TimerB prescale match register\r
+#define TIMER_O_TAR 0x00000048 // TimerA register\r
+#define TIMER_O_TBR 0x0000004C // TimerB register\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the reset values of the timer registers.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_RV_CFG 0x00000000 // Configuration register RV\r
+#define TIMER_RV_TAMR 0x00000000 // TimerA mode register RV\r
+#define TIMER_RV_TBMR 0x00000000 // TimerB mode register RV\r
+#define TIMER_RV_CTL 0x00000000 // Control register RV\r
+#define TIMER_RV_IMR 0x00000000 // Interrupt mask register RV\r
+#define TIMER_RV_RIS 0x00000000 // Interrupt status register RV\r
+#define TIMER_RV_MIS 0x00000000 // Masked interrupt status reg RV\r
+#define TIMER_RV_ICR 0x00000000 // Interrupt clear register RV\r
+#define TIMER_RV_TAILR 0xFFFFFFFF // TimerA interval load reg RV\r
+#define TIMER_RV_TBILR 0x0000FFFF // TimerB interval load reg RV\r
+#define TIMER_RV_TAMATCHR 0xFFFFFFFF // TimerA match register RV\r
+#define TIMER_RV_TBMATCHR 0x0000FFFF // TimerB match register RV\r
+#define TIMER_RV_TAPR 0x00000000 // TimerA prescale register RV\r
+#define TIMER_RV_TBPR 0x00000000 // TimerB prescale register RV\r
+#define TIMER_RV_TAPMR 0x00000000 // TimerA prescale match reg RV\r
+#define TIMER_RV_TBPMR 0x00000000 // TimerB prescale match regi RV\r
+#define TIMER_RV_TAR 0xFFFFFFFF // TimerA register RV\r
+#define TIMER_RV_TBR 0x0000FFFF // TimerB register RV\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the TIMER_CFG register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_CFG_CFG_MSK 0x00000007 // Configuration options mask\r
+#define TIMER_CFG_16_BIT 0x00000004 // Two 16 bit timers\r
+#define TIMER_CFG_32_BIT_RTC 0x00000001 // 32 bit RTC\r
+#define TIMER_CFG_32_BIT_TIMER 0x00000000 // 32 bit timer\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the TIMER_TnMR register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_TNMR_TNAMS 0x00000008 // Alternate mode select\r
+#define TIMER_TNMR_TNCMR 0x00000004 // Capture mode - count or time\r
+#define TIMER_TNMR_TNTMR_MSK 0x00000003 // Timer mode mask\r
+#define TIMER_TNMR_TNTMR_CAP 0x00000003 // Mode - capture\r
+#define TIMER_TNMR_TNTMR_PERIOD 0x00000002 // Mode - periodic\r
+#define TIMER_TNMR_TNTMR_1_SHOT 0x00000001 // Mode - one shot\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the TIMER_CTL register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_CTL_TBPWML 0x00004000 // TimerB PWM output level invert\r
+#define TIMER_CTL_TBOTE 0x00002000 // TimerB output trigger enable\r
+#define TIMER_CTL_TBEVENT_MSK 0x00000C00 // TimerB event mode mask\r
+#define TIMER_CTL_TBEVENT_BOTH 0x00000C00 // TimerB event mode - both edges\r
+#define TIMER_CTL_TBEVENT_NEG 0x00000400 // TimerB event mode - neg edge\r
+#define TIMER_CTL_TBEVENT_POS 0x00000000 // TimerB event mode - pos edge\r
+#define TIMER_CTL_TBSTALL 0x00000200 // TimerB stall enable\r
+#define TIMER_CTL_TBEN 0x00000100 // TimerB enable\r
+#define TIMER_CTL_TAPWML 0x00000040 // TimerA PWM output level invert\r
+#define TIMER_CTL_TAOTE 0x00000020 // TimerA output trigger enable\r
+#define TIMER_CTL_RTCEN 0x00000010 // RTC counter enable\r
+#define TIMER_CTL_TAEVENT_MSK 0x0000000C // TimerA event mode mask\r
+#define TIMER_CTL_TAEVENT_BOTH 0x0000000C // TimerA event mode - both edges\r
+#define TIMER_CTL_TAEVENT_NEG 0x00000004 // TimerA event mode - neg edge\r
+#define TIMER_CTL_TAEVENT_POS 0x00000000 // TimerA event mode - pos edge\r
+#define TIMER_CTL_TASTALL 0x00000002 // TimerA stall enable\r
+#define TIMER_CTL_TAEN 0x00000001 // TimerA enable\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the TIMER_IMR register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_IMR_CBEIM 0x00000400 // CaptureB event interrupt mask\r
+#define TIMER_IMR_CBMIM 0x00000200 // CaptureB match interrupt mask\r
+#define TIMER_IMR_TBTOIM 0x00000100 // TimerB time out interrupt mask\r
+#define TIMER_IMR_RTCIM 0x00000008 // RTC interrupt mask\r
+#define TIMER_IMR_CAEIM 0x00000004 // CaptureA event interrupt mask\r
+#define TIMER_IMR_CAMIM 0x00000002 // CaptureA match interrupt mask\r
+#define TIMER_IMR_TATOIM 0x00000001 // TimerA time out interrupt mask\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the TIMER_RIS register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_RIS_CBERIS 0x00000400 // CaptureB event raw int status\r
+#define TIMER_RIS_CBMRIS 0x00000200 // CaptureB match raw int status\r
+#define TIMER_RIS_TBTORIS 0x00000100 // TimerB time out raw int status\r
+#define TIMER_RIS_RTCRIS 0x00000008 // RTC raw int status\r
+#define TIMER_RIS_CAERIS 0x00000004 // CaptureA event raw int status\r
+#define TIMER_RIS_CAMRIS 0x00000002 // CaptureA match raw int status\r
+#define TIMER_RIS_TATORIS 0x00000001 // TimerA time out raw int status\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the TIMER_MIS register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_RIS_CBEMIS 0x00000400 // CaptureB event masked int status\r
+#define TIMER_RIS_CBMMIS 0x00000200 // CaptureB match masked int status\r
+#define TIMER_RIS_TBTOMIS 0x00000100 // TimerB time out masked int stat\r
+#define TIMER_RIS_RTCMIS 0x00000008 // RTC masked int status\r
+#define TIMER_RIS_CAEMIS 0x00000004 // CaptureA event masked int status\r
+#define TIMER_RIS_CAMMIS 0x00000002 // CaptureA match masked int status\r
+#define TIMER_RIS_TATOMIS 0x00000001 // TimerA time out masked int stat\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the TIMER_ICR register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_ICR_CBECINT 0x00000400 // CaptureB event interrupt clear\r
+#define TIMER_ICR_CBMCINT 0x00000200 // CaptureB match interrupt clear\r
+#define TIMER_ICR_TBTOCINT 0x00000100 // TimerB time out interrupt clear\r
+#define TIMER_ICR_RTCCINT 0x00000008 // RTC interrupt clear\r
+#define TIMER_ICR_CAECINT 0x00000004 // CaptureA event interrupt clear\r
+#define TIMER_ICR_CAMCINT 0x00000002 // CaptureA match interrupt clear\r
+#define TIMER_ICR_TATOCINT 0x00000001 // TimerA time out interrupt clear\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the TIMER_TAILR register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_TAILR_TAILRH 0xFFFF0000 // TimerB load val in 32 bit mode\r
+#define TIMER_TAILR_TAILRL 0x0000FFFF // TimerA interval load value\r
+\r
+//*****************************************************************************\r
+//\r
+// The following defines the bit fields in the TIMER_TBILR register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_TBILR_TBILRL 0x0000FFFF // TimerB interval load value\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the TIMER_TAMATCHR register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_TAMATCHR_TAMRH 0xFFFF0000 // TimerB match val in 32 bit mode\r
+#define TIMER_TAMATCHR_TAMRL 0x0000FFFF // TimerA match value\r
+\r
+//*****************************************************************************\r
+//\r
+// The following defines the bit fields in the TIMER_TBMATCHR register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_TBMATCHR_TBMRL 0x0000FFFF // TimerB match load value\r
+\r
+//*****************************************************************************\r
+//\r
+// The following defines the bit fields in the TIMER_TnPR register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_TNPR_TNPSR 0x000000FF // TimerN prescale value\r
+\r
+//*****************************************************************************\r
+//\r
+// The following defines the bit fields in the TIMER_TnPMR register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_TNPMR_TNPSMR 0x000000FF // TimerN prescale match value\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the TIMER_TAR register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_TAR_TARH 0xFFFF0000 // TimerB val in 32 bit mode\r
+#define TIMER_TAR_TARL 0x0000FFFF // TimerA value\r
+\r
+//*****************************************************************************\r
+//\r
+// The following defines the bit fields in the TIMER_TBR register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_TBR_TBRL 0x0000FFFF // TimerB value\r
+\r
+#endif // __HW_TIMER_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_types.h - Common types and macros.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_TYPES_H__\r
+#define __HW_TYPES_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// Define a boolean type, and values for true and false.\r
+//\r
+//*****************************************************************************\r
+typedef unsigned char tBoolean;\r
+\r
+#ifndef true\r
+#define true 1\r
+#endif\r
+\r
+#ifndef false\r
+#define false 0\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Macros for hardware access, both direct and via the bit-band region.\r
+//\r
+//*****************************************************************************\r
+#define HWREG(x) \\r
+ (*((volatile unsigned long *)(x)))\r
+#define HWREGH(x) \\r
+ (*((volatile unsigned short *)(x)))\r
+#define HWREGB(x) \\r
+ (*((volatile unsigned char *)(x)))\r
+#define HWREGBITW(x, b) \\r
+ HWREG(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \\r
+ (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2))\r
+#define HWREGBITH(x, b) \\r
+ HWREGH(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \\r
+ (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2))\r
+#define HWREGBITB(x, b) \\r
+ HWREGB(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \\r
+ (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2))\r
+\r
+//*****************************************************************************\r
+//\r
+// Helper Macros for determining silicon revisions, etc.\r
+//\r
+// These macros will be used by Driverlib at "run-time" to create necessary\r
+// conditional code blocks that will allow a single version of the Driverlib\r
+// "binary" code to support multiple(all) Stellaris silicon revisions.\r
+//\r
+// It is expected that these macros will be used inside of a standard 'C' \r
+// conditional block of code, e.g.\r
+//\r
+// if(DEVICE_IS_SANDSTORM())\r
+// {\r
+// do some Sandstorm specific code here.\r
+// }\r
+//\r
+// By default, these macros will be defined as run-time checks of the\r
+// appropriate register(s) to allow creation of run-time conditional code\r
+// blocks for a common DriverLib across the entire Stellaris family.\r
+//\r
+// However, if code-space optimization is required, these macros can be "hard-\r
+// coded" for a specific version of Stellaris silicon. Many compilers will\r
+// then detect the "hard-coded" conditionals, and appropriately optimize the\r
+// code blocks, eliminating any "unreachable" code. This would result in \r
+// a smaller Driverlib, thus producing a smaller final application size, but\r
+// at the cost of limiting the Driverlib binary to a specific Stellaris\r
+// silicon revision.\r
+//\r
+//*****************************************************************************\r
+#ifndef DEVICE_IS_SANDSTORM\r
+#define DEVICE_IS_SANDSTORM \\r
+ (((HWREG(SYSCTL_DID0) & SYSCTL_DID0_VER_MASK) == SYSCTL_DID0_VER_0) || \\r
+ (((HWREG(SYSCTL_DID0) & SYSCTL_DID0_VER_MASK) == SYSCTL_DID0_VER_1) && \\r
+ ((HWREG(SYSCTL_DID0) & SYSCTL_DID0_CLASS_MASK) == \\r
+ SYSCTL_DID0_CLASS_SANDSTORM)))\r
+#endif\r
+\r
+#ifndef DEVICE_IS_FURY\r
+#define DEVICE_IS_FURY \\r
+ (((HWREG(SYSCTL_DID0) & SYSCTL_DID0_VER_MASK) == SYSCTL_DID0_VER_1) && \\r
+ ((HWREG(SYSCTL_DID0) & SYSCTL_DID0_CLASS_MASK) == \\r
+ SYSCTL_DID0_CLASS_FURY))\r
+#endif\r
+\r
+#ifndef DEVICE_IS_REVA2\r
+#define DEVICE_IS_REVA2 \\r
+ (((HWREG(SYSCTL_DID0) & SYSCTL_DID0_MAJ_MASK) == SYSCTL_DID0_MAJ_A) && \\r
+ ((HWREG(SYSCTL_DID0) & SYSCTL_DID0_MIN_MASK) == SYSCTL_DID0_MIN_2))\r
+#endif\r
+\r
+#ifndef DEVICE_IS_REVC1\r
+#define DEVICE_IS_REVC1 \\r
+ (((HWREG(SYSCTL_DID0) & SYSCTL_DID0_MAJ_MASK) == SYSCTL_DID0_MAJ_C) && \\r
+ ((HWREG(SYSCTL_DID0) & SYSCTL_DID0_MIN_MASK) == SYSCTL_DID0_MIN_1))\r
+#endif\r
+\r
+#ifndef DEVICE_IS_REVC2\r
+#define DEVICE_IS_REVC2 \\r
+ (((HWREG(SYSCTL_DID0) & SYSCTL_DID0_MAJ_MASK) == SYSCTL_DID0_MAJ_C) && \\r
+ ((HWREG(SYSCTL_DID0) & SYSCTL_DID0_MIN_MASK) == SYSCTL_DID0_MIN_2))\r
+#endif\r
+\r
+#endif // __HW_TYPES_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_uart.h - Macros and defines used when accessing the UART hardware\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_UART_H__\r
+#define __HW_UART_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// UART Register Offsets.\r
+//\r
+//*****************************************************************************\r
+#define UART_O_DR 0x00000000 // Data Register\r
+#define UART_O_RSR 0x00000004 // Receive Status Register (read)\r
+#define UART_O_ECR 0x00000004 // Error Clear Register (write)\r
+#define UART_O_FR 0x00000018 // Flag Register (read only)\r
+#define UART_O_IBRD 0x00000024 // Integer Baud Rate Divisor Reg\r
+#define UART_O_FBRD 0x00000028 // Fractional Baud Rate Divisor Reg\r
+#define UART_O_LCR_H 0x0000002C // Line Control Register, HIGH byte\r
+#define UART_O_CTL 0x00000030 // Control Register\r
+#define UART_O_IFLS 0x00000034 // Interrupt FIFO Level Select Reg\r
+#define UART_O_IM 0x00000038 // Interrupt Mask Set/Clear Reg\r
+#define UART_O_RIS 0x0000003C // Raw Interrupt Status Register\r
+#define UART_O_MIS 0x00000040 // Masked Interrupt Status Register\r
+#define UART_O_ICR 0x00000044 // Interrupt Clear Register\r
+#define UART_O_PeriphID4 0x00000FD0 //\r
+#define UART_O_PeriphID5 0x00000FD4 //\r
+#define UART_O_PeriphID6 0x00000FD8 //\r
+#define UART_O_PeriphID7 0x00000FDC //\r
+#define UART_O_PeriphID0 0x00000FE0 //\r
+#define UART_O_PeriphID1 0x00000FE4 //\r
+#define UART_O_PeriphID2 0x00000FE8 //\r
+#define UART_O_PeriphID3 0x00000FEC //\r
+#define UART_O_PCellID0 0x00000FF0 //\r
+#define UART_O_PCellID1 0x00000FF4 //\r
+#define UART_O_PCellID2 0x00000FF8 //\r
+#define UART_O_PCellID3 0x00000FFC //\r
+\r
+//*****************************************************************************\r
+//\r
+// Data Register bits\r
+//\r
+//*****************************************************************************\r
+#define UART_DR_OE 0x00000800 // Overrun Error\r
+#define UART_DR_BE 0x00000400 // Break Error\r
+#define UART_DR_PE 0x00000200 // Parity Error\r
+#define UART_DR_FE 0x00000100 // Framing Error\r
+#define UART_DR_DATA_MASK 0x000000FF // UART data\r
+\r
+//*****************************************************************************\r
+//\r
+// Receive Status Register bits\r
+//\r
+//*****************************************************************************\r
+#define UART_RSR_OE 0x00000008 // Overrun Error\r
+#define UART_RSR_BE 0x00000004 // Break Error\r
+#define UART_RSR_PE 0x00000002 // Parity Error\r
+#define UART_RSR_FE 0x00000001 // Framing Error\r
+\r
+//*****************************************************************************\r
+//\r
+// Flag Register bits\r
+//\r
+//*****************************************************************************\r
+#define UART_FR_TXFE 0x00000080 // TX FIFO Empty\r
+#define UART_FR_RXFF 0x00000040 // RX FIFO Full\r
+#define UART_FR_TXFF 0x00000020 // TX FIFO Full\r
+#define UART_FR_RXFE 0x00000010 // RX FIFO Empty\r
+#define UART_FR_BUSY 0x00000008 // UART Busy\r
+\r
+//*****************************************************************************\r
+//\r
+// Integer baud-rate divisor\r
+//\r
+//*****************************************************************************\r
+#define UART_IBRD_DIVINT_MASK 0x0000FFFF // Integer baud-rate divisor\r
+\r
+//*****************************************************************************\r
+//\r
+// Fractional baud-rate divisor\r
+//\r
+//*****************************************************************************\r
+#define UART_FBRD_DIVFRAC_MASK 0x0000003F // Fractional baud-rate divisor\r
+\r
+//*****************************************************************************\r
+//\r
+// Line Control Register High bits\r
+//\r
+//*****************************************************************************\r
+#define UART_LCR_H_SPS 0x00000080 // Stick Parity Select\r
+#define UART_LCR_H_WLEN 0x00000060 // Word length\r
+#define UART_LCR_H_WLEN_8 0x00000060 // 8 bit data\r
+#define UART_LCR_H_WLEN_7 0x00000040 // 7 bit data\r
+#define UART_LCR_H_WLEN_6 0x00000020 // 6 bit data\r
+#define UART_LCR_H_WLEN_5 0x00000000 // 5 bit data\r
+#define UART_LCR_H_FEN 0x00000010 // Enable FIFO\r
+#define UART_LCR_H_STP2 0x00000008 // Two Stop Bits Select\r
+#define UART_LCR_H_EPS 0x00000004 // Even Parity Select\r
+#define UART_LCR_H_PEN 0x00000002 // Parity Enable\r
+#define UART_LCR_H_BRK 0x00000001 // Send Break\r
+\r
+//*****************************************************************************\r
+//\r
+// Control Register bits\r
+//\r
+//*****************************************************************************\r
+#define UART_CTL_RXE 0x00000200 // Receive Enable\r
+#define UART_CTL_TXE 0x00000100 // Transmit Enable\r
+#define UART_CTL_LBE 0x00000080 // Loopback Enable\r
+#define UART_CTL_SIRLP 0x00000004 // SIR (IrDA) Low Power Enable\r
+#define UART_CTL_SIREN 0x00000002 // SIR (IrDA) Enable\r
+#define UART_CTL_UARTEN 0x00000001 // UART Enable\r
+\r
+//*****************************************************************************\r
+//\r
+// Interrupt FIFO Level Select Register bits\r
+//\r
+//*****************************************************************************\r
+#define UART_IFLS_RX1_8 0x00000000 // 1/8 Full\r
+#define UART_IFLS_RX2_8 0x00000010 // 1/4 Full\r
+#define UART_IFLS_RX4_8 0x00000020 // 1/2 Full\r
+#define UART_IFLS_RX6_8 0x00000030 // 3/4 Full\r
+#define UART_IFLS_RX7_8 0x00000040 // 7/8 Full\r
+#define UART_IFLS_TX1_8 0x00000000 // 1/8 Full\r
+#define UART_IFLS_TX2_8 0x00000001 // 1/4 Full\r
+#define UART_IFLS_TX4_8 0x00000002 // 1/2 Full\r
+#define UART_IFLS_TX6_8 0x00000003 // 3/4 Full\r
+#define UART_IFLS_TX7_8 0x00000004 // 7/8 Full\r
+\r
+//*****************************************************************************\r
+//\r
+// Interrupt Mask Set/Clear Register bits\r
+//\r
+//*****************************************************************************\r
+#define UART_IM_OEIM 0x00000400 // Overrun Error Interrupt Mask\r
+#define UART_IM_BEIM 0x00000200 // Break Error Interrupt Mask\r
+#define UART_IM_PEIM 0x00000100 // Parity Error Interrupt Mask\r
+#define UART_IM_FEIM 0x00000080 // Framing Error Interrupt Mask\r
+#define UART_IM_RTIM 0x00000040 // Receive Timeout Interrupt Mask\r
+#define UART_IM_TXIM 0x00000020 // Transmit Interrupt Mask\r
+#define UART_IM_RXIM 0x00000010 // Receive Interrupt Mask\r
+\r
+//*****************************************************************************\r
+//\r
+// Raw Interrupt Status Register\r
+//\r
+//*****************************************************************************\r
+#define UART_RIS_OERIS 0x00000400 // Overrun Error Interrupt Status\r
+#define UART_RIS_BERIS 0x00000200 // Break Error Interrupt Status\r
+#define UART_RIS_PERIS 0x00000100 // Parity Error Interrupt Status\r
+#define UART_RIS_FERIS 0x00000080 // Framing Error Interrupt Status\r
+#define UART_RIS_RTRIS 0x00000040 // Receive Timeout Interrupt Status\r
+#define UART_RIS_TXRIS 0x00000020 // Transmit Interrupt Status\r
+#define UART_RIS_RXRIS 0x00000010 // Receive Interrupt Status\r
+\r
+//*****************************************************************************\r
+//\r
+// Masked Interrupt Status Register\r
+//\r
+//*****************************************************************************\r
+#define UART_MIS_OEMIS 0x00000400 // Overrun Error Interrupt Status\r
+#define UART_MIS_BEMIS 0x00000200 // Break Error Interrupt Status\r
+#define UART_MIS_PEMIS 0x00000100 // Parity Error Interrupt Status\r
+#define UART_MIS_FEMIS 0x00000080 // Framing Error Interrupt Status\r
+#define UART_MIS_RTMIS 0x00000040 // Receive Timeout Interrupt Status\r
+#define UART_MIS_TXMIS 0x00000020 // Transmit Interrupt Status\r
+#define UART_MIS_RXMIS 0x00000010 // Receive Interrupt Status\r
+\r
+//*****************************************************************************\r
+//\r
+// Interrupt Clear Register bits\r
+//\r
+//*****************************************************************************\r
+#define UART_ICR_OEIC 0x00000400 // Overrun Error Interrupt Clear\r
+#define UART_ICR_BEIC 0x00000200 // Break Error Interrupt Clear\r
+#define UART_ICR_PEIC 0x00000100 // Parity Error Interrupt Clear\r
+#define UART_ICR_FEIC 0x00000080 // Framing Error Interrupt Clear\r
+#define UART_ICR_RTIC 0x00000040 // Receive Timeout Interrupt Clear\r
+#define UART_ICR_TXIC 0x00000020 // Transmit Interrupt Clear\r
+#define UART_ICR_RXIC 0x00000010 // Receive Interrupt Clear\r
+\r
+#define UART_RSR_ANY (UART_RSR_OE | \\r
+ UART_RSR_BE | \\r
+ UART_RSR_PE | \\r
+ UART_RSR_FE)\r
+\r
+//*****************************************************************************\r
+//\r
+// Reset Values for UART Registers.\r
+//\r
+//*****************************************************************************\r
+#define UART_RV_DR 0x00000000\r
+#define UART_RV_RSR 0x00000000\r
+#define UART_RV_ECR 0x00000000\r
+#define UART_RV_FR 0x00000090\r
+#define UART_RV_IBRD 0x00000000\r
+#define UART_RV_FBRD 0x00000000\r
+#define UART_RV_LCR_H 0x00000000\r
+#define UART_RV_CTL 0x00000300\r
+#define UART_RV_IFLS 0x00000012\r
+#define UART_RV_IM 0x00000000\r
+#define UART_RV_RIS 0x00000000\r
+#define UART_RV_MIS 0x00000000\r
+#define UART_RV_ICR 0x00000000\r
+#define UART_RV_PeriphID4 0x00000000\r
+#define UART_RV_PeriphID5 0x00000000\r
+#define UART_RV_PeriphID6 0x00000000\r
+#define UART_RV_PeriphID7 0x00000000\r
+#define UART_RV_PeriphID0 0x00000011\r
+#define UART_RV_PeriphID1 0x00000000\r
+#define UART_RV_PeriphID2 0x00000018\r
+#define UART_RV_PeriphID3 0x00000001\r
+#define UART_RV_PCellID0 0x0000000D\r
+#define UART_RV_PCellID1 0x000000F0\r
+#define UART_RV_PCellID2 0x00000005\r
+#define UART_RV_PCellID3 0x000000B1\r
+\r
+#endif // __HW_UART_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_watchdog.h - Macros used when accessing the Watchdog Timer hardware.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_WATCHDOG_H__\r
+#define __HW_WATCHDOG_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the offsets of the Watchdog Timer registers.\r
+//\r
+//*****************************************************************************\r
+#define WDT_O_LOAD 0x00000000 // Load register\r
+#define WDT_O_VALUE 0x00000004 // Current value register\r
+#define WDT_O_CTL 0x00000008 // Control register\r
+#define WDT_O_ICR 0x0000000C // Interrupt clear register\r
+#define WDT_O_RIS 0x00000010 // Raw interrupt status register\r
+#define WDT_O_MIS 0x00000014 // Masked interrupt status register\r
+#define WDT_O_TEST 0x00000418 // Test register\r
+#define WDT_O_LOCK 0x00000C00 // Lock register\r
+#define WDT_O_PeriphID4 0x00000FD0 //\r
+#define WDT_O_PeriphID5 0x00000FD4 //\r
+#define WDT_O_PeriphID6 0x00000FD8 //\r
+#define WDT_O_PeriphID7 0x00000FDC //\r
+#define WDT_O_PeriphID0 0x00000FE0 //\r
+#define WDT_O_PeriphID1 0x00000FE4 //\r
+#define WDT_O_PeriphID2 0x00000FE8 //\r
+#define WDT_O_PeriphID3 0x00000FEC //\r
+#define WDT_O_PCellID0 0x00000FF0 //\r
+#define WDT_O_PCellID1 0x00000FF4 //\r
+#define WDT_O_PCellID2 0x00000FF8 //\r
+#define WDT_O_PCellID3 0x00000FFC //\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the WDT_CTL register.\r
+//\r
+//*****************************************************************************\r
+#define WDT_CTL_RESEN 0x00000002 // Enable reset output\r
+#define WDT_CTL_INTEN 0x00000001 // Enable the WDT counter and int\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the WDT_ISR, WDT_RIS, and WDT_MIS\r
+// registers.\r
+//\r
+//*****************************************************************************\r
+#define WDT_INT_TIMEOUT 0x00000001 // Watchdog timer expired\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the WDT_TEST register.\r
+//\r
+//*****************************************************************************\r
+#define WDT_TEST_STALL 0x00000100 // Watchdog stall enable\r
+#ifndef DEPRECATED\r
+#define WDT_TEST_STALL_EN 0x00000100 // Watchdog stall enable\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the WDT_LOCK register.\r
+//\r
+//*****************************************************************************\r
+#define WDT_LOCK_LOCKED 0x00000001 // Watchdog timer is locked\r
+#define WDT_LOCK_UNLOCKED 0x00000000 // Watchdog timer is unlocked\r
+#define WDT_LOCK_UNLOCK 0x1ACCE551 // Unlocks the watchdog timer\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the reset values for the WDT registers.\r
+//\r
+//*****************************************************************************\r
+#define WDT_RV_LOAD 0xFFFFFFFF // Load register\r
+#define WDT_RV_VALUE 0xFFFFFFFF // Current value register\r
+#define WDT_RV_CTL 0x00000000 // Control register\r
+#define WDT_RV_RIS 0x00000000 // Raw interrupt status register\r
+#define WDT_RV_MIS 0x00000000 // Masked interrupt status register\r
+#define WDT_RV_LOCK 0x00000000 // Lock register\r
+#define WDT_RV_PeriphID4 0x00000000 //\r
+#define WDT_RV_PeriphID5 0x00000000 //\r
+#define WDT_RV_PeriphID6 0x00000000 //\r
+#define WDT_RV_PeriphID7 0x00000000 //\r
+#define WDT_RV_PeriphID0 0x00000005 //\r
+#define WDT_RV_PeriphID1 0x00000018 //\r
+#define WDT_RV_PeriphID2 0x00000018 //\r
+#define WDT_RV_PeriphID3 0x00000001 //\r
+#define WDT_RV_PCellID0 0x0000000D //\r
+#define WDT_RV_PCellID1 0x000000F0 //\r
+#define WDT_RV_PCellID2 0x00000005 //\r
+#define WDT_RV_PCellID3 0x000000B1 //\r
+\r
+#endif // __HW_WATCHDOG_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// i2c.h - Prototypes for the I2C Driver.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __I2C_H__\r
+#define __I2C_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Defines for the API.\r
+//\r
+//*****************************************************************************\r
+//*****************************************************************************\r
+//\r
+// Interrupt defines.\r
+//\r
+//*****************************************************************************\r
+#define I2C_INT_MASTER 0x00000001\r
+#define I2C_INT_SLAVE 0x00000002\r
+\r
+//*****************************************************************************\r
+//\r
+// I2C Master commands.\r
+//\r
+//*****************************************************************************\r
+#define I2C_MASTER_CMD_SINGLE_SEND \\r
+ (I2C_MASTER_CS_STOP | I2C_MASTER_CS_START | I2C_MASTER_CS_RUN)\r
+#define I2C_MASTER_CMD_SINGLE_RECEIVE \\r
+ (I2C_MASTER_CS_STOP | I2C_MASTER_CS_START | I2C_MASTER_CS_RUN)\r
+#define I2C_MASTER_CMD_BURST_SEND_START \\r
+ (I2C_MASTER_CS_START | I2C_MASTER_CS_RUN)\r
+#define I2C_MASTER_CMD_BURST_SEND_CONT \\r
+ (I2C_MASTER_CS_RUN)\r
+#define I2C_MASTER_CMD_BURST_SEND_FINISH \\r
+ (I2C_MASTER_CS_STOP | I2C_MASTER_CS_RUN)\r
+#define I2C_MASTER_CMD_BURST_SEND_ERROR_STOP \\r
+ (I2C_MASTER_CS_STOP)\r
+#define I2C_MASTER_CMD_BURST_RECEIVE_START \\r
+ (I2C_MASTER_CS_ACK | I2C_MASTER_CS_START | I2C_MASTER_CS_RUN)\r
+#define I2C_MASTER_CMD_BURST_RECEIVE_CONT \\r
+ (I2C_MASTER_CS_ACK | I2C_MASTER_CS_RUN)\r
+#define I2C_MASTER_CMD_BURST_RECEIVE_FINISH \\r
+ (I2C_MASTER_CS_STOP | I2C_MASTER_CS_RUN)\r
+#define I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP \\r
+ (I2C_MASTER_CS_STOP | I2C_MASTER_CS_RUN)\r
+\r
+//*****************************************************************************\r
+//\r
+// I2C Master error status.\r
+//\r
+//*****************************************************************************\r
+#define I2C_MASTER_ERR_NONE 0\r
+#define I2C_MASTER_ERR_ADDR_ACK 0x00000004\r
+#define I2C_MASTER_ERR_DATA_ACK 0x00000008\r
+#define I2C_MASTER_ERR_ARB_LOST 0x00000010\r
+\r
+//*****************************************************************************\r
+//\r
+// I2C Slave action requests\r
+//\r
+//*****************************************************************************\r
+#define I2C_SLAVE_ACT_NONE 0\r
+#define I2C_SLAVE_ACT_RREQ 0x00000001 // Master has sent data\r
+#define I2C_SLAVE_ACT_TREQ 0x00000002 // Master has requested data\r
+\r
+//*****************************************************************************\r
+// Miscellaneous I2C driver definitions.\r
+//*****************************************************************************\r
+#define I2C_MASTER_MAX_RETRIES 1000 // Number of retries\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+extern void I2CIntRegister(unsigned long ulBase, void(fnHandler)(void));\r
+extern void I2CIntUnregister(unsigned long ulBase);\r
+extern tBoolean I2CMasterBusBusy(unsigned long ulBase);\r
+extern tBoolean I2CMasterBusy(unsigned long ulBase);\r
+extern void I2CMasterControl(unsigned long ulBase, unsigned long ulCmd);\r
+extern unsigned long I2CMasterDataGet(unsigned long ulBase);\r
+extern void I2CMasterDataPut(unsigned long ulBase, unsigned char ucData);\r
+extern void I2CMasterDisable(unsigned long ulBase);\r
+extern void I2CMasterEnable(unsigned long ulBase);\r
+extern unsigned long I2CMasterErr(unsigned long ulBase);\r
+extern void I2CMasterInit(unsigned long ulBase, tBoolean bFast);\r
+extern void I2CMasterIntClear(unsigned long ulBase);\r
+extern void I2CMasterIntDisable(unsigned long ulBase);\r
+extern void I2CMasterIntEnable(unsigned long ulBase);\r
+extern tBoolean I2CMasterIntStatus(unsigned long ulBase, tBoolean bMasked);\r
+extern void I2CMasterSlaveAddrSet(unsigned long ulBase,\r
+ unsigned char ucSlaveAddr,\r
+ tBoolean bReceive);\r
+extern unsigned long I2CSlaveDataGet(unsigned long ulBase);\r
+extern void I2CSlaveDataPut(unsigned long ulBase, unsigned char ucData);\r
+extern void I2CSlaveDisable(unsigned long ulBase);\r
+extern void I2CSlaveEnable(unsigned long ulBase);\r
+extern void I2CSlaveInit(unsigned long ulBase, unsigned char ucSlaveAddr);\r
+extern void I2CSlaveIntClear(unsigned long ulBase);\r
+extern void I2CSlaveIntDisable(unsigned long ulBase);\r
+extern void I2CSlaveIntEnable(unsigned long ulBase);\r
+extern tBoolean I2CSlaveIntStatus(unsigned long ulBase, tBoolean bMasked);\r
+extern unsigned long I2CSlaveStatus(unsigned long ulBase);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __I2C_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// interrupt.h - Prototypes for the NVIC Interrupt Controller Driver.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __INTERRUPT_H__\r
+#define __INTERRUPT_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+extern void IntMasterEnable(void);\r
+extern void IntMasterDisable(void);\r
+extern void IntRegister(unsigned long ulInterrupt, void (*pfnHandler)(void));\r
+extern void IntUnregister(unsigned long ulInterrupt);\r
+extern void IntPriorityGroupingSet(unsigned long ulBits);\r
+extern unsigned long IntPriorityGroupingGet(void);\r
+extern void IntPrioritySet(unsigned long ulInterrupt,\r
+ unsigned char ucPriority);\r
+extern long IntPriorityGet(unsigned long ulInterrupt);\r
+extern void IntEnable(unsigned long ulInterrupt);\r
+extern void IntDisable(unsigned long ulInterrupt);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __INTERRUPT_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// flash.h - Prototypes for the flash driver.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __FLASH_H__\r
+#define __FLASH_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to FlashProtectSet(), and returned by\r
+// FlashProtectGet().\r
+//\r
+//*****************************************************************************\r
+typedef enum\r
+{\r
+ FlashReadWrite, // Flash can be read and written\r
+ FlashReadOnly, // Flash can only be read\r
+ FlashExecuteOnly // Flash can only be executed\r
+}\r
+tFlashProtection;\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+extern unsigned long FlashUsecGet(void);\r
+extern void FlashUsecSet(unsigned long ulClocks);\r
+extern long FlashErase(unsigned long ulAddress);\r
+extern long FlashProgram(unsigned long *pulData, unsigned long ulAddress,\r
+ unsigned long ulCount);\r
+extern tFlashProtection FlashProtectGet(unsigned long ulAddress);\r
+extern long FlashProtectSet(unsigned long ulAddress,\r
+ tFlashProtection eProtect);\r
+extern long FlashProtectSave(void);\r
+extern long FlashUserGet(unsigned long *pulUser0, unsigned long *pulUser1);\r
+extern long FlashUserSet(unsigned long ulUser0, unsigned long ulUser1);\r
+extern long FlashUserSave(void);\r
+extern void FlashIntRegister(void (*pfnHandler)(void));\r
+extern void FlashIntUnregister(void);\r
+extern void FlashIntEnable(unsigned long ulIntFlags);\r
+extern void FlashIntDisable(unsigned long ulIntFlags);\r
+extern unsigned long FlashIntGetStatus(tBoolean bMasked);\r
+extern void FlashIntClear(unsigned long ulIntFlags);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __FLASH_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// timer.h - Prototypes for the timer module\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __TIMER_H__\r
+#define __TIMER_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to TimerConfigure as the ulConfig parameter.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_CFG_32_BIT_OS 0x00000001 // 32-bit one-shot timer\r
+#define TIMER_CFG_32_BIT_PER 0x00000002 // 32-bit periodic timer\r
+#define TIMER_CFG_32_RTC 0x01000000 // 32-bit RTC timer\r
+#define TIMER_CFG_16_BIT_PAIR 0x04000000 // Two 16-bit timers\r
+#define TIMER_CFG_A_ONE_SHOT 0x00000001 // Timer A one-shot timer\r
+#define TIMER_CFG_A_PERIODIC 0x00000002 // Timer A periodic timer\r
+#define TIMER_CFG_A_CAP_COUNT 0x00000003 // Timer A event counter\r
+#define TIMER_CFG_A_CAP_TIME 0x00000007 // Timer A event timer\r
+#define TIMER_CFG_A_PWM 0x0000000A // Timer A PWM output\r
+#define TIMER_CFG_B_ONE_SHOT 0x00000100 // Timer B one-shot timer\r
+#define TIMER_CFG_B_PERIODIC 0x00000200 // Timer B periodic timer\r
+#define TIMER_CFG_B_CAP_COUNT 0x00000300 // Timer B event counter\r
+#define TIMER_CFG_B_CAP_TIME 0x00000700 // Timer B event timer\r
+#define TIMER_CFG_B_PWM 0x00000A00 // Timer B PWM output\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to TimerIntEnable, TimerIntDisable, and\r
+// TimerIntClear as the ulIntFlags parameter, and returned from TimerIntStatus.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_CAPB_EVENT 0x00000400 // CaptureB event interrupt\r
+#define TIMER_CAPB_MATCH 0x00000200 // CaptureB match interrupt\r
+#define TIMER_TIMB_TIMEOUT 0x00000100 // TimerB time out interrupt\r
+#define TIMER_RTC_MATCH 0x00000008 // RTC interrupt mask\r
+#define TIMER_CAPA_EVENT 0x00000004 // CaptureA event interrupt\r
+#define TIMER_CAPA_MATCH 0x00000002 // CaptureA match interrupt\r
+#define TIMER_TIMA_TIMEOUT 0x00000001 // TimerA time out interrupt\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to TimerControlEvent as the ulEvent parameter.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_EVENT_POS_EDGE 0x00000000 // Count positive edges\r
+#define TIMER_EVENT_NEG_EDGE 0x00000404 // Count negative edges\r
+#define TIMER_EVENT_BOTH_EDGES 0x00000C0C // Count both edges\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to most of the timer APIs as the ulTimer\r
+// parameter.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_A 0x000000ff // Timer A\r
+#define TIMER_B 0x0000ff00 // Timer B\r
+#define TIMER_BOTH 0x0000ffff // Timer Both\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+extern void TimerEnable(unsigned long ulBase, unsigned long ulTimer);\r
+extern void TimerDisable(unsigned long ulBase, unsigned long ulTimer);\r
+extern void TimerConfigure(unsigned long ulBase, unsigned long ulConfig);\r
+extern void TimerControlLevel(unsigned long ulBase, unsigned long ulTimer,\r
+ tBoolean bInvert);\r
+extern void TimerControlTrigger(unsigned long ulBase, unsigned long ulTimer,\r
+ tBoolean bEnable);\r
+extern void TimerControlEvent(unsigned long ulBase, unsigned long ulTimer,\r
+ unsigned long ulEvent);\r
+extern void TimerControlStall(unsigned long ulBase, unsigned long ulTimer,\r
+ tBoolean bStall);\r
+extern void TimerRTCEnable(unsigned long ulBase);\r
+extern void TimerRTCDisable(unsigned long ulBase);\r
+extern void TimerPrescaleSet(unsigned long ulBase, unsigned long ulTimer,\r
+ unsigned long ulValue);\r
+extern unsigned long TimerPrescaleGet(unsigned long ulBase,\r
+ unsigned long ulTimer);\r
+extern void TimerPrescaleMatchSet(unsigned long ulBase, unsigned long ulTimer,\r
+ unsigned long ulValue);\r
+extern unsigned long TimerPrescaleMatchGet(unsigned long ulBase,\r
+ unsigned long ulTimer);\r
+extern void TimerLoadSet(unsigned long ulBase, unsigned long ulTimer,\r
+ unsigned long ulValue);\r
+extern unsigned long TimerLoadGet(unsigned long ulBase, unsigned long ulTimer);\r
+extern unsigned long TimerValueGet(unsigned long ulBase,\r
+ unsigned long ulTimer);\r
+extern void TimerMatchSet(unsigned long ulBase, unsigned long ulTimer,\r
+ unsigned long ulValue);\r
+extern unsigned long TimerMatchGet(unsigned long ulBase,\r
+ unsigned long ulTimer);\r
+extern void TimerIntRegister(unsigned long ulBase, unsigned long ulTimer,\r
+ void (*pfnHandler)(void));\r
+extern void TimerIntUnregister(unsigned long ulBase, unsigned long ulTimer);\r
+extern void TimerIntEnable(unsigned long ulBase, unsigned long ulIntFlags);\r
+extern void TimerIntDisable(unsigned long ulBase, unsigned long ulIntFlags);\r
+extern unsigned long TimerIntStatus(unsigned long ulBase, tBoolean bMasked);\r
+extern void TimerIntClear(unsigned long ulBase, unsigned long ulIntFlags);\r
+extern void TimerQuiesce(unsigned long ulBase);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __TIMER_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// osram128x64x4.c - Driver for the OSRAM 128x64x4 graphical OLED display.\r
+//\r
+// Copyright (c) 2006-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+//*****************************************************************************\r
+//\r
+//! \addtogroup ek_lm3sx965_api\r
+//! @{\r
+//\r
+//*****************************************************************************\r
+\r
+#include "hw_ssi.h"\r
+#include "hw_memmap.h"\r
+#include "hw_sysctl.h"\r
+#include "hw_types.h"\r
+#include "debug.h"\r
+#include "gpio.h"\r
+#include "ssi.h"\r
+#include "sysctl.h"\r
+#include "osram128x64x4.h"\r
+\r
+//*****************************************************************************\r
+//\r
+// Flag to indicate if SSI port is enabled for OSRAM usage.\r
+//\r
+//*****************************************************************************\r
+static volatile tBoolean g_bSSIEnabled = false;\r
+\r
+//*****************************************************************************\r
+//\r
+// Define the OSRAM 128x64x4 Remap Setting(s). This will be used in\r
+// several places in the code to switch between vertical and horizontal\r
+// address incrementing.\r
+//\r
+// The Remap Command (0xA0) takes one 8-bit parameter. The parameter is\r
+// defined as follows.\r
+//\r
+// Bit 7: Reserved\r
+// Bit 6: Disable(0)/Enable(1) COM Split Odd Even\r
+// When enabled, the COM signals are split Odd on one side, even on\r
+// the other. Otherwise, they are split 0-39 on one side, 40-79 on\r
+// the other.\r
+// Bit 5: Reserved\r
+// Bit 4: Disable(0)/Enable(1) COM Remap\r
+// When Enabled, ROW 0-79 map to COM 79-0 (i.e. reverse row order)\r
+// Bit 3: Reserved\r
+// Bit 2: Horizontal(0)/Vertical(1) Address Increment\r
+// When set, data RAM address will increment along the column rather\r
+// than along the row.\r
+// Bit 1: Disable(0)/Enable(1) Nibble Remap\r
+// When enabled, the upper and lower nibbles in the DATA bus for access\r
+// to the data RAM are swapped.\r
+// Bit 0: Disable(0)/Enable(1) Column Address Remap\r
+// When enabled, DATA RAM columns 0-63 are remapped to Segment Columns\r
+// 127-0.\r
+//\r
+//*****************************************************************************\r
+#define OSRAM_INIT_REMAP 0x52\r
+#define OSRAM_INIT_OFFSET 0x4C\r
+static const unsigned char g_pucOSRAM128x64x4VerticalInc[] = { 0xA0, 0x56 };\r
+static const unsigned char g_pucOSRAM128x64x4HorizontalInc[] = { 0xA0, 0x52 };\r
+\r
+//*****************************************************************************\r
+//\r
+// A 5x7 font (in a 6x8 cell, where the sixth column is omitted from this\r
+// table) for displaying text on the OLED display. The data is organized as\r
+// bytes from the left column to the right column, with each byte containing\r
+// the top row in the LSB and the bottom row in the MSB.\r
+//\r
+// Note: This is the same font data that is used in the EK-LM3S811\r
+// osram96x16x1 driver. The single bit-per-pixel is expaned in the StringDraw\r
+// function to the appropriate four bit-per-pixel gray scale format.\r
+//\r
+//*****************************************************************************\r
+static const unsigned char g_pucFont[96][5] =\r
+{\r
+ { 0x00, 0x00, 0x00, 0x00, 0x00 }, // " "\r
+ { 0x00, 0x00, 0x4f, 0x00, 0x00 }, // !\r
+ { 0x00, 0x07, 0x00, 0x07, 0x00 }, // "\r
+ { 0x14, 0x7f, 0x14, 0x7f, 0x14 }, // #\r
+ { 0x24, 0x2a, 0x7f, 0x2a, 0x12 }, // $\r
+ { 0x23, 0x13, 0x08, 0x64, 0x62 }, // %\r
+ { 0x36, 0x49, 0x55, 0x22, 0x50 }, // &\r
+ { 0x00, 0x05, 0x03, 0x00, 0x00 }, // '\r
+ { 0x00, 0x1c, 0x22, 0x41, 0x00 }, // (\r
+ { 0x00, 0x41, 0x22, 0x1c, 0x00 }, // )\r
+ { 0x14, 0x08, 0x3e, 0x08, 0x14 }, // *\r
+ { 0x08, 0x08, 0x3e, 0x08, 0x08 }, // +\r
+ { 0x00, 0x50, 0x30, 0x00, 0x00 }, // ,\r
+ { 0x08, 0x08, 0x08, 0x08, 0x08 }, // -\r
+ { 0x00, 0x60, 0x60, 0x00, 0x00 }, // .\r
+ { 0x20, 0x10, 0x08, 0x04, 0x02 }, // /\r
+ { 0x3e, 0x51, 0x49, 0x45, 0x3e }, // 0\r
+ { 0x00, 0x42, 0x7f, 0x40, 0x00 }, // 1\r
+ { 0x42, 0x61, 0x51, 0x49, 0x46 }, // 2\r
+ { 0x21, 0x41, 0x45, 0x4b, 0x31 }, // 3\r
+ { 0x18, 0x14, 0x12, 0x7f, 0x10 }, // 4\r
+ { 0x27, 0x45, 0x45, 0x45, 0x39 }, // 5\r
+ { 0x3c, 0x4a, 0x49, 0x49, 0x30 }, // 6\r
+ { 0x01, 0x71, 0x09, 0x05, 0x03 }, // 7\r
+ { 0x36, 0x49, 0x49, 0x49, 0x36 }, // 8\r
+ { 0x06, 0x49, 0x49, 0x29, 0x1e }, // 9\r
+ { 0x00, 0x36, 0x36, 0x00, 0x00 }, // :\r
+ { 0x00, 0x56, 0x36, 0x00, 0x00 }, // ;\r
+ { 0x08, 0x14, 0x22, 0x41, 0x00 }, // <\r
+ { 0x14, 0x14, 0x14, 0x14, 0x14 }, // =\r
+ { 0x00, 0x41, 0x22, 0x14, 0x08 }, // >\r
+ { 0x02, 0x01, 0x51, 0x09, 0x06 }, // ?\r
+ { 0x32, 0x49, 0x79, 0x41, 0x3e }, // @\r
+ { 0x7e, 0x11, 0x11, 0x11, 0x7e }, // A\r
+ { 0x7f, 0x49, 0x49, 0x49, 0x36 }, // B\r
+ { 0x3e, 0x41, 0x41, 0x41, 0x22 }, // C\r
+ { 0x7f, 0x41, 0x41, 0x22, 0x1c }, // D\r
+ { 0x7f, 0x49, 0x49, 0x49, 0x41 }, // E\r
+ { 0x7f, 0x09, 0x09, 0x09, 0x01 }, // F\r
+ { 0x3e, 0x41, 0x49, 0x49, 0x7a }, // G\r
+ { 0x7f, 0x08, 0x08, 0x08, 0x7f }, // H\r
+ { 0x00, 0x41, 0x7f, 0x41, 0x00 }, // I\r
+ { 0x20, 0x40, 0x41, 0x3f, 0x01 }, // J\r
+ { 0x7f, 0x08, 0x14, 0x22, 0x41 }, // K\r
+ { 0x7f, 0x40, 0x40, 0x40, 0x40 }, // L\r
+ { 0x7f, 0x02, 0x0c, 0x02, 0x7f }, // M\r
+ { 0x7f, 0x04, 0x08, 0x10, 0x7f }, // N\r
+ { 0x3e, 0x41, 0x41, 0x41, 0x3e }, // O\r
+ { 0x7f, 0x09, 0x09, 0x09, 0x06 }, // P\r
+ { 0x3e, 0x41, 0x51, 0x21, 0x5e }, // Q\r
+ { 0x7f, 0x09, 0x19, 0x29, 0x46 }, // R\r
+ { 0x46, 0x49, 0x49, 0x49, 0x31 }, // S\r
+ { 0x01, 0x01, 0x7f, 0x01, 0x01 }, // T\r
+ { 0x3f, 0x40, 0x40, 0x40, 0x3f }, // U\r
+ { 0x1f, 0x20, 0x40, 0x20, 0x1f }, // V\r
+ { 0x3f, 0x40, 0x38, 0x40, 0x3f }, // W\r
+ { 0x63, 0x14, 0x08, 0x14, 0x63 }, // X\r
+ { 0x07, 0x08, 0x70, 0x08, 0x07 }, // Y\r
+ { 0x61, 0x51, 0x49, 0x45, 0x43 }, // Z\r
+ { 0x00, 0x7f, 0x41, 0x41, 0x00 }, // [\r
+ { 0x02, 0x04, 0x08, 0x10, 0x20 }, // "\"\r
+ { 0x00, 0x41, 0x41, 0x7f, 0x00 }, // ]\r
+ { 0x04, 0x02, 0x01, 0x02, 0x04 }, // ^\r
+ { 0x40, 0x40, 0x40, 0x40, 0x40 }, // _\r
+ { 0x00, 0x01, 0x02, 0x04, 0x00 }, // `\r
+ { 0x20, 0x54, 0x54, 0x54, 0x78 }, // a\r
+ { 0x7f, 0x48, 0x44, 0x44, 0x38 }, // b\r
+ { 0x38, 0x44, 0x44, 0x44, 0x20 }, // c\r
+ { 0x38, 0x44, 0x44, 0x48, 0x7f }, // d\r
+ { 0x38, 0x54, 0x54, 0x54, 0x18 }, // e\r
+ { 0x08, 0x7e, 0x09, 0x01, 0x02 }, // f\r
+ { 0x0c, 0x52, 0x52, 0x52, 0x3e }, // g\r
+ { 0x7f, 0x08, 0x04, 0x04, 0x78 }, // h\r
+ { 0x00, 0x44, 0x7d, 0x40, 0x00 }, // i\r
+ { 0x20, 0x40, 0x44, 0x3d, 0x00 }, // j\r
+ { 0x7f, 0x10, 0x28, 0x44, 0x00 }, // k\r
+ { 0x00, 0x41, 0x7f, 0x40, 0x00 }, // l\r
+ { 0x7c, 0x04, 0x18, 0x04, 0x78 }, // m\r
+ { 0x7c, 0x08, 0x04, 0x04, 0x78 }, // n\r
+ { 0x38, 0x44, 0x44, 0x44, 0x38 }, // o\r
+ { 0x7c, 0x14, 0x14, 0x14, 0x08 }, // p\r
+ { 0x08, 0x14, 0x14, 0x18, 0x7c }, // q\r
+ { 0x7c, 0x08, 0x04, 0x04, 0x08 }, // r\r
+ { 0x48, 0x54, 0x54, 0x54, 0x20 }, // s\r
+ { 0x04, 0x3f, 0x44, 0x40, 0x20 }, // t\r
+ { 0x3c, 0x40, 0x40, 0x20, 0x7c }, // u\r
+ { 0x1c, 0x20, 0x40, 0x20, 0x1c }, // v\r
+ { 0x3c, 0x40, 0x30, 0x40, 0x3c }, // w\r
+ { 0x44, 0x28, 0x10, 0x28, 0x44 }, // x\r
+ { 0x0c, 0x50, 0x50, 0x50, 0x3c }, // y\r
+ { 0x44, 0x64, 0x54, 0x4c, 0x44 }, // z\r
+ { 0x00, 0x08, 0x36, 0x41, 0x00 }, // {\r
+ { 0x00, 0x00, 0x7f, 0x00, 0x00 }, // |\r
+ { 0x00, 0x41, 0x36, 0x08, 0x00 }, // }\r
+ { 0x02, 0x01, 0x02, 0x04, 0x02 }, // ~\r
+ { 0x02, 0x01, 0x02, 0x04, 0x02 }, // ~\r
+};\r
+\r
+//*****************************************************************************\r
+//\r
+// The sequence of commands used to initialize the SSD0303 controller. Each\r
+// command is described as follows: there is a byte specifying the number of\r
+// bytes in the command sequence, followed by that many bytes of command data.\r
+// Note: This initialization sequence is derived from OSRAM App Note AN018.\r
+//\r
+//*****************************************************************************\r
+static const unsigned char g_pucOSRAM128x64x4Init[] =\r
+{\r
+ //\r
+ // Column Address\r
+ //\r
+ 4, 0x15, 0, 63, 0xe3,\r
+\r
+ //\r
+ // Row Address\r
+ //\r
+ 4, 0x75, 0, 63, 0xe3,\r
+\r
+ //\r
+ // Contrast Control\r
+ //\r
+ 3, 0x81, 50, 0xe3,\r
+\r
+ //\r
+ // Half Current Range\r
+ //\r
+ 2, 0x85, 0xe3,\r
+\r
+ //\r
+ // Display Re-map\r
+ //\r
+ 3, 0xA0, OSRAM_INIT_REMAP, 0xe3,\r
+\r
+ //\r
+ // Display Start Line\r
+ //\r
+ 3, 0xA1, 0, 0xe3,\r
+\r
+ //\r
+ // Display Offset\r
+ //\r
+ 3, 0xA2, OSRAM_INIT_OFFSET, 0xe3,\r
+\r
+ //\r
+ // Display Mode Normal\r
+ //\r
+ 2, 0xA4, 0xe3,\r
+\r
+ //\r
+ // Multiplex Ratio\r
+ //\r
+ 3, 0xA8, 63, 0xe3,\r
+\r
+ //\r
+ // Phase Length\r
+ //\r
+ 3, 0xB1, 0x22, 0xe3,\r
+\r
+ //\r
+ // Row Period\r
+ //\r
+ 3, 0xB2, 70, 0xe3,\r
+\r
+ //\r
+ // Display Clock Divide\r
+ //\r
+ 3, 0xB3, 0xF1, 0xe3,\r
+\r
+ //\r
+ // VSL\r
+ //\r
+ 3, 0xBF, 0x0D, 0xe3,\r
+\r
+ //\r
+ // VCOMH\r
+ //\r
+ 3, 0xBE, 0x02, 0xe3,\r
+\r
+ //\r
+ // VP\r
+ //\r
+ 3, 0xBC, 0x10, 0xe3,\r
+\r
+ //\r
+ // Gamma\r
+ //\r
+ 10, 0xB8, 0x01, 0x11, 0x22, 0x32, 0x43, 0x54, 0x65, 0x76, 0xe3,\r
+\r
+ //\r
+ // Set DC-DC\r
+ 3, 0xAD, 0x03, 0xe3,\r
+\r
+ //\r
+ // Display ON/OFF\r
+ //\r
+ 2, 0xAF, 0xe3,\r
+};\r
+\r
+//*****************************************************************************\r
+//\r
+//! \internal\r
+//!\r
+//! Write a sequence of command bytes to the SSD0323 controller.\r
+//!\r
+//! The data is written in a polled fashion; this function will not return\r
+//! until the entire byte sequence has been written to the controller.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+static void\r
+OSRAMWriteCommand(const unsigned char *pucBuffer, unsigned long ulCount)\r
+{\r
+ unsigned long ulTemp;\r
+\r
+ //\r
+ // Return iff SSI port is not enabled for OSRAM.\r
+ //\r
+ if(!g_bSSIEnabled)\r
+ {\r
+ return;\r
+ }\r
+\r
+ //\r
+ // Clear the command/control bit to enable command mode.\r
+ //\r
+ GPIOPinWrite(GPIO_PORTC_BASE, GPIO_PIN_7, 0);\r
+\r
+ //\r
+ // Loop while there are more bytes left to be transferred.\r
+ //\r
+ while(ulCount != 0)\r
+ {\r
+ //\r
+ // Write the next byte to the controller.\r
+ //\r
+ SSIDataPut(SSI0_BASE, *pucBuffer++);\r
+\r
+ //\r
+ // Dummy read to drain the fifo and time the GPIO signal.\r
+ //\r
+ SSIDataGet(SSI0_BASE, &ulTemp);\r
+\r
+ //\r
+ // Decrement the BYTE counter.\r
+ //\r
+ ulCount--;\r
+ }\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! \internal\r
+//!\r
+//! Write a sequence of data bytes to the SSD0323 controller.\r
+//!\r
+//! The data is written in a polled fashion; this function will not return\r
+//! until the entire byte sequence has been written to the controller.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+static void\r
+OSRAMWriteData(const unsigned char *pucBuffer, unsigned long ulCount)\r
+{\r
+ unsigned long ulTemp;\r
+\r
+ //\r
+ // Return iff SSI port is not enabled for OSRAM.\r
+ //\r
+ if(!g_bSSIEnabled)\r
+ {\r
+ return;\r
+ }\r
+\r
+ //\r
+ // Set the command/control bit to enable data mode.\r
+ //\r
+ GPIOPinWrite(GPIO_PORTC_BASE, GPIO_PIN_7, GPIO_PIN_7);\r
+\r
+ //\r
+ // Loop while there are more bytes left to be transferred.\r
+ //\r
+ while(ulCount != 0)\r
+ {\r
+ //\r
+ // Write the next byte to the controller.\r
+ //\r
+ SSIDataPut(SSI0_BASE, *pucBuffer++);\r
+\r
+ //\r
+ // Dummy read to drain the fifo and time the GPIO signal.\r
+ //\r
+ SSIDataGet(SSI0_BASE, &ulTemp);\r
+\r
+ //\r
+ // Decrement the BYTE counter.\r
+ //\r
+ ulCount--;\r
+ }\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! Clears the OLED display.\r
+//!\r
+//! This function will clear the display RAM. All pixels in the display will\r
+//! be turned off.\r
+//!\r
+//! This function is contained in <tt>osram128x64x4.c</tt>, with\r
+//! <tt>osram128x64x4.h</tt> containing the API definition for use by\r
+//! applications.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+void\r
+OSRAM128x64x4Clear(void)\r
+{\r
+ static const unsigned char pucCommand1[] = { 0x15, 0, 63 };\r
+ static const unsigned char pucCommand2[] = { 0x75, 0, 79 };\r
+ unsigned long ulRow, ulColumn;\r
+ static unsigned char pucZeroBuffer[8] = { 0, 0, 0, 0, 0, 0, 0, 0};\r
+\r
+ //\r
+ // Set the window to fill the entire display.\r
+ //\r
+ OSRAMWriteCommand(pucCommand1, sizeof(pucCommand1));\r
+ OSRAMWriteCommand(pucCommand2, sizeof(pucCommand2));\r
+ OSRAMWriteCommand(g_pucOSRAM128x64x4VerticalInc,\r
+ sizeof(g_pucOSRAM128x64x4VerticalInc));\r
+\r
+ //\r
+ // In vertical address increment mode, loop through each column, filling\r
+ // each row with 0.\r
+ //\r
+ for(ulColumn = 0; ulColumn < (128/2); ulColumn++)\r
+ {\r
+ //\r
+ // 8 rows (bytes) per row of text.\r
+ //\r
+ for(ulRow = 0; ulRow < 80; ulRow += 8)\r
+ {\r
+ OSRAMWriteData(pucZeroBuffer, sizeof(pucZeroBuffer));\r
+ }\r
+ }\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! Displays a string on the OLED display.\r
+//!\r
+//! \param pcStr is a pointer to the string to display.\r
+//! \param ulX is the horizontal position to display the string, specified in\r
+//! columns from the left edge of the display.\r
+//! \param ulY is the vertical position to display the string, specified in\r
+//! rows from the top edge of the display.\r
+//! \param ucLevel is the 4-bit grey scale value to be used for displayed text.\r
+//!\r
+//! This function will draw a string on the display. Only the ASCII characters\r
+//! between 32 (space) and 126 (tilde) are supported; other characters will\r
+//! result in random data being draw on the display (based on whatever appears\r
+//! before/after the font in memory). The font is mono-spaced, so characters\r
+//! such as "i" and "l" have more white space around them than characters such\r
+//! as "m" or "w".\r
+//!\r
+//! If the drawing of the string reaches the right edge of the display, no more\r
+//! characters will be drawn. Therefore, special care is not required to avoid\r
+//! supplying a string that is "too long" to display.\r
+//!\r
+//! This function is contained in <tt>osram128x64x4.c</tt>, with\r
+//! <tt>osram128x64x4.h</tt> containing the API definition for use by\r
+//! applications.\r
+//!\r
+//! \note Because the OLED display packs 2 pixels of data in a single byte, the\r
+//! parameter \e ulX must be an even column number (e.g. 0, 2, 4, etc).\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+void\r
+OSRAM128x64x4StringDraw(const char *pcStr, unsigned long ulX,\r
+ unsigned long ulY, unsigned char ucLevel)\r
+{\r
+ static unsigned char pucBuffer[8];\r
+ unsigned long ulIdx1, ulIdx2;\r
+ unsigned char ucTemp;\r
+\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT(ulX < 128);\r
+ ASSERT((ulX & 1) == 0);\r
+ ASSERT(ulY < 64);\r
+ ASSERT(ucLevel < 16);\r
+\r
+ //\r
+ // Setup a window starting at the specified column and row, ending\r
+ // at the right edge of the display and 8 rows down (single character row).\r
+ //\r
+ pucBuffer[0] = 0x15;\r
+ pucBuffer[1] = ulX / 2;\r
+ pucBuffer[2] = 63;\r
+ OSRAMWriteCommand(pucBuffer, 3);\r
+ pucBuffer[0] = 0x75;\r
+ pucBuffer[1] = ulY;\r
+ pucBuffer[2] = ulY + 7;\r
+ OSRAMWriteCommand(pucBuffer, 3);\r
+ OSRAMWriteCommand(g_pucOSRAM128x64x4VerticalInc,\r
+ sizeof(g_pucOSRAM128x64x4VerticalInc));\r
+\r
+ //\r
+ // Loop while there are more characters in the string.\r
+ //\r
+ while(*pcStr != 0)\r
+ {\r
+ //\r
+ // Get a working copy of the current character and convert to an\r
+ // index into the character bit-map array.\r
+ //\r
+ ucTemp = *pcStr;\r
+ ucTemp &= 0x7F;\r
+ if(ucTemp < ' ')\r
+ {\r
+ ucTemp = ' ';\r
+ }\r
+ else\r
+ {\r
+ ucTemp -= ' ';\r
+ }\r
+\r
+ //\r
+ // Build and display the character buffer.\r
+ //\r
+ for(ulIdx1 = 0; ulIdx1 < 3; ulIdx1++)\r
+ {\r
+ //\r
+ // Convert two columns of 1-bit font data into a single data\r
+ // byte column of 4-bit font data.\r
+ //\r
+ for(ulIdx2 = 0; ulIdx2 < 8; ulIdx2++)\r
+ {\r
+ pucBuffer[ulIdx2] = 0;\r
+ if(g_pucFont[ucTemp][ulIdx1*2] & (1 << ulIdx2))\r
+ {\r
+ pucBuffer[ulIdx2] = ((ucLevel << 4) & 0xf0);\r
+ }\r
+ if((ulIdx1 < 2) &&\r
+ (g_pucFont[ucTemp][ulIdx1*2+1] & (1 << ulIdx2)))\r
+ {\r
+ pucBuffer[ulIdx2] |= ((ucLevel << 0) & 0x0f);\r
+ }\r
+ }\r
+\r
+ //\r
+ // If there is room, dump the single data byte column to the\r
+ // display. Otherwise, bail out.\r
+ //\r
+ if(ulX < 126)\r
+ {\r
+ OSRAMWriteData(pucBuffer, 8);\r
+ ulX += 2;\r
+ }\r
+ else\r
+ {\r
+ return;\r
+ }\r
+ }\r
+\r
+ //\r
+ // Advance to the next character.\r
+ //\r
+ pcStr++;\r
+ }\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! Displays an image on the OLED display.\r
+//!\r
+//! \param pucImage is a pointer to the image data.\r
+//! \param ulX is the horizontal position to display this image, specified in\r
+//! columns from the left edge of the display.\r
+//! \param ulY is the vertical position to display this image, specified in\r
+//! rows from the top of the display.\r
+//! \param ulWidth is the width of the image, specified in columns.\r
+//! \param ulHeight is the height of the image, specified in rows.\r
+//!\r
+//! This function will display a bitmap graphic on the display. Because of the\r
+//! format of the display RAM, the starting column (/e ulX) and the number of\r
+//! columns (/e ulWidth) must be an integer multiple of two.\r
+//!\r
+//! The image data is organized with the first row of image data appearing left\r
+//! to right, followed immediately by the second row of image data. Each byte\r
+//! contains the data for two columns in the current row, with the leftmost\r
+//! column being contained in bits 7:4 and the rightmost column being contained\r
+//! in bits 3:0.\r
+//!\r
+//! For example, an image six columns wide and seven scan lines tall would\r
+//! be arranged as follows (showing how the twenty one bytes of the image would\r
+//! appear on the display):\r
+//!\r
+//! \verbatim\r
+//! +-------------------+-------------------+-------------------+\r
+//! | Byte 0 | Byte 1 | Byte 2 |\r
+//! +---------+---------+---------+---------+---------+---------+\r
+//! | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 |\r
+//! +---------+---------+---------+---------+---------+---------+\r
+//! | Byte 3 | Byte 4 | Byte 5 |\r
+//! +---------+---------+---------+---------+---------+---------+\r
+//! | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 |\r
+//! +---------+---------+---------+---------+---------+---------+\r
+//! | Byte 6 | Byte 7 | Byte 8 |\r
+//! +---------+---------+---------+---------+---------+---------+\r
+//! | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 |\r
+//! +---------+---------+---------+---------+---------+---------+\r
+//! | Byte 9 | Byte 10 | Byte 11 |\r
+//! +---------+---------+---------+---------+---------+---------+\r
+//! | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 |\r
+//! +---------+---------+---------+---------+---------+---------+\r
+//! | Byte 12 | Byte 13 | Byte 14 |\r
+//! +---------+---------+---------+--3------+---------+---------+\r
+//! | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 |\r
+//! +---------+---------+---------+---------+---------+---------+\r
+//! | Byte 15 | Byte 16 | Byte 17 |\r
+//! +---------+---------+---------+---------+---------+---------+\r
+//! | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 |\r
+//! +---------+---------+---------+---------+---------+---------+\r
+//! | Byte 18 | Byte 19 | Byte 20 |\r
+//! +---------+---------+---------+---------+---------+---------+\r
+//! | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 |\r
+//! +---------+---------+---------+---------+---------+---------+\r
+//! \endverbatim\r
+//!\r
+//! This function is contained in <tt>osram128x64x4.c</tt>, with\r
+//! <tt>osram128x64x4.h</tt> containing the API definition for use by`\r
+//! applications.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+void\r
+OSRAM128x64x4ImageDraw(const unsigned char *pucImage, unsigned long ulX,\r
+ unsigned long ulY, unsigned long ulWidth,\r
+ unsigned long ulHeight)\r
+{\r
+ static unsigned char pucBuffer[8];\r
+\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT(ulX < 128);\r
+ ASSERT((ulX & 1) == 0);\r
+ ASSERT(ulY < 64);\r
+ ASSERT((ulX + ulWidth) <= 128);\r
+ ASSERT((ulY + ulHeight) <= 64);\r
+ ASSERT((ulWidth & 1) == 0);\r
+\r
+ //\r
+ // Setup a window starting at the specified column and row, and ending\r
+ // at the column + width and row+height.\r
+ //\r
+ pucBuffer[0] = 0x15;\r
+ pucBuffer[1] = ulX / 2;\r
+ pucBuffer[2] = (ulX + ulWidth - 2) / 2;\r
+ OSRAMWriteCommand(pucBuffer, 3);\r
+ pucBuffer[0] = 0x75;\r
+ pucBuffer[1] = ulY;\r
+ pucBuffer[2] = ulY + ulHeight - 1;\r
+ OSRAMWriteCommand(pucBuffer, 3);\r
+ OSRAMWriteCommand(g_pucOSRAM128x64x4HorizontalInc,\r
+ sizeof(g_pucOSRAM128x64x4HorizontalInc));\r
+\r
+ //\r
+ // Loop while there are more rows to display.\r
+ //\r
+ while(ulHeight--)\r
+ {\r
+ //\r
+ // Write this row of image data.\r
+ //\r
+ OSRAMWriteData(pucImage, (ulWidth / 2));\r
+\r
+ //\r
+ // Advance to the next row of the image.\r
+ //\r
+ pucImage += (ulWidth / 2);\r
+ }\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! Enable the SSI component of the OLED display driver.\r
+//!\r
+//! \param ulFrequency specifies the SSI Clock Frequency to be used.\r
+//!\r
+//! This function initializes the SSI interface to the OLED display.\r
+//!\r
+//! This function is contained in <tt>osram128x64x4.c</tt>, with\r
+//! <tt>osram128x64x4.h</tt> containing the API definition for use by\r
+//! applications.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+void\r
+OSRAM128x64x4Enable(unsigned long ulFrequency)\r
+{\r
+ unsigned long ulTemp;\r
+\r
+ //\r
+ // Disable the SSI port.\r
+ //\r
+ SSIDisable(SSI0_BASE);\r
+\r
+ //\r
+ // Configure the SSI0 port for master mode.\r
+ //\r
+ SSIConfig(SSI0_BASE, SSI_FRF_MOTO_MODE_2, SSI_MODE_MASTER, ulFrequency, 8);\r
+\r
+ //\r
+ // (Re)Enable SSI control of the FSS pin.\r
+ //\r
+ GPIOPinTypeSSI(GPIO_PORTA_BASE, GPIO_PIN_3);\r
+ GPIOPadConfigSet(GPIO_PORTA_BASE, GPIO_PIN_3, GPIO_STRENGTH_8MA,\r
+ GPIO_PIN_TYPE_STD_WPU);\r
+\r
+ //\r
+ // Enable the SSI port.\r
+ //\r
+ SSIEnable(SSI0_BASE);\r
+\r
+ //\r
+ // Drain the receive fifo.\r
+ //\r
+ while(SSIDataNonBlockingGet(SSI0_BASE, &ulTemp) != 0)\r
+ {\r
+ }\r
+\r
+ //\r
+ // Indicate that the OSRAM driver can use the SSI Port.\r
+ //\r
+ g_bSSIEnabled = true;\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! Enable the SSI component of the OLED display driver.\r
+//!\r
+//! \param ulFrequency specifies the SSI Clock Frequency to be used.\r
+//!\r
+//! This function initializes the SSI interface to the OLED display.\r
+//!\r
+//! This function is contained in <tt>osram128x64x4.c</tt>, with\r
+//! <tt>osram128x64x4.h</tt> containing the API definition for use by\r
+//! applications.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+void\r
+OSRAM128x64x4Disable(void)\r
+{\r
+ unsigned long ulTemp;\r
+\r
+ //\r
+ // Indicate that the OSRAM driver can no longer use the SSI Port.\r
+ //\r
+ g_bSSIEnabled = false;\r
+\r
+ //\r
+ // Drain the receive fifo.\r
+ //\r
+ while(SSIDataNonBlockingGet(SSI0_BASE, &ulTemp) != 0)\r
+ {\r
+ }\r
+\r
+ //\r
+ // Disable the SSI port.\r
+ //\r
+ SSIDisable(SSI0_BASE);\r
+\r
+ //\r
+ // Disable SSI control of the FSS pin.\r
+ //\r
+ GPIODirModeSet(GPIO_PORTA_BASE, GPIO_PIN_3, GPIO_DIR_MODE_OUT);\r
+ GPIOPadConfigSet(GPIO_PORTA_BASE, GPIO_PIN_3, GPIO_STRENGTH_8MA,\r
+ GPIO_PIN_TYPE_STD_WPU);\r
+ GPIOPinWrite(GPIO_PORTA_BASE, GPIO_PIN_3, GPIO_PIN_3);\r
+\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! Initialize the OLED display.\r
+//!\r
+//! \param ulFrequency specifies the SSI Clock Frequency to be used.\r
+//!\r
+//! This function initializes the SSI interface to the OLED display and\r
+//! configures the SSD0323 controller on the panel.\r
+//!\r
+//! This function is contained in <tt>osram128x64x4.c</tt>, with\r
+//! <tt>osram128x64x4.h</tt> containing the API definition for use by\r
+//! applications.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+void\r
+OSRAM128x64x4Init(unsigned long ulFrequency)\r
+{\r
+ unsigned long ulIdx;\r
+\r
+ //\r
+ // Enable the SSI0 and GPIO port blocks as they are needed by this driver.\r
+ //\r
+ SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI0);\r
+ SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA);\r
+ SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOC);\r
+\r
+ //\r
+ // Configure the SSI0CLK and SSIOTX pins for SSI operation.\r
+ //\r
+ GPIOPinTypeSSI(GPIO_PORTA_BASE, GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_5);\r
+ GPIOPadConfigSet(GPIO_PORTA_BASE, GPIO_PIN_2, GPIO_STRENGTH_8MA,\r
+ GPIO_PIN_TYPE_STD_WPU);\r
+ GPIOPadConfigSet(GPIO_PORTA_BASE, GPIO_PIN_3, GPIO_STRENGTH_8MA,\r
+ GPIO_PIN_TYPE_STD_WPU);\r
+ GPIOPadConfigSet(GPIO_PORTA_BASE, GPIO_PIN_5, GPIO_STRENGTH_8MA,\r
+ GPIO_PIN_TYPE_STD_WPU);\r
+\r
+ //\r
+ // Configure the PC7 pin as a D/Cn signal for OLED device.\r
+ //\r
+ GPIODirModeSet(GPIO_PORTC_BASE, GPIO_PIN_7, GPIO_DIR_MODE_OUT);\r
+ GPIOPadConfigSet(GPIO_PORTC_BASE, GPIO_PIN_7, GPIO_STRENGTH_8MA,\r
+ GPIO_PIN_TYPE_STD);\r
+ GPIOPinWrite(GPIO_PORTC_BASE, GPIO_PIN_7, GPIO_PIN_7);\r
+\r
+ //\r
+ // Configure and enable the SSI0 port for master mode.\r
+ //\r
+ OSRAM128x64x4Enable(ulFrequency);\r
+\r
+ //\r
+ // Clear the frame buffer.\r
+ //\r
+ OSRAM128x64x4Clear();\r
+\r
+ //\r
+ // Initialize the SSD0323 controller. Loop through the initialization\r
+ // sequence array, sending each command "string" to the controller.\r
+ //\r
+ for(ulIdx = 0; ulIdx < sizeof(g_pucOSRAM128x64x4Init);\r
+ ulIdx += g_pucOSRAM128x64x4Init[ulIdx] + 1)\r
+ {\r
+ //\r
+ // Send this command.\r
+ //\r
+ OSRAMWriteCommand(g_pucOSRAM128x64x4Init + ulIdx + 1,\r
+ g_pucOSRAM128x64x4Init[ulIdx] - 1);\r
+ }\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! Turns on the OLED display.\r
+//!\r
+//! This function will turn on the OLED display, causing it to display the\r
+//! contents of its internal frame buffer.\r
+//!\r
+//! This function is contained in <tt>osram128x64x4.c</tt>, with\r
+//! <tt>osram128x64x4.h</tt> containing the API definition for use by\r
+//! applications.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+void\r
+OSRAM128x64x4DisplayOn(void)\r
+{\r
+ unsigned long ulIdx;\r
+\r
+ //\r
+ // Initialize the SSD0323 controller. Loop through the initialization\r
+ // sequence array, sending each command "string" to the controller.\r
+ //\r
+ for(ulIdx = 0; ulIdx < sizeof(g_pucOSRAM128x64x4Init);\r
+ ulIdx += g_pucOSRAM128x64x4Init[ulIdx] + 1)\r
+ {\r
+ //\r
+ // Send this command.\r
+ //\r
+ OSRAMWriteCommand(g_pucOSRAM128x64x4Init + ulIdx + 1,\r
+ g_pucOSRAM128x64x4Init[ulIdx] - 1);\r
+ }\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! Turns off the OLED display.\r
+//!\r
+//! This function will turn off the OLED display. This will stop the scanning\r
+//! of the panel and turn off the on-chip DC-DC converter, preventing damage to\r
+//! the panel due to burn-in (it has similar characters to a CRT in this\r
+//! respect).\r
+//!\r
+//! This function is contained in <tt>osram128x64x4.c</tt>, with\r
+//! <tt>osram128x64x4.h</tt> containing the API definition for use by\r
+//! applications.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+void\r
+OSRAM128x64x4DisplayOff(void)\r
+{\r
+ static const unsigned char pucCommand1[] =\r
+ {\r
+ 0xAE, 0xAD, 0x02\r
+ };\r
+\r
+ //\r
+ // Turn off the DC-DC converter and the display.\r
+ //\r
+ OSRAMWriteCommand(pucCommand1, sizeof(pucCommand1));\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+// Close the Doxygen group.\r
+//! @}\r
+//\r
+//*****************************************************************************\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// osram128x64x4.h - Prototypes for the driver for the OSRAM 128x64x4 graphical\r
+// OLED display.\r
+//\r
+// Copyright (c) 2006-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __OSRAM128X64X4_H__\r
+#define __OSRAM128X64X4_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the driver APIs.\r
+//\r
+//*****************************************************************************\r
+extern void OSRAM128x64x4Clear(void);\r
+extern void OSRAM128x64x4StringDraw(const char *pcStr,\r
+ unsigned long ulX,\r
+ unsigned long ulY,\r
+ unsigned char ucLevel);\r
+extern void OSRAM128x64x4ImageDraw(const unsigned char *pucImage,\r
+ unsigned long ulX,\r
+ unsigned long ulY,\r
+ unsigned long ulWidth,\r
+ unsigned long ulHeight);\r
+extern void OSRAM128x64x4Init(unsigned long ulFrequency);\r
+extern void OSRAM128x64x4Enable(unsigned long ulFrequency);\r
+extern void OSRAM128x64x4Disable(void);\r
+extern void OSRAM128x64x4DisplayOn(void);\r
+extern void OSRAM128x64x4DisplayOff(void);\r
+\r
+//*****************************************************************************\r
+//\r
+// The following macro(s) map old names for the OSRAM functions to the new\r
+// names. In new code, the new names should be used in favor of the old names.\r
+//\r
+//*****************************************************************************\r
+#ifndef DEPRECATED\r
+#define OSRAM128x64x1InitSSI OSRAM128x64x4Enable\r
+#endif\r
+\r
+#endif // __OSRAM128X64X4_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// pwm.h - API function protoypes for Pulse Width Modulation (PWM) ports\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __PWM_H__\r
+#define __PWM_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// The following defines are passed to PWMGenConfigure() as the ulConfig\r
+// parameter and specify the configuration of the PWM generator.\r
+//\r
+//*****************************************************************************\r
+#define PWM_GEN_MODE_DOWN 0x00000000 // Down count mode\r
+#define PWM_GEN_MODE_UP_DOWN 0x00000002 // Up/Down count mode\r
+#define PWM_GEN_MODE_SYNC 0x00000038 // Synchronous updates\r
+#define PWM_GEN_MODE_NO_SYNC 0x00000000 // Immediate updates\r
+#define PWM_GEN_MODE_DBG_RUN 0x00000004 // Continue running in debug mode\r
+#define PWM_GEN_MODE_DBG_STOP 0x00000000 // Stop running in debug mode\r
+\r
+//*****************************************************************************\r
+//\r
+// Defines for enabling, disabling, and clearing PWM generator interrupts and\r
+// triggers.\r
+//\r
+//*****************************************************************************\r
+#define PWM_INT_CNT_ZERO 0x00000001 // Int if COUNT = 0\r
+#define PWM_INT_CNT_LOAD 0x00000002 // Int if COUNT = LOAD\r
+#define PWM_INT_CNT_AU 0x00000004 // Int if COUNT = CMPA U\r
+#define PWM_INT_CNT_AD 0x00000008 // Int if COUNT = CMPA D\r
+#define PWM_INT_CNT_BU 0x00000010 // Int if COUNT = CMPA U\r
+#define PWM_INT_CNT_BD 0x00000020 // Int if COUNT = CMPA D\r
+#define PWM_TR_CNT_ZERO 0x00000100 // Trig if COUNT = 0\r
+#define PWM_TR_CNT_LOAD 0x00000200 // Trig if COUNT = LOAD\r
+#define PWM_TR_CNT_AU 0x00000400 // Trig if COUNT = CMPA U\r
+#define PWM_TR_CNT_AD 0x00000800 // Trig if COUNT = CMPA D\r
+#define PWM_TR_CNT_BU 0x00001000 // Trig if COUNT = CMPA U\r
+#define PWM_TR_CNT_BD 0x00002000 // Trig if COUNT = CMPA D\r
+\r
+//*****************************************************************************\r
+//\r
+// Defines for enabling, disabling, and clearing PWM interrupts.\r
+//\r
+//*****************************************************************************\r
+#define PWM_INT_GEN_0 0x00000001 // Generator 0 interrupt\r
+#define PWM_INT_GEN_1 0x00000002 // Generator 1 interrupt\r
+#define PWM_INT_GEN_2 0x00000004 // Generator 2 interrupt\r
+#define PWM_INT_FAULT 0x00010000 // Fault interrupt\r
+\r
+//*****************************************************************************\r
+//\r
+// Defines to identify the generators within a module.\r
+//\r
+//*****************************************************************************\r
+#define PWM_GEN_0 0x00000040 // Offset address of Gen0\r
+#define PWM_GEN_1 0x00000080 // Offset address of Gen1\r
+#define PWM_GEN_2 0x000000C0 // Offset address of Gen2\r
+\r
+#define PWM_GEN_0_BIT 0x00000001 // Bit-wise ID for Gen0\r
+#define PWM_GEN_1_BIT 0x00000002 // Bit-wise ID for Gen1\r
+#define PWM_GEN_2_BIT 0x00000004 // Bit-wise ID for Gen2\r
+\r
+//*****************************************************************************\r
+//\r
+// Defines to identify the outputs within a module.\r
+//\r
+//*****************************************************************************\r
+#define PWM_OUT_0 0x00000040 // Encoded offset address of PWM0\r
+#define PWM_OUT_1 0x00000041 // Encoded offset address of PWM1\r
+#define PWM_OUT_2 0x00000082 // Encoded offset address of PWM2\r
+#define PWM_OUT_3 0x00000083 // Encoded offset address of PWM3\r
+#define PWM_OUT_4 0x000000C4 // Encoded offset address of PWM4\r
+#define PWM_OUT_5 0x000000C5 // Encoded offset address of PWM5\r
+\r
+#define PWM_OUT_0_BIT 0x00000001 // Bit-wise ID for PWM0\r
+#define PWM_OUT_1_BIT 0x00000002 // Bit-wise ID for PWM1\r
+#define PWM_OUT_2_BIT 0x00000004 // Bit-wise ID for PWM2\r
+#define PWM_OUT_3_BIT 0x00000008 // Bit-wise ID for PWM3\r
+#define PWM_OUT_4_BIT 0x00000010 // Bit-wise ID for PWM4\r
+#define PWM_OUT_5_BIT 0x00000020 // Bit-wise ID for PWM5\r
+\r
+//*****************************************************************************\r
+//\r
+// API Function prototypes\r
+//\r
+//*****************************************************************************\r
+extern void PWMGenConfigure(unsigned long ulBase, unsigned long ulGen,\r
+ unsigned long ulConfig);\r
+extern void PWMGenPeriodSet(unsigned long ulBase, unsigned long ulGen,\r
+ unsigned long ulPeriod);\r
+extern unsigned long PWMGenPeriodGet(unsigned long ulBase,\r
+ unsigned long ulGen);\r
+extern void PWMGenEnable(unsigned long ulBase, unsigned long ulGen);\r
+extern void PWMGenDisable(unsigned long ulBase, unsigned long ulGen);\r
+extern void PWMPulseWidthSet(unsigned long ulBase, unsigned long ulPWMOut,\r
+ unsigned long ulWidth);\r
+extern unsigned long PWMPulseWidthGet(unsigned long ulBase,\r
+ unsigned long ulPWMOut);\r
+extern void PWMDeadBandEnable(unsigned long ulBase, unsigned long ulGen,\r
+ unsigned short usRise, unsigned short usFall);\r
+extern void PWMDeadBandDisable(unsigned long ulBase, unsigned long ulGen);\r
+extern void PWMSyncUpdate(unsigned long ulBase, unsigned long ulGenBits);\r
+extern void PWMSyncTimeBase(unsigned long ulBase, unsigned long ulGenBits);\r
+extern void PWMOutputState(unsigned long ulBase, unsigned long ulPWMOutBits,\r
+ tBoolean bEnable);\r
+extern void PWMOutputInvert(unsigned long ulBase, unsigned long ulPWMOutBits,\r
+ tBoolean bInvert);\r
+extern void PWMOutputFault(unsigned long ulBase, unsigned long ulPWMOutBits,\r
+ tBoolean bFaultKill);\r
+extern void PWMGenIntRegister(unsigned long ulBase, unsigned long ulGen,\r
+ void (*pfnIntHandler)(void));\r
+extern void PWMGenIntUnregister(unsigned long ulBase, unsigned long ulGen);\r
+extern void PWMFaultIntRegister(unsigned long ulBase,\r
+ void (*pfnIntHandler)(void));\r
+extern void PWMFaultIntUnregister(unsigned long ulBase);\r
+extern void PWMGenIntTrigEnable(unsigned long ulBase, unsigned long ulGen,\r
+ unsigned long ulIntTrig);\r
+extern void PWMGenIntTrigDisable(unsigned long ulBase, unsigned long ulGen,\r
+ unsigned long ulIntTrig);\r
+extern unsigned long PWMGenIntStatus(unsigned long ulBase, unsigned long ulGen,\r
+ tBoolean bMasked);\r
+extern void PWMGenIntClear(unsigned long ulBase, unsigned long ulGen,\r
+ unsigned long ulInts);\r
+extern void PWMIntEnable(unsigned long ulBase, unsigned long ulGenFault);\r
+extern void PWMIntDisable(unsigned long ulBase, unsigned long ulGenFault);\r
+extern void PWMFaultIntClear(unsigned long ulBase);\r
+extern unsigned long PWMIntStatus(unsigned long ulBase, tBoolean bMasked);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __PWM_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// qei.h - Prototypes for the Quadrature Encoder Driver.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __QEI_H__\r
+#define __QEI_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to QEIConfigure as the ulConfig paramater.\r
+//\r
+//*****************************************************************************\r
+#define QEI_CONFIG_CAPTURE_A 0x00000000 // Count on ChA edges only\r
+#define QEI_CONFIG_CAPTURE_A_B 0x00000008 // Count on ChA and ChB edges\r
+#define QEI_CONFIG_NO_RESET 0x00000000 // Do not reset on index pulse\r
+#define QEI_CONFIG_RESET_IDX 0x00000010 // Reset position on index pulse\r
+#define QEI_CONFIG_QUADRATURE 0x00000000 // ChA and ChB are quadrature\r
+#define QEI_CONFIG_CLOCK_DIR 0x00000004 // ChA and ChB are clock and dir\r
+#define QEI_CONFIG_NO_SWAP 0x00000000 // Do not swap ChA and ChB\r
+#define QEI_CONFIG_SWAP 0x00000002 // Swap ChA and ChB\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to QEIVelocityConfigure as the ulPreDiv parameter.\r
+//\r
+//*****************************************************************************\r
+#define QEI_VELDIV_1 0x00000000 // Predivide by 1\r
+#define QEI_VELDIV_2 0x00000040 // Predivide by 2\r
+#define QEI_VELDIV_4 0x00000080 // Predivide by 4\r
+#define QEI_VELDIV_8 0x000000C0 // Predivide by 8\r
+#define QEI_VELDIV_16 0x00000100 // Predivide by 16\r
+#define QEI_VELDIV_32 0x00000140 // Predivide by 32\r
+#define QEI_VELDIV_64 0x00000180 // Predivide by 64\r
+#define QEI_VELDIV_128 0x000001C0 // Predivide by 128\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to QEIEnableInts, QEIDisableInts, and QEIClearInts\r
+// as the ulIntFlags parameter, and returned by QEIGetIntStatus.\r
+//\r
+//*****************************************************************************\r
+#define QEI_INTERROR 0x00000008 // Phase error detected\r
+#define QEI_INTDIR 0x00000004 // Direction change\r
+#define QEI_INTTIMER 0x00000002 // Velocity timer expired\r
+#define QEI_INTINDEX 0x00000001 // Index pulse detected\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+extern void QEIEnable(unsigned long ulBase);\r
+extern void QEIDisable(unsigned long ulBase);\r
+extern void QEIConfigure(unsigned long ulBase, unsigned long ulConfig,\r
+ unsigned long ulMaxPosition);\r
+extern unsigned long QEIPositionGet(unsigned long ulBase);\r
+extern void QEIPositionSet(unsigned long ulBase, unsigned long ulPosition);\r
+extern long QEIDirectionGet(unsigned long ulBase);\r
+extern tBoolean QEIErrorGet(unsigned long ulBase);\r
+extern void QEIVelocityEnable(unsigned long ulBase);\r
+extern void QEIVelocityDisable(unsigned long ulBase);\r
+extern void QEIVelocityConfigure(unsigned long ulBase, unsigned long ulPreDiv,\r
+ unsigned long ulPeriod);\r
+extern unsigned long QEIVelocityGet(unsigned long ulBase);\r
+extern void QEIIntRegister(unsigned long ulBase, void (*pfnHandler)(void));\r
+extern void QEIIntUnregister(unsigned long ulBase);\r
+extern void QEIIntEnable(unsigned long ulBase, unsigned long ulIntFlags);\r
+extern void QEIIntDisable(unsigned long ulBase, unsigned long ulIntFlags);\r
+extern unsigned long QEIIntStatus(unsigned long ulBase, tBoolean bMasked);\r
+extern void QEIIntClear(unsigned long ulBase, unsigned long ulIntFlags);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __QEI_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// ssi.h - Prototypes for the Synchronous Serial Interface Driver.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __SSI_H__\r
+#define __SSI_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to SSIIntEnable, SSIIntDisable, and SSIIntClear\r
+// as the ulIntFlags parameter, and returned by SSIIntStatus.\r
+//\r
+//*****************************************************************************\r
+#define SSI_TXFF 0x00000008 // TX FIFO half empty or less\r
+#define SSI_RXFF 0x00000004 // RX FIFO half full or less\r
+#define SSI_RXTO 0x00000002 // RX timeout\r
+#define SSI_RXOR 0x00000001 // RX overrun\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to SSIConfig.\r
+//\r
+//*****************************************************************************\r
+#define SSI_FRF_MOTO_MODE_0 0x00000000 // Moto fmt, polarity 0, phase 0\r
+#define SSI_FRF_MOTO_MODE_1 0x00000002 // Moto fmt, polarity 0, phase 1\r
+#define SSI_FRF_MOTO_MODE_2 0x00000001 // Moto fmt, polarity 1, phase 0\r
+#define SSI_FRF_MOTO_MODE_3 0x00000003 // Moto fmt, polarity 1, phase 1\r
+#define SSI_FRF_TI 0x00000010 // TI frame format\r
+#define SSI_FRF_NMW 0x00000020 // National MicroWire frame format\r
+\r
+#define SSI_MODE_MASTER 0x00000000 // SSI master\r
+#define SSI_MODE_SLAVE 0x00000001 // SSI slave\r
+#define SSI_MODE_SLAVE_OD 0x00000002 // SSI slave with output disabled\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+extern void SSIConfig(unsigned long ulBase, unsigned long ulProtocol,\r
+ unsigned long ulMode, unsigned long ulBitRate,\r
+ unsigned long ulDataWidth);\r
+extern void SSIDataGet(unsigned long ulBase, unsigned long *pulData);\r
+extern long SSIDataNonBlockingGet(unsigned long ulBase,\r
+ unsigned long *pulData);\r
+extern void SSIDataPut(unsigned long ulBase, unsigned long ulData);\r
+extern long SSIDataNonBlockingPut(unsigned long ulBase, unsigned long ulData);\r
+extern void SSIDisable(unsigned long ulBase);\r
+extern void SSIEnable(unsigned long ulBase);\r
+extern void SSIIntClear(unsigned long ulBase, unsigned long ulIntFlags);\r
+extern void SSIIntDisable(unsigned long ulBase, unsigned long ulIntFlags);\r
+extern void SSIIntEnable(unsigned long ulBase, unsigned long ulIntFlags);\r
+extern void SSIIntRegister(unsigned long ulBase, void(*pfnHandler)(void));\r
+extern unsigned long SSIIntStatus(unsigned long ulBase, tBoolean bMasked);\r
+extern void SSIIntUnregister(unsigned long ulBase);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __SSI_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// sysctl.h - Prototypes for the system control driver.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __SYSCTL_H__\r
+#define __SYSCTL_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the\r
+// SysCtlPeripheralPresent(), SysCtlPeripheralEnable(),\r
+// SysCtlPeripheralDisable(), and SysCtlPeripheralReset() APIs as the\r
+// ulPeripheral parameter. The peripherals in the fourth group (upper nibble\r
+// is 3) can only be used with the SysCtlPeripheralPresent() API.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_PERIPH_PWM 0x00100010 // PWM\r
+#define SYSCTL_PERIPH_ADC 0x00100001 // ADC\r
+#define SYSCTL_PERIPH_HIBERNATE 0x00000040 // Hibernation module\r
+#define SYSCTL_PERIPH_WDOG 0x00000008 // Watchdog\r
+#define SYSCTL_PERIPH_CAN0 0x00100100 // CAN 0\r
+#define SYSCTL_PERIPH_CAN1 0x00100200 // CAN 1\r
+#define SYSCTL_PERIPH_UART0 0x10000001 // UART 0\r
+#define SYSCTL_PERIPH_UART1 0x10000002 // UART 1\r
+#define SYSCTL_PERIPH_UART2 0x10000004 // UART 2\r
+#define SYSCTL_PERIPH_SSI 0x10000010 // SSI\r
+#define SYSCTL_PERIPH_SSI0 0x10000010 // SSI 0\r
+#define SYSCTL_PERIPH_SSI1 0x10000020 // SSI 1\r
+#define SYSCTL_PERIPH_QEI 0x10000100 // QEI\r
+#define SYSCTL_PERIPH_QEI0 0x10000100 // QEI 0\r
+#define SYSCTL_PERIPH_QEI1 0x10000200 // QEI 1\r
+#define SYSCTL_PERIPH_I2C 0x10001000 // I2C\r
+#define SYSCTL_PERIPH_I2C0 0x10001000 // I2C 0\r
+#define SYSCTL_PERIPH_I2C1 0x10004000 // I2C 1\r
+#define SYSCTL_PERIPH_TIMER0 0x10100001 // Timer 0\r
+#define SYSCTL_PERIPH_TIMER1 0x10100002 // Timer 1\r
+#define SYSCTL_PERIPH_TIMER2 0x10100004 // Timer 2\r
+#define SYSCTL_PERIPH_TIMER3 0x10100008 // Timer 3\r
+#define SYSCTL_PERIPH_COMP0 0x10100100 // Analog comparator 0\r
+#define SYSCTL_PERIPH_COMP1 0x10100200 // Analog comparator 1\r
+#define SYSCTL_PERIPH_COMP2 0x10100400 // Analog comparator 2\r
+#define SYSCTL_PERIPH_GPIOA 0x20000001 // GPIO A\r
+#define SYSCTL_PERIPH_GPIOB 0x20000002 // GPIO B\r
+#define SYSCTL_PERIPH_GPIOC 0x20000004 // GPIO C\r
+#define SYSCTL_PERIPH_GPIOD 0x20000008 // GPIO D\r
+#define SYSCTL_PERIPH_GPIOE 0x20000010 // GPIO E\r
+#define SYSCTL_PERIPH_GPIOF 0x20000020 // GPIO F\r
+#define SYSCTL_PERIPH_GPIOG 0x20000040 // GPIO G\r
+#define SYSCTL_PERIPH_GPIOH 0x20000080 // GPIO H\r
+#define SYSCTL_PERIPH_ETH 0x20105000 // ETH\r
+#define SYSCTL_PERIPH_MPU 0x30000080 // Cortex M3 MPU\r
+#define SYSCTL_PERIPH_TEMP 0x30000020 // Temperature sensor\r
+#define SYSCTL_PERIPH_PLL 0x30000010 // PLL\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the SysCtlPinPresent() API\r
+// as the ulPin parameter.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_PIN_PWM0 0x00000001 // PWM0 pin\r
+#define SYSCTL_PIN_PWM1 0x00000002 // PWM1 pin\r
+#define SYSCTL_PIN_PWM2 0x00000004 // PWM2 pin\r
+#define SYSCTL_PIN_PWM3 0x00000008 // PWM3 pin\r
+#define SYSCTL_PIN_PWM4 0x00000010 // PWM4 pin\r
+#define SYSCTL_PIN_PWM5 0x00000020 // PWM5 pin\r
+#define SYSCTL_PIN_C0MINUS 0x00000040 // C0- pin\r
+#define SYSCTL_PIN_C0PLUS 0x00000080 // C0+ pin\r
+#define SYSCTL_PIN_C0O 0x00000100 // C0o pin\r
+#define SYSCTL_PIN_C1MINUS 0x00000200 // C1- pin\r
+#define SYSCTL_PIN_C1PLUS 0x00000400 // C1+ pin\r
+#define SYSCTL_PIN_C1O 0x00000800 // C1o pin\r
+#define SYSCTL_PIN_C2MINUS 0x00001000 // C2- pin\r
+#define SYSCTL_PIN_C2PLUS 0x00002000 // C2+ pin\r
+#define SYSCTL_PIN_C2O 0x00004000 // C2o pin\r
+#define SYSCTL_PIN_MC_FAULT0 0x00008000 // MC0 Fault pin\r
+#define SYSCTL_PIN_ADC0 0x00010000 // ADC0 pin\r
+#define SYSCTL_PIN_ADC1 0x00020000 // ADC1 pin\r
+#define SYSCTL_PIN_ADC2 0x00040000 // ADC2 pin\r
+#define SYSCTL_PIN_ADC3 0x00080000 // ADC3 pin\r
+#define SYSCTL_PIN_ADC4 0x00100000 // ADC4 pin\r
+#define SYSCTL_PIN_ADC5 0x00200000 // ADC5 pin\r
+#define SYSCTL_PIN_ADC6 0x00400000 // ADC6 pin\r
+#define SYSCTL_PIN_ADC7 0x00800000 // ADC7 pin\r
+#define SYSCTL_PIN_CCP0 0x01000000 // CCP0 pin\r
+#define SYSCTL_PIN_CCP1 0x02000000 // CCP1 pin\r
+#define SYSCTL_PIN_CCP2 0x04000000 // CCP2 pin\r
+#define SYSCTL_PIN_CCP3 0x08000000 // CCP3 pin\r
+#define SYSCTL_PIN_CCP4 0x10000000 // CCP4 pin\r
+#define SYSCTL_PIN_CCP5 0x20000000 // CCP5 pin\r
+#define SYSCTL_PIN_32KHZ 0x80000000 // 32kHz pin\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the SysCtlLDOSet() API as\r
+// the ulVoltage value, or returned by the SysCtlLDOGet() API.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_LDO_2_25V 0x00000005 // LDO output of 2.25V\r
+#define SYSCTL_LDO_2_30V 0x00000004 // LDO output of 2.30V\r
+#define SYSCTL_LDO_2_35V 0x00000003 // LDO output of 2.35V\r
+#define SYSCTL_LDO_2_40V 0x00000002 // LDO output of 2.40V\r
+#define SYSCTL_LDO_2_45V 0x00000001 // LDO output of 2.45V\r
+#define SYSCTL_LDO_2_50V 0x00000000 // LDO output of 2.50V\r
+#define SYSCTL_LDO_2_55V 0x0000001f // LDO output of 2.55V\r
+#define SYSCTL_LDO_2_60V 0x0000001e // LDO output of 2.60V\r
+#define SYSCTL_LDO_2_65V 0x0000001d // LDO output of 2.65V\r
+#define SYSCTL_LDO_2_70V 0x0000001c // LDO output of 2.70V\r
+#define SYSCTL_LDO_2_75V 0x0000001b // LDO output of 2.75V\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the SysCtlLDOConfigSet() API.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_LDOCFG_ARST 0x00000001 // Allow LDO failure to reset\r
+#define SYSCTL_LDOCFG_NORST 0x00000000 // Do not reset on LDO failure\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the SysCtlIntEnable(),\r
+// SysCtlIntDisable(), and SysCtlIntClear() APIs, or returned in the bit mask\r
+// by the SysCtlIntStatus() API.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_INT_PLL_LOCK 0x00000040 // PLL lock interrupt\r
+#define SYSCTL_INT_CUR_LIMIT 0x00000020 // Current limit interrupt\r
+#define SYSCTL_INT_IOSC_FAIL 0x00000010 // Internal oscillator failure int\r
+#define SYSCTL_INT_MOSC_FAIL 0x00000008 // Main oscillator failure int\r
+#define SYSCTL_INT_POR 0x00000004 // Power on reset interrupt\r
+#define SYSCTL_INT_BOR 0x00000002 // Brown out interrupt\r
+#define SYSCTL_INT_PLL_FAIL 0x00000001 // PLL failure interrupt\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the SysCtlResetCauseClear()\r
+// API or returned by the SysCtlResetCauseGet() API.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_CAUSE_LDO 0x00000020 // LDO power not OK reset\r
+#define SYSCTL_CAUSE_SW 0x00000010 // Software reset\r
+#define SYSCTL_CAUSE_WDOG 0x00000008 // Watchdog reset\r
+#define SYSCTL_CAUSE_BOR 0x00000004 // Brown-out reset\r
+#define SYSCTL_CAUSE_POR 0x00000002 // Power on reset\r
+#define SYSCTL_CAUSE_EXT 0x00000001 // External reset\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the SysCtlBrownOutConfigSet()\r
+// API as the ulConfig parameter.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_BOR_RESET 0x00000002 // Reset instead of interrupting\r
+#define SYSCTL_BOR_RESAMPLE 0x00000001 // Resample BOR before asserting\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the SysCtlPWMClockSet() API\r
+// as the ulConfig parameter, and can be returned by the SysCtlPWMClockGet()\r
+// API.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_PWMDIV_1 0x00000000 // PWM clock is processor clock /1\r
+#define SYSCTL_PWMDIV_2 0x00100000 // PWM clock is processor clock /2\r
+#define SYSCTL_PWMDIV_4 0x00120000 // PWM clock is processor clock /4\r
+#define SYSCTL_PWMDIV_8 0x00140000 // PWM clock is processor clock /8\r
+#define SYSCTL_PWMDIV_16 0x00160000 // PWM clock is processor clock /16\r
+#define SYSCTL_PWMDIV_32 0x00180000 // PWM clock is processor clock /32\r
+#define SYSCTL_PWMDIV_64 0x001A0000 // PWM clock is processor clock /64\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the SysCtlADCSpeedSet() API\r
+// as the ulSpeed parameter, and can be returned by the SyCtlADCSpeedGet()\r
+// API.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_ADCSPEED_1MSPS 0x00000300 // 1,000,000 samples per second\r
+#define SYSCTL_ADCSPEED_500KSPS 0x00000200 // 500,000 samples per second\r
+#define SYSCTL_ADCSPEED_250KSPS 0x00000100 // 250,000 samples per second\r
+#define SYSCTL_ADCSPEED_125KSPS 0x00000000 // 125,000 samples per second\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the SysCtlClockSet() API as\r
+// the ulConfig parameter.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_SYSDIV_1 0x07800000 // Processor clock is osc/pll /1\r
+#define SYSCTL_SYSDIV_2 0x00C00000 // Processor clock is osc/pll /2\r
+#define SYSCTL_SYSDIV_3 0x01400000 // Processor clock is osc/pll /3\r
+#define SYSCTL_SYSDIV_4 0x01C00000 // Processor clock is osc/pll /4\r
+#define SYSCTL_SYSDIV_5 0x02400000 // Processor clock is osc/pll /5\r
+#define SYSCTL_SYSDIV_6 0x02C00000 // Processor clock is osc/pll /6\r
+#define SYSCTL_SYSDIV_7 0x03400000 // Processor clock is osc/pll /7\r
+#define SYSCTL_SYSDIV_8 0x03C00000 // Processor clock is osc/pll /8\r
+#define SYSCTL_SYSDIV_9 0x04400000 // Processor clock is osc/pll /9\r
+#define SYSCTL_SYSDIV_10 0x04C00000 // Processor clock is osc/pll /10\r
+#define SYSCTL_SYSDIV_11 0x05400000 // Processor clock is osc/pll /11\r
+#define SYSCTL_SYSDIV_12 0x05C00000 // Processor clock is osc/pll /12\r
+#define SYSCTL_SYSDIV_13 0x06400000 // Processor clock is osc/pll /13\r
+#define SYSCTL_SYSDIV_14 0x06C00000 // Processor clock is osc/pll /14\r
+#define SYSCTL_SYSDIV_15 0x07400000 // Processor clock is osc/pll /15\r
+#define SYSCTL_SYSDIV_16 0x07C00000 // Processor clock is osc/pll /16\r
+#define SYSCTL_USE_PLL 0x00000000 // System clock is the PLL clock\r
+#define SYSCTL_USE_OSC 0x00003800 // System clock is the osc clock\r
+#define SYSCTL_XTAL_3_57MHZ 0x00000100 // External crystal is 3.579545MHz\r
+#define SYSCTL_XTAL_3_68MHZ 0x00000140 // External crystal is 3.6864MHz\r
+#define SYSCTL_XTAL_4MHZ 0x00000180 // External crystal is 4MHz\r
+#define SYSCTL_XTAL_4_09MHZ 0x000001C0 // External crystal is 4.096MHz\r
+#define SYSCTL_XTAL_4_91MHZ 0x00000200 // External crystal is 4.9152MHz\r
+#define SYSCTL_XTAL_5MHZ 0x00000240 // External crystal is 5MHz\r
+#define SYSCTL_XTAL_5_12MHZ 0x00000280 // External crystal is 5.12MHz\r
+#define SYSCTL_XTAL_6MHZ 0x000002C0 // External crystal is 6MHz\r
+#define SYSCTL_XTAL_6_14MHZ 0x00000300 // External crystal is 6.144MHz\r
+#define SYSCTL_XTAL_7_37MHZ 0x00000340 // External crystal is 7.3728MHz\r
+#define SYSCTL_XTAL_8MHZ 0x00000380 // External crystal is 8MHz\r
+#define SYSCTL_XTAL_8_19MHZ 0x000003C0 // External crystal is 8.192MHz\r
+#define SYSCTL_OSC_MAIN 0x00000000 // Oscillator source is main osc\r
+#define SYSCTL_OSC_INT 0x00000010 // Oscillator source is int. osc\r
+#define SYSCTL_OSC_INT4 0x00000020 // Oscillator source is int. osc /4\r
+#define SYSCTL_INT_OSC_DIS 0x00000002 // Disable internal oscillator\r
+#define SYSCTL_MAIN_OSC_DIS 0x00000001 // Disable main oscillator\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+extern unsigned long SysCtlSRAMSizeGet(void);\r
+extern unsigned long SysCtlFlashSizeGet(void);\r
+extern tBoolean SysCtlPinPresent(unsigned long ulPin);\r
+extern tBoolean SysCtlPeripheralPresent(unsigned long ulPeripheral);\r
+extern void SysCtlPeripheralReset(unsigned long ulPeripheral);\r
+extern void SysCtlPeripheralEnable(unsigned long ulPeripheral);\r
+extern void SysCtlPeripheralDisable(unsigned long ulPeripheral);\r
+extern void SysCtlPeripheralSleepEnable(unsigned long ulPeripheral);\r
+extern void SysCtlPeripheralSleepDisable(unsigned long ulPeripheral);\r
+extern void SysCtlPeripheralDeepSleepEnable(unsigned long ulPeripheral);\r
+extern void SysCtlPeripheralDeepSleepDisable(unsigned long ulPeripheral);\r
+extern void SysCtlPeripheralClockGating(tBoolean bEnable);\r
+extern void SysCtlIntRegister(void (*pfnHandler)(void));\r
+extern void SysCtlIntUnregister(void);\r
+extern void SysCtlIntEnable(unsigned long ulInts);\r
+extern void SysCtlIntDisable(unsigned long ulInts);\r
+extern void SysCtlIntClear(unsigned long ulInts);\r
+extern unsigned long SysCtlIntStatus(tBoolean bMasked);\r
+extern void SysCtlLDOSet(unsigned long ulVoltage);\r
+extern unsigned long SysCtlLDOGet(void);\r
+extern void SysCtlLDOConfigSet(unsigned long ulConfig);\r
+extern void SysCtlReset(void);\r
+extern void SysCtlSleep(void);\r
+extern void SysCtlDeepSleep(void);\r
+extern unsigned long SysCtlResetCauseGet(void);\r
+extern void SysCtlResetCauseClear(unsigned long ulCauses);\r
+extern void SysCtlBrownOutConfigSet(unsigned long ulConfig,\r
+ unsigned long ulDelay);\r
+extern void SysCtlClockSet(unsigned long ulConfig);\r
+extern unsigned long SysCtlClockGet(void);\r
+extern void SysCtlPWMClockSet(unsigned long ulConfig);\r
+extern unsigned long SysCtlPWMClockGet(void);\r
+extern void SysCtlADCSpeedSet(unsigned long ulSpeed);\r
+extern unsigned long SysCtlADCSpeedGet(void);\r
+extern void SysCtlIOSCVerificationSet(tBoolean bEnable);\r
+extern void SysCtlMOSCVerificationSet(tBoolean bEnable);\r
+extern void SysCtlPLLVerificationSet(tBoolean bEnable);\r
+extern void SysCtlClkVerificationClear(void);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __SYSCTL_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// systick.h - Prototypes for the SysTick driver.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __SYSTICK_H__\r
+#define __SYSTICK_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+extern void SysTickEnable(void);\r
+extern void SysTickDisable(void);\r
+extern void SysTickIntRegister(void (*pfnHandler)(void));\r
+extern void SysTickIntUnregister(void);\r
+extern void SysTickIntEnable(void);\r
+extern void SysTickIntDisable(void);\r
+extern void SysTickPeriodSet(unsigned long ulPeriod);\r
+extern unsigned long SysTickPeriodGet(void);\r
+extern unsigned long SysTickValueGet(void);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __SYSTICK_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// uart.h - Defines and Macros for the UART.\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __UART_H__\r
+#define __UART_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to UARTIntEnable, UARTIntDisable, and UARTIntClear\r
+// as the ulIntFlags parameter, and returned from UARTIntStatus.\r
+//\r
+//*****************************************************************************\r
+#define UART_INT_OE 0x400 // Overrun Error Interrupt Mask\r
+#define UART_INT_BE 0x200 // Break Error Interrupt Mask\r
+#define UART_INT_PE 0x100 // Parity Error Interrupt Mask\r
+#define UART_INT_FE 0x080 // Framing Error Interrupt Mask\r
+#define UART_INT_RT 0x040 // Receive Timeout Interrupt Mask\r
+#define UART_INT_TX 0x020 // Transmit Interrupt Mask\r
+#define UART_INT_RX 0x010 // Receive Interrupt Mask\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to UARTConfigSet as the ulConfig parameter and\r
+// returned by UARTConfigGet in the pulConfig parameter. Additionally, the\r
+// UART_CONFIG_PAR_* subset can be passed to UARTParityModeSet as the ulParity\r
+// parameter, and are returned by UARTParityModeGet.\r
+//\r
+//*****************************************************************************\r
+#define UART_CONFIG_WLEN_8 0x00000060 // 8 bit data\r
+#define UART_CONFIG_WLEN_7 0x00000040 // 7 bit data\r
+#define UART_CONFIG_WLEN_6 0x00000020 // 6 bit data\r
+#define UART_CONFIG_WLEN_5 0x00000000 // 5 bit data\r
+#define UART_CONFIG_STOP_ONE 0x00000000 // One stop bit\r
+#define UART_CONFIG_STOP_TWO 0x00000008 // Two stop bits\r
+#define UART_CONFIG_PAR_NONE 0x00000000 // No parity\r
+#define UART_CONFIG_PAR_EVEN 0x00000006 // Even parity\r
+#define UART_CONFIG_PAR_ODD 0x00000002 // Odd parity\r
+#define UART_CONFIG_PAR_ONE 0x00000086 // Parity bit is one\r
+#define UART_CONFIG_PAR_ZERO 0x00000082 // Parity bit is zero\r
+\r
+//*****************************************************************************\r
+//\r
+// API Function prototypes\r
+//\r
+//*****************************************************************************\r
+extern void UARTParityModeSet(unsigned long ulBase, unsigned long ulParity);\r
+extern unsigned long UARTParityModeGet(unsigned long ulBase);\r
+extern void UARTConfigSet(unsigned long ulBase, unsigned long ulBaud,\r
+ unsigned long ulConfig);\r
+extern void UARTConfigGet(unsigned long ulBase, unsigned long *pulBaud,\r
+ unsigned long *pulConfig);\r
+extern void UARTEnable(unsigned long ulBase);\r
+extern void UARTDisable(unsigned long ulBase);\r
+extern void UARTEnableSIR(unsigned long ulBase, tBoolean bLowPower);\r
+extern void UARTDisableSIR(unsigned long ulBase);\r
+extern tBoolean UARTCharsAvail(unsigned long ulBase);\r
+extern tBoolean UARTSpaceAvail(unsigned long ulBase);\r
+extern long UARTCharNonBlockingGet(unsigned long ulBase);\r
+extern long UARTCharGet(unsigned long ulBase);\r
+extern tBoolean UARTCharNonBlockingPut(unsigned long ulBase,\r
+ unsigned char ucData);\r
+extern void UARTCharPut(unsigned long ulBase, unsigned char ucData);\r
+extern void UARTBreakCtl(unsigned long ulBase, tBoolean bBreakState);\r
+extern void UARTIntRegister(unsigned long ulBase, void(*pfnHandler)(void));\r
+extern void UARTIntUnregister(unsigned long ulBase);\r
+extern void UARTIntEnable(unsigned long ulBase, unsigned long ulIntFlags);\r
+extern void UARTIntDisable(unsigned long ulBase, unsigned long ulIntFlags);\r
+extern unsigned long UARTIntStatus(unsigned long ulBase, tBoolean bMasked);\r
+extern void UARTIntClear(unsigned long ulBase, unsigned long ulIntFlags);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __UART_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// watchdog.h - Prototypes for the Watchdog Timer API\r
+//\r
+// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __WATCHDOG_H__\r
+#define __WATCHDOG_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+extern tBoolean WatchdogRunning(unsigned long ulBase);\r
+extern void WatchdogEnable(unsigned long ulBase);\r
+extern void WatchdogResetEnable(unsigned long ulBase);\r
+extern void WatchdogResetDisable(unsigned long ulBase);\r
+extern void WatchdogLock(unsigned long ulBase);\r
+extern void WatchdogUnlock(unsigned long ulBase);\r
+extern tBoolean WatchdogLockState(unsigned long ulBase);\r
+extern void WatchdogReloadSet(unsigned long ulBase, unsigned long ulLoadVal);\r
+extern unsigned long WatchdogReloadGet(unsigned long ulBase);\r
+extern unsigned long WatchdogValueGet(unsigned long ulBase);\r
+extern void WatchdogIntRegister(unsigned long ulBase, void(*pfnHandler)(void));\r
+extern void WatchdogIntUnregister(unsigned long ulBase);\r
+extern void WatchdogIntEnable(unsigned long ulBase);\r
+extern unsigned long WatchdogIntStatus(unsigned long ulBase, tBoolean bMasked);\r
+extern void WatchdogIntClear(unsigned long ulBase);\r
+extern void WatchdogStallDisable(unsigned long ulBase);\r
+extern void WatchdogStallDisable(unsigned long ulBase);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __WATCHDOG_H__\r
--- /dev/null
+/*\r
+ FreeRTOS.org V4.3.0 - Copyright (C) 2003-2007 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS.org distribution.\r
+\r
+ FreeRTOS.org is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS.org is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS.org; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS.org, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section\r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license\r
+ and contact details. Please ensure to read the configuration and relevant\r
+ port sections of the online documentation.\r
+\r
+ Also see http://www.SafeRTOS.com for an IEC 61508 compliant version along\r
+ with commercial development and support options.\r
+ ***************************************************************************\r
+*/\r
+\r
+/*-----------------------------------------------------------\r
+ * Simple parallel port IO routines.\r
+ *-----------------------------------------------------------*/\r
+\r
+/*\r
+*/\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/* Demo includes. */\r
+#include "partest.h"\r
+\r
+/* Library includes. */\r
+#include "hw_types.h"\r
+#include "gpio.h"\r
+#include "hw_memmap.h"\r
+\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestInitialise( void )\r
+{\r
+ GPIODirModeSet( GPIO_PORTF_BASE, GPIO_PIN_0, GPIO_DIR_MODE_OUT );\r
+ GPIOPadConfigSet( GPIO_PORTF_BASE, GPIO_PIN_0, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD );\r
+ GPIOPinWrite( GPIO_PORTF_BASE, GPIO_PIN_0, 0 );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue )\r
+{\r
+ /* There is only one LED. */\r
+ ( void ) uxLED;\r
+ \r
+ GPIOPinWrite( GPIO_PORTF_BASE, GPIO_PIN_0, xValue );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+unsigned portBASE_TYPE uxParTestGetLED( unsigned portBASE_TYPE uxLED )\r
+{\r
+ /* There is only one LED. */\r
+ ( void ) uxLED;\r
+\r
+ return GPIOPinRead( GPIO_PORTF_BASE, GPIO_PIN_0 ); \r
+}\r
+\r
+\r
--- /dev/null
+### uVision2 Project, (C) Keil Software\r
+### Do not modify !\r
+\r
+ cExt (*.c)\r
+ aExt (*.s*; *.src; *.a*)\r
+ oExt (*.obj)\r
+ lExt (*.lib)\r
+ tExt (*.txt; *.h; *.inc)\r
+ pExt (*.plm)\r
+ CppX (*.cpp)\r
+ DaveTm { 0,0,0,0,0,0,0,0 }\r
+\r
+Target (FreeRTOS_Demo), 0x0004 // Tools: 'ARM-ADS'\r
+GRPOPT 1,(Demo_Source),0,0,0\r
+GRPOPT 2,(Libraries),0,0,0\r
+GRPOPT 3,(RTOS_Source),0,0,0\r
+GRPOPT 4,(uIP_Source),1,0,0\r
+\r
+OPTFFF 1,1,1,0,0,0,0,0,<..\Common\Minimal\BlockQ.c><BlockQ.c> \r
+OPTFFF 1,2,1,0,0,0,0,0,<..\Common\Minimal\blocktim.c><blocktim.c> \r
+OPTFFF 1,3,1,0,0,0,0,0,<..\Common\Minimal\death.c><death.c> \r
+OPTFFF 1,4,1,0,0,0,0,0,<..\Common\Minimal\integer.c><integer.c> \r
+OPTFFF 1,5,1,0,0,0,0,0,<.\main.c><main.c> \r
+OPTFFF 1,6,1,0,0,0,0,0,<.\ParTest\ParTest.c><ParTest.c> \r
+OPTFFF 1,7,1,0,0,0,0,0,<..\Common\Minimal\PollQ.c><PollQ.c> \r
+OPTFFF 1,8,1,0,0,0,0,0,<..\Common\Minimal\semtest.c><semtest.c> \r
+OPTFFF 1,9,2,0,0,0,0,0,<.\startup_rvmdk.S><startup_rvmdk.S> \r
+OPTFFF 1,10,1,0,0,0,0,0,<.\timertest.c><timertest.c> \r
+OPTFFF 1,11,5,0,0,0,0,0,<.\FreeRTOSConfig.h><FreeRTOSConfig.h> \r
+OPTFFF 2,12,4,0,0,0,0,0,<.\LuminaryDrivers\driverlib.lib><driverlib.lib> \r
+OPTFFF 2,13,1,0,0,0,0,0,<.\LuminaryDrivers\osram128x64x4.c><osram128x64x4.c> \r
+OPTFFF 3,14,1,0,0,0,0,0,<..\..\Source\tasks.c><tasks.c> \r
+OPTFFF 3,15,1,0,0,0,0,0,<..\..\Source\list.c><list.c> \r
+OPTFFF 3,16,1,0,0,0,0,0,<..\..\Source\queue.c><queue.c> \r
+OPTFFF 3,17,1,0,0,0,0,0,<..\..\Source\portable\RVDS\ARM_CM3\port.c><port.c> \r
+OPTFFF 3,18,1,0,0,0,0,0,<..\..\Source\portable\MemMang\heap_2.c><heap_2.c> \r
+OPTFFF 4,19,1,352321536,0,0,0,0,<.\webserver\uIP_Task.c><uIP_Task.c> \r
+OPTFFF 4,20,1,0,0,0,0,0,<.\webserver\emac.c><emac.c> \r
+OPTFFF 4,21,1,0,0,0,0,0,<.\webserver\httpd.c><httpd.c> \r
+OPTFFF 4,22,1,0,0,0,0,0,<.\webserver\httpd-cgi.c><httpd-cgi.c> \r
+OPTFFF 4,23,1,0,0,0,0,0,<.\webserver\httpd-fs.c><httpd-fs.c> \r
+OPTFFF 4,24,1,0,0,0,0,0,<.\webserver\http-strings.c><http-strings.c> \r
+OPTFFF 4,25,1,0,0,0,0,0,<..\Common\ethernet\uIP\uip-1.0\uip\uip_arp.c><uip_arp.c> \r
+OPTFFF 4,26,1,0,0,0,0,0,<..\Common\ethernet\uIP\uip-1.0\uip\psock.c><psock.c> \r
+OPTFFF 4,27,1,0,0,0,0,0,<..\Common\ethernet\uIP\uip-1.0\uip\timer.c><timer.c> \r
+OPTFFF 4,28,1,0,0,0,0,0,<..\Common\ethernet\uIP\uip-1.0\uip\uip.c><uip.c> \r
+\r
+\r
+TARGOPT 1, (FreeRTOS_Demo)\r
+ ADSCLK=8000000\r
+ OPTTT 1,1,1,0\r
+ OPTHX 1,65535,0,0,0\r
+ OPTLX 79,66,8,<.\rvmdk\>\r
+ OPTOX 16\r
+ OPTLT 1,1,1,0,1,1,0,1,0,0,0,0\r
+ OPTXL 1,1,1,1,1,1,1,0,0\r
+ OPTFL 1,0,1\r
+ OPTAX 255\r
+ OPTBL 0,(Data Sheet)<DATASHTS\Luminary\LM3S6965.PDF>\r
+ OPTDL (SARMCM3.DLL)()(DLM.DLL)(-pLM3S6965)(SARMCM3.DLL)()(TLM.DLL)(-pLM3S6965)\r
+ OPTDBG 48126,3,()()()()()()()()()() (BIN\lmidk-agdi.dll)()()()\r
+ OPTKEY 0,(DLGTARM)((1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(107=-1,-1,-1,-1,0)(100=-1,-1,-1,-1,0)(101=-1,-1,-1,-1,0)(102=-1,-1,-1,-1,0)(161=-1,-1,-1,-1,0)(162=-1,-1,-1,-1,0)(150=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0)(1014=-1,-1,-1,-1,0)(1016=-1,-1,-1,-1,0))\r
+ OPTKEY 0,(ARMDBGFLAGS)()\r
+ OPTKEY 0,(lmidk-agdi)(-B0 -O1792)\r
+ OPTMM 1,2,(0)\r
+ OPTDF 0x84\r
+ OPTLE <>\r
+ OPTLC <>\r
+EndOpt\r
+\r
--- /dev/null
+### uVision2 Project, (C) Keil Software\r
+### Do not modify !\r
+\r
+Target (FreeRTOS_Demo), 0x0004 // Tools: 'ARM-ADS'\r
+\r
+Group (Demo_Source)\r
+Group (Libraries)\r
+Group (RTOS_Source)\r
+Group (uIP_Source)\r
+\r
+File 1,1,<..\Common\Minimal\BlockQ.c><BlockQ.c> 0x46520544 \r
+File 1,1,<..\Common\Minimal\blocktim.c><blocktim.c> 0x46520544 \r
+File 1,1,<..\Common\Minimal\death.c><death.c> 0x46520544 \r
+File 1,1,<..\Common\Minimal\integer.c><integer.c> 0x46520544 \r
+File 1,1,<.\main.c><main.c> 0x4664AC5E \r
+File 1,1,<.\ParTest\ParTest.c><ParTest.c> 0x46520580 \r
+File 1,1,<..\Common\Minimal\PollQ.c><PollQ.c> 0x46520544 \r
+File 1,1,<..\Common\Minimal\semtest.c><semtest.c> 0x46520544 \r
+File 1,2,<.\startup_rvmdk.S><startup_rvmdk.S> 0x4664B752 \r
+File 1,1,<.\timertest.c><timertest.c> 0x46520544 \r
+File 1,5,<.\FreeRTOSConfig.h><FreeRTOSConfig.h> 0x466376CC \r
+File 2,4,<.\LuminaryDrivers\driverlib.lib><driverlib.lib> 0x46647F6C \r
+File 2,1,<.\LuminaryDrivers\osram128x64x4.c><osram128x64x4.c> 0x46649D66 \r
+File 3,1,<..\..\Source\tasks.c><tasks.c> 0x46520544 \r
+File 3,1,<..\..\Source\list.c><list.c> 0x46520544 \r
+File 3,1,<..\..\Source\queue.c><queue.c> 0x46520544 \r
+File 3,1,<..\..\Source\portable\RVDS\ARM_CM3\port.c><port.c> 0x44FB69B0 \r
+File 3,1,<..\..\Source\portable\MemMang\heap_2.c><heap_2.c> 0x46520580 \r
+File 4,1,<.\webserver\uIP_Task.c><uIP_Task.c> 0x4664CFB2 \r
+File 4,1,<.\webserver\emac.c><emac.c> 0x4664A47C \r
+File 4,1,<.\webserver\httpd.c><httpd.c> 0x46118A3C \r
+File 4,1,<.\webserver\httpd-cgi.c><httpd-cgi.c> 0x4651A7C0 \r
+File 4,1,<.\webserver\httpd-fs.c><httpd-fs.c> 0x45613A4C \r
+File 4,1,<.\webserver\http-strings.c><http-strings.c> 0x45613A4C \r
+File 4,1,<..\Common\ethernet\uIP\uip-1.0\uip\uip_arp.c><uip_arp.c> 0x4651BF30 \r
+File 4,1,<..\Common\ethernet\uIP\uip-1.0\uip\psock.c><psock.c> 0x45613A10 \r
+File 4,1,<..\Common\ethernet\uIP\uip-1.0\uip\timer.c><timer.c> 0x45613A10 \r
+File 4,1,<..\Common\ethernet\uIP\uip-1.0\uip\uip.c><uip.c> 0x4651C50C \r
+\r
+\r
+Options 1,0,0 // Target 'FreeRTOS_Demo'\r
+ Device (LM3S6965)\r
+ Vendor (Luminary Micro)\r
+ Cpu (IRAM(0x20000000-0x2000FFFF) IROM(0-0x3FFFF) CLOCK(6000000) CPUTYPE("Cortex-M3"))\r
+ FlashUt ()\r
+ StupF ("STARTUP\Luminary\Startup.s" ("Luminary Startup Code"))\r
+ FlashDR (UL2CM3(-UU0101L5E -O14 -S0 -C0 -N00("ARM Cortex-M3") -D00(1BA00477) -L00(4) -FO7 -FD20000000 -FC800 -FN1 -FF0LM3S_256 -FS00 -FL040000))\r
+ DevID (4337)\r
+ Rgf (LM3Sxxxx.H)\r
+ Mem ()\r
+ C ()\r
+ A ()\r
+ RL ()\r
+ OH ()\r
+ DBC_IFX ()\r
+ DBC_CMS ()\r
+ DBC_AMS ()\r
+ DBC_LMS ()\r
+ UseEnv=0\r
+ EnvBin ()\r
+ EnvInc ()\r
+ EnvLib ()\r
+ EnvReg (ÿLuminary\)\r
+ OrgReg (ÿLuminary\)\r
+ TgStat=16\r
+ OutDir (.\rvmdk\)\r
+ OutName (RTOSDemo)\r
+ GenApp=1\r
+ GenLib=0\r
+ GenHex=0\r
+ Debug=1\r
+ Browse=1\r
+ LstDir (.\rvmdk\)\r
+ HexSel=1\r
+ MG32K=0\r
+ TGMORE=0\r
+ RunUsr 0 1 <fromelf --bin --output .\rvmdk\RTOSDemo.bin .\rvmdk\RTOSDemo.axf>\r
+ RunUsr 1 0 <>\r
+ BrunUsr 0 0 <>\r
+ BrunUsr 1 0 <>\r
+ CrunUsr 0 0 <>\r
+ CrunUsr 1 0 <>\r
+ SVCSID <>\r
+ GLFLAGS=1790\r
+ ADSFLGA { 16,3,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }\r
+ ACPUTYP ("Cortex-M3")\r
+ ADSTFLGA { 0,12,0,2,99,0,0,66,0,0,0,0,0,0,0,0,0,0,0,0 }\r
+ OCMADSOCM { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }\r
+ OCMADSIRAM { 0,0,0,0,32,0,0,1,0 }\r
+ OCMADSIROM { 1,0,0,0,0,0,0,4,0 }\r
+ OCMADSXRAM { 0,0,0,0,0,0,0,0,0 }\r
+ OCR_RVCT { 1,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,4,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,32,0,0,1,0,0,0,0,0,0,0,0,0,0 }\r
+ RV_STAVEC ()\r
+ ADSCCFLG { 9,32,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }\r
+ ADSCMISC ()\r
+ ADSCDEFN (RVDS_ARMCM3_LM3S102, "PACK_STRUCT_END=","ALIGN_STRUCT_END=")\r
+ ADSCUDEF ()\r
+ ADSCINCD (.;.\LuminaryDrivers;..\..\Source\portable\RVDS\ARM_CM3;..\..\Source\include;..\Common\include;..\Common\ethernet\uIP\uip-1.0\uip;.\webserver)\r
+ ADSASFLG { 1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }\r
+ ADSAMISC ()\r
+ ADSADEFN ()\r
+ ADSAUDEF ()\r
+ ADSAINCD ()\r
+ PropFld { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }\r
+ IncBld=1\r
+ AlwaysBuild=0\r
+ GenAsm=0\r
+ AsmAsm=0\r
+ PublicsOnly=0\r
+ StopCode=3\r
+ CustArgs ()\r
+ LibMods ()\r
+ ADSLDFG { 17,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }\r
+ ADSLDTA (0x00000000)\r
+ ADSLDDA (0x20000000)\r
+ ADSLDSC ()\r
+ ADSLDIB ()\r
+ ADSLDIC ()\r
+ ADSLDMC (--entry Reset_Handler)\r
+ ADSLDIF ()\r
+ ADSLDDW ()\r
+ OPTDL (SARMCM3.DLL)()(DLM.DLL)(-pLM3S6965)(SARMCM3.DLL)()(TLM.DLL)(-pLM3S6965)\r
+ OPTDBG 48126,3,()()()()()()()()()() (BIN\lmidk-agdi.dll)()()()\r
+ FLASH1 { 1,0,0,0,1,0,0,0,3,0,0,0,0,0,0,0,0,0,0,0 }\r
+ FLASH2 (BIN\lmidk-agdi.dll)\r
+ FLASH3 ("" ())\r
+ FLASH4 ()\r
+EndOpt\r
+\r
--- /dev/null
+#ifndef BITMAP_H\r
+#define BITMAP_H\r
+\r
+const unsigned char pucImage[] =\r
+{\r
+0x00, 0x0a, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,\r
+0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,\r
+0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,\r
+0xaa, 0xaa, 0xaa, 0x00, 0x0a, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,\r
+0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,\r
+0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,\r
+0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xa0, 0x0a, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,\r
+0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,\r
+0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,\r
+0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xaa, 0xaa, 0xaa, 0xaf, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfa, 0xaa,\r
+0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf7,\r
+0x00, 0x8f, 0xff, 0xff, 0xf8, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0xff, 0xff, 0xff, 0xff, 0xf8, 0x88, 0x88, 0x88,\r
+0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x8f, 0xff, 0xff, 0xff, 0xff, 0xff, 0x88, 0x77, 0x77, 0x78, 0x8f, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xf8, 0x88, 0x77, 0x77, 0x88, 0x8f, 0xff, 0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff,\r
+0xff, 0xff, 0xf0, 0x00, 0x00, 0x8f, 0x00, 0xff, 0x87, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x78, 0xff, 0xff,\r
+0xf7, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x78, 0xff, 0xff, 0xff, 0x87, 0x77, 0x77, 0x77, 0x77, 0x77,\r
+0x77, 0x77, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x7f, 0xff, 0xff, 0xfa, 0xaa,\r
+0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0x70, 0x00, 0x00, 0x8f, 0x00, 0xff, 0x87, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77,\r
+0x77, 0x77, 0xff, 0xff, 0xf7, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x78, 0xff, 0xff, 0xf8, 0x77, 0x77,\r
+0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x78, 0xff, 0xff, 0xff, 0xff, 0x87, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x8f,\r
+0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0x70, 0x08, 0x00, 0x8f, 0x00, 0xff, 0x87, 0x77, 0x77, 0x77,\r
+0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x8f, 0xff, 0xf7, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x78, 0xff,\r
+0xff, 0x87, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x8f, 0xff, 0xff, 0xf8, 0x77, 0x77, 0x77, 0x77, 0x77,\r
+0x77, 0x77, 0x77, 0x8f, 0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0x00, 0x0f, 0x00, 0x8f, 0x00, 0xff,\r
+0x87, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x78, 0xff, 0xf7, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77,\r
+0x77, 0x77, 0x78, 0xff, 0xf8, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x78, 0xff, 0xff, 0xf8, 0x77,\r
+0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x8f, 0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0x70, 0x07,\r
+0x00, 0x70, 0x00, 0xff, 0x87, 0x77, 0x77, 0x77, 0xff, 0xff, 0xf8, 0x77, 0x77, 0x77, 0x77, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0x77, 0x77, 0x77, 0x7f, 0xff, 0xff, 0xff, 0xff, 0x87, 0x77, 0x77, 0x77, 0x78, 0xff, 0xff, 0xf8, 0x77, 0x77, 0x77, 0x77,\r
+0xff, 0xff, 0x87, 0x77, 0x77, 0x77, 0x8f, 0xff, 0xff, 0xff, 0x88, 0x8f, 0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff,\r
+0xff, 0xff, 0x80, 0x00, 0x00, 0x00, 0x07, 0xff, 0x87, 0x77, 0x77, 0x77, 0xff, 0xff, 0xff, 0x87, 0x77, 0x77, 0x77, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0x77, 0x77, 0x77, 0x7f, 0xff, 0xff, 0xff, 0xff, 0x77, 0x77, 0x77, 0x77, 0xff, 0xff, 0xff, 0xff,\r
+0x87, 0x77, 0x77, 0x77, 0xff, 0xff, 0x77, 0x77, 0x77, 0x77, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfa, 0xaa,\r
+0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0xf7, 0x00, 0x00, 0x00, 0x0f, 0xff, 0x87, 0x77, 0x77, 0x77, 0xff, 0xff, 0xff, 0xf8,\r
+0x77, 0x77, 0x77, 0xff, 0xff, 0xff, 0xff, 0xff, 0x77, 0x77, 0x77, 0x7f, 0xff, 0xff, 0xff, 0xff, 0x77, 0x77, 0x77, 0x77,\r
+0xff, 0xff, 0xff, 0xff, 0xf7, 0x77, 0x77, 0x77, 0x8f, 0xff, 0x77, 0x77, 0x77, 0x77, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0xff, 0x70, 0x00, 0x00, 0xff, 0xff, 0x87, 0x77, 0x77, 0x77,\r
+0xff, 0xff, 0xff, 0xf8, 0x77, 0x77, 0x77, 0xff, 0xff, 0xff, 0xff, 0xff, 0x77, 0x77, 0x77, 0x7f, 0xff, 0xff, 0xff, 0xff,\r
+0x77, 0x77, 0x77, 0x78, 0xff, 0xff, 0xff, 0xff, 0xf8, 0x77, 0x77, 0x77, 0x8f, 0xff, 0x77, 0x77, 0x77, 0x77, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0x87, 0x77, 0x77, 0x77, 0xff, 0xff, 0xff, 0xf7, 0x77, 0x77, 0x78, 0xff, 0xff, 0xff, 0xff, 0xff, 0x77, 0x77, 0x77, 0x7f,\r
+0xff, 0xff, 0xff, 0xf8, 0x77, 0x77, 0x77, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xff, 0x87, 0x77, 0x77, 0x78, 0xff, 0x87, 0x77,\r
+0x77, 0x77, 0x78, 0x8f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0x88, 0xff, 0xff, 0xff, 0x87, 0x77, 0x77, 0x77, 0xff, 0xff, 0xf8, 0x87, 0x77, 0x77, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0x77, 0x77, 0x77, 0x7f, 0xff, 0xff, 0xff, 0xf8, 0x77, 0x77, 0x77, 0x8f, 0xff, 0xff, 0xff, 0xff, 0xff, 0x87, 0x77, 0x77,\r
+0x78, 0xff, 0x87, 0x77, 0x77, 0x77, 0x77, 0x77, 0x8f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0x80, 0x00, 0x8f, 0x8f, 0xff, 0x87, 0x77, 0x77, 0x77, 0x88, 0x88, 0x77, 0x77, 0x77, 0x77, 0x8f, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0x77, 0x77, 0x77, 0x7f, 0xff, 0xff, 0xff, 0xf8, 0x77, 0x77, 0x77, 0x8f, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0x87, 0x77, 0x77, 0x78, 0xff, 0xf7, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x88, 0xff, 0xff, 0xff, 0xff, 0xfa, 0xaa,\r
+0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0xf7, 0x00, 0x00, 0x8f, 0x07, 0xff, 0x87, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77,\r
+0x77, 0x77, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x77, 0x77, 0x77, 0x7f, 0xff, 0xff, 0xff, 0xf8, 0x77, 0x77, 0x77, 0x8f,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0x87, 0x77, 0x77, 0x78, 0xff, 0xf8, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x8f, 0xff,\r
+0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0x70, 0x07, 0x00, 0x8f, 0x00, 0xff, 0x87, 0x77, 0x77, 0x77,\r
+0x77, 0x77, 0x77, 0x77, 0x88, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x77, 0x77, 0x77, 0x7f, 0xff, 0xff, 0xff, 0xf8,\r
+0x77, 0x77, 0x77, 0x8f, 0xff, 0xff, 0xff, 0xff, 0xff, 0x87, 0x77, 0x77, 0x78, 0xff, 0xff, 0xf8, 0x77, 0x77, 0x77, 0x77,\r
+0x77, 0x77, 0x77, 0x8f, 0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0x70, 0x0f, 0x00, 0x8f, 0x00, 0xff,\r
+0x87, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x8f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x77, 0x77, 0x77, 0x7f,\r
+0xff, 0xff, 0xff, 0xf8, 0x77, 0x77, 0x77, 0x8f, 0xff, 0xff, 0xff, 0xff, 0xff, 0x87, 0x77, 0x77, 0x78, 0xff, 0xff, 0xff,\r
+0x87, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x78, 0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0x00, 0x0f,\r
+0x00, 0x8f, 0x00, 0xff, 0x87, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x78, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0x77, 0x77, 0x77, 0x7f, 0xff, 0xff, 0xff, 0xf8, 0x77, 0x77, 0x77, 0x8f, 0xff, 0xff, 0xff, 0xff, 0xff, 0x87, 0x77, 0x77,\r
+0x78, 0xff, 0xff, 0xff, 0xff, 0x88, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff,\r
+0xff, 0xff, 0x70, 0x08, 0x00, 0x88, 0x00, 0xff, 0x87, 0x77, 0x77, 0x77, 0x88, 0x88, 0x77, 0x77, 0x77, 0x78, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0x77, 0x77, 0x77, 0x7f, 0xff, 0xff, 0xff, 0xf8, 0x77, 0x77, 0x77, 0x8f, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0x87, 0x77, 0x77, 0x78, 0xff, 0xff, 0xff, 0xff, 0xff, 0x88, 0x77, 0x77, 0x77, 0x77, 0x77, 0xff, 0xff, 0xfa, 0xaa,\r
+0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0x70, 0x00, 0x00, 0x70, 0x07, 0xff, 0x87, 0x77, 0x77, 0x77, 0xff, 0xff, 0x77, 0x77,\r
+0x77, 0x77, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x77, 0x77, 0x77, 0x7f, 0xff, 0xff, 0xff, 0xf8, 0x77, 0x77, 0x77, 0x7f,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0x87, 0x77, 0x77, 0x78, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf8, 0x77, 0x77, 0x77, 0x77,\r
+0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0xf8, 0x00, 0x00, 0x00, 0x7f, 0xff, 0x87, 0x77, 0x77, 0x77,\r
+0xff, 0xff, 0xf7, 0x77, 0x77, 0x77, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x77, 0x77, 0x77, 0x7f, 0xff, 0xff, 0xff, 0xff,\r
+0x77, 0x77, 0x77, 0x78, 0xff, 0xff, 0xff, 0xff, 0xf8, 0x77, 0x77, 0x77, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0x87, 0x77, 0x77, 0x77, 0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0xff, 0x80, 0x00, 0x00, 0xff, 0xff,\r
+0x87, 0x77, 0x77, 0x77, 0xff, 0xff, 0xf8, 0x77, 0x77, 0x77, 0x8f, 0xff, 0xff, 0xff, 0xff, 0xff, 0x77, 0x77, 0x77, 0x7f,\r
+0xff, 0xff, 0xff, 0xff, 0x77, 0x77, 0x77, 0x77, 0xff, 0xff, 0xff, 0xff, 0xf7, 0x77, 0x77, 0x77, 0x8f, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0x87, 0x77, 0x77, 0x77, 0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0x87, 0x88,\r
+0x88, 0x8f, 0xff, 0xff, 0x87, 0x77, 0x77, 0x77, 0xff, 0xff, 0xff, 0x77, 0x77, 0x77, 0x8f, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0x77, 0x77, 0x77, 0x7f, 0xff, 0xff, 0xff, 0xff, 0x77, 0x77, 0x77, 0x77, 0xff, 0xff, 0xff, 0xff, 0x87, 0x77, 0x77, 0x77,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x87, 0x77, 0x77, 0x77, 0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff,\r
+0xff, 0xff, 0x00, 0x07, 0xff, 0xff, 0xff, 0xff, 0x87, 0x77, 0x77, 0x77, 0xff, 0xff, 0xff, 0x87, 0x77, 0x77, 0x7f, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0x77, 0x77, 0x77, 0x7f, 0xff, 0xff, 0xff, 0xff, 0x87, 0x77, 0x77, 0x77, 0x8f, 0xff, 0xff, 0xff,\r
+0x77, 0x77, 0x77, 0x77, 0xff, 0xff, 0xf7, 0x88, 0xff, 0xff, 0xff, 0xff, 0x87, 0x77, 0x77, 0x77, 0xff, 0xff, 0xfa, 0xaa,\r
+0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0x80, 0x00, 0xff, 0xff, 0xff, 0xff, 0x87, 0x77, 0x77, 0x77, 0xff, 0xff, 0xff, 0xf7,\r
+0x77, 0x77, 0x78, 0xff, 0xff, 0xff, 0xff, 0xff, 0x77, 0x77, 0x77, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xf8, 0x77, 0x77, 0x77,\r
+0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x78, 0xff, 0xff, 0x87, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x78,\r
+0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0xf7, 0x00, 0x88, 0x88, 0x88, 0xff, 0x87, 0x77, 0x77, 0x77,\r
+0xff, 0xff, 0xff, 0xf8, 0x77, 0x77, 0x77, 0xff, 0xff, 0xff, 0xff, 0xff, 0x77, 0x77, 0x77, 0x7f, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0x87, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x8f, 0xff, 0xff, 0x87, 0x77, 0x77, 0x77, 0x77, 0x77,\r
+0x77, 0x77, 0x77, 0x7f, 0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0x70, 0x00, 0x00, 0x00, 0x00, 0xff,\r
+0x87, 0x77, 0x77, 0x77, 0xff, 0xff, 0xff, 0xf8, 0x77, 0x77, 0x77, 0x8f, 0xff, 0xff, 0xff, 0xff, 0x77, 0x77, 0x77, 0x7f,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xf8, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x78, 0xff, 0xff, 0xff, 0x87, 0x77,\r
+0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0xff, 0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0x70, 0x00,\r
+0x00, 0x00, 0x00, 0xff, 0x87, 0x77, 0x77, 0x77, 0xff, 0xff, 0xff, 0xff, 0x77, 0x77, 0x77, 0x7f, 0xff, 0xff, 0xff, 0xff,\r
+0x77, 0x77, 0x77, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x87, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x8f, 0xff,\r
+0xff, 0xff, 0x87, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x8f, 0xff, 0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff,\r
+0xff, 0xff, 0x70, 0x00, 0x00, 0x00, 0x07, 0xff, 0x88, 0x88, 0x88, 0x88, 0xff, 0xff, 0xff, 0xff, 0x88, 0x88, 0x88, 0x88,\r
+0xff, 0xff, 0xff, 0xff, 0x88, 0x88, 0x88, 0x8f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf8, 0x87, 0x77, 0x77, 0x77,\r
+0x88, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x88, 0x77, 0x77, 0x77, 0x77, 0x88, 0x8f, 0xff, 0xff, 0xff, 0xff, 0xfa, 0xaa,\r
+0xaa, 0xaf, 0xff, 0xff, 0x00, 0x0f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff, 0x00, 0x0f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff, 0x00, 0x0f, 0x70, 0x08, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff, 0x00, 0x07, 0x70, 0x07,\r
+0x88, 0x88, 0x88, 0xff, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88,\r
+0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88,\r
+0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff,\r
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xfa, 0xaa,\r
+0xaa, 0xaf, 0xff, 0xff, 0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r
+0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff, 0xf7, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x70, 0x00, 0x00, 0x00,\r
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r
+0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0x70, 0x08, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0x70, 0x08,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaf, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfa, 0xaa,\r
+0xaa, 0xaf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaa, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,\r
+0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,\r
+0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,\r
+0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x0a, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,\r
+0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,\r
+0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,\r
+0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xa0, 0x00, 0xaa, 0xaa, 0xaa,\r
+0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,\r
+0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,\r
+0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x00,\r
+0x00 };\r
+\r
+#define bmpBITMAP_HEIGHT 50\r
+#define bmpBITMAP_WIDTH 128\r
+\r
+#endif\r
--- /dev/null
+#ifndef LCD_MESSAGE_H\r
+#define LCD_MESSAGE_H\r
+\r
+typedef struct\r
+{\r
+ char *pcMessage;\r
+} xOLEDMessage;\r
+\r
+#endif /* LCD_MESSAGE_H */\r
--- /dev/null
+/*\r
+ FreeRTOS.org V4.3.0 - Copyright (C) 2003-2007 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS.org distribution.\r
+\r
+ FreeRTOS.org is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS.org is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS.org; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS.org, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section\r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license\r
+ and contact details. Please ensure to read the configuration and relevant\r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+\r
+/*\r
+ * Creates all the demo application tasks, then starts the scheduler. The WEB\r
+ * documentation provides more details of the standard demo application tasks.\r
+ * In addition to the standard demo tasks, the following tasks and tests are\r
+ * defined and/or created within this file:\r
+ *\r
+ * "Fast Interrupt Test" - A high frequency periodic interrupt is generated\r
+ * using a free running timer to demonstrate the use of the\r
+ * configKERNEL_INTERRUPT_PRIORITY configuration constant. The interrupt\r
+ * service routine measures the number of processor clocks that occur between\r
+ * each interrupt - and in so doing measures the jitter in the interrupt timing.\r
+ * The maximum measured jitter time is latched in the ulMaxJitter variable, and\r
+ * displayed on the OLED display by the 'Check' task as described below. The\r
+ * fast interrupt is configured and handled in the timertest.c source file.\r
+ *\r
+ * "OLED" task - the OLED task is a 'gatekeeper' task. It is the only task that\r
+ * is permitted to access the display directly. Other tasks wishing to write a\r
+ * message to the OLED send the message on a queue to the OLED task instead of\r
+ * accessing the OLED themselves. The OLED task just blocks on the queue waiting\r
+ * for messages - waking and displaying the messages as they arrive.\r
+ *\r
+ * "Check" task - This only executes every five seconds but has the highest\r
+ * priority so is guaranteed to get processor time. Its main function is to\r
+ * check that all the standard demo tasks are still operational. Should any\r
+ * unexpected behaviour within a demo task be discovered the 'check' task will\r
+ * write an error to the OLED (via the OLED task). If all the demo tasks are\r
+ * executing with their expected behaviour then the check task writes PASS\r
+ * along with the max jitter time to the OLED (again via the OLED task), as\r
+ * described above.\r
+ *\r
+ * "uIP" task - This is the task that handles the uIP stack. All TCP/IP\r
+ * processing is performed in this task.\r
+ */\r
+\r
+\r
+\r
+/* Standard includes. */\r
+#include <stdio.h>\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "Task.h"\r
+#include "queue.h"\r
+#include "semphr.h"\r
+\r
+/* Demo app includes. */\r
+#include "BlockQ.h"\r
+#include "death.h"\r
+#include "integer.h"\r
+#include "blocktim.h"\r
+#include "flash.h"\r
+#include "partest.h"\r
+#include "semtest.h"\r
+#include "pollq.h"\r
+#include "lcd_message.h"\r
+#include "bitmap.h"\r
+\r
+/* Hardware library includes. */\r
+#include "hw_memmap.h"\r
+#include "hw_types.h"\r
+#include "sysctl.h"\r
+#include "gpio.h"\r
+#include "osram128x64x4.h"\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* The time between cycles of the 'check' task. */\r
+#define mainCHECK_DELAY ( ( portTickType ) 5000 / portTICK_RATE_MS )\r
+\r
+/* Size of the stack allocated to the uIP task. */\r
+#define mainBASIC_WEB_STACK_SIZE ( 200 )\r
+\r
+/* The check task uses the sprintf function so requires a little more stack too. */\r
+#define mainCHECK_TASK_STACK_SIZE ( configMINIMAL_STACK_SIZE + 50 )\r
+\r
+/* Task priorities. */\r
+#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
+#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 )\r
+#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 )\r
+#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
+#define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 )\r
+#define mainINTEGER_TASK_PRIORITY ( tskIDLE_PRIORITY )\r
+\r
+/* The maximum number of message that can be waiting for display at any one\r
+time. */\r
+#define mainOLED_QUEUE_SIZE ( 3 )\r
+\r
+/* Dimensions the buffer into which the jitter time is written. */\r
+#define mainMAX_MSG_LEN 25\r
+\r
+/* The period of the system clock in nano seconds. This is used to calculate\r
+the jitter time in nano seconds. */\r
+#define mainNS_PER_CLOCK ( ( unsigned portLONG ) ( ( 1.0 / ( double ) configCPU_CLOCK_HZ ) * 1000000000.0 ) )\r
+\r
+/* Constants used when writing strings to the display. */\r
+#define mainCHARACTER_HEIGHT ( 9 )\r
+#define mainMAX_ROWS ( mainCHARACTER_HEIGHT * 7 )\r
+#define mainFULL_SCALE ( 15 )\r
+#define ulSSI_FREQUENCY 1000000\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Checks the status of all the demo tasks then prints a message to the\r
+ * display. The message will be either PASS - an include in brackets the\r
+ * maximum measured jitter time (as described at the to of the file), or a\r
+ * message that describes which of the standard demo tasks an error has been\r
+ * discovered in.\r
+ *\r
+ * Messages are not written directly to the terminal, but passed to vOLEDTask\r
+ * via a queue.\r
+ */\r
+static void vCheckTask( void *pvParameters );\r
+\r
+/*\r
+ * The task that handles the uIP stack. All TCP/IP processing is performed in\r
+ * this task.\r
+ */\r
+extern void vuIP_Task( void *pvParameters );\r
+\r
+/*\r
+ * The display is written two by more than one task so is controlled by a\r
+ * 'gatekeeper' task. This is the only task that is actually permitted to\r
+ * access the display directly. Other tasks wanting to display a message send\r
+ * the message to the gatekeeper.\r
+ */\r
+static void vOLEDTask( void *pvParameters );\r
+\r
+/*\r
+ * Configure the hardware for the demo.\r
+ */\r
+static void prvSetupHardware( void );\r
+\r
+/*\r
+ * Configures the high frequency timers - those used to measure the timing\r
+ * jitter while the real time kernel is executing.\r
+ */\r
+extern void vSetupTimer( void );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* The queue used to send messages to the OLED task. */\r
+xQueueHandle xOLEDQueue;\r
+\r
+/* The welcome text. */\r
+const portCHAR * const pcWelcomeMessage = " www.FreeRTOS.org";\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+int main( void )\r
+{\r
+ prvSetupHardware();\r
+\r
+ /* Create the queue used by the OLED task. Messages for display on the OLED\r
+ are received via this queue. */\r
+ xOLEDQueue = xQueueCreate( mainOLED_QUEUE_SIZE, sizeof( xOLEDMessage ) );\r
+\r
+ /* Create the uIP task. */\r
+ xTaskCreate( vuIP_Task, ( signed portCHAR * ) "uIP", mainBASIC_WEB_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY - 1, NULL );\r
+\r
+ /* Start the standard demo tasks. */\r
+ vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY );\r
+ vCreateBlockTimeTasks();\r
+ vStartSemaphoreTasks( mainSEM_TEST_PRIORITY );\r
+ vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY );\r
+ vStartIntegerMathTasks( mainINTEGER_TASK_PRIORITY );\r
+\r
+ /* Start the tasks defined within this file/specific to this demo. */\r
+ xTaskCreate( vCheckTask, ( signed portCHAR * ) "Check", mainCHECK_TASK_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL );\r
+ xTaskCreate( vOLEDTask, ( signed portCHAR * ) "OLED", configMINIMAL_STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );\r
+\r
+ /* The suicide tasks must be created last as they need to know how many\r
+ tasks were running prior to their creation in order to ascertain whether\r
+ or not the correct/expected number of tasks are running at any given time. */\r
+ vCreateSuicidalTasks( mainCREATOR_TASK_PRIORITY );\r
+\r
+ /* Configure the high frequency interrupt used to measure the interrupt\r
+ jitter time. */\r
+ #ifdef __ICCARM__\r
+ vSetupTimer();\r
+ #endif\r
+ \r
+ /* Start the scheduler. */\r
+ vTaskStartScheduler();\r
+\r
+ /* Will only get here if there was insufficient memory to create the idle\r
+ task. */\r
+ return 0;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void prvSetupHardware( void )\r
+{\r
+ /* Set the clocking to run from the PLL at 50 MHz */\r
+ SysCtlClockSet( SYSCTL_SYSDIV_4 | SYSCTL_USE_PLL | SYSCTL_OSC_MAIN | SYSCTL_XTAL_8MHZ );\r
+ \r
+ /* Enable/Reset the Ethernet Controller */\r
+ SysCtlPeripheralEnable( SYSCTL_PERIPH_ETH );\r
+ SysCtlPeripheralReset( SYSCTL_PERIPH_ETH );\r
+ \r
+ /* Enable Port F for Ethernet LEDs\r
+ LED0 Bit 3 Output\r
+ LED1 Bit 2 Output */\r
+ SysCtlPeripheralEnable( SYSCTL_PERIPH_GPIOF );\r
+ GPIODirModeSet( GPIO_PORTF_BASE, (GPIO_PIN_2 | GPIO_PIN_3), GPIO_DIR_MODE_HW );\r
+ GPIOPadConfigSet( GPIO_PORTF_BASE, (GPIO_PIN_2 | GPIO_PIN_3 ), GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD ); \r
+ \r
+ vParTestInitialise();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void vCheckTask( void *pvParameters )\r
+{\r
+portTickType xLastExecutionTime;\r
+xOLEDMessage xMessage;\r
+static portCHAR cPassMessage[ mainMAX_MSG_LEN ];\r
+extern unsigned portLONG ulMaxJitter;\r
+\r
+ xLastExecutionTime = xTaskGetTickCount();\r
+ xMessage.pcMessage = cPassMessage;\r
+ \r
+ for( ;; )\r
+ {\r
+ /* Perform this check every mainCHECK_DELAY milliseconds. */\r
+ vTaskDelayUntil( &xLastExecutionTime, mainCHECK_DELAY );\r
+\r
+ /* Has an error been found in any task? */\r
+\r
+ if( xAreBlockingQueuesStillRunning() != pdTRUE )\r
+ {\r
+ xMessage.pcMessage = "ERROR IN BLOCK Q";\r
+ }\r
+ else if( xAreBlockTimeTestTasksStillRunning() != pdTRUE )\r
+ {\r
+ xMessage.pcMessage = "ERROR IN BLOCK TIME";\r
+ }\r
+ else if( xAreSemaphoreTasksStillRunning() != pdTRUE )\r
+ {\r
+ xMessage.pcMessage = "ERROR IN SEMAPHORE";\r
+ }\r
+ else if( xArePollingQueuesStillRunning() != pdTRUE )\r
+ {\r
+ xMessage.pcMessage = "ERROR IN POLL Q";\r
+ }\r
+ else if( xIsCreateTaskStillRunning() != pdTRUE )\r
+ {\r
+ xMessage.pcMessage = "ERROR IN CREATE";\r
+ }\r
+ else if( xAreIntegerMathsTaskStillRunning() != pdTRUE )\r
+ {\r
+ xMessage.pcMessage = "ERROR IN MATH";\r
+ }\r
+ else\r
+ {\r
+ #ifdef __ICCARM__\r
+ sprintf( cPassMessage, "PASS [%uns]", ulMaxJitter * mainNS_PER_CLOCK );\r
+ #else\r
+ sprintf( cPassMessage, "PASS" );\r
+ #endif\r
+ }\r
+\r
+ /* Send the message to the OLED gatekeeper for display. */\r
+ xQueueSend( xOLEDQueue, &xMessage, portMAX_DELAY );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+\r
+\r
+void vOLEDTask( void *pvParameters )\r
+{\r
+xOLEDMessage xMessage;\r
+unsigned portLONG ulY = mainMAX_ROWS;\r
+\r
+ /* Initialise the OLED and display a startup message. */\r
+ OSRAM128x64x4Init( ulSSI_FREQUENCY ); \r
+ \r
+ OSRAM128x64x4StringDraw( " POWERED BY FreeRTOS", 0, 0, mainFULL_SCALE );\r
+ OSRAM128x64x4ImageDraw( pucImage, 0, mainCHARACTER_HEIGHT + 1, bmpBITMAP_WIDTH, bmpBITMAP_HEIGHT );\r
+ \r
+ for( ;; )\r
+ {\r
+ /* Wait for a message to arrive that requires displaying. */\r
+ xQueueReceive( xOLEDQueue, &xMessage, portMAX_DELAY );\r
+ \r
+ /* Write the message on the next available row. */\r
+ ulY += mainCHARACTER_HEIGHT;\r
+ if( ulY >= mainMAX_ROWS )\r
+ {\r
+ ulY = mainCHARACTER_HEIGHT;\r
+ OSRAM128x64x4Clear();\r
+ OSRAM128x64x4StringDraw( pcWelcomeMessage, 0, 0, mainFULL_SCALE ); \r
+ }\r
+\r
+ /* Display the message. */\r
+ OSRAM128x64x4StringDraw( xMessage.pcMessage, 0, ulY, mainFULL_SCALE );\r
+ }\r
+}\r
--- /dev/null
+; <<< Use Configuration Wizard in Context Menu >>>\r
+;******************************************************************************\r
+;\r
+; startup_rvmdk.S - Startup code for use with Keil's uVision.\r
+;\r
+; Copyright (c) 2007 Luminary Micro, Inc. All rights reserved.\r
+; \r
+; Software License Agreement\r
+; \r
+; Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+; exclusively on LMI's microcontroller products.\r
+; \r
+; The software is owned by LMI and/or its suppliers, and is protected under\r
+; applicable copyright laws. All rights are reserved. Any use in violation\r
+; of the foregoing restrictions may subject the user to criminal sanctions\r
+; under applicable laws, as well as to civil liability for the breach of the\r
+; terms and conditions of this license.\r
+; \r
+; THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+; OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+; MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+; LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+; CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+; \r
+; This is part of revision 1408 of the Stellaris Peripheral Driver Library.\r
+;\r
+;******************************************************************************\r
+\r
+;******************************************************************************\r
+;\r
+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\r
+;\r
+;******************************************************************************\r
+Stack EQU 0x00000800\r
+\r
+;******************************************************************************\r
+;\r
+; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\r
+;\r
+;******************************************************************************\r
+Heap EQU 0x00000000\r
+\r
+;******************************************************************************\r
+;\r
+; Allocate space for the stack.\r
+;\r
+;******************************************************************************\r
+ AREA STACK, NOINIT, READWRITE, ALIGN=3\r
+StackMem\r
+ SPACE Stack\r
+__initial_sp\r
+\r
+;******************************************************************************\r
+;\r
+; Allocate space for the heap.\r
+;\r
+;******************************************************************************\r
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3\r
+__heap_base\r
+HeapMem\r
+ SPACE Heap\r
+__heap_limit\r
+\r
+;******************************************************************************\r
+;\r
+; Indicate that the code in this file preserves 8-byte alignment of the stack.\r
+;\r
+;******************************************************************************\r
+ PRESERVE8\r
+\r
+;******************************************************************************\r
+;\r
+; Place code into the reset code section.\r
+;\r
+;******************************************************************************\r
+ AREA RESET, CODE, READONLY\r
+ THUMB\r
+\r
+;******************************************************************************\r
+;\r
+; The vector table.\r
+;\r
+;******************************************************************************\r
+ EXPORT __Vectors\r
+__Vectors\r
+ DCD StackMem + Stack ; Top of Stack\r
+ DCD Reset_Handler ; Reset Handler\r
+ DCD NmiSR ; NMI Handler\r
+ DCD FaultISR ; Hard Fault Handler\r
+ DCD IntDefaultHandler ; MPU Fault Handler\r
+ DCD IntDefaultHandler ; Bus Fault Handler\r
+ DCD IntDefaultHandler ; Usage Fault Handler\r
+ DCD 0 ; Reserved\r
+ DCD 0 ; Reserved\r
+ DCD 0 ; Reserved\r
+ DCD 0 ; Reserved\r
+ DCD IntDefaultHandler ; SVCall Handler\r
+ DCD IntDefaultHandler ; Debug Monitor Handler\r
+ DCD 0 ; Reserved\r
+ EXTERN xPortPendSVHandler\r
+ DCD xPortPendSVHandler ; PendSV Handler\r
+ EXTERN xPortSysTickHandler\r
+ DCD xPortSysTickHandler ; SysTick Handler\r
+ DCD IntDefaultHandler ; GPIO Port A\r
+ DCD IntDefaultHandler ; GPIO Port B\r
+ DCD IntDefaultHandler ; GPIO Port C\r
+ DCD IntDefaultHandler ; GPIO Port D\r
+ DCD IntDefaultHandler ; GPIO Port E\r
+ DCD IntDefaultHandler ; UART0\r
+ DCD IntDefaultHandler ; UART1\r
+ DCD IntDefaultHandler ; SSI\r
+ DCD IntDefaultHandler ; I2C\r
+ DCD IntDefaultHandler ; PWM Fault\r
+ DCD IntDefaultHandler ; PWM Generator 0\r
+ DCD IntDefaultHandler ; PWM Generator 1\r
+ DCD IntDefaultHandler ; PWM Generator 2\r
+ DCD IntDefaultHandler ; Quadrature Encoder\r
+ DCD IntDefaultHandler ; ADC Sequence 0\r
+ DCD IntDefaultHandler ; ADC Sequence 1\r
+ DCD IntDefaultHandler ; ADC Sequence 2\r
+ DCD IntDefaultHandler ; ADC Sequence 3\r
+ DCD IntDefaultHandler ; Watchdog\r
+ EXTERN Timer0IntHandler\r
+ DCD Timer0IntHandler ; Timer 0A\r
+ DCD IntDefaultHandler ; Timer 0B\r
+ DCD IntDefaultHandler ; Timer 1A\r
+ DCD IntDefaultHandler ; Timer 1B\r
+ DCD IntDefaultHandler ; Timer 2A\r
+ DCD IntDefaultHandler ; Timer 2B\r
+ DCD IntDefaultHandler ; Comp 0\r
+ DCD IntDefaultHandler ; Comp 1\r
+ DCD IntDefaultHandler ; Comp 2\r
+ DCD IntDefaultHandler ; System Control\r
+ DCD IntDefaultHandler ; Flash Control\r
+ DCD IntDefaultHandler ; GPIO Port F\r
+ DCD IntDefaultHandler ; GPIO Port G\r
+ DCD IntDefaultHandler ; GPIO Port H\r
+ DCD IntDefaultHandler ; UART2 Rx and Tx\r
+ DCD IntDefaultHandler ; SSI1 Rx and Tx\r
+ DCD IntDefaultHandler ; Timer 3 subtimer A\r
+ DCD IntDefaultHandler ; Timer 3 subtimer B\r
+ DCD IntDefaultHandler ; I2C1 Master and Slave\r
+ DCD IntDefaultHandler ; Quadrature Encoder 1\r
+ DCD IntDefaultHandler ; CAN0\r
+ DCD IntDefaultHandler ; CAN1\r
+ DCD 0 ; Reserved\r
+ EXTERN vEMAC_ISR\r
+ DCD vEMAC_ISR ; Ethernet\r
+ DCD IntDefaultHandler ; Hibernate\r
+\r
+;******************************************************************************\r
+;\r
+; This is the code that gets called when the processor first starts execution\r
+; following a reset event.\r
+;\r
+;******************************************************************************\r
+ EXPORT Reset_Handler\r
+Reset_Handler\r
+ ;\r
+ ; Call the C library enty point that handles startup. This will copy\r
+ ; the .data section initializers from flash to SRAM and zero fill the\r
+ ; .bss section. It will then call __rt_entry, which will be either the\r
+ ; C library version or the one supplied here depending on the\r
+ ; configured startup type.\r
+ ;\r
+ IMPORT __main\r
+ B __main\r
+\r
+;******************************************************************************\r
+;\r
+; This is the code that gets called when the processor receives a NMI. This\r
+; simply enters an infinite loop, preserving the system state for examination\r
+; by a debugger.\r
+;\r
+;******************************************************************************\r
+NmiSR\r
+ B NmiSR\r
+\r
+;******************************************************************************\r
+;\r
+; This is the code that gets called when the processor receives a fault\r
+; interrupt. This simply enters an infinite loop, preserving the system state\r
+; for examination by a debugger.\r
+;\r
+;******************************************************************************\r
+FaultISR\r
+ B FaultISR\r
+\r
+;******************************************************************************\r
+;\r
+; This is the code that gets called when the processor receives an unexpected\r
+; interrupt. This simply enters an infinite loop, preserving the system state\r
+; for examination by a debugger.\r
+;\r
+;******************************************************************************\r
+IntDefaultHandler\r
+ B IntDefaultHandler\r
+\r
+;******************************************************************************\r
+;\r
+; Make sure the end of this section is aligned.\r
+;\r
+;******************************************************************************\r
+ ALIGN\r
+\r
+;******************************************************************************\r
+;\r
+; Some code in the normal code section for initializing the heap and stack.\r
+;\r
+;******************************************************************************\r
+ AREA |.text|, CODE, READONLY\r
+\r
+;******************************************************************************\r
+;\r
+; The function expected of the C library startup code for defining the stack\r
+; and heap memory locations. For the C library version of the startup code,\r
+; provide this function so that the C library initialization code can find out\r
+; the location of the stack and heap.\r
+;\r
+;******************************************************************************\r
+ IF :DEF: __MICROLIB\r
+ EXPORT __initial_sp\r
+ EXPORT __heap_base\r
+ EXPORT __heap_limit\r
+ ELSE\r
+ IMPORT __use_two_region_memory\r
+ EXPORT __user_initial_stackheap\r
+__user_initial_stackheap\r
+ LDR R0, =HeapMem\r
+ LDR R1, =(StackMem + Stack)\r
+ LDR R2, =(HeapMem + Heap)\r
+ LDR R3, =StackMem\r
+ BX LR\r
+ ENDIF\r
+\r
+;******************************************************************************\r
+;\r
+; Make sure the end of this section is aligned.\r
+;\r
+;******************************************************************************\r
+ ALIGN\r
+\r
+;******************************************************************************\r
+;\r
+; Tell the assembler that we're done.\r
+;\r
+;******************************************************************************\r
+ END\r
--- /dev/null
+/*\r
+ FreeRTOS.org V4.3.0 - Copyright (C) 2003-2007 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS.org distribution.\r
+\r
+ FreeRTOS.org is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS.org is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS.org; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS.org, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section\r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license\r
+ and contact details. Please ensure to read the configuration and relevant\r
+ port sections of the online documentation.\r
+\r
+ Also see http://www.SafeRTOS.com for an IEC 61508 compliant version along\r
+ with commercial development and support options.\r
+ ***************************************************************************\r
+*/\r
+\r
+/* High speed timer test as described in main.c. */\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+\r
+/* Library includes. */\r
+#include "hw_ints.h"\r
+#include "hw_memmap.h"\r
+#include "hw_types.h"\r
+#include "interrupt.h"\r
+#include "sysctl.h"\r
+#include "LMI_timer.h"\r
+\r
+/* The set frequency of the interrupt. Deviations from this are measured as\r
+the jitter. */\r
+#define timerINTERRUPT_FREQUENCY ( 20000UL )\r
+\r
+/* The expected time between each of the timer interrupts - if the jitter was\r
+zero. */\r
+#define timerEXPECTED_DIFFERENCE_VALUE ( configCPU_CLOCK_HZ / timerINTERRUPT_FREQUENCY )\r
+\r
+/* The highest available interrupt priority. */\r
+#define timerHIGHEST_PRIORITY ( 0 )\r
+\r
+/* Misc defines. */\r
+#define timerMAX_32BIT_VALUE ( 0xffffffffUL )\r
+#define timerTIMER_1_COUNT_VALUE ( * ( ( unsigned long * ) ( TIMER1_BASE + 0x48 ) ) )\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Interrupt handler in which the jitter is measured. */\r
+void Timer0IntHandler( void );\r
+\r
+/* Stores the value of the maximum recorded jitter between interrupts. */\r
+unsigned portLONG ulMaxJitter = 0;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void vSetupTimer( void )\r
+{\r
+unsigned long ulFrequency;\r
+\r
+ /* Timer zero is used to generate the interrupts, and timer 1 is used\r
+ to measure the jitter. */\r
+ SysCtlPeripheralEnable( SYSCTL_PERIPH_TIMER0 );\r
+ SysCtlPeripheralEnable( SYSCTL_PERIPH_TIMER1 );\r
+ TimerConfigure( TIMER0_BASE, TIMER_CFG_32_BIT_PER );\r
+ TimerConfigure( TIMER1_BASE, TIMER_CFG_32_BIT_PER );\r
+ \r
+ /* Set the timer interrupt to be above the kernel - highest. */\r
+ IntPrioritySet( INT_TIMER0A, timerHIGHEST_PRIORITY );\r
+\r
+ /* Just used to measure time. */\r
+ TimerLoadSet(TIMER1_BASE, TIMER_A, timerMAX_32BIT_VALUE );\r
+ \r
+ /* The rate at which the timer will interrupt. */\r
+ ulFrequency = configCPU_CLOCK_HZ / timerINTERRUPT_FREQUENCY; \r
+ TimerLoadSet( TIMER0_BASE, TIMER_A, ulFrequency );\r
+ IntEnable( INT_TIMER0A );\r
+ TimerIntEnable( TIMER0_BASE, TIMER_TIMA_TIMEOUT );\r
+\r
+ /* Enable both timers. */ \r
+ TimerEnable( TIMER0_BASE, TIMER_A );\r
+ TimerEnable( TIMER1_BASE, TIMER_A );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void Timer0IntHandler( void )\r
+{\r
+unsigned portLONG ulDifference, ulCurrentCount;\r
+static portLONG ulMaxDifference = 0, ulLastCount = 0;\r
+\r
+ /* We use the timer 1 counter value to measure the clock cycles between\r
+ the timer 0 interrupts. */\r
+ ulCurrentCount = timerTIMER_1_COUNT_VALUE;\r
+\r
+ if( ulCurrentCount < ulLastCount )\r
+ { \r
+ /* How many times has timer 1 counted since the last interrupt? */\r
+ ulDifference = ulLastCount - ulCurrentCount;\r
+ \r
+ /* Is this the largest difference we have measured yet? */\r
+ if( ulDifference > ulMaxDifference )\r
+ {\r
+ ulMaxDifference = ulDifference;\r
+ ulMaxJitter = ulMaxDifference - timerEXPECTED_DIFFERENCE_VALUE;\r
+ }\r
+ }\r
+ \r
+ ulLastCount = ulCurrentCount;\r
+\r
+ TimerIntClear( TIMER0_BASE, TIMER_TIMA_TIMEOUT );\r
+}\r
+\r
+\r
+\r
+\r
+\r
--- /dev/null
+APP_SOURCES += httpd.c http-strings.c httpd-fs.c httpd-cgi.c\r
--- /dev/null
+/*\r
+ * Copyright (c) 2006, Swedish Institute of Computer Science.\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ * 1. Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the\r
+ * documentation and/or other materials provided with the distribution.\r
+ * 3. Neither the name of the Institute nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND\r
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\r
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\r
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\r
+ * SUCH DAMAGE.\r
+ *\r
+ * This file is part of the uIP TCP/IP stack\r
+ *\r
+ * $Id: clock-arch.h,v 1.2 2006/06/12 08:00:31 adam Exp $\r
+ */\r
+\r
+#ifndef __CLOCK_ARCH_H__\r
+#define __CLOCK_ARCH_H__\r
+\r
+#include "FreeRTOS.h"\r
+\r
+typedef unsigned long clock_time_t;\r
+#define CLOCK_CONF_SECOND configTICK_RATE_HZ\r
+\r
+#endif /* __CLOCK_ARCH_H__ */\r
--- /dev/null
+/*\r
+ FreeRTOS.org V4.3.0 - Copyright (C) 2003-2007 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS.org distribution.\r
+\r
+ FreeRTOS.org is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS.org is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS.org; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS.org, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section\r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license\r
+ and contact details. Please ensure to read the configuration and relevant\r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/* Kernel includes. */\r
+#include "FreeRTOS.h"\r
+#include "Semphr.h"\r
+#include "task.h"\r
+\r
+/* Demo includes. */\r
+#include "EMAC.h"\r
+\r
+/* uIP includes. */\r
+#include "uip.h"\r
+\r
+/* Hardware library includes. */\r
+#include "hw_types.h"\r
+#include "hw_memmap.h"\r
+#include "hw_ints.h"\r
+#include "hw_ethernet.h"\r
+#include "ethernet.h"\r
+#include "interrupt.h"\r
+\r
+#define emacNUM_RX_BUFFERS 5\r
+#define emacFRAM_SIZE_BYTES 2\r
+#define macNEGOTIATE_DELAY 2000\r
+#define macWAIT_SEND_TIME ( 10 )\r
+\r
+/* The task that handles the MAC peripheral. This is created at a high\r
+priority and is effectively a deferred interrupt handler. The peripheral\r
+handling is deferred to a task to prevent the entire FIFO having to be read\r
+from within an ISR. */\r
+void vMACHandleTask( void *pvParameters );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* The semaphore used to wake the uIP task when data arrives. */\r
+xSemaphoreHandle xEMACSemaphore = NULL;\r
+\r
+/* The semaphore used to wake the interrupt handler task. The peripheral\r
+is processed at the task level to prevent the need to read the entire FIFO from\r
+within the ISR itself. */\r
+xSemaphoreHandle xMACInterruptSemaphore = NULL;\r
+\r
+/* The buffer used by the uIP stack. In this case the pointer is used to\r
+point to one of the Rx buffers. */\r
+unsigned portCHAR *uip_buf;\r
+\r
+/* Buffers into which Rx data is placed. */\r
+static unsigned portCHAR ucRxBuffers[ emacNUM_RX_BUFFERS ][ UIP_BUFSIZE + ( 4 * emacFRAM_SIZE_BYTES ) ];\r
+\r
+/* The length of the data within each of the Rx buffers. */\r
+static unsigned portLONG ulRxLength[ emacNUM_RX_BUFFERS ];\r
+\r
+/* Used to keep a track of the number of bytes to transmit. */\r
+static unsigned portLONG ulNextTxSpace;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+portBASE_TYPE vInitEMAC( void )\r
+{\r
+unsigned long ulTemp;\r
+portBASE_TYPE xReturn;\r
+\r
+ /* Ensure all interrupts are disabled. */\r
+ EthernetIntDisable( ETH_BASE, ( ETH_INT_PHY | ETH_INT_MDIO | ETH_INT_RXER | ETH_INT_RXOF | ETH_INT_TX | ETH_INT_TXER | ETH_INT_RX));\r
+\r
+ /* Clear any interrupts that were already pending. */\r
+ ulTemp = EthernetIntStatus( ETH_BASE, pdFALSE );\r
+ EthernetIntClear( ETH_BASE, ulTemp );\r
+\r
+ /* Initialise the MAC and connect. */\r
+ EthernetInit( ETH_BASE );\r
+ EthernetConfigSet( ETH_BASE, ( ETH_CFG_TX_DPLXEN | ETH_CFG_TX_CRCEN | ETH_CFG_TX_PADEN ) );\r
+ EthernetEnable( ETH_BASE );\r
+\r
+ /* Mark each Rx buffer as empty. */\r
+ for( ulTemp = 0; ulTemp < emacNUM_RX_BUFFERS; ulTemp++ )\r
+ {\r
+ ulRxLength[ ulTemp ] = 0;\r
+ }\r
+ \r
+ /* Create the queue and task used to defer the MAC processing to the\r
+ task level. */\r
+ vSemaphoreCreateBinary( xMACInterruptSemaphore );\r
+ xSemaphoreTake( xMACInterruptSemaphore, 0 );\r
+ xReturn = xTaskCreate( vMACHandleTask, ( signed portCHAR * ) "MAC", configMINIMAL_STACK_SIZE, NULL, configMAX_PRIORITIES - 1, NULL );\r
+ vTaskDelay( macNEGOTIATE_DELAY );\r
+ \r
+ /* We are only interested in Rx interrupts. */\r
+ IntPrioritySet( INT_ETH, configKERNEL_INTERRUPT_PRIORITY );\r
+ IntEnable( INT_ETH );\r
+ EthernetIntEnable(ETH_BASE, ETH_INT_RX);\r
+\r
+ return xReturn;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+unsigned int uiGetEMACRxData( unsigned char *ucBuffer )\r
+{\r
+static unsigned long ulNextRxBuffer = 0;\r
+unsigned int iLen;\r
+\r
+ iLen = ulRxLength[ ulNextRxBuffer ];\r
+\r
+ if( iLen != 0 )\r
+ {\r
+ /* Leave room for the size at the start of the buffer. */\r
+ uip_buf = &( ucRxBuffers[ ulNextRxBuffer ][ 2 ] );\r
+ \r
+ ulRxLength[ ulNextRxBuffer ] = 0;\r
+ \r
+ ulNextRxBuffer++;\r
+ if( ulNextRxBuffer >= emacNUM_RX_BUFFERS )\r
+ {\r
+ ulNextRxBuffer = 0;\r
+ }\r
+ }\r
+\r
+ return iLen;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vInitialiseSend( void )\r
+{\r
+ /* Set the index to the first byte to send - skipping over the size\r
+ bytes. */\r
+ ulNextTxSpace = 2;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vIncrementTxLength( unsigned portLONG ulLength )\r
+{\r
+ ulNextTxSpace += ulLength;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vSendBufferToMAC( void )\r
+{\r
+unsigned long *pulSource;\r
+unsigned portSHORT * pus;\r
+unsigned portLONG ulNextWord;\r
+\r
+ /* Locate the data to be send. */\r
+ pus = ( unsigned portSHORT * ) uip_buf;\r
+\r
+ /* Add in the size of the data. */\r
+ pus--;\r
+ *pus = ulNextTxSpace;\r
+\r
+ /* Wait for data to be sent if there is no space immediately. */\r
+ while( !EthernetSpaceAvail( ETH_BASE ) )\r
+ {\r
+ vTaskDelay( macWAIT_SEND_TIME );\r
+ }\r
+ \r
+ pulSource = ( unsigned portLONG * ) pus; \r
+ \r
+ for( ulNextWord = 0; ulNextWord < ulNextTxSpace; ulNextWord += sizeof( unsigned portLONG ) )\r
+ {\r
+ HWREG(ETH_BASE + MAC_O_DATA) = *pulSource;\r
+ pulSource++;\r
+ }\r
+\r
+ /* Go. */\r
+ HWREG( ETH_BASE + MAC_O_TR ) = MAC_TR_NEWTX;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vEMAC_ISR( void )\r
+{\r
+portBASE_TYPE xSwitchRequired = pdFALSE;\r
+unsigned portLONG ulTemp;\r
+\r
+ /* Clear the interrupt. */\r
+ ulTemp = EthernetIntStatus( ETH_BASE, pdFALSE );\r
+ EthernetIntClear( ETH_BASE, ulTemp );\r
+ \r
+ /* Was it an Rx interrupt? */\r
+ if( ulTemp & ETH_INT_RX )\r
+ {\r
+ xSwitchRequired = pdTRUE;\r
+ xSemaphoreGiveFromISR( xMACInterruptSemaphore, pdFALSE );\r
+ EthernetIntDisable( ETH_BASE, ETH_INT_RX );\r
+ }\r
+ \r
+ /* Switch to the uIP task. */\r
+ portEND_SWITCHING_ISR( xSwitchRequired );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vMACHandleTask( void *pvParameters )\r
+{\r
+unsigned long ulLen = 0, i;\r
+unsigned portLONG ulLength, ulInt;\r
+unsigned long *pulBuffer;\r
+static unsigned portLONG ulNextRxBuffer = 0;\r
+portBASE_TYPE xSwitchRequired = pdFALSE;\r
+\r
+ for( ;; )\r
+ {\r
+ /* Wait for something to do. */\r
+ xSemaphoreTake( xMACInterruptSemaphore, portMAX_DELAY );\r
+ \r
+ while( ( ulInt = ( EthernetIntStatus( ETH_BASE, pdFALSE ) & ETH_INT_RX ) ) != 0 )\r
+ { \r
+ ulLength = HWREG( ETH_BASE + MAC_O_DATA );\r
+ \r
+ /* Leave room at the start of the buffer for the size. */\r
+ pulBuffer = ( unsigned long * ) &( ucRxBuffers[ ulNextRxBuffer ][ 2 ] ); \r
+ *pulBuffer = ( ulLength >> 16 );\r
+\r
+ /* Get the size of the data. */ \r
+ pulBuffer = ( unsigned long * ) &( ucRxBuffers[ ulNextRxBuffer ][ 4 ] ); \r
+ ulLength &= 0xFFFF;\r
+ \r
+ if( ulLength > 4 )\r
+ {\r
+ ulLength -= 4;\r
+ \r
+ if( ulLength >= UIP_BUFSIZE )\r
+ {\r
+ /* The data won't fit in our buffer. Ensure we don't\r
+ try to write into the buffer. */\r
+ ulLength = 0;\r
+ }\r
+\r
+ /* Read out the data into our buffer. */\r
+ for( i = 0; i < ulLength; i += sizeof( unsigned portLONG ) )\r
+ {\r
+ *pulBuffer = HWREG( ETH_BASE + MAC_O_DATA );\r
+ pulBuffer++;\r
+ }\r
+ \r
+ /* Store the length of the data into the separate array. */\r
+ ulRxLength[ ulNextRxBuffer ] = ulLength;\r
+ \r
+ /* Use the next buffer the next time through. */\r
+ ulNextRxBuffer++;\r
+ if( ulNextRxBuffer >= emacNUM_RX_BUFFERS )\r
+ {\r
+ ulNextRxBuffer = 0;\r
+ }\r
+ \r
+ /* Ensure the uIP task is not blocked as data has arrived. */\r
+ xSemaphoreGive( xEMACSemaphore );\r
+ }\r
+ }\r
+ \r
+ EthernetIntEnable( ETH_BASE, ETH_INT_RX );\r
+ }\r
+}\r
+\r
--- /dev/null
+/*----------------------------------------------------------------------------\r
+ * LPC2378 Ethernet Definitions\r
+ *----------------------------------------------------------------------------\r
+ * Name: EMAC.H\r
+ * Purpose: Philips LPC2378 EMAC hardware definitions\r
+ *----------------------------------------------------------------------------\r
+ * Copyright (c) 2006 KEIL - An ARM Company. All rights reserved.\r
+ *---------------------------------------------------------------------------*/\r
+#ifndef __EMAC_H\r
+#define __EMAC_H\r
+\r
+/* MAC address definition. The MAC address must be unique on the network. */\r
+#define emacETHADDR0 0\r
+#define emacETHADDR1 0xbd\r
+#define emacETHADDR2 0x33\r
+#define emacETHADDR3 0x02\r
+#define emacETHADDR4 0x64\r
+#define emacETHADDR5 0x24\r
+\r
+\r
+/* EMAC Memory Buffer configuration for 16K Ethernet RAM. */\r
+#define NUM_RX_FRAG 4 /* Num.of RX Fragments 4*1536= 6.0kB */\r
+#define NUM_TX_FRAG 2 /* Num.of TX Fragments 2*1536= 3.0kB */\r
+#define ETH_FRAG_SIZE 1536 /* Packet Fragment size 1536 Bytes */\r
+\r
+#define ETH_MAX_FLEN 1536 /* Max. Ethernet Frame Size */\r
+\r
+/* EMAC variables located in 16K Ethernet SRAM */\r
+#define RX_DESC_BASE 0x7FE00000\r
+#define RX_STAT_BASE (RX_DESC_BASE + NUM_RX_FRAG*8)\r
+#define TX_DESC_BASE (RX_STAT_BASE + NUM_RX_FRAG*8)\r
+#define TX_STAT_BASE (TX_DESC_BASE + NUM_TX_FRAG*8)\r
+#define RX_BUF_BASE (TX_STAT_BASE + NUM_TX_FRAG*4)\r
+#define TX_BUF_BASE (RX_BUF_BASE + NUM_RX_FRAG*ETH_FRAG_SIZE)\r
+\r
+/* RX and TX descriptor and status definitions. */\r
+#define RX_DESC_PACKET(i) (*(unsigned int *)(RX_DESC_BASE + 8*i))\r
+#define RX_DESC_CTRL(i) (*(unsigned int *)(RX_DESC_BASE+4 + 8*i))\r
+#define RX_STAT_INFO(i) (*(unsigned int *)(RX_STAT_BASE + 8*i))\r
+#define RX_STAT_HASHCRC(i) (*(unsigned int *)(RX_STAT_BASE+4 + 8*i))\r
+#define TX_DESC_PACKET(i) (*(unsigned int *)(TX_DESC_BASE + 8*i))\r
+#define TX_DESC_CTRL(i) (*(unsigned int *)(TX_DESC_BASE+4 + 8*i))\r
+#define TX_STAT_INFO(i) (*(unsigned int *)(TX_STAT_BASE + 4*i))\r
+#define RX_BUF(i) (RX_BUF_BASE + ETH_FRAG_SIZE*i)\r
+#define TX_BUF(i) (TX_BUF_BASE + ETH_FRAG_SIZE*i)\r
+\r
+/* MAC Configuration Register 1 */\r
+#define MAC1_REC_EN 0x00000001 /* Receive Enable */\r
+#define MAC1_PASS_ALL 0x00000002 /* Pass All Receive Frames */\r
+#define MAC1_RX_FLOWC 0x00000004 /* RX Flow Control */\r
+#define MAC1_TX_FLOWC 0x00000008 /* TX Flow Control */\r
+#define MAC1_LOOPB 0x00000010 /* Loop Back Mode */\r
+#define MAC1_RES_TX 0x00000100 /* Reset TX Logic */\r
+#define MAC1_RES_MCS_TX 0x00000200 /* Reset MAC TX Control Sublayer */\r
+#define MAC1_RES_RX 0x00000400 /* Reset RX Logic */\r
+#define MAC1_RES_MCS_RX 0x00000800 /* Reset MAC RX Control Sublayer */\r
+#define MAC1_SIM_RES 0x00004000 /* Simulation Reset */\r
+#define MAC1_SOFT_RES 0x00008000 /* Soft Reset MAC */\r
+\r
+/* MAC Configuration Register 2 */\r
+#define MAC2_FULL_DUP 0x00000001 /* Full Duplex Mode */\r
+#define MAC2_FRM_LEN_CHK 0x00000002 /* Frame Length Checking */\r
+#define MAC2_HUGE_FRM_EN 0x00000004 /* Huge Frame Enable */\r
+#define MAC2_DLY_CRC 0x00000008 /* Delayed CRC Mode */\r
+#define MAC2_CRC_EN 0x00000010 /* Append CRC to every Frame */\r
+#define MAC2_PAD_EN 0x00000020 /* Pad all Short Frames */\r
+#define MAC2_VLAN_PAD_EN 0x00000040 /* VLAN Pad Enable */\r
+#define MAC2_ADET_PAD_EN 0x00000080 /* Auto Detect Pad Enable */\r
+#define MAC2_PPREAM_ENF 0x00000100 /* Pure Preamble Enforcement */\r
+#define MAC2_LPREAM_ENF 0x00000200 /* Long Preamble Enforcement */\r
+#undef MAC2_NO_BACKOFF /* Remove compiler warning. */\r
+#define MAC2_NO_BACKOFF 0x00001000 /* No Backoff Algorithm */\r
+#define MAC2_BACK_PRESSURE 0x00002000 /* Backoff Presurre / No Backoff */\r
+#define MAC2_EXCESS_DEF 0x00004000 /* Excess Defer */\r
+\r
+/* Back-to-Back Inter-Packet-Gap Register */\r
+#define IPGT_FULL_DUP 0x00000015 /* Recommended value for Full Duplex */\r
+#define IPGT_HALF_DUP 0x00000012 /* Recommended value for Half Duplex */\r
+\r
+/* Non Back-to-Back Inter-Packet-Gap Register */\r
+#define IPGR_DEF 0x00000012 /* Recommended value */\r
+\r
+/* Collision Window/Retry Register */\r
+#define CLRT_DEF 0x0000370F /* Default value */\r
+\r
+/* PHY Support Register */\r
+#undef SUPP_SPEED /* Remove compiler warning. */\r
+#define SUPP_SPEED 0x00000100 /* Reduced MII Logic Current Speed */\r
+#define SUPP_RES_RMII 0x00000800 /* Reset Reduced MII Logic */\r
+\r
+/* Test Register */\r
+#define TEST_SHCUT_PQUANTA 0x00000001 /* Shortcut Pause Quanta */\r
+#define TEST_TST_PAUSE 0x00000002 /* Test Pause */\r
+#define TEST_TST_BACKP 0x00000004 /* Test Back Pressure */\r
+\r
+/* MII Management Configuration Register */\r
+#define MCFG_SCAN_INC 0x00000001 /* Scan Increment PHY Address */\r
+#define MCFG_SUPP_PREAM 0x00000002 /* Suppress Preamble */\r
+#define MCFG_CLK_SEL 0x0000001C /* Clock Select Mask */\r
+#define MCFG_RES_MII 0x00008000 /* Reset MII Management Hardware */\r
+\r
+/* MII Management Command Register */\r
+#undef MCMD_READ /* Remove compiler warning. */\r
+#define MCMD_READ 0x00000001 /* MII Read */\r
+#undef MCMD_SCAN /* Remove compiler warning. */\r
+#define MCMD_SCAN 0x00000002 /* MII Scan continuously */\r
+\r
+#define MII_WR_TOUT 0x00050000 /* MII Write timeout count */\r
+#define MII_RD_TOUT 0x00050000 /* MII Read timeout count */\r
+\r
+/* MII Management Address Register */\r
+#define MADR_REG_ADR 0x0000001F /* MII Register Address Mask */\r
+#define MADR_PHY_ADR 0x00001F00 /* PHY Address Mask */\r
+\r
+/* MII Management Indicators Register */\r
+#undef MIND_BUSY /* Remove compiler warning. */\r
+#define MIND_BUSY 0x00000001 /* MII is Busy */\r
+#define MIND_SCAN 0x00000002 /* MII Scanning in Progress */\r
+#define MIND_NOT_VAL 0x00000004 /* MII Read Data not valid */\r
+#define MIND_MII_LINK_FAIL 0x00000008 /* MII Link Failed */\r
+\r
+/* Command Register */\r
+#define CR_RX_EN 0x00000001 /* Enable Receive */\r
+#define CR_TX_EN 0x00000002 /* Enable Transmit */\r
+#define CR_REG_RES 0x00000008 /* Reset Host Registers */\r
+#define CR_TX_RES 0x00000010 /* Reset Transmit Datapath */\r
+#define CR_RX_RES 0x00000020 /* Reset Receive Datapath */\r
+#define CR_PASS_RUNT_FRM 0x00000040 /* Pass Runt Frames */\r
+#define CR_PASS_RX_FILT 0x00000080 /* Pass RX Filter */\r
+#define CR_TX_FLOW_CTRL 0x00000100 /* TX Flow Control */\r
+#define CR_RMII 0x00000200 /* Reduced MII Interface */\r
+#define CR_FULL_DUP 0x00000400 /* Full Duplex */\r
+\r
+/* Status Register */\r
+#define SR_RX_EN 0x00000001 /* Enable Receive */\r
+#define SR_TX_EN 0x00000002 /* Enable Transmit */\r
+\r
+/* Transmit Status Vector 0 Register */\r
+#define TSV0_CRC_ERR 0x00000001 /* CRC error */\r
+#define TSV0_LEN_CHKERR 0x00000002 /* Length Check Error */\r
+#define TSV0_LEN_OUTRNG 0x00000004 /* Length Out of Range */\r
+#define TSV0_DONE 0x00000008 /* Tramsmission Completed */\r
+#define TSV0_MCAST 0x00000010 /* Multicast Destination */\r
+#define TSV0_BCAST 0x00000020 /* Broadcast Destination */\r
+#define TSV0_PKT_DEFER 0x00000040 /* Packet Deferred */\r
+#define TSV0_EXC_DEFER 0x00000080 /* Excessive Packet Deferral */\r
+#define TSV0_EXC_COLL 0x00000100 /* Excessive Collision */\r
+#define TSV0_LATE_COLL 0x00000200 /* Late Collision Occured */\r
+#define TSV0_GIANT 0x00000400 /* Giant Frame */\r
+#define TSV0_UNDERRUN 0x00000800 /* Buffer Underrun */\r
+#define TSV0_BYTES 0x0FFFF000 /* Total Bytes Transferred */\r
+#define TSV0_CTRL_FRAME 0x10000000 /* Control Frame */\r
+#define TSV0_PAUSE 0x20000000 /* Pause Frame */\r
+#define TSV0_BACK_PRESS 0x40000000 /* Backpressure Method Applied */\r
+#define TSV0_VLAN 0x80000000 /* VLAN Frame */\r
+\r
+/* Transmit Status Vector 1 Register */\r
+#define TSV1_BYTE_CNT 0x0000FFFF /* Transmit Byte Count */\r
+#define TSV1_COLL_CNT 0x000F0000 /* Transmit Collision Count */\r
+\r
+/* Receive Status Vector Register */\r
+#define RSV_BYTE_CNT 0x0000FFFF /* Receive Byte Count */\r
+#define RSV_PKT_IGNORED 0x00010000 /* Packet Previously Ignored */\r
+#define RSV_RXDV_SEEN 0x00020000 /* RXDV Event Previously Seen */\r
+#define RSV_CARR_SEEN 0x00040000 /* Carrier Event Previously Seen */\r
+#define RSV_REC_CODEV 0x00080000 /* Receive Code Violation */\r
+#define RSV_CRC_ERR 0x00100000 /* CRC Error */\r
+#define RSV_LEN_CHKERR 0x00200000 /* Length Check Error */\r
+#define RSV_LEN_OUTRNG 0x00400000 /* Length Out of Range */\r
+#define RSV_REC_OK 0x00800000 /* Frame Received OK */\r
+#define RSV_MCAST 0x01000000 /* Multicast Frame */\r
+#define RSV_BCAST 0x02000000 /* Broadcast Frame */\r
+#define RSV_DRIB_NIBB 0x04000000 /* Dribble Nibble */\r
+#define RSV_CTRL_FRAME 0x08000000 /* Control Frame */\r
+#define RSV_PAUSE 0x10000000 /* Pause Frame */\r
+#define RSV_UNSUPP_OPC 0x20000000 /* Unsupported Opcode */\r
+#define RSV_VLAN 0x40000000 /* VLAN Frame */\r
+\r
+/* Flow Control Counter Register */\r
+#define FCC_MIRR_CNT 0x0000FFFF /* Mirror Counter */\r
+#define FCC_PAUSE_TIM 0xFFFF0000 /* Pause Timer */\r
+\r
+/* Flow Control Status Register */\r
+#define FCS_MIRR_CNT 0x0000FFFF /* Mirror Counter Current */\r
+\r
+/* Receive Filter Control Register */\r
+#define RFC_UCAST_EN 0x00000001 /* Accept Unicast Frames Enable */\r
+#define RFC_BCAST_EN 0x00000002 /* Accept Broadcast Frames Enable */\r
+#define RFC_MCAST_EN 0x00000004 /* Accept Multicast Frames Enable */\r
+#define RFC_UCAST_HASH_EN 0x00000008 /* Accept Unicast Hash Filter Frames */\r
+#define RFC_MCAST_HASH_EN 0x00000010 /* Accept Multicast Hash Filter Fram.*/\r
+#define RFC_PERFECT_EN 0x00000020 /* Accept Perfect Match Enable */\r
+#define RFC_MAGP_WOL_EN 0x00001000 /* Magic Packet Filter WoL Enable */\r
+#define RFC_PFILT_WOL_EN 0x00002000 /* Perfect Filter WoL Enable */\r
+\r
+/* Receive Filter WoL Status/Clear Registers */\r
+#define WOL_UCAST 0x00000001 /* Unicast Frame caused WoL */\r
+#define WOL_BCAST 0x00000002 /* Broadcast Frame caused WoL */\r
+#define WOL_MCAST 0x00000004 /* Multicast Frame caused WoL */\r
+#define WOL_UCAST_HASH 0x00000008 /* Unicast Hash Filter Frame WoL */\r
+#define WOL_MCAST_HASH 0x00000010 /* Multicast Hash Filter Frame WoL */\r
+#define WOL_PERFECT 0x00000020 /* Perfect Filter WoL */\r
+#define WOL_RX_FILTER 0x00000080 /* RX Filter caused WoL */\r
+#define WOL_MAG_PACKET 0x00000100 /* Magic Packet Filter caused WoL */\r
+\r
+/* Interrupt Status/Enable/Clear/Set Registers */\r
+#define INT_RX_OVERRUN 0x00000001 /* Overrun Error in RX Queue */\r
+#define INT_RX_ERR 0x00000002 /* Receive Error */\r
+#define INT_RX_FIN 0x00000004 /* RX Finished Process Descriptors */\r
+#define INT_RX_DONE 0x00000008 /* Receive Done */\r
+#define INT_TX_UNDERRUN 0x00000010 /* Transmit Underrun */\r
+#define INT_TX_ERR 0x00000020 /* Transmit Error */\r
+#define INT_TX_FIN 0x00000040 /* TX Finished Process Descriptors */\r
+#define INT_TX_DONE 0x00000080 /* Transmit Done */\r
+#define INT_SOFT_INT 0x00001000 /* Software Triggered Interrupt */\r
+#define INT_WAKEUP 0x00002000 /* Wakeup Event Interrupt */\r
+\r
+/* Power Down Register */\r
+#define PD_POWER_DOWN 0x80000000 /* Power Down MAC */\r
+\r
+/* RX Descriptor Control Word */\r
+#define RCTRL_SIZE 0x000007FF /* Buffer size mask */\r
+#define RCTRL_INT 0x80000000 /* Generate RxDone Interrupt */\r
+\r
+/* RX Status Hash CRC Word */\r
+#define RHASH_SA 0x000001FF /* Hash CRC for Source Address */\r
+#define RHASH_DA 0x001FF000 /* Hash CRC for Destination Address */\r
+\r
+/* RX Status Information Word */\r
+#define RINFO_SIZE 0x000007FF /* Data size in bytes */\r
+#define RINFO_CTRL_FRAME 0x00040000 /* Control Frame */\r
+#define RINFO_VLAN 0x00080000 /* VLAN Frame */\r
+#define RINFO_FAIL_FILT 0x00100000 /* RX Filter Failed */\r
+#define RINFO_MCAST 0x00200000 /* Multicast Frame */\r
+#define RINFO_BCAST 0x00400000 /* Broadcast Frame */\r
+#define RINFO_CRC_ERR 0x00800000 /* CRC Error in Frame */\r
+#define RINFO_SYM_ERR 0x01000000 /* Symbol Error from PHY */\r
+#define RINFO_LEN_ERR 0x02000000 /* Length Error */\r
+#define RINFO_RANGE_ERR 0x04000000 /* Range Error (exceeded max. size) */\r
+#define RINFO_ALIGN_ERR 0x08000000 /* Alignment Error */\r
+#define RINFO_OVERRUN 0x10000000 /* Receive overrun */\r
+#define RINFO_NO_DESCR 0x20000000 /* No new Descriptor available */\r
+#define RINFO_LAST_FLAG 0x40000000 /* Last Fragment in Frame */\r
+#define RINFO_ERR 0x80000000 /* Error Occured (OR of all errors) */\r
+\r
+#define RINFO_ERR_MASK (RINFO_FAIL_FILT | RINFO_CRC_ERR | RINFO_SYM_ERR | \\r
+ RINFO_LEN_ERR | RINFO_ALIGN_ERR | RINFO_OVERRUN)\r
+\r
+/* TX Descriptor Control Word */\r
+#define TCTRL_SIZE 0x000007FF /* Size of data buffer in bytes */\r
+#define TCTRL_OVERRIDE 0x04000000 /* Override Default MAC Registers */\r
+#define TCTRL_HUGE 0x08000000 /* Enable Huge Frame */\r
+#define TCTRL_PAD 0x10000000 /* Pad short Frames to 64 bytes */\r
+#define TCTRL_CRC 0x20000000 /* Append a hardware CRC to Frame */\r
+#define TCTRL_LAST 0x40000000 /* Last Descriptor for TX Frame */\r
+#define TCTRL_INT 0x80000000 /* Generate TxDone Interrupt */\r
+\r
+/* TX Status Information Word */\r
+#define TINFO_COL_CNT 0x01E00000 /* Collision Count */\r
+#define TINFO_DEFER 0x02000000 /* Packet Deferred (not an error) */\r
+#define TINFO_EXCESS_DEF 0x04000000 /* Excessive Deferral */\r
+#define TINFO_EXCESS_COL 0x08000000 /* Excessive Collision */\r
+#define TINFO_LATE_COL 0x10000000 /* Late Collision Occured */\r
+#define TINFO_UNDERRUN 0x20000000 /* Transmit Underrun */\r
+#define TINFO_NO_DESCR 0x40000000 /* No new Descriptor available */\r
+#define TINFO_ERR 0x80000000 /* Error Occured (OR of all errors) */\r
+\r
+/* DP83848C PHY Registers */\r
+#define PHY_REG_BMCR 0x00 /* Basic Mode Control Register */\r
+#define PHY_REG_BMSR 0x01 /* Basic Mode Status Register */\r
+#define PHY_REG_IDR1 0x02 /* PHY Identifier 1 */\r
+#define PHY_REG_IDR2 0x03 /* PHY Identifier 2 */\r
+#define PHY_REG_ANAR 0x04 /* Auto-Negotiation Advertisement */\r
+#define PHY_REG_ANLPAR 0x05 /* Auto-Neg. Link Partner Abitily */\r
+#define PHY_REG_ANER 0x06 /* Auto-Neg. Expansion Register */\r
+#define PHY_REG_ANNPTR 0x07 /* Auto-Neg. Next Page TX */\r
+\r
+/* PHY Extended Registers */\r
+#define PHY_REG_STS 0x10 /* Status Register */\r
+#define PHY_REG_MICR 0x11 /* MII Interrupt Control Register */\r
+#define PHY_REG_MISR 0x12 /* MII Interrupt Status Register */\r
+#define PHY_REG_FCSCR 0x14 /* False Carrier Sense Counter */\r
+#define PHY_REG_RECR 0x15 /* Receive Error Counter */\r
+#define PHY_REG_PCSR 0x16 /* PCS Sublayer Config. and Status */\r
+#define PHY_REG_RBR 0x17 /* RMII and Bypass Register */\r
+#define PHY_REG_LEDCR 0x18 /* LED Direct Control Register */\r
+#define PHY_REG_PHYCR 0x19 /* PHY Control Register */\r
+#define PHY_REG_10BTSCR 0x1A /* 10Base-T Status/Control Register */\r
+#define PHY_REG_CDCTRL1 0x1B /* CD Test Control and BIST Extens. */\r
+#define PHY_REG_EDCR 0x1D /* Energy Detect Control Register */\r
+\r
+#define PHY_FULLD_100M 0x2100 /* Full Duplex 100Mbit */\r
+#define PHY_HALFD_100M 0x2000 /* Half Duplex 100Mbit */\r
+#define PHY_FULLD_10M 0x0100 /* Full Duplex 10Mbit */\r
+#define PHY_HALFD_10M 0x0000 /* Half Duplex 10MBit */\r
+#define PHY_AUTO_NEG 0x3000 /* Select Auto Negotiation */\r
+\r
+#define DP83848C_DEF_ADR 0x0100 /* Default PHY device address */\r
+#define DP83848C_ID 0x20005C90 /* PHY Identifier */\r
+\r
+// prototypes\r
+portBASE_TYPE vInitEMAC(void);\r
+unsigned short ReadFrameBE_EMAC(void);\r
+void vIncrementTxLength(unsigned long ulLength);\r
+void CopyFromFrame_EMAC(void *Dest, unsigned short Size);\r
+void DummyReadFrame_EMAC(unsigned short Size);\r
+unsigned short StartReadFrame(void);\r
+void EndReadFrame(void);\r
+unsigned int CheckFrameReceived(void);\r
+void vInitialiseSend(void);\r
+unsigned int Rdy4Tx(void);\r
+void vSendBufferToMAC(void);\r
+void vEMACWaitForInput( void );\r
+unsigned int uiGetEMACRxData( unsigned char *ucBuffer );\r
+\r
+\r
+#endif\r
+\r
+/*----------------------------------------------------------------------------\r
+ * end of file\r
+ *---------------------------------------------------------------------------*/\r
+\r
--- /dev/null
+http_http "http://"\r
+http_200 "200 "\r
+http_301 "301 "\r
+http_302 "302 "\r
+http_get "GET "\r
+http_10 "HTTP/1.0"\r
+http_11 "HTTP/1.1"\r
+http_content_type "content-type: "\r
+http_texthtml "text/html"\r
+http_location "location: "\r
+http_host "host: "\r
+http_crnl "\r\n"\r
+http_index_html "/index.html"\r
+http_404_html "/404.html"\r
+http_referer "Referer:"\r
+http_header_200 "HTTP/1.0 200 OK\r\nServer: uIP/1.0 http://www.sics.se/~adam/uip/\r\nConnection: close\r\n"\r
+http_header_404 "HTTP/1.0 404 Not found\r\nServer: uIP/1.0 http://www.sics.se/~adam/uip/\r\nConnection: close\r\n"\r
+http_content_type_plain "Content-type: text/plain\r\n\r\n"\r
+http_content_type_html "Content-type: text/html\r\n\r\n"\r
+http_content_type_css "Content-type: text/css\r\n\r\n"\r
+http_content_type_text "Content-type: text/text\r\n\r\n"\r
+http_content_type_png "Content-type: image/png\r\n\r\n"\r
+http_content_type_gif "Content-type: image/gif\r\n\r\n"\r
+http_content_type_jpg "Content-type: image/jpeg\r\n\r\n"\r
+http_content_type_binary "Content-type: application/octet-stream\r\n\r\n"\r
+http_html ".html"\r
+http_shtml ".shtml"\r
+http_htm ".htm"\r
+http_css ".css"\r
+http_png ".png"\r
+http_gif ".gif"\r
+http_jpg ".jpg"\r
+http_text ".txt"\r
+http_txt ".txt"\r
+\r
--- /dev/null
+const char http_http[8] = \r
+/* "http://" */\r
+{0x68, 0x74, 0x74, 0x70, 0x3a, 0x2f, 0x2f, };\r
+const char http_200[5] = \r
+/* "200 " */\r
+{0x32, 0x30, 0x30, 0x20, };\r
+const char http_301[5] = \r
+/* "301 " */\r
+{0x33, 0x30, 0x31, 0x20, };\r
+const char http_302[5] = \r
+/* "302 " */\r
+{0x33, 0x30, 0x32, 0x20, };\r
+const char http_get[5] = \r
+/* "GET " */\r
+{0x47, 0x45, 0x54, 0x20, };\r
+const char http_10[9] = \r
+/* "HTTP/1.0" */\r
+{0x48, 0x54, 0x54, 0x50, 0x2f, 0x31, 0x2e, 0x30, };\r
+const char http_11[9] = \r
+/* "HTTP/1.1" */\r
+{0x48, 0x54, 0x54, 0x50, 0x2f, 0x31, 0x2e, 0x31, };\r
+const char http_content_type[15] = \r
+/* "content-type: " */\r
+{0x63, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, };\r
+const char http_texthtml[10] = \r
+/* "text/html" */\r
+{0x74, 0x65, 0x78, 0x74, 0x2f, 0x68, 0x74, 0x6d, 0x6c, };\r
+const char http_location[11] = \r
+/* "location: " */\r
+{0x6c, 0x6f, 0x63, 0x61, 0x74, 0x69, 0x6f, 0x6e, 0x3a, 0x20, };\r
+const char http_host[7] = \r
+/* "host: " */\r
+{0x68, 0x6f, 0x73, 0x74, 0x3a, 0x20, };\r
+const char http_crnl[3] = \r
+/* "\r\n" */\r
+{0xd, 0xa, };\r
+const char http_index_html[12] = \r
+/* "/index.html" */\r
+{0x2f, 0x69, 0x6e, 0x64, 0x65, 0x78, 0x2e, 0x68, 0x74, 0x6d, 0x6c, };\r
+const char http_404_html[10] = \r
+/* "/404.html" */\r
+{0x2f, 0x34, 0x30, 0x34, 0x2e, 0x68, 0x74, 0x6d, 0x6c, };\r
+const char http_referer[9] = \r
+/* "Referer:" */\r
+{0x52, 0x65, 0x66, 0x65, 0x72, 0x65, 0x72, 0x3a, };\r
+const char http_header_200[84] = \r
+/* "HTTP/1.0 200 OK\r\nServer: uIP/1.0 http://www.sics.se/~adam/uip/\r\nConnection: close\r\n" */\r
+{0x48, 0x54, 0x54, 0x50, 0x2f, 0x31, 0x2e, 0x30, 0x20, 0x32, 0x30, 0x30, 0x20, 0x4f, 0x4b, 0xd, 0xa, 0x53, 0x65, 0x72, 0x76, 0x65, 0x72, 0x3a, 0x20, 0x75, 0x49, 0x50, 0x2f, 0x31, 0x2e, 0x30, 0x20, 0x68, 0x74, 0x74, 0x70, 0x3a, 0x2f, 0x2f, 0x77, 0x77, 0x77, 0x2e, 0x73, 0x69, 0x63, 0x73, 0x2e, 0x73, 0x65, 0x2f, 0x7e, 0x61, 0x64, 0x61, 0x6d, 0x2f, 0x75, 0x69, 0x70, 0x2f, 0xd, 0xa, 0x43, 0x6f, 0x6e, 0x6e, 0x65, 0x63, 0x74, 0x69, 0x6f, 0x6e, 0x3a, 0x20, 0x63, 0x6c, 0x6f, 0x73, 0x65, 0xd, 0xa, };\r
+const char http_header_404[91] = \r
+/* "HTTP/1.0 404 Not found\r\nServer: uIP/1.0 http://www.sics.se/~adam/uip/\r\nConnection: close\r\n" */\r
+{0x48, 0x54, 0x54, 0x50, 0x2f, 0x31, 0x2e, 0x30, 0x20, 0x34, 0x30, 0x34, 0x20, 0x4e, 0x6f, 0x74, 0x20, 0x66, 0x6f, 0x75, 0x6e, 0x64, 0xd, 0xa, 0x53, 0x65, 0x72, 0x76, 0x65, 0x72, 0x3a, 0x20, 0x75, 0x49, 0x50, 0x2f, 0x31, 0x2e, 0x30, 0x20, 0x68, 0x74, 0x74, 0x70, 0x3a, 0x2f, 0x2f, 0x77, 0x77, 0x77, 0x2e, 0x73, 0x69, 0x63, 0x73, 0x2e, 0x73, 0x65, 0x2f, 0x7e, 0x61, 0x64, 0x61, 0x6d, 0x2f, 0x75, 0x69, 0x70, 0x2f, 0xd, 0xa, 0x43, 0x6f, 0x6e, 0x6e, 0x65, 0x63, 0x74, 0x69, 0x6f, 0x6e, 0x3a, 0x20, 0x63, 0x6c, 0x6f, 0x73, 0x65, 0xd, 0xa, };\r
+const char http_content_type_plain[29] = \r
+/* "Content-type: text/plain\r\n\r\n" */\r
+{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x74, 0x65, 0x78, 0x74, 0x2f, 0x70, 0x6c, 0x61, 0x69, 0x6e, 0xd, 0xa, 0xd, 0xa, };\r
+const char http_content_type_html[28] = \r
+/* "Content-type: text/html\r\n\r\n" */\r
+{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x74, 0x65, 0x78, 0x74, 0x2f, 0x68, 0x74, 0x6d, 0x6c, 0xd, 0xa, 0xd, 0xa, };\r
+const char http_content_type_css [27] = \r
+/* "Content-type: text/css\r\n\r\n" */\r
+{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x74, 0x65, 0x78, 0x74, 0x2f, 0x63, 0x73, 0x73, 0xd, 0xa, 0xd, 0xa, };\r
+const char http_content_type_text[28] = \r
+/* "Content-type: text/text\r\n\r\n" */\r
+{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x74, 0x65, 0x78, 0x74, 0x2f, 0x74, 0x65, 0x78, 0x74, 0xd, 0xa, 0xd, 0xa, };\r
+const char http_content_type_png [28] = \r
+/* "Content-type: image/png\r\n\r\n" */\r
+{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x69, 0x6d, 0x61, 0x67, 0x65, 0x2f, 0x70, 0x6e, 0x67, 0xd, 0xa, 0xd, 0xa, };\r
+const char http_content_type_gif [28] = \r
+/* "Content-type: image/gif\r\n\r\n" */\r
+{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x69, 0x6d, 0x61, 0x67, 0x65, 0x2f, 0x67, 0x69, 0x66, 0xd, 0xa, 0xd, 0xa, };\r
+const char http_content_type_jpg [29] = \r
+/* "Content-type: image/jpeg\r\n\r\n" */\r
+{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x69, 0x6d, 0x61, 0x67, 0x65, 0x2f, 0x6a, 0x70, 0x65, 0x67, 0xd, 0xa, 0xd, 0xa, };\r
+const char http_content_type_binary[43] = \r
+/* "Content-type: application/octet-stream\r\n\r\n" */\r
+{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x61, 0x70, 0x70, 0x6c, 0x69, 0x63, 0x61, 0x74, 0x69, 0x6f, 0x6e, 0x2f, 0x6f, 0x63, 0x74, 0x65, 0x74, 0x2d, 0x73, 0x74, 0x72, 0x65, 0x61, 0x6d, 0xd, 0xa, 0xd, 0xa, };\r
+const char http_html[6] = \r
+/* ".html" */\r
+{0x2e, 0x68, 0x74, 0x6d, 0x6c, };\r
+const char http_shtml[7] = \r
+/* ".shtml" */\r
+{0x2e, 0x73, 0x68, 0x74, 0x6d, 0x6c, };\r
+const char http_htm[5] = \r
+/* ".htm" */\r
+{0x2e, 0x68, 0x74, 0x6d, };\r
+const char http_css[5] = \r
+/* ".css" */\r
+{0x2e, 0x63, 0x73, 0x73, };\r
+const char http_png[5] = \r
+/* ".png" */\r
+{0x2e, 0x70, 0x6e, 0x67, };\r
+const char http_gif[5] = \r
+/* ".gif" */\r
+{0x2e, 0x67, 0x69, 0x66, };\r
+const char http_jpg[5] = \r
+/* ".jpg" */\r
+{0x2e, 0x6a, 0x70, 0x67, };\r
+const char http_text[5] = \r
+/* ".txt" */\r
+{0x2e, 0x74, 0x78, 0x74, };\r
+const char http_txt[5] = \r
+/* ".txt" */\r
+{0x2e, 0x74, 0x78, 0x74, };\r
--- /dev/null
+extern const char http_http[8];\r
+extern const char http_200[5];\r
+extern const char http_301[5];\r
+extern const char http_302[5];\r
+extern const char http_get[5];\r
+extern const char http_10[9];\r
+extern const char http_11[9];\r
+extern const char http_content_type[15];\r
+extern const char http_texthtml[10];\r
+extern const char http_location[11];\r
+extern const char http_host[7];\r
+extern const char http_crnl[3];\r
+extern const char http_index_html[12];\r
+extern const char http_404_html[10];\r
+extern const char http_referer[9];\r
+extern const char http_header_200[84];\r
+extern const char http_header_404[91];\r
+extern const char http_content_type_plain[29];\r
+extern const char http_content_type_html[28];\r
+extern const char http_content_type_css [27];\r
+extern const char http_content_type_text[28];\r
+extern const char http_content_type_png [28];\r
+extern const char http_content_type_gif [28];\r
+extern const char http_content_type_jpg [29];\r
+extern const char http_content_type_binary[43];\r
+extern const char http_html[6];\r
+extern const char http_shtml[7];\r
+extern const char http_htm[5];\r
+extern const char http_css[5];\r
+extern const char http_png[5];\r
+extern const char http_gif[5];\r
+extern const char http_jpg[5];\r
+extern const char http_text[5];\r
+extern const char http_txt[5];\r
--- /dev/null
+/**\r
+ * \addtogroup httpd\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * \file\r
+ * Web server script interface\r
+ * \author\r
+ * Adam Dunkels <adam@sics.se>\r
+ *\r
+ */\r
+\r
+/*\r
+ * Copyright (c) 2001-2006, Adam Dunkels.\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ * 1. Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the\r
+ * documentation and/or other materials provided with the distribution.\r
+ * 3. The name of the author may not be used to endorse or promote\r
+ * products derived from this software without specific prior\r
+ * written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS\r
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\r
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY\r
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE\r
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\r
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\r
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * This file is part of the uIP TCP/IP stack.\r
+ *\r
+ * $Id: httpd-cgi.c,v 1.2 2006/06/11 21:46:37 adam Exp $\r
+ *\r
+ */\r
+\r
+#include "uip.h"\r
+#include "psock.h"\r
+#include "httpd.h"\r
+#include "httpd-cgi.h"\r
+#include "httpd-fs.h"\r
+\r
+#include <stdio.h>\r
+#include <string.h>\r
+\r
+HTTPD_CGI_CALL(file, "file-stats", file_stats);\r
+HTTPD_CGI_CALL(tcp, "tcp-connections", tcp_stats);\r
+HTTPD_CGI_CALL(net, "net-stats", net_stats);\r
+HTTPD_CGI_CALL(rtos, "rtos-stats", rtos_stats );\r
+HTTPD_CGI_CALL(io, "led-io", led_io );\r
+\r
+\r
+static const struct httpd_cgi_call *calls[] = { &file, &tcp, &net, &rtos, &io, NULL };\r
+\r
+/*---------------------------------------------------------------------------*/\r
+static\r
+PT_THREAD(nullfunction(struct httpd_state *s, char *ptr))\r
+{\r
+ PSOCK_BEGIN(&s->sout);\r
+ PSOCK_END(&s->sout);\r
+}\r
+/*---------------------------------------------------------------------------*/\r
+httpd_cgifunction\r
+httpd_cgi(char *name)\r
+{\r
+ const struct httpd_cgi_call **f;\r
+\r
+ /* Find the matching name in the table, return the function. */\r
+ for(f = calls; *f != NULL; ++f) {\r
+ if(strncmp((*f)->name, name, strlen((*f)->name)) == 0) {\r
+ return (*f)->function;\r
+ }\r
+ }\r
+ return nullfunction;\r
+}\r
+/*---------------------------------------------------------------------------*/\r
+static unsigned short\r
+generate_file_stats(void *arg)\r
+{\r
+ char *f = (char *)arg;\r
+ return snprintf((char *)uip_appdata, UIP_APPDATA_SIZE, "%5u", httpd_fs_count(f));\r
+}\r
+/*---------------------------------------------------------------------------*/\r
+static\r
+PT_THREAD(file_stats(struct httpd_state *s, char *ptr))\r
+{\r
+ PSOCK_BEGIN(&s->sout);\r
+\r
+ PSOCK_GENERATOR_SEND(&s->sout, generate_file_stats, strchr(ptr, ' ') + 1);\r
+\r
+ PSOCK_END(&s->sout);\r
+}\r
+/*---------------------------------------------------------------------------*/\r
+static const char closed[] = /* "CLOSED",*/\r
+{0x43, 0x4c, 0x4f, 0x53, 0x45, 0x44, 0};\r
+static const char syn_rcvd[] = /* "SYN-RCVD",*/\r
+{0x53, 0x59, 0x4e, 0x2d, 0x52, 0x43, 0x56,\r
+ 0x44, 0};\r
+static const char syn_sent[] = /* "SYN-SENT",*/\r
+{0x53, 0x59, 0x4e, 0x2d, 0x53, 0x45, 0x4e,\r
+ 0x54, 0};\r
+static const char established[] = /* "ESTABLISHED",*/\r
+{0x45, 0x53, 0x54, 0x41, 0x42, 0x4c, 0x49, 0x53, 0x48,\r
+ 0x45, 0x44, 0};\r
+static const char fin_wait_1[] = /* "FIN-WAIT-1",*/\r
+{0x46, 0x49, 0x4e, 0x2d, 0x57, 0x41, 0x49,\r
+ 0x54, 0x2d, 0x31, 0};\r
+static const char fin_wait_2[] = /* "FIN-WAIT-2",*/\r
+{0x46, 0x49, 0x4e, 0x2d, 0x57, 0x41, 0x49,\r
+ 0x54, 0x2d, 0x32, 0};\r
+static const char closing[] = /* "CLOSING",*/\r
+{0x43, 0x4c, 0x4f, 0x53, 0x49,\r
+ 0x4e, 0x47, 0};\r
+static const char time_wait[] = /* "TIME-WAIT,"*/\r
+{0x54, 0x49, 0x4d, 0x45, 0x2d, 0x57, 0x41,\r
+ 0x49, 0x54, 0};\r
+static const char last_ack[] = /* "LAST-ACK"*/\r
+{0x4c, 0x41, 0x53, 0x54, 0x2d, 0x41, 0x43,\r
+ 0x4b, 0};\r
+\r
+static const char *states[] = {\r
+ closed,\r
+ syn_rcvd,\r
+ syn_sent,\r
+ established,\r
+ fin_wait_1,\r
+ fin_wait_2,\r
+ closing,\r
+ time_wait,\r
+ last_ack};\r
+\r
+\r
+static unsigned short\r
+generate_tcp_stats(void *arg)\r
+{\r
+ struct uip_conn *conn;\r
+ struct httpd_state *s = (struct httpd_state *)arg;\r
+\r
+ conn = &uip_conns[s->count];\r
+ return snprintf((char *)uip_appdata, UIP_APPDATA_SIZE,\r
+ "<tr><td>%d</td><td>%u.%u.%u.%u:%u</td><td>%s</td><td>%u</td><td>%u</td><td>%c %c</td></tr>\r\n",\r
+ htons(conn->lport),\r
+ htons(conn->ripaddr[0]) >> 8,\r
+ htons(conn->ripaddr[0]) & 0xff,\r
+ htons(conn->ripaddr[1]) >> 8,\r
+ htons(conn->ripaddr[1]) & 0xff,\r
+ htons(conn->rport),\r
+ states[conn->tcpstateflags & UIP_TS_MASK],\r
+ conn->nrtx,\r
+ conn->timer,\r
+ (uip_outstanding(conn))? '*':' ',\r
+ (uip_stopped(conn))? '!':' ');\r
+}\r
+/*---------------------------------------------------------------------------*/\r
+static\r
+PT_THREAD(tcp_stats(struct httpd_state *s, char *ptr))\r
+{\r
+\r
+ PSOCK_BEGIN(&s->sout);\r
+\r
+ for(s->count = 0; s->count < UIP_CONNS; ++s->count) {\r
+ if((uip_conns[s->count].tcpstateflags & UIP_TS_MASK) != UIP_CLOSED) {\r
+ PSOCK_GENERATOR_SEND(&s->sout, generate_tcp_stats, s);\r
+ }\r
+ }\r
+\r
+ PSOCK_END(&s->sout);\r
+}\r
+/*---------------------------------------------------------------------------*/\r
+static unsigned short\r
+generate_net_stats(void *arg)\r
+{\r
+ struct httpd_state *s = (struct httpd_state *)arg;\r
+ return snprintf((char *)uip_appdata, UIP_APPDATA_SIZE,\r
+ "%5u\n", ((uip_stats_t *)&uip_stat)[s->count]);\r
+}\r
+\r
+static\r
+PT_THREAD(net_stats(struct httpd_state *s, char *ptr))\r
+{\r
+ PSOCK_BEGIN(&s->sout);\r
+\r
+#if UIP_STATISTICS\r
+\r
+ for(s->count = 0; s->count < sizeof(uip_stat) / sizeof(uip_stats_t);\r
+ ++s->count) {\r
+ PSOCK_GENERATOR_SEND(&s->sout, generate_net_stats, s);\r
+ }\r
+\r
+#endif /* UIP_STATISTICS */\r
+\r
+ PSOCK_END(&s->sout);\r
+}\r
+/*---------------------------------------------------------------------------*/\r
+\r
+extern void vTaskList( signed char *pcWriteBuffer );\r
+static char cCountBuf[ 32 ];\r
+long lRefreshCount = 0;\r
+static unsigned short\r
+generate_rtos_stats(void *arg)\r
+{\r
+ lRefreshCount++;\r
+ sprintf( cCountBuf, "<p><br>Refresh count = %d", lRefreshCount );\r
+ vTaskList( uip_appdata );\r
+ strcat( uip_appdata, cCountBuf );\r
+\r
+ return strlen( uip_appdata );\r
+}\r
+/*---------------------------------------------------------------------------*/\r
+\r
+\r
+static\r
+PT_THREAD(rtos_stats(struct httpd_state *s, char *ptr))\r
+{\r
+ PSOCK_BEGIN(&s->sout);\r
+ PSOCK_GENERATOR_SEND(&s->sout, generate_rtos_stats, NULL);\r
+ PSOCK_END(&s->sout);\r
+}\r
+/*---------------------------------------------------------------------------*/\r
+\r
+char *pcStatus;\r
+extern unsigned long uxParTestGetLED( unsigned long uxLED );\r
+\r
+static unsigned short generate_io_state( void *arg )\r
+{\r
+ if( uxParTestGetLED( 0 ) )\r
+ {\r
+ pcStatus = "checked";\r
+ }\r
+ else\r
+ {\r
+ pcStatus = "";\r
+ }\r
+\r
+ sprintf( uip_appdata,\r
+ "<input type=\"checkbox\" name=\"LED0\" value=\"1\" %s>LED"\\r
+ "<p>"\\r
+ "<input type=\"text\" name=\"LCD\" value=\"Enter LCD text\" size=\"16\">",\r
+ pcStatus );\r
+\r
+ return strlen( uip_appdata );\r
+}\r
+/*---------------------------------------------------------------------------*/\r
+\r
+static PT_THREAD(led_io(struct httpd_state *s, char *ptr))\r
+{\r
+ PSOCK_BEGIN(&s->sout);\r
+ PSOCK_GENERATOR_SEND(&s->sout, generate_io_state, NULL);\r
+ PSOCK_END(&s->sout);\r
+}\r
+\r
+/** @} */\r
+\r
+\r
+\r
+\r
+\r
+\r
--- /dev/null
+/**\r
+ * \addtogroup httpd\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * \file\r
+ * Web server script interface header file\r
+ * \author\r
+ * Adam Dunkels <adam@sics.se>\r
+ *\r
+ */\r
+\r
+\r
+\r
+/*\r
+ * Copyright (c) 2001, Adam Dunkels.\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ * 1. Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the\r
+ * documentation and/or other materials provided with the distribution.\r
+ * 3. The name of the author may not be used to endorse or promote\r
+ * products derived from this software without specific prior\r
+ * written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS\r
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\r
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY\r
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE\r
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\r
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\r
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * This file is part of the uIP TCP/IP stack.\r
+ *\r
+ * $Id: httpd-cgi.h,v 1.2 2006/06/11 21:46:38 adam Exp $\r
+ *\r
+ */\r
+\r
+#ifndef __HTTPD_CGI_H__\r
+#define __HTTPD_CGI_H__\r
+\r
+#include "psock.h"\r
+#include "httpd.h"\r
+\r
+typedef PT_THREAD((* httpd_cgifunction)(struct httpd_state *, char *));\r
+\r
+httpd_cgifunction httpd_cgi(char *name);\r
+\r
+struct httpd_cgi_call {\r
+ const char *name;\r
+ const httpd_cgifunction function;\r
+};\r
+\r
+/**\r
+ * \brief HTTPD CGI function declaration\r
+ * \param name The C variable name of the function\r
+ * \param str The string name of the function, used in the script file\r
+ * \param function A pointer to the function that implements it\r
+ *\r
+ * This macro is used for declaring a HTTPD CGI\r
+ * function. This function is then added to the list of\r
+ * HTTPD CGI functions with the httpd_cgi_add() function.\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define HTTPD_CGI_CALL(name, str, function) \\r
+static PT_THREAD(function(struct httpd_state *, char *)); \\r
+static const struct httpd_cgi_call name = {str, function}\r
+\r
+void httpd_cgi_init(void);\r
+#endif /* __HTTPD_CGI_H__ */\r
+\r
+/** @} */\r
--- /dev/null
+/*\r
+ * Copyright (c) 2001, Swedish Institute of Computer Science.\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ * 1. Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the\r
+ * documentation and/or other materials provided with the distribution.\r
+ * 3. Neither the name of the Institute nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND\r
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\r
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\r
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\r
+ * SUCH DAMAGE.\r
+ *\r
+ * This file is part of the lwIP TCP/IP stack.\r
+ *\r
+ * Author: Adam Dunkels <adam@sics.se>\r
+ *\r
+ * $Id: httpd-fs.c,v 1.1 2006/06/07 09:13:08 adam Exp $\r
+ */\r
+\r
+#include "httpd.h"\r
+#include "httpd-fs.h"\r
+#include "httpd-fsdata.h"\r
+\r
+#ifndef NULL\r
+#define NULL 0\r
+#endif /* NULL */\r
+\r
+#include "httpd-fsdata.c"\r
+\r
+#if HTTPD_FS_STATISTICS\r
+static u16_t count[HTTPD_FS_NUMFILES];\r
+#endif /* HTTPD_FS_STATISTICS */\r
+\r
+/*-----------------------------------------------------------------------------------*/\r
+static u8_t\r
+httpd_fs_strcmp(const char *str1, const char *str2)\r
+{\r
+ u8_t i;\r
+ i = 0;\r
+ loop:\r
+\r
+ if(str2[i] == 0 ||\r
+ str1[i] == '\r' ||\r
+ str1[i] == '\n') {\r
+ return 0;\r
+ }\r
+\r
+ if(str1[i] != str2[i]) {\r
+ return 1;\r
+ }\r
+\r
+\r
+ ++i;\r
+ goto loop;\r
+}\r
+/*-----------------------------------------------------------------------------------*/\r
+int\r
+httpd_fs_open(const char *name, struct httpd_fs_file *file)\r
+{\r
+#if HTTPD_FS_STATISTICS\r
+ u16_t i = 0;\r
+#endif /* HTTPD_FS_STATISTICS */\r
+ struct httpd_fsdata_file_noconst *f;\r
+\r
+ for(f = (struct httpd_fsdata_file_noconst *)HTTPD_FS_ROOT;\r
+ f != NULL;\r
+ f = (struct httpd_fsdata_file_noconst *)f->next) {\r
+\r
+ if(httpd_fs_strcmp(name, f->name) == 0) {\r
+ file->data = f->data;\r
+ file->len = f->len;\r
+#if HTTPD_FS_STATISTICS\r
+ ++count[i];\r
+#endif /* HTTPD_FS_STATISTICS */\r
+ return 1;\r
+ }\r
+#if HTTPD_FS_STATISTICS\r
+ ++i;\r
+#endif /* HTTPD_FS_STATISTICS */\r
+\r
+ }\r
+ return 0;\r
+}\r
+/*-----------------------------------------------------------------------------------*/\r
+void\r
+httpd_fs_init(void)\r
+{\r
+#if HTTPD_FS_STATISTICS\r
+ u16_t i;\r
+ for(i = 0; i < HTTPD_FS_NUMFILES; i++) {\r
+ count[i] = 0;\r
+ }\r
+#endif /* HTTPD_FS_STATISTICS */\r
+}\r
+/*-----------------------------------------------------------------------------------*/\r
+#if HTTPD_FS_STATISTICS\r
+u16_t httpd_fs_count\r
+(char *name)\r
+{\r
+ struct httpd_fsdata_file_noconst *f;\r
+ u16_t i;\r
+\r
+ i = 0;\r
+ for(f = (struct httpd_fsdata_file_noconst *)HTTPD_FS_ROOT;\r
+ f != NULL;\r
+ f = (struct httpd_fsdata_file_noconst *)f->next) {\r
+\r
+ if(httpd_fs_strcmp(name, f->name) == 0) {\r
+ return count[i];\r
+ }\r
+ ++i;\r
+ }\r
+ return 0;\r
+}\r
+#endif /* HTTPD_FS_STATISTICS */\r
+/*-----------------------------------------------------------------------------------*/\r
--- /dev/null
+/*\r
+ * Copyright (c) 2001, Swedish Institute of Computer Science.\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ * 1. Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the\r
+ * documentation and/or other materials provided with the distribution.\r
+ * 3. Neither the name of the Institute nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND\r
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\r
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\r
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\r
+ * SUCH DAMAGE.\r
+ *\r
+ * This file is part of the lwIP TCP/IP stack.\r
+ *\r
+ * Author: Adam Dunkels <adam@sics.se>\r
+ *\r
+ * $Id: httpd-fs.h,v 1.1 2006/06/07 09:13:08 adam Exp $\r
+ */\r
+#ifndef __HTTPD_FS_H__\r
+#define __HTTPD_FS_H__\r
+\r
+#define HTTPD_FS_STATISTICS 1\r
+\r
+struct httpd_fs_file {\r
+ char *data;\r
+ int len;\r
+};\r
+\r
+/* file must be allocated by caller and will be filled in\r
+ by the function. */\r
+int httpd_fs_open(const char *name, struct httpd_fs_file *file);\r
+\r
+#ifdef HTTPD_FS_STATISTICS\r
+#if HTTPD_FS_STATISTICS == 1\r
+u16_t httpd_fs_count(char *name);\r
+#endif /* HTTPD_FS_STATISTICS */\r
+#endif /* HTTPD_FS_STATISTICS */\r
+\r
+void httpd_fs_init(void);\r
+\r
+#endif /* __HTTPD_FS_H__ */\r
--- /dev/null
+<html>\r
+ <body bgcolor="white">\r
+ <center>\r
+ <h1>404 - file not found</h1>\r
+ <h3>Go <a href="/">here</a> instead.</h3>\r
+ </center>\r
+ </body>\r
+</html>
\ No newline at end of file
--- /dev/null
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">\r
+<html>\r
+ <head>\r
+ <title>FreeRTOS.org uIP WEB server demo</title>\r
+ </head>\r
+ <BODY onLoad="window.setTimeout("location.href='index.shtml'",100)"bgcolor="#CCCCff">\r
+<font face="arial">\r
+Loading index.shtml. Click <a href="index.shtml">here</a> if not automatically redirected.\r
+</font>\r
+</font>\r
+</body>\r
+</html>\r
+\r
--- /dev/null
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">\r
+<html>\r
+ <head>\r
+ <title>FreeRTOS.org uIP WEB server demo</title>\r
+ </head>\r
+ <BODY onLoad="window.setTimeout("location.href='index.shtml'",2000)"bgcolor="#CCCCff">\r
+<font face="arial">\r
+<a href="index.shtml">RTOS Stats</a> <b>|</b> <a href="stats.shtml">TCP Stats</a> <b>|</b> <a href="tcp.shtml">Connections</a> <b>|</b> <a href="http://www.freertos.org/">FreeRTOS.org Homepage</a> <b>|</b> <a href="io.shtml">IO</a>\r
+<br><p>\r
+<hr>\r
+<br><p>\r
+<h2>Task statistics</h2>\r
+Page will refresh every 2 seconds.<p>\r
+<font face="courier"><pre>Task State Priority Stack #<br>************************************************<br>\r
+%! rtos-stats\r
+</pre></font>\r
+</font>\r
+</body>\r
+</html>\r
+\r
--- /dev/null
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">\r
+<html>\r
+ <head>\r
+ <title>FreeRTOS.org uIP WEB server demo</title>\r
+ </head>\r
+ <BODY bgcolor="#CCCCff">\r
+<font face="arial">\r
+<a href="index.shtml">RTOS Stats</a> <b>|</b> <a href="stats.shtml">TCP Stats</a> <b>|</b> <a href="tcp.shtml">Connections</a> <b>|</b> <a href="http://www.freertos.org/">FreeRTOS.org Homepage</a> <b>|</b> <a href="io.shtml">IO</a>\r
+<br><p>\r
+<hr>\r
+<b>LED and LCD IO</b><br>\r
+\r
+<p>\r
+\r
+Use the check box to turn on or off the LED, enter text to display on the OLED display, then click "Update IO".\r
+\r
+\r
+<p>\r
+<form name="aForm" action="/io.shtml" method="get">\r
+%! led-io\r
+<p>\r
+<input type="submit" value="Update IO">\r
+</form>\r
+<br><p>\r
+</font>\r
+</body>\r
+</html>\r
+\r
--- /dev/null
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">\r
+<html>\r
+ <head>\r
+ <title>FreeRTOS.org uIP WEB server demo</title>\r
+ </head>\r
+ <BODY bgcolor="#CCCCff">\r
+<font face="arial">\r
+<a href="index.shtml">RTOS Stats</a> <b>|</b> <a href="stats.shtml">TCP Stats</a> <b>|</b> <a href="tcp.shtml">Connections</a> <b>|</b> <a href="http://www.freertos.org/">FreeRTOS.org Homepage</a> <b>|</b> <a href="io.shtml">IO</a>\r
+<br><p>\r
+<hr>\r
+<br><p>\r
+<h2>Network statistics</h2>\r
+<table width="300" border="0">\r
+<tr><td align="left"><font face="courier"><pre>\r
+IP Packets dropped\r
+ Packets received\r
+ Packets sent\r
+IP errors IP version/header length\r
+ IP length, high byte\r
+ IP length, low byte\r
+ IP fragments\r
+ Header checksum\r
+ Wrong protocol\r
+ICMP Packets dropped\r
+ Packets received\r
+ Packets sent\r
+ Type errors\r
+TCP Packets dropped\r
+ Packets received\r
+ Packets sent\r
+ Checksum errors\r
+ Data packets without ACKs\r
+ Resets\r
+ Retransmissions\r
+ No connection avaliable\r
+ Connection attempts to closed ports\r
+</pre></font></td><td><pre>%! net-stats\r
+</pre></table>\r
+</font>\r
+</body>\r
+</html>\r
--- /dev/null
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">\r
+<html>\r
+ <head>\r
+ <title>FreeRTOS.org uIP WEB server demo</title>\r
+ </head>\r
+ <BODY bgcolor="#CCCCff">\r
+<font face="arial">\r
+<a href="index.shtml">RTOS Stats</a> <b>|</b> <a href="stats.shtml">TCP Stats</a> <b>|</b> <a href="tcp.shtml">Connections</a> <b>|</b> <a href="http://www.freertos.org/">FreeRTOS.org Homepage</a> <b>|</b> <a href="io.shtml">IO</a>\r
+<br><p>\r
+<hr>\r
+<br>\r
+<h2>Network connections</h2>\r
+<p>\r
+<table>\r
+<tr><th>Local</th><th>Remote</th><th>State</th><th>Retransmissions</th><th>Timer</th><th>Flags</th></tr>\r
+%! tcp-connections\r
+</pre></font>\r
+</font>\r
+</body>\r
+</html>\r
+\r
--- /dev/null
+static const unsigned char data_404_html[] = {\r
+ /* /404.html */\r
+ 0x2f, 0x34, 0x30, 0x34, 0x2e, 0x68, 0x74, 0x6d, 0x6c, 0,\r
+ 0x3c, 0x68, 0x74, 0x6d, 0x6c, 0x3e, 0xd, 0xa, 0x20, 0x20, \r
+ 0x3c, 0x62, 0x6f, 0x64, 0x79, 0x20, 0x62, 0x67, 0x63, 0x6f, \r
+ 0x6c, 0x6f, 0x72, 0x3d, 0x22, 0x77, 0x68, 0x69, 0x74, 0x65, \r
+ 0x22, 0x3e, 0xd, 0xa, 0x20, 0x20, 0x20, 0x20, 0x3c, 0x63, \r
+ 0x65, 0x6e, 0x74, 0x65, 0x72, 0x3e, 0xd, 0xa, 0x20, 0x20, \r
+ 0x20, 0x20, 0x20, 0x20, 0x3c, 0x68, 0x31, 0x3e, 0x34, 0x30, \r
+ 0x34, 0x20, 0x2d, 0x20, 0x66, 0x69, 0x6c, 0x65, 0x20, 0x6e, \r
+ 0x6f, 0x74, 0x20, 0x66, 0x6f, 0x75, 0x6e, 0x64, 0x3c, 0x2f, \r
+ 0x68, 0x31, 0x3e, 0xd, 0xa, 0x20, 0x20, 0x20, 0x20, 0x20, \r
+ 0x20, 0x3c, 0x68, 0x33, 0x3e, 0x47, 0x6f, 0x20, 0x3c, 0x61, \r
+ 0x20, 0x68, 0x72, 0x65, 0x66, 0x3d, 0x22, 0x2f, 0x22, 0x3e, \r
+ 0x68, 0x65, 0x72, 0x65, 0x3c, 0x2f, 0x61, 0x3e, 0x20, 0x69, \r
+ 0x6e, 0x73, 0x74, 0x65, 0x61, 0x64, 0x2e, 0x3c, 0x2f, 0x68, \r
+ 0x33, 0x3e, 0xd, 0xa, 0x20, 0x20, 0x20, 0x20, 0x3c, 0x2f, \r
+ 0x63, 0x65, 0x6e, 0x74, 0x65, 0x72, 0x3e, 0xd, 0xa, 0x20, \r
+ 0x20, 0x3c, 0x2f, 0x62, 0x6f, 0x64, 0x79, 0x3e, 0xd, 0xa, \r
+ 0x3c, 0x2f, 0x68, 0x74, 0x6d, 0x6c, 0x3e, 0};\r
+\r
+static const unsigned char data_index_html[] = {\r
+ /* /index.html */\r
+ 0x2f, 0x69, 0x6e, 0x64, 0x65, 0x78, 0x2e, 0x68, 0x74, 0x6d, 0x6c, 0,\r
+ 0x3c, 0x21, 0x44, 0x4f, 0x43, 0x54, 0x59, 0x50, 0x45, 0x20, \r
+ 0x48, 0x54, 0x4d, 0x4c, 0x20, 0x50, 0x55, 0x42, 0x4c, 0x49, \r
+ 0x43, 0x20, 0x22, 0x2d, 0x2f, 0x2f, 0x57, 0x33, 0x43, 0x2f, \r
+ 0x2f, 0x44, 0x54, 0x44, 0x20, 0x48, 0x54, 0x4d, 0x4c, 0x20, \r
+ 0x34, 0x2e, 0x30, 0x31, 0x20, 0x54, 0x72, 0x61, 0x6e, 0x73, \r
+ 0x69, 0x74, 0x69, 0x6f, 0x6e, 0x61, 0x6c, 0x2f, 0x2f, 0x45, \r
+ 0x4e, 0x22, 0x20, 0x22, 0x68, 0x74, 0x74, 0x70, 0x3a, 0x2f, \r
+ 0x2f, 0x77, 0x77, 0x77, 0x2e, 0x77, 0x33, 0x2e, 0x6f, 0x72, \r
+ 0x67, 0x2f, 0x54, 0x52, 0x2f, 0x68, 0x74, 0x6d, 0x6c, 0x34, \r
+ 0x2f, 0x6c, 0x6f, 0x6f, 0x73, 0x65, 0x2e, 0x64, 0x74, 0x64, \r
+ 0x22, 0x3e, 0xd, 0xa, 0x3c, 0x68, 0x74, 0x6d, 0x6c, 0x3e, \r
+ 0xd, 0xa, 0x20, 0x20, 0x3c, 0x68, 0x65, 0x61, 0x64, 0x3e, \r
+ 0xd, 0xa, 0x20, 0x20, 0x20, 0x20, 0x3c, 0x74, 0x69, 0x74, \r
+ 0x6c, 0x65, 0x3e, 0x46, 0x72, 0x65, 0x65, 0x52, 0x54, 0x4f, \r
+ 0x53, 0x2e, 0x6f, 0x72, 0x67, 0x20, 0x75, 0x49, 0x50, 0x20, \r
+ 0x57, 0x45, 0x42, 0x20, 0x73, 0x65, 0x72, 0x76, 0x65, 0x72, \r
+ 0x20, 0x64, 0x65, 0x6d, 0x6f, 0x3c, 0x2f, 0x74, 0x69, 0x74, \r
+ 0x6c, 0x65, 0x3e, 0xd, 0xa, 0x20, 0x20, 0x3c, 0x2f, 0x68, \r
+ 0x65, 0x61, 0x64, 0x3e, 0xd, 0xa, 0x20, 0x20, 0x3c, 0x42, \r
+ 0x4f, 0x44, 0x59, 0x20, 0x6f, 0x6e, 0x4c, 0x6f, 0x61, 0x64, \r
+ 0x3d, 0x22, 0x77, 0x69, 0x6e, 0x64, 0x6f, 0x77, 0x2e, 0x73, \r
+ 0x65, 0x74, 0x54, 0x69, 0x6d, 0x65, 0x6f, 0x75, 0x74, 0x28, \r
+ 0x26, 0x71, 0x75, 0x6f, 0x74, 0x3b, 0x6c, 0x6f, 0x63, 0x61, \r
+ 0x74, 0x69, 0x6f, 0x6e, 0x2e, 0x68, 0x72, 0x65, 0x66, 0x3d, \r
+ 0x27, 0x69, 0x6e, 0x64, 0x65, 0x78, 0x2e, 0x73, 0x68, 0x74, \r
+ 0x6d, 0x6c, 0x27, 0x26, 0x71, 0x75, 0x6f, 0x74, 0x3b, 0x2c, \r
+ 0x31, 0x30, 0x30, 0x29, 0x22, 0x62, 0x67, 0x63, 0x6f, 0x6c, \r
+ 0x6f, 0x72, 0x3d, 0x22, 0x23, 0x43, 0x43, 0x43, 0x43, 0x66, \r
+ 0x66, 0x22, 0x3e, 0xd, 0xa, 0x3c, 0x66, 0x6f, 0x6e, 0x74, \r
+ 0x20, 0x66, 0x61, 0x63, 0x65, 0x3d, 0x22, 0x61, 0x72, 0x69, \r
+ 0x61, 0x6c, 0x22, 0x3e, 0xd, 0xa, 0x4c, 0x6f, 0x61, 0x64, \r
+ 0x69, 0x6e, 0x67, 0x20, 0x69, 0x6e, 0x64, 0x65, 0x78, 0x2e, \r
+ 0x73, 0x68, 0x74, 0x6d, 0x6c, 0x2e, 0x20, 0x20, 0x43, 0x6c, \r
+ 0x69, 0x63, 0x6b, 0x20, 0x3c, 0x61, 0x20, 0x68, 0x72, 0x65, \r
+ 0x66, 0x3d, 0x22, 0x69, 0x6e, 0x64, 0x65, 0x78, 0x2e, 0x73, \r
+ 0x68, 0x74, 0x6d, 0x6c, 0x22, 0x3e, 0x68, 0x65, 0x72, 0x65, \r
+ 0x3c, 0x2f, 0x61, 0x3e, 0x20, 0x69, 0x66, 0x20, 0x6e, 0x6f, \r
+ 0x74, 0x20, 0x61, 0x75, 0x74, 0x6f, 0x6d, 0x61, 0x74, 0x69, \r
+ 0x63, 0x61, 0x6c, 0x6c, 0x79, 0x20, 0x72, 0x65, 0x64, 0x69, \r
+ 0x72, 0x65, 0x63, 0x74, 0x65, 0x64, 0x2e, 0xd, 0xa, 0x3c, \r
+ 0x2f, 0x66, 0x6f, 0x6e, 0x74, 0x3e, 0xd, 0xa, 0x3c, 0x2f, \r
+ 0x66, 0x6f, 0x6e, 0x74, 0x3e, 0xd, 0xa, 0x3c, 0x2f, 0x62, \r
+ 0x6f, 0x64, 0x79, 0x3e, 0xd, 0xa, 0x3c, 0x2f, 0x68, 0x74, \r
+ 0x6d, 0x6c, 0x3e, 0xd, 0xa, 0xd, 0xa, 0};\r
+\r
+static const unsigned char data_index_shtml[] = {\r
+ /* /index.shtml */\r
+ 0x2f, 0x69, 0x6e, 0x64, 0x65, 0x78, 0x2e, 0x73, 0x68, 0x74, 0x6d, 0x6c, 0,\r
+ 0x3c, 0x21, 0x44, 0x4f, 0x43, 0x54, 0x59, 0x50, 0x45, 0x20, \r
+ 0x48, 0x54, 0x4d, 0x4c, 0x20, 0x50, 0x55, 0x42, 0x4c, 0x49, \r
+ 0x43, 0x20, 0x22, 0x2d, 0x2f, 0x2f, 0x57, 0x33, 0x43, 0x2f, \r
+ 0x2f, 0x44, 0x54, 0x44, 0x20, 0x48, 0x54, 0x4d, 0x4c, 0x20, \r
+ 0x34, 0x2e, 0x30, 0x31, 0x20, 0x54, 0x72, 0x61, 0x6e, 0x73, \r
+ 0x69, 0x74, 0x69, 0x6f, 0x6e, 0x61, 0x6c, 0x2f, 0x2f, 0x45, \r
+ 0x4e, 0x22, 0x20, 0x22, 0x68, 0x74, 0x74, 0x70, 0x3a, 0x2f, \r
+ 0x2f, 0x77, 0x77, 0x77, 0x2e, 0x77, 0x33, 0x2e, 0x6f, 0x72, \r
+ 0x67, 0x2f, 0x54, 0x52, 0x2f, 0x68, 0x74, 0x6d, 0x6c, 0x34, \r
+ 0x2f, 0x6c, 0x6f, 0x6f, 0x73, 0x65, 0x2e, 0x64, 0x74, 0x64, \r
+ 0x22, 0x3e, 0xd, 0xa, 0x3c, 0x68, 0x74, 0x6d, 0x6c, 0x3e, \r
+ 0xd, 0xa, 0x20, 0x20, 0x3c, 0x68, 0x65, 0x61, 0x64, 0x3e, \r
+ 0xd, 0xa, 0x20, 0x20, 0x20, 0x20, 0x3c, 0x74, 0x69, 0x74, \r
+ 0x6c, 0x65, 0x3e, 0x46, 0x72, 0x65, 0x65, 0x52, 0x54, 0x4f, \r
+ 0x53, 0x2e, 0x6f, 0x72, 0x67, 0x20, 0x75, 0x49, 0x50, 0x20, \r
+ 0x57, 0x45, 0x42, 0x20, 0x73, 0x65, 0x72, 0x76, 0x65, 0x72, \r
+ 0x20, 0x64, 0x65, 0x6d, 0x6f, 0x3c, 0x2f, 0x74, 0x69, 0x74, \r
+ 0x6c, 0x65, 0x3e, 0xd, 0xa, 0x20, 0x20, 0x3c, 0x2f, 0x68, \r
+ 0x65, 0x61, 0x64, 0x3e, 0xd, 0xa, 0x20, 0x20, 0x3c, 0x42, \r
+ 0x4f, 0x44, 0x59, 0x20, 0x6f, 0x6e, 0x4c, 0x6f, 0x61, 0x64, \r
+ 0x3d, 0x22, 0x77, 0x69, 0x6e, 0x64, 0x6f, 0x77, 0x2e, 0x73, \r
+ 0x65, 0x74, 0x54, 0x69, 0x6d, 0x65, 0x6f, 0x75, 0x74, 0x28, \r
+ 0x26, 0x71, 0x75, 0x6f, 0x74, 0x3b, 0x6c, 0x6f, 0x63, 0x61, \r
+ 0x74, 0x69, 0x6f, 0x6e, 0x2e, 0x68, 0x72, 0x65, 0x66, 0x3d, \r
+ 0x27, 0x69, 0x6e, 0x64, 0x65, 0x78, 0x2e, 0x73, 0x68, 0x74, \r
+ 0x6d, 0x6c, 0x27, 0x26, 0x71, 0x75, 0x6f, 0x74, 0x3b, 0x2c, \r
+ 0x32, 0x30, 0x30, 0x30, 0x29, 0x22, 0x62, 0x67, 0x63, 0x6f, \r
+ 0x6c, 0x6f, 0x72, 0x3d, 0x22, 0x23, 0x43, 0x43, 0x43, 0x43, \r
+ 0x66, 0x66, 0x22, 0x3e, 0xd, 0xa, 0x3c, 0x66, 0x6f, 0x6e, \r
+ 0x74, 0x20, 0x66, 0x61, 0x63, 0x65, 0x3d, 0x22, 0x61, 0x72, \r
+ 0x69, 0x61, 0x6c, 0x22, 0x3e, 0xd, 0xa, 0x3c, 0x61, 0x20, \r
+ 0x68, 0x72, 0x65, 0x66, 0x3d, 0x22, 0x69, 0x6e, 0x64, 0x65, \r
+ 0x78, 0x2e, 0x73, 0x68, 0x74, 0x6d, 0x6c, 0x22, 0x3e, 0x52, \r
+ 0x54, 0x4f, 0x53, 0x20, 0x53, 0x74, 0x61, 0x74, 0x73, 0x3c, \r
+ 0x2f, 0x61, 0x3e, 0x20, 0x3c, 0x62, 0x3e, 0x7c, 0x3c, 0x2f, \r
+ 0x62, 0x3e, 0x20, 0x3c, 0x61, 0x20, 0x68, 0x72, 0x65, 0x66, \r
+ 0x3d, 0x22, 0x73, 0x74, 0x61, 0x74, 0x73, 0x2e, 0x73, 0x68, \r
+ 0x74, 0x6d, 0x6c, 0x22, 0x3e, 0x54, 0x43, 0x50, 0x20, 0x53, \r
+ 0x74, 0x61, 0x74, 0x73, 0x3c, 0x2f, 0x61, 0x3e, 0x20, 0x3c, \r
+ 0x62, 0x3e, 0x7c, 0x3c, 0x2f, 0x62, 0x3e, 0x20, 0x3c, 0x61, \r
+ 0x20, 0x68, 0x72, 0x65, 0x66, 0x3d, 0x22, 0x74, 0x63, 0x70, \r
+ 0x2e, 0x73, 0x68, 0x74, 0x6d, 0x6c, 0x22, 0x3e, 0x43, 0x6f, \r
+ 0x6e, 0x6e, 0x65, 0x63, 0x74, 0x69, 0x6f, 0x6e, 0x73, 0x3c, \r
+ 0x2f, 0x61, 0x3e, 0x20, 0x3c, 0x62, 0x3e, 0x7c, 0x3c, 0x2f, \r
+ 0x62, 0x3e, 0x20, 0x3c, 0x61, 0x20, 0x68, 0x72, 0x65, 0x66, \r
+ 0x3d, 0x22, 0x68, 0x74, 0x74, 0x70, 0x3a, 0x2f, 0x2f, 0x77, \r
+ 0x77, 0x77, 0x2e, 0x66, 0x72, 0x65, 0x65, 0x72, 0x74, 0x6f, \r
+ 0x73, 0x2e, 0x6f, 0x72, 0x67, 0x2f, 0x22, 0x3e, 0x46, 0x72, \r
+ 0x65, 0x65, 0x52, 0x54, 0x4f, 0x53, 0x2e, 0x6f, 0x72, 0x67, \r
+ 0x20, 0x48, 0x6f, 0x6d, 0x65, 0x70, 0x61, 0x67, 0x65, 0x3c, \r
+ 0x2f, 0x61, 0x3e, 0x20, 0x3c, 0x62, 0x3e, 0x7c, 0x3c, 0x2f, \r
+ 0x62, 0x3e, 0x20, 0x3c, 0x61, 0x20, 0x68, 0x72, 0x65, 0x66, \r
+ 0x3d, 0x22, 0x69, 0x6f, 0x2e, 0x73, 0x68, 0x74, 0x6d, 0x6c, \r
+ 0x22, 0x3e, 0x49, 0x4f, 0x3c, 0x2f, 0x61, 0x3e, 0xd, 0xa, \r
+ 0x3c, 0x62, 0x72, 0x3e, 0x3c, 0x70, 0x3e, 0xd, 0xa, 0x3c, \r
+ 0x68, 0x72, 0x3e, 0xd, 0xa, 0x3c, 0x62, 0x72, 0x3e, 0x3c, \r
+ 0x70, 0x3e, 0xd, 0xa, 0x3c, 0x68, 0x32, 0x3e, 0x54, 0x61, \r
+ 0x73, 0x6b, 0x20, 0x73, 0x74, 0x61, 0x74, 0x69, 0x73, 0x74, \r
+ 0x69, 0x63, 0x73, 0x3c, 0x2f, 0x68, 0x32, 0x3e, 0xd, 0xa, \r
+ 0x50, 0x61, 0x67, 0x65, 0x20, 0x77, 0x69, 0x6c, 0x6c, 0x20, \r
+ 0x72, 0x65, 0x66, 0x72, 0x65, 0x73, 0x68, 0x20, 0x65, 0x76, \r
+ 0x65, 0x72, 0x79, 0x20, 0x32, 0x20, 0x73, 0x65, 0x63, 0x6f, \r
+ 0x6e, 0x64, 0x73, 0x2e, 0x3c, 0x70, 0x3e, 0xd, 0xa, 0x3c, \r
+ 0x66, 0x6f, 0x6e, 0x74, 0x20, 0x66, 0x61, 0x63, 0x65, 0x3d, \r
+ 0x22, 0x63, 0x6f, 0x75, 0x72, 0x69, 0x65, 0x72, 0x22, 0x3e, \r
+ 0x3c, 0x70, 0x72, 0x65, 0x3e, 0x54, 0x61, 0x73, 0x6b, 0x20, \r
+ 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x53, \r
+ 0x74, 0x61, 0x74, 0x65, 0x20, 0x20, 0x50, 0x72, 0x69, 0x6f, \r
+ 0x72, 0x69, 0x74, 0x79, 0x20, 0x20, 0x53, 0x74, 0x61, 0x63, \r
+ 0x6b, 0x9, 0x23, 0x3c, 0x62, 0x72, 0x3e, 0x2a, 0x2a, 0x2a, \r
+ 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, \r
+ 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, \r
+ 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, \r
+ 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, \r
+ 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x3c, 0x62, 0x72, 0x3e, 0xd, \r
+ 0xa, 0x25, 0x21, 0x20, 0x72, 0x74, 0x6f, 0x73, 0x2d, 0x73, \r
+ 0x74, 0x61, 0x74, 0x73, 0xd, 0xa, 0x3c, 0x2f, 0x70, 0x72, \r
+ 0x65, 0x3e, 0x3c, 0x2f, 0x66, 0x6f, 0x6e, 0x74, 0x3e, 0xd, \r
+ 0xa, 0x3c, 0x2f, 0x66, 0x6f, 0x6e, 0x74, 0x3e, 0xd, 0xa, \r
+ 0x3c, 0x2f, 0x62, 0x6f, 0x64, 0x79, 0x3e, 0xd, 0xa, 0x3c, \r
+ 0x2f, 0x68, 0x74, 0x6d, 0x6c, 0x3e, 0xd, 0xa, 0xd, 0xa, \r
+0};\r
+\r
+static const unsigned char data_io_shtml[] = {\r
+ /* /io.shtml */\r
+ 0x2f, 0x69, 0x6f, 0x2e, 0x73, 0x68, 0x74, 0x6d, 0x6c, 0,\r
+ 0x3c, 0x21, 0x44, 0x4f, 0x43, 0x54, 0x59, 0x50, 0x45, 0x20, \r
+ 0x48, 0x54, 0x4d, 0x4c, 0x20, 0x50, 0x55, 0x42, 0x4c, 0x49, \r
+ 0x43, 0x20, 0x22, 0x2d, 0x2f, 0x2f, 0x57, 0x33, 0x43, 0x2f, \r
+ 0x2f, 0x44, 0x54, 0x44, 0x20, 0x48, 0x54, 0x4d, 0x4c, 0x20, \r
+ 0x34, 0x2e, 0x30, 0x31, 0x20, 0x54, 0x72, 0x61, 0x6e, 0x73, \r
+ 0x69, 0x74, 0x69, 0x6f, 0x6e, 0x61, 0x6c, 0x2f, 0x2f, 0x45, \r
+ 0x4e, 0x22, 0x20, 0x22, 0x68, 0x74, 0x74, 0x70, 0x3a, 0x2f, \r
+ 0x2f, 0x77, 0x77, 0x77, 0x2e, 0x77, 0x33, 0x2e, 0x6f, 0x72, \r
+ 0x67, 0x2f, 0x54, 0x52, 0x2f, 0x68, 0x74, 0x6d, 0x6c, 0x34, \r
+ 0x2f, 0x6c, 0x6f, 0x6f, 0x73, 0x65, 0x2e, 0x64, 0x74, 0x64, \r
+ 0x22, 0x3e, 0xd, 0xa, 0x3c, 0x68, 0x74, 0x6d, 0x6c, 0x3e, \r
+ 0xd, 0xa, 0x20, 0x20, 0x3c, 0x68, 0x65, 0x61, 0x64, 0x3e, \r
+ 0xd, 0xa, 0x20, 0x20, 0x20, 0x20, 0x3c, 0x74, 0x69, 0x74, \r
+ 0x6c, 0x65, 0x3e, 0x46, 0x72, 0x65, 0x65, 0x52, 0x54, 0x4f, \r
+ 0x53, 0x2e, 0x6f, 0x72, 0x67, 0x20, 0x75, 0x49, 0x50, 0x20, \r
+ 0x57, 0x45, 0x42, 0x20, 0x73, 0x65, 0x72, 0x76, 0x65, 0x72, \r
+ 0x20, 0x64, 0x65, 0x6d, 0x6f, 0x3c, 0x2f, 0x74, 0x69, 0x74, \r
+ 0x6c, 0x65, 0x3e, 0xd, 0xa, 0x20, 0x20, 0x3c, 0x2f, 0x68, \r
+ 0x65, 0x61, 0x64, 0x3e, 0xd, 0xa, 0x20, 0x20, 0x3c, 0x42, \r
+ 0x4f, 0x44, 0x59, 0x20, 0x62, 0x67, 0x63, 0x6f, 0x6c, 0x6f, \r
+ 0x72, 0x3d, 0x22, 0x23, 0x43, 0x43, 0x43, 0x43, 0x66, 0x66, \r
+ 0x22, 0x3e, 0xd, 0xa, 0x3c, 0x66, 0x6f, 0x6e, 0x74, 0x20, \r
+ 0x66, 0x61, 0x63, 0x65, 0x3d, 0x22, 0x61, 0x72, 0x69, 0x61, \r
+ 0x6c, 0x22, 0x3e, 0xd, 0xa, 0x3c, 0x61, 0x20, 0x68, 0x72, \r
+ 0x65, 0x66, 0x3d, 0x22, 0x69, 0x6e, 0x64, 0x65, 0x78, 0x2e, \r
+ 0x73, 0x68, 0x74, 0x6d, 0x6c, 0x22, 0x3e, 0x52, 0x54, 0x4f, \r
+ 0x53, 0x20, 0x53, 0x74, 0x61, 0x74, 0x73, 0x3c, 0x2f, 0x61, \r
+ 0x3e, 0x20, 0x3c, 0x62, 0x3e, 0x7c, 0x3c, 0x2f, 0x62, 0x3e, \r
+ 0x20, 0x3c, 0x61, 0x20, 0x68, 0x72, 0x65, 0x66, 0x3d, 0x22, \r
+ 0x73, 0x74, 0x61, 0x74, 0x73, 0x2e, 0x73, 0x68, 0x74, 0x6d, \r
+ 0x6c, 0x22, 0x3e, 0x54, 0x43, 0x50, 0x20, 0x53, 0x74, 0x61, \r
+ 0x74, 0x73, 0x3c, 0x2f, 0x61, 0x3e, 0x20, 0x3c, 0x62, 0x3e, \r
+ 0x7c, 0x3c, 0x2f, 0x62, 0x3e, 0x20, 0x3c, 0x61, 0x20, 0x68, \r
+ 0x72, 0x65, 0x66, 0x3d, 0x22, 0x74, 0x63, 0x70, 0x2e, 0x73, \r
+ 0x68, 0x74, 0x6d, 0x6c, 0x22, 0x3e, 0x43, 0x6f, 0x6e, 0x6e, \r
+ 0x65, 0x63, 0x74, 0x69, 0x6f, 0x6e, 0x73, 0x3c, 0x2f, 0x61, \r
+ 0x3e, 0x20, 0x3c, 0x62, 0x3e, 0x7c, 0x3c, 0x2f, 0x62, 0x3e, \r
+ 0x20, 0x3c, 0x61, 0x20, 0x68, 0x72, 0x65, 0x66, 0x3d, 0x22, \r
+ 0x68, 0x74, 0x74, 0x70, 0x3a, 0x2f, 0x2f, 0x77, 0x77, 0x77, \r
+ 0x2e, 0x66, 0x72, 0x65, 0x65, 0x72, 0x74, 0x6f, 0x73, 0x2e, \r
+ 0x6f, 0x72, 0x67, 0x2f, 0x22, 0x3e, 0x46, 0x72, 0x65, 0x65, \r
+ 0x52, 0x54, 0x4f, 0x53, 0x2e, 0x6f, 0x72, 0x67, 0x20, 0x48, \r
+ 0x6f, 0x6d, 0x65, 0x70, 0x61, 0x67, 0x65, 0x3c, 0x2f, 0x61, \r
+ 0x3e, 0x20, 0x3c, 0x62, 0x3e, 0x7c, 0x3c, 0x2f, 0x62, 0x3e, \r
+ 0x20, 0x3c, 0x61, 0x20, 0x68, 0x72, 0x65, 0x66, 0x3d, 0x22, \r
+ 0x69, 0x6f, 0x2e, 0x73, 0x68, 0x74, 0x6d, 0x6c, 0x22, 0x3e, \r
+ 0x49, 0x4f, 0x3c, 0x2f, 0x61, 0x3e, 0xd, 0xa, 0x3c, 0x62, \r
+ 0x72, 0x3e, 0x3c, 0x70, 0x3e, 0xd, 0xa, 0x3c, 0x68, 0x72, \r
+ 0x3e, 0xd, 0xa, 0x3c, 0x62, 0x3e, 0x4c, 0x45, 0x44, 0x20, \r
+ 0x61, 0x6e, 0x64, 0x20, 0x4c, 0x43, 0x44, 0x20, 0x49, 0x4f, \r
+ 0x3c, 0x2f, 0x62, 0x3e, 0x3c, 0x62, 0x72, 0x3e, 0xd, 0xa, \r
+ 0xd, 0xa, 0x3c, 0x70, 0x3e, 0xd, 0xa, 0xd, 0xa, 0x55, \r
+ 0x73, 0x65, 0x20, 0x74, 0x68, 0x65, 0x20, 0x63, 0x68, 0x65, \r
+ 0x63, 0x6b, 0x20, 0x62, 0x6f, 0x78, 0x20, 0x74, 0x6f, 0x20, \r
+ 0x74, 0x75, 0x72, 0x6e, 0x20, 0x6f, 0x6e, 0x20, 0x6f, 0x72, \r
+ 0x20, 0x6f, 0x66, 0x66, 0x20, 0x74, 0x68, 0x65, 0x20, 0x4c, \r
+ 0x45, 0x44, 0x2c, 0x20, 0x65, 0x6e, 0x74, 0x65, 0x72, 0x20, \r
+ 0x74, 0x65, 0x78, 0x74, 0x20, 0x74, 0x6f, 0x20, 0x64, 0x69, \r
+ 0x73, 0x70, 0x6c, 0x61, 0x79, 0x20, 0x6f, 0x6e, 0x20, 0x74, \r
+ 0x68, 0x65, 0x20, 0x4f, 0x4c, 0x45, 0x44, 0x20, 0x64, 0x69, \r
+ 0x73, 0x70, 0x6c, 0x61, 0x79, 0x2c, 0x20, 0x74, 0x68, 0x65, \r
+ 0x6e, 0x20, 0x63, 0x6c, 0x69, 0x63, 0x6b, 0x20, 0x22, 0x55, \r
+ 0x70, 0x64, 0x61, 0x74, 0x65, 0x20, 0x49, 0x4f, 0x22, 0x2e, \r
+ 0xd, 0xa, 0xd, 0xa, 0xd, 0xa, 0x3c, 0x70, 0x3e, 0xd, \r
+ 0xa, 0x3c, 0x66, 0x6f, 0x72, 0x6d, 0x20, 0x6e, 0x61, 0x6d, \r
+ 0x65, 0x3d, 0x22, 0x61, 0x46, 0x6f, 0x72, 0x6d, 0x22, 0x20, \r
+ 0x61, 0x63, 0x74, 0x69, 0x6f, 0x6e, 0x3d, 0x22, 0x2f, 0x69, \r
+ 0x6f, 0x2e, 0x73, 0x68, 0x74, 0x6d, 0x6c, 0x22, 0x20, 0x6d, \r
+ 0x65, 0x74, 0x68, 0x6f, 0x64, 0x3d, 0x22, 0x67, 0x65, 0x74, \r
+ 0x22, 0x3e, 0xd, 0xa, 0x25, 0x21, 0x20, 0x6c, 0x65, 0x64, \r
+ 0x2d, 0x69, 0x6f, 0xd, 0xa, 0x3c, 0x70, 0x3e, 0xd, 0xa, \r
+ 0x3c, 0x69, 0x6e, 0x70, 0x75, 0x74, 0x20, 0x74, 0x79, 0x70, \r
+ 0x65, 0x3d, 0x22, 0x73, 0x75, 0x62, 0x6d, 0x69, 0x74, 0x22, \r
+ 0x20, 0x76, 0x61, 0x6c, 0x75, 0x65, 0x3d, 0x22, 0x55, 0x70, \r
+ 0x64, 0x61, 0x74, 0x65, 0x20, 0x49, 0x4f, 0x22, 0x3e, 0xd, \r
+ 0xa, 0x3c, 0x2f, 0x66, 0x6f, 0x72, 0x6d, 0x3e, 0xd, 0xa, \r
+ 0x3c, 0x62, 0x72, 0x3e, 0x3c, 0x70, 0x3e, 0xd, 0xa, 0x3c, \r
+ 0x2f, 0x66, 0x6f, 0x6e, 0x74, 0x3e, 0xd, 0xa, 0x3c, 0x2f, \r
+ 0x62, 0x6f, 0x64, 0x79, 0x3e, 0xd, 0xa, 0x3c, 0x2f, 0x68, \r
+ 0x74, 0x6d, 0x6c, 0x3e, 0xd, 0xa, 0xd, 0xa, 0};\r
+\r
+static const unsigned char data_stats_shtml[] = {\r
+ /* /stats.shtml */\r
+ 0x2f, 0x73, 0x74, 0x61, 0x74, 0x73, 0x2e, 0x73, 0x68, 0x74, 0x6d, 0x6c, 0,\r
+ 0x3c, 0x21, 0x44, 0x4f, 0x43, 0x54, 0x59, 0x50, 0x45, 0x20, \r
+ 0x48, 0x54, 0x4d, 0x4c, 0x20, 0x50, 0x55, 0x42, 0x4c, 0x49, \r
+ 0x43, 0x20, 0x22, 0x2d, 0x2f, 0x2f, 0x57, 0x33, 0x43, 0x2f, \r
+ 0x2f, 0x44, 0x54, 0x44, 0x20, 0x48, 0x54, 0x4d, 0x4c, 0x20, \r
+ 0x34, 0x2e, 0x30, 0x31, 0x20, 0x54, 0x72, 0x61, 0x6e, 0x73, \r
+ 0x69, 0x74, 0x69, 0x6f, 0x6e, 0x61, 0x6c, 0x2f, 0x2f, 0x45, \r
+ 0x4e, 0x22, 0x20, 0x22, 0x68, 0x74, 0x74, 0x70, 0x3a, 0x2f, \r
+ 0x2f, 0x77, 0x77, 0x77, 0x2e, 0x77, 0x33, 0x2e, 0x6f, 0x72, \r
+ 0x67, 0x2f, 0x54, 0x52, 0x2f, 0x68, 0x74, 0x6d, 0x6c, 0x34, \r
+ 0x2f, 0x6c, 0x6f, 0x6f, 0x73, 0x65, 0x2e, 0x64, 0x74, 0x64, \r
+ 0x22, 0x3e, 0xd, 0xa, 0x3c, 0x68, 0x74, 0x6d, 0x6c, 0x3e, \r
+ 0xd, 0xa, 0x20, 0x20, 0x3c, 0x68, 0x65, 0x61, 0x64, 0x3e, \r
+ 0xd, 0xa, 0x20, 0x20, 0x20, 0x20, 0x3c, 0x74, 0x69, 0x74, \r
+ 0x6c, 0x65, 0x3e, 0x46, 0x72, 0x65, 0x65, 0x52, 0x54, 0x4f, \r
+ 0x53, 0x2e, 0x6f, 0x72, 0x67, 0x20, 0x75, 0x49, 0x50, 0x20, \r
+ 0x57, 0x45, 0x42, 0x20, 0x73, 0x65, 0x72, 0x76, 0x65, 0x72, \r
+ 0x20, 0x64, 0x65, 0x6d, 0x6f, 0x3c, 0x2f, 0x74, 0x69, 0x74, \r
+ 0x6c, 0x65, 0x3e, 0xd, 0xa, 0x20, 0x20, 0x3c, 0x2f, 0x68, \r
+ 0x65, 0x61, 0x64, 0x3e, 0xd, 0xa, 0x20, 0x20, 0x3c, 0x42, \r
+ 0x4f, 0x44, 0x59, 0x20, 0x62, 0x67, 0x63, 0x6f, 0x6c, 0x6f, \r
+ 0x72, 0x3d, 0x22, 0x23, 0x43, 0x43, 0x43, 0x43, 0x66, 0x66, \r
+ 0x22, 0x3e, 0xd, 0xa, 0x3c, 0x66, 0x6f, 0x6e, 0x74, 0x20, \r
+ 0x66, 0x61, 0x63, 0x65, 0x3d, 0x22, 0x61, 0x72, 0x69, 0x61, \r
+ 0x6c, 0x22, 0x3e, 0xd, 0xa, 0x3c, 0x61, 0x20, 0x68, 0x72, \r
+ 0x65, 0x66, 0x3d, 0x22, 0x69, 0x6e, 0x64, 0x65, 0x78, 0x2e, \r
+ 0x73, 0x68, 0x74, 0x6d, 0x6c, 0x22, 0x3e, 0x52, 0x54, 0x4f, \r
+ 0x53, 0x20, 0x53, 0x74, 0x61, 0x74, 0x73, 0x3c, 0x2f, 0x61, \r
+ 0x3e, 0x20, 0x3c, 0x62, 0x3e, 0x7c, 0x3c, 0x2f, 0x62, 0x3e, \r
+ 0x20, 0x3c, 0x61, 0x20, 0x68, 0x72, 0x65, 0x66, 0x3d, 0x22, \r
+ 0x73, 0x74, 0x61, 0x74, 0x73, 0x2e, 0x73, 0x68, 0x74, 0x6d, \r
+ 0x6c, 0x22, 0x3e, 0x54, 0x43, 0x50, 0x20, 0x53, 0x74, 0x61, \r
+ 0x74, 0x73, 0x3c, 0x2f, 0x61, 0x3e, 0x20, 0x3c, 0x62, 0x3e, \r
+ 0x7c, 0x3c, 0x2f, 0x62, 0x3e, 0x20, 0x3c, 0x61, 0x20, 0x68, \r
+ 0x72, 0x65, 0x66, 0x3d, 0x22, 0x74, 0x63, 0x70, 0x2e, 0x73, \r
+ 0x68, 0x74, 0x6d, 0x6c, 0x22, 0x3e, 0x43, 0x6f, 0x6e, 0x6e, \r
+ 0x65, 0x63, 0x74, 0x69, 0x6f, 0x6e, 0x73, 0x3c, 0x2f, 0x61, \r
+ 0x3e, 0x20, 0x3c, 0x62, 0x3e, 0x7c, 0x3c, 0x2f, 0x62, 0x3e, \r
+ 0x20, 0x3c, 0x61, 0x20, 0x68, 0x72, 0x65, 0x66, 0x3d, 0x22, \r
+ 0x68, 0x74, 0x74, 0x70, 0x3a, 0x2f, 0x2f, 0x77, 0x77, 0x77, \r
+ 0x2e, 0x66, 0x72, 0x65, 0x65, 0x72, 0x74, 0x6f, 0x73, 0x2e, \r
+ 0x6f, 0x72, 0x67, 0x2f, 0x22, 0x3e, 0x46, 0x72, 0x65, 0x65, \r
+ 0x52, 0x54, 0x4f, 0x53, 0x2e, 0x6f, 0x72, 0x67, 0x20, 0x48, \r
+ 0x6f, 0x6d, 0x65, 0x70, 0x61, 0x67, 0x65, 0x3c, 0x2f, 0x61, \r
+ 0x3e, 0x20, 0x3c, 0x62, 0x3e, 0x7c, 0x3c, 0x2f, 0x62, 0x3e, \r
+ 0x20, 0x3c, 0x61, 0x20, 0x68, 0x72, 0x65, 0x66, 0x3d, 0x22, \r
+ 0x69, 0x6f, 0x2e, 0x73, 0x68, 0x74, 0x6d, 0x6c, 0x22, 0x3e, \r
+ 0x49, 0x4f, 0x3c, 0x2f, 0x61, 0x3e, 0xd, 0xa, 0x3c, 0x62, \r
+ 0x72, 0x3e, 0x3c, 0x70, 0x3e, 0xd, 0xa, 0x3c, 0x68, 0x72, \r
+ 0x3e, 0xd, 0xa, 0x3c, 0x62, 0x72, 0x3e, 0x3c, 0x70, 0x3e, \r
+ 0xd, 0xa, 0x3c, 0x68, 0x32, 0x3e, 0x4e, 0x65, 0x74, 0x77, \r
+ 0x6f, 0x72, 0x6b, 0x20, 0x73, 0x74, 0x61, 0x74, 0x69, 0x73, \r
+ 0x74, 0x69, 0x63, 0x73, 0x3c, 0x2f, 0x68, 0x32, 0x3e, 0xd, \r
+ 0xa, 0x3c, 0x74, 0x61, 0x62, 0x6c, 0x65, 0x20, 0x77, 0x69, \r
+ 0x64, 0x74, 0x68, 0x3d, 0x22, 0x33, 0x30, 0x30, 0x22, 0x20, \r
+ 0x62, 0x6f, 0x72, 0x64, 0x65, 0x72, 0x3d, 0x22, 0x30, 0x22, \r
+ 0x3e, 0xd, 0xa, 0x3c, 0x74, 0x72, 0x3e, 0x3c, 0x74, 0x64, \r
+ 0x20, 0x61, 0x6c, 0x69, 0x67, 0x6e, 0x3d, 0x22, 0x6c, 0x65, \r
+ 0x66, 0x74, 0x22, 0x3e, 0x3c, 0x66, 0x6f, 0x6e, 0x74, 0x20, \r
+ 0x66, 0x61, 0x63, 0x65, 0x3d, 0x22, 0x63, 0x6f, 0x75, 0x72, \r
+ 0x69, 0x65, 0x72, 0x22, 0x3e, 0x3c, 0x70, 0x72, 0x65, 0x3e, \r
+ 0xd, 0xa, 0x49, 0x50, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, \r
+ 0x20, 0x20, 0x20, 0x20, 0x20, 0x50, 0x61, 0x63, 0x6b, 0x65, \r
+ 0x74, 0x73, 0x20, 0x64, 0x72, 0x6f, 0x70, 0x70, 0x65, 0x64, \r
+ 0xd, 0xa, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, \r
+ 0x20, 0x20, 0x20, 0x20, 0x20, 0x50, 0x61, 0x63, 0x6b, 0x65, \r
+ 0x74, 0x73, 0x20, 0x72, 0x65, 0x63, 0x65, 0x69, 0x76, 0x65, \r
+ 0x64, 0xd, 0xa, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, \r
+ 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x50, 0x61, 0x63, 0x6b, \r
+ 0x65, 0x74, 0x73, 0x20, 0x73, 0x65, 0x6e, 0x74, 0xd, 0xa, \r
+ 0x49, 0x50, 0x20, 0x65, 0x72, 0x72, 0x6f, 0x72, 0x73, 0x20, \r
+ 0x20, 0x20, 0x20, 0x49, 0x50, 0x20, 0x76, 0x65, 0x72, 0x73, \r
+ 0x69, 0x6f, 0x6e, 0x2f, 0x68, 0x65, 0x61, 0x64, 0x65, 0x72, \r
+ 0x20, 0x6c, 0x65, 0x6e, 0x67, 0x74, 0x68, 0xd, 0xa, 0x20, \r
+ 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, \r
+ 0x20, 0x20, 0x49, 0x50, 0x20, 0x6c, 0x65, 0x6e, 0x67, 0x74, \r
+ 0x68, 0x2c, 0x20, 0x68, 0x69, 0x67, 0x68, 0x20, 0x62, 0x79, \r
+ 0x74, 0x65, 0xd, 0xa, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, \r
+ 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x49, 0x50, 0x20, \r
+ 0x6c, 0x65, 0x6e, 0x67, 0x74, 0x68, 0x2c, 0x20, 0x6c, 0x6f, \r
+ 0x77, 0x20, 0x62, 0x79, 0x74, 0x65, 0xd, 0xa, 0x20, 0x20, \r
+ 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, \r
+ 0x20, 0x49, 0x50, 0x20, 0x66, 0x72, 0x61, 0x67, 0x6d, 0x65, \r
+ 0x6e, 0x74, 0x73, 0xd, 0xa, 0x20, 0x20, 0x20, 0x20, 0x20, \r
+ 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x48, 0x65, \r
+ 0x61, 0x64, 0x65, 0x72, 0x20, 0x63, 0x68, 0x65, 0x63, 0x6b, \r
+ 0x73, 0x75, 0x6d, 0xd, 0xa, 0x20, 0x20, 0x20, 0x20, 0x20, \r
+ 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x57, 0x72, \r
+ 0x6f, 0x6e, 0x67, 0x20, 0x70, 0x72, 0x6f, 0x74, 0x6f, 0x63, \r
+ 0x6f, 0x6c, 0xd, 0xa, 0x49, 0x43, 0x4d, 0x50, 0x9, 0x20, \r
+ 0x20, 0x20, 0x20, 0x20, 0x50, 0x61, 0x63, 0x6b, 0x65, 0x74, \r
+ 0x73, 0x20, 0x64, 0x72, 0x6f, 0x70, 0x70, 0x65, 0x64, 0xd, \r
+ 0xa, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, \r
+ 0x20, 0x20, 0x20, 0x20, 0x50, 0x61, 0x63, 0x6b, 0x65, 0x74, \r
+ 0x73, 0x20, 0x72, 0x65, 0x63, 0x65, 0x69, 0x76, 0x65, 0x64, \r
+ 0xd, 0xa, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, \r
+ 0x20, 0x20, 0x20, 0x20, 0x20, 0x50, 0x61, 0x63, 0x6b, 0x65, \r
+ 0x74, 0x73, 0x20, 0x73, 0x65, 0x6e, 0x74, 0xd, 0xa, 0x20, \r
+ 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, \r
+ 0x20, 0x20, 0x54, 0x79, 0x70, 0x65, 0x20, 0x65, 0x72, 0x72, \r
+ 0x6f, 0x72, 0x73, 0xd, 0xa, 0x54, 0x43, 0x50, 0x20, 0x20, \r
+ 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x50, 0x61, \r
+ 0x63, 0x6b, 0x65, 0x74, 0x73, 0x20, 0x64, 0x72, 0x6f, 0x70, \r
+ 0x70, 0x65, 0x64, 0xd, 0xa, 0x20, 0x20, 0x20, 0x20, 0x20, \r
+ 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x50, 0x61, \r
+ 0x63, 0x6b, 0x65, 0x74, 0x73, 0x20, 0x72, 0x65, 0x63, 0x65, \r
+ 0x69, 0x76, 0x65, 0x64, 0xd, 0xa, 0x20, 0x20, 0x20, 0x20, \r
+ 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x50, \r
+ 0x61, 0x63, 0x6b, 0x65, 0x74, 0x73, 0x20, 0x73, 0x65, 0x6e, \r
+ 0x74, 0xd, 0xa, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, \r
+ 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x43, 0x68, 0x65, 0x63, \r
+ 0x6b, 0x73, 0x75, 0x6d, 0x20, 0x65, 0x72, 0x72, 0x6f, 0x72, \r
+ 0x73, 0xd, 0xa, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, \r
+ 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x44, 0x61, 0x74, 0x61, \r
+ 0x20, 0x70, 0x61, 0x63, 0x6b, 0x65, 0x74, 0x73, 0x20, 0x77, \r
+ 0x69, 0x74, 0x68, 0x6f, 0x75, 0x74, 0x20, 0x41, 0x43, 0x4b, \r
+ 0x73, 0xd, 0xa, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, \r
+ 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x52, 0x65, 0x73, 0x65, \r
+ 0x74, 0x73, 0xd, 0xa, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, \r
+ 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x52, 0x65, 0x74, \r
+ 0x72, 0x61, 0x6e, 0x73, 0x6d, 0x69, 0x73, 0x73, 0x69, 0x6f, \r
+ 0x6e, 0x73, 0xd, 0xa, 0x9, 0x20, 0x20, 0x20, 0x20, 0x20, \r
+ 0x4e, 0x6f, 0x20, 0x63, 0x6f, 0x6e, 0x6e, 0x65, 0x63, 0x74, \r
+ 0x69, 0x6f, 0x6e, 0x20, 0x61, 0x76, 0x61, 0x6c, 0x69, 0x61, \r
+ 0x62, 0x6c, 0x65, 0xd, 0xa, 0x9, 0x20, 0x20, 0x20, 0x20, \r
+ 0x20, 0x43, 0x6f, 0x6e, 0x6e, 0x65, 0x63, 0x74, 0x69, 0x6f, \r
+ 0x6e, 0x20, 0x61, 0x74, 0x74, 0x65, 0x6d, 0x70, 0x74, 0x73, \r
+ 0x20, 0x74, 0x6f, 0x20, 0x63, 0x6c, 0x6f, 0x73, 0x65, 0x64, \r
+ 0x20, 0x70, 0x6f, 0x72, 0x74, 0x73, 0xd, 0xa, 0x3c, 0x2f, \r
+ 0x70, 0x72, 0x65, 0x3e, 0x3c, 0x2f, 0x66, 0x6f, 0x6e, 0x74, \r
+ 0x3e, 0x3c, 0x2f, 0x74, 0x64, 0x3e, 0x3c, 0x74, 0x64, 0x3e, \r
+ 0x3c, 0x70, 0x72, 0x65, 0x3e, 0x25, 0x21, 0x20, 0x6e, 0x65, \r
+ 0x74, 0x2d, 0x73, 0x74, 0x61, 0x74, 0x73, 0xd, 0xa, 0x3c, \r
+ 0x2f, 0x70, 0x72, 0x65, 0x3e, 0x3c, 0x2f, 0x74, 0x61, 0x62, \r
+ 0x6c, 0x65, 0x3e, 0xd, 0xa, 0x3c, 0x2f, 0x66, 0x6f, 0x6e, \r
+ 0x74, 0x3e, 0xd, 0xa, 0x3c, 0x2f, 0x62, 0x6f, 0x64, 0x79, \r
+ 0x3e, 0xd, 0xa, 0x3c, 0x2f, 0x68, 0x74, 0x6d, 0x6c, 0x3e, \r
+ 0xd, 0xa, 0};\r
+\r
+static const unsigned char data_tcp_shtml[] = {\r
+ /* /tcp.shtml */\r
+ 0x2f, 0x74, 0x63, 0x70, 0x2e, 0x73, 0x68, 0x74, 0x6d, 0x6c, 0,\r
+ 0x3c, 0x21, 0x44, 0x4f, 0x43, 0x54, 0x59, 0x50, 0x45, 0x20, \r
+ 0x48, 0x54, 0x4d, 0x4c, 0x20, 0x50, 0x55, 0x42, 0x4c, 0x49, \r
+ 0x43, 0x20, 0x22, 0x2d, 0x2f, 0x2f, 0x57, 0x33, 0x43, 0x2f, \r
+ 0x2f, 0x44, 0x54, 0x44, 0x20, 0x48, 0x54, 0x4d, 0x4c, 0x20, \r
+ 0x34, 0x2e, 0x30, 0x31, 0x20, 0x54, 0x72, 0x61, 0x6e, 0x73, \r
+ 0x69, 0x74, 0x69, 0x6f, 0x6e, 0x61, 0x6c, 0x2f, 0x2f, 0x45, \r
+ 0x4e, 0x22, 0x20, 0x22, 0x68, 0x74, 0x74, 0x70, 0x3a, 0x2f, \r
+ 0x2f, 0x77, 0x77, 0x77, 0x2e, 0x77, 0x33, 0x2e, 0x6f, 0x72, \r
+ 0x67, 0x2f, 0x54, 0x52, 0x2f, 0x68, 0x74, 0x6d, 0x6c, 0x34, \r
+ 0x2f, 0x6c, 0x6f, 0x6f, 0x73, 0x65, 0x2e, 0x64, 0x74, 0x64, \r
+ 0x22, 0x3e, 0xd, 0xa, 0x3c, 0x68, 0x74, 0x6d, 0x6c, 0x3e, \r
+ 0xd, 0xa, 0x20, 0x20, 0x3c, 0x68, 0x65, 0x61, 0x64, 0x3e, \r
+ 0xd, 0xa, 0x20, 0x20, 0x20, 0x20, 0x3c, 0x74, 0x69, 0x74, \r
+ 0x6c, 0x65, 0x3e, 0x46, 0x72, 0x65, 0x65, 0x52, 0x54, 0x4f, \r
+ 0x53, 0x2e, 0x6f, 0x72, 0x67, 0x20, 0x75, 0x49, 0x50, 0x20, \r
+ 0x57, 0x45, 0x42, 0x20, 0x73, 0x65, 0x72, 0x76, 0x65, 0x72, \r
+ 0x20, 0x64, 0x65, 0x6d, 0x6f, 0x3c, 0x2f, 0x74, 0x69, 0x74, \r
+ 0x6c, 0x65, 0x3e, 0xd, 0xa, 0x20, 0x20, 0x3c, 0x2f, 0x68, \r
+ 0x65, 0x61, 0x64, 0x3e, 0xd, 0xa, 0x20, 0x20, 0x3c, 0x42, \r
+ 0x4f, 0x44, 0x59, 0x20, 0x62, 0x67, 0x63, 0x6f, 0x6c, 0x6f, \r
+ 0x72, 0x3d, 0x22, 0x23, 0x43, 0x43, 0x43, 0x43, 0x66, 0x66, \r
+ 0x22, 0x3e, 0xd, 0xa, 0x3c, 0x66, 0x6f, 0x6e, 0x74, 0x20, \r
+ 0x66, 0x61, 0x63, 0x65, 0x3d, 0x22, 0x61, 0x72, 0x69, 0x61, \r
+ 0x6c, 0x22, 0x3e, 0xd, 0xa, 0x3c, 0x61, 0x20, 0x68, 0x72, \r
+ 0x65, 0x66, 0x3d, 0x22, 0x69, 0x6e, 0x64, 0x65, 0x78, 0x2e, \r
+ 0x73, 0x68, 0x74, 0x6d, 0x6c, 0x22, 0x3e, 0x52, 0x54, 0x4f, \r
+ 0x53, 0x20, 0x53, 0x74, 0x61, 0x74, 0x73, 0x3c, 0x2f, 0x61, \r
+ 0x3e, 0x20, 0x3c, 0x62, 0x3e, 0x7c, 0x3c, 0x2f, 0x62, 0x3e, \r
+ 0x20, 0x3c, 0x61, 0x20, 0x68, 0x72, 0x65, 0x66, 0x3d, 0x22, \r
+ 0x73, 0x74, 0x61, 0x74, 0x73, 0x2e, 0x73, 0x68, 0x74, 0x6d, \r
+ 0x6c, 0x22, 0x3e, 0x54, 0x43, 0x50, 0x20, 0x53, 0x74, 0x61, \r
+ 0x74, 0x73, 0x3c, 0x2f, 0x61, 0x3e, 0x20, 0x3c, 0x62, 0x3e, \r
+ 0x7c, 0x3c, 0x2f, 0x62, 0x3e, 0x20, 0x3c, 0x61, 0x20, 0x68, \r
+ 0x72, 0x65, 0x66, 0x3d, 0x22, 0x74, 0x63, 0x70, 0x2e, 0x73, \r
+ 0x68, 0x74, 0x6d, 0x6c, 0x22, 0x3e, 0x43, 0x6f, 0x6e, 0x6e, \r
+ 0x65, 0x63, 0x74, 0x69, 0x6f, 0x6e, 0x73, 0x3c, 0x2f, 0x61, \r
+ 0x3e, 0x20, 0x3c, 0x62, 0x3e, 0x7c, 0x3c, 0x2f, 0x62, 0x3e, \r
+ 0x20, 0x3c, 0x61, 0x20, 0x68, 0x72, 0x65, 0x66, 0x3d, 0x22, \r
+ 0x68, 0x74, 0x74, 0x70, 0x3a, 0x2f, 0x2f, 0x77, 0x77, 0x77, \r
+ 0x2e, 0x66, 0x72, 0x65, 0x65, 0x72, 0x74, 0x6f, 0x73, 0x2e, \r
+ 0x6f, 0x72, 0x67, 0x2f, 0x22, 0x3e, 0x46, 0x72, 0x65, 0x65, \r
+ 0x52, 0x54, 0x4f, 0x53, 0x2e, 0x6f, 0x72, 0x67, 0x20, 0x48, \r
+ 0x6f, 0x6d, 0x65, 0x70, 0x61, 0x67, 0x65, 0x3c, 0x2f, 0x61, \r
+ 0x3e, 0x20, 0x3c, 0x62, 0x3e, 0x7c, 0x3c, 0x2f, 0x62, 0x3e, \r
+ 0x20, 0x3c, 0x61, 0x20, 0x68, 0x72, 0x65, 0x66, 0x3d, 0x22, \r
+ 0x69, 0x6f, 0x2e, 0x73, 0x68, 0x74, 0x6d, 0x6c, 0x22, 0x3e, \r
+ 0x49, 0x4f, 0x3c, 0x2f, 0x61, 0x3e, 0xd, 0xa, 0x3c, 0x62, \r
+ 0x72, 0x3e, 0x3c, 0x70, 0x3e, 0xd, 0xa, 0x3c, 0x68, 0x72, \r
+ 0x3e, 0xd, 0xa, 0x3c, 0x62, 0x72, 0x3e, 0xd, 0xa, 0x3c, \r
+ 0x68, 0x32, 0x3e, 0x4e, 0x65, 0x74, 0x77, 0x6f, 0x72, 0x6b, \r
+ 0x20, 0x63, 0x6f, 0x6e, 0x6e, 0x65, 0x63, 0x74, 0x69, 0x6f, \r
+ 0x6e, 0x73, 0x3c, 0x2f, 0x68, 0x32, 0x3e, 0xd, 0xa, 0x3c, \r
+ 0x70, 0x3e, 0xd, 0xa, 0x3c, 0x74, 0x61, 0x62, 0x6c, 0x65, \r
+ 0x3e, 0xd, 0xa, 0x3c, 0x74, 0x72, 0x3e, 0x3c, 0x74, 0x68, \r
+ 0x3e, 0x4c, 0x6f, 0x63, 0x61, 0x6c, 0x3c, 0x2f, 0x74, 0x68, \r
+ 0x3e, 0x3c, 0x74, 0x68, 0x3e, 0x52, 0x65, 0x6d, 0x6f, 0x74, \r
+ 0x65, 0x3c, 0x2f, 0x74, 0x68, 0x3e, 0x3c, 0x74, 0x68, 0x3e, \r
+ 0x53, 0x74, 0x61, 0x74, 0x65, 0x3c, 0x2f, 0x74, 0x68, 0x3e, \r
+ 0x3c, 0x74, 0x68, 0x3e, 0x52, 0x65, 0x74, 0x72, 0x61, 0x6e, \r
+ 0x73, 0x6d, 0x69, 0x73, 0x73, 0x69, 0x6f, 0x6e, 0x73, 0x3c, \r
+ 0x2f, 0x74, 0x68, 0x3e, 0x3c, 0x74, 0x68, 0x3e, 0x54, 0x69, \r
+ 0x6d, 0x65, 0x72, 0x3c, 0x2f, 0x74, 0x68, 0x3e, 0x3c, 0x74, \r
+ 0x68, 0x3e, 0x46, 0x6c, 0x61, 0x67, 0x73, 0x3c, 0x2f, 0x74, \r
+ 0x68, 0x3e, 0x3c, 0x2f, 0x74, 0x72, 0x3e, 0xd, 0xa, 0x25, \r
+ 0x21, 0x20, 0x74, 0x63, 0x70, 0x2d, 0x63, 0x6f, 0x6e, 0x6e, \r
+ 0x65, 0x63, 0x74, 0x69, 0x6f, 0x6e, 0x73, 0xd, 0xa, 0x3c, \r
+ 0x2f, 0x70, 0x72, 0x65, 0x3e, 0x3c, 0x2f, 0x66, 0x6f, 0x6e, \r
+ 0x74, 0x3e, 0xd, 0xa, 0x3c, 0x2f, 0x66, 0x6f, 0x6e, 0x74, \r
+ 0x3e, 0xd, 0xa, 0x3c, 0x2f, 0x62, 0x6f, 0x64, 0x79, 0x3e, \r
+ 0xd, 0xa, 0x3c, 0x2f, 0x68, 0x74, 0x6d, 0x6c, 0x3e, 0xd, \r
+ 0xa, 0xd, 0xa, 0};\r
+\r
+const struct httpd_fsdata_file file_404_html[] = {{NULL, data_404_html, data_404_html + 10, sizeof(data_404_html) - 10}};\r
+\r
+const struct httpd_fsdata_file file_index_html[] = {{file_404_html, data_index_html, data_index_html + 12, sizeof(data_index_html) - 12}};\r
+\r
+const struct httpd_fsdata_file file_index_shtml[] = {{file_index_html, data_index_shtml, data_index_shtml + 13, sizeof(data_index_shtml) - 13}};\r
+\r
+const struct httpd_fsdata_file file_io_shtml[] = {{file_index_shtml, data_io_shtml, data_io_shtml + 10, sizeof(data_io_shtml) - 10}};\r
+\r
+const struct httpd_fsdata_file file_stats_shtml[] = {{file_io_shtml, data_stats_shtml, data_stats_shtml + 13, sizeof(data_stats_shtml) - 13}};\r
+\r
+const struct httpd_fsdata_file file_tcp_shtml[] = {{file_stats_shtml, data_tcp_shtml, data_tcp_shtml + 11, sizeof(data_tcp_shtml) - 11}};\r
+\r
+#define HTTPD_FS_ROOT file_tcp_shtml\r
+\r
+#define HTTPD_FS_NUMFILES 6\r
--- /dev/null
+/*\r
+ * Copyright (c) 2001, Swedish Institute of Computer Science.\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ * 1. Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the\r
+ * documentation and/or other materials provided with the distribution.\r
+ * 3. Neither the name of the Institute nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND\r
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\r
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\r
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\r
+ * SUCH DAMAGE.\r
+ *\r
+ * This file is part of the lwIP TCP/IP stack.\r
+ *\r
+ * Author: Adam Dunkels <adam@sics.se>\r
+ *\r
+ * $Id: httpd-fsdata.h,v 1.1 2006/06/07 09:13:08 adam Exp $\r
+ */\r
+#ifndef __HTTPD_FSDATA_H__\r
+#define __HTTPD_FSDATA_H__\r
+\r
+#include "uip.h"\r
+\r
+struct httpd_fsdata_file {\r
+ const struct httpd_fsdata_file *next;\r
+ const char *name;\r
+ const char *data;\r
+ const int len;\r
+#ifdef HTTPD_FS_STATISTICS\r
+#if HTTPD_FS_STATISTICS == 1\r
+ u16_t count;\r
+#endif /* HTTPD_FS_STATISTICS */\r
+#endif /* HTTPD_FS_STATISTICS */\r
+};\r
+\r
+struct httpd_fsdata_file_noconst {\r
+ struct httpd_fsdata_file *next;\r
+ char *name;\r
+ char *data;\r
+ int len;\r
+#ifdef HTTPD_FS_STATISTICS\r
+#if HTTPD_FS_STATISTICS == 1\r
+ u16_t count;\r
+#endif /* HTTPD_FS_STATISTICS */\r
+#endif /* HTTPD_FS_STATISTICS */\r
+};\r
+\r
+#endif /* __HTTPD_FSDATA_H__ */\r
--- /dev/null
+/**\r
+ * \addtogroup apps\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * \defgroup httpd Web server\r
+ * @{\r
+ * The uIP web server is a very simplistic implementation of an HTTP\r
+ * server. It can serve web pages and files from a read-only ROM\r
+ * filesystem, and provides a very small scripting language.\r
+\r
+ */\r
+\r
+/**\r
+ * \file\r
+ * Web server\r
+ * \author\r
+ * Adam Dunkels <adam@sics.se>\r
+ */\r
+\r
+\r
+/*\r
+ * Copyright (c) 2004, Adam Dunkels.\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ * 1. Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the\r
+ * documentation and/or other materials provided with the distribution.\r
+ * 3. Neither the name of the Institute nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND\r
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\r
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\r
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\r
+ * SUCH DAMAGE.\r
+ *\r
+ * This file is part of the uIP TCP/IP stack.\r
+ *\r
+ * Author: Adam Dunkels <adam@sics.se>\r
+ *\r
+ * $Id: httpd.c,v 1.2 2006/06/11 21:46:38 adam Exp $\r
+ */\r
+\r
+#include "uip.h"\r
+#include "httpd.h"\r
+#include "httpd-fs.h"\r
+#include "httpd-cgi.h"\r
+#include "http-strings.h"\r
+\r
+#include <string.h>\r
+\r
+#define STATE_WAITING 0\r
+#define STATE_OUTPUT 1\r
+\r
+#define ISO_nl 0x0a\r
+#define ISO_space 0x20\r
+#define ISO_bang 0x21\r
+#define ISO_percent 0x25\r
+#define ISO_period 0x2e\r
+#define ISO_slash 0x2f\r
+#define ISO_colon 0x3a\r
+\r
+\r
+/*---------------------------------------------------------------------------*/\r
+static unsigned short\r
+generate_part_of_file(void *state)\r
+{\r
+ struct httpd_state *s = (struct httpd_state *)state;\r
+\r
+ if(s->file.len > uip_mss()) {\r
+ s->len = uip_mss();\r
+ } else {\r
+ s->len = s->file.len;\r
+ }\r
+ memcpy(uip_appdata, s->file.data, s->len);\r
+ \r
+ return s->len;\r
+}\r
+/*---------------------------------------------------------------------------*/\r
+static\r
+PT_THREAD(send_file(struct httpd_state *s))\r
+{\r
+ PSOCK_BEGIN(&s->sout);\r
+ \r
+ do {\r
+ PSOCK_GENERATOR_SEND(&s->sout, generate_part_of_file, s);\r
+ s->file.len -= s->len;\r
+ s->file.data += s->len;\r
+ } while(s->file.len > 0);\r
+ \r
+ PSOCK_END(&s->sout);\r
+}\r
+/*---------------------------------------------------------------------------*/\r
+static\r
+PT_THREAD(send_part_of_file(struct httpd_state *s))\r
+{\r
+ PSOCK_BEGIN(&s->sout);\r
+\r
+ PSOCK_SEND(&s->sout, s->file.data, s->len);\r
+ \r
+ PSOCK_END(&s->sout);\r
+}\r
+/*---------------------------------------------------------------------------*/\r
+static void\r
+next_scriptstate(struct httpd_state *s)\r
+{\r
+ char *p;\r
+ p = strchr(s->scriptptr, ISO_nl) + 1;\r
+ s->scriptlen -= (unsigned short)(p - s->scriptptr);\r
+ s->scriptptr = p;\r
+}\r
+/*---------------------------------------------------------------------------*/\r
+static\r
+PT_THREAD(handle_script(struct httpd_state *s))\r
+{\r
+ char *ptr;\r
+ \r
+ PT_BEGIN(&s->scriptpt);\r
+\r
+\r
+ while(s->file.len > 0) {\r
+\r
+ /* Check if we should start executing a script. */\r
+ if(*s->file.data == ISO_percent &&\r
+ *(s->file.data + 1) == ISO_bang) {\r
+ s->scriptptr = s->file.data + 3;\r
+ s->scriptlen = s->file.len - 3;\r
+ if(*(s->scriptptr - 1) == ISO_colon) {\r
+ httpd_fs_open(s->scriptptr + 1, &s->file);\r
+ PT_WAIT_THREAD(&s->scriptpt, send_file(s));\r
+ } else {\r
+ PT_WAIT_THREAD(&s->scriptpt,\r
+ httpd_cgi(s->scriptptr)(s, s->scriptptr));\r
+ }\r
+ next_scriptstate(s);\r
+ \r
+ /* The script is over, so we reset the pointers and continue\r
+ sending the rest of the file. */\r
+ s->file.data = s->scriptptr;\r
+ s->file.len = s->scriptlen;\r
+ } else {\r
+ /* See if we find the start of script marker in the block of HTML\r
+ to be sent. */\r
+\r
+ if(s->file.len > uip_mss()) {\r
+ s->len = uip_mss();\r
+ } else {\r
+ s->len = s->file.len;\r
+ }\r
+\r
+ if(*s->file.data == ISO_percent) {\r
+ ptr = strchr(s->file.data + 1, ISO_percent);\r
+ } else {\r
+ ptr = strchr(s->file.data, ISO_percent);\r
+ }\r
+ if(ptr != NULL &&\r
+ ptr != s->file.data) {\r
+ s->len = (int)(ptr - s->file.data);\r
+ if(s->len >= uip_mss()) {\r
+ s->len = uip_mss();\r
+ }\r
+ }\r
+ PT_WAIT_THREAD(&s->scriptpt, send_part_of_file(s));\r
+ s->file.data += s->len;\r
+ s->file.len -= s->len;\r
+ \r
+ }\r
+ }\r
+ \r
+ PT_END(&s->scriptpt);\r
+}\r
+/*---------------------------------------------------------------------------*/\r
+static\r
+PT_THREAD(send_headers(struct httpd_state *s, const char *statushdr))\r
+{\r
+ char *ptr;\r
+\r
+ PSOCK_BEGIN(&s->sout);\r
+\r
+ PSOCK_SEND_STR(&s->sout, statushdr);\r
+\r
+ ptr = strrchr(s->filename, ISO_period);\r
+ if(ptr == NULL) {\r
+ PSOCK_SEND_STR(&s->sout, http_content_type_binary);\r
+ } else if(strncmp(http_html, ptr, 5) == 0 ||\r
+ strncmp(http_shtml, ptr, 6) == 0) {\r
+ PSOCK_SEND_STR(&s->sout, http_content_type_html);\r
+ } else if(strncmp(http_css, ptr, 4) == 0) {\r
+ PSOCK_SEND_STR(&s->sout, http_content_type_css);\r
+ } else if(strncmp(http_png, ptr, 4) == 0) {\r
+ PSOCK_SEND_STR(&s->sout, http_content_type_png);\r
+ } else if(strncmp(http_gif, ptr, 4) == 0) {\r
+ PSOCK_SEND_STR(&s->sout, http_content_type_gif);\r
+ } else if(strncmp(http_jpg, ptr, 4) == 0) {\r
+ PSOCK_SEND_STR(&s->sout, http_content_type_jpg);\r
+ } else {\r
+ PSOCK_SEND_STR(&s->sout, http_content_type_plain);\r
+ }\r
+ PSOCK_END(&s->sout);\r
+}\r
+/*---------------------------------------------------------------------------*/\r
+static\r
+PT_THREAD(handle_output(struct httpd_state *s))\r
+{\r
+ char *ptr;\r
+ \r
+ PT_BEGIN(&s->outputpt);\r
+ \r
+ if(!httpd_fs_open(s->filename, &s->file)) {\r
+ httpd_fs_open(http_404_html, &s->file);\r
+ strcpy(s->filename, http_404_html);\r
+ PT_WAIT_THREAD(&s->outputpt,\r
+ send_headers(s,\r
+ http_header_404));\r
+ PT_WAIT_THREAD(&s->outputpt,\r
+ send_file(s));\r
+ } else {\r
+ PT_WAIT_THREAD(&s->outputpt,\r
+ send_headers(s,\r
+ http_header_200));\r
+ ptr = strchr(s->filename, ISO_period);\r
+ if(ptr != NULL && strncmp(ptr, http_shtml, 6) == 0) {\r
+ PT_INIT(&s->scriptpt);\r
+ PT_WAIT_THREAD(&s->outputpt, handle_script(s));\r
+ } else {\r
+ PT_WAIT_THREAD(&s->outputpt,\r
+ send_file(s));\r
+ }\r
+ }\r
+ PSOCK_CLOSE(&s->sout);\r
+ PT_END(&s->outputpt);\r
+}\r
+/*---------------------------------------------------------------------------*/\r
+static\r
+PT_THREAD(handle_input(struct httpd_state *s))\r
+{\r
+ PSOCK_BEGIN(&s->sin);\r
+\r
+ PSOCK_READTO(&s->sin, ISO_space);\r
+\r
+ \r
+ if(strncmp(s->inputbuf, http_get, 4) != 0) {\r
+ PSOCK_CLOSE_EXIT(&s->sin);\r
+ }\r
+ PSOCK_READTO(&s->sin, ISO_space);\r
+\r
+ if(s->inputbuf[0] != ISO_slash) {\r
+ PSOCK_CLOSE_EXIT(&s->sin);\r
+ }\r
+\r
+ if(s->inputbuf[1] == ISO_space) {\r
+ strncpy(s->filename, http_index_html, sizeof(s->filename));\r
+ } else {\r
+\r
+ s->inputbuf[PSOCK_DATALEN(&s->sin) - 1] = 0;\r
+\r
+ /* Process any form input being sent to the server. */\r
+ {\r
+ extern void vApplicationProcessFormInput( char *pcInputString, long xInputLength );\r
+ vApplicationProcessFormInput( s->inputbuf, PSOCK_DATALEN(&s->sin) );\r
+ }\r
+\r
+ strncpy(s->filename, &s->inputbuf[0], sizeof(s->filename));\r
+ }\r
+\r
+ /* httpd_log_file(uip_conn->ripaddr, s->filename);*/\r
+ \r
+ s->state = STATE_OUTPUT;\r
+\r
+ while(1) {\r
+ PSOCK_READTO(&s->sin, ISO_nl);\r
+\r
+ if(strncmp(s->inputbuf, http_referer, 8) == 0) {\r
+ s->inputbuf[PSOCK_DATALEN(&s->sin) - 2] = 0;\r
+ /* httpd_log(&s->inputbuf[9]);*/\r
+ }\r
+ }\r
+ \r
+ PSOCK_END(&s->sin);\r
+}\r
+/*---------------------------------------------------------------------------*/\r
+static void\r
+handle_connection(struct httpd_state *s)\r
+{\r
+ handle_input(s);\r
+ if(s->state == STATE_OUTPUT) {\r
+ handle_output(s);\r
+ }\r
+}\r
+/*---------------------------------------------------------------------------*/\r
+void\r
+httpd_appcall(void)\r
+{\r
+ struct httpd_state *s = (struct httpd_state *)&(uip_conn->appstate);\r
+\r
+ if(uip_closed() || uip_aborted() || uip_timedout()) {\r
+ } else if(uip_connected()) {\r
+ PSOCK_INIT(&s->sin, s->inputbuf, sizeof(s->inputbuf) - 1);\r
+ PSOCK_INIT(&s->sout, s->inputbuf, sizeof(s->inputbuf) - 1);\r
+ PT_INIT(&s->outputpt);\r
+ s->state = STATE_WAITING;\r
+ /* timer_set(&s->timer, CLOCK_SECOND * 100);*/\r
+ s->timer = 0;\r
+ handle_connection(s);\r
+ } else if(s != NULL) {\r
+ if(uip_poll()) {\r
+ ++s->timer;\r
+ if(s->timer >= 20) {\r
+ uip_abort();\r
+ }\r
+ } else {\r
+ s->timer = 0;\r
+ }\r
+ handle_connection(s);\r
+ } else {\r
+ uip_abort();\r
+ }\r
+}\r
+/*---------------------------------------------------------------------------*/\r
+/**\r
+ * \brief Initialize the web server\r
+ *\r
+ * This function initializes the web server and should be\r
+ * called at system boot-up.\r
+ */\r
+void\r
+httpd_init(void)\r
+{\r
+ uip_listen(HTONS(80));\r
+}\r
+/*---------------------------------------------------------------------------*/\r
+/** @} */\r
--- /dev/null
+/*\r
+ * Copyright (c) 2001-2005, Adam Dunkels.\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ * 1. Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the\r
+ * documentation and/or other materials provided with the distribution.\r
+ * 3. The name of the author may not be used to endorse or promote\r
+ * products derived from this software without specific prior\r
+ * written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS\r
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\r
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY\r
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE\r
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\r
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\r
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * This file is part of the uIP TCP/IP stack.\r
+ *\r
+ * $Id: httpd.h,v 1.2 2006/06/11 21:46:38 adam Exp $\r
+ *\r
+ */\r
+\r
+#ifndef __HTTPD_H__\r
+#define __HTTPD_H__\r
+\r
+#include "psock.h"\r
+#include "httpd-fs.h"\r
+\r
+struct httpd_state {\r
+ unsigned char timer;\r
+ struct psock sin, sout;\r
+ struct pt outputpt, scriptpt;\r
+ char inputbuf[50];\r
+ char filename[20];\r
+ char state;\r
+ struct httpd_fs_file file;\r
+ int len;\r
+ char *scriptptr;\r
+ int scriptlen;\r
+ \r
+ unsigned short count;\r
+};\r
+\r
+void httpd_init(void);\r
+void httpd_appcall(void);\r
+\r
+void httpd_log(char *msg);\r
+void httpd_log_file(u16_t *requester, char *file);\r
+\r
+#endif /* __HTTPD_H__ */\r
--- /dev/null
+#!/usr/bin/perl\r
+\r
+open(OUTPUT, "> httpd-fsdata.c");\r
+\r
+chdir("httpd-fs");\r
+\r
+opendir(DIR, ".");\r
+@files = grep { !/^\./ && !/(CVS|~)/ } readdir(DIR);\r
+closedir(DIR);\r
+\r
+foreach $file (@files) { \r
+ \r
+ if(-d $file && $file !~ /^\./) {\r
+ print "Processing directory $file\n";\r
+ opendir(DIR, $file);\r
+ @newfiles = grep { !/^\./ && !/(CVS|~)/ } readdir(DIR);\r
+ closedir(DIR);\r
+ printf "Adding files @newfiles\n";\r
+ @files = (@files, map { $_ = "$file/$_" } @newfiles);\r
+ next;\r
+ }\r
+}\r
+\r
+foreach $file (@files) {\r
+ if(-f $file) {\r
+ \r
+ print "Adding file $file\n";\r
+ \r
+ open(FILE, $file) || die "Could not open file $file\n";\r
+\r
+ $file =~ s-^-/-;\r
+ $fvar = $file;\r
+ $fvar =~ s-/-_-g;\r
+ $fvar =~ s-\.-_-g;\r
+ # for AVR, add PROGMEM here\r
+ print(OUTPUT "static const unsigned char data".$fvar."[] = {\n");\r
+ print(OUTPUT "\t/* $file */\n\t");\r
+ for($j = 0; $j < length($file); $j++) {\r
+ printf(OUTPUT "%#02x, ", unpack("C", substr($file, $j, 1)));\r
+ }\r
+ printf(OUTPUT "0,\n");\r
+ \r
+ \r
+ $i = 0; \r
+ while(read(FILE, $data, 1)) {\r
+ if($i == 0) {\r
+ print(OUTPUT "\t");\r
+ }\r
+ printf(OUTPUT "%#02x, ", unpack("C", $data));\r
+ $i++;\r
+ if($i == 10) {\r
+ print(OUTPUT "\n");\r
+ $i = 0;\r
+ }\r
+ }\r
+ print(OUTPUT "0};\n\n");\r
+ close(FILE);\r
+ push(@fvars, $fvar);\r
+ push(@pfiles, $file);\r
+ }\r
+}\r
+\r
+for($i = 0; $i < @fvars; $i++) {\r
+ $file = $pfiles[$i];\r
+ $fvar = $fvars[$i];\r
+\r
+ if($i == 0) {\r
+ $prevfile = "NULL";\r
+ } else {\r
+ $prevfile = "file" . $fvars[$i - 1];\r
+ }\r
+ print(OUTPUT "const struct httpd_fsdata_file file".$fvar."[] = {{$prevfile, data$fvar, ");\r
+ print(OUTPUT "data$fvar + ". (length($file) + 1) .", ");\r
+ print(OUTPUT "sizeof(data$fvar) - ". (length($file) + 1) ."}};\n\n");\r
+}\r
+\r
+print(OUTPUT "#define HTTPD_FS_ROOT file$fvars[$i - 1]\n\n");\r
+print(OUTPUT "#define HTTPD_FS_NUMFILES $i\n");\r
--- /dev/null
+#!/usr/bin/perl\r
+\r
+\r
+sub stringify {\r
+ my $name = shift(@_);\r
+ open(OUTPUTC, "> $name.c");\r
+ open(OUTPUTH, "> $name.h");\r
+ \r
+ open(FILE, "$name");\r
+ \r
+ while(<FILE>) {\r
+ if(/(.+) "(.+)"/) {\r
+ $var = $1;\r
+ $data = $2;\r
+ \r
+ $datan = $data;\r
+ $datan =~ s/\\r/\r/g;\r
+ $datan =~ s/\\n/\n/g;\r
+ $datan =~ s/\\01/\01/g; \r
+ $datan =~ s/\\0/\0/g;\r
+ \r
+ printf(OUTPUTC "const char $var\[%d] = \n", length($datan) + 1);\r
+ printf(OUTPUTC "/* \"$data\" */\n");\r
+ printf(OUTPUTC "{");\r
+ for($j = 0; $j < length($datan); $j++) {\r
+ printf(OUTPUTC "%#02x, ", unpack("C", substr($datan, $j, 1)));\r
+ }\r
+ printf(OUTPUTC "};\n");\r
+ \r
+ printf(OUTPUTH "extern const char $var\[%d];\n", length($datan) + 1);\r
+ \r
+ }\r
+ }\r
+ close(OUTPUTC);\r
+ close(OUTPUTH);\r
+}\r
+stringify("http-strings");\r
+\r
+exit 0;\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS.org V4.3.0 - Copyright (C) 2003-2007 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS.org distribution.\r
+\r
+ FreeRTOS.org is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS.org is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS.org; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS.org, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section\r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license\r
+ and contact details. Please ensure to read the configuration and relevant\r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+/* Standard includes. */\r
+#include <string.h>\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "semphr.h"\r
+\r
+#include "lcd_message.h"\r
+\r
+/* uip includes. */\r
+#include "hw_types.h"\r
+\r
+#include "uip.h"\r
+#include "uip_arp.h"\r
+#include "httpd.h"\r
+#include "timer.h"\r
+#include "clock-arch.h"\r
+#include "hw_ethernet.h"\r
+#include "ethernet.h"\r
+#include "hw_memmap.h"\r
+#include "lmi_flash.h"\r
+\r
+/* Demo includes. */\r
+#include "emac.h"\r
+#include "partest.h"\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* IP address configuration. */\r
+#define uipIP_ADDR0 172\r
+#define uipIP_ADDR1 25\r
+#define uipIP_ADDR2 218\r
+#define uipIP_ADDR3 9 \r
+\r
+/* How long to wait before attempting to connect the MAC again. */\r
+#define uipINIT_WAIT 100\r
+\r
+/* Shortcut to the header within the Rx buffer. */\r
+#define xHeader ((struct uip_eth_hdr *) &uip_buf[ 0 ])\r
+\r
+/* Standard constant. */\r
+#define uipTOTAL_FRAME_HEADER_SIZE 54\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Send the uIP buffer to the MAC.\r
+ */\r
+static void prvENET_Send(void);\r
+\r
+/*\r
+ * Setup the MAC address in the MAC itself, and in the uIP stack.\r
+ */\r
+static void prvSetMACAddress( void );\r
+\r
+/*\r
+ * Port functions required by the uIP stack.\r
+ */\r
+void clock_init( void );\r
+clock_time_t clock_time( void );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* The semaphore used by the ISR to wake the uIP task. */\r
+extern xSemaphoreHandle xEMACSemaphore;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void clock_init(void)\r
+{\r
+ /* This is done when the scheduler starts. */\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+clock_time_t clock_time( void )\r
+{\r
+ return xTaskGetTickCount();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vuIP_Task( void *pvParameters )\r
+{\r
+portBASE_TYPE i;\r
+uip_ipaddr_t xIPAddr;\r
+struct timer periodic_timer, arp_timer;\r
+extern void ( vEMAC_ISR )( void );\r
+\r
+ /* Create the semaphore used by the ISR to wake this task. */\r
+ vSemaphoreCreateBinary( xEMACSemaphore );\r
+ \r
+ /* Initialise the uIP stack. */\r
+ timer_set( &periodic_timer, configTICK_RATE_HZ / 2 );\r
+ timer_set( &arp_timer, configTICK_RATE_HZ * 10 );\r
+ uip_init();\r
+ uip_ipaddr( xIPAddr, uipIP_ADDR0, uipIP_ADDR1, uipIP_ADDR2, uipIP_ADDR3 );\r
+ uip_sethostaddr( xIPAddr );\r
+ httpd_init();\r
+\r
+ while( vInitEMAC() != pdPASS )\r
+ {\r
+ vTaskDelay( uipINIT_WAIT );\r
+ }\r
+ prvSetMACAddress(); \r
+ \r
+\r
+ for( ;; )\r
+ {\r
+ /* Is there received data ready to be processed? */\r
+ uip_len = uiGetEMACRxData( uip_buf );\r
+ \r
+ if( uip_len > 0 )\r
+ {\r
+ /* Standard uIP loop taken from the uIP manual. */\r
+\r
+ if( xHeader->type == htons( UIP_ETHTYPE_IP ) )\r
+ {\r
+ uip_arp_ipin();\r
+ uip_input();\r
+\r
+ /* If the above function invocation resulted in data that\r
+ should be sent out on the network, the global variable\r
+ uip_len is set to a value > 0. */\r
+ if( uip_len > 0 )\r
+ {\r
+ uip_arp_out();\r
+ prvENET_Send();\r
+ }\r
+ }\r
+ else if( xHeader->type == htons( UIP_ETHTYPE_ARP ) )\r
+ {\r
+ uip_arp_arpin();\r
+\r
+ /* If the above function invocation resulted in data that\r
+ should be sent out on the network, the global variable\r
+ uip_len is set to a value > 0. */\r
+ if( uip_len > 0 )\r
+ {\r
+ prvENET_Send();\r
+ }\r
+ }\r
+ }\r
+ else\r
+ {\r
+ if( timer_expired( &periodic_timer ) )\r
+ {\r
+ timer_reset( &periodic_timer );\r
+ for( i = 0; i < UIP_CONNS; i++ )\r
+ {\r
+ uip_periodic( i );\r
+ \r
+ /* If the above function invocation resulted in data that\r
+ should be sent out on the network, the global variable\r
+ uip_len is set to a value > 0. */\r
+ if( uip_len > 0 )\r
+ {\r
+ uip_arp_out();\r
+ prvENET_Send();\r
+ }\r
+ } \r
+ \r
+ /* Call the ARP timer function every 10 seconds. */\r
+ if( timer_expired( &arp_timer ) )\r
+ {\r
+ timer_reset( &arp_timer );\r
+ uip_arp_timer();\r
+ }\r
+ }\r
+ else\r
+ { \r
+ /* We did not receive a packet, and there was no periodic\r
+ processing to perform. Block for a fixed period. If a packet\r
+ is received during this period we will be woken by the ISR\r
+ giving us the Semaphore. */\r
+ xSemaphoreTake( xEMACSemaphore, configTICK_RATE_HZ / 2 ); \r
+ }\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvENET_Send(void)\r
+{\r
+ vInitialiseSend();\r
+ vIncrementTxLength( uip_len );\r
+ vSendBufferToMAC();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvSetMACAddress( void )\r
+{\r
+unsigned portLONG ulUser0, ulUser1;\r
+unsigned char pucMACArray[8];\r
+struct uip_eth_addr xAddr;\r
+\r
+ /* Get the device MAC address from flash */\r
+ FlashUserGet(&ulUser0, &ulUser1);\r
+\r
+ /* Convert the MAC address from flash into sequence of bytes. */\r
+ pucMACArray[0] = ((ulUser0 >> 0) & 0xff);\r
+ pucMACArray[1] = ((ulUser0 >> 8) & 0xff);\r
+ pucMACArray[2] = ((ulUser0 >> 16) & 0xff);\r
+ pucMACArray[3] = ((ulUser1 >> 0) & 0xff);\r
+ pucMACArray[4] = ((ulUser1 >> 8) & 0xff);\r
+ pucMACArray[5] = ((ulUser1 >> 16) & 0xff);\r
+\r
+ /* Program the MAC address. */\r
+ EthernetMACAddrSet(ETH_BASE, pucMACArray);\r
+\r
+ xAddr.addr[ 0 ] = pucMACArray[0];\r
+ xAddr.addr[ 1 ] = pucMACArray[1];\r
+ xAddr.addr[ 2 ] = pucMACArray[2];\r
+ xAddr.addr[ 3 ] = pucMACArray[3];\r
+ xAddr.addr[ 4 ] = pucMACArray[4];\r
+ xAddr.addr[ 5 ] = pucMACArray[5];\r
+ uip_setethaddr( xAddr );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationProcessFormInput( portCHAR *pcInputString, portBASE_TYPE xInputLength )\r
+{\r
+char *c, *pcText;\r
+static portCHAR cMessageForDisplay[ 32 ];\r
+extern xQueueHandle xOLEDQueue;\r
+xOLEDMessage xOLEDMessage;\r
+\r
+ /* Process the form input sent by the IO page of the served HTML. */\r
+\r
+ c = strstr( pcInputString, "?" );\r
+\r
+ if( c )\r
+ {\r
+ /* Turn LED's on or off in accordance with the check box status. */\r
+ if( strstr( c, "LED0=1" ) != NULL )\r
+ {\r
+ vParTestSetLED( 0, 1 );\r
+ }\r
+ else\r
+ {\r
+ vParTestSetLED( 0, 0 );\r
+ } \r
+ \r
+ /* Find the start of the text to be displayed on the LCD. */\r
+ pcText = strstr( c, "LCD=" );\r
+ pcText += strlen( "LCD=" );\r
+\r
+ /* Terminate the file name for further processing within uIP. */\r
+ *c = 0x00;\r
+\r
+ /* Terminate the LCD string. */\r
+ c = strstr( pcText, " " );\r
+ if( c != NULL )\r
+ {\r
+ *c = 0x00;\r
+ }\r
+\r
+ /* Add required spaces. */\r
+ while( ( c = strstr( pcText, "+" ) ) != NULL )\r
+ {\r
+ *c = ' ';\r
+ }\r
+\r
+ /* Write the message to the LCD. */\r
+ strcpy( cMessageForDisplay, pcText );\r
+ xOLEDMessage.pcMessage = cMessageForDisplay;\r
+ xQueueSend( xOLEDQueue, &xOLEDMessage, portMAX_DELAY );\r
+ }\r
+}\r
+\r
--- /dev/null
+/**\r
+ * \addtogroup uipopt\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * \name Project-specific configuration options\r
+ * @{\r
+ *\r
+ * uIP has a number of configuration options that can be overridden\r
+ * for each project. These are kept in a project-specific uip-conf.h\r
+ * file and all configuration names have the prefix UIP_CONF.\r
+ */\r
+\r
+/*\r
+ * Copyright (c) 2006, Swedish Institute of Computer Science.\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ * 1. Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the\r
+ * documentation and/or other materials provided with the distribution.\r
+ * 3. Neither the name of the Institute nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND\r
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\r
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\r
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\r
+ * SUCH DAMAGE.\r
+ *\r
+ * This file is part of the uIP TCP/IP stack\r
+ *\r
+ * $Id: uip-conf.h,v 1.6 2006/06/12 08:00:31 adam Exp $\r
+ */\r
+\r
+/**\r
+ * \file\r
+ * An example uIP configuration file\r
+ * \author\r
+ * Adam Dunkels <adam@sics.se>\r
+ */\r
+\r
+#ifndef __UIP_CONF_H__\r
+#define __UIP_CONF_H__\r
+\r
+#include <stdint.h>\r
+\r
+/**\r
+ * 8 bit datatype\r
+ *\r
+ * This typedef defines the 8-bit type used throughout uIP.\r
+ *\r
+ * \hideinitializer\r
+ */\r
+typedef uint8_t u8_t;\r
+\r
+/**\r
+ * 16 bit datatype\r
+ *\r
+ * This typedef defines the 16-bit type used throughout uIP.\r
+ *\r
+ * \hideinitializer\r
+ */\r
+typedef uint16_t u16_t;\r
+\r
+/**\r
+ * Statistics datatype\r
+ *\r
+ * This typedef defines the dataype used for keeping statistics in\r
+ * uIP.\r
+ *\r
+ * \hideinitializer\r
+ */\r
+typedef unsigned short uip_stats_t;\r
+\r
+/**\r
+ * Maximum number of TCP connections.\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define UIP_CONF_MAX_CONNECTIONS 40\r
+\r
+/**\r
+ * Maximum number of listening TCP ports.\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define UIP_CONF_MAX_LISTENPORTS 40\r
+\r
+/**\r
+ * uIP buffer size.\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define UIP_CONF_BUFFER_SIZE 1500\r
+\r
+/**\r
+ * CPU byte order.\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define UIP_CONF_BYTE_ORDER LITTLE_ENDIAN\r
+\r
+/**\r
+ * Logging on or off\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define UIP_CONF_LOGGING 0\r
+\r
+/**\r
+ * UDP support on or off\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define UIP_CONF_UDP 0\r
+\r
+/**\r
+ * UDP checksums on or off\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define UIP_CONF_UDP_CHECKSUMS 1\r
+\r
+/**\r
+ * uIP statistics on or off\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define UIP_CONF_STATISTICS 1\r
+\r
+/* Here we include the header file for the application(s) we use in\r
+ our project. */\r
+/*#include "smtp.h"*/\r
+/*#include "hello-world.h"*/\r
+/*#include "telnetd.h"*/\r
+#include "webserver.h"\r
+/*#include "dhcpc.h"*/\r
+/*#include "resolv.h"*/\r
+/*#include "webclient.h"*/\r
+\r
+#define UIP_CONF_EXTERNAL_BUFFER\r
+\r
+#endif /* __UIP_CONF_H__ */\r
+\r
+/** @} */\r
+/** @} */\r
--- /dev/null
+/*\r
+ * Copyright (c) 2002, Adam Dunkels.\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ * 1. Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above\r
+ * copyright notice, this list of conditions and the following\r
+ * disclaimer in the documentation and/or other materials provided\r
+ * with the distribution.\r
+ * 3. The name of the author may not be used to endorse or promote\r
+ * products derived from this software without specific prior\r
+ * written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS\r
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\r
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY\r
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE\r
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\r
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\r
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * This file is part of the uIP TCP/IP stack\r
+ *\r
+ * $Id: webserver.h,v 1.2 2006/06/11 21:46:38 adam Exp $\r
+ *\r
+ */\r
+#ifndef __WEBSERVER_H__\r
+#define __WEBSERVER_H__\r
+\r
+#include "httpd.h"\r
+\r
+typedef struct httpd_state uip_tcp_appstate_t;\r
+/* UIP_APPCALL: the name of the application function. This function\r
+ must return void and take no arguments (i.e., C type "void\r
+ appfunc(void)"). */\r
+#ifndef UIP_APPCALL\r
+#define UIP_APPCALL httpd_appcall\r
+#endif\r
+\r
+\r
+#endif /* __WEBSERVER_H__ */\r
projects / freertos / commitdiff