--- /dev/null
+#################################################################################################
+# #
+# Author: Gary Carlson (gcarlson@carlson-minot.com) #
+# Generated for Atmel AT91SAM9G20-EK evaluation board using Atmel SAM-ICE (J-Link) version 8. #
+# #
+#################################################################################################
+
+# Define basic characteristics for the CPU. The AT91SAM9G20 processor is a subtle variant of
+# the AT91SAM9260 and shares the same tap ID as it.
+
+set _CHIPNAME at91sam9g20
+set _ENDIAN little
+set _CPUTAPID 0x0792603f
+
+# Set reset type. Note that the AT91SAM9G20-EK board has the trst signal disconnected. In theory this script
+# therefore should require "srst_only". With some J-Link debuggers at least, "srst_only" causes a temporary USB
+# communication fault. This appears to be more likely attributed to an internal proprietary firmware quirk inside the
+# dongle itself. Using "trst_and_srst" works fine, however. So if you can't beat them -- join them. If you are using
+# something other the a J-Link dongle you may be able to change this back to "srst_only".
+
+reset_config trst_and_srst
+
+# Set up the CPU and generate a new jtag tap for AT91SAM9G20.
+
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+# Use caution changing the delays listed below. These seem to be affected by the board and type of
+# debugger dongle. A value of 200 ms seems to work reliably for the configuration listed in the file header above.
+
+jtag_nsrst_delay 200
+jtag_ntrst_delay 200
+
+# Set fallback clock to 1/6 of worst-case clock speed (which would be the 32.768 kHz slow clock).
+
+jtag_rclk 5
+
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm926ejs
+
+# Establish internal SRAM memory work areas that are important to pre-bootstrap loaders, etc. The
+# AT91SAM9G20 has two SRAM areas, one starting at 0x00200000 and the other starting at 0x00300000.
+# Both areas are 16 kB long.
+
+$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x00200000 -work-area-size 0x4000 -work-area-backup 1
+$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x00300000 -work-area-size 0x4000 -work-area-backup 1
+
+# If you don't want to execute built-in boot rom code (and there are good reasons at times not to do that) in the
+# AT91SAM9 family, the microcontroller is a lump on a log without initialization. Because this family has
+# some powerful features, we want to have a special function that handles "reset init". To do this we declare
+# an event handler where these special activities can take place.
+
+scan_chain
+$_TARGETNAME configure -event reset-init {at91sam9g20_init}
+
+# NandFlash configuration and definition
+# Future TBD
+
+proc read_register {register} {
+ set result ""
+ ocd_mem2array result 32 $register 1
+ return $result(0)
+}
+
+proc at91sam9g20_init { } {
+
+ # At reset AT91SAM9G20 chip runs on slow clock (32.768 kHz). To shift over to a normal clock requires
+ # a number of steps that must be carefully performed. The process outline below follows the
+ # recommended procedure outlined in the AT91SAM9G20 technical manual.
+ #
+ # Several key and very important things to keep in mind:
+ # The SDRAM parts used currently on the Atmel evaluation board are -75 grade parts. This
+ # means the master clock (MCLK) must be at or below 133 MHz or timing errors will occur. The processor
+ # core can operate up to 400 MHz and therefore PCLK must be at or below this to function properly.
+
+ jtag_khz 2 # Slow-speed oscillator enabled at reset, so run jtag speed slow.
+ halt # Make sure processor is halted, or error will result in following steps.
+ mww 0xfffffd08 0xa5000501 # RSTC_MR : enable user reset.
+ mww 0xfffffd44 0x00008000 # WDT_MR : disable watchdog.
+
+ # Enable the main 18.432 MHz oscillator in CKGR_MOR register.
+ # Wait for MOSCS in PMC_SR to assert indicating oscillator is again stable after change to CKGR_MOR.
+
+ mww 0xfffffc20 0x00004001
+ while { [expr [read_register 0xfffffc68] & 0x01] != 1 } { sleep 1 }
+
+ # Set PLLA Register for 792.576 MHz (divider: bypass, multiplier: 43).
+ # Wait for LOCKA signal in PMC_SR to assert indicating PLLA is stable.
+
+ mww 0xfffffc28 0x202a3f01
+ while { [expr [read_register 0xfffffc68] & 0x02] != 2 } { sleep 1 }
+
+ # Set master system clock prescaler divide by 6 and processor clock divide by 2 in PMC_MCKR.
+ # Wait for MCKRDY signal from PMC_SR to assert.
+
+ mww 0xfffffc30 0x00000101
+ while { [expr [read_register 0xfffffc68] & 0x08] != 8 } { sleep 1 }
+
+ # Now change PMC_MCKR register to select PLLA.
+ # Wait for MCKRDY signal from PMC_SR to assert.
+
+ mww 0xfffffc30 0x00001302
+ while { [expr [read_register 0xfffffc68] & 0x08] != 8 } { sleep 1 }
+
+ # Processor and master clocks are now operating and stable at maximum frequency possible:
+ # -> MCLK = 132.096 MHz
+ # -> PCLK = 396.288 MHz
+
+ # Switch over to adaptive clocking.
+
+ jtag_khz 0
+
+ # Enable faster DCC downloads.
+
+ arm7_9 dcc_downloads enable
+
+ # To be able to use external SDRAM, several peripheral configuration registers must
+ # be modified. The first change is made to PIO_ASR to select peripheral functions
+ # for D15 through D31. The second change is made to the PIO_PDR register to disable
+ # this for D15 through D31.
+
+ mww 0xfffff870 0xffff0000
+ mww 0xfffff804 0xffff0000
+
+ # The EBI chip select register EBI_CS must be specifically configured to enable the internal SDRAM controller
+ # using CS1. Additionally we want CS3 assigned to NandFlash. Also VDDIO is connected physically on
+ # the board to the 3.3 VDC power supply so set the appropriate register bit to notify the micrcontroller.
+
+ mww 0xffffef1c 0x000100a
+
+ # The AT91SAM9G20-EK evaluation board has built-in NandFlash. The exact physical timing characteristics
+ # for the memory type used on the current board (MT29F2G08AACWP) can be established by setting
+ # four registers in order: SMC_SETUP3, SMC_PULSE3, SMC_CYCLE3, and SMC_MODE3.
+
+ mww 0xffffec30 0x00020002
+ mww 0xffffec34 0x04040404
+ mww 0xffffec38 0x00070007
+ mww 0xffffec3c 0x00030003
+
+ # Identify NandFlash bank 0. Disabled at the moment because a memory driver is not yet complete.
+
+# nand probe 0
+
+ # Now setup SDRAM. This is tricky and configuration is very important for reliability! The current calculations
+ # are based on 2 x Micron MT48LC16M16A2-75 memory (4 M x 16 bit x 4 banks). If you use this file as a reference
+ # for a new board that uses different SDRAM devices or clock rates, you need to recalculate the value inserted
+ # into the SDRAM_CR register. Using the memory datasheet for the -75 grade part and assuming a master clock
+ # of 132.096 MHz then the SDCLK period is equal to 7.6 ns. This means the device requires:
+ #
+ # CAS latency = 3 cycles
+ # TXSR = 10 cycles
+ # TRAS = 6 cycles
+ # TRCD = 3 cycles
+ # TRP = 3 cycles
+ # TRC = 9 cycles
+ # TWR = 2 cycles
+ # 9 column, 13 row, 4 banks
+ # refresh equal to or less then 7.8 us for commerical/industrial rated devices
+ #
+ # Thus SDRAM_CR = 0xa6339279
+
+ mww 0xffffea08 0xa6339279
+
+ # Next issue a 'NOP' command through the SDRAMC_MR register followed by writing a zero value into
+ # the starting memory location for the SDRAM.
+
+ mww 0xffffea00 0x00000001
+ mww 0x20000000 0
+
+ # Issue an 'All Banks Precharge' command through the SDRAMC_MR register followed by writing a zero
+ # value into the starting memory location for the SDRAM.
+
+ mww 0xffffea00 0x00000002
+ mww 0x20000000 0
+
+ # Now issue an 'Auto-Refresh' command through the SDRAMC_MR register. Follow this operation by writing
+ # zero values eight times into the starting memory location for the SDRAM.
+
+ mww 0xffffea00 0x4
+ mww 0x20000000 0
+ mww 0x20000000 0
+ mww 0x20000000 0
+ mww 0x20000000 0
+ mww 0x20000000 0
+ mww 0x20000000 0
+ mww 0x20000000 0
+ mww 0x20000000 0
+
+ # Almost done, so next issue a 'Load Mode Register' command followed by a zero value write to the
+ # the starting memory location for the SDRAM.
+
+ mww 0xffffea00 0x3
+ mww 0x20000000 0
+
+ # Signal normal mode using the SDRAMC_MR register and follow with a zero value write the the starting
+ # memory location for the SDRAM.
+
+ mww 0xffffea00 0x0
+ mww 0x20000000 0
+
+ # Finally set the refresh rate to about every 7 us (7.5 ns x 924 cycles).
+
+ mww 0xffffea04 0x0000039c
+}
+
projects / openocd / commitdiff