ARM: add "core_type" field to "struct arm"

It's used to flag cores with the "TrustZone" extension,
and is used in subsequent patches to set up support for
the registers shadowed by its new secure monitor mode.

The ARM1176 and Cortex-A8 both support this new mode.

Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>

diff --git a/src/target/arm11.c b/src/target/arm11.c
index 3a2358521040ff3a7e232267f1d9b42cc38178ab..6e007cfa41ce0dbbc0abeddf1074b52cac2c05f7 100644 (file)
--- a/src/target/arm11.c
+++ b/src/target/arm11.c
@@ -1780,6 +1780,11 @@ static int arm11_init_target(struct command_context *cmd_ctx,
                struct target *target)
 {
        /* Initialize anything we can set up without talking to the target */
+
+       /* FIXME Switch to use the standard build_reg_cache() not custom
+        * code.  Do it from examine(), after we check whether we're
+        * an arm1176 and thus support the Secure Monitor mode.
+        */
        return arm11_build_reg_cache(target);
 }
 
@@ -1787,7 +1792,7 @@ static int arm11_init_target(struct command_context *cmd_ctx,
 static int arm11_examine(struct target *target)
 {
        int retval;
-
+       char *type;
        FNC_INFO;
        struct arm11_common *arm11 = target_to_arm11(target);
 
@@ -1818,13 +1823,21 @@ static int arm11_examine(struct target *target)
 
        switch (arm11->device_id & 0x0FFFF000)
        {
-       case 0x07B36000:        LOG_INFO("found ARM1136"); break;
-       case 0x07B56000:        LOG_INFO("found ARM1156"); break;
-       case 0x07B76000:        LOG_INFO("found ARM1176"); break;
+       case 0x07B36000:
+               type = "ARM1136";
+               break;
+       case 0x07B56000:
+               type = "ARM1156";
+               break;
+       case 0x07B76000:
+               arm11->arm.core_type = ARM_MODE_MON;
+               type = "ARM1176";
+               break;
        default:
                LOG_ERROR("'target arm11' expects IDCODE 0x*7B*7****");
                return ERROR_FAIL;
        }
+       LOG_INFO("found %s", type);
 
        arm11->debug_version = (arm11->didr >> 16) & 0x0F;
 

diff --git a/src/target/armv4_5.c b/src/target/armv4_5.c
index d22e0f3ac603dea077e5d9485143cf5abeb7085c..3e27ba4183cdb3783482a8d428380566001d4a60 100644 (file)
--- a/src/target/armv4_5.c
+++ b/src/target/armv4_5.c
@@ -1015,5 +1015,8 @@ int armv4_5_init_arch_info(struct target *target, struct arm *armv4_5)
        armv4_5->core_state = ARMV4_5_STATE_ARM;
        armv4_5->core_mode = ARMV4_5_MODE_USR;
 
+       /* core_type may be overridden by subtype logic */
+       armv4_5->core_type = ARMV4_5_MODE_ANY;
+
        return ERROR_OK;
 }

diff --git a/src/target/armv4_5.h b/src/target/armv4_5.h
index 81eac476d8871d683f8b2931c28982bed4560fa6..f9aa4baf7ef8b372b6ebebcf476761a9a7817cc6 100644 (file)
--- a/src/target/armv4_5.h
+++ b/src/target/armv4_5.h
@@ -89,7 +89,15 @@ struct arm
        int common_magic;
        struct reg_cache *core_cache;
 
-       int /* armv4_5_mode */ core_mode;
+       /**
+        * Indicates what registers are in the ARM state core register set.
+        * ARMV4_5_MODE_ANY indicates the standard set of 37 registers,
+        * seen on for example ARM7TDMI cores.  ARM_MODE_MON indicates three
+        * more registers are shadowed, for "Secure Monitor" mode.
+        */
+       enum armv4_5_mode core_type;
+
+       enum armv4_5_mode core_mode;
        enum armv4_5_state core_state;
 
        /** Flag reporting unavailability of the BKPT instruction. */

diff --git a/src/target/cortex_a8.c b/src/target/cortex_a8.c
index 04b3f872b496b1baf8aa074fee189ac0c5a1912b..f8ff3920e3eff553ec28ba52960bf9ce423e9355 100644 (file)
--- a/src/target/cortex_a8.c
+++ b/src/target/cortex_a8.c
@@ -1423,6 +1423,8 @@ static void cortex_a8_build_reg_cache(struct target *target)
        struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
        struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
 
+       armv4_5->core_type = ARM_MODE_MON;
+
        (*cache_p) = armv4_5_build_reg_cache(target, armv4_5);
        armv4_5->core_cache = (*cache_p);
 }