Start a new demo for a new SH2A port.

git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@943 1d2547de-c912-0410-9cb9-b8ca96c0e9e2

diff --git a/Demo/SuperH_SH7216_Renesas/RTOSDemo.hws b/Demo/SuperH_SH7216_Renesas/RTOSDemo.hws
new file mode 100644 (file)
index 0000000..b679a05
--- /dev/null
+++ b/Demo/SuperH_SH7216_Renesas/RTOSDemo.hws
@@ -0,0 +1,41 @@
+[HIMDBVersion]\r
+2.0\r
+[DATABASE_VERSION]\r
+"11.0" \r
+[WORKSPACE_DETAILS]\r
+"RTOSDemo" "C:\E\Dev\FreeRTOS\WorkingCopy\Demo\SuperH_SH7216_Renesas" "C:\E\Dev\FreeRTOS\WorkingCopy\Demo\SuperH_SH7216_Renesas\RTOSDemo.hws" "SuperH RISC engine" "Renesas SuperH Standard" \r
+[SHARED_WORKSPACE_CONTROL_STATUS]\r
+"" "" "" \r
+"" "" "" \r
+[PROJECTS]\r
+"RTOSDemo" "C:\E\Dev\FreeRTOS\WorkingCopy\Demo\SuperH_SH7216_Renesas\RTOSDemo" "C:\E\Dev\FreeRTOS\WorkingCopy\Demo\SuperH_SH7216_Renesas\RTOSDemo\RTOSDemo.hwp" 0 \r
+[INFORMATION]\r
+"No workspace information available" \r
+[SCRAP]\r
+[PROJECT_DEPENDENCY]\r
+[WORKSPACE_PROPERTIES]\r
+[HELP_FILES]\r
+"c:\devtools\renesas\hew\tools\renesas\sh\9_3_2\hew\stdlib.chm" "C/C++ Standard Library Help" 1 \r
+[GENERAL_DATA_PROJECT]\r
+[USERMENUTOOLS]\r
+[CUSTOMPLACEHOLDERS]\r
+[MAKEFILE_BUILD_INFO]\r
+"$(WORKSPDIR)\make\$(PROJECTNAME)_$(CONFIGNAME).mak" "" "$(WORKSPDIR)\make" 0 0 0 \r
+[VD_CONFIGURATION_OPTIONS]\r
+"ACTIVE_DESKTOP" "0" \r
+[VD_CONFIGURATIONS]\r
+"0" "Default1" "1" \r
+"1" "Default2" "1" \r
+"2" "Default3" "1" \r
+"3" "Default4" "1" \r
+[OPTIONS_DEBUG_TAB]\r
+0 0 0 0 0 \r
+[VCS]\r
+"" "" "" 0 \r
+[VCS_PROJECT]\r
+[MAKEFILE_ENV_STRINGS]\r
+[MAKEFILE_ENV_FLAGS]\r
+1 0 0 \r
+[MAKEFILE_CLEAN_INFO]\r
+"" \r
+[END]\r

diff --git a/Demo/SuperH_SH7216_Renesas/RTOSDemo.tws b/Demo/SuperH_SH7216_Renesas/RTOSDemo.tws
new file mode 100644 (file)
index 0000000..d401e2c
--- /dev/null
+++ b/Demo/SuperH_SH7216_Renesas/RTOSDemo.tws
@@ -0,0 +1,15 @@
+[HIMDBVersion]\r
+2.0\r
+[DATABASE_VERSION]\r
+"1.2" \r
+[CURRENT_PROJECT]\r
+"RTOSDemo" \r
+[GENERAL_DATA]\r
+[BREAKPOINTS]\r
+[OPEN_WORKSPACE_FILES]\r
+"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\SuperH_SH7216_Renesas\RTOSDemo\main.c" \r
+[WORKSPACE_FILE_STATES]\r
+"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\SuperH_SH7216_Renesas\RTOSDemo\main.c" -4 -23 1400 586 1 0 \r
+[LOADED_PROJECTS]\r
+"RTOSDemo" \r
+[END]\r

diff --git a/Demo/SuperH_SH7216_Renesas/RTOSDemo/RTOSDemo.c b/Demo/SuperH_SH7216_Renesas/RTOSDemo/RTOSDemo.c
new file mode 100644 (file)
index 0000000..03891c5
--- /dev/null
+++ b/Demo/SuperH_SH7216_Renesas/RTOSDemo/RTOSDemo.c
@@ -0,0 +1,15 @@
+\r
+void main(void);\r
+\r
+void main(void)\r
+{\r
+volatile unsigned long ul;\r
+\r
+       for( ;; )\r
+       {\r
+               ul++;\r
+               ul++;\r
+       }\r
+}\r
+\r
+\r

diff --git a/Demo/SuperH_SH7216_Renesas/RTOSDemo/RTOSDemo.hwp b/Demo/SuperH_SH7216_Renesas/RTOSDemo/RTOSDemo.hwp
new file mode 100644 (file)
index 0000000..c3fcd4c
--- /dev/null
+++ b/Demo/SuperH_SH7216_Renesas/RTOSDemo/RTOSDemo.hwp
@@ -0,0 +1,163 @@
+[HIMDBVersion]\r
+2.0\r
+[DATABASE_VERSION]\r
+"2.8" \r
+[PROJECT_DETAILS]\r
+"RTOSDemo" "C:\E\Dev\FreeRTOS\WorkingCopy\Demo\SuperH_SH7216_Renesas\RTOSDemo" "C:\E\Dev\FreeRTOS\WorkingCopy\Demo\SuperH_SH7216_Renesas\RTOSDemo\RTOSDemo.hwp" "SuperH RISC engine" "Renesas SuperH Standard" "Application" "SH2A-FPU" "Other" \r
+[INFORMATION]\r
+"No project information available" \r
+[TOOL_CHAIN]\r
+"Renesas SuperH RISC engine Standard Toolchain" "9.3.2.0" \r
+[CONFIGURATIONS]\r
+"Debug_SH7216_E10A-USB_SYSTEM__SH" "C:\E\Dev\FreeRTOS\WorkingCopy\Demo\SuperH_SH7216_Renesas\RTOSDemo\Debug_SH7216_E10A-USB_SYSTEM__SH" \r
+[BUILD_PHASES]\r
+"Renesas OptLinker" 1 \r
+"Renesas SH Assembler" 1 \r
+"Renesas SH C/C++ Compiler" 1 \r
+"Renesas SH C/C++ Library Generator" 1 \r
+[TOOL_ENVIRONMENT]\r
+[EXTENSIONS]\r
+"Absolute file" "ABS" \r
+"Assembly include file" "INC" \r
+"Assembly list file" "LIS" \r
+"Assembly source file" "ASM" \r
+"Assembly source file" "SRC" \r
+"Binary file" "BIN" \r
+"C header file" "H" \r
+"C list file" "LST" \r
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+"Expanded assembly source file" "EXP" \r
+"Hex file" "HEX" \r
+"Library file" "LIB" \r
+"Library information file" "LBP" \r
+"Linkage map file" "MAP" \r
+"Linkage symbol file" "FSY" \r
+"Object file" "OBJ" \r
+"Optimize map file" "bls" \r
+"Preprocessed C source file" "P" \r
+"Preprocessed C++ source file" "PP" \r
+"Profile file" "PRO" \r
+"Relocatable file" "REL" \r
+"Rts information file" "RTS" \r
+"S-Record file" "MOT" \r
+"Stack information file" "SNI" \r
+"TD include object file" "RTI" \r
+[FILE_GROUPS]\r
+"Absolute file" "BIN" "NONE" "" \r
+"Assembly include file" "TEXT" "EDITOR" "" \r
+"Assembly list file" "TEXT" "EDITOR" "" \r
+"Assembly source file" "TEXT" "EDITOR" "" \r
+"Binary file" "BIN" "NONE" "" \r
+"C header file" "TEXT" "EDITOR" "" \r
+"C list file" "TEXT" "EDITOR" "" \r
+"C source file" "TEXT" "EDITOR" "" \r
+"C++ header file" "TEXT" "EDITOR" "" \r
+"C++ list file" "TEXT" "EDITOR" "" \r
+"C++ source file" "TEXT" "EDITOR" "" \r
+"CPU information file" "BIN" "NONE" "" \r
+"Calling information file" "BIN" "NONE" "" \r
+"Debug information file" "BIN" "NONE" "" \r
+"Expanded assembly source file" "TEXT" "EDITOR" "" \r
+"Hex file" "TEXT" "EDITOR" "" \r
+"Library file" "BIN" "NONE" "" \r
+"Library information file" "TEXT" "EDITOR" "" \r
+"Linkage map file" "TEXT" "EDITOR" "" \r
+"Linkage symbol file" "TEXT" "EDITOR" "" \r
+"Object file" "BIN" "NONE" "" \r
+"Optimize map file" "BIN" "NONE" "" \r
+"Preprocessed C source file" "TEXT" "EDITOR" "" \r
+"Preprocessed C++ source file" "TEXT" "EDITOR" "" \r
+"Profile file" "BIN" "NONE" "" \r
+"Relocatable file" "BIN" "NONE" "" \r
+"Rts information file" "BIN" "NONE" "" \r
+"S-Record file" "TEXT" "EDITOR" "" \r
+"Stack information file" "BIN" "NONE" "" \r
+"TD include object file" "BIN" "NONE" "" \r
+[ASSOCIATED_APPLICATIONS]\r
+[TOOLCHAIN_PHASE]\r
+"Renesas OptLinker" \r
+"Renesas SH Assembler" \r
+"Renesas SH C/C++ Compiler" \r
+"Renesas SH C/C++ Library Generator" \r
+[UTILITY_PHASE]\r
+[CUSTOM_PHASES]\r
+[CUSTOM_PHASE_INPUT_GROUP]\r
+[CUSTOM_PHASE_OUTPUT_SYNTAX]\r
+[BUILD_ORDER]\r
+"Renesas SH C/C++ Library Generator" 1 \r
+"Renesas SH C/C++ Compiler" 1 \r
+"Renesas SH Assembler" 1 \r
+"Renesas OptLinker" 1 \r
+[BUILD_PHASE_DETAILS]\r
+"Renesas OptLinker" "Object file|Library file|Relocatable file" 0 \r
+"Renesas SH Assembler" "Assembly source file|Linkage symbol file" 1 \r
+"Renesas SH C/C++ Compiler" "C source file|C++ source file" 1 \r
+"Renesas SH C/C++ Library Generator" "" 0 \r
+[BUILD_FILE_ORDER_Assembly source file]\r
+"Renesas SH Assembler" 1 \r
+[BUILD_FILE_ORDER_C source file]\r
+"Renesas SH C/C++ Compiler" 1 \r
+[BUILD_FILE_ORDER_C++ source file]\r
+"Renesas SH C/C++ Compiler" 1 \r
+[BUILD_FILE_ORDER_Linkage symbol file]\r
+"Renesas SH Assembler" 1 \r
+[SCRAP]\r
+"Project Generator Setup File" "$(PROJDIR)\RTOSDemo.pgs" \r
+[MAPPINGS]\r
+"Assembly source file" "Renesas SH Assembler" "Renesas SH C/C++ Compiler" \r
+"Library file" "Renesas OptLinker" "Renesas SH C/C++ Library Generator" \r
+"Object file" "Renesas OptLinker" "Renesas SH Assembler" \r
+"Object file" "Renesas OptLinker" "Renesas SH C/C++ Compiler" \r
+[PROJECT_FILES]\r
+"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\SuperH_SH7216_Renesas\RTOSDemo\dbsct.c" "User" "C source file" 2 \r
+"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\SuperH_SH7216_Renesas\RTOSDemo\intprg.c" "User" "C source file" 2 \r
+"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\SuperH_SH7216_Renesas\RTOSDemo\main.c" "User" "C source file" 2 \r
+"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\SuperH_SH7216_Renesas\RTOSDemo\resetprg.c" "User" "C source file" 2 \r
+"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\SuperH_SH7216_Renesas\RTOSDemo\vecttbl.c" "User" "C source file" 2 \r
+[FOLDER]\r
+"C source file" "C source file" \r
+[GENERAL_DATA_PROJECT]\r
+"USE_CUSTOM_LINKAGE_ORDER" "0" \r
+[ON_DEMAND_COMPONENTS_LOADED]\r
+[SYNC_SESSION_NAMES]\r
+[SESSIONS]\r
+"SessionSH7216_E10A-USB_SYSTEM__SH" "C:\E\Dev\FreeRTOS\WorkingCopy\Demo\SuperH_SH7216_Renesas\RTOSDemo\SessionSH7216_E10A-USB_SYSTEM__SH.hsf" 0 \r
+[GENERAL_DATA_SESSION_SessionSH7216_E10A-USB_SYSTEM__SH]\r
+[OPTIONS_Debug_SH7216_E10A-USB_SYSTEM__SH_Renesas OptLinker]\r
+"Single Shot" "00fbbc001d68ac10" 4 \r
+[OPTIONS_Debug_SH7216_E10A-USB_SYSTEM__SH_Renesas SH Assembler]\r
+"Assembly source file" "075d11aefc68ac10" 3 \r
+"Linkage symbol file" "075d11aefc68ac10" 3 \r
+[OPTIONS_Debug_SH7216_E10A-USB_SYSTEM__SH_Renesas SH C/C++ Compiler]\r
+"C source file" "075d11aefc68ac10" 2 \r
+"C++ source file" "075d11aefc68ac10" 2 \r
+"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\SuperH_SH7216_Renesas\RTOSDemo\dbsct.c" "075d11aefc68ac10" 2 \r
+"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\SuperH_SH7216_Renesas\RTOSDemo\intprg.c" "075d11aefc68ac10" 2 \r
+"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\SuperH_SH7216_Renesas\RTOSDemo\main.c" "01407c001d68ac10" 2 \r
+"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\SuperH_SH7216_Renesas\RTOSDemo\resetprg.c" "075d11aefc68ac10" 2 \r
+"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\SuperH_SH7216_Renesas\RTOSDemo\vecttbl.c" "075d11aefc68ac10" 2 \r
+[OPTIONS_Debug_SH7216_E10A-USB_SYSTEM__SH_Renesas SH C/C++ Library Generator]\r
+"Single Shot" "075d11aefc68ac10" 1 \r
+[OPTIONS_Debug_SH7216_E10A-USB_SYSTEM__SH]\r
+"" 0 \r
+"[S|OUTPUTPATH|^"$(CONFIGDIR)\$(PROJECTNAME).lib^"] [V|VERSION|7] [S|CPU|SH2AFPU] [S|ENDIAN|BIG] [S|ROUND|ZERO] [B|DENORMALIZE|0] [B|SPEED|0] [B|RUNTIME|1] [B|NEW|0] [B|CTYPE|0] [B|MATH|0] [B|MATHF|0] [B|STDARG|0] [B|STDIO|0] [B|STDLIB|1] [B|STRING|1] [B|IOS|0] [B|COMPLEX|0] [B|CPPSTRING|0] [S|MODE|BUILD/CHANGED]" 1 \r
+"[V|VERSION|6] [B|DEBUG|1] [S|OUTPUTPATH|^"$(CONFIGDIR)\$(FILELEAF).obj^"] [B|LIST|0] [B|CHGINCPATH|1] [B|ERRORPATH|1] [S|CPU|SH2AFPU] [S|ENDIAN|BIG] [S|ROUND|ZERO] [B|DENORMALIZE|0]" 3 \r
+"[V|VERSION|6] [B|OPTIMIZE|0] [B|DEBUG|1] [S|OUTPUT|^"$(CONFIGDIR)\$(PROJECTNAME).abs^"] [S|ROM|(D,R)] [B|LIST|1] [S|LIST|^"$(CONFIGDIR)\$(PROJECTNAME).map^"] [S|FORM|STYPE] [S|OUTPUT|^"$(CONFIGDIR)\$(PROJECTNAME).mot^"] [S|START|DVECTTBL,DINTTBL(000000000)|PResetPRG,PIntPRG(000000800)|P,C,C$BSEC,C$DSEC,D(000001000)|B,R(0FFF80000)|S(0FFFBFC00)]" 4 \r
+"[V|VERSION|7] [B|DEBUG|1] [S|OUTPUTPATH|^"$(CONFIGDIR)\$(FILELEAF).obj^"] [B|LIST|0] [B|CHGINCPATH|1] [B|ERRORPATH|1] [S|CPU|SH2AFPU] [S|ENDIAN|BIG] [S|ROUND|ZERO] [B|DENORMALIZE|0]" 2 \r
+[EXCLUDED_FILES_Debug_SH7216_E10A-USB_SYSTEM__SH]\r
+[LINKAGE_ORDER_Debug_SH7216_E10A-USB_SYSTEM__SH]\r
+[GENERAL_DATA_CONFIGURATION_Debug_SH7216_E10A-USB_SYSTEM__SH]\r
+[GENERAL_DATA_CONFIGURATION_SESSION_Debug_SH7216_E10A-USB_SYSTEM__SH_SessionSH7216_E10A-USB_SYSTEM__SH]\r
+[SESSION_DATA_CONFIGURATION_SESSION_Debug_SH7216_E10A-USB_SYSTEM__SH_SessionSH7216_E10A-USB_SYSTEM__SH]\r
+"MEMORY_MAPPING_OPTIONS" "Unknown Options" \r
+[EXT_DEBUGGER_INFO]\r
+0 "" "" "" "" \r
+[END]\r

diff --git a/Demo/SuperH_SH7216_Renesas/RTOSDemo/RTOSDemo.nav b/Demo/SuperH_SH7216_Renesas/RTOSDemo/RTOSDemo.nav
new file mode 100644 (file)
index 0000000..86dfd15
Binary files /dev/null and b/Demo/SuperH_SH7216_Renesas/RTOSDemo/RTOSDemo.nav differ

diff --git a/Demo/SuperH_SH7216_Renesas/RTOSDemo/RTOSDemo.pgs b/Demo/SuperH_SH7216_Renesas/RTOSDemo/RTOSDemo.pgs
new file mode 100644 (file)
index 0000000..5aa07f7
--- /dev/null
+++ b/Demo/SuperH_SH7216_Renesas/RTOSDemo/RTOSDemo.pgs
@@ -0,0 +1,35 @@
+; Project Generator Setup Infomation
+
+[PGS Version]
+Version=1.0
+
+[Toolchain]
+Toolchain=Renesas SuperH Standard
+Toolchain Name=Renesas SuperH RISC engine Standard Toolchain
+Toolchain Version=9.3.2.0
+
+[CPU]
+CPU Family=SuperH RISC engine
+CPU Series=SH2A-FPU
+CPU Type=Other
+Operating Mode=Not Support
+Address Space=Not Support
+Multiple=Not Support
+Divide=Not Support
+
+[Project]
+Project Name=RTOSDemo
+Project Type=Application
+
+[Stack Settings]
+Stack Pointer Address=H'FFFC0000
+Stack Size=H'400
+Stack Section Name=S
+Stack Section Address=
+Source File Name=stacksct.h
+Description=#pragma stacksize 0x400         /* Do not modify this line. */
+Default Stack Pointer Address=H'FFFC0000
+Default Stack Size=H'400
+
+[Initial Settings]
+Simulator I/O=disable

diff --git a/Demo/SuperH_SH7216_Renesas/RTOSDemo/RTOSDemo.tps b/Demo/SuperH_SH7216_Renesas/RTOSDemo/RTOSDemo.tps
new file mode 100644 (file)
index 0000000..804f6fa
--- /dev/null
+++ b/Demo/SuperH_SH7216_Renesas/RTOSDemo/RTOSDemo.tps
@@ -0,0 +1,20 @@
+[HIMDBVersion]\r
+2.0\r
+[DATABASE_VERSION]\r
+"1.1" \r
+[SESSIONS_]\r
+"SessionSH7216_E10A-USB_SYSTEM__SH" \r
+[CONFIGURATIONS]\r
+"Debug_SH7216_E10A-USB_SYSTEM__SH" \r
+[CURRENT_CONFIGURATION]\r
+"Debug_SH7216_E10A-USB_SYSTEM__SH" \r
+[CURRENT_SESSION]\r
+"SessionSH7216_E10A-USB_SYSTEM__SH" \r
+[GENERAL_DATA_PROJECT]\r
+[GENERAL_DATA_CONFIGURATION_Debug_SH7216_E10A-USB_SYSTEM__SH]\r
+"PROJECT_FILES_MODIFIED_DATA_TAG" "FALSE" \r
+[SESSIONS_Debug_SH7216_E10A-USB_SYSTEM__SH]\r
+"SessionSH7216_E10A-USB_SYSTEM__SH" \r
+[GENERAL_DATA_SESSION_SessionSH7216_E10A-USB_SYSTEM__SH]\r
+[GENERAL_DATA_CONFIGURATION_SESSION_Debug_SH7216_E10A-USB_SYSTEM__SH_SessionSH7216_E10A-USB_SYSTEM__SH]\r
+[END]\r

diff --git a/Demo/SuperH_SH7216_Renesas/RTOSDemo/SessionSH7216_E10A-USB_SYSTEM__SH.hsf b/Demo/SuperH_SH7216_Renesas/RTOSDemo/SessionSH7216_E10A-USB_SYSTEM__SH.hsf
new file mode 100644 (file)
index 0000000..8d2d23b
--- /dev/null
+++ b/Demo/SuperH_SH7216_Renesas/RTOSDemo/SessionSH7216_E10A-USB_SYSTEM__SH.hsf
@@ -0,0 +1,324 @@
+[HIMDBVersion]\r
+2.0\r
+[DATABASE_VERSION]\r
+"2.3" \r
+[SESSION_DETAILS]\r
+"" \r
+[INFORMATION]\r
+"" \r
+[GENERAL_DATA]\r
+"FIRST_CONNECTION_TAG" "NO" \r
+"RESET_CPU_AFTER_DOWNLOAD_TAG" "VARIANT_FALSE_STORE_TAG" \r
+"{08009853-4189-4ADA-848F-0F1A84AFE443}MonitorCtrlLabelAddress" "" \r
+"{08009853-4189-4ADA-848F-0F1A84AFE443}MonitorCtrlMonitorLastSaveLogDirectory" "" \r
+"{08009853-4189-4ADA-848F-0F1A84AFE443}MonitorCtrlViews" "0" \r
+"{287A8023-99B5-49E1-A54E-4DDCA43D7959}MapCtrlECX_MAP_FIND_SYMBOL_LIST" "" \r
+"{287A8023-99B5-49E1-A54E-4DDCA43D7959}MapCtrlViews" "0" \r
+"{2BA6A3EE-6488-11D5-80D4-00C04F68EAD7}ECXLABEL_ADDDLG_ADDR" "" \r
+"{2BA6A3EE-6488-11D5-80D4-00C04F68EAD7}LabelCtrlSymbolFileDir" "" \r
+"{2BA6A3EE-6488-11D5-80D4-00C04F68EAD7}LabelCtrlSymbolFileName" "" \r
+"{2BA6A3EE-6488-11D5-80D4-00C04F68EAD7}LabelCtrlViews" "0" \r
+"{2BA6A3EF-6488-11D5-80D4-00C04F68EAD7}StatusCtrlViews" "0" \r
+"{30F726A1-F13D-4E21-9A4F-FD7FF70EDFDA}TraceCtrlSaveFileDir" "" \r
+"{30F726A1-F13D-4E21-9A4F-FD7FF70EDFDA}TraceCtrlSaveFileName" "" \r
+"{30F726A1-F13D-4E21-9A4F-FD7FF70EDFDA}TraceCtrlViews" "0" \r
+"{313F4FC1-6566-11D5-8BBE-0004E2013C71}CmdLineCtrlBatchFileName" "" \r
+"{313F4FC1-6566-11D5-8BBE-0004E2013C71}CmdLineCtrlBreakpointFlag" "-1 " \r
+"{313F4FC1-6566-11D5-8BBE-0004E2013C71}CmdLineCtrlBreakpointStatus" "-1 " \r
+"{313F4FC1-6566-11D5-8BBE-0004E2013C71}CmdLineCtrlBrowseDirectory" "" \r
+"{313F4FC1-6566-11D5-8BBE-0004E2013C71}CmdLineCtrlLogFileName" "" \r
+"{313F4FC1-6566-11D5-8BBE-0004E2013C71}CmdLineCtrlSplitterPosition" "242" \r
+"{313F4FC1-6566-11D5-8BBE-0004E2013C71}CmdLineCtrlViews" "0" \r
+"{313F4FC1-6566-11D5-8BBE-0004E2013C71}TclTkCtrlLogFileName" "" \r
+"{313F4FC2-6566-11D5-8BBE-0004E2013C71}ECX_MEMORY_COMPARE_END_ADDRESS" "" \r
+"{313F4FC2-6566-11D5-8BBE-0004E2013C71}ECX_MEMORY_COMPARE_START_ADDRESS" "" \r
+"{313F4FC2-6566-11D5-8BBE-0004E2013C71}ECX_MEMORY_DISPLAY_DEST_ADDRESS" "" \r
+"{313F4FC2-6566-11D5-8BBE-0004E2013C71}ECX_MEMORY_DISPLAY_END_ADDRESS" "" \r
+"{313F4FC2-6566-11D5-8BBE-0004E2013C71}ECX_MEMORY_DISPLAY_START_ADDRESS" "" \r
+"{313F4FC2-6566-11D5-8BBE-0004E2013C71}ECX_MEMORY_FILL_END_ADDRESS" "" \r
+"{313F4FC2-6566-11D5-8BBE-0004E2013C71}ECX_MEMORY_FILL_START_ADDRESS" "" \r
+"{313F4FC2-6566-11D5-8BBE-0004E2013C71}ECX_MEMORY_MOVE_END_ADDRESS" "" \r
+"{313F4FC2-6566-11D5-8BBE-0004E2013C71}ECX_MEMORY_MOVE_START_ADDRESS" "" \r
+"{313F4FC2-6566-11D5-8BBE-0004E2013C71}ECX_MEMORY_SEARCH_END_ADDRESS" "" \r
+"{313F4FC2-6566-11D5-8BBE-0004E2013C71}ECX_MEMORY_SEARCH_START_ADDRESS" "" \r
+"{313F4FC2-6566-11D5-8BBE-0004E2013C71}ECX_MEMORY_SET_DEST_ADDRESS" "" \r
+"{313F4FC2-6566-11D5-8BBE-0004E2013C71}ECX_MEMORY_TEST_END_ADDRESS" "" \r
+"{313F4FC2-6566-11D5-8BBE-0004E2013C71}ECX_MEMORY_TEST_START_ADDRESS" "" \r
+"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryCtrlViews" "0" \r
+"{5F75FDA0-6FF0-11D5-B7CE-00E029352378}PACtrlSaveFileDir" "" \r
+"{5F75FDA0-6FF0-11D5-B7CE-00E029352378}PACtrlSaveFileName" "" \r
+"{5F75FDA0-6FF0-11D5-B7CE-00E029352378}PACtrlViews" "0" \r
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+"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOCtrlSaveFileName" "" \r
+"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOCtrlViews" "0" \r
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+[STATUSBAR_STATEINFO_VD1]\r
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+"[B|SIMIOF|1] [I|SIMIOADR|0x00000000] [S|ROM_MODE|^"^"] [S|MAP|^"^"] [S|RESOURCE|^"^"]" \r
+[DOWNLOAD_MODULES]\r
+"$(CONFIGDIR)\$(PROJECTNAME).abs" 0 "Elf/Dwarf2" 0 0 1 0 \r
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+"TRUE" \r
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+"FALSE" \r
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+"TRUE" \r
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+"FALSE" \r
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+"1" \r
+[COMMAND_FILES]\r
+[DEFAULT_DEBUG_FORMAT]\r
+"Elf/Dwarf2" \r
+[FLASH_DETAILS]\r
+"" 0 0 "" 0 "" 0 0 "" 0 0 0 0 0 0 0 "" "" "" "" "" \r
+[BREAKPOINTS]\r
+[END]\r

diff --git a/Demo/SuperH_SH7216_Renesas/RTOSDemo/SessionSH7216_E10A-USB_SYSTEM__SH.ini b/Demo/SuperH_SH7216_Renesas/RTOSDemo/SessionSH7216_E10A-USB_SYSTEM__SH.ini
new file mode 100644 (file)
index 0000000..4f273cf
--- /dev/null
+++ b/Demo/SuperH_SH7216_Renesas/RTOSDemo/SessionSH7216_E10A-USB_SYSTEM__SH.ini
@@ -0,0 +1,4 @@
+[E10A USB Cpu Select]\r
+FREQUENCY=12.50\r
+[Key]\r
+Key=1\r

diff --git a/Demo/SuperH_SH7216_Renesas/RTOSDemo/SessionSH7216_E10A-USB_SYSTEM__SH_Heush2acustom1.ini b/Demo/SuperH_SH7216_Renesas/RTOSDemo/SessionSH7216_E10A-USB_SYSTEM__SH_Heush2acustom1.ini
new file mode 100644 (file)
index 0000000..b82cebe
--- /dev/null
+++ b/Demo/SuperH_SH7216_Renesas/RTOSDemo/SessionSH7216_E10A-USB_SYSTEM__SH_Heush2acustom1.ini
@@ -0,0 +1,3 @@
+[E10A USB Cpu Select]\r
+CPU Select=5\r
+FREQUENCY=12.50\r

diff --git a/Demo/SuperH_SH7216_Renesas/RTOSDemo/dbsct.c b/Demo/SuperH_SH7216_Renesas/RTOSDemo/dbsct.c
new file mode 100644 (file)
index 0000000..5ee5205
--- /dev/null
+++ b/Demo/SuperH_SH7216_Renesas/RTOSDemo/dbsct.c
@@ -0,0 +1,30 @@
+/***********************************************************************/\r
+/*                                                                     */\r
+/*  FILE        :dbsct.c                                               */\r
+/*  DATE        :Sun, Dec 27, 2009                                     */\r
+/*  DESCRIPTION :Setting of B,R Section                                */\r
+/*  CPU TYPE    :Other                                                 */\r
+/*                                                                     */\r
+/*  This file is generated by Renesas Project Generator (Ver.4.16).    */\r
+/*                                                                     */\r
+/***********************************************************************/\r
+                  \r
+\r
+\r
+#include "typedefine.h"\r
+\r
+#pragma section $DSEC\r
+static const struct {\r
+    _UBYTE *rom_s;       /* Start address of the initialized data section in ROM */\r
+    _UBYTE *rom_e;       /* End address of the initialized data section in ROM   */\r
+    _UBYTE *ram_s;       /* Start address of the initialized data section in RAM */\r
+}   DTBL[] = {\r
+    { __sectop("D"), __secend("D"), __sectop("R") }\r
+};\r
+#pragma section $BSEC\r
+static const struct {\r
+    _UBYTE *b_s;         /* Start address of non-initialized data section */\r
+    _UBYTE *b_e;         /* End address of non-initialized data section */\r
+}   BTBL[] = {\r
+    { __sectop("B"), __secend("B") }\r
+};\r

diff --git a/Demo/SuperH_SH7216_Renesas/RTOSDemo/intprg.c b/Demo/SuperH_SH7216_Renesas/RTOSDemo/intprg.c
new file mode 100644 (file)
index 0000000..71a435a
--- /dev/null
+++ b/Demo/SuperH_SH7216_Renesas/RTOSDemo/intprg.c
@@ -0,0 +1,22 @@
+/***********************************************************************/\r
+/*                                                                     */\r
+/*  FILE        :intprg.c                                              */\r
+/*  DATE        :Sun, Dec 27, 2009                                     */\r
+/*  DESCRIPTION :Interrupt Program                                     */\r
+/*  CPU TYPE    :Other                                                 */\r
+/*                                                                     */\r
+/*  This file is generated by Renesas Project Generator (Ver.4.16).    */\r
+/*                                                                     */\r
+/***********************************************************************/\r
+                  \r
+\r
+\r
+#include <machine.h>\r
+#include "vect.h"\r
+#pragma section IntPRG\r
+\r
+// 4 Illegal code\r
+void INT_Illegal_code(void){/* sleep(); */}\r
+\r
+// Dummy\r
+void Dummy(void){/* sleep(); */}\r

diff --git a/Demo/SuperH_SH7216_Renesas/RTOSDemo/main.c b/Demo/SuperH_SH7216_Renesas/RTOSDemo/main.c
new file mode 100644 (file)
index 0000000..03891c5
--- /dev/null
+++ b/Demo/SuperH_SH7216_Renesas/RTOSDemo/main.c
@@ -0,0 +1,15 @@
+\r
+void main(void);\r
+\r
+void main(void)\r
+{\r
+volatile unsigned long ul;\r
+\r
+       for( ;; )\r
+       {\r
+               ul++;\r
+               ul++;\r
+       }\r
+}\r
+\r
+\r

diff --git a/Demo/SuperH_SH7216_Renesas/RTOSDemo/resetprg.c b/Demo/SuperH_SH7216_Renesas/RTOSDemo/resetprg.c
new file mode 100644 (file)
index 0000000..f3b5d30
--- /dev/null
+++ b/Demo/SuperH_SH7216_Renesas/RTOSDemo/resetprg.c
@@ -0,0 +1,106 @@
+/***********************************************************************/\r
+/*                                                                     */\r
+/*  FILE        :resetprg.c                                            */\r
+/*  DATE        :Sun, Dec 27, 2009                                     */\r
+/*  DESCRIPTION :Reset Program                                         */\r
+/*  CPU TYPE    :Other                                                 */\r
+/*                                                                     */\r
+/*  This file is generated by Renesas Project Generator (Ver.4.16).    */\r
+/*                                                                     */\r
+/***********************************************************************/\r
+                  \r
+\r
+\r
+#include       <machine.h>\r
+#include       <_h_c_lib.h>\r
+//#include     <stddef.h>                                      // Remove the comment when you use errno\r
+//#include     <stdlib.h>                                      // Remove the comment when you use rand()\r
+#include       "typedefine.h"\r
+#include       "stacksct.h"\r
+\r
+#define SR_Init    0x000000F0\r
+#ifdef _FPD    // when -fpu=double is specified\r
+#define FPSCR_Init 0x000C0001\r
+#else\r
+#define FPSCR_Init 0x00040001\r
+#endif\r
+#define INT_OFFSET 0x10\r
+\r
+extern _UINT INT_Vectors;\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+void PowerON_Reset_PC(void);\r
+void Manual_Reset_PC(void);\r
+void main(void);\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+//#ifdef __cplusplus                           // Enable I/O in the application(both SIM I/O and hardware I/O)\r
+//extern "C" {\r
+//#endif\r
+//extern void _INIT_IOLIB(void);\r
+//extern void _CLOSEALL(void);\r
+//#ifdef __cplusplus\r
+//}\r
+//#endif\r
+\r
+//extern void srand(_UINT);            // Remove the comment when you use rand()\r
+//extern _SBYTE *_s1ptr;                               // Remove the comment when you use strtok()\r
+               \r
+//#ifdef __cplusplus                           // Use Hardware Setup\r
+//extern "C" {\r
+//#endif\r
+//extern void HardwareSetup(void);\r
+//#ifdef __cplusplus\r
+//}\r
+//#endif\r
+       \r
+//#ifdef __cplusplus                   // Remove the comment when you use global class object\r
+//extern "C" {                                 // Sections C$INIT and C$END will be generated\r
+//#endif\r
+//extern void _CALL_INIT(void);\r
+//extern void _CALL_END(void);\r
+//#ifdef __cplusplus\r
+//}\r
+//#endif\r
+\r
+#pragma section ResetPRG\r
+\r
+#pragma entry PowerON_Reset_PC\r
+\r
+void PowerON_Reset_PC(void)\r
+{\r
+       set_vbr((void *)((_UBYTE *)&INT_Vectors - INT_OFFSET));\r
+\r
+       set_fpscr(FPSCR_Init);\r
+\r
+       _INITSCT();\r
+\r
+//     _CALL_INIT();                                   // Remove the comment when you use global class object\r
+\r
+//     _INIT_IOLIB();                                  // Enable I/O in the application(both SIM I/O and hardware I/O)\r
+\r
+//     errno=0;                                                // Remove the comment when you use errno\r
+//     srand((_UINT)1);                                        // Remove the comment when you use rand()\r
+//     _s1ptr=NULL;                                    // Remove the comment when you use strtok()\r
+\r
+//     HardwareSetup();                                // Use Hardware Setup\r
+\r
+       set_cr(SR_Init);\r
+\r
+       main();\r
+\r
+//     _CLOSEALL();                                    // Close I/O in the application(both SIM I/O andhardware I/O)\r
+\r
+//     _CALL_END();                                    // Remove the comment when you use global class object\r
+\r
+       sleep();\r
+}\r
+\r
+//#pragma entry Manual_Reset_PC                // Remove the comment when you use Manual Reset\r
+void Manual_Reset_PC(void)     \r
+{\r
+}\r

diff --git a/Demo/SuperH_SH7216_Renesas/RTOSDemo/stacksct.h b/Demo/SuperH_SH7216_Renesas/RTOSDemo/stacksct.h
new file mode 100644 (file)
index 0000000..fb2eddb
--- /dev/null
+++ b/Demo/SuperH_SH7216_Renesas/RTOSDemo/stacksct.h
@@ -0,0 +1,11 @@
+/***********************************************************************/\r
+/*                                                                     */\r
+/*  FILE        :stacksct.h                                            */\r
+/*  DATE        :Sun, Dec 27, 2009                                     */\r
+/*  DESCRIPTION :Setting of Stack area                                 */\r
+/*  CPU TYPE    :Other                                                 */\r
+/*                                                                     */\r
+/*  This file is generated by Renesas Project Generator (Ver.4.16).    */\r
+/*                                                                     */\r
+/***********************************************************************/\r
+#pragma stacksize 0x400         /* Do not modify this line. */\r

diff --git a/Demo/SuperH_SH7216_Renesas/RTOSDemo/typedefine.h b/Demo/SuperH_SH7216_Renesas/RTOSDemo/typedefine.h
new file mode 100644 (file)
index 0000000..372d680
--- /dev/null
+++ b/Demo/SuperH_SH7216_Renesas/RTOSDemo/typedefine.h
@@ -0,0 +1,23 @@
+/***********************************************************************/\r
+/*                                                                     */\r
+/*  FILE        :typedefine.h                                          */\r
+/*  DATE        :Sun, Dec 27, 2009                                     */\r
+/*  DESCRIPTION :Aliases of Integer Type                               */\r
+/*  CPU TYPE    :Other                                                 */\r
+/*                                                                     */\r
+/*  This file is generated by Renesas Project Generator (Ver.4.16).    */\r
+/*                                                                     */\r
+/***********************************************************************/\r
+                  \r
+\r
+\r
+typedef signed char _SBYTE;\r
+typedef unsigned char _UBYTE;\r
+typedef signed short _SWORD;\r
+typedef unsigned short _UWORD;\r
+typedef signed int _SINT;\r
+typedef unsigned int _UINT;\r
+typedef signed long _SDWORD;\r
+typedef unsigned long _UDWORD;\r
+typedef signed long long _SQWORD;\r
+typedef unsigned long long _UQWORD;\r

diff --git a/Demo/SuperH_SH7216_Renesas/RTOSDemo/vect.h b/Demo/SuperH_SH7216_Renesas/RTOSDemo/vect.h
new file mode 100644 (file)
index 0000000..4331b08
--- /dev/null
+++ b/Demo/SuperH_SH7216_Renesas/RTOSDemo/vect.h
@@ -0,0 +1,37 @@
+/***********************************************************************/\r
+/*                                                                     */\r
+/*  FILE        :vect.h                                                */\r
+/*  DATE        :Sun, Dec 27, 2009                                     */\r
+/*  DESCRIPTION :Definition of Vector                                  */\r
+/*  CPU TYPE    :Other                                                 */\r
+/*                                                                     */\r
+/*  This file is generated by Renesas Project Generator (Ver.4.16).    */\r
+/*                                                                     */\r
+/***********************************************************************/\r
+                  \r
+\r
+\r
+\r
+\r
+//;<<VECTOR DATA START (POWER ON RESET)>>\r
+//;0 Power On Reset PC\r
+extern void PowerON_Reset_PC(void);                                                                                                                \r
+\r
+//;<<VECTOR DATA END (POWER ON RESET)>>\r
+// 1 Power On Reset SP\r
+\r
+//;<<VECTOR DATA START (MANUAL RESET)>>\r
+//;2 Manual Reset PC\r
+extern void Manual_Reset_PC(void);                                                                                                                 \r
+\r
+//;<<VECTOR DATA END (MANUAL RESET)>>\r
+// 3 Manual Reset SP\r
+\r
+\r
+// 4 Illegal code\r
+#pragma interrupt INT_Illegal_code\r
+extern void INT_Illegal_code(void);\r
+\r
+// Dummy\r
+#pragma interrupt Dummy\r
+extern void Dummy(void);\r

diff --git a/Demo/SuperH_SH7216_Renesas/RTOSDemo/vecttbl.c b/Demo/SuperH_SH7216_Renesas/RTOSDemo/vecttbl.c
new file mode 100644 (file)
index 0000000..3382443
--- /dev/null
+++ b/Demo/SuperH_SH7216_Renesas/RTOSDemo/vecttbl.c
@@ -0,0 +1,39 @@
+/***********************************************************************/\r
+/*                                                                     */\r
+/*  FILE        :vecttbl.c                                             */\r
+/*  DATE        :Sun, Dec 27, 2009                                     */\r
+/*  DESCRIPTION :Initialize of Vector Table                            */\r
+/*  CPU TYPE    :Other                                                 */\r
+/*                                                                     */\r
+/*  This file is generated by Renesas Project Generator (Ver.4.16).    */\r
+/*                                                                     */\r
+/***********************************************************************/\r
+                  \r
+\r
+\r
+#include "vect.h"\r
+\r
+#pragma section VECTTBL\r
+\r
+void *RESET_Vectors[] = {\r
+//;<<VECTOR DATA START (POWER ON RESET)>>\r
+//;0 Power On Reset PC\r
+    (void*)    PowerON_Reset_PC,                                                                                                                \r
+//;<<VECTOR DATA END (POWER ON RESET)>>\r
+// 1 Power On Reset SP\r
+    __secend("S"),\r
+//;<<VECTOR DATA START (MANUAL RESET)>>\r
+//;2 Manual Reset PC\r
+    (void*)    Manual_Reset_PC,                                                                                                                 \r
+//;<<VECTOR DATA END (MANUAL RESET)>>\r
+// 3 Manual Reset SP\r
+    __secend("S")\r
+\r
+};\r
+#pragma section INTTBL\r
+void *INT_Vectors[] = {\r
+// 4 Illegal code\r
+    (void*) INT_Illegal_code,\r
+// xx Reserved\r
+    (void*) Dummy\r
+};\r