]> git.sur5r.net Git - freertos/commitdiff
Split out the processor dependent stuff from main.c.
authorRichardBarry <RichardBarry@1d2547de-c912-0410-9cb9-b8ca96c0e9e2>
Thu, 29 Jan 2009 15:06:24 +0000 (15:06 +0000)
committerRichardBarry <RichardBarry@1d2547de-c912-0410-9cb9-b8ca96c0e9e2>
Thu, 29 Jan 2009 15:06:24 +0000 (15:06 +0000)
git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@636 1d2547de-c912-0410-9cb9-b8ca96c0e9e2

Demo/NEC_V850ES_Fx3_IAR/LowLevelInit/LowLevelInit_Fx3.c [new file with mode: 0644]
Demo/NEC_V850ES_Fx3_IAR/LowLevelInit/LowLevelInit_Jx3.c [new file with mode: 0644]

diff --git a/Demo/NEC_V850ES_Fx3_IAR/LowLevelInit/LowLevelInit_Fx3.c b/Demo/NEC_V850ES_Fx3_IAR/LowLevelInit/LowLevelInit_Fx3.c
new file mode 100644 (file)
index 0000000..1551b02
--- /dev/null
@@ -0,0 +1,128 @@
+/*\r
+       FreeRTOS.org V5.1.1 - Copyright (C) 2003-2008 Richard Barry.\r
+\r
+       This file is part of the FreeRTOS.org distribution.\r
+\r
+       FreeRTOS.org is free software; you can redistribute it and/or modify\r
+       it under the terms of the GNU General Public License as published by\r
+       the Free Software Foundation; either version 2 of the License, or\r
+       (at your option) any later version.\r
+\r
+       FreeRTOS.org is distributed in the hope that it will be useful,\r
+       but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+       MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\r
+       GNU General Public License for more details.\r
+\r
+       You should have received a copy of the GNU General Public License\r
+       along with FreeRTOS.org; if not, write to the Free Software\r
+       Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA\r
+\r
+       A special exception to the GPL can be applied should you wish to distribute\r
+       a combined work that includes FreeRTOS.org, without being obliged to provide\r
+       the source code for any proprietary components.  See the licensing section\r
+       of http://www.FreeRTOS.org for full details of how and when the exception\r
+       can be applied.\r
+\r
+    ***************************************************************************\r
+    ***************************************************************************\r
+    *                                                                         *\r
+    * SAVE TIME AND MONEY!  We can port FreeRTOS.org to your own hardware,    *\r
+    * and even write all or part of your application on your behalf.          *\r
+    * See http://www.OpenRTOS.com for details of the services we provide to   *\r
+    * expedite your project.                                                  *\r
+    *                                                                         *\r
+    ***************************************************************************\r
+    ***************************************************************************\r
+\r
+       Please ensure to read the configuration and relevant port sections of the\r
+       online documentation.\r
+\r
+       http://www.FreeRTOS.org - Documentation, latest information, license and\r
+       contact details.\r
+\r
+       http://www.SafeRTOS.com - A version that is certified for use in safety\r
+       critical systems.\r
+\r
+       http://www.OpenRTOS.com - Commercial support, development, porting,\r
+       licensing and training services.\r
+*/\r
+\r
+#include "FreeRTOS.h"\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Called by the startup code to initialise the run time system. */\r
+unsigned portCHAR __low_level_init(void);\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+unsigned portCHAR __low_level_init(void)\r
+{\r
+unsigned portCHAR resetflag = RESF;\r
+unsigned portCHAR psval = 0;\r
+\r
+       /* Setup provided by NEC. */\r
+\r
+       /* Disable global interrupts to ensure no interrupts occur during system\r
+       setup. */\r
+       portDISABLE_INTERRUPTS();\r
+\r
+       PRCMD = 0x00;\r
+       OCDM = 0x00;\r
+       VSWC = 0x12;\r
+       VSWC = 18;\r
+\r
+       /* Set main system clock */\r
+       OSTS = 0x06;\r
+       psval = 0x80;\r
+       PRCMD = psval;\r
+       PCC = psval;\r
+       while (!OSTC)\r
+       {\r
+               ;\r
+       }\r
+\r
+       PLLS = 0x03;\r
+       PLLON = 1;\r
+       while (LOCKR)\r
+       {\r
+               ;\r
+       }\r
+\r
+       psval = 0x01;\r
+       PRCMD = psval;\r
+       MCM = psval;\r
+       SELPLL = 1;\r
+\r
+       /* Set fCPU */\r
+       psval = PCC | 0x00;\r
+       PRCMD = psval;\r
+       PCC = psval;\r
+       RCM = 0x83;\r
+\r
+       /* Set fXP1 */\r
+       SELCNT4 = 0x00;\r
+\r
+       /* Set fBRG */\r
+       PRSM0 = 0x00;\r
+\r
+       /* Stand-by setting */\r
+       psval = 0x00;\r
+       PRCMD = psval;\r
+       PSC = psval;\r
+\r
+       /* WDT2 setting */\r
+       WDTM2 = 0x1F;\r
+\r
+       /* PCL setting */\r
+       PCLM = 0x00;\r
+\r
+       /* disable dma0 - dma3 */\r
+       E00 = 0;        \r
+       E11 = 0;\r
+       E22 = 0;\r
+       E33 = 0;        \r
+\r
+       return pdTRUE;\r
+}\r
+/*-----------------------------------------------------------*/\r
diff --git a/Demo/NEC_V850ES_Fx3_IAR/LowLevelInit/LowLevelInit_Jx3.c b/Demo/NEC_V850ES_Fx3_IAR/LowLevelInit/LowLevelInit_Jx3.c
new file mode 100644 (file)
index 0000000..e5a0624
--- /dev/null
@@ -0,0 +1,99 @@
+/*\r
+       FreeRTOS.org V5.1.1 - Copyright (C) 2003-2008 Richard Barry.\r
+\r
+       This file is part of the FreeRTOS.org distribution.\r
+\r
+       FreeRTOS.org is free software; you can redistribute it and/or modify\r
+       it under the terms of the GNU General Public License as published by\r
+       the Free Software Foundation; either version 2 of the License, or\r
+       (at your option) any later version.\r
+\r
+       FreeRTOS.org is distributed in the hope that it will be useful,\r
+       but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+       MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\r
+       GNU General Public License for more details.\r
+\r
+       You should have received a copy of the GNU General Public License\r
+       along with FreeRTOS.org; if not, write to the Free Software\r
+       Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA\r
+\r
+       A special exception to the GPL can be applied should you wish to distribute\r
+       a combined work that includes FreeRTOS.org, without being obliged to provide\r
+       the source code for any proprietary components.  See the licensing section\r
+       of http://www.FreeRTOS.org for full details of how and when the exception\r
+       can be applied.\r
+\r
+    ***************************************************************************\r
+    ***************************************************************************\r
+    *                                                                         *\r
+    * SAVE TIME AND MONEY!  We can port FreeRTOS.org to your own hardware,    *\r
+    * and even write all or part of your application on your behalf.          *\r
+    * See http://www.OpenRTOS.com for details of the services we provide to   *\r
+    * expedite your project.                                                  *\r
+    *                                                                         *\r
+    ***************************************************************************\r
+    ***************************************************************************\r
+\r
+       Please ensure to read the configuration and relevant port sections of the\r
+       online documentation.\r
+\r
+       http://www.FreeRTOS.org - Documentation, latest information, license and\r
+       contact details.\r
+\r
+       http://www.SafeRTOS.com - A version that is certified for use in safety\r
+       critical systems.\r
+\r
+       http://www.OpenRTOS.com - Commercial support, development, porting,\r
+       licensing and training services.\r
+*/\r
+\r
+#include "FreeRTOS.h"\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Called by the startup code to initialise the run time system. */\r
+unsigned portCHAR __low_level_init(void);\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+unsigned portCHAR __low_level_init(void)\r
+{\r
+unsigned portCHAR resetflag = RESF;\r
+unsigned portCHAR psval = 0;\r
+unsigned portBASE_TYPE i = 0;        \r
+\r
+       /* Setup provided by NEC. */\r
+\r
+       portDISABLE_INTERRUPTS();         /* disable global interrupts */                      \r
+\r
+       PRCMD = 0x00;                     /* On-chip debug mode */\r
+       OCDM = 0x00;\r
+       VSWC = 0x00;                      /* set system wait control register */\r
+       WDTM2 = 0x00;                     /* WDT2 setting */\r
+       PLLON = 0;                        /* PLL stop mode */\r
+       psval = 0x0A | 0x00;\r
+       PRCMD = psval;                    /* set Command Register */\r
+       CKC = psval;                      /* set Clock Control Register */\r
+       PLLS = 0x03;\r
+       psval = 0x80;                     /* Set fXX and fCPU */\r
+       PRCMD = psval;\r
+       PCC = psval;\r
+       PLLON = 1;                        /* activate PLL */\r
+       for( i = 0; i <= 2000; i++ )      /* Wait for stabilisation */\r
+       {\r
+       portNOP();\r
+       }\r
+       while( LOCK )                     /* Wait for PLL frequency stabiliasation */\r
+       {\r
+       ;\r
+       }\r
+       SELPLL = 1;                       /* Set PLL mode active */\r
+       RSTOP = 0;                        /* Set fR (enable) */\r
+       BGCE0 = 0;                        /* Set fBRG(disable) */\r
+       psval = 0x00;                     /* Stand-by setting */\r
+       PRCMD = psval;                    /* set Command Register */\r
+       PSC = psval;                      /* set Power Save Control Register */\r
+\r
+       return pdTRUE;\r
+}\r
+/*-----------------------------------------------------------*/\r