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--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>\r
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+ <comment></comment>\r
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+</projectDescription>\r
--- /dev/null
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+</project>\r
--- /dev/null
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--- /dev/null
+eclipse.preferences.version=1\r
+environment/project/cdt.managedbuild.config.gnu.cygwin.exe.debug.5899473/MSYS_HOME/delimiter=;\r
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--- /dev/null
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--- /dev/null
+eclipse.preferences.version=1\r
+org.eclipse.ltk.core.refactoring.enable.project.refactoring.history=false\r
--- /dev/null
+/*\r
+ FreeRTOS V8.2.1 - Copyright (C) 2015 Real Time Engineers Ltd.\r
+ All rights reserved\r
+\r
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
+\r
+ ***************************************************************************\r
+ >>! NOTE: The modification to the GPL is included to allow you to !<<\r
+ >>! distribute a combined work that includes FreeRTOS without being !<<\r
+ >>! obliged to provide the source code for proprietary components !<<\r
+ >>! outside of the FreeRTOS kernel. !<<\r
+ ***************************************************************************\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+ FOR A PARTICULAR PURPOSE. Full license text is available on the following\r
+ link: http://www.freertos.org/a00114.html\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS provides completely free yet professionally developed, *\r
+ * robust, strictly quality controlled, supported, and cross *\r
+ * platform software that is more than just the market leader, it *\r
+ * is the industry's de facto standard. *\r
+ * *\r
+ * Help yourself get started quickly while simultaneously helping *\r
+ * to support the FreeRTOS project by purchasing a FreeRTOS *\r
+ * tutorial book, reference manual, or both: *\r
+ * http://www.FreeRTOS.org/Documentation *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading\r
+ the FAQ page "My application does not run, what could be wrong?". Have you\r
+ defined configASSERT()?\r
+\r
+ http://www.FreeRTOS.org/support - In return for receiving this top quality\r
+ embedded software for free we request you assist our global community by\r
+ participating in the support forum.\r
+\r
+ http://www.FreeRTOS.org/training - Investing in training allows your team to\r
+ be as productive as possible as early as possible. Now you can receive\r
+ FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
+ Ltd, and the world's leading authority on the world's leading RTOS.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
+\r
+ http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
+ Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
+ Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS\r
+ licenses offer ticketed support, indemnification and commercial middleware.\r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
+ mission critical applications that require provable dependability.\r
+\r
+ 1 tab == 4 spaces!\r
+*/\r
+\r
+/******************************************************************************\r
+ * NOTE 1: This project provides two demo applications. A simple blinky style\r
+ * project, and a more comprehensive test and demo application. The\r
+ * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting in main.c is used to select\r
+ * between the two. See the notes on using mainCREATE_SIMPLE_BLINKY_DEMO_ONLY\r
+ * in main.c. This file implements the simply blinky style version.\r
+ *\r
+ * NOTE 2: This file only contains the source code that is specific to the\r
+ * basic demo. Generic functions, such FreeRTOS hook functions, and functions\r
+ * required to configure the hardware are defined in main.c.\r
+ ******************************************************************************\r
+ *\r
+ * See http://www.FreeRTOS.org/RTOS_Intel_Quark_Galileo_GCC.html for usage\r
+ * instructions.\r
+ *\r
+ * main_blinky() creates one queue, and two tasks. It then starts the\r
+ * scheduler.\r
+ *\r
+ * The Queue Send Task:\r
+ * The queue send task is implemented by the prvQueueSendTask() function in\r
+ * this file. prvQueueSendTask() sits in a loop that causes it to repeatedly\r
+ * block for 200 milliseconds, before sending the value 100 to the queue that\r
+ * was created within main_blinky(). Once the value is sent, the task loops\r
+ * back around to block for another 200 milliseconds...and so on.\r
+ *\r
+ * The Queue Receive Task:\r
+ * The queue receive task is implemented by the prvQueueReceiveTask() function\r
+ * in this file. prvQueueReceiveTask() sits in a loop where it repeatedly\r
+ * blocks on attempts to read data from the queue that was created within\r
+ * main_blinky(). When data is received, the task checks the value of the\r
+ * data, and if the value equals the expected 100, outputs a message to the COM\r
+ * port. The 'block time' parameter passed to the queue receive function\r
+ * specifies that the task should be held in the Blocked state indefinitely to\r
+ * wait for data to be available on the queue. The queue receive task will only\r
+ * leave the Blocked state when the queue send task writes to the queue. As the\r
+ * queue send task writes to the queue every 200 milliseconds, the queue receive\r
+ * task leaves the Blocked state every 200 milliseconds, and therefore writes to\r
+ * the COM port every 200 milliseconds.\r
+ */\r
+\r
+/* Kernel includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "semphr.h"\r
+\r
+/* Added Galileo SERIAL support */\r
+#include "galileo_support.h"\r
+\r
+/* Priorities at which the tasks are created. */\r
+#define mainQUEUE_RECEIVE_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
+#define mainQUEUE_SEND_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 )\r
+\r
+/* The rate at which data is sent to the queue. The 200ms value is converted\r
+to ticks using the portTICK_PERIOD_MS constant. */\r
+#define mainQUEUE_SEND_FREQUENCY_MS ( pdMS_TO_TICKS( 200 ) )\r
+\r
+/* The number of items the queue can hold. This is 1 as the receive task\r
+will remove items as they are added, meaning the send task should always find\r
+the queue empty. */\r
+#define mainQUEUE_LENGTH ( 1 )\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * The tasks as described in the comments at the top of this file.\r
+ */\r
+static void prvQueueReceiveTask( void *pvParameters );\r
+static void prvQueueSendTask( void *pvParameters );\r
+\r
+/*\r
+ * Called by main() to create the simply blinky style application if\r
+ * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 1.\r
+ */\r
+void main_blinky( void );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* The queue used by both tasks. */\r
+static QueueHandle_t xQueue = NULL;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* See http://www.FreeRTOS.org/RTOS_Intel_Quark_Galileo_GCC.html for usage\r
+instructions. */\r
+void main_blinky( void )\r
+{\r
+ /* Create the queue. */\r
+ xQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( uint32_t ) );\r
+\r
+ if( xQueue != NULL )\r
+ {\r
+ /* Start the two tasks as described in the comments at the top of this\r
+ file. */\r
+ xTaskCreate( prvQueueReceiveTask, /* The function that implements the task. */\r
+ "Rx", /* The text name assigned to the task - for debug only as it is not used by the kernel. */\r
+ configMINIMAL_STACK_SIZE * 2, /* The size of the stack to allocate to the task. */\r
+ NULL, /* The parameter passed to the task - not used in this case. */\r
+ mainQUEUE_RECEIVE_TASK_PRIORITY, /* The priority assigned to the task. */\r
+ NULL ); /* The task handle is not required, so NULL is passed. */\r
+\r
+ xTaskCreate( prvQueueSendTask, "TX", configMINIMAL_STACK_SIZE * 2, NULL, mainQUEUE_SEND_TASK_PRIORITY, NULL );\r
+\r
+ /* Start the tasks and timer running. */\r
+ vTaskStartScheduler();\r
+ }\r
+\r
+ /* If all is well, the scheduler will now be running, and the following\r
+ line will never be reached. If the following line does execute, then\r
+ there was either insufficient FreeRTOS heap memory available for the idle\r
+ and/or timer tasks to be created, or vTaskStartScheduler() was called from\r
+ User mode. See the memory management section on the FreeRTOS web site for\r
+ more details on the FreeRTOS heap http://www.freertos.org/a00111.html. The\r
+ mode from which main() is called is set in the C start up code and must be\r
+ a privileged mode (not user mode). */\r
+ for( ;; );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvQueueSendTask( void *pvParameters )\r
+{\r
+TickType_t xNextWakeTime;\r
+const uint32_t ulValueToSend = 100UL;\r
+\r
+ /* Remove compiler warning about unused parameter. */\r
+ ( void ) pvParameters;\r
+\r
+ /* Initialise xNextWakeTime - this only needs to be done once. */\r
+ xNextWakeTime = xTaskGetTickCount();\r
+\r
+ for( ;; )\r
+ {\r
+ /* Place this task in the blocked state until it is time to run again. */\r
+ vTaskDelayUntil( &xNextWakeTime, mainQUEUE_SEND_FREQUENCY_MS );\r
+\r
+ /* Send to the queue - causing the queue receive task to unblock and\r
+ write to the COM port. 0 is used as the block time so the sending\r
+ operation will not block - it shouldn't need to block as the queue\r
+ should always be empty at this point in the code. */\r
+ xQueueSend( xQueue, &ulValueToSend, 0U );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvQueueReceiveTask( void *pvParameters )\r
+{\r
+uint32_t ulReceivedValue, ulLEDStatus;\r
+const uint32_t ulExpectedValue = 100UL;\r
+\r
+ /* Remove compiler warning about unused parameter. */\r
+ ( void ) pvParameters;\r
+\r
+ /* Initial cursor position to skip a line) */\r
+ g_printf_rcc( 5, 2, DEFAULT_SCREEN_COLOR, "LED on the Galileo board should be blinking." );\r
+\r
+ for( ;; )\r
+ {\r
+ /* Wait until something arrives in the queue - this task will block\r
+ indefinitely provided INCLUDE_vTaskSuspend is set to 1 in\r
+ FreeRTOSConfig.h. */\r
+ xQueueReceive( xQueue, &ulReceivedValue, portMAX_DELAY );\r
+\r
+ /* To get here something must have been received from the queue, but\r
+ is it the expected value? If it is, write a message to the COMP\r
+ port. */\r
+ if( ulReceivedValue == ulExpectedValue )\r
+ {\r
+ /* Toggle the LED, and also print the LED toggle state to the\r
+ UART. */\r
+ ulLEDStatus = ulBlinkLED();\r
+\r
+ /* Print the LED status */\r
+ g_printf_rcc( 6, 2, DEFAULT_SCREEN_COLOR, "LED State = %d\r\n", ( int ) ulLEDStatus );\r
+ ulReceivedValue = 0U;\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V8.2.1 - Copyright (C) 2015 Real Time Engineers Ltd.\r
+ All rights reserved\r
+\r
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
+\r
+ ***************************************************************************\r
+ >>! NOTE: The modification to the GPL is included to allow you to !<<\r
+ >>! distribute a combined work that includes FreeRTOS without being !<<\r
+ >>! obliged to provide the source code for proprietary components !<<\r
+ >>! outside of the FreeRTOS kernel. !<<\r
+ ***************************************************************************\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+ FOR A PARTICULAR PURPOSE. Full license text is available on the following\r
+ link: http://www.freertos.org/a00114.html\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS provides completely free yet professionally developed, *\r
+ * robust, strictly quality controlled, supported, and cross *\r
+ * platform software that is more than just the market leader, it *\r
+ * is the industry's de facto standard. *\r
+ * *\r
+ * Help yourself get started quickly while simultaneously helping *\r
+ * to support the FreeRTOS project by purchasing a FreeRTOS *\r
+ * tutorial book, reference manual, or both: *\r
+ * http://www.FreeRTOS.org/Documentation *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading\r
+ the FAQ page "My application does not run, what could be wrong?". Have you\r
+ defined configASSERT()?\r
+\r
+ http://www.FreeRTOS.org/support - In return for receiving this top quality\r
+ embedded software for free we request you assist our global community by\r
+ participating in the support forum.\r
+\r
+ http://www.FreeRTOS.org/training - Investing in training allows your team to\r
+ be as productive as possible as early as possible. Now you can receive\r
+ FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
+ Ltd, and the world's leading authority on the world's leading RTOS.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
+\r
+ http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
+ Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
+ Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS\r
+ licenses offer ticketed support, indemnification and commercial middleware.\r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
+ mission critical applications that require provable dependability.\r
+\r
+ 1 tab == 4 spaces!\r
+*/\r
+\r
+#ifndef FREERTOS_CONFIG_H\r
+#define FREERTOS_CONFIG_H\r
+\r
+/*-----------------------------------------------------------\r
+ * Application specific definitions.\r
+ *\r
+ * These definitions should be adjusted for your particular hardware and\r
+ * application requirements.\r
+ *\r
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE\r
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.\r
+ *\r
+ * See http://www.freertos.org/a00110.html.\r
+ *----------------------------------------------------------*/\r
+\r
+/*\r
+ * The FreeRTOS Quark port implements a full interrupt nesting model.\r
+ *\r
+ * Interrupts that are assigned a priority at or below\r
+ * configMAX_API_CALL_INTERRUPT_PRIORITY can call interrupt safe API functions\r
+ * and will nest.\r
+ *\r
+ * Interrupts that are assigned a priority above\r
+ * configMAX_API_CALL_INTERRUPT_PRIORITY cannot call any FreeRTOS API functions,\r
+ * will nest, and will not be masked by FreeRTOS critical sections (although all\r
+ * interrupts are briefly masked by the hardware itself on interrupt entry).\r
+ *\r
+ * FreeRTOS functions that can be called from an interrupt are those that end in\r
+ * "FromISR". FreeRTOS maintains a separate interrupt safe API to enable\r
+ * interrupt entry to be shorter, faster, simpler and smaller.\r
+ *\r
+ * User definable interrupt priorities range from 2 (the lowest) to 15 (the\r
+ * highest).\r
+ */\r
+#define configMAX_API_CALL_INTERRUPT_PRIORITY 10\r
+\r
+/*\r
+ * Interrupt entry code will switch the stack in use to a dedicated system \r
+ * stack.\r
+ *\r
+ * configISR_STACK_SIZE defines the number of 32-bit values that can be stored\r
+ * on the system stack, and must be large enough to hold a potentially nested\r
+ * interrupt stack frame.\r
+ *\r
+ * Changing this parameter necessitates a complete rebuild so the assembly files\r
+ * also get rebuilt.\r
+ */\r
+#define configISR_STACK_SIZE 350\r
+\r
+/*\r
+ * If configSUPPORT_FPU is set to 1 then tasks can optionally have a floating\r
+ * point context (the floating point registers will be saved as part of the task\r
+ * context). If configSUPPORT_FPU is set to 1 then a task must *not* use any\r
+ * floating point instructions until after it has called vPortTaskUsesFPU().\r
+ *\r
+ * If configSUPPORT_FPU is set to 0 then floating point instructions must never\r
+ * be used.\r
+ */\r
+#define configSUPPORT_FPU 1\r
+\r
+/* There are two ways of implementing interrupt handlers:\r
+ *\r
+ * 1) As standard C functions -\r
+ *\r
+ * This method can only be used if configUSE_COMMON_INTERRUPT_ENTRY_POINT\r
+ * is set to 1. The C function is installed using\r
+ * xPortRegisterCInterruptHandler().\r
+ *\r
+ * This is the simplest of the two methods but incurs a slightly longer\r
+ * interrupt entry time.\r
+ *\r
+ * 2) By using an assembly stub that wraps the handler in the FreeRTOS\r
+ * portFREERTOS_INTERRUPT_ENTRY and portFREERTOS_INTERRUPT_EXIT macros. The handler is installed\r
+ * using xPortInstallInterruptHandler().\r
+ *\r
+ * This method can always be used. It is slightly more complex than\r
+ * method 1 but benefits from a faster interrupt entry time.\r
+ *\r
+ * Changing this parameter necessitates a complete clean build.\r
+ */\r
+#define configUSE_COMMON_INTERRUPT_ENTRY_POINT 1\r
+\r
+#define configCPU_CLOCK_HZ ( 400000000UL )\r
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1\r
+#define configMINIMAL_STACK_SIZE ( 125 )\r
+#define configUSE_TICKLESS_IDLE 0\r
+#define configTICK_RATE_HZ ( ( TickType_t ) 1000 )\r
+#define configUSE_PREEMPTION 1\r
+#define configUSE_IDLE_HOOK 1\r
+#define configUSE_TICK_HOOK 1\r
+#define configMAX_PRIORITIES ( 7 )\r
+#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 55 * 1024 ) )\r
+#define configMAX_TASK_NAME_LEN ( 10 )\r
+#define configUSE_TRACE_FACILITY 0\r
+#define configUSE_16_BIT_TICKS 0\r
+#define configIDLE_SHOULD_YIELD 1\r
+#define configUSE_MUTEXES 1\r
+#define configQUEUE_REGISTRY_SIZE 8\r
+#define configCHECK_FOR_STACK_OVERFLOW 2\r
+#define configUSE_RECURSIVE_MUTEXES 1\r
+#define configUSE_MALLOC_FAILED_HOOK 1\r
+#define configUSE_APPLICATION_TASK_TAG 0\r
+#define configUSE_COUNTING_SEMAPHORES 1\r
+#define configUSE_QUEUE_SETS 1\r
+#define configUSE_TASK_NOTIFICATIONS 1\r
+\r
+/* Co-routine definitions. */\r
+#define configUSE_CO_ROUTINES 0\r
+#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )\r
+\r
+/* Software timer definitions. */\r
+#define configUSE_TIMERS 1\r
+#define configTIMER_TASK_PRIORITY ( configMAX_PRIORITIES - 1 )\r
+#define configTIMER_QUEUE_LENGTH 8\r
+#define configTIMER_TASK_STACK_DEPTH ( configMINIMAL_STACK_SIZE * 2 )\r
+\r
+/* Set the following definitions to 1 to include the API function, or zero\r
+to exclude the API function. */\r
+#define INCLUDE_vTaskPrioritySet 1\r
+#define INCLUDE_uxTaskPriorityGet 1\r
+#define INCLUDE_vTaskDelete 1\r
+#define INCLUDE_vTaskCleanUpResources 1\r
+#define INCLUDE_vTaskSuspend 1\r
+#define INCLUDE_vTaskDelayUntil 1\r
+#define INCLUDE_vTaskDelay 1\r
+#define INCLUDE_xTimerPendFunctionCall 1\r
+#define INCLUDE_eTaskGetState 1\r
+\r
+/* This demo makes use of one or more example stats formatting functions. These\r
+format the raw data provided by the uxTaskGetSystemState() function in to human\r
+readable ASCII form. See the notes in the implementation of vTaskList() within\r
+FreeRTOS/Source/tasks.c for limitations. */\r
+#define configUSE_STATS_FORMATTING_FUNCTIONS 1\r
+\r
+/* portCONFIGURE_TIMER_FOR_RUN_TIME_STATS is not required because the time base\r
+comes from the ulHighFrequencyTimerCounts variable which is incremented in a\r
+high frequency timer that is already being started as part of the interrupt\r
+nesting test. */\r
+#define configGENERATE_RUN_TIME_STATS 0\r
+\r
+/* The size of the global output buffer that is available for use when there\r
+are multiple command interpreters running at once (for example, one on a UART\r
+and one on TCP/IP). This is done to prevent an output buffer being defined by\r
+each implementation - which would waste RAM. In this case, there is only one\r
+command interpreter running. */\r
+#define configCOMMAND_INT_MAX_OUTPUT_SIZE 2096\r
+\r
+/* This file is included from assembler files - make sure C code is not included\r
+in assembler files. */\r
+#ifndef __ASSEMBLER__\r
+ void vAssertCalled( const char * pcFile, unsigned long ulLine );\r
+ void vConfigureTickInterrupt( void );\r
+ void vClearTickInterrupt( void );\r
+#endif /* __ASSEMBLER__ */\r
+\r
+\r
+\r
+/* Normal assert() semantics without relying on the provision of an assert.h\r
+header file. */\r
+#define configASSERT( x ) if( ( x ) == 0 ) vAssertCalled( __FILE__, __LINE__ );\r
+\r
+\r
+\r
+/****** Hardware/compiler specific settings. *******************************************/\r
+\r
+/*\r
+ * The application must provide a function that configures a peripheral to\r
+ * create the FreeRTOS tick interrupt, then define configSETUP_TICK_INTERRUPT()\r
+ * in FreeRTOSConfig.h to call the function. This file contains a function\r
+ * that is suitable for use on the Zynq MPU. FreeRTOS_Tick_Handler() must\r
+ * be installed as the peripheral's interrupt handler.\r
+ */\r
+#define configSETUP_TICK_INTERRUPT() vConfigureTickInterrupt()\r
+#define configCLEAR_TICK_INTERRUPT() vClearTickInterrupt()\r
+\r
+\r
+/* Compiler specifics. */\r
+#define fabs( x ) __builtin_fabs( ( x ) )\r
+\r
+#endif /* FREERTOS_CONFIG_H */\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V8.2.1 - Copyright (C) 2015 Real Time Engineers Ltd.\r
+ All rights reserved\r
+\r
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
+\r
+ ***************************************************************************\r
+ >>! NOTE: The modification to the GPL is included to allow you to !<<\r
+ >>! distribute a combined work that includes FreeRTOS without being !<<\r
+ >>! obliged to provide the source code for proprietary components !<<\r
+ >>! outside of the FreeRTOS kernel. !<<\r
+ ***************************************************************************\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+ FOR A PARTICULAR PURPOSE. Full license text is available on the following\r
+ link: http://www.freertos.org/a00114.html\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS provides completely free yet professionally developed, *\r
+ * robust, strictly quality controlled, supported, and cross *\r
+ * platform software that is more than just the market leader, it *\r
+ * is the industry's de facto standard. *\r
+ * *\r
+ * Help yourself get started quickly while simultaneously helping *\r
+ * to support the FreeRTOS project by purchasing a FreeRTOS *\r
+ * tutorial book, reference manual, or both: *\r
+ * http://www.FreeRTOS.org/Documentation *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading\r
+ the FAQ page "My application does not run, what could be wrong?". Have you\r
+ defined configASSERT()?\r
+\r
+ http://www.FreeRTOS.org/support - In return for receiving this top quality\r
+ embedded software for free we request you assist our global community by\r
+ participating in the support forum.\r
+\r
+ http://www.FreeRTOS.org/training - Investing in training allows your team to\r
+ be as productive as possible as early as possible. Now you can receive\r
+ FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
+ Ltd, and the world's leading authority on the world's leading RTOS.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
+\r
+ http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
+ Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
+ Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS\r
+ licenses offer ticketed support, indemnification and commercial middleware.\r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
+ mission critical applications that require provable dependability.\r
+\r
+ 1 tab == 4 spaces!\r
+*/\r
+\r
+/*\r
+ * Provides the port specific part of the standard IntQ test, which is\r
+ * implemented in FreeRTOS/Demo/Common/Minimal/IntQueue.c. Three HPET timers\r
+ * are used to generate the interrupts. The timers are configured in\r
+ * prvSetupHardware(), in main.c.\r
+ */\r
+\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+\r
+/* Demo includes. */\r
+#include "IntQueueTimer.h"\r
+#include "IntQueue.h"\r
+\r
+/*\r
+ * Prototypes of the callback functions which are called from the HPET timer\r
+ * support file. For demonstration purposes, timer 0 and timer 1 are standard\r
+ * C functions that use the central interrupt handler, and are installed using\r
+ * xPortRegisterCInterruptHandler() - and timer 2 uses its own interrupt entry\r
+ * asm wrapper code and is installed using xPortInstallInterruptHandler(). For\r
+ * convenience the asm wrapper which calls vApplicationHPETTimer1Handler(), is\r
+ * implemented in RegTest.S. See\r
+ * http://www.freertos.org/RTOS_Intel_Quark_Galileo_GCC.html#interrupts for more\r
+ * details.\r
+ */\r
+void vApplicationHPETTimer0Handler( void );\r
+void vApplicationHPETTimer1Handler( void );\r
+void vApplicationHPETTimer2Handler( void );\r
+\r
+/*\r
+ * Set to pdTRUE when vInitialiseTimerForIntQueueTest() is called so the timer\r
+ * callback functions know the scheduler is running and the tests can run.\r
+ */\r
+static volatile BaseType_t xSchedulerRunning = pdFALSE;\r
+\r
+/* Used to count the nesting depth to ensure the test is testing what it is\r
+intended to test. */\r
+static volatile uint32_t ulMaxInterruptNesting = 0;\r
+extern volatile uint32_t ulInterruptNesting;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void vInitialiseTimerForIntQueueTest( void )\r
+{\r
+ /* The HPET timers are set up in main(), before the scheduler is started,\r
+ so there is nothing to do here other than note the scheduler is now running.\r
+ This could be done by calling a FreeRTOS API function, but its convenient\r
+ and efficient just to store the fact in a file scope variable. */\r
+ xSchedulerRunning = pdTRUE;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationHPETTimer0Handler( void )\r
+{\r
+BaseType_t xHigherPriorityTaskWoken;\r
+\r
+ if( xSchedulerRunning != pdFALSE )\r
+ {\r
+ if( ulInterruptNesting > ulMaxInterruptNesting )\r
+ {\r
+ ulMaxInterruptNesting = ulInterruptNesting;\r
+ }\r
+\r
+ xHigherPriorityTaskWoken = xFirstTimerHandler();\r
+ portYIELD_FROM_ISR( xHigherPriorityTaskWoken );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationHPETTimer1Handler( void )\r
+{\r
+BaseType_t xHigherPriorityTaskWoken;\r
+\r
+ if( xSchedulerRunning != pdFALSE )\r
+ {\r
+ if( ulInterruptNesting > ulMaxInterruptNesting )\r
+ {\r
+ ulMaxInterruptNesting = ulInterruptNesting;\r
+ }\r
+\r
+ xHigherPriorityTaskWoken = xSecondTimerHandler();\r
+ portYIELD_FROM_ISR( xHigherPriorityTaskWoken );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationHPETTimer2Handler( void )\r
+{\r
+ if( ulInterruptNesting > ulMaxInterruptNesting )\r
+ {\r
+ ulMaxInterruptNesting = ulInterruptNesting;\r
+ }\r
+}\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V8.2.1 - Copyright (C) 2015 Real Time Engineers Ltd.\r
+ All rights reserved\r
+\r
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
+\r
+ ***************************************************************************\r
+ >>! NOTE: The modification to the GPL is included to allow you to !<<\r
+ >>! distribute a combined work that includes FreeRTOS without being !<<\r
+ >>! obliged to provide the source code for proprietary components !<<\r
+ >>! outside of the FreeRTOS kernel. !<<\r
+ ***************************************************************************\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+ FOR A PARTICULAR PURPOSE. Full license text is available on the following\r
+ link: http://www.freertos.org/a00114.html\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS provides completely free yet professionally developed, *\r
+ * robust, strictly quality controlled, supported, and cross *\r
+ * platform software that is more than just the market leader, it *\r
+ * is the industry's de facto standard. *\r
+ * *\r
+ * Help yourself get started quickly while simultaneously helping *\r
+ * to support the FreeRTOS project by purchasing a FreeRTOS *\r
+ * tutorial book, reference manual, or both: *\r
+ * http://www.FreeRTOS.org/Documentation *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading\r
+ the FAQ page "My application does not run, what could be wrong?". Have you\r
+ defined configASSERT()?\r
+\r
+ http://www.FreeRTOS.org/support - In return for receiving this top quality\r
+ embedded software for free we request you assist our global community by\r
+ participating in the support forum.\r
+\r
+ http://www.FreeRTOS.org/training - Investing in training allows your team to\r
+ be as productive as possible as early as possible. Now you can receive\r
+ FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
+ Ltd, and the world's leading authority on the world's leading RTOS.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
+\r
+ http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
+ Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
+ Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS\r
+ licenses offer ticketed support, indemnification and commercial middleware.\r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
+ mission critical applications that require provable dependability.\r
+\r
+ 1 tab == 4 spaces!\r
+*/\r
+\r
+#ifndef INT_QUEUE_TIMER_H\r
+#define INT_QUEUE_TIMER_H\r
+\r
+void vInitialiseTimerForIntQueueTest( void );\r
+portBASE_TYPE xTimer0Handler( void );\r
+portBASE_TYPE xTimer1Handler( void );\r
+\r
+#endif\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V8.2.1 - Copyright (C) 2015 Real Time Engineers Ltd.\r
+ All rights reserved\r
+\r
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
+\r
+ ***************************************************************************\r
+ >>! NOTE: The modification to the GPL is included to allow you to !<<\r
+ >>! distribute a combined work that includes FreeRTOS without being !<<\r
+ >>! obliged to provide the source code for proprietary components !<<\r
+ >>! outside of the FreeRTOS kernel. !<<\r
+ ***************************************************************************\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+ FOR A PARTICULAR PURPOSE. Full license text is available on the following\r
+ link: http://www.freertos.org/a00114.html\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS provides completely free yet professionally developed, *\r
+ * robust, strictly quality controlled, supported, and cross *\r
+ * platform software that is more than just the market leader, it *\r
+ * is the industry's de facto standard. *\r
+ * *\r
+ * Help yourself get started quickly while simultaneously helping *\r
+ * to support the FreeRTOS project by purchasing a FreeRTOS *\r
+ * tutorial book, reference manual, or both: *\r
+ * http://www.FreeRTOS.org/Documentation *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading\r
+ the FAQ page "My application does not run, what could be wrong?". Have you\r
+ defined configASSERT()?\r
+\r
+ http://www.FreeRTOS.org/support - In return for receiving this top quality\r
+ embedded software for free we request you assist our global community by\r
+ participating in the support forum.\r
+\r
+ http://www.FreeRTOS.org/training - Investing in training allows your team to\r
+ be as productive as possible as early as possible. Now you can receive\r
+ FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
+ Ltd, and the world's leading authority on the world's leading RTOS.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
+\r
+ http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
+ Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
+ Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS\r
+ licenses offer ticketed support, indemnification and commercial middleware.\r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
+ mission critical applications that require provable dependability.\r
+\r
+ 1 tab == 4 spaces!\r
+*/\r
+\r
+.file "RegTest.S"\r
+#include "FreeRTOSConfig.h"\r
+#include "ISR_Support.h"\r
+\r
+ .extern ulRegTest1Counter\r
+ .extern ulRegTest2Counter\r
+ .extern dRegTest1_st7\r
+ .extern dRegTest1_st6\r
+ .extern dRegTest1_st5\r
+ .extern dRegTest1_st4\r
+ .extern dRegTest1_st3\r
+ .extern dRegTest1_st2\r
+ .extern dRegTest1_st1\r
+ .extern dRegTest2_st7\r
+ .extern dRegTest2_st6\r
+ .extern dRegTest2_st5\r
+ .extern dRegTest2_st4\r
+ .extern dRegTest2_st3\r
+ .extern dRegTest2_st2\r
+ .extern dRegTest2_st1\r
+ .extern vGenerateYieldInterrupt\r
+ .extern vHPETIRQHandler1\r
+ \r
+ .global vRegTest1\r
+ .global vRegTest2\r
+ .global vApplicationHPETTimer1Wrapper\r
+\r
+ .section .text.last /* Push up the memory to check executing from higher memory addresses. */\r
+ .align 4\r
+\r
+.func vRegTest1\r
+vRegTest1:\r
+\r
+ /* Set initial values into the general purpose registers. */\r
+ movl $0x11111111, %eax\r
+ movl $0x22222222, %ebx\r
+ movl $0x33333333, %ecx\r
+ movl $0x44444444, %edx\r
+ movl $0x55555555, %esi\r
+ movl $0x66666666, %edi\r
+\r
+ /* Set initial values into the floating point registers. */\r
+ .if configSUPPORT_FPU == 1\r
+ fldl dRegTest1_st7\r
+ fldl dRegTest1_st6\r
+ fldl dRegTest1_st5\r
+ fldl dRegTest1_st4\r
+ fldl dRegTest1_st3\r
+ fldl dRegTest1_st2\r
+ fldl dRegTest1_st1\r
+ .endif /* configSUPPORT_FPU */\r
+\r
+_RegTest1Loop:\r
+\r
+ /* Loop checking the values originally loaded into the general purpose\r
+ registers remain through the life of the task. */\r
+ cmp $0x11111111, %eax\r
+ jne _RegTest1Error\r
+ cmp $0x22222222, %ebx\r
+ jne _RegTest1Error\r
+ cmp $0x33333333, %ecx\r
+ jne _RegTest1Error\r
+ cmp $0x44444444, %edx\r
+ jne _RegTest1Error\r
+ cmp $0x55555555, %esi\r
+ jne _RegTest1Error\r
+ cmp $0x66666666, %edi\r
+ jne _RegTest1Error\r
+\r
+\r
+ .if configSUPPORT_FPU == 1\r
+ /* Loop checking the values originally loaded into the floating point\r
+ registers remain through the life of the task. */\r
+ push %eax /* push clobbered register. */\r
+ fldl dRegTest1_st7 /* st( 0 ) set to st( 7 ) value. */\r
+ fucomp %st( 7 ) /* Compare st( 0 ) with st( 7 ) and pop. */\r
+ fnstsw %ax /* Copy status word to ax. */\r
+ and $0x45, %ah /* Mask bits. */\r
+ xor $0x40, %ah /* test bits. */\r
+ jne _RegTest1Error\r
+ fldl dRegTest1_st6\r
+ fucomp %st( 6 )\r
+ fnstsw %ax\r
+ and $0x45, %ah\r
+ xor $0x40, %ah\r
+ jne _RegTest1Error\r
+ fldl dRegTest1_st5\r
+ fucomp %st( 5 )\r
+ fnstsw %ax\r
+ and $0x45, %ah\r
+ xor $0x40, %ah\r
+ jne _RegTest1Error\r
+ fldl dRegTest1_st4\r
+ fucomp %st( 4 )\r
+ fnstsw %ax\r
+ and $0x45, %ah\r
+ xor $0x40, %ah\r
+ jne _RegTest1Error\r
+ fldl dRegTest1_st3\r
+ fucomp %st( 3 )\r
+ fnstsw %ax\r
+ and $0x45, %ah\r
+ xor $0x40, %ah\r
+ jne _RegTest1Error\r
+ fldl dRegTest1_st2\r
+ fucomp %st( 2 )\r
+ fnstsw %ax\r
+ and $0x45, %ah\r
+ xor $0x40, %ah\r
+ jne _RegTest1Error\r
+ fldl dRegTest1_st1\r
+ fucomp %st( 1 )\r
+ fnstsw %ax\r
+ and $0x45, %ah\r
+ xor $0x40, %ah\r
+ jne _RegTest1Error\r
+\r
+ /* Restore clobbered register. */\r
+ pop %eax\r
+ .endif /* configSUPPORT_FPU */\r
+\r
+ /* Incrememnt the loop counter to prove this task has not gone into the\r
+ error null loop. */\r
+ add $1, ulRegTest1Counter\r
+\r
+ /* Loop again. */\r
+ jmp _RegTest1Loop\r
+\r
+_RegTest1Error:\r
+ jmp .\r
+.endfunc\r
+/*-----------------------------------------------------------*/\r
+\r
+.func vRegTest2\r
+vRegTest2:\r
+\r
+ /* Set initial values into the general purpose registers. */\r
+ movl $0x10101010, %eax\r
+ movl $0x20202020, %ebx\r
+ movl $0x30303030, %ecx\r
+ movl $0x40404040, %edx\r
+ movl $0x50505050, %esi\r
+ movl $0x60606060, %edi\r
+\r
+ /* Set initial values into the floating point registers. */\r
+ .if configSUPPORT_FPU == 1\r
+ fldl dRegTest2_st7\r
+ fldl dRegTest2_st6\r
+ fldl dRegTest2_st5\r
+ fldl dRegTest2_st4\r
+ fldl dRegTest2_st3\r
+ fldl dRegTest2_st2\r
+ fldl dRegTest2_st1\r
+ .endif\r
+\r
+_RegTest2Loop:\r
+\r
+ /* Loop checking the values originally loaded into the general purpose\r
+ registers remain through the life of the task. */\r
+ cmp $0x10101010, %eax\r
+ jne _RegTest2Error\r
+ cmp $0x20202020, %ebx\r
+ jne _RegTest2Error\r
+ cmp $0x30303030, %ecx\r
+ jne _RegTest2Error\r
+ cmp $0x40404040, %edx\r
+ jne _RegTest2Error\r
+ cmp $0x50505050, %esi\r
+ jne _RegTest2Error\r
+ cmp $0x60606060, %edi\r
+ jne _RegTest1Error\r
+\r
+ .if configSUPPORT_FPU == 1\r
+ /* Loop checking the values originally loaded into the floating point\r
+ registers remain through the life of the task. */\r
+ /* Loop checking the values originally loaded into the floating point\r
+ registers remain through the life of the task. */\r
+ push %eax /* push clobbered register. */\r
+ fldl dRegTest2_st7 /* st( 0 ) set to st( 7 ) value. */\r
+ fucomp %st( 7 ) /* Compare st( 0 ) with st( 7 ) and pop. */\r
+ fnstsw %ax /* Copy status word to ax. */\r
+ and $0x45, %ah /* Mask bits. */\r
+ xor $0x40, %ah /* test bits. */\r
+ jne _RegTest1Error\r
+ fldl dRegTest2_st6\r
+ fucomp %st( 6 )\r
+ fnstsw %ax\r
+ and $0x45, %ah\r
+ xor $0x40, %ah\r
+ jne _RegTest1Error\r
+ fldl dRegTest2_st5\r
+ fucomp %st( 5 )\r
+ fnstsw %ax\r
+ and $0x45, %ah\r
+ xor $0x40, %ah\r
+ jne _RegTest1Error\r
+ fldl dRegTest2_st4\r
+ fucomp %st( 4 )\r
+ fnstsw %ax\r
+ and $0x45, %ah\r
+ xor $0x40, %ah\r
+ jne _RegTest1Error\r
+ fldl dRegTest2_st3\r
+ fucomp %st( 3 )\r
+ fnstsw %ax\r
+ and $0x45, %ah\r
+ xor $0x40, %ah\r
+ jne _RegTest1Error\r
+ fldl dRegTest2_st2\r
+ fucomp %st( 2 )\r
+ fnstsw %ax\r
+ and $0x45, %ah\r
+ xor $0x40, %ah\r
+ jne _RegTest1Error\r
+ fldl dRegTest2_st1\r
+ fucomp %st( 1 )\r
+ fnstsw %ax\r
+ and $0x45, %ah\r
+ xor $0x40, %ah\r
+ jne _RegTest1Error\r
+\r
+ /* Restore clobbered register. */\r
+ pop %eax\r
+\r
+ .endif /* configSUPPORT_FPU */\r
+\r
+ /* Force a yield from one of the reg test tasks to increase coverage. */\r
+ call vGenerateYieldInterrupt\r
+\r
+ /* Increment the loop counter to prove this task has not entered the error\r
+ null loop. */\r
+ add $1, ulRegTest2Counter\r
+ jmp _RegTest2Loop\r
+\r
+_RegTest2Error:\r
+ jmp .\r
+\r
+.endfunc\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Purely for demonstration purposes, two of the HPET timers used by the\r
+IntQueue test use the central interrupt handler, and timer 1 uses its own\r
+assembly wrapper - which is defined below. See\r
+http://www.freertos.org/RTOS_Intel_Quark_Galileo_GCC.html#interrupts for more\r
+information. */\r
+.func vApplicationHPETTimer1Wrapper\r
+vApplicationHPETTimer1Wrapper:\r
+\r
+ portFREERTOS_INTERRUPT_ENTRY\r
+ call vHPETIRQHandler1\r
+ portFREERTOS_INTERRUPT_EXIT\r
+\r
+.endfunc\r
+\r
+.end\r
--- /dev/null
+/*\r
+ FreeRTOS V8.2.1 - Copyright (C) 2015 Real Time Engineers Ltd.\r
+ All rights reserved\r
+\r
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
+\r
+ ***************************************************************************\r
+ >>! NOTE: The modification to the GPL is included to allow you to !<<\r
+ >>! distribute a combined work that includes FreeRTOS without being !<<\r
+ >>! obliged to provide the source code for proprietary components !<<\r
+ >>! outside of the FreeRTOS kernel. !<<\r
+ ***************************************************************************\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+ FOR A PARTICULAR PURPOSE. Full license text is available on the following\r
+ link: http://www.freertos.org/a00114.html\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS provides completely free yet professionally developed, *\r
+ * robust, strictly quality controlled, supported, and cross *\r
+ * platform software that is more than just the market leader, it *\r
+ * is the industry's de facto standard. *\r
+ * *\r
+ * Help yourself get started quickly while simultaneously helping *\r
+ * to support the FreeRTOS project by purchasing a FreeRTOS *\r
+ * tutorial book, reference manual, or both: *\r
+ * http://www.FreeRTOS.org/Documentation *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading\r
+ the FAQ page "My application does not run, what could be wrong?". Have you\r
+ defined configASSERT()?\r
+\r
+ http://www.FreeRTOS.org/support - In return for receiving this top quality\r
+ embedded software for free we request you assist our global community by\r
+ participating in the support forum.\r
+\r
+ http://www.FreeRTOS.org/training - Investing in training allows your team to\r
+ be as productive as possible as early as possible. Now you can receive\r
+ FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
+ Ltd, and the world's leading authority on the world's leading RTOS.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
+\r
+ http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
+ Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
+ Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS\r
+ licenses offer ticketed support, indemnification and commercial middleware.\r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
+ mission critical applications that require provable dependability.\r
+\r
+ 1 tab == 4 spaces!\r
+*/\r
+\r
+/******************************************************************************\r
+ * NOTE 1: This project provides two demo applications. A simple blinky style\r
+ * project, and a more comprehensive test and demo application. The\r
+ * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting in main.c is used to select\r
+ * between the two. See the notes on using mainCREATE_SIMPLE_BLINKY_DEMO_ONLY\r
+ * in main.c. This file implements the comprehensive test and demo version.\r
+ *\r
+ * NOTE 2: This file only contains the source code that is specific to the\r
+ * full demo. Generic functions, such FreeRTOS hook functions, and functions\r
+ * required to configure the hardware, are defined in main.c.\r
+ *\r
+ ******************************************************************************\r
+ *\r
+ * See http://www.FreeRTOS.org/RTOS_Intel_Quark_Galileo_GCC.html for usage\r
+ * instructions.\r
+ *\r
+ * main_full() creates all the demo application tasks and software timers, then\r
+ * starts the scheduler. The web documentation provides more details of the\r
+ * standard demo application tasks, which provide no particular functionality,\r
+ * but do provide a good example of how to use the FreeRTOS API.\r
+ *\r
+ * In addition to the standard demo tasks, the following tasks and tests are\r
+ * defined and/or created within this file:\r
+ *\r
+ * "Reg test" tasks - These fill both the core and floating point registers with\r
+ * known values, then check that each register maintains its expected value for\r
+ * the lifetime of the task. Each task uses a different set of values. The reg\r
+ * test tasks execute with a very low priority, so get preempted very\r
+ * frequently. A register containing an unexpected value is indicative of an\r
+ * error in the context switching mechanism.\r
+ *\r
+ * "Check" task - The check task period is set to five seconds. The task checks\r
+ * that all the standard demo tasks, and the register check tasks, are not only\r
+ * still executing, but are executing without reporting any errors. The check\r
+ * task toggles an LED on each iteration. If the LED toggles every 5 seconds\r
+ * then no errors have been found. If the LED toggles every 1 second then a\r
+ * potential error has been detected.\r
+ */\r
+\r
+/* Standard includes. */\r
+#include <stdio.h>\r
+#include <stdlib.h>\r
+#include <string.h>\r
+#include <stdint.h>\r
+\r
+/* FreeRTOS includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "timers.h"\r
+\r
+/* Standard demo includes. */\r
+#include "blocktim.h"\r
+#include "flash_timer.h"\r
+#include "semtest.h"\r
+#include "GenQTest.h"\r
+#include "QPeek.h"\r
+#include "countsem.h"\r
+#include "dynamic.h"\r
+#include "QueueOverwrite.h"\r
+#include "QueueSet.h"\r
+#include "recmutex.h"\r
+#include "EventGroupsDemo.h"\r
+#include "death.h"\r
+#include "TimerDemo.h"\r
+#include "BlockQ.h"\r
+#include "flop.h"\r
+#include "TaskNotify.h"\r
+#include "IntQueue.h"\r
+\r
+/* Galileo includes. */\r
+#include "galileo_support.h"\r
+\r
+/* The rate at which the check task cycles if no errors have been detected, and\r
+if a [potential] error has been detected. Increasing the toggle rate in the\r
+presense of an error gives visual feedback of the system status. */\r
+#define mainNO_ERROR_CHECK_TASK_PERIOD pdMS_TO_TICKS( 5000UL )\r
+#define mainERROR_CHECK_TASK_PERIOD pdMS_TO_TICKS( 1000UL )\r
+\r
+/* The priorities of the various demo application tasks. */\r
+#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 )\r
+#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 1 )\r
+#define mainGEN_QUEUE_TASK_PRIORITY ( tskIDLE_PRIORITY )\r
+#define mainQUEUE_OVERWRITE_TASK_PRIORITY ( tskIDLE_PRIORITY )\r
+#define mainMATHS_TASK_PRIORITY ( tskIDLE_PRIORITY )\r
+\r
+/* The base period used by the timer test tasks. */\r
+#define mainTIMER_TEST_PERIOD ( 50 )\r
+\r
+/* Parameters that are passed into the check tasks for no other purpose other\r
+than to check the port does this correctly. */\r
+#define mainREG_TEST_1_PARAMETER ( 0x12345678UL )\r
+#define mainREG_TEST_2_PARAMETER ( 0x87654321UL )\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * The function that implements the check task, as described at the top of this\r
+ * file.\r
+ */\r
+static void prvCheckTask( void *pvParameters );\r
+\r
+/*\r
+ * Entry points for the register check tasks, as described at the top of this\r
+ * file.\r
+ */\r
+static void prvRegTest1Entry( void *pvParameters );\r
+static void prvRegTest2Entry( void *pvParameters );\r
+\r
+/*\r
+ * The implementation of the register check tasks, which are implemented in\r
+ * RegTest.S. These functions are called by prvRegTest1Entry() and\r
+ * prvRegTest2Entry() respectively.\r
+ */\r
+extern void vRegTest1( void );\r
+extern void vRegTest2( void );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Constants used by the register check tasks when checking the FPU registers. */\r
+const double dRegTest1_st7 = 7.0, dRegTest1_st6 = 6.0, dRegTest1_st5 = 5.0, dRegTest1_st4 = 4.0, dRegTest1_st3 = 3.0, dRegTest1_st2 = 2.0, dRegTest1_st1 = 1.0;\r
+const double dRegTest2_st7 = 700.0, dRegTest2_st6 = 600.0, dRegTest2_st5 = 500.0, dRegTest2_st4 = 400.0, dRegTest2_st3 = 300.0, dRegTest2_st2 = 200.0, dRegTest2_st1 = 100.0;\r
+\r
+/* Counters used by the register check tasks to indicate that they are still\r
+executing without having discovered any errors. */\r
+volatile uint32_t ulRegTest1Counter, ulRegTest2Counter;\r
+volatile uint32_t ulCheckLoops = 0;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* See http://www.FreeRTOS.org/RTOS_Intel_Quark_Galileo_GCC.html for usage\r
+instructions. */\r
+void main_full( void )\r
+{\r
+ /* Create all the other standard demo tasks. */\r
+ vCreateBlockTimeTasks();\r
+ vStartSemaphoreTasks( mainSEM_TEST_PRIORITY );\r
+ vStartGenericQueueTasks( mainGEN_QUEUE_TASK_PRIORITY );\r
+ vStartQueuePeekTasks();\r
+ vStartCountingSemaphoreTasks();\r
+ vStartDynamicPriorityTasks();\r
+ vStartQueueOverwriteTask( mainQUEUE_OVERWRITE_TASK_PRIORITY );\r
+ vStartQueueSetTasks();\r
+ vStartRecursiveMutexTasks();\r
+ vStartEventGroupTasks();\r
+ vStartTimerDemoTask( mainTIMER_TEST_PERIOD );\r
+ vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY );\r
+ vStartTaskNotifyTask();\r
+ vStartInterruptQueueTasks();\r
+\r
+ #if configSUPPORT_FPU == 1\r
+ {\r
+ vStartMathTasks( mainMATHS_TASK_PRIORITY );\r
+ }\r
+ #endif /* configSUPPORT_FPU */\r
+\r
+ /* Create the 'check' task, as described at the top of this file. */\r
+ xTaskCreate( prvCheckTask, "Check", configMINIMAL_STACK_SIZE * 2, NULL, configMAX_PRIORITIES - 1, NULL );\r
+\r
+ /* Create the register test tasks, as described at the top of this file. */\r
+ xTaskCreate( prvRegTest1Entry, "Reg1", configMINIMAL_STACK_SIZE, ( void * ) mainREG_TEST_1_PARAMETER, tskIDLE_PRIORITY, NULL );\r
+ xTaskCreate( prvRegTest2Entry, "Reg2", configMINIMAL_STACK_SIZE, ( void * ) mainREG_TEST_2_PARAMETER, tskIDLE_PRIORITY, NULL );\r
+\r
+ /* Death tasks must be created last as they check the number of tasks\r
+ running against the number of tasks expected to be running as part of their\r
+ sanity checks. */\r
+ vCreateSuicidalTasks( tskIDLE_PRIORITY );\r
+\r
+ /* Display HPET Information (Disable in HPET.H). */\r
+ vCreateHPETInfoUpdateTask();\r
+\r
+ /* Start the scheduler itself. */\r
+ vTaskStartScheduler();\r
+\r
+ /* If all is well, the scheduler will now be running, and the following line\r
+ will never be reached. If the following line does execute, then there was\r
+ insufficient FreeRTOS heap memory available for the idle and/or timer tasks\r
+ to be created. See the memory management section on the FreeRTOS web site\r
+ for more details. */\r
+ for( ;; );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvRegTest1Entry( void *pvParameters )\r
+{\r
+ /* Remove compiler warning if configASSERT() is not defined. */\r
+ ( void ) pvParameters;\r
+\r
+ /* Check the parameter is passed in correctly. */\r
+ configASSERT( ( ( uint32_t) pvParameters ) == mainREG_TEST_1_PARAMETER );\r
+\r
+ /* Tell FreeRTOS that this task needs a floating point context. */\r
+ portTASK_USES_FLOATING_POINT();\r
+\r
+ /* Call the assembly file routine that performs the 'reg test' functionality\r
+ as described at the top of this file. */\r
+ vRegTest1();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvRegTest2Entry( void *pvParameters )\r
+{\r
+ /* Remove compiler warning if configASSERT() is not defined. */\r
+ ( void ) pvParameters;\r
+\r
+ /* Check the parameter is passed in correctly. */\r
+ configASSERT( ( ( uint32_t) pvParameters ) == mainREG_TEST_2_PARAMETER );\r
+\r
+ /* Tell FreeRTOS that this task needs a floating point context. */\r
+ portTASK_USES_FLOATING_POINT();\r
+\r
+ /* Call the assembly file routine that performs the 'reg test' functionality\r
+ as described at the top of this file. */\r
+ vRegTest2();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvCheckTask( void *pvParameters )\r
+{\r
+uint32_t ulLastRegTest1Counter = 0UL, ulLastRegTest2Counter = 0UL;\r
+uint32_t ulErrorOccurred, ulElapsedTimeInSeconds = 0UL;\r
+TickType_t xLastExpireTime, xBlockTime = mainNO_ERROR_CHECK_TASK_PERIOD;\r
+BaseType_t xErrorFlag = pdFALSE;\r
+\r
+ /* Avoid compiler warnings. */\r
+ ( void ) pvParameters;\r
+\r
+ /* Initialise the last expire time to the current time. */\r
+ xLastExpireTime = xTaskGetTickCount();\r
+\r
+ /* Message to wait for an update - first update won't happen for X seconds. */\r
+ g_printf_rcc( 5, 2, DEFAULT_SCREEN_COLOR, "Starting task check loop - Please wait for a status update." );\r
+ g_printf_rcc( 6, 2, DEFAULT_SCREEN_COLOR, "No task errors encountered." );\r
+\r
+ for( ;; )\r
+ {\r
+ vTaskDelayUntil( &xLastExpireTime, xBlockTime );\r
+ ulElapsedTimeInSeconds += xBlockTime;\r
+\r
+ /* Have any of the standard demo tasks detected an error in their\r
+ operation? If so, latch the offending test in a bit map so it can be\r
+ printed to the terminal. Once one error has occurred the cycle rate is\r
+ increased to increase the rate at which the LED toggles, which can cause\r
+ further errors to be detected (as some tests will not expect the\r
+ increased cycle rate). */\r
+\r
+ ulErrorOccurred = 0UL;\r
+\r
+ if( xAreQueuePeekTasksStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorOccurred |= ( 0x01UL << 0UL );\r
+ }\r
+\r
+ if( xAreGenericQueueTasksStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorOccurred |= ( 0x01UL << 1UL );\r
+ }\r
+\r
+ if( xAreBlockTimeTestTasksStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorOccurred |= ( 0x01UL << 2UL );\r
+ }\r
+\r
+ if( xAreSemaphoreTasksStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorOccurred |= ( 0x01UL << 3UL );\r
+ }\r
+\r
+ if( xAreCountingSemaphoreTasksStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorOccurred |= ( 0x01UL << 4UL );\r
+ }\r
+\r
+ if( xAreDynamicPriorityTasksStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorOccurred |= ( 0x01UL << 5UL );\r
+ }\r
+\r
+ if( xIsQueueOverwriteTaskStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorOccurred |= ( 0x01UL << 6UL );\r
+ }\r
+\r
+ if( xAreQueueSetTasksStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorOccurred |= ( 0x01UL << 7UL );\r
+ }\r
+\r
+ if( xAreRecursiveMutexTasksStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorOccurred |= ( 0x01UL << 8UL );\r
+ }\r
+\r
+ if( xAreEventGroupTasksStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorOccurred |= ( 0x01UL << 9UL );\r
+ }\r
+\r
+ if( xIsCreateTaskStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorOccurred |= ( 0x01UL << 10UL );\r
+ }\r
+\r
+ if( xAreTimerDemoTasksStillRunning( xBlockTime ) != pdTRUE )\r
+ {\r
+ ulErrorOccurred |= ( 0x01UL << 11UL );\r
+ }\r
+\r
+ if( xAreBlockingQueuesStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorOccurred |= ( 0x01UL << 12UL );\r
+ }\r
+\r
+ if( xAreTaskNotificationTasksStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorOccurred |= ( 1UL << 13UL );\r
+ }\r
+\r
+ if( xAreIntQueueTasksStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorOccurred |= ( 1UL << 14UL );\r
+ }\r
+\r
+ #if configSUPPORT_FPU == 1\r
+ {\r
+ if( xAreMathsTaskStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorOccurred |= ( 0x01UL << 15UL );\r
+ }\r
+ }\r
+ #endif /* configSUPPORT_FPU */\r
+\r
+ /* Check the register test tasks are still looping. */\r
+ if( ulRegTest1Counter == ulLastRegTest1Counter )\r
+ {\r
+ ulErrorOccurred |= ( 0x01UL << 16UL );\r
+ }\r
+ else\r
+ {\r
+ ulLastRegTest1Counter = ulRegTest1Counter;\r
+ }\r
+\r
+ if( ulRegTest2Counter == ulLastRegTest2Counter )\r
+ {\r
+ ulErrorOccurred |= ( 0x01UL << 17UL );\r
+ }\r
+ else\r
+ {\r
+ ulLastRegTest2Counter = ulRegTest2Counter;\r
+ }\r
+\r
+ if( ulErrorOccurred != 0UL )\r
+ {\r
+ /* Decrease the block time, which will increase the rate at\r
+ which the LED blinks - and in so doing - give visual feedback of\r
+ the error status. */\r
+ xBlockTime = mainERROR_CHECK_TASK_PERIOD;\r
+ }\r
+\r
+ /* Print the hex bit pattern, time, and the loop number - just to make\r
+ sure the task is still cycling. */\r
+ g_printf_rcc( 5, 2, DEFAULT_SCREEN_COLOR,\r
+ "Status code: 0x%08x at task check time : %8ds, loop #: %8d\r",\r
+ ulErrorOccurred, ( ulElapsedTimeInSeconds / 1000 ), ( ulCheckLoops + 1 ) );\r
+\r
+ /* Print the current free heap size and the minimum ever free heap\r
+ size. */\r
+ g_printf_rcc( 6, 2, DEFAULT_SCREEN_COLOR,\r
+ "Current free heap: %d bytes, Min. free heap: %d bytes\r",\r
+ xPortGetFreeHeapSize(), xPortGetMinimumEverFreeHeapSize() );\r
+\r
+ /* Show the first error that occurred on a separate line. */\r
+ if( ( xErrorFlag == pdFALSE ) && ( ulErrorOccurred != pdFALSE ) )\r
+ {\r
+ xErrorFlag = pdTRUE;\r
+ g_printf_rcc( 7, 2, ANSI_COLOR_RED,\r
+ "Error code: 0x%08x at check time : %8ds (First Error), loop#: %8d \r",\r
+ ulErrorOccurred, ( ulElapsedTimeInSeconds / 1000 ), ( ulCheckLoops + 1 ) );\r
+ }\r
+\r
+ /* Flash the LED */\r
+ ulBlinkLED();\r
+\r
+ /* Crude Overflow check to keep printf() statements <= 8 digits long */\r
+ ulCheckLoops++;\r
+ if( ulCheckLoops > 10000000UL )\r
+ {\r
+ ulCheckLoops = 0UL;\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
--- /dev/null
+[{000214A0-0000-0000-C000-000000000046}]\r
+Prop3=19,2\r
+[InternetShortcut]\r
+URL=http://www.freertos.org/RTOS_Intel_Quark_Galileo_GCC.html\r
+IDList=\r
--- /dev/null
+/*--------------------------------------------------------------------\r
+ Copyright(c) 2015 Intel Corporation. All rights reserved.\r
+\r
+ Redistribution and use in source and binary forms, with or without\r
+ modification, are permitted provided that the following conditions\r
+ are met:\r
+\r
+ * Redistributions of source code must retain the above copyright\r
+ notice, this list of conditions and the following disclaimer.\r
+ * Redistributions in binary form must reproduce the above copyright\r
+ notice, this list of conditions and the following disclaimer in\r
+ the documentation and/or other materials provided with the\r
+ distribution.\r
+ * Neither the name of Intel Corporation nor the names of its\r
+ contributors may be used to endorse or promote products derived\r
+ from this software without specific prior written permission.\r
+\r
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
+ "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
+ LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
+ A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\r
+ OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\r
+ SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\r
+ DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\r
+ THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ --------------------------------------------------------------------*/\r
+\r
+/*-----------------------------------------------------------------------\r
+ * Any required includes\r
+ *------------------------------------------------------------------------\r
+ */\r
+#include "GPIO_I2C.h"\r
+\r
+/*-----------------------------------------------------------------------\r
+ * Any required local definitions\r
+ *------------------------------------------------------------------------\r
+ */\r
+#ifndef NULL\r
+ #define NULL (void *)0\r
+#endif\r
+/*-----------------------------------------------------------------------\r
+ * Function prototypes\r
+ *------------------------------------------------------------------------\r
+ */\r
+static void vGalileoRouteLEDPins(void);\r
+\r
+/*-----------------------------------------------------------------------\r
+ * Static variables\r
+ *------------------------------------------------------------------------\r
+ */\r
+static struct BOARD_GPIO_CONTROLLER_CONFIG GpioConfig;\r
+static struct BOARD_LEGACY_GPIO_CONFIG LegacyGpioConfig;\r
+\r
+static uint32_t LegacyGpioBase = 0;\r
+static uint32_t IohGpioBase = 0;\r
+static uint32_t I2CGpioBase = 0;\r
+\r
+static uint32_t bGalileoGPIOInitialized = FALSE;\r
+\r
+/*-----------------------------------------------------------------------\r
+ * GPIO support functions\r
+ *------------------------------------------------------------------------\r
+ */\r
+ static uint32_t pciIOread32(uint32_t addr)\r
+ {\r
+ outl(IO_PCI_ADDRESS_PORT, addr);\r
+ uint32_t data = inl(IO_PCI_DATA_PORT);\r
+ return data;\r
+ }\r
+ /*-----------------------------------------------------------*/\r
+\r
+ static void pciIOwrite32(uint32_t addr, uint32_t IO_data)\r
+ {\r
+ outl(IO_PCI_ADDRESS_PORT, addr);\r
+ outl(IO_PCI_DATA_PORT, IO_data );\r
+ }\r
+ /*-----------------------------------------------------------*/\r
+\r
+ static int32_t uiGalileoGPIORead(uint32_t Offset, uint8_t UseMask)\r
+ {\r
+ // Keep reserved bits [31:8]\r
+ if (UseMask)\r
+ return *((volatile uint32_t *) (uintn_t)(IohGpioBase + Offset)) & 0xFFFFFF00;\r
+ else\r
+ return *((volatile uint32_t *) (uintn_t)(IohGpioBase + Offset));\r
+ }\r
+ /*-----------------------------------------------------------*/\r
+\r
+ static void vGalileoGPIOWrite(uint32_t Offset, uint32_t WriteData32)\r
+ {\r
+ uint32_t Data32 = uiGalileoGPIORead(Offset, true);\r
+ if (Offset != GPIO_INTSTATUS)\r
+ Data32 |= (WriteData32 & 0x000FFFFF);\r
+ *((volatile uint32_t *) (uintn_t)(IohGpioBase + Offset)) = Data32;\r
+ }\r
+ /*-----------------------------------------------------------*/\r
+\r
+ static int32_t uiGalileoLegacyGPIOPCIRead(uint32_t addr, uint32_t Mask)\r
+ {\r
+ // Keep reserved bits (Mask Varies)\r
+ return pciIOread32(addr) & Mask;\r
+ }\r
+ /*-----------------------------------------------------------*/\r
+\r
+ static void vGalileoLegacyGPIOPCIWrite(uint32_t addr, uint32_t WriteData32, uint32_t Mask)\r
+ {\r
+ uint32_t Data32 = uiGalileoLegacyGPIOPCIRead(addr, Mask);\r
+ Data32 |= (WriteData32 & ~Mask);\r
+ pciIOwrite32(addr, Data32);\r
+ }\r
+ /*-----------------------------------------------------------*/\r
+\r
+ static int32_t uiGalileoLegacyGPIOPortRead(uint32_t addr, uint32_t Mask)\r
+ {\r
+ // Keep reserved bits (Mask Varies)\r
+ return inl(addr) & Mask;\r
+ }\r
+ /*-----------------------------------------------------------*/\r
+\r
+ static void vGalileoLegacyGPIOPortRMW(uint32_t addr, uint32_t WriteData32, uint32_t Mask)\r
+ {\r
+ uint32_t Data32 = uiGalileoLegacyGPIOPortRead(addr, Mask);\r
+ Data32 |= (WriteData32 & ~Mask);\r
+ outl(addr, Data32);\r
+ }\r
+ /*-----------------------------------------------------------*/\r
+\r
+ /*-----------------------------------------------------------------------\r
+ * Controller initialization functions\r
+ *------------------------------------------------------------------------\r
+ */\r
+ void vGalileoInitializeLegacyGPIO(void)\r
+ {\r
+ // Read Register Default Values into Structure\r
+ struct BOARD_LEGACY_GPIO_CONFIG LegacyGPIOConfigTable[] =\r
+ { PLATFORM_LEGACY_GPIO_CONFIG_DEFINITION };\r
+\r
+ // BDF for Legacy GPIO (from the Quark Datasheet)\r
+ uint8_t Bus = LEGACY_GPIO_BUS_NUMBER;\r
+ uint8_t Device = LEGACY_GPIO_DEVICE_NUMBER;\r
+ uint8_t Func = LEGACY_GPIO_FUNCTION_NUMBER;\r
+\r
+ // Get PCI Configuration IO Address\r
+ LegacyGpioBase =\r
+ uiGalileoLegacyGPIOPCIRead(IO_PCI_ADDRESS(Bus, Device, Func, R_QNC_LPC_GBA_BASE), B_QNC_LPC_GPA_BASE_MASK);\r
+\r
+ // Quiet compiler by doing a legacy GPIO write\r
+ uint32_t PciCmd = uiGalileoLegacyGPIOPCIRead((LegacyGpioBase + PCI_REG_PCICMD), 0xFFFFFFFF);\r
+ vGalileoLegacyGPIOPCIWrite((LegacyGpioBase + PCI_REG_PCICMD), (PciCmd | 0x7), 0xFFFFFFFF);\r
+\r
+ // Setup Structure\r
+ LegacyGpioConfig = LegacyGPIOConfigTable[0];\r
+\r
+ // Update values\r
+ vGalileoLegacyGPIOPortRMW(LegacyGpioBase + R_QNC_GPIO_CGEN_CORE_WELL, LegacyGpioConfig.CoreWellEnable, 0xFFFFFFFC);\r
+ vGalileoLegacyGPIOPortRMW(LegacyGpioBase + R_QNC_GPIO_CGIO_CORE_WELL, LegacyGpioConfig.CoreWellIoSelect, 0xFFFFFFFC);\r
+ vGalileoLegacyGPIOPortRMW(LegacyGpioBase + R_QNC_GPIO_CGLVL_CORE_WELL, LegacyGpioConfig.CoreWellLvlForInputOrOutput, 0xFFFFFFFC);\r
+ vGalileoLegacyGPIOPortRMW(LegacyGpioBase + R_QNC_GPIO_CGTPE_CORE_WELL, LegacyGpioConfig.CoreWellTriggerPositiveEdge, 0xFFFFFFFC);\r
+ vGalileoLegacyGPIOPortRMW(LegacyGpioBase + R_QNC_GPIO_CGTNE_CORE_WELL, LegacyGpioConfig.CoreWellTriggerNegativeEdge, 0xFFFFFFFC);\r
+ vGalileoLegacyGPIOPortRMW(LegacyGpioBase + R_QNC_GPIO_CGGPE_CORE_WELL, LegacyGpioConfig.ResumeWellGPEEnable, 0xFFFFFFFC);\r
+ vGalileoLegacyGPIOPortRMW(LegacyGpioBase + R_QNC_GPIO_CGSMI_CORE_WELL, LegacyGpioConfig.ResumeWellSMIEnable, 0xFFFFFFFC);\r
+ vGalileoLegacyGPIOPortRMW(LegacyGpioBase + R_QNC_GPIO_CGEN_CORE_WELL, LegacyGpioConfig.CoreWellTriggerStatus, 0xFFFFFFFC);\r
+ vGalileoLegacyGPIOPortRMW(LegacyGpioBase + R_QNC_GPIO_CNMIEN_CORE_WELL, LegacyGpioConfig.ResumeWellNMIEnable, 0xFFFFFFFC);\r
+ vGalileoLegacyGPIOPortRMW(LegacyGpioBase + R_QNC_GPIO_RGEN_RESUME_WELL, LegacyGpioConfig.ResumeWellEnable, 0xFFFFFFC0);\r
+ vGalileoLegacyGPIOPortRMW(LegacyGpioBase + R_QNC_GPIO_RGIO_RESUME_WELL, LegacyGpioConfig.ResumeWellIoSelect, 0xFFFFFFC0);\r
+ vGalileoLegacyGPIOPortRMW(LegacyGpioBase + R_QNC_GPIO_RGLVL_RESUME_WELL, LegacyGpioConfig.ResumeWellLvlForInputOrOutput, 0xFFFFFFC0);\r
+ vGalileoLegacyGPIOPortRMW(LegacyGpioBase + R_QNC_GPIO_RGTPE_RESUME_WELL, LegacyGpioConfig.ResumeWellTriggerPositiveEdge, 0xFFFFFFC0);\r
+ vGalileoLegacyGPIOPortRMW(LegacyGpioBase + R_QNC_GPIO_RGTNE_RESUME_WELL, LegacyGpioConfig.ResumeWellTriggerNegativeEdge, 0xFFFFFFC0);\r
+ vGalileoLegacyGPIOPortRMW(LegacyGpioBase + R_QNC_GPIO_RGGPE_RESUME_WELL, LegacyGpioConfig.CoreWellGPEEnable, 0xFFFFFFC0);\r
+ vGalileoLegacyGPIOPortRMW(LegacyGpioBase + R_QNC_GPIO_RGSMI_RESUME_WELL, LegacyGpioConfig.CoreWellSMIEnable, 0xFFFFFFC0);\r
+ vGalileoLegacyGPIOPortRMW(LegacyGpioBase + R_QNC_GPIO_RGTS_RESUME_WELL, LegacyGpioConfig.ResumeWellTriggerStatus, 0xFFFFFFC0);\r
+ vGalileoLegacyGPIOPortRMW(LegacyGpioBase + R_QNC_GPIO_RNMIEN_RESUME_WELL, LegacyGpioConfig.CoreWellNMIEnable, 0xFFFFFFC0);\r
+ }\r
+ /*-----------------------------------------------------------*/\r
+\r
+ void vGalileoInitializeGpioController(void)\r
+ {\r
+ // Read Register Default Values into Structure\r
+ struct BOARD_GPIO_CONTROLLER_CONFIG BoardGpioControllerConfigTable[] =\r
+ { PLATFORM_GPIO_CONTROLLER_CONFIG_DEFINITION };\r
+\r
+ // BDF for I2C Controller (from the Quark Datasheet)\r
+ uint8_t Bus = IOH_I2C_GPIO_BUS_NUMBER;\r
+ uint8_t Device = IOH_I2C_GPIO_DEVICE_NUMBER;\r
+ uint8_t Func = IOH_I2C_GPIO_FUNCTION_NUMBER;\r
+\r
+ // Get PCI Configuration MMIO Address\r
+ uint32_t gpio_controller_base = MMIO_PCI_ADDRESS(Bus, Device, Func, 0);\r
+\r
+ // Get Vendor and Device IDs\r
+ uint16_t PciVid = mem_read(gpio_controller_base, PCI_REG_VID, 2);\r
+ uint16_t PciDid = mem_read(gpio_controller_base, PCI_REG_DID, 2);\r
+\r
+ // Check for valid VID and DID\r
+ if((PciVid == V_IOH_I2C_GPIO_VENDOR_ID) && (PciDid == V_IOH_I2C_GPIO_DEVICE_ID))\r
+ {\r
+ // Read PCICMD\r
+ uint8_t PciCmd = mem_read(gpio_controller_base, PCI_REG_PCICMD, 1);\r
+ // Enable Bus Master(Bit2), MMIO Space(Bit1) & I/O Space(Bit0)\r
+ mem_write(gpio_controller_base, PCI_REG_PCICMD, 1, (PciCmd | 0x7));\r
+ // Read MEM_BASE\r
+ IohGpioBase = mem_read(gpio_controller_base, R_IOH_GPIO_MEMBAR, 4);\r
+ // Setup Structure\r
+ GpioConfig = BoardGpioControllerConfigTable[0];\r
+ // IEN- Interrupt Enable Register\r
+ vGalileoGPIOWrite(GPIO_INTEN, GpioConfig.IntEn);\r
+ // ISTATUS- Interrupt Status Register\r
+ vGalileoGPIOWrite(GPIO_INTSTATUS, 0);\r
+ // GPIO SWPORTA Data Register - GPIO_SWPORTA_DR\r
+ vGalileoGPIOWrite(GPIO_SWPORTA_DR, GpioConfig.PortADR);\r
+ // GPIO SWPORTA Data Direction Register - GPIO_SWPORTA_DDR\r
+ vGalileoGPIOWrite(GPIO_SWPORTA_DDR, GpioConfig.PortADir);\r
+ // Interrupt Mask Register - GPIO_INTMASK\r
+ vGalileoGPIOWrite(GPIO_INTMASK, GpioConfig.IntMask);\r
+ // Interrupt Level Type Register - GPIO_INTTYPE_LEVEL\r
+ vGalileoGPIOWrite(GPIO_INTTYPE_LEVEL, GpioConfig.IntType);\r
+ // Interrupt Polarity Type Register - GPIO_INT_POLARITY\r
+ vGalileoGPIOWrite(GPIO_INT_POLARITY, GpioConfig.IntPolarity);\r
+ // Interrupt Debounce Type Register - GPIO_DEBOUNCE\r
+ vGalileoGPIOWrite(GPIO_DEBOUNCE, GpioConfig.Debounce);\r
+ // Interrupt Clock Synchronization Register - GPIO_LS_SYNC\r
+ vGalileoGPIOWrite(GPIO_LS_SYNC, GpioConfig.LsSync);\r
+ bGalileoGPIOInitialized = true;\r
+ }\r
+ }\r
+ /*-----------------------------------------------------------*/\r
+\r
+ /*-----------------------------------------------------------------------\r
+ * I/O direction and level setting functions\r
+ *------------------------------------------------------------------------\r
+ */\r
+ void vGalileoSetGPIOBitDirection(uint32_t GPIONumber, uint32_t Direction)\r
+ {\r
+ /* Check Range. */\r
+ if(GPIONumber <= 9)\r
+ {\r
+ /* setup gpio direction. */\r
+ if (bGalileoGPIOInitialized)\r
+ {\r
+ if(Direction == GPIO_OUTPUT)\r
+ GpioConfig.PortADir |= (1 << GPIONumber);\r
+ else\r
+ GpioConfig.PortADir &= ~(1 << GPIONumber);\r
+ vGalileoGPIOWrite(GPIO_SWPORTA_DDR, GpioConfig.PortADir);\r
+ }\r
+ }\r
+ }\r
+ /*-----------------------------------------------------------*/\r
+\r
+ void vGalileoSetGPIOBitLevel(uint32_t GPIONumber, uint32_t Level)\r
+ {\r
+ /* Check Range. */\r
+ if(GPIONumber <= 9)\r
+ {\r
+ /* Set the bit high or low. */\r
+ if (bGalileoGPIOInitialized)\r
+ {\r
+ // 1 for on, 0 for off.\r
+ if (Level == HIGH)\r
+ GpioConfig.PortADR |= (1 << GPIONumber);\r
+ else\r
+ GpioConfig.PortADR &= ~(1 << GPIONumber);\r
+ vGalileoGPIOWrite(GPIO_SWPORTA_DR, GpioConfig.PortADR);\r
+ }\r
+ }\r
+ }\r
+ /*-----------------------------------------------------------*/\r
+\r
+ static void LegacyGpioSetLevel(uint32_t RegOffset, uint32_t GpioNum, uint8_t HighLevel)\r
+ {\r
+ uint32_t RegValue;\r
+ uint32_t legacy_gpio_base;\r
+ uint32_t GpioNumMask;\r
+ uint8_t Bus = LEGACY_GPIO_BUS_NUMBER;\r
+ uint8_t Device = LEGACY_GPIO_DEVICE_NUMBER;\r
+ uint8_t Func = LEGACY_GPIO_FUNCTION_NUMBER;\r
+\r
+ // Get PCI Configuration IO Address\r
+ legacy_gpio_base =\r
+ uiGalileoLegacyGPIOPCIRead(IO_PCI_ADDRESS(Bus, Device, Func, R_QNC_LPC_GBA_BASE), B_QNC_LPC_GPA_BASE_MASK);\r
+\r
+ // Read register (Port I/O )\r
+ RegValue = inl(legacy_gpio_base + RegOffset);\r
+\r
+ // Set Data and mask\r
+ GpioNumMask = (1 << GpioNum);\r
+ if (HighLevel)\r
+ RegValue |= (GpioNumMask);\r
+ else\r
+ RegValue &= ~(GpioNumMask);\r
+\r
+ // Write the data (Port I/O )\r
+ outl((legacy_gpio_base + RegOffset), RegValue);\r
+ }\r
+ /*-----------------------------------------------------------*/\r
+\r
+ void vGalileoLegacyGPIOInitializationForLED(void)\r
+ {\r
+ // Setup multiplexers to route GPIO_SUS<5> to LED\r
+ vGalileoRouteLEDPins();\r
+\r
+ // Set GPIO_SUS<5> as output\r
+ LegacyGpioSetLevel (R_QNC_GPIO_RGIO_RESUME_WELL,\r
+ GALILEO_GEN2_FLASH_UPDATE_LED_RESUMEWELL_GPIO, GPIO_OUTPUT);\r
+\r
+ // Set GPIO_SUS<5> level to low\r
+ LegacyGpioSetLevel (R_QNC_GPIO_RGLVL_RESUME_WELL,\r
+ GALILEO_GEN2_FLASH_UPDATE_LED_RESUMEWELL_GPIO, LOW);\r
+ }\r
+ /*-----------------------------------------------------------*/\r
+\r
+ void vGalileoBlinkLEDUsingLegacyGPIO(uint32_t Level)\r
+ {\r
+ LegacyGpioSetLevel (R_QNC_GPIO_RGLVL_RESUME_WELL,\r
+ GALILEO_GEN2_FLASH_UPDATE_LED_RESUMEWELL_GPIO, Level);\r
+ }\r
+ /*-----------------------------------------------------------*/\r
+\r
+ /*-----------------------------------------------------------------------\r
+ * I2C support functions\r
+ *------------------------------------------------------------------------\r
+ */\r
+ static inline uint64_t rdtsc(void)\r
+ {\r
+ uint32_t lo, hi;\r
+ uint64_t tsc;\r
+ __asm__ __volatile__ ("rdtsc" : "=a" (lo), "=d" (hi));\r
+ tsc = hi;\r
+ tsc <<= 32;\r
+ tsc |= lo;\r
+ return tsc;\r
+ }\r
+ /*-----------------------------------------------------------*/\r
+\r
+ void vMicroSecondDelay(uint32_t DelayTime)\r
+ {\r
+ uint64_t diff_in_us = 0;\r
+ uint64_t cpufreq_in_mhz = 400;\r
+ uint64_t tsc_start = rdtsc();\r
+ uint64_t tsc_current = tsc_start;\r
+\r
+ do\r
+ {\r
+ diff_in_us = ((tsc_current - tsc_start) / cpufreq_in_mhz);\r
+ tsc_current = rdtsc();\r
+ }\r
+ while (diff_in_us < (uint64_t) DelayTime);\r
+ }\r
+ /*-----------------------------------------------------------*/\r
+\r
+ void vMilliSecondDelay(uint32_t DelayTime)\r
+ {\r
+ vMicroSecondDelay (DelayTime * 1000);\r
+ }\r
+ /*-----------------------------------------------------------*/\r
+\r
+ static uintn_t GetI2CIoPortBaseAddress(void)\r
+ {\r
+ uint8_t Bus = IOH_I2C_GPIO_BUS_NUMBER;\r
+ uint8_t Device = IOH_I2C_GPIO_DEVICE_NUMBER;\r
+ int8_t Func = IOH_I2C_GPIO_FUNCTION_NUMBER;\r
+ uint32_t I2C_controller_base = MMIO_PCI_ADDRESS(Bus, Device, Func, 0);\r
+ uintn_t I2CIoPortBaseAddress = mem_read(I2C_controller_base, R_IOH_I2C_MEMBAR, 4);\r
+ return I2CIoPortBaseAddress;\r
+ }\r
+ /*-----------------------------------------------------------*/\r
+\r
+ static void EnableI2CMmioSpace(void)\r
+ {\r
+ uint8_t Bus = IOH_I2C_GPIO_BUS_NUMBER;\r
+ uint8_t Device = IOH_I2C_GPIO_DEVICE_NUMBER;\r
+ uint8_t Func = IOH_I2C_GPIO_FUNCTION_NUMBER;\r
+ uint32_t I2C_controller_base = MMIO_PCI_ADDRESS(Bus, Device, Func, 0);\r
+ uint8_t PciCmd = mem_read(I2C_controller_base, PCI_REG_PCICMD, 1);\r
+ mem_write(I2C_controller_base, PCI_REG_PCICMD, 1, (PciCmd | 0x7));\r
+ }\r
+ /*-----------------------------------------------------------*/\r
+\r
+ static void DisableI2CController(void)\r
+ {\r
+ uintn_t I2CIoPortBaseAddress;\r
+ uint32_t Addr;\r
+ uint32_t Data;\r
+ uint8_t PollCount = 0;\r
+\r
+ // Get I2C Memory Mapped registers base address.\r
+ I2CIoPortBaseAddress = GetI2CIoPortBaseAddress ();\r
+\r
+ // Disable the I2C Controller by setting IC_ENABLE.ENABLE to zero\r
+ Addr = I2CIoPortBaseAddress + I2C_REG_ENABLE;\r
+ Data = *((volatile uint32_t *) (uintn_t)(Addr));\r
+ Data &= ~B_I2C_REG_ENABLE;\r
+ *((volatile uint32_t *) (uintn_t)(Addr)) = Data;\r
+\r
+ // Read the IC_ENABLE_STATUS.IC_EN Bit to check if Controller is disabled\r
+ Data = 0xFF;\r
+ Addr = I2CIoPortBaseAddress + I2C_REG_ENABLE_STATUS;\r
+ Data = *((volatile uint32_t *) (uintn_t)(Addr)) & I2C_REG_ENABLE_STATUS;\r
+ while (Data != 0)\r
+ {\r
+ // Poll the IC_ENABLE_STATUS.IC_EN Bit to check if Controller is disabled, until timeout (TI2C_POLL*MAX_T_POLL_COUNT).\r
+ if (++PollCount >= MAX_T_POLL_COUNT)\r
+ break;\r
+ vMicroSecondDelay(TI2C_POLL);\r
+ Data = *((volatile uint32_t *) (uintn_t)(Addr));\r
+ Data &= I2C_REG_ENABLE_STATUS;\r
+ }\r
+\r
+ // Read IC_CLR_INTR register to automatically clear the combined interrupt,\r
+ // all individual interrupts and the IC_TX_ABRT_SOURCE register.\r
+ if (PollCount < MAX_T_POLL_COUNT)\r
+ {\r
+ Addr = I2CIoPortBaseAddress + I2C_REG_CLR_INT;\r
+ Data = *((volatile uint32_t *) (uintn_t)(Addr));\r
+ }\r
+ }\r
+ /*-----------------------------------------------------------*/\r
+\r
+ static void EnableI2CController(void)\r
+ {\r
+ uintn_t I2CIoPortBaseAddress;\r
+ uint32_t Addr;\r
+ uint32_t Data;\r
+\r
+ // Get I2C Memory Mapped registers base address.\r
+ I2CIoPortBaseAddress = GetI2CIoPortBaseAddress ();\r
+\r
+ // Enable the I2C Controller by setting IC_ENABLE.ENABLE to 1\r
+ Addr = I2CIoPortBaseAddress + I2C_REG_ENABLE;\r
+ Data = *((volatile uint32_t *) (uintn_t)(Addr));\r
+ Data |= B_I2C_REG_ENABLE;\r
+ *((volatile uint32_t *) (uintn_t)(Addr)) = Data;\r
+\r
+ // Clear overflow and abort error status bits before transactions.\r
+ Addr = I2CIoPortBaseAddress + I2C_REG_CLR_RX_OVER;\r
+ Data = *((volatile uint32_t *) (uintn_t)(Addr));\r
+ Addr = I2CIoPortBaseAddress + I2C_REG_CLR_TX_OVER;\r
+ Data = *((volatile uint32_t *) (uintn_t)(Addr));\r
+ Addr = I2CIoPortBaseAddress + I2C_REG_CLR_TX_ABRT;\r
+ Data = *((volatile uint32_t *) (uintn_t)(Addr));\r
+ }\r
+ /*-----------------------------------------------------------*/\r
+\r
+ static uint32_t InitializeInternal(I2C_ADDR_MODE AddrMode)\r
+ {\r
+ uintn_t I2CIoPortBaseAddress;\r
+ uintn_t Addr;\r
+ uint32_t Data;\r
+ uint32_t Status = 0;\r
+\r
+ // Enable access to I2C Controller MMIO space.\r
+ EnableI2CMmioSpace ();\r
+\r
+ // Disable I2C Controller initially\r
+ DisableI2CController ();\r
+\r
+ // Get I2C Memory Mapped registers base address.\r
+ I2CIoPortBaseAddress = GetI2CIoPortBaseAddress ();\r
+\r
+ // Clear START_DET\r
+ Addr = I2CIoPortBaseAddress + I2C_REG_CLR_START_DET;\r
+ Data = *((volatile uint32_t *) (uintn_t)(Addr));\r
+ Data &= ~B_I2C_REG_CLR_START_DET;\r
+ *((volatile uint32_t *) (uintn_t)(Addr)) = Data;\r
+\r
+ // Clear STOP_DET\r
+ Addr = I2CIoPortBaseAddress + I2C_REG_CLR_STOP_DET;\r
+ Data = *((volatile uint32_t *) (uintn_t)(Addr));\r
+ Data &= ~B_I2C_REG_CLR_STOP_DET;\r
+ *((volatile uint32_t *) (uintn_t)(Addr)) = Data;\r
+\r
+ // Set addressing mode to user defined (7 or 10 bit) and\r
+ // speed mode to that defined by PCD (standard mode default).\r
+ Addr = I2CIoPortBaseAddress + I2C_REG_CON;\r
+ Data = *((volatile uint32_t *) (uintn_t)(Addr));\r
+\r
+ // Set Addressing Mode\r
+ if (AddrMode == EfiI2CSevenBitAddrMode)\r
+ Data &= ~B_I2C_REG_CON_10BITADD_MASTER;\r
+ else\r
+ Data |= B_I2C_REG_CON_10BITADD_MASTER;\r
+\r
+ // Set Speed Mode\r
+ Data &= ~B_I2C_REG_CON_SPEED;\r
+\r
+ // Default to slow mode\r
+ Data |= BIT1;\r
+ *((volatile uint32_t *) (uintn_t)(Addr)) = Data;\r
+ Data = *((volatile uint32_t *) (uintn_t)(Addr));\r
+ return Status;\r
+ }\r
+ /*-----------------------------------------------------------*/\r
+\r
+ static void I2cEntry(uint16_t *SaveCmdPtr, uint32_t *SaveBar0Ptr)\r
+ {\r
+ uint8_t Bus = IOH_I2C_GPIO_BUS_NUMBER;\r
+ uint8_t Device = IOH_I2C_GPIO_DEVICE_NUMBER;\r
+ uint8_t Func = IOH_I2C_GPIO_FUNCTION_NUMBER;\r
+ uint32_t I2C_controller_base = MMIO_PCI_ADDRESS(Bus, Device, Func, 0);\r
+\r
+ I2CGpioBase = mem_read(I2C_controller_base, R_IOH_I2C_MEMBAR, 4);\r
+ *SaveBar0Ptr = I2CGpioBase;\r
+ if (((*SaveBar0Ptr) & B_IOH_I2C_GPIO_MEMBAR_ADDR_MASK) == 0)\r
+ {\r
+ mem_write(I2C_controller_base, R_IOH_I2C_MEMBAR, 4, IO_PCI_ADDRESS(Bus, Device, Func, 0));\r
+ // also Save Cmd Register, Setup by InitializeInternal later during xfers.\r
+ *SaveCmdPtr = mem_read(I2C_controller_base, PCI_REG_PCICMD, 1);\r
+ }\r
+ }\r
+ /*-----------------------------------------------------------*/\r
+\r
+ static void I2cExit(uint16_t SaveCmd, uint32_t SaveBar0)\r
+ {\r
+ if ((SaveBar0 & B_IOH_I2C_GPIO_MEMBAR_ADDR_MASK) == 0)\r
+ {\r
+ uint8_t Bus = IOH_I2C_GPIO_BUS_NUMBER;\r
+ uint8_t Device = IOH_I2C_GPIO_DEVICE_NUMBER;\r
+ uint8_t Func = IOH_I2C_GPIO_FUNCTION_NUMBER;\r
+ uint32_t I2C_controller_base = MMIO_PCI_ADDRESS(Bus, Device, Func, 0);\r
+ mem_write(I2C_controller_base, PCI_REG_PCICMD, 1, SaveCmd);\r
+ mem_write(I2C_controller_base, R_IOH_I2C_MEMBAR, 4, SaveBar0);\r
+ }\r
+ }\r
+ /*-----------------------------------------------------------*/\r
+\r
+ static uint32_t WaitForStopDet(void)\r
+ {\r
+ uintn_t I2CIoPortBaseAddress;\r
+ uint32_t Addr;\r
+ uint32_t Data;\r
+ uint32_t PollCount = 0;\r
+ uint32_t Status = 0;\r
+\r
+ // Get I2C Memory Mapped registers base address.\r
+ I2CIoPortBaseAddress = GetI2CIoPortBaseAddress ();\r
+\r
+ // Wait for STOP Detect.\r
+ Addr = I2CIoPortBaseAddress + I2C_REG_RAW_INTR_STAT;\r
+ do\r
+ {\r
+ Data = *((volatile uint32_t *) (uintn_t)(Addr));\r
+ if ((Data & I2C_REG_RAW_INTR_STAT_TX_ABRT) != 0)\r
+ {\r
+ Status = -1;\r
+ break;\r
+ }\r
+ if ((Data & I2C_REG_RAW_INTR_STAT_TX_OVER) != 0)\r
+ {\r
+ Status = -1;\r
+ break;\r
+ }\r
+ if ((Data & I2C_REG_RAW_INTR_STAT_RX_OVER) != 0)\r
+ {\r
+ Status = -1;\r
+ break;\r
+ }\r
+ if ((Data & I2C_REG_RAW_INTR_STAT_STOP_DET) != 0)\r
+ {\r
+ Status = 0;\r
+ break;\r
+ }\r
+ vMicroSecondDelay(TI2C_POLL);\r
+ PollCount++;\r
+ if (PollCount >= MAX_STOP_DET_POLL_COUNT)\r
+ {\r
+ Status = -1;\r
+ break;\r
+ }\r
+ } while (TRUE);\r
+\r
+ return Status;\r
+ }\r
+ /*-----------------------------------------------------------*/\r
+\r
+ uint32_t WriteMultipleByte(uintn_t I2CAddress, uint8_t *WriteBuffer, uintn_t Length)\r
+ {\r
+ uintn_t I2CIoPortBaseAddress;\r
+ uintn_t Index;\r
+ uintn_t Addr;\r
+ uint32_t Data;\r
+ uint32_t Status = 0;\r
+\r
+ if (Length > I2C_FIFO_SIZE)\r
+ return -1; // Routine does not handle xfers > fifo size.\r
+\r
+ I2CIoPortBaseAddress = GetI2CIoPortBaseAddress ();\r
+\r
+ // Write to the IC_TAR register the address of the slave device to be addressed\r
+ Addr = I2CIoPortBaseAddress + I2C_REG_TAR;\r
+ Data = *((volatile uint32_t *) (uintn_t)(Addr));\r
+ Data &= ~B_I2C_REG_TAR;\r
+ Data |= I2CAddress;\r
+ *((volatile uint32_t *) (uintn_t)(Addr)) = Data;\r
+\r
+ // Enable the I2C Controller\r
+ EnableI2CController ();\r
+\r
+ // Write the data and transfer direction to the IC_DATA_CMD register.\r
+ // Also specify that transfer should be terminated by STOP condition.\r
+ Addr = I2CIoPortBaseAddress + I2C_REG_DATA_CMD;\r
+ for (Index = 0; Index < Length; Index++)\r
+ {\r
+ Data = *((volatile uint32_t *) (uintn_t)(Addr));\r
+ Data &= 0xFFFFFF00;\r
+ Data |= (uint8_t)WriteBuffer[Index];\r
+ Data &= ~B_I2C_REG_DATA_CMD_RW;\r
+ if (Index == (Length-1))\r
+ Data |= B_I2C_REG_DATA_CMD_STOP;\r
+ *((volatile uint32_t *) (uintn_t)(Addr)) = Data;\r
+ }\r
+\r
+ // Wait for transfer completion\r
+ Status = WaitForStopDet ();\r
+\r
+ // Ensure I2C Controller disabled.\r
+ DisableI2CController ();\r
+\r
+ return Status;\r
+ }\r
+ /*-----------------------------------------------------------*/\r
+\r
+ static void I2CWriteMultipleBytes(I2C_DEVICE_ADDRESS SlaveAddress,\r
+ I2C_ADDR_MODE AddrMode, uintn_t *Length, void *Buffer)\r
+ {\r
+ uintn_t I2CAddress;\r
+ uint16_t SaveCmd;\r
+ uint32_t SaveBar0;\r
+\r
+ if (Buffer != NULL && Length != NULL)\r
+ {\r
+ SaveCmd = 0;\r
+ SaveBar0 = 0;\r
+ I2cEntry (&SaveCmd, &SaveBar0);\r
+ if (InitializeInternal(AddrMode) == 0)\r
+ {\r
+ I2CAddress = SlaveAddress.I2CDeviceAddress;\r
+ WriteMultipleByte(I2CAddress, Buffer, (*Length));\r
+ }\r
+ I2cExit (SaveCmd, SaveBar0);\r
+ }\r
+ }\r
+ /*-----------------------------------------------------------*/\r
+\r
+ uint32_t ReadMultipleByte(uintn_t I2CAddress, uint8_t *Buffer,\r
+ uintn_t WriteLength, uintn_t ReadLength)\r
+ {\r
+ uintn_t I2CIoPortBaseAddress;\r
+ uintn_t Index;\r
+ uintn_t Addr;\r
+ uint32_t Data;\r
+ uint8_t PollCount;\r
+ uint32_t Status;\r
+\r
+ if (WriteLength > I2C_FIFO_SIZE || ReadLength > I2C_FIFO_SIZE)\r
+ return -1; // Routine does not handle xfers > fifo size.\r
+\r
+ I2CIoPortBaseAddress = GetI2CIoPortBaseAddress ();\r
+\r
+ // Write to the IC_TAR register the address of the slave device to be addressed\r
+ Addr = I2CIoPortBaseAddress + I2C_REG_TAR;\r
+ Data = *((volatile uint32_t *) (uintn_t)(Addr));\r
+ Data &= ~B_I2C_REG_TAR;\r
+ Data |= I2CAddress;\r
+ *((volatile uint32_t *) (uintn_t)(Addr)) = Data;\r
+\r
+ // Enable the I2C Controller\r
+ EnableI2CController ();\r
+\r
+ // Write the data (sub-addresses) to the IC_DATA_CMD register.\r
+ Addr = I2CIoPortBaseAddress + I2C_REG_DATA_CMD;\r
+ for (Index = 0; Index < WriteLength; Index++)\r
+ {\r
+ Data = *((volatile uint32_t *) (uintn_t)(Addr));\r
+ Data &= 0xFFFFFF00;\r
+ Data |= (uint8_t)Buffer[Index];\r
+ Data &= ~B_I2C_REG_DATA_CMD_RW;\r
+ *((volatile uint32_t *) (uintn_t)(Addr)) = Data;\r
+ }\r
+\r
+ // Issue Read Transfers for each byte (Restart issued when write/read bit changed).\r
+ for (Index = 0; Index < ReadLength; Index++)\r
+ {\r
+ Data = *((volatile uint32_t *) (uintn_t)(Addr));\r
+ Data |= B_I2C_REG_DATA_CMD_RW;\r
+ // Issue a STOP for last read transfer.\r
+ if (Index == (ReadLength-1))\r
+ Data |= B_I2C_REG_DATA_CMD_STOP;\r
+ *((volatile uint32_t *) (uintn_t)(Addr)) = Data;\r
+ }\r
+\r
+ // Wait for STOP condition.\r
+ Status = WaitForStopDet();\r
+ if (Status != 0)\r
+ {\r
+ // Poll Receive FIFO Buffer Level register until valid (upto MAX_T_POLL_COUNT times).\r
+ Data = 0;\r
+ PollCount = 0;\r
+ Addr = I2CIoPortBaseAddress + I2C_REG_RXFLR;\r
+ Data = *((volatile uint32_t *) (uintn_t)(Addr));\r
+ while ((Data != ReadLength) && (PollCount < MAX_T_POLL_COUNT))\r
+ {\r
+ vMicroSecondDelay(TI2C_POLL);\r
+ PollCount++;\r
+ Data = *((volatile uint32_t *) (uintn_t)(Addr));\r
+ }\r
+\r
+ Addr = I2CIoPortBaseAddress + I2C_REG_RAW_INTR_STAT;\r
+ Data = *((volatile uint32_t *) (uintn_t)(Addr));\r
+\r
+ // If no timeout or device error then read rx data.\r
+ if (PollCount == MAX_T_POLL_COUNT)\r
+ {\r
+ Status = -1;\r
+ }\r
+ else if ((Data & I2C_REG_RAW_INTR_STAT_RX_OVER) != 0)\r
+ {\r
+ Status = -1;\r
+ }\r
+ else\r
+ {\r
+ // Clear RX underflow before reading IC_DATA_CMD.\r
+ Addr = I2CIoPortBaseAddress + I2C_REG_CLR_RX_UNDER;\r
+ Data = *((volatile uint32_t *) (uintn_t)(Addr));\r
+\r
+ // Read data.\r
+ Addr = I2CIoPortBaseAddress + I2C_REG_DATA_CMD;\r
+ for (Index = 0; Index < ReadLength; Index++)\r
+ {\r
+ Data = *((volatile uint32_t *) (uintn_t)(Addr));\r
+ Data &= 0x000000FF;\r
+ *(Buffer+Index) = (uint8_t)Data;\r
+ }\r
+ Addr = I2CIoPortBaseAddress + I2C_REG_RAW_INTR_STAT;\r
+ Data = *((volatile uint32_t *) (uintn_t)(Addr));\r
+ Data &= I2C_REG_RAW_INTR_STAT_RX_UNDER;\r
+ if (Data != 0)\r
+ {\r
+ Status = -1;\r
+ }\r
+ else\r
+ {\r
+ Status = 0;\r
+ }\r
+ }\r
+ }\r
+\r
+ // Ensure I2C Controller disabled.\r
+ DisableI2CController ();\r
+\r
+ return Status;\r
+ }\r
+ /*-----------------------------------------------------------*/\r
+\r
+ static void I2CReadMultipleBytes(I2C_DEVICE_ADDRESS SlaveAddress, I2C_ADDR_MODE AddrMode,\r
+ uintn_t *WriteLength, uintn_t *ReadLength, void *Buffer )\r
+ {\r
+ uintn_t I2CAddress;\r
+ uint16_t SaveCmd;\r
+ uint32_t SaveBar0;\r
+\r
+ if (Buffer != NULL && WriteLength != NULL && ReadLength != NULL)\r
+ {\r
+ SaveCmd = 0;\r
+ SaveBar0 = 0;\r
+ I2cEntry (&SaveCmd, &SaveBar0);\r
+ if (InitializeInternal(AddrMode) == 0)\r
+ {\r
+ I2CAddress = SlaveAddress.I2CDeviceAddress;\r
+ ReadMultipleByte(I2CAddress, Buffer, (*WriteLength), (*ReadLength));\r
+ }\r
+ I2cExit (SaveCmd, SaveBar0);\r
+ }\r
+ }\r
+ /*-----------------------------------------------------------*/\r
+\r
+ /*-----------------------------------------------------------------------\r
+ * Pcal9555 chips used on Galileo Gen 2 boards (see FAB-H schematic)\r
+ *------------------------------------------------------------------------\r
+ */\r
+ static void Pcal9555SetPortRegBit(uint32_t Pcal9555SlaveAddr, uint32_t GpioNum, uint8_t RegBase, uint8_t LogicOne)\r
+ {\r
+ uintn_t ReadLength;\r
+ uintn_t WriteLength;\r
+ uint8_t Data[2];\r
+ uint8_t *RegValuePtr;\r
+ uint8_t GpioNumMask;\r
+ uint8_t SubAddr;\r
+ I2C_DEVICE_ADDRESS I2cDeviceAddr;\r
+ I2C_ADDR_MODE I2cAddrMode;\r
+\r
+ // Set I2C address and mode.\r
+ I2cDeviceAddr.I2CDeviceAddress = (uintn_t) Pcal9555SlaveAddr;\r
+ I2cAddrMode = EfiI2CSevenBitAddrMode;\r
+\r
+ // Set I2C subaddress and GPIO mask.\r
+ if (GpioNum < 8)\r
+ {\r
+ SubAddr = RegBase;\r
+ GpioNumMask = (uintn_t) (1 << GpioNum);\r
+ }\r
+ else\r
+ {\r
+ SubAddr = RegBase + 1;\r
+ GpioNumMask = (uintn_t) (1 << (GpioNum - 8));\r
+ }\r
+\r
+ // Output port value always at 2nd byte in Data variable.\r
+ RegValuePtr = &Data[1];\r
+\r
+ // On read entry - sub address at 2nd byte, on read exit - output\r
+ // port value in 2nd byte.\r
+ Data[1] = SubAddr;\r
+ WriteLength = 1;\r
+ ReadLength = 1;\r
+ I2CReadMultipleBytes(I2cDeviceAddr, I2cAddrMode, &WriteLength, &ReadLength, &Data[1]);\r
+\r
+ // Adjust output port bit using mask value.\r
+ if (LogicOne)\r
+ *RegValuePtr = *RegValuePtr | GpioNumMask;\r
+ else\r
+ *RegValuePtr = *RegValuePtr & ~(GpioNumMask);\r
+\r
+ // Update register. Sub address at 1st byte, value at 2nd byte.\r
+ WriteLength = 2;\r
+ Data[0] = SubAddr;\r
+ I2CWriteMultipleBytes(I2cDeviceAddr,I2cAddrMode, &WriteLength, Data);\r
+ }\r
+ /*-----------------------------------------------------------*/\r
+\r
+ static void PlatformPcal9555GpioPullup(uint32_t Pcal9555SlaveAddr, uint32_t GpioNum, uint32_t Enable)\r
+ {\r
+ Pcal9555SetPortRegBit(Pcal9555SlaveAddr, GpioNum, PCAL9555_REG_PULL_EN_PORT0, Enable );\r
+ }\r
+ /*-----------------------------------------------------------*/\r
+\r
+ static void PlatformPcal9555GpioSetDir(uint32_t Pcal9555SlaveAddr, uint32_t GpioNum, uint32_t CfgAsInput)\r
+ {\r
+ Pcal9555SetPortRegBit(Pcal9555SlaveAddr, GpioNum, PCAL9555_REG_CFG_PORT0, CfgAsInput);\r
+ }\r
+ /*-----------------------------------------------------------*/\r
+\r
+ static void PlatformPcal9555GpioSetLevel(uint32_t Pcal9555SlaveAddr, uint32_t GpioNum, uint32_t HighLevel )\r
+ {\r
+ Pcal9555SetPortRegBit(Pcal9555SlaveAddr, GpioNum, PCAL9555_REG_OUT_PORT0, HighLevel );\r
+ }\r
+ /*-----------------------------------------------------------*/\r
+\r
+ /*-----------------------------------------------------------------------\r
+ * GPIO pin routing function\r
+ *------------------------------------------------------------------------\r
+ */\r
+ static void vGalileoRouteLEDPins(void)\r
+ {\r
+ // For GpioNums below values 0 to 7 are for Port0 IE. P0-0 - P0-7 and\r
+ // values 8 to 15 are for Port1 IE. P1-0 - P1-7.\r
+ // Disable Pull-ups / pull downs on EXP0 pin for LVL_B_PU7 signal.\r
+ PlatformPcal9555GpioPullup (\r
+ GALILEO_GEN2_IOEXP0_7BIT_SLAVE_ADDR, // IO Expander 0.\r
+ 15, // P1-7.\r
+ FALSE\r
+ );\r
+\r
+ // Make LVL_B_OE7_N an output pin.\r
+ PlatformPcal9555GpioSetDir (\r
+ GALILEO_GEN2_IOEXP0_7BIT_SLAVE_ADDR, // IO Expander 0.\r
+ 14, // P1-6.\r
+ FALSE);\r
+\r
+ // Set level of LVL_B_OE7_N to low.\r
+ PlatformPcal9555GpioSetLevel (\r
+ GALILEO_GEN2_IOEXP0_7BIT_SLAVE_ADDR,\r
+ 14,\r
+ FALSE);\r
+\r
+ // Make MUX8_SEL an output pin.\r
+ PlatformPcal9555GpioSetDir (\r
+ GALILEO_GEN2_IOEXP1_7BIT_SLAVE_ADDR, // IO Expander 1.\r
+ 14, // P1-6.\r
+ FALSE);\r
+\r
+ // Set level of MUX8_SEL to low to route GPIO_SUS<5> to LED.\r
+ PlatformPcal9555GpioSetLevel (\r
+ GALILEO_GEN2_IOEXP1_7BIT_SLAVE_ADDR, // IO Expander 1.\r
+ 14, // P1-6.\r
+ FALSE);\r
+ }\r
+ /*-----------------------------------------------------------*/\r
--- /dev/null
+/*--------------------------------------------------------------------\r
+ Copyright(c) 2015 Intel Corporation. All rights reserved.\r
+\r
+ Redistribution and use in source and binary forms, with or without\r
+ modification, are permitted provided that the following conditions\r
+ are met:\r
+\r
+ * Redistributions of source code must retain the above copyright\r
+ notice, this list of conditions and the following disclaimer.\r
+ * Redistributions in binary form must reproduce the above copyright\r
+ notice, this list of conditions and the following disclaimer in\r
+ the documentation and/or other materials provided with the\r
+ distribution.\r
+ * Neither the name of Intel Corporation nor the names of its\r
+ contributors may be used to endorse or promote products derived\r
+ from this software without specific prior written permission.\r
+\r
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
+ "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
+ LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
+ A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\r
+ OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\r
+ SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\r
+ DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\r
+ THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ --------------------------------------------------------------------*/\r
+\r
+#ifndef __GPIO_I2C_H__\r
+#define __GPIO_I2C_H__\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+//---------------------------------------------------------------------\r
+// Any required includes\r
+//---------------------------------------------------------------------\r
+#include "galileo_gen_defs.h"\r
+\r
+//---------------------------------------------------------------------\r
+// PCI Configuration Map Register Offsets\r
+//---------------------------------------------------------------------\r
+#define PCI_REG_VID 0x00 // Vendor ID Register\r
+#define PCI_REG_DID 0x02 // Device ID Register\r
+#define PCI_REG_PCICMD 0x04 // PCI Command Register\r
+#define PCI_REG_PCISTS 0x06 // PCI Status Register\r
+#define PCI_REG_RID 0x08 // PCI Revision ID Register\r
+#define PCI_REG_PI 0x09 // Programming Interface\r
+#define PCI_REG_SCC 0x0a // Sub Class Code Register\r
+#define PCI_REG_BCC 0x0b // Base Class Code Register\r
+#define PCI_REG_PMLT 0x0d // Primary Master Latency Timer\r
+#define PCI_REG_HDR 0x0e // Header Type Register\r
+#define PCI_REG_PBUS 0x18 // Primary Bus Number Register\r
+#define PCI_REG_SBUS 0x19 // Secondary Bus Number Register\r
+#define PCI_REG_SUBUS 0x1a // Subordinate Bus Number Register\r
+#define PCI_REG_SMLT 0x1b // Secondary Master Latency Timer\r
+#define PCI_REG_IOBASE 0x1c // I/O base Register\r
+#define PCI_REG_IOLIMIT 0x1d // I/O Limit Register\r
+#define PCI_REG_SECSTATUS 0x1e // Secondary Status Register\r
+#define PCI_REG_MEMBASE 0x20 // Memory Base Register\r
+#define PCI_REG_MEMLIMIT 0x22 // Memory Limit Register\r
+#define PCI_REG_PRE_MEMBASE 0x24 // Prefetchable memory Base register\r
+#define PCI_REG_PRE_MEMLIMIT 0x26 // Prefetchable memory Limit register\r
+#define PCI_REG_SVID0 0x2c // Subsystem Vendor ID low byte\r
+#define PCI_REG_SVID1 0x2d // Subsystem Vendor ID high byte\r
+#define PCI_REG_SID0 0x2e // Subsystem ID low byte\r
+#define PCI_REG_SID1 0x2f // Subsystem ID high byte\r
+#define PCI_REG_IOBASE_U 0x30 // I/O base Upper Register\r
+#define PCI_REG_IOLIMIT_U 0x32 // I/O Limit Upper Register\r
+#define PCI_REG_INTLINE 0x3c // Interrupt Line Register\r
+#define PCI_REG_BRIDGE_CNTL 0x3e // Bridge Control Register\r
+\r
+#define IO_PCI_ADDRESS(bus, dev, fn, reg) \\r
+(0x80000000 | (bus << 16) | (dev << 11) | (fn << 8) | (reg & ~3))\r
+\r
+//---------------------------------------------------------------------\r
+// PCI Read/Write IO Data\r
+//---------------------------------------------------------------------\r
+#define IO_PCI_ADDRESS_PORT 0xcf8\r
+#define IO_PCI_DATA_PORT 0xcfc\r
+\r
+//---------------------------------------------------------------------\r
+// GPIO structures\r
+//---------------------------------------------------------------------\r
+\r
+struct __attribute__ ((__packed__)) BOARD_GPIO_CONTROLLER_CONFIG\r
+{\r
+uint32_t PortADR; ///< Value for IOH REG GPIO_SWPORTA_DR.\r
+uint32_t PortADir; ///< Value for IOH REG GPIO_SWPORTA_DDR.\r
+uint32_t IntEn; ///< Value for IOH REG GPIO_INTEN.\r
+uint32_t IntMask; ///< Value for IOH REG GPIO_INTMASK.\r
+uint32_t IntType; ///< Value for IOH REG GPIO_INTTYPE_LEVEL.\r
+uint32_t IntPolarity; ///< Value for IOH REG GPIO_INT_POLARITY.\r
+uint32_t Debounce; ///< Value for IOH REG GPIO_DEBOUNCE.\r
+uint32_t LsSync; ///< Value for IOH REG GPIO_LS_SYNC.\r
+};\r
+\r
+struct __attribute__ ((__packed__)) BOARD_LEGACY_GPIO_CONFIG\r
+{\r
+uint32_t CoreWellEnable; ///< Value for QNC NC Reg R_QNC_GPIO_CGEN_CORE_WELL.\r
+uint32_t CoreWellIoSelect; ///< Value for QNC NC Reg R_QNC_GPIO_CGIO_CORE_WELL.\r
+uint32_t CoreWellLvlForInputOrOutput; ///< Value for QNC NC Reg R_QNC_GPIO_CGLVL_CORE_WELL.\r
+uint32_t CoreWellTriggerPositiveEdge; ///< Value for QNC NC Reg R_QNC_GPIO_CGTPE_CORE_WELL.\r
+uint32_t CoreWellTriggerNegativeEdge; ///< Value for QNC NC Reg R_QNC_GPIO_CGTNE_CORE_WELL.\r
+uint32_t CoreWellGPEEnable; ///< Value for QNC NC Reg R_QNC_GPIO_CGGPE_CORE_WELL.\r
+uint32_t CoreWellSMIEnable; ///< Value for QNC NC Reg R_QNC_GPIO_CGSMI_CORE_WELL.\r
+uint32_t CoreWellTriggerStatus; ///< Value for QNC NC Reg R_QNC_GPIO_CGTS_CORE_WELL.\r
+uint32_t CoreWellNMIEnable; ///< Value for QNC NC Reg R_QNC_GPIO_CGNMIEN_CORE_WELL.\r
+uint32_t ResumeWellEnable; ///< Value for QNC NC Reg R_QNC_GPIO_RGEN_RESUME_WELL.\r
+uint32_t ResumeWellIoSelect; ///< Value for QNC NC Reg R_QNC_GPIO_RGIO_RESUME_WELL.\r
+uint32_t ResumeWellLvlForInputOrOutput;///< Value for QNC NC Reg R_QNC_GPIO_RGLVL_RESUME_WELL.\r
+uint32_t ResumeWellTriggerPositiveEdge;///< Value for QNC NC Reg R_QNC_GPIO_RGTPE_RESUME_WELL.\r
+uint32_t ResumeWellTriggerNegativeEdge;///< Value for QNC NC Reg R_QNC_GPIO_RGTNE_RESUME_WELL.\r
+uint32_t ResumeWellGPEEnable; ///< Value for QNC NC Reg R_QNC_GPIO_RGGPE_RESUME_WELL.\r
+uint32_t ResumeWellSMIEnable; ///< Value for QNC NC Reg R_QNC_GPIO_RGSMI_RESUME_WELL.\r
+uint32_t ResumeWellTriggerStatus; ///< Value for QNC NC Reg R_QNC_GPIO_RGTS_RESUME_WELL.\r
+uint32_t ResumeWellNMIEnable; ///< Value for QNC NC Reg R_QNC_GPIO_RGNMIEN_RESUME_WELL.\r
+} ;\r
+\r
+//---------------------------------------------------------------------\r
+// GPIO definitions\r
+//---------------------------------------------------------------------\r
+#define GALILEO_GEN2_GPIO_CONTROLLER_INITIALIZER {0x05, 0x05, 0, 0, 0, 0, 0, 0}\r
+#define GALILEO_GEN2_LEGACY_GPIO_INITIALIZER {0x03, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, \\r
+ 0x03, 0x00, 0x3f, 0x1c, 0x02, 0x00, 0x00, \\r
+ 0x00, 0x00, 0x3f, 0x00}\r
+\r
+#define PLATFORM_GPIO_CONTROLLER_CONFIG_DEFINITION \\r
+/* EFI_PLATFORM_TYPE - Galileo Gen 2 */ \\r
+GALILEO_GEN2_GPIO_CONTROLLER_INITIALIZER ,\\r
+\r
+#define PLATFORM_LEGACY_GPIO_CONFIG_DEFINITION \\r
+/* EFI_PLATFORM_TYPE - Galileo Gen 2 */ \\r
+GALILEO_GEN2_LEGACY_GPIO_INITIALIZER , \\r
+\r
+#define IOH_I2C_GPIO_BUS_NUMBER 0x00\r
+#define IOH_I2C_GPIO_DEVICE_NUMBER 0x15\r
+#define IOH_I2C_GPIO_FUNCTION_NUMBER 0x02\r
+\r
+#define INTEL_VENDOR_ID 0x8086\r
+#define V_IOH_I2C_GPIO_VENDOR_ID INTEL_VENDOR_ID\r
+#define V_IOH_I2C_GPIO_DEVICE_ID 0x0934\r
+\r
+#define R_IOH_I2C_MEMBAR 0x10\r
+#define R_IOH_GPIO_MEMBAR 0x14\r
+\r
+#define GPIO_SWPORTA_DR 0x00\r
+#define GPIO_SWPORTA_DDR 0x04\r
+#define GPIO_SWPORTB_DR 0x0C\r
+#define GPIO_SWPORTB_DDR 0x10\r
+#define GPIO_SWPORTC_DR 0x18\r
+#define GPIO_SWPORTC_DDR 0x1C\r
+#define GPIO_SWPORTD_DR 0x24\r
+#define GPIO_SWPORTD_DDR 0x28\r
+#define GPIO_INTEN 0x30\r
+#define GPIO_INTMASK 0x34\r
+#define GPIO_INTTYPE_LEVEL 0x38\r
+#define GPIO_INT_POLARITY 0x3C\r
+#define GPIO_INTSTATUS 0x40\r
+#define GPIO_RAW_INTSTATUS 0x44\r
+#define GPIO_DEBOUNCE 0x48\r
+#define GPIO_PORTA_EOI 0x4C\r
+#define GPIO_EXT_PORTA 0x50\r
+#define GPIO_EXT_PORTB 0x54\r
+#define GPIO_EXT_PORTC 0x58\r
+#define GPIO_EXT_PORTD 0x5C\r
+#define GPIO_LS_SYNC 0x60\r
+#define GPIO_CONFIG_REG2 0x70\r
+#define GPIO_CONFIG_REG1 0x74\r
+\r
+//---------------------------------------------------------------------\r
+// GPIO defines for cypress chip\r
+//---------------------------------------------------------------------\r
+#define PCAL9555_REG_OUT_PORT0 0x02\r
+#define PCAL9555_REG_OUT_PORT1 0x03\r
+#define PCAL9555_REG_CFG_PORT0 0x06\r
+#define PCAL9555_REG_CFG_PORT1 0x07\r
+#define PCAL9555_REG_PULL_EN_PORT0 0x46\r
+#define PCAL9555_REG_PULL_EN_PORT1 0x47\r
+\r
+//---------------------------------------------------------------------\r
+// Three IO Expanders at fixed addresses on Galileo Gen2.\r
+//---------------------------------------------------------------------\r
+#define GALILEO_GEN2_IOEXP0_7BIT_SLAVE_ADDR 0x25\r
+#define GALILEO_GEN2_IOEXP1_7BIT_SLAVE_ADDR 0x26\r
+#define GALILEO_GEN2_IOEXP2_7BIT_SLAVE_ADDR 0x27\r
+\r
+//---------------------------------------------------------------------\r
+// Legacy GPIO defines\r
+//---------------------------------------------------------------------\r
+#define LEGACY_GPIO_BUS_NUMBER 0\r
+#define LEGACY_GPIO_DEVICE_NUMBER 31\r
+#define LEGACY_GPIO_FUNCTION_NUMBER 0\r
+\r
+#define R_QNC_LPC_GBA_BASE 0x44\r
+#define B_QNC_LPC_GPA_BASE_MASK 0x0000FFC0\r
+\r
+//---------------------------------------------------------------------\r
+// I2C structures and enums\r
+//---------------------------------------------------------------------\r
+ typedef struct\r
+ {\r
+ /// The I2C hardware address to which the I2C device is preassigned or allocated.\r
+ uintn_t I2CDeviceAddress : 10;\r
+ } I2C_DEVICE_ADDRESS;\r
+\r
+ typedef enum _I2C_ADDR_MODE\r
+ {\r
+ EfiI2CSevenBitAddrMode,\r
+ EfiI2CTenBitAddrMode,\r
+ } I2C_ADDR_MODE;\r
+\r
+//---------------------------------------------------------------------\r
+// I2C definitions\r
+//---------------------------------------------------------------------\r
+#define GALILEO_GEN2_FLASH_UPDATE_LED_RESUMEWELL_GPIO 5\r
+#define R_QNC_GPIO_CGEN_CORE_WELL 0x00\r
+#define R_QNC_GPIO_CGIO_CORE_WELL 0x04\r
+#define R_QNC_GPIO_CGLVL_CORE_WELL 0x08\r
+#define R_QNC_GPIO_CGTPE_CORE_WELL 0x0C // Core well GPIO Trigger Positive Edge Enable\r
+#define R_QNC_GPIO_CGTNE_CORE_WELL 0x10 // Core well GPIO Trigger Negative Edge Enable\r
+#define R_QNC_GPIO_CGGPE_CORE_WELL 0x14 // Core well GPIO GPE Enable\r
+#define R_QNC_GPIO_CGSMI_CORE_WELL 0x18 // Core well GPIO SMI Enable\r
+#define R_QNC_GPIO_CGTS_CORE_WELL 0x1C // Core well GPIO Trigger Status\r
+#define R_QNC_GPIO_RGEN_RESUME_WELL 0x20\r
+#define R_QNC_GPIO_RGIO_RESUME_WELL 0x24\r
+#define R_QNC_GPIO_RGLVL_RESUME_WELL 0x28\r
+#define R_QNC_GPIO_RGTPE_RESUME_WELL 0x2C // Resume well GPIO Trigger Positive Edge Enable\r
+#define R_QNC_GPIO_RGTNE_RESUME_WELL 0x30 // Resume well GPIO Trigger Negative Edge Enable\r
+#define R_QNC_GPIO_RGGPE_RESUME_WELL 0x34 // Resume well GPIO GPE Enable\r
+#define R_QNC_GPIO_RGSMI_RESUME_WELL 0x38 // Resume well GPIO SMI Enable\r
+#define R_QNC_GPIO_RGTS_RESUME_WELL 0x3C // Resume well GPIO Trigger Status\r
+#define R_QNC_GPIO_CNMIEN_CORE_WELL 0x40 // Core well GPIO NMI Enable\r
+#define R_QNC_GPIO_RNMIEN_RESUME_WELL 0x44 // Resume well GPIO NMI Enable\r
+\r
+#define B_IOH_I2C_GPIO_MEMBAR_ADDR_MASK 0xFFFFF000 // [31:12].\r
+#define I2C_REG_CLR_START_DET 0x64 // Clear START DET Interrupt Register\r
+#define I2C_REG_CLR_STOP_DET 0x60 // Clear STOP DET Interrupt Register\r
+#define B_I2C_REG_CLR_START_DET (BIT0) // Clear START DET Interrupt Register\r
+#define B_I2C_REG_CLR_STOP_DET (BIT0) // Clear STOP DET Interrupt Register\r
+#define B_I2C_REG_CON_10BITADD_MASTER (BIT4) // 7-bit addressing (0) or 10-bit addressing (1)\r
+#define B_I2C_REG_CON_SPEED (BIT2+BIT1) // standard mode (01) or fast mode (10)\r
+#define I2C_REG_CON 0x00 // Control Register\r
+#define I2C_REG_ENABLE 0x6C // Enable Register\r
+#define B_I2C_REG_ENABLE (BIT0) // Enable (1) or disable (0) I2C Controller\r
+#define I2C_REG_ENABLE_STATUS 0x9C // Enable Status Register\r
+#define I2C_REG_CLR_INT 0x40 // Clear Combined and Individual Interrupt Register\r
+#define MAX_T_POLL_COUNT 100\r
+#define TI2C_POLL 25 // microseconds\r
+#define I2C_REG_CLR_RX_OVER 0x48 // Clear RX Over Interrupt Register\r
+#define I2C_REG_CLR_TX_OVER 0x4C // Clear TX Over Interrupt Register\r
+#define I2C_REG_CLR_TX_ABRT 0x54 // Clear TX ABRT Interrupt Register\r
+#define I2C_FIFO_SIZE 16\r
+#define I2C_REG_TAR 0x04 // Master Target Address Register\r
+#define B_I2C_REG_TAR (BIT9+BIT8+BIT7+BIT6+BIT5+BIT4+BIT3+BIT2+BIT1+BIT0) // Master Target Address bits\r
+#define I2C_REG_DATA_CMD 0x10 // Data Buffer and Command Register\r
+#define B_I2C_REG_DATA_CMD_RW (BIT8) // Data Buffer and Command Register Read/Write bit\r
+#define I2C_REG_RXFLR 0x78 // Receive FIFO Level Register\r
+#define B_I2C_REG_DATA_CMD_STOP (BIT9) // Data Buffer and Command Register STOP bit\r
+#define I2C_REG_RAW_INTR_STAT 0x34 // Raw Interrupt Status Register\r
+#define I2C_REG_RAW_INTR_STAT_RX_OVER (BIT1) // Raw Interrupt Status Register RX Overflow signal status.\r
+#define I2C_REG_RAW_INTR_STAT_RX_UNDER (BIT0) // Raw Interrupt Status Register RX Underflow signal status.\r
+#define I2C_REG_CLR_RX_UNDER 0x44 // Clear RX Under Interrupt Register\r
+#define MAX_STOP_DET_POLL_COUNT ((1000 * 1000) / TI2C_POLL) // Extreme for expected Stop detect.\r
+#define I2C_REG_RAW_INTR_STAT_TX_ABRT (BIT6) // Raw Interrupt Status Register TX Abort status.\r
+#define I2C_REG_RAW_INTR_STAT_TX_OVER (BIT3) // Raw Interrupt Status Register TX Overflow signal status.\r
+#define I2C_REG_RAW_INTR_STAT_STOP_DET (BIT9) // Raw Interrupt Status Register STOP_DET signal status.\r
+\r
+//---------------------------------------------------------------------\r
+// GPIO Prototypes\r
+//---------------------------------------------------------------------\r
+#define GPIO_OUTPUT (0)\r
+#define GPIO_INPUT (1)\r
+#define LOW (0)\r
+#define HIGH (1)\r
+#define GPIO_NUMBER (7UL)\r
+\r
+void vMicroSecondDelay(uint32_t DelayTime);\r
+void vMilliSecondDelay(uint32_t DelayTime);\r
+void vGalileoInitializeLegacyGPIO(void);\r
+void vGalileoInitializeGpioController(void);\r
+void vGalileoLegacyGPIOInitializationForLED(void);\r
+void vGalileoSetGPIOBitDirection(uint32_t GPIONumber, uint32_t Direction);\r
+void vGalileoSetGPIOBitLevel(uint32_t GPIONumber, uint32_t Level);\r
+void vGalileoBlinkLEDUsingLegacyGPIO(uint32_t Level);\r
+\r
+#ifdef __cplusplus\r
+ } /* extern C */\r
+#endif\r
+\r
+#endif /* __GPIO_I2C_H__ */\r
+\r
--- /dev/null
+/*--------------------------------------------------------------------\r
+ Copyright(c) 2015 Intel Corporation. All rights reserved.\r
+\r
+ Redistribution and use in source and binary forms, with or without\r
+ modification, are permitted provided that the following conditions\r
+ are met:\r
+\r
+ * Redistributions of source code must retain the above copyright\r
+ notice, this list of conditions and the following disclaimer.\r
+ * Redistributions in binary form must reproduce the above copyright\r
+ notice, this list of conditions and the following disclaimer in\r
+ the documentation and/or other materials provided with the\r
+ distribution.\r
+ * Neither the name of Intel Corporation nor the names of its\r
+ contributors may be used to endorse or promote products derived\r
+ from this software without specific prior written permission.\r
+\r
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
+ "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
+ LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
+ A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\r
+ OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\r
+ SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\r
+ DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\r
+ THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ --------------------------------------------------------------------*/\r
+\r
+/*-----------------------------------------------------------------------\r
+ * Any required includes\r
+ *------------------------------------------------------------------------\r
+ */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "portmacro.h"\r
+#include "galileo_support.h"\r
+\r
+/*-----------------------------------------------------------------------\r
+ * Function prototypes\r
+ *------------------------------------------------------------------------\r
+ */\r
+#if( hpetUSE_HPET_TIMER_NUMBER_0 == 1 )\r
+ static void vHPETIRQHandler0(void);\r
+#endif\r
+#if( hpetUSE_HPET_TIMER_NUMBER_1 == 1 )\r
+ void vHPETIRQHandler1(void);\r
+#endif\r
+#if( hpetUSE_HPET_TIMER_NUMBER_2 == 1 )\r
+ static void vHPETIRQHandler2(void);\r
+#endif\r
+\r
+/*-----------------------------------------------------------------------\r
+ * Always inline HPET ISR related routines (even with no optimization),\r
+ * This is done for speed reasons to keep the ISR as fast as possible.\r
+ *------------------------------------------------------------------------\r
+ */\r
+#if (hpetHPET_TIMER_IN_USE)\r
+ static inline void vSetTVS( uint32_t ) __attribute__((always_inline));\r
+ static inline void vSetHPETComparator( uint32_t, uint64_t ) __attribute__((always_inline));\r
+ static inline uint64_t ullReadHPETCounters( void ) __attribute__((always_inline));\r
+ static inline void vHPET_ISR (uint32_t) __attribute__((always_inline));\r
+#endif\r
+\r
+/*-----------------------------------------------------------------------\r
+ * Global variables\r
+ *------------------------------------------------------------------------\r
+ */\r
+volatile uint32_t hpet_general_status;\r
+volatile uint32_t ulHPETTimerNumber [3] = {0, 1, 2};\r
+volatile uint32_t ulHPETTotalInterrupts [3] = {0, 0, 0};\r
+volatile uint32_t ulHPETElapsedSeconds [3] = {0, 0, 0};\r
+volatile uint32_t ulHPETInterruptFrequency [3] = {0, 0, 0};\r
+volatile uint32_t ulHPETTicksToInterrupt [3] = {0, 0, 0};\r
+struct hpet_info PrintInfo[3] =\r
+{\r
+ {0, 0, 0, 0, 0, 0, 0},\r
+ {1, 0, 0, 0, 0, 0, 0},\r
+ {2, 0, 0, 0, 0, 0, 0},\r
+};\r
+\r
+/*-----------------------------------------------------------------------\r
+ * Static variables\r
+ *------------------------------------------------------------------------\r
+ */\r
+#if (hpetHPET_TIMER_IN_USE)\r
+ static uint32_t hpet_general_id;\r
+ static uint32_t hpet_counter_tick_period;\r
+#endif\r
+\r
+/*-----------------------------------------------------------------------\r
+ * General HPET functions\r
+ *------------------------------------------------------------------------\r
+ */\r
+#if (hpetHPET_TIMER_IN_USE)\r
+static void vClearHPETCounters( void )\r
+{\r
+ hpetHPET_MAIN_CTR_LOW = 0UL;\r
+ hpetHPET_MAIN_CTR_HIGH = 0UL;\r
+}\r
+#endif\r
+/*-----------------------------------------------------------*/\r
+\r
+#if (hpetHPET_TIMER_IN_USE)\r
+void vClearHPETElapsedSeconds( void )\r
+{\r
+ #if( hpetUSE_HPET_TIMER_NUMBER_0 == 1 )\r
+ {\r
+ ulHPETElapsedSeconds[0] = 0UL;\r
+ ulHPETTotalInterrupts [0] = 0UL;\r
+ }\r
+ #endif\r
+ #if( hpetUSE_HPET_TIMER_NUMBER_1 == 1 )\r
+ {\r
+ ulHPETElapsedSeconds[1] = 0UL;\r
+ ulHPETTotalInterrupts [1] = 0UL;\r
+ }\r
+ #endif\r
+ #if( hpetUSE_HPET_TIMER_NUMBER_2 == 1 )\r
+ {\r
+ ulHPETElapsedSeconds[2] = 0UL;\r
+ ulHPETTotalInterrupts [2] = 0UL;\r
+ }\r
+ #endif\r
+}\r
+#endif\r
+/*-----------------------------------------------------------*/\r
+\r
+#if (hpetHPET_TIMER_IN_USE)\r
+static inline void vSetTVS( uint32_t TimerNumber )\r
+{\r
+ volatile uint32_t hpet_cfg = 0UL;\r
+ const uint32_t uiTVS = (1UL << 6UL);\r
+\r
+ #if( hpetUSE_HPET_TIMER_NUMBER_0 == 1 )\r
+ {\r
+ if (TimerNumber == 0)\r
+ {\r
+ hpet_cfg = hpetHPET_TMR0_CONFIG_LOW | uiTVS;\r
+ hpetHPET_TMR0_CONFIG_LOW = hpet_cfg;\r
+ }\r
+ }\r
+ #endif\r
+ #if( hpetUSE_HPET_TIMER_NUMBER_1 == 1 )\r
+ {\r
+ if (TimerNumber == 1)\r
+ {\r
+ hpet_cfg = hpetHPET_TMR1_CONFIG_LOW | uiTVS;\r
+ hpetHPET_TMR1_CONFIG_LOW = hpet_cfg;\r
+ }\r
+ }\r
+ #endif\r
+ #if( hpetUSE_HPET_TIMER_NUMBER_2 == 1 )\r
+ {\r
+ if (TimerNumber == 2)\r
+ {\r
+ hpet_cfg = hpetHPET_TMR2_CONFIG_LOW | uiTVS;\r
+ hpetHPET_TMR2_CONFIG_LOW = hpet_cfg;\r
+ }\r
+ }\r
+ #endif\r
+}\r
+#endif\r
+/*-----------------------------------------------------------*/\r
+\r
+#if (hpetHPET_TIMER_IN_USE)\r
+static inline void vSetHPETComparator( uint32_t TimerNumber, uint64_t Value )\r
+{\r
+ #if( hpetUSE_HPET_TIMER_NUMBER_0 == 1 )\r
+ {\r
+ if (TimerNumber == 0)\r
+ {\r
+ vSetTVS(TimerNumber);\r
+ hpetHPET_TMR0_COMPARATOR_LOW = (uint32_t)(Value & 0xFFFFFFFFULL);\r
+ vSetTVS(TimerNumber);\r
+ hpetHPET_TMR0_COMPARATOR_HIGH = (uint32_t)((Value >> 32UL) & 0xFFFFFFFFULL);\r
+ }\r
+ }\r
+ #endif\r
+ #if( hpetUSE_HPET_TIMER_NUMBER_1 == 1 )\r
+ {\r
+ if (TimerNumber == 1)\r
+ {\r
+ vSetTVS(TimerNumber);\r
+ hpetHPET_TMR1_COMPARATOR_LOW = (uint32_t)(Value & 0xFFFFFFFFULL);\r
+ vSetTVS(TimerNumber);\r
+ hpetHPET_TMR1_COMPARATOR_HIGH = (uint32_t)((Value >> 32UL) & 0xFFFFFFFFULL);\r
+ }\r
+ }\r
+ #endif\r
+ #if( hpetUSE_HPET_TIMER_NUMBER_2 == 1 )\r
+ {\r
+ if (TimerNumber == 2)\r
+ {\r
+ vSetTVS(TimerNumber);\r
+ hpetHPET_TMR2_COMPARATOR_LOW = (uint32_t)(Value & 0xFFFFFFFFULL);\r
+ vSetTVS(TimerNumber);\r
+ hpetHPET_TMR2_COMPARATOR_HIGH = (uint32_t)((Value >> 32UL) & 0xFFFFFFFFULL);\r
+ }\r
+ }\r
+ #endif\r
+}\r
+#endif\r
+/*-----------------------------------------------------------*/\r
+\r
+#if (hpetHPET_TIMER_IN_USE)\r
+static inline uint64_t ullReadHPETCounters( void )\r
+{\r
+ volatile uint64_t Counters = (uint64_t)\r
+ (((uint64_t)hpetHPET_MAIN_CTR_HIGH << 32UL) |\r
+ (uint64_t)hpetHPET_MAIN_CTR_LOW);\r
+ return Counters;\r
+}\r
+#endif\r
+/*-----------------------------------------------------------*/\r
+\r
+#if (hpetHPET_TIMER_IN_USE)\r
+static void vStopHPETTimer( uint32_t ClearCounters )\r
+{\r
+ uint32_t hpet_cfg = 0UL;\r
+\r
+ /* Clear configuration enable bit */\r
+ hpet_cfg = hpetHPET_GENERAL_CONFIGURATION;\r
+ hpet_cfg &= ~hpetHPET_CFG_ENABLE;\r
+ hpetHPET_GENERAL_CONFIGURATION = hpet_cfg;\r
+\r
+ /* Clear counters */\r
+ if (ClearCounters)\r
+ vClearHPETCounters();\r
+}\r
+#endif\r
+/*-----------------------------------------------------------*/\r
+\r
+#if (hpetHPET_TIMER_IN_USE)\r
+static void vStartHPETTimer( void )\r
+{\r
+ uint32_t hpet_cfg = 0UL;\r
+ uint8_t LegacyMode = TRUE; // See table in doc # 329676 page 867\r
+\r
+ hpet_general_status = hpetHPET_GENERAL_STATUS;\r
+\r
+ if (hpet_general_status != 0x0UL)\r
+ hpetHPET_GENERAL_STATUS = hpet_general_status;\r
+\r
+ hpet_cfg = hpetHPET_GENERAL_CONFIGURATION;\r
+ hpet_cfg |= hpetHPET_CFG_ENABLE;\r
+\r
+ if(LegacyMode != FALSE)\r
+ hpet_cfg |= hpetHPET_CFG_LEGACY;\r
+ else\r
+ hpet_cfg &= ~hpetHPET_CFG_LEGACY;\r
+\r
+ hpetHPET_GENERAL_CONFIGURATION = hpet_cfg;\r
+}\r
+#endif\r
+/*-----------------------------------------------------------*/\r
+\r
+#if (hpetHPET_TIMER_IN_USE)\r
+static void vConfigureHPETTimer( uint32_t TimerNumber, uint32_t PeriodicMode )\r
+{\r
+ uint32_t hpet_cfg = 0UL; // Configuration data\r
+ uint8_t IRQNumber = 0; // Hardware ISR number\r
+ uint8_t Triggering = 0; // Level or Edge sensitive\r
+\r
+ #if( hpetUSE_HPET_TIMER_NUMBER_0 == 1 )\r
+ {\r
+ if (TimerNumber == 0)\r
+ {\r
+ IRQNumber = TIMER0_IRQ;\r
+ Triggering = TIMER0_TRIGGERING;\r
+ hpet_cfg = hpetHPET_TMR0_CONFIG_LOW;\r
+ }\r
+ }\r
+ #endif\r
+ #if( hpetUSE_HPET_TIMER_NUMBER_1 == 1 )\r
+ {\r
+ if (TimerNumber == 1)\r
+ {\r
+ IRQNumber = TIMER1_IRQ;\r
+ Triggering = TIMER1_TRIGGERING;\r
+ hpet_cfg = hpetHPET_TMR1_CONFIG_LOW;\r
+ }\r
+ }\r
+ #endif\r
+ #if( hpetUSE_HPET_TIMER_NUMBER_2 == 1 )\r
+ {\r
+ if (TimerNumber == 2)\r
+ {\r
+ IRQNumber = TIMER2_IRQ;\r
+ Triggering = TIMER2_TRIGGERING;\r
+ hpet_cfg = hpetHPET_TMR2_CONFIG_LOW;\r
+ }\r
+ }\r
+ #endif\r
+\r
+ /* Modify configuration */\r
+ if (PeriodicMode != FALSE)\r
+ {\r
+ hpet_cfg |= hpetHPET_TN_ENABLE | hpetHPET_TN_PERIODIC | hpetHPET_TN_SETVAL |\r
+ hpetHPET_TN_32BIT | ((IRQNumber & 0x1F) << 9UL);\r
+ }\r
+ else\r
+ {\r
+ hpet_cfg |= hpetHPET_TN_ENABLE | hpetHPET_TN_SETVAL |\r
+ hpetHPET_TN_32BIT | ((IRQNumber & 0x1F) << 9UL);\r
+ }\r
+\r
+ /* Setup triggering bit */\r
+ if (Triggering != hpetHPET_INT_EDGE)\r
+ hpet_cfg |= (1UL << 1UL);\r
+ else\r
+ hpet_cfg &= ~(1UL << 1UL);\r
+\r
+ /* write-out configuration */\r
+ #if( hpetUSE_HPET_TIMER_NUMBER_0 == 1 )\r
+ if (TimerNumber == 0)\r
+ {\r
+ hpetHPET_TMR0_CONFIG_LOW = hpet_cfg;\r
+ }\r
+ #endif\r
+ #if( hpetUSE_HPET_TIMER_NUMBER_1 == 1 )\r
+ if (TimerNumber == 1)\r
+ {\r
+ hpetHPET_TMR1_CONFIG_LOW = hpet_cfg;\r
+ }\r
+ #endif\r
+ #if( hpetUSE_HPET_TIMER_NUMBER_2 == 1 )\r
+ if (TimerNumber == 2)\r
+ {\r
+ hpetHPET_TMR2_CONFIG_LOW = hpet_cfg;\r
+ }\r
+ #endif\r
+}\r
+#endif\r
+/*-----------------------------------------------------------*/\r
+\r
+#if (hpetHPET_TIMER_IN_USE)\r
+static void vGetHPETCapabilitiesAndStatus( void )\r
+{\r
+ /* Get HPET capabilities and ID */\r
+ hpet_general_id = hpetHPET_GENERAL_ID;\r
+\r
+ /* Invalid vendor ID - Should be Intel (0x8086") */\r
+ if ((hpet_general_id >> 16) != 0x8086UL)\r
+ {\r
+ configASSERT( 0 );\r
+ }\r
+\r
+ /* Get number of ns/tick - default is 69.841279 */\r
+ hpet_counter_tick_period = hpetHPET_COUNTER_TICK_PERIOD;\r
+\r
+ /* General status of HPET - bit 0 = T0, bit 1 = T1 and bit 2 = T2.\r
+ * In level triggered mode 1 means interrupt is active */\r
+ hpet_general_status = hpetHPET_GENERAL_STATUS;\r
+}\r
+#endif\r
+/*-----------------------------------------------------------*/\r
+\r
+#if (hpetHPET_TIMER_IN_USE)\r
+static void vCheckHPETIRQCapabilities( uint32_t TimerNumber)\r
+{\r
+ uint32_t hpet_cfg_h = 0UL;\r
+ uint32_t hpet_cfg_l = 0UL;\r
+ uint32_t IRQNumber = 0UL;\r
+ uint32_t Triggering = hpetHPET_INT_EDGE;\r
+\r
+ #if( hpetUSE_HPET_TIMER_NUMBER_0 == 1 )\r
+ {\r
+ if (TimerNumber == 0)\r
+ {\r
+ IRQNumber = TIMER0_IRQ;\r
+ Triggering = TIMER0_TRIGGERING;\r
+ hpet_cfg_h = hpetHPET_TMR0_CONFIG_HIGH;\r
+ hpet_cfg_l = hpetHPET_TMR0_CONFIG_LOW;\r
+ }\r
+ }\r
+ #endif\r
+ #if( hpetUSE_HPET_TIMER_NUMBER_1 == 1 )\r
+ {\r
+ if (TimerNumber == 1)\r
+ {\r
+ IRQNumber = TIMER1_IRQ;\r
+ Triggering = TIMER1_TRIGGERING;\r
+ hpet_cfg_h = hpetHPET_TMR1_CONFIG_HIGH;\r
+ hpet_cfg_l = hpetHPET_TMR1_CONFIG_LOW;\r
+ }\r
+ }\r
+ #endif\r
+ #if( hpetUSE_HPET_TIMER_NUMBER_2 == 1 )\r
+ {\r
+ if (TimerNumber == 2)\r
+ {\r
+ IRQNumber = TIMER2_IRQ;\r
+ Triggering = TIMER2_TRIGGERING;\r
+ hpet_cfg_h = hpetHPET_TMR2_CONFIG_HIGH;\r
+ hpet_cfg_l = hpetHPET_TMR2_CONFIG_LOW;\r
+ }\r
+ }\r
+ #endif\r
+\r
+ /* Setup configuration register */\r
+ hpet_cfg_l |= hpetHPET_TN_ENABLE | hpetHPET_TN_PERIODIC |\r
+ hpetHPET_TN_32BIT | ((IRQNumber & 0x1F) << 9UL);\r
+\r
+ /* Setup triggering bit */\r
+ if (Triggering != hpetHPET_INT_EDGE)\r
+ hpet_cfg_l |= (1UL << 1UL);\r
+ else\r
+ hpet_cfg_l &= ~(1UL << 1UL);\r
+\r
+ /* Write then read back configuration */\r
+ #if( hpetUSE_HPET_TIMER_NUMBER_0 == 1 )\r
+ {\r
+ if (TimerNumber == 0)\r
+ {\r
+ hpetHPET_TMR0_CONFIG_HIGH = hpet_cfg_h;\r
+ hpetHPET_TMR0_CONFIG_LOW = hpet_cfg_l;\r
+ hpet_cfg_l = hpetHPET_TMR0_CONFIG_LOW;\r
+ }\r
+ }\r
+ #endif\r
+ #if( hpetUSE_HPET_TIMER_NUMBER_1 == 1 )\r
+ {\r
+ if (TimerNumber == 1)\r
+ {\r
+ hpetHPET_TMR1_CONFIG_HIGH = hpet_cfg_h;\r
+ hpetHPET_TMR1_CONFIG_LOW = hpet_cfg_l;\r
+ hpet_cfg_l = hpetHPET_TMR1_CONFIG_LOW;\r
+ }\r
+ }\r
+ #endif\r
+ #if( hpetUSE_HPET_TIMER_NUMBER_2 == 1 )\r
+ {\r
+ if (TimerNumber == 2)\r
+ {\r
+ hpetHPET_TMR2_CONFIG_HIGH = hpet_cfg_h;\r
+ hpetHPET_TMR2_CONFIG_LOW = hpet_cfg_l;\r
+ hpet_cfg_l = hpetHPET_TMR2_CONFIG_LOW;\r
+ }\r
+ }\r
+ #endif\r
+}\r
+#endif\r
+/*-----------------------------------------------------------*/\r
+\r
+#if (hpetHPET_TIMER_IN_USE)\r
+static uint32_t uiCalibrateHPETTimer(uint32_t TimerNumber, uint32_t Calibrate)\r
+{\r
+ uint32_t ticks_per_ms = 15422; // 1e-3/64.84127e-9 (denominator is hpet_counter_tick_period)\r
+ if (Calibrate)\r
+ {\r
+ uint32_t uiRunningTotal = 0UL;\r
+ uint32_t i = 0UL;\r
+ for (i = 0; i < 5; i++)\r
+ uiRunningTotal += uiCalibrateTimer(TimerNumber, hpetHPETIMER);\r
+ ticks_per_ms = (uiRunningTotal / 5);\r
+ }\r
+ return ticks_per_ms;\r
+}\r
+#endif\r
+/*-----------------------------------------------------------*/\r
+\r
+#if (hpetHPET_TIMER_IN_USE)\r
+static void vSetupIOApic( uint32_t TimerNumber )\r
+{\r
+ uint8_t DeliveryMode = 1; // 0 means fixed (use ISR Vector)\r
+ uint8_t DestinationMode = 0; // Used by local APIC for MSI\r
+ uint8_t IRQPolarity = 1; // 0 means active high, 1 = active low\r
+ uint8_t InterruptMask = 0; // 0 means allow interrupts\r
+ uint8_t Triggering = hpetHPET_INT_EDGE; // Level or Edge sensitive\r
+ uint8_t IRQNumber = 0; // Hardware IRQ number\r
+ uint8_t ISRVector = 0; // Desired ISR vector\r
+\r
+ /* Select polarity and triggering */\r
+ #if( hpetUSE_HPET_TIMER_NUMBER_0 == 1 )\r
+ {\r
+ if (TimerNumber == 0)\r
+ {\r
+ IRQNumber = TIMER0_IRQ;\r
+ ISRVector = hpetHPET_TIMER0_ISR_VECTOR;\r
+ IRQPolarity = TIMER0_POLARITY;\r
+ Triggering = TIMER0_TRIGGERING;\r
+ }\r
+ }\r
+ #endif\r
+ #if( hpetUSE_HPET_TIMER_NUMBER_1 == 1 )\r
+ {\r
+ if (TimerNumber == 1)\r
+ {\r
+ IRQNumber = TIMER1_IRQ;\r
+ ISRVector = hpetHPET_TIMER1_ISR_VECTOR;\r
+ IRQPolarity = TIMER1_POLARITY;\r
+ Triggering = TIMER1_TRIGGERING;\r
+ }\r
+ }\r
+ #endif\r
+ #if( hpetUSE_HPET_TIMER_NUMBER_2 == 1 )\r
+ {\r
+ if (TimerNumber == 2)\r
+ {\r
+ IRQNumber = TIMER2_IRQ;\r
+ ISRVector = hpetHPET_TIMER2_ISR_VECTOR;\r
+ IRQPolarity = TIMER2_POLARITY;\r
+ Triggering = TIMER2_TRIGGERING;\r
+ }\r
+ }\r
+ #endif\r
+\r
+ /* Data to write to RTE register Lower DW */\r
+ uint32_t ConfigDataLDW = (uint32_t)(ISRVector | ((DeliveryMode & 0x07) << 8UL));\r
+\r
+ /* Set or clear bits in configuration data */\r
+ if (DestinationMode == 0)\r
+ ConfigDataLDW &= ~(1UL << 11UL);\r
+ else\r
+ ConfigDataLDW |= (1UL << 11UL);\r
+\r
+ if (IRQPolarity == 0)\r
+ ConfigDataLDW &= ~(1UL << 13UL);\r
+ else\r
+ ConfigDataLDW |= (1UL << 13UL);\r
+\r
+ if (Triggering != FALSE)\r
+ ConfigDataLDW |= (1UL << 15UL);\r
+ else\r
+ ConfigDataLDW &= ~(1UL << 15UL);\r
+\r
+ if (InterruptMask == 0)\r
+ ConfigDataLDW &= ~(1UL << 16UL);\r
+ else\r
+ ConfigDataLDW |= (1UL << 16UL);\r
+\r
+ /* Data to write to RTE register Upper DW */\r
+ uint32_t LocalAPIC_DID = ((portAPIC_ID_REGISTER & 0xFF000000UL) >> 24UL); // get local APIC DID\r
+ uint32_t LocalAPIC_EDID = ((portAPIC_ID_REGISTER & 0x00FF0000UL) >> 16UL); // get local APIC Extended DID\r
+ uint32_t ConfigDataUDW = (uint32_t)(((LocalAPIC_DID << 24UL) & 0xFF000000UL) |\r
+ ((LocalAPIC_EDID << 16UL) & 0x00FF0000UL));\r
+\r
+ /* Setup IDX and WDW register to write RTE data */\r
+ hpetIO_APIC_IDX = hpetIO_APIC_RTE_OFFSET + ((2 * IRQNumber) + 1);\r
+ hpetIO_APIC_WDW = ConfigDataUDW;\r
+ hpetIO_APIC_IDX = hpetIO_APIC_RTE_OFFSET + ((2 * IRQNumber) + 0);\r
+ hpetIO_APIC_WDW = ConfigDataLDW;\r
+}\r
+#endif\r
+/*-----------------------------------------------------------*/\r
+\r
+#if (hpetHPET_TIMER_IN_USE)\r
+static void vInitilizeHPETInterrupt( uint32_t TimerNumber )\r
+{\r
+ /* NOTE: In non-legacy mode interrupts are sent as MSI messages to LAPIC */\r
+\r
+ uint32_t ticks_per_ms = 0UL; // Get # ticks per ms\r
+ uint32_t InterruptFrequency = 0UL; // Get times per second to interrupt\r
+\r
+ /* Stop the timers and reset the main counter */\r
+ vStopHPETTimer(true);\r
+\r
+ /* Initialise hardware */\r
+ vSetupIOApic(TimerNumber);\r
+\r
+ /* Register ISRs. Purely for demonstration purposes, timer 0 and timer 2\r
+ use the central interrupt entry code, so are installed using\r
+ xPortRegisterCInterruptHandler(), while timer 1 uses its own interrupt\r
+ entry code, so is installed using xPortInstallInterruptHandler(). For\r
+ convenience the entry code for timer 1 is implemented at the bottom of\r
+ RegTest.S.See\r
+ http://www.freertos.org/RTOS_Intel_Quark_Galileo_GCC.html#interrupts for\r
+ more information. */\r
+ #if( hpetUSE_HPET_TIMER_NUMBER_0 == 1 )\r
+ {\r
+ if (TimerNumber == 0)\r
+ {\r
+ InterruptFrequency = hpetHPET_TIMER0_INTERRUPT_RATE;\r
+ xPortRegisterCInterruptHandler( vHPETIRQHandler0, hpetHPET_TIMER0_ISR_VECTOR );\r
+ }\r
+ }\r
+ #endif\r
+ #if( hpetUSE_HPET_TIMER_NUMBER_1 == 1 )\r
+ {\r
+ if (TimerNumber == 1)\r
+ {\r
+ extern void vApplicationHPETTimer1Wrapper( void );\r
+\r
+ InterruptFrequency = hpetHPET_TIMER1_INTERRUPT_RATE;\r
+ xPortInstallInterruptHandler( vApplicationHPETTimer1Wrapper, hpetHPET_TIMER1_ISR_VECTOR );\r
+ }\r
+ }\r
+ #endif\r
+ #if ( hpetUSE_HPET_TIMER_NUMBER_2 == 1)\r
+ {\r
+ if (TimerNumber == 2)\r
+ {\r
+ configASSERT(TimerNumber == 2)\r
+ InterruptFrequency = hpetHPET_TIMER2_INTERRUPT_RATE;\r
+ xPortRegisterCInterruptHandler( vHPETIRQHandler2, hpetHPET_TIMER2_ISR_VECTOR );\r
+ }\r
+ }\r
+ #endif\r
+\r
+ /* Get calibrated ticks per millisecond before initialization. */\r
+ ticks_per_ms = uiCalibrateHPETTimer(TimerNumber, TRUE);\r
+\r
+ /* Check IRQ compatibility - will assert here if there is a problem. */\r
+ vCheckHPETIRQCapabilities(TimerNumber);\r
+\r
+ /* Get HPET capabilities and ID and status */\r
+ vGetHPETCapabilitiesAndStatus();\r
+\r
+ /* Sanity check for frequency */\r
+ if ( InterruptFrequency < 1 )\r
+ InterruptFrequency = 20; // default is 50 ms interrupt rate\r
+\r
+ /* Save interrupt frequency */\r
+ ulHPETInterruptFrequency[TimerNumber] = InterruptFrequency;\r
+\r
+ /* Calculate required number of ticks */\r
+ uint32_t ticks = ( ticks_per_ms * 1000UL ) / ulHPETInterruptFrequency[TimerNumber];\r
+\r
+ /* Save the number of ticks to interrupt */\r
+ ulHPETTicksToInterrupt[TimerNumber] = ticks;\r
+\r
+ /* Make sure counters are zeroed */\r
+ vClearHPETCounters();\r
+\r
+ /* Write out comparator value */\r
+ vSetHPETComparator(TimerNumber, ticks);\r
+\r
+ /* Set target timer non-periodic mode with first interrupt at tick */\r
+ vConfigureHPETTimer(TimerNumber, FALSE);\r
+\r
+ /* Start the timer */\r
+ vStartHPETTimer();\r
+}\r
+#endif\r
+/*-----------------------------------------------------------*/\r
+\r
+#if (hpetHPET_TIMER_IN_USE)\r
+void vInitializeAllHPETInterrupts( void )\r
+{\r
+ #if( hpetUSE_HPET_TIMER_NUMBER_0 == 1 )\r
+ vInitilizeHPETInterrupt( 0 );\r
+ #endif\r
+ #if( hpetUSE_HPET_TIMER_NUMBER_1 == 1 )\r
+ vInitilizeHPETInterrupt( 1 );\r
+ #endif\r
+ #if( hpetUSE_HPET_TIMER_NUMBER_2 == 1 )\r
+ vInitilizeHPETInterrupt( 2 );\r
+ #endif\r
+}\r
+#endif\r
+/*-----------------------------------------------------------*/\r
+\r
+uint32_t uiCalibrateTimer( uint32_t TimerNumber, uint32_t TimerType)\r
+{\r
+ /*---------------------------------------------------------------------*/\r
+ /* NOTE: If TimerType = LVTIMER then TimerNumber is ignored (PIT # 2 */\r
+ /* is always used) */\r
+ /*---------------------------------------------------------------------*/\r
+ /*---------------------------------------------------------------------*/\r
+ /* PIT (programmable interval timer) mode register Bit definitions */\r
+ /*----------------------------------------------------------------------\r
+ Mode register is at address 0x43:\r
+ Bits Usage\r
+ 6 and 7 Select channel :\r
+ 0 0 = Channel 0\r
+ 0 1 = Channel 1\r
+ 1 0 = Channel 2\r
+ 1 1 = Read-back command (8254 only)\r
+ 4 and 5 Access mode :\r
+ 0 0 = Latch count value command\r
+ 0 1 = Access mode: lobyte only\r
+ 1 0 = Access mode: hibyte only\r
+ 1 1 = Access mode: lobyte/hibyte\r
+ 1 to 3 Operating mode :\r
+ 0 0 0 = Mode 0 (interrupt on terminal count)\r
+ 0 0 1 = Mode 1 (hardware re-triggerable one-shot)\r
+ 0 1 0 = Mode 2 (rate generator)\r
+ 0 1 1 = Mode 3 (square wave generator)\r
+ 1 0 0 = Mode 4 (software triggered strobe)\r
+ 1 0 1 = Mode 5 (hardware triggered strobe)\r
+ 1 1 0 = Mode 2 (rate generator, same as 010b)\r
+ 1 1 1 = Mode 3 (square wave generator, same as 011b)\r
+ 0 BCD/Binary mode: 0 = 16-bit binary, 1 = four-digit BCD\r
+ ----------------------------------------------------------------------*/\r
+\r
+ /* Used to calculate LVT ticks */\r
+ const uint32_t uiLargeNumber = 0x7fffffffUL;\r
+\r
+ /* Default return value */\r
+ uint32_t ticks = 0;\r
+\r
+ /* Check timer type */\r
+ switch (TimerType)\r
+ {\r
+ case hpetLVTIMER:\r
+ case hpetHPETIMER:\r
+ break;\r
+ default:\r
+ return ticks;\r
+ break;\r
+ }\r
+\r
+ /* Set timeout counter to a very large value */\r
+ uint64_t timeout_counter = (uint64_t) (uiLargeNumber * 4);\r
+\r
+ /* Set PIT Ch2 to one-shot mode */\r
+ uint32_t gate_register = ((inw(GATE_CONTROL) & 0xfd) | 0x01);\r
+ outw(GATE_CONTROL, gate_register);\r
+ outw(MODE_REGISTER, ONESHOT_MODE);\r
+\r
+ /* Set counter for 10 ms - 1193180/100 Hz ~ 11932 */\r
+ uint16_t pit_counter = 11932;\r
+ outb(CHANNEL2_DATA, (char) (pit_counter & 0xff));\r
+ outb(CHANNEL2_DATA, (char) ((pit_counter >> 8) & 0xff));\r
+\r
+ /* Start target timer */\r
+ if (TimerType == hpetLVTIMER)\r
+ {\r
+ portAPIC_LVT_TIMER = portAPIC_TIMER_INT_VECTOR;\r
+ portAPIC_TMRDIV = portAPIC_DIV_16;\r
+ }\r
+ else if (TimerType == hpetHPETIMER)\r
+ {\r
+ #if (hpetHPET_TIMER_IN_USE)\r
+ // Initialize HPE timer\r
+ vStopHPETTimer(TRUE);\r
+ /* Write out comparator value - we don't want it to interrupt */\r
+ vSetHPETComparator(TimerNumber, 0xFFFFFFFFUL);\r
+ // Configure HPE timer for non-periodic mode\r
+ vConfigureHPETTimer(TimerNumber, FALSE);\r
+ #else\r
+ ( void ) TimerNumber;\r
+ #endif\r
+ }\r
+\r
+ /* Reset PIT one-shot counter */\r
+ gate_register = (inw(GATE_CONTROL) & 0xfe);\r
+ outw(GATE_CONTROL, gate_register);\r
+ gate_register |= 0x01;\r
+ outw(GATE_CONTROL, gate_register);\r
+\r
+ /* Setup target timer initial counts */\r
+ if (TimerType == hpetLVTIMER)\r
+ {\r
+ portAPIC_TIMER_INITIAL_COUNT = uiLargeNumber;\r
+ }\r
+ else if (TimerType == hpetHPETIMER)\r
+ {\r
+ #if (hpetHPET_TIMER_IN_USE)\r
+ vStartHPETTimer();\r
+ #endif\r
+ }\r
+\r
+ /* Wait for PIT counter to expire */\r
+ for (;;)\r
+ {\r
+ gate_register = inw(GATE_CONTROL);\r
+ if ((gate_register & 0x20) || (--timeout_counter == 0))\r
+ {\r
+ /* Stop target timer and exit loop */\r
+ if (TimerType == hpetLVTIMER)\r
+ {\r
+ portAPIC_LVT_TIMER = portAPIC_DISABLE;\r
+ break;\r
+ }\r
+ else if (TimerType == hpetHPETIMER)\r
+ {\r
+ #if (hpetHPET_TIMER_IN_USE)\r
+ vStopHPETTimer(FALSE);\r
+ break;\r
+ #endif\r
+ }\r
+ }\r
+ }\r
+\r
+ /* Check for timeout */\r
+ if (timeout_counter != 0)\r
+ {\r
+ if (TimerType == hpetLVTIMER)\r
+ {\r
+ /* Counter started at a large number so subtract counts */\r
+ ticks = (uiLargeNumber - portAPIC_TIMER_CURRENT_COUNT);\r
+ /* adjust ticks for 1 ms and divider ratio */\r
+ ticks = ((((ticks << 4UL) * 100) / 1000) >> 4UL);\r
+ }\r
+ else if (TimerType == hpetHPETIMER)\r
+ {\r
+ #if (hpetHPET_TIMER_IN_USE)\r
+ /* Read timer counter - we only need the low counter */\r
+ ticks = (uint32_t)(ullReadHPETCounters() & 0xFFFFFFFFULL);\r
+ /* Clear timer counter */\r
+ vClearHPETCounters();\r
+ /* Return 1 ms tick counts. Timed for 10 ms so just divide by 10 */\r
+ ticks /= 10;\r
+ #endif\r
+ }\r
+ }\r
+\r
+ /* Return adjusted counts for a 1 ms interrupt rate.\r
+ * Should be approximately 25000 for LV Timer.\r
+ * Should be approximately 15000 for HPE Timers */\r
+ return ticks;\r
+}\r
+\r
+/*-----------------------------------------------------------------------\r
+ * Interrupt service functions\r
+ *------------------------------------------------------------------------\r
+ */\r
+#if (hpetHPET_TIMER_IN_USE)\r
+static inline void vHPET_ISR( uint32_t TimerNumber )\r
+{\r
+ /*-----------------------------------------------------------------*/\r
+ /* Notes: In edge triggered mode, no need to clear int status bits.*/\r
+ /* */\r
+ /* In non-periodic mode, comparator is added to current counts, */\r
+ /* do not clear main counters. */\r
+ /*-----------------------------------------------------------------*/\r
+ __asm volatile( "cli" );\r
+\r
+ /* Bump HPE timer interrupt count - available in a global variable */\r
+ ulHPETTotalInterrupts[TimerNumber] += 1UL;\r
+\r
+ /* Bump HPE timer elapsed seconds count - available in a global variable */\r
+ if ((ulHPETTotalInterrupts[TimerNumber] %\r
+ (ulHPETInterruptFrequency[TimerNumber] + 0UL)) == 0UL)\r
+ ulHPETElapsedSeconds[TimerNumber] += 1UL;\r
+\r
+ /* Reload comparators - a must do in non-periodic mode */\r
+ uint64_t ullNewValue = (uint64_t)\r
+ (ullReadHPETCounters() + (uint64_t)ulHPETTicksToInterrupt[TimerNumber]);\r
+ vSetHPETComparator(TimerNumber, ullNewValue);\r
+\r
+ __asm volatile( "sti" );\r
+}\r
+#endif\r
+/*-----------------------------------------------------------*/\r
+\r
+#if( hpetUSE_HPET_TIMER_NUMBER_0 == 1 )\r
+ extern void vApplicationHPETTimer0Handler( void );\r
+ static void vHPETIRQHandler0( void )\r
+ {\r
+ vHPET_ISR( 0 );\r
+ vApplicationHPETTimer0Handler();\r
+ hpetIO_APIC_EOI = hpetHPET_TIMER0_ISR_VECTOR;\r
+ }\r
+#endif\r
+/*-----------------------------------------------------------*/\r
+\r
+#if( hpetUSE_HPET_TIMER_NUMBER_1 == 1 )\r
+ extern void vApplicationHPETTimer1Handler( void );\r
+ void vHPETIRQHandler1( void )\r
+ {\r
+ vHPET_ISR( 1 );\r
+ vApplicationHPETTimer1Handler();\r
+ hpetIO_APIC_EOI = hpetHPET_TIMER1_ISR_VECTOR;\r
+ }\r
+#endif\r
+/*-----------------------------------------------------------*/\r
+\r
+#if( hpetUSE_HPET_TIMER_NUMBER_2 == 1 )\r
+ extern void vApplicationHPETTimer2Handler( void );\r
+ static void vHPETIRQHandler2( void )\r
+ {\r
+ vHPET_ISR( 2 );\r
+ vApplicationHPETTimer2Handler();\r
+ hpetIO_APIC_EOI = hpetHPET_TIMER2_ISR_VECTOR;\r
+ }\r
+#endif\r
+\r
+/*-----------------------------------------------------------------------\r
+ * Print HPET information functions\r
+ *------------------------------------------------------------------------\r
+ */\r
+#if ((hpetHPET_PRINT_INFO == 1 ) && (hpetHPET_TIMER_IN_USE))\r
+static void prvUpdateHPETInfoTask( void *pvParameters )\r
+{\r
+TickType_t xNextWakeTime, xBlockTime;\r
+uint32_t TimerNumber;\r
+uint8_t row, col, execute;\r
+struct hpet_info *pi;\r
+\r
+ /* Remove compiler warning about unused parameter. */\r
+ ( void ) pvParameters;\r
+\r
+ /* Initialise xNextWakeTime - this only needs to be done once. */\r
+ xNextWakeTime = xTaskGetTickCount();\r
+\r
+ /* Set task blocking period. */\r
+ xBlockTime = pdMS_TO_TICKS( 500 );\r
+\r
+ for( ;; )\r
+ {\r
+ /* Place this task in the blocked state until it is time to run again. */\r
+ vTaskDelayUntil( &xNextWakeTime, xBlockTime );\r
+\r
+ /* Print all information */\r
+ for (TimerNumber = 0; TimerNumber <= 2; TimerNumber++)\r
+ {\r
+ execute = pdFALSE;\r
+ pi = &PrintInfo[TimerNumber];\r
+ pi->timer_number = TimerNumber;\r
+ pi->main_counter_h = hpetHPET_MAIN_CTR_HIGH;\r
+ pi->main_counter_l = hpetHPET_MAIN_CTR_LOW;\r
+ pi->total_interrupts = ulHPETTotalInterrupts[TimerNumber];\r
+ pi->elapsed_seconds = ulHPETElapsedSeconds[TimerNumber];\r
+ #if (hpetUSE_HPET_TIMER_NUMBER_0 == 1 )\r
+ if(TimerNumber == 0)\r
+ {\r
+ row = 8 ; col = 1;\r
+ pi->comparator_h = hpetHPET_TMR0_COMPARATOR_HIGH;\r
+ pi->comparator_l = hpetHPET_TMR0_COMPARATOR_LOW;\r
+ execute = pdTRUE;\r
+ }\r
+ #endif\r
+ #if ( hpetUSE_HPET_TIMER_NUMBER_1 == 1 )\r
+ if(TimerNumber == 1)\r
+ {\r
+ row = 12 ; col = 1;\r
+ pi->comparator_h = hpetHPET_TMR1_COMPARATOR_HIGH;\r
+ pi->comparator_l = hpetHPET_TMR1_COMPARATOR_LOW;\r
+ execute = pdTRUE;\r
+ }\r
+ #endif\r
+ #if ( hpetUSE_HPET_TIMER_NUMBER_2 == 1 )\r
+ if(TimerNumber == 2)\r
+ {\r
+ row = 16 ; col = 1;\r
+ pi->comparator_h = hpetHPET_TMR2_COMPARATOR_HIGH;\r
+ pi->comparator_l = hpetHPET_TMR2_COMPARATOR_LOW;\r
+ execute = pdTRUE;\r
+ }\r
+ #endif\r
+\r
+ /* Print information on screen */\r
+ if(execute == pdTRUE)\r
+ {\r
+ g_printf_rcc(row, col, ANSI_COLOR_WHITE,\r
+ " HPE Timer Number = %d", pi->timer_number);\r
+ g_printf_rcc(row+1, col, ANSI_COLOR_WHITE,\r
+ " Timer Counters = 0x%08x:%08x, Comparator = 0x%08x:%08x",\r
+ pi->main_counter_h, pi->main_counter_l,\r
+ pi->comparator_h, pi->comparator_l);\r
+ g_printf_rcc(row+2, col, ANSI_COLOR_WHITE,\r
+ " Total Interrupts = 0x%08x Elapsed Seconds = %u",\r
+ pi->total_interrupts, pi->elapsed_seconds);\r
+ g_printf_rcc(row+3, col, DEFAULT_SCREEN_COLOR , "\r");\r
+ }\r
+ }\r
+ }\r
+}\r
+#endif\r
+/*-----------------------------------------------------------*/\r
+\r
+void vCreateHPETInfoUpdateTask( void )\r
+{\r
+#if ((hpetHPET_PRINT_INFO == 1 ) && (hpetHPET_TIMER_IN_USE))\r
+ /* Create the task that displays HPE timer information. */\r
+ xTaskCreate( prvUpdateHPETInfoTask, "HPETInfo", (configMINIMAL_STACK_SIZE << 1),\r
+ NULL, (tskIDLE_PRIORITY), NULL );\r
+#endif\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+\r
+\r
--- /dev/null
+/*--------------------------------------------------------------------\r
+ Copyright(c) 2015 Intel Corporation. All rights reserved.\r
+\r
+ Redistribution and use in source and binary forms, with or without\r
+ modification, are permitted provided that the following conditions\r
+ are met:\r
+\r
+ * Redistributions of source code must retain the above copyright\r
+ notice, this list of conditions and the following disclaimer.\r
+ * Redistributions in binary form must reproduce the above copyright\r
+ notice, this list of conditions and the following disclaimer in\r
+ the documentation and/or other materials provided with the\r
+ distribution.\r
+ * Neither the name of Intel Corporation nor the names of its\r
+ contributors may be used to endorse or promote products derived\r
+ from this software without specific prior written permission.\r
+\r
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
+ "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
+ LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
+ A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\r
+ OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\r
+ SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\r
+ DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\r
+ THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ --------------------------------------------------------------------*/\r
+\r
+#ifndef HPET_H\r
+#define HPET_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+//---------------------------------------------------------------------\r
+// HPET support definitions\r
+//---------------------------------------------------------------------\r
+#define hpetUSE_HPET_TIMER_NUMBER_0 ( 1 ) // 0 = false, 1 = true\r
+#define hpetUSE_HPET_TIMER_NUMBER_1 ( 1 ) // 0 = false, 1 = true\r
+#define hpetUSE_HPET_TIMER_NUMBER_2 ( 1 ) // 0 = false, 1 = true\r
+\r
+//---------------------------------------------------------------------\r
+// HPE timers general purpose register addresses\r
+//---------------------------------------------------------------------\r
+#define hpetHPET_GENERAL_ID ( *( ( volatile uint32_t * ) 0xFED00000UL ) )\r
+#define hpetHPET_COUNTER_TICK_PERIOD ( *( ( volatile uint32_t * ) 0xFED00004UL ) )\r
+#define hpetHPET_GENERAL_CONFIGURATION ( *( ( volatile uint32_t * ) 0xFED00010UL ) )\r
+#define hpetHPET_GENERAL_STATUS ( *( ( volatile uint32_t * ) 0xFED00020UL ) )\r
+#define hpetHPET_MAIN_CTR_LOW ( *( ( volatile uint32_t * ) 0xFED000F0UL ) )\r
+#define hpetHPET_MAIN_CTR_HIGH ( *( ( volatile uint32_t * ) 0xFED000F4UL ) )\r
+\r
+//---------------------------------------------------------------------\r
+// HPE timer specific support definitions\r
+//---------------------------------------------------------------------\r
+#if (hpetUSE_HPET_TIMER_NUMBER_0 == 1)\r
+ #define TIMER0_TRIGGERING ( 0 ) // 1 = level, 0 = edge\r
+ #define TIMER0_POLARITY ( 0 ) // 0 = active high, 1 = active low\r
+ #define TIMER0_IRQ ( 2 ) // 0 is default for legacy 8259, 2 for IO APIC\r
+ #define hpetHPET_TIMER0_ISR_VECTOR ( 0x32 ) // HPET Timer - I/O APIC\r
+ #define hpetHPET_TIMER0_INTERRUPT_RATE ( 2000 ) // Number of times per second to interrupt\r
+ #define hpetHPET_TMR0_CONFIG_LOW ( *( ( volatile uint32_t * ) 0xFED00100UL ) )\r
+ #define hpetHPET_TMR0_CONFIG_HIGH ( *( ( volatile uint32_t * ) 0xFED00104UL ) )\r
+ #define hpetHPET_TMR0_COMPARATOR_LOW ( *( ( volatile uint32_t * ) 0xFED00108UL ) )\r
+ #define hpetHPET_TMR0_COMPARATOR_HIGH ( *( ( volatile uint32_t * ) 0xFED0010CUL ) )\r
+#endif\r
+#if (hpetUSE_HPET_TIMER_NUMBER_1 == 1)\r
+ #define TIMER1_TRIGGERING ( 0 ) // 1 = level, 0 = edge\r
+ #define TIMER1_POLARITY ( 0 ) // 0 = active high, 1 = active low\r
+ #define TIMER1_IRQ ( 8 ) // 8 is default for 8259 & IO APIC\r
+ #define hpetHPET_TIMER1_ISR_VECTOR ( 0x85 ) // HPET Timer - I/O APIC\r
+ #define hpetHPET_TIMER1_INTERRUPT_RATE ( 1500 ) // Number of times per second to interrupt\r
+ #define hpetHPET_TMR1_CONFIG_LOW ( *( ( volatile uint32_t * ) 0xFED00120UL ) )\r
+ #define hpetHPET_TMR1_CONFIG_HIGH ( *( ( volatile uint32_t * ) 0xFED00124UL ) )\r
+ #define hpetHPET_TMR1_COMPARATOR_LOW ( *( ( volatile uint32_t * ) 0xFED00128UL ) )\r
+ #define hpetHPET_TMR1_COMPARATOR_HIGH ( *( ( volatile uint32_t * ) 0xFED0012CUL ) )\r
+#endif\r
+#if (hpetUSE_HPET_TIMER_NUMBER_2 == 1)\r
+ #define TIMER2_TRIGGERING ( 0 ) // 1 = level, 0 = edge\r
+ #define TIMER2_POLARITY ( 0 ) // 0 = active high, 1 = active low\r
+ #define TIMER2_IRQ ( 11 ) // 11 is default for 8259 & IO APIC\r
+ #define hpetHPET_TIMER2_ISR_VECTOR ( 0x95 ) // HPET Timer - I/O APIC\r
+ #define hpetHPET_TIMER2_INTERRUPT_RATE ( 1400 ) // Number of times per second to interrupt\r
+ #define hpetHPET_TMR2_CONFIG_LOW ( *( ( volatile uint32_t * ) 0xFED00140UL ) )\r
+ #define hpetHPET_TMR2_CONFIG_HIGH ( *( ( volatile uint32_t * ) 0xFED00144UL ) )\r
+ #define hpetHPET_TMR2_COMPARATOR_LOW ( *( ( volatile uint32_t * ) 0xFED00148UL ) )\r
+ #define hpetHPET_TMR2_COMPARATOR_HIGH ( *( ( volatile uint32_t * ) 0xFED0014CUL ) )\r
+#endif\r
+\r
+//---------------------------------------------------------------------\r
+// Disables code if no timer is enabled (quiets the compiler)\r
+//---------------------------------------------------------------------\r
+#define hpetHPET_TIMER_IN_USE (hpetUSE_HPET_TIMER_NUMBER_0 | hpetUSE_HPET_TIMER_NUMBER_1 | hpetUSE_HPET_TIMER_NUMBER_2)\r
+\r
+//---------------------------------------------------------------------\r
+// Allow HPET variable printout on screen (1 = allow)\r
+//---------------------------------------------------------------------\r
+#define hpetHPET_PRINT_INFO 0\r
+\r
+//---------------------------------------------------------------------\r
+// HPET bit checking and manipulation definitions\r
+//---------------------------------------------------------------------\r
+#define hpetHPET_CFG_ENABLE 0x001\r
+#define hpetHPET_CFG_LEGACY 0x002\r
+#define hpetHPET_TN_ENABLE 0x004\r
+#define hpetHPET_TN_PERIODIC 0x008\r
+#define hpetHPET_TN_PERIODIC_CAP 0x010\r
+#define hpetHPET_TN_SETVAL 0x040\r
+#define hpetHPET_TN_32BIT 0x100\r
+#define hpetHPET_INT_EDGE 0x000\r
+#define hpetHPET_INT_LEVEL 0x001\r
+#define hpetHPET_POL_HIGH 0x000\r
+#define hpetHPET_POL_LOW 0x001\r
+\r
+//---------------------------------------------------------------------\r
+// I/O APIC register addresses and definitions\r
+//---------------------------------------------------------------------\r
+#define hpetIO_APIC_IDX ( *( ( volatile uint32_t * ) 0xFEC00000UL ) )\r
+#define hpetIO_APIC_WDW ( *( ( volatile uint32_t * ) 0xFEC00010UL ) )\r
+#define hpetIO_APIC_EOI ( *( ( volatile uint32_t * ) 0xFEC00040UL ) )\r
+\r
+#define hpetIO_APIC_ID 0x00 // Get/Set APIC ID information\r
+#define hpetIO_APIC_VERSION 0x01 // Get APIC version information\r
+#define hpetIO_APIC_RTE_OFFSET 0x10 // add 2* RTE Table (0-23) to this offset\r
+\r
+//---------------------------------------------------------------------\r
+// Used for timer calibration\r
+//---------------------------------------------------------------------\r
+#define hpetLVTIMER ( 0 ) // Constant definition\r
+#define hpetHPETIMER ( 1 ) // Constant definition\r
+\r
+//---------------------------------------------------------------------\r
+// HPET variables Structure\r
+//---------------------------------------------------------------------\r
+struct __attribute__ ((__packed__)) hpet_info\r
+{\r
+ unsigned int timer_number;\r
+ unsigned int main_counter_h;\r
+ unsigned int main_counter_l;\r
+ unsigned int comparator_h;\r
+ unsigned int comparator_l;\r
+ unsigned int total_interrupts;\r
+ unsigned int elapsed_seconds;\r
+};\r
+\r
+//---------------------------------------------------------------------\r
+// Variables other modules may want to access\r
+//---------------------------------------------------------------------\r
+extern volatile uint32_t hpet_general_status;\r
+extern volatile uint32_t ulHPETTimerNumber [3];\r
+extern volatile uint32_t ulHPETTotalInterrupts [3];\r
+extern volatile uint32_t ulHPETElapsedSeconds [3];\r
+extern volatile uint32_t ulHPETInterruptFrequency [3];\r
+extern volatile uint32_t ulHPETTicksToInterrupt [3];\r
+extern struct hpet_info PrintInfo[3];\r
+\r
+//---------------------------------------------------------------------\r
+// Function prototypes\r
+//---------------------------------------------------------------------\r
+#if (hpetHPET_TIMER_IN_USE)\r
+ void vClearHPETElapsedSeconds( void );\r
+ uint32_t uiCalibrateTimer(uint32_t TimerNumber, uint32_t TimerType );\r
+ void vInitializeAllHPETInterrupts( void );\r
+ void vCreateHPETInfoUpdateTask( void );\r
+#endif\r
+\r
+#ifdef __cplusplus\r
+ } /* extern C */\r
+#endif\r
+\r
+#endif /* HPET_H */\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V8.2.1 - Copyright (C) 2015 Real Time Engineers Ltd.\r
+ All rights reserved\r
+\r
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
+\r
+ ***************************************************************************\r
+ >>! NOTE: The modification to the GPL is included to allow you to !<<\r
+ >>! distribute a combined work that includes FreeRTOS without being !<<\r
+ >>! obliged to provide the source code for proprietary components !<<\r
+ >>! outside of the FreeRTOS kernel. !<<\r
+ ***************************************************************************\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+ FOR A PARTICULAR PURPOSE. Full license text is available on the following\r
+ link: http://www.freertos.org/a00114.html\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS provides completely free yet professionally developed, *\r
+ * robust, strictly quality controlled, supported, and cross *\r
+ * platform software that is more than just the market leader, it *\r
+ * is the industry's de facto standard. *\r
+ * *\r
+ * Help yourself get started quickly while simultaneously helping *\r
+ * to support the FreeRTOS project by purchasing a FreeRTOS *\r
+ * tutorial book, reference manual, or both: *\r
+ * http://www.FreeRTOS.org/Documentation *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading\r
+ the FAQ page "My application does not run, what could be wrong?". Have you\r
+ defined configASSERT()?\r
+\r
+ http://www.FreeRTOS.org/support - In return for receiving this top quality\r
+ embedded software for free we request you assist our global community by\r
+ participating in the support forum.\r
+\r
+ http://www.FreeRTOS.org/training - Investing in training allows your team to\r
+ be as productive as possible as early as possible. Now you can receive\r
+ FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
+ Ltd, and the world's leading authority on the world's leading RTOS.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
+\r
+ http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
+ Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
+ Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS\r
+ licenses offer ticketed support, indemnification and commercial middleware.\r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
+ mission critical applications that require provable dependability.\r
+\r
+ 1 tab == 4 spaces!\r
+*/\r
+\r
+\r
+/*\r
+ * The library functions not provided by libgcc for freestanding environments.\r
+ * The implementation of the functions in this file have made NO attempt\r
+ * whatsoever to be optimised!\r
+ */\r
+\r
+#warning The functions in this file are very basic, and not optimised.\r
+\r
+#include <stddef.h>\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void *memcpy( void *pvDest, const void *pvSource, size_t xBytes )\r
+{\r
+/* The compiler used during development seems to err unless these volatiles are\r
+included at -O3 optimisation. */\r
+volatile unsigned char *pcDest = ( volatile unsigned char * ) pvDest, *pcSource = ( volatile unsigned char * ) pvSource;\r
+size_t x;\r
+\r
+ /* Extremely crude standard library implementations in lieu of having a C\r
+ library. */\r
+ if( pvDest != pvSource )\r
+ {\r
+ for( x = 0; x < xBytes; x++ )\r
+ {\r
+ pcDest[ x ] = pcSource[ x ];\r
+ }\r
+ }\r
+\r
+ return pvDest;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void *memset( void *pvDest, int iValue, size_t xBytes )\r
+{\r
+/* The compiler used during development seems to err unless these volatiles are\r
+included at -O3 optimisation. */\r
+volatile unsigned char * volatile pcDest = ( volatile unsigned char * volatile ) pvDest;\r
+volatile size_t x;\r
+\r
+ /* Extremely crude standard library implementations in lieu of having a C\r
+ library. */\r
+ for( x = 0; x < xBytes; x++ )\r
+ {\r
+ pcDest[ x ] = ( unsigned char ) iValue;\r
+ }\r
+\r
+ return pvDest;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+int memcmp( const void *pvMem1, const void *pvMem2, unsigned long ulBytes )\r
+{\r
+const volatile unsigned char *pucMem1 = pvMem1, *pucMem2 = pvMem2;\r
+register unsigned long x;\r
+\r
+ /* Extremely crude standard library implementations in lieu of having a C\r
+ library. */\r
+ for( x = 0; x < ulBytes; x++ )\r
+ {\r
+ if( pucMem1[ x ] != pucMem2[ x ] )\r
+ {\r
+ break;\r
+ }\r
+ }\r
+\r
+ return ulBytes - x;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+int strcmp( const char *pcString1, const char *pcString2 )\r
+{\r
+volatile int iReturn, iIndex = 0;\r
+\r
+ /* Extremely crude standard library implementations in lieu of having a C\r
+ library. */\r
+\r
+ while( ( pcString1[ iIndex ] != 0x00 ) && ( pcString2[ iIndex ] != 0x00 ) )\r
+ {\r
+ iIndex++;\r
+ }\r
+\r
+ if( ( pcString1[ iIndex ] == 0x00 ) && ( pcString2[ iIndex ] == 0x00 ) )\r
+ {\r
+ iReturn = 0;\r
+ }\r
+ else\r
+ {\r
+ iReturn = ~0;\r
+ }\r
+\r
+ return iReturn;\r
+}\r
+\r
+\r
--- /dev/null
+/*--------------------------------------------------------------------\r
+ Copyright(c) 2015 Intel Corporation. All rights reserved.\r
+\r
+ Redistribution and use in source and binary forms, with or without\r
+ modification, are permitted provided that the following conditions\r
+ are met:\r
+\r
+ * Redistributions of source code must retain the above copyright\r
+ notice, this list of conditions and the following disclaimer.\r
+ * Redistributions in binary form must reproduce the above copyright\r
+ notice, this list of conditions and the following disclaimer in\r
+ the documentation and/or other materials provided with the\r
+ distribution.\r
+ * Neither the name of Intel Corporation nor the names of its\r
+ contributors may be used to endorse or promote products derived\r
+ from this software without specific prior written permission.\r
+\r
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
+ "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
+ LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
+ A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\r
+ OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\r
+ SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\r
+ DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\r
+ THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ --------------------------------------------------------------------*/\r
+\r
+/*-----------------------------------------------------------------------\r
+ * Any required includes\r
+ *------------------------------------------------------------------------\r
+ */\r
+#include "multiboot.h"\r
+#include "galileo_support.h"\r
+\r
+/*-----------------------------------------------------------------------\r
+ * Any required local definitions\r
+ *------------------------------------------------------------------------\r
+ */\r
+#ifndef NULL\r
+ #define NULL (void *)0\r
+#endif\r
+\r
+#define MUTEX_WAIT_TIME (( TickType_t ) 8 )\r
+\r
+/*-----------------------------------------------------------------------\r
+ * Function prototypes\r
+ *------------------------------------------------------------------------\r
+ */\r
+extern void *memcpy( void *pvDest, const void *pvSource, unsigned long ulBytes );\r
+\r
+/*-----------------------------------------------------------------------\r
+ * Global variables\r
+ *------------------------------------------------------------------------\r
+ */\r
+uint32_t bootinfo = 1UL;\r
+uint32_t bootsign = 1UL;\r
+\r
+/*-----------------------------------------------------------------------\r
+ * Static variables\r
+ *------------------------------------------------------------------------\r
+ */\r
+static uint32_t bGalileoSerialPortInitialized = FALSE;\r
+static uint32_t uiLEDBlinkState = LED_OFF;\r
+static uint16_t usIRQMask = 0xfffb;\r
+static uint32_t UART_PCI_Base = 0UL;\r
+static uint32_t UART_MMIO_Base = 0UL;\r
+static SemaphoreHandle_t semPrintfGate = 0;\r
+\r
+/*------------------------------------------------------------------------\r
+ * GDT default entries (used in GDT setup code)\r
+ *------------------------------------------------------------------------\r
+ */\r
+static struct sd gdt_default[NGDE] =\r
+{\r
+ /* sd_lolimit sd_lobase sd_midbase sd_access sd_hilim_fl sd_hibase */\r
+ /* 0th entry NULL */\r
+ { 0, 0, 0, 0, 0, 0, },\r
+ /* 1st, Kernel Code Segment */\r
+ { 0xffff, 0, 0, 0x9a, 0xcf, 0, },\r
+ /* 2nd, Kernel Data Segment */\r
+ { 0xffff, 0, 0, 0x92, 0xcf, 0, },\r
+ /* 3rd, Kernel Stack Segment */\r
+ { 0xffff, 0, 0, 0x92, 0xcf, 0, },\r
+ /* 4st, Boot Code Segment */\r
+ { 0xffff, 0, 0, 0x9a, 0xcf, 0, },\r
+ /* 5th, Code Segment for BIOS32 request */\r
+ { 0xffff, 0, 0, 0x9a, 0xcf, 0, },\r
+ /* 6th, Data Segment for BIOS32 request */\r
+ { 0xffff, 0, 0, 0x92, 0xcf, 0, },\r
+};\r
+\r
+extern struct sd gdt[]; /* Global segment table (defined in startup.S) */\r
+\r
+/*------------------------------------------------------------------------\r
+ * Set segment registers (used in GDT setup code)\r
+ *------------------------------------------------------------------------\r
+ */\r
+void setsegs()\r
+{\r
+ extern int __text_end;\r
+ struct sd *psd;\r
+ uint32_t np, ds_end;\r
+\r
+ ds_end = 0xffffffff/PAGE_SIZE; /* End page number */\r
+\r
+ psd = &gdt_default[1]; /* Kernel code segment */\r
+ np = ((int)&__text_end - 0 + PAGE_SIZE-1) / PAGE_SIZE; /* Number of code pages */\r
+ psd->sd_lolimit = np;\r
+ psd->sd_hilim_fl = FLAGS_SETTINGS | ((np >> 16) & 0xff);\r
+\r
+ psd = &gdt_default[2]; /* Kernel data segment */\r
+ psd->sd_lolimit = ds_end;\r
+ psd->sd_hilim_fl = FLAGS_SETTINGS | ((ds_end >> 16) & 0xff);\r
+\r
+ psd = &gdt_default[3]; /* Kernel stack segment */\r
+ psd->sd_lolimit = ds_end;\r
+ psd->sd_hilim_fl = FLAGS_SETTINGS | ((ds_end >> 16) & 0xff);\r
+\r
+ psd = &gdt_default[4]; /* Boot code segment */\r
+ psd->sd_lolimit = ds_end;\r
+ psd->sd_hilim_fl = FLAGS_SETTINGS | ((ds_end >> 16) & 0xff);\r
+\r
+ memcpy(gdt, gdt_default, sizeof(gdt_default));\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/*-----------------------------------------------------------------------\r
+ * Debug serial port display update functions\r
+ *------------------------------------------------------------------------\r
+ */\r
+ static void vCreatePrintfSemaphore( void )\r
+ {\r
+ if (semPrintfGate == 0)\r
+ {\r
+ semPrintfGate = xSemaphoreCreateRecursiveMutex();\r
+ vQueueAddToRegistry( ( QueueHandle_t ) semPrintfGate, "g_printf_Mutex" );\r
+ }\r
+ }\r
+ /*-----------------------------------------------------------*/\r
+\r
+ void ClearScreen(void)\r
+ {\r
+ g_printf(ANSI_CLEAR_SB);\r
+ g_printf(ANSI_CLEAR_SCREEN);\r
+ }\r
+ /*-----------------------------------------------------------*/\r
+\r
+ void MoveToScreenPosition(uint8_t row, uint8_t col)\r
+ {\r
+ g_printf("%c[%d;%dH", (char) 0x1B, row, col);\r
+ }\r
+ /*-----------------------------------------------------------*/\r
+\r
+ void UngatedMoveToScreenPosition(uint8_t row, uint8_t col)\r
+ {\r
+ printf("%c[%d;%dH", (char) 0x1B, row, col);\r
+ }\r
+/*-----------------------------------------------------------*/\r
+\r
+ void SetScreenColor(const char *color)\r
+ {\r
+ g_printf("%s", color);\r
+ }\r
+ /*-----------------------------------------------------------*/\r
+\r
+ void g_printf(const char *format, ...)\r
+ {\r
+\r
+ if (semPrintfGate == 0)\r
+ vCreatePrintfSemaphore();\r
+\r
+ if (xSemaphoreTakeRecursive(semPrintfGate, MUTEX_WAIT_TIME))\r
+ {\r
+ va_list arguments;\r
+ va_start(arguments,format);\r
+ print(0, format, arguments);\r
+ xSemaphoreGiveRecursive(semPrintfGate);\r
+ }\r
+ }\r
+ /*-----------------------------------------------------------*/\r
+\r
+ void g_printf_rcc(uint8_t row, uint8_t col, const char *color, const char *format, ...)\r
+ {\r
+ if (semPrintfGate == 0)\r
+ vCreatePrintfSemaphore();\r
+\r
+ if (xSemaphoreTakeRecursive(semPrintfGate, MUTEX_WAIT_TIME ))\r
+ {\r
+ UngatedMoveToScreenPosition(row, col);\r
+ printf("%s",color);\r
+ va_list arguments;\r
+ va_start(arguments,format);\r
+ print(0, format, arguments);\r
+ xSemaphoreGiveRecursive(semPrintfGate);\r
+ }\r
+}\r
+ /*-----------------------------------------------------------*/\r
+\r
+ void vPrintBanner( void )\r
+ {\r
+ if (bGalileoSerialPortInitialized)\r
+ {\r
+ /* Print an RTOSDemo Loaded message */\r
+ ClearScreen();\r
+ g_printf_rcc(1, 2, DEFAULT_BANNER_COLOR,\r
+ "%c[1mHELLO from the multiboot compliant FreeRTOS kernel!%c[0m",\r
+ (char) 0x1B, (char) 0x1B );\r
+ printf(ANSI_HIDE_CURSOR);\r
+ }\r
+ }\r
+ /*-----------------------------------------------------------*/\r
+\r
+/*------------------------------------------------------------------------\r
+ * Multiboot support (show parameters passed back from GRUB)\r
+ *------------------------------------------------------------------------\r
+ */\r
+void show_kernel_parameters( unsigned long magic, unsigned long addr )\r
+{\r
+ /* Set to 0 to quiet display. */\r
+ uint8_t print_values = 1;\r
+\r
+ /* Initialise serial port if necessary. */\r
+ vInitializeGalileoSerialPort(DEBUG_SERIAL_PORT);\r
+\r
+ if (print_values != 0)\r
+ {\r
+ ClearScreen();\r
+ g_printf(DEFAULT_SCREEN_COLOR);\r
+ MoveToScreenPosition(1, 2);\r
+ g_printf ("\n\r ...MULTIBOOT VALUES RETURNED FROM GRUB...\n\n\r");\r
+ g_printf(ANSI_COLOR_WHITE);\r
+ }\r
+\r
+ if (magic != MULTIBOOT_BOOTLOADER_MAGIC)\r
+ {\r
+ printf(ANSI_COLOR_RED);\r
+ if (print_values != 0)\r
+ g_printf (" Invalid magic number returned: 0x%08x\n\r", (unsigned) magic);\r
+ g_printf(ANSI_COLOR_RESET);\r
+ }\r
+ else\r
+ {\r
+ multiboot_info_t *mbi;\r
+ /* Set MBI to the address of the Multiboot information structure. */\r
+ mbi = (multiboot_info_t *) addr;\r
+\r
+ /* Is the command line passed? */\r
+ if (CHECK_FLAG (mbi->flags, 2))\r
+ if (print_values != 0)\r
+ g_printf (" cmdline = %s\n\r", (char *) mbi->cmdline);\r
+\r
+ /* Print out the flags. */\r
+ if (print_values != 0)\r
+ g_printf (" flags = 0x%08x\n\r", (unsigned) mbi->flags);\r
+\r
+ /* Are mem_* valid? */\r
+ if (CHECK_FLAG (mbi->flags, 0))\r
+ if (print_values != 0)\r
+ g_printf (" mem_lower = %u KB, mem_upper = %u KB\n\r",\r
+ (unsigned) mbi->mem_lower, (unsigned) mbi->mem_upper);\r
+\r
+ /* Is boot_device valid? */\r
+ if (CHECK_FLAG (mbi->flags, 1))\r
+ if (print_values != 0)\r
+ g_printf (" boot_device = 0x%08x\n\r", (unsigned) mbi->boot_device);\r
+\r
+ if (CHECK_FLAG (mbi->flags, 3))\r
+ {\r
+ module_t *mod;\r
+ int i;\r
+ if (print_values != 0)\r
+ g_printf (" mods_count = %d, mods_addr = 0x%08x\n\r",\r
+ (int) mbi->mods_count, (int) mbi->mods_addr);\r
+ for (i = 0, mod = (module_t *) mbi->mods_addr;\r
+ i < (int)mbi->mods_count;\r
+ i++, mod++)\r
+ {\r
+ if (print_values != 0)\r
+ g_printf (" mod_start = 0x%08x, mod_end = 0x%08x, cmdline = %s\n\r",\r
+ (unsigned) mod->mod_start,\r
+ (unsigned) mod->mod_end,\r
+ (char *) mod->string);\r
+ }\r
+ }\r
+\r
+ /* Bits 4 and 5 are mutually exclusive! */\r
+ if (CHECK_FLAG (mbi->flags, 4) && CHECK_FLAG (mbi->flags, 5))\r
+ {\r
+ if (print_values != 0)\r
+ g_printf (" Both bits 4 and 5 are set.\n\r");\r
+ }\r
+ else\r
+ {\r
+ /* Is the symbol table of a.out valid? */\r
+ if (CHECK_FLAG (mbi->flags, 4))\r
+ {\r
+ aout_symbol_table_t *multiboot_aout_sym = &(mbi->u.aout_sym);\r
+ if (print_values != 0)\r
+ g_printf (" multiboot_aout_symbol_table: tabsize = 0x%08x, "\r
+ "strsize = 0x%08x, addr = 0x%08x\n\r",\r
+ (unsigned) multiboot_aout_sym->tabsize,\r
+ (unsigned) multiboot_aout_sym->strsize,\r
+ (unsigned) multiboot_aout_sym->addr);\r
+ }\r
+\r
+ /* Is the section header table of ELF valid? */\r
+ if (CHECK_FLAG (mbi->flags, 5))\r
+ {\r
+ elf_section_header_table_t *multiboot_elf_sec = &(mbi->u.elf_sec);\r
+ if (print_values != 0)\r
+ g_printf (" multiboot_elf_sec: num = %u, size = 0x%08x,"\r
+ " addr = 0x%08x, shndx = 0x%04x\n\r",\r
+ (unsigned) multiboot_elf_sec->num, (unsigned) multiboot_elf_sec->size,\r
+ (unsigned) multiboot_elf_sec->addr, (unsigned) multiboot_elf_sec->shndx);\r
+ }\r
+\r
+ /* Are mmap_* valid? */\r
+ if (CHECK_FLAG (mbi->flags, 6))\r
+ {\r
+ memory_map_t *mmap;\r
+ if (print_values != 0)\r
+ g_printf (" mmap_addr = 0x%08x, mmap_length = 0x%08x\n\r",\r
+ (unsigned) mbi->mmap_addr, (unsigned) mbi->mmap_length);\r
+ for (mmap = (memory_map_t *) mbi->mmap_addr;\r
+ (unsigned long) mmap < mbi->mmap_addr + mbi->mmap_length;\r
+ mmap = (memory_map_t *) ((unsigned long) mmap\r
+ + mmap->size + sizeof (mmap->size)))\r
+ {\r
+ if (print_values != 0)\r
+ g_printf (" size = 0x%08x, base_addr = 0x%04x%04x,"\r
+ " length = 0x%04x%04x, type = 0x%04x\n\r",\r
+ (unsigned) mmap->size,\r
+ (uint16_t) mmap->base_addr_high,\r
+ (uint16_t)mmap->base_addr_low,\r
+ (uint16_t)mmap->length_high,\r
+ (uint16_t)mmap->length_low,\r
+ (unsigned) mmap->type);\r
+ }\r
+ }\r
+\r
+ if (print_values != 0)\r
+ {\r
+ g_printf(DEFAULT_SCREEN_COLOR);\r
+ g_printf ("\n\r Press any key to continue.\n\r");\r
+ while (ucGalileoGetchar() == 0)\r
+ {\r
+ __asm volatile( "NOP" );\r
+ }\r
+ }\r
+ main();\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/*------------------------------------------------------------------------\r
+ * 8259 PIC initialization and support code\r
+ *------------------------------------------------------------------------\r
+ */\r
+ void vInitialize8259Chips(void)\r
+ {\r
+ /* Set interrupt mask */\r
+ uint16_t IRQMask = 0xffff;\r
+ outb(IMR1, (uint8_t) (IRQMask & 0xff));\r
+ outb(IMR2, (uint8_t) ((IRQMask >> 8) & 0xff));\r
+\r
+ /* Initialise the 8259A interrupt controllers */\r
+\r
+ /* Master device */\r
+ outb(ICU1, 0x11); /* ICW1: icw4 needed */\r
+ outb(ICU1+1, 0x20); /* ICW2: base ivec 32 */\r
+ outb(ICU1+1, 0x4); /* ICW3: cascade on irq2 */\r
+ outb(ICU1+1, 0x1); /* ICW4: buf. master, 808x mode */\r
+\r
+ /* Slave device */\r
+ outb(ICU2, 0x11); /* ICW1: icw4 needed */\r
+ outb(ICU2+1, 0x28); /* ICW2: base ivec 40 */\r
+ outb(ICU2+1, 0x2); /* ICW3: slave on irq2 */\r
+ outb(ICU2+1, 0xb); /* ICW4: buf. slave, 808x mode */\r
+\r
+ vMicroSecondDelay (100);\r
+\r
+ /* always read ISR */\r
+ outb(ICU1, 0xb); /* OCW3: set ISR on read */\r
+ outb(ICU2, 0xb); /* OCW3: set ISR on read */\r
+\r
+ /* Set interrupt mask - leave bit 2 enabled for IC cascade */\r
+ IRQMask = 0xfffb;\r
+ outb(IMR1, (uint8_t) (IRQMask & 0xff));\r
+ outb(IMR2, (uint8_t) ((IRQMask >> 8) & 0xff));\r
+ }\r
+ /*-----------------------------------------------------------*/\r
+\r
+ void vClearIRQMask(uint8_t IRQNumber)\r
+ {\r
+ if( ( IRQNumber > 31 ) && ( IRQNumber < 48 ) )\r
+ {\r
+ usIRQMask &= ~( 1 << (IRQNumber - 32 ) );\r
+ usIRQMask &= 0xfffb; // bit 2 is slave cascade\r
+ usIRQMask |= 0x0200; // bit 14 is reserved\r
+ outb(IMR1, (uint8_t) (usIRQMask & 0xff));\r
+ outb(IMR2, (uint8_t) ((usIRQMask >> 8) & 0xff));\r
+ }\r
+ }\r
+ /*-----------------------------------------------------------*/\r
+\r
+ void vSetIRQMask(uint8_t IRQNumber)\r
+ {\r
+ if( ( IRQNumber > 31 ) && ( IRQNumber < 48 ) )\r
+ {\r
+ usIRQMask |= ( 1 << (IRQNumber - 32 ) );\r
+ usIRQMask &= 0xfffb; // bit 2 is slave cascade\r
+ usIRQMask |= 0x0200; // bit 14 is reserved\r
+ outb(IMR1, (uint8_t) (usIRQMask & 0xff));\r
+ outb(IMR2, (uint8_t) ((usIRQMask >> 8) & 0xff));\r
+ }\r
+ }\r
+ /*-----------------------------------------------------------*/\r
+\r
+ /*-----------------------------------------------------------------------\r
+ * 82C54 PIT (programmable interval timer) initialization\r
+ *------------------------------------------------------------------------\r
+ */\r
+ void vInitializePIT(void)\r
+ {\r
+ /* Set the hardware clock: timer 0, 16-bit counter, rate */\r
+ /* generator mode, and counter runs in binary */\r
+ outb(CLKCNTL, 0x34);\r
+\r
+ /* Set the clock rate to 1.193 Mhz, this is 1 ms interrupt rate */\r
+ uint16_t intrate = 1193;\r
+ /* Must write LSB first, then MSB */\r
+ outb(CLKBASE, (char) (intrate & 0xff));\r
+ outb(CLKBASE, (char) ((intrate >> 8) & 0xff));\r
+ }\r
+ /*-----------------------------------------------------------*/\r
+\r
+ /*-----------------------------------------------------------------------\r
+ * LED support for main_blinky()\r
+ *------------------------------------------------------------------------\r
+ */\r
+ uint32_t ulBlinkLED(void)\r
+ {\r
+ if( uiLEDBlinkState == LED_OFF )\r
+ {\r
+ uiLEDBlinkState = LED_ON;\r
+ }\r
+ else\r
+ {\r
+ uiLEDBlinkState = LED_OFF;\r
+ }\r
+\r
+ vGalileoBlinkLEDUsingLegacyGPIO(uiLEDBlinkState);\r
+\r
+ return uiLEDBlinkState;\r
+ }\r
+ /*-----------------------------------------------------------*/\r
+\r
+ /*-----------------------------------------------------------------------\r
+ * Serial port initialization code\r
+ *------------------------------------------------------------------------\r
+ */\r
+ static void vInitializeGalileoUART(uint32_t portnumber)\r
+ {\r
+ volatile uint8_t divisor = 24;\r
+ volatile uint8_t output_data = 0x3 & 0xFB & 0xF7;\r
+ volatile uint8_t input_data = 0;\r
+ volatile uint8_t lcr = 0;\r
+\r
+ if (portnumber == DEBUG_SERIAL_PORT)\r
+ UART_PCI_Base = MMIO_PCI_ADDRESS(0, 20, 5, 0);\r
+ else\r
+ UART_PCI_Base = MMIO_PCI_ADDRESS(0, 20, 1, 0);\r
+\r
+ uint32_t base = mem_read(UART_PCI_Base, 0x10, 4);\r
+ UART_MMIO_Base = base;\r
+\r
+ mem_write(base, R_UART_SCR, 1, 0xAB);\r
+\r
+ mem_write(base, R_UART_LCR, 1, output_data | B_UARY_LCR_DLAB);\r
+\r
+ mem_write(base, R_UART_BAUD_HIGH, 1, (uint8_t)(divisor >> 8));\r
+ mem_write(base, R_UART_BAUD_LOW, 1, (uint8_t)(divisor & 0xff));\r
+\r
+ mem_write(base, R_UART_LCR, 1, output_data);\r
+\r
+ mem_write(base, R_UART_FCR, 1, (uint8_t)(B_UARY_FCR_TRFIFIE |\r
+ B_UARY_FCR_RESETRF | B_UARY_FCR_RESETTF | 0x30));\r
+\r
+ input_data = mem_read(base, R_UART_MCR, 1);\r
+ input_data |= BIT1;\r
+ input_data &= ~BIT5;\r
+ mem_write(base, R_UART_MCR, 1, input_data);\r
+\r
+ lcr = mem_read(base, R_UART_LCR, 1);\r
+ mem_write(base, R_UART_LCR, 1, (uint8_t) (lcr & ~B_UARY_LCR_DLAB));\r
+\r
+ mem_write(base, R_UART_IER, 1, 0);\r
+ }\r
+ /*-----------------------------------------------------------*/\r
+\r
+ void vInitializeGalileoSerialPort(uint32_t portnumber)\r
+ {\r
+ if( bGalileoSerialPortInitialized == FALSE )\r
+ {\r
+ /* Initialise for 115200, 8, 1, none and no handshaking */\r
+ vInitializeGalileoUART(portnumber);\r
+ bGalileoSerialPortInitialized = TRUE;\r
+ }\r
+ }\r
+ /*-----------------------------------------------------------*/\r
+\r
+ /*-----------------------------------------------------------------------\r
+ * Serial port support functions\r
+ *------------------------------------------------------------------------\r
+ */\r
+ void vGalileoPrintc(char c)\r
+ {\r
+ if (bGalileoSerialPortInitialized)\r
+ {\r
+ while((mem_read(UART_MMIO_Base, R_UART_LSR, 1) & B_UART_LSR_TXRDY) == 0);\r
+ mem_write(UART_MMIO_Base, R_UART_BAUD_THR, 1, c);\r
+ }\r
+ }\r
+ /*-----------------------------------------------------------*/\r
+\r
+ uint8_t ucGalileoGetchar()\r
+ {\r
+ uint8_t c = 0;\r
+ if (bGalileoSerialPortInitialized)\r
+ {\r
+ if((mem_read(UART_MMIO_Base, R_UART_LSR, 1) & B_UART_LSR_RXRDY) != 0)\r
+ c = mem_read(UART_MMIO_Base, R_UART_BAUD_THR, 1);\r
+ }\r
+ return c;\r
+ }\r
+ /*-----------------------------------------------------------*/\r
+\r
+ void vGalileoPuts(const char *string)\r
+ {\r
+ if (bGalileoSerialPortInitialized)\r
+ {\r
+ while(*string)\r
+ vGalileoPrintc(*string++);\r
+ }\r
+ }\r
+ /*-----------------------------------------------------------*/\r
--- /dev/null
+/*--------------------------------------------------------------------\r
+ Copyright(c) 2015 Intel Corporation. All rights reserved.\r
+\r
+ Redistribution and use in source and binary forms, with or without\r
+ modification, are permitted provided that the following conditions\r
+ are met:\r
+\r
+ * Redistributions of source code must retain the above copyright\r
+ notice, this list of conditions and the following disclaimer.\r
+ * Redistributions in binary form must reproduce the above copyright\r
+ notice, this list of conditions and the following disclaimer in\r
+ the documentation and/or other materials provided with the\r
+ distribution.\r
+ * Neither the name of Intel Corporation nor the names of its\r
+ contributors may be used to endorse or promote products derived\r
+ from this software without specific prior written permission.\r
+\r
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
+ "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
+ LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
+ A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\r
+ OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\r
+ SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\r
+ DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\r
+ THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ --------------------------------------------------------------------*/\r
+\r
+#ifndef __GALILEO_GEN_DEFS_H__\r
+#define __GALILEO_GEN_DEFS_H__\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/*-----------------------------------------------------------------------\r
+ * Any required includes\r
+ *------------------------------------------------------------------------\r
+ */\r
+#include <stdarg.h>\r
+#include "stdint.h"\r
+\r
+//---------------------------------------------------------------------\r
+// Printf prototype\r
+//---------------------------------------------------------------------\r
+extern int printf( const char *format, ... );\r
+extern int print( char **out, const char *format, va_list args );\r
+extern int sprintf(char *out, const char *format, ...);\r
+\r
+//---------------------------------------------------------------------\r
+// Prototypes (assembly language functions in startup.S)\r
+//---------------------------------------------------------------------\r
+extern void halt( void );\r
+extern int32_t inb( int32_t );\r
+extern int32_t inw( int32_t );\r
+extern int32_t inl( int32_t );\r
+extern int32_t outb( int32_t, int32_t );\r
+extern int32_t outw( int32_t, int32_t );\r
+extern int32_t outl( int32_t, int32_t) ;\r
+\r
+//---------------------------------------------------------------------\r
+// GP definitions\r
+//---------------------------------------------------------------------\r
+#ifndef TRUE\r
+ #define TRUE ( 1 )\r
+#endif\r
+\r
+#ifndef FALSE\r
+ #define FALSE ( 0 )\r
+#endif\r
+\r
+#ifndef true\r
+ #define true TRUE\r
+#endif\r
+\r
+#ifndef false\r
+ #define false FALSE\r
+#endif\r
+\r
+#ifndef OK\r
+ #define OK TRUE\r
+#endif\r
+\r
+//---------------------------------------------------------------------\r
+// General bit pattern definitions\r
+//---------------------------------------------------------------------\r
+#define BIT0 0x00000001U\r
+#define BIT1 0x00000002U\r
+#define BIT2 0x00000004U\r
+#define BIT3 0x00000008U\r
+#define BIT4 0x00000010U\r
+#define BIT5 0x00000020U\r
+#define BIT6 0x00000040U\r
+#define BIT7 0x00000080U\r
+#define BIT8 0x00000100U\r
+#define BIT9 0x00000200U\r
+\r
+//---------------------------------------------------------------------\r
+// MMIO support definitions\r
+//---------------------------------------------------------------------\r
+#define EC_BASE 0xE0000000 /* Base of MMConfig space */\r
+#define MMCONFIG_BASE EC_BASE\r
+#define MMIO_PCI_ADDRESS(bus,dev,fn,reg) ( \\r
+ (EC_BASE) + \\r
+ ((bus) << 20) + \\r
+ ((dev) << 15) + \\r
+ ((fn) << 12) + \\r
+ (reg))\r
+\r
+//---------------------------------------------------------------------\r
+// MMIO read/write/set/clear/modify macros\r
+//---------------------------------------------------------------------\r
+#define mem_read(base, offset, size) ({ \\r
+ volatile uint32_t a = (base) + (offset); \\r
+ volatile uint64_t v; \\r
+ switch (size) { \\r
+ case 1: \\r
+ v = (uint8_t)(*((uint8_t *)a)); \\r
+ break; \\r
+ case 2: \\r
+ v = (uint16_t)(*((uint16_t *)a)); \\r
+ break; \\r
+ case 4: \\r
+ v = (uint32_t)(*((uint32_t *)a)); \\r
+ break; \\r
+ case 8: \\r
+ v = (uint64_t)(*((uint64_t *)a)); \\r
+ break; \\r
+ default: \\r
+ halt(); \\r
+ } \\r
+ v; \\r
+})\r
+\r
+// No cache bypass necessary -- MTRRs should handle this\r
+#define mem_write(base, offset, size, value) { \\r
+ volatile uint32_t a = (base) + (offset); \\r
+ switch (size) { \\r
+ case 1: \\r
+ *((uint8_t *)a) = (uint8_t)(value); \\r
+ break; \\r
+ case 2: \\r
+ *((uint16_t *)a) = (uint16_t)(value); \\r
+ break; \\r
+ case 4: \\r
+ *((uint32_t *)a) = (uint32_t)(value); \\r
+ break; \\r
+ case 8: \\r
+ *((uint64_t *)a) = (uint64_t)(value); \\r
+ break; \\r
+ default: \\r
+ halt(); \\r
+ } \\r
+}\r
+\r
+#define mem_set(base, offset, size, smask) { \\r
+ volatile uint32_t a = (base) + (offset); \\r
+ switch (size) { \\r
+ case 1: \\r
+ *((uint8_t *)a) = (uint8_t)((*((uint8_t *)a)) | (smask)); \\r
+ break; \\r
+ case 2: \\r
+ *((uint16_t *)a) = (uint16_t)((*((uint16_t *)a)) | (smask)); \\r
+ break; \\r
+ case 4: \\r
+ *((uint32_t *)a) = (uint32_t)((*((uint32_t *)a)) | (smask)); \\r
+ break; \\r
+ case 8: \\r
+ *((uint64_t *)a) = (uint64_t)((*((uint64_t *)a)) | (smask)); \\r
+ break; \\r
+ } \\r
+}\r
+\r
+#define mem_clear(base, offset, size, cmask) { \\r
+ volatile uint32_t a = (base) + (offset); \\r
+ switch (size) { \\r
+ case 1: \\r
+ *((uint8_t *)a) = (uint8_t)((*((uint8_t *)a) & ~(cmask))); \\r
+ break; \\r
+ case 2: \\r
+ *((uint16_t *)a) = (uint16_t)((*((uint16_t *)a) & ~(cmask))); \\r
+ break; \\r
+ case 4: \\r
+ *((uint32_t *)a) = (uint32_t)((*((uint32_t *)a) & ~(cmask))); \\r
+ break; \\r
+ case 8: \\r
+ *((uint64_t *)a) = (uint64_t)((*((uint64_t *)a) & ~(cmask))); \\r
+ break; \\r
+ } \\r
+}\r
+\r
+#define mem_modify(base, offset, size, cmask, smask) { \\r
+ volatile uint32_t a = (base) + (offset); \\r
+ switch (size) { \\r
+ case 1: \\r
+ *((uint8_t *)a) = (uint8_t)((*((uint8_t *)a) & ~(cmask)) | (smask)); \\r
+ break; \\r
+ case 2: \\r
+ *((uint16_t *)a) = (uint16_t)((*((uint16_t *)a) & ~(cmask)) | (smask)); \\r
+ break; \\r
+ case 4: \\r
+ *((uint32_t *)a) = (uint32_t)((*((uint32_t *)a) & ~(cmask)) | (smask)); \\r
+ break; \\r
+ case 8: \\r
+ *((uint64_t *)a) = (uint64_t)((*((uint64_t *)a) & ~(cmask)) | (smask)); \\r
+ break; \\r
+ } \\r
+\r
+#ifdef __cplusplus\r
+ } /* extern C */\r
+#endif\r
+\r
+#endif /* GALILEO_GEN_DEFS */\r
+\r
--- /dev/null
+/*--------------------------------------------------------------------\r
+ Copyright(c) 2015 Intel Corporation. All rights reserved.\r
+\r
+ Redistribution and use in source and binary forms, with or without\r
+ modification, are permitted provided that the following conditions\r
+ are met:\r
+\r
+ * Redistributions of source code must retain the above copyright\r
+ notice, this list of conditions and the following disclaimer.\r
+ * Redistributions in binary form must reproduce the above copyright\r
+ notice, this list of conditions and the following disclaimer in\r
+ the documentation and/or other materials provided with the\r
+ distribution.\r
+ * Neither the name of Intel Corporation nor the names of its\r
+ contributors may be used to endorse or promote products derived\r
+ from this software without specific prior written permission.\r
+\r
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
+ "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
+ LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
+ A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\r
+ OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\r
+ SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\r
+ DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\r
+ THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ --------------------------------------------------------------------*/\r
+\r
+#ifndef __GALILEO_SUPPORT_H__\r
+#define __GALILEO_SUPPORT_H__\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+//---------------------------------------------------------------------\r
+// Any required includes\r
+//---------------------------------------------------------------------\r
+#include "FreeRTOS.h"\r
+#include "semphr.h"\r
+#include "galileo_gen_defs.h"\r
+#include "GPIO_I2C.h"\r
+#include "HPET.h"\r
+\r
+//---------------------------------------------------------------------\r
+// Application main entry point\r
+//---------------------------------------------------------------------\r
+extern int main( void );\r
+\r
+//---------------------------------------------------------------------\r
+// Defines for GDT\r
+//---------------------------------------------------------------------\r
+#define NGDE 8 /* Number of global descriptor entries */\r
+#define FLAGS_GRANULARITY 0x80\r
+#define FLAGS_SIZE 0x40\r
+#define FLAGS_SETTINGS ( FLAGS_GRANULARITY | FLAGS_SIZE )\r
+#define PAGE_SIZE 4096\r
+\r
+struct __attribute__ ((__packed__)) sd\r
+{\r
+ unsigned short sd_lolimit;\r
+ unsigned short sd_lobase;\r
+ unsigned char sd_midbase;\r
+ unsigned char sd_access;\r
+ unsigned char sd_hilim_fl;\r
+ unsigned char sd_hibase;\r
+};\r
+\r
+void setsegs();\r
+\r
+//---------------------------------------------------------------------\r
+// Debug serial port display update definitions\r
+//---------------------------------------------------------------------\r
+#define ANSI_CLEAR_SB "\e[3J"\r
+#define ANSI_CLEAR_LINE "\x1b[2K"\r
+#define ANSI_CLEAR_SCREEN "\x1b[2J"\r
+#define ANSI_COLOR_RED "\x1b[31m"\r
+#define ANSI_COLOR_GREEN "\x1b[32m"\r
+#define ANSI_COLOR_YELLOW "\x1b[33m"\r
+#define ANSI_COLOR_BLUE "\x1b[34m"\r
+#define ANSI_COLOR_MAGENTA "\x1b[35m"\r
+#define ANSI_COLOR_CYAN "\x1b[36m"\r
+#define ANSI_COLOR_RESET "\x1b[0m"\r
+#define ANSI_COLOR_WHITE ANSI_COLOR_RESET\r
+\r
+#define DEFAULT_SCREEN_COLOR ANSI_COLOR_YELLOW\r
+#define DEFAULT_BANNER_COLOR ANSI_COLOR_CYAN\r
+\r
+#define ANSI_HIDE_CURSOR "\x1b[?25l"\r
+#define ANSI_SHOW_CURSOR "\x1b[?25h"\r
+\r
+void ClearScreen(void);\r
+void MoveToScreenPosition(uint8_t row, uint8_t col);\r
+void UngatedMoveToScreenPosition(uint8_t row, uint8_t col);\r
+void SetScreenColor(const char *);\r
+void g_printf(const char *format, ...);\r
+void g_printf_rcc(uint8_t row, uint8_t col, const char *color, const char *format, ...);\r
+void vPrintBanner( void );\r
+\r
+//---------------------------------------------------------------------\r
+// 8259 PIC (programmable interrupt controller) definitions\r
+//---------------------------------------------------------------------\r
+#define IMR1 (0x21) /* Interrupt Mask Register #1 */\r
+#define IMR2 (0xA1) /* Interrupt Mask Register #2 */\r
+#define ICU1 (0x20)\r
+#define ICU2 (0xA0)\r
+#define EOI (0x20)\r
+\r
+void vInitialize8259Chips(void);\r
+void vClearIRQMask(uint8_t IRQNumber);\r
+void vSetIRQMask(uint8_t IRQNumber);\r
+\r
+//---------------------------------------------------------------------\r
+// 82C54 PIT (programmable interval timer) definitions\r
+//---------------------------------------------------------------------\r
+#define GATE_CONTROL 0x61\r
+#define CHANNEL2_DATA 0x42\r
+#define MODE_REGISTER 0x43\r
+#define ONESHOT_MODE 0xB2\r
+#define CLKBASE 0x40\r
+#define CLKCNTL MODE_REGISTER\r
+\r
+void vInitializePIT(void);\r
+\r
+//---------------------------------------------------------------------\r
+// LED support for main_blinky()\r
+//---------------------------------------------------------------------\r
+#define LED_ON ( 1 )\r
+#define LED_OFF ( 0 )\r
+\r
+uint32_t ulBlinkLED(void); /* Blink the LED and return the LED status. */\r
+\r
+//---------------------------------------------------------------------\r
+// Serial port support definitions\r
+//---------------------------------------------------------------------\r
+#define CLIENT_SERIAL_PORT 0\r
+#define DEBUG_SERIAL_PORT 1\r
+\r
+#define R_UART_THR 0\r
+#define R_UART_IER 0x04\r
+#define R_UART_BAUD_THR R_UART_THR\r
+#define R_UART_BAUD_LOW R_UART_BAUD_THR\r
+#define R_UART_BAUD_HIGH R_UART_IER\r
+#define R_UART_FCR 0x08\r
+#define B_UARY_FCR_TRFIFIE BIT0\r
+#define B_UARY_FCR_RESETRF BIT1\r
+#define B_UARY_FCR_RESETTF BIT2\r
+#define R_UART_LCR 0x0C\r
+#define B_UARY_LCR_DLAB BIT7\r
+#define R_UART_MCR 0x10\r
+#define R_UART_LSR 0x14\r
+#define B_UART_LSR_RXRDY BIT0\r
+#define B_UART_LSR_OE BIT1\r
+#define B_UART_LSR_PE BIT2\r
+#define B_UART_LSR_FE BIT3\r
+#define B_UART_LSR_BI BIT4\r
+#define B_UART_LSR_TXRDY BIT5\r
+#define B_UART_LSR_TEMT BIT6\r
+#define R_UART_MSR 0x18\r
+#define R_UART_SCR 0x1C\r
+\r
+void vInitializeGalileoSerialPort(uint32_t portnumber);\r
+void vGalileoPrintc(char c);\r
+uint8_t ucGalileoGetchar();\r
+void vGalileoPuts(const char *string);\r
+\r
+#ifdef __cplusplus\r
+ } /* extern C */\r
+#endif\r
+\r
+#endif /* __GALILEO_SUPPORT_H__ */\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V8.2.1 - Copyright (C) 2015 Real Time Engineers Ltd.\r
+ All rights reserved\r
+\r
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
+\r
+ ***************************************************************************\r
+ >>! NOTE: The modification to the GPL is included to allow you to !<<\r
+ >>! distribute a combined work that includes FreeRTOS without being !<<\r
+ >>! obliged to provide the source code for proprietary components !<<\r
+ >>! outside of the FreeRTOS kernel. !<<\r
+ ***************************************************************************\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+ FOR A PARTICULAR PURPOSE. Full license text is available on the following\r
+ link: http://www.freertos.org/a00114.html\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS provides completely free yet professionally developed, *\r
+ * robust, strictly quality controlled, supported, and cross *\r
+ * platform software that is more than just the market leader, it *\r
+ * is the industry's de facto standard. *\r
+ * *\r
+ * Help yourself get started quickly while simultaneously helping *\r
+ * to support the FreeRTOS project by purchasing a FreeRTOS *\r
+ * tutorial book, reference manual, or both: *\r
+ * http://www.FreeRTOS.org/Documentation *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading\r
+ the FAQ page "My application does not run, what could be wrong?". Have you\r
+ defined configASSERT()?\r
+\r
+ http://www.FreeRTOS.org/support - In return for receiving this top quality\r
+ embedded software for free we request you assist our global community by\r
+ participating in the support forum.\r
+\r
+ http://www.FreeRTOS.org/training - Investing in training allows your team to\r
+ be as productive as possible as early as possible. Now you can receive\r
+ FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
+ Ltd, and the world's leading authority on the world's leading RTOS.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
+\r
+ http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
+ Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
+ Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS\r
+ licenses offer ticketed support, indemnification and commercial middleware.\r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
+ mission critical applications that require provable dependability.\r
+\r
+ 1 tab == 4 spaces!\r
+*/\r
+\r
+#ifndef MATH_H\r
+#define MATH_H\r
+\r
+double fabs( double x );\r
+\r
+#endif /* math_h */\r
--- /dev/null
+/*\r
+ * Multiboot OS definitions and structures.\r
+ */\r
+\r
+#ifndef _MULTIBOOT_H_\r
+#define _MULTIBOOT_H_\r
+\r
+#define MULTIBOOT_HEADER_MAGIC 0x1BADB002\r
+#define MULTIBOOT_HEADER_FLAGS 0x00010003\r
+#define MULTIBOOT_BOOTLOADER_MAGIC 0x2BADB002\r
+\r
+typedef unsigned long t_32 ;\r
+\r
+typedef struct multiboot_header\r
+ {\r
+ t_32 Magic;\r
+ t_32 flags;\r
+ t_32 checksum;\r
+ t_32 header_addr;\r
+ t_32 load_addr;\r
+ t_32 load_end_addr;\r
+ t_32 bss_end_addr;\r
+ t_32 entry_addr;\r
+ t_32 video_mode;\r
+ t_32 width;\r
+ t_32 height;\r
+ t_32 depth;\r
+} multiboot_header_t;\r
+\r
+/* Symbol table for a.out. */\r
+typedef struct aout_symbol_table\r
+{\r
+ t_32 tabsize;\r
+ t_32 strsize;\r
+ t_32 addr;\r
+ t_32 reserved;\r
+} aout_symbol_table_t;\r
+\r
+/* Section header table for ELF. */\r
+typedef struct elf_section_header_table\r
+{\r
+ t_32 num;\r
+ t_32 size;\r
+ t_32 addr;\r
+ t_32 shndx;\r
+} elf_section_header_table_t;\r
+\r
+/* Multiboot information. */\r
+typedef struct multiboot_info\r
+{\r
+ t_32 flags;\r
+ t_32 mem_lower;\r
+ t_32 mem_upper;\r
+ t_32 boot_device;\r
+ t_32 cmdline;\r
+ t_32 mods_count;\r
+ t_32 mods_addr;\r
+ union\r
+ {\r
+ aout_symbol_table_t aout_sym;\r
+ elf_section_header_table_t elf_sec;\r
+ } u;\r
+ t_32 mmap_length;\r
+ t_32 mmap_addr;\r
+} multiboot_info_t;\r
+\r
+/* Module structure. */\r
+typedef struct module\r
+{\r
+ t_32 mod_start;\r
+ t_32 mod_end;\r
+ t_32 string;\r
+ t_32 reserved;\r
+} module_t;\r
+\r
+/* Memory map. Offset 0 is base_addr_low -no size. */\r
+typedef struct memory_map\r
+{\r
+ t_32 size;\r
+ t_32 base_addr_low;\r
+ t_32 base_addr_high;\r
+ t_32 length_low;\r
+ t_32 length_high;\r
+ t_32 type;\r
+} memory_map_t;\r
+\r
+#define CHECK_FLAG(flags,bit) ((flags) & (1 << (bit)))\r
+\r
+#endif /* _MULTIBOOT_H_ */\r
--- /dev/null
+/*\r
+ Copyright 2001, 2002 Georges Menie (www.menie.org)\r
+ stdarg version contributed by Christian Ettinger\r
+\r
+ This program is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU Lesser General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ This program is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU Lesser General Public License for more details.\r
+\r
+ You should have received a copy of the GNU Lesser General Public License\r
+ along with this program; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+*/\r
+\r
+#include <stdarg.h>\r
+#include "galileo_support.h"\r
+\r
+static void printchar(char **str, int c)\r
+{\r
+ if (str) {\r
+ **str = (char)c;\r
+ ++(*str);\r
+ }\r
+ else\r
+ {\r
+ vGalileoPrintc( c );\r
+ }\r
+}\r
+\r
+#define PAD_RIGHT 1\r
+#define PAD_ZERO 2\r
+\r
+static int prints(char **out, const char *string, int width, int pad)\r
+{\r
+ register int pc = 0, padchar = ' ';\r
+\r
+ if (width > 0) {\r
+ register int len = 0;\r
+ register const char *ptr;\r
+ for (ptr = string; *ptr; ++ptr) ++len;\r
+ if (len >= width) width = 0;\r
+ else width -= len;\r
+ if (pad & PAD_ZERO) padchar = '0';\r
+ }\r
+ if (!(pad & PAD_RIGHT)) {\r
+ for ( ; width > 0; --width) {\r
+ printchar (out, padchar);\r
+ ++pc;\r
+ }\r
+ }\r
+ for ( ; *string ; ++string) {\r
+ printchar (out, *string);\r
+ ++pc;\r
+ }\r
+ for ( ; width > 0; --width) {\r
+ printchar (out, padchar);\r
+ ++pc;\r
+ }\r
+\r
+ return pc;\r
+}\r
+\r
+/* the following should be enough for 32 bit int */\r
+#define PRINT_BUF_LEN 12\r
+\r
+static int printi(char **out, int i, int b, int sg, int width, int pad, int letbase)\r
+{\r
+ char print_buf[PRINT_BUF_LEN];\r
+ register char *s;\r
+ register int t, neg = 0, pc = 0;\r
+ register unsigned int u = (unsigned int)i;\r
+\r
+ if (i == 0) {\r
+ print_buf[0] = '0';\r
+ print_buf[1] = '\0';\r
+ return prints (out, print_buf, width, pad);\r
+ }\r
+\r
+ if (sg && b == 10 && i < 0) {\r
+ neg = 1;\r
+ u = (unsigned int)-i;\r
+ }\r
+\r
+ s = print_buf + PRINT_BUF_LEN-1;\r
+ *s = '\0';\r
+\r
+ while (u) {\r
+ t = (unsigned int)u % b;\r
+ if( t >= 10 )\r
+ t += letbase - '0' - 10;\r
+ *--s = (char)(t + '0');\r
+ u /= b;\r
+ }\r
+\r
+ if (neg) {\r
+ if( width && (pad & PAD_ZERO) ) {\r
+ printchar (out, '-');\r
+ ++pc;\r
+ --width;\r
+ }\r
+ else {\r
+ *--s = '-';\r
+ }\r
+ }\r
+\r
+ return pc + prints (out, s, width, pad);\r
+}\r
+\r
+int print( char **out, const char *format, va_list args )\r
+{\r
+ register int width, pad;\r
+ register int pc = 0;\r
+ char scr[2];\r
+\r
+ for (; *format != 0; ++format) {\r
+ if (*format == '%') {\r
+ ++format;\r
+ width = pad = 0;\r
+ if (*format == '\0') break;\r
+ if (*format == '%') goto out;\r
+ if (*format == '-') {\r
+ ++format;\r
+ pad = PAD_RIGHT;\r
+ }\r
+ while (*format == '0') {\r
+ ++format;\r
+ pad |= PAD_ZERO;\r
+ }\r
+ for ( ; *format >= '0' && *format <= '9'; ++format) {\r
+ width *= 10;\r
+ width += *format - '0';\r
+ }\r
+ if( *format == 's' ) {\r
+ register char *s = (char *)va_arg( args, int );\r
+ pc += prints (out, s?s:"(null)", width, pad);\r
+ continue;\r
+ }\r
+ if( *format == 'd' ) {\r
+ pc += printi (out, va_arg( args, int ), 10, 1, width, pad, 'a');\r
+ continue;\r
+ }\r
+ if( *format == 'x' ) {\r
+ pc += printi (out, va_arg( args, int ), 16, 0, width, pad, 'a');\r
+ continue;\r
+ }\r
+ if( *format == 'X' ) {\r
+ pc += printi (out, va_arg( args, int ), 16, 0, width, pad, 'A');\r
+ continue;\r
+ }\r
+ if( *format == 'u' ) {\r
+ pc += printi (out, va_arg( args, int ), 10, 0, width, pad, 'a');\r
+ continue;\r
+ }\r
+ if( *format == 'c' ) {\r
+ /* char are converted to int then pushed on the stack */\r
+ scr[0] = (char)va_arg( args, int );\r
+ scr[1] = '\0';\r
+ pc += prints (out, scr, width, pad);\r
+ continue;\r
+ }\r
+ }\r
+ else {\r
+ out:\r
+ printchar (out, *format);\r
+ ++pc;\r
+ }\r
+ }\r
+ if (out) **out = '\0';\r
+ va_end( args );\r
+ return pc;\r
+}\r
+\r
+int printf(const char *format, ...)\r
+{\r
+ va_list args;\r
+ \r
+ va_start( args, format );\r
+ return print( 0, format, args );\r
+}\r
+\r
+int sprintf(char *out, const char *format, ...)\r
+{\r
+ va_list args;\r
+ \r
+ va_start( args, format );\r
+ return print( &out, format, args );\r
+}\r
+\r
+\r
+int snprintf( char *buf, unsigned int count, const char *format, ... )\r
+{\r
+ va_list args;\r
+ \r
+ ( void ) count;\r
+ \r
+ va_start( args, format );\r
+ return print( &buf, format, args );\r
+}\r
+\r
+\r
+#ifdef TEST_PRINTF\r
+int main(void)\r
+{\r
+ char *ptr = "Hello world!";\r
+ char *np = 0;\r
+ int i = 5;\r
+ unsigned int bs = sizeof(int)*8;\r
+ int mi;\r
+ char buf[80];\r
+\r
+ mi = (1 << (bs-1)) + 1;\r
+ printf("%s\n", ptr);\r
+ printf("printf test\n");\r
+ printf("%s is null pointer\n", np);\r
+ printf("%d = 5\n", i);\r
+ printf("%d = - max int\n", mi);\r
+ printf("char %c = 'a'\n", 'a');\r
+ printf("hex %x = ff\n", 0xff);\r
+ printf("hex %02x = 00\n", 0);\r
+ printf("signed %d = unsigned %u = hex %x\n", -3, -3, -3);\r
+ printf("%d %s(s)%", 0, "message");\r
+ printf("\n");\r
+ printf("%d %s(s) with %%\n", 0, "message");\r
+ sprintf(buf, "justif: \"%-10s\"\n", "left"); printf("%s", buf);\r
+ sprintf(buf, "justif: \"%10s\"\n", "right"); printf("%s", buf);\r
+ sprintf(buf, " 3: %04d zero padded\n", 3); printf("%s", buf);\r
+ sprintf(buf, " 3: %-4d left justif.\n", 3); printf("%s", buf);\r
+ sprintf(buf, " 3: %4d right justif.\n", 3); printf("%s", buf);\r
+ sprintf(buf, "-3: %04d zero padded\n", -3); printf("%s", buf);\r
+ sprintf(buf, "-3: %-4d left justif.\n", -3); printf("%s", buf);\r
+ sprintf(buf, "-3: %4d right justif.\n", -3); printf("%s", buf);\r
+\r
+ return 0;\r
+}\r
+\r
+/*\r
+ * if you compile this file with\r
+ * gcc -Wall $(YOUR_C_OPTIONS) -DTEST_PRINTF -c printf.c\r
+ * you will get a normal warning:\r
+ * printf.c:214: warning: spurious trailing `%' in format\r
+ * this line is testing an invalid % at the end of the format string.\r
+ *\r
+ * this should display (on 32bit int machine) :\r
+ *\r
+ * Hello world!\r
+ * printf test\r
+ * (null) is null pointer\r
+ * 5 = 5\r
+ * -2147483647 = - max int\r
+ * char a = 'a'\r
+ * hex ff = ff\r
+ * hex 00 = 00\r
+ * signed -3 = unsigned 4294967293 = hex fffffffd\r
+ * 0 message(s)\r
+ * 0 message(s) with %\r
+ * justif: "left "\r
+ * justif: " right"\r
+ * 3: 0003 zero padded\r
+ * 3: 3 left justif.\r
+ * 3: 3 right justif.\r
+ * -3: -003 zero padded\r
+ * -3: -3 left justif.\r
+ * -3: -3 right justif.\r
+ */\r
+\r
+#endif\r
+\r
+\r
+/* To keep linker happy. */\r
+int write( int i, char* c, int n)\r
+{\r
+ (void)i;\r
+ (void)n;\r
+ (void)c;\r
+ return 0;\r
+}\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V8.2.1 - Copyright (C) 2015 Real Time Engineers Ltd.\r
+ All rights reserved\r
+\r
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
+\r
+ ***************************************************************************\r
+ >>! NOTE: The modification to the GPL is included to allow you to !<<\r
+ >>! distribute a combined work that includes FreeRTOS without being !<<\r
+ >>! obliged to provide the source code for proprietary components !<<\r
+ >>! outside of the FreeRTOS kernel. !<<\r
+ ***************************************************************************\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+ FOR A PARTICULAR PURPOSE. Full license text is available on the following\r
+ link: http://www.freertos.org/a00114.html\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS provides completely free yet professionally developed, *\r
+ * robust, strictly quality controlled, supported, and cross *\r
+ * platform software that is more than just the market leader, it *\r
+ * is the industry's de facto standard. *\r
+ * *\r
+ * Help yourself get started quickly while simultaneously helping *\r
+ * to support the FreeRTOS project by purchasing a FreeRTOS *\r
+ * tutorial book, reference manual, or both: *\r
+ * http://www.FreeRTOS.org/Documentation *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading\r
+ the FAQ page "My application does not run, what could be wrong?". Have you\r
+ defined configASSERT()?\r
+\r
+ http://www.FreeRTOS.org/support - In return for receiving this top quality\r
+ embedded software for free we request you assist our global community by\r
+ participating in the support forum.\r
+\r
+ http://www.FreeRTOS.org/training - Investing in training allows your team to\r
+ be as productive as possible as early as possible. Now you can receive\r
+ FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
+ Ltd, and the world's leading authority on the world's leading RTOS.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
+\r
+ http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
+ Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
+ Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS\r
+ licenses offer ticketed support, indemnification and commercial middleware.\r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
+ mission critical applications that require provable dependability.\r
+\r
+ 1 tab == 4 spaces!\r
+*/\r
+\r
+/* Set to 1 to enable functionality */\r
+#define __SHOW_KERNEL_PARAMS__ 0\r
+\r
+/* Local definitions boot loader */\r
+#define MULTIBOOT_SIGNATURE 0x2BADB002\r
+#define MULTIBOOT_BOOTINFO_MMAP 0x00000040\r
+\r
+/* Local definitions for GD table */\r
+#define GDT_ENTRIES 8\r
+#define GDT_ENTRY_SIZE 8\r
+#define GDT_BYTES (GDT_ENTRIES * GDT_ENTRY_SIZE)\r
+\r
+ /* Globals and externs */\r
+ .global _mboot_hdr\r
+ .global _start\r
+ .global _restart\r
+\r
+ .extern bootsign\r
+ .extern bootinfo\r
+\r
+ .extern __text_start\r
+ .extern __text_end\r
+ .extern __data_vma\r
+ .extern __data_lma\r
+ .extern __data_start\r
+ .extern __data_end\r
+ .extern __bss_start\r
+ .extern __bss_end\r
+ .extern __stack_for_main\r
+\r
+ .global __text_start\r
+ .global __text_end\r
+ .global __data_vma\r
+ .global __data_lma\r
+ .global __data_start\r
+ .global __data_end\r
+ .global __bss_start\r
+ .global __bss_end\r
+\r
+ .extern setsegs\r
+ .extern CRT_Init\r
+ .extern kernel_load_check\r
+ .extern main\r
+\r
+ /* Local constants for multiboot section */\r
+ .set ALIGN, 1<<0 /* align loaded modules on page boundaries */\r
+ .set MEMINFO, 1<<1 /* provide memory map */\r
+ .set MAGIC, 0x1BADB002 /* 'magic number' lets bootloader find the header */\r
+ .set FLAGS, ALIGN|MEMINFO /* this is the multiboot 'flag' field */\r
+ .set CHECKSUM, -(MAGIC + FLAGS) /* checksum of above */\r
+\r
+ /* Set-up GDT */\r
+ .section .data\r
+\r
+ .align 16\r
+ .globl gdt\r
+ gdt: .space GDT_BYTES\r
+ gdtr: .word (GDT_BYTES-1) /* sizeof _gdt -1 (in bytes) */\r
+ .long gdt /* global pointer to the gdt */\r
+\r
+ /* Start of application text */\r
+ .section .text.entry\r
+\r
+ /* Skip mb header */\r
+ jmp _start\r
+\r
+ .align 4\r
+ /* Multiboot header */\r
+ _mboot_hdr:\r
+ .long MAGIC /* offset = 0 */\r
+ .long FLAGS /* offset = 4 */\r
+ .long CHECKSUM /* offset = 8 */\r
+ .long _mboot_hdr /* should be header address - offset = 12 */\r
+ .long __text_start /* load address (start of text) - offset = 16 */\r
+ .long __bss_start /* load end address (end of data) - offset = 20*/\r
+ .long __bss_end /* bss end address - offset = 24*/\r
+ .long _start /* entry_addr - offset = 28*/\r
+\r
+ /* Start of executable code */\r
+ _start:\r
+\r
+ /* Store boot arguments */\r
+ movl %eax, bootsign\r
+ movl %ebx, bootinfo\r
+\r
+ /* Check to see if kernel is bootstrapped by grub */\r
+ cmpl $MULTIBOOT_SIGNATURE, %eax\r
+ jne _local_loop\r
+ testb $MULTIBOOT_BOOTINFO_MMAP, (%ebx)\r
+ je _local_loop\r
+\r
+ _restart:\r
+\r
+ /* Initialise the stack pointer */\r
+ movl $__stack_for_main, %esp\r
+\r
+ /* Reset EFLAGS. */\r
+ pushl $0\r
+ popf\r
+\r
+ /* Set up the global descriptor table */\r
+ call setsegs\r
+ lgdt gdtr\r
+ ljmp $0x8, $gdt1 /* CS descriptor 1 */\r
+ gdt1:\r
+ movl $0x10, %eax /* DS descriptor 2 */\r
+ movw %ax, %ds\r
+ movw %ax, %es\r
+ movw %ax, %fs\r
+ movw %ax, %gs\r
+ movl $0x18, %eax /* SS descriptor 3 */\r
+ movw %ax, %ss\r
+\r
+ /* Clear interrupt flag */\r
+ cli\r
+\r
+ /* Initialise platform */\r
+ call CRT_Init\r
+\r
+ /* Show kernel parameters and call main, or just call main */\r
+ #if (__SHOW_KERNEL_PARAMS__ == 1)\r
+ /*---------------------------------------------------------------------\r
+ On successful OS load EAX should contain 0x2BADB002\r
+ EBX should contain the physical address of multiboot info structure\r
+\r
+ Push the pointers to the multiboot information structure\r
+ and the magic number on the stack and check values returned\r
+ ----------------------------------------------------------------------*/\r
+ movl bootsign, %eax\r
+ movl bootinfo, %ebx\r
+ pushl %ebx /* Multiboot information */\r
+ pushl %eax /* Magic number */\r
+ call show_kernel_parameters\r
+ #else\r
+ /*---------------------------------------------------------------------\r
+ Call main() routine\r
+ ----------------------------------------------------------------------*/\r
+ call main\r
+ #endif\r
+\r
+ /* Should not get here, but just in case - loop forever */\r
+ cli\r
+ _local_loop:\r
+ hlt\r
+ jmp _local_loop\r
+\r
+ /*-------------------------------------------------------------------------\r
+ GLOBAL ASSEMBLY LANGUAGE ROUTINES\r
+ --------------------------------------------------------------------------*/\r
+\r
+ /* halt */\r
+ .globl halt\r
+ halt:\r
+ jmp halt\r
+ ret\r
+\r
+ /* inb */\r
+ .globl inb\r
+ inb: movl 4(%esp), %edx\r
+ xorl %eax, %eax # clr eax\r
+ inb %dx, %al\r
+ ret\r
+\r
+ /* inw */\r
+ .globl inw\r
+ inw: movl 4(%esp), %edx\r
+ xorl %eax, %eax # clr eax\r
+ inw %dx, %ax\r
+ ret\r
+\r
+ /* inl */\r
+ .globl inl\r
+ inl: movl 4(%esp), %edx\r
+ xorl %eax, %eax\r
+ inl %dx, %eax\r
+ ret\r
+\r
+ /* outb */\r
+ .globl outb\r
+ outb: movl 4(%esp), %edx\r
+ movl 8(%esp), %eax\r
+ outb %al, %dx\r
+ ret\r
+\r
+ /* outw */\r
+ .globl outw\r
+ outw: movl 4(%esp), %edx\r
+ movl 8(%esp), %eax\r
+ outw %ax, %dx\r
+ ret\r
+\r
+ /* outl */\r
+ .globl outl\r
+ outl: movl 4(%esp), %edx\r
+ movl 8(%esp), %eax\r
+ outl %eax, %dx\r
+ ret\r
+\r
+.end\r
--- /dev/null
+/*\r
+ FreeRTOS V8.2.1 - Copyright (C) 2015 Real Time Engineers Ltd.\r
+ All rights reserved\r
+\r
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
+\r
+ ***************************************************************************\r
+ >>! NOTE: The modification to the GPL is included to allow you to !<<\r
+ >>! distribute a combined work that includes FreeRTOS without being !<<\r
+ >>! obliged to provide the source code for proprietary components !<<\r
+ >>! outside of the FreeRTOS kernel. !<<\r
+ ***************************************************************************\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+ FOR A PARTICULAR PURPOSE. Full license text is available on the following\r
+ link: http://www.freertos.org/a00114.html\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS provides completely free yet professionally developed, *\r
+ * robust, strictly quality controlled, supported, and cross *\r
+ * platform software that is more than just the market leader, it *\r
+ * is the industry's de facto standard. *\r
+ * *\r
+ * Help yourself get started quickly while simultaneously helping *\r
+ * to support the FreeRTOS project by purchasing a FreeRTOS *\r
+ * tutorial book, reference manual, or both: *\r
+ * http://www.FreeRTOS.org/Documentation *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading\r
+ the FAQ page "My application does not run, what could be wrong?". Have you\r
+ defined configASSERT()?\r
+\r
+ http://www.FreeRTOS.org/support - In return for receiving this top quality\r
+ embedded software for free we request you assist our global community by\r
+ participating in the support forum.\r
+\r
+ http://www.FreeRTOS.org/training - Investing in training allows your team to\r
+ be as productive as possible as early as possible. Now you can receive\r
+ FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
+ Ltd, and the world's leading authority on the world's leading RTOS.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
+\r
+ http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
+ Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
+ Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS\r
+ licenses offer ticketed support, indemnification and commercial middleware.\r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
+ mission critical applications that require provable dependability.\r
+\r
+ 1 tab == 4 spaces!\r
+*/\r
+#ifndef FREERTOS_STDINT\r
+#define FREERTOS_STDINT\r
+\r
+/*******************************************************************************\r
+ * THIS IS NOT A FULL stdint.h IMPLEMENTATION - It only contains the definitions\r
+ * necessary to build the FreeRTOS code. It is provided to allow FreeRTOS to be\r
+ * built using compilers that do not provide their own stdint.h definition.\r
+ *\r
+ * To use this file:\r
+ *\r
+ * 1) Copy this file into the directory that contains your FreeRTOSConfig.h\r
+ * header file, as that directory will already be in the compilers include\r
+ * path.\r
+ *\r
+ * 2) Rename the copied file stdint.h.\r
+ *\r
+ */\r
+\r
+typedef signed char int8_t;\r
+typedef unsigned char uint8_t;\r
+typedef signed short int16_t;\r
+typedef unsigned short uint16_t;\r
+typedef signed long int32_t;\r
+typedef unsigned long uint32_t;\r
+typedef signed long long int64_t;\r
+typedef unsigned long long uint64_t;\r
+typedef uint32_t uintn_t;\r
+\r
+#endif /* FREERTOS_STDINT */\r
--- /dev/null
+/*\r
+ * Temporary file for use only during development when there are no library or\r
+ * header files.\r
+ */\r
+\r
+#ifndef STDIO_H\r
+#define STDIO_H\r
+\r
+int sprintf(char *out, const char *format, ...);\r
+\r
+#endif /* stdio_h */\r
--- /dev/null
+/*\r
+ * Temporary file for use only during development when there are no library or\r
+ * header files.\r
+ */\r
+\r
+\r
+#ifndef STDLIB_H\r
+#define STDLIB_H\r
+\r
+\r
+/*\r
+ * Extremely crude standard library implementations in lieu of having a C\r
+ * library.\r
+ */\r
+void *memset( void *pvDest, int iValue, unsigned long ulBytes );\r
+void *memcpy( void *pvDest, const void *pvSource, unsigned long ulBytes );\r
+int memcmp( const void *pvMem1, const void *pvMem2, unsigned long ulBytes );\r
+\r
+#endif /* STDLIB_H */\r
+\r
--- /dev/null
+\r
+/*\r
+ * Temporary file for use only during development when there are no library or\r
+ * header files.\r
+ */\r
+\r
+#ifndef STRING_H\r
+#define STRING_H\r
+\r
+//typedef unsigned long size_t;\r
+\r
+/*\r
+ * Extremely crude standard library implementations in lieu of having a C\r
+ * library.\r
+ */\r
+unsigned long strlen( const char* pcString );\r
+int strcmp( const char *pcString1, const char *pcString2 );\r
+void *memset( void *pvDest, int iValue, unsigned long ulBytes );\r
+void *memcpy( void *pvDest, const void *pvSource, unsigned long ulBytes );\r
+int memcmp( const void *pvMem1, const void *pvMem2, unsigned long ulBytes );\r
+#endif /* string_h */\r
--- /dev/null
+OUTPUT_FORMAT("elf32-i386")\r
+OUTPUT_ARCH(i386)\r
+ENTRY(_start)\r
+\r
+physbase = 0x00100000;\r
+\r
+SECTIONS\r
+{ \r
+ . = physbase;\r
+ . = ALIGN(4096);\r
+ .text :\r
+ {\r
+ __text_start = ABSOLUTE(.);\r
+ *(.text.entry)\r
+ *(.text)\r
+ *(.text.last)\r
+ *(.text.*)\r
+ . = ALIGN(4);\r
+ *(.rodata)\r
+ *( .rodata.*)\r
+ __text_end = ABSOLUTE(.);\r
+ . = ALIGN(4096);\r
+ }\r
+ \r
+ /* Read-write data (initialised) */\r
+ .data :\r
+ {\r
+ __data_start = ABSOLUTE(.);\r
+ __data_lma = LOADADDR(.data); \r
+ __data_vma = ABSOLUTE(.);\r
+ *(.data)\r
+ *(.data.*)\r
+ __data_end = ABSOLUTE(.);\r
+ . = ALIGN(4096);\r
+ }\r
+\r
+ /* Read-write data (uninitialised) */\r
+ .bss :\r
+ {\r
+ __bss_start = ABSOLUTE(.);\r
+ *(.bss)\r
+ *(COMMON)\r
+ __bss_end = ABSOLUTE(.);\r
+ . = ALIGN(1024);\r
+ }\r
+ \r
+ /* stack used before the scheduler starts */\r
+ .boot_stack :\r
+ {\r
+ /* 2K for the boot stack. This could be avoided by using the same RAM\r
+ as used by the FreeRTOS system/interrupt stack. */\r
+ . += 2048;\r
+ __stack_for_main = ABSOLUTE( . );\r
+ . = ALIGN(1024);\r
+ }\r
+\r
+ /*exception unwinding and source language information */\r
+ .eh_frame : { KEEP (*(.eh_frame)) . = ALIGN(4); }\r
+\r
+ /* function exports */\r
+ .drectve : { KEEP (*(.drectve)) }\r
+ \r
+ .comment 0 : { *(.comment) }\r
+\r
+}
\ No newline at end of file
--- /dev/null
+/*\r
+ FreeRTOS V8.2.1 - Copyright (C) 2015 Real Time Engineers Ltd.\r
+ All rights reserved\r
+\r
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
+\r
+ ***************************************************************************\r
+ >>! NOTE: The modification to the GPL is included to allow you to !<<\r
+ >>! distribute a combined work that includes FreeRTOS without being !<<\r
+ >>! obliged to provide the source code for proprietary components !<<\r
+ >>! outside of the FreeRTOS kernel. !<<\r
+ ***************************************************************************\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+ FOR A PARTICULAR PURPOSE. Full license text is available on the following\r
+ link: http://www.freertos.org/a00114.html\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS provides completely free yet professionally developed, *\r
+ * robust, strictly quality controlled, supported, and cross *\r
+ * platform software that is more than just the market leader, it *\r
+ * is the industry's de facto standard. *\r
+ * *\r
+ * Help yourself get started quickly while simultaneously helping *\r
+ * to support the FreeRTOS project by purchasing a FreeRTOS *\r
+ * tutorial book, reference manual, or both: *\r
+ * http://www.FreeRTOS.org/Documentation *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading\r
+ the FAQ page "My application does not run, what could be wrong?". Have you\r
+ defined configASSERT()?\r
+\r
+ http://www.FreeRTOS.org/support - In return for receiving this top quality\r
+ embedded software for free we request you assist our global community by\r
+ participating in the support forum.\r
+\r
+ http://www.FreeRTOS.org/training - Investing in training allows your team to\r
+ be as productive as possible as early as possible. Now you can receive\r
+ FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
+ Ltd, and the world's leading authority on the world's leading RTOS.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
+\r
+ http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
+ Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
+ Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS\r
+ licenses offer ticketed support, indemnification and commercial middleware.\r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
+ mission critical applications that require provable dependability.\r
+\r
+ 1 tab == 4 spaces!\r
+*/\r
+\r
+/******************************************************************************\r
+ * This project provides two demo applications. A simple blinky style project,\r
+ * and a more comprehensive test and demo application. The\r
+ * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting (defined in this file) is used to\r
+ * select between the two. The simply blinky demo is implemented and described\r
+ * in main_blinky.c. The more comprehensive test and demo application is\r
+ * implemented and described in main_full.c.\r
+ *\r
+ * This file implements the code that is not demo specific, including the\r
+ * hardware setup and FreeRTOS hook functions.\r
+ *\r
+ * ENSURE TO READ THE DOCUMENTATION PAGE FOR THIS PORT AND DEMO APPLICATION ON\r
+ * THE http://www.FreeRTOS.org WEB SITE FOR FULL INFORMATION ON USING THIS DEMO\r
+ * APPLICATION, AND ITS ASSOCIATE FreeRTOS ARCHITECTURE PORT!\r
+ * http://www.FreeRTOS.org/RTOS_Intel_Quark_Galileo_GCC.html\r
+ *\r
+ */\r
+\r
+/* Standard includes. */\r
+#include <stdlib.h>\r
+\r
+/* Scheduler include files. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "semphr.h"\r
+\r
+/* Standard demo includes, only necessary for the tick hook. */\r
+#include "TimerDemo.h"\r
+#include "QueueOverwrite.h"\r
+#include "EventGroupsDemo.h"\r
+#include "QueueSet.h"\r
+#include "TaskNotify.h"\r
+#include "IntQueue.h"\r
+\r
+/* Added Galileo serial support. */\r
+#include "galileo_support.h"\r
+\r
+/* Set to 1 to sit in a loop on start up, allowing a debugger to connect to the\r
+application before main() executes. */\r
+#define mainWAIT_FOR_DEBUG_CONNECTION 0\r
+\r
+/* Set mainCREATE_SIMPLE_BLINKY_DEMO_ONLY to one to run the simple blinky demo,\r
+or 0 to run the more comprehensive test and demo application. */\r
+#define mainCREATE_SIMPLE_BLINKY_DEMO_ONLY 1\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * main_blinky() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 1.\r
+ * main_full() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 0.\r
+ */\r
+#if( mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 )\r
+ extern void main_blinky( void );\r
+#else\r
+ extern void main_full( void );\r
+#endif /* mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 */\r
+\r
+/* Prototypes for functions called from asm start up code. */\r
+int main( void );\r
+void CRT_Init( void );\r
+\r
+/*\r
+ * Prototypes for the standard FreeRTOS callback/hook functions implemented\r
+ * within this file.\r
+ */\r
+void vApplicationMallocFailedHook( void );\r
+void vApplicationIdleHook( void );\r
+void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName );\r
+void vApplicationTickHook( void );\r
+\r
+/*\r
+ * Perform any hardware/peripheral related initialisation necessary to run the\r
+ * demo.\r
+ */\r
+static void prvSetupHardware( void );\r
+static void prvCalibrateLVTimer( void );\r
+\r
+/*\r
+ * If mainWAIT_FOR_DEBUG_CONNECTION is set to 1 then the following function will\r
+ * sit in a loop on start up, allowing a debugger to connect to the application\r
+ * before main() executes. If mainWAIT_FOR_DEBUG_CONNECTION is not set to 1\r
+ * then the following function does nothing.\r
+ */\r
+static void prvLoopToWaitForDebugConnection( void );\r
+\r
+/*\r
+ * Helper functions used when an assert is triggered. The first periodically\r
+ * displays an assert message, and the second clears the assert message when the\r
+ * function called by the configASSERT() macro is exited.\r
+ */\r
+static void prvDisplayAssertion( const char * pcFile, unsigned long ulLine );\r
+static void prvClearAssertionLine( void );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* See http://www.FreeRTOS.org/RTOS_Intel_Quark_Galileo_GCC.html for usage\r
+instructions. */\r
+int main( void )\r
+{\r
+ /* Optionally wait for a debugger to connect. */\r
+ prvLoopToWaitForDebugConnection();\r
+\r
+ /* Init the UART, GPIO, etc. */\r
+ prvSetupHardware();\r
+\r
+ /* The mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting is described at the top\r
+ of this file. */\r
+ #if( mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 )\r
+ {\r
+ g_printf_rcc( 3, 2, DEFAULT_SCREEN_COLOR, "Running main_blinky()." );\r
+ main_blinky();\r
+ }\r
+ #else\r
+ {\r
+ g_printf_rcc( 3, 2, DEFAULT_SCREEN_COLOR, "Running main_full()." );\r
+ main_full();\r
+ }\r
+ #endif\r
+\r
+ return 0;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationMallocFailedHook( void )\r
+{\r
+ /* Called if a call to pvPortMalloc() fails because there is insufficient\r
+ free memory available in the FreeRTOS heap. pvPortMalloc() is called\r
+ internally by FreeRTOS API functions that create tasks, queues, software\r
+ timers, and semaphores. The size of the FreeRTOS heap is set by the\r
+ configTOTAL_HEAP_SIZE configuration constant in FreeRTOSConfig.h.\r
+\r
+ Force an assert. */\r
+ configASSERT( xTaskGetTickCount() == 0 );\r
+ taskDISABLE_INTERRUPTS();\r
+ for( ;; );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName )\r
+{\r
+ ( void ) pcTaskName;\r
+ ( void ) pxTask;\r
+\r
+ /* Run time stack overflow checking is performed if\r
+ configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook\r
+ function is called if a stack overflow is detected.\r
+\r
+ Increase the size of the stack allocated to the offending task.\r
+\r
+ Force an assert. */\r
+ configASSERT( pxTask == NULL );\r
+ taskDISABLE_INTERRUPTS();\r
+ for( ;; );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationIdleHook( void )\r
+{\r
+ volatile unsigned long xFreeHeapSpace;\r
+\r
+ /* This is just a trivial example of an idle hook. It is called on each\r
+ cycle of the idle task. It must *NOT* attempt to block. In this case the\r
+ idle task just queries the amount of FreeRTOS heap that remains. See the\r
+ memory management section on the http://www.FreeRTOS.org web site for memory\r
+ management options. If there is a lot of heap memory free then the\r
+ configTOTAL_HEAP_SIZE value in FreeRTOSConfig.h can be reduced to free up\r
+ RAM. */\r
+ xFreeHeapSpace = xPortGetFreeHeapSize();\r
+\r
+ /* Remove compiler warning about xFreeHeapSpace being set but never used. */\r
+ ( void ) xFreeHeapSpace;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvDisplayAssertion( const char * pcFile, unsigned long ulLine )\r
+{\r
+extern void vMilliSecondDelay( uint32_t DelayTime );\r
+const uint32_t ul500ms = 500UL;\r
+\r
+ /* Display assertion file and line. Don't use the gated g_printf just in\r
+ the assert was triggered while the gating semaphore was taken. Always print\r
+ on line 23. */\r
+ UngatedMoveToScreenPosition( 23, 2 );\r
+ printf( ANSI_COLOR_RED );\r
+ printf( "ASSERT: File = %s, Line = %u\n\r", pcFile, ulLine );\r
+ printf( ANSI_COLOR_RESET );\r
+ printf( ANSI_SHOW_CURSOR );\r
+ vMilliSecondDelay( ul500ms );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvClearAssertionLine( void )\r
+{\r
+ UngatedMoveToScreenPosition( 23, 1 );\r
+ printf( ANSI_COLOR_RESET );\r
+ printf( ANSI_CLEAR_LINE );\r
+ printf( ANSI_HIDE_CURSOR );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vAssertCalled( const char * pcFile, unsigned long ulLine )\r
+{\r
+volatile uint32_t ul = 0;\r
+\r
+ ( void ) pcFile;\r
+ ( void ) ulLine;\r
+\r
+ taskENTER_CRITICAL();\r
+ {\r
+ /* Set ul to a non-zero value or press a key to step out of this\r
+ function in order to inspect the location of the assert(). */\r
+\r
+ /* Clear any pending key presses. */\r
+ while( ucGalileoGetchar() != 0 )\r
+ {\r
+ /* Nothing to do here - the key press is just discarded. */\r
+ }\r
+\r
+ do\r
+ {\r
+ prvDisplayAssertion(pcFile, ulLine);\r
+ } while ( ( ul == pdFALSE ) && ( ucGalileoGetchar() == 0 ) );\r
+\r
+ prvClearAssertionLine();\r
+ }\r
+ taskEXIT_CRITICAL();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationTickHook( void )\r
+{\r
+ #if( mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 0 )\r
+ {\r
+ extern void vTimerPeriodicISRTests( void );\r
+\r
+ /* The full demo includes a software timer demo/test that requires\r
+ prodding periodically from the tick interrupt. */\r
+ vTimerPeriodicISRTests();\r
+\r
+ /* Call the periodic queue overwrite from ISR demo. */\r
+ vQueueOverwritePeriodicISRDemo();\r
+\r
+ /* Call the periodic event group from ISR demo. */\r
+ vPeriodicEventGroupsProcessing();\r
+\r
+ /* Call the periodic queue set from ISR demo. */\r
+ vQueueSetAccessQueueSetFromISR();\r
+\r
+ /* Use task notifications from an interrupt. */\r
+ xNotifyTaskFromISR();\r
+ }\r
+ #endif\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvSetupHardware( void )\r
+{\r
+ ClearScreen();\r
+ printf( ANSI_COLOR_WHITE );\r
+\r
+ /* Initialise the serial port and GPIO. */\r
+ vInitializeGalileoSerialPort( DEBUG_SERIAL_PORT );\r
+ vGalileoInitializeGpioController();\r
+ vGalileoInitializeLegacyGPIO();\r
+\r
+ /* Initialise HPET interrupt(s) */\r
+ #if( ( mainCREATE_SIMPLE_BLINKY_DEMO_ONLY != 1 ) && ( hpetHPET_TIMER_IN_USE != 0 ) )\r
+ {\r
+ portDISABLE_INTERRUPTS();\r
+ vInitializeAllHPETInterrupts();\r
+ }\r
+ #endif\r
+\r
+ /* Setup the LED. */\r
+ vGalileoLegacyGPIOInitializationForLED();\r
+\r
+ /* Demonstrates how to calibrate LAPIC Timer. The calibration value\r
+ calculated here may get overwritten when the scheduler starts. */\r
+ prvCalibrateLVTimer();\r
+\r
+ /* Print RTOS loaded message. */\r
+ vPrintBanner();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvLoopToWaitForDebugConnection( void )\r
+{\r
+ /* Debug if define = 1. */\r
+ #if( mainWAIT_FOR_DEBUG_CONNECTION == 1 )\r
+ {\r
+ /* When using the debugger, set this value to pdFALSE, and the application\r
+ will sit in a loop at the top of main() to allow the debugger to attached\r
+ before the application starts running. Once attached, set\r
+ ulExitResetSpinLoop to a non-zero value to leave the loop. */\r
+ volatile uint32_t ulExitResetSpinLoop = pdFALSE;\r
+\r
+ /* Must initialize UART before anything will print. */\r
+ vInitializeGalileoSerialPort( DEBUG_SERIAL_PORT );\r
+\r
+ /* RTOS loaded message. */\r
+ vPrintBanner();\r
+\r
+ /* Output instruction message. */\r
+ MoveToScreenPosition( 3, 1 );\r
+ g_printf( DEFAULT_SCREEN_COLOR );\r
+ g_printf( " Waiting for JTAG connection.\n\n\r" );\r
+ g_printf( ANSI_COLOR_RESET );\r
+ g_printf( " Once connected, either set ulExitResetSpinLoop to a non-zero value,\n\r" );\r
+ g_printf( " or you can [PRESS ANY KEY] to start the debug session.\n\n\r" );\r
+ printf( ANSI_SHOW_CURSOR );\r
+\r
+ /* Use the debugger to set the ulExitResetSpinLoop to a non-zero value\r
+ or press a key to exit this loop, and step through the application. In\r
+ Eclipse, simple hover over the variable to see its value in a pop-over\r
+ box, then edit the value in the pop-over box. */\r
+ do\r
+ {\r
+ portNOP();\r
+\r
+ } while( ( ulExitResetSpinLoop == pdFALSE ) && ( ucGalileoGetchar() == 0 ) );\r
+ }\r
+ #endif\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void CRT_Init( void )\r
+{\r
+extern uint32_t __bss_start[];\r
+extern uint32_t __bss_end[];\r
+extern uint32_t __data_vma[];\r
+extern uint32_t __data_lma[];\r
+extern uint32_t __data_start[];\r
+extern uint32_t __data_end[];\r
+uint32_t x = 255;\r
+size_t xSize;\r
+\r
+ /* Zero out bss. */\r
+ xSize = ( ( size_t ) __bss_end ) - ( ( size_t ) __bss_start );\r
+ memset( ( void * ) __bss_start, 0x00, xSize );\r
+\r
+ /* Copy initialised variables. */\r
+ xSize = ( ( size_t ) __data_end ) - ( ( size_t ) __data_start );\r
+ memcpy( ( void * ) __data_vma, __data_lma, xSize );\r
+\r
+ /* Ensure no interrupts are pending. */\r
+ do\r
+ {\r
+ portAPIC_EOI = 0;\r
+ x--;\r
+ } while( x > 0 );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvCalibrateLVTimer( void )\r
+{\r
+uint32_t uiInitialTimerCounts, uiCalibratedTimerCounts;\r
+\r
+ /* Disable LAPIC Counter. */\r
+ portAPIC_LVT_TIMER = portAPIC_DISABLE;\r
+\r
+ /* Calibrate the LV Timer counts to ensure it matches the HPET timer over\r
+ extended periods. */\r
+ uiInitialTimerCounts = ( ( configCPU_CLOCK_HZ >> 4UL ) / configTICK_RATE_HZ );\r
+ uiCalibratedTimerCounts = uiCalibrateTimer( 0, hpetLVTIMER );\r
+\r
+ if( uiCalibratedTimerCounts != 0 )\r
+ {\r
+ uiInitialTimerCounts = uiCalibratedTimerCounts;\r
+ }\r
+\r
+ /* Set the interrupt frequency. */\r
+ portAPIC_TMRDIV = portAPIC_DIV_16;\r
+ portAPIC_TIMER_INITIAL_COUNT = uiInitialTimerCounts;\r
+\r
+ /* Enable LAPIC Counter. */\r
+ portAPIC_LVT_TIMER = portAPIC_TIMER_PERIODIC | portAPIC_TIMER_INT_VECTOR;\r
+\r
+ /* Sometimes needed. */\r
+ portAPIC_TMRDIV = portAPIC_DIV_16;\r
+}\r
--- /dev/null
+/*\r
+ FreeRTOS V8.2.1 - Copyright (C) 2015 Real Time Engineers Ltd.\r
+ All rights reserved\r
+\r
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
+\r
+ ***************************************************************************\r
+ >>! NOTE: The modification to the GPL is included to allow you to !<<\r
+ >>! distribute a combined work that includes FreeRTOS without being !<<\r
+ >>! obliged to provide the source code for proprietary components !<<\r
+ >>! outside of the FreeRTOS kernel. !<<\r
+ ***************************************************************************\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+ FOR A PARTICULAR PURPOSE. Full license text is available on the following\r
+ link: http://www.freertos.org/a00114.html\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS provides completely free yet professionally developed, *\r
+ * robust, strictly quality controlled, supported, and cross *\r
+ * platform software that is more than just the market leader, it *\r
+ * is the industry's de facto standard. *\r
+ * *\r
+ * Help yourself get started quickly while simultaneously helping *\r
+ * to support the FreeRTOS project by purchasing a FreeRTOS *\r
+ * tutorial book, reference manual, or both: *\r
+ * http://www.FreeRTOS.org/Documentation *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading\r
+ the FAQ page "My application does not run, what could be wrong?". Have you\r
+ defined configASSERT()?\r
+\r
+ http://www.FreeRTOS.org/support - In return for receiving this top quality\r
+ embedded software for free we request you assist our global community by\r
+ participating in the support forum.\r
+\r
+ http://www.FreeRTOS.org/training - Investing in training allows your team to\r
+ be as productive as possible as early as possible. Now you can receive\r
+ FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
+ Ltd, and the world's leading authority on the world's leading RTOS.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
+\r
+ http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
+ Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
+ Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS\r
+ licenses offer ticketed support, indemnification and commercial middleware.\r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
+ mission critical applications that require provable dependability.\r
+\r
+ 1 tab == 4 spaces!\r
+*/\r
+\r
+ .extern ulTopOfSystemStack\r
+ .extern ulInterruptNesting\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+.macro portFREERTOS_INTERRUPT_ENTRY\r
+\r
+ /* Save general purpose registers. */\r
+ pusha\r
+\r
+ /* If ulInterruptNesting is zero the rest of the task context will need\r
+ saving and a stack switch might be required. */\r
+ movl ulInterruptNesting, %eax\r
+ test %eax, %eax\r
+ jne 2f\r
+\r
+ /* Interrupts are not nested, so save the rest of the task context. */\r
+ .if configSUPPORT_FPU == 1\r
+\r
+ /* If the task has a buffer allocated to save the FPU context then\r
+ save the FPU context now. */\r
+ movl pucPortTaskFPUContextBuffer, %eax\r
+ test %eax, %eax\r
+ je 1f\r
+ fnsave ( %eax ) /* Save FLOP context into ucTempFPUBuffer array. */\r
+ fwait\r
+\r
+ 1:\r
+ /* Save the address of the FPU context, if any. */\r
+ push pucPortTaskFPUContextBuffer\r
+\r
+ .endif /* configSUPPORT_FPU */\r
+\r
+ /* Find the TCB. */\r
+ movl pxCurrentTCB, %eax\r
+\r
+ /* Stack location is first item in the TCB. */\r
+ movl %esp, (%eax)\r
+\r
+ /* Switch stacks. */\r
+ movl ulTopOfSystemStack, %esp\r
+ movl %esp, %ebp\r
+\r
+ 2:\r
+ /* Increment nesting count. */\r
+ add $1, ulInterruptNesting\r
+\r
+.endm\r
+/*-----------------------------------------------------------*/\r
+\r
+.macro portINTERRUPT_EPILOGUE\r
+\r
+ cli\r
+ sub $1, ulInterruptNesting\r
+\r
+ /* If the nesting has unwound to zero. */\r
+ movl ulInterruptNesting, %eax\r
+ test %eax, %eax\r
+ jne 2f\r
+\r
+ /* If a yield was requested then select a new TCB now. */\r
+ movl ulPortYieldPending, %eax\r
+ test %eax, %eax\r
+ je 1f\r
+ movl $0, ulPortYieldPending\r
+ call vTaskSwitchContext\r
+\r
+ 1:\r
+ /* Stack location is first item in the TCB. */\r
+ movl pxCurrentTCB, %eax\r
+ movl (%eax), %esp\r
+\r
+ .if configSUPPORT_FPU == 1\r
+\r
+ /* Restore address of task's FPU context buffer. */\r
+ pop pucPortTaskFPUContextBuffer\r
+\r
+ /* If the task has a buffer allocated in which its FPU context is saved,\r
+ then restore it now. */\r
+ movl pucPortTaskFPUContextBuffer, %eax\r
+ test %eax, %eax\r
+ je 1f\r
+ frstor ( %eax )\r
+ 1:\r
+ .endif\r
+\r
+ 2:\r
+ popa\r
+\r
+.endm\r
+/*-----------------------------------------------------------*/\r
+\r
+.macro portFREERTOS_INTERRUPT_EXIT\r
+\r
+ portINTERRUPT_EPILOGUE\r
+ /* EOI. */\r
+ movl $0x00, (0xFEE000B0)\r
+ iret\r
+\r
+.endm\r
--- /dev/null
+/*\r
+ FreeRTOS V8.2.1 - Copyright (C) 2015 Real Time Engineers Ltd.\r
+ All rights reserved\r
+\r
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
+\r
+ ***************************************************************************\r
+ >>! NOTE: The modification to the GPL is included to allow you to !<<\r
+ >>! distribute a combined work that includes FreeRTOS without being !<<\r
+ >>! obliged to provide the source code for proprietary components !<<\r
+ >>! outside of the FreeRTOS kernel. !<<\r
+ ***************************************************************************\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+ FOR A PARTICULAR PURPOSE. Full license text is available on the following\r
+ link: http://www.freertos.org/a00114.html\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS provides completely free yet professionally developed, *\r
+ * robust, strictly quality controlled, supported, and cross *\r
+ * platform software that is more than just the market leader, it *\r
+ * is the industry's de facto standard. *\r
+ * *\r
+ * Help yourself get started quickly while simultaneously helping *\r
+ * to support the FreeRTOS project by purchasing a FreeRTOS *\r
+ * tutorial book, reference manual, or both: *\r
+ * http://www.FreeRTOS.org/Documentation *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading\r
+ the FAQ page "My application does not run, what could be wrong?". Have you\r
+ defined configASSERT()?\r
+\r
+ http://www.FreeRTOS.org/support - In return for receiving this top quality\r
+ embedded software for free we request you assist our global community by\r
+ participating in the support forum.\r
+\r
+ http://www.FreeRTOS.org/training - Investing in training allows your team to\r
+ be as productive as possible as early as possible. Now you can receive\r
+ FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
+ Ltd, and the world's leading authority on the world's leading RTOS.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
+\r
+ http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
+ Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
+ Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS\r
+ licenses offer ticketed support, indemnification and commercial middleware.\r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
+ mission critical applications that require provable dependability.\r
+\r
+ 1 tab == 4 spaces!\r
+*/\r
+\r
+/* Standard includes. */\r
+#include <limits.h>\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 )\r
+ /* Check the configuration. */\r
+ #if( configMAX_PRIORITIES > 32 )\r
+ #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.\r
+ #endif\r
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */\r
+\r
+#if( configISR_STACK_SIZE < ( configMINIMAL_STACK_SIZE * 2 ) )\r
+ #warning configISR_STACK_SIZE is probably too small!\r
+#endif /* ( configISR_STACK_SIZE < configMINIMAL_STACK_SIZE * 2 ) */\r
+\r
+#if( ( configMAX_API_CALL_INTERRUPT_PRIORITY > portMAX_PRIORITY ) || ( configMAX_API_CALL_INTERRUPT_PRIORITY < 2 ) )\r
+ #error configMAX_API_CALL_INTERRUPT_PRIORITY must be between 2 and 15\r
+#endif\r
+\r
+/* A critical section is exited when the critical section nesting count reaches\r
+this value. */\r
+#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 )\r
+\r
+/* Tasks are not created with a floating point context, but can be given a\r
+floating point context after they have been created. A variable is stored as\r
+part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task\r
+does not have an FPU context, or any other value if the task does have an FPU\r
+context. */\r
+#define portNO_FLOATING_POINT_CONTEXT ( ( StackType_t ) 0 )\r
+\r
+/* Only the IF bit is set so tasks start with interrupts enabled. */\r
+#define portINITIAL_EFLAGS ( 0x200UL )\r
+\r
+/* Error interrupts are at the highest priority vectors. */\r
+#define portAPIC_LVT_ERROR_VECTOR ( 0xfe )\r
+#define portAPIC_SPURIOUS_INT_VECTOR ( 0xff )\r
+\r
+/* EFLAGS bits. */\r
+#define portEFLAGS_IF ( 0x200UL )\r
+\r
+/* FPU context size if FSAVE is used. */\r
+#define portFPU_CONTEXT_SIZE_BYTES 108\r
+\r
+/* The expected size of each entry in the IDT. Used to check structure packing\r
+ is set correctly. */\r
+#define portEXPECTED_IDT_ENTRY_SIZE 8\r
+\r
+/* Default flags setting for entries in the IDT. */\r
+#define portIDT_FLAGS ( 0x8E )\r
+\r
+/* This is the lowest possible ISR vector available to application code. */\r
+#define portAPIC_MIN_ALLOWABLE_VECTOR ( 0x20 )\r
+\r
+/* If configASSERT() is defined then the system stack is filled with this value\r
+to allow for a crude stack overflow check. */\r
+#define portSTACK_WORD ( 0xecececec )\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Starts the first task executing.\r
+ */\r
+extern void vPortStartFirstTask( void );\r
+\r
+/*\r
+ * Used to catch tasks that attempt to return from their implementing function.\r
+ */\r
+static void prvTaskExitError( void );\r
+\r
+/*\r
+ * Complete one descriptor in the IDT.\r
+ */\r
+static void prvSetInterruptGate( uint8_t ucNumber, ISR_Handler_t pxHandlerFunction, uint8_t ucFlags );\r
+\r
+/*\r
+ * The default handler installed in each IDT position.\r
+ */\r
+extern void vPortCentralInterruptWrapper( void );\r
+\r
+/*\r
+ * Handler for portYIELD().\r
+ */\r
+extern void vPortYieldCall( void );\r
+\r
+/*\r
+ * Configure the APIC to generate the RTOS tick.\r
+ */\r
+static void prvSetupTimerInterrupt( void );\r
+\r
+/*\r
+ * Tick interrupt handler.\r
+ */\r
+extern void vPortTimerHandler( void );\r
+\r
+/*\r
+ * Check an interrupt vector is not too high, too low, in use by FreeRTOS, or\r
+ * already in use by the application.\r
+ */\r
+static BaseType_t prvCheckValidityOfVectorNumber( uint32_t ulVectorNumber );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* A variable is used to keep track of the critical section nesting. This\r
+variable must be initialised to a non zero value to ensure interrupts don't\r
+inadvertently become unmasked before the scheduler starts. It is set to zero\r
+before the first task starts executing. */\r
+volatile uint32_t ulCriticalNesting = 9999UL;\r
+\r
+/* A structure used to map the various fields of an IDT entry into separate\r
+structure members. */\r
+struct IDTEntry\r
+{\r
+ uint16_t usISRLow; /* Low 16 bits of handler address. */\r
+ uint16_t usSegmentSelector; /* Flat model means this is not changed. */\r
+ uint8_t ucZero; /* Must be set to zero. */\r
+ uint8_t ucFlags; /* Flags for this entry. */\r
+ uint16_t usISRHigh; /* High 16 bits of handler address. */\r
+} __attribute__( ( packed ) );\r
+typedef struct IDTEntry IDTEntry_t;\r
+\r
+\r
+/* Use to pass the location of the IDT to the CPU. */\r
+struct IDTPointer\r
+{\r
+ uint16_t usTableLimit;\r
+ uint32_t ulTableBase; /* The address of the first entry in xInterruptDescriptorTable. */\r
+} __attribute__( ( __packed__ ) );\r
+typedef struct IDTPointer IDTPointer_t;\r
+\r
+/* The IDT itself. */\r
+static __attribute__ ( ( aligned( 32 ) ) ) IDTEntry_t xInterruptDescriptorTable[ portNUM_VECTORS ];\r
+\r
+#if ( configUSE_COMMON_INTERRUPT_ENTRY_POINT == 1 )\r
+\r
+ /* A table in which application defined interrupt handlers are stored. These\r
+ are called by the central interrupt handler if a common interrupt entry\r
+ point it used. */\r
+ static ISR_Handler_t xInterruptHandlerTable[ portNUM_VECTORS ] = { NULL };\r
+\r
+#endif /* configUSE_COMMON_INTERRUPT_ENTRY_POINT */\r
+\r
+#if ( configSUPPORT_FPU == 1 )\r
+\r
+ /* Saved as part of the task context. If pucPortTaskFPUContextBuffer is NULL\r
+ then the task does not have an FPU context. If pucPortTaskFPUContextBuffer is\r
+ not NULL then it points to a buffer into which the FPU context can be saved. */\r
+ uint8_t *pucPortTaskFPUContextBuffer __attribute__((used)) = pdFALSE;\r
+\r
+#endif /* configSUPPORT_FPU */\r
+\r
+/* The stack used by interrupt handlers. */\r
+static uint32_t ulSystemStack[ configISR_STACK_SIZE ] __attribute__((used)) = { 0 };\r
+\r
+/* Don't use the very top of the system stack so the return address\r
+appears as 0 if the debugger tries to unwind the stack. */\r
+volatile uint32_t ulTopOfSystemStack __attribute__((used)) = ( uint32_t ) &( ulSystemStack[ configISR_STACK_SIZE - 5 ] );\r
+\r
+/* If a yield is requested from an interrupt or from a critical section then\r
+the yield is not performed immediately, and ulPortYieldPending is set to pdTRUE\r
+instead to indicate the yield should be performed at the end of the interrupt\r
+when the critical section is exited. */\r
+volatile uint32_t ulPortYieldPending __attribute__((used)) = pdFALSE;\r
+\r
+/* Counts the interrupt nesting depth. Used to know when to switch to the\r
+interrupt/system stack and when to save/restore a complete context. */\r
+volatile uint32_t ulInterruptNesting __attribute__((used)) = 0;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * See header file for description.\r
+ */\r
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )\r
+{\r
+uint32_t ulCodeSegment;\r
+\r
+ /* Setup the initial stack as expected by the portFREERTOS_INTERRUPT_EXIT macro. */\r
+\r
+ *pxTopOfStack = 0x00;\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = 0x00;\r
+ pxTopOfStack--;\r
+\r
+ /* Parameters first. */\r
+ *pxTopOfStack = ( StackType_t ) pvParameters;\r
+ pxTopOfStack--;\r
+\r
+ /* There is nothing to return to so assert if attempting to use the return\r
+ address. */\r
+ *pxTopOfStack = ( StackType_t ) prvTaskExitError;\r
+ pxTopOfStack--;\r
+\r
+ /* iret used to start the task pops up to here. */\r
+ *pxTopOfStack = portINITIAL_EFLAGS;\r
+ pxTopOfStack--;\r
+\r
+ /* CS */\r
+ __asm volatile( "movl %%cs, %0" : "=r" ( ulCodeSegment ) );\r
+ *pxTopOfStack = ulCodeSegment;\r
+ pxTopOfStack--;\r
+\r
+ /* First instruction in the task. */\r
+ *pxTopOfStack = ( StackType_t ) pxCode;\r
+ pxTopOfStack--;\r
+\r
+ /* General purpose registers as expected by a POPA instruction. */\r
+ *pxTopOfStack = 0xEA;\r
+ pxTopOfStack--;\r
+\r
+ *pxTopOfStack = 0xEC;\r
+ pxTopOfStack--;\r
+\r
+ *pxTopOfStack = 0xED1; /* EDX */\r
+ pxTopOfStack--;\r
+\r
+ *pxTopOfStack = 0xEB1; /* EBX */\r
+ pxTopOfStack--;\r
+\r
+ /* Hole for ESP. */\r
+ pxTopOfStack--;\r
+\r
+ *pxTopOfStack = 0x00; /* EBP */\r
+ pxTopOfStack--;\r
+\r
+ *pxTopOfStack = 0xE5; /* ESI */\r
+ pxTopOfStack--;\r
+\r
+ *pxTopOfStack = 0xeeeeeeee; /* EDI */\r
+\r
+ #if ( configSUPPORT_FPU == 1 )\r
+ {\r
+ pxTopOfStack--;\r
+\r
+ /* Buffer for FPU context, which is initialised to NULL as tasks are not\r
+ created with an FPU context. */\r
+ *pxTopOfStack = portNO_FLOATING_POINT_CONTEXT;\r
+ }\r
+ #endif /* configSUPPORT_FPU */\r
+\r
+ return pxTopOfStack;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvSetInterruptGate( uint8_t ucNumber, ISR_Handler_t pxHandlerFunction, uint8_t ucFlags )\r
+{\r
+uint16_t usCodeSegment;\r
+uint32_t ulBase = ( uint32_t ) pxHandlerFunction;\r
+\r
+ xInterruptDescriptorTable[ ucNumber ].usISRLow = ( uint16_t ) ( ulBase & USHRT_MAX );\r
+ xInterruptDescriptorTable[ ucNumber ].usISRHigh = ( uint16_t ) ( ( ulBase >> 16UL ) & USHRT_MAX );\r
+\r
+ /* When the flat model is used the CS will never change. */\r
+ __asm volatile( "mov %%cs, %0" : "=r" ( usCodeSegment ) );\r
+ xInterruptDescriptorTable[ ucNumber ].usSegmentSelector = usCodeSegment;\r
+ xInterruptDescriptorTable[ ucNumber ].ucZero = 0;\r
+ xInterruptDescriptorTable[ ucNumber ].ucFlags = ucFlags;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortSetupIDT( void )\r
+{\r
+uint32_t ulNum;\r
+IDTPointer_t xIDT;\r
+\r
+ #if ( configUSE_COMMON_INTERRUPT_ENTRY_POINT == 1 )\r
+ {\r
+ for( ulNum = 0; ulNum < portNUM_VECTORS; ulNum++ )\r
+ {\r
+ /* If a handler has not already been installed on this vector. */\r
+ if( ( xInterruptDescriptorTable[ ulNum ].usISRLow == 0x00 ) && ( xInterruptDescriptorTable[ ulNum ].usISRHigh == 0x00 ) )\r
+ {\r
+ prvSetInterruptGate( ( uint8_t ) ulNum, vPortCentralInterruptWrapper, portIDT_FLAGS );\r
+ }\r
+ }\r
+ }\r
+ #endif /* configUSE_COMMON_INTERRUPT_ENTRY_POINT */\r
+\r
+ /* Set IDT address. */\r
+ xIDT.ulTableBase = ( uint32_t ) xInterruptDescriptorTable;\r
+ xIDT.usTableLimit = sizeof( xInterruptDescriptorTable ) - 1;\r
+\r
+ /* Set IDT in CPU. */\r
+ __asm volatile( "lidt %0" :: "m" (xIDT) );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvTaskExitError( void )\r
+{\r
+ /* A function that implements a task must not exit or attempt to return to\r
+ its caller as there is nothing to return to. If a task wants to exit it\r
+ should instead call vTaskDelete( NULL ).\r
+\r
+ Artificially force an assert() to be triggered if configASSERT() is\r
+ defined, then stop here so application writers can catch the error. */\r
+ configASSERT( ulCriticalNesting == ~0UL );\r
+ portDISABLE_INTERRUPTS();\r
+ for( ;; );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvSetupTimerInterrupt( void )\r
+{\r
+extern void vPortAPICErrorHandlerWrapper( void );\r
+extern void vPortAPICSpuriousHandler( void );\r
+\r
+ /* Initialise LAPIC to a well known state. */\r
+ portAPIC_LDR = 0xFFFFFFFF;\r
+ portAPIC_LDR = ( ( portAPIC_LDR & 0x00FFFFFF ) | 0x00000001 );\r
+ portAPIC_LVT_TIMER = portAPIC_DISABLE;\r
+ portAPIC_LVT_PERF = portAPIC_NMI;\r
+ portAPIC_LVT_LINT0 = portAPIC_DISABLE;\r
+ portAPIC_LVT_LINT1 = portAPIC_DISABLE;\r
+ portAPIC_TASK_PRIORITY = 0;\r
+\r
+ /* Install APIC timer ISR vector. */\r
+ prvSetInterruptGate( ( uint8_t ) portAPIC_TIMER_INT_VECTOR, vPortTimerHandler, portIDT_FLAGS );\r
+\r
+ /* Install API error handler. */\r
+ prvSetInterruptGate( ( uint8_t ) portAPIC_LVT_ERROR_VECTOR, vPortAPICErrorHandlerWrapper, portIDT_FLAGS );\r
+\r
+ /* Install Yield handler. */\r
+ prvSetInterruptGate( ( uint8_t ) portAPIC_YIELD_INT_VECTOR, vPortYieldCall, portIDT_FLAGS );\r
+\r
+ /* Install spurious interrupt vector. */\r
+ prvSetInterruptGate( ( uint8_t ) portAPIC_SPURIOUS_INT_VECTOR, vPortAPICSpuriousHandler, portIDT_FLAGS );\r
+\r
+ /* Enable the APIC, mapping the spurious interrupt at the same time. */\r
+ portAPIC_SPURIOUS_INT = portAPIC_SPURIOUS_INT_VECTOR | portAPIC_ENABLE_BIT;\r
+\r
+ /* Set timer error vector. */\r
+ portAPIC_LVT_ERROR = portAPIC_LVT_ERROR_VECTOR;\r
+\r
+ /* Set the interrupt frequency. */\r
+ portAPIC_TMRDIV = portAPIC_DIV_16;\r
+ portAPIC_TIMER_INITIAL_COUNT = ( ( configCPU_CLOCK_HZ >> 4UL ) / configTICK_RATE_HZ ) - 1UL;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+BaseType_t xPortStartScheduler( void )\r
+{\r
+BaseType_t xWord;\r
+\r
+ /* Some versions of GCC require the -mno-ms-bitfields command line option\r
+ for packing to work. */\r
+ configASSERT( sizeof( struct IDTEntry ) == portEXPECTED_IDT_ENTRY_SIZE );\r
+\r
+ /* Fill part of the system stack with a known value to help detect stack\r
+ overflow. A few zeros are left so GDB doesn't get confused unwinding\r
+ the stack. */\r
+ for( xWord = 0; xWord < configISR_STACK_SIZE - 20; xWord++ )\r
+ {\r
+ ulSystemStack[ xWord ] = portSTACK_WORD;\r
+ }\r
+\r
+ /* Initialise Interrupt Descriptor Table (IDT). */\r
+ vPortSetupIDT();\r
+\r
+ /* Initialise LAPIC and install system handlers. */\r
+ prvSetupTimerInterrupt();\r
+\r
+ /* Make sure the stack used by interrupts is aligned. */\r
+ ulTopOfSystemStack &= ~portBYTE_ALIGNMENT_MASK;\r
+\r
+ ulCriticalNesting = 0;\r
+\r
+ /* Enable LAPIC Counter.*/\r
+ portAPIC_LVT_TIMER = portAPIC_TIMER_PERIODIC | portAPIC_TIMER_INT_VECTOR;\r
+\r
+ /* Sometimes needed. */\r
+ portAPIC_TMRDIV = portAPIC_DIV_16;\r
+\r
+ /* Should not return from the following function as the scheduler will then\r
+ be executing the tasks. */\r
+ vPortStartFirstTask();\r
+\r
+ return 0;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortEndScheduler( void )\r
+{\r
+ /* Not implemented in ports where there is nothing to return to.\r
+ Artificially force an assert. */\r
+ configASSERT( ulCriticalNesting == 1000UL );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortEnterCritical( void )\r
+{\r
+ if( ulCriticalNesting == 0 )\r
+ {\r
+ #if( configMAX_API_CALL_INTERRUPT_PRIORITY == portMAX_PRIORITY )\r
+ {\r
+ __asm volatile( "cli" );\r
+ }\r
+ #else\r
+ {\r
+ portAPIC_TASK_PRIORITY = portMAX_API_CALL_PRIORITY;\r
+ configASSERT( portAPIC_TASK_PRIORITY == portMAX_API_CALL_PRIORITY );\r
+ }\r
+ #endif\r
+ }\r
+\r
+ /* Now interrupts are disabled ulCriticalNesting can be accessed\r
+ directly. Increment ulCriticalNesting to keep a count of how many times\r
+ portENTER_CRITICAL() has been called. */\r
+ ulCriticalNesting++;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortExitCritical( void )\r
+{\r
+ if( ulCriticalNesting > portNO_CRITICAL_NESTING )\r
+ {\r
+ /* Decrement the nesting count as the critical section is being\r
+ exited. */\r
+ ulCriticalNesting--;\r
+\r
+ /* If the nesting level has reached zero then all interrupt\r
+ priorities must be re-enabled. */\r
+ if( ulCriticalNesting == portNO_CRITICAL_NESTING )\r
+ {\r
+ /* Critical nesting has reached zero so all interrupt priorities\r
+ should be unmasked. */\r
+ #if( configMAX_API_CALL_INTERRUPT_PRIORITY == portMAX_PRIORITY )\r
+ {\r
+ __asm volatile( "sti" );\r
+ }\r
+ #else\r
+ {\r
+ portAPIC_TASK_PRIORITY = 0;\r
+\r
+ /* If a yield was pended from within the critical section then\r
+ perform the yield now. */\r
+ if( ulPortYieldPending != pdFALSE )\r
+ {\r
+ ulPortYieldPending = pdFALSE;\r
+ __asm volatile( portYIELD_INTERRUPT );\r
+ }\r
+ }\r
+ #endif\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+uint32_t ulPortSetInterruptMask( void )\r
+{\r
+volatile uint32_t ulOriginalMask;\r
+\r
+ /* Set mask to max syscall priority. */\r
+ #if( configMAX_API_CALL_INTERRUPT_PRIORITY == portMAX_PRIORITY )\r
+ {\r
+ /* Return whether interrupts were already enabled or not. Pop adjusts\r
+ the stack first. */\r
+ __asm volatile( "pushf \t\n"\r
+ "pop %0 \t\n"\r
+ "cli "\r
+ : "=rm" (ulOriginalMask) :: "memory" );\r
+\r
+ ulOriginalMask &= portEFLAGS_IF;\r
+ }\r
+ #else\r
+ {\r
+ /* Return original mask. */\r
+ ulOriginalMask = portAPIC_TASK_PRIORITY;\r
+ portAPIC_TASK_PRIORITY = portMAX_API_CALL_PRIORITY;\r
+ configASSERT( portAPIC_TASK_PRIORITY == portMAX_API_CALL_PRIORITY );\r
+ }\r
+ #endif\r
+\r
+ return ulOriginalMask;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortClearInterruptMask( uint32_t ulNewMaskValue )\r
+{\r
+ #if( configMAX_API_CALL_INTERRUPT_PRIORITY == portMAX_PRIORITY )\r
+ {\r
+ if( ulNewMaskValue != pdFALSE )\r
+ {\r
+ __asm volatile( "sti" );\r
+ }\r
+ }\r
+ #else\r
+ {\r
+ portAPIC_TASK_PRIORITY = ulNewMaskValue;\r
+ configASSERT( portAPIC_TASK_PRIORITY == ulNewMaskValue );\r
+ }\r
+ #endif\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+#if ( configSUPPORT_FPU == 1 )\r
+\r
+ void vPortTaskUsesFPU( void )\r
+ {\r
+ /* A task is registering the fact that it needs an FPU context. Allocate a\r
+ buffer into which the context can be saved. */\r
+ pucPortTaskFPUContextBuffer = ( uint8_t * ) pvPortMalloc( portFPU_CONTEXT_SIZE_BYTES );\r
+ configASSERT( pucPortTaskFPUContextBuffer );\r
+\r
+ /* Initialise the floating point registers. */\r
+ __asm volatile( "fninit" );\r
+ }\r
+\r
+#endif /* configSUPPORT_FPU */\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortAPICErrorHandler( void )\r
+{\r
+/* Variable to hold the APIC error status for viewing in the debugger. */\r
+volatile uint32_t ulErrorStatus = 0;\r
+\r
+ portAPIC_ERROR_STATUS = 0;\r
+ ulErrorStatus = portAPIC_ERROR_STATUS;\r
+ ( void ) ulErrorStatus;\r
+\r
+ /* Force an assert. */\r
+ configASSERT( ulCriticalNesting == ~0UL );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+#if( configUSE_COMMON_INTERRUPT_ENTRY_POINT == 1 )\r
+\r
+ void vPortCentralInterruptHandler( uint32_t ulVector )\r
+ {\r
+ if( ulVector < portNUM_VECTORS )\r
+ {\r
+ if( xInterruptHandlerTable[ ulVector ] != NULL )\r
+ {\r
+ ( xInterruptHandlerTable[ ulVector ] )();\r
+ }\r
+ }\r
+\r
+ /* Check for a system stack overflow. */\r
+ configASSERT( ulSystemStack[ 10 ] == portSTACK_WORD );\r
+ configASSERT( ulSystemStack[ 12 ] == portSTACK_WORD );\r
+ configASSERT( ulSystemStack[ 14 ] == portSTACK_WORD );\r
+ }\r
+\r
+#endif /* configUSE_COMMON_INTERRUPT_ENTRY_POINT */\r
+/*-----------------------------------------------------------*/\r
+\r
+#if ( configUSE_COMMON_INTERRUPT_ENTRY_POINT == 1 )\r
+\r
+ BaseType_t xPortRegisterCInterruptHandler( ISR_Handler_t pxHandler, uint32_t ulVectorNumber )\r
+ {\r
+ BaseType_t xReturn;\r
+\r
+ if( prvCheckValidityOfVectorNumber( ulVectorNumber ) != pdFAIL )\r
+ {\r
+ /* Save the handler passed in by the application in the vector number\r
+ passed in. The addresses are then called from the central interrupt\r
+ handler. */\r
+ xInterruptHandlerTable[ ulVectorNumber ] = pxHandler;\r
+\r
+ xReturn = pdPASS;\r
+ }\r
+\r
+ return xReturn;\r
+ }\r
+\r
+#endif /* configUSE_COMMON_INTERRUPT_ENTRY_POINT */\r
+/*-----------------------------------------------------------*/\r
+\r
+BaseType_t xPortInstallInterruptHandler( ISR_Handler_t pxHandler, uint32_t ulVectorNumber )\r
+{\r
+BaseType_t xReturn;\r
+\r
+ if( prvCheckValidityOfVectorNumber( ulVectorNumber ) != pdFAIL )\r
+ {\r
+ taskENTER_CRITICAL();\r
+ {\r
+ /* Update the IDT to include the application defined handler. */\r
+ prvSetInterruptGate( ( uint8_t ) ulVectorNumber, ( ISR_Handler_t ) pxHandler, portIDT_FLAGS );\r
+ }\r
+ taskEXIT_CRITICAL();\r
+\r
+ xReturn = pdPASS;\r
+ }\r
+\r
+ return xReturn;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static BaseType_t prvCheckValidityOfVectorNumber( uint32_t ulVectorNumber )\r
+{\r
+BaseType_t xReturn;\r
+\r
+ /* Check validity of vector number. */\r
+ if( ulVectorNumber >= portNUM_VECTORS )\r
+ {\r
+ /* Too high. */\r
+ xReturn = pdFAIL;\r
+ }\r
+ else if( ulVectorNumber < portAPIC_MIN_ALLOWABLE_VECTOR )\r
+ {\r
+ /* Too low. */\r
+ xReturn = pdFAIL;\r
+ }\r
+ else if( ulVectorNumber == portAPIC_TIMER_INT_VECTOR )\r
+ {\r
+ /* In use by FreeRTOS. */\r
+ xReturn = pdFAIL;\r
+ }\r
+ else if( ulVectorNumber == portAPIC_YIELD_INT_VECTOR )\r
+ {\r
+ /* In use by FreeRTOS. */\r
+ xReturn = pdFAIL;\r
+ }\r
+ else if( ulVectorNumber == portAPIC_LVT_ERROR_VECTOR )\r
+ {\r
+ /* In use by FreeRTOS. */\r
+ xReturn = pdFAIL;\r
+ }\r
+ else if( ulVectorNumber == portAPIC_SPURIOUS_INT_VECTOR )\r
+ {\r
+ /* In use by FreeRTOS. */\r
+ xReturn = pdFAIL;\r
+ }\r
+ else if( xInterruptHandlerTable[ ulVectorNumber ] != NULL )\r
+ {\r
+ /* Already in use by the application. */\r
+ xReturn = pdFAIL;\r
+ }\r
+ else\r
+ {\r
+ xReturn = pdPASS;\r
+ }\r
+\r
+ return xReturn;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vGenerateYieldInterrupt( void )\r
+{\r
+ __asm volatile( portYIELD_INTERRUPT );\r
+}\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V8.2.1 - Copyright (C) 2015 Real Time Engineers Ltd.\r
+ All rights reserved\r
+\r
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
+\r
+ ***************************************************************************\r
+ >>! NOTE: The modification to the GPL is included to allow you to !<<\r
+ >>! distribute a combined work that includes FreeRTOS without being !<<\r
+ >>! obliged to provide the source code for proprietary components !<<\r
+ >>! outside of the FreeRTOS kernel. !<<\r
+ ***************************************************************************\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+ FOR A PARTICULAR PURPOSE. Full license text is available on the following\r
+ link: http://www.freertos.org/a00114.html\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS provides completely free yet professionally developed, *\r
+ * robust, strictly quality controlled, supported, and cross *\r
+ * platform software that is more than just the market leader, it *\r
+ * is the industry's de facto standard. *\r
+ * *\r
+ * Help yourself get started quickly while simultaneously helping *\r
+ * to support the FreeRTOS project by purchasing a FreeRTOS *\r
+ * tutorial book, reference manual, or both: *\r
+ * http://www.FreeRTOS.org/Documentation *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading\r
+ the FAQ page "My application does not run, what could be wrong?". Have you\r
+ defined configASSERT()?\r
+\r
+ http://www.FreeRTOS.org/support - In return for receiving this top quality\r
+ embedded software for free we request you assist our global community by\r
+ participating in the support forum.\r
+\r
+ http://www.FreeRTOS.org/training - Investing in training allows your team to\r
+ be as productive as possible as early as possible. Now you can receive\r
+ FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
+ Ltd, and the world's leading authority on the world's leading RTOS.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
+\r
+ http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
+ Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
+ Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS\r
+ licenses offer ticketed support, indemnification and commercial middleware.\r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
+ mission critical applications that require provable dependability.\r
+\r
+ 1 tab == 4 spaces!\r
+*/\r
+\r
+.file "portASM.S"\r
+#include "FreeRTOSConfig.h"\r
+#include "ISR_Support.h"\r
+\r
+ .extern pxCurrentTCB\r
+ .extern vTaskSwitchContext\r
+ .extern vPortCentralInterruptHandler\r
+ .extern xTaskIncrementTick\r
+ .extern vPortAPICErrorHandler\r
+ .extern pucPortTaskFPUContextBuffer\r
+ .extern ulPortYieldPending\r
+\r
+ .global vPortStartFirstTask\r
+ .global vPortCentralInterruptWrapper\r
+ .global vPortAPICErrorHandlerWrapper\r
+ .global vPortTimerHandler\r
+ .global vPortYieldCall\r
+ .global vPortAPICSpuriousHandler\r
+\r
+ .text\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+.align 4\r
+.func vPortYieldCall\r
+vPortYieldCall:\r
+ /* Save general purpose registers. */\r
+ pusha\r
+\r
+ .if configSUPPORT_FPU == 1\r
+\r
+ /* If the task has a buffer allocated to save the FPU context then save\r
+ the FPU context now. */\r
+ movl pucPortTaskFPUContextBuffer, %eax\r
+ test %eax, %eax\r
+ je 1f\r
+ fnsave ( %eax )\r
+ fwait\r
+\r
+ 1:\r
+\r
+ /* Save the address of the FPU context, if any. */\r
+ push pucPortTaskFPUContextBuffer\r
+\r
+ .endif /* configSUPPORT_FPU */\r
+\r
+ /* Find the TCB. */\r
+ movl pxCurrentTCB, %eax\r
+\r
+ /* Stack location is first item in the TCB. */\r
+ movl %esp, (%eax)\r
+\r
+ call vTaskSwitchContext\r
+\r
+ /* Find the location of pxCurrentTCB again - a callee saved register could\r
+ be used in place of eax to prevent this second load, but that then relies\r
+ on the compiler and other asm code. */\r
+ movl pxCurrentTCB, %eax\r
+ movl (%eax), %esp\r
+\r
+ .if configSUPPORT_FPU == 1\r
+\r
+ /* Restore address of task's FPU context buffer. */\r
+ pop pucPortTaskFPUContextBuffer\r
+\r
+ /* If the task has a buffer allocated in which its FPU context is saved,\r
+ then restore it now. */\r
+ movl pucPortTaskFPUContextBuffer, %eax\r
+ test %eax, %eax\r
+ je 1f\r
+ frstor ( %eax )\r
+ 1:\r
+ .endif\r
+\r
+ popa\r
+ iret\r
+\r
+.endfunc\r
+/*-----------------------------------------------------------*/\r
+\r
+.align 4\r
+.func vPortStartFirstTask\r
+vPortStartFirstTask:\r
+\r
+ /* Find the TCB. */\r
+ movl pxCurrentTCB, %eax\r
+\r
+ /* Stack location is first item in the TCB. */\r
+ movl (%eax), %esp\r
+\r
+ /* Restore FPU context flag. */\r
+ .if configSUPPORT_FPU == 1\r
+\r
+ pop pucPortTaskFPUContextBuffer\r
+\r
+ .endif /* configSUPPORT_FPU */\r
+\r
+ /* Restore general purpose registers. */\r
+ popa\r
+ iret\r
+.endfunc\r
+/*-----------------------------------------------------------*/\r
+\r
+.align 4\r
+.func vPortAPICErrorHandlerWrapper\r
+vPortAPICErrorHandlerWrapper:\r
+ pusha\r
+ call vPortAPICErrorHandler\r
+ popa\r
+ /* EOI. */\r
+ movl $0x00, (0xFEE000B0)\r
+ iret\r
+.endfunc\r
+/*-----------------------------------------------------------*/\r
+\r
+.align 4\r
+.func vPortTimerHandler\r
+vPortTimerHandler:\r
+\r
+ /* Save general purpose registers. */\r
+ pusha\r
+\r
+ /* Interrupts are not nested, so save the rest of the task context. */\r
+ .if configSUPPORT_FPU == 1\r
+\r
+ /* If the task has a buffer allocated to save the FPU context then save the\r
+ FPU context now. */\r
+ movl pucPortTaskFPUContextBuffer, %eax\r
+ test %eax, %eax\r
+ je 1f\r
+ fnsave ( %eax ) /* Save FLOP context into ucTempFPUBuffer array. */\r
+ fwait\r
+\r
+ 1:\r
+ /* Save the address of the FPU context, if any. */\r
+ push pucPortTaskFPUContextBuffer\r
+\r
+ .endif /* configSUPPORT_FPU */\r
+\r
+ /* Find the TCB. */\r
+ movl pxCurrentTCB, %eax\r
+\r
+ /* Stack location is first item in the TCB. */\r
+ movl %esp, (%eax)\r
+\r
+ /* Switch stacks. */\r
+ movl ulTopOfSystemStack, %esp\r
+ movl %esp, %ebp\r
+\r
+ /* Increment nesting count. */\r
+ add $1, ulInterruptNesting\r
+\r
+ call xTaskIncrementTick\r
+\r
+ sti\r
+\r
+ /* Is a switch to another task required? */\r
+ test %eax, %eax\r
+ je _skip_context_switch\r
+ cli\r
+ call vTaskSwitchContext\r
+\r
+_skip_context_switch:\r
+ cli\r
+\r
+ /* Decrement the variable used to determine if a switch to a system\r
+ stack is necessary. */\r
+ sub $1, ulInterruptNesting\r
+\r
+ /* Stack location is first item in the TCB. */\r
+ movl pxCurrentTCB, %eax\r
+ movl (%eax), %esp\r
+\r
+ .if configSUPPORT_FPU == 1\r
+\r
+ /* Restore address of task's FPU context buffer. */\r
+ pop pucPortTaskFPUContextBuffer\r
+\r
+ /* If the task has a buffer allocated in which its FPU context is saved,\r
+ then restore it now. */\r
+ movl pucPortTaskFPUContextBuffer, %eax\r
+ test %eax, %eax\r
+ je 1f\r
+ frstor ( %eax )\r
+ 1:\r
+ .endif\r
+\r
+ popa\r
+\r
+ /* EOI. */\r
+ movl $0x00, (0xFEE000B0)\r
+ iret\r
+\r
+.endfunc\r
+/*-----------------------------------------------------------*/\r
+\r
+.if configUSE_COMMON_INTERRUPT_ENTRY_POINT == 1\r
+\r
+ .align 4\r
+ .func vPortCentralInterruptWrapper\r
+ vPortCentralInterruptWrapper:\r
+\r
+ portFREERTOS_INTERRUPT_ENTRY\r
+\r
+ movl $0xFEE00170, %eax /* Highest In Service Register (ISR) long word. */\r
+ movl $8, %ecx /* Loop counter. */\r
+\r
+ next_isr_long_word:\r
+ test %ecx, %ecx /* Loop counter reached 0? */\r
+ je wrapper_epilogue /* Looked at all ISR registers without finding a bit set. */\r
+ sub $1, %ecx /* Sub 1 from loop counter. */\r
+ movl (%eax), %ebx /* Load next ISR long word. */\r
+ sub $0x10, %eax /* Point to next ISR long word in case no bits are set in the current long word. */\r
+ test %ebx, %ebx /* Are there any bits set? */\r
+ je next_isr_long_word /* Look at next ISR long word if no bits were set. */\r
+ sti\r
+ bsr %ebx, %ebx /* A bit was set, which one? */\r
+ movl $32, %eax /* Destination operand for following multiplication. */\r
+ mul %ecx /* Calculate base vector for current register, 32 vectors per register. */\r
+ add %ebx, %eax /* Add bit offset into register to get final vector number. */\r
+ push %eax /* Vector number is function parameter. */\r
+ call vPortCentralInterruptHandler\r
+ pop %eax /* Remove parameter. */\r
+\r
+ wrapper_epilogue:\r
+ portFREERTOS_INTERRUPT_EXIT\r
+\r
+ .endfunc\r
+\r
+.endif /* configUSE_COMMON_INTERRUPT_ENTRY_POINT */\r
+/*-----------------------------------------------------------*/\r
+\r
+.align 4\r
+.func vPortAPISpuriousHandler\r
+vPortAPICSpuriousHandler:\r
+ iret\r
+\r
+.endfunc\r
+\r
+.end\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V8.2.1 - Copyright (C) 2015 Real Time Engineers Ltd.\r
+ All rights reserved\r
+\r
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
+\r
+ ***************************************************************************\r
+ >>! NOTE: The modification to the GPL is included to allow you to !<<\r
+ >>! distribute a combined work that includes FreeRTOS without being !<<\r
+ >>! obliged to provide the source code for proprietary components !<<\r
+ >>! outside of the FreeRTOS kernel. !<<\r
+ ***************************************************************************\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+ FOR A PARTICULAR PURPOSE. Full license text is available on the following\r
+ link: http://www.freertos.org/a00114.html\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS provides completely free yet professionally developed, *\r
+ * robust, strictly quality controlled, supported, and cross *\r
+ * platform software that is more than just the market leader, it *\r
+ * is the industry's de facto standard. *\r
+ * *\r
+ * Help yourself get started quickly while simultaneously helping *\r
+ * to support the FreeRTOS project by purchasing a FreeRTOS *\r
+ * tutorial book, reference manual, or both: *\r
+ * http://www.FreeRTOS.org/Documentation *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading\r
+ the FAQ page "My application does not run, what could be wrong?". Have you\r
+ defined configASSERT()?\r
+\r
+ http://www.FreeRTOS.org/support - In return for receiving this top quality\r
+ embedded software for free we request you assist our global community by\r
+ participating in the support forum.\r
+\r
+ http://www.FreeRTOS.org/training - Investing in training allows your team to\r
+ be as productive as possible as early as possible. Now you can receive\r
+ FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
+ Ltd, and the world's leading authority on the world's leading RTOS.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
+\r
+ http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
+ Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
+ Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS\r
+ licenses offer ticketed support, indemnification and commercial middleware.\r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
+ mission critical applications that require provable dependability.\r
+\r
+ 1 tab == 4 spaces!\r
+*/\r
+\r
+#ifndef PORTMACRO_H\r
+#define PORTMACRO_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/*-----------------------------------------------------------\r
+ * Port specific definitions.\r
+ *\r
+ * The settings in this file configure FreeRTOS correctly for the given hardware\r
+ * and compiler.\r
+ *\r
+ * These settings should not be altered.\r
+ *-----------------------------------------------------------\r
+ */\r
+\r
+/* Type definitions. */\r
+#define portCHAR char\r
+#define portFLOAT float\r
+#define portDOUBLE double\r
+#define portLONG long\r
+#define portSHORT short\r
+#define portSTACK_TYPE uint32_t\r
+#define portBASE_TYPE long\r
+\r
+typedef portSTACK_TYPE StackType_t;\r
+typedef long BaseType_t;\r
+typedef unsigned long UBaseType_t;\r
+\r
+typedef uint32_t TickType_t;\r
+#define portMAX_DELAY ( ( TickType_t ) 0xffffffffUL )\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Hardware specifics. */\r
+#define portSTACK_GROWTH ( -1 )\r
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )\r
+#define portBYTE_ALIGNMENT 32\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Task utilities. */\r
+\r
+/* The interrupt priority (for vectors 16 to 255) is determined using vector/16.\r
+The quotient is rounded to the nearest integer with 1 being the lowest priority\r
+and 15 is the highest. Therefore the following two interrupts are at the lowest\r
+priority. *NOTE 1* If the yield vector is changed then it must also be changed\r
+in the portYIELD_INTERRUPT definition immediately below. */\r
+#define portAPIC_TIMER_INT_VECTOR ( 0x21 )\r
+#define portAPIC_YIELD_INT_VECTOR ( 0x20 )\r
+\r
+/* Build yield interrupt instruction. */\r
+#define portYIELD_INTERRUPT "int $0x20"\r
+\r
+/* APIC register addresses. */\r
+#define portAPIC_EOI ( *( ( volatile uint32_t * ) 0xFEE000B0UL ) )\r
+\r
+/* APIC bit definitions. */\r
+#define portAPIC_ENABLE_BIT ( 1UL << 8UL )\r
+#define portAPIC_TIMER_PERIODIC ( 1UL << 17UL )\r
+#define portAPIC_DISABLE ( 1UL << 16UL )\r
+#define portAPIC_NMI ( 4 << 8)\r
+#define portAPIC_DIV_16 ( 0x03 )\r
+\r
+/* Define local API register addresses. */\r
+#define portAPIC_ID_REGISTER ( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0x20UL ) ) )\r
+#define portAPIC_SPURIOUS_INT ( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0xF0UL ) ) )\r
+#define portAPIC_LVT_TIMER ( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0x320UL ) ) )\r
+#define portAPIC_TIMER_INITIAL_COUNT ( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0x380UL ) ) )\r
+#define portAPIC_TIMER_CURRENT_COUNT ( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0x390UL ) ) )\r
+#define portAPIC_TASK_PRIORITY ( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0x80UL ) ) )\r
+#define portAPIC_LVT_ERROR ( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0x370UL ) ) )\r
+#define portAPIC_ERROR_STATUS ( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0x280UL ) ) )\r
+#define portAPIC_LDR ( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0xD0UL ) ) )\r
+#define portAPIC_TMRDIV ( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0x3E0UL ) ) )\r
+#define portAPIC_LVT_PERF ( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0x340UL ) ) )\r
+#define portAPIC_LVT_LINT0 ( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0x350UL ) ) )\r
+#define portAPIC_LVT_LINT1 ( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0x360UL ) ) )\r
+\r
+/* Don't yield if inside a critical section - instead hold the yield pending\r
+so it is performed when the critical section is exited. */\r
+#define portYIELD() \\r
+{ \\r
+extern volatile uint32_t ulCriticalNesting; \\r
+extern volatile uint32_t ulPortYieldPending; \\r
+ if( ulCriticalNesting != 0 ) \\r
+ { \\r
+ ulPortYieldPending = pdTRUE; \\r
+ } \\r
+ else \\r
+ { \\r
+ __asm volatile( portYIELD_INTERRUPT ); \\r
+ } \\r
+}\r
+\r
+/* Called at the end of an ISR that can cause a context switch - pend a yield if\r
+xSwithcRequired is not false. */\r
+#define portEND_SWITCHING_ISR( xSwitchRequired ) \\r
+{ \\r
+extern volatile uint32_t ulPortYieldPending; \\r
+ if( xSwitchRequired != pdFALSE ) \\r
+ { \\r
+ ulPortYieldPending = 1; \\r
+ } \\r
+}\r
+\r
+/* Same as portEND_SWITCHING_ISR() - take your pick which name to use. */\r
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )\r
+\r
+/*-----------------------------------------------------------\r
+ * Critical section control\r
+ *----------------------------------------------------------*/\r
+\r
+/* Critical sections for use in interrupts. */\r
+#define portSET_INTERRUPT_MASK_FROM_ISR() ulPortSetInterruptMask()\r
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vPortClearInterruptMask( x )\r
+\r
+extern void vPortEnterCritical( void );\r
+extern void vPortExitCritical( void );\r
+extern uint32_t ulPortSetInterruptMask( void );\r
+extern void vPortClearInterruptMask( uint32_t ulNewMaskValue );\r
+\r
+/* These macros do not globally disable/enable interrupts. They do mask off\r
+interrupts that have a priority below configMAX_API_CALL_INTERRUPT_PRIORITY. */\r
+#define portENTER_CRITICAL() vPortEnterCritical()\r
+#define portEXIT_CRITICAL() vPortExitCritical()\r
+#define portDISABLE_INTERRUPTS() __asm volatile( "cli" )\r
+#define portENABLE_INTERRUPTS() __asm volatile( "sti" )\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Task function macros as described on the FreeRTOS.org WEB site. These are\r
+not required for this port but included in case common demo code that uses these\r
+macros is used. */\r
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )\r
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )\r
+\r
+/* Architecture specific optimisations. */\r
+#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1\r
+\r
+ /* Store/clear the ready priorities in a bit map. */\r
+ #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) \\r
+ __asm volatile( "bsr %1, %0\n\t" \\r
+ :"=r"(uxTopPriority) : "rm"(uxReadyPriorities) : "cc" )\r
+\r
+ #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )\r
+ #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )\r
+\r
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */\r
+\r
+#define portNOP() __asm volatile( "NOP" )\r
+\r
+/*-----------------------------------------------------------\r
+ * Misc\r
+ *----------------------------------------------------------*/\r
+\r
+#define portNUM_VECTORS 256\r
+#define portMAX_PRIORITY 15\r
+typedef void ( *ISR_Handler_t ) ( void );\r
+\r
+/* Any task that uses the floating point unit MUST call vPortTaskUsesFPU()\r
+before any floating point instructions are executed. */\r
+#ifndef configSUPPORT_FPU\r
+ #define configSUPPORT_FPU 0\r
+#endif\r
+\r
+#if configSUPPORT_FPU == 1\r
+ void vPortTaskUsesFPU( void );\r
+ #define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU()\r
+#endif\r
+\r
+/* See the comments under the configUSE_COMMON_INTERRUPT_ENTRY_POINT definition\r
+below. */\r
+BaseType_t xPortRegisterCInterruptHandler( ISR_Handler_t pxHandler, uint32_t ulVectorNumber );\r
+BaseType_t xPortInstallInterruptHandler( ISR_Handler_t pxHandler, uint32_t ulVectorNumber );\r
+\r
+#ifndef configAPIC_BASE\r
+ /* configAPIC_BASE_ADDRESS sets the base address of the local APIC. It can\r
+ be overridden in FreeRTOSConfig.h should it not be constant. */\r
+ #define configAPIC_BASE 0xFEE00000UL\r
+#endif\r
+\r
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION\r
+ /* The FreeRTOS scheduling algorithm selects the task that will enter the\r
+ Running state. configUSE_PORT_OPTIMISED_TASK_SELECTION is used to set how\r
+ that is done.\r
+\r
+ If configUSE_PORT_OPTIMISED_TASK_SELECTION is set to 0 then the task to\r
+ enter the Running state is selected using a portable algorithm written in\r
+ C. This is the slowest method, but the algorithm does not restrict the\r
+ maximum number of unique RTOS task priorities that are available.\r
+\r
+ If configUSE_PORT_OPTIMISED_TASK_SELECTION is set to 1 then the task to\r
+ enter the Running state is selected using a single assembly instruction.\r
+ This is the fastest method, but restricts the maximum number of unique RTOS\r
+ task priorities to 32 (the same task priority can be assigned to any number\r
+ of RTOS tasks). */\r
+ #warning configUSE_PORT_OPTIMISED_TASK_SELECTION was not defined in FreeRTOSConfig.h and has been defaulted to 1\r
+ #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1\r
+#endif\r
+\r
+#ifndef configUSE_COMMON_INTERRUPT_ENTRY_POINT\r
+ /* There are two ways of implementing interrupt handlers:\r
+\r
+ 1) As standard C functions -\r
+\r
+ This method can only be used if configUSE_COMMON_INTERRUPT_ENTRY_POINT\r
+ is set to 1. The C function is installed using\r
+ xPortRegisterCInterruptHandler().\r
+\r
+ This is the simplest of the two methods but incurs a slightly longer\r
+ interrupt entry time.\r
+\r
+ 2) By using an assembly stub that wraps the handler in the FreeRTOS\r
+ portFREERTOS_INTERRUPT_ENTRY and portFREERTOS_INTERRUPT_EXIT macros.\r
+\r
+ This method can always be used. It is slightly more complex than\r
+ method 1 but benefits from a faster interrupt entry time. */\r
+ #warning config_USE_COMMON_INTERRUPT_ENTRY_POINT was not defined in FreeRTOSConfig.h and has been defaulted to 1.\r
+ #define configUSE_COMMON_INTERRUPT_ENTRY_POINT 1\r
+#endif\r
+\r
+#ifndef configISR_STACK_SIZE\r
+ /* Interrupt entry code will switch the stack in use to a dedicated system \r
+ stack.\r
+\r
+ configISR_STACK_SIZE defines the number of 32-bit values that can be stored\r
+ on the system stack, and must be large enough to hold a potentially nested\r
+ interrupt stack frame. */\r
+\r
+ #error configISE_STACK_SIZE was not defined in FreeRTOSConfig.h.\r
+#endif\r
+\r
+#ifndef configMAX_API_CALL_INTERRUPT_PRIORITY\r
+ /* Interrupt safe FreeRTOS functions (those that end in "FromISR" must not\r
+ be called from an interrupt that has a priority above that set by\r
+ configMAX_API_CALL_INTERRUPT_PRIORITY. */\r
+ #warning configMAX_API_CALL_INTERRUPT_PRIORITY was not defined in FreeRTOSConfig.h and has been defaulted to 10\r
+ #define configMAX_API_CALL_INTERRUPT_PRIORITY 10\r
+#endif\r
+\r
+#ifndef configSUPPORT_FPU\r
+ #warning configSUPPORT_FPU was not defined in FreeRTOSConfig.h and has been defaulted to 0\r
+ #define configSUPPORT_FPU 0\r
+#endif\r
+\r
+/* The value written to the task priority register to raise the interrupt mask\r
+to the maximum from which FreeRTOS API calls can be made. */\r
+#define portAPIC_PRIORITY_SHIFT ( 4UL )\r
+#define portAPIC_MAX_SUB_PRIORITY ( 0x0fUL )\r
+#define portMAX_API_CALL_PRIORITY ( ( configMAX_API_CALL_INTERRUPT_PRIORITY << portAPIC_PRIORITY_SHIFT ) | portAPIC_MAX_SUB_PRIORITY )\r
+\r
+/* Asserts if interrupt safe FreeRTOS functions are called from a priority\r
+above the max system call interrupt priority. */\r
+#define portAPIC_PROCESSOR_PRIORITY ( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0xA0UL ) ) )\r
+#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() configASSERT( ( portAPIC_PROCESSOR_PRIORITY ) <= ( portMAX_API_CALL_PRIORITY ) )\r
+\r
+#ifdef __cplusplus\r
+ } /* extern C */\r
+#endif\r
+\r
+#endif /* PORTMACRO_H */\r
+\r
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