Create an updated AVR32 UC3A project.

git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@1031 1d2547de-c912-0410-9cb9-b8ca96c0e9e2

diff --git a/Demo/AVR32_UC3A_GCC/.cproject b/Demo/AVR32_UC3A_GCC/.cproject
new file mode 100644 (file)
index 0000000..a21e6dc
--- /dev/null
+++ b/Demo/AVR32_UC3A_GCC/.cproject
@@ -0,0 +1,2137 @@
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diff --git a/Demo/AVR32_UC3A_GCC/.framework b/Demo/AVR32_UC3A_GCC/.framework
new file mode 100644 (file)
index 0000000..a413af2
--- /dev/null
+++ b/Demo/AVR32_UC3A_GCC/.framework
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+<?fileVersion 1.0.0?>
+<framework-data>
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diff --git a/Demo/AVR32_UC3A_GCC/.project b/Demo/AVR32_UC3A_GCC/.project
new file mode 100644 (file)
index 0000000..7660c46
--- /dev/null
+++ b/Demo/AVR32_UC3A_GCC/.project
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+                                       <value></value>\r
+                               </dictionary>\r
+                               <dictionary>\r
+                                       <key>org.eclipse.cdt.make.core.append_environment</key>\r
+                                       <value>true</value>\r
+                               </dictionary>\r
+                               <dictionary>\r
+                                       <key>org.eclipse.cdt.make.core.buildArguments</key>\r
+                                       <value></value>\r
+                               </dictionary>\r
+                               <dictionary>\r
+                                       <key>org.eclipse.cdt.make.core.buildCommand</key>\r
+                                       <value>make</value>\r
+                               </dictionary>\r
+                               <dictionary>\r
+                                       <key>org.eclipse.cdt.make.core.buildLocation</key>\r
+                                       <value>${workspace_loc:/FreeRTOS6/Debug}</value>\r
+                               </dictionary>\r
+                               <dictionary>\r
+                                       <key>org.eclipse.cdt.make.core.contents</key>\r
+                                       <value>org.eclipse.cdt.make.core.activeConfigSettings</value>\r
+                               </dictionary>\r
+                               <dictionary>\r
+                                       <key>org.eclipse.cdt.make.core.enableAutoBuild</key>\r
+                                       <value>false</value>\r
+                               </dictionary>\r
+                               <dictionary>\r
+                                       <key>org.eclipse.cdt.make.core.enableCleanBuild</key>\r
+                                       <value>true</value>\r
+                               </dictionary>\r
+                               <dictionary>\r
+                                       <key>org.eclipse.cdt.make.core.enableFullBuild</key>\r
+                                       <value>true</value>\r
+                               </dictionary>\r
+                               <dictionary>\r
+                                       <key>org.eclipse.cdt.make.core.stopOnError</key>\r
+                                       <value>true</value>\r
+                               </dictionary>\r
+                               <dictionary>\r
+                                       <key>org.eclipse.cdt.make.core.useDefaultBuildCmd</key>\r
+                                       <value>true</value>\r
+                               </dictionary>\r
+                       </arguments>\r
+               </buildCommand>\r
+               <buildCommand>\r
+                       <name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>\r
+                       <arguments>\r
+                       </arguments>\r
+               </buildCommand>\r
+       </buildSpec>\r
+       <natures>\r
+               <nature>com.atmel.avr32.core.nature</nature>\r
+               <nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>\r
+               <nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>\r
+               <nature>org.eclipse.cdt.core.cnature</nature>\r
+       </natures>\r
+</projectDescription>\r

diff --git a/Demo/AVR32_UC3A_GCC/.settings/com.atmel.avr32.debug.prefs b/Demo/AVR32_UC3A_GCC/.settings/com.atmel.avr32.debug.prefs
new file mode 100644 (file)
index 0000000..4008fbe
--- /dev/null
+++ b/Demo/AVR32_UC3A_GCC/.settings/com.atmel.avr32.debug.prefs
@@ -0,0 +1,4 @@
+#Wed Dec 02 11:26:33 GMT 2009\r
+Search.Terms=\r
+SelectedWatchables=\r
+eclipse.preferences.version=1\r

diff --git a/Demo/AVR32_UC3A_GCC/.settings/com.atmel.avr32.managedbuilder.prefs b/Demo/AVR32_UC3A_GCC/.settings/com.atmel.avr32.managedbuilder.prefs
new file mode 100644 (file)
index 0000000..e1e1f24
--- /dev/null
+++ b/Demo/AVR32_UC3A_GCC/.settings/com.atmel.avr32.managedbuilder.prefs
@@ -0,0 +1,6 @@
+#Sun Jun 13 13:55:07 BST 2010\r
+eclipse.preferences.version=1\r
+project.part.id=UC3A0512\r
+project.secured=false\r
+project.secured.flash=0\r
+project.secured.ram=0\r

diff --git a/Demo/AVR32_UC3A_GCC/Atmel_SW_Framework/BOARDS/EVK1100/evk1100.h b/Demo/AVR32_UC3A_GCC/Atmel_SW_Framework/BOARDS/EVK1100/evk1100.h
new file mode 100644 (file)
index 0000000..efca9a2
--- /dev/null
+++ b/Demo/AVR32_UC3A_GCC/Atmel_SW_Framework/BOARDS/EVK1100/evk1100.h
@@ -0,0 +1,330 @@
+/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */\r
+
+/*This file is prepared for Doxygen automatic documentation generation.*/\r
+/*! \file *********************************************************************\r
+ *\r
+ * \brief AT32UC3A EVK1100 board header file.\r
+ *\r
+ * This file contains definitions and services related to the features of the\r
+ * EVK1100 board rev. B and C.\r
+ *\r
+ * To use this board, define BOARD=EVK1100.\r
+ *\r
+ * - Compiler:           IAR EWAVR32 and GNU GCC for AVR32\r
+ * - Supported devices:  All AVR32 AT32UC3A devices can be used.\r
+ * - AppNote:\r
+ *\r
+ * \author               Atmel Corporation: http://www.atmel.com \n\r
+ *                       Support and FAQ: http://support.atmel.no/\r
+ *\r
+ ******************************************************************************/\r
+\r
+/* Copyright (c) 2009 Atmel Corporation. All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice, this\r
+ * list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an Atmel\r
+ * AVR product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\r
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\r
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\r
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE\r
+ *\r
+ */\r
+\r
+#ifndef _EVK1100_H_\r
+#define _EVK1100_H_\r
+\r
+#ifdef EVK1100_REVA\r
+#  include "evk1100_revA.h"\r
+#else\r
+\r
+#include "compiler.h"\r
+\r
+#ifdef __AVR32_ABI_COMPILER__ // Automatically defined when compiling for AVR32, not when assembling.\r
+#  include "led.h"\r
+#endif  // __AVR32_ABI_COMPILER__\r
+\r
+\r
+/*! \name Oscillator Definitions\r
+ */\r
+//! @{\r
+\r
+// RCOsc has no custom calibration by default. Set the following definition to\r
+// the appropriate value if a custom RCOsc calibration has been applied to your\r
+// part.\r
+//#define FRCOSC          AVR32_PM_RCOSC_FREQUENCY              //!< RCOsc frequency: Hz.\r
+\r
+#define FOSC32          32768                                 //!< Osc32 frequency: Hz.\r
+#define OSC32_STARTUP   AVR32_PM_OSCCTRL32_STARTUP_8192_RCOSC //!< Osc32 startup time: RCOsc periods.\r
+\r
+#define FOSC0           12000000                              //!< Osc0 frequency: Hz.\r
+#define OSC0_STARTUP    AVR32_PM_OSCCTRL0_STARTUP_2048_RCOSC  //!< Osc0 startup time: RCOsc periods.\r
+\r
+// Osc1 crystal is not mounted by default. Set the following definitions to the\r
+// appropriate values if a custom Osc1 crystal is mounted on your board.\r
+//#define FOSC1           12000000                              //!< Osc1 frequency: Hz.\r
+//#define OSC1_STARTUP    AVR32_PM_OSCCTRL1_STARTUP_2048_RCOSC  //!< Osc1 startup time: RCOsc periods.\r
+\r
+//! @}\r
+\r
+\r
+/*! \name SDRAM Definitions\r
+ */\r
+//! @{\r
+\r
+//! Part header file of used SDRAM(s).\r
+#define SDRAM_PART_HDR  "MT48LC16M16A2TG7E/mt48lc16m16a2tg7e.h"\r
+\r
+//! Data bus width to use the SDRAM(s) with (16 or 32 bits; always 16 bits on\r
+//! UC3).\r
+#define SDRAM_DBW       16\r
+\r
+//! @}\r
+\r
+\r
+/*! \name USB Definitions\r
+ */\r
+//! @{\r
+\r
+//! Multiplexed pin used for USB_ID: AVR32_USBB_USB_ID_x_x.\r
+//! To be selected according to the AVR32_USBB_USB_ID_x_x_PIN and\r
+//! AVR32_USBB_USB_ID_x_x_FUNCTION definitions from <avr32/uc3axxxx.h>.\r
+#define USB_ID                      AVR32_USBB_USB_ID_0_0\r
+\r
+//! Multiplexed pin used for USB_VBOF: AVR32_USBB_USB_VBOF_x_x.\r
+//! To be selected according to the AVR32_USBB_USB_VBOF_x_x_PIN and\r
+//! AVR32_USBB_USB_VBOF_x_x_FUNCTION definitions from <avr32/uc3axxxx.h>.\r
+#define USB_VBOF                    AVR32_USBB_USB_VBOF_0_1\r
+\r
+//! Active level of the USB_VBOF output pin.\r
+#define USB_VBOF_ACTIVE_LEVEL       LOW\r
+\r
+//! USB overcurrent detection pin.\r
+#define USB_OVERCURRENT_DETECT_PIN  AVR32_PIN_PX33\r
+\r
+//! @}\r
+\r
+\r
+//! GPIO connection of the MAC PHY PWR_DOWN/INT signal.\r
+#define MACB_INTERRUPT_PIN  AVR32_PIN_PA24\r
+\r
+\r
+//! Number of LEDs.\r
+#define LED_COUNT   8\r
+\r
+/*! \name GPIO Connections of LEDs\r
+ */\r
+//! @{\r
+#define LED0_GPIO   AVR32_PIN_PB27\r
+#define LED1_GPIO   AVR32_PIN_PB28\r
+#define LED2_GPIO   AVR32_PIN_PB29\r
+#define LED3_GPIO   AVR32_PIN_PB30\r
+#define LED4_GPIO   AVR32_PIN_PB19\r
+#define LED5_GPIO   AVR32_PIN_PB20\r
+#define LED6_GPIO   AVR32_PIN_PB21\r
+#define LED7_GPIO   AVR32_PIN_PB22\r
+//! @}\r
+\r
+/*! \name PWM Channels of LEDs\r
+ */\r
+//! @{\r
+#define LED0_PWM    (-1)\r
+#define LED1_PWM    (-1)\r
+#define LED2_PWM    (-1)\r
+#define LED3_PWM    (-1)\r
+#define LED4_PWM      0\r
+#define LED5_PWM      1\r
+#define LED6_PWM      2\r
+#define LED7_PWM      3\r
+//! @}\r
+\r
+/*! \name PWM Functions of LEDs\r
+ */\r
+//! @{\r
+#define LED0_PWM_FUNCTION   (-1)\r
+#define LED1_PWM_FUNCTION   (-1)\r
+#define LED2_PWM_FUNCTION   (-1)\r
+#define LED3_PWM_FUNCTION   (-1)\r
+#define LED4_PWM_FUNCTION   AVR32_PWM_0_FUNCTION\r
+#define LED5_PWM_FUNCTION   AVR32_PWM_1_FUNCTION\r
+#define LED6_PWM_FUNCTION   AVR32_PWM_2_FUNCTION\r
+#define LED7_PWM_FUNCTION   AVR32_PWM_3_FUNCTION\r
+//! @}\r
+\r
+/*! \name Color Identifiers of LEDs to Use with LED Functions\r
+ */\r
+//! @{\r
+#define LED_MONO0_GREEN   LED0\r
+#define LED_MONO1_GREEN   LED1\r
+#define LED_MONO2_GREEN   LED2\r
+#define LED_MONO3_GREEN   LED3\r
+#define LED_BI0_GREEN     LED5\r
+#define LED_BI0_RED       LED4\r
+#define LED_BI1_GREEN     LED7\r
+#define LED_BI1_RED       LED6\r
+//! @}\r
+\r
+\r
+/*! \name GPIO Connections of Push Buttons\r
+ */\r
+//! @{\r
+#define GPIO_PUSH_BUTTON_0            AVR32_PIN_PX16\r
+#define GPIO_PUSH_BUTTON_0_PRESSED    0\r
+#define GPIO_PUSH_BUTTON_1            AVR32_PIN_PX19\r
+#define GPIO_PUSH_BUTTON_1_PRESSED    0\r
+#define GPIO_PUSH_BUTTON_2            AVR32_PIN_PX22\r
+#define GPIO_PUSH_BUTTON_2_PRESSED    0\r
+//! @}\r
+\r
+\r
+/*! \name GPIO Connections of the Joystick\r
+ */\r
+//! @{\r
+#define GPIO_JOYSTICK_PUSH            AVR32_PIN_PA20\r
+#define GPIO_JOYSTICK_PUSH_PRESSED    0\r
+#define GPIO_JOYSTICK_LEFT            AVR32_PIN_PA25\r
+#define GPIO_JOYSTICK_LEFT_PRESSED    0\r
+#define GPIO_JOYSTICK_RIGHT           AVR32_PIN_PA28\r
+#define GPIO_JOYSTICK_RIGHT_PRESSED   0\r
+#define GPIO_JOYSTICK_UP              AVR32_PIN_PA26\r
+#define GPIO_JOYSTICK_UP_PRESSED      0\r
+#define GPIO_JOYSTICK_DOWN            AVR32_PIN_PA27\r
+#define GPIO_JOYSTICK_DOWN_PRESSED    0\r
+//! @}\r
+\r
+\r
+/*! \name ADC Connection of the Potentiometer\r
+ */\r
+//! @{\r
+#define ADC_POTENTIOMETER_CHANNEL   1\r
+#define ADC_POTENTIOMETER_PIN       AVR32_ADC_AD_1_PIN\r
+#define ADC_POTENTIOMETER_FUNCTION  AVR32_ADC_AD_1_FUNCTION\r
+//! @}\r
+\r
+\r
+/*! \name ADC Connection of the Temperature Sensor\r
+ */\r
+//! @{\r
+#define ADC_TEMPERATURE_CHANNEL     0\r
+#define ADC_TEMPERATURE_PIN         AVR32_ADC_AD_0_PIN\r
+#define ADC_TEMPERATURE_FUNCTION    AVR32_ADC_AD_0_FUNCTION\r
+//! @}\r
+\r
+\r
+/*! \name ADC Connection of the Light Sensor\r
+ */\r
+//! @{\r
+#define ADC_LIGHT_CHANNEL           2\r
+#define ADC_LIGHT_PIN               AVR32_ADC_AD_2_PIN\r
+#define ADC_LIGHT_FUNCTION          AVR32_ADC_AD_2_FUNCTION\r
+//! @}\r
+\r
+\r
+/*! \name SPI Connections of the DIP204 LCD\r
+ */\r
+//! @{\r
+#define DIP204_SPI                  (&AVR32_SPI1)\r
+#define DIP204_SPI_NPCS             2\r
+#define DIP204_SPI_SCK_PIN          AVR32_SPI1_SCK_0_0_PIN\r
+#define DIP204_SPI_SCK_FUNCTION     AVR32_SPI1_SCK_0_0_FUNCTION\r
+#define DIP204_SPI_MISO_PIN         AVR32_SPI1_MISO_0_0_PIN\r
+#define DIP204_SPI_MISO_FUNCTION    AVR32_SPI1_MISO_0_0_FUNCTION\r
+#define DIP204_SPI_MOSI_PIN         AVR32_SPI1_MOSI_0_0_PIN\r
+#define DIP204_SPI_MOSI_FUNCTION    AVR32_SPI1_MOSI_0_0_FUNCTION\r
+#define DIP204_SPI_NPCS_PIN         AVR32_SPI1_NPCS_2_0_PIN\r
+#define DIP204_SPI_NPCS_FUNCTION    AVR32_SPI1_NPCS_2_0_FUNCTION\r
+//! @}\r
+\r
+/*! \name GPIO and PWM Connections of the DIP204 LCD Backlight\r
+ */\r
+//! @{\r
+#define DIP204_BACKLIGHT_PIN        AVR32_PIN_PB18\r
+#define DIP204_PWM_CHANNEL          6\r
+#define DIP204_PWM_PIN              AVR32_PWM_6_PIN\r
+#define DIP204_PWM_FUNCTION         AVR32_PWM_6_FUNCTION\r
+//! @}\r
+\r
+\r
+/*! \name SPI Connections of the AT45DBX Data Flash Memory\r
+ */\r
+//! @{\r
+#define AT45DBX_SPI                 (&AVR32_SPI1)\r
+#define AT45DBX_SPI_NPCS            0\r
+#define AT45DBX_SPI_SCK_PIN         AVR32_SPI1_SCK_0_0_PIN\r
+#define AT45DBX_SPI_SCK_FUNCTION    AVR32_SPI1_SCK_0_0_FUNCTION\r
+#define AT45DBX_SPI_MISO_PIN        AVR32_SPI1_MISO_0_0_PIN\r
+#define AT45DBX_SPI_MISO_FUNCTION   AVR32_SPI1_MISO_0_0_FUNCTION\r
+#define AT45DBX_SPI_MOSI_PIN        AVR32_SPI1_MOSI_0_0_PIN\r
+#define AT45DBX_SPI_MOSI_FUNCTION   AVR32_SPI1_MOSI_0_0_FUNCTION\r
+#define AT45DBX_SPI_NPCS0_PIN       AVR32_SPI1_NPCS_0_0_PIN\r
+#define AT45DBX_SPI_NPCS0_FUNCTION  AVR32_SPI1_NPCS_0_0_FUNCTION\r
+//! @}\r
+\r
+\r
+/*! \name GPIO and SPI Connections of the SD/MMC Connector\r
+ */\r
+//! @{\r
+#define SD_MMC_CARD_DETECT_PIN      AVR32_PIN_PA02\r
+#define SD_MMC_WRITE_PROTECT_PIN    AVR32_PIN_PA07\r
+#define SD_MMC_SPI                  (&AVR32_SPI1)\r
+#define SD_MMC_SPI_NPCS             1\r
+#define SD_MMC_SPI_SCK_PIN          AVR32_SPI1_SCK_0_0_PIN\r
+#define SD_MMC_SPI_SCK_FUNCTION     AVR32_SPI1_SCK_0_0_FUNCTION\r
+#define SD_MMC_SPI_MISO_PIN         AVR32_SPI1_MISO_0_0_PIN\r
+#define SD_MMC_SPI_MISO_FUNCTION    AVR32_SPI1_MISO_0_0_FUNCTION\r
+#define SD_MMC_SPI_MOSI_PIN         AVR32_SPI1_MOSI_0_0_PIN\r
+#define SD_MMC_SPI_MOSI_FUNCTION    AVR32_SPI1_MOSI_0_0_FUNCTION\r
+#define SD_MMC_SPI_NPCS_PIN         AVR32_SPI1_NPCS_1_0_PIN\r
+#define SD_MMC_SPI_NPCS_FUNCTION    AVR32_SPI1_NPCS_1_0_FUNCTION\r
+//! @}\r
+\r
+\r
+/*! \name TWI Connections of the Spare TWI Connector\r
+ */\r
+//! @{\r
+#define SPARE_TWI                   (&AVR32_TWI)\r
+#define SPARE_TWI_SCL_PIN           AVR32_TWI_SCL_0_0_PIN\r
+#define SPARE_TWI_SCL_FUNCTION      AVR32_TWI_SCL_0_0_FUNCTION\r
+#define SPARE_TWI_SDA_PIN           AVR32_TWI_SDA_0_0_PIN\r
+#define SPARE_TWI_SDA_FUNCTION      AVR32_TWI_SDA_0_0_FUNCTION\r
+//! @}\r
+\r
+\r
+/*! \name SPI Connections of the Spare SPI Connector\r
+ */\r
+//! @{\r
+#define SPARE_SPI                   (&AVR32_SPI0)\r
+#define SPARE_SPI_NPCS              0\r
+#define SPARE_SPI_SCK_PIN           AVR32_SPI0_SCK_0_0_PIN\r
+#define SPARE_SPI_SCK_FUNCTION      AVR32_SPI0_SCK_0_0_FUNCTION\r
+#define SPARE_SPI_MISO_PIN          AVR32_SPI0_MISO_0_0_PIN\r
+#define SPARE_SPI_MISO_FUNCTION     AVR32_SPI0_MISO_0_0_FUNCTION\r
+#define SPARE_SPI_MOSI_PIN          AVR32_SPI0_MOSI_0_0_PIN\r
+#define SPARE_SPI_MOSI_FUNCTION     AVR32_SPI0_MOSI_0_0_FUNCTION\r
+#define SPARE_SPI_NPCS_PIN          AVR32_SPI0_NPCS_0_0_PIN\r
+#define SPARE_SPI_NPCS_FUNCTION     AVR32_SPI0_NPCS_0_0_FUNCTION\r
+//! @}\r
+\r
+\r
+#endif  // !EVK1100_REVA\r
+\r
+#endif  // _EVK1100_H_\r

diff --git a/Demo/AVR32_UC3A_GCC/Atmel_SW_Framework/BOARDS/EVK1100/led.c b/Demo/AVR32_UC3A_GCC/Atmel_SW_Framework/BOARDS/EVK1100/led.c
new file mode 100644 (file)
index 0000000..22f2070
--- /dev/null
+++ b/Demo/AVR32_UC3A_GCC/Atmel_SW_Framework/BOARDS/EVK1100/led.c
@@ -0,0 +1,346 @@
+/* This source file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */\r
+
+/*This file is prepared for Doxygen automatic documentation generation.*/\r
+/*! \file *********************************************************************\r
+ *\r
+ * \brief AT32UC3A EVK1100 board LEDs support package.\r
+ *\r
+ * This file contains definitions and services related to the LED features of\r
+ * the EVK1100 board.\r
+ *\r
+ * - Compiler:           IAR EWAVR32 and GNU GCC for AVR32\r
+ * - Supported devices:  All AVR32 AT32UC3A devices can be used.\r
+ * - AppNote:\r
+ *\r
+ * \author               Atmel Corporation: http://www.atmel.com \n\r
+ *                       Support and FAQ: http://support.atmel.no/\r
+ *\r
+ ******************************************************************************/\r
+\r
+/* Copyright (c) 2009 Atmel Corporation. All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice, this\r
+ * list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an Atmel\r
+ * AVR product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\r
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\r
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\r
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE\r
+ *\r
+ */\r
+\r
+#include <avr32/io.h>\r
+#include "preprocessor.h"\r
+#include "compiler.h"\r
+#include "evk1100.h"\r
+#include "led.h"\r
+\r
+\r
+//! Structure describing LED hardware connections.\r
+typedef const struct\r
+{\r
+  struct\r
+  {\r
+    U32 PORT;     //!< LED GPIO port.\r
+    U32 PIN_MASK; //!< Bit-mask of LED pin in GPIO port.\r
+  } GPIO; //!< LED GPIO descriptor.\r
+  struct\r
+  {\r
+    S32 CHANNEL;  //!< LED PWM channel (< 0 if N/A).\r
+    S32 FUNCTION; //!< LED pin PWM function (< 0 if N/A).\r
+  } PWM;  //!< LED PWM descriptor.\r
+} tLED_DESCRIPTOR;\r
+\r
+\r
+//! Hardware descriptors of all LEDs.\r
+static tLED_DESCRIPTOR LED_DESCRIPTOR[LED_COUNT] =\r
+{\r
+#define INSERT_LED_DESCRIPTOR(LED_NO, unused)                 \\r
+  {                                                           \\r
+    {LED##LED_NO##_GPIO / 32, 1 << (LED##LED_NO##_GPIO % 32)},\\r
+    {LED##LED_NO##_PWM,       LED##LED_NO##_PWM_FUNCTION    } \\r
+  },\r
+  MREPEAT(LED_COUNT, INSERT_LED_DESCRIPTOR, ~)\r
+#undef INSERT_LED_DESCRIPTOR\r
+};\r
+\r
+\r
+//! Saved state of all LEDs.\r
+static volatile U32 LED_State = (1 << LED_COUNT) - 1;\r
+\r
+\r
+U32 LED_Read_Display(void)\r
+{\r
+  return LED_State;\r
+}\r
+\r
+\r
+void LED_Display(U32 leds)\r
+{\r
+  // Use the LED descriptors to get the connections of a given LED to the MCU.\r
+  tLED_DESCRIPTOR *led_descriptor;\r
+  volatile avr32_gpio_port_t *led_gpio_port;\r
+\r
+  // Make sure only existing LEDs are specified.\r
+  leds &= (1 << LED_COUNT) - 1;\r
+\r
+  // Update the saved state of all LEDs with the requested changes.\r
+  LED_State = leds;\r
+\r
+  // For all LEDs...\r
+  for (led_descriptor = &LED_DESCRIPTOR[0];\r
+       led_descriptor < LED_DESCRIPTOR + LED_COUNT;\r
+       led_descriptor++)\r
+  {\r
+    // Set the LED to the requested state.\r
+    led_gpio_port = &AVR32_GPIO.port[led_descriptor->GPIO.PORT];\r
+    if (leds & 1)\r
+    {\r
+      led_gpio_port->ovrc  = led_descriptor->GPIO.PIN_MASK;\r
+    }\r
+    else\r
+    {\r
+      led_gpio_port->ovrs  = led_descriptor->GPIO.PIN_MASK;\r
+    }\r
+    led_gpio_port->oders = led_descriptor->GPIO.PIN_MASK;\r
+    led_gpio_port->gpers = led_descriptor->GPIO.PIN_MASK;\r
+    leds >>= 1;\r
+  }\r
+}\r
+\r
+\r
+U32 LED_Read_Display_Mask(U32 mask)\r
+{\r
+  return Rd_bits(LED_State, mask);\r
+}\r
+\r
+\r
+void LED_Display_Mask(U32 mask, U32 leds)\r
+{\r
+  // Use the LED descriptors to get the connections of a given LED to the MCU.\r
+  tLED_DESCRIPTOR *led_descriptor = &LED_DESCRIPTOR[0] - 1;\r
+  volatile avr32_gpio_port_t *led_gpio_port;\r
+  U8 led_shift;\r
+\r
+  // Make sure only existing LEDs are specified.\r
+  mask &= (1 << LED_COUNT) - 1;\r
+\r
+  // Update the saved state of all LEDs with the requested changes.\r
+  Wr_bits(LED_State, mask, leds);\r
+\r
+  // While there are specified LEDs left to manage...\r
+  while (mask)\r
+  {\r
+    // Select the next specified LED and set it to the requested state.\r
+    led_shift = 1 + ctz(mask);\r
+    led_descriptor += led_shift;\r
+    led_gpio_port = &AVR32_GPIO.port[led_descriptor->GPIO.PORT];\r
+    leds >>= led_shift - 1;\r
+    if (leds & 1)\r
+    {\r
+      led_gpio_port->ovrc  = led_descriptor->GPIO.PIN_MASK;\r
+    }\r
+    else\r
+    {\r
+      led_gpio_port->ovrs  = led_descriptor->GPIO.PIN_MASK;\r
+    }\r
+    led_gpio_port->oders = led_descriptor->GPIO.PIN_MASK;\r
+    led_gpio_port->gpers = led_descriptor->GPIO.PIN_MASK;\r
+    leds >>= 1;\r
+    mask >>= led_shift;\r
+  }\r
+}\r
+\r
+\r
+Bool LED_Test(U32 leds)\r
+{\r
+  return Tst_bits(LED_State, leds);\r
+}\r
+\r
+\r
+void LED_Off(U32 leds)\r
+{\r
+  // Use the LED descriptors to get the connections of a given LED to the MCU.\r
+  tLED_DESCRIPTOR *led_descriptor = &LED_DESCRIPTOR[0] - 1;\r
+  volatile avr32_gpio_port_t *led_gpio_port;\r
+  U8 led_shift;\r
+\r
+  // Make sure only existing LEDs are specified.\r
+  leds &= (1 << LED_COUNT) - 1;\r
+\r
+  // Update the saved state of all LEDs with the requested changes.\r
+  Clr_bits(LED_State, leds);\r
+\r
+  // While there are specified LEDs left to manage...\r
+  while (leds)\r
+  {\r
+    // Select the next specified LED and turn it off.\r
+    led_shift = 1 + ctz(leds);\r
+    led_descriptor += led_shift;\r
+    led_gpio_port = &AVR32_GPIO.port[led_descriptor->GPIO.PORT];\r
+    led_gpio_port->ovrs  = led_descriptor->GPIO.PIN_MASK;\r
+    led_gpio_port->oders = led_descriptor->GPIO.PIN_MASK;\r
+    led_gpio_port->gpers = led_descriptor->GPIO.PIN_MASK;\r
+    leds >>= led_shift;\r
+  }\r
+}\r
+\r
+\r
+void LED_On(U32 leds)\r
+{\r
+  // Use the LED descriptors to get the connections of a given LED to the MCU.\r
+  tLED_DESCRIPTOR *led_descriptor = &LED_DESCRIPTOR[0] - 1;\r
+  volatile avr32_gpio_port_t *led_gpio_port;\r
+  U8 led_shift;\r
+\r
+  // Make sure only existing LEDs are specified.\r
+  leds &= (1 << LED_COUNT) - 1;\r
+\r
+  // Update the saved state of all LEDs with the requested changes.\r
+  Set_bits(LED_State, leds);\r
+\r
+  // While there are specified LEDs left to manage...\r
+  while (leds)\r
+  {\r
+    // Select the next specified LED and turn it on.\r
+    led_shift = 1 + ctz(leds);\r
+    led_descriptor += led_shift;\r
+    led_gpio_port = &AVR32_GPIO.port[led_descriptor->GPIO.PORT];\r
+    led_gpio_port->ovrc  = led_descriptor->GPIO.PIN_MASK;\r
+    led_gpio_port->oders = led_descriptor->GPIO.PIN_MASK;\r
+    led_gpio_port->gpers = led_descriptor->GPIO.PIN_MASK;\r
+    leds >>= led_shift;\r
+  }\r
+}\r
+\r
+\r
+void LED_Toggle(U32 leds)\r
+{\r
+  // Use the LED descriptors to get the connections of a given LED to the MCU.\r
+  tLED_DESCRIPTOR *led_descriptor = &LED_DESCRIPTOR[0] - 1;\r
+  volatile avr32_gpio_port_t *led_gpio_port;\r
+  U8 led_shift;\r
+\r
+  // Make sure only existing LEDs are specified.\r
+  leds &= (1 << LED_COUNT) - 1;\r
+\r
+  // Update the saved state of all LEDs with the requested changes.\r
+  Tgl_bits(LED_State, leds);\r
+\r
+  // While there are specified LEDs left to manage...\r
+  while (leds)\r
+  {\r
+    // Select the next specified LED and toggle it.\r
+    led_shift = 1 + ctz(leds);\r
+    led_descriptor += led_shift;\r
+    led_gpio_port = &AVR32_GPIO.port[led_descriptor->GPIO.PORT];\r
+    led_gpio_port->ovrt  = led_descriptor->GPIO.PIN_MASK;\r
+    led_gpio_port->oders = led_descriptor->GPIO.PIN_MASK;\r
+    led_gpio_port->gpers = led_descriptor->GPIO.PIN_MASK;\r
+    leds >>= led_shift;\r
+  }\r
+}\r
+\r
+\r
+U32 LED_Read_Display_Field(U32 field)\r
+{\r
+  return Rd_bitfield(LED_State, field);\r
+}\r
+\r
+\r
+void LED_Display_Field(U32 field, U32 leds)\r
+{\r
+  // Move the bit-field to the appropriate position for the bit-mask.\r
+  LED_Display_Mask(field, leds << ctz(field));\r
+}\r
+\r
+\r
+U8 LED_Get_Intensity(U32 led)\r
+{\r
+  tLED_DESCRIPTOR *led_descriptor;\r
+\r
+  // Check that the argument value is valid.\r
+  led = ctz(led);\r
+  led_descriptor = &LED_DESCRIPTOR[led];\r
+  if (led >= LED_COUNT || led_descriptor->PWM.CHANNEL < 0) return 0;\r
+\r
+  // Return the duty cycle value if the LED PWM channel is enabled, else 0.\r
+  return (AVR32_PWM.sr & (1 << led_descriptor->PWM.CHANNEL)) ?\r
+           AVR32_PWM.channel[led_descriptor->PWM.CHANNEL].cdty : 0;\r
+}\r
+\r
+\r
+void LED_Set_Intensity(U32 leds, U8 intensity)\r
+{\r
+  tLED_DESCRIPTOR *led_descriptor = &LED_DESCRIPTOR[0] - 1;\r
+  volatile avr32_pwm_channel_t *led_pwm_channel;\r
+  volatile avr32_gpio_port_t *led_gpio_port;\r
+  U8 led_shift;\r
+\r
+  // For each specified LED...\r
+  for (leds &= (1 << LED_COUNT) - 1; leds; leds >>= led_shift)\r
+  {\r
+    // Select the next specified LED and check that it has a PWM channel.\r
+    led_shift = 1 + ctz(leds);\r
+    led_descriptor += led_shift;\r
+    if (led_descriptor->PWM.CHANNEL < 0) continue;\r
+\r
+    // Initialize or update the LED PWM channel.\r
+    led_pwm_channel = &AVR32_PWM.channel[led_descriptor->PWM.CHANNEL];\r
+    if (!(AVR32_PWM.sr & (1 << led_descriptor->PWM.CHANNEL)))\r
+    {\r
+      led_pwm_channel->cmr = (AVR32_PWM_CPRE_MCK << AVR32_PWM_CPRE_OFFSET) &\r
+                             ~(AVR32_PWM_CALG_MASK |\r
+                               AVR32_PWM_CPOL_MASK |\r
+                               AVR32_PWM_CPD_MASK);\r
+      led_pwm_channel->cprd = 0x000000FF;\r
+      led_pwm_channel->cdty = intensity;\r
+      AVR32_PWM.ena = 1 << led_descriptor->PWM.CHANNEL;\r
+    }\r
+    else\r
+    {\r
+      AVR32_PWM.isr;\r
+      while (!(AVR32_PWM.isr & (1 << led_descriptor->PWM.CHANNEL)));\r
+      led_pwm_channel->cupd = intensity;\r
+    }\r
+\r
+    // Switch the LED pin to its PWM function.\r
+    led_gpio_port = &AVR32_GPIO.port[led_descriptor->GPIO.PORT];\r
+    if (led_descriptor->PWM.FUNCTION & 0x1)\r
+    {\r
+      led_gpio_port->pmr0s = led_descriptor->GPIO.PIN_MASK;\r
+    }\r
+    else\r
+    {\r
+      led_gpio_port->pmr0c = led_descriptor->GPIO.PIN_MASK;\r
+    }\r
+    if (led_descriptor->PWM.FUNCTION & 0x2)\r
+    {\r
+      led_gpio_port->pmr1s = led_descriptor->GPIO.PIN_MASK;\r
+    }\r
+    else\r
+    {\r
+      led_gpio_port->pmr1c = led_descriptor->GPIO.PIN_MASK;\r
+    }\r
+    led_gpio_port->gperc = led_descriptor->GPIO.PIN_MASK;\r
+  }\r
+}\r

diff --git a/Demo/AVR32_UC3A_GCC/Atmel_SW_Framework/BOARDS/EVK1100/led.h b/Demo/AVR32_UC3A_GCC/Atmel_SW_Framework/BOARDS/EVK1100/led.h
new file mode 100644 (file)
index 0000000..29f8822
--- /dev/null
+++ b/Demo/AVR32_UC3A_GCC/Atmel_SW_Framework/BOARDS/EVK1100/led.h
@@ -0,0 +1,191 @@
+/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */\r
+
+/*This file is prepared for Doxygen automatic documentation generation.*/\r
+/*! \file *********************************************************************\r
+ *\r
+ * \brief AT32UC3A EVK1100 board LEDs support package.\r
+ *\r
+ * This file contains definitions and services related to the LED features of\r
+ * the EVK1100 board.\r
+ *\r
+ * - Compiler:           IAR EWAVR32 and GNU GCC for AVR32\r
+ * - Supported devices:  All AVR32 AT32UC3A devices can be used.\r
+ * - AppNote:\r
+ *\r
+ * \author               Atmel Corporation: http://www.atmel.com \n\r
+ *                       Support and FAQ: http://support.atmel.no/\r
+ *\r
+ ******************************************************************************/\r
+\r
+/* Copyright (c) 2009 Atmel Corporation. All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice, this\r
+ * list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an Atmel\r
+ * AVR product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\r
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\r
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\r
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE\r
+ *\r
+ */\r
+\r
+#ifndef _LED_H_\r
+#define _LED_H_\r
+\r
+#include "compiler.h"\r
+\r
+\r
+/*! \name Identifiers of LEDs to Use with LED Functions\r
+ */\r
+//! @{\r
+#define LED0  0x01\r
+#define LED1  0x02\r
+#define LED2  0x04\r
+#define LED3  0x08\r
+#define LED4  0x10\r
+#define LED5  0x20\r
+#define LED6  0x40\r
+#define LED7  0x80\r
+//! @}\r
+\r
+\r
+/*! \brief Gets the last state of all LEDs set through the LED API.\r
+ *\r
+ * \return State of all LEDs (1 bit per LED).\r
+ *\r
+ * \note The GPIO pin configuration of all LEDs is left unchanged.\r
+ */\r
+extern U32 LED_Read_Display(void);\r
+\r
+/*! \brief Sets the state of all LEDs.\r
+ *\r
+ * \param leds New state of all LEDs (1 bit per LED).\r
+ *\r
+ * \note The pins of all LEDs are set to GPIO output mode.\r
+ */\r
+extern void LED_Display(U32 leds);\r
+\r
+/*! \brief Gets the last state of the specified LEDs set through the LED API.\r
+ *\r
+ * \param mask LEDs of which to get the state (1 bit per LED).\r
+ *\r
+ * \return State of the specified LEDs (1 bit per LED).\r
+ *\r
+ * \note The GPIO pin configuration of all LEDs is left unchanged.\r
+ */\r
+extern U32 LED_Read_Display_Mask(U32 mask);\r
+\r
+/*! \brief Sets the state of the specified LEDs.\r
+ *\r
+ * \param mask LEDs of which to set the state (1 bit per LED).\r
+ *\r
+ * \param leds New state of the specified LEDs (1 bit per LED).\r
+ *\r
+ * \note The pins of the specified LEDs are set to GPIO output mode.\r
+ */\r
+extern void LED_Display_Mask(U32 mask, U32 leds);\r
+\r
+/*! \brief Tests the last state of the specified LEDs set through the LED API.\r
+ *\r
+ * \param leds LEDs of which to test the state (1 bit per LED).\r
+ *\r
+ * \return \c TRUE if at least one of the specified LEDs has a state on, else\r
+ *         \c FALSE.\r
+ *\r
+ * \note The GPIO pin configuration of all LEDs is left unchanged.\r
+ */\r
+extern Bool LED_Test(U32 leds);\r
+\r
+/*! \brief Turns off the specified LEDs.\r
+ *\r
+ * \param leds LEDs to turn off (1 bit per LED).\r
+ *\r
+ * \note The pins of the specified LEDs are set to GPIO output mode.\r
+ */\r
+extern void LED_Off(U32 leds);\r
+\r
+/*! \brief Turns on the specified LEDs.\r
+ *\r
+ * \param leds LEDs to turn on (1 bit per LED).\r
+ *\r
+ * \note The pins of the specified LEDs are set to GPIO output mode.\r
+ */\r
+extern void LED_On(U32 leds);\r
+\r
+/*! \brief Toggles the specified LEDs.\r
+ *\r
+ * \param leds LEDs to toggle (1 bit per LED).\r
+ *\r
+ * \note The pins of the specified LEDs are set to GPIO output mode.\r
+ */\r
+extern void LED_Toggle(U32 leds);\r
+\r
+/*! \brief Gets as a bit-field the last state of the specified LEDs set through\r
+ *         the LED API.\r
+ *\r
+ * \param field LEDs of which to get the state (1 bit per LED).\r
+ *\r
+ * \return State of the specified LEDs (1 bit per LED, beginning with the first\r
+ *         specified LED).\r
+ *\r
+ * \note The GPIO pin configuration of all LEDs is left unchanged.\r
+ */\r
+extern U32 LED_Read_Display_Field(U32 field);\r
+\r
+/*! \brief Sets as a bit-field the state of the specified LEDs.\r
+ *\r
+ * \param field LEDs of which to set the state (1 bit per LED).\r
+ * \param leds New state of the specified LEDs (1 bit per LED, beginning with\r
+ *             the first specified LED).\r
+ *\r
+ * \note The pins of the specified LEDs are set to GPIO output mode.\r
+ */\r
+extern void LED_Display_Field(U32 field, U32 leds);\r
+\r
+/*! \brief Gets the intensity of the specified LED.\r
+ *\r
+ * \param led LED of which to get the intensity (1 bit per LED; only the least\r
+ *            significant set bit is used).\r
+ *\r
+ * \return Intensity of the specified LED (0x00 to 0xFF).\r
+ *\r
+ * \warning The PWM channel of the specified LED is supposed to be used only by\r
+ *          this module.\r
+ *\r
+ * \note The GPIO pin configuration of all LEDs is left unchanged.\r
+ */\r
+extern U8 LED_Get_Intensity(U32 led);\r
+\r
+/*! \brief Sets the intensity of the specified LEDs.\r
+ *\r
+ * \param leds LEDs of which to set the intensity (1 bit per LED).\r
+ * \param intensity New intensity of the specified LEDs (0x00 to 0xFF).\r
+ *\r
+ * \warning The PWM channels of the specified LEDs are supposed to be used only\r
+ *          by this module.\r
+ *\r
+ * \note The pins of the specified LEDs are set to PWM output mode.\r
+ */\r
+extern void LED_Set_Intensity(U32 leds, U8 intensity);\r
+\r
+\r
+#endif  // _LED_H_\r

diff --git a/Demo/AVR32_UC3A_GCC/Atmel_SW_Framework/BOARDS/EVK1100/readme.html b/Demo/AVR32_UC3A_GCC/Atmel_SW_Framework/BOARDS/EVK1100/readme.html
new file mode 100644 (file)
index 0000000..2a3a402
--- /dev/null
+++ b/Demo/AVR32_UC3A_GCC/Atmel_SW_Framework/BOARDS/EVK1100/readme.html
@@ -0,0 +1,33 @@
+<!doctype HTML public "-//W3C//DTD HTML 4.0 Frameset//EN">
+<html>
+   <head>
+      <link rel="stylesheet" type="text/css" href="../../.docsrc/AVR32_ns.css">
+   </head>
+   <body>
+   <div id="wrapper">
+<p align="left" class="whs2"><a href="../BOARDS_Readme.html"<font color="red"></font>Back to BOARDS page</a></p>   
+<h1 align="center" class="whs1">AVR UC3 Series Software Framework: EVK1100 board software abstraction<br>
+</h1>
+
+<p align="center" class="whs2">Copyright &copy; 2007 Atmel Corporation</p>
+
+<h2>Content</h2>
+<p>The abstraction is made of the following files:</p>
+<DL>
+<DT><li><a href="evk1100.h">evk1100.h:</a>a preprocessor mapping of the on-board AT32UC3A pins connections to the on-board hardware resources.</li>
+</DL>
+<DL>
+<DT><li><a href="led.c">led.c</a> and <a href="led.h">led.h: </a>a specific set of functions to easily control the EVK1100 LEDs.</li>
+</DL>
+    
+
+<p>&nbsp;</p>
+
+
+<hr align="center" width="50%" class="whs4">
+
+    <p class=legalfooter>AVR is a registered trademark of
+    Atmel Corporation.</p>
+   <div>>
+   </body>
+</html>

diff --git a/Demo/AVR32_UC3A_GCC/Atmel_SW_Framework/BOARDS/board.h b/Demo/AVR32_UC3A_GCC/Atmel_SW_Framework/BOARDS/board.h
new file mode 100644 (file)
index 0000000..fbdd094
--- /dev/null
+++ b/Demo/AVR32_UC3A_GCC/Atmel_SW_Framework/BOARDS/board.h
@@ -0,0 +1,121 @@
+/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */\r
+
+/*This file is prepared for Doxygen automatic documentation generation.*/\r
+/*! \file *********************************************************************\r
+ *\r
+ * \brief Standard board header file.\r
+ *\r
+ * This file includes the appropriate board header file according to the\r
+ * defined board.\r
+ *\r
+ * - Compiler:           IAR EWAVR32 and GNU GCC for AVR32\r
+ * - Supported devices:  All AVR32 devices can be used.\r
+ * - AppNote:\r
+ *\r
+ * \author               Atmel Corporation: http://www.atmel.com \n\r
+ *                       Support and FAQ: http://support.atmel.no/\r
+ *\r
+ ******************************************************************************/\r
+\r
+/* Copyright (c) 2009 Atmel Corporation. All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice, this\r
+ * list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an Atmel\r
+ * AVR product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\r
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\r
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\r
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE\r
+ *\r
+ */\r
+\r
+#ifndef _BOARD_H_\r
+#define _BOARD_H_\r
+\r
+#include <avr32/io.h>\r
+\r
+/*! \name Base Boards\r
+ */\r
+//! @{\r
+#define EVK1100           1   //!< AT32UC3A EVK1100 board.\r
+#define EVK1101           2   //!< AT32UC3B EVK1101 board.\r
+#define UC3C_EK           3   //!< AT32UC3C UC3C_EK board.\r
+#define EVK1104           4   //!< AT32UC3A3 EVK1104 board.\r
+#define EVK1105           5   //!< AT32UC3A EVK1105 board.\r
+#define STK1000           6   //!< AT32AP7000 STK1000 board.\r
+#define NGW100            7   //!< AT32AP7000 NGW100 board.\r
+#define STK600_RCUC3L0    8   //!< STK600 RCUC3L0 board.\r
+#define UC3L_EK           9   //!< AT32UC3L-EK board.\r
+#define USER_BOARD        99  //!< User-reserved board (if any).\r
+//! @}\r
+\r
+/*! \name Extension Boards\r
+ */\r
+//! @{\r
+#define EXT1102           1   //!< AT32UC3B EXT1102 board.\r
+#define MC300             2   //!< AT32UC3 MC300 board.\r
+#define USER_EXT_BOARD    99  //!< User-reserved extension board (if any).\r
+//! @}\r
+\r
+#if BOARD == EVK1100\r
+  #include "EVK1100/evk1100.h"\r
+#elif BOARD == EVK1101\r
+  #include "EVK1101/evk1101.h"\r
+#elif BOARD == UC3C_EK\r
+  #include "UC3C_EK/uc3c_ek.h"\r
+#elif BOARD == EVK1104\r
+  #include "EVK1104/evk1104.h"\r
+#elif BOARD == EVK1105\r
+  #include "EVK1105/evk1105.h"\r
+#elif BOARD == STK1000\r
+  #include "STK1000/stk1000.h"\r
+#elif BOARD == NGW100\r
+  #include "NGW100/ngw100.h"\r
+#elif BOARD == STK600_RCUC3L0\r
+  #include "STK600/RCUC3L0/stk600_rcuc3l0.h"\r
+#elif BOARD == UC3L_EK\r
+  #include "UC3L_EK/uc3l_ek.h"\r
+#elif BOARD == USER_BOARD\r
+  // User-reserved area: #include the header file of your board here (if any).\r
+  #include "user_board.h"\r
+#else\r
+  #error No known AVR32 board defined\r
+#endif\r
+\r
+#if (defined EXT_BOARD)\r
+  #if EXT_BOARD == EXT1102\r
+    #include "EXT1102/ext1102.h"\r
+  #elif EXT_BOARD == MC300\r
+    #include "MC300/mc300.h"\r
+  #elif EXT_BOARD == USER_EXT_BOARD\r
+    // User-reserved area: #include the header file of your extension board here\r
+    // (if any).\r
+  #endif\r
+#endif\r
+\r
+\r
+#ifndef FRCOSC\r
+  #define FRCOSC    AVR32_PM_RCOSC_FREQUENCY  //!< Default RCOsc frequency.\r
+#endif\r
+\r
+\r
+#endif  // _BOARD_H_\r

diff --git a/Demo/AVR32_UC3A_GCC/Atmel_SW_Framework/DRIVERS/GPIO/gpio.c b/Demo/AVR32_UC3A_GCC/Atmel_SW_Framework/DRIVERS/GPIO/gpio.c
new file mode 100644 (file)
index 0000000..42f4c49
--- /dev/null
+++ b/Demo/AVR32_UC3A_GCC/Atmel_SW_Framework/DRIVERS/GPIO/gpio.c
@@ -0,0 +1,458 @@
+/* This source file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */\r
+
+/*This file has been prepared for Doxygen automatic documentation generation.*/\r
+/*! \file *********************************************************************\r
+ *\r
+ * \brief GPIO driver for AVR32 UC3.\r
+ *\r
+ * This file defines a useful set of functions for the GPIO.\r
+ *\r
+ * - Compiler:           IAR EWAVR32 and GNU GCC for AVR32\r
+ * - Supported devices:  All AVR32 devices with a GPIO module can be used.\r
+ * - AppNote:\r
+ *\r
+ * \author               Atmel Corporation: http://www.atmel.com \n\r
+ *                       Support and FAQ: http://support.atmel.no/\r
+ *\r
+ *****************************************************************************/\r
+\r
+/* Copyright (c) 2009 Atmel Corporation. All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice, this\r
+ * list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an Atmel\r
+ * AVR product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\r
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\r
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\r
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE\r
+ *\r
+ */\r
+\r
+#include "gpio.h"\r
+\r
+//! GPIO module instance.\r
+#define GPIO  AVR32_GPIO\r
+\r
+\r
+/*! \name Peripheral Bus Interface\r
+ */\r
+//! @{\r
+\r
+\r
+int gpio_enable_module(const gpio_map_t gpiomap, unsigned int size)\r
+{\r
+  int status = GPIO_SUCCESS;\r
+  unsigned int i;\r
+\r
+  for (i = 0; i < size; i++)\r
+  {\r
+    status |= gpio_enable_module_pin(gpiomap->pin, gpiomap->function);\r
+    gpiomap++;\r
+  }\r
+\r
+  return status;\r
+}\r
+\r
+\r
+int gpio_enable_module_pin(unsigned int pin, unsigned int function)\r
+{\r
+  volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];\r
+\r
+  // Enable the correct function.\r
+  switch (function)\r
+  {\r
+  case 0: // A function.\r
+    gpio_port->pmr0c = 1 << (pin & 0x1F);\r
+    gpio_port->pmr1c = 1 << (pin & 0x1F);\r
+#if defined(AVR32_GPIO_210_H_INCLUDED) || defined(AVR32_GPIO_211_H_INCLUDED)\r
+    gpio_port->pmr2c = 1 << (pin & 0x1F);\r
+#endif\r
+    break;\r
+\r
+  case 1: // B function.\r
+    gpio_port->pmr0s = 1 << (pin & 0x1F);\r
+    gpio_port->pmr1c = 1 << (pin & 0x1F);\r
+#if defined(AVR32_GPIO_210_H_INCLUDED) || defined(AVR32_GPIO_211_H_INCLUDED)\r
+    gpio_port->pmr2c = 1 << (pin & 0x1F);\r
+#endif\r
+    break;\r
+\r
+  case 2: // C function.\r
+    gpio_port->pmr0c = 1 << (pin & 0x1F);\r
+    gpio_port->pmr1s = 1 << (pin & 0x1F);\r
+#if defined(AVR32_GPIO_210_H_INCLUDED) || defined(AVR32_GPIO_211_H_INCLUDED)\r
+    gpio_port->pmr2c = 1 << (pin & 0x1F);\r
+#endif\r
+    break;\r
+\r
+  case 3: // D function.\r
+    gpio_port->pmr0s = 1 << (pin & 0x1F);\r
+    gpio_port->pmr1s = 1 << (pin & 0x1F);\r
+#if defined(AVR32_GPIO_210_H_INCLUDED) || defined(AVR32_GPIO_211_H_INCLUDED)\r
+    gpio_port->pmr2c = 1 << (pin & 0x1F);\r
+#endif\r
+    break;\r
+\r
+#if defined(AVR32_GPIO_210_H_INCLUDED) || defined(AVR32_GPIO_211_H_INCLUDED)\r
+  case 4: // E function.\r
+    gpio_port->pmr0c = 1 << (pin & 0x1F);\r
+    gpio_port->pmr1c = 1 << (pin & 0x1F);\r
+    gpio_port->pmr2s = 1 << (pin & 0x1F);\r
+    break;\r
+    \r
+  case 5: // F function.\r
+    gpio_port->pmr0s = 1 << (pin & 0x1F);\r
+    gpio_port->pmr1c = 1 << (pin & 0x1F);\r
+    gpio_port->pmr2s = 1 << (pin & 0x1F);\r
+    break;\r
+    \r
+  case 6: // G function.\r
+    gpio_port->pmr0c = 1 << (pin & 0x1F);\r
+    gpio_port->pmr1s = 1 << (pin & 0x1F);\r
+    gpio_port->pmr2s = 1 << (pin & 0x1F);\r
+    break;\r
+    \r
+  case 7: // H function.\r
+    gpio_port->pmr0s = 1 << (pin & 0x1F);\r
+    gpio_port->pmr1s = 1 << (pin & 0x1F);\r
+    gpio_port->pmr2s = 1 << (pin & 0x1F);\r
+    break;\r
+#endif\r
+\r
+  default:\r
+    return GPIO_INVALID_ARGUMENT;\r
+  }\r
+\r
+  // Disable GPIO control.\r
+  gpio_port->gperc = 1 << (pin & 0x1F);\r
+\r
+  return GPIO_SUCCESS;\r
+}\r
+\r
+\r
+void gpio_enable_gpio(const gpio_map_t gpiomap, unsigned int size)\r
+{\r
+  unsigned int i;\r
+\r
+  for (i = 0; i < size; i++)\r
+  {\r
+    gpio_enable_gpio_pin(gpiomap->pin);\r
+    gpiomap++;\r
+  }\r
+}\r
+\r
+\r
+void gpio_enable_gpio_pin(unsigned int pin)\r
+{\r
+  volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];\r
+  gpio_port->oderc = 1 << (pin & 0x1F);\r
+  gpio_port->gpers = 1 << (pin & 0x1F);\r
+}\r
+\r
+\r
+// The open-drain mode is not synthesized on the current AVR32 products.\r
+// If one day some AVR32 products have this feature, the corresponding part\r
+// numbers should be listed in the #if below.\r
+// Note that other functions are available in this driver to use pins with open\r
+// drain in GPIO mode. The advantage of the open-drain mode functions over these\r
+// other functions is that they can be used not only in GPIO mode but also in\r
+// module mode.\r
+#if 0\r
+\r
+\r
+void gpio_enable_pin_open_drain(unsigned int pin)\r
+{\r
+  volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];\r
+  gpio_port->odmers = 1 << (pin & 0x1F);\r
+}\r
+\r
+\r
+void gpio_disable_pin_open_drain(unsigned int pin)\r
+{\r
+  volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];\r
+  gpio_port->odmerc = 1 << (pin & 0x1F);\r
+}\r
+\r
+\r
+#endif\r
+\r
+\r
+void gpio_enable_pin_pull_up(unsigned int pin)\r
+{\r
+  volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];\r
+  gpio_port->puers = 1 << (pin & 0x1F);\r
+#if defined(AVR32_GPIO_200_H_INCLUDED) || defined(AVR32_GPIO_210_H_INCLUDED) || defined(AVR32_GPIO_211_H_INCLUDED)\r
+  gpio_port->pderc = 1 << (pin & 0x1F);\r
+#endif\r
+}\r
+\r
+\r
+void gpio_disable_pin_pull_up(unsigned int pin)\r
+{\r
+  volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];\r
+  gpio_port->puerc = 1 << (pin & 0x1F);\r
+}\r
+\r
+#if defined(AVR32_GPIO_200_H_INCLUDED) || defined(AVR32_GPIO_210_H_INCLUDED) || defined(AVR32_GPIO_211_H_INCLUDED)\r
+// Added support of Pull-up Resistor, Pull-down Resistor and Buskeeper Control.\r
+\r
+/*! \brief Enables the pull-down resistor of a pin.\r
+ *\r
+ * \param pin The pin number.\r
+ */\r
+void gpio_enable_pin_pull_down(unsigned int pin)\r
+{\r
+  volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];\r
+  gpio_port->puerc = 1 << (pin & 0x1F);\r
+  gpio_port->pders = 1 << (pin & 0x1F);\r
+}\r
+\r
+/*! \brief Disables the pull-down resistor of a pin.\r
+ *\r
+ * \param pin The pin number.\r
+ */\r
+void gpio_disable_pin_pull_down(unsigned int pin)\r
+{\r
+  volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];\r
+  gpio_port->pderc = 1 << (pin & 0x1F);\r
+}\r
+\r
+/*! \brief Enables the buskeeper functionality on a pin.\r
+ *\r
+ * \param pin The pin number.\r
+ */\r
+void gpio_enable_pin_buskeeper(unsigned int pin)\r
+{\r
+  volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];\r
+  gpio_port->puers = 1 << (pin & 0x1F);\r
+  gpio_port->pders = 1 << (pin & 0x1F);\r
+}\r
+\r
+/*! \brief Disables the buskeeper functionality on a pin.\r
+ *\r
+ * \param pin The pin number.\r
+ */\r
+void gpio_disable_pin_buskeeper(unsigned int pin)\r
+{\r
+  volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];\r
+  gpio_port->puerc = 1 << (pin & 0x1F);\r
+  gpio_port->pderc = 1 << (pin & 0x1F);\r
+}\r
+\r
+#endif\r
+\r
+int gpio_get_pin_value(unsigned int pin)\r
+{\r
+  volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];\r
+  return (gpio_port->pvr >> (pin & 0x1F)) & 1;\r
+}\r
+\r
+\r
+int gpio_get_gpio_pin_output_value(unsigned int pin)\r
+{\r
+  volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];\r
+  return (gpio_port->ovr >> (pin & 0x1F)) & 1;\r
+}\r
+\r
+\r
+int gpio_get_gpio_open_drain_pin_output_value(unsigned int pin)\r
+{\r
+  volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];\r
+  return ((gpio_port->oder >> (pin & 0x1F)) & 1) ^ 1;\r
+}\r
+\r
+\r
+void gpio_set_gpio_pin(unsigned int pin)\r
+{\r
+  volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];\r
+\r
+  gpio_port->ovrs  = 1 << (pin & 0x1F); // Value to be driven on the I/O line: 1.\r
+  gpio_port->oders = 1 << (pin & 0x1F); // The GPIO output driver is enabled for that pin.\r
+  gpio_port->gpers = 1 << (pin & 0x1F); // The GPIO module controls that pin.\r
+}\r
+\r
+\r
+void gpio_clr_gpio_pin(unsigned int pin)\r
+{\r
+  volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];\r
+\r
+  gpio_port->ovrc  = 1 << (pin & 0x1F); // Value to be driven on the I/O line: 0.\r
+  gpio_port->oders = 1 << (pin & 0x1F); // The GPIO output driver is enabled for that pin.\r
+  gpio_port->gpers = 1 << (pin & 0x1F); // The GPIO module controls that pin.\r
+}\r
+\r
+\r
+void gpio_tgl_gpio_pin(unsigned int pin)\r
+{\r
+  volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];\r
+\r
+  gpio_port->ovrt  = 1 << (pin & 0x1F); // Toggle the I/O line.\r
+  gpio_port->oders = 1 << (pin & 0x1F); // The GPIO output driver is enabled for that pin.\r
+  gpio_port->gpers = 1 << (pin & 0x1F); // The GPIO module controls that pin.\r
+}\r
+\r
+\r
+void gpio_set_gpio_open_drain_pin(unsigned int pin)\r
+{\r
+  volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];\r
+\r
+  gpio_port->oderc = 1 << (pin & 0x1F); // The GPIO output driver is disabled for that pin.\r
+  gpio_port->gpers = 1 << (pin & 0x1F); // The GPIO module controls that pin.\r
+}\r
+\r
+\r
+void gpio_clr_gpio_open_drain_pin(unsigned int pin)\r
+{\r
+  volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];\r
+\r
+  gpio_port->ovrc  = 1 << (pin & 0x1F); // Value to be driven on the I/O line: 0.\r
+  gpio_port->oders = 1 << (pin & 0x1F); // The GPIO output driver is enabled for that pin.\r
+  gpio_port->gpers = 1 << (pin & 0x1F); // The GPIO module controls that pin.\r
+}\r
+\r
+\r
+void gpio_tgl_gpio_open_drain_pin(unsigned int pin)\r
+{\r
+  volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];\r
+\r
+  gpio_port->ovrc  = 1 << (pin & 0x1F); // Value to be driven on the I/O line if the GPIO output driver is enabled: 0.\r
+  gpio_port->odert = 1 << (pin & 0x1F); // The GPIO output driver is toggled for that pin.\r
+  gpio_port->gpers = 1 << (pin & 0x1F); // The GPIO module controls that pin.\r
+}\r
+\r
+\r
+void gpio_enable_pin_glitch_filter(unsigned int pin)\r
+{\r
+  volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];\r
+  gpio_port->gfers = 1 << (pin & 0x1F);\r
+}\r
+\r
+\r
+void gpio_disable_pin_glitch_filter(unsigned int pin)\r
+{\r
+  volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];\r
+  gpio_port->gferc = 1 << (pin & 0x1F);\r
+}\r
+\r
+/*! \brief Configure the edge detector of an input pin\r
+ *\r
+ * \param pin The pin number.\r
+ * \param mode The edge detection mode (\ref GPIO_PIN_CHANGE, \ref GPIO_RISING_EDGE\r
+ *             or \ref GPIO_FALLING_EDGE).\r
+ *\r
+ * \return \ref GPIO_SUCCESS or \ref GPIO_INVALID_ARGUMENT.\r
+ */\r
+static int gpio_configure_edge_detector(unsigned int pin, unsigned int mode)\r
+{\r
+  volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];\r
+  \r
+  // Configure the edge detector.\r
+  switch (mode)\r
+  {\r
+  case GPIO_PIN_CHANGE:\r
+    gpio_port->imr0c = 1 << (pin & 0x1F);\r
+    gpio_port->imr1c = 1 << (pin & 0x1F);\r
+    break;\r
+\r
+  case GPIO_RISING_EDGE:\r
+    gpio_port->imr0s = 1 << (pin & 0x1F);\r
+    gpio_port->imr1c = 1 << (pin & 0x1F);\r
+    break;\r
+\r
+  case GPIO_FALLING_EDGE:\r
+    gpio_port->imr0c = 1 << (pin & 0x1F);\r
+    gpio_port->imr1s = 1 << (pin & 0x1F);\r
+    break;\r
+\r
+  default:\r
+    return GPIO_INVALID_ARGUMENT;\r
+  }\r
+\r
+  return GPIO_SUCCESS;\r
+}\r
+\r
+\r
+int gpio_enable_pin_interrupt(unsigned int pin, unsigned int mode)\r
+{\r
+  volatile avr32_gpio_port_t  *gpio_port = &GPIO.port[pin >> 5];\r
+\r
+  // Enable the glitch filter.\r
+  gpio_port->gfers = 1 << (pin & 0x1F);\r
+\r
+  // Configure the edge detector.\r
+  if(GPIO_INVALID_ARGUMENT == gpio_configure_edge_detector(pin, mode))\r
+    return(GPIO_INVALID_ARGUMENT);\r
+\r
+  // Enable interrupt.\r
+  gpio_port->iers = 1 << (pin & 0x1F);\r
+\r
+  return GPIO_SUCCESS;\r
+}\r
+\r
+\r
+void gpio_disable_pin_interrupt(unsigned int pin)\r
+{\r
+  volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];\r
+  gpio_port->ierc = 1 << (pin & 0x1F);\r
+}\r
+\r
+\r
+int gpio_get_pin_interrupt_flag(unsigned int pin)\r
+{\r
+  volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];\r
+  return (gpio_port->ifr >> (pin & 0x1F)) & 1;\r
+}\r
+\r
+\r
+void gpio_clear_pin_interrupt_flag(unsigned int pin)\r
+{\r
+  volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];\r
+  gpio_port->ifrc = 1 << (pin & 0x1F);\r
+}\r
+\r
+\r
+//#\r
+//# Peripheral Event System Support.\r
+//#\r
+#if UC3L\r
+int gpio_configure_pin_periph_event_mode(unsigned int pin, unsigned int mode, unsigned int use_igf)\r
+{\r
+  volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];\r
+\r
+  if(TRUE == use_igf)\r
+  {\r
+    // Enable the glitch filter.\r
+    gpio_port->gfers = 1 << (pin & 0x1F);\r
+  }\r
+  else\r
+  {\r
+    // Disable the glitch filter.\r
+    gpio_port->gferc = 1 << (pin & 0x1F);\r
+  }\r
+\r
+  // Configure the edge detector.\r
+  return(gpio_configure_edge_detector(pin, mode));\r
+}\r
+\r
+#endif\r
+\r
+//! @}\r

diff --git a/Demo/AVR32_UC3A_GCC/Atmel_SW_Framework/DRIVERS/GPIO/gpio.h b/Demo/AVR32_UC3A_GCC/Atmel_SW_Framework/DRIVERS/GPIO/gpio.h
new file mode 100644 (file)
index 0000000..3aa700b
--- /dev/null
+++ b/Demo/AVR32_UC3A_GCC/Atmel_SW_Framework/DRIVERS/GPIO/gpio.h
@@ -0,0 +1,583 @@
+/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */\r
+
+/*This file has been prepared for Doxygen automatic documentation generation.*/\r
+/*! \file *********************************************************************\r
+ *\r
+ * \brief GPIO header for AVR32 UC3.\r
+ *\r
+ * This file contains basic GPIO driver functions.\r
+ *\r
+ * - Compiler:           IAR EWAVR32 and GNU GCC for AVR32\r
+ * - Supported devices:  All AVR32 devices with a GPIO module can be used.\r
+ * - AppNote:\r
+ *\r
+ * \author               Atmel Corporation: http://www.atmel.com \n\r
+ *                       Support and FAQ: http://support.atmel.no/\r
+ *\r
+ *****************************************************************************/\r
+\r
+/* Copyright (c) 2009 Atmel Corporation. All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice, this\r
+ * list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an Atmel\r
+ * AVR product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\r
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\r
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\r
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE\r
+ *\r
+ */\r
+\r
+#ifndef _GPIO_H_\r
+#define _GPIO_H_\r
+\r
+#include <avr32/io.h>\r
+#include "compiler.h"\r
+\r
+/*! \name Return Values of the GPIO API\r
+ */\r
+//! @{\r
+#define GPIO_SUCCESS            0 //!< Function successfully completed.\r
+#define GPIO_INVALID_ARGUMENT   1 //!< Input parameters are out of range.\r
+//! @}\r
+\r
+\r
+/*! \name Interrupt Trigger Modes\r
+ */\r
+//! @{\r
+#define GPIO_PIN_CHANGE         0 //!< Interrupt triggered upon pin change.\r
+#define GPIO_RISING_EDGE        1 //!< Interrupt triggered upon rising edge.\r
+#define GPIO_FALLING_EDGE       2 //!< Interrupt triggered upon falling edge.\r
+//! @}\r
+\r
+\r
+//! A type definition of pins and modules connectivity.\r
+typedef struct\r
+{\r
+  unsigned char pin;              //!< Module pin.\r
+  unsigned char function;         //!< Module function.\r
+} gpio_map_t[];\r
+\r
+\r
+/*! \name Peripheral Bus Interface\r
+ *\r
+ * Low-speed interface with a non-deterministic number of clock cycles per\r
+ * access.\r
+ *\r
+ * This interface operates with lower clock frequencies (fPB <= fCPU), and its\r
+ * timing is not deterministic since it needs to access a shared bus which may\r
+ * be heavily loaded.\r
+ *\r
+ * \note This interface is immediately available without initialization.\r
+ */\r
+//! @{\r
+\r
+/*! \brief Enables specific module modes for a set of pins.\r
+ *\r
+ * \param gpiomap The pin map.\r
+ * \param size The number of pins in \a gpiomap.\r
+ *\r
+ * \return \ref GPIO_SUCCESS or \ref GPIO_INVALID_ARGUMENT.\r
+ */\r
+extern int gpio_enable_module(const gpio_map_t gpiomap, unsigned int size);\r
+\r
+/*! \brief Enables a specific module mode for a pin.\r
+ *\r
+ * \param pin The pin number.\n\r
+ *            Refer to the product header file `uc3x.h' (where x is the part\r
+ *            number; e.g. x = a0512) for module pins. E.g., to enable a PWM\r
+ *            channel output, the pin number can be AVR32_PWM_3_PIN for PWM\r
+ *            channel 3.\r
+ * \param function The pin function.\n\r
+ *                 Refer to the product header file `uc3x.h' (where x is the\r
+ *                 part number; e.g. x = a0512) for module pin functions. E.g.,\r
+ *                 to enable a PWM channel output, the pin function can be\r
+ *                 AVR32_PWM_3_FUNCTION for PWM channel 3.\r
+ *\r
+ * \return \ref GPIO_SUCCESS or \ref GPIO_INVALID_ARGUMENT.\r
+ */\r
+extern int gpio_enable_module_pin(unsigned int pin, unsigned int function);\r
+\r
+/*! \brief Enables the GPIO mode of a set of pins.\r
+ *\r
+ * \param gpiomap The pin map.\r
+ * \param size The number of pins in \a gpiomap.\r
+ */\r
+extern void gpio_enable_gpio(const gpio_map_t gpiomap, unsigned int size);\r
+\r
+/*! \brief Enables the GPIO mode of a pin.\r
+ *\r
+ * \param pin The pin number.\n\r
+ *            Refer to the product header file `uc3x.h' (where x is the part\r
+ *            number; e.g. x = a0512) for pin definitions. E.g., to enable the\r
+ *            GPIO mode of PX21, AVR32_PIN_PX21 can be used. Module pins such as\r
+ *            AVR32_PWM_3_PIN for PWM channel 3 can also be used to release\r
+ *            module pins for GPIO.\r
+ */\r
+extern void gpio_enable_gpio_pin(unsigned int pin);\r
+\r
+// The open-drain mode is not synthesized on the current AVR32 products.\r
+// If one day some AVR32 products have this feature, the corresponding part\r
+// numbers should be listed in the #if below.\r
+// Note that other functions are available in this driver to use pins with open\r
+// drain in GPIO mode. The advantage of the open-drain mode functions over these\r
+// other functions is that they can be used not only in GPIO mode but also in\r
+// module mode.\r
+#if 0\r
+\r
+/*! \brief Enables the open-drain mode of a pin.\r
+ *\r
+ * \param pin The pin number.\r
+ */\r
+extern void gpio_enable_pin_open_drain(unsigned int pin);\r
+\r
+/*! \brief Disables the open-drain mode of a pin.\r
+ *\r
+ * \param pin The pin number.\r
+ */\r
+extern void gpio_disable_pin_open_drain(unsigned int pin);\r
+\r
+#endif\r
+\r
+/*! \brief Enables the pull-up resistor of a pin.\r
+ *\r
+ * \param pin The pin number.\r
+ */\r
+extern void gpio_enable_pin_pull_up(unsigned int pin);\r
+\r
+/*! \brief Disables the pull-up resistor of a pin.\r
+ *\r
+ * \param pin The pin number.\r
+ */\r
+extern void gpio_disable_pin_pull_up(unsigned int pin);\r
+\r
+#if defined(AVR32_GPIO_200_H_INCLUDED) || defined(AVR32_GPIO_210_H_INCLUDED) || defined(AVR32_GPIO_211_H_INCLUDED)\r
+// Added support of Pull-up Resistor, Pull-down Resistor and Buskeeper Control.\r
+\r
+/*! \brief Enables the pull-down resistor of a pin.\r
+ *\r
+ * \param pin The pin number.\r
+ */\r
+extern void gpio_enable_pin_pull_down(unsigned int pin);\r
+\r
+/*! \brief Disables the pull-down resistor of a pin.\r
+ *\r
+ * \param pin The pin number.\r
+ */\r
+extern void gpio_disable_pin_pull_down(unsigned int pin);\r
+\r
+/*! \brief Enables the buskeeper functionality on a pin.\r
+ *\r
+ * \param pin The pin number.\r
+ */\r
+extern void gpio_enable_pin_buskeeper(unsigned int pin);\r
+\r
+/*! \brief Disables the buskeeper functionality on a pin.\r
+ *\r
+ * \param pin The pin number.\r
+ */\r
+extern void gpio_disable_pin_buskeeper(unsigned int pin);\r
+\r
+#endif\r
+\r
+/*! \brief Returns the value of a pin.\r
+ *\r
+ * \param pin The pin number.\r
+ *\r
+ * \return The pin value.\r
+ */\r
+extern int gpio_get_pin_value(unsigned int pin);\r
+\r
+/*! \brief Returns the output value set for a GPIO pin.\r
+ *\r
+ * \param pin The pin number.\r
+ *\r
+ * \return The pin output value.\r
+ *\r
+ * \note This function must be used in conjunction with \ref gpio_set_gpio_pin,\r
+ *       \ref gpio_clr_gpio_pin and \ref gpio_tgl_gpio_pin.\r
+ */\r
+extern int gpio_get_gpio_pin_output_value(unsigned int pin);\r
+\r
+/*! \brief Returns the output value set for a GPIO pin using open drain.\r
+ *\r
+ * \param pin The pin number.\r
+ *\r
+ * \return The pin output value.\r
+ *\r
+ * \note This function must be used in conjunction with\r
+ *       \ref gpio_set_gpio_open_drain_pin, \ref gpio_clr_gpio_open_drain_pin\r
+ *       and \ref gpio_tgl_gpio_open_drain_pin.\r
+ */\r
+extern int gpio_get_gpio_open_drain_pin_output_value(unsigned int pin);\r
+\r
+/*! \brief Drives a GPIO pin to 1.\r
+ *\r
+ * \param pin The pin number.\r
+ */\r
+extern void gpio_set_gpio_pin(unsigned int pin);\r
+\r
+/*! \brief Drives a GPIO pin to 0.\r
+ *\r
+ * \param pin The pin number.\r
+ */\r
+extern void gpio_clr_gpio_pin(unsigned int pin);\r
+\r
+/*! \brief Toggles a GPIO pin.\r
+ *\r
+ * \param pin The pin number.\r
+ */\r
+extern void gpio_tgl_gpio_pin(unsigned int pin);\r
+\r
+/*! \brief Drives a GPIO pin to 1 using open drain.\r
+ *\r
+ * \param pin The pin number.\r
+ */\r
+extern void gpio_set_gpio_open_drain_pin(unsigned int pin);\r
+\r
+/*! \brief Drives a GPIO pin to 0 using open drain.\r
+ *\r
+ * \param pin The pin number.\r
+ */\r
+extern void gpio_clr_gpio_open_drain_pin(unsigned int pin);\r
+\r
+/*! \brief Toggles a GPIO pin using open drain.\r
+ *\r
+ * \param pin The pin number.\r
+ */\r
+extern void gpio_tgl_gpio_open_drain_pin(unsigned int pin);\r
+\r
+/*! \brief Enables the glitch filter of a pin.\r
+ *\r
+ * When the glitch filter is enabled, a glitch with duration of less than 1\r
+ * clock cycle is automatically rejected, while a pulse with duration of 2 clock\r
+ * cycles or more is accepted. For pulse durations between 1 clock cycle and 2\r
+ * clock cycles, the pulse may or may not be taken into account, depending on\r
+ * the precise timing of its occurrence. Thus for a pulse to be guaranteed\r
+ * visible it must exceed 2 clock cycles, whereas for a glitch to be reliably\r
+ * filtered out, its duration must not exceed 1 clock cycle. The filter\r
+ * introduces 2 clock cycles latency.\r
+ *\r
+ * \param pin The pin number.\r
+ */\r
+extern void gpio_enable_pin_glitch_filter(unsigned int pin);\r
+\r
+/*! \brief Disables the glitch filter of a pin.\r
+ *\r
+ * \param pin The pin number.\r
+ */\r
+extern void gpio_disable_pin_glitch_filter(unsigned int pin);\r
+\r
+/*! \brief Enables the interrupt of a pin with the specified settings.\r
+ *\r
+ * \param pin The pin number.\r
+ * \param mode The trigger mode (\ref GPIO_PIN_CHANGE, \ref GPIO_RISING_EDGE or\r
+ *             \ref GPIO_FALLING_EDGE).\r
+ *\r
+ * \return \ref GPIO_SUCCESS or \ref GPIO_INVALID_ARGUMENT.\r
+ */\r
+extern int gpio_enable_pin_interrupt(unsigned int pin, unsigned int mode);\r
+\r
+/*! \brief Disables the interrupt of a pin.\r
+ *\r
+ * \param pin The pin number.\r
+ */\r
+extern void gpio_disable_pin_interrupt(unsigned int pin);\r
+\r
+/*! \brief Gets the interrupt flag of a pin.\r
+ *\r
+ * \param pin The pin number.\r
+ *\r
+ * \return The pin interrupt flag.\r
+ */\r
+extern int gpio_get_pin_interrupt_flag(unsigned int pin);\r
+\r
+/*! \brief Clears the interrupt flag of a pin.\r
+ *\r
+ * \param pin The pin number.\r
+ */\r
+extern void gpio_clear_pin_interrupt_flag(unsigned int pin);\r
+\r
+//! @}\r
+\r
+\r
+#if (defined AVR32_GPIO_LOCAL_ADDRESS)\r
+/*! \name Local Bus Interface\r
+ *\r
+ * High-speed interface with only one clock cycle per access.\r
+ *\r
+ * This interface operates with high clock frequency (fCPU), and its timing is\r
+ * deterministic since it does not need to access a shared bus which may be\r
+ * heavily loaded.\r
+ *\r
+ * \warning To use this interface, the clock frequency of the peripheral bus on\r
+ *          which the GPIO peripheral is connected must be set to the CPU clock\r
+ *          frequency (fPB = fCPU).\r
+ *\r
+ * \note This interface has to be initialized in order to be available.\r
+ */\r
+//! @{\r
+\r
+/*! \brief Enables the local bus interface for GPIO.\r
+ *\r
+ * \note This function must have been called at least once before using other\r
+ *       functions in this interface.\r
+ */\r
+#if (defined __GNUC__)\r
+__attribute__((__always_inline__))\r
+#endif\r
+extern __inline__ void gpio_local_init(void)\r
+{\r
+  Set_system_register(AVR32_CPUCR,\r
+                      Get_system_register(AVR32_CPUCR) | AVR32_CPUCR_LOCEN_MASK);\r
+}\r
+\r
+/*! \brief Enables the output driver of a pin.\r
+ *\r
+ * \param pin The pin number.\r
+ *\r
+ * \note \ref gpio_local_init must have been called beforehand.\r
+ *\r
+ * \note This function does not enable the GPIO mode of the pin.\r
+ *       \ref gpio_enable_gpio_pin can be called for this purpose.\r
+ */\r
+#if (defined __GNUC__)\r
+__attribute__((__always_inline__))\r
+#endif\r
+extern __inline__ void gpio_local_enable_pin_output_driver(unsigned int pin)\r
+{\r
+  AVR32_GPIO_LOCAL.port[pin >> 5].oders = 1 << (pin & 0x1F);\r
+}\r
+\r
+/*! \brief Disables the output driver of a pin.\r
+ *\r
+ * \param pin The pin number.\r
+ *\r
+ * \note \ref gpio_local_init must have been called beforehand.\r
+ */\r
+#if (defined __GNUC__)\r
+__attribute__((__always_inline__))\r
+#endif\r
+extern __inline__ void gpio_local_disable_pin_output_driver(unsigned int pin)\r
+{\r
+  AVR32_GPIO_LOCAL.port[pin >> 5].oderc = 1 << (pin & 0x1F);\r
+}\r
+\r
+/*! \brief Returns the value of a pin.\r
+ *\r
+ * \param pin The pin number.\r
+ *\r
+ * \return The pin value.\r
+ *\r
+ * \note \ref gpio_local_init must have been called beforehand.\r
+ */\r
+#if (defined __GNUC__)\r
+__attribute__((__always_inline__))\r
+#endif\r
+extern __inline__ int gpio_local_get_pin_value(unsigned int pin)\r
+{\r
+  return (AVR32_GPIO_LOCAL.port[pin >> 5].pvr >> (pin & 0x1F)) & 1;\r
+}\r
+\r
+/*! \brief Drives a GPIO pin to 1.\r
+ *\r
+ * \param pin The pin number.\r
+ *\r
+ * \note \ref gpio_local_init must have been called beforehand.\r
+ *\r
+ * \note This function does not enable the GPIO mode of the pin nor its output\r
+ *       driver. \ref gpio_enable_gpio_pin and\r
+ *       \ref gpio_local_enable_pin_output_driver can be called for this\r
+ *       purpose.\r
+ */\r
+#if (defined __GNUC__)\r
+__attribute__((__always_inline__))\r
+#endif\r
+extern __inline__ void gpio_local_set_gpio_pin(unsigned int pin)\r
+{\r
+  AVR32_GPIO_LOCAL.port[pin >> 5].ovrs = 1 << (pin & 0x1F);\r
+}\r
+\r
+/*! \brief Drives a GPIO pin to 0.\r
+ *\r
+ * \param pin The pin number.\r
+ *\r
+ * \note \ref gpio_local_init must have been called beforehand.\r
+ *\r
+ * \note This function does not enable the GPIO mode of the pin nor its output\r
+ *       driver. \ref gpio_enable_gpio_pin and\r
+ *       \ref gpio_local_enable_pin_output_driver can be called for this\r
+ *       purpose.\r
+ */\r
+#if (defined __GNUC__)\r
+__attribute__((__always_inline__))\r
+#endif\r
+extern __inline__ void gpio_local_clr_gpio_pin(unsigned int pin)\r
+{\r
+  AVR32_GPIO_LOCAL.port[pin >> 5].ovrc = 1 << (pin & 0x1F);\r
+}\r
+\r
+/*! \brief Toggles a GPIO pin.\r
+ *\r
+ * \param pin The pin number.\r
+ *\r
+ * \note \ref gpio_local_init must have been called beforehand.\r
+ *\r
+ * \note This function does not enable the GPIO mode of the pin nor its output\r
+ *       driver. \ref gpio_enable_gpio_pin and\r
+ *       \ref gpio_local_enable_pin_output_driver can be called for this\r
+ *       purpose.\r
+ */\r
+#if (defined __GNUC__)\r
+__attribute__((__always_inline__))\r
+#endif\r
+extern __inline__ void gpio_local_tgl_gpio_pin(unsigned int pin)\r
+{\r
+  AVR32_GPIO_LOCAL.port[pin >> 5].ovrt = 1 << (pin & 0x1F);\r
+}\r
+\r
+/*! \brief Initializes the configuration of a GPIO pin so that it can be used\r
+ *         with GPIO open-drain functions.\r
+ *\r
+ * \note This function must have been called at least once before using\r
+ *       \ref gpio_local_set_gpio_open_drain_pin,\r
+ *       \ref gpio_local_clr_gpio_open_drain_pin or\r
+ *       \ref gpio_local_tgl_gpio_open_drain_pin.\r
+ */\r
+#if (defined __GNUC__)\r
+__attribute__((__always_inline__))\r
+#endif\r
+extern __inline__ void gpio_local_init_gpio_open_drain_pin(unsigned int pin)\r
+{\r
+  AVR32_GPIO_LOCAL.port[pin >> 5].ovrc = 1 << (pin & 0x1F);\r
+}\r
+\r
+/*! \brief Drives a GPIO pin to 1 using open drain.\r
+ *\r
+ * \param pin The pin number.\r
+ *\r
+ * \note \ref gpio_local_init and \ref gpio_local_init_gpio_open_drain_pin must\r
+ *       have been called beforehand.\r
+ *\r
+ * \note This function does not enable the GPIO mode of the pin.\r
+ *       \ref gpio_enable_gpio_pin can be called for this purpose.\r
+ */\r
+#if (defined __GNUC__)\r
+__attribute__((__always_inline__))\r
+#endif\r
+extern __inline__ void gpio_local_set_gpio_open_drain_pin(unsigned int pin)\r
+{\r
+  AVR32_GPIO_LOCAL.port[pin >> 5].oderc = 1 << (pin & 0x1F);\r
+}\r
+\r
+/*! \brief Drives a GPIO pin to 0 using open drain.\r
+ *\r
+ * \param pin The pin number.\r
+ *\r
+ * \note \ref gpio_local_init and \ref gpio_local_init_gpio_open_drain_pin must\r
+ *       have been called beforehand.\r
+ *\r
+ * \note This function does not enable the GPIO mode of the pin.\r
+ *       \ref gpio_enable_gpio_pin can be called for this purpose.\r
+ */\r
+#if (defined __GNUC__)\r
+__attribute__((__always_inline__))\r
+#endif\r
+extern __inline__ void gpio_local_clr_gpio_open_drain_pin(unsigned int pin)\r
+{\r
+  AVR32_GPIO_LOCAL.port[pin >> 5].oders = 1 << (pin & 0x1F);\r
+}\r
+\r
+/*! \brief Toggles a GPIO pin using open drain.\r
+ *\r
+ * \param pin The pin number.\r
+ *\r
+ * \note \ref gpio_local_init and \ref gpio_local_init_gpio_open_drain_pin must\r
+ *       have been called beforehand.\r
+ *\r
+ * \note This function does not enable the GPIO mode of the pin.\r
+ *       \ref gpio_enable_gpio_pin can be called for this purpose.\r
+ */\r
+#if (defined __GNUC__)\r
+__attribute__((__always_inline__))\r
+#endif\r
+extern __inline__ void gpio_local_tgl_gpio_open_drain_pin(unsigned int pin)\r
+{\r
+  AVR32_GPIO_LOCAL.port[pin >> 5].odert = 1 << (pin & 0x1F);\r
+}\r
+\r
+//! @}\r
+#endif // AVR32_GPIO_LOCAL_ADDRESS\r
+\r
+#if UC3L\r
+//! @{\r
+/*! \name Peripheral Event System support\r
+ *\r
+ * The GPIO can be programmed to output peripheral events whenever an interrupt\r
+ * condition is detected, such as pin value change, or only when a rising or\r
+ * falling edge is detected.\r
+ *\r
+ */\r
+\r
+/*! \brief Enables the peripheral event generation of a pin.\r
+ *\r
+ * \param pin The pin number.\r
+ *\r
+ */\r
+#if (defined __GNUC__)\r
+__attribute__((__always_inline__))\r
+#endif\r
+extern __inline__ void gpio_enable_pin_periph_event(unsigned int pin)\r
+{\r
+  AVR32_GPIO.port[pin >> 5].oderc = 1 << (pin & 0x1F); // The GPIO output driver is disabled for that pin.\r
+  AVR32_GPIO.port[pin >> 5].evers = 1 << (pin & 0x1F);\r
+}\r
+\r
+/*! \brief Disables the peripheral event generation of a pin.\r
+ *\r
+ * \param pin The pin number.\r
+ *\r
+ */\r
+#if (defined __GNUC__)\r
+__attribute__((__always_inline__))\r
+#endif\r
+extern __inline__ void gpio_disable_pin_periph_event(unsigned int pin)\r
+{\r
+  AVR32_GPIO.port[pin >> 5].everc = 1 << (pin & 0x1F);\r
+}\r
+\r
+/*! \brief Configure the peripheral event trigger mode of a pin\r
+ *\r
+ * \param pin The pin number.\r
+ * \param mode The trigger mode (\ref GPIO_PIN_CHANGE, \ref GPIO_RISING_EDGE or\r
+ *             \ref GPIO_FALLING_EDGE).\r
+ * \param use_igf use the Input Glitch Filter (TRUE) or not (FALSE).\r
+ *\r
+ * \return \ref GPIO_SUCCESS or \ref GPIO_INVALID_ARGUMENT.\r
+ */\r
+extern int gpio_configure_pin_periph_event_mode(unsigned int pin, unsigned int mode, unsigned int use_igf);\r
+\r
+//! @}\r
+#endif\r
+\r
+\r
+#endif  // _GPIO_H_\r

diff --git a/Demo/AVR32_UC3A_GCC/Atmel_SW_Framework/DRIVERS/GPIO/readme.html b/Demo/AVR32_UC3A_GCC/Atmel_SW_Framework/DRIVERS/GPIO/readme.html
new file mode 100644 (file)
index 0000000..10803f0
--- /dev/null
+++ b/Demo/AVR32_UC3A_GCC/Atmel_SW_Framework/DRIVERS/GPIO/readme.html
@@ -0,0 +1,40 @@
+<!doctype HTML public "-//W3C//DTD HTML 4.0 Frameset//EN">
+<html>
+   <head>
+      <link rel="stylesheet" type="text/css" href="../../.docsrc/AVR32_ns.css">
+   </head>
+   <body>
+   <div id="wrapper">
+<p align="left" class="whs2"><a href="../DRIVERS_Readme.html"<font color="red"></font>Back to DRIVERS page</a></p>
+<h1 align="center" class="whs1">AVR UC3 Series Software Framework: General-Purpose Input/Output (GPIO) Driver<br>
+</h1>
+
+<p align="center" class="whs2">Copyright &copy; 2007 Atmel Corporation</p>
+
+<h2>Introduction</h2>
+    <p>The General-Purpose Input/Output (GPIO) gives access to the MCU pins.
+    The GPIO can be interfaced through a peripheral bus or the local bus.</p>
+
+<p>&nbsp;</p>
+
+<h2>GPIO Software Driver</h2>
+
+    <p>This driver provides an API to get access to the main features of the GPIO controller.</p>
+    <p>&nbsp;</p>
+    <p>The driver is composed of <a href="gpio.c">gpio.c</a> and <a href="gpio.h">gpio.h</a> (for accurate API description, read this header file).</p>
+    <p>&nbsp;</p>
+
+<h2>GPIO Software Driver Examples</h2>
+    <p>Two examples are currently available:
+       <li><a href="./PERIPHERAL_BUS_EXAMPLE/readme.html"> demonstrates the peripheral bus interface</a>;</li>
+       <li><a href="./LOCAL_BUS_EXAMPLE/readme.html"> demonstrates the local bus interface</a>.</li>
+    </p>
+<p>&nbsp;</p>
+
+<hr align="center" width="50%" class="whs4">
+
+    <p class=legalfooter>AVR is a registered trademark of
+    Atmel Corporation.</p>
+</div>
+   </body>
+</html>

diff --git a/Demo/AVR32_UC3A_GCC/Atmel_SW_Framework/DRIVERS/INTC/exception._S b/Demo/AVR32_UC3A_GCC/Atmel_SW_Framework/DRIVERS/INTC/exception._S
new file mode 100644 (file)
index 0000000..8e32d0a
--- /dev/null
+++ b/Demo/AVR32_UC3A_GCC/Atmel_SW_Framework/DRIVERS/INTC/exception._S
@@ -0,0 +1,239 @@
+/* This file is part of the ATMEL AVR32-SoftwareFramework-AT32UC3-1.5.0 Release */\r
+
+/*This file is prepared for Doxygen automatic documentation generation.*/
+/*! \file *********************************************************************
+ *
+ * \brief Exception and interrupt vectors.
+ *
+ * This file maps all events supported by an AVR32.
+ *
+ * - Compiler:           GNU GCC for AVR32
+ * - Supported devices:  All AVR32 devices with an INTC module can be used.
+ * - AppNote:
+ *
+ * \author               Atmel Corporation: http://www.atmel.com \n
+ *                       Support and FAQ: http://support.atmel.no/
+ *
+ ******************************************************************************/
+
+/* Copyright (c) 2009 Atmel Corporation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an Atmel
+ * AVR product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
+ *
+ */
+
+#if !__AVR32_UC__ && !__AVR32_AP__
+  #error Implementation of the AVR32 architecture not supported by the INTC driver.
+#endif
+
+
+#include <avr32/io.h>
+
+
+//! @{
+//! \verbatim
+
+
+  .section  .exception, "ax", @progbits
+
+
+// Start of Exception Vector Table.
+
+  // EVBA must be aligned with a power of two strictly greater than the EVBA-
+  // relative offset of the last vector.
+  .balign 0x200
+
+  // Export symbol.
+  .global _evba
+  .type _evba, @function
+_evba:
+
+        .org  0x000
+        // Unrecoverable Exception.
+_handle_Unrecoverable_Exception:
+        rjmp $
+
+        .org  0x004
+        // TLB Multiple Hit.
+_handle_TLB_Multiple_Hit:
+        rjmp $
+
+        .org  0x008
+        // Bus Error Data Fetch.
+_handle_Bus_Error_Data_Fetch:
+        rjmp $
+
+        .org  0x00C
+         // Bus Error Instruction Fetch.
+_handle_Bus_Error_Instruction_Fetch:
+        rjmp $
+
+        .org  0x010
+        // NMI.
+_handle_NMI:
+        rjmp $
+
+        .org  0x014
+        // Instruction Address.
+_handle_Instruction_Address:
+        rjmp $
+
+        .org  0x018
+        // ITLB Protection.
+_handle_ITLB_Protection:
+        rjmp $
+
+        .org  0x01C
+        // Breakpoint.
+_handle_Breakpoint:
+        rjmp $
+
+        .org  0x020
+        // Illegal Opcode.
+_handle_Illegal_Opcode:
+        rjmp $
+
+        .org  0x024
+        // Unimplemented Instruction.
+_handle_Unimplemented_Instruction:
+        rjmp $
+
+        .org  0x028
+        // Privilege Violation.
+_handle_Privilege_Violation:
+        rjmp $
+
+        .org  0x02C
+        // Floating-Point: UNUSED IN AVR32UC and AVR32AP.
+_handle_Floating_Point:
+        rjmp $
+
+        .org  0x030
+        // Coprocessor Absent: UNUSED IN AVR32UC.
+_handle_Coprocessor_Absent:
+        rjmp $
+
+        .org  0x034
+        // Data Address (Read).
+_handle_Data_Address_Read:
+        rjmp $
+
+        .org  0x038
+        // Data Address (Write).
+_handle_Data_Address_Write:
+        rjmp $
+
+        .org  0x03C
+        // DTLB Protection (Read).
+_handle_DTLB_Protection_Read:
+        rjmp $
+
+        .org  0x040
+        // DTLB Protection (Write).
+_handle_DTLB_Protection_Write:
+        rjmp $
+
+        .org  0x044
+        // DTLB Modified: UNUSED IN AVR32UC.
+_handle_DTLB_Modified:
+        rjmp $
+
+        .org  0x050
+        // ITLB Miss.
+_handle_ITLB_Miss:
+        rjmp $
+
+        .org  0x060
+        // DTLB Miss (Read).
+_handle_DTLB_Miss_Read:
+        rjmp $
+
+        .org  0x070
+        // DTLB Miss (Write).
+_handle_DTLB_Miss_Write:
+        rjmp $
+
+        .org  0x100
+        // Supervisor Call.
+_handle_Supervisor_Call:
+        rjmp $
+
+
+// Interrupt support.
+// The interrupt controller must provide the offset address relative to EVBA.
+// Important note:
+//   All interrupts call a C function named _get_interrupt_handler.
+//   This function will read group and interrupt line number to then return in
+//   R12 a pointer to a user-provided interrupt handler.
+
+  .balign 4
+
+  .irp    priority, 0, 1, 2, 3
+_int\priority:
+#if __AVR32_UC__
+  // R8-R12, LR, PC and SR are automatically pushed onto the system stack by the
+  // CPU upon interrupt entry. No other register is saved by hardware.
+#elif __AVR32_AP__
+  // PC and SR are automatically saved in respectively RAR_INTx and RSR_INTx by
+  // the CPU upon interrupt entry. No other register is saved by hardware.
+  pushm   r8-r12, lr
+#endif
+  mov     r12, \priority  // Pass the int_level parameter to the _get_interrupt_handler function.
+  call    _get_interrupt_handler
+  cp.w    r12, 0          // Get the pointer to the interrupt handler returned by the function.
+#if __AVR32_UC__
+  movne   pc, r12         // If this was not a spurious interrupt (R12 != NULL), jump to the handler.
+#elif __AVR32_AP__
+  breq    spint\priority  // If this was a spurious interrupt (R12 == NULL), branch.
+  st.w    --sp, r12       // Push the pointer to the interrupt handler onto the system stack since no register may be altered.
+  popm    r8-r12, lr, pc  // Restore registers and jump to the handler.
+spint\priority:
+  popm    r8-r12, lr
+#endif
+  rete                    // If this was a spurious interrupt (R12 == NULL), return from event handler.
+  .endr
+
+
+// Constant data area.
+
+  .balign 4
+
+  // Values to store in the interrupt priority registers for the various interrupt priority levels.
+  // The interrupt priority registers contain the interrupt priority level and
+  // the EVBA-relative interrupt vector offset.
+  .global ipr_val
+  .type ipr_val, @object
+ipr_val:
+  .word (AVR32_INTC_INT0 << AVR32_INTC_IPR_INTLEVEL_OFFSET) | (_int0 - _evba),\
+        (AVR32_INTC_INT1 << AVR32_INTC_IPR_INTLEVEL_OFFSET) | (_int1 - _evba),\
+        (AVR32_INTC_INT2 << AVR32_INTC_IPR_INTLEVEL_OFFSET) | (_int2 - _evba),\
+        (AVR32_INTC_INT3 << AVR32_INTC_IPR_INTLEVEL_OFFSET) | (_int3 - _evba)
+
+
+//! \endverbatim
+//! @}

diff --git a/Demo/AVR32_UC3A_GCC/Atmel_SW_Framework/DRIVERS/INTC/exception._s82 b/Demo/AVR32_UC3A_GCC/Atmel_SW_Framework/DRIVERS/INTC/exception._s82
new file mode 100644 (file)
index 0000000..e477128
--- /dev/null
+++ b/Demo/AVR32_UC3A_GCC/Atmel_SW_Framework/DRIVERS/INTC/exception._s82
@@ -0,0 +1,247 @@
+/*This file is prepared for Doxygen automatic documentation generation.*/\r
+/*! \file *********************************************************************\r
+ *\r
+ * \brief Exception and interrupt vectors.\r
+ *\r
+ * This file maps all events supported by an AVR32.\r
+ *\r
+ * - Compiler:           IAR EWAVR32\r
+ * - Supported devices:  All AVR32 devices with an INTC module can be used.\r
+ * - AppNote:\r
+ *\r
+ * \author               Atmel Corporation: http://www.atmel.com \n\r
+ *                       Support and FAQ: http://support.atmel.no/\r
+ *\r
+ ******************************************************************************/\r
+\r
+/* Copyright (c) 2009 Atmel Corporation. All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice, this\r
+ * list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an Atmel\r
+ * AVR product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\r
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\r
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\r
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE\r
+ *\r
+ */\r
+\r
+#if __CORE__ != __AVR32A__ && __CORE__ != __AVR32B__\r
+  #error Implementation of the AVR32 architecture not supported by the INTC driver.\r
+#endif\r
+\r
+\r
+#include <avr32/io.h>\r
+\r
+\r
+//! @{\r
+//! \verbatim\r
+\r
+\r
+// Start of Exception Vector Table.\r
+\r
+  // EVBA must be aligned with a power of two strictly greater than the EVBA-\r
+  // relative offset of the last vector.\r
+  COMMON  EVTAB:CODE:ROOT(9)\r
+\r
+\r
+  // Force EVBA initialization.\r
+  EXTERN  ??init_EVBA\r
+  REQUIRE ??init_EVBA\r
+\r
+  // Export symbol.\r
+  PUBLIC  ??EVBA\r
+  PUBLIC  _evba\r
+??EVBA:\r
+_evba:\r
+\r
+        ORG 0x000\r
+        // Unrecoverable Exception.\r
+_handle_Unrecoverable_Exception:\r
+        rjmp $\r
+\r
+        ORG 0x004\r
+        // TLB Multiple Hit.\r
+_handle_TLB_Multiple_Hit:\r
+        rjmp $\r
+\r
+        ORG 0x008\r
+        // Bus Error Data Fetch.\r
+_handle_Bus_Error_Data_Fetch:\r
+        rjmp $\r
+\r
+        ORG 0x00C\r
+         // Bus Error Instruction Fetch.\r
+_handle_Bus_Error_Instruction_Fetch:\r
+        rjmp $\r
+\r
+        ORG 0x010\r
+        // NMI.\r
+_handle_NMI:\r
+        rjmp $\r
+\r
+        ORG 0x014\r
+        // Instruction Address.\r
+_handle_Instruction_Address:\r
+        rjmp $\r
+\r
+        ORG 0x018\r
+        // ITLB Protection.\r
+_handle_ITLB_Protection:\r
+        rjmp $\r
+\r
+        ORG 0x01C\r
+        // Breakpoint.\r
+_handle_Breakpoint:\r
+        rjmp $\r
+\r
+        ORG 0x020\r
+        // Illegal Opcode.\r
+_handle_Illegal_Opcode:\r
+        rjmp $\r
+\r
+        ORG 0x024\r
+        // Unimplemented Instruction.\r
+_handle_Unimplemented_Instruction:\r
+        rjmp $\r
+\r
+        ORG 0x028\r
+        // Privilege Violation.\r
+_handle_Privilege_Violation:\r
+        rjmp $\r
+\r
+        ORG 0x02C\r
+        // Floating-Point: UNUSED IN AVR32UC and AVR32AP.\r
+_handle_Floating_Point:\r
+        rjmp $\r
+\r
+        ORG 0x030\r
+        // Coprocessor Absent: UNUSED IN AVR32UC.\r
+_handle_Coprocessor_Absent:\r
+        rjmp $\r
+\r
+        ORG 0x034\r
+        // Data Address (Read).\r
+_handle_Data_Address_Read:\r
+        rjmp $\r
+\r
+        ORG 0x038\r
+        // Data Address (Write).\r
+_handle_Data_Address_Write:\r
+        rjmp $\r
+\r
+        ORG 0x03C\r
+        // DTLB Protection (Read).\r
+_handle_DTLB_Protection_Read:\r
+        rjmp $\r
+\r
+        ORG 0x040\r
+        // DTLB Protection (Write).\r
+_handle_DTLB_Protection_Write:\r
+        rjmp $\r
+\r
+        ORG 0x044\r
+        // DTLB Modified: UNUSED IN AVR32UC.\r
+_handle_DTLB_Modified:\r
+        rjmp $\r
+\r
+        ORG 0x050\r
+        // ITLB Miss.\r
+_handle_ITLB_Miss:\r
+        rjmp $\r
+\r
+        ORG 0x060\r
+        // DTLB Miss (Read).\r
+_handle_DTLB_Miss_Read:\r
+        rjmp $\r
+\r
+        ORG 0x070\r
+        // DTLB Miss (Write).\r
+_handle_DTLB_Miss_Write:\r
+        rjmp $\r
+\r
+        ORG 0x100\r
+        // Supervisor Call.\r
+_handle_Supervisor_Call:\r
+        rjmp $\r
+\r
+\r
+// Interrupt support.\r
+// The interrupt controller must provide the offset address relative to EVBA.\r
+// Important note:\r
+//   All interrupts call a C function named _get_interrupt_handler.\r
+//   This function will read group and interrupt line number to then return in\r
+//   R12 a pointer to a user-provided interrupt handler.\r
+\r
+  ALIGN 2\r
+\r
+  REPTI   priority, 0, 1, 2, 3\r
+_int<priority>:\r
+#if __CORE__ == __AVR32A__\r
+  // R8-R12, LR, PC and SR are automatically pushed onto the system stack by the\r
+  // CPU upon interrupt entry. No other register is saved by hardware.\r
+#elif __CORE__ == __AVR32B__\r
+  // PC and SR are automatically saved in respectively RAR_INTx and RSR_INTx by\r
+  // the CPU upon interrupt entry. No other register is saved by hardware.\r
+  pushm   r8-r12, lr\r
+#endif\r
+  mov     r12, priority   // Pass the int_level parameter to the _get_interrupt_handler function.\r
+  mcall   __get_interrupt_handler\r
+  cp.w    r12, 0          // Get the pointer to the interrupt handler returned by the function.\r
+#if __CORE__ == __AVR32A__\r
+  movne   pc, r12         // If this was not a spurious interrupt (R12 != NULL), jump to the handler.\r
+#elif __CORE__ == __AVR32B__\r
+  breq    spint<priority> // If this was a spurious interrupt (R12 == NULL), branch.\r
+  st.w    --sp, r12       // Push the pointer to the interrupt handler onto the system stack since no register may be altered.\r
+  popm    r8-r12, lr, pc  // Restore registers and jump to the handler.\r
+spint<priority>:\r
+  popm    r8-r12, lr\r
+#endif\r
+  rete                    // If this was a spurious interrupt (R12 == NULL), return from event handler.\r
+  ENDR\r
+\r
+\r
+// Constant data area.\r
+\r
+  ALIGN 2\r
+\r
+  // Import symbol.\r
+  EXTERN  _get_interrupt_handler\r
+__get_interrupt_handler:\r
+  DC32  _get_interrupt_handler\r
+\r
+  // Values to store in the interrupt priority registers for the various interrupt priority levels.\r
+  // The interrupt priority registers contain the interrupt priority level and\r
+  // the EVBA-relative interrupt vector offset.\r
+  PUBLIC  ipr_val\r
+ipr_val:\r
+  DC32  (AVR32_INTC_INT0 << AVR32_INTC_IPR_INTLEVEL_OFFSET) | (_int0 - _evba),\\r
+        (AVR32_INTC_INT1 << AVR32_INTC_IPR_INTLEVEL_OFFSET) | (_int1 - _evba),\\r
+        (AVR32_INTC_INT2 << AVR32_INTC_IPR_INTLEVEL_OFFSET) | (_int2 - _evba),\\r
+        (AVR32_INTC_INT3 << AVR32_INTC_IPR_INTLEVEL_OFFSET) | (_int3 - _evba)\r
+\r
+\r
+  END\r
+\r
+\r
+//! \endverbatim\r
+//! @}\r

diff --git a/Demo/AVR32_UC3A_GCC/Atmel_SW_Framework/DRIVERS/INTC/intc.c b/Demo/AVR32_UC3A_GCC/Atmel_SW_Framework/DRIVERS/INTC/intc.c
new file mode 100644 (file)
index 0000000..03dd56b
--- /dev/null
+++ b/Demo/AVR32_UC3A_GCC/Atmel_SW_Framework/DRIVERS/INTC/intc.c
@@ -0,0 +1,214 @@
+/* This source file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */\r
+
+/*This file is prepared for Doxygen automatic documentation generation.*/\r
+/*! \file *********************************************************************\r
+ *\r
+ * \brief INTC driver for AVR32 UC3.\r
+ *\r
+ * AVR32 Interrupt Controller driver module.\r
+ *\r
+ * - Compiler:           IAR EWAVR32 and GNU GCC for AVR32\r
+ * - Supported devices:  All AVR32 devices with an INTC module can be used.\r
+ * - AppNote:\r
+ *\r
+ * \author               Atmel Corporation: http://www.atmel.com \n\r
+ *                       Support and FAQ: http://support.atmel.no/\r
+ *\r
+ ******************************************************************************/\r
+\r
+/* Copyright (c) 2009 Atmel Corporation. All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice, this\r
+ * list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an Atmel\r
+ * AVR product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\r
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\r
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\r
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE\r
+ *\r
+ */\r
+\r
+#include <avr32/io.h>\r
+#include "compiler.h"\r
+#include "preprocessor.h"\r
+#include "intc.h"\r
+\r
+// define _evba from exception.S\r
+extern void _evba;\r
+\r
+//! Values to store in the interrupt priority registers for the various interrupt priority levels.\r
+extern const unsigned int ipr_val[AVR32_INTC_NUM_INT_LEVELS];\r
+\r
+//! Creates a table of interrupt line handlers per interrupt group in order to optimize RAM space.\r
+//! Each line handler table contains a set of pointers to interrupt handlers.\r
+#if (defined __GNUC__)\r
+#define DECL_INT_LINE_HANDLER_TABLE(GRP, unused) \\r
+static volatile __int_handler _int_line_handler_table_##GRP[Max(AVR32_INTC_NUM_IRQS_PER_GRP##GRP, 1)];\r
+#elif (defined __ICCAVR32__)\r
+#define DECL_INT_LINE_HANDLER_TABLE(GRP, unused) \\r
+static volatile __no_init __int_handler _int_line_handler_table_##GRP[Max(AVR32_INTC_NUM_IRQS_PER_GRP##GRP, 1)];\r
+#endif\r
+MREPEAT(AVR32_INTC_NUM_INT_GRPS, DECL_INT_LINE_HANDLER_TABLE, ~);\r
+#undef DECL_INT_LINE_HANDLER_TABLE\r
+\r
+//! Table containing for each interrupt group the number of interrupt request\r
+//! lines and a pointer to the table of interrupt line handlers.\r
+static const struct\r
+{\r
+  unsigned int num_irqs;\r
+  volatile __int_handler *_int_line_handler_table;\r
+} _int_handler_table[AVR32_INTC_NUM_INT_GRPS] =\r
+{\r
+#define INSERT_INT_LINE_HANDLER_TABLE(GRP, unused) \\r
+  {AVR32_INTC_NUM_IRQS_PER_GRP##GRP, _int_line_handler_table_##GRP},\r
+  MREPEAT(AVR32_INTC_NUM_INT_GRPS, INSERT_INT_LINE_HANDLER_TABLE, ~)\r
+#undef INSERT_INT_LINE_HANDLER_TABLE\r
+};\r
+\r
+\r
+/*! \brief Default interrupt handler.\r
+ *\r
+ * \note Taken and adapted from Newlib.\r
+ */\r
+#if (defined __GNUC__)\r
+__attribute__((__interrupt__))\r
+#elif (defined __ICCAVR32__)\r
+__interrupt\r
+#endif\r
+static void _unhandled_interrupt(void)\r
+{\r
+  // Catch unregistered interrupts.\r
+  while (TRUE);\r
+}\r
+\r
+\r
+/*! \brief Gets the interrupt handler of the current event at the \a int_level\r
+ *         interrupt priority level (called from exception.S).\r
+ *\r
+ * \param int_level Interrupt priority level to handle.\r
+ *\r
+ * \return Interrupt handler to execute.\r
+ *\r
+ * \note Taken and adapted from Newlib.\r
+ */\r
+__int_handler _get_interrupt_handler(unsigned int int_level)\r
+{\r
+  // ICR3 is mapped first, ICR0 last.\r
+  // Code in exception.S puts int_level in R12 which is used by AVR32-GCC to\r
+  // pass a single argument to a function.\r
+  unsigned int int_grp = AVR32_INTC.icr[AVR32_INTC_INT3 - int_level];\r
+  unsigned int int_req = AVR32_INTC.irr[int_grp];\r
+\r
+  // As an interrupt may disappear while it is being fetched by the CPU\r
+  // (spurious interrupt caused by a delayed response from an MCU peripheral to\r
+  // an interrupt flag clear or interrupt disable instruction), check if there\r
+  // are remaining interrupt lines to process.\r
+  // If a spurious interrupt occurs, the status register (SR) contains an\r
+  // execution mode and interrupt level masks corresponding to a level 0\r
+  // interrupt, whatever the interrupt priority level causing the spurious\r
+  // event. This behavior has been chosen because a spurious interrupt has not\r
+  // to be a priority one and because it may not cause any trouble to other\r
+  // interrupts.\r
+  // However, these spurious interrupts place the hardware in an unstable state\r
+  // and could give problems in other/future versions of the CPU, so the\r
+  // software has to be written so that they never occur. The only safe way of\r
+  // achieving this is to always clear or disable peripheral interrupts with the\r
+  // following sequence:\r
+  // 1: Mask the interrupt in the CPU by setting GM (or IxM) in SR.\r
+  // 2: Perform the bus access to the peripheral register that clears or\r
+  //    disables the interrupt.\r
+  // 3: Wait until the interrupt has actually been cleared or disabled by the\r
+  //    peripheral. This is usually performed by reading from a register in the\r
+  //    same peripheral (it DOES NOT have to be the same register that was\r
+  //    accessed in step 2, but it MUST be in the same peripheral), what takes\r
+  //    bus system latencies into account, but peripheral internal latencies\r
+  //    (generally 0 cycle) also have to be considered.\r
+  // 4: Unmask the interrupt in the CPU by clearing GM (or IxM) in SR.\r
+  // Note that steps 1 and 4 are useless inside interrupt handlers as the\r
+  // corresponding interrupt level is automatically masked by IxM (unless IxM is\r
+  // explicitly cleared by the software).\r
+  //\r
+  // Get the right IRQ handler.\r
+  //\r
+  // If several interrupt lines are active in the group, the interrupt line with\r
+  // the highest number is selected. This is to be coherent with the\r
+  // prioritization of interrupt groups performed by the hardware interrupt\r
+  // controller.\r
+  //\r
+  // If no handler has been registered for the pending interrupt,\r
+  // _unhandled_interrupt will be selected thanks to the initialization of\r
+  // _int_line_handler_table_x by INTC_init_interrupts.\r
+  //\r
+  // exception.S will provide the interrupt handler with a clean interrupt stack\r
+  // frame, with nothing more pushed onto the stack. The interrupt handler must\r
+  // manage the `rete' instruction, what can be done thanks to pure assembly,\r
+  // inline assembly or the `__attribute__((__interrupt__))' C function\r
+  // attribute.\r
+  return (int_req) ? _int_handler_table[int_grp]._int_line_handler_table[32 - clz(int_req) - 1] : NULL;\r
+}\r
+\r
+//! Init EVBA address. This sequence might also be done in the UTILS/STARTUP/GCC/crt0.S\r
+static __inline__ void INTC_init_evba(void)\r
+{\r
+  Set_system_register(AVR32_EVBA, (int)&_evba );\r
+}\r
+\r
+void INTC_init_interrupts(void)\r
+{\r
+  unsigned int int_grp, int_req;\r
+\r
+  INTC_init_evba();\r
+\r
+  // For all interrupt groups,\r
+  for (int_grp = 0; int_grp < AVR32_INTC_NUM_INT_GRPS; int_grp++)\r
+  {\r
+    // For all interrupt request lines of each group,\r
+    for (int_req = 0; int_req < _int_handler_table[int_grp].num_irqs; int_req++)\r
+    {\r
+      // Assign _unhandled_interrupt as default interrupt handler.\r
+      _int_handler_table[int_grp]._int_line_handler_table[int_req] = &_unhandled_interrupt;\r
+    }\r
+\r
+    // Set the interrupt group priority register to its default value.\r
+    // By default, all interrupt groups are linked to the interrupt priority\r
+    // level 0 and to the interrupt vector _int0.\r
+    AVR32_INTC.ipr[int_grp] = ipr_val[AVR32_INTC_INT0];\r
+  }\r
+}\r
+\r
+\r
+void INTC_register_interrupt(__int_handler handler, unsigned int irq, unsigned int int_level)\r
+{\r
+  // Determine the group of the IRQ.\r
+  unsigned int int_grp = irq / AVR32_INTC_MAX_NUM_IRQS_PER_GRP;\r
+\r
+  // Store in _int_line_handler_table_x the pointer to the interrupt handler, so\r
+  // that _get_interrupt_handler can retrieve it when the interrupt is vectored.\r
+  _int_handler_table[int_grp]._int_line_handler_table[irq % AVR32_INTC_MAX_NUM_IRQS_PER_GRP] = handler;\r
+\r
+  // Program the corresponding IPRX register to set the interrupt priority level\r
+  // and the interrupt vector offset that will be fetched by the core interrupt\r
+  // system.\r
+  // NOTE: The _intx functions are intermediate assembly functions between the\r
+  // core interrupt system and the user interrupt handler.\r
+  AVR32_INTC.ipr[int_grp] = ipr_val[int_level & (AVR32_INTC_IPR_INTLEVEL_MASK >> AVR32_INTC_IPR_INTLEVEL_OFFSET)];\r
+}\r

diff --git a/Demo/AVR32_UC3A_GCC/Atmel_SW_Framework/DRIVERS/INTC/intc.h b/Demo/AVR32_UC3A_GCC/Atmel_SW_Framework/DRIVERS/INTC/intc.h
new file mode 100644 (file)
index 0000000..035f0a9
--- /dev/null
+++ b/Demo/AVR32_UC3A_GCC/Atmel_SW_Framework/DRIVERS/INTC/intc.h
@@ -0,0 +1,100 @@
+/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */\r
+
+/*This file is prepared for Doxygen automatic documentation generation.*/\r
+/*! \file *********************************************************************\r
+ *\r
+ * \brief INTC driver for AVR32 UC3.\r
+ *\r
+ * AVR32 Interrupt Controller driver module.\r
+ *\r
+ * - Compiler:           IAR EWAVR32 and GNU GCC for AVR32\r
+ * - Supported devices:  All AVR32 devices with an INTC module can be used.\r
+ * - AppNote:\r
+ *\r
+ * \author               Atmel Corporation: http://www.atmel.com \n\r
+ *                       Support and FAQ: http://support.atmel.no/\r
+ *\r
+ ******************************************************************************/\r
+\r
+/* Copyright (c) 2009 Atmel Corporation. All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice, this\r
+ * list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an Atmel\r
+ * AVR product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\r
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\r
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\r
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE\r
+ *\r
+ */\r
+\r
+#ifndef _INTC_H_\r
+#define _INTC_H_\r
+\r
+#include "compiler.h"\r
+\r
+\r
+//! Maximal number of interrupt request lines per group.\r
+#define AVR32_INTC_MAX_NUM_IRQS_PER_GRP             32\r
+\r
+//! Number of interrupt priority levels.\r
+#define AVR32_INTC_NUM_INT_LEVELS                   (1 << AVR32_INTC_IPR_INTLEVEL_SIZE)\r
+\r
+\r
+#ifdef __AVR32_ABI_COMPILER__ // Automatically defined when compiling for AVR32, not when assembling.\r
+\r
+//! Pointer to interrupt handler.\r
+#if (defined __GNUC__)\r
+typedef void (*__int_handler)(void);\r
+#elif (defined __ICCAVR32__)\r
+typedef void (__interrupt *__int_handler)(void);\r
+#endif\r
+\r
+\r
+/*! \brief Initializes the hardware interrupt controller driver.\r
+ *\r
+ * \note Taken and adapted from Newlib.\r
+ */\r
+extern void INTC_init_interrupts(void);\r
+\r
+/*! \brief Registers an interrupt handler.\r
+ *\r
+ * \param handler   Interrupt handler to register.\r
+ * \param irq       IRQ of the interrupt handler to register.\r
+ * \param int_level Interrupt priority level to assign to the group of this IRQ.\r
+ *\r
+ * \warning The interrupt handler must manage the `rete' instruction, what can\r
+ *          be done thanks to pure assembly, inline assembly or the\r
+ *          `__attribute__((__interrupt__))' C function attribute.\r
+ *\r
+ * \warning If several interrupt handlers of a same group are registered with\r
+ *          different priority levels, only the latest priority level set will\r
+ *          be effective.\r
+ *\r
+ * \note Taken and adapted from Newlib.\r
+ */\r
+extern void INTC_register_interrupt(__int_handler handler, unsigned int irq, unsigned int int_level);\r
+\r
+#endif  // __AVR32_ABI_COMPILER__\r
+\r
+\r
+#endif  // _INTC_H_\r

diff --git a/Demo/AVR32_UC3A_GCC/Atmel_SW_Framework/DRIVERS/PM/README.txt b/Demo/AVR32_UC3A_GCC/Atmel_SW_Framework/DRIVERS/PM/README.txt
new file mode 100644 (file)
index 0000000..d8d7320
--- /dev/null
+++ b/Demo/AVR32_UC3A_GCC/Atmel_SW_Framework/DRIVERS/PM/README.txt
@@ -0,0 +1,30 @@
+
+The PM module is very specific to the device it is integrated in. Thus instead
+of providing one low-level software driver for all PM modules which could be
+cumbersome to use and maintain, this folder contains instead several versions of
+PM software drivers, depending on the device it was intended for.
+
+Furthermore, the software drivers do not have the same API (mostly due to major
+differences between PM module versions).
+
+Note however that the power_clocks_lib.c/.h collection is destined to provide
+a high-level API abstracting the existence of modules dealing with Power
+Management and Clock configuration and System Control.
+
+Here is a brief presentation of the files present in this folder:
+- pm_at32ap7000.h, pm_at32ap7000.c: low-level software driver for a PM module
+  with version 100
+
+- pm.c, pm.h: low-level software driver for a PM module with version 2xx
+- pm_conf_clocks.c: Clocks configuration library relying on pm.c/.h for a PM
+  module with version 2xx. Its interface is available in pm.h.
+
+- pm_uc3l.h, pm_uc3l.c: low-level software driver for the UC3L devices PM module
+
+- pm_uc3c.h, pm_uc3c.c: low-level software driver for the UC3C devices PM module
+
+- power_clocks_lib.h, power_clocks_lib.c: high-level library to abstract features
+  such as oscillators/pll/dfll configuration, clock configuration, System-sensible
+  parameters configuration, buses clocks configuration, sleep mode, reset. This
+  list of features being quite broad, an implementation of this library must
+  use several modules of a device.

diff --git a/Demo/AVR32_UC3A_GCC/Atmel_SW_Framework/DRIVERS/PM/pm.c b/Demo/AVR32_UC3A_GCC/Atmel_SW_Framework/DRIVERS/PM/pm.c
new file mode 100644 (file)
index 0000000..e1a55fb
--- /dev/null
+++ b/Demo/AVR32_UC3A_GCC/Atmel_SW_Framework/DRIVERS/PM/pm.c
@@ -0,0 +1,546 @@
+/* This source file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */\r
+
+/*This file has been prepared for Doxygen automatic documentation generation.*/\r
+/*! \file *********************************************************************\r
+ *\r
+ * \brief Power Manager driver.\r
+ *\r
+ *\r
+ * - Compiler:           IAR EWAVR32 and GNU GCC for AVR32\r
+ * - Supported devices:  All AVR32 devices.\r
+ * - AppNote:\r
+ *\r
+ * \author               Atmel Corporation: http://www.atmel.com \n\r
+ *                       Support and FAQ: http://support.atmel.no/\r
+ *\r
+ *****************************************************************************/\r
+\r
+/* Copyright (c) 2009 Atmel Corporation. All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice, this\r
+ * list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an Atmel\r
+ * AVR product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\r
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\r
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\r
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE\r
+ *\r
+ */\r
+\r
+#include "compiler.h"\r
+#include "pm.h"\r
+\r
+\r
+/*! \name PM Writable Bit-Field Registers\r
+ */\r
+//! @{\r
+\r
+typedef union\r
+{\r
+  unsigned long                 mcctrl;\r
+  avr32_pm_mcctrl_t             MCCTRL;\r
+} u_avr32_pm_mcctrl_t;\r
+\r
+typedef union\r
+{\r
+  unsigned long                 cksel;\r
+  avr32_pm_cksel_t              CKSEL;\r
+} u_avr32_pm_cksel_t;\r
+\r
+typedef union\r
+{\r
+  unsigned long                 pll;\r
+  avr32_pm_pll_t                PLL;\r
+} u_avr32_pm_pll_t;\r
+\r
+typedef union\r
+{\r
+  unsigned long                 oscctrl0;\r
+  avr32_pm_oscctrl0_t           OSCCTRL0;\r
+} u_avr32_pm_oscctrl0_t;\r
+\r
+typedef union\r
+{\r
+  unsigned long                 oscctrl1;\r
+  avr32_pm_oscctrl1_t           OSCCTRL1;\r
+} u_avr32_pm_oscctrl1_t;\r
+\r
+typedef union\r
+{\r
+  unsigned long                 oscctrl32;\r
+  avr32_pm_oscctrl32_t          OSCCTRL32;\r
+} u_avr32_pm_oscctrl32_t;\r
+\r
+typedef union\r
+{\r
+  unsigned long                 ier;\r
+  avr32_pm_ier_t                IER;\r
+} u_avr32_pm_ier_t;\r
+\r
+typedef union\r
+{\r
+  unsigned long                 idr;\r
+  avr32_pm_idr_t                IDR;\r
+} u_avr32_pm_idr_t;\r
+\r
+typedef union\r
+{\r
+  unsigned long                 icr;\r
+  avr32_pm_icr_t                ICR;\r
+} u_avr32_pm_icr_t;\r
+\r
+typedef union\r
+{\r
+  unsigned long                 gcctrl;\r
+  avr32_pm_gcctrl_t             GCCTRL;\r
+} u_avr32_pm_gcctrl_t;\r
+\r
+typedef union\r
+{\r
+  unsigned long                 rccr;\r
+  avr32_pm_rccr_t               RCCR;\r
+} u_avr32_pm_rccr_t;\r
+\r
+typedef union\r
+{\r
+  unsigned long                 bgcr;\r
+  avr32_pm_bgcr_t               BGCR;\r
+} u_avr32_pm_bgcr_t;\r
+\r
+typedef union\r
+{\r
+  unsigned long                 vregcr;\r
+  avr32_pm_vregcr_t             VREGCR;\r
+} u_avr32_pm_vregcr_t;\r
+\r
+typedef union\r
+{\r
+  unsigned long                 bod;\r
+  avr32_pm_bod_t                BOD;\r
+} u_avr32_pm_bod_t;\r
+\r
+//! @}\r
+\r
+\r
+/*! \brief Sets the mode of the oscillator 0.\r
+ *\r
+ * \param pm Base address of the Power Manager (i.e. &AVR32_PM).\r
+ * \param mode Oscillator 0 mode (i.e. AVR32_PM_OSCCTRL0_MODE_x).\r
+ */\r
+static void pm_set_osc0_mode(volatile avr32_pm_t *pm, unsigned int mode)\r
+{\r
+  // Read\r
+  u_avr32_pm_oscctrl0_t u_avr32_pm_oscctrl0 = {pm->oscctrl0};\r
+  // Modify\r
+  u_avr32_pm_oscctrl0.OSCCTRL0.mode = mode;\r
+  // Write\r
+  pm->oscctrl0 = u_avr32_pm_oscctrl0.oscctrl0;\r
+}\r
+\r
+\r
+void pm_enable_osc0_ext_clock(volatile avr32_pm_t *pm)\r
+{\r
+  pm_set_osc0_mode(pm, AVR32_PM_OSCCTRL0_MODE_EXT_CLOCK);\r
+}\r
+\r
+\r
+void pm_enable_osc0_crystal(volatile avr32_pm_t *pm, unsigned int fosc0)\r
+{\r
+  pm_set_osc0_mode(pm, (fosc0 <  900000) ? AVR32_PM_OSCCTRL0_MODE_CRYSTAL_G0 :\r
+                       (fosc0 < 3000000) ? AVR32_PM_OSCCTRL0_MODE_CRYSTAL_G1 :\r
+                       (fosc0 < 8000000) ? AVR32_PM_OSCCTRL0_MODE_CRYSTAL_G2 :\r
+                                           AVR32_PM_OSCCTRL0_MODE_CRYSTAL_G3);\r
+}\r
+\r
+\r
+void pm_enable_clk0(volatile avr32_pm_t *pm, unsigned int startup)\r
+{\r
+  pm_enable_clk0_no_wait(pm, startup);\r
+  pm_wait_for_clk0_ready(pm);\r
+}\r
+\r
+\r
+void pm_disable_clk0(volatile avr32_pm_t *pm)\r
+{\r
+  pm->mcctrl &= ~AVR32_PM_MCCTRL_OSC0EN_MASK;\r
+}\r
+\r
+\r
+void pm_enable_clk0_no_wait(volatile avr32_pm_t *pm, unsigned int startup)\r
+{\r
+  // Read register\r
+  u_avr32_pm_oscctrl0_t u_avr32_pm_oscctrl0 = {pm->oscctrl0};\r
+  // Modify\r
+  u_avr32_pm_oscctrl0.OSCCTRL0.startup = startup;\r
+  // Write back\r
+  pm->oscctrl0 = u_avr32_pm_oscctrl0.oscctrl0;\r
+\r
+  pm->mcctrl |= AVR32_PM_MCCTRL_OSC0EN_MASK;\r
+}\r
+\r
+\r
+void pm_wait_for_clk0_ready(volatile avr32_pm_t *pm)\r
+{\r
+  while (!(pm->poscsr & AVR32_PM_POSCSR_OSC0RDY_MASK));\r
+}\r
+\r
+\r
+/*! \brief Sets the mode of the oscillator 1.\r
+ *\r
+ * \param pm Base address of the Power Manager (i.e. &AVR32_PM).\r
+ * \param mode Oscillator 1 mode (i.e. AVR32_PM_OSCCTRL1_MODE_x).\r
+ */\r
+static void pm_set_osc1_mode(volatile avr32_pm_t *pm, unsigned int mode)\r
+{\r
+  // Read\r
+  u_avr32_pm_oscctrl1_t u_avr32_pm_oscctrl1 = {pm->oscctrl1};\r
+  // Modify\r
+  u_avr32_pm_oscctrl1.OSCCTRL1.mode = mode;\r
+  // Write\r
+  pm->oscctrl1 = u_avr32_pm_oscctrl1.oscctrl1;\r
+}\r
+\r
+\r
+void pm_enable_osc1_ext_clock(volatile avr32_pm_t *pm)\r
+{\r
+  pm_set_osc1_mode(pm, AVR32_PM_OSCCTRL1_MODE_EXT_CLOCK);\r
+}\r
+\r
+\r
+void pm_enable_osc1_crystal(volatile avr32_pm_t *pm, unsigned int fosc1)\r
+{\r
+  pm_set_osc1_mode(pm, (fosc1 <  900000) ? AVR32_PM_OSCCTRL1_MODE_CRYSTAL_G0 :\r
+                       (fosc1 < 3000000) ? AVR32_PM_OSCCTRL1_MODE_CRYSTAL_G1 :\r
+                       (fosc1 < 8000000) ? AVR32_PM_OSCCTRL1_MODE_CRYSTAL_G2 :\r
+                                           AVR32_PM_OSCCTRL1_MODE_CRYSTAL_G3);\r
+}\r
+\r
+\r
+void pm_enable_clk1(volatile avr32_pm_t *pm, unsigned int startup)\r
+{\r
+  pm_enable_clk1_no_wait(pm, startup);\r
+  pm_wait_for_clk1_ready(pm);\r
+}\r
+\r
+\r
+void pm_disable_clk1(volatile avr32_pm_t *pm)\r
+{\r
+  pm->mcctrl &= ~AVR32_PM_MCCTRL_OSC1EN_MASK;\r
+}\r
+\r
+\r
+void pm_enable_clk1_no_wait(volatile avr32_pm_t *pm, unsigned int startup)\r
+{\r
+  // Read register\r
+  u_avr32_pm_oscctrl1_t u_avr32_pm_oscctrl1 = {pm->oscctrl1};\r
+  // Modify\r
+  u_avr32_pm_oscctrl1.OSCCTRL1.startup = startup;\r
+  // Write back\r
+  pm->oscctrl1 = u_avr32_pm_oscctrl1.oscctrl1;\r
+\r
+  pm->mcctrl |= AVR32_PM_MCCTRL_OSC1EN_MASK;\r
+}\r
+\r
+\r
+void pm_wait_for_clk1_ready(volatile avr32_pm_t *pm)\r
+{\r
+  while (!(pm->poscsr & AVR32_PM_POSCSR_OSC1RDY_MASK));\r
+}\r
+\r
+\r
+/*! \brief Sets the mode of the 32-kHz oscillator.\r
+ *\r
+ * \param pm Base address of the Power Manager (i.e. &AVR32_PM).\r
+ * \param mode 32-kHz oscillator mode (i.e. AVR32_PM_OSCCTRL32_MODE_x).\r
+ */\r
+static void pm_set_osc32_mode(volatile avr32_pm_t *pm, unsigned int mode)\r
+{\r
+  // Read\r
+  u_avr32_pm_oscctrl32_t u_avr32_pm_oscctrl32 = {pm->oscctrl32};\r
+  // Modify\r
+  u_avr32_pm_oscctrl32.OSCCTRL32.mode = mode;\r
+  // Write\r
+  pm->oscctrl32 = u_avr32_pm_oscctrl32.oscctrl32;\r
+}\r
+\r
+\r
+void pm_enable_osc32_ext_clock(volatile avr32_pm_t *pm)\r
+{\r
+  pm_set_osc32_mode(pm, AVR32_PM_OSCCTRL32_MODE_EXT_CLOCK);\r
+}\r
+\r
+\r
+void pm_enable_osc32_crystal(volatile avr32_pm_t *pm)\r
+{\r
+  pm_set_osc32_mode(pm, AVR32_PM_OSCCTRL32_MODE_CRYSTAL);\r
+}\r
+\r
+\r
+void pm_enable_clk32(volatile avr32_pm_t *pm, unsigned int startup)\r
+{\r
+  pm_enable_clk32_no_wait(pm, startup);\r
+  pm_wait_for_clk32_ready(pm);\r
+}\r
+\r
+\r
+void pm_disable_clk32(volatile avr32_pm_t *pm)\r
+{\r
+  pm->oscctrl32 &= ~AVR32_PM_OSCCTRL32_OSC32EN_MASK;\r
+}\r
+\r
+\r
+void pm_enable_clk32_no_wait(volatile avr32_pm_t *pm, unsigned int startup)\r
+{\r
+  // Read register\r
+  u_avr32_pm_oscctrl32_t u_avr32_pm_oscctrl32 = {pm->oscctrl32};\r
+  // Modify\r
+  u_avr32_pm_oscctrl32.OSCCTRL32.osc32en = 1;\r
+  u_avr32_pm_oscctrl32.OSCCTRL32.startup = startup;\r
+  // Write back\r
+  pm->oscctrl32 = u_avr32_pm_oscctrl32.oscctrl32;\r
+}\r
+\r
+\r
+void pm_wait_for_clk32_ready(volatile avr32_pm_t *pm)\r
+{\r
+  while (!(pm->poscsr & AVR32_PM_POSCSR_OSC32RDY_MASK));\r
+}\r
+\r
+\r
+void pm_cksel(volatile avr32_pm_t *pm,\r
+              unsigned int pbadiv,\r
+              unsigned int pbasel,\r
+              unsigned int pbbdiv,\r
+              unsigned int pbbsel,\r
+              unsigned int hsbdiv,\r
+              unsigned int hsbsel)\r
+{\r
+  u_avr32_pm_cksel_t u_avr32_pm_cksel = {0};\r
+\r
+  u_avr32_pm_cksel.CKSEL.cpusel = hsbsel;\r
+  u_avr32_pm_cksel.CKSEL.cpudiv = hsbdiv;\r
+  u_avr32_pm_cksel.CKSEL.hsbsel = hsbsel;\r
+  u_avr32_pm_cksel.CKSEL.hsbdiv = hsbdiv;\r
+  u_avr32_pm_cksel.CKSEL.pbasel = pbasel;\r
+  u_avr32_pm_cksel.CKSEL.pbadiv = pbadiv;\r
+  u_avr32_pm_cksel.CKSEL.pbbsel = pbbsel;\r
+  u_avr32_pm_cksel.CKSEL.pbbdiv = pbbdiv;\r
+\r
+  pm->cksel = u_avr32_pm_cksel.cksel;\r
+\r
+  // Wait for ckrdy bit and then clear it\r
+  while (!(pm->poscsr & AVR32_PM_POSCSR_CKRDY_MASK));\r
+}\r
+\r
+\r
+void pm_gc_setup(volatile avr32_pm_t *pm,\r
+                  unsigned int gc,\r
+                  unsigned int osc_or_pll, // Use Osc (=0) or PLL (=1)\r
+                  unsigned int pll_osc, // Sel Osc0/PLL0 or Osc1/PLL1\r
+                  unsigned int diven,\r
+                  unsigned int div)\r
+{\r
+  u_avr32_pm_gcctrl_t u_avr32_pm_gcctrl = {0};\r
+\r
+  u_avr32_pm_gcctrl.GCCTRL.oscsel = pll_osc;\r
+  u_avr32_pm_gcctrl.GCCTRL.pllsel = osc_or_pll;\r
+  u_avr32_pm_gcctrl.GCCTRL.diven  = diven;\r
+  u_avr32_pm_gcctrl.GCCTRL.div    = div;\r
+\r
+  pm->gcctrl[gc] = u_avr32_pm_gcctrl.gcctrl;\r
+}\r
+\r
+\r
+void pm_gc_enable(volatile avr32_pm_t *pm,\r
+                  unsigned int gc)\r
+{\r
+  pm->gcctrl[gc] |= AVR32_PM_GCCTRL_CEN_MASK;\r
+}\r
+\r
+\r
+void pm_gc_disable(volatile avr32_pm_t *pm,\r
+                   unsigned int gc)\r
+{\r
+  pm->gcctrl[gc] &= ~AVR32_PM_GCCTRL_CEN_MASK;\r
+}\r
+\r
+\r
+void pm_pll_setup(volatile avr32_pm_t *pm,\r
+                  unsigned int pll,\r
+                  unsigned int mul,\r
+                  unsigned int div,\r
+                  unsigned int osc,\r
+                  unsigned int lockcount)\r
+{\r
+  u_avr32_pm_pll_t u_avr32_pm_pll = {0};\r
+\r
+  u_avr32_pm_pll.PLL.pllosc   = osc;\r
+  u_avr32_pm_pll.PLL.plldiv   = div;\r
+  u_avr32_pm_pll.PLL.pllmul   = mul;\r
+  u_avr32_pm_pll.PLL.pllcount = lockcount;\r
+\r
+  pm->pll[pll] = u_avr32_pm_pll.pll;\r
+}\r
+\r
+\r
+void pm_pll_set_option(volatile avr32_pm_t *pm,\r
+                       unsigned int pll,\r
+                       unsigned int pll_freq,\r
+                       unsigned int pll_div2,\r
+                       unsigned int pll_wbwdisable)\r
+{\r
+  u_avr32_pm_pll_t u_avr32_pm_pll = {pm->pll[pll]};\r
+  u_avr32_pm_pll.PLL.pllopt = pll_freq | (pll_div2 << 1) | (pll_wbwdisable << 2);\r
+  pm->pll[pll] = u_avr32_pm_pll.pll;\r
+}\r
+\r
+\r
+unsigned int pm_pll_get_option(volatile avr32_pm_t *pm,\r
+                               unsigned int pll)\r
+{\r
+  return (pm->pll[pll] & AVR32_PM_PLLOPT_MASK) >> AVR32_PM_PLLOPT_OFFSET;\r
+}\r
+\r
+\r
+void pm_pll_enable(volatile avr32_pm_t *pm,\r
+                  unsigned int pll)\r
+{\r
+  pm->pll[pll] |= AVR32_PM_PLLEN_MASK;\r
+}\r
+\r
+\r
+void pm_pll_disable(volatile avr32_pm_t *pm,\r
+                  unsigned int pll)\r
+{\r
+  pm->pll[pll] &= ~AVR32_PM_PLLEN_MASK;\r
+}\r
+\r
+\r
+void pm_wait_for_pll0_locked(volatile avr32_pm_t *pm)\r
+{\r
+  while (!(pm->poscsr & AVR32_PM_POSCSR_LOCK0_MASK));\r
+}\r
+\r
+\r
+void pm_wait_for_pll1_locked(volatile avr32_pm_t *pm)\r
+{\r
+  while (!(pm->poscsr & AVR32_PM_POSCSR_LOCK1_MASK));\r
+}\r
+\r
+\r
+void pm_switch_to_clock(volatile avr32_pm_t *pm, unsigned long clock)\r
+{\r
+  // Read\r
+  u_avr32_pm_mcctrl_t u_avr32_pm_mcctrl = {pm->mcctrl};\r
+  // Modify\r
+  u_avr32_pm_mcctrl.MCCTRL.mcsel = clock;\r
+  // Write back\r
+  pm->mcctrl = u_avr32_pm_mcctrl.mcctrl;\r
+}\r
+\r
+\r
+void pm_switch_to_osc0(volatile avr32_pm_t *pm, unsigned int fosc0, unsigned int startup)\r
+{\r
+  pm_enable_osc0_crystal(pm, fosc0);            // Enable the Osc0 in crystal mode\r
+  pm_enable_clk0(pm, startup);                  // Crystal startup time - This parameter is critical and depends on the characteristics of the crystal\r
+  pm_switch_to_clock(pm, AVR32_PM_MCSEL_OSC0);  // Then switch main clock to Osc0\r
+}\r
+\r
+\r
+void pm_bod_enable_irq(volatile avr32_pm_t *pm)\r
+{\r
+  pm->ier = AVR32_PM_IER_BODDET_MASK;\r
+}\r
+\r
+\r
+void pm_bod_disable_irq(volatile avr32_pm_t *pm)\r
+{\r
+  Bool global_interrupt_enabled = Is_global_interrupt_enabled();\r
+\r
+  if (global_interrupt_enabled) Disable_global_interrupt();\r
+  pm->idr = AVR32_PM_IDR_BODDET_MASK;\r
+  pm->isr;\r
+  if (global_interrupt_enabled) Enable_global_interrupt();\r
+}\r
+\r
+\r
+void pm_bod_clear_irq(volatile avr32_pm_t *pm)\r
+{\r
+  pm->icr = AVR32_PM_ICR_BODDET_MASK;\r
+}\r
+\r
+\r
+unsigned long pm_bod_get_irq_status(volatile avr32_pm_t *pm)\r
+{\r
+  return ((pm->isr & AVR32_PM_ISR_BODDET_MASK) != 0);\r
+}\r
+\r
+\r
+unsigned long pm_bod_get_irq_enable_bit(volatile avr32_pm_t *pm)\r
+{\r
+  return ((pm->imr & AVR32_PM_IMR_BODDET_MASK) != 0);\r
+}\r
+\r
+\r
+unsigned long pm_bod_get_level(volatile avr32_pm_t *pm)\r
+{\r
+  return (pm->bod & AVR32_PM_BOD_LEVEL_MASK) >> AVR32_PM_BOD_LEVEL_OFFSET;\r
+}\r
+\r
+\r
+unsigned long pm_read_gplp(volatile avr32_pm_t *pm, unsigned long gplp)\r
+{\r
+  return pm->gplp[gplp];\r
+}\r
+\r
+\r
+void pm_write_gplp(volatile avr32_pm_t *pm, unsigned long gplp, unsigned long value)\r
+{\r
+  pm->gplp[gplp] = value;\r
+}\r
+\r
+\r
+long pm_enable_module(volatile avr32_pm_t *pm, unsigned long module)\r
+{\r
+  unsigned long domain = module>>5;\r
+  unsigned long *regptr = (unsigned long*)(&(pm->cpumask) + domain);\r
+\r
+  // Implementation-specific shortcut: the ckMASK registers are contiguous and\r
+  // memory-mapped in that order: CPUMASK, HSBMASK, PBAMASK, PBBMASK.\r
+\r
+  *regptr |= (1<<(module%32));\r
+\r
+  return PASS;\r
+}\r
+\r
+long pm_disable_module(volatile avr32_pm_t *pm, unsigned long module)\r
+{\r
+  unsigned long domain = module>>5;\r
+  unsigned long *regptr = (unsigned long*)(&(pm->cpumask) + domain);\r
+\r
+  // Implementation-specific shortcut: the ckMASK registers are contiguous and\r
+  // memory-mapped in that order: CPUMASK, HSBMASK, PBAMASK, PBBMASK.\r
+\r
+  *regptr &= ~(1<<(module%32));\r
+\r
+  return PASS;\r
+}\r

diff --git a/Demo/AVR32_UC3A_GCC/Atmel_SW_Framework/DRIVERS/PM/pm.h b/Demo/AVR32_UC3A_GCC/Atmel_SW_Framework/DRIVERS/PM/pm.h
new file mode 100644 (file)
index 0000000..b244332
--- /dev/null
+++ b/Demo/AVR32_UC3A_GCC/Atmel_SW_Framework/DRIVERS/PM/pm.h
@@ -0,0 +1,493 @@
+/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */\r
+
+/*This file has been prepared for Doxygen automatic documentation generation.*/\r
+/*! \file *********************************************************************\r
+ *\r
+ * \brief Power Manager driver.\r
+ *\r
+ *\r
+ * - Compiler:           IAR EWAVR32 and GNU GCC for AVR32\r
+ * - Supported devices:  All AVR32 devices.\r
+ * - AppNote:\r
+ *\r
+ * \author               Atmel Corporation: http://www.atmel.com \n\r
+ *                       Support and FAQ: http://support.atmel.no/\r
+ *\r
+ *****************************************************************************/\r
+\r
+/* Copyright (c) 2009 Atmel Corporation. All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice, this\r
+ * list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an Atmel\r
+ * AVR product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\r
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\r
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\r
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE\r
+ *\r
+ */\r
+\r
+#ifndef _PM_H_\r
+#define _PM_H_\r
+\r
+#include <avr32/io.h>\r
+#include "compiler.h"\r
+#include "preprocessor.h"\r
+\r
+\r
+/*! \brief Sets the MCU in the specified sleep mode.\r
+ *\r
+ * \param mode Sleep mode:\r
+ *   \arg \c AVR32_PM_SMODE_IDLE: Idle;\r
+ *   \arg \c AVR32_PM_SMODE_FROZEN: Frozen;\r
+ *   \arg \c AVR32_PM_SMODE_STANDBY: Standby;\r
+ *   \arg \c AVR32_PM_SMODE_STOP: Stop;\r
+ *   \arg \c AVR32_PM_SMODE_DEEP_STOP: DeepStop;\r
+ *   \arg \c AVR32_PM_SMODE_STATIC: Static.\r
+ */\r
+#define SLEEP(mode)   {__asm__ __volatile__ ("sleep "STRINGZ(mode));}\r
+\r
+\r
+//! Input and output parameters when initializing PM clocks using pm_configure_clocks().\r
+typedef struct\r
+{\r
+  //! CPU frequency (input/output argument).\r
+  unsigned long cpu_f;\r
+\r
+  //! PBA frequency (input/output argument).\r
+  unsigned long pba_f;\r
+\r
+  //! Oscillator 0's external crystal(or external clock) frequency (board dependant) (input argument).\r
+  unsigned long osc0_f;\r
+\r
+  //! Oscillator 0's external crystal(or external clock) startup time: AVR32_PM_OSCCTRL0_STARTUP_x_RCOSC (input argument).\r
+  unsigned long osc0_startup;\r
+} pm_freq_param_t;\r
+\r
+#define PM_FREQ_STATUS_FAIL   (-1)\r
+#define PM_FREQ_STATUS_OK     (0)\r
+\r
+\r
+/*! \brief Gets the MCU reset cause.\r
+ *\r
+ * \param pm Base address of the Power Manager instance (i.e. &AVR32_PM).\r
+ *\r
+ * \return The MCU reset cause which can be masked with the\r
+ *         \c AVR32_PM_RCAUSE_x_MASK bit-masks to isolate specific causes.\r
+ */\r
+#if (defined __GNUC__)\r
+__attribute__((__always_inline__))\r
+#endif\r
+extern __inline__ unsigned int pm_get_reset_cause(volatile avr32_pm_t *pm)\r
+{\r
+  return pm->rcause;\r
+}\r
+\r
+\r
+/*!\r
+ * \brief This function will enable the external clock mode of the oscillator 0.\r
+ * \param pm Base address of the Power Manager (i.e. &AVR32_PM)\r
+ */\r
+extern void pm_enable_osc0_ext_clock(volatile avr32_pm_t *pm);\r
+\r
+\r
+/*!\r
+ * \brief This function will enable the crystal mode of the oscillator 0.\r
+ * \param pm Base address of the Power Manager (i.e. &AVR32_PM)\r
+ * \param fosc0 Oscillator 0 crystal frequency (Hz)\r
+ */\r
+extern void pm_enable_osc0_crystal(volatile avr32_pm_t *pm, unsigned int fosc0);\r
+\r
+\r
+/*!\r
+ * \brief This function will enable the oscillator 0 to be used with a startup time.\r
+ * \param pm Base address of the Power Manager (i.e. &AVR32_PM)\r
+ * \param startup Clock 0 startup time. AVR32_PM_OSCCTRL0_STARTUP_x_RCOSC.\r
+ */\r
+extern void pm_enable_clk0(volatile avr32_pm_t *pm, unsigned int startup);\r
+\r
+\r
+/*!\r
+ * \brief This function will disable the oscillator 0.\r
+ * \param pm Base address of the Power Manager (i.e. &AVR32_PM)\r
+ */\r
+extern void pm_disable_clk0(volatile avr32_pm_t *pm);\r
+\r
+\r
+/*!\r
+ * \brief This function will enable the oscillator 0 to be used with no startup time.\r
+ * \param pm Base address of the Power Manager (i.e. &AVR32_PM)\r
+ * \param startup Clock 0 startup time, for which the function does not wait. AVR32_PM_OSCCTRL0_STARTUP_x_RCOSC.\r
+ */\r
+extern void pm_enable_clk0_no_wait(volatile avr32_pm_t *pm, unsigned int startup);\r
+\r
+\r
+/*!\r
+ * \brief This function will wait until the Osc0 clock is ready.\r
+ * \param pm Base address of the Power Manager (i.e. &AVR32_PM)\r
+ */\r
+extern void pm_wait_for_clk0_ready(volatile avr32_pm_t *pm);\r
+\r
+\r
+/*!\r
+ * \brief This function will enable the external clock mode of the oscillator 1.\r
+ * \param pm Base address of the Power Manager (i.e. &AVR32_PM)\r
+ */\r
+extern void pm_enable_osc1_ext_clock(volatile avr32_pm_t *pm);\r
+\r
+\r
+/*!\r
+ * \brief This function will enable the crystal mode of the oscillator 1.\r
+ * \param pm Base address of the Power Manager (i.e. &AVR32_PM)\r
+ * \param fosc1 Oscillator 1 crystal frequency (Hz)\r
+ */\r
+extern void pm_enable_osc1_crystal(volatile avr32_pm_t *pm, unsigned int fosc1);\r
+\r
+\r
+/*!\r
+ * \brief This function will enable the oscillator 1 to be used with a startup time.\r
+ * \param pm Base address of the Power Manager (i.e. &AVR32_PM)\r
+ * \param startup Clock 1 startup time. AVR32_PM_OSCCTRL1_STARTUP_x_RCOSC.\r
+ */\r
+extern void pm_enable_clk1(volatile avr32_pm_t *pm, unsigned int startup);\r
+\r
+\r
+/*!\r
+ * \brief This function will disable the oscillator 1.\r
+ * \param pm Base address of the Power Manager (i.e. &AVR32_PM)\r
+ */\r
+extern void pm_disable_clk1(volatile avr32_pm_t *pm);\r
+\r
+\r
+/*!\r
+ * \brief This function will enable the oscillator 1 to be used with no startup time.\r
+ * \param pm Base address of the Power Manager (i.e. &AVR32_PM)\r
+ * \param startup Clock 1 startup time, for which the function does not wait. AVR32_PM_OSCCTRL1_STARTUP_x_RCOSC.\r
+ */\r
+extern void pm_enable_clk1_no_wait(volatile avr32_pm_t *pm, unsigned int startup);\r
+\r
+\r
+/*!\r
+ * \brief This function will wait until the Osc1 clock is ready.\r
+ * \param pm Base address of the Power Manager (i.e. &AVR32_PM)\r
+ */\r
+extern void pm_wait_for_clk1_ready(volatile avr32_pm_t *pm);\r
+\r
+\r
+/*!\r
+ * \brief This function will enable the external clock mode of the 32-kHz oscillator.\r
+ * \param pm Base address of the Power Manager (i.e. &AVR32_PM)\r
+ */\r
+extern void pm_enable_osc32_ext_clock(volatile avr32_pm_t *pm);\r
+\r
+\r
+/*!\r
+ * \brief This function will enable the crystal mode of the 32-kHz oscillator.\r
+ * \param pm Base address of the Power Manager (i.e. &AVR32_PM)\r
+ */\r
+extern void pm_enable_osc32_crystal(volatile avr32_pm_t *pm);\r
+\r
+\r
+/*!\r
+ * \brief This function will enable the oscillator 32 to be used with a startup time.\r
+ * \param pm Base address of the Power Manager (i.e. &AVR32_PM)\r
+ * \param startup Clock 32 kHz startup time. AVR32_PM_OSCCTRL32_STARTUP_x_RCOSC.\r
+ */\r
+extern void pm_enable_clk32(volatile avr32_pm_t *pm, unsigned int startup);\r
+\r
+\r
+/*!\r
+ * \brief This function will disable the oscillator 32.\r
+ * \param pm Base address of the Power Manager (i.e. &AVR32_PM)\r
+ */\r
+extern void pm_disable_clk32(volatile avr32_pm_t *pm);\r
+\r
+\r
+/*!\r
+ * \brief This function will enable the oscillator 32 to be used with no startup time.\r
+ * \param pm Base address of the Power Manager (i.e. &AVR32_PM)\r
+ * \param startup Clock 32 kHz startup time, for which the function does not wait. AVR32_PM_OSCCTRL32_STARTUP_x_RCOSC.\r
+ */\r
+extern void pm_enable_clk32_no_wait(volatile avr32_pm_t *pm, unsigned int startup);\r
+\r
+\r
+/*!\r
+ * \brief This function will wait until the osc32 clock is ready.\r
+ * \param pm Base address of the Power Manager (i.e. &AVR32_PM)\r
+ */\r
+extern void pm_wait_for_clk32_ready(volatile avr32_pm_t *pm);\r
+\r
+\r
+/*!\r
+ * \brief This function will select all the power manager clocks.\r
+ * \param pm Base address of the Power Manager (i.e. &AVR32_PM)\r
+ * \param pbadiv Peripheral Bus A clock divisor enable\r
+ * \param pbasel Peripheral Bus A select\r
+ * \param pbbdiv Peripheral Bus B clock divisor enable\r
+ * \param pbbsel Peripheral Bus B select\r
+ * \param hsbdiv High Speed Bus clock divisor enable (CPU clock = HSB clock)\r
+ * \param hsbsel High Speed Bus select (CPU clock = HSB clock )\r
+ */\r
+extern void pm_cksel(volatile avr32_pm_t *pm, unsigned int pbadiv, unsigned int pbasel, unsigned int pbbdiv, unsigned int pbbsel, unsigned int hsbdiv, unsigned int hsbsel);\r
+\r
+\r
+/*!\r
+ * \brief This function will setup a generic clock.\r
+ * \param pm Base address of the Power Manager (i.e. &AVR32_PM)\r
+ * \param gc generic clock number (0 for gc0...)\r
+ * \param osc_or_pll Use OSC (=0) or PLL (=1)\r
+ * \param pll_osc Select Osc0/PLL0 or Osc1/PLL1\r
+ * \param diven Generic clock divisor enable\r
+ * \param div Generic clock divisor\r
+ */\r
+extern void pm_gc_setup(volatile avr32_pm_t *pm, unsigned int gc, unsigned int osc_or_pll, unsigned int pll_osc, unsigned int diven, unsigned int div);\r
+\r
+\r
+/*!\r
+ * \brief This function will enable a generic clock.\r
+ * \param pm Base address of the Power Manager (i.e. &AVR32_PM)\r
+ * \param gc generic clock number (0 for gc0...)\r
+ */\r
+extern void pm_gc_enable(volatile avr32_pm_t *pm, unsigned int gc);\r
+\r
+\r
+/*!\r
+ * \brief This function will disable a generic clock.\r
+ * \param pm Base address of the Power Manager (i.e. &AVR32_PM)\r
+ * \param gc generic clock number (0 for gc0...)\r
+ */\r
+extern void pm_gc_disable(volatile avr32_pm_t *pm, unsigned int gc);\r
+\r
+\r
+/*!\r
+ * \brief This function will setup a PLL.\r
+ * \param pm Base address of the Power Manager (i.e. &AVR32_PM)\r
+ * \param pll PLL number(0 for PLL0, 1 for PLL1)\r
+ * \param mul PLL MUL in the PLL formula\r
+ * \param div PLL DIV in the PLL formula\r
+ * \param osc OSC number (0 for osc0, 1 for osc1)\r
+ * \param lockcount PLL lockount\r
+ */\r
+extern void pm_pll_setup(volatile avr32_pm_t *pm, unsigned int pll, unsigned int mul, unsigned int div, unsigned int osc, unsigned int lockcount);\r
+\r
+\r
+/*!\r
+ * \brief This function will set a PLL option.\r
+ * \param pm Base address of the Power Manager (i.e. &AVR32_PM)\r
+ * \param pll PLL number(0 for PLL0, 1 for PLL1)\r
+ * \param pll_freq Set to 1 for VCO frequency range 80-180MHz, set to 0 for VCO frequency range 160-240Mhz.\r
+ * \param pll_div2 Divide the PLL output frequency by 2 (this settings does not change the FVCO value)\r
+ * \param pll_wbwdisable 1 Disable the Wide-Bandith Mode (Wide-Bandwith mode allow a faster startup time and out-of-lock time). 0 to enable the Wide-Bandith Mode.\r
+ */\r
+extern void pm_pll_set_option(volatile avr32_pm_t *pm, unsigned int pll, unsigned int  pll_freq, unsigned int  pll_div2, unsigned int  pll_wbwdisable);\r
+\r
+\r
+/*!\r
+ * \brief This function will get a PLL option.\r
+ * \param pm Base address of the Power Manager (i.e. &AVR32_PM)\r
+ * \param pll PLL number(0 for PLL0, 1 for PLL1)\r
+ * \return       Option\r
+ */\r
+extern unsigned int pm_pll_get_option(volatile avr32_pm_t *pm, unsigned int pll);\r
+\r
+\r
+/*!\r
+ * \brief This function will enable a PLL.\r
+ * \param pm Base address of the Power Manager (i.e. &AVR32_PM)\r
+ * \param pll PLL number(0 for PLL0, 1 for PLL1)\r
+ */\r
+extern void pm_pll_enable(volatile avr32_pm_t *pm, unsigned int pll);\r
+\r
+\r
+/*!\r
+ * \brief This function will disable a PLL.\r
+ * \param pm Base address of the Power Manager (i.e. &AVR32_PM)\r
+ * \param pll PLL number(0 for PLL0, 1 for PLL1)\r
+ */\r
+extern void pm_pll_disable(volatile avr32_pm_t *pm, unsigned int pll);\r
+\r
+\r
+/*!\r
+ * \brief This function will wait for PLL0 locked\r
+ * \param pm Base address of the Power Manager (i.e. &AVR32_PM)\r
+ */\r
+extern void pm_wait_for_pll0_locked(volatile avr32_pm_t *pm);\r
+\r
+\r
+/*!\r
+ * \brief This function will wait for PLL1 locked\r
+ * \param pm Base address of the Power Manager (i.e. &AVR32_PM)\r
+ */\r
+extern void pm_wait_for_pll1_locked(volatile avr32_pm_t *pm);\r
+\r
+\r
+/*!\r
+ * \brief This function will switch the power manager main clock.\r
+ * \param pm Base address of the Power Manager (i.e. &AVR32_PM)\r
+ * \param clock Clock to be switched on. AVR32_PM_MCSEL_SLOW for RCOsc, AVR32_PM_MCSEL_OSC0 for Osc0, AVR32_PM_MCSEL_PLL0 for PLL0.\r
+ */\r
+extern void pm_switch_to_clock(volatile avr32_pm_t *pm, unsigned long clock);\r
+\r
+\r
+/*!\r
+ * \brief Switch main clock to clock Osc0 (crystal mode)\r
+ * \param pm Base address of the Power Manager (i.e. &AVR32_PM)\r
+ * \param fosc0 Oscillator 0 crystal frequency (Hz)\r
+ * \param startup Crystal 0 startup time. AVR32_PM_OSCCTRL0_STARTUP_x_RCOSC.\r
+ */\r
+extern void pm_switch_to_osc0(volatile avr32_pm_t *pm, unsigned int fosc0, unsigned int startup);\r
+\r
+\r
+/*! \brief Enables the Brown-Out Detector interrupt.\r
+ *\r
+ * \param pm Base address of the Power Manager (i.e. &AVR32_PM).\r
+ */\r
+extern void pm_bod_enable_irq(volatile avr32_pm_t *pm);\r
+\r
+\r
+/*! \brief Disables the Brown-Out Detector interrupt.\r
+ *\r
+ * \param pm Base address of the Power Manager (i.e. &AVR32_PM).\r
+ */\r
+extern void pm_bod_disable_irq(volatile avr32_pm_t *pm);\r
+\r
+\r
+/*! \brief Clears the Brown-Out Detector interrupt flag.\r
+ *\r
+ * \param pm Base address of the Power Manager (i.e. &AVR32_PM).\r
+ */\r
+extern void pm_bod_clear_irq(volatile avr32_pm_t *pm);\r
+\r
+\r
+/*! \brief Gets the Brown-Out Detector interrupt flag.\r
+ *\r
+ * \param pm Base address of the Power Manager (i.e. &AVR32_PM).\r
+ *\r
+ * \retval 0 No BOD interrupt.\r
+ * \retval 1 BOD interrupt pending.\r
+ */\r
+extern unsigned long pm_bod_get_irq_status(volatile avr32_pm_t *pm);\r
+\r
+\r
+/*! \brief Gets the Brown-Out Detector interrupt enable status.\r
+ *\r
+ * \param pm Base address of the Power Manager (i.e. &AVR32_PM).\r
+ *\r
+ * \retval 0 BOD interrupt disabled.\r
+ * \retval 1 BOD interrupt enabled.\r
+ */\r
+extern unsigned long pm_bod_get_irq_enable_bit(volatile avr32_pm_t *pm);\r
+\r
+\r
+/*! \brief Gets the triggering threshold of the Brown-Out Detector.\r
+ *\r
+ * \param pm Base address of the Power Manager (i.e. &AVR32_PM).\r
+ *\r
+ * \return Triggering threshold of the BOD. See the electrical characteristics\r
+ *         in the part datasheet for actual voltage levels.\r
+ */\r
+extern unsigned long pm_bod_get_level(volatile avr32_pm_t *pm);\r
+\r
+\r
+/*!\r
+ * \brief Read the content of the PM GPLP registers\r
+ * \param pm Base address of the Power Manager (i.e. &AVR32_PM)\r
+ * \param gplp GPLP register index (0,1,... depending on the number of GPLP registers for a given part)\r
+ *\r
+ * \return The content of the chosen GPLP register.\r
+ */\r
+extern unsigned long pm_read_gplp(volatile avr32_pm_t *pm, unsigned long gplp);\r
+\r
+\r
+/*!\r
+ * \brief Write into the PM GPLP registers\r
+ * \param pm Base address of the Power Manager (i.e. &AVR32_PM)\r
+ * \param gplp GPLP register index (0,1,... depending on the number of GPLP registers for a given part)\r
+ * \param value Value to write\r
+ */\r
+extern void pm_write_gplp(volatile avr32_pm_t *pm, unsigned long gplp, unsigned long value);\r
+\r
+\r
+/*! \brief Enable the clock of a module.\r
+ *\r
+ * \param pm Base address of the Power Manager (i.e. &AVR32_PM)\r
+ * \param module The module to clock (use one of the defines in the part-specific\r
+ * header file under "toolchain folder"/avr32/inc(lude)/avr32/; depending on the\r
+ * clock domain, look for the sections "CPU clocks", "HSB clocks", "PBx clocks")\r
+ *\r
+ * \return Status.\r
+ *   \retval 0  Success.\r
+ *   \retval <0 An error occured.\r
+ */\r
+extern long pm_enable_module(volatile avr32_pm_t *pm, unsigned long module);\r
+\r
+/*! \brief Disable the clock of a module.\r
+ *\r
+ * \param pm Base address of the Power Manager (i.e. &AVR32_PM)\r
+ * \param module The module to shut down (use one of the defines in the part-specific\r
+ * header file under "toolchain folder"/avr32/inc(lude)/avr32/; depending on the\r
+ * clock domain, look for the sections "CPU clocks", "HSB clocks", "PBx clocks")\r
+ *\r
+ * \return Status.\r
+ *   \retval 0  Success.\r
+ *   \retval <0 An error occured.\r
+ */\r
+extern long pm_disable_module(volatile avr32_pm_t *pm, unsigned long module);\r
+\r
+\r
+\r
+/*! \brief Automatically configure the CPU, PBA, PBB, and HSB clocks\r
+ *         according to the user wishes.\r
+ *\r
+ * This function needs some parameters stored in a pm_freq_param_t structure:\r
+ *  - cpu_f and pba_f are the wanted frequencies,\r
+ *  - osc0_f is the oscillator 0 on-board frequency (e.g. FOSC0),\r
+ *  - osc0_startup is the oscillator 0 startup time (e.g. OSC0_STARTUP).\r
+ *\r
+ * The function will then configure the clocks using the following rules:\r
+ *  - It first try to find a valid PLL frequency (the highest possible value to avoid jitter) in order\r
+ *    to satisfy the CPU frequency,\r
+ *  - It optimizes the configuration depending the various divide stages,\r
+ *  - Then, the PBA frequency is configured from the CPU freq.\r
+ *  - Note that HSB and PBB are configured with the same frequency as CPU.\r
+ *  - Note also that the number of wait states of the flash read accesses is automatically set-up depending\r
+ *    the CPU frequency. As a consequence, the application needs the FLASHC driver to compile.\r
+ *\r
+ * The CPU, HSB and PBA frequencies programmed after configuration are stored back into cpu_f and pba_f.\r
+ *\r
+ * \param param    pointer on the configuration structure.\r
+ *\r
+ * \retval PM_FREQ_STATUS_OK    Mode successfully initialized.\r
+ * \retval PM_FREQ_STATUS_FAIL  The configuration can not be done.\r
+ */\r
+extern int pm_configure_clocks(pm_freq_param_t *param);\r
+\r
+\r
+/*! \brief Automatically configure the USB clock.\r
+ *\r
+ * USB clock is configured to 48MHz, using the PLL1 from the Oscillator0, assuming\r
+ * a 12 MHz crystal is connected to it.\r
+ */\r
+extern void pm_configure_usb_clock(void);\r
+\r
+\r
+#endif  // _PM_H_\r

diff --git a/Demo/AVR32_UC3A_GCC/Atmel_SW_Framework/DRIVERS/PM/pm_conf_clocks.c b/Demo/AVR32_UC3A_GCC/Atmel_SW_Framework/DRIVERS/PM/pm_conf_clocks.c
new file mode 100644 (file)
index 0000000..9fd07e9
--- /dev/null
+++ b/Demo/AVR32_UC3A_GCC/Atmel_SW_Framework/DRIVERS/PM/pm_conf_clocks.c
@@ -0,0 +1,268 @@
+/* This source file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */\r
+
+/*This file has been prepared for Doxygen automatic documentation generation.*/\r
+/*! \file *********************************************************************\r
+ *\r
+ * \brief Power Manager clocks configuration helper.\r
+ *\r
+ *\r
+ * - Compiler:           IAR EWAVR32 and GNU GCC for AVR32\r
+ * - Supported devices:  All AVR32 devices.\r
+ * - AppNote:\r
+ *\r
+ * \author               Atmel Corporation: http://www.atmel.com \n\r
+ *                       Support and FAQ: http://support.atmel.no/\r
+ *\r
+ *****************************************************************************/\r
+\r
+/* Copyright (c) 2009 Atmel Corporation. All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice, this\r
+ * list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an Atmel\r
+ * AVR product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\r
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\r
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\r
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE\r
+ *\r
+ */\r
+\r
+#include <string.h>\r
+#include "compiler.h"\r
+#include "pm.h"\r
+\r
+extern void flashc_set_wait_state(unsigned int wait_state);\r
+#if (defined AVR32_FLASHC_210_H_INCLUDED)\r
+extern void flashc_issue_command(unsigned int command, int page_number);\r
+#endif\r
+\r
+\r
+#define PM_MAX_MUL                ((1 << AVR32_PM_PLL0_PLLMUL_SIZE) - 1)\r
+\r
+\r
+int pm_configure_clocks(pm_freq_param_t *param)\r
+{\r
+  // Supported frequencies:\r
+  // Fosc0 mul div PLL div2_en cpu_f pba_f   Comment\r
+  //  12   15   1  192     1     12    12\r
+  //  12    9   3   40     1     20    20    PLL out of spec\r
+  //  12   15   1  192     1     24    12\r
+  //  12    9   1  120     1     30    15\r
+  //  12    9   3   40     0     40    20    PLL out of spec\r
+  //  12   15   1  192     1     48    12\r
+  //  12   15   1  192     1     48    24\r
+  //  12    8   1  108     1     54    27\r
+  //  12    9   1  120     1     60    15\r
+  //  12    9   1  120     1     60    30\r
+  //  12   10   1  132     1     66    16.5\r
+  //\r
+  unsigned long in_cpu_f  = param->cpu_f;\r
+  unsigned long in_osc0_f = param->osc0_f;\r
+  unsigned long mul, div, div2_en = 0, div2_cpu = 0, div2_pba = 0;\r
+  unsigned long pll_freq, rest;\r
+  Bool b_div2_pba, b_div2_cpu;\r
+\r
+  // Switch to external Oscillator 0\r
+  pm_switch_to_osc0(&AVR32_PM, in_osc0_f, param->osc0_startup);\r
+\r
+  // Start with CPU freq config\r
+  if (in_cpu_f == in_osc0_f)\r
+  {\r
+    param->cpu_f = in_osc0_f;\r
+    param->pba_f = in_osc0_f;\r
+    return PM_FREQ_STATUS_OK;\r
+  }\r
+  else if (in_cpu_f < in_osc0_f)\r
+  {\r
+    // TBD\r
+  }\r
+\r
+  rest = in_cpu_f % in_osc0_f;\r
+\r
+  for (div = 1; div < 32; div++)\r
+  {\r
+    if ((div * rest) % in_osc0_f == 0)\r
+      break;\r
+  }\r
+  if (div == 32)\r
+    return PM_FREQ_STATUS_FAIL;\r
+\r
+  mul = (in_cpu_f * div) / in_osc0_f;\r
+\r
+  if (mul > PM_MAX_MUL)\r
+    return PM_FREQ_STATUS_FAIL;\r
+\r
+  // export 2power from PLL div to div2_cpu\r
+  while (!(div % 2))\r
+  {\r
+    div /= 2;\r
+    div2_cpu++;\r
+  }\r
+\r
+  // Here we know the mul and div parameter of the PLL config.\r
+  // . Check out if the PLL has a valid in_cpu_f.\r
+  // . Try to have for the PLL frequency (VCO output) the highest possible value\r
+  //   to reduce jitter.\r
+  while (in_osc0_f * 2 * mul / div < AVR32_PM_PLL_VCO_RANGE0_MAX_FREQ)\r
+  {\r
+    if (2 * mul > PM_MAX_MUL)\r
+      break;\r
+    mul *= 2;\r
+    div2_cpu++;\r
+  }\r
+\r
+  if (div2_cpu != 0)\r
+  {\r
+    div2_cpu--;\r
+    div2_en = 1;\r
+  }\r
+\r
+  pll_freq = in_osc0_f * mul / (div * (1 << div2_en));\r
+\r
+  // Update real CPU Frequency\r
+  param->cpu_f = pll_freq / (1 << div2_cpu);\r
+  mul--;\r
+\r
+  pm_pll_setup(&AVR32_PM\r
+  , 0   // pll\r
+  , mul // mul\r
+  , div // div\r
+  , 0   // osc\r
+  , 16  // lockcount\r
+  );\r
+\r
+  pm_pll_set_option(&AVR32_PM\r
+  , 0 // pll\r
+  // PLL clock is lower than 160MHz: need to set pllopt.\r
+  , (pll_freq < AVR32_PM_PLL_VCO_RANGE0_MIN_FREQ) ? 1 : 0 // pll_freq\r
+  , div2_en // pll_div2\r
+  , 0 // pll_wbwdisable\r
+  );\r
+\r
+  rest = pll_freq;\r
+  while (rest > AVR32_PM_PBA_MAX_FREQ ||\r
+         rest != param->pba_f)\r
+  {\r
+    div2_pba++;\r
+    rest = pll_freq / (1 << div2_pba);\r
+    if (rest < param->pba_f)\r
+      break;\r
+  }\r
+\r
+  // Update real PBA Frequency\r
+  param->pba_f = pll_freq / (1 << div2_pba);\r
+\r
+  // Enable PLL0\r
+  pm_pll_enable(&AVR32_PM, 0);\r
+\r
+  // Wait for PLL0 locked\r
+  pm_wait_for_pll0_locked(&AVR32_PM);\r
+\r
+  if (div2_cpu)\r
+  {\r
+    b_div2_cpu = TRUE;\r
+    div2_cpu--;\r
+  }\r
+  else\r
+    b_div2_cpu = FALSE;\r
+\r
+  if (div2_pba)\r
+  {\r
+    b_div2_pba = TRUE;\r
+    div2_pba--;\r
+  }\r
+  else\r
+    b_div2_pba = FALSE;\r
+\r
+  pm_cksel(&AVR32_PM\r
+  , b_div2_pba, div2_pba // PBA\r
+  , b_div2_cpu, div2_cpu // PBB\r
+  , b_div2_cpu, div2_cpu // HSB\r
+  );\r
+\r
+  if (param->cpu_f > AVR32_FLASHC_FWS_0_MAX_FREQ)\r
+  {\r
+    flashc_set_wait_state(1);\r
+#if (defined AVR32_FLASHC_210_H_INCLUDED)\r
+    if (param->cpu_f > AVR32_FLASHC_HSEN_FWS_1_MAX_FREQ)\r
+      flashc_issue_command(AVR32_FLASHC_FCMD_CMD_HSEN, -1);\r
+    else\r
+      flashc_issue_command(AVR32_FLASHC_FCMD_CMD_HSDIS, -1);\r
+#endif\r
+  }\r
+  else\r
+  {\r
+    flashc_set_wait_state(0);\r
+#if (defined AVR32_FLASHC_210_H_INCLUDED)\r
+    if (param->cpu_f > AVR32_FLASHC_HSEN_FWS_0_MAX_FREQ)\r
+      flashc_issue_command(AVR32_FLASHC_FCMD_CMD_HSEN, -1);\r
+    else\r
+      flashc_issue_command(AVR32_FLASHC_FCMD_CMD_HSDIS, -1);\r
+#endif\r
+  }\r
+\r
+  pm_switch_to_clock(&AVR32_PM, AVR32_PM_MCCTRL_MCSEL_PLL0);\r
+\r
+  return PM_FREQ_STATUS_OK;\r
+}\r
+\r
+\r
+void pm_configure_usb_clock(void)\r
+{\r
+#if UC3A3\r
+\r
+  // Setup USB GCLK.\r
+  pm_gc_setup(&AVR32_PM, AVR32_PM_GCLK_USBB, // gc\r
+                  0,                  // osc_or_pll: use Osc (if 0) or PLL (if 1)\r
+                  0,                  // pll_osc: select Osc0/PLL0 or Osc1/PLL1\r
+                  0,                  // diven\r
+                  0);                 // div\r
+\r
+  // Enable USB GCLK.\r
+  pm_gc_enable(&AVR32_PM, AVR32_PM_GCLK_USBB);\r
+#else\r
+  // Use 12MHz from OSC0 and generate 96 MHz\r
+  pm_pll_setup(&AVR32_PM, 1,  // pll.\r
+         7,   // mul.\r
+         1,   // div.\r
+         0,   // osc.\r
+         16); // lockcount.\r
+\r
+  pm_pll_set_option(&AVR32_PM, 1, // pll.\r
+         1,  // pll_freq: choose the range 80-180MHz.\r
+         1,  // pll_div2.\r
+         0); // pll_wbwdisable.\r
+\r
+  // start PLL1 and wait forl lock\r
+  pm_pll_enable(&AVR32_PM, 1);\r
+\r
+  // Wait for PLL1 locked.\r
+  pm_wait_for_pll1_locked(&AVR32_PM);\r
+\r
+  pm_gc_setup(&AVR32_PM, AVR32_PM_GCLK_USBB,  // gc.\r
+            1,  // osc_or_pll: use Osc (if 0) or PLL (if 1).\r
+            1,  // pll_osc: select Osc0/PLL0 or Osc1/PLL1.\r
+            0,  // diven.\r
+            0); // div.\r
+  pm_gc_enable(&AVR32_PM, AVR32_PM_GCLK_USBB);\r
+#endif\r
+}\r

diff --git a/Demo/AVR32_UC3A_GCC/Atmel_SW_Framework/DRIVERS/PM/power_clocks_lib.c b/Demo/AVR32_UC3A_GCC/Atmel_SW_Framework/DRIVERS/PM/power_clocks_lib.c
new file mode 100644 (file)
index 0000000..3f549d6
--- /dev/null
+++ b/Demo/AVR32_UC3A_GCC/Atmel_SW_Framework/DRIVERS/PM/power_clocks_lib.c
@@ -0,0 +1,566 @@
+/* This source file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */\r
+
+/*This file has been prepared for Doxygen automatic documentation generation.*/\r
+/*! \file *********************************************************************\r
+ *\r
+ * \brief High-level library abstracting features such as oscillators/pll/dfll\r
+ *        configuration, clock configuration, System-sensible parameters\r
+ *        configuration, buses clocks configuration, sleep mode, reset.\r
+ *\r
+ *\r
+ * - Compiler:           IAR EWAVR32 and GNU GCC for AVR32\r
+ * - Supported devices:  All AVR32 devices.\r
+ * - AppNote:\r
+ *\r
+ * \author               Atmel Corporation: http://www.atmel.com \n\r
+ *                       Support and FAQ: http://support.atmel.no/\r
+ *\r
+ *****************************************************************************/\r
+\r
+/* Copyright (c) 2009 Atmel Corporation. All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice, this\r
+ * list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an Atmel\r
+ * AVR product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\r
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\r
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\r
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE\r
+ *\r
+ */\r
+#include "power_clocks_lib.h"\r
+\r
+\r
+//! Device-specific data\r
+#if UC3L\r
+static long int pcl_configure_clocks_uc3l(pcl_freq_param_t *param); // FORWARD declaration\r
+#endif\r
+\r
+#if UC3C\r
+static long int pcl_configure_clocks_uc3c(pcl_freq_param_t *param); // FORWARD declaration\r
+#endif\r
+\r
+long int pcl_configure_clocks(pcl_freq_param_t *param)\r
+{\r
+#ifndef AVR32_PM_VERSION_RESETVALUE\r
+  // Implementation for UC3A, UC3A3, UC3B parts.\r
+  return(pm_configure_clocks(param));\r
+#else\r
+  #ifdef AVR32_PM_410_H_INCLUDED\r
+    // Implementation for UC3C parts.\r
+    return(pcl_configure_clocks_uc3c(param));\r
+  #else\r
+    // Implementation for UC3L parts.\r
+    return(pcl_configure_clocks_uc3l(param));\r
+  #endif\r
+#endif\r
+}\r
+\r
+\r
+//! Device-specific implementation\r
+#if UC3L\r
+// FORWARD declaration\r
+static long int pcl_configure_synchronous_clocks( pm_clk_src_t main_clk_src,\r
+                                                  unsigned long main_clock_freq_hz,\r
+                                                  pcl_freq_param_t *param);\r
+\r
+long int pcl_configure_clocks_rcsys(pcl_freq_param_t *param)\r
+{\r
+  // Supported main clock sources: PCL_MC_RCSYS\r
+\r
+  // Supported synchronous clocks frequencies if RCSYS is the main clock source:\r
+  // 115200Hz, 57600Hz, 28800Hz, 14400Hz, 7200Hz, 3600Hz, 1800Hz, 900Hz, 450Hz.\r
+\r
+  // NOTE: by default, this implementation doesn't perform thorough checks on the\r
+  // input parameters. To enable the checks, define AVR32SFW_INPUT_CHECK.\r
+\r
+#ifdef AVR32SFW_INPUT_CHECK\r
+  // Verify that fCPU >= fPBx\r
+  if((param->cpu_f < param->pba_f) || (param->cpu_f < param->pbb_f))\r
+    return(-1);\r
+#endif\r
+\r
+#ifdef AVR32SFW_INPUT_CHECK\r
+    // Verify that the target frequencies are reachable.\r
+    if((param->cpu_f > SCIF_SLOWCLOCK_FREQ_HZ) || (param->pba_f > SCIF_SLOWCLOCK_FREQ_HZ)\r
+      || (param->pbb_f > SCIF_SLOWCLOCK_FREQ_HZ))\r
+      return(-1);\r
+#endif\r
+\r
+  return(pcl_configure_synchronous_clocks(PM_CLK_SRC_SLOW, SCIF_SLOWCLOCK_FREQ_HZ, param));\r
+}\r
+\r
+\r
+long int pcl_configure_clocks_rc120m(pcl_freq_param_t *param)\r
+{\r
+  // Supported main clock sources: PCL_MC_RC120M\r
+\r
+  // Supported synchronous clocks frequencies if RC120M is the main clock source:\r
+  // 30MHz, 15MHz, 7.5MHz, 3.75MHz, 1.875MHz, 937.5kHz, 468.75kHz.\r
+\r
+  // NOTE: by default, this implementation doesn't perform thorough checks on the\r
+  // input parameters. To enable the checks, define AVR32SFW_INPUT_CHECK.\r
+\r
+#ifdef AVR32SFW_INPUT_CHECK\r
+  // Verify that fCPU >= fPBx\r
+  if((param->cpu_f < param->pba_f) || (param->cpu_f < param->pbb_f))\r
+    return(-1);\r
+#endif\r
+\r
+#ifdef AVR32SFW_INPUT_CHECK\r
+  // Verify that the target frequencies are reachable.\r
+  if((param->cpu_f > SCIF_RC120M_FREQ_HZ) || (param->pba_f > SCIF_RC120M_FREQ_HZ)\r
+    || (param->pbb_f > SCIF_RC120M_FREQ_HZ))\r
+    return(-1);\r
+#endif\r
+\r
+  // Start the 120MHz internal RCosc (RC120M) clock\r
+  scif_start_rc120M();\r
+\r
+  return(pcl_configure_synchronous_clocks(PM_CLK_SRC_RC120M, SCIF_RC120M_FREQ_HZ, param));\r
+}\r
+\r
+\r
+long int pcl_configure_clocks_osc0(pcl_freq_param_t *param)\r
+{\r
+  // Supported main clock sources: PCL_MC_OSC0\r
+\r
+  // Supported synchronous clocks frequencies if OSC0 is the main clock source:\r
+  // (these obviously depend on the OSC0 frequency; we'll take 16MHz as an example)\r
+  // 16MHz, 8MHz, 4MHz, 2MHz, 1MHz, 500kHz, 250kHz, 125kHz, 62.5kHz.\r
+\r
+  // NOTE: by default, this implementation doesn't perform thorough checks on the\r
+  // input parameters. To enable the checks, define AVR32SFW_INPUT_CHECK.\r
+\r
+  unsigned long               main_clock_freq;\r
+\r
+\r
+#ifdef AVR32SFW_INPUT_CHECK\r
+  // Verify that fCPU >= fPBx\r
+  if((param->cpu_f < param->pba_f) || (param->cpu_f < param->pbb_f))\r
+    return(-1);\r
+#endif\r
+\r
+  main_clock_freq = param->osc0_f;\r
+#ifdef AVR32SFW_INPUT_CHECK\r
+  // Verify that the target frequencies are reachable.\r
+  if((param->cpu_f > main_clock_freq) || (param->pba_f > main_clock_freq)\r
+    || (param->pbb_f > main_clock_freq))\r
+    return(-1);\r
+#endif\r
+  // Configure OSC0 in crystal mode, external crystal with a fcrystal Hz frequency.\r
+  scif_configure_osc_crystalmode(SCIF_OSC0, main_clock_freq);\r
+  // Enable the OSC0\r
+  scif_enable_osc(SCIF_OSC0, param->osc0_startup, true);\r
+\r
+  return(pcl_configure_synchronous_clocks(PM_CLK_SRC_OSC0, main_clock_freq, param));\r
+}\r
+\r
+\r
+long int pcl_configure_clocks_dfll0(pcl_freq_param_t *param)\r
+{\r
+  // Supported main clock sources: PCL_MC_DFLL\r
+\r
+  // Supported synchronous clocks frequencies if DFLL is the main clock source:\r
+  // (these obviously depend on the DFLL target frequency; we'll take 100MHz as an example)\r
+  // 50MHz, 25MHz, 12.5MHz, 6.25MHz, 3.125MHz, 1562.5kHz, 781.25kHz, 390.625kHz.\r
+\r
+  // NOTE: by default, this implementation doesn't perform thorough checks on the\r
+  // input parameters. To enable the checks, define AVR32SFW_INPUT_CHECK.\r
+\r
+  unsigned long   main_clock_freq;\r
+  scif_gclk_opt_t *pgc_dfllif_ref_opt;\r
+\r
+\r
+#ifdef AVR32SFW_INPUT_CHECK\r
+  // Verify that fCPU >= fPBx\r
+  if((param->cpu_f < param->pba_f) || (param->cpu_f < param->pbb_f))\r
+    return(-1);\r
+#endif\r
+\r
+  main_clock_freq = param->dfll_f;\r
+#ifdef AVR32SFW_INPUT_CHECK\r
+  // Verify that the target DFLL output frequency is in the correct range.\r
+  if((main_clock_freq > SCIF_DFLL_MAXFREQ_HZ) || (main_clock_freq < SCIF_DFLL_MINFREQ_HZ))\r
+    return(-1);\r
+  // Verify that the target frequencies are reachable.\r
+  if((param->cpu_f > main_clock_freq) || (param->pba_f > main_clock_freq)\r
+    || (param->pbb_f > main_clock_freq))\r
+    return(-1);\r
+#endif\r
+  pgc_dfllif_ref_opt = (scif_gclk_opt_t *)param->pextra_params;\r
+  // Implementation note: this implementation configures the DFLL in closed-loop\r
+  // mode (because it gives the best accuracy) which enables the generic clock CLK_DFLLIF_REF\r
+  // as a reference (RCSYS being used as the generic clock source, undivided).\r
+  scif_dfll0_closedloop_configure_and_start(pgc_dfllif_ref_opt, main_clock_freq, TRUE);\r
+\r
+  return(pcl_configure_synchronous_clocks(PM_CLK_SRC_DFLL0, main_clock_freq, param));\r
+}\r
+\r
+\r
+static long int pcl_configure_clocks_uc3l(pcl_freq_param_t *param)\r
+{\r
+  // Supported main clock sources: PCL_MC_RCSYS, PCL_MC_OSC0, PCL_MC_DFLL0, PCL_MC_RC120M\r
+\r
+  // Supported synchronous clocks frequencies if RCSYS is the main clock source:\r
+  // 115200Hz, 57600Hz, 28800Hz, 14400Hz, 7200Hz, 3600Hz, 1800Hz, 900Hz, 450Hz.\r
+\r
+  // Supported synchronous clocks frequencies if RC120M is the main clock source:\r
+  // 30MHz, 15MHz, 7.5MHz, 3.75MHz, 1.875MHz, 937.5kHz, 468.75kHz.\r
+\r
+  // Supported synchronous clocks frequencies if OSC0 is the main clock source:\r
+  // (these obviously depend on the OSC0 frequency; we'll take 16MHz as an example)\r
+  // 16MHz, 8MHz, 4MHz, 2MHz, 1MHz, 500kHz, 250kHz, 125kHz, 62.5kHz.\r
+\r
+  // Supported synchronous clocks frequencies if DFLL is the main clock source:\r
+  // (these obviously depend on the DFLL target frequency; we'll take 100MHz as an example)\r
+  // 50MHz, 25MHz, 12.5MHz, 6.25MHz, 3.125MHz, 1562.5kHz, 781.25kHz, 390.625kHz.\r
+\r
+  // NOTE: by default, this implementation doesn't perform thorough checks on the\r
+  // input parameters. To enable the checks, define AVR32SFW_INPUT_CHECK.\r
+\r
+\r
+#ifdef AVR32SFW_INPUT_CHECK\r
+  // Verify that fCPU >= fPBx\r
+  if((param->cpu_f < param->pba_f) || (param->cpu_f < param->pbb_f))\r
+    return(-1);\r
+#endif\r
+\r
+  if(PCL_MC_RCSYS == param->main_clk_src)\r
+  {\r
+    return(pcl_configure_clocks_rcsys(param));\r
+  }\r
+  else if(PCL_MC_RC120M == param->main_clk_src)\r
+  {\r
+    return(pcl_configure_clocks_rc120m(param));\r
+  }\r
+  else if(PCL_MC_OSC0 == param->main_clk_src)\r
+  {\r
+    return(pcl_configure_clocks_osc0(param));\r
+  }\r
+  else // PCL_MC_DFLL0 == param->main_clk_src\r
+  {\r
+    return(pcl_configure_clocks_dfll0(param));\r
+  }\r
+}\r
+\r
+static long int pcl_configure_synchronous_clocks(pm_clk_src_t main_clk_src, unsigned long main_clock_freq_hz, pcl_freq_param_t *param)\r
+{\r
+  //#\r
+  //# Set the Synchronous clock division ratio for each clock domain\r
+  //#\r
+  pm_set_all_cksel(main_clock_freq_hz, param->cpu_f, param->pba_f, param->pbb_f);\r
+\r
+  //#\r
+  //# Set the Flash wait state and the speed read mode (depending on the target CPU frequency).\r
+  //#\r
+#if UC3L\r
+    flashcdw_set_flash_waitstate_and_readmode(param->cpu_f);\r
+#elif UC3C\r
+    flashc_set_flash_waitstate_and_readmode(param->cpu_f);\r
+#endif\r
+\r
+\r
+  //#\r
+  //# Switch the main clock source to the selected clock.\r
+  //#\r
+  pm_set_mclk_source(main_clk_src);\r
+\r
+  return PASS;\r
+}\r
+\r
+#endif // UC3L device-specific implementation\r
+\r
+//! UC3C Device-specific implementation\r
+#if UC3C\r
+static long int pcl_configure_clocks_uc3c(pcl_freq_param_t *param)\r
+{\r
+  #define PM_MAX_MUL                         ((1 << AVR32_SCIF_PLLMUL_SIZE) - 1)\r
+  #define AVR32_PM_PBA_MAX_FREQ              66000000\r
+  #define AVR32_PM_PLL_VCO_RANGE0_MAX_FREQ   240000000\r
+  #define AVR32_PM_PLL_VCO_RANGE0_MIN_FREQ   160000000\r
+\r
+    // Implementation for  UC3C parts.\r
+        // Supported frequencies:\r
+        // Fosc0 mul div PLL div2_en cpu_f pba_f   Comment\r
+        //  12   15   1  192     1     12    12\r
+        //  12    9   3   40     1     20    20    PLL out of spec\r
+        //  12   15   1  192     1     24    12\r
+        //  12    9   1  120     1     30    15\r
+        //  12    9   3   40     0     40    20    PLL out of spec\r
+        //  12   15   1  192     1     48    12\r
+        //  12   15   1  192     1     48    24\r
+        //  12    8   1  108     1     54    27\r
+        //  12    9   1  120     1     60    15\r
+        //  12    9   1  120     1     60    30\r
+        //  12   10   1  132     1     66    16.5\r
+        //\r
+        unsigned long in_cpu_f  = param->cpu_f;\r
+        unsigned long in_osc0_f = param->osc0_f;\r
+        unsigned long mul, div, div2_en = 0, div2_cpu = 0, div2_pba = 0;\r
+        unsigned long pll_freq, rest;\r
+        Bool b_div2_pba, b_div2_cpu;\r
+\r
+        // Configure OSC0 in crystal mode, external crystal with a FOSC0 Hz frequency.\r
+        scif_configure_osc_crystalmode(SCIF_OSC0, in_osc0_f);\r
+        // Enable the OSC0\r
+        scif_enable_osc(SCIF_OSC0, param->osc0_startup, true);\r
+        // Set the main clock source as being OSC0.\r
+        pm_set_mclk_source(PM_CLK_SRC_OSC0);\r
+\r
+        // Start with CPU freq config\r
+        if (in_cpu_f == in_osc0_f)\r
+        {\r
+          param->cpu_f = in_osc0_f;\r
+          param->pba_f = in_osc0_f;\r
+          return PASS;\r
+        }\r
+        else if (in_cpu_f < in_osc0_f)\r
+        {\r
+          // TBD\r
+        }\r
+\r
+        rest = in_cpu_f % in_osc0_f;\r
+\r
+        for (div = 1; div < 32; div++)\r
+        {\r
+          if ((div * rest) % in_osc0_f == 0)\r
+            break;\r
+        }\r
+        if (div == 32)\r
+          return FAIL;\r
+\r
+        mul = (in_cpu_f * div) / in_osc0_f;\r
+\r
+        if (mul > PM_MAX_MUL)\r
+          return FAIL;\r
+\r
+        // export 2power from PLL div to div2_cpu\r
+        while (!(div % 2))\r
+        {\r
+          div /= 2;\r
+          div2_cpu++;\r
+        }\r
+\r
+        // Here we know the mul and div parameter of the PLL config.\r
+        // . Check out if the PLL has a valid in_cpu_f.\r
+        // . Try to have for the PLL frequency (VCO output) the highest possible value\r
+        //   to reduce jitter.\r
+        while (in_osc0_f * 2 * mul / div < AVR32_PM_PLL_VCO_RANGE0_MAX_FREQ)\r
+        {\r
+          if (2 * mul > PM_MAX_MUL)\r
+            break;\r
+          mul *= 2;\r
+          div2_cpu++;\r
+        }\r
+\r
+        if (div2_cpu != 0)\r
+        {\r
+          div2_cpu--;\r
+          div2_en = 1;\r
+        }\r
+\r
+        pll_freq = in_osc0_f * mul / (div * (1 << div2_en));\r
+\r
+        // Update real CPU Frequency\r
+        param->cpu_f = pll_freq / (1 << div2_cpu);\r
+        mul--;\r
+\r
+        scif_pll_opt_t opt;\r
+\r
+        opt.osc = SCIF_OSC0,     // Sel Osc0 or Osc1\r
+        opt.lockcount = 16,      // lockcount in main clock for the PLL wait lock\r
+        opt.div = div,             // DIV=1 in the formula\r
+        opt.mul = mul,             // MUL=7 in the formula\r
+        opt.pll_div2 = div2_en,        // pll_div2 Divide the PLL output frequency by 2 (this settings does not change the FVCO value)\r
+        opt.pll_wbwdisable = 0,  //pll_wbwdisable 1 Disable the Wide-Bandith Mode (Wide-Bandwith mode allow a faster startup time and out-of-lock time). 0 to enable the Wide-Bandith Mode.\r
+        opt.pll_freq = (pll_freq < AVR32_PM_PLL_VCO_RANGE0_MIN_FREQ) ? 1 : 0,        // Set to 1 for VCO frequency range 80-180MHz, set to 0 for VCO frequency range 160-240Mhz.\r
+\r
+\r
+        scif_pll_setup(SCIF_PLL0, opt); // lockcount in main clock for the PLL wait lock\r
+\r
+        /* Enable PLL0 */\r
+        scif_pll_enable(SCIF_PLL0);\r
+\r
+        /* Wait for PLL0 locked */\r
+        scif_wait_for_pll_locked(SCIF_PLL0) ;\r
+\r
+        rest = pll_freq;\r
+        while (rest > AVR32_PM_PBA_MAX_FREQ ||\r
+               rest != param->pba_f)\r
+        {\r
+          div2_pba++;\r
+          rest = pll_freq / (1 << div2_pba);\r
+          if (rest < param->pba_f)\r
+            break;\r
+        }\r
+\r
+        // Update real PBA Frequency\r
+        param->pba_f = pll_freq / (1 << div2_pba);\r
+\r
+\r
+        if (div2_cpu)\r
+        {\r
+          b_div2_cpu = TRUE;\r
+          div2_cpu--;\r
+        }\r
+        else\r
+          b_div2_cpu = FALSE;\r
+\r
+        if (div2_pba)\r
+        {\r
+          b_div2_pba = TRUE;\r
+          div2_pba--;\r
+        }\r
+        else\r
+          b_div2_pba = FALSE;\r
+\r
+        if (b_div2_cpu == TRUE )\r
+        {\r
+          pm_set_clk_domain_div(PM_CLK_DOMAIN_0, (pm_divratio_t) div2_cpu); // CPU\r
+          pm_set_clk_domain_div(PM_CLK_DOMAIN_1, (pm_divratio_t) div2_cpu); // HSB\r
+          pm_set_clk_domain_div(PM_CLK_DOMAIN_3, (pm_divratio_t) div2_cpu); // PBB\r
+        }\r
+        if (b_div2_pba == TRUE )\r
+        {\r
+          pm_set_clk_domain_div(PM_CLK_DOMAIN_2, (pm_divratio_t) div2_pba); // PBA\r
+          pm_set_clk_domain_div(PM_CLK_DOMAIN_4, (pm_divratio_t) div2_pba); // PBC\r
+        }\r
+\r
+        // Set Flashc Wait State\r
+        flashc_set_flash_waitstate_and_readmode(param->cpu_f);\r
+\r
+        // Set the main clock source as being PLL0.\r
+        pm_set_mclk_source(PM_CLK_SRC_PLL0);\r
+\r
+        return PASS;\r
+}\r
+#endif // UC3C device-specific implementation\r
+\r
+long int pcl_switch_to_osc(pcl_osc_t osc, unsigned int fcrystal, unsigned int startup)\r
+{\r
+#ifndef AVR32_PM_VERSION_RESETVALUE\r
+// Implementation for UC3A, UC3A3, UC3B parts.\r
+  if(PCL_OSC0 == osc)\r
+  {\r
+    // Configure OSC0 in crystal mode, external crystal with a FOSC0 Hz frequency,\r
+    // enable the OSC0, set the main clock source as being OSC0.\r
+    pm_switch_to_osc0(&AVR32_PM, fcrystal, startup);\r
+  }\r
+  else\r
+  {\r
+    return PCL_NOT_SUPPORTED;\r
+  }\r
+#else\r
+// Implementation for UC3C, UC3L parts.\r
+  #if AVR32_PM_VERSION_RESETVALUE < 0x400\r
+    return PCL_NOT_SUPPORTED;\r
+  #else\r
+  if(PCL_OSC0 == osc)\r
+  {\r
+    // Configure OSC0 in crystal mode, external crystal with a fcrystal Hz frequency.\r
+    scif_configure_osc_crystalmode(SCIF_OSC0, fcrystal);\r
+    // Enable the OSC0\r
+    scif_enable_osc(SCIF_OSC0, startup, true);\r
+    // Set the Flash wait state and the speed read mode (depending on the target CPU frequency).\r
+#if UC3L\r
+    flashcdw_set_flash_waitstate_and_readmode(fcrystal);\r
+#elif UC3C\r
+    flashc_set_flash_waitstate_and_readmode(fcrystal);\r
+#endif\r
+    // Set the main clock source as being OSC0.\r
+    pm_set_mclk_source(PM_CLK_SRC_OSC0);\r
+  }\r
+  else\r
+  {\r
+    return PCL_NOT_SUPPORTED;\r
+  }\r
+  #endif\r
+#endif\r
+  return PASS;\r
+}\r
+\r
+long int pcl_configure_usb_clock(void)\r
+{\r
+#ifndef AVR32_PM_VERSION_RESETVALUE\r
+// Implementation for UC3A, UC3A3, UC3B parts.\r
+  pm_configure_usb_clock();\r
+  return PASS;\r
+#else\r
+  #ifdef AVR32_PM_410_H_INCLUDED\r
+    const scif_pll_opt_t opt = {\r
+              .osc = SCIF_OSC0,     // Sel Osc0 or Osc1\r
+              .lockcount = 16,      // lockcount in main clock for the PLL wait lock\r
+              .div = 1,             // DIV=1 in the formula\r
+              .mul = 5,             // MUL=7 in the formula\r
+              .pll_div2 = 1,        // pll_div2 Divide the PLL output frequency by 2 (this settings does not change the FVCO value)\r
+              .pll_wbwdisable = 0,  //pll_wbwdisable 1 Disable the Wide-Bandith Mode (Wide-Bandwith mode allow a faster startup time and out-of-lock time). 0 to enable the Wide-Bandith Mode.\r
+              .pll_freq = 1,        // Set to 1 for VCO frequency range 80-180MHz, set to 0 for VCO frequency range 160-240Mhz.\r
+    };\r
+\r
+    /* Setup PLL1 on Osc0, mul=7 ,no divisor, lockcount=16, ie. 16Mhzx6 = 96MHz output */\r
+    scif_pll_setup(SCIF_PLL1, opt); // lockcount in main clock for the PLL wait lock\r
+\r
+    /* Enable PLL1 */\r
+    scif_pll_enable(SCIF_PLL1);\r
+\r
+    /* Wait for PLL1 locked */\r
+    scif_wait_for_pll_locked(SCIF_PLL1) ;\r
+\r
+  // Implementation for UC3C parts.\r
+    // Setup the generic clock for USB\r
+    scif_gc_setup(AVR32_SCIF_GCLK_USB,\r
+                  SCIF_GCCTRL_PLL1,\r
+                  AVR32_SCIF_GC_NO_DIV_CLOCK,\r
+                  0);\r
+    // Now enable the generic clock\r
+    scif_gc_enable(AVR32_SCIF_GCLK_USB);\r
+    return PASS;\r
+  #else\r
+      return PCL_NOT_SUPPORTED;\r
+  #endif\r
+#endif\r
+}\r
+\r
+\r
+#if UC3L\r
+#else\r
+void pcl_write_gplp(unsigned long gplp, unsigned long value)\r
+{\r
+#ifndef AVR32_PM_VERSION_RESETVALUE\r
+// Implementation for UC3A, UC3A3, UC3B parts.\r
+  pm_write_gplp(&AVR32_PM,gplp,value);\r
+#else\r
+  scif_write_gplp(gplp,value);\r
+#endif\r
+}\r
+\r
+unsigned long pcl_read_gplp(unsigned long gplp)\r
+{\r
+#ifndef AVR32_PM_VERSION_RESETVALUE\r
+// Implementation for UC3A, UC3A3, UC3B parts.\r
+  return pm_read_gplp(&AVR32_PM,gplp);\r
+#else\r
+  return scif_read_gplp(gplp);\r
+#endif\r
+}\r
+#endif\r

diff --git a/Demo/AVR32_UC3A_GCC/Atmel_SW_Framework/DRIVERS/PM/power_clocks_lib.h b/Demo/AVR32_UC3A_GCC/Atmel_SW_Framework/DRIVERS/PM/power_clocks_lib.h
new file mode 100644 (file)
index 0000000..7661717
--- /dev/null
+++ b/Demo/AVR32_UC3A_GCC/Atmel_SW_Framework/DRIVERS/PM/power_clocks_lib.h
@@ -0,0 +1,379 @@
+/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */\r
+
+/*This file has been prepared for Doxygen automatic documentation generation.*/\r
+/*! \file *********************************************************************\r
+ *\r
+ * \brief High-level library abstracting features such as oscillators/pll/dfll\r
+ *        configuration, clock configuration, System-sensible parameters\r
+ *        configuration, buses clocks configuration, sleep mode, reset.\r
+ *\r
+ *\r
+ * - Compiler:           IAR EWAVR32 and GNU GCC for AVR32\r
+ * - Supported devices:  All AVR32 devices.\r
+ * - AppNote:\r
+ *\r
+ * \author               Atmel Corporation: http://www.atmel.com \n\r
+ *                       Support and FAQ: http://support.atmel.no/\r
+ *\r
+ *****************************************************************************/\r
+\r
+/* Copyright (c) 2009 Atmel Corporation. All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice, this\r
+ * list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an Atmel\r
+ * AVR product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\r
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\r
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\r
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE\r
+ *\r
+ */\r
+\r
+#ifndef _POWER_CLOCKS_LIB_H_\r
+#define _POWER_CLOCKS_LIB_H_\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+#include <avr32/io.h>\r
+#include "compiler.h"\r
+\r
+#ifndef AVR32_PM_VERSION_RESETVALUE\r
+// Support for UC3A, UC3A3, UC3B parts.\r
+  #include "pm.h"\r
+#else\r
+//! Device-specific data\r
+#if UC3L \r
+  #include "pm_uc3l.h"\r
+  #include "scif_uc3l.h"\r
+  #include "flashcdw.h"\r
+#elif UC3C\r
+  #include "pm_uc3c.h"\r
+  #include "scif_uc3c.h"\r
+  #include "flashc.h"\r
+#endif\r
+#endif\r
+\r
+/*! \name Clocks Management\r
+ */\r
+//! @{\r
+\r
+//! The different oscillators\r
+typedef enum\r
+{\r
+  PCL_OSC0  = 0,\r
+  PCL_OSC1  = 1\r
+} pcl_osc_t;\r
+\r
+//! The different DFLLs\r
+typedef enum\r
+{\r
+  PCL_DFLL0  = 0,\r
+  PCL_DFLL1  = 1\r
+} pcl_dfll_t;\r
+\r
+//! Possible Main Clock Sources\r
+typedef enum\r
+{\r
+  PCL_MC_RCSYS,      // Default main clock source, supported by all (aka Slow Clock)\r
+  PCL_MC_OSC0,       // Supported by all\r
+  PCL_MC_OSC1,       // Supported by UC3C only\r
+  PCL_MC_OSC0_PLL0,  // Supported by UC3A, UC3B, UC3A3, UC3C (the main clock source is PLL0 with OSC0 as reference)\r
+  PCL_MC_OSC1_PLL0,  // Supported by UC3A, UC3B, UC3A3, UC3C (the main clock source is PLL0 with OSC1 as reference)\r
+  PCL_MC_OSC0_PLL1,  // Supported by UC3C  (the main clock source is PLL1 with OSC0 as reference)\r
+  PCL_MC_OSC1_PLL1,  // Supported by UC3C  (the main clock source is PLL1 with OSC1 as reference)\r
+  PCL_MC_DFLL0,      // Supported by UC3L\r
+  PCL_MC_DFLL1,      // Not supported yet\r
+  PCL_MC_RC120M,     // Supported by UC3L, UC3C\r
+  PCL_MC_RC8M,       // Supported by UC3C\r
+  PCL_MC_CRIPOSC     // Supported by UC3C\r
+} pcl_mainclk_t;\r
+\r
+//! Input and output parameters to configure clocks with pcl_configure_clocks().\r
+// NOTE: regarding the frequency settings, always abide by the datasheet rules and min & max supported frequencies.\r
+#ifndef AVR32_PM_VERSION_RESETVALUE\r
+// Support for UC3A, UC3A3, UC3B parts.\r
+#define pcl_freq_param_t  pm_freq_param_t // See pm.h\r
+#else\r
+// Support for UC3C, UC3L parts.\r
+typedef struct\r
+{\r
+  //! Main clock source selection (input argument).\r
+  pcl_mainclk_t main_clk_src;\r
+\r
+  //! Target CPU frequency (input/output argument).\r
+  unsigned long cpu_f;\r
+\r
+  //! Target PBA frequency (input/output argument).\r
+  unsigned long pba_f;\r
+\r
+  //! Target PBB frequency (input/output argument).\r
+  unsigned long pbb_f;\r
+\r
+  //! Target PBC frequency (input/output argument).\r
+  unsigned long pbc_f;\r
+\r
+  //! Oscillator 0's external crystal(or external clock) frequency (board dependant) (input argument).\r
+  unsigned long osc0_f;\r
+\r
+  //! Oscillator 0's external crystal(or external clock) startup time: AVR32_PM_OSCCTRL0_STARTUP_x_RCOSC (input argument).\r
+  unsigned long osc0_startup;\r
+\r
+  //! DFLL target frequency (input/output argument) (NOTE: the bigger, the most stable the frequency)\r
+  unsigned long dfll_f;\r
+  \r
+  //! Other parameters that might be necessary depending on the device (implementation-dependent).\r
+  // For the UC3L DFLL setup, this parameter should be pointing to a structure of\r
+  // type (scif_gclk_opt_t *).\r
+  void *pextra_params;\r
+} pcl_freq_param_t;\r
+#endif\r
+\r
+//! Define "not supported" for the lib.\r
+#define PCL_NOT_SUPPORTED (-10000)\r
+\r
+/*! \brief Automatically configure the CPU, PBA, PBB, and HSB clocks\r
+ *\r
+ * This function needs some parameters stored in a pcl_freq_param_t structure:\r
+ *  - main_clk_src is the id of the main clock source to use,\r
+ *  - cpu_f and pba_f and pbb_f are the wanted frequencies,\r
+ *  - osc0_f is the oscillator 0's external crystal (or external clock) on-board frequency (e.g. FOSC0),\r
+ *  - osc0_startup is the oscillator 0's external crystal (or external clock) startup time (e.g. OSC0_STARTUP).\r
+ *  - dfll_f is the target DFLL frequency to set-up if main_clk_src is the dfll.\r
+ *\r
+ * The CPU, HSB and PBA frequencies programmed after configuration are stored back into cpu_f and pba_f.\r
+ *\r
+ * \note: since it is dynamically computing the appropriate field values of the\r
+ * configuration registers from the parameters structure, this function is not\r
+ * optimal in terms of code size. For a code size optimal solution, it is better\r
+ * to create a new function from pcl_configure_clocks() and modify it to use\r
+ * preprocessor computation from pre-defined target frequencies.\r
+ *\r
+ * \param param    pointer on the configuration structure.\r
+ *\r
+ * \retval 0   Success.\r
+ * \retval <0  The configuration cannot be performed.\r
+ */\r
+extern long int pcl_configure_clocks(pcl_freq_param_t *param);\r
+\r
+/*! \brief Automatically configure the CPU, PBA, PBB, and HSB clocks using the RCSYS osc as main source clock.\r
+ *\r
+ * This function needs some parameters stored in a pcl_freq_param_t structure:\r
+ *  - cpu_f and pba_f and pbb_f are the wanted frequencies\r
+ *\r
+ * Supported main clock sources: PCL_MC_RCSYS\r
+ *\r
+ * Supported synchronous clocks frequencies:\r
+ * 115200Hz, 57600Hz, 28800Hz, 14400Hz, 7200Hz, 3600Hz, 1800Hz, 900Hz, 450Hz.\r
+ *\r
+ * \note: by default, this implementation doesn't perform thorough checks on the\r
+ *        input parameters. To enable the checks, define AVR32SFW_INPUT_CHECK.\r
+ *\r
+ * \note: since it is dynamically computing the appropriate field values of the\r
+ * configuration registers from the parameters structure, this function is not\r
+ * optimal in terms of code size. For a code size optimal solution, it is better\r
+ * to create a new function from pcl_configure_clocks_rcsys() and modify it to use\r
+ * preprocessor computation from pre-defined target frequencies.\r
+ *\r
+ * \param param    pointer on the configuration structure.\r
+ *\r
+ * \retval 0   Success.\r
+ * \retval <0  The configuration cannot be performed.\r
+ */\r
+extern long int pcl_configure_clocks_rcsys(pcl_freq_param_t *param);\r
+\r
+/*! \brief Automatically configure the CPU, PBA, PBB, and HSB clocks using the RC120M osc as main source clock.\r
+ *\r
+ * This function needs some parameters stored in a pcl_freq_param_t structure:\r
+ *  - cpu_f and pba_f and pbb_f are the wanted frequencies\r
+ *\r
+ * Supported main clock sources: PCL_MC_RC120M\r
+ *\r
+ * Supported synchronous clocks frequencies:\r
+ * 30MHz, 15MHz, 7.5MHz, 3.75MHz, 1.875MHz, 937.5kHz, 468.75kHz.\r
+ *\r
+ * \note: by default, this implementation doesn't perform thorough checks on the\r
+ *        input parameters. To enable the checks, define AVR32SFW_INPUT_CHECK.\r
+ *\r
+ * \note: since it is dynamically computing the appropriate field values of the\r
+ * configuration registers from the parameters structure, this function is not\r
+ * optimal in terms of code size. For a code size optimal solution, it is better\r
+ * to create a new function from pcl_configure_clocks_rc120m() and modify it to\r
+ * use preprocessor computation from pre-defined target frequencies.\r
+ *\r
+ * \param param    pointer on the configuration structure.\r
+ *\r
+ * \retval 0   Success.\r
+ * \retval <0  The configuration cannot be performed.\r
+ */\r
+extern long int pcl_configure_clocks_rc120m(pcl_freq_param_t *param);\r
+\r
+/*! \brief Automatically configure the CPU, PBA, PBB, and HSB clocks using the OSC0 osc as main source clock\r
+ *\r
+ * This function needs some parameters stored in a pcl_freq_param_t structure:\r
+ *  - cpu_f and pba_f and pbb_f are the wanted frequencies,\r
+ *  - osc0_f is the oscillator 0's external crystal (or external clock) on-board frequency (e.g. FOSC0),\r
+ *  - osc0_startup is the oscillator 0's external crystal (or external clock) startup time (e.g. OSC0_STARTUP).\r
+ *\r
+ * Supported main clock sources: PCL_MC_OSC0\r
+ *\r
+ * Supported synchronous clocks frequencies:\r
+ * (these obviously depend on the OSC0 frequency; we'll take 16MHz as an example)\r
+ * 16MHz, 8MHz, 4MHz, 2MHz, 1MHz, 500kHz, 250kHz, 125kHz, 62.5kHz.\r
+ *\r
+ * \note: by default, this implementation doesn't perform thorough checks on the\r
+ *        input parameters. To enable the checks, define AVR32SFW_INPUT_CHECK.\r
+ *\r
+ * \note: since it is dynamically computing the appropriate field values of the\r
+ * configuration registers from the parameters structure, this function is not\r
+ * optimal in terms of code size. For a code size optimal solution, it is better\r
+ * to create a new function from pcl_configure_clocks_osc0() and modify it to use\r
+ * preprocessor computation from pre-defined target frequencies.\r
+ *\r
+ * \param param    pointer on the configuration structure.\r
+ *\r
+ * \retval 0   Success.\r
+ * \retval <0  The configuration cannot be performed.\r
+ */\r
+extern long int pcl_configure_clocks_osc0(pcl_freq_param_t *param);\r
+\r
+/*! \brief Automatically configure the CPU, PBA, PBB, and HSB clocks using the DFLL0 as main source clock\r
+ *\r
+ * This function needs some parameters stored in a pcl_freq_param_t structure:\r
+ *  - cpu_f and pba_f and pbb_f are the wanted frequencies,\r
+ *  - dfll_f is the target DFLL frequency to set-up\r
+ *\r
+ * \note: when the DFLL0 is to be used as main source clock for the synchronous clocks,\r
+ *  the target frequency of the DFLL should be chosen to be as high as possible\r
+ *  within the specification range (for stability reasons); the target cpu and pbx\r
+ *  frequencies will then be reached by appropriate division ratio.\r
+ *\r
+ * Supported main clock sources: PCL_MC_DFLL0\r
+ *\r
+ * Supported synchronous clocks frequencies:\r
+ * (these obviously depend on the DFLL target frequency; we'll take 100MHz as an example)\r
+ * 50MHz, 25MHz, 12.5MHz, 6.25MHz, 3.125MHz, 1562.5kHz, 781.25kHz, 390.625kHz.\r
+ *\r
+ * \note: by default, this implementation doesn't perform thorough checks on the\r
+ *        input parameters. To enable the checks, define AVR32SFW_INPUT_CHECK.\r
+ *\r
+ * \note: since it is dynamically computing the appropriate field values of the\r
+ * configuration registers from the parameters structure, this function is not\r
+ * optimal in terms of code size. For a code size optimal solution, it is better\r
+ * to create a new function from pcl_configure_clocks_dfll0() and modify it to\r
+ * use preprocessor computation from pre-defined target frequencies.\r
+ *\r
+ * \param param    pointer on the configuration structure.\r
+ *\r
+ * \retval 0   Success.\r
+ * \retval <0  The configuration cannot be performed.\r
+ */\r
+extern long int pcl_configure_clocks_dfll0(pcl_freq_param_t *param);\r
+\r
+/*! \brief Switch the main clock source to Osc0 configured in crystal mode\r
+ *\r
+ * \param osc The oscillator to enable and switch to.\r
+ * \param fcrystal Oscillator external crystal frequency (Hz)\r
+ * \param startup Oscillator startup time.\r
+ *\r
+ * \return Status.\r
+ *   \retval 0  Success.\r
+ *   \retval <0 An error occured.\r
+ */\r
+extern long int pcl_switch_to_osc(pcl_osc_t osc, unsigned int fcrystal, unsigned int startup);\r
+\r
+/*! \brief Enable the clock of a module.\r
+ *\r
+ * \param module The module to clock (use one of the defines in the part-specific\r
+ * header file under "toolchain folder"/avr32/inc(lude)/avr32/; depending on the\r
+ * clock domain, look for the sections "CPU clocks", "HSB clocks", "PBx clocks"\r
+ * or look in the module section).\r
+ *\r
+ * \return Status.\r
+ *   \retval 0  Success.\r
+ *   \retval <0 An error occured.\r
+ */\r
+#ifndef AVR32_PM_VERSION_RESETVALUE\r
+// Implementation for UC3A, UC3A3, UC3B parts.\r
+#define pcl_enable_module(module) pm_enable_module(&AVR32_PM, module)\r
+#else\r
+// Implementation for UC3C, UC3L parts.\r
+#define pcl_enable_module(module) pm_enable_module(module)\r
+#endif\r
+\r
+/*! \brief Disable the clock of a module.\r
+ *\r
+ * \param module The module to shut down (use one of the defines in the part-specific\r
+ * header file under "toolchain folder"/avr32/inc(lude)/avr32/; depending on the\r
+ * clock domain, look for the sections "CPU clocks", "HSB clocks", "PBx clocks"\r
+ * or look in the module section).\r
+ *\r
+ * \return Status.\r
+ *   \retval 0  Success.\r
+ *   \retval <0 An error occured.\r
+ */\r
+#ifndef AVR32_PM_VERSION_RESETVALUE\r
+// Implementation for UC3A, UC3A3, UC3B parts.\r
+#define pcl_disable_module(module)  pm_disable_module(&AVR32_PM, module)\r
+#else\r
+// Implementation for UC3C, UC3L parts.\r
+#define pcl_disable_module(module)  pm_disable_module(module)\r
+#endif\r
+\r
+/*! \brief Configure the USB Clock\r
+ *\r
+ *\r
+ * \return Status.\r
+ *   \retval 0  Success.\r
+ *   \retval <0 An error occured.\r
+ */\r
+extern long int pcl_configure_usb_clock(void);\r
+\r
+//! @}\r
+\r
+/*! \name Power Management\r
+ */\r
+//! @{\r
+/*!\r
+ * \brief Read the content of the GPLP registers\r
+ * \param gplp GPLP register index (0,1,... depending on the number of GPLP registers for a given part)\r
+ *\r
+ * \return The content of the chosen GPLP register.\r
+ */\r
+extern unsigned long pcl_read_gplp(unsigned long gplp);\r
+\r
+\r
+/*!\r
+ * \brief Write into the GPLP registers\r
+ * \param gplp GPLP register index (0,1,... depending on the number of GPLP registers for a given part)\r
+ * \param value Value to write\r
+ */\r
+extern void pcl_write_gplp(unsigned long gplp, unsigned long value);\r
+\r
+//! @}\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif  // _POWER_CLOCKS_LIB_H_\r

diff --git a/Demo/AVR32_UC3A_GCC/Atmel_SW_Framework/DRIVERS/PM/readme.html b/Demo/AVR32_UC3A_GCC/Atmel_SW_Framework/DRIVERS/PM/readme.html
new file mode 100644 (file)
index 0000000..3e49c66
--- /dev/null
+++ b/Demo/AVR32_UC3A_GCC/Atmel_SW_Framework/DRIVERS/PM/readme.html
@@ -0,0 +1,108 @@
+<!doctype HTML public "-//W3C//DTD HTML 4.0 Frameset//EN">
+<html>
+   <head>
+      <link rel="stylesheet" type="text/css" href="../../.docsrc/AVR32_ns.css">
+   </head>
+   <body>
+   <div id="wrapper">
+<p align="left" class="whs2"><a href="../DRIVERS_Readme.html"<font color="red"></font>Back to DRIVERS page</a></p>
+<h1 align="center" class="whs1">AVR UC3 Series Software Framework: Power Manager Driver<br>
+</h1>
+
+<p align="center" class="whs2">Copyright &copy; 2007 Atmel Corporation</p>
+
+<h2>Introduction</h2>
+<h3>UC3A0/1, UC3B, UC3A3</h3>
+    <p>The Power Manager (PM) controls the oscillators and PLLs, and generates the clocks and
+resets in the device. The PM controls two fast crystal oscillators, as well as two PLLs, which can
+multiply the clock from either oscillator to provide higher frequencies. Additionally, a low-power
+32 KHz oscillator is used to generate the real-time counter clock for high accuracy real-time
+measurements. The PM also contains a low-power RC oscillator with fast start-up time, which
+can be used to clock the digital logic.</p>
+
+<h3> UC3L, UC3C </h3>
+    <p>The Power Manager (PM) provides synchronous clocks used to clock the main digital logic in the
+device, namely the CPU, and the modules and peripherals connected to the HSB and PBx buses. The PM also
+contains advanced power-saving features and a Reset Controller.</p>
+
+
+<p>&nbsp;</p>
+
+<h2>Power Manager Driver</h2>
+<h3>UC3A0/1, UC3B, UC3A3</h3>
+    <p>The driver is composed of <a href="pm.c">pm.c</a> and <a href="pm.h">pm.h</a>.</p>
+    <p>&nbsp;</p>
+    <p>This driver provides interfaces for PM main hardware features:
+
+       <li>oscillator source setup: external or crystal;
+       <li>oscillator startup;
+       <li>PLL setup;
+       <li>main clock source setup.
+    </p>
+    <p>&nbsp;</p>
+    <p>Two examples are available:<p>
+       <a href=" EXAMPLE1/readme.html">EXAMPLE1:</a> how to configure the Power Manager to use Oscillator 0 as source of main clock, generic clock configuration and switch to a sleep mode<p>
+       <a href=" EXAMPLE2/readme.html">EXAMPLE2:</a> how to configure a PLL and switch the main clock to PLL output and do a generic clock configuration.</p>
+<p>&nbsp;</p>
+
+<p>
+  The file <a href="pm_conf_clocks.c">pm_conf_clocks.c</a> provides functions to simplify the usage of this driver.
+  It is used to configure all clocks at once by specifying frequencies needed.
+</p>
+
+<p>
+  The file <a href="power_clocks_lib.c">power_clocks_lib.c</a> (and <a href="power_clocks_lib.h">power_clocks_lib.h</a>)
+  provides functions to abstract features such as oscillators/pll/dfll configuration, clock configuration, System-sensible
+  parameters configuration, buses clocks configuration, sleep mode, reset.
+</p>
+<p></p>
+
+<h3>UC3L</h3>
+    <p>The driver is composed of <a href="pm_uc3l.c">pm_uc3l.c</a> and <a href="pm_uc3l.h">pm_uc3l.h</a>.</p>
+    <p>&nbsp;</p>
+    <p>This driver provides interfaces for PM main hardware features:
+       <li>main clock source setup,
+       <li>clock domains setup,
+       <li>peripheral modules setup,
+       <li>Sleep modes setup,
+       <li>reset,
+       <li>PM interrupts setup.
+    </p>
+    <p>&nbsp;</p>
+    <p>Three examples are available:<p>
+       <a href=" EXAMPLE1/readme.html">EXAMPLE1:</a> how to configure the Power Manager to use Oscillator 0 as source of main clock, generic clock configuration and switch to a sleep mode. This example is not applicable to the AT32UC3L-EK board because no external crystal/clock is connected to OSC0 on that board.<p>
+       <a href=" EXAMPLE2/readme.html">EXAMPLE2:</a> how to configure a DFLL and switch the main clock to the DFLL output and do a generic clock configuration.</p>
+       <a href=" EXAMPLE3/readme.html">EXAMPLE2:</a> how to use the RC120M internal oscillator as main clock source and do a Generic clock configuration.</p>
+<p>&nbsp;</p>
+
+<h3>UC3C</h3>
+    <p>The driver is composed of <a href="pm_uc3c.c">pm_uc3c.c</a> and <a href="pm_uc3c.h">pm_uc3c.h</a>.</p>
+    <p>&nbsp;</p>
+    <p>This driver provides interfaces for PM main hardware features:
+       <li>main clock source setup,
+       <li>clock domains setup,
+       <li>peripheral modules setup,
+       <li>Sleep modes setup,
+       <li>reset,
+       <li>PM interrupts setup.
+    </p>
+    <p>&nbsp;</p>
+    <p>Two examples are available:<p>
+       <a href=" EXAMPLE1/readme.html">EXAMPLE1:</a> how to configure the Power Manager to use Oscillator 0 as source of main clock, generic clock configuration and switch to a sleep mode<p>
+       <a href=" EXAMPLE2/readme.html">EXAMPLE2:</a> how to configure a PLL and switch the main clock to PLL output and do a generic clock configuration.</p>
+<p>&nbsp;</p>
+
+<p>
+  The file <a href="power_clocks_lib.c">power_clocks_lib.c</a> (and <a href="power_clocks_lib.h">power_clocks_lib.h</a>)
+  provides functions to abstract features such as oscillators/pll/dfll configuration, clock configuration, System-sensible
+  parameters configuration, buses clocks configuration, sleep mode, reset.
+</p>
+
+
+<hr align="center" width="50%" class="whs4">
+
+    <p class=legalfooter>AVR is a registered trademark of
+    Atmel Corporation.</p>
+</div>
+   </body>
+</html>

diff --git a/Demo/AVR32_UC3A_GCC/Atmel_SW_Framework/DRIVERS/USART/readme.html b/Demo/AVR32_UC3A_GCC/Atmel_SW_Framework/DRIVERS/USART/readme.html
new file mode 100644 (file)
index 0000000..e9a2bdb
--- /dev/null
+++ b/Demo/AVR32_UC3A_GCC/Atmel_SW_Framework/DRIVERS/USART/readme.html
@@ -0,0 +1,40 @@
+<!-- UC3_START -->
+<!doctype HTML public "-//W3C//DTD HTML 4.0 Frameset//EN">
+<html>
+   <head>
+      <link rel="stylesheet" type="text/css" href="../../.docsrc/AVR32_ns.css">
+   </head>
+      <div id="wrapper">
+   <body>
+<p align="left" class="whs2"><a href="../DRIVERS_Readme.html"<font color="red"></font>Back to DRIVERS page</a></p>   
+<h1 align="center" class="whs1">AVR UC3 Series Software Framework: USART Driver<br>
+</h1>
+
+<p align="center" class="whs2">Copyright &copy; 2007 Atmel Corporation</p>
+
+<h2>Introduction</h2>
+    <p>This driver will let you communicate through serial ports of all AVR&reg;32 AT32UC3 devices.</p>
+<p>&nbsp;</p>
+
+The USART driver philosophy of usage is:
+<li> Configure one (or several) USART in the wanted mode [usart_init_xxxxx]</li>
+<li> Send or receive data on the configured USART, [usart_putchar, usart_getchar, usart_write_line, ...]</li>
+
+<h2>USART Driver</h2>
+    <p>The driver is composed of <a href="usart.c">usart.c</a> and <a href="usart.h">usart.h</a>.</p>
+    </p>
+
+<p>&nbsp;</p>
+    <p>One example is currently available: </p>
+    <p><li><a href="./USART_EXAMPLE/readme.html">Simple access to a serial port</a></li></p>
+<p>&nbsp;</p>
+
+
+<hr align="center" width="50%" class="whs4">
+
+    <p class=legalfooter>AVR is a registered trademark of
+    Atmel Corporation.</p>
+   </div>
+   </body>
+</html>
+<!-- UC3_END -->

diff --git a/Demo/AVR32_UC3A_GCC/Atmel_SW_Framework/DRIVERS/USART/usart.c b/Demo/AVR32_UC3A_GCC/Atmel_SW_Framework/DRIVERS/USART/usart.c
new file mode 100644 (file)
index 0000000..bfdc977
--- /dev/null
+++ b/Demo/AVR32_UC3A_GCC/Atmel_SW_Framework/DRIVERS/USART/usart.c
@@ -0,0 +1,914 @@
+/* This source file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */\r
+
+/*This file is prepared for Doxygen automatic documentation generation.*/\r
+/*! \file *********************************************************************\r
+ *\r
+ * \brief USART driver for AVR32 UC3.\r
+ *\r
+ * This file contains basic functions for the AVR32 USART, with support for all\r
+ * modes, settings and clock speeds.\r
+ *\r
+ * - Compiler:           IAR EWAVR32 and GNU GCC for AVR32\r
+ * - Supported devices:  All AVR32 devices with a USART module can be used.\r
+ * - AppNote:\r
+ *\r
+ * \author               Atmel Corporation: http://www.atmel.com \n\r
+ *                       Support and FAQ: http://support.atmel.no/\r
+ *\r
+ ******************************************************************************/\r
+\r
+/* Copyright (c) 2009 Atmel Corporation. All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice, this\r
+ * list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an Atmel\r
+ * AVR product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\r
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\r
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\r
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE\r
+ *\r
+ */\r
+\r
+#include "compiler.h"\r
+#include "usart.h"\r
+\r
+\r
+//------------------------------------------------------------------------------\r
+/*! \name Private Functions\r
+ */\r
+//! @{\r
+\r
+\r
+/*! \brief Checks if the USART is in multidrop mode.\r
+ *\r
+ * \param usart Base address of the USART instance.\r
+ *\r
+ * \return \c 1 if the USART is in multidrop mode, otherwise \c 0.\r
+ */\r
+#if (defined __GNUC__)\r
+__attribute__((__always_inline__))\r
+#endif\r
+static __inline__ int usart_mode_is_multidrop(volatile avr32_usart_t *usart)\r
+{\r
+  return ((usart->mr >> AVR32_USART_MR_PAR_OFFSET) & AVR32_USART_MR_PAR_MULTI) == AVR32_USART_MR_PAR_MULTI;\r
+}\r
+\r
+\r
+/*! \brief Calculates a clock divider (\e CD) and a fractional part (\e FP) for\r
+ *         the USART asynchronous modes to generate a baud rate as close as\r
+ *         possible to the baud rate set point.\r
+ *\r
+ * Baud rate calculation:\r
+ * \f$ Baudrate = \frac{SelectedClock}{Over \times (CD + \frac{FP}{8})} \f$, \e Over being 16 or 8.\r
+ * The maximal oversampling is selected if it allows to generate a baud rate close to the set point.\r
+ *\r
+ * \param usart     Base address of the USART instance.\r
+ * \param baudrate  Baud rate set point.\r
+ * \param pba_hz    USART module input clock frequency (PBA clock, Hz).\r
+ *\r
+ * \retval USART_SUCCESS        Baud rate successfully initialized.\r
+ * \retval USART_INVALID_INPUT  Baud rate set point is out of range for the given input clock frequency.\r
+ */\r
+static int usart_set_async_baudrate(volatile avr32_usart_t *usart, unsigned int baudrate, unsigned long pba_hz)\r
+{\r
+  unsigned int over = (pba_hz >= 16 * baudrate) ? 16 : 8;\r
+  unsigned int cd_fp = ((1 << AVR32_USART_BRGR_FP_SIZE) * pba_hz + (over * baudrate) / 2) / (over * baudrate);\r
+  unsigned int cd = cd_fp >> AVR32_USART_BRGR_FP_SIZE;\r
+  unsigned int fp = cd_fp & ((1 << AVR32_USART_BRGR_FP_SIZE) - 1);\r
+\r
+  if (cd < 1 || cd > (1 << AVR32_USART_BRGR_CD_SIZE) - 1)\r
+    return USART_INVALID_INPUT;\r
+\r
+  usart->mr = (usart->mr & ~(AVR32_USART_MR_USCLKS_MASK |\r
+                             AVR32_USART_MR_SYNC_MASK |\r
+                             AVR32_USART_MR_OVER_MASK)) |\r
+              AVR32_USART_MR_USCLKS_MCK << AVR32_USART_MR_USCLKS_OFFSET |\r
+              ((over == 16) ? AVR32_USART_MR_OVER_X16 : AVR32_USART_MR_OVER_X8) << AVR32_USART_MR_OVER_OFFSET;\r
+\r
+  usart->brgr = cd << AVR32_USART_BRGR_CD_OFFSET |\r
+                fp << AVR32_USART_BRGR_FP_OFFSET;\r
+\r
+  return USART_SUCCESS;\r
+}\r
+\r
+\r
+/*! \brief Calculates a clock divider (\e CD) for the USART synchronous master\r
+ *         modes to generate a baud rate as close as possible to the baud rate\r
+ *         set point.\r
+ *\r
+ * Baud rate calculation:\r
+ * \f$ Baudrate = \frac{SelectedClock}{CD} \f$.\r
+ *\r
+ * \param usart     Base address of the USART instance.\r
+ * \param baudrate  Baud rate set point.\r
+ * \param pba_hz    USART module input clock frequency (PBA clock, Hz).\r
+ *\r
+ * \retval USART_SUCCESS        Baud rate successfully initialized.\r
+ * \retval USART_INVALID_INPUT  Baud rate set point is out of range for the given input clock frequency.\r
+ */\r
+static int usart_set_sync_master_baudrate(volatile avr32_usart_t *usart, unsigned int baudrate, unsigned long pba_hz)\r
+{\r
+  unsigned int cd = (pba_hz + baudrate / 2) / baudrate;\r
+\r
+  if (cd < 1 || cd > (1 << AVR32_USART_BRGR_CD_SIZE) - 1)\r
+    return USART_INVALID_INPUT;\r
+\r
+  usart->mr = (usart->mr & ~AVR32_USART_MR_USCLKS_MASK) |\r
+              AVR32_USART_MR_USCLKS_MCK << AVR32_USART_MR_USCLKS_OFFSET |\r
+              AVR32_USART_MR_SYNC_MASK;\r
+\r
+  usart->brgr = cd << AVR32_USART_BRGR_CD_OFFSET;\r
+\r
+  return USART_SUCCESS;\r
+}\r
+\r
+\r
+/*! \brief Selects the SCK pin as the source of baud rate for the USART\r
+ *         synchronous slave modes.\r
+ *\r
+ * \param usart Base address of the USART instance.\r
+ *\r
+ * \retval USART_SUCCESS  Baud rate successfully initialized.\r
+ */\r
+static int usart_set_sync_slave_baudrate(volatile avr32_usart_t *usart)\r
+{\r
+  usart->mr = (usart->mr & ~AVR32_USART_MR_USCLKS_MASK) |\r
+              AVR32_USART_MR_USCLKS_SCK << AVR32_USART_MR_USCLKS_OFFSET |\r
+              AVR32_USART_MR_SYNC_MASK;\r
+\r
+  return USART_SUCCESS;\r
+}\r
+\r
+\r
+/*! \brief Calculates a clock divider (\e CD) for the USART ISO7816 mode to\r
+ *         generate an ISO7816 clock as close as possible to the clock set point.\r
+ *\r
+ * ISO7816 clock calculation:\r
+ * \f$ Clock = \frac{SelectedClock}{CD} \f$.\r
+ *\r
+ * \param usart   Base address of the USART instance.\r
+ * \param clock   ISO7816 clock set point.\r
+ * \param pba_hz  USART module input clock frequency (PBA clock, Hz).\r
+ *\r
+ * \retval USART_SUCCESS        ISO7816 clock successfully initialized.\r
+ * \retval USART_INVALID_INPUT  ISO7816 clock set point is out of range for the given input clock frequency.\r
+ */\r
+static int usart_set_iso7816_clock(volatile avr32_usart_t *usart, unsigned int clock, unsigned long pba_hz)\r
+{\r
+  unsigned int cd = (pba_hz + clock / 2) / clock;\r
+\r
+  if (cd < 1 || cd > (1 << AVR32_USART_BRGR_CD_SIZE) - 1)\r
+    return USART_INVALID_INPUT;\r
+\r
+  usart->mr = (usart->mr & ~(AVR32_USART_MR_USCLKS_MASK |\r
+                             AVR32_USART_MR_SYNC_MASK |\r
+                             AVR32_USART_MR_OVER_MASK)) |\r
+              AVR32_USART_MR_USCLKS_MCK << AVR32_USART_MR_USCLKS_OFFSET |\r
+              AVR32_USART_MR_OVER_X16 << AVR32_USART_MR_OVER_OFFSET;\r
+\r
+  usart->brgr = cd << AVR32_USART_BRGR_CD_OFFSET;\r
+\r
+  return USART_SUCCESS;\r
+}\r
+\r
+\r
+#if defined(AVR32_USART_400_H_INCLUDED) || \\r
+    defined(AVR32_USART_410_H_INCLUDED) || \\r
+    defined(AVR32_USART_420_H_INCLUDED) || \\r
+    defined(AVR32_USART_440_H_INCLUDED) || \\r
+    defined(AVR32_USART_602_H_INCLUDED)\r
+\r
+\r
+/*! \brief Calculates a clock divider (\e CD) for the USART SPI master mode to\r
+ *         generate a baud rate as close as possible to the baud rate set point.\r
+ *\r
+ * Baud rate calculation:\r
+ * \f$ Baudrate = \frac{SelectedClock}{CD} \f$.\r
+ *\r
+ * \param usart     Base address of the USART instance.\r
+ * \param baudrate  Baud rate set point.\r
+ * \param pba_hz    USART module input clock frequency (PBA clock, Hz).\r
+ *\r
+ * \retval USART_SUCCESS        Baud rate successfully initialized.\r
+ * \retval USART_INVALID_INPUT  Baud rate set point is out of range for the given input clock frequency.\r
+ */\r
+static int usart_set_spi_master_baudrate(volatile avr32_usart_t *usart, unsigned int baudrate, unsigned long pba_hz)\r
+{\r
+  unsigned int cd = (pba_hz + baudrate / 2) / baudrate;\r
+\r
+  if (cd < 4 || cd > (1 << AVR32_USART_BRGR_CD_SIZE) - 1)\r
+    return USART_INVALID_INPUT;\r
+\r
+  usart->mr = (usart->mr & ~AVR32_USART_MR_USCLKS_MASK) |\r
+              AVR32_USART_MR_USCLKS_MCK << AVR32_USART_MR_USCLKS_OFFSET;\r
+\r
+  usart->brgr = cd << AVR32_USART_BRGR_CD_OFFSET;\r
+\r
+  return USART_SUCCESS;\r
+}\r
+\r
+\r
+/*! \brief Selects the SCK pin as the source of baud rate for the USART SPI\r
+ *         slave mode.\r
+ *\r
+ * \param usart Base address of the USART instance.\r
+ *\r
+ * \retval USART_SUCCESS  Baud rate successfully initialized.\r
+ */\r
+static int usart_set_spi_slave_baudrate(volatile avr32_usart_t *usart)\r
+{\r
+  usart->mr = (usart->mr & ~AVR32_USART_MR_USCLKS_MASK) |\r
+              AVR32_USART_MR_USCLKS_SCK << AVR32_USART_MR_USCLKS_OFFSET;\r
+\r
+  return USART_SUCCESS;\r
+}\r
+\r
+\r
+#endif  // USART rev. >= 4.0.0\r
+\r
+\r
+//! @}\r
+\r
+\r
+//------------------------------------------------------------------------------\r
+/*! \name Initialization Functions\r
+ */\r
+//! @{\r
+\r
+\r
+void usart_reset(volatile avr32_usart_t *usart)\r
+{\r
+  Bool global_interrupt_enabled = Is_global_interrupt_enabled();\r
+\r
+  // Disable all USART interrupts.\r
+  // Interrupts needed should be set explicitly on every reset.\r
+  if (global_interrupt_enabled) Disable_global_interrupt();\r
+  usart->idr = 0xFFFFFFFF;\r
+  usart->csr;\r
+  if (global_interrupt_enabled) Enable_global_interrupt();\r
+\r
+  // Reset mode and other registers that could cause unpredictable behavior after reset.\r
+  usart->mr = 0;\r
+  usart->rtor = 0;\r
+  usart->ttgr = 0;\r
+\r
+  // Shutdown TX and RX (will be re-enabled when setup has successfully completed),\r
+  // reset status bits and turn off DTR and RTS.\r
+  usart->cr = AVR32_USART_CR_RSTRX_MASK   |\r
+              AVR32_USART_CR_RSTTX_MASK   |\r
+              AVR32_USART_CR_RSTSTA_MASK  |\r
+              AVR32_USART_CR_RSTIT_MASK   |\r
+              AVR32_USART_CR_RSTNACK_MASK |\r
+#ifndef AVR32_USART_440_H_INCLUDED\r
+// Note: Modem Signal Management DTR-DSR-DCD-RI are not included in USART rev.440.\r
+              AVR32_USART_CR_DTRDIS_MASK  |\r
+#endif\r
+              AVR32_USART_CR_RTSDIS_MASK;\r
+}\r
+\r
+\r
+int usart_init_rs232(volatile avr32_usart_t *usart, const usart_options_t *opt, long pba_hz)\r
+{\r
+  // Reset the USART and shutdown TX and RX.\r
+  usart_reset(usart);\r
+\r
+  // Check input values.\r
+  if (!opt || // Null pointer.\r
+      opt->charlength < 5 || opt->charlength > 9 ||\r
+      opt->paritytype > 7 ||\r
+      opt->stopbits > 2 + 255 ||\r
+      opt->channelmode > 3 ||\r
+      usart_set_async_baudrate(usart, opt->baudrate, pba_hz) == USART_INVALID_INPUT)\r
+    return USART_INVALID_INPUT;\r
+\r
+  if (opt->charlength == 9)\r
+  {\r
+    // Character length set to 9 bits. MODE9 dominates CHRL.\r
+    usart->mr |= AVR32_USART_MR_MODE9_MASK;\r
+  }\r
+  else\r
+  {\r
+    // CHRL gives the character length (- 5) when MODE9 = 0.\r
+    usart->mr |= (opt->charlength - 5) << AVR32_USART_MR_CHRL_OFFSET;\r
+  }\r
+\r
+  usart->mr |= opt->paritytype << AVR32_USART_MR_PAR_OFFSET |\r
+               opt->channelmode << AVR32_USART_MR_CHMODE_OFFSET;\r
+\r
+  if (opt->stopbits > USART_2_STOPBITS)\r
+  {\r
+    // Set two stop bits\r
+    usart->mr |= AVR32_USART_MR_NBSTOP_2 << AVR32_USART_MR_NBSTOP_OFFSET;\r
+    // and a timeguard period gives the rest.\r
+    usart->ttgr = opt->stopbits - USART_2_STOPBITS;\r
+  }\r
+  else\r
+    // Insert 1, 1.5 or 2 stop bits.\r
+    usart->mr |= opt->stopbits << AVR32_USART_MR_NBSTOP_OFFSET;\r
+\r
+  // Set normal mode.\r
+  usart->mr = (usart->mr & ~AVR32_USART_MR_MODE_MASK) |\r
+              AVR32_USART_MR_MODE_NORMAL << AVR32_USART_MR_MODE_OFFSET;\r
+\r
+  // Setup complete; enable communication.\r
+  // Enable input and output.\r
+  usart->cr = AVR32_USART_CR_RXEN_MASK |\r
+              AVR32_USART_CR_TXEN_MASK;\r
+\r
+  return USART_SUCCESS;\r
+}\r
+\r
+\r
+int usart_init_rs232_tx_only(volatile avr32_usart_t *usart, const usart_options_t *opt, long pba_hz)\r
+{\r
+  // Reset the USART and shutdown TX and RX.\r
+  usart_reset(usart);\r
+\r
+  // Check input values.\r
+  if (!opt || // Null pointer.\r
+      opt->charlength < 5 || opt->charlength > 9 ||\r
+      opt->paritytype > 7 ||\r
+      opt->stopbits == 1 || opt->stopbits > 2 + 255 ||\r
+      opt->channelmode > 3 ||\r
+      usart_set_sync_master_baudrate(usart, opt->baudrate, pba_hz) == USART_INVALID_INPUT)\r
+    return USART_INVALID_INPUT;\r
+\r
+  if (opt->charlength == 9)\r
+  {\r
+    // Character length set to 9 bits. MODE9 dominates CHRL.\r
+    usart->mr |= AVR32_USART_MR_MODE9_MASK;\r
+  }\r
+  else\r
+  {\r
+    // CHRL gives the character length (- 5) when MODE9 = 0.\r
+    usart->mr |= (opt->charlength - 5) << AVR32_USART_MR_CHRL_OFFSET;\r
+  }\r
+\r
+  usart->mr |= opt->paritytype << AVR32_USART_MR_PAR_OFFSET |\r
+               opt->channelmode << AVR32_USART_MR_CHMODE_OFFSET;\r
+\r
+  if (opt->stopbits > USART_2_STOPBITS)\r
+  {\r
+    // Set two stop bits\r
+    usart->mr |= AVR32_USART_MR_NBSTOP_2 << AVR32_USART_MR_NBSTOP_OFFSET;\r
+    // and a timeguard period gives the rest.\r
+    usart->ttgr = opt->stopbits - USART_2_STOPBITS;\r
+  }\r
+  else\r
+    // Insert 1 or 2 stop bits.\r
+    usart->mr |= opt->stopbits << AVR32_USART_MR_NBSTOP_OFFSET;\r
+\r
+  // Set normal mode.\r
+  usart->mr = (usart->mr & ~AVR32_USART_MR_MODE_MASK) |\r
+              AVR32_USART_MR_MODE_NORMAL << AVR32_USART_MR_MODE_OFFSET;\r
+\r
+  // Setup complete; enable communication.\r
+  // Enable only output as input is not possible in synchronous mode without\r
+  // transferring clock.\r
+  usart->cr = AVR32_USART_CR_TXEN_MASK;\r
+\r
+  return USART_SUCCESS;\r
+}\r
+\r
+\r
+int usart_init_hw_handshaking(volatile avr32_usart_t *usart, const usart_options_t *opt, long pba_hz)\r
+{\r
+  // First: Setup standard RS232.\r
+  if (usart_init_rs232(usart, opt, pba_hz) == USART_INVALID_INPUT)\r
+    return USART_INVALID_INPUT;\r
+\r
+  // Set hardware handshaking mode.\r
+  usart->mr = (usart->mr & ~AVR32_USART_MR_MODE_MASK) |\r
+              AVR32_USART_MR_MODE_HARDWARE << AVR32_USART_MR_MODE_OFFSET;\r
+\r
+  return USART_SUCCESS;\r
+}\r
+\r
+\r
+int usart_init_modem(volatile avr32_usart_t *usart, const usart_options_t *opt, long pba_hz)\r
+{\r
+  // First: Setup standard RS232.\r
+  if (usart_init_rs232(usart, opt, pba_hz) == USART_INVALID_INPUT)\r
+    return USART_INVALID_INPUT;\r
+\r
+  // Set modem mode.\r
+  usart->mr = (usart->mr & ~AVR32_USART_MR_MODE_MASK) |\r
+              AVR32_USART_MR_MODE_MODEM << AVR32_USART_MR_MODE_OFFSET;\r
+\r
+  return USART_SUCCESS;\r
+}\r
+\r
+\r
+int usart_init_sync_master(volatile avr32_usart_t *usart, const usart_options_t *opt, long pba_hz)\r
+{\r
+  // Reset the USART and shutdown TX and RX.\r
+  usart_reset(usart);\r
+\r
+  // Check input values.\r
+  if (!opt || // Null pointer.\r
+      opt->charlength < 5 || opt->charlength > 9 ||\r
+      opt->paritytype > 7 ||\r
+      opt->stopbits == 1 || opt->stopbits > 2 + 255 ||\r
+      opt->channelmode > 3 ||\r
+      usart_set_sync_master_baudrate(usart, opt->baudrate, pba_hz) == USART_INVALID_INPUT)\r
+    return USART_INVALID_INPUT;\r
+\r
+  if (opt->charlength == 9)\r
+  {\r
+    // Character length set to 9 bits. MODE9 dominates CHRL.\r
+    usart->mr |= AVR32_USART_MR_MODE9_MASK;\r
+  }\r
+  else\r
+  {\r
+    // CHRL gives the character length (- 5) when MODE9 = 0.\r
+    usart->mr |= (opt->charlength - 5) << AVR32_USART_MR_CHRL_OFFSET;\r
+  }\r
+\r
+  usart->mr |= opt->paritytype << AVR32_USART_MR_PAR_OFFSET |\r
+               opt->channelmode << AVR32_USART_MR_CHMODE_OFFSET;\r
+\r
+  if (opt->stopbits > USART_2_STOPBITS)\r
+  {\r
+    // Set two stop bits\r
+    usart->mr |= AVR32_USART_MR_NBSTOP_2 << AVR32_USART_MR_NBSTOP_OFFSET;\r
+    // and a timeguard period gives the rest.\r
+    usart->ttgr = opt->stopbits - USART_2_STOPBITS;\r
+  }\r
+  else\r
+    // Insert 1 or 2 stop bits.\r
+    usart->mr |= opt->stopbits << AVR32_USART_MR_NBSTOP_OFFSET;\r
+\r
+  // Set normal mode.\r
+  usart->mr = (usart->mr & ~AVR32_USART_MR_MODE_MASK) |\r
+              AVR32_USART_MR_MODE_NORMAL << AVR32_USART_MR_MODE_OFFSET |\r
+              AVR32_USART_MR_CLKO_MASK;\r
+\r
+  // Setup complete; enable communication.\r
+  // Enable input and output.\r
+  usart->cr = AVR32_USART_CR_RXEN_MASK |\r
+              AVR32_USART_CR_TXEN_MASK;\r
+\r
+  return USART_SUCCESS;\r
+}\r
+\r
+\r
+int usart_init_sync_slave(volatile avr32_usart_t *usart, const usart_options_t *opt, long pba_hz)\r
+{\r
+  // Reset the USART and shutdown TX and RX.\r
+  usart_reset(usart);\r
+\r
+  // Check input values.\r
+  if (!opt || // Null pointer.\r
+      opt->charlength < 5 || opt->charlength > 9 ||\r
+      opt->paritytype > 7 ||\r
+      opt->stopbits == 1 || opt->stopbits > 2 + 255 ||\r
+      opt->channelmode > 3 ||\r
+      usart_set_sync_slave_baudrate(usart) == USART_INVALID_INPUT)\r
+    return USART_INVALID_INPUT;\r
+\r
+  if (opt->charlength == 9)\r
+  {\r
+    // Character length set to 9 bits. MODE9 dominates CHRL.\r
+    usart->mr |= AVR32_USART_MR_MODE9_MASK;\r
+  }\r
+  else\r
+  {\r
+    // CHRL gives the character length (- 5) when MODE9 = 0.\r
+    usart->mr |= (opt->charlength - 5) << AVR32_USART_MR_CHRL_OFFSET;\r
+  }\r
+\r
+  usart->mr |= opt->paritytype << AVR32_USART_MR_PAR_OFFSET |\r
+               opt->channelmode << AVR32_USART_MR_CHMODE_OFFSET;\r
+\r
+  if (opt->stopbits > USART_2_STOPBITS)\r
+  {\r
+    // Set two stop bits\r
+    usart->mr |= AVR32_USART_MR_NBSTOP_2 << AVR32_USART_MR_NBSTOP_OFFSET;\r
+    // and a timeguard period gives the rest.\r
+    usart->ttgr = opt->stopbits - USART_2_STOPBITS;\r
+  }\r
+  else\r
+    // Insert 1 or 2 stop bits.\r
+    usart->mr |= opt->stopbits << AVR32_USART_MR_NBSTOP_OFFSET;\r
+\r
+  // Set normal mode.\r
+  usart->mr = (usart->mr & ~AVR32_USART_MR_MODE_MASK) |\r
+              AVR32_USART_MR_MODE_NORMAL << AVR32_USART_MR_MODE_OFFSET;\r
+\r
+  // Setup complete; enable communication.\r
+  // Enable input and output.\r
+  usart->cr = AVR32_USART_CR_RXEN_MASK |\r
+              AVR32_USART_CR_TXEN_MASK;\r
+\r
+  return USART_SUCCESS;\r
+}\r
+\r
+\r
+int usart_init_rs485(volatile avr32_usart_t *usart, const usart_options_t *opt, long pba_hz)\r
+{\r
+  // First: Setup standard RS232.\r
+  if (usart_init_rs232(usart, opt, pba_hz) == USART_INVALID_INPUT)\r
+    return USART_INVALID_INPUT;\r
+\r
+  // Set RS485 mode.\r
+  usart->mr = (usart->mr & ~AVR32_USART_MR_MODE_MASK) |\r
+              AVR32_USART_MR_MODE_RS485 << AVR32_USART_MR_MODE_OFFSET;\r
+\r
+  return USART_SUCCESS;\r
+}\r
+\r
+\r
+int usart_init_IrDA(volatile avr32_usart_t *usart, const usart_options_t *opt,\r
+                    long pba_hz, unsigned char irda_filter)\r
+{\r
+  // First: Setup standard RS232.\r
+  if (usart_init_rs232(usart, opt, pba_hz) == USART_INVALID_INPUT)\r
+    return USART_INVALID_INPUT;\r
+\r
+  // Set IrDA filter.\r
+  usart->ifr = irda_filter;\r
+\r
+  // Set IrDA mode and activate filtering of input.\r
+  usart->mr = (usart->mr & ~AVR32_USART_MR_MODE_MASK) |\r
+              AVR32_USART_MODE_IRDA << AVR32_USART_MR_MODE_OFFSET |\r
+              AVR32_USART_MR_FILTER_MASK;\r
+\r
+  return USART_SUCCESS;\r
+}\r
+\r
+\r
+int usart_init_iso7816(volatile avr32_usart_t *usart, const usart_iso7816_options_t *opt, int t, long pba_hz)\r
+{\r
+  // Reset the USART and shutdown TX and RX.\r
+  usart_reset(usart);\r
+\r
+  // Check input values.\r
+  if (!opt || // Null pointer.\r
+      opt->paritytype > 1)\r
+    return USART_INVALID_INPUT;\r
+\r
+  if (t == 0)\r
+  {\r
+    // Set USART mode to ISO7816, T=0.\r
+    // The T=0 protocol always uses 2 stop bits.\r
+    usart->mr = AVR32_USART_MR_MODE_ISO7816_T0 << AVR32_USART_MR_MODE_OFFSET |\r
+                AVR32_USART_MR_NBSTOP_2 << AVR32_USART_MR_NBSTOP_OFFSET |\r
+                opt->bit_order << AVR32_USART_MR_MSBF_OFFSET; // Allow MSBF in T=0.\r
+  }\r
+  else if (t == 1)\r
+  {\r
+    // Only LSB first in the T=1 protocol.\r
+    // max_iterations field is only used in T=0 mode.\r
+    if (opt->bit_order != 0 ||\r
+        opt->max_iterations != 0)\r
+      return USART_INVALID_INPUT;\r
+\r
+    // Set USART mode to ISO7816, T=1.\r
+    // The T=1 protocol always uses 1 stop bit.\r
+    usart->mr = AVR32_USART_MR_MODE_ISO7816_T1 << AVR32_USART_MR_MODE_OFFSET |\r
+                AVR32_USART_MR_NBSTOP_1 << AVR32_USART_MR_NBSTOP_OFFSET;\r
+  }\r
+  else\r
+    return USART_INVALID_INPUT;\r
+\r
+  if (usart_set_iso7816_clock(usart, opt->iso7816_hz, pba_hz) == USART_INVALID_INPUT)\r
+    return USART_INVALID_INPUT;\r
+\r
+  // Set FIDI register: bit rate = selected clock/FI_DI_ratio/16.\r
+  usart->fidi = opt->fidi_ratio;\r
+\r
+  // Set ISO7816 spesific options in the MODE register.\r
+  usart->mr |= opt->paritytype << AVR32_USART_MR_PAR_OFFSET |\r
+               AVR32_USART_MR_CLKO_MASK | // Enable clock output.\r
+               opt->inhibit_nack << AVR32_USART_MR_INACK_OFFSET |\r
+               opt->dis_suc_nack << AVR32_USART_MR_DSNACK_OFFSET |\r
+               opt->max_iterations << AVR32_USART_MR_MAX_ITERATION_OFFSET;\r
+\r
+  // Setup complete; enable the receiver by default.\r
+  usart_iso7816_enable_receiver(usart);\r
+\r
+  return USART_SUCCESS;\r
+}\r
+\r
+\r
+#if defined(AVR32_USART_400_H_INCLUDED) || \\r
+    defined(AVR32_USART_410_H_INCLUDED) || \\r
+    defined(AVR32_USART_420_H_INCLUDED) || \\r
+    defined(AVR32_USART_440_H_INCLUDED) || \\r
+    defined(AVR32_USART_602_H_INCLUDED)\r
+\r
+\r
+int usart_init_lin_master(volatile avr32_usart_t *usart, unsigned long baudrate, long pba_hz)\r
+{\r
+  // Reset the USART and shutdown TX and RX.\r
+  usart_reset(usart);\r
+\r
+  // Check input values.\r
+  if (usart_set_async_baudrate(usart, baudrate, pba_hz) == USART_INVALID_INPUT)\r
+    return USART_INVALID_INPUT;\r
+\r
+  usart->mr |= AVR32_USART_MR_MODE_LIN_MASTER << AVR32_USART_MR_MODE_OFFSET;  // LIN master mode.\r
+\r
+  // Setup complete; enable communication.\r
+  // Enable input and output.\r
+  usart->cr = AVR32_USART_CR_RXEN_MASK |\r
+              AVR32_USART_CR_TXEN_MASK;\r
+\r
+  return USART_SUCCESS;\r
+}\r
+\r
+\r
+int usart_init_lin_slave(volatile avr32_usart_t *usart, unsigned long baudrate, long pba_hz)\r
+{\r
+  // Reset the USART and shutdown TX and RX.\r
+  usart_reset(usart);\r
+\r
+  // Check input values.\r
+  if (usart_set_async_baudrate(usart, baudrate, pba_hz) == USART_INVALID_INPUT)\r
+    return USART_INVALID_INPUT;\r
+\r
+  usart->mr |= AVR32_USART_MR_MODE_LIN_SLAVE << AVR32_USART_MR_MODE_OFFSET; // LIN slave mode.\r
+\r
+  // Setup complete; enable communication.\r
+  // Enable input and output.\r
+  usart->cr = AVR32_USART_CR_RXEN_MASK |\r
+              AVR32_USART_CR_TXEN_MASK;\r
+\r
+  return USART_SUCCESS;\r
+}\r
+\r
+\r
+int usart_init_spi_master(volatile avr32_usart_t *usart, const usart_spi_options_t *opt, long pba_hz)\r
+{\r
+  // Reset the USART and shutdown TX and RX.\r
+  usart_reset(usart);\r
+\r
+  // Check input values.\r
+  if (!opt || // Null pointer.\r
+      opt->charlength < 5 || opt->charlength > 9 ||\r
+      opt->spimode > 3 ||\r
+      opt->channelmode > 3 ||\r
+      usart_set_spi_master_baudrate(usart, opt->baudrate, pba_hz) == USART_INVALID_INPUT)\r
+    return USART_INVALID_INPUT;\r
+\r
+  if (opt->charlength == 9)\r
+  {\r
+    // Character length set to 9 bits. MODE9 dominates CHRL.\r
+    usart->mr |= AVR32_USART_MR_MODE9_MASK;\r
+  }\r
+  else\r
+  {\r
+    // CHRL gives the character length (- 5) when MODE9 = 0.\r
+    usart->mr |= (opt->charlength - 5) << AVR32_USART_MR_CHRL_OFFSET;\r
+  }\r
+\r
+  usart->mr |= AVR32_USART_MR_MODE_SPI_MASTER << AVR32_USART_MR_MODE_OFFSET | // SPI master mode.\r
+               ((opt->spimode & 0x1) ^ 0x1) << AVR32_USART_MR_SYNC_OFFSET |   // SPI clock phase.\r
+               opt->channelmode << AVR32_USART_MR_CHMODE_OFFSET |             // Channel mode.\r
+               (opt->spimode >> 1) << AVR32_USART_MR_MSBF_OFFSET |            // SPI clock polarity.\r
+               AVR32_USART_MR_CLKO_MASK;                                      // Drive SCK pin.\r
+\r
+  // Setup complete; enable communication.\r
+  // Enable input and output.\r
+  usart->cr = AVR32_USART_CR_RXEN_MASK |\r
+              AVR32_USART_CR_TXEN_MASK;\r
+\r
+  return USART_SUCCESS;\r
+}\r
+\r
+\r
+int usart_init_spi_slave(volatile avr32_usart_t *usart, const usart_spi_options_t *opt, long pba_hz)\r
+{\r
+  // Reset the USART and shutdown TX and RX.\r
+  usart_reset(usart);\r
+\r
+  // Check input values.\r
+  if (!opt || // Null pointer.\r
+      opt->charlength < 5 || opt->charlength > 9 ||\r
+      opt->spimode > 3 ||\r
+      opt->channelmode > 3 ||\r
+      usart_set_spi_slave_baudrate(usart) == USART_INVALID_INPUT)\r
+    return USART_INVALID_INPUT;\r
+\r
+  if (opt->charlength == 9)\r
+  {\r
+    // Character length set to 9 bits. MODE9 dominates CHRL.\r
+    usart->mr |= AVR32_USART_MR_MODE9_MASK;\r
+  }\r
+  else\r
+  {\r
+    // CHRL gives the character length (- 5) when MODE9 = 0.\r
+    usart->mr |= (opt->charlength - 5) << AVR32_USART_MR_CHRL_OFFSET;\r
+  }\r
+\r
+  usart->mr |= AVR32_USART_MR_MODE_SPI_SLAVE << AVR32_USART_MR_MODE_OFFSET |  // SPI slave mode.\r
+               ((opt->spimode & 0x1) ^ 0x1) << AVR32_USART_MR_SYNC_OFFSET |   // SPI clock phase.\r
+               opt->channelmode << AVR32_USART_MR_CHMODE_OFFSET |             // Channel mode.\r
+               (opt->spimode >> 1) << AVR32_USART_MR_MSBF_OFFSET;             // SPI clock polarity.\r
+\r
+  // Setup complete; enable communication.\r
+  // Enable input and output.\r
+  usart->cr = AVR32_USART_CR_RXEN_MASK |\r
+              AVR32_USART_CR_TXEN_MASK;\r
+\r
+  return USART_SUCCESS;\r
+}\r
+\r
+\r
+#endif  // USART rev. >= 4.0.0\r
+\r
+\r
+//! @}\r
+\r
+\r
+//------------------------------------------------------------------------------\r
+#if defined(AVR32_USART_400_H_INCLUDED) || \\r
+    defined(AVR32_USART_410_H_INCLUDED) || \\r
+    defined(AVR32_USART_420_H_INCLUDED) || \\r
+    defined(AVR32_USART_440_H_INCLUDED) || \\r
+    defined(AVR32_USART_602_H_INCLUDED)\r
+\r
+\r
+/*! \name SPI Control Functions\r
+ */\r
+//! @{\r
+\r
+\r
+int usart_spi_selectChip(volatile avr32_usart_t *usart)\r
+{\r
+  // Force the SPI chip select.\r
+  usart->cr = AVR32_USART_CR_RTSEN_MASK;\r
+\r
+  return USART_SUCCESS;\r
+}\r
+\r
+\r
+int usart_spi_unselectChip(volatile avr32_usart_t *usart)\r
+{\r
+  int timeout = USART_DEFAULT_TIMEOUT;\r
+\r
+  do\r
+  {\r
+    if (!timeout--) return USART_FAILURE;\r
+  } while (!usart_tx_empty(usart));\r
+\r
+  // Release the SPI chip select.\r
+  usart->cr = AVR32_USART_CR_RTSDIS_MASK;\r
+\r
+  return USART_SUCCESS;\r
+}\r
+\r
+\r
+//! @}\r
+\r
+\r
+#endif  // USART rev. >= 4.0.0\r
+\r
+\r
+//------------------------------------------------------------------------------\r
+/*! \name Transmit/Receive Functions\r
+ */\r
+//! @{\r
+\r
+\r
+int usart_send_address(volatile avr32_usart_t *usart, int address)\r
+{\r
+  // Check if USART is in multidrop / RS485 mode.\r
+  if (!usart_mode_is_multidrop(usart)) return USART_MODE_FAULT;\r
+\r
+  // Prepare to send an address.\r
+  usart->cr = AVR32_USART_CR_SENDA_MASK;\r
+\r
+  // Write the address to TX.\r
+  usart_bw_write_char(usart, address);\r
+\r
+  return USART_SUCCESS;\r
+}\r
+\r
+\r
+int usart_write_char(volatile avr32_usart_t *usart, int c)\r
+{\r
+  if (usart_tx_ready(usart))\r
+  {\r
+    usart->thr = (c << AVR32_USART_THR_TXCHR_OFFSET) & AVR32_USART_THR_TXCHR_MASK;\r
+    return USART_SUCCESS;\r
+  }\r
+  else\r
+    return USART_TX_BUSY;\r
+}\r
+\r
+\r
+int usart_putchar(volatile avr32_usart_t *usart, int c)\r
+{\r
+  int timeout = USART_DEFAULT_TIMEOUT;\r
+\r
+  if (c == '\n')\r
+  {\r
+    do\r
+    {\r
+      if (!timeout--) return USART_FAILURE;\r
+    } while (usart_write_char(usart, '\r') != USART_SUCCESS);\r
+\r
+    timeout = USART_DEFAULT_TIMEOUT;\r
+  }\r
+\r
+  do\r
+  {\r
+    if (!timeout--) return USART_FAILURE;\r
+  } while (usart_write_char(usart, c) != USART_SUCCESS);\r
+\r
+  return USART_SUCCESS;\r
+}\r
+\r
+\r
+int usart_read_char(volatile avr32_usart_t *usart, int *c)\r
+{\r
+  // Check for errors: frame, parity and overrun. In RS485 mode, a parity error\r
+  // would mean that an address char has been received.\r
+  if (usart->csr & (AVR32_USART_CSR_OVRE_MASK |\r
+                    AVR32_USART_CSR_FRAME_MASK |\r
+                    AVR32_USART_CSR_PARE_MASK))\r
+    return USART_RX_ERROR;\r
+\r
+  // No error; if we really did receive a char, read it and return SUCCESS.\r
+  if (usart_test_hit(usart))\r
+  {\r
+    *c = (usart->rhr & AVR32_USART_RHR_RXCHR_MASK) >> AVR32_USART_RHR_RXCHR_OFFSET;\r
+    return USART_SUCCESS;\r
+  }\r
+  else\r
+    return USART_RX_EMPTY;\r
+}\r
+\r
+\r
+int usart_getchar(volatile avr32_usart_t *usart)\r
+{\r
+  int c, ret;\r
+\r
+  while ((ret = usart_read_char(usart, &c)) == USART_RX_EMPTY);\r
+\r
+  if (ret == USART_RX_ERROR)\r
+    return USART_FAILURE;\r
+\r
+  return c;\r
+}\r
+\r
+\r
+void usart_write_line(volatile avr32_usart_t *usart, const char *string)\r
+{\r
+  while (*string != '\0')\r
+    usart_putchar(usart, *string++);\r
+}\r
+\r
+\r
+int usart_get_echo_line(volatile avr32_usart_t *usart)\r
+{\r
+  int rx_char;\r
+  int retval = USART_SUCCESS;\r
+\r
+  while (1)\r
+  {\r
+    rx_char = usart_getchar(usart);\r
+    if (rx_char == USART_FAILURE)\r
+    {\r
+      usart_write_line(usart, "Error!!!\n");\r
+      retval = USART_FAILURE;\r
+      break;\r
+    }\r
+    if (rx_char == '\x03')\r
+    {\r
+      retval = USART_FAILURE;\r
+      break;\r
+    }\r
+    usart_putchar(usart, rx_char);\r
+    if (rx_char == '\r')\r
+    {\r
+      usart_putchar(usart, '\n');\r
+      break;\r
+    }\r
+  }\r
+\r
+  return retval;\r
+}\r
+\r
+\r
+//! @}\r

diff --git a/Demo/AVR32_UC3A_GCC/Atmel_SW_Framework/DRIVERS/USART/usart.h b/Demo/AVR32_UC3A_GCC/Atmel_SW_Framework/DRIVERS/USART/usart.h
new file mode 100644 (file)
index 0000000..6230a5b
--- /dev/null
+++ b/Demo/AVR32_UC3A_GCC/Atmel_SW_Framework/DRIVERS/USART/usart.h
@@ -0,0 +1,889 @@
+/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */\r
+
+/*This file is prepared for Doxygen automatic documentation generation.*/\r
+/*! \file *********************************************************************\r
+ *\r
+ * \brief USART driver for AVR32 UC3.\r
+ *\r
+ * This file contains basic functions for the AVR32 USART, with support for all\r
+ * modes, settings and clock speeds.\r
+ *\r
+ * - Compiler:           IAR EWAVR32 and GNU GCC for AVR32\r
+ * - Supported devices:  All AVR32 devices with a USART module can be used.\r
+ * - AppNote:\r
+ *\r
+ * \author               Atmel Corporation: http://www.atmel.com \n\r
+ *                       Support and FAQ: http://support.atmel.no/\r
+ *\r
+ ******************************************************************************/\r
+\r
+/* Copyright (c) 2009 Atmel Corporation. All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice, this\r
+ * list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an Atmel\r
+ * AVR product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\r
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\r
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\r
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE\r
+ *\r
+ */\r
+\r
+#ifndef _USART_H_\r
+#define _USART_H_\r
+\r
+#include <avr32/io.h>\r
+#include "compiler.h"\r
+\r
+\r
+/*! \name Return Values\r
+ */\r
+//! @{\r
+#define USART_SUCCESS                 0 //!< Successful completion.\r
+#define USART_FAILURE                -1 //!< Failure because of some unspecified reason.\r
+#define USART_INVALID_INPUT           1 //!< Input value out of range.\r
+#define USART_INVALID_ARGUMENT       -1 //!< Argument value out of range.\r
+#define USART_TX_BUSY                 2 //!< Transmitter was busy.\r
+#define USART_RX_EMPTY                3 //!< Nothing was received.\r
+#define USART_RX_ERROR                4 //!< Transmission error occurred.\r
+#define USART_MODE_FAULT              5 //!< USART not in the appropriate mode.\r
+//! @}\r
+\r
+//! Default time-out value (number of attempts).\r
+#define USART_DEFAULT_TIMEOUT         10000\r
+\r
+/*! \name Parity Settings\r
+ */\r
+//! @{\r
+#define USART_EVEN_PARITY             AVR32_USART_MR_PAR_EVEN   //!< Use even parity on character transmission.\r
+#define USART_ODD_PARITY              AVR32_USART_MR_PAR_ODD    //!< Use odd parity on character transmission.\r
+#define USART_SPACE_PARITY            AVR32_USART_MR_PAR_SPACE  //!< Use a space as parity bit.\r
+#define USART_MARK_PARITY             AVR32_USART_MR_PAR_MARK   //!< Use a mark as parity bit.\r
+#define USART_NO_PARITY               AVR32_USART_MR_PAR_NONE   //!< Don't use a parity bit.\r
+#define USART_MULTIDROP_PARITY        AVR32_USART_MR_PAR_MULTI  //!< Parity bit is used to flag address characters.\r
+//! @}\r
+\r
+/*! \name Stop Bits Settings\r
+ */\r
+//! @{\r
+#define USART_1_STOPBIT               AVR32_USART_MR_NBSTOP_1   //!< Use 1 stop bit.\r
+#define USART_1_5_STOPBITS            AVR32_USART_MR_NBSTOP_1_5 //!< Use 1.5 stop bits.\r
+#define USART_2_STOPBITS              AVR32_USART_MR_NBSTOP_2   //!< Use 2 stop bits (for more, just give the number of bits).\r
+//! @}\r
+\r
+/*! \name Channel Modes\r
+ */\r
+//! @{\r
+#define USART_NORMAL_CHMODE           AVR32_USART_MR_CHMODE_NORMAL      //!< Normal communication.\r
+#define USART_AUTO_ECHO               AVR32_USART_MR_CHMODE_ECHO        //!< Echo data.\r
+#define USART_LOCAL_LOOPBACK          AVR32_USART_MR_CHMODE_LOCAL_LOOP  //!< Local loopback.\r
+#define USART_REMOTE_LOOPBACK         AVR32_USART_MR_CHMODE_REMOTE_LOOP //!< Remote loopback.\r
+//! @}\r
+\r
+#if defined(AVR32_USART_400_H_INCLUDED) || \\r
+    defined(AVR32_USART_410_H_INCLUDED) || \\r
+    defined(AVR32_USART_420_H_INCLUDED) || \\r
+    defined(AVR32_USART_440_H_INCLUDED) || \\r
+    defined(AVR32_USART_602_H_INCLUDED)\r
+\r
+/*! \name LIN Node Actions\r
+ */\r
+//! @{\r
+#define USART_LIN_PUBLISH_ACTION      AVR32_USART_LINMR_NACT_PUBLISH    //!< The USART transmits the response.\r
+#define USART_LIN_SUBSCRIBE_ACTION    AVR32_USART_LINMR_NACT_SUBSCRIBE  //!< The USART receives the response.\r
+#define USART_LIN_IGNORE_ACTION       AVR32_USART_LINMR_NACT_IGNORE     //!< The USART does not transmit and does not receive the reponse.\r
+//! @}\r
+\r
+/*! \name LIN Checksum Types\r
+ */\r
+//! @{\r
+#define USART_LIN_ENHANCED_CHECKSUM   0 //!< LIN 2.0 "enhanced" checksum.\r
+#define USART_LIN_CLASSIC_CHECKSUM    1 //!< LIN 1.3 "classic" checksum.\r
+//! @}\r
+\r
+#endif  // USART rev. >= 4.0.0\r
+\r
+\r
+//! Input parameters when initializing RS232 and similar modes.\r
+typedef struct\r
+{\r
+  //! Set baud rate of the USART (unused in slave modes).\r
+  unsigned long baudrate;\r
+\r
+  //! Number of bits to transmit as a character (5 to 9).\r
+  unsigned char charlength;\r
+\r
+  //! How to calculate the parity bit: \ref USART_EVEN_PARITY, \ref USART_ODD_PARITY,\r
+  //! \ref USART_SPACE_PARITY, \ref USART_MARK_PARITY, \ref USART_NO_PARITY or\r
+  //! \ref USART_MULTIDROP_PARITY.\r
+  unsigned char paritytype;\r
+\r
+  //! Number of stop bits between two characters: \ref USART_1_STOPBIT,\r
+  //! \ref USART_1_5_STOPBITS, \ref USART_2_STOPBITS or any number from 3 to 257\r
+  //! which will result in a time guard period of that length between characters.\r
+  //! \note \ref USART_1_5_STOPBITS is supported in asynchronous modes only.\r
+  unsigned short stopbits;\r
+\r
+  //! Run the channel in testmode: \ref USART_NORMAL_CHMODE, \ref USART_AUTO_ECHO,\r
+  //! \ref USART_LOCAL_LOOPBACK or \ref USART_REMOTE_LOOPBACK.\r
+  unsigned char channelmode;\r
+} usart_options_t;\r
+\r
+//! Input parameters when initializing ISO7816 mode.\r
+typedef struct\r
+{\r
+  //! Set the frequency of the ISO7816 clock.\r
+  unsigned long iso7816_hz;\r
+\r
+  //! The number of ISO7816 clock ticks in every bit period (1 to 2047, 0 = disable clock).\r
+  //! Bit rate = \ref iso7816_hz / \ref fidi_ratio.\r
+  unsigned short fidi_ratio;\r
+\r
+  //! How to calculate the parity bit: \ref USART_EVEN_PARITY for normal mode or\r
+  //! \ref USART_ODD_PARITY for inverse mode.\r
+  unsigned char paritytype;\r
+\r
+  //! Inhibit Non Acknowledge:\n\r
+  //!   - 0: the NACK is generated;\n\r
+  //!   - 1: the NACK is not generated.\r
+  //!\r
+  //! \note This bit will be used only in ISO7816 mode, protocol T = 0 receiver.\r
+  int inhibit_nack;\r
+\r
+  //! Disable successive NACKs.\r
+  //! Successive parity errors are counted up to the value in the \ref max_iterations field.\r
+  //! These parity errors generate a NACK on the ISO line. As soon as this value is reached,\r
+  //! no addititional NACK is sent on the ISO line. The ITERATION flag is asserted.\r
+  int dis_suc_nack;\r
+\r
+  //! Max number of repetitions (0 to 7).\r
+  unsigned char max_iterations;\r
+\r
+  //! Bit order in transmitted characters:\n\r
+  //!   - 0: LSB first;\n\r
+  //!   - 1: MSB first.\r
+  int bit_order;\r
+} usart_iso7816_options_t;\r
+\r
+#if defined(AVR32_USART_400_H_INCLUDED) || \\r
+    defined(AVR32_USART_410_H_INCLUDED) || \\r
+    defined(AVR32_USART_420_H_INCLUDED) || \\r
+    defined(AVR32_USART_440_H_INCLUDED) || \\r
+    defined(AVR32_USART_602_H_INCLUDED)\r
+\r
+//! Input parameters when initializing SPI mode.\r
+typedef struct\r
+{\r
+  //! Set the frequency of the SPI clock (unused in slave mode).\r
+  unsigned long baudrate;\r
+\r
+  //! Number of bits to transmit as a character (5 to 9).\r
+  unsigned char charlength;\r
+\r
+  //! Which SPI mode to use.\r
+  unsigned char spimode;\r
+\r
+  //! Run the channel in testmode: \ref USART_NORMAL_CHMODE, \ref USART_AUTO_ECHO,\r
+  //! \ref USART_LOCAL_LOOPBACK or \ref USART_REMOTE_LOOPBACK.\r
+  unsigned char channelmode;\r
+} usart_spi_options_t;\r
+\r
+#endif  // USART rev. >= 4.0.0\r
+\r
+\r
+//------------------------------------------------------------------------------\r
+/*! \name Initialization Functions\r
+ */\r
+//! @{\r
+\r
+/*! \brief Resets the USART and disables TX and RX.\r
+ *\r
+ * \param usart   Base address of the USART instance.\r
+ */\r
+extern void usart_reset(volatile avr32_usart_t *usart);\r
+\r
+/*! \brief Sets up the USART to use the standard RS232 protocol.\r
+ *\r
+ * \param usart   Base address of the USART instance.\r
+ * \param opt     Options needed to set up RS232 communication (see \ref usart_options_t).\r
+ * \param pba_hz  USART module input clock frequency (PBA clock, Hz).\r
+ *\r
+ * \retval USART_SUCCESS        Mode successfully initialized.\r
+ * \retval USART_INVALID_INPUT  One or more of the arguments is out of valid range.\r
+ */\r
+extern int usart_init_rs232(volatile avr32_usart_t *usart, const usart_options_t *opt, long pba_hz);\r
+\r
+/*! \brief Sets up the USART to use the standard RS232 protocol in TX-only mode.\r
+ *\r
+ * Compared to \ref usart_init_rs232, this function allows very high baud rates\r
+ * (up to \a pba_hz instead of \a pba_hz / \c 8) at the expense of full duplex.\r
+ *\r
+ * \param usart   Base address of the USART instance.\r
+ * \param opt     Options needed to set up RS232 communication (see \ref usart_options_t).\r
+ * \param pba_hz  USART module input clock frequency (PBA clock, Hz).\r
+ *\r
+ * \retval USART_SUCCESS        Mode successfully initialized.\r
+ * \retval USART_INVALID_INPUT  One or more of the arguments is out of valid range.\r
+ *\r
+ * \note The \c 1.5 stop bit is not supported in this mode.\r
+ */\r
+extern int usart_init_rs232_tx_only(volatile avr32_usart_t *usart, const usart_options_t *opt, long pba_hz);\r
+\r
+/*! \brief Sets up the USART to use hardware handshaking.\r
+ *\r
+ * \param usart   Base address of the USART instance.\r
+ * \param opt     Options needed to set up RS232 communication (see \ref usart_options_t).\r
+ * \param pba_hz  USART module input clock frequency (PBA clock, Hz).\r
+ *\r
+ * \retval USART_SUCCESS        Mode successfully initialized.\r
+ * \retval USART_INVALID_INPUT  One or more of the arguments is out of valid range.\r
+ *\r
+ * \note \ref usart_init_rs232 does not need to be invoked before this function.\r
+ */\r
+extern int usart_init_hw_handshaking(volatile avr32_usart_t *usart, const usart_options_t *opt, long pba_hz);\r
+\r
+/*! \brief Sets up the USART to use the modem protocol, activating dedicated inputs/outputs.\r
+ *\r
+ * \param usart   Base address of the USART instance.\r
+ * \param opt     Options needed to set up RS232 communication (see \ref usart_options_t).\r
+ * \param pba_hz  USART module input clock frequency (PBA clock, Hz).\r
+ *\r
+ * \retval USART_SUCCESS        Mode successfully initialized.\r
+ * \retval USART_INVALID_INPUT  One or more of the arguments is out of valid range.\r
+ */\r
+extern int usart_init_modem(volatile avr32_usart_t *usart, const usart_options_t *opt, long pba_hz);\r
+\r
+/*! \brief Sets up the USART to use a synchronous RS232-like protocol in master mode.\r
+ *\r
+ * \param usart   Base address of the USART instance.\r
+ * \param opt     Options needed to set up RS232 communication (see \ref usart_options_t).\r
+ * \param pba_hz  USART module input clock frequency (PBA clock, Hz).\r
+ *\r
+ * \retval USART_SUCCESS        Mode successfully initialized.\r
+ * \retval USART_INVALID_INPUT  One or more of the arguments is out of valid range.\r
+ */\r
+extern int usart_init_sync_master(volatile avr32_usart_t *usart, const usart_options_t *opt, long pba_hz);\r
+\r
+/*! \brief Sets up the USART to use a synchronous RS232-like protocol in slave mode.\r
+ *\r
+ * \param usart   Base address of the USART instance.\r
+ * \param opt     Options needed to set up RS232 communication (see \ref usart_options_t).\r
+ * \param pba_hz  USART module input clock frequency (PBA clock, Hz).\r
+ *\r
+ * \retval USART_SUCCESS        Mode successfully initialized.\r
+ * \retval USART_INVALID_INPUT  One or more of the arguments is out of valid range.\r
+ */\r
+extern int usart_init_sync_slave(volatile avr32_usart_t *usart, const usart_options_t *opt, long pba_hz);\r
+\r
+/*! \brief Sets up the USART to use the RS485 protocol.\r
+ *\r
+ * \param usart   Base address of the USART instance.\r
+ * \param opt     Options needed to set up RS232 communication (see \ref usart_options_t).\r
+ * \param pba_hz  USART module input clock frequency (PBA clock, Hz).\r
+ *\r
+ * \retval USART_SUCCESS        Mode successfully initialized.\r
+ * \retval USART_INVALID_INPUT  One or more of the arguments is out of valid range.\r
+ */\r
+extern int usart_init_rs485(volatile avr32_usart_t *usart, const usart_options_t *opt, long pba_hz);\r
+\r
+/*! \brief Sets up the USART to use the IrDA protocol.\r
+ *\r
+ * \param usart         Base address of the USART instance.\r
+ * \param opt           Options needed to set up RS232 communication (see \ref usart_options_t).\r
+ * \param pba_hz        USART module input clock frequency (PBA clock, Hz).\r
+ * \param irda_filter   Counter used to distinguish received ones from zeros.\r
+ *\r
+ * \retval USART_SUCCESS        Mode successfully initialized.\r
+ * \retval USART_INVALID_INPUT  One or more of the arguments is out of valid range.\r
+ */\r
+extern int usart_init_IrDA(volatile avr32_usart_t *usart, const usart_options_t *opt,\r
+                           long pba_hz, unsigned char irda_filter);\r
+\r
+/*! \brief Sets up the USART to use the ISO7816 T=0 or T=1 smartcard protocols.\r
+ *\r
+ * The receiver is enabled by default. \ref usart_iso7816_enable_receiver and\r
+ * \ref usart_iso7816_enable_transmitter can be called to change the half-duplex\r
+ * communication direction.\r
+ *\r
+ * \param usart   Base address of the USART instance.\r
+ * \param opt     Options needed to set up ISO7816 communication (see \ref usart_iso7816_options_t).\r
+ * \param t       ISO7816 mode to use (T=0 or T=1).\r
+ * \param pba_hz  USART module input clock frequency (PBA clock, Hz).\r
+ *\r
+ * \retval USART_SUCCESS        Mode successfully initialized.\r
+ * \retval USART_INVALID_INPUT  One or more of the arguments is out of valid range.\r
+ */\r
+extern int usart_init_iso7816(volatile avr32_usart_t *usart, const usart_iso7816_options_t *opt, int t, long pba_hz);\r
+\r
+#if defined(AVR32_USART_400_H_INCLUDED) || \\r
+    defined(AVR32_USART_410_H_INCLUDED) || \\r
+    defined(AVR32_USART_420_H_INCLUDED) || \\r
+    defined(AVR32_USART_440_H_INCLUDED) || \\r
+    defined(AVR32_USART_602_H_INCLUDED)\r
+\r
+/*! \brief Sets up the USART to use the LIN master mode.\r
+ *\r
+ * \param usart     Base address of the USART instance.\r
+ * \param baudrate  Baud rate.\r
+ * \param pba_hz    USART module input clock frequency (PBA clock, Hz).\r
+ *\r
+ */\r
+extern int usart_init_lin_master(volatile avr32_usart_t *usart, unsigned long baudrate, long pba_hz);\r
+\r
+/*! \brief Sets up the USART to use the LIN slave mode.\r
+ *\r
+ * \param usart     Base address of the USART instance.\r
+ * \param baudrate  Baud rate.\r
+ * \param pba_hz    USART module input clock frequency (PBA clock, Hz).\r
+ *\r
+ */\r
+extern int usart_init_lin_slave(volatile avr32_usart_t *usart, unsigned long baudrate, long pba_hz);\r
+\r
+/*! \brief Sets up the USART to use the SPI master mode.\r
+ *\r
+ * \ref usart_spi_selectChip and \ref usart_spi_unselectChip can be called to\r
+ * select or unselect the SPI slave chip.\r
+ *\r
+ * \param usart   Base address of the USART instance.\r
+ * \param opt     Options needed to set up SPI mode (see \ref usart_spi_options_t).\r
+ * \param pba_hz  USART module input clock frequency (PBA clock, Hz).\r
+ *\r
+ * \retval USART_SUCCESS        Mode successfully initialized.\r
+ * \retval USART_INVALID_INPUT  One or more of the arguments is out of valid range.\r
+ */\r
+extern int usart_init_spi_master(volatile avr32_usart_t *usart, const usart_spi_options_t *opt, long pba_hz);\r
+\r
+/*! \brief Sets up the USART to use the SPI slave mode.\r
+ *\r
+ * \param usart   Base address of the USART instance.\r
+ * \param opt     Options needed to set up SPI mode (see \ref usart_spi_options_t).\r
+ * \param pba_hz  USART module input clock frequency (PBA clock, Hz).\r
+ *\r
+ * \retval USART_SUCCESS        Mode successfully initialized.\r
+ * \retval USART_INVALID_INPUT  One or more of the arguments is out of valid range.\r
+ */\r
+extern int usart_init_spi_slave(volatile avr32_usart_t *usart, const usart_spi_options_t *opt, long pba_hz);\r
+\r
+#endif  // USART rev. >= 4.0.0\r
+\r
+//! @}\r
+\r
+\r
+//------------------------------------------------------------------------------\r
+/*! \name Read and Reset Error Status Bits\r
+ */\r
+//! @{\r
+\r
+/*! \brief Resets the error status.\r
+ *\r
+ * This function resets the status bits indicating that a parity error,\r
+ * framing error or overrun has occurred. The RXBRK bit, indicating\r
+ * a start/end of break condition on the RX line, is also reset.\r
+ *\r
+ * \param usart   Base address of the USART instance.\r
+ */\r
+#if (defined __GNUC__)\r
+__attribute__((__always_inline__))\r
+#endif\r
+extern __inline__ void usart_reset_status(volatile avr32_usart_t *usart)\r
+{\r
+  usart->cr = AVR32_USART_CR_RSTSTA_MASK;\r
+}\r
+\r
+/*! \brief Checks if a parity error has occurred since last status reset.\r
+ *\r
+ * \param usart   Base address of the USART instance.\r
+ *\r
+ * \return \c 1 if a parity error has been detected, otherwise \c 0.\r
+ */\r
+#if (defined __GNUC__)\r
+__attribute__((__always_inline__))\r
+#endif\r
+extern __inline__ int usart_parity_error(volatile avr32_usart_t *usart)\r
+{\r
+  return (usart->csr & AVR32_USART_CSR_PARE_MASK) != 0;\r
+}\r
+\r
+/*! \brief Checks if a framing error has occurred since last status reset.\r
+ *\r
+ * \param usart   Base address of the USART instance.\r
+ *\r
+ * \return \c 1 if a framing error has been detected, otherwise \c 0.\r
+ */\r
+#if (defined __GNUC__)\r
+__attribute__((__always_inline__))\r
+#endif\r
+extern __inline__ int usart_framing_error(volatile avr32_usart_t *usart)\r
+{\r
+  return (usart->csr & AVR32_USART_CSR_FRAME_MASK) != 0;\r
+}\r
+\r
+/*! \brief Checks if an overrun error has occurred since last status reset.\r
+ *\r
+ * \param usart   Base address of the USART instance.\r
+ *\r
+ * \return \c 1 if a overrun error has been detected, otherwise \c 0.\r
+ */\r
+#if (defined __GNUC__)\r
+__attribute__((__always_inline__))\r
+#endif\r
+extern __inline__ int usart_overrun_error(volatile avr32_usart_t *usart)\r
+{\r
+  return (usart->csr & AVR32_USART_CSR_OVRE_MASK) != 0;\r
+}\r
+\r
+#if defined(AVR32_USART_400_H_INCLUDED) || \\r
+    defined(AVR32_USART_410_H_INCLUDED) || \\r
+    defined(AVR32_USART_420_H_INCLUDED) || \\r
+    defined(AVR32_USART_440_H_INCLUDED) || \\r
+    defined(AVR32_USART_602_H_INCLUDED)\r
+\r
+/*! \brief Get LIN Error Status\r
+ *\r
+ * \param usart   Base address of the USART instance.\r
+ *\r
+ * \retval The binary value of the error field.\r
+ */\r
+#if (defined __GNUC__)\r
+__attribute__((__always_inline__))\r
+#endif\r
+extern __inline__ int usart_lin_get_error(volatile avr32_usart_t *usart)\r
+{\r
+  return (usart->csr & (AVR32_USART_CSR_LINSNRE_MASK |\r
+                        AVR32_USART_CSR_LINCE_MASK |\r
+                        AVR32_USART_CSR_LINIPE_MASK |\r
+                        AVR32_USART_CSR_LINISFE_MASK |\r
+                        AVR32_USART_CSR_LINBE_MASK)) >> AVR32_USART_CSR_LINBE_OFFSET;\r
+}\r
+\r
+#endif  // USART rev. >= 4.0.0\r
+\r
+//! @}\r
+\r
+\r
+//------------------------------------------------------------------------------\r
+/*! \name ISO7816 Control Functions\r
+ */\r
+//! @{\r
+\r
+/*! \brief Enables the ISO7816 receiver.\r
+ *\r
+ * The ISO7816 transmitter is disabled.\r
+ *\r
+ * \param usart   Base address of the USART instance.\r
+ */\r
+#if (defined __GNUC__)\r
+__attribute__((__always_inline__))\r
+#endif\r
+extern __inline__ void usart_iso7816_enable_receiver(volatile avr32_usart_t *usart)\r
+{\r
+  usart->cr = AVR32_USART_CR_TXDIS_MASK | AVR32_USART_CR_RXEN_MASK;\r
+}\r
+\r
+/*! \brief Enables the ISO7816 transmitter.\r
+ *\r
+ * The ISO7816 receiver is disabled.\r
+ *\r
+ * \param usart   Base address of the USART instance.\r
+ */\r
+#if (defined __GNUC__)\r
+__attribute__((__always_inline__))\r
+#endif\r
+extern __inline__ void usart_iso7816_enable_transmitter(volatile avr32_usart_t *usart)\r
+{\r
+  usart->cr = AVR32_USART_CR_RXDIS_MASK | AVR32_USART_CR_TXEN_MASK;\r
+}\r
+\r
+//! @}\r
+\r
+\r
+//------------------------------------------------------------------------------\r
+#if defined(AVR32_USART_400_H_INCLUDED) || \\r
+    defined(AVR32_USART_410_H_INCLUDED) || \\r
+    defined(AVR32_USART_420_H_INCLUDED) || \\r
+    defined(AVR32_USART_440_H_INCLUDED) || \\r
+    defined(AVR32_USART_602_H_INCLUDED)\r
+\r
+/*! \name LIN Control Functions\r
+ */\r
+//! @{\r
+\r
+/*! \brief Sets the node action.\r
+ *\r
+ * \param usart   Base address of the USART instance.\r
+ * \param action  The node action: \ref USART_LIN_PUBLISH_ACTION,\r
+ *                \ref USART_LIN_SUBSCRIBE_ACTION or\r
+ *                \ref USART_LIN_IGNORE_ACTION.\r
+ */\r
+#if (defined __GNUC__)\r
+__attribute__((__always_inline__))\r
+#endif\r
+extern __inline__ void usart_lin_set_node_action(volatile avr32_usart_t *usart, unsigned char action)\r
+{\r
+  usart->linmr = (usart->linmr & ~AVR32_USART_LINMR_NACT_MASK) |\r
+                 action << AVR32_USART_LINMR_NACT_OFFSET;\r
+}\r
+\r
+/*! \brief Enables or disables the Identifier parity.\r
+ *\r
+ * \param usart   Base address of the USART instance.\r
+ * \param parity  Whether to enable the Identifier parity: \c TRUE or \c FALSE.\r
+ */\r
+#if (defined __GNUC__)\r
+__attribute__((__always_inline__))\r
+#endif\r
+extern __inline__ void usart_lin_enable_parity(volatile avr32_usart_t *usart, unsigned char parity)\r
+{\r
+  usart->linmr = (usart->linmr & ~AVR32_USART_LINMR_PARDIS_MASK) |\r
+                 !parity << AVR32_USART_LINMR_PARDIS_OFFSET;\r
+}\r
+\r
+/*! \brief Enables or disables the checksum.\r
+ *\r
+ * \param usart   Base address of the USART instance.\r
+ * \param parity  Whether to enable the checksum: \c TRUE or \c FALSE.\r
+ */\r
+#if (defined __GNUC__)\r
+__attribute__((__always_inline__))\r
+#endif\r
+extern __inline__ void usart_lin_enable_checksum(volatile avr32_usart_t *usart, unsigned char checksum)\r
+{\r
+  usart->linmr = (usart->linmr & ~AVR32_USART_LINMR_CHKDIS_MASK) |\r
+                 !checksum << AVR32_USART_LINMR_CHKDIS_OFFSET;\r
+}\r
+\r
+/*! \brief Sets the checksum type.\r
+ *\r
+ * \param usart   Base address of the USART instance.\r
+ * \param chktyp  The checksum type: \ref USART_LIN_ENHANCED_CHEKSUM or\r
+ *                \ref USART_LIN_CLASSIC_CHECKSUM.\r
+ */\r
+#if (defined __GNUC__)\r
+__attribute__((__always_inline__))\r
+#endif\r
+extern __inline__ void usart_lin_set_checksum(volatile avr32_usart_t *usart, unsigned char chktyp)\r
+{\r
+  usart->linmr = (usart->linmr & ~AVR32_USART_LINMR_CHKTYP_MASK) |\r
+                 chktyp << AVR32_USART_LINMR_CHKTYP_OFFSET;\r
+}\r
+\r
+/*! \brief Gets the response data length.\r
+ *\r
+ * \param usart   Base address of the USART instance.\r
+ *\r
+ * \return The response data length.\r
+ */\r
+#if (defined __GNUC__)\r
+__attribute__((__always_inline__))\r
+#endif\r
+extern __inline__ unsigned char usart_lin_get_data_length(volatile avr32_usart_t *usart)\r
+{\r
+  if (usart->linmr & AVR32_USART_LINMR_DLM_MASK)\r
+  {\r
+    unsigned char data_length = 1 << ((usart->linir >> (AVR32_USART_LINIR_IDCHR_OFFSET + 4)) & 0x03);\r
+    if (data_length == 1)\r
+      data_length = 2;\r
+    return data_length;\r
+  }\r
+  else\r
+    return ((usart->linmr & AVR32_USART_LINMR_DLC_MASK) >> AVR32_USART_LINMR_DLC_OFFSET) + 1;\r
+}\r
+\r
+/*! \brief Sets the response data length for LIN 1.x.\r
+ *\r
+ * \param usart   Base address of the USART instance.\r
+ */\r
+#if (defined __GNUC__)\r
+__attribute__((__always_inline__))\r
+#endif\r
+extern __inline__ void usart_lin_set_data_length_lin1x(volatile avr32_usart_t *usart)\r
+{\r
+  usart->linmr |= AVR32_USART_LINMR_DLM_MASK;\r
+}\r
+\r
+/*! \brief Sets the response data length for LIN 2.x.\r
+ *\r
+ * \param usart         Base address of the USART instance.\r
+ * \param data_length   The response data length.\r
+ */\r
+#if (defined __GNUC__)\r
+__attribute__((__always_inline__))\r
+#endif\r
+extern __inline__ void usart_lin_set_data_length_lin2x(volatile avr32_usart_t *usart, unsigned char data_length)\r
+{\r
+  usart->linmr = (usart->linmr & ~(AVR32_USART_LINMR_DLC_MASK |\r
+                                   AVR32_USART_LINMR_DLM_MASK)) |\r
+                 (data_length - 1) << AVR32_USART_LINMR_DLC_OFFSET;\r
+}\r
+\r
+/*! \brief Enables or disables the frame slot mode.\r
+ *\r
+ * \param usart       Base address of the USART instance.\r
+ * \param frameslot   Whether to enable the frame slot mode: \c TRUE or\r
+ *                    \c FALSE.\r
+ */\r
+#if (defined __GNUC__)\r
+__attribute__((__always_inline__))\r
+#endif\r
+extern __inline__ void usart_lin_enable_frameslot(volatile avr32_usart_t *usart, unsigned char frameslot)\r
+{\r
+  usart->linmr = (usart->linmr & ~AVR32_USART_LINMR_FSDIS_MASK) |\r
+                 !frameslot << AVR32_USART_LINMR_FSDIS_OFFSET;\r
+}\r
+\r
+/*! \brief Gets the Identifier character.\r
+ *\r
+ * \param usart   Base address of the USART instance.\r
+ *\r
+ * \return The Identifier character.\r
+ */\r
+#if (defined __GNUC__)\r
+__attribute__((__always_inline__))\r
+#endif\r
+extern __inline__ unsigned char usart_lin_get_id_char(volatile avr32_usart_t *usart)\r
+{\r
+  return (usart->linir & AVR32_USART_LINIR_IDCHR_MASK) >> AVR32_USART_LINIR_IDCHR_OFFSET;\r
+}\r
+\r
+/*! \brief Sets the Identifier character.\r
+ *\r
+ * \param usart     Base address of the USART instance.\r
+ * \param id_char   The Identifier character.\r
+ */\r
+#if (defined __GNUC__)\r
+__attribute__((__always_inline__))\r
+#endif\r
+extern __inline__ void usart_lin_set_id_char(volatile avr32_usart_t *usart, unsigned char id_char)\r
+{\r
+  usart->linir = (usart->linir & ~AVR32_USART_LINIR_IDCHR_MASK) |\r
+                 id_char << AVR32_USART_LINIR_IDCHR_OFFSET;\r
+}\r
+\r
+//! @}\r
+\r
+#endif  // USART rev. >= 4.0.0\r
+\r
+\r
+//------------------------------------------------------------------------------\r
+#if defined(AVR32_USART_400_H_INCLUDED) || \\r
+    defined(AVR32_USART_410_H_INCLUDED) || \\r
+    defined(AVR32_USART_420_H_INCLUDED) || \\r
+    defined(AVR32_USART_440_H_INCLUDED) || \\r
+    defined(AVR32_USART_602_H_INCLUDED)\r
+\r
+/*! \name SPI Control Functions\r
+ */\r
+//! @{\r
+\r
+/*! \brief Selects SPI slave chip.\r
+ *\r
+ * \param usart   Base address of the USART instance.\r
+ *\r
+ * \retval USART_SUCCESS        Success.\r
+ */\r
+extern int usart_spi_selectChip(volatile avr32_usart_t *usart);\r
+\r
+/*! \brief Unselects SPI slave chip.\r
+ *\r
+ * \param usart   Base address of the USART instance.\r
+ *\r
+ * \retval USART_SUCCESS        Success.\r
+ * \retval USART_FAILURE        Time-out.\r
+ */\r
+extern int usart_spi_unselectChip(volatile avr32_usart_t *usart);\r
+\r
+//! @}\r
+\r
+#endif  // USART rev. >= 4.0.0\r
+\r
+\r
+//------------------------------------------------------------------------------\r
+/*! \name Transmit/Receive Functions\r
+ */\r
+//! @{\r
+\r
+/*! \brief Addresses a receiver.\r
+ *\r
+ * While in RS485 mode, receivers only accept data addressed to them.\r
+ * A packet/char with the address tag set has to precede any data.\r
+ * This function is used to address a receiver. This receiver should read\r
+ * all the following data, until an address packet addresses another receiver.\r
+ *\r
+ * \param usart     Base address of the USART instance.\r
+ * \param address   Address of the target device.\r
+ *\r
+ * \retval USART_SUCCESS    Address successfully sent (if current mode is RS485).\r
+ * \retval USART_MODE_FAULT Wrong operating mode.\r
+ */\r
+extern int usart_send_address(volatile avr32_usart_t *usart, int address);\r
+\r
+/*! \brief Tests if the USART is ready to transmit a character.\r
+ *\r
+ * \param usart   Base address of the USART instance.\r
+ *\r
+ * \return \c 1 if the USART Transmit Holding Register is free, otherwise \c 0.\r
+ */\r
+#if (defined __GNUC__)\r
+__attribute__((__always_inline__))\r
+#endif\r
+extern __inline__ int usart_tx_ready(volatile avr32_usart_t *usart)\r
+{\r
+  return (usart->csr & AVR32_USART_CSR_TXRDY_MASK) != 0;\r
+}\r
+\r
+/*! \brief Writes the given character to the TX buffer if the transmitter is ready.\r
+ *\r
+ * \param usart   Base address of the USART instance.\r
+ * \param c       The character (up to 9 bits) to transmit.\r
+ *\r
+ * \retval USART_SUCCESS  The transmitter was ready.\r
+ * \retval USART_TX_BUSY  The transmitter was busy.\r
+ */\r
+extern int usart_write_char(volatile avr32_usart_t *usart, int c);\r
+\r
+/*! \brief An active wait writing a character to the USART.\r
+ *\r
+ * \param usart   Base address of the USART instance.\r
+ * \param c       The character (up to 9 bits) to transmit.\r
+ */\r
+#if (defined __GNUC__)\r
+__attribute__((__always_inline__))\r
+#endif\r
+extern __inline__ void usart_bw_write_char(volatile avr32_usart_t *usart, int c)\r
+{\r
+  while (usart_write_char(usart, c) != USART_SUCCESS);\r
+}\r
+\r
+/*! \brief Sends a character with the USART.\r
+ *\r
+ * \param usart   Base address of the USART instance.\r
+ * \param c       Character to write.\r
+ *\r
+ * \retval USART_SUCCESS  The character was written.\r
+ * \retval USART_FAILURE  The function timed out before the USART transmitter became ready to send.\r
+ */\r
+extern int usart_putchar(volatile avr32_usart_t *usart, int c);\r
+\r
+/*! \brief Tests if all requested USART transmissions are over.\r
+ *\r
+ * \param usart   Base address of the USART instance.\r
+ *\r
+ * \return \c 1 if the USART Transmit Shift Register and the USART Transmit\r
+ *         Holding Register are free, otherwise \c 0.\r
+ */\r
+#if (defined __GNUC__)\r
+__attribute__((__always_inline__))\r
+#endif\r
+extern __inline__ int usart_tx_empty(volatile avr32_usart_t *usart)\r
+{\r
+  return (usart->csr & AVR32_USART_CSR_TXEMPTY_MASK) != 0;\r
+}\r
+\r
+/*! \brief Tests if the USART contains a received character.\r
+ *\r
+ * \param usart   Base address of the USART instance.\r
+ *\r
+ * \return \c 1 if the USART Receive Holding Register is full, otherwise \c 0.\r
+ */\r
+#if (defined __GNUC__)\r
+__attribute__((__always_inline__))\r
+#endif\r
+extern __inline__ int usart_test_hit(volatile avr32_usart_t *usart)\r
+{\r
+  return (usart->csr & AVR32_USART_CSR_RXRDY_MASK) != 0;\r
+}\r
+\r
+/*! \brief Checks the RX buffer for a received character, and stores it at the\r
+ *         given memory location.\r
+ *\r
+ * \param usart   Base address of the USART instance.\r
+ * \param c       Pointer to the where the read character should be stored\r
+ *                (must be at least short in order to accept 9-bit characters).\r
+ *\r
+ * \retval USART_SUCCESS  The character was read successfully.\r
+ * \retval USART_RX_EMPTY The RX buffer was empty.\r
+ * \retval USART_RX_ERROR An error was deteceted.\r
+ */\r
+extern int usart_read_char(volatile avr32_usart_t *usart, int *c);\r
+\r
+/*! \brief Waits until a character is received, and returns it.\r
+ *\r
+ * \param usart   Base address of the USART instance.\r
+ *\r
+ * \return The received character, or \ref USART_FAILURE upon error.\r
+ */\r
+extern int usart_getchar(volatile avr32_usart_t *usart);\r
+\r
+/*! \brief Writes one character string to the USART.\r
+ *\r
+ * \param usart   Base address of the USART instance.\r
+ * \param string  String to be written.\r
+ */\r
+extern void usart_write_line(volatile avr32_usart_t *usart, const char *string);\r
+\r
+/*! \brief Gets and echoes characters until end of line.\r
+ *\r
+ * \param usart   Base address of the USART instance.\r
+ *\r
+ * \retval USART_SUCCESS  Success.\r
+ * \retval USART_FAILURE  Low-level error detected or ETX character received.\r
+ */\r
+extern int usart_get_echo_line(volatile avr32_usart_t *usart);\r
+\r
+#if defined(AVR32_USART_400_H_INCLUDED) || \\r
+    defined(AVR32_USART_410_H_INCLUDED) || \\r
+    defined(AVR32_USART_420_H_INCLUDED) || \\r
+    defined(AVR32_USART_440_H_INCLUDED) || \\r
+    defined(AVR32_USART_602_H_INCLUDED)\r
+\r
+/*! \brief Abort LIN transmission.\r
+ *\r
+ * \param usart   Base address of the USART instance.\r
+ */\r
+#if (defined __GNUC__)\r
+__attribute__((__always_inline__))\r
+#endif\r
+extern __inline__ void usart_lin_abort(volatile avr32_usart_t *usart)\r
+{\r
+  usart->cr = AVR32_USART_LINABT_MASK;\r
+}\r
+\r
+/*! \brief Tests if a LIN transfer has been completed.\r
+ *\r
+ * \param usart   Base address of the USART instance.\r
+ *\r
+ * \return \c 1 if a LIN transfer has been completed, otherwise \c 0.\r
+ */\r
+#if (defined __GNUC__)\r
+__attribute__((__always_inline__))\r
+#endif\r
+extern __inline__ int usart_lin_transfer_completed(volatile avr32_usart_t *usart)\r
+{\r
+  return (usart->csr & AVR32_USART_CSR_LINTC_MASK) != 0;\r
+}\r
+\r
+#endif  // USART rev. >= 4.0.0\r
+\r
+//! @}\r
+\r
+\r
+#endif  // _USART_H_\r

diff --git a/Demo/AVR32_UC3A_GCC/Atmel_SW_Framework/UTILS/LIBS/NEWLIB_ADDONS/INCLUDE/nlao_cpu.h b/Demo/AVR32_UC3A_GCC/Atmel_SW_Framework/UTILS/LIBS/NEWLIB_ADDONS/INCLUDE/nlao_cpu.h
new file mode 100644 (file)
index 0000000..101c9df
--- /dev/null
+++ b/Demo/AVR32_UC3A_GCC/Atmel_SW_Framework/UTILS/LIBS/NEWLIB_ADDONS/INCLUDE/nlao_cpu.h
@@ -0,0 +1,63 @@
+/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */\r
+
+/*This file is prepared for Doxygen automatic documentation generation.*/\r
+/*! \file *********************************************************************\r
+ *\r
+ * \brief NEWLIB_ADDONS CPU include file for AVR32.\r
+ *\r
+ * - Compiler:           GNU GCC for AVR32\r
+ * - Supported devices:  All AVR32 devices can be used.\r
+ * - AppNote:\r
+ *\r
+ * \author               Atmel Corporation: http://www.atmel.com \n\r
+ *                       Support and FAQ: http://support.atmel.no/\r
+ *\r
+ ******************************************************************************/\r
+\r
+/* Copyright (c) 2009 Atmel Corporation. All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice, this\r
+ * list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an Atmel\r
+ * AVR product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\r
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\r
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\r
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE\r
+ *\r
+ */\r
+\r
+#ifndef __AVR32_NEWLIB_ADDONS_CPU_H__\r
+#define __AVR32_NEWLIB_ADDONS_CPU_H__\r
+\r
+#include <_ansi.h>\r
+\r
+_BEGIN_STD_C\r
+\r
+#define CPU_HZ get_cpu_hz()\r
+\r
+void udelay(unsigned long usec);\r
+void set_cpu_hz(unsigned int clk_hz);\r
+unsigned int get_cpu_hz();\r
+\r
+_END_STD_C\r
+\r
+#endif\r

diff --git a/Demo/AVR32_UC3A_GCC/Atmel_SW_Framework/UTILS/LIBS/NEWLIB_ADDONS/INCLUDE/nlao_exceptions.h b/Demo/AVR32_UC3A_GCC/Atmel_SW_Framework/UTILS/LIBS/NEWLIB_ADDONS/INCLUDE/nlao_exceptions.h
new file mode 100644 (file)
index 0000000..6e9168c
--- /dev/null
+++ b/Demo/AVR32_UC3A_GCC/Atmel_SW_Framework/UTILS/LIBS/NEWLIB_ADDONS/INCLUDE/nlao_exceptions.h
@@ -0,0 +1,120 @@
+/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */\r
+
+/*This file is prepared for Doxygen automatic documentation generation.*/\r
+/*! \file *********************************************************************\r
+ *\r
+ * \brief NEWLIB_ADDONS exceptions include file for AVR32.\r
+ *\r
+ * - Compiler:           GNU GCC for AVR32\r
+ * - Supported devices:  All AVR32 devices can be used.\r
+ * - AppNote:\r
+ *\r
+ * \author               Atmel Corporation: http://www.atmel.com \n\r
+ *                       Support and FAQ: http://support.atmel.no/\r
+ *\r
+ ******************************************************************************/\r
+\r
+/* Copyright (c) 2009 Atmel Corporation. All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice, this\r
+ * list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an Atmel\r
+ * AVR product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\r
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\r
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\r
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE\r
+ *\r
+ */\r
+\r
+#ifndef __AVR32_NEWLIB_ADDONS_EXCEPTIONS_H__\r
+#define __AVR32_NEWLIB_ADDONS_EXCEPTIONS_H__\r
+\r
+#include <_ansi.h>\r
+\r
+_BEGIN_STD_C\r
+\r
+/*\r
+ Exception vector offsets\r
+*/\r
+#define EVBA_UNRECOVERABLE    0x000\r
+#define EVBA_TLB_MULTIPLE     0x004\r
+#define EVBA_BUS_ERROR_DATA   0x008\r
+#define EVBA_BUS_ERROR_INSTR  0x00C\r
+#define EVBA_NMI              0x010\r
+#define EVBA_INSTR_ADDR       0x014\r
+#define EVBA_ITLB_MISS        0x050\r
+#define EVBA_ITLB_PROT        0x018\r
+#define EVBA_BREAKPOINT       0x01C\r
+#define EVBA_ILLEGAL_OPCODE   0x020\r
+#define EVBA_UNIMPLEMENTED    0x024\r
+#define EVBA_PRIVILEGE_VIOL   0x028\r
+#define EVBA_FLOATING_POINT   0x02C\r
+#define EVBA_COP_ABSENT       0x030\r
+#define EVBA_SCALL            0x100\r
+#define EVBA_DATA_ADDR_R      0x034\r
+#define EVBA_DATA_ADDR_W      0x038\r
+#define EVBA_DTLB_MISS_R      0x060\r
+#define EVBA_DTLB_MISS_W      0x070\r
+#define EVBA_DTLB_PROT_R      0x03C\r
+#define EVBA_DTLB_PROT_W      0x040\r
+#define EVBA_DTLB_MODIFIED    0x044\r
+\r
+\r
+/*\r
+   Define the form of the function used when registering exceptions.\r
+   The function should return the address which the exception should\r
+   return to after the exception processing.\r
+*/\r
+\r
+typedef unsigned int (*__exception_handler)(int /*evba_offset*/, int /*return address*/);\r
+\r
+/*\r
+   Define the form of the function used when registering a scall handler.\r
+*/\r
+\r
+typedef void (*__scall_handler)(int /*code*/, int /*p1*/, int /*p2*/\r
+                                         , int /*p3*/, int /*p4*/);\r
+\r
+/*\r
+   Function for registering an exception handler for the exception with\r
+   offset given by evba_offset.\r
+*/\r
+void _register_exception_handler(__exception_handler handler, int evba_offset);\r
+\r
+/*\r
+   Function for registering a scall handler which can be a arbirary\r
+   function which uses r8-r12 for parameters.\r
+*/\r
+void _register_scall_handler(__scall_handler handler);\r
+\r
+/*\r
+   Initialize exceptions. Must be called before registering exception handlers\r
+   and needed to enable exceptions. 'evba' is the pointer to the exception\r
+   vector. 'handler_table' is a pointer to an array where the pointers to\r
+   the exception handlers are stored. This array must be at least 0x104 bytes\r
+   and word aligned.\r
+*/\r
+void init_exceptions(void *evba, void *handler_table);\r
+\r
+_END_STD_C\r
+\r
+#endif\r

diff --git a/Demo/AVR32_UC3A_GCC/Atmel_SW_Framework/UTILS/LIBS/NEWLIB_ADDONS/INCLUDE/nlao_interrupts.h b/Demo/AVR32_UC3A_GCC/Atmel_SW_Framework/UTILS/LIBS/NEWLIB_ADDONS/INCLUDE/nlao_interrupts.h
new file mode 100644 (file)
index 0000000..057c005
--- /dev/null
+++ b/Demo/AVR32_UC3A_GCC/Atmel_SW_Framework/UTILS/LIBS/NEWLIB_ADDONS/INCLUDE/nlao_interrupts.h
@@ -0,0 +1,82 @@
+/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */\r
+
+/*This file is prepared for Doxygen automatic documentation generation.*/\r
+/*! \file *********************************************************************\r
+ *\r
+ * \brief NEWLIB_ADDONS interrupts include file for AVR32.\r
+ *\r
+ * - Compiler:           GNU GCC for AVR32\r
+ * - Supported devices:  All AVR32 devices can be used.\r
+ * - AppNote:\r
+ *\r
+ * \author               Atmel Corporation: http://www.atmel.com \n\r
+ *                       Support and FAQ: http://support.atmel.no/\r
+ *\r
+ ******************************************************************************/\r
+\r
+/* Copyright (c) 2009 Atmel Corporation. All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice, this\r
+ * list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an Atmel\r
+ * AVR product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\r
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\r
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\r
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE\r
+ *\r
+ */\r
+\r
+#ifndef __AVR32_NEWLIB_ADDONS_INTERRUPTS_H__\r
+#define __AVR32_NEWLIB_ADDONS_INTERRUPTS_H__\r
+\r
+#include <_ansi.h>\r
+\r
+_BEGIN_STD_C\r
+\r
+#define INT_GRPS          64\r
+#define INT_LINES         32\r
+#define INTPR_BASE        (__intc_base__ + 0x0000)\r
+#define INTREQ_BASE       (__intc_base__ + 64*4)\r
+#define INTCAUSE_BASE     (__intc_base__ + 2*64*4)\r
+\r
+//Register offsets\r
+#define INTLEVEL          30\r
+#define AUTOVECTOR        0\r
+#define AUTOVECTOR_BITS   14\r
+\r
+//Priorities\r
+#define INT0              0\r
+#define INT1              1\r
+#define INT2              2\r
+#define INT3              3\r
+\r
+\r
+typedef void (*__newlib_int_handler)(int /* int_grp*/, void */*user_handle*/);\r
+\r
+__newlib_int_handler register_interrupt(__newlib_int_handler handler, int int_grp, int line, int priority,\r
+                                 .../* void *user_handle*/);\r
+void init_interrupts();\r
+void set_interrupts_base(void *base);\r
+\r
+_END_STD_C\r
+\r
+#endif\r

diff --git a/Demo/AVR32_UC3A_GCC/Atmel_SW_Framework/UTILS/LIBS/NEWLIB_ADDONS/INCLUDE/nlao_io.h b/Demo/AVR32_UC3A_GCC/Atmel_SW_Framework/UTILS/LIBS/NEWLIB_ADDONS/INCLUDE/nlao_io.h
new file mode 100644 (file)
index 0000000..2e515c6
--- /dev/null
+++ b/Demo/AVR32_UC3A_GCC/Atmel_SW_Framework/UTILS/LIBS/NEWLIB_ADDONS/INCLUDE/nlao_io.h
@@ -0,0 +1,174 @@
+/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */\r
+
+/*This file is prepared for Doxygen automatic documentation generation.*/\r
+/*! \file *********************************************************************\r
+ *\r
+ * \brief NEWLIB_ADDONS miscellaneous macros include file for AVR32.\r
+ *\r
+ * - Compiler:           GNU GCC for AVR32\r
+ * - Supported devices:  All AVR32 devices can be used.\r
+ * - AppNote:\r
+ *\r
+ * \author               Atmel Corporation: http://www.atmel.com \n\r
+ *                       Support and FAQ: http://support.atmel.no/\r
+ *\r
+ ******************************************************************************/\r
+\r
+/* Copyright (c) 2009 Atmel Corporation. All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice, this\r
+ * list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an Atmel\r
+ * AVR product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\r
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\r
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\r
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE\r
+ *\r
+ */\r
+\r
+#ifndef __AVR32_NEWLIB_ADDONS_IO_H__\r
+#define __AVR32_NEWLIB_ADDONS_IO_H__\r
+\r
+#include <_ansi.h>\r
+\r
+_BEGIN_STD_C\r
+\r
+typedef char u8;\r
+typedef unsigned int u32;\r
+\r
+#define __raw_writeb(v,a)       (*(volatile unsigned char  *)(a) = (v))\r
+#define __raw_writew(v,a)       (*(volatile unsigned short *)(a) = (v))\r
+#define __raw_writel(v,a)       (*(volatile unsigned int   *)(a) = (v))\r
+\r
+#define __raw_readb(a)          (*(volatile unsigned char  *)(a))\r
+#define __raw_readw(a)          (*(volatile unsigned short *)(a))\r
+#define __raw_readl(a)          (*(volatile unsigned int   *)(a))\r
+\r
+/* As long as I/O is only performed in P4 (or possibly P3), we're safe */\r
+#define writeb(v,a)            __raw_writeb(v,a)\r
+#define writew(v,a)            __raw_writew(v,a)\r
+#define writel(v,a)            __raw_writel(v,a)\r
+\r
+#define readb(a)               __raw_readb(a)\r
+#define readw(a)               __raw_readw(a)\r
+#define readl(a)               __raw_readl(a)\r
+\r
+/* Memory segments when segmentation is enabled */\r
+#define P0SEG          0x00000000\r
+#define P1SEG          0x80000000\r
+#define P2SEG          0xa0000000\r
+#define P3SEG          0xc0000000\r
+#define P4SEG          0xe0000000\r
+\r
+/* Returns the privileged segment base of a given address */\r
+#define PXSEG(a)       (((unsigned long)(a)) & 0xe0000000)\r
+\r
+/* Returns the physical address of a PnSEG (n=1,2) address */\r
+#define PHYSADDR(a)    (((unsigned long)(a)) & 0x1fffffff)\r
+\r
+/*\r
+ * Map an address to a certain privileged segment\r
+ */\r
+#define P1SEGADDR(a) ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P1SEG))\r
+#define P2SEGADDR(a) ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P2SEG))\r
+#define P3SEGADDR(a) ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P3SEG))\r
+#define P4SEGADDR(a) ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P4SEG))\r
+\r
+\r
+#define cached(addr) P1SEGADDR(addr)\r
+#define uncached(addr) P2SEGADDR(addr)\r
+#define physaddr(addr) PHYSADDR(addr)\r
+\r
+#define BF(field, value) \\r
+  ({ union { \\r
+      struct { \\r
+       unsigned           : 32 - field ##  _OFFSET -  field ##  _SIZE ; \\r
+       unsigned long __val: field ##  _SIZE ; \\r
+      }; \\r
+      unsigned long __ul; \\r
+     } __tmp; \\r
+     __tmp.__ul = 0; \\r
+     __tmp.__val = value; \\r
+     __tmp.__ul;})\r
+\r
+#define BF_D(field, value) \\r
+  ({ union { \\r
+      struct { \\r
+       unsigned long long : 64 - field ##  _OFFSET -  field ##  _SIZE ; \\r
+       unsigned long long __val: field ##  _SIZE ; \\r
+      }; \\r
+      unsigned long long __ul; \\r
+     } __tmp; \\r
+     __tmp.__ul = 0; \\r
+     __tmp.__val = value; \\r
+     __tmp.__ul;})\r
+\r
+#define BFINS(var, field, value) \\r
+  { union {\\r
+      struct { \\r
+       unsigned           : 32 - field ##  _OFFSET -  field ##  _SIZE ; \\r
+       unsigned long __val: field ##  _SIZE ; \\r
+      }; \\r
+      unsigned long __ul; \\r
+     } __tmp; \\r
+     __tmp.__ul = var; \\r
+     __tmp.__val = value; \\r
+     var = __tmp.__ul;}\r
+\r
+#define BFEXT(var, field) \\r
+  ({ union {\\r
+      struct { \\r
+       unsigned           : 32 - field ##  _OFFSET -  field ##  _SIZE ; \\r
+       unsigned long __val: field ##  _SIZE ; \\r
+      }; \\r
+      unsigned long __ul; \\r
+     } __tmp; \\r
+     __tmp.__ul = var; \\r
+     __tmp.__val; })\r
+\r
+#define BFINS_D(var, field, value) \\r
+  { union {\\r
+      struct { \\r
+       unsigned long long : 64 - field ##  _OFFSET -  field ##  _SIZE ; \\r
+       unsigned long long __val: field ##  _SIZE ; \\r
+      }; \\r
+      unsigned long long __ul; \\r
+     } __tmp; \\r
+     __tmp.__ul = var; \\r
+     __tmp.__val = value; \\r
+     var = __tmp.__ul;}\r
+\r
+#define BFEXT_D(var, field) \\r
+  ({ union {\\r
+      struct { \\r
+       unsigned long long : 64 - field ##  _OFFSET -  field ##  _SIZE ; \\r
+       unsigned long long __val: field ##  _SIZE ; \\r
+      }; \\r
+      unsigned long long __ul; \\r
+     } __tmp; \\r
+     __tmp.__ul = var; \\r
+     __tmp.__val; })\r
+\r
+\r
+_END_STD_C\r
+\r
+#endif\r

diff --git a/Demo/AVR32_UC3A_GCC/Atmel_SW_Framework/UTILS/LIBS/NEWLIB_ADDONS/INCLUDE/nlao_usart.h b/Demo/AVR32_UC3A_GCC/Atmel_SW_Framework/UTILS/LIBS/NEWLIB_ADDONS/INCLUDE/nlao_usart.h
new file mode 100644 (file)
index 0000000..36d3cab
--- /dev/null
+++ b/Demo/AVR32_UC3A_GCC/Atmel_SW_Framework/UTILS/LIBS/NEWLIB_ADDONS/INCLUDE/nlao_usart.h
@@ -0,0 +1,208 @@
+/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */\r
+
+/*This file is prepared for Doxygen automatic documentation generation.*/\r
+/*! \file *********************************************************************\r
+ *\r
+ * \brief NEWLIB_ADDONS USART include file for AVR32.\r
+ *\r
+ * - Compiler:           GNU GCC for AVR32\r
+ * - Supported devices:  All AVR32 devices can be used.\r
+ * - AppNote:\r
+ *\r
+ * \author               Atmel Corporation: http://www.atmel.com \n\r
+ *                       Support and FAQ: http://support.atmel.no/\r
+ *\r
+ ******************************************************************************/\r
+\r
+/* Copyright (c) 2009 Atmel Corporation. All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice, this\r
+ * list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an Atmel\r
+ * AVR product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\r
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\r
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\r
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE\r
+ *\r
+ */\r
+\r
+#ifndef __AVR32_NEWLIB_ADDONS_USART_H__\r
+#define __AVR32_NEWLIB_ADDONS_USART_H__\r
+\r
+#include <_ansi.h>\r
+\r
+#include "nlao_io.h"\r
+\r
+_BEGIN_STD_C\r
+\r
+struct usart3 {\r
+       volatile u32    us_cr;\r
+       volatile u32    us_mr;\r
+       volatile u32    us_ier;\r
+       volatile u32    us_idr;\r
+       volatile u32    us_imr;\r
+       volatile u32    us_csr;\r
+       volatile u32    us_rhr;\r
+       volatile u32    us_thr;\r
+       volatile u32    us_brgr;\r
+       volatile u32    us_rtor;\r
+       volatile u32    us_ttgr;\r
+       volatile u32    us_reserved[5];\r
+       volatile u32    us_fidi;\r
+       volatile u32    us_ner;\r
+       volatile u32    us_xxr;\r
+       volatile u32    us_if;\r
+};\r
+\r
+/* Register offsets */\r
+#define US_CR                  0x0000\r
+#define US_MR                  0x0004\r
+#define US_IER                 0x0008\r
+#define US_IDR                 0x000c\r
+#define US_IMR                 0x0010\r
+#define US_CSR                 0x0014\r
+#define US_RHR                 0x0018\r
+#define US_THR                 0x001c\r
+#define US_BRGR                        0x0020\r
+#define US_RTOR                        0x0024\r
+#define US_TTGR                        0x0028\r
+\r
+#define US_FIDI                        0x0040\r
+#define US_NER                 0x0044\r
+#define US_XXR                 0x0048\r
+#define US_IF                  0x004c\r
+\r
+#define US_RPR                  0x0100\r
+#define US_RCR                  0x0104\r
+#define US_TPR                  0x0108\r
+#define US_TCR                  0x010c\r
+#define US_RNPR                 0x0110\r
+#define US_RNCR                 0x0114\r
+#define US_TNPR                 0x0118\r
+#define US_TNCR                 0x011c\r
+#define US_PTCR                 0x0120\r
+#define US_PTSR                 0x0124\r
+\r
+\r
+\r
+\r
+/* USART3 Control Register */\r
+#define US_CR_RSTRX            (1 <<  2)\r
+#define US_CR_RSTTX            (1 <<  3)\r
+#define US_CR_RXEN             (1 <<  4)\r
+#define US_CR_RXDIS            (1 <<  5)\r
+#define US_CR_TXEN             (1 <<  6)\r
+#define US_CR_TXDIS            (1 <<  7)\r
+#define US_CR_RSTSTA           (1 <<  8)\r
+#define US_CR_STTBRK           (1 <<  9)\r
+#define US_CR_STPBRK           (1 << 10)\r
+\r
+#define US_CR_DTREN            (1 << 16)\r
+#define US_CR_DTRDIS           (1 << 17)\r
+#define US_CR_RTSEN            (1 << 18)\r
+#define US_CR_RTSDIS           (1 << 19)\r
+\r
+/* USART3 Mode Register */\r
+#define US_MR_MODE             (15 <<  0)\r
+#define US_MR_MODE_NORMAL      ( 0 <<  0)\r
+#define US_MR_MODE_HWFLOW      ( 2 <<  0)\r
+#define US_MR_CLKS             ( 3 <<  4)\r
+#define US_MR_CLKS_CLOCK       ( 0 <<  4)\r
+#define US_MR_CLKS_FDIV1       ( 1 <<  4)\r
+#define US_MR_CLKS_SLOW                ( 2 <<  4)\r
+#define US_MR_CLKS_EXT         ( 3 <<  4)\r
+#define US_MR_CHRL_5BITS       ( 0 <<  6)\r
+#define US_MR_CHRL_6BITS       ( 1 <<  6)\r
+#define US_MR_CHRL_7BITS       ( 2 <<  6)\r
+#define US_MR_CHRL_8BITS       ( 3 <<  6)\r
+#define US_MR_SYNC             ( 1 <<  8)\r
+#define US_MR_PAR_EVEN         ( 0 <<  9)\r
+#define US_MR_PAR_ODD          ( 1 <<  9)\r
+#define US_MR_PAR_SPACE                ( 2 <<  9)\r
+#define US_MR_PAR_MARK         ( 3 <<  9)\r
+#define US_MR_PAR_NONE         ( 4 <<  9)\r
+#define US_MR_PAR_MDROP                ( 6 <<  9)\r
+#define US_MR_NBSTOP_1BIT      ( 0 << 12)\r
+#define US_MR_NBSTOP_1_5BIT    ( 1 << 12)\r
+#define US_MR_NBSTOP_2BITS     ( 2 << 12)\r
+#define US_MR_OVER             ( 1 << 19)\r
+#define US_MR_OVER_X16         ( 0 << 19)\r
+#define US_MR_OVER_X8          ( 1 << 19)\r
+\r
+/* USART3 Channel Status Register */\r
+#define US_CSR_RXRDY           (1 <<  0)\r
+#define US_CSR_TXRDY           (1 <<  1)\r
+#define US_CSR_RXBRK           (1 <<  2)\r
+#define US_CSR_ENDRX           (1 <<  3)\r
+#define US_CSR_ENDTX           (1 <<  4)\r
+\r
+\r
+#define US_CSR_OVRE            (1 <<  5)\r
+#define US_CSR_FRAME           (1 <<  6)\r
+#define US_CSR_PARE            (1 <<  7)\r
+\r
+#define US_CSR_TXEMPTY         (1 <<  9)\r
+\r
+#define US_CSR_TXBUFE           (1 << 11)\r
+#define US_CSR_RXBUFF           (1 << 12)\r
+#define US_CSR_RIIC            (1 << 16)\r
+#define US_CSR_DSRIC           (1 << 17)\r
+#define US_CSR_DCDIC           (1 << 18)\r
+#define US_CSR_CTSIC           (1 << 19)\r
+#define US_CSR_RI              (1 << 20)\r
+#define US_CSR_DSR             (1 << 21)\r
+#define US_CSR_DCD             (1 << 22)\r
+#define US_CSR_CTS             (1 << 23)\r
+\r
+/* USART3 Baud Rate Generator Register */\r
+#define US_BRGR_CD_OFFSET      0\r
+#define US_BRGR_FP_OFFSET      16\r
+\r
+#define US_BRGR_CD_SIZE                16\r
+#define US_BRGR_FP_SIZE                3\r
+\r
+#define US_BRGR_CD             (0xFFFF <<  0)\r
+#define US_BRGR_FP             (     7 << 16)\r
+\r
+/*USART3 PDC Transfer Control Register */\r
+#define US_PTCR_RXTEN           (1 << 0)\r
+#define US_PTCR_RXTDIS          (1 << 1)\r
+#define US_PTCR_TXTEN           (1 << 8)\r
+#define US_PTCR_TXTDIS          (1 << 9)\r
+\r
+/*USART3 PDC Transfer Status Register */\r
+#define US_PTSR_RXTEN           (1 << 0)\r
+#define US_PTSR_TXTEN           (1 << 8)\r
+\r
+\r
+int usart_init(int baudrate);\r
+void usart_putc(char c);\r
+void usart_puts(const char *s);\r
+int usart_getc(void);\r
+int usart_tstc(void);\r
+void usart_setbrg(int baudrate, int cpu_clock);\r
+void set_usart_base(void *usart_base);\r
+\r
+\r
+_END_STD_C\r
+\r
+#endif /* MERLIN_USART3_H */\r

diff --git a/Demo/AVR32_UC3A_GCC/Atmel_SW_Framework/UTILS/LINKER_SCRIPTS/AT32UC3A/0128/GCC/link_uc3a0128.lds b/Demo/AVR32_UC3A_GCC/Atmel_SW_Framework/UTILS/LINKER_SCRIPTS/AT32UC3A/0128/GCC/link_uc3a0128.lds
new file mode 100644 (file)
index 0000000..9ede0e3
--- /dev/null
+++ b/Demo/AVR32_UC3A_GCC/Atmel_SW_Framework/UTILS/LINKER_SCRIPTS/AT32UC3A/0128/GCC/link_uc3a0128.lds
@@ -0,0 +1,266 @@
+/******************************************************************************
+ * AVR32 AT32UC3A0128 GNU LD script file.
+ *
+ * - Compiler:           GNU GCC for AVR32
+ * - Supported devices:  AVR32 AT32UC3A0128
+ *
+ * - author              Atmel Corporation: http://www.atmel.com \n
+ *                       Support and FAQ: http://support.atmel.no/
+ *
+ ******************************************************************************/
+
+/* Copyright (c) 2009 Atmel Corporation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an Atmel
+ * AVR product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
+ *
+ */
+
+OUTPUT_FORMAT("elf32-avr32", "elf32-avr32", "elf32-avr32")
+
+OUTPUT_ARCH(avr32:uc)
+
+ENTRY(_start)
+
+MEMORY
+{
+  FLASH (rxai!w) : ORIGIN = 0x80000000, LENGTH = 0x00020000
+  INTRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0x00007FFC
+  USERPAGE : ORIGIN = 0x80800000, LENGTH = 0x00000200
+}
+
+PHDRS
+{
+  FLASH PT_LOAD;
+  INTRAM_ALIGN PT_NULL;
+  INTRAM_AT_FLASH PT_LOAD;
+  INTRAM PT_NULL;
+  USERPAGE PT_LOAD;
+}
+
+SECTIONS
+{
+  /* If this heap size is selected, all the INTRAM space from the end of the
+     data area to the beginning of the stack will be allocated for the heap. */
+  __max_heap_size__ = -1;
+
+  /* Use a default heap size if heap size was not defined. */
+  __heap_size__ = DEFINED(__heap_size__) ? __heap_size__ : __max_heap_size__;
+
+  /* Use a default stack size if stack size was not defined. */
+  __stack_size__ = DEFINED(__stack_size__) ? __stack_size__ : 4K;
+
+  /* Read-only sections, merged into text segment: */
+  PROVIDE (__executable_start = 0x80000000); . = 0x80000000;
+  .interp         : { *(.interp) } >FLASH AT>FLASH :FLASH
+  .reset : {  *(.reset) } >FLASH AT>FLASH :FLASH
+  .hash           : { *(.hash) } >FLASH AT>FLASH :FLASH
+  .dynsym         : { *(.dynsym) } >FLASH AT>FLASH :FLASH
+  .dynstr         : { *(.dynstr) } >FLASH AT>FLASH :FLASH
+  .gnu.version    : { *(.gnu.version) } >FLASH AT>FLASH :FLASH
+  .gnu.version_d  : { *(.gnu.version_d) } >FLASH AT>FLASH :FLASH
+  .gnu.version_r  : { *(.gnu.version_r) } >FLASH AT>FLASH :FLASH
+  .rel.init       : { *(.rel.init) } >FLASH AT>FLASH :FLASH
+  .rela.init      : { *(.rela.init) } >FLASH AT>FLASH :FLASH
+  .rel.text       : { *(.rel.text .rel.text.* .rel.gnu.linkonce.t.*) } >FLASH AT>FLASH :FLASH
+  .rela.text      : { *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*) } >FLASH AT>FLASH :FLASH
+  .rel.fini       : { *(.rel.fini) } >FLASH AT>FLASH :FLASH
+  .rela.fini      : { *(.rela.fini) } >FLASH AT>FLASH :FLASH
+  .rel.rodata     : { *(.rel.rodata .rel.rodata.* .rel.gnu.linkonce.r.*) } >FLASH AT>FLASH :FLASH
+  .rela.rodata    : { *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*) } >FLASH AT>FLASH :FLASH
+  .rel.data.rel.ro   : { *(.rel.data.rel.ro*) } >FLASH AT>FLASH :FLASH
+  .rela.data.rel.ro   : { *(.rel.data.rel.ro*) } >FLASH AT>FLASH :FLASH
+  .rel.data       : { *(.rel.data .rel.data.* .rel.gnu.linkonce.d.*) } >FLASH AT>FLASH :FLASH
+  .rela.data      : { *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*) } >FLASH AT>FLASH :FLASH
+  .rel.tdata     : { *(.rel.tdata .rel.tdata.* .rel.gnu.linkonce.td.*) } >FLASH AT>FLASH :FLASH
+  .rela.tdata    : { *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*) } >FLASH AT>FLASH :FLASH
+  .rel.tbss      : { *(.rel.tbss .rel.tbss.* .rel.gnu.linkonce.tb.*) } >FLASH AT>FLASH :FLASH
+  .rela.tbss     : { *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*) } >FLASH AT>FLASH :FLASH
+  .rel.ctors      : { *(.rel.ctors) } >FLASH AT>FLASH :FLASH
+  .rela.ctors     : { *(.rela.ctors) } >FLASH AT>FLASH :FLASH
+  .rel.dtors      : { *(.rel.dtors) } >FLASH AT>FLASH :FLASH
+  .rela.dtors     : { *(.rela.dtors) } >FLASH AT>FLASH :FLASH
+  .rel.got        : { *(.rel.got) } >FLASH AT>FLASH :FLASH
+  .rela.got       : { *(.rela.got) } >FLASH AT>FLASH :FLASH
+  .rel.bss        : { *(.rel.bss .rel.bss.* .rel.gnu.linkonce.b.*) } >FLASH AT>FLASH :FLASH
+  .rela.bss       : { *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*) } >FLASH AT>FLASH :FLASH
+  .rel.plt        : { *(.rel.plt) } >FLASH AT>FLASH :FLASH
+  .rela.plt       : { *(.rela.plt) } >FLASH AT>FLASH :FLASH
+  .init           :
+  {
+    KEEP (*(.init))
+  } >FLASH AT>FLASH :FLASH =0xd703d703
+  .plt            : { *(.plt) } >FLASH AT>FLASH :FLASH
+  .text           :
+  {
+    *(.text .stub .text.* .gnu.linkonce.t.*)
+    KEEP (*(.text.*personality*))
+    /* .gnu.warning sections are handled specially by elf32.em.  */
+    *(.gnu.warning)
+  } >FLASH AT>FLASH :FLASH =0xd703d703
+  .fini           :
+  {
+    KEEP (*(.fini))
+  } >FLASH AT>FLASH :FLASH =0xd703d703
+  PROVIDE (__etext = .);
+  PROVIDE (_etext = .);
+  PROVIDE (etext = .);
+  .rodata         : { *(.rodata .rodata.* .gnu.linkonce.r.*) } >FLASH AT>FLASH :FLASH
+  .rodata1        : { *(.rodata1) } >FLASH AT>FLASH :FLASH
+  .eh_frame_hdr : { *(.eh_frame_hdr) } >FLASH AT>FLASH :FLASH
+  .eh_frame       : ONLY_IF_RO { KEEP (*(.eh_frame)) } >FLASH AT>FLASH :FLASH
+  .gcc_except_table   : ONLY_IF_RO { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) } >FLASH AT>FLASH :FLASH
+  .lalign      : { . = ALIGN(8); PROVIDE(_data_lma = .); } >FLASH AT>FLASH :FLASH
+  . = ORIGIN(INTRAM);
+  .dalign      : { . = ALIGN(8); PROVIDE(_data = .); } >INTRAM AT>INTRAM :INTRAM_ALIGN
+  /* Exception handling  */
+  .eh_frame       : ONLY_IF_RW { KEEP (*(.eh_frame)) } >INTRAM AT>FLASH :INTRAM_AT_FLASH
+  .gcc_except_table   : ONLY_IF_RW { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) } >INTRAM AT>FLASH :INTRAM_AT_FLASH
+  /* Thread Local Storage sections  */
+  .tdata         : { *(.tdata .tdata.* .gnu.linkonce.td.*) } >INTRAM AT>FLASH :INTRAM_AT_FLASH
+  .tbss                  : { *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) } >INTRAM AT>FLASH :INTRAM_AT_FLASH
+  /* Ensure the __preinit_array_start label is properly aligned.  We
+     could instead move the label definition inside the section, but
+     the linker would then create the section even if it turns out to
+     be empty, which isn't pretty.  */
+  PROVIDE (__preinit_array_start = ALIGN(32 / 8));
+  .preinit_array     : { KEEP (*(.preinit_array)) } >INTRAM AT>FLASH :INTRAM_AT_FLASH
+  PROVIDE (__preinit_array_end = .);
+  PROVIDE (__init_array_start = .);
+  .init_array     : { KEEP (*(.init_array)) } >INTRAM AT>FLASH :INTRAM_AT_FLASH
+  PROVIDE (__init_array_end = .);
+  PROVIDE (__fini_array_start = .);
+  .fini_array     : { KEEP (*(.fini_array)) } >INTRAM AT>FLASH :INTRAM_AT_FLASH
+  PROVIDE (__fini_array_end = .);
+  .ctors          :
+  {
+    /* gcc uses crtbegin.o to find the start of
+       the constructors, so we make sure it is
+       first.  Because this is a wildcard, it
+       doesn't matter if the user does not
+       actually link against crtbegin.o; the
+       linker won't look for a file to match a
+       wildcard.  The wildcard also means that it
+       doesn't matter which directory crtbegin.o
+       is in.  */
+    KEEP (*crtbegin*.o(.ctors))
+    /* We don't want to include the .ctor section from
+       from the crtend.o file until after the sorted ctors.
+       The .ctor section from the crtend file contains the
+       end of ctors marker and it must be last */
+    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .ctors))
+    KEEP (*(SORT(.ctors.*)))
+    KEEP (*(.ctors))
+  } >INTRAM AT>FLASH :INTRAM_AT_FLASH
+  .dtors          :
+  {
+    KEEP (*crtbegin*.o(.dtors))
+    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .dtors))
+    KEEP (*(SORT(.dtors.*)))
+    KEEP (*(.dtors))
+  } >INTRAM AT>FLASH :INTRAM_AT_FLASH
+  .jcr            : { KEEP (*(.jcr)) } >INTRAM AT>FLASH :INTRAM_AT_FLASH
+  .data.rel.ro : { *(.data.rel.ro.local) *(.data.rel.ro*) } >INTRAM AT>FLASH :INTRAM_AT_FLASH
+  .dynamic        : { *(.dynamic) } >INTRAM AT>FLASH :INTRAM_AT_FLASH
+  .got            : { *(.got.plt) *(.got) } >INTRAM AT>FLASH :INTRAM_AT_FLASH
+  .ramtext        : { *(.ramtext .ramtext.*) } >INTRAM AT>FLASH :INTRAM_AT_FLASH
+  .ddalign     : { . = ALIGN(8); } >INTRAM AT>FLASH :INTRAM_AT_FLASH
+  .data           :
+  {
+    *(.data .data.* .gnu.linkonce.d.*)
+    KEEP (*(.gnu.linkonce.d.*personality*))
+    SORT(CONSTRUCTORS)
+  } >INTRAM AT>FLASH :INTRAM_AT_FLASH
+  .data1          : { *(.data1) } >INTRAM AT>FLASH :INTRAM_AT_FLASH
+  .balign      : { . = ALIGN(8); PROVIDE(_edata = .); } >INTRAM AT>FLASH :INTRAM_AT_FLASH
+  PROVIDE (edata = .);
+  __bss_start = .;
+  .bss            :
+  {
+    *(.dynbss)
+    *(.bss .bss.* .gnu.linkonce.b.*)
+    *(COMMON)
+    /* Align here to ensure that the .bss section occupies space up to
+       _end.  Align after .bss to ensure correct alignment even if the
+       .bss section disappears because there are no input sections.  */
+    . = ALIGN(8);
+  } >INTRAM AT>INTRAM :INTRAM
+  . = ALIGN(8);
+  _end = .;
+  PROVIDE (end = .);
+  __heap_start__ = ALIGN(8);
+  .heap           :
+  {
+    *(.heap)
+    . = (__heap_size__ == __max_heap_size__) ?
+        ORIGIN(INTRAM) + LENGTH(INTRAM) - __stack_size__ - ABSOLUTE(.) :
+        __heap_size__;
+  } >INTRAM AT>INTRAM :INTRAM
+  __heap_end__ = .;
+  /* Stabs debugging sections.  */
+  .stab          0 : { *(.stab) }
+  .stabstr       0 : { *(.stabstr) }
+  .stab.excl     0 : { *(.stab.excl) }
+  .stab.exclstr  0 : { *(.stab.exclstr) }
+  .stab.index    0 : { *(.stab.index) }
+  .stab.indexstr 0 : { *(.stab.indexstr) }
+  .comment       0 : { *(.comment) }
+  /* DWARF debug sections.
+     Symbols in the DWARF debugging sections are relative to the beginning
+     of the section so we begin them at 0.  */
+  /* DWARF 1 */
+  .debug          0 : { *(.debug) }
+  .line           0 : { *(.line) }
+  /* GNU DWARF 1 extensions */
+  .debug_srcinfo  0 : { *(.debug_srcinfo) }
+  .debug_sfnames  0 : { *(.debug_sfnames) }
+  /* DWARF 1.1 and DWARF 2 */
+  .debug_aranges  0 : { *(.debug_aranges) }
+  .debug_pubnames 0 : { *(.debug_pubnames) }
+  /* DWARF 2 */
+  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }
+  .debug_abbrev   0 : { *(.debug_abbrev) }
+  .debug_line     0 : { *(.debug_line) }
+  .debug_frame    0 : { *(.debug_frame) }
+  .debug_str      0 : { *(.debug_str) }
+  .debug_loc      0 : { *(.debug_loc) }
+  .debug_macinfo  0 : { *(.debug_macinfo) }
+  /* SGI/MIPS DWARF 2 extensions */
+  .debug_weaknames 0 : { *(.debug_weaknames) }
+  .debug_funcnames 0 : { *(.debug_funcnames) }
+  .debug_typenames 0 : { *(.debug_typenames) }
+  .debug_varnames  0 : { *(.debug_varnames) }
+  .stack         ORIGIN(INTRAM) + LENGTH(INTRAM) - __stack_size__ :
+  {
+    _stack = .;
+    *(.stack)
+    . = __stack_size__;
+    _estack = .;
+  } >INTRAM AT>INTRAM :INTRAM
+  .userpage       : { *(.userpage .userpage.*) } >USERPAGE AT>USERPAGE :USERPAGE
+  /DISCARD/ : { *(.note.GNU-stack) }
+}

diff --git a/Demo/AVR32_UC3A_GCC/Atmel_SW_Framework/UTILS/LINKER_SCRIPTS/AT32UC3A/0128/IAR/lnkuc3a0128.xcl b/Demo/AVR32_UC3A_GCC/Atmel_SW_Framework/UTILS/LINKER_SCRIPTS/AT32UC3A/0128/IAR/lnkuc3a0128.xcl
new file mode 100644 (file)
index 0000000..104e022
--- /dev/null
+++ b/Demo/AVR32_UC3A_GCC/Atmel_SW_Framework/UTILS/LINKER_SCRIPTS/AT32UC3A/0128/IAR/lnkuc3a0128.xcl
@@ -0,0 +1,153 @@
+/******************************************************************************\r
+ * AVR32 AT32UC3A0128 XLINK command file for AVR32 IAR C/C++ Compiler.\r
+ *\r
+ * The assumed memory layout is the one of the AT32UC3A0128:\r
+ *\r
+ *   Start       Stop        Name     Type\r
+ *   ----------  ----------  -----    --------------\r
+ *   0x00000000  0x00007FFF  SRAM     RAM\r
+ *   0x80000000  0x8001FFFF  FLASH    FLASH\r
+ *   0x80800000  0x808001FF  USER     FLASH\r
+ *\r
+ * Usage:  xlink  your_file(s)  -f xcl-file  libraries\r
+ *\r
+ * - Compiler:           IAR EWAVR32\r
+ * - Supported devices:  AVR32 AT32UC3A0128\r
+ *\r
+ * - author              Atmel Corporation: http://www.atmel.com \n\r
+ *                       Support and FAQ: http://support.atmel.no/\r
+ *\r
+ ******************************************************************************/\r
+\r
+/* Copyright (c) 2009 Atmel Corporation. All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice, this\r
+ * list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an Atmel\r
+ * AVR product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\r
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\r
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\r
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE\r
+ *\r
+ */\r
+\r
+/************************************************************************/\r
+/*      The following segments are defined in this link file:           */\r
+/*                                                                      */\r
+/*      Code segments                                                   */\r
+/*      CODE32    -- Program code used by __code32 functions.           */\r
+/*      RESET     -- Reset code.                                        */\r
+/*      EVSEG     -- Exception vector handlers.                         */\r
+/*                                                                      */\r
+/*      Constant segments                                               */\r
+/*      INITTAB   -- Segment initializer table.                         */\r
+/*      DIFUNCT   -- Dynamic initialization vector used by C++.         */\r
+/*      SWITCH    -- Switch tables.                                     */\r
+/*      ACTAB     -- Table of pointers to acall functions.              */\r
+/*                                                                      */\r
+/*      DATA21_ID -- Initialization data for DATA21_I.                  */\r
+/*      DATA32_ID -- Initialization data for DATA32_I.                  */\r
+/*      DATA32_C  -- Constant __data32 data.                            */\r
+/*                                                                      */\r
+/*      CHECKSUM  -- Checksum segment.                                  */\r
+/*                                                                      */\r
+/*      Data segments                                                   */\r
+/*      DATA21_I  -- Initialized __data21 data with non-zero            */\r
+/*                   initial value.                                     */\r
+/*      DATA32_I  -- Initialized __data32 data with non-zero            */\r
+/*                   initial value.                                     */\r
+/*      DATA21_Z  -- Initialized __data21 data with zero initial value. */\r
+/*      DATA32_Z  -- Initialized __data32 data with zero initial value. */\r
+/*      DATA21_N  -- Non-initialized __data21.                          */\r
+/*      DATA32_N  -- Non-initialized __data32.                          */\r
+/*      SSTACK    -- The system stack.                                  */\r
+/*      CSTACK    -- The application stack.                             */\r
+/*      HEAP      -- The heap used by malloc and free.                  */\r
+/*                                                                      */\r
+/************************************************************************/\r
+\r
+/************************************************************************/\r
+/*      Define CPU                                                      */\r
+/************************************************************************/\r
+\r
+-cavr32\r
+\r
+// Declare the IPR0 memory location\r
+-DIPR0=FFFF0800\r
+\r
+/************************************************************************/\r
+/*      Reset code is located at address 0x80000000 and up.             */\r
+/************************************************************************/\r
+\r
+-Z(CODE)RESET=80000000-8001FFFF\r
+\r
+/************************************************************************/\r
+/*      The exception handler code is located at address 0x80000000     */\r
+/*      and up. Make sure that the exception table gets properly        */\r
+/*      allocated. By using the special -Z@ allocation primitive, the   */\r
+/*      placement is guaranteed to be at _EVBASE and onwards.           */\r
+/************************************************************************/\r
+\r
+-Z@(CODE)EVTAB=80004000-8001FFFF\r
+-Z@(CODE)EV100=80004100-8001FFFF\r
+-P(CODE)EVSEG=80004000-8001FFFF\r
+\r
+/************************************************************************/\r
+/*      Allocate code and const segments.                               */\r
+/************************************************************************/\r
+\r
+-P(CODE)CODE32=80000000-8001FFFF\r
+-P(CONST)DATA32_C=80000000-8001FFFF\r
+-P(CONST)USERDATA32_C=80800000-808001FF\r
+\r
+// Initializers\r
+-Z(CONST)INITTAB,DIFUNCT=80000000-8001FFFF\r
+-Z(CONST)CHECKSUM,SWITCH=80000000-8001FFFF\r
+-Z(CONST)DATA21_ID,DATA32_ID=80000000-8001FFFF\r
+-Z(CONST)RAMCODE21_ID,RAMCODE32_ID=80000000-8001FFFF\r
+\r
+-Z(CONST)ACTAB,HTAB=80000000-8001FFFF\r
+\r
+/************************************************************************/\r
+/*      Allocate the read/write segments that are mapped to RAM.        */\r
+/************************************************************************/\r
+\r
+-Z(CODE)RAMCODE21=00000004-00007FFF\r
+-Z(DATA)DATA21_I,DATA21_Z,DATA21_N=00000004-00007FFF\r
+-Z(CODE)RAMCODE32=00000004-00007FFF\r
+-Z(DATA)DATA32_I,DATA32_Z,DATA32_N=00000004-00007FFF\r
+-Z(DATA)TRACEBUFFER=00000004-00007FFF\r
+\r
+-Z(DATA)SSTACK+_SSTACK_SIZE#00000004-00007FFF\r
+-Z(DATA)CSTACK+_CSTACK_SIZE#00000004-00007FFF\r
+-Z(DATA)HEAP+_HEAP_SIZE=00000004-00007FFF\r
+\r
+/************************************************************************/\r
+/*      Copy the RAMCODE bytes to the initializer segments.             */\r
+/************************************************************************/\r
+\r
+-QRAMCODE21=RAMCODE21_ID\r
+-QRAMCODE32=RAMCODE32_ID\r
+\r
+/************************************************************************/\r
+/*      End of File                                                     */\r
+/************************************************************************/\r

diff --git a/Demo/AVR32_UC3A_GCC/Atmel_SW_Framework/UTILS/LINKER_SCRIPTS/AT32UC3A/0256/GCC/link_uc3a0256.lds b/Demo/AVR32_UC3A_GCC/Atmel_SW_Framework/UTILS/LINKER_SCRIPTS/AT32UC3A/0256/GCC/link_uc3a0256.lds
new file mode 100644 (file)
index 0000000..c1bd0ec
--- /dev/null
+++ b/Demo/AVR32_UC3A_GCC/Atmel_SW_Framework/UTILS/LINKER_SCRIPTS/AT32UC3A/0256/GCC/link_uc3a0256.lds
@@ -0,0 +1,266 @@
+/******************************************************************************
+ * AVR32 AT32UC3A0256 GNU LD script file.
+ *
+ * - Compiler:           GNU GCC for AVR32
+ * - Supported devices:  AVR32 AT32UC3A0256
+ *
+ * - author              Atmel Corporation: http://www.atmel.com \n
+ *                       Support and FAQ: http://support.atmel.no/
+ *
+ ******************************************************************************/
+
+/* Copyright (c) 2009 Atmel Corporation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an Atmel
+ * AVR product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
+ *
+ */
+
+OUTPUT_FORMAT("elf32-avr32", "elf32-avr32", "elf32-avr32")
+
+OUTPUT_ARCH(avr32:uc)
+
+ENTRY(_start)
+
+MEMORY
+{
+  FLASH (rxai!w) : ORIGIN = 0x80000000, LENGTH = 0x00040000
+  INTRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0x0000FFFC
+  USERPAGE : ORIGIN = 0x80800000, LENGTH = 0x00000200
+}
+
+PHDRS
+{
+  FLASH PT_LOAD;
+  INTRAM_ALIGN PT_NULL;
+  INTRAM_AT_FLASH PT_LOAD;
+  INTRAM PT_NULL;
+  USERPAGE PT_LOAD;
+}
+
+SECTIONS
+{
+  /* If this heap size is selected, all the INTRAM space from the end of the
+     data area to the beginning of the stack will be allocated for the heap. */
+  __max_heap_size__ = -1;
+
+  /* Use a default heap size if heap size was not defined. */
+  __heap_size__ = DEFINED(__heap_size__) ? __heap_size__ : __max_heap_size__;
+
+  /* Use a default stack size if stack size was not defined. */
+  __stack_size__ = DEFINED(__stack_size__) ? __stack_size__ : 4K;
+
+  /* Read-only sections, merged into text segment: */
+  PROVIDE (__executable_start = 0x80000000); . = 0x80000000;
+  .interp         : { *(.interp) } >FLASH AT>FLASH :FLASH
+  .reset : {  *(.reset) } >FLASH AT>FLASH :FLASH
+  .hash           : { *(.hash) } >FLASH AT>FLASH :FLASH
+  .dynsym         : { *(.dynsym) } >FLASH AT>FLASH :FLASH
+  .dynstr         : { *(.dynstr) } >FLASH AT>FLASH :FLASH
+  .gnu.version    : { *(.gnu.version) } >FLASH AT>FLASH :FLASH
+  .gnu.version_d  : { *(.gnu.version_d) } >FLASH AT>FLASH :FLASH
+  .gnu.version_r  : { *(.gnu.version_r) } >FLASH AT>FLASH :FLASH
+  .rel.init       : { *(.rel.init) } >FLASH AT>FLASH :FLASH
+  .rela.init      : { *(.rela.init) } >FLASH AT>FLASH :FLASH
+  .rel.text       : { *(.rel.text .rel.text.* .rel.gnu.linkonce.t.*) } >FLASH AT>FLASH :FLASH
+  .rela.text      : { *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*) } >FLASH AT>FLASH :FLASH
+  .rel.fini       : { *(.rel.fini) } >FLASH AT>FLASH :FLASH
+  .rela.fini      : { *(.rela.fini) } >FLASH AT>FLASH :FLASH
+  .rel.rodata     : { *(.rel.rodata .rel.rodata.* .rel.gnu.linkonce.r.*) } >FLASH AT>FLASH :FLASH
+  .rela.rodata    : { *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*) } >FLASH AT>FLASH :FLASH
+  .rel.data.rel.ro   : { *(.rel.data.rel.ro*) } >FLASH AT>FLASH :FLASH
+  .rela.data.rel.ro   : { *(.rel.data.rel.ro*) } >FLASH AT>FLASH :FLASH
+  .rel.data       : { *(.rel.data .rel.data.* .rel.gnu.linkonce.d.*) } >FLASH AT>FLASH :FLASH
+  .rela.data      : { *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*) } >FLASH AT>FLASH :FLASH
+  .rel.tdata     : { *(.rel.tdata .rel.tdata.* .rel.gnu.linkonce.td.*) } >FLASH AT>FLASH :FLASH
+  .rela.tdata    : { *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*) } >FLASH AT>FLASH :FLASH
+  .rel.tbss      : { *(.rel.tbss .rel.tbss.* .rel.gnu.linkonce.tb.*) } >FLASH AT>FLASH :FLASH
+  .rela.tbss     : { *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*) } >FLASH AT>FLASH :FLASH
+  .rel.ctors      : { *(.rel.ctors) } >FLASH AT>FLASH :FLASH
+  .rela.ctors     : { *(.rela.ctors) } >FLASH AT>FLASH :FLASH
+  .rel.dtors      : { *(.rel.dtors) } >FLASH AT>FLASH :FLASH
+  .rela.dtors     : { *(.rela.dtors) } >FLASH AT>FLASH :FLASH
+  .rel.got        : { *(.rel.got) } >FLASH AT>FLASH :FLASH
+  .rela.got       : { *(.rela.got) } >FLASH AT>FLASH :FLASH
+  .rel.bss        : { *(.rel.bss .rel.bss.* .rel.gnu.linkonce.b.*) } >FLASH AT>FLASH :FLASH
+  .rela.bss       : { *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*) } >FLASH AT>FLASH :FLASH
+  .rel.plt        : { *(.rel.plt) } >FLASH AT>FLASH :FLASH
+  .rela.plt       : { *(.rela.plt) } >FLASH AT>FLASH :FLASH
+  .init           :
+  {
+    KEEP (*(.init))
+  } >FLASH AT>FLASH :FLASH =0xd703d703
+  .plt            : { *(.plt) } >FLASH AT>FLASH :FLASH
+  .text           :
+  {
+    *(.text .stub .text.* .gnu.linkonce.t.*)
+    KEEP (*(.text.*personality*))
+    /* .gnu.warning sections are handled specially by elf32.em.  */
+    *(.gnu.warning)
+  } >FLASH AT>FLASH :FLASH =0xd703d703
+  .fini           :
+  {
+    KEEP (*(.fini))
+  } >FLASH AT>FLASH :FLASH =0xd703d703
+  PROVIDE (__etext = .);
+  PROVIDE (_etext = .);
+  PROVIDE (etext = .);
+  .rodata         : { *(.rodata .rodata.* .gnu.linkonce.r.*) } >FLASH AT>FLASH :FLASH
+  .rodata1        : { *(.rodata1) } >FLASH AT>FLASH :FLASH
+  .eh_frame_hdr : { *(.eh_frame_hdr) } >FLASH AT>FLASH :FLASH
+  .eh_frame       : ONLY_IF_RO { KEEP (*(.eh_frame)) } >FLASH AT>FLASH :FLASH
+  .gcc_except_table   : ONLY_IF_RO { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) } >FLASH AT>FLASH :FLASH
+  .lalign      : { . = ALIGN(8); PROVIDE(_data_lma = .); } >FLASH AT>FLASH :FLASH
+  . = ORIGIN(INTRAM);
+  .dalign      : { . = ALIGN(8); PROVIDE(_data = .); } >INTRAM AT>INTRAM :INTRAM_ALIGN
+  /* Exception handling  */
+  .eh_frame       : ONLY_IF_RW { KEEP (*(.eh_frame)) } >INTRAM AT>FLASH :INTRAM_AT_FLASH
+  .gcc_except_table   : ONLY_IF_RW { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) } >INTRAM AT>FLASH :INTRAM_AT_FLASH
+  /* Thread Local Storage sections  */
+  .tdata         : { *(.tdata .tdata.* .gnu.linkonce.td.*) } >INTRAM AT>FLASH :INTRAM_AT_FLASH
+  .tbss                  : { *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) } >INTRAM AT>FLASH :INTRAM_AT_FLASH
+  /* Ensure the __preinit_array_start label is properly aligned.  We
+     could instead move the label definition inside the section, but
+     the linker would then create the section even if it turns out to
+     be empty, which isn't pretty.  */
+  PROVIDE (__preinit_array_start = ALIGN(32 / 8));
+  .preinit_array     : { KEEP (*(.preinit_array)) } >INTRAM AT>FLASH :INTRAM_AT_FLASH
+  PROVIDE (__preinit_array_end = .);
+  PROVIDE (__init_array_start = .);
+  .init_array     : { KEEP (*(.init_array)) } >INTRAM AT>FLASH :INTRAM_AT_FLASH
+  PROVIDE (__init_array_end = .);
+  PROVIDE (__fini_array_start = .);
+  .fini_array     : { KEEP (*(.fini_array)) } >INTRAM AT>FLASH :INTRAM_AT_FLASH
+  PROVIDE (__fini_array_end = .);
+  .ctors          :
+  {
+    /* gcc uses crtbegin.o to find the start of
+       the constructors, so we make sure it is
+       first.  Because this is a wildcard, it
+       doesn't matter if the user does not
+       actually link against crtbegin.o; the
+       linker won't look for a file to match a
+       wildcard.  The wildcard also means that it
+       doesn't matter which directory crtbegin.o
+       is in.  */
+    KEEP (*crtbegin*.o(.ctors))
+    /* We don't want to include the .ctor section from
+       from the crtend.o file until after the sorted ctors.
+       The .ctor section from the crtend file contains the
+       end of ctors marker and it must be last */
+    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .ctors))
+    KEEP (*(SORT(.ctors.*)))
+    KEEP (*(.ctors))
+  } >INTRAM AT>FLASH :INTRAM_AT_FLASH
+  .dtors          :
+  {
+    KEEP (*crtbegin*.o(.dtors))
+    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .dtors))
+    KEEP (*(SORT(.dtors.*)))
+    KEEP (*(.dtors))
+  } >INTRAM AT>FLASH :INTRAM_AT_FLASH
+  .jcr            : { KEEP (*(.jcr)) } >INTRAM AT>FLASH :INTRAM_AT_FLASH
+  .data.rel.ro : { *(.data.rel.ro.local) *(.data.rel.ro*) } >INTRAM AT>FLASH :INTRAM_AT_FLASH
+  .dynamic        : { *(.dynamic) } >INTRAM AT>FLASH :INTRAM_AT_FLASH
+  .got            : { *(.got.plt) *(.got) } >INTRAM AT>FLASH :INTRAM_AT_FLASH
+  .ramtext        : { *(.ramtext .ramtext.*) } >INTRAM AT>FLASH :INTRAM_AT_FLASH
+  .ddalign     : { . = ALIGN(8); } >INTRAM AT>FLASH :INTRAM_AT_FLASH
+  .data           :
+  {
+    *(.data .data.* .gnu.linkonce.d.*)
+    KEEP (*(.gnu.linkonce.d.*personality*))
+    SORT(CONSTRUCTORS)
+  } >INTRAM AT>FLASH :INTRAM_AT_FLASH
+  .data1          : { *(.data1) } >INTRAM AT>FLASH :INTRAM_AT_FLASH
+  .balign      : { . = ALIGN(8); PROVIDE(_edata = .); } >INTRAM AT>FLASH :INTRAM_AT_FLASH
+  PROVIDE (edata = .);
+  __bss_start = .;
+  .bss            :
+  {
+    *(.dynbss)
+    *(.bss .bss.* .gnu.linkonce.b.*)
+    *(COMMON)
+    /* Align here to ensure that the .bss section occupies space up to
+       _end.  Align after .bss to ensure correct alignment even if the
+       .bss section disappears because there are no input sections.  */
+    . = ALIGN(8);
+  } >INTRAM AT>INTRAM :INTRAM
+  . = ALIGN(8);
+  _end = .;
+  PROVIDE (end = .);
+  __heap_start__ = ALIGN(8);
+  .heap           :
+  {
+    *(.heap)
+    . = (__heap_size__ == __max_heap_size__) ?
+        ORIGIN(INTRAM) + LENGTH(INTRAM) - __stack_size__ - ABSOLUTE(.) :
+        __heap_size__;
+  } >INTRAM AT>INTRAM :INTRAM
+  __heap_end__ = .;
+  /* Stabs debugging sections.  */
+  .stab          0 : { *(.stab) }
+  .stabstr       0 : { *(.stabstr) }
+  .stab.excl     0 : { *(.stab.excl) }
+  .stab.exclstr  0 : { *(.stab.exclstr) }
+  .stab.index    0 : { *(.stab.index) }
+  .stab.indexstr 0 : { *(.stab.indexstr) }
+  .comment       0 : { *(.comment) }
+  /* DWARF debug sections.
+     Symbols in the DWARF debugging sections are relative to the beginning
+     of the section so we begin them at 0.  */
+  /* DWARF 1 */
+  .debug          0 : { *(.debug) }
+  .line           0 : { *(.line) }
+  /* GNU DWARF 1 extensions */
+  .debug_srcinfo  0 : { *(.debug_srcinfo) }
+  .debug_sfnames  0 : { *(.debug_sfnames) }
+  /* DWARF 1.1 and DWARF 2 */
+  .debug_aranges  0 : { *(.debug_aranges) }
+  .debug_pubnames 0 : { *(.debug_pubnames) }
+  /* DWARF 2 */
+  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }
+  .debug_abbrev   0 : { *(.debug_abbrev) }
+  .debug_line     0 : { *(.debug_line) }
+  .debug_frame    0 : { *(.debug_frame) }
+  .debug_str      0 : { *(.debug_str) }
+  .debug_loc      0 : { *(.debug_loc) }
+  .debug_macinfo  0 : { *(.debug_macinfo) }
+  /* SGI/MIPS DWARF 2 extensions */
+  .debug_weaknames 0 : { *(.debug_weaknames) }
+  .debug_funcnames 0 : { *(.debug_funcnames) }
+  .debug_typenames 0 : { *(.debug_typenames) }
+  .debug_varnames  0 : { *(.debug_varnames) }
+  .stack         ORIGIN(INTRAM) + LENGTH(INTRAM) - __stack_size__ :
+  {
+    _stack = .;
+    *(.stack)
+    . = __stack_size__;
+    _estack = .;
+  } >INTRAM AT>INTRAM :INTRAM
+  .userpage       : { *(.userpage .userpage.*) } >USERPAGE AT>USERPAGE :USERPAGE
+  /DISCARD/ : { *(.note.GNU-stack) }
+}

diff --git a/Demo/AVR32_UC3A_GCC/Atmel_SW_Framework/UTILS/LINKER_SCRIPTS/AT32UC3A/0256/IAR/lnkuc3a0256.xcl b/Demo/AVR32_UC3A_GCC/Atmel_SW_Framework/UTILS/LINKER_SCRIPTS/AT32UC3A/0256/IAR/lnkuc3a0256.xcl
new file mode 100644 (file)
index 0000000..0381add
--- /dev/null
+++ b/Demo/AVR32_UC3A_GCC/Atmel_SW_Framework/UTILS/LINKER_SCRIPTS/AT32UC3A/0256/IAR/lnkuc3a0256.xcl
@@ -0,0 +1,153 @@
+/******************************************************************************\r
+ * AVR32 AT32UC3A0256 XLINK command file for AVR32 IAR C/C++ Compiler.\r
+ *\r
+ * The assumed memory layout is the one of the AT32UC3A0256:\r
+ *\r
+ *   Start       Stop        Name     Type\r
+ *   ----------  ----------  -----    --------------\r
+ *   0x00000000  0x0000FFFF  SRAM     RAM\r
+ *   0x80000000  0x8003FFFF  FLASH    FLASH\r
+ *   0x80800000  0x808001FF  USER     FLASH\r
+ *\r
+ * Usage:  xlink  your_file(s)  -f xcl-file  libraries\r
+ *\r
+ * - Compiler:           IAR EWAVR32\r
+ * - Supported devices:  AVR32 AT32UC3A0256\r
+ *\r
+ * - author              Atmel Corporation: http://www.atmel.com \n\r
+ *                       Support and FAQ: http://support.atmel.no/\r
+ *\r
+ ******************************************************************************/\r
+\r
+/* Copyright (c) 2009 Atmel Corporation. All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice, this\r
+ * list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an Atmel\r
+ * AVR product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\r
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\r
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\r
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE\r
+ *\r
+ */\r
+\r
+/************************************************************************/\r
+/*      The following segments are defined in this link file:           */\r
+/*                                                                      */\r
+/*      Code segments                                                   */\r
+/*      CODE32    -- Program code used by __code32 functions.           */\r
+/*      RESET     -- Reset code.                                        */\r
+/*      EVSEG     -- Exception vector handlers.                         */\r
+/*                                                                      */\r
+/*      Constant segments                                               */\r
+/*      INITTAB   -- Segment initializer table.                         */\r
+/*      DIFUNCT   -- Dynamic initialization vector used by C++.         */\r
+/*      SWITCH    -- Switch tables.                                     */\r
+/*      ACTAB     -- Table of pointers to acall functions.              */\r
+/*                                                                      */\r
+/*      DATA21_ID -- Initialization data for DATA21_I.                  */\r
+/*      DATA32_ID -- Initialization data for DATA32_I.                  */\r
+/*      DATA32_C  -- Constant __data32 data.                            */\r
+/*                                                                      */\r
+/*      CHECKSUM  -- Checksum segment.                                  */\r
+/*                                                                      */\r
+/*      Data segments                                                   */\r
+/*      DATA21_I  -- Initialized __data21 data with non-zero            */\r
+/*                   initial value.                                     */\r
+/*      DATA32_I  -- Initialized __data32 data with non-zero            */\r
+/*                   initial value.                                     */\r
+/*      DATA21_Z  -- Initialized __data21 data with zero initial value. */\r
+/*      DATA32_Z  -- Initialized __data32 data with zero initial value. */\r
+/*      DATA21_N  -- Non-initialized __data21.                          */\r
+/*      DATA32_N  -- Non-initialized __data32.                          */\r
+/*      SSTACK    -- The system stack.                                  */\r
+/*      CSTACK    -- The application stack.                             */\r
+/*      HEAP      -- The heap used by malloc and free.                  */\r
+/*                                                                      */\r
+/************************************************************************/\r
+\r
+/************************************************************************/\r
+/*      Define CPU                                                      */\r
+/************************************************************************/\r
+\r
+-cavr32\r
+\r
+// Declare the IPR0 memory location\r
+-DIPR0=FFFF0800\r
+\r
+/************************************************************************/\r
+/*      Reset code is located at address 0x80000000 and up.             */\r
+/************************************************************************/\r
+\r
+-Z(CODE)RESET=80000000-8003FFFF\r
+\r
+/************************************************************************/\r
+/*      The exception handler code is located at address 0x80000000     */\r
+/*      and up. Make sure that the exception table gets properly        */\r
+/*      allocated. By using the special -Z@ allocation primitive, the   */\r
+/*      placement is guaranteed to be at _EVBASE and onwards.           */\r
+/************************************************************************/\r
+\r
+-Z@(CODE)EVTAB=80004000-8003FFFF\r
+-Z@(CODE)EV100=80004100-8003FFFF\r
+-P(CODE)EVSEG=80004000-8003FFFF\r
+\r
+/************************************************************************/\r
+/*      Allocate code and const segments.                               */\r
+/************************************************************************/\r
+\r
+-P(CODE)CODE32=80000000-8003FFFF\r
+-P(CONST)DATA32_C=80000000-8003FFFF\r
+-P(CONST)USERDATA32_C=80800000-808001FF\r
+\r
+// Initializers\r
+-Z(CONST)INITTAB,DIFUNCT=80000000-8003FFFF\r
+-Z(CONST)CHECKSUM,SWITCH=80000000-8003FFFF\r
+-Z(CONST)DATA21_ID,DATA32_ID=80000000-8003FFFF\r
+-Z(CONST)RAMCODE21_ID,RAMCODE32_ID=80000000-8003FFFF\r
+\r
+-Z(CONST)ACTAB,HTAB=80000000-8003FFFF\r
+\r
+/************************************************************************/\r
+/*      Allocate the read/write segments that are mapped to RAM.        */\r
+/************************************************************************/\r
+\r
+-Z(CODE)RAMCODE21=00000004-0000FFFF\r
+-Z(DATA)DATA21_I,DATA21_Z,DATA21_N=00000004-0000FFFF\r
+-Z(CODE)RAMCODE32=00000004-0000FFFF\r
+-Z(DATA)DATA32_I,DATA32_Z,DATA32_N=00000004-0000FFFF\r
+-Z(DATA)TRACEBUFFER=00000004-0000FFFF\r
+\r
+-Z(DATA)SSTACK+_SSTACK_SIZE#00000004-0000FFFF\r
+-Z(DATA)CSTACK+_CSTACK_SIZE#00000004-0000FFFF\r
+-Z(DATA)HEAP+_HEAP_SIZE=00000004-0000FFFF\r
+\r
+/************************************************************************/\r
+/*      Copy the RAMCODE bytes to the initializer segments.             */\r
+/************************************************************************/\r
+\r
+-QRAMCODE21=RAMCODE21_ID\r
+-QRAMCODE32=RAMCODE32_ID\r
+\r
+/************************************************************************/\r
+/*      End of File                                                     */\r
+/************************************************************************/\r

diff --git a/Demo/AVR32_UC3A_GCC/Atmel_SW_Framework/UTILS/LINKER_SCRIPTS/AT32UC3A/0512/GCC/link_uc3a0512.lds b/Demo/AVR32_UC3A_GCC/Atmel_SW_Framework/UTILS/LINKER_SCRIPTS/AT32UC3A/0512/GCC/link_uc3a0512.lds
new file mode 100644 (file)
index 0000000..59152ac
--- /dev/null
+++ b/Demo/AVR32_UC3A_GCC/Atmel_SW_Framework/UTILS/LINKER_SCRIPTS/AT32UC3A/0512/GCC/link_uc3a0512.lds
@@ -0,0 +1,266 @@
+/******************************************************************************
+ * AVR32 AT32UC3A0512 GNU LD script file.
+ *
+ * - Compiler:           GNU GCC for AVR32
+ * - Supported devices:  AVR32 AT32UC3A0512
+ *
+ * - author              Atmel Corporation: http://www.atmel.com \n
+ *                       Support and FAQ: http://support.atmel.no/
+ *
+ ******************************************************************************/
+
+/* Copyright (c) 2009 Atmel Corporation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an Atmel
+ * AVR product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
+ *
+ */
+
+OUTPUT_FORMAT("elf32-avr32", "elf32-avr32", "elf32-avr32")
+
+OUTPUT_ARCH(avr32:uc)
+
+ENTRY(_start)
+
+MEMORY
+{
+  FLASH (rxai!w) : ORIGIN = 0x80000000, LENGTH = 0x00080000
+  INTRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0x0000FFFC
+  USERPAGE : ORIGIN = 0x80800000, LENGTH = 0x00000200
+}
+
+PHDRS
+{
+  FLASH PT_LOAD;
+  INTRAM_ALIGN PT_NULL;
+  INTRAM_AT_FLASH PT_LOAD;
+  INTRAM PT_NULL;
+  USERPAGE PT_LOAD;
+}
+
+SECTIONS
+{
+  /* If this heap size is selected, all the INTRAM space from the end of the
+     data area to the beginning of the stack will be allocated for the heap. */
+  __max_heap_size__ = -1;
+
+  /* Use a default heap size if heap size was not defined. */
+  __heap_size__ = DEFINED(__heap_size__) ? __heap_size__ : __max_heap_size__;
+
+  /* Use a default stack size if stack size was not defined. */
+  __stack_size__ = DEFINED(__stack_size__) ? __stack_size__ : 4K;
+
+  /* Read-only sections, merged into text segment: */
+  PROVIDE (__executable_start = 0x80000000); . = 0x80000000;
+  .interp         : { *(.interp) } >FLASH AT>FLASH :FLASH
+  .reset : {  *(.reset) } >FLASH AT>FLASH :FLASH
+  .hash           : { *(.hash) } >FLASH AT>FLASH :FLASH
+  .dynsym         : { *(.dynsym) } >FLASH AT>FLASH :FLASH
+  .dynstr         : { *(.dynstr) } >FLASH AT>FLASH :FLASH
+  .gnu.version    : { *(.gnu.version) } >FLASH AT>FLASH :FLASH
+  .gnu.version_d  : { *(.gnu.version_d) } >FLASH AT>FLASH :FLASH
+  .gnu.version_r  : { *(.gnu.version_r) } >FLASH AT>FLASH :FLASH
+  .rel.init       : { *(.rel.init) } >FLASH AT>FLASH :FLASH
+  .rela.init      : { *(.rela.init) } >FLASH AT>FLASH :FLASH
+  .rel.text       : { *(.rel.text .rel.text.* .rel.gnu.linkonce.t.*) } >FLASH AT>FLASH :FLASH
+  .rela.text      : { *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*) } >FLASH AT>FLASH :FLASH
+  .rel.fini       : { *(.rel.fini) } >FLASH AT>FLASH :FLASH
+  .rela.fini      : { *(.rela.fini) } >FLASH AT>FLASH :FLASH
+  .rel.rodata     : { *(.rel.rodata .rel.rodata.* .rel.gnu.linkonce.r.*) } >FLASH AT>FLASH :FLASH
+  .rela.rodata    : { *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*) } >FLASH AT>FLASH :FLASH
+  .rel.data.rel.ro   : { *(.rel.data.rel.ro*) } >FLASH AT>FLASH :FLASH
+  .rela.data.rel.ro   : { *(.rel.data.rel.ro*) } >FLASH AT>FLASH :FLASH
+  .rel.data       : { *(.rel.data .rel.data.* .rel.gnu.linkonce.d.*) } >FLASH AT>FLASH :FLASH
+  .rela.data      : { *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*) } >FLASH AT>FLASH :FLASH
+  .rel.tdata     : { *(.rel.tdata .rel.tdata.* .rel.gnu.linkonce.td.*) } >FLASH AT>FLASH :FLASH
+  .rela.tdata    : { *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*) } >FLASH AT>FLASH :FLASH
+  .rel.tbss      : { *(.rel.tbss .rel.tbss.* .rel.gnu.linkonce.tb.*) } >FLASH AT>FLASH :FLASH
+  .rela.tbss     : { *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*) } >FLASH AT>FLASH :FLASH
+  .rel.ctors      : { *(.rel.ctors) } >FLASH AT>FLASH :FLASH
+  .rela.ctors     : { *(.rela.ctors) } >FLASH AT>FLASH :FLASH
+  .rel.dtors      : { *(.rel.dtors) } >FLASH AT>FLASH :FLASH
+  .rela.dtors     : { *(.rela.dtors) } >FLASH AT>FLASH :FLASH
+  .rel.got        : { *(.rel.got) } >FLASH AT>FLASH :FLASH
+  .rela.got       : { *(.rela.got) } >FLASH AT>FLASH :FLASH
+  .rel.bss        : { *(.rel.bss .rel.bss.* .rel.gnu.linkonce.b.*) } >FLASH AT>FLASH :FLASH
+  .rela.bss       : { *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*) } >FLASH AT>FLASH :FLASH
+  .rel.plt        : { *(.rel.plt) } >FLASH AT>FLASH :FLASH
+  .rela.plt       : { *(.rela.plt) } >FLASH AT>FLASH :FLASH
+  .init           :
+  {
+    KEEP (*(.init))
+  } >FLASH AT>FLASH :FLASH =0xd703d703
+  .plt            : { *(.plt) } >FLASH AT>FLASH :FLASH
+  .text           :
+  {
+    *(.text .stub .text.* .gnu.linkonce.t.*)
+    KEEP (*(.text.*personality*))
+    /* .gnu.warning sections are handled specially by elf32.em.  */
+    *(.gnu.warning)
+  } >FLASH AT>FLASH :FLASH =0xd703d703
+  .fini           :
+  {
+    KEEP (*(.fini))
+  } >FLASH AT>FLASH :FLASH =0xd703d703
+  PROVIDE (__etext = .);
+  PROVIDE (_etext = .);
+  PROVIDE (etext = .);
+  .rodata         : { *(.rodata .rodata.* .gnu.linkonce.r.*) } >FLASH AT>FLASH :FLASH
+  .rodata1        : { *(.rodata1) } >FLASH AT>FLASH :FLASH
+  .eh_frame_hdr : { *(.eh_frame_hdr) } >FLASH AT>FLASH :FLASH
+  .eh_frame       : ONLY_IF_RO { KEEP (*(.eh_frame)) } >FLASH AT>FLASH :FLASH
+  .gcc_except_table   : ONLY_IF_RO { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) } >FLASH AT>FLASH :FLASH
+  .lalign      : { . = ALIGN(8); PROVIDE(_data_lma = .); } >FLASH AT>FLASH :FLASH
+  . = ORIGIN(INTRAM);
+  .dalign      : { . = ALIGN(8); PROVIDE(_data = .); } >INTRAM AT>INTRAM :INTRAM_ALIGN
+  /* Exception handling  */
+  .eh_frame       : ONLY_IF_RW { KEEP (*(.eh_frame)) } >INTRAM AT>FLASH :INTRAM_AT_FLASH
+  .gcc_except_table   : ONLY_IF_RW { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) } >INTRAM AT>FLASH :INTRAM_AT_FLASH
+  /* Thread Local Storage sections  */
+  .tdata         : { *(.tdata .tdata.* .gnu.linkonce.td.*) } >INTRAM AT>FLASH :INTRAM_AT_FLASH
+  .tbss                  : { *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) } >INTRAM AT>FLASH :INTRAM_AT_FLASH
+  /* Ensure the __preinit_array_start label is properly aligned.  We
+     could instead move the label definition inside the section, but
+     the linker would then create the section even if it turns out to
+     be empty, which isn't pretty.  */
+  PROVIDE (__preinit_array_start = ALIGN(32 / 8));
+  .preinit_array     : { KEEP (*(.preinit_array)) } >INTRAM AT>FLASH :INTRAM_AT_FLASH
+  PROVIDE (__preinit_array_end = .);
+  PROVIDE (__init_array_start = .);
+  .init_array     : { KEEP (*(.init_array)) } >INTRAM AT>FLASH :INTRAM_AT_FLASH
+  PROVIDE (__init_array_end = .);
+  PROVIDE (__fini_array_start = .);
+  .fini_array     : { KEEP (*(.fini_array)) } >INTRAM AT>FLASH :INTRAM_AT_FLASH
+  PROVIDE (__fini_array_end = .);
+  .ctors          :
+  {
+    /* gcc uses crtbegin.o to find the start of
+       the constructors, so we make sure it is
+       first.  Because this is a wildcard, it
+       doesn't matter if the user does not
+       actually link against crtbegin.o; the
+       linker won't look for a file to match a
+       wildcard.  The wildcard also means that it
+       doesn't matter which directory crtbegin.o
+       is in.  */
+    KEEP (*crtbegin*.o(.ctors))
+    /* We don't want to include the .ctor section from
+       from the crtend.o file until after the sorted ctors.
+       The .ctor section from the crtend file contains the
+       end of ctors marker and it must be last */
+    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .ctors))
+    KEEP (*(SORT(.ctors.*)))
+    KEEP (*(.ctors))
+  } >INTRAM AT>FLASH :INTRAM_AT_FLASH
+  .dtors          :
+  {
+    KEEP (*crtbegin*.o(.dtors))
+    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .dtors))
+    KEEP (*(SORT(.dtors.*)))
+    KEEP (*(.dtors))
+  } >INTRAM AT>FLASH :INTRAM_AT_FLASH
+  .jcr            : { KEEP (*(.jcr)) } >INTRAM AT>FLASH :INTRAM_AT_FLASH
+  .data.rel.ro : { *(.data.rel.ro.local) *(.data.rel.ro*) } >INTRAM AT>FLASH :INTRAM_AT_FLASH
+  .dynamic        : { *(.dynamic) } >INTRAM AT>FLASH :INTRAM_AT_FLASH
+  .got            : { *(.got.plt) *(.got) } >INTRAM AT>FLASH :INTRAM_AT_FLASH
+  .ramtext        : { *(.ramtext .ramtext.*) } >INTRAM AT>FLASH :INTRAM_AT_FLASH
+  .ddalign     : { . = ALIGN(8); } >INTRAM AT>FLASH :INTRAM_AT_FLASH
+  .data           :
+  {
+    *(.data .data.* .gnu.linkonce.d.*)
+    KEEP (*(.gnu.linkonce.d.*personality*))
+    SORT(CONSTRUCTORS)
+  } >INTRAM AT>FLASH :INTRAM_AT_FLASH
+  .data1          : { *(.data1) } >INTRAM AT>FLASH :INTRAM_AT_FLASH
+  .balign      : { . = ALIGN(8); PROVIDE(_edata = .); } >INTRAM AT>FLASH :INTRAM_AT_FLASH
+  PROVIDE (edata = .);
+  __bss_start = .;
+  .bss            :
+  {
+    *(.dynbss)
+    *(.bss .bss.* .gnu.linkonce.b.*)
+    *(COMMON)
+    /* Align here to ensure that the .bss section occupies space up to
+       _end.  Align after .bss to ensure correct alignment even if the
+       .bss section disappears because there are no input sections.  */
+    . = ALIGN(8);
+  } >INTRAM AT>INTRAM :INTRAM
+  . = ALIGN(8);
+  _end = .;
+  PROVIDE (end = .);
+  __heap_start__ = ALIGN(8);
+  .heap           :
+  {
+    *(.heap)
+    . = (__heap_size__ == __max_heap_size__) ?
+        ORIGIN(INTRAM) + LENGTH(INTRAM) - __stack_size__ - ABSOLUTE(.) :
+        __heap_size__;
+  } >INTRAM AT>INTRAM :INTRAM
+  __heap_end__ = .;
+  /* Stabs debugging sections.  */
+  .stab          0 : { *(.stab) }
+  .stabstr       0 : { *(.stabstr) }
+  .stab.excl     0 : { *(.stab.excl) }
+  .stab.exclstr  0 : { *(.stab.exclstr) }
+  .stab.index    0 : { *(.stab.index) }
+  .stab.indexstr 0 : { *(.stab.indexstr) }
+  .comment       0 : { *(.comment) }
+  /* DWARF debug sections.
+     Symbols in the DWARF debugging sections are relative to the beginning
+     of the section so we begin them at 0.  */
+  /* DWARF 1 */
+  .debug          0 : { *(.debug) }
+  .line           0 : { *(.line) }
+  /* GNU DWARF 1 extensions */
+  .debug_srcinfo  0 : { *(.debug_srcinfo) }
+  .debug_sfnames  0 : { *(.debug_sfnames) }
+  /* DWARF 1.1 and DWARF 2 */
+  .debug_aranges  0 : { *(.debug_aranges) }
+  .debug_pubnames 0 : { *(.debug_pubnames) }
+  /* DWARF 2 */
+  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }
+  .debug_abbrev   0 : { *(.debug_abbrev) }
+  .debug_line     0 : { *(.debug_line) }
+  .debug_frame    0 : { *(.debug_frame) }
+  .debug_str      0 : { *(.debug_str) }
+  .debug_loc      0 : { *(.debug_loc) }
+  .debug_macinfo  0 : { *(.debug_macinfo) }
+  /* SGI/MIPS DWARF 2 extensions */
+  .debug_weaknames 0 : { *(.debug_weaknames) }
+  .debug_funcnames 0 : { *(.debug_funcnames) }
+  .debug_typenames 0 : { *(.debug_typenames) }
+  .debug_varnames  0 : { *(.debug_varnames) }
+  .stack         ORIGIN(INTRAM) + LENGTH(INTRAM) - __stack_size__ :
+  {
+    _stack = .;
+    *(.stack)
+    . = __stack_size__;
+    _estack = .;
+  } >INTRAM AT>INTRAM :INTRAM
+  .userpage       : { *(.userpage .userpage.*) } >USERPAGE AT>USERPAGE :USERPAGE
+  /DISCARD/ : { *(.note.GNU-stack) }
+}

diff --git a/Demo/AVR32_UC3A_GCC/Atmel_SW_Framework/UTILS/LINKER_SCRIPTS/AT32UC3A/0512/IAR/lnkuc3a0512.xcl b/Demo/AVR32_UC3A_GCC/Atmel_SW_Framework/UTILS/LINKER_SCRIPTS/AT32UC3A/0512/IAR/lnkuc3a0512.xcl
new file mode 100644 (file)
index 0000000..65e2a96
--- /dev/null
+++ b/Demo/AVR32_UC3A_GCC/Atmel_SW_Framework/UTILS/LINKER_SCRIPTS/AT32UC3A/0512/IAR/lnkuc3a0512.xcl
@@ -0,0 +1,153 @@
+/******************************************************************************\r
+ * AVR32 AT32UC3A0512 XLINK command file for AVR32 IAR C/C++ Compiler.\r
+ *\r
+ * The assumed memory layout is the one of the AT32UC3A0512:\r
+ *\r
+ *   Start       Stop        Name     Type\r
+ *   ----------  ----------  -----    --------------\r
+ *   0x00000000  0x0000FFFF  SRAM     RAM\r
+ *   0x80000000  0x8007FFFF  FLASH    FLASH\r
+ *   0x80800000  0x808001FF  USER     FLASH\r
+ *\r
+ * Usage:  xlink  your_file(s)  -f xcl-file  libraries\r
+ *\r
+ * - Compiler:           IAR EWAVR32\r
+ * - Supported devices:  AVR32 AT32UC3A0512\r
+ *\r
+ * - author              Atmel Corporation: http://www.atmel.com \n\r
+ *                       Support and FAQ: http://support.atmel.no/\r
+ *\r
+ ******************************************************************************/\r
+\r
+/* Copyright (c) 2009 Atmel Corporation. All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice, this\r
+ * list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an Atmel\r
+ * AVR product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\r
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\r
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\r
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE\r
+ *\r
+ */\r
+\r
+/************************************************************************/\r
+/*      The following segments are defined in this link file:           */\r
+/*                                                                      */\r
+/*      Code segments                                                   */\r
+/*      CODE32    -- Program code used by __code32 functions.           */\r
+/*      RESET     -- Reset code.                                        */\r
+/*      EVSEG     -- Exception vector handlers.                         */\r
+/*                                                                      */\r
+/*      Constant segments                                               */\r
+/*      INITTAB   -- Segment initializer table.                         */\r
+/*      DIFUNCT   -- Dynamic initialization vector used by C++.         */\r
+/*      SWITCH    -- Switch tables.                                     */\r
+/*      ACTAB     -- Table of pointers to acall functions.              */\r
+/*                                                                      */\r
+/*      DATA21_ID -- Initialization data for DATA21_I.                  */\r
+/*      DATA32_ID -- Initialization data for DATA32_I.                  */\r
+/*      DATA32_C  -- Constant __data32 data.                            */\r
+/*                                                                      */\r
+/*      CHECKSUM  -- Checksum segment.                                  */\r
+/*                                                                      */\r
+/*      Data segments                                                   */\r
+/*      DATA21_I  -- Initialized __data21 data with non-zero            */\r
+/*                   initial value.                                     */\r
+/*      DATA32_I  -- Initialized __data32 data with non-zero            */\r
+/*                   initial value.                                     */\r
+/*      DATA21_Z  -- Initialized __data21 data with zero initial value. */\r
+/*      DATA32_Z  -- Initialized __data32 data with zero initial value. */\r
+/*      DATA21_N  -- Non-initialized __data21.                          */\r
+/*      DATA32_N  -- Non-initialized __data32.                          */\r
+/*      SSTACK    -- The system stack.                                  */\r
+/*      CSTACK    -- The application stack.                             */\r
+/*      HEAP      -- The heap used by malloc and free.                  */\r
+/*                                                                      */\r
+/************************************************************************/\r
+\r
+/************************************************************************/\r
+/*      Define CPU                                                      */\r
+/************************************************************************/\r
+\r
+-cavr32\r
+\r
+// Declare the IPR0 memory location\r
+-DIPR0=FFFF0800\r
+\r
+/************************************************************************/\r
+/*      Reset code is located at address 0x80000000 and up.             */\r
+/************************************************************************/\r
+\r
+-Z(CODE)RESET=80000000-8007FFFF\r
+\r
+/************************************************************************/\r
+/*      The exception handler code is located at address 0x80000000     */\r
+/*      and up. Make sure that the exception table gets properly        */\r
+/*      allocated. By using the special -Z@ allocation primitive, the   */\r
+/*      placement is guaranteed to be at _EVBASE and onwards.           */\r
+/************************************************************************/\r
+\r
+-Z@(CODE)EVTAB=80004000-8007FFFF\r
+-Z@(CODE)EV100=80004100-8007FFFF\r
+-P(CODE)EVSEG=80004000-8007FFFF\r
+\r
+/************************************************************************/\r
+/*      Allocate code and const segments.                               */\r
+/************************************************************************/\r
+\r
+-P(CODE)CODE32=80000000-8007FFFF\r
+-P(CONST)DATA32_C=80000000-8007FFFF\r
+-P(CONST)USERDATA32_C=80800000-808001FF\r
+\r
+// Initializers\r
+-Z(CONST)INITTAB,DIFUNCT=80000000-8007FFFF\r
+-Z(CONST)CHECKSUM,SWITCH=80000000-8007FFFF\r
+-Z(CONST)DATA21_ID,DATA32_ID=80000000-8007FFFF\r
+-Z(CONST)RAMCODE21_ID,RAMCODE32_ID=80000000-8007FFFF\r
+\r
+-Z(CONST)ACTAB,HTAB=80000000-8007FFFF\r
+\r
+/************************************************************************/\r
+/*      Allocate the read/write segments that are mapped to RAM.        */\r
+/************************************************************************/\r
+\r
+-Z(CODE)RAMCODE21=00000004-0000FFFF\r
+-Z(DATA)DATA21_I,DATA21_Z,DATA21_N=00000004-0000FFFF\r
+-Z(CODE)RAMCODE32=00000004-0000FFFF\r
+-Z(DATA)DATA32_I,DATA32_Z,DATA32_N=00000004-0000FFFF\r
+-Z(DATA)TRACEBUFFER=00000004-0000FFFF\r
+\r
+-Z(DATA)SSTACK+_SSTACK_SIZE#00000004-0000FFFF\r
+-Z(DATA)CSTACK+_CSTACK_SIZE#00000004-0000FFFF\r
+-Z(DATA)HEAP+_HEAP_SIZE=00000004-0000FFFF\r
+\r
+/************************************************************************/\r
+/*      Copy the RAMCODE bytes to the initializer segments.             */\r
+/************************************************************************/\r
+\r
+-QRAMCODE21=RAMCODE21_ID\r
+-QRAMCODE32=RAMCODE32_ID\r
+\r
+/************************************************************************/\r
+/*      End of File                                                     */\r
+/************************************************************************/\r

diff --git a/Demo/AVR32_UC3A_GCC/Atmel_SW_Framework/UTILS/LINKER_SCRIPTS/AT32UC3A/1128/GCC/link_uc3a1128.lds b/Demo/AVR32_UC3A_GCC/Atmel_SW_Framework/UTILS/LINKER_SCRIPTS/AT32UC3A/1128/GCC/link_uc3a1128.lds
new file mode 100644 (file)
index 0000000..66c71a8
--- /dev/null
+++ b/Demo/AVR32_UC3A_GCC/Atmel_SW_Framework/UTILS/LINKER_SCRIPTS/AT32UC3A/1128/GCC/link_uc3a1128.lds
@@ -0,0 +1,266 @@
+/******************************************************************************
+ * AVR32 AT32UC3A1128 GNU LD script file.
+ *
+ * - Compiler:           GNU GCC for AVR32
+ * - Supported devices:  AVR32 AT32UC3A1128
+ *
+ * - author              Atmel Corporation: http://www.atmel.com \n
+ *                       Support and FAQ: http://support.atmel.no/
+ *
+ ******************************************************************************/
+
+/* Copyright (c) 2009 Atmel Corporation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an Atmel
+ * AVR product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
+ *
+ */
+
+OUTPUT_FORMAT("elf32-avr32", "elf32-avr32", "elf32-avr32")
+
+OUTPUT_ARCH(avr32:uc)
+
+ENTRY(_start)
+
+MEMORY
+{
+  FLASH (rxai!w) : ORIGIN = 0x80000000, LENGTH = 0x00020000
+  INTRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0x00007FFC
+  USERPAGE : ORIGIN = 0x80800000, LENGTH = 0x00000200
+}
+
+PHDRS
+{
+  FLASH PT_LOAD;
+  INTRAM_ALIGN PT_NULL;
+  INTRAM_AT_FLASH PT_LOAD;
+  INTRAM PT_NULL;
+  USERPAGE PT_LOAD;
+}
+
+SECTIONS
+{
+  /* If this heap size is selected, all the INTRAM space from the end of the
+     data area to the beginning of the stack will be allocated for the heap. */
+  __max_heap_size__ = -1;
+
+  /* Use a default heap size if heap size was not defined. */
+  __heap_size__ = DEFINED(__heap_size__) ? __heap_size__ : __max_heap_size__;
+
+  /* Use a default stack size if stack size was not defined. */
+  __stack_size__ = DEFINED(__stack_size__) ? __stack_size__ : 4K;
+
+  /* Read-only sections, merged into text segment: */
+  PROVIDE (__executable_start = 0x80000000); . = 0x80000000;
+  .interp         : { *(.interp) } >FLASH AT>FLASH :FLASH
+  .reset : {  *(.reset) } >FLASH AT>FLASH :FLASH
+  .hash           : { *(.hash) } >FLASH AT>FLASH :FLASH
+  .dynsym         : { *(.dynsym) } >FLASH AT>FLASH :FLASH
+  .dynstr         : { *(.dynstr) } >FLASH AT>FLASH :FLASH
+  .gnu.version    : { *(.gnu.version) } >FLASH AT>FLASH :FLASH
+  .gnu.version_d  : { *(.gnu.version_d) } >FLASH AT>FLASH :FLASH
+  .gnu.version_r  : { *(.gnu.version_r) } >FLASH AT>FLASH :FLASH
+  .rel.init       : { *(.rel.init) } >FLASH AT>FLASH :FLASH
+  .rela.init      : { *(.rela.init) } >FLASH AT>FLASH :FLASH
+  .rel.text       : { *(.rel.text .rel.text.* .rel.gnu.linkonce.t.*) } >FLASH AT>FLASH :FLASH
+  .rela.text      : { *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*) } >FLASH AT>FLASH :FLASH
+  .rel.fini       : { *(.rel.fini) } >FLASH AT>FLASH :FLASH
+  .rela.fini      : { *(.rela.fini) } >FLASH AT>FLASH :FLASH
+  .rel.rodata     : { *(.rel.rodata .rel.rodata.* .rel.gnu.linkonce.r.*) } >FLASH AT>FLASH :FLASH
+  .rela.rodata    : { *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*) } >FLASH AT>FLASH :FLASH
+  .rel.data.rel.ro   : { *(.rel.data.rel.ro*) } >FLASH AT>FLASH :FLASH
+  .rela.data.rel.ro   : { *(.rel.data.rel.ro*) } >FLASH AT>FLASH :FLASH
+  .rel.data       : { *(.rel.data .rel.data.* .rel.gnu.linkonce.d.*) } >FLASH AT>FLASH :FLASH
+  .rela.data      : { *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*) } >FLASH AT>FLASH :FLASH
+  .rel.tdata     : { *(.rel.tdata .rel.tdata.* .rel.gnu.linkonce.td.*) } >FLASH AT>FLASH :FLASH
+  .rela.tdata    : { *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*) } >FLASH AT>FLASH :FLASH
+  .rel.tbss      : { *(.rel.tbss .rel.tbss.* .rel.gnu.linkonce.tb.*) } >FLASH AT>FLASH :FLASH
+  .rela.tbss     : { *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*) } >FLASH AT>FLASH :FLASH
+  .rel.ctors      : { *(.rel.ctors) } >FLASH AT>FLASH :FLASH
+  .rela.ctors     : { *(.rela.ctors) } >FLASH AT>FLASH :FLASH
+  .rel.dtors      : { *(.rel.dtors) } >FLASH AT>FLASH :FLASH
+  .rela.dtors     : { *(.rela.dtors) } >FLASH AT>FLASH :FLASH
+  .rel.got        : { *(.rel.got) } >FLASH AT>FLASH :FLASH
+  .rela.got       : { *(.rela.got) } >FLASH AT>FLASH :FLASH
+  .rel.bss        : { *(.rel.bss .rel.bss.* .rel.gnu.linkonce.b.*) } >FLASH AT>FLASH :FLASH
+  .rela.bss       : { *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*) } >FLASH AT>FLASH :FLASH
+  .rel.plt        : { *(.rel.plt) } >FLASH AT>FLASH :FLASH
+  .rela.plt       : { *(.rela.plt) } >FLASH AT>FLASH :FLASH
+  .init           :
+  {
+    KEEP (*(.init))
+  } >FLASH AT>FLASH :FLASH =0xd703d703
+  .plt            : { *(.plt) } >FLASH AT>FLASH :FLASH
+  .text           :
+  {
+    *(.text .stub .text.* .gnu.linkonce.t.*)
+    KEEP (*(.text.*personality*))
+    /* .gnu.warning sections are handled specially by elf32.em.  */
+    *(.gnu.warning)
+  } >FLASH AT>FLASH :FLASH =0xd703d703
+  .fini           :
+  {
+    KEEP (*(.fini))
+  } >FLASH AT>FLASH :FLASH =0xd703d703
+  PROVIDE (__etext = .);
+  PROVIDE (_etext = .);
+  PROVIDE (etext = .);
+  .rodata         : { *(.rodata .rodata.* .gnu.linkonce.r.*) } >FLASH AT>FLASH :FLASH
+  .rodata1        : { *(.rodata1) } >FLASH AT>FLASH :FLASH
+  .eh_frame_hdr : { *(.eh_frame_hdr) } >FLASH AT>FLASH :FLASH
+  .eh_frame       : ONLY_IF_RO { KEEP (*(.eh_frame)) } >FLASH AT>FLASH :FLASH
+  .gcc_except_table   : ONLY_IF_RO { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) } >FLASH AT>FLASH :FLASH
+  .lalign      : { . = ALIGN(8); PROVIDE(_data_lma = .); } >FLASH AT>FLASH :FLASH
+  . = ORIGIN(INTRAM);
+  .dalign      : { . = ALIGN(8); PROVIDE(_data = .); } >INTRAM AT>INTRAM :INTRAM_ALIGN
+  /* Exception handling  */
+  .eh_frame       : ONLY_IF_RW { KEEP (*(.eh_frame)) } >INTRAM AT>FLASH :INTRAM_AT_FLASH
+  .gcc_except_table   : ONLY_IF_RW { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) } >INTRAM AT>FLASH :INTRAM_AT_FLASH
+  /* Thread Local Storage sections  */
+  .tdata         : { *(.tdata .tdata.* .gnu.linkonce.td.*) } >INTRAM AT>FLASH :INTRAM_AT_FLASH
+  .tbss                  : { *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) } >INTRAM AT>FLASH :INTRAM_AT_FLASH
+  /* Ensure the __preinit_array_start label is properly aligned.  We
+     could instead move the label definition inside the section, but
+     the linker would then create the section even if it turns out to
+     be empty, which isn't pretty.  */
+  PROVIDE (__preinit_array_start = ALIGN(32 / 8));
+  .preinit_array     : { KEEP (*(.preinit_array)) } >INTRAM AT>FLASH :INTRAM_AT_FLASH
+  PROVIDE (__preinit_array_end = .);
+  PROVIDE (__init_array_start = .);
+  .init_array     : { KEEP (*(.init_array)) } >INTRAM AT>FLASH :INTRAM_AT_FLASH
+  PROVIDE (__init_array_end = .);
+  PROVIDE (__fini_array_start = .);
+  .fini_array     : { KEEP (*(.fini_array)) } >INTRAM AT>FLASH :INTRAM_AT_FLASH
+  PROVIDE (__fini_array_end = .);
+  .ctors          :
+  {
+    /* gcc uses crtbegin.o to find the start of
+       the constructors, so we make sure it is
+       first.  Because this is a wildcard, it
+       doesn't matter if the user does not
+       actually link against crtbegin.o; the
+       linker won't look for a file to match a
+       wildcard.  The wildcard also means that it
+       doesn't matter which directory crtbegin.o
+       is in.  */
+    KEEP (*crtbegin*.o(.ctors))
+    /* We don't want to include the .ctor section from
+       from the crtend.o file until after the sorted ctors.
+       The .ctor section from the crtend file contains the
+       end of ctors marker and it must be last */
+    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .ctors))
+    KEEP (*(SORT(.ctors.*)))
+    KEEP (*(.ctors))
+  } >INTRAM AT>FLASH :INTRAM_AT_FLASH
+  .dtors          :
+  {
+    KEEP (*crtbegin*.o(.dtors))
+    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .dtors))
+    KEEP (*(SORT(.dtors.*)))
+    KEEP (*(.dtors))
+  } >INTRAM AT>FLASH :INTRAM_AT_FLASH
+  .jcr            : { KEEP (*(.jcr)) } >INTRAM AT>FLASH :INTRAM_AT_FLASH
+  .data.rel.ro : { *(.data.rel.ro.local) *(.data.rel.ro*) } >INTRAM AT>FLASH :INTRAM_AT_FLASH
+  .dynamic        : { *(.dynamic) } >INTRAM AT>FLASH :INTRAM_AT_FLASH
+  .got            : { *(.got.plt) *(.got) } >INTRAM AT>FLASH :INTRAM_AT_FLASH
+  .ramtext        : { *(.ramtext .ramtext.*) } >INTRAM AT>FLASH :INTRAM_AT_FLASH
+  .ddalign     : { . = ALIGN(8); } >INTRAM AT>FLASH :INTRAM_AT_FLASH
+  .data           :
+  {
+    *(.data .data.* .gnu.linkonce.d.*)
+    KEEP (*(.gnu.linkonce.d.*personality*))
+    SORT(CONSTRUCTORS)
+  } >INTRAM AT>FLASH :INTRAM_AT_FLASH
+  .data1          : { *(.data1) } >INTRAM AT>FLASH :INTRAM_AT_FLASH
+  .balign      : { . = ALIGN(8); PROVIDE(_edata = .); } >INTRAM AT>FLASH :INTRAM_AT_FLASH
+  PROVIDE (edata = .);
+  __bss_start = .;
+  .bss            :
+  {
+    *(.dynbss)
+    *(.bss .bss.* .gnu.linkonce.b.*)
+    *(COMMON)
+    /* Align here to ensure that the .bss section occupies space up to
+       _end.  Align after .bss to ensure correct alignment even if the
+       .bss section disappears because there are no input sections.  */
+    . = ALIGN(8);
+  } >INTRAM AT>INTRAM :INTRAM
+  . = ALIGN(8);
+  _end = .;
+  PROVIDE (end = .);
+  __heap_start__ = ALIGN(8);
+  .heap           :
+  {
+    *(.heap)
+    . = (__heap_size__ == __max_heap_size__) ?
+        ORIGIN(INTRAM) + LENGTH(INTRAM) - __stack_size__ - ABSOLUTE(.) :
+        __heap_size__;
+  } >INTRAM AT>INTRAM :INTRAM
+  __heap_end__ = .;
+  /* Stabs debugging sections.  */
+  .stab          0 : { *(.stab) }
+  .stabstr       0 : { *(.stabstr) }
+  .stab.excl     0 : { *(.stab.excl) }
+  .stab.exclstr  0 : { *(.stab.exclstr) }
+  .stab.index    0 : { *(.stab.index) }
+  .stab.indexstr 0 : { *(.stab.indexstr) }
+  .comment       0 : { *(.comment) }
+  /* DWARF debug sections.
+     Symbols in the DWARF debugging sections are relative to the beginning
+     of the section so we begin them at 0.  */
+  /* DWARF 1 */
+  .debug          0 : { *(.debug) }
+  .line           0 : { *(.line) }
+  /* GNU DWARF 1 extensions */
+  .debug_srcinfo  0 : { *(.debug_srcinfo) }
+  .debug_sfnames  0 : { *(.debug_sfnames) }
+  /* DWARF 1.1 and DWARF 2 */
+  .debug_aranges  0 : { *(.debug_aranges) }
+  .debug_pubnames 0 : { *(.debug_pubnames) }
+  /* DWARF 2 */
+  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }
+  .debug_abbrev   0 : { *(.debug_abbrev) }
+  .debug_line     0 : { *(.debug_line) }
+  .debug_frame    0 : { *(.debug_frame) }
+  .debug_str      0 : { *(.debug_str) }
+  .debug_loc      0 : { *(.debug_loc) }
+  .debug_macinfo  0 : { *(.debug_macinfo) }
+  /* SGI/MIPS DWARF 2 extensions */
+  .debug_weaknames 0 : { *(.debug_weaknames) }
+  .debug_funcnames 0 : { *(.debug_funcnames) }
+  .debug_typenames 0 : { *(.debug_typenames) }
+  .debug_varnames  0 : { *(.debug_varnames) }
+  .stack         ORIGIN(INTRAM) + LENGTH(INTRAM) - __stack_size__ :
+  {
+    _stack = .;
+    *(.stack)
+    . = __stack_size__;
+    _estack = .;
+  } >INTRAM AT>INTRAM :INTRAM
+  .userpage       : { *(.userpage .userpage.*) } >USERPAGE AT>USERPAGE :USERPAGE
+  /DISCARD/ : { *(.note.GNU-stack) }
+}

diff --git a/Demo/AVR32_UC3A_GCC/Atmel_SW_Framework/UTILS/LINKER_SCRIPTS/AT32UC3A/1128/IAR/lnkuc3a1128.xcl b/Demo/AVR32_UC3A_GCC/Atmel_SW_Framework/UTILS/LINKER_SCRIPTS/AT32UC3A/1128/IAR/lnkuc3a1128.xcl
new file mode 100644 (file)
index 0000000..0971aac
--- /dev/null
+++ b/Demo/AVR32_UC3A_GCC/Atmel_SW_Framework/UTILS/LINKER_SCRIPTS/AT32UC3A/1128/IAR/lnkuc3a1128.xcl
@@ -0,0 +1,153 @@
+/******************************************************************************\r
+ * AVR32 AT32UC3A1128 XLINK command file for AVR32 IAR C/C++ Compiler.\r
+ *\r
+ * The assumed memory layout is the one of the AT32UC3A1128:\r
+ *\r
+ *   Start       Stop        Name     Type\r
+ *   ----------  ----------  -----    --------------\r
+ *   0x00000000  0x00007FFF  SRAM     RAM\r
+ *   0x80000000  0x8001FFFF  FLASH    FLASH\r
+ *   0x80800000  0x808001FF  USER     FLASH\r
+ *\r
+ * Usage:  xlink  your_file(s)  -f xcl-file  libraries\r
+ *\r
+ * - Compiler:           IAR EWAVR32\r
+ * - Supported devices:  AVR32 AT32UC3A1128\r
+ *\r
+ * - author              Atmel Corporation: http://www.atmel.com \n\r
+ *                       Support and FAQ: http://support.atmel.no/\r
+ *\r
+ ******************************************************************************/\r
+\r
+/* Copyright (c) 2009 Atmel Corporation. All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice, this\r
+ * list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an Atmel\r
+ * AVR product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\r
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\r
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\r
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE\r
+ *\r
+ */\r
+\r
+/************************************************************************/\r
+/*      The following segments are defined in this link file:           */\r
+/*                                                                      */\r
+/*      Code segments                                                   */\r
+/*      CODE32    -- Program code used by __code32 functions.           */\r
+/*      RESET     -- Reset code.                                        */\r
+/*      EVSEG     -- Exception vector handlers.                         */\r
+/*                                                                      */\r
+/*      Constant segments                                               */\r
+/*      INITTAB   -- Segment initializer table.                         */\r
+/*      DIFUNCT   -- Dynamic initialization vector used by C++.         */\r
+/*      SWITCH    -- Switch tables.                                     */\r
+/*      ACTAB     -- Table of pointers to acall functions.              */\r
+/*                                                                      */\r
+/*      DATA21_ID -- Initialization data for DATA21_I.                  */\r
+/*      DATA32_ID -- Initialization data for DATA32_I.                  */\r
+/*      DATA32_C  -- Constant __data32 data.                            */\r
+/*                                                                      */\r
+/*      CHECKSUM  -- Checksum segment.                                  */\r
+/*                                                                      */\r
+/*      Data segments                                                   */\r
+/*      DATA21_I  -- Initialized __data21 data with non-zero            */\r
+/*                   initial value.                                     */\r
+/*      DATA32_I  -- Initialized __data32 data with non-zero            */\r
+/*                   initial value.                                     */\r
+/*      DATA21_Z  -- Initialized __data21 data with zero initial value. */\r
+/*      DATA32_Z  -- Initialized __data32 data with zero initial value. */\r
+/*      DATA21_N  -- Non-initialized __data21.                          */\r
+/*      DATA32_N  -- Non-initialized __data32.                          */\r
+/*      SSTACK    -- The system stack.                                  */\r
+/*      CSTACK    -- The application stack.                             */\r
+/*      HEAP      -- The heap used by malloc and free.                  */\r
+/*                                                                      */\r
+/************************************************************************/\r
+\r
+/************************************************************************/\r
+/*      Define CPU                                                      */\r
+/************************************************************************/\r
+\r
+-cavr32\r
+\r
+// Declare the IPR0 memory location\r
+-DIPR0=FFFF0800\r
+\r
+/************************************************************************/\r
+/*      Reset code is located at address 0x80000000 and up.             */\r
+/************************************************************************/\r
+\r
+-Z(CODE)RESET=80000000-8001FFFF\r
+\r
+/************************************************************************/\r
+/*      The exception handler code is located at address 0x80000000     */\r
+/*      and up. Make sure that the exception table gets properly        */\r
+/*      allocated. By using the special -Z@ allocation primitive, the   */\r
+/*      placement is guaranteed to be at _EVBASE and onwards.           */\r
+/************************************************************************/\r
+\r
+-Z@(CODE)EVTAB=80004000-8001FFFF\r
+-Z@(CODE)EV100=80004100-8001FFFF\r
+-P(CODE)EVSEG=80004000-8001FFFF\r
+\r
+/************************************************************************/\r
+/*      Allocate code and const segments.                               */\r
+/************************************************************************/\r
+\r
+-P(CODE)CODE32=80000000-8001FFFF\r
+-P(CONST)DATA32_C=80000000-8001FFFF\r
+-P(CONST)USERDATA32_C=80800000-808001FF\r
+\r
+// Initializers\r
+-Z(CONST)INITTAB,DIFUNCT=80000000-8001FFFF\r
+-Z(CONST)CHECKSUM,SWITCH=80000000-8001FFFF\r
+-Z(CONST)DATA21_ID,DATA32_ID=80000000-8001FFFF\r
+-Z(CONST)RAMCODE21_ID,RAMCODE32_ID=80000000-8001FFFF\r
+\r
+-Z(CONST)ACTAB,HTAB=80000000-8001FFFF\r
+\r
+/************************************************************************/\r
+/*      Allocate the read/write segments that are mapped to RAM.        */\r
+/************************************************************************/\r
+\r
+-Z(CODE)RAMCODE21=00000004-00007FFF\r
+-Z(DATA)DATA21_I,DATA21_Z,DATA21_N=00000004-00007FFF\r
+-Z(CODE)RAMCODE32=00000004-00007FFF\r
+-Z(DATA)DATA32_I,DATA32_Z,DATA32_N=00000004-00007FFF\r
+-Z(DATA)TRACEBUFFER=00000004-00007FFF\r
+\r
+-Z(DATA)SSTACK+_SSTACK_SIZE#00000004-00007FFF\r
+-Z(DATA)CSTACK+_CSTACK_SIZE#00000004-00007FFF\r
+-Z(DATA)HEAP+_HEAP_SIZE=00000004-00007FFF\r
+\r
+/************************************************************************/\r
+/*      Copy the RAMCODE bytes to the initializer segments.             */\r
+/************************************************************************/\r
+\r
+-QRAMCODE21=RAMCODE21_ID\r
+-QRAMCODE32=RAMCODE32_ID\r
+\r
+/************************************************************************/\r
+/*      End of File                                                     */\r
+/************************************************************************/\r

diff --git a/Demo/AVR32_UC3A_GCC/Atmel_SW_Framework/UTILS/LINKER_SCRIPTS/AT32UC3A/1256/GCC/link_uc3a1256.lds b/Demo/AVR32_UC3A_GCC/Atmel_SW_Framework/UTILS/LINKER_SCRIPTS/AT32UC3A/1256/GCC/link_uc3a1256.lds
new file mode 100644 (file)
index 0000000..a5926d8
--- /dev/null
+++ b/Demo/AVR32_UC3A_GCC/Atmel_SW_Framework/UTILS/LINKER_SCRIPTS/AT32UC3A/1256/GCC/link_uc3a1256.lds
@@ -0,0 +1,266 @@
+/******************************************************************************
+ * AVR32 AT32UC3A1256 GNU LD script file.
+ *
+ * - Compiler:           GNU GCC for AVR32
+ * - Supported devices:  AVR32 AT32UC3A1256
+ *
+ * - author              Atmel Corporation: http://www.atmel.com \n
+ *                       Support and FAQ: http://support.atmel.no/
+ *
+ ******************************************************************************/
+
+/* Copyright (c) 2009 Atmel Corporation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an Atmel
+ * AVR product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
+ *
+ */
+
+OUTPUT_FORMAT("elf32-avr32", "elf32-avr32", "elf32-avr32")
+
+OUTPUT_ARCH(avr32:uc)
+
+ENTRY(_start)
+
+MEMORY
+{
+  FLASH (rxai!w) : ORIGIN = 0x80000000, LENGTH = 0x00040000
+  INTRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0x0000FFFC
+  USERPAGE : ORIGIN = 0x80800000, LENGTH = 0x00000200
+}
+
+PHDRS
+{
+  FLASH PT_LOAD;
+  INTRAM_ALIGN PT_NULL;
+  INTRAM_AT_FLASH PT_LOAD;
+  INTRAM PT_NULL;
+  USERPAGE PT_LOAD;
+}
+
+SECTIONS
+{
+  /* If this heap size is selected, all the INTRAM space from the end of the
+     data area to the beginning of the stack will be allocated for the heap. */
+  __max_heap_size__ = -1;
+
+  /* Use a default heap size if heap size was not defined. */
+  __heap_size__ = DEFINED(__heap_size__) ? __heap_size__ : __max_heap_size__;
+
+  /* Use a default stack size if stack size was not defined. */
+  __stack_size__ = DEFINED(__stack_size__) ? __stack_size__ : 4K;
+
+  /* Read-only sections, merged into text segment: */
+  PROVIDE (__executable_start = 0x80000000); . = 0x80000000;
+  .interp         : { *(.interp) } >FLASH AT>FLASH :FLASH
+  .reset : {  *(.reset) } >FLASH AT>FLASH :FLASH
+  .hash           : { *(.hash) } >FLASH AT>FLASH :FLASH
+  .dynsym         : { *(.dynsym) } >FLASH AT>FLASH :FLASH
+  .dynstr         : { *(.dynstr) } >FLASH AT>FLASH :FLASH
+  .gnu.version    : { *(.gnu.version) } >FLASH AT>FLASH :FLASH
+  .gnu.version_d  : { *(.gnu.version_d) } >FLASH AT>FLASH :FLASH
+  .gnu.version_r  : { *(.gnu.version_r) } >FLASH AT>FLASH :FLASH
+  .rel.init       : { *(.rel.init) } >FLASH AT>FLASH :FLASH
+  .rela.init      : { *(.rela.init) } >FLASH AT>FLASH :FLASH
+  .rel.text       : { *(.rel.text .rel.text.* .rel.gnu.linkonce.t.*) } >FLASH AT>FLASH :FLASH
+  .rela.text      : { *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*) } >FLASH AT>FLASH :FLASH
+  .rel.fini       : { *(.rel.fini) } >FLASH AT>FLASH :FLASH
+  .rela.fini      : { *(.rela.fini) } >FLASH AT>FLASH :FLASH
+  .rel.rodata     : { *(.rel.rodata .rel.rodata.* .rel.gnu.linkonce.r.*) } >FLASH AT>FLASH :FLASH
+  .rela.rodata    : { *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*) } >FLASH AT>FLASH :FLASH
+  .rel.data.rel.ro   : { *(.rel.data.rel.ro*) } >FLASH AT>FLASH :FLASH
+  .rela.data.rel.ro   : { *(.rel.data.rel.ro*) } >FLASH AT>FLASH :FLASH
+  .rel.data       : { *(.rel.data .rel.data.* .rel.gnu.linkonce.d.*) } >FLASH AT>FLASH :FLASH
+  .rela.data      : { *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*) } >FLASH AT>FLASH :FLASH
+  .rel.tdata     : { *(.rel.tdata .rel.tdata.* .rel.gnu.linkonce.td.*) } >FLASH AT>FLASH :FLASH
+  .rela.tdata    : { *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*) } >FLASH AT>FLASH :FLASH
+  .rel.tbss      : { *(.rel.tbss .rel.tbss.* .rel.gnu.linkonce.tb.*) } >FLASH AT>FLASH :FLASH
+  .rela.tbss     : { *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*) } >FLASH AT>FLASH :FLASH
+  .rel.ctors      : { *(.rel.ctors) } >FLASH AT>FLASH :FLASH
+  .rela.ctors     : { *(.rela.ctors) } >FLASH AT>FLASH :FLASH
+  .rel.dtors      : { *(.rel.dtors) } >FLASH AT>FLASH :FLASH
+  .rela.dtors     : { *(.rela.dtors) } >FLASH AT>FLASH :FLASH
+  .rel.got        : { *(.rel.got) } >FLASH AT>FLASH :FLASH
+  .rela.got       : { *(.rela.got) } >FLASH AT>FLASH :FLASH
+  .rel.bss        : { *(.rel.bss .rel.bss.* .rel.gnu.linkonce.b.*) } >FLASH AT>FLASH :FLASH
+  .rela.bss       : { *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*) } >FLASH AT>FLASH :FLASH
+  .rel.plt        : { *(.rel.plt) } >FLASH AT>FLASH :FLASH
+  .rela.plt       : { *(.rela.plt) } >FLASH AT>FLASH :FLASH
+  .init           :
+  {
+    KEEP (*(.init))
+  } >FLASH AT>FLASH :FLASH =0xd703d703
+  .plt            : { *(.plt) } >FLASH AT>FLASH :FLASH
+  .text           :
+  {
+    *(.text .stub .text.* .gnu.linkonce.t.*)
+    KEEP (*(.text.*personality*))
+    /* .gnu.warning sections are handled specially by elf32.em.  */
+    *(.gnu.warning)
+  } >FLASH AT>FLASH :FLASH =0xd703d703
+  .fini           :
+  {
+    KEEP (*(.fini))
+  } >FLASH AT>FLASH :FLASH =0xd703d703
+  PROVIDE (__etext = .);
+  PROVIDE (_etext = .);
+  PROVIDE (etext = .);
+  .rodata         : { *(.rodata .rodata.* .gnu.linkonce.r.*) } >FLASH AT>FLASH :FLASH
+  .rodata1        : { *(.rodata1) } >FLASH AT>FLASH :FLASH
+  .eh_frame_hdr : { *(.eh_frame_hdr) } >FLASH AT>FLASH :FLASH
+  .eh_frame       : ONLY_IF_RO { KEEP (*(.eh_frame)) } >FLASH AT>FLASH :FLASH
+  .gcc_except_table   : ONLY_IF_RO { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) } >FLASH AT>FLASH :FLASH
+  .lalign      : { . = ALIGN(8); PROVIDE(_data_lma = .); } >FLASH AT>FLASH :FLASH
+  . = ORIGIN(INTRAM);
+  .dalign      : { . = ALIGN(8); PROVIDE(_data = .); } >INTRAM AT>INTRAM :INTRAM_ALIGN
+  /* Exception handling  */
+  .eh_frame       : ONLY_IF_RW { KEEP (*(.eh_frame)) } >INTRAM AT>FLASH :INTRAM_AT_FLASH
+  .gcc_except_table   : ONLY_IF_RW { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) } >INTRAM AT>FLASH :INTRAM_AT_FLASH
+  /* Thread Local Storage sections  */
+  .tdata         : { *(.tdata .tdata.* .gnu.linkonce.td.*) } >INTRAM AT>FLASH :INTRAM_AT_FLASH
+  .tbss                  : { *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) } >INTRAM AT>FLASH :INTRAM_AT_FLASH
+  /* Ensure the __preinit_array_start label is properly aligned.  We
+     could instead move the label definition inside the section, but
+     the linker would then create the section even if it turns out to
+     be empty, which isn't pretty.  */
+  PROVIDE (__preinit_array_start = ALIGN(32 / 8));
+  .preinit_array     : { KEEP (*(.preinit_array)) } >INTRAM AT>FLASH :INTRAM_AT_FLASH
+  PROVIDE (__preinit_array_end = .);
+  PROVIDE (__init_array_start = .);
+  .init_array     : { KEEP (*(.init_array)) } >INTRAM AT>FLASH :INTRAM_AT_FLASH
+  PROVIDE (__init_array_end = .);
+  PROVIDE (__fini_array_start = .);
+  .fini_array     : { KEEP (*(.fini_array)) } >INTRAM AT>FLASH :INTRAM_AT_FLASH
+  PROVIDE (__fini_array_end = .);
+  .ctors          :
+  {
+    /* gcc uses crtbegin.o to find the start of
+       the constructors, so we make sure it is
+       first.  Because this is a wildcard, it
+       doesn't matter if the user does not
+       actually link against crtbegin.o; the
+       linker won't look for a file to match a
+       wildcard.  The wildcard also means that it
+       doesn't matter which directory crtbegin.o
+       is in.  */
+    KEEP (*crtbegin*.o(.ctors))
+    /* We don't want to include the .ctor section from
+       from the crtend.o file until after the sorted ctors.
+       The .ctor section from the crtend file contains the
+       end of ctors marker and it must be last */
+    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .ctors))
+    KEEP (*(SORT(.ctors.*)))
+    KEEP (*(.ctors))
+  } >INTRAM AT>FLASH :INTRAM_AT_FLASH
+  .dtors          :
+  {
+    KEEP (*crtbegin*.o(.dtors))
+    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .dtors))
+    KEEP (*(SORT(.dtors.*)))
+    KEEP (*(.dtors))
+  } >INTRAM AT>FLASH :INTRAM_AT_FLASH
+  .jcr            : { KEEP (*(.jcr)) } >INTRAM AT>FLASH :INTRAM_AT_FLASH
+  .data.rel.ro : { *(.data.rel.ro.local) *(.data.rel.ro*) } >INTRAM AT>FLASH :INTRAM_AT_FLASH
+  .dynamic        : { *(.dynamic) } >INTRAM AT>FLASH :INTRAM_AT_FLASH
+  .got            : { *(.got.plt) *(.got) } >INTRAM AT>FLASH :INTRAM_AT_FLASH
+  .ramtext        : { *(.ramtext .ramtext.*) } >INTRAM AT>FLASH :INTRAM_AT_FLASH
+  .ddalign     : { . = ALIGN(8); } >INTRAM AT>FLASH :INTRAM_AT_FLASH
+  .data           :
+  {
+    *(.data .data.* .gnu.linkonce.d.*)
+    KEEP (*(.gnu.linkonce.d.*personality*))
+    SORT(CONSTRUCTORS)
+  } >INTRAM AT>FLASH :INTRAM_AT_FLASH
+  .data1          : { *(.data1) } >INTRAM AT>FLASH :INTRAM_AT_FLASH
+  .balign      : { . = ALIGN(8); PROVIDE(_edata = .); } >INTRAM AT>FLASH :INTRAM_AT_FLASH
+  PROVIDE (edata = .);
+  __bss_start = .;
+  .bss            :
+  {
+    *(.dynbss)
+    *(.bss .bss.* .gnu.linkonce.b.*)
+    *(COMMON)
+    /* Align here to ensure that the .bss section occupies space up to
+       _end.  Align after .bss to ensure correct alignment even if the
+       .bss section disappears because there are no input sections.  */
+    . = ALIGN(8);
+  } >INTRAM AT>INTRAM :INTRAM
+  . = ALIGN(8);
+  _end = .;
+  PROVIDE (end = .);
+  __heap_start__ = ALIGN(8);
+  .heap           :
+  {
+    *(.heap)
+    . = (__heap_size__ == __max_heap_size__) ?
+        ORIGIN(INTRAM) + LENGTH(INTRAM) - __stack_size__ - ABSOLUTE(.) :
+        __heap_size__;
+  } >INTRAM AT>INTRAM :INTRAM
+  __heap_end__ = .;
+  /* Stabs debugging sections.  */
+  .stab          0 : { *(.stab) }
+  .stabstr       0 : { *(.stabstr) }
+  .stab.excl     0 : { *(.stab.excl) }
+  .stab.exclstr  0 : { *(.stab.exclstr) }
+  .stab.index    0 : { *(.stab.index) }
+  .stab.indexstr 0 : { *(.stab.indexstr) }
+  .comment       0 : { *(.comment) }
+  /* DWARF debug sections.
+     Symbols in the DWARF debugging sections are relative to the beginning
+     of the section so we begin them at 0.  */
+  /* DWARF 1 */
+  .debug          0 : { *(.debug) }
+  .line           0 : { *(.line) }
+  /* GNU DWARF 1 extensions */
+  .debug_srcinfo  0 : { *(.debug_srcinfo) }
+  .debug_sfnames  0 : { *(.debug_sfnames) }
+  /* DWARF 1.1 and DWARF 2 */
+  .debug_aranges  0 : { *(.debug_aranges) }
+  .debug_pubnames 0 : { *(.debug_pubnames) }
+  /* DWARF 2 */
+  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }
+  .debug_abbrev   0 : { *(.debug_abbrev) }
+  .debug_line     0 : { *(.debug_line) }
+  .debug_frame    0 : { *(.debug_frame) }
+  .debug_str      0 : { *(.debug_str) }
+  .debug_loc      0 : { *(.debug_loc) }
+  .debug_macinfo  0 : { *(.debug_macinfo) }
+  /* SGI/MIPS DWARF 2 extensions */
+  .debug_weaknames 0 : { *(.debug_weaknames) }
+  .debug_funcnames 0 : { *(.debug_funcnames) }
+  .debug_typenames 0 : { *(.debug_typenames) }
+  .debug_varnames  0 : { *(.debug_varnames) }
+  .stack         ORIGIN(INTRAM) + LENGTH(INTRAM) - __stack_size__ :
+  {
+    _stack = .;
+    *(.stack)
+    . = __stack_size__;
+    _estack = .;
+  } >INTRAM AT>INTRAM :INTRAM
+  .userpage       : { *(.userpage .userpage.*) } >USERPAGE AT>USERPAGE :USERPAGE
+  /DISCARD/ : { *(.note.GNU-stack) }
+}

diff --git a/Demo/AVR32_UC3A_GCC/Atmel_SW_Framework/UTILS/LINKER_SCRIPTS/AT32UC3A/1256/IAR/lnkuc3a1256.xcl b/Demo/AVR32_UC3A_GCC/Atmel_SW_Framework/UTILS/LINKER_SCRIPTS/AT32UC3A/1256/IAR/lnkuc3a1256.xcl
new file mode 100644 (file)
index 0000000..f707ed2
--- /dev/null
+++ b/Demo/AVR32_UC3A_GCC/Atmel_SW_Framework/UTILS/LINKER_SCRIPTS/AT32UC3A/1256/IAR/lnkuc3a1256.xcl
@@ -0,0 +1,153 @@
+/******************************************************************************\r
+ * AVR32 AT32UC3A1256 XLINK command file for AVR32 IAR C/C++ Compiler.\r
+ *\r
+ * The assumed memory layout is the one of the AT32UC3A1256:\r
+ *\r
+ *   Start       Stop        Name     Type\r
+ *   ----------  ----------  -----    --------------\r
+ *   0x00000000  0x0000FFFF  SRAM     RAM\r
+ *   0x80000000  0x8003FFFF  FLASH    FLASH\r
+ *   0x80800000  0x808001FF  USER     FLASH\r
+ *\r
+ * Usage:  xlink  your_file(s)  -f xcl-file  libraries\r
+ *\r
+ * - Compiler:           IAR EWAVR32\r
+ * - Supported devices:  AVR32 AT32UC3A1256\r
+ *\r
+ * - author              Atmel Corporation: http://www.atmel.com \n\r
+ *                       Support and FAQ: http://support.atmel.no/\r
+ *\r
+ ******************************************************************************/\r
+\r
+/* Copyright (c) 2009 Atmel Corporation. All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice, this\r
+ * list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an Atmel\r
+ * AVR product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\r
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\r
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\r
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE\r
+ *\r
+ */\r
+\r
+/************************************************************************/\r
+/*      The following segments are defined in this link file:           */\r
+/*                                                                      */\r
+/*      Code segments                                                   */\r
+/*      CODE32    -- Program code used by __code32 functions.           */\r
+/*      RESET     -- Reset code.                                        */\r
+/*      EVSEG     -- Exception vector handlers.                         */\r
+/*                                                                      */\r
+/*      Constant segments                                               */\r
+/*      INITTAB   -- Segment initializer table.                         */\r
+/*      DIFUNCT   -- Dynamic initialization vector used by C++.         */\r
+/*      SWITCH    -- Switch tables.                                     */\r
+/*      ACTAB     -- Table of pointers to acall functions.              */\r
+/*                                                                      */\r
+/*      DATA21_ID -- Initialization data for DATA21_I.                  */\r
+/*      DATA32_ID -- Initialization data for DATA32_I.                  */\r
+/*      DATA32_C  -- Constant __data32 data.                            */\r
+/*                                                                      */\r
+/*      CHECKSUM  -- Checksum segment.                                  */\r
+/*                                                                      */\r
+/*      Data segments                                                   */\r
+/*      DATA21_I  -- Initialized __data21 data with non-zero            */\r
+/*                   initial value.                                     */\r
+/*      DATA32_I  -- Initialized __data32 data with non-zero            */\r
+/*                   initial value.                                     */\r
+/*      DATA21_Z  -- Initialized __data21 data with zero initial value. */\r
+/*      DATA32_Z  -- Initialized __data32 data with zero initial value. */\r
+/*      DATA21_N  -- Non-initialized __data21.                          */\r
+/*      DATA32_N  -- Non-initialized __data32.                          */\r
+/*      SSTACK    -- The system stack.                                  */\r
+/*      CSTACK    -- The application stack.                             */\r
+/*      HEAP      -- The heap used by malloc and free.                  */\r
+/*                                                                      */\r
+/************************************************************************/\r
+\r
+/************************************************************************/\r
+/*      Define CPU                                                      */\r
+/************************************************************************/\r
+\r
+-cavr32\r
+\r
+// Declare the IPR0 memory location\r
+-DIPR0=FFFF0800\r
+\r
+/************************************************************************/\r
+/*      Reset code is located at address 0x80000000 and up.             */\r
+/************************************************************************/\r
+\r
+-Z(CODE)RESET=80000000-8003FFFF\r
+\r
+/************************************************************************/\r
+/*      The exception handler code is located at address 0x80000000     */\r
+/*      and up. Make sure that the exception table gets properly        */\r
+/*      allocated. By using the special -Z@ allocation primitive, the   */\r
+/*      placement is guaranteed to be at _EVBASE and onwards.           */\r
+/************************************************************************/\r
+\r
+-Z@(CODE)EVTAB=80004000-8003FFFF\r
+-Z@(CODE)EV100=80004100-8003FFFF\r
+-P(CODE)EVSEG=80004000-8003FFFF\r
+\r
+/************************************************************************/\r
+/*      Allocate code and const segments.                               */\r
+/************************************************************************/\r
+\r
+-P(CODE)CODE32=80000000-8003FFFF\r
+-P(CONST)DATA32_C=80000000-8003FFFF\r
+-P(CONST)USERDATA32_C=80800000-808001FF\r
+\r
+// Initializers\r
+-Z(CONST)INITTAB,DIFUNCT=80000000-8003FFFF\r
+-Z(CONST)CHECKSUM,SWITCH=80000000-8003FFFF\r
+-Z(CONST)DATA21_ID,DATA32_ID=80000000-8003FFFF\r
+-Z(CONST)RAMCODE21_ID,RAMCODE32_ID=80000000-8003FFFF\r
+\r
+-Z(CONST)ACTAB,HTAB=80000000-8003FFFF\r
+\r
+/************************************************************************/\r
+/*      Allocate the read/write segments that are mapped to RAM.        */\r
+/************************************************************************/\r
+\r
+-Z(CODE)RAMCODE21=00000004-0000FFFF\r
+-Z(DATA)DATA21_I,DATA21_Z,DATA21_N=00000004-0000FFFF\r
+-Z(CODE)RAMCODE32=00000004-0000FFFF\r
+-Z(DATA)DATA32_I,DATA32_Z,DATA32_N=00000004-0000FFFF\r
+-Z(DATA)TRACEBUFFER=00000004-0000FFFF\r
+\r
+-Z(DATA)SSTACK+_SSTACK_SIZE#00000004-0000FFFF\r
+-Z(DATA)CSTACK+_CSTACK_SIZE#00000004-0000FFFF\r
+-Z(DATA)HEAP+_HEAP_SIZE=00000004-0000FFFF\r
+\r
+/************************************************************************/\r
+/*      Copy the RAMCODE bytes to the initializer segments.             */\r
+/************************************************************************/\r
+\r
+-QRAMCODE21=RAMCODE21_ID\r
+-QRAMCODE32=RAMCODE32_ID\r
+\r
+/************************************************************************/\r
+/*      End of File                                                     */\r
+/************************************************************************/\r

diff --git a/Demo/AVR32_UC3A_GCC/Atmel_SW_Framework/UTILS/LINKER_SCRIPTS/AT32UC3A/1512/GCC/link_uc3a1512.lds b/Demo/AVR32_UC3A_GCC/Atmel_SW_Framework/UTILS/LINKER_SCRIPTS/AT32UC3A/1512/GCC/link_uc3a1512.lds
new file mode 100644 (file)
index 0000000..03588f8
--- /dev/null
+++ b/Demo/AVR32_UC3A_GCC/Atmel_SW_Framework/UTILS/LINKER_SCRIPTS/AT32UC3A/1512/GCC/link_uc3a1512.lds
@@ -0,0 +1,266 @@
+/******************************************************************************
+ * AVR32 AT32UC3A1512 GNU LD script file.
+ *
+ * - Compiler:           GNU GCC for AVR32
+ * - Supported devices:  AVR32 AT32UC3A1512
+ *
+ * - author              Atmel Corporation: http://www.atmel.com \n
+ *                       Support and FAQ: http://support.atmel.no/
+ *
+ ******************************************************************************/
+
+/* Copyright (c) 2009 Atmel Corporation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an Atmel
+ * AVR product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
+ *
+ */
+
+OUTPUT_FORMAT("elf32-avr32", "elf32-avr32", "elf32-avr32")
+
+OUTPUT_ARCH(avr32:uc)
+
+ENTRY(_start)
+
+MEMORY
+{
+  FLASH (rxai!w) : ORIGIN = 0x80000000, LENGTH = 0x00080000
+  INTRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0x0000FFFC
+  USERPAGE : ORIGIN = 0x80800000, LENGTH = 0x00000200
+}
+
+PHDRS
+{
+  FLASH PT_LOAD;
+  INTRAM_ALIGN PT_NULL;
+  INTRAM_AT_FLASH PT_LOAD;
+  INTRAM PT_NULL;
+  USERPAGE PT_LOAD;
+}
+
+SECTIONS
+{
+  /* If this heap size is selected, all the INTRAM space from the end of the
+     data area to the beginning of the stack will be allocated for the heap. */
+  __max_heap_size__ = -1;
+
+  /* Use a default heap size if heap size was not defined. */
+  __heap_size__ = DEFINED(__heap_size__) ? __heap_size__ : __max_heap_size__;
+
+  /* Use a default stack size if stack size was not defined. */
+  __stack_size__ = DEFINED(__stack_size__) ? __stack_size__ : 4K;
+
+  /* Read-only sections, merged into text segment: */
+  PROVIDE (__executable_start = 0x80000000); . = 0x80000000;
+  .interp         : { *(.interp) } >FLASH AT>FLASH :FLASH
+  .reset : {  *(.reset) } >FLASH AT>FLASH :FLASH
+  .hash           : { *(.hash) } >FLASH AT>FLASH :FLASH
+  .dynsym         : { *(.dynsym) } >FLASH AT>FLASH :FLASH
+  .dynstr         : { *(.dynstr) } >FLASH AT>FLASH :FLASH
+  .gnu.version    : { *(.gnu.version) } >FLASH AT>FLASH :FLASH
+  .gnu.version_d  : { *(.gnu.version_d) } >FLASH AT>FLASH :FLASH
+  .gnu.version_r  : { *(.gnu.version_r) } >FLASH AT>FLASH :FLASH
+  .rel.init       : { *(.rel.init) } >FLASH AT>FLASH :FLASH
+  .rela.init      : { *(.rela.init) } >FLASH AT>FLASH :FLASH
+  .rel.text       : { *(.rel.text .rel.text.* .rel.gnu.linkonce.t.*) } >FLASH AT>FLASH :FLASH
+  .rela.text      : { *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*) } >FLASH AT>FLASH :FLASH
+  .rel.fini       : { *(.rel.fini) } >FLASH AT>FLASH :FLASH
+  .rela.fini      : { *(.rela.fini) } >FLASH AT>FLASH :FLASH
+  .rel.rodata     : { *(.rel.rodata .rel.rodata.* .rel.gnu.linkonce.r.*) } >FLASH AT>FLASH :FLASH
+  .rela.rodata    : { *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*) } >FLASH AT>FLASH :FLASH
+  .rel.data.rel.ro   : { *(.rel.data.rel.ro*) } >FLASH AT>FLASH :FLASH
+  .rela.data.rel.ro   : { *(.rel.data.rel.ro*) } >FLASH AT>FLASH :FLASH
+  .rel.data       : { *(.rel.data .rel.data.* .rel.gnu.linkonce.d.*) } >FLASH AT>FLASH :FLASH
+  .rela.data      : { *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*) } >FLASH AT>FLASH :FLASH
+  .rel.tdata     : { *(.rel.tdata .rel.tdata.* .rel.gnu.linkonce.td.*) } >FLASH AT>FLASH :FLASH
+  .rela.tdata    : { *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*) } >FLASH AT>FLASH :FLASH
+  .rel.tbss      : { *(.rel.tbss .rel.tbss.* .rel.gnu.linkonce.tb.*) } >FLASH AT>FLASH :FLASH
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+  .rel.ctors      : { *(.rel.ctors) } >FLASH AT>FLASH :FLASH
+  .rela.ctors     : { *(.rela.ctors) } >FLASH AT>FLASH :FLASH
+  .rel.dtors      : { *(.rel.dtors) } >FLASH AT>FLASH :FLASH
+  .rela.dtors     : { *(.rela.dtors) } >FLASH AT>FLASH :FLASH
+  .rel.got        : { *(.rel.got) } >FLASH AT>FLASH :FLASH
+  .rela.got       : { *(.rela.got) } >FLASH AT>FLASH :FLASH
+  .rel.bss        : { *(.rel.bss .rel.bss.* .rel.gnu.linkonce.b.*) } >FLASH AT>FLASH :FLASH
+  .rela.bss       : { *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*) } >FLASH AT>FLASH :FLASH
+  .rel.plt        : { *(.rel.plt) } >FLASH AT>FLASH :FLASH
+  .rela.plt       : { *(.rela.plt) } >FLASH AT>FLASH :FLASH
+  .init           :
+  {
+    KEEP (*(.init))
+  } >FLASH AT>FLASH :FLASH =0xd703d703
+  .plt            : { *(.plt) } >FLASH AT>FLASH :FLASH
+  .text           :
+  {
+    *(.text .stub .text.* .gnu.linkonce.t.*)
+    KEEP (*(.text.*personality*))
+    /* .gnu.warning sections are handled specially by elf32.em.  */
+    *(.gnu.warning)
+  } >FLASH AT>FLASH :FLASH =0xd703d703
+  .fini           :
+  {
+    KEEP (*(.fini))
+  } >FLASH AT>FLASH :FLASH =0xd703d703
+  PROVIDE (__etext = .);
+  PROVIDE (_etext = .);
+  PROVIDE (etext = .);
+  .rodata         : { *(.rodata .rodata.* .gnu.linkonce.r.*) } >FLASH AT>FLASH :FLASH
+  .rodata1        : { *(.rodata1) } >FLASH AT>FLASH :FLASH
+  .eh_frame_hdr : { *(.eh_frame_hdr) } >FLASH AT>FLASH :FLASH
+  .eh_frame       : ONLY_IF_RO { KEEP (*(.eh_frame)) } >FLASH AT>FLASH :FLASH
+  .gcc_except_table   : ONLY_IF_RO { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) } >FLASH AT>FLASH :FLASH
+  .lalign      : { . = ALIGN(8); PROVIDE(_data_lma = .); } >FLASH AT>FLASH :FLASH
+  . = ORIGIN(INTRAM);
+  .dalign      : { . = ALIGN(8); PROVIDE(_data = .); } >INTRAM AT>INTRAM :INTRAM_ALIGN
+  /* Exception handling  */
+  .eh_frame       : ONLY_IF_RW { KEEP (*(.eh_frame)) } >INTRAM AT>FLASH :INTRAM_AT_FLASH
+  .gcc_except_table   : ONLY_IF_RW { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) } >INTRAM AT>FLASH :INTRAM_AT_FLASH
+  /* Thread Local Storage sections  */
+  .tdata         : { *(.tdata .tdata.* .gnu.linkonce.td.*) } >INTRAM AT>FLASH :INTRAM_AT_FLASH
+  .tbss                  : { *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) } >INTRAM AT>FLASH :INTRAM_AT_FLASH
+  /* Ensure the __preinit_array_start label is properly aligned.  We
+     could instead move the label definition inside the section, but
+     the linker would then create the section even if it turns out to
+     be empty, which isn't pretty.  */
+  PROVIDE (__preinit_array_start = ALIGN(32 / 8));
+  .preinit_array     : { KEEP (*(.preinit_array)) } >INTRAM AT>FLASH :INTRAM_AT_FLASH
+  PROVIDE (__preinit_array_end = .);
+  PROVIDE (__init_array_start = .);
+  .init_array     : { KEEP (*(.init_array)) } >INTRAM AT>FLASH :INTRAM_AT_FLASH
+  PROVIDE (__init_array_end = .);
+  PROVIDE (__fini_array_start = .);
+  .fini_array     : { KEEP (*(.fini_array)) } >INTRAM AT>FLASH :INTRAM_AT_FLASH
+  PROVIDE (__fini_array_end = .);
+  .ctors          :
+  {
+    /* gcc uses crtbegin.o to find the start of
+       the constructors, so we make sure it is
+       first.  Because this is a wildcard, it
+       doesn't matter if the user does not
+       actually link against crtbegin.o; the
+       linker won't look for a file to match a
+       wildcard.  The wildcard also means that it
+       doesn't matter which directory crtbegin.o
+       is in.  */
+    KEEP (*crtbegin*.o(.ctors))
+    /* We don't want to include the .ctor section from
+       from the crtend.o file until after the sorted ctors.
+       The .ctor section from the crtend file contains the
+       end of ctors marker and it must be last */
+    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .ctors))
+    KEEP (*(SORT(.ctors.*)))
+    KEEP (*(.ctors))
+  } >INTRAM AT>FLASH :INTRAM_AT_FLASH
+  .dtors          :
+  {
+    KEEP (*crtbegin*.o(.dtors))
+    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .dtors))
+    KEEP (*(SORT(.dtors.*)))
+    KEEP (*(.dtors))
+  } >INTRAM AT>FLASH :INTRAM_AT_FLASH
+  .jcr            : { KEEP (*(.jcr)) } >INTRAM AT>FLASH :INTRAM_AT_FLASH
+  .data.rel.ro : { *(.data.rel.ro.local) *(.data.rel.ro*) } >INTRAM AT>FLASH :INTRAM_AT_FLASH
+  .dynamic        : { *(.dynamic) } >INTRAM AT>FLASH :INTRAM_AT_FLASH
+  .got            : { *(.got.plt) *(.got) } >INTRAM AT>FLASH :INTRAM_AT_FLASH
+  .ramtext        : { *(.ramtext .ramtext.*) } >INTRAM AT>FLASH :INTRAM_AT_FLASH
+  .ddalign     : { . = ALIGN(8); } >INTRAM AT>FLASH :INTRAM_AT_FLASH
+  .data           :
+  {
+    *(.data .data.* .gnu.linkonce.d.*)
+    KEEP (*(.gnu.linkonce.d.*personality*))
+    SORT(CONSTRUCTORS)
+  } >INTRAM AT>FLASH :INTRAM_AT_FLASH
+  .data1          : { *(.data1) } >INTRAM AT>FLASH :INTRAM_AT_FLASH
+  .balign      : { . = ALIGN(8); PROVIDE(_edata = .); } >INTRAM AT>FLASH :INTRAM_AT_FLASH
+  PROVIDE (edata = .);
+  __bss_start = .;
+  .bss            :
+  {
+    *(.dynbss)
+    *(.bss .bss.* .gnu.linkonce.b.*)
+    *(COMMON)
+    /* Align here to ensure that the .bss section occupies space up to
+       _end.  Align after .bss to ensure correct alignment even if the
+       .bss section disappears because there are no input sections.  */
+    . = ALIGN(8);
+  } >INTRAM AT>INTRAM :INTRAM
+  . = ALIGN(8);
+  _end = .;
+  PROVIDE (end = .);
+  __heap_start__ = ALIGN(8);
+  .heap           :
+  {
+    *(.heap)
+    . = (__heap_size__ == __max_heap_size__) ?
+        ORIGIN(INTRAM) + LENGTH(INTRAM) - __stack_size__ - ABSOLUTE(.) :
+        __heap_size__;
+  } >INTRAM AT>INTRAM :INTRAM
+  __heap_end__ = .;
+  /* Stabs debugging sections.  */
+  .stab          0 : { *(.stab) }
+  .stabstr       0 : { *(.stabstr) }
+  .stab.excl     0 : { *(.stab.excl) }
+  .stab.exclstr  0 : { *(.stab.exclstr) }
+  .stab.index    0 : { *(.stab.index) }
+  .stab.indexstr 0 : { *(.stab.indexstr) }
+  .comment       0 : { *(.comment) }
+  /* DWARF debug sections.
+     Symbols in the DWARF debugging sections are relative to the beginning
+     of the section so we begin them at 0.  */
+  /* DWARF 1 */
+  .debug          0 : { *(.debug) }
+  .line           0 : { *(.line) }
+  /* GNU DWARF 1 extensions */
+  .debug_srcinfo  0 : { *(.debug_srcinfo) }
+  .debug_sfnames  0 : { *(.debug_sfnames) }
+  /* DWARF 1.1 and DWARF 2 */
+  .debug_aranges  0 : { *(.debug_aranges) }
+  .debug_pubnames 0 : { *(.debug_pubnames) }
+  /* DWARF 2 */
+  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }
+  .debug_abbrev   0 : { *(.debug_abbrev) }
+  .debug_line     0 : { *(.debug_line) }
+  .debug_frame    0 : { *(.debug_frame) }
+  .debug_str      0 : { *(.debug_str) }
+  .debug_loc      0 : { *(.debug_loc) }
+  .debug_macinfo  0 : { *(.debug_macinfo) }
+  /* SGI/MIPS DWARF 2 extensions */
+  .debug_weaknames 0 : { *(.debug_weaknames) }
+  .debug_funcnames 0 : { *(.debug_funcnames) }
+  .debug_typenames 0 : { *(.debug_typenames) }
+  .debug_varnames  0 : { *(.debug_varnames) }
+  .stack         ORIGIN(INTRAM) + LENGTH(INTRAM) - __stack_size__ :
+  {
+    _stack = .;
+    *(.stack)
+    . = __stack_size__;
+    _estack = .;
+  } >INTRAM AT>INTRAM :INTRAM
+  .userpage       : { *(.userpage .userpage.*) } >USERPAGE AT>USERPAGE :USERPAGE
+  /DISCARD/ : { *(.note.GNU-stack) }
+}

diff --git a/Demo/AVR32_UC3A_GCC/Atmel_SW_Framework/UTILS/LINKER_SCRIPTS/AT32UC3A/1512/IAR/lnkuc3a1512.xcl b/Demo/AVR32_UC3A_GCC/Atmel_SW_Framework/UTILS/LINKER_SCRIPTS/AT32UC3A/1512/IAR/lnkuc3a1512.xcl
new file mode 100644 (file)
index 0000000..6aa01c6
--- /dev/null
+++ b/Demo/AVR32_UC3A_GCC/Atmel_SW_Framework/UTILS/LINKER_SCRIPTS/AT32UC3A/1512/IAR/lnkuc3a1512.xcl
@@ -0,0 +1,153 @@
+/******************************************************************************\r
+ * AVR32 AT32UC3A1512 XLINK command file for AVR32 IAR C/C++ Compiler.\r
+ *\r
+ * The assumed memory layout is the one of the AT32UC3A1512:\r
+ *\r
+ *   Start       Stop        Name     Type\r
+ *   ----------  ----------  -----    --------------\r
+ *   0x00000000  0x0000FFFF  SRAM     RAM\r
+ *   0x80000000  0x8007FFFF  FLASH    FLASH\r
+ *   0x80800000  0x808001FF  USER     FLASH\r
+ *\r
+ * Usage:  xlink  your_file(s)  -f xcl-file  libraries\r
+ *\r
+ * - Compiler:           IAR EWAVR32\r
+ * - Supported devices:  AVR32 AT32UC3A1512\r
+ *\r
+ * - author              Atmel Corporation: http://www.atmel.com \n\r
+ *                       Support and FAQ: http://support.atmel.no/\r
+ *\r
+ ******************************************************************************/\r
+\r
+/* Copyright (c) 2009 Atmel Corporation. All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice, this\r
+ * list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an Atmel\r
+ * AVR product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\r
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\r
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\r
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE\r
+ *\r
+ */\r
+\r
+/************************************************************************/\r
+/*      The following segments are defined in this link file:           */\r
+/*                                                                      */\r
+/*      Code segments                                                   */\r
+/*      CODE32    -- Program code used by __code32 functions.           */\r
+/*      RESET     -- Reset code.                                        */\r
+/*      EVSEG     -- Exception vector handlers.                         */\r
+/*                                                                      */\r
+/*      Constant segments                                               */\r
+/*      INITTAB   -- Segment initializer table.                         */\r
+/*      DIFUNCT   -- Dynamic initialization vector used by C++.         */\r
+/*      SWITCH    -- Switch tables.                                     */\r
+/*      ACTAB     -- Table of pointers to acall functions.              */\r
+/*                                                                      */\r
+/*      DATA21_ID -- Initialization data for DATA21_I.                  */\r
+/*      DATA32_ID -- Initialization data for DATA32_I.                  */\r
+/*      DATA32_C  -- Constant __data32 data.                            */\r
+/*                                                                      */\r
+/*      CHECKSUM  -- Checksum segment.                                  */\r
+/*                                                                      */\r
+/*      Data segments                                                   */\r
+/*      DATA21_I  -- Initialized __data21 data with non-zero            */\r
+/*                   initial value.                                     */\r
+/*      DATA32_I  -- Initialized __data32 data with non-zero            */\r
+/*                   initial value.                                     */\r
+/*      DATA21_Z  -- Initialized __data21 data with zero initial value. */\r
+/*      DATA32_Z  -- Initialized __data32 data with zero initial value. */\r
+/*      DATA21_N  -- Non-initialized __data21.                          */\r
+/*      DATA32_N  -- Non-initialized __data32.                          */\r
+/*      SSTACK    -- The system stack.                                  */\r
+/*      CSTACK    -- The application stack.                             */\r
+/*      HEAP      -- The heap used by malloc and free.                  */\r
+/*                                                                      */\r
+/************************************************************************/\r
+\r
+/************************************************************************/\r
+/*      Define CPU                                                      */\r
+/************************************************************************/\r
+\r
+-cavr32\r
+\r
+// Declare the IPR0 memory location\r
+-DIPR0=FFFF0800\r
+\r
+/************************************************************************/\r
+/*      Reset code is located at address 0x80000000 and up.             */\r
+/************************************************************************/\r
+\r
+-Z(CODE)RESET=80000000-8007FFFF\r
+\r
+/************************************************************************/\r
+/*      The exception handler code is located at address 0x80000000     */\r
+/*      and up. Make sure that the exception table gets properly        */\r
+/*      allocated. By using the special -Z@ allocation primitive, the   */\r
+/*      placement is guaranteed to be at _EVBASE and onwards.           */\r
+/************************************************************************/\r
+\r
+-Z@(CODE)EVTAB=80004000-8007FFFF\r
+-Z@(CODE)EV100=80004100-8007FFFF\r
+-P(CODE)EVSEG=80004000-8007FFFF\r
+\r
+/************************************************************************/\r
+/*      Allocate code and const segments.                               */\r
+/************************************************************************/\r
+\r
+-P(CODE)CODE32=80000000-8007FFFF\r
+-P(CONST)DATA32_C=80000000-8007FFFF\r
+-P(CONST)USERDATA32_C=80800000-808001FF\r
+\r
+// Initializers\r
+-Z(CONST)INITTAB,DIFUNCT=80000000-8007FFFF\r
+-Z(CONST)CHECKSUM,SWITCH=80000000-8007FFFF\r
+-Z(CONST)DATA21_ID,DATA32_ID=80000000-8007FFFF\r
+-Z(CONST)RAMCODE21_ID,RAMCODE32_ID=80000000-8007FFFF\r
+\r
+-Z(CONST)ACTAB,HTAB=80000000-8007FFFF\r
+\r
+/************************************************************************/\r
+/*      Allocate the read/write segments that are mapped to RAM.        */\r
+/************************************************************************/\r
+\r
+-Z(CODE)RAMCODE21=00000004-0000FFFF\r
+-Z(DATA)DATA21_I,DATA21_Z,DATA21_N=00000004-0000FFFF\r
+-Z(CODE)RAMCODE32=00000004-0000FFFF\r
+-Z(DATA)DATA32_I,DATA32_Z,DATA32_N=00000004-0000FFFF\r
+-Z(DATA)TRACEBUFFER=00000004-0000FFFF\r
+\r
+-Z(DATA)SSTACK+_SSTACK_SIZE#00000004-0000FFFF\r
+-Z(DATA)CSTACK+_CSTACK_SIZE#00000004-0000FFFF\r
+-Z(DATA)HEAP+_HEAP_SIZE=00000004-0000FFFF\r
+\r
+/************************************************************************/\r
+/*      Copy the RAMCODE bytes to the initializer segments.             */\r
+/************************************************************************/\r
+\r
+-QRAMCODE21=RAMCODE21_ID\r
+-QRAMCODE32=RAMCODE32_ID\r
+\r
+/************************************************************************/\r
+/*      End of File                                                     */\r
+/************************************************************************/\r

diff --git a/Demo/AVR32_UC3A_GCC/Atmel_SW_Framework/UTILS/PREPROCESSOR/mrepeat.h b/Demo/AVR32_UC3A_GCC/Atmel_SW_Framework/UTILS/PREPROCESSOR/mrepeat.h
new file mode 100644 (file)
index 0000000..45be184
--- /dev/null
+++ b/Demo/AVR32_UC3A_GCC/Atmel_SW_Framework/UTILS/PREPROCESSOR/mrepeat.h
@@ -0,0 +1,328 @@
+/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */\r
+
+/*This file is prepared for Doxygen automatic documentation generation.*/\r
+/*! \file *********************************************************************\r
+ *\r
+ * \brief Preprocessor macro repeating utils.\r
+ *\r
+ * - Compiler:           IAR EWAVR32 and GNU GCC for AVR32\r
+ * - Supported devices:  All AVR32 devices can be used.\r
+ *\r
+ * \author               Atmel Corporation: http://www.atmel.com \n\r
+ *                       Support and FAQ: http://support.atmel.no/\r
+ *\r
+ ******************************************************************************/\r
+\r
+/* Copyright (c) 2009 Atmel Corporation. All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice, this\r
+ * list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an Atmel\r
+ * AVR product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\r
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\r
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\r
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE\r
+ *\r
+ */\r
+\r
+#ifndef _MREPEAT_H_\r
+#define _MREPEAT_H_\r
+\r
+#include "preprocessor.h"\r
+\r
+\r
+//! Maximal number of repetitions supported by MREPEAT.\r
+#define MREPEAT_LIMIT   256\r
+\r
+/*! \brief Macro repeat.\r
+ *\r
+ * This macro represents a horizontal repetition construct.\r
+ *\r
+ * \param count  The number of repetitious calls to macro. Valid values range from 0 to MREPEAT_LIMIT.\r
+ * \param macro  A binary operation of the form macro(n, data). This macro is expanded by MREPEAT with\r
+ *               the current repetition number and the auxiliary data argument.\r
+ * \param data   Auxiliary data passed to macro.\r
+ *\r
+ * \return       <tt>macro(0, data) macro(1, data) ... macro(count - 1, data)</tt>\r
+ */\r
+#define MREPEAT(count, macro, data)         TPASTE2(MREPEAT, count)(macro, data)\r
+\r
+#define MREPEAT0(  macro, data)\r
+#define MREPEAT1(  macro, data)       MREPEAT0(  macro, data)   macro(  0, data)\r
+#define MREPEAT2(  macro, data)       MREPEAT1(  macro, data)   macro(  1, data)\r
+#define MREPEAT3(  macro, data)       MREPEAT2(  macro, data)   macro(  2, data)\r
+#define MREPEAT4(  macro, data)       MREPEAT3(  macro, data)   macro(  3, data)\r
+#define MREPEAT5(  macro, data)       MREPEAT4(  macro, data)   macro(  4, data)\r
+#define MREPEAT6(  macro, data)       MREPEAT5(  macro, data)   macro(  5, data)\r
+#define MREPEAT7(  macro, data)       MREPEAT6(  macro, data)   macro(  6, data)\r
+#define MREPEAT8(  macro, data)       MREPEAT7(  macro, data)   macro(  7, data)\r
+#define MREPEAT9(  macro, data)       MREPEAT8(  macro, data)   macro(  8, data)\r
+#define MREPEAT10( macro, data)       MREPEAT9(  macro, data)   macro(  9, data)\r
+#define MREPEAT11( macro, data)       MREPEAT10( macro, data)   macro( 10, data)\r
+#define MREPEAT12( macro, data)       MREPEAT11( macro, data)   macro( 11, data)\r
+#define MREPEAT13( macro, data)       MREPEAT12( macro, data)   macro( 12, data)\r
+#define MREPEAT14( macro, data)       MREPEAT13( macro, data)   macro( 13, data)\r
+#define MREPEAT15( macro, data)       MREPEAT14( macro, data)   macro( 14, data)\r
+#define MREPEAT16( macro, data)       MREPEAT15( macro, data)   macro( 15, data)\r
+#define MREPEAT17( macro, data)       MREPEAT16( macro, data)   macro( 16, data)\r
+#define MREPEAT18( macro, data)       MREPEAT17( macro, data)   macro( 17, data)\r
+#define MREPEAT19( macro, data)       MREPEAT18( macro, data)   macro( 18, data)\r
+#define MREPEAT20( macro, data)       MREPEAT19( macro, data)   macro( 19, data)\r
+#define MREPEAT21( macro, data)       MREPEAT20( macro, data)   macro( 20, data)\r
+#define MREPEAT22( macro, data)       MREPEAT21( macro, data)   macro( 21, data)\r
+#define MREPEAT23( macro, data)       MREPEAT22( macro, data)   macro( 22, data)\r
+#define MREPEAT24( macro, data)       MREPEAT23( macro, data)   macro( 23, data)\r
+#define MREPEAT25( macro, data)       MREPEAT24( macro, data)   macro( 24, data)\r
+#define MREPEAT26( macro, data)       MREPEAT25( macro, data)   macro( 25, data)\r
+#define MREPEAT27( macro, data)       MREPEAT26( macro, data)   macro( 26, data)\r
+#define MREPEAT28( macro, data)       MREPEAT27( macro, data)   macro( 27, data)\r
+#define MREPEAT29( macro, data)       MREPEAT28( macro, data)   macro( 28, data)\r
+#define MREPEAT30( macro, data)       MREPEAT29( macro, data)   macro( 29, data)\r
+#define MREPEAT31( macro, data)       MREPEAT30( macro, data)   macro( 30, data)\r
+#define MREPEAT32( macro, data)       MREPEAT31( macro, data)   macro( 31, data)\r
+#define MREPEAT33( macro, data)       MREPEAT32( macro, data)   macro( 32, data)\r
+#define MREPEAT34( macro, data)       MREPEAT33( macro, data)   macro( 33, data)\r
+#define MREPEAT35( macro, data)       MREPEAT34( macro, data)   macro( 34, data)\r
+#define MREPEAT36( macro, data)       MREPEAT35( macro, data)   macro( 35, data)\r
+#define MREPEAT37( macro, data)       MREPEAT36( macro, data)   macro( 36, data)\r
+#define MREPEAT38( macro, data)       MREPEAT37( macro, data)   macro( 37, data)\r
+#define MREPEAT39( macro, data)       MREPEAT38( macro, data)   macro( 38, data)\r
+#define MREPEAT40( macro, data)       MREPEAT39( macro, data)   macro( 39, data)\r
+#define MREPEAT41( macro, data)       MREPEAT40( macro, data)   macro( 40, data)\r
+#define MREPEAT42( macro, data)       MREPEAT41( macro, data)   macro( 41, data)\r
+#define MREPEAT43( macro, data)       MREPEAT42( macro, data)   macro( 42, data)\r
+#define MREPEAT44( macro, data)       MREPEAT43( macro, data)   macro( 43, data)\r
+#define MREPEAT45( macro, data)       MREPEAT44( macro, data)   macro( 44, data)\r
+#define MREPEAT46( macro, data)       MREPEAT45( macro, data)   macro( 45, data)\r
+#define MREPEAT47( macro, data)       MREPEAT46( macro, data)   macro( 46, data)\r
+#define MREPEAT48( macro, data)       MREPEAT47( macro, data)   macro( 47, data)\r
+#define MREPEAT49( macro, data)       MREPEAT48( macro, data)   macro( 48, data)\r
+#define MREPEAT50( macro, data)       MREPEAT49( macro, data)   macro( 49, data)\r
+#define MREPEAT51( macro, data)       MREPEAT50( macro, data)   macro( 50, data)\r
+#define MREPEAT52( macro, data)       MREPEAT51( macro, data)   macro( 51, data)\r
+#define MREPEAT53( macro, data)       MREPEAT52( macro, data)   macro( 52, data)\r
+#define MREPEAT54( macro, data)       MREPEAT53( macro, data)   macro( 53, data)\r
+#define MREPEAT55( macro, data)       MREPEAT54( macro, data)   macro( 54, data)\r
+#define MREPEAT56( macro, data)       MREPEAT55( macro, data)   macro( 55, data)\r
+#define MREPEAT57( macro, data)       MREPEAT56( macro, data)   macro( 56, data)\r
+#define MREPEAT58( macro, data)       MREPEAT57( macro, data)   macro( 57, data)\r
+#define MREPEAT59( macro, data)       MREPEAT58( macro, data)   macro( 58, data)\r
+#define MREPEAT60( macro, data)       MREPEAT59( macro, data)   macro( 59, data)\r
+#define MREPEAT61( macro, data)       MREPEAT60( macro, data)   macro( 60, data)\r
+#define MREPEAT62( macro, data)       MREPEAT61( macro, data)   macro( 61, data)\r
+#define MREPEAT63( macro, data)       MREPEAT62( macro, data)   macro( 62, data)\r
+#define MREPEAT64( macro, data)       MREPEAT63( macro, data)   macro( 63, data)\r
+#define MREPEAT65( macro, data)       MREPEAT64( macro, data)   macro( 64, data)\r
+#define MREPEAT66( macro, data)       MREPEAT65( macro, data)   macro( 65, data)\r
+#define MREPEAT67( macro, data)       MREPEAT66( macro, data)   macro( 66, data)\r
+#define MREPEAT68( macro, data)       MREPEAT67( macro, data)   macro( 67, data)\r
+#define MREPEAT69( macro, data)       MREPEAT68( macro, data)   macro( 68, data)\r
+#define MREPEAT70( macro, data)       MREPEAT69( macro, data)   macro( 69, data)\r
+#define MREPEAT71( macro, data)       MREPEAT70( macro, data)   macro( 70, data)\r
+#define MREPEAT72( macro, data)       MREPEAT71( macro, data)   macro( 71, data)\r
+#define MREPEAT73( macro, data)       MREPEAT72( macro, data)   macro( 72, data)\r
+#define MREPEAT74( macro, data)       MREPEAT73( macro, data)   macro( 73, data)\r
+#define MREPEAT75( macro, data)       MREPEAT74( macro, data)   macro( 74, data)\r
+#define MREPEAT76( macro, data)       MREPEAT75( macro, data)   macro( 75, data)\r
+#define MREPEAT77( macro, data)       MREPEAT76( macro, data)   macro( 76, data)\r
+#define MREPEAT78( macro, data)       MREPEAT77( macro, data)   macro( 77, data)\r
+#define MREPEAT79( macro, data)       MREPEAT78( macro, data)   macro( 78, data)\r
+#define MREPEAT80( macro, data)       MREPEAT79( macro, data)   macro( 79, data)\r
+#define MREPEAT81( macro, data)       MREPEAT80( macro, data)   macro( 80, data)\r
+#define MREPEAT82( macro, data)       MREPEAT81( macro, data)   macro( 81, data)\r
+#define MREPEAT83( macro, data)       MREPEAT82( macro, data)   macro( 82, data)\r
+#define MREPEAT84( macro, data)       MREPEAT83( macro, data)   macro( 83, data)\r
+#define MREPEAT85( macro, data)       MREPEAT84( macro, data)   macro( 84, data)\r
+#define MREPEAT86( macro, data)       MREPEAT85( macro, data)   macro( 85, data)\r
+#define MREPEAT87( macro, data)       MREPEAT86( macro, data)   macro( 86, data)\r
+#define MREPEAT88( macro, data)       MREPEAT87( macro, data)   macro( 87, data)\r
+#define MREPEAT89( macro, data)       MREPEAT88( macro, data)   macro( 88, data)\r
+#define MREPEAT90( macro, data)       MREPEAT89( macro, data)   macro( 89, data)\r
+#define MREPEAT91( macro, data)       MREPEAT90( macro, data)   macro( 90, data)\r
+#define MREPEAT92( macro, data)       MREPEAT91( macro, data)   macro( 91, data)\r
+#define MREPEAT93( macro, data)       MREPEAT92( macro, data)   macro( 92, data)\r
+#define MREPEAT94( macro, data)       MREPEAT93( macro, data)   macro( 93, data)\r
+#define MREPEAT95( macro, data)       MREPEAT94( macro, data)   macro( 94, data)\r
+#define MREPEAT96( macro, data)       MREPEAT95( macro, data)   macro( 95, data)\r
+#define MREPEAT97( macro, data)       MREPEAT96( macro, data)   macro( 96, data)\r
+#define MREPEAT98( macro, data)       MREPEAT97( macro, data)   macro( 97, data)\r
+#define MREPEAT99( macro, data)       MREPEAT98( macro, data)   macro( 98, data)\r
+#define MREPEAT100(macro, data)       MREPEAT99( macro, data)   macro( 99, data)\r
+#define MREPEAT101(macro, data)       MREPEAT100(macro, data)   macro(100, data)\r
+#define MREPEAT102(macro, data)       MREPEAT101(macro, data)   macro(101, data)\r
+#define MREPEAT103(macro, data)       MREPEAT102(macro, data)   macro(102, data)\r
+#define MREPEAT104(macro, data)       MREPEAT103(macro, data)   macro(103, data)\r
+#define MREPEAT105(macro, data)       MREPEAT104(macro, data)   macro(104, data)\r
+#define MREPEAT106(macro, data)       MREPEAT105(macro, data)   macro(105, data)\r
+#define MREPEAT107(macro, data)       MREPEAT106(macro, data)   macro(106, data)\r
+#define MREPEAT108(macro, data)       MREPEAT107(macro, data)   macro(107, data)\r
+#define MREPEAT109(macro, data)       MREPEAT108(macro, data)   macro(108, data)\r
+#define MREPEAT110(macro, data)       MREPEAT109(macro, data)   macro(109, data)\r
+#define MREPEAT111(macro, data)       MREPEAT110(macro, data)   macro(110, data)\r
+#define MREPEAT112(macro, data)       MREPEAT111(macro, data)   macro(111, data)\r
+#define MREPEAT113(macro, data)       MREPEAT112(macro, data)   macro(112, data)\r
+#define MREPEAT114(macro, data)       MREPEAT113(macro, data)   macro(113, data)\r
+#define MREPEAT115(macro, data)       MREPEAT114(macro, data)   macro(114, data)\r
+#define MREPEAT116(macro, data)       MREPEAT115(macro, data)   macro(115, data)\r
+#define MREPEAT117(macro, data)       MREPEAT116(macro, data)   macro(116, data)\r
+#define MREPEAT118(macro, data)       MREPEAT117(macro, data)   macro(117, data)\r
+#define MREPEAT119(macro, data)       MREPEAT118(macro, data)   macro(118, data)\r
+#define MREPEAT120(macro, data)       MREPEAT119(macro, data)   macro(119, data)\r
+#define MREPEAT121(macro, data)       MREPEAT120(macro, data)   macro(120, data)\r
+#define MREPEAT122(macro, data)       MREPEAT121(macro, data)   macro(121, data)\r
+#define MREPEAT123(macro, data)       MREPEAT122(macro, data)   macro(122, data)\r
+#define MREPEAT124(macro, data)       MREPEAT123(macro, data)   macro(123, data)\r
+#define MREPEAT125(macro, data)       MREPEAT124(macro, data)   macro(124, data)\r
+#define MREPEAT126(macro, data)       MREPEAT125(macro, data)   macro(125, data)\r
+#define MREPEAT127(macro, data)       MREPEAT126(macro, data)   macro(126, data)\r
+#define MREPEAT128(macro, data)       MREPEAT127(macro, data)   macro(127, data)\r
+#define MREPEAT129(macro, data)       MREPEAT128(macro, data)   macro(128, data)\r
+#define MREPEAT130(macro, data)       MREPEAT129(macro, data)   macro(129, data)\r
+#define MREPEAT131(macro, data)       MREPEAT130(macro, data)   macro(130, data)\r
+#define MREPEAT132(macro, data)       MREPEAT131(macro, data)   macro(131, data)\r
+#define MREPEAT133(macro, data)       MREPEAT132(macro, data)   macro(132, data)\r
+#define MREPEAT134(macro, data)       MREPEAT133(macro, data)   macro(133, data)\r
+#define MREPEAT135(macro, data)       MREPEAT134(macro, data)   macro(134, data)\r
+#define MREPEAT136(macro, data)       MREPEAT135(macro, data)   macro(135, data)\r
+#define MREPEAT137(macro, data)       MREPEAT136(macro, data)   macro(136, data)\r
+#define MREPEAT138(macro, data)       MREPEAT137(macro, data)   macro(137, data)\r
+#define MREPEAT139(macro, data)       MREPEAT138(macro, data)   macro(138, data)\r
+#define MREPEAT140(macro, data)       MREPEAT139(macro, data)   macro(139, data)\r
+#define MREPEAT141(macro, data)       MREPEAT140(macro, data)   macro(140, data)\r
+#define MREPEAT142(macro, data)       MREPEAT141(macro, data)   macro(141, data)\r
+#define MREPEAT143(macro, data)       MREPEAT142(macro, data)   macro(142, data)\r
+#define MREPEAT144(macro, data)       MREPEAT143(macro, data)   macro(143, data)\r
+#define MREPEAT145(macro, data)       MREPEAT144(macro, data)   macro(144, data)\r
+#define MREPEAT146(macro, data)       MREPEAT145(macro, data)   macro(145, data)\r
+#define MREPEAT147(macro, data)       MREPEAT146(macro, data)   macro(146, data)\r
+#define MREPEAT148(macro, data)       MREPEAT147(macro, data)   macro(147, data)\r
+#define MREPEAT149(macro, data)       MREPEAT148(macro, data)   macro(148, data)\r
+#define MREPEAT150(macro, data)       MREPEAT149(macro, data)   macro(149, data)\r
+#define MREPEAT151(macro, data)       MREPEAT150(macro, data)   macro(150, data)\r
+#define MREPEAT152(macro, data)       MREPEAT151(macro, data)   macro(151, data)\r
+#define MREPEAT153(macro, data)       MREPEAT152(macro, data)   macro(152, data)\r
+#define MREPEAT154(macro, data)       MREPEAT153(macro, data)   macro(153, data)\r
+#define MREPEAT155(macro, data)       MREPEAT154(macro, data)   macro(154, data)\r
+#define MREPEAT156(macro, data)       MREPEAT155(macro, data)   macro(155, data)\r
+#define MREPEAT157(macro, data)       MREPEAT156(macro, data)   macro(156, data)\r
+#define MREPEAT158(macro, data)       MREPEAT157(macro, data)   macro(157, data)\r
+#define MREPEAT159(macro, data)       MREPEAT158(macro, data)   macro(158, data)\r
+#define MREPEAT160(macro, data)       MREPEAT159(macro, data)   macro(159, data)\r
+#define MREPEAT161(macro, data)       MREPEAT160(macro, data)   macro(160, data)\r
+#define MREPEAT162(macro, data)       MREPEAT161(macro, data)   macro(161, data)\r
+#define MREPEAT163(macro, data)       MREPEAT162(macro, data)   macro(162, data)\r
+#define MREPEAT164(macro, data)       MREPEAT163(macro, data)   macro(163, data)\r
+#define MREPEAT165(macro, data)       MREPEAT164(macro, data)   macro(164, data)\r
+#define MREPEAT166(macro, data)       MREPEAT165(macro, data)   macro(165, data)\r
+#define MREPEAT167(macro, data)       MREPEAT166(macro, data)   macro(166, data)\r
+#define MREPEAT168(macro, data)       MREPEAT167(macro, data)   macro(167, data)\r
+#define MREPEAT169(macro, data)       MREPEAT168(macro, data)   macro(168, data)\r
+#define MREPEAT170(macro, data)       MREPEAT169(macro, data)   macro(169, data)\r
+#define MREPEAT171(macro, data)       MREPEAT170(macro, data)   macro(170, data)\r
+#define MREPEAT172(macro, data)       MREPEAT171(macro, data)   macro(171, data)\r
+#define MREPEAT173(macro, data)       MREPEAT172(macro, data)   macro(172, data)\r
+#define MREPEAT174(macro, data)       MREPEAT173(macro, data)   macro(173, data)\r
+#define MREPEAT175(macro, data)       MREPEAT174(macro, data)   macro(174, data)\r
+#define MREPEAT176(macro, data)       MREPEAT175(macro, data)   macro(175, data)\r
+#define MREPEAT177(macro, data)       MREPEAT176(macro, data)   macro(176, data)\r
+#define MREPEAT178(macro, data)       MREPEAT177(macro, data)   macro(177, data)\r
+#define MREPEAT179(macro, data)       MREPEAT178(macro, data)   macro(178, data)\r
+#define MREPEAT180(macro, data)       MREPEAT179(macro, data)   macro(179, data)\r
+#define MREPEAT181(macro, data)       MREPEAT180(macro, data)   macro(180, data)\r
+#define MREPEAT182(macro, data)       MREPEAT181(macro, data)   macro(181, data)\r
+#define MREPEAT183(macro, data)       MREPEAT182(macro, data)   macro(182, data)\r
+#define MREPEAT184(macro, data)       MREPEAT183(macro, data)   macro(183, data)\r
+#define MREPEAT185(macro, data)       MREPEAT184(macro, data)   macro(184, data)\r
+#define MREPEAT186(macro, data)       MREPEAT185(macro, data)   macro(185, data)\r
+#define MREPEAT187(macro, data)       MREPEAT186(macro, data)   macro(186, data)\r
+#define MREPEAT188(macro, data)       MREPEAT187(macro, data)   macro(187, data)\r
+#define MREPEAT189(macro, data)       MREPEAT188(macro, data)   macro(188, data)\r
+#define MREPEAT190(macro, data)       MREPEAT189(macro, data)   macro(189, data)\r
+#define MREPEAT191(macro, data)       MREPEAT190(macro, data)   macro(190, data)\r
+#define MREPEAT192(macro, data)       MREPEAT191(macro, data)   macro(191, data)\r
+#define MREPEAT193(macro, data)       MREPEAT192(macro, data)   macro(192, data)\r
+#define MREPEAT194(macro, data)       MREPEAT193(macro, data)   macro(193, data)\r
+#define MREPEAT195(macro, data)       MREPEAT194(macro, data)   macro(194, data)\r
+#define MREPEAT196(macro, data)       MREPEAT195(macro, data)   macro(195, data)\r
+#define MREPEAT197(macro, data)       MREPEAT196(macro, data)   macro(196, data)\r
+#define MREPEAT198(macro, data)       MREPEAT197(macro, data)   macro(197, data)\r
+#define MREPEAT199(macro, data)       MREPEAT198(macro, data)   macro(198, data)\r
+#define MREPEAT200(macro, data)       MREPEAT199(macro, data)   macro(199, data)\r
+#define MREPEAT201(macro, data)       MREPEAT200(macro, data)   macro(200, data)\r
+#define MREPEAT202(macro, data)       MREPEAT201(macro, data)   macro(201, data)\r
+#define MREPEAT203(macro, data)       MREPEAT202(macro, data)   macro(202, data)\r
+#define MREPEAT204(macro, data)       MREPEAT203(macro, data)   macro(203, data)\r
+#define MREPEAT205(macro, data)       MREPEAT204(macro, data)   macro(204, data)\r
+#define MREPEAT206(macro, data)       MREPEAT205(macro, data)   macro(205, data)\r
+#define MREPEAT207(macro, data)       MREPEAT206(macro, data)   macro(206, data)\r
+#define MREPEAT208(macro, data)       MREPEAT207(macro, data)   macro(207, data)\r
+#define MREPEAT209(macro, data)       MREPEAT208(macro, data)   macro(208, data)\r
+#define MREPEAT210(macro, data)       MREPEAT209(macro, data)   macro(209, data)\r
+#define MREPEAT211(macro, data)       MREPEAT210(macro, data)   macro(210, data)\r
+#define MREPEAT212(macro, data)       MREPEAT211(macro, data)   macro(211, data)\r
+#define MREPEAT213(macro, data)       MREPEAT212(macro, data)   macro(212, data)\r
+#define MREPEAT214(macro, data)       MREPEAT213(macro, data)   macro(213, data)\r
+#define MREPEAT215(macro, data)       MREPEAT214(macro, data)   macro(214, data)\r
+#define MREPEAT216(macro, data)       MREPEAT215(macro, data)   macro(215, data)\r
+#define MREPEAT217(macro, data)       MREPEAT216(macro, data)   macro(216, data)\r
+#define MREPEAT218(macro, data)       MREPEAT217(macro, data)   macro(217, data)\r
+#define MREPEAT219(macro, data)       MREPEAT218(macro, data)   macro(218, data)\r
+#define MREPEAT220(macro, data)       MREPEAT219(macro, data)   macro(219, data)\r
+#define MREPEAT221(macro, data)       MREPEAT220(macro, data)   macro(220, data)\r
+#define MREPEAT222(macro, data)       MREPEAT221(macro, data)   macro(221, data)\r
+#define MREPEAT223(macro, data)       MREPEAT222(macro, data)   macro(222, data)\r
+#define MREPEAT224(macro, data)       MREPEAT223(macro, data)   macro(223, data)\r
+#define MREPEAT225(macro, data)       MREPEAT224(macro, data)   macro(224, data)\r
+#define MREPEAT226(macro, data)       MREPEAT225(macro, data)   macro(225, data)\r
+#define MREPEAT227(macro, data)       MREPEAT226(macro, data)   macro(226, data)\r
+#define MREPEAT228(macro, data)       MREPEAT227(macro, data)   macro(227, data)\r
+#define MREPEAT229(macro, data)       MREPEAT228(macro, data)   macro(228, data)\r
+#define MREPEAT230(macro, data)       MREPEAT229(macro, data)   macro(229, data)\r
+#define MREPEAT231(macro, data)       MREPEAT230(macro, data)   macro(230, data)\r
+#define MREPEAT232(macro, data)       MREPEAT231(macro, data)   macro(231, data)\r
+#define MREPEAT233(macro, data)       MREPEAT232(macro, data)   macro(232, data)\r
+#define MREPEAT234(macro, data)       MREPEAT233(macro, data)   macro(233, data)\r
+#define MREPEAT235(macro, data)       MREPEAT234(macro, data)   macro(234, data)\r
+#define MREPEAT236(macro, data)       MREPEAT235(macro, data)   macro(235, data)\r
+#define MREPEAT237(macro, data)       MREPEAT236(macro, data)   macro(236, data)\r
+#define MREPEAT238(macro, data)       MREPEAT237(macro, data)   macro(237, data)\r
+#define MREPEAT239(macro, data)       MREPEAT238(macro, data)   macro(238, data)\r
+#define MREPEAT240(macro, data)       MREPEAT239(macro, data)   macro(239, data)\r
+#define MREPEAT241(macro, data)       MREPEAT240(macro, data)   macro(240, data)\r
+#define MREPEAT242(macro, data)       MREPEAT241(macro, data)   macro(241, data)\r
+#define MREPEAT243(macro, data)       MREPEAT242(macro, data)   macro(242, data)\r
+#define MREPEAT244(macro, data)       MREPEAT243(macro, data)   macro(243, data)\r
+#define MREPEAT245(macro, data)       MREPEAT244(macro, data)   macro(244, data)\r
+#define MREPEAT246(macro, data)       MREPEAT245(macro, data)   macro(245, data)\r
+#define MREPEAT247(macro, data)       MREPEAT246(macro, data)   macro(246, data)\r
+#define MREPEAT248(macro, data)       MREPEAT247(macro, data)   macro(247, data)\r
+#define MREPEAT249(macro, data)       MREPEAT248(macro, data)   macro(248, data)\r
+#define MREPEAT250(macro, data)       MREPEAT249(macro, data)   macro(249, data)\r
+#define MREPEAT251(macro, data)       MREPEAT250(macro, data)   macro(250, data)\r
+#define MREPEAT252(macro, data)       MREPEAT251(macro, data)   macro(251, data)\r
+#define MREPEAT253(macro, data)       MREPEAT252(macro, data)   macro(252, data)\r
+#define MREPEAT254(macro, data)       MREPEAT253(macro, data)   macro(253, data)\r
+#define MREPEAT255(macro, data)       MREPEAT254(macro, data)   macro(254, data)\r
+#define MREPEAT256(macro, data)       MREPEAT255(macro, data)   macro(255, data)\r
+\r
+\r
+#endif  // _MREPEAT_H_\r

diff --git a/Demo/AVR32_UC3A_GCC/Atmel_SW_Framework/UTILS/PREPROCESSOR/preprocessor.h b/Demo/AVR32_UC3A_GCC/Atmel_SW_Framework/UTILS/PREPROCESSOR/preprocessor.h
new file mode 100644 (file)
index 0000000..adf8e1d
--- /dev/null
+++ b/Demo/AVR32_UC3A_GCC/Atmel_SW_Framework/UTILS/PREPROCESSOR/preprocessor.h
@@ -0,0 +1,55 @@
+/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */\r
+
+/*This file is prepared for Doxygen automatic documentation generation.*/\r
+/*! \file *********************************************************************\r
+ *\r
+ * \brief Preprocessor utils.\r
+ *\r
+ * - Compiler:           IAR EWAVR32 and GNU GCC for AVR32\r
+ * - Supported devices:  All AVR32 devices can be used.\r
+ *\r
+ * \author               Atmel Corporation: http://www.atmel.com \n\r
+ *                       Support and FAQ: http://support.atmel.no/\r
+ *\r
+ ******************************************************************************/\r
+\r
+/* Copyright (c) 2009 Atmel Corporation. All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice, this\r
+ * list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an Atmel\r
+ * AVR product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\r
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\r
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\r
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE\r
+ *\r
+ */\r
+\r
+#ifndef _PREPROCESSOR_H_\r
+#define _PREPROCESSOR_H_\r
+\r
+#include "tpaste.h"\r
+#include "stringz.h"\r
+#include "mrepeat.h"\r
+\r
+\r
+#endif  // _PREPROCESSOR_H_\r

diff --git a/Demo/AVR32_UC3A_GCC/Atmel_SW_Framework/UTILS/PREPROCESSOR/stringz.h b/Demo/AVR32_UC3A_GCC/Atmel_SW_Framework/UTILS/PREPROCESSOR/stringz.h
new file mode 100644 (file)
index 0000000..153e07f
--- /dev/null
+++ b/Demo/AVR32_UC3A_GCC/Atmel_SW_Framework/UTILS/PREPROCESSOR/stringz.h
@@ -0,0 +1,75 @@
+/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */\r
+
+/*This file is prepared for Doxygen automatic documentation generation.*/\r
+/*! \file *********************************************************************\r
+ *\r
+ * \brief Preprocessor stringizing utils.\r
+ *\r
+ * - Compiler:           IAR EWAVR32 and GNU GCC for AVR32\r
+ * - Supported devices:  All AVR32 devices can be used.\r
+ *\r
+ * \author               Atmel Corporation: http://www.atmel.com \n\r
+ *                       Support and FAQ: http://support.atmel.no/\r
+ *\r
+ ******************************************************************************/\r
+\r
+/* Copyright (c) 2009 Atmel Corporation. All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice, this\r
+ * list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an Atmel\r
+ * AVR product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\r
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\r
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\r
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE\r
+ *\r
+ */\r
+\r
+#ifndef _STRINGZ_H_\r
+#define _STRINGZ_H_\r
+\r
+\r
+/*! \brief Stringize.\r
+ *\r
+ * Stringize a preprocessing token, this token being allowed to be \#defined.\r
+ *\r
+ * May be used only within macros with the token passed as an argument if the token is \#defined.\r
+ *\r
+ * For example, writing STRINGZ(PIN) within a macro \#defined by PIN_NAME(PIN)\r
+ * and invoked as PIN_NAME(PIN0) with PIN0 \#defined as A0 is equivalent to\r
+ * writing "A0".\r
+ */\r
+#define STRINGZ(x)                                #x\r
+\r
+/*! \brief Absolute stringize.\r
+ *\r
+ * Stringize a preprocessing token, this token being allowed to be \#defined.\r
+ *\r
+ * No restriction of use if the token is \#defined.\r
+ *\r
+ * For example, writing ASTRINGZ(PIN0) anywhere with PIN0 \#defined as A0 is\r
+ * equivalent to writing "A0".\r
+ */\r
+#define ASTRINGZ(x)                               STRINGZ(x)\r
+\r
+\r
+#endif  // _STRINGZ_H_\r

diff --git a/Demo/AVR32_UC3A_GCC/Atmel_SW_Framework/UTILS/PREPROCESSOR/tpaste.h b/Demo/AVR32_UC3A_GCC/Atmel_SW_Framework/UTILS/PREPROCESSOR/tpaste.h
new file mode 100644 (file)
index 0000000..cc46a5d
--- /dev/null
+++ b/Demo/AVR32_UC3A_GCC/Atmel_SW_Framework/UTILS/PREPROCESSOR/tpaste.h
@@ -0,0 +1,95 @@
+/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */\r
+
+/*This file is prepared for Doxygen automatic documentation generation.*/\r
+/*! \file *********************************************************************\r
+ *\r
+ * \brief Preprocessor token pasting utils.\r
+ *\r
+ * - Compiler:           IAR EWAVR32 and GNU GCC for AVR32\r
+ * - Supported devices:  All AVR32 devices can be used.\r
+ *\r
+ * \author               Atmel Corporation: http://www.atmel.com \n\r
+ *                       Support and FAQ: http://support.atmel.no/\r
+ *\r
+ ******************************************************************************/\r
+\r
+/* Copyright (c) 2009 Atmel Corporation. All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice, this\r
+ * list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an Atmel\r
+ * AVR product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\r
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\r
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\r
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE\r
+ *\r
+ */\r
+\r
+#ifndef _TPASTE_H_\r
+#define _TPASTE_H_\r
+\r
+\r
+/*! \name Token Paste\r
+ *\r
+ * Paste N preprocessing tokens together, these tokens being allowed to be \#defined.\r
+ *\r
+ * May be used only within macros with the tokens passed as arguments if the tokens are \#defined.\r
+ *\r
+ * For example, writing TPASTE2(U, WIDTH) within a macro \#defined by\r
+ * UTYPE(WIDTH) and invoked as UTYPE(UL_WIDTH) with UL_WIDTH \#defined as 32 is\r
+ * equivalent to writing U32.\r
+ */\r
+//! @{\r
+#define TPASTE2( a, b)                            a##b\r
+#define TPASTE3( a, b, c)                         a##b##c\r
+#define TPASTE4( a, b, c, d)                      a##b##c##d\r
+#define TPASTE5( a, b, c, d, e)                   a##b##c##d##e\r
+#define TPASTE6( a, b, c, d, e, f)                a##b##c##d##e##f\r
+#define TPASTE7( a, b, c, d, e, f, g)             a##b##c##d##e##f##g\r
+#define TPASTE8( a, b, c, d, e, f, g, h)          a##b##c##d##e##f##g##h\r
+#define TPASTE9( a, b, c, d, e, f, g, h, i)       a##b##c##d##e##f##g##h##i\r
+#define TPASTE10(a, b, c, d, e, f, g, h, i, j)    a##b##c##d##e##f##g##h##i##j\r
+//! @}\r
+\r
+/*! \name Absolute Token Paste\r
+ *\r
+ * Paste N preprocessing tokens together, these tokens being allowed to be \#defined.\r
+ *\r
+ * No restriction of use if the tokens are \#defined.\r
+ *\r
+ * For example, writing ATPASTE2(U, UL_WIDTH) anywhere with UL_WIDTH \#defined\r
+ * as 32 is equivalent to writing U32.\r
+ */\r
+//! @{\r
+#define ATPASTE2( a, b)                           TPASTE2( a, b)\r
+#define ATPASTE3( a, b, c)                        TPASTE3( a, b, c)\r
+#define ATPASTE4( a, b, c, d)                     TPASTE4( a, b, c, d)\r
+#define ATPASTE5( a, b, c, d, e)                  TPASTE5( a, b, c, d, e)\r
+#define ATPASTE6( a, b, c, d, e, f)               TPASTE6( a, b, c, d, e, f)\r
+#define ATPASTE7( a, b, c, d, e, f, g)            TPASTE7( a, b, c, d, e, f, g)\r
+#define ATPASTE8( a, b, c, d, e, f, g, h)         TPASTE8( a, b, c, d, e, f, g, h)\r
+#define ATPASTE9( a, b, c, d, e, f, g, h, i)      TPASTE9( a, b, c, d, e, f, g, h, i)\r
+#define ATPASTE10(a, b, c, d, e, f, g, h, i, j)   TPASTE10(a, b, c, d, e, f, g, h, i, j)\r
+//! @}\r
+\r
+\r
+#endif  // _TPASTE_H_\r

diff --git a/Demo/AVR32_UC3A_GCC/Atmel_SW_Framework/UTILS/compiler.h b/Demo/AVR32_UC3A_GCC/Atmel_SW_Framework/UTILS/compiler.h
new file mode 100644 (file)
index 0000000..655e1bc
--- /dev/null
+++ b/Demo/AVR32_UC3A_GCC/Atmel_SW_Framework/UTILS/compiler.h
@@ -0,0 +1,1145 @@
+/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */\r
+
+/*This file is prepared for Doxygen automatic documentation generation.*/\r
+/*! \file *********************************************************************\r
+ *\r
+ * \brief Compiler file for AVR32.\r
+ *\r
+ * This file defines commonly used types and macros.\r
+ *\r
+ * - Compiler:           IAR EWAVR32 and GNU GCC for AVR32\r
+ * - Supported devices:  All AVR32 devices can be used.\r
+ * - AppNote:\r
+ *\r
+ * \author               Atmel Corporation: http://www.atmel.com \n\r
+ *                       Support and FAQ: http://support.atmel.no/\r
+ *\r
+ ******************************************************************************/\r
+\r
+/* Copyright (c) 2009 Atmel Corporation. All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice, this\r
+ * list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an Atmel\r
+ * AVR product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\r
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\r
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\r
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE\r
+ *\r
+ */\r
+\r
+#ifndef _COMPILER_H_\r
+#define _COMPILER_H_\r
+\r
+#if ((defined __GNUC__) && (defined __AVR32__)) || (defined __ICCAVR32__ || defined __AAVR32__)\r
+#  include <avr32/io.h>\r
+#endif\r
+#if (defined __ICCAVR32__)\r
+#  include <intrinsics.h>\r
+#endif\r
+#include "preprocessor.h"\r
+\r
+#include "parts.h"\r
+\r
+\r
+//_____ D E C L A R A T I O N S ____________________________________________\r
+\r
+#ifdef __AVR32_ABI_COMPILER__ // Automatically defined when compiling for AVR32, not when assembling.\r
+\r
+#include <stddef.h>\r
+#include <stdlib.h>\r
+\r
+\r
+#if (defined __ICCAVR32__)\r
+\r
+/*! \name Compiler Keywords\r
+ *\r
+ * Port of some keywords from GNU GCC for AVR32 to IAR Embedded Workbench for Atmel AVR32.\r
+ */\r
+//! @{\r
+#define __asm__             asm\r
+#define __inline__          inline\r
+#define __volatile__\r
+//! @}\r
+\r
+#endif\r
+\r
+\r
+/*! \name Usual Types\r
+ */\r
+//! @{\r
+typedef unsigned char           Bool; //!< Boolean.\r
+#ifndef __cplusplus\r
+#if !defined(__bool_true_false_are_defined)\r
+typedef unsigned char           bool; //!< Boolean.\r
+#endif\r
+#endif\r
+typedef signed char             S8 ;  //!< 8-bit signed integer.\r
+typedef unsigned char           U8 ;  //!< 8-bit unsigned integer.\r
+typedef signed short int        S16;  //!< 16-bit signed integer.\r
+typedef unsigned short int      U16;  //!< 16-bit unsigned integer.\r
+typedef signed long int         S32;  //!< 32-bit signed integer.\r
+typedef unsigned long int       U32;  //!< 32-bit unsigned integer.\r
+typedef signed long long int    S64;  //!< 64-bit signed integer.\r
+typedef unsigned long long int  U64;  //!< 64-bit unsigned integer.\r
+typedef float                   F32;  //!< 32-bit floating-point number.\r
+typedef double                  F64;  //!< 64-bit floating-point number.\r
+//! @}\r
+\r
+\r
+/*! \name Status Types\r
+ */\r
+//! @{\r
+typedef Bool                Status_bool_t;  //!< Boolean status.\r
+typedef U8                  Status_t;       //!< 8-bit-coded status.\r
+//! @}\r
+\r
+\r
+/*! \name Aliasing Aggregate Types\r
+ */\r
+//! @{\r
+\r
+//! 16-bit union.\r
+typedef union\r
+{\r
+  S16 s16   ;\r
+  U16 u16   ;\r
+  S8  s8 [2];\r
+  U8  u8 [2];\r
+} Union16;\r
+\r
+//! 32-bit union.\r
+typedef union\r
+{\r
+  S32 s32   ;\r
+  U32 u32   ;\r
+  S16 s16[2];\r
+  U16 u16[2];\r
+  S8  s8 [4];\r
+  U8  u8 [4];\r
+} Union32;\r
+\r
+//! 64-bit union.\r
+typedef union\r
+{\r
+  S64 s64   ;\r
+  U64 u64   ;\r
+  S32 s32[2];\r
+  U32 u32[2];\r
+  S16 s16[4];\r
+  U16 u16[4];\r
+  S8  s8 [8];\r
+  U8  u8 [8];\r
+} Union64;\r
+\r
+//! Union of pointers to 64-, 32-, 16- and 8-bit unsigned integers.\r
+typedef union\r
+{\r
+  S64 *s64ptr;\r
+  U64 *u64ptr;\r
+  S32 *s32ptr;\r
+  U32 *u32ptr;\r
+  S16 *s16ptr;\r
+  U16 *u16ptr;\r
+  S8  *s8ptr ;\r
+  U8  *u8ptr ;\r
+} UnionPtr;\r
+\r
+//! Union of pointers to volatile 64-, 32-, 16- and 8-bit unsigned integers.\r
+typedef union\r
+{\r
+  volatile S64 *s64ptr;\r
+  volatile U64 *u64ptr;\r
+  volatile S32 *s32ptr;\r
+  volatile U32 *u32ptr;\r
+  volatile S16 *s16ptr;\r
+  volatile U16 *u16ptr;\r
+  volatile S8  *s8ptr ;\r
+  volatile U8  *u8ptr ;\r
+} UnionVPtr;\r
+\r
+//! Union of pointers to constant 64-, 32-, 16- and 8-bit unsigned integers.\r
+typedef union\r
+{\r
+  const S64 *s64ptr;\r
+  const U64 *u64ptr;\r
+  const S32 *s32ptr;\r
+  const U32 *u32ptr;\r
+  const S16 *s16ptr;\r
+  const U16 *u16ptr;\r
+  const S8  *s8ptr ;\r
+  const U8  *u8ptr ;\r
+} UnionCPtr;\r
+\r
+//! Union of pointers to constant volatile 64-, 32-, 16- and 8-bit unsigned integers.\r
+typedef union\r
+{\r
+  const volatile S64 *s64ptr;\r
+  const volatile U64 *u64ptr;\r
+  const volatile S32 *s32ptr;\r
+  const volatile U32 *u32ptr;\r
+  const volatile S16 *s16ptr;\r
+  const volatile U16 *u16ptr;\r
+  const volatile S8  *s8ptr ;\r
+  const volatile U8  *u8ptr ;\r
+} UnionCVPtr;\r
+\r
+//! Structure of pointers to 64-, 32-, 16- and 8-bit unsigned integers.\r
+typedef struct\r
+{\r
+  S64 *s64ptr;\r
+  U64 *u64ptr;\r
+  S32 *s32ptr;\r
+  U32 *u32ptr;\r
+  S16 *s16ptr;\r
+  U16 *u16ptr;\r
+  S8  *s8ptr ;\r
+  U8  *u8ptr ;\r
+} StructPtr;\r
+\r
+//! Structure of pointers to volatile 64-, 32-, 16- and 8-bit unsigned integers.\r
+typedef struct\r
+{\r
+  volatile S64 *s64ptr;\r
+  volatile U64 *u64ptr;\r
+  volatile S32 *s32ptr;\r
+  volatile U32 *u32ptr;\r
+  volatile S16 *s16ptr;\r
+  volatile U16 *u16ptr;\r
+  volatile S8  *s8ptr ;\r
+  volatile U8  *u8ptr ;\r
+} StructVPtr;\r
+\r
+//! Structure of pointers to constant 64-, 32-, 16- and 8-bit unsigned integers.\r
+typedef struct\r
+{\r
+  const S64 *s64ptr;\r
+  const U64 *u64ptr;\r
+  const S32 *s32ptr;\r
+  const U32 *u32ptr;\r
+  const S16 *s16ptr;\r
+  const U16 *u16ptr;\r
+  const S8  *s8ptr ;\r
+  const U8  *u8ptr ;\r
+} StructCPtr;\r
+\r
+//! Structure of pointers to constant volatile 64-, 32-, 16- and 8-bit unsigned integers.\r
+typedef struct\r
+{\r
+  const volatile S64 *s64ptr;\r
+  const volatile U64 *u64ptr;\r
+  const volatile S32 *s32ptr;\r
+  const volatile U32 *u32ptr;\r
+  const volatile S16 *s16ptr;\r
+  const volatile U16 *u16ptr;\r
+  const volatile S8  *s8ptr ;\r
+  const volatile U8  *u8ptr ;\r
+} StructCVPtr;\r
+\r
+//! @}\r
+\r
+#endif  // __AVR32_ABI_COMPILER__\r
+\r
+\r
+//_____ M A C R O S ________________________________________________________\r
+\r
+/*! \name Usual Constants\r
+ */\r
+//! @{\r
+#define DISABLE   0\r
+#define ENABLE    1\r
+#define DISABLED  0\r
+#define ENABLED   1\r
+#define OFF       0\r
+#define ON        1\r
+#define FALSE     0\r
+#define TRUE      1\r
+#ifndef __cplusplus\r
+#if !defined(__bool_true_false_are_defined)\r
+#define false     FALSE\r
+#define true      TRUE\r
+#endif\r
+#endif\r
+#define KO        0\r
+#define OK        1\r
+#define PASS      0\r
+#define FAIL      1\r
+#define LOW       0\r
+#define HIGH      1\r
+#define CLR       0\r
+#define SET       1\r
+//! @}\r
+\r
+\r
+#ifdef __AVR32_ABI_COMPILER__ // Automatically defined when compiling for AVR32, not when assembling.\r
+\r
+/*! \name Bit-Field Handling\r
+ */\r
+//! @{\r
+\r
+/*! \brief Reads the bits of a value specified by a given bit-mask.\r
+ *\r
+ * \param value Value to read bits from.\r
+ * \param mask  Bit-mask indicating bits to read.\r
+ *\r
+ * \return Read bits.\r
+ */\r
+#define Rd_bits( value, mask)        ((value) & (mask))\r
+\r
+/*! \brief Writes the bits of a C lvalue specified by a given bit-mask.\r
+ *\r
+ * \param lvalue  C lvalue to write bits to.\r
+ * \param mask    Bit-mask indicating bits to write.\r
+ * \param bits    Bits to write.\r
+ *\r
+ * \return Resulting value with written bits.\r
+ */\r
+#define Wr_bits(lvalue, mask, bits)  ((lvalue) = ((lvalue) & ~(mask)) |\\r
+                                                 ((bits  ) &  (mask)))\r
+\r
+/*! \brief Tests the bits of a value specified by a given bit-mask.\r
+ *\r
+ * \param value Value of which to test bits.\r
+ * \param mask  Bit-mask indicating bits to test.\r
+ *\r
+ * \return \c 1 if at least one of the tested bits is set, else \c 0.\r
+ */\r
+#define Tst_bits( value, mask)  (Rd_bits(value, mask) != 0)\r
+\r
+/*! \brief Clears the bits of a C lvalue specified by a given bit-mask.\r
+ *\r
+ * \param lvalue  C lvalue of which to clear bits.\r
+ * \param mask    Bit-mask indicating bits to clear.\r
+ *\r
+ * \return Resulting value with cleared bits.\r
+ */\r
+#define Clr_bits(lvalue, mask)  ((lvalue) &= ~(mask))\r
+\r
+/*! \brief Sets the bits of a C lvalue specified by a given bit-mask.\r
+ *\r
+ * \param lvalue  C lvalue of which to set bits.\r
+ * \param mask    Bit-mask indicating bits to set.\r
+ *\r
+ * \return Resulting value with set bits.\r
+ */\r
+#define Set_bits(lvalue, mask)  ((lvalue) |=  (mask))\r
+\r
+/*! \brief Toggles the bits of a C lvalue specified by a given bit-mask.\r
+ *\r
+ * \param lvalue  C lvalue of which to toggle bits.\r
+ * \param mask    Bit-mask indicating bits to toggle.\r
+ *\r
+ * \return Resulting value with toggled bits.\r
+ */\r
+#define Tgl_bits(lvalue, mask)  ((lvalue) ^=  (mask))\r
+\r
+/*! \brief Reads the bit-field of a value specified by a given bit-mask.\r
+ *\r
+ * \param value Value to read a bit-field from.\r
+ * \param mask  Bit-mask indicating the bit-field to read.\r
+ *\r
+ * \return Read bit-field.\r
+ */\r
+#define Rd_bitfield( value, mask)           (Rd_bits( value, mask) >> ctz(mask))\r
+\r
+/*! \brief Writes the bit-field of a C lvalue specified by a given bit-mask.\r
+ *\r
+ * \param lvalue    C lvalue to write a bit-field to.\r
+ * \param mask      Bit-mask indicating the bit-field to write.\r
+ * \param bitfield  Bit-field to write.\r
+ *\r
+ * \return Resulting value with written bit-field.\r
+ */\r
+#define Wr_bitfield(lvalue, mask, bitfield) (Wr_bits(lvalue, mask, (U32)(bitfield) << ctz(mask)))\r
+\r
+//! @}\r
+\r
+\r
+/*! \brief This macro is used to test fatal errors.\r
+ *\r
+ * The macro tests if the expression is FALSE. If it is, a fatal error is\r
+ * detected and the application hangs up.\r
+ *\r
+ * \param expr  Expression to evaluate and supposed to be nonzero.\r
+ */\r
+#ifdef _ASSERT_ENABLE_\r
+  #define Assert(expr) \\r
+  {\\r
+    if (!(expr)) while (TRUE);\\r
+  }\r
+#else\r
+  #define Assert(expr)\r
+#endif\r
+\r
+\r
+/*! \name Zero-Bit Counting\r
+ *\r
+ * Under AVR32-GCC, __builtin_clz and __builtin_ctz behave like macros when\r
+ * applied to constant expressions (values known at compile time), so they are\r
+ * more optimized than the use of the corresponding assembly instructions and\r
+ * they can be used as constant expressions e.g. to initialize objects having\r
+ * static storage duration, and like the corresponding assembly instructions\r
+ * when applied to non-constant expressions (values unknown at compile time), so\r
+ * they are more optimized than an assembly periphrasis. Hence, clz and ctz\r
+ * ensure a possible and optimized behavior for both constant and non-constant\r
+ * expressions.\r
+ */\r
+//! @{\r
+\r
+/*! \brief Counts the leading zero bits of the given value considered as a 32-bit integer.\r
+ *\r
+ * \param u Value of which to count the leading zero bits.\r
+ *\r
+ * \return The count of leading zero bits in \a u.\r
+ */\r
+#if (defined __GNUC__)\r
+  #define clz(u)              __builtin_clz(u)\r
+#elif (defined __ICCAVR32__)\r
+  #define clz(u)              __count_leading_zeros(u)\r
+#endif\r
+\r
+/*! \brief Counts the trailing zero bits of the given value considered as a 32-bit integer.\r
+ *\r
+ * \param u Value of which to count the trailing zero bits.\r
+ *\r
+ * \return The count of trailing zero bits in \a u.\r
+ */\r
+#if (defined __GNUC__)\r
+  #define ctz(u)              __builtin_ctz(u)\r
+#elif (defined __ICCAVR32__)\r
+  #define ctz(u)              __count_trailing_zeros(u)\r
+#endif\r
+\r
+//! @}\r
+\r
+\r
+/*! \name Bit Reversing\r
+ */\r
+//! @{\r
+\r
+/*! \brief Reverses the bits of \a u8.\r
+ *\r
+ * \param u8  U8 of which to reverse the bits.\r
+ *\r
+ * \return Value resulting from \a u8 with reversed bits.\r
+ */\r
+#define bit_reverse8(u8)    ((U8)(bit_reverse32((U8)(u8)) >> 24))\r
+\r
+/*! \brief Reverses the bits of \a u16.\r
+ *\r
+ * \param u16 U16 of which to reverse the bits.\r
+ *\r
+ * \return Value resulting from \a u16 with reversed bits.\r
+ */\r
+#define bit_reverse16(u16)  ((U16)(bit_reverse32((U16)(u16)) >> 16))\r
+\r
+/*! \brief Reverses the bits of \a u32.\r
+ *\r
+ * \param u32 U32 of which to reverse the bits.\r
+ *\r
+ * \return Value resulting from \a u32 with reversed bits.\r
+ */\r
+#if (defined __GNUC__)\r
+  #define bit_reverse32(u32) \\r
+  (\\r
+    {\\r
+      unsigned int __value = (U32)(u32);\\r
+      __asm__ ("brev\t%0" : "+r" (__value) :  : "cc");\\r
+      (U32)__value;\\r
+    }\\r
+  )\r
+#elif (defined __ICCAVR32__)\r
+  #define bit_reverse32(u32)  ((U32)__bit_reverse((U32)(u32)))\r
+#endif\r
+\r
+/*! \brief Reverses the bits of \a u64.\r
+ *\r
+ * \param u64 U64 of which to reverse the bits.\r
+ *\r
+ * \return Value resulting from \a u64 with reversed bits.\r
+ */\r
+#define bit_reverse64(u64)  ((U64)(((U64)bit_reverse32((U64)(u64) >> 32)) |\\r
+                                   ((U64)bit_reverse32((U64)(u64)) << 32)))\r
+\r
+//! @}\r
+\r
+\r
+/*! \name Alignment\r
+ */\r
+//! @{\r
+\r
+/*! \brief Tests alignment of the number \a val with the \a n boundary.\r
+ *\r
+ * \param val Input value.\r
+ * \param n   Boundary.\r
+ *\r
+ * \return \c 1 if the number \a val is aligned with the \a n boundary, else \c 0.\r
+ */\r
+#define Test_align(val, n     ) (!Tst_bits( val, (n) - 1     )   )\r
+\r
+/*! \brief Gets alignment of the number \a val with respect to the \a n boundary.\r
+ *\r
+ * \param val Input value.\r
+ * \param n   Boundary.\r
+ *\r
+ * \return Alignment of the number \a val with respect to the \a n boundary.\r
+ */\r
+#define Get_align( val, n     ) (  Rd_bits( val, (n) - 1     )   )\r
+\r
+/*! \brief Sets alignment of the lvalue number \a lval to \a alg with respect to the \a n boundary.\r
+ *\r
+ * \param lval  Input/output lvalue.\r
+ * \param n     Boundary.\r
+ * \param alg   Alignment.\r
+ *\r
+ * \return New value of \a lval resulting from its alignment set to \a alg with respect to the \a n boundary.\r
+ */\r
+#define Set_align(lval, n, alg) (  Wr_bits(lval, (n) - 1, alg)   )\r
+\r
+/*! \brief Aligns the number \a val with the upper \a n boundary.\r
+ *\r
+ * \param val Input value.\r
+ * \param n   Boundary.\r
+ *\r
+ * \return Value resulting from the number \a val aligned with the upper \a n boundary.\r
+ */\r
+#define Align_up(  val, n     ) (((val) + ((n) - 1)) & ~((n) - 1))\r
+\r
+/*! \brief Aligns the number \a val with the lower \a n boundary.\r
+ *\r
+ * \param val Input value.\r
+ * \param n   Boundary.\r
+ *\r
+ * \return Value resulting from the number \a val aligned with the lower \a n boundary.\r
+ */\r
+#define Align_down(val, n     ) ( (val)              & ~((n) - 1))\r
+\r
+//! @}\r
+\r
+\r
+/*! \name Mathematics\r
+ *\r
+ * The same considerations as for clz and ctz apply here but AVR32-GCC does not\r
+ * provide built-in functions to access the assembly instructions abs, min and\r
+ * max and it does not produce them by itself in most cases, so two sets of\r
+ * macros are defined here:\r
+ *   - Abs, Min and Max to apply to constant expressions (values known at\r
+ *     compile time);\r
+ *   - abs, min and max to apply to non-constant expressions (values unknown at\r
+ *     compile time).\r
+ */\r
+//! @{\r
+\r
+/*! \brief Takes the absolute value of \a a.\r
+ *\r
+ * \param a Input value.\r
+ *\r
+ * \return Absolute value of \a a.\r
+ *\r
+ * \note More optimized if only used with values known at compile time.\r
+ */\r
+#define Abs(a)              (((a) <  0 ) ? -(a) : (a))\r
+\r
+/*! \brief Takes the minimal value of \a a and \a b.\r
+ *\r
+ * \param a Input value.\r
+ * \param b Input value.\r
+ *\r
+ * \return Minimal value of \a a and \a b.\r
+ *\r
+ * \note More optimized if only used with values known at compile time.\r
+ */\r
+#define Min(a, b)           (((a) < (b)) ?  (a) : (b))\r
+\r
+/*! \brief Takes the maximal value of \a a and \a b.\r
+ *\r
+ * \param a Input value.\r
+ * \param b Input value.\r
+ *\r
+ * \return Maximal value of \a a and \a b.\r
+ *\r
+ * \note More optimized if only used with values known at compile time.\r
+ */\r
+#define Max(a, b)           (((a) > (b)) ?  (a) : (b))\r
+\r
+/*! \brief Takes the absolute value of \a a.\r
+ *\r
+ * \param a Input value.\r
+ *\r
+ * \return Absolute value of \a a.\r
+ *\r
+ * \note More optimized if only used with values unknown at compile time.\r
+ */\r
+#if (defined __GNUC__)\r
+  #define abs(a) \\r
+  (\\r
+    {\\r
+      int __value = (a);\\r
+      __asm__ ("abs\t%0" : "+r" (__value) :  : "cc");\\r
+      __value;\\r
+    }\\r
+  )\r
+#elif (defined __ICCAVR32__)\r
+  #define abs(a)      Abs(a)\r
+#endif\r
+\r
+/*! \brief Takes the minimal value of \a a and \a b.\r
+ *\r
+ * \param a Input value.\r
+ * \param b Input value.\r
+ *\r
+ * \return Minimal value of \a a and \a b.\r
+ *\r
+ * \note More optimized if only used with values unknown at compile time.\r
+ */\r
+#if (defined __GNUC__)\r
+  #define min(a, b) \\r
+  (\\r
+    {\\r
+      int __value, __arg_a = (a), __arg_b = (b);\\r
+      __asm__ ("min\t%0, %1, %2" : "=r" (__value) : "r" (__arg_a), "r" (__arg_b));\\r
+      __value;\\r
+    }\\r
+  )\r
+#elif (defined __ICCAVR32__)\r
+  #define min(a, b)   __min(a, b)\r
+#endif\r
+\r
+/*! \brief Takes the maximal value of \a a and \a b.\r
+ *\r
+ * \param a Input value.\r
+ * \param b Input value.\r
+ *\r
+ * \return Maximal value of \a a and \a b.\r
+ *\r
+ * \note More optimized if only used with values unknown at compile time.\r
+ */\r
+#if (defined __GNUC__)\r
+  #define max(a, b) \\r
+  (\\r
+    {\\r
+      int __value, __arg_a = (a), __arg_b = (b);\\r
+      __asm__ ("max\t%0, %1, %2" : "=r" (__value) : "r" (__arg_a), "r" (__arg_b));\\r
+      __value;\\r
+    }\\r
+  )\r
+#elif (defined __ICCAVR32__)\r
+  #define max(a, b)   __max(a, b)\r
+#endif\r
+\r
+//! @}\r
+\r
+\r
+/*! \brief Calls the routine at address \a addr.\r
+ *\r
+ * It generates a long call opcode.\r
+ *\r
+ * For example, `Long_call(0x80000000)' generates a software reset on a UC3 if\r
+ * it is invoked from the CPU supervisor mode.\r
+ *\r
+ * \param addr  Address of the routine to call.\r
+ *\r
+ * \note It may be used as a long jump opcode in some special cases.\r
+ */\r
+#define Long_call(addr)                   ((*(void (*)(void))(addr))())\r
+\r
+/*! \brief Resets the CPU by software.\r
+ *\r
+ * \warning It shall not be called from the CPU application mode.\r
+ */\r
+#if (defined __GNUC__)\r
+  #define Reset_CPU() \\r
+  (\\r
+    {\\r
+      __asm__ __volatile__ (\\r
+        "lddpc   r9, 3f\n\t"\\r
+        "mfsr    r8, %[SR]\n\t"\\r
+        "bfextu  r8, r8, %[SR_M_OFFSET], %[SR_M_SIZE]\n\t"\\r
+        "cp.w    r8, 0b001\n\t"\\r
+        "breq    0f\n\t"\\r
+        "sub     r8, pc, $ - 1f\n\t"\\r
+        "pushm   r8-r9\n\t"\\r
+        "rete\n"\\r
+        "0:\n\t"\\r
+        "mtsr    %[SR], r9\n"\\r
+        "1:\n\t"\\r
+        "mov     r0, 0\n\t"\\r
+        "mov     r1, 0\n\t"\\r
+        "mov     r2, 0\n\t"\\r
+        "mov     r3, 0\n\t"\\r
+        "mov     r4, 0\n\t"\\r
+        "mov     r5, 0\n\t"\\r
+        "mov     r6, 0\n\t"\\r
+        "mov     r7, 0\n\t"\\r
+        "mov     r8, 0\n\t"\\r
+        "mov     r9, 0\n\t"\\r
+        "mov     r10, 0\n\t"\\r
+        "mov     r11, 0\n\t"\\r
+        "mov     r12, 0\n\t"\\r
+        "mov     sp, 0\n\t"\\r
+        "stdsp   sp[0], sp\n\t"\\r
+        "ldmts   sp, sp\n\t"\\r
+        "mov     lr, 0\n\t"\\r
+        "lddpc   pc, 2f\n\t"\\r
+        ".balign 4\n"\\r
+        "2:\n\t"\\r
+        ".word   _start\n"\\r
+        "3:\n\t"\\r
+        ".word   %[RESET_SR]"\\r
+        :\\r
+        : [SR] "i" (AVR32_SR),\\r
+          [SR_M_OFFSET] "i" (AVR32_SR_M_OFFSET),\\r
+          [SR_M_SIZE] "i" (AVR32_SR_M_SIZE),\\r
+          [RESET_SR] "i" (AVR32_SR_GM_MASK | AVR32_SR_EM_MASK | (AVR32_SR_M_SUP << AVR32_SR_M_OFFSET))\\r
+      );\\r
+    }\\r
+  )\r
+#elif (defined __ICCAVR32__)\r
+  #define Reset_CPU() \\r
+  {\\r
+    extern void *volatile __program_start;\\r
+    __asm__ __volatile__ (\\r
+      "mov     r7, LWRD(__program_start)\n\t"\\r
+      "orh     r7, HWRD(__program_start)\n\t"\\r
+      "mov     r9, LWRD("ASTRINGZ(AVR32_SR_GM_MASK | AVR32_SR_EM_MASK | (AVR32_SR_M_SUP << AVR32_SR_M_OFFSET))")\n\t"\\r
+      "orh     r9, HWRD("ASTRINGZ(AVR32_SR_GM_MASK | AVR32_SR_EM_MASK | (AVR32_SR_M_SUP << AVR32_SR_M_OFFSET))")\n\t"\\r
+      "mfsr    r8, "ASTRINGZ(AVR32_SR)"\n\t"\\r
+      "bfextu  r8, r8, "ASTRINGZ(AVR32_SR_M_OFFSET)", "ASTRINGZ(AVR32_SR_M_SIZE)"\n\t"\\r
+      "cp.w    r8, 001b\n\t"\\r
+      "breq    $ + 10\n\t"\\r
+      "sub     r8, pc, -12\n\t"\\r
+      "pushm   r8-r9\n\t"\\r
+      "rete\n\t"\\r
+      "mtsr    "ASTRINGZ(AVR32_SR)", r9\n\t"\\r
+      "mov     r0, 0\n\t"\\r
+      "mov     r1, 0\n\t"\\r
+      "mov     r2, 0\n\t"\\r
+      "mov     r3, 0\n\t"\\r
+      "mov     r4, 0\n\t"\\r
+      "mov     r5, 0\n\t"\\r
+      "mov     r6, 0\n\t"\\r
+      "st.w    r0[4], r7\n\t"\\r
+      "mov     r7, 0\n\t"\\r
+      "mov     r8, 0\n\t"\\r
+      "mov     r9, 0\n\t"\\r
+      "mov     r10, 0\n\t"\\r
+      "mov     r11, 0\n\t"\\r
+      "mov     r12, 0\n\t"\\r
+      "mov     sp, 0\n\t"\\r
+      "stdsp   sp[0], sp\n\t"\\r
+      "ldmts   sp, sp\n\t"\\r
+      "mov     lr, 0\n\t"\\r
+      "ld.w    pc, lr[4]"\\r
+    );\\r
+    __program_start;\\r
+  }\r
+#endif\r
+\r
+\r
+/*! \name System Register Access\r
+ */\r
+//! @{\r
+\r
+/*! \brief Gets the value of the \a sysreg system register.\r
+ *\r
+ * \param sysreg  Address of the system register of which to get the value.\r
+ *\r
+ * \return Value of the \a sysreg system register.\r
+ */\r
+#if (defined __GNUC__)\r
+  #define Get_system_register(sysreg)         __builtin_mfsr(sysreg)\r
+#elif (defined __ICCAVR32__)\r
+  #define Get_system_register(sysreg)         __get_system_register(sysreg)\r
+#endif\r
+\r
+/*! \brief Sets the value of the \a sysreg system register to \a value.\r
+ *\r
+ * \param sysreg  Address of the system register of which to set the value.\r
+ * \param value   Value to set the \a sysreg system register to.\r
+ */\r
+#if (defined __GNUC__)\r
+  #define Set_system_register(sysreg, value)  __builtin_mtsr(sysreg, value)\r
+#elif (defined __ICCAVR32__)\r
+  #define Set_system_register(sysreg, value)  __set_system_register(sysreg, value)\r
+#endif\r
+\r
+//! @}\r
+\r
+\r
+/*! \name CPU Status Register Access\r
+ */\r
+//! @{\r
+\r
+/*! \brief Tells whether exceptions are globally enabled.\r
+ *\r
+ * \return \c 1 if exceptions are globally enabled, else \c 0.\r
+ */\r
+#define Is_global_exception_enabled()         (!Tst_bits(Get_system_register(AVR32_SR), AVR32_SR_EM_MASK))\r
+\r
+/*! \brief Disables exceptions globally.\r
+ */\r
+#if (defined __GNUC__)\r
+  #define Disable_global_exception()          ({__asm__ __volatile__ ("ssrf\t%0" :  : "i" (AVR32_SR_EM_OFFSET));})\r
+#elif (defined __ICCAVR32__)\r
+  #define Disable_global_exception()          (__set_status_flag(AVR32_SR_EM_OFFSET))\r
+#endif\r
+\r
+/*! \brief Enables exceptions globally.\r
+ */\r
+#if (defined __GNUC__)\r
+  #define Enable_global_exception()           ({__asm__ __volatile__ ("csrf\t%0" :  : "i" (AVR32_SR_EM_OFFSET));})\r
+#elif (defined __ICCAVR32__)\r
+  #define Enable_global_exception()           (__clear_status_flag(AVR32_SR_EM_OFFSET))\r
+#endif\r
+\r
+/*! \brief Tells whether interrupts are globally enabled.\r
+ *\r
+ * \return \c 1 if interrupts are globally enabled, else \c 0.\r
+ */\r
+#define Is_global_interrupt_enabled()         (!Tst_bits(Get_system_register(AVR32_SR), AVR32_SR_GM_MASK))\r
+\r
+/*! \brief Disables interrupts globally.\r
+ */\r
+#if (defined __GNUC__)\r
+  #define Disable_global_interrupt()          ({__asm__ __volatile__ ("ssrf\t%0" :  : "i" (AVR32_SR_GM_OFFSET));})\r
+#elif (defined __ICCAVR32__)\r
+  #define Disable_global_interrupt()          (__disable_interrupt())\r
+#endif\r
+\r
+/*! \brief Enables interrupts globally.\r
+ */\r
+#if (defined __GNUC__)\r
+  #define Enable_global_interrupt()           ({__asm__ __volatile__ ("csrf\t%0" :  : "i" (AVR32_SR_GM_OFFSET));})\r
+#elif (defined __ICCAVR32__)\r
+  #define Enable_global_interrupt()           (__enable_interrupt())\r
+#endif\r
+\r
+/*! \brief Tells whether interrupt level \a int_level is enabled.\r
+ *\r
+ * \param int_level Interrupt level (0 to 3).\r
+ *\r
+ * \return \c 1 if interrupt level \a int_level is enabled, else \c 0.\r
+ */\r
+#define Is_interrupt_level_enabled(int_level) (!Tst_bits(Get_system_register(AVR32_SR), TPASTE3(AVR32_SR_I, int_level, M_MASK)))\r
+\r
+/*! \brief Disables interrupt level \a int_level.\r
+ *\r
+ * \param int_level Interrupt level to disable (0 to 3).\r
+ */\r
+#if (defined __GNUC__)\r
+  #define Disable_interrupt_level(int_level)  ({__asm__ __volatile__ ("ssrf\t%0" :  : "i" (TPASTE3(AVR32_SR_I, int_level, M_OFFSET)));})\r
+#elif (defined __ICCAVR32__)\r
+  #define Disable_interrupt_level(int_level)  (__set_status_flag(TPASTE3(AVR32_SR_I, int_level, M_OFFSET)))\r
+#endif\r
+\r
+/*! \brief Enables interrupt level \a int_level.\r
+ *\r
+ * \param int_level Interrupt level to enable (0 to 3).\r
+ */\r
+#if (defined __GNUC__)\r
+  #define Enable_interrupt_level(int_level)   ({__asm__ __volatile__ ("csrf\t%0" :  : "i" (TPASTE3(AVR32_SR_I, int_level, M_OFFSET)));})\r
+#elif (defined __ICCAVR32__)\r
+  #define Enable_interrupt_level(int_level)   (__clear_status_flag(TPASTE3(AVR32_SR_I, int_level, M_OFFSET)))\r
+#endif\r
+\r
+/*! \brief Protects subsequent code from interrupts.\r
+ */\r
+#define AVR32_ENTER_CRITICAL_REGION( ) \\r
+  { \\r
+  Bool global_interrupt_enabled = Is_global_interrupt_enabled(); \\r
+  Disable_global_interrupt(); // Disable the appropriate interrupts.\r
+\r
+/*! \brief This macro must always be used in conjunction with AVR32_ENTER_CRITICAL_REGION\r
+ *         so that interrupts are enabled again.\r
+ */\r
+#define AVR32_LEAVE_CRITICAL_REGION( ) \\r
+  if (global_interrupt_enabled) Enable_global_interrupt(); \\r
+  }\r
+\r
+//! @}\r
+\r
+\r
+/*! \name Debug Register Access\r
+ */\r
+//! @{\r
+\r
+/*! \brief Gets the value of the \a dbgreg debug register.\r
+ *\r
+ * \param dbgreg  Address of the debug register of which to get the value.\r
+ *\r
+ * \return Value of the \a dbgreg debug register.\r
+ */\r
+#if (defined __GNUC__)\r
+  #define Get_debug_register(dbgreg)          __builtin_mfdr(dbgreg)\r
+#elif (defined __ICCAVR32__)\r
+  #define Get_debug_register(dbgreg)          __get_debug_register(dbgreg)\r
+#endif\r
+\r
+/*! \brief Sets the value of the \a dbgreg debug register to \a value.\r
+ *\r
+ * \param dbgreg  Address of the debug register of which to set the value.\r
+ * \param value   Value to set the \a dbgreg debug register to.\r
+ */\r
+#if (defined __GNUC__)\r
+  #define Set_debug_register(dbgreg, value)   __builtin_mtdr(dbgreg, value)\r
+#elif (defined __ICCAVR32__)\r
+  #define Set_debug_register(dbgreg, value)   __set_debug_register(dbgreg, value)\r
+#endif\r
+\r
+//! @}\r
+\r
+#endif  // __AVR32_ABI_COMPILER__\r
+\r
+\r
+//! Boolean evaluating MCU little endianism.\r
+#if ((defined __GNUC__) && (defined __AVR32__)) || ((defined __ICCAVR32__) || (defined __AAVR32__))\r
+  #define LITTLE_ENDIAN_MCU     FALSE\r
+#else\r
+  #error If you are here, you should check what is exactly the processor you are using...\r
+  #define LITTLE_ENDIAN_MCU     FALSE\r
+#endif\r
+\r
+// Check that MCU endianism is correctly defined.\r
+#ifndef LITTLE_ENDIAN_MCU\r
+  #error YOU MUST define the MCU endianism with LITTLE_ENDIAN_MCU: either FALSE or TRUE\r
+#endif\r
+\r
+//! Boolean evaluating MCU big endianism.\r
+#define BIG_ENDIAN_MCU        (!LITTLE_ENDIAN_MCU)\r
+\r
+\r
+#ifdef __AVR32_ABI_COMPILER__ // Automatically defined when compiling for AVR32, not when assembling.\r
+\r
+/*! \name MCU Endianism Handling\r
+ */\r
+//! @{\r
+\r
+#if (LITTLE_ENDIAN_MCU==TRUE)\r
+  #define LSB(u16)        (((U8  *)&(u16))[0])  //!< Least significant byte of \a u16.\r
+  #define MSB(u16)        (((U8  *)&(u16))[1])  //!< Most significant byte of \a u16.\r
+\r
+  #define LSH(u32)        (((U16 *)&(u32))[0])  //!< Least significant half-word of \a u32.\r
+  #define MSH(u32)        (((U16 *)&(u32))[1])  //!< Most significant half-word of \a u32.\r
+  #define LSB0W(u32)      (((U8  *)&(u32))[0])  //!< Least significant byte of 1st rank of \a u32.\r
+  #define LSB1W(u32)      (((U8  *)&(u32))[1])  //!< Least significant byte of 2nd rank of \a u32.\r
+  #define LSB2W(u32)      (((U8  *)&(u32))[2])  //!< Least significant byte of 3rd rank of \a u32.\r
+  #define LSB3W(u32)      (((U8  *)&(u32))[3])  //!< Least significant byte of 4th rank of \a u32.\r
+  #define MSB3W(u32)      LSB0W(u32)            //!< Most significant byte of 4th rank of \a u32.\r
+  #define MSB2W(u32)      LSB1W(u32)            //!< Most significant byte of 3rd rank of \a u32.\r
+  #define MSB1W(u32)      LSB2W(u32)            //!< Most significant byte of 2nd rank of \a u32.\r
+  #define MSB0W(u32)      LSB3W(u32)            //!< Most significant byte of 1st rank of \a u32.\r
+\r
+  #define LSW(u64)        (((U32 *)&(u64))[0])  //!< Least significant word of \a u64.\r
+  #define MSW(u64)        (((U32 *)&(u64))[1])  //!< Most significant word of \a u64.\r
+  #define LSH0(u64)       (((U16 *)&(u64))[0])  //!< Least significant half-word of 1st rank of \a u64.\r
+  #define LSH1(u64)       (((U16 *)&(u64))[1])  //!< Least significant half-word of 2nd rank of \a u64.\r
+  #define LSH2(u64)       (((U16 *)&(u64))[2])  //!< Least significant half-word of 3rd rank of \a u64.\r
+  #define LSH3(u64)       (((U16 *)&(u64))[3])  //!< Least significant half-word of 4th rank of \a u64.\r
+  #define MSH3(u64)       LSH0(u64)             //!< Most significant half-word of 4th rank of \a u64.\r
+  #define MSH2(u64)       LSH1(u64)             //!< Most significant half-word of 3rd rank of \a u64.\r
+  #define MSH1(u64)       LSH2(u64)             //!< Most significant half-word of 2nd rank of \a u64.\r
+  #define MSH0(u64)       LSH3(u64)             //!< Most significant half-word of 1st rank of \a u64.\r
+  #define LSB0D(u64)      (((U8  *)&(u64))[0])  //!< Least significant byte of 1st rank of \a u64.\r
+  #define LSB1D(u64)      (((U8  *)&(u64))[1])  //!< Least significant byte of 2nd rank of \a u64.\r
+  #define LSB2D(u64)      (((U8  *)&(u64))[2])  //!< Least significant byte of 3rd rank of \a u64.\r
+  #define LSB3D(u64)      (((U8  *)&(u64))[3])  //!< Least significant byte of 4th rank of \a u64.\r
+  #define LSB4D(u64)      (((U8  *)&(u64))[4])  //!< Least significant byte of 5th rank of \a u64.\r
+  #define LSB5D(u64)      (((U8  *)&(u64))[5])  //!< Least significant byte of 6th rank of \a u64.\r
+  #define LSB6D(u64)      (((U8  *)&(u64))[6])  //!< Least significant byte of 7th rank of \a u64.\r
+  #define LSB7D(u64)      (((U8  *)&(u64))[7])  //!< Least significant byte of 8th rank of \a u64.\r
+  #define MSB7D(u64)      LSB0D(u64)            //!< Most significant byte of 8th rank of \a u64.\r
+  #define MSB6D(u64)      LSB1D(u64)            //!< Most significant byte of 7th rank of \a u64.\r
+  #define MSB5D(u64)      LSB2D(u64)            //!< Most significant byte of 6th rank of \a u64.\r
+  #define MSB4D(u64)      LSB3D(u64)            //!< Most significant byte of 5th rank of \a u64.\r
+  #define MSB3D(u64)      LSB4D(u64)            //!< Most significant byte of 4th rank of \a u64.\r
+  #define MSB2D(u64)      LSB5D(u64)            //!< Most significant byte of 3rd rank of \a u64.\r
+  #define MSB1D(u64)      LSB6D(u64)            //!< Most significant byte of 2nd rank of \a u64.\r
+  #define MSB0D(u64)      LSB7D(u64)            //!< Most significant byte of 1st rank of \a u64.\r
+\r
+#elif (BIG_ENDIAN_MCU==TRUE) \r
+  #define MSB(u16)        (((U8  *)&(u16))[0])  //!< Most significant byte of \a u16.\r
+  #define LSB(u16)        (((U8  *)&(u16))[1])  //!< Least significant byte of \a u16.\r
+\r
+  #define MSH(u32)        (((U16 *)&(u32))[0])  //!< Most significant half-word of \a u32.\r
+  #define LSH(u32)        (((U16 *)&(u32))[1])  //!< Least significant half-word of \a u32.\r
+  #define MSB0W(u32)      (((U8  *)&(u32))[0])  //!< Most significant byte of 1st rank of \a u32.\r
+  #define MSB1W(u32)      (((U8  *)&(u32))[1])  //!< Most significant byte of 2nd rank of \a u32.\r
+  #define MSB2W(u32)      (((U8  *)&(u32))[2])  //!< Most significant byte of 3rd rank of \a u32.\r
+  #define MSB3W(u32)      (((U8  *)&(u32))[3])  //!< Most significant byte of 4th rank of \a u32.\r
+  #define LSB3W(u32)      MSB0W(u32)            //!< Least significant byte of 4th rank of \a u32.\r
+  #define LSB2W(u32)      MSB1W(u32)            //!< Least significant byte of 3rd rank of \a u32.\r
+  #define LSB1W(u32)      MSB2W(u32)            //!< Least significant byte of 2nd rank of \a u32.\r
+  #define LSB0W(u32)      MSB3W(u32)            //!< Least significant byte of 1st rank of \a u32.\r
+\r
+  #define MSW(u64)        (((U32 *)&(u64))[0])  //!< Most significant word of \a u64.\r
+  #define LSW(u64)        (((U32 *)&(u64))[1])  //!< Least significant word of \a u64.\r
+  #define MSH0(u64)       (((U16 *)&(u64))[0])  //!< Most significant half-word of 1st rank of \a u64.\r
+  #define MSH1(u64)       (((U16 *)&(u64))[1])  //!< Most significant half-word of 2nd rank of \a u64.\r
+  #define MSH2(u64)       (((U16 *)&(u64))[2])  //!< Most significant half-word of 3rd rank of \a u64.\r
+  #define MSH3(u64)       (((U16 *)&(u64))[3])  //!< Most significant half-word of 4th rank of \a u64.\r
+  #define LSH3(u64)       MSH0(u64)             //!< Least significant half-word of 4th rank of \a u64.\r
+  #define LSH2(u64)       MSH1(u64)             //!< Least significant half-word of 3rd rank of \a u64.\r
+  #define LSH1(u64)       MSH2(u64)             //!< Least significant half-word of 2nd rank of \a u64.\r
+  #define LSH0(u64)       MSH3(u64)             //!< Least significant half-word of 1st rank of \a u64.\r
+  #define MSB0D(u64)      (((U8  *)&(u64))[0])  //!< Most significant byte of 1st rank of \a u64.\r
+  #define MSB1D(u64)      (((U8  *)&(u64))[1])  //!< Most significant byte of 2nd rank of \a u64.\r
+  #define MSB2D(u64)      (((U8  *)&(u64))[2])  //!< Most significant byte of 3rd rank of \a u64.\r
+  #define MSB3D(u64)      (((U8  *)&(u64))[3])  //!< Most significant byte of 4th rank of \a u64.\r
+  #define MSB4D(u64)      (((U8  *)&(u64))[4])  //!< Most significant byte of 5th rank of \a u64.\r
+  #define MSB5D(u64)      (((U8  *)&(u64))[5])  //!< Most significant byte of 6th rank of \a u64.\r
+  #define MSB6D(u64)      (((U8  *)&(u64))[6])  //!< Most significant byte of 7th rank of \a u64.\r
+  #define MSB7D(u64)      (((U8  *)&(u64))[7])  //!< Most significant byte of 8th rank of \a u64.\r
+  #define LSB7D(u64)      MSB0D(u64)            //!< Least significant byte of 8th rank of \a u64.\r
+  #define LSB6D(u64)      MSB1D(u64)            //!< Least significant byte of 7th rank of \a u64.\r
+  #define LSB5D(u64)      MSB2D(u64)            //!< Least significant byte of 6th rank of \a u64.\r
+  #define LSB4D(u64)      MSB3D(u64)            //!< Least significant byte of 5th rank of \a u64.\r
+  #define LSB3D(u64)      MSB4D(u64)            //!< Least significant byte of 4th rank of \a u64.\r
+  #define LSB2D(u64)      MSB5D(u64)            //!< Least significant byte of 3rd rank of \a u64.\r
+  #define LSB1D(u64)      MSB6D(u64)            //!< Least significant byte of 2nd rank of \a u64.\r
+  #define LSB0D(u64)      MSB7D(u64)            //!< Least significant byte of 1st rank of \a u64.\r
+\r
+#else\r
+  #error  Unknown endianism.\r
+#endif\r
+\r
+//! @}\r
+\r
+\r
+/*! \name Endianism Conversion\r
+ *\r
+ * The same considerations as for clz and ctz apply here but AVR32-GCC's\r
+ * __builtin_bswap_16 and __builtin_bswap_32 do not behave like macros when\r
+ * applied to constant expressions, so two sets of macros are defined here:\r
+ *   - Swap16, Swap32 and Swap64 to apply to constant expressions (values known\r
+ *     at compile time);\r
+ *   - swap16, swap32 and swap64 to apply to non-constant expressions (values\r
+ *     unknown at compile time).\r
+ */\r
+//! @{\r
+\r
+/*! \brief Toggles the endianism of \a u16 (by swapping its bytes).\r
+ *\r
+ * \param u16 U16 of which to toggle the endianism.\r
+ *\r
+ * \return Value resulting from \a u16 with toggled endianism.\r
+ *\r
+ * \note More optimized if only used with values known at compile time.\r
+ */\r
+#define Swap16(u16) ((U16)(((U16)(u16) >> 8) |\\r
+                           ((U16)(u16) << 8)))\r
+\r
+/*! \brief Toggles the endianism of \a u32 (by swapping its bytes).\r
+ *\r
+ * \param u32 U32 of which to toggle the endianism.\r
+ *\r
+ * \return Value resulting from \a u32 with toggled endianism.\r
+ *\r
+ * \note More optimized if only used with values known at compile time.\r
+ */\r
+#define Swap32(u32) ((U32)(((U32)Swap16((U32)(u32) >> 16)) |\\r
+                           ((U32)Swap16((U32)(u32)) << 16)))\r
+\r
+/*! \brief Toggles the endianism of \a u64 (by swapping its bytes).\r
+ *\r
+ * \param u64 U64 of which to toggle the endianism.\r
+ *\r
+ * \return Value resulting from \a u64 with toggled endianism.\r
+ *\r
+ * \note More optimized if only used with values known at compile time.\r
+ */\r
+#define Swap64(u64) ((U64)(((U64)Swap32((U64)(u64) >> 32)) |\\r
+                           ((U64)Swap32((U64)(u64)) << 32)))\r
+\r
+/*! \brief Toggles the endianism of \a u16 (by swapping its bytes).\r
+ *\r
+ * \param u16 U16 of which to toggle the endianism.\r
+ *\r
+ * \return Value resulting from \a u16 with toggled endianism.\r
+ *\r
+ * \note More optimized if only used with values unknown at compile time.\r
+ */\r
+#if (defined __GNUC__)\r
+  #define swap16(u16) ((U16)__builtin_bswap_16((U16)(u16)))\r
+#elif (defined __ICCAVR32__)\r
+  #define swap16(u16) ((U16)__swap_bytes_in_halfwords((U16)(u16)))\r
+#endif\r
+\r
+/*! \brief Toggles the endianism of \a u32 (by swapping its bytes).\r
+ *\r
+ * \param u32 U32 of which to toggle the endianism.\r
+ *\r
+ * \return Value resulting from \a u32 with toggled endianism.\r
+ *\r
+ * \note More optimized if only used with values unknown at compile time.\r
+ */\r
+#if (defined __GNUC__)\r
+  #define swap32(u32) ((U32)__builtin_bswap_32((U32)(u32)))\r
+#elif (defined __ICCAVR32__)\r
+  #define swap32(u32) ((U32)__swap_bytes((U32)(u32)))\r
+#endif\r
+\r
+/*! \brief Toggles the endianism of \a u64 (by swapping its bytes).\r
+ *\r
+ * \param u64 U64 of which to toggle the endianism.\r
+ *\r
+ * \return Value resulting from \a u64 with toggled endianism.\r
+ *\r
+ * \note More optimized if only used with values unknown at compile time.\r
+ */\r
+#define swap64(u64) ((U64)(((U64)swap32((U64)(u64) >> 32)) |\\r
+                           ((U64)swap32((U64)(u64)) << 32)))\r
+\r
+//! @}\r
+\r
+\r
+/*! \name Target Abstraction\r
+ */\r
+//! @{\r
+\r
+#define _GLOBEXT_           extern      //!< extern storage-class specifier.\r
+#define _CONST_TYPE_        const       //!< const type qualifier.\r
+#define _MEM_TYPE_SLOW_                 //!< Slow memory type.\r
+#define _MEM_TYPE_MEDFAST_              //!< Fairly fast memory type.\r
+#define _MEM_TYPE_FAST_                 //!< Fast memory type.\r
+\r
+typedef U8                  Byte;       //!< 8-bit unsigned integer.\r
+\r
+#define memcmp_ram2ram      memcmp      //!< Target-specific memcmp of RAM to RAM.\r
+#define memcmp_code2ram     memcmp      //!< Target-specific memcmp of RAM to NVRAM.\r
+#define memcpy_ram2ram      memcpy      //!< Target-specific memcpy from RAM to RAM.\r
+#define memcpy_code2ram     memcpy      //!< Target-specific memcpy from NVRAM to RAM.\r
+\r
+#define LSB0(u32)           LSB0W(u32)  //!< Least significant byte of 1st rank of \a u32.\r
+#define LSB1(u32)           LSB1W(u32)  //!< Least significant byte of 2nd rank of \a u32.\r
+#define LSB2(u32)           LSB2W(u32)  //!< Least significant byte of 3rd rank of \a u32.\r
+#define LSB3(u32)           LSB3W(u32)  //!< Least significant byte of 4th rank of \a u32.\r
+#define MSB3(u32)           MSB3W(u32)  //!< Most significant byte of 4th rank of \a u32.\r
+#define MSB2(u32)           MSB2W(u32)  //!< Most significant byte of 3rd rank of \a u32.\r
+#define MSB1(u32)           MSB1W(u32)  //!< Most significant byte of 2nd rank of \a u32.\r
+#define MSB0(u32)           MSB0W(u32)  //!< Most significant byte of 1st rank of \a u32.\r
+\r
+//! @}\r
+\r
+#endif  // __AVR32_ABI_COMPILER__\r
+\r
+\r
+#endif  // _COMPILER_H_\r

diff --git a/Demo/AVR32_UC3A_GCC/Atmel_SW_Framework/UTILS/parts.h b/Demo/AVR32_UC3A_GCC/Atmel_SW_Framework/UTILS/parts.h
new file mode 100644 (file)
index 0000000..3810fbc
--- /dev/null
+++ b/Demo/AVR32_UC3A_GCC/Atmel_SW_Framework/UTILS/parts.h
@@ -0,0 +1,203 @@
+/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */\r
+
+/*This file is prepared for Doxygen automatic documentation generation.*/\r
+/*! \file *********************************************************************\r
+ *\r
+ * \brief Arch file for AVR32.\r
+ *\r
+ * This file defines common AVR32 UC3 series.\r
+ *\r
+ * - Compiler:           IAR EWAVR32 and GNU GCC for AVR32\r
+ * - Supported devices:  All AVR32 devices can be used.\r
+ * - AppNote:\r
+ *\r
+ * \author               Atmel Corporation: http://www.atmel.com \n\r
+ *                       Support and FAQ: http://support.atmel.no/\r
+ *\r
+ ******************************************************************************/\r
+\r
+/* Copyright (c) 2009 Atmel Corporation. All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice, this\r
+ * list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an Atmel\r
+ * AVR product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\r
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\r
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\r
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE\r
+ *\r
+ */\r
+\r
+#ifndef _ARCH_H_\r
+#define _ARCH_H_\r
+\r
+// UC3 A Series\r
+#define UC3A0    ( defined (__GNUC__) && \\r
+                   ( defined (__AVR32_UC3A0128__)   || \\r
+                     defined (__AVR32_UC3A0256__)   || \\r
+                     defined (__AVR32_UC3A0512__)   || \\r
+                     defined (__AVR32_UC3A0512ES__)))  \\r
+            ||((defined(__ICCAVR32__) || defined(__AAVR32__)) && \\r
+                   ( defined (__AT32UC3A0128__)     || \\r
+                     defined (__AT32UC3A0256__)     || \\r
+                     defined (__AT32UC3A0512__)     || \\r
+                     defined (__AT32UC3A0512ES__)))\r
+                     \r
+#define UC3A1    ( defined (__GNUC__) && \\r
+                   ( defined (__AVR32_UC3A1128__)   || \\r
+                     defined (__AVR32_UC3A1256__)   || \\r
+                     defined (__AVR32_UC3A1512__)   || \\r
+                     defined (__AVR32_UC3A1512ES__)))  \\r
+            ||((defined(__ICCAVR32__) || defined(__AAVR32__)) && \\r
+                   ( defined (__AT32UC3A1128__)     || \\r
+                     defined (__AT32UC3A1256__)     || \\r
+                     defined (__AT32UC3A1512__)     || \\r
+                     defined (__AT32UC3A1512ES__)))\r
+                     \r
+#define UC3A3  ( defined (__GNUC__) && \\r
+                   ( defined (__AVR32_UC3A364__)    || \\r
+                     defined (__AVR32_UC3A364S__)   || \\r
+                     defined (__AVR32_UC3A3128__)   || \\r
+                     defined (__AVR32_UC3A3128S__)  || \\r
+                     defined (__AVR32_UC3A3256__)   || \\r
+                     defined (__AVR32_UC3A3256S__)))  \\r
+            ||((defined(__ICCAVR32__) || defined(__AAVR32__)) && \\r
+                   ( defined (__AT32UC3A364__)      || \\r
+                     defined (__AT32UC3A364S__)     || \\r
+                     defined (__AT32UC3A3128__)     || \\r
+                     defined (__AT32UC3A3128S__)    || \\r
+                     defined (__AT32UC3A3256__)     || \\r
+                     defined (__AT32UC3A3256S__)))\r
+                     \r
+#define UC3A (UC3A0 || UC3A1 || UC3A3)\r
+\r
+// UC3 B Series\r
+#define UC3B0  ( defined (__GNUC__) && \\r
+                   ( defined (__AVR32_UC3B064__)     || \\r
+                     defined (__AVR32_UC3B0128__)    || \\r
+                     defined (__AVR32_UC3B0256__)    || \\r
+                     defined (__AVR32_UC3B0256ES__)  || \\r
+                     defined (__AVR32_UC3B0512__)    || \\r
+                     defined (__AVR32_UC3B0512REVC_))) \\r
+            ||((defined(__ICCAVR32__) || defined(__AAVR32__)) && \\r
+                   ( defined (__AT32UC3B064__)       || \\r
+                     defined (__AT32UC3B0128__)      || \\r
+                     defined (__AT32UC3B0256__)      || \\r
+                     defined (__AT32UC3B0256ES__)    || \\r
+                     defined (__AT32UC3B0512__)      || \\r
+                     defined (__AT32UC3B0512REVC__)))\r
+\r
+#define UC3B1  ( defined (__GNUC__) && \\r
+                   ( defined (__AVR32_UC3B164__)     || \\r
+                     defined (__AVR32_UC3B1128__)    || \\r
+                     defined (__AVR32_UC3B1256__)    || \\r
+                     defined (__AVR32_UC3B1256ES__)  || \\r
+                     defined (__AVR32_UC3B1512__)    || \\r
+                     defined (__AVR32_UC3B1512ES__))) \\r
+            ||((defined(__ICCAVR32__) || defined(__AAVR32__)) && \\r
+                   ( defined (__AT32UC3B164__)       || \\r
+                     defined (__AT32UC3B1128__)      || \\r
+                     defined (__AT32UC3B1256__)      || \\r
+                     defined (__AT32UC3B1256ES__)    || \\r
+                     defined (__AT32UC3B1512__)      || \\r
+                     defined (__AT32UC3B1512REVC__)))\r
+\r
+#define UC3B (UC3B0 || UC3B1 )\r
+\r
+// UC3 C Series\r
+#define UC3C0    ( defined (__GNUC__) && \\r
+                   ( defined (__AVR32_UC3C064C__)       || \\r
+                     defined (__AVR32_UC3C0128C__)      || \\r
+                     defined (__AVR32_UC3C0256C__)      || \\r
+                     defined (__AVR32_UC3C0512CREVC__)))  \\r
+            ||((defined(__ICCAVR32__) || defined(__AAVR32__)) && \\r
+                   ( defined (__AT32UC3C064C__)         || \\r
+                     defined (__AT32UC3C0128C__)        || \\r
+                     defined (__AT32UC3C0256C__)        || \\r
+                     defined (__AT32UC3C0512C__)))\r
+                     \r
+#define UC3C1    ( defined (__GNUC__) && \\r
+                   ( defined (__AVR32_UC3C164C__)       || \\r
+                     defined (__AVR32_UC3C1128C__)      || \\r
+                     defined (__AVR32_UC3C1256C__)      || \\r
+                     defined (__AVR32_UC3C1512CREVC__)))  \\r
+            ||((defined(__ICCAVR32__) || defined(__AAVR32__)) && \\r
+                   ( defined (__AT32UC3C164C__)         || \\r
+                     defined (__AT32UC3C1128C__)        || \\r
+                     defined (__AT32UC3C1256C__)        || \\r
+                     defined (__AT32UC3C1512C__)))\r
+                     \r
+#define UC3C2    ( defined (__GNUC__) && \\r
+                   ( defined (__AVR32_UC3C264C__)       || \\r
+                     defined (__AVR32_UC3C2128C__)      || \\r
+                     defined (__AVR32_UC3C2256C__)      || \\r
+                     defined (__AVR32_UC3C2512CREVC__)))  \\r
+            ||((defined(__ICCAVR32__) || defined(__AAVR32__)) && \\r
+                   ( defined (__AT32UC3C264C__)         || \\r
+                     defined (__AT32UC3C2128C__)        || \\r
+                     defined (__AT32UC3C2256C__)        || \\r
+                     defined (__AT32UC3C2512C__)))\r
+\r
+#define UC3C (UC3C0 || UC3C1 || UC3C2)\r
+\r
+// UC3 L Device series\r
+#define UC3L0 ( defined (__GNUC__) && \\r
+                  ( defined (__AVR32_UC3L016__)     || \\r
+                    defined (__AVR32_UC3L032__)     || \\r
+                    defined (__AVR32_UC3L064__)     || \\r
+                    defined (__AVR32_UC3L064REVB__))) \\r
+           ||((defined(__ICCAVR32__) || defined(__AAVR32__)) && \\r
+                  ( defined (__AT32UC3L016__)     || \\r
+                    defined (__AT32UC3L032__)     || \\r
+                    defined (__AT32UC3L064__)     || \\r
+                    defined (__AT32UC3L064REVB__)))\r
+                    \r
+#define UC3L1 ( defined (__GNUC__) && \\r
+                  ( defined (__AVR32_UC3L116__)     || \\r
+                    defined (__AVR32_UC3L132__)     || \\r
+                    defined (__AVR32_UC3L164__))) \\r
+           ||((defined(__ICCAVR32__) || defined(__AAVR32__)) && \\r
+                  ( defined (__AT32UC3L116__)     || \\r
+                    defined (__AT32UC3L132__)     || \\r
+                    defined (__AT32UC3L164__)))\r
+                    \r
+#define UC3L2 ( defined (__GNUC__) && \\r
+                  ( defined (__AVR32_UC3L216__)     || \\r
+                    defined (__AVR32_UC3L232__)     || \\r
+                    defined (__AVR32_UC3L264__))) \\r
+           ||((defined(__ICCAVR32__) || defined(__AAVR32__)) && \\r
+                  ( defined (__AT32UC3L216__)     || \\r
+                    defined (__AT32UC3L232__)     || \\r
+                    defined (__AT32UC3L264__)))\r
+                    \r
+#define UC3L3 ( defined (__GNUC__) && \\r
+                  ( defined (__AVR32_UC3L316__)     || \\r
+                    defined (__AVR32_UC3L332__)     || \\r
+                    defined (__AVR32_UC3L364__))) \\r
+             ||((defined(__ICCAVR32__) || defined(__AAVR32__)) && \\r
+                  ( defined (__AT32UC3L316__)     || \\r
+                    defined (__AT32UC3L332__)     || \\r
+                    defined (__AT32UC3L364__)))\r
+\r
+#define UC3L (UC3L0 || UC3L1 || UC3L2 || UC3L3)\r
+\r
+#endif  // _ARCH_H_\r

diff --git a/Demo/AVR32_UC3A_GCC/FreeRTOSConfig.h b/Demo/AVR32_UC3A_GCC/FreeRTOSConfig.h
new file mode 100644 (file)
index 0000000..8909c1e
--- /dev/null
+++ b/Demo/AVR32_UC3A_GCC/FreeRTOSConfig.h
@@ -0,0 +1,128 @@
+/*\r
+    FreeRTOS V6.0.5 - Copyright (C) 2010 Real Time Engineers Ltd.\r
+\r
+    ***************************************************************************\r
+    *                                                                         *\r
+    * If you are:                                                             *\r
+    *                                                                         *\r
+    *    + New to FreeRTOS,                                                   *\r
+    *    + Wanting to learn FreeRTOS or multitasking in general quickly       *\r
+    *    + Looking for basic training,                                        *\r
+    *    + Wanting to improve your FreeRTOS skills and productivity           *\r
+    *                                                                         *\r
+    * then take a look at the FreeRTOS eBook                                  *\r
+    *                                                                         *\r
+    *        "Using the FreeRTOS Real Time Kernel - a Practical Guide"        *\r
+    *                  http://www.FreeRTOS.org/Documentation                  *\r
+    *                                                                         *\r
+    * A pdf reference manual is also available.  Both are usually delivered   *\r
+    * to your inbox within 20 minutes to two hours when purchased between 8am *\r
+    * and 8pm GMT (although please allow up to 24 hours in case of            *\r
+    * exceptional circumstances).  Thank you for your support!                *\r
+    *                                                                         *\r
+    ***************************************************************************\r
+\r
+    This file is part of the FreeRTOS distribution.\r
+\r
+    FreeRTOS is free software; you can redistribute it and/or modify it under\r
+    the terms of the GNU General Public License (version 2) as published by the\r
+    Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+    ***NOTE*** The exception to the GPL is included to allow you to distribute\r
+    a combined work that includes FreeRTOS without being obliged to provide the\r
+    source code for proprietary components outside of the FreeRTOS kernel.\r
+    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT\r
+    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\r
+    FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\r
+    more details. You should have received a copy of the GNU General Public \r
+    License and the FreeRTOS license exception along with FreeRTOS; if not it \r
+    can be viewed here: http://www.freertos.org/a00114.html and also obtained \r
+    by writing to Richard Barry, contact details for whom are available on the\r
+    FreeRTOS WEB site.\r
+\r
+    1 tab == 4 spaces!\r
+\r
+    http://www.FreeRTOS.org - Documentation, latest information, license and\r
+    contact details.\r
+\r
+    http://www.SafeRTOS.com - A version that is certified for use in safety\r
+    critical systems.\r
+\r
+    http://www.OpenRTOS.com - Commercial support, development, porting,\r
+    licensing and training services.\r
+*/\r
+\r
+\r
+#ifndef FREERTOS_CONFIG_H\r
+#define FREERTOS_CONFIG_H\r
+\r
+#define BOARD 1\r
+\r
+#include "board.h"\r
+\r
+\r
+/*-----------------------------------------------------------\r
+ * Application specific definitions.\r
+ *\r
+ * These definitions should be adjusted for your particular hardware and\r
+ * application requirements.\r
+ *\r
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE\r
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.\r
+ *\r
+ * See http://www.freertos.org/a00110.html.\r
+ *----------------------------------------------------------*/\r
+\r
+#define configUSE_PREEMPTION      0\r
+#define configUSE_IDLE_HOOK       0\r
+#define configUSE_TICK_HOOK       0\r
+#define configCPU_CLOCK_HZ        ( FOSC0 ) /* Hz clk gen */\r
+#define configPBA_CLOCK_HZ        ( FOSC0 )\r
+#define configTICK_RATE_HZ        ( ( portTickType ) 1000 )\r
+#define configMAX_PRIORITIES      ( ( unsigned portBASE_TYPE ) 8 )\r
+#define configMINIMAL_STACK_SIZE  ( ( unsigned short ) 128 )\r
+/* configTOTAL_HEAP_SIZE is not used when heap_3.c is used. */\r
+#define configTOTAL_HEAP_SIZE     ( ( size_t ) ( 1024*25 ) )\r
+#define configMAX_TASK_NAME_LEN   ( 16 )\r
+#define configUSE_TRACE_FACILITY  0\r
+#define configUSE_16_BIT_TICKS    0\r
+#define configIDLE_SHOULD_YIELD   1\r
+\r
+/* Co-routine definitions. */\r
+#define configUSE_CO_ROUTINES     0\r
+#define configMAX_CO_ROUTINE_PRIORITIES ( 0 )\r
+\r
+/* Set the following definitions to 1 to include the API function, or zero\r
+to exclude the API function. */\r
+\r
+#define INCLUDE_vTaskPrioritySet            1\r
+#define INCLUDE_uxTaskPriorityGet           1\r
+#define INCLUDE_vTaskDelete                 1\r
+#define INCLUDE_vTaskCleanUpResources       0\r
+#define INCLUDE_vTaskSuspend                1\r
+#define INCLUDE_vTaskDelayUntil             1\r
+#define INCLUDE_vTaskDelay                  1\r
+#define INCLUDE_xTaskGetCurrentTaskHandle   0\r
+#define INCLUDE_xTaskGetSchedulerState         1\r
+\r
+/* configHEAP_INIT is a boolean indicating whether to initialize the heap with\r
+   0xA5 in order to be able to determine the maximal heap consumption. */\r
+#define configHEAP_INIT               0\r
+\r
+/* Debug trace configuration.\r
+   configDBG is a boolean indicating whether to activate the debug trace. */\r
+/* EVK1100 Board Definitions. */\r
+#define configDBG                     1\r
+#define configDBG_USART               (&AVR32_USART1)\r
+#define configDBG_USART_RX_PIN        AVR32_USART1_RXD_0_0_PIN\r
+#define configDBG_USART_RX_FUNCTION   AVR32_USART1_RXD_0_0_FUNCTION\r
+#define configDBG_USART_TX_PIN        AVR32_USART1_TXD_0_0_PIN\r
+#define configDBG_USART_TX_FUNCTION   AVR32_USART1_TXD_0_0_FUNCTION\r
+#define configDBG_USART_BAUDRATE      57600\r
+#define serialPORT_USART              (&AVR32_USART1)\r
+#define serialPORT_USART_RX_PIN       AVR32_USART1_RXD_0_0_PIN\r
+#define serialPORT_USART_RX_FUNCTION  AVR32_USART1_RXD_0_0_FUNCTION\r
+#define serialPORT_USART_TX_PIN       AVR32_USART1_TXD_0_0_PIN\r
+#define serialPORT_USART_TX_FUNCTION  AVR32_USART1_TXD_0_0_FUNCTION\r
+#define serialPORT_USART_IRQ          AVR32_USART1_IRQ\r
+#define serialPORT_USART_BAUDRATE     57600\r
+#endif /* FREERTOS_CONFIG_H */\r

diff --git a/Demo/AVR32_UC3A_GCC/ParTest/ParTest.c b/Demo/AVR32_UC3A_GCC/ParTest/ParTest.c
new file mode 100644 (file)
index 0000000..fd91e87
--- /dev/null
+++ b/Demo/AVR32_UC3A_GCC/ParTest/ParTest.c
@@ -0,0 +1,117 @@
+/*This file has been prepared for Doxygen automatic documentation generation.*/\r
+/*! \file *********************************************************************\r
+ *\r
+ * \brief FreeRTOS LEDs Management for AVR32 UC3.\r
+ *\r
+ * - Compiler:           IAR EWAVR32 and GNU GCC for AVR32\r
+ * - Supported devices:  All AVR32 devices can be used.\r
+ * - AppNote:\r
+ *\r
+ * \author               Atmel Corporation: http://www.atmel.com \n\r
+ *                       Support and FAQ: http://support.atmel.no/\r
+ *\r
+ *****************************************************************************/\r
+\r
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of ATMEL may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND\r
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,\r
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\r
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\r
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF\r
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ */\r
+\r
+\r
+\r
+#include <avr32/io.h>\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "partest.h"\r
+\r
+\r
+/*-----------------------------------------------------------\r
+ * Simple parallel port IO routines.\r
+ *-----------------------------------------------------------*/\r
+\r
+#define partstALL_OUTPUTS_OFF     ( ( unsigned portCHAR ) 0x00 )\r
+#if( BOARD==EVK1100 )\r
+#  define partstMAX_OUTPUT_LED    ( ( unsigned portCHAR ) 8 )\r
+\r
+#elif( BOARD==EVK1101 )\r
+#  define partstMAX_OUTPUT_LED    ( ( unsigned portCHAR ) 4 )\r
+#endif\r
+\r
+static volatile unsigned portCHAR ucCurrentOutputValue = partstALL_OUTPUTS_OFF; /*lint !e956 File scope parameters okay here. */\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestInitialise( void )\r
+{\r
+       LED_Display( partstALL_OUTPUTS_OFF ); /* Start with all LEDs off. */\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue )\r
+{\r
+unsigned portCHAR ucBit;\r
+\r
+       if( uxLED >= partstMAX_OUTPUT_LED )\r
+       {\r
+               return;\r
+       }\r
+\r
+       ucBit = ( ( unsigned portCHAR ) 1 ) << uxLED;\r
+\r
+       vTaskSuspendAll();\r
+       {\r
+               if( xValue == pdTRUE )\r
+               {\r
+                       ucCurrentOutputValue |= ucBit;\r
+               }\r
+               else\r
+               {\r
+                       ucCurrentOutputValue &= ~ucBit;\r
+               }\r
+\r
+               LED_Display(ucCurrentOutputValue);\r
+       }\r
+       xTaskResumeAll();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestToggleLED( unsigned portBASE_TYPE uxLED )\r
+{\r
+unsigned portCHAR ucBit;\r
+\r
+         if( uxLED >= partstMAX_OUTPUT_LED )\r
+         {\r
+       return;\r
+       }\r
+\r
+       ucBit = ( ( unsigned portCHAR ) 1 ) << uxLED;\r
+\r
+       vTaskSuspendAll();\r
+       {\r
+               ucCurrentOutputValue ^= ucBit;\r
+               LED_Display(ucCurrentOutputValue);\r
+       }\r
+       xTaskResumeAll();\r
+}\r

diff --git a/Demo/AVR32_UC3A_GCC/conf_isp.h b/Demo/AVR32_UC3A_GCC/conf_isp.h
new file mode 100644 (file)
index 0000000..05fd4dc
--- /dev/null
+++ b/Demo/AVR32_UC3A_GCC/conf_isp.h
@@ -0,0 +1,119 @@
+/*This file is prepared for Doxygen automatic documentation generation.*/\r
+/*! \file ******************************************************************\r
+ *\r
+ * \brief ISP configuration file.\r
+ *\r
+ * This file contains the possible external configuration of the ISP.\r
+ *\r
+ * - Compiler:           IAR EWAVR32 and GNU GCC for AVR32\r
+ * - Supported devices:  All AVR32 devices with a USB module can be used.\r
+ * - AppNote:\r
+ *\r
+ * \author               Atmel Corporation: http://www.atmel.com \n\r
+ *                       Support and FAQ: http://support.atmel.no/\r
+ *\r
+ ***************************************************************************/\r
+\r
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of ATMEL may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND\r
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,\r
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\r
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\r
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF\r
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ */\r
+\r
+\r
+#ifndef _CONF_ISP_H_\r
+#define _CONF_ISP_H_\r
+\r
+#include <avr32/io.h>\r
+#include "compiler.h"\r
+\r
+\r
+//_____ D E F I N I T I O N S ______________________________________________\r
+\r
+#define PRODUCT_MANUFACTURER_ID       0x58\r
+#define PRODUCT_FAMILY_ID             0x20\r
+\r
+#define ISP_VERSION                   0x00\r
+#define ISP_ID0                       0x00\r
+#define ISP_ID1                       0x00\r
+\r
+#define ISP_GPFB_FORCE                31\r
+#define ISP_GPFB_FORCE_MASK           0x80000000\r
+#define ISP_GPFB_FORCE_OFFSET         31\r
+#define ISP_GPFB_FORCE_SIZE           1\r
+\r
+#define ISP_GPFB_IO_COND_EN           30\r
+#define ISP_GPFB_IO_COND_EN_MASK      0x40000000\r
+#define ISP_GPFB_IO_COND_EN_OFFSET    30\r
+#define ISP_GPFB_IO_COND_EN_SIZE      1\r
+\r
+#define ISP_GPFB_BOD_EN               29\r
+#define ISP_GPFB_BOD_EN_MASK          0x20000000\r
+#define ISP_GPFB_BOD_EN_OFFSET        29\r
+#define ISP_GPFB_BOD_EN_SIZE          1\r
+\r
+#define ISP_CFG                       (*(volatile U32 *)ISP_CFG_ADDRESS)\r
+#define ISP_CFG_ADDRESS               (AVR32_FLASHC_USER_PAGE_ADDRESS + ISP_CFG_OFFSET)\r
+#define ISP_CFG_OFFSET                0x000001FC\r
+#define ISP_CFG_SIZE                  4\r
+\r
+#define ISP_CFG_BOOT_KEY              17\r
+#define ISP_CFG_BOOT_KEY_MASK         0xFFFE0000\r
+#define ISP_CFG_BOOT_KEY_OFFSET       17\r
+#define ISP_CFG_BOOT_KEY_SIZE         15\r
+#define ISP_CFG_BOOT_KEY_VALUE        0x494F\r
+\r
+#define ISP_CFG_IO_COND_LEVEL         16\r
+#define ISP_CFG_IO_COND_LEVEL_MASK    0x00010000\r
+#define ISP_CFG_IO_COND_LEVEL_OFFSET  16\r
+#define ISP_CFG_IO_COND_LEVEL_SIZE    1\r
+\r
+#define ISP_CFG_IO_COND_PIN           8\r
+#define ISP_CFG_IO_COND_PIN_MASK      0x0000FF00\r
+#define ISP_CFG_IO_COND_PIN_OFFSET    8\r
+#define ISP_CFG_IO_COND_PIN_SIZE      8\r
+\r
+#define ISP_CFG_CRC8                  0\r
+#define ISP_CFG_CRC8_MASK             0x000000FF\r
+#define ISP_CFG_CRC8_OFFSET           0\r
+#define ISP_CFG_CRC8_SIZE             8\r
+#define ISP_CFG_CRC8_POLYNOMIAL       0x107\r
+\r
+#define ISP_KEY                       (*(volatile U32 *)ISP_KEY_ADDRESS)\r
+#define ISP_KEY_ADDRESS               (AVR32_SRAM_ADDRESS + ISP_KEY_OFFSET)\r
+#define ISP_KEY_OFFSET                0x00000000\r
+#define ISP_KEY_SIZE                  4\r
+#define ISP_KEY_VALUE                 ('I' << 24 | 'S' << 16 | 'P' << 8 | 'K')\r
+\r
+#ifndef ISP_OSC\r
+  #define ISP_OSC                     0\r
+#endif\r
+\r
+#define DFU_FRAME_LENGTH              2048\r
+\r
+#define PROGRAM_START_ADDRESS         (AVR32_FLASH_ADDRESS + PROGRAM_START_OFFSET)\r
+#define PROGRAM_START_OFFSET          0x00002000\r
+\r
+\r
+#endif  // _CONF_ISP_H_\r

diff --git a/Demo/AVR32_UC3A_GCC/exception.x b/Demo/AVR32_UC3A_GCC/exception.x
new file mode 100644 (file)
index 0000000..24641a1
--- /dev/null
+++ b/Demo/AVR32_UC3A_GCC/exception.x
@@ -0,0 +1,239 @@
+/* This file is part of the ATMEL AVR32-SoftwareFramework-AT32UC3-1.5.0 Release */\r
+
+/*This file is prepared for Doxygen automatic documentation generation.*/
+/*! \file *********************************************************************
+ *
+ * \brief Exception and interrupt vectors.
+ *
+ * This file maps all events supported by an AVR32.
+ *
+ * - Compiler:           GNU GCC for AVR32
+ * - Supported devices:  All AVR32 devices with an INTC module can be used.
+ * - AppNote:
+ *
+ * \author               Atmel Corporation: http://www.atmel.com \n
+ *                       Support and FAQ: http://support.atmel.no/
+ *
+ ******************************************************************************/
+
+/* Copyright (c) 2009 Atmel Corporation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an Atmel
+ * AVR product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
+ *
+ */
+
+#if !__AVR32_UC__ && !__AVR32_AP__
+  #error Implementation of the AVR32 architecture not supported by the INTC driver.
+#endif
+
+
+#include <avr32/io.h>
+
+
+//! @{
+//! \verbatim
+
+
+  .section  .exception, "ax", @progbits
+
+
+// Start of Exception Vector Table.
+
+  // EVBA must be aligned with a power of two strictly greater than the EVBA-
+  // relative offset of the last vector.
+  .balign 0x200
+
+  // Export symbol.
+  .global _evba
+  .type _evba, @function
+_evba:
+
+        .org  0x000
+        // Unrecoverable Exception.
+_handle_Unrecoverable_Exception:
+        rjmp $
+
+        .org  0x004
+        // TLB Multiple Hit.
+_handle_TLB_Multiple_Hit:
+        rjmp $
+
+        .org  0x008
+        // Bus Error Data Fetch.
+_handle_Bus_Error_Data_Fetch:
+        rjmp $
+
+        .org  0x00C
+         // Bus Error Instruction Fetch.
+_handle_Bus_Error_Instruction_Fetch:
+        rjmp $
+
+        .org  0x010
+        // NMI.
+_handle_NMI:
+        rjmp $
+
+        .org  0x014
+        // Instruction Address.
+_handle_Instruction_Address:
+        rjmp $
+
+        .org  0x018
+        // ITLB Protection.
+_handle_ITLB_Protection:
+        rjmp $
+
+        .org  0x01C
+        // Breakpoint.
+_handle_Breakpoint:
+        rjmp $
+
+        .org  0x020
+        // Illegal Opcode.
+_handle_Illegal_Opcode:
+        rjmp $
+
+        .org  0x024
+        // Unimplemented Instruction.
+_handle_Unimplemented_Instruction:
+        rjmp $
+
+        .org  0x028
+        // Privilege Violation.
+_handle_Privilege_Violation:
+        rjmp $
+
+        .org  0x02C
+        // Floating-Point: UNUSED IN AVR32UC and AVR32AP.
+_handle_Floating_Point:
+        rjmp $
+
+        .org  0x030
+        // Coprocessor Absent: UNUSED IN AVR32UC.
+_handle_Coprocessor_Absent:
+        rjmp $
+
+        .org  0x034
+        // Data Address (Read).
+_handle_Data_Address_Read:
+        rjmp $
+
+        .org  0x038
+        // Data Address (Write).
+_handle_Data_Address_Write:
+        rjmp $
+
+        .org  0x03C
+        // DTLB Protection (Read).
+_handle_DTLB_Protection_Read:
+        rjmp $
+
+        .org  0x040
+        // DTLB Protection (Write).
+_handle_DTLB_Protection_Write:
+        rjmp $
+
+        .org  0x044
+        // DTLB Modified: UNUSED IN AVR32UC.
+_handle_DTLB_Modified:
+        rjmp $
+
+        .org  0x050
+        // ITLB Miss.
+_handle_ITLB_Miss:
+        rjmp $
+
+        .org  0x060
+        // DTLB Miss (Read).
+_handle_DTLB_Miss_Read:
+        rjmp $
+
+        .org  0x070
+        // DTLB Miss (Write).
+_handle_DTLB_Miss_Write:
+        rjmp $
+
+        .org  0x100
+        // Supervisor Call.
+_handle_Supervisor_Call:
+        lda.w   pc, SCALLYield\r
+
+
+// Interrupt support.
+// The interrupt controller must provide the offset address relative to EVBA.
+// Important note:
+//   All interrupts call a C function named _get_interrupt_handler.
+//   This function will read group and interrupt line number to then return in
+//   R12 a pointer to a user-provided interrupt handler.
+
+  .balign 4
+
+  .irp    priority, 0, 1, 2, 3
+_int\priority:
+#if __AVR32_UC__
+  // R8-R12, LR, PC and SR are automatically pushed onto the system stack by the
+  // CPU upon interrupt entry. No other register is saved by hardware.
+#elif __AVR32_AP__
+  // PC and SR are automatically saved in respectively RAR_INTx and RSR_INTx by
+  // the CPU upon interrupt entry. No other register is saved by hardware.
+  pushm   r8-r12, lr
+#endif
+  mov     r12, \priority  // Pass the int_level parameter to the _get_interrupt_handler function.
+  call    _get_interrupt_handler
+  cp.w    r12, 0          // Get the pointer to the interrupt handler returned by the function.
+#if __AVR32_UC__
+  movne   pc, r12         // If this was not a spurious interrupt (R12 != NULL), jump to the handler.
+#elif __AVR32_AP__
+  breq    spint\priority  // If this was a spurious interrupt (R12 == NULL), branch.
+  st.w    --sp, r12       // Push the pointer to the interrupt handler onto the system stack since no register may be altered.
+  popm    r8-r12, lr, pc  // Restore registers and jump to the handler.
+spint\priority:
+  popm    r8-r12, lr
+#endif
+  rete                    // If this was a spurious interrupt (R12 == NULL), return from event handler.
+  .endr
+
+
+// Constant data area.
+
+  .balign 4
+
+  // Values to store in the interrupt priority registers for the various interrupt priority levels.
+  // The interrupt priority registers contain the interrupt priority level and
+  // the EVBA-relative interrupt vector offset.
+  .global ipr_val
+  .type ipr_val, @object
+ipr_val:
+  .word (AVR32_INTC_INT0 << AVR32_INTC_IPR_INTLEVEL_OFFSET) | (_int0 - _evba),\
+        (AVR32_INTC_INT1 << AVR32_INTC_IPR_INTLEVEL_OFFSET) | (_int1 - _evba),\
+        (AVR32_INTC_INT2 << AVR32_INTC_IPR_INTLEVEL_OFFSET) | (_int2 - _evba),\
+        (AVR32_INTC_INT3 << AVR32_INTC_IPR_INTLEVEL_OFFSET) | (_int3 - _evba)
+
+
+//! \endverbatim
+//! @}

diff --git a/Demo/AVR32_UC3A_GCC/main.c b/Demo/AVR32_UC3A_GCC/main.c
new file mode 100644 (file)
index 0000000..c6ca79e
--- /dev/null
+++ b/Demo/AVR32_UC3A_GCC/main.c
@@ -0,0 +1,278 @@
+/*\r
+    FreeRTOS V6.0.5 - Copyright (C) 2010 Real Time Engineers Ltd.\r
+\r
+    ***************************************************************************\r
+    *                                                                         *\r
+    * If you are:                                                             *\r
+    *                                                                         *\r
+    *    + New to FreeRTOS,                                                   *\r
+    *    + Wanting to learn FreeRTOS or multitasking in general quickly       *\r
+    *    + Looking for basic training,                                        *\r
+    *    + Wanting to improve your FreeRTOS skills and productivity           *\r
+    *                                                                         *\r
+    * then take a look at the FreeRTOS eBook                                  *\r
+    *                                                                         *\r
+    *        "Using the FreeRTOS Real Time Kernel - a Practical Guide"        *\r
+    *                  http://www.FreeRTOS.org/Documentation                  *\r
+    *                                                                         *\r
+    * A pdf reference manual is also available.  Both are usually delivered   *\r
+    * to your inbox within 20 minutes to two hours when purchased between 8am *\r
+    * and 8pm GMT (although please allow up to 24 hours in case of            *\r
+    * exceptional circumstances).  Thank you for your support!                *\r
+    *                                                                         *\r
+    ***************************************************************************\r
+\r
+    This file is part of the FreeRTOS distribution.\r
+\r
+    FreeRTOS is free software; you can redistribute it and/or modify it under\r
+    the terms of the GNU General Public License (version 2) as published by the\r
+    Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+    ***NOTE*** The exception to the GPL is included to allow you to distribute\r
+    a combined work that includes FreeRTOS without being obliged to provide the\r
+    source code for proprietary components outside of the FreeRTOS kernel.\r
+    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT\r
+    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\r
+    FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\r
+    more details. You should have received a copy of the GNU General Public \r
+    License and the FreeRTOS license exception along with FreeRTOS; if not it \r
+    can be viewed here: http://www.freertos.org/a00114.html and also obtained \r
+    by writing to Richard Barry, contact details for whom are available on the\r
+    FreeRTOS WEB site.\r
+\r
+    1 tab == 4 spaces!\r
+\r
+    http://www.FreeRTOS.org - Documentation, latest information, license and\r
+    contact details.\r
+\r
+    http://www.SafeRTOS.com - A version that is certified for use in safety\r
+    critical systems.\r
+\r
+    http://www.OpenRTOS.com - Commercial support, development, porting,\r
+    licensing and training services.\r
+*/\r
+\r
+/*\r
+ * This is a simple demo that creates a number of tasks from a pool of\r
+ * 'standard demo tasks' which are used by all the FreeRTOS port demos.  The\r
+ * standard demo tasks don't provide any useful functionality other than to\r
+ * demonstrate the FreeRTOS API being used and show how the scheduler behaves.\r
+ *\r
+ * A COM test is included whereby one task transmits characters on the UART\r
+ * which are then received by another task.  A loopback connector is required\r
+ * on the UART1 connector for this test to pass (pins 2 and 3 need to be\r
+ * connected together - a paper clip is usually all that is required).  LED\r
+ * 5 red and green are under the control of the COM test tasks.  Red will toggle\r
+ * each time a character is successfully transmitted, and the green LED toggles\r
+ * for each received character.\r
+ *\r
+ * In addition this file creates a 'Check' task.  This periodically inspects\r
+ * the standard demo tasks and makes a few other simple tests to see if the\r
+ * system is performing as expected.  The check task toggles LED 6 green every\r
+ * 3 seconds provided no errors exist and sets it to red if an error has\r
+ * occurred.  The toggle rate will increase to 500ms if an error is detected\r
+ * at any time.  This mechanism can be tested by removing the loopback\r
+ * connector from UART1, and in so doing deliberately generating an error in\r
+ * the COM test task.\r
+ *\r
+ * LED 1 through 4 are controlled by simple LED flashing tasks.  Each should\r
+ * toggle at a fixed but different frequency.\r
+ *\r
+ */\r
+\r
+#include <stdio.h>\r
+#include <stdlib.h>\r
+#include <string.h>\r
+\r
+/* Environment header files. */\r
+#include "pm.h"\r
+\r
+/* Scheduler header files. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/* Demo file headers. */\r
+#include "partest.h"\r
+#include "serial.h"\r
+#include "integer.h"\r
+#include "comtest.h"\r
+#include "PollQ.h"\r
+#include "semtest.h"\r
+#include "dynamic.h"\r
+#include "BlockQ.h"\r
+#include "death.h"\r
+#include "flop.h"\r
+#include "flash.h"\r
+\r
+/* Task priorities. */\r
+#define mainLED_TASK_PRIORITY     ( tskIDLE_PRIORITY + 1 )\r
+#define mainCOM_TEST_PRIORITY     ( tskIDLE_PRIORITY + 2 )\r
+#define mainQUEUE_POLL_PRIORITY   ( tskIDLE_PRIORITY + 2 )\r
+#define mainSEM_TEST_PRIORITY     ( tskIDLE_PRIORITY + 1 )\r
+#define mainBLOCK_Q_PRIORITY      ( tskIDLE_PRIORITY + 3 )\r
+#define mainCHECK_TASK_PRIORITY   ( tskIDLE_PRIORITY + 4 )\r
+#define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 )\r
+#define mainFLASH_TASK_PRIORITY   ( tskIDLE_PRIORITY + 1 )\r
+\r
+/* Baud rate used by the loopback test task. */\r
+#define mainCOM_TEST_BAUD_RATE    ( ( unsigned long ) 38400 )\r
+\r
+/* LED used by the serial port tasks.  This is toggled on each character Tx,\r
+and mainCOM_TEST_LED + 1 is toggled on each character Rx. */\r
+#define mainCOM_TEST_LED          ( 4 )\r
+\r
+/* LED that is toggled by the check task.  The check task periodically checks\r
+that all the other tasks are operating without error.  If an error is found at\r
+any time the LED toggle frequency increases. */\r
+#define mainCHECK_TASK_LED        ( 6 )\r
+\r
+/* The frequency at which the check task executes assuming no errors have been\r
+found.  portTICK_RATE_MS is used to convert milliseconds to ticks, depending on\r
+the tick frequency. */\r
+#define mainNO_ERROR_FLASH_RATE          ( ( portTickType ) 3000 / portTICK_RATE_MS  )\r
+\r
+/* The frequency at which the check task executes if an error has been found\r
+in any of the demo tasks. */\r
+#define mainERROR_FLASH_RATE      ( (portTickType) 500 / portTICK_RATE_MS )\r
+\r
+/* The LED to use by the simple flash task. */\r
+#define mainSIMPLE_FLASH_LED      ( 0 )\r
+\r
+/* The frequency of the simple flashing LED. */\r
+#define mainSIMPLE_FLASH_RATE     ( ( portTickType ) 200 / portTICK_RATE_MS )\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * The 'Check' task that executes at the highest priority and calls\r
+ * prvCheckOtherTasksAreStillRunning().  See the description at the top\r
+ * of the file.\r
+ */\r
+static void prvErrorChecks( void *pvParameters );\r
+\r
+/*\r
+ * Checks that all the demo application tasks are still executing without error\r
+ * - as described at the top of the file.\r
+ */\r
+static portBASE_TYPE prvCheckOtherTasksAreStillRunning( void );\r
+/*-----------------------------------------------------------*/\r
+\r
+int main( void )\r
+{\r
+       /* Start the crystal oscillator 0 and switch the main clock to it. */\r
+       pm_switch_to_osc0(&AVR32_PM, FOSC0, OSC0_STARTUP);\r
+\r
+       /* Setup the LED's for output. */\r
+       vParTestInitialise();\r
+\r
+       /* Start the standard demo tasks. */\r
+       vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainCOM_TEST_BAUD_RATE, mainCOM_TEST_LED );\r
+       vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY );\r
+       vStartIntegerMathTasks( tskIDLE_PRIORITY );\r
+       vStartSemaphoreTasks( mainSEM_TEST_PRIORITY );\r
+       vStartDynamicPriorityTasks();\r
+       vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY );\r
+       vStartMathTasks( tskIDLE_PRIORITY );\r
+       vStartLEDFlashTasks( mainLED_TASK_PRIORITY );\r
+\r
+       /* Start the demo tasks defined within this file, first the check\r
+       task as described at the top of this file. */\r
+       xTaskCreate( prvErrorChecks,                                            /* The function that implements the task. */\r
+                            ( const signed char * ) "ErrCheck",        /* The name of the task.  The kernel does not use this, its just to facilitate debugging. */\r
+                            configMINIMAL_STACK_SIZE,                          /* The size of the stack (in words) that should be allocated to the task. */\r
+                            NULL,                                                              /* No task parameter is being used. */\r
+                            mainCHECK_TASK_PRIORITY,                           /* The priority to assign to the task, 0 being the lowest priority, configMAX_PRIORITIES - 1 being the highest priority. */\r
+                            NULL );                                                            /* Not interested in receiving a handle to the task being created, so just passing in NULL. */\r
+\r
+       /* This task has to be created last as it keeps account of the number of\r
+       tasks it expects to see running. */\r
+       vCreateSuicidalTasks( mainCREATOR_TASK_PRIORITY );\r
+\r
+       /* Start the scheduler. */\r
+       vTaskStartScheduler();\r
+\r
+       /* Will only get here if there was insufficient memory to create the idle\r
+       task. */\r
+       for( ;; );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvErrorChecks( void *pvParameters )\r
+{\r
+portTickType xDelayPeriod = mainNO_ERROR_FLASH_RATE;\r
+\r
+       /* The parameters are not used.  Prevent compiler warnings. */\r
+       ( void ) pvParameters;\r
+\r
+       /* Cycle for ever, delaying then checking all the other tasks are still\r
+       operating without error. */\r
+       vParTestSetLED( mainCHECK_TASK_LED, pdFALSE );\r
+\r
+       for( ;; )\r
+       {\r
+               /* Delay until it is time to execute again. */\r
+               vTaskDelay( xDelayPeriod );\r
+\r
+               /* Check all other tasks are still operating without error.\r
+               Check that vMemCheckTask did increment the counter. */\r
+               if( prvCheckOtherTasksAreStillRunning() != pdPASS )\r
+               {\r
+                       /* An error has occurred in one of the tasks.  Increase the\r
+                       frequency at which this task executes and in so doing increase\r
+                       the rate at which the mainCHECK_TASK_LED toggles. */\r
+                       xDelayPeriod = mainERROR_FLASH_RATE;\r
+                       vParTestSetLED( mainCHECK_TASK_LED, pdTRUE );\r
+               }\r
+\r
+               /* Toggle the LED - the frequency of the LED toggle indicates the\r
+               health of the system. */\r
+               vParTestToggleLED( mainCHECK_TASK_LED + 1 );\r
+       }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static portBASE_TYPE prvCheckOtherTasksAreStillRunning( void )\r
+{\r
+portBASE_TYPE xStatus = pdPASS;\r
+\r
+       if( xAreComTestTasksStillRunning() != pdPASS )\r
+       {\r
+               xStatus = pdFAIL;\r
+       }\r
+\r
+       if( xArePollingQueuesStillRunning() != pdPASS )\r
+       {\r
+               xStatus = pdFAIL;\r
+       }\r
+\r
+       if( xAreIntegerMathsTaskStillRunning() != pdPASS )\r
+       {\r
+               xStatus = pdFAIL;\r
+       }\r
+\r
+       if( xAreSemaphoreTasksStillRunning() != pdPASS )\r
+       {\r
+               xStatus = pdFAIL;\r
+       }\r
+\r
+       if( xAreBlockingQueuesStillRunning() != pdPASS )\r
+       {\r
+               xStatus = pdFAIL;\r
+       }\r
+\r
+       if( xAreDynamicPriorityTasksStillRunning() != pdPASS )\r
+       {\r
+               xStatus = pdFAIL;\r
+       }\r
+\r
+       if( xAreMathsTaskStillRunning() != pdPASS )\r
+       {\r
+               xStatus = pdFAIL;\r
+       }\r
+\r
+       if( xIsCreateTaskStillRunning() != pdPASS )\r
+       {\r
+               xStatus = pdFAIL;\r
+       }\r
+\r
+       return xStatus;\r
+}\r
+/*-----------------------------------------------------------*/\r

diff --git a/Demo/AVR32_UC3A_GCC/serial/serial.c b/Demo/AVR32_UC3A_GCC/serial/serial.c
new file mode 100644 (file)
index 0000000..6221462
--- /dev/null
+++ b/Demo/AVR32_UC3A_GCC/serial/serial.c
@@ -0,0 +1,373 @@
+/*This file has been prepared for Doxygen automatic documentation generation.*/\r
+/*! \file *********************************************************************\r
+ *\r
+ * \brief FreeRTOS Serial Port management example for AVR32 UC3.\r
+ *\r
+ * - Compiler:           IAR EWAVR32 and GNU GCC for AVR32\r
+ * - Supported devices:  All AVR32 devices can be used.\r
+ * - AppNote:\r
+ *\r
+ * \author               Atmel Corporation: http://www.atmel.com \n\r
+ *                       Support and FAQ: http://support.atmel.no/\r
+ *\r
+ *****************************************************************************/\r
+\r
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of ATMEL may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND\r
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,\r
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\r
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\r
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF\r
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ */\r
+\r
+\r
+/*\r
+  BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER FOR USART.\r
+*/\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "queue.h"\r
+#include "task.h"\r
+\r
+/* Demo application includes. */\r
+#include "serial.h"\r
+#include <avr32/io.h>\r
+#include "board.h"\r
+#include "gpio.h"\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Constants to setup and access the USART. */\r
+#define serINVALID_COMPORT_HANDLER        ( ( xComPortHandle ) 0 )\r
+#define serINVALID_QUEUE                  ( ( xQueueHandle ) 0 )\r
+#define serHANDLE                         ( ( xComPortHandle ) 1 )\r
+#define serNO_BLOCK                       ( ( portTickType ) 0 )\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Queues used to hold received characters, and characters waiting to be\r
+transmitted. */\r
+static xQueueHandle xRxedChars;\r
+static xQueueHandle xCharsForTx;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Forward declaration. */\r
+static void vprvSerialCreateQueues( unsigned portBASE_TYPE uxQueueLength,\r
+                                                                       xQueueHandle *pxRxedChars,\r
+                                                                       xQueueHandle *pxCharsForTx );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+#if __GNUC__\r
+       __attribute__((__noinline__))\r
+#elif __ICCAVR32__\r
+       #pragma optimize = no_inline\r
+#endif\r
+\r
+static portBASE_TYPE prvUSART_ISR_NonNakedBehaviour( void )\r
+{\r
+       /* Now we can declare the local variables. */\r
+       signed portCHAR     cChar;\r
+       portBASE_TYPE     xHigherPriorityTaskWoken = pdFALSE;\r
+       unsigned portLONG     ulStatus;\r
+       volatile avr32_usart_t  *usart = serialPORT_USART;\r
+       portBASE_TYPE retstatus;\r
+\r
+       /* What caused the interrupt? */\r
+       ulStatus = usart->csr & usart->imr;\r
+\r
+       if (ulStatus & AVR32_USART_CSR_TXRDY_MASK)\r
+       {\r
+               /* The interrupt was caused by the THR becoming empty.  Are there any\r
+               more characters to transmit?\r
+               Because FreeRTOS is not supposed to run with nested interrupts, put all OS\r
+               calls in a critical section . */\r
+               portENTER_CRITICAL();\r
+                       retstatus = xQueueReceiveFromISR( xCharsForTx, &cChar, &xHigherPriorityTaskWoken );\r
+               portEXIT_CRITICAL();\r
+\r
+               if (retstatus == pdTRUE)\r
+               {\r
+                       /* A character was retrieved from the queue so can be sent to the\r
+                        THR now. */\r
+                       usart->thr = cChar;\r
+               }\r
+               else\r
+               {\r
+                       /* Queue empty, nothing to send so turn off the Tx interrupt. */\r
+                       usart->idr = AVR32_USART_IDR_TXRDY_MASK;\r
+               }\r
+       }\r
+\r
+       if (ulStatus & AVR32_USART_CSR_RXRDY_MASK)\r
+       {\r
+               /* The interrupt was caused by the receiver getting data. */\r
+               cChar = usart->rhr; //TODO\r
+\r
+               /* Because FreeRTOS is not supposed to run with nested interrupts, put all OS\r
+               calls in a critical section . */\r
+               portENTER_CRITICAL();\r
+                       xQueueSendFromISR(xRxedChars, &cChar, &xHigherPriorityTaskWoken);\r
+               portEXIT_CRITICAL();\r
+       }\r
+\r
+       /* The return value will be used by portEXIT_SWITCHING_ISR() to know if it\r
+       should perform a vTaskSwitchContext(). */\r
+       return ( xHigherPriorityTaskWoken );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * USART interrupt service routine.\r
+ */\r
+#if __GNUC__\r
+       __attribute__((__naked__))\r
+#elif __ICCAVR32__\r
+       #pragma shadow_registers = full   // Naked.\r
+#endif\r
+\r
+static void vUSART_ISR( void )\r
+{\r
+       /* This ISR can cause a context switch, so the first statement must be a\r
+       call to the portENTER_SWITCHING_ISR() macro.  This must be BEFORE any\r
+       variable declarations. */\r
+       portENTER_SWITCHING_ISR();\r
+\r
+       prvUSART_ISR_NonNakedBehaviour();\r
+\r
+       /* Exit the ISR.  If a task was woken by either a character being received\r
+       or transmitted then a context switch will occur. */\r
+       portEXIT_SWITCHING_ISR();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+\r
+/*\r
+ * Init the serial port for the Minimal implementation.\r
+ */\r
+xComPortHandle xSerialPortInitMinimal( unsigned portLONG ulWantedBaud, unsigned portBASE_TYPE uxQueueLength )\r
+{\r
+static const gpio_map_t USART_GPIO_MAP =\r
+{\r
+       { serialPORT_USART_RX_PIN, serialPORT_USART_RX_FUNCTION },\r
+       { serialPORT_USART_TX_PIN, serialPORT_USART_TX_FUNCTION }\r
+};\r
+\r
+xComPortHandle    xReturn = serHANDLE;\r
+volatile avr32_usart_t  *usart = serialPORT_USART;\r
+int cd; /* USART Clock Divider. */\r
+\r
+       /* Create the rx and tx queues. */\r
+       vprvSerialCreateQueues( uxQueueLength, &xRxedChars, &xCharsForTx );\r
+\r
+       /* Configure USART. */\r
+       if( ( xRxedChars != serINVALID_QUEUE ) &&\r
+         ( xCharsForTx != serINVALID_QUEUE ) &&\r
+         ( ulWantedBaud != ( unsigned portLONG ) 0 ) )\r
+       {\r
+               portENTER_CRITICAL();\r
+               {\r
+                       /**\r
+                       ** Reset USART.\r
+                       **/\r
+                       /* Disable all USART interrupt sources to begin... */\r
+                       usart->idr = 0xFFFFFFFF;\r
+\r
+                       /* Reset mode and other registers that could cause unpredictable\r
+                        behaviour after reset */\r
+                       usart->mr = 0; /* Reset Mode register. */\r
+                       usart->rtor = 0; /* Reset Receiver Time-out register. */\r
+                       usart->ttgr = 0; /* Reset Transmitter Timeguard register. */\r
+\r
+                       /* Shutdown RX and TX, reset status bits, reset iterations in CSR, reset NACK\r
+                        and turn off DTR and RTS */\r
+                       usart->cr = AVR32_USART_CR_RSTRX_MASK   |\r
+                                          AVR32_USART_CR_RSTTX_MASK   |\r
+                                          AVR32_USART_CR_RXDIS_MASK   |\r
+                                          AVR32_USART_CR_TXDIS_MASK   |\r
+                                          AVR32_USART_CR_RSTSTA_MASK  |\r
+                                          AVR32_USART_CR_RSTIT_MASK   |\r
+                                          AVR32_USART_CR_RSTNACK_MASK |\r
+                                          AVR32_USART_CR_DTRDIS_MASK  |\r
+                                          AVR32_USART_CR_RTSDIS_MASK;\r
+\r
+                       /**\r
+                       ** Configure USART.\r
+                       **/\r
+                       /* Enable USART RXD & TXD pins. */\r
+                       gpio_enable_module( USART_GPIO_MAP, sizeof( USART_GPIO_MAP ) / sizeof( USART_GPIO_MAP[0] ) );\r
+\r
+                       /* Set the USART baudrate to be as close as possible to the wanted baudrate. */\r
+                       /*\r
+                       *             ** BAUDRATE CALCULATION **\r
+                       *\r
+                       *                 Selected Clock                       Selected Clock\r
+                       *     baudrate = ----------------   or     baudrate = ----------------\r
+                       *                    16 x CD                              8 x CD\r
+                       *\r
+                       *       (with 16x oversampling)              (with 8x oversampling)\r
+                       */\r
+\r
+                       if( ulWantedBaud < ( configCPU_CLOCK_HZ / 16 ) )\r
+                       {\r
+                               /* Use 8x oversampling */\r
+                               usart->mr |= (1<<AVR32_USART_MR_OVER_OFFSET);\r
+                               cd = configCPU_CLOCK_HZ / (8*ulWantedBaud);\r
+\r
+                               if( cd < 2 )\r
+                               {\r
+                                       return serINVALID_COMPORT_HANDLER;\r
+                               }\r
+\r
+                               usart->brgr = (cd << AVR32_USART_BRGR_CD_OFFSET);\r
+                       }\r
+                       else\r
+                       {\r
+                               /* Use 16x oversampling */\r
+                               usart->mr &= ~(1<<AVR32_USART_MR_OVER_OFFSET);\r
+                               cd = configCPU_CLOCK_HZ / (16*ulWantedBaud);\r
+\r
+                               if( cd > 65535 )\r
+                               {\r
+                                       /* Baudrate is too low */\r
+                                       return serINVALID_COMPORT_HANDLER;\r
+                               }\r
+                       }\r
+\r
+                       usart->brgr = (cd << AVR32_USART_BRGR_CD_OFFSET);\r
+\r
+                       /* Set the USART Mode register: Mode=Normal(0), Clk selection=MCK(0),\r
+                       CHRL=8,  SYNC=0(asynchronous), PAR=None, NBSTOP=1, CHMODE=0, MSBF=0,\r
+                       MODE9=0, CKLO=0, OVER(previously done when setting the baudrate),\r
+                       other fields not used in this mode. */\r
+                       usart->mr |= ((8-5) << AVR32_USART_MR_CHRL_OFFSET  ) |\r
+                                       (   4  << AVR32_USART_MR_PAR_OFFSET   ) |\r
+                                       (   1  << AVR32_USART_MR_NBSTOP_OFFSET);\r
+\r
+                       /* Write the Transmit Timeguard Register */\r
+                       usart->ttgr = 0;\r
+\r
+\r
+                       /* Register the USART interrupt handler to the interrupt controller and\r
+                        enable the USART interrupt. */\r
+                       INTC_register_interrupt((__int_handler)&vUSART_ISR, serialPORT_USART_IRQ, AVR32_INTC_INT1);\r
+\r
+                       /* Enable USART interrupt sources (but not Tx for now)... */\r
+                       usart->ier = AVR32_USART_IER_RXRDY_MASK;\r
+\r
+                       /* Enable receiver and transmitter... */\r
+                       usart->cr |= AVR32_USART_CR_TXEN_MASK | AVR32_USART_CR_RXEN_MASK;\r
+               }\r
+               portEXIT_CRITICAL();\r
+       }\r
+       else\r
+       {\r
+               xReturn = serINVALID_COMPORT_HANDLER;\r
+       }\r
+\r
+       return xReturn;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed portCHAR *pcRxedChar, portTickType xBlockTime )\r
+{\r
+       /* The port handle is not required as this driver only supports UART0. */\r
+       ( void ) pxPort;\r
+\r
+       /* Get the next character from the buffer.  Return false if no characters\r
+       are available, or arrive before xBlockTime expires. */\r
+       if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) )\r
+       {\r
+               return pdTRUE;\r
+       }\r
+       else\r
+       {\r
+               return pdFALSE;\r
+       }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vSerialPutString( xComPortHandle pxPort, const signed portCHAR * const pcString, unsigned portSHORT usStringLength )\r
+{\r
+signed portCHAR *pxNext;\r
+\r
+       /* NOTE: This implementation does not handle the queue being full as no\r
+       block time is used! */\r
+\r
+       /* The port handle is not required as this driver only supports UART0. */\r
+       ( void ) pxPort;\r
+\r
+       /* Send each character in the string, one at a time. */\r
+       pxNext = ( signed portCHAR * ) pcString;\r
+       while( *pxNext )\r
+       {\r
+               xSerialPutChar( pxPort, *pxNext, serNO_BLOCK );\r
+               pxNext++;\r
+       }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed portCHAR cOutChar, portTickType xBlockTime )\r
+{\r
+volatile avr32_usart_t  *usart = serialPORT_USART;\r
+\r
+       /* Place the character in the queue of characters to be transmitted. */\r
+       if( xQueueSend( xCharsForTx, &cOutChar, xBlockTime ) != pdPASS )\r
+       {\r
+               return pdFAIL;\r
+       }\r
+\r
+       /* Turn on the Tx interrupt so the ISR will remove the character from the\r
+       queue and send it.   This does not need to be in a critical section as\r
+       if the interrupt has already removed the character the next interrupt\r
+       will simply turn off the Tx interrupt again. */\r
+       usart->ier = (1 << AVR32_USART_IER_TXRDY_OFFSET);\r
+\r
+       return pdPASS;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vSerialClose( xComPortHandle xPort )\r
+{\r
+  /* Not supported as not required by the demo application. */\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/*###########################################################*/\r
+\r
+/*\r
+ * Create the rx and tx queues.\r
+ */\r
+static void vprvSerialCreateQueues(  unsigned portBASE_TYPE uxQueueLength, xQueueHandle *pxRxedChars, xQueueHandle *pxCharsForTx )\r
+{\r
+       /* Create the queues used to hold Rx and Tx characters. */\r
+       xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) );\r
+       xCharsForTx = xQueueCreate( uxQueueLength + 1, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) );\r
+\r
+       /* Pass back a reference to the queues so the serial API file can\r
+       post/receive characters. */\r
+       *pxRxedChars = xRxedChars;\r
+       *pxCharsForTx = xCharsForTx;\r
+}\r
+/*-----------------------------------------------------------*/\r

diff --git a/Demo/AVR32_UC3A_GCC/trampoline.S b/Demo/AVR32_UC3A_GCC/trampoline.S
new file mode 100644 (file)
index 0000000..3611581
--- /dev/null
+++ b/Demo/AVR32_UC3A_GCC/trampoline.S
@@ -0,0 +1,72 @@
+/*This file is prepared for Doxygen automatic documentation generation.*/\r
+/*! \file *********************************************************************\r
+ *\r
+ * \brief AVR32 UC3 ISP trampoline.\r
+ *\r
+ * In order to be able to program a project with both BatchISP and JTAGICE mkII\r
+ * without having to take the general-purpose fuses into consideration, add this\r
+ * file to the project and change the program entry point to _trampoline.\r
+ *\r
+ * The pre-programmed ISP will be erased if JTAGICE mkII is used.\r
+ *\r
+ * - Compiler:           GNU GCC for AVR32\r
+ * - Supported devices:  All AVR32UC devices can be used.\r
+ *\r
+ * \author               Atmel Corporation: http://www.atmel.com \n\r
+ *                       Support and FAQ: http://support.atmel.no/\r
+ *\r
+ ******************************************************************************/\r
+\r
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of ATMEL may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND\r
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,\r
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\r
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\r
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF\r
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ */\r
+\r
+\r
+#include "conf_isp.h"\r
+\r
+\r
+//! @{\r
+//! \verbatim\r
+\r
+\r
+  // This must be linked @ 0x80000000 if it is to be run upon reset.\r
+  .section  .reset, "ax", @progbits\r
+\r
+\r
+  .global _trampoline\r
+  .type _trampoline, @function\r
+_trampoline:\r
+  // Jump to program start.\r
+  rjmp    program_start\r
+\r
+  .org  0x00002000\r
+program_start:\r
+  // Jump to the C runtime startup routine.\r
+  lda.w   pc, _stext\r
+\r
+\r
+//! \endverbatim\r
+//! @}\r