target: am437x: use more descriptive names

Use more descriptive names for JRC and DAPs
so they more closely match documentation.

For example there's no Cortex A9 DAP, that's
the DebugSS DAP where Cortex A9 target sits. In
that same DAP we have have ETM, STM and both
dual-PRU subsystems.

Change-Id: I0e66ebb6299763f96606fae3e4c62e5785c804f2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Reviewed-on: http://openocd.zylin.com/2620
Tested-by: jenkins
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Paul Fertser <fercerpav@gmail.com>

diff --git a/tcl/target/am437x.cfg b/tcl/target/am437x.cfg
index 8b51f996791fb39788b104950a146a3c035459c6..1e3cbc52c463158d5c78363df4787e4d239b1784 100644 (file)
--- a/tcl/target/am437x.cfg
+++ b/tcl/target/am437x.cfg
@@ -439,27 +439,36 @@ if { [info exists CHIPNAME] } {
    set _CHIPNAME am437x
 }
 
+set JRC_MODULE         icepick_d
+set DEBUGSS_MODULE     debugss
+set M3_MODULE          m3_wakeupss
+
+set JRC_NAME           $_CHIPNAME.$JRC_MODULE
+set DEBUGSS_NAME       $_CHIPNAME.$DEBUGSS_MODULE
+set M3_NAME            $_CHIPNAME.$M3_MODULE
+set _TARGETNAME                $_CHIPNAME.mpuss
+
 #
-# M3 DAP
+# M3 WakeupSS DAP
 #
 if { [info exists M3_DAP_TAPID] } {
        set _M3_DAP_TAPID $M3_DAP_TAPID
 } else {
        set _M3_DAP_TAPID 0x4b6b902f
 }
-jtag newtap $_CHIPNAME m3_dap -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_M3_DAP_TAPID -disable
-jtag configure $_CHIPNAME.m3_dap -event tap-enable "icepick_d_tapenable $_CHIPNAME.jrc 11"
+jtag newtap $_CHIPNAME $M3_MODULE -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_M3_DAP_TAPID -disable
+jtag configure $M3_NAME -event tap-enable "icepick_d_tapenable $JRC_NAME 11"
 
 #
-# Cortex A9 DAP
+# DebugSS DAP
 #
 if { [info exists DAP_TAPID] } {
    set _DAP_TAPID $DAP_TAPID
 } else {
    set _DAP_TAPID 0x46b6902f
 }
-jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID -disable
-jtag configure $_CHIPNAME.dap -event tap-enable "icepick_d_tapenable $_CHIPNAME.jrc 12"
+jtag newtap $_CHIPNAME $DEBUGSS_MODULE -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID -disable
+jtag configure $DEBUGSS_NAME -event tap-enable "icepick_d_tapenable $JRC_NAME 12"
 
 #
 # ICEpick-D (JTAG route controller)
@@ -469,16 +478,16 @@ if { [info exists JRC_TAPID] } {
 } else {
    set _JRC_TAPID 0x0b98c02f
 }
-jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f -expected-id $_JRC_TAPID -ignore-version
-jtag configure $_CHIPNAME.jrc -event setup "jtag tapenable $_CHIPNAME.dap"
-# some TCK tycles are required to activate the DEBUG power domain
-jtag configure $_CHIPNAME.jrc -event post-reset "runtest 100"
+jtag newtap $_CHIPNAME $JRC_MODULE -irlen 6 -ircapture 0x1 -irmask 0x3f -expected-id $_JRC_TAPID -ignore-version
+jtag configure $JRC_NAME -event setup "jtag tapenable $DEBUGSS_NAME"
+ # some TCK tycles are required to activate the DEBUG power domain
+jtag configure $JRC_NAME -event post-reset "runtest 100"
 
 #
 # Cortex A9 target
 #
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_a -chain-position $_CHIPNAME.dap -dbgbase 0x80000000
+target create $_TARGETNAME cortex_a -chain-position $DEBUGSS_NAME -dbgbase 0x80000000
+
 
 # SRAM: 256K at 0x4030.0000
 $_TARGETNAME configure -work-area-phys 0x40300000 -work-area-size 0x40000