*/
int jtag_error=ERROR_OK;
+
typedef struct cmd_queue_page_s
{
void *address;
return retval;
}
+static const char *jtag_tap_name(jtag_tap_t *tap)
+{
+ return (tap == NULL) ? "(unknown)" : tap->dotted_name;
+}
+
int jtag_check_value(u8 *captured, void *priv, scan_field_t *field)
{
int retval = ERROR_OK;
* acknowledged the error
*/
LOG_WARNING("TAP %s:",
- (field->tap == NULL) ? "(unknown)" : field->tap->dotted_name );
+ jtag_tap_name(field->tap));
if (compare_failed)
{
char *captured_char = buf_to_str(captured, (num_bits > 64) ? 64 : num_bits, 16);
tap = NULL;
chain_pos = 0;
+ int val;
for(;;){
tap = jtag_NextEnabledTap(tap);
if( tap == NULL ){
break;
}
-
- if (buf_get_u32(ir_test, chain_pos, 2) != 0x1)
+ val = buf_get_u32(ir_test, chain_pos, 2);
+ if (val != 0x1)
{
char *cbuf = buf_to_str(ir_test, total_ir_length, 16);
- LOG_ERROR("Error validating JTAG scan chain, IR mismatch, scan returned 0x%s", cbuf);
+ LOG_ERROR("Could not validate JTAG scan chain, IR mismatch, scan returned 0x%s. tap=%s pos=%d expected 0x1 got %0x", cbuf, jtag_tap_name(tap), chain_pos, val);
free(cbuf);
free(ir_test);
return ERROR_JTAG_INIT_FAILED;
chain_pos += tap->ir_length;
}
- if (buf_get_u32(ir_test, chain_pos, 2) != 0x3)
+ val = buf_get_u32(ir_test, chain_pos, 2);
+ if (val != 0x3)
{
char *cbuf = buf_to_str(ir_test, total_ir_length, 16);
- LOG_ERROR("Error validating JTAG scan chain, IR mismatch, scan returned 0x%s", cbuf);
+ LOG_ERROR("Could not validate end of JTAG scan chain, IR mismatch, scan returned 0x%s. pos=%d expected 0x3 got %0x", cbuf, chain_pos, val);
free(cbuf);
free(ir_test);
return ERROR_JTAG_INIT_FAILED;
if (jtag_validate_chain() != ERROR_OK)
{
- LOG_ERROR("Could not validate JTAG chain, continuing anyway...");
+ LOG_WARNING("Could not validate JTAG chain, continuing anyway...");
}
return ERROR_OK;
}
}
+
/* map state number to SVF state string */
const char* jtag_state_name(enum tap_state state)
{
return ret;
}
+
# SDMA_BYPASS - disables SDMA -
#
# Per ARM: DDI0211J_arm1136_r1p5_trm.pdf - the ARM 1136 as a 5 bit IR register
-jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_CPUTAPID
# No IDCODE for this TAP
jtag newtap $_CHIPNAME whatchacallit -irlen 4 -ircapture 0 -irmask 0xf -expected-id 0x0
# Per section 40.17.1, table 40-85 the IR register is 4 bits
# But this conflicts with Diagram 6-13, "3bits ir and drs"
-jtag newtap $_CHIPNAME smda -irlen 5 -ircapture 0x1 -irmask 0xf -expected-id $_SDMATAPID
+jtag newtap $_CHIPNAME smda -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_SDMATAPID
set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
target create $_TARGETNAME arm11 -endian $_ENDIAN -chain-position $_TARGETNAME