Rename directories in the RISC-V port.

git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2610 1d2547de-c912-0410-9cb9-b8ca96c0e9e2

diff --git a/FreeRTOS/Source/portable/GCC/RISC-V-RV32/CLINT/freertos_risc_v_port_specific_extensions.h b/FreeRTOS/Source/portable/GCC/RISC-V-RV32/CLINT/freertos_risc_v_port_specific_extensions.h
deleted file mode 100644 (file)
index 85013b7..0000000
--- a/FreeRTOS/Source/portable/GCC/RISC-V-RV32/CLINT/freertos_risc_v_port_specific_extensions.h
+++ /dev/null
@@ -1,74 +0,0 @@
-/*\r
- * FreeRTOS Kernel V10.1.1\r
- * Copyright (C) 2018 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\r
- *\r
- * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
- * this software and associated documentation files (the "Software"), to deal in\r
- * the Software without restriction, including without limitation the rights to\r
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
- * the Software, and t\r
-\r
- o permit persons to whom the Software is furnished to do so,\r
- * subject to the following conditions:\r
- *\r
- * The above copyright notice and this permission notice shall be included in all\r
- * copies or substantial portions of the Software.\r
- *\r
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
- *\r
- * http://www.FreeRTOS.org\r
- * http://aws.amazon.com/freertos\r
- *\r
- * 1 tab == 4 spaces!\r
- */\r
-\r
-/*\r
- * The FreeRTOS kernel's RISC-V port is split between the the code that is\r
- * common across all currently supported RISC-V chips (implementations of the\r
- * RISC-V ISA), and code which tailors the port to a specific RISC-V chip:\r
- *\r
- * + The code that is common to all RISC-V chips is implemented in\r
- *   FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S.  There is only one\r
- *   portASM.S file because the same file is used no matter which RISC-V chip is\r
- *   in use.\r
- *\r
- * + The code that tailors the kernel's RISC-V port to a specific RISC-V\r
- *   chip is implemented in freertos_risc_v_port_specific_extensions.h.  There\r
- *   is one freertos_risc_v_port_specific_extensions.h that can be used with any\r
- *   RISC-V chip that both includes a standard CLINT and does not add to the\r
- *   base set of RISC-V registers.  There are additional\r
- *   freertos_risc_v_port_specific_extensions.h files for RISC-V implementations\r
- *   that do not include a standard CLINT or do add to the base set of RISC-V\r
- *   regiters.\r
- *\r
- * CARE MUST BE TAKEN TO INCLDUE THE CORRECT\r
- * freertos_risc_v_port_specific_extensions.h HEADER FILE FOR THE CHIP\r
- * IN USE.  To include the correct freertos_risc_v_port_specific_extensions.h\r
- * header file ensure the path to the correct header file is in the assembler's\r
- * include path.\r
- *\r
- * This freertos_risc_v_port_specific_extensions.h is for use on RISC-V chips\r
- * that include a standard CLINT and do not add to the base set of RISC-V\r
- * registers.\r
- *\r
- */\r
-\r
-#ifndef __FREERTOS_RISC_V_EXTENSIONS_H__\r
-#define __FREERTOS_RISC_V_EXTENSIONS_H__\r
-\r
-.macro portSAVE_ADDITIONAL_REGISTERS\r
-       /* This file is for use with chips that do not add to the standard RISC-V\r
-        * register set, so there is nothing to do here. */\r
-       .endm\r
-\r
-.macro portRESTORE_ADDITIONAL_REGISTERS\r
-       /* This file is for use with chips that do not add to the standard RISC-V\r
-        * register set, so there is nothing to do here. */\r
-       .endm\r
-\r
-#endif /* __FREERTOS_RISC_V_EXTENSIONS_H__ */\r

diff --git a/FreeRTOS/Source/portable/GCC/RISC-V-RV32/CLINT_no_extensions/freertos_risc_v_port_specific_extensions.h b/FreeRTOS/Source/portable/GCC/RISC-V-RV32/CLINT_no_extensions/freertos_risc_v_port_specific_extensions.h
new file mode 100644 (file)
index 0000000..0252ecd
--- /dev/null
+++ b/FreeRTOS/Source/portable/GCC/RISC-V-RV32/CLINT_no_extensions/freertos_risc_v_port_specific_extensions.h
@@ -0,0 +1,66 @@
+/*\r
+ * FreeRTOS Kernel V10.1.1\r
+ * Copyright (C) 2018 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and t\r
+\r
+ o permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+/*\r
+ * The FreeRTOS kernel's RISC-V port is split between the the code that is\r
+ * common across all currently supported RISC-V chips (implementations of the\r
+ * RISC-V ISA), and code which tailors the port to a specific RISC-V chip:\r
+ *\r
+ * + The code that is common to all RISC-V chips is implemented in\r
+ *   FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S.  There is only one\r
+ *   portASM.S file because the same file is used no matter which RISC-V chip is\r
+ *   in use.\r
+ *\r
+ * + The code that tailors the kernel's RISC-V port to a specific RISC-V\r
+ *   chip is implemented in freertos_risc_v_port_specific_extensions.h.  There\r
+ *   is one freertos_risc_v_port_specific_extensions.h that can be used with any\r
+ *   RISC-V chip that both includes a standard CLINT and does not add to the\r
+ *   base set of RISC-V registers.  There are additional\r
+ *   freertos_risc_v_port_specific_extensions.h files for RISC-V implementations\r
+ *   that do not include a standard CLINT or do add to the base set of RISC-V\r
+ *   regiters.\r
+ *\r
+ * CARE MUST BE TAKEN TO INCLDUE THE CORRECT\r
+ * freertos_risc_v_port_specific_extensions.h HEADER FILE FOR THE CHIP\r
+ * IN USE.  To include the correct freertos_risc_v_port_specific_extensions.h\r
+ * header file ensure the path to the correct header file is in the assembler's\r
+ * include path.\r
+ *\r
+ * This freertos_risc_v_port_specific_extensions.h is for use on RISC-V chips\r
+ * that include a standard CLINT and do not add to the base set of RISC-V\r
+ * registers.\r
+ *\r
+ */\r
+\r
+#ifndef __FREERTOS_RISC_V_EXTENSIONS_H__\r
+#define __FREERTOS_RISC_V_EXTENSIONS_H__\r
+\r
+#define portasmHAS_CLINT 1\r
+\r
+#endif /* __FREERTOS_RISC_V_EXTENSIONS_H__ */\r

diff --git a/FreeRTOS/Source/portable/GCC/RISC-V-RV32/Pulpino_Vega_RV32M1RM/freertos_risc_v_port_specific_extensions.h b/FreeRTOS/Source/portable/GCC/RISC-V-RV32/Pulpino_Vega_RV32M1RM/freertos_risc_v_port_specific_extensions.h
new file mode 100644 (file)
index 0000000..e106b72
--- /dev/null
+++ b/FreeRTOS/Source/portable/GCC/RISC-V-RV32/Pulpino_Vega_RV32M1RM/freertos_risc_v_port_specific_extensions.h
@@ -0,0 +1,73 @@
+/*\r
+ * FreeRTOS Kernel V10.1.1\r
+ * Copyright (C) 2018 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and t\r
+\r
+ o permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+/*\r
+ * The FreeRTOS kernel's RISC-V port is split between the the code that is\r
+ * common across all currently supported RISC-V chips (implementations of the\r
+ * RISC-V ISA), and code which tailors the port to a specific RISC-V chip:\r
+ *\r
+ * + The code that is common to all RISC-V chips is implemented in\r
+ *   FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S.  There is only one\r
+ *   portASM.S file because the same file is used no matter which RISC-V chip is\r
+ *   in use.\r
+ *\r
+ * + The code that tailors the kernel's RISC-V port to a specific RISC-V\r
+ *   chip is implemented in freertos_risc_v_port_specific_extensions.h.  There\r
+ *   is one freertos_risc_v_port_specific_extensions.h that can be used with any\r
+ *   RISC-V chip that both includes a standard CLINT and does not add to the\r
+ *   base set of RISC-V registers.  There are additional\r
+ *   freertos_risc_v_port_specific_extensions.h files for RISC-V implementations\r
+ *   that do not include a standard CLINT or do add to the base set of RISC-V\r
+ *   regiters.\r
+ *\r
+ * CARE MUST BE TAKEN TO INCLDUE THE CORRECT\r
+ * freertos_risc_v_port_specific_extensions.h HEADER FILE FOR THE CHIP\r
+ * IN USE.  To include the correct freertos_risc_v_port_specific_extensions.h\r
+ * header file ensure the path to the correct header file is in the assembler's\r
+ * include path.\r
+ *\r
+ * This freertos_risc_v_port_specific_extensions.h is for use with Pulpino Ri5cy\r
+ * devices, developed and tested using the Vega board RV32M1RM.\r
+ *\r
+ */\r
+\r
+#ifndef __FREERTOS_RISC_V_EXTENSIONS_H__\r
+#define __FREERTOS_RISC_V_EXTENSIONS_H__\r
+\r
+#define portasmHAS_CLINT 0\r
+\r
+.macro portasmSAVE_ADDITIONAL_REGISTERS\r
+       .endm\r
+\r
+.macro portasmRESTORE_ADDITIONAL_REGISTERS\r
+       /* This file is for use with chips that do not add to the standard RISC-V\r
+        * register set, so there is nothing to do here. */\r
+       .endm\r
+\r
+#endif /* __FREERTOS_RISC_V_EXTENSIONS_H__ */\r

diff --git a/FreeRTOS/Source/portable/GCC/RISC-V-RV32/port.c b/FreeRTOS/Source/portable/GCC/RISC-V-RV32/port.c
index 95ec89e349922171ec8c6d4a8e15d476c1f8c9ac..3f9a981477c9945697e053afa1e815a02afe5885 100644 (file)
--- a/FreeRTOS/Source/portable/GCC/RISC-V-RV32/port.c
+++ b/FreeRTOS/Source/portable/GCC/RISC-V-RV32/port.c
@@ -206,27 +206,31 @@ const uint32_t ulMPIE_Bit = 0x80, ulMPP_Bits = 0x1800;
 }\r
 /*-----------------------------------------------------------*/\r
 \r
-void vPortSetupTimerInterrupt( void )\r
-{\r
-uint32_t ulCurrentTimeHigh, ulCurrentTimeLow;\r
-volatile uint32_t * const pulTimeHigh = ( volatile uint32_t * const ) ( configCLINT_BASE_ADDRESS + 0xBFFC );\r
-volatile uint32_t * const pulTimeLow = ( volatile uint32_t * const ) ( configCLINT_BASE_ADDRESS + 0xBFF8 );\r
+#if( configCLINT_BASE_ADDRESS != 0 )\r
 \r
-       do\r
+       void vPortSetupTimerInterrupt( void )\r
        {\r
-               ulCurrentTimeHigh = *pulTimeHigh;\r
-               ulCurrentTimeLow = *pulTimeLow;\r
-       } while( ulCurrentTimeHigh != *pulTimeHigh );\r
-\r
-       ullNextTime = ( uint64_t ) ulCurrentTimeHigh;\r
-       ullNextTime <<= 32ULL;\r
-       ullNextTime |= ( uint64_t ) ulCurrentTimeLow;\r
-       ullNextTime += ( uint64_t ) ulTimerIncrementsForOneTick;\r
-       *pullMachineTimerCompareRegister = ullNextTime;\r
-\r
-       /* Prepare the time to use after the next tick interrupt. */\r
-       ullNextTime += ( uint64_t ) ulTimerIncrementsForOneTick;\r
-}\r
+       uint32_t ulCurrentTimeHigh, ulCurrentTimeLow;\r
+       volatile uint32_t * const pulTimeHigh = ( volatile uint32_t * const ) ( configCLINT_BASE_ADDRESS + 0xBFFC );\r
+       volatile uint32_t * const pulTimeLow = ( volatile uint32_t * const ) ( configCLINT_BASE_ADDRESS + 0xBFF8 );\r
+\r
+               do\r
+               {\r
+                       ulCurrentTimeHigh = *pulTimeHigh;\r
+                       ulCurrentTimeLow = *pulTimeLow;\r
+               } while( ulCurrentTimeHigh != *pulTimeHigh );\r
+\r
+               ullNextTime = ( uint64_t ) ulCurrentTimeHigh;\r
+               ullNextTime <<= 32ULL;\r
+               ullNextTime |= ( uint64_t ) ulCurrentTimeLow;\r
+               ullNextTime += ( uint64_t ) ulTimerIncrementsForOneTick;\r
+               *pullMachineTimerCompareRegister = ullNextTime;\r
+\r
+               /* Prepare the time to use after the next tick interrupt. */\r
+               ullNextTime += ( uint64_t ) ulTimerIncrementsForOneTick;\r
+       }\r
+\r
+#endif /* ( configCLINT_BASE_ADDRESS != 0 ) */\r
 /*-----------------------------------------------------------*/\r
 \r
 BaseType_t xPortStartScheduler( void )\r
@@ -247,14 +251,26 @@ extern void xPortStartFirstTask( void );
                started. */\r
                configASSERT( ( xISRStackTop & portBYTE_ALIGNMENT_MASK ) == 0 );\r
        }\r
-       #endif\r
+       #endif /* configASSERT_DEFINED */\r
 \r
+       /* If there is a CLINT then it is ok to use the default implementation\r
+       in this file, otherwise vPortSetupTimerInterrupt() must be implemented to\r
+       configure whichever clock is to be used to generate the tick interrupt. */\r
        vPortSetupTimerInterrupt();\r
 \r
-       /* Enable mtime and external interrupts.  1<<7 for timer interrupt, 1<<11\r
-       for external interrupt.  _RB_ What happens here when mtime is not present as\r
-       with pulpino? */\r
-       __asm volatile( "csrs mie, %0" :: "r"(0x880) );\r
+       #if( configCLINT_BASE_ADDRESS != 0 )\r
+       {\r
+               /* Enable mtime and external interrupts.  1<<7 for timer interrupt, 1<<11\r
+               for external interrupt.  _RB_ What happens here when mtime is not present as\r
+               with pulpino? */\r
+               __asm volatile( "csrs mie, %0" :: "r"(0x880) );\r
+       }\r
+       #else\r
+       {\r
+               /* Enable external interrupts. */\r
+               __asm volatile( "csrs mie, %0" :: "r"(0x800) );\r
+       }\r
+       #endif /* configCLINT_BASE_ADDRESS */\r
 \r
        xPortStartFirstTask();\r
 \r

diff --git a/FreeRTOS/Source/portable/GCC/RISC-V-RV32/portASM.S b/FreeRTOS/Source/portable/GCC/RISC-V-RV32/portASM.S
index 6b93f375fcb58e7d22237ebd8a6091739c02e343..eddad68c64882bc9d288babc0903b7a58cdf2f8c 100644 (file)
--- a/FreeRTOS/Source/portable/GCC/RISC-V-RV32/portASM.S
+++ b/FreeRTOS/Source/portable/GCC/RISC-V-RV32/portASM.S
@@ -6,9 +6,7 @@
  * this software and associated documentation files (the "Software"), to deal in\r
  * the Software without restriction, including without limitation the rights to\r
  * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
- * the Software, and t\r
-\r
- o permit persons to whom the Software is furnished to do so,\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
  * subject to the following conditions:\r
  *\r
  * The above copyright notice and this permission notice shall be included in all\r
@@ -59,25 +57,50 @@
  */\r
 #include "freertos_risc_v_port_specific_extensions.h"\r
 \r
+/* Check the freertos_risc_v_port_specific_extensions.h and/or command line\r
+definitions. */\r
+#ifndef portasmHAS_CLINT\r
+       #error freertos_risc_v_port_specific_extensions.h must define portasmHAS_CLINT to either 1 (CLINT present) or 0 (clint not present).\r
+#endif\r
+\r
+#ifndef portasmHANDLE_INTERRUPT\r
+       #error portasmHANDLE_INTERRUPT must be defined to the function to be called to handle external/peripheral interrupts.  portASM_HANDLE_INTERRUPT can be defined on the assmbler command line or in the appropriate freertos_risc_v_port_specific_extensions.h header file.\r
+#endif\r
+\r
+#ifndef portasmSAVE_ADDITIONAL_REGISTERS\r
+       /* portasmSAVE_ADDITIONAL_REGISTERS is not defined so assume no additional\r
+       registers need to be saved. */\r
+       #define portasmSAVE_ADDITIONAL_REGISTERS\r
+#endif\r
+\r
+#ifndef portasmRESTORE_ADDITIONAL_REGISTERS\r
+       /* portasmRESTORE_ADDITIONAL_REGISTERS is not defined so assume no\r
+       additional registers need to be restored. */\r
+       #define portasmRESTORE_ADDITIONAL_REGISTERS\r
+#endif\r
+\r
 #if __riscv_xlen == 64\r
        #error Not implemented yet - change lw to ld, and sw to sd.\r
-       #define WORD_SIZE 8\r
+       #define portWORD_SIZE 8\r
 #elif __riscv_xlen == 32\r
-       #define WORD_SIZE 4\r
+       #define portWORD_SIZE 4\r
 #else\r
-       #error Assembler has not defined __riscv_xlen\r
+       #error Assembler did not define __riscv_xlen\r
 #endif\r
 \r
-#define CONTEXT_SIZE ( 30 * WORD_SIZE )\r
+/* Only the standard core registers are stored by default.  Any additional\r
+registers must be saved by the portasmSAVE_ADDITIONAL_REGISTERS and\r
+portasmRESTORE_ADDITIONAL_REGISTERS macros - which can be defined in a chip\r
+specific version of freertos_risc_v_port_specific_extensions.h.  See the notes\r
+at the top of this file. */\r
+#define portCONTEXT_SIZE ( 30 * portWORD_SIZE )\r
 \r
 .global xPortStartFirstTask\r
-.global vPortTrapHandler\r
+.global vFreeRTOSPortTrapHandler\r
 .extern pxCurrentTCB\r
 .extern ulPortTrapHandler\r
 .extern vTaskSwitchContext\r
 .extern Timer_IRQHandler\r
-\r
-\r
 .extern pullMachineTimerCompareRegister\r
 .extern pullNextTime\r
 .extern ulTimerIncrementsForOneTick\r
@@ -86,92 +109,99 @@
 \r
 /*-----------------------------------------------------------*/\r
 \r
-.align 8\r
-vPortTrapHandler:\r
-       addi sp, sp, -CONTEXT_SIZE\r
-       sw x1, 1 * WORD_SIZE( sp )\r
-       sw x5, 2 * WORD_SIZE( sp )\r
-       sw x6, 3 * WORD_SIZE( sp )\r
-       sw x7, 4 * WORD_SIZE( sp )\r
-       sw x8, 5 * WORD_SIZE( sp )\r
-       sw x9, 6 * WORD_SIZE( sp )\r
-       sw x10, 7 * WORD_SIZE( sp )\r
-       sw x11, 8 * WORD_SIZE( sp )\r
-       sw x12, 9 * WORD_SIZE( sp )\r
-       sw x13, 10 * WORD_SIZE( sp )\r
-       sw x14, 11 * WORD_SIZE( sp )\r
-       sw x15, 12 * WORD_SIZE( sp )\r
-       sw x16, 13 * WORD_SIZE( sp )\r
-       sw x17, 14 * WORD_SIZE( sp )\r
-       sw x18, 15 * WORD_SIZE( sp )\r
-       sw x19, 16 * WORD_SIZE( sp )\r
-       sw x20, 17 * WORD_SIZE( sp )\r
-       sw x21, 18 * WORD_SIZE( sp )\r
-       sw x22, 19 * WORD_SIZE( sp )\r
-       sw x23, 20 * WORD_SIZE( sp )\r
-       sw x24, 21 * WORD_SIZE( sp )\r
-       sw x25, 22 * WORD_SIZE( sp )\r
-       sw x26, 23 * WORD_SIZE( sp )\r
-       sw x27, 24 * WORD_SIZE( sp )\r
-       sw x28, 25 * WORD_SIZE( sp )\r
-       sw x29, 26 * WORD_SIZE( sp )\r
-       sw x30, 27 * WORD_SIZE( sp )\r
-       sw x31, 28 * WORD_SIZE( sp )\r
-\r
-       portSAVE_ADDITIONAL_REGISTERS                   /* Defined in freertos_risc_v_port_specific_extensions.h to save any registers unique to the RISC-V implementation. */\r
-\r
-       csrr t0, mstatus                                                /* Required for MPIE bit. */\r
-       sw t0, 29 * WORD_SIZE( sp )\r
-\r
-       lw  t0, pxCurrentTCB                                    /* Load pxCurrentTCB. */\r
-       sw  sp, 0( t0 )                                                 /* Write sp to first TCB member. */\r
+.align 16\r
+vFreeRTOSPortTrapHandler:\r
+       addi sp, sp, -portCONTEXT_SIZE\r
+       sw x1, 1 * portWORD_SIZE( sp )\r
+       sw x5, 2 * portWORD_SIZE( sp )\r
+       sw x6, 3 * portWORD_SIZE( sp )\r
+       sw x7, 4 * portWORD_SIZE( sp )\r
+       sw x8, 5 * portWORD_SIZE( sp )\r
+       sw x9, 6 * portWORD_SIZE( sp )\r
+       sw x10, 7 * portWORD_SIZE( sp )\r
+       sw x11, 8 * portWORD_SIZE( sp )\r
+       sw x12, 9 * portWORD_SIZE( sp )\r
+       sw x13, 10 * portWORD_SIZE( sp )\r
+       sw x14, 11 * portWORD_SIZE( sp )\r
+       sw x15, 12 * portWORD_SIZE( sp )\r
+       sw x16, 13 * portWORD_SIZE( sp )\r
+       sw x17, 14 * portWORD_SIZE( sp )\r
+       sw x18, 15 * portWORD_SIZE( sp )\r
+       sw x19, 16 * portWORD_SIZE( sp )\r
+       sw x20, 17 * portWORD_SIZE( sp )\r
+       sw x21, 18 * portWORD_SIZE( sp )\r
+       sw x22, 19 * portWORD_SIZE( sp )\r
+       sw x23, 20 * portWORD_SIZE( sp )\r
+       sw x24, 21 * portWORD_SIZE( sp )\r
+       sw x25, 22 * portWORD_SIZE( sp )\r
+       sw x26, 23 * portWORD_SIZE( sp )\r
+       sw x27, 24 * portWORD_SIZE( sp )\r
+       sw x28, 25 * portWORD_SIZE( sp )\r
+       sw x29, 26 * portWORD_SIZE( sp )\r
+       sw x30, 27 * portWORD_SIZE( sp )\r
+       sw x31, 28 * portWORD_SIZE( sp )\r
+\r
+       portasmSAVE_ADDITIONAL_REGISTERS        /* Defined in freertos_risc_v_port_specific_extensions.h to save any registers unique to the RISC-V implementation. */\r
+\r
+       csrr t0, mstatus                                        /* Required for MPIE bit. */\r
+       sw t0, 29 * portWORD_SIZE( sp )\r
+\r
+       lw  t0, pxCurrentTCB                            /* Load pxCurrentTCB. */\r
+       sw  sp, 0( t0 )                                         /* Write sp to first TCB member. */\r
 \r
        csrr a0, mcause\r
        csrr a1, mepc\r
 \r
 test_if_asynchronous:\r
-       srli a2, a0, 0x1f                                               /* MSB of mcause is 1 if handing an asynchronous interrupt - shift to LSB to clear other bits. */\r
-       beq a2, x0, handle_synchronous                  /* Branch past interrupt handing if not asynchronous. */\r
-       sw a1, 0( sp )                                                  /* Asynch so save unmodified exception return address. */\r
+       srli a2, a0, 0x1f                                       /* MSB of mcause is 1 if handing an asynchronous interrupt - shift to LSB to clear other bits. */\r
+       beq a2, x0, handle_synchronous          /* Branch past interrupt handing if not asynchronous. */\r
+       sw a1, 0( sp )                                          /* Asynch so save unmodified exception return address. */\r
 \r
 handle_asynchronous:\r
-test_if_mtimer:\r
-       lui t0, 0x80000\r
-       addi t1, t0, 7                                                  /* 0x80000007 == machine timer interrupt. */\r
-       bne a0, t1, test_if_external_interrupt\r
-\r
-       lw t0, pullMachineTimerCompareRegister  /* Load address of compare register into t0. */\r
-       lw t1, pullNextTime                                             /* Load the address of ullNextTime into t1. */\r
-       lw t2, 0(t1)                                                    /* Load the low word of ullNextTime into t2. */\r
-       lw t3, 4(t1)                                                    /* Load the high word of ullNextTime into t3. */\r
-       sw t2, 0(t0)                                                    /* Store low word of ullNextTime into compare register. */\r
-       sw t3, 4(t0)                                                    /* Store high word of ullNextTime into compare register. */\r
-       lw t0, ulTimerIncrementsForOneTick              /* Load the value of ullTimerIncrementForOneTick into t0 (could this be optimized by storing in an array next to pullNextTime?). */\r
-       add t4, t0, t2                                                  /* Add the low word of ullNextTime to the timer increments for one tick (assumes timer increment for one tick fits in 32-bits. */\r
-       sltu t5, t4, t2                                                 /* See if the sum of low words overflowed (what about the zero case?). */\r
-       add t6, t3, t5                                                  /* Add overflow to high word of ullNextTime. */\r
-       sw t4, 0(t1)                                                    /* Store new low word of ullNextTime. */\r
-       sw t6, 4(t1)                                                    /* Store new high word of ullNextTime. */\r
-       lw sp, xISRStackTop                                             /* Switch to ISR stack before function call. */\r
-       jal xTaskIncrementTick\r
-       beqz a0, processed_source                               /* Don't switch context if incrementing tick didn't unblock a task. */\r
-       jal vTaskSwitchContext\r
-       j processed_source\r
 \r
-test_if_external_interrupt:\r
-       addi t1, t1, 4                                                  /* 0x80000007 + 4 = 0x8000000b == Machine external interrupt. */\r
-       bne a0, t1, as_yet_unhandled                    /* Something as yet unhandled. */\r
-       jal vPortHandleInterrupt\r
+#if( portasmHAS_CLINT != 0 )\r
+\r
+       test_if_mtimer:                                                 /* If there is a CLINT then the mtimer is used to generate the tick interrupt. */\r
+               lui t0, 0x80000\r
+               addi t1, t0, 7                                          /* 0x80000007 == machine timer interrupt. */\r
+               bne a0, t1, test_if_external_interrupt\r
+\r
+               lw t0, pullMachineTimerCompareRegister  /* Load address of compare register into t0. */\r
+               lw t1, pullNextTime                                     /* Load the address of ullNextTime into t1. */\r
+               lw t2, 0(t1)                                            /* Load the low word of ullNextTime into t2. */\r
+               lw t3, 4(t1)                                            /* Load the high word of ullNextTime into t3. */\r
+               sw t2, 0(t0)                                            /* Store low word of ullNextTime into compare register. */\r
+               sw t3, 4(t0)                                            /* Store high word of ullNextTime into compare register. */\r
+               lw t0, ulTimerIncrementsForOneTick      /* Load the value of ullTimerIncrementForOneTick into t0 (could this be optimized by storing in an array next to pullNextTime?). */\r
+               add t4, t0, t2                                          /* Add the low word of ullNextTime to the timer increments for one tick (assumes timer increment for one tick fits in 32-bits. */\r
+               sltu t5, t4, t2                                         /* See if the sum of low words overflowed (what about the zero case?). */\r
+               add t6, t3, t5                                          /* Add overflow to high word of ullNextTime. */\r
+               sw t4, 0(t1)                                            /* Store new low word of ullNextTime. */\r
+               sw t6, 4(t1)                                            /* Store new high word of ullNextTime. */\r
+               lw sp, xISRStackTop                                     /* Switch to ISR stack before function call. */\r
+               jal xTaskIncrementTick\r
+               beqz a0, processed_source                       /* Don't switch context if incrementing tick didn't unblock a task. */\r
+               jal vTaskSwitchContext\r
+               j processed_source\r
+\r
+       test_if_external_interrupt:                     /* If there is a CLINT and the mtimer interrupt is not pending then check to see if an external interrupt is pending. */\r
+               addi t1, t1, 4                                  /* 0x80000007 + 4 = 0x8000000b == Machine external interrupt. */\r
+               bne a0, t1, as_yet_unhandled    /* Something as yet unhandled. */\r
+\r
+#endif /* portasmHAS_CLINT */\r
+\r
+       lw sp, xISRStackTop                                     /* Switch to ISR stack before function call. */\r
+       jal portasmHANDLE_INTERRUPT                     /* Jump to the interrupt handler if there is no CLINT or if there is a CLINT and it has been determined that an external interrupt is pending. */\r
        j processed_source\r
 \r
 handle_synchronous:\r
-       addi a1, a1, 4                                                  /* Synchronous so updated exception return address to the instruction after the instruction that generated the exeption. */\r
-       sw a1, 0( sp )                                                  /* Save updated exception return address. */\r
+       addi a1, a1, 4                                          /* Synchronous so updated exception return address to the instruction after the instruction that generated the exeption. */\r
+       sw a1, 0( sp )                                          /* Save updated exception return address. */\r
 \r
 test_if_environment_call:\r
-       li t0, 11                                                               /* 11 == environment call. */\r
-       bne a0, t0, is_exception                                /* Not an M environment call, so some other exception. */\r
-       lw sp, xISRStackTop                                             /* Switch to ISR stack before function call. */\r
+       li t0, 11                                                       /* 11 == environment call. */\r
+       bne a0, t0, is_exception                        /* Not an M environment call, so some other exception. */\r
+       lw sp, xISRStackTop                                     /* Switch to ISR stack before function call. */\r
        jal vTaskSwitchContext\r
        j processed_source\r
 \r
@@ -184,91 +214,96 @@ as_yet_unhandled:
        j as_yet_unhandled\r
 \r
 processed_source:\r
-       lw  sp, pxCurrentTCB                                    /* Load pxCurrentTCB. */\r
-       lw  sp, 0( sp )                                                 /* Read sp from first TCB member. */\r
+       lw  sp, pxCurrentTCB                            /* Load pxCurrentTCB. */\r
+       lw  sp, 0( sp )                                         /* Read sp from first TCB member. */\r
 \r
        /* Load mret with the address of the next task. */\r
        lw t0, 0( sp )\r
        csrw mepc, t0\r
 \r
        /* Load mstatus with the interrupt enable bits used by the task. */\r
-       lw  t0, 29 * WORD_SIZE( sp )\r
-       csrw mstatus, t0                                                /* Required for MPIE bit. */\r
-\r
-       portRESTORE_ADDITIONAL_REGISTERS                /* Defined in freertos_risc_v_port_specific_extensions.h to restore any registers unique to the RISC-V implementation. */\r
-\r
-       lw  x1, 1 * WORD_SIZE( sp )\r
-       lw  x5, 2 * WORD_SIZE( sp )                             /* t0 */\r
-       lw  x6, 3 * WORD_SIZE( sp )                             /* t1 */\r
-       lw  x7, 4 * WORD_SIZE( sp )                             /* t2 */\r
-       lw  x8, 5 * WORD_SIZE( sp )                             /* s0/fp */\r
-       lw  x9, 6 * WORD_SIZE( sp )                             /* s1 */\r
-       lw  x10, 7 * WORD_SIZE( sp )                    /* a0 */\r
-       lw  x11, 8 * WORD_SIZE( sp )                    /* a1 */\r
-       lw  x12, 9 * WORD_SIZE( sp )                    /* a2 */\r
-       lw  x13, 10 * WORD_SIZE( sp )                   /* a3 */\r
-       lw  x14, 11 * WORD_SIZE( sp )                   /* a4 */\r
-       lw  x15, 12 * WORD_SIZE( sp )                   /* a5 */\r
-       lw  x16, 13 * WORD_SIZE( sp )                   /* a6 */\r
-       lw  x17, 14 * WORD_SIZE( sp )                   /* a7 */\r
-       lw  x18, 15 * WORD_SIZE( sp )                   /* s2 */\r
-       lw  x19, 16 * WORD_SIZE( sp )                   /* s3 */\r
-       lw  x20, 17 * WORD_SIZE( sp )                   /* s4 */\r
-       lw  x21, 18 * WORD_SIZE( sp )                   /* s5 */\r
-       lw  x22, 19 * WORD_SIZE( sp )                   /* s6 */\r
-       lw  x23, 20 * WORD_SIZE( sp )                   /* s7 */\r
-       lw  x24, 21 * WORD_SIZE( sp )                   /* s8 */\r
-       lw  x25, 22 * WORD_SIZE( sp )                   /* s9 */\r
-       lw  x26, 23 * WORD_SIZE( sp )                   /* s10 */\r
-       lw  x27, 24 * WORD_SIZE( sp )                   /* s11 */\r
-       lw  x28, 25 * WORD_SIZE( sp )                   /* t3 */\r
-       lw  x29, 26 * WORD_SIZE( sp )                   /* t4 */\r
-       lw  x30, 27 * WORD_SIZE( sp )                   /* t5 */\r
-       lw  x31, 28 * WORD_SIZE( sp )                   /* t6 */\r
-       addi    sp, sp, CONTEXT_SIZE\r
+       lw  t0, 29 * portWORD_SIZE( sp )\r
+       csrw mstatus, t0                                        /* Required for MPIE bit. */\r
+\r
+       portasmRESTORE_ADDITIONAL_REGISTERS     /* Defined in freertos_risc_v_port_specific_extensions.h to restore any registers unique to the RISC-V implementation. */\r
+\r
+       lw  x1, 1 * portWORD_SIZE( sp )\r
+       lw  x5, 2 * portWORD_SIZE( sp )         /* t0 */\r
+       lw  x6, 3 * portWORD_SIZE( sp )         /* t1 */\r
+       lw  x7, 4 * portWORD_SIZE( sp )         /* t2 */\r
+       lw  x8, 5 * portWORD_SIZE( sp )         /* s0/fp */\r
+       lw  x9, 6 * portWORD_SIZE( sp )         /* s1 */\r
+       lw  x10, 7 * portWORD_SIZE( sp )        /* a0 */\r
+       lw  x11, 8 * portWORD_SIZE( sp )        /* a1 */\r
+       lw  x12, 9 * portWORD_SIZE( sp )        /* a2 */\r
+       lw  x13, 10 * portWORD_SIZE( sp )       /* a3 */\r
+       lw  x14, 11 * portWORD_SIZE( sp )       /* a4 */\r
+       lw  x15, 12 * portWORD_SIZE( sp )       /* a5 */\r
+       lw  x16, 13 * portWORD_SIZE( sp )       /* a6 */\r
+       lw  x17, 14 * portWORD_SIZE( sp )       /* a7 */\r
+       lw  x18, 15 * portWORD_SIZE( sp )       /* s2 */\r
+       lw  x19, 16 * portWORD_SIZE( sp )       /* s3 */\r
+       lw  x20, 17 * portWORD_SIZE( sp )       /* s4 */\r
+       lw  x21, 18 * portWORD_SIZE( sp )       /* s5 */\r
+       lw  x22, 19 * portWORD_SIZE( sp )       /* s6 */\r
+       lw  x23, 20 * portWORD_SIZE( sp )       /* s7 */\r
+       lw  x24, 21 * portWORD_SIZE( sp )       /* s8 */\r
+       lw  x25, 22 * portWORD_SIZE( sp )       /* s9 */\r
+       lw  x26, 23 * portWORD_SIZE( sp )       /* s10 */\r
+       lw  x27, 24 * portWORD_SIZE( sp )       /* s11 */\r
+       lw  x28, 25 * portWORD_SIZE( sp )       /* t3 */\r
+       lw  x29, 26 * portWORD_SIZE( sp )       /* t4 */\r
+       lw  x30, 27 * portWORD_SIZE( sp )       /* t5 */\r
+       lw  x31, 28 * portWORD_SIZE( sp )       /* t6 */\r
+       addi    sp, sp, portCONTEXT_SIZE\r
 \r
        mret\r
 /*-----------------------------------------------------------*/\r
 \r
-.align 8\r
+.align 16\r
 xPortStartFirstTask:\r
 \r
-       la t0, vPortTrapHandler\r
+#if( portasmHAS_CLINT != 0 )\r
+       /* If there is a clint then interrupts can branch directly to the FreeRTOS\r
+       trap handler.  Otherwise the interrupt controller will need to be configured\r
+       outside of this file. */\r
+       la t0, vFreeRTOSPortTrapHandler\r
        csrw mtvec, t0\r
+#endif /* portasmHAS_CLILNT */\r
 \r
        lw  sp, pxCurrentTCB                    /* Load pxCurrentTCB. */\r
        lw  sp, 0( sp )                                 /* Read sp from first TCB member. */\r
 \r
        lw  x1, 0( sp ) /* Note for starting the scheduler the exception return address is used as the function return address. */\r
-       lw  x5, 2 * WORD_SIZE( sp )             /* t0 */\r
-       lw  x6, 3 * WORD_SIZE( sp )             /* t1 */\r
-       lw  x7, 4 * WORD_SIZE( sp )             /* t2 */\r
-       lw  x8, 5 * WORD_SIZE( sp )             /* s0/fp */\r
-       lw  x9, 6 * WORD_SIZE( sp )             /* s1 */\r
-       lw  x10, 7 * WORD_SIZE( sp )    /* a0 */\r
-       lw  x11, 8 * WORD_SIZE( sp )    /* a1 */\r
-       lw  x12, 9 * WORD_SIZE( sp )    /* a2 */\r
-       lw  x13, 10 * WORD_SIZE( sp )   /* a3 */\r
-       lw  x14, 11 * WORD_SIZE( sp )   /* a4 */\r
-       lw  x15, 12 * WORD_SIZE( sp )   /* a5 */\r
-       lw  x16, 13 * WORD_SIZE( sp )   /* a6 */\r
-       lw  x17, 14 * WORD_SIZE( sp )   /* a7 */\r
-       lw  x18, 15 * WORD_SIZE( sp )   /* s2 */\r
-       lw  x19, 16 * WORD_SIZE( sp )   /* s3 */\r
-       lw  x20, 17 * WORD_SIZE( sp )   /* s4 */\r
-       lw  x21, 18 * WORD_SIZE( sp )   /* s5 */\r
-       lw  x22, 19 * WORD_SIZE( sp )   /* s6 */\r
-       lw  x23, 20 * WORD_SIZE( sp )   /* s7 */\r
-       lw  x24, 21 * WORD_SIZE( sp )   /* s8 */\r
-       lw  x25, 22 * WORD_SIZE( sp )   /* s9 */\r
-       lw  x26, 23 * WORD_SIZE( sp )   /* s10 */\r
-       lw  x27, 24 * WORD_SIZE( sp )   /* s11 */\r
-       lw  x28, 25 * WORD_SIZE( sp )   /* t3 */\r
-       lw  x29, 26 * WORD_SIZE( sp )   /* t4 */\r
-       lw  x30, 27 * WORD_SIZE( sp )   /* t5 */\r
-       lw  x31, 28 * WORD_SIZE( sp )   /* t6 */\r
-       addi    sp, sp, CONTEXT_SIZE\r
-       csrs    mstatus, 8                              /* Enable machine interrupts. */\r
+       lw  x5, 2 * portWORD_SIZE( sp )         /* t0 */\r
+       lw  x6, 3 * portWORD_SIZE( sp )         /* t1 */\r
+       lw  x7, 4 * portWORD_SIZE( sp )         /* t2 */\r
+       lw  x8, 5 * portWORD_SIZE( sp )         /* s0/fp */\r
+       lw  x9, 6 * portWORD_SIZE( sp )         /* s1 */\r
+       lw  x10, 7 * portWORD_SIZE( sp )        /* a0 */\r
+       lw  x11, 8 * portWORD_SIZE( sp )        /* a1 */\r
+       lw  x12, 9 * portWORD_SIZE( sp )        /* a2 */\r
+       lw  x13, 10 * portWORD_SIZE( sp )       /* a3 */\r
+       lw  x14, 11 * portWORD_SIZE( sp )       /* a4 */\r
+       lw  x15, 12 * portWORD_SIZE( sp )       /* a5 */\r
+       lw  x16, 13 * portWORD_SIZE( sp )       /* a6 */\r
+       lw  x17, 14 * portWORD_SIZE( sp )       /* a7 */\r
+       lw  x18, 15 * portWORD_SIZE( sp )       /* s2 */\r
+       lw  x19, 16 * portWORD_SIZE( sp )       /* s3 */\r
+       lw  x20, 17 * portWORD_SIZE( sp )       /* s4 */\r
+       lw  x21, 18 * portWORD_SIZE( sp )       /* s5 */\r
+       lw  x22, 19 * portWORD_SIZE( sp )       /* s6 */\r
+       lw  x23, 20 * portWORD_SIZE( sp )       /* s7 */\r
+       lw  x24, 21 * portWORD_SIZE( sp )       /* s8 */\r
+       lw  x25, 22 * portWORD_SIZE( sp )       /* s9 */\r
+       lw  x26, 23 * portWORD_SIZE( sp )       /* s10 */\r
+       lw  x27, 24 * portWORD_SIZE( sp )       /* s11 */\r
+       lw  x28, 25 * portWORD_SIZE( sp )       /* t3 */\r
+       lw  x29, 26 * portWORD_SIZE( sp )       /* t4 */\r
+       lw  x30, 27 * portWORD_SIZE( sp )       /* t5 */\r
+       lw  x31, 28 * portWORD_SIZE( sp )       /* t6 */\r
+       addi    sp, sp, portCONTEXT_SIZE\r
+       csrs    mstatus, 8                                      /* Enable machine interrupts. */\r
        ret\r
 \r
 /*-----------------------------------------------------------*/\r