#define portexR12_STACK_OFFSET 13\r
#define portexR15_STACK_OFFSET 16\r
#define portexR18_STACK_OFFSET 18\r
+#define portexMSR_STACK_OFFSET 19\r
#define portexR19_STACK_OFFSET -1\r
\r
#define portexESR_DS_MASK 0x00001000UL\r
\r
+#define portexASM_HANDLER_STACK_FRAME_SIZE 84UL\r
\r
/* Exclude the entire file if the MicroBlaze is not configured to handle\r
exceptions, or the application defined configuration item \r
#if ( MICROBLAZE_EXCEPTIONS_ENABLED == 1 ) && ( configINSTALL_EXCEPTION_HANDLERS == 1 )\r
\r
/* These are global volatiles to allow their inspection by a debugger. */\r
-unsigned long *pulStackPointerOnFunctionEntry = NULL;\r
+unsigned long *pulStackPointerOnFunctionEntry = NULL, ulBTROnFunctionEntry = 0UL;\r
\r
static xPortRegisterDump xRegisterDump;\r
\r
void vPortExceptionHandler( void *pvExceptionID );\r
extern void vPortExceptionHandlerEntry( void *pvExceptionID );\r
\r
+/*-----------------------------------------------------------*/\r
+extern void vApplicationExceptionRegisterDump( xPortRegisterDump *xRegisterDump ) __attribute__((weak));\r
+void vApplicationExceptionRegisterDump( xPortRegisterDump *xRegisterDump )\r
+{\r
+ for( ;; )\r
+ {\r
+ portNOP();\r
+ }\r
+}\r
/*-----------------------------------------------------------*/\r
\r
void vPortExceptionHandler( void *pvExceptionID )\r
xRegisterDump.ulR10 = pulStackPointerOnFunctionEntry[ portexR10_STACK_OFFSET ];\r
xRegisterDump.ulR11 = pulStackPointerOnFunctionEntry[ portexR11_STACK_OFFSET ];\r
xRegisterDump.ulR12 = pulStackPointerOnFunctionEntry[ portexR12_STACK_OFFSET ];\r
+ xRegisterDump.ulR15_return_address_from_subroutine = pulStackPointerOnFunctionEntry[ portexR15_STACK_OFFSET ];\r
+ xRegisterDump.ulR18 = pulStackPointerOnFunctionEntry[ portexR18_STACK_OFFSET ];\r
xRegisterDump.ulR19 = pulStackPointerOnFunctionEntry[ portexR19_STACK_OFFSET ];\r
\r
/* Obtain the value of all other registers. */\r
- //xRegisterDump.ulR1 =\r
xRegisterDump.ulR2_small_data_area = mfgpr( R2 );\r
xRegisterDump.ulR13_read_write_small_data_area = mfgpr( R13 );\r
xRegisterDump.ulR14_return_address_from_interrupt = mfgpr( R14 );\r
- xRegisterDump.ulR15_return_address_from_subroutine = mfgpr( R15 );\r
xRegisterDump.ulR16_return_address_from_trap = mfgpr( R16 );\r
xRegisterDump.ulR17_return_address_from_some_exceptions = mfgpr( R17 );\r
xRegisterDump.ulR18 = mfgpr( R18 );\r
xRegisterDump.ulR29 = mfgpr( R29 );\r
xRegisterDump.ulR30 = mfgpr( R30 );\r
xRegisterDump.ulR31 = mfgpr( R31 );\r
-\r
+ xRegisterDump.ulR1_SP = ( ( unsigned long ) pulStackPointerOnFunctionEntry ) + portexASM_HANDLER_STACK_FRAME_SIZE;\r
+ xRegisterDump.ulBTR = ulBTROnFunctionEntry;\r
+ xRegisterDump.ulMSR = pulStackPointerOnFunctionEntry[ portexMSR_STACK_OFFSET ];\r
+ xRegisterDump.ulEAR = mfear();\r
xRegisterDump.ulESR = mfesr();\r
+ xRegisterDump.ulEDR = mfedr();\r
+\r
+\r
+#ifdef THIS_IS_PROBABLY_INCORRECT\r
if( ( xRegisterDump.ulESR * portexESR_DS_MASK ) != 0UL )\r
{\r
xRegisterDump.ulPC = mfbtr();\r
{\r
xRegisterDump.ulPC = xRegisterDump.ulR17_return_address_from_some_exceptions - 4;\r
}\r
+#else\r
+ xRegisterDump.ulPC = xRegisterDump.ulR17_return_address_from_some_exceptions - 4;\r
+#endif\r
\r
- // xRegisterDump.ulSP =;\r
\r
- // PC changes\r
- // MSR changes\r
- // BTR changes\r
+ #if XPAR_MICROBLAZE_0_USE_FPU == 1\r
+ {\r
+ xRegisterDump.ulFSR = mffsr();\r
+ }\r
+ #else\r
+ {\r
+ xRegisterDump.ulFSR = 0UL;\r
+ }\r
+ #endif\r
\r
switch( ( unsigned long ) pvExceptionID )\r
{\r
xRegisterDump.pcExceptionCause = ( signed char * const ) "XEXC_ID_DIV_BY_ZERO";\r
break;\r
\r
- case XEXC_ID_FPU :\r
- /*_RB_ More decoding required here and in other exceptions. */\r
- xRegisterDump.pcExceptionCause = ( signed char * const ) "XEXC_ID_FPU";\r
- break;\r
-\r
case XEXC_ID_STACK_VIOLATION :\r
xRegisterDump.pcExceptionCause = ( signed char * const ) "XEXC_ID_STACK_VIOLATION or XEXC_ID_MMU";\r
break;\r
+\r
+ #if XPAR_MICROBLAZE_0_USE_FPU == 1\r
+\r
+ case XEXC_ID_FPU :\r
+ /*_RB_ More decoding required here and in other exceptions. */\r
+ xRegisterDump.pcExceptionCause = ( signed char * const ) "XEXC_ID_FPU see ulFSR value";\r
+ break;\r
+\r
+ #endif /* XPAR_MICROBLAZE_0_USE_FPU */\r
}\r
\r
+ vApplicationExceptionRegisterDump( &xRegisterDump );\r
+\r
/* Must not attempt to leave this function! */\r
for( ;; )\r
{\r
\r
void vPortExceptionsInstallHandlers( void )\r
{\r
- #if XPAR_MICROBLAZE_0_UNALIGNED_EXCEPTIONS == 1\r
- microblaze_register_exception_handler( XEXC_ID_UNALIGNED_ACCESS, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_UNALIGNED_ACCESS );\r
- #endif /* XPAR_MICROBLAZE_0_UNALIGNED_EXCEPTIONS*/\r
+static unsigned long ulHandlersAlreadyInstalled = pdFALSE;\r
+\r
+ if( ulHandlersAlreadyInstalled == pdFALSE )\r
+ {\r
+ ulHandlersAlreadyInstalled = pdTRUE;\r
\r
- #if XPAR_MICROBLAZE_0_ILL_OPCODE_EXCEPTION == 1\r
- microblaze_register_exception_handler( XEXC_ID_ILLEGAL_OPCODE, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_ILLEGAL_OPCODE );\r
- #endif /* XPAR_MICROBLAZE_0_ILL_OPCODE_EXCEPTION*/\r
+ #if XPAR_MICROBLAZE_0_UNALIGNED_EXCEPTIONS == 1\r
+ microblaze_register_exception_handler( XEXC_ID_UNALIGNED_ACCESS, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_UNALIGNED_ACCESS );\r
+ #endif /* XPAR_MICROBLAZE_0_UNALIGNED_EXCEPTIONS*/\r
\r
- #if XPAR_MICROBLAZE_0_M_AXI_I_BUS_EXCEPTION == 1\r
- microblaze_register_exception_handler( XEXC_ID_M_AXI_I_EXCEPTION, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_M_AXI_I_EXCEPTION );\r
- #endif /* XPAR_MICROBLAZE_0_M_AXI_I_BUS_EXCEPTION*/\r
+ #if XPAR_MICROBLAZE_0_ILL_OPCODE_EXCEPTION == 1\r
+ microblaze_register_exception_handler( XEXC_ID_ILLEGAL_OPCODE, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_ILLEGAL_OPCODE );\r
+ #endif /* XPAR_MICROBLAZE_0_ILL_OPCODE_EXCEPTION*/\r
\r
- #if XPAR_MICROBLAZE_0_M_AXI_D_BUS_EXCEPTION == 1\r
- microblaze_register_exception_handler( XEXC_ID_M_AXI_D_EXCEPTION, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_M_AXI_D_EXCEPTION );\r
- #endif /* XPAR_MICROBLAZE_0_M_AXI_D_BUS_EXCEPTION*/\r
+ #if XPAR_MICROBLAZE_0_M_AXI_I_BUS_EXCEPTION == 1\r
+ microblaze_register_exception_handler( XEXC_ID_M_AXI_I_EXCEPTION, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_M_AXI_I_EXCEPTION );\r
+ #endif /* XPAR_MICROBLAZE_0_M_AXI_I_BUS_EXCEPTION*/\r
\r
- #if XPAR_MICROBLAZE_0_IPLB_BUS_EXCEPTION == 1\r
- microblaze_register_exception_handler( XEXC_ID_IPLB_EXCEPTION, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_IPLB_EXCEPTION );\r
- #endif /* XPAR_MICROBLAZE_0_IPLB_BUS_EXCEPTION*/\r
+ #if XPAR_MICROBLAZE_0_M_AXI_D_BUS_EXCEPTION == 1\r
+ microblaze_register_exception_handler( XEXC_ID_M_AXI_D_EXCEPTION, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_M_AXI_D_EXCEPTION );\r
+ #endif /* XPAR_MICROBLAZE_0_M_AXI_D_BUS_EXCEPTION*/\r
\r
- #if XPAR_MICROBLAZE_0_DPLB_BUS_EXCEPTION == 1\r
- microblaze_register_exception_handler( XEXC_ID_DPLB_EXCEPTION, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_DPLB_EXCEPTION );\r
- #endif /* XPAR_MICROBLAZE_0_DPLB_BUS_EXCEPTION*/\r
+ #if XPAR_MICROBLAZE_0_IPLB_BUS_EXCEPTION == 1\r
+ microblaze_register_exception_handler( XEXC_ID_IPLB_EXCEPTION, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_IPLB_EXCEPTION );\r
+ #endif /* XPAR_MICROBLAZE_0_IPLB_BUS_EXCEPTION*/\r
\r
- #if XPAR_MICROBLAZE_0_DIV_ZERO_EXCEPTION == 1\r
- microblaze_register_exception_handler( XEXC_ID_DIV_BY_ZERO, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_DIV_BY_ZERO );\r
- #endif /* XPAR_MICROBLAZE_0_DIV_ZERO_EXCEPTION*/\r
+ #if XPAR_MICROBLAZE_0_DPLB_BUS_EXCEPTION == 1\r
+ microblaze_register_exception_handler( XEXC_ID_DPLB_EXCEPTION, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_DPLB_EXCEPTION );\r
+ #endif /* XPAR_MICROBLAZE_0_DPLB_BUS_EXCEPTION*/\r
\r
- #if XPAR_MICROBLAZE_0_FPU_EXCEPTION == 1\r
- microblaze_register_exception_handler( XEXC_ID_FPU, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_FPU );\r
- #endif /* XPAR_MICROBLAZE_0_FPU_EXCEPTION*/\r
+ #if XPAR_MICROBLAZE_0_DIV_ZERO_EXCEPTION == 1\r
+ microblaze_register_exception_handler( XEXC_ID_DIV_BY_ZERO, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_DIV_BY_ZERO );\r
+ #endif /* XPAR_MICROBLAZE_0_DIV_ZERO_EXCEPTION*/\r
\r
- #if XPAR_MICROBLAZE_0_FSL_EXCEPTION == 1\r
- microblaze_register_exception_handler( XEXC_ID_FSL, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_FSL );\r
- #endif /* XPAR_MICROBLAZE_0_FSL_EXCEPTION*/\r
+ #if XPAR_MICROBLAZE_0_FPU_EXCEPTION == 1\r
+ microblaze_register_exception_handler( XEXC_ID_FPU, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_FPU );\r
+ #endif /* XPAR_MICROBLAZE_0_FPU_EXCEPTION*/\r
+\r
+ #if XPAR_MICROBLAZE_0_FSL_EXCEPTION == 1\r
+ microblaze_register_exception_handler( XEXC_ID_FSL, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_FSL );\r
+ #endif /* XPAR_MICROBLAZE_0_FSL_EXCEPTION*/\r
+ }\r
}\r
-/*-----------------------------------------------------------*/\r
\r
/* Exclude the entire file if the MicroBlaze is not configured to handle\r
exceptions, or the application defined configuration item \r