Correct PLL setting for the defined configCPU_CLOCK_HZ setting.

git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@399 1d2547de-c912-0410-9cb9-b8ca96c0e9e2

diff --git a/Demo/ARM7_LPC2129_IAR/main.c b/Demo/ARM7_LPC2129_IAR/main.c
index 0d941447f6eca3fd729d7f3278c0b58ee71268ef..4c7a22fe22407a6ad86c1061066c8d760df95b6c 100644 (file)
--- a/Demo/ARM7_LPC2129_IAR/main.c
+++ b/Demo/ARM7_LPC2129_IAR/main.c
@@ -112,7 +112,7 @@
 #define mainRX_ENABLE                          ( ( unsigned portLONG ) 0x0004 )\r
 \r
 /* Constants to setup the PLL. */\r
-#define mainPLL_MUL_4                          ( ( unsigned portCHAR ) 0x0003 )\r
+#define mainPLL_MUL_5                          ( ( unsigned portCHAR ) 0x0004 )\r
 #define mainPLL_DIV_1                          ( ( unsigned portCHAR ) 0x0000 )\r
 #define mainPLL_ENABLE                         ( ( unsigned portCHAR ) 0x0001 )\r
 #define mainPLL_CONNECT                                ( ( unsigned portCHAR ) 0x0003 )\r
@@ -188,8 +188,8 @@ void main( void )
 \r
 static void prvSetupHardware( void )\r
 {\r
-       /* Setup the PLL to multiply the XTAL input by 4. */\r
-       PLLCFG = ( mainPLL_MUL_4 | mainPLL_DIV_1 );\r
+       /* Setup the PLL to multiply the XTAL input by 5. */\r
+       PLLCFG = ( mainPLL_MUL_5 | mainPLL_DIV_1 );\r
 \r
        /* Activate the PLL by turning it on then feeding the correct sequence of\r
        bytes. */\r