Add barrier instructions to GCC CM3/4 code.

git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@1853 1d2547de-c912-0410-9cb9-b8ca96c0e9e2

diff --git a/FreeRTOS/Source/portable/GCC/ARM_CM3/port.c b/FreeRTOS/Source/portable/GCC/ARM_CM3/port.c
index 4d43873efccb3257116b9bb1b1150e72462e2c4c..f4090d74a198073c6c52ca129049948fb9ca436c 100644 (file)
--- a/FreeRTOS/Source/portable/GCC/ARM_CM3/port.c
+++ b/FreeRTOS/Source/portable/GCC/ARM_CM3/port.c
@@ -56,19 +56,19 @@
     ***************************************************************************\r
 \r
 \r
-    http://www.FreeRTOS.org - Documentation, books, training, latest versions, \r
+    http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
     license and Real Time Engineers Ltd. contact details.\r
 \r
     http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
     including FreeRTOS+Trace - an indispensable productivity tool, and our new\r
     fully thread aware and reentrant UDP/IP stack.\r
 \r
-    http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High \r
-    Integrity Systems, who sell the code with commercial support, \r
+    http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
+    Integrity Systems, who sell the code with commercial support,\r
     indemnification and middleware, under the OpenRTOS brand.\r
-    \r
-    http://www.SafeRTOS.com - High Integrity Systems also provide a safety \r
-    engineered and independently SIL3 certified version for use in safety and \r
+\r
+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+    engineered and independently SIL3 certified version for use in safety and\r
     mission critical applications that require provable dependability.\r
 */\r
 \r
@@ -259,6 +259,11 @@ void vPortYieldFromISR( void )
 {\r
        /* Set a PendSV to request a context switch. */\r
        portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\r
+\r
+       /* Barriers are normally not required but do ensure the code is completely\r
+       within the specified behaviour for the architecture. */\r
+       __asm volatile( "dsb" );\r
+       __asm volatile( "isb" );\r
 }\r
 /*-----------------------------------------------------------*/\r
 \r
@@ -266,6 +271,8 @@ void vPortEnterCritical( void )
 {\r
        portDISABLE_INTERRUPTS();\r
        uxCriticalNesting++;\r
+       __asm volatile( "dsb" );\r
+       __asm volatile( "isb" );\r
 }\r
 /*-----------------------------------------------------------*/\r
 \r
@@ -438,6 +445,8 @@ void xPortSysTickHandler( void )
                        if( xModifiableIdleTime > 0 )\r
                        {\r
                                __asm volatile( "wfi" );\r
+                               __asm volatile( "dsb" );\r
+                               __asm volatile( "isb" );\r
                        }\r
                        configPOST_SLEEP_PROCESSING( xExpectedIdleTime );\r
 \r