Update Risc-V port to use environment call in place of software interrupt - still...

git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2592 1d2547de-c912-0410-9cb9-b8ca96c0e9e2

diff --git a/FreeRTOS/Source/portable/GCC/RISC-V-RV32/port.c b/FreeRTOS/Source/portable/GCC/RISC-V-RV32/port.c
index 4f09da8ca3972c796d615c95f806145ff68e94d6..ed2c29885fc86fb621290f9067d0bbe6e191994a 100644 (file)
--- a/FreeRTOS/Source/portable/GCC/RISC-V-RV32/port.c
+++ b/FreeRTOS/Source/portable/GCC/RISC-V-RV32/port.c
@@ -94,6 +94,12 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px
                x28-31          t3-6                    Temporaries                                     Caller\r
        */\r
 \r
+       /* To ensure alignment. */\r
+       //_RB_  pxTopOfStack--;\r
+       //_RB_  pxTopOfStack--;\r
+       //_RB_pxTopOfStack--;\r
+\r
+       /* Numbers correspond to the x register number. */\r
        pxTopOfStack--;\r
        *pxTopOfStack = ( StackType_t ) 31;\r
        pxTopOfStack--;\r
@@ -185,7 +191,7 @@ volatile uint32_t * const pulTimeLow = ( volatile uint32_t * const ) ( configCTR
        ullNextTime += ullTimerIncrementsForOneTick;\r
 \r
        /* Enable timer interrupt */\r
-       __asm volatile( "csrs mie, %0" :: "r"(0x80) );\r
+       __asm volatile( "csrs mie, %0" :: "r"(0x80) ); /* 1<<7 for timer interrupt. */\r
 }\r
 /*-----------------------------------------------------------*/\r
 \r
@@ -196,19 +202,21 @@ volatile uint32_t * const ulSoftInterrupt = ( uint32_t * ) configCTRL_BASE;
        vTaskSwitchContext();\r
 \r
        /* Clear software interrupt. */\r
-       *( ( uint32_t * ) configCTRL_BASE ) = 0UL;\r
+       *( ( uint32_t * ) configCTRL_BASE ) &= 0x08UL;\r
 }\r
 /*-----------------------------------------------------------*/\r
 \r
 void Timer_IRQHandler( void )\r
 {\r
+extern void vTaskSwitchContext( void );\r
+\r
        /* Reload for the next timer interrupt. */\r
        *pullMachineTimerCompareRegister = ullNextTime;\r
        ullNextTime += ullTimerIncrementsForOneTick;\r
 \r
        if( xTaskIncrementTick() != pdFALSE )\r
        {\r
-               portYIELD();\r
+               vTaskSwitchContext();\r
        }\r
 }\r
 /*-----------------------------------------------------------*/\r
@@ -217,6 +225,17 @@ BaseType_t xPortStartScheduler( void )
 {\r
 extern void xPortStartFirstTask( void );\r
 \r
+       #if( configASSERT_DEFINED == 1 )\r
+       {\r
+               volatile uint32_t mtvec = 0;\r
+\r
+               /* Check the least significant two bits of mtvec are 00 - indicating single\r
+               vector mode. */\r
+               __asm volatile( "csrr %0, mtvec" : "=r"( mtvec ) );\r
+               configASSERT( ( mtvec & 0x03UL ) == 0 );\r
+       }\r
+       #endif\r
+\r
        vPortSetupTimerInterrupt();\r
        xPortStartFirstTask();\r
 \r

diff --git a/FreeRTOS/Source/portable/GCC/RISC-V-RV32/portASM.S b/FreeRTOS/Source/portable/GCC/RISC-V-RV32/portASM.S
index d27391d77ab254740ec77afb3f5b191355ce82e8..f376b61e3ab3cc66fc6efc13a55cd1110b35e080 100644 (file)
--- a/FreeRTOS/Source/portable/GCC/RISC-V-RV32/portASM.S
+++ b/FreeRTOS/Source/portable/GCC/RISC-V-RV32/portASM.S
@@ -82,14 +82,14 @@ xPortStartFirstTask:
     addi    sp, sp, CONTEXT_SIZE\r
     csrs    mstatus, 8              /* Enable machine interrupts. */\r
     csrs    mie, 8                  /* Enable soft interrupt. */\r
-     ret\r
+    ret\r
 \r
 /*-----------------------------------------------------------*/\r
 \r
 .align 8\r
 vPortTrapHandler:\r
        addi sp, sp, -CONTEXT_SIZE\r
-       sw x1, 1( sp )\r
+       sw x1, 1 * WORD_SIZE( sp )\r
        sw x5, 2 * WORD_SIZE( sp )\r
        sw x6, 3 * WORD_SIZE( sp )\r
        sw x7, 4 * WORD_SIZE( sp )\r
@@ -118,10 +118,6 @@ vPortTrapHandler:
        sw x30, 27 * WORD_SIZE( sp )\r
        sw x31, 28 * WORD_SIZE( sp )\r
 \r
-    /* Save exception return address. */\r
-    csrr t0, mepc\r
-    sw t0, 0( sp )\r
-\r
     lw  t0, pxCurrentTCB            /* Load pxCurrentTCB. */\r
     sw  sp, 0( t0 )                 /* Write sp from first TCB member. */\r
 \r
@@ -130,6 +126,9 @@ vPortTrapHandler:
        mv a2, sp\r
        jal handle_trap\r
        csrw mepc, a0\r
+       /* Save exception return address. */\r
+       sw a0, 0( sp )\r
+\r
 \r
        # Remain in M-mode after mret\r
        li t0, 0x00001800 /* MSTATUS MPP */\r
@@ -138,11 +137,11 @@ vPortTrapHandler:
     lw  sp, pxCurrentTCB            /* Load pxCurrentTCB. */\r
     lw  sp, 0( sp )                 /* Read sp from first TCB member. */\r
 \r
-    /* Load mret with the address of the first task. */\r
+    /* Load mret with the address of the next task. */\r
     lw t0, 0( sp )\r
     csrw mepc, t0\r
 \r
-    lw  x1, 1( sp )\r
+    lw  x1, 1 * WORD_SIZE( sp )\r
     lw  x5, 2 * WORD_SIZE( sp )     /* t0 */\r
     lw  x6, 3 * WORD_SIZE( sp )     /* t1 */\r
     lw  x7, 4 * WORD_SIZE( sp )     /* t2 */\r

diff --git a/FreeRTOS/Source/portable/GCC/RISC-V-RV32/portmacro.h b/FreeRTOS/Source/portable/GCC/RISC-V-RV32/portmacro.h
index 828e810bb50bd60560b3fd94e742cf346150895d..d1df6815a44faf341bd0379f3ab9e2b6b1e1263a 100644 (file)
--- a/FreeRTOS/Source/portable/GCC/RISC-V-RV32/portmacro.h
+++ b/FreeRTOS/Source/portable/GCC/RISC-V-RV32/portmacro.h
@@ -70,7 +70,7 @@ not need to be guarded with a critical section. */
 \r
 \r
 /* Scheduler utilities. */\r
-#define portYIELD() *( ( uint32_t * ) configCTRL_BASE ) = 1UL\r
+#define portYIELD() __asm volatile( "ecall" ); // software interrupt alternative *( ( uint32_t * ) configCTRL_BASE ) |= 0x08UL\r
 #define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) vPortYield()\r
 #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )\r
 /*-----------------------------------------------------------*/\r