reg_t -> struct reg

Remove misleading typedef and redundant suffix from struct reg.

diff --git a/src/server/gdb_server.c b/src/server/gdb_server.c
index 732f68be96b3d05796206ff52fa08c6ef3abc1d5..85855d9140aa0cbd8b3887e88a03d5e1613eddb1 100644 (file)
--- a/src/server/gdb_server.c
+++ b/src/server/gdb_server.c
@@ -863,7 +863,7 @@ static int gdb_reg_pos(target_t *target, int pos, int len)
  * The format of reg->value is little endian
  *
  */
-void gdb_str_to_target(target_t *target, char *tstr, reg_t *reg)
+void gdb_str_to_target(target_t *target, char *tstr, struct reg *reg)
 {
        int i;
 
@@ -917,7 +917,7 @@ void gdb_target_to_reg(target_t *target, char *tstr, int str_len, uint8_t *bin)
 
 int gdb_get_registers_packet(struct connection *connection, target_t *target, char* packet, int packet_size)
 {
-       reg_t **reg_list;
+       struct reg **reg_list;
        int reg_list_size;
        int retval;
        int reg_packet_size = 0;
@@ -968,7 +968,7 @@ int gdb_get_registers_packet(struct connection *connection, target_t *target, ch
 int gdb_set_registers_packet(struct connection *connection, target_t *target, char *packet, int packet_size)
 {
        int i;
-       reg_t **reg_list;
+       struct reg **reg_list;
        int reg_list_size;
        int retval;
        char *packet_p;
@@ -1019,7 +1019,7 @@ int gdb_set_registers_packet(struct connection *connection, target_t *target, ch
                free(bin_buf);
        }
 
-       /* free reg_t *reg_list[] array allocated by get_gdb_reg_list */
+       /* free struct reg *reg_list[] array allocated by get_gdb_reg_list */
        free(reg_list);
 
        gdb_put_packet(connection, "OK", 2);
@@ -1031,7 +1031,7 @@ int gdb_get_register_packet(struct connection *connection, target_t *target, cha
 {
        char *reg_packet;
        int reg_num = strtoul(packet + 1, NULL, 16);
-       reg_t **reg_list;
+       struct reg **reg_list;
        int reg_list_size;
        int retval;
 
@@ -1067,7 +1067,7 @@ int gdb_set_register_packet(struct connection *connection, target_t *target, cha
        char *separator;
        uint8_t *bin_buf;
        int reg_num = strtoul(packet + 1, &separator, 16);
-       reg_t **reg_list;
+       struct reg **reg_list;
        int reg_list_size;
        int retval;
        struct reg_arch_type *arch_type;

diff --git a/src/target/arm11.c b/src/target/arm11.c
index 22925c8e86dd948752a08a33e6f5cb53fda83231..0b1b9c0d7f50187a7649484c5fa05b17d7201fc1 100644 (file)
--- a/src/target/arm11.c
+++ b/src/target/arm11.c
@@ -248,14 +248,14 @@ enum arm11_regcache_ids
 
 static uint8_t arm11_gdb_dummy_fp_value[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
 
-static reg_t arm11_gdb_dummy_fp_reg =
+static struct reg arm11_gdb_dummy_fp_reg =
 {
        "GDB dummy floating-point register", arm11_gdb_dummy_fp_value, 0, 1, 96, NULL, 0, NULL, 0
 };
 
 static uint8_t arm11_gdb_dummy_fps_value[] = {0, 0, 0, 0};
 
-static reg_t arm11_gdb_dummy_fps_reg =
+static struct reg arm11_gdb_dummy_fps_reg =
 {
        "GDB dummy floating-point status register", arm11_gdb_dummy_fps_value, 0, 1, 32, NULL, 0, NULL, 0
 };
@@ -266,8 +266,8 @@ static int arm11_step(struct target_s *target, int current,
                uint32_t address, int handle_breakpoints);
 /* helpers */
 static int arm11_build_reg_cache(target_t *target);
-static int arm11_set_reg(reg_t *reg, uint8_t *buf);
-static int arm11_get_reg(reg_t *reg);
+static int arm11_set_reg(struct reg *reg, uint8_t *buf);
+static int arm11_get_reg(struct reg *reg);
 
 static void arm11_record_register_history(struct arm11_common * arm11);
 static void arm11_dump_reg_changes(struct arm11_common * arm11);
@@ -1245,14 +1245,14 @@ static int arm11_soft_reset_halt(struct target_s *target)
 
 /* target register access for gdb */
 static int arm11_get_gdb_reg_list(struct target_s *target,
-               struct reg_s **reg_list[], int *reg_list_size)
+               struct reg **reg_list[], int *reg_list_size)
 {
        FNC_INFO;
 
        struct arm11_common * arm11 = target->arch_info;
 
        *reg_list_size  = ARM11_GDB_REGISTER_COUNT;
-       *reg_list               = malloc(sizeof(reg_t*) * ARM11_GDB_REGISTER_COUNT);
+       *reg_list               = malloc(sizeof(struct reg*) * ARM11_GDB_REGISTER_COUNT);
 
        for (size_t i = 16; i < 24; i++)
        {
@@ -1657,7 +1657,7 @@ static int arm11_run_algorithm(struct target_s *target,
        // Set register parameters
        for (int i = 0; i < num_reg_params; i++)
        {
-               reg_t *reg = register_get_by_name(arm11->core_cache, reg_params[i].reg_name, 0);
+               struct reg *reg = register_get_by_name(arm11->core_cache, reg_params[i].reg_name, 0);
                if (!reg)
                {
                        LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
@@ -1742,7 +1742,7 @@ static int arm11_run_algorithm(struct target_s *target,
        {
                if (reg_params[i].direction != PARAM_OUT)
                {
-                       reg_t *reg = register_get_by_name(arm11->core_cache, reg_params[i].reg_name, 0);
+                       struct reg *reg = register_get_by_name(arm11->core_cache, reg_params[i].reg_name, 0);
                        if (!reg)
                        {
                                LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
@@ -1891,7 +1891,7 @@ static int arm11_examine(struct target_s *target)
 
 
 /** Load a register that is marked !valid in the register cache */
-static int arm11_get_reg(reg_t *reg)
+static int arm11_get_reg(struct reg *reg)
 {
        FNC_INFO;
 
@@ -1914,7 +1914,7 @@ static int arm11_get_reg(reg_t *reg)
 }
 
 /** Change a value in the register cache */
-static int arm11_set_reg(reg_t *reg, uint8_t *buf)
+static int arm11_set_reg(struct reg *reg, uint8_t *buf)
 {
        FNC_INFO;
 
@@ -1934,7 +1934,7 @@ static int arm11_build_reg_cache(target_t *target)
        struct arm11_common *arm11 = target->arch_info;
 
        NEW(struct reg_cache,           cache,                          1);
-       NEW(reg_t,                              reg_list,                       ARM11_REGCACHE_COUNT);
+       NEW(struct reg,                         reg_list,                       ARM11_REGCACHE_COUNT);
        NEW(struct arm11_reg_state,     arm11_reg_states,       ARM11_REGCACHE_COUNT);
 
        if (arm11_regs_arch_type == -1)
@@ -1970,7 +1970,7 @@ static int arm11_build_reg_cache(target_t *target)
 
        for (i = 0; i < ARM11_REGCACHE_COUNT; i++)
        {
-               reg_t *                                         r       = reg_list                      + i;
+               struct reg *                                            r       = reg_list                      + i;
                const struct arm11_reg_defs *   rd      = arm11_reg_defs        + i;
                struct arm11_reg_state *                        rs      = arm11_reg_states      + i;
 

diff --git a/src/target/arm11.h b/src/target/arm11.h
index b397709a82c287afd45a0ab234df0e648237edc0..6bc1a25133c85cd7f3c8d8a69d2ebf5bb07514e7 100644 (file)
--- a/src/target/arm11.h
+++ b/src/target/arm11.h
@@ -104,7 +104,7 @@ struct arm11_common
        /** \name Shadow registers to save processor state */
        /*@{*/
 
-       reg_t * reg_list;                                                       /**< target register list */
+       struct reg *    reg_list;                                                       /**< target register list */
        uint32_t                reg_values[ARM11_REGCACHE_COUNT];       /**< data for registers */
 
        /*@}*/

diff --git a/src/target/arm720t.c b/src/target/arm720t.c
index b258e2f9ce440e994f523f51319bcc5075c75713..7f2b4038062b6d26cd1f9ad807d007112931973f 100644 (file)
--- a/src/target/arm720t.c
+++ b/src/target/arm720t.c
@@ -304,7 +304,7 @@ static int arm720t_soft_reset_halt(struct target_s *target)
 {
        int retval = ERROR_OK;
        struct arm720t_common *arm720t = target_to_arm720(target);
-       reg_t *dbg_stat = &arm720t->arm7tdmi_common.arm7_9_common
+       struct reg *dbg_stat = &arm720t->arm7tdmi_common.arm7_9_common
                        .eice_cache->reg_list[EICE_DBG_STAT];
        struct armv4_5_common_s *armv4_5 = &arm720t->arm7tdmi_common
                        .arm7_9_common.armv4_5_common;

diff --git a/src/target/arm7_9_common.c b/src/target/arm7_9_common.c
index 9bb75673518f5dd730f77e35c7528553c44d779e..0523d82979368fc0ef654963a0258bb485a14194 100644 (file)
--- a/src/target/arm7_9_common.c
+++ b/src/target/arm7_9_common.c
@@ -704,7 +704,7 @@ int arm7_9_execute_sys_speed(struct target_s *target)
        int retval;
        struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
        struct arm_jtag *jtag_info = &arm7_9->jtag_info;
-       reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
+       struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
 
        /* set RESTART instruction */
        jtag_set_end_state(TAP_IDLE);
@@ -757,7 +757,7 @@ int arm7_9_execute_fast_sys_speed(struct target_s *target)
 
        struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
        struct arm_jtag *jtag_info = &arm7_9->jtag_info;
-       reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
+       struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
 
        /* set RESTART instruction */
        jtag_set_end_state(TAP_IDLE);
@@ -834,7 +834,7 @@ int arm7_9_handle_target_request(void *priv)
                return ERROR_OK;
        struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
        struct arm_jtag *jtag_info = &arm7_9->jtag_info;
-       reg_t *dcc_control = &arm7_9->eice_cache->reg_list[EICE_COMMS_CTRL];
+       struct reg *dcc_control = &arm7_9->eice_cache->reg_list[EICE_COMMS_CTRL];
 
        if (!target->dbg_msg_enabled)
                return ERROR_OK;
@@ -891,7 +891,7 @@ int arm7_9_poll(target_t *target)
 {
        int retval;
        struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
-       reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
+       struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
 
        /* read debug status register */
        embeddedice_read_reg(dbg_stat);
@@ -931,7 +931,7 @@ int arm7_9_poll(target_t *target)
 
                        if (check_pc)
                        {
-                               reg_t *reg = register_get_by_name(target->reg_cache, "pc", 1);
+                               struct reg *reg = register_get_by_name(target->reg_cache, "pc", 1);
                                uint32_t t=*((uint32_t *)reg->value);
                                if (t != 0)
                                {
@@ -1115,7 +1115,7 @@ int arm7_9_deassert_reset(target_t *target)
 int arm7_9_clear_halt(target_t *target)
 {
        struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
-       reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
+       struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
 
        /* we used DBGRQ only if we didn't come out of reset */
        if (!arm7_9->debug_entry_from_reset && arm7_9->use_dbgrq)
@@ -1173,8 +1173,8 @@ int arm7_9_soft_reset_halt(struct target_s *target)
 {
        struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
        struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
-       reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
-       reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
+       struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
+       struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
        int i;
        int retval;
 
@@ -1291,7 +1291,7 @@ int arm7_9_halt(target_t *target)
        }
 
        struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
-       reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
+       struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
 
        LOG_DEBUG("target->state: %s",
                  target_state_name(target));
@@ -1354,8 +1354,8 @@ int arm7_9_debug_entry(target_t *target)
        int retval;
        struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
        struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
-       reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
-       reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
+       struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
+       struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
 
 #ifdef _DEBUG_ARM7_9_
        LOG_DEBUG("-");
@@ -1599,7 +1599,7 @@ int arm7_9_restore_context(target_t *target)
 {
        struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
        struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
-       reg_t *reg;
+       struct reg *reg;
        struct armv4_5_core_reg *reg_arch_info;
        enum armv4_5_mode current_mode = armv4_5->core_mode;
        int i, j;
@@ -1803,7 +1803,7 @@ int arm7_9_resume(struct target_s *target, int current, uint32_t address, int ha
        struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
        struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
        struct breakpoint *breakpoint = target->breakpoints;
-       reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
+       struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
        int err, retval = ERROR_OK;
 
        LOG_DEBUG("-");
@@ -2409,7 +2409,7 @@ int arm7_9_write_memory(struct target_s *target, uint32_t address, uint32_t size
 {
        struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
        struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
-       reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
+       struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
 
        uint32_t reg[16];
        uint32_t num_accesses = 0;

diff --git a/src/target/arm7tdmi.c b/src/target/arm7tdmi.c
index aea012dc079c2e24d8652152c355a4d2ad1dec0c..1beae89a711b1fb22349c0f23fde2d5d8d93d3b7 100644 (file)
--- a/src/target/arm7tdmi.c
+++ b/src/target/arm7tdmi.c
@@ -582,7 +582,7 @@ static void arm7tdmi_branch_resume_thumb(target_t *target)
        struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
        struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
        struct arm_jtag *jtag_info = &arm7_9->jtag_info;
-       reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
+       struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
 
        LOG_DEBUG("-");
 

diff --git a/src/target/arm920t.c b/src/target/arm920t.c
index 32f4a2fff057be81fe187c11d95cb68bc36b6288..0173550d8698a7d98512960797c5600a25943e61 100644 (file)
--- a/src/target/arm920t.c
+++ b/src/target/arm920t.c
@@ -555,7 +555,7 @@ int arm920t_soft_reset_halt(struct target_s *target)
        struct arm920t_common *arm920t = target_to_arm920(target);
        struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
        struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
-       reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
+       struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
 
        if ((retval = target_halt(target)) != ERROR_OK)
        {

diff --git a/src/target/arm926ejs.c b/src/target/arm926ejs.c
index fd8e0b6a33c8049bd6c3c07d1ce6a4c924368368..7d37590fb1acae2e0c9b4eb71b99c131a3f9d7a1 100644 (file)
--- a/src/target/arm926ejs.c
+++ b/src/target/arm926ejs.c
@@ -232,7 +232,7 @@ static int arm926ejs_mcr(target_t *target, int cpnum, uint32_t op1,
 static int arm926ejs_examine_debug_reason(target_t *target)
 {
        struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
-       reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
+       struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
        int debug_reason;
        int retval;
 
@@ -524,7 +524,7 @@ int arm926ejs_soft_reset_halt(struct target_s *target)
        struct arm926ejs_common *arm926ejs = target_to_arm926(target);
        struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
        struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
-       reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
+       struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
 
        if ((retval = target_halt(target)) != ERROR_OK)
        {

diff --git a/src/target/arm9tdmi.c b/src/target/arm9tdmi.c
index 1edb6264c06dc50e3f25bbd86514f08436d1b51f..0c390dfb8ca8763684c5d9eb0dd54df991700350 100644 (file)
--- a/src/target/arm9tdmi.c
+++ b/src/target/arm9tdmi.c
@@ -651,7 +651,7 @@ static void arm9tdmi_branch_resume_thumb(target_t *target)
        struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
        struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
        struct arm_jtag *jtag_info = &arm7_9->jtag_info;
-       reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
+       struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
 
        /* LDMIA r0-15, [r0] at debug speed
        * register values will start to appear on 4th DCLK
@@ -860,7 +860,7 @@ COMMAND_HANDLER(handle_arm9tdmi_catch_vectors_command)
 {
        target_t *target = get_current_target(cmd_ctx);
        struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
-       reg_t *vector_catch;
+       struct reg *vector_catch;
        uint32_t vector_catch_value;
 
        /* it's uncommon, but some ARM7 chips can support this */

diff --git a/src/target/armv4_5.c b/src/target/armv4_5.c
index 4040623e3a3b3391b4e03041815af44a6a3c6dc3..02105e5f3eee34df362f1884352001813b0e8cb2 100644 (file)
--- a/src/target/armv4_5.c
+++ b/src/target/armv4_5.c
@@ -155,19 +155,19 @@ int armv4_5_core_reg_map[7][17] =
 
 uint8_t armv4_5_gdb_dummy_fp_value[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
 
-reg_t armv4_5_gdb_dummy_fp_reg =
+struct reg armv4_5_gdb_dummy_fp_reg =
 {
        "GDB dummy floating-point register", armv4_5_gdb_dummy_fp_value, 0, 1, 96, NULL, 0, NULL, 0
 };
 
 uint8_t armv4_5_gdb_dummy_fps_value[] = {0, 0, 0, 0};
 
-reg_t armv4_5_gdb_dummy_fps_reg =
+struct reg armv4_5_gdb_dummy_fps_reg =
 {
        "GDB dummy floating-point status register", armv4_5_gdb_dummy_fps_value, 0, 1, 32, NULL, 0, NULL, 0
 };
 
-int armv4_5_get_core_reg(reg_t *reg)
+int armv4_5_get_core_reg(struct reg *reg)
 {
        int retval;
        struct armv4_5_core_reg *armv4_5 = reg->arch_info;
@@ -185,7 +185,7 @@ int armv4_5_get_core_reg(reg_t *reg)
        return retval;
 }
 
-int armv4_5_set_core_reg(reg_t *reg, uint8_t *buf)
+int armv4_5_set_core_reg(struct reg *reg, uint8_t *buf)
 {
        struct armv4_5_core_reg *armv4_5 = reg->arch_info;
        target_t *target = armv4_5->target;
@@ -253,7 +253,7 @@ struct reg_cache* armv4_5_build_reg_cache(target_t *target, struct arm *armv4_5_
 {
        int num_regs = 37;
        struct reg_cache *cache = malloc(sizeof(struct reg_cache));
-       reg_t *reg_list = malloc(sizeof(reg_t) * num_regs);
+       struct reg *reg_list = malloc(sizeof(struct reg) * num_regs);
        struct armv4_5_core_reg *arch_info = malloc(sizeof(struct armv4_5_core_reg) * num_regs);
        int i;
 
@@ -483,7 +483,7 @@ int armv4_5_register_commands(struct command_context_s *cmd_ctx)
        return ERROR_OK;
 }
 
-int armv4_5_get_gdb_reg_list(target_t *target, reg_t **reg_list[], int *reg_list_size)
+int armv4_5_get_gdb_reg_list(target_t *target, struct reg **reg_list[], int *reg_list_size)
 {
        struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
        int i;
@@ -492,7 +492,7 @@ int armv4_5_get_gdb_reg_list(target_t *target, reg_t **reg_list[], int *reg_list
                return ERROR_FAIL;
 
        *reg_list_size = 26;
-       *reg_list = malloc(sizeof(reg_t*) * (*reg_list_size));
+       *reg_list = malloc(sizeof(struct reg*) * (*reg_list_size));
 
        for (i = 0; i < 16; i++)
        {
@@ -596,7 +596,7 @@ int armv4_5_run_algorithm_inner(struct target_s *target, int num_mem_params, str
 
        for (i = 0; i < num_reg_params; i++)
        {
-               reg_t *reg = register_get_by_name(armv4_5->core_cache, reg_params[i].reg_name, 0);
+               struct reg *reg = register_get_by_name(armv4_5->core_cache, reg_params[i].reg_name, 0);
                if (!reg)
                {
                        LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
@@ -669,7 +669,7 @@ int armv4_5_run_algorithm_inner(struct target_s *target, int num_mem_params, str
                if (reg_params[i].direction != PARAM_OUT)
                {
 
-                       reg_t *reg = register_get_by_name(armv4_5->core_cache, reg_params[i].reg_name, 0);
+                       struct reg *reg = register_get_by_name(armv4_5->core_cache, reg_params[i].reg_name, 0);
                        if (!reg)
                        {
                                LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);

diff --git a/src/target/armv4_5.h b/src/target/armv4_5.h
index 9823f4e66b936b070d14d3d7c1bd06eabcc20a50..16fb85df4d9dc517aa4097d4229ae6be5d968ca4 100644 (file)
--- a/src/target/armv4_5.h
+++ b/src/target/armv4_5.h
@@ -177,7 +177,7 @@ static __inline enum armv4_5_mode armv4_5_number_to_mode(int number)
 
 int armv4_5_arch_state(struct target_s *target);
 int armv4_5_get_gdb_reg_list(target_t *target,
-               reg_t **reg_list[], int *reg_list_size);
+               struct reg **reg_list[], int *reg_list_size);
 
 int armv4_5_register_commands(struct command_context_s *cmd_ctx);
 int armv4_5_init_arch_info(target_t *target, struct arm *armv4_5);

diff --git a/src/target/armv7a.c b/src/target/armv7a.c
index efe3d36d47a1301cebc9e8152e1b0fb0d7714cdc..ead5b9c21ffeeabf9d40eaa853a9cebfd32ef75d 100644 (file)
--- a/src/target/armv7a.c
+++ b/src/target/armv7a.c
@@ -167,7 +167,7 @@ int armv7a_core_reg_map[8][17] =
 
 uint8_t armv7a_gdb_dummy_fp_value[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
 
-reg_t armv7a_gdb_dummy_fp_reg =
+struct reg armv7a_gdb_dummy_fp_reg =
 {
        "GDB dummy floating-point register", armv7a_gdb_dummy_fp_value,
                        0, 1, 96, NULL, 0, NULL, 0

diff --git a/src/target/armv7m.c b/src/target/armv7m.c
index 4a6869fae6b3dc3eb18a49e5507a36471f5bbf3a..29698039c0d4ec57dd57fb9fbd75a0193fe604bc 100644 (file)
--- a/src/target/armv7m.c
+++ b/src/target/armv7m.c
@@ -61,14 +61,14 @@ static uint8_t armv7m_gdb_dummy_fp_value[12] = {
        0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 };
 
-static reg_t armv7m_gdb_dummy_fp_reg =
+static struct reg armv7m_gdb_dummy_fp_reg =
 {
        "GDB dummy floating-point register", armv7m_gdb_dummy_fp_value, 0, 1, 96, NULL, 0, NULL, 0
 };
 
 static uint8_t armv7m_gdb_dummy_fps_value[] = {0, 0, 0, 0};
 
-static reg_t armv7m_gdb_dummy_fps_reg =
+static struct reg armv7m_gdb_dummy_fps_reg =
 {
        "GDB dummy floating-point status register", armv7m_gdb_dummy_fps_value, 0, 1, 32, NULL, 0, NULL, 0
 };
@@ -76,7 +76,7 @@ static reg_t armv7m_gdb_dummy_fps_reg =
 #ifdef ARMV7_GDB_HACKS
 uint8_t armv7m_gdb_dummy_cpsr_value[] = {0, 0, 0, 0};
 
-reg_t armv7m_gdb_dummy_cpsr_reg =
+struct reg armv7m_gdb_dummy_cpsr_reg =
 {
        "GDB dummy cpsr register", armv7m_gdb_dummy_cpsr_value, 0, 1, 32, NULL, 0, NULL, 0
 };
@@ -178,7 +178,7 @@ char *armv7m_exception_string(int number)
        return enamebuf;
 }
 
-static int armv7m_get_core_reg(reg_t *reg)
+static int armv7m_get_core_reg(struct reg *reg)
 {
        int retval;
        struct armv7m_core_reg *armv7m_reg = reg->arch_info;
@@ -195,7 +195,7 @@ static int armv7m_get_core_reg(reg_t *reg)
        return retval;
 }
 
-static int armv7m_set_core_reg(reg_t *reg, uint8_t *buf)
+static int armv7m_set_core_reg(struct reg *reg, uint8_t *buf)
 {
        struct armv7m_core_reg *armv7m_reg = reg->arch_info;
        target_t *target = armv7m_reg->target;
@@ -279,13 +279,13 @@ int armv7m_invalidate_core_regs(target_t *target)
  * hardware, so this also fakes a set of long-obsolete FPA registers that
  * are not used in EABI based software stacks.
  */
-int armv7m_get_gdb_reg_list(target_t *target, reg_t **reg_list[], int *reg_list_size)
+int armv7m_get_gdb_reg_list(target_t *target, struct reg **reg_list[], int *reg_list_size)
 {
        struct armv7m_common *armv7m = target_to_armv7m(target);
        int i;
 
        *reg_list_size = 26;
-       *reg_list = malloc(sizeof(reg_t*) * (*reg_list_size));
+       *reg_list = malloc(sizeof(struct reg*) * (*reg_list_size));
 
        /*
         * GDB register packet format for ARM:
@@ -398,7 +398,7 @@ int armv7m_run_algorithm(struct target_s *target,
 
        for (i = 0; i < num_reg_params; i++)
        {
-               reg_t *reg = register_get_by_name(armv7m->core_cache, reg_params[i].reg_name, 0);
+               struct reg *reg = register_get_by_name(armv7m->core_cache, reg_params[i].reg_name, 0);
 //             uint32_t regvalue;
 
                if (!reg)
@@ -462,7 +462,7 @@ int armv7m_run_algorithm(struct target_s *target,
        {
                if (reg_params[i].direction != PARAM_OUT)
                {
-                       reg_t *reg = register_get_by_name(armv7m->core_cache, reg_params[i].reg_name, 0);
+                       struct reg *reg = register_get_by_name(armv7m->core_cache, reg_params[i].reg_name, 0);
 
                        if (!reg)
                        {
@@ -530,7 +530,7 @@ struct reg_cache *armv7m_build_reg_cache(target_t *target)
        int num_regs = ARMV7M_NUM_REGS;
        struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
        struct reg_cache *cache = malloc(sizeof(struct reg_cache));
-       reg_t *reg_list = calloc(num_regs, sizeof(reg_t));
+       struct reg *reg_list = calloc(num_regs, sizeof(struct reg));
        struct armv7m_core_reg *arch_info = calloc(num_regs, sizeof(struct armv7m_core_reg));
        int i;
 

diff --git a/src/target/armv7m.h b/src/target/armv7m.h
index 2f4fbdb531d9c9d38b7534b238d4ed01882eb1c7..60f4cba0eb9ea0a533f5ac3a3e2979422dacf45d 100644 (file)
--- a/src/target/armv7m.h
+++ b/src/target/armv7m.h
@@ -140,7 +140,7 @@ int armv7m_mode_to_number(enum armv7m_mode mode);
 
 int armv7m_arch_state(struct target_s *target);
 int armv7m_get_gdb_reg_list(target_t *target,
-               reg_t **reg_list[], int *reg_list_size);
+               struct reg **reg_list[], int *reg_list_size);
 
 int armv7m_register_commands(struct command_context_s *cmd_ctx);
 int armv7m_init_arch_info(target_t *target, struct armv7m_common *armv7m);

diff --git a/src/target/cortex_m3.c b/src/target/cortex_m3.c
index 9f9016d2ca0a79f9b939aa74c1ec651b5e040ea1..58c3d8f71d4a0b8aaa2a22109d73c279d549cb67 100644 (file)
--- a/src/target/cortex_m3.c
+++ b/src/target/cortex_m3.c
@@ -53,7 +53,7 @@ static int cortex_m3_store_core_reg_u32(target_t *target,
 
 #ifdef ARMV7_GDB_HACKS
 extern uint8_t armv7m_gdb_dummy_cpsr_value[];
-extern reg_t armv7m_gdb_dummy_cpsr_reg;
+extern struct reg armv7m_gdb_dummy_cpsr_reg;
 #endif
 
 static int cortexm3_dap_read_coreregister_u32(struct swjdp_common *swjdp,
@@ -1453,14 +1453,14 @@ struct dwt_reg_state {
        uint32_t        value;  /* scratch/cache */
 };
 
-static int cortex_m3_dwt_get_reg(struct reg_s *reg)
+static int cortex_m3_dwt_get_reg(struct reg *reg)
 {
        struct dwt_reg_state *state = reg->arch_info;
 
        return target_read_u32(state->target, state->addr, &state->value);
 }
 
-static int cortex_m3_dwt_set_reg(struct reg_s *reg, uint8_t *buf)
+static int cortex_m3_dwt_set_reg(struct reg *reg, uint8_t *buf)
 {
        struct dwt_reg_state *state = reg->arch_info;
 
@@ -1495,7 +1495,7 @@ static struct dwt_reg dwt_comp[] = {
 static int dwt_reg_type = -1;
 
 static void
-cortex_m3_dwt_addreg(struct target_s *t, struct reg_s *r, struct dwt_reg *d)
+cortex_m3_dwt_addreg(struct target_s *t, struct reg *r, struct dwt_reg *d)
 {
        struct dwt_reg_state *state;
 

diff --git a/src/target/embeddedice.c b/src/target/embeddedice.c
index 4d939818b28f81c650ed49b7e5f313cb7dafc291..21195f7efa1ce39ea9a7615db65998ec0fff9255 100644 (file)
--- a/src/target/embeddedice.c
+++ b/src/target/embeddedice.c
@@ -146,7 +146,7 @@ static const struct {
 
 static int embeddedice_reg_arch_type = -1;
 
-static int embeddedice_get_reg(reg_t *reg)
+static int embeddedice_get_reg(struct reg *reg)
 {
        int retval;
 
@@ -168,7 +168,7 @@ embeddedice_build_reg_cache(target_t *target, struct arm7_9_common *arm7_9)
 {
        int retval;
        struct reg_cache *reg_cache = malloc(sizeof(struct reg_cache));
-       reg_t *reg_list = NULL;
+       struct reg *reg_list = NULL;
        struct embeddedice_reg *arch_info = NULL;
        struct arm_jtag *jtag_info = &arm7_9->jtag_info;
        int num_regs = ARRAY_SIZE(eice_regs);
@@ -185,7 +185,7 @@ embeddedice_build_reg_cache(target_t *target, struct arm7_9_common *arm7_9)
                num_regs--;
 
        /* the actual registers are kept in two arrays */
-       reg_list = calloc(num_regs, sizeof(reg_t));
+       reg_list = calloc(num_regs, sizeof(struct reg));
        arch_info = calloc(num_regs, sizeof(struct embeddedice_reg));
 
        /* fill in values for the reg cache */
@@ -312,7 +312,7 @@ int embeddedice_setup(target_t *target)
         */
        if (arm7_9->has_monitor_mode)
        {
-               reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
+               struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
 
                embeddedice_read_reg(dbg_ctrl);
                if ((retval = jtag_execute_queue()) != ERROR_OK)
@@ -328,7 +328,7 @@ int embeddedice_setup(target_t *target)
  * optionally checking the value read.
  * Note that at this level, all registers are 32 bits wide.
  */
-int embeddedice_read_reg_w_check(reg_t *reg,
+int embeddedice_read_reg_w_check(struct reg *reg,
                uint8_t *check_value, uint8_t *check_mask)
 {
        struct embeddedice_reg *ice_reg = reg->arch_info;
@@ -449,7 +449,7 @@ int embeddedice_receive(struct arm_jtag *jtag_info, uint32_t *data, uint32_t siz
  * Queue a read for an EmbeddedICE register into the register cache,
  * not checking the value read.
  */
-int embeddedice_read_reg(reg_t *reg)
+int embeddedice_read_reg(struct reg *reg)
 {
        return embeddedice_read_reg_w_check(reg, NULL, NULL);
 }
@@ -458,7 +458,7 @@ int embeddedice_read_reg(reg_t *reg)
  * Queue a write for an EmbeddedICE register, updating the register cache.
  * Uses embeddedice_write_reg().
  */
-void embeddedice_set_reg(reg_t *reg, uint32_t value)
+void embeddedice_set_reg(struct reg *reg, uint32_t value)
 {
        embeddedice_write_reg(reg, value);
 
@@ -472,7 +472,7 @@ void embeddedice_set_reg(reg_t *reg, uint32_t value)
  * Write an EmbeddedICE register, updating the register cache.
  * Uses embeddedice_set_reg(); not queued.
  */
-int embeddedice_set_reg_w_exec(reg_t *reg, uint8_t *buf)
+int embeddedice_set_reg_w_exec(struct reg *reg, uint8_t *buf)
 {
        int retval;
 
@@ -485,7 +485,7 @@ int embeddedice_set_reg_w_exec(reg_t *reg, uint8_t *buf)
 /**
  * Queue a write for an EmbeddedICE register, bypassing the register cache.
  */
-void embeddedice_write_reg(reg_t *reg, uint32_t value)
+void embeddedice_write_reg(struct reg *reg, uint32_t value)
 {
        struct embeddedice_reg *ice_reg = reg->arch_info;
 
@@ -504,7 +504,7 @@ void embeddedice_write_reg(reg_t *reg, uint32_t value)
  * Queue a write for an EmbeddedICE register, using cached value.
  * Uses embeddedice_write_reg().
  */
-void embeddedice_store_reg(reg_t *reg)
+void embeddedice_store_reg(struct reg *reg)
 {
        embeddedice_write_reg(reg, buf_get_u32(reg->value, 0, reg->size));
 }

diff --git a/src/target/embeddedice.h b/src/target/embeddedice.h
index 47ef3d96b9d6160f5a02e07a990b234ed98a81c2..23673f918658dc2f083aa29af1b9f7294f17bcdf 100644 (file)
--- a/src/target/embeddedice.h
+++ b/src/target/embeddedice.h
@@ -98,15 +98,15 @@ struct reg_cache* embeddedice_build_reg_cache(target_t *target,
 
 int embeddedice_setup(target_t *target);
 
-int embeddedice_read_reg(reg_t *reg);
-int embeddedice_read_reg_w_check(reg_t *reg,
+int embeddedice_read_reg(struct reg *reg);
+int embeddedice_read_reg_w_check(struct reg *reg,
                uint8_t* check_value, uint8_t* check_mask);
 
-void embeddedice_write_reg(reg_t *reg, uint32_t value);
-void embeddedice_store_reg(reg_t *reg);
+void embeddedice_write_reg(struct reg *reg, uint32_t value);
+void embeddedice_store_reg(struct reg *reg);
 
-void embeddedice_set_reg(reg_t *reg, uint32_t value);
-int embeddedice_set_reg_w_exec(reg_t *reg, uint8_t *buf);
+void embeddedice_set_reg(struct reg *reg, uint32_t value);
+int embeddedice_set_reg_w_exec(struct reg *reg, uint8_t *buf);
 
 int embeddedice_receive(struct arm_jtag *jtag_info, uint32_t *data, uint32_t size);
 int embeddedice_send(struct arm_jtag *jtag_info, uint32_t *data, uint32_t size);

diff --git a/src/target/etb.c b/src/target/etb.c
index 6f9562abd00e82b384af7447296aa6c0ac51caab..c1c7f4b15b457b334698c53729598eaecd3db45d 100644 (file)
--- a/src/target/etb.c
+++ b/src/target/etb.c
@@ -40,7 +40,7 @@ static char* etb_reg_list[] =
 
 static int etb_reg_arch_type = -1;
 
-static int etb_get_reg(reg_t *reg);
+static int etb_get_reg(struct reg *reg);
 
 static int etb_set_instr(struct etb *etb, uint32_t new_instr)
 {
@@ -94,15 +94,15 @@ static int etb_scann(struct etb *etb, uint32_t new_scan_chain)
        return ERROR_OK;
 }
 
-static int etb_read_reg_w_check(reg_t *, uint8_t *, uint8_t *);
-static int etb_set_reg_w_exec(reg_t *, uint8_t *);
+static int etb_read_reg_w_check(struct reg *, uint8_t *, uint8_t *);
+static int etb_set_reg_w_exec(struct reg *, uint8_t *);
 
-static int etb_read_reg(reg_t *reg)
+static int etb_read_reg(struct reg *reg)
 {
        return etb_read_reg_w_check(reg, NULL, NULL);
 }
 
-static int etb_get_reg(reg_t *reg)
+static int etb_get_reg(struct reg *reg)
 {
        int retval;
 
@@ -124,7 +124,7 @@ static int etb_get_reg(reg_t *reg)
 struct reg_cache* etb_build_reg_cache(struct etb *etb)
 {
        struct reg_cache *reg_cache = malloc(sizeof(struct reg_cache));
-       reg_t *reg_list = NULL;
+       struct reg *reg_list = NULL;
        struct etb_reg *arch_info = NULL;
        int num_regs = 9;
        int i;
@@ -134,7 +134,7 @@ struct reg_cache* etb_build_reg_cache(struct etb *etb)
                etb_reg_arch_type = register_reg_arch_type(etb_get_reg, etb_set_reg_w_exec);
 
        /* the actual registers are kept in two arrays */
-       reg_list = calloc(num_regs, sizeof(reg_t));
+       reg_list = calloc(num_regs, sizeof(struct reg));
        arch_info = calloc(num_regs, sizeof(struct etb_reg));
 
        /* fill in values for the reg cache */
@@ -224,7 +224,7 @@ static int etb_read_ram(struct etb *etb, uint32_t *data, int num_frames)
        return ERROR_OK;
 }
 
-static int etb_read_reg_w_check(reg_t *reg,
+static int etb_read_reg_w_check(struct reg *reg,
                uint8_t* check_value, uint8_t* check_mask)
 {
        struct etb_reg *etb_reg = reg->arch_info;
@@ -278,9 +278,9 @@ static int etb_read_reg_w_check(reg_t *reg,
        return ERROR_OK;
 }
 
-static int etb_write_reg(reg_t *, uint32_t);
+static int etb_write_reg(struct reg *, uint32_t);
 
-static int etb_set_reg(reg_t *reg, uint32_t value)
+static int etb_set_reg(struct reg *reg, uint32_t value)
 {
        int retval;
 
@@ -297,7 +297,7 @@ static int etb_set_reg(reg_t *reg, uint32_t value)
        return ERROR_OK;
 }
 
-static int etb_set_reg_w_exec(reg_t *reg, uint8_t *buf)
+static int etb_set_reg_w_exec(struct reg *reg, uint8_t *buf)
 {
        int retval;
 
@@ -311,7 +311,7 @@ static int etb_set_reg_w_exec(reg_t *reg, uint8_t *buf)
        return ERROR_OK;
 }
 
-static int etb_write_reg(reg_t *reg, uint32_t value)
+static int etb_write_reg(struct reg *reg, uint32_t value)
 {
        struct etb_reg *etb_reg = reg->arch_info;
        uint8_t reg_addr = etb_reg->addr & 0x7f;
@@ -435,8 +435,8 @@ static int etb_init(struct etm_context *etm_ctx)
 static trace_status_t etb_status(struct etm_context *etm_ctx)
 {
        struct etb *etb = etm_ctx->capture_driver_priv;
-       reg_t *control = &etb->reg_cache->reg_list[ETB_CTRL];
-       reg_t *status = &etb->reg_cache->reg_list[ETB_STATUS];
+       struct reg *control = &etb->reg_cache->reg_list[ETB_CTRL];
+       struct reg *status = &etb->reg_cache->reg_list[ETB_STATUS];
        trace_status_t retval = 0;
        int etb_timeout = 100;
 
@@ -671,7 +671,7 @@ static int etb_start_capture(struct etm_context *etm_ctx)
 static int etb_stop_capture(struct etm_context *etm_ctx)
 {
        struct etb *etb = etm_ctx->capture_driver_priv;
-       reg_t *etb_ctrl_reg = &etb->reg_cache->reg_list[ETB_CTRL];
+       struct reg *etb_ctrl_reg = &etb->reg_cache->reg_list[ETB_CTRL];
 
        etb_write_reg(etb_ctrl_reg, 0x0);
        jtag_execute_queue();

diff --git a/src/target/etm.c b/src/target/etm.c
index 667eb5bd1db9b40ff07f737b5fe3b0869324fcfd..0aa1a73911554a8f4fa827d9efe5aea0679d38a2 100644 (file)
--- a/src/target/etm.c
+++ b/src/target/etm.c
@@ -216,12 +216,12 @@ static const struct etm_reg_info etm_outputs[] = {
 
 static int etm_reg_arch_type = -1;
 
-static int etm_get_reg(reg_t *reg);
-static int etm_read_reg_w_check(reg_t *reg,
+static int etm_get_reg(struct reg *reg);
+static int etm_read_reg_w_check(struct reg *reg,
                uint8_t* check_value, uint8_t* check_mask);
 static int etm_register_user_commands(struct command_context_s *cmd_ctx);
-static int etm_set_reg_w_exec(reg_t *reg, uint8_t *buf);
-static int etm_write_reg(reg_t *reg, uint32_t value);
+static int etm_set_reg_w_exec(struct reg *reg, uint8_t *buf);
+static int etm_write_reg(struct reg *reg, uint32_t value);
 
 static command_t *etm_cmd;
 
@@ -229,7 +229,7 @@ static command_t *etm_cmd;
 /* Look up register by ID ... most ETM instances only
  * support a subset of the possible registers.
  */
-static reg_t *etm_reg_lookup(struct etm_context *etm_ctx, unsigned id)
+static struct reg *etm_reg_lookup(struct etm_context *etm_ctx, unsigned id)
 {
        struct reg_cache *cache = etm_ctx->reg_cache;
        int i;
@@ -251,7 +251,7 @@ static void etm_reg_add(unsigned bcd_vers, struct arm_jtag *jtag_info,
                struct reg_cache *cache, struct etm_reg *ereg,
                const struct etm_reg_info *r, unsigned nreg)
 {
-       reg_t *reg = cache->reg_list;
+       struct reg *reg = cache->reg_list;
 
        reg += cache->num_regs;
        ereg += cache->num_regs;
@@ -283,7 +283,7 @@ struct reg_cache *etm_build_reg_cache(target_t *target,
                struct arm_jtag *jtag_info, struct etm_context *etm_ctx)
 {
        struct reg_cache *reg_cache = malloc(sizeof(struct reg_cache));
-       reg_t *reg_list = NULL;
+       struct reg *reg_list = NULL;
        struct etm_reg *arch_info = NULL;
        unsigned bcd_vers, config;
 
@@ -293,7 +293,7 @@ struct reg_cache *etm_build_reg_cache(target_t *target,
                                etm_set_reg_w_exec);
 
        /* the actual registers are kept in two arrays */
-       reg_list = calloc(128, sizeof(reg_t));
+       reg_list = calloc(128, sizeof(struct reg));
        arch_info = calloc(128, sizeof(struct etm_reg));
 
        /* fill in values for the reg cache */
@@ -411,12 +411,12 @@ struct reg_cache *etm_build_reg_cache(target_t *target,
        return reg_cache;
 }
 
-static int etm_read_reg(reg_t *reg)
+static int etm_read_reg(struct reg *reg)
 {
        return etm_read_reg_w_check(reg, NULL, NULL);
 }
 
-static int etm_store_reg(reg_t *reg)
+static int etm_store_reg(struct reg *reg)
 {
        return etm_write_reg(reg, buf_get_u32(reg->value, 0, reg->size));
 }
@@ -427,7 +427,7 @@ int etm_setup(target_t *target)
        uint32_t etm_ctrl_value;
        struct arm *arm = target_to_arm(target);
        struct etm_context *etm_ctx = arm->etm;
-       reg_t *etm_ctrl_reg;
+       struct reg *etm_ctrl_reg;
 
        etm_ctrl_reg = etm_reg_lookup(etm_ctx, ETM_CTRL);
        if (!etm_ctrl_reg)
@@ -467,7 +467,7 @@ int etm_setup(target_t *target)
        return ERROR_OK;
 }
 
-static int etm_get_reg(reg_t *reg)
+static int etm_get_reg(struct reg *reg)
 {
        int retval;
 
@@ -486,7 +486,7 @@ static int etm_get_reg(reg_t *reg)
        return ERROR_OK;
 }
 
-static int etm_read_reg_w_check(reg_t *reg,
+static int etm_read_reg_w_check(struct reg *reg,
                uint8_t* check_value, uint8_t* check_mask)
 {
        struct etm_reg *etm_reg = reg->arch_info;
@@ -542,7 +542,7 @@ static int etm_read_reg_w_check(reg_t *reg,
        return ERROR_OK;
 }
 
-static int etm_set_reg(reg_t *reg, uint32_t value)
+static int etm_set_reg(struct reg *reg, uint32_t value)
 {
        int retval;
 
@@ -559,7 +559,7 @@ static int etm_set_reg(reg_t *reg, uint32_t value)
        return ERROR_OK;
 }
 
-static int etm_set_reg_w_exec(reg_t *reg, uint8_t *buf)
+static int etm_set_reg_w_exec(struct reg *reg, uint8_t *buf)
 {
        int retval;
 
@@ -573,7 +573,7 @@ static int etm_set_reg_w_exec(reg_t *reg, uint8_t *buf)
        return ERROR_OK;
 }
 
-static int etm_write_reg(reg_t *reg, uint32_t value)
+static int etm_write_reg(struct reg *reg, uint32_t value)
 {
        struct etm_reg *etm_reg = reg->arch_info;
        const struct etm_reg_info *r = etm_reg->reg_info;
@@ -1340,7 +1340,7 @@ COMMAND_HANDLER(handle_etm_tracemode_command)
        /* only update ETM_CTRL register if tracemode changed */
        if (etm->tracemode != tracemode)
        {
-               reg_t *etm_ctrl_reg;
+               struct reg *etm_ctrl_reg;
 
                etm_ctrl_reg = etm_reg_lookup(etm, ETM_CTRL);
                if (!etm_ctrl_reg)
@@ -1524,7 +1524,7 @@ COMMAND_HANDLER(handle_etm_info_command)
        target_t *target;
        struct arm *arm;
        struct etm_context *etm;
-       reg_t *etm_sys_config_reg;
+       struct reg *etm_sys_config_reg;
        int max_port_size;
        uint32_t config;
 
@@ -1675,7 +1675,7 @@ COMMAND_HANDLER(handle_etm_status_command)
 
        /* ETM status */
        if (etm->bcd_vers >= 0x11) {
-               reg_t *reg;
+               struct reg *reg;
 
                reg = etm_reg_lookup(etm, ETM_STATUS);
                if (!reg)
@@ -1984,7 +1984,7 @@ COMMAND_HANDLER(handle_etm_start_command)
        target_t *target;
        struct arm *arm;
        struct etm_context *etm_ctx;
-       reg_t *etm_ctrl_reg;
+       struct reg *etm_ctrl_reg;
 
        target = get_current_target(cmd_ctx);
        arm = target_to_arm(target);
@@ -2032,7 +2032,7 @@ COMMAND_HANDLER(handle_etm_stop_command)
        target_t *target;
        struct arm *arm;
        struct etm_context *etm_ctx;
-       reg_t *etm_ctrl_reg;
+       struct reg *etm_ctrl_reg;
 
        target = get_current_target(cmd_ctx);
        arm = target_to_arm(target);

diff --git a/src/target/feroceon.c b/src/target/feroceon.c
index 73292e1077d9105ec9a2bc90a9d73ec7e1b002d3..41769d67f1d9ebeccea84c31e23903f4e75f3781 100644 (file)
--- a/src/target/feroceon.c
+++ b/src/target/feroceon.c
@@ -406,7 +406,7 @@ void feroceon_set_dbgrq(target_t *target)
 {
        struct arm *armv4_5 = target->arch_info;
        struct arm7_9_common *arm7_9 = armv4_5->arch_info;
-       reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
+       struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
 
        buf_set_u32(dbg_ctrl->value, 0, 8, 2);
        embeddedice_store_reg(dbg_ctrl);

diff --git a/src/target/mips32.c b/src/target/mips32.c
index ddc27a66155ae271a5cb32aa22c7f88f8891eb30..c9ef1380efd06de078527ce2590a83105b622486 100644 (file)
--- a/src/target/mips32.c
+++ b/src/target/mips32.c
@@ -88,14 +88,14 @@ struct mips32_core_reg mips32_core_reg_list_arch_info[MIPS32NUMCOREREGS] =
 
 uint8_t mips32_gdb_dummy_fp_value[] = {0, 0, 0, 0};
 
-reg_t mips32_gdb_dummy_fp_reg =
+struct reg mips32_gdb_dummy_fp_reg =
 {
        "GDB dummy floating-point register", mips32_gdb_dummy_fp_value, 0, 1, 32, NULL, 0, NULL, 0
 };
 
 int mips32_core_reg_arch_type = -1;
 
-int mips32_get_core_reg(reg_t *reg)
+int mips32_get_core_reg(struct reg *reg)
 {
        int retval;
        struct mips32_core_reg *mips32_reg = reg->arch_info;
@@ -112,7 +112,7 @@ int mips32_get_core_reg(reg_t *reg)
        return retval;
 }
 
-int mips32_set_core_reg(reg_t *reg, uint8_t *buf)
+int mips32_set_core_reg(struct reg *reg, uint8_t *buf)
 {
        struct mips32_core_reg *mips32_reg = reg->arch_info;
        target_t *target = mips32_reg->target;
@@ -186,7 +186,7 @@ int mips32_invalidate_core_regs(target_t *target)
        return ERROR_OK;
 }
 
-int mips32_get_gdb_reg_list(target_t *target, reg_t **reg_list[], int *reg_list_size)
+int mips32_get_gdb_reg_list(target_t *target, struct reg **reg_list[], int *reg_list_size)
 {
        /* get pointers to arch-specific information */
        struct mips32_common *mips32 = target->arch_info;
@@ -194,7 +194,7 @@ int mips32_get_gdb_reg_list(target_t *target, reg_t **reg_list[], int *reg_list_
 
        /* include floating point registers */
        *reg_list_size = MIPS32NUMCOREREGS + MIPS32NUMFPREGS;
-       *reg_list = malloc(sizeof(reg_t*) * (*reg_list_size));
+       *reg_list = malloc(sizeof(struct reg*) * (*reg_list_size));
 
        for (i = 0; i < MIPS32NUMCOREREGS; i++)
        {
@@ -279,7 +279,7 @@ struct reg_cache *mips32_build_reg_cache(target_t *target)
        int num_regs = MIPS32NUMCOREREGS;
        struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
        struct reg_cache *cache = malloc(sizeof(struct reg_cache));
-       reg_t *reg_list = malloc(sizeof(reg_t) * num_regs);
+       struct reg *reg_list = malloc(sizeof(struct reg) * num_regs);
        struct mips32_core_reg *arch_info = malloc(sizeof(struct mips32_core_reg) * num_regs);
        int i;
 

diff --git a/src/target/mips32.h b/src/target/mips32.h
index 7cecb7542b62cc4326abbb65339ed3a7a0d18a82..3b4f64273ff05915a4cf8b9f6a5228fc6ffa92a1 100644 (file)
--- a/src/target/mips32.h
+++ b/src/target/mips32.h
@@ -150,6 +150,6 @@ int mips32_register_commands(struct command_context_s *cmd_ctx);
 
 int mips32_invalidate_core_regs(target_t *target);
 int mips32_get_gdb_reg_list(target_t *target,
-               reg_t **reg_list[], int *reg_list_size);
+               struct reg **reg_list[], int *reg_list_size);
 
 #endif /*MIPS32_H*/

diff --git a/src/target/register.c b/src/target/register.c
index c3ad830a55151f123e3eb6183dc9098333c6d0fe..f26835bdea0815e9b5beb0ae4eb39a0745f2242c 100644 (file)
--- a/src/target/register.c
+++ b/src/target/register.c
@@ -30,7 +30,7 @@
 
 struct reg_arch_type *reg_arch_types = NULL;
 
-reg_t* register_get_by_name(struct reg_cache *first,
+struct reg* register_get_by_name(struct reg_cache *first,
                const char *name, bool search_all)
 {
        int i;
@@ -66,7 +66,7 @@ struct reg_cache** register_get_last_cache_p(struct reg_cache **first)
        return cache_p;
 }
 
-int register_reg_arch_type(int (*get)(reg_t *reg), int (*set)(reg_t *reg, uint8_t *buf))
+int register_reg_arch_type(int (*get)(struct reg *reg), int (*set)(struct reg *reg, uint8_t *buf))
 {
        struct reg_arch_type** arch_type_p = &reg_arch_types;
        int id = 0;
@@ -104,12 +104,12 @@ struct reg_arch_type* register_get_arch_type(int id)
        return NULL;
 }
 
-static int register_get_dummy_core_reg(reg_t *reg)
+static int register_get_dummy_core_reg(struct reg *reg)
 {
        return ERROR_OK;
 }
 
-static int register_set_dummy_core_reg(reg_t *reg, uint8_t *buf)
+static int register_set_dummy_core_reg(struct reg *reg, uint8_t *buf)
 {
        reg->dirty = 1;
        reg->valid = 1;
@@ -117,7 +117,7 @@ static int register_set_dummy_core_reg(reg_t *reg, uint8_t *buf)
        return ERROR_OK;
 }
 
-void register_init_dummy(reg_t *reg)
+void register_init_dummy(struct reg *reg)
 {
        static int dummy_arch_type = -1;
        if (dummy_arch_type == -1)

diff --git a/src/target/register.h b/src/target/register.h
index 57342ba395d1322bbf80dc8fe584eb7c6de82b30..ca8866b1e2cece5253ec393eda5adf557a085318 100644 (file)
--- a/src/target/register.h
+++ b/src/target/register.h
@@ -33,7 +33,7 @@ struct bitfield_desc
        int num_bits;
 };
 
-typedef struct reg_s
+struct reg
 {
        char *name;
        void *value;
@@ -44,32 +44,32 @@ typedef struct reg_s
        int num_bitfields;
        void *arch_info;
        int arch_type;
-} reg_t;
+};
 
 struct reg_cache
 {
        char *name;
        struct reg_cache *next;
-       reg_t *reg_list;
+       struct reg *reg_list;
        int num_regs;
 };
 
 struct reg_arch_type
 {
        int id;
-       int (*get)(reg_t *reg);
-       int (*set)(reg_t *reg, uint8_t *buf);
+       int (*get)(struct reg *reg);
+       int (*set)(struct reg *reg, uint8_t *buf);
        struct reg_arch_type *next;
 };
 
-reg_t* register_get_by_name(struct reg_cache *first,
+struct reg* register_get_by_name(struct reg_cache *first,
                const char *name, bool search_all);
 struct reg_cache** register_get_last_cache_p(struct reg_cache **first);
 
-int register_reg_arch_type(int (*get)(reg_t *reg),
-               int (*set)(reg_t *reg, uint8_t *buf));
+int register_reg_arch_type(int (*get)(struct reg *reg),
+               int (*set)(struct reg *reg, uint8_t *buf));
 struct reg_arch_type* register_get_arch_type(int id);
 
-void register_init_dummy(reg_t *reg);
+void register_init_dummy(struct reg *reg);
 
 #endif /* REGISTER_H */

diff --git a/src/target/target.c b/src/target/target.c
index 16497b4527cc07caa9d3ec992367942dc3d731bd..0cba285ba4f6046aab367be680b7bfd4c599ef8a 100644 (file)
--- a/src/target/target.c
+++ b/src/target/target.c
@@ -622,7 +622,7 @@ int target_remove_watchpoint(struct target_s *target,
 }
 
 int target_get_gdb_reg_list(struct target_s *target,
-               struct reg_s **reg_list[], int *reg_list_size)
+               struct reg **reg_list[], int *reg_list_size)
 {
        return target->type->get_gdb_reg_list(target, reg_list, reg_list_size);
 }
@@ -1865,7 +1865,7 @@ int handle_target(void *priv)
 COMMAND_HANDLER(handle_reg_command)
 {
        target_t *target;
-       reg_t *reg = NULL;
+       struct reg *reg = NULL;
        int count = 0;
        char *value;
 
@@ -3042,7 +3042,7 @@ COMMAND_HANDLER(handle_profile_command)
 
        int numSamples = 0;
        /* hopefully it is safe to cache! We want to stop/restart as quickly as possible. */
-       reg_t *reg = register_get_by_name(target->reg_cache, "pc", 1);
+       struct reg *reg = register_get_by_name(target->reg_cache, "pc", 1);
 
        for (;;)
        {

diff --git a/src/target/target.h b/src/target/target.h
index 50e8c624eb4492b545fb119b01b059720a637cfe..b2c908a82c349d9e759bbd9deeb756107084215e 100644 (file)
--- a/src/target/target.h
+++ b/src/target/target.h
@@ -32,7 +32,7 @@
 #include "algorithm.h"
 #include "command.h"
 
-struct reg_s;
+struct reg;
 struct trace;
 struct command_context_s;
 
@@ -339,7 +339,7 @@ int target_remove_watchpoint(struct target_s *target,
  * This routine is a wrapper for target->type->get_gdb_reg_list.
  */
 int target_get_gdb_reg_list(struct target_s *target,
-               struct reg_s **reg_list[], int *reg_list_size);
+               struct reg **reg_list[], int *reg_list_size);
 
 /**
  * Step the target.

diff --git a/src/target/target_type.h b/src/target/target_type.h
index 98d8665e4f530b8f5bf49d9237b63dd1647ad46f..37e438deea41216b0b1e2093deb5176f17a2cdc4 100644 (file)
--- a/src/target/target_type.h
+++ b/src/target/target_type.h
@@ -91,7 +91,7 @@ struct target_type
         * list, however it is after GDB is connected that monitor commands can
         * be run to properly initialize the target
         */
-       int (*get_gdb_reg_list)(struct target_s *target, struct reg_s **reg_list[], int *reg_list_size);
+       int (*get_gdb_reg_list)(struct target_s *target, struct reg **reg_list[], int *reg_list_size);
 
        /* target memory access
        * size: 1 = byte (8bit), 2 = half-word (16bit), 4 = word (32bit)

diff --git a/src/target/xscale.c b/src/target/xscale.c
index 33dd3564183fc21c5ed39bd14ce1bf99cd8d6bd8..e757271a37fb1a7a19442261af70d4d2fcffe1dc 100644 (file)
--- a/src/target/xscale.c
+++ b/src/target/xscale.c
@@ -61,8 +61,8 @@ static int xscale_resume(struct target_s *, int current,
        uint32_t address, int handle_breakpoints, int debug_execution);
 static int xscale_debug_entry(target_t *);
 static int xscale_restore_context(target_t *);
-static int xscale_get_reg(reg_t *reg);
-static int xscale_set_reg(reg_t *reg, uint8_t *buf);
+static int xscale_get_reg(struct reg *reg);
+static int xscale_set_reg(struct reg *reg, uint8_t *buf);
 static int xscale_set_breakpoint(struct target_s *, struct breakpoint *);
 static int xscale_set_watchpoint(struct target_s *, struct watchpoint *);
 static int xscale_unset_breakpoint(struct target_s *, struct breakpoint *);
@@ -135,7 +135,7 @@ static const struct xscale_reg xscale_reg_arch_info[] =
 static int xscale_reg_arch_type = -1;
 
 /* convenience wrapper to access XScale specific registers */
-static int xscale_set_reg_u32(reg_t *reg, uint32_t value)
+static int xscale_set_reg_u32(struct reg *reg, uint32_t value)
 {
        uint8_t buf[4];
 
@@ -1125,7 +1125,7 @@ static int xscale_halt(target_t *target)
 static int xscale_enable_single_step(struct target_s *target, uint32_t next_pc)
 {
        struct xscale_common *xscale = target_to_xscale(target);
-       reg_t *ibcr0 = &xscale->reg_cache->reg_list[XSCALE_IBCR0];
+       struct reg *ibcr0 = &xscale->reg_cache->reg_list[XSCALE_IBCR0];
        int retval;
 
        if (xscale->ibcr0_used)
@@ -1152,7 +1152,7 @@ static int xscale_enable_single_step(struct target_s *target, uint32_t next_pc)
 static int xscale_disable_single_step(struct target_s *target)
 {
        struct xscale_common *xscale = target_to_xscale(target);
-       reg_t *ibcr0 = &xscale->reg_cache->reg_list[XSCALE_IBCR0];
+       struct reg *ibcr0 = &xscale->reg_cache->reg_list[XSCALE_IBCR0];
        int retval;
 
        if ((retval = xscale_set_reg_u32(ibcr0, 0x0)) != ERROR_OK)
@@ -2230,7 +2230,7 @@ static int xscale_set_watchpoint(struct target_s *target,
 {
        struct xscale_common *xscale = target_to_xscale(target);
        uint8_t enable = 0;
-       reg_t *dbcon = &xscale->reg_cache->reg_list[XSCALE_DBCON];
+       struct reg *dbcon = &xscale->reg_cache->reg_list[XSCALE_DBCON];
        uint32_t dbcon_value = buf_get_u32(dbcon->value, 0, 32);
 
        if (target->state != TARGET_HALTED)
@@ -2311,7 +2311,7 @@ static int xscale_unset_watchpoint(struct target_s *target,
                struct watchpoint *watchpoint)
 {
        struct xscale_common *xscale = target_to_xscale(target);
-       reg_t *dbcon = &xscale->reg_cache->reg_list[XSCALE_DBCON];
+       struct reg *dbcon = &xscale->reg_cache->reg_list[XSCALE_DBCON];
        uint32_t dbcon_value = buf_get_u32(dbcon->value, 0, 32);
 
        if (target->state != TARGET_HALTED)
@@ -2363,7 +2363,7 @@ static int xscale_remove_watchpoint(struct target_s *target, struct watchpoint *
        return ERROR_OK;
 }
 
-static int xscale_get_reg(reg_t *reg)
+static int xscale_get_reg(struct reg *reg)
 {
        struct xscale_reg *arch_info = reg->arch_info;
        target_t *target = arch_info->target;
@@ -2408,7 +2408,7 @@ static int xscale_get_reg(reg_t *reg)
        return ERROR_OK;
 }
 
-static int xscale_set_reg(reg_t *reg, uint8_t* buf)
+static int xscale_set_reg(struct reg *reg, uint8_t* buf)
 {
        struct xscale_reg *arch_info = reg->arch_info;
        target_t *target = arch_info->target;
@@ -2455,7 +2455,7 @@ static int xscale_set_reg(reg_t *reg, uint8_t* buf)
 static int xscale_write_dcsr_sw(target_t *target, uint32_t value)
 {
        struct xscale_common *xscale = target_to_xscale(target);
-       reg_t *dcsr = &xscale->reg_cache->reg_list[XSCALE_DCSR];
+       struct reg *dcsr = &xscale->reg_cache->reg_list[XSCALE_DCSR];
        struct xscale_reg *dcsr_arch_info = dcsr->arch_info;
 
        /* send CP write request (command 0x41) */
@@ -2839,7 +2839,7 @@ static void xscale_build_reg_cache(target_t *target)
        /* fill in values for the xscale reg cache */
        (*cache_p)->name = "XScale registers";
        (*cache_p)->next = NULL;
-       (*cache_p)->reg_list = malloc(num_regs * sizeof(reg_t));
+       (*cache_p)->reg_list = malloc(num_regs * sizeof(struct reg));
        (*cache_p)->num_regs = num_regs;
 
        for (i = 0; i < num_regs; i++)
@@ -3503,7 +3503,7 @@ COMMAND_HANDLER(xscale_handle_cp15)
                return ERROR_OK;
        }
        uint32_t reg_no = 0;
-       reg_t *reg = NULL;
+       struct reg *reg = NULL;
        if (argc > 0)
        {
                COMMAND_PARSE_NUMBER(u32, args[0], reg_no);