while ((!((status = at91sam7_get_flash_status(bank,flashplane)) & waitbits)) && (timeout-- > 0))
{
LOG_DEBUG("status[%i]: 0x%x", flashplane, status);
- usleep(1000);
+ alive_sleep(1);
}
LOG_DEBUG("status[%i]: 0x%x", flashplane, status);
while ((!((status = cfi_get_u8(bank, 0, 0x0)) & 0x80)) && (timeout-- > 0))
{
LOG_DEBUG("status: 0x%x", status);
- usleep(1000);
+ alive_sleep(1);
}
/* mask out bit 0 (reserved) */
}
oldstatus = status;
- usleep(1000);
+ alive_sleep(1);
} while (timeout-- > 0);
LOG_ERROR("timeout, status: 0x%x", status);
target_t *target = bank->target;
do
{
- usleep(1000);
+ alive_sleep(1);
timeout--;
target_read_u32(target, F_STAT, &status);
}while (((status & FS_DONE) == 0) && timeout);
return 1;
}
- usleep(1000);
+ alive_sleep(1);
} while (timeout-- > 0);
return 0;
return 1;
}
- usleep(1000);
+ alive_sleep(1);
} while (timeout-- > 0);
return 0;
/* Send read status command */
device->controller->command(device, NAND_CMD_STATUS);
- usleep(1000);
+ alive_sleep(1);
/* read status */
if (device->device->options & NAND_BUSWIDTH_16)
if (status & S3C2410_NFSTAT_BUSY)
return 1;
- usleep(1000);
+ alive_sleep(1);
} while (timeout-- > 0);
return 0;
if (status & S3C2440_NFSTAT_READY)
return 1;
- usleep(1000);
+ alive_sleep(1);
} while (timeout-- > 0);
while (((status = stellaris_get_flash_status(bank)) & waitbits) && (timeout-- > 0))
{
LOG_DEBUG("status: 0x%x", status);
- usleep(1000);
+ alive_sleep(1);
}
/* Flash errors are reflected in the FLASH_CRIS register */
while (((status = stm32x_get_flash_status(bank)) & FLASH_BSY) && (timeout-- > 0))
{
LOG_DEBUG("status: 0x%x", status);
- usleep(1000);
+ alive_sleep(1);
}
return status;
target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), cmd);
while (((retval = str7x_status(bank)) & str7x_info->busy_bits)){
- usleep(1000);
+ alive_sleep(1);
}
retval = str7x_result(bank);
target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), cmd);
while (((retval = str7x_status(bank)) & str7x_info->busy_bits)){
- usleep(1000);
+ alive_sleep(1);
}
retval = str7x_result(bank);
while (((retval = str7x_status(bank)) & str7x_info->busy_bits))
{
- usleep(1000);
+ alive_sleep(1);
}
retval = str7x_result(bank);
while (((retval = str7x_status(bank)) & str7x_info->busy_bits))
{
- usleep(1000);
+ alive_sleep(1);
}
retval = str7x_result(bank);
}
if( status & 0x80 )
break;
- usleep(1000);
+ alive_sleep(1);
}
/* clear status, also clear read array */
target_read_u8(target, bank_adr, &status);
if( status & 0x80 )
break;
- usleep(1000);
+ alive_sleep(1);
}
/* clear status reg and read array */
target_read_u8(target, bank_adr, &status);
if( status & 0x80 )
break;
- usleep(1000);
+ alive_sleep(1);
}
/* clear status reg and read array */
/* wait for erase completion */
while (!((status = str9xpec_isc_status(chain_pos)) & ISC_STATUS_BUSY)) {
- usleep(1000);
+ alive_sleep(1);
}
free(buffer);
do
{
target_read_u32(target, 0xFFE8A814, &fmbptr);
- usleep(1000);
+ alive_sleep(1);
}
while (!(fmbptr & 0x0200));
target_read_u32(target, 0xFFE8BC0C, &fmmstat);
if (fmmstat & 0x0100)
{
- usleep(1000);
+ alive_sleep(1);
}
}
while (fmmstat & 0x0100);
target_read_u32(target, 0xFFE8BC0C, &fmmstat);
if (fmmstat & 0x0100)
{
- usleep(1000);
+ alive_sleep(1);
}
}
while (fmmstat & 0x0100);