Second phase of changing the directory that starts Cortex, with one that starts CORTEX.

git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@1253 1d2547de-c912-0410-9cb9-b8ca96c0e9e2

diff --git a/Demo/CORTEX_STM32L152_IAR/FreeRTOSConfig.h b/Demo/CORTEX_STM32L152_IAR/FreeRTOSConfig.h
new file mode 100644 (file)
index 0000000..74acd46
--- /dev/null
+++ b/Demo/CORTEX_STM32L152_IAR/FreeRTOSConfig.h
@@ -0,0 +1,136 @@
+/*\r
+    FreeRTOS V6.1.0 - Copyright (C) 2010 Real Time Engineers Ltd.\r
+\r
+    ***************************************************************************\r
+    *                                                                         *\r
+    * If you are:                                                             *\r
+    *                                                                         *\r
+    *    + New to FreeRTOS,                                                   *\r
+    *    + Wanting to learn FreeRTOS or multitasking in general quickly       *\r
+    *    + Looking for basic training,                                        *\r
+    *    + Wanting to improve your FreeRTOS skills and productivity           *\r
+    *                                                                         *\r
+    * then take a look at the FreeRTOS books - available as PDF or paperback  *\r
+    *                                                                         *\r
+    *        "Using the FreeRTOS Real Time Kernel - a Practical Guide"        *\r
+    *                  http://www.FreeRTOS.org/Documentation                  *\r
+    *                                                                         *\r
+    * A pdf reference manual is also available.  Both are usually delivered   *\r
+    * to your inbox within 20 minutes to two hours when purchased between 8am *\r
+    * and 8pm GMT (although please allow up to 24 hours in case of            *\r
+    * exceptional circumstances).  Thank you for your support!                *\r
+    *                                                                         *\r
+    ***************************************************************************\r
+\r
+    This file is part of the FreeRTOS distribution.\r
+\r
+    FreeRTOS is free software; you can redistribute it and/or modify it under\r
+    the terms of the GNU General Public License (version 2) as published by the\r
+    Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+    ***NOTE*** The exception to the GPL is included to allow you to distribute\r
+    a combined work that includes FreeRTOS without being obliged to provide the\r
+    source code for proprietary components outside of the FreeRTOS kernel.\r
+    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT\r
+    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\r
+    FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\r
+    more details. You should have received a copy of the GNU General Public\r
+    License and the FreeRTOS license exception along with FreeRTOS; if not it\r
+    can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
+    by writing to Richard Barry, contact details for whom are available on the\r
+    FreeRTOS WEB site.\r
+\r
+    1 tab == 4 spaces!\r
+\r
+    http://www.FreeRTOS.org - Documentation, latest information, license and\r
+    contact details.\r
+\r
+    http://www.SafeRTOS.com - A version that is certified for use in safety\r
+    critical systems.\r
+\r
+    http://www.OpenRTOS.com - Commercial support, development, porting,\r
+    licensing and training services.\r
+*/\r
+\r
+#ifndef FREERTOS_CONFIG_H\r
+#define FREERTOS_CONFIG_H\r
+\r
+/*-----------------------------------------------------------\r
+ * Application specific definitions.\r
+ *\r
+ * These definitions should be adjusted for your particular hardware and\r
+ * application requirements.\r
+ *\r
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE\r
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.\r
+ *\r
+ * See http://www.freertos.org/a00110.html.\r
+ *----------------------------------------------------------*/\r
+\r
+#define configUSE_PREEMPTION                   1\r
+#define configUSE_IDLE_HOOK                            1\r
+#define configUSE_TICK_HOOK                            1\r
+#define configCPU_CLOCK_HZ                             ( 32000000UL )  \r
+#define configTICK_RATE_HZ                             ( ( portTickType ) 1000 )\r
+#define configMAX_PRIORITIES                   ( ( unsigned portBASE_TYPE ) 5 )\r
+#define configMINIMAL_STACK_SIZE               ( ( unsigned short ) 70 )\r
+#define configTOTAL_HEAP_SIZE                  ( ( size_t ) ( 10 * 1024 ) )\r
+#define configMAX_TASK_NAME_LEN                        ( 16 )\r
+#define configUSE_TRACE_FACILITY               0\r
+#define configUSE_16_BIT_TICKS                 0\r
+#define configIDLE_SHOULD_YIELD                        1\r
+#define configUSE_MUTEXES                              1\r
+#define configQUEUE_REGISTRY_SIZE              5\r
+#define configGENERATE_RUN_TIME_STATS  1\r
+#define configCHECK_FOR_STACK_OVERFLOW 2\r
+#define configUSE_RECURSIVE_MUTEXES            0\r
+#define configUSE_MALLOC_FAILED_HOOK   1\r
+#define configUSE_APPLICATION_TASK_TAG 0\r
+\r
+/* Co-routine definitions. */\r
+#define configUSE_CO_ROUTINES          0\r
+#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )\r
+\r
+/* Set the following definitions to 1 to include the API function, or zero\r
+to exclude the API function. */\r
+\r
+#define INCLUDE_vTaskPrioritySet               1\r
+#define INCLUDE_uxTaskPriorityGet              1\r
+#define INCLUDE_vTaskDelete                            1\r
+#define INCLUDE_vTaskCleanUpResources  0\r
+#define INCLUDE_vTaskSuspend                   1\r
+#define INCLUDE_vTaskDelayUntil                        1\r
+#define INCLUDE_vTaskDelay                             1\r
+\r
+/* Use the system definition, if there is one */\r
+#ifdef __NVIC_PRIO_BITS\r
+       #define configPRIO_BITS       __NVIC_PRIO_BITS\r
+#else\r
+       #define configPRIO_BITS       4        /* 15 priority levels */\r
+#endif\r
+\r
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY                        15\r
+#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY   5\r
+\r
+/* The lowest priority. */\r
+#define configKERNEL_INTERRUPT_PRIORITY        ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )\r
+/* Priority 5, or 160 as only the top three bits are implemented. */\r
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY   ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )\r
+\r
+/* Prevent the following definitions being included when FreeRTOSConfig.h\r
+is included from an asm file. */\r
+#ifdef __ICCARM__\r
+       #include "stm32l1xx_tim.h"\r
+       extern void vConfigureTimerForRunTimeStats( void );\r
+       extern unsigned long ulTIM6_OverflowCount;\r
+#endif /* __ICCARM__ */\r
+\r
+#define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() vConfigureTimerForRunTimeStats()\r
+#define portALT_GET_RUN_TIME_COUNTER_VALUE( ulCountValue )                                                                     \\r
+       {                                                                                                                                                                               \\r
+               TIM_Cmd( TIM6, DISABLE );                                                                                                                       \\r
+               ulCountValue = ( ( ulTIM6_OverflowCount << 16UL ) | ( unsigned long ) TIM6->CNT );      \\r
+               TIM_Cmd( TIM6, ENABLE );                                                                                                                        \\r
+       }\r
+\r
+#endif /* FREERTOS_CONFIG_H */\r
+\r

diff --git a/Demo/CORTEX_STM32L152_IAR/ParTest.c b/Demo/CORTEX_STM32L152_IAR/ParTest.c
new file mode 100644 (file)
index 0000000..53353d6
--- /dev/null
+++ b/Demo/CORTEX_STM32L152_IAR/ParTest.c
@@ -0,0 +1,149 @@
+/*\r
+    FreeRTOS V6.1.0 - Copyright (C) 2010 Real Time Engineers Ltd.\r
+\r
+    ***************************************************************************\r
+    *                                                                         *\r
+    * If you are:                                                             *\r
+    *                                                                         *\r
+    *    + New to FreeRTOS,                                                   *\r
+    *    + Wanting to learn FreeRTOS or multitasking in general quickly       *\r
+    *    + Looking for basic training,                                        *\r
+    *    + Wanting to improve your FreeRTOS skills and productivity           *\r
+    *                                                                         *\r
+    * then take a look at the FreeRTOS books - available as PDF or paperback  *\r
+    *                                                                         *\r
+    *        "Using the FreeRTOS Real Time Kernel - a Practical Guide"        *\r
+    *                  http://www.FreeRTOS.org/Documentation                  *\r
+    *                                                                         *\r
+    * A pdf reference manual is also available.  Both are usually delivered   *\r
+    * to your inbox within 20 minutes to two hours when purchased between 8am *\r
+    * and 8pm GMT (although please allow up to 24 hours in case of            *\r
+    * exceptional circumstances).  Thank you for your support!                *\r
+    *                                                                         *\r
+    ***************************************************************************\r
+\r
+    This file is part of the FreeRTOS distribution.\r
+\r
+    FreeRTOS is free software; you can redistribute it and/or modify it under\r
+    the terms of the GNU General Public License (version 2) as published by the\r
+    Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+    ***NOTE*** The exception to the GPL is included to allow you to distribute\r
+    a combined work that includes FreeRTOS without being obliged to provide the\r
+    source code for proprietary components outside of the FreeRTOS kernel.\r
+    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT\r
+    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\r
+    FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\r
+    more details. You should have received a copy of the GNU General Public\r
+    License and the FreeRTOS license exception along with FreeRTOS; if not it\r
+    can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
+    by writing to Richard Barry, contact details for whom are available on the\r
+    FreeRTOS WEB site.\r
+\r
+    1 tab == 4 spaces!\r
+\r
+    http://www.FreeRTOS.org - Documentation, latest information, license and\r
+    contact details.\r
+\r
+    http://www.SafeRTOS.com - A version that is certified for use in safety\r
+    critical systems.\r
+\r
+    http://www.OpenRTOS.com - Commercial support, development, porting,\r
+    licensing and training services.\r
+*/\r
+\r
+/*-----------------------------------------------------------\r
+ * Simple parallel port IO routines.\r
+ *-----------------------------------------------------------*/\r
+\r
+/* Kernel includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/* ST library functions. */\r
+#include "stm32l152_eval.h"\r
+\r
+#define partstMAX_OUTPUT_LED 4\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestInitialise( void )\r
+{\r
+       /* Configure the output LEDs.   Note that JP18 and JP19 must be closed on\r
+       the Eval board for LED3 and LED4 to work. */\r
+       STM_EVAL_LEDInit( LED1 );\r
+       STM_EVAL_LEDInit( LED2 );\r
+       STM_EVAL_LEDInit( LED3 );\r
+       STM_EVAL_LEDInit( LED4 );\r
+       STM_EVAL_LEDOff( LED1 );\r
+       STM_EVAL_LEDOff( LED2 );\r
+       STM_EVAL_LEDOff( LED3 );\r
+       STM_EVAL_LEDOff( LED4 );        \r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue )\r
+{\r
+       vTaskSuspendAll();\r
+       {\r
+               if( xValue != pdFALSE )\r
+               {\r
+                       switch( uxLED )\r
+                       {\r
+                               case 0: STM_EVAL_LEDOn( LED1 );\r
+                                               break;\r
+       \r
+                               case 1: STM_EVAL_LEDOn( LED2 );\r
+                                               break;\r
+       \r
+                               case 2: STM_EVAL_LEDOn( LED3 );\r
+                                               break;\r
+       \r
+                               case 3: STM_EVAL_LEDOn( LED4 );\r
+                                               break;                                  \r
+                       }\r
+               }\r
+               else\r
+               {\r
+                       switch( uxLED )\r
+                       {\r
+                               case 0: STM_EVAL_LEDOff( LED1 );\r
+                                               break;\r
+       \r
+                               case 1: STM_EVAL_LEDOff( LED2 );\r
+                                               break;\r
+       \r
+                               case 2: STM_EVAL_LEDOff( LED3 );\r
+                                               break;\r
+       \r
+                               case 3: STM_EVAL_LEDOff( LED4 );\r
+                                               break;                                  \r
+                       }\r
+               }\r
+       }\r
+       xTaskResumeAll();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestToggleLED( unsigned portBASE_TYPE uxLED )\r
+{\r
+       vTaskSuspendAll();\r
+       {\r
+               switch( uxLED )\r
+               {\r
+                       case 0: STM_EVAL_LEDToggle( LED1 );\r
+                                       break;\r
+\r
+                       case 1: STM_EVAL_LEDToggle( LED2 );\r
+                                       break;\r
+\r
+                       case 2: STM_EVAL_LEDToggle( LED3 );\r
+                                       break;\r
+\r
+                       case 3: STM_EVAL_LEDToggle( LED4 );\r
+                                       break;                                  \r
+               }\r
+       }\r
+       xTaskResumeAll();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r

diff --git a/Demo/CORTEX_STM32L152_IAR/RTOSDemo.ewd b/Demo/CORTEX_STM32L152_IAR/RTOSDemo.ewd
new file mode 100644 (file)
index 0000000..9155522
--- /dev/null
+++ b/Demo/CORTEX_STM32L152_IAR/RTOSDemo.ewd
@@ -0,0 +1,1683 @@
+<?xml version="1.0" encoding="iso-8859-1"?>\r
+\r
+<project>\r
+  <fileVersion>2</fileVersion>\r
+  <configuration>\r
+    <name>Debug</name>\r
+    <toolchain>\r
+      <name>ARM</name>\r
+    </toolchain>\r
+    <debug>1</debug>\r
+    <settings>\r
+      <name>C-SPY</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>22</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>CInput</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CEndian</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CProcessor</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>OCVariant</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>MacOverride</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>MacFile</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>MemOverride</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>MemFile</name>\r
+          <state>$TOOLKIT_DIR$\CONFIG\debugger\ST\iostm32l152xx.ddf</state>\r
+        </option>\r
+        <option>\r
+          <name>RunToEnable</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>RunToName</name>\r
+          <state>main</state>\r
+        </option>\r
+        <option>\r
+          <name>CExtraOptionsCheck</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CExtraOptions</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>CFpuProcessor</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>OCDDFArgumentProducer</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>OCDownloadSuppressDownload</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCDownloadVerifyAll</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCProductVersion</name>\r
+          <state>6.10.1.52170</state>\r
+        </option>\r
+        <option>\r
+          <name>OCDynDriverList</name>\r
+          <state>JLINK_ID</state>\r
+        </option>\r
+        <option>\r
+          <name>OCLastSavedByProductVersion</name>\r
+          <state>6.10.1.52170</state>\r
+        </option>\r
+        <option>\r
+          <name>OCDownloadAttachToProgram</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>UseFlashLoader</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CLowLevel</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>OCBE8Slave</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>MacFile2</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>CDevice</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>FlashLoadersV3</name>\r
+          <state>$TOOLKIT_DIR$\config\flashloader\ST\FlashSTM32L15xxB.board</state>\r
+        </option>\r
+        <option>\r
+          <name>OCImagesSuppressCheck1</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCImagesPath1</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>OCImagesSuppressCheck2</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCImagesPath2</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>OCImagesSuppressCheck3</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCImagesPath3</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>OverrideDefFlashBoard</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCImagesOffset1</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>OCImagesOffset2</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>OCImagesOffset3</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>OCImagesUse1</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCImagesUse2</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCImagesUse3</name>\r
+          <state>0</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>ARMSIM_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>1</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>OCSimDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>OCSimEnablePSP</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCSimPspOverrideConfig</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCSimPspConfigFile</name>\r
+          <state></state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>ANGEL_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>0</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>CCAngelHeartbeat</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CAngelCommunication</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CAngelCommBaud</name>\r
+          <version>0</version>\r
+          <state>3</state>\r
+        </option>\r
+        <option>\r
+          <name>CAngelCommPort</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>ANGELTCPIP</name>\r
+          <state>aaa.bbb.ccc.ddd</state>\r
+        </option>\r
+        <option>\r
+          <name>DoAngelLogfile</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>AngelLogFile</name>\r
+          <state>$PROJ_DIR$\cspycomm.log</state>\r
+        </option>\r
+        <option>\r
+          <name>OCDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>GDBSERVER_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>0</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>OCDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>TCPIP</name>\r
+          <state>aaa.bbb.ccc.ddd</state>\r
+        </option>\r
+        <option>\r
+          <name>DoLogfile</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>LogFile</name>\r
+          <state>$PROJ_DIR$\cspycomm.log</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJTagBreakpointRadio</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJTagDoUpdateBreakpoints</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJTagUpdateBreakpoints</name>\r
+          <state>_call_main</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>IARROM_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>1</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>CRomLogFileCheck</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CRomLogFileEditB</name>\r
+          <state>$PROJ_DIR$\cspycomm.log</state>\r
+        </option>\r
+        <option>\r
+          <name>CRomCommPort</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CRomCommBaud</name>\r
+          <version>0</version>\r
+          <state>7</state>\r
+        </option>\r
+        <option>\r
+          <name>OCDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>JLINK_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>12</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>JLinkSpeed</name>\r
+          <state>32</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkDoLogfile</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkLogFile</name>\r
+          <state>$PROJ_DIR$\cspycomm.log</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkHWResetDelay</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>JLinkInitialSpeed</name>\r
+          <state>32</state>\r
+        </option>\r
+        <option>\r
+          <name>CCDoJlinkMultiTarget</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCScanChainNonARMDevices</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkMultiTarget</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkIRLength</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkCommRadio</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkTCPIP</name>\r
+          <state>aaa.bbb.ccc.ddd</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkSpeedRadioV2</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCUSBDevice</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchReset</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchUndef</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchSWI</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchData</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchPrefetch</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchIRQ</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchFIQ</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkBreakpointRadio</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkDoUpdateBreakpoints</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkUpdateBreakpoints</name>\r
+          <state>_call_main</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkInterfaceRadio</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>OCJLinkAttachSlave</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkResetList</name>\r
+          <version>4</version>\r
+          <state>7</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkInterfaceCmdLine</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCCatchCORERESET</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCCatchMMERR</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCCatchNOCPERR</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCCatchCHRERR</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCCatchSTATERR</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCCatchBUSERR</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCCatchINTERR</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCCatchHARDERR</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCCatchDummy</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCJLinkScriptFile</name>\r
+          <state>1</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>LMIFTDI_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>2</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>OCDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>LmiftdiSpeed</name>\r
+          <state>500</state>\r
+        </option>\r
+        <option>\r
+          <name>CCLmiftdiDoLogfile</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCLmiftdiLogFile</name>\r
+          <state>$PROJ_DIR$\cspycomm.log</state>\r
+        </option>\r
+        <option>\r
+          <name>CCLmiFtdiInterfaceRadio</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCLmiFtdiInterfaceCmdLine</name>\r
+          <state>0</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>MACRAIGOR_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>3</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>jtag</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>EmuSpeed</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>TCPIP</name>\r
+          <state>aaa.bbb.ccc.ddd</state>\r
+        </option>\r
+        <option>\r
+          <name>DoLogfile</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>LogFile</name>\r
+          <state>$PROJ_DIR$\cspycomm.log</state>\r
+        </option>\r
+        <option>\r
+          <name>DoEmuMultiTarget</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>EmuMultiTarget</name>\r
+          <state>0@ARM7TDMI</state>\r
+        </option>\r
+        <option>\r
+          <name>EmuHWReset</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CEmuCommBaud</name>\r
+          <version>0</version>\r
+          <state>4</state>\r
+        </option>\r
+        <option>\r
+          <name>CEmuCommPort</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>jtago</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>UnusedAddr</name>\r
+          <state>0x00800000</state>\r
+        </option>\r
+        <option>\r
+          <name>CCMacraigorHWResetDelay</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>CCJTagBreakpointRadio</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJTagDoUpdateBreakpoints</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJTagUpdateBreakpoints</name>\r
+          <state>_call_main</state>\r
+        </option>\r
+        <option>\r
+          <name>CCMacraigorInterfaceRadio</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCMacraigorInterfaceCmdLine</name>\r
+          <state>0</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>PEMICRO_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>0</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>OCDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>OCPEMicroAttachSlave</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CCPEMicroInterfaceList</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCPEMicroResetDelay</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>CCPEMicroJtagSpeed</name>\r
+          <state>#UNINITIALIZED#</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJPEMicroShowSettings</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>DoLogfile</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>LogFile</name>\r
+          <state>$PROJ_DIR$\cspycomm.log</state>\r
+        </option>\r
+        <option>\r
+          <name>CCPEMicroUSBDevice</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCPEMicroSerialPort</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJPEMicroTCPIPAutoScanNetwork</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CCPEMicroTCPIP</name>\r
+          <state>10.0.0.1</state>\r
+        </option>\r
+        <option>\r
+          <name>CCPEMicroCommCmdLineProducer</name>\r
+          <state>0</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>RDI_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>1</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>CRDIDriverDll</name>\r
+          <state>###Uninitialized###</state>\r
+        </option>\r
+        <option>\r
+          <name>CRDILogFileCheck</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CRDILogFileEdit</name>\r
+          <state>$PROJ_DIR$\cspycomm.log</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDIHWReset</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchReset</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchUndef</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchSWI</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchData</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchPrefetch</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchIRQ</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchFIQ</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDIUseETM</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>STLINK_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>1</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>OCDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CCSTLinkInterfaceRadio</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCSTLinkInterfaceCmdLine</name>\r
+          <state>0</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>THIRDPARTY_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>0</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>CThirdPartyDriverDll</name>\r
+          <state>###Uninitialized###</state>\r
+        </option>\r
+        <option>\r
+          <name>CThirdPartyLogFileCheck</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CThirdPartyLogFileEditB</name>\r
+          <state>$PROJ_DIR$\cspycomm.log</state>\r
+        </option>\r
+        <option>\r
+          <name>OCDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <debuggerPlugins>\r
+      <plugin>\r
+        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file>\r
+        <loadFlag>1</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$TOOLKIT_DIR$\plugins\rtos\PowerPac\PowerPacRTOS.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB6_Plugin.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin</file>\r
+        <loadFlag>1</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$EW_DIR$\common\plugins\FreeRTOS\FreeRTOSPlugin.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$EW_DIR$\common\plugins\OpenRTOS\OpenRTOSPlugin.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$EW_DIR$\common\plugins\Profiling\Profiling.ENU.ewplugin</file>\r
+        <loadFlag>1</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$EW_DIR$\common\plugins\Stack\Stack.ENU.ewplugin</file>\r
+        <loadFlag>1</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin</file>\r
+        <loadFlag>1</loadFlag>\r
+      </plugin>\r
+    </debuggerPlugins>\r
+  </configuration>\r
+  <configuration>\r
+    <name>Release</name>\r
+    <toolchain>\r
+      <name>ARM</name>\r
+    </toolchain>\r
+    <debug>1</debug>\r
+    <settings>\r
+      <name>C-SPY</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>22</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>CInput</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CEndian</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CProcessor</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>OCVariant</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>MacOverride</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>MacFile</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>MemOverride</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>MemFile</name>\r
+          <state>$TOOLKIT_DIR$\CONFIG\debugger\ST\iostm32l152xx.ddf</state>\r
+        </option>\r
+        <option>\r
+          <name>RunToEnable</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>RunToName</name>\r
+          <state>main</state>\r
+        </option>\r
+        <option>\r
+          <name>CExtraOptionsCheck</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CExtraOptions</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>CFpuProcessor</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>OCDDFArgumentProducer</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>OCDownloadSuppressDownload</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCDownloadVerifyAll</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCProductVersion</name>\r
+          <state>6.10.1.52170</state>\r
+        </option>\r
+        <option>\r
+          <name>OCDynDriverList</name>\r
+          <state>JLINK_ID</state>\r
+        </option>\r
+        <option>\r
+          <name>OCLastSavedByProductVersion</name>\r
+          <state>6.10.1.52170</state>\r
+        </option>\r
+        <option>\r
+          <name>OCDownloadAttachToProgram</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>UseFlashLoader</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CLowLevel</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>OCBE8Slave</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>MacFile2</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>CDevice</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>FlashLoadersV3</name>\r
+          <state>$TOOLKIT_DIR$\config\flashloader\ST\FlashSTM32L15xxB.board</state>\r
+        </option>\r
+        <option>\r
+          <name>OCImagesSuppressCheck1</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCImagesPath1</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>OCImagesSuppressCheck2</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCImagesPath2</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>OCImagesSuppressCheck3</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCImagesPath3</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>OverrideDefFlashBoard</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCImagesOffset1</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>OCImagesOffset2</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>OCImagesOffset3</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>OCImagesUse1</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCImagesUse2</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCImagesUse3</name>\r
+          <state>0</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>ARMSIM_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>1</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>OCSimDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>OCSimEnablePSP</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCSimPspOverrideConfig</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCSimPspConfigFile</name>\r
+          <state></state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>ANGEL_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>0</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>CCAngelHeartbeat</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CAngelCommunication</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CAngelCommBaud</name>\r
+          <version>0</version>\r
+          <state>3</state>\r
+        </option>\r
+        <option>\r
+          <name>CAngelCommPort</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>ANGELTCPIP</name>\r
+          <state>aaa.bbb.ccc.ddd</state>\r
+        </option>\r
+        <option>\r
+          <name>DoAngelLogfile</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>AngelLogFile</name>\r
+          <state>$PROJ_DIR$\cspycomm.log</state>\r
+        </option>\r
+        <option>\r
+          <name>OCDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>GDBSERVER_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>0</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>OCDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>TCPIP</name>\r
+          <state>aaa.bbb.ccc.ddd</state>\r
+        </option>\r
+        <option>\r
+          <name>DoLogfile</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>LogFile</name>\r
+          <state>$PROJ_DIR$\cspycomm.log</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJTagBreakpointRadio</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJTagDoUpdateBreakpoints</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJTagUpdateBreakpoints</name>\r
+          <state>_call_main</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>IARROM_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>1</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>CRomLogFileCheck</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CRomLogFileEditB</name>\r
+          <state>$PROJ_DIR$\cspycomm.log</state>\r
+        </option>\r
+        <option>\r
+          <name>CRomCommPort</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CRomCommBaud</name>\r
+          <version>0</version>\r
+          <state>7</state>\r
+        </option>\r
+        <option>\r
+          <name>OCDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>JLINK_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>12</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>JLinkSpeed</name>\r
+          <state>32</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkDoLogfile</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkLogFile</name>\r
+          <state>$PROJ_DIR$\cspycomm.log</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkHWResetDelay</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>JLinkInitialSpeed</name>\r
+          <state>32</state>\r
+        </option>\r
+        <option>\r
+          <name>CCDoJlinkMultiTarget</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCScanChainNonARMDevices</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkMultiTarget</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkIRLength</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkCommRadio</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkTCPIP</name>\r
+          <state>aaa.bbb.ccc.ddd</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkSpeedRadioV2</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCUSBDevice</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchReset</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchUndef</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchSWI</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchData</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchPrefetch</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchIRQ</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchFIQ</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkBreakpointRadio</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkDoUpdateBreakpoints</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkUpdateBreakpoints</name>\r
+          <state>_call_main</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkInterfaceRadio</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>OCJLinkAttachSlave</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkResetList</name>\r
+          <version>4</version>\r
+          <state>7</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkInterfaceCmdLine</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCCatchCORERESET</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCCatchMMERR</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCCatchNOCPERR</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCCatchCHRERR</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCCatchSTATERR</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCCatchBUSERR</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCCatchINTERR</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCCatchHARDERR</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCCatchDummy</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCJLinkScriptFile</name>\r
+          <state>1</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>LMIFTDI_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>2</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>OCDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>LmiftdiSpeed</name>\r
+          <state>500</state>\r
+        </option>\r
+        <option>\r
+          <name>CCLmiftdiDoLogfile</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCLmiftdiLogFile</name>\r
+          <state>$PROJ_DIR$\cspycomm.log</state>\r
+        </option>\r
+        <option>\r
+          <name>CCLmiFtdiInterfaceRadio</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCLmiFtdiInterfaceCmdLine</name>\r
+          <state>0</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>MACRAIGOR_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>3</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>jtag</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>EmuSpeed</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>TCPIP</name>\r
+          <state>aaa.bbb.ccc.ddd</state>\r
+        </option>\r
+        <option>\r
+          <name>DoLogfile</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>LogFile</name>\r
+          <state>$PROJ_DIR$\cspycomm.log</state>\r
+        </option>\r
+        <option>\r
+          <name>DoEmuMultiTarget</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>EmuMultiTarget</name>\r
+          <state>0@ARM7TDMI</state>\r
+        </option>\r
+        <option>\r
+          <name>EmuHWReset</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CEmuCommBaud</name>\r
+          <version>0</version>\r
+          <state>4</state>\r
+        </option>\r
+        <option>\r
+          <name>CEmuCommPort</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>jtago</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>UnusedAddr</name>\r
+          <state>0x00800000</state>\r
+        </option>\r
+        <option>\r
+          <name>CCMacraigorHWResetDelay</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>CCJTagBreakpointRadio</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJTagDoUpdateBreakpoints</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJTagUpdateBreakpoints</name>\r
+          <state>_call_main</state>\r
+        </option>\r
+        <option>\r
+          <name>CCMacraigorInterfaceRadio</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCMacraigorInterfaceCmdLine</name>\r
+          <state>0</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>PEMICRO_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>0</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>OCDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>OCPEMicroAttachSlave</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CCPEMicroInterfaceList</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCPEMicroResetDelay</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>CCPEMicroJtagSpeed</name>\r
+          <state>#UNINITIALIZED#</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJPEMicroShowSettings</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>DoLogfile</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>LogFile</name>\r
+          <state>$PROJ_DIR$\cspycomm.log</state>\r
+        </option>\r
+        <option>\r
+          <name>CCPEMicroUSBDevice</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCPEMicroSerialPort</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJPEMicroTCPIPAutoScanNetwork</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CCPEMicroTCPIP</name>\r
+          <state>10.0.0.1</state>\r
+        </option>\r
+        <option>\r
+          <name>CCPEMicroCommCmdLineProducer</name>\r
+          <state>0</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>RDI_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>1</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>CRDIDriverDll</name>\r
+          <state>###Uninitialized###</state>\r
+        </option>\r
+        <option>\r
+          <name>CRDILogFileCheck</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CRDILogFileEdit</name>\r
+          <state>$PROJ_DIR$\cspycomm.log</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDIHWReset</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchReset</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchUndef</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchSWI</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchData</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchPrefetch</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchIRQ</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchFIQ</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDIUseETM</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>STLINK_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>1</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>OCDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CCSTLinkInterfaceRadio</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCSTLinkInterfaceCmdLine</name>\r
+          <state>0</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>THIRDPARTY_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>0</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>CThirdPartyDriverDll</name>\r
+          <state>###Uninitialized###</state>\r
+        </option>\r
+        <option>\r
+          <name>CThirdPartyLogFileCheck</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CThirdPartyLogFileEditB</name>\r
+          <state>$PROJ_DIR$\cspycomm.log</state>\r
+        </option>\r
+        <option>\r
+          <name>OCDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <debuggerPlugins>\r
+      <plugin>\r
+        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file>\r
+        <loadFlag>1</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$TOOLKIT_DIR$\plugins\rtos\PowerPac\PowerPacRTOS.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB6_Plugin.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin</file>\r
+        <loadFlag>1</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$EW_DIR$\common\plugins\FreeRTOS\FreeRTOSPlugin.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$EW_DIR$\common\plugins\OpenRTOS\OpenRTOSPlugin.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$EW_DIR$\common\plugins\Profiling\Profiling.ENU.ewplugin</file>\r
+        <loadFlag>1</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$EW_DIR$\common\plugins\Stack\Stack.ENU.ewplugin</file>\r
+        <loadFlag>1</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin</file>\r
+        <loadFlag>1</loadFlag>\r
+      </plugin>\r
+    </debuggerPlugins>\r
+  </configuration>\r
+</project>\r
+\r
+\r

diff --git a/Demo/CORTEX_STM32L152_IAR/RTOSDemo.ewp b/Demo/CORTEX_STM32L152_IAR/RTOSDemo.ewp
new file mode 100644 (file)
index 0000000..b875274
--- /dev/null
+++ b/Demo/CORTEX_STM32L152_IAR/RTOSDemo.ewp
@@ -0,0 +1,1838 @@
+<?xml version="1.0" encoding="iso-8859-1"?>\r
+\r
+<project>\r
+  <fileVersion>2</fileVersion>\r
+  <configuration>\r
+    <name>Debug</name>\r
+    <toolchain>\r
+      <name>ARM</name>\r
+    </toolchain>\r
+    <debug>1</debug>\r
+    <settings>\r
+      <name>General</name>\r
+      <archiveVersion>3</archiveVersion>\r
+      <data>\r
+        <version>18</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>ExePath</name>\r
+          <state>Debug\Exe</state>\r
+        </option>\r
+        <option>\r
+          <name>ObjPath</name>\r
+          <state>Debug\Obj</state>\r
+        </option>\r
+        <option>\r
+          <name>ListPath</name>\r
+          <state>Debug\List</state>\r
+        </option>\r
+        <option>\r
+          <name>Variant</name>\r
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+          <state>$TOOLKIT_DIR$\INC\c\DLib_Config_Normal.h</state>\r
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+          <state>$PROJ_DIR$\system_and_ST_code\STM32L152_EVAL</state>\r
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+          <state>$PROJ_DIR$\..\..\Source\include</state>\r
+          <state>$PROJ_DIR$\..\..\Source\portable\IAR\ARM_CM3</state>\r
+          <state>$PROJ_DIR$</state>\r
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+          <state>.text</state>\r
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+          <name>IProcessorMode2</name>\r
+          <state>1</state>\r
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+        <option>\r
+          <name>CCOptLevel</name>\r
+          <state>1</state>\r
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+        <option>\r
+          <name>CCPosIndRwpi</name>\r
+          <state>0</state>\r
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+        <option>\r
+          <name>CCPosIndNoDynInit</name>\r
+          <state>0</state>\r
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+        <option>\r
+          <name>IccLang</name>\r
+          <state>0</state>\r
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+        <option>\r
+          <name>IccCDialect</name>\r
+          <state>1</state>\r
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+        <option>\r
+          <name>IccAllowVLA</name>\r
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+        <option>\r
+          <name>IccCppDialect</name>\r
+          <state>1</state>\r
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+        <option>\r
+          <name>IccRTTI</name>\r
+          <state>1</state>\r
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+        <option>\r
+          <name>IccStaticDestr</name>\r
+          <state>1</state>\r
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+        <option>\r
+          <name>IccRelaxedFpPrecision</name>\r
+          <state>0</state>\r
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+        <option>\r
+          <name>IccCppInlineSemantics</name>\r
+          <state>0</state>\r
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+      </data>\r
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+      <archiveVersion>0</archiveVersion>\r
+      <data>\r
+        <version>0</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
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+      <name>BILINK</name>\r
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+  </configuration>\r
+  <group>\r
+    <name>FreeRTOS_Source</name>\r
+    <group>\r
+      <name>Portable</name>\r
+      <file>\r
+        <name>$PROJ_DIR$\..\..\Source\portable\MemMang\heap_2.c</name>\r
+      </file>\r
+      <file>\r
+        <name>$PROJ_DIR$\..\..\Source\portable\IAR\ARM_CM3\port.c</name>\r
+      </file>\r
+      <file>\r
+        <name>$PROJ_DIR$\..\..\Source\portable\IAR\ARM_CM3\portasm.s</name>\r
+      </file>\r
+    </group>\r
+    <file>\r
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+    </file>\r
+    <file>\r
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+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\system_and_ST_code\STM32L1xx_StdPeriph_Driver\src\stm32l1xx_spi.c</name>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\..\..\Source\tasks.c</name>\r
+    </file>\r
+  </group>\r
+  <group>\r
+    <name>Standard_Demo_Code</name>\r
+    <file>\r
+      <name>$PROJ_DIR$\..\Common\Minimal\comtest.c</name>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\..\Common\Minimal\dynamic.c</name>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\..\Common\Minimal\flash.c</name>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\..\Common\Minimal\GenQTest.c</name>\r
+    </file>\r
+  </group>\r
+  <group>\r
+    <name>System_and_ST_Code</name>\r
+    <group>\r
+      <name>Eval_Board_Library</name>\r
+      <file>\r
+        <name>$PROJ_DIR$\system_and_ST_code\STM32L152_EVAL\stm32l152_eval.c</name>\r
+      </file>\r
+      <file>\r
+        <name>$PROJ_DIR$\system_and_ST_code\STM32L152_EVAL\stm32l152_eval_lcd.c</name>\r
+      </file>\r
+    </group>\r
+    <group>\r
+      <name>Peripheral_Library</name>\r
+      <file>\r
+        <name>$PROJ_DIR$\system_and_ST_code\STM32L1xx_StdPeriph_Driver\src\misc.c</name>\r
+      </file>\r
+      <file>\r
+        <name>$PROJ_DIR$\system_and_ST_code\STM32L1xx_StdPeriph_Driver\src\stm32l1xx_exti.c</name>\r
+      </file>\r
+      <file>\r
+        <name>$PROJ_DIR$\system_and_ST_code\STM32L1xx_StdPeriph_Driver\src\stm32l1xx_gpio.c</name>\r
+      </file>\r
+      <file>\r
+        <name>$PROJ_DIR$\system_and_ST_code\STM32L1xx_StdPeriph_Driver\src\stm32l1xx_pwr.c</name>\r
+      </file>\r
+      <file>\r
+        <name>$PROJ_DIR$\system_and_ST_code\STM32L1xx_StdPeriph_Driver\src\stm32l1xx_rcc.c</name>\r
+      </file>\r
+      <file>\r
+        <name>$PROJ_DIR$\system_and_ST_code\STM32L1xx_StdPeriph_Driver\src\stm32l1xx_syscfg.c</name>\r
+      </file>\r
+      <file>\r
+        <name>$PROJ_DIR$\system_and_ST_code\STM32L1xx_StdPeriph_Driver\src\stm32l1xx_tim.c</name>\r
+      </file>\r
+      <file>\r
+        <name>$PROJ_DIR$\system_and_ST_code\STM32L1xx_StdPeriph_Driver\src\stm32l1xx_usart.c</name>\r
+      </file>\r
+    </group>\r
+    <file>\r
+      <name>$PROJ_DIR$\system_and_ST_code\startup_stm32l1xx_md.s</name>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\system_and_ST_code\stm32l1xx_it.c</name>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\system_and_ST_code\system_stm32l1xx.c</name>\r
+    </file>\r
+  </group>\r
+  <file>\r
+    <name>$PROJ_DIR$\main.c</name>\r
+  </file>\r
+  <file>\r
+    <name>$PROJ_DIR$\ParTest.c</name>\r
+  </file>\r
+  <file>\r
+    <name>$PROJ_DIR$\serial.c</name>\r
+  </file>\r
+</project>\r
+\r
+\r

diff --git a/Demo/CORTEX_STM32L152_IAR/RTOSDemo.eww b/Demo/CORTEX_STM32L152_IAR/RTOSDemo.eww
new file mode 100644 (file)
index 0000000..239a938
--- /dev/null
+++ b/Demo/CORTEX_STM32L152_IAR/RTOSDemo.eww
@@ -0,0 +1,10 @@
+<?xml version="1.0" encoding="iso-8859-1"?>\r
+\r
+<workspace>\r
+  <project>\r
+    <path>$WS_DIR$\RTOSDemo.ewp</path>\r
+  </project>\r
+  <batchBuild/>\r
+</workspace>\r
+\r
+\r

diff --git a/Demo/CORTEX_STM32L152_IAR/main.c b/Demo/CORTEX_STM32L152_IAR/main.c
new file mode 100644 (file)
index 0000000..694a8c3
--- /dev/null
+++ b/Demo/CORTEX_STM32L152_IAR/main.c
@@ -0,0 +1,599 @@
+/*\r
+    FreeRTOS V6.1.0 - Copyright (C) 2010 Real Time Engineers Ltd.\r
+\r
+    ***************************************************************************\r
+    *                                                                         *\r
+    * If you are:                                                             *\r
+    *                                                                         *\r
+    *    + New to FreeRTOS,                                                   *\r
+    *    + Wanting to learn FreeRTOS or multitasking in general quickly       *\r
+    *    + Looking for basic training,                                        *\r
+    *    + Wanting to improve your FreeRTOS skills and productivity           *\r
+    *                                                                         *\r
+    * then take a look at the FreeRTOS books - available as PDF or paperback  *\r
+    *                                                                         *\r
+    *        "Using the FreeRTOS Real Time Kernel - a Practical Guide"        *\r
+    *                  http://www.FreeRTOS.org/Documentation                  *\r
+    *                                                                         *\r
+    * A pdf reference manual is also available.  Both are usually delivered   *\r
+    * to your inbox within 20 minutes to two hours when purchased between 8am *\r
+    * and 8pm GMT (although please allow up to 24 hours in case of            *\r
+    * exceptional circumstances).  Thank you for your support!                *\r
+    *                                                                         *\r
+    ***************************************************************************\r
+\r
+    This file is part of the FreeRTOS distribution.\r
+\r
+    FreeRTOS is free software; you can redistribute it and/or modify it under\r
+    the terms of the GNU General Public License (version 2) as published by the\r
+    Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+    ***NOTE*** The exception to the GPL is included to allow you to distribute\r
+    a combined work that includes FreeRTOS without being obliged to provide the\r
+    source code for proprietary components outside of the FreeRTOS kernel.\r
+    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT\r
+    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\r
+    FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\r
+    more details. You should have received a copy of the GNU General Public\r
+    License and the FreeRTOS license exception along with FreeRTOS; if not it\r
+    can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
+    by writing to Richard Barry, contact details for whom are available on the\r
+    FreeRTOS WEB site.\r
+\r
+    1 tab == 4 spaces!\r
+\r
+    http://www.FreeRTOS.org - Documentation, latest information, license and\r
+    contact details.\r
+\r
+    http://www.SafeRTOS.com - A version that is certified for use in safety\r
+    critical systems.\r
+\r
+    http://www.OpenRTOS.com - Commercial support, development, porting,\r
+    licensing and training services.\r
+*/\r
+\r
+/*\r
+ * The documentation page for this demo available on http://www.FreeRTOS.org\r
+ * documents the hardware configuration required to run this demo.  It also\r
+ * provides more information on the expected demo application behaviour.\r
+ *\r
+ * main() creates all the demo application tasks, then starts the scheduler.\r
+ * A lot of the created tasks are from the pool of "standard demo" tasks.  The\r
+ * web documentation provides more details of the standard demo tasks, which\r
+ * provide no particular functionality but do provide good examples of how to\r
+ * use the FreeRTOS API.\r
+ *\r
+ * In addition to the standard demo tasks, the following tasks, interrupts and\r
+ * tests are defined and/or created within this file:\r
+ *\r
+ * "LCD" task - The LCD task is a 'gatekeeper' task.  It is the only task that\r
+ * is permitted to access the LCD and therefore ensures access to the LCD is\r
+ * always serialised and there are no mutual exclusion issues.  When a task or\r
+ * an interrupt wants to write to the LCD, it does not access the LCD directly\r
+ * but instead sends the message to the LCD task.  The LCD task then performs\r
+ * the actual LCD output.  This mechanism also allows interrupts to, in effect,\r
+ * write to the LCD by sending messages to the LCD task.\r
+ *\r
+ * The LCD task is also a demonstration of a 'controller' task design pattern.\r
+ * Some tasks do not actually send a string to the LCD task directly, but\r
+ * instead send a command that is interpreted by the LCD task.  In a normal\r
+ * application these commands can be control values or set points, in this\r
+ * simple example the commands just result in messages being displayed on the\r
+ * LCD.\r
+ *\r
+ * "Button Poll" task - This task polls the state of the 'up' key on the\r
+ * joystick input device.  It uses the vTaskDelay() API function to control\r
+ * the poll rate to ensure debouncing is not necessary and that the task does\r
+ * not use all the available CPU processing time.\r
+ *\r
+ * Button Interrupt and run time stats display - The select button on the\r
+ * joystick input device is configured to generate an external interrupt.  The\r
+ * handler for this interrupt sends a message to LCD task, which interprets the\r
+ * message to mean, firstly write a message to the LCD, and secondly, generate\r
+ * a table of run time statistics.  The run time statistics are displayed as a\r
+ * table that contains information on how much processing time each task has\r
+ * been allocated since the application started to execute.  This information\r
+ * is provided both as an absolute time, and as a percentage of the total run\r
+ * time.  The information is displayed in the terminal IO window of the IAR\r
+ * embedded workbench.  The online documentation for this demo shows a screen\r
+ * shot demonstrating where the run time stats can be viewed.\r
+ *\r
+ * Idle Hook - The idle hook is a function that is called on each iteration of\r
+ * the idle task.  In this case it is used to place the processor into a low\r
+ * power mode.  Note however that this application is implemented using standard\r
+ * components, and is therefore not optimised for low power operation.  Lower\r
+ * power consumption would be achieved by converting polling tasks into event\r
+ * driven tasks, and slowing the tick interrupt frequency.\r
+ *\r
+ * "Check" function called from the tick hook - The tick hook is called during\r
+ * each tick interrupt.  It is called from an interrupt context so must execute\r
+ * quickly, not attempt to block, and not call any FreeRTOS API functions that\r
+ * do not end in "FromISR".  In this case the tick hook executes a 'check'\r
+ * function.  This only executes every five seconds.  Its main function is to\r
+ * check that all the standard demo tasks are still operational.  Each time it\r
+ * executes it sends a status code to the LCD task.  The LCD task interprets the\r
+ * code and displays an appropriate message - which will be PASS if no tasks\r
+ * have reported any errors, or a message stating which task has reported an\r
+ * error.\r
+*/\r
+\r
+/* Standard includes. */\r
+#include <stdio.h>\r
+\r
+/* Kernel includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "queue.h"\r
+\r
+/* Demo application includes. */\r
+#include "partest.h"\r
+#include "flash.h"\r
+#include "dynamic.h"\r
+#include "comtest2.h"\r
+#include "GenQTest.h"\r
+\r
+/* Eval board includes. */\r
+#include "stm32_eval.h"\r
+#include "stm32l152_eval_lcd.h"\r
+\r
+/* The priorities assigned to the tasks. */\r
+#define mainFLASH_TASK_PRIORITY                        ( tskIDLE_PRIORITY + 1 )\r
+#define mainLCD_TASK_PRIORITY                  ( tskIDLE_PRIORITY + 1 )\r
+#define mainCOM_TEST_PRIORITY                  ( tskIDLE_PRIORITY + 2 )\r
+#define mainGENERIC_QUEUE_TEST_PRIORITY        ( tskIDLE_PRIORITY )\r
+\r
+/* The length of the queue (the number of items the queue can hold) that is used\r
+to send messages from tasks and interrupts the the LCD task. */\r
+#define mainQUEUE_LENGTH                               ( 5 )\r
+\r
+/* Codes sent within messages to the LCD task so the LCD task can interpret\r
+exactly what the message it just received was.  These are sent in the\r
+cMessageID member of the message structure (defined below). */\r
+#define mainMESSAGE_BUTTON_UP                  ( 1 )\r
+#define mainMESSAGE_BUTTON_SEL                 ( 2 )\r
+#define mainMESSAGE_STATUS                             ( 3 )\r
+\r
+/* When the cMessageID member of the message sent to the LCD task is\r
+mainMESSAGE_STATUS then these definitions are sent in the lMessageValue member\r
+of the same message and indicate what the status actually is. */\r
+#define mainERROR_DYNAMIC_TASKS                        ( pdPASS + 1 )\r
+#define mainERROR_COM_TEST                             ( pdPASS + 2 )\r
+#define mainERROR_GEN_QUEUE_TEST               ( pdPASS + 3 )\r
+\r
+/* Baud rate used by the comtest tasks. */\r
+#define mainCOM_TEST_BAUD_RATE                 ( 115200 )\r
+\r
+/* The LED used by the comtest tasks. See the comtest.c file for more\r
+information. */\r
+#define mainCOM_TEST_LED                               ( 3 )\r
+\r
+/* The LCD task uses printf() so requires more stack than most of the other\r
+tasks. */\r
+#define mainLCD_TASK_STACK_SIZE                        ( configMINIMAL_STACK_SIZE * 2 )\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * System configuration is performed prior to main() being called, this function\r
+ * configures the peripherals used by the demo application.\r
+ */\r
+static void prvSetupHardware( void );\r
+\r
+/*\r
+ * Definition of the LCD/controller task described in the comments at the top\r
+ * of this file.\r
+ */\r
+static void prvLCDTask( void *pvParameters );\r
+\r
+/*\r
+ * Definition of the button poll task described in the comments at the top of\r
+ * this file.\r
+ */\r
+static void prvButtonPollTask( void *pvParameters );\r
+\r
+/*\r
+ * Converts a status message value into an appropriate string for display on\r
+ * the LCD.  The string is written to pcBuffer.\r
+ */\r
+static void prvGenerateStatusMessage( char *pcBuffer, long lStatusValue );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* The time base for the run time stats is generated by the 16 bit timer 6.\r
+Each time the timer overflows ulTIM6_OverflowCount is incremented.  Therefore,\r
+when converting the total run time to a 32 bit number, the most significant two\r
+bytes are given by ulTIM6_OverflowCount and the least significant two bytes are\r
+given by the current TIM6 counter value.  Care must be taken with data\r
+consistency when combining the two in case a timer overflow occurs as the\r
+value is being read. */\r
+unsigned long ulTIM6_OverflowCount = 0UL;\r
+\r
+/* The handle of the queue used to send messages from tasks and interrupts to\r
+the LCD task. */\r
+static xQueueHandle xLCDQueue = NULL;\r
+\r
+/* The definition of each message sent from tasks and interrupts to the LCD\r
+task. */\r
+typedef struct\r
+{\r
+       char cMessageID;        /* << States what the message is. */\r
+       long lMessageValue; /* << States the message value (can be an integer, string pointer, etc. depending on the value of cMessageID). */\r
+} xQueueMessage;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void main( void )\r
+{\r
+       /* Configure the peripherals used by this demo application.  This includes\r
+       configuring the joystick input select button to generate interrupts. */\r
+       prvSetupHardware();\r
+       \r
+       /* Create the queue used by tasks and interrupts to send strings to the LCD\r
+       task. */\r
+       xLCDQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( xQueueMessage ) );\r
+       \r
+       /* If the queue could not be created then don't create any tasks that might\r
+       attempt to use the queue. */\r
+       if( xLCDQueue != NULL )\r
+       {\r
+               /* Add the created queue to the queue registry so it can be viewed in\r
+               the IAR FreeRTOS state viewer plug-in. */\r
+               vQueueAddToRegistry( xLCDQueue, "LCDQueue" );\r
+               \r
+               /* Create the LCD and button poll tasks, as described at the top of this\r
+               file. */\r
+               xTaskCreate( prvLCDTask, ( signed char * ) "LCD", mainLCD_TASK_STACK_SIZE, NULL, mainLCD_TASK_PRIORITY, NULL );\r
+               xTaskCreate( prvButtonPollTask, ( signed char * ) "ButPoll", configMINIMAL_STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );\r
+               \r
+               /* Create a subset of the standard demo tasks. */\r
+               vStartDynamicPriorityTasks();\r
+               vStartLEDFlashTasks( mainFLASH_TASK_PRIORITY );\r
+               vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainCOM_TEST_BAUD_RATE, mainCOM_TEST_LED );\r
+               vStartGenericQueueTasks( mainGENERIC_QUEUE_TEST_PRIORITY );\r
+               \r
+               /* Start the scheduler. */\r
+               vTaskStartScheduler();\r
+       }\r
+       \r
+       /* If all is well then this line will never be reached.  If it is reached\r
+       then it is likely that there was insufficient (FreeRTOS) heap memory space\r
+       to create the idle task.  This may have been trapped by the malloc() failed\r
+       hook function, if one is configured. */\r
+       for( ;; );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvLCDTask( void *pvParameters )\r
+{\r
+xQueueMessage xReceivedMessage;\r
+long lLine = Line1;\r
+const long lFontHeight = (((sFONT *)LCD_GetFont())->Height);\r
+\r
+/* Buffer into which strings are formatted and placed ready for display on the\r
+LCD.  Note this is a static variable to prevent it being allocated on the task\r
+stack, which is too small to hold such a variable.  The stack size is configured\r
+when the task is created. */\r
+static char cBuffer[ 512 ];\r
+\r
+       /* This function is the only function that uses printf().  If printf() is\r
+       used from any other function then some sort of mutual exclusion on stdout\r
+       will be necessary.\r
+       \r
+       This is also the only function that is permitted to access the LCD.\r
+       \r
+       First print out the number of bytes that remain in the FreeRTOS heap.  This\r
+       can be viewed in the terminal IO window within the IAR Embedded Workbench. */\r
+       printf( "%d bytes of heap space remain unallocated\n", xPortGetFreeHeapSize() );\r
+\r
+       for( ;; )\r
+       {\r
+               /* Wait for a message to be received.  Using portMAX_DELAY as the block\r
+               time will result in an indefinite wait provided INCLUDE_vTaskSuspend is\r
+               set to 1 in FreeRTOSConfig.h, therefore there is no need to check the\r
+               function return value and the function will only return when a value\r
+               has been received. */\r
+               xQueueReceive( xLCDQueue, &xReceivedMessage, portMAX_DELAY );\r
+\r
+               /* Clear the LCD if no room remains for any more text output. */\r
+               if( lLine > Line9 )\r
+               {\r
+                       LCD_Clear( Blue );\r
+                       lLine = 0;\r
+               }\r
+                               \r
+               /* What is this message?  What does it contain? */\r
+               switch( xReceivedMessage.cMessageID )\r
+               {\r
+                       case mainMESSAGE_BUTTON_UP              :       /* The button poll task has just\r
+                                                                                               informed this task that the up\r
+                                                                                               button on the joystick input has\r
+                                                                                               been pressed or released. */\r
+                                                                                               sprintf( cBuffer, "Button up = %d", xReceivedMessage.lMessageValue );\r
+                                                                                               break;\r
+\r
+                       case mainMESSAGE_BUTTON_SEL             :       /* The select button interrupt\r
+                                                                                               just informed this task that the\r
+                                                                                               select button was pressed.\r
+                                                                                               Generate a table of task run time\r
+                                                                                               statistics and output this to\r
+                                                                                               the terminal IO window in the IAR\r
+                                                                                               embedded workbench. */\r
+                                                                                               printf( "\nTask\t     Abs Time\t     %%Time\n*****************************************" );\r
+                                                                                               vTaskGetRunTimeStats( ( signed char * ) cBuffer );\r
+                                                                                               printf( cBuffer );\r
+                                                                                               \r
+                                                                                               /* Also print out a message to\r
+                                                                                               the LCD - in this case the\r
+                                                                                               pointer to the string to print\r
+                                                                                               is sent directly in the\r
+                                                                                               lMessageValue member of the\r
+                                                                                               message.  This just demonstrates\r
+                                                                                               a different communication\r
+                                                                                               technique. */\r
+                                                                                               sprintf( cBuffer, "%s", ( char * ) xReceivedMessage.lMessageValue );\r
+                                                                                               break;\r
+                                                                                               \r
+                       case mainMESSAGE_STATUS                 :       /* The tick interrupt hook\r
+                                                                                               function has just informed this\r
+                                                                                               task of the system status.\r
+                                                                                               Generate a string in accordance\r
+                                                                                               with the status value. */\r
+                                                                                               prvGenerateStatusMessage( cBuffer, xReceivedMessage.lMessageValue );\r
+                                                                                               break;\r
+                                                                                               \r
+                       default                                                 :       sprintf( cBuffer, "Unknown message" );\r
+                                                                                               break;\r
+               }\r
+               \r
+               /* Output the message that was placed into the cBuffer array within the\r
+               switch statement above. */\r
+               LCD_DisplayStringLine( lLine, ( uint8_t * ) cBuffer );\r
+               \r
+               /* Move onto the next LCD line, ready for the next iteration of this\r
+               loop. */\r
+               lLine += lFontHeight;\r
+       }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvGenerateStatusMessage( char *pcBuffer, long lStatusValue )\r
+{\r
+       /* Just a utility function to convert a status value into a meaningful\r
+       string for output onto the LCD. */\r
+       switch( lStatusValue )\r
+       {\r
+               case pdPASS                                             :       sprintf( pcBuffer, "Task status = PASS" );\r
+                                                                                       break;\r
+               case mainERROR_DYNAMIC_TASKS    :       sprintf( pcBuffer, "Error: Dynamic tasks" );\r
+                                                                                       break;\r
+               case mainERROR_COM_TEST                 :       sprintf( pcBuffer, "Err: loop connected?" ); /* Error in COM test - is the Loopback connector connected? */                                                                                                             \r
+                                                                                       break;\r
+               case mainERROR_GEN_QUEUE_TEST   :       sprintf( pcBuffer, "Error: Gen Q test" );\r
+                                                                                       break;\r
+               default                                                 :       sprintf( pcBuffer, "Unknown status" );\r
+                                                                                       break;\r
+       }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void EXTI9_5_IRQHandler( void )\r
+{\r
+/* Define the message sent to the LCD task from this interrupt. */\r
+const xQueueMessage xMessage = { mainMESSAGE_BUTTON_SEL, ( unsigned long ) "Select Interrupt!" };\r
+long lHigherPriorityTaskWoken = pdFALSE;\r
+\r
+       /* This is the interrupt handler for the joystick select button input.\r
+       The button has been pushed, write a message to the LCD via the LCD task. */\r
+       xQueueSendFromISR( xLCDQueue, &xMessage, &lHigherPriorityTaskWoken );\r
+       \r
+       EXTI_ClearITPendingBit( SEL_BUTTON_EXTI_LINE );\r
+       \r
+       /* If writing to xLCDQueue caused a task to unblock, and the unblocked task\r
+       has a priority equal to or above the task that this interrupt interrupted,\r
+       then lHigherPriorityTaskWoken will have been set to pdTRUE internally within\r
+       xQueuesendFromISR(), and portEND_SWITCHING_ISR() will ensure that this\r
+       interrupt returns directly to the higher priority unblocked task. */\r
+       portEND_SWITCHING_ISR( lHigherPriorityTaskWoken );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationTickHook( void )\r
+{\r
+static unsigned long ulCounter = 0;\r
+static const unsigned long ulCheckFrequency = 5000UL / portTICK_RATE_MS;\r
+long lHigherPriorityTaskWoken = pdFALSE;\r
+\r
+/* Define the status message that is sent to the LCD task.  By default the\r
+status is PASS. */\r
+static xQueueMessage xStatusMessage = { mainMESSAGE_STATUS, pdPASS };\r
+\r
+       /* This is called from within the tick interrupt and performs the 'check'\r
+       functionality as described in the comments at the top of this file.\r
+\r
+       Is it time to perform the 'check' functionality again? */\r
+       ulCounter++;\r
+       if( ulCounter >= ulCheckFrequency )\r
+       {\r
+               /* See if the standard demo tasks are executing as expected, changing\r
+               the message that is sent to the LCD task from PASS to an error code if\r
+               any tasks set reports an error. */\r
+               if( xAreDynamicPriorityTasksStillRunning() != pdPASS )\r
+               {\r
+                       xStatusMessage.lMessageValue = mainERROR_DYNAMIC_TASKS;\r
+               }\r
+               \r
+               if( xAreComTestTasksStillRunning() != pdPASS )\r
+               {\r
+                       xStatusMessage.lMessageValue = mainERROR_COM_TEST;\r
+               }\r
+               \r
+               if( xAreGenericQueueTasksStillRunning() != pdPASS )\r
+               {\r
+                       xStatusMessage.lMessageValue = mainERROR_GEN_QUEUE_TEST;\r
+               }\r
+               \r
+               /* As this is the tick hook the lHigherPriorityTaskWoken parameter is not\r
+               needed (a context switch is going to be performed anyway), but it must\r
+               still be provided. */\r
+               xQueueSendFromISR( xLCDQueue, &xStatusMessage, &lHigherPriorityTaskWoken );\r
+               ulCounter = 0;\r
+       }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvButtonPollTask( void *pvParameters )\r
+{\r
+long lLastState = pdTRUE;\r
+long lState;\r
+xQueueMessage xMessage;\r
+\r
+       /* This tasks performs the button polling functionality as described at the\r
+       top of this file. */\r
+       for( ;; )\r
+       {\r
+               /* Check the button state. */\r
+               lState = STM_EVAL_PBGetState( BUTTON_UP );\r
+               if( lState != lLastState )\r
+               {\r
+                       /* The state has changed, send a message to the LCD task. */\r
+                       xMessage.cMessageID = mainMESSAGE_BUTTON_UP;\r
+                       xMessage.lMessageValue = lState;\r
+                       lLastState = lState;\r
+                       xQueueSend( xLCDQueue, &xMessage, portMAX_DELAY );\r
+               }\r
+               \r
+               /* Block for 10 milliseconds so this task does not utilise all the CPU\r
+               time and debouncing of the button is not necessary. */\r
+               vTaskDelay( 10 / portTICK_RATE_MS );\r
+       }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvSetupHardware( void )\r
+{\r
+       /* Ensure that all 4 interrupt priority bits are used as the pre-emption\r
+       priority. */\r
+       NVIC_PriorityGroupConfig( NVIC_PriorityGroup_4 );\r
+       \r
+       /* Initialise the LEDs. */\r
+       vParTestInitialise();\r
+\r
+       /* Initialise the joystick inputs. */\r
+       STM_EVAL_PBInit( BUTTON_UP, BUTTON_MODE_GPIO );\r
+       STM_EVAL_PBInit( BUTTON_DOWN, BUTTON_MODE_GPIO );\r
+       STM_EVAL_PBInit( BUTTON_LEFT, BUTTON_MODE_GPIO );\r
+       STM_EVAL_PBInit( BUTTON_RIGHT, BUTTON_MODE_GPIO );\r
+       \r
+       /* The select button in the middle of the joystick is configured to generate\r
+       an interrupt.  The Eval board library will configure the interrupt\r
+       priority to be the lowest priority available so the priority need not be\r
+       set here explicitly.  It is important that the priority is equal to or\r
+       below that set by the configMAX_SYSCALL_INTERRUPT_PRIORITY value set in\r
+       FreeRTOSConfig.h. */\r
+       STM_EVAL_PBInit( BUTTON_SEL, BUTTON_MODE_EXTI );\r
+\r
+       /* Initialize the LCD */\r
+       STM32L152_LCD_Init();   \r
+       LCD_Clear( Blue );\r
+       LCD_SetBackColor( Blue );\r
+       LCD_SetTextColor( White );\r
+       LCD_DisplayStringLine( Line0, "  www.FreeRTOS.org" );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vConfigureTimerForRunTimeStats( void )\r
+{\r
+TIM_TimeBaseInitTypeDef  TIM_TimeBaseStructure;\r
+NVIC_InitTypeDef NVIC_InitStructure;\r
+\r
+       /* The time base for the run time stats is generated by the 16 bit timer 6.\r
+       Each time the timer overflows ulTIM6_OverflowCount is incremented.\r
+       Therefore, when converting the total run time to a 32 bit number, the most\r
+       significant two bytes are given by ulTIM6_OverflowCount and the least\r
+       significant two bytes are given by the current TIM6 counter value.  Care\r
+       must be taken with data consistency when combining the two in case a timer\r
+       overflow occurs as the value is being read.\r
+       \r
+       The portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() macro (in FreeRTOSConfig.h) is\r
+       defined to call this function, so the kernel will call this function\r
+       automatically at the appropriate time. */\r
+\r
+       /* TIM6 clock enable */\r
+       RCC_APB1PeriphClockCmd( RCC_APB1Periph_TIM6, ENABLE );\r
+\r
+       /* The 32MHz clock divided by 5000 should tick (very) approximately every\r
+       150uS and overflow a 16bit timer (very) approximately every 10 seconds. */\r
+       TIM_TimeBaseStructure.TIM_Period = 65535;\r
+       TIM_TimeBaseStructure.TIM_Prescaler = 5000;\r
+       TIM_TimeBaseStructure.TIM_ClockDivision = TIM_CKD_DIV1;\r
+       TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;\r
+       \r
+       TIM_TimeBaseInit( TIM6, &TIM_TimeBaseStructure );\r
+       \r
+       /* Only interrupt on overflow events. */\r
+       TIM6->CR1 |= TIM_CR1_URS;\r
+       \r
+       /* Enable the interrupt. */\r
+       TIM_ITConfig( TIM6, TIM_IT_Update, ENABLE );\r
+       \r
+       /* Enable the TIM6 global Interrupt */\r
+       NVIC_InitStructure.NVIC_IRQChannel = TIM6_IRQn;\r
+       NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = configLIBRARY_LOWEST_INTERRUPT_PRIORITY;\r
+       NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0x00; /* Not used as 4 bits are used for the pre-emption priority. */\r
+       NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;\r
+       NVIC_Init(&NVIC_InitStructure);\r
+       \r
+       TIM_ClearITPendingBit( TIM6, TIM_IT_Update );\r
+       TIM_Cmd( TIM6, ENABLE );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void TIM6_IRQHandler( void )\r
+{\r
+       /* Interrupt handler for TIM 6\r
+       \r
+       The time base for the run time stats is generated by the 16 bit timer 6.\r
+       Each time the timer overflows ulTIM6_OverflowCount is incremented.\r
+       Therefore, when converting the total run time to a 32 bit number, the most\r
+       significant two bytes are given by ulTIM6_OverflowCount and the least\r
+       significant two bytes are given by the current TIM6 counter value.  Care\r
+       must be taken with data consistency when combining the two in case a timer\r
+       overflow occurs as the value is being read. */\r
+       if( TIM_GetITStatus( TIM6, TIM_IT_Update) != RESET)\r
+       {\r
+               ulTIM6_OverflowCount++;\r
+               TIM_ClearITPendingBit( TIM6, TIM_IT_Update );\r
+       }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationStackOverflowHook( xTaskHandle *pxTask, signed char *pcTaskName )\r
+{\r
+       ( void ) pcTaskName;\r
+       ( void ) pxTask;\r
+       \r
+       /* Run time stack overflow checking is performed if\r
+       configconfigCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2.  This hook\r
+       function is called if a stack overflow is detected. */\r
+       for( ;; );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationMallocFailedHook( void )\r
+{\r
+       /* Called if a call to pvPortMalloc() fails because there is insufficient\r
+       free memory available in the FreeRTOS heap.  pvPortMalloc() is called\r
+       internally by FreeRTOS API functions that create tasks, queues or\r
+       semaphores. */\r
+       for( ;; );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationIdleHook( void )\r
+{\r
+       /* Called on each iteration of the idle task.  In this case the idle task\r
+       just enters a low(ish) power mode. */\r
+       PWR_EnterSleepMode( PWR_Regulator_ON, PWR_SLEEPEntry_WFI );\r
+}\r
+\r
+\r
+\r

diff --git a/Demo/CORTEX_STM32L152_IAR/serial.c b/Demo/CORTEX_STM32L152_IAR/serial.c
new file mode 100644 (file)
index 0000000..0668d49
--- /dev/null
+++ b/Demo/CORTEX_STM32L152_IAR/serial.c
@@ -0,0 +1,246 @@
+/*\r
+    FreeRTOS V6.1.0 - Copyright (C) 2010 Real Time Engineers Ltd.\r
+\r
+    ***************************************************************************\r
+    *                                                                         *\r
+    * If you are:                                                             *\r
+    *                                                                         *\r
+    *    + New to FreeRTOS,                                                   *\r
+    *    + Wanting to learn FreeRTOS or multitasking in general quickly       *\r
+    *    + Looking for basic training,                                        *\r
+    *    + Wanting to improve your FreeRTOS skills and productivity           *\r
+    *                                                                         *\r
+    * then take a look at the FreeRTOS books - available as PDF or paperback  *\r
+    *                                                                         *\r
+    *        "Using the FreeRTOS Real Time Kernel - a Practical Guide"        *\r
+    *                  http://www.FreeRTOS.org/Documentation                  *\r
+    *                                                                         *\r
+    * A pdf reference manual is also available.  Both are usually delivered   *\r
+    * to your inbox within 20 minutes to two hours when purchased between 8am *\r
+    * and 8pm GMT (although please allow up to 24 hours in case of            *\r
+    * exceptional circumstances).  Thank you for your support!                *\r
+    *                                                                         *\r
+    ***************************************************************************\r
+\r
+    This file is part of the FreeRTOS distribution.\r
+\r
+    FreeRTOS is free software; you can redistribute it and/or modify it under\r
+    the terms of the GNU General Public License (version 2) as published by the\r
+    Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+    ***NOTE*** The exception to the GPL is included to allow you to distribute\r
+    a combined work that includes FreeRTOS without being obliged to provide the\r
+    source code for proprietary components outside of the FreeRTOS kernel.\r
+    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT\r
+    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\r
+    FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\r
+    more details. You should have received a copy of the GNU General Public\r
+    License and the FreeRTOS license exception along with FreeRTOS; if not it\r
+    can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
+    by writing to Richard Barry, contact details for whom are available on the\r
+    FreeRTOS WEB site.\r
+\r
+    1 tab == 4 spaces!\r
+\r
+    http://www.FreeRTOS.org - Documentation, latest information, license and\r
+    contact details.\r
+\r
+    http://www.SafeRTOS.com - A version that is certified for use in safety\r
+    critical systems.\r
+\r
+    http://www.OpenRTOS.com - Commercial support, development, porting,\r
+    licensing and training services.\r
+*/\r
+\r
+/*\r
+       BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER FOR UART0.\r
+       \r
+       ***Note*** This example uses queues to send each character into an interrupt\r
+       service routine and out of an interrupt service routine individually.  This\r
+       is done to demonstrate queues being used in an interrupt, and to deliberately\r
+       load the system to test the FreeRTOS port.  It is *NOT* meant to be an \r
+       example of an efficient implementation.  An efficient implementation should\r
+       use FIFO's or DMA if available, and only use FreeRTOS API functions when \r
+       enough has been received to warrant a task being unblocked to process the\r
+       data.\r
+*/\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "queue.h"\r
+#include "semphr.h"\r
+#include "comtest2.h"\r
+\r
+/* Library includes. */\r
+#include "stm32l152_eval.h"\r
+\r
+/* Demo application includes. */\r
+#include "serial.h"\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Misc defines. */\r
+#define serINVALID_QUEUE                               ( ( xQueueHandle ) 0 )\r
+#define serNO_BLOCK                                            ( ( portTickType ) 0 )\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* The queue used to hold received characters. */\r
+static xQueueHandle xRxedChars;\r
+static xQueueHandle xCharsForTx;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * See the serial2.h header file.\r
+ */\r
+xComPortHandle xSerialPortInitMinimal( unsigned portLONG ulWantedBaud, unsigned portBASE_TYPE uxQueueLength )\r
+{\r
+USART_InitTypeDef USART_InitStructure;\r
+xComPortHandle xReturn;\r
+NVIC_InitTypeDef NVIC_InitStructure;\r
+\r
+       /* Create the queues used to hold Rx/Tx characters. */\r
+       xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) );\r
+       xCharsForTx = xQueueCreate( uxQueueLength + 1, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) );\r
+       \r
+       /* If the queues were created correctly then setup the serial port\r
+       hardware. */\r
+       if( ( xRxedChars != serINVALID_QUEUE ) && ( xCharsForTx != serINVALID_QUEUE ) )\r
+       {\r
+               USART_InitStructure.USART_BaudRate = ulWantedBaud;\r
+               USART_InitStructure.USART_WordLength = USART_WordLength_8b;\r
+               USART_InitStructure.USART_StopBits = USART_StopBits_1;\r
+               USART_InitStructure.USART_Parity = USART_Parity_No;\r
+               USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;\r
+               USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;\r
+               \r
+               /* The Eval board COM2 is being used, which in reality is the STM32\r
+               USART3. */\r
+               STM_EVAL_COMInit( COM2, &USART_InitStructure );\r
+               \r
+               NVIC_InitStructure.NVIC_IRQChannel = USART3_IRQn;\r
+               NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY;\r
+               NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0; /* Not used as 4 bits are used for the pre-emption priority. */;\r
+               NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;\r
+               NVIC_Init( &NVIC_InitStructure );\r
+               USART_ITConfig( USART3, USART_IT_RXNE, ENABLE );\r
+       }\r
+       else\r
+       {\r
+               xReturn = ( xComPortHandle ) 0;\r
+       }\r
+\r
+       /* This demo file only supports a single port but we have to return\r
+       something to comply with the standard demo header file. */\r
+       return xReturn;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed portCHAR *pcRxedChar, portTickType xBlockTime )\r
+{\r
+       /* The port handle is not required as this driver only supports one port. */\r
+       ( void ) pxPort;\r
+\r
+       /* Get the next character from the buffer.  Return false if no characters\r
+       are available, or arrive before xBlockTime expires. */\r
+       if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) )\r
+       {\r
+               return pdTRUE;\r
+       }\r
+       else\r
+       {\r
+               return pdFALSE;\r
+       }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vSerialPutString( xComPortHandle pxPort, const signed portCHAR * const pcString, unsigned portSHORT usStringLength )\r
+{\r
+signed portCHAR *pxNext;\r
+\r
+       /* A couple of parameters that this port does not use. */\r
+       ( void ) usStringLength;\r
+       ( void ) pxPort;\r
+\r
+       /* NOTE: This implementation does not handle the queue being full as no\r
+       block time is used! */\r
+\r
+       /* The port handle is not required as this driver only supports UART1. */\r
+       ( void ) pxPort;\r
+\r
+       /* Send each character in the string, one at a time. */\r
+       pxNext = ( signed portCHAR * ) pcString;\r
+       while( *pxNext )\r
+       {\r
+               xSerialPutChar( pxPort, *pxNext, serNO_BLOCK );\r
+               pxNext++;\r
+       }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed portCHAR cOutChar, portTickType xBlockTime )\r
+{\r
+signed portBASE_TYPE xReturn;\r
+\r
+       if( xQueueSend( xCharsForTx, &cOutChar, xBlockTime ) == pdPASS )\r
+       {\r
+               xReturn = pdPASS;\r
+               USART_ITConfig( USART3, USART_IT_TXE, ENABLE );\r
+       }\r
+       else\r
+       {\r
+               xReturn = pdFAIL;\r
+       }\r
+\r
+       return xReturn;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vSerialClose( xComPortHandle xPort )\r
+{\r
+       /* Not supported as not required by the demo application. */\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void USART3_IRQHandler( void )\r
+{\r
+portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE;\r
+portCHAR cChar;\r
+\r
+       if( USART_GetITStatus( USART3, USART_IT_TXE ) == SET )\r
+       {\r
+               /* The interrupt was caused by the TX register becoming empty.  Are \r
+               there any more characters to transmit? */\r
+               if( xQueueReceiveFromISR( xCharsForTx, &cChar, &xHigherPriorityTaskWoken ) == pdTRUE )\r
+               {\r
+                       /* A character was retrieved from the queue so can be sent to the\r
+                       USART now. */\r
+                       USART_SendData( USART3, cChar );\r
+               }\r
+               else\r
+               {\r
+                       USART_ITConfig( USART3, USART_IT_TXE, DISABLE );                \r
+               }               \r
+       }\r
+       \r
+       if( USART_GetITStatus( USART3, USART_IT_RXNE ) == SET )\r
+       {\r
+               /* A character has been received on the USART, send it to the Rx\r
+               handler task. */\r
+               cChar = USART_ReceiveData( USART3 );\r
+               xQueueSendFromISR( xRxedChars, &cChar, &xHigherPriorityTaskWoken );\r
+       }       \r
+\r
+       /* If sending or receiving from a queue has caused a task to unblock, and\r
+       the unblocked task has a priority equal to or higher than the currently \r
+       running task (the task this ISR interrupted), then xHigherPriorityTaskWoken \r
+       will have automatically been set to pdTRUE within the queue send or receive \r
+       function.  portEND_SWITCHING_ISR() will then ensure that this ISR returns \r
+       directly to the higher priority unblocked task. */\r
+       portEND_SWITCHING_ISR( xHigherPriorityTaskWoken );\r
+}\r
+\r
+\r
+\r
+\r
+\r
+       \r

diff --git a/Demo/CORTEX_STM32L152_IAR/settings/RTOSDemo.cspy.bat b/Demo/CORTEX_STM32L152_IAR/settings/RTOSDemo.cspy.bat
new file mode 100644 (file)
index 0000000..b4f2a0c
--- /dev/null
+++ b/Demo/CORTEX_STM32L152_IAR/settings/RTOSDemo.cspy.bat
@@ -0,0 +1,15 @@
+@REM This batch file has been generated by the IAR Embedded Workbench\r
+@REM C-SPY Debugger, as an aid to preparing a command line for running\r
+@REM the cspybat command line utility using the appropriate settings.\r
+@REM\r
+@REM You can launch cspybat by typing the name of this batch file followed\r
+@REM by the name of the debug file (usually an ELF/DWARF or UBROF file).\r
+@REM Note that this file is generated every time a new debug session\r
+@REM is initialized, so you may want to move or rename the file before\r
+@REM making changes.\r
+@REM \r
+\r
+\r
+"C:\devtools\IAR Systems\Embedded Workbench 6.0\common\bin\cspybat" "C:\devtools\IAR Systems\Embedded Workbench 6.0\arm\bin\armproc.dll" "C:\devtools\IAR Systems\Embedded Workbench 6.0\arm\bin\armjlink.dll"  %1 --plugin "C:\devtools\IAR Systems\Embedded Workbench 6.0\arm\bin\armbat.dll" --flash_loader "C:\devtools\IAR Systems\Embedded Workbench 6.0\arm\config\flashloader\ST\FlashSTM32L15xxB.board" --backend -B "--endian=little" "--cpu=Cortex-M3" "--fpu=None" "-p" "C:\devtools\IAR Systems\Embedded Workbench 6.0\arm\CONFIG\debugger\ST\iostm32l152xx.ddf" "--semihosting" "--device=STM32L152xB" "--drv_communication=USB0" "--jlink_speed=auto" "--jlink_initial_speed=32" "--jlink_reset_strategy=0,0" "--jlink_interface=SWD" "--drv_catch_exceptions=0x000" \r
+\r
+\r

diff --git a/Demo/CORTEX_STM32L152_IAR/settings/RTOSDemo.dbgdt b/Demo/CORTEX_STM32L152_IAR/settings/RTOSDemo.dbgdt
new file mode 100644 (file)
index 0000000..cf214cc
--- /dev/null
+++ b/Demo/CORTEX_STM32L152_IAR/settings/RTOSDemo.dbgdt
@@ -0,0 +1,68 @@
+<?xml version="1.0" encoding="iso-8859-1"?>\r
+\r
+<Project>\r
+  <Desktop>\r
+    <Static>\r
+      <Debug-Log>\r
+        \r
+        \r
+      <PreferedWindows><Position>3</Position><ScreenPosX>0</ScreenPosX><ScreenPosY>0</ScreenPosY><Windows/></PreferedWindows><ColumnWidth0>20</ColumnWidth0><ColumnWidth1>1622</ColumnWidth1></Debug-Log>\r
+      <Build>\r
+        <ColumnWidth0>20</ColumnWidth0>\r
+        <ColumnWidth1>1216</ColumnWidth1>\r
+        <ColumnWidth2>324</ColumnWidth2>\r
+        <ColumnWidth3>81</ColumnWidth3>\r
+      <PreferedWindows><Position>3</Position><ScreenPosX>0</ScreenPosX><ScreenPosY>0</ScreenPosY><Windows><Window><Factory>Debug-Log</Factory></Window></Windows></PreferedWindows></Build>\r
+      <Workspace>\r
+        <ColumnWidths>\r
+          \r
+          \r
+          \r
+          \r
+        <Column0>332</Column0><Column1>27</Column1><Column2>27</Column2><Column3>27</Column3></ColumnWidths>\r
+      </Workspace>\r
+      <Disassembly>\r
+        <PreferedWindows>\r
+          \r
+          \r
+          \r
+          \r
+        <Position>2</Position><ScreenPosX>0</ScreenPosX><ScreenPosY>0</ScreenPosY><Windows/></PreferedWindows>\r
+        \r
+        \r
+        \r
+      <MixedMode>1</MixedMode><CodeCovShow>1</CodeCovShow><InstrProfShow>1</InstrProfShow></Disassembly>\r
+    <Watch><Format><struct_types/><watch_formats><Fmt><Key>{W}Watch-0:tmppre</Key><Value>1</Value></Fmt></watch_formats></Format><PreferedWindows><Position>2</Position><ScreenPosX>0</ScreenPosX><ScreenPosY>0</ScreenPosY><Windows/></PreferedWindows><Column0>151</Column0><Column1>148</Column1><Column2>100</Column2><Column3>100</Column3></Watch><QuickWatch><PreferedWindows><Position>2</Position><ScreenPosX>0</ScreenPosX><ScreenPosY>0</ScreenPosY><Windows/></PreferedWindows><Column0>208</Column0><Column1>100</Column1><Column2>100</Column2><Column3>100</Column3></QuickWatch><TerminalIO><PreferedWindows><Position>2</Position><ScreenPosX>0</ScreenPosX><ScreenPosY>0</ScreenPosY><Windows/></PreferedWindows><InputSource>1</InputSource><InputMode>10</InputMode><Filename>$PROJ_DIR$\TermIOInput.txt</Filename><InputEcho>1</InputEcho><ShowReset>0</ShowReset></TerminalIO><TASKVIEW><Column0>200</Column0><Column1>100</Column1><Column2>100</Column2><Column3>100</Column3><Column4>100</Column4><Column5>100</Column5><Column6>100</Column6><Column7>150</Column7></TASKVIEW><QUEUEVIEW><Column0>300</Column0><Column1>100</Column1><Column2>100</Column2><Column3>100</Column3><Column4>100</Column4><Column5>100</Column5><Column6>100</Column6></QUEUEVIEW><Register><PreferedWindows><Position>2</Position><ScreenPosX>0</ScreenPosX><ScreenPosY>0</ScreenPosY><Windows/></PreferedWindows></Register><CallStack><PreferedWindows><Position>1</Position><ScreenPosX>0</ScreenPosX><ScreenPosY>0</ScreenPosY><Windows/></PreferedWindows><ViewArgs>1</ViewArgs></CallStack></Static>\r
+    <Windows>\r
+      \r
+      \r
+    <Wnd0>\r
+        <Tabs>\r
+          <Tab>\r
+            <Identity>TabID-15530-21362</Identity>\r
+            <TabName>Workspace</TabName>\r
+            <Factory>Workspace</Factory>\r
+            <Session>\r
+              \r
+            <NodeDict><ExpandedNode>RTOSDemo</ExpandedNode><ExpandedNode>RTOSDemo/FreeRTOS_Source</ExpandedNode><ExpandedNode>RTOSDemo/FreeRTOS_Source/Portable</ExpandedNode><ExpandedNode>RTOSDemo/Standard_Demo_Code</ExpandedNode></NodeDict></Session>\r
+          </Tab>\r
+        </Tabs>\r
+        \r
+      <SelectedTab>0</SelectedTab></Wnd0><Wnd1><Tabs><Tab><Identity>TabID-10464-23570</Identity><TabName>Tasks</TabName><Factory>TASKVIEW</Factory><Session/></Tab></Tabs><SelectedTab>0</SelectedTab></Wnd1><Wnd2><Tabs><Tab><Identity>TabID-31438-23586</Identity><TabName>Queues</TabName><Factory>QUEUEVIEW</Factory><Session/></Tab></Tabs><SelectedTab>0</SelectedTab></Wnd2><Wnd3><Tabs><Tab><Identity>TabID-15541-875</Identity><TabName>Terminal I/O</TabName><Factory>TerminalIO</Factory><Session/></Tab></Tabs><SelectedTab>0</SelectedTab></Wnd3></Windows>\r
+    <Editor>\r
+      \r
+      \r
+      \r
+      \r
+    <Pane><Tab><Factory>TextEditor</Factory><Filename>$WS_DIR$\main.c</Filename><XPos>0</XPos><YPos>219</YPos><SelStart>10728</SelStart><SelEnd>10728</SelEnd></Tab><ActiveTab>0</ActiveTab><Tab><Factory>TextEditor</Factory><Filename>$WS_DIR$\..\..\Source\queue.c</Filename><XPos>0</XPos><YPos>1035</YPos><SelStart>35647</SelStart><SelEnd>35647</SelEnd></Tab></Pane><ActivePane>0</ActivePane><Sizes><Pane><X>1000000</X><Y>1000000</Y></Pane></Sizes><SplitMode>1</SplitMode></Editor>\r
+    <Positions>\r
+      \r
+      \r
+      \r
+      \r
+      \r
+    <Top><Row0><Sizes><Toolbar-012aad60><key>iaridepm.enu1</key></Toolbar-012aad60><Toolbar-09947288><key>debuggergui.enu1</key></Toolbar-09947288></Sizes></Row0><Row1><Sizes><Toolbar-06af74f0><key>armjlink.enu1</key></Toolbar-06af74f0></Sizes></Row1></Top><Left><Row0><Sizes><Wnd0><Rect><Top>-2</Top><Left>-2</Left><Bottom>659</Bottom><Right>406</Right><x>-2</x><y>-2</y><xscreen>200</xscreen><yscreen>200</yscreen><sizeHorzCX>119048</sizeHorzCX><sizeHorzCY>203666</sizeHorzCY><sizeVertCX>242857</sizeVertCX><sizeVertCY>673116</sizeVertCY></Rect></Wnd0></Sizes></Row0></Left><Right><Row0><Sizes><Wnd3><Rect><Top>-2</Top><Left>-2</Left><Bottom>659</Bottom><Right>436</Right><x>-2</x><y>-2</y><xscreen>200</xscreen><yscreen>200</yscreen><sizeHorzCX>119048</sizeHorzCX><sizeHorzCY>203666</sizeHorzCY><sizeVertCX>260714</sizeVertCX><sizeVertCY>673116</sizeVertCY></Rect></Wnd3></Sizes></Row0></Right><Bottom><Row0><Sizes><Wnd1><Rect><Top>-2</Top><Left>-2</Left><Bottom>172</Bottom><Right>1682</Right><x>-2</x><y>-2</y><xscreen>1684</xscreen><yscreen>174</yscreen><sizeHorzCX>1002381</sizeHorzCX><sizeHorzCY>177189</sizeHorzCY><sizeVertCX>119048</sizeVertCX><sizeVertCY>203666</sizeVertCY></Rect></Wnd1></Sizes></Row0><Row1><Sizes><Wnd2><Rect><Top>170</Top><Left>-2</Left><Bottom>255</Bottom><Right>1682</Right><x>-2</x><y>170</y><xscreen>1684</xscreen><yscreen>85</yscreen><sizeHorzCX>1002381</sizeHorzCX><sizeHorzCY>86558</sizeHorzCY><sizeVertCX>119048</sizeVertCX><sizeVertCY>203666</sizeVertCY></Rect></Wnd2></Sizes></Row1></Bottom><Float><Sizes/></Float></Positions>\r
+  </Desktop>\r
+</Project>\r
+\r
+\r

diff --git a/Demo/CORTEX_STM32L152_IAR/settings/RTOSDemo.dni b/Demo/CORTEX_STM32L152_IAR/settings/RTOSDemo.dni
new file mode 100644 (file)
index 0000000..5764d41
--- /dev/null
+++ b/Demo/CORTEX_STM32L152_IAR/settings/RTOSDemo.dni
@@ -0,0 +1,105 @@
+[DebugChecksum]\r
+Checksum=1802430239\r
+[DisAssemblyWindow]\r
+NumStates=_ 1\r
+State 1=_ 1\r
+[InstructionProfiling]\r
+Enabled=_ 0\r
+[CodeCoverage]\r
+Enabled=_ 0\r
+[Profiling]\r
+Enabled=0\r
+[Exceptions]\r
+StopOnUncaught=_ 0\r
+StopOnThrow=_ 0\r
+[StackPlugin]\r
+Enabled=1\r
+OverflowWarningsEnabled=1\r
+WarningThreshold=90\r
+SpWarningsEnabled=1\r
+WarnHow=0\r
+UseTrigger=1\r
+TriggerName=main\r
+LimitSize=0\r
+ByteLimit=50\r
+[SWOTraceHWSettings]\r
+CpuClock=32000000\r
+ClockAutoDetect=1\r
+ClockWanted=6000000\r
+JtagSpeed=2000000\r
+Prescaler=16\r
+TimeStampPrescIndex=0\r
+TimeStampPrescData=0\r
+PcSampCYCTAP=1\r
+PcSampPOSTCNT=15\r
+PcSampIndex=0\r
+DataLogMode=0\r
+ITMportsEnable=1\r
+ITMportsTermIO=1\r
+ITMportsLogFile=0\r
+ITMlogFile=$PROJ_DIR$\ITM.log\r
+[Interrupts]\r
+Enabled=1\r
+[MemoryMap]\r
+Enabled=0\r
+Base=0\r
+UseAuto=0\r
+TypeViolation=1\r
+UnspecRange=1\r
+ActionState=1\r
+[TraceHelper]\r
+Enabled=0\r
+ShowSource=1\r
+[DataLog]\r
+LogEnabled=0\r
+SumEnabled=0\r
+GraphEnabled=0\r
+ShowTimeLog=1\r
+ShowTimeSum=1\r
+[InterruptLog]\r
+LogEnabled=0\r
+SumEnabled=0\r
+GraphEnabled=0\r
+ShowTimeLog=1\r
+ShowTimeSum=1\r
+SumSortOrder=0\r
+[PowerLog]\r
+LogEnabled=0\r
+GraphEnabled=0\r
+ShowTimeLog=1\r
+ShowTimeSum=0\r
+Title0=Power [mA]\r
+Setup0=0 1 0 500 2 0 4 1 0\r
+[Log file]\r
+LoggingEnabled=_ 0\r
+LogFile=_ ""\r
+Category=_ 0\r
+[TermIOLog]\r
+LoggingEnabled=_ 0\r
+LogFile=_ ""\r
+[SWOTraceWindow]\r
+PcSampling=0\r
+InterruptLogs=0\r
+ForcedTimeStamps=0\r
+EventCPI=0\r
+EventEXC=0\r
+EventFOLD=0\r
+EventLSU=0\r
+EventSLEEP=0\r
+[TraceHelperExtra]\r
+Enabled=0\r
+ShowSource=1\r
+[CallStackLog]\r
+Enabled=0\r
+[DriverProfiling]\r
+Enabled=0\r
+Mode=3\r
+Graph=0\r
+Symbiont=0\r
+[Disassemble mode]\r
+mode=0\r
+[Breakpoints]\r
+Count=0\r
+[Aliases]\r
+Count=0\r
+SuppressDialog=0\r

diff --git a/Demo/CORTEX_STM32L152_IAR/settings/RTOSDemo.wsdt b/Demo/CORTEX_STM32L152_IAR/settings/RTOSDemo.wsdt
new file mode 100644 (file)
index 0000000..b4f7f17
--- /dev/null
+++ b/Demo/CORTEX_STM32L152_IAR/settings/RTOSDemo.wsdt
@@ -0,0 +1,49 @@
+<?xml version="1.0" encoding="iso-8859-1"?>\r
+\r
+<Workspace>\r
+  <ConfigDictionary>\r
+    \r
+  <CurrentConfigs><Project>RTOSDemo/Debug</Project></CurrentConfigs></ConfigDictionary>\r
+  <Desktop>\r
+    <Static>\r
+      <Workspace>\r
+        <ColumnWidths>\r
+          \r
+          \r
+          \r
+          \r
+        <Column0>364</Column0><Column1>27</Column1><Column2>27</Column2><Column3>27</Column3></ColumnWidths>\r
+      </Workspace>\r
+    <Build><ColumnWidth0>20</ColumnWidth0><ColumnWidth1>1216</ColumnWidth1><ColumnWidth2>324</ColumnWidth2><ColumnWidth3>81</ColumnWidth3></Build><TerminalIO/><Debug-Log><ColumnWidth0>20</ColumnWidth0><ColumnWidth1>1622</ColumnWidth1></Debug-Log></Static>\r
+    <Windows>\r
+      \r
+    <Wnd2>\r
+        <Tabs>\r
+          <Tab>\r
+            <Identity>TabID-27630-4718</Identity>\r
+            <TabName>Workspace</TabName>\r
+            <Factory>Workspace</Factory>\r
+            <Session>\r
+              \r
+            <NodeDict><ExpandedNode>RTOSDemo</ExpandedNode></NodeDict></Session>\r
+          </Tab>\r
+        </Tabs>\r
+        \r
+      <SelectedTab>0</SelectedTab></Wnd2><Wnd3><Tabs><Tab><Identity>TabID-10002-7709</Identity><TabName>Build</TabName><Factory>Build</Factory><Session/></Tab><Tab><Identity>TabID-18437-21512</Identity><TabName>Debug Log</TabName><Factory>Debug-Log</Factory><Session/></Tab></Tabs><SelectedTab>0</SelectedTab></Wnd3></Windows>\r
+    <Editor>\r
+      \r
+      \r
+      \r
+      \r
+    <Pane><Tab><Factory>TextEditor</Factory><Filename>$WS_DIR$\main.c</Filename><XPos>0</XPos><YPos>219</YPos><SelStart>10728</SelStart><SelEnd>10728</SelEnd></Tab><ActiveTab>0</ActiveTab><Tab><Factory>TextEditor</Factory><Filename>$WS_DIR$\..\..\Source\queue.c</Filename><XPos>0</XPos><YPos>1035</YPos><SelStart>35647</SelStart><SelEnd>35647</SelEnd></Tab></Pane><ActivePane>0</ActivePane><Sizes><Pane><X>1000000</X><Y>1000000</Y></Pane></Sizes><SplitMode>1</SplitMode></Editor>\r
+    <Positions>\r
+      \r
+      \r
+      \r
+      \r
+      \r
+    <Top><Row0><Sizes><Toolbar-012aad60><key>iaridepm.enu1</key></Toolbar-012aad60></Sizes></Row0><Row1><Sizes/></Row1></Top><Left><Row0><Sizes><Wnd2><Rect><Top>-2</Top><Left>-2</Left><Bottom>740</Bottom><Right>438</Right><x>-2</x><y>-2</y><xscreen>200</xscreen><yscreen>200</yscreen><sizeHorzCX>119048</sizeHorzCX><sizeHorzCY>203666</sizeHorzCY><sizeVertCX>261905</sizeVertCX><sizeVertCY>755601</sizeVertCY></Rect></Wnd2></Sizes></Row0></Left><Right><Row0><Sizes/></Row0></Right><Bottom><Row0><Sizes><Wnd3><Rect><Top>-2</Top><Left>-2</Left><Bottom>198</Bottom><Right>1682</Right><x>-2</x><y>-2</y><xscreen>1684</xscreen><yscreen>200</yscreen><sizeHorzCX>1002381</sizeHorzCX><sizeHorzCY>203666</sizeHorzCY><sizeVertCX>119048</sizeVertCX><sizeVertCY>203666</sizeVertCY></Rect></Wnd3></Sizes></Row0></Bottom><Float><Sizes/></Float></Positions>\r
+  </Desktop>\r
+</Workspace>\r
+\r
+\r

diff --git a/Demo/CORTEX_STM32L152_IAR/settings/RTOSDemo_Debug.jlink b/Demo/CORTEX_STM32L152_IAR/settings/RTOSDemo_Debug.jlink
new file mode 100644 (file)
index 0000000..228ff82
--- /dev/null
+++ b/Demo/CORTEX_STM32L152_IAR/settings/RTOSDemo_Debug.jlink
@@ -0,0 +1,23 @@
+[BREAKPOINTS]\r
+ShowInfoWin = 1\r
+EnableFlashBP = 2\r
+BPDuringExecution = 0\r
+[CFI]\r
+CFISize = 0x00\r
+CFIAddr = 0x00\r
+[CPU]\r
+OverrideMemMap = 0\r
+AllowSimulation = 1\r
+ScriptFile=""\r
+[FLASH]\r
+SkipProgOnCRCMatch = 1\r
+VerifyDownload = 1\r
+AllowCaching = 1\r
+EnableFlashDL = 2\r
+Override = 0\r
+Device="ADUC7020X62"\r
+[GENERAL]\r
+WorkRAMSize = 0x00\r
+WorkRAMAddr = 0x00\r
+[SWO]\r
+SWOLogFile=""\r

diff --git a/Demo/CORTEX_STM32L152_IAR/system_and_ST_code/CMSIS/CM3/CoreSupport/core_cm3.c b/Demo/CORTEX_STM32L152_IAR/system_and_ST_code/CMSIS/CM3/CoreSupport/core_cm3.c
new file mode 100644 (file)
index 0000000..56fddc5
--- /dev/null
+++ b/Demo/CORTEX_STM32L152_IAR/system_and_ST_code/CMSIS/CM3/CoreSupport/core_cm3.c
@@ -0,0 +1,784 @@
+/**************************************************************************//**\r
+ * @file     core_cm3.c\r
+ * @brief    CMSIS Cortex-M3 Core Peripheral Access Layer Source File\r
+ * @version  V1.30\r
+ * @date     30. October 2009\r
+ *\r
+ * @note\r
+ * Copyright (C) 2009 ARM Limited. All rights reserved.\r
+ *\r
+ * @par\r
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M \r
+ * processor based microcontrollers.  This file can be freely distributed \r
+ * within development tools that are supporting such ARM based processors. \r
+ *\r
+ * @par\r
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+ *\r
+ ******************************************************************************/\r
+\r
+#include <stdint.h>\r
+\r
+/* define compiler specific symbols */\r
+#if defined ( __CC_ARM   )\r
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */\r
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */\r
+\r
+#elif defined ( __ICCARM__ )\r
+  #define __ASM           __asm                                       /*!< asm keyword for IAR Compiler          */\r
+  #define __INLINE        inline                                      /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */\r
+\r
+#elif defined   (  __GNUC__  )\r
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */\r
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */\r
+\r
+#elif defined   (  __TASKING__  )\r
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */\r
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */\r
+\r
+#endif\r
+\r
+\r
+/* ###################  Compiler specific Intrinsics  ########################### */\r
+\r
+#if defined ( __CC_ARM   ) /*------------------RealView Compiler -----------------*/\r
+/* ARM armcc specific functions */\r
+\r
+/**\r
+ * @brief  Return the Process Stack Pointer\r
+ *\r
+ * @return ProcessStackPointer\r
+ *\r
+ * Return the actual process stack pointer\r
+ */\r
+__ASM uint32_t __get_PSP(void)\r
+{\r
+  mrs r0, psp\r
+  bx lr\r
+}\r
+\r
+/**\r
+ * @brief  Set the Process Stack Pointer\r
+ *\r
+ * @param  topOfProcStack  Process Stack Pointer\r
+ *\r
+ * Assign the value ProcessStackPointer to the MSP \r
+ * (process stack pointer) Cortex processor register\r
+ */\r
+__ASM void __set_PSP(uint32_t topOfProcStack)\r
+{\r
+  msr psp, r0\r
+  bx lr\r
+}\r
+\r
+/**\r
+ * @brief  Return the Main Stack Pointer\r
+ *\r
+ * @return Main Stack Pointer\r
+ *\r
+ * Return the current value of the MSP (main stack pointer)\r
+ * Cortex processor register\r
+ */\r
+__ASM uint32_t __get_MSP(void)\r
+{\r
+  mrs r0, msp\r
+  bx lr\r
+}\r
+\r
+/**\r
+ * @brief  Set the Main Stack Pointer\r
+ *\r
+ * @param  topOfMainStack  Main Stack Pointer\r
+ *\r
+ * Assign the value mainStackPointer to the MSP \r
+ * (main stack pointer) Cortex processor register\r
+ */\r
+__ASM void __set_MSP(uint32_t mainStackPointer)\r
+{\r
+  msr msp, r0\r
+  bx lr\r
+}\r
+\r
+/**\r
+ * @brief  Reverse byte order in unsigned short value\r
+ *\r
+ * @param   value  value to reverse\r
+ * @return         reversed value\r
+ *\r
+ * Reverse byte order in unsigned short value\r
+ */\r
+__ASM uint32_t __REV16(uint16_t value)\r
+{\r
+  rev16 r0, r0\r
+  bx lr\r
+}\r
+\r
+/**\r
+ * @brief  Reverse byte order in signed short value with sign extension to integer\r
+ *\r
+ * @param   value  value to reverse\r
+ * @return         reversed value\r
+ *\r
+ * Reverse byte order in signed short value with sign extension to integer\r
+ */\r
+__ASM int32_t __REVSH(int16_t value)\r
+{\r
+  revsh r0, r0\r
+  bx lr\r
+}\r
+\r
+\r
+#if (__ARMCC_VERSION < 400000)\r
+\r
+/**\r
+ * @brief  Remove the exclusive lock created by ldrex\r
+ *\r
+ * Removes the exclusive lock which is created by ldrex.\r
+ */\r
+__ASM void __CLREX(void)\r
+{\r
+  clrex\r
+}\r
+\r
+/**\r
+ * @brief  Return the Base Priority value\r
+ *\r
+ * @return BasePriority\r
+ *\r
+ * Return the content of the base priority register\r
+ */\r
+__ASM uint32_t  __get_BASEPRI(void)\r
+{\r
+  mrs r0, basepri\r
+  bx lr\r
+}\r
+\r
+/**\r
+ * @brief  Set the Base Priority value\r
+ *\r
+ * @param  basePri  BasePriority\r
+ *\r
+ * Set the base priority register\r
+ */\r
+__ASM void __set_BASEPRI(uint32_t basePri)\r
+{\r
+  msr basepri, r0\r
+  bx lr\r
+}\r
+\r
+/**\r
+ * @brief  Return the Priority Mask value\r
+ *\r
+ * @return PriMask\r
+ *\r
+ * Return state of the priority mask bit from the priority mask register\r
+ */\r
+__ASM uint32_t __get_PRIMASK(void)\r
+{\r
+  mrs r0, primask\r
+  bx lr\r
+}\r
+\r
+/**\r
+ * @brief  Set the Priority Mask value\r
+ *\r
+ * @param  priMask  PriMask\r
+ *\r
+ * Set the priority mask bit in the priority mask register\r
+ */\r
+__ASM void __set_PRIMASK(uint32_t priMask)\r
+{\r
+  msr primask, r0\r
+  bx lr\r
+}\r
+\r
+/**\r
+ * @brief  Return the Fault Mask value\r
+ *\r
+ * @return FaultMask\r
+ *\r
+ * Return the content of the fault mask register\r
+ */\r
+__ASM uint32_t  __get_FAULTMASK(void)\r
+{\r
+  mrs r0, faultmask\r
+  bx lr\r
+}\r
+\r
+/**\r
+ * @brief  Set the Fault Mask value\r
+ *\r
+ * @param  faultMask  faultMask value\r
+ *\r
+ * Set the fault mask register\r
+ */\r
+__ASM void __set_FAULTMASK(uint32_t faultMask)\r
+{\r
+  msr faultmask, r0\r
+  bx lr\r
+}\r
+\r
+/**\r
+ * @brief  Return the Control Register value\r
+ * \r
+ * @return Control value\r
+ *\r
+ * Return the content of the control register\r
+ */\r
+__ASM uint32_t __get_CONTROL(void)\r
+{\r
+  mrs r0, control\r
+  bx lr\r
+}\r
+\r
+/**\r
+ * @brief  Set the Control Register value\r
+ *\r
+ * @param  control  Control value\r
+ *\r
+ * Set the control register\r
+ */\r
+__ASM void __set_CONTROL(uint32_t control)\r
+{\r
+  msr control, r0\r
+  bx lr\r
+}\r
+\r
+#endif /* __ARMCC_VERSION  */ \r
+\r
+\r
+\r
+#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/\r
+/* IAR iccarm specific functions */\r
+#pragma diag_suppress=Pe940\r
+\r
+/**\r
+ * @brief  Return the Process Stack Pointer\r
+ *\r
+ * @return ProcessStackPointer\r
+ *\r
+ * Return the actual process stack pointer\r
+ */\r
+uint32_t __get_PSP(void)\r
+{\r
+  __ASM("mrs r0, psp");\r
+  __ASM("bx lr");\r
+}\r
+\r
+/**\r
+ * @brief  Set the Process Stack Pointer\r
+ *\r
+ * @param  topOfProcStack  Process Stack Pointer\r
+ *\r
+ * Assign the value ProcessStackPointer to the MSP \r
+ * (process stack pointer) Cortex processor register\r
+ */\r
+void __set_PSP(uint32_t topOfProcStack)\r
+{\r
+  __ASM("msr psp, r0");\r
+  __ASM("bx lr");\r
+}\r
+\r
+/**\r
+ * @brief  Return the Main Stack Pointer\r
+ *\r
+ * @return Main Stack Pointer\r
+ *\r
+ * Return the current value of the MSP (main stack pointer)\r
+ * Cortex processor register\r
+ */\r
+uint32_t __get_MSP(void)\r
+{\r
+  __ASM("mrs r0, msp");\r
+  __ASM("bx lr");\r
+}\r
+\r
+/**\r
+ * @brief  Set the Main Stack Pointer\r
+ *\r
+ * @param  topOfMainStack  Main Stack Pointer\r
+ *\r
+ * Assign the value mainStackPointer to the MSP \r
+ * (main stack pointer) Cortex processor register\r
+ */\r
+void __set_MSP(uint32_t topOfMainStack)\r
+{\r
+  __ASM("msr msp, r0");\r
+  __ASM("bx lr");\r
+}\r
+\r
+/**\r
+ * @brief  Reverse byte order in unsigned short value\r
+ *\r
+ * @param  value  value to reverse\r
+ * @return        reversed value\r
+ *\r
+ * Reverse byte order in unsigned short value\r
+ */\r
+uint32_t __REV16(uint16_t value)\r
+{\r
+  __ASM("rev16 r0, r0");\r
+  __ASM("bx lr");\r
+}\r
+\r
+/**\r
+ * @brief  Reverse bit order of value\r
+ *\r
+ * @param  value  value to reverse\r
+ * @return        reversed value\r
+ *\r
+ * Reverse bit order of value\r
+ */\r
+uint32_t __RBIT(uint32_t value)\r
+{\r
+  __ASM("rbit r0, r0");\r
+  __ASM("bx lr");\r
+}\r
+\r
+/**\r
+ * @brief  LDR Exclusive (8 bit)\r
+ *\r
+ * @param  *addr  address pointer\r
+ * @return        value of (*address)\r
+ *\r
+ * Exclusive LDR command for 8 bit values)\r
+ */\r
+uint8_t __LDREXB(uint8_t *addr)\r
+{\r
+  __ASM("ldrexb r0, [r0]");\r
+  __ASM("bx lr"); \r
+}\r
+\r
+/**\r
+ * @brief  LDR Exclusive (16 bit)\r
+ *\r
+ * @param  *addr  address pointer\r
+ * @return        value of (*address)\r
+ *\r
+ * Exclusive LDR command for 16 bit values\r
+ */\r
+uint16_t __LDREXH(uint16_t *addr)\r
+{\r
+  __ASM("ldrexh r0, [r0]");\r
+  __ASM("bx lr");\r
+}\r
+\r
+/**\r
+ * @brief  LDR Exclusive (32 bit)\r
+ *\r
+ * @param  *addr  address pointer\r
+ * @return        value of (*address)\r
+ *\r
+ * Exclusive LDR command for 32 bit values\r
+ */\r
+uint32_t __LDREXW(uint32_t *addr)\r
+{\r
+  __ASM("ldrex r0, [r0]");\r
+  __ASM("bx lr");\r
+}\r
+\r
+/**\r
+ * @brief  STR Exclusive (8 bit)\r
+ *\r
+ * @param  value  value to store\r
+ * @param  *addr  address pointer\r
+ * @return        successful / failed\r
+ *\r
+ * Exclusive STR command for 8 bit values\r
+ */\r
+uint32_t __STREXB(uint8_t value, uint8_t *addr)\r
+{\r
+  __ASM("strexb r0, r0, [r1]");\r
+  __ASM("bx lr");\r
+}\r
+\r
+/**\r
+ * @brief  STR Exclusive (16 bit)\r
+ *\r
+ * @param  value  value to store\r
+ * @param  *addr  address pointer\r
+ * @return        successful / failed\r
+ *\r
+ * Exclusive STR command for 16 bit values\r
+ */\r
+uint32_t __STREXH(uint16_t value, uint16_t *addr)\r
+{\r
+  __ASM("strexh r0, r0, [r1]");\r
+  __ASM("bx lr");\r
+}\r
+\r
+/**\r
+ * @brief  STR Exclusive (32 bit)\r
+ *\r
+ * @param  value  value to store\r
+ * @param  *addr  address pointer\r
+ * @return        successful / failed\r
+ *\r
+ * Exclusive STR command for 32 bit values\r
+ */\r
+uint32_t __STREXW(uint32_t value, uint32_t *addr)\r
+{\r
+  __ASM("strex r0, r0, [r1]");\r
+  __ASM("bx lr");\r
+}\r
+\r
+#pragma diag_default=Pe940\r
+\r
+\r
+#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/\r
+/* GNU gcc specific functions */\r
+\r
+/**\r
+ * @brief  Return the Process Stack Pointer\r
+ *\r
+ * @return ProcessStackPointer\r
+ *\r
+ * Return the actual process stack pointer\r
+ */\r
+uint32_t __get_PSP(void) __attribute__( ( naked ) );\r
+uint32_t __get_PSP(void)\r
+{\r
+  uint32_t result=0;\r
+\r
+  __ASM volatile ("MRS %0, psp\n\t" \r
+                  "MOV r0, %0 \n\t"\r
+                  "BX  lr     \n\t"  : "=r" (result) );\r
+  return(result);\r
+}\r
+\r
+/**\r
+ * @brief  Set the Process Stack Pointer\r
+ *\r
+ * @param  topOfProcStack  Process Stack Pointer\r
+ *\r
+ * Assign the value ProcessStackPointer to the MSP \r
+ * (process stack pointer) Cortex processor register\r
+ */\r
+void __set_PSP(uint32_t topOfProcStack) __attribute__( ( naked ) );\r
+void __set_PSP(uint32_t topOfProcStack)\r
+{\r
+  __ASM volatile ("MSR psp, %0\n\t"\r
+                  "BX  lr     \n\t" : : "r" (topOfProcStack) );\r
+}\r
+\r
+/**\r
+ * @brief  Return the Main Stack Pointer\r
+ *\r
+ * @return Main Stack Pointer\r
+ *\r
+ * Return the current value of the MSP (main stack pointer)\r
+ * Cortex processor register\r
+ */\r
+uint32_t __get_MSP(void) __attribute__( ( naked ) );\r
+uint32_t __get_MSP(void)\r
+{\r
+  uint32_t result=0;\r
+\r
+  __ASM volatile ("MRS %0, msp\n\t" \r
+                  "MOV r0, %0 \n\t"\r
+                  "BX  lr     \n\t"  : "=r" (result) );\r
+  return(result);\r
+}\r
+\r
+/**\r
+ * @brief  Set the Main Stack Pointer\r
+ *\r
+ * @param  topOfMainStack  Main Stack Pointer\r
+ *\r
+ * Assign the value mainStackPointer to the MSP \r
+ * (main stack pointer) Cortex processor register\r
+ */\r
+void __set_MSP(uint32_t topOfMainStack) __attribute__( ( naked ) );\r
+void __set_MSP(uint32_t topOfMainStack)\r
+{\r
+  __ASM volatile ("MSR msp, %0\n\t"\r
+                  "BX  lr     \n\t" : : "r" (topOfMainStack) );\r
+}\r
+\r
+/**\r
+ * @brief  Return the Base Priority value\r
+ *\r
+ * @return BasePriority\r
+ *\r
+ * Return the content of the base priority register\r
+ */\r
+uint32_t __get_BASEPRI(void)\r
+{\r
+  uint32_t result=0;\r
+  \r
+  __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );\r
+  return(result);\r
+}\r
+\r
+/**\r
+ * @brief  Set the Base Priority value\r
+ *\r
+ * @param  basePri  BasePriority\r
+ *\r
+ * Set the base priority register\r
+ */\r
+void __set_BASEPRI(uint32_t value)\r
+{\r
+  __ASM volatile ("MSR basepri, %0" : : "r" (value) );\r
+}\r
+\r
+/**\r
+ * @brief  Return the Priority Mask value\r
+ *\r
+ * @return PriMask\r
+ *\r
+ * Return state of the priority mask bit from the priority mask register\r
+ */\r
+uint32_t __get_PRIMASK(void)\r
+{\r
+  uint32_t result=0;\r
+\r
+  __ASM volatile ("MRS %0, primask" : "=r" (result) );\r
+  return(result);\r
+}\r
+\r
+/**\r
+ * @brief  Set the Priority Mask value\r
+ *\r
+ * @param  priMask  PriMask\r
+ *\r
+ * Set the priority mask bit in the priority mask register\r
+ */\r
+void __set_PRIMASK(uint32_t priMask)\r
+{\r
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) );\r
+}\r
+\r
+/**\r
+ * @brief  Return the Fault Mask value\r
+ *\r
+ * @return FaultMask\r
+ *\r
+ * Return the content of the fault mask register\r
+ */\r
+uint32_t __get_FAULTMASK(void)\r
+{\r
+  uint32_t result=0;\r
+  \r
+  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );\r
+  return(result);\r
+}\r
+\r
+/**\r
+ * @brief  Set the Fault Mask value\r
+ *\r
+ * @param  faultMask  faultMask value\r
+ *\r
+ * Set the fault mask register\r
+ */\r
+void __set_FAULTMASK(uint32_t faultMask)\r
+{\r
+  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );\r
+}\r
+\r
+/**\r
+ * @brief  Return the Control Register value\r
+* \r
+*  @return Control value\r
+ *\r
+ * Return the content of the control register\r
+ */\r
+uint32_t __get_CONTROL(void)\r
+{\r
+  uint32_t result=0;\r
+\r
+  __ASM volatile ("MRS %0, control" : "=r" (result) );\r
+  return(result);\r
+}\r
+\r
+/**\r
+ * @brief  Set the Control Register value\r
+ *\r
+ * @param  control  Control value\r
+ *\r
+ * Set the control register\r
+ */\r
+void __set_CONTROL(uint32_t control)\r
+{\r
+  __ASM volatile ("MSR control, %0" : : "r" (control) );\r
+}\r
+\r
+\r
+/**\r
+ * @brief  Reverse byte order in integer value\r
+ *\r
+ * @param  value  value to reverse\r
+ * @return        reversed value\r
+ *\r
+ * Reverse byte order in integer value\r
+ */\r
+uint32_t __REV(uint32_t value)\r
+{\r
+  uint32_t result=0;\r
+  \r
+  __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );\r
+  return(result);\r
+}\r
+\r
+/**\r
+ * @brief  Reverse byte order in unsigned short value\r
+ *\r
+ * @param  value  value to reverse\r
+ * @return        reversed value\r
+ *\r
+ * Reverse byte order in unsigned short value\r
+ */\r
+uint32_t __REV16(uint16_t value)\r
+{\r
+  uint32_t result=0;\r
+  \r
+  __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );\r
+  return(result);\r
+}\r
+\r
+/**\r
+ * @brief  Reverse byte order in signed short value with sign extension to integer\r
+ *\r
+ * @param  value  value to reverse\r
+ * @return        reversed value\r
+ *\r
+ * Reverse byte order in signed short value with sign extension to integer\r
+ */\r
+int32_t __REVSH(int16_t value)\r
+{\r
+  uint32_t result=0;\r
+  \r
+  __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );\r
+  return(result);\r
+}\r
+\r
+/**\r
+ * @brief  Reverse bit order of value\r
+ *\r
+ * @param  value  value to reverse\r
+ * @return        reversed value\r
+ *\r
+ * Reverse bit order of value\r
+ */\r
+uint32_t __RBIT(uint32_t value)\r
+{\r
+  uint32_t result=0;\r
+  \r
+   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );\r
+   return(result);\r
+}\r
+\r
+/**\r
+ * @brief  LDR Exclusive (8 bit)\r
+ *\r
+ * @param  *addr  address pointer\r
+ * @return        value of (*address)\r
+ *\r
+ * Exclusive LDR command for 8 bit value\r
+ */\r
+uint8_t __LDREXB(uint8_t *addr)\r
+{\r
+    uint8_t result=0;\r
+  \r
+   __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );\r
+   return(result);\r
+}\r
+\r
+/**\r
+ * @brief  LDR Exclusive (16 bit)\r
+ *\r
+ * @param  *addr  address pointer\r
+ * @return        value of (*address)\r
+ *\r
+ * Exclusive LDR command for 16 bit values\r
+ */\r
+uint16_t __LDREXH(uint16_t *addr)\r
+{\r
+    uint16_t result=0;\r
+  \r
+   __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );\r
+   return(result);\r
+}\r
+\r
+/**\r
+ * @brief  LDR Exclusive (32 bit)\r
+ *\r
+ * @param  *addr  address pointer\r
+ * @return        value of (*address)\r
+ *\r
+ * Exclusive LDR command for 32 bit values\r
+ */\r
+uint32_t __LDREXW(uint32_t *addr)\r
+{\r
+    uint32_t result=0;\r
+  \r
+   __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );\r
+   return(result);\r
+}\r
+\r
+/**\r
+ * @brief  STR Exclusive (8 bit)\r
+ *\r
+ * @param  value  value to store\r
+ * @param  *addr  address pointer\r
+ * @return        successful / failed\r
+ *\r
+ * Exclusive STR command for 8 bit values\r
+ */\r
+uint32_t __STREXB(uint8_t value, uint8_t *addr)\r
+{\r
+   uint32_t result=0;\r
+  \r
+   __ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );\r
+   return(result);\r
+}\r
+\r
+/**\r
+ * @brief  STR Exclusive (16 bit)\r
+ *\r
+ * @param  value  value to store\r
+ * @param  *addr  address pointer\r
+ * @return        successful / failed\r
+ *\r
+ * Exclusive STR command for 16 bit values\r
+ */\r
+uint32_t __STREXH(uint16_t value, uint16_t *addr)\r
+{\r
+   uint32_t result=0;\r
+  \r
+   __ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );\r
+   return(result);\r
+}\r
+\r
+/**\r
+ * @brief  STR Exclusive (32 bit)\r
+ *\r
+ * @param  value  value to store\r
+ * @param  *addr  address pointer\r
+ * @return        successful / failed\r
+ *\r
+ * Exclusive STR command for 32 bit values\r
+ */\r
+uint32_t __STREXW(uint32_t value, uint32_t *addr)\r
+{\r
+   uint32_t result=0;\r
+  \r
+   __ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );\r
+   return(result);\r
+}\r
+\r
+\r
+#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/\r
+/* TASKING carm specific functions */\r
+\r
+/*\r
+ * The CMSIS functions have been implemented as intrinsics in the compiler.\r
+ * Please use "carm -?i" to get an up to date list of all instrinsics,\r
+ * Including the CMSIS ones.\r
+ */\r
+\r
+#endif\r

diff --git a/Demo/CORTEX_STM32L152_IAR/system_and_ST_code/CMSIS/CM3/CoreSupport/core_cm3.h b/Demo/CORTEX_STM32L152_IAR/system_and_ST_code/CMSIS/CM3/CoreSupport/core_cm3.h
new file mode 100644 (file)
index 0000000..2c46056
--- /dev/null
+++ b/Demo/CORTEX_STM32L152_IAR/system_and_ST_code/CMSIS/CM3/CoreSupport/core_cm3.h
@@ -0,0 +1,1818 @@
+/**************************************************************************//**\r
+ * @file     core_cm3.h\r
+ * @brief    CMSIS Cortex-M3 Core Peripheral Access Layer Header File\r
+ * @version  V1.30\r
+ * @date     30. October 2009\r
+ *\r
+ * @note\r
+ * Copyright (C) 2009 ARM Limited. All rights reserved.\r
+ *\r
+ * @par\r
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M\r
+ * processor based microcontrollers.  This file can be freely distributed\r
+ * within development tools that are supporting such ARM based processors.\r
+ *\r
+ * @par\r
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+ *\r
+ ******************************************************************************/\r
+\r
+#ifndef __CM3_CORE_H__\r
+#define __CM3_CORE_H__\r
+\r
+/** @addtogroup CMSIS_CM3_core_LintCinfiguration CMSIS CM3 Core Lint Configuration\r
+ *\r
+ * List of Lint messages which will be suppressed and not shown:\r
+ *   - Error 10: \n\r
+ *     register uint32_t __regBasePri         __asm("basepri"); \n\r
+ *     Error 10: Expecting ';'\r
+ * .\r
+ *   - Error 530: \n\r
+ *     return(__regBasePri); \n\r
+ *     Warning 530: Symbol '__regBasePri' (line 264) not initialized\r
+ * .\r
+ *   - Error 550: \n\r
+ *     __regBasePri = (basePri & 0x1ff); \n\r
+ *     Warning 550: Symbol '__regBasePri' (line 271) not accessed\r
+ * .\r
+ *   - Error 754: \n\r
+ *     uint32_t RESERVED0[24]; \n\r
+ *     Info 754: local structure member '<some, not used in the HAL>' (line 109, file ./cm3_core.h) not referenced\r
+ * .\r
+ *   - Error 750: \n\r
+ *     #define __CM3_CORE_H__ \n\r
+ *     Info 750: local macro '__CM3_CORE_H__' (line 43, file./cm3_core.h) not referenced\r
+ * .\r
+ *   - Error 528: \n\r
+ *     static __INLINE void NVIC_DisableIRQ(uint32_t IRQn) \n\r
+ *     Warning 528: Symbol 'NVIC_DisableIRQ(unsigned int)' (line 419, file ./cm3_core.h) not referenced\r
+ * .\r
+ *   - Error 751: \n\r
+ *     } InterruptType_Type; \n\r
+ *     Info 751: local typedef 'InterruptType_Type' (line 170, file ./cm3_core.h) not referenced\r
+ * .\r
+ * Note:  To re-enable a Message, insert a space before 'lint' *\r
+ *\r
+ */\r
+\r
+/*lint -save */\r
+/*lint -e10  */\r
+/*lint -e530 */\r
+/*lint -e550 */\r
+/*lint -e754 */\r
+/*lint -e750 */\r
+/*lint -e528 */\r
+/*lint -e751 */\r
+\r
+\r
+/** @addtogroup CMSIS_CM3_core_definitions CM3 Core Definitions\r
+  This file defines all structures and symbols for CMSIS core:\r
+    - CMSIS version number\r
+    - Cortex-M core registers and bitfields\r
+    - Cortex-M core peripheral base address\r
+  @{\r
+ */\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+#define __CM3_CMSIS_VERSION_MAIN  (0x01)                                                       /*!< [31:16] CMSIS HAL main version */\r
+#define __CM3_CMSIS_VERSION_SUB   (0x30)                                                       /*!< [15:0]  CMSIS HAL sub version  */\r
+#define __CM3_CMSIS_VERSION       ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number       */\r
+\r
+#define __CORTEX_M                (0x03)                                                       /*!< Cortex core                    */\r
+\r
+#include <stdint.h>                           /* Include standard types */\r
+\r
+#if defined (__ICCARM__)\r
+  #include <intrinsics.h>                     /* IAR Intrinsics   */\r
+#endif\r
+\r
+\r
+#ifndef __NVIC_PRIO_BITS\r
+  #define __NVIC_PRIO_BITS    4               /*!< standard definition for NVIC Priority Bits */\r
+#endif\r
+\r
+\r
+\r
+\r
+/**\r
+ * IO definitions\r
+ *\r
+ * define access restrictions to peripheral registers\r
+ */\r
+\r
+#ifdef __cplusplus\r
+  #define     __I     volatile                /*!< defines 'read only' permissions      */\r
+#else\r
+  #define     __I     volatile const          /*!< defines 'read only' permissions      */\r
+#endif\r
+#define     __O     volatile                  /*!< defines 'write only' permissions     */\r
+#define     __IO    volatile                  /*!< defines 'read / write' permissions   */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ *                 Register Abstraction\r
+ ******************************************************************************/\r
+/** @addtogroup CMSIS_CM3_core_register CMSIS CM3 Core Register\r
+ @{\r
+*/\r
+\r
+\r
+/** @addtogroup CMSIS_CM3_NVIC CMSIS CM3 NVIC\r
+  memory mapped structure for Nested Vectored Interrupt Controller (NVIC)\r
+  @{\r
+ */\r
+typedef struct\r
+{\r
+  __IO uint32_t ISER[8];                      /*!< Offset: 0x000  Interrupt Set Enable Register           */\r
+       uint32_t RESERVED0[24];\r
+  __IO uint32_t ICER[8];                      /*!< Offset: 0x080  Interrupt Clear Enable Register         */\r
+       uint32_t RSERVED1[24];\r
+  __IO uint32_t ISPR[8];                      /*!< Offset: 0x100  Interrupt Set Pending Register          */\r
+       uint32_t RESERVED2[24];\r
+  __IO uint32_t ICPR[8];                      /*!< Offset: 0x180  Interrupt Clear Pending Register        */\r
+       uint32_t RESERVED3[24];\r
+  __IO uint32_t IABR[8];                      /*!< Offset: 0x200  Interrupt Active bit Register           */\r
+       uint32_t RESERVED4[56];\r
+  __IO uint8_t  IP[240];                      /*!< Offset: 0x300  Interrupt Priority Register (8Bit wide) */\r
+       uint32_t RESERVED5[644];\r
+  __O  uint32_t STIR;                         /*!< Offset: 0xE00  Software Trigger Interrupt Register     */\r
+}  NVIC_Type;\r
+/*@}*/ /* end of group CMSIS_CM3_NVIC */\r
+\r
+\r
+/** @addtogroup CMSIS_CM3_SCB CMSIS CM3 SCB\r
+  memory mapped structure for System Control Block (SCB)\r
+  @{\r
+ */\r
+typedef struct\r
+{\r
+  __I  uint32_t CPUID;                        /*!< Offset: 0x00  CPU ID Base Register                                  */\r
+  __IO uint32_t ICSR;                         /*!< Offset: 0x04  Interrupt Control State Register                      */\r
+  __IO uint32_t VTOR;                         /*!< Offset: 0x08  Vector Table Offset Register                          */\r
+  __IO uint32_t AIRCR;                        /*!< Offset: 0x0C  Application Interrupt / Reset Control Register        */\r
+  __IO uint32_t SCR;                          /*!< Offset: 0x10  System Control Register                               */\r
+  __IO uint32_t CCR;                          /*!< Offset: 0x14  Configuration Control Register                        */\r
+  __IO uint8_t  SHP[12];                      /*!< Offset: 0x18  System Handlers Priority Registers (4-7, 8-11, 12-15) */\r
+  __IO uint32_t SHCSR;                        /*!< Offset: 0x24  System Handler Control and State Register             */\r
+  __IO uint32_t CFSR;                         /*!< Offset: 0x28  Configurable Fault Status Register                    */\r
+  __IO uint32_t HFSR;                         /*!< Offset: 0x2C  Hard Fault Status Register                            */\r
+  __IO uint32_t DFSR;                         /*!< Offset: 0x30  Debug Fault Status Register                           */\r
+  __IO uint32_t MMFAR;                        /*!< Offset: 0x34  Mem Manage Address Register                           */\r
+  __IO uint32_t BFAR;                         /*!< Offset: 0x38  Bus Fault Address Register                            */\r
+  __IO uint32_t AFSR;                         /*!< Offset: 0x3C  Auxiliary Fault Status Register                       */\r
+  __I  uint32_t PFR[2];                       /*!< Offset: 0x40  Processor Feature Register                            */\r
+  __I  uint32_t DFR;                          /*!< Offset: 0x48  Debug Feature Register                                */\r
+  __I  uint32_t ADR;                          /*!< Offset: 0x4C  Auxiliary Feature Register                            */\r
+  __I  uint32_t MMFR[4];                      /*!< Offset: 0x50  Memory Model Feature Register                         */\r
+  __I  uint32_t ISAR[5];                      /*!< Offset: 0x60  ISA Feature Register                                  */\r
+} SCB_Type;\r
+\r
+/* SCB CPUID Register Definitions */\r
+#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */\r
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFul << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */\r
+\r
+#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */\r
+#define SCB_CPUID_VARIANT_Msk              (0xFul << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */\r
+\r
+#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */\r
+#define SCB_CPUID_PARTNO_Msk               (0xFFFul << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */\r
+\r
+#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */\r
+#define SCB_CPUID_REVISION_Msk             (0xFul << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */\r
+\r
+/* SCB Interrupt Control State Register Definitions */\r
+#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */\r
+#define SCB_ICSR_NMIPENDSET_Msk            (1ul << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */\r
+#define SCB_ICSR_PENDSVSET_Msk             (1ul << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */\r
+#define SCB_ICSR_PENDSVCLR_Msk             (1ul << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */\r
+\r
+#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */\r
+#define SCB_ICSR_PENDSTSET_Msk             (1ul << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */\r
+\r
+#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */\r
+#define SCB_ICSR_PENDSTCLR_Msk             (1ul << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */\r
+\r
+#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */\r
+#define SCB_ICSR_ISRPREEMPT_Msk            (1ul << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */\r
+\r
+#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */\r
+#define SCB_ICSR_ISRPENDING_Msk            (1ul << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */\r
+\r
+#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */\r
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFul << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */\r
+\r
+#define SCB_ICSR_RETTOBASE_Pos             11                                             /*!< SCB ICSR: RETTOBASE Position */\r
+#define SCB_ICSR_RETTOBASE_Msk             (1ul << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */\r
+\r
+#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */\r
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFul << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */\r
+\r
+/* SCB Interrupt Control State Register Definitions */\r
+#define SCB_VTOR_TBLBASE_Pos               29                                             /*!< SCB VTOR: TBLBASE Position */\r
+#define SCB_VTOR_TBLBASE_Msk               (0x1FFul << SCB_VTOR_TBLBASE_Pos)              /*!< SCB VTOR: TBLBASE Mask */\r
+\r
+#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */\r
+#define SCB_VTOR_TBLOFF_Msk                (0x3FFFFFul << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */\r
+\r
+/* SCB Application Interrupt and Reset Control Register Definitions */\r
+#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */\r
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFul << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */\r
+\r
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */\r
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFul << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */\r
+\r
+#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */\r
+#define SCB_AIRCR_ENDIANESS_Msk            (1ul << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */\r
+\r
+#define SCB_AIRCR_PRIGROUP_Pos              8                                             /*!< SCB AIRCR: PRIGROUP Position */\r
+#define SCB_AIRCR_PRIGROUP_Msk             (7ul << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */\r
+\r
+#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */\r
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1ul << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */\r
+\r
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */\r
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1ul << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r
+\r
+#define SCB_AIRCR_VECTRESET_Pos             0                                             /*!< SCB AIRCR: VECTRESET Position */\r
+#define SCB_AIRCR_VECTRESET_Msk            (1ul << SCB_AIRCR_VECTRESET_Pos)               /*!< SCB AIRCR: VECTRESET Mask */\r
+\r
+/* SCB System Control Register Definitions */\r
+#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */\r
+#define SCB_SCR_SEVONPEND_Msk              (1ul << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */\r
+\r
+#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */\r
+#define SCB_SCR_SLEEPDEEP_Msk              (1ul << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */\r
+\r
+#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */\r
+#define SCB_SCR_SLEEPONEXIT_Msk            (1ul << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */\r
+\r
+/* SCB Configuration Control Register Definitions */\r
+#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */\r
+#define SCB_CCR_STKALIGN_Msk               (1ul << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */\r
+\r
+#define SCB_CCR_BFHFNMIGN_Pos               8                                             /*!< SCB CCR: BFHFNMIGN Position */\r
+#define SCB_CCR_BFHFNMIGN_Msk              (1ul << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */\r
+\r
+#define SCB_CCR_DIV_0_TRP_Pos               4                                             /*!< SCB CCR: DIV_0_TRP Position */\r
+#define SCB_CCR_DIV_0_TRP_Msk              (1ul << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */\r
+\r
+#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */\r
+#define SCB_CCR_UNALIGN_TRP_Msk            (1ul << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */\r
+\r
+#define SCB_CCR_USERSETMPEND_Pos            1                                             /*!< SCB CCR: USERSETMPEND Position */\r
+#define SCB_CCR_USERSETMPEND_Msk           (1ul << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */\r
+\r
+#define SCB_CCR_NONBASETHRDENA_Pos          0                                             /*!< SCB CCR: NONBASETHRDENA Position */\r
+#define SCB_CCR_NONBASETHRDENA_Msk         (1ul << SCB_CCR_NONBASETHRDENA_Pos)            /*!< SCB CCR: NONBASETHRDENA Mask */\r
+\r
+/* SCB System Handler Control and State Register Definitions */\r
+#define SCB_SHCSR_USGFAULTENA_Pos          18                                             /*!< SCB SHCSR: USGFAULTENA Position */\r
+#define SCB_SHCSR_USGFAULTENA_Msk          (1ul << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTENA_Pos          17                                             /*!< SCB SHCSR: BUSFAULTENA Position */\r
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1ul << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTENA_Pos          16                                             /*!< SCB SHCSR: MEMFAULTENA Position */\r
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1ul << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */\r
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1ul << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14                                             /*!< SCB SHCSR: BUSFAULTPENDED Position */\r
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1ul << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13                                             /*!< SCB SHCSR: MEMFAULTPENDED Position */\r
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1ul << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12                                             /*!< SCB SHCSR: USGFAULTPENDED Position */\r
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1ul << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_SYSTICKACT_Pos           11                                             /*!< SCB SHCSR: SYSTICKACT Position */\r
+#define SCB_SHCSR_SYSTICKACT_Msk           (1ul << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */\r
+\r
+#define SCB_SHCSR_PENDSVACT_Pos            10                                             /*!< SCB SHCSR: PENDSVACT Position */\r
+#define SCB_SHCSR_PENDSVACT_Msk            (1ul << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */\r
+\r
+#define SCB_SHCSR_MONITORACT_Pos            8                                             /*!< SCB SHCSR: MONITORACT Position */\r
+#define SCB_SHCSR_MONITORACT_Msk           (1ul << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */\r
+\r
+#define SCB_SHCSR_SVCALLACT_Pos             7                                             /*!< SCB SHCSR: SVCALLACT Position */\r
+#define SCB_SHCSR_SVCALLACT_Msk            (1ul << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */\r
+\r
+#define SCB_SHCSR_USGFAULTACT_Pos           3                                             /*!< SCB SHCSR: USGFAULTACT Position */\r
+#define SCB_SHCSR_USGFAULTACT_Msk          (1ul << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTACT_Pos           1                                             /*!< SCB SHCSR: BUSFAULTACT Position */\r
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1ul << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTACT_Pos           0                                             /*!< SCB SHCSR: MEMFAULTACT Position */\r
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1ul << SCB_SHCSR_MEMFAULTACT_Pos)             /*!< SCB SHCSR: MEMFAULTACT Mask */\r
+\r
+/* SCB Configurable Fault Status Registers Definitions */\r
+#define SCB_CFSR_USGFAULTSR_Pos            16                                             /*!< SCB CFSR: Usage Fault Status Register Position */\r
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFul << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */\r
+\r
+#define SCB_CFSR_BUSFAULTSR_Pos             8                                             /*!< SCB CFSR: Bus Fault Status Register Position */\r
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFul << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */\r
+\r
+#define SCB_CFSR_MEMFAULTSR_Pos             0                                             /*!< SCB CFSR: Memory Manage Fault Status Register Position */\r
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFul << SCB_CFSR_MEMFAULTSR_Pos)            /*!< SCB CFSR: Memory Manage Fault Status Register Mask */\r
+\r
+/* SCB Hard Fault Status Registers Definitions */\r
+#define SCB_HFSR_DEBUGEVT_Pos              31                                             /*!< SCB HFSR: DEBUGEVT Position */\r
+#define SCB_HFSR_DEBUGEVT_Msk              (1ul << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */\r
+\r
+#define SCB_HFSR_FORCED_Pos                30                                             /*!< SCB HFSR: FORCED Position */\r
+#define SCB_HFSR_FORCED_Msk                (1ul << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */\r
+\r
+#define SCB_HFSR_VECTTBL_Pos                1                                             /*!< SCB HFSR: VECTTBL Position */\r
+#define SCB_HFSR_VECTTBL_Msk               (1ul << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */\r
+\r
+/* SCB Debug Fault Status Register Definitions */\r
+#define SCB_DFSR_EXTERNAL_Pos               4                                             /*!< SCB DFSR: EXTERNAL Position */\r
+#define SCB_DFSR_EXTERNAL_Msk              (1ul << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */\r
+\r
+#define SCB_DFSR_VCATCH_Pos                 3                                             /*!< SCB DFSR: VCATCH Position */\r
+#define SCB_DFSR_VCATCH_Msk                (1ul << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */\r
+\r
+#define SCB_DFSR_DWTTRAP_Pos                2                                             /*!< SCB DFSR: DWTTRAP Position */\r
+#define SCB_DFSR_DWTTRAP_Msk               (1ul << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */\r
+\r
+#define SCB_DFSR_BKPT_Pos                   1                                             /*!< SCB DFSR: BKPT Position */\r
+#define SCB_DFSR_BKPT_Msk                  (1ul << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */\r
+\r
+#define SCB_DFSR_HALTED_Pos                 0                                             /*!< SCB DFSR: HALTED Position */\r
+#define SCB_DFSR_HALTED_Msk                (1ul << SCB_DFSR_HALTED_Pos)                   /*!< SCB DFSR: HALTED Mask */\r
+/*@}*/ /* end of group CMSIS_CM3_SCB */\r
+\r
+\r
+/** @addtogroup CMSIS_CM3_SysTick CMSIS CM3 SysTick\r
+  memory mapped structure for SysTick\r
+  @{\r
+ */\r
+typedef struct\r
+{\r
+  __IO uint32_t CTRL;                         /*!< Offset: 0x00  SysTick Control and Status Register */\r
+  __IO uint32_t LOAD;                         /*!< Offset: 0x04  SysTick Reload Value Register       */\r
+  __IO uint32_t VAL;                          /*!< Offset: 0x08  SysTick Current Value Register      */\r
+  __I  uint32_t CALIB;                        /*!< Offset: 0x0C  SysTick Calibration Register        */\r
+} SysTick_Type;\r
+\r
+/* SysTick Control / Status Register Definitions */\r
+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */\r
+#define SysTick_CTRL_COUNTFLAG_Msk         (1ul << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */\r
+\r
+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */\r
+#define SysTick_CTRL_CLKSOURCE_Msk         (1ul << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */\r
+\r
+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */\r
+#define SysTick_CTRL_TICKINT_Msk           (1ul << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */\r
+\r
+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */\r
+#define SysTick_CTRL_ENABLE_Msk            (1ul << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */\r
+\r
+/* SysTick Reload Register Definitions */\r
+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */\r
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFul << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */\r
+\r
+/* SysTick Current Register Definitions */\r
+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */\r
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFul << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */\r
+\r
+/* SysTick Calibration Register Definitions */\r
+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */\r
+#define SysTick_CALIB_NOREF_Msk            (1ul << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */\r
+\r
+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */\r
+#define SysTick_CALIB_SKEW_Msk             (1ul << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */\r
+\r
+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */\r
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFul << SysTick_VAL_CURRENT_Pos)        /*!< SysTick CALIB: TENMS Mask */\r
+/*@}*/ /* end of group CMSIS_CM3_SysTick */\r
+\r
+\r
+/** @addtogroup CMSIS_CM3_ITM CMSIS CM3 ITM\r
+  memory mapped structure for Instrumentation Trace Macrocell (ITM)\r
+  @{\r
+ */\r
+typedef struct\r
+{\r
+  __O  union\r
+  {\r
+    __O  uint8_t    u8;                       /*!< Offset:       ITM Stimulus Port 8-bit                   */\r
+    __O  uint16_t   u16;                      /*!< Offset:       ITM Stimulus Port 16-bit                  */\r
+    __O  uint32_t   u32;                      /*!< Offset:       ITM Stimulus Port 32-bit                  */\r
+  }  PORT [32];                               /*!< Offset: 0x00  ITM Stimulus Port Registers               */\r
+       uint32_t RESERVED0[864];\r
+  __IO uint32_t TER;                          /*!< Offset:       ITM Trace Enable Register                 */\r
+       uint32_t RESERVED1[15];\r
+  __IO uint32_t TPR;                          /*!< Offset:       ITM Trace Privilege Register              */\r
+       uint32_t RESERVED2[15];\r
+  __IO uint32_t TCR;                          /*!< Offset:       ITM Trace Control Register                */\r
+       uint32_t RESERVED3[29];\r
+  __IO uint32_t IWR;                          /*!< Offset:       ITM Integration Write Register            */\r
+  __IO uint32_t IRR;                          /*!< Offset:       ITM Integration Read Register             */\r
+  __IO uint32_t IMCR;                         /*!< Offset:       ITM Integration Mode Control Register     */\r
+       uint32_t RESERVED4[43];\r
+  __IO uint32_t LAR;                          /*!< Offset:       ITM Lock Access Register                  */\r
+  __IO uint32_t LSR;                          /*!< Offset:       ITM Lock Status Register                  */\r
+       uint32_t RESERVED5[6];\r
+  __I  uint32_t PID4;                         /*!< Offset:       ITM Peripheral Identification Register #4 */\r
+  __I  uint32_t PID5;                         /*!< Offset:       ITM Peripheral Identification Register #5 */\r
+  __I  uint32_t PID6;                         /*!< Offset:       ITM Peripheral Identification Register #6 */\r
+  __I  uint32_t PID7;                         /*!< Offset:       ITM Peripheral Identification Register #7 */\r
+  __I  uint32_t PID0;                         /*!< Offset:       ITM Peripheral Identification Register #0 */\r
+  __I  uint32_t PID1;                         /*!< Offset:       ITM Peripheral Identification Register #1 */\r
+  __I  uint32_t PID2;                         /*!< Offset:       ITM Peripheral Identification Register #2 */\r
+  __I  uint32_t PID3;                         /*!< Offset:       ITM Peripheral Identification Register #3 */\r
+  __I  uint32_t CID0;                         /*!< Offset:       ITM Component  Identification Register #0 */\r
+  __I  uint32_t CID1;                         /*!< Offset:       ITM Component  Identification Register #1 */\r
+  __I  uint32_t CID2;                         /*!< Offset:       ITM Component  Identification Register #2 */\r
+  __I  uint32_t CID3;                         /*!< Offset:       ITM Component  Identification Register #3 */\r
+} ITM_Type;\r
+\r
+/* ITM Trace Privilege Register Definitions */\r
+#define ITM_TPR_PRIVMASK_Pos                0                                             /*!< ITM TPR: PRIVMASK Position */\r
+#define ITM_TPR_PRIVMASK_Msk               (0xFul << ITM_TPR_PRIVMASK_Pos)                /*!< ITM TPR: PRIVMASK Mask */\r
+\r
+/* ITM Trace Control Register Definitions */\r
+#define ITM_TCR_BUSY_Pos                   23                                             /*!< ITM TCR: BUSY Position */\r
+#define ITM_TCR_BUSY_Msk                   (1ul << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */\r
+\r
+#define ITM_TCR_ATBID_Pos                  16                                             /*!< ITM TCR: ATBID Position */\r
+#define ITM_TCR_ATBID_Msk                  (0x7Ful << ITM_TCR_ATBID_Pos)                  /*!< ITM TCR: ATBID Mask */\r
+\r
+#define ITM_TCR_TSPrescale_Pos              8                                             /*!< ITM TCR: TSPrescale Position */\r
+#define ITM_TCR_TSPrescale_Msk             (3ul << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */\r
+\r
+#define ITM_TCR_SWOENA_Pos                  4                                             /*!< ITM TCR: SWOENA Position */\r
+#define ITM_TCR_SWOENA_Msk                 (1ul << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */\r
+\r
+#define ITM_TCR_DWTENA_Pos                  3                                             /*!< ITM TCR: DWTENA Position */\r
+#define ITM_TCR_DWTENA_Msk                 (1ul << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */\r
+\r
+#define ITM_TCR_SYNCENA_Pos                 2                                             /*!< ITM TCR: SYNCENA Position */\r
+#define ITM_TCR_SYNCENA_Msk                (1ul << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */\r
+\r
+#define ITM_TCR_TSENA_Pos                   1                                             /*!< ITM TCR: TSENA Position */\r
+#define ITM_TCR_TSENA_Msk                  (1ul << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */\r
+\r
+#define ITM_TCR_ITMENA_Pos                  0                                             /*!< ITM TCR: ITM Enable bit Position */\r
+#define ITM_TCR_ITMENA_Msk                 (1ul << ITM_TCR_ITMENA_Pos)                    /*!< ITM TCR: ITM Enable bit Mask */\r
+\r
+/* ITM Integration Write Register Definitions */\r
+#define ITM_IWR_ATVALIDM_Pos                0                                             /*!< ITM IWR: ATVALIDM Position */\r
+#define ITM_IWR_ATVALIDM_Msk               (1ul << ITM_IWR_ATVALIDM_Pos)                  /*!< ITM IWR: ATVALIDM Mask */\r
+\r
+/* ITM Integration Read Register Definitions */\r
+#define ITM_IRR_ATREADYM_Pos                0                                             /*!< ITM IRR: ATREADYM Position */\r
+#define ITM_IRR_ATREADYM_Msk               (1ul << ITM_IRR_ATREADYM_Pos)                  /*!< ITM IRR: ATREADYM Mask */\r
+\r
+/* ITM Integration Mode Control Register Definitions */\r
+#define ITM_IMCR_INTEGRATION_Pos            0                                             /*!< ITM IMCR: INTEGRATION Position */\r
+#define ITM_IMCR_INTEGRATION_Msk           (1ul << ITM_IMCR_INTEGRATION_Pos)              /*!< ITM IMCR: INTEGRATION Mask */\r
+\r
+/* ITM Lock Status Register Definitions */\r
+#define ITM_LSR_ByteAcc_Pos                 2                                             /*!< ITM LSR: ByteAcc Position */\r
+#define ITM_LSR_ByteAcc_Msk                (1ul << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */\r
+\r
+#define ITM_LSR_Access_Pos                  1                                             /*!< ITM LSR: Access Position */\r
+#define ITM_LSR_Access_Msk                 (1ul << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */\r
+\r
+#define ITM_LSR_Present_Pos                 0                                             /*!< ITM LSR: Present Position */\r
+#define ITM_LSR_Present_Msk                (1ul << ITM_LSR_Present_Pos)                   /*!< ITM LSR: Present Mask */\r
+/*@}*/ /* end of group CMSIS_CM3_ITM */\r
+\r
+\r
+/** @addtogroup CMSIS_CM3_InterruptType CMSIS CM3 Interrupt Type\r
+  memory mapped structure for Interrupt Type\r
+  @{\r
+ */\r
+typedef struct\r
+{\r
+       uint32_t RESERVED0;\r
+  __I  uint32_t ICTR;                         /*!< Offset: 0x04  Interrupt Control Type Register */\r
+#if ((defined __CM3_REV) && (__CM3_REV >= 0x200))\r
+  __IO uint32_t ACTLR;                        /*!< Offset: 0x08  Auxiliary Control Register      */\r
+#else\r
+       uint32_t RESERVED1;\r
+#endif\r
+} InterruptType_Type;\r
+\r
+/* Interrupt Controller Type Register Definitions */\r
+#define InterruptType_ICTR_INTLINESNUM_Pos  0                                             /*!< InterruptType ICTR: INTLINESNUM Position */\r
+#define InterruptType_ICTR_INTLINESNUM_Msk (0x1Ful << InterruptType_ICTR_INTLINESNUM_Pos) /*!< InterruptType ICTR: INTLINESNUM Mask */\r
+\r
+/* Auxiliary Control Register Definitions */\r
+#define InterruptType_ACTLR_DISFOLD_Pos     2                                             /*!< InterruptType ACTLR: DISFOLD Position */\r
+#define InterruptType_ACTLR_DISFOLD_Msk    (1ul << InterruptType_ACTLR_DISFOLD_Pos)       /*!< InterruptType ACTLR: DISFOLD Mask */\r
+\r
+#define InterruptType_ACTLR_DISDEFWBUF_Pos  1                                             /*!< InterruptType ACTLR: DISDEFWBUF Position */\r
+#define InterruptType_ACTLR_DISDEFWBUF_Msk (1ul << InterruptType_ACTLR_DISDEFWBUF_Pos)    /*!< InterruptType ACTLR: DISDEFWBUF Mask */\r
+\r
+#define InterruptType_ACTLR_DISMCYCINT_Pos  0                                             /*!< InterruptType ACTLR: DISMCYCINT Position */\r
+#define InterruptType_ACTLR_DISMCYCINT_Msk (1ul << InterruptType_ACTLR_DISMCYCINT_Pos)    /*!< InterruptType ACTLR: DISMCYCINT Mask */\r
+/*@}*/ /* end of group CMSIS_CM3_InterruptType */\r
+\r
+\r
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1)\r
+/** @addtogroup CMSIS_CM3_MPU CMSIS CM3 MPU\r
+  memory mapped structure for Memory Protection Unit (MPU)\r
+  @{\r
+ */\r
+typedef struct\r
+{\r
+  __I  uint32_t TYPE;                         /*!< Offset: 0x00  MPU Type Register                              */\r
+  __IO uint32_t CTRL;                         /*!< Offset: 0x04  MPU Control Register                           */\r
+  __IO uint32_t RNR;                          /*!< Offset: 0x08  MPU Region RNRber Register                     */\r
+  __IO uint32_t RBAR;                         /*!< Offset: 0x0C  MPU Region Base Address Register               */\r
+  __IO uint32_t RASR;                         /*!< Offset: 0x10  MPU Region Attribute and Size Register         */\r
+  __IO uint32_t RBAR_A1;                      /*!< Offset: 0x14  MPU Alias 1 Region Base Address Register       */\r
+  __IO uint32_t RASR_A1;                      /*!< Offset: 0x18  MPU Alias 1 Region Attribute and Size Register */\r
+  __IO uint32_t RBAR_A2;                      /*!< Offset: 0x1C  MPU Alias 2 Region Base Address Register       */\r
+  __IO uint32_t RASR_A2;                      /*!< Offset: 0x20  MPU Alias 2 Region Attribute and Size Register */\r
+  __IO uint32_t RBAR_A3;                      /*!< Offset: 0x24  MPU Alias 3 Region Base Address Register       */\r
+  __IO uint32_t RASR_A3;                      /*!< Offset: 0x28  MPU Alias 3 Region Attribute and Size Register */\r
+} MPU_Type;\r
+\r
+/* MPU Type Register */\r
+#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */\r
+#define MPU_TYPE_IREGION_Msk               (0xFFul << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */\r
+\r
+#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */\r
+#define MPU_TYPE_DREGION_Msk               (0xFFul << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */\r
+\r
+#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */\r
+#define MPU_TYPE_SEPARATE_Msk              (1ul << MPU_TYPE_SEPARATE_Pos)                 /*!< MPU TYPE: SEPARATE Mask */\r
+\r
+/* MPU Control Register */\r
+#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */\r
+#define MPU_CTRL_PRIVDEFENA_Msk            (1ul << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */\r
+\r
+#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */\r
+#define MPU_CTRL_HFNMIENA_Msk              (1ul << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */\r
+\r
+#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */\r
+#define MPU_CTRL_ENABLE_Msk                (1ul << MPU_CTRL_ENABLE_Pos)                   /*!< MPU CTRL: ENABLE Mask */\r
+\r
+/* MPU Region Number Register */\r
+#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */\r
+#define MPU_RNR_REGION_Msk                 (0xFFul << MPU_RNR_REGION_Pos)                 /*!< MPU RNR: REGION Mask */\r
+\r
+/* MPU Region Base Address Register */\r
+#define MPU_RBAR_ADDR_Pos                   5                                             /*!< MPU RBAR: ADDR Position */\r
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFul << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */\r
+\r
+#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */\r
+#define MPU_RBAR_VALID_Msk                 (1ul << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */\r
+\r
+#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */\r
+#define MPU_RBAR_REGION_Msk                (0xFul << MPU_RBAR_REGION_Pos)                 /*!< MPU RBAR: REGION Mask */\r
+\r
+/* MPU Region Attribute and Size Register */\r
+#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: XN Position */\r
+#define MPU_RASR_XN_Msk                    (1ul << MPU_RASR_XN_Pos)                       /*!< MPU RASR: XN Mask */\r
+\r
+#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: AP Position */\r
+#define MPU_RASR_AP_Msk                    (7ul << MPU_RASR_AP_Pos)                       /*!< MPU RASR: AP Mask */\r
+\r
+#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: TEX Position */\r
+#define MPU_RASR_TEX_Msk                   (7ul << MPU_RASR_TEX_Pos)                      /*!< MPU RASR: TEX Mask */\r
+\r
+#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: Shareable bit Position */\r
+#define MPU_RASR_S_Msk                     (1ul << MPU_RASR_S_Pos)                        /*!< MPU RASR: Shareable bit Mask */\r
+\r
+#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: Cacheable bit Position */\r
+#define MPU_RASR_C_Msk                     (1ul << MPU_RASR_C_Pos)                        /*!< MPU RASR: Cacheable bit Mask */\r
+\r
+#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: Bufferable bit Position */\r
+#define MPU_RASR_B_Msk                     (1ul << MPU_RASR_B_Pos)                        /*!< MPU RASR: Bufferable bit Mask */\r
+\r
+#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */\r
+#define MPU_RASR_SRD_Msk                   (0xFFul << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */\r
+\r
+#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */\r
+#define MPU_RASR_SIZE_Msk                  (0x1Ful << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */\r
+\r
+#define MPU_RASR_ENA_Pos                     0                                            /*!< MPU RASR: Region enable bit Position */\r
+#define MPU_RASR_ENA_Msk                    (0x1Ful << MPU_RASR_ENA_Pos)                  /*!< MPU RASR: Region enable bit Disable Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_CM3_MPU */\r
+#endif\r
+\r
+\r
+/** @addtogroup CMSIS_CM3_CoreDebug CMSIS CM3 Core Debug\r
+  memory mapped structure for Core Debug Register\r
+  @{\r
+ */\r
+typedef struct\r
+{\r
+  __IO uint32_t DHCSR;                        /*!< Offset: 0x00  Debug Halting Control and Status Register    */\r
+  __O  uint32_t DCRSR;                        /*!< Offset: 0x04  Debug Core Register Selector Register        */\r
+  __IO uint32_t DCRDR;                        /*!< Offset: 0x08  Debug Core Register Data Register            */\r
+  __IO uint32_t DEMCR;                        /*!< Offset: 0x0C  Debug Exception and Monitor Control Register */\r
+} CoreDebug_Type;\r
+\r
+/* Debug Halting Control and Status Register */\r
+#define CoreDebug_DHCSR_DBGKEY_Pos         16                                             /*!< CoreDebug DHCSR: DBGKEY Position */\r
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFul << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */\r
+\r
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25                                             /*!< CoreDebug DHCSR: S_RESET_ST Position */\r
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1ul << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */\r
+\r
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24                                             /*!< CoreDebug DHCSR: S_RETIRE_ST Position */\r
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1ul << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */\r
+\r
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19                                             /*!< CoreDebug DHCSR: S_LOCKUP Position */\r
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1ul << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */\r
+\r
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18                                             /*!< CoreDebug DHCSR: S_SLEEP Position */\r
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1ul << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */\r
+\r
+#define CoreDebug_DHCSR_S_HALT_Pos         17                                             /*!< CoreDebug DHCSR: S_HALT Position */\r
+#define CoreDebug_DHCSR_S_HALT_Msk         (1ul << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */\r
+\r
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16                                             /*!< CoreDebug DHCSR: S_REGRDY Position */\r
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1ul << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */\r
+\r
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5                                             /*!< CoreDebug DHCSR: C_SNAPSTALL Position */\r
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1ul << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */\r
+\r
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3                                             /*!< CoreDebug DHCSR: C_MASKINTS Position */\r
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1ul << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */\r
+\r
+#define CoreDebug_DHCSR_C_STEP_Pos          2                                             /*!< CoreDebug DHCSR: C_STEP Position */\r
+#define CoreDebug_DHCSR_C_STEP_Msk         (1ul << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */\r
+\r
+#define CoreDebug_DHCSR_C_HALT_Pos          1                                             /*!< CoreDebug DHCSR: C_HALT Position */\r
+#define CoreDebug_DHCSR_C_HALT_Msk         (1ul << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */\r
+\r
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0                                             /*!< CoreDebug DHCSR: C_DEBUGEN Position */\r
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1ul << CoreDebug_DHCSR_C_DEBUGEN_Pos)         /*!< CoreDebug DHCSR: C_DEBUGEN Mask */\r
+\r
+/* Debug Core Register Selector Register */\r
+#define CoreDebug_DCRSR_REGWnR_Pos         16                                             /*!< CoreDebug DCRSR: REGWnR Position */\r
+#define CoreDebug_DCRSR_REGWnR_Msk         (1ul << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */\r
+\r
+#define CoreDebug_DCRSR_REGSEL_Pos          0                                             /*!< CoreDebug DCRSR: REGSEL Position */\r
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1Ful << CoreDebug_DCRSR_REGSEL_Pos)         /*!< CoreDebug DCRSR: REGSEL Mask */\r
+\r
+/* Debug Exception and Monitor Control Register */\r
+#define CoreDebug_DEMCR_TRCENA_Pos         24                                             /*!< CoreDebug DEMCR: TRCENA Position */\r
+#define CoreDebug_DEMCR_TRCENA_Msk         (1ul << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_REQ_Pos        19                                             /*!< CoreDebug DEMCR: MON_REQ Position */\r
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1ul << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_STEP_Pos       18                                             /*!< CoreDebug DEMCR: MON_STEP Position */\r
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1ul << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_PEND_Pos       17                                             /*!< CoreDebug DEMCR: MON_PEND Position */\r
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1ul << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_EN_Pos         16                                             /*!< CoreDebug DEMCR: MON_EN Position */\r
+#define CoreDebug_DEMCR_MON_EN_Msk         (1ul << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10                                             /*!< CoreDebug DEMCR: VC_HARDERR Position */\r
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1ul << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9                                             /*!< CoreDebug DEMCR: VC_INTERR Position */\r
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1ul << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8                                             /*!< CoreDebug DEMCR: VC_BUSERR Position */\r
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1ul << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7                                             /*!< CoreDebug DEMCR: VC_STATERR Position */\r
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1ul << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6                                             /*!< CoreDebug DEMCR: VC_CHKERR Position */\r
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1ul << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5                                             /*!< CoreDebug DEMCR: VC_NOCPERR Position */\r
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1ul << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4                                             /*!< CoreDebug DEMCR: VC_MMERR Position */\r
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1ul << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0                                             /*!< CoreDebug DEMCR: VC_CORERESET Position */\r
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1ul << CoreDebug_DEMCR_VC_CORERESET_Pos)      /*!< CoreDebug DEMCR: VC_CORERESET Mask */\r
+/*@}*/ /* end of group CMSIS_CM3_CoreDebug */\r
+\r
+\r
+/* Memory mapping of Cortex-M3 Hardware */\r
+#define SCS_BASE            (0xE000E000)                              /*!< System Control Space Base Address */\r
+#define ITM_BASE            (0xE0000000)                              /*!< ITM Base Address                  */\r
+#define CoreDebug_BASE      (0xE000EDF0)                              /*!< Core Debug Base Address           */\r
+#define SysTick_BASE        (SCS_BASE +  0x0010)                      /*!< SysTick Base Address              */\r
+#define NVIC_BASE           (SCS_BASE +  0x0100)                      /*!< NVIC Base Address                 */\r
+#define SCB_BASE            (SCS_BASE +  0x0D00)                      /*!< System Control Block Base Address */\r
+\r
+#define InterruptType       ((InterruptType_Type *) SCS_BASE)         /*!< Interrupt Type Register           */\r
+#define SCB                 ((SCB_Type *)           SCB_BASE)         /*!< SCB configuration struct          */\r
+#define SysTick             ((SysTick_Type *)       SysTick_BASE)     /*!< SysTick configuration struct      */\r
+#define NVIC                ((NVIC_Type *)          NVIC_BASE)        /*!< NVIC configuration struct         */\r
+#define ITM                 ((ITM_Type *)           ITM_BASE)         /*!< ITM configuration struct          */\r
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct   */\r
+\r
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1)\r
+  #define MPU_BASE          (SCS_BASE +  0x0D90)                      /*!< Memory Protection Unit            */\r
+  #define MPU               ((MPU_Type*)            MPU_BASE)         /*!< Memory Protection Unit            */\r
+#endif\r
+\r
+/*@}*/ /* end of group CMSIS_CM3_core_register */\r
+\r
+\r
+/*******************************************************************************\r
+ *                Hardware Abstraction Layer\r
+ ******************************************************************************/\r
+\r
+#if defined ( __CC_ARM   )\r
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */\r
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */\r
+\r
+#elif defined ( __ICCARM__ )\r
+  #define __ASM           __asm                                       /*!< asm keyword for IAR Compiler          */\r
+  #define __INLINE        inline                                      /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */\r
+\r
+#elif defined   (  __GNUC__  )\r
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */\r
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */\r
+\r
+#elif defined   (  __TASKING__  )\r
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */\r
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */\r
+\r
+#endif\r
+\r
+\r
+/* ###################  Compiler specific Intrinsics  ########################### */\r
+\r
+#if defined ( __CC_ARM   ) /*------------------RealView Compiler -----------------*/\r
+/* ARM armcc specific functions */\r
+\r
+#define __enable_fault_irq                __enable_fiq\r
+#define __disable_fault_irq               __disable_fiq\r
+\r
+#define __NOP                             __nop\r
+#define __WFI                             __wfi\r
+#define __WFE                             __wfe\r
+#define __SEV                             __sev\r
+#define __ISB()                           __isb(0)\r
+#define __DSB()                           __dsb(0)\r
+#define __DMB()                           __dmb(0)\r
+#define __REV                             __rev\r
+#define __RBIT                            __rbit\r
+#define __LDREXB(ptr)                     ((unsigned char ) __ldrex(ptr))\r
+#define __LDREXH(ptr)                     ((unsigned short) __ldrex(ptr))\r
+#define __LDREXW(ptr)                     ((unsigned int  ) __ldrex(ptr))\r
+#define __STREXB(value, ptr)              __strex(value, ptr)\r
+#define __STREXH(value, ptr)              __strex(value, ptr)\r
+#define __STREXW(value, ptr)              __strex(value, ptr)\r
+\r
+\r
+/* intrinsic unsigned long long __ldrexd(volatile void *ptr) */\r
+/* intrinsic int __strexd(unsigned long long val, volatile void *ptr) */\r
+/* intrinsic void __enable_irq();     */\r
+/* intrinsic void __disable_irq();    */\r
+\r
+\r
+/**\r
+ * @brief  Return the Process Stack Pointer\r
+ *\r
+ * @return ProcessStackPointer\r
+ *\r
+ * Return the actual process stack pointer\r
+ */\r
+extern uint32_t __get_PSP(void);\r
+\r
+/**\r
+ * @brief  Set the Process Stack Pointer\r
+ *\r
+ * @param  topOfProcStack  Process Stack Pointer\r
+ *\r
+ * Assign the value ProcessStackPointer to the MSP\r
+ * (process stack pointer) Cortex processor register\r
+ */\r
+extern void __set_PSP(uint32_t topOfProcStack);\r
+\r
+/**\r
+ * @brief  Return the Main Stack Pointer\r
+ *\r
+ * @return Main Stack Pointer\r
+ *\r
+ * Return the current value of the MSP (main stack pointer)\r
+ * Cortex processor register\r
+ */\r
+extern uint32_t __get_MSP(void);\r
+\r
+/**\r
+ * @brief  Set the Main Stack Pointer\r
+ *\r
+ * @param  topOfMainStack  Main Stack Pointer\r
+ *\r
+ * Assign the value mainStackPointer to the MSP\r
+ * (main stack pointer) Cortex processor register\r
+ */\r
+extern void __set_MSP(uint32_t topOfMainStack);\r
+\r
+/**\r
+ * @brief  Reverse byte order in unsigned short value\r
+ *\r
+ * @param   value  value to reverse\r
+ * @return         reversed value\r
+ *\r
+ * Reverse byte order in unsigned short value\r
+ */\r
+extern uint32_t __REV16(uint16_t value);\r
+\r
+/**\r
+ * @brief  Reverse byte order in signed short value with sign extension to integer\r
+ *\r
+ * @param   value  value to reverse\r
+ * @return         reversed value\r
+ *\r
+ * Reverse byte order in signed short value with sign extension to integer\r
+ */\r
+extern int32_t __REVSH(int16_t value);\r
+\r
+\r
+#if (__ARMCC_VERSION < 400000)\r
+\r
+/**\r
+ * @brief  Remove the exclusive lock created by ldrex\r
+ *\r
+ * Removes the exclusive lock which is created by ldrex.\r
+ */\r
+extern void __CLREX(void);\r
+\r
+/**\r
+ * @brief  Return the Base Priority value\r
+ *\r
+ * @return BasePriority\r
+ *\r
+ * Return the content of the base priority register\r
+ */\r
+extern uint32_t __get_BASEPRI(void);\r
+\r
+/**\r
+ * @brief  Set the Base Priority value\r
+ *\r
+ * @param  basePri  BasePriority\r
+ *\r
+ * Set the base priority register\r
+ */\r
+extern void __set_BASEPRI(uint32_t basePri);\r
+\r
+/**\r
+ * @brief  Return the Priority Mask value\r
+ *\r
+ * @return PriMask\r
+ *\r
+ * Return state of the priority mask bit from the priority mask register\r
+ */\r
+extern uint32_t __get_PRIMASK(void);\r
+\r
+/**\r
+ * @brief  Set the Priority Mask value\r
+ *\r
+ * @param   priMask  PriMask\r
+ *\r
+ * Set the priority mask bit in the priority mask register\r
+ */\r
+extern void __set_PRIMASK(uint32_t priMask);\r
+\r
+/**\r
+ * @brief  Return the Fault Mask value\r
+ *\r
+ * @return FaultMask\r
+ *\r
+ * Return the content of the fault mask register\r
+ */\r
+extern uint32_t __get_FAULTMASK(void);\r
+\r
+/**\r
+ * @brief  Set the Fault Mask value\r
+ *\r
+ * @param  faultMask faultMask value\r
+ *\r
+ * Set the fault mask register\r
+ */\r
+extern void __set_FAULTMASK(uint32_t faultMask);\r
+\r
+/**\r
+ * @brief  Return the Control Register value\r
+ *\r
+ * @return Control value\r
+ *\r
+ * Return the content of the control register\r
+ */\r
+extern uint32_t __get_CONTROL(void);\r
+\r
+/**\r
+ * @brief  Set the Control Register value\r
+ *\r
+ * @param  control  Control value\r
+ *\r
+ * Set the control register\r
+ */\r
+extern void __set_CONTROL(uint32_t control);\r
+\r
+#else  /* (__ARMCC_VERSION >= 400000)  */\r
+\r
+/**\r
+ * @brief  Remove the exclusive lock created by ldrex\r
+ *\r
+ * Removes the exclusive lock which is created by ldrex.\r
+ */\r
+#define __CLREX                           __clrex\r
+\r
+/**\r
+ * @brief  Return the Base Priority value\r
+ *\r
+ * @return BasePriority\r
+ *\r
+ * Return the content of the base priority register\r
+ */\r
+static __INLINE uint32_t  __get_BASEPRI(void)\r
+{\r
+  register uint32_t __regBasePri         __ASM("basepri");\r
+  return(__regBasePri);\r
+}\r
+\r
+/**\r
+ * @brief  Set the Base Priority value\r
+ *\r
+ * @param  basePri  BasePriority\r
+ *\r
+ * Set the base priority register\r
+ */\r
+static __INLINE void __set_BASEPRI(uint32_t basePri)\r
+{\r
+  register uint32_t __regBasePri         __ASM("basepri");\r
+  __regBasePri = (basePri & 0xff);\r
+}\r
+\r
+/**\r
+ * @brief  Return the Priority Mask value\r
+ *\r
+ * @return PriMask\r
+ *\r
+ * Return state of the priority mask bit from the priority mask register\r
+ */\r
+static __INLINE uint32_t __get_PRIMASK(void)\r
+{\r
+  register uint32_t __regPriMask         __ASM("primask");\r
+  return(__regPriMask);\r
+}\r
+\r
+/**\r
+ * @brief  Set the Priority Mask value\r
+ *\r
+ * @param  priMask  PriMask\r
+ *\r
+ * Set the priority mask bit in the priority mask register\r
+ */\r
+static __INLINE void __set_PRIMASK(uint32_t priMask)\r
+{\r
+  register uint32_t __regPriMask         __ASM("primask");\r
+  __regPriMask = (priMask);\r
+}\r
+\r
+/**\r
+ * @brief  Return the Fault Mask value\r
+ *\r
+ * @return FaultMask\r
+ *\r
+ * Return the content of the fault mask register\r
+ */\r
+static __INLINE uint32_t __get_FAULTMASK(void)\r
+{\r
+  register uint32_t __regFaultMask       __ASM("faultmask");\r
+  return(__regFaultMask);\r
+}\r
+\r
+/**\r
+ * @brief  Set the Fault Mask value\r
+ *\r
+ * @param  faultMask  faultMask value\r
+ *\r
+ * Set the fault mask register\r
+ */\r
+static __INLINE void __set_FAULTMASK(uint32_t faultMask)\r
+{\r
+  register uint32_t __regFaultMask       __ASM("faultmask");\r
+  __regFaultMask = (faultMask & 1);\r
+}\r
+\r
+/**\r
+ * @brief  Return the Control Register value\r
+ *\r
+ * @return Control value\r
+ *\r
+ * Return the content of the control register\r
+ */\r
+static __INLINE uint32_t __get_CONTROL(void)\r
+{\r
+  register uint32_t __regControl         __ASM("control");\r
+  return(__regControl);\r
+}\r
+\r
+/**\r
+ * @brief  Set the Control Register value\r
+ *\r
+ * @param  control  Control value\r
+ *\r
+ * Set the control register\r
+ */\r
+static __INLINE void __set_CONTROL(uint32_t control)\r
+{\r
+  register uint32_t __regControl         __ASM("control");\r
+  __regControl = control;\r
+}\r
+\r
+#endif /* __ARMCC_VERSION  */\r
+\r
+\r
+\r
+#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/\r
+/* IAR iccarm specific functions */\r
+\r
+#define __enable_irq                              __enable_interrupt        /*!< global Interrupt enable */\r
+#define __disable_irq                             __disable_interrupt       /*!< global Interrupt disable */\r
+\r
+static __INLINE void __enable_fault_irq()         { __ASM ("cpsie f"); }\r
+static __INLINE void __disable_fault_irq()        { __ASM ("cpsid f"); }\r
+\r
+#define __NOP                                     __no_operation            /*!< no operation intrinsic in IAR Compiler */\r
+static __INLINE  void __WFI()                     { __ASM ("wfi"); }\r
+static __INLINE  void __WFE()                     { __ASM ("wfe"); }\r
+static __INLINE  void __SEV()                     { __ASM ("sev"); }\r
+static __INLINE  void __CLREX()                   { __ASM ("clrex"); }\r
+\r
+/* intrinsic void __ISB(void)                                     */\r
+/* intrinsic void __DSB(void)                                     */\r
+/* intrinsic void __DMB(void)                                     */\r
+/* intrinsic void __set_PRIMASK();                                */\r
+/* intrinsic void __get_PRIMASK();                                */\r
+/* intrinsic void __set_FAULTMASK();                              */\r
+/* intrinsic void __get_FAULTMASK();                              */\r
+/* intrinsic uint32_t __REV(uint32_t value);                      */\r
+/* intrinsic uint32_t __REVSH(uint32_t value);                    */\r
+/* intrinsic unsigned long __STREX(unsigned long, unsigned long); */\r
+/* intrinsic unsigned long __LDREX(unsigned long *);              */\r
+\r
+\r
+/**\r
+ * @brief  Return the Process Stack Pointer\r
+ *\r
+ * @return ProcessStackPointer\r
+ *\r
+ * Return the actual process stack pointer\r
+ */\r
+extern uint32_t __get_PSP(void);\r
+\r
+/**\r
+ * @brief  Set the Process Stack Pointer\r
+ *\r
+ * @param  topOfProcStack  Process Stack Pointer\r
+ *\r
+ * Assign the value ProcessStackPointer to the MSP\r
+ * (process stack pointer) Cortex processor register\r
+ */\r
+extern void __set_PSP(uint32_t topOfProcStack);\r
+\r
+/**\r
+ * @brief  Return the Main Stack Pointer\r
+ *\r
+ * @return Main Stack Pointer\r
+ *\r
+ * Return the current value of the MSP (main stack pointer)\r
+ * Cortex processor register\r
+ */\r
+extern uint32_t __get_MSP(void);\r
+\r
+/**\r
+ * @brief  Set the Main Stack Pointer\r
+ *\r
+ * @param  topOfMainStack  Main Stack Pointer\r
+ *\r
+ * Assign the value mainStackPointer to the MSP\r
+ * (main stack pointer) Cortex processor register\r
+ */\r
+extern void __set_MSP(uint32_t topOfMainStack);\r
+\r
+/**\r
+ * @brief  Reverse byte order in unsigned short value\r
+ *\r
+ * @param  value  value to reverse\r
+ * @return        reversed value\r
+ *\r
+ * Reverse byte order in unsigned short value\r
+ */\r
+extern uint32_t __REV16(uint16_t value);\r
+\r
+/**\r
+ * @brief  Reverse bit order of value\r
+ *\r
+ * @param  value  value to reverse\r
+ * @return        reversed value\r
+ *\r
+ * Reverse bit order of value\r
+ */\r
+extern uint32_t __RBIT(uint32_t value);\r
+\r
+/**\r
+ * @brief  LDR Exclusive (8 bit)\r
+ *\r
+ * @param  *addr  address pointer\r
+ * @return        value of (*address)\r
+ *\r
+ * Exclusive LDR command for 8 bit values)\r
+ */\r
+extern uint8_t __LDREXB(uint8_t *addr);\r
+\r
+/**\r
+ * @brief  LDR Exclusive (16 bit)\r
+ *\r
+ * @param  *addr  address pointer\r
+ * @return        value of (*address)\r
+ *\r
+ * Exclusive LDR command for 16 bit values\r
+ */\r
+extern uint16_t __LDREXH(uint16_t *addr);\r
+\r
+/**\r
+ * @brief  LDR Exclusive (32 bit)\r
+ *\r
+ * @param  *addr  address pointer\r
+ * @return        value of (*address)\r
+ *\r
+ * Exclusive LDR command for 32 bit values\r
+ */\r
+extern uint32_t __LDREXW(uint32_t *addr);\r
+\r
+/**\r
+ * @brief  STR Exclusive (8 bit)\r
+ *\r
+ * @param  value  value to store\r
+ * @param  *addr  address pointer\r
+ * @return        successful / failed\r
+ *\r
+ * Exclusive STR command for 8 bit values\r
+ */\r
+extern uint32_t __STREXB(uint8_t value, uint8_t *addr);\r
+\r
+/**\r
+ * @brief  STR Exclusive (16 bit)\r
+ *\r
+ * @param  value  value to store\r
+ * @param  *addr  address pointer\r
+ * @return        successful / failed\r
+ *\r
+ * Exclusive STR command for 16 bit values\r
+ */\r
+extern uint32_t __STREXH(uint16_t value, uint16_t *addr);\r
+\r
+/**\r
+ * @brief  STR Exclusive (32 bit)\r
+ *\r
+ * @param  value  value to store\r
+ * @param  *addr  address pointer\r
+ * @return        successful / failed\r
+ *\r
+ * Exclusive STR command for 32 bit values\r
+ */\r
+extern uint32_t __STREXW(uint32_t value, uint32_t *addr);\r
+\r
+\r
+\r
+#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/\r
+/* GNU gcc specific functions */\r
+\r
+static __INLINE void __enable_irq()               { __ASM volatile ("cpsie i"); }\r
+static __INLINE void __disable_irq()              { __ASM volatile ("cpsid i"); }\r
+\r
+static __INLINE void __enable_fault_irq()         { __ASM volatile ("cpsie f"); }\r
+static __INLINE void __disable_fault_irq()        { __ASM volatile ("cpsid f"); }\r
+\r
+static __INLINE void __NOP()                      { __ASM volatile ("nop"); }\r
+static __INLINE void __WFI()                      { __ASM volatile ("wfi"); }\r
+static __INLINE void __WFE()                      { __ASM volatile ("wfe"); }\r
+static __INLINE void __SEV()                      { __ASM volatile ("sev"); }\r
+static __INLINE void __ISB()                      { __ASM volatile ("isb"); }\r
+static __INLINE void __DSB()                      { __ASM volatile ("dsb"); }\r
+static __INLINE void __DMB()                      { __ASM volatile ("dmb"); }\r
+static __INLINE void __CLREX()                    { __ASM volatile ("clrex"); }\r
+\r
+\r
+/**\r
+ * @brief  Return the Process Stack Pointer\r
+ *\r
+ * @return ProcessStackPointer\r
+ *\r
+ * Return the actual process stack pointer\r
+ */\r
+extern uint32_t __get_PSP(void);\r
+\r
+/**\r
+ * @brief  Set the Process Stack Pointer\r
+ *\r
+ * @param  topOfProcStack  Process Stack Pointer\r
+ *\r
+ * Assign the value ProcessStackPointer to the MSP\r
+ * (process stack pointer) Cortex processor register\r
+ */\r
+extern void __set_PSP(uint32_t topOfProcStack);\r
+\r
+/**\r
+ * @brief  Return the Main Stack Pointer\r
+ *\r
+ * @return Main Stack Pointer\r
+ *\r
+ * Return the current value of the MSP (main stack pointer)\r
+ * Cortex processor register\r
+ */\r
+extern uint32_t __get_MSP(void);\r
+\r
+/**\r
+ * @brief  Set the Main Stack Pointer\r
+ *\r
+ * @param  topOfMainStack  Main Stack Pointer\r
+ *\r
+ * Assign the value mainStackPointer to the MSP\r
+ * (main stack pointer) Cortex processor register\r
+ */\r
+extern void __set_MSP(uint32_t topOfMainStack);\r
+\r
+/**\r
+ * @brief  Return the Base Priority value\r
+ *\r
+ * @return BasePriority\r
+ *\r
+ * Return the content of the base priority register\r
+ */\r
+extern uint32_t __get_BASEPRI(void);\r
+\r
+/**\r
+ * @brief  Set the Base Priority value\r
+ *\r
+ * @param  basePri  BasePriority\r
+ *\r
+ * Set the base priority register\r
+ */\r
+extern void __set_BASEPRI(uint32_t basePri);\r
+\r
+/**\r
+ * @brief  Return the Priority Mask value\r
+ *\r
+ * @return PriMask\r
+ *\r
+ * Return state of the priority mask bit from the priority mask register\r
+ */\r
+extern uint32_t  __get_PRIMASK(void);\r
+\r
+/**\r
+ * @brief  Set the Priority Mask value\r
+ *\r
+ * @param  priMask  PriMask\r
+ *\r
+ * Set the priority mask bit in the priority mask register\r
+ */\r
+extern void __set_PRIMASK(uint32_t priMask);\r
+\r
+/**\r
+ * @brief  Return the Fault Mask value\r
+ *\r
+ * @return FaultMask\r
+ *\r
+ * Return the content of the fault mask register\r
+ */\r
+extern uint32_t __get_FAULTMASK(void);\r
+\r
+/**\r
+ * @brief  Set the Fault Mask value\r
+ *\r
+ * @param  faultMask  faultMask value\r
+ *\r
+ * Set the fault mask register\r
+ */\r
+extern void __set_FAULTMASK(uint32_t faultMask);\r
+\r
+/**\r
+ * @brief  Return the Control Register value\r
+*\r
+*  @return Control value\r
+ *\r
+ * Return the content of the control register\r
+ */\r
+extern uint32_t __get_CONTROL(void);\r
+\r
+/**\r
+ * @brief  Set the Control Register value\r
+ *\r
+ * @param  control  Control value\r
+ *\r
+ * Set the control register\r
+ */\r
+extern void __set_CONTROL(uint32_t control);\r
+\r
+/**\r
+ * @brief  Reverse byte order in integer value\r
+ *\r
+ * @param  value  value to reverse\r
+ * @return        reversed value\r
+ *\r
+ * Reverse byte order in integer value\r
+ */\r
+extern uint32_t __REV(uint32_t value);\r
+\r
+/**\r
+ * @brief  Reverse byte order in unsigned short value\r
+ *\r
+ * @param  value  value to reverse\r
+ * @return        reversed value\r
+ *\r
+ * Reverse byte order in unsigned short value\r
+ */\r
+extern uint32_t __REV16(uint16_t value);\r
+\r
+/**\r
+ * @brief  Reverse byte order in signed short value with sign extension to integer\r
+ *\r
+ * @param  value  value to reverse\r
+ * @return        reversed value\r
+ *\r
+ * Reverse byte order in signed short value with sign extension to integer\r
+ */\r
+extern int32_t __REVSH(int16_t value);\r
+\r
+/**\r
+ * @brief  Reverse bit order of value\r
+ *\r
+ * @param  value  value to reverse\r
+ * @return        reversed value\r
+ *\r
+ * Reverse bit order of value\r
+ */\r
+extern uint32_t __RBIT(uint32_t value);\r
+\r
+/**\r
+ * @brief  LDR Exclusive (8 bit)\r
+ *\r
+ * @param  *addr  address pointer\r
+ * @return        value of (*address)\r
+ *\r
+ * Exclusive LDR command for 8 bit value\r
+ */\r
+extern uint8_t __LDREXB(uint8_t *addr);\r
+\r
+/**\r
+ * @brief  LDR Exclusive (16 bit)\r
+ *\r
+ * @param  *addr  address pointer\r
+ * @return        value of (*address)\r
+ *\r
+ * Exclusive LDR command for 16 bit values\r
+ */\r
+extern uint16_t __LDREXH(uint16_t *addr);\r
+\r
+/**\r
+ * @brief  LDR Exclusive (32 bit)\r
+ *\r
+ * @param  *addr  address pointer\r
+ * @return        value of (*address)\r
+ *\r
+ * Exclusive LDR command for 32 bit values\r
+ */\r
+extern uint32_t __LDREXW(uint32_t *addr);\r
+\r
+/**\r
+ * @brief  STR Exclusive (8 bit)\r
+ *\r
+ * @param  value  value to store\r
+ * @param  *addr  address pointer\r
+ * @return        successful / failed\r
+ *\r
+ * Exclusive STR command for 8 bit values\r
+ */\r
+extern uint32_t __STREXB(uint8_t value, uint8_t *addr);\r
+\r
+/**\r
+ * @brief  STR Exclusive (16 bit)\r
+ *\r
+ * @param  value  value to store\r
+ * @param  *addr  address pointer\r
+ * @return        successful / failed\r
+ *\r
+ * Exclusive STR command for 16 bit values\r
+ */\r
+extern uint32_t __STREXH(uint16_t value, uint16_t *addr);\r
+\r
+/**\r
+ * @brief  STR Exclusive (32 bit)\r
+ *\r
+ * @param  value  value to store\r
+ * @param  *addr  address pointer\r
+ * @return        successful / failed\r
+ *\r
+ * Exclusive STR command for 32 bit values\r
+ */\r
+extern uint32_t __STREXW(uint32_t value, uint32_t *addr);\r
+\r
+\r
+#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/\r
+/* TASKING carm specific functions */\r
+\r
+/*\r
+ * The CMSIS functions have been implemented as intrinsics in the compiler.\r
+ * Please use "carm -?i" to get an up to date list of all instrinsics,\r
+ * Including the CMSIS ones.\r
+ */\r
+\r
+#endif\r
+\r
+\r
+/** @addtogroup CMSIS_CM3_Core_FunctionInterface CMSIS CM3 Core Function Interface\r
+  Core  Function Interface containing:\r
+  - Core NVIC Functions\r
+  - Core SysTick Functions\r
+  - Core Reset Functions\r
+*/\r
+/*@{*/\r
+\r
+/* ##########################   NVIC functions  #################################### */\r
+\r
+/**\r
+ * @brief  Set the Priority Grouping in NVIC Interrupt Controller\r
+ *\r
+ * @param  PriorityGroup is priority grouping field\r
+ *\r
+ * Set the priority grouping field using the required unlock sequence.\r
+ * The parameter priority_grouping is assigned to the field\r
+ * SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used.\r
+ * In case of a conflict between priority grouping and available\r
+ * priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\r
+ */\r
+static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)\r
+{\r
+  uint32_t reg_value;\r
+  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);                         /* only values 0..7 are used          */\r
+\r
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */\r
+  reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk);             /* clear bits to change               */\r
+  reg_value  =  (reg_value                       |\r
+                (0x5FA << SCB_AIRCR_VECTKEY_Pos) |\r
+                (PriorityGroupTmp << 8));                                     /* Insert write key and priorty group */\r
+  SCB->AIRCR =  reg_value;\r
+}\r
+\r
+/**\r
+ * @brief  Get the Priority Grouping from NVIC Interrupt Controller\r
+ *\r
+ * @return priority grouping field\r
+ *\r
+ * Get the priority grouping from NVIC Interrupt Controller.\r
+ * priority grouping is SCB->AIRCR [10:8] PRIGROUP field.\r
+ */\r
+static __INLINE uint32_t NVIC_GetPriorityGrouping(void)\r
+{\r
+  return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos);   /* read priority grouping field */\r
+}\r
+\r
+/**\r
+ * @brief  Enable Interrupt in NVIC Interrupt Controller\r
+ *\r
+ * @param  IRQn   The positive number of the external interrupt to enable\r
+ *\r
+ * Enable a device specific interupt in the NVIC interrupt controller.\r
+ * The interrupt number cannot be a negative value.\r
+ */\r
+static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)\r
+{\r
+  NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */\r
+}\r
+\r
+/**\r
+ * @brief  Disable the interrupt line for external interrupt specified\r
+ *\r
+ * @param  IRQn   The positive number of the external interrupt to disable\r
+ *\r
+ * Disable a device specific interupt in the NVIC interrupt controller.\r
+ * The interrupt number cannot be a negative value.\r
+ */\r
+static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)\r
+{\r
+  NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */\r
+}\r
+\r
+/**\r
+ * @brief  Read the interrupt pending bit for a device specific interrupt source\r
+ *\r
+ * @param  IRQn    The number of the device specifc interrupt\r
+ * @return         1 = interrupt pending, 0 = interrupt not pending\r
+ *\r
+ * Read the pending register in NVIC and return 1 if its status is pending,\r
+ * otherwise it returns 0\r
+ */\r
+static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+  return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */\r
+}\r
+\r
+/**\r
+ * @brief  Set the pending bit for an external interrupt\r
+ *\r
+ * @param  IRQn    The number of the interrupt for set pending\r
+ *\r
+ * Set the pending bit for the specified interrupt.\r
+ * The interrupt number cannot be a negative value.\r
+ */\r
+static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+  NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */\r
+}\r
+\r
+/**\r
+ * @brief  Clear the pending bit for an external interrupt\r
+ *\r
+ * @param  IRQn    The number of the interrupt for clear pending\r
+ *\r
+ * Clear the pending bit for the specified interrupt.\r
+ * The interrupt number cannot be a negative value.\r
+ */\r
+static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
+{\r
+  NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */\r
+}\r
+\r
+/**\r
+ * @brief  Read the active bit for an external interrupt\r
+ *\r
+ * @param  IRQn    The number of the interrupt for read active bit\r
+ * @return         1 = interrupt active, 0 = interrupt not active\r
+ *\r
+ * Read the active register in NVIC and returns 1 if its status is active,\r
+ * otherwise it returns 0.\r
+ */\r
+static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)\r
+{\r
+  return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */\r
+}\r
+\r
+/**\r
+ * @brief  Set the priority for an interrupt\r
+ *\r
+ * @param  IRQn      The number of the interrupt for set priority\r
+ * @param  priority  The priority to set\r
+ *\r
+ * Set the priority for the specified interrupt. The interrupt\r
+ * number can be positive to specify an external (device specific)\r
+ * interrupt, or negative to specify an internal (core) interrupt.\r
+ *\r
+ * Note: The priority cannot be set for every core interrupt.\r
+ */\r
+static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r
+{\r
+  if(IRQn < 0) {\r
+    SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M3 System Interrupts */\r
+  else {\r
+    NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff);    }        /* set Priority for device specific Interrupts  */\r
+}\r
+\r
+/**\r
+ * @brief  Read the priority for an interrupt\r
+ *\r
+ * @param  IRQn      The number of the interrupt for get priority\r
+ * @return           The priority for the interrupt\r
+ *\r
+ * Read the priority for the specified interrupt. The interrupt\r
+ * number can be positive to specify an external (device specific)\r
+ * interrupt, or negative to specify an internal (core) interrupt.\r
+ *\r
+ * The returned priority value is automatically aligned to the implemented\r
+ * priority bits of the microcontroller.\r
+ *\r
+ * Note: The priority cannot be set for every core interrupt.\r
+ */\r
+static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)\r
+{\r
+\r
+  if(IRQn < 0) {\r
+    return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M3 system interrupts */\r
+  else {\r
+    return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)]           >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */\r
+}\r
+\r
+\r
+/**\r
+ * @brief  Encode the priority for an interrupt\r
+ *\r
+ * @param  PriorityGroup    The used priority group\r
+ * @param  PreemptPriority  The preemptive priority value (starting from 0)\r
+ * @param  SubPriority      The sub priority value (starting from 0)\r
+ * @return                  The encoded priority for the interrupt\r
+ *\r
+ * Encode the priority for an interrupt with the given priority group,\r
+ * preemptive priority value and sub priority value.\r
+ * In case of a conflict between priority grouping and available\r
+ * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.\r
+ *\r
+ * The returned priority value can be used for NVIC_SetPriority(...) function\r
+ */\r
+static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\r
+{\r
+  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */\r
+  uint32_t PreemptPriorityBits;\r
+  uint32_t SubPriorityBits;\r
+\r
+  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;\r
+  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;\r
+\r
+  return (\r
+           ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |\r
+           ((SubPriority     & ((1 << (SubPriorityBits    )) - 1)))\r
+         );\r
+}\r
+\r
+\r
+/**\r
+ * @brief  Decode the priority of an interrupt\r
+ *\r
+ * @param  Priority           The priority for the interrupt\r
+ * @param  PriorityGroup      The used priority group\r
+ * @param  pPreemptPriority   The preemptive priority value (starting from 0)\r
+ * @param  pSubPriority       The sub priority value (starting from 0)\r
+ *\r
+ * Decode an interrupt priority value with the given priority group to\r
+ * preemptive priority value and sub priority value.\r
+ * In case of a conflict between priority grouping and available\r
+ * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.\r
+ *\r
+ * The priority value can be retrieved with NVIC_GetPriority(...) function\r
+ */\r
+static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)\r
+{\r
+  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */\r
+  uint32_t PreemptPriorityBits;\r
+  uint32_t SubPriorityBits;\r
+\r
+  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;\r
+  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;\r
+\r
+  *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);\r
+  *pSubPriority     = (Priority                   ) & ((1 << (SubPriorityBits    )) - 1);\r
+}\r
+\r
+\r
+\r
+/* ##################################    SysTick function  ############################################ */\r
+\r
+#if (!defined (__Vendor_SysTickConfig)) || (__Vendor_SysTickConfig == 0)\r
+\r
+/**\r
+ * @brief  Initialize and start the SysTick counter and its interrupt.\r
+ *\r
+ * @param   ticks   number of ticks between two interrupts\r
+ * @return  1 = failed, 0 = successful\r
+ *\r
+ * Initialise the system tick timer and its interrupt and start the\r
+ * system tick timer / counter in free running mode to generate\r
+ * periodical interrupts.\r
+ */\r
+static __INLINE uint32_t SysTick_Config(uint32_t ticks)\r
+{\r
+  if (ticks > SysTick_LOAD_RELOAD_Msk)  return (1);            /* Reload value impossible */\r
+\r
+  SysTick->LOAD  = (ticks & SysTick_LOAD_RELOAD_Msk) - 1;      /* set reload register */\r
+  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Cortex-M0 System Interrupts */\r
+  SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */\r
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\r
+                   SysTick_CTRL_TICKINT_Msk   |\r
+                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */\r
+  return (0);                                                  /* Function successful */\r
+}\r
+\r
+#endif\r
+\r
+\r
+\r
+\r
+/* ##################################    Reset function  ############################################ */\r
+\r
+/**\r
+ * @brief  Initiate a system reset request.\r
+ *\r
+ * Initiate a system reset request to reset the MCU\r
+ */\r
+static __INLINE void NVIC_SystemReset(void)\r
+{\r
+  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |\r
+                 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |\r
+                 SCB_AIRCR_SYSRESETREQ_Msk);                   /* Keep priority group unchanged */\r
+  __DSB();                                                     /* Ensure completion of memory access */\r
+  while(1);                                                    /* wait until reset */\r
+}\r
+\r
+/*@}*/ /* end of group CMSIS_CM3_Core_FunctionInterface */\r
+\r
+\r
+\r
+/* ##################################### Debug In/Output function ########################################### */\r
+\r
+/** @addtogroup CMSIS_CM3_CoreDebugInterface CMSIS CM3 Core Debug Interface\r
+  Core Debug Interface containing:\r
+  - Core Debug Receive / Transmit Functions\r
+  - Core Debug Defines\r
+  - Core Debug Variables\r
+*/\r
+/*@{*/\r
+\r
+extern volatile int ITM_RxBuffer;                    /*!< variable to receive characters                             */\r
+#define             ITM_RXBUFFER_EMPTY    0x5AA55AA5 /*!< value identifying ITM_RxBuffer is ready for next character */\r
+\r
+\r
+/**\r
+ * @brief  Outputs a character via the ITM channel 0\r
+ *\r
+ * @param  ch   character to output\r
+ * @return      character to output\r
+ *\r
+ * The function outputs a character via the ITM channel 0.\r
+ * The function returns when no debugger is connected that has booked the output.\r
+ * It is blocking when a debugger is connected, but the previous character send is not transmitted.\r
+ */\r
+static __INLINE uint32_t ITM_SendChar (uint32_t ch)\r
+{\r
+  if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk)  &&      /* Trace enabled */\r
+      (ITM->TCR & ITM_TCR_ITMENA_Msk)                  &&      /* ITM enabled */\r
+      (ITM->TER & (1ul << 0)        )                    )     /* ITM Port #0 enabled */\r
+  {\r
+    while (ITM->PORT[0].u32 == 0);\r
+    ITM->PORT[0].u8 = (uint8_t) ch;\r
+  }\r
+  return (ch);\r
+}\r
+\r
+\r
+/**\r
+ * @brief  Inputs a character via variable ITM_RxBuffer\r
+ *\r
+ * @return      received character, -1 = no character received\r
+ *\r
+ * The function inputs a character via variable ITM_RxBuffer.\r
+ * The function returns when no debugger is connected that has booked the output.\r
+ * It is blocking when a debugger is connected, but the previous character send is not transmitted.\r
+ */\r
+static __INLINE int ITM_ReceiveChar (void) {\r
+  int ch = -1;                               /* no character available */\r
+\r
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {\r
+    ch = ITM_RxBuffer;\r
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */\r
+  }\r
+\r
+  return (ch);\r
+}\r
+\r
+\r
+/**\r
+ * @brief  Check if a character via variable ITM_RxBuffer is available\r
+ *\r
+ * @return      1 = character available, 0 = no character available\r
+ *\r
+ * The function checks  variable ITM_RxBuffer whether a character is available or not.\r
+ * The function returns '1' if a character is available and '0' if no character is available.\r
+ */\r
+static __INLINE int ITM_CheckChar (void) {\r
+\r
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {\r
+    return (0);                                 /* no character available */\r
+  } else {\r
+    return (1);                                 /*    character available */\r
+  }\r
+}\r
+\r
+/*@}*/ /* end of group CMSIS_CM3_core_DebugInterface */\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+/*@}*/ /* end of group CMSIS_CM3_core_definitions */\r
+\r
+#endif /* __CM3_CORE_H__ */\r
+\r
+/*lint -restore */\r

diff --git a/Demo/CORTEX_STM32L152_IAR/system_and_ST_code/CMSIS/CM3/DeviceSupport/ST/Release_Notes_for_STM32L1xx_CMSIS.html b/Demo/CORTEX_STM32L152_IAR/system_and_ST_code/CMSIS/CM3/DeviceSupport/ST/Release_Notes_for_STM32L1xx_CMSIS.html
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+{page:Section1;}\r
+-->\r
+  </style><!--[if gte mso 10]> <style> /* Style Definitions */ table.MsoNormalTable {mso-style-name:"Table Normal"; mso-tstyle-rowband-size:0; mso-tstyle-colband-size:0; mso-style-noshow:yes; mso-style-parent:""; mso-padding-alt:0in 5.4pt 0in 5.4pt; mso-para-margin:0in; mso-para-margin-bottom:.0001pt; mso-pagination:widow-orphan; font-size:10.0pt; font-family:"Times New Roman"; mso-ansi-language:#0400; mso-fareast-language:#0400; mso-bidi-language:#0400;} </style> <![endif]--><!--[if gte mso 9]><xml> <o:shapedefaults v:ext="edit" spidmax="5122"/> </xml><![endif]--><!--[if gte mso 9]><xml> <o:shapelayout v:ext="edit"> <o:idmap v:ext="edit" data="1"/> </o:shapelayout></xml><![endif]--></head><body style="" lang="EN-US" link="blue" vlink="blue">\r
+<div class="Section1">\r
+<p class="MsoNormal"><span style="font-family: Arial;"><o:p><br>\r
+</o:p></span></p>\r
+<div align="center">\r
+<table class="MsoNormalTable" style="width: 675pt;" border="0" cellpadding="0" cellspacing="0" width="900">\r
+  <tbody>\r
+    <tr style="">\r
+      <td style="padding: 0cm;" valign="top">\r
+      <table class="MsoNormalTable" style="width: 675pt;" border="0" cellpadding="0" cellspacing="0" width="900">\r
+        <tbody>\r
+          <tr>\r
+            <td style="vertical-align: top;"><span style="font-size: 8pt; font-family: Arial; color: blue;"><a href="../../../../../Release_Notes.html">Back to Release page</a></span></td>\r
+          </tr>\r
+          <tr style="">\r
+            <td style="padding: 1.5pt;">\r
+            <h1 style="margin-bottom: 18pt; text-align: center;" align="center"><span style="font-size: 20pt; font-family: Verdana; color: rgb(51, 102, 255);">Release\r
+Notes for STM32L1xx CMSIS</span><span style="font-size: 20pt; font-family: Verdana;"><o:p></o:p></span></h1>\r
+            <p class="MsoNormal" style="text-align: center;" align="center"><span style="font-size: 10pt; font-family: Arial; color: black;">Copyright\r
+2010 STMicroelectronics</span><span style="color: black;"><u1:p></u1:p><o:p></o:p></span></p>\r
+            <p class="MsoNormal" style="text-align: center;" align="center"><span style="font-size: 10pt; font-family: Arial; color: black;"><img alt="" id="_x0000_i1025" src="../../../../../_htmresc/logo.bmp" style="border: 0px solid ; width: 86px; height: 65px;"></span><span style="font-size: 10pt;"><o:p></o:p></span></p>\r
+            </td>\r
+          </tr>\r
+        </tbody>\r
+      </table>\r
+      <p class="MsoNormal"><span style="font-family: Arial; display: none;"><o:p>&nbsp;</o:p></span></p>\r
+      <table class="MsoNormalTable" style="width: 675pt;" border="0" cellpadding="0" width="900">\r
+        <tbody>\r
+          <tr>\r
+            <td style="padding: 0cm;" valign="top">\r
+            <h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial;"><span style="font-size: 12pt; color: white;">Contents<o:p></o:p></span></h2>\r
+            <ol style="margin-top: 0cm;" start="1" type="1">\r
+              <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><a href="#History">STM32L1xx\r
+CMSIS\r
+update History</a><o:p></o:p></span></li>\r
+              <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><a href="#License">License</a><o:p></o:p></span></li>\r
+            </ol>\r
+            <span style="font-family: &quot;Times New Roman&quot;;"></span>\r
+            <h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial;"><a name="History"></a><span style="font-size: 12pt; color: white;">STM32L1xx\r
+CMSIS\r
+update History</span></h2>\r
+            <h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; margin-right: 558.05pt;"><span style="font-size: 10pt; font-family: Arial; color: white;">1.0.0RC1\r
+- 07/02/2010</span></h3><ol style="margin-top: 0in;" start="1" type="1">\r
+              <li class="MsoNormal" style=""><b><i><span style="font-size: 10pt; font-family: Verdana;">General</span></i></b><i><span style="font-size: 10pt; font-family: Verdana;"></span></i><i><span style="font-size: 10pt;"><o:p></o:p></span></i></li>\r
+            </ol>\r
+            <ul style="margin-top: 0in;" type="disc">\r
+              <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">STM32L1xx CMSIS files\r
+updated to <span style="font-weight: bold;">CMSIS V1.30</span> release</span></li>\r
+              <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Directory structure\r
+updated to be aligned with CMSIS V1.30<br>\r
+                </span></li>\r
+              <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add support\r
+for&nbsp;<b>STM32L Ultra Low-power\r
+Medium-density&nbsp; (STM32L15xx8/B) devices</b>.&nbsp;</span><span style="font-size: 10pt;"><o:p></o:p></span></li>\r
+            </ul>\r
+            <ol style="margin-top: 0in;" start="2" type="1">\r
+              <li class="MsoNormal" style=""><b><i><span style="font-size: 10pt; font-family: Verdana;">CMSIS Core Peripheral\r
+Access Layer</span></i></b></li>\r
+            </ol>\r
+            <ul>\r
+              <li><b><i><span style="font-size: 10pt; font-family: Verdana;"></span></i></b><span style="font-size: 10pt; font-family: Verdana;"> Refer to <a href="../../../CMSIS_changes.htm" target="_blank">CMSIS changes</a></span></li>\r
+            </ul>\r
+            <ol style="margin-top: 0in; list-style-type: decimal;" start="3">\r
+              <li class="MsoNormal" style=""><b><i><span style="font-size: 10pt; font-family: Verdana;">STM32L1xx CMSIS Device\r
+Peripheral Access Layer </span></i></b><b><i><span style="font-size: 10pt;"><o:p></o:p></span></i></b></li>\r
+            </ol>\r
+            <ul style="margin-top: 0in;" type="disc">\r
+              <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="text-decoration: underline;">STM32L1xx CMSIS Cortex-M3 Device\r
+Peripheral Access Layer Header File:</span> <span style="font-weight: bold; font-style: italic;">stm32l1xx.h</span></span><br>\r
+              </li>\r
+              <ul>\r
+                <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">All library files renamed with stm32l15x to stm32l1xx.</span></li>\r
+                <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">STM32L15X_LP product name renamed to STM32L1XX_MD.<br>\r
+                  </span></li>\r
+                <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">HSE_VALUE value changed to 8MHz.</span></li>\r
+                <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add new register in SYSCFG: PMC register</span></li>\r
+                <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">RTC TCR register renamed to TAFCR</span></li>\r
+                <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">GPIOF&nbsp; renamed to GPIOH</span></li>\r
+                <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add and update of all peripherals bits definitions<br>\r
+</span></li>\r
+\r
+              </ul>\r
+              <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="text-decoration: underline;">STM32L1xx CMSIS Cortex-M3 Device\r
+Peripheral Access Layer System Files:</span> <span style="font-weight: bold; font-style: italic;">system_stm32l1xx.h and\r
+system_stm32l1xx.c</span></span><br>\r
+                <span style="font-size: 10pt; font-family: Verdana;"></span></li>\r
+              <ul>\r
+                <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">SystemFrequency\r
+variable name changed to SystemCoreClock</span><br>\r
+                  <span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;"></span></span></li>\r
+                <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">Default </span></span><span style="font-size: 10pt; font-family: Verdana;">SystemCoreClock</span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;"> is changed to 32MHz (change the default frequency from SYSCLK_FREQ_HSE to SYSCLK_FREQ_32MHz).</span></span><span style="font-size: 10pt; font-family: Verdana;"><br>\r
+                  </span></li>\r
+                <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">All while(1) loop were\r
+removed from all clock setting functions. User has to handle the HSE\r
+startup failure.<br>\r
+                  </span></li>\r
+                <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Additional function <span style="font-weight: bold; font-style: italic;">void\r
+SystemCoreClockUpdate (void)</span> is provided.<br>\r
+                  </span></li>\r
+              </ul>\r
+              <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="text-decoration: underline;">STM32F10x CMSIS Startup files:</span>\r
+                <span style="font-weight: bold; font-style: italic;">startup_stm32l1xx_md.s</span></span></li>\r
+              <ul>\r
+                <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Startup file name changed from <span style="font-weight: bold;">startup_stm32l15x_lp</span>.s to <span style="font-weight: bold;">startup_stm32l1xx_md.s</span><span style="font-weight: bold; font-style: italic;">.</span></span></li>\r
+                \r
+                <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">SystemInit() function\r
+is called from startup file (startup_stm32l1xx_md.s) before to branch\r
+to application main.<br>\r
+To reconfigure the default setting of SystemInit() function, refer to\r
+system_stm32l1xx.c file <br>\r
+                  </span></li>\r
+                \r
+              </ul>\r
+            </ul>\r
+            <ul style="margin-top: 0in;" type="disc">\r
+            </ul>\r
+            <h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial;"><a name="License"></a><span style="font-size: 12pt; color: white;">License<o:p></o:p></span></h2>\r
+            <p class="MsoNormal" style="margin: 4.5pt 0cm;"><span style="font-size: 10pt; font-family: Verdana; color: black;">The\r
+enclosed firmware and all the related documentation are not covered by\r
+a License Agreement, if you need such License you can contact your\r
+local STMicroelectronics office.<u1:p></u1:p><o:p></o:p></span></p>\r
+            <p class="MsoNormal"><b style=""><span style="font-size: 10pt; font-family: Verdana; color: black;">THE\r
+PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO\r
+SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR\r
+ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY\r
+CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY\r
+CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH\r
+THEIR PRODUCTS. <o:p></o:p></span></b></p>\r
+            <p class="MsoNormal"><span style="color: black;"><o:p>&nbsp;</o:p></span></p>\r
+            <div class="MsoNormal" style="text-align: center;" align="center"><span style="color: black;">\r
+            <hr align="center" size="2" width="100%"></span></div>\r
+            <p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt; text-align: center;" align="center"><span style="font-size: 10pt; font-family: Verdana; color: black;">For\r
+complete documentation on </span><span style="font-size: 10pt; font-family: Verdana;">STM32L (<span style="color: black;">CORTEX M3) 32-Bit Microcontrollers\r
+visit </span><u><span style="color: blue;"><a href="http://www.st.com/stm32l" target="_blank">www.st.com/STM32L</a></span></u></span><span style="color: black;"><o:p></o:p></span></p>\r
+            </td>\r
+          </tr>\r
+        </tbody>\r
+      </table>\r
+      <p class="MsoNormal"><span style="font-size: 10pt;"><o:p></o:p></span></p>\r
+      </td>\r
+    </tr>\r
+  </tbody>\r
+</table>\r
+</div>\r
+<p class="MsoNormal"><o:p>&nbsp;</o:p></p>\r
+</div>\r
+\r
+</body></html>
\ No newline at end of file

diff --git a/Demo/CORTEX_STM32L152_IAR/system_and_ST_code/CMSIS/CM3/DeviceSupport/ST/STM32L1xx/startup/arm/startup_stm32l1xx_md.s b/Demo/CORTEX_STM32L152_IAR/system_and_ST_code/CMSIS/CM3/DeviceSupport/ST/STM32L1xx/startup/arm/startup_stm32l1xx_md.s
new file mode 100644 (file)
index 0000000..3917b31
--- /dev/null
+++ b/Demo/CORTEX_STM32L152_IAR/system_and_ST_code/CMSIS/CM3/DeviceSupport/ST/STM32L1xx/startup/arm/startup_stm32l1xx_md.s
@@ -0,0 +1,312 @@
+;******************** (C) COPYRIGHT 2010 STMicroelectronics ********************\r
+;* File Name          : startup_stm32l15x_lp.s\r
+;* Author             : MCD Application Team\r
+;* Version            : V1.0.0RC1\r
+;* Date               : 07/02/2010\r
+;* Description        : STM32L15x Low Power Devices vector table for RVMDK \r
+;*                      toolchain.\r
+;*                      This module performs:\r
+;*                      - Set the initial SP\r
+;*                      - Set the initial PC == Reset_Handler\r
+;*                      - Set the vector table entries with the exceptions ISR address\r
+;*                      - Branches to __main in the C library (which eventually\r
+;*                        calls main()).\r
+;*                      After Reset the CortexM3 processor is in Thread mode,\r
+;*                      priority is Privileged, and the Stack is set to Main.\r
+;* <<< Use Configuration Wizard in Context Menu >>>   \r
+;*******************************************************************************\r
+; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
+; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,\r
+; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE\r
+; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING\r
+; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+;*******************************************************************************\r
+\r
+; Amount of memory (in bytes) allocated for Stack\r
+; Tailor this value to your application needs\r
+; <h> Stack Configuration\r
+;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\r
+; </h>\r
+\r
+Stack_Size      EQU     0x00000400\r
+\r
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3\r
+Stack_Mem       SPACE   Stack_Size\r
+__initial_sp\r
+\r
+\r
+; <h> Heap Configuration\r
+;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\r
+; </h>\r
+\r
+Heap_Size       EQU     0x00000200\r
+\r
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3\r
+__heap_base\r
+Heap_Mem        SPACE   Heap_Size\r
+__heap_limit\r
+\r
+                PRESERVE8\r
+                THUMB\r
+\r
+\r
+; Vector Table Mapped to Address 0 at Reset\r
+                AREA    RESET, DATA, READONLY\r
+                EXPORT  __Vectors\r
+                EXPORT  __Vectors_End\r
+                EXPORT  __Vectors_Size\r
+\r
+__Vectors       DCD     __initial_sp              ; Top of Stack\r
+                DCD     Reset_Handler             ; Reset Handler\r
+                DCD     NMI_Handler               ; NMI Handler\r
+                DCD     HardFault_Handler         ; Hard Fault Handler\r
+                DCD     MemManage_Handler         ; MPU Fault Handler\r
+                DCD     BusFault_Handler          ; Bus Fault Handler\r
+                DCD     UsageFault_Handler        ; Usage Fault Handler\r
+                DCD     0                         ; Reserved\r
+                DCD     0                         ; Reserved\r
+                DCD     0                         ; Reserved\r
+                DCD     0                         ; Reserved\r
+                DCD     SVC_Handler               ; SVCall Handler\r
+                DCD     DebugMon_Handler          ; Debug Monitor Handler\r
+                DCD     0                         ; Reserved\r
+                DCD     PendSV_Handler            ; PendSV Handler\r
+                DCD     SysTick_Handler           ; SysTick Handler\r
+\r
+                ; External Interrupts\r
+                DCD     WWDG_IRQHandler           ; Window Watchdog\r
+                DCD     PVD_IRQHandler            ; PVD through EXTI Line detect\r
+                DCD     TAMPER_STAMP_IRQHandler   ; Tamper and Time Stamp\r
+                DCD     RTC_WKUP_IRQHandler       ; RTC Wakeup\r
+                DCD     FLASH_IRQHandler          ; FLASH\r
+                DCD     RCC_IRQHandler            ; RCC\r
+                DCD     EXTI0_IRQHandler          ; EXTI Line 0\r
+                DCD     EXTI1_IRQHandler          ; EXTI Line 1\r
+                DCD     EXTI2_IRQHandler          ; EXTI Line 2\r
+                DCD     EXTI3_IRQHandler          ; EXTI Line 3\r
+                DCD     EXTI4_IRQHandler          ; EXTI Line 4\r
+                DCD     DMA1_Channel1_IRQHandler  ; DMA1 Channel 1\r
+                DCD     DMA1_Channel2_IRQHandler  ; DMA1 Channel 2\r
+                DCD     DMA1_Channel3_IRQHandler  ; DMA1 Channel 3\r
+                DCD     DMA1_Channel4_IRQHandler  ; DMA1 Channel 4\r
+                DCD     DMA1_Channel5_IRQHandler  ; DMA1 Channel 5\r
+                DCD     DMA1_Channel6_IRQHandler  ; DMA1 Channel 6\r
+                DCD     DMA1_Channel7_IRQHandler  ; DMA1 Channel 7\r
+                DCD     ADC1_IRQHandler           ; ADC1\r
+                DCD     USB_HP_IRQHandler         ; USB High Priority\r
+                DCD     USB_LP_IRQHandler         ; USB Low  Priority\r
+                DCD     DAC_IRQHandler            ; DAC\r
+                DCD     COMP_IRQHandler           ; COMP through EXTI Line\r
+                DCD     EXTI9_5_IRQHandler        ; EXTI Line 9..5\r
+                DCD     LCD_IRQHandler            ; LCD\r
+                DCD     TIM9_IRQHandler           ; TIM9\r
+                DCD     TIM10_IRQHandler          ; TIM10\r
+                DCD     TIM11_IRQHandler          ; TIM11\r
+                DCD     TIM2_IRQHandler           ; TIM2\r
+                DCD     TIM3_IRQHandler           ; TIM3\r
+                DCD     TIM4_IRQHandler           ; TIM4\r
+                DCD     I2C1_EV_IRQHandler        ; I2C1 Event\r
+                DCD     I2C1_ER_IRQHandler        ; I2C1 Error\r
+                DCD     I2C2_EV_IRQHandler        ; I2C2 Event\r
+                DCD     I2C2_ER_IRQHandler        ; I2C2 Error\r
+                DCD     SPI1_IRQHandler           ; SPI1\r
+                DCD     SPI2_IRQHandler           ; SPI2\r
+                DCD     USART1_IRQHandler         ; USART1\r
+                DCD     USART2_IRQHandler         ; USART2\r
+                DCD     USART3_IRQHandler         ; USART3\r
+                DCD     EXTI15_10_IRQHandler      ; EXTI Line 15..10\r
+                DCD     RTC_Alarm_IRQHandler      ; RTC Alarm through EXTI Line\r
+                DCD     USB_FS_WKUP_IRQHandler    ; USB FS Wakeup from suspend\r
+                DCD     TIM6_IRQHandler           ; TIM6\r
+                DCD     TIM7_IRQHandler           ; TIM7\r
+__Vectors_End\r
+\r
+__Vectors_Size  EQU  __Vectors_End - __Vectors\r
+\r
+                AREA    |.text|, CODE, READONLY\r
+\r
+; Reset handler routine\r
+Reset_Handler    PROC\r
+                 EXPORT  Reset_Handler             [WEAK]\r
+        IMPORT  __main\r
+        IMPORT  SystemInit  \r
+                 LDR     R0, =SystemInit\r
+                 BLX     R0              \r
+                 LDR     R0, =__main\r
+                 BX      R0\r
+                 ENDP\r
+\r
+; Dummy Exception Handlers (infinite loops which can be modified)\r
+\r
+NMI_Handler     PROC\r
+                EXPORT  NMI_Handler                [WEAK]\r
+                B       .\r
+                ENDP\r
+HardFault_Handler\\r
+                PROC\r
+                EXPORT  HardFault_Handler          [WEAK]\r
+                B       .\r
+                ENDP\r
+MemManage_Handler\\r
+                PROC\r
+                EXPORT  MemManage_Handler          [WEAK]\r
+                B       .\r
+                ENDP\r
+BusFault_Handler\\r
+                PROC\r
+                EXPORT  BusFault_Handler           [WEAK]\r
+                B       .\r
+                ENDP\r
+UsageFault_Handler\\r
+                PROC\r
+                EXPORT  UsageFault_Handler         [WEAK]\r
+                B       .\r
+                ENDP\r
+SVC_Handler     PROC\r
+                EXPORT  SVC_Handler                [WEAK]\r
+                B       .\r
+                ENDP\r
+DebugMon_Handler\\r
+                PROC\r
+                EXPORT  DebugMon_Handler           [WEAK]\r
+                B       .\r
+                ENDP\r
+PendSV_Handler  PROC\r
+                EXPORT  PendSV_Handler             [WEAK]\r
+                B       .\r
+                ENDP\r
+SysTick_Handler PROC\r
+                EXPORT  SysTick_Handler            [WEAK]\r
+                B       .\r
+                ENDP\r
+\r
+Default_Handler PROC\r
+\r
+                EXPORT  WWDG_IRQHandler            [WEAK]\r
+                EXPORT  PVD_IRQHandler             [WEAK]\r
+                EXPORT  TAMPER_STAMP_IRQHandler    [WEAK]\r
+                EXPORT  RTC_WKUP_IRQHandler        [WEAK]\r
+                EXPORT  FLASH_IRQHandler           [WEAK]\r
+                EXPORT  RCC_IRQHandler             [WEAK]\r
+                EXPORT  EXTI0_IRQHandler           [WEAK]\r
+                EXPORT  EXTI1_IRQHandler           [WEAK]\r
+                EXPORT  EXTI2_IRQHandler           [WEAK]\r
+                EXPORT  EXTI3_IRQHandler           [WEAK]\r
+                EXPORT  EXTI4_IRQHandler           [WEAK]\r
+                EXPORT  DMA1_Channel1_IRQHandler   [WEAK]\r
+                EXPORT  DMA1_Channel2_IRQHandler   [WEAK]\r
+                EXPORT  DMA1_Channel3_IRQHandler   [WEAK]\r
+                EXPORT  DMA1_Channel4_IRQHandler   [WEAK]\r
+                EXPORT  DMA1_Channel5_IRQHandler   [WEAK]\r
+                EXPORT  DMA1_Channel6_IRQHandler   [WEAK]\r
+                EXPORT  DMA1_Channel7_IRQHandler   [WEAK]\r
+                EXPORT  ADC1_IRQHandler            [WEAK]\r
+                EXPORT  USB_HP_IRQHandler          [WEAK]\r
+                EXPORT  USB_LP_IRQHandler          [WEAK]\r
+                EXPORT  DAC_IRQHandler             [WEAK]\r
+                EXPORT  COMP_IRQHandler            [WEAK]\r
+                EXPORT  EXTI9_5_IRQHandler         [WEAK]\r
+                EXPORT  LCD_IRQHandler             [WEAK]\r
+                EXPORT  TIM9_IRQHandler            [WEAK]\r
+                EXPORT  TIM10_IRQHandler           [WEAK]\r
+                EXPORT  TIM11_IRQHandler           [WEAK]\r
+                EXPORT  TIM2_IRQHandler            [WEAK]\r
+                EXPORT  TIM3_IRQHandler            [WEAK]\r
+                EXPORT  TIM4_IRQHandler            [WEAK]\r
+                EXPORT  I2C1_EV_IRQHandler         [WEAK]\r
+                EXPORT  I2C1_ER_IRQHandler         [WEAK]\r
+                EXPORT  I2C2_EV_IRQHandler         [WEAK]\r
+                EXPORT  I2C2_ER_IRQHandler         [WEAK]\r
+                EXPORT  SPI1_IRQHandler            [WEAK]\r
+                EXPORT  SPI2_IRQHandler            [WEAK]\r
+                EXPORT  USART1_IRQHandler          [WEAK]\r
+                EXPORT  USART2_IRQHandler          [WEAK]\r
+                EXPORT  USART3_IRQHandler          [WEAK]\r
+                EXPORT  EXTI15_10_IRQHandler       [WEAK]\r
+                EXPORT  RTC_Alarm_IRQHandler       [WEAK]\r
+                EXPORT  USB_FS_WKUP_IRQHandler     [WEAK]\r
+                EXPORT  TIM6_IRQHandler            [WEAK]\r
+                EXPORT  TIM7_IRQHandler            [WEAK]\r
+\r
+WWDG_IRQHandler\r
+PVD_IRQHandler\r
+TAMPER_STAMP_IRQHandler\r
+RTC_WKUP_IRQHandler\r
+FLASH_IRQHandler\r
+RCC_IRQHandler\r
+EXTI0_IRQHandler\r
+EXTI1_IRQHandler\r
+EXTI2_IRQHandler\r
+EXTI3_IRQHandler\r
+EXTI4_IRQHandler\r
+DMA1_Channel1_IRQHandler\r
+DMA1_Channel2_IRQHandler\r
+DMA1_Channel3_IRQHandler\r
+DMA1_Channel4_IRQHandler\r
+DMA1_Channel5_IRQHandler\r
+DMA1_Channel6_IRQHandler\r
+DMA1_Channel7_IRQHandler\r
+ADC1_IRQHandler\r
+USB_HP_IRQHandler\r
+USB_LP_IRQHandler\r
+DAC_IRQHandler\r
+COMP_IRQHandler\r
+EXTI9_5_IRQHandler\r
+LCD_IRQHandler\r
+TIM9_IRQHandler\r
+TIM10_IRQHandler\r
+TIM11_IRQHandler\r
+TIM2_IRQHandler\r
+TIM3_IRQHandler\r
+TIM4_IRQHandler\r
+I2C1_EV_IRQHandler\r
+I2C1_ER_IRQHandler\r
+I2C2_EV_IRQHandler\r
+I2C2_ER_IRQHandler\r
+SPI1_IRQHandler\r
+SPI2_IRQHandler\r
+USART1_IRQHandler\r
+USART2_IRQHandler\r
+USART3_IRQHandler\r
+EXTI15_10_IRQHandler\r
+RTC_Alarm_IRQHandler\r
+USB_FS_WKUP_IRQHandler\r
+TIM6_IRQHandler\r
+TIM7_IRQHandler\r
+\r
+                B       .\r
+\r
+                ENDP\r
+\r
+                ALIGN\r
+\r
+;*******************************************************************************\r
+; User Stack and Heap initialization\r
+;*******************************************************************************\r
+                 IF      :DEF:__MICROLIB           \r
+                \r
+                 EXPORT  __initial_sp\r
+                 EXPORT  __heap_base\r
+                 EXPORT  __heap_limit\r
+                \r
+                 ELSE\r
+                \r
+                 IMPORT  __use_two_region_memory\r
+                 EXPORT  __user_initial_stackheap\r
+                 \r
+__user_initial_stackheap\r
+\r
+                 LDR     R0, =  Heap_Mem\r
+                 LDR     R1, =(Stack_Mem + Stack_Size)\r
+                 LDR     R2, = (Heap_Mem +  Heap_Size)\r
+                 LDR     R3, = Stack_Mem\r
+                 BX      LR\r
+\r
+                 ALIGN\r
+\r
+                 ENDIF\r
+\r
+                 END\r
+\r
+;******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE*****\r

diff --git a/Demo/CORTEX_STM32L152_IAR/system_and_ST_code/CMSIS/CM3/DeviceSupport/ST/STM32L1xx/startup/iar/startup_stm32l1xx_md.s b/Demo/CORTEX_STM32L152_IAR/system_and_ST_code/CMSIS/CM3/DeviceSupport/ST/STM32L1xx/startup/iar/startup_stm32l1xx_md.s
new file mode 100644 (file)
index 0000000..43aa9a4
--- /dev/null
+++ b/Demo/CORTEX_STM32L152_IAR/system_and_ST_code/CMSIS/CM3/DeviceSupport/ST/STM32L1xx/startup/iar/startup_stm32l1xx_md.s
@@ -0,0 +1,455 @@
+;/******************** (C) COPYRIGHT 2010 STMicroelectronics ********************\r
+;* File Name          : startup_stm32l15x_lp.s\r
+;* Author             : MCD Application Team\r
+;* Version            : V1.0.0RC1\r
+;* Date               : 07/02/2010\r
+;* Description        : STM32L15x Low Power Devices vector table for EWARM5.x toolchain.\r
+;*                      This module performs:\r
+;*                      - Set the initial SP\r
+;*                      - Set the initial PC == __iar_program_start,\r
+;*                      - Set the vector table entries with the exceptions ISR \r
+;*                        address.\r
+;*                      After Reset the Cortex-M3 processor is in Thread mode,\r
+;*                      priority is Privileged, and the Stack is set to Main.\r
+;********************************************************************************\r
+;* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+;* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
+;* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,\r
+;* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE\r
+;* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING\r
+;* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+;*******************************************************************************/\r
+;\r
+;\r
+; The modules in this file are included in the libraries, and may be replaced\r
+; by any user-defined modules that define the PUBLIC symbol _program_start or\r
+; a user defined start symbol.\r
+; To override the cstartup defined in the library, simply add your modified\r
+; version to the workbench project.\r
+;\r
+; The vector table is normally located at address 0.\r
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.\r
+; The name "__vector_table" has special meaning for C-SPY:\r
+; it is where the SP start value is found, and the NVIC vector\r
+; table register (VTOR) is initialized to this address if != 0.\r
+;\r
+; Cortex-M version\r
+;\r
+\r
+        MODULE  ?cstartup\r
+\r
+        ;; Forward declaration of sections.\r
+        SECTION CSTACK:DATA:NOROOT(3)\r
+\r
+        SECTION .intvec:CODE:NOROOT(2)\r
+\r
+        EXTERN  __iar_program_start\r
+        EXTERN  SystemInit        \r
+        PUBLIC  __vector_table\r
+\r
+        DATA\r
+__vector_table\r
+        DCD     sfe(CSTACK)\r
+        DCD     Reset_Handler             ; Reset Handler\r
+\r
+        DCD     NMI_Handler               ; NMI Handler\r
+        DCD     HardFault_Handler         ; Hard Fault Handler\r
+        DCD     MemManage_Handler         ; MPU Fault Handler\r
+        DCD     BusFault_Handler          ; Bus Fault Handler\r
+        DCD     UsageFault_Handler        ; Usage Fault Handler\r
+        DCD     0                         ; Reserved\r
+        DCD     0                         ; Reserved\r
+        DCD     0                         ; Reserved\r
+        DCD     0                         ; Reserved\r
+        DCD     SVC_Handler               ; SVCall Handler\r
+        DCD     DebugMon_Handler          ; Debug Monitor Handler\r
+        DCD     0                         ; Reserved\r
+        DCD     PendSV_Handler            ; PendSV Handler\r
+        DCD     SysTick_Handler           ; SysTick Handler\r
+\r
+         ; External Interrupts\r
+        DCD     WWDG_IRQHandler           ; Window Watchdog\r
+        DCD     PVD_IRQHandler            ; PVD through EXTI Line detect\r
+        DCD     TAMPER_STAMP_IRQHandler   ; Tamper and Time Stamp\r
+        DCD     RTC_WKUP_IRQHandler       ; RTC Wakeup\r
+        DCD     FLASH_IRQHandler          ; FLASH\r
+        DCD     RCC_IRQHandler            ; RCC\r
+        DCD     EXTI0_IRQHandler          ; EXTI Line 0\r
+        DCD     EXTI1_IRQHandler          ; EXTI Line 1\r
+        DCD     EXTI2_IRQHandler          ; EXTI Line 2\r
+        DCD     EXTI3_IRQHandler          ; EXTI Line 3\r
+        DCD     EXTI4_IRQHandler          ; EXTI Line 4\r
+        DCD     DMA1_Channel1_IRQHandler  ; DMA1 Channel 1\r
+        DCD     DMA1_Channel2_IRQHandler  ; DMA1 Channel 2\r
+        DCD     DMA1_Channel3_IRQHandler  ; DMA1 Channel 3\r
+        DCD     DMA1_Channel4_IRQHandler  ; DMA1 Channel 4\r
+        DCD     DMA1_Channel5_IRQHandler  ; DMA1 Channel 5\r
+        DCD     DMA1_Channel6_IRQHandler  ; DMA1 Channel 6\r
+        DCD     DMA1_Channel7_IRQHandler  ; DMA1 Channel 7\r
+        DCD     ADC1_IRQHandler           ; ADC1\r
+        DCD     USB_HP_IRQHandler         ; USB High Priority\r
+        DCD     USB_LP_IRQHandler         ; USB Low  Priority\r
+        DCD     DAC_IRQHandler            ; DAC\r
+        DCD     COMP_IRQHandler           ; COMP through EXTI Line\r
+        DCD     EXTI9_5_IRQHandler        ; EXTI Line 9..5\r
+        DCD     LCD_IRQHandler            ; LCD\r
+        DCD     TIM9_IRQHandler           ; TIM9\r
+        DCD     TIM10_IRQHandler          ; TIM10\r
+        DCD     TIM11_IRQHandler          ; TIM11\r
+        DCD     TIM2_IRQHandler           ; TIM2\r
+        DCD     TIM3_IRQHandler           ; TIM3\r
+        DCD     TIM4_IRQHandler           ; TIM4\r
+        DCD     I2C1_EV_IRQHandler        ; I2C1 Event\r
+        DCD     I2C1_ER_IRQHandler        ; I2C1 Error\r
+        DCD     I2C2_EV_IRQHandler        ; I2C2 Event\r
+        DCD     I2C2_ER_IRQHandler        ; I2C2 Error\r
+        DCD     SPI1_IRQHandler           ; SPI1\r
+        DCD     SPI2_IRQHandler           ; SPI2\r
+        DCD     USART1_IRQHandler         ; USART1\r
+        DCD     USART2_IRQHandler         ; USART2\r
+        DCD     USART3_IRQHandler         ; USART3\r
+        DCD     EXTI15_10_IRQHandler      ; EXTI Line 15..10\r
+        DCD     RTC_Alarm_IRQHandler      ; RTC Alarm through EXTI Line\r
+        DCD     USB_FS_WKUP_IRQHandler    ; USB FS Wakeup from suspend\r
+        DCD     TIM6_IRQHandler           ; TIM6\r
+        DCD     TIM7_IRQHandler           ; TIM7\r
+        \r
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\r
+;;\r
+;; Default interrupt handlers.\r
+;;\r
+        THUMB\r
+\r
+        PUBWEAK Reset_Handler\r
+        SECTION .text:CODE:REORDER(2)\r
+Reset_Handler\r
+        LDR     R0, =SystemInit\r
+        BLX     R0\r
+        LDR     R0, =__iar_program_start\r
+        BX      R0\r
+        \r
+        PUBWEAK NMI_Handler\r
+        SECTION .text:CODE:REORDER(1)\r
+NMI_Handler\r
+        B NMI_Handler\r
+        \r
+        \r
+        PUBWEAK HardFault_Handler\r
+        SECTION .text:CODE:REORDER(1)\r
+HardFault_Handler\r
+        B HardFault_Handler\r
+        \r
+        \r
+        PUBWEAK MemManage_Handler\r
+        SECTION .text:CODE:REORDER(1)\r
+MemManage_Handler\r
+        B MemManage_Handler\r
+        \r
+                \r
+        PUBWEAK BusFault_Handler\r
+        SECTION .text:CODE:REORDER(1)\r
+BusFault_Handler\r
+        B BusFault_Handler\r
+        \r
+        \r
+        PUBWEAK UsageFault_Handler\r
+        SECTION .text:CODE:REORDER(1)\r
+UsageFault_Handler\r
+        B UsageFault_Handler\r
+        \r
+        \r
+        PUBWEAK SVC_Handler\r
+        SECTION .text:CODE:REORDER(1)\r
+SVC_Handler\r
+        B SVC_Handler\r
+        \r
+        \r
+        PUBWEAK DebugMon_Handler\r
+        SECTION .text:CODE:REORDER(1)\r
+DebugMon_Handler\r
+        B DebugMon_Handler\r
+        \r
+        \r
+        PUBWEAK PendSV_Handler\r
+        SECTION .text:CODE:REORDER(1)\r
+PendSV_Handler\r
+        B PendSV_Handler\r
+        \r
+        \r
+        PUBWEAK SysTick_Handler\r
+        SECTION .text:CODE:REORDER(1)\r
+SysTick_Handler\r
+        B SysTick_Handler\r
+        \r
+        \r
+        PUBWEAK WWDG_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+WWDG_IRQHandler\r
+        B WWDG_IRQHandler\r
+        \r
+        \r
+        PUBWEAK PVD_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+PVD_IRQHandler\r
+        B PVD_IRQHandler\r
+        \r
+        \r
+        PUBWEAK TAMPER_STAMP_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+TAMPER_STAMP_IRQHandler\r
+        B TAMPER_STAMP_IRQHandler\r
+        \r
+        \r
+        PUBWEAK RTC_WKUP_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+RTC_WKUP_IRQHandler\r
+        B RTC_WKUP_IRQHandler\r
+        \r
+        \r
+        PUBWEAK FLASH_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+FLASH_IRQHandler\r
+        B FLASH_IRQHandler\r
+        \r
+        \r
+        PUBWEAK RCC_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+RCC_IRQHandler\r
+        B RCC_IRQHandler\r
+        \r
+        \r
+        PUBWEAK EXTI0_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+EXTI0_IRQHandler\r
+        B EXTI0_IRQHandler\r
+        \r
+        \r
+        PUBWEAK EXTI1_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+EXTI1_IRQHandler\r
+        B EXTI1_IRQHandler\r
+        \r
+        \r
+        PUBWEAK EXTI2_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+EXTI2_IRQHandler\r
+        B EXTI2_IRQHandler\r
+        \r
+        \r
+        PUBWEAK EXTI3_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+EXTI3_IRQHandler\r
+        B EXTI3_IRQHandler\r
+        \r
+        \r
+        PUBWEAK EXTI4_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+EXTI4_IRQHandler\r
+        B EXTI4_IRQHandler\r
+        \r
+        \r
+        PUBWEAK DMA1_Channel1_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+DMA1_Channel1_IRQHandler\r
+        B DMA1_Channel1_IRQHandler\r
+        \r
+        \r
+        PUBWEAK DMA1_Channel2_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+DMA1_Channel2_IRQHandler\r
+        B DMA1_Channel2_IRQHandler\r
+        \r
+        \r
+        PUBWEAK DMA1_Channel3_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+DMA1_Channel3_IRQHandler\r
+        B DMA1_Channel3_IRQHandler\r
+        \r
+        \r
+        PUBWEAK DMA1_Channel4_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+DMA1_Channel4_IRQHandler\r
+        B DMA1_Channel4_IRQHandler\r
+        \r
+        \r
+        PUBWEAK DMA1_Channel5_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+DMA1_Channel5_IRQHandler\r
+        B DMA1_Channel5_IRQHandler\r
+        \r
+        \r
+        PUBWEAK DMA1_Channel6_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+DMA1_Channel6_IRQHandler\r
+        B DMA1_Channel6_IRQHandler\r
+        \r
+        \r
+        PUBWEAK DMA1_Channel7_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+DMA1_Channel7_IRQHandler\r
+        B DMA1_Channel7_IRQHandler\r
+        \r
+        \r
+        PUBWEAK ADC1_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+ADC1_IRQHandler\r
+        B ADC1_IRQHandler\r
+        \r
+        \r
+        PUBWEAK USB_HP_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+USB_HP_IRQHandler\r
+        B USB_HP_IRQHandler\r
+        \r
+        \r
+        PUBWEAK USB_LP_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+USB_LP_IRQHandler\r
+        B USB_LP_IRQHandler\r
+        \r
+        \r
+        PUBWEAK DAC_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+DAC_IRQHandler\r
+        B DAC_IRQHandler\r
+        \r
+        \r
+        PUBWEAK COMP_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+COMP_IRQHandler\r
+        B COMP_IRQHandler\r
+        \r
+        \r
+        PUBWEAK EXTI9_5_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+EXTI9_5_IRQHandler\r
+        B EXTI9_5_IRQHandler\r
+        \r
+        \r
+        PUBWEAK LCD_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+LCD_IRQHandler\r
+        B LCD_IRQHandler\r
+        \r
+        \r
+        PUBWEAK TIM9_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+TIM9_IRQHandler\r
+        B TIM9_IRQHandler\r
+        \r
+        \r
+        PUBWEAK TIM10_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+TIM10_IRQHandler\r
+        B TIM10_IRQHandler\r
+        \r
+        \r
+        PUBWEAK TIM11_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+TIM11_IRQHandler\r
+        B TIM11_IRQHandler\r
+        \r
+        \r
+        PUBWEAK TIM2_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+TIM2_IRQHandler\r
+        B TIM2_IRQHandler\r
+        \r
+        \r
+        PUBWEAK TIM3_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+TIM3_IRQHandler\r
+        B TIM3_IRQHandler\r
+        \r
+        \r
+        PUBWEAK TIM4_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+TIM4_IRQHandler\r
+        B TIM4_IRQHandler\r
+        \r
+        \r
+        PUBWEAK I2C1_EV_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+I2C1_EV_IRQHandler\r
+        B I2C1_EV_IRQHandler\r
+        \r
+        \r
+        PUBWEAK I2C1_ER_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+I2C1_ER_IRQHandler\r
+        B I2C1_ER_IRQHandler\r
+        \r
+        \r
+        PUBWEAK I2C2_EV_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+I2C2_EV_IRQHandler\r
+        B I2C2_EV_IRQHandler\r
+        \r
+        \r
+        PUBWEAK I2C2_ER_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+I2C2_ER_IRQHandler\r
+        B I2C2_ER_IRQHandler\r
+        \r
+        \r
+        PUBWEAK SPI1_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+SPI1_IRQHandler\r
+        B SPI1_IRQHandler\r
+        \r
+        \r
+        PUBWEAK SPI2_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+SPI2_IRQHandler\r
+        B SPI2_IRQHandler\r
+        \r
+        \r
+        PUBWEAK USART1_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+USART1_IRQHandler\r
+        B USART1_IRQHandler\r
+        \r
+        \r
+        PUBWEAK USART2_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+USART2_IRQHandler\r
+        B USART2_IRQHandler\r
+        \r
+        \r
+        PUBWEAK USART3_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+USART3_IRQHandler\r
+        B USART3_IRQHandler\r
+        \r
+        \r
+        PUBWEAK EXTI15_10_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+EXTI15_10_IRQHandler\r
+        B EXTI15_10_IRQHandler\r
+        \r
+        \r
+        PUBWEAK RTC_Alarm_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+RTC_Alarm_IRQHandler\r
+        B RTC_Alarm_IRQHandler\r
+        \r
+        \r
+        PUBWEAK USB_FS_WKUP_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+USB_FS_WKUP_IRQHandler\r
+        B USB_FS_WKUP_IRQHandler\r
+        \r
+\r
+        PUBWEAK TIM6_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+TIM6_IRQHandler\r
+        B TIM6_IRQHandler\r
+        \r
+\r
+        PUBWEAK TIM7_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+TIM7_IRQHandler\r
+        B TIM7_IRQHandler                \r
+\r
+        END\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r

diff --git a/Demo/CORTEX_STM32L152_IAR/system_and_ST_code/CMSIS/CM3/DeviceSupport/ST/STM32L1xx/stm32l1xx.h b/Demo/CORTEX_STM32L152_IAR/system_and_ST_code/CMSIS/CM3/DeviceSupport/ST/STM32L1xx/stm32l1xx.h
new file mode 100644 (file)
index 0000000..1fa0eda
--- /dev/null
+++ b/Demo/CORTEX_STM32L152_IAR/system_and_ST_code/CMSIS/CM3/DeviceSupport/ST/STM32L1xx/stm32l1xx.h
@@ -0,0 +1,5043 @@
+/**\r
+  ******************************************************************************\r
+  * @file    stm32l1xx.h\r
+  * @author  STMicroelectronics - MCD Application Team\r
+  * @version V1.0.0RC1\r
+  * @date    07/02/2010\r
+  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer Header File. \r
+  *          This file contains all the peripheral register's definitions, bits \r
+  *          definitions and memory mapping for STM32L1xx devices.  \r
+  ******************************************************************************\r
+  *\r
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+  *\r
+  * <h2><center>&copy; COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+  ******************************************************************************\r
+  */\r
+\r
+/** @addtogroup CMSIS\r
+  * @{\r
+  */\r
+\r
+/** @addtogroup stm32l1xx\r
+  * @{\r
+  */\r
+    \r
+#ifndef __STM32L1XX_H\r
+#define __STM32L1XX_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif \r
+  \r
+/** @addtogroup Library_configuration_section\r
+  * @{\r
+  */\r
+  \r
+/* Uncomment the line below according to the target STM32L device used in your \r
+   application \r
+  */\r
+\r
+#if !defined (STM32L1XX_MD)\r
+  #define STM32L1XX_MD    /*!< STM32L1XX_MD: STM32L Ultra Low Power Medium-density devices */\r
+#endif\r
+/*  Tip: To avoid modifying this file each time you need to switch between these\r
+        devices, you can define the device in your toolchain compiler preprocessor.\r
+\r
+ - Ultra Low Power Medium-density devices are STM32L151xx and STM32L152xx \r
+   microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.\r
+\r
+  */\r
+\r
+#if !defined  USE_STDPERIPH_DRIVER\r
+/**\r
+ * @brief Comment the line below if you will not use the peripherals drivers.\r
+   In this case, these drivers will not be included and the application code will \r
+   be based on direct access to peripherals registers \r
+   */\r
+  /*#define USE_STDPERIPH_DRIVER*/\r
+#endif\r
+\r
+/**\r
+ * @brief In the following line adjust the value of External High Speed oscillator (HSE)\r
+   used in your application \r
+   \r
+   Tip: To avoid modifying this file each time you need to use different HSE, you\r
+        can define the HSE value in your toolchain compiler preprocessor.\r
+  */  \r
+#define HSE_VALUE    ((uint32_t)8000000) /*!< Value of the External oscillator in Hz*/\r
+\r
+/**\r
+ * @brief In the following line adjust the External High Speed oscillator (HSE) Startup \r
+   Timeout value \r
+   */\r
+#define HSE_STARTUP_TIMEOUT   ((uint16_t)0x0500) /*!< Time out for HSE start up */\r
+\r
+#define MSI_VALUE  ((uint32_t)2000000)  /*!< Default value of the Internal Multi Speed oscillator in Hz */\r
+#define HSI_VALUE  ((uint32_t)16000000) /*!< Value of the Internal High Speed oscillator in Hz */\r
+#define LSI_VALUE  ((uint32_t)37000)    /*!< Value of the Internal Low Speed oscillator in Hz */\r
+#define LSE_VALUE  ((uint32_t)32768)    /*!< Value of the External Low Speed oscillator in Hz */\r
+\r
+/**\r
+ * @brief STM32L1xx Standard Peripheral Library version number\r
+   */\r
+#define __STM32L1XX_STDPERIPH_VERSION_MAIN   (0x01) /*!< [31:16] STM32L1xx Standard Peripheral Library main version */                                  \r
+#define __STM32L1XX_STDPERIPH_VERSION_SUB1   (0x00) /*!< [15:8]  STM32L1xx Standard Peripheral Library sub1 version */\r
+#define __STM32L1XX_STDPERIPH_VERSION_SUB2   (0x00) /*!< [7:0]  STM32L1xx Standard Peripheral Library sub2 version */ \r
+#define __STM32L1XX_STDPERIPH_VERSION       ((__STM32L1XX_STDPERIPH_VERSION_MAIN << 16)\\r
+                                             | (__STM32L1XX_STDPERIPH_VERSION_SUB1 << 8)\\r
+                                             | __STM32L1XX_STDPERIPH_VERSION_SUB2)\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @addtogroup Configuration_section_for_CMSIS\r
+  * @{\r
+  */\r
+\r
+/**\r
+ * @brief STM32L1xx Interrupt Number Definition, according to the selected device \r
+ *        in @ref Library_configuration_section \r
+ */\r
+#define __MPU_PRESENT             1 /*!< STM32L provide a MPU present */\r
+#define __NVIC_PRIO_BITS          4 /*!< STM32 uses 4 Bits for the Priority Levels    */\r
+#define __Vendor_SysTickConfig    0 /*!< Set to 1 if different SysTick Config is used */\r
+\r
+/*!< Interrupt Number Definition */\r
+typedef enum IRQn\r
+{\r
+/******  Cortex-M3 Processor Exceptions Numbers ***************************************************/\r
+  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                             */\r
+  MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M3 Memory Management Interrupt              */\r
+  BusFault_IRQn               = -11,    /*!< 5 Cortex-M3 Bus Fault Interrupt                      */\r
+  UsageFault_IRQn             = -10,    /*!< 6 Cortex-M3 Usage Fault Interrupt                    */\r
+  SVCall_IRQn                 = -5,     /*!< 11 Cortex-M3 SV Call Interrupt                       */\r
+  DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M3 Debug Monitor Interrupt                 */\r
+  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M3 Pend SV Interrupt                       */\r
+  SysTick_IRQn                = -1,     /*!< 15 Cortex-M3 System Tick Interrupt                   */\r
+\r
+/******  STM32L specific Interrupt Numbers ********************************************************/\r
+  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                            */\r
+  PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detection Interrupt            */\r
+  TAMPER_STAMP_IRQn           = 2,      /*!< Tamper and Time Stamp through EXTI Line Interrupts   */\r
+  RTC_WKUP_IRQn               = 3,      /*!< RTC Wakeup Timer through EXTI Line Interrupt         */\r
+  FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                               */\r
+  RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                 */\r
+  EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                 */\r
+  EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                 */\r
+  EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                 */\r
+  EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                 */\r
+  EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                 */\r
+  DMA1_Channel1_IRQn          = 11,     /*!< DMA1 Channel 1 global Interrupt                      */\r
+  DMA1_Channel2_IRQn          = 12,     /*!< DMA1 Channel 2 global Interrupt                      */\r
+  DMA1_Channel3_IRQn          = 13,     /*!< DMA1 Channel 3 global Interrupt                      */\r
+  DMA1_Channel4_IRQn          = 14,     /*!< DMA1 Channel 4 global Interrupt                      */\r
+  DMA1_Channel5_IRQn          = 15,     /*!< DMA1 Channel 5 global Interrupt                      */\r
+  DMA1_Channel6_IRQn          = 16,     /*!< DMA1 Channel 6 global Interrupt                      */\r
+  DMA1_Channel7_IRQn          = 17,     /*!< DMA1 Channel 7 global Interrupt                      */\r
+  ADC1_IRQn                   = 18,     /*!< ADC1 global Interrupt                                */\r
+  USB_HP_IRQn                 = 19,     /*!< USB High Priority Interrupt                          */\r
+  USB_LP_IRQn                 = 20,     /*!< USB Low Priority Interrupt                           */\r
+  DAC_IRQn                    = 21,     /*!< DAC Interrupt                                        */\r
+  COMP_IRQn                   = 22,     /*!< Comparator through EXTI Line Interrupt               */\r
+  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                        */\r
+  LCD_IRQn                    = 24,     /*!< LCD Interrupt                                        */\r
+  TIM9_IRQn                   = 25,     /*!< TIM9 global Interrupt                                */\r
+  TIM10_IRQn                  = 26,     /*!< TIM10 global Interrupt                               */\r
+  TIM11_IRQn                  = 27,     /*!< TIM11 global Interrupt                               */\r
+  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                */\r
+  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                */\r
+  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                */  \r
+  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                 */\r
+  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                 */\r
+  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                 */\r
+  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                 */  \r
+  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                */\r
+  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                */\r
+  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                              */\r
+  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                              */  \r
+  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                              */  \r
+  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                      */\r
+  RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm through EXTI Line Interrupt                */\r
+  USB_FS_WKUP_IRQn            = 42,     /*!< USB FS WakeUp from suspend through EXTI Line Interrupt  */\r
+  TIM6_IRQn                   = 43,     /*!< TIM6 global Interrupt                                */\r
+  TIM7_IRQn                   = 44      /*!< TIM7 global Interrupt                                */\r
+} IRQn_Type;\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+#include "core_cm3.h"\r
+#include "system_stm32l1xx.h"\r
+#include <stdint.h>\r
+\r
+/** @addtogroup Exported_types\r
+  * @{\r
+  */  \r
+\r
+typedef enum {FALSE = 0, TRUE = !FALSE} bool;\r
+\r
+typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;\r
+\r
+typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;\r
+#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))\r
+\r
+typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @addtogroup Peripheral_registers_structures\r
+  * @{\r
+  */   \r
+\r
+/** \r
+  * @brief Analog to Digital Converter  \r
+  */\r
+\r
+typedef struct\r
+{\r
+  __IO uint32_t SR;\r
+  __IO uint32_t CR1;\r
+  __IO uint32_t CR2;\r
+  __IO uint32_t SMPR1;\r
+  __IO uint32_t SMPR2;\r
+  __IO uint32_t SMPR3;\r
+  __IO uint32_t JOFR1;\r
+  __IO uint32_t JOFR2;\r
+  __IO uint32_t JOFR3;\r
+  __IO uint32_t JOFR4;\r
+  __IO uint32_t HTR;\r
+  __IO uint32_t LTR;\r
+  __IO uint32_t SQR1;\r
+  __IO uint32_t SQR2;\r
+  __IO uint32_t SQR3;\r
+  __IO uint32_t SQR4;\r
+  __IO uint32_t SQR5;\r
+  __IO uint32_t JSQR;\r
+  __IO uint32_t JDR1;\r
+  __IO uint32_t JDR2;\r
+  __IO uint32_t JDR3;\r
+  __IO uint32_t JDR4;\r
+  __IO uint32_t DR;\r
+} ADC_TypeDef;\r
+\r
+typedef struct\r
+{\r
+  __IO uint32_t CSR;\r
+  __IO uint32_t CCR;\r
+} ADC_Common_TypeDef;\r
+\r
+\r
+/** \r
+  * @brief Comparator \r
+  */\r
+\r
+typedef struct\r
+{\r
+  __IO uint32_t CSR;\r
+} COMP_TypeDef;\r
+\r
+/** \r
+  * @brief CRC calculation unit \r
+  */\r
+\r
+typedef struct\r
+{\r
+  __IO uint32_t DR;\r
+  __IO uint8_t  IDR;\r
+  uint8_t   RESERVED0;\r
+  uint16_t  RESERVED1;\r
+  __IO uint32_t CR;\r
+} CRC_TypeDef;\r
+\r
+/** \r
+  * @brief Digital to Analog Converter\r
+  */\r
+\r
+typedef struct\r
+{\r
+  __IO uint32_t CR;\r
+  __IO uint32_t SWTRIGR;\r
+  __IO uint32_t DHR12R1;\r
+  __IO uint32_t DHR12L1;\r
+  __IO uint32_t DHR8R1;\r
+  __IO uint32_t DHR12R2;\r
+  __IO uint32_t DHR12L2;\r
+  __IO uint32_t DHR8R2;\r
+  __IO uint32_t DHR12RD;\r
+  __IO uint32_t DHR12LD;\r
+  __IO uint32_t DHR8RD;\r
+  __IO uint32_t DOR1;\r
+  __IO uint32_t DOR2;\r
+  __IO uint32_t SR;  \r
+} DAC_TypeDef;\r
+\r
+/** \r
+  * @brief Debug MCU\r
+  */\r
+\r
+typedef struct\r
+{\r
+  __IO uint32_t IDCODE;\r
+  __IO uint32_t CR;\r
+  __IO uint32_t APB1FZ;\r
+  __IO uint32_t APB2FZ;        \r
+}DBGMCU_TypeDef;\r
+\r
+/** \r
+  * @brief DMA Controller\r
+  */\r
+\r
+typedef struct\r
+{\r
+  __IO uint32_t CCR;\r
+  __IO uint32_t CNDTR;\r
+  __IO uint32_t CPAR;\r
+  __IO uint32_t CMAR;\r
+} DMA_Channel_TypeDef;\r
+\r
+typedef struct\r
+{\r
+  __IO uint32_t ISR;\r
+  __IO uint32_t IFCR;\r
+} DMA_TypeDef;\r
+\r
+/** \r
+  * @brief External Interrupt/Event Controller\r
+  */\r
+\r
+typedef struct\r
+{\r
+  __IO uint32_t IMR;\r
+  __IO uint32_t EMR;\r
+  __IO uint32_t RTSR;\r
+  __IO uint32_t FTSR;\r
+  __IO uint32_t SWIER;\r
+  __IO uint32_t PR;\r
+} EXTI_TypeDef;\r
+\r
+/** \r
+  * @brief FLASH Registers\r
+  */\r
+\r
+typedef struct\r
+{\r
+  __IO uint32_t ACR;\r
+  __IO uint32_t PECR;\r
+  __IO uint32_t PDKEYR;\r
+  __IO uint32_t PEKEYR;\r
+  __IO uint32_t PRGKEYR;\r
+  __IO uint32_t OPTKEYR;\r
+  __IO uint32_t SR;\r
+  __IO uint32_t OBR;\r
+  __IO uint32_t WRPR;       \r
+} FLASH_TypeDef;\r
+\r
+/** \r
+  * @brief Option Bytes Registers\r
+  */\r
+  \r
+typedef struct\r
+{\r
+  __IO uint32_t RDP;\r
+  __IO uint32_t USER;\r
+  __IO uint32_t WRP01;\r
+  __IO uint32_t WRP23;\r
+} OB_TypeDef;\r
+\r
+/** \r
+  * @brief General Purpose IO\r
+  */\r
+\r
+typedef struct\r
+{\r
+  __IO uint32_t MODER;\r
+  __IO uint16_t OTYPER;\r
+  uint16_t RESERVED0;\r
+  __IO uint32_t OSPEEDR;\r
+  __IO uint32_t PUPDR;\r
+  __IO uint16_t IDR;\r
+  uint16_t RESERVED1;\r
+  __IO uint16_t ODR;\r
+  uint16_t RESERVED2;\r
+  __IO uint16_t BSRRL; /* BSRR register is split to 2 * 16-bit fields BSRRL */\r
+  __IO uint16_t BSRRH; /* BSRR register is split to 2 * 16-bit fields BSRRH */\r
+  __IO uint32_t LCKR;\r
+  __IO uint32_t AFR[2];\r
+} GPIO_TypeDef;\r
+\r
+/** \r
+  * @brief SysTem Configuration\r
+  */\r
+\r
+typedef struct\r
+{\r
+  __IO uint32_t MEMRMP;\r
+  __IO uint32_t PMC;\r
+  __IO uint32_t EXTICR[4];\r
+} SYSCFG_TypeDef;\r
+\r
+/** \r
+  * @brief Inter-integrated Circuit Interface\r
+  */\r
+\r
+typedef struct\r
+{\r
+  __IO uint16_t CR1;\r
+  uint16_t  RESERVED0;\r
+  __IO uint16_t CR2;\r
+  uint16_t  RESERVED1;\r
+  __IO uint16_t OAR1;\r
+  uint16_t  RESERVED2;\r
+  __IO uint16_t OAR2;\r
+  uint16_t  RESERVED3;\r
+  __IO uint16_t DR;\r
+  uint16_t  RESERVED4;\r
+  __IO uint16_t SR1;\r
+  uint16_t  RESERVED5;\r
+  __IO uint16_t SR2;\r
+  uint16_t  RESERVED6;\r
+  __IO uint16_t CCR;\r
+  uint16_t  RESERVED7;\r
+  __IO uint16_t TRISE;\r
+  uint16_t  RESERVED8;\r
+} I2C_TypeDef;\r
+\r
+/** \r
+  * @brief Independent WATCHDOG\r
+  */\r
+\r
+typedef struct\r
+{\r
+  __IO uint32_t KR;\r
+  __IO uint32_t PR;\r
+  __IO uint32_t RLR;\r
+  __IO uint32_t SR;\r
+} IWDG_TypeDef;\r
+\r
+\r
+/** \r
+  * @brief LCD\r
+  */\r
+\r
+typedef struct\r
+{\r
+  __IO uint32_t CR;\r
+  __IO uint32_t FCR;\r
+  __IO uint32_t SR;\r
+  __IO uint32_t CLR;\r
+  uint32_t RESERVED;\r
+  __IO uint32_t RAM[16];\r
+} LCD_TypeDef;\r
+\r
+/** \r
+  * @brief Power Control\r
+  */\r
+\r
+typedef struct\r
+{\r
+  __IO uint32_t CR;\r
+  __IO uint32_t CSR;\r
+} PWR_TypeDef;\r
+\r
+/** \r
+  * @brief Reset and Clock Control\r
+  */\r
+\r
+typedef struct\r
+{\r
+  __IO uint32_t CR;\r
+  __IO uint32_t ICSCR;\r
+  __IO uint32_t CFGR;\r
+  __IO uint32_t CIR;\r
+  __IO uint32_t AHBRSTR;\r
+  __IO uint32_t APB2RSTR;\r
+  __IO uint32_t APB1RSTR;\r
+  __IO uint32_t AHBENR;\r
+  __IO uint32_t APB2ENR;\r
+  __IO uint32_t APB1ENR;\r
+  __IO uint32_t AHBLPENR;\r
+  __IO uint32_t APB2LPENR;\r
+  __IO uint32_t APB1LPENR;      \r
+  __IO uint32_t CSR;    \r
+} RCC_TypeDef;\r
+\r
+/** \r
+  * @brief Routing Interface \r
+  */\r
+\r
+typedef struct\r
+{\r
+  __IO uint32_t ICR;\r
+  __IO uint32_t ASCR1;\r
+  __IO uint32_t ASCR2;\r
+  __IO uint32_t HYSCR1;\r
+  __IO uint32_t HYSCR2;\r
+  __IO uint32_t HYSCR3;\r
+} RI_TypeDef;\r
+\r
+/** \r
+  * @brief Real-Time Clock\r
+  */\r
+\r
+typedef struct\r
+{\r
+  __IO uint32_t TR;\r
+  __IO uint32_t DR;\r
+  __IO uint32_t CR;\r
+  __IO uint32_t ISR;\r
+  __IO uint32_t PRER;\r
+  __IO uint32_t WUTR;\r
+  __IO uint32_t CALIBR;\r
+  __IO uint32_t ALRMAR;\r
+  __IO uint32_t ALRMBR;\r
+  __IO uint32_t WRP;\r
+  uint32_t RESERVED1;\r
+  uint32_t RESERVED2;\r
+  __IO uint32_t TSTR;\r
+  __IO uint32_t TSDR;\r
+  uint32_t RESERVED3;\r
+  uint32_t RESERVED4;\r
+  __IO uint32_t TAFCR;\r
+  uint32_t RESERVED5;\r
+  uint32_t RESERVED6;\r
+  uint32_t RESERVED7;\r
+  __IO uint32_t BK0R;\r
+  __IO uint32_t BK1R;\r
+  __IO uint32_t BK2R;\r
+  __IO uint32_t BK3R;\r
+  __IO uint32_t BK4R;\r
+  __IO uint32_t BK5R;\r
+  __IO uint32_t BK6R;\r
+  __IO uint32_t BK7R;\r
+  __IO uint32_t BK8R;\r
+  __IO uint32_t BK9R;\r
+  __IO uint32_t BK10R;\r
+  __IO uint32_t BK11R;\r
+  __IO uint32_t BK12R;\r
+  __IO uint32_t BK13R;\r
+  __IO uint32_t BK14R;\r
+  __IO uint32_t BK15R;\r
+  __IO uint32_t BK16R;\r
+  __IO uint32_t BK17R;\r
+  __IO uint32_t BK18R;\r
+  __IO uint32_t BK19R;\r
+} RTC_TypeDef;\r
+\r
+/** \r
+  * @brief Serial Peripheral Interface\r
+  */\r
+\r
+typedef struct\r
+{\r
+  __IO uint16_t CR1;\r
+  uint16_t  RESERVED0;\r
+  __IO uint16_t CR2;\r
+  uint16_t  RESERVED1;\r
+  __IO uint16_t SR;\r
+  uint16_t  RESERVED2;\r
+  __IO uint16_t DR;\r
+  uint16_t  RESERVED3;\r
+  __IO uint16_t CRCPR;\r
+  uint16_t  RESERVED4;\r
+  __IO uint16_t RXCRCR;\r
+  uint16_t  RESERVED5;\r
+  __IO uint16_t TXCRCR;\r
+  uint16_t  RESERVED6;  \r
+} SPI_TypeDef;\r
+\r
+/** \r
+  * @brief TIM\r
+  */\r
+\r
+typedef struct\r
+{\r
+  __IO uint16_t CR1;\r
+  uint16_t  RESERVED0;\r
+  __IO uint16_t CR2;\r
+  uint16_t  RESERVED1;\r
+  __IO uint16_t SMCR;\r
+  uint16_t  RESERVED2;\r
+  __IO uint16_t DIER;\r
+  uint16_t  RESERVED3;\r
+  __IO uint16_t SR;\r
+  uint16_t  RESERVED4;\r
+  __IO uint16_t EGR;\r
+  uint16_t  RESERVED5;\r
+  __IO uint16_t CCMR1;\r
+  uint16_t  RESERVED6;\r
+  __IO uint16_t CCMR2;\r
+  uint16_t  RESERVED7;\r
+  __IO uint16_t CCER;\r
+  uint16_t  RESERVED8;\r
+  __IO uint16_t CNT;\r
+  uint16_t  RESERVED9;\r
+  __IO uint16_t PSC;\r
+  uint16_t  RESERVED10;\r
+  __IO uint16_t ARR;\r
+  uint16_t  RESERVED11;\r
+  uint32_t  RESERVED12;\r
+  __IO uint16_t CCR1;\r
+  uint16_t  RESERVED13;\r
+  __IO uint16_t CCR2;\r
+  uint16_t  RESERVED14;\r
+  __IO uint16_t CCR3;\r
+  uint16_t  RESERVED15;\r
+  __IO uint16_t CCR4;\r
+  uint16_t  RESERVED16;\r
+  uint32_t  RESERVED17;\r
+  __IO uint16_t DCR;\r
+  uint16_t  RESERVED18;\r
+  __IO uint16_t DMAR;\r
+  uint16_t  RESERVED19;\r
+  __IO uint16_t OR;\r
+  uint16_t  RESERVED20;\r
+} TIM_TypeDef;\r
+\r
+/** \r
+  * @brief Universal Synchronous Asynchronous Receiver Transmitter\r
+  */\r
+ \r
+typedef struct\r
+{\r
+  __IO uint16_t SR;\r
+  uint16_t  RESERVED0;\r
+  __IO uint16_t DR;\r
+  uint16_t  RESERVED1;\r
+  __IO uint16_t BRR;\r
+  uint16_t  RESERVED2;\r
+  __IO uint16_t CR1;\r
+  uint16_t  RESERVED3;\r
+  __IO uint16_t CR2;\r
+  uint16_t  RESERVED4;\r
+  __IO uint16_t CR3;\r
+  uint16_t  RESERVED5;\r
+  __IO uint16_t GTPR;\r
+  uint16_t  RESERVED6;\r
+} USART_TypeDef;\r
+\r
+/** \r
+  * @brief Window WATCHDOG\r
+  */\r
+\r
+typedef struct\r
+{\r
+  __IO uint32_t CR;\r
+  __IO uint32_t CFR;\r
+  __IO uint32_t SR;\r
+} WWDG_TypeDef;\r
+\r
+/**\r
+  * @}\r
+  */\r
+  \r
+/** @addtogroup Peripheral_memory_map\r
+  * @{\r
+  */\r
+\r
+#define PERIPH_BB_BASE        ((uint32_t)0x42000000) /*!< Peripheral base address in the alias region */\r
+#define SRAM_BB_BASE          ((uint32_t)0x22000000) /*!< SRAM base address in the alias region */\r
+\r
+#define SRAM_BASE             ((uint32_t)0x20000000) /*!< SRAM base address in the bit-band region */\r
+#define PERIPH_BASE           ((uint32_t)0x40000000) /*!< Peripheral base address in the bit-band region */\r
+\r
+/*!< Peripheral memory map */\r
+#define APB1PERIPH_BASE       PERIPH_BASE\r
+#define APB2PERIPH_BASE       (PERIPH_BASE + 0x10000)\r
+#define AHBPERIPH_BASE        (PERIPH_BASE + 0x20000)\r
+\r
+#define TIM2_BASE             (APB1PERIPH_BASE + 0x0000)\r
+#define TIM3_BASE             (APB1PERIPH_BASE + 0x0400)\r
+#define TIM4_BASE             (APB1PERIPH_BASE + 0x0800)\r
+#define TIM6_BASE             (APB1PERIPH_BASE + 0x1000)\r
+#define TIM7_BASE             (APB1PERIPH_BASE + 0x1400)\r
+#define LCD_BASE              (APB1PERIPH_BASE + 0x2400)\r
+#define RTC_BASE              (APB1PERIPH_BASE + 0x2800)\r
+#define WWDG_BASE             (APB1PERIPH_BASE + 0x2C00)\r
+#define IWDG_BASE             (APB1PERIPH_BASE + 0x3000)\r
+#define SPI2_BASE             (APB1PERIPH_BASE + 0x3800)\r
+#define USART2_BASE           (APB1PERIPH_BASE + 0x4400)\r
+#define USART3_BASE           (APB1PERIPH_BASE + 0x4800)\r
+#define I2C1_BASE             (APB1PERIPH_BASE + 0x5400)\r
+#define I2C2_BASE             (APB1PERIPH_BASE + 0x5800)\r
+#define PWR_BASE              (APB1PERIPH_BASE + 0x7000)\r
+#define DAC_BASE              (APB1PERIPH_BASE + 0x7400)\r
+#define COMP_BASE             (APB1PERIPH_BASE + 0x7C00)\r
+#define RI_BASE               (APB1PERIPH_BASE + 0x7C04)\r
+\r
+#define SYSCFG_BASE           (APB2PERIPH_BASE + 0x0000)\r
+#define EXTI_BASE             (APB2PERIPH_BASE + 0x0400)\r
+#define TIM9_BASE             (APB2PERIPH_BASE + 0x0800)\r
+#define TIM10_BASE            (APB2PERIPH_BASE + 0x0C00)\r
+#define TIM11_BASE            (APB2PERIPH_BASE + 0x1000)\r
+#define ADC1_BASE             (APB2PERIPH_BASE + 0x2400)\r
+#define ADC_BASE              (APB2PERIPH_BASE + 0x2700)\r
+#define SPI1_BASE             (APB2PERIPH_BASE + 0x3000)\r
+#define USART1_BASE           (APB2PERIPH_BASE + 0x3800)\r
+\r
+#define GPIOA_BASE            (AHBPERIPH_BASE + 0x0000)\r
+#define GPIOB_BASE            (AHBPERIPH_BASE + 0x0400)\r
+#define GPIOC_BASE            (AHBPERIPH_BASE + 0x0800)\r
+#define GPIOD_BASE            (AHBPERIPH_BASE + 0x0C00)\r
+#define GPIOE_BASE            (AHBPERIPH_BASE + 0x1000)\r
+#define GPIOH_BASE            (AHBPERIPH_BASE + 0x1400)\r
+#define CRC_BASE              (AHBPERIPH_BASE + 0x3000)\r
+#define RCC_BASE              (AHBPERIPH_BASE + 0x3800)\r
+\r
+\r
+#define FLASH_R_BASE          (AHBPERIPH_BASE + 0x3C00) /*!< FLASH registers base address */\r
+#define OB_BASE               ((uint32_t)0x1FF80000)    /*!< FLASH Option Bytes base address */\r
+\r
+#define DMA1_BASE             (AHBPERIPH_BASE + 0x6000)\r
+#define DMA1_Channel1_BASE    (DMA1_BASE + 0x0008)\r
+#define DMA1_Channel2_BASE    (DMA1_BASE + 0x001C)\r
+#define DMA1_Channel3_BASE    (DMA1_BASE + 0x0030)\r
+#define DMA1_Channel4_BASE    (DMA1_BASE + 0x0044)\r
+#define DMA1_Channel5_BASE    (DMA1_BASE + 0x0058)\r
+#define DMA1_Channel6_BASE    (DMA1_BASE + 0x006C)\r
+#define DMA1_Channel7_BASE    (DMA1_BASE + 0x0080)\r
+\r
+\r
+#define DBGMCU_BASE           ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */\r
+\r
+/**\r
+  * @}\r
+  */\r
+  \r
+/** @addtogroup Peripheral_declaration\r
+  * @{\r
+  */  \r
+\r
+#define TIM2                ((TIM_TypeDef *) TIM2_BASE)\r
+#define TIM3                ((TIM_TypeDef *) TIM3_BASE)\r
+#define TIM4                ((TIM_TypeDef *) TIM4_BASE)\r
+#define TIM6                ((TIM_TypeDef *) TIM6_BASE)\r
+#define TIM7                ((TIM_TypeDef *) TIM7_BASE)\r
+#define LCD                 ((LCD_TypeDef *) LCD_BASE)\r
+#define RTC                 ((RTC_TypeDef *) RTC_BASE)\r
+#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)\r
+#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)\r
+#define SPI2                ((SPI_TypeDef *) SPI2_BASE)\r
+#define USART2              ((USART_TypeDef *) USART2_BASE)\r
+#define USART3              ((USART_TypeDef *) USART3_BASE)\r
+#define I2C1                ((I2C_TypeDef *) I2C1_BASE)\r
+#define I2C2                ((I2C_TypeDef *) I2C2_BASE)\r
+#define PWR                 ((PWR_TypeDef *) PWR_BASE)\r
+#define DAC                 ((DAC_TypeDef *) DAC_BASE)\r
+#define COMP                ((COMP_TypeDef *) COMP_BASE)\r
+#define RI                  ((RI_TypeDef *) RI_BASE)\r
+#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)\r
+#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)\r
+\r
+#define ADC1                ((ADC_TypeDef *) ADC1_BASE)\r
+#define ADC                 ((ADC_Common_TypeDef *) ADC_BASE)\r
+#define TIM9                ((TIM_TypeDef *) TIM9_BASE)\r
+#define TIM10               ((TIM_TypeDef *) TIM10_BASE)\r
+#define TIM11               ((TIM_TypeDef *) TIM11_BASE)\r
+#define SPI1                ((SPI_TypeDef *) SPI1_BASE)\r
+#define USART1              ((USART_TypeDef *) USART1_BASE)\r
+#define DMA1                ((DMA_TypeDef *) DMA1_BASE)\r
+#define DMA1_Channel1       ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)\r
+#define DMA1_Channel2       ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)\r
+#define DMA1_Channel3       ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)\r
+#define DMA1_Channel4       ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)\r
+#define DMA1_Channel5       ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)\r
+#define DMA1_Channel6       ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)\r
+#define DMA1_Channel7       ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)\r
+#define RCC                 ((RCC_TypeDef *) RCC_BASE)\r
+#define CRC                 ((CRC_TypeDef *) CRC_BASE)\r
+\r
+#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)\r
+#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)\r
+#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)\r
+#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)\r
+#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)\r
+#define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)\r
+\r
+#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)\r
+#define OB                  ((OB_TypeDef *) OB_BASE) \r
+\r
+#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @addtogroup Exported_constants\r
+  * @{\r
+  */\r
+  \r
+  /** @addtogroup Peripheral_Registers_Bits_Definition\r
+  * @{\r
+  */\r
+    \r
+/******************************************************************************/\r
+/*                         Peripheral Registers_Bits_Definition               */\r
+/******************************************************************************/\r
+/******************************************************************************/\r
+/*                                                                            */\r
+/*                        Analog to Digital Converter                         */\r
+/*                                                                            */\r
+/******************************************************************************/\r
+\r
+/********************  Bit definition for ADC_SR register  ********************/\r
+#define  ADC_SR_AWD                          ((uint32_t)0x00000001)        /*!< Analog watchdog flag */\r
+#define  ADC_SR_EOC                          ((uint32_t)0x00000002)        /*!< End of conversion */\r
+#define  ADC_SR_JEOC                         ((uint32_t)0x00000004)        /*!< Injected channel end of conversion */\r
+#define  ADC_SR_JSTRT                        ((uint32_t)0x00000008)        /*!< Injected channel Start flag */\r
+#define  ADC_SR_STRT                         ((uint32_t)0x00000010)        /*!< Regular channel Start flag */\r
+#define  ADC_SR_OVR                          ((uint32_t)0x00000020)        /*!< Overrun flag */\r
+#define  ADC_SR_ADONS                        ((uint32_t)0x00000040)        /*!< ADC ON status */\r
+#define  ADC_SR_RCNR                         ((uint32_t)0x00000100)        /*!< Regular channel not ready flag */\r
+#define  ADC_SR_JCNR                         ((uint32_t)0x00000200)        /*!< Injected channel not ready flag */\r
+\r
+/*******************  Bit definition for ADC_CR1 register  ********************/\r
+#define  ADC_CR1_AWDCH                       ((uint32_t)0x0000001F)        /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */\r
+#define  ADC_CR1_AWDCH_0                     ((uint32_t)0x00000001)        /*!< Bit 0 */\r
+#define  ADC_CR1_AWDCH_1                     ((uint32_t)0x00000002)        /*!< Bit 1 */\r
+#define  ADC_CR1_AWDCH_2                     ((uint32_t)0x00000004)        /*!< Bit 2 */\r
+#define  ADC_CR1_AWDCH_3                     ((uint32_t)0x00000008)        /*!< Bit 3 */\r
+#define  ADC_CR1_AWDCH_4                     ((uint32_t)0x00000010)        /*!< Bit 4 */\r
+\r
+#define  ADC_CR1_EOCIE                       ((uint32_t)0x00000020)        /*!< Interrupt enable for EOC */\r
+#define  ADC_CR1_AWDIE                       ((uint32_t)0x00000040)        /*!< Analog Watchdog interrupt enable */\r
+#define  ADC_CR1_JEOCIE                      ((uint32_t)0x00000080)        /*!< Interrupt enable for injected channels */\r
+#define  ADC_CR1_SCAN                        ((uint32_t)0x00000100)        /*!< Scan mode */\r
+#define  ADC_CR1_AWDSGL                      ((uint32_t)0x00000200)        /*!< Enable the watchdog on a single channel in scan mode */\r
+#define  ADC_CR1_JAUTO                       ((uint32_t)0x00000400)        /*!< Automatic injected group conversion */\r
+#define  ADC_CR1_DISCEN                      ((uint32_t)0x00000800)        /*!< Discontinuous mode on regular channels */\r
+#define  ADC_CR1_JDISCEN                     ((uint32_t)0x00001000)        /*!< Discontinuous mode on injected channels */\r
+\r
+#define  ADC_CR1_DISCNUM                     ((uint32_t)0x0000E000)        /*!< DISCNUM[2:0] bits (Discontinuous mode channel count) */\r
+#define  ADC_CR1_DISCNUM_0                   ((uint32_t)0x00002000)        /*!< Bit 0 */\r
+#define  ADC_CR1_DISCNUM_1                   ((uint32_t)0x00004000)        /*!< Bit 1 */\r
+#define  ADC_CR1_DISCNUM_2                   ((uint32_t)0x00008000)        /*!< Bit 2 */\r
+\r
+#define  ADC_CR1_PDD                         ((uint32_t)0x00010000)        /*!< Power Down during Delay phase */\r
+#define  ADC_CR1_PDI                         ((uint32_t)0x00020000)        /*!< Power Down during Idle phase */\r
+\r
+#define  ADC_CR1_JAWDEN                      ((uint32_t)0x00400000)        /*!< Analog watchdog enable on injected channels */\r
+#define  ADC_CR1_AWDEN                       ((uint32_t)0x00800000)        /*!< Analog watchdog enable on regular channels */\r
+\r
+#define  ADC_CR1_RES                         ((uint32_t)0x03000000)        /*!< RES[1:0] bits (Resolution) */\r
+#define  ADC_CR1_RES_0                       ((uint32_t)0x01000000)        /*!< Bit 0 */\r
+#define  ADC_CR1_RES_1                       ((uint32_t)0x02000000)        /*!< Bit 1 */\r
+\r
+#define  ADC_CR1_OVRIE                       ((uint32_t)0x04000000)        /*!< Overrun interrupt enable */\r
+  \r
+/*******************  Bit definition for ADC_CR2 register  ********************/\r
+#define  ADC_CR2_ADON                        ((uint32_t)0x00000001)        /*!< A/D Converter ON / OFF */\r
+#define  ADC_CR2_CONT                        ((uint32_t)0x00000002)        /*!< Continuous Conversion */\r
+\r
+#define  ADC_CR2_DELS                        ((uint32_t)0x00000070)        /*!< DELS[2:0] bits (Delay selection) */\r
+#define  ADC_CR2_DELS_0                      ((uint32_t)0x00000010)        /*!< Bit 0 */\r
+#define  ADC_CR2_DELS_1                      ((uint32_t)0x00000020)        /*!< Bit 1 */\r
+#define  ADC_CR2_DELS_2                      ((uint32_t)0x00000040)        /*!< Bit 2 */\r
+\r
+#define  ADC_CR2_DMA                         ((uint32_t)0x00000100)        /*!< Direct Memory access mode */\r
+#define  ADC_CR2_DDS                         ((uint32_t)0x00000200)        /*!< DMA disable selection (Single ADC) */\r
+#define  ADC_CR2_EOCS                        ((uint32_t)0x00000400)        /*!< End of conversion selection */\r
+#define  ADC_CR2_ALIGN                       ((uint32_t)0x00000800)        /*!< Data Alignment */\r
+\r
+#define  ADC_CR2_JEXTSEL                     ((uint32_t)0x000F0000)        /*!< JEXTSEL[3:0] bits (External event select for injected group) */\r
+#define  ADC_CR2_JEXTSEL_0                   ((uint32_t)0x00010000)        /*!< Bit 0 */\r
+#define  ADC_CR2_JEXTSEL_1                   ((uint32_t)0x00020000)        /*!< Bit 1 */\r
+#define  ADC_CR2_JEXTSEL_2                   ((uint32_t)0x00040000)        /*!< Bit 2 */\r
+#define  ADC_CR2_JEXTSEL_3                   ((uint32_t)0x00080000)        /*!< Bit 3 */\r
+\r
+#define  ADC_CR2_JEXTEN                      ((uint32_t)0x00300000)        /*!< JEXTEN[1:0] bits (External Trigger Conversion mode for injected channels) */\r
+#define  ADC_CR2_JEXTEN_0                    ((uint32_t)0x00100000)        /*!< Bit 0 */\r
+#define  ADC_CR2_JEXTEN_1                    ((uint32_t)0x00200000)        /*!< Bit 1 */\r
+\r
+#define  ADC_CR2_JSWSTART                    ((uint32_t)0x00400000)        /*!< Start Conversion of injected channels */\r
+\r
+#define  ADC_CR2_EXTSEL                      ((uint32_t)0x0F000000)        /*!< EXTSEL[3:0] bits (External Event Select for regular group) */\r
+#define  ADC_CR2_EXTSEL_0                    ((uint32_t)0x01000000)        /*!< Bit 0 */\r
+#define  ADC_CR2_EXTSEL_1                    ((uint32_t)0x02000000)        /*!< Bit 1 */\r
+#define  ADC_CR2_EXTSEL_2                    ((uint32_t)0x04000000)        /*!< Bit 2 */\r
+#define  ADC_CR2_EXTSEL_3                    ((uint32_t)0x08000000)        /*!< Bit 3 */\r
+\r
+#define  ADC_CR2_EXTEN                       ((uint32_t)0x30000000)        /*!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) */\r
+#define  ADC_CR2_EXTEN_0                     ((uint32_t)0x10000000)        /*!< Bit 0 */\r
+#define  ADC_CR2_EXTEN_1                     ((uint32_t)0x20000000)        /*!< Bit 1 */\r
+\r
+#define  ADC_CR2_SWSTART                     ((uint32_t)0x40000000)        /*!< Start Conversion of regular channels */\r
+\r
+/******************  Bit definition for ADC_SMPR1 register  *******************/\r
+#define  ADC_SMPR1_SMP20                     ((uint32_t)0x00000007)        /*!< SMP20[2:0] bits (Channel 20 Sample time selection) */\r
+#define  ADC_SMPR1_SMP20_0                   ((uint32_t)0x00000001)        /*!< Bit 0 */\r
+#define  ADC_SMPR1_SMP20_1                   ((uint32_t)0x00000002)        /*!< Bit 1 */\r
+#define  ADC_SMPR1_SMP20_2                   ((uint32_t)0x00000004)        /*!< Bit 2 */\r
+\r
+#define  ADC_SMPR1_SMP21                     ((uint32_t)0x00000038)        /*!< SMP21[2:0] bits (Channel 21 Sample time selection) */\r
+#define  ADC_SMPR1_SMP21_0                   ((uint32_t)0x00000008)        /*!< Bit 0 */\r
+#define  ADC_SMPR1_SMP21_1                   ((uint32_t)0x00000010)        /*!< Bit 1 */\r
+#define  ADC_SMPR1_SMP21_2                   ((uint32_t)0x00000020)        /*!< Bit 2 */\r
+\r
+#define  ADC_SMPR1_SMP22                     ((uint32_t)0x000001C0)        /*!< SMP22[2:0] bits (Channel 22 Sample time selection) */\r
+#define  ADC_SMPR1_SMP22_0                   ((uint32_t)0x00000040)        /*!< Bit 0 */\r
+#define  ADC_SMPR1_SMP22_1                   ((uint32_t)0x00000080)        /*!< Bit 1 */\r
+#define  ADC_SMPR1_SMP22_2                   ((uint32_t)0x00000100)        /*!< Bit 2 */\r
+\r
+#define  ADC_SMPR1_SMP23                     ((uint32_t)0x00000E00)        /*!< SMP23[2:0] bits (Channel 23 Sample time selection) */\r
+#define  ADC_SMPR1_SMP23_0                   ((uint32_t)0x00000200)        /*!< Bit 0 */\r
+#define  ADC_SMPR1_SMP23_1                   ((uint32_t)0x00000400)        /*!< Bit 1 */\r
+#define  ADC_SMPR1_SMP23_2                   ((uint32_t)0x00000800)        /*!< Bit 2 */\r
+\r
+#define  ADC_SMPR1_SMP24                     ((uint32_t)0x00007000)        /*!< SMP24[2:0] bits (Channel 24 Sample time selection) */\r
+#define  ADC_SMPR1_SMP24_0                   ((uint32_t)0x00001000)        /*!< Bit 0 */\r
+#define  ADC_SMPR1_SMP24_1                   ((uint32_t)0x00002000)        /*!< Bit 1 */\r
+#define  ADC_SMPR1_SMP24_2                   ((uint32_t)0x00004000)        /*!< Bit 2 */\r
+\r
+#define  ADC_SMPR1_SMP25                     ((uint32_t)0x00038000)        /*!< SMP25[2:0] bits (Channel 25 Sample time selection) */\r
+#define  ADC_SMPR1_SMP25_0                   ((uint32_t)0x00008000)        /*!< Bit 0 */\r
+#define  ADC_SMPR1_SMP25_1                   ((uint32_t)0x00010000)        /*!< Bit 1 */\r
+#define  ADC_SMPR1_SMP25_2                   ((uint32_t)0x00020000)        /*!< Bit 2 */\r
+\r
+/******************  Bit definition for ADC_SMPR2 register  *******************/\r
+#define  ADC_SMPR2_SMP10                     ((uint32_t)0x00000007)        /*!< SMP10[2:0] bits (Channel 10 Sample time selection) */\r
+#define  ADC_SMPR2_SMP10_0                   ((uint32_t)0x00000001)        /*!< Bit 0 */\r
+#define  ADC_SMPR2_SMP10_1                   ((uint32_t)0x00000002)        /*!< Bit 1 */\r
+#define  ADC_SMPR2_SMP10_2                   ((uint32_t)0x00000004)        /*!< Bit 2 */\r
+\r
+#define  ADC_SMPR2_SMP11                     ((uint32_t)0x00000038)        /*!< SMP11[2:0] bits (Channel 11 Sample time selection) */\r
+#define  ADC_SMPR2_SMP11_0                   ((uint32_t)0x00000008)        /*!< Bit 0 */\r
+#define  ADC_SMPR2_SMP11_1                   ((uint32_t)0x00000010)        /*!< Bit 1 */\r
+#define  ADC_SMPR2_SMP11_2                   ((uint32_t)0x00000020)        /*!< Bit 2 */\r
+\r
+#define  ADC_SMPR2_SMP12                     ((uint32_t)0x000001C0)        /*!< SMP12[2:0] bits (Channel 12 Sample time selection) */\r
+#define  ADC_SMPR2_SMP12_0                   ((uint32_t)0x00000040)        /*!< Bit 0 */\r
+#define  ADC_SMPR2_SMP12_1                   ((uint32_t)0x00000080)        /*!< Bit 1 */\r
+#define  ADC_SMPR2_SMP12_2                   ((uint32_t)0x00000100)        /*!< Bit 2 */\r
+\r
+#define  ADC_SMPR2_SMP13                     ((uint32_t)0x00000E00)        /*!< SMP13[2:0] bits (Channel 13 Sample time selection) */\r
+#define  ADC_SMPR2_SMP13_0                   ((uint32_t)0x00000200)        /*!< Bit 0 */\r
+#define  ADC_SMPR2_SMP13_1                   ((uint32_t)0x00000400)        /*!< Bit 1 */\r
+#define  ADC_SMPR2_SMP13_2                   ((uint32_t)0x00000800)        /*!< Bit 2 */\r
+\r
+#define  ADC_SMPR2_SMP14                     ((uint32_t)0x00007000)        /*!< SMP14[2:0] bits (Channel 14 Sample time selection) */\r
+#define  ADC_SMPR2_SMP14_0                   ((uint32_t)0x00001000)        /*!< Bit 0 */\r
+#define  ADC_SMPR2_SMP14_1                   ((uint32_t)0x00002000)        /*!< Bit 1 */\r
+#define  ADC_SMPR2_SMP14_2                   ((uint32_t)0x00004000)        /*!< Bit 2 */\r
+\r
+#define  ADC_SMPR2_SMP15                     ((uint32_t)0x00038000)        /*!< SMP15[2:0] bits (Channel 5 Sample time selection) */\r
+#define  ADC_SMPR2_SMP15_0                   ((uint32_t)0x00008000)        /*!< Bit 0 */\r
+#define  ADC_SMPR2_SMP15_1                   ((uint32_t)0x00010000)        /*!< Bit 1 */\r
+#define  ADC_SMPR2_SMP15_2                   ((uint32_t)0x00020000)        /*!< Bit 2 */\r
+\r
+#define  ADC_SMPR2_SMP16                     ((uint32_t)0x001C0000)        /*!< SMP16[2:0] bits (Channel 16 Sample time selection) */\r
+#define  ADC_SMPR2_SMP16_0                   ((uint32_t)0x00040000)        /*!< Bit 0 */\r
+#define  ADC_SMPR2_SMP16_1                   ((uint32_t)0x00080000)        /*!< Bit 1 */\r
+#define  ADC_SMPR2_SMP16_2                   ((uint32_t)0x00100000)        /*!< Bit 2 */\r
+\r
+#define  ADC_SMPR2_SMP17                     ((uint32_t)0x00E00000)        /*!< SMP17[2:0] bits (Channel 17 Sample time selection) */\r
+#define  ADC_SMPR2_SMP17_0                   ((uint32_t)0x00200000)        /*!< Bit 0 */\r
+#define  ADC_SMPR2_SMP17_1                   ((uint32_t)0x00400000)        /*!< Bit 1 */\r
+#define  ADC_SMPR2_SMP17_2                   ((uint32_t)0x00800000)        /*!< Bit 2 */\r
+\r
+#define  ADC_SMPR2_SMP18                     ((uint32_t)0x07000000)        /*!< SMP18[2:0] bits (Channel 18 Sample time selection) */\r
+#define  ADC_SMPR2_SMP18_0                   ((uint32_t)0x01000000)        /*!< Bit 0 */\r
+#define  ADC_SMPR2_SMP18_1                   ((uint32_t)0x02000000)        /*!< Bit 1 */\r
+#define  ADC_SMPR2_SMP18_2                   ((uint32_t)0x04000000)        /*!< Bit 2 */\r
+\r
+#define  ADC_SMPR2_SMP19                     ((uint32_t)0x38000000)        /*!< SMP19[2:0] bits (Channel 19 Sample time selection) */\r
+#define  ADC_SMPR2_SMP19_0                   ((uint32_t)0x08000000)        /*!< Bit 0 */\r
+#define  ADC_SMPR2_SMP19_1                   ((uint32_t)0x10000000)        /*!< Bit 1 */\r
+#define  ADC_SMPR2_SMP19_2                   ((uint32_t)0x20000000)        /*!< Bit 2 */\r
+\r
+/******************  Bit definition for ADC_SMPR3 register  *******************/\r
+#define  ADC_SMPR3_SMP0                      ((uint32_t)0x00000007)        /*!< SMP0[2:0] bits (Channel 0 Sample time selection) */\r
+#define  ADC_SMPR3_SMP0_0                    ((uint32_t)0x00000001)        /*!< Bit 0 */\r
+#define  ADC_SMPR3_SMP0_1                    ((uint32_t)0x00000002)        /*!< Bit 1 */\r
+#define  ADC_SMPR3_SMP0_2                    ((uint32_t)0x00000004)        /*!< Bit 2 */\r
+ \r
+#define  ADC_SMPR3_SMP1                      ((uint32_t)0x00000038)        /*!< SMP1[2:0] bits (Channel 1 Sample time selection) */\r
+#define  ADC_SMPR3_SMP1_0                    ((uint32_t)0x00000008)        /*!< Bit 0 */\r
+#define  ADC_SMPR3_SMP1_1                    ((uint32_t)0x00000010)        /*!< Bit 1 */\r
+#define  ADC_SMPR3_SMP1_2                    ((uint32_t)0x00000020)        /*!< Bit 2 */\r
+\r
+#define  ADC_SMPR3_SMP2                      ((uint32_t)0x000001C0)        /*!< SMP2[2:0] bits (Channel 2 Sample time selection) */\r
+#define  ADC_SMPR3_SMP2_0                    ((uint32_t)0x00000040)        /*!< Bit 0 */\r
+#define  ADC_SMPR3_SMP2_1                    ((uint32_t)0x00000080)        /*!< Bit 1 */\r
+#define  ADC_SMPR3_SMP2_2                    ((uint32_t)0x00000100)        /*!< Bit 2 */\r
+\r
+#define  ADC_SMPR3_SMP3                      ((uint32_t)0x00000E00)        /*!< SMP3[2:0] bits (Channel 3 Sample time selection) */\r
+#define  ADC_SMPR3_SMP3_0                    ((uint32_t)0x00000200)        /*!< Bit 0 */\r
+#define  ADC_SMPR3_SMP3_1                    ((uint32_t)0x00000400)        /*!< Bit 1 */\r
+#define  ADC_SMPR3_SMP3_2                    ((uint32_t)0x00000800)        /*!< Bit 2 */\r
+\r
+#define  ADC_SMPR3_SMP4                      ((uint32_t)0x00007000)        /*!< SMP4[2:0] bits (Channel 4 Sample time selection) */\r
+#define  ADC_SMPR3_SMP4_0                    ((uint32_t)0x00001000)        /*!< Bit 0 */\r
+#define  ADC_SMPR3_SMP4_1                    ((uint32_t)0x00002000)        /*!< Bit 1 */\r
+#define  ADC_SMPR3_SMP4_2                    ((uint32_t)0x00004000)        /*!< Bit 2 */\r
+\r
+#define  ADC_SMPR3_SMP5                      ((uint32_t)0x00038000)        /*!< SMP5[2:0] bits (Channel 5 Sample time selection) */\r
+#define  ADC_SMPR3_SMP5_0                    ((uint32_t)0x00008000)        /*!< Bit 0 */\r
+#define  ADC_SMPR3_SMP5_1                    ((uint32_t)0x00010000)        /*!< Bit 1 */\r
+#define  ADC_SMPR3_SMP5_2                    ((uint32_t)0x00020000)        /*!< Bit 2 */\r
+\r
+#define  ADC_SMPR3_SMP6                      ((uint32_t)0x001C0000)        /*!< SMP6[2:0] bits (Channel 6 Sample time selection) */\r
+#define  ADC_SMPR3_SMP6_0                    ((uint32_t)0x00040000)        /*!< Bit 0 */\r
+#define  ADC_SMPR3_SMP6_1                    ((uint32_t)0x00080000)        /*!< Bit 1 */\r
+#define  ADC_SMPR3_SMP6_2                    ((uint32_t)0x00100000)        /*!< Bit 2 */\r
+\r
+#define  ADC_SMPR3_SMP7                      ((uint32_t)0x00E00000)        /*!< SMP7[2:0] bits (Channel 7 Sample time selection) */\r
+#define  ADC_SMPR3_SMP7_0                    ((uint32_t)0x00200000)        /*!< Bit 0 */\r
+#define  ADC_SMPR3_SMP7_1                    ((uint32_t)0x00400000)        /*!< Bit 1 */\r
+#define  ADC_SMPR3_SMP7_2                    ((uint32_t)0x00800000)        /*!< Bit 2 */\r
+\r
+#define  ADC_SMPR3_SMP8                      ((uint32_t)0x07000000)        /*!< SMP8[2:0] bits (Channel 8 Sample time selection) */\r
+#define  ADC_SMPR3_SMP8_0                    ((uint32_t)0x01000000)        /*!< Bit 0 */\r
+#define  ADC_SMPR3_SMP8_1                    ((uint32_t)0x02000000)        /*!< Bit 1 */\r
+#define  ADC_SMPR3_SMP8_2                    ((uint32_t)0x04000000)        /*!< Bit 2 */\r
+\r
+#define  ADC_SMPR3_SMP9                      ((uint32_t)0x38000000)        /*!< SMP9[2:0] bits (Channel 9 Sample time selection) */\r
+#define  ADC_SMPR3_SMP9_0                    ((uint32_t)0x08000000)        /*!< Bit 0 */\r
+#define  ADC_SMPR3_SMP9_1                    ((uint32_t)0x10000000)        /*!< Bit 1 */\r
+#define  ADC_SMPR3_SMP9_2                    ((uint32_t)0x20000000)        /*!< Bit 2 */\r
+\r
+\r
+/******************  Bit definition for ADC_JOFR1 register  *******************/\r
+#define  ADC_JOFR1_JOFFSET1                  ((uint32_t)0x00000FFF)        /*!< Data offset for injected channel 1 */\r
+\r
+/******************  Bit definition for ADC_JOFR2 register  *******************/\r
+#define  ADC_JOFR2_JOFFSET2                  ((uint32_t)0x00000FFF)        /*!< Data offset for injected channel 2 */\r
+\r
+/******************  Bit definition for ADC_JOFR3 register  *******************/\r
+#define  ADC_JOFR3_JOFFSET3                  ((uint32_t)0x00000FFF)        /*!< Data offset for injected channel 3 */\r
+\r
+/******************  Bit definition for ADC_JOFR4 register  *******************/\r
+#define  ADC_JOFR4_JOFFSET4                  ((uint32_t)0x00000FFF)        /*!< Data offset for injected channel 4 */\r
+\r
+/*******************  Bit definition for ADC_HTR register  ********************/\r
+#define  ADC_HTR_HT                          ((uint32_t)0x00000FFF)        /*!< Analog watchdog high threshold */\r
+\r
+/*******************  Bit definition for ADC_LTR register  ********************/\r
+#define  ADC_LTR_LT                          ((uint32_t)0x00000FFF)         /*!< Analog watchdog low threshold */\r
+\r
+/*******************  Bit definition for ADC_SQR1 register  *******************/\r
+#define  ADC_SQR1_SQ25                       ((uint32_t)0x0000001F)        /*!< SQ25[4:0] bits (25th conversion in regular sequence) */\r
+#define  ADC_SQR1_SQ25_0                     ((uint32_t)0x00000001)        /*!< Bit 0 */\r
+#define  ADC_SQR1_SQ25_1                     ((uint32_t)0x00000002)        /*!< Bit 1 */\r
+#define  ADC_SQR1_SQ25_2                     ((uint32_t)0x00000004)        /*!< Bit 2 */\r
+#define  ADC_SQR1_SQ25_3                     ((uint32_t)0x00000008)        /*!< Bit 3 */\r
+#define  ADC_SQR1_SQ25_4                     ((uint32_t)0x00000010)        /*!< Bit 4 */\r
+\r
+#define  ADC_SQR1_SQ26                       ((uint32_t)0x000003E0)        /*!< SQ26[4:0] bits (26th conversion in regular sequence) */\r
+#define  ADC_SQR1_SQ26_0                     ((uint32_t)0x00000020)        /*!< Bit 0 */\r
+#define  ADC_SQR1_SQ26_1                     ((uint32_t)0x00000040)        /*!< Bit 1 */\r
+#define  ADC_SQR1_SQ26_2                     ((uint32_t)0x00000080)        /*!< Bit 2 */\r
+#define  ADC_SQR1_SQ26_3                     ((uint32_t)0x00000100)        /*!< Bit 3 */\r
+#define  ADC_SQR1_SQ26_4                     ((uint32_t)0x00000200)        /*!< Bit 4 */\r
+\r
+#define  ADC_SQR1_SQ27                       ((uint32_t)0x00007C00)        /*!< SQ27[4:0] bits (27th conversion in regular sequence) */\r
+#define  ADC_SQR1_SQ27_0                     ((uint32_t)0x00000400)        /*!< Bit 0 */\r
+#define  ADC_SQR1_SQ27_1                     ((uint32_t)0x00000800)        /*!< Bit 1 */\r
+#define  ADC_SQR1_SQ27_2                     ((uint32_t)0x00001000)        /*!< Bit 2 */\r
+#define  ADC_SQR1_SQ27_3                     ((uint32_t)0x00002000)        /*!< Bit 3 */\r
+#define  ADC_SQR1_SQ27_4                     ((uint32_t)0x00004000)        /*!< Bit 4 */\r
+\r
+#define  ADC_SQR1_L                          ((uint32_t)0x00F00000)        /*!< L[3:0] bits (Regular channel sequence length) */\r
+#define  ADC_SQR1_L_0                        ((uint32_t)0x00100000)        /*!< Bit 0 */\r
+#define  ADC_SQR1_L_1                        ((uint32_t)0x00200000)        /*!< Bit 1 */\r
+#define  ADC_SQR1_L_2                        ((uint32_t)0x00400000)        /*!< Bit 2 */\r
+#define  ADC_SQR1_L_3                        ((uint32_t)0x00800000)        /*!< Bit 3 */\r
+\r
+/*******************  Bit definition for ADC_SQR2 register  *******************/\r
+#define  ADC_SQR2_SQ19                       ((uint32_t)0x0000001F)        /*!< SQ19[4:0] bits (19th conversion in regular sequence) */\r
+#define  ADC_SQR2_SQ19_0                     ((uint32_t)0x00000001)        /*!< Bit 0 */\r
+#define  ADC_SQR2_SQ19_1                     ((uint32_t)0x00000002)        /*!< Bit 1 */\r
+#define  ADC_SQR2_SQ19_2                     ((uint32_t)0x00000004)        /*!< Bit 2 */\r
+#define  ADC_SQR2_SQ19_3                     ((uint32_t)0x00000008)        /*!< Bit 3 */\r
+#define  ADC_SQR2_SQ19_4                     ((uint32_t)0x00000010)        /*!< Bit 4 */\r
+\r
+#define  ADC_SQR2_SQ20                       ((uint32_t)0x000003E0)        /*!< SQ20[4:0] bits (20th conversion in regular sequence) */\r
+#define  ADC_SQR2_SQ20_0                     ((uint32_t)0x00000020)        /*!< Bit 0 */\r
+#define  ADC_SQR2_SQ20_1                     ((uint32_t)0x00000040)        /*!< Bit 1 */\r
+#define  ADC_SQR2_SQ20_2                     ((uint32_t)0x00000080)        /*!< Bit 2 */\r
+#define  ADC_SQR2_SQ20_3                     ((uint32_t)0x00000100)        /*!< Bit 3 */\r
+#define  ADC_SQR2_SQ20_4                     ((uint32_t)0x00000200)        /*!< Bit 4 */\r
+\r
+#define  ADC_SQR2_SQ21                       ((uint32_t)0x00007C00)        /*!< SQ21[4:0] bits (21th conversion in regular sequence) */\r
+#define  ADC_SQR2_SQ21_0                     ((uint32_t)0x00000400)        /*!< Bit 0 */\r
+#define  ADC_SQR2_SQ21_1                     ((uint32_t)0x00000800)        /*!< Bit 1 */\r
+#define  ADC_SQR2_SQ21_2                     ((uint32_t)0x00001000)        /*!< Bit 2 */\r
+#define  ADC_SQR2_SQ21_3                     ((uint32_t)0x00002000)        /*!< Bit 3 */\r
+#define  ADC_SQR2_SQ21_4                     ((uint32_t)0x00004000)        /*!< Bit 4 */\r
+\r
+#define  ADC_SQR2_SQ22                       ((uint32_t)0x000F8000)        /*!< SQ22[4:0] bits (22th conversion in regular sequence) */\r
+#define  ADC_SQR2_SQ22_0                     ((uint32_t)0x00008000)        /*!< Bit 0 */\r
+#define  ADC_SQR2_SQ22_1                     ((uint32_t)0x00010000)        /*!< Bit 1 */\r
+#define  ADC_SQR2_SQ22_2                     ((uint32_t)0x00020000)        /*!< Bit 2 */\r
+#define  ADC_SQR2_SQ22_3                     ((uint32_t)0x00040000)        /*!< Bit 3 */\r
+#define  ADC_SQR2_SQ22_4                     ((uint32_t)0x00080000)        /*!< Bit 4 */\r
+\r
+#define  ADC_SQR2_SQ23                       ((uint32_t)0x01F00000)        /*!< SQ23[4:0] bits (23th conversion in regular sequence) */\r
+#define  ADC_SQR2_SQ23_0                     ((uint32_t)0x00100000)        /*!< Bit 0 */\r
+#define  ADC_SQR2_SQ23_1                     ((uint32_t)0x00200000)        /*!< Bit 1 */\r
+#define  ADC_SQR2_SQ23_2                     ((uint32_t)0x00400000)        /*!< Bit 2 */\r
+#define  ADC_SQR2_SQ23_3                     ((uint32_t)0x00800000)        /*!< Bit 3 */\r
+#define  ADC_SQR2_SQ23_4                     ((uint32_t)0x01000000)        /*!< Bit 4 */\r
+\r
+#define  ADC_SQR2_SQ24                       ((uint32_t)0x3E000000)        /*!< SQ24[4:0] bits (24th conversion in regular sequence) */\r
+#define  ADC_SQR2_SQ24_0                     ((uint32_t)0x02000000)        /*!< Bit 0 */\r
+#define  ADC_SQR2_SQ24_1                     ((uint32_t)0x04000000)        /*!< Bit 1 */\r
+#define  ADC_SQR2_SQ24_2                     ((uint32_t)0x08000000)        /*!< Bit 2 */\r
+#define  ADC_SQR2_SQ24_3                     ((uint32_t)0x10000000)        /*!< Bit 3 */\r
+#define  ADC_SQR2_SQ24_4                     ((uint32_t)0x20000000)        /*!< Bit 4 */\r
+\r
+/*******************  Bit definition for ADC_SQR3 register  *******************/\r
+#define  ADC_SQR3_SQ13                       ((uint32_t)0x0000001F)        /*!< SQ13[4:0] bits (13th conversion in regular sequence) */\r
+#define  ADC_SQR3_SQ13_0                     ((uint32_t)0x00000001)        /*!< Bit 0 */\r
+#define  ADC_SQR3_SQ13_1                     ((uint32_t)0x00000002)        /*!< Bit 1 */\r
+#define  ADC_SQR3_SQ13_2                     ((uint32_t)0x00000004)        /*!< Bit 2 */\r
+#define  ADC_SQR3_SQ13_3                     ((uint32_t)0x00000008)        /*!< Bit 3 */\r
+#define  ADC_SQR3_SQ13_4                     ((uint32_t)0x00000010)        /*!< Bit 4 */\r
+\r
+#define  ADC_SQR3_SQ14                       ((uint32_t)0x000003E0)        /*!< SQ14[4:0] bits (14th conversion in regular sequence) */\r
+#define  ADC_SQR3_SQ14_0                     ((uint32_t)0x00000020)        /*!< Bit 0 */\r
+#define  ADC_SQR3_SQ14_1                     ((uint32_t)0x00000040)        /*!< Bit 1 */\r
+#define  ADC_SQR3_SQ14_2                     ((uint32_t)0x00000080)        /*!< Bit 2 */\r
+#define  ADC_SQR3_SQ14_3                     ((uint32_t)0x00000100)        /*!< Bit 3 */\r
+#define  ADC_SQR3_SQ14_4                     ((uint32_t)0x00000200)        /*!< Bit 4 */\r
+\r
+#define  ADC_SQR3_SQ15                       ((uint32_t)0x00007C00)        /*!< SQ15[4:0] bits (15th conversion in regular sequence) */\r
+#define  ADC_SQR3_SQ15_0                     ((uint32_t)0x00000400)        /*!< Bit 0 */\r
+#define  ADC_SQR3_SQ15_1                     ((uint32_t)0x00000800)        /*!< Bit 1 */\r
+#define  ADC_SQR3_SQ15_2                     ((uint32_t)0x00001000)        /*!< Bit 2 */\r
+#define  ADC_SQR3_SQ15_3                     ((uint32_t)0x00002000)        /*!< Bit 3 */\r
+#define  ADC_SQR3_SQ15_4                     ((uint32_t)0x00004000)        /*!< Bit 4 */\r
+\r
+#define  ADC_SQR3_SQ16                       ((uint32_t)0x000F8000)        /*!< SQ16[4:0] bits (16th conversion in regular sequence) */\r
+#define  ADC_SQR3_SQ16_0                     ((uint32_t)0x00008000)        /*!< Bit 0 */\r
+#define  ADC_SQR3_SQ16_1                     ((uint32_t)0x00010000)        /*!< Bit 1 */\r
+#define  ADC_SQR3_SQ16_2                     ((uint32_t)0x00020000)        /*!< Bit 2 */\r
+#define  ADC_SQR3_SQ16_3                     ((uint32_t)0x00040000)        /*!< Bit 3 */\r
+#define  ADC_SQR3_SQ16_4                     ((uint32_t)0x00080000)        /*!< Bit 4 */\r
+\r
+#define  ADC_SQR3_SQ17                       ((uint32_t)0x01F00000)        /*!< SQ17[4:0] bits (17th conversion in regular sequence) */\r
+#define  ADC_SQR3_SQ17_0                     ((uint32_t)0x00100000)        /*!< Bit 0 */\r
+#define  ADC_SQR3_SQ17_1                     ((uint32_t)0x00200000)        /*!< Bit 1 */\r
+#define  ADC_SQR3_SQ17_2                     ((uint32_t)0x00400000)        /*!< Bit 2 */\r
+#define  ADC_SQR3_SQ17_3                     ((uint32_t)0x00800000)        /*!< Bit 3 */\r
+#define  ADC_SQR3_SQ17_4                     ((uint32_t)0x01000000)        /*!< Bit 4 */\r
+\r
+#define  ADC_SQR3_SQ18                       ((uint32_t)0x3E000000)        /*!< SQ18[4:0] bits (18th conversion in regular sequence) */\r
+#define  ADC_SQR3_SQ18_0                     ((uint32_t)0x02000000)        /*!< Bit 0 */\r
+#define  ADC_SQR3_SQ18_1                     ((uint32_t)0x04000000)        /*!< Bit 1 */\r
+#define  ADC_SQR3_SQ18_2                     ((uint32_t)0x08000000)        /*!< Bit 2 */\r
+#define  ADC_SQR3_SQ18_3                     ((uint32_t)0x10000000)        /*!< Bit 3 */\r
+#define  ADC_SQR3_SQ18_4                     ((uint32_t)0x20000000)        /*!< Bit 4 */\r
+\r
+/*******************  Bit definition for ADC_SQR4 register  *******************/\r
+#define  ADC_SQR4_SQ7                        ((uint32_t)0x0000001F)        /*!< SQ7[4:0] bits (7th conversion in regular sequence) */\r
+#define  ADC_SQR4_SQ7_0                      ((uint32_t)0x00000001)        /*!< Bit 0 */\r
+#define  ADC_SQR4_SQ7_1                      ((uint32_t)0x00000002)        /*!< Bit 1 */\r
+#define  ADC_SQR4_SQ7_2                      ((uint32_t)0x00000004)        /*!< Bit 2 */\r
+#define  ADC_SQR4_SQ7_3                      ((uint32_t)0x00000008)        /*!< Bit 3 */\r
+#define  ADC_SQR4_SQ7_4                      ((uint32_t)0x00000010)        /*!< Bit 4 */\r
+\r
+#define  ADC_SQR4_SQ8                        ((uint32_t)0x000003E0)        /*!< SQ8[4:0] bits (8th conversion in regular sequence) */\r
+#define  ADC_SQR4_SQ8_0                      ((uint32_t)0x00000020)        /*!< Bit 0 */\r
+#define  ADC_SQR4_SQ8_1                      ((uint32_t)0x00000040)        /*!< Bit 1 */\r
+#define  ADC_SQR4_SQ8_2                      ((uint32_t)0x00000080)        /*!< Bit 2 */\r
+#define  ADC_SQR4_SQ8_3                      ((uint32_t)0x00000100)        /*!< Bit 3 */\r
+#define  ADC_SQR4_SQ8_4                      ((uint32_t)0x00000200)        /*!< Bit 4 */\r
+\r
+#define  ADC_SQR4_SQ9                        ((uint32_t)0x00007C00)        /*!< SQ9[4:0] bits (9th conversion in regular sequence) */\r
+#define  ADC_SQR4_SQ9_0                      ((uint32_t)0x00000400)        /*!< Bit 0 */\r
+#define  ADC_SQR4_SQ9_1                      ((uint32_t)0x00000800)        /*!< Bit 1 */\r
+#define  ADC_SQR4_SQ9_2                      ((uint32_t)0x00001000)        /*!< Bit 2 */\r
+#define  ADC_SQR4_SQ9_3                      ((uint32_t)0x00002000)        /*!< Bit 3 */\r
+#define  ADC_SQR4_SQ9_4                      ((uint32_t)0x00004000)        /*!< Bit 4 */\r
+\r
+#define  ADC_SQR4_SQ10                        ((uint32_t)0x000F8000)        /*!< SQ10[4:0] bits (10th conversion in regular sequence) */\r
+#define  ADC_SQR4_SQ10_0                      ((uint32_t)0x00008000)        /*!< Bit 0 */\r
+#define  ADC_SQR4_SQ10_1                      ((uint32_t)0x00010000)        /*!< Bit 1 */\r
+#define  ADC_SQR4_SQ10_2                      ((uint32_t)0x00020000)        /*!< Bit 2 */\r
+#define  ADC_SQR4_SQ10_3                      ((uint32_t)0x00040000)        /*!< Bit 3 */\r
+#define  ADC_SQR4_SQ10_4                      ((uint32_t)0x00080000)        /*!< Bit 4 */\r
+\r
+#define  ADC_SQR4_SQ11                        ((uint32_t)0x01F00000)        /*!< SQ11[4:0] bits (11th conversion in regular sequence) */\r
+#define  ADC_SQR4_SQ11_0                      ((uint32_t)0x00100000)        /*!< Bit 0 */\r
+#define  ADC_SQR4_SQ11_1                      ((uint32_t)0x00200000)        /*!< Bit 1 */\r
+#define  ADC_SQR4_SQ11_2                      ((uint32_t)0x00400000)        /*!< Bit 2 */\r
+#define  ADC_SQR4_SQ11_3                      ((uint32_t)0x00800000)        /*!< Bit 3 */\r
+#define  ADC_SQR4_SQ11_4                      ((uint32_t)0x01000000)        /*!< Bit 4 */\r
+\r
+#define  ADC_SQR4_SQ12                        ((uint32_t)0x3E000000)        /*!< SQ12[4:0] bits (12th conversion in regular sequence) */\r
+#define  ADC_SQR4_SQ12_0                      ((uint32_t)0x02000000)        /*!< Bit 0 */\r
+#define  ADC_SQR4_SQ12_1                      ((uint32_t)0x04000000)        /*!< Bit 1 */\r
+#define  ADC_SQR4_SQ12_2                      ((uint32_t)0x08000000)        /*!< Bit 2 */\r
+#define  ADC_SQR4_SQ12_3                      ((uint32_t)0x10000000)        /*!< Bit 3 */\r
+#define  ADC_SQR4_SQ12_4                      ((uint32_t)0x20000000)        /*!< Bit 4 */\r
+\r
+/*******************  Bit definition for ADC_SQR5 register  *******************/\r
+#define  ADC_SQR5_SQ1                        ((uint32_t)0x0000001F)        /*!< SQ1[4:0] bits (1st conversion in regular sequence) */\r
+#define  ADC_SQR5_SQ1_0                      ((uint32_t)0x00000001)        /*!< Bit 0 */\r
+#define  ADC_SQR5_SQ1_1                      ((uint32_t)0x00000002)        /*!< Bit 1 */\r
+#define  ADC_SQR5_SQ1_2                      ((uint32_t)0x00000004)        /*!< Bit 2 */\r
+#define  ADC_SQR5_SQ1_3                      ((uint32_t)0x00000008)        /*!< Bit 3 */\r
+#define  ADC_SQR5_SQ1_4                      ((uint32_t)0x00000010)        /*!< Bit 4 */\r
+\r
+#define  ADC_SQR5_SQ2                        ((uint32_t)0x000003E0)        /*!< SQ2[4:0] bits (2nd conversion in regular sequence) */\r
+#define  ADC_SQR5_SQ2_0                      ((uint32_t)0x00000020)        /*!< Bit 0 */\r
+#define  ADC_SQR5_SQ2_1                      ((uint32_t)0x00000040)        /*!< Bit 1 */\r
+#define  ADC_SQR5_SQ2_2                      ((uint32_t)0x00000080)        /*!< Bit 2 */\r
+#define  ADC_SQR5_SQ2_3                      ((uint32_t)0x00000100)        /*!< Bit 3 */\r
+#define  ADC_SQR5_SQ2_4                      ((uint32_t)0x00000200)        /*!< Bit 4 */\r
+\r
+#define  ADC_SQR5_SQ3                        ((uint32_t)0x00007C00)        /*!< SQ3[4:0] bits (3rd conversion in regular sequence) */\r
+#define  ADC_SQR5_SQ3_0                      ((uint32_t)0x00000400)        /*!< Bit 0 */\r
+#define  ADC_SQR5_SQ3_1                      ((uint32_t)0x00000800)        /*!< Bit 1 */\r
+#define  ADC_SQR5_SQ3_2                      ((uint32_t)0x00001000)        /*!< Bit 2 */\r
+#define  ADC_SQR5_SQ3_3                      ((uint32_t)0x00002000)        /*!< Bit 3 */\r
+#define  ADC_SQR5_SQ3_4                      ((uint32_t)0x00004000)        /*!< Bit 4 */\r
+\r
+#define  ADC_SQR5_SQ4                        ((uint32_t)0x000F8000)        /*!< SQ4[4:0] bits (4th conversion in regular sequence) */\r
+#define  ADC_SQR5_SQ4_0                      ((uint32_t)0x00008000)        /*!< Bit 0 */\r
+#define  ADC_SQR5_SQ4_1                      ((uint32_t)0x00010000)        /*!< Bit 1 */\r
+#define  ADC_SQR5_SQ4_2                      ((uint32_t)0x00020000)        /*!< Bit 2 */\r
+#define  ADC_SQR5_SQ4_3                      ((uint32_t)0x00040000)        /*!< Bit 3 */\r
+#define  ADC_SQR5_SQ4_4                      ((uint32_t)0x00080000)        /*!< Bit 4 */\r
+\r
+#define  ADC_SQR5_SQ5                        ((uint32_t)0x01F00000)        /*!< SQ5[4:0] bits (5th conversion in regular sequence) */\r
+#define  ADC_SQR5_SQ5_0                      ((uint32_t)0x00100000)        /*!< Bit 0 */\r
+#define  ADC_SQR5_SQ5_1                      ((uint32_t)0x00200000)        /*!< Bit 1 */\r
+#define  ADC_SQR5_SQ5_2                      ((uint32_t)0x00400000)        /*!< Bit 2 */\r
+#define  ADC_SQR5_SQ5_3                      ((uint32_t)0x00800000)        /*!< Bit 3 */\r
+#define  ADC_SQR5_SQ5_4                      ((uint32_t)0x01000000)        /*!< Bit 4 */\r
+\r
+#define  ADC_SQR5_SQ6                        ((uint32_t)0x3E000000)        /*!< SQ6[4:0] bits (6th conversion in regular sequence) */\r
+#define  ADC_SQR5_SQ6_0                      ((uint32_t)0x02000000)        /*!< Bit 0 */\r
+#define  ADC_SQR5_SQ6_1                      ((uint32_t)0x04000000)        /*!< Bit 1 */\r
+#define  ADC_SQR5_SQ6_2                      ((uint32_t)0x08000000)        /*!< Bit 2 */\r
+#define  ADC_SQR5_SQ6_3                      ((uint32_t)0x10000000)        /*!< Bit 3 */\r
+#define  ADC_SQR5_SQ6_4                      ((uint32_t)0x20000000)        /*!< Bit 4 */\r
+\r
+\r
+/*******************  Bit definition for ADC_JSQR register  *******************/\r
+#define  ADC_JSQR_JSQ1                       ((uint32_t)0x0000001F)        /*!< JSQ1[4:0] bits (1st conversion in injected sequence) */  \r
+#define  ADC_JSQR_JSQ1_0                     ((uint32_t)0x00000001)        /*!< Bit 0 */\r
+#define  ADC_JSQR_JSQ1_1                     ((uint32_t)0x00000002)        /*!< Bit 1 */\r
+#define  ADC_JSQR_JSQ1_2                     ((uint32_t)0x00000004)        /*!< Bit 2 */\r
+#define  ADC_JSQR_JSQ1_3                     ((uint32_t)0x00000008)        /*!< Bit 3 */\r
+#define  ADC_JSQR_JSQ1_4                     ((uint32_t)0x00000010)        /*!< Bit 4 */\r
+\r
+#define  ADC_JSQR_JSQ2                       ((uint32_t)0x000003E0)        /*!< JSQ2[4:0] bits (2nd conversion in injected sequence) */\r
+#define  ADC_JSQR_JSQ2_0                     ((uint32_t)0x00000020)        /*!< Bit 0 */\r
+#define  ADC_JSQR_JSQ2_1                     ((uint32_t)0x00000040)        /*!< Bit 1 */\r
+#define  ADC_JSQR_JSQ2_2                     ((uint32_t)0x00000080)        /*!< Bit 2 */\r
+#define  ADC_JSQR_JSQ2_3                     ((uint32_t)0x00000100)        /*!< Bit 3 */\r
+#define  ADC_JSQR_JSQ2_4                     ((uint32_t)0x00000200)        /*!< Bit 4 */\r
+\r
+#define  ADC_JSQR_JSQ3                       ((uint32_t)0x00007C00)        /*!< JSQ3[4:0] bits (3rd conversion in injected sequence) */\r
+#define  ADC_JSQR_JSQ3_0                     ((uint32_t)0x00000400)        /*!< Bit 0 */\r
+#define  ADC_JSQR_JSQ3_1                     ((uint32_t)0x00000800)        /*!< Bit 1 */\r
+#define  ADC_JSQR_JSQ3_2                     ((uint32_t)0x00001000)        /*!< Bit 2 */\r
+#define  ADC_JSQR_JSQ3_3                     ((uint32_t)0x00002000)        /*!< Bit 3 */\r
+#define  ADC_JSQR_JSQ3_4                     ((uint32_t)0x00004000)        /*!< Bit 4 */\r
+\r
+#define  ADC_JSQR_JSQ4                       ((uint32_t)0x000F8000)        /*!< JSQ4[4:0] bits (4th conversion in injected sequence) */\r
+#define  ADC_JSQR_JSQ4_0                     ((uint32_t)0x00008000)        /*!< Bit 0 */\r
+#define  ADC_JSQR_JSQ4_1                     ((uint32_t)0x00010000)        /*!< Bit 1 */\r
+#define  ADC_JSQR_JSQ4_2                     ((uint32_t)0x00020000)        /*!< Bit 2 */\r
+#define  ADC_JSQR_JSQ4_3                     ((uint32_t)0x00040000)        /*!< Bit 3 */\r
+#define  ADC_JSQR_JSQ4_4                     ((uint32_t)0x00080000)        /*!< Bit 4 */\r
+\r
+#define  ADC_JSQR_JL                         ((uint32_t)0x00300000)        /*!< JL[1:0] bits (Injected Sequence length) */\r
+#define  ADC_JSQR_JL_0                       ((uint32_t)0x00100000)        /*!< Bit 0 */\r
+#define  ADC_JSQR_JL_1                       ((uint32_t)0x00200000)        /*!< Bit 1 */\r
+\r
+/*******************  Bit definition for ADC_JDR1 register  *******************/\r
+#define  ADC_JDR1_JDATA                      ((uint32_t)0x0000FFFF)        /*!< Injected data */\r
+\r
+/*******************  Bit definition for ADC_JDR2 register  *******************/\r
+#define  ADC_JDR2_JDATA                      ((uint32_t)0x0000FFFF)        /*!< Injected data */\r
+\r
+/*******************  Bit definition for ADC_JDR3 register  *******************/\r
+#define  ADC_JDR3_JDATA                      ((uint32_t)0x0000FFFF)        /*!< Injected data */\r
+\r
+/*******************  Bit definition for ADC_JDR4 register  *******************/\r
+#define  ADC_JDR4_JDATA                      ((uint32_t)0x0000FFFF)        /*!< Injected data */\r
+\r
+/********************  Bit definition for ADC_DR register  ********************/\r
+#define  ADC_DR_DATA                         ((uint32_t)0x0000FFFF)        /*!< Regular data */\r
+\r
+\r
+/*******************  Bit definition for ADC_CSR register  ********************/\r
+#define  ADC_CSR_AWD1                        ((uint32_t)0x00000001)        /*!< ADC1 Analog watchdog flag */\r
+#define  ADC_CSR_EOC1                        ((uint32_t)0x00000002)        /*!< ADC1 End of conversion */\r
+#define  ADC_CSR_JEOC1                       ((uint32_t)0x00000004)        /*!< ADC1 Injected channel end of conversion */\r
+#define  ADC_CSR_JSTRT1                      ((uint32_t)0x00000008)        /*!< ADC1 Injected channel Start flag */\r
+#define  ADC_CSR_STRT1                       ((uint32_t)0x00000010)        /*!< ADC1 Regular channel Start flag */\r
+#define  ADC_CSR_OVR1                        ((uint32_t)0x00000020)        /*!< ADC1 overrun  flag */\r
+#define  ADC_CSR_ADONS1                      ((uint32_t)0x00000040)        /*!< ADON status of ADC1 */\r
+\r
+/*******************  Bit definition for ADC_CCR register  ********************/\r
+#define  ADC_CCR_ADCPRE                      ((uint32_t)0x00030000)        /*!< ADC prescaler*/\r
+#define  ADC_CCR_ADCPRE_0                    ((uint32_t)0x00010000)        /*!< Bit 0 */\r
+#define  ADC_CCR_ADCPRE_1                    ((uint32_t)0x00020000)        /*!< Bit 1 */ \r
+#define  ADC_CCR_TSVREFE                     ((uint32_t)0x00800000)        /*!< Temperature Sensor and VREFINT Enable */\r
+\r
+/******************************************************************************/\r
+/*                                                                            */\r
+/*                        Comparator                                          */\r
+/*                                                                            */\r
+/******************************************************************************/\r
+\r
+/******************  Bit definition for COMP_CSR register  ********************/\r
+#define  COMP_CSR_10KPU                      ((uint32_t)0x00000001)        /*!< 10K pull-up resistor */\r
+#define  COMP_CSR_400KPU                     ((uint32_t)0x00000002)        /*!< 400K pull-up resistor */\r
+#define  COMP_CSR_10KPD                      ((uint32_t)0x00000004)        /*!< 10K pull-down resistor */\r
+#define  COMP_CSR_400KPD                     ((uint32_t)0x00000008)        /*!< 400K pull-down resistor */\r
+\r
+#define  COMP_CSR_CMP1EN                     ((uint32_t)0x00000010)        /*!< Comparator 1 enable */\r
+#define  COMP_CSR_CMP1OUT                    ((uint32_t)0x00000080)        /*!< Comparator 1 output */\r
+\r
+#define  COMP_CSR_SPEED                      ((uint32_t)0x00001000)        /*!< Comparator 2 speed */\r
+#define  COMP_CSR_CMP2OUT                    ((uint32_t)0x00002000)        /*!< Comparator 2 ouput */\r
+\r
+#define  COMP_CSR_VREFOUTEN                  ((uint32_t)0x00010000)        /*!< Comparator Vref Enable */\r
+#define  COMP_CSR_WNDWE                      ((uint32_t)0x00020000)        /*!< Window mode enable */\r
+\r
+#define  COMP_CSR_INSEL                      ((uint32_t)0x001C0000)        /*!< INSEL[2:0] Inversion input Selection */\r
+#define  COMP_CSR_INSEL_0                    ((uint32_t)0x00040000)        /*!< Bit 0 */\r
+#define  COMP_CSR_INSEL_1                    ((uint32_t)0x00080000)        /*!< Bit 1 */\r
+#define  COMP_CSR_INSEL_2                    ((uint32_t)0x00100000)        /*!< Bit 2 */\r
+\r
+#define  COMP_CSR_OUTSEL                     ((uint32_t)0x00E00000)        /*!< OUTSEL[2:0] comparator 2 output redirection */\r
+#define  COMP_CSR_OUTSEL_0                   ((uint32_t)0x00200000)        /*!< Bit 0 */\r
+#define  COMP_CSR_OUTSEL_1                   ((uint32_t)0x00400000)        /*!< Bit 1 */\r
+#define  COMP_CSR_OUTSEL_2                   ((uint32_t)0x00800000)        /*!< Bit 2 */\r
+\r
+/******************************************************************************/\r
+/*                                                                            */\r
+/*                          CRC calculation unit                              */\r
+/*                                                                            */\r
+/******************************************************************************/\r
+\r
+/*******************  Bit definition for CRC_DR register  *********************/\r
+#define  CRC_DR_DR                           ((uint32_t)0xFFFFFFFF) /*!< Data register bits */\r
+\r
+/*******************  Bit definition for CRC_IDR register  ********************/\r
+#define  CRC_IDR_IDR                         ((uint8_t)0xFF)        /*!< General-purpose 8-bit data register bits */\r
+\r
+/********************  Bit definition for CRC_CR register  ********************/\r
+#define  CRC_CR_RESET                        ((uint32_t)0x00000001) /*!< RESET bit */\r
+\r
+/******************************************************************************/\r
+/*                                                                            */\r
+/*                      Digital to Analog Converter                           */\r
+/*                                                                            */\r
+/******************************************************************************/\r
+\r
+/********************  Bit definition for DAC_CR register  ********************/\r
+#define  DAC_CR_EN1                          ((uint32_t)0x00000001)        /*!<DAC channel1 enable */\r
+#define  DAC_CR_BOFF1                        ((uint32_t)0x00000002)        /*!<DAC channel1 output buffer disable */\r
+#define  DAC_CR_TEN1                         ((uint32_t)0x00000004)        /*!<DAC channel1 Trigger enable */\r
+\r
+#define  DAC_CR_TSEL1                        ((uint32_t)0x00000038)        /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */\r
+#define  DAC_CR_TSEL1_0                      ((uint32_t)0x00000008)        /*!<Bit 0 */\r
+#define  DAC_CR_TSEL1_1                      ((uint32_t)0x00000010)        /*!<Bit 1 */\r
+#define  DAC_CR_TSEL1_2                      ((uint32_t)0x00000020)        /*!<Bit 2 */\r
+\r
+#define  DAC_CR_WAVE1                        ((uint32_t)0x000000C0)        /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */\r
+#define  DAC_CR_WAVE1_0                      ((uint32_t)0x00000040)        /*!<Bit 0 */\r
+#define  DAC_CR_WAVE1_1                      ((uint32_t)0x00000080)        /*!<Bit 1 */\r
+\r
+#define  DAC_CR_MAMP1                        ((uint32_t)0x00000F00)        /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */\r
+#define  DAC_CR_MAMP1_0                      ((uint32_t)0x00000100)        /*!<Bit 0 */\r
+#define  DAC_CR_MAMP1_1                      ((uint32_t)0x00000200)        /*!<Bit 1 */\r
+#define  DAC_CR_MAMP1_2                      ((uint32_t)0x00000400)        /*!<Bit 2 */\r
+#define  DAC_CR_MAMP1_3                      ((uint32_t)0x00000800)        /*!<Bit 3 */\r
+\r
+#define  DAC_CR_DMAEN1                       ((uint32_t)0x00001000)        /*!<DAC channel1 DMA enable */\r
+#define  DAC_CR_EN2                          ((uint32_t)0x00010000)        /*!<DAC channel2 enable */\r
+#define  DAC_CR_BOFF2                        ((uint32_t)0x00020000)        /*!<DAC channel2 output buffer disable */\r
+#define  DAC_CR_TEN2                         ((uint32_t)0x00040000)        /*!<DAC channel2 Trigger enable */\r
+\r
+#define  DAC_CR_TSEL2                        ((uint32_t)0x00380000)        /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */\r
+#define  DAC_CR_TSEL2_0                      ((uint32_t)0x00080000)        /*!<Bit 0 */\r
+#define  DAC_CR_TSEL2_1                      ((uint32_t)0x00100000)        /*!<Bit 1 */\r
+#define  DAC_CR_TSEL2_2                      ((uint32_t)0x00200000)        /*!<Bit 2 */\r
+\r
+#define  DAC_CR_WAVE2                        ((uint32_t)0x00C00000)        /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */\r
+#define  DAC_CR_WAVE2_0                      ((uint32_t)0x00400000)        /*!<Bit 0 */\r
+#define  DAC_CR_WAVE2_1                      ((uint32_t)0x00800000)        /*!<Bit 1 */\r
+\r
+#define  DAC_CR_MAMP2                        ((uint32_t)0x0F000000)        /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */\r
+#define  DAC_CR_MAMP2_0                      ((uint32_t)0x01000000)        /*!<Bit 0 */\r
+#define  DAC_CR_MAMP2_1                      ((uint32_t)0x02000000)        /*!<Bit 1 */\r
+#define  DAC_CR_MAMP2_2                      ((uint32_t)0x04000000)        /*!<Bit 2 */\r
+#define  DAC_CR_MAMP2_3                      ((uint32_t)0x08000000)        /*!<Bit 3 */\r
+\r
+#define  DAC_CR_DMAEN2                       ((uint32_t)0x10000000)        /*!<DAC channel2 DMA enabled */\r
+\r
+/*****************  Bit definition for DAC_SWTRIGR register  ******************/\r
+#define  DAC_SWTRIGR_SWTRIG1                 ((uint8_t)0x01)               /*!<DAC channel1 software trigger */\r
+#define  DAC_SWTRIGR_SWTRIG2                 ((uint8_t)0x02)               /*!<DAC channel2 software trigger */\r
+\r
+/*****************  Bit definition for DAC_DHR12R1 register  ******************/\r
+#define  DAC_DHR12R1_DACC1DHR                ((uint16_t)0x0FFF)            /*!<DAC channel1 12-bit Right aligned data */\r
+\r
+/*****************  Bit definition for DAC_DHR12L1 register  ******************/\r
+#define  DAC_DHR12L1_DACC1DHR                ((uint16_t)0xFFF0)            /*!<DAC channel1 12-bit Left aligned data */\r
+\r
+/******************  Bit definition for DAC_DHR8R1 register  ******************/\r
+#define  DAC_DHR8R1_DACC1DHR                 ((uint8_t)0xFF)               /*!<DAC channel1 8-bit Right aligned data */\r
+\r
+/*****************  Bit definition for DAC_DHR12R2 register  ******************/\r
+#define  DAC_DHR12R2_DACC2DHR                ((uint16_t)0x0FFF)            /*!<DAC channel2 12-bit Right aligned data */\r
+\r
+/*****************  Bit definition for DAC_DHR12L2 register  ******************/\r
+#define  DAC_DHR12L2_DACC2DHR                ((uint16_t)0xFFF0)            /*!<DAC channel2 12-bit Left aligned data */\r
+\r
+/******************  Bit definition for DAC_DHR8R2 register  ******************/\r
+#define  DAC_DHR8R2_DACC2DHR                 ((uint8_t)0xFF)               /*!<DAC channel2 8-bit Right aligned data */\r
+\r
+/*****************  Bit definition for DAC_DHR12RD register  ******************/\r
+#define  DAC_DHR12RD_DACC1DHR                ((uint32_t)0x00000FFF)        /*!<DAC channel1 12-bit Right aligned data */\r
+#define  DAC_DHR12RD_DACC2DHR                ((uint32_t)0x0FFF0000)        /*!<DAC channel2 12-bit Right aligned data */\r
+\r
+/*****************  Bit definition for DAC_DHR12LD register  ******************/\r
+#define  DAC_DHR12LD_DACC1DHR                ((uint32_t)0x0000FFF0)        /*!<DAC channel1 12-bit Left aligned data */\r
+#define  DAC_DHR12LD_DACC2DHR                ((uint32_t)0xFFF00000)        /*!<DAC channel2 12-bit Left aligned data */\r
+\r
+/******************  Bit definition for DAC_DHR8RD register  ******************/\r
+#define  DAC_DHR8RD_DACC1DHR                 ((uint16_t)0x00FF)            /*!<DAC channel1 8-bit Right aligned data */\r
+#define  DAC_DHR8RD_DACC2DHR                 ((uint16_t)0xFF00)            /*!<DAC channel2 8-bit Right aligned data */\r
+\r
+/*******************  Bit definition for DAC_DOR1 register  *******************/\r
+#define  DAC_DOR1_DACC1DOR                   ((uint16_t)0x0FFF)            /*!<DAC channel1 data output */\r
+\r
+/*******************  Bit definition for DAC_DOR2 register  *******************/\r
+#define  DAC_DOR2_DACC2DOR                   ((uint16_t)0x0FFF)            /*!<DAC channel2 data output */\r
+\r
+/********************  Bit definition for DAC_SR register  ********************/\r
+#define  DAC_SR_DMAUDR1                      ((uint32_t)0x00002000)        /*!<DAC channel1 DMA underrun flag */\r
+#define  DAC_SR_DMAUDR2                      ((uint32_t)0x20000000)        /*!<DAC channel2 DMA underrun flag */\r
+\r
+/******************************************************************************/\r
+/*                                                                            */\r
+/*                                 Debug MCU                                  */\r
+/*                                                                            */\r
+/******************************************************************************/\r
+\r
+/****************  Bit definition for DBGMCU_IDCODE register  *****************/\r
+#define  DBGMCU_IDCODE_DEV_ID                ((uint32_t)0x00000FFF)        /*!< Device Identifier */\r
+\r
+#define  DBGMCU_IDCODE_REV_ID                ((uint32_t)0xFFFF0000)        /*!< REV_ID[15:0] bits (Revision Identifier) */\r
+#define  DBGMCU_IDCODE_REV_ID_0              ((uint32_t)0x00010000)        /*!< Bit 0 */\r
+#define  DBGMCU_IDCODE_REV_ID_1              ((uint32_t)0x00020000)        /*!< Bit 1 */\r
+#define  DBGMCU_IDCODE_REV_ID_2              ((uint32_t)0x00040000)        /*!< Bit 2 */\r
+#define  DBGMCU_IDCODE_REV_ID_3              ((uint32_t)0x00080000)        /*!< Bit 3 */\r
+#define  DBGMCU_IDCODE_REV_ID_4              ((uint32_t)0x00100000)        /*!< Bit 4 */\r
+#define  DBGMCU_IDCODE_REV_ID_5              ((uint32_t)0x00200000)        /*!< Bit 5 */\r
+#define  DBGMCU_IDCODE_REV_ID_6              ((uint32_t)0x00400000)        /*!< Bit 6 */\r
+#define  DBGMCU_IDCODE_REV_ID_7              ((uint32_t)0x00800000)        /*!< Bit 7 */\r
+#define  DBGMCU_IDCODE_REV_ID_8              ((uint32_t)0x01000000)        /*!< Bit 8 */\r
+#define  DBGMCU_IDCODE_REV_ID_9              ((uint32_t)0x02000000)        /*!< Bit 9 */\r
+#define  DBGMCU_IDCODE_REV_ID_10             ((uint32_t)0x04000000)        /*!< Bit 10 */\r
+#define  DBGMCU_IDCODE_REV_ID_11             ((uint32_t)0x08000000)        /*!< Bit 11 */\r
+#define  DBGMCU_IDCODE_REV_ID_12             ((uint32_t)0x10000000)        /*!< Bit 12 */\r
+#define  DBGMCU_IDCODE_REV_ID_13             ((uint32_t)0x20000000)        /*!< Bit 13 */\r
+#define  DBGMCU_IDCODE_REV_ID_14             ((uint32_t)0x40000000)        /*!< Bit 14 */\r
+#define  DBGMCU_IDCODE_REV_ID_15             ((uint32_t)0x80000000)        /*!< Bit 15 */\r
+\r
+/******************  Bit definition for DBGMCU_CR register  *******************/\r
+#define  DBGMCU_CR_DBG_SLEEP                 ((uint32_t)0x00000001)        /*!< Debug Sleep Mode */\r
+#define  DBGMCU_CR_DBG_STOP                  ((uint32_t)0x00000002)        /*!< Debug Stop Mode */\r
+#define  DBGMCU_CR_DBG_STANDBY               ((uint32_t)0x00000004)        /*!< Debug Standby mode */\r
+#define  DBGMCU_CR_TRACE_IOEN                ((uint32_t)0x00000020)        /*!< Trace Pin Assignment Control */\r
+\r
+#define  DBGMCU_CR_TRACE_MODE                ((uint32_t)0x000000C0)        /*!< TRACE_MODE[1:0] bits (Trace Pin Assignment Control) */\r
+#define  DBGMCU_CR_TRACE_MODE_0              ((uint32_t)0x00000040)        /*!< Bit 0 */\r
+#define  DBGMCU_CR_TRACE_MODE_1              ((uint32_t)0x00000080)        /*!< Bit 1 */\r
+\r
+/******************  Bit definition for DBGMCU_APB1_FZ register  **************/\r
+\r
+#define  DBGMCU_APB1_FZ_DBG_TIM2_STOP             ((uint32_t)0x00000001)        /*!< TIM2 counter stopped when core is halted */\r
+#define  DBGMCU_APB1_FZ_DBG_TIM3_STOP             ((uint32_t)0x00000002)        /*!< TIM3 counter stopped when core is halted */\r
+#define  DBGMCU_APB1_FZ_DBG_TIM4_STOP             ((uint32_t)0x00000004)        /*!< TIM4 counter stopped when core is halted */\r
+#define  DBGMCU_APB1_FZ_DBG_TIM6_STOP             ((uint32_t)0x00000010)        /*!< TIM6 counter stopped when core is halted */\r
+#define  DBGMCU_APB1_FZ_DBG_TIM7_STOP             ((uint32_t)0x00000020)        /*!< TIM7 counter stopped when core is halted */\r
+#define  DBGMCU_APB1_FZ_DBG_WWDG_STOP             ((uint32_t)0x00000800)        /*!< Debug Window Watchdog stopped when Core is halted */\r
+#define  DBGMCU_APB1_FZ_DBG_IWDG_STOP             ((uint32_t)0x00001000)        /*!< Debug Independent Watchdog stopped when Core is halted */\r
+#define  DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT    ((uint32_t)0x00200000)        /*!< SMBUS timeout mode stopped when Core is halted */\r
+#define  DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT    ((uint32_t)0x00400000)        /*!< SMBUS timeout mode stopped when Core is halted */\r
+\r
+/******************  Bit definition for DBGMCU_APB2_FZ register  **************/\r
+\r
+#define  DBGMCU_APB2_FZ_DBG_TIM9_STOP             ((uint32_t)0x00000004)        /*!< TIM9 counter stopped when core is halted */\r
+#define  DBGMCU_APB2_FZ_DBG_TIM10_STOP            ((uint32_t)0x00000008)        /*!< TIM10 counter stopped when core is halted */\r
+#define  DBGMCU_APB2_FZ_DBG_TIM11_STOP            ((uint32_t)0x00000010)        /*!< TIM11 counter stopped when core is halted */\r
+\r
+/******************************************************************************/\r
+/*                                                                            */\r
+/*                             DMA Controller                                 */\r
+/*                                                                            */\r
+/******************************************************************************/\r
+\r
+/*******************  Bit definition for DMA_ISR register  ********************/\r
+#define  DMA_ISR_GIF1                        ((uint32_t)0x00000001)        /*!< Channel 1 Global interrupt flag */\r
+#define  DMA_ISR_TCIF1                       ((uint32_t)0x00000002)        /*!< Channel 1 Transfer Complete flag */\r
+#define  DMA_ISR_HTIF1                       ((uint32_t)0x00000004)        /*!< Channel 1 Half Transfer flag */\r
+#define  DMA_ISR_TEIF1                       ((uint32_t)0x00000008)        /*!< Channel 1 Transfer Error flag */\r
+#define  DMA_ISR_GIF2                        ((uint32_t)0x00000010)        /*!< Channel 2 Global interrupt flag */\r
+#define  DMA_ISR_TCIF2                       ((uint32_t)0x00000020)        /*!< Channel 2 Transfer Complete flag */\r
+#define  DMA_ISR_HTIF2                       ((uint32_t)0x00000040)        /*!< Channel 2 Half Transfer flag */\r
+#define  DMA_ISR_TEIF2                       ((uint32_t)0x00000080)        /*!< Channel 2 Transfer Error flag */\r
+#define  DMA_ISR_GIF3                        ((uint32_t)0x00000100)        /*!< Channel 3 Global interrupt flag */\r
+#define  DMA_ISR_TCIF3                       ((uint32_t)0x00000200)        /*!< Channel 3 Transfer Complete flag */\r
+#define  DMA_ISR_HTIF3                       ((uint32_t)0x00000400)        /*!< Channel 3 Half Transfer flag */\r
+#define  DMA_ISR_TEIF3                       ((uint32_t)0x00000800)        /*!< Channel 3 Transfer Error flag */\r
+#define  DMA_ISR_GIF4                        ((uint32_t)0x00001000)        /*!< Channel 4 Global interrupt flag */\r
+#define  DMA_ISR_TCIF4                       ((uint32_t)0x00002000)        /*!< Channel 4 Transfer Complete flag */\r
+#define  DMA_ISR_HTIF4                       ((uint32_t)0x00004000)        /*!< Channel 4 Half Transfer flag */\r
+#define  DMA_ISR_TEIF4                       ((uint32_t)0x00008000)        /*!< Channel 4 Transfer Error flag */\r
+#define  DMA_ISR_GIF5                        ((uint32_t)0x00010000)        /*!< Channel 5 Global interrupt flag */\r
+#define  DMA_ISR_TCIF5                       ((uint32_t)0x00020000)        /*!< Channel 5 Transfer Complete flag */\r
+#define  DMA_ISR_HTIF5                       ((uint32_t)0x00040000)        /*!< Channel 5 Half Transfer flag */\r
+#define  DMA_ISR_TEIF5                       ((uint32_t)0x00080000)        /*!< Channel 5 Transfer Error flag */\r
+#define  DMA_ISR_GIF6                        ((uint32_t)0x00100000)        /*!< Channel 6 Global interrupt flag */\r
+#define  DMA_ISR_TCIF6                       ((uint32_t)0x00200000)        /*!< Channel 6 Transfer Complete flag */\r
+#define  DMA_ISR_HTIF6                       ((uint32_t)0x00400000)        /*!< Channel 6 Half Transfer flag */\r
+#define  DMA_ISR_TEIF6                       ((uint32_t)0x00800000)        /*!< Channel 6 Transfer Error flag */\r
+#define  DMA_ISR_GIF7                        ((uint32_t)0x01000000)        /*!< Channel 7 Global interrupt flag */\r
+#define  DMA_ISR_TCIF7                       ((uint32_t)0x02000000)        /*!< Channel 7 Transfer Complete flag */\r
+#define  DMA_ISR_HTIF7                       ((uint32_t)0x04000000)        /*!< Channel 7 Half Transfer flag */\r
+#define  DMA_ISR_TEIF7                       ((uint32_t)0x08000000)        /*!< Channel 7 Transfer Error flag */\r
+\r
+/*******************  Bit definition for DMA_IFCR register  *******************/\r
+#define  DMA_IFCR_CGIF1                      ((uint32_t)0x00000001)        /*!< Channel 1 Global interrupt clearr */\r
+#define  DMA_IFCR_CTCIF1                     ((uint32_t)0x00000002)        /*!< Channel 1 Transfer Complete clear */\r
+#define  DMA_IFCR_CHTIF1                     ((uint32_t)0x00000004)        /*!< Channel 1 Half Transfer clear */\r
+#define  DMA_IFCR_CTEIF1                     ((uint32_t)0x00000008)        /*!< Channel 1 Transfer Error clear */\r
+#define  DMA_IFCR_CGIF2                      ((uint32_t)0x00000010)        /*!< Channel 2 Global interrupt clear */\r
+#define  DMA_IFCR_CTCIF2                     ((uint32_t)0x00000020)        /*!< Channel 2 Transfer Complete clear */\r
+#define  DMA_IFCR_CHTIF2                     ((uint32_t)0x00000040)        /*!< Channel 2 Half Transfer clear */\r
+#define  DMA_IFCR_CTEIF2                     ((uint32_t)0x00000080)        /*!< Channel 2 Transfer Error clear */\r
+#define  DMA_IFCR_CGIF3                      ((uint32_t)0x00000100)        /*!< Channel 3 Global interrupt clear */\r
+#define  DMA_IFCR_CTCIF3                     ((uint32_t)0x00000200)        /*!< Channel 3 Transfer Complete clear */\r
+#define  DMA_IFCR_CHTIF3                     ((uint32_t)0x00000400)        /*!< Channel 3 Half Transfer clear */\r
+#define  DMA_IFCR_CTEIF3                     ((uint32_t)0x00000800)        /*!< Channel 3 Transfer Error clear */\r
+#define  DMA_IFCR_CGIF4                      ((uint32_t)0x00001000)        /*!< Channel 4 Global interrupt clear */\r
+#define  DMA_IFCR_CTCIF4                     ((uint32_t)0x00002000)        /*!< Channel 4 Transfer Complete clear */\r
+#define  DMA_IFCR_CHTIF4                     ((uint32_t)0x00004000)        /*!< Channel 4 Half Transfer clear */\r
+#define  DMA_IFCR_CTEIF4                     ((uint32_t)0x00008000)        /*!< Channel 4 Transfer Error clear */\r
+#define  DMA_IFCR_CGIF5                      ((uint32_t)0x00010000)        /*!< Channel 5 Global interrupt clear */\r
+#define  DMA_IFCR_CTCIF5                     ((uint32_t)0x00020000)        /*!< Channel 5 Transfer Complete clear */\r
+#define  DMA_IFCR_CHTIF5                     ((uint32_t)0x00040000)        /*!< Channel 5 Half Transfer clear */\r
+#define  DMA_IFCR_CTEIF5                     ((uint32_t)0x00080000)        /*!< Channel 5 Transfer Error clear */\r
+#define  DMA_IFCR_CGIF6                      ((uint32_t)0x00100000)        /*!< Channel 6 Global interrupt clear */\r
+#define  DMA_IFCR_CTCIF6                     ((uint32_t)0x00200000)        /*!< Channel 6 Transfer Complete clear */\r
+#define  DMA_IFCR_CHTIF6                     ((uint32_t)0x00400000)        /*!< Channel 6 Half Transfer clear */\r
+#define  DMA_IFCR_CTEIF6                     ((uint32_t)0x00800000)        /*!< Channel 6 Transfer Error clear */\r
+#define  DMA_IFCR_CGIF7                      ((uint32_t)0x01000000)        /*!< Channel 7 Global interrupt clear */\r
+#define  DMA_IFCR_CTCIF7                     ((uint32_t)0x02000000)        /*!< Channel 7 Transfer Complete clear */\r
+#define  DMA_IFCR_CHTIF7                     ((uint32_t)0x04000000)        /*!< Channel 7 Half Transfer clear */\r
+#define  DMA_IFCR_CTEIF7                     ((uint32_t)0x08000000)        /*!< Channel 7 Transfer Error clear */\r
+\r
+/*******************  Bit definition for DMA_CCR1 register  *******************/\r
+#define  DMA_CCR1_EN                         ((uint16_t)0x0001)            /*!< Channel enable*/\r
+#define  DMA_CCR1_TCIE                       ((uint16_t)0x0002)            /*!< Transfer complete interrupt enable */\r
+#define  DMA_CCR1_HTIE                       ((uint16_t)0x0004)            /*!< Half Transfer interrupt enable */\r
+#define  DMA_CCR1_TEIE                       ((uint16_t)0x0008)            /*!< Transfer error interrupt enable */\r
+#define  DMA_CCR1_DIR                        ((uint16_t)0x0010)            /*!< Data transfer direction */\r
+#define  DMA_CCR1_CIRC                       ((uint16_t)0x0020)            /*!< Circular mode */\r
+#define  DMA_CCR1_PINC                       ((uint16_t)0x0040)            /*!< Peripheral increment mode */\r
+#define  DMA_CCR1_MINC                       ((uint16_t)0x0080)            /*!< Memory increment mode */\r
+\r
+#define  DMA_CCR1_PSIZE                      ((uint16_t)0x0300)            /*!< PSIZE[1:0] bits (Peripheral size) */\r
+#define  DMA_CCR1_PSIZE_0                    ((uint16_t)0x0100)            /*!< Bit 0 */\r
+#define  DMA_CCR1_PSIZE_1                    ((uint16_t)0x0200)            /*!< Bit 1 */\r
+\r
+#define  DMA_CCR1_MSIZE                      ((uint16_t)0x0C00)            /*!< MSIZE[1:0] bits (Memory size) */\r
+#define  DMA_CCR1_MSIZE_0                    ((uint16_t)0x0400)            /*!< Bit 0 */\r
+#define  DMA_CCR1_MSIZE_1                    ((uint16_t)0x0800)            /*!< Bit 1 */\r
+\r
+#define  DMA_CCR1_PL                         ((uint16_t)0x3000)            /*!< PL[1:0] bits(Channel Priority level) */\r
+#define  DMA_CCR1_PL_0                       ((uint16_t)0x1000)            /*!< Bit 0 */\r
+#define  DMA_CCR1_PL_1                       ((uint16_t)0x2000)            /*!< Bit 1 */\r
+\r
+#define  DMA_CCR1_MEM2MEM                    ((uint16_t)0x4000)            /*!< Memory to memory mode */\r
+\r
+/*******************  Bit definition for DMA_CCR2 register  *******************/\r
+#define  DMA_CCR2_EN                         ((uint16_t)0x0001)            /*!< Channel enable */\r
+#define  DMA_CCR2_TCIE                       ((uint16_t)0x0002)            /*!< ransfer complete interrupt enable */\r
+#define  DMA_CCR2_HTIE                       ((uint16_t)0x0004)            /*!< Half Transfer interrupt enable */\r
+#define  DMA_CCR2_TEIE                       ((uint16_t)0x0008)            /*!< Transfer error interrupt enable */\r
+#define  DMA_CCR2_DIR                        ((uint16_t)0x0010)            /*!< Data transfer direction */\r
+#define  DMA_CCR2_CIRC                       ((uint16_t)0x0020)            /*!< Circular mode */\r
+#define  DMA_CCR2_PINC                       ((uint16_t)0x0040)            /*!< Peripheral increment mode */\r
+#define  DMA_CCR2_MINC                       ((uint16_t)0x0080)            /*!< Memory increment mode */\r
+\r
+#define  DMA_CCR2_PSIZE                      ((uint16_t)0x0300)            /*!< PSIZE[1:0] bits (Peripheral size) */\r
+#define  DMA_CCR2_PSIZE_0                    ((uint16_t)0x0100)            /*!< Bit 0 */\r
+#define  DMA_CCR2_PSIZE_1                    ((uint16_t)0x0200)            /*!< Bit 1 */\r
+\r
+#define  DMA_CCR2_MSIZE                      ((uint16_t)0x0C00)            /*!< MSIZE[1:0] bits (Memory size) */\r
+#define  DMA_CCR2_MSIZE_0                    ((uint16_t)0x0400)            /*!< Bit 0 */\r
+#define  DMA_CCR2_MSIZE_1                    ((uint16_t)0x0800)            /*!< Bit 1 */\r
+\r
+#define  DMA_CCR2_PL                         ((uint16_t)0x3000)            /*!< PL[1:0] bits (Channel Priority level) */\r
+#define  DMA_CCR2_PL_0                       ((uint16_t)0x1000)            /*!< Bit 0 */\r
+#define  DMA_CCR2_PL_1                       ((uint16_t)0x2000)            /*!< Bit 1 */\r
+\r
+#define  DMA_CCR2_MEM2MEM                    ((uint16_t)0x4000)            /*!< Memory to memory mode */\r
+\r
+/*******************  Bit definition for DMA_CCR3 register  *******************/\r
+#define  DMA_CCR3_EN                         ((uint16_t)0x0001)            /*!< Channel enable */\r
+#define  DMA_CCR3_TCIE                       ((uint16_t)0x0002)            /*!< Transfer complete interrupt enable */\r
+#define  DMA_CCR3_HTIE                       ((uint16_t)0x0004)            /*!< Half Transfer interrupt enable */\r
+#define  DMA_CCR3_TEIE                       ((uint16_t)0x0008)            /*!< Transfer error interrupt enable */\r
+#define  DMA_CCR3_DIR                        ((uint16_t)0x0010)            /*!< Data transfer direction */\r
+#define  DMA_CCR3_CIRC                       ((uint16_t)0x0020)            /*!< Circular mode */\r
+#define  DMA_CCR3_PINC                       ((uint16_t)0x0040)            /*!< Peripheral increment mode */\r
+#define  DMA_CCR3_MINC                       ((uint16_t)0x0080)            /*!< Memory increment mode */\r
+\r
+#define  DMA_CCR3_PSIZE                      ((uint16_t)0x0300)            /*!< PSIZE[1:0] bits (Peripheral size) */\r
+#define  DMA_CCR3_PSIZE_0                    ((uint16_t)0x0100)            /*!< Bit 0 */\r
+#define  DMA_CCR3_PSIZE_1                    ((uint16_t)0x0200)            /*!< Bit 1 */\r
+\r
+#define  DMA_CCR3_MSIZE                      ((uint16_t)0x0C00)            /*!< MSIZE[1:0] bits (Memory size) */\r
+#define  DMA_CCR3_MSIZE_0                    ((uint16_t)0x0400)            /*!< Bit 0 */\r
+#define  DMA_CCR3_MSIZE_1                    ((uint16_t)0x0800)            /*!< Bit 1 */\r
+\r
+#define  DMA_CCR3_PL                         ((uint16_t)0x3000)            /*!< PL[1:0] bits (Channel Priority level) */\r
+#define  DMA_CCR3_PL_0                       ((uint16_t)0x1000)            /*!< Bit 0 */\r
+#define  DMA_CCR3_PL_1                       ((uint16_t)0x2000)            /*!< Bit 1 */\r
+\r
+#define  DMA_CCR3_MEM2MEM                    ((uint16_t)0x4000)            /*!< Memory to memory mode */\r
+\r
+/*!<******************  Bit definition for DMA_CCR4 register  *******************/\r
+#define  DMA_CCR4_EN                         ((uint16_t)0x0001)            /*!< Channel enable */\r
+#define  DMA_CCR4_TCIE                       ((uint16_t)0x0002)            /*!< Transfer complete interrupt enable */\r
+#define  DMA_CCR4_HTIE                       ((uint16_t)0x0004)            /*!< Half Transfer interrupt enable */\r
+#define  DMA_CCR4_TEIE                       ((uint16_t)0x0008)            /*!< Transfer error interrupt enable */\r
+#define  DMA_CCR4_DIR                        ((uint16_t)0x0010)            /*!< Data transfer direction */\r
+#define  DMA_CCR4_CIRC                       ((uint16_t)0x0020)            /*!< Circular mode */\r
+#define  DMA_CCR4_PINC                       ((uint16_t)0x0040)            /*!< Peripheral increment mode */\r
+#define  DMA_CCR4_MINC                       ((uint16_t)0x0080)            /*!< Memory increment mode */\r
+\r
+#define  DMA_CCR4_PSIZE                      ((uint16_t)0x0300)            /*!< PSIZE[1:0] bits (Peripheral size) */\r
+#define  DMA_CCR4_PSIZE_0                    ((uint16_t)0x0100)            /*!< Bit 0 */\r
+#define  DMA_CCR4_PSIZE_1                    ((uint16_t)0x0200)            /*!< Bit 1 */\r
+\r
+#define  DMA_CCR4_MSIZE                      ((uint16_t)0x0C00)            /*!< MSIZE[1:0] bits (Memory size) */\r
+#define  DMA_CCR4_MSIZE_0                    ((uint16_t)0x0400)            /*!< Bit 0 */\r
+#define  DMA_CCR4_MSIZE_1                    ((uint16_t)0x0800)            /*!< Bit 1 */\r
+\r
+#define  DMA_CCR4_PL                         ((uint16_t)0x3000)            /*!< PL[1:0] bits (Channel Priority level) */\r
+#define  DMA_CCR4_PL_0                       ((uint16_t)0x1000)            /*!< Bit 0 */\r
+#define  DMA_CCR4_PL_1                       ((uint16_t)0x2000)            /*!< Bit 1 */\r
+\r
+#define  DMA_CCR4_MEM2MEM                    ((uint16_t)0x4000)            /*!< Memory to memory mode */\r
+\r
+/******************  Bit definition for DMA_CCR5 register  *******************/\r
+#define  DMA_CCR5_EN                         ((uint16_t)0x0001)            /*!< Channel enable */\r
+#define  DMA_CCR5_TCIE                       ((uint16_t)0x0002)            /*!< Transfer complete interrupt enable */\r
+#define  DMA_CCR5_HTIE                       ((uint16_t)0x0004)            /*!< Half Transfer interrupt enable */\r
+#define  DMA_CCR5_TEIE                       ((uint16_t)0x0008)            /*!< Transfer error interrupt enable */\r
+#define  DMA_CCR5_DIR                        ((uint16_t)0x0010)            /*!< Data transfer direction */\r
+#define  DMA_CCR5_CIRC                       ((uint16_t)0x0020)            /*!< Circular mode */\r
+#define  DMA_CCR5_PINC                       ((uint16_t)0x0040)            /*!< Peripheral increment mode */\r
+#define  DMA_CCR5_MINC                       ((uint16_t)0x0080)            /*!< Memory increment mode */\r
+\r
+#define  DMA_CCR5_PSIZE                      ((uint16_t)0x0300)            /*!< PSIZE[1:0] bits (Peripheral size) */\r
+#define  DMA_CCR5_PSIZE_0                    ((uint16_t)0x0100)            /*!< Bit 0 */\r
+#define  DMA_CCR5_PSIZE_1                    ((uint16_t)0x0200)            /*!< Bit 1 */\r
+\r
+#define  DMA_CCR5_MSIZE                      ((uint16_t)0x0C00)            /*!< MSIZE[1:0] bits (Memory size) */\r
+#define  DMA_CCR5_MSIZE_0                    ((uint16_t)0x0400)            /*!< Bit 0 */\r
+#define  DMA_CCR5_MSIZE_1                    ((uint16_t)0x0800)            /*!< Bit 1 */\r
+\r
+#define  DMA_CCR5_PL                         ((uint16_t)0x3000)            /*!< PL[1:0] bits (Channel Priority level) */\r
+#define  DMA_CCR5_PL_0                       ((uint16_t)0x1000)            /*!< Bit 0 */\r
+#define  DMA_CCR5_PL_1                       ((uint16_t)0x2000)            /*!< Bit 1 */\r
+\r
+#define  DMA_CCR5_MEM2MEM                    ((uint16_t)0x4000)            /*!< Memory to memory mode enable */\r
+\r
+/*******************  Bit definition for DMA_CCR6 register  *******************/\r
+#define  DMA_CCR6_EN                         ((uint16_t)0x0001)            /*!< Channel enable */\r
+#define  DMA_CCR6_TCIE                       ((uint16_t)0x0002)            /*!< Transfer complete interrupt enable */\r
+#define  DMA_CCR6_HTIE                       ((uint16_t)0x0004)            /*!< Half Transfer interrupt enable */\r
+#define  DMA_CCR6_TEIE                       ((uint16_t)0x0008)            /*!< Transfer error interrupt enable */\r
+#define  DMA_CCR6_DIR                        ((uint16_t)0x0010)            /*!< Data transfer direction */\r
+#define  DMA_CCR6_CIRC                       ((uint16_t)0x0020)            /*!< Circular mode */\r
+#define  DMA_CCR6_PINC                       ((uint16_t)0x0040)            /*!< Peripheral increment mode */\r
+#define  DMA_CCR6_MINC                       ((uint16_t)0x0080)            /*!< Memory increment mode */\r
+\r
+#define  DMA_CCR6_PSIZE                      ((uint16_t)0x0300)            /*!< PSIZE[1:0] bits (Peripheral size) */\r
+#define  DMA_CCR6_PSIZE_0                    ((uint16_t)0x0100)            /*!< Bit 0 */\r
+#define  DMA_CCR6_PSIZE_1                    ((uint16_t)0x0200)            /*!< Bit 1 */\r
+\r
+#define  DMA_CCR6_MSIZE                      ((uint16_t)0x0C00)            /*!< MSIZE[1:0] bits (Memory size) */\r
+#define  DMA_CCR6_MSIZE_0                    ((uint16_t)0x0400)            /*!< Bit 0 */\r
+#define  DMA_CCR6_MSIZE_1                    ((uint16_t)0x0800)            /*!< Bit 1 */\r
+\r
+#define  DMA_CCR6_PL                         ((uint16_t)0x3000)            /*!< PL[1:0] bits (Channel Priority level) */\r
+#define  DMA_CCR6_PL_0                       ((uint16_t)0x1000)            /*!< Bit 0 */\r
+#define  DMA_CCR6_PL_1                       ((uint16_t)0x2000)            /*!< Bit 1 */\r
+\r
+#define  DMA_CCR6_MEM2MEM                    ((uint16_t)0x4000)            /*!< Memory to memory mode */\r
+\r
+/*******************  Bit definition for DMA_CCR7 register  *******************/\r
+#define  DMA_CCR7_EN                         ((uint16_t)0x0001)            /*!< Channel enable */\r
+#define  DMA_CCR7_TCIE                       ((uint16_t)0x0002)            /*!< Transfer complete interrupt enable */\r
+#define  DMA_CCR7_HTIE                       ((uint16_t)0x0004)            /*!< Half Transfer interrupt enable */\r
+#define  DMA_CCR7_TEIE                       ((uint16_t)0x0008)            /*!< Transfer error interrupt enable */\r
+#define  DMA_CCR7_DIR                        ((uint16_t)0x0010)            /*!< Data transfer direction */\r
+#define  DMA_CCR7_CIRC                       ((uint16_t)0x0020)            /*!< Circular mode */\r
+#define  DMA_CCR7_PINC                       ((uint16_t)0x0040)            /*!< Peripheral increment mode */\r
+#define  DMA_CCR7_MINC                       ((uint16_t)0x0080)            /*!< Memory increment mode */\r
+\r
+#define  DMA_CCR7_PSIZE            ,         ((uint16_t)0x0300)            /*!< PSIZE[1:0] bits (Peripheral size) */\r
+#define  DMA_CCR7_PSIZE_0                    ((uint16_t)0x0100)            /*!< Bit 0 */\r
+#define  DMA_CCR7_PSIZE_1                    ((uint16_t)0x0200)            /*!< Bit 1 */\r
+\r
+#define  DMA_CCR7_MSIZE                      ((uint16_t)0x0C00)            /*!< MSIZE[1:0] bits (Memory size) */\r
+#define  DMA_CCR7_MSIZE_0                    ((uint16_t)0x0400)            /*!< Bit 0 */\r
+#define  DMA_CCR7_MSIZE_1                    ((uint16_t)0x0800)            /*!< Bit 1 */\r
+\r
+#define  DMA_CCR7_PL                         ((uint16_t)0x3000)            /*!< PL[1:0] bits (Channel Priority level) */\r
+#define  DMA_CCR7_PL_0                       ((uint16_t)0x1000)            /*!< Bit 0 */\r
+#define  DMA_CCR7_PL_1                       ((uint16_t)0x2000)            /*!< Bit 1 */\r
+\r
+#define  DMA_CCR7_MEM2MEM                    ((uint16_t)0x4000)            /*!< Memory to memory mode enable */\r
+\r
+/******************  Bit definition for DMA_CNDTR1 register  ******************/\r
+#define  DMA_CNDTR1_NDT                      ((uint16_t)0xFFFF)            /*!< Number of data to Transfer */\r
+\r
+/******************  Bit definition for DMA_CNDTR2 register  ******************/\r
+#define  DMA_CNDTR2_NDT                      ((uint16_t)0xFFFF)            /*!< Number of data to Transfer */\r
+\r
+/******************  Bit definition for DMA_CNDTR3 register  ******************/\r
+#define  DMA_CNDTR3_NDT                      ((uint16_t)0xFFFF)            /*!< Number of data to Transfer */\r
+\r
+/******************  Bit definition for DMA_CNDTR4 register  ******************/\r
+#define  DMA_CNDTR4_NDT                      ((uint16_t)0xFFFF)            /*!< Number of data to Transfer */\r
+\r
+/******************  Bit definition for DMA_CNDTR5 register  ******************/\r
+#define  DMA_CNDTR5_NDT                      ((uint16_t)0xFFFF)            /*!< Number of data to Transfer */\r
+\r
+/******************  Bit definition for DMA_CNDTR6 register  ******************/\r
+#define  DMA_CNDTR6_NDT                      ((uint16_t)0xFFFF)            /*!< Number of data to Transfer */\r
+\r
+/******************  Bit definition for DMA_CNDTR7 register  ******************/\r
+#define  DMA_CNDTR7_NDT                      ((uint16_t)0xFFFF)            /*!< Number of data to Transfer */\r
+\r
+/******************  Bit definition for DMA_CPAR1 register  *******************/\r
+#define  DMA_CPAR1_PA                        ((uint32_t)0xFFFFFFFF)        /*!< Peripheral Address */\r
+\r
+/******************  Bit definition for DMA_CPAR2 register  *******************/\r
+#define  DMA_CPAR2_PA                        ((uint32_t)0xFFFFFFFF)        /*!< Peripheral Address */\r
+\r
+/******************  Bit definition for DMA_CPAR3 register  *******************/\r
+#define  DMA_CPAR3_PA                        ((uint32_t)0xFFFFFFFF)        /*!< Peripheral Address */\r
+\r
+\r
+/******************  Bit definition for DMA_CPAR4 register  *******************/\r
+#define  DMA_CPAR4_PA                        ((uint32_t)0xFFFFFFFF)        /*!< Peripheral Address */\r
+\r
+/******************  Bit definition for DMA_CPAR5 register  *******************/\r
+#define  DMA_CPAR5_PA                        ((uint32_t)0xFFFFFFFF)        /*!< Peripheral Address */\r
+\r
+/******************  Bit definition for DMA_CPAR6 register  *******************/\r
+#define  DMA_CPAR6_PA                        ((uint32_t)0xFFFFFFFF)        /*!< Peripheral Address */\r
+\r
+\r
+/******************  Bit definition for DMA_CPAR7 register  *******************/\r
+#define  DMA_CPAR7_PA                        ((uint32_t)0xFFFFFFFF)        /*!< Peripheral Address */\r
+\r
+/******************  Bit definition for DMA_CMAR1 register  *******************/\r
+#define  DMA_CMAR1_MA                        ((uint32_t)0xFFFFFFFF)        /*!< Memory Address */\r
+\r
+/******************  Bit definition for DMA_CMAR2 register  *******************/\r
+#define  DMA_CMAR2_MA                        ((uint32_t)0xFFFFFFFF)        /*!< Memory Address */\r
+\r
+/******************  Bit definition for DMA_CMAR3 register  *******************/\r
+#define  DMA_CMAR3_MA                        ((uint32_t)0xFFFFFFFF)        /*!< Memory Address */\r
+\r
+\r
+/******************  Bit definition for DMA_CMAR4 register  *******************/\r
+#define  DMA_CMAR4_MA                        ((uint32_t)0xFFFFFFFF)        /*!< Memory Address */\r
+\r
+/******************  Bit definition for DMA_CMAR5 register  *******************/\r
+#define  DMA_CMAR5_MA                        ((uint32_t)0xFFFFFFFF)        /*!< Memory Address */\r
+\r
+/******************  Bit definition for DMA_CMAR6 register  *******************/\r
+#define  DMA_CMAR6_MA                        ((uint32_t)0xFFFFFFFF)        /*!< Memory Address */\r
+\r
+/******************  Bit definition for DMA_CMAR7 register  *******************/\r
+#define  DMA_CMAR7_MA                        ((uint32_t)0xFFFFFFFF)        /*!< Memory Address */\r
+\r
+/******************************************************************************/\r
+/*                                                                            */\r
+/*                    External Interrupt/Event Controller                     */\r
+/*                                                                            */\r
+/******************************************************************************/\r
+\r
+/*******************  Bit definition for EXTI_IMR register  *******************/\r
+#define  EXTI_IMR_MR0                        ((uint32_t)0x00000001)        /*!< Interrupt Mask on line 0 */\r
+#define  EXTI_IMR_MR1                        ((uint32_t)0x00000002)        /*!< Interrupt Mask on line 1 */\r
+#define  EXTI_IMR_MR2                        ((uint32_t)0x00000004)        /*!< Interrupt Mask on line 2 */\r
+#define  EXTI_IMR_MR3                        ((uint32_t)0x00000008)        /*!< Interrupt Mask on line 3 */\r
+#define  EXTI_IMR_MR4                        ((uint32_t)0x00000010)        /*!< Interrupt Mask on line 4 */\r
+#define  EXTI_IMR_MR5                        ((uint32_t)0x00000020)        /*!< Interrupt Mask on line 5 */\r
+#define  EXTI_IMR_MR6                        ((uint32_t)0x00000040)        /*!< Interrupt Mask on line 6 */\r
+#define  EXTI_IMR_MR7                        ((uint32_t)0x00000080)        /*!< Interrupt Mask on line 7 */\r
+#define  EXTI_IMR_MR8                        ((uint32_t)0x00000100)        /*!< Interrupt Mask on line 8 */\r
+#define  EXTI_IMR_MR9                        ((uint32_t)0x00000200)        /*!< Interrupt Mask on line 9 */\r
+#define  EXTI_IMR_MR10                       ((uint32_t)0x00000400)        /*!< Interrupt Mask on line 10 */\r
+#define  EXTI_IMR_MR11                       ((uint32_t)0x00000800)        /*!< Interrupt Mask on line 11 */\r
+#define  EXTI_IMR_MR12                       ((uint32_t)0x00001000)        /*!< Interrupt Mask on line 12 */\r
+#define  EXTI_IMR_MR13                       ((uint32_t)0x00002000)        /*!< Interrupt Mask on line 13 */\r
+#define  EXTI_IMR_MR14                       ((uint32_t)0x00004000)        /*!< Interrupt Mask on line 14 */\r
+#define  EXTI_IMR_MR15                       ((uint32_t)0x00008000)        /*!< Interrupt Mask on line 15 */\r
+#define  EXTI_IMR_MR16                       ((uint32_t)0x00010000)        /*!< Interrupt Mask on line 16 */\r
+#define  EXTI_IMR_MR17                       ((uint32_t)0x00020000)        /*!< Interrupt Mask on line 17 */\r
+#define  EXTI_IMR_MR18                       ((uint32_t)0x00040000)        /*!< Interrupt Mask on line 18 */\r
+#define  EXTI_IMR_MR19                       ((uint32_t)0x00080000)        /*!< Interrupt Mask on line 19 */\r
+#define  EXTI_IMR_MR20                       ((uint32_t)0x00100000)        /*!< Interrupt Mask on line 20 */\r
+#define  EXTI_IMR_MR21                       ((uint32_t)0x00200000)        /*!< Interrupt Mask on line 21 */\r
+#define  EXTI_IMR_MR22                       ((uint32_t)0x00400000)        /*!< Interrupt Mask on line 22 */\r
+\r
+/*******************  Bit definition for EXTI_EMR register  *******************/\r
+#define  EXTI_EMR_MR0                        ((uint32_t)0x00000001)        /*!< Event Mask on line 0 */\r
+#define  EXTI_EMR_MR1                        ((uint32_t)0x00000002)        /*!< Event Mask on line 1 */\r
+#define  EXTI_EMR_MR2                        ((uint32_t)0x00000004)        /*!< Event Mask on line 2 */\r
+#define  EXTI_EMR_MR3                        ((uint32_t)0x00000008)        /*!< Event Mask on line 3 */\r
+#define  EXTI_EMR_MR4                        ((uint32_t)0x00000010)        /*!< Event Mask on line 4 */\r
+#define  EXTI_EMR_MR5                        ((uint32_t)0x00000020)        /*!< Event Mask on line 5 */\r
+#define  EXTI_EMR_MR6                        ((uint32_t)0x00000040)        /*!< Event Mask on line 6 */\r
+#define  EXTI_EMR_MR7                        ((uint32_t)0x00000080)        /*!< Event Mask on line 7 */\r
+#define  EXTI_EMR_MR8                        ((uint32_t)0x00000100)        /*!< Event Mask on line 8 */\r
+#define  EXTI_EMR_MR9                        ((uint32_t)0x00000200)        /*!< Event Mask on line 9 */\r
+#define  EXTI_EMR_MR10                       ((uint32_t)0x00000400)        /*!< Event Mask on line 10 */\r
+#define  EXTI_EMR_MR11                       ((uint32_t)0x00000800)        /*!< Event Mask on line 11 */\r
+#define  EXTI_EMR_MR12                       ((uint32_t)0x00001000)        /*!< Event Mask on line 12 */\r
+#define  EXTI_EMR_MR13                       ((uint32_t)0x00002000)        /*!< Event Mask on line 13 */\r
+#define  EXTI_EMR_MR14                       ((uint32_t)0x00004000)        /*!< Event Mask on line 14 */\r
+#define  EXTI_EMR_MR15                       ((uint32_t)0x00008000)        /*!< Event Mask on line 15 */\r
+#define  EXTI_EMR_MR16                       ((uint32_t)0x00010000)        /*!< Event Mask on line 16 */\r
+#define  EXTI_EMR_MR17                       ((uint32_t)0x00020000)        /*!< Event Mask on line 17 */\r
+#define  EXTI_EMR_MR18                       ((uint32_t)0x00040000)        /*!< Event Mask on line 18 */\r
+#define  EXTI_EMR_MR19                       ((uint32_t)0x00080000)        /*!< Event Mask on line 19 */\r
+#define  EXTI_EMR_MR20                       ((uint32_t)0x00100000)        /*!< Event Mask on line 20 */\r
+#define  EXTI_EMR_MR21                       ((uint32_t)0x00200000)        /*!< Event Mask on line 21 */\r
+#define  EXTI_EMR_MR22                       ((uint32_t)0x00400000)        /*!< Event Mask on line 22 */\r
+\r
+/******************  Bit definition for EXTI_RTSR register  *******************/\r
+#define  EXTI_RTSR_TR0                       ((uint32_t)0x00000001)        /*!< Rising trigger event configuration bit of line 0 */\r
+#define  EXTI_RTSR_TR1                       ((uint32_t)0x00000002)        /*!< Rising trigger event configuration bit of line 1 */\r
+#define  EXTI_RTSR_TR2                       ((uint32_t)0x00000004)        /*!< Rising trigger event configuration bit of line 2 */\r
+#define  EXTI_RTSR_TR3                       ((uint32_t)0x00000008)        /*!< Rising trigger event configuration bit of line 3 */\r
+#define  EXTI_RTSR_TR4                       ((uint32_t)0x00000010)        /*!< Rising trigger event configuration bit of line 4 */\r
+#define  EXTI_RTSR_TR5                       ((uint32_t)0x00000020)        /*!< Rising trigger event configuration bit of line 5 */\r
+#define  EXTI_RTSR_TR6                       ((uint32_t)0x00000040)        /*!< Rising trigger event configuration bit of line 6 */\r
+#define  EXTI_RTSR_TR7                       ((uint32_t)0x00000080)        /*!< Rising trigger event configuration bit of line 7 */\r
+#define  EXTI_RTSR_TR8                       ((uint32_t)0x00000100)        /*!< Rising trigger event configuration bit of line 8 */\r
+#define  EXTI_RTSR_TR9                       ((uint32_t)0x00000200)        /*!< Rising trigger event configuration bit of line 9 */\r
+#define  EXTI_RTSR_TR10                      ((uint32_t)0x00000400)        /*!< Rising trigger event configuration bit of line 10 */\r
+#define  EXTI_RTSR_TR11                      ((uint32_t)0x00000800)        /*!< Rising trigger event configuration bit of line 11 */\r
+#define  EXTI_RTSR_TR12                      ((uint32_t)0x00001000)        /*!< Rising trigger event configuration bit of line 12 */\r
+#define  EXTI_RTSR_TR13                      ((uint32_t)0x00002000)        /*!< Rising trigger event configuration bit of line 13 */\r
+#define  EXTI_RTSR_TR14                      ((uint32_t)0x00004000)        /*!< Rising trigger event configuration bit of line 14 */\r
+#define  EXTI_RTSR_TR15                      ((uint32_t)0x00008000)        /*!< Rising trigger event configuration bit of line 15 */\r
+#define  EXTI_RTSR_TR16                      ((uint32_t)0x00010000)        /*!< Rising trigger event configuration bit of line 16 */\r
+#define  EXTI_RTSR_TR17                      ((uint32_t)0x00020000)        /*!< Rising trigger event configuration bit of line 17 */\r
+#define  EXTI_RTSR_TR18                      ((uint32_t)0x00040000)        /*!< Rising trigger event configuration bit of line 18 */\r
+#define  EXTI_RTSR_TR19                      ((uint32_t)0x00080000)        /*!< Rising trigger event configuration bit of line 19 */\r
+#define  EXTI_RTSR_TR20                      ((uint32_t)0x00100000)        /*!< Rising trigger event configuration bit of line 20 */\r
+#define  EXTI_RTSR_TR21                      ((uint32_t)0x00200000)        /*!< Rising trigger event configuration bit of line 21 */\r
+#define  EXTI_RTSR_TR22                      ((uint32_t)0x00400000)        /*!< Rising trigger event configuration bit of line 22 */\r
+\r
+/******************  Bit definition for EXTI_FTSR register  *******************/\r
+#define  EXTI_FTSR_TR0                       ((uint32_t)0x00000001)        /*!< Falling trigger event configuration bit of line 0 */\r
+#define  EXTI_FTSR_TR1                       ((uint32_t)0x00000002)        /*!< Falling trigger event configuration bit of line 1 */\r
+#define  EXTI_FTSR_TR2                       ((uint32_t)0x00000004)        /*!< Falling trigger event configuration bit of line 2 */\r
+#define  EXTI_FTSR_TR3                       ((uint32_t)0x00000008)        /*!< Falling trigger event configuration bit of line 3 */\r
+#define  EXTI_FTSR_TR4                       ((uint32_t)0x00000010)        /*!< Falling trigger event configuration bit of line 4 */\r
+#define  EXTI_FTSR_TR5                       ((uint32_t)0x00000020)        /*!< Falling trigger event configuration bit of line 5 */\r
+#define  EXTI_FTSR_TR6                       ((uint32_t)0x00000040)        /*!< Falling trigger event configuration bit of line 6 */\r
+#define  EXTI_FTSR_TR7                       ((uint32_t)0x00000080)        /*!< Falling trigger event configuration bit of line 7 */\r
+#define  EXTI_FTSR_TR8                       ((uint32_t)0x00000100)        /*!< Falling trigger event configuration bit of line 8 */\r
+#define  EXTI_FTSR_TR9                       ((uint32_t)0x00000200)        /*!< Falling trigger event configuration bit of line 9 */\r
+#define  EXTI_FTSR_TR10                      ((uint32_t)0x00000400)        /*!< Falling trigger event configuration bit of line 10 */\r
+#define  EXTI_FTSR_TR11                      ((uint32_t)0x00000800)        /*!< Falling trigger event configuration bit of line 11 */\r
+#define  EXTI_FTSR_TR12                      ((uint32_t)0x00001000)        /*!< Falling trigger event configuration bit of line 12 */\r
+#define  EXTI_FTSR_TR13                      ((uint32_t)0x00002000)        /*!< Falling trigger event configuration bit of line 13 */\r
+#define  EXTI_FTSR_TR14                      ((uint32_t)0x00004000)        /*!< Falling trigger event configuration bit of line 14 */\r
+#define  EXTI_FTSR_TR15                      ((uint32_t)0x00008000)        /*!< Falling trigger event configuration bit of line 15 */\r
+#define  EXTI_FTSR_TR16                      ((uint32_t)0x00010000)        /*!< Falling trigger event configuration bit of line 16 */\r
+#define  EXTI_FTSR_TR17                      ((uint32_t)0x00020000)        /*!< Falling trigger event configuration bit of line 17 */\r
+#define  EXTI_FTSR_TR18                      ((uint32_t)0x00040000)        /*!< Falling trigger event configuration bit of line 18 */\r
+#define  EXTI_FTSR_TR19                      ((uint32_t)0x00080000)        /*!< Falling trigger event configuration bit of line 19 */\r
+#define  EXTI_FTSR_TR20                      ((uint32_t)0x00100000)        /*!< Falling trigger event configuration bit of line 20 */\r
+#define  EXTI_FTSR_TR21                      ((uint32_t)0x00200000)        /*!< Falling trigger event configuration bit of line 21 */\r
+#define  EXTI_FTSR_TR22                      ((uint32_t)0x00400000)        /*!< Falling trigger event configuration bit of line 22 */\r
+\r
+/******************  Bit definition for EXTI_SWIER register  ******************/\r
+#define  EXTI_SWIER_SWIER0                   ((uint32_t)0x00000001)        /*!< Software Interrupt on line 0 */\r
+#define  EXTI_SWIER_SWIER1                   ((uint32_t)0x00000002)        /*!< Software Interrupt on line 1 */\r
+#define  EXTI_SWIER_SWIER2                   ((uint32_t)0x00000004)        /*!< Software Interrupt on line 2 */\r
+#define  EXTI_SWIER_SWIER3                   ((uint32_t)0x00000008)        /*!< Software Interrupt on line 3 */\r
+#define  EXTI_SWIER_SWIER4                   ((uint32_t)0x00000010)        /*!< Software Interrupt on line 4 */\r
+#define  EXTI_SWIER_SWIER5                   ((uint32_t)0x00000020)        /*!< Software Interrupt on line 5 */\r
+#define  EXTI_SWIER_SWIER6                   ((uint32_t)0x00000040)        /*!< Software Interrupt on line 6 */\r
+#define  EXTI_SWIER_SWIER7                   ((uint32_t)0x00000080)        /*!< Software Interrupt on line 7 */\r
+#define  EXTI_SWIER_SWIER8                   ((uint32_t)0x00000100)        /*!< Software Interrupt on line 8 */\r
+#define  EXTI_SWIER_SWIER9                   ((uint32_t)0x00000200)        /*!< Software Interrupt on line 9 */\r
+#define  EXTI_SWIER_SWIER10                  ((uint32_t)0x00000400)        /*!< Software Interrupt on line 10 */\r
+#define  EXTI_SWIER_SWIER11                  ((uint32_t)0x00000800)        /*!< Software Interrupt on line 11 */\r
+#define  EXTI_SWIER_SWIER12                  ((uint32_t)0x00001000)        /*!< Software Interrupt on line 12 */\r
+#define  EXTI_SWIER_SWIER13                  ((uint32_t)0x00002000)        /*!< Software Interrupt on line 13 */\r
+#define  EXTI_SWIER_SWIER14                  ((uint32_t)0x00004000)        /*!< Software Interrupt on line 14 */\r
+#define  EXTI_SWIER_SWIER15                  ((uint32_t)0x00008000)        /*!< Software Interrupt on line 15 */\r
+#define  EXTI_SWIER_SWIER16                  ((uint32_t)0x00010000)        /*!< Software Interrupt on line 16 */\r
+#define  EXTI_SWIER_SWIER17                  ((uint32_t)0x00020000)        /*!< Software Interrupt on line 17 */\r
+#define  EXTI_SWIER_SWIER18                  ((uint32_t)0x00040000)        /*!< Software Interrupt on line 18 */\r
+#define  EXTI_SWIER_SWIER19                  ((uint32_t)0x00080000)        /*!< Software Interrupt on line 19 */\r
+#define  EXTI_SWIER_SWIER20                  ((uint32_t)0x00100000)        /*!< Software Interrupt on line 20 */\r
+#define  EXTI_SWIER_SWIER21                  ((uint32_t)0x00200000)        /*!< Software Interrupt on line 21 */\r
+#define  EXTI_SWIER_SWIER22                  ((uint32_t)0x00400000)        /*!< Software Interrupt on line 22 */\r
+\r
+/*******************  Bit definition for EXTI_PR register  ********************/\r
+#define  EXTI_PR_PR0                         ((uint32_t)0x00000001)        /*!< Pending bit 0 */\r
+#define  EXTI_PR_PR1                         ((uint32_t)0x00000002)        /*!< Pending bit 1 */\r
+#define  EXTI_PR_PR2                         ((uint32_t)0x00000004)        /*!< Pending bit 2 */\r
+#define  EXTI_PR_PR3                         ((uint32_t)0x00000008)        /*!< Pending bit 3 */\r
+#define  EXTI_PR_PR4                         ((uint32_t)0x00000010)        /*!< Pending bit 4 */\r
+#define  EXTI_PR_PR5                         ((uint32_t)0x00000020)        /*!< Pending bit 5 */\r
+#define  EXTI_PR_PR6                         ((uint32_t)0x00000040)        /*!< Pending bit 6 */\r
+#define  EXTI_PR_PR7                         ((uint32_t)0x00000080)        /*!< Pending bit 7 */\r
+#define  EXTI_PR_PR8                         ((uint32_t)0x00000100)        /*!< Pending bit 8 */\r
+#define  EXTI_PR_PR9                         ((uint32_t)0x00000200)        /*!< Pending bit 9 */\r
+#define  EXTI_PR_PR10                        ((uint32_t)0x00000400)        /*!< Pending bit 10 */\r
+#define  EXTI_PR_PR11                        ((uint32_t)0x00000800)        /*!< Pending bit 11 */\r
+#define  EXTI_PR_PR12                        ((uint32_t)0x00001000)        /*!< Pending bit 12 */\r
+#define  EXTI_PR_PR13                        ((uint32_t)0x00002000)        /*!< Pending bit 13 */\r
+#define  EXTI_PR_PR14                        ((uint32_t)0x00004000)        /*!< Pending bit 14 */\r
+#define  EXTI_PR_PR15                        ((uint32_t)0x00008000)        /*!< Pending bit 15 */\r
+#define  EXTI_PR_PR16                        ((uint32_t)0x00010000)        /*!< Pending bit 16 */\r
+#define  EXTI_PR_PR17                        ((uint32_t)0x00020000)        /*!< Pending bit 17 */\r
+#define  EXTI_PR_PR18                        ((uint32_t)0x00040000)        /*!< Pending bit 18 */\r
+#define  EXTI_PR_PR19                        ((uint32_t)0x00080000)        /*!< Pending bit 19 */\r
+#define  EXTI_PR_PR20                        ((uint32_t)0x00100000)        /*!< Pending bit 20 */\r
+#define  EXTI_PR_PR21                        ((uint32_t)0x00200000)        /*!< Pending bit 21 */\r
+#define  EXTI_PR_PR22                        ((uint32_t)0x00400000)        /*!< Pending bit 22 */\r
+\r
+/******************************************************************************/\r
+/*                                                                            */\r
+/*                      FLASH and Option Bytes Registers                      */\r
+/*                                                                            */\r
+/******************************************************************************/\r
+\r
+/*******************  Bit definition for FLASH_ACR register  ******************/\r
+#define  FLASH_ACR_LATENCY                   ((uint32_t)0x00000001)        /*!< Latency */\r
+#define  FLASH_ACR_PRFTEN                    ((uint32_t)0x00000002)        /*!< Prefetch Buffer Enable */\r
+#define  FLASH_ACR_ACC64                     ((uint32_t)0x00000004)        /*!< Access 64 bits */\r
+#define  FLASH_ACR_SLEEP_PD                  ((uint32_t)0x00000008)        /*!< Flash mode during sleep mode */\r
+#define  FLASH_ACR_RUN_PD                    ((uint32_t)0x00000010)        /*!< Flash mode during RUN mode */\r
+\r
+/*******************  Bit definition for FLASH_PECR register  ******************/\r
+#define FLASH_PECR_PELOCK                    ((uint32_t)0x00000001)        /*!< FLASH_PECR and Flash data Lock */\r
+#define FLASH_PECR_PRGLOCK                   ((uint32_t)0x00000002)        /*!< Program matrix Lock */\r
+#define FLASH_PECR_OPTLOCK                   ((uint32_t)0x00000004)        /*!< Option byte matrix Lock */\r
+#define FLASH_PECR_PROG                      ((uint32_t)0x00000008)        /*!< Program matrix selection */\r
+#define FLASH_PECR_DATA                      ((uint32_t)0x00000010)        /*!< Data matrix selection */\r
+#define FLASH_PECR_FTDW                      ((uint32_t)0x00000100)        /*!< Fixed Time Data write for Word/Half Word/Byte programming */\r
+#define FLASH_PECR_ERASE                     ((uint32_t)0x00000200)        /*!< Page erasing mode */\r
+#define FLASH_PECR_FPRG                      ((uint32_t)0x00000400)        /*!< Fast Page/Half Page programming mode */\r
+#define FLASH_PECR_EOPIE                     ((uint32_t)0x00010000)        /*!< End of programming interrupt */ \r
+#define FLASH_PECR_ERRIE                     ((uint32_t)0x00020000)        /*!< Error interrupt */ \r
+#define FLASH_PECR_OBL_LAUNCH                ((uint32_t)0x00040000)        /*!< Launch the option byte loading */ \r
+\r
+/******************  Bit definition for FLASH_PDKEYR register  ******************/\r
+#define  FLASH_PDKEYR_PDKEYR                 ((uint32_t)0xFFFFFFFF)       /*!< FLASH_PEC and data matrix Key */\r
+\r
+/******************  Bit definition for FLASH_PEKEYR register  ******************/\r
+#define  FLASH_PEKEYR_PEKEYR                 ((uint32_t)0xFFFFFFFF)       /*!< FLASH_PEC and data matrix Key */\r
+\r
+/******************  Bit definition for FLASH_PRGKEYR register  ******************/\r
+#define  FLASH_PRGKEYR_PRGKEYR               ((uint32_t)0xFFFFFFFF)        /*!< Program matrix Key */\r
+\r
+/******************  Bit definition for FLASH_OPTKEYR register  ******************/\r
+#define  FLASH_OPTKEYR_OPTKEYR               ((uint32_t)0xFFFFFFFF)        /*!< Option bytes matrix Key */\r
+\r
+/******************  Bit definition for FLASH_SR register  *******************/\r
+#define  FLASH_SR_BSY                        ((uint32_t)0x00000001)        /*!< Busy */\r
+#define  FLASH_SR_EOP                        ((uint32_t)0x00000002)        /*!< End Of Programming*/\r
+#define  FLASH_SR_ENHV                       ((uint32_t)0x00000004)        /*!< End of high voltage */\r
+#define  FLASH_SR_READY                      ((uint32_t)0x00000008)        /*!< Flash ready after low power mode */\r
+\r
+#define  FLASH_SR_WRPERR                     ((uint32_t)0x00000100)        /*!< Write protected error */\r
+#define  FLASH_SR_PGAERR                     ((uint32_t)0x00000200)        /*!< Programming Alignment Error */\r
+#define  FLASH_SR_SIZERR                     ((uint32_t)0x00000400)        /*!< Size error */\r
+#define  FLASH_SR_OPTVERR                    ((uint32_t)0x00000800)        /*!< Option validity error */\r
+\r
+/******************  Bit definition for FLASH_OBR register  *******************/\r
+#define  FLASH_OBR_RDPRT                     ((uint16_t)0x000000AA)        /*!< Read Protection */\r
+#define  FLASH_OBR_BOR_LEV                   ((uint16_t)0x000F0000)        /*!< BOR_LEV[3:0] Brown Out Reset Threshold Level*/\r
+#define  FLASH_OBR_USER                      ((uint32_t)0x00700000)        /*!< User Option Bytes */\r
+#define  FLASH_OBR_IWDG_SW                   ((uint32_t)0x00100000)        /*!< IWDG_SW */\r
+#define  FLASH_OBR_nRST_STOP                 ((uint32_t)0x00200000)        /*!< nRST_STOP */\r
+#define  FLASH_OBR_nRST_STDBY                ((uint32_t)0x00400000)        /*!< nRST_STDBY */\r
+\r
+/******************  Bit definition for FLASH_WRPR register  ******************/\r
+#define  FLASH_WRPR_WRP                      ((uint32_t)0xFFFFFFFF)        /*!< Write Protect */\r
+\r
+/******************************************************************************/\r
+/*                                                                            */\r
+/*                        General Purpose IOs                                 */\r
+/*                                                                            */\r
+/******************************************************************************/\r
+/*******************  Bit definition for GPIO_MODER register  *****************/  \r
+#define GPIO_MODER_MODER0          ((uint32_t)0x00000003)\r
+#define GPIO_MODER_MODER0_0        ((uint32_t)0x00000001)\r
+#define GPIO_MODER_MODER0_1        ((uint32_t)0x00000002)\r
+#define GPIO_MODER_MODER1          ((uint32_t)0x0000000C)\r
+#define GPIO_MODER_MODER1_0        ((uint32_t)0x00000004)\r
+#define GPIO_MODER_MODER1_1        ((uint32_t)0x00000008)\r
+#define GPIO_MODER_MODER2          ((uint32_t)0x00000030)\r
+#define GPIO_MODER_MODER2_0        ((uint32_t)0x00000010)\r
+#define GPIO_MODER_MODER2_1        ((uint32_t)0x00000020)\r
+#define GPIO_MODER_MODER3          ((uint32_t)0x000000C0)\r
+#define GPIO_MODER_MODER3_0        ((uint32_t)0x00000040)\r
+#define GPIO_MODER_MODER3_1        ((uint32_t)0x00000080)\r
+#define GPIO_MODER_MODER4          ((uint32_t)0x00000300)\r
+#define GPIO_MODER_MODER4_0        ((uint32_t)0x00000100)\r
+#define GPIO_MODER_MODER4_1        ((uint32_t)0x00000200)\r
+#define GPIO_MODER_MODER5          ((uint32_t)0x00000C00)\r
+#define GPIO_MODER_MODER5_0        ((uint32_t)0x00000400)\r
+#define GPIO_MODER_MODER5_1        ((uint32_t)0x00000800)\r
+#define GPIO_MODER_MODER6          ((uint32_t)0x00003000)\r
+#define GPIO_MODER_MODER6_0        ((uint32_t)0x00001000)\r
+#define GPIO_MODER_MODER6_1        ((uint32_t)0x00002000)\r
+#define GPIO_MODER_MODER7          ((uint32_t)0x0000C000)\r
+#define GPIO_MODER_MODER7_0        ((uint32_t)0x00004000)\r
+#define GPIO_MODER_MODER7_1        ((uint32_t)0x00008000)\r
+#define GPIO_MODER_MODER8          ((uint32_t)0x00030000)\r
+#define GPIO_MODER_MODER8_0        ((uint32_t)0x00010000)\r
+#define GPIO_MODER_MODER8_1        ((uint32_t)0x00020000)\r
+#define GPIO_MODER_MODER9          ((uint32_t)0x000C0000)\r
+#define GPIO_MODER_MODER9_0        ((uint32_t)0x00040000)\r
+#define GPIO_MODER_MODER9_1        ((uint32_t)0x00080000)\r
+#define GPIO_MODER_MODER10         ((uint32_t)0x00300000)\r
+#define GPIO_MODER_MODER10_0       ((uint32_t)0x00100000)\r
+#define GPIO_MODER_MODER10_1       ((uint32_t)0x00200000)\r
+#define GPIO_MODER_MODER11         ((uint32_t)0x00C00000)\r
+#define GPIO_MODER_MODER11_0       ((uint32_t)0x00400000)\r
+#define GPIO_MODER_MODER11_1       ((uint32_t)0x00800000)\r
+#define GPIO_MODER_MODER12         ((uint32_t)0x03000000)\r
+#define GPIO_MODER_MODER12_0       ((uint32_t)0x01000000)\r
+#define GPIO_MODER_MODER12_1       ((uint32_t)0x02000000)\r
+#define GPIO_MODER_MODER13         ((uint32_t)0x0C000000)\r
+#define GPIO_MODER_MODER13_0       ((uint32_t)0x04000000)\r
+#define GPIO_MODER_MODER13_1       ((uint32_t)0x08000000)\r
+#define GPIO_MODER_MODER14         ((uint32_t)0x30000000)\r
+#define GPIO_MODER_MODER14_0       ((uint32_t)0x10000000)\r
+#define GPIO_MODER_MODER14_1       ((uint32_t)0x20000000)\r
+#define GPIO_MODER_MODER15         ((uint32_t)0xC0000000)\r
+#define GPIO_MODER_MODER15_0       ((uint32_t)0x40000000)\r
+#define GPIO_MODER_MODER15_1       ((uint32_t)0x80000000)\r
+\r
+/*******************  Bit definition for GPIO_OTYPER register  ****************/   \r
+#define GPIO_OTYPER_OT_0           ((uint32_t)0x00000001)\r
+#define GPIO_OTYPER_OT_1           ((uint32_t)0x00000002)\r
+#define GPIO_OTYPER_OT_2           ((uint32_t)0x00000004)\r
+#define GPIO_OTYPER_OT_3           ((uint32_t)0x00000008)\r
+#define GPIO_OTYPER_OT_4           ((uint32_t)0x00000010)\r
+#define GPIO_OTYPER_OT_5           ((uint32_t)0x00000020)\r
+#define GPIO_OTYPER_OT_6           ((uint32_t)0x00000040)\r
+#define GPIO_OTYPER_OT_7           ((uint32_t)0x00000080)\r
+#define GPIO_OTYPER_OT_8           ((uint32_t)0x00000100)\r
+#define GPIO_OTYPER_OT_9           ((uint32_t)0x00000200)\r
+#define GPIO_OTYPER_OT_10          ((uint32_t)0x00000400)\r
+#define GPIO_OTYPER_OT_11          ((uint32_t)0x00000800)\r
+#define GPIO_OTYPER_OT_12          ((uint32_t)0x00001000)\r
+#define GPIO_OTYPER_OT_13          ((uint32_t)0x00002000)\r
+#define GPIO_OTYPER_OT_14          ((uint32_t)0x00004000)\r
+#define GPIO_OTYPER_OT_15          ((uint32_t)0x00008000)\r
+\r
+/*******************  Bit definition for GPIO_OSPEEDR register  ***************/  \r
+#define GPIO_OSPEEDER_OSPEEDR0     ((uint32_t)0x00000003)\r
+#define GPIO_OSPEEDER_OSPEEDR0_0   ((uint32_t)0x00000001)\r
+#define GPIO_OSPEEDER_OSPEEDR0_1   ((uint32_t)0x00000002)\r
+#define GPIO_OSPEEDER_OSPEEDR1     ((uint32_t)0x0000000C)\r
+#define GPIO_OSPEEDER_OSPEEDR1_0   ((uint32_t)0x00000004)\r
+#define GPIO_OSPEEDER_OSPEEDR1_1   ((uint32_t)0x00000008)\r
+#define GPIO_OSPEEDER_OSPEEDR2     ((uint32_t)0x00000030)\r
+#define GPIO_OSPEEDER_OSPEEDR2_0   ((uint32_t)0x00000010)\r
+#define GPIO_OSPEEDER_OSPEEDR2_1   ((uint32_t)0x00000020)\r
+#define GPIO_OSPEEDER_OSPEEDR3     ((uint32_t)0x000000C0)\r
+#define GPIO_OSPEEDER_OSPEEDR3_0   ((uint32_t)0x00000040)\r
+#define GPIO_OSPEEDER_OSPEEDR3_1   ((uint32_t)0x00000080)\r
+#define GPIO_OSPEEDER_OSPEEDR4     ((uint32_t)0x00000300)\r
+#define GPIO_OSPEEDER_OSPEEDR4_0   ((uint32_t)0x00000100)\r
+#define GPIO_OSPEEDER_OSPEEDR4_1   ((uint32_t)0x00000200)\r
+#define GPIO_OSPEEDER_OSPEEDR5     ((uint32_t)0x00000C00)\r
+#define GPIO_OSPEEDER_OSPEEDR5_0   ((uint32_t)0x00000400)\r
+#define GPIO_OSPEEDER_OSPEEDR5_1   ((uint32_t)0x00000800)\r
+#define GPIO_OSPEEDER_OSPEEDR6     ((uint32_t)0x00003000)\r
+#define GPIO_OSPEEDER_OSPEEDR6_0   ((uint32_t)0x00001000)\r
+#define GPIO_OSPEEDER_OSPEEDR6_1   ((uint32_t)0x00002000)\r
+#define GPIO_OSPEEDER_OSPEEDR7     ((uint32_t)0x0000C000)\r
+#define GPIO_OSPEEDER_OSPEEDR7_0   ((uint32_t)0x00004000)\r
+#define GPIO_OSPEEDER_OSPEEDR7_1   ((uint32_t)0x00008000)\r
+#define GPIO_OSPEEDER_OSPEEDR8     ((uint32_t)0x00030000)\r
+#define GPIO_OSPEEDER_OSPEEDR8_0   ((uint32_t)0x00010000)\r
+#define GPIO_OSPEEDER_OSPEEDR8_1   ((uint32_t)0x00020000)\r
+#define GPIO_OSPEEDER_OSPEEDR9     ((uint32_t)0x000C0000)\r
+#define GPIO_OSPEEDER_OSPEEDR9_0   ((uint32_t)0x00040000)\r
+#define GPIO_OSPEEDER_OSPEEDR9_1   ((uint32_t)0x00080000)\r
+#define GPIO_OSPEEDER_OSPEEDR10    ((uint32_t)0x00300000)\r
+#define GPIO_OSPEEDER_OSPEEDR10_0  ((uint32_t)0x00100000)\r
+#define GPIO_OSPEEDER_OSPEEDR10_1  ((uint32_t)0x00200000)\r
+#define GPIO_OSPEEDER_OSPEEDR11    ((uint32_t)0x00C00000)\r
+#define GPIO_OSPEEDER_OSPEEDR11_0  ((uint32_t)0x00400000)\r
+#define GPIO_OSPEEDER_OSPEEDR11_1  ((uint32_t)0x00800000)\r
+#define GPIO_OSPEEDER_OSPEEDR12    ((uint32_t)0x03000000)\r
+#define GPIO_OSPEEDER_OSPEEDR12_0  ((uint32_t)0x01000000)\r
+#define GPIO_OSPEEDER_OSPEEDR12_1  ((uint32_t)0x02000000)\r
+#define GPIO_OSPEEDER_OSPEEDR13    ((uint32_t)0x0C000000)\r
+#define GPIO_OSPEEDER_OSPEEDR13_0  ((uint32_t)0x04000000)\r
+#define GPIO_OSPEEDER_OSPEEDR13_1  ((uint32_t)0x08000000)\r
+#define GPIO_OSPEEDER_OSPEEDR14    ((uint32_t)0x30000000)\r
+#define GPIO_OSPEEDER_OSPEEDR14_0  ((uint32_t)0x10000000)\r
+#define GPIO_OSPEEDER_OSPEEDR14_1  ((uint32_t)0x20000000)\r
+#define GPIO_OSPEEDER_OSPEEDR15    ((uint32_t)0xC0000000)\r
+#define GPIO_OSPEEDER_OSPEEDR15_0  ((uint32_t)0x40000000)\r
+#define GPIO_OSPEEDER_OSPEEDR15_1  ((uint32_t)0x80000000)\r
+\r
+/*******************  Bit definition for GPIO_PUPDR register  *****************/  \r
+#define GPIO_PUPDR_PUPDR0          ((uint32_t)0x00000003)\r
+#define GPIO_PUPDR_PUPDR0_0        ((uint32_t)0x00000001)\r
+#define GPIO_PUPDR_PUPDR0_1        ((uint32_t)0x00000002)\r
+#define GPIO_PUPDR_PUPDR1          ((uint32_t)0x0000000C)\r
+#define GPIO_PUPDR_PUPDR1_0        ((uint32_t)0x00000004)\r
+#define GPIO_PUPDR_PUPDR1_1        ((uint32_t)0x00000008)\r
+#define GPIO_PUPDR_PUPDR2          ((uint32_t)0x00000030)\r
+#define GPIO_PUPDR_PUPDR2_0        ((uint32_t)0x00000010)\r
+#define GPIO_PUPDR_PUPDR2_1        ((uint32_t)0x00000020)\r
+#define GPIO_PUPDR_PUPDR3          ((uint32_t)0x000000C0)\r
+#define GPIO_PUPDR_PUPDR3_0        ((uint32_t)0x00000040)\r
+#define GPIO_PUPDR_PUPDR3_1        ((uint32_t)0x00000080)\r
+#define GPIO_PUPDR_PUPDR4          ((uint32_t)0x00000300)\r
+#define GPIO_PUPDR_PUPDR4_0        ((uint32_t)0x00000100)\r
+#define GPIO_PUPDR_PUPDR4_1        ((uint32_t)0x00000200)\r
+#define GPIO_PUPDR_PUPDR5          ((uint32_t)0x00000C00)\r
+#define GPIO_PUPDR_PUPDR5_0        ((uint32_t)0x00000400)\r
+#define GPIO_PUPDR_PUPDR5_1        ((uint32_t)0x00000800)\r
+#define GPIO_PUPDR_PUPDR6          ((uint32_t)0x00003000)\r
+#define GPIO_PUPDR_PUPDR6_0        ((uint32_t)0x00001000)\r
+#define GPIO_PUPDR_PUPDR6_1        ((uint32_t)0x00002000)\r
+#define GPIO_PUPDR_PUPDR7          ((uint32_t)0x0000C000)\r
+#define GPIO_PUPDR_PUPDR7_0        ((uint32_t)0x00004000)\r
+#define GPIO_PUPDR_PUPDR7_1        ((uint32_t)0x00008000)\r
+#define GPIO_PUPDR_PUPDR8          ((uint32_t)0x00030000)\r
+#define GPIO_PUPDR_PUPDR8_0        ((uint32_t)0x00010000)\r
+#define GPIO_PUPDR_PUPDR8_1        ((uint32_t)0x00020000)\r
+#define GPIO_PUPDR_PUPDR9          ((uint32_t)0x000C0000)\r
+#define GPIO_PUPDR_PUPDR9_0        ((uint32_t)0x00040000)\r
+#define GPIO_PUPDR_PUPDR9_1        ((uint32_t)0x00080000)\r
+#define GPIO_PUPDR_PUPDR10         ((uint32_t)0x00300000)\r
+#define GPIO_PUPDR_PUPDR10_0       ((uint32_t)0x00100000)\r
+#define GPIO_PUPDR_PUPDR10_1       ((uint32_t)0x00200000)\r
+#define GPIO_PUPDR_PUPDR11         ((uint32_t)0x00C00000)\r
+#define GPIO_PUPDR_PUPDR11_0       ((uint32_t)0x00400000)\r
+#define GPIO_PUPDR_PUPDR11_1       ((uint32_t)0x00800000)\r
+#define GPIO_PUPDR_PUPDR12         ((uint32_t)0x03000000)\r
+#define GPIO_PUPDR_PUPDR12_0       ((uint32_t)0x01000000)\r
+#define GPIO_PUPDR_PUPDR12_1       ((uint32_t)0x02000000)\r
+#define GPIO_PUPDR_PUPDR13         ((uint32_t)0x0C000000)\r
+#define GPIO_PUPDR_PUPDR13_0       ((uint32_t)0x04000000)\r
+#define GPIO_PUPDR_PUPDR13_1       ((uint32_t)0x08000000)\r
+#define GPIO_PUPDR_PUPDR14         ((uint32_t)0x30000000)\r
+#define GPIO_PUPDR_PUPDR14_0       ((uint32_t)0x10000000)\r
+#define GPIO_PUPDR_PUPDR14_1       ((uint32_t)0x20000000)\r
+#define GPIO_PUPDR_PUPDR15         ((uint32_t)0xC0000000)\r
+#define GPIO_PUPDR_PUPDR15_0       ((uint32_t)0x40000000)\r
+#define GPIO_PUPDR_PUPDR15_1       ((uint32_t)0x80000000)\r
+\r
+/*******************  Bit definition for GPIO_IDR register  *******************/  \r
+#define GPIO_OTYPER_IDR_0          ((uint32_t)0x00000001)\r
+#define GPIO_OTYPER_IDR_1          ((uint32_t)0x00000002)\r
+#define GPIO_OTYPER_IDR_2          ((uint32_t)0x00000004)\r
+#define GPIO_OTYPER_IDR_3          ((uint32_t)0x00000008)\r
+#define GPIO_OTYPER_IDR_4          ((uint32_t)0x00000010)\r
+#define GPIO_OTYPER_IDR_5          ((uint32_t)0x00000020)\r
+#define GPIO_OTYPER_IDR_6          ((uint32_t)0x00000040)\r
+#define GPIO_OTYPER_IDR_7          ((uint32_t)0x00000080)\r
+#define GPIO_OTYPER_IDR_8          ((uint32_t)0x00000100)\r
+#define GPIO_OTYPER_IDR_9          ((uint32_t)0x00000200)\r
+#define GPIO_OTYPER_IDR_10         ((uint32_t)0x00000400)\r
+#define GPIO_OTYPER_IDR_11         ((uint32_t)0x00000800)\r
+#define GPIO_OTYPER_IDR_12         ((uint32_t)0x00001000)\r
+#define GPIO_OTYPER_IDR_13         ((uint32_t)0x00002000)\r
+#define GPIO_OTYPER_IDR_14         ((uint32_t)0x00004000)\r
+#define GPIO_OTYPER_IDR_15         ((uint32_t)0x00008000)\r
+\r
+/*******************  Bit definition for GPIO_ODR register  *******************/   \r
+#define GPIO_OTYPER_ODR_0          ((uint32_t)0x00000001)\r
+#define GPIO_OTYPER_ODR_1          ((uint32_t)0x00000002)\r
+#define GPIO_OTYPER_ODR_2          ((uint32_t)0x00000004)\r
+#define GPIO_OTYPER_ODR_3          ((uint32_t)0x00000008)\r
+#define GPIO_OTYPER_ODR_4          ((uint32_t)0x00000010)\r
+#define GPIO_OTYPER_ODR_5          ((uint32_t)0x00000020)\r
+#define GPIO_OTYPER_ODR_6          ((uint32_t)0x00000040)\r
+#define GPIO_OTYPER_ODR_7          ((uint32_t)0x00000080)\r
+#define GPIO_OTYPER_ODR_8          ((uint32_t)0x00000100)\r
+#define GPIO_OTYPER_ODR_9          ((uint32_t)0x00000200)\r
+#define GPIO_OTYPER_ODR_10         ((uint32_t)0x00000400)\r
+#define GPIO_OTYPER_ODR_11         ((uint32_t)0x00000800)\r
+#define GPIO_OTYPER_ODR_12         ((uint32_t)0x00001000)\r
+#define GPIO_OTYPER_ODR_13         ((uint32_t)0x00002000)\r
+#define GPIO_OTYPER_ODR_14         ((uint32_t)0x00004000)\r
+#define GPIO_OTYPER_ODR_15         ((uint32_t)0x00008000)\r
+\r
+/*******************  Bit definition for GPIO_BSRR register  ******************/  \r
+#define GPIO_BSRR_BS_0             ((uint32_t)0x00000001)\r
+#define GPIO_BSRR_BS_1             ((uint32_t)0x00000002)\r
+#define GPIO_BSRR_BS_2             ((uint32_t)0x00000004)\r
+#define GPIO_BSRR_BS_3             ((uint32_t)0x00000008)\r
+#define GPIO_BSRR_BS_4             ((uint32_t)0x00000010)\r
+#define GPIO_BSRR_BS_5             ((uint32_t)0x00000020)\r
+#define GPIO_BSRR_BS_6             ((uint32_t)0x00000040)\r
+#define GPIO_BSRR_BS_7             ((uint32_t)0x00000080)\r
+#define GPIO_BSRR_BS_8             ((uint32_t)0x00000100)\r
+#define GPIO_BSRR_BS_9             ((uint32_t)0x00000200)\r
+#define GPIO_BSRR_BS_10            ((uint32_t)0x00000400)\r
+#define GPIO_BSRR_BS_11            ((uint32_t)0x00000800)\r
+#define GPIO_BSRR_BS_12            ((uint32_t)0x00001000)\r
+#define GPIO_BSRR_BS_13            ((uint32_t)0x00002000)\r
+#define GPIO_BSRR_BS_14            ((uint32_t)0x00004000)\r
+#define GPIO_BSRR_BS_15            ((uint32_t)0x00008000)\r
+#define GPIO_BSRR_BR_0             ((uint32_t)0x00010000)\r
+#define GPIO_BSRR_BR_1             ((uint32_t)0x00020000)\r
+#define GPIO_BSRR_BR_2             ((uint32_t)0x00040000)\r
+#define GPIO_BSRR_BR_3             ((uint32_t)0x00080000)\r
+#define GPIO_BSRR_BR_4             ((uint32_t)0x00100000)\r
+#define GPIO_BSRR_BR_5             ((uint32_t)0x00200000)\r
+#define GPIO_BSRR_BR_6             ((uint32_t)0x00400000)\r
+#define GPIO_BSRR_BR_7             ((uint32_t)0x00800000)\r
+#define GPIO_BSRR_BR_8             ((uint32_t)0x01000000)\r
+#define GPIO_BSRR_BR_9             ((uint32_t)0x02000000)\r
+#define GPIO_BSRR_BR_10            ((uint32_t)0x04000000)\r
+#define GPIO_BSRR_BR_11            ((uint32_t)0x08000000)\r
+#define GPIO_BSRR_BR_12            ((uint32_t)0x10000000)\r
+#define GPIO_BSRR_BR_13            ((uint32_t)0x20000000)\r
+#define GPIO_BSRR_BR_14            ((uint32_t)0x40000000)\r
+#define GPIO_BSRR_BR_15            ((uint32_t)0x80000000)\r
+\r
+/******************************************************************************/\r
+/*                                                                            */\r
+/*                      Inter-integrated Circuit Interface                    */\r
+/*                                                                            */\r
+/******************************************************************************/\r
+\r
+/*******************  Bit definition for I2C_CR1 register  ********************/\r
+#define  I2C_CR1_PE                          ((uint16_t)0x0001)            /*!< Peripheral Enable */\r
+#define  I2C_CR1_SMBUS                       ((uint16_t)0x0002)            /*!< SMBus Mode */\r
+#define  I2C_CR1_SMBTYPE                     ((uint16_t)0x0008)            /*!< SMBus Type */\r
+#define  I2C_CR1_ENARP                       ((uint16_t)0x0010)            /*!< ARP Enable */\r
+#define  I2C_CR1_ENPEC                       ((uint16_t)0x0020)            /*!< PEC Enable */\r
+#define  I2C_CR1_ENGC                        ((uint16_t)0x0040)            /*!< General Call Enable */\r
+#define  I2C_CR1_NOSTRETCH                   ((uint16_t)0x0080)            /*!< Clock Stretching Disable (Slave mode) */\r
+#define  I2C_CR1_START                       ((uint16_t)0x0100)            /*!< Start Generation */\r
+#define  I2C_CR1_STOP                        ((uint16_t)0x0200)            /*!< Stop Generation */\r
+#define  I2C_CR1_ACK                         ((uint16_t)0x0400)            /*!< Acknowledge Enable */\r
+#define  I2C_CR1_POS                         ((uint16_t)0x0800)            /*!< Acknowledge/PEC Position (for data reception) */\r
+#define  I2C_CR1_PEC                         ((uint16_t)0x1000)            /*!< Packet Error Checking */\r
+#define  I2C_CR1_ALERT                       ((uint16_t)0x2000)            /*!< SMBus Alert */\r
+#define  I2C_CR1_SWRST                       ((uint16_t)0x8000)            /*!< Software Reset */\r
+\r
+/*******************  Bit definition for I2C_CR2 register  ********************/\r
+#define  I2C_CR2_FREQ                        ((uint16_t)0x003F)            /*!< FREQ[5:0] bits (Peripheral Clock Frequency) */\r
+#define  I2C_CR2_FREQ_0                      ((uint16_t)0x0001)            /*!< Bit 0 */\r
+#define  I2C_CR2_FREQ_1                      ((uint16_t)0x0002)            /*!< Bit 1 */\r
+#define  I2C_CR2_FREQ_2                      ((uint16_t)0x0004)            /*!< Bit 2 */\r
+#define  I2C_CR2_FREQ_3                      ((uint16_t)0x0008)            /*!< Bit 3 */\r
+#define  I2C_CR2_FREQ_4                      ((uint16_t)0x0010)            /*!< Bit 4 */\r
+#define  I2C_CR2_FREQ_5                      ((uint16_t)0x0020)            /*!< Bit 5 */\r
+\r
+#define  I2C_CR2_ITERREN                     ((uint16_t)0x0100)            /*!< Error Interrupt Enable */\r
+#define  I2C_CR2_ITEVTEN                     ((uint16_t)0x0200)            /*!< Event Interrupt Enable */\r
+#define  I2C_CR2_ITBUFEN                     ((uint16_t)0x0400)            /*!< Buffer Interrupt Enable */\r
+#define  I2C_CR2_DMAEN                       ((uint16_t)0x0800)            /*!< DMA Requests Enable */\r
+#define  I2C_CR2_LAST                        ((uint16_t)0x1000)            /*!< DMA Last Transfer */\r
+\r
+/*******************  Bit definition for I2C_OAR1 register  *******************/\r
+#define  I2C_OAR1_ADD1_7                     ((uint16_t)0x00FE)            /*!< Interface Address */\r
+#define  I2C_OAR1_ADD8_9                     ((uint16_t)0x0300)            /*!< Interface Address */\r
+\r
+#define  I2C_OAR1_ADD0                       ((uint16_t)0x0001)            /*!< Bit 0 */\r
+#define  I2C_OAR1_ADD1                       ((uint16_t)0x0002)            /*!< Bit 1 */\r
+#define  I2C_OAR1_ADD2                       ((uint16_t)0x0004)            /*!< Bit 2 */\r
+#define  I2C_OAR1_ADD3                       ((uint16_t)0x0008)            /*!< Bit 3 */\r
+#define  I2C_OAR1_ADD4                       ((uint16_t)0x0010)            /*!< Bit 4 */\r
+#define  I2C_OAR1_ADD5                       ((uint16_t)0x0020)            /*!< Bit 5 */\r
+#define  I2C_OAR1_ADD6                       ((uint16_t)0x0040)            /*!< Bit 6 */\r
+#define  I2C_OAR1_ADD7                       ((uint16_t)0x0080)            /*!< Bit 7 */\r
+#define  I2C_OAR1_ADD8                       ((uint16_t)0x0100)            /*!< Bit 8 */\r
+#define  I2C_OAR1_ADD9                       ((uint16_t)0x0200)            /*!< Bit 9 */\r
+\r
+#define  I2C_OAR1_ADDMODE                    ((uint16_t)0x8000)            /*!< Addressing Mode (Slave mode) */\r
+\r
+/*******************  Bit definition for I2C_OAR2 register  *******************/\r
+#define  I2C_OAR2_ENDUAL                     ((uint8_t)0x01)               /*!< Dual addressing mode enable */\r
+#define  I2C_OAR2_ADD2                       ((uint8_t)0xFE)               /*!< Interface address */\r
+\r
+/********************  Bit definition for I2C_DR register  ********************/\r
+#define  I2C_DR_DR                           ((uint8_t)0xFF)               /*!< 8-bit Data Register */\r
+\r
+/*******************  Bit definition for I2C_SR1 register  ********************/\r
+#define  I2C_SR1_SB                          ((uint16_t)0x0001)            /*!< Start Bit (Master mode) */\r
+#define  I2C_SR1_ADDR                        ((uint16_t)0x0002)            /*!< Address sent (master mode)/matched (slave mode) */\r
+#define  I2C_SR1_BTF                         ((uint16_t)0x0004)            /*!< Byte Transfer Finished */\r
+#define  I2C_SR1_ADD10                       ((uint16_t)0x0008)            /*!< 10-bit header sent (Master mode) */\r
+#define  I2C_SR1_STOPF                       ((uint16_t)0x0010)            /*!< Stop detection (Slave mode) */\r
+#define  I2C_SR1_RXNE                        ((uint16_t)0x0040)            /*!< Data Register not Empty (receivers) */\r
+#define  I2C_SR1_TXE                         ((uint16_t)0x0080)            /*!< Data Register Empty (transmitters) */\r
+#define  I2C_SR1_BERR                        ((uint16_t)0x0100)            /*!< Bus Error */\r
+#define  I2C_SR1_ARLO                        ((uint16_t)0x0200)            /*!< Arbitration Lost (master mode) */\r
+#define  I2C_SR1_AF                          ((uint16_t)0x0400)            /*!< Acknowledge Failure */\r
+#define  I2C_SR1_OVR                         ((uint16_t)0x0800)            /*!< Overrun/Underrun */\r
+#define  I2C_SR1_PECERR                      ((uint16_t)0x1000)            /*!< PEC Error in reception */\r
+#define  I2C_SR1_TIMEOUT                     ((uint16_t)0x4000)            /*!< Timeout or Tlow Error */\r
+#define  I2C_SR1_SMBALERT                    ((uint16_t)0x8000)            /*!< SMBus Alert */\r
+\r
+/*******************  Bit definition for I2C_SR2 register  ********************/\r
+#define  I2C_SR2_MSL                         ((uint16_t)0x0001)            /*!< Master/Slave */\r
+#define  I2C_SR2_BUSY                        ((uint16_t)0x0002)            /*!< Bus Busy */\r
+#define  I2C_SR2_TRA                         ((uint16_t)0x0004)            /*!< Transmitter/Receiver */\r
+#define  I2C_SR2_GENCALL                     ((uint16_t)0x0010)            /*!< General Call Address (Slave mode) */\r
+#define  I2C_SR2_SMBDEFAULT                  ((uint16_t)0x0020)            /*!< SMBus Device Default Address (Slave mode) */\r
+#define  I2C_SR2_SMBHOST                     ((uint16_t)0x0040)            /*!< SMBus Host Header (Slave mode) */\r
+#define  I2C_SR2_DUALF                       ((uint16_t)0x0080)            /*!< Dual Flag (Slave mode) */\r
+#define  I2C_SR2_PEC                         ((uint16_t)0xFF00)            /*!< Packet Error Checking Register */\r
+\r
+/*******************  Bit definition for I2C_CCR register  ********************/\r
+#define  I2C_CCR_CCR                         ((uint16_t)0x0FFF)            /*!< Clock Control Register in Fast/Standard mode (Master mode) */\r
+#define  I2C_CCR_DUTY                        ((uint16_t)0x4000)            /*!< Fast Mode Duty Cycle */\r
+#define  I2C_CCR_FS                          ((uint16_t)0x8000)            /*!< I2C Master Mode Selection */\r
+\r
+/******************  Bit definition for I2C_TRISE register  *******************/\r
+#define  I2C_TRISE_TRISE                     ((uint8_t)0x3F)               /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */\r
+\r
+/******************************************************************************/\r
+/*                                                                            */\r
+/*                           Independent WATCHDOG                             */\r
+/*                                                                            */\r
+/******************************************************************************/\r
+\r
+/*******************  Bit definition for IWDG_KR register  ********************/\r
+#define  IWDG_KR_KEY                         ((uint16_t)0xFFFF)            /*!< Key value (write only, read 0000h) */\r
+\r
+/*******************  Bit definition for IWDG_PR register  ********************/\r
+#define  IWDG_PR_PR                          ((uint8_t)0x07)               /*!< PR[2:0] (Prescaler divider) */\r
+#define  IWDG_PR_PR_0                        ((uint8_t)0x01)               /*!< Bit 0 */\r
+#define  IWDG_PR_PR_1                        ((uint8_t)0x02)               /*!< Bit 1 */\r
+#define  IWDG_PR_PR_2                        ((uint8_t)0x04)               /*!< Bit 2 */\r
+\r
+/*******************  Bit definition for IWDG_RLR register  *******************/\r
+#define  IWDG_RLR_RL                         ((uint16_t)0x0FFF)            /*!< Watchdog counter reload value */\r
+\r
+/*******************  Bit definition for IWDG_SR register  ********************/\r
+#define  IWDG_SR_PVU                         ((uint8_t)0x01)               /*!< Watchdog prescaler value update */\r
+#define  IWDG_SR_RVU                         ((uint8_t)0x02)               /*!< Watchdog counter reload value update */\r
+\r
+/******************************************************************************/\r
+/*                                                                            */\r
+/*                                    LCD                                     */\r
+/*                                                                            */\r
+/******************************************************************************/\r
+\r
+/*******************  Bit definition for LCD_CR register  *********************/\r
+#define LCD_CR_LCDEN               ((uint32_t)0x00000001)     /*!< LCD Enable Bit */\r
+#define LCD_CR_VSEL                ((uint32_t)0x00000002)     /*!< Voltage source selector Bit */\r
+\r
+#define LCD_CR_DUTY                ((uint32_t)0x0000001C)     /*!< DUTY[2:0] bits (Duty selector) */\r
+#define LCD_CR_DUTY_0              ((uint32_t)0x00000004)     /*!< Duty selector Bit 0 */\r
+#define LCD_CR_DUTY_1              ((uint32_t)0x00000008)     /*!< Duty selector Bit 1 */\r
+#define LCD_CR_DUTY_2              ((uint32_t)0x00000010)     /*!< Duty selector Bit 2 */\r
+\r
+#define LCD_CR_BIAS                ((uint32_t)0x00000060)     /*!< BIAS[1:0] bits (Bias selector) */\r
+#define LCD_CR_BIAS_0              ((uint32_t)0x00000020)     /*!< Bias selector Bit 0 */\r
+#define LCD_CR_BIAS_1              ((uint32_t)0x00000040)     /*!< Bias selector Bit 1 */\r
+\r
+#define LCD_CR_MUX_SEG             ((uint32_t)0x00000080)     /*!< Mux Segment Enable Bit */\r
+\r
+/*******************  Bit definition for LCD_FCR register  ********************/\r
+#define LCD_FCR_HD                 ((uint32_t)0x00000001)     /*!< High Drive Enable Bit */\r
+#define LCD_FCR_SOFIE              ((uint32_t)0x00000002)     /*!< Start of Frame Interrupt Enable Bit */\r
+#define LCD_FCR_UDDIE              ((uint32_t)0x00000008)     /*!< Update Display Done Interrupt Enable Bit */\r
+\r
+#define LCD_FCR_PON                ((uint32_t)0x00000070)     /*!< PON[2:0] bits (Puls ON Duration) */\r
+#define LCD_FCR_PON_0              ((uint32_t)0x00000010)     /*!< Bit 0 */\r
+#define LCD_FCR_PON_1              ((uint32_t)0x00000020)     /*!< Bit 1 */\r
+#define LCD_FCR_PON_2              ((uint32_t)0x00000040)     /*!< Bit 2 */\r
+\r
+#define LCD_FCR_DEAD               ((uint32_t)0x00000380)     /*!< DEAD[2:0] bits (DEAD Time) */\r
+#define LCD_FCR_DEAD_0             ((uint32_t)0x00000080)     /*!< Bit 0 */\r
+#define LCD_FCR_DEAD_1             ((uint32_t)0x00000100)     /*!< Bit 1 */\r
+#define LCD_FCR_DEAD_2             ((uint32_t)0x00000200)     /*!< Bit 2 */\r
+\r
+#define LCD_FCR_CC                 ((uint32_t)0x00001C00)     /*!< CC[2:0] bits (Contrast Control) */\r
+#define LCD_FCR_CC_0               ((uint32_t)0x00000400)     /*!< Bit 0 */\r
+#define LCD_FCR_CC_1               ((uint32_t)0x00000800)     /*!< Bit 1 */\r
+#define LCD_FCR_CC_2               ((uint32_t)0x00001000)     /*!< Bit 2 */\r
+\r
+#define LCD_FCR_BLINKF             ((uint32_t)0x0000E000)     /*!< BLINKF[2:0] bits (Blink Frequency) */\r
+#define LCD_FCR_BLINKF_0           ((uint32_t)0x00002000)     /*!< Bit 0 */\r
+#define LCD_FCR_BLINKF_1           ((uint32_t)0x00004000)     /*!< Bit 1 */\r
+#define LCD_FCR_BLINKF_2           ((uint32_t)0x00008000)     /*!< Bit 2 */\r
+\r
+#define LCD_FCR_BLINK              ((uint32_t)0x00030000)     /*!< BLINK[1:0] bits (Blink Enable) */\r
+#define LCD_FCR_BLINK_0            ((uint32_t)0x00010000)     /*!< Bit 0 */\r
+#define LCD_FCR_BLINK_1            ((uint32_t)0x00020000)     /*!< Bit 1 */\r
+\r
+#define LCD_FCR_DIV                ((uint32_t)0x003C0000)     /*!< DIV[3:0] bits (Divider) */\r
+#define LCD_FCR_PS                 ((uint32_t)0x03C00000)     /*!< PS[3:0] bits (Prescaler) */\r
+\r
+/*******************  Bit definition for LCD_SR register  *********************/\r
+#define LCD_SR_ENS                 ((uint32_t)0x00000001)     /*!< LCD Enabled Bit */\r
+#define LCD_SR_SOF                 ((uint32_t)0x00000002)     /*!< Start Of Frame Flag Bit */\r
+#define LCD_SR_UDR                 ((uint32_t)0x00000004)     /*!< Update Display Request Bit */\r
+#define LCD_SR_UDD                 ((uint32_t)0x00000008)     /*!< Update Display Done Flag Bit */\r
+#define LCD_SR_RDY                 ((uint32_t)0x00000010)     /*!< Ready Flag Bit */\r
+#define LCD_SR_FCRSR               ((uint32_t)0x00000020)     /*!< LCD FCR Register Synchronization Flag Bit */\r
+\r
+/*******************  Bit definition for LCD_CLR register  ********************/\r
+#define LCD_CLR_SOFC               ((uint32_t)0x00000002)     /*!< Start Of Frame Flag Clear Bit */\r
+#define LCD_CLR_UDDC               ((uint32_t)0x00000008)     /*!< Update Display Done Flag Clear Bit */\r
+\r
+/*******************  Bit definition for LCD_RAM register  ********************/\r
+#define LCD_RAM_SEGMENT_DATA       ((uint32_t)0xFFFFFFFF)     /*!< Segment Data Bits */\r
+\r
+/******************************************************************************/\r
+/*                                                                            */\r
+/*                             Power Control                                  */\r
+/*                                                                            */\r
+/******************************************************************************/\r
+\r
+/********************  Bit definition for PWR_CR register  ********************/\r
+#define  PWR_CR_LPSDSR                       ((uint16_t)0x0001)     /*!< Low-power deepsleep/sleep/low power run */\r
+#define  PWR_CR_PDDS                         ((uint16_t)0x0002)     /*!< Power Down Deepsleep */\r
+#define  PWR_CR_CWUF                         ((uint16_t)0x0004)     /*!< Clear Wakeup Flag */\r
+#define  PWR_CR_CSBF                         ((uint16_t)0x0008)     /*!< Clear Standby Flag */\r
+#define  PWR_CR_PVDE                         ((uint16_t)0x0010)     /*!< Power Voltage Detector Enable */\r
+\r
+#define  PWR_CR_PLS                          ((uint16_t)0x00E0)     /*!< PLS[2:0] bits (PVD Level Selection) */\r
+#define  PWR_CR_PLS_0                        ((uint16_t)0x0020)     /*!< Bit 0 */\r
+#define  PWR_CR_PLS_1                        ((uint16_t)0x0040)     /*!< Bit 1 */\r
+#define  PWR_CR_PLS_2                        ((uint16_t)0x0080)     /*!< Bit 2 */\r
+\r
+/*!< PVD level configuration */\r
+#define  PWR_CR_PLS_LEV0                     ((uint16_t)0x0000)     /*!< PVD level 0 */\r
+#define  PWR_CR_PLS_LEV1                     ((uint16_t)0x0020)     /*!< PVD level 1 */\r
+#define  PWR_CR_PLS_LEV2                     ((uint16_t)0x0040)     /*!< PVD level 2 */\r
+#define  PWR_CR_PLS_LEV3                     ((uint16_t)0x0060)     /*!< PVD level 3 */\r
+#define  PWR_CR_PLS_LEV4                     ((uint16_t)0x0080)     /*!< PVD level 4 */\r
+#define  PWR_CR_PLS_LEV5                     ((uint16_t)0x00A0)     /*!< PVD level 5 */\r
+#define  PWR_CR_PLS_LEV6                     ((uint16_t)0x00C0)     /*!< PVD level 6 */\r
+#define  PWR_CR_PLS_LEV7                     ((uint16_t)0x00E0)     /*!< PVD level 7 */\r
+\r
+#define  PWR_CR_DBP                          ((uint16_t)0x0100)     /*!< Disable Backup Domain write protection */\r
+#define  PWR_CR_ULP                          ((uint16_t)0x0200)     /*!< Ultra Low Power mode */\r
+#define  PWR_CR_FWU                          ((uint16_t)0x0400)     /*!< Fast wakeup */\r
+\r
+#define  PWR_CR_VOS                          ((uint16_t)0x1800)     /*!< VOS[1:0] bits (Voltage scaling range selection) */\r
+#define  PWR_CR_VOS_0                        ((uint16_t)0x0800)     /*!< Bit 0 */\r
+#define  PWR_CR_VOS_1                        ((uint16_t)0x1000)     /*!< Bit 1 */\r
+#define  PWR_CR_LPRUN                        ((uint16_t)0x4000)     /*!< Low power run mode */\r
+\r
+/*******************  Bit definition for PWR_CSR register  ********************/\r
+#define  PWR_CSR_WUF                         ((uint16_t)0x0001)     /*!< Wakeup Flag */\r
+#define  PWR_CSR_SBF                         ((uint16_t)0x0002)     /*!< Standby Flag */\r
+#define  PWR_CSR_PVDO                        ((uint16_t)0x0004)     /*!< PVD Output */\r
+#define  PWR_CSR_VREFINTRDYF                 ((uint16_t)0x0008)     /*!< Internal voltage reference (VREFINT) ready flag */\r
+#define  PWR_CSR_VOSF                        ((uint16_t)0x0010)     /*!< Voltage Scaling select flag */\r
+#define  PWR_CSR_REGLPF                      ((uint16_t)0x0020)     /*!< Regulator LP flag */\r
+\r
+#define  PWR_CSR_EWUP1                       ((uint16_t)0x0100)     /*!< Enable WKUP pin 1 */\r
+#define  PWR_CSR_EWUP2                       ((uint16_t)0x0200)     /*!< Enable WKUP pin 2 */\r
+#define  PWR_CSR_EWUP3                       ((uint16_t)0x0400)     /*!< Enable WKUP pin 3 */\r
+\r
+/******************************************************************************/\r
+/*                                                                            */\r
+/*                         Reset and Clock Control                            */\r
+/*                                                                            */\r
+/******************************************************************************/\r
+/********************  Bit definition for RCC_CR register  ********************/\r
+#define  RCC_CR_HSION                        ((uint32_t)0x00000001)        /*!< Internal High Speed clock enable */\r
+#define  RCC_CR_HSIRDY                       ((uint32_t)0x00000002)        /*!< Internal High Speed clock ready flag */\r
+\r
+#define  RCC_CR_MSION                        ((uint32_t)0x00000100)        /*!< Internal Multi Speed clock enable */\r
+#define  RCC_CR_MSIRDY                       ((uint32_t)0x00000200)        /*!< Internal Multi Speed clock ready flag */\r
+\r
+#define  RCC_CR_HSEON                        ((uint32_t)0x00010000)        /*!< External High Speed clock enable */\r
+#define  RCC_CR_HSERDY                       ((uint32_t)0x00020000)        /*!< External High Speed clock ready flag */\r
+#define  RCC_CR_HSEBYP                       ((uint32_t)0x00040000)        /*!< External High Speed clock Bypass */\r
+\r
+#define  RCC_CR_PLLON                        ((uint32_t)0x01000000)        /*!< PLL enable */\r
+#define  RCC_CR_PLLRDY                       ((uint32_t)0x02000000)        /*!< PLL clock ready flag */\r
+#define  RCC_CR_CSSON                        ((uint32_t)0x10000000)        /*!< Clock Security System enable */\r
+\r
+#define  RCC_CR_RTCPRE                       ((uint32_t)0x60000000)        /*!< RTC/LCD Prescaler */\r
+#define  RCC_CR_RTCPRE_0                     ((uint32_t)0x20000000)        /*!< Bit0 */\r
+#define  RCC_CR_RTCPRE_1                     ((uint32_t)0x40000000)        /*!< Bit1 */\r
+\r
+/********************  Bit definition for RCC_ICSCR register  *****************/\r
+#define  RCC_ICSCR_HSICAL                    ((uint32_t)0x000000FF)        /*!< Internal High Speed clock Calibration */\r
+#define  RCC_ICSCR_HSITRIM                   ((uint32_t)0x00001F00)        /*!< Internal High Speed clock trimming */\r
+\r
+#define  RCC_ICSCR_MSIRANGE                  ((uint32_t)0x0000E000)        /*!< Internal Multi Speed clock Range */\r
+#define  RCC_ICSCR_MSIRANGE_64KHz            ((uint32_t)0x00000000)        /*!< Internal Multi Speed clock Range 64KHz */\r
+#define  RCC_ICSCR_MSIRANGE_128KHz           ((uint32_t)0x00002000)        /*!< Internal Multi Speed clock Range 128KHz */\r
+#define  RCC_ICSCR_MSIRANGE_256KHz           ((uint32_t)0x00004000)        /*!< Internal Multi Speed clock Range 256KHz */\r
+#define  RCC_ICSCR_MSIRANGE_512KHz           ((uint32_t)0x00006000)        /*!< Internal Multi Speed clock Range 512KHz */\r
+#define  RCC_ICSCR_MSIRANGE_1MHz             ((uint32_t)0x00008000)        /*!< Internal Multi Speed clock Range 1MHz */\r
+#define  RCC_ICSCR_MSIRANGE_2MHz             ((uint32_t)0x0000A000)        /*!< Internal Multi Speed clock Range 2MHz */\r
+#define  RCC_ICSCR_MSIRANGE_4MHz             ((uint32_t)0x0000C000)        /*!< Internal Multi Speed clock Range 4MHz */\r
+#define  RCC_ICSCR_MSICAL                    ((uint32_t)0x00FF0000)        /*!< Internal Multi Speed clock Calibration */\r
+#define  RCC_ICSCR_MSITRIM                   ((uint32_t)0xFF000000)        /*!< Internal Multi Speed clock trimming */\r
+\r
+/********************  Bit definition for RCC_CFGR register  ******************/\r
+#define  RCC_CFGR_SW                         ((uint32_t)0x00000003)        /*!< SW[1:0] bits (System clock Switch) */\r
+#define  RCC_CFGR_SW_0                       ((uint32_t)0x00000001)        /*!< Bit 0 */\r
+#define  RCC_CFGR_SW_1                       ((uint32_t)0x00000002)        /*!< Bit 1 */\r
+\r
+/*!< SW configuration */\r
+#define  RCC_CFGR_SW_MSI                     ((uint32_t)0x00000000)        /*!< MSI selected as system clock */\r
+#define  RCC_CFGR_SW_HSI                     ((uint32_t)0x00000001)        /*!< HSI selected as system clock */\r
+#define  RCC_CFGR_SW_HSE                     ((uint32_t)0x00000002)        /*!< HSE selected as system clock */\r
+#define  RCC_CFGR_SW_PLL                     ((uint32_t)0x00000003)        /*!< PLL selected as system clock */\r
+\r
+#define  RCC_CFGR_SWS                        ((uint32_t)0x0000000C)        /*!< SWS[1:0] bits (System Clock Switch Status) */\r
+#define  RCC_CFGR_SWS_0                      ((uint32_t)0x00000004)        /*!< Bit 0 */\r
+#define  RCC_CFGR_SWS_1                      ((uint32_t)0x00000008)        /*!< Bit 1 */\r
+\r
+/*!< SWS configuration */\r
+#define  RCC_CFGR_SWS_MSI                    ((uint32_t)0x00000000)        /*!< MSI oscillator used as system clock */\r
+#define  RCC_CFGR_SWS_HSI                    ((uint32_t)0x00000004)        /*!< HSI oscillator used as system clock */\r
+#define  RCC_CFGR_SWS_HSE                    ((uint32_t)0x00000008)        /*!< HSE oscillator used as system clock */\r
+#define  RCC_CFGR_SWS_PLL                    ((uint32_t)0x0000000C)        /*!< PLL used as system clock */\r
+\r
+#define  RCC_CFGR_HPRE                       ((uint32_t)0x000000F0)        /*!< HPRE[3:0] bits (AHB prescaler) */\r
+#define  RCC_CFGR_HPRE_0                     ((uint32_t)0x00000010)        /*!< Bit 0 */\r
+#define  RCC_CFGR_HPRE_1                     ((uint32_t)0x00000020)        /*!< Bit 1 */\r
+#define  RCC_CFGR_HPRE_2                     ((uint32_t)0x00000040)        /*!< Bit 2 */\r
+#define  RCC_CFGR_HPRE_3                     ((uint32_t)0x00000080)        /*!< Bit 3 */\r
+\r
+/*!< HPRE configuration */\r
+#define  RCC_CFGR_HPRE_DIV1                  ((uint32_t)0x00000000)        /*!< SYSCLK not divided */\r
+#define  RCC_CFGR_HPRE_DIV2                  ((uint32_t)0x00000080)        /*!< SYSCLK divided by 2 */\r
+#define  RCC_CFGR_HPRE_DIV4                  ((uint32_t)0x00000090)        /*!< SYSCLK divided by 4 */\r
+#define  RCC_CFGR_HPRE_DIV8                  ((uint32_t)0x000000A0)        /*!< SYSCLK divided by 8 */\r
+#define  RCC_CFGR_HPRE_DIV16                 ((uint32_t)0x000000B0)        /*!< SYSCLK divided by 16 */\r
+#define  RCC_CFGR_HPRE_DIV64                 ((uint32_t)0x000000C0)        /*!< SYSCLK divided by 64 */\r
+#define  RCC_CFGR_HPRE_DIV128                ((uint32_t)0x000000D0)        /*!< SYSCLK divided by 128 */\r
+#define  RCC_CFGR_HPRE_DIV256                ((uint32_t)0x000000E0)        /*!< SYSCLK divided by 256 */\r
+#define  RCC_CFGR_HPRE_DIV512                ((uint32_t)0x000000F0)        /*!< SYSCLK divided by 512 */\r
+\r
+#define  RCC_CFGR_PPRE1                      ((uint32_t)0x00000700)        /*!< PRE1[2:0] bits (APB1 prescaler) */\r
+#define  RCC_CFGR_PPRE1_0                    ((uint32_t)0x00000100)        /*!< Bit 0 */\r
+#define  RCC_CFGR_PPRE1_1                    ((uint32_t)0x00000200)        /*!< Bit 1 */\r
+#define  RCC_CFGR_PPRE1_2                    ((uint32_t)0x00000400)        /*!< Bit 2 */\r
+\r
+/*!< PPRE1 configuration */\r
+#define  RCC_CFGR_PPRE1_DIV1                 ((uint32_t)0x00000000)        /*!< HCLK not divided */\r
+#define  RCC_CFGR_PPRE1_DIV2                 ((uint32_t)0x00000400)        /*!< HCLK divided by 2 */\r
+#define  RCC_CFGR_PPRE1_DIV4                 ((uint32_t)0x00000500)        /*!< HCLK divided by 4 */\r
+#define  RCC_CFGR_PPRE1_DIV8                 ((uint32_t)0x00000600)        /*!< HCLK divided by 8 */\r
+#define  RCC_CFGR_PPRE1_DIV16                ((uint32_t)0x00000700)        /*!< HCLK divided by 16 */\r
+\r
+#define  RCC_CFGR_PPRE2                      ((uint32_t)0x00003800)        /*!< PRE2[2:0] bits (APB2 prescaler) */\r
+#define  RCC_CFGR_PPRE2_0                    ((uint32_t)0x00000800)        /*!< Bit 0 */\r
+#define  RCC_CFGR_PPRE2_1                    ((uint32_t)0x00001000)        /*!< Bit 1 */\r
+#define  RCC_CFGR_PPRE2_2                    ((uint32_t)0x00002000)        /*!< Bit 2 */\r
+\r
+/*!< PPRE2 configuration */\r
+#define  RCC_CFGR_PPRE2_DIV1                 ((uint32_t)0x00000000)        /*!< HCLK not divided */\r
+#define  RCC_CFGR_PPRE2_DIV2                 ((uint32_t)0x00002000)        /*!< HCLK divided by 2 */\r
+#define  RCC_CFGR_PPRE2_DIV4                 ((uint32_t)0x00002800)        /*!< HCLK divided by 4 */\r
+#define  RCC_CFGR_PPRE2_DIV8                 ((uint32_t)0x00003000)        /*!< HCLK divided by 8 */\r
+#define  RCC_CFGR_PPRE2_DIV16                ((uint32_t)0x00003800)        /*!< HCLK divided by 16 */\r
+\r
+/*!< PLL entry clock source*/\r
+#define  RCC_CFGR_PLLSRC                     ((uint32_t)0x00010000)        /*!< PLL entry clock source */\r
+\r
+#define  RCC_CFGR_PLLSRC_HSI                 ((uint32_t)0x00000000)        /*!< HSI as PLL entry clock source */\r
+#define  RCC_CFGR_PLLSRC_HSE                 ((uint32_t)0x00010000)        /*!< HSE as PLL entry clock source */\r
+\r
+\r
+#define  RCC_CFGR_PLLMUL                     ((uint32_t)0x003C0000)        /*!< PLLMUL[3:0] bits (PLL multiplication factor) */\r
+#define  RCC_CFGR_PLLMUL_0                   ((uint32_t)0x00040000)        /*!< Bit 0 */\r
+#define  RCC_CFGR_PLLMUL_1                   ((uint32_t)0x00080000)        /*!< Bit 1 */\r
+#define  RCC_CFGR_PLLMUL_2                   ((uint32_t)0x00100000)        /*!< Bit 2 */\r
+#define  RCC_CFGR_PLLMUL_3                   ((uint32_t)0x00200000)        /*!< Bit 3 */\r
+\r
+/*!< PLLMUL configuration */\r
+#define  RCC_CFGR_PLLMUL3                    ((uint32_t)0x00000000)        /*!< PLL input clock * 3 */\r
+#define  RCC_CFGR_PLLMUL4                    ((uint32_t)0x00040000)        /*!< PLL input clock * 4 */\r
+#define  RCC_CFGR_PLLMUL6                    ((uint32_t)0x00080000)        /*!< PLL input clock * 6 */\r
+#define  RCC_CFGR_PLLMUL8                    ((uint32_t)0x000C0000)        /*!< PLL input clock * 8 */\r
+#define  RCC_CFGR_PLLMUL12                   ((uint32_t)0x00100000)        /*!< PLL input clock * 12 */\r
+#define  RCC_CFGR_PLLMUL16                   ((uint32_t)0x00140000)        /*!< PLL input clock * 16 */\r
+#define  RCC_CFGR_PLLMUL24                   ((uint32_t)0x00180000)        /*!< PLL input clock * 24 */\r
+#define  RCC_CFGR_PLLMUL32                   ((uint32_t)0x001C0000)        /*!< PLL input clock * 32 */\r
+#define  RCC_CFGR_PLLMUL48                   ((uint32_t)0x00200000)        /*!< PLL input clock * 48 */\r
+\r
+/*!< PLLDIV configuration */\r
+#define  RCC_CFGR_PLLDIV                     ((uint32_t)0x00C00000)        /*!< PLLDIV[1:0] bits (PLL Output Division) */\r
+#define  RCC_CFGR_PLLDIV_0                   ((uint32_t)0x00400000)        /*!< Bit0 */\r
+#define  RCC_CFGR_PLLDIV_1                   ((uint32_t)0x00800000)        /*!< Bit1 */\r
+\r
+\r
+/*!< PLLDIV configuration */\r
+#define  RCC_CFGR_PLLDIV1                    ((uint32_t)0x00000000)        /*!< PLL clock output = CKVCO / 1 */\r
+#define  RCC_CFGR_PLLDIV2                    ((uint32_t)0x00400000)        /*!< PLL clock output = CKVCO / 2 */\r
+#define  RCC_CFGR_PLLDIV3                    ((uint32_t)0x00800000)        /*!< PLL clock output = CKVCO / 3 */\r
+#define  RCC_CFGR_PLLDIV4                    ((uint32_t)0x00C00000)        /*!< PLL clock output = CKVCO / 4 */\r
+\r
+\r
+#define  RCC_CFGR_MCOSEL                     ((uint32_t)0x07000000)        /*!< MCO[2:0] bits (Microcontroller Clock Output) */\r
+#define  RCC_CFGR_MCOSEL_0                   ((uint32_t)0x01000000)        /*!< Bit 0 */\r
+#define  RCC_CFGR_MCOSEL_1                   ((uint32_t)0x02000000)        /*!< Bit 1 */\r
+#define  RCC_CFGR_MCOSEL_2                   ((uint32_t)0x04000000)        /*!< Bit 2 */\r
+\r
+/*!< MCO configuration */\r
+#define  RCC_CFGR_MCO_NOCLOCK                ((uint32_t)0x00000000)        /*!< No clock */\r
+#define  RCC_CFGR_MCO_SYSCLK                 ((uint32_t)0x01000000)        /*!< System clock selected */\r
+#define  RCC_CFGR_MCO_HSI                    ((uint32_t)0x02000000)        /*!< Internal 16 MHz RC oscillator clock selected */\r
+#define  RCC_CFGR_MCO_MSI                    ((uint32_t)0x03000000)        /*!< Internal Medium Speed RC oscillator clock selected */\r
+#define  RCC_CFGR_MCO_HSE                    ((uint32_t)0x04000000)        /*!< External 1-25 MHz oscillator clock selected */\r
+#define  RCC_CFGR_MCO_PLL                    ((uint32_t)0x05000000)        /*!< PLL clock divided */\r
+#define  RCC_CFGR_MCO_LSI                    ((uint32_t)0x06000000)        /*!< LSI selected */\r
+#define  RCC_CFGR_MCO_LSE                    ((uint32_t)0x07000000)        /*!< LSE selected */\r
+\r
+#define  RCC_CFGR_MCOPRE                     ((uint32_t)0x70000000)        /*!< MCOPRE[2:0] bits (Microcontroller Clock Output Prescaler) */\r
+#define  RCC_CFGR_MCOPRE_0                   ((uint32_t)0x10000000)        /*!< Bit 0 */\r
+#define  RCC_CFGR_MCOPRE_1                   ((uint32_t)0x20000000)        /*!< Bit 1 */\r
+#define  RCC_CFGR_MCOPRE_2                   ((uint32_t)0x40000000)        /*!< Bit 2 */\r
+\r
+/*!< MCO Prescaler configuration */\r
+#define  RCC_CFGR_MCO_DIV1                   ((uint32_t)0x00000000)        /*!< MCO Clock divided by 1 */\r
+#define  RCC_CFGR_MCO_DIV2                   ((uint32_t)0x10000000)        /*!< MCO Clock divided by 2 */\r
+#define  RCC_CFGR_MCO_DIV4                   ((uint32_t)0x20000000)        /*!< MCO Clock divided by 4 */\r
+#define  RCC_CFGR_MCO_DIV8                   ((uint32_t)0x30000000)        /*!< MCO Clock divided by 8 */\r
+#define  RCC_CFGR_MCO_DIV16                  ((uint32_t)0x40000000)        /*!< MCO Clock divided by 16 */\r
+\r
+/*!<******************  Bit definition for RCC_CIR register  ********************/\r
+#define  RCC_CIR_LSIRDYF                     ((uint32_t)0x00000001)        /*!< LSI Ready Interrupt flag */\r
+#define  RCC_CIR_LSERDYF                     ((uint32_t)0x00000002)        /*!< LSE Ready Interrupt flag */\r
+#define  RCC_CIR_HSIRDYF                     ((uint32_t)0x00000004)        /*!< HSI Ready Interrupt flag */\r
+#define  RCC_CIR_HSERDYF                     ((uint32_t)0x00000008)        /*!< HSE Ready Interrupt flag */\r
+#define  RCC_CIR_PLLRDYF                     ((uint32_t)0x00000010)        /*!< PLL Ready Interrupt flag */\r
+#define  RCC_CIR_MSIRDYF                     ((uint32_t)0x00000020)        /*!< MSI Ready Interrupt flag */\r
+#define  RCC_CIR_CSSF                        ((uint32_t)0x00000080)        /*!< Clock Security System Interrupt flag */\r
+\r
+#define  RCC_CIR_LSIRDYIE                    ((uint32_t)0x00000100)        /*!< LSI Ready Interrupt Enable */\r
+#define  RCC_CIR_LSERDYIE                    ((uint32_t)0x00000200)        /*!< LSE Ready Interrupt Enable */\r
+#define  RCC_CIR_HSIRDYIE                    ((uint32_t)0x00000400)        /*!< HSI Ready Interrupt Enable */\r
+#define  RCC_CIR_HSERDYIE                    ((uint32_t)0x00000800)        /*!< HSE Ready Interrupt Enable */\r
+#define  RCC_CIR_PLLRDYIE                    ((uint32_t)0x00001000)        /*!< PLL Ready Interrupt Enable */\r
+#define  RCC_CIR_MSIRDYIE                    ((uint32_t)0x00002000)        /*!< MSI Ready Interrupt Enable */\r
+\r
+#define  RCC_CIR_LSIRDYC                     ((uint32_t)0x00010000)        /*!< LSI Ready Interrupt Clear */\r
+#define  RCC_CIR_LSERDYC                     ((uint32_t)0x00020000)        /*!< LSE Ready Interrupt Clear */\r
+#define  RCC_CIR_HSIRDYC                     ((uint32_t)0x00040000)        /*!< HSI Ready Interrupt Clear */\r
+#define  RCC_CIR_HSERDYC                     ((uint32_t)0x00080000)        /*!< HSE Ready Interrupt Clear */\r
+#define  RCC_CIR_PLLRDYC                     ((uint32_t)0x00100000)        /*!< PLL Ready Interrupt Clear */\r
+#define  RCC_CIR_MSIRDYC                     ((uint32_t)0x00200000)        /*!< MSI Ready Interrupt Clear */\r
+#define  RCC_CIR_CSSC                        ((uint32_t)0x00800000)        /*!< Clock Security System Interrupt Clear */\r
+\r
+\r
+/*****************  Bit definition for RCC_AHBRSTR register  ******************/\r
+#define  RCC_AHBRSTR_GPIOARST                ((uint32_t)0x00000001)        /*!< GPIO port A reset */\r
+#define  RCC_AHBRSTR_GPIOBRST                ((uint32_t)0x00000002)        /*!< GPIO port B reset */\r
+#define  RCC_AHBRSTR_GPIOCRST                ((uint32_t)0x00000004)        /*!< GPIO port C reset */\r
+#define  RCC_AHBRSTR_GPIODRST                ((uint32_t)0x00000008)        /*!< GPIO port D reset */\r
+#define  RCC_AHBRSTR_GPIOERST                ((uint32_t)0x00000010)        /*!< GPIO port E reset */\r
+#define  RCC_AHBRSTR_GPIOHRST                ((uint32_t)0x00000020)        /*!< GPIO port H reset */\r
+#define  RCC_AHBRSTR_CRCRST                  ((uint32_t)0x00001000)        /*!< CRC reset */\r
+#define  RCC_AHBRSTR_FLITFRST                ((uint32_t)0x00008000)        /*!< FLITF reset */\r
+#define  RCC_AHBRSTR_DMA1RST                 ((uint32_t)0x01000000)        /*!< DMA1 reset */\r
+ \r
+/*****************  Bit definition for RCC_APB2RSTR register  *****************/\r
+#define  RCC_APB2RSTR_SYSCFGRST              ((uint32_t)0x00000001)        /*!< System Configuration SYSCFG reset */\r
+#define  RCC_APB2RSTR_TIM9RST                ((uint32_t)0x00000004)        /*!< TIM9 reset */\r
+#define  RCC_APB2RSTR_TIM10RST               ((uint32_t)0x00000008)        /*!< TIM10 reset */\r
+#define  RCC_APB2RSTR_TIM11RST               ((uint32_t)0x00000010)        /*!< TIM11 reset */\r
+#define  RCC_APB2RSTR_ADC1RST                ((uint32_t)0x00000200)        /*!< ADC1 reset */\r
+#define  RCC_APB2RSTR_SPI1RST                ((uint32_t)0x00001000)        /*!< SPI1 reset */\r
+#define  RCC_APB2RSTR_USART1RST              ((uint32_t)0x00004000)        /*!< USART1 reset */\r
+\r
+/*****************  Bit definition for RCC_APB1RSTR register  *****************/\r
+#define  RCC_APB1RSTR_TIM2RST                ((uint32_t)0x00000001)        /*!< Timer 2 reset */\r
+#define  RCC_APB1RSTR_TIM3RST                ((uint32_t)0x00000002)        /*!< Timer 3 reset */\r
+#define  RCC_APB1RSTR_TIM4RST                ((uint32_t)0x00000004)        /*!< Timer 4 reset */\r
+#define  RCC_APB1RSTR_TIM6RST                ((uint32_t)0x00000010)        /*!< Timer 6 reset */\r
+#define  RCC_APB1RSTR_TIM7RST                ((uint32_t)0x00000020)        /*!< Timer 7 reset */\r
+#define  RCC_APB1RSTR_LCDRST                 ((uint32_t)0x00000200)        /*!< LCD reset */\r
+#define  RCC_APB1RSTR_WWDGRST                ((uint32_t)0x00000800)        /*!< Window Watchdog reset */\r
+#define  RCC_APB1RSTR_SPI2RST                ((uint32_t)0x00004000)        /*!< SPI 2 reset */\r
+#define  RCC_APB1RSTR_USART2RST              ((uint32_t)0x00020000)        /*!< USART 2 reset */\r
+#define  RCC_APB1RSTR_USART3RST              ((uint32_t)0x00040000)        /*!< RUSART 3 reset */\r
+#define  RCC_APB1RSTR_I2C1RST                ((uint32_t)0x00200000)        /*!< I2C 1 reset */\r
+#define  RCC_APB1RSTR_I2C2RST                ((uint32_t)0x00400000)        /*!< I2C 2 reset */\r
+#define  RCC_APB1RSTR_USBRST                 ((uint32_t)0x00800000)        /*!< USB reset */\r
+#define  RCC_APB1RSTR_PWRRST                 ((uint32_t)0x10000000)        /*!< Power interface reset */\r
+#define  RCC_APB1RSTR_DACRST                 ((uint32_t)0x20000000)        /*!< DAC interface reset */\r
+#define  RCC_APB1RSTR_COMPRST                ((uint32_t)0x80000000)        /*!< Comparator interface reset */\r
+\r
+/******************  Bit definition for RCC_AHBENR register  ******************/\r
+#define  RCC_AHBENR_GPIOAEN                  ((uint32_t)0x00000001)        /*!< GPIO port A clock enable */\r
+#define  RCC_AHBENR_GPIOBEN                  ((uint32_t)0x00000002)        /*!< GPIO port B clock enable */\r
+#define  RCC_AHBENR_GPIOCEN                  ((uint32_t)0x00000004)        /*!< GPIO port C clock enable */\r
+#define  RCC_AHBENR_GPIODEN                  ((uint32_t)0x00000008)        /*!< GPIO port D clock enable */\r
+#define  RCC_AHBENR_GPIOEEN                  ((uint32_t)0x00000010)        /*!< GPIO port E clock enable */\r
+#define  RCC_AHBENR_GPIOHEN                  ((uint32_t)0x00000020)        /*!< GPIO port H clock enable */\r
+#define  RCC_AHBENR_CRCEN                    ((uint32_t)0x00001000)        /*!< CRC clock enable */\r
+#define  RCC_AHBENR_FLITFEN                  ((uint32_t)0x00008000)        /*!< FLITF clock enable (has effect only when\r
+                                                                                the Flash memory is in power down mode) */\r
+#define  RCC_AHBENR_DMA1EN                   ((uint32_t)0x01000000)        /*!< DMA1 clock enable */\r
+\r
+\r
+/******************  Bit definition for RCC_APB2ENR register  *****************/\r
+#define  RCC_APB2ENR_SYSCFGEN                ((uint32_t)0x00000001)         /*!< System Configuration SYSCFG clock enable */\r
+#define  RCC_APB2ENR_TIM9EN                  ((uint32_t)0x00000004)         /*!< TIM9 interface clock enable */\r
+#define  RCC_APB2ENR_TIM10EN                 ((uint32_t)0x00000008)         /*!< TIM10 interface clock enable */\r
+#define  RCC_APB2ENR_TIM11EN                 ((uint32_t)0x00000010)         /*!< TIM11 Timer clock enable */\r
+#define  RCC_APB2ENR_ADC1EN                  ((uint32_t)0x00000200)         /*!< ADC1 clock enable */\r
+#define  RCC_APB2ENR_SPI1EN                  ((uint32_t)0x00001000)         /*!< SPI1 clock enable */\r
+#define  RCC_APB2ENR_USART1EN                ((uint32_t)0x00004000)         /*!< USART1 clock enable */\r
+\r
+\r
+/*****************  Bit definition for RCC_APB1ENR register  ******************/\r
+#define  RCC_APB1ENR_TIM2EN                  ((uint32_t)0x00000001)        /*!< Timer 2 clock enabled*/\r
+#define  RCC_APB1ENR_TIM3EN                  ((uint32_t)0x00000002)        /*!< Timer 3 clock enable */\r
+#define  RCC_APB1ENR_TIM4EN                  ((uint32_t)0x00000004)        /*!< Timer 4 clock enable */\r
+#define  RCC_APB1ENR_TIM6EN                  ((uint32_t)0x00000010)        /*!< Timer 6 clock enable */\r
+#define  RCC_APB1ENR_TIM7EN                  ((uint32_t)0x00000020)        /*!< Timer 7 clock enable */\r
+#define  RCC_APB1ENR_LCDEN                   ((uint32_t)0x00000200)        /*!< LCD clock enable */\r
+#define  RCC_APB1ENR_WWDGEN                  ((uint32_t)0x00000800)        /*!< Window Watchdog clock enable */\r
+#define  RCC_APB1ENR_SPI2EN                  ((uint32_t)0x00004000)        /*!< SPI 2 clock enable */\r
+#define  RCC_APB1ENR_USART2EN                ((uint32_t)0x00020000)        /*!< USART 2 clock enable */\r
+#define  RCC_APB1ENR_USART3EN                ((uint32_t)0x00040000)        /*!< USART 3 clock enable */\r
+#define  RCC_APB1ENR_I2C1EN                  ((uint32_t)0x00200000)        /*!< I2C 1 clock enable */\r
+#define  RCC_APB1ENR_I2C2EN                  ((uint32_t)0x00400000)        /*!< I2C 2 clock enable */\r
+#define  RCC_APB1ENR_USBEN                   ((uint32_t)0x00800000)        /*!< USB clock enable */\r
+#define  RCC_APB1ENR_PWREN                   ((uint32_t)0x10000000)        /*!< Power interface clock enable */\r
+#define  RCC_APB1ENR_DACEN                   ((uint32_t)0x20000000)        /*!< DAC interface clock enable */\r
+#define  RCC_APB1ENR_COMPEN                  ((uint32_t)0x80000000)        /*!< Comparator interface clock enable */\r
+\r
+/******************  Bit definition for RCC_AHBLPENR register  ****************/\r
+#define  RCC_AHBLPENR_GPIOALPEN              ((uint32_t)0x00000001)        /*!< GPIO port A clock enabled in sleep mode */\r
+#define  RCC_AHBLPENR_GPIOBLPEN              ((uint32_t)0x00000002)        /*!< GPIO port B clock enabled in sleep mode */\r
+#define  RCC_AHBLPENR_GPIOCLPEN              ((uint32_t)0x00000004)        /*!< GPIO port C clock enabled in sleep mode */\r
+#define  RCC_AHBLPENR_GPIODLPEN              ((uint32_t)0x00000008)        /*!< GPIO port D clock enabled in sleep mode */\r
+#define  RCC_AHBLPENR_GPIOELPEN              ((uint32_t)0x00000010)        /*!< GPIO port E clock enabled in sleep mode */\r
+#define  RCC_AHBLPENR_GPIOHLPEN              ((uint32_t)0x00000020)        /*!< GPIO port H clock enabled in sleep mode */\r
+#define  RCC_AHBLPENR_CRCLPEN                ((uint32_t)0x00001000)        /*!< CRC clock enabled in sleep mode */\r
+#define  RCC_AHBLPENR_FLITFLPEN              ((uint32_t)0x00008000)        /*!< Flash Interface clock enabled in sleep mode\r
+                                                                                (has effect only when the Flash memory is\r
+                                                                                 in power down mode) */\r
+#define  RCC_AHBLPENR_SRAMLPEN               ((uint32_t)0x00010000)        /*!< SRAM clock enabled in sleep mode */\r
+#define  RCC_AHBLPENR_DMA1LPEN               ((uint32_t)0x01000000)        /*!< DMA1 clock enabled in sleep mode */\r
+\r
+/******************  Bit definition for RCC_APB2LPENR register  ***************/\r
+#define  RCC_APB2LPENR_SYSCFGLPEN            ((uint32_t)0x00000001)         /*!< System Configuration SYSCFG clock enabled in sleep mode */\r
+#define  RCC_APB2LPENR_TIM9LPEN              ((uint32_t)0x00000004)         /*!< TIM9 interface clock enabled in sleep mode */\r
+#define  RCC_APB2LPENR_TIM10LPEN             ((uint32_t)0x00000008)         /*!< TIM10 interface clock enabled in sleep mode */\r
+#define  RCC_APB2LPENR_TIM11LPEN             ((uint32_t)0x00000010)         /*!< TIM11 Timer clock enabled in sleep mode */\r
+#define  RCC_APB2LPENR_ADC1LPEN              ((uint32_t)0x00000200)         /*!< ADC1 clock enabled in sleep mode */\r
+#define  RCC_APB2LPENR_SPI1LPEN              ((uint32_t)0x00001000)         /*!< SPI1 clock enabled in sleep mode */\r
+#define  RCC_APB2LPENR_USART1LPEN            ((uint32_t)0x00004000)         /*!< USART1 clock enabled in sleep mode */\r
+\r
+/*****************  Bit definition for RCC_APB1LPENR register  ****************/\r
+#define  RCC_APB1LPENR_TIM2LPEN              ((uint32_t)0x00000001)        /*!< Timer 2 clock enabled in sleep mode */\r
+#define  RCC_APB1LPENR_TIM3LPEN              ((uint32_t)0x00000002)        /*!< Timer 3 clock enabled in sleep mode */\r
+#define  RCC_APB1LPENR_TIM4LPEN              ((uint32_t)0x00000004)        /*!< Timer 4 clock enabled in sleep mode */\r
+#define  RCC_APB1LPENR_TIM6LPEN              ((uint32_t)0x00000010)        /*!< Timer 6 clock enabled in sleep mode */\r
+#define  RCC_APB1LPENR_TIM7LPEN              ((uint32_t)0x00000020)        /*!< Timer 7 clock enabled in sleep mode */\r
+#define  RCC_APB1LPENR_LCDLPEN               ((uint32_t)0x00000200)        /*!< LCD clock enabled in sleep mode */\r
+#define  RCC_APB1LPENR_WWDGLPEN              ((uint32_t)0x00000800)        /*!< Window Watchdog clock enabled in sleep mode */\r
+#define  RCC_APB1LPENR_SPI2LPEN              ((uint32_t)0x00004000)        /*!< SPI 2 clock enabled in sleep mode */\r
+#define  RCC_APB1LPENR_USART2LPEN            ((uint32_t)0x00020000)        /*!< USART 2 clock enabled in sleep mode */\r
+#define  RCC_APB1LPENR_USART3LPEN            ((uint32_t)0x00040000)        /*!< USART 3 clock enabled in sleep mode */\r
+#define  RCC_APB1LPENR_I2C1LPEN              ((uint32_t)0x00200000)        /*!< I2C 1 clock enabled in sleep mode */\r
+#define  RCC_APB1LPENR_I2C2LPEN              ((uint32_t)0x00400000)        /*!< I2C 2 clock enabled in sleep mode */\r
+#define  RCC_APB1LPENR_USBLPEN               ((uint32_t)0x00800000)        /*!< USB clock enabled in sleep mode */\r
+#define  RCC_APB1LPENR_PWRLPEN               ((uint32_t)0x10000000)        /*!< Power interface clock enabled in sleep mode */\r
+#define  RCC_APB1LPENR_DACLPEN               ((uint32_t)0x20000000)        /*!< DAC interface clock enabled in sleep mode */\r
+#define  RCC_APB1LPENR_COMPLPEN              ((uint32_t)0x80000000)        /*!< Comparator interface clock enabled in sleep mode*/\r
+\r
+/*******************  Bit definition for RCC_CSR register  ********************/\r
+#define  RCC_CSR_LSION                      ((uint32_t)0x00000001)        /*!< Internal Low Speed oscillator enable */\r
+#define  RCC_CSR_LSIRDY                     ((uint32_t)0x00000002)        /*!< Internal Low Speed oscillator Ready */\r
+\r
+#define  RCC_CSR_LSEON                      ((uint32_t)0x00000100)        /*!< External Low Speed oscillator enable */\r
+#define  RCC_CSR_LSERDY                     ((uint32_t)0x00000200)        /*!< External Low Speed oscillator Ready */\r
+#define  RCC_CSR_LSEBYP                     ((uint32_t)0x00000400)        /*!< External Low Speed oscillator Bypass */\r
+\r
+#define  RCC_CSR_RTCSEL                     ((uint32_t)0x00030000)        /*!< RTCSEL[1:0] bits (RTC clock source selection) */\r
+#define  RCC_CSR_RTCSEL_0                   ((uint32_t)0x00010000)        /*!< Bit 0 */\r
+#define  RCC_CSR_RTCSEL_1                   ((uint32_t)0x00020000)        /*!< Bit 1 */\r
+\r
+/*!< RTC congiguration */\r
+#define  RCC_CSR_RTCSEL_NOCLOCK             ((uint32_t)0x00000000)        /*!< No clock */\r
+#define  RCC_CSR_RTCSEL_LSE                 ((uint32_t)0x00010000)        /*!< LSE oscillator clock used as RTC clock */\r
+#define  RCC_CSR_RTCSEL_LSI                 ((uint32_t)0x00020000)        /*!< LSI oscillator clock used as RTC clock */\r
+#define  RCC_CSR_RTCSEL_HSE                 ((uint32_t)0x00030000)        /*!< HSE oscillator clock divided by 2, 4, 8 or 16 by RTCPRE used as RTC clock */\r
+\r
+#define  RCC_CSR_RTCEN                      ((uint32_t)0x00400000)        /*!< RTC clock enable */\r
+#define  RCC_CSR_RTCRST                     ((uint32_t)0x00800000)        /*!< RTC reset  */\r
+ \r
+#define  RCC_CSR_RMVF                       ((uint32_t)0x01000000)        /*!< Remove reset flag */\r
+#define  RCC_CSR_OBLRSTF                    ((uint32_t)0x02000000)        /*!< Option Bytes Loader reset flag */\r
+#define  RCC_CSR_PINRSTF                    ((uint32_t)0x04000000)        /*!< PIN reset flag */\r
+#define  RCC_CSR_PORRSTF                    ((uint32_t)0x08000000)        /*!< POR/PDR reset flag */\r
+#define  RCC_CSR_SFTRSTF                    ((uint32_t)0x10000000)        /*!< Software Reset flag */\r
+#define  RCC_CSR_IWDGRSTF                   ((uint32_t)0x20000000)        /*!< Independent Watchdog reset flag */\r
+#define  RCC_CSR_WWDGRSTF                   ((uint32_t)0x40000000)        /*!< Window watchdog reset flag */\r
+#define  RCC_CSR_LPWRRSTF                   ((uint32_t)0x80000000)        /*!< Low-Power reset flag */\r
+\r
+\r
+/******************************************************************************/\r
+/*                                                                            */\r
+/*                             Real-Time Clock                                */\r
+/*                                                                            */\r
+/******************************************************************************/\r
+/********************  Bits definition for RTC_TR register  *******************/\r
+#define RTC_TR_PM                            ((uint32_t)0x00400000)\r
+#define RTC_TR_HT                            ((uint32_t)0x00300000)\r
+#define RTC_TR_HT_0                          ((uint32_t)0x00100000)\r
+#define RTC_TR_HT_1                          ((uint32_t)0x00200000)\r
+#define RTC_TR_HU                            ((uint32_t)0x000F0000)\r
+#define RTC_TR_HU_0                          ((uint32_t)0x00010000)\r
+#define RTC_TR_HU_1                          ((uint32_t)0x00020000)\r
+#define RTC_TR_HU_2                          ((uint32_t)0x00040000)\r
+#define RTC_TR_HU_3                          ((uint32_t)0x00080000)\r
+#define RTC_TR_MNT                           ((uint32_t)0x00007000)\r
+#define RTC_TR_MNT_0                         ((uint32_t)0x00001000)\r
+#define RTC_TR_MNT_1                         ((uint32_t)0x00002000)\r
+#define RTC_TR_MNT_2                         ((uint32_t)0x00004000)\r
+#define RTC_TR_MNU                           ((uint32_t)0x00000F00)\r
+#define RTC_TR_MNU_0                         ((uint32_t)0x00000100)\r
+#define RTC_TR_MNU_1                         ((uint32_t)0x00000200)\r
+#define RTC_TR_MNU_2                         ((uint32_t)0x00000400)\r
+#define RTC_TR_MNU_3                         ((uint32_t)0x00000800)\r
+#define RTC_TR_ST                            ((uint32_t)0x00000070)\r
+#define RTC_TR_ST_0                          ((uint32_t)0x00000010)\r
+#define RTC_TR_ST_1                          ((uint32_t)0x00000020)\r
+#define RTC_TR_ST_2                          ((uint32_t)0x00000040)\r
+#define RTC_TR_SU                            ((uint32_t)0x0000000F)\r
+#define RTC_TR_SU_0                          ((uint32_t)0x00000001)\r
+#define RTC_TR_SU_1                          ((uint32_t)0x00000002)\r
+#define RTC_TR_SU_2                          ((uint32_t)0x00000004)\r
+#define RTC_TR_SU_3                          ((uint32_t)0x00000008)\r
+\r
+/********************  Bits definition for RTC_DR register  *******************/\r
+#define RTC_DR_YT                            ((uint32_t)0x00F00000)\r
+#define RTC_DR_YT_0                          ((uint32_t)0x00100000)\r
+#define RTC_DR_YT_1                          ((uint32_t)0x00200000)\r
+#define RTC_DR_YT_2                          ((uint32_t)0x00400000)\r
+#define RTC_DR_YT_3                          ((uint32_t)0x00800000)\r
+#define RTC_DR_YU                            ((uint32_t)0x000F0000)\r
+#define RTC_DR_YU_0                          ((uint32_t)0x00010000)\r
+#define RTC_DR_YU_1                          ((uint32_t)0x00020000)\r
+#define RTC_DR_YU_2                          ((uint32_t)0x00040000)\r
+#define RTC_DR_YU_3                          ((uint32_t)0x00080000)\r
+#define RTC_DR_WDU                           ((uint32_t)0x0000E000)\r
+#define RTC_DR_WDU_0                         ((uint32_t)0x00002000)\r
+#define RTC_DR_WDU_1                         ((uint32_t)0x00004000)\r
+#define RTC_DR_WDU_2                         ((uint32_t)0x00008000)\r
+#define RTC_DR_MT                            ((uint32_t)0x00001000)\r
+#define RTC_DR_MU                            ((uint32_t)0x00000F00)\r
+#define RTC_DR_MU_0                          ((uint32_t)0x00000100)\r
+#define RTC_DR_MU_1                          ((uint32_t)0x00000200)\r
+#define RTC_DR_MU_2                          ((uint32_t)0x00000400)\r
+#define RTC_DR_MU_3                          ((uint32_t)0x00000800)\r
+#define RTC_DR_DT                            ((uint32_t)0x00000030)\r
+#define RTC_DR_DT_0                          ((uint32_t)0x00000010)\r
+#define RTC_DR_DT_1                          ((uint32_t)0x00000020)\r
+#define RTC_DR_DU                            ((uint32_t)0x0000000F)\r
+#define RTC_DR_DU_0                          ((uint32_t)0x00000001)\r
+#define RTC_DR_DU_1                          ((uint32_t)0x00000002)\r
+#define RTC_DR_DU_2                          ((uint32_t)0x00000004)\r
+#define RTC_DR_DU_3                          ((uint32_t)0x00000008)\r
+\r
+/********************  Bits definition for RTC_CR register  *******************/\r
+#define RTC_CR_COE                           ((uint32_t)0x00800000)\r
+#define RTC_CR_OSEL                          ((uint32_t)0x00600000)\r
+#define RTC_CR_OSEL_0                        ((uint32_t)0x00200000)\r
+#define RTC_CR_OSEL_1                        ((uint32_t)0x00400000)\r
+#define RTC_CR_POL                           ((uint32_t)0x00100000)\r
+#define RTC_CR_BCK                           ((uint32_t)0x00040000)\r
+#define RTC_CR_SUB1H                         ((uint32_t)0x00020000)\r
+#define RTC_CR_ADD1H                         ((uint32_t)0x00010000)\r
+#define RTC_CR_TSIE                          ((uint32_t)0x00008000)\r
+#define RTC_CR_WUTIE                         ((uint32_t)0x00004000)\r
+#define RTC_CR_ALRBIE                        ((uint32_t)0x00002000)\r
+#define RTC_CR_ALRAIE                        ((uint32_t)0x00001000)\r
+#define RTC_CR_TSE                           ((uint32_t)0x00000800)\r
+#define RTC_CR_WUTE                          ((uint32_t)0x00000400)\r
+#define RTC_CR_ALRBE                         ((uint32_t)0x00000200)\r
+#define RTC_CR_ALRAE                         ((uint32_t)0x00000100)\r
+#define RTC_CR_DCE                           ((uint32_t)0x00000080)\r
+#define RTC_CR_FMT                           ((uint32_t)0x00000040)\r
+#define RTC_CR_REFCKON                       ((uint32_t)0x00000010)\r
+#define RTC_CR_TSEDGE                        ((uint32_t)0x00000008)\r
+#define RTC_CR_WUCKSEL                       ((uint32_t)0x00000007)\r
+#define RTC_CR_WUCKSEL_0                     ((uint32_t)0x00000001)\r
+#define RTC_CR_WUCKSEL_1                     ((uint32_t)0x00000002)\r
+#define RTC_CR_WUCKSEL_2                     ((uint32_t)0x00000004)\r
+\r
+/********************  Bits definition for RTC_ISR register  ******************/\r
+#define RTC_ISR_TAMPF                        ((uint32_t)0x00002000)\r
+#define RTC_ISR_TSOVF                        ((uint32_t)0x00001000)\r
+#define RTC_ISR_TSF                          ((uint32_t)0x00000800)\r
+#define RTC_ISR_WUTF                         ((uint32_t)0x00000400)\r
+#define RTC_ISR_ALRBF                        ((uint32_t)0x00000200)\r
+#define RTC_ISR_ALRAF                        ((uint32_t)0x00000100)\r
+#define RTC_ISR_INIT                         ((uint32_t)0x00000080)\r
+#define RTC_ISR_INITF                        ((uint32_t)0x00000040)\r
+#define RTC_ISR_RSF                          ((uint32_t)0x00000020)\r
+#define RTC_ISR_INITS                        ((uint32_t)0x00000010)\r
+#define RTC_ISR_WUTWF                        ((uint32_t)0x00000004)\r
+#define RTC_ISR_ALRBWF                       ((uint32_t)0x00000002)\r
+#define RTC_ISR_ALRAWF                       ((uint32_t)0x00000001)\r
+\r
+/********************  Bits definition for RTC_PRER register  *****************/\r
+#define RTC_PRER_PREDIV_A                    ((uint32_t)0x007F0000)\r
+#define RTC_PRER_PREDIV_S                    ((uint32_t)0x00001FFF)\r
+\r
+/********************  Bits definition for RTC_WUTR register  *****************/\r
+#define RTC_WUTR_WUT                         ((uint32_t)0x0000FFFF)\r
+\r
+/********************  Bits definition for RTC_CALIBR register  ***************/\r
+#define RTC_CALIBR_DCS                       ((uint32_t)0x00000080)\r
+#define RTC_CALIBR_DC                        ((uint32_t)0x0000001F)\r
+\r
+/********************  Bits definition for RTC_ALRMAR register  ***************/\r
+#define RTC_ALRMAR_MSK3                      ((uint32_t)0x80000000)\r
+#define RTC_ALRMAR_WDSEL                     ((uint32_t)0x40000000)\r
+#define RTC_ALRMAR_DT                        ((uint32_t)0x30000000)\r
+#define RTC_ALRMAR_DT_0                      ((uint32_t)0x10000000)\r
+#define RTC_ALRMAR_DT_1                      ((uint32_t)0x20000000)\r
+#define RTC_ALRMAR_DU                        ((uint32_t)0x0F000000)\r
+#define RTC_ALRMAR_DU_0                      ((uint32_t)0x01000000)\r
+#define RTC_ALRMAR_DU_1                      ((uint32_t)0x02000000)\r
+#define RTC_ALRMAR_DU_2                      ((uint32_t)0x04000000)\r
+#define RTC_ALRMAR_DU_3                      ((uint32_t)0x08000000)\r
+#define RTC_ALRMAR_MSK2                      ((uint32_t)0x00800000)\r
+#define RTC_ALRMAR_PM                        ((uint32_t)0x00400000)\r
+#define RTC_ALRMAR_HT                        ((uint32_t)0x00300000)\r
+#define RTC_ALRMAR_HT_0                      ((uint32_t)0x00100000)\r
+#define RTC_ALRMAR_HT_1                      ((uint32_t)0x00200000)\r
+#define RTC_ALRMAR_HU                        ((uint32_t)0x000F0000)\r
+#define RTC_ALRMAR_HU_0                      ((uint32_t)0x00010000)\r
+#define RTC_ALRMAR_HU_1                      ((uint32_t)0x00020000)\r
+#define RTC_ALRMAR_HU_2                      ((uint32_t)0x00040000)\r
+#define RTC_ALRMAR_HU_3                      ((uint32_t)0x00080000)\r
+#define RTC_ALRMAR_MSK1                      ((uint32_t)0x00008000)\r
+#define RTC_ALRMAR_MNT                       ((uint32_t)0x00007000)\r
+#define RTC_ALRMAR_MNT_0                     ((uint32_t)0x00001000)\r
+#define RTC_ALRMAR_MNT_1                     ((uint32_t)0x00002000)\r
+#define RTC_ALRMAR_MNT_2                     ((uint32_t)0x00004000)\r
+#define RTC_ALRMAR_MNU                       ((uint32_t)0x00000F00)\r
+#define RTC_ALRMAR_MNU_0                     ((uint32_t)0x00000100)\r
+#define RTC_ALRMAR_MNU_1                     ((uint32_t)0x00000200)\r
+#define RTC_ALRMAR_MNU_2                     ((uint32_t)0x00000400)\r
+#define RTC_ALRMAR_MNU_3                     ((uint32_t)0x00000800)\r
+#define RTC_ALRMAR_MSK0                      ((uint32_t)0x00000080)\r
+#define RTC_ALRMAR_ST                        ((uint32_t)0x00000070)\r
+#define RTC_ALRMAR_ST_0                      ((uint32_t)0x00000010)\r
+#define RTC_ALRMAR_ST_1                      ((uint32_t)0x00000020)\r
+#define RTC_ALRMAR_ST_2                      ((uint32_t)0x00000040)\r
+#define RTC_ALRMAR_SU                        ((uint32_t)0x0000000F)\r
+#define RTC_ALRMAR_SU_0                      ((uint32_t)0x00000001)\r
+#define RTC_ALRMAR_SU_1                      ((uint32_t)0x00000002)\r
+#define RTC_ALRMAR_SU_2                      ((uint32_t)0x00000004)\r
+#define RTC_ALRMAR_SU_3                      ((uint32_t)0x00000008)\r
+\r
+/********************  Bits definition for RTC_ALRMBR register  ***************/\r
+#define RTC_ALRMBR_MSK3                      ((uint32_t)0x80000000)\r
+#define RTC_ALRMBR_WDSEL                     ((uint32_t)0x40000000)\r
+#define RTC_ALRMBR_DT                        ((uint32_t)0x30000000)\r
+#define RTC_ALRMBR_DT_0                      ((uint32_t)0x10000000)\r
+#define RTC_ALRMBR_DT_1                      ((uint32_t)0x20000000)\r
+#define RTC_ALRMBR_DU                        ((uint32_t)0x0F000000)\r
+#define RTC_ALRMBR_DU_0                      ((uint32_t)0x01000000)\r
+#define RTC_ALRMBR_DU_1                      ((uint32_t)0x02000000)\r
+#define RTC_ALRMBR_DU_2                      ((uint32_t)0x04000000)\r
+#define RTC_ALRMBR_DU_3                      ((uint32_t)0x08000000)\r
+#define RTC_ALRMBR_MSK2                      ((uint32_t)0x00800000)\r
+#define RTC_ALRMBR_PM                        ((uint32_t)0x00400000)\r
+#define RTC_ALRMBR_HT                        ((uint32_t)0x00300000)\r
+#define RTC_ALRMBR_HT_0                      ((uint32_t)0x00100000)\r
+#define RTC_ALRMBR_HT_1                      ((uint32_t)0x00200000)\r
+#define RTC_ALRMBR_HU                        ((uint32_t)0x000F0000)\r
+#define RTC_ALRMBR_HU_0                      ((uint32_t)0x00010000)\r
+#define RTC_ALRMBR_HU_1                      ((uint32_t)0x00020000)\r
+#define RTC_ALRMBR_HU_2                      ((uint32_t)0x00040000)\r
+#define RTC_ALRMBR_HU_3                      ((uint32_t)0x00080000)\r
+#define RTC_ALRMBR_MSK1                      ((uint32_t)0x00008000)\r
+#define RTC_ALRMBR_MNT                       ((uint32_t)0x00007000)\r
+#define RTC_ALRMBR_MNT_0                     ((uint32_t)0x00001000)\r
+#define RTC_ALRMBR_MNT_1                     ((uint32_t)0x00002000)\r
+#define RTC_ALRMBR_MNT_2                     ((uint32_t)0x00004000)\r
+#define RTC_ALRMBR_MNU                       ((uint32_t)0x00000F00)\r
+#define RTC_ALRMBR_MNU_0                     ((uint32_t)0x00000100)\r
+#define RTC_ALRMBR_MNU_1                     ((uint32_t)0x00000200)\r
+#define RTC_ALRMBR_MNU_2                     ((uint32_t)0x00000400)\r
+#define RTC_ALRMBR_MNU_3                     ((uint32_t)0x00000800)\r
+#define RTC_ALRMBR_MSK0                      ((uint32_t)0x00000080)\r
+#define RTC_ALRMBR_ST                        ((uint32_t)0x00000070)\r
+#define RTC_ALRMBR_ST_0                      ((uint32_t)0x00000010)\r
+#define RTC_ALRMBR_ST_1                      ((uint32_t)0x00000020)\r
+#define RTC_ALRMBR_ST_2                      ((uint32_t)0x00000040)\r
+#define RTC_ALRMBR_SU                        ((uint32_t)0x0000000F)\r
+#define RTC_ALRMBR_SU_0                      ((uint32_t)0x00000001)\r
+#define RTC_ALRMBR_SU_1                      ((uint32_t)0x00000002)\r
+#define RTC_ALRMBR_SU_2                      ((uint32_t)0x00000004)\r
+#define RTC_ALRMBR_SU_3                      ((uint32_t)0x00000008)\r
+\r
+/********************  Bits definition for RTC_WRP register  ******************/\r
+#define RTC_WRP_KEY                          ((uint32_t)0x000000FF)\r
+\r
+/********************  Bits definition for RTC_TSTR register  *****************/\r
+#define RTC_TSTR_PM                          ((uint32_t)0x00400000)\r
+#define RTC_TSTR_HT                          ((uint32_t)0x00300000)\r
+#define RTC_TSTR_HT_0                        ((uint32_t)0x00100000)\r
+#define RTC_TSTR_HT_1                        ((uint32_t)0x00200000)\r
+#define RTC_TSTR_HU                          ((uint32_t)0x000F0000)\r
+#define RTC_TSTR_HU_0                        ((uint32_t)0x00010000)\r
+#define RTC_TSTR_HU_1                        ((uint32_t)0x00020000)\r
+#define RTC_TSTR_HU_2                        ((uint32_t)0x00040000)\r
+#define RTC_TSTR_HU_3                        ((uint32_t)0x00080000)\r
+#define RTC_TSTR_MNT                         ((uint32_t)0x00007000)\r
+#define RTC_TSTR_MNT_0                       ((uint32_t)0x00001000)\r
+#define RTC_TSTR_MNT_1                       ((uint32_t)0x00002000)\r
+#define RTC_TSTR_MNT_2                       ((uint32_t)0x00004000)\r
+#define RTC_TSTR_MNU                         ((uint32_t)0x00000F00)\r
+#define RTC_TSTR_MNU_0                       ((uint32_t)0x00000100)\r
+#define RTC_TSTR_MNU_1                       ((uint32_t)0x00000200)\r
+#define RTC_TSTR_MNU_2                       ((uint32_t)0x00000400)\r
+#define RTC_TSTR_MNU_3                       ((uint32_t)0x00000800)\r
+#define RTC_TSTR_ST                          ((uint32_t)0x00000070)\r
+#define RTC_TSTR_ST_0                        ((uint32_t)0x00000010)\r
+#define RTC_TSTR_ST_1                        ((uint32_t)0x00000020)\r
+#define RTC_TSTR_ST_2                        ((uint32_t)0x00000040)\r
+#define RTC_TSTR_SU                          ((uint32_t)0x0000000F)\r
+#define RTC_TSTR_SU_0                        ((uint32_t)0x00000001)\r
+#define RTC_TSTR_SU_1                        ((uint32_t)0x00000002)\r
+#define RTC_TSTR_SU_2                        ((uint32_t)0x00000004)\r
+#define RTC_TSTR_SU_3                        ((uint32_t)0x00000008)\r
+\r
+/********************  Bits definition for RTC_TSDR register  *****************/\r
+#define RTC_TSDR_WDU                         ((uint32_t)0x0000E000)\r
+#define RTC_TSDR_WDU_0                       ((uint32_t)0x00002000)\r
+#define RTC_TSDR_WDU_1                       ((uint32_t)0x00004000)\r
+#define RTC_TSDR_WDU_2                       ((uint32_t)0x00008000)\r
+#define RTC_TSDR_MT                          ((uint32_t)0x00001000)\r
+#define RTC_TSDR_MU                          ((uint32_t)0x00000F00)\r
+#define RTC_TSDR_MU_0                        ((uint32_t)0x00000100)\r
+#define RTC_TSDR_MU_1                        ((uint32_t)0x00000200)\r
+#define RTC_TSDR_MU_2                        ((uint32_t)0x00000400)\r
+#define RTC_TSDR_MU_3                        ((uint32_t)0x00000800)\r
+#define RTC_TSDR_DT                          ((uint32_t)0x00000030)\r
+#define RTC_TSDR_DT_0                        ((uint32_t)0x00000010)\r
+#define RTC_TSDR_DT_1                        ((uint32_t)0x00000020)\r
+#define RTC_TSDR_DU                          ((uint32_t)0x0000000F)\r
+#define RTC_TSDR_DU_0                        ((uint32_t)0x00000001)\r
+#define RTC_TSDR_DU_1                        ((uint32_t)0x00000002)\r
+#define RTC_TSDR_DU_2                        ((uint32_t)0x00000004)\r
+#define RTC_TSDR_DU_3                        ((uint32_t)0x00000008)\r
+\r
+/********************  Bits definition for RTC_TAFCR register  ****************/\r
+#define RTC_TAFCR_ALARMOUTTYPE               ((uint32_t)0x00040000)\r
+#define RTC_TAFCR_TAMPIE                     ((uint32_t)0x00000004)\r
+#define RTC_TAFCR_TAMPEDGE                   ((uint32_t)0x00000002)\r
+#define RTC_TAFCR_TAMPE                      ((uint32_t)0x00000001)\r
+\r
+/********************  Bits definition for RTC_BK0R register  *****************/\r
+#define RTC_BK0R_BCK                         ((uint32_t)0xFFFFFFFF)\r
+\r
+/********************  Bits definition for RTC_BK1R register  *****************/\r
+#define RTC_BK1R_BCK                         ((uint32_t)0xFFFFFFFF)\r
+\r
+/********************  Bits definition for RTC_BK2R register  *****************/\r
+#define RTC_BK2R_BCK                         ((uint32_t)0xFFFFFFFF)\r
+\r
+/********************  Bits definition for RTC_BK3R register  *****************/\r
+#define RTC_BK3R_BCK                         ((uint32_t)0xFFFFFFFF)\r
+\r
+/********************  Bits definition for RTC_BK4R register  *****************/\r
+#define RTC_BK4R_BCK                         ((uint32_t)0xFFFFFFFF)\r
+\r
+/********************  Bits definition for RTC_BK5R register  *****************/\r
+#define RTC_BK5R_BCK                         ((uint32_t)0xFFFFFFFF)\r
+\r
+/********************  Bits definition for RTC_BK6R register  *****************/\r
+#define RTC_BK6R_BCK                         ((uint32_t)0xFFFFFFFF)\r
+\r
+/********************  Bits definition for RTC_BK7R register  *****************/\r
+#define RTC_BK7R_BCK                         ((uint32_t)0xFFFFFFFF)\r
+\r
+/********************  Bits definition for RTC_BK8R register  *****************/\r
+#define RTC_BK8R_BCK                         ((uint32_t)0xFFFFFFFF)\r
+\r
+/********************  Bits definition for RTC_BK9R register  *****************/\r
+#define RTC_BK9R_BCK                         ((uint32_t)0xFFFFFFFF)\r
+\r
+/********************  Bits definition for RTC_BK10R register  ****************/\r
+#define RTC_BK10R_BCK                        ((uint32_t)0xFFFFFFFF)\r
+\r
+/********************  Bits definition for RTC_BK11R register  ****************/\r
+#define RTC_BK11R_BCK                        ((uint32_t)0xFFFFFFFF)\r
+\r
+/********************  Bits definition for RTC_BK12R register  ****************/\r
+#define RTC_BK12R_BCK                        ((uint32_t)0xFFFFFFFF)\r
+\r
+/********************  Bits definition for RTC_BK13R register  ****************/\r
+#define RTC_BK13R_BCK                        ((uint32_t)0xFFFFFFFF)\r
+\r
+/********************  Bits definition for RTC_BK14R register  ****************/\r
+#define RTC_BK14R_BCK                        ((uint32_t)0xFFFFFFFF)\r
+\r
+/********************  Bits definition for RTC_BK15R register  ****************/\r
+#define RTC_BK15R_BCK                        ((uint32_t)0xFFFFFFFF)\r
+\r
+/********************  Bits definition for RTC_BK16R register  ****************/\r
+#define RTC_BK16R_BCK                        ((uint32_t)0xFFFFFFFF)\r
+\r
+/********************  Bits definition for RTC_BK17R register  ****************/\r
+#define RTC_BK17R_BCK                        ((uint32_t)0xFFFFFFFF)\r
+\r
+/********************  Bits definition for RTC_BK18R register  ****************/\r
+#define RTC_BK18R_BCK                        ((uint32_t)0xFFFFFFFF)\r
+\r
+/********************  Bits definition for RTC_BK19R register  ****************/\r
+#define RTC_BK19R_BCK                        ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************************************************************************/\r
+/*                                                                            */\r
+/*                        Serial Peripheral Interface                         */\r
+/*                                                                            */\r
+/******************************************************************************/\r
+\r
+/*******************  Bit definition for SPI_CR1 register  ********************/\r
+#define  SPI_CR1_CPHA                        ((uint16_t)0x0001)            /*!< Clock Phase */\r
+#define  SPI_CR1_CPOL                        ((uint16_t)0x0002)            /*!< Clock Polarity */\r
+#define  SPI_CR1_MSTR                        ((uint16_t)0x0004)            /*!< Master Selection */\r
+\r
+#define  SPI_CR1_BR                          ((uint16_t)0x0038)            /*!< BR[2:0] bits (Baud Rate Control) */\r
+#define  SPI_CR1_BR_0                        ((uint16_t)0x0008)            /*!< Bit 0 */\r
+#define  SPI_CR1_BR_1                        ((uint16_t)0x0010)            /*!< Bit 1 */\r
+#define  SPI_CR1_BR_2                        ((uint16_t)0x0020)            /*!< Bit 2 */\r
+\r
+#define  SPI_CR1_SPE                         ((uint16_t)0x0040)            /*!< SPI Enable */\r
+#define  SPI_CR1_LSBFIRST                    ((uint16_t)0x0080)            /*!< Frame Format */\r
+#define  SPI_CR1_SSI                         ((uint16_t)0x0100)            /*!< Internal slave select */\r
+#define  SPI_CR1_SSM                         ((uint16_t)0x0200)            /*!< Software slave management */\r
+#define  SPI_CR1_RXONLY                      ((uint16_t)0x0400)            /*!< Receive only */\r
+#define  SPI_CR1_DFF                         ((uint16_t)0x0800)            /*!< Data Frame Format */\r
+#define  SPI_CR1_CRCNEXT                     ((uint16_t)0x1000)            /*!< Transmit CRC next */\r
+#define  SPI_CR1_CRCEN                       ((uint16_t)0x2000)            /*!< Hardware CRC calculation enable */\r
+#define  SPI_CR1_BIDIOE                      ((uint16_t)0x4000)            /*!< Output enable in bidirectional mode */\r
+#define  SPI_CR1_BIDIMODE                    ((uint16_t)0x8000)            /*!< Bidirectional data mode enable */\r
+\r
+/*******************  Bit definition for SPI_CR2 register  ********************/\r
+#define  SPI_CR2_RXDMAEN                     ((uint8_t)0x01)               /*!< Rx Buffer DMA Enable */\r
+#define  SPI_CR2_TXDMAEN                     ((uint8_t)0x02)               /*!< Tx Buffer DMA Enable */\r
+#define  SPI_CR2_SSOE                        ((uint8_t)0x04)               /*!< SS Output Enable */\r
+#define  SPI_CR2_ERRIE                       ((uint8_t)0x20)               /*!< Error Interrupt Enable */\r
+#define  SPI_CR2_RXNEIE                      ((uint8_t)0x40)               /*!< RX buffer Not Empty Interrupt Enable */\r
+#define  SPI_CR2_TXEIE                       ((uint8_t)0x80)               /*!< Tx buffer Empty Interrupt Enable */\r
+\r
+/********************  Bit definition for SPI_SR register  ********************/\r
+#define  SPI_SR_RXNE                         ((uint8_t)0x01)               /*!< Receive buffer Not Empty */\r
+#define  SPI_SR_TXE                          ((uint8_t)0x02)               /*!< Transmit buffer Empty */\r
+#define  SPI_SR_CRCERR                       ((uint8_t)0x10)               /*!< CRC Error flag */\r
+#define  SPI_SR_MODF                         ((uint8_t)0x20)               /*!< Mode fault */\r
+#define  SPI_SR_OVR                          ((uint8_t)0x40)               /*!< Overrun flag */\r
+#define  SPI_SR_BSY                          ((uint8_t)0x80)               /*!< Busy flag */\r
+\r
+/********************  Bit definition for SPI_DR register  ********************/\r
+#define  SPI_DR_DR                           ((uint16_t)0xFFFF)            /*!< Data Register */\r
+\r
+/*******************  Bit definition for SPI_CRCPR register  ******************/\r
+#define  SPI_CRCPR_CRCPOLY                   ((uint16_t)0xFFFF)            /*!< CRC polynomial register */\r
+\r
+/******************  Bit definition for SPI_RXCRCR register  ******************/\r
+#define  SPI_RXCRCR_RXCRC                    ((uint16_t)0xFFFF)            /*!< Rx CRC Register */\r
+\r
+/******************  Bit definition for SPI_TXCRCR register  ******************/\r
+#define  SPI_TXCRCR_TXCRC                    ((uint16_t)0xFFFF)            /*!< Tx CRC Register */\r
+\r
+/******************************************************************************/\r
+/*                                                                            */\r
+/*                       System Configuration (SYSCFG)                        */\r
+/*                                                                            */\r
+/******************************************************************************/\r
+/*****************  Bit definition for SYSCFG_MEMRMP register  ****************/\r
+#define SYSCFG_MEMRMP_MEM_MODE          ((uint32_t)0x00000003) /*!< SYSCFG_Memory Remap Config */\r
+#define SYSCFG_MEMRMP_MEM_MODE_0        ((uint32_t)0x00000001) /*!< Bit 0 */\r
+#define SYSCFG_MEMRMP_MEM_MODE_1        ((uint32_t)0x00000002) /*!< Bit 1 */\r
+\r
+/*****************  Bit definition for SYSCFG_PMC register  *******************/\r
+#define SYSCFG_PMC_USB_PU               ((uint32_t)0x00000001) /*!< SYSCFG PMC */\r
+\r
+/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/\r
+#define SYSCFG_EXTICR1_EXTI0            ((uint16_t)0x000F) /*!< EXTI 0 configuration */\r
+#define SYSCFG_EXTICR1_EXTI1            ((uint16_t)0x00F0) /*!< EXTI 1 configuration */\r
+#define SYSCFG_EXTICR1_EXTI2            ((uint16_t)0x0F00) /*!< EXTI 2 configuration */\r
+#define SYSCFG_EXTICR1_EXTI3            ((uint16_t)0xF000) /*!< EXTI 3 configuration */\r
+\r
+/** \r
+  * @brief  EXTI0 configuration  \r
+  */ \r
+#define SYSCFG_EXTICR1_EXTI0_PA         ((uint16_t)0x0000) /*!< PA[0] pin */\r
+#define SYSCFG_EXTICR1_EXTI0_PB         ((uint16_t)0x0001) /*!< PB[0] pin */\r
+#define SYSCFG_EXTICR1_EXTI0_PC         ((uint16_t)0x0002) /*!< PC[0] pin */\r
+#define SYSCFG_EXTICR1_EXTI0_PD         ((uint16_t)0x0003) /*!< PD[0] pin */\r
+#define SYSCFG_EXTICR1_EXTI0_PE         ((uint16_t)0x0004) /*!< PE[0] pin */\r
+#define SYSCFG_EXTICR1_EXTI0_PH         ((uint16_t)0x0005) /*!< PH[0] pin */\r
+\r
+/** \r
+  * @brief  EXTI1 configuration  \r
+  */ \r
+#define SYSCFG_EXTICR1_EXTI1_PA         ((uint16_t)0x0000) /*!< PA[1] pin */\r
+#define SYSCFG_EXTICR1_EXTI1_PB         ((uint16_t)0x0010) /*!< PB[1] pin */\r
+#define SYSCFG_EXTICR1_EXTI1_PC         ((uint16_t)0x0020) /*!< PC[1] pin */\r
+#define SYSCFG_EXTICR1_EXTI1_PD         ((uint16_t)0x0030) /*!< PD[1] pin */\r
+#define SYSCFG_EXTICR1_EXTI1_PE         ((uint16_t)0x0040) /*!< PE[1] pin */\r
+#define SYSCFG_EXTICR1_EXTI1_PH         ((uint16_t)0x0050) /*!< PH[1] pin */\r
+\r
+/** \r
+  * @brief  EXTI2 configuration  \r
+  */ \r
+#define SYSCFG_EXTICR1_EXTI2_PA         ((uint16_t)0x0000) /*!< PA[2] pin */\r
+#define SYSCFG_EXTICR1_EXTI2_PB         ((uint16_t)0x0100) /*!< PB[2] pin */\r
+#define SYSCFG_EXTICR1_EXTI2_PC         ((uint16_t)0x0200) /*!< PC[2] pin */\r
+#define SYSCFG_EXTICR1_EXTI2_PD         ((uint16_t)0x0300) /*!< PD[2] pin */\r
+#define SYSCFG_EXTICR1_EXTI2_PE         ((uint16_t)0x0400) /*!< PE[2] pin */\r
+#define SYSCFG_EXTICR1_EXTI2_PH         ((uint16_t)0x0500) /*!< PH[2] pin */\r
+\r
+/** \r
+  * @brief  EXTI3 configuration  \r
+  */ \r
+#define SYSCFG_EXTICR1_EXTI3_PA         ((uint16_t)0x0000) /*!< PA[3] pin */\r
+#define SYSCFG_EXTICR1_EXTI3_PB         ((uint16_t)0x1000) /*!< PB[3] pin */\r
+#define SYSCFG_EXTICR1_EXTI3_PC         ((uint16_t)0x2000) /*!< PC[3] pin */\r
+#define SYSCFG_EXTICR1_EXTI3_PD         ((uint16_t)0x3000) /*!< PD[3] pin */\r
+#define SYSCFG_EXTICR1_EXTI3_PE         ((uint16_t)0x4000) /*!< PE[3] pin */\r
+\r
+/*****************  Bit definition for SYSCFG_EXTICR2 register  *****************/\r
+#define SYSCFG_EXTICR2_EXTI4            ((uint16_t)0x000F) /*!< EXTI 4 configuration */\r
+#define SYSCFG_EXTICR2_EXTI5            ((uint16_t)0x00F0) /*!< EXTI 5 configuration */\r
+#define SYSCFG_EXTICR2_EXTI6            ((uint16_t)0x0F00) /*!< EXTI 6 configuration */\r
+#define SYSCFG_EXTICR2_EXTI7            ((uint16_t)0xF000) /*!< EXTI 7 configuration */\r
+\r
+/** \r
+  * @brief  EXTI4 configuration  \r
+  */ \r
+#define SYSCFG_EXTICR2_EXTI4_PA         ((uint16_t)0x0000) /*!< PA[4] pin */\r
+#define SYSCFG_EXTICR2_EXTI4_PB         ((uint16_t)0x0001) /*!< PB[4] pin */\r
+#define SYSCFG_EXTICR2_EXTI4_PC         ((uint16_t)0x0002) /*!< PC[4] pin */\r
+#define SYSCFG_EXTICR2_EXTI4_PD         ((uint16_t)0x0003) /*!< PD[4] pin */\r
+#define SYSCFG_EXTICR2_EXTI4_PE         ((uint16_t)0x0004) /*!< PE[4] pin */\r
+\r
+/** \r
+  * @brief  EXTI5 configuration  \r
+  */ \r
+#define SYSCFG_EXTICR2_EXTI5_PA         ((uint16_t)0x0000) /*!< PA[5] pin */\r
+#define SYSCFG_EXTICR2_EXTI5_PB         ((uint16_t)0x0010) /*!< PB[5] pin */\r
+#define SYSCFG_EXTICR2_EXTI5_PC         ((uint16_t)0x0020) /*!< PC[5] pin */\r
+#define SYSCFG_EXTICR2_EXTI5_PD         ((uint16_t)0x0030) /*!< PD[5] pin */\r
+#define SYSCFG_EXTICR2_EXTI5_PE         ((uint16_t)0x0040) /*!< PE[5] pin */\r
+\r
+/** \r
+  * @brief  EXTI6 configuration  \r
+  */ \r
+#define SYSCFG_EXTICR2_EXTI6_PA         ((uint16_t)0x0000) /*!< PA[6] pin */\r
+#define SYSCFG_EXTICR2_EXTI6_PB         ((uint16_t)0x0100) /*!< PB[6] pin */\r
+#define SYSCFG_EXTICR2_EXTI6_PC         ((uint16_t)0x0200) /*!< PC[6] pin */\r
+#define SYSCFG_EXTICR2_EXTI6_PD         ((uint16_t)0x0300) /*!< PD[6] pin */\r
+#define SYSCFG_EXTICR2_EXTI6_PE         ((uint16_t)0x0400) /*!< PE[6] pin */\r
+\r
+/** \r
+  * @brief  EXTI7 configuration  \r
+  */ \r
+#define SYSCFG_EXTICR2_EXTI7_PA         ((uint16_t)0x0000) /*!< PA[7] pin */\r
+#define SYSCFG_EXTICR2_EXTI7_PB         ((uint16_t)0x1000) /*!< PB[7] pin */\r
+#define SYSCFG_EXTICR2_EXTI7_PC         ((uint16_t)0x2000) /*!< PC[7] pin */\r
+#define SYSCFG_EXTICR2_EXTI7_PD         ((uint16_t)0x3000) /*!< PD[7] pin */\r
+#define SYSCFG_EXTICR2_EXTI7_PE         ((uint16_t)0x4000) /*!< PE[7] pin */\r
+\r
+/*****************  Bit definition for SYSCFG_EXTICR3 register  *****************/\r
+#define SYSCFG_EXTICR3_EXTI8            ((uint16_t)0x000F) /*!< EXTI 8 configuration */\r
+#define SYSCFG_EXTICR3_EXTI9            ((uint16_t)0x00F0) /*!< EXTI 9 configuration */\r
+#define SYSCFG_EXTICR3_EXTI10           ((uint16_t)0x0F00) /*!< EXTI 10 configuration */\r
+#define SYSCFG_EXTICR3_EXTI11           ((uint16_t)0xF000) /*!< EXTI 11 configuration */\r
+                                                                         \r
+/** \r
+  * @brief  EXTI8 configuration  \r
+  */ \r
+#define SYSCFG_EXTICR3_EXTI8_PA         ((uint16_t)0x0000) /*!< PA[8] pin */\r
+#define SYSCFG_EXTICR3_EXTI8_PB         ((uint16_t)0x0001) /*!< PB[8] pin */\r
+#define SYSCFG_EXTICR3_EXTI8_PC         ((uint16_t)0x0002) /*!< PC[8] pin */\r
+#define SYSCFG_EXTICR3_EXTI8_PD         ((uint16_t)0x0003) /*!< PD[8] pin */\r
+#define SYSCFG_EXTICR3_EXTI8_PE         ((uint16_t)0x0004) /*!< PE[8] pin */\r
+\r
+/** \r
+  * @brief  EXTI9 configuration  \r
+  */ \r
+#define SYSCFG_EXTICR3_EXTI9_PA         ((uint16_t)0x0000) /*!< PA[9] pin */\r
+#define SYSCFG_EXTICR3_EXTI9_PB         ((uint16_t)0x0010) /*!< PB[9] pin */\r
+#define SYSCFG_EXTICR3_EXTI9_PC         ((uint16_t)0x0020) /*!< PC[9] pin */\r
+#define SYSCFG_EXTICR3_EXTI9_PD         ((uint16_t)0x0030) /*!< PD[9] pin */\r
+#define SYSCFG_EXTICR3_EXTI9_PE         ((uint16_t)0x0040) /*!< PE[9] pin */\r
+\r
+/** \r
+  * @brief  EXTI10 configuration  \r
+  */ \r
+#define SYSCFG_EXTICR3_EXTI10_PA        ((uint16_t)0x0000) /*!< PA[10] pin */\r
+#define SYSCFG_EXTICR3_EXTI10_PB        ((uint16_t)0x0100) /*!< PB[10] pin */\r
+#define SYSCFG_EXTICR3_EXTI10_PC        ((uint16_t)0x0200) /*!< PC[10] pin */\r
+#define SYSCFG_EXTICR3_EXTI10_PD        ((uint16_t)0x0300) /*!< PD[10] pin */\r
+#define SYSCFG_EXTICR3_EXTI10_PE        ((uint16_t)0x0400) /*!< PE[10] pin */\r
+\r
+/** \r
+  * @brief  EXTI11 configuration  \r
+  */ \r
+#define SYSCFG_EXTICR3_EXTI11_PA        ((uint16_t)0x0000) /*!< PA[11] pin */\r
+#define SYSCFG_EXTICR3_EXTI11_PB        ((uint16_t)0x1000) /*!< PB[11] pin */\r
+#define SYSCFG_EXTICR3_EXTI11_PC        ((uint16_t)0x2000) /*!< PC[11] pin */\r
+#define SYSCFG_EXTICR3_EXTI11_PD        ((uint16_t)0x3000) /*!< PD[11] pin */\r
+#define SYSCFG_EXTICR3_EXTI11_PE        ((uint16_t)0x4000) /*!< PE[11] pin */\r
+\r
+/*****************  Bit definition for SYSCFG_EXTICR4 register  *****************/\r
+#define SYSCFG_EXTICR4_EXTI12           ((uint16_t)0x000F) /*!< EXTI 12 configuration */\r
+#define SYSCFG_EXTICR4_EXTI13           ((uint16_t)0x00F0) /*!< EXTI 13 configuration */\r
+#define SYSCFG_EXTICR4_EXTI14           ((uint16_t)0x0F00) /*!< EXTI 14 configuration */\r
+#define SYSCFG_EXTICR4_EXTI15           ((uint16_t)0xF000) /*!< EXTI 15 configuration */\r
+\r
+/** \r
+  * @brief  EXTI12 configuration  \r
+  */ \r
+#define SYSCFG_EXTICR4_EXTI12_PA        ((uint16_t)0x0000) /*!< PA[12] pin */\r
+#define SYSCFG_EXTICR4_EXTI12_PB        ((uint16_t)0x0001) /*!< PB[12] pin */\r
+#define SYSCFG_EXTICR4_EXTI12_PC        ((uint16_t)0x0002) /*!< PC[12] pin */\r
+#define SYSCFG_EXTICR4_EXTI12_PD        ((uint16_t)0x0003) /*!< PD[12] pin */\r
+#define SYSCFG_EXTICR4_EXTI12_PE        ((uint16_t)0x0004) /*!< PE[12] pin */\r
+\r
+/** \r
+  * @brief  EXTI13 configuration  \r
+  */ \r
+#define SYSCFG_EXTICR4_EXTI13_PA        ((uint16_t)0x0000) /*!< PA[13] pin */\r
+#define SYSCFG_EXTICR4_EXTI13_PB        ((uint16_t)0x0010) /*!< PB[13] pin */\r
+#define SYSCFG_EXTICR4_EXTI13_PC        ((uint16_t)0x0020) /*!< PC[13] pin */\r
+#define SYSCFG_EXTICR4_EXTI13_PD        ((uint16_t)0x0030) /*!< PD[13] pin */\r
+#define SYSCFG_EXTICR4_EXTI13_PE        ((uint16_t)0x0040) /*!< PE[13] pin */\r
+\r
+/** \r
+  * @brief  EXTI14 configuration  \r
+  */ \r
+#define SYSCFG_EXTICR4_EXTI14_PA        ((uint16_t)0x0000) /*!< PA[14] pin */\r
+#define SYSCFG_EXTICR4_EXTI14_PB        ((uint16_t)0x0100) /*!< PB[14] pin */\r
+#define SYSCFG_EXTICR4_EXTI14_PC        ((uint16_t)0x0200) /*!< PC[14] pin */\r
+#define SYSCFG_EXTICR4_EXTI14_PD        ((uint16_t)0x0300) /*!< PD[14] pin */\r
+#define SYSCFG_EXTICR4_EXTI14_PE        ((uint16_t)0x0400) /*!< PE[14] pin */\r
+\r
+/** \r
+  * @brief  EXTI15 configuration  \r
+  */ \r
+#define SYSCFG_EXTICR4_EXTI15_PA        ((uint16_t)0x0000) /*!< PA[15] pin */\r
+#define SYSCFG_EXTICR4_EXTI15_PB        ((uint16_t)0x1000) /*!< PB[15] pin */\r
+#define SYSCFG_EXTICR4_EXTI15_PC        ((uint16_t)0x2000) /*!< PC[15] pin */\r
+#define SYSCFG_EXTICR4_EXTI15_PD        ((uint16_t)0x3000) /*!< PD[15] pin */\r
+#define SYSCFG_EXTICR4_EXTI15_PE        ((uint16_t)0x4000) /*!< PE[15] pin */\r
+ \r
+/******************************************************************************/\r
+/*                                                                            */\r
+/*                       Routing Interface (RI)                               */\r
+/*                                                                            */\r
+/******************************************************************************/\r
+\r
+/********************  Bit definition for RI_ICR register  ********************/\r
+#define  RI_ICR_IC1Z                    ((uint32_t)0x0000000F) /*!< IC1Z[3:0] bits (Input Capture 1 select bits) */\r
+#define  RI_ICR_IC1Z_0                  ((uint32_t)0x00000001) /*!< Bit 0 */\r
+#define  RI_ICR_IC1Z_1                  ((uint32_t)0x00000002) /*!< Bit 1 */\r
+#define  RI_ICR_IC1Z_2                  ((uint32_t)0x00000004) /*!< Bit 2 */\r
+#define  RI_ICR_IC1Z_3                  ((uint32_t)0x00000008) /*!< Bit 3 */\r
+\r
+#define  RI_ICR_IC2Z                    ((uint32_t)0x000000F0) /*!< IC2Z[3:0] bits (Input Capture 2 select bits) */\r
+#define  RI_ICR_IC2Z_0                  ((uint32_t)0x00000010) /*!< Bit 0 */\r
+#define  RI_ICR_IC2Z_1                  ((uint32_t)0x00000020) /*!< Bit 1 */\r
+#define  RI_ICR_IC2Z_2                  ((uint32_t)0x00000040) /*!< Bit 2 */\r
+#define  RI_ICR_IC2Z_3                  ((uint32_t)0x00000080) /*!< Bit 3 */\r
+\r
+#define  RI_ICR_IC3Z                    ((uint32_t)0x00000F00) /*!< IC3Z[3:0] bits (Input Capture 3 select bits) */\r
+#define  RI_ICR_IC3Z_0                  ((uint32_t)0x00000100) /*!< Bit 0 */\r
+#define  RI_ICR_IC3Z_1                  ((uint32_t)0x00000200) /*!< Bit 1 */\r
+#define  RI_ICR_IC3Z_2                  ((uint32_t)0x00000400) /*!< Bit 2 */\r
+#define  RI_ICR_IC3Z_3                  ((uint32_t)0x00000800) /*!< Bit 3 */\r
+\r
+#define  RI_ICR_IC4Z                    ((uint32_t)0x0000F000) /*!< IC2Z[3:0] bits (Input Capture 2 select bits) */\r
+#define  RI_ICR_IC4Z_0                  ((uint32_t)0x00001000) /*!< Bit 0 */\r
+#define  RI_ICR_IC4Z_1                  ((uint32_t)0x00002000) /*!< Bit 1 */\r
+#define  RI_ICR_IC4Z_2                  ((uint32_t)0x00004000) /*!< Bit 2 */\r
+#define  RI_ICR_IC4Z_3                  ((uint32_t)0x00008000) /*!< Bit 3 */\r
+\r
+#define  RI_ICR_TIM                     ((uint32_t)0x00030000) /*!< TIM[3:0] bits (Timers select bits) */\r
+#define  RI_ICR_TIM_0                   ((uint32_t)0x00010000) /*!< Bit 0 */\r
+#define  RI_ICR_TIM_1                   ((uint32_t)0x00020000) /*!< Bit 1 */\r
+\r
+#define  RI_ICR_IC1                     ((uint32_t)0x00040000) /*!< Input capture 1 */\r
+#define  RI_ICR_IC2                     ((uint32_t)0x00080000) /*!< Input capture 2 */\r
+#define  RI_ICR_IC3                     ((uint32_t)0x00100000) /*!< Input capture 3 */\r
+#define  RI_ICR_IC4                     ((uint32_t)0x00200000) /*!< Input capture 4 */\r
+\r
+/********************  Bit definition for RI_ASCR1 register  ********************/\r
+#define  RI_ASCR1_CH                    ((uint32_t)0x03FCFFFF) /*!< AS_CH[25:18] & AS_CH[15:0] bits ( Analog switches selection bits) */\r
+#define  RI_ASCR1_CH_0                  ((uint32_t)0x00000001) /*!< Bit 0 */\r
+#define  RI_ASCR1_CH_1                  ((uint32_t)0x00000002) /*!< Bit 1 */\r
+#define  RI_ASCR1_CH_2                  ((uint32_t)0x00000004) /*!< Bit 2 */\r
+#define  RI_ASCR1_CH_3                  ((uint32_t)0x00000008) /*!< Bit 3 */\r
+#define  RI_ASCR1_CH_4                  ((uint32_t)0x00000010) /*!< Bit 4 */\r
+#define  RI_ASCR1_CH_5                  ((uint32_t)0x00000020) /*!< Bit 5 */\r
+#define  RI_ASCR1_CH_6                  ((uint32_t)0x00000040) /*!< Bit 6 */\r
+#define  RI_ASCR1_CH_7                  ((uint32_t)0x00000080) /*!< Bit 7 */\r
+#define  RI_ASCR1_CH_8                  ((uint32_t)0x00000100) /*!< Bit 8 */\r
+#define  RI_ASCR1_CH_9                  ((uint32_t)0x00000200) /*!< Bit 9 */\r
+#define  RI_ASCR1_CH_10                 ((uint32_t)0x00000400) /*!< Bit 10 */\r
+#define  RI_ASCR1_CH_11                 ((uint32_t)0x00000800) /*!< Bit 11 */\r
+#define  RI_ASCR1_CH_12                 ((uint32_t)0x00001000) /*!< Bit 12 */\r
+#define  RI_ASCR1_CH_13                 ((uint32_t)0x00002000) /*!< Bit 13 */\r
+#define  RI_ASCR1_CH_14                 ((uint32_t)0x00004000) /*!< Bit 14 */\r
+#define  RI_ASCR1_CH_15                 ((uint32_t)0x00008000) /*!< Bit 15 */\r
+#define  RI_ASCR1_CH_18                 ((uint32_t)0x00040000) /*!< Bit 18 */\r
+#define  RI_ASCR1_CH_19                 ((uint32_t)0x00080000) /*!< Bit 19 */\r
+#define  RI_ASCR1_CH_20                 ((uint32_t)0x00100000) /*!< Bit 20 */\r
+#define  RI_ASCR1_CH_21                 ((uint32_t)0x00200000) /*!< Bit 21 */\r
+#define  RI_ASCR1_CH_22                 ((uint32_t)0x00400000) /*!< Bit 22 */\r
+#define  RI_ASCR1_CH_23                 ((uint32_t)0x00800000) /*!< Bit 23 */\r
+#define  RI_ASCR1_CH_24                 ((uint32_t)0x01000000) /*!< Bit 24 */\r
+#define  RI_ASCR1_CH_25                 ((uint32_t)0x02000000) /*!< Bit 25 */\r
+\r
+#define  RI_ASCR1_VCOMP                 ((uint32_t)0x04000000) /*!< ADC analog switch selection for internal node to COMP1 */\r
+#define  RI_ASCR1_SCM                   ((uint32_t)0x80000000) /*!< I/O Switch control mode */\r
+\r
+/********************  Bit definition for RI_ASCR2 register  ********************/\r
+#define  RI_ASCR2_GR10_1                ((uint32_t)0x00000001) /*!< GR10-1 selection bit */\r
+#define  RI_ASCR2_GR10_2                ((uint32_t)0x00000002) /*!< GR10-2 selection bit */\r
+#define  RI_ASCR2_GR10_3                ((uint32_t)0x00000004) /*!< GR10-3 selection bit */\r
+#define  RI_ASCR2_GR10_4                ((uint32_t)0x00000008) /*!< GR10-4 selection bit */\r
+#define  RI_ASCR2_GR6_1                 ((uint32_t)0x00000010) /*!< GR6-1 selection bit */\r
+#define  RI_ASCR2_GR6_2                 ((uint32_t)0x00000020) /*!< GR6-2 selection bit */\r
+#define  RI_ASCR2_GR5_1                 ((uint32_t)0x00000040) /*!< GR5-1 selection bit */\r
+#define  RI_ASCR2_GR5_2                 ((uint32_t)0x00000080) /*!< GR5-2 selection bit */\r
+#define  RI_ASCR2_GR5_3                 ((uint32_t)0x00000100) /*!< GR5-3 selection bit */\r
+#define  RI_ASCR2_GR4_1                 ((uint32_t)0x00000200) /*!< GR4-1 selection bit */\r
+#define  RI_ASCR2_GR4_2                 ((uint32_t)0x00000400) /*!< GR4-2 selection bit */\r
+#define  RI_ASCR2_GR4_3                 ((uint32_t)0x00000800) /*!< GR4-3 selection bit */\r
+\r
+\r
+/********************  Bit definition for RI_HYSCR1 register  ********************/\r
+#define  RI_HYSCR1_PA                   ((uint32_t)0x0000FFFF) /*!< PA[15:0] Port A Hysteresis selection */\r
+#define  RI_HYSCR1_PA_0                 ((uint32_t)0x00000001) /*!< Bit 0 */\r
+#define  RI_HYSCR1_PA_1                 ((uint32_t)0x00000002) /*!< Bit 1 */\r
+#define  RI_HYSCR1_PA_2                 ((uint32_t)0x00000004) /*!< Bit 2 */\r
+#define  RI_HYSCR1_PA_3                 ((uint32_t)0x00000008) /*!< Bit 3 */\r
+#define  RI_HYSCR1_PA_4                 ((uint32_t)0x00000010) /*!< Bit 4 */\r
+#define  RI_HYSCR1_PA_5                 ((uint32_t)0x00000020) /*!< Bit 5 */\r
+#define  RI_HYSCR1_PA_6                 ((uint32_t)0x00000040) /*!< Bit 6 */\r
+#define  RI_HYSCR1_PA_7                 ((uint32_t)0x00000080) /*!< Bit 7 */\r
+#define  RI_HYSCR1_PA_8                 ((uint32_t)0x00000100) /*!< Bit 8 */\r
+#define  RI_HYSCR1_PA_9                 ((uint32_t)0x00000200) /*!< Bit 9 */\r
+#define  RI_HYSCR1_PA_10                ((uint32_t)0x00000400) /*!< Bit 10 */\r
+#define  RI_HYSCR1_PA_11                ((uint32_t)0x00000800) /*!< Bit 11 */\r
+#define  RI_HYSCR1_PA_12                ((uint32_t)0x00001000) /*!< Bit 12 */\r
+#define  RI_HYSCR1_PA_13                ((uint32_t)0x00002000) /*!< Bit 13 */\r
+#define  RI_HYSCR1_PA_14                ((uint32_t)0x00004000) /*!< Bit 14 */\r
+#define  RI_HYSCR1_PA_15                ((uint32_t)0x00008000) /*!< Bit 15 */\r
+\r
+#define  RI_HYSCR1_PB                   ((uint32_t)0xFFFF0000) /*!< PB[15:0] Port B Hysteresis selection */\r
+#define  RI_HYSCR1_PB_0                 ((uint32_t)0x00010000) /*!< Bit 0 */\r
+#define  RI_HYSCR1_PB_1                 ((uint32_t)0x00020000) /*!< Bit 1 */\r
+#define  RI_HYSCR1_PB_2                 ((uint32_t)0x00040000) /*!< Bit 2 */\r
+#define  RI_HYSCR1_PB_3                 ((uint32_t)0x00080000) /*!< Bit 3 */\r
+#define  RI_HYSCR1_PB_4                 ((uint32_t)0x00100000) /*!< Bit 4 */\r
+#define  RI_HYSCR1_PB_5                 ((uint32_t)0x00200000) /*!< Bit 5 */\r
+#define  RI_HYSCR1_PB_6                 ((uint32_t)0x00400000) /*!< Bit 6 */\r
+#define  RI_HYSCR1_PB_7                 ((uint32_t)0x00800000) /*!< Bit 7 */\r
+#define  RI_HYSCR1_PB_8                 ((uint32_t)0x01000000) /*!< Bit 8 */\r
+#define  RI_HYSCR1_PB_9                 ((uint32_t)0x02000000) /*!< Bit 9 */\r
+#define  RI_HYSCR1_PB_10                ((uint32_t)0x04000000) /*!< Bit 10 */\r
+#define  RI_HYSCR1_PB_11                ((uint32_t)0x08000000) /*!< Bit 11 */\r
+#define  RI_HYSCR1_PB_12                ((uint32_t)0x10000000) /*!< Bit 12 */\r
+#define  RI_HYSCR1_PB_13                ((uint32_t)0x20000000) /*!< Bit 13 */\r
+#define  RI_HYSCR1_PB_14                ((uint32_t)0x40000000) /*!< Bit 14 */\r
+#define  RI_HYSCR1_PB_15                ((uint32_t)0x80000000) /*!< Bit 15 */\r
+\r
+/********************  Bit definition for RI_HYSCR2 register  ********************/\r
+#define  RI_HYSCR2_PC                   ((uint32_t)0x0000FFFF) /*!< PC[15:0] Port C Hysteresis selection */\r
+#define  RI_HYSCR2_PC_0                 ((uint32_t)0x00000001) /*!< Bit 0 */\r
+#define  RI_HYSCR2_PC_1                 ((uint32_t)0x00000002) /*!< Bit 1 */\r
+#define  RI_HYSCR2_PC_2                 ((uint32_t)0x00000004) /*!< Bit 2 */\r
+#define  RI_HYSCR2_PC_3                 ((uint32_t)0x00000008) /*!< Bit 3 */\r
+#define  RI_HYSCR2_PC_4                 ((uint32_t)0x00000010) /*!< Bit 4 */\r
+#define  RI_HYSCR2_PC_5                 ((uint32_t)0x00000020) /*!< Bit 5 */\r
+#define  RI_HYSCR2_PC_6                 ((uint32_t)0x00000040) /*!< Bit 6 */\r
+#define  RI_HYSCR2_PC_7                 ((uint32_t)0x00000080) /*!< Bit 7 */\r
+#define  RI_HYSCR2_PC_8                 ((uint32_t)0x00000100) /*!< Bit 8 */\r
+#define  RI_HYSCR2_PC_9                 ((uint32_t)0x00000200) /*!< Bit 9 */\r
+#define  RI_HYSCR2_PC_10                ((uint32_t)0x00000400) /*!< Bit 10 */\r
+#define  RI_HYSCR2_PC_11                ((uint32_t)0x00000800) /*!< Bit 11 */\r
+#define  RI_HYSCR2_PC_12                ((uint32_t)0x00001000) /*!< Bit 12 */\r
+#define  RI_HYSCR2_PC_13                ((uint32_t)0x00002000) /*!< Bit 13 */\r
+#define  RI_HYSCR2_PC_14                ((uint32_t)0x00004000) /*!< Bit 14 */\r
+#define  RI_HYSCR2_PC_15                ((uint32_t)0x00008000) /*!< Bit 15 */\r
+\r
+#define  RI_HYSCR2_PD                   ((uint32_t)0xFFFF0000) /*!< PD[15:0] Port D Hysteresis selection */\r
+#define  RI_HYSCR2_PD_0                 ((uint32_t)0x00010000) /*!< Bit 0 */\r
+#define  RI_HYSCR2_PD_1                 ((uint32_t)0x00020000) /*!< Bit 1 */\r
+#define  RI_HYSCR2_PD_2                 ((uint32_t)0x00040000) /*!< Bit 2 */\r
+#define  RI_HYSCR2_PD_3                 ((uint32_t)0x00080000) /*!< Bit 3 */\r
+#define  RI_HYSCR2_PD_4                 ((uint32_t)0x00100000) /*!< Bit 4 */\r
+#define  RI_HYSCR2_PD_5                 ((uint32_t)0x00200000) /*!< Bit 5 */\r
+#define  RI_HYSCR2_PD_6                 ((uint32_t)0x00400000) /*!< Bit 6 */\r
+#define  RI_HYSCR2_PD_7                 ((uint32_t)0x00800000) /*!< Bit 7 */\r
+#define  RI_HYSCR2_PD_8                 ((uint32_t)0x01000000) /*!< Bit 8 */\r
+#define  RI_HYSCR2_PD_9                 ((uint32_t)0x02000000) /*!< Bit 9 */\r
+#define  RI_HYSCR2_PD_10                ((uint32_t)0x04000000) /*!< Bit 10 */\r
+#define  RI_HYSCR2_PD_11                ((uint32_t)0x08000000) /*!< Bit 11 */\r
+#define  RI_HYSCR2_PD_12                ((uint32_t)0x10000000) /*!< Bit 12 */\r
+#define  RI_HYSCR2_PD_13                ((uint32_t)0x20000000) /*!< Bit 13 */\r
+#define  RI_HYSCR2_PD_14                ((uint32_t)0x40000000) /*!< Bit 14 */\r
+#define  RI_HYSCR2_PD_15                ((uint32_t)0x80000000) /*!< Bit 15 */\r
+\r
+/********************  Bit definition for RI_HYSCR3 register  ********************/\r
+#define  RI_HYSCR2_PE                   ((uint32_t)0x0000FFFF) /*!< PE[15:0] Port E Hysteresis selection */\r
+#define  RI_HYSCR2_PE_0                 ((uint32_t)0x00000001) /*!< Bit 0 */\r
+#define  RI_HYSCR2_PE_1                 ((uint32_t)0x00000002) /*!< Bit 1 */\r
+#define  RI_HYSCR2_PE_2                 ((uint32_t)0x00000004) /*!< Bit 2 */\r
+#define  RI_HYSCR2_PE_3                 ((uint32_t)0x00000008) /*!< Bit 3 */\r
+#define  RI_HYSCR2_PE_4                 ((uint32_t)0x00000010) /*!< Bit 4 */\r
+#define  RI_HYSCR2_PE_5                 ((uint32_t)0x00000020) /*!< Bit 5 */\r
+#define  RI_HYSCR2_PE_6                 ((uint32_t)0x00000040) /*!< Bit 6 */\r
+#define  RI_HYSCR2_PE_7                 ((uint32_t)0x00000080) /*!< Bit 7 */\r
+#define  RI_HYSCR2_PE_8                 ((uint32_t)0x00000100) /*!< Bit 8 */\r
+#define  RI_HYSCR2_PE_9                 ((uint32_t)0x00000200) /*!< Bit 9 */\r
+#define  RI_HYSCR2_PE_10                ((uint32_t)0x00000400) /*!< Bit 10 */\r
+#define  RI_HYSCR2_PE_11                ((uint32_t)0x00000800) /*!< Bit 11 */\r
+#define  RI_HYSCR2_PE_12                ((uint32_t)0x00001000) /*!< Bit 12 */\r
+#define  RI_HYSCR2_PE_13                ((uint32_t)0x00002000) /*!< Bit 13 */\r
+#define  RI_HYSCR2_PE_14                ((uint32_t)0x00004000) /*!< Bit 14 */\r
+#define  RI_HYSCR2_PE_15                ((uint32_t)0x00008000) /*!< Bit 15 */\r
+\r
+/******************************************************************************/\r
+/*                                                                            */\r
+/*                                    TIM                                     */\r
+/*                                                                            */\r
+/******************************************************************************/\r
+\r
+/*******************  Bit definition for TIM_CR1 register  ********************/\r
+#define  TIM_CR1_CEN                         ((uint16_t)0x0001)            /*!<Counter enable */\r
+#define  TIM_CR1_UDIS                        ((uint16_t)0x0002)            /*!<Update disable */\r
+#define  TIM_CR1_URS                         ((uint16_t)0x0004)            /*!<Update request source */\r
+#define  TIM_CR1_OPM                         ((uint16_t)0x0008)            /*!<One pulse mode */\r
+#define  TIM_CR1_DIR                         ((uint16_t)0x0010)            /*!<Direction */\r
+\r
+#define  TIM_CR1_CMS                         ((uint16_t)0x0060)            /*!<CMS[1:0] bits (Center-aligned mode selection) */\r
+#define  TIM_CR1_CMS_0                       ((uint16_t)0x0020)            /*!<Bit 0 */\r
+#define  TIM_CR1_CMS_1                       ((uint16_t)0x0040)            /*!<Bit 1 */\r
+\r
+#define  TIM_CR1_ARPE                        ((uint16_t)0x0080)            /*!<Auto-reload preload enable */\r
+\r
+#define  TIM_CR1_CKD                         ((uint16_t)0x0300)            /*!<CKD[1:0] bits (clock division) */\r
+#define  TIM_CR1_CKD_0                       ((uint16_t)0x0100)            /*!<Bit 0 */\r
+#define  TIM_CR1_CKD_1                       ((uint16_t)0x0200)            /*!<Bit 1 */\r
+\r
+/*******************  Bit definition for TIM_CR2 register  ********************/\r
+#define  TIM_CR2_CCPC                        ((uint16_t)0x0001)            /*!<Capture/Compare Preloaded Control */\r
+#define  TIM_CR2_CCUS                        ((uint16_t)0x0004)            /*!<Capture/Compare Control Update Selection */\r
+#define  TIM_CR2_CCDS                        ((uint16_t)0x0008)            /*!<Capture/Compare DMA Selection */\r
+\r
+#define  TIM_CR2_MMS                         ((uint16_t)0x0070)            /*!<MMS[2:0] bits (Master Mode Selection) */\r
+#define  TIM_CR2_MMS_0                       ((uint16_t)0x0010)            /*!<Bit 0 */\r
+#define  TIM_CR2_MMS_1                       ((uint16_t)0x0020)            /*!<Bit 1 */\r
+#define  TIM_CR2_MMS_2                       ((uint16_t)0x0040)            /*!<Bit 2 */\r
+\r
+#define  TIM_CR2_TI1S                        ((uint16_t)0x0080)            /*!<TI1 Selection */\r
+#define  TIM_CR2_OIS1                        ((uint16_t)0x0100)            /*!<Output Idle state 1 (OC1 output) */\r
+#define  TIM_CR2_OIS1N                       ((uint16_t)0x0200)            /*!<Output Idle state 1 (OC1N output) */\r
+#define  TIM_CR2_OIS2                        ((uint16_t)0x0400)            /*!<Output Idle state 2 (OC2 output) */\r
+#define  TIM_CR2_OIS2N                       ((uint16_t)0x0800)            /*!<Output Idle state 2 (OC2N output) */\r
+#define  TIM_CR2_OIS3                        ((uint16_t)0x1000)            /*!<Output Idle state 3 (OC3 output) */\r
+#define  TIM_CR2_OIS3N                       ((uint16_t)0x2000)            /*!<Output Idle state 3 (OC3N output) */\r
+#define  TIM_CR2_OIS4                        ((uint16_t)0x4000)            /*!<Output Idle state 4 (OC4 output) */\r
+\r
+/*******************  Bit definition for TIM_SMCR register  *******************/\r
+#define  TIM_SMCR_SMS                        ((uint16_t)0x0007)            /*!<SMS[2:0] bits (Slave mode selection) */\r
+#define  TIM_SMCR_SMS_0                      ((uint16_t)0x0001)            /*!<Bit 0 */\r
+#define  TIM_SMCR_SMS_1                      ((uint16_t)0x0002)            /*!<Bit 1 */\r
+#define  TIM_SMCR_SMS_2                      ((uint16_t)0x0004)            /*!<Bit 2 */\r
+\r
+#define  TIM_SMCR_OCCS                       ((uint16_t)0x0008)            /*!<OCCS bits (OCref Clear Selection) */\r
+\r
+#define  TIM_SMCR_TS                         ((uint16_t)0x0070)            /*!<TS[2:0] bits (Trigger selection) */\r
+#define  TIM_SMCR_TS_0                       ((uint16_t)0x0010)            /*!<Bit 0 */\r
+#define  TIM_SMCR_TS_1                       ((uint16_t)0x0020)            /*!<Bit 1 */\r
+#define  TIM_SMCR_TS_2                       ((uint16_t)0x0040)            /*!<Bit 2 */\r
+\r
+#define  TIM_SMCR_MSM                        ((uint16_t)0x0080)            /*!<Master/slave mode */\r
+\r
+#define  TIM_SMCR_ETF                        ((uint16_t)0x0F00)            /*!<ETF[3:0] bits (External trigger filter) */\r
+#define  TIM_SMCR_ETF_0                      ((uint16_t)0x0100)            /*!<Bit 0 */\r
+#define  TIM_SMCR_ETF_1                      ((uint16_t)0x0200)            /*!<Bit 1 */\r
+#define  TIM_SMCR_ETF_2                      ((uint16_t)0x0400)            /*!<Bit 2 */\r
+#define  TIM_SMCR_ETF_3                      ((uint16_t)0x0800)            /*!<Bit 3 */\r
+\r
+#define  TIM_SMCR_ETPS                       ((uint16_t)0x3000)            /*!<ETPS[1:0] bits (External trigger prescaler) */\r
+#define  TIM_SMCR_ETPS_0                     ((uint16_t)0x1000)            /*!<Bit 0 */\r
+#define  TIM_SMCR_ETPS_1                     ((uint16_t)0x2000)            /*!<Bit 1 */\r
+\r
+#define  TIM_SMCR_ECE                        ((uint16_t)0x4000)            /*!<External clock enable */\r
+#define  TIM_SMCR_ETP                        ((uint16_t)0x8000)            /*!<External trigger polarity */\r
+\r
+/*******************  Bit definition for TIM_DIER register  *******************/\r
+#define  TIM_DIER_UIE                        ((uint16_t)0x0001)            /*!<Update interrupt enable */\r
+#define  TIM_DIER_CC1IE                      ((uint16_t)0x0002)            /*!<Capture/Compare 1 interrupt enable */\r
+#define  TIM_DIER_CC2IE                      ((uint16_t)0x0004)            /*!<Capture/Compare 2 interrupt enable */\r
+#define  TIM_DIER_CC3IE                      ((uint16_t)0x0008)            /*!<Capture/Compare 3 interrupt enable */\r
+#define  TIM_DIER_CC4IE                      ((uint16_t)0x0010)            /*!<Capture/Compare 4 interrupt enable */\r
+#define  TIM_DIER_COMIE                      ((uint16_t)0x0020)            /*!<COM interrupt enable */\r
+#define  TIM_DIER_TIE                        ((uint16_t)0x0040)            /*!<Trigger interrupt enable */\r
+#define  TIM_DIER_BIE                        ((uint16_t)0x0080)            /*!<Break interrupt enable */\r
+#define  TIM_DIER_UDE                        ((uint16_t)0x0100)            /*!<Update DMA request enable */\r
+#define  TIM_DIER_CC1DE                      ((uint16_t)0x0200)            /*!<Capture/Compare 1 DMA request enable */\r
+#define  TIM_DIER_CC2DE                      ((uint16_t)0x0400)            /*!<Capture/Compare 2 DMA request enable */\r
+#define  TIM_DIER_CC3DE                      ((uint16_t)0x0800)            /*!<Capture/Compare 3 DMA request enable */\r
+#define  TIM_DIER_CC4DE                      ((uint16_t)0x1000)            /*!<Capture/Compare 4 DMA request enable */\r
+#define  TIM_DIER_COMDE                      ((uint16_t)0x2000)            /*!<COM DMA request enable */\r
+#define  TIM_DIER_TDE                        ((uint16_t)0x4000)            /*!<Trigger DMA request enable */\r
+\r
+/********************  Bit definition for TIM_SR register  ********************/\r
+#define  TIM_SR_UIF                          ((uint16_t)0x0001)            /*!<Update interrupt Flag */\r
+#define  TIM_SR_CC1IF                        ((uint16_t)0x0002)            /*!<Capture/Compare 1 interrupt Flag */\r
+#define  TIM_SR_CC2IF                        ((uint16_t)0x0004)            /*!<Capture/Compare 2 interrupt Flag */\r
+#define  TIM_SR_CC3IF                        ((uint16_t)0x0008)            /*!<Capture/Compare 3 interrupt Flag */\r
+#define  TIM_SR_CC4IF                        ((uint16_t)0x0010)            /*!<Capture/Compare 4 interrupt Flag */\r
+#define  TIM_SR_COMIF                        ((uint16_t)0x0020)            /*!<COM interrupt Flag */\r
+#define  TIM_SR_TIF                          ((uint16_t)0x0040)            /*!<Trigger interrupt Flag */\r
+#define  TIM_SR_BIF                          ((uint16_t)0x0080)            /*!<Break interrupt Flag */\r
+#define  TIM_SR_CC1OF                        ((uint16_t)0x0200)            /*!<Capture/Compare 1 Overcapture Flag */\r
+#define  TIM_SR_CC2OF                        ((uint16_t)0x0400)            /*!<Capture/Compare 2 Overcapture Flag */\r
+#define  TIM_SR_CC3OF                        ((uint16_t)0x0800)            /*!<Capture/Compare 3 Overcapture Flag */\r
+#define  TIM_SR_CC4OF                        ((uint16_t)0x1000)            /*!<Capture/Compare 4 Overcapture Flag */\r
+\r
+/*******************  Bit definition for TIM_EGR register  ********************/\r
+#define  TIM_EGR_UG                          ((uint8_t)0x01)               /*!<Update Generation */\r
+#define  TIM_EGR_CC1G                        ((uint8_t)0x02)               /*!<Capture/Compare 1 Generation */\r
+#define  TIM_EGR_CC2G                        ((uint8_t)0x04)               /*!<Capture/Compare 2 Generation */\r
+#define  TIM_EGR_CC3G                        ((uint8_t)0x08)               /*!<Capture/Compare 3 Generation */\r
+#define  TIM_EGR_CC4G                        ((uint8_t)0x10)               /*!<Capture/Compare 4 Generation */\r
+#define  TIM_EGR_COMG                        ((uint8_t)0x20)               /*!<Capture/Compare Control Update Generation */\r
+#define  TIM_EGR_TG                          ((uint8_t)0x40)               /*!<Trigger Generation */\r
+#define  TIM_EGR_BG                          ((uint8_t)0x80)               /*!<Break Generation */\r
+\r
+/******************  Bit definition for TIM_CCMR1 register  *******************/\r
+#define  TIM_CCMR1_CC1S                      ((uint16_t)0x0003)            /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */\r
+#define  TIM_CCMR1_CC1S_0                    ((uint16_t)0x0001)            /*!<Bit 0 */\r
+#define  TIM_CCMR1_CC1S_1                    ((uint16_t)0x0002)            /*!<Bit 1 */\r
+\r
+#define  TIM_CCMR1_OC1FE                     ((uint16_t)0x0004)            /*!<Output Compare 1 Fast enable */\r
+#define  TIM_CCMR1_OC1PE                     ((uint16_t)0x0008)            /*!<Output Compare 1 Preload enable */\r
+\r
+#define  TIM_CCMR1_OC1M                      ((uint16_t)0x0070)            /*!<OC1M[2:0] bits (Output Compare 1 Mode) */\r
+#define  TIM_CCMR1_OC1M_0                    ((uint16_t)0x0010)            /*!<Bit 0 */\r
+#define  TIM_CCMR1_OC1M_1                    ((uint16_t)0x0020)            /*!<Bit 1 */\r
+#define  TIM_CCMR1_OC1M_2                    ((uint16_t)0x0040)            /*!<Bit 2 */\r
+\r
+#define  TIM_CCMR1_OC1CE                     ((uint16_t)0x0080)            /*!<Output Compare 1Clear Enable */\r
+\r
+#define  TIM_CCMR1_CC2S                      ((uint16_t)0x0300)            /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */\r
+#define  TIM_CCMR1_CC2S_0                    ((uint16_t)0x0100)            /*!<Bit 0 */\r
+#define  TIM_CCMR1_CC2S_1                    ((uint16_t)0x0200)            /*!<Bit 1 */\r
+\r
+#define  TIM_CCMR1_OC2FE                     ((uint16_t)0x0400)            /*!<Output Compare 2 Fast enable */\r
+#define  TIM_CCMR1_OC2PE                     ((uint16_t)0x0800)            /*!<Output Compare 2 Preload enable */\r
+\r
+#define  TIM_CCMR1_OC2M                      ((uint16_t)0x7000)            /*!<OC2M[2:0] bits (Output Compare 2 Mode) */\r
+#define  TIM_CCMR1_OC2M_0                    ((uint16_t)0x1000)            /*!<Bit 0 */\r
+#define  TIM_CCMR1_OC2M_1                    ((uint16_t)0x2000)            /*!<Bit 1 */\r
+#define  TIM_CCMR1_OC2M_2                    ((uint16_t)0x4000)            /*!<Bit 2 */\r
+\r
+#define  TIM_CCMR1_OC2CE                     ((uint16_t)0x8000)            /*!<Output Compare 2 Clear Enable */\r
+\r
+/*----------------------------------------------------------------------------*/\r
+\r
+#define  TIM_CCMR1_IC1PSC                    ((uint16_t)0x000C)            /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */\r
+#define  TIM_CCMR1_IC1PSC_0                  ((uint16_t)0x0004)            /*!<Bit 0 */\r
+#define  TIM_CCMR1_IC1PSC_1                  ((uint16_t)0x0008)            /*!<Bit 1 */\r
+\r
+#define  TIM_CCMR1_IC1F                      ((uint16_t)0x00F0)            /*!<IC1F[3:0] bits (Input Capture 1 Filter) */\r
+#define  TIM_CCMR1_IC1F_0                    ((uint16_t)0x0010)            /*!<Bit 0 */\r
+#define  TIM_CCMR1_IC1F_1                    ((uint16_t)0x0020)            /*!<Bit 1 */\r
+#define  TIM_CCMR1_IC1F_2                    ((uint16_t)0x0040)            /*!<Bit 2 */\r
+#define  TIM_CCMR1_IC1F_3                    ((uint16_t)0x0080)            /*!<Bit 3 */\r
+\r
+#define  TIM_CCMR1_IC2PSC                    ((uint16_t)0x0C00)            /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */\r
+#define  TIM_CCMR1_IC2PSC_0                  ((uint16_t)0x0400)            /*!<Bit 0 */\r
+#define  TIM_CCMR1_IC2PSC_1                  ((uint16_t)0x0800)            /*!<Bit 1 */\r
+\r
+#define  TIM_CCMR1_IC2F                      ((uint16_t)0xF000)            /*!<IC2F[3:0] bits (Input Capture 2 Filter) */\r
+#define  TIM_CCMR1_IC2F_0                    ((uint16_t)0x1000)            /*!<Bit 0 */\r
+#define  TIM_CCMR1_IC2F_1                    ((uint16_t)0x2000)            /*!<Bit 1 */\r
+#define  TIM_CCMR1_IC2F_2                    ((uint16_t)0x4000)            /*!<Bit 2 */\r
+#define  TIM_CCMR1_IC2F_3                    ((uint16_t)0x8000)            /*!<Bit 3 */\r
+\r
+/******************  Bit definition for TIM_CCMR2 register  *******************/\r
+#define  TIM_CCMR2_CC3S                      ((uint16_t)0x0003)            /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */\r
+#define  TIM_CCMR2_CC3S_0                    ((uint16_t)0x0001)            /*!<Bit 0 */\r
+#define  TIM_CCMR2_CC3S_1                    ((uint16_t)0x0002)            /*!<Bit 1 */\r
+\r
+#define  TIM_CCMR2_OC3FE                     ((uint16_t)0x0004)            /*!<Output Compare 3 Fast enable */\r
+#define  TIM_CCMR2_OC3PE                     ((uint16_t)0x0008)            /*!<Output Compare 3 Preload enable */\r
+\r
+#define  TIM_CCMR2_OC3M                      ((uint16_t)0x0070)            /*!<OC3M[2:0] bits (Output Compare 3 Mode) */\r
+#define  TIM_CCMR2_OC3M_0                    ((uint16_t)0x0010)            /*!<Bit 0 */\r
+#define  TIM_CCMR2_OC3M_1                    ((uint16_t)0x0020)            /*!<Bit 1 */\r
+#define  TIM_CCMR2_OC3M_2                    ((uint16_t)0x0040)            /*!<Bit 2 */\r
+\r
+#define  TIM_CCMR2_OC3CE                     ((uint16_t)0x0080)            /*!<Output Compare 3 Clear Enable */\r
+\r
+#define  TIM_CCMR2_CC4S                      ((uint16_t)0x0300)            /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */\r
+#define  TIM_CCMR2_CC4S_0                    ((uint16_t)0x0100)            /*!<Bit 0 */\r
+#define  TIM_CCMR2_CC4S_1                    ((uint16_t)0x0200)            /*!<Bit 1 */\r
+\r
+#define  TIM_CCMR2_OC4FE                     ((uint16_t)0x0400)            /*!<Output Compare 4 Fast enable */\r
+#define  TIM_CCMR2_OC4PE                     ((uint16_t)0x0800)            /*!<Output Compare 4 Preload enable */\r
+\r
+#define  TIM_CCMR2_OC4M                      ((uint16_t)0x7000)            /*!<OC4M[2:0] bits (Output Compare 4 Mode) */\r
+#define  TIM_CCMR2_OC4M_0                    ((uint16_t)0x1000)            /*!<Bit 0 */\r
+#define  TIM_CCMR2_OC4M_1                    ((uint16_t)0x2000)            /*!<Bit 1 */\r
+#define  TIM_CCMR2_OC4M_2                    ((uint16_t)0x4000)            /*!<Bit 2 */\r
+\r
+#define  TIM_CCMR2_OC4CE                     ((uint16_t)0x8000)            /*!<Output Compare 4 Clear Enable */\r
+\r
+/*----------------------------------------------------------------------------*/\r
+\r
+#define  TIM_CCMR2_IC3PSC                    ((uint16_t)0x000C)            /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */\r
+#define  TIM_CCMR2_IC3PSC_0                  ((uint16_t)0x0004)            /*!<Bit 0 */\r
+#define  TIM_CCMR2_IC3PSC_1                  ((uint16_t)0x0008)            /*!<Bit 1 */\r
+\r
+#define  TIM_CCMR2_IC3F                      ((uint16_t)0x00F0)            /*!<IC3F[3:0] bits (Input Capture 3 Filter) */\r
+#define  TIM_CCMR2_IC3F_0                    ((uint16_t)0x0010)            /*!<Bit 0 */\r
+#define  TIM_CCMR2_IC3F_1                    ((uint16_t)0x0020)            /*!<Bit 1 */\r
+#define  TIM_CCMR2_IC3F_2                    ((uint16_t)0x0040)            /*!<Bit 2 */\r
+#define  TIM_CCMR2_IC3F_3                    ((uint16_t)0x0080)            /*!<Bit 3 */\r
+\r
+#define  TIM_CCMR2_IC4PSC                    ((uint16_t)0x0C00)            /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */\r
+#define  TIM_CCMR2_IC4PSC_0                  ((uint16_t)0x0400)            /*!<Bit 0 */\r
+#define  TIM_CCMR2_IC4PSC_1                  ((uint16_t)0x0800)            /*!<Bit 1 */\r
+\r
+#define  TIM_CCMR2_IC4F                      ((uint16_t)0xF000)            /*!<IC4F[3:0] bits (Input Capture 4 Filter) */\r
+#define  TIM_CCMR2_IC4F_0                    ((uint16_t)0x1000)            /*!<Bit 0 */\r
+#define  TIM_CCMR2_IC4F_1                    ((uint16_t)0x2000)            /*!<Bit 1 */\r
+#define  TIM_CCMR2_IC4F_2                    ((uint16_t)0x4000)            /*!<Bit 2 */\r
+#define  TIM_CCMR2_IC4F_3                    ((uint16_t)0x8000)            /*!<Bit 3 */\r
+\r
+/*******************  Bit definition for TIM_CCER register  *******************/\r
+#define  TIM_CCER_CC1E                       ((uint16_t)0x0001)            /*!<Capture/Compare 1 output enable */\r
+#define  TIM_CCER_CC1P                       ((uint16_t)0x0002)            /*!<Capture/Compare 1 output Polarity */\r
+#define  TIM_CCER_CC1NE                      ((uint16_t)0x0004)            /*!<Capture/Compare 1 Complementary output enable */\r
+#define  TIM_CCER_CC1NP                      ((uint16_t)0x0008)            /*!<Capture/Compare 1 Complementary output Polarity */\r
+#define  TIM_CCER_CC2E                       ((uint16_t)0x0010)            /*!<Capture/Compare 2 output enable */\r
+#define  TIM_CCER_CC2P                       ((uint16_t)0x0020)            /*!<Capture/Compare 2 output Polarity */\r
+#define  TIM_CCER_CC2NE                      ((uint16_t)0x0040)            /*!<Capture/Compare 2 Complementary output enable */\r
+#define  TIM_CCER_CC2NP                      ((uint16_t)0x0080)            /*!<Capture/Compare 2 Complementary output Polarity */\r
+#define  TIM_CCER_CC3E                       ((uint16_t)0x0100)            /*!<Capture/Compare 3 output enable */\r
+#define  TIM_CCER_CC3P                       ((uint16_t)0x0200)            /*!<Capture/Compare 3 output Polarity */\r
+#define  TIM_CCER_CC3NE                      ((uint16_t)0x0400)            /*!<Capture/Compare 3 Complementary output enable */\r
+#define  TIM_CCER_CC3NP                      ((uint16_t)0x0800)            /*!<Capture/Compare 3 Complementary output Polarity */\r
+#define  TIM_CCER_CC4E                       ((uint16_t)0x1000)            /*!<Capture/Compare 4 output enable */\r
+#define  TIM_CCER_CC4P                       ((uint16_t)0x2000)            /*!<Capture/Compare 4 output Polarity */\r
+#define  TIM_CCER_CC4NP                      ((uint16_t)0x8000)            /*!<Capture/Compare 4 Complementary output Polarity */\r
+\r
+/*******************  Bit definition for TIM_CNT register  ********************/\r
+#define  TIM_CNT_CNT                         ((uint16_t)0xFFFF)            /*!<Counter Value */\r
+\r
+/*******************  Bit definition for TIM_PSC register  ********************/\r
+#define  TIM_PSC_PSC                         ((uint16_t)0xFFFF)            /*!<Prescaler Value */\r
+\r
+/*******************  Bit definition for TIM_ARR register  ********************/\r
+#define  TIM_ARR_ARR                         ((uint16_t)0xFFFF)            /*!<actual auto-reload Value */\r
+\r
+/*******************  Bit definition for TIM_RCR register  ********************/\r
+#define  TIM_RCR_REP                         ((uint8_t)0xFF)               /*!<Repetition Counter Value */\r
+\r
+/*******************  Bit definition for TIM_CCR1 register  *******************/\r
+#define  TIM_CCR1_CCR1                       ((uint16_t)0xFFFF)            /*!<Capture/Compare 1 Value */\r
+\r
+/*******************  Bit definition for TIM_CCR2 register  *******************/\r
+#define  TIM_CCR2_CCR2                       ((uint16_t)0xFFFF)            /*!<Capture/Compare 2 Value */\r
+\r
+/*******************  Bit definition for TIM_CCR3 register  *******************/\r
+#define  TIM_CCR3_CCR3                       ((uint16_t)0xFFFF)            /*!<Capture/Compare 3 Value */\r
+\r
+/*******************  Bit definition for TIM_CCR4 register  *******************/\r
+#define  TIM_CCR4_CCR4                       ((uint16_t)0xFFFF)            /*!<Capture/Compare 4 Value */\r
+\r
+/*******************  Bit definition for TIM_DCR register  ********************/\r
+#define  TIM_DCR_DBA                         ((uint16_t)0x001F)            /*!<DBA[4:0] bits (DMA Base Address) */\r
+#define  TIM_DCR_DBA_0                       ((uint16_t)0x0001)            /*!<Bit 0 */\r
+#define  TIM_DCR_DBA_1                       ((uint16_t)0x0002)            /*!<Bit 1 */\r
+#define  TIM_DCR_DBA_2                       ((uint16_t)0x0004)            /*!<Bit 2 */\r
+#define  TIM_DCR_DBA_3                       ((uint16_t)0x0008)            /*!<Bit 3 */\r
+#define  TIM_DCR_DBA_4                       ((uint16_t)0x0010)            /*!<Bit 4 */\r
+\r
+#define  TIM_DCR_DBL                         ((uint16_t)0x1F00)            /*!<DBL[4:0] bits (DMA Burst Length) */\r
+#define  TIM_DCR_DBL_0                       ((uint16_t)0x0100)            /*!<Bit 0 */\r
+#define  TIM_DCR_DBL_1                       ((uint16_t)0x0200)            /*!<Bit 1 */\r
+#define  TIM_DCR_DBL_2                       ((uint16_t)0x0400)            /*!<Bit 2 */\r
+#define  TIM_DCR_DBL_3                       ((uint16_t)0x0800)            /*!<Bit 3 */\r
+#define  TIM_DCR_DBL_4                       ((uint16_t)0x1000)            /*!<Bit 4 */\r
+\r
+/*******************  Bit definition for TIM_DMAR register  *******************/\r
+#define  TIM_DMAR_DMAB                       ((uint16_t)0xFFFF)            /*!<DMA register for burst accesses */\r
+\r
+/*******************  Bit definition for TIM_OR register  *********************/\r
+#define  TIM_OR_TI1RMP                       ((uint16_t)0x0003)            /*!<Option register for TI1 Remapping */\r
+#define  TIM_OR_TI1RMP_0                     ((uint16_t)0x0001)            /*!<Bit 0 */\r
+#define  TIM_OR_TI1RMP_1                     ((uint16_t)0x0002)            /*!<Bit 1 */\r
+\r
+/******************************************************************************/\r
+/*                                                                            */\r
+/*         Universal Synchronous Asynchronous Receiver Transmitter            */\r
+/*                                                                            */\r
+/******************************************************************************/\r
+\r
+/*******************  Bit definition for USART_SR register  *******************/\r
+#define  USART_SR_PE                         ((uint16_t)0x0001)            /*!< Parity Error */\r
+#define  USART_SR_FE                         ((uint16_t)0x0002)            /*!< Framing Error */\r
+#define  USART_SR_NE                         ((uint16_t)0x0004)            /*!< Noise Error Flag */\r
+#define  USART_SR_ORE                        ((uint16_t)0x0008)            /*!< OverRun Error */\r
+#define  USART_SR_IDLE                       ((uint16_t)0x0010)            /*!< IDLE line detected */\r
+#define  USART_SR_RXNE                       ((uint16_t)0x0020)            /*!< Read Data Register Not Empty */\r
+#define  USART_SR_TC                         ((uint16_t)0x0040)            /*!< Transmission Complete */\r
+#define  USART_SR_TXE                        ((uint16_t)0x0080)            /*!< Transmit Data Register Empty */\r
+#define  USART_SR_LBD                        ((uint16_t)0x0100)            /*!< LIN Break Detection Flag */\r
+#define  USART_SR_CTS                        ((uint16_t)0x0200)            /*!< CTS Flag */\r
+\r
+/*******************  Bit definition for USART_DR register  *******************/\r
+#define  USART_DR_DR                         ((uint16_t)0x01FF)            /*!< Data value */\r
+\r
+/******************  Bit definition for USART_BRR register  *******************/\r
+#define  USART_BRR_DIV_FRACTION              ((uint16_t)0x000F)            /*!< Fraction of USARTDIV */\r
+#define  USART_BRR_DIV_MANTISSA              ((uint16_t)0xFFF0)            /*!< Mantissa of USARTDIV */\r
+\r
+/******************  Bit definition for USART_CR1 register  *******************/\r
+#define  USART_CR1_SBK                       ((uint16_t)0x0001)            /*!< Send Break */\r
+#define  USART_CR1_RWU                       ((uint16_t)0x0002)            /*!< Receiver wakeup */\r
+#define  USART_CR1_RE                        ((uint16_t)0x0004)            /*!< Receiver Enable */\r
+#define  USART_CR1_TE                        ((uint16_t)0x0008)            /*!< Transmitter Enable */\r
+#define  USART_CR1_IDLEIE                    ((uint16_t)0x0010)            /*!< IDLE Interrupt Enable */\r
+#define  USART_CR1_RXNEIE                    ((uint16_t)0x0020)            /*!< RXNE Interrupt Enable */\r
+#define  USART_CR1_TCIE                      ((uint16_t)0x0040)            /*!< Transmission Complete Interrupt Enable */\r
+#define  USART_CR1_TXEIE                     ((uint16_t)0x0080)            /*!< PE Interrupt Enable */\r
+#define  USART_CR1_PEIE                      ((uint16_t)0x0100)            /*!< PE Interrupt Enable */\r
+#define  USART_CR1_PS                        ((uint16_t)0x0200)            /*!< Parity Selection */\r
+#define  USART_CR1_PCE                       ((uint16_t)0x0400)            /*!< Parity Control Enable */\r
+#define  USART_CR1_WAKE                      ((uint16_t)0x0800)            /*!< Wakeup method */\r
+#define  USART_CR1_M                         ((uint16_t)0x1000)            /*!< Word length */\r
+#define  USART_CR1_UE                        ((uint16_t)0x2000)            /*!< USART Enable */\r
+#define  USART_CR1_OVER8                     ((uint16_t)0x8000)            /*!< Oversampling mode */\r
+\r
+/******************  Bit definition for USART_CR2 register  *******************/\r
+#define  USART_CR2_ADD                       ((uint16_t)0x000F)            /*!< Address of the USART node */\r
+#define  USART_CR2_LBDL                      ((uint16_t)0x0020)            /*!< LIN Break Detection Length */\r
+#define  USART_CR2_LBDIE                     ((uint16_t)0x0040)            /*!< LIN Break Detection Interrupt Enable */\r
+#define  USART_CR2_LBCL                      ((uint16_t)0x0100)            /*!< Last Bit Clock pulse */\r
+#define  USART_CR2_CPHA                      ((uint16_t)0x0200)            /*!< Clock Phase */\r
+#define  USART_CR2_CPOL                      ((uint16_t)0x0400)            /*!< Clock Polarity */\r
+#define  USART_CR2_CLKEN                     ((uint16_t)0x0800)            /*!< Clock Enable */\r
+\r
+#define  USART_CR2_STOP                      ((uint16_t)0x3000)            /*!< STOP[1:0] bits (STOP bits) */\r
+#define  USART_CR2_STOP_0                    ((uint16_t)0x1000)            /*!< Bit 0 */\r
+#define  USART_CR2_STOP_1                    ((uint16_t)0x2000)            /*!< Bit 1 */\r
+\r
+#define  USART_CR2_LINEN                     ((uint16_t)0x4000)            /*!< LIN mode enable */\r
+\r
+/******************  Bit definition for USART_CR3 register  *******************/\r
+#define  USART_CR3_EIE                       ((uint16_t)0x0001)            /*!< Error Interrupt Enable */\r
+#define  USART_CR3_IREN                      ((uint16_t)0x0002)            /*!< IrDA mode Enable */\r
+#define  USART_CR3_IRLP                      ((uint16_t)0x0004)            /*!< IrDA Low-Power */\r
+#define  USART_CR3_HDSEL                     ((uint16_t)0x0008)            /*!< Half-Duplex Selection */\r
+#define  USART_CR3_NACK                      ((uint16_t)0x0010)            /*!< Smartcard NACK enable */\r
+#define  USART_CR3_SCEN                      ((uint16_t)0x0020)            /*!< Smartcard mode enable */\r
+#define  USART_CR3_DMAR                      ((uint16_t)0x0040)            /*!< DMA Enable Receiver */\r
+#define  USART_CR3_DMAT                      ((uint16_t)0x0080)            /*!< DMA Enable Transmitter */\r
+#define  USART_CR3_RTSE                      ((uint16_t)0x0100)            /*!< RTS Enable */\r
+#define  USART_CR3_CTSE                      ((uint16_t)0x0200)            /*!< CTS Enable */\r
+#define  USART_CR3_CTSIE                     ((uint16_t)0x0400)            /*!< CTS Interrupt Enable */\r
+#define  USART_CR3_ONEBIT                    ((uint16_t)0x0800)            /*!< One sample bit method enable */\r
+\r
+/******************  Bit definition for USART_GTPR register  ******************/\r
+#define  USART_GTPR_PSC                      ((uint16_t)0x00FF)            /*!< PSC[7:0] bits (Prescaler value) */\r
+#define  USART_GTPR_PSC_0                    ((uint16_t)0x0001)            /*!< Bit 0 */\r
+#define  USART_GTPR_PSC_1                    ((uint16_t)0x0002)            /*!< Bit 1 */\r
+#define  USART_GTPR_PSC_2                    ((uint16_t)0x0004)            /*!< Bit 2 */\r
+#define  USART_GTPR_PSC_3                    ((uint16_t)0x0008)            /*!< Bit 3 */\r
+#define  USART_GTPR_PSC_4                    ((uint16_t)0x0010)            /*!< Bit 4 */\r
+#define  USART_GTPR_PSC_5                    ((uint16_t)0x0020)            /*!< Bit 5 */\r
+#define  USART_GTPR_PSC_6                    ((uint16_t)0x0040)            /*!< Bit 6 */\r
+#define  USART_GTPR_PSC_7                    ((uint16_t)0x0080)            /*!< Bit 7 */\r
+\r
+#define  USART_GTPR_GT                       ((uint16_t)0xFF00)            /*!< Guard time value */\r
+\r
+/******************************************************************************/\r
+/*                                                                            */\r
+/*                                   USB                                      */\r
+/*                                                                            */\r
+/******************************************************************************/\r
+\r
+/*!<Endpoint-specific registers */\r
+/*******************  Bit definition for USB_EP0R register  *******************/\r
+#define  USB_EP0R_EA                         ((uint16_t)0x000F)            /*!<Endpoint Address */\r
+\r
+#define  USB_EP0R_STAT_TX                    ((uint16_t)0x0030)            /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */\r
+#define  USB_EP0R_STAT_TX_0                  ((uint16_t)0x0010)            /*!<Bit 0 */\r
+#define  USB_EP0R_STAT_TX_1                  ((uint16_t)0x0020)            /*!<Bit 1 */\r
+\r
+#define  USB_EP0R_DTOG_TX                    ((uint16_t)0x0040)            /*!<Data Toggle, for transmission transfers */\r
+#define  USB_EP0R_CTR_TX                     ((uint16_t)0x0080)            /*!<Correct Transfer for transmission */\r
+#define  USB_EP0R_EP_KIND                    ((uint16_t)0x0100)            /*!<Endpoint Kind */\r
+\r
+#define  USB_EP0R_EP_TYPE                    ((uint16_t)0x0600)            /*!<EP_TYPE[1:0] bits (Endpoint type) */\r
+#define  USB_EP0R_EP_TYPE_0                  ((uint16_t)0x0200)            /*!<Bit 0 */\r
+#define  USB_EP0R_EP_TYPE_1                  ((uint16_t)0x0400)            /*!<Bit 1 */\r
+\r
+#define  USB_EP0R_SETUP                      ((uint16_t)0x0800)            /*!<Setup transaction completed */\r
+\r
+#define  USB_EP0R_STAT_RX                    ((uint16_t)0x3000)            /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */\r
+#define  USB_EP0R_STAT_RX_0                  ((uint16_t)0x1000)            /*!<Bit 0 */\r
+#define  USB_EP0R_STAT_RX_1                  ((uint16_t)0x2000)            /*!<Bit 1 */\r
+\r
+#define  USB_EP0R_DTOG_RX                    ((uint16_t)0x4000)            /*!<Data Toggle, for reception transfers */\r
+#define  USB_EP0R_CTR_RX                     ((uint16_t)0x8000)            /*!<Correct Transfer for reception */\r
+\r
+/*******************  Bit definition for USB_EP1R register  *******************/\r
+#define  USB_EP1R_EA                         ((uint16_t)0x000F)            /*!<Endpoint Address */\r
+\r
+#define  USB_EP1R_STAT_TX                    ((uint16_t)0x0030)            /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */\r
+#define  USB_EP1R_STAT_TX_0                  ((uint16_t)0x0010)            /*!<Bit 0 */\r
+#define  USB_EP1R_STAT_TX_1                  ((uint16_t)0x0020)            /*!<Bit 1 */\r
+\r
+#define  USB_EP1R_DTOG_TX                    ((uint16_t)0x0040)            /*!<Data Toggle, for transmission transfers */\r
+#define  USB_EP1R_CTR_TX                     ((uint16_t)0x0080)            /*!<Correct Transfer for transmission */\r
+#define  USB_EP1R_EP_KIND                    ((uint16_t)0x0100)            /*!<Endpoint Kind */\r
+\r
+#define  USB_EP1R_EP_TYPE                    ((uint16_t)0x0600)            /*!<EP_TYPE[1:0] bits (Endpoint type) */\r
+#define  USB_EP1R_EP_TYPE_0                  ((uint16_t)0x0200)            /*!<Bit 0 */\r
+#define  USB_EP1R_EP_TYPE_1                  ((uint16_t)0x0400)            /*!<Bit 1 */\r
+\r
+#define  USB_EP1R_SETUP                      ((uint16_t)0x0800)            /*!<Setup transaction completed */\r
+\r
+#define  USB_EP1R_STAT_RX                    ((uint16_t)0x3000)            /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */\r
+#define  USB_EP1R_STAT_RX_0                  ((uint16_t)0x1000)            /*!<Bit 0 */\r
+#define  USB_EP1R_STAT_RX_1                  ((uint16_t)0x2000)            /*!<Bit 1 */\r
+\r
+#define  USB_EP1R_DTOG_RX                    ((uint16_t)0x4000)            /*!<Data Toggle, for reception transfers */\r
+#define  USB_EP1R_CTR_RX                     ((uint16_t)0x8000)            /*!<Correct Transfer for reception */\r
+\r
+/*******************  Bit definition for USB_EP2R register  *******************/\r
+#define  USB_EP2R_EA                         ((uint16_t)0x000F)            /*!<Endpoint Address */\r
+\r
+#define  USB_EP2R_STAT_TX                    ((uint16_t)0x0030)            /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */\r
+#define  USB_EP2R_STAT_TX_0                  ((uint16_t)0x0010)            /*!<Bit 0 */\r
+#define  USB_EP2R_STAT_TX_1                  ((uint16_t)0x0020)            /*!<Bit 1 */\r
+\r
+#define  USB_EP2R_DTOG_TX                    ((uint16_t)0x0040)            /*!<Data Toggle, for transmission transfers */\r
+#define  USB_EP2R_CTR_TX                     ((uint16_t)0x0080)            /*!<Correct Transfer for transmission */\r
+#define  USB_EP2R_EP_KIND                    ((uint16_t)0x0100)            /*!<Endpoint Kind */\r
+\r
+#define  USB_EP2R_EP_TYPE                    ((uint16_t)0x0600)            /*!<EP_TYPE[1:0] bits (Endpoint type) */\r
+#define  USB_EP2R_EP_TYPE_0                  ((uint16_t)0x0200)            /*!<Bit 0 */\r
+#define  USB_EP2R_EP_TYPE_1                  ((uint16_t)0x0400)            /*!<Bit 1 */\r
+\r
+#define  USB_EP2R_SETUP                      ((uint16_t)0x0800)            /*!<Setup transaction completed */\r
+\r
+#define  USB_EP2R_STAT_RX                    ((uint16_t)0x3000)            /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */\r
+#define  USB_EP2R_STAT_RX_0                  ((uint16_t)0x1000)            /*!<Bit 0 */\r
+#define  USB_EP2R_STAT_RX_1                  ((uint16_t)0x2000)            /*!<Bit 1 */\r
+\r
+#define  USB_EP2R_DTOG_RX                    ((uint16_t)0x4000)            /*!<Data Toggle, for reception transfers */\r
+#define  USB_EP2R_CTR_RX                     ((uint16_t)0x8000)            /*!<Correct Transfer for reception */\r
+\r
+/*******************  Bit definition for USB_EP3R register  *******************/\r
+#define  USB_EP3R_EA                         ((uint16_t)0x000F)            /*!<Endpoint Address */\r
+\r
+#define  USB_EP3R_STAT_TX                    ((uint16_t)0x0030)            /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */\r
+#define  USB_EP3R_STAT_TX_0                  ((uint16_t)0x0010)            /*!<Bit 0 */\r
+#define  USB_EP3R_STAT_TX_1                  ((uint16_t)0x0020)            /*!<Bit 1 */\r
+\r
+#define  USB_EP3R_DTOG_TX                    ((uint16_t)0x0040)            /*!<Data Toggle, for transmission transfers */\r
+#define  USB_EP3R_CTR_TX                     ((uint16_t)0x0080)            /*!<Correct Transfer for transmission */\r
+#define  USB_EP3R_EP_KIND                    ((uint16_t)0x0100)            /*!<Endpoint Kind */\r
+\r
+#define  USB_EP3R_EP_TYPE                    ((uint16_t)0x0600)            /*!<EP_TYPE[1:0] bits (Endpoint type) */\r
+#define  USB_EP3R_EP_TYPE_0                  ((uint16_t)0x0200)            /*!<Bit 0 */\r
+#define  USB_EP3R_EP_TYPE_1                  ((uint16_t)0x0400)            /*!<Bit 1 */\r
+\r
+#define  USB_EP3R_SETUP                      ((uint16_t)0x0800)            /*!<Setup transaction completed */\r
+\r
+#define  USB_EP3R_STAT_RX                    ((uint16_t)0x3000)            /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */\r
+#define  USB_EP3R_STAT_RX_0                  ((uint16_t)0x1000)            /*!<Bit 0 */\r
+#define  USB_EP3R_STAT_RX_1                  ((uint16_t)0x2000)            /*!<Bit 1 */\r
+\r
+#define  USB_EP3R_DTOG_RX                    ((uint16_t)0x4000)            /*!<Data Toggle, for reception transfers */\r
+#define  USB_EP3R_CTR_RX                     ((uint16_t)0x8000)            /*!<Correct Transfer for reception */\r
+\r
+/*******************  Bit definition for USB_EP4R register  *******************/\r
+#define  USB_EP4R_EA                         ((uint16_t)0x000F)            /*!<Endpoint Address */\r
+\r
+#define  USB_EP4R_STAT_TX                    ((uint16_t)0x0030)            /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */\r
+#define  USB_EP4R_STAT_TX_0                  ((uint16_t)0x0010)            /*!<Bit 0 */\r
+#define  USB_EP4R_STAT_TX_1                  ((uint16_t)0x0020)            /*!<Bit 1 */\r
+\r
+#define  USB_EP4R_DTOG_TX                    ((uint16_t)0x0040)            /*!<Data Toggle, for transmission transfers */\r
+#define  USB_EP4R_CTR_TX                     ((uint16_t)0x0080)            /*!<Correct Transfer for transmission */\r
+#define  USB_EP4R_EP_KIND                    ((uint16_t)0x0100)            /*!<Endpoint Kind */\r
+\r
+#define  USB_EP4R_EP_TYPE                    ((uint16_t)0x0600)            /*!<EP_TYPE[1:0] bits (Endpoint type) */\r
+#define  USB_EP4R_EP_TYPE_0                  ((uint16_t)0x0200)            /*!<Bit 0 */\r
+#define  USB_EP4R_EP_TYPE_1                  ((uint16_t)0x0400)            /*!<Bit 1 */\r
+\r
+#define  USB_EP4R_SETUP                      ((uint16_t)0x0800)            /*!<Setup transaction completed */\r
+\r
+#define  USB_EP4R_STAT_RX                    ((uint16_t)0x3000)            /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */\r
+#define  USB_EP4R_STAT_RX_0                  ((uint16_t)0x1000)            /*!<Bit 0 */\r
+#define  USB_EP4R_STAT_RX_1                  ((uint16_t)0x2000)            /*!<Bit 1 */\r
+\r
+#define  USB_EP4R_DTOG_RX                    ((uint16_t)0x4000)            /*!<Data Toggle, for reception transfers */\r
+#define  USB_EP4R_CTR_RX                     ((uint16_t)0x8000)            /*!<Correct Transfer for reception */\r
+\r
+/*******************  Bit definition for USB_EP5R register  *******************/\r
+#define  USB_EP5R_EA                         ((uint16_t)0x000F)            /*!<Endpoint Address */\r
+\r
+#define  USB_EP5R_STAT_TX                    ((uint16_t)0x0030)            /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */\r
+#define  USB_EP5R_STAT_TX_0                  ((uint16_t)0x0010)            /*!<Bit 0 */\r
+#define  USB_EP5R_STAT_TX_1                  ((uint16_t)0x0020)            /*!<Bit 1 */\r
+\r
+#define  USB_EP5R_DTOG_TX                    ((uint16_t)0x0040)            /*!<Data Toggle, for transmission transfers */\r
+#define  USB_EP5R_CTR_TX                     ((uint16_t)0x0080)            /*!<Correct Transfer for transmission */\r
+#define  USB_EP5R_EP_KIND                    ((uint16_t)0x0100)            /*!<Endpoint Kind */\r
+\r
+#define  USB_EP5R_EP_TYPE                    ((uint16_t)0x0600)            /*!<EP_TYPE[1:0] bits (Endpoint type) */\r
+#define  USB_EP5R_EP_TYPE_0                  ((uint16_t)0x0200)            /*!<Bit 0 */\r
+#define  USB_EP5R_EP_TYPE_1                  ((uint16_t)0x0400)            /*!<Bit 1 */\r
+\r
+#define  USB_EP5R_SETUP                      ((uint16_t)0x0800)            /*!<Setup transaction completed */\r
+\r
+#define  USB_EP5R_STAT_RX                    ((uint16_t)0x3000)            /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */\r
+#define  USB_EP5R_STAT_RX_0                  ((uint16_t)0x1000)            /*!<Bit 0 */\r
+#define  USB_EP5R_STAT_RX_1                  ((uint16_t)0x2000)            /*!<Bit 1 */\r
+\r
+#define  USB_EP5R_DTOG_RX                    ((uint16_t)0x4000)            /*!<Data Toggle, for reception transfers */\r
+#define  USB_EP5R_CTR_RX                     ((uint16_t)0x8000)            /*!<Correct Transfer for reception */\r
+\r
+/*******************  Bit definition for USB_EP6R register  *******************/\r
+#define  USB_EP6R_EA                         ((uint16_t)0x000F)            /*!<Endpoint Address */\r
+\r
+#define  USB_EP6R_STAT_TX                    ((uint16_t)0x0030)            /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */\r
+#define  USB_EP6R_STAT_TX_0                  ((uint16_t)0x0010)            /*!<Bit 0 */\r
+#define  USB_EP6R_STAT_TX_1                  ((uint16_t)0x0020)            /*!<Bit 1 */\r
+\r
+#define  USB_EP6R_DTOG_TX                    ((uint16_t)0x0040)            /*!<Data Toggle, for transmission transfers */\r
+#define  USB_EP6R_CTR_TX                     ((uint16_t)0x0080)            /*!<Correct Transfer for transmission */\r
+#define  USB_EP6R_EP_KIND                    ((uint16_t)0x0100)            /*!<Endpoint Kind */\r
+\r
+#define  USB_EP6R_EP_TYPE                    ((uint16_t)0x0600)            /*!<EP_TYPE[1:0] bits (Endpoint type) */\r
+#define  USB_EP6R_EP_TYPE_0                  ((uint16_t)0x0200)            /*!<Bit 0 */\r
+#define  USB_EP6R_EP_TYPE_1                  ((uint16_t)0x0400)            /*!<Bit 1 */\r
+\r
+#define  USB_EP6R_SETUP                      ((uint16_t)0x0800)            /*!<Setup transaction completed */\r
+\r
+#define  USB_EP6R_STAT_RX                    ((uint16_t)0x3000)            /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */\r
+#define  USB_EP6R_STAT_RX_0                  ((uint16_t)0x1000)            /*!<Bit 0 */\r
+#define  USB_EP6R_STAT_RX_1                  ((uint16_t)0x2000)            /*!<Bit 1 */\r
+\r
+#define  USB_EP6R_DTOG_RX                    ((uint16_t)0x4000)            /*!<Data Toggle, for reception transfers */\r
+#define  USB_EP6R_CTR_RX                     ((uint16_t)0x8000)            /*!<Correct Transfer for reception */\r
+\r
+/*******************  Bit definition for USB_EP7R register  *******************/\r
+#define  USB_EP7R_EA                         ((uint16_t)0x000F)            /*!<Endpoint Address */\r
+\r
+#define  USB_EP7R_STAT_TX                    ((uint16_t)0x0030)            /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */\r
+#define  USB_EP7R_STAT_TX_0                  ((uint16_t)0x0010)            /*!<Bit 0 */\r
+#define  USB_EP7R_STAT_TX_1                  ((uint16_t)0x0020)            /*!<Bit 1 */\r
+\r
+#define  USB_EP7R_DTOG_TX                    ((uint16_t)0x0040)            /*!<Data Toggle, for transmission transfers */\r
+#define  USB_EP7R_CTR_TX                     ((uint16_t)0x0080)            /*!<Correct Transfer for transmission */\r
+#define  USB_EP7R_EP_KIND                    ((uint16_t)0x0100)            /*!<Endpoint Kind */\r
+\r
+#define  USB_EP7R_EP_TYPE                    ((uint16_t)0x0600)            /*!<EP_TYPE[1:0] bits (Endpoint type) */\r
+#define  USB_EP7R_EP_TYPE_0                  ((uint16_t)0x0200)            /*!<Bit 0 */\r
+#define  USB_EP7R_EP_TYPE_1                  ((uint16_t)0x0400)            /*!<Bit 1 */\r
+\r
+#define  USB_EP7R_SETUP                      ((uint16_t)0x0800)            /*!<Setup transaction completed */\r
+\r
+#define  USB_EP7R_STAT_RX                    ((uint16_t)0x3000)            /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */\r
+#define  USB_EP7R_STAT_RX_0                  ((uint16_t)0x1000)            /*!<Bit 0 */\r
+#define  USB_EP7R_STAT_RX_1                  ((uint16_t)0x2000)            /*!<Bit 1 */\r
+\r
+#define  USB_EP7R_DTOG_RX                    ((uint16_t)0x4000)            /*!<Data Toggle, for reception transfers */\r
+#define  USB_EP7R_CTR_RX                     ((uint16_t)0x8000)            /*!<Correct Transfer for reception */\r
+\r
+/*!<Common registers */\r
+/*******************  Bit definition for USB_CNTR register  *******************/\r
+#define  USB_CNTR_FRES                       ((uint16_t)0x0001)            /*!<Force USB Reset */\r
+#define  USB_CNTR_PDWN                       ((uint16_t)0x0002)            /*!<Power down */\r
+#define  USB_CNTR_LP_MODE                    ((uint16_t)0x0004)            /*!<Low-power mode */\r
+#define  USB_CNTR_FSUSP                      ((uint16_t)0x0008)            /*!<Force suspend */\r
+#define  USB_CNTR_RESUME                     ((uint16_t)0x0010)            /*!<Resume request */\r
+#define  USB_CNTR_ESOFM                      ((uint16_t)0x0100)            /*!<Expected Start Of Frame Interrupt Mask */\r
+#define  USB_CNTR_SOFM                       ((uint16_t)0x0200)            /*!<Start Of Frame Interrupt Mask */\r
+#define  USB_CNTR_RESETM                     ((uint16_t)0x0400)            /*!<RESET Interrupt Mask */\r
+#define  USB_CNTR_SUSPM                      ((uint16_t)0x0800)            /*!<Suspend mode Interrupt Mask */\r
+#define  USB_CNTR_WKUPM                      ((uint16_t)0x1000)            /*!<Wakeup Interrupt Mask */\r
+#define  USB_CNTR_ERRM                       ((uint16_t)0x2000)            /*!<Error Interrupt Mask */\r
+#define  USB_CNTR_PMAOVRM                    ((uint16_t)0x4000)            /*!<Packet Memory Area Over / Underrun Interrupt Mask */\r
+#define  USB_CNTR_CTRM                       ((uint16_t)0x8000)            /*!<Correct Transfer Interrupt Mask */\r
+\r
+/*******************  Bit definition for USB_ISTR register  *******************/\r
+#define  USB_ISTR_EP_ID                      ((uint16_t)0x000F)            /*!<Endpoint Identifier */\r
+#define  USB_ISTR_DIR                        ((uint16_t)0x0010)            /*!<Direction of transaction */\r
+#define  USB_ISTR_ESOF                       ((uint16_t)0x0100)            /*!<Expected Start Of Frame */\r
+#define  USB_ISTR_SOF                        ((uint16_t)0x0200)            /*!<Start Of Frame */\r
+#define  USB_ISTR_RESET                      ((uint16_t)0x0400)            /*!<USB RESET request */\r
+#define  USB_ISTR_SUSP                       ((uint16_t)0x0800)            /*!<Suspend mode request */\r
+#define  USB_ISTR_WKUP                       ((uint16_t)0x1000)            /*!<Wake up */\r
+#define  USB_ISTR_ERR                        ((uint16_t)0x2000)            /*!<Error */\r
+#define  USB_ISTR_PMAOVR                     ((uint16_t)0x4000)            /*!<Packet Memory Area Over / Underrun */\r
+#define  USB_ISTR_CTR                        ((uint16_t)0x8000)            /*!<Correct Transfer */\r
+\r
+/*******************  Bit definition for USB_FNR register  ********************/\r
+#define  USB_FNR_FN                          ((uint16_t)0x07FF)            /*!<Frame Number */\r
+#define  USB_FNR_LSOF                        ((uint16_t)0x1800)            /*!<Lost SOF */\r
+#define  USB_FNR_LCK                         ((uint16_t)0x2000)            /*!<Locked */\r
+#define  USB_FNR_RXDM                        ((uint16_t)0x4000)            /*!<Receive Data - Line Status */\r
+#define  USB_FNR_RXDP                        ((uint16_t)0x8000)            /*!<Receive Data + Line Status */\r
+\r
+/******************  Bit definition for USB_DADDR register  *******************/\r
+#define  USB_DADDR_ADD                       ((uint8_t)0x7F)               /*!<ADD[6:0] bits (Device Address) */\r
+#define  USB_DADDR_ADD0                      ((uint8_t)0x01)               /*!<Bit 0 */\r
+#define  USB_DADDR_ADD1                      ((uint8_t)0x02)               /*!<Bit 1 */\r
+#define  USB_DADDR_ADD2                      ((uint8_t)0x04)               /*!<Bit 2 */\r
+#define  USB_DADDR_ADD3                      ((uint8_t)0x08)               /*!<Bit 3 */\r
+#define  USB_DADDR_ADD4                      ((uint8_t)0x10)               /*!<Bit 4 */\r
+#define  USB_DADDR_ADD5                      ((uint8_t)0x20)               /*!<Bit 5 */\r
+#define  USB_DADDR_ADD6                      ((uint8_t)0x40)               /*!<Bit 6 */\r
+\r
+#define  USB_DADDR_EF                        ((uint8_t)0x80)               /*!<Enable Function */\r
+\r
+/******************  Bit definition for USB_BTABLE register  ******************/    \r
+#define  USB_BTABLE_BTABLE                   ((uint16_t)0xFFF8)            /*!<Buffer Table */\r
+\r
+/*!< Buffer descriptor table */\r
+/*****************  Bit definition for USB_ADDR0_TX register  *****************/\r
+#define  USB_ADDR0_TX_ADDR0_TX               ((uint16_t)0xFFFE)            /*!< Transmission Buffer Address 0 */\r
+\r
+/*****************  Bit definition for USB_ADDR1_TX register  *****************/\r
+#define  USB_ADDR1_TX_ADDR1_TX               ((uint16_t)0xFFFE)            /*!< Transmission Buffer Address 1 */\r
+\r
+/*****************  Bit definition for USB_ADDR2_TX register  *****************/\r
+#define  USB_ADDR2_TX_ADDR2_TX               ((uint16_t)0xFFFE)            /*!< Transmission Buffer Address 2 */\r
+\r
+/*****************  Bit definition for USB_ADDR3_TX register  *****************/\r
+#define  USB_ADDR3_TX_ADDR3_TX               ((uint16_t)0xFFFE)            /*!< Transmission Buffer Address 3 */\r
+\r
+/*****************  Bit definition for USB_ADDR4_TX register  *****************/\r
+#define  USB_ADDR4_TX_ADDR4_TX               ((uint16_t)0xFFFE)            /*!< Transmission Buffer Address 4 */\r
+\r
+/*****************  Bit definition for USB_ADDR5_TX register  *****************/\r
+#define  USB_ADDR5_TX_ADDR5_TX               ((uint16_t)0xFFFE)            /*!< Transmission Buffer Address 5 */\r
+\r
+/*****************  Bit definition for USB_ADDR6_TX register  *****************/\r
+#define  USB_ADDR6_TX_ADDR6_TX               ((uint16_t)0xFFFE)            /*!< Transmission Buffer Address 6 */\r
+\r
+/*****************  Bit definition for USB_ADDR7_TX register  *****************/\r
+#define  USB_ADDR7_TX_ADDR7_TX               ((uint16_t)0xFFFE)            /*!< Transmission Buffer Address 7 */\r
+\r
+/*----------------------------------------------------------------------------*/\r
+\r
+/*****************  Bit definition for USB_COUNT0_TX register  ****************/\r
+#define  USB_COUNT0_TX_COUNT0_TX             ((uint16_t)0x03FF)            /*!< Transmission Byte Count 0 */\r
+\r
+/*****************  Bit definition for USB_COUNT1_TX register  ****************/\r
+#define  USB_COUNT1_TX_COUNT1_TX             ((uint16_t)0x03FF)            /*!< Transmission Byte Count 1 */\r
+\r
+/*****************  Bit definition for USB_COUNT2_TX register  ****************/\r
+#define  USB_COUNT2_TX_COUNT2_TX             ((uint16_t)0x03FF)            /*!< Transmission Byte Count 2 */\r
+\r
+/*****************  Bit definition for USB_COUNT3_TX register  ****************/\r
+#define  USB_COUNT3_TX_COUNT3_TX             ((uint16_t)0x03FF)            /*!< Transmission Byte Count 3 */\r
+\r
+/*****************  Bit definition for USB_COUNT4_TX register  ****************/\r
+#define  USB_COUNT4_TX_COUNT4_TX             ((uint16_t)0x03FF)            /*!< Transmission Byte Count 4 */\r
+\r
+/*****************  Bit definition for USB_COUNT5_TX register  ****************/\r
+#define  USB_COUNT5_TX_COUNT5_TX             ((uint16_t)0x03FF)            /*!< Transmission Byte Count 5 */\r
+\r
+/*****************  Bit definition for USB_COUNT6_TX register  ****************/\r
+#define  USB_COUNT6_TX_COUNT6_TX             ((uint16_t)0x03FF)            /*!< Transmission Byte Count 6 */\r
+\r
+/*****************  Bit definition for USB_COUNT7_TX register  ****************/\r
+#define  USB_COUNT7_TX_COUNT7_TX             ((uint16_t)0x03FF)            /*!< Transmission Byte Count 7 */\r
+\r
+/*----------------------------------------------------------------------------*/\r
+\r
+/****************  Bit definition for USB_COUNT0_TX_0 register  ***************/\r
+#define  USB_COUNT0_TX_0_COUNT0_TX_0         ((uint32_t)0x000003FF)        /*!< Transmission Byte Count 0 (low) */\r
+\r
+/****************  Bit definition for USB_COUNT0_TX_1 register  ***************/\r
+#define  USB_COUNT0_TX_1_COUNT0_TX_1         ((uint32_t)0x03FF0000)        /*!< Transmission Byte Count 0 (high) */\r
+\r
+/****************  Bit definition for USB_COUNT1_TX_0 register  ***************/\r
+#define  USB_COUNT1_TX_0_COUNT1_TX_0          ((uint32_t)0x000003FF)        /*!< Transmission Byte Count 1 (low) */\r
+\r
+/****************  Bit definition for USB_COUNT1_TX_1 register  ***************/\r
+#define  USB_COUNT1_TX_1_COUNT1_TX_1          ((uint32_t)0x03FF0000)        /*!< Transmission Byte Count 1 (high) */\r
+\r
+/****************  Bit definition for USB_COUNT2_TX_0 register  ***************/\r
+#define  USB_COUNT2_TX_0_COUNT2_TX_0         ((uint32_t)0x000003FF)        /*!< Transmission Byte Count 2 (low) */\r
+\r
+/****************  Bit definition for USB_COUNT2_TX_1 register  ***************/\r
+#define  USB_COUNT2_TX_1_COUNT2_TX_1         ((uint32_t)0x03FF0000)        /*!< Transmission Byte Count 2 (high) */\r
+\r
+/****************  Bit definition for USB_COUNT3_TX_0 register  ***************/\r
+#define  USB_COUNT3_TX_0_COUNT3_TX_0         ((uint16_t)0x000003FF)        /*!< Transmission Byte Count 3 (low) */\r
+\r
+/****************  Bit definition for USB_COUNT3_TX_1 register  ***************/\r
+#define  USB_COUNT3_TX_1_COUNT3_TX_1         ((uint16_t)0x03FF0000)        /*!< Transmission Byte Count 3 (high) */\r
+\r
+/****************  Bit definition for USB_COUNT4_TX_0 register  ***************/\r
+#define  USB_COUNT4_TX_0_COUNT4_TX_0         ((uint32_t)0x000003FF)        /*!< Transmission Byte Count 4 (low) */\r
+\r
+/****************  Bit definition for USB_COUNT4_TX_1 register  ***************/\r
+#define  USB_COUNT4_TX_1_COUNT4_TX_1         ((uint32_t)0x03FF0000)        /*!< Transmission Byte Count 4 (high) */\r
+\r
+/****************  Bit definition for USB_COUNT5_TX_0 register  ***************/\r
+#define  USB_COUNT5_TX_0_COUNT5_TX_0         ((uint32_t)0x000003FF)        /*!< Transmission Byte Count 5 (low) */\r
+\r
+/****************  Bit definition for USB_COUNT5_TX_1 register  ***************/\r
+#define  USB_COUNT5_TX_1_COUNT5_TX_1         ((uint32_t)0x03FF0000)        /*!< Transmission Byte Count 5 (high) */\r
+\r
+/****************  Bit definition for USB_COUNT6_TX_0 register  ***************/\r
+#define  USB_COUNT6_TX_0_COUNT6_TX_0         ((uint32_t)0x000003FF)        /*!< Transmission Byte Count 6 (low) */\r
+\r
+/****************  Bit definition for USB_COUNT6_TX_1 register  ***************/\r
+#define  USB_COUNT6_TX_1_COUNT6_TX_1         ((uint32_t)0x03FF0000)        /*!< Transmission Byte Count 6 (high) */\r
+\r
+/****************  Bit definition for USB_COUNT7_TX_0 register  ***************/\r
+#define  USB_COUNT7_TX_0_COUNT7_TX_0         ((uint32_t)0x000003FF)        /*!< Transmission Byte Count 7 (low) */\r
+\r
+/****************  Bit definition for USB_COUNT7_TX_1 register  ***************/\r
+#define  USB_COUNT7_TX_1_COUNT7_TX_1         ((uint32_t)0x03FF0000)        /*!< Transmission Byte Count 7 (high) */\r
+\r
+/*----------------------------------------------------------------------------*/\r
+\r
+/*****************  Bit definition for USB_ADDR0_RX register  *****************/\r
+#define  USB_ADDR0_RX_ADDR0_RX               ((uint16_t)0xFFFE)            /*!< Reception Buffer Address 0 */\r
+\r
+/*****************  Bit definition for USB_ADDR1_RX register  *****************/\r
+#define  USB_ADDR1_RX_ADDR1_RX               ((uint16_t)0xFFFE)            /*!< Reception Buffer Address 1 */\r
+\r
+/*****************  Bit definition for USB_ADDR2_RX register  *****************/\r
+#define  USB_ADDR2_RX_ADDR2_RX               ((uint16_t)0xFFFE)            /*!< Reception Buffer Address 2 */\r
+\r
+/*****************  Bit definition for USB_ADDR3_RX register  *****************/\r
+#define  USB_ADDR3_RX_ADDR3_RX               ((uint16_t)0xFFFE)            /*!< Reception Buffer Address 3 */\r
+\r
+/*****************  Bit definition for USB_ADDR4_RX register  *****************/\r
+#define  USB_ADDR4_RX_ADDR4_RX               ((uint16_t)0xFFFE)            /*!< Reception Buffer Address 4 */\r
+\r
+/*****************  Bit definition for USB_ADDR5_RX register  *****************/\r
+#define  USB_ADDR5_RX_ADDR5_RX               ((uint16_t)0xFFFE)            /*!< Reception Buffer Address 5 */\r
+\r
+/*****************  Bit definition for USB_ADDR6_RX register  *****************/\r
+#define  USB_ADDR6_RX_ADDR6_RX               ((uint16_t)0xFFFE)            /*!< Reception Buffer Address 6 */\r
+\r
+/*****************  Bit definition for USB_ADDR7_RX register  *****************/\r
+#define  USB_ADDR7_RX_ADDR7_RX               ((uint16_t)0xFFFE)            /*!< Reception Buffer Address 7 */\r
+\r
+/*----------------------------------------------------------------------------*/\r
+\r
+/*****************  Bit definition for USB_COUNT0_RX register  ****************/\r
+#define  USB_COUNT0_RX_COUNT0_RX             ((uint16_t)0x03FF)            /*!< Reception Byte Count */\r
+\r
+#define  USB_COUNT0_RX_NUM_BLOCK             ((uint16_t)0x7C00)            /*!< NUM_BLOCK[4:0] bits (Number of blocks) */\r
+#define  USB_COUNT0_RX_NUM_BLOCK_0           ((uint16_t)0x0400)            /*!< Bit 0 */\r
+#define  USB_COUNT0_RX_NUM_BLOCK_1           ((uint16_t)0x0800)            /*!< Bit 1 */\r
+#define  USB_COUNT0_RX_NUM_BLOCK_2           ((uint16_t)0x1000)            /*!< Bit 2 */\r
+#define  USB_COUNT0_RX_NUM_BLOCK_3           ((uint16_t)0x2000)            /*!< Bit 3 */\r
+#define  USB_COUNT0_RX_NUM_BLOCK_4           ((uint16_t)0x4000)            /*!< Bit 4 */\r
+\r
+#define  USB_COUNT0_RX_BLSIZE                ((uint16_t)0x8000)            /*!< BLock SIZE */\r
+\r
+/*****************  Bit definition for USB_COUNT1_RX register  ****************/\r
+#define  USB_COUNT1_RX_COUNT1_RX             ((uint16_t)0x03FF)            /*!< Reception Byte Count */\r
+\r
+#define  USB_COUNT1_RX_NUM_BLOCK             ((uint16_t)0x7C00)            /*!< NUM_BLOCK[4:0] bits (Number of blocks) */\r
+#define  USB_COUNT1_RX_NUM_BLOCK_0           ((uint16_t)0x0400)            /*!< Bit 0 */\r
+#define  USB_COUNT1_RX_NUM_BLOCK_1           ((uint16_t)0x0800)            /*!< Bit 1 */\r
+#define  USB_COUNT1_RX_NUM_BLOCK_2           ((uint16_t)0x1000)            /*!< Bit 2 */\r
+#define  USB_COUNT1_RX_NUM_BLOCK_3           ((uint16_t)0x2000)            /*!< Bit 3 */\r
+#define  USB_COUNT1_RX_NUM_BLOCK_4           ((uint16_t)0x4000)            /*!< Bit 4 */\r
+\r
+#define  USB_COUNT1_RX_BLSIZE                ((uint16_t)0x8000)            /*!< BLock SIZE */\r
+\r
+/*****************  Bit definition for USB_COUNT2_RX register  ****************/\r
+#define  USB_COUNT2_RX_COUNT2_RX             ((uint16_t)0x03FF)            /*!< Reception Byte Count */\r
+\r
+#define  USB_COUNT2_RX_NUM_BLOCK             ((uint16_t)0x7C00)            /*!< NUM_BLOCK[4:0] bits (Number of blocks) */\r
+#define  USB_COUNT2_RX_NUM_BLOCK_0           ((uint16_t)0x0400)            /*!< Bit 0 */\r
+#define  USB_COUNT2_RX_NUM_BLOCK_1           ((uint16_t)0x0800)            /*!< Bit 1 */\r
+#define  USB_COUNT2_RX_NUM_BLOCK_2           ((uint16_t)0x1000)            /*!< Bit 2 */\r
+#define  USB_COUNT2_RX_NUM_BLOCK_3           ((uint16_t)0x2000)            /*!< Bit 3 */\r
+#define  USB_COUNT2_RX_NUM_BLOCK_4           ((uint16_t)0x4000)            /*!< Bit 4 */\r
+\r
+#define  USB_COUNT2_RX_BLSIZE                ((uint16_t)0x8000)            /*!< BLock SIZE */\r
+\r
+/*****************  Bit definition for USB_COUNT3_RX register  ****************/\r
+#define  USB_COUNT3_RX_COUNT3_RX             ((uint16_t)0x03FF)            /*!< Reception Byte Count */\r
+\r
+#define  USB_COUNT3_RX_NUM_BLOCK             ((uint16_t)0x7C00)            /*!< NUM_BLOCK[4:0] bits (Number of blocks) */\r
+#define  USB_COUNT3_RX_NUM_BLOCK_0           ((uint16_t)0x0400)            /*!< Bit 0 */\r
+#define  USB_COUNT3_RX_NUM_BLOCK_1           ((uint16_t)0x0800)            /*!< Bit 1 */\r
+#define  USB_COUNT3_RX_NUM_BLOCK_2           ((uint16_t)0x1000)            /*!< Bit 2 */\r
+#define  USB_COUNT3_RX_NUM_BLOCK_3           ((uint16_t)0x2000)            /*!< Bit 3 */\r
+#define  USB_COUNT3_RX_NUM_BLOCK_4           ((uint16_t)0x4000)            /*!< Bit 4 */\r
+\r
+#define  USB_COUNT3_RX_BLSIZE                ((uint16_t)0x8000)            /*!< BLock SIZE */\r
+\r
+/*****************  Bit definition for USB_COUNT4_RX register  ****************/\r
+#define  USB_COUNT4_RX_COUNT4_RX             ((uint16_t)0x03FF)            /*!< Reception Byte Count */\r
+\r
+#define  USB_COUNT4_RX_NUM_BLOCK             ((uint16_t)0x7C00)            /*!< NUM_BLOCK[4:0] bits (Number of blocks) */\r
+#define  USB_COUNT4_RX_NUM_BLOCK_0           ((uint16_t)0x0400)            /*!< Bit 0 */\r
+#define  USB_COUNT4_RX_NUM_BLOCK_1           ((uint16_t)0x0800)            /*!< Bit 1 */\r
+#define  USB_COUNT4_RX_NUM_BLOCK_2           ((uint16_t)0x1000)            /*!< Bit 2 */\r
+#define  USB_COUNT4_RX_NUM_BLOCK_3           ((uint16_t)0x2000)            /*!< Bit 3 */\r
+#define  USB_COUNT4_RX_NUM_BLOCK_4           ((uint16_t)0x4000)            /*!< Bit 4 */\r
+\r
+#define  USB_COUNT4_RX_BLSIZE                ((uint16_t)0x8000)            /*!< BLock SIZE */\r
+\r
+/*****************  Bit definition for USB_COUNT5_RX register  ****************/\r
+#define  USB_COUNT5_RX_COUNT5_RX             ((uint16_t)0x03FF)            /*!< Reception Byte Count */\r
+\r
+#define  USB_COUNT5_RX_NUM_BLOCK             ((uint16_t)0x7C00)            /*!< NUM_BLOCK[4:0] bits (Number of blocks) */\r
+#define  USB_COUNT5_RX_NUM_BLOCK_0           ((uint16_t)0x0400)            /*!< Bit 0 */\r
+#define  USB_COUNT5_RX_NUM_BLOCK_1           ((uint16_t)0x0800)            /*!< Bit 1 */\r
+#define  USB_COUNT5_RX_NUM_BLOCK_2           ((uint16_t)0x1000)            /*!< Bit 2 */\r
+#define  USB_COUNT5_RX_NUM_BLOCK_3           ((uint16_t)0x2000)            /*!< Bit 3 */\r
+#define  USB_COUNT5_RX_NUM_BLOCK_4           ((uint16_t)0x4000)            /*!< Bit 4 */\r
+\r
+#define  USB_COUNT5_RX_BLSIZE                ((uint16_t)0x8000)            /*!< BLock SIZE */\r
+\r
+/*****************  Bit definition for USB_COUNT6_RX register  ****************/\r
+#define  USB_COUNT6_RX_COUNT6_RX             ((uint16_t)0x03FF)            /*!< Reception Byte Count */\r
+\r
+#define  USB_COUNT6_RX_NUM_BLOCK             ((uint16_t)0x7C00)            /*!< NUM_BLOCK[4:0] bits (Number of blocks) */\r
+#define  USB_COUNT6_RX_NUM_BLOCK_0           ((uint16_t)0x0400)            /*!< Bit 0 */\r
+#define  USB_COUNT6_RX_NUM_BLOCK_1           ((uint16_t)0x0800)            /*!< Bit 1 */\r
+#define  USB_COUNT6_RX_NUM_BLOCK_2           ((uint16_t)0x1000)            /*!< Bit 2 */\r
+#define  USB_COUNT6_RX_NUM_BLOCK_3           ((uint16_t)0x2000)            /*!< Bit 3 */\r
+#define  USB_COUNT6_RX_NUM_BLOCK_4           ((uint16_t)0x4000)            /*!< Bit 4 */\r
+\r
+#define  USB_COUNT6_RX_BLSIZE                ((uint16_t)0x8000)            /*!< BLock SIZE */\r
+\r
+/*****************  Bit definition for USB_COUNT7_RX register  ****************/\r
+#define  USB_COUNT7_RX_COUNT7_RX             ((uint16_t)0x03FF)            /*!< Reception Byte Count */\r
+\r
+#define  USB_COUNT7_RX_NUM_BLOCK             ((uint16_t)0x7C00)            /*!< NUM_BLOCK[4:0] bits (Number of blocks) */\r
+#define  USB_COUNT7_RX_NUM_BLOCK_0           ((uint16_t)0x0400)            /*!< Bit 0 */\r
+#define  USB_COUNT7_RX_NUM_BLOCK_1           ((uint16_t)0x0800)            /*!< Bit 1 */\r
+#define  USB_COUNT7_RX_NUM_BLOCK_2           ((uint16_t)0x1000)            /*!< Bit 2 */\r
+#define  USB_COUNT7_RX_NUM_BLOCK_3           ((uint16_t)0x2000)            /*!< Bit 3 */\r
+#define  USB_COUNT7_RX_NUM_BLOCK_4           ((uint16_t)0x4000)            /*!< Bit 4 */\r
+\r
+#define  USB_COUNT7_RX_BLSIZE                ((uint16_t)0x8000)            /*!< BLock SIZE */\r
+\r
+/*----------------------------------------------------------------------------*/\r
+\r
+/****************  Bit definition for USB_COUNT0_RX_0 register  ***************/\r
+#define  USB_COUNT0_RX_0_COUNT0_RX_0         ((uint32_t)0x000003FF)        /*!< Reception Byte Count (low) */\r
+\r
+#define  USB_COUNT0_RX_0_NUM_BLOCK_0         ((uint32_t)0x00007C00)        /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */\r
+#define  USB_COUNT0_RX_0_NUM_BLOCK_0_0       ((uint32_t)0x00000400)        /*!< Bit 0 */\r
+#define  USB_COUNT0_RX_0_NUM_BLOCK_0_1       ((uint32_t)0x00000800)        /*!< Bit 1 */\r
+#define  USB_COUNT0_RX_0_NUM_BLOCK_0_2       ((uint32_t)0x00001000)        /*!< Bit 2 */\r
+#define  USB_COUNT0_RX_0_NUM_BLOCK_0_3       ((uint32_t)0x00002000)        /*!< Bit 3 */\r
+#define  USB_COUNT0_RX_0_NUM_BLOCK_0_4       ((uint32_t)0x00004000)        /*!< Bit 4 */\r
+\r
+#define  USB_COUNT0_RX_0_BLSIZE_0            ((uint32_t)0x00008000)        /*!< BLock SIZE (low) */\r
+\r
+/****************  Bit definition for USB_COUNT0_RX_1 register  ***************/\r
+#define  USB_COUNT0_RX_1_COUNT0_RX_1         ((uint32_t)0x03FF0000)        /*!< Reception Byte Count (high) */\r
+\r
+#define  USB_COUNT0_RX_1_NUM_BLOCK_1         ((uint32_t)0x7C000000)        /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */\r
+#define  USB_COUNT0_RX_1_NUM_BLOCK_1_0       ((uint32_t)0x04000000)        /*!< Bit 1 */\r
+#define  USB_COUNT0_RX_1_NUM_BLOCK_1_1       ((uint32_t)0x08000000)        /*!< Bit 1 */\r
+#define  USB_COUNT0_RX_1_NUM_BLOCK_1_2       ((uint32_t)0x10000000)        /*!< Bit 2 */\r
+#define  USB_COUNT0_RX_1_NUM_BLOCK_1_3       ((uint32_t)0x20000000)        /*!< Bit 3 */\r
+#define  USB_COUNT0_RX_1_NUM_BLOCK_1_4       ((uint32_t)0x40000000)        /*!< Bit 4 */\r
+\r
+#define  USB_COUNT0_RX_1_BLSIZE_1            ((uint32_t)0x80000000)        /*!< BLock SIZE (high) */\r
+\r
+/****************  Bit definition for USB_COUNT1_RX_0 register  ***************/\r
+#define  USB_COUNT1_RX_0_COUNT1_RX_0         ((uint32_t)0x000003FF)        /*!< Reception Byte Count (low) */\r
+\r
+#define  USB_COUNT1_RX_0_NUM_BLOCK_0         ((uint32_t)0x00007C00)        /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */\r
+#define  USB_COUNT1_RX_0_NUM_BLOCK_0_0       ((uint32_t)0x00000400)        /*!< Bit 0 */\r
+#define  USB_COUNT1_RX_0_NUM_BLOCK_0_1       ((uint32_t)0x00000800)        /*!< Bit 1 */\r
+#define  USB_COUNT1_RX_0_NUM_BLOCK_0_2       ((uint32_t)0x00001000)        /*!< Bit 2 */\r
+#define  USB_COUNT1_RX_0_NUM_BLOCK_0_3       ((uint32_t)0x00002000)        /*!< Bit 3 */\r
+#define  USB_COUNT1_RX_0_NUM_BLOCK_0_4       ((uint32_t)0x00004000)        /*!< Bit 4 */\r
+\r
+#define  USB_COUNT1_RX_0_BLSIZE_0            ((uint32_t)0x00008000)        /*!< BLock SIZE (low) */\r
+\r
+/****************  Bit definition for USB_COUNT1_RX_1 register  ***************/\r
+#define  USB_COUNT1_RX_1_COUNT1_RX_1         ((uint32_t)0x03FF0000)        /*!< Reception Byte Count (high) */\r
+\r
+#define  USB_COUNT1_RX_1_NUM_BLOCK_1         ((uint32_t)0x7C000000)        /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */\r
+#define  USB_COUNT1_RX_1_NUM_BLOCK_1_0       ((uint32_t)0x04000000)        /*!< Bit 0 */\r
+#define  USB_COUNT1_RX_1_NUM_BLOCK_1_1       ((uint32_t)0x08000000)        /*!< Bit 1 */\r
+#define  USB_COUNT1_RX_1_NUM_BLOCK_1_2       ((uint32_t)0x10000000)        /*!< Bit 2 */\r
+#define  USB_COUNT1_RX_1_NUM_BLOCK_1_3       ((uint32_t)0x20000000)        /*!< Bit 3 */\r
+#define  USB_COUNT1_RX_1_NUM_BLOCK_1_4       ((uint32_t)0x40000000)        /*!< Bit 4 */\r
+\r
+#define  USB_COUNT1_RX_1_BLSIZE_1            ((uint32_t)0x80000000)        /*!< BLock SIZE (high) */\r
+\r
+/****************  Bit definition for USB_COUNT2_RX_0 register  ***************/\r
+#define  USB_COUNT2_RX_0_COUNT2_RX_0         ((uint32_t)0x000003FF)        /*!< Reception Byte Count (low) */\r
+\r
+#define  USB_COUNT2_RX_0_NUM_BLOCK_0         ((uint32_t)0x00007C00)        /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */\r
+#define  USB_COUNT2_RX_0_NUM_BLOCK_0_0       ((uint32_t)0x00000400)        /*!< Bit 0 */\r
+#define  USB_COUNT2_RX_0_NUM_BLOCK_0_1       ((uint32_t)0x00000800)        /*!< Bit 1 */\r
+#define  USB_COUNT2_RX_0_NUM_BLOCK_0_2       ((uint32_t)0x00001000)        /*!< Bit 2 */\r
+#define  USB_COUNT2_RX_0_NUM_BLOCK_0_3       ((uint32_t)0x00002000)        /*!< Bit 3 */\r
+#define  USB_COUNT2_RX_0_NUM_BLOCK_0_4       ((uint32_t)0x00004000)        /*!< Bit 4 */\r
+\r
+#define  USB_COUNT2_RX_0_BLSIZE_0            ((uint32_t)0x00008000)        /*!< BLock SIZE (low) */\r
+\r
+/****************  Bit definition for USB_COUNT2_RX_1 register  ***************/\r
+#define  USB_COUNT2_RX_1_COUNT2_RX_1         ((uint32_t)0x03FF0000)        /*!< Reception Byte Count (high) */\r
+\r
+#define  USB_COUNT2_RX_1_NUM_BLOCK_1         ((uint32_t)0x7C000000)        /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */\r
+#define  USB_COUNT2_RX_1_NUM_BLOCK_1_0       ((uint32_t)0x04000000)        /*!< Bit 0 */\r
+#define  USB_COUNT2_RX_1_NUM_BLOCK_1_1       ((uint32_t)0x08000000)        /*!< Bit 1 */\r
+#define  USB_COUNT2_RX_1_NUM_BLOCK_1_2       ((uint32_t)0x10000000)        /*!< Bit 2 */\r
+#define  USB_COUNT2_RX_1_NUM_BLOCK_1_3       ((uint32_t)0x20000000)        /*!< Bit 3 */\r
+#define  USB_COUNT2_RX_1_NUM_BLOCK_1_4       ((uint32_t)0x40000000)        /*!< Bit 4 */\r
+\r
+#define  USB_COUNT2_RX_1_BLSIZE_1            ((uint32_t)0x80000000)        /*!< BLock SIZE (high) */\r
+\r
+/****************  Bit definition for USB_COUNT3_RX_0 register  ***************/\r
+#define  USB_COUNT3_RX_0_COUNT3_RX_0         ((uint32_t)0x000003FF)        /*!< Reception Byte Count (low) */\r
+\r
+#define  USB_COUNT3_RX_0_NUM_BLOCK_0         ((uint32_t)0x00007C00)        /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */\r
+#define  USB_COUNT3_RX_0_NUM_BLOCK_0_0       ((uint32_t)0x00000400)        /*!< Bit 0 */\r
+#define  USB_COUNT3_RX_0_NUM_BLOCK_0_1       ((uint32_t)0x00000800)        /*!< Bit 1 */\r
+#define  USB_COUNT3_RX_0_NUM_BLOCK_0_2       ((uint32_t)0x00001000)        /*!< Bit 2 */\r
+#define  USB_COUNT3_RX_0_NUM_BLOCK_0_3       ((uint32_t)0x00002000)        /*!< Bit 3 */\r
+#define  USB_COUNT3_RX_0_NUM_BLOCK_0_4       ((uint32_t)0x00004000)        /*!< Bit 4 */\r
+\r
+#define  USB_COUNT3_RX_0_BLSIZE_0            ((uint32_t)0x00008000)        /*!< BLock SIZE (low) */\r
+\r
+/****************  Bit definition for USB_COUNT3_RX_1 register  ***************/\r
+#define  USB_COUNT3_RX_1_COUNT3_RX_1         ((uint32_t)0x03FF0000)        /*!< Reception Byte Count (high) */\r
+\r
+#define  USB_COUNT3_RX_1_NUM_BLOCK_1         ((uint32_t)0x7C000000)        /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */\r
+#define  USB_COUNT3_RX_1_NUM_BLOCK_1_0       ((uint32_t)0x04000000)        /*!< Bit 0 */\r
+#define  USB_COUNT3_RX_1_NUM_BLOCK_1_1       ((uint32_t)0x08000000)        /*!< Bit 1 */\r
+#define  USB_COUNT3_RX_1_NUM_BLOCK_1_2       ((uint32_t)0x10000000)        /*!< Bit 2 */\r
+#define  USB_COUNT3_RX_1_NUM_BLOCK_1_3       ((uint32_t)0x20000000)        /*!< Bit 3 */\r
+#define  USB_COUNT3_RX_1_NUM_BLOCK_1_4       ((uint32_t)0x40000000)        /*!< Bit 4 */\r
+\r
+#define  USB_COUNT3_RX_1_BLSIZE_1            ((uint32_t)0x80000000)        /*!< BLock SIZE (high) */\r
+\r
+/****************  Bit definition for USB_COUNT4_RX_0 register  ***************/\r
+#define  USB_COUNT4_RX_0_COUNT4_RX_0         ((uint32_t)0x000003FF)        /*!< Reception Byte Count (low) */\r
+\r
+#define  USB_COUNT4_RX_0_NUM_BLOCK_0         ((uint32_t)0x00007C00)        /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */\r
+#define  USB_COUNT4_RX_0_NUM_BLOCK_0_0      ((uint32_t)0x00000400)        /*!< Bit 0 */\r
+#define  USB_COUNT4_RX_0_NUM_BLOCK_0_1      ((uint32_t)0x00000800)        /*!< Bit 1 */\r
+#define  USB_COUNT4_RX_0_NUM_BLOCK_0_2      ((uint32_t)0x00001000)        /*!< Bit 2 */\r
+#define  USB_COUNT4_RX_0_NUM_BLOCK_0_3      ((uint32_t)0x00002000)        /*!< Bit 3 */\r
+#define  USB_COUNT4_RX_0_NUM_BLOCK_0_4      ((uint32_t)0x00004000)        /*!< Bit 4 */\r
+\r
+#define  USB_COUNT4_RX_0_BLSIZE_0            ((uint32_t)0x00008000)        /*!< BLock SIZE (low) */\r
+\r
+/****************  Bit definition for USB_COUNT4_RX_1 register  ***************/\r
+#define  USB_COUNT4_RX_1_COUNT4_RX_1         ((uint32_t)0x03FF0000)        /*!< Reception Byte Count (high) */\r
+\r
+#define  USB_COUNT4_RX_1_NUM_BLOCK_1         ((uint32_t)0x7C000000)        /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */\r
+#define  USB_COUNT4_RX_1_NUM_BLOCK_1_0       ((uint32_t)0x04000000)        /*!< Bit 0 */\r
+#define  USB_COUNT4_RX_1_NUM_BLOCK_1_1       ((uint32_t)0x08000000)        /*!< Bit 1 */\r
+#define  USB_COUNT4_RX_1_NUM_BLOCK_1_2       ((uint32_t)0x10000000)        /*!< Bit 2 */\r
+#define  USB_COUNT4_RX_1_NUM_BLOCK_1_3       ((uint32_t)0x20000000)        /*!< Bit 3 */\r
+#define  USB_COUNT4_RX_1_NUM_BLOCK_1_4       ((uint32_t)0x40000000)        /*!< Bit 4 */\r
+\r
+#define  USB_COUNT4_RX_1_BLSIZE_1            ((uint32_t)0x80000000)        /*!< BLock SIZE (high) */\r
+\r
+/****************  Bit definition for USB_COUNT5_RX_0 register  ***************/\r
+#define  USB_COUNT5_RX_0_COUNT5_RX_0         ((uint32_t)0x000003FF)        /*!< Reception Byte Count (low) */\r
+\r
+#define  USB_COUNT5_RX_0_NUM_BLOCK_0         ((uint32_t)0x00007C00)        /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */\r
+#define  USB_COUNT5_RX_0_NUM_BLOCK_0_0       ((uint32_t)0x00000400)        /*!< Bit 0 */\r
+#define  USB_COUNT5_RX_0_NUM_BLOCK_0_1       ((uint32_t)0x00000800)        /*!< Bit 1 */\r
+#define  USB_COUNT5_RX_0_NUM_BLOCK_0_2       ((uint32_t)0x00001000)        /*!< Bit 2 */\r
+#define  USB_COUNT5_RX_0_NUM_BLOCK_0_3       ((uint32_t)0x00002000)        /*!< Bit 3 */\r
+#define  USB_COUNT5_RX_0_NUM_BLOCK_0_4       ((uint32_t)0x00004000)        /*!< Bit 4 */\r
+\r
+#define  USB_COUNT5_RX_0_BLSIZE_0            ((uint32_t)0x00008000)        /*!< BLock SIZE (low) */\r
+\r
+/****************  Bit definition for USB_COUNT5_RX_1 register  ***************/\r
+#define  USB_COUNT5_RX_1_COUNT5_RX_1         ((uint32_t)0x03FF0000)        /*!< Reception Byte Count (high) */\r
+\r
+#define  USB_COUNT5_RX_1_NUM_BLOCK_1         ((uint32_t)0x7C000000)        /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */\r
+#define  USB_COUNT5_RX_1_NUM_BLOCK_1_0       ((uint32_t)0x04000000)        /*!< Bit 0 */\r
+#define  USB_COUNT5_RX_1_NUM_BLOCK_1_1       ((uint32_t)0x08000000)        /*!< Bit 1 */\r
+#define  USB_COUNT5_RX_1_NUM_BLOCK_1_2       ((uint32_t)0x10000000)        /*!< Bit 2 */\r
+#define  USB_COUNT5_RX_1_NUM_BLOCK_1_3       ((uint32_t)0x20000000)        /*!< Bit 3 */\r
+#define  USB_COUNT5_RX_1_NUM_BLOCK_1_4       ((uint32_t)0x40000000)        /*!< Bit 4 */\r
+\r
+#define  USB_COUNT5_RX_1_BLSIZE_1            ((uint32_t)0x80000000)        /*!< BLock SIZE (high) */\r
+\r
+/***************  Bit definition for USB_COUNT6_RX_0  register  ***************/\r
+#define  USB_COUNT6_RX_0_COUNT6_RX_0         ((uint32_t)0x000003FF)        /*!< Reception Byte Count (low) */\r
+\r
+#define  USB_COUNT6_RX_0_NUM_BLOCK_0         ((uint32_t)0x00007C00)        /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */\r
+#define  USB_COUNT6_RX_0_NUM_BLOCK_0_0       ((uint32_t)0x00000400)        /*!< Bit 0 */\r
+#define  USB_COUNT6_RX_0_NUM_BLOCK_0_1       ((uint32_t)0x00000800)        /*!< Bit 1 */\r
+#define  USB_COUNT6_RX_0_NUM_BLOCK_0_2       ((uint32_t)0x00001000)        /*!< Bit 2 */\r
+#define  USB_COUNT6_RX_0_NUM_BLOCK_0_3       ((uint32_t)0x00002000)        /*!< Bit 3 */\r
+#define  USB_COUNT6_RX_0_NUM_BLOCK_0_4       ((uint32_t)0x00004000)        /*!< Bit 4 */\r
+\r
+#define  USB_COUNT6_RX_0_BLSIZE_0            ((uint32_t)0x00008000)        /*!< BLock SIZE (low) */\r
+\r
+/****************  Bit definition for USB_COUNT6_RX_1 register  ***************/\r
+#define  USB_COUNT6_RX_1_COUNT6_RX_1         ((uint32_t)0x03FF0000)        /*!< Reception Byte Count (high) */\r
+\r
+#define  USB_COUNT6_RX_1_NUM_BLOCK_1         ((uint32_t)0x7C000000)        /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */\r
+#define  USB_COUNT6_RX_1_NUM_BLOCK_1_0       ((uint32_t)0x04000000)        /*!< Bit 0 */\r
+#define  USB_COUNT6_RX_1_NUM_BLOCK_1_1       ((uint32_t)0x08000000)        /*!< Bit 1 */\r
+#define  USB_COUNT6_RX_1_NUM_BLOCK_1_2       ((uint32_t)0x10000000)        /*!< Bit 2 */\r
+#define  USB_COUNT6_RX_1_NUM_BLOCK_1_3       ((uint32_t)0x20000000)        /*!< Bit 3 */\r
+#define  USB_COUNT6_RX_1_NUM_BLOCK_1_4       ((uint32_t)0x40000000)        /*!< Bit 4 */\r
+\r
+#define  USB_COUNT6_RX_1_BLSIZE_1            ((uint32_t)0x80000000)        /*!< BLock SIZE (high) */\r
+\r
+/***************  Bit definition for USB_COUNT7_RX_0 register  ****************/\r
+#define  USB_COUNT7_RX_0_COUNT7_RX_0         ((uint32_t)0x000003FF)        /*!< Reception Byte Count (low) */\r
+\r
+#define  USB_COUNT7_RX_0_NUM_BLOCK_0         ((uint32_t)0x00007C00)        /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */\r
+#define  USB_COUNT7_RX_0_NUM_BLOCK_0_0       ((uint32_t)0x00000400)        /*!< Bit 0 */\r
+#define  USB_COUNT7_RX_0_NUM_BLOCK_0_1       ((uint32_t)0x00000800)        /*!< Bit 1 */\r
+#define  USB_COUNT7_RX_0_NUM_BLOCK_0_2       ((uint32_t)0x00001000)        /*!< Bit 2 */\r
+#define  USB_COUNT7_RX_0_NUM_BLOCK_0_3       ((uint32_t)0x00002000)        /*!< Bit 3 */\r
+#define  USB_COUNT7_RX_0_NUM_BLOCK_0_4       ((uint32_t)0x00004000)        /*!< Bit 4 */\r
+\r
+#define  USB_COUNT7_RX_0_BLSIZE_0            ((uint32_t)0x00008000)        /*!< BLock SIZE (low) */\r
+\r
+/***************  Bit definition for USB_COUNT7_RX_1 register  ****************/\r
+#define  USB_COUNT7_RX_1_COUNT7_RX_1         ((uint32_t)0x03FF0000)        /*!< Reception Byte Count (high) */\r
+\r
+#define  USB_COUNT7_RX_1_NUM_BLOCK_1         ((uint32_t)0x7C000000)        /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */\r
+#define  USB_COUNT7_RX_1_NUM_BLOCK_1_0       ((uint32_t)0x04000000)        /*!< Bit 0 */\r
+#define  USB_COUNT7_RX_1_NUM_BLOCK_1_1       ((uint32_t)0x08000000)        /*!< Bit 1 */\r
+#define  USB_COUNT7_RX_1_NUM_BLOCK_1_2       ((uint32_t)0x10000000)        /*!< Bit 2 */\r
+#define  USB_COUNT7_RX_1_NUM_BLOCK_1_3       ((uint32_t)0x20000000)        /*!< Bit 3 */\r
+#define  USB_COUNT7_RX_1_NUM_BLOCK_1_4       ((uint32_t)0x40000000)        /*!< Bit 4 */\r
+\r
+#define  USB_COUNT7_RX_1_BLSIZE_1            ((uint32_t)0x80000000)        /*!< BLock SIZE (high) */\r
+\r
+/******************************************************************************/\r
+/*                                                                            */\r
+/*                            Window WATCHDOG                                 */\r
+/*                                                                            */\r
+/******************************************************************************/\r
+\r
+/*******************  Bit definition for WWDG_CR register  ********************/\r
+#define  WWDG_CR_T                           ((uint8_t)0x7F)               /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */\r
+#define  WWDG_CR_T0                          ((uint8_t)0x01)               /*!< Bit 0 */\r
+#define  WWDG_CR_T1                          ((uint8_t)0x02)               /*!< Bit 1 */\r
+#define  WWDG_CR_T2                          ((uint8_t)0x04)               /*!< Bit 2 */\r
+#define  WWDG_CR_T3                          ((uint8_t)0x08)               /*!< Bit 3 */\r
+#define  WWDG_CR_T4                          ((uint8_t)0x10)               /*!< Bit 4 */\r
+#define  WWDG_CR_T5                          ((uint8_t)0x20)               /*!< Bit 5 */\r
+#define  WWDG_CR_T6                          ((uint8_t)0x40)               /*!< Bit 6 */\r
+\r
+#define  WWDG_CR_WDGA                        ((uint8_t)0x80)               /*!< Activation bit */\r
+\r
+/*******************  Bit definition for WWDG_CFR register  *******************/\r
+#define  WWDG_CFR_W                          ((uint16_t)0x007F)            /*!< W[6:0] bits (7-bit window value) */\r
+#define  WWDG_CFR_W0                         ((uint16_t)0x0001)            /*!< Bit 0 */\r
+#define  WWDG_CFR_W1                         ((uint16_t)0x0002)            /*!< Bit 1 */\r
+#define  WWDG_CFR_W2                         ((uint16_t)0x0004)            /*!< Bit 2 */\r
+#define  WWDG_CFR_W3                         ((uint16_t)0x0008)            /*!< Bit 3 */\r
+#define  WWDG_CFR_W4                         ((uint16_t)0x0010)            /*!< Bit 4 */\r
+#define  WWDG_CFR_W5                         ((uint16_t)0x0020)            /*!< Bit 5 */\r
+#define  WWDG_CFR_W6                         ((uint16_t)0x0040)            /*!< Bit 6 */\r
+\r
+#define  WWDG_CFR_WDGTB                      ((uint16_t)0x0180)            /*!< WDGTB[1:0] bits (Timer Base) */\r
+#define  WWDG_CFR_WDGTB0                     ((uint16_t)0x0080)            /*!< Bit 0 */\r
+#define  WWDG_CFR_WDGTB1                     ((uint16_t)0x0100)            /*!< Bit 1 */\r
+\r
+#define  WWDG_CFR_EWI                        ((uint16_t)0x0200)            /*!< Early Wakeup Interrupt */\r
+\r
+/*******************  Bit definition for WWDG_SR register  ********************/\r
+#define  WWDG_SR_EWIF                        ((uint8_t)0x01)               /*!< Early Wakeup Interrupt Flag */\r
+\r
+/******************************************************************************/\r
+/*                                                                            */\r
+/*                               SystemTick                                   */\r
+/*                                                                            */\r
+/******************************************************************************/\r
+\r
+/*****************  Bit definition for SysTick_CTRL register  *****************/\r
+#define  SysTick_CTRL_ENABLE                 ((uint32_t)0x00000001)        /*!< Counter enable */\r
+#define  SysTick_CTRL_TICKINT                ((uint32_t)0x00000002)        /*!< Counting down to 0 pends the SysTick handler */\r
+#define  SysTick_CTRL_CLKSOURCE              ((uint32_t)0x00000004)        /*!< Clock source */\r
+#define  SysTick_CTRL_COUNTFLAG              ((uint32_t)0x00010000)        /*!< Count Flag */\r
+\r
+/*****************  Bit definition for SysTick_LOAD register  *****************/\r
+#define  SysTick_LOAD_RELOAD                 ((uint32_t)0x00FFFFFF)        /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */\r
+\r
+/*****************  Bit definition for SysTick_VAL register  ******************/\r
+#define  SysTick_VAL_CURRENT                 ((uint32_t)0x00FFFFFF)        /*!< Current value at the time the register is accessed */\r
+\r
+/*****************  Bit definition for SysTick_CALIB register  ****************/\r
+#define  SysTick_CALIB_TENMS                 ((uint32_t)0x00FFFFFF)        /*!< Reload value to use for 10ms timing */\r
+#define  SysTick_CALIB_SKEW                  ((uint32_t)0x40000000)        /*!< Calibration value is not exactly 10 ms */\r
+#define  SysTick_CALIB_NOREF                 ((uint32_t)0x80000000)        /*!< The reference clock is not provided */\r
+\r
+/******************************************************************************/\r
+/*                                                                            */\r
+/*                  Nested Vectored Interrupt Controller                      */\r
+/*                                                                            */\r
+/******************************************************************************/\r
+\r
+/******************  Bit definition for NVIC_ISER register  *******************/\r
+#define  NVIC_ISER_SETENA                    ((uint32_t)0xFFFFFFFF)        /*!< Interrupt set enable bits */\r
+#define  NVIC_ISER_SETENA_0                  ((uint32_t)0x00000001)        /*!< bit 0 */\r
+#define  NVIC_ISER_SETENA_1                  ((uint32_t)0x00000002)        /*!< bit 1 */\r
+#define  NVIC_ISER_SETENA_2                  ((uint32_t)0x00000004)        /*!< bit 2 */\r
+#define  NVIC_ISER_SETENA_3                  ((uint32_t)0x00000008)        /*!< bit 3 */\r
+#define  NVIC_ISER_SETENA_4                  ((uint32_t)0x00000010)        /*!< bit 4 */\r
+#define  NVIC_ISER_SETENA_5                  ((uint32_t)0x00000020)        /*!< bit 5 */\r
+#define  NVIC_ISER_SETENA_6                  ((uint32_t)0x00000040)        /*!< bit 6 */\r
+#define  NVIC_ISER_SETENA_7                  ((uint32_t)0x00000080)        /*!< bit 7 */\r
+#define  NVIC_ISER_SETENA_8                  ((uint32_t)0x00000100)        /*!< bit 8 */\r
+#define  NVIC_ISER_SETENA_9                  ((uint32_t)0x00000200)        /*!< bit 9 */\r
+#define  NVIC_ISER_SETENA_10                 ((uint32_t)0x00000400)        /*!< bit 10 */\r
+#define  NVIC_ISER_SETENA_11                 ((uint32_t)0x00000800)        /*!< bit 11 */\r
+#define  NVIC_ISER_SETENA_12                 ((uint32_t)0x00001000)        /*!< bit 12 */\r
+#define  NVIC_ISER_SETENA_13                 ((uint32_t)0x00002000)        /*!< bit 13 */\r
+#define  NVIC_ISER_SETENA_14                 ((uint32_t)0x00004000)        /*!< bit 14 */\r
+#define  NVIC_ISER_SETENA_15                 ((uint32_t)0x00008000)        /*!< bit 15 */\r
+#define  NVIC_ISER_SETENA_16                 ((uint32_t)0x00010000)        /*!< bit 16 */\r
+#define  NVIC_ISER_SETENA_17                 ((uint32_t)0x00020000)        /*!< bit 17 */\r
+#define  NVIC_ISER_SETENA_18                 ((uint32_t)0x00040000)        /*!< bit 18 */\r
+#define  NVIC_ISER_SETENA_19                 ((uint32_t)0x00080000)        /*!< bit 19 */\r
+#define  NVIC_ISER_SETENA_20                 ((uint32_t)0x00100000)        /*!< bit 20 */\r
+#define  NVIC_ISER_SETENA_21                 ((uint32_t)0x00200000)        /*!< bit 21 */\r
+#define  NVIC_ISER_SETENA_22                 ((uint32_t)0x00400000)        /*!< bit 22 */\r
+#define  NVIC_ISER_SETENA_23                 ((uint32_t)0x00800000)        /*!< bit 23 */\r
+#define  NVIC_ISER_SETENA_24                 ((uint32_t)0x01000000)        /*!< bit 24 */\r
+#define  NVIC_ISER_SETENA_25                 ((uint32_t)0x02000000)        /*!< bit 25 */\r
+#define  NVIC_ISER_SETENA_26                 ((uint32_t)0x04000000)        /*!< bit 26 */\r
+#define  NVIC_ISER_SETENA_27                 ((uint32_t)0x08000000)        /*!< bit 27 */\r
+#define  NVIC_ISER_SETENA_28                 ((uint32_t)0x10000000)        /*!< bit 28 */\r
+#define  NVIC_ISER_SETENA_29                 ((uint32_t)0x20000000)        /*!< bit 29 */\r
+#define  NVIC_ISER_SETENA_30                 ((uint32_t)0x40000000)        /*!< bit 30 */\r
+#define  NVIC_ISER_SETENA_31                 ((uint32_t)0x80000000)        /*!< bit 31 */\r
+\r
+/******************  Bit definition for NVIC_ICER register  *******************/\r
+#define  NVIC_ICER_CLRENA                   ((uint32_t)0xFFFFFFFF)        /*!< Interrupt clear-enable bits */\r
+#define  NVIC_ICER_CLRENA_0                  ((uint32_t)0x00000001)        /*!< bit 0 */\r
+#define  NVIC_ICER_CLRENA_1                  ((uint32_t)0x00000002)        /*!< bit 1 */\r
+#define  NVIC_ICER_CLRENA_2                  ((uint32_t)0x00000004)        /*!< bit 2 */\r
+#define  NVIC_ICER_CLRENA_3                  ((uint32_t)0x00000008)        /*!< bit 3 */\r
+#define  NVIC_ICER_CLRENA_4                  ((uint32_t)0x00000010)        /*!< bit 4 */\r
+#define  NVIC_ICER_CLRENA_5                  ((uint32_t)0x00000020)        /*!< bit 5 */\r
+#define  NVIC_ICER_CLRENA_6                  ((uint32_t)0x00000040)        /*!< bit 6 */\r
+#define  NVIC_ICER_CLRENA_7                  ((uint32_t)0x00000080)        /*!< bit 7 */\r
+#define  NVIC_ICER_CLRENA_8                  ((uint32_t)0x00000100)        /*!< bit 8 */\r
+#define  NVIC_ICER_CLRENA_9                  ((uint32_t)0x00000200)        /*!< bit 9 */\r
+#define  NVIC_ICER_CLRENA_10                 ((uint32_t)0x00000400)        /*!< bit 10 */\r
+#define  NVIC_ICER_CLRENA_11                 ((uint32_t)0x00000800)        /*!< bit 11 */\r
+#define  NVIC_ICER_CLRENA_12                 ((uint32_t)0x00001000)        /*!< bit 12 */\r
+#define  NVIC_ICER_CLRENA_13                 ((uint32_t)0x00002000)        /*!< bit 13 */\r
+#define  NVIC_ICER_CLRENA_14                 ((uint32_t)0x00004000)        /*!< bit 14 */\r
+#define  NVIC_ICER_CLRENA_15                 ((uint32_t)0x00008000)        /*!< bit 15 */\r
+#define  NVIC_ICER_CLRENA_16                 ((uint32_t)0x00010000)        /*!< bit 16 */\r
+#define  NVIC_ICER_CLRENA_17                 ((uint32_t)0x00020000)        /*!< bit 17 */\r
+#define  NVIC_ICER_CLRENA_18                 ((uint32_t)0x00040000)        /*!< bit 18 */\r
+#define  NVIC_ICER_CLRENA_19                 ((uint32_t)0x00080000)        /*!< bit 19 */\r
+#define  NVIC_ICER_CLRENA_20                 ((uint32_t)0x00100000)        /*!< bit 20 */\r
+#define  NVIC_ICER_CLRENA_21                 ((uint32_t)0x00200000)        /*!< bit 21 */\r
+#define  NVIC_ICER_CLRENA_22                 ((uint32_t)0x00400000)        /*!< bit 22 */\r
+#define  NVIC_ICER_CLRENA_23                 ((uint32_t)0x00800000)        /*!< bit 23 */\r
+#define  NVIC_ICER_CLRENA_24                 ((uint32_t)0x01000000)        /*!< bit 24 */\r
+#define  NVIC_ICER_CLRENA_25                 ((uint32_t)0x02000000)        /*!< bit 25 */\r
+#define  NVIC_ICER_CLRENA_26                 ((uint32_t)0x04000000)        /*!< bit 26 */\r
+#define  NVIC_ICER_CLRENA_27                 ((uint32_t)0x08000000)        /*!< bit 27 */\r
+#define  NVIC_ICER_CLRENA_28                 ((uint32_t)0x10000000)        /*!< bit 28 */\r
+#define  NVIC_ICER_CLRENA_29                 ((uint32_t)0x20000000)        /*!< bit 29 */\r
+#define  NVIC_ICER_CLRENA_30                 ((uint32_t)0x40000000)        /*!< bit 30 */\r
+#define  NVIC_ICER_CLRENA_31                 ((uint32_t)0x80000000)        /*!< bit 31 */\r
+\r
+/******************  Bit definition for NVIC_ISPR register  *******************/\r
+#define  NVIC_ISPR_SETPEND                   ((uint32_t)0xFFFFFFFF)        /*!< Interrupt set-pending bits */\r
+#define  NVIC_ISPR_SETPEND_0                 ((uint32_t)0x00000001)        /*!< bit 0 */\r
+#define  NVIC_ISPR_SETPEND_1                 ((uint32_t)0x00000002)        /*!< bit 1 */\r
+#define  NVIC_ISPR_SETPEND_2                 ((uint32_t)0x00000004)        /*!< bit 2 */\r
+#define  NVIC_ISPR_SETPEND_3                 ((uint32_t)0x00000008)        /*!< bit 3 */\r
+#define  NVIC_ISPR_SETPEND_4                 ((uint32_t)0x00000010)        /*!< bit 4 */\r
+#define  NVIC_ISPR_SETPEND_5                 ((uint32_t)0x00000020)        /*!< bit 5 */\r
+#define  NVIC_ISPR_SETPEND_6                 ((uint32_t)0x00000040)        /*!< bit 6 */\r
+#define  NVIC_ISPR_SETPEND_7                 ((uint32_t)0x00000080)        /*!< bit 7 */\r
+#define  NVIC_ISPR_SETPEND_8                 ((uint32_t)0x00000100)        /*!< bit 8 */\r
+#define  NVIC_ISPR_SETPEND_9                 ((uint32_t)0x00000200)        /*!< bit 9 */\r
+#define  NVIC_ISPR_SETPEND_10                ((uint32_t)0x00000400)        /*!< bit 10 */\r
+#define  NVIC_ISPR_SETPEND_11                ((uint32_t)0x00000800)        /*!< bit 11 */\r
+#define  NVIC_ISPR_SETPEND_12                ((uint32_t)0x00001000)        /*!< bit 12 */\r
+#define  NVIC_ISPR_SETPEND_13                ((uint32_t)0x00002000)        /*!< bit 13 */\r
+#define  NVIC_ISPR_SETPEND_14                ((uint32_t)0x00004000)        /*!< bit 14 */\r
+#define  NVIC_ISPR_SETPEND_15                ((uint32_t)0x00008000)        /*!< bit 15 */\r
+#define  NVIC_ISPR_SETPEND_16                ((uint32_t)0x00010000)        /*!< bit 16 */\r
+#define  NVIC_ISPR_SETPEND_17                ((uint32_t)0x00020000)        /*!< bit 17 */\r
+#define  NVIC_ISPR_SETPEND_18                ((uint32_t)0x00040000)        /*!< bit 18 */\r
+#define  NVIC_ISPR_SETPEND_19                ((uint32_t)0x00080000)        /*!< bit 19 */\r
+#define  NVIC_ISPR_SETPEND_20                ((uint32_t)0x00100000)        /*!< bit 20 */\r
+#define  NVIC_ISPR_SETPEND_21                ((uint32_t)0x00200000)        /*!< bit 21 */\r
+#define  NVIC_ISPR_SETPEND_22                ((uint32_t)0x00400000)        /*!< bit 22 */\r
+#define  NVIC_ISPR_SETPEND_23                ((uint32_t)0x00800000)        /*!< bit 23 */\r
+#define  NVIC_ISPR_SETPEND_24                ((uint32_t)0x01000000)        /*!< bit 24 */\r
+#define  NVIC_ISPR_SETPEND_25                ((uint32_t)0x02000000)        /*!< bit 25 */\r
+#define  NVIC_ISPR_SETPEND_26                ((uint32_t)0x04000000)        /*!< bit 26 */\r
+#define  NVIC_ISPR_SETPEND_27                ((uint32_t)0x08000000)        /*!< bit 27 */\r
+#define  NVIC_ISPR_SETPEND_28                ((uint32_t)0x10000000)        /*!< bit 28 */\r
+#define  NVIC_ISPR_SETPEND_29                ((uint32_t)0x20000000)        /*!< bit 29 */\r
+#define  NVIC_ISPR_SETPEND_30                ((uint32_t)0x40000000)        /*!< bit 30 */\r
+#define  NVIC_ISPR_SETPEND_31                ((uint32_t)0x80000000)        /*!< bit 31 */\r
+\r
+/******************  Bit definition for NVIC_ICPR register  *******************/\r
+#define  NVIC_ICPR_CLRPEND                   ((uint32_t)0xFFFFFFFF)        /*!< Interrupt clear-pending bits */\r
+#define  NVIC_ICPR_CLRPEND_0                 ((uint32_t)0x00000001)        /*!< bit 0 */\r
+#define  NVIC_ICPR_CLRPEND_1                 ((uint32_t)0x00000002)        /*!< bit 1 */\r
+#define  NVIC_ICPR_CLRPEND_2                 ((uint32_t)0x00000004)        /*!< bit 2 */\r
+#define  NVIC_ICPR_CLRPEND_3                 ((uint32_t)0x00000008)        /*!< bit 3 */\r
+#define  NVIC_ICPR_CLRPEND_4                 ((uint32_t)0x00000010)        /*!< bit 4 */\r
+#define  NVIC_ICPR_CLRPEND_5                 ((uint32_t)0x00000020)        /*!< bit 5 */\r
+#define  NVIC_ICPR_CLRPEND_6                 ((uint32_t)0x00000040)        /*!< bit 6 */\r
+#define  NVIC_ICPR_CLRPEND_7                 ((uint32_t)0x00000080)        /*!< bit 7 */\r
+#define  NVIC_ICPR_CLRPEND_8                 ((uint32_t)0x00000100)        /*!< bit 8 */\r
+#define  NVIC_ICPR_CLRPEND_9                 ((uint32_t)0x00000200)        /*!< bit 9 */\r
+#define  NVIC_ICPR_CLRPEND_10                ((uint32_t)0x00000400)        /*!< bit 10 */\r
+#define  NVIC_ICPR_CLRPEND_11                ((uint32_t)0x00000800)        /*!< bit 11 */\r
+#define  NVIC_ICPR_CLRPEND_12                ((uint32_t)0x00001000)        /*!< bit 12 */\r
+#define  NVIC_ICPR_CLRPEND_13                ((uint32_t)0x00002000)        /*!< bit 13 */\r
+#define  NVIC_ICPR_CLRPEND_14                ((uint32_t)0x00004000)        /*!< bit 14 */\r
+#define  NVIC_ICPR_CLRPEND_15                ((uint32_t)0x00008000)        /*!< bit 15 */\r
+#define  NVIC_ICPR_CLRPEND_16                ((uint32_t)0x00010000)        /*!< bit 16 */\r
+#define  NVIC_ICPR_CLRPEND_17                ((uint32_t)0x00020000)        /*!< bit 17 */\r
+#define  NVIC_ICPR_CLRPEND_18                ((uint32_t)0x00040000)        /*!< bit 18 */\r
+#define  NVIC_ICPR_CLRPEND_19                ((uint32_t)0x00080000)        /*!< bit 19 */\r
+#define  NVIC_ICPR_CLRPEND_20                ((uint32_t)0x00100000)        /*!< bit 20 */\r
+#define  NVIC_ICPR_CLRPEND_21                ((uint32_t)0x00200000)        /*!< bit 21 */\r
+#define  NVIC_ICPR_CLRPEND_22                ((uint32_t)0x00400000)        /*!< bit 22 */\r
+#define  NVIC_ICPR_CLRPEND_23                ((uint32_t)0x00800000)        /*!< bit 23 */\r
+#define  NVIC_ICPR_CLRPEND_24                ((uint32_t)0x01000000)        /*!< bit 24 */\r
+#define  NVIC_ICPR_CLRPEND_25                ((uint32_t)0x02000000)        /*!< bit 25 */\r
+#define  NVIC_ICPR_CLRPEND_26                ((uint32_t)0x04000000)        /*!< bit 26 */\r
+#define  NVIC_ICPR_CLRPEND_27                ((uint32_t)0x08000000)        /*!< bit 27 */\r
+#define  NVIC_ICPR_CLRPEND_28                ((uint32_t)0x10000000)        /*!< bit 28 */\r
+#define  NVIC_ICPR_CLRPEND_29                ((uint32_t)0x20000000)        /*!< bit 29 */\r
+#define  NVIC_ICPR_CLRPEND_30                ((uint32_t)0x40000000)        /*!< bit 30 */\r
+#define  NVIC_ICPR_CLRPEND_31                ((uint32_t)0x80000000)        /*!< bit 31 */\r
+\r
+/******************  Bit definition for NVIC_IABR register  *******************/\r
+#define  NVIC_IABR_ACTIVE                    ((uint32_t)0xFFFFFFFF)        /*!< Interrupt active flags */\r
+#define  NVIC_IABR_ACTIVE_0                  ((uint32_t)0x00000001)        /*!< bit 0 */\r
+#define  NVIC_IABR_ACTIVE_1                  ((uint32_t)0x00000002)        /*!< bit 1 */\r
+#define  NVIC_IABR_ACTIVE_2                  ((uint32_t)0x00000004)        /*!< bit 2 */\r
+#define  NVIC_IABR_ACTIVE_3                  ((uint32_t)0x00000008)        /*!< bit 3 */\r
+#define  NVIC_IABR_ACTIVE_4                  ((uint32_t)0x00000010)        /*!< bit 4 */\r
+#define  NVIC_IABR_ACTIVE_5                  ((uint32_t)0x00000020)        /*!< bit 5 */\r
+#define  NVIC_IABR_ACTIVE_6                  ((uint32_t)0x00000040)        /*!< bit 6 */\r
+#define  NVIC_IABR_ACTIVE_7                  ((uint32_t)0x00000080)        /*!< bit 7 */\r
+#define  NVIC_IABR_ACTIVE_8                  ((uint32_t)0x00000100)        /*!< bit 8 */\r
+#define  NVIC_IABR_ACTIVE_9                  ((uint32_t)0x00000200)        /*!< bit 9 */\r
+#define  NVIC_IABR_ACTIVE_10                 ((uint32_t)0x00000400)        /*!< bit 10 */\r
+#define  NVIC_IABR_ACTIVE_11                 ((uint32_t)0x00000800)        /*!< bit 11 */\r
+#define  NVIC_IABR_ACTIVE_12                 ((uint32_t)0x00001000)        /*!< bit 12 */\r
+#define  NVIC_IABR_ACTIVE_13                 ((uint32_t)0x00002000)        /*!< bit 13 */\r
+#define  NVIC_IABR_ACTIVE_14                 ((uint32_t)0x00004000)        /*!< bit 14 */\r
+#define  NVIC_IABR_ACTIVE_15                 ((uint32_t)0x00008000)        /*!< bit 15 */\r
+#define  NVIC_IABR_ACTIVE_16                 ((uint32_t)0x00010000)        /*!< bit 16 */\r
+#define  NVIC_IABR_ACTIVE_17                 ((uint32_t)0x00020000)        /*!< bit 17 */\r
+#define  NVIC_IABR_ACTIVE_18                 ((uint32_t)0x00040000)        /*!< bit 18 */\r
+#define  NVIC_IABR_ACTIVE_19                 ((uint32_t)0x00080000)        /*!< bit 19 */\r
+#define  NVIC_IABR_ACTIVE_20                 ((uint32_t)0x00100000)        /*!< bit 20 */\r
+#define  NVIC_IABR_ACTIVE_21                 ((uint32_t)0x00200000)        /*!< bit 21 */\r
+#define  NVIC_IABR_ACTIVE_22                 ((uint32_t)0x00400000)        /*!< bit 22 */\r
+#define  NVIC_IABR_ACTIVE_23                 ((uint32_t)0x00800000)        /*!< bit 23 */\r
+#define  NVIC_IABR_ACTIVE_24                 ((uint32_t)0x01000000)        /*!< bit 24 */\r
+#define  NVIC_IABR_ACTIVE_25                 ((uint32_t)0x02000000)        /*!< bit 25 */\r
+#define  NVIC_IABR_ACTIVE_26                 ((uint32_t)0x04000000)        /*!< bit 26 */\r
+#define  NVIC_IABR_ACTIVE_27                 ((uint32_t)0x08000000)        /*!< bit 27 */\r
+#define  NVIC_IABR_ACTIVE_28                 ((uint32_t)0x10000000)        /*!< bit 28 */\r
+#define  NVIC_IABR_ACTIVE_29                 ((uint32_t)0x20000000)        /*!< bit 29 */\r
+#define  NVIC_IABR_ACTIVE_30                 ((uint32_t)0x40000000)        /*!< bit 30 */\r
+#define  NVIC_IABR_ACTIVE_31                 ((uint32_t)0x80000000)        /*!< bit 31 */\r
+\r
+/******************  Bit definition for NVIC_PRI0 register  *******************/\r
+#define  NVIC_IPR0_PRI_0                     ((uint32_t)0x000000FF)        /*!< Priority of interrupt 0 */\r
+#define  NVIC_IPR0_PRI_1                     ((uint32_t)0x0000FF00)        /*!< Priority of interrupt 1 */\r
+#define  NVIC_IPR0_PRI_2                     ((uint32_t)0x00FF0000)        /*!< Priority of interrupt 2 */\r
+#define  NVIC_IPR0_PRI_3                     ((uint32_t)0xFF000000)        /*!< Priority of interrupt 3 */\r
+\r
+/******************  Bit definition for NVIC_PRI1 register  *******************/\r
+#define  NVIC_IPR1_PRI_4                     ((uint32_t)0x000000FF)        /*!< Priority of interrupt 4 */\r
+#define  NVIC_IPR1_PRI_5                     ((uint32_t)0x0000FF00)        /*!< Priority of interrupt 5 */\r
+#define  NVIC_IPR1_PRI_6                     ((uint32_t)0x00FF0000)        /*!< Priority of interrupt 6 */\r
+#define  NVIC_IPR1_PRI_7                     ((uint32_t)0xFF000000)        /*!< Priority of interrupt 7 */\r
+\r
+/******************  Bit definition for NVIC_PRI2 register  *******************/\r
+#define  NVIC_IPR2_PRI_8                     ((uint32_t)0x000000FF)        /*!< Priority of interrupt 8 */\r
+#define  NVIC_IPR2_PRI_9                     ((uint32_t)0x0000FF00)        /*!< Priority of interrupt 9 */\r
+#define  NVIC_IPR2_PRI_10                    ((uint32_t)0x00FF0000)        /*!< Priority of interrupt 10 */\r
+#define  NVIC_IPR2_PRI_11                    ((uint32_t)0xFF000000)        /*!< Priority of interrupt 11 */\r
+\r
+/******************  Bit definition for NVIC_PRI3 register  *******************/\r
+#define  NVIC_IPR3_PRI_12                    ((uint32_t)0x000000FF)        /*!< Priority of interrupt 12 */\r
+#define  NVIC_IPR3_PRI_13                    ((uint32_t)0x0000FF00)        /*!< Priority of interrupt 13 */\r
+#define  NVIC_IPR3_PRI_14                    ((uint32_t)0x00FF0000)        /*!< Priority of interrupt 14 */\r
+#define  NVIC_IPR3_PRI_15                    ((uint32_t)0xFF000000)        /*!< Priority of interrupt 15 */\r
+\r
+/******************  Bit definition for NVIC_PRI4 register  *******************/\r
+#define  NVIC_IPR4_PRI_16                    ((uint32_t)0x000000FF)        /*!< Priority of interrupt 16 */\r
+#define  NVIC_IPR4_PRI_17                    ((uint32_t)0x0000FF00)        /*!< Priority of interrupt 17 */\r
+#define  NVIC_IPR4_PRI_18                    ((uint32_t)0x00FF0000)        /*!< Priority of interrupt 18 */\r
+#define  NVIC_IPR4_PRI_19                    ((uint32_t)0xFF000000)        /*!< Priority of interrupt 19 */\r
+\r
+/******************  Bit definition for NVIC_PRI5 register  *******************/\r
+#define  NVIC_IPR5_PRI_20                    ((uint32_t)0x000000FF)        /*!< Priority of interrupt 20 */\r
+#define  NVIC_IPR5_PRI_21                    ((uint32_t)0x0000FF00)        /*!< Priority of interrupt 21 */\r
+#define  NVIC_IPR5_PRI_22                    ((uint32_t)0x00FF0000)        /*!< Priority of interrupt 22 */\r
+#define  NVIC_IPR5_PRI_23                    ((uint32_t)0xFF000000)        /*!< Priority of interrupt 23 */\r
+\r
+/******************  Bit definition for NVIC_PRI6 register  *******************/\r
+#define  NVIC_IPR6_PRI_24                    ((uint32_t)0x000000FF)        /*!< Priority of interrupt 24 */\r
+#define  NVIC_IPR6_PRI_25                    ((uint32_t)0x0000FF00)        /*!< Priority of interrupt 25 */\r
+#define  NVIC_IPR6_PRI_26                    ((uint32_t)0x00FF0000)        /*!< Priority of interrupt 26 */\r
+#define  NVIC_IPR6_PRI_27                    ((uint32_t)0xFF000000)        /*!< Priority of interrupt 27 */\r
+\r
+/******************  Bit definition for NVIC_PRI7 register  *******************/\r
+#define  NVIC_IPR7_PRI_28                    ((uint32_t)0x000000FF)        /*!< Priority of interrupt 28 */\r
+#define  NVIC_IPR7_PRI_29                    ((uint32_t)0x0000FF00)        /*!< Priority of interrupt 29 */\r
+#define  NVIC_IPR7_PRI_30                    ((uint32_t)0x00FF0000)        /*!< Priority of interrupt 30 */\r
+#define  NVIC_IPR7_PRI_31                    ((uint32_t)0xFF000000)        /*!< Priority of interrupt 31 */\r
+\r
+/******************  Bit definition for SCB_CPUID register  *******************/\r
+#define  SCB_CPUID_REVISION                  ((uint32_t)0x0000000F)        /*!< Implementation defined revision number */\r
+#define  SCB_CPUID_PARTNO                    ((uint32_t)0x0000FFF0)        /*!< Number of processor within family */\r
+#define  SCB_CPUID_Constant                  ((uint32_t)0x000F0000)        /*!< Reads as 0x0F */\r
+#define  SCB_CPUID_VARIANT                   ((uint32_t)0x00F00000)        /*!< Implementation defined variant number */\r
+#define  SCB_CPUID_IMPLEMENTER               ((uint32_t)0xFF000000)        /*!< Implementer code. ARM is 0x41 */\r
+\r
+/*******************  Bit definition for SCB_ICSR register  *******************/\r
+#define  SCB_ICSR_VECTACTIVE                 ((uint32_t)0x000001FF)        /*!< Active ISR number field */\r
+#define  SCB_ICSR_RETTOBASE                  ((uint32_t)0x00000800)        /*!< All active exceptions minus the IPSR_current_exception yields the empty set */\r
+#define  SCB_ICSR_VECTPENDING                ((uint32_t)0x003FF000)        /*!< Pending ISR number field */\r
+#define  SCB_ICSR_ISRPENDING                 ((uint32_t)0x00400000)        /*!< Interrupt pending flag */\r
+#define  SCB_ICSR_ISRPREEMPT                 ((uint32_t)0x00800000)        /*!< It indicates that a pending interrupt becomes active in the next running cycle */\r
+#define  SCB_ICSR_PENDSTCLR                  ((uint32_t)0x02000000)        /*!< Clear pending SysTick bit */\r
+#define  SCB_ICSR_PENDSTSET                  ((uint32_t)0x04000000)        /*!< Set pending SysTick bit */\r
+#define  SCB_ICSR_PENDSVCLR                  ((uint32_t)0x08000000)        /*!< Clear pending pendSV bit */\r
+#define  SCB_ICSR_PENDSVSET                  ((uint32_t)0x10000000)        /*!< Set pending pendSV bit */\r
+#define  SCB_ICSR_NMIPENDSET                 ((uint32_t)0x80000000)        /*!< Set pending NMI bit */\r
+\r
+/*******************  Bit definition for SCB_VTOR register  *******************/\r
+#define  SCB_VTOR_TBLOFF                     ((uint32_t)0x1FFFFF80)        /*!< Vector table base offset field */\r
+#define  SCB_VTOR_TBLBASE                    ((uint32_t)0x20000000)        /*!< Table base in code(0) or RAM(1) */\r
+\r
+/*!<*****************  Bit definition for SCB_AIRCR register  *******************/\r
+#define  SCB_AIRCR_VECTRESET                 ((uint32_t)0x00000001)        /*!< System Reset bit */\r
+#define  SCB_AIRCR_VECTCLRACTIVE             ((uint32_t)0x00000002)        /*!< Clear active vector bit */\r
+#define  SCB_AIRCR_SYSRESETREQ               ((uint32_t)0x00000004)        /*!< Requests chip control logic to generate a reset */\r
+\r
+#define  SCB_AIRCR_PRIGROUP                  ((uint32_t)0x00000700)        /*!< PRIGROUP[2:0] bits (Priority group) */\r
+#define  SCB_AIRCR_PRIGROUP_0                ((uint32_t)0x00000100)        /*!< Bit 0 */\r
+#define  SCB_AIRCR_PRIGROUP_1                ((uint32_t)0x00000200)        /*!< Bit 1 */\r
+#define  SCB_AIRCR_PRIGROUP_2                ((uint32_t)0x00000400)        /*!< Bit 2  */\r
+\r
+/* prority group configuration */\r
+#define  SCB_AIRCR_PRIGROUP0                 ((uint32_t)0x00000000)        /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */\r
+#define  SCB_AIRCR_PRIGROUP1                 ((uint32_t)0x00000100)        /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */\r
+#define  SCB_AIRCR_PRIGROUP2                 ((uint32_t)0x00000200)        /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */\r
+#define  SCB_AIRCR_PRIGROUP3                 ((uint32_t)0x00000300)        /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */\r
+#define  SCB_AIRCR_PRIGROUP4                 ((uint32_t)0x00000400)        /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */\r
+#define  SCB_AIRCR_PRIGROUP5                 ((uint32_t)0x00000500)        /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */\r
+#define  SCB_AIRCR_PRIGROUP6                 ((uint32_t)0x00000600)        /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */\r
+#define  SCB_AIRCR_PRIGROUP7                 ((uint32_t)0x00000700)        /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */\r
+\r
+#define  SCB_AIRCR_ENDIANESS                 ((uint32_t)0x00008000)        /*!< Data endianness bit */\r
+#define  SCB_AIRCR_VECTKEY                   ((uint32_t)0xFFFF0000)        /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */\r
+\r
+/*******************  Bit definition for SCB_SCR register  ********************/\r
+#define  SCB_SCR_SLEEPONEXIT                 ((uint8_t)0x02)               /*!< Sleep on exit bit */\r
+#define  SCB_SCR_SLEEPDEEP                   ((uint8_t)0x04)               /*!< Sleep deep bit */\r
+#define  SCB_SCR_SEVONPEND                   ((uint8_t)0x10)               /*!< Wake up from WFE */\r
+\r
+/********************  Bit definition for SCB_CCR register  *******************/\r
+#define  SCB_CCR_NONBASETHRDENA              ((uint16_t)0x0001)            /*!< Thread mode can be entered from any level in Handler mode by controlled return value */\r
+#define  SCB_CCR_USERSETMPEND                ((uint16_t)0x0002)            /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */\r
+#define  SCB_CCR_UNALIGN_TRP                 ((uint16_t)0x0008)            /*!< Trap for unaligned access */\r
+#define  SCB_CCR_DIV_0_TRP                   ((uint16_t)0x0010)            /*!< Trap on Divide by 0 */\r
+#define  SCB_CCR_BFHFNMIGN                   ((uint16_t)0x0100)            /*!< Handlers running at priority -1 and -2 */\r
+#define  SCB_CCR_STKALIGN                    ((uint16_t)0x0200)            /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */\r
+\r
+/*******************  Bit definition for SCB_SHPR register ********************/\r
+#define  SCB_SHPR_PRI_N                      ((uint32_t)0x000000FF)        /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */\r
+#define  SCB_SHPR_PRI_N1                     ((uint32_t)0x0000FF00)        /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */\r
+#define  SCB_SHPR_PRI_N2                     ((uint32_t)0x00FF0000)        /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */\r
+#define  SCB_SHPR_PRI_N3                     ((uint32_t)0xFF000000)        /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */\r
+\r
+/******************  Bit definition for SCB_SHCSR register  *******************/\r
+#define  SCB_SHCSR_MEMFAULTACT               ((uint32_t)0x00000001)        /*!< MemManage is active */\r
+#define  SCB_SHCSR_BUSFAULTACT               ((uint32_t)0x00000002)        /*!< BusFault is active */\r
+#define  SCB_SHCSR_USGFAULTACT               ((uint32_t)0x00000008)        /*!< UsageFault is active */\r
+#define  SCB_SHCSR_SVCALLACT                 ((uint32_t)0x00000080)        /*!< SVCall is active */\r
+#define  SCB_SHCSR_MONITORACT                ((uint32_t)0x00000100)        /*!< Monitor is active */\r
+#define  SCB_SHCSR_PENDSVACT                 ((uint32_t)0x00000400)        /*!< PendSV is active */\r
+#define  SCB_SHCSR_SYSTICKACT                ((uint32_t)0x00000800)        /*!< SysTick is active */\r
+#define  SCB_SHCSR_USGFAULTPENDED            ((uint32_t)0x00001000)        /*!< Usage Fault is pended */\r
+#define  SCB_SHCSR_MEMFAULTPENDED            ((uint32_t)0x00002000)        /*!< MemManage is pended */\r
+#define  SCB_SHCSR_BUSFAULTPENDED            ((uint32_t)0x00004000)        /*!< Bus Fault is pended */\r
+#define  SCB_SHCSR_SVCALLPENDED              ((uint32_t)0x00008000)        /*!< SVCall is pended */\r
+#define  SCB_SHCSR_MEMFAULTENA               ((uint32_t)0x00010000)        /*!< MemManage enable */\r
+#define  SCB_SHCSR_BUSFAULTENA               ((uint32_t)0x00020000)        /*!< Bus Fault enable */\r
+#define  SCB_SHCSR_USGFAULTENA               ((uint32_t)0x00040000)        /*!< UsageFault enable */\r
+\r
+/*******************  Bit definition for SCB_CFSR register  *******************/\r
+/*!< MFSR */\r
+#define  SCB_CFSR_IACCVIOL                   ((uint32_t)0x00000001)        /*!< Instruction access violation */\r
+#define  SCB_CFSR_DACCVIOL                   ((uint32_t)0x00000002)        /*!< Data access violation */\r
+#define  SCB_CFSR_MUNSTKERR                  ((uint32_t)0x00000008)        /*!< Unstacking error */\r
+#define  SCB_CFSR_MSTKERR                    ((uint32_t)0x00000010)        /*!< Stacking error */\r
+#define  SCB_CFSR_MMARVALID                  ((uint32_t)0x00000080)        /*!< Memory Manage Address Register address valid flag */\r
+/*!< BFSR */\r
+#define  SCB_CFSR_IBUSERR                    ((uint32_t)0x00000100)        /*!< Instruction bus error flag */\r
+#define  SCB_CFSR_PRECISERR                  ((uint32_t)0x00000200)        /*!< Precise data bus error */\r
+#define  SCB_CFSR_IMPRECISERR                ((uint32_t)0x00000400)        /*!< Imprecise data bus error */\r
+#define  SCB_CFSR_UNSTKERR                   ((uint32_t)0x00000800)        /*!< Unstacking error */\r
+#define  SCB_CFSR_STKERR                     ((uint32_t)0x00001000)        /*!< Stacking error */\r
+#define  SCB_CFSR_BFARVALID                  ((uint32_t)0x00008000)        /*!< Bus Fault Address Register address valid flag */\r
+/*!< UFSR */\r
+#define  SCB_CFSR_UNDEFINSTR                 ((uint32_t)0x00010000)        /*!< The processor attempt to excecute an undefined instruction */\r
+#define  SCB_CFSR_INVSTATE                   ((uint32_t)0x00020000)        /*!< Invalid combination of EPSR and instruction */\r
+#define  SCB_CFSR_INVPC                      ((uint32_t)0x00040000)        /*!< Attempt to load EXC_RETURN into pc illegally */\r
+#define  SCB_CFSR_NOCP                       ((uint32_t)0x00080000)        /*!< Attempt to use a coprocessor instruction */\r
+#define  SCB_CFSR_UNALIGNED                  ((uint32_t)0x01000000)        /*!< Fault occurs when there is an attempt to make an unaligned memory access */\r
+#define  SCB_CFSR_DIVBYZERO                  ((uint32_t)0x02000000)        /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */\r
+\r
+/*******************  Bit definition for SCB_HFSR register  *******************/\r
+#define  SCB_HFSR_VECTTBL                    ((uint32_t)0x00000002)        /*!< Fault occures because of vector table read on exception processing */\r
+#define  SCB_HFSR_FORCED                     ((uint32_t)0x40000000)        /*!< Hard Fault activated when a configurable Fault was received and cannot activate */\r
+#define  SCB_HFSR_DEBUGEVT                   ((uint32_t)0x80000000)        /*!< Fault related to debug */\r
+\r
+/*******************  Bit definition for SCB_DFSR register  *******************/\r
+#define  SCB_DFSR_HALTED                     ((uint8_t)0x01)               /*!< Halt request flag */\r
+#define  SCB_DFSR_BKPT                       ((uint8_t)0x02)               /*!< BKPT flag */\r
+#define  SCB_DFSR_DWTTRAP                    ((uint8_t)0x04)               /*!< Data Watchpoint and Trace (DWT) flag */\r
+#define  SCB_DFSR_VCATCH                     ((uint8_t)0x08)               /*!< Vector catch flag */\r
+#define  SCB_DFSR_EXTERNAL                   ((uint8_t)0x10)               /*!< External debug request flag */\r
+\r
+/*******************  Bit definition for SCB_MMFAR register  ******************/\r
+#define  SCB_MMFAR_ADDRESS                   ((uint32_t)0xFFFFFFFF)        /*!< Mem Manage fault address field */\r
+\r
+/*******************  Bit definition for SCB_BFAR register  *******************/\r
+#define  SCB_BFAR_ADDRESS                    ((uint32_t)0xFFFFFFFF)        /*!< Bus fault address field */\r
+\r
+/*******************  Bit definition for SCB_afsr register  *******************/\r
+#define  SCB_AFSR_IMPDEF                     ((uint32_t)0xFFFFFFFF)        /*!< Implementation defined */\r
+/**\r
+  * @}\r
+  */\r
+\r
+ /**\r
+  * @}\r
+  */ \r
+\r
+#ifdef USE_STDPERIPH_DRIVER\r
+  #include "stm32l1xx_conf.h"\r
+#endif\r
+\r
+/** @addtogroup Exported_macro\r
+  * @{\r
+  */\r
+\r
+#define SET_BIT(REG, BIT)     ((REG) |= (BIT))\r
+\r
+#define CLEAR_BIT(REG, BIT)   ((REG) &= ~(BIT))\r
+\r
+#define READ_BIT(REG, BIT)    ((REG) & (BIT))\r
+\r
+#define CLEAR_REG(REG)        ((REG) = (0x0))\r
+\r
+#define WRITE_REG(REG, VAL)   ((REG) = (VAL))\r
+\r
+#define READ_REG(REG)         ((REG))\r
+\r
+#define MODIFY_REG(REG, CLEARMASK, SETMASK)  WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32L1XX_H */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+  /**\r
+  * @}\r
+  */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r

diff --git a/Demo/CORTEX_STM32L152_IAR/system_and_ST_code/CMSIS/CM3/DeviceSupport/ST/STM32L1xx/system_stm32l1xx.h b/Demo/CORTEX_STM32L152_IAR/system_and_ST_code/CMSIS/CM3/DeviceSupport/ST/STM32L1xx/system_stm32l1xx.h
new file mode 100644 (file)
index 0000000..9f2ec07
--- /dev/null
+++ b/Demo/CORTEX_STM32L152_IAR/system_and_ST_code/CMSIS/CM3/DeviceSupport/ST/STM32L1xx/system_stm32l1xx.h
@@ -0,0 +1,97 @@
+/**\r
+  ******************************************************************************\r
+  * @file    system_stm32l1xx.h\r
+  * @author  MCD Application Team\r
+  * @version V1.0.0RC1\r
+  * @date    07/02/2010\r
+  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Header File.\r
+  ******************************************************************************  \r
+  *\r
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+  *\r
+  * <h2><center>&copy; COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+  ******************************************************************************\r
+  */\r
+\r
+/** @addtogroup CMSIS\r
+  * @{\r
+  */\r
+\r
+/** @addtogroup stm32l1xx_system\r
+  * @{\r
+  */  \r
+  \r
+/**\r
+  * @brief Define to prevent recursive inclusion\r
+  */\r
+#ifndef __SYSTEM_STM32L1XX_H\r
+#define __SYSTEM_STM32L1XX_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif \r
+\r
+/** @addtogroup STM32L1xx_System_Includes\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+\r
+/** @addtogroup STM32L1xx_System_Exported_types\r
+  * @{\r
+  */\r
+\r
+extern uint32_t SystemCoreClock;          /*!< System Clock Frequency (Core Clock) */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @addtogroup STM32L1xx_System_Exported_Constants\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @addtogroup STM32L1xx_System_Exported_Macros\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @addtogroup STM32L1xx_System_Exported_Functions\r
+  * @{\r
+  */\r
+  \r
+extern void SystemInit(void);\r
+extern void SystemCoreClockUpdate(void);\r
+/**\r
+  * @}\r
+  */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /*__SYSTEM_STM32L1XX_H */\r
+\r
+/**\r
+  * @}\r
+  */\r
+  \r
+/**\r
+  * @}\r
+  */  \r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r

diff --git a/Demo/CORTEX_STM32L152_IAR/system_and_ST_code/CMSIS/CMSIS changes.htm b/Demo/CORTEX_STM32L152_IAR/system_and_ST_code/CMSIS/CMSIS changes.htm
new file mode 100644 (file)
index 0000000..162ffcc
--- /dev/null
+++ b/Demo/CORTEX_STM32L152_IAR/system_and_ST_code/CMSIS/CMSIS changes.htm
@@ -0,0 +1,320 @@
+<html>\r
+\r
+<head>\r
+<title>CMSIS Changes</title>\r
+<meta http-equiv="Content-Type" content="text/html; charset=windows-1252">\r
+<meta name="GENERATOR" content="Microsoft FrontPage 6.0">\r
+<meta name="ProgId" content="FrontPage.Editor.Document">\r
+<style>\r
+<!--\r
+/*-----------------------------------------------------------\r
+Keil Software CHM Style Sheet\r
+-----------------------------------------------------------*/\r
+body         { color: #000000; background-color: #FFFFFF; font-size: 75%; font-family: \r
+               Verdana, Arial, 'Sans Serif' }\r
+a:link       { color: #0000FF; text-decoration: underline }\r
+a:visited    { color: #0000FF; text-decoration: underline }\r
+a:active     { color: #FF0000; text-decoration: underline }\r
+a:hover      { color: #FF0000; text-decoration: underline }\r
+h1           { font-family: Verdana; font-size: 18pt; color: #000080; font-weight: bold; \r
+               text-align: Center; margin-right: 3 }\r
+h2           { font-family: Verdana; font-size: 14pt; color: #000080; font-weight: bold; \r
+               background-color: #CCCCCC; margin-top: 24; margin-bottom: 3; \r
+               padding: 6 }\r
+h3           { font-family: Verdana; font-size: 10pt; font-weight: bold; background-color: \r
+               #CCCCCC; margin-top: 24; margin-bottom: 3; padding: 6 }\r
+pre          { font-family: Courier New; font-size: 10pt; background-color: #CCFFCC; \r
+               margin-left: 24; margin-right: 24 }\r
+ul           { list-style-type: square; margin-top: 6pt; margin-bottom: 0 }\r
+ol           { margin-top: 6pt; margin-bottom: 0 }\r
+li           { clear: both; margin-bottom: 6pt }\r
+table        { font-size: 100%; border-width: 0; padding: 0 }\r
+th           { color: #FFFFFF; background-color: #000080; text-align: left; vertical-align: \r
+               bottom; padding-right: 6pt }\r
+tr           { text-align: left; vertical-align: top }\r
+td           { text-align: left; vertical-align: top; padding-right: 6pt }\r
+.ToolT       { font-size: 8pt; color: #808080 }\r
+.TinyT       { font-size: 8pt; text-align: Center }\r
+code         { color: #000000; background-color: #E0E0E0; font-family: 'Courier New', Courier; \r
+               line-height: 120%; font-style: normal }\r
+/*-----------------------------------------------------------\r
+Notes\r
+-----------------------------------------------------------*/\r
+p.note       { font-weight: bold; clear: both; margin-bottom: 3pt; padding-top: 6pt }\r
+/*-----------------------------------------------------------\r
+Expanding/Contracting Divisions\r
+-----------------------------------------------------------*/\r
+#expand      { text-decoration: none; margin-bottom: 3pt }\r
+img.expand   { border-style: none; border-width: medium }\r
+div.expand   { display: none; margin-left: 9pt; margin-top: 0 }\r
+/*-----------------------------------------------------------\r
+Where List Tags\r
+-----------------------------------------------------------*/\r
+p.wh         { font-weight: bold; clear: both; margin-top: 6pt; margin-bottom: 3pt }\r
+table.wh     { width: 100% }\r
+td.whItem    { white-space: nowrap; font-style: italic; padding-right: 6pt; padding-bottom: \r
+               6pt }\r
+td.whDesc    { padding-bottom: 6pt }\r
+/*-----------------------------------------------------------\r
+Keil Table Tags\r
+-----------------------------------------------------------*/\r
+table.kt     { border: 1pt solid #000000 }\r
+th.kt        { white-space: nowrap; border-bottom: 1pt solid #000000; padding-left: 6pt; \r
+               padding-right: 6pt; padding-top: 4pt; padding-bottom: 4pt }\r
+tr.kt        {  }\r
+td.kt        { color: #000000; background-color: #E0E0E0; border-top: 1pt solid #A0A0A0; \r
+               padding-left: 6pt; padding-right: 6pt; padding-top: 2pt; \r
+               padding-bottom: 2pt }\r
+/*-----------------------------------------------------------\r
+-----------------------------------------------------------*/\r
+-->\r
+\r
+</style>\r
+</head>\r
+\r
+<body>\r
+\r
+<h1>Changes to CMSIS version V1.20</h1>\r
+\r
+<hr>\r
+\r
+<h2>1. Removed CMSIS Middelware packages</h2>\r
+<p>\r
+  CMSIS Middleware is on hold from ARM side until a agreement between all CMSIS partners is found.\r
+</p>\r
+\r
+<h2>2. SystemFrequency renamed to SystemCoreClock</h2>\r
+<p>\r
+  The variable name <strong>SystemCoreClock</strong> is more precise than <strong>SystemFrequency</strong>\r
+  because the variable holds the clock value at which the core is running.\r
+</p>\r
+\r
+<h2>3. Changed startup concept</h2>\r
+<p>\r
+  The old startup concept (calling SystemInit_ExtMemCtl from startup file and calling SystemInit \r
+  from main) has the weakness that it does not work for controllers which need a already \r
+  configuerd clock system to configure the external memory controller.\r
+</p>\r
+\r
+<h3>Changed startup concept</h3>\r
+<ul>\r
+  <li>\r
+    SystemInit() is called from startup file before <strong>premain</strong>.\r
+  </li>\r
+  <li>\r
+    <strong>SystemInit()</strong> configures the clock system and also configures\r
+    an existing external memory controller.\r
+  </li>\r
+  <li>\r
+    <strong>SystemInit()</strong> must not use global variables.\r
+  </li>\r
+  <li>\r
+    <strong>SystemCoreClock</strong> is initialized with a correct predefined value.\r
+  </li>\r
+  <li>\r
+    Additional function <strong>void SystemCoreClockUpdate (void)</strong> is provided.<br>\r
+   <strong>SystemCoreClockUpdate()</strong> updates the variable <strong>SystemCoreClock</strong>\r
+   and must be called whenever the core clock is changed.<br>\r
+   <strong>SystemCoreClockUpdate()</strong> evaluates the clock register settings and calculates\r
+   the current core clock.\r
+  </li>\r
+</ul>\r
+      \r
+\r
+<h2>4. Advanced Debug Functions</h2>\r
+<p>\r
+  ITM communication channel is only capable for OUT direction. To allow also communication for\r
+  IN direction a simple concept is provided.\r
+</p>\r
+<ul>\r
+  <li>\r
+    Global variable <strong>volatile int ITM_RxBuffer</strong> used for IN data.\r
+  </li>\r
+  <li>\r
+    Function <strong>int ITM_CheckChar (void)</strong> checks if a new character is available.\r
+  </li>\r
+  <li>\r
+    Function <strong>int ITM_ReceiveChar (void)</strong> retrieves the new character.\r
+  </li>\r
+</ul>\r
+\r
+<p>\r
+  For detailed explanation see file <strong>CMSIS debug support.htm</strong>. \r
+</p>\r
+\r
+\r
+<h2>5. Core Register Bit Definitions</h2>\r
+<p>\r
+  Files core_cm3.h and core_cm0.h contain now bit definitions for Core Registers. The name for the\r
+  defines correspond with the Cortex-M Technical Reference Manual.  \r
+</p>\r
+<p>\r
+  e.g. SysTick structure with bit definitions\r
+</p>\r
+<pre>\r
+/** @addtogroup CMSIS_CM3_SysTick CMSIS CM3 SysTick\r
+  memory mapped structure for SysTick\r
+  @{\r
+ */\r
+typedef struct\r
+{\r
+  __IO uint32_t CTRL;                         /*!< Offset: 0x00  SysTick Control and Status Register */\r
+  __IO uint32_t LOAD;                         /*!< Offset: 0x04  SysTick Reload Value Register       */\r
+  __IO uint32_t VAL;                          /*!< Offset: 0x08  SysTick Current Value Register      */\r
+  __I  uint32_t CALIB;                        /*!< Offset: 0x0C  SysTick Calibration Register        */\r
+} SysTick_Type;\r
+\r
+/* SysTick Control / Status Register Definitions */\r
+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */\r
+#define SysTick_CTRL_COUNTFLAG_Msk         (1ul << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */\r
+\r
+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */\r
+#define SysTick_CTRL_CLKSOURCE_Msk         (1ul << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */\r
+\r
+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */\r
+#define SysTick_CTRL_TICKINT_Msk           (1ul << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */\r
+\r
+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */\r
+#define SysTick_CTRL_ENABLE_Msk            (1ul << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */\r
+\r
+/* SysTick Reload Register Definitions */\r
+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */\r
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFul << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */\r
+\r
+/* SysTick Current Register Definitions */\r
+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */\r
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFul << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */\r
+\r
+/* SysTick Calibration Register Definitions */\r
+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */\r
+#define SysTick_CALIB_NOREF_Msk            (1ul << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */\r
+\r
+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */\r
+#define SysTick_CALIB_SKEW_Msk             (1ul << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */\r
+\r
+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */\r
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFul << SysTick_VAL_CURRENT_Pos)        /*!< SysTick CALIB: TENMS Mask */\r
+/*@}*/ /* end of group CMSIS_CM3_SysTick */</pre>\r
+\r
+<h2>7. DoxyGen Tags</h2>\r
+<p>\r
+  DoxyGen tags in files core_cm3.[c,h] and core_cm0.[c,h] are reworked to create proper documentation\r
+  using DoxyGen.\r
+</p>\r
+\r
+<h2>8. Folder Structure</h2>\r
+<p>\r
+  The folder structure is changed to differentiate the single support packages.\r
+</p>\r
+\r
+  <ul>\r
+    <li>CM0</li>\r
+    <li>CM3\r
+       <ul>\r
+         <li>CoreSupport</li>\r
+         <li>DeviceSupport</li>\r
+           <ul>\r
+             <li>Vendor \r
+               <ul>\r
+                 <li>Device\r
+                   <ul>\r
+                      <li>Startup\r
+                        <ul>\r
+                          <li>Toolchain</li>\r
+                          <li>Toolchain</li>\r
+                          <li>...</li>\r
+                        </ul>\r
+                      </li>\r
+                   </ul>\r
+                 </li>\r
+                 <li>Device</li>\r
+                 <li>...</li>\r
+               </ul>\r
+             </li>\r
+             <li>Vendor</li>\r
+             <li>...</li>\r
+           </ul>\r
+         </li>\r
+         <li>Example\r
+           <ul>\r
+             <li>Toolchain \r
+               <ul>\r
+                 <li>Device</li>\r
+                 <li>Device</li>\r
+                 <li>...</li>\r
+               </ul>\r
+             </li>\r
+             <li>Toolchain</li>\r
+             <li>...</li>\r
+           </ul>\r
+         </li>\r
+       </ul>\r
+    </li>\r
+     \r
+    <li>Documentation</li>\r
+  </ul>\r
+\r
+<h2>9. Open Points</h2>\r
+<p>\r
+  Following points need to be clarified and solved:\r
+</p>\r
+<ul>\r
+  <li>\r
+    <p>\r
+      Equivalent C and Assembler startup files.\r
+    </p>\r
+    <p>\r
+      Is there a need for having C startup files although assembler startup files are\r
+      very efficient and do not need to be changed?\r
+    <p/>\r
+  </li>\r
+  <li>\r
+    <p>\r
+      Placing of HEAP in external RAM.\r
+    </p>\r
+    <p>\r
+      It must be possible to place HEAP in external RAM if the device supports an \r
+      external memory controller.\r
+    </p>\r
+  </li>\r
+  <li>\r
+    <p>\r
+      Placing of STACK /HEAP.\r
+    </p>\r
+    <p>\r
+      STACK should always be placed at the end of internal RAM.\r
+    </p>\r
+    <p>\r
+      If HEAP is placed in internal RAM than it should be placed after RW ZI section.\r
+    </p>\r
+  </li>\r
+  <li>\r
+    <p>\r
+      Removing core_cm3.c and core_cm0.c.\r
+    </p>\r
+    <p>\r
+      On a long term the functions in core_cm3.c and core_cm0.c must be replaced with \r
+      appropriate compiler intrinsics.\r
+    </p>\r
+  </li>\r
+</ul>\r
+\r
+\r
+<h2>10. Limitations</h2>\r
+<p>\r
+  The following limitations are not covered with the current CMSIS version:\r
+</p>\r
+<ul>\r
+ <li>\r
+  No <strong>C startup files</strong> for ARM toolchain are provided. \r
+ </li>\r
+ <li>\r
+  No <strong>C startup files</strong> for GNU toolchain are provided. \r
+ </li>\r
+ <li>\r
+  No <strong>C startup files</strong> for IAR toolchain are provided. \r
+ </li>\r
+ <li>\r
+  No <strong>Tasking</strong> projects are provided yet. \r
+ </li>\r
+</ul>\r

diff --git a/Demo/CORTEX_STM32L152_IAR/system_and_ST_code/CMSIS/CMSIS debug support.htm b/Demo/CORTEX_STM32L152_IAR/system_and_ST_code/CMSIS/CMSIS debug support.htm
new file mode 100644 (file)
index 0000000..efda685
--- /dev/null
+++ b/Demo/CORTEX_STM32L152_IAR/system_and_ST_code/CMSIS/CMSIS debug support.htm
@@ -0,0 +1,243 @@
+<html>\r
+\r
+<head>\r
+<title>CMSIS Debug Support</title>\r
+<meta http-equiv="Content-Type" content="text/html; charset=windows-1252">\r
+<meta name="GENERATOR" content="Microsoft FrontPage 6.0">\r
+<meta name="ProgId" content="FrontPage.Editor.Document">\r
+<style>\r
+<!--\r
+/*-----------------------------------------------------------\r
+Keil Software CHM Style Sheet\r
+-----------------------------------------------------------*/\r
+body         { color: #000000; background-color: #FFFFFF; font-size: 75%; font-family: \r
+               Verdana, Arial, 'Sans Serif' }\r
+a:link       { color: #0000FF; text-decoration: underline }\r
+a:visited    { color: #0000FF; text-decoration: underline }\r
+a:active     { color: #FF0000; text-decoration: underline }\r
+a:hover      { color: #FF0000; text-decoration: underline }\r
+h1           { font-family: Verdana; font-size: 18pt; color: #000080; font-weight: bold; \r
+               text-align: Center; margin-right: 3 }\r
+h2           { font-family: Verdana; font-size: 14pt; color: #000080; font-weight: bold; \r
+               background-color: #CCCCCC; margin-top: 24; margin-bottom: 3; \r
+               padding: 6 }\r
+h3           { font-family: Verdana; font-size: 10pt; font-weight: bold; background-color: \r
+               #CCCCCC; margin-top: 24; margin-bottom: 3; padding: 6 }\r
+pre          { font-family: Courier New; font-size: 10pt; background-color: #CCFFCC; \r
+               margin-left: 24; margin-right: 24 }\r
+ul           { list-style-type: square; margin-top: 6pt; margin-bottom: 0 }\r
+ol           { margin-top: 6pt; margin-bottom: 0 }\r
+li           { clear: both; margin-bottom: 6pt }\r
+table        { font-size: 100%; border-width: 0; padding: 0 }\r
+th           { color: #FFFFFF; background-color: #000080; text-align: left; vertical-align: \r
+               bottom; padding-right: 6pt }\r
+tr           { text-align: left; vertical-align: top }\r
+td           { text-align: left; vertical-align: top; padding-right: 6pt }\r
+.ToolT       { font-size: 8pt; color: #808080 }\r
+.TinyT       { font-size: 8pt; text-align: Center }\r
+code         { color: #000000; background-color: #E0E0E0; font-family: 'Courier New', Courier; \r
+               line-height: 120%; font-style: normal }\r
+/*-----------------------------------------------------------\r
+Notes\r
+-----------------------------------------------------------*/\r
+p.note       { font-weight: bold; clear: both; margin-bottom: 3pt; padding-top: 6pt }\r
+/*-----------------------------------------------------------\r
+Expanding/Contracting Divisions\r
+-----------------------------------------------------------*/\r
+#expand      { text-decoration: none; margin-bottom: 3pt }\r
+img.expand   { border-style: none; border-width: medium }\r
+div.expand   { display: none; margin-left: 9pt; margin-top: 0 }\r
+/*-----------------------------------------------------------\r
+Where List Tags\r
+-----------------------------------------------------------*/\r
+p.wh         { font-weight: bold; clear: both; margin-top: 6pt; margin-bottom: 3pt }\r
+table.wh     { width: 100% }\r
+td.whItem    { white-space: nowrap; font-style: italic; padding-right: 6pt; padding-bottom: \r
+               6pt }\r
+td.whDesc    { padding-bottom: 6pt }\r
+/*-----------------------------------------------------------\r
+Keil Table Tags\r
+-----------------------------------------------------------*/\r
+table.kt     { border: 1pt solid #000000 }\r
+th.kt        { white-space: nowrap; border-bottom: 1pt solid #000000; padding-left: 6pt; \r
+               padding-right: 6pt; padding-top: 4pt; padding-bottom: 4pt }\r
+tr.kt        {  }\r
+td.kt        { color: #000000; background-color: #E0E0E0; border-top: 1pt solid #A0A0A0; \r
+               padding-left: 6pt; padding-right: 6pt; padding-top: 2pt; \r
+               padding-bottom: 2pt }\r
+/*-----------------------------------------------------------\r
+-----------------------------------------------------------*/\r
+-->\r
+\r
+</style>\r
+</head>\r
+\r
+<body>\r
+\r
+<h1>CMSIS Debug Support</h1>\r
+\r
+<hr>\r
+\r
+<h2>Cortex-M3 ITM Debug Access</h2>\r
+<p>\r
+  The Cortex-M3 incorporates the Instrumented Trace Macrocell (ITM) that provides together with \r
+  the Serial Viewer Output trace capabilities for the microcontroller system. The ITM has \r
+  32 communication channels which are able to transmit 32 / 16 / 8 bit values; two ITM \r
+  communication channels are used by CMSIS to output the following information:\r
+</p>\r
+<ul>\r
+       <li>ITM Channel 0: used for printf-style output via the debug interface.</li>\r
+       <li>ITM Channel 31: is reserved for RTOS kernel awareness debugging.</li>\r
+</ul>\r
+\r
+<h2>Debug IN / OUT functions</h2>\r
+<p>CMSIS provides following debug functions:</p>\r
+<ul>\r
+       <li>ITM_SendChar (uses ITM channel 0)</li>\r
+       <li>ITM_ReceiveChar (uses global variable)</li>\r
+       <li>ITM_CheckChar (uses global variable)</li>\r
+</ul>\r
+\r
+<h3>ITM_SendChar</h3>\r
+<p>\r
+  <strong>ITM_SendChar</strong> is used to transmit a character over ITM channel 0 from \r
+  the microcontroller system to the debug system. <br>\r
+  Only a 8 bit value is transmitted.\r
+</p>\r
+<pre>\r
+static __INLINE uint32_t ITM_SendChar (uint32_t ch)\r
+{\r
+  /* check if debugger connected and ITM channel enabled for tracing */\r
+  if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA)  &amp;&amp;\r
+      (ITM-&gt;TCR & ITM_TCR_ITMENA)                  &amp;&amp;\r
+      (ITM-&gt;TER & (1UL &lt;&lt; 0))  ) \r
+  {\r
+    while (ITM-&gt;PORT[0].u32 == 0);\r
+    ITM-&gt;PORT[0].u8 = (uint8_t)ch;\r
+  }  \r
+  return (ch);\r
+}</pre>\r
+\r
+<h3>ITM_ReceiveChar</h3>\r
+<p>\r
+  ITM communication channel is only capable for OUT direction. For IN direction\r
+  a globel variable is used. A simple mechansim detects if a character is received.\r
+  The project to test need to be build with debug information.\r
+</p>\r
+\r
+<p>\r
+  The globale variable <strong>ITM_RxBuffer</strong> is used to transmit a 8 bit value from debug system\r
+  to microcontroller system. <strong>ITM_RxBuffer</strong> is 32 bit wide to enshure a proper handshake.\r
+</p>\r
+<pre>\r
+extern volatile int ITM_RxBuffer;                    /* variable to receive characters                             */\r
+</pre>\r
+<p>\r
+  A dedicated bit pattern is used to determin if <strong>ITM_RxBuffer</strong> is empty\r
+  or contains a valid value.\r
+</p>\r
+<pre>\r
+#define             ITM_RXBUFFER_EMPTY    0x5AA55AA5 /* value identifying ITM_RxBuffer is ready for next character */\r
+</pre>\r
+<p>\r
+  <strong>ITM_ReceiveChar</strong> is used to receive a 8 bit value from the debug system. The function is nonblocking.\r
+  It returns the received character or '-1' if no character was available.\r
+</p>\r
+<pre>\r
+static __INLINE int ITM_ReceiveChar (void) {\r
+  int ch = -1;                               /* no character available */\r
+\r
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {\r
+    ch = ITM_RxBuffer;\r
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */\r
+  }\r
+  \r
+  return (ch); \r
+}\r
+</pre>\r
+\r
+<h3>ITM_CheckChar</h3>\r
+<p>\r
+  <strong>ITM_CheckChar</strong> is used to check if a character is received.\r
+</p>\r
+<pre>\r
+static __INLINE int ITM_CheckChar (void) {\r
+\r
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {\r
+    return (0);                                 /* no character available */\r
+  } else {\r
+    return (1);                                 /*    character available */\r
+  }\r
+}</pre>\r
+\r
+\r
+<h2>ITM Debug Support in uVision</h2>\r
+<p>\r
+  uVision uses in a debug session the <strong>Debug (printf) Viewer</strong> window to \r
+  display the debug data.\r
+</p>\r
+<p>Direction microcontroller system -&gt; uVision:</p>\r
+<ul>\r
+  <li>\r
+    Characters received via ITM communication channel 0 are written in a printf style\r
+    to <strong>Debug (printf) Viewer</strong> window.\r
+  </li>\r
+</ul>\r
+\r
+<p>Direction uVision -&gt; microcontroller system:</p>\r
+<ul>\r
+  <li>Check if <strong>ITM_RxBuffer</strong> variable is available (only performed once).</li>\r
+  <li>Read character from <strong>Debug (printf) Viewer</strong> window.</li>\r
+  <li>If <strong>ITM_RxBuffer</strong> empty write character to <strong>ITM_RxBuffer</strong>.</li>\r
+</ul>\r
+\r
+<p class="Note">Note</p>\r
+<ul>\r
+  <li><p>Current solution does not use a buffer machanism for trasmitting the characters.</p>\r
+  </li>\r
+</ul>\r
+\r
+<h2>RTX Kernel awareness in uVision</h2>\r
+<p>\r
+  uVision / RTX are using a simple and efficient solution for RTX Kernel awareness.\r
+  No format overhead is necessary.<br>\r
+  uVsion debugger decodes the RTX events via the 32 / 16 / 8 bit ITM write access\r
+  to ITM communication channel 31.\r
+</p>\r
+\r
+<p>Following RTX events are traced:</p>\r
+<ul>\r
+  <li>Task Create / Delete event\r
+    <ol>\r
+      <li>32 bit access. Task start address is transmitted</li>\r
+      <li>16 bit access. Task ID and Create/Delete flag are transmitted<br>\r
+          High byte holds Create/Delete flag, Low byte holds TASK ID.\r
+      </li>\r
+    </ol>\r
+  </li>\r
+  <li>Task switch event\r
+    <ol>\r
+      <li>8 bit access. Task ID of current task is transmitted</li>\r
+    </ol>\r
+  </li>\r
+</ul>\r
+\r
+<p class="Note">Note</p>\r
+<ul>\r
+  <li><p>Other RTOS information could be retrieved via memory read access in a polling mode manner.</p>\r
+  </li>\r
+</ul>\r
+\r
+\r
+<p class="MsoNormal"><span lang="EN-GB">&nbsp;</span></p>\r
+\r
+<hr>\r
+\r
+<p class="TinyT">Copyright © KEIL - An ARM Company.<br>\r
+All rights reserved.<br>\r
+Visit our web site at <a href="http://www.keil.com">www.keil.com</a>.\r
+</p>\r
+\r
+</body>\r
+\r
+</html>
\ No newline at end of file

diff --git a/Demo/CORTEX_STM32L152_IAR/system_and_ST_code/CMSIS/CMSIS_changes.htm b/Demo/CORTEX_STM32L152_IAR/system_and_ST_code/CMSIS/CMSIS_changes.htm
new file mode 100644 (file)
index 0000000..162ffcc
--- /dev/null
+++ b/Demo/CORTEX_STM32L152_IAR/system_and_ST_code/CMSIS/CMSIS_changes.htm
@@ -0,0 +1,320 @@
+<html>\r
+\r
+<head>\r
+<title>CMSIS Changes</title>\r
+<meta http-equiv="Content-Type" content="text/html; charset=windows-1252">\r
+<meta name="GENERATOR" content="Microsoft FrontPage 6.0">\r
+<meta name="ProgId" content="FrontPage.Editor.Document">\r
+<style>\r
+<!--\r
+/*-----------------------------------------------------------\r
+Keil Software CHM Style Sheet\r
+-----------------------------------------------------------*/\r
+body         { color: #000000; background-color: #FFFFFF; font-size: 75%; font-family: \r
+               Verdana, Arial, 'Sans Serif' }\r
+a:link       { color: #0000FF; text-decoration: underline }\r
+a:visited    { color: #0000FF; text-decoration: underline }\r
+a:active     { color: #FF0000; text-decoration: underline }\r
+a:hover      { color: #FF0000; text-decoration: underline }\r
+h1           { font-family: Verdana; font-size: 18pt; color: #000080; font-weight: bold; \r
+               text-align: Center; margin-right: 3 }\r
+h2           { font-family: Verdana; font-size: 14pt; color: #000080; font-weight: bold; \r
+               background-color: #CCCCCC; margin-top: 24; margin-bottom: 3; \r
+               padding: 6 }\r
+h3           { font-family: Verdana; font-size: 10pt; font-weight: bold; background-color: \r
+               #CCCCCC; margin-top: 24; margin-bottom: 3; padding: 6 }\r
+pre          { font-family: Courier New; font-size: 10pt; background-color: #CCFFCC; \r
+               margin-left: 24; margin-right: 24 }\r
+ul           { list-style-type: square; margin-top: 6pt; margin-bottom: 0 }\r
+ol           { margin-top: 6pt; margin-bottom: 0 }\r
+li           { clear: both; margin-bottom: 6pt }\r
+table        { font-size: 100%; border-width: 0; padding: 0 }\r
+th           { color: #FFFFFF; background-color: #000080; text-align: left; vertical-align: \r
+               bottom; padding-right: 6pt }\r
+tr           { text-align: left; vertical-align: top }\r
+td           { text-align: left; vertical-align: top; padding-right: 6pt }\r
+.ToolT       { font-size: 8pt; color: #808080 }\r
+.TinyT       { font-size: 8pt; text-align: Center }\r
+code         { color: #000000; background-color: #E0E0E0; font-family: 'Courier New', Courier; \r
+               line-height: 120%; font-style: normal }\r
+/*-----------------------------------------------------------\r
+Notes\r
+-----------------------------------------------------------*/\r
+p.note       { font-weight: bold; clear: both; margin-bottom: 3pt; padding-top: 6pt }\r
+/*-----------------------------------------------------------\r
+Expanding/Contracting Divisions\r
+-----------------------------------------------------------*/\r
+#expand      { text-decoration: none; margin-bottom: 3pt }\r
+img.expand   { border-style: none; border-width: medium }\r
+div.expand   { display: none; margin-left: 9pt; margin-top: 0 }\r
+/*-----------------------------------------------------------\r
+Where List Tags\r
+-----------------------------------------------------------*/\r
+p.wh         { font-weight: bold; clear: both; margin-top: 6pt; margin-bottom: 3pt }\r
+table.wh     { width: 100% }\r
+td.whItem    { white-space: nowrap; font-style: italic; padding-right: 6pt; padding-bottom: \r
+               6pt }\r
+td.whDesc    { padding-bottom: 6pt }\r
+/*-----------------------------------------------------------\r
+Keil Table Tags\r
+-----------------------------------------------------------*/\r
+table.kt     { border: 1pt solid #000000 }\r
+th.kt        { white-space: nowrap; border-bottom: 1pt solid #000000; padding-left: 6pt; \r
+               padding-right: 6pt; padding-top: 4pt; padding-bottom: 4pt }\r
+tr.kt        {  }\r
+td.kt        { color: #000000; background-color: #E0E0E0; border-top: 1pt solid #A0A0A0; \r
+               padding-left: 6pt; padding-right: 6pt; padding-top: 2pt; \r
+               padding-bottom: 2pt }\r
+/*-----------------------------------------------------------\r
+-----------------------------------------------------------*/\r
+-->\r
+\r
+</style>\r
+</head>\r
+\r
+<body>\r
+\r
+<h1>Changes to CMSIS version V1.20</h1>\r
+\r
+<hr>\r
+\r
+<h2>1. Removed CMSIS Middelware packages</h2>\r
+<p>\r
+  CMSIS Middleware is on hold from ARM side until a agreement between all CMSIS partners is found.\r
+</p>\r
+\r
+<h2>2. SystemFrequency renamed to SystemCoreClock</h2>\r
+<p>\r
+  The variable name <strong>SystemCoreClock</strong> is more precise than <strong>SystemFrequency</strong>\r
+  because the variable holds the clock value at which the core is running.\r
+</p>\r
+\r
+<h2>3. Changed startup concept</h2>\r
+<p>\r
+  The old startup concept (calling SystemInit_ExtMemCtl from startup file and calling SystemInit \r
+  from main) has the weakness that it does not work for controllers which need a already \r
+  configuerd clock system to configure the external memory controller.\r
+</p>\r
+\r
+<h3>Changed startup concept</h3>\r
+<ul>\r
+  <li>\r
+    SystemInit() is called from startup file before <strong>premain</strong>.\r
+  </li>\r
+  <li>\r
+    <strong>SystemInit()</strong> configures the clock system and also configures\r
+    an existing external memory controller.\r
+  </li>\r
+  <li>\r
+    <strong>SystemInit()</strong> must not use global variables.\r
+  </li>\r
+  <li>\r
+    <strong>SystemCoreClock</strong> is initialized with a correct predefined value.\r
+  </li>\r
+  <li>\r
+    Additional function <strong>void SystemCoreClockUpdate (void)</strong> is provided.<br>\r
+   <strong>SystemCoreClockUpdate()</strong> updates the variable <strong>SystemCoreClock</strong>\r
+   and must be called whenever the core clock is changed.<br>\r
+   <strong>SystemCoreClockUpdate()</strong> evaluates the clock register settings and calculates\r
+   the current core clock.\r
+  </li>\r
+</ul>\r
+      \r
+\r
+<h2>4. Advanced Debug Functions</h2>\r
+<p>\r
+  ITM communication channel is only capable for OUT direction. To allow also communication for\r
+  IN direction a simple concept is provided.\r
+</p>\r
+<ul>\r
+  <li>\r
+    Global variable <strong>volatile int ITM_RxBuffer</strong> used for IN data.\r
+  </li>\r
+  <li>\r
+    Function <strong>int ITM_CheckChar (void)</strong> checks if a new character is available.\r
+  </li>\r
+  <li>\r
+    Function <strong>int ITM_ReceiveChar (void)</strong> retrieves the new character.\r
+  </li>\r
+</ul>\r
+\r
+<p>\r
+  For detailed explanation see file <strong>CMSIS debug support.htm</strong>. \r
+</p>\r
+\r
+\r
+<h2>5. Core Register Bit Definitions</h2>\r
+<p>\r
+  Files core_cm3.h and core_cm0.h contain now bit definitions for Core Registers. The name for the\r
+  defines correspond with the Cortex-M Technical Reference Manual.  \r
+</p>\r
+<p>\r
+  e.g. SysTick structure with bit definitions\r
+</p>\r
+<pre>\r
+/** @addtogroup CMSIS_CM3_SysTick CMSIS CM3 SysTick\r
+  memory mapped structure for SysTick\r
+  @{\r
+ */\r
+typedef struct\r
+{\r
+  __IO uint32_t CTRL;                         /*!< Offset: 0x00  SysTick Control and Status Register */\r
+  __IO uint32_t LOAD;                         /*!< Offset: 0x04  SysTick Reload Value Register       */\r
+  __IO uint32_t VAL;                          /*!< Offset: 0x08  SysTick Current Value Register      */\r
+  __I  uint32_t CALIB;                        /*!< Offset: 0x0C  SysTick Calibration Register        */\r
+} SysTick_Type;\r
+\r
+/* SysTick Control / Status Register Definitions */\r
+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */\r
+#define SysTick_CTRL_COUNTFLAG_Msk         (1ul << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */\r
+\r
+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */\r
+#define SysTick_CTRL_CLKSOURCE_Msk         (1ul << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */\r
+\r
+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */\r
+#define SysTick_CTRL_TICKINT_Msk           (1ul << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */\r
+\r
+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */\r
+#define SysTick_CTRL_ENABLE_Msk            (1ul << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */\r
+\r
+/* SysTick Reload Register Definitions */\r
+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */\r
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFul << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */\r
+\r
+/* SysTick Current Register Definitions */\r
+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */\r
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFul << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */\r
+\r
+/* SysTick Calibration Register Definitions */\r
+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */\r
+#define SysTick_CALIB_NOREF_Msk            (1ul << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */\r
+\r
+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */\r
+#define SysTick_CALIB_SKEW_Msk             (1ul << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */\r
+\r
+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */\r
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFul << SysTick_VAL_CURRENT_Pos)        /*!< SysTick CALIB: TENMS Mask */\r
+/*@}*/ /* end of group CMSIS_CM3_SysTick */</pre>\r
+\r
+<h2>7. DoxyGen Tags</h2>\r
+<p>\r
+  DoxyGen tags in files core_cm3.[c,h] and core_cm0.[c,h] are reworked to create proper documentation\r
+  using DoxyGen.\r
+</p>\r
+\r
+<h2>8. Folder Structure</h2>\r
+<p>\r
+  The folder structure is changed to differentiate the single support packages.\r
+</p>\r
+\r
+  <ul>\r
+    <li>CM0</li>\r
+    <li>CM3\r
+       <ul>\r
+         <li>CoreSupport</li>\r
+         <li>DeviceSupport</li>\r
+           <ul>\r
+             <li>Vendor \r
+               <ul>\r
+                 <li>Device\r
+                   <ul>\r
+                      <li>Startup\r
+                        <ul>\r
+                          <li>Toolchain</li>\r
+                          <li>Toolchain</li>\r
+                          <li>...</li>\r
+                        </ul>\r
+                      </li>\r
+                   </ul>\r
+                 </li>\r
+                 <li>Device</li>\r
+                 <li>...</li>\r
+               </ul>\r
+             </li>\r
+             <li>Vendor</li>\r
+             <li>...</li>\r
+           </ul>\r
+         </li>\r
+         <li>Example\r
+           <ul>\r
+             <li>Toolchain \r
+               <ul>\r
+                 <li>Device</li>\r
+                 <li>Device</li>\r
+                 <li>...</li>\r
+               </ul>\r
+             </li>\r
+             <li>Toolchain</li>\r
+             <li>...</li>\r
+           </ul>\r
+         </li>\r
+       </ul>\r
+    </li>\r
+     \r
+    <li>Documentation</li>\r
+  </ul>\r
+\r
+<h2>9. Open Points</h2>\r
+<p>\r
+  Following points need to be clarified and solved:\r
+</p>\r
+<ul>\r
+  <li>\r
+    <p>\r
+      Equivalent C and Assembler startup files.\r
+    </p>\r
+    <p>\r
+      Is there a need for having C startup files although assembler startup files are\r
+      very efficient and do not need to be changed?\r
+    <p/>\r
+  </li>\r
+  <li>\r
+    <p>\r
+      Placing of HEAP in external RAM.\r
+    </p>\r
+    <p>\r
+      It must be possible to place HEAP in external RAM if the device supports an \r
+      external memory controller.\r
+    </p>\r
+  </li>\r
+  <li>\r
+    <p>\r
+      Placing of STACK /HEAP.\r
+    </p>\r
+    <p>\r
+      STACK should always be placed at the end of internal RAM.\r
+    </p>\r
+    <p>\r
+      If HEAP is placed in internal RAM than it should be placed after RW ZI section.\r
+    </p>\r
+  </li>\r
+  <li>\r
+    <p>\r
+      Removing core_cm3.c and core_cm0.c.\r
+    </p>\r
+    <p>\r
+      On a long term the functions in core_cm3.c and core_cm0.c must be replaced with \r
+      appropriate compiler intrinsics.\r
+    </p>\r
+  </li>\r
+</ul>\r
+\r
+\r
+<h2>10. Limitations</h2>\r
+<p>\r
+  The following limitations are not covered with the current CMSIS version:\r
+</p>\r
+<ul>\r
+ <li>\r
+  No <strong>C startup files</strong> for ARM toolchain are provided. \r
+ </li>\r
+ <li>\r
+  No <strong>C startup files</strong> for GNU toolchain are provided. \r
+ </li>\r
+ <li>\r
+  No <strong>C startup files</strong> for IAR toolchain are provided. \r
+ </li>\r
+ <li>\r
+  No <strong>Tasking</strong> projects are provided yet. \r
+ </li>\r
+</ul>\r

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+  \r
+  <title>CMSIS: Cortex Microcontroller Software Interface Standard</title><meta http-equiv="Content-Type" content="text/html; charset=windows-1252">\r
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+       background-color: #E0E0E0;\r
+}\r
+.O\r
+       {color:#1D315B;\r
+       font-size:149%;}\r
+    -->\r
+  </style></head>\r
+<body>\r
+<h1>Cortex Microcontroller Software Interface Standard</h1>\r
+\r
+<p align="center">This file describes the Cortex Microcontroller Software Interface Standard (CMSIS).</p>\r
+<p align="center">Version: 1.30 - 30. October 2009</p>\r
+\r
+<p class="TinyT">Information in this file, the accompany manuals, and software is<br>\r
+                 Copyright © ARM Ltd.<br>All rights reserved.\r
+</p>\r
+\r
+<hr>\r
+\r
+<p><span style="FONT-WEIGHT: bold">Revision History</span></p>\r
+<ul>\r
+       <li>Version 1.00: initial release. </li>\r
+       <li>Version 1.01: added __LDREX<em>x</em>, __STREX<em>x</em>, and __CLREX.</li>\r
+       <li>Version 1.02: added Cortex-M0. </li>\r
+       <li>Version 1.10: second review. </li>\r
+       <li>Version 1.20: third review. </li>\r
+       <li>Version 1.30 PRE-RELEASE: reworked Startup Concept, additional Debug Functionality.</li>\r
+       <li>Version 1.30 2nd PRE-RELEASE: changed folder structure, added doxyGen comments, added Bit definitions.</li>\r
+       <li>Version 1.30: updated Device Support Packages.</li>\r
+</ul>\r
+\r
+<hr>\r
+\r
+<h2>Contents</h2>\r
+\r
+<ol>\r
+  <li class="LI2"><a href="#1">About</a></li>\r
+  <li class="LI2"><a href="#2">Coding Rules and Conventions</a></li>\r
+  <li class="LI2"><a href="#3">CMSIS Files</a></li>\r
+  <li class="LI2"><a href="#4">Core Peripheral Access Layer</a></li>\r
+  <li class="LI2"><a href="#5">CMSIS Example</a></li>\r
+</ol>\r
+\r
+<h2><a name="1"></a>About</h2>\r
+\r
+<p>\r
+  The <strong>Cortex Microcontroller Software Interface Standard (CMSIS)</strong> answers the challenges\r
+  that are faced when software components are deployed to physical microcontroller devices based on a\r
+  Cortex-M0 or Cortex-M3 processor. The CMSIS will be also expanded to future Cortex-M \r
+  processor cores (the term Cortex-M is used to indicate that). The CMSIS is defined in close co-operation\r
+  with various silicon and software vendors and provides a common approach to interface to peripherals, \r
+  real-time operating systems, and middleware components.\r
+</p>\r
+\r
+<p>ARM provides as part of the CMSIS the following software layers that are\r
+available for various compiler implementations:</p>\r
+<ul>\r
+  <li><strong>Core Peripheral Access Layer</strong>: contains name definitions, \r
+    address definitions and helper functions to\r
+    access core registers and peripherals. It defines also a device\r
+    independent interface for RTOS Kernels that includes debug channel\r
+    definitions.</li>\r
+</ul>\r
+\r
+<p>These software layers are expanded by Silicon partners with:</p>\r
+<ul>\r
+  <li><strong>Device Peripheral Access Layer</strong>: provides definitions\r
+    for all device peripherals</li>\r
+  <li><strong>Access Functions for Peripherals (optional)</strong>: provides\r
+    additional helper functions for peripherals</li>\r
+</ul>\r
+\r
+<p>CMSIS defines for a Cortex-M Microcontroller System:</p>\r
+<ul>\r
+  <li style="text-align: left;">A common way to access peripheral registers\r
+    and a common way to define exception vectors.</li>\r
+  <li style="text-align: left;">The register names of the <strong>Core\r
+    Peripherals</strong> and<strong> </strong>the names of the <strong>Core\r
+    Exception Vectors</strong>.</li>\r
+  <li>An device independent interface for RTOS Kernels including a debug\r
+    channel.</li>\r
+</ul>\r
+\r
+<p>\r
+  By using CMSIS compliant software components, the user can easier re-use template code. \r
+  CMSIS is intended to enable the combination of software components from multiple middleware vendors.\r
+</p>\r
+\r
+<h2><a name="2"></a>Coding Rules and Conventions</h2>\r
+\r
+<p>\r
+  The following section describes the coding rules and conventions used in the CMSIS \r
+  implementation. It contains also information about data types and version number information.\r
+</p>\r
+\r
+<h3>Essentials</h3>\r
+<ul>\r
+  <li>The CMSIS C code conforms to MISRA 2004 rules. In case of MISRA violations, \r
+      there are disable and enable sequences for PC-LINT inserted.</li>\r
+  <li>ANSI standard data types defined in the ANSI C header file\r
+    <strong>&lt;stdint.h&gt;</strong> are used.</li>\r
+  <li>#define constants that include expressions must be enclosed by\r
+    parenthesis.</li>\r
+  <li>Variables and parameters have a complete data type.</li>\r
+  <li>All functions in the <strong>Core Peripheral Access Layer</strong> are\r
+    re-entrant.</li>\r
+  <li>The <strong>Core Peripheral Access Layer</strong> has no blocking code\r
+    (which means that wait/query loops are done at other software layers).</li>\r
+  <li>For each exception/interrupt there is definition for:\r
+  <ul>\r
+    <li>an exception/interrupt handler with the postfix <strong>_Handler </strong>\r
+       (for exceptions) or <strong>_IRQHandler</strong> (for interrupts).</li>\r
+    <li>a default exception/interrupt handler (weak definition) that contains an endless loop.</li>\r
+    <li>a #define of the interrupt number with the postfix <strong>_IRQn</strong>.</li>\r
+  </ul></li>\r
+</ul>\r
+\r
+<h3>Recommendations</h3>\r
+\r
+<p>The CMSIS recommends the following conventions for identifiers.</p>\r
+<ul>\r
+  <li><strong>CAPITAL</strong> names to identify Core Registers, Peripheral Registers, and CPU Instructions.</li>\r
+  <li><strong>CamelCase</strong> names to identify peripherals access functions and interrupts.</li>\r
+  <li><strong>PERIPHERAL_</strong> prefix to identify functions that belong to specify peripherals.</li>\r
+  <li><strong>Doxygen</strong> comments for all functions are included as described under <strong>Function Comments</strong> below.</li>\r
+</ul>\r
+\r
+<b>Comments</b>\r
+\r
+<ul>\r
+  <li>Comments use the ANSI C90 style (<em>/* comment */</em>) or C++ style \r
+  (<em>// comment</em>). It is assumed that the programming tools support today \r
+       consistently the C++ comment style.</li>\r
+  <li><strong>Function Comments</strong> provide for each function the following information:\r
+  <ul>\r
+    <li>one-line brief function overview.</li>\r
+    <li>detailed parameter explanation.</li>\r
+    <li>detailed information about return values.</li>\r
+    <li>detailed description of the actual function.</li>\r
+  </ul>\r
+  <p><b>Doxygen Example:</b></p>\r
+  <pre>\r
+/** \r
+ * @brief  Enable Interrupt in NVIC Interrupt Controller\r
+ * @param  IRQn  interrupt number that specifies the interrupt\r
+ * @return none.\r
+ * Enable the specified interrupt in the NVIC Interrupt Controller.\r
+ * Other settings of the interrupt such as priority are not affected.\r
+ */</pre>\r
+  </li>\r
+</ul>\r
+\r
+<h3>Data Types and IO Type Qualifiers</h3>\r
+\r
+<p>\r
+  The <strong>Cortex-M HAL</strong> uses the standard types from the standard ANSI C header file\r
+  <strong>&lt;stdint.h&gt;</strong>. <strong>IO Type Qualifiers</strong> are used to specify the access\r
+  to peripheral variables. IO Type Qualifiers are indented to be used for automatic generation of \r
+  debug information of peripheral registers.\r
+</p>\r
+\r
+<table class="kt" border="0" cellpadding="0" cellspacing="0">\r
+  <tbody>\r
+    <tr>\r
+      <th class="kt" nowrap="nowrap">IO Type Qualifier</th>\r
+      <th class="kt">#define</th>\r
+      <th class="kt">Description</th>\r
+    </tr>\r
+    <tr>\r
+      <td class="kt" nowrap="nowrap">__I</td>\r
+      <td class="kt">volatile const</td>\r
+      <td class="kt">Read access only</td>\r
+    </tr>\r
+    <tr>\r
+      <td class="kt" nowrap="nowrap">__O</td>\r
+      <td class="kt">volatile</td>\r
+      <td class="kt">Write access only</td>\r
+    </tr>\r
+    <tr>\r
+      <td class="kt" nowrap="nowrap">__IO</td>\r
+      <td class="kt">volatile</td>\r
+      <td class="kt">Read and write access</td>\r
+    </tr>\r
+  </tbody>\r
+</table>\r
+\r
+<h3>CMSIS Version Number</h3>\r
+<p>\r
+  File <strong>core_cm3.h</strong> contains the version number of the CMSIS with the following define:\r
+</p>\r
+\r
+<pre>\r
+#define __CM3_CMSIS_VERSION_MAIN  (0x01)      /* [31:16] main version       */\r
+#define __CM3_CMSIS_VERSION_SUB   (0x30)      /* [15:0]  sub version        */\r
+#define __CM3_CMSIS_VERSION       ((__CM3_CMSIS_VERSION_MAIN &lt;&lt; 16) | __CM3_CMSIS_VERSION_SUB)</pre>\r
+\r
+<p>\r
+  File <strong>core_cm0.h</strong> contains the version number of the CMSIS with the following define:\r
+</p>\r
+\r
+<pre>\r
+#define __CM0_CMSIS_VERSION_MAIN  (0x01)      /* [31:16] main version       */\r
+#define __CM0_CMSIS_VERSION_SUB   (0x30)      /* [15:0]  sub version        */\r
+#define __CM0_CMSIS_VERSION       ((__CM0_CMSIS_VERSION_MAIN &lt;&lt; 16) | __CM0_CMSIS_VERSION_SUB)</pre>\r
+\r
+\r
+<h3>CMSIS Cortex Core</h3>\r
+<p>\r
+  File <strong>core_cm3.h</strong> contains the type of the CMSIS Cortex-M with the following define:\r
+</p>\r
+\r
+<pre>\r
+#define __CORTEX_M                (0x03)</pre>\r
+\r
+<p>\r
+  File <strong>core_cm0.h</strong> contains the type of the CMSIS Cortex-M with the following define:\r
+</p>\r
+\r
+<pre>\r
+#define __CORTEX_M                (0x00)</pre>\r
+\r
+\r
+<h2><a name="3"></a>CMSIS Files</h2>\r
+<p>\r
+  This section describes the Files provided in context with the CMSIS to access the Cortex-M\r
+  hardware and peripherals.\r
+</p>\r
+\r
+<table class="kt" border="0" cellpadding="0" cellspacing="0">\r
+  <tbody>\r
+    <tr>\r
+      <th class="kt" nowrap="nowrap">File</th>\r
+      <th class="kt">Provider</th>\r
+      <th class="kt">Description</th>\r
+    </tr>\r
+    <tr>\r
+      <td class="kt" nowrap="nowrap"><i>device.h</i></td>\r
+      <td class="kt">Device specific (provided by silicon partner)</td>\r
+      <td class="kt">Defines the peripherals for the actual device. The file may use \r
+        several other include files to define the peripherals of the actual device.</td>\r
+    </tr>\r
+    <tr>\r
+      <td class="kt" nowrap="nowrap">core_cm0.h</td>\r
+      <td class="kt">ARM (for RealView ARMCC, IAR, and GNU GCC)</td>\r
+      <td class="kt">Defines the core peripherals for the Cortex-M0 CPU and core peripherals.</td>\r
+    </tr>\r
+    <tr>\r
+      <td class="kt" nowrap="nowrap">core_cm3.h</td>\r
+      <td class="kt">ARM (for RealView ARMCC, IAR, and GNU GCC)</td>\r
+      <td class="kt">Defines the core peripherals for the Cortex-M3 CPU and core peripherals.</td>\r
+    </tr>\r
+    <tr>\r
+      <td class="kt" nowrap="nowrap">core_cm0.c</td>\r
+      <td class="kt">ARM (for RealView ARMCC, IAR, and GNU GCC)</td>\r
+      <td class="kt">Provides helper functions that access core registers.</td>\r
+    </tr>\r
+    <tr>\r
+      <td class="kt" nowrap="nowrap">core_cm3.c</td>\r
+      <td class="kt">ARM (for RealView ARMCC, IAR, and GNU GCC)</td>\r
+      <td class="kt">Provides helper functions that access core registers.</td>\r
+    </tr>\r
+    <tr>\r
+      <td class="kt" nowrap="nowrap">startup<i>_device</i></td>\r
+      <td class="kt">ARM (adapted by compiler partner / silicon partner)</td>\r
+      <td class="kt">Provides the Cortex-M startup code and the complete (device specific) Interrupt Vector Table</td>\r
+    </tr>\r
+    <tr>\r
+      <td class="kt" nowrap="nowrap">system<i>_device</i></td>\r
+      <td class="kt">ARM (adapted by silicon partner)</td>\r
+      <td class="kt">Provides a device specific configuration file for the device. It configures the device initializes \r
+        typically the oscillator (PLL) that is part of the microcontroller device</td>\r
+    </tr>\r
+  </tbody>\r
+</table>\r
+\r
+<h3><em>device.h</em></h3>\r
+\r
+<p>\r
+  The file <em><strong>device.h</strong></em> is provided by the silicon vendor and is the \r
+  <u><strong>central include file</strong></u> that the application programmer is using in \r
+  the C source code. This file contains:\r
+</p>\r
+<ul>\r
+  <li>\r
+       <p><strong>Interrupt Number Definition</strong>: provides interrupt numbers \r
+       (IRQn) for all core and device specific exceptions and interrupts.</p>\r
+       </li>\r
+       <li>\r
+       <p><strong>Configuration for core_cm0.h / core_cm3.h</strong>: reflects the \r
+       actual configuration of the Cortex-M processor that is part of the actual \r
+       device. As such the file <strong>core_cm0.h / core_cm3.h</strong> is included that \r
+       implements access to processor registers and core peripherals. </p>\r
+       </li>\r
+       <li>\r
+       <p><strong>Device Peripheral Access Layer</strong>: provides definitions\r
+    for all device peripherals. It contains all data structures and the address \r
+       mapping for the device specific peripherals. </p>\r
+       </li>\r
+  <li><strong>Access Functions for Peripherals (optional)</strong>: provides\r
+    additional helper functions for peripherals that are useful for programming \r
+       of these peripherals. Access Functions may be provided as inline functions \r
+       or can be extern references to a device specific library provided by the \r
+       silicon vendor.</li>\r
+</ul>\r
+\r
+\r
+<h4><strong>Interrupt Number Definition</strong></h4>\r
+\r
+<p>To access the device specific interrupts the device.h file defines IRQn \r
+numbers for the complete device using a enum typedef as shown below:</p>\r
+<pre>\r
+typedef enum IRQn\r
+{\r
+/******  Cortex-M3 Processor Exceptions/Interrupt Numbers ************************************************/\r
+  NonMaskableInt_IRQn             = -14,      /*!&lt; 2 Non Maskable Interrupt                              */\r
+  HardFault_IRQn                  = -13,      /*!&lt; 3 Cortex-M3 Hard Fault Interrupt                      */\r
+  MemoryManagement_IRQn           = -12,      /*!&lt; 4 Cortex-M3 Memory Management Interrupt               */\r
+  BusFault_IRQn                   = -11,      /*!&lt; 5 Cortex-M3 Bus Fault Interrupt                       */\r
+  UsageFault_IRQn                 = -10,      /*!&lt; 6 Cortex-M3 Usage Fault Interrupt                     */\r
+  SVCall_IRQn                     = -5,       /*!&lt; 11 Cortex-M3 SV Call Interrupt                        */\r
+  DebugMonitor_IRQn               = -4,       /*!&lt; 12 Cortex-M3 Debug Monitor Interrupt                  */\r
+  PendSV_IRQn                     = -2,       /*!&lt; 14 Cortex-M3 Pend SV Interrupt                        */\r
+  SysTick_IRQn                    = -1,       /*!&lt; 15 Cortex-M3 System Tick Interrupt                    */\r
+/******  STM32 specific Interrupt Numbers ****************************************************************/\r
+  WWDG_STM_IRQn                   = 0,        /*!&lt; Window WatchDog Interrupt                             */\r
+  PVD_STM_IRQn                    = 1,        /*!&lt; PVD through EXTI Line detection Interrupt             */\r
+  :\r
+  :\r
+  } IRQn_Type;</pre>\r
+\r
+\r
+<h4>Configuration for core_cm0.h / core_cm3.h</h4>\r
+<p>\r
+  The Cortex-M core configuration options which are defined for each device implementation. Some \r
+  configuration options are reflected in the CMSIS layer using the #define settings described below.\r
+</p>\r
+<p>\r
+  To access core peripherals file <em><strong>device.h</strong></em> includes file <b>core_cm0.h / core_cm3.h</b>.\r
+  Several features in <strong>core_cm0.h / core_cm3.h</strong> are configured by the following defines that must be \r
+  defined before <strong>#include &lt;core_cm0.h&gt;</strong> / <strong>#include &lt;core_cm3.h&gt;</strong>\r
+  preprocessor command.\r
+</p>\r
+\r
+<table class="kt" border="0" cellpadding="0" cellspacing="0">\r
+  <tbody>\r
+    <tr>\r
+      <th class="kt" nowrap="nowrap">#define</th>\r
+      <th class="kt" nowrap="nowrap">File</th>\r
+      <th class="kt" nowrap="nowrap">Value</th>\r
+      <th class="kt">Description</th>\r
+    </tr>\r
+    <tr>\r
+      <td class="kt" nowrap="nowrap">__NVIC_PRIO_BITS</td>\r
+      <td class="kt">core_cm0.h</td>\r
+      <td class="kt" nowrap="nowrap">(2)</td>\r
+      <td class="kt">Number of priority bits implemented in the NVIC (device specific)</td>\r
+    </tr>\r
+    <tr>\r
+      <td class="kt" nowrap="nowrap">__NVIC_PRIO_BITS</td>\r
+      <td class="kt">core_cm3.h</td>\r
+      <td class="kt" nowrap="nowrap">(2 ... 8)</td>\r
+      <td class="kt">Number of priority bits implemented in the NVIC (device specific)</td>\r
+    </tr>\r
+    <tr>\r
+      <td class="kt" nowrap="nowrap">__MPU_PRESENT</td>\r
+      <td class="kt">core_cm0.h, core_cm3.h</td>\r
+      <td class="kt" nowrap="nowrap">(0, 1)</td>\r
+      <td class="kt">Defines if an MPU is present or not</td>\r
+    </tr>\r
+    <tr>\r
+      <td class="kt" nowrap="nowrap">__Vendor_SysTickConfig</td>\r
+      <td class="kt">core_cm0.h, core_cm3.h</td>\r
+      <td class="kt" nowrap="nowrap">(1)</td>\r
+      <td class="kt">When this define is setup to 1, the <strong>SysTickConfig</strong> function \r
+               in <strong>core_cm3.h</strong> is excluded. In this case the <em><strong>device.h</strong></em> \r
+               file must contain a vendor specific implementation of this function.</td>\r
+    </tr>\r
+  </tbody>\r
+</table>\r
+\r
+\r
+<h4>Device Peripheral Access Layer</h4>\r
+<p>\r
+  Each peripheral uses a prefix which consists of <strong>&lt;device abbreviation&gt;_</strong> \r
+  and <strong>&lt;peripheral name&gt;_</strong> to identify peripheral registers that access this \r
+  specific peripheral. The intention of this is to avoid name collisions caused\r
+  due to short names. If more than one peripheral of the same type exists, \r
+  identifiers have a postfix (digit or letter). For example:\r
+</p>\r
+<ul>\r
+       <li>&lt;device abbreviation&gt;_UART_Type: defines the generic register layout for all UART channels in a device.\r
+      <pre>\r
+typedef struct\r
+{\r
+  union {\r
+  __I  uint8_t  RBR;                     /*!< Offset: 0x000   Receiver Buffer Register    */\r
+  __O  uint8_t  THR;                     /*!< Offset: 0x000   Transmit Holding Register   */\r
+  __IO uint8_t  DLL;                     /*!< Offset: 0x000   Divisor Latch LSB           */\r
+       uint32_t RESERVED0;\r
+  };\r
+  union {\r
+  __IO uint8_t  DLM;                     /*!< Offset: 0x004   Divisor Latch MSB           */\r
+  __IO uint32_t IER;                     /*!< Offset: 0x004   Interrupt Enable Register   */\r
+  };\r
+  union {\r
+  __I  uint32_t IIR;                     /*!< Offset: 0x008   Interrupt ID Register       */\r
+  __O  uint8_t  FCR;                     /*!< Offset: 0x008   FIFO Control Register       */\r
+  };\r
+  __IO uint8_t  LCR;                     /*!< Offset: 0x00C   Line Control Register       */\r
+       uint8_t  RESERVED1[7];\r
+  __I  uint8_t  LSR;                     /*!< Offset: 0x014   Line Status Register        */\r
+       uint8_t  RESERVED2[7];\r
+  __IO uint8_t  SCR;                     /*!< Offset: 0x01C   Scratch Pad Register        */\r
+       uint8_t  RESERVED3[3];\r
+  __IO uint32_t ACR;                     /*!< Offset: 0x020   Autobaud Control Register   */\r
+  __IO uint8_t  ICR;                     /*!< Offset: 0x024   IrDA Control Register       */\r
+       uint8_t  RESERVED4[3];\r
+  __IO uint8_t  FDR;                     /*!< Offset: 0x028   Fractional Divider Register */\r
+       uint8_t  RESERVED5[7];\r
+  __IO uint8_t  TER;                     /*!< Offset: 0x030   Transmit Enable Register    */\r
+       uint8_t  RESERVED6[39];\r
+  __I  uint8_t  FIFOLVL;                 /*!< Offset: 0x058   FIFO Level Register         */\r
+} LPC_UART_TypeDef;</pre>\r
+  </li>\r
+       <li>&lt;device abbreviation&gt;_UART1: is a pointer to a register structure that refers to a specific UART. \r
+      For example UART1-&gt;DR is the data register of UART1.\r
+      <pre>\r
+#define LPC_UART2             ((LPC_UART_TypeDef      *) LPC_UART2_BASE    )\r
+#define LPC_UART3             ((LPC_UART_TypeDef      *) LPC_UART3_BASE    )</pre>\r
+  </li>\r
+</ul>\r
+\r
+<h5>Minimal Requiements</h5>\r
+<p>\r
+  To access the peripheral registers and related function in a device the files <strong><em>device.h</em></strong> \r
+  and <strong>core_cm0.h</strong> / <strong>core_cm3.h</strong> defines as a minimum:\r
+</p>\r
+<ul>\r
+  <li>The <strong>Register Layout Typedef</strong> for each peripheral that defines all register names.\r
+      Names that start with RESERVE are used to introduce space into the structure to adjust the addresses of\r
+      the peripheral registers. For example:\r
+      <pre>\r
+typedef struct {\r
+  __IO uint32_t CTRL;      /* SysTick Control and Status Register */\r
+  __IO uint32_t LOAD;      /* SysTick Reload Value Register       */\r
+  __IO uint32_t VAL;       /* SysTick Current Value Register      */\r
+  __I  uint32_t CALIB;     /* SysTick Calibration Register        */\r
+  } SysTick_Type;</pre>\r
+  </li>\r
+\r
+  <li>\r
+    <strong>Base Address</strong> for each peripheral (in case of multiple peripherals \r
+    that use the same <strong>register layout typedef</strong> multiple base addresses are defined). For example:\r
+    <pre>\r
+#define SysTick_BASE (SCS_BASE + 0x0010)            /* SysTick Base Address */</pre>\r
+  </li>\r
+\r
+  <li>\r
+    <strong>Access Definition</strong> for each peripheral (in case of multiple peripherals that use \r
+    the same <strong>register layout typedef</strong> multiple access definitions exist, i.e. LPC_UART0, \r
+    LPC_UART2). For Example:\r
+    <pre>\r
+#define SysTick ((SysTick_Type *) SysTick_BASE)     /* SysTick access definition */</pre>\r
+  </li>\r
+</ul>\r
+\r
+<p>\r
+  These definitions allow to access the peripheral registers from user code with simple assignments like:\r
+</p>\r
+<pre>SysTick-&gt;CTRL = 0;</pre>\r
+\r
+<h5>Optional Features</h5>\r
+<p>In addition the <em> <strong>device.h </strong></em>file may define:</p>\r
+<ul>\r
+       <li>\r
+    #define constants that simplify access to the peripheral registers. \r
+         These constant define bit-positions or other specific patterns are that required for the \r
+    programming of the peripheral registers. The identifiers used start with \r
+    <strong>&lt;device abbreviation&gt;_</strong> and <strong>&lt;peripheral name&gt;_</strong>. \r
+    It is recommended to use CAPITAL letters for such #define constants.\r
+  </li>\r
+       <li>\r
+    Functions that perform more complex functions with the peripheral (i.e. status query before \r
+    a sending register is accessed). Again these function start with \r
+    <strong>&lt;device abbreviation&gt;_</strong> and <strong>&lt;peripheral name&gt;_</strong>. \r
+  </li>\r
+</ul>\r
+\r
+<h3>core_cm0.h and core_cm0.c</h3>\r
+<p>\r
+  File <b>core_cm0.h</b> describes the data structures for the Cortex-M0 core peripherals and does \r
+  the address mapping of this structures. It also provides basic access to the Cortex-M0 core registers \r
+  and core peripherals with efficient functions (defined as <strong>static inline</strong>).\r
+</p>\r
+<p>\r
+  File <b>core_cm0.c</b> defines several helper functions that access processor registers.\r
+</p>\r
+<p>Together these files implement the <a href="#4">Core Peripheral Access Layer</a> for a Cortex-M0.</p>\r
+\r
+<h3>core_cm3.h and core_cm3.c</h3>\r
+<p>\r
+  File <b>core_cm3.h</b> describes the data structures for the Cortex-M3 core peripherals and does \r
+  the address mapping of this structures. It also provides basic access to the Cortex-M3 core registers \r
+  and core peripherals with efficient functions (defined as <strong>static inline</strong>).\r
+</p>\r
+<p>\r
+  File <b>core_cm3.c</b> defines several helper functions that access processor registers.\r
+</p>\r
+<p>Together these files implement the <a href="#4">Core Peripheral Access Layer</a> for a Cortex-M3.</p>\r
+\r
+<h3>startup_<em>device</em></h3>\r
+<p>\r
+  A template file for <strong>startup_<em>device</em></strong> is provided by ARM for each supported\r
+  compiler. It is adapted by the silicon vendor to include interrupt vectors for all device specific \r
+  interrupt handlers. Each interrupt handler is defined as <strong><em>weak</em></strong> function \r
+  to an dummy handler. Therefore the interrupt handler can be directly used in application software \r
+  without any requirements to adapt the <strong>startup_<em>device</em></strong> file.\r
+</p>\r
+<p>\r
+  The following exception names are fixed and define the start of the vector table for a Cortex-M0:\r
+</p>\r
+<pre>\r
+__Vectors       DCD     __initial_sp              ; Top of Stack\r
+                DCD     Reset_Handler             ; Reset Handler\r
+                DCD     NMI_Handler               ; NMI Handler\r
+                DCD     HardFault_Handler         ; Hard Fault Handler\r
+                DCD     0                         ; Reserved\r
+                DCD     0                         ; Reserved\r
+                DCD     0                         ; Reserved\r
+                DCD     0                         ; Reserved\r
+                DCD     0                         ; Reserved\r
+                DCD     0                         ; Reserved\r
+                DCD     0                         ; Reserved\r
+                DCD     SVC_Handler               ; SVCall Handler\r
+                DCD     0                         ; Reserved\r
+                DCD     0                         ; Reserved\r
+                DCD     PendSV_Handler            ; PendSV Handler\r
+                DCD     SysTick_Handler           ; SysTick Handler</pre>\r
+\r
+<p>\r
+  The following exception names are fixed and define the start of the vector table for a Cortex-M3:\r
+</p>\r
+<pre>\r
+__Vectors       DCD     __initial_sp              ; Top of Stack\r
+                DCD     Reset_Handler             ; Reset Handler\r
+                DCD     NMI_Handler               ; NMI Handler\r
+                DCD     HardFault_Handler         ; Hard Fault Handler\r
+                DCD     MemManage_Handler         ; MPU Fault Handler\r
+                DCD     BusFault_Handler          ; Bus Fault Handler\r
+                DCD     UsageFault_Handler        ; Usage Fault Handler\r
+                DCD     0                         ; Reserved\r
+                DCD     0                         ; Reserved\r
+                DCD     0                         ; Reserved\r
+                DCD     0                         ; Reserved\r
+                DCD     SVC_Handler               ; SVCall Handler\r
+                DCD     DebugMon_Handler          ; Debug Monitor Handler\r
+                DCD     0                         ; Reserved\r
+                DCD     PendSV_Handler            ; PendSV Handler\r
+                DCD     SysTick_Handler           ; SysTick Handler</pre>\r
+\r
+<p>\r
+  In the following examples for device specific interrupts are shown:\r
+</p>\r
+<pre>\r
+; External Interrupts\r
+                DCD     WWDG_IRQHandler           ; Window Watchdog\r
+                DCD     PVD_IRQHandler            ; PVD through EXTI Line detect\r
+                DCD     TAMPER_IRQHandler         ; Tamper</pre>\r
+\r
+<p>\r
+  Device specific interrupts must have a dummy function that can be overwritten in user code. \r
+  Below is an example for this dummy function.\r
+</p>\r
+<pre>\r
+Default_Handler PROC\r
+                EXPORT WWDG_IRQHandler   [WEAK]\r
+                EXPORT PVD_IRQHandler    [WEAK]\r
+                EXPORT TAMPER_IRQHandler [WEAK]\r
+                :\r
+                :\r
+                WWDG_IRQHandler\r
+                PVD_IRQHandler\r
+                TAMPER_IRQHandler\r
+                :\r
+                :\r
+                B .\r
+                ENDP</pre>\r
+                \r
+<p>\r
+  The user application may simply define an interrupt handler function by using the handler name\r
+  as shown below.\r
+</p>\r
+<pre>\r
+void WWDG_IRQHandler(void)\r
+{\r
+  :\r
+  :\r
+}</pre>\r
+\r
+\r
+<h3><a name="4"></a>system_<em>device</em>.c</h3>\r
+<p>\r
+  A template file for <strong>system_<em>device</em>.c</strong> is provided by ARM but adapted by \r
+  the silicon vendor to match their actual device. As a <strong>minimum requirement</strong> \r
+  this file must provide a device specific system configuration function and a global variable \r
+  that contains the system frequency. It configures the device and initializes typically the \r
+  oscillator (PLL) that is part of the microcontroller device.\r
+</p>\r
+<p>\r
+  The file <strong>system_</strong><em><strong>device</strong></em><strong>.c</strong> must provide\r
+  as a minimum requirement the SystemInit function as shown below.\r
+</p>\r
+\r
+<table class="kt" border="0" cellpadding="0" cellspacing="0">\r
+  <tbody>\r
+    <tr>\r
+      <th class="kt">Function Definition</th>\r
+      <th class="kt">Description</th>\r
+    </tr>\r
+    <tr>\r
+      <td class="kt" nowrap="nowrap">void SystemInit (void)</td>\r
+      <td class="kt">Setup the microcontroller system. Typically this function configures the \r
+                     oscillator (PLL) that is part of the microcontroller device. For systems \r
+                     with variable clock speed it also updates the variable SystemCoreClock.<br>\r
+                     SystemInit is called from startup<i>_device</i> file.</td>\r
+    </tr>\r
+    <tr>\r
+      <td class="kt" nowrap="nowrap">void SystemCoreClockUpdate (void)</td>\r
+      <td class="kt">Updates the variable SystemCoreClock and must be called whenever the \r
+                     core clock is changed during program execution. SystemCoreClockUpdate()\r
+                     evaluates the clock register settings and calculates the current core clock.\r
+</td>\r
+    </tr>\r
+  </tbody>\r
+</table>\r
+\r
+<p>\r
+  Also part of the file <strong>system_</strong><em><strong>device</strong></em><strong>.c</strong> \r
+  is the variable <strong>SystemCoreClock</strong> which contains the current CPU clock speed shown below.\r
+</p>\r
+\r
+<table class="kt" border="0" cellpadding="0" cellspacing="0">\r
+  <tbody>\r
+    <tr>\r
+      <th class="kt">Variable Definition</th>\r
+      <th class="kt">Description</th>\r
+    </tr>\r
+    <tr>\r
+      <td class="kt" nowrap="nowrap">uint32_t SystemCoreClock</td>\r
+      <td class="kt">Contains the system core clock (which is the system clock frequency supplied \r
+                     to the SysTick timer and the processor core clock). This variable can be \r
+                     used by the user application to setup the SysTick timer or configure other \r
+                     parameters. It may also be used by debugger to query the frequency of the \r
+                     debug timer or configure the trace clock speed.<br>\r
+                     SystemCoreClock is initialized with a correct predefined value.<br><br>\r
+                                The compiler must be configured to avoid the removal of this variable in \r
+                                case that the application program is not using it. It is important for \r
+                                debug systems that the variable is physically present in memory so that \r
+                                it can be examined to configure the debugger.</td>\r
+    </tr>\r
+  </tbody>\r
+</table>\r
+\r
+<p class="Note">Note</p>\r
+<ul>\r
+  <li><p>The above definitions are the minimum requirements for the file <strong>\r
+       system_</strong><em><strong>device</strong></em><strong>.c</strong>. This \r
+       file may export more functions or variables that provide a more flexible \r
+       configuration of the microcontroller system.</p>\r
+  </li>\r
+</ul>\r
+\r
+\r
+<h2>Core Peripheral Access Layer</h2>\r
+\r
+<h3>Cortex-M Core Register Access</h3>\r
+<p>\r
+  The following functions are defined in <strong>core_cm0.h</strong> / <strong>core_cm3.h</strong>\r
+  and provide access to Cortex-M core registers.\r
+</p>\r
+\r
+<table class="kt" border="0" cellpadding="0" cellspacing="0">\r
+  <tbody>\r
+    <tr>\r
+      <th class="kt">Function Definition</th>\r
+      <th class="kt">Core</th>\r
+      <th class="kt">Core Register</th>\r
+      <th class="kt">Description</th>\r
+    </tr>\r
+    <tr>\r
+      <td class="kt" nowrap="nowrap">void __enable_irq (void)</td>\r
+      <td class="kt">M0, M3</td>\r
+      <td class="kt">PRIMASK = 0</td>\r
+      <td class="kt">Global Interrupt enable (using the instruction <strong>CPSIE \r
+               i</strong>)</td>\r
+    </tr>\r
+    <tr>\r
+      <td class="kt" nowrap="nowrap">void __disable_irq (void)</td>\r
+      <td class="kt">M0, M3</td>\r
+      <td class="kt">PRIMASK = 1</td>\r
+      <td class="kt">Global Interrupt disable (using the instruction <strong>\r
+               CPSID i</strong>)</td>\r
+    </tr>\r
+    <tr>\r
+      <td class="kt" nowrap="nowrap">void __set_PRIMASK (uint32_t value)</td>\r
+      <td class="kt">M0, M3</td>\r
+      <td class="kt">PRIMASK = value</td>\r
+      <td class="kt">Assign value to Priority Mask Register (using the instruction \r
+               <strong>MSR</strong>)</td>\r
+    </tr>\r
+    <tr>\r
+      <td class="kt" nowrap="nowrap">uint32_t __get_PRIMASK (void)</td>\r
+      <td class="kt">M0, M3</td>\r
+      <td class="kt">return PRIMASK</td>\r
+      <td class="kt">Return Priority Mask Register (using the instruction \r
+               <strong>MRS</strong>)</td>\r
+    </tr>\r
+    <tr>\r
+      <td class="kt" nowrap="nowrap">void __enable_fault_irq (void)</td>\r
+      <td class="kt">M3</td>\r
+      <td class="kt">FAULTMASK = 0</td>\r
+      <td class="kt">Global Fault exception and Interrupt enable (using the \r
+               instruction <strong>CPSIE \r
+               f</strong>)</td>\r
+    </tr>\r
+    <tr>\r
+      <td class="kt" nowrap="nowrap">void __disable_fault_irq (void)</td>\r
+      <td class="kt">M3</td>\r
+      <td class="kt">FAULTMASK = 1</td>\r
+      <td class="kt">Global Fault exception and Interrupt disable (using the \r
+               instruction <strong>CPSID f</strong>)</td>\r
+    </tr>\r
+    <tr>\r
+      <td class="kt" nowrap="nowrap">void __set_FAULTMASK (uint32_t value)</td>\r
+      <td class="kt">M3</td>\r
+      <td class="kt">FAULTMASK = value</td>\r
+      <td class="kt">Assign value to Fault Mask Register (using the instruction \r
+               <strong>MSR</strong>)</td>\r
+    </tr>\r
+    <tr>\r
+      <td class="kt" nowrap="nowrap">uint32_t __get_FAULTMASK (void)</td>\r
+      <td class="kt">M3</td>\r
+      <td class="kt">return FAULTMASK</td>\r
+      <td class="kt">Return Fault Mask Register (using the instruction <strong>MRS</strong>)</td>\r
+    </tr>\r
+    <tr>\r
+      <td class="kt" nowrap="nowrap">void __set_BASEPRI (uint32_t value)</td>\r
+      <td class="kt">M3</td>\r
+      <td class="kt">BASEPRI = value</td>\r
+      <td class="kt">Set Base Priority (using the instruction <strong>MSR</strong>)</td>\r
+    </tr>\r
+    <tr>\r
+      <td class="kt" nowrap="nowrap">uiuint32_t __get_BASEPRI (void)</td>\r
+      <td class="kt">M3</td>\r
+      <td class="kt">return BASEPRI</td>\r
+      <td class="kt">Return Base Priority (using the instruction <strong>MRS</strong>)</td>\r
+    </tr>\r
+    <tr>\r
+      <td class="kt" nowrap="nowrap">void __set_CONTROL (uint32_t value)</td>\r
+      <td class="kt">M0, M3</td>\r
+      <td class="kt">CONTROL = value</td>\r
+      <td class="kt">Set CONTROL register value (using the instruction <strong>MSR</strong>)</td>\r
+    </tr>\r
+    <tr>\r
+      <td class="kt" nowrap="nowrap">uint32_t __get_CONTROL (void)</td>\r
+      <td class="kt">M0, M3</td>\r
+      <td class="kt">return CONTROL</td>\r
+      <td class="kt">Return Control Register Value (using the instruction\r
+               <strong>MRS</strong>)</td>\r
+    </tr>\r
+    <tr>\r
+      <td class="kt" nowrap="nowrap">void __set_PSP (uint32_t TopOfProcStack)</td>\r
+      <td class="kt">M0, M3</td>\r
+      <td class="kt">PSP = TopOfProcStack</td>\r
+      <td class="kt">Set Process Stack Pointer value (using the instruction\r
+               <strong>MSR</strong>)</td>\r
+    </tr>\r
+    <tr>\r
+      <td class="kt" nowrap="nowrap">uint32_t __get_PSP (void)</td>\r
+      <td class="kt">M0, M3</td>\r
+      <td class="kt">return PSP</td>\r
+      <td class="kt">Return Process Stack Pointer (using the instruction <strong>MRS</strong>)</td>\r
+    </tr>\r
+    <tr>\r
+      <td class="kt" nowrap="nowrap">void __set_MSP (uint32_t TopOfMainStack)</td>\r
+      <td class="kt">M0, M3</td>\r
+      <td class="kt">MSP = TopOfMainStack</td>\r
+      <td class="kt">Set Main Stack Pointer (using the instruction <strong>MSR</strong>)</td>\r
+    </tr>\r
+    <tr>\r
+      <td class="kt" nowrap="nowrap">uint32_t __get_MSP (void)</td>\r
+      <td class="kt">M0, M3</td>\r
+      <td class="kt">return MSP</td>\r
+      <td class="kt">Return Main Stack Pointer (using the instruction <strong>MRS</strong>)</td>\r
+    </tr>\r
+  </tbody>\r
+</table>\r
+\r
+<h3>Cortex-M Instruction Access</h3>\r
+<p>\r
+  The following functions are defined in <strong>core_cm0.h</strong> / <strong>core_cm3.h</strong>and\r
+  generate specific Cortex-M instructions. The functions are implemented in the file \r
+  <strong>core_cm0.c</strong> / <strong>core_cm3.c</strong>.\r
+</p>\r
+\r
+<table class="kt" border="0" cellpadding="0" cellspacing="0">\r
+  <tbody>\r
+    <tr>\r
+      <th class="kt">Name</th>\r
+      <th class="kt">Core</th>\r
+      <th class="kt">Generated CPU Instruction</th>\r
+      <th class="kt">Description</th>\r
+    </tr>\r
+    <tr>\r
+      <td class="kt" nowrap="nowrap">void __NOP (void)</td>\r
+      <td class="kt">M0, M3</td>\r
+      <td class="kt">NOP</td>\r
+      <td class="kt">No Operation</td>\r
+    </tr>\r
+    <tr>\r
+      <td class="kt" nowrap="nowrap">void __WFI (void)</td>\r
+      <td class="kt">M0, M3</td>\r
+      <td class="kt">WFI</td>\r
+      <td class="kt">Wait for Interrupt</td>\r
+    </tr>\r
+    <tr>\r
+      <td class="kt" nowrap="nowrap">void __WFE (void)</td>\r
+      <td class="kt">M0, M3</td>\r
+      <td class="kt">WFE</td>\r
+      <td class="kt">Wait for Event</td>\r
+    </tr>\r
+    <tr>\r
+      <td class="kt" nowrap="nowrap">void __SEV (void)</td>\r
+      <td class="kt">M0, M3</td>\r
+      <td class="kt">SEV</td>\r
+      <td class="kt">Set Event</td>\r
+    </tr>\r
+    <tr>\r
+      <td class="kt" nowrap="nowrap">void __ISB (void)</td>\r
+      <td class="kt">M0, M3</td>\r
+      <td class="kt">ISB</td>\r
+      <td class="kt">Instruction Synchronization Barrier</td>\r
+    </tr>\r
+    <tr>\r
+      <td class="kt" nowrap="nowrap">void __DSB (void)</td>\r
+      <td class="kt">M0, M3</td>\r
+      <td class="kt">DSB</td>\r
+      <td class="kt">Data Synchronization Barrier</td>\r
+    </tr>\r
+    <tr>\r
+      <td class="kt" nowrap="nowrap">void __DMB (void)</td>\r
+      <td class="kt">M0, M3</td>\r
+      <td class="kt">DMB</td>\r
+      <td class="kt">Data Memory Barrier</td>\r
+    </tr>\r
+    <tr>\r
+      <td class="kt" nowrap="nowrap">uint32_t __REV (uint32_t value)</td>\r
+      <td class="kt">M0, M3</td>\r
+      <td class="kt">REV</td>\r
+      <td class="kt">Reverse byte order in integer value.</td>\r
+    </tr>\r
+    <tr>\r
+      <td class="kt" nowrap="nowrap">uint32_t __REV16 (uint16_t value)</td>\r
+      <td class="kt">M0, M3</td>\r
+      <td class="kt">REV16</td>\r
+      <td class="kt">Reverse byte order in unsigned short value. </td>\r
+    </tr>\r
+    <tr>\r
+      <td class="kt" nowrap="nowrap">sint32_t __REVSH (sint16_t value)</td>\r
+      <td class="kt">M0, M3</td>\r
+      <td class="kt">REVSH</td>\r
+      <td class="kt">Reverse byte order in signed short value with sign extension to integer.</td>\r
+    </tr>\r
+    <tr>\r
+      <td class="kt" nowrap="nowrap">uint32_t __RBIT (uint32_t value)</td>\r
+      <td class="kt">M3</td>\r
+      <td class="kt">RBIT</td>\r
+      <td class="kt">Reverse bit order of value</td>\r
+    </tr>\r
+    <tr>\r
+      <td class="kt" nowrap="nowrap">uint8_t __LDREXB (uint8_t *addr)</td>\r
+      <td class="kt">M3</td>\r
+      <td class="kt">LDREXB</td>\r
+      <td class="kt">Load exclusive byte</td>\r
+    </tr>\r
+    <tr>\r
+      <td class="kt" nowrap="nowrap">uint16_t __LDREXH (uint16_t *addr)</td>\r
+      <td class="kt">M3</td>\r
+      <td class="kt">LDREXH</td>\r
+      <td class="kt">Load exclusive half-word</td>\r
+    </tr>\r
+    <tr>\r
+      <td class="kt" nowrap="nowrap">uint32_t __LDREXW (uint32_t *addr)</td>\r
+      <td class="kt">M3</td>\r
+      <td class="kt">LDREXW</td>\r
+      <td class="kt">Load exclusive word</td>\r
+    </tr>\r
+    <tr>\r
+      <td class="kt" nowrap="nowrap">uint32_t __STREXB (uint8_t value, uint8_t *addr)</td>\r
+      <td class="kt">M3</td>\r
+      <td class="kt">STREXB</td>\r
+      <td class="kt">Store exclusive byte</td>\r
+    </tr>\r
+    <tr>\r
+      <td class="kt" nowrap="nowrap">uint32_t __STREXB (uint16_t value, uint16_t *addr)</td>\r
+      <td class="kt">M3</td>\r
+      <td class="kt">STREXH</td>\r
+      <td class="kt">Store exclusive half-word</td>\r
+    </tr>\r
+    <tr>\r
+      <td class="kt" nowrap="nowrap">uint32_t __STREXB (uint32_t value, uint32_t *addr)</td>\r
+      <td class="kt">M3</td>\r
+      <td class="kt">STREXW</td>\r
+      <td class="kt">Store exclusive word</td>\r
+    </tr>\r
+    <tr>\r
+      <td class="kt" nowrap="nowrap">void  __CLREX (void)</td>\r
+      <td class="kt">M3</td>\r
+      <td class="kt">CLREX</td>\r
+      <td class="kt">Remove the exclusive lock created by __LDREXB, __LDREXH, or __LDREXW</td>\r
+    </tr>\r
+  </tbody>\r
+</table>\r
+\r
+\r
+<h3>NVIC Access Functions</h3>\r
+<p>\r
+  The CMSIS provides access to the NVIC via the register interface structure and several helper\r
+  functions that simplify the setup of the NVIC. The CMSIS HAL uses IRQ numbers (IRQn) to \r
+  identify the interrupts. The first device interrupt has the IRQn value 0. Therefore negative \r
+  IRQn values are used for processor core exceptions.\r
+</p>\r
+<p>\r
+  For the IRQn values of core exceptions the file <strong><em>device.h</em></strong> provides \r
+  the following enum names.\r
+</p>\r
+\r
+<table class="kt" border="0" cellpadding="0" cellspacing="0">\r
+  <tbody>\r
+    <tr>\r
+      <th class="kt" nowrap="nowrap">Core Exception enum Value</th>\r
+      <th class="kt">Core</th>\r
+      <th class="kt">IRQn</th>\r
+      <th class="kt">Description</th>\r
+    </tr>\r
+    <tr>\r
+      <td class="kt" nowrap="nowrap">NonMaskableInt_IRQn</td>\r
+      <td class="kt">M0, M3</td>\r
+      <td class="kt">-14</td>\r
+      <td class="kt">Cortex-M Non Maskable Interrupt</td>\r
+    </tr>\r
+    <tr>\r
+      <td class="kt" nowrap="nowrap">HardFault_IRQn</td>\r
+      <td class="kt">M0, M3</td>\r
+      <td class="kt">-13</td>\r
+      <td class="kt">Cortex-M Hard Fault Interrupt</td>\r
+    </tr>\r
+    <tr>\r
+      <td class="kt" nowrap="nowrap">MemoryManagement_IRQn</td>\r
+      <td class="kt">M3</td>\r
+      <td class="kt">-12</td>\r
+      <td class="kt">Cortex-M Memory Management Interrupt</td>\r
+    </tr>\r
+    <tr>\r
+      <td class="kt" nowrap="nowrap">BusFault_IRQn</td>\r
+      <td class="kt">M3</td>\r
+      <td class="kt">-11</td>\r
+      <td class="kt">Cortex-M Bus Fault Interrupt</td>\r
+    </tr>\r
+    <tr>\r
+      <td class="kt" nowrap="nowrap">UsageFault_IRQn</td>\r
+      <td class="kt">M3</td>\r
+      <td class="kt">-10</td>\r
+      <td class="kt">Cortex-M Usage Fault Interrupt</td>\r
+    </tr>\r
+    <tr>\r
+      <td class="kt" nowrap="nowrap">SVCall_IRQn</td>\r
+      <td class="kt">M0, M3</td>\r
+      <td class="kt">-5</td>\r
+      <td class="kt">Cortex-M SV Call Interrupt </td>\r
+    </tr>\r
+    <tr>\r
+      <td class="kt" nowrap="nowrap">DebugMonitor_IRQn</td>\r
+      <td class="kt">M3</td>\r
+      <td class="kt">-4</td>\r
+      <td class="kt">Cortex-M Debug Monitor Interrupt</td>\r
+    </tr>\r
+    <tr>\r
+      <td class="kt" nowrap="nowrap">PendSV_IRQn</td>\r
+      <td class="kt">M0, M3</td>\r
+      <td class="kt">-2</td>\r
+      <td class="kt">Cortex-M Pend SV Interrupt</td>\r
+    </tr>\r
+    <tr>\r
+      <td class="kt" nowrap="nowrap">SysTick_IRQn</td>\r
+      <td class="kt">M0, M3</td>\r
+      <td class="kt">-1</td>\r
+      <td class="kt">Cortex-M System Tick Interrupt</td>\r
+    </tr>\r
+  </tbody>\r
+</table>\r
+\r
+<p>The following functions simplify the setup of the NVIC.\r
+The functions are defined as <strong>static inline</strong>.</p>\r
+\r
+<table class="kt" border="0" cellpadding="0" cellspacing="0">\r
+  <tbody>\r
+    <tr>\r
+      <th class="kt" nowrap="nowrap">Name</th>\r
+      <th class="kt">Core</th>\r
+      <th class="kt">Parameter</th>\r
+      <th class="kt">Description</th>\r
+    </tr>\r
+    <tr>\r
+      <td class="kt" nowrap="nowrap">void NVIC_SetPriorityGrouping (uint32_t PriorityGroup)</td>\r
+      <td class="kt">M3</td>\r
+      <td class="kt">Priority Grouping Value</td>\r
+      <td class="kt">Set the Priority Grouping (Groups . Subgroups)</td>\r
+    </tr>\r
+    <tr>\r
+      <td class="kt" nowrap="nowrap">uint32_t NVIC_GetPriorityGrouping (void)</td>\r
+      <td class="kt">M3</td>\r
+      <td class="kt">(void)</td>\r
+      <td class="kt">Get the Priority Grouping (Groups . Subgroups)</td>\r
+    </tr>\r
+    <tr>\r
+      <td class="kt" nowrap="nowrap">void NVIC_EnableIRQ (IRQn_Type IRQn)</td>\r
+      <td class="kt">M0, M3</td>\r
+      <td class="kt">IRQ Number</td>\r
+      <td class="kt">Enable IRQn</td>\r
+    </tr>\r
+    <tr>\r
+      <td class="kt" nowrap="nowrap">void NVIC_DisableIRQ (IRQn_Type IRQn)</td>\r
+      <td class="kt">M0, M3</td>\r
+      <td class="kt">IRQ Number</td>\r
+      <td class="kt">Disable IRQn</td>\r
+    </tr>\r
+    <tr>\r
+      <td class="kt" nowrap="nowrap">uint32_t NVIC_GetPendingIRQ (IRQn_Type IRQn)</td>\r
+      <td class="kt">M0, M3</td>\r
+      <td class="kt">IRQ Number</td>\r
+      <td class="kt">Return 1 if IRQn is pending else 0</td>\r
+    </tr>\r
+    <tr>\r
+      <td class="kt" nowrap="nowrap">void NVIC_SetPendingIRQ (IRQn_Type IRQn)</td>\r
+      <td class="kt">M0, M3</td>\r
+      <td class="kt">IRQ Number</td>\r
+      <td class="kt">Set IRQn Pending</td>\r
+    </tr>\r
+    <tr>\r
+      <td class="kt" nowrap="nowrap">void NVIC_ClearPendingIRQ (IRQn_Type IRQn)</td>\r
+      <td class="kt">M0, M3</td>\r
+      <td class="kt">IRQ Number</td>\r
+      <td class="kt">Clear IRQn Pending Status</td>\r
+    </tr>\r
+    <tr>\r
+      <td class="kt" nowrap="nowrap">uint32_t NVIC_GetActive (IRQn_Type IRQn)</td>\r
+      <td class="kt">M3</td>\r
+      <td class="kt">IRQ Number</td>\r
+      <td class="kt">Return 1 if IRQn is active else 0</td>\r
+    </tr>\r
+    <tr>\r
+      <td class="kt" nowrap="nowrap">void NVIC_SetPriority (IRQn_Type IRQn, uint32_t priority)</td>\r
+      <td class="kt">M0, M3</td>\r
+      <td class="kt">IRQ Number, Priority</td>\r
+      <td class="kt">Set Priority for IRQn<br>\r
+                     (not threadsafe for Cortex-M0)</td>\r
+    </tr>\r
+    <tr>\r
+      <td class="kt" nowrap="nowrap">uint32_t NVIC_GetPriority (IRQn_Type IRQn)</td>\r
+      <td class="kt">M0, M3</td>\r
+      <td class="kt">IRQ Number</td>\r
+      <td class="kt">Get Priority for IRQn</td>\r
+    </tr>\r
+    <tr>\r
+<!--      <td class="kt" nowrap="nowrap">uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)</td> -->\r
+      <td class="kt">uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)</td>\r
+      <td class="kt">M3</td>\r
+      <td class="kt">IRQ Number, Priority Group, Preemptive Priority, Sub Priority</td>\r
+      <td class="kt">Encode priority for given group, preemptive and sub priority</td>\r
+    </tr>\r
+<!--      <td class="kt" nowrap="nowrap">NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)</td> -->\r
+      <td class="kt">NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)</td>\r
+      <td class="kt">M3</td>\r
+      <td class="kt">IRQ Number, Priority, pointer to Priority Group, pointer to Preemptive Priority, pointer to Sub Priority</td>\r
+      <td class="kt">Deccode given priority to group, preemptive and sub priority</td>\r
+    </tr>\r
+    <tr>\r
+      <td class="kt" nowrap="nowrap">void NVIC_SystemReset (void)</td>\r
+      <td class="kt">M0, M3</td>\r
+      <td class="kt">(void)</td>\r
+      <td class="kt">Resets the System</td>\r
+    </tr>\r
+  </tbody>\r
+</table>\r
+<p class="Note">Note</p>\r
+<ul>\r
+  <li><p>The processor exceptions have negative enum values. Device specific interrupts \r
+              have positive enum values and start with 0. The values are defined in\r
+         <b><em>device.h</em></b> file.\r
+      </p>\r
+  </li>\r
+  <li><p>The values for <b>PreemptPriority</b> and <b>SubPriority</b>\r
+         used in functions <b>NVIC_EncodePriority</b> and <b>NVIC_DecodePriority</b>\r
+         depend on the available __NVIC_PRIO_BITS implemented in the NVIC.\r
+      </p>\r
+  </li>\r
+</ul>\r
+\r
+\r
+<h3>SysTick Configuration Function</h3>\r
+\r
+<p>The following function is used to configure the SysTick timer and start the \r
+SysTick interrupt.</p>\r
+\r
+<table class="kt" border="0" cellpadding="0" cellspacing="0">\r
+  <tbody>\r
+    <tr>\r
+      <th class="kt" nowrap="nowrap">Name</th>\r
+      <th class="kt">Parameter</th>\r
+      <th class="kt">Description</th>\r
+    </tr>\r
+    <tr>\r
+      <td class="kt" nowrap="nowrap">uint32_t Sys<span class="style1">TickConfig \r
+               (uint32_t ticks)</span></td>\r
+      <td class="kt">ticks is SysTick counter reload value</td>\r
+      <td class="kt">Setup the SysTick timer and enable the SysTick interrupt. After this \r
+               call the SysTick timer creates interrupts with the specified time \r
+               interval. <br>\r
+               <br>\r
+               Return: 0 when successful, 1 on failure.<br>\r
+               </td>\r
+    </tr>\r
+  </tbody>\r
+</table>\r
+\r
+\r
+<h3>Cortex-M3 ITM Debug Access</h3>\r
+\r
+<p>The Cortex-M3 incorporates the Instrumented Trace Macrocell (ITM) that \r
+provides together with the Serial Viewer Output trace capabilities for the \r
+microcontroller system. The ITM has 32 communication channels; two ITM \r
+communication channels are used by CMSIS to output the following information:</p>\r
+<ul>\r
+       <li>ITM Channel 0: implements the <strong>ITM_SendChar</strong> function \r
+       which can be used for printf-style output via the debug interface.</li>\r
+       <li>ITM Channel 31: is reserved for the RTOS kernel and can be used for \r
+       kernel awareness debugging.</li>\r
+</ul>\r
+<p class="Note">Note</p>\r
+<ul>\r
+  <li><p>The ITM channel 31 is selected for the RTOS kernel since some kernels \r
+       may use the Privileged level for program execution. ITM \r
+       channels have 4 groups with 8 channels each, whereby each group can be \r
+       configured for access rights in the Unprivileged level. The ITM channel 0 \r
+       may be therefore enabled for the user task whereas ITM channel 31 may be \r
+       accessible only in Privileged level from the RTOS kernel itself.</p>\r
+  </li>\r
+</ul>\r
+\r
+<p>The prototype of the <strong>ITM_SendChar</strong> routine is shown in the \r
+table below.</p>\r
+\r
+<table class="kt" border="0" cellpadding="0" cellspacing="0">\r
+  <tbody>\r
+    <tr>\r
+      <th class="kt" nowrap="nowrap">Name</th>\r
+      <th class="kt">Parameter</th>\r
+      <th class="kt">Description</th>\r
+    </tr>\r
+    <tr>\r
+      <td class="kt" nowrap="nowrap">void uint32_t ITM_SendChar(uint32_t chr)</td>\r
+      <td class="kt">character to output</td>\r
+      <td class="kt">The function outputs a character via the ITM channel 0. The \r
+                                function returns when no debugger is connected that has booked the \r
+                                output. It is blocking when a debugger is connected, but the \r
+                                previous character send is not transmitted. <br><br>\r
+                                Return: the input character 'chr'.</td>\r
+    </tr>\r
+  </tbody>\r
+</table>\r
+\r
+<p>\r
+  Example for the usage of the ITM Channel 31 for RTOS Kernels:\r
+</p>\r
+<pre>\r
+  // check if debugger connected and ITM channel enabled for tracing\r
+  if ((CoreDebug-&gt;DEMCR &amp; CoreDebug_DEMCR_TRCENA) &amp;&amp;\r
+  (ITM-&gt;TCR &amp; ITM_TCR_ITMENA) &amp;&amp;\r
+  (ITM-&gt;TER &amp; (1UL &lt;&lt; 31))) {\r
+    // transmit trace data\r
+    while (ITM-&gt;PORT31_U32 == 0);\r
+    ITM-&gt;PORT[31].u8 = task_id;      // id of next task\r
+    while (ITM-&gt;PORT[31].u32 == 0);\r
+    ITM-&gt;PORT[31].u32 = task_status; // status information\r
+  }</pre>\r
+\r
+\r
+<h3>Cortex-M3 additional Debug Access</h3>\r
+\r
+<p>CMSIS provides additional debug functions to enlarge the Cortex-M3 Debug Access.\r
+Data can be transmitted via a certain global buffer variable towards the target system.</p>\r
+\r
+<p>The buffer variable and the prototypes of the additional functions are shown in the \r
+table below.</p>\r
+\r
+<table class="kt" border="0" cellpadding="0" cellspacing="0">\r
+  <tbody>\r
+    <tr>\r
+      <th class="kt" nowrap="nowrap">Name</th>\r
+      <th class="kt">Parameter</th>\r
+      <th class="kt">Description</th>\r
+    </tr>\r
+    <tr>\r
+      <td class="kt" nowrap="nowrap">extern volatile int ITM_RxBuffer</td>\r
+      <td class="kt"> </td>\r
+      <td class="kt">Buffer to transmit data towards debug system. <br><br>\r
+                                Value 0x5AA55AA5 indicates that buffer is empty.</td>\r
+    </tr>\r
+    <tr>\r
+      <td class="kt" nowrap="nowrap">int ITM_ReceiveChar (void)</td>\r
+      <td class="kt">none</td>\r
+      <td class="kt">The nonblocking functions returns the character stored in \r
+                     ITM_RxBuffer. <br><br>\r
+                                Return: -1 indicates that no character was received.</td>\r
+    </tr>\r
+    <tr>\r
+      <td class="kt" nowrap="nowrap">int ITM_CheckChar (void)</td>\r
+      <td class="kt">none</td>\r
+      <td class="kt">The function checks if a character is available in ITM_RxBuffer. <br><br>\r
+                                Return: 1 indicates that a character is available, 0 indicates that\r
+                     no character is available.</td>\r
+    </tr>\r
+  </tbody>\r
+</table>\r
+\r
+\r
+<h2><a name="5"></a>CMSIS Example</h2>\r
+<p>\r
+  The following section shows a typical example for using the CMSIS layer in user applications.\r
+  The example is based on a STM32F10x Device.\r
+</p>\r
+<pre>\r
+#include "stm32f10x.h"\r
+\r
+volatile uint32_t msTicks;                       /* timeTicks counter */\r
+\r
+void SysTick_Handler(void) {\r
+  msTicks++;                                     /* increment timeTicks counter */\r
+}\r
+\r
+__INLINE static void Delay (uint32_t dlyTicks) {\r
+  uint32_t curTicks = msTicks;\r
+\r
+  while ((msTicks - curTicks) &lt; dlyTicks);\r
+}\r
+\r
+__INLINE static void LED_Config(void) {\r
+  ;                                              /* Configure the LEDs */\r
+}\r
+\r
+__INLINE static void LED_On (uint32_t led) {\r
+  ;                                              /* Turn On  LED */\r
+}\r
+\r
+__INLINE static void LED_Off (uint32_t led) {\r
+  ;                                              /* Turn Off LED */\r
+}\r
+\r
+int main (void) {\r
+  if (SysTick_Config (SystemCoreClock / 1000)) { /* Setup SysTick for 1 msec interrupts */\r
+    ;                                            /* Handle Error */\r
+    while (1);\r
+  }\r
+  \r
+  LED_Config();                                  /* configure the LEDs */                            \r
+ \r
+  while(1) {\r
+    LED_On (0x100);                              /* Turn  on the LED   */\r
+    Delay (100);                                 /* delay  100 Msec    */\r
+    LED_Off (0x100);                             /* Turn off the LED   */\r
+    Delay (100);                                 /* delay  100 Msec    */\r
+  }\r
+}</pre>\r
+\r
+\r
+</body></html>
\ No newline at end of file

diff --git a/Demo/CORTEX_STM32L152_IAR/system_and_ST_code/CMSIS/License.doc b/Demo/CORTEX_STM32L152_IAR/system_and_ST_code/CMSIS/License.doc
new file mode 100644 (file)
index 0000000..b6b8ace
Binary files /dev/null and b/Demo/CORTEX_STM32L152_IAR/system_and_ST_code/CMSIS/License.doc differ

diff --git a/Demo/CORTEX_STM32L152_IAR/system_and_ST_code/Common/fonts.c b/Demo/CORTEX_STM32L152_IAR/system_and_ST_code/Common/fonts.c
new file mode 100644 (file)
index 0000000..d45111b
--- /dev/null
+++ b/Demo/CORTEX_STM32L152_IAR/system_and_ST_code/Common/fonts.c
@@ -0,0 +1,996 @@
+/**\r
+  ******************************************************************************\r
+  * @file    fonts.c\r
+  * @author  MCD Application Team\r
+  * @version V4.4.0RC1\r
+  * @date    07/02/2010\r
+  * @brief   This file provides text fonts for STM32xx-EVAL's LCD driver. \r
+  ******************************************************************************\r
+  * @copy\r
+  *\r
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+  *\r
+  * <h2><center>&copy; COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+  */ \r
+  \r
+/* Includes ------------------------------------------------------------------*/\r
+#include "fonts.h"\r
+\r
+/** @addtogroup Utilities\r
+  * @{\r
+  */\r
+  \r
+/** @addtogroup STM32_EVAL\r
+  * @{\r
+  */ \r
+\r
+/** @addtogroup Common\r
+  * @{\r
+  */\r
+\r
+/** @addtogroup FONTS\r
+  * @brief      This file includes the Fonts driver of STM32-EVAL boards.\r
+  * @{\r
+  */  \r
+\r
+/** @defgroup FONTS_Private_Types\r
+  * @{\r
+  */ \r
+/**\r
+  * @}\r
+  */ \r
+\r
+\r
+/** @defgroup FONTS_Private_Defines\r
+  * @{\r
+  */\r
+/**\r
+  * @}\r
+  */ \r
+\r
+\r
+/** @defgroup FONTS_Private_Macros\r
+  * @{\r
+  */\r
+/**\r
+  * @}\r
+  */ \r
+  \r
+\r
+/** @defgroup FONTS_Private_Variables\r
+  * @{\r
+  */\r
+const uint16_t ASCII16x24_Table [] = {\r
+/** \r
+  * @brief        Space ' '  \r
+  */ \r
+         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        '!'  \r
+  */ \r
+         0x0000, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180,\r
+         0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0000, 0x0000,\r
+         0x0180, 0x0180, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        '"'  \r
+  */ \r
+         0x0000, 0x0000, 0x00CC, 0x00CC, 0x00CC, 0x00CC, 0x00CC, 0x00CC,\r
+         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        '#'  \r
+  */ \r
+         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0C60, 0x0C60,\r
+         0x0C60, 0x0630, 0x0630, 0x1FFE, 0x1FFE, 0x0630, 0x0738, 0x0318,\r
+         0x1FFE, 0x1FFE, 0x0318, 0x0318, 0x018C, 0x018C, 0x018C, 0x0000,\r
+/** \r
+  * @brief        '$'  \r
+  */ \r
+         0x0000, 0x0080, 0x03E0, 0x0FF8, 0x0E9C, 0x1C8C, 0x188C, 0x008C,\r
+         0x0098, 0x01F8, 0x07E0, 0x0E80, 0x1C80, 0x188C, 0x188C, 0x189C,\r
+         0x0CB8, 0x0FF0, 0x03E0, 0x0080, 0x0080, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        '%'  \r
+  */ \r
+         0x0000, 0x0000, 0x0000, 0x180E, 0x0C1B, 0x0C11, 0x0611, 0x0611,\r
+         0x0311, 0x0311, 0x019B, 0x018E, 0x38C0, 0x6CC0, 0x4460, 0x4460,\r
+         0x4430, 0x4430, 0x4418, 0x6C18, 0x380C, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        '&'  \r
+  */ \r
+         0x0000, 0x01E0, 0x03F0, 0x0738, 0x0618, 0x0618, 0x0330, 0x01F0,\r
+         0x00F0, 0x00F8, 0x319C, 0x330E, 0x1E06, 0x1C06, 0x1C06, 0x3F06,\r
+         0x73FC, 0x21F0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        '''  \r
+  */ \r
+         0x0000, 0x0000, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C,\r
+         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        '('  \r
+  */ \r
+         0x0000, 0x0200, 0x0300, 0x0180, 0x00C0, 0x00C0, 0x0060, 0x0060,\r
+         0x0030, 0x0030, 0x0030, 0x0030, 0x0030, 0x0030, 0x0030, 0x0030,\r
+         0x0060, 0x0060, 0x00C0, 0x00C0, 0x0180, 0x0300, 0x0200, 0x0000,\r
+/** \r
+  * @brief        ')'  \r
+  */ \r
+         0x0000, 0x0020, 0x0060, 0x00C0, 0x0180, 0x0180, 0x0300, 0x0300,\r
+         0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600,\r
+         0x0300, 0x0300, 0x0180, 0x0180, 0x00C0, 0x0060, 0x0020, 0x0000,\r
+/** \r
+  * @brief        '*'  \r
+  */ \r
+         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x00C0, 0x00C0,\r
+         0x06D8, 0x07F8, 0x01E0, 0x0330, 0x0738, 0x0000, 0x0000, 0x0000,\r
+         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        '+'  \r
+  */ \r
+         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0180, 0x0180,\r
+         0x0180, 0x0180, 0x0180, 0x3FFC, 0x3FFC, 0x0180, 0x0180, 0x0180,\r
+         0x0180, 0x0180, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        ','  \r
+  */ \r
+         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+         0x0000, 0x0180, 0x0180, 0x0100, 0x0100, 0x0080, 0x0000, 0x0000,\r
+/** \r
+  * @brief        '-'  \r
+  */ \r
+         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+         0x0000, 0x0000, 0x0000, 0x0000, 0x07E0, 0x07E0, 0x0000, 0x0000,\r
+         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        '.'  \r
+  */ \r
+         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+         0x0000, 0x00C0, 0x00C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        '/'  \r
+  */ \r
+         0x0000, 0x0C00, 0x0C00, 0x0600, 0x0600, 0x0600, 0x0300, 0x0300,\r
+         0x0300, 0x0380, 0x0180, 0x0180, 0x0180, 0x00C0, 0x00C0, 0x00C0,\r
+         0x0060, 0x0060, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        '0'  \r
+  */ \r
+         0x0000, 0x03E0, 0x07F0, 0x0E38, 0x0C18, 0x180C, 0x180C, 0x180C,\r
+         0x180C, 0x180C, 0x180C, 0x180C, 0x180C, 0x180C, 0x0C18, 0x0E38,\r
+         0x07F0, 0x03E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        '1'  \r
+  */ \r
+         0x0000, 0x0100, 0x0180, 0x01C0, 0x01F0, 0x0198, 0x0188, 0x0180,\r
+         0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180,\r
+         0x0180, 0x0180, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        '2'  \r
+  */ \r
+         0x0000, 0x03E0, 0x0FF8, 0x0C18, 0x180C, 0x180C, 0x1800, 0x1800,\r
+         0x0C00, 0x0600, 0x0300, 0x0180, 0x00C0, 0x0060, 0x0030, 0x0018,\r
+         0x1FFC, 0x1FFC, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        '3'  \r
+  */ \r
+         0x0000, 0x01E0, 0x07F8, 0x0E18, 0x0C0C, 0x0C0C, 0x0C00, 0x0600,\r
+         0x03C0, 0x07C0, 0x0C00, 0x1800, 0x1800, 0x180C, 0x180C, 0x0C18,\r
+         0x07F8, 0x03E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        '4'  \r
+  */ \r
+         0x0000, 0x0C00, 0x0E00, 0x0F00, 0x0F00, 0x0D80, 0x0CC0, 0x0C60,\r
+         0x0C60, 0x0C30, 0x0C18, 0x0C0C, 0x3FFC, 0x3FFC, 0x0C00, 0x0C00,\r
+         0x0C00, 0x0C00, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        '5'  \r
+  */ \r
+         0x0000, 0x0FF8, 0x0FF8, 0x0018, 0x0018, 0x000C, 0x03EC, 0x07FC,\r
+         0x0E1C, 0x1C00, 0x1800, 0x1800, 0x1800, 0x180C, 0x0C1C, 0x0E18,\r
+         0x07F8, 0x03E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        '6'  \r
+  */ \r
+         0x0000, 0x07C0, 0x0FF0, 0x1C38, 0x1818, 0x0018, 0x000C, 0x03CC,\r
+         0x0FEC, 0x0E3C, 0x1C1C, 0x180C, 0x180C, 0x180C, 0x1C18, 0x0E38,\r
+         0x07F0, 0x03E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        '7'  \r
+  */ \r
+         0x0000, 0x1FFC, 0x1FFC, 0x0C00, 0x0600, 0x0600, 0x0300, 0x0380,\r
+         0x0180, 0x01C0, 0x00C0, 0x00E0, 0x0060, 0x0060, 0x0070, 0x0030,\r
+         0x0030, 0x0030, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        '8'  \r
+  */ \r
+         0x0000, 0x03E0, 0x07F0, 0x0E38, 0x0C18, 0x0C18, 0x0C18, 0x0638,\r
+         0x07F0, 0x07F0, 0x0C18, 0x180C, 0x180C, 0x180C, 0x180C, 0x0C38,\r
+         0x0FF8, 0x03E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        '9'  \r
+  */ \r
+         0x0000, 0x03E0, 0x07F0, 0x0E38, 0x0C1C, 0x180C, 0x180C, 0x180C,\r
+         0x1C1C, 0x1E38, 0x1BF8, 0x19E0, 0x1800, 0x0C00, 0x0C00, 0x0E1C,\r
+         0x07F8, 0x01F0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        ':'  \r
+  */ \r
+         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0180, 0x0180,\r
+         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+         0x0180, 0x0180, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        ';'  \r
+  */ \r
+         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0180, 0x0180,\r
+         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+         0x0180, 0x0180, 0x0100, 0x0100, 0x0080, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        '<'  \r
+  */ \r
+         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+         0x1000, 0x1C00, 0x0F80, 0x03E0, 0x00F8, 0x0018, 0x00F8, 0x03E0,\r
+         0x0F80, 0x1C00, 0x1000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        '='  \r
+  */ \r
+         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+         0x1FF8, 0x0000, 0x0000, 0x0000, 0x1FF8, 0x0000, 0x0000, 0x0000,\r
+         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        '>'  \r
+  */ \r
+         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+         0x0008, 0x0038, 0x01F0, 0x07C0, 0x1F00, 0x1800, 0x1F00, 0x07C0,\r
+         0x01F0, 0x0038, 0x0008, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        '?'  \r
+  */ \r
+         0x0000, 0x03E0, 0x0FF8, 0x0C18, 0x180C, 0x180C, 0x1800, 0x0C00,\r
+         0x0600, 0x0300, 0x0180, 0x00C0, 0x00C0, 0x00C0, 0x0000, 0x0000,\r
+         0x00C0, 0x00C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        '@'  \r
+  */ \r
+         0x0000, 0x0000, 0x07E0, 0x1818, 0x2004, 0x29C2, 0x4A22, 0x4411,\r
+         0x4409, 0x4409, 0x4409, 0x2209, 0x1311, 0x0CE2, 0x4002, 0x2004,\r
+         0x1818, 0x07E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        'A'  \r
+  */ \r
+         0x0000, 0x0380, 0x0380, 0x06C0, 0x06C0, 0x06C0, 0x0C60, 0x0C60,\r
+         0x1830, 0x1830, 0x1830, 0x3FF8, 0x3FF8, 0x701C, 0x600C, 0x600C,\r
+         0xC006, 0xC006, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        'B'  \r
+  */ \r
+         0x0000, 0x03FC, 0x0FFC, 0x0C0C, 0x180C, 0x180C, 0x180C, 0x0C0C,\r
+         0x07FC, 0x0FFC, 0x180C, 0x300C, 0x300C, 0x300C, 0x300C, 0x180C,\r
+         0x1FFC, 0x07FC, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        'C'  \r
+  */ \r
+         0x0000, 0x07C0, 0x1FF0, 0x3838, 0x301C, 0x700C, 0x6006, 0x0006,\r
+         0x0006, 0x0006, 0x0006, 0x0006, 0x0006, 0x6006, 0x700C, 0x301C,\r
+         0x1FF0, 0x07E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        'D'  \r
+  */ \r
+         0x0000, 0x03FE, 0x0FFE, 0x0E06, 0x1806, 0x1806, 0x3006, 0x3006,\r
+         0x3006, 0x3006, 0x3006, 0x3006, 0x3006, 0x1806, 0x1806, 0x0E06,\r
+         0x0FFE, 0x03FE, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        'E'  \r
+  */ \r
+         0x0000, 0x3FFC, 0x3FFC, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C,\r
+         0x1FFC, 0x1FFC, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C,\r
+         0x3FFC, 0x3FFC, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        'F'  \r
+  */ \r
+         0x0000, 0x3FF8, 0x3FF8, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018,\r
+         0x1FF8, 0x1FF8, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018,\r
+         0x0018, 0x0018, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        'G'  \r
+  */ \r
+         0x0000, 0x0FE0, 0x3FF8, 0x783C, 0x600E, 0xE006, 0xC007, 0x0003,\r
+         0x0003, 0xFE03, 0xFE03, 0xC003, 0xC007, 0xC006, 0xC00E, 0xF03C,\r
+         0x3FF8, 0x0FE0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        'H'  \r
+  */ \r
+         0x0000, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C,\r
+         0x3FFC, 0x3FFC, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C,\r
+         0x300C, 0x300C, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        'I'  \r
+  */ \r
+         0x0000, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180,\r
+         0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180,\r
+         0x0180, 0x0180, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        'J'  \r
+  */ \r
+         0x0000, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600,\r
+         0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0618, 0x0618, 0x0738,\r
+         0x03F0, 0x01E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        'K'  \r
+  */ \r
+         0x0000, 0x3006, 0x1806, 0x0C06, 0x0606, 0x0306, 0x0186, 0x00C6,\r
+         0x0066, 0x0076, 0x00DE, 0x018E, 0x0306, 0x0606, 0x0C06, 0x1806,\r
+         0x3006, 0x6006, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        'L'  \r
+  */ \r
+         0x0000, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018,\r
+         0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018,\r
+         0x1FF8, 0x1FF8, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        'M'  \r
+  */ \r
+         0x0000, 0xE00E, 0xF01E, 0xF01E, 0xF01E, 0xD836, 0xD836, 0xD836,\r
+         0xD836, 0xCC66, 0xCC66, 0xCC66, 0xC6C6, 0xC6C6, 0xC6C6, 0xC6C6,\r
+         0xC386, 0xC386, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        'N'  \r
+  */ \r
+         0x0000, 0x300C, 0x301C, 0x303C, 0x303C, 0x306C, 0x306C, 0x30CC,\r
+         0x30CC, 0x318C, 0x330C, 0x330C, 0x360C, 0x360C, 0x3C0C, 0x3C0C,\r
+         0x380C, 0x300C, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        'O'  \r
+  */ \r
+         0x0000, 0x07E0, 0x1FF8, 0x381C, 0x700E, 0x6006, 0xC003, 0xC003,\r
+         0xC003, 0xC003, 0xC003, 0xC003, 0xC003, 0x6006, 0x700E, 0x381C,\r
+         0x1FF8, 0x07E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        'P'  \r
+  */ \r
+         0x0000, 0x0FFC, 0x1FFC, 0x380C, 0x300C, 0x300C, 0x300C, 0x300C,\r
+         0x180C, 0x1FFC, 0x07FC, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C,\r
+         0x000C, 0x000C, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        'Q'  \r
+  */ \r
+         0x0000, 0x07E0, 0x1FF8, 0x381C, 0x700E, 0x6006, 0xE003, 0xC003,\r
+         0xC003, 0xC003, 0xC003, 0xC003, 0xE007, 0x6306, 0x3F0E, 0x3C1C,\r
+         0x3FF8, 0xF7E0, 0xC000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        'R'  \r
+  */ \r
+         0x0000, 0x0FFE, 0x1FFE, 0x3806, 0x3006, 0x3006, 0x3006, 0x3806,\r
+         0x1FFE, 0x07FE, 0x0306, 0x0606, 0x0C06, 0x1806, 0x1806, 0x3006,\r
+         0x3006, 0x6006, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        'S'  \r
+  */ \r
+         0x0000, 0x03E0, 0x0FF8, 0x0C1C, 0x180C, 0x180C, 0x000C, 0x001C,\r
+         0x03F8, 0x0FE0, 0x1E00, 0x3800, 0x3006, 0x3006, 0x300E, 0x1C1C,\r
+         0x0FF8, 0x07E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        'T'  \r
+  */ \r
+         0x0000, 0x7FFE, 0x7FFE, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180,\r
+         0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180,\r
+         0x0180, 0x0180, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        'U'  \r
+  */ \r
+         0x0000, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C,\r
+         0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x1818,\r
+         0x1FF8, 0x07E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        'V'  \r
+  */ \r
+         0x0000, 0x6003, 0x3006, 0x3006, 0x3006, 0x180C, 0x180C, 0x180C,\r
+         0x0C18, 0x0C18, 0x0E38, 0x0630, 0x0630, 0x0770, 0x0360, 0x0360,\r
+         0x01C0, 0x01C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        'W'  \r
+  */ \r
+         0x0000, 0x6003, 0x61C3, 0x61C3, 0x61C3, 0x3366, 0x3366, 0x3366,\r
+         0x3366, 0x3366, 0x3366, 0x1B6C, 0x1B6C, 0x1B6C, 0x1A2C, 0x1E3C,\r
+         0x0E38, 0x0E38, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        'X'  \r
+  */ \r
+         0x0000, 0xE00F, 0x700C, 0x3018, 0x1830, 0x0C70, 0x0E60, 0x07C0,\r
+         0x0380, 0x0380, 0x03C0, 0x06E0, 0x0C70, 0x1C30, 0x1818, 0x300C,\r
+         0x600E, 0xE007, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        'Y'  \r
+  */ \r
+         0x0000, 0xC003, 0x6006, 0x300C, 0x381C, 0x1838, 0x0C30, 0x0660,\r
+         0x07E0, 0x03C0, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180,\r
+         0x0180, 0x0180, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        'Z'  \r
+  */ \r
+         0x0000, 0x7FFC, 0x7FFC, 0x6000, 0x3000, 0x1800, 0x0C00, 0x0600,\r
+         0x0300, 0x0180, 0x00C0, 0x0060, 0x0030, 0x0018, 0x000C, 0x0006,\r
+         0x7FFE, 0x7FFE, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        '['  \r
+  */ \r
+         0x0000, 0x03E0, 0x03E0, 0x0060, 0x0060, 0x0060, 0x0060, 0x0060,\r
+         0x0060, 0x0060, 0x0060, 0x0060, 0x0060, 0x0060, 0x0060, 0x0060,\r
+         0x0060, 0x0060, 0x0060, 0x0060, 0x0060, 0x03E0, 0x03E0, 0x0000,\r
+/** \r
+  * @brief        '\'  \r
+  */ \r
+         0x0000, 0x0030, 0x0030, 0x0060, 0x0060, 0x0060, 0x00C0, 0x00C0,\r
+         0x00C0, 0x01C0, 0x0180, 0x0180, 0x0180, 0x0300, 0x0300, 0x0300,\r
+         0x0600, 0x0600, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        ']'  \r
+  */ \r
+         0x0000, 0x03E0, 0x03E0, 0x0300, 0x0300, 0x0300, 0x0300, 0x0300,\r
+         0x0300, 0x0300, 0x0300, 0x0300, 0x0300, 0x0300, 0x0300, 0x0300,\r
+         0x0300, 0x0300, 0x0300, 0x0300, 0x0300, 0x03E0, 0x03E0, 0x0000,\r
+/** \r
+  * @brief        '^'  \r
+  */ \r
+         0x0000, 0x0000, 0x01C0, 0x01C0, 0x0360, 0x0360, 0x0360, 0x0630,\r
+         0x0630, 0x0C18, 0x0C18, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        '_'  \r
+  */ \r
+         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+         0x0000, 0xFFFF, 0xFFFF, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        '''  \r
+  */ \r
+         0x0000, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C, 0x0000,\r
+         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        'a'  \r
+  */ \r
+         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x03F0, 0x07F8,\r
+         0x0C1C, 0x0C0C, 0x0F00, 0x0FF0, 0x0CF8, 0x0C0C, 0x0C0C, 0x0F1C,\r
+         0x0FF8, 0x18F0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        'b'  \r
+  */ \r
+         0x0000, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x03D8, 0x0FF8,\r
+         0x0C38, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x0C38,\r
+         0x0FF8, 0x03D8, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        'c'  \r
+  */ \r
+         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x03C0, 0x07F0,\r
+         0x0E30, 0x0C18, 0x0018, 0x0018, 0x0018, 0x0018, 0x0C18, 0x0E30,\r
+         0x07F0, 0x03C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        'd'  \r
+  */ \r
+         0x0000, 0x1800, 0x1800, 0x1800, 0x1800, 0x1800, 0x1BC0, 0x1FF0,\r
+         0x1C30, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1C30,\r
+         0x1FF0, 0x1BC0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        'e'  \r
+  */ \r
+         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x03C0, 0x0FF0,\r
+         0x0C30, 0x1818, 0x1FF8, 0x1FF8, 0x0018, 0x0018, 0x1838, 0x1C30,\r
+         0x0FF0, 0x07C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        'f'  \r
+  */ \r
+         0x0000, 0x0F80, 0x0FC0, 0x00C0, 0x00C0, 0x00C0, 0x07F0, 0x07F0,\r
+         0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0,\r
+         0x00C0, 0x00C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        'g'  \r
+  */ \r
+         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0DE0, 0x0FF8,\r
+         0x0E18, 0x0C0C, 0x0C0C, 0x0C0C, 0x0C0C, 0x0C0C, 0x0C0C, 0x0E18,\r
+         0x0FF8, 0x0DE0, 0x0C00, 0x0C0C, 0x061C, 0x07F8, 0x01F0, 0x0000,\r
+/** \r
+  * @brief        'h'  \r
+  */ \r
+         0x0000, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x07D8, 0x0FF8,\r
+         0x1C38, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818,\r
+         0x1818, 0x1818, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        'i'  \r
+  */ \r
+         0x0000, 0x00C0, 0x00C0, 0x0000, 0x0000, 0x0000, 0x00C0, 0x00C0,\r
+         0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0,\r
+         0x00C0, 0x00C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        'j'  \r
+  */ \r
+         0x0000, 0x00C0, 0x00C0, 0x0000, 0x0000, 0x0000, 0x00C0, 0x00C0,\r
+         0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0,\r
+         0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00F8, 0x0078, 0x0000,\r
+/** \r
+  * @brief        'k'  \r
+  */ \r
+         0x0000, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C, 0x0C0C, 0x060C,\r
+         0x030C, 0x018C, 0x00CC, 0x006C, 0x00FC, 0x019C, 0x038C, 0x030C,\r
+         0x060C, 0x0C0C, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        'l'  \r
+  */ \r
+         0x0000, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0,\r
+         0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0,\r
+         0x00C0, 0x00C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        'm'  \r
+  */ \r
+         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x3C7C, 0x7EFF,\r
+         0xE3C7, 0xC183, 0xC183, 0xC183, 0xC183, 0xC183, 0xC183, 0xC183,\r
+         0xC183, 0xC183, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        'n'  \r
+  */ \r
+         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0798, 0x0FF8,\r
+         0x1C38, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818,\r
+         0x1818, 0x1818, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        'o'  \r
+  */ \r
+         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x03C0, 0x0FF0,\r
+         0x0C30, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x0C30,\r
+         0x0FF0, 0x03C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        'p'  \r
+  */ \r
+         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x03D8, 0x0FF8,\r
+         0x0C38, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x0C38,\r
+         0x0FF8, 0x03D8, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0000,\r
+/** \r
+  * @brief        'q'  \r
+  */ \r
+         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x1BC0, 0x1FF0,\r
+         0x1C30, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1C30,\r
+         0x1FF0, 0x1BC0, 0x1800, 0x1800, 0x1800, 0x1800, 0x1800, 0x0000,\r
+/** \r
+  * @brief        'r'  \r
+  */ \r
+         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x07B0, 0x03F0,\r
+         0x0070, 0x0030, 0x0030, 0x0030, 0x0030, 0x0030, 0x0030, 0x0030,\r
+         0x0030, 0x0030, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        's'  \r
+  */ \r
+         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x03E0, 0x03F0,\r
+         0x0E38, 0x0C18, 0x0038, 0x03F0, 0x07C0, 0x0C00, 0x0C18, 0x0E38,\r
+         0x07F0, 0x03E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        't'  \r
+  */ \r
+         0x0000, 0x0000, 0x0080, 0x00C0, 0x00C0, 0x00C0, 0x07F0, 0x07F0,\r
+         0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0,\r
+         0x07C0, 0x0780, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        'u'  \r
+  */ \r
+         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x1818, 0x1818,\r
+         0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1C38,\r
+         0x1FF0, 0x19E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        'v'  \r
+  */ \r
+         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x180C, 0x0C18,\r
+         0x0C18, 0x0C18, 0x0630, 0x0630, 0x0630, 0x0360, 0x0360, 0x0360,\r
+         0x01C0, 0x01C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        'w'  \r
+  */ \r
+         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x41C1, 0x41C1,\r
+         0x61C3, 0x6363, 0x6363, 0x6363, 0x3636, 0x3636, 0x3636, 0x1C1C,\r
+         0x1C1C, 0x1C1C, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        'x'  \r
+  */ \r
+         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x381C, 0x1C38,\r
+         0x0C30, 0x0660, 0x0360, 0x0360, 0x0360, 0x0360, 0x0660, 0x0C30,\r
+         0x1C38, 0x381C, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        'y'  \r
+  */ \r
+         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x3018, 0x1830,\r
+         0x1830, 0x1870, 0x0C60, 0x0C60, 0x0CE0, 0x06C0, 0x06C0, 0x0380,\r
+         0x0380, 0x0380, 0x0180, 0x0180, 0x01C0, 0x00F0, 0x0070, 0x0000,\r
+/** \r
+  * @brief        'z'  \r
+  */ \r
+         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x1FFC, 0x1FFC,\r
+         0x0C00, 0x0600, 0x0300, 0x0180, 0x00C0, 0x0060, 0x0030, 0x0018,\r
+         0x1FFC, 0x1FFC, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        '{'  \r
+  */ \r
+         0x0000, 0x0300, 0x0180, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0,\r
+         0x00C0, 0x0060, 0x0060, 0x0030, 0x0060, 0x0040, 0x00C0, 0x00C0,\r
+         0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x0180, 0x0300, 0x0000, 0x0000,\r
+/** \r
+  * @brief        '|'  \r
+  */ \r
+         0x0000, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180,\r
+         0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180,\r
+         0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0000,\r
+/** \r
+  * @brief        '}'  \r
+  */ \r
+         0x0000, 0x0060, 0x00C0, 0x01C0, 0x0180, 0x0180, 0x0180, 0x0180,\r
+         0x0180, 0x0300, 0x0300, 0x0600, 0x0300, 0x0100, 0x0180, 0x0180,\r
+         0x0180, 0x0180, 0x0180, 0x0180, 0x00C0, 0x0060, 0x0000, 0x0000,\r
+/** \r
+  * @brief        '~'  \r
+  */ \r
+         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+         0x10F0, 0x1FF8, 0x0F08, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000};\r
+\r
+const uint16_t ASCII12x12_Table [] = {\r
+    0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,\r
+    0x0000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x0000,0x2000,0x0000,0x0000,\r
+    0x0000,0x5000,0x5000,0x5000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,\r
+    0x0000,0x0900,0x0900,0x1200,0x7f00,0x1200,0x7f00,0x1200,0x2400,0x2400,0x0000,0x0000,\r
+    0x1000,0x3800,0x5400,0x5000,0x5000,0x3800,0x1400,0x5400,0x5400,0x3800,0x1000,0x0000,\r
+    0x0000,0x3080,0x4900,0x4900,0x4a00,0x32c0,0x0520,0x0920,0x0920,0x10c0,0x0000,0x0000,\r
+    0x0000,0x0c00,0x1200,0x1200,0x1400,0x1800,0x2500,0x2300,0x2300,0x1d80,0x0000,0x0000,\r
+    0x0000,0x4000,0x4000,0x4000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,\r
+    0x0000,0x0800,0x1000,0x1000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x1000,0x1000,\r
+    0x0000,0x4000,0x2000,0x2000,0x1000,0x1000,0x1000,0x1000,0x1000,0x1000,0x2000,0x2000,\r
+    0x0000,0x2000,0x7000,0x2000,0x5000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,\r
+    0x0000,0x0000,0x0000,0x0800,0x0800,0x7f00,0x0800,0x0800,0x0000,0x0000,0x0000,0x0000,\r
+    0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x2000,0x2000,0x4000,\r
+    0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x7000,0x0000,0x0000,0x0000,0x0000,0x0000,\r
+    0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x2000,0x0000,0x0000,\r
+    0x0000,0x1000,0x1000,0x1000,0x2000,0x2000,0x2000,0x2000,0x4000,0x4000,0x0000,0x0000,\r
+    0x0000,0x1000,0x2800,0x4400,0x4400,0x4400,0x4400,0x4400,0x2800,0x1000,0x0000,0x0000,\r
+    0x0000,0x1000,0x3000,0x5000,0x1000,0x1000,0x1000,0x1000,0x1000,0x1000,0x0000,0x0000,\r
+    0x0000,0x3000,0x4800,0x4400,0x0400,0x0800,0x1000,0x2000,0x4000,0x7c00,0x0000,0x0000,\r
+    0x0000,0x3000,0x4800,0x0400,0x0800,0x1000,0x0800,0x4400,0x4800,0x3000,0x0000,0x0000,\r
+    0x0000,0x0800,0x1800,0x1800,0x2800,0x2800,0x4800,0x7c00,0x0800,0x0800,0x0000,0x0000,\r
+    0x0000,0x3c00,0x2000,0x4000,0x7000,0x4800,0x0400,0x4400,0x4800,0x3000,0x0000,0x0000,\r
+    0x0000,0x1800,0x2400,0x4000,0x5000,0x6800,0x4400,0x4400,0x2800,0x1000,0x0000,0x0000,\r
+    0x0000,0x7c00,0x0400,0x0800,0x1000,0x1000,0x1000,0x2000,0x2000,0x2000,0x0000,0x0000,\r
+    0x0000,0x1000,0x2800,0x4400,0x2800,0x1000,0x2800,0x4400,0x2800,0x1000,0x0000,0x0000,\r
+    0x0000,0x1000,0x2800,0x4400,0x4400,0x2c00,0x1400,0x0400,0x4800,0x3000,0x0000,0x0000,\r
+    0x0000,0x0000,0x0000,0x2000,0x0000,0x0000,0x0000,0x0000,0x0000,0x2000,0x0000,0x0000,\r
+    0x0000,0x0000,0x0000,0x2000,0x0000,0x0000,0x0000,0x0000,0x0000,0x2000,0x2000,0x4000,\r
+    0x0000,0x0000,0x0400,0x0800,0x3000,0x4000,0x3000,0x0800,0x0400,0x0000,0x0000,0x0000,\r
+    0x0000,0x0000,0x0000,0x7c00,0x0000,0x0000,0x7c00,0x0000,0x0000,0x0000,0x0000,0x0000,\r
+    0x0000,0x0000,0x4000,0x2000,0x1800,0x0400,0x1800,0x2000,0x4000,0x0000,0x0000,0x0000,\r
+    0x0000,0x3800,0x6400,0x4400,0x0400,0x0800,0x1000,0x1000,0x0000,0x1000,0x0000,0x0000,\r
+    0x0000,0x0f80,0x1040,0x2ea0,0x51a0,0x5120,0x5120,0x5120,0x5320,0x4dc0,0x2020,0x1040,\r
+    0x0000,0x0800,0x1400,0x1400,0x1400,0x2200,0x3e00,0x2200,0x4100,0x4100,0x0000,0x0000,\r
+    0x0000,0x3c00,0x2200,0x2200,0x2200,0x3c00,0x2200,0x2200,0x2200,0x3c00,0x0000,0x0000,\r
+    0x0000,0x0e00,0x1100,0x2100,0x2000,0x2000,0x2000,0x2100,0x1100,0x0e00,0x0000,0x0000,\r
+    0x0000,0x3c00,0x2200,0x2100,0x2100,0x2100,0x2100,0x2100,0x2200,0x3c00,0x0000,0x0000,\r
+    0x0000,0x3e00,0x2000,0x2000,0x2000,0x3e00,0x2000,0x2000,0x2000,0x3e00,0x0000,0x0000,\r
+    0x0000,0x3e00,0x2000,0x2000,0x2000,0x3c00,0x2000,0x2000,0x2000,0x2000,0x0000,0x0000,\r
+    0x0000,0x0e00,0x1100,0x2100,0x2000,0x2700,0x2100,0x2100,0x1100,0x0e00,0x0000,0x0000,\r
+    0x0000,0x2100,0x2100,0x2100,0x2100,0x3f00,0x2100,0x2100,0x2100,0x2100,0x0000,0x0000,\r
+    0x0000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x0000,0x0000,\r
+    0x0000,0x0800,0x0800,0x0800,0x0800,0x0800,0x0800,0x4800,0x4800,0x3000,0x0000,0x0000,\r
+    0x0000,0x2200,0x2400,0x2800,0x2800,0x3800,0x2800,0x2400,0x2400,0x2200,0x0000,0x0000,\r
+    0x0000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x3e00,0x0000,0x0000,\r
+    0x0000,0x2080,0x3180,0x3180,0x3180,0x2a80,0x2a80,0x2a80,0x2a80,0x2480,0x0000,0x0000,\r
+    0x0000,0x2100,0x3100,0x3100,0x2900,0x2900,0x2500,0x2300,0x2300,0x2100,0x0000,0x0000,\r
+    0x0000,0x0c00,0x1200,0x2100,0x2100,0x2100,0x2100,0x2100,0x1200,0x0c00,0x0000,0x0000,\r
+    0x0000,0x3c00,0x2200,0x2200,0x2200,0x3c00,0x2000,0x2000,0x2000,0x2000,0x0000,0x0000,\r
+    0x0000,0x0c00,0x1200,0x2100,0x2100,0x2100,0x2100,0x2100,0x1600,0x0d00,0x0100,0x0000,\r
+    0x0000,0x3e00,0x2100,0x2100,0x2100,0x3e00,0x2400,0x2200,0x2100,0x2080,0x0000,0x0000,\r
+    0x0000,0x1c00,0x2200,0x2200,0x2000,0x1c00,0x0200,0x2200,0x2200,0x1c00,0x0000,0x0000,\r
+    0x0000,0x3e00,0x0800,0x0800,0x0800,0x0800,0x0800,0x0800,0x0800,0x0800,0x0000,0x0000,\r
+    0x0000,0x2100,0x2100,0x2100,0x2100,0x2100,0x2100,0x2100,0x1200,0x0c00,0x0000,0x0000,\r
+    0x0000,0x4100,0x4100,0x2200,0x2200,0x2200,0x1400,0x1400,0x1400,0x0800,0x0000,0x0000,\r
+    0x0000,0x4440,0x4a40,0x2a40,0x2a80,0x2a80,0x2a80,0x2a80,0x2a80,0x1100,0x0000,0x0000,\r
+    0x0000,0x4100,0x2200,0x1400,0x1400,0x0800,0x1400,0x1400,0x2200,0x4100,0x0000,0x0000,\r
+    0x0000,0x4100,0x2200,0x2200,0x1400,0x0800,0x0800,0x0800,0x0800,0x0800,0x0000,0x0000,\r
+    0x0000,0x7e00,0x0200,0x0400,0x0800,0x1000,0x1000,0x2000,0x4000,0x7e00,0x0000,0x0000,\r
+    0x0000,0x3000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,\r
+    0x0000,0x4000,0x4000,0x2000,0x2000,0x2000,0x2000,0x2000,0x1000,0x1000,0x0000,0x0000,\r
+    0x0000,0x6000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,\r
+    0x0000,0x1000,0x2800,0x2800,0x2800,0x4400,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,\r
+    0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x7e00,\r
+    0x4000,0x2000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,\r
+    0x0000,0x0000,0x0000,0x3800,0x4400,0x0400,0x3c00,0x4400,0x4400,0x3c00,0x0000,0x0000,\r
+    0x0000,0x4000,0x4000,0x5800,0x6400,0x4400,0x4400,0x4400,0x6400,0x5800,0x0000,0x0000,\r
+    0x0000,0x0000,0x0000,0x3000,0x4800,0x4000,0x4000,0x4000,0x4800,0x3000,0x0000,0x0000,\r
+    0x0000,0x0400,0x0400,0x3400,0x4c00,0x4400,0x4400,0x4400,0x4c00,0x3400,0x0000,0x0000,\r
+    0x0000,0x0000,0x0000,0x3800,0x4400,0x4400,0x7c00,0x4000,0x4400,0x3800,0x0000,0x0000,\r
+    0x0000,0x6000,0x4000,0xe000,0x4000,0x4000,0x4000,0x4000,0x4000,0x4000,0x0000,0x0000,\r
+    0x0000,0x0000,0x0000,0x3400,0x4c00,0x4400,0x4400,0x4400,0x4c00,0x3400,0x0400,0x4400,\r
+    0x0000,0x4000,0x4000,0x5800,0x6400,0x4400,0x4400,0x4400,0x4400,0x4400,0x0000,0x0000,\r
+    0x0000,0x4000,0x0000,0x4000,0x4000,0x4000,0x4000,0x4000,0x4000,0x4000,0x0000,0x0000,\r
+    0x0000,0x4000,0x0000,0x4000,0x4000,0x4000,0x4000,0x4000,0x4000,0x4000,0x4000,0x4000,\r
+    0x0000,0x4000,0x4000,0x4800,0x5000,0x6000,0x5000,0x5000,0x4800,0x4800,0x0000,0x0000,\r
+    0x0000,0x4000,0x4000,0x4000,0x4000,0x4000,0x4000,0x4000,0x4000,0x4000,0x0000,0x0000,\r
+    0x0000,0x0000,0x0000,0x5200,0x6d00,0x4900,0x4900,0x4900,0x4900,0x4900,0x0000,0x0000,\r
+    0x0000,0x0000,0x0000,0x5800,0x6400,0x4400,0x4400,0x4400,0x4400,0x4400,0x0000,0x0000,\r
+    0x0000,0x0000,0x0000,0x3800,0x4400,0x4400,0x4400,0x4400,0x4400,0x3800,0x0000,0x0000,\r
+    0x0000,0x0000,0x0000,0x5800,0x6400,0x4400,0x4400,0x4400,0x6400,0x5800,0x4000,0x4000,\r
+    0x0000,0x0000,0x0000,0x3400,0x4c00,0x4400,0x4400,0x4400,0x4c00,0x3400,0x0400,0x0400,\r
+    0x0000,0x0000,0x0000,0x5000,0x6000,0x4000,0x4000,0x4000,0x4000,0x4000,0x0000,0x0000,\r
+    0x0000,0x0000,0x0000,0x3000,0x4800,0x4000,0x3000,0x0800,0x4800,0x3000,0x0000,0x0000,\r
+    0x0000,0x4000,0x4000,0xe000,0x4000,0x4000,0x4000,0x4000,0x4000,0x6000,0x0000,0x0000,\r
+    0x0000,0x0000,0x0000,0x4400,0x4400,0x4400,0x4400,0x4400,0x4c00,0x3400,0x0000,0x0000,\r
+    0x0000,0x0000,0x0000,0x4400,0x4400,0x2800,0x2800,0x2800,0x2800,0x1000,0x0000,0x0000,\r
+    0x0000,0x0000,0x0000,0x4900,0x4900,0x5500,0x5500,0x5500,0x5500,0x2200,0x0000,0x0000,\r
+    0x0000,0x0000,0x0000,0x4400,0x2800,0x2800,0x1000,0x2800,0x2800,0x4400,0x0000,0x0000,\r
+    0x0000,0x0000,0x0000,0x4400,0x4400,0x2800,0x2800,0x2800,0x1000,0x1000,0x1000,0x1000,\r
+    0x0000,0x0000,0x0000,0x7800,0x0800,0x1000,0x2000,0x2000,0x4000,0x7800,0x0000,0x0000,\r
+    0x0000,0x1000,0x2000,0x2000,0x2000,0x2000,0x4000,0x2000,0x2000,0x2000,0x2000,0x2000,\r
+    0x0000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,\r
+    0x0000,0x4000,0x2000,0x2000,0x2000,0x2000,0x1000,0x2000,0x2000,0x2000,0x2000,0x2000,\r
+    0x0000,0x0000,0x0000,0x0000,0x7400,0x5800,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,\r
+    0x0000,0x0000,0x7000,0x5000,0x5000,0x5000,0x5000,0x5000,0x5000,0x7000,0x0000,0x0000};\r
+\r
+const uint16_t ASCII8x12_Table [] = {\r
+    0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,\r
+    0x00,0x00,0x00,0x10,0x10,0x10,0x10,0x10,0x10,0x00,0x10,0x00,\r
+    0x00,0x00,0x00,0x28,0x28,0x28,0x00,0x00,0x00,0x00,0x00,0x00,\r
+    0x00,0x00,0x00,0x14,0x14,0x3e,0x14,0x28,0x7c,0x28,0x28,0x00,\r
+    0x00,0x00,0x10,0x38,0x54,0x50,0x38,0x14,0x14,0x54,0x38,0x10,\r
+    0x00,0x00,0x00,0x44,0xa8,0xa8,0x50,0x14,0x1a,0x2a,0x24,0x00,\r
+    0x00,0x00,0x00,0x20,0x50,0x50,0x20,0xe8,0x98,0x98,0x60,0x00,\r
+    0x00,0x00,0x00,0x80,0x80,0x80,0x00,0x00,0x00,0x00,0x00,0x00,\r
+    0x00,0x00,0x00,0x40,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,\r
+    0x00,0x00,0x00,0x80,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,\r
+    0x00,0x00,0x00,0x40,0xe0,0x40,0xa0,0x00,0x00,0x00,0x00,0x00,\r
+    0x00,0x00,0x00,0x00,0x00,0x20,0x20,0xf8,0x20,0x20,0x00,0x00,\r
+    0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x40,\r
+    0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xc0,0x00,0x00,0x00,\r
+    0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x00,\r
+    0x00,0x00,0x00,0x20,0x20,0x20,0x40,0x40,0x80,0x80,0x80,0x00,\r
+    0x00,0x00,0x00,0x60,0x90,0x90,0x90,0x90,0x90,0x90,0x60,0x00,\r
+    0x00,0x00,0x00,0x20,0x60,0xa0,0x20,0x20,0x20,0x20,0x20,0x00,\r
+    0x00,0x00,0x00,0x60,0x90,0x10,0x10,0x20,0x40,0x80,0xf0,0x00,\r
+    0x00,0x00,0x00,0x60,0x90,0x10,0x60,0x10,0x10,0x90,0x60,0x00,\r
+    0x00,0x00,0x00,0x10,0x30,0x50,0x50,0x90,0xf8,0x10,0x10,0x00,\r
+    0x00,0x00,0x00,0x70,0x40,0x80,0xe0,0x10,0x10,0x90,0x60,0x00,\r
+    0x00,0x00,0x00,0x60,0x90,0x80,0xa0,0xd0,0x90,0x90,0x60,0x00,\r
+    0x00,0x00,0x00,0xf0,0x10,0x20,0x20,0x20,0x40,0x40,0x40,0x00,\r
+    0x00,0x00,0x00,0x60,0x90,0x90,0x60,0x90,0x90,0x90,0x60,0x00,\r
+    0x00,0x00,0x00,0x60,0x90,0x90,0xb0,0x50,0x10,0x90,0x60,0x00,\r
+    0x00,0x00,0x00,0x00,0x00,0x40,0x00,0x00,0x00,0x00,0x40,0x00,\r
+    0x00,0x00,0x00,0x00,0x00,0x40,0x00,0x00,0x00,0x00,0x40,0x40,\r
+    0x00,0x00,0x00,0x00,0x00,0x10,0x60,0x80,0x60,0x10,0x00,0x00,\r
+    0x00,0x00,0x00,0x00,0x00,0x00,0xf0,0x00,0xf0,0x00,0x00,0x00,\r
+    0x00,0x00,0x00,0x00,0x00,0x80,0x60,0x10,0x60,0x80,0x00,0x00,\r
+    0x00,0x00,0x00,0x60,0x90,0x10,0x20,0x40,0x40,0x00,0x40,0x00,\r
+    0x00,0x00,0x00,0x1c,0x22,0x5b,0xa5,0xa5,0xa5,0xa5,0x9e,0x41,\r
+    0x00,0x00,0x00,0x20,0x50,0x50,0x50,0x50,0x70,0x88,0x88,0x00,\r
+    0x00,0x00,0x00,0xf0,0x88,0x88,0xf0,0x88,0x88,0x88,0xf0,0x00,\r
+    0x00,0x00,0x00,0x38,0x44,0x84,0x80,0x80,0x84,0x44,0x38,0x00,\r
+    0x00,0x00,0x00,0xe0,0x90,0x88,0x88,0x88,0x88,0x90,0xe0,0x00,\r
+    0x00,0x00,0x00,0xf8,0x80,0x80,0xf8,0x80,0x80,0x80,0xf8,0x00,\r
+    0x00,0x00,0x00,0x78,0x40,0x40,0x70,0x40,0x40,0x40,0x40,0x00,\r
+    0x00,0x00,0x00,0x38,0x44,0x84,0x80,0x9c,0x84,0x44,0x38,0x00,\r
+    0x00,0x00,0x00,0x88,0x88,0x88,0xf8,0x88,0x88,0x88,0x88,0x00,\r
+    0x00,0x00,0x00,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x00,\r
+    0x00,0x00,0x00,0x10,0x10,0x10,0x10,0x10,0x90,0x90,0x60,0x00,\r
+    0x00,0x00,0x00,0x88,0x90,0xa0,0xe0,0xa0,0x90,0x90,0x88,0x00,\r
+    0x00,0x00,0x00,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0xf0,0x00,\r
+    0x00,0x00,0x00,0x82,0xc6,0xc6,0xaa,0xaa,0xaa,0xaa,0x92,0x00,\r
+    0x00,0x00,0x00,0x84,0xc4,0xa4,0xa4,0x94,0x94,0x8c,0x84,0x00,\r
+    0x00,0x00,0x00,0x30,0x48,0x84,0x84,0x84,0x84,0x48,0x30,0x00,\r
+    0x00,0x00,0x00,0xf0,0x88,0x88,0x88,0xf0,0x80,0x80,0x80,0x00,\r
+    0x00,0x00,0x00,0x30,0x48,0x84,0x84,0x84,0x84,0x58,0x34,0x04,\r
+    0x00,0x00,0x00,0x78,0x44,0x44,0x78,0x50,0x48,0x44,0x42,0x00,\r
+    0x00,0x00,0x00,0x70,0x88,0x80,0x70,0x08,0x88,0x88,0x70,0x00,\r
+    0x00,0x00,0x00,0xf8,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x00,\r
+    0x00,0x00,0x00,0x84,0x84,0x84,0x84,0x84,0x84,0x48,0x30,0x00,\r
+    0x00,0x00,0x00,0x88,0x88,0x50,0x50,0x50,0x50,0x50,0x20,0x00,\r
+    0x00,0x00,0x00,0x92,0xaa,0xaa,0xaa,0xaa,0xaa,0xaa,0x44,0x00,\r
+    0x00,0x00,0x00,0x84,0x48,0x48,0x30,0x30,0x48,0x48,0x84,0x00,\r
+    0x00,0x00,0x00,0x88,0x50,0x50,0x20,0x20,0x20,0x20,0x20,0x00,\r
+    0x00,0x00,0x00,0xf8,0x08,0x10,0x20,0x20,0x40,0x80,0xf8,0x00,\r
+    0x00,0x00,0x00,0xc0,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,\r
+    0x00,0x00,0x00,0x80,0x80,0x40,0x40,0x40,0x40,0x20,0x20,0x00,\r
+    0x00,0x00,0x00,0xc0,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,\r
+    0x00,0x00,0x00,0x40,0xa0,0xa0,0xa0,0x00,0x00,0x00,0x00,0x00,\r
+    0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xf8,\r
+    0x00,0x00,0x00,0x80,0x40,0x00,0x00,0x00,0x00,0x00,0x00,0x00,\r
+    0x00,0x00,0x00,0x00,0x00,0xe0,0x10,0x70,0x90,0x90,0x70,0x00,\r
+    0x00,0x00,0x00,0x80,0x80,0xa0,0xd0,0x90,0x90,0xd0,0xa0,0x00,\r
+    0x00,0x00,0x00,0x00,0x00,0x60,0x90,0x80,0x80,0x90,0x60,0x00,\r
+    0x00,0x00,0x00,0x10,0x10,0x50,0xb0,0x90,0x90,0xb0,0x50,0x00,\r
+    0x00,0x00,0x00,0x00,0x00,0x60,0x90,0xf0,0x80,0x90,0x60,0x00,\r
+    0x00,0x00,0x00,0xc0,0x80,0xc0,0x80,0x80,0x80,0x80,0x80,0x00,\r
+    0x00,0x00,0x00,0x00,0x00,0x50,0xb0,0x90,0x90,0xb0,0x50,0x10,\r
+    0x00,0x00,0x00,0x80,0x80,0xa0,0xd0,0x90,0x90,0x90,0x90,0x00,\r
+    0x00,0x00,0x00,0x80,0x00,0x80,0x80,0x80,0x80,0x80,0x80,0x00,\r
+    0x00,0x00,0x00,0x80,0x00,0x80,0x80,0x80,0x80,0x80,0x80,0x80,\r
+    0x00,0x00,0x00,0x80,0x80,0x90,0xa0,0xc0,0xa0,0x90,0x90,0x00,\r
+    0x00,0x00,0x00,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x00,\r
+    0x00,0x00,0x00,0x00,0x00,0xa6,0xda,0x92,0x92,0x92,0x92,0x00,\r
+    0x00,0x00,0x00,0x00,0x00,0xa0,0xd0,0x90,0x90,0x90,0x90,0x00,\r
+    0x00,0x00,0x00,0x00,0x00,0x60,0x90,0x90,0x90,0x90,0x60,0x00,\r
+    0x00,0x00,0x00,0x00,0x00,0xa0,0xd0,0x90,0x90,0xd0,0xa0,0x80,\r
+    0x00,0x00,0x00,0x00,0x00,0x50,0xb0,0x90,0x90,0xb0,0x50,0x10,\r
+    0x00,0x00,0x00,0x00,0x00,0xa0,0xc0,0x80,0x80,0x80,0x80,0x00,\r
+    0x00,0x00,0x00,0x00,0x00,0xe0,0x90,0x40,0x20,0x90,0x60,0x00,\r
+    0x00,0x00,0x00,0x80,0x80,0xc0,0x80,0x80,0x80,0x80,0xc0,0x00,\r
+    0x00,0x00,0x00,0x00,0x00,0x90,0x90,0x90,0x90,0xb0,0x50,0x00,\r
+    0x00,0x00,0x00,0x00,0x00,0x88,0x88,0x50,0x50,0x50,0x20,0x00,\r
+    0x00,0x00,0x00,0x00,0x00,0x92,0xaa,0xaa,0xaa,0xaa,0x44,0x00,\r
+    0x00,0x00,0x00,0x00,0x00,0x88,0x50,0x20,0x20,0x50,0x88,0x00,\r
+    0x00,0x00,0x00,0x00,0x00,0x88,0x50,0x50,0x50,0x20,0x20,0x20,\r
+    0x00,0x00,0x00,0x00,0x00,0xf0,0x10,0x20,0x40,0x80,0xf0,0x00,\r
+    0x00,0x00,0x00,0xc0,0x80,0x80,0x80,0x00,0x80,0x80,0x80,0x80,\r
+    0x00,0x00,0x00,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,\r
+    0x00,0x00,0x00,0xc0,0x40,0x40,0x40,0x20,0x40,0x40,0x40,0x40,\r
+    0x00,0x00,0x00,0x00,0x00,0x00,0xe8,0xb0,0x00,0x00,0x00,0x00,\r
+    0x00,0x00,0x00,0x00,0xe0,0xa0,0xa0,0xa0,0xa0,0xa0,0xe0,0x00};\r
+\r
+const uint16_t ASCII8x8_Table [] = {\r
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r
+    0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x40,\r
+    0xa0, 0xa0, 0xa0, 0x00, 0x00, 0x00, 0x00, 0x00,\r
+    0x00, 0x24, 0x24, 0xfe, 0x48, 0xfc, 0x48, 0x48,\r
+    0x38, 0x54, 0x50, 0x38, 0x14, 0x14, 0x54, 0x38,\r
+    0x44, 0xa8, 0xa8, 0x50, 0x14, 0x1a, 0x2a, 0x24,\r
+    0x10, 0x28, 0x28, 0x10, 0x74, 0x4c, 0x4c, 0x30,\r
+    0x10, 0x10, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00,\r
+    0x08, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x08,\r
+    0x10, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x10,\r
+    0x00, 0x00, 0x24, 0x18, 0x3c, 0x18, 0x24, 0x00,\r
+    0x00, 0x00, 0x10, 0x10, 0x7c, 0x10, 0x10, 0x00,\r
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x08, 0x10,\r
+    0x00, 0x00, 0x00, 0x00, 0x3c, 0x00, 0x00, 0x00,\r
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x18,\r
+    0x08, 0x08, 0x08, 0x10, 0x10, 0x20, 0x20, 0x20,\r
+    0x18, 0x24, 0x24, 0x24, 0x24, 0x24, 0x24, 0x18,\r
+    0x08, 0x18, 0x28, 0x08, 0x08, 0x08, 0x08, 0x08,\r
+    0x38, 0x44, 0x00, 0x04, 0x08, 0x10, 0x20, 0x7c,\r
+    0x18, 0x24, 0x04, 0x18, 0x04, 0x04, 0x24, 0x18,\r
+    0x04, 0x0c, 0x14, 0x24, 0x44, 0x7e, 0x04, 0x04,\r
+    0x3c, 0x20, 0x20, 0x38, 0x04, 0x04, 0x24, 0x18,\r
+    0x18, 0x24, 0x20, 0x38, 0x24, 0x24, 0x24, 0x18,\r
+    0x3c, 0x04, 0x08, 0x08, 0x08, 0x10, 0x10, 0x10,\r
+    0x18, 0x24, 0x24, 0x18, 0x24, 0x24, 0x24, 0x18,\r
+    0x18, 0x24, 0x24, 0x24, 0x1c, 0x04, 0x24, 0x18,\r
+    0x00, 0x00, 0x10, 0x00, 0x00, 0x10, 0x00, 0x00,\r
+    0x00, 0x00, 0x08, 0x00, 0x00, 0x08, 0x10, 0x00,\r
+    0x00, 0x00, 0x04, 0x18, 0x20, 0x18, 0x04, 0x00,\r
+    0x00, 0x00, 0x00, 0x3c, 0x00, 0x3c, 0x00, 0x00,\r
+    0x00, 0x00, 0x20, 0x18, 0x04, 0x18, 0x20, 0x00,\r
+    0x18, 0x24, 0x04, 0x08, 0x10, 0x10, 0x00, 0x10,\r
+    0x3c, 0x42, 0x99, 0xa5, 0xa5, 0x9d, 0x42, 0x38,\r
+    0x38, 0x44, 0x44, 0x44, 0x7c, 0x44, 0x44, 0x44,\r
+    0x78, 0x44, 0x44, 0x78, 0x44, 0x44, 0x44, 0x78,\r
+    0x1c, 0x22, 0x42, 0x40, 0x40, 0x42, 0x22, 0x1c,\r
+    0x70, 0x48, 0x44, 0x44, 0x44, 0x44, 0x48, 0x70,\r
+    0x7c, 0x40, 0x40, 0x7c, 0x40, 0x40, 0x40, 0x7c,\r
+    0x3c, 0x20, 0x20, 0x38, 0x20, 0x20, 0x20, 0x20,\r
+    0x1c, 0x22, 0x42, 0x40, 0x4e, 0x42, 0x22, 0x1c,\r
+    0x44, 0x44, 0x44, 0x7c, 0x44, 0x44, 0x44, 0x44,\r
+    0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,\r
+    0x04, 0x04, 0x04, 0x04, 0x04, 0x24, 0x24, 0x18,\r
+    0x44, 0x48, 0x50, 0x70, 0x50, 0x48, 0x48, 0x44,\r
+    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x3c,\r
+    0x82, 0xc6, 0xc6, 0xaa, 0xaa, 0xaa, 0xaa, 0x92,\r
+    0x42, 0x62, 0x52, 0x52, 0x4a, 0x4a, 0x46, 0x42,\r
+    0x18, 0x24, 0x42, 0x42, 0x42, 0x42, 0x24, 0x18,\r
+    0x78, 0x44, 0x44, 0x44, 0x78, 0x40, 0x40, 0x40,\r
+    0x18, 0x24, 0x42, 0x42, 0x42, 0x42, 0x2c, 0x1a,\r
+    0x78, 0x44, 0x44, 0x78, 0x50, 0x48, 0x44, 0x42,\r
+    0x38, 0x44, 0x40, 0x38, 0x04, 0x44, 0x44, 0x38,\r
+    0x7c, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,\r
+    0x42, 0x42, 0x42, 0x42, 0x42, 0x42, 0x24, 0x18,\r
+    0x44, 0x44, 0x28, 0x28, 0x28, 0x28, 0x28, 0x10,\r
+    0x92, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x44,\r
+    0x42, 0x24, 0x24, 0x18, 0x18, 0x24, 0x24, 0x42,\r
+    0x44, 0x28, 0x28, 0x10, 0x10, 0x10, 0x10, 0x10,\r
+    0x7c, 0x04, 0x08, 0x10, 0x10, 0x20, 0x40, 0x7c,\r
+    0x1c, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x1c,\r
+    0x10, 0x10, 0x08, 0x08, 0x08, 0x08, 0x04, 0x04,\r
+    0x1c, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x1c,\r
+    0x10, 0x28, 0x44, 0x00, 0x00, 0x00, 0x00, 0x00,\r
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r
+    0x20, 0x10, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00,\r
+    0x00, 0x00, 0x18, 0x04, 0x1c, 0x24, 0x24, 0x1c,\r
+    0x20, 0x20, 0x28, 0x34, 0x24, 0x24, 0x34, 0x28,\r
+    0x00, 0x00, 0x18, 0x24, 0x20, 0x20, 0x24, 0x18,\r
+    0x04, 0x04, 0x14, 0x2c, 0x24, 0x24, 0x2c, 0x14,\r
+    0x00, 0x00, 0x18, 0x24, 0x3c, 0x20, 0x24, 0x18,\r
+    0x00, 0x18, 0x10, 0x10, 0x18, 0x10, 0x10, 0x10,\r
+    0x00, 0x18, 0x24, 0x24, 0x18, 0x04, 0x24, 0x18,\r
+    0x20, 0x20, 0x28, 0x34, 0x24, 0x24, 0x24, 0x24,\r
+    0x10, 0x00, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,\r
+    0x08, 0x00, 0x08, 0x08, 0x08, 0x08, 0x28, 0x10,\r
+    0x20, 0x20, 0x24, 0x28, 0x30, 0x28, 0x24, 0x24,\r
+    0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,\r
+    0x00, 0x00, 0xa6, 0xda, 0x92, 0x92, 0x92, 0x92,\r
+    0x00, 0x00, 0x28, 0x34, 0x24, 0x24, 0x24, 0x24,\r
+    0x00, 0x00, 0x18, 0x24, 0x24, 0x24, 0x24, 0x18,\r
+    0x00, 0x28, 0x34, 0x24, 0x38, 0x20, 0x20, 0x20,\r
+    0x00, 0x14, 0x2c, 0x24, 0x1c, 0x04, 0x04, 0x04,\r
+    0x00, 0x00, 0x2c, 0x30, 0x20, 0x20, 0x20, 0x20,\r
+    0x00, 0x00, 0x18, 0x24, 0x10, 0x08, 0x24, 0x18,\r
+    0x00, 0x10, 0x38, 0x10, 0x10, 0x10, 0x10, 0x18,\r
+    0x00, 0x00, 0x24, 0x24, 0x24, 0x24, 0x2c, 0x14,\r
+    0x00, 0x00, 0x44, 0x44, 0x28, 0x28, 0x28, 0x10,\r
+    0x00, 0x00, 0x92, 0xaa, 0xaa, 0xaa, 0xaa, 0x44,\r
+    0x00, 0x00, 0x44, 0x28, 0x10, 0x10, 0x28, 0x44,\r
+    0x00, 0x28, 0x28, 0x28, 0x10, 0x10, 0x10, 0x10,\r
+    0x00, 0x00, 0x3c, 0x04, 0x08, 0x10, 0x20, 0x3c,\r
+    0x00, 0x08, 0x10, 0x10, 0x20, 0x10, 0x10, 0x08,\r
+    0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,\r
+    0x00, 0x10, 0x08, 0x08, 0x04, 0x08, 0x08, 0x10,\r
+    0x00, 0x00, 0x00, 0x60, 0x92, 0x0c, 0x00, 0x00,\r
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff};\r
+\r
+\r
+sFONT Font16x24 = {\r
+  ASCII16x24_Table,\r
+  16, /* Width */\r
+  24, /* Height */\r
+};\r
+\r
+sFONT Font12x12 = {\r
+  ASCII12x12_Table,\r
+  12, /* Width */\r
+  12, /* Height */\r
+};\r
+\r
+sFONT Font8x12 = {\r
+  ASCII8x12_Table,\r
+  8, /* Width */\r
+  12, /* Height */\r
+};\r
+\r
+\r
+sFONT Font8x8 = {\r
+  ASCII8x8_Table,\r
+  8, /* Width */\r
+  8, /* Height */\r
+};\r
+   \r
+/**\r
+  * @}\r
+  */ \r
+\r
+\r
+/** @defgroup FONTS_Private_Function_Prototypes\r
+  * @{\r
+  */ \r
+/**\r
+  * @}\r
+  */ \r
+\r
+\r
+/** @defgroup FONTS_Private_Functions\r
+  * @{\r
+  */\r
+    \r
+/**\r
+  * @}\r
+  */\r
+  \r
+/**\r
+  * @}\r
+  */ \r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */  \r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r

diff --git a/Demo/CORTEX_STM32L152_IAR/system_and_ST_code/Common/fonts.h b/Demo/CORTEX_STM32L152_IAR/system_and_ST_code/Common/fonts.h
new file mode 100644 (file)
index 0000000..00fa116
--- /dev/null
+++ b/Demo/CORTEX_STM32L152_IAR/system_and_ST_code/Common/fonts.h
@@ -0,0 +1,117 @@
+/**\r
+  ******************************************************************************\r
+  * @file    fonts.h\r
+  * @author  MCD Application Team\r
+  * @version V4.4.0RC1\r
+  * @date    07/02/2010\r
+  * @brief   Header for fonts.c\r
+  ******************************************************************************\r
+  * @copy\r
+  *\r
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+  *\r
+  * <h2><center>&copy; COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+  */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __FONTS_H\r
+#define __FONTS_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include <stdint.h>\r
+\r
+/** @addtogroup Utilities\r
+  * @{\r
+  */\r
+  \r
+/** @addtogroup STM32_EVAL\r
+  * @{\r
+  */ \r
+\r
+/** @addtogroup Common\r
+  * @{\r
+  */\r
+\r
+/** @addtogroup FONTS\r
+  * @{\r
+  */ \r
+\r
+/** @defgroup FONTS_Exported_Types\r
+  * @{\r
+  */ \r
+typedef struct _tFont\r
+{    \r
+  const uint16_t *table;\r
+  uint16_t Width;\r
+  uint16_t Height;\r
+  \r
+} sFONT;\r
+\r
+extern sFONT Font16x24;\r
+extern sFONT Font12x12;\r
+extern sFONT Font8x12;\r
+extern sFONT Font8x8;\r
+\r
+/**\r
+  * @}\r
+  */ \r
+\r
+/** @defgroup FONTS_Exported_Constants\r
+  * @{\r
+  */ \r
+#define LINE(x) ((x) * (((sFONT *)LCD_GetFont())->Height))\r
+\r
+/**\r
+  * @}\r
+  */ \r
+\r
+/** @defgroup FONTS_Exported_Macros\r
+  * @{\r
+  */ \r
+/**\r
+  * @}\r
+  */ \r
+\r
+/** @defgroup FONTS_Exported_Functions\r
+  * @{\r
+  */ \r
+/**\r
+  * @}\r
+  */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+  \r
+#endif /* __FONTS_H */\r
+ \r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */ \r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */      \r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r

diff --git a/Demo/CORTEX_STM32L152_IAR/system_and_ST_code/STM32L152_EVAL/stm32l152_eval.c b/Demo/CORTEX_STM32L152_IAR/system_and_ST_code/STM32L152_EVAL/stm32l152_eval.c
new file mode 100644 (file)
index 0000000..1f087a7
--- /dev/null
+++ b/Demo/CORTEX_STM32L152_IAR/system_and_ST_code/STM32L152_EVAL/stm32l152_eval.c
@@ -0,0 +1,584 @@
+/**\r
+  ******************************************************************************\r
+  * @file    stm32l152_eval.c\r
+  * @author  MCD Application Team\r
+  * @version V4.4.0RC1\r
+  * @date    07/02/2010\r
+  * @brief   This file provides\r
+  *            - set of firmware functions to manage Leds, push-button and COM ports\r
+  *            - low level initialization functions for SD card (on SPI) and\r
+  *              temperature sensor (LM75)\r
+  *          available on STM32L152-EVAL evaluation board from STMicroelectronics.\r
+  ******************************************************************************\r
+  * @copy\r
+  *\r
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+  *\r
+  * <h2><center>&copy; COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+  */ \r
+  \r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l152_eval.h"\r
+#include "stm32l1xx_spi.h"\r
+#include "stm32l1xx_i2c.h"\r
+\r
+/** @addtogroup Utilities\r
+  * @{\r
+  */ \r
+\r
+/** @addtogroup STM32_EVAL\r
+  * @{\r
+  */ \r
+\r
+/** @addtogroup STM32L152_EVAL\r
+  * @{\r
+  */   \r
+    \r
+/** @defgroup STM32L152_EVAL_LOW_LEVEL \r
+  * @brief This file provides firmware functions to manage Leds, push-buttons, \r
+  *        COM ports, SD card on SPI and temperature sensor (LM75) available on \r
+  *        STM32L152-EVAL evaluation board from STMicroelectronics.\r
+  * @{\r
+  */ \r
+\r
+/** @defgroup STM32L152_EVAL_LOW_LEVEL_Private_TypesDefinitions\r
+  * @{\r
+  */ \r
+/**\r
+  * @}\r
+  */ \r
+\r
+\r
+/** @defgroup STM32L152_EVAL_LOW_LEVEL_Private_Defines\r
+  * @{\r
+  */ \r
+/**\r
+  * @}\r
+  */ \r
+\r
+\r
+/** @defgroup STM32L152_EVAL_LOW_LEVEL_Private_Macros\r
+  * @{\r
+  */ \r
+/**\r
+  * @}\r
+  */ \r
+\r
+\r
+/** @defgroup STM32L152_EVAL_LOW_LEVEL_Private_Variables\r
+  * @{\r
+  */ \r
+GPIO_TypeDef* GPIO_PORT[LEDn] = {LED1_GPIO_PORT, LED2_GPIO_PORT, LED3_GPIO_PORT,\r
+                                 LED4_GPIO_PORT};\r
+const uint16_t GPIO_PIN[LEDn] = {LED1_PIN, LED2_PIN, LED3_PIN,\r
+                                 LED4_PIN};\r
+const uint32_t GPIO_CLK[LEDn] = {LED1_GPIO_CLK, LED2_GPIO_CLK, LED3_GPIO_CLK,\r
+                                 LED4_GPIO_CLK};\r
+\r
+GPIO_TypeDef* BUTTON_PORT[BUTTONn] = {WAKEUP_BUTTON_GPIO_PORT, TAMPER_BUTTON_GPIO_PORT,\r
+                                      KEY_BUTTON_GPIO_PORT, RIGHT_BUTTON_GPIO_PORT,\r
+                                      LEFT_BUTTON_GPIO_PORT, UP_BUTTON_GPIO_PORT,\r
+                                      DOWN_BUTTON_GPIO_PORT, SEL_BUTTON_GPIO_PORT}; \r
+\r
+const uint16_t BUTTON_PIN[BUTTONn] = {WAKEUP_BUTTON_PIN, TAMPER_BUTTON_PIN,\r
+                                      KEY_BUTTON_PIN, RIGHT_BUTTON_PIN,\r
+                                      LEFT_BUTTON_PIN, UP_BUTTON_PIN,\r
+                                      DOWN_BUTTON_PIN, SEL_BUTTON_PIN}; \r
+\r
+const uint32_t BUTTON_CLK[BUTTONn] = {WAKEUP_BUTTON_GPIO_CLK, TAMPER_BUTTON_GPIO_CLK,\r
+                                      KEY_BUTTON_GPIO_CLK, RIGHT_BUTTON_GPIO_CLK,\r
+                                      LEFT_BUTTON_GPIO_CLK, UP_BUTTON_GPIO_CLK,\r
+                                      DOWN_BUTTON_GPIO_CLK, SEL_BUTTON_GPIO_CLK};\r
+\r
+const uint16_t BUTTON_EXTI_LINE[BUTTONn] = {WAKEUP_BUTTON_EXTI_LINE,\r
+                                            TAMPER_BUTTON_EXTI_LINE, \r
+                                            KEY_BUTTON_EXTI_LINE,\r
+                                            RIGHT_BUTTON_EXTI_LINE,\r
+                                            LEFT_BUTTON_EXTI_LINE,\r
+                                            UP_BUTTON_EXTI_LINE,\r
+                                            DOWN_BUTTON_EXTI_LINE,\r
+                                            SEL_BUTTON_EXTI_LINE};\r
+\r
+const uint16_t BUTTON_PORT_SOURCE[BUTTONn] = {WAKEUP_BUTTON_EXTI_PORT_SOURCE,\r
+                                              TAMPER_BUTTON_EXTI_PORT_SOURCE, \r
+                                              KEY_BUTTON_EXTI_PORT_SOURCE,\r
+                                              RIGHT_BUTTON_EXTI_PORT_SOURCE,\r
+                                              LEFT_BUTTON_EXTI_PORT_SOURCE,\r
+                                              UP_BUTTON_EXTI_PORT_SOURCE,\r
+                                              DOWN_BUTTON_EXTI_PORT_SOURCE,\r
+                                              SEL_BUTTON_EXTI_PORT_SOURCE};\r
+                                                                \r
+const uint16_t BUTTON_PIN_SOURCE[BUTTONn] = {WAKEUP_BUTTON_EXTI_PIN_SOURCE,\r
+                                             TAMPER_BUTTON_EXTI_PIN_SOURCE, \r
+                                             KEY_BUTTON_EXTI_PIN_SOURCE,\r
+                                             RIGHT_BUTTON_EXTI_PIN_SOURCE,\r
+                                             LEFT_BUTTON_EXTI_PIN_SOURCE,\r
+                                             UP_BUTTON_EXTI_PIN_SOURCE,\r
+                                             DOWN_BUTTON_EXTI_PIN_SOURCE,\r
+                                             SEL_BUTTON_EXTI_PIN_SOURCE}; \r
+                                             \r
+const uint16_t BUTTON_IRQn[BUTTONn] = {WAKEUP_BUTTON_EXTI_IRQn, TAMPER_BUTTON_EXTI_IRQn,\r
+                                       KEY_BUTTON_EXTI_IRQn, RIGHT_BUTTON_EXTI_IRQn,\r
+                                       LEFT_BUTTON_EXTI_IRQn, UP_BUTTON_EXTI_IRQn,\r
+                                       DOWN_BUTTON_EXTI_IRQn, SEL_BUTTON_EXTI_IRQn};\r
+\r
+USART_TypeDef* COM_USART[COMn] = {EVAL_COM1, EVAL_COM2}; \r
+\r
+GPIO_TypeDef* COM_TX_PORT[COMn] = {EVAL_COM1_TX_GPIO_PORT, EVAL_COM2_TX_GPIO_PORT};\r
+ \r
+GPIO_TypeDef* COM_RX_PORT[COMn] = {EVAL_COM1_RX_GPIO_PORT, EVAL_COM2_RX_GPIO_PORT};\r
+\r
+const uint32_t COM_USART_CLK[COMn] = {EVAL_COM1_CLK, EVAL_COM2_CLK};\r
+\r
+const uint32_t COM_TX_PORT_CLK[COMn] = {EVAL_COM1_TX_GPIO_CLK, EVAL_COM2_TX_GPIO_CLK};\r
+ \r
+const uint32_t COM_RX_PORT_CLK[COMn] = {EVAL_COM1_RX_GPIO_CLK, EVAL_COM2_RX_GPIO_CLK};\r
+\r
+const uint16_t COM_TX_PIN[COMn] = {EVAL_COM1_TX_PIN, EVAL_COM2_TX_PIN};\r
+\r
+const uint16_t COM_RX_PIN[COMn] = {EVAL_COM1_RX_PIN, EVAL_COM2_RX_PIN};\r
+ \r
+const uint16_t COM_TX_PIN_SOURCE[COMn] = {EVAL_COM1_TX_SOURCE, EVAL_COM2_TX_SOURCE};\r
+\r
+const uint16_t COM_RX_PIN_SOURCE[COMn] = {EVAL_COM1_RX_SOURCE, EVAL_COM2_RX_SOURCE};\r
+ \r
+const uint16_t COM_TX_AF[COMn] = {EVAL_COM1_TX_AF, EVAL_COM2_TX_AF};\r
+ \r
+const uint16_t COM_RX_AF[COMn] = {EVAL_COM1_RX_AF, EVAL_COM2_RX_AF};\r
+\r
+/**\r
+  * @}\r
+  */ \r
+\r
+\r
+/** @defgroup STM32L152_EVAL_LOW_LEVEL_Private_FunctionPrototypes\r
+  * @{\r
+  */ \r
+\r
+/**\r
+  * @}\r
+  */ \r
+\r
+/** @defgroup STM32L152_EVAL_LOW_LEVEL_Private_Functions\r
+  * @{\r
+  */ \r
+\r
+/**\r
+  * @brief  Configures LED GPIO.\r
+  * @param  Led: Specifies the Led to be configured. \r
+  *   This parameter can be one of following parameters:\r
+  *     @arg LED1\r
+  *     @arg LED2\r
+  *     @arg LED3\r
+  *     @arg LED4\r
+  * @retval None\r
+  */\r
+void STM_EVAL_LEDInit(Led_TypeDef Led)\r
+{\r
+  GPIO_InitTypeDef  GPIO_InitStructure;\r
+  \r
+  /* Enable the GPIO_LED Clock */\r
+  RCC_AHBPeriphClockCmd(GPIO_CLK[Led], ENABLE);\r
+\r
+  /* Configure the GPIO_LED pin */\r
+  GPIO_InitStructure.GPIO_Pin = GPIO_PIN[Led];\r
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT;\r
+  GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;\r
+  GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;\r
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_40MHz;\r
+  GPIO_Init(GPIO_PORT[Led], &GPIO_InitStructure);\r
+  GPIO_PORT[Led]->BSRRL = GPIO_PIN[Led];\r
+}\r
+\r
+/**\r
+  * @brief  Turns selected LED On.\r
+  * @param  Led: Specifies the Led to be set on. \r
+  *   This parameter can be one of following parameters:\r
+  *     @arg LED1\r
+  *     @arg LED2\r
+  *     @arg LED3\r
+  *     @arg LED4  \r
+  * @retval None\r
+  */\r
+void STM_EVAL_LEDOn(Led_TypeDef Led)\r
+{\r
+  GPIO_PORT[Led]->BSRRH = GPIO_PIN[Led];\r
+}\r
+\r
+/**\r
+  * @brief  Turns selected LED Off.\r
+  * @param  Led: Specifies the Led to be set off. \r
+  *   This parameter can be one of following parameters:\r
+  *     @arg LED1\r
+  *     @arg LED2\r
+  *     @arg LED3\r
+  *     @arg LED4 \r
+  * @retval None\r
+  */\r
+void STM_EVAL_LEDOff(Led_TypeDef Led)\r
+{\r
+  GPIO_PORT[Led]->BSRRL = GPIO_PIN[Led];  \r
+}\r
+\r
+/**\r
+  * @brief  Toggles the selected LED.\r
+  * @param  Led: Specifies the Led to be toggled. \r
+  *   This parameter can be one of following parameters:\r
+  *     @arg LED1\r
+  *     @arg LED2\r
+  *     @arg LED3\r
+  *     @arg LED4  \r
+  * @retval None\r
+  */\r
+void STM_EVAL_LEDToggle(Led_TypeDef Led)\r
+{\r
+  GPIO_PORT[Led]->ODR ^= GPIO_PIN[Led];\r
+}\r
+\r
+/**\r
+  * @brief  Configures Button GPIO and EXTI Line.\r
+  * @param  Button: Specifies the Button to be configured.\r
+  *   This parameter can be one of following parameters:   \r
+  *     @arg BUTTON_WAKEUP: Wakeup Push Button\r
+  *     @arg BUTTON_TAMPER: Tamper Push Button  \r
+  *     @arg BUTTON_KEY: Key Push Button \r
+  *     @arg BUTTON_RIGHT: Joystick Right Push Button \r
+  *     @arg BUTTON_LEFT: Joystick Left Push Button \r
+  *     @arg BUTTON_UP: Joystick Up Push Button \r
+  *     @arg BUTTON_DOWN: Joystick Down Push Button\r
+  *     @arg BUTTON_SEL: Joystick Sel Push Button\r
+  * @param  Button_Mode: Specifies Button mode.\r
+  *   This parameter can be one of following parameters:   \r
+  *     @arg BUTTON_MODE_GPIO: Button will be used as simple IO \r
+  *     @arg BUTTON_MODE_EXTI: Button will be connected to EXTI line with interrupt\r
+  *                     generation capability  \r
+  * @retval None\r
+  */\r
+void STM_EVAL_PBInit(Button_TypeDef Button, ButtonMode_TypeDef Button_Mode)\r
+{\r
+  GPIO_InitTypeDef GPIO_InitStructure;\r
+  EXTI_InitTypeDef EXTI_InitStructure;\r
+  NVIC_InitTypeDef NVIC_InitStructure;\r
+\r
+  /* Enable the BUTTON Clock */\r
+  RCC_AHBPeriphClockCmd(BUTTON_CLK[Button], ENABLE);\r
+  RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);\r
+\r
+  /* Configure Button pin as input */\r
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN;\r
+  GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;\r
+  GPIO_InitStructure.GPIO_Pin = BUTTON_PIN[Button];\r
+  GPIO_Init(BUTTON_PORT[Button], &GPIO_InitStructure);\r
+\r
+\r
+  if (Button_Mode == BUTTON_MODE_EXTI)\r
+  {\r
+    /* Connect Button EXTI Line to Button GPIO Pin */\r
+    SYSCFG_EXTILineConfig(BUTTON_PORT_SOURCE[Button], BUTTON_PIN_SOURCE[Button]);\r
+\r
+    /* Configure Button EXTI line */\r
+    EXTI_InitStructure.EXTI_Line = BUTTON_EXTI_LINE[Button];\r
+    EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt;\r
+    \r
+    if((Button != BUTTON_WAKEUP) && (Button != BUTTON_KEY) && (Button != BUTTON_TAMPER))\r
+    {\r
+      EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Falling;  \r
+    }\r
+    else\r
+    {\r
+      EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising;  \r
+    }\r
+    EXTI_InitStructure.EXTI_LineCmd = ENABLE;\r
+    EXTI_Init(&EXTI_InitStructure);\r
+\r
+    /* Enable and set Button EXTI Interrupt to the lowest priority */\r
+    NVIC_InitStructure.NVIC_IRQChannel = BUTTON_IRQn[Button];\r
+    NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0x0F;\r
+    NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0x0F;\r
+    NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;\r
+\r
+    NVIC_Init(&NVIC_InitStructure); \r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  Returns the selected Button state.\r
+  * @param  Button: Specifies the Button to be checked.\r
+  *   This parameter can be one of following parameters:    \r
+  *     @arg BUTTON_WAKEUP: Wakeup Push Button\r
+  *     @arg BUTTON_TAMPER: Tamper Push Button  \r
+  *     @arg BUTTON_KEY: Key Push Button \r
+  *     @arg BUTTON_RIGHT: Joystick Right Push Button \r
+  *     @arg BUTTON_LEFT: Joystick Left Push Button \r
+  *     @arg BUTTON_UP: Joystick Up Push Button \r
+  *     @arg BUTTON_DOWN: Joystick Down Push Button\r
+  *     @arg BUTTON_SEL: Joystick Sel Push Button    \r
+  * @retval The Button GPIO pin value.\r
+  */\r
+uint32_t STM_EVAL_PBGetState(Button_TypeDef Button)\r
+{\r
+  return GPIO_ReadInputDataBit(BUTTON_PORT[Button], BUTTON_PIN[Button]);\r
+}\r
+\r
+\r
+/**\r
+  * @brief  Configures COM port.\r
+  * @param  COM: Specifies the COM port to be configured.\r
+  *   This parameter can be one of following parameters:    \r
+  *     @arg COM1\r
+  *     @arg COM2  \r
+  * @param  USART_InitStruct: pointer to a USART_InitTypeDef structure that\r
+  *   contains the configuration information for the specified USART peripheral.\r
+  * @retval None\r
+  */\r
+void STM_EVAL_COMInit(COM_TypeDef COM, USART_InitTypeDef* USART_InitStruct)\r
+{\r
+  GPIO_InitTypeDef GPIO_InitStructure;\r
+\r
+  /* Enable GPIO clock */\r
+  RCC_AHBPeriphClockCmd(COM_TX_PORT_CLK[COM] | COM_RX_PORT_CLK[COM], ENABLE);\r
+\r
+  /* Enable UART clock */\r
+  RCC_APB1PeriphClockCmd(COM_USART_CLK[COM], ENABLE);\r
+\r
+  /* Connect PXx to USARTx_Tx*/\r
+  GPIO_PinAFConfig(COM_TX_PORT[COM], COM_TX_PIN_SOURCE[COM], COM_TX_AF[COM]);\r
+\r
+  /* Connect PXx to USARTx_Rx*/\r
+  GPIO_PinAFConfig(COM_RX_PORT[COM], COM_RX_PIN_SOURCE[COM], COM_RX_AF[COM]);\r
+  \r
+  /* Configure USART Tx as alternate function push-pull */\r
+  GPIO_InitStructure.GPIO_Pin = COM_TX_PIN[COM];\r
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;\r
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_40MHz;\r
+  GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;\r
+  GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;\r
+  GPIO_Init(COM_TX_PORT[COM], &GPIO_InitStructure);\r
+    \r
+  /* Configure USART Rx as input floating */\r
+  GPIO_InitStructure.GPIO_Pin = COM_RX_PIN[COM];\r
+  GPIO_Init(COM_RX_PORT[COM], &GPIO_InitStructure);\r
+\r
+  /* USART configuration */\r
+  USART_Init(COM_USART[COM], USART_InitStruct);\r
+    \r
+  /* Enable USART */\r
+  USART_Cmd(COM_USART[COM], ENABLE);\r
+}\r
+\r
+/**\r
+  * @brief  DeInitializes the SPI interface.\r
+  * @param  None\r
+  * @retval None\r
+  */\r
+void SD_LowLevel_DeInit(void)\r
+{\r
+  GPIO_InitTypeDef  GPIO_InitStructure;\r
+  \r
+  SPI_Cmd(SD_SPI, DISABLE); /*!< SD_SPI disable */\r
+  SPI_DeInit(SD_SPI);   /*!< DeInitializes the SD_SPI */\r
+  \r
+  /*!< SD_SPI Periph clock disable */\r
+  RCC_APB1PeriphClockCmd(SD_SPI_CLK, DISABLE); \r
+\r
+  /*!< Configure SD_SPI pins: SCK */\r
+  GPIO_InitStructure.GPIO_Pin = SD_SPI_SCK_PIN;\r
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN;\r
+  GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;\r
+  GPIO_Init(SD_SPI_SCK_GPIO_PORT, &GPIO_InitStructure);\r
+\r
+  /*!< Configure SD_SPI pins: MISO */\r
+  GPIO_InitStructure.GPIO_Pin = SD_SPI_MISO_PIN;\r
+  GPIO_Init(SD_SPI_MISO_GPIO_PORT, &GPIO_InitStructure);\r
+\r
+  /*!< Configure SD_SPI pins: MOSI */\r
+  GPIO_InitStructure.GPIO_Pin = SD_SPI_MOSI_PIN;\r
+  GPIO_Init(SD_SPI_MOSI_GPIO_PORT, &GPIO_InitStructure);\r
+\r
+  /*!< Configure SD_SPI_CS_PIN pin: SD Card CS pin */\r
+  GPIO_InitStructure.GPIO_Pin = SD_CS_PIN;\r
+  GPIO_Init(SD_CS_GPIO_PORT, &GPIO_InitStructure);\r
+\r
+  /*!< Configure SD_SPI_DETECT_PIN pin: SD Card detect pin */\r
+  GPIO_InitStructure.GPIO_Pin = SD_DETECT_PIN;\r
+  GPIO_Init(SD_DETECT_GPIO_PORT, &GPIO_InitStructure);\r
+}\r
+\r
+/**\r
+  * @brief  Initializes the SD Card and put it into StandBy State (Ready for \r
+  *         data transfer).\r
+  * @param  None\r
+  * @retval None\r
+  */\r
+void SD_LowLevel_Init(void)\r
+{\r
+  GPIO_InitTypeDef  GPIO_InitStructure;\r
+  SPI_InitTypeDef   SPI_InitStructure;\r
+\r
+  /*!< SD_SPI_CS_GPIO, SD_SPI_MOSI_GPIO, SD_SPI_MISO_GPIO, SD_SPI_DETECT_GPIO \r
+       and SD_SPI_SCK_GPIO Periph clock enable */\r
+  RCC_AHBPeriphClockCmd(SD_CS_GPIO_CLK | SD_SPI_MOSI_GPIO_CLK | SD_SPI_MISO_GPIO_CLK |\r
+                        SD_SPI_SCK_GPIO_CLK | SD_DETECT_GPIO_CLK, ENABLE);\r
+\r
+  /*!< SD_SPI Periph clock enable */\r
+  RCC_APB1PeriphClockCmd(SD_SPI_CLK, ENABLE); \r
+\r
+  /*!< Configure SD_SPI pins: SCK */\r
+  GPIO_InitStructure.GPIO_Pin = SD_SPI_SCK_PIN;\r
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;\r
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_40MHz;\r
+  GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;\r
+  GPIO_InitStructure.GPIO_PuPd  = GPIO_PuPd_UP;\r
+  GPIO_Init(SD_SPI_SCK_GPIO_PORT, &GPIO_InitStructure);\r
+\r
+  /*!< Configure SD_SPI pins: MISO */\r
+  GPIO_InitStructure.GPIO_Pin = SD_SPI_MISO_PIN;\r
+  GPIO_Init(SD_SPI_MISO_GPIO_PORT, &GPIO_InitStructure);\r
+\r
+  /*!< Configure SD_SPI pins: MOSI */\r
+  GPIO_InitStructure.GPIO_Pin = SD_SPI_MOSI_PIN;\r
+  GPIO_Init(SD_SPI_MOSI_GPIO_PORT, &GPIO_InitStructure);\r
+\r
+  /*!< Configure SD_SPI_CS_PIN pin: SD Card CS pin */\r
+  GPIO_InitStructure.GPIO_Pin = SD_CS_PIN;\r
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT;\r
+  GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;\r
+  GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;\r
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_40MHz;\r
+  GPIO_Init(SD_CS_GPIO_PORT, &GPIO_InitStructure);\r
+\r
+  /*!< Configure SD_SPI_DETECT_PIN pin: SD Card detect pin */\r
+  GPIO_InitStructure.GPIO_Pin = SD_DETECT_PIN;\r
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN;\r
+  GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;\r
+  GPIO_Init(SD_DETECT_GPIO_PORT, &GPIO_InitStructure);\r
+\r
+  /* Connect PXx to SD_SPI_SCK */\r
+  GPIO_PinAFConfig(SD_SPI_SCK_GPIO_PORT, SD_SPI_SCK_SOURCE, SD_SPI_SCK_AF);\r
+\r
+  /* Connect PXx to SD_SPI_MISO */\r
+  GPIO_PinAFConfig(SD_SPI_MISO_GPIO_PORT, SD_SPI_MISO_SOURCE, SD_SPI_MISO_AF); \r
+\r
+  /* Connect PXx to SD_SPI_MOSI */\r
+  GPIO_PinAFConfig(SD_SPI_MOSI_GPIO_PORT, SD_SPI_MOSI_SOURCE, SD_SPI_MOSI_AF);  \r
+  \r
+  /*!< SD_SPI Config */\r
+  SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex;\r
+  SPI_InitStructure.SPI_Mode = SPI_Mode_Master;\r
+  SPI_InitStructure.SPI_DataSize = SPI_DataSize_8b;\r
+  SPI_InitStructure.SPI_CPOL = SPI_CPOL_High;\r
+  SPI_InitStructure.SPI_CPHA = SPI_CPHA_2Edge;\r
+  SPI_InitStructure.SPI_NSS = SPI_NSS_Soft;\r
+  SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2;\r
+\r
+  SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB;\r
+  SPI_InitStructure.SPI_CRCPolynomial = 7;\r
+  SPI_Init(SD_SPI, &SPI_InitStructure);\r
+  \r
+  SPI_Cmd(SD_SPI, ENABLE); /*!< SD_SPI enable */\r
+}\r
+\r
+/**\r
+  * @brief  DeInitializes the LM75_I2C.\r
+  * @param  None\r
+  * @retval None\r
+  */\r
+void LM75_LowLevel_DeInit(void)\r
+{ \r
+  GPIO_InitTypeDef  GPIO_InitStructure;\r
+\r
+  /*!< Disable LM75_I2C */\r
+  I2C_Cmd(LM75_I2C, DISABLE);\r
+  \r
+  /*!< DeInitializes the LM75_I2C */\r
+  I2C_DeInit(LM75_I2C);\r
+  \r
+  /*!< LM75_I2C Periph clock disable */\r
+  RCC_APB1PeriphClockCmd(LM75_I2C_CLK, DISABLE);\r
+    \r
+  /*!< Configure LM75_I2C pins: SCL */\r
+  GPIO_InitStructure.GPIO_Pin = LM75_I2C_SCL_PIN;\r
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN;\r
+  GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;\r
+  GPIO_Init(LM75_I2C_SCL_GPIO_PORT, &GPIO_InitStructure);\r
+\r
+  /*!< Configure LM75_I2C pins: SDA */\r
+  GPIO_InitStructure.GPIO_Pin = LM75_I2C_SDA_PIN;\r
+  GPIO_Init(LM75_I2C_SDA_GPIO_PORT, &GPIO_InitStructure);\r
+\r
+  /*!< Configure LM75_I2C pin: SMBUS ALERT */\r
+  GPIO_InitStructure.GPIO_Pin = LM75_I2C_SMBUSALERT_PIN;\r
+  GPIO_Init(LM75_I2C_SMBUSALERT_GPIO_PORT, &GPIO_InitStructure);\r
+}\r
+\r
+/**\r
+  * @brief  Initializes the LM75_I2C.\r
+  * @param  None\r
+  * @retval None\r
+  */\r
+void LM75_LowLevel_Init(void)\r
+{ \r
+  GPIO_InitTypeDef  GPIO_InitStructure;\r
+\r
+  /*!< LM75_I2C Periph clock enable */\r
+  RCC_APB1PeriphClockCmd(LM75_I2C_CLK, ENABLE);\r
+    \r
+  /*!< LM75_I2C_SCL_GPIO_CLK, LM75_I2C_SDA_GPIO_CLK \r
+       and LM75_I2C_SMBUSALERT_GPIO_CLK Periph clock enable */\r
+  RCC_AHBPeriphClockCmd(LM75_I2C_SCL_GPIO_CLK | LM75_I2C_SDA_GPIO_CLK |\r
+                        LM75_I2C_SMBUSALERT_GPIO_CLK, ENABLE);\r
+  \r
+  /*!< Configure LM75_I2C pins: SCL */\r
+  GPIO_InitStructure.GPIO_Pin = LM75_I2C_SCL_PIN;\r
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;\r
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_40MHz;\r
+  GPIO_InitStructure.GPIO_OType = GPIO_OType_OD;\r
+  GPIO_InitStructure.GPIO_PuPd  = GPIO_PuPd_NOPULL;\r
+  GPIO_Init(LM75_I2C_SCL_GPIO_PORT, &GPIO_InitStructure);\r
+\r
+  /*!< Configure LM75_I2C pins: SDA */\r
+  GPIO_InitStructure.GPIO_Pin = LM75_I2C_SDA_PIN;\r
+  GPIO_Init(LM75_I2C_SDA_GPIO_PORT, &GPIO_InitStructure);\r
+\r
+  /*!< Configure LM75_I2C pin: SMBUS ALERT */\r
+  GPIO_InitStructure.GPIO_Pin = LM75_I2C_SMBUSALERT_PIN;\r
+  GPIO_Init(LM75_I2C_SMBUSALERT_GPIO_PORT, &GPIO_InitStructure);\r
+\r
+\r
+  /* Connect PXx to I2C_SCL */\r
+  GPIO_PinAFConfig(LM75_I2C_SCL_GPIO_PORT, LM75_I2C_SCL_SOURCE, LM75_I2C_SCL_AF);\r
+\r
+  /* Connect PXx to I2C_SDA */\r
+  GPIO_PinAFConfig(LM75_I2C_SDA_GPIO_PORT, LM75_I2C_SDA_SOURCE, LM75_I2C_SDA_AF); \r
+\r
+  /* Connect PXx to I2C_SMBUSALER */\r
+  GPIO_PinAFConfig(LM75_I2C_SMBUSALERT_GPIO_PORT, LM75_I2C_SMBUSALERT_SOURCE, LM75_I2C_SMBUSALERT_AF);     \r
+}\r
+\r
+/**\r
+  * @}\r
+  */ \r
+\r
+\r
+/**\r
+  * @}\r
+  */ \r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */    \r
+\r
+/**\r
+  * @}\r
+  */ \r
+    \r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r

diff --git a/Demo/CORTEX_STM32L152_IAR/system_and_ST_code/STM32L152_EVAL/stm32l152_eval.h b/Demo/CORTEX_STM32L152_IAR/system_and_ST_code/STM32L152_EVAL/stm32l152_eval.h
new file mode 100644 (file)
index 0000000..56df0fb
--- /dev/null
+++ b/Demo/CORTEX_STM32L152_IAR/system_and_ST_code/STM32L152_EVAL/stm32l152_eval.h
@@ -0,0 +1,337 @@
+/**\r
+  ******************************************************************************\r
+  * @file    stm32l152_eval.h\r
+  * @author  MCD Application Team\r
+  * @version V4.4.0RC1\r
+  * @date    07/02/2010\r
+  * @brief   This file contains definitions for STM32L152_EVAL's Leds, push-buttons\r
+  *          and COM ports hardware resources.\r
+  ******************************************************************************\r
+  * @copy\r
+  *\r
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+  *\r
+  * <h2><center>&copy; COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+  */ \r
+  \r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32L152_EVAL_H\r
+#define __STM32L152_EVAL_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32_eval.h"\r
+\r
+/** @addtogroup Utilities\r
+  * @{\r
+  */\r
+\r
+/** @addtogroup STM32_EVAL\r
+  * @{\r
+  */\r
+\r
+/** @addtogroup STM32L152_EVAL\r
+  * @{\r
+  */\r
+      \r
+/** @addtogroup STM32L152_EVAL_LOW_LEVEL\r
+  * @{\r
+  */ \r
+\r
+/** @defgroup STM32L152_EVAL_LOW_LEVEL_Exported_Types\r
+  * @{\r
+  */\r
+/**\r
+  * @}\r
+  */ \r
+\r
+/** @defgroup STM32L152_EVAL_LOW_LEVEL_Exported_Constants\r
+  * @{\r
+  */ \r
+\r
+/** @addtogroup STM32L152_EVAL_LOW_LEVEL_LED\r
+  * @{\r
+  */\r
+#define LEDn                             4\r
+\r
+#define LED1_PIN                         GPIO_Pin_0\r
+#define LED1_GPIO_PORT                   GPIOD\r
+#define LED1_GPIO_CLK                    RCC_AHBPeriph_GPIOD  \r
+  \r
+#define LED2_PIN                         GPIO_Pin_1\r
+#define LED2_GPIO_PORT                   GPIOD\r
+#define LED2_GPIO_CLK                    RCC_AHBPeriph_GPIOD  \r
+  \r
+#define LED3_PIN                         GPIO_Pin_4\r
+#define LED3_GPIO_PORT                   GPIOD\r
+#define LED3_GPIO_CLK                    RCC_AHBPeriph_GPIOD  \r
+  \r
+#define LED4_PIN                         GPIO_Pin_5\r
+#define LED4_GPIO_PORT                   GPIOD\r
+#define LED4_GPIO_CLK                    RCC_AHBPeriph_GPIOD\r
+\r
+/**\r
+  * @}\r
+  */ \r
+  \r
+/** @addtogroup STM32L152_EVAL_LOW_LEVEL_BUTTON\r
+  * @{\r
+  */  \r
+#define BUTTONn                          8 \r
+\r
+/**\r
+ * @brief Wakeup push-button\r
+ */\r
+#define WAKEUP_BUTTON_PIN                GPIO_Pin_13\r
+#define WAKEUP_BUTTON_GPIO_PORT          GPIOC\r
+#define WAKEUP_BUTTON_GPIO_CLK           RCC_AHBPeriph_GPIOC\r
+#define WAKEUP_BUTTON_EXTI_LINE          EXTI_Line13\r
+#define WAKEUP_BUTTON_EXTI_PORT_SOURCE   EXTI_PortSourceGPIOC\r
+#define WAKEUP_BUTTON_EXTI_PIN_SOURCE    EXTI_PinSource13\r
+#define WAKEUP_BUTTON_EXTI_IRQn          EXTI15_10_IRQn \r
+\r
+/**\r
+ * @brief Tamper push-button\r
+ */\r
+#define TAMPER_BUTTON_PIN                GPIO_Pin_13\r
+#define TAMPER_BUTTON_GPIO_PORT          GPIOC\r
+#define TAMPER_BUTTON_GPIO_CLK           RCC_AHBPeriph_GPIOC\r
+#define TAMPER_BUTTON_EXTI_LINE          EXTI_Line13\r
+#define TAMPER_BUTTON_EXTI_PORT_SOURCE   EXTI_PortSourceGPIOC\r
+#define TAMPER_BUTTON_EXTI_PIN_SOURCE    EXTI_PinSource13\r
+#define TAMPER_BUTTON_EXTI_IRQn          EXTI15_10_IRQn \r
+\r
+/**\r
+ * @brief Key push-button\r
+ */\r
+#define KEY_BUTTON_PIN                   GPIO_Pin_13\r
+#define KEY_BUTTON_GPIO_PORT             GPIOC\r
+#define KEY_BUTTON_GPIO_CLK              RCC_AHBPeriph_GPIOC\r
+#define KEY_BUTTON_EXTI_LINE             EXTI_Line13\r
+#define KEY_BUTTON_EXTI_PORT_SOURCE      EXTI_PortSourceGPIOC\r
+#define KEY_BUTTON_EXTI_PIN_SOURCE       EXTI_PinSource13\r
+#define KEY_BUTTON_EXTI_IRQn             EXTI15_10_IRQn\r
+\r
+/**\r
+ * @brief Joystick Right push-button\r
+ */\r
+#define RIGHT_BUTTON_PIN                 GPIO_Pin_11\r
+#define RIGHT_BUTTON_GPIO_PORT           GPIOE\r
+#define RIGHT_BUTTON_GPIO_CLK            RCC_AHBPeriph_GPIOE\r
+#define RIGHT_BUTTON_EXTI_LINE           EXTI_Line11\r
+#define RIGHT_BUTTON_EXTI_PORT_SOURCE    EXTI_PortSourceGPIOE\r
+#define RIGHT_BUTTON_EXTI_PIN_SOURCE     EXTI_PinSource11\r
+#define RIGHT_BUTTON_EXTI_IRQn           EXTI15_10_IRQn\r
+\r
+/**\r
+ * @brief Joystick Left push-button\r
+ */\r
+#define LEFT_BUTTON_PIN                  GPIO_Pin_12\r
+#define LEFT_BUTTON_GPIO_PORT            GPIOE\r
+#define LEFT_BUTTON_GPIO_CLK             RCC_AHBPeriph_GPIOE\r
+#define LEFT_BUTTON_EXTI_LINE            EXTI_Line12\r
+#define LEFT_BUTTON_EXTI_PORT_SOURCE     EXTI_PortSourceGPIOE\r
+#define LEFT_BUTTON_EXTI_PIN_SOURCE      EXTI_PinSource12\r
+#define LEFT_BUTTON_EXTI_IRQn            EXTI15_10_IRQn  \r
+\r
+/**\r
+ * @brief Joystick Up push-button\r
+ */\r
+#define UP_BUTTON_PIN                    GPIO_Pin_9\r
+#define UP_BUTTON_GPIO_PORT              GPIOE\r
+#define UP_BUTTON_GPIO_CLK               RCC_AHBPeriph_GPIOE\r
+#define UP_BUTTON_EXTI_LINE              EXTI_Line9\r
+#define UP_BUTTON_EXTI_PORT_SOURCE       EXTI_PortSourceGPIOE\r
+#define UP_BUTTON_EXTI_PIN_SOURCE        EXTI_PinSource9\r
+#define UP_BUTTON_EXTI_IRQn              EXTI9_5_IRQn  \r
+\r
+/**\r
+ * @brief Joystick Down push-button\r
+ */  \r
+#define DOWN_BUTTON_PIN                  GPIO_Pin_10\r
+#define DOWN_BUTTON_GPIO_PORT            GPIOE\r
+#define DOWN_BUTTON_GPIO_CLK             RCC_AHBPeriph_GPIOE\r
+#define DOWN_BUTTON_EXTI_LINE            EXTI_Line10\r
+#define DOWN_BUTTON_EXTI_PORT_SOURCE     EXTI_PortSourceGPIOE\r
+#define DOWN_BUTTON_EXTI_PIN_SOURCE      EXTI_PinSource10\r
+#define DOWN_BUTTON_EXTI_IRQn            EXTI15_10_IRQn  \r
+\r
+/**\r
+ * @brief Joystick Sel push-button\r
+ */\r
+#define SEL_BUTTON_PIN                   GPIO_Pin_8\r
+#define SEL_BUTTON_GPIO_PORT             GPIOE\r
+#define SEL_BUTTON_GPIO_CLK              RCC_AHBPeriph_GPIOE\r
+#define SEL_BUTTON_EXTI_LINE             EXTI_Line8\r
+#define SEL_BUTTON_EXTI_PORT_SOURCE      EXTI_PortSourceGPIOE\r
+#define SEL_BUTTON_EXTI_PIN_SOURCE       EXTI_PinSource8\r
+#define SEL_BUTTON_EXTI_IRQn             EXTI9_5_IRQn \r
+\r
+/**\r
+  * @}\r
+  */ \r
+\r
+/** @addtogroup STM32L152_EVAL_LOW_LEVEL_COM\r
+  * @{\r
+  */\r
+#define COMn                             2\r
+\r
+/**\r
+ * @brief Definition for COM port1, connected to USART2\r
+ */ \r
+#define EVAL_COM1                        USART2\r
+#define EVAL_COM1_CLK                    RCC_APB1Periph_USART2\r
+#define EVAL_COM1_TX_PIN                 GPIO_Pin_5\r
+#define EVAL_COM1_TX_GPIO_PORT           GPIOD\r
+#define EVAL_COM1_TX_GPIO_CLK            RCC_AHBPeriph_GPIOD\r
+#define EVAL_COM1_TX_SOURCE              GPIO_PinSource5\r
+#define EVAL_COM1_TX_AF                  GPIO_AF_USART2\r
+#define EVAL_COM1_RX_PIN                 GPIO_Pin_6\r
+#define EVAL_COM1_RX_GPIO_PORT           GPIOD\r
+#define EVAL_COM1_RX_GPIO_CLK            RCC_AHBPeriph_GPIOD\r
+#define EVAL_COM1_RX_SOURCE              GPIO_PinSource6\r
+#define EVAL_COM1_RX_AF                  GPIO_AF_USART2\r
+#define EVAL_COM1_IRQn                   USART2_IRQn\r
+\r
+/**\r
+ * @brief Definition for COM port2, connected to USART3\r
+ */ \r
+#define EVAL_COM2                        USART3\r
+#define EVAL_COM2_CLK                    RCC_APB1Periph_USART3\r
+\r
+#define EVAL_COM2_TX_PIN                 GPIO_Pin_10\r
+#define EVAL_COM2_TX_GPIO_PORT           GPIOC\r
+#define EVAL_COM2_TX_GPIO_CLK            RCC_AHBPeriph_GPIOC\r
+#define EVAL_COM2_TX_SOURCE              GPIO_PinSource10\r
+#define EVAL_COM2_TX_AF                  GPIO_AF_USART3\r
+\r
+#define EVAL_COM2_RX_PIN                 GPIO_Pin_11\r
+#define EVAL_COM2_RX_GPIO_PORT           GPIOC\r
+#define EVAL_COM2_RX_GPIO_CLK            RCC_AHBPeriph_GPIOC\r
+#define EVAL_COM2_RX_SOURCE              GPIO_PinSource11\r
+#define EVAL_COM2_RX_AF                  GPIO_AF_USART3\r
+#define EVAL_COM2_IRQn                   USART3_IRQn\r
+\r
+/**\r
+  * @}\r
+  */ \r
+\r
+/** @addtogroup STM32L152_EVAL_LOW_LEVEL_SD_FLASH\r
+  * @{\r
+  */ \r
+/**\r
+  * @brief  SD Card SPI Interface\r
+  */  \r
+#define SD_SPI                           SPI2\r
+#define SD_SPI_CLK                       RCC_APB1Periph_SPI2\r
+#define SD_SPI_SCK_PIN                   GPIO_Pin_13                 /* PB.13 */\r
+#define SD_SPI_SCK_GPIO_PORT             GPIOB                       /* GPIOB */\r
+#define SD_SPI_SCK_GPIO_CLK              RCC_AHBPeriph_GPIOB\r
+#define SD_SPI_SCK_SOURCE                GPIO_PinSource13\r
+#define SD_SPI_SCK_AF                    GPIO_AF_SPI2\r
+#define SD_SPI_MISO_PIN                  GPIO_Pin_14                 /* PB.14 */\r
+#define SD_SPI_MISO_GPIO_PORT            GPIOB                       /* GPIOB */\r
+#define SD_SPI_MISO_GPIO_CLK             RCC_AHBPeriph_GPIOB\r
+#define SD_SPI_MISO_SOURCE               GPIO_PinSource14\r
+#define SD_SPI_MISO_AF                   GPIO_AF_SPI2\r
+#define SD_SPI_MOSI_PIN                  GPIO_Pin_15                 /* PB.15 */\r
+#define SD_SPI_MOSI_GPIO_PORT            GPIOB                       /* GPIOB */\r
+#define SD_SPI_MOSI_GPIO_CLK             RCC_AHBPeriph_GPIOB\r
+#define SD_SPI_MOSI_SOURCE               GPIO_PinSource15\r
+#define SD_SPI_MOSI_AF                   GPIO_AF_SPI2\r
+#define SD_CS_PIN                        GPIO_Pin_7                  /* PD.07 */\r
+#define SD_CS_GPIO_PORT                  GPIOD                       /* GPIOD */\r
+#define SD_CS_GPIO_CLK                   RCC_AHBPeriph_GPIOD\r
+#define SD_DETECT_PIN                    GPIO_Pin_7                  /* PE.07 */\r
+#define SD_DETECT_GPIO_PORT              GPIOE                       /* GPIOE */\r
+#define SD_DETECT_GPIO_CLK               RCC_AHBPeriph_GPIOE\r
+/**\r
+  * @}\r
+  */ \r
+  \r
+/** @addtogroup STM32L152_EVAL_LOW_LEVEL_TSENSOR_I2C\r
+  * @{\r
+  */\r
+/**\r
+  * @brief  LM75 Temperature Sensor I2C Interface pins\r
+  */  \r
+#define LM75_I2C                         I2C1\r
+#define LM75_I2C_CLK                     RCC_APB1Periph_I2C1\r
+#define LM75_I2C_SCL_PIN                 GPIO_Pin_6                  /* PB.06 */\r
+#define LM75_I2C_SCL_GPIO_PORT           GPIOB                       /* GPIOB */\r
+#define LM75_I2C_SCL_GPIO_CLK            RCC_AHBPeriph_GPIOB\r
+#define LM75_I2C_SCL_SOURCE              GPIO_PinSource6\r
+#define LM75_I2C_SCL_AF                  GPIO_AF_I2C1\r
+#define LM75_I2C_SDA_PIN                 GPIO_Pin_7                  /* PB.07 */\r
+#define LM75_I2C_SDA_GPIO_PORT           GPIOB                       /* GPIOB */\r
+#define LM75_I2C_SDA_GPIO_CLK            RCC_AHBPeriph_GPIOB\r
+#define LM75_I2C_SDA_SOURCE              GPIO_PinSource7\r
+#define LM75_I2C_SDA_AF                  GPIO_AF_I2C1\r
+#define LM75_I2C_SMBUSALERT_PIN          GPIO_Pin_5                  /* PB.05 */\r
+#define LM75_I2C_SMBUSALERT_GPIO_PORT    GPIOB                       /* GPIOB */\r
+#define LM75_I2C_SMBUSALERT_GPIO_CLK     RCC_AHBPeriph_GPIOB\r
+#define LM75_I2C_SMBUSALERT_SOURCE       GPIO_PinSource5\r
+#define LM75_I2C_SMBUSALERT_AF           GPIO_AF_I2C1\r
+/**\r
+  * @}\r
+  */  \r
+/**\r
+  * @}\r
+  */ \r
+  \r
+/** @defgroup STM32L152_EVAL_LOW_LEVEL_Exported_Macros\r
+  * @{\r
+  */  \r
+/**\r
+  * @}\r
+  */ \r
+\r
+\r
+/** @defgroup STM32L152_EVAL_LOW_LEVEL_Exported_Functions\r
+  * @{\r
+  */\r
+void STM_EVAL_LEDInit(Led_TypeDef Led);\r
+void STM_EVAL_LEDOn(Led_TypeDef Led);\r
+void STM_EVAL_LEDOff(Led_TypeDef Led);\r
+void STM_EVAL_LEDToggle(Led_TypeDef Led);\r
+void STM_EVAL_PBInit(Button_TypeDef Button, ButtonMode_TypeDef Button_Mode);\r
+uint32_t STM_EVAL_PBGetState(Button_TypeDef Button);\r
+void STM_EVAL_COMInit(COM_TypeDef COM, USART_InitTypeDef* USART_InitStruct); \r
+void SD_LowLevel_DeInit(void);\r
+void SD_LowLevel_Init(void); \r
+void LM75_LowLevel_DeInit(void);\r
+void LM75_LowLevel_Init(void);  \r
+/**\r
+  * @}\r
+  */\r
+  \r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32L152_EVAL_H */\r
+/**\r
+  * @}\r
+  */ \r
+\r
+/**\r
+  * @}\r
+  */ \r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */  \r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r

diff --git a/Demo/CORTEX_STM32L152_IAR/system_and_ST_code/STM32L152_EVAL/stm32l152_eval_lcd.c b/Demo/CORTEX_STM32L152_IAR/system_and_ST_code/STM32L152_EVAL/stm32l152_eval_lcd.c
new file mode 100644 (file)
index 0000000..8c3f05a
--- /dev/null
+++ b/Demo/CORTEX_STM32L152_IAR/system_and_ST_code/STM32L152_EVAL/stm32l152_eval_lcd.c
@@ -0,0 +1,1528 @@
+/**\r
+  ******************************************************************************\r
+  * @file    stm32l152_eval_lcd.c\r
+  * @author  MCD Application Team\r
+  * @version V4.4.0RC1\r
+  * @date    07/02/2010\r
+  * @brief   This file includes the LCD driver for AM-240320L8TNQW00H (LCD_ILI9320),\r
+  *          AM-240320LDTNQW00H (LCD_SPFD5408B) Liquid Crystal Display Module\r
+  *          of STM32L152-EVAL board.\r
+  ******************************************************************************\r
+  * @copy\r
+  *\r
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+  *\r
+  * <h2><center>&copy; COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+  */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l152_eval_lcd.h"\r
+#include "../Common/fonts.c"\r
+\r
+/** @addtogroup Utilities\r
+  * @{\r
+  */\r
+\r
+/** @addtogroup STM32_EVAL\r
+  * @{\r
+  */\r
+\r
+/** @addtogroup STM32L152_EVAL\r
+  * @{\r
+  */\r
+\r
+/** @defgroup STM32L152_EVAL_LCD\r
+  * @brief   This file includes the LCD driver for AM-240320L8TNQW00H (LCD_ILI9320),\r
+  *          AM-240320LDTNQW00H (LCD_SPFD5408B) Liquid Crystal Display Module\r
+  *          of STM32L152-EVAL board.\r
+  * @{\r
+  */\r
+\r
+/** @defgroup STM32L152_EVAL_LCD_Private_Types\r
+  * @{\r
+  */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup STM32L152_EVAL_LCD_Private_Defines\r
+  * @{\r
+  */\r
+#define LCD_ILI9320        0x9320\r
+#define LCD_SPFD5408       0x5408\r
+#define START_BYTE         0x70\r
+#define SET_INDEX          0x00\r
+#define READ_STATUS        0x01\r
+#define LCD_WRITE_REG      0x02\r
+#define LCD_READ_REG       0x03\r
+#define MAX_POLY_CORNERS   200\r
+#define POLY_Y(Z)          ((int32_t)((Points + Z)->X))\r
+#define POLY_X(Z)          ((int32_t)((Points + Z)->Y))\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup STM32L152_EVAL_LCD_Private_Macros\r
+  * @{\r
+  */\r
+#define ABS(X)  ((X) > 0 ? (X) : -(X))\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup STM32L152_EVAL_LCD_Private_Variables\r
+  * @{\r
+  */\r
+static sFONT *LCD_Currentfonts;\r
+/* Global variables to set the written text color */\r
+static __IO uint16_t TextColor = 0x0000, BackColor = 0xFFFF;\r
+static __IO uint32_t LCDType = LCD_SPFD5408;\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup STM32L152_EVAL_LCD_Private_Function_Prototypes\r
+  * @{\r
+  */\r
+#ifndef USE_Delay\r
+static void delay(__IO uint32_t nCount);\r
+#endif /* USE_Delay*/\r
+\r
+static void PutPixel(int16_t x, int16_t y);\r
+static void LCD_PolyLineRelativeClosed(pPoint Points, uint16_t PointCount, uint16_t Closed);\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup STM32L152_EVAL_LCD_Private_Functions\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @brief  DeInitializes the LCD.\r
+  * @param  None\r
+  * @retval None\r
+  */\r
+void STM32L152_LCD_DeInit(void)\r
+{\r
+  GPIO_InitTypeDef GPIO_InitStructure;\r
+\r
+  /*!< LCD Display Off */\r
+  LCD_DisplayOff();\r
+\r
+  /*!< LCD_SPI disable */\r
+  SPI_Cmd(LCD_SPI, DISABLE);\r
+\r
+  /*!< LCD_SPI DeInit */\r
+  SPI_DeInit(LCD_SPI);\r
+\r
+  /*!< Disable SPI clock  */\r
+  RCC_APB1PeriphClockCmd(LCD_SPI_CLK, DISABLE);\r
+\r
+  /* Configure NCS in Output Push-Pull mode */\r
+  GPIO_InitStructure.GPIO_Pin = LCD_NCS_PIN;\r
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN;\r
+  GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;\r
+  GPIO_Init(LCD_NCS_GPIO_PORT, &GPIO_InitStructure);\r
+\r
+  /* Configure SPI pins: SCK, MISO and MOSI */\r
+  GPIO_InitStructure.GPIO_Pin = LCD_SPI_SCK_PIN;\r
+  GPIO_Init(LCD_SPI_SCK_GPIO_PORT, &GPIO_InitStructure);\r
+\r
+  GPIO_InitStructure.GPIO_Pin = LCD_SPI_MISO_PIN;\r
+  GPIO_Init(LCD_SPI_MISO_GPIO_PORT, &GPIO_InitStructure);\r
+\r
+  GPIO_InitStructure.GPIO_Pin = LCD_SPI_MOSI_PIN;\r
+  GPIO_Init(LCD_SPI_MOSI_GPIO_PORT, &GPIO_InitStructure);\r
+}\r
+\r
+/**\r
+  * @brief  Setups the LCD.\r
+  * @param  None\r
+  * @retval None\r
+  */\r
+void LCD_Setup(void)\r
+{\r
+/* Configure the LCD Control pins --------------------------------------------*/\r
+  LCD_CtrlLinesConfig();\r
+\r
+/* Configure the LCD_SPI interface ----------------------------------------------*/\r
+  LCD_SPIConfig();\r
+\r
+  if(LCDType == LCD_SPFD5408)\r
+  {\r
+    /* Start Initial Sequence --------------------------------------------------*/\r
+    LCD_WriteReg(LCD_REG_227, 0x3008); /* Set internal timing */\r
+    LCD_WriteReg(LCD_REG_231, 0x0012); /* Set internal timing */\r
+    LCD_WriteReg(LCD_REG_239, 0x1231); /* Set internal timing */\r
+    LCD_WriteReg(LCD_REG_1, 0x0100);   /* Set SS and SM bit */\r
+    LCD_WriteReg(LCD_REG_2, 0x0700);   /* Set 1 line inversion */\r
+    LCD_WriteReg(LCD_REG_3, 0x1030);   /* Set GRAM write direction and BGR=1. */\r
+    LCD_WriteReg(LCD_REG_4, 0x0000);   /* Resize register */\r
+    LCD_WriteReg(LCD_REG_8, 0x0202);   /* Set the back porch and front porch */\r
+    LCD_WriteReg(LCD_REG_9, 0x0000);   /* Set non-display area refresh cycle ISC[3:0] */\r
+    LCD_WriteReg(LCD_REG_10, 0x0000);  /* FMARK function */\r
+    LCD_WriteReg(LCD_REG_12, 0x0000);  /* RGB interface setting */\r
+    LCD_WriteReg(LCD_REG_13, 0x0000);  /* Frame marker Position */\r
+    LCD_WriteReg(LCD_REG_15, 0x0000);  /* RGB interface polarity */\r
+    /* Power On sequence -------------------------------------------------------*/\r
+    LCD_WriteReg(LCD_REG_16, 0x0000);  /* SAP, BT[3:0], AP, DSTB, SLP, STB */\r
+    LCD_WriteReg(LCD_REG_17, 0x0000);  /* DC1[2:0], DC0[2:0], VC[2:0] */\r
+    LCD_WriteReg(LCD_REG_18, 0x0000);  /* VREG1OUT voltage */\r
+    LCD_WriteReg(LCD_REG_19, 0x0000);  /* VDV[4:0] for VCOM amplitude */\r
+    _delay_(20);                /* Dis-charge capacitor power voltage (200ms) */\r
+    LCD_WriteReg(LCD_REG_17, 0x0007);  /* DC1[2:0], DC0[2:0], VC[2:0] */\r
+    _delay_(5);                 /* Delay 50 ms */\r
+    LCD_WriteReg(LCD_REG_16, 0x12B0);  /* SAP, BT[3:0], AP, DSTB, SLP, STB */\r
+    _delay_(5);                  /* Delay 50 ms */\r
+    LCD_WriteReg(LCD_REG_18, 0x01BD);  /* External reference voltage= Vci */\r
+    _delay_(5);                 /* Delay 50 ms */\r
+    LCD_WriteReg(LCD_REG_19, 0x1400);       /* VDV[4:0] for VCOM amplitude */\r
+    LCD_WriteReg(LCD_REG_41, 0x000E);  /* VCM[4:0] for VCOMH */\r
+    _delay_(5);                 /* Delay 50 ms */\r
+    LCD_WriteReg(LCD_REG_32, 0x0000);  /* GRAM horizontal Address */\r
+    LCD_WriteReg(LCD_REG_33, 0x013F);  /* GRAM Vertical Address */\r
+    /* Adjust the Gamma Curve --------------------------------------------------*/\r
+    LCD_WriteReg(LCD_REG_48, 0x0007);\r
+    LCD_WriteReg(LCD_REG_49, 0x0302);\r
+    LCD_WriteReg(LCD_REG_50, 0x0105);\r
+    LCD_WriteReg(LCD_REG_53, 0x0206);\r
+    LCD_WriteReg(LCD_REG_54, 0x0808);\r
+    LCD_WriteReg(LCD_REG_55, 0x0206);\r
+    LCD_WriteReg(LCD_REG_56, 0x0504);\r
+    LCD_WriteReg(LCD_REG_57, 0x0007);\r
+    LCD_WriteReg(LCD_REG_60, 0x0105);\r
+    LCD_WriteReg(LCD_REG_61, 0x0808);\r
+    /* Set GRAM area -----------------------------------------------------------*/\r
+    LCD_WriteReg(LCD_REG_80, 0x0000);  /* Horizontal GRAM Start Address */\r
+    LCD_WriteReg(LCD_REG_81, 0x00EF);  /* Horizontal GRAM End Address */\r
+    LCD_WriteReg(LCD_REG_82, 0x0000);  /* Vertical GRAM Start Address */\r
+    LCD_WriteReg(LCD_REG_83, 0x013F);  /* Vertical GRAM End Address */\r
+    LCD_WriteReg(LCD_REG_96,  0xA700); /* Gate Scan Line */\r
+    LCD_WriteReg(LCD_REG_97,  0x0001); /* NDL,VLE, REV */\r
+    LCD_WriteReg(LCD_REG_106, 0x0000); /* Set scrolling line */\r
+    /* Partial Display Control -------------------------------------------------*/\r
+    LCD_WriteReg(LCD_REG_128, 0x0000);\r
+    LCD_WriteReg(LCD_REG_129, 0x0000);\r
+    LCD_WriteReg(LCD_REG_130, 0x0000);\r
+    LCD_WriteReg(LCD_REG_131, 0x0000);\r
+    LCD_WriteReg(LCD_REG_132, 0x0000);\r
+    LCD_WriteReg(LCD_REG_133, 0x0000);\r
+    /* Panel Control -----------------------------------------------------------*/\r
+    LCD_WriteReg(LCD_REG_144, 0x0010);\r
+    LCD_WriteReg(LCD_REG_146, 0x0000);\r
+    LCD_WriteReg(LCD_REG_147, 0x0003);\r
+    LCD_WriteReg(LCD_REG_149, 0x0110);\r
+    LCD_WriteReg(LCD_REG_151, 0x0000);\r
+    LCD_WriteReg(LCD_REG_152, 0x0000);\r
+    /* Set GRAM write direction and BGR = 1\r
+       I/D=01 (Horizontal : increment, Vertical : decrement)\r
+       AM=1 (address is updated in vertical writing direction) */\r
+    LCD_WriteReg(LCD_REG_3, 0x1018);\r
+    LCD_WriteReg(LCD_REG_7, 0x0112);   /* 262K color and display ON */\r
+  }\r
+  else if(LCDType == LCD_ILI9320)\r
+  {\r
+    _delay_(5); /* Delay 50 ms */\r
+    /* Start Initial Sequence ------------------------------------------------*/\r
+    LCD_WriteReg(LCD_REG_229, 0x8000); /* Set the internal vcore voltage */\r
+    LCD_WriteReg(LCD_REG_0,  0x0001); /* Start internal OSC. */\r
+    LCD_WriteReg(LCD_REG_1,  0x0100); /* set SS and SM bit */\r
+    LCD_WriteReg(LCD_REG_2,  0x0700); /* set 1 line inversion */\r
+    LCD_WriteReg(LCD_REG_3,  0x1030); /* set GRAM write direction and BGR=1. */\r
+    LCD_WriteReg(LCD_REG_4,  0x0000); /* Resize register */\r
+    LCD_WriteReg(LCD_REG_8,  0x0202); /* set the back porch and front porch */\r
+    LCD_WriteReg(LCD_REG_9,  0x0000); /* set non-display area refresh cycle ISC[3:0] */\r
+    LCD_WriteReg(LCD_REG_10, 0x0000); /* FMARK function */\r
+    LCD_WriteReg(LCD_REG_12, 0x0000); /* RGB interface setting */\r
+    LCD_WriteReg(LCD_REG_13, 0x0000); /* Frame marker Position */\r
+    LCD_WriteReg(LCD_REG_15, 0x0000); /* RGB interface polarity */\r
+    /* Power On sequence -----------------------------------------------------*/\r
+    LCD_WriteReg(LCD_REG_16, 0x0000); /* SAP, BT[3:0], AP, DSTB, SLP, STB */\r
+    LCD_WriteReg(LCD_REG_17, 0x0000); /* DC1[2:0], DC0[2:0], VC[2:0] */\r
+    LCD_WriteReg(LCD_REG_18, 0x0000); /* VREG1OUT voltage */\r
+    LCD_WriteReg(LCD_REG_19, 0x0000); /* VDV[4:0] for VCOM amplitude */\r
+    _delay_(20);                      /* Dis-charge capacitor power voltage (200ms) */\r
+    LCD_WriteReg(LCD_REG_16, 0x17B0); /* SAP, BT[3:0], AP, DSTB, SLP, STB */\r
+    LCD_WriteReg(LCD_REG_17, 0x0137); /* DC1[2:0], DC0[2:0], VC[2:0] */\r
+    _delay_(5);                       /* Delay 50 ms */\r
+    LCD_WriteReg(LCD_REG_18, 0x0139); /* VREG1OUT voltage */\r
+    _delay_(5);                       /* Delay 50 ms */\r
+    LCD_WriteReg(LCD_REG_19, 0x1d00); /* VDV[4:0] for VCOM amplitude */\r
+    LCD_WriteReg(LCD_REG_41, 0x0013); /* VCM[4:0] for VCOMH */\r
+    _delay_(5);                       /* Delay 50 ms */\r
+    LCD_WriteReg(LCD_REG_32, 0x0000); /* GRAM horizontal Address */\r
+    LCD_WriteReg(LCD_REG_33, 0x0000); /* GRAM Vertical Address */\r
+    /* Adjust the Gamma Curve ------------------------------------------------*/\r
+    LCD_WriteReg(LCD_REG_48, 0x0006);\r
+    LCD_WriteReg(LCD_REG_49, 0x0101);\r
+    LCD_WriteReg(LCD_REG_50, 0x0003);\r
+    LCD_WriteReg(LCD_REG_53, 0x0106);\r
+    LCD_WriteReg(LCD_REG_54, 0x0b02);\r
+    LCD_WriteReg(LCD_REG_55, 0x0302);\r
+    LCD_WriteReg(LCD_REG_56, 0x0707);\r
+    LCD_WriteReg(LCD_REG_57, 0x0007);\r
+    LCD_WriteReg(LCD_REG_60, 0x0600);\r
+    LCD_WriteReg(LCD_REG_61, 0x020b);\r
+\r
+    /* Set GRAM area ---------------------------------------------------------*/\r
+    LCD_WriteReg(LCD_REG_80, 0x0000); /* Horizontal GRAM Start Address */\r
+    LCD_WriteReg(LCD_REG_81, 0x00EF); /* Horizontal GRAM End Address */\r
+    LCD_WriteReg(LCD_REG_82, 0x0000); /* Vertical GRAM Start Address */\r
+    LCD_WriteReg(LCD_REG_83, 0x013F); /* Vertical GRAM End Address */\r
+    LCD_WriteReg(LCD_REG_96,  0x2700); /* Gate Scan Line */\r
+    LCD_WriteReg(LCD_REG_97,  0x0001); /* NDL,VLE, REV */\r
+    LCD_WriteReg(LCD_REG_106, 0x0000); /* set scrolling line */\r
+    /* Partial Display Control -----------------------------------------------*/\r
+    LCD_WriteReg(LCD_REG_128, 0x0000);\r
+    LCD_WriteReg(LCD_REG_129, 0x0000);\r
+    LCD_WriteReg(LCD_REG_130, 0x0000);\r
+    LCD_WriteReg(LCD_REG_131, 0x0000);\r
+    LCD_WriteReg(LCD_REG_132, 0x0000);\r
+    LCD_WriteReg(LCD_REG_133, 0x0000);\r
+    /* Panel Control ---------------------------------------------------------*/\r
+    LCD_WriteReg(LCD_REG_144, 0x0010);\r
+    LCD_WriteReg(LCD_REG_146, 0x0000);\r
+    LCD_WriteReg(LCD_REG_147, 0x0003);\r
+    LCD_WriteReg(LCD_REG_149, 0x0110);\r
+    LCD_WriteReg(LCD_REG_151, 0x0000);\r
+    LCD_WriteReg(LCD_REG_152, 0x0000);\r
+    /* Set GRAM write direction and BGR = 1 */\r
+    /* I/D=01 (Horizontal : increment, Vertical : decrement) */\r
+    /* AM=1 (address is updated in vertical writing direction) */\r
+    LCD_WriteReg(LCD_REG_3, 0x1018);\r
+    LCD_WriteReg(LCD_REG_7, 0x0173); /* 262K color and display ON */\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  * @brief  Initializes the LCD.\r
+  * @param  None\r
+  * @retval None\r
+  */\r
+void STM32L152_LCD_Init(void)\r
+{\r
+  /* Setups the LCD */\r
+  LCD_Setup();\r
+\r
+  /* Try to read new LCD controller ID 0x5408 */\r
+  if (LCD_ReadReg(LCD_REG_0) == LCD_SPFD5408)\r
+  {\r
+    LCDType = LCD_SPFD5408;\r
+  }\r
+  else\r
+  {\r
+    LCDType = LCD_ILI9320;\r
+    /* Setups the LCD */\r
+    LCD_Setup();\r
+  }\r
+\r
+  LCD_SetFont(&LCD_DEFAULT_FONT);\r
+}\r
+\r
+/**\r
+  * @brief  Sets the LCD Text and Background colors.\r
+  * @param  _TextColor: specifies the Text Color.\r
+  * @param  _BackColor: specifies the Background Color.\r
+  * @retval None\r
+  */\r
+void LCD_SetColors(__IO uint16_t _TextColor, __IO uint16_t _BackColor)\r
+{\r
+  TextColor = _TextColor;\r
+  BackColor = _BackColor;\r
+}\r
+\r
+/**\r
+  * @brief  Gets the LCD Text and Background colors.\r
+  * @param  _TextColor: pointer to the variable that will contain the Text\r
+            Color.\r
+  * @param  _BackColor: pointer to the variable that will contain the Background\r
+            Color.\r
+  * @retval None\r
+  */\r
+void LCD_GetColors(__IO uint16_t *_TextColor, __IO uint16_t *_BackColor)\r
+{\r
+  *_TextColor = TextColor; *_BackColor = BackColor;\r
+}\r
+\r
+/**\r
+  * @brief  Sets the Text color.\r
+  * @param  Color: specifies the Text color code RGB(5-6-5).\r
+  * @retval None\r
+  */\r
+void LCD_SetTextColor(__IO uint16_t Color)\r
+{\r
+  TextColor = Color;\r
+}\r
+\r
+\r
+/**\r
+  * @brief  Sets the Background color.\r
+  * @param  Color: specifies the Background color code RGB(5-6-5).\r
+  * @retval None\r
+  */\r
+void LCD_SetBackColor(__IO uint16_t Color)\r
+{\r
+  BackColor = Color;\r
+}\r
+\r
+/**\r
+  * @brief  Sets the Text Font.\r
+  * @param  fonts: specifies the font to be used.\r
+  * @retval None\r
+  */\r
+void LCD_SetFont(sFONT *fonts)\r
+{\r
+  LCD_Currentfonts = fonts;\r
+}\r
+\r
+/**\r
+  * @brief  Gets the Text Font.\r
+  * @param  None.\r
+  * @retval the used font.\r
+  */\r
+sFONT *LCD_GetFont(void)\r
+{\r
+  return LCD_Currentfonts;\r
+}\r
+\r
+/**\r
+  * @brief  Clears the selected line.\r
+  * @param  Line: the Line to be cleared.\r
+  *   This parameter can be one of the following values:\r
+  *     @arg Linex: where x can be 0..n\r
+  * @retval None\r
+  */\r
+void LCD_ClearLine(uint8_t Line)\r
+{\r
+  uint16_t refcolumn = LCD_PIXEL_WIDTH - 1;\r
+\r
+  /* Send the string character by character on lCD */\r
+  while (((refcolumn + 1) & 0xFFFF) >= LCD_Currentfonts->Width)\r
+  {\r
+    /* Display one character on LCD */\r
+    LCD_DisplayChar(Line, refcolumn, ' ');\r
+    /* Decrement the column position by 16 */\r
+    refcolumn -= LCD_Currentfonts->Width;\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  * @brief  Clears the hole LCD.\r
+  * @param  Color: the color of the background.\r
+  * @retval None\r
+  */\r
+void LCD_Clear(uint16_t Color)\r
+{\r
+  uint32_t index = 0;\r
+\r
+  LCD_SetCursor(0x00, 0x013F);\r
+\r
+  LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */\r
+\r
+  for(index = 0; index < 76800; index++)\r
+  {\r
+    LCD_WriteRAM(Color);\r
+  }\r
+\r
+  LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET);\r
+\r
+}\r
+\r
+\r
+/**\r
+  * @brief  Sets the cursor position.\r
+  * @param  Xpos: specifies the X position.\r
+  * @param  Ypos: specifies the Y position.\r
+  * @retval None\r
+  */\r
+void LCD_SetCursor(uint8_t Xpos, uint16_t Ypos)\r
+{\r
+  LCD_WriteReg(LCD_REG_32, Xpos);\r
+  LCD_WriteReg(LCD_REG_33, Ypos);\r
+}\r
+\r
+\r
+/**\r
+  * @brief  Draws a character on LCD.\r
+  * @param  Xpos: the Line where to display the character shape.\r
+  * @param  Ypos: start column address.\r
+  * @param  c: pointer to the character data.\r
+  * @retval None\r
+  */\r
+void LCD_DrawChar(uint8_t Xpos, uint16_t Ypos, const uint16_t *c)\r
+{\r
+  uint32_t index = 0, i = 0;\r
+  uint8_t Xaddress = 0;\r
+\r
+  Xaddress = Xpos;\r
+\r
+  LCD_SetCursor(Xaddress, Ypos);\r
+\r
+  for(index = 0; index < LCD_Currentfonts->Height; index++)\r
+  {\r
+    LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */\r
+\r
+    for(i = 0; i < LCD_Currentfonts->Width; i++)\r
+    {\r
+      if((((c[index] & ((0x80 << ((LCD_Currentfonts->Width / 12 ) * 8 ) ) >> i)) == 0x00) &&(LCD_Currentfonts->Width <= 12))||\r
+        (((c[index] & (0x1 << i)) == 0x00)&&(LCD_Currentfonts->Width > 12 )))\r
+\r
+      {\r
+        LCD_WriteRAM(BackColor);\r
+      }\r
+      else\r
+      {\r
+        LCD_WriteRAM(TextColor);\r
+      }\r
+    }\r
+\r
+    LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET);\r
+    Xaddress++;\r
+    LCD_SetCursor(Xaddress, Ypos);\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  * @brief  Displays one character (16dots width, 24dots height).\r
+  * @param  Line: the Line where to display the character shape .\r
+  *   This parameter can be one of the following values:\r
+  *     @arg Linex: where x can be 0..9\r
+  * @param  Column: start column address.\r
+  * @param  Ascii: character ascii code, must be between 0x20 and 0x7E.\r
+  * @retval None\r
+  */\r
+void LCD_DisplayChar(uint8_t Line, uint16_t Column, uint8_t Ascii)\r
+{\r
+  Ascii -= 32;\r
+  LCD_DrawChar(Line, Column, &LCD_Currentfonts->table[Ascii * LCD_Currentfonts->Height]);\r
+}\r
+\r
+\r
+/**\r
+  * @brief  Displays a maximum of 20 char on the LCD.\r
+  * @param  Line: the Line where to display the character shape .\r
+  *   This parameter can be one of the following values:\r
+  *     @arg Linex: where x can be 0..9\r
+  * @param  *ptr: pointer to string to display on LCD.\r
+  * @retval None\r
+  */\r
+void LCD_DisplayStringLine(uint8_t Line, uint8_t *ptr)\r
+{\r
+  uint16_t refcolumn = LCD_PIXEL_WIDTH - 1;\r
+\r
+  /* Send the string character by character on lCD */\r
+  while ((*ptr != 0) & (((refcolumn + 1) & 0xFFFF) >= LCD_Currentfonts->Width))\r
+  {\r
+    /* Display one character on LCD */\r
+    LCD_DisplayChar(Line, refcolumn, *ptr);\r
+    /* Decrement the column position by 16 */\r
+    refcolumn -= LCD_Currentfonts->Width;\r
+    /* Point on the next character */\r
+    ptr++;\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  * @brief  Sets a display window\r
+  * @param  Xpos: specifies the X buttom left position.\r
+  * @param  Ypos: specifies the Y buttom left position.\r
+  * @param  Height: display window height.\r
+  * @param  Width: display window width.\r
+  * @retval None\r
+  */\r
+void LCD_SetDisplayWindow(uint8_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width)\r
+{\r
+  /* Horizontal GRAM Start Address */\r
+  if(Xpos >= Height)\r
+  {\r
+    LCD_WriteReg(LCD_REG_80, (Xpos - Height + 1));\r
+  }\r
+  else\r
+  {\r
+    LCD_WriteReg(LCD_REG_80, 0);\r
+  }\r
+  /* Horizontal GRAM End Address */\r
+  LCD_WriteReg(LCD_REG_81, Xpos);\r
+  /* Vertical GRAM Start Address */\r
+  if(Ypos >= Width)\r
+  {\r
+    LCD_WriteReg(LCD_REG_82, (Ypos - Width + 1));\r
+  }\r
+  else\r
+  {\r
+    LCD_WriteReg(LCD_REG_82, 0);\r
+  }\r
+  /* Vertical GRAM End Address */\r
+  LCD_WriteReg(LCD_REG_83, Ypos);\r
+\r
+  LCD_SetCursor(Xpos, Ypos);\r
+}\r
+\r
+\r
+/**\r
+  * @brief  Disables LCD Window mode.\r
+  * @param  None\r
+  * @retval None\r
+  */\r
+void LCD_WindowModeDisable(void)\r
+{\r
+  LCD_SetDisplayWindow(239, 0x13F, 240, 320);\r
+  LCD_WriteReg(LCD_REG_3, 0x1018);\r
+}\r
+\r
+/**\r
+  * @brief  Displays a line.\r
+  * @param  Xpos: specifies the X position.\r
+  * @param  Ypos: specifies the Y position.\r
+  * @param  Length: line length.\r
+  * @param  Direction: line direction.\r
+  *   This parameter can be one of the following values: Vertical or Horizontal.\r
+  * @retval None\r
+  */\r
+void LCD_DrawLine(uint8_t Xpos, uint16_t Ypos, uint16_t Length, uint8_t Direction)\r
+{\r
+  uint32_t i = 0;\r
+\r
+  LCD_SetCursor(Xpos, Ypos);\r
+\r
+  if(Direction == LCD_DIR_HORIZONTAL)\r
+  {\r
+    LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */\r
+\r
+    for(i = 0; i < Length; i++)\r
+    {\r
+      LCD_WriteRAM(TextColor);\r
+    }\r
+    LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET);\r
+  }\r
+  else\r
+  {\r
+    for(i = 0; i < Length; i++)\r
+    {\r
+      LCD_WriteRAMWord(TextColor);\r
+      Xpos++;\r
+      LCD_SetCursor(Xpos, Ypos);\r
+    }\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  * @brief  Displays a rectangle.\r
+  * @param  Xpos: specifies the X position.\r
+  * @param  Ypos: specifies the Y position.\r
+  * @param  Height: display rectangle height.\r
+  * @param  Width: display rectangle width.\r
+  * @retval None\r
+  */\r
+void LCD_DrawRect(uint8_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width)\r
+{\r
+  LCD_DrawLine(Xpos, Ypos, Width, LCD_DIR_HORIZONTAL);\r
+  LCD_DrawLine((Xpos + Height), Ypos, Width, LCD_DIR_HORIZONTAL);\r
+\r
+  LCD_DrawLine(Xpos, Ypos, Height, LCD_DIR_VERTICAL);\r
+  LCD_DrawLine(Xpos, (Ypos - Width + 1), Height, LCD_DIR_VERTICAL);\r
+}\r
+\r
+\r
+/**\r
+  * @brief  Displays a circle.\r
+  * @param  Xpos: specifies the X position.\r
+  * @param  Ypos: specifies the Y position.\r
+  * @param  Radius\r
+  * @retval None\r
+  */\r
+void LCD_DrawCircle(uint8_t Xpos, uint16_t Ypos, uint16_t Radius)\r
+{\r
+  int32_t  D;/* Decision Variable */\r
+  uint32_t  CurX;/* Current X Value */\r
+  uint32_t  CurY;/* Current Y Value */\r
+\r
+  D = 3 - (Radius << 1);\r
+  CurX = 0;\r
+  CurY = Radius;\r
+\r
+  while (CurX <= CurY)\r
+  {\r
+    LCD_SetCursor(Xpos + CurX, Ypos + CurY);\r
+    LCD_WriteRAMWord(TextColor);\r
+    LCD_SetCursor(Xpos + CurX, Ypos - CurY);\r
+    LCD_WriteRAMWord(TextColor);\r
+\r
+    LCD_SetCursor(Xpos - CurX, Ypos + CurY);\r
+    LCD_WriteRAMWord(TextColor);\r
+\r
+    LCD_SetCursor(Xpos - CurX, Ypos - CurY);\r
+    LCD_WriteRAMWord(TextColor);\r
+\r
+    LCD_SetCursor(Xpos + CurY, Ypos + CurX);\r
+    LCD_WriteRAMWord(TextColor);\r
+\r
+    LCD_SetCursor(Xpos + CurY, Ypos - CurX);\r
+    LCD_WriteRAMWord(TextColor);\r
+\r
+    LCD_SetCursor(Xpos - CurY, Ypos + CurX);\r
+    LCD_WriteRAMWord(TextColor);\r
+\r
+    LCD_SetCursor(Xpos - CurY, Ypos - CurX);\r
+    LCD_WriteRAMWord(TextColor);\r
+\r
+    if (D < 0)\r
+    {\r
+      D += (CurX << 2) + 6;\r
+    }\r
+    else\r
+    {\r
+      D += ((CurX - CurY) << 2) + 10;\r
+      CurY--;\r
+    }\r
+    CurX++;\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  * @brief  Displays a monocolor picture.\r
+  * @param  Pict: pointer to the picture array.\r
+  * @retval None\r
+  */\r
+void LCD_DrawMonoPict(const uint32_t *Pict)\r
+{\r
+  uint32_t index = 0, i = 0;\r
+  LCD_SetCursor(0, (LCD_PIXEL_WIDTH - 1));\r
+\r
+  LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */\r
+\r
+  for(index = 0; index < 2400; index++)\r
+  {\r
+    for(i = 0; i < 32; i++)\r
+    {\r
+      if((Pict[index] & (1 << i)) == 0x00)\r
+      {\r
+        LCD_WriteRAM(BackColor);\r
+      }\r
+      else\r
+      {\r
+        LCD_WriteRAM(TextColor);\r
+      }\r
+    }\r
+  }\r
+\r
+  LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET);\r
+}\r
+\r
+#ifdef USE_LCD_DrawBMP\r
+/**\r
+  * @brief  Displays a bitmap picture loaded in the SPI Flash.\r
+  * @param  BmpAddress: Bmp picture address in the SPI Flash.\r
+  * @retval None\r
+  */\r
+void LCD_DrawBMP(uint32_t BmpAddress)\r
+{\r
+  uint32_t i = 0, size = 0;\r
+  /* Read bitmap size */\r
+  SPI_FLASH_BufferRead((uint8_t*)&size, BmpAddress + 2, 4);\r
+  /* get bitmap data address offset */\r
+  SPI_FLASH_BufferRead((uint8_t*)&i, BmpAddress + 10, 4);\r
+\r
+  size = (size - i)/2;\r
+  SPI_FLASH_StartReadSequence(BmpAddress + i);\r
+  /* Disable SPI1  */\r
+  SPI_Cmd(SPI1, DISABLE);\r
+  /* SPI in 16-bit mode */\r
+  SPI_DataSizeConfig(SPI1, SPI_DataSize_16b);\r
+  /* Enable SPI1  */\r
+  SPI_Cmd(SPI1, ENABLE);\r
+\r
+  if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))\r
+  {\r
+    /* Set GRAM write direction and BGR = 1 */\r
+    /* I/D=00 (Horizontal : decrement, Vertical : decrement) */\r
+    /* AM=1 (address is updated in vertical writing direction) */\r
+    LCD_WriteReg(LCD_REG_3, 0x1008);\r
+    LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */\r
+  }\r
+\r
+  /* Read bitmap data from SPI Flash and send them to LCD */\r
+  for(i = 0; i < size; i++)\r
+  {\r
+    LCD_WriteRAM(__REV16(SPI_FLASH_SendHalfWord(0xA5A5)));\r
+  }\r
+  if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))\r
+  {\r
+    LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET);\r
+  }\r
+\r
+  /* Deselect the FLASH: Chip Select high */\r
+  SPI_FLASH_CS_HIGH();\r
+  /* Disable SPI1  */\r
+  SPI_Cmd(SPI1, DISABLE);\r
+  /* SPI in 8-bit mode */\r
+  SPI_DataSizeConfig(SPI1, SPI_DataSize_8b);\r
+  /* Enable SPI1  */\r
+  SPI_Cmd(SPI1, ENABLE);\r
+\r
+  if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))\r
+  {\r
+    /* Set GRAM write direction and BGR = 1 */\r
+    /* I/D = 01 (Horizontal : increment, Vertical : decrement) */\r
+    /* AM = 1 (address is updated in vertical writing direction) */\r
+    LCD_WriteReg(LCD_REG_3, 0x1018);\r
+  }\r
+}\r
+#endif /* USE_LCD_DrawBMP */\r
+\r
+/**\r
+  * @brief  Displays a full rectangle.\r
+  * @param  Xpos: specifies the X position.\r
+  * @param  Ypos: specifies the Y position.\r
+  * @param  Height: rectangle height.\r
+  * @param  Width: rectangle width.\r
+  * @retval None\r
+  */\r
+void LCD_DrawFullRect(uint16_t Xpos, uint16_t Ypos, uint16_t Width, uint16_t Height)\r
+{\r
+  LCD_SetTextColor(TextColor);\r
+\r
+  LCD_DrawLine(Xpos, Ypos, Width, LCD_DIR_HORIZONTAL);\r
+  LCD_DrawLine((Xpos + Height), Ypos, Width, LCD_DIR_HORIZONTAL);\r
+\r
+  LCD_DrawLine(Xpos, Ypos, Height, LCD_DIR_VERTICAL);\r
+  LCD_DrawLine(Xpos, (Ypos - Width + 1), Height, LCD_DIR_VERTICAL);\r
+\r
+  Width -= 2;\r
+  Height--;\r
+  Ypos--;\r
+\r
+  LCD_SetTextColor(BackColor);\r
+\r
+  while(Height--)\r
+  {\r
+    LCD_DrawLine(++Xpos, Ypos, Width, LCD_DIR_HORIZONTAL);\r
+  }\r
+\r
+  LCD_SetTextColor(TextColor);\r
+}\r
+\r
+/**\r
+  * @brief  Displays a full circle.\r
+  * @param  Xpos: specifies the X position.\r
+  * @param  Ypos: specifies the Y position.\r
+  * @param  Radius\r
+  * @retval None\r
+  */\r
+void LCD_DrawFullCircle(uint16_t Xpos, uint16_t Ypos, uint16_t Radius)\r
+{\r
+  int32_t  D;    /* Decision Variable */\r
+  uint32_t  CurX;/* Current X Value */\r
+  uint32_t  CurY;/* Current Y Value */\r
+\r
+  D = 3 - (Radius << 1);\r
+\r
+  CurX = 0;\r
+  CurY = Radius;\r
+\r
+  LCD_SetTextColor(BackColor);\r
+\r
+  while (CurX <= CurY)\r
+  {\r
+    if(CurY > 0)\r
+    {\r
+      LCD_DrawLine(Xpos - CurX, Ypos + CurY, 2*CurY, LCD_DIR_HORIZONTAL);\r
+      LCD_DrawLine(Xpos + CurX, Ypos + CurY, 2*CurY, LCD_DIR_HORIZONTAL);\r
+    }\r
+\r
+    if(CurX > 0)\r
+    {\r
+      LCD_DrawLine(Xpos - CurY, Ypos + CurX, 2*CurX, LCD_DIR_HORIZONTAL);\r
+      LCD_DrawLine(Xpos + CurY, Ypos + CurX, 2*CurX, LCD_DIR_HORIZONTAL);\r
+    }\r
+    if (D < 0)\r
+    {\r
+      D += (CurX << 2) + 6;\r
+    }\r
+    else\r
+    {\r
+      D += ((CurX - CurY) << 2) + 10;\r
+      CurY--;\r
+    }\r
+    CurX++;\r
+  }\r
+\r
+  LCD_SetTextColor(TextColor);\r
+  LCD_DrawCircle(Xpos, Ypos, Radius);\r
+}\r
+\r
+/**\r
+  * @brief  Displays an uni line (between two points).\r
+  * @param  x1: specifies the point 1 x position.\r
+  * @param  y1: specifies the point 1 y position.\r
+  * @param  x2: specifies the point 2 x position.\r
+  * @param  y2: specifies the point 2 y position.\r
+  * @retval None\r
+  */\r
+void LCD_DrawUniLine(uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2)\r
+{\r
+  int16_t deltax = 0, deltay = 0, x = 0, y = 0, xinc1 = 0, xinc2 = 0,\r
+  yinc1 = 0, yinc2 = 0, den = 0, num = 0, numadd = 0, numpixels = 0,\r
+  curpixel = 0;\r
+\r
+  deltax = ABS(x2 - x1);        /* The difference between the x's */\r
+  deltay = ABS(y2 - y1);        /* The difference between the y's */\r
+  x = x1;                       /* Start x off at the first pixel */\r
+  y = y1;                       /* Start y off at the first pixel */\r
+\r
+  if (x2 >= x1)                 /* The x-values are increasing */\r
+  {\r
+    xinc1 = 1;\r
+    xinc2 = 1;\r
+  }\r
+  else                          /* The x-values are decreasing */\r
+  {\r
+    xinc1 = -1;\r
+    xinc2 = -1;\r
+  }\r
+\r
+  if (y2 >= y1)                 /* The y-values are increasing */\r
+  {\r
+    yinc1 = 1;\r
+    yinc2 = 1;\r
+  }\r
+  else                          /* The y-values are decreasing */\r
+  {\r
+    yinc1 = -1;\r
+    yinc2 = -1;\r
+  }\r
+\r
+  if (deltax >= deltay)         /* There is at least one x-value for every y-value */\r
+  {\r
+    xinc1 = 0;                  /* Don't change the x when numerator >= denominator */\r
+    yinc2 = 0;                  /* Don't change the y for every iteration */\r
+    den = deltax;\r
+    num = deltax / 2;\r
+    numadd = deltay;\r
+    numpixels = deltax;         /* There are more x-values than y-values */\r
+  }\r
+  else                          /* There is at least one y-value for every x-value */\r
+  {\r
+    xinc2 = 0;                  /* Don't change the x for every iteration */\r
+    yinc1 = 0;                  /* Don't change the y when numerator >= denominator */\r
+    den = deltay;\r
+    num = deltay / 2;\r
+    numadd = deltax;\r
+    numpixels = deltay;         /* There are more y-values than x-values */\r
+  }\r
+\r
+  for (curpixel = 0; curpixel <= numpixels; curpixel++)\r
+  {\r
+    PutPixel(x, y);             /* Draw the current pixel */\r
+    num += numadd;              /* Increase the numerator by the top of the fraction */\r
+    if (num >= den)             /* Check if numerator >= denominator */\r
+    {\r
+      num -= den;               /* Calculate the new numerator value */\r
+      x += xinc1;               /* Change the x as appropriate */\r
+      y += yinc1;               /* Change the y as appropriate */\r
+    }\r
+    x += xinc2;                 /* Change the x as appropriate */\r
+    y += yinc2;                 /* Change the y as appropriate */\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  Displays an polyline (between many points).\r
+  * @param  Points: pointer to the points array.\r
+  * @param  PointCount: Number of points.\r
+  * @retval None\r
+  */\r
+void LCD_PolyLine(pPoint Points, uint16_t PointCount)\r
+{\r
+  int16_t X = 0, Y = 0;\r
+\r
+  if(PointCount < 2)\r
+  {\r
+    return;\r
+  }\r
+\r
+  while(--PointCount)\r
+  {\r
+    X = Points->X;\r
+    Y = Points->Y;\r
+    Points++;\r
+    LCD_DrawUniLine(X, Y, Points->X, Points->Y);\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  Displays an relative polyline (between many points).\r
+  * @param  Points: pointer to the points array.\r
+  * @param  PointCount: Number of points.\r
+  * @param  Closed: specifies if the draw is closed or not.\r
+  *           1: closed, 0 : not closed.\r
+  * @retval None\r
+  */\r
+static void LCD_PolyLineRelativeClosed(pPoint Points, uint16_t PointCount, uint16_t Closed)\r
+{\r
+  int16_t X = 0, Y = 0;\r
+  pPoint First = Points;\r
+\r
+  if(PointCount < 2)\r
+  {\r
+    return;\r
+  }\r
+  X = Points->X;\r
+  Y = Points->Y;\r
+  while(--PointCount)\r
+  {\r
+    Points++;\r
+    LCD_DrawUniLine(X, Y, X + Points->X, Y + Points->Y);\r
+    X = X + Points->X;\r
+    Y = Y + Points->Y;\r
+  }\r
+  if(Closed)\r
+  {\r
+    LCD_DrawUniLine(First->X, First->Y, X, Y);\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  Displays a closed polyline (between many points).\r
+  * @param  Points: pointer to the points array.\r
+  * @param  PointCount: Number of points.\r
+  * @retval None\r
+  */\r
+void LCD_ClosedPolyLine(pPoint Points, uint16_t PointCount)\r
+{\r
+  LCD_PolyLine(Points, PointCount);\r
+  LCD_DrawUniLine(Points->X, Points->Y, (Points+PointCount-1)->X, (Points+PointCount-1)->Y);\r
+}\r
+\r
+/**\r
+  * @brief  Displays a relative polyline (between many points).\r
+  * @param  Points: pointer to the points array.\r
+  * @param  PointCount: Number of points.\r
+  * @retval None\r
+  */\r
+void LCD_PolyLineRelative(pPoint Points, uint16_t PointCount)\r
+{\r
+  LCD_PolyLineRelativeClosed(Points, PointCount, 0);\r
+}\r
+\r
+/**\r
+  * @brief  Displays a closed relative polyline (between many points).\r
+  * @param  Points: pointer to the points array.\r
+  * @param  PointCount: Number of points.\r
+  * @retval None\r
+  */\r
+void LCD_ClosedPolyLineRelative(pPoint Points, uint16_t PointCount)\r
+{\r
+  LCD_PolyLineRelativeClosed(Points, PointCount, 1);\r
+}\r
+\r
+\r
+/**\r
+  * @brief  Displays a  full polyline (between many points).\r
+  * @param  Points: pointer to the points array.\r
+  * @param  PointCount: Number of points.\r
+  * @retval None\r
+  */\r
+void LCD_FillPolyLine(pPoint Points, uint16_t PointCount)\r
+{\r
+  /*  public-domain code by Darel Rex Finley, 2007 */\r
+  uint16_t  nodes = 0, nodeX[MAX_POLY_CORNERS], pixelX = 0, pixelY = 0, i = 0,\r
+  j = 0, swap = 0;\r
+  uint16_t  IMAGE_LEFT = 0, IMAGE_RIGHT = 0, IMAGE_TOP = 0, IMAGE_BOTTOM = 0;\r
+\r
+  IMAGE_LEFT = IMAGE_RIGHT = Points->X;\r
+  IMAGE_TOP= IMAGE_BOTTOM = Points->Y;\r
+\r
+  for(i = 1; i < PointCount; i++)\r
+  {\r
+    pixelX = POLY_X(i);\r
+    if(pixelX < IMAGE_LEFT)\r
+    {\r
+      IMAGE_LEFT = pixelX;\r
+    }\r
+    if(pixelX > IMAGE_RIGHT)\r
+    {\r
+      IMAGE_RIGHT = pixelX;\r
+    }\r
+\r
+    pixelY = POLY_Y(i);\r
+    if(pixelY < IMAGE_TOP)\r
+    {\r
+      IMAGE_TOP = pixelY;\r
+    }\r
+    if(pixelY > IMAGE_BOTTOM)\r
+    {\r
+      IMAGE_BOTTOM = pixelY;\r
+    }\r
+  }\r
+\r
+  LCD_SetTextColor(BackColor);\r
+\r
+  /*  Loop through the rows of the image. */\r
+  for (pixelY = IMAGE_TOP; pixelY < IMAGE_BOTTOM; pixelY++)\r
+  {\r
+    /* Build a list of nodes. */\r
+    nodes = 0; j = PointCount-1;\r
+\r
+    for (i = 0; i < PointCount; i++)\r
+    {\r
+      if (POLY_Y(i)<(double) pixelY && POLY_Y(j)>=(double) pixelY || POLY_Y(j)<(double) pixelY && POLY_Y(i)>=(double) pixelY)\r
+      {\r
+        nodeX[nodes++]=(int) (POLY_X(i)+((pixelY-POLY_Y(i))*(POLY_X(j)-POLY_X(i)))/(POLY_Y(j)-POLY_Y(i)));\r
+      }\r
+      j = i;\r
+    }\r
+\r
+    /* Sort the nodes, via a simple \93Bubble\94 sort. */\r
+    i = 0;\r
+    while (i < nodes-1)\r
+    {\r
+      if (nodeX[i]>nodeX[i+1])\r
+      {\r
+        swap = nodeX[i];\r
+        nodeX[i] = nodeX[i+1];\r
+        nodeX[i+1] = swap;\r
+        if(i)\r
+        {\r
+          i--;\r
+        }\r
+      }\r
+      else\r
+      {\r
+        i++;\r
+      }\r
+    }\r
+\r
+    /*  Fill the pixels between node pairs. */\r
+    for (i = 0; i < nodes; i+=2)\r
+    {\r
+      if(nodeX[i] >= IMAGE_RIGHT)\r
+      {\r
+        break;\r
+      }\r
+      if(nodeX[i+1] > IMAGE_LEFT)\r
+      {\r
+        if (nodeX[i] < IMAGE_LEFT)\r
+        {\r
+          nodeX[i]=IMAGE_LEFT;\r
+        }\r
+        if(nodeX[i+1] > IMAGE_RIGHT)\r
+        {\r
+          nodeX[i+1] = IMAGE_RIGHT;\r
+        }\r
+        LCD_SetTextColor(BackColor);\r
+        LCD_DrawLine(pixelY, nodeX[i+1], nodeX[i+1] - nodeX[i], LCD_DIR_HORIZONTAL);\r
+        LCD_SetTextColor(TextColor);\r
+        PutPixel(pixelY, nodeX[i+1]);\r
+        PutPixel(pixelY, nodeX[i]);\r
+        /* for (j=nodeX[i]; j<nodeX[i+1]; j++) PutPixel(j,pixelY); */\r
+      }\r
+    }\r
+  }\r
+\r
+  /* draw the edges */\r
+  LCD_SetTextColor(TextColor);\r
+}\r
+\r
+/**\r
+  * @brief  Reset LCD control line(/CS) and Send Start-Byte\r
+  * @param  Start_Byte: the Start-Byte to be sent\r
+  * @retval None\r
+  */\r
+void LCD_nCS_StartByte(uint8_t Start_Byte)\r
+{\r
+  LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_RESET);\r
+\r
+  SPI_SendData(LCD_SPI, Start_Byte);\r
+\r
+  while(SPI_GetFlagStatus(LCD_SPI, SPI_FLAG_BSY) != RESET)\r
+  {\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  * @brief  Writes index to select the LCD register.\r
+  * @param  LCD_Reg: address of the selected register.\r
+  * @retval None\r
+  */\r
+void LCD_WriteRegIndex(uint8_t LCD_Reg)\r
+{\r
+  /* Reset LCD control line(/CS) and Send Start-Byte */\r
+  LCD_nCS_StartByte(START_BYTE | SET_INDEX);\r
+\r
+  /* Write 16-bit Reg Index (High Byte is 0) */\r
+  SPI_SendData(LCD_SPI, 0x00);\r
+\r
+  while(SPI_GetFlagStatus(LCD_SPI, SPI_FLAG_BSY) != RESET)\r
+  {\r
+  }\r
+\r
+  SPI_SendData(LCD_SPI, LCD_Reg);\r
+\r
+  while(SPI_GetFlagStatus(LCD_SPI, SPI_FLAG_BSY) != RESET)\r
+  {\r
+  }\r
+\r
+  LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET);\r
+}\r
+\r
+\r
+/**\r
+  * @brief  Writes to the selected LCD ILI9320 register.\r
+  * @param  LCD_Reg: address of the selected register.\r
+  * @param  LCD_RegValue: value to write to the selected register.\r
+  * @retval None\r
+  */\r
+void LCD_WriteReg(uint8_t LCD_Reg, uint16_t LCD_RegValue)\r
+{\r
+  /* Write 16-bit Index (then Write Reg) */\r
+  LCD_WriteRegIndex(LCD_Reg);\r
+\r
+  /* Write 16-bit Reg */\r
+  /* Reset LCD control line(/CS) and Send Start-Byte */\r
+  LCD_nCS_StartByte(START_BYTE | LCD_WRITE_REG);\r
+\r
+  SPI_SendData(LCD_SPI, LCD_RegValue >> 8);\r
+\r
+  while(SPI_GetFlagStatus(LCD_SPI, SPI_FLAG_BSY) != RESET)\r
+  {\r
+  }\r
+\r
+  SPI_SendData(LCD_SPI, (LCD_RegValue & 0xFF));\r
+\r
+  while(SPI_GetFlagStatus(LCD_SPI, SPI_FLAG_BSY) != RESET)\r
+  {\r
+  }\r
+\r
+  LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET);\r
+}\r
+\r
+\r
+/**\r
+  * @brief  Reads the selected LCD Register.\r
+  * @param  LCD_Reg: address of the selected register.\r
+  * @retval LCD Register Value.\r
+  */\r
+uint16_t LCD_ReadReg(uint8_t LCD_Reg)\r
+{\r
+  uint16_t tmp = 0;\r
+  uint8_t i = 0;\r
+\r
+  /* LCD_SPI prescaler: 4 */\r
+  LCD_SPI->CR1 &= 0xFFC7;\r
+  LCD_SPI->CR1 |= 0x0008;\r
+  /* Write 16-bit Index (then Read Reg) */\r
+  LCD_WriteRegIndex(LCD_Reg);\r
+  /* Read 16-bit Reg */\r
+  /* Reset LCD control line(/CS) and Send Start-Byte */\r
+  LCD_nCS_StartByte(START_BYTE | LCD_READ_REG);\r
+\r
+  for(i = 0; i < 5; i++)\r
+  {\r
+    SPI_SendData(LCD_SPI, 0xFF);\r
+    while(SPI_GetFlagStatus(LCD_SPI, SPI_FLAG_BSY) != RESET)\r
+    {\r
+    }\r
+    /* One byte of invalid dummy data read after the start byte */\r
+    while(SPI_GetFlagStatus(LCD_SPI, SPI_FLAG_RXNE) == RESET)\r
+    {\r
+    }\r
+    SPI_ReceiveData(LCD_SPI);\r
+  }\r
+\r
+  SPI_SendData(LCD_SPI, 0xFF);\r
+\r
+  /* Read upper byte */\r
+  while(SPI_GetFlagStatus(LCD_SPI, SPI_FLAG_BSY) != RESET)\r
+  {\r
+  }\r
+\r
+  /* Read lower byte */\r
+  while(SPI_GetFlagStatus(LCD_SPI, SPI_FLAG_RXNE) == RESET)\r
+  {\r
+  }\r
+  tmp = SPI_ReceiveData(LCD_SPI);\r
+\r
+\r
+  SPI_SendData(LCD_SPI, 0xFF);\r
+  while(SPI_GetFlagStatus(LCD_SPI, SPI_FLAG_BSY) != RESET)\r
+  {\r
+  }\r
+\r
+  /* Read lower byte */\r
+  while(SPI_GetFlagStatus(LCD_SPI, SPI_FLAG_RXNE) == RESET)\r
+  {\r
+  }\r
+\r
+  tmp = ((tmp & 0xFF) << 8) | SPI_ReceiveData(LCD_SPI);\r
+  LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET);\r
+\r
+  /* LCD_SPI prescaler: 2 */\r
+  LCD_SPI->CR1 &= 0xFFC7;\r
+\r
+  return tmp;\r
+}\r
+\r
+\r
+/**\r
+  * @brief  Prepare to write to the LCD RAM.\r
+  * @param  None\r
+  * @retval None\r
+  */\r
+void LCD_WriteRAM_Prepare(void)\r
+{\r
+  LCD_WriteRegIndex(LCD_REG_34); /* Select GRAM Reg */\r
+\r
+  /* Reset LCD control line(/CS) and Send Start-Byte */\r
+  LCD_nCS_StartByte(START_BYTE | LCD_WRITE_REG);\r
+}\r
+\r
+\r
+/**\r
+  * @brief  Writes 1 word to the LCD RAM.\r
+  * @param  RGB_Code: the pixel color in RGB mode (5-6-5).\r
+  * @retval None\r
+  */\r
+void LCD_WriteRAMWord(uint16_t RGB_Code)\r
+{\r
+  LCD_WriteRAM_Prepare();\r
+\r
+  LCD_WriteRAM(RGB_Code);\r
+\r
+  LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET);\r
+}\r
+\r
+/**\r
+  * @brief  Writes to the LCD RAM.\r
+  * @param  RGB_Code: the pixel color in RGB mode (5-6-5).\r
+  * @retval None\r
+  */\r
+void LCD_WriteRAM(uint16_t RGB_Code)\r
+{\r
+  SPI_SendData(LCD_SPI, RGB_Code >> 8);\r
+  while(SPI_GetFlagStatus(LCD_SPI, SPI_FLAG_BSY) != RESET)\r
+  {\r
+  }\r
+  SPI_SendData(LCD_SPI, RGB_Code & 0xFF);\r
+  while(SPI_GetFlagStatus(LCD_SPI, SPI_FLAG_BSY) != RESET)\r
+  {\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  * @brief  Power on the LCD.\r
+  * @param  None\r
+  * @retval None\r
+  */\r
+void LCD_PowerOn(void)\r
+{\r
+  /* Power On sequence ---------------------------------------------------------*/\r
+  LCD_WriteReg(LCD_REG_16, 0x0000); /* SAP, BT[3:0], AP, DSTB, SLP, STB */\r
+  LCD_WriteReg(LCD_REG_17, 0x0000); /* DC1[2:0], DC0[2:0], VC[2:0] */\r
+  LCD_WriteReg(LCD_REG_18, 0x0000); /* VREG1OUT voltage */\r
+  LCD_WriteReg(LCD_REG_19, 0x0000); /* VDV[4:0] for VCOM amplitude */\r
+  _delay_(20);                 /* Dis-charge capacitor power voltage (200ms) */\r
+  LCD_WriteReg(LCD_REG_16, 0x17B0); /* SAP, BT[3:0], AP, DSTB, SLP, STB */\r
+  LCD_WriteReg(LCD_REG_17, 0x0137); /* DC1[2:0], DC0[2:0], VC[2:0] */\r
+  _delay_(5);                /* Delay 50 ms */\r
+  LCD_WriteReg(LCD_REG_18, 0x0139); /* VREG1OUT voltage */\r
+  _delay_(5);                /* delay 50 ms */\r
+  LCD_WriteReg(LCD_REG_19, 0x1d00); /* VDV[4:0] for VCOM amplitude */\r
+  LCD_WriteReg(LCD_REG_41, 0x0013); /* VCM[4:0] for VCOMH */\r
+  _delay_(5);                /* delay 50 ms */\r
+  LCD_WriteReg(LCD_REG_7, 0x0173);  /* 262K color and display ON */\r
+}\r
+\r
+\r
+/**\r
+  * @brief  Enables the Display.\r
+  * @param  None\r
+  * @retval None\r
+  */\r
+void LCD_DisplayOn(void)\r
+{\r
+  /* Display On */\r
+  LCD_WriteReg(LCD_REG_7, 0x0173); /* 262K color and display ON */\r
+}\r
+\r
+\r
+/**\r
+  * @brief  Disables the Display.\r
+  * @param  None\r
+  * @retval None\r
+  */\r
+void LCD_DisplayOff(void)\r
+{\r
+  /* Display Off */\r
+  LCD_WriteReg(LCD_REG_7, 0x0);\r
+}\r
+\r
+\r
+/**\r
+  * @brief  Configures LCD control lines in Output Push-Pull mode.\r
+  * @param  None\r
+  * @retval None\r
+  */\r
+void LCD_CtrlLinesConfig(void)\r
+{\r
+  GPIO_InitTypeDef GPIO_InitStructure;\r
+\r
+  RCC_AHBPeriphClockCmd(LCD_NCS_GPIO_CLK, ENABLE);\r
+\r
+  /* Configure NCS (PF.02) in Output Push-Pull mode */\r
+  GPIO_InitStructure.GPIO_Pin = LCD_NCS_PIN;\r
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz;\r
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT;\r
+  GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;\r
+  GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;\r
+  GPIO_Init(LCD_NCS_GPIO_PORT, &GPIO_InitStructure);\r
+\r
+  LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET);\r
+}\r
+\r
+\r
+/**\r
+  * @brief  Sets or reset LCD control lines.\r
+  * @param  GPIOx: where x can be B or D to select the GPIO peripheral.\r
+  * @param  CtrlPins: the Control line.\r
+  *   This parameter can be:\r
+  *     @arg LCD_NCS_PIN: Chip Select pin\r
+  *     @arg LCD_NWR_PIN: Read/Write Selection pin\r
+  *     @arg LCD_RS_PIN: Register/RAM Selection pin\r
+  * @param  BitVal: specifies the value to be written to the selected bit.\r
+  *   This parameter can be:\r
+  *     @arg Bit_RESET: to clear the port pin\r
+  *     @arg Bit_SET: to set the port pin\r
+  * @retval None\r
+  */\r
+void LCD_CtrlLinesWrite(GPIO_TypeDef* GPIOx, uint16_t CtrlPins, BitAction BitVal)\r
+{\r
+  /* Set or Reset the control line */\r
+  GPIO_WriteBit(GPIOx, CtrlPins, BitVal);\r
+}\r
+\r
+\r
+/**\r
+  * @brief  Configures the LCD_SPI interface.\r
+  * @param  None\r
+  * @retval None\r
+  */\r
+void LCD_SPIConfig(void)\r
+{\r
+  SPI_InitTypeDef    SPI_InitStructure;\r
+  GPIO_InitTypeDef   GPIO_InitStructure;\r
+\r
+  /* Enable LCD_SPI_SCK_GPIO_CLK, LCD_SPI_MISO_GPIO_CLK and LCD_SPI_MOSI_GPIO_CLK clock */\r
+  RCC_AHBPeriphClockCmd(LCD_SPI_SCK_GPIO_CLK | LCD_SPI_MISO_GPIO_CLK | LCD_SPI_MOSI_GPIO_CLK, ENABLE);\r
+\r
+  /* Enable LCD_SPI and SYSCFG clock  */\r
+  RCC_APB2PeriphClockCmd(LCD_SPI_CLK | RCC_APB2Periph_SYSCFG, ENABLE);\r
+\r
+  /* Configure LCD_SPI SCK pin */\r
+  GPIO_InitStructure.GPIO_Pin = LCD_SPI_SCK_PIN;\r
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_40MHz;\r
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;\r
+  GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;\r
+  GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;\r
+  GPIO_Init(LCD_SPI_SCK_GPIO_PORT, &GPIO_InitStructure);\r
+\r
+  /* Configure LCD_SPI MISO pin */\r
+  GPIO_InitStructure.GPIO_Pin = LCD_SPI_MISO_PIN;\r
+  GPIO_Init(LCD_SPI_MISO_GPIO_PORT, &GPIO_InitStructure);\r
+\r
+  /* Configure LCD_SPI MOSI pin */\r
+  GPIO_InitStructure.GPIO_Pin = LCD_SPI_MOSI_PIN;\r
+  GPIO_Init(LCD_SPI_MOSI_GPIO_PORT, &GPIO_InitStructure);\r
+\r
+  /* Connect PE.13 to SPI SCK */\r
+  GPIO_PinAFConfig(LCD_SPI_SCK_GPIO_PORT, LCD_SPI_SCK_SOURCE, LCD_SPI_SCK_AF);\r
+\r
+  /* Connect PE.14 to SPI MISO */\r
+  GPIO_PinAFConfig(LCD_SPI_MISO_GPIO_PORT, LCD_SPI_MISO_SOURCE, LCD_SPI_MISO_AF);\r
+\r
+  /* Connect PE.15 to SPI MOSI */\r
+  GPIO_PinAFConfig(LCD_SPI_MOSI_GPIO_PORT, LCD_SPI_MOSI_SOURCE, LCD_SPI_MOSI_AF);\r
+\r
+  SPI_DeInit(LCD_SPI);\r
+\r
+  /* SPI Config */\r
+  SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex;\r
+  SPI_InitStructure.SPI_Mode = SPI_Mode_Master;\r
+  SPI_InitStructure.SPI_DataSize = SPI_DataSize_8b;\r
+  SPI_InitStructure.SPI_CPOL = SPI_CPOL_High;\r
+  SPI_InitStructure.SPI_CPHA = SPI_CPHA_2Edge;\r
+  SPI_InitStructure.SPI_NSS = SPI_NSS_Soft;\r
+  SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2;\r
+  SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB;\r
+  SPI_InitStructure.SPI_CRCPolynomial = 7;\r
+  SPI_Init(LCD_SPI, &SPI_InitStructure);\r
+\r
+  /* SPI enable */\r
+  SPI_Cmd(LCD_SPI, ENABLE);\r
+}\r
+\r
+/**\r
+  * @brief  Displays a pixel.\r
+  * @param  x: pixel x.\r
+  * @param  y: pixel y.\r
+  * @retval None\r
+  */\r
+static void PutPixel(int16_t x, int16_t y)\r
+{\r
+  if(x < 0 || x > 239 || y < 0 || y > 319)\r
+  {\r
+    return;\r
+  }\r
+  LCD_DrawLine(x, y, 1, LCD_DIR_HORIZONTAL);\r
+}\r
+\r
+#ifndef USE_Delay\r
+/**\r
+  * @brief  Inserts a delay time.\r
+  * @param  nCount: specifies the delay time length.\r
+  * @retval None\r
+  */\r
+static void delay(__IO uint32_t nCount)\r
+{\r
+  __IO uint32_t index = 0;\r
+  for(index = (34000 * nCount); index != 0; index--)\r
+  {\r
+  }\r
+}\r
+#endif /* USE_Delay*/\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r

diff --git a/Demo/CORTEX_STM32L152_IAR/system_and_ST_code/STM32L152_EVAL/stm32l152_eval_lcd.h b/Demo/CORTEX_STM32L152_IAR/system_and_ST_code/STM32L152_EVAL/stm32l152_eval_lcd.h
new file mode 100644 (file)
index 0000000..e3c06a1
--- /dev/null
+++ b/Demo/CORTEX_STM32L152_IAR/system_and_ST_code/STM32L152_EVAL/stm32l152_eval_lcd.h
@@ -0,0 +1,391 @@
+/**\r
+  ******************************************************************************\r
+  * @file    stm32l152_eval_lcd.h\r
+  * @author  MCD Application Team\r
+  * @version V4.4.0RC1\r
+  * @date    07/02/2010\r
+  * @brief   This file contains all the functions prototypes for the stm32l152_eval_lcd\r
+  *          firmware driver.\r
+  ******************************************************************************\r
+  * @copy\r
+  *\r
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+  *\r
+  * <h2><center>&copy; COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+  */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32L152_EVAL_LCD_H\r
+#define __STM32L152_EVAL_LCD_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx.h"\r
+#include "../Common/fonts.h"\r
+\r
+/** @addtogroup Utilities\r
+  * @{\r
+  */\r
+\r
+/** @addtogroup STM32_EVAL\r
+  * @{\r
+  */\r
+\r
+/** @addtogroup STM32L152_EVAL\r
+  * @{\r
+  */\r
+\r
+/** @addtogroup STM32L152_EVAL_LCD\r
+  * @{\r
+  */\r
+\r
+\r
+/** @defgroup STM32L152_EVAL_LCD_Exported_Types\r
+  * @{\r
+  */\r
+typedef struct\r
+{\r
+  int16_t X;\r
+  int16_t Y;\r
+} Point, * pPoint;\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup STM32L152_EVAL_LCD_Exported_Constants\r
+  * @{\r
+  */\r
+\r
+/**\r
+ * @brief Uncomment the line below if you want to use LCD_DrawBMP function to\r
+ *        display a bitmap picture on the LCD. This function assumes that the bitmap\r
+ *        file is loaded in the SPI Flash (mounted on STM32L152-EVAL board), however\r
+ *        user can tailor it according to his application hardware requirement.\r
+ */\r
+/*#define USE_LCD_DrawBMP*/\r
+\r
+/**\r
+ * @brief Uncomment the line below if you want to use user defined Delay function\r
+ *        (for precise timing), otherwise default _delay_ function defined within\r
+ *         this driver is used (less precise timing).\r
+ */\r
+/* #define USE_Delay */\r
+\r
+#ifdef USE_Delay\r
+#include "main.h"\r
+\r
+  #define _delay_     Delay  /* !< User can provide more timing precise _delay_ function\r
+                                   (with 10ms time base), using SysTick for example */\r
+#else\r
+  #define _delay_     delay      /* !< Default _delay_ function with less precise timing */\r
+#endif\r
+\r
+\r
+/**\r
+  * @brief  LCD Control pins\r
+  */\r
+#define LCD_NCS_PIN             GPIO_Pin_2\r
+#define LCD_NCS_GPIO_PORT       GPIOH\r
+#define LCD_NCS_GPIO_CLK        RCC_AHBPeriph_GPIOH\r
+\r
+/**\r
+  * @brief  LCD SPI Interface pins\r
+  */\r
+#define LCD_SPI_SCK_PIN               GPIO_Pin_13                    /* PE.13 */\r
+#define LCD_SPI_SCK_GPIO_PORT         GPIOE                          /* GPIOE */\r
+#define LCD_SPI_SCK_GPIO_CLK          RCC_AHBPeriph_GPIOE\r
+#define LCD_SPI_SCK_SOURCE            GPIO_PinSource13\r
+#define LCD_SPI_SCK_AF                GPIO_AF_SPI1\r
+#define LCD_SPI_MISO_PIN              GPIO_Pin_14                    /* PE.14 */\r
+#define LCD_SPI_MISO_GPIO_PORT        GPIOE                          /* GPIOE */\r
+#define LCD_SPI_MISO_GPIO_CLK         RCC_AHBPeriph_GPIOE\r
+#define LCD_SPI_MISO_SOURCE           GPIO_PinSource14\r
+#define LCD_SPI_MISO_AF               GPIO_AF_SPI1\r
+#define LCD_SPI_MOSI_PIN              GPIO_Pin_15                    /* PE.15 */\r
+#define LCD_SPI_MOSI_GPIO_PORT        GPIOE                          /* GPIOE */\r
+#define LCD_SPI_MOSI_GPIO_CLK         RCC_AHBPeriph_GPIOE\r
+#define LCD_SPI_MOSI_SOURCE           GPIO_PinSource15\r
+#define LCD_SPI_MOSI_AF               GPIO_AF_SPI1\r
+#define LCD_SPI                       SPI1\r
+#define LCD_SPI_CLK                   RCC_APB2Periph_SPI1\r
+\r
+\r
+/**\r
+  * @brief  LCD Registers\r
+  */\r
+#define LCD_REG_0             0x00\r
+#define LCD_REG_1             0x01\r
+#define LCD_REG_2             0x02\r
+#define LCD_REG_3             0x03\r
+#define LCD_REG_4             0x04\r
+#define LCD_REG_5             0x05\r
+#define LCD_REG_6             0x06\r
+#define LCD_REG_7             0x07\r
+#define LCD_REG_8             0x08\r
+#define LCD_REG_9             0x09\r
+#define LCD_REG_10            0x0A\r
+#define LCD_REG_12            0x0C\r
+#define LCD_REG_13            0x0D\r
+#define LCD_REG_14            0x0E\r
+#define LCD_REG_15            0x0F\r
+#define LCD_REG_16            0x10\r
+#define LCD_REG_17            0x11\r
+#define LCD_REG_18            0x12\r
+#define LCD_REG_19            0x13\r
+#define LCD_REG_20            0x14\r
+#define LCD_REG_21            0x15\r
+#define LCD_REG_22            0x16\r
+#define LCD_REG_23            0x17\r
+#define LCD_REG_24            0x18\r
+#define LCD_REG_25            0x19\r
+#define LCD_REG_26            0x1A\r
+#define LCD_REG_27            0x1B\r
+#define LCD_REG_28            0x1C\r
+#define LCD_REG_29            0x1D\r
+#define LCD_REG_30            0x1E\r
+#define LCD_REG_31            0x1F\r
+#define LCD_REG_32            0x20\r
+#define LCD_REG_33            0x21\r
+#define LCD_REG_34            0x22\r
+#define LCD_REG_36            0x24\r
+#define LCD_REG_37            0x25\r
+#define LCD_REG_40            0x28\r
+#define LCD_REG_41            0x29\r
+#define LCD_REG_43            0x2B\r
+#define LCD_REG_45            0x2D\r
+#define LCD_REG_48            0x30\r
+#define LCD_REG_49            0x31\r
+#define LCD_REG_50            0x32\r
+#define LCD_REG_51            0x33\r
+#define LCD_REG_52            0x34\r
+#define LCD_REG_53            0x35\r
+#define LCD_REG_54            0x36\r
+#define LCD_REG_55            0x37\r
+#define LCD_REG_56            0x38\r
+#define LCD_REG_57            0x39\r
+#define LCD_REG_59            0x3B\r
+#define LCD_REG_60            0x3C\r
+#define LCD_REG_61            0x3D\r
+#define LCD_REG_62            0x3E\r
+#define LCD_REG_63            0x3F\r
+#define LCD_REG_64            0x40\r
+#define LCD_REG_65            0x41\r
+#define LCD_REG_66            0x42\r
+#define LCD_REG_67            0x43\r
+#define LCD_REG_68            0x44\r
+#define LCD_REG_69            0x45\r
+#define LCD_REG_70            0x46\r
+#define LCD_REG_71            0x47\r
+#define LCD_REG_72            0x48\r
+#define LCD_REG_73            0x49\r
+#define LCD_REG_74            0x4A\r
+#define LCD_REG_75            0x4B\r
+#define LCD_REG_76            0x4C\r
+#define LCD_REG_77            0x4D\r
+#define LCD_REG_78            0x4E\r
+#define LCD_REG_79            0x4F\r
+#define LCD_REG_80            0x50\r
+#define LCD_REG_81            0x51\r
+#define LCD_REG_82            0x52\r
+#define LCD_REG_83            0x53\r
+#define LCD_REG_96            0x60\r
+#define LCD_REG_97            0x61\r
+#define LCD_REG_106           0x6A\r
+#define LCD_REG_118           0x76\r
+#define LCD_REG_128           0x80\r
+#define LCD_REG_129           0x81\r
+#define LCD_REG_130           0x82\r
+#define LCD_REG_131           0x83\r
+#define LCD_REG_132           0x84\r
+#define LCD_REG_133           0x85\r
+#define LCD_REG_134           0x86\r
+#define LCD_REG_135           0x87\r
+#define LCD_REG_136           0x88\r
+#define LCD_REG_137           0x89\r
+#define LCD_REG_139           0x8B\r
+#define LCD_REG_140           0x8C\r
+#define LCD_REG_141           0x8D\r
+#define LCD_REG_143           0x8F\r
+#define LCD_REG_144           0x90\r
+#define LCD_REG_145           0x91\r
+#define LCD_REG_146           0x92\r
+#define LCD_REG_147           0x93\r
+#define LCD_REG_148           0x94\r
+#define LCD_REG_149           0x95\r
+#define LCD_REG_150           0x96\r
+#define LCD_REG_151           0x97\r
+#define LCD_REG_152           0x98\r
+#define LCD_REG_153           0x99\r
+#define LCD_REG_154           0x9A\r
+#define LCD_REG_157           0x9D\r
+#define LCD_REG_192           0xC0\r
+#define LCD_REG_193           0xC1\r
+#define LCD_REG_227           0xE3\r
+#define LCD_REG_229           0xE5\r
+#define LCD_REG_231           0xE7\r
+#define LCD_REG_239           0xEF\r
+\r
+\r
+/**\r
+  * @brief  LCD color\r
+  */\r
+#define LCD_COLOR_WHITE          0xFFFF\r
+#define LCD_COLOR_BLACK          0x0000\r
+#define LCD_COLOR_GREY           0xF7DE\r
+#define LCD_COLOR_BLUE           0x001F\r
+#define LCD_COLOR_BLUE2          0x051F\r
+#define LCD_COLOR_RED            0xF800\r
+#define LCD_COLOR_MAGENTA        0xF81F\r
+#define LCD_COLOR_GREEN          0x07E0\r
+#define LCD_COLOR_CYAN           0x7FFF\r
+#define LCD_COLOR_YELLOW         0xFFE0\r
+\r
+/**\r
+  * @brief  LCD Lines depending on the chosen fonts.\r
+  */\r
+#define LCD_LINE_0               LINE(0)\r
+#define LCD_LINE_1               LINE(1)\r
+#define LCD_LINE_2               LINE(2)\r
+#define LCD_LINE_3               LINE(3)\r
+#define LCD_LINE_4               LINE(4)\r
+#define LCD_LINE_5               LINE(5)\r
+#define LCD_LINE_6               LINE(6)\r
+#define LCD_LINE_7               LINE(7)\r
+#define LCD_LINE_8               LINE(8)\r
+#define LCD_LINE_9               LINE(9)\r
+#define LCD_LINE_10              LINE(10)\r
+#define LCD_LINE_11              LINE(11)\r
+#define LCD_LINE_12              LINE(12)\r
+#define LCD_LINE_13              LINE(13)\r
+#define LCD_LINE_14              LINE(14)\r
+#define LCD_LINE_15              LINE(15)\r
+#define LCD_LINE_16              LINE(16)\r
+#define LCD_LINE_17              LINE(17)\r
+#define LCD_LINE_18              LINE(18)\r
+#define LCD_LINE_19              LINE(19)\r
+#define LCD_LINE_20              LINE(20)\r
+#define LCD_LINE_21              LINE(21)\r
+#define LCD_LINE_22              LINE(22)\r
+#define LCD_LINE_23              LINE(23)\r
+#define LCD_LINE_24              LINE(24)\r
+#define LCD_LINE_25              LINE(25)\r
+#define LCD_LINE_26              LINE(26)\r
+#define LCD_LINE_27              LINE(27)\r
+#define LCD_LINE_28              LINE(28)\r
+#define LCD_LINE_29              LINE(29)\r
+\r
+\r
+/**\r
+  * @brief LCD default font\r
+  */\r
+#define LCD_DEFAULT_FONT         Font16x24\r
+\r
+/**\r
+  * @brief  LCD Direction\r
+  */\r
+#define LCD_DIR_HORIZONTAL       0x0000\r
+#define LCD_DIR_VERTICAL         0x0001\r
+\r
+/**\r
+  * @brief  LCD Size (Width and Height)\r
+  */\r
+#define LCD_PIXEL_WIDTH          0x0140\r
+#define LCD_PIXEL_HEIGHT         0x00F0\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup STM32L152_EVAL_LCD_Exported_Macros\r
+  * @{\r
+  */\r
+#define ASSEMBLE_RGB(R, G, B)    ((((R)& 0xF8) << 8) | (((G) & 0xFC) << 3) | (((B) & 0xF8) >> 3))\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup STM32L152_EVAL_LCD_Exported_Functions\r
+  * @{\r
+  */\r
+void STM32L152_LCD_DeInit(void);\r
+void LCD_Setup(void);\r
+void STM32L152_LCD_Init(void);\r
+void LCD_SetColors(__IO uint16_t _TextColor, __IO uint16_t _BackColor);\r
+void LCD_GetColors(__IO uint16_t *_TextColor, __IO uint16_t *_BackColor);\r
+void LCD_SetTextColor(__IO uint16_t Color);\r
+void LCD_SetBackColor(__IO uint16_t Color);\r
+void LCD_ClearLine(uint8_t Line);\r
+void LCD_Clear(uint16_t Color);\r
+void LCD_SetCursor(uint8_t Xpos, uint16_t Ypos);\r
+void LCD_DrawChar(uint8_t Xpos, uint16_t Ypos, const uint16_t *c);\r
+void LCD_DisplayChar(uint8_t Line, uint16_t Column, uint8_t Ascii);\r
+void LCD_SetFont(sFONT *fonts);\r
+sFONT *LCD_GetFont(void);\r
+void LCD_DisplayStringLine(uint8_t Line, uint8_t *ptr);\r
+void LCD_SetDisplayWindow(uint8_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width);\r
+void LCD_WindowModeDisable(void);\r
+void LCD_DrawLine(uint8_t Xpos, uint16_t Ypos, uint16_t Length, uint8_t Direction);\r
+void LCD_DrawRect(uint8_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width);\r
+void LCD_DrawCircle(uint8_t Xpos, uint16_t Ypos, uint16_t Radius);\r
+void LCD_DrawMonoPict(const uint32_t *Pict);\r
+void LCD_DrawBMP(uint32_t BmpAddress);\r
+void LCD_DrawUniLine(uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2);\r
+void LCD_DrawFullRect(uint16_t Xpos, uint16_t Ypos, uint16_t Width, uint16_t Height);\r
+void LCD_DrawFullCircle(uint16_t Xpos, uint16_t Ypos, uint16_t Radius);\r
+void LCD_PolyLine(pPoint Points, uint16_t PointCount);\r
+void LCD_PolyLineRelative(pPoint Points, uint16_t PointCount);\r
+void LCD_ClosedPolyLine(pPoint Points, uint16_t PointCount);\r
+void LCD_ClosedPolyLineRelative(pPoint Points, uint16_t PointCount);\r
+void LCD_FillPolyLine(pPoint Points, uint16_t PointCount);\r
+void LCD_nCS_StartByte(uint8_t Start_Byte);\r
+void LCD_WriteRegIndex(uint8_t LCD_Reg);\r
+void LCD_WriteReg(uint8_t LCD_Reg, uint16_t LCD_RegValue);\r
+void LCD_WriteRAM_Prepare(void);\r
+void LCD_WriteRAMWord(uint16_t RGB_Code);\r
+uint16_t LCD_ReadReg(uint8_t LCD_Reg);\r
+void LCD_WriteRAM(uint16_t RGB_Code);\r
+void LCD_PowerOn(void);\r
+void LCD_DisplayOn(void);\r
+void LCD_DisplayOff(void);\r
+\r
+void LCD_CtrlLinesConfig(void);\r
+void LCD_CtrlLinesWrite(GPIO_TypeDef* GPIOx, uint16_t CtrlPins, BitAction BitVal);\r
+void LCD_SPIConfig(void);\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32L152_EVAL_LCD_H */\r
+\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r

diff --git a/Demo/CORTEX_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/inc/misc.h b/Demo/CORTEX_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/inc/misc.h
new file mode 100644 (file)
index 0000000..6ae338d
--- /dev/null
+++ b/Demo/CORTEX_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/inc/misc.h
@@ -0,0 +1,219 @@
+/**\r
+  ******************************************************************************\r
+  * @file    misc.h\r
+  * @author  MCD Application Team\r
+  * @version V1.0.0RC1\r
+  * @date    07/02/2010\r
+  * @brief   This file contains all the functions prototypes for the miscellaneous\r
+  *          firmware library functions (add-on to CMSIS functions).\r
+  ******************************************************************************\r
+  * @copy\r
+  *\r
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+  *\r
+  * <h2><center>&copy; COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+  */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __MISC_H\r
+#define __MISC_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+  * @{\r
+  */\r
+\r
+/** @addtogroup MISC\r
+  * @{\r
+  */\r
+\r
+/** @defgroup MISC_Exported_Types\r
+  * @{\r
+  */\r
+\r
+/** \r
+  * @brief  NVIC Init Structure definition  \r
+  */\r
+\r
+typedef struct\r
+{\r
+  uint8_t NVIC_IRQChannel;                    /*!< Specifies the IRQ channel to be enabled or disabled.\r
+                                                   This parameter can be a value of @ref IRQn_Type \r
+                                                   (For the complete STM32 Devices IRQ Channels list, please\r
+                                                    refer to stm32l1xx.h file) */\r
+\r
+  uint8_t NVIC_IRQChannelPreemptionPriority;  /*!< Specifies the pre-emption priority for the IRQ channel\r
+                                                   specified in NVIC_IRQChannel. This parameter can be a value\r
+                                                   between 0 and 15 as described in the table @ref NVIC_Priority_Table */\r
+\r
+  uint8_t NVIC_IRQChannelSubPriority;         /*!< Specifies the subpriority level for the IRQ channel specified\r
+                                                   in NVIC_IRQChannel. This parameter can be a value\r
+                                                   between 0 and 15 as described in the table @ref NVIC_Priority_Table */\r
+\r
+  FunctionalState NVIC_IRQChannelCmd;         /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel\r
+                                                   will be enabled or disabled. \r
+                                                   This parameter can be set either to ENABLE or DISABLE */   \r
+} NVIC_InitTypeDef;\r
+ \r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup NVIC_Priority_Table \r
+  * @{\r
+  */\r
+\r
+/**\r
+@code  \r
+ The table below gives the allowed values of the pre-emption priority and subpriority according\r
+ to the Priority Grouping configuration performed by NVIC_PriorityGroupConfig function\r
+  ============================================================================================================================\r
+    NVIC_PriorityGroup   | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority  | Description\r
+  ============================================================================================================================\r
+   NVIC_PriorityGroup_0  |                0                  |            0-15             |   0 bits for pre-emption priority\r
+                         |                                   |                             |   4 bits for subpriority\r
+  ----------------------------------------------------------------------------------------------------------------------------\r
+   NVIC_PriorityGroup_1  |                0-1                |            0-7              |   1 bits for pre-emption priority\r
+                         |                                   |                             |   3 bits for subpriority\r
+  ----------------------------------------------------------------------------------------------------------------------------    \r
+   NVIC_PriorityGroup_2  |                0-3                |            0-3              |   2 bits for pre-emption priority\r
+                         |                                   |                             |   2 bits for subpriority\r
+  ----------------------------------------------------------------------------------------------------------------------------    \r
+   NVIC_PriorityGroup_3  |                0-7                |            0-1              |   3 bits for pre-emption priority\r
+                         |                                   |                             |   1 bits for subpriority\r
+  ----------------------------------------------------------------------------------------------------------------------------    \r
+   NVIC_PriorityGroup_4  |                0-15               |            0                |   4 bits for pre-emption priority\r
+                         |                                   |                             |   0 bits for subpriority                       \r
+  ============================================================================================================================\r
+@endcode\r
+*/\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup MISC_Exported_Constants\r
+  * @{\r
+  */\r
+\r
+/** @defgroup Vector_Table_Base \r
+  * @{\r
+  */\r
+\r
+#define NVIC_VectTab_RAM             ((uint32_t)0x20000000)\r
+#define NVIC_VectTab_FLASH           ((uint32_t)0x08000000)\r
+#define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || \\r
+                                  ((VECTTAB) == NVIC_VectTab_FLASH))\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup System_Low_Power \r
+  * @{\r
+  */\r
+\r
+#define NVIC_LP_SEVONPEND            ((uint8_t)0x10)\r
+#define NVIC_LP_SLEEPDEEP            ((uint8_t)0x04)\r
+#define NVIC_LP_SLEEPONEXIT          ((uint8_t)0x02)\r
+#define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \\r
+                        ((LP) == NVIC_LP_SLEEPDEEP) || \\r
+                        ((LP) == NVIC_LP_SLEEPONEXIT))\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup Preemption_Priority_Group \r
+  * @{\r
+  */\r
+\r
+#define NVIC_PriorityGroup_0         ((uint32_t)0x700) /*!< 0 bits for pre-emption priority\r
+                                                            4 bits for subpriority */\r
+#define NVIC_PriorityGroup_1         ((uint32_t)0x600) /*!< 1 bits for pre-emption priority\r
+                                                            3 bits for subpriority */\r
+#define NVIC_PriorityGroup_2         ((uint32_t)0x500) /*!< 2 bits for pre-emption priority\r
+                                                            2 bits for subpriority */\r
+#define NVIC_PriorityGroup_3         ((uint32_t)0x400) /*!< 3 bits for pre-emption priority\r
+                                                            1 bits for subpriority */\r
+#define NVIC_PriorityGroup_4         ((uint32_t)0x300) /*!< 4 bits for pre-emption priority\r
+                                                            0 bits for subpriority */\r
+\r
+#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PriorityGroup_0) || \\r
+                                       ((GROUP) == NVIC_PriorityGroup_1) || \\r
+                                       ((GROUP) == NVIC_PriorityGroup_2) || \\r
+                                       ((GROUP) == NVIC_PriorityGroup_3) || \\r
+                                       ((GROUP) == NVIC_PriorityGroup_4))\r
+\r
+#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY)  ((PRIORITY) < 0x10)\r
+\r
+#define IS_NVIC_SUB_PRIORITY(PRIORITY)  ((PRIORITY) < 0x10)\r
+\r
+#define IS_NVIC_OFFSET(OFFSET)  ((OFFSET) < 0x0001FFFF)\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup SysTick_clock_source \r
+  * @{\r
+  */\r
+\r
+#define SysTick_CLKSource_HCLK_Div8    ((uint32_t)0xFFFFFFFB)\r
+#define SysTick_CLKSource_HCLK         ((uint32_t)0x00000004)\r
+#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_HCLK) || \\r
+                                       ((SOURCE) == SysTick_CLKSource_HCLK_Div8))\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup MISC_Exported_Macros\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup MISC_Exported_Functions\r
+  * @{\r
+  */\r
+\r
+void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup);\r
+void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct);\r
+void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset);\r
+void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState);\r
+void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __MISC_H */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r

diff --git a/Demo/CORTEX_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/inc/stm32l1xx_exti.h b/Demo/CORTEX_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/inc/stm32l1xx_exti.h
new file mode 100644 (file)
index 0000000..769e4fc
--- /dev/null
+++ b/Demo/CORTEX_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/inc/stm32l1xx_exti.h
@@ -0,0 +1,201 @@
+/**\r
+  ******************************************************************************\r
+  * @file    stm32l1xx_exti.h\r
+  * @author  MCD Application Team\r
+  * @version V1.0.0RC1\r
+  * @date    07/02/2010\r
+  * @brief   This file contains all the functions prototypes for the EXTI firmware\r
+  *          library.\r
+  ******************************************************************************\r
+  * @copy\r
+  *\r
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+  *\r
+  * <h2><center>&copy; COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+  */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32L1xx_EXTI_H\r
+#define __STM32L1xx_EXTI_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+  * @{\r
+  */\r
+\r
+/** @addtogroup EXTI\r
+  * @{\r
+  */\r
+\r
+/** @defgroup EXTI_Exported_Types\r
+  * @{\r
+  */\r
+\r
+/** \r
+  * @brief  EXTI mode enumeration  \r
+  */\r
+\r
+typedef enum\r
+{\r
+  EXTI_Mode_Interrupt = 0x00,\r
+  EXTI_Mode_Event = 0x04\r
+}EXTIMode_TypeDef;\r
+\r
+#define IS_EXTI_MODE(MODE) (((MODE) == EXTI_Mode_Interrupt) || ((MODE) == EXTI_Mode_Event))\r
+\r
+/** \r
+  * @brief  EXTI Trigger enumeration  \r
+  */\r
+\r
+typedef enum\r
+{\r
+  EXTI_Trigger_Rising = 0x08,\r
+  EXTI_Trigger_Falling = 0x0C,  \r
+  EXTI_Trigger_Rising_Falling = 0x10\r
+}EXTITrigger_TypeDef;\r
+\r
+#define IS_EXTI_TRIGGER(TRIGGER) (((TRIGGER) == EXTI_Trigger_Rising) || \\r
+                                  ((TRIGGER) == EXTI_Trigger_Falling) || \\r
+                                  ((TRIGGER) == EXTI_Trigger_Rising_Falling))\r
+/** \r
+  * @brief  EXTI Init Structure definition  \r
+  */\r
+\r
+typedef struct\r
+{\r
+  uint32_t EXTI_Line;               /*!< Specifies the EXTI lines to be enabled or disabled.\r
+                                         This parameter can be any combination of @ref EXTI_Lines */\r
+   \r
+  EXTIMode_TypeDef EXTI_Mode;       /*!< Specifies the mode for the EXTI lines.\r
+                                         This parameter can be a value of @ref EXTIMode_TypeDef */\r
+\r
+  EXTITrigger_TypeDef EXTI_Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines.\r
+                                         This parameter can be a value of @ref EXTIMode_TypeDef */\r
+\r
+  FunctionalState EXTI_LineCmd;     /*!< Specifies the new state of the selected EXTI lines.\r
+                                         This parameter can be set either to ENABLE or DISABLE */ \r
+}EXTI_InitTypeDef;\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup EXTI_Exported_Constants\r
+  * @{\r
+  */\r
+\r
+/** @defgroup EXTI_Lines \r
+  * @{\r
+  */\r
+\r
+#define EXTI_Line0       ((uint32_t)0x00000001)  /*!< External interrupt line 0 */\r
+#define EXTI_Line1       ((uint32_t)0x00000002)  /*!< External interrupt line 1 */\r
+#define EXTI_Line2       ((uint32_t)0x00000004)  /*!< External interrupt line 2 */\r
+#define EXTI_Line3       ((uint32_t)0x00000008)  /*!< External interrupt line 3 */\r
+#define EXTI_Line4       ((uint32_t)0x00000010)  /*!< External interrupt line 4 */\r
+#define EXTI_Line5       ((uint32_t)0x00000020)  /*!< External interrupt line 5 */\r
+#define EXTI_Line6       ((uint32_t)0x00000040)  /*!< External interrupt line 6 */\r
+#define EXTI_Line7       ((uint32_t)0x00000080)  /*!< External interrupt line 7 */\r
+#define EXTI_Line8       ((uint32_t)0x00000100)  /*!< External interrupt line 8 */\r
+#define EXTI_Line9       ((uint32_t)0x00000200)  /*!< External interrupt line 9 */\r
+#define EXTI_Line10      ((uint32_t)0x00000400)  /*!< External interrupt line 10 */\r
+#define EXTI_Line11      ((uint32_t)0x00000800)  /*!< External interrupt line 11 */\r
+#define EXTI_Line12      ((uint32_t)0x00001000)  /*!< External interrupt line 12 */\r
+#define EXTI_Line13      ((uint32_t)0x00002000)  /*!< External interrupt line 13 */\r
+#define EXTI_Line14      ((uint32_t)0x00004000)  /*!< External interrupt line 14 */\r
+#define EXTI_Line15      ((uint32_t)0x00008000)  /*!< External interrupt line 15 */\r
+#define EXTI_Line16      ((uint32_t)0x00010000)  /*!< External interrupt line 16 \r
+                                                      Connected to the PVD Output */\r
+#define EXTI_Line17      ((uint32_t)0x00020000)  /*!< External interrupt line 17 \r
+                                                      Connected to the RTC Alarm \r
+                                                      event */\r
+#define EXTI_Line18      ((uint32_t)0x00040000)  /*!< External interrupt line 18 \r
+                                                      Connected to the USB Device \r
+                                                      FS Wakeup from suspend event */\r
+#define EXTI_Line19      ((uint32_t)0x00080000)  /*!< External interrupt line 19 \r
+                                                      Connected to the RTC Tamper \r
+                                                      and Time Stamp events */ \r
+#define EXTI_Line20      ((uint32_t)0x00100000)  /*!< External interrupt line 20 \r
+                                                      Connected to the RTC Wakeup \r
+                                                      event */\r
+#define EXTI_Line21      ((uint32_t)0x00200000)  /*!< External interrupt line 21 \r
+                                                      Connected to the Comparator 1 \r
+                                                      event */\r
+\r
+#define EXTI_Line22      ((uint32_t)0x00400000)  /*!< External interrupt line 22 \r
+                                                      Connected to the Comparator 2\r
+                                                      event */\r
+                                                                                                  \r
+#define IS_EXTI_LINE(LINE) ((((LINE) & (uint32_t)0xFF800000) == 0x00) && ((LINE) != (uint16_t)0x00))\r
+\r
+#define IS_GET_EXTI_LINE(LINE) (((LINE) == EXTI_Line0) || ((LINE) == EXTI_Line1) || \\r
+                                ((LINE) == EXTI_Line2) || ((LINE) == EXTI_Line3) || \\r
+                                ((LINE) == EXTI_Line4) || ((LINE) == EXTI_Line5) || \\r
+                                ((LINE) == EXTI_Line6) || ((LINE) == EXTI_Line7) || \\r
+                                ((LINE) == EXTI_Line8) || ((LINE) == EXTI_Line9) || \\r
+                                ((LINE) == EXTI_Line10) || ((LINE) == EXTI_Line11) || \\r
+                                ((LINE) == EXTI_Line12) || ((LINE) == EXTI_Line13) || \\r
+                                ((LINE) == EXTI_Line14) || ((LINE) == EXTI_Line15) || \\r
+                                ((LINE) == EXTI_Line16) || ((LINE) == EXTI_Line17) || \\r
+                                ((LINE) == EXTI_Line18) || ((LINE) == EXTI_Line19) || \\r
+                                ((LINE) == EXTI_Line20) || ((LINE) == EXTI_Line21) || \\r
+                                ((LINE) == EXTI_Line22))\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup EXTI_Exported_Macros\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup EXTI_Exported_Functions\r
+  * @{\r
+  */\r
+\r
+void EXTI_DeInit(void);\r
+void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct);\r
+void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct);\r
+void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line);\r
+FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line);\r
+void EXTI_ClearFlag(uint32_t EXTI_Line);\r
+ITStatus EXTI_GetITStatus(uint32_t EXTI_Line);\r
+void EXTI_ClearITPendingBit(uint32_t EXTI_Line);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32L1xx_EXTI_H */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r

diff --git a/Demo/CORTEX_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/inc/stm32l1xx_gpio.h b/Demo/CORTEX_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/inc/stm32l1xx_gpio.h
new file mode 100644 (file)
index 0000000..189be5a
--- /dev/null
+++ b/Demo/CORTEX_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/inc/stm32l1xx_gpio.h
@@ -0,0 +1,369 @@
+/**\r
+  ******************************************************************************\r
+  * @file    stm32l1xx_gpio.h\r
+  * @author  MCD Application Team\r
+  * @version V1.0.0RC1\r
+  * @date    07/02/2010\r
+  * @brief   This file contains all the functions prototypes for the GPIO \r
+  *          firmware library.\r
+  ******************************************************************************\r
+  * @copy\r
+  *\r
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+  *\r
+  * <h2><center>&copy; COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+  */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32L1xx_GPIO_H\r
+#define __STM32L1xx_GPIO_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+  * @{\r
+  */\r
+\r
+/** @addtogroup GPIO\r
+  * @{\r
+  */\r
+\r
+/** @defgroup GPIO_Exported_Types\r
+  * @{\r
+  */ \r
+#define IS_GPIO_ALL_PERIPH(PERIPH) (((PERIPH) == GPIOA) || \\r
+                                    ((PERIPH) == GPIOB) || \\r
+                                    ((PERIPH) == GPIOC) || \\r
+                                    ((PERIPH) == GPIOD) || \\r
+                                    ((PERIPH) == GPIOE) || \\r
+                                    ((PERIPH) == GPIOH))\r
+\r
+/** @defgroup Configuration_Mode_enumeration \r
+  * @{\r
+  */ \r
+typedef enum\r
+{ \r
+  GPIO_Mode_IN   = 0x00, /*!< GPIO Input Mode */\r
+  GPIO_Mode_OUT  = 0x01, /*!< GPIO Output Mode */\r
+  GPIO_Mode_AF   = 0x02, /*!< GPIO Alternate function Mode */\r
+  GPIO_Mode_AN   = 0x03  /*!< GPIO Analog Mode */\r
+}GPIOMode_TypeDef;\r
+#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_Mode_IN)  || ((MODE) == GPIO_Mode_OUT) || \\r
+                            ((MODE) == GPIO_Mode_AF)|| ((MODE) == GPIO_Mode_AN))\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup Output_type_enumeration\r
+  * @{\r
+  */ \r
+typedef enum\r
+{ GPIO_OType_PP = 0x00,\r
+  GPIO_OType_OD = 0x01\r
+}GPIOOType_TypeDef;\r
+#define IS_GPIO_OTYPE(OTYPE) (((OTYPE) == GPIO_OType_PP) || ((OTYPE) == GPIO_OType_OD))\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup Output_Maximum_frequency_enumeration \r
+  * @{\r
+  */ \r
+typedef enum\r
+{ \r
+  GPIO_Speed_400KHz = 0x00, /*!< Very Low Speed */\r
+  GPIO_Speed_2MHz   = 0x01, /*!< Low Speed */\r
+  GPIO_Speed_10MHz  = 0x02, /*!< Medium Speed */\r
+  GPIO_Speed_40MHz  = 0x03  /*!< High Speed */\r
+}GPIOSpeed_TypeDef;\r
+#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_Speed_400KHz) || ((SPEED) == GPIO_Speed_2MHz) || \\r
+                              ((SPEED) == GPIO_Speed_10MHz)||  ((SPEED) == GPIO_Speed_40MHz))\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup Configuration_Pull-Up_Pull-Down_enumeration \r
+  * @{\r
+  */ \r
+typedef enum\r
+{ GPIO_PuPd_NOPULL = 0x00,\r
+  GPIO_PuPd_UP     = 0x01,\r
+  GPIO_PuPd_DOWN   = 0x02\r
+}GPIOPuPd_TypeDef;\r
+#define IS_GPIO_PUPD(PUPD) (((PUPD) == GPIO_PuPd_NOPULL) || ((PUPD) == GPIO_PuPd_UP) || \\r
+                            ((PUPD) == GPIO_PuPd_DOWN))\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup Bit_SET_and_Bit_RESET_enumeration\r
+  * @{\r
+  */\r
+typedef enum\r
+{ Bit_RESET = 0,\r
+  Bit_SET\r
+}BitAction;\r
+#define IS_GPIO_BIT_ACTION(ACTION) (((ACTION) == Bit_RESET) || ((ACTION) == Bit_SET))\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** \r
+  * @brief  GPIO Init structure definition\r
+  */ \r
+typedef struct\r
+{\r
+  uint32_t GPIO_Pin;              /*!< Specifies the GPIO pins to be configured.\r
+                                       This parameter can be any value of @ref GPIO_pins_define */\r
+\r
+  GPIOMode_TypeDef GPIO_Mode;     /*!< Specifies the operating mode for the selected pins.\r
+                                       This parameter can be a value of @ref GPIOMode_TypeDef */\r
+\r
+  GPIOSpeed_TypeDef GPIO_Speed;   /*!< Specifies the speed for the selected pins.\r
+                                       This parameter can be a value of @ref GPIOSpeed_TypeDef */\r
+\r
+  GPIOOType_TypeDef GPIO_OType;   /*!< Specifies the operating output type for the selected pins.\r
+                                       This parameter can be a value of @ref GPIOOType_TypeDef */\r
+\r
+  GPIOPuPd_TypeDef GPIO_PuPd;     /*!< Specifies the operating Pull-up/Pull down for the selected pins.\r
+                                       This parameter can be a value of @ref GPIOPuPd_TypeDef */\r
+}GPIO_InitTypeDef;\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup GPIO_Exported_Constants\r
+  * @{\r
+  */\r
+  \r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup GPIO_pins_define \r
+  * @{\r
+  */\r
+#define GPIO_Pin_0                 ((uint16_t)0x0001)  /*!< Pin 0 selected */\r
+#define GPIO_Pin_1                 ((uint16_t)0x0002)  /*!< Pin 1 selected */\r
+#define GPIO_Pin_2                 ((uint16_t)0x0004)  /*!< Pin 2 selected */\r
+#define GPIO_Pin_3                 ((uint16_t)0x0008)  /*!< Pin 3 selected */\r
+#define GPIO_Pin_4                 ((uint16_t)0x0010)  /*!< Pin 4 selected */\r
+#define GPIO_Pin_5                 ((uint16_t)0x0020)  /*!< Pin 5 selected */\r
+#define GPIO_Pin_6                 ((uint16_t)0x0040)  /*!< Pin 6 selected */\r
+#define GPIO_Pin_7                 ((uint16_t)0x0080)  /*!< Pin 7 selected */\r
+#define GPIO_Pin_8                 ((uint16_t)0x0100)  /*!< Pin 8 selected */\r
+#define GPIO_Pin_9                 ((uint16_t)0x0200)  /*!< Pin 9 selected */\r
+#define GPIO_Pin_10                ((uint16_t)0x0400)  /*!< Pin 10 selected */\r
+#define GPIO_Pin_11                ((uint16_t)0x0800)  /*!< Pin 11 selected */\r
+#define GPIO_Pin_12                ((uint16_t)0x1000)  /*!< Pin 12 selected */\r
+#define GPIO_Pin_13                ((uint16_t)0x2000)  /*!< Pin 13 selected */\r
+#define GPIO_Pin_14                ((uint16_t)0x4000)  /*!< Pin 14 selected */\r
+#define GPIO_Pin_15                ((uint16_t)0x8000)  /*!< Pin 15 selected */\r
+#define GPIO_Pin_All               ((uint16_t)0xFFFF)  /*!< All pins selected */\r
+\r
+#define IS_GPIO_PIN(PIN) ((PIN) != (uint16_t)0x00)\r
+#define IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_Pin_0) || \\r
+                              ((PIN) == GPIO_Pin_1) || \\r
+                              ((PIN) == GPIO_Pin_2) || \\r
+                              ((PIN) == GPIO_Pin_3) || \\r
+                              ((PIN) == GPIO_Pin_4) || \\r
+                              ((PIN) == GPIO_Pin_5) || \\r
+                              ((PIN) == GPIO_Pin_6) || \\r
+                              ((PIN) == GPIO_Pin_7) || \\r
+                              ((PIN) == GPIO_Pin_8) || \\r
+                              ((PIN) == GPIO_Pin_9) || \\r
+                              ((PIN) == GPIO_Pin_10) || \\r
+                              ((PIN) == GPIO_Pin_11) || \\r
+                              ((PIN) == GPIO_Pin_12) || \\r
+                              ((PIN) == GPIO_Pin_13) || \\r
+                              ((PIN) == GPIO_Pin_14) || \\r
+                              ((PIN) == GPIO_Pin_15))\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup GPIO_Pin_sources \r
+  * @{\r
+  */ \r
+#define GPIO_PinSource0            ((uint8_t)0x00)\r
+#define GPIO_PinSource1            ((uint8_t)0x01)\r
+#define GPIO_PinSource2            ((uint8_t)0x02)\r
+#define GPIO_PinSource3            ((uint8_t)0x03)\r
+#define GPIO_PinSource4            ((uint8_t)0x04)\r
+#define GPIO_PinSource5            ((uint8_t)0x05)\r
+#define GPIO_PinSource6            ((uint8_t)0x06)\r
+#define GPIO_PinSource7            ((uint8_t)0x07)\r
+#define GPIO_PinSource8            ((uint8_t)0x08)\r
+#define GPIO_PinSource9            ((uint8_t)0x09)\r
+#define GPIO_PinSource10           ((uint8_t)0x0A)\r
+#define GPIO_PinSource11           ((uint8_t)0x0B)\r
+#define GPIO_PinSource12           ((uint8_t)0x0C)\r
+#define GPIO_PinSource13           ((uint8_t)0x0D)\r
+#define GPIO_PinSource14           ((uint8_t)0x0E)\r
+#define GPIO_PinSource15           ((uint8_t)0x0F)\r
+\r
+#define IS_GPIO_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == GPIO_PinSource0) || \\r
+                                       ((PINSOURCE) == GPIO_PinSource1) || \\r
+                                       ((PINSOURCE) == GPIO_PinSource2) || \\r
+                                       ((PINSOURCE) == GPIO_PinSource3) || \\r
+                                       ((PINSOURCE) == GPIO_PinSource4) || \\r
+                                       ((PINSOURCE) == GPIO_PinSource5) || \\r
+                                       ((PINSOURCE) == GPIO_PinSource6) || \\r
+                                       ((PINSOURCE) == GPIO_PinSource7) || \\r
+                                       ((PINSOURCE) == GPIO_PinSource8) || \\r
+                                       ((PINSOURCE) == GPIO_PinSource9) || \\r
+                                       ((PINSOURCE) == GPIO_PinSource10) || \\r
+                                       ((PINSOURCE) == GPIO_PinSource11) || \\r
+                                       ((PINSOURCE) == GPIO_PinSource12) || \\r
+                                       ((PINSOURCE) == GPIO_PinSource13) || \\r
+                                       ((PINSOURCE) == GPIO_PinSource14) || \\r
+                                       ((PINSOURCE) == GPIO_PinSource15))\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup GPIO_Alternat_function_selection_define \r
+  * @{\r
+  */\r
+\r
+/** \r
+  * @brief  AF 0 selection  \r
+  */ \r
+#define GPIO_AF_RTC_50Hz      ((uint8_t)0x00)  /*!< RTC 50/60 Hz Alternate Function mapping */\r
+#define GPIO_AF_MCO           ((uint8_t)0x00)  /*!< MCO Alternate Function mapping */\r
+#define GPIO_AF_RTC_AF1       ((uint8_t)0x00)  /*!< RTC_AF1 Alternate Function mapping */\r
+#define GPIO_AF_WKUP          ((uint8_t)0x00)  /*!< Wakeup (WKUP1, WKUP2 and WKUP3) Alternate Function mapping */\r
+#define GPIO_AF_SWJ           ((uint8_t)0x00)  /*!< SWJ (SW and JTAG) Alternate Function mapping */\r
+#define GPIO_AF_TRACE         ((uint8_t)0x00)  /*!< TRACE Alternate Function mapping */\r
+\r
+/** \r
+  * @brief  AF 1 selection  \r
+  */ \r
+#define GPIO_AF_TIM2          ((uint8_t)0x01)  /*!< TIM2 Alternate Function mapping */\r
+/** \r
+  * @brief  AF 2 selection  \r
+  */ \r
+#define GPIO_AF_TIM3          ((uint8_t)0x02)  /*!< TIM3 Alternate Function mapping */\r
+#define GPIO_AF_TIM4          ((uint8_t)0x02)  /*!< TIM4 Alternate Function mapping */\r
+/** \r
+  * @brief  AF 3 selection  \r
+  */ \r
+#define GPIO_AF_TIM9           ((uint8_t)0x03)  /*!< TIM9 Alternate Function mapping */\r
+#define GPIO_AF_TIM10          ((uint8_t)0x03)  /*!< TIM10 Alternate Function mapping */\r
+#define GPIO_AF_TIM11          ((uint8_t)0x03)  /*!< TIM11 Alternate Function mapping */\r
+/** \r
+  * @brief  AF 4 selection  \r
+  */ \r
+#define GPIO_AF_I2C1          ((uint8_t)0x04)  /*!< I2C1 Alternate Function mapping */\r
+#define GPIO_AF_I2C2          ((uint8_t)0x04)  /*!< I2C2 Alternate Function mapping */\r
+/** \r
+  * @brief  AF 5 selection  \r
+  */ \r
+#define GPIO_AF_SPI1          ((uint8_t)0x05)  /*!< SPI1 Alternate Function mapping */\r
+#define GPIO_AF_SPI2          ((uint8_t)0x05)  /*!< SPI2 Alternate Function mapping */\r
+/** \r
+  * @brief  AF 7 selection  \r
+  */ \r
+#define GPIO_AF_USART1        ((uint8_t)0x07)  /*!< USART1 Alternate Function mapping */\r
+#define GPIO_AF_USART2        ((uint8_t)0x07)  /*!< USART2 Alternate Function mapping */\r
+#define GPIO_AF_USART3        ((uint8_t)0x07)  /*!< USART3 Alternate Function mapping */\r
+/** \r
+  * @brief  AF 10 selection  \r
+  */ \r
+#define GPIO_AF_USB           ((uint8_t)0xA)  /*!< USB Full speed device  Alternate Function mapping */\r
+/** \r
+  * @brief  AF 11 selection  \r
+  */ \r
+#define GPIO_AF_LCD           ((uint8_t)0x0B)  /*!< LCD Alternate Function mapping */\r
+/** \r
+  * @brief  AF 14 selection  \r
+  */ \r
+#define GPIO_AF_RI            ((uint8_t)0x0E)  /*!< RI Alternate Function mapping */\r
+\r
+/** \r
+  * @brief  AF 15 selection  \r
+  */ \r
+#define GPIO_AF_EVENTOUT      ((uint8_t)0x0F)  /*!< EVENTOUT Alternate Function mapping */\r
+\r
+#define IS_GPIO_AF(AF)   (((AF) == GPIO_AF_RTC_50Hz) || ((AF) == GPIO_AF_MCO) || \\r
+                          ((AF) == GPIO_AF_RTC_AF1) || ((AF) == GPIO_AF_WKUP) || \\r
+                          ((AF) == GPIO_AF_SWJ)    || ((AF) == GPIO_AF_TRACE) || \\r
+                          ((AF) == GPIO_AF_TIM2)   || ((AF)== GPIO_AF_TIM3) || \\r
+                          ((AF) == GPIO_AF_TIM4)   || ((AF)== GPIO_AF_TIM9) || \\r
+                          ((AF) == GPIO_AF_TIM10)  || ((AF)== GPIO_AF_TIM11) || \\r
+                          ((AF) == GPIO_AF_I2C1)   || ((AF) == GPIO_AF_I2C2) || \\r
+                          ((AF) == GPIO_AF_SPI1)   || ((AF) == GPIO_AF_SPI2) || \\r
+                          ((AF) == GPIO_AF_USART1) || ((AF) == GPIO_AF_USART2) || \\r
+                          ((AF) == GPIO_AF_USART3) || ((AF) == GPIO_AF_USB) || \\r
+                          ((AF) == GPIO_AF_LCD)    || ((AF) == GPIO_AF_RI) || \\r
+                          ((AF) == GPIO_AF_EVENTOUT))\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup GPIO_Legacy \r
+  * @{\r
+  */\r
+    \r
+#define GPIO_Mode_AIN GPIO_Mode_AN\r
+\r
+/**\r
+  * @}\r
+  */\r
+  \r
+/** @defgroup GPIO_Exported_Macros\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup GPIO_Exported_Functions\r
+  * @{\r
+  */\r
+void GPIO_DeInit(GPIO_TypeDef* GPIOx);\r
+void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct);\r
+void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct);\r
+uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);\r
+uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx);\r
+uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);\r
+uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx);\r
+void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);\r
+void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);\r
+void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal);\r
+void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal);\r
+void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);\r
+void GPIO_PinAFConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO_AF);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /*__STM32L1xx_GPIO_H */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r

diff --git a/Demo/CORTEX_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/inc/stm32l1xx_i2c.h b/Demo/CORTEX_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/inc/stm32l1xx_i2c.h
new file mode 100644 (file)
index 0000000..d4d2997
--- /dev/null
+++ b/Demo/CORTEX_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/inc/stm32l1xx_i2c.h
@@ -0,0 +1,670 @@
+/**\r
+  ******************************************************************************\r
+  * @file    stm32l1xx_i2c.h\r
+  * @author  MCD Application Team\r
+  * @version V1.0.0RC1\r
+  * @date    07/02/2010\r
+  * @brief   This file contains all the functions prototypes for the I2C firmware \r
+  *          library.\r
+  ******************************************************************************\r
+  * @copy\r
+  *\r
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+  *\r
+  * <h2><center>&copy; COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+  */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32L1xx_I2C_H\r
+#define __STM32L1xx_I2C_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+  * @{\r
+  */\r
+\r
+/** @addtogroup I2C\r
+  * @{\r
+  */\r
+\r
+/** @defgroup I2C_Exported_Types\r
+  * @{\r
+  */\r
+\r
+/** \r
+  * @brief  I2C Init structure definition  \r
+  */\r
+\r
+typedef struct\r
+{\r
+  uint32_t I2C_ClockSpeed;          /*!< Specifies the clock frequency.\r
+                                         This parameter must be set to a value lower than 400kHz */\r
+\r
+  uint16_t I2C_Mode;                /*!< Specifies the I2C mode.\r
+                                         This parameter can be a value of @ref I2C_mode */\r
+\r
+  uint16_t I2C_DutyCycle;           /*!< Specifies the I2C fast mode duty cycle.\r
+                                         This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */\r
+\r
+  uint16_t I2C_OwnAddress1;         /*!< Specifies the first device own address.\r
+                                         This parameter can be a 7-bit or 10-bit address. */\r
+\r
+  uint16_t I2C_Ack;                 /*!< Enables or disables the acknowledgement.\r
+                                         This parameter can be a value of @ref I2C_acknowledgement */\r
+\r
+  uint16_t I2C_AcknowledgedAddress; /*!< Specifies if 7-bit or 10-bit address is acknowledged.\r
+                                         This parameter can be a value of @ref I2C_acknowledged_address */\r
+}I2C_InitTypeDef;\r
+\r
+/**\r
+  * @}\r
+  */ \r
+\r
+\r
+/** @defgroup I2C_Exported_Constants\r
+  * @{\r
+  */\r
+\r
+#define IS_I2C_ALL_PERIPH(PERIPH) (((PERIPH) == I2C1) || \\r
+                                   ((PERIPH) == I2C2))\r
+/** @defgroup I2C_mode \r
+  * @{\r
+  */\r
+\r
+#define I2C_Mode_I2C                    ((uint16_t)0x0000)\r
+#define I2C_Mode_SMBusDevice            ((uint16_t)0x0002)  \r
+#define I2C_Mode_SMBusHost              ((uint16_t)0x000A)\r
+#define IS_I2C_MODE(MODE) (((MODE) == I2C_Mode_I2C) || \\r
+                           ((MODE) == I2C_Mode_SMBusDevice) || \\r
+                           ((MODE) == I2C_Mode_SMBusHost))\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup I2C_duty_cycle_in_fast_mode \r
+  * @{\r
+  */\r
+\r
+#define I2C_DutyCycle_16_9              ((uint16_t)0x4000) /*!< I2C fast mode Tlow/Thigh = 16/9 */\r
+#define I2C_DutyCycle_2                 ((uint16_t)0xBFFF) /*!< I2C fast mode Tlow/Thigh = 2 */\r
+#define IS_I2C_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_DutyCycle_16_9) || \\r
+                                  ((CYCLE) == I2C_DutyCycle_2))\r
+/**\r
+  * @}\r
+  */ \r
+\r
+/** @defgroup I2C_acknowledgement\r
+  * @{\r
+  */\r
+\r
+#define I2C_Ack_Enable                  ((uint16_t)0x0400)\r
+#define I2C_Ack_Disable                 ((uint16_t)0x0000)\r
+#define IS_I2C_ACK_STATE(STATE) (((STATE) == I2C_Ack_Enable) || \\r
+                                 ((STATE) == I2C_Ack_Disable))\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup I2C_transfer_direction \r
+  * @{\r
+  */\r
+\r
+#define  I2C_Direction_Transmitter      ((uint8_t)0x00)\r
+#define  I2C_Direction_Receiver         ((uint8_t)0x01)\r
+#define IS_I2C_DIRECTION(DIRECTION) (((DIRECTION) == I2C_Direction_Transmitter) || \\r
+                                     ((DIRECTION) == I2C_Direction_Receiver))\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup I2C_acknowledged_address \r
+  * @{\r
+  */\r
+\r
+#define I2C_AcknowledgedAddress_7bit    ((uint16_t)0x4000)\r
+#define I2C_AcknowledgedAddress_10bit   ((uint16_t)0xC000)\r
+#define IS_I2C_ACKNOWLEDGE_ADDRESS(ADDRESS) (((ADDRESS) == I2C_AcknowledgedAddress_7bit) || \\r
+                                             ((ADDRESS) == I2C_AcknowledgedAddress_10bit))\r
+/**\r
+  * @}\r
+  */ \r
+\r
+/** @defgroup I2C_registers \r
+  * @{\r
+  */\r
+\r
+#define I2C_Register_CR1                ((uint8_t)0x00)\r
+#define I2C_Register_CR2                ((uint8_t)0x04)\r
+#define I2C_Register_OAR1               ((uint8_t)0x08)\r
+#define I2C_Register_OAR2               ((uint8_t)0x0C)\r
+#define I2C_Register_DR                 ((uint8_t)0x10)\r
+#define I2C_Register_SR1                ((uint8_t)0x14)\r
+#define I2C_Register_SR2                ((uint8_t)0x18)\r
+#define I2C_Register_CCR                ((uint8_t)0x1C)\r
+#define I2C_Register_TRISE              ((uint8_t)0x20)\r
+#define IS_I2C_REGISTER(REGISTER) (((REGISTER) == I2C_Register_CR1) || \\r
+                                   ((REGISTER) == I2C_Register_CR2) || \\r
+                                   ((REGISTER) == I2C_Register_OAR1) || \\r
+                                   ((REGISTER) == I2C_Register_OAR2) || \\r
+                                   ((REGISTER) == I2C_Register_DR) || \\r
+                                   ((REGISTER) == I2C_Register_SR1) || \\r
+                                   ((REGISTER) == I2C_Register_SR2) || \\r
+                                   ((REGISTER) == I2C_Register_CCR) || \\r
+                                   ((REGISTER) == I2C_Register_TRISE))\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup I2C_SMBus_alert_pin_level \r
+  * @{\r
+  */\r
+\r
+#define I2C_SMBusAlert_Low              ((uint16_t)0x2000)\r
+#define I2C_SMBusAlert_High             ((uint16_t)0xDFFF)\r
+#define IS_I2C_SMBUS_ALERT(ALERT) (((ALERT) == I2C_SMBusAlert_Low) || \\r
+                                   ((ALERT) == I2C_SMBusAlert_High))\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup I2C_PEC_position \r
+  * @{\r
+  */\r
+\r
+#define I2C_PECPosition_Next            ((uint16_t)0x0800)\r
+#define I2C_PECPosition_Current         ((uint16_t)0xF7FF)\r
+#define IS_I2C_PEC_POSITION(POSITION) (((POSITION) == I2C_PECPosition_Next) || \\r
+                                       ((POSITION) == I2C_PECPosition_Current))\r
+/**\r
+  * @}\r
+  */ \r
+\r
+/** @defgroup I2C_interrupts_definition \r
+  * @{\r
+  */\r
+\r
+#define I2C_IT_BUF                      ((uint16_t)0x0400)\r
+#define I2C_IT_EVT                      ((uint16_t)0x0200)\r
+#define I2C_IT_ERR                      ((uint16_t)0x0100)\r
+#define IS_I2C_CONFIG_IT(IT) ((((IT) & (uint16_t)0xF8FF) == 0x00) && ((IT) != 0x00))\r
+/**\r
+  * @}\r
+  */ \r
+\r
+/** @defgroup I2C_interrupts_definition \r
+  * @{\r
+  */\r
+\r
+#define I2C_IT_SMBALERT                 ((uint32_t)0x01008000)\r
+#define I2C_IT_TIMEOUT                  ((uint32_t)0x01004000)\r
+#define I2C_IT_PECERR                   ((uint32_t)0x01001000)\r
+#define I2C_IT_OVR                      ((uint32_t)0x01000800)\r
+#define I2C_IT_AF                       ((uint32_t)0x01000400)\r
+#define I2C_IT_ARLO                     ((uint32_t)0x01000200)\r
+#define I2C_IT_BERR                     ((uint32_t)0x01000100)\r
+#define I2C_IT_TXE                      ((uint32_t)0x06000080)\r
+#define I2C_IT_RXNE                     ((uint32_t)0x06000040)\r
+#define I2C_IT_STOPF                    ((uint32_t)0x02000010)\r
+#define I2C_IT_ADD10                    ((uint32_t)0x02000008)\r
+#define I2C_IT_BTF                      ((uint32_t)0x02000004)\r
+#define I2C_IT_ADDR                     ((uint32_t)0x02000002)\r
+#define I2C_IT_SB                       ((uint32_t)0x02000001)\r
+\r
+#define IS_I2C_CLEAR_IT(IT) ((((IT) & (uint16_t)0x20FF) == 0x00) && ((IT) != (uint16_t)0x00))\r
+\r
+#define IS_I2C_GET_IT(IT) (((IT) == I2C_IT_SMBALERT) || ((IT) == I2C_IT_TIMEOUT) || \\r
+                           ((IT) == I2C_IT_PECERR) || ((IT) == I2C_IT_OVR) || \\r
+                           ((IT) == I2C_IT_AF) || ((IT) == I2C_IT_ARLO) || \\r
+                           ((IT) == I2C_IT_BERR) || ((IT) == I2C_IT_TXE) || \\r
+                           ((IT) == I2C_IT_RXNE) || ((IT) == I2C_IT_STOPF) || \\r
+                           ((IT) == I2C_IT_ADD10) || ((IT) == I2C_IT_BTF) || \\r
+                           ((IT) == I2C_IT_ADDR) || ((IT) == I2C_IT_SB))\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup I2C_flags_definition \r
+  * @{\r
+  */\r
+\r
+/** \r
+  * @brief  SR2 register flags  \r
+  */\r
+\r
+#define I2C_FLAG_DUALF                  ((uint32_t)0x00800000)\r
+#define I2C_FLAG_SMBHOST                ((uint32_t)0x00400000)\r
+#define I2C_FLAG_SMBDEFAULT             ((uint32_t)0x00200000)\r
+#define I2C_FLAG_GENCALL                ((uint32_t)0x00100000)\r
+#define I2C_FLAG_TRA                    ((uint32_t)0x00040000)\r
+#define I2C_FLAG_BUSY                   ((uint32_t)0x00020000)\r
+#define I2C_FLAG_MSL                    ((uint32_t)0x00010000)\r
+\r
+/** \r
+  * @brief  SR1 register flags  \r
+  */\r
+\r
+#define I2C_FLAG_SMBALERT               ((uint32_t)0x10008000)\r
+#define I2C_FLAG_TIMEOUT                ((uint32_t)0x10004000)\r
+#define I2C_FLAG_PECERR                 ((uint32_t)0x10001000)\r
+#define I2C_FLAG_OVR                    ((uint32_t)0x10000800)\r
+#define I2C_FLAG_AF                     ((uint32_t)0x10000400)\r
+#define I2C_FLAG_ARLO                   ((uint32_t)0x10000200)\r
+#define I2C_FLAG_BERR                   ((uint32_t)0x10000100)\r
+#define I2C_FLAG_TXE                    ((uint32_t)0x10000080)\r
+#define I2C_FLAG_RXNE                   ((uint32_t)0x10000040)\r
+#define I2C_FLAG_STOPF                  ((uint32_t)0x10000010)\r
+#define I2C_FLAG_ADD10                  ((uint32_t)0x10000008)\r
+#define I2C_FLAG_BTF                    ((uint32_t)0x10000004)\r
+#define I2C_FLAG_ADDR                   ((uint32_t)0x10000002)\r
+#define I2C_FLAG_SB                     ((uint32_t)0x10000001)\r
+\r
+#define IS_I2C_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0x20FF) == 0x00) && ((FLAG) != (uint16_t)0x00))\r
+\r
+#define IS_I2C_GET_FLAG(FLAG) (((FLAG) == I2C_FLAG_DUALF) || ((FLAG) == I2C_FLAG_SMBHOST) || \\r
+                               ((FLAG) == I2C_FLAG_SMBDEFAULT) || ((FLAG) == I2C_FLAG_GENCALL) || \\r
+                               ((FLAG) == I2C_FLAG_TRA) || ((FLAG) == I2C_FLAG_BUSY) || \\r
+                               ((FLAG) == I2C_FLAG_MSL) || ((FLAG) == I2C_FLAG_SMBALERT) || \\r
+                               ((FLAG) == I2C_FLAG_TIMEOUT) || ((FLAG) == I2C_FLAG_PECERR) || \\r
+                               ((FLAG) == I2C_FLAG_OVR) || ((FLAG) == I2C_FLAG_AF) || \\r
+                               ((FLAG) == I2C_FLAG_ARLO) || ((FLAG) == I2C_FLAG_BERR) || \\r
+                               ((FLAG) == I2C_FLAG_TXE) || ((FLAG) == I2C_FLAG_RXNE) || \\r
+                               ((FLAG) == I2C_FLAG_STOPF) || ((FLAG) == I2C_FLAG_ADD10) || \\r
+                               ((FLAG) == I2C_FLAG_BTF) || ((FLAG) == I2C_FLAG_ADDR) || \\r
+                               ((FLAG) == I2C_FLAG_SB))\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup I2C_Events \r
+  * @{\r
+  */\r
+\r
+/*========================================\r
+     \r
+                     I2C Master Events (Events grouped in order of communication)\r
+                                                        ==========================================*/\r
+/** \r
+  * @brief  Communication start\r
+  * \r
+  * After sending the START condition (I2C_GenerateSTART() function) the master \r
+  * has to wait for this event. It means that the Start condition has been correctly \r
+  * released on the I2C bus (the bus is free, no other devices is communicating).\r
+  * \r
+  */\r
+/* --EV5 */\r
+#define  I2C_EVENT_MASTER_MODE_SELECT                      ((uint32_t)0x00030001)  /* BUSY, MSL and SB flag */\r
+\r
+/** \r
+  * @brief  Address Acknowledge\r
+  * \r
+  * After checking on EV5 (start condition correctly released on the bus), the \r
+  * master sends the address of the slave(s) with which it will communicate \r
+  * (I2C_Send7bitAddress() function, it also determines the direction of the communication: \r
+  * Master transmitter or Receiver). Then the master has to wait that a slave acknowledges \r
+  * his address. If an acknowledge is sent on the bus, one of the following events will \r
+  * be set:\r
+  * \r
+  *  1) In case of Master Receiver (7-bit addressing): the I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED \r
+  *     event is set.\r
+  *  \r
+  *  2) In case of Master Transmitter (7-bit addressing): the I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED \r
+  *     is set\r
+  *  \r
+  *  3) In case of 10-Bit addressing mode, the master (just after generating the START \r
+  *  and checking on EV5) has to send the header of 10-bit addressing mode (I2C_SendData() \r
+  *  function). Then master should wait on EV9. It means that the 10-bit addressing \r
+  *  header has been correctly sent on the bus. Then master should send the second part of \r
+  *  the 10-bit address (LSB) using the function I2C_Send7bitAddress(). Then master \r
+  *  should wait for event EV6. \r
+  *     \r
+  */\r
+\r
+/* --EV6 */\r
+#define  I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED        ((uint32_t)0x00070082)  /* BUSY, MSL, ADDR, TXE and TRA flags */\r
+#define  I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED           ((uint32_t)0x00030002)  /* BUSY, MSL and ADDR flags */\r
+/* --EV9 */\r
+#define  I2C_EVENT_MASTER_MODE_ADDRESS10                   ((uint32_t)0x00030008)  /* BUSY, MSL and ADD10 flags */\r
+\r
+/** \r
+  * @brief Communication events\r
+  * \r
+  * If a communication is established (START condition generated and slave address \r
+  * acknowledged) then the master has to check on one of the following events for \r
+  * communication procedures:\r
+  *  \r
+  * 1) Master Receiver mode: The master has to wait on the event EV7 then to read \r
+  *    the data received from the slave (I2C_ReceiveData() function).\r
+  * \r
+  * 2) Master Transmitter mode: The master has to send data (I2C_SendData() \r
+  *    function) then to wait on event EV8 or EV8_2.\r
+  *    These two events are similar: \r
+  *     - EV8 means that the data has been written in the data register and is \r
+  *       being shifted out.\r
+  *     - EV8_2 means that the data has been physically shifted out and output \r
+  *       on the bus.\r
+  *     In most cases, using EV8 is sufficient for the application.\r
+  *     Using EV8_2 leads to a slower communication but ensure more reliable test.\r
+  *     EV8_2 is also more suitable than EV8 for testing on the last data transmission \r
+  *     (before Stop condition generation).\r
+  *     \r
+  *  @note In case the  user software does not guarantee that this event EV7 is \r
+  *  managed before the current byte end of transfer, then user may check on EV7 \r
+  *  and BTF flag at the same time (ie. (I2C_EVENT_MASTER_BYTE_RECEIVED | I2C_FLAG_BTF)).\r
+  *  In this case the communication may be slower.\r
+  * \r
+  */\r
+\r
+/* Master RECEIVER mode -----------------------------*/ \r
+/* --EV7 */\r
+#define  I2C_EVENT_MASTER_BYTE_RECEIVED                    ((uint32_t)0x00030040)  /* BUSY, MSL and RXNE flags */\r
+\r
+/* Master TRANSMITTER mode --------------------------*/\r
+/* --EV8 */\r
+#define I2C_EVENT_MASTER_BYTE_TRANSMITTING                 ((uint32_t)0x00070080) /* TRA, BUSY, MSL, TXE flags */\r
+/* --EV8_2 */\r
+#define  I2C_EVENT_MASTER_BYTE_TRANSMITTED                 ((uint32_t)0x00070084)  /* TRA, BUSY, MSL, TXE and BTF flags */\r
+\r
+\r
+/*========================================\r
+     \r
+                     I2C Slave Events (Events grouped in order of communication)\r
+                                                        ==========================================*/\r
+\r
+/** \r
+  * @brief  Communication start events\r
+  * \r
+  * Wait on one of these events at the start of the communication. It means that \r
+  * the I2C peripheral detected a Start condition on the bus (generated by master \r
+  * device) followed by the peripheral address. The peripheral generates an ACK \r
+  * condition on the bus (if the acknowledge feature is enabled through function \r
+  * I2C_AcknowledgeConfig()) and the events listed above are set :\r
+  *  \r
+  * 1) In normal case (only one address managed by the slave), when the address \r
+  *   sent by the master matches the own address of the peripheral (configured by \r
+  *   I2C_OwnAddress1 field) the I2C_EVENT_SLAVE_XXX_ADDRESS_MATCHED event is set \r
+  *   (where XXX could be TRANSMITTER or RECEIVER).\r
+  *    \r
+  * 2) In case the address sent by the master matches the second address of the \r
+  *   peripheral (configured by the function I2C_OwnAddress2Config() and enabled \r
+  *   by the function I2C_DualAddressCmd()) the events I2C_EVENT_SLAVE_XXX_SECONDADDRESS_MATCHED \r
+  *   (where XXX could be TRANSMITTER or RECEIVER) are set.\r
+  *   \r
+  * 3) In case the address sent by the master is General Call (address 0x00) and \r
+  *   if the General Call is enabled for the peripheral (using function I2C_GeneralCallCmd()) \r
+  *   the following event is set I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED.   \r
+  * \r
+  */\r
+\r
+/* --EV1  (all the events below are variants of EV1) */   \r
+/* 1) Case of One Single Address managed by the slave */\r
+#define  I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED          ((uint32_t)0x00020002) /* BUSY and ADDR flags */\r
+#define  I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED       ((uint32_t)0x00060082) /* TRA, BUSY, TXE and ADDR flags */\r
+\r
+/* 2) Case of Dual address managed by the slave */\r
+#define  I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED    ((uint32_t)0x00820000)  /* DUALF and BUSY flags */\r
+#define  I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((uint32_t)0x00860080)  /* DUALF, TRA, BUSY and TXE flags */\r
+\r
+/* 3) Case of General Call enabled for the slave */\r
+#define  I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED        ((uint32_t)0x00120000)  /* GENCALL and BUSY flags */\r
+\r
+/** \r
+  * @brief  Communication events\r
+  * \r
+  * Wait on one of these events when EV1 has already been checked and: \r
+  * \r
+  * - Slave RECEIVER mode:\r
+  *     - EV2: When the application is expecting a data byte to be received. \r
+  *     - EV4: When the application is expecting the end of the communication: master \r
+  *       sends a stop condition and data transmission is stopped.\r
+  *    \r
+  * - Slave Transmitter mode:\r
+  *    - EV3: When a byte has been transmitted by the slave and the application is expecting \r
+  *      the end of the byte transmission. The two events I2C_EVENT_SLAVE_BYTE_TRANSMITTED and\r
+  *      I2C_EVENT_SLAVE_BYTE_TRANSMITTING are similar. The second one can optionally be \r
+  *      used when the user software doesn't guarantee the EV3 is managed before the\r
+  *      current byte end of tranfer.\r
+  *    - EV3_2: When the master sends a NACK in order to tell slave that data transmission \r
+  *      shall end (before sending the STOP condition). In this case slave has to stop sending \r
+  *      data bytes and expect a Stop condition on the bus.\r
+  *      \r
+  *  @note In case the  user software does not guarantee that the event EV2 is \r
+  *  managed before the current byte end of transfer, then user may check on EV2 \r
+  *  and BTF flag at the same time (ie. (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_BTF)).\r
+  *  In this case the communication may be slower.\r
+  *\r
+  */\r
+\r
+/* Slave RECEIVER mode --------------------------*/ \r
+/* --EV2 */\r
+#define  I2C_EVENT_SLAVE_BYTE_RECEIVED                     ((uint32_t)0x00020040)  /* BUSY and RXNE flags */\r
+/* --EV4  */\r
+#define  I2C_EVENT_SLAVE_STOP_DETECTED                     ((uint32_t)0x00000010)  /* STOPF flag */\r
+\r
+/* Slave TRANSMITTER mode -----------------------*/\r
+/* --EV3 */\r
+#define  I2C_EVENT_SLAVE_BYTE_TRANSMITTED                  ((uint32_t)0x00060084)  /* TRA, BUSY, TXE and BTF flags */\r
+#define  I2C_EVENT_SLAVE_BYTE_TRANSMITTING                 ((uint32_t)0x00060080)  /* TRA, BUSY and TXE flags */\r
+/* --EV3_2 */\r
+#define  I2C_EVENT_SLAVE_ACK_FAILURE                       ((uint32_t)0x00000400)  /* AF flag */\r
+\r
+/*===========================      End of Events Description           ==========================================*/\r
+\r
+#define IS_I2C_EVENT(EVENT) (((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED) || \\r
+                             ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED) || \\r
+                             ((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED) || \\r
+                             ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED) || \\r
+                             ((EVENT) == I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED) || \\r
+                             ((EVENT) == I2C_EVENT_SLAVE_BYTE_RECEIVED) || \\r
+                             ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF)) || \\r
+                             ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL)) || \\r
+                             ((EVENT) == I2C_EVENT_SLAVE_BYTE_TRANSMITTED) || \\r
+                             ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF)) || \\r
+                             ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL)) || \\r
+                             ((EVENT) == I2C_EVENT_SLAVE_STOP_DETECTED) || \\r
+                             ((EVENT) == I2C_EVENT_MASTER_MODE_SELECT) || \\r
+                             ((EVENT) == I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED) || \\r
+                             ((EVENT) == I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED) || \\r
+                             ((EVENT) == I2C_EVENT_MASTER_BYTE_RECEIVED) || \\r
+                             ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTED) || \\r
+                             ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTING) || \\r
+                             ((EVENT) == I2C_EVENT_MASTER_MODE_ADDRESS10) || \\r
+                             ((EVENT) == I2C_EVENT_SLAVE_ACK_FAILURE))\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup I2C_own_address1 \r
+  * @{\r
+  */\r
+\r
+#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x3FF)\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup I2C_clock_speed \r
+  * @{\r
+  */\r
+\r
+#define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) >= 0x1) && ((SPEED) <= 400000))\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup I2C_Exported_Macros\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup I2C_Exported_Functions\r
+  * @{\r
+  */\r
+\r
+void I2C_DeInit(I2C_TypeDef* I2Cx);\r
+void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct);\r
+void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct);\r
+void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
+void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
+void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
+void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
+void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
+void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
+void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address);\r
+void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
+void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
+void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState);\r
+void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data);\r
+uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx);\r
+void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction);\r
+uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register);\r
+void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
+void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, uint16_t I2C_SMBusAlert);\r
+void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
+void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition);\r
+void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
+uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx);\r
+void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
+void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
+void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle);\r
+\r
+/**\r
+ * @brief\r
+ ****************************************************************************************\r
+ *\r
+ *                         I2C State Monitoring Functions\r
+ *                       \r
+ ****************************************************************************************   \r
+ * This I2C driver provides three different ways for I2C state monitoring\r
+ *  depending on the application requirements and constraints:\r
+ *        \r
+ *  \r
+ * 1) Basic state monitoring:\r
+ *    Using I2C_CheckEvent() function:\r
+ *    It compares the status registers (SR1 and SR2) content to a given event\r
+ *    (can be the combination of one or more flags).\r
+ *    It returns SUCCESS if the current status includes the given flags \r
+ *    and returns ERROR if one or more flags are missing in the current status.\r
+ *    - When to use:\r
+ *      - This function is suitable for most applications as well as for startup \r
+ *      activity since the events are fully described in the product reference manual \r
+ *      (RM0008).\r
+ *      - It is also suitable for users who need to define their own events.\r
+ *    - Limitations:\r
+ *      - If an error occurs (ie. error flags are set besides to the monitored flags),\r
+ *        the I2C_CheckEvent() function may return SUCCESS despite the communication\r
+ *        hold or corrupted real state. \r
+ *        In this case, it is advised to use error interrupts to monitor the error\r
+ *        events and handle them in the interrupt IRQ handler.\r
+ *        \r
+ *        @note \r
+ *        For error management, it is advised to use the following functions:\r
+ *          - I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR).\r
+ *          - I2Cx_ER_IRQHandler() which is called when the error interurpt occurs.\r
+ *            Where x is the peripheral instance (I2C1, I2C2 ...)\r
+ *          - I2C_GetFlagStatus() or I2C_GetITStatus() to be called into the I2Cx_ER_IRQHandler() function \r
+ *            in order to determine which error occured.\r
+ *          - I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd() and/or I2C_GenerateStop() \r
+ *            in order to clear the error flag and source and return to correct \r
+ *            communication status.\r
+ *            \r
+ *\r
+ *  2) Advanced state monitoring:\r
+ *     Using the function I2C_GetLastEvent() which returns the image of both status \r
+ *     registers in a single word (uint32_t) (Status Register 2 value is shifted left \r
+ *     by 16 bits and concatenated to Status Register 1).\r
+ *     - When to use:\r
+ *       - This function is suitable for the same applications above but it allows to\r
+ *         overcome the limitations of I2C_GetFlagStatus() function (see below).\r
+ *         The returned value could be compared to events already defined in the \r
+ *         library (stm32f10x_i2c.h) or to custom values defined by user.\r
+ *       - This function is suitable when multiple flags are monitored at the same time.\r
+ *       - At the opposite of I2C_CheckEvent() function, this function allows user to\r
+ *         choose when an event is accepted (when all events flags are set and no \r
+ *         other flags are set or just when the needed flags are set like \r
+ *         I2C_CheckEvent() function).\r
+ *     - Limitations:\r
+ *       - User may need to define his own events.\r
+ *       - Same remark concerning the error management is applicable for this \r
+ *         function if user decides to check only regular communication flags (and \r
+ *         ignores error flags).\r
+ *     \r
+ *\r
+ *  3) Flag-based state monitoring:\r
+ *     Using the function I2C_GetFlagStatus() which simply returns the status of \r
+ *     one single flag (ie. I2C_FLAG_RXNE ...). \r
+ *     - When to use:\r
+ *        - This function could be used for specific applications or in debug phase.\r
+ *        - It is suitable when only one flag checking is needed (most I2C events \r
+ *          are monitored through multiple flags).\r
+ *     - Limitations: \r
+ *        - When calling this function, the Status register is accessed. Some flags are\r
+ *          cleared when the status register is accessed. So checking the status\r
+ *          of one Flag, may clear other ones.\r
+ *        - Function may need to be called twice or more in order to monitor one \r
+ *          single event.\r
+ *            \r
+ */\r
+\r
+/**\r
+ * \r
+ *  1) Basic state monitoring\r
+ *******************************************************************************\r
+ */\r
+ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT);\r
+/**\r
+ * \r
+ *  2) Advanced state monitoring\r
+ *******************************************************************************\r
+ */\r
+uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx);\r
+/**\r
+ * \r
+ *  3) Flag-based state monitoring\r
+ *******************************************************************************\r
+ */\r
+FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);\r
+/**\r
+ *\r
+ *******************************************************************************\r
+ */\r
+\r
+void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);\r
+ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT);\r
+void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /*__STM32L1xx_I2C_H */\r
+/**\r
+  * @}\r
+  */ \r
+\r
+/**\r
+  * @}\r
+  */ \r
+\r
+/**\r
+  * @}\r
+  */ \r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r

diff --git a/Demo/CORTEX_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/inc/stm32l1xx_pwr.h b/Demo/CORTEX_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/inc/stm32l1xx_pwr.h
new file mode 100644 (file)
index 0000000..d96aa9e
--- /dev/null
+++ b/Demo/CORTEX_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/inc/stm32l1xx_pwr.h
@@ -0,0 +1,208 @@
+/**\r
+  ******************************************************************************\r
+  * @file    stm32l1xx_pwr.h\r
+  * @author  MCD Application Team\r
+  * @version V1.0.0RC1\r
+  * @date    07/02/2010\r
+  * @brief   This file contains all the functions prototypes for the PWR firmware \r
+  *          library.\r
+  ******************************************************************************\r
+  * @copy\r
+  *\r
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+  *\r
+  * <h2><center>&copy; COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+  */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32L1xx_PWR_H\r
+#define __STM32L1xx_PWR_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+  * @{\r
+  */\r
+\r
+/** @addtogroup PWR\r
+  * @{\r
+  */ \r
+\r
+/** @defgroup PWR_Exported_Types\r
+  * @{\r
+  */ \r
+\r
+/**\r
+  * @}\r
+  */ \r
+\r
+/** @defgroup PWR_Exported_Constants\r
+  * @{\r
+  */ \r
+\r
+/** @defgroup PVD_detection_level \r
+  * @{\r
+  */ \r
+\r
+#define PWR_PVDLevel_0          PWR_CR_PLS_LEV0\r
+#define PWR_PVDLevel_1          PWR_CR_PLS_LEV1\r
+#define PWR_PVDLevel_2          PWR_CR_PLS_LEV2\r
+#define PWR_PVDLevel_3          PWR_CR_PLS_LEV3\r
+#define PWR_PVDLevel_4          PWR_CR_PLS_LEV4\r
+#define PWR_PVDLevel_5          PWR_CR_PLS_LEV5\r
+#define PWR_PVDLevel_6          PWR_CR_PLS_LEV6\r
+#define PWR_PVDLevel_7          PWR_CR_PLS_LEV7 /* External input analog voltage \r
+                                               (Compare internally to VREFINT) */\r
+#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLevel_0) || ((LEVEL) == PWR_PVDLevel_1)|| \\r
+                                 ((LEVEL) == PWR_PVDLevel_2) || ((LEVEL) == PWR_PVDLevel_3)|| \\r
+                                 ((LEVEL) == PWR_PVDLevel_4) || ((LEVEL) == PWR_PVDLevel_5)|| \\r
+                                 ((LEVEL) == PWR_PVDLevel_6) || ((LEVEL) == PWR_PVDLevel_7))\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup WakeUp_Pins \r
+  * @{\r
+  */\r
+\r
+#define PWR_WakeUpPin_1           ((uint32_t)0x00000000)\r
+#define PWR_WakeUpPin_2           ((uint32_t)0x00000004)\r
+#define PWR_WakeUpPin_3           ((uint32_t)0x00000008)\r
+#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WakeUpPin_1) || \\r
+                                ((PIN) == PWR_WakeUpPin_2) || \\r
+                                ((PIN) == PWR_WakeUpPin_3))\r
+/**\r
+  * @}\r
+  */\r
+\r
+  \r
+/** @defgroup Voltage_Scaling_Ranges\r
+  * @{\r
+  */\r
+\r
+#define PWR_VoltageScaling_Range1       PWR_CR_VOS_0\r
+#define PWR_VoltageScaling_Range2       PWR_CR_VOS_1\r
+#define PWR_VoltageScaling_Range3       PWR_CR_VOS\r
+\r
+#define IS_PWR_VOLTAGE_SCALING_RANGE(RANGE) (((RANGE) == PWR_VoltageScaling_Range1) || \\r
+                                             ((RANGE) == PWR_VoltageScaling_Range2) || \\r
+                                             ((RANGE) == PWR_VoltageScaling_Range3))\r
+/**\r
+  * @}\r
+  */    \r
+  \r
+/** @defgroup Regulator_state_is_Sleep_STOP_mode \r
+  * @{\r
+  */\r
+\r
+#define PWR_Regulator_ON                ((uint32_t)0x00000000)\r
+#define PWR_Regulator_LowPower          PWR_CR_LPSDSR\r
+#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_Regulator_ON) || \\r
+                                     ((REGULATOR) == PWR_Regulator_LowPower))\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup SLEEP_mode_entry \r
+  * @{\r
+  */\r
+\r
+#define PWR_SLEEPEntry_WFI         ((uint8_t)0x01)\r
+#define PWR_SLEEPEntry_WFE         ((uint8_t)0x02)\r
+#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPEntry_WFI) || ((ENTRY) == PWR_SLEEPEntry_WFE))\r
+ \r
+/**\r
+  * @}\r
+  */\r
+  \r
+/** @defgroup STOP_mode_entry \r
+  * @{\r
+  */\r
+\r
+#define PWR_STOPEntry_WFI         ((uint8_t)0x01)\r
+#define PWR_STOPEntry_WFE         ((uint8_t)0x02)\r
+#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPEntry_WFI) || ((ENTRY) == PWR_STOPEntry_WFE))\r
+ \r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup PWR_Flag \r
+  * @{\r
+  */\r
+\r
+#define PWR_FLAG_WU               PWR_CSR_WUF\r
+#define PWR_FLAG_SB               PWR_CSR_SBF\r
+#define PWR_FLAG_PVDO             PWR_CSR_PVDO\r
+#define PWR_FLAG_VREFINTRDY       PWR_CSR_VREFINTRDYF\r
+#define PWR_FLAG_VOS              PWR_CSR_VOSF\r
+#define PWR_FLAG_REGLP            PWR_CSR_REGLPF\r
+\r
+#define IS_PWR_GET_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB) || \\r
+                               ((FLAG) == PWR_FLAG_PVDO) || ((FLAG) == PWR_FLAG_VREFINTRDY) || \\r
+                               ((FLAG) == PWR_FLAG_VOS) || ((FLAG) == PWR_FLAG_REGLP))\r
+\r
+#define IS_PWR_CLEAR_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB))\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup PWR_Exported_Macros\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup PWR_Exported_Functions\r
+  * @{\r
+  */\r
+\r
+void PWR_DeInit(void);\r
+void PWR_RTCAccessCmd(FunctionalState NewState);\r
+void PWR_PVDCmd(FunctionalState NewState);\r
+void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel);\r
+void PWR_WakeUpPinCmd(uint32_t PWR_WakeUpPin, FunctionalState NewState);\r
+void PWR_FastWakeUpCmd(FunctionalState NewState);\r
+void PWR_UltraLowPowerCmd(FunctionalState NewState);\r
+void PWR_VoltageScalingConfig(uint32_t PWR_VoltageScaling);\r
+void PWR_EnterLowPowerRunMode(FunctionalState NewState);\r
+void PWR_EnterSleepMode(uint32_t PWR_Regulator, uint8_t PWR_SLEEPEntry);\r
+void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry);\r
+void PWR_EnterSTANDBYMode(void);\r
+FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG);\r
+void PWR_ClearFlag(uint32_t PWR_FLAG);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32L1xx_PWR_H */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r

diff --git a/Demo/CORTEX_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/inc/stm32l1xx_rcc.h b/Demo/CORTEX_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/inc/stm32l1xx_rcc.h
new file mode 100644 (file)
index 0000000..a9b949c
--- /dev/null
+++ b/Demo/CORTEX_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/inc/stm32l1xx_rcc.h
@@ -0,0 +1,471 @@
+/**\r
+  ******************************************************************************\r
+  * @file    stm32l1xx_rcc.h\r
+  * @author  MCD Application Team\r
+  * @version V1.0.0RC1\r
+  * @date    07/02/2010\r
+  * @brief   This file contains all the functions prototypes for the RCC \r
+  *          firmware library.\r
+  ******************************************************************************\r
+  * @copy\r
+  *\r
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+  *\r
+  * <h2><center>&copy; COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+  */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32L1xx_RCC_H\r
+#define __STM32L1xx_RCC_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+  * @{\r
+  */\r
+\r
+/** @addtogroup RCC\r
+  * @{\r
+  */\r
+\r
+/** @defgroup RCC_Exported_Types\r
+  * @{\r
+  */\r
+\r
+typedef struct\r
+{\r
+  uint32_t SYSCLK_Frequency;\r
+  uint32_t HCLK_Frequency;\r
+  uint32_t PCLK1_Frequency;\r
+  uint32_t PCLK2_Frequency;\r
+}RCC_ClocksTypeDef;\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup RCC_Exported_Constants\r
+  * @{\r
+  */\r
+\r
+/** @defgroup HSE_configuration \r
+  * @{\r
+  */\r
+\r
+#define RCC_HSE_OFF                      ((uint8_t)0x00)\r
+#define RCC_HSE_ON                       ((uint8_t)0x01)\r
+#define RCC_HSE_Bypass                   ((uint8_t)0x05)\r
+#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \\r
+                         ((HSE) == RCC_HSE_Bypass))\r
+\r
+/**\r
+  * @}\r
+  */ \r
+\r
+/** @defgroup MSI_Clock_Range \r
+  * @{\r
+  */\r
+\r
+#define RCC_MSIRange_64KHz               RCC_ICSCR_MSIRANGE_64KHz\r
+#define RCC_MSIRange_128KHz              RCC_ICSCR_MSIRANGE_128KHz\r
+#define RCC_MSIRange_256KHz              RCC_ICSCR_MSIRANGE_256KHz\r
+#define RCC_MSIRange_512KHz              RCC_ICSCR_MSIRANGE_512KHz\r
+#define RCC_MSIRange_1MHz                RCC_ICSCR_MSIRANGE_1MHz\r
+#define RCC_MSIRange_2MHz                RCC_ICSCR_MSIRANGE_2MHz\r
+#define RCC_MSIRange_4MHz                RCC_ICSCR_MSIRANGE_4MHz\r
+\r
+#define IS_RCC_MSI_CLOCK_RANGE(RANGE) (((RANGE) == RCC_MSIRange_64KHz) || \\r
+                                       ((RANGE) == RCC_MSIRange_128KHz) || \\r
+                                       ((RANGE) == RCC_MSIRange_256KHz) || \\r
+                                       ((RANGE) == RCC_MSIRange_512KHz) || \\r
+                                       ((RANGE) == RCC_MSIRange_1MHz) || \\r
+                                       ((RANGE) == RCC_MSIRange_2MHz) || \\r
+                                       ((RANGE) == RCC_MSIRange_4MHz))\r
+\r
+/**\r
+  * @}\r
+  */ \r
+  \r
+/** @defgroup PLL_Clock_Source \r
+  * @{\r
+  */\r
+\r
+#define RCC_PLLSource_HSI                ((uint8_t)0x00)\r
+#define RCC_PLLSource_HSE                ((uint8_t)0x01)\r
+\r
+#define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI) || \\r
+                                   ((SOURCE) == RCC_PLLSource_HSE))\r
+/**\r
+  * @}\r
+  */ \r
+\r
+/** @defgroup PLL_Multiplication_Factor \r
+  * @{\r
+  */\r
+\r
+#define RCC_PLLMul_3                     ((uint8_t)0x00)\r
+#define RCC_PLLMul_4                     ((uint8_t)0x04)\r
+#define RCC_PLLMul_6                     ((uint8_t)0x08)\r
+#define RCC_PLLMul_8                     ((uint8_t)0x0C)\r
+#define RCC_PLLMul_12                    ((uint8_t)0x10)\r
+#define RCC_PLLMul_16                    ((uint8_t)0x14)\r
+#define RCC_PLLMul_24                    ((uint8_t)0x18)\r
+#define RCC_PLLMul_32                    ((uint8_t)0x1C)\r
+#define RCC_PLLMul_48                    ((uint8_t)0x20)\r
+\r
+\r
+#define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_3) || ((MUL) == RCC_PLLMul_4) || \\r
+                             ((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_8) || \\r
+                             ((MUL) == RCC_PLLMul_12) || ((MUL) == RCC_PLLMul_16) || \\r
+                             ((MUL) == RCC_PLLMul_24) || ((MUL) == RCC_PLLMul_32) || \\r
+                             ((MUL) == RCC_PLLMul_48))\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup PLL_Divider_Factor \r
+  * @{\r
+  */\r
+\r
+#define RCC_PLLDiv_2                     ((uint8_t)0x40)\r
+#define RCC_PLLDiv_3                     ((uint8_t)0x80)\r
+#define RCC_PLLDiv_4                     ((uint8_t)0xC0)\r
+\r
+\r
+#define IS_RCC_PLL_DIV(DIV) (((DIV) == RCC_PLLDiv_2) || ((DIV) == RCC_PLLDiv_3) || \\r
+                             ((DIV) == RCC_PLLDiv_4))\r
+/**\r
+  * @}\r
+  */\r
+  \r
+/** @defgroup System_Clock_Source \r
+  * @{\r
+  */\r
+\r
+#define RCC_SYSCLKSource_MSI             RCC_CFGR_SW_MSI\r
+#define RCC_SYSCLKSource_HSI             RCC_CFGR_SW_HSI\r
+#define RCC_SYSCLKSource_HSE             RCC_CFGR_SW_HSE\r
+#define RCC_SYSCLKSource_PLLCLK          RCC_CFGR_SW_PLL\r
+#define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_MSI) || \\r
+                                      ((SOURCE) == RCC_SYSCLKSource_HSI) || \\r
+                                      ((SOURCE) == RCC_SYSCLKSource_HSE) || \\r
+                                      ((SOURCE) == RCC_SYSCLKSource_PLLCLK))\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup AHB_Clock_Source\r
+  * @{\r
+  */\r
+\r
+#define RCC_SYSCLK_Div1                  RCC_CFGR_HPRE_DIV1\r
+#define RCC_SYSCLK_Div2                  RCC_CFGR_HPRE_DIV2\r
+#define RCC_SYSCLK_Div4                  RCC_CFGR_HPRE_DIV4\r
+#define RCC_SYSCLK_Div8                  RCC_CFGR_HPRE_DIV8\r
+#define RCC_SYSCLK_Div16                 RCC_CFGR_HPRE_DIV16\r
+#define RCC_SYSCLK_Div64                 RCC_CFGR_HPRE_DIV64\r
+#define RCC_SYSCLK_Div128                RCC_CFGR_HPRE_DIV128\r
+#define RCC_SYSCLK_Div256                RCC_CFGR_HPRE_DIV256\r
+#define RCC_SYSCLK_Div512                RCC_CFGR_HPRE_DIV512\r
+#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \\r
+                           ((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \\r
+                           ((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \\r
+                           ((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \\r
+                           ((HCLK) == RCC_SYSCLK_Div512))\r
+/**\r
+  * @}\r
+  */ \r
+\r
+/** @defgroup APB1_APB2_Clock_Source\r
+  * @{\r
+  */\r
+\r
+#define RCC_HCLK_Div1                    RCC_CFGR_PPRE1_DIV1\r
+#define RCC_HCLK_Div2                    RCC_CFGR_PPRE1_DIV2\r
+#define RCC_HCLK_Div4                    RCC_CFGR_PPRE1_DIV4\r
+#define RCC_HCLK_Div8                    RCC_CFGR_PPRE1_DIV8\r
+#define RCC_HCLK_Div16                   RCC_CFGR_PPRE1_DIV16\r
+#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \\r
+                           ((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \\r
+                           ((PCLK) == RCC_HCLK_Div16))\r
+/**\r
+  * @}\r
+  */\r
+  \r
+\r
+/** @defgroup RCC_Interrupt_Source \r
+  * @{\r
+  */\r
+\r
+#define RCC_IT_LSIRDY                    ((uint8_t)0x01)\r
+#define RCC_IT_LSERDY                    ((uint8_t)0x02)\r
+#define RCC_IT_HSIRDY                    ((uint8_t)0x04)\r
+#define RCC_IT_HSERDY                    ((uint8_t)0x08)\r
+#define RCC_IT_PLLRDY                    ((uint8_t)0x10)\r
+#define RCC_IT_MSIRDY                    ((uint8_t)0x20)\r
+#define RCC_IT_CSS                       ((uint8_t)0x80)\r
+\r
+#define IS_RCC_IT(IT) ((((IT) & (uint8_t)0xC0) == 0x00) && ((IT) != 0x00))\r
+\r
+#define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \\r
+                           ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \\r
+                           ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_MSIRDY) || \\r
+                           ((IT) == RCC_IT_CSS))\r
+\r
+#define IS_RCC_CLEAR_IT(IT) ((((IT) & (uint8_t)0x40) == 0x00) && ((IT) != 0x00))\r
+\r
+/**\r
+  * @}\r
+  */\r
+  \r
+/** @defgroup LSE_Configuration \r
+  * @{\r
+  */\r
+\r
+#define RCC_LSE_OFF                      ((uint8_t)0x00)\r
+#define RCC_LSE_ON                       ((uint8_t)0x01)\r
+#define RCC_LSE_Bypass                   ((uint8_t)0x05)\r
+#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \\r
+                         ((LSE) == RCC_LSE_Bypass))\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup RTC_Clock_Source\r
+  * @{\r
+  */\r
+\r
+#define RCC_RTCCLKSource_LSE             RCC_CSR_RTCSEL_LSE\r
+#define RCC_RTCCLKSource_LSI             RCC_CSR_RTCSEL_LSI\r
+#define RCC_RTCCLKSource_HSE_Div2        RCC_CSR_RTCSEL_HSE\r
+#define RCC_RTCCLKSource_HSE_Div4        ((uint32_t)RCC_CSR_RTCSEL_HSE | RCC_CR_RTCPRE_0)\r
+#define RCC_RTCCLKSource_HSE_Div8        ((uint32_t)RCC_CSR_RTCSEL_HSE | RCC_CR_RTCPRE_1)\r
+#define RCC_RTCCLKSource_HSE_Div16       ((uint32_t)RCC_CSR_RTCSEL_HSE | RCC_CR_RTCPRE)\r
+#define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \\r
+                                      ((SOURCE) == RCC_RTCCLKSource_LSI) || \\r
+                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div2) || \\r
+                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div4) || \\r
+                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div8) || \\r
+                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div16))\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup AHB_Peripherals \r
+  * @{\r
+  */\r
+\r
+#define RCC_AHBPeriph_GPIOA               RCC_AHBENR_GPIOAEN\r
+#define RCC_AHBPeriph_GPIOB               RCC_AHBENR_GPIOBEN\r
+#define RCC_AHBPeriph_GPIOC               RCC_AHBENR_GPIOCEN\r
+#define RCC_AHBPeriph_GPIOD               RCC_AHBENR_GPIODEN\r
+#define RCC_AHBPeriph_GPIOE               RCC_AHBENR_GPIOEEN\r
+#define RCC_AHBPeriph_GPIOH               RCC_AHBENR_GPIOHEN\r
+#define RCC_AHBPeriph_CRC                 RCC_AHBENR_CRCEN\r
+#define RCC_AHBPeriph_FLITF               RCC_AHBENR_FLITFEN\r
+#define RCC_AHBPeriph_SRAM                RCC_AHBLPENR_SRAMLPEN\r
+#define RCC_AHBPeriph_DMA1                RCC_AHBENR_DMA1EN\r
+\r
+#define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xFEFF6FC0) == 0x00) && ((PERIPH) != 0x00))\r
+#define IS_RCC_AHB_LPMODE_PERIPH(PERIPH) ((((PERIPH) & 0xFEFE6FC0) == 0x00) && ((PERIPH) != 0x00))\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup APB2_Peripherals \r
+  * @{\r
+  */\r
+\r
+#define RCC_APB2Periph_SYSCFG            RCC_APB2ENR_SYSCFGEN\r
+#define RCC_APB2Periph_TIM9              RCC_APB2ENR_TIM9EN\r
+#define RCC_APB2Periph_TIM10             RCC_APB2ENR_TIM10EN\r
+#define RCC_APB2Periph_TIM11             RCC_APB2ENR_TIM11EN\r
+#define RCC_APB2Periph_ADC1              RCC_APB2ENR_ADC1EN\r
+#define RCC_APB2Periph_SPI1              RCC_APB2ENR_SPI1EN\r
+#define RCC_APB2Periph_USART1            RCC_APB2ENR_USART1EN\r
+\r
+#define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFADE2) == 0x00) && ((PERIPH) != 0x00))\r
+/**\r
+  * @}\r
+  */ \r
+\r
+/** @defgroup APB1_Peripherals \r
+  * @{\r
+  */\r
+\r
+#define RCC_APB1Periph_TIM2              RCC_APB1ENR_TIM2EN\r
+#define RCC_APB1Periph_TIM3              RCC_APB1ENR_TIM3EN\r
+#define RCC_APB1Periph_TIM4              RCC_APB1ENR_TIM4EN\r
+#define RCC_APB1Periph_TIM6              RCC_APB1ENR_TIM6EN\r
+#define RCC_APB1Periph_TIM7              RCC_APB1ENR_TIM7EN\r
+#define RCC_APB1Periph_LCD               RCC_APB1ENR_LCDEN\r
+#define RCC_APB1Periph_WWDG              RCC_APB1ENR_WWDGEN\r
+#define RCC_APB1Periph_SPI2              RCC_APB1ENR_SPI2EN\r
+#define RCC_APB1Periph_USART2            RCC_APB1ENR_USART2EN\r
+#define RCC_APB1Periph_USART3            RCC_APB1ENR_USART3EN\r
+#define RCC_APB1Periph_I2C1              RCC_APB1ENR_I2C1EN\r
+#define RCC_APB1Periph_I2C2              RCC_APB1ENR_I2C2EN\r
+#define RCC_APB1Periph_USB               RCC_APB1ENR_USBEN\r
+#define RCC_APB1Periph_PWR               RCC_APB1ENR_PWREN\r
+#define RCC_APB1Periph_DAC               RCC_APB1ENR_DACEN\r
+#define RCC_APB1Periph_COMP              RCC_APB1ENR_COMPEN\r
+\r
+#define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0x4F19B5C8) == 0x00) && ((PERIPH) != 0x00))\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup MCO_Clock_Source\r
+  * @{\r
+  */\r
+\r
+#define RCC_MCOSource_NoClock            ((uint8_t)0x00)\r
+#define RCC_MCOSource_SYSCLK             ((uint8_t)0x01)\r
+#define RCC_MCOSource_HSI                ((uint8_t)0x02)\r
+#define RCC_MCOSource_MSI                ((uint8_t)0x03)\r
+#define RCC_MCOSource_HSE                ((uint8_t)0x04)\r
+#define RCC_MCOSource_PLLCLK             ((uint8_t)0x05)\r
+#define RCC_MCOSource_LSI                ((uint8_t)0x06)\r
+#define RCC_MCOSource_LSE                ((uint8_t)0x07)\r
+\r
+#define IS_RCC_MCO_SOURCE(SOURCE) (((SOURCE) == RCC_MCOSource_NoClock) || ((SOURCE) == RCC_MCOSource_SYSCLK) || \\r
+                                   ((SOURCE) == RCC_MCOSource_HSI)  || ((SOURCE) == RCC_MCOSource_MSI) || \\r
+                                   ((SOURCE) == RCC_MCOSource_HSE)  || ((SOURCE) == RCC_MCOSource_PLLCLK) || \\r
+                                   ((SOURCE) == RCC_MCOSource_LSI) || ((SOURCE) == RCC_MCOSource_LSE))\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup MCO_Output_Divider \r
+  * @{\r
+  */\r
+\r
+#define RCC_MCODiv_1                     ((uint8_t)0x00)\r
+#define RCC_MCODiv_2                     ((uint8_t)0x10)\r
+#define RCC_MCODiv_4                     ((uint8_t)0x20)\r
+#define RCC_MCODiv_8                     ((uint8_t)0x30)\r
+#define RCC_MCODiv_16                    ((uint8_t)0x40)\r
+\r
+#define IS_RCC_MCO_DIV(DIV) (((DIV) == RCC_MCODiv_1) || ((DIV) == RCC_MCODiv_2) || \\r
+                             ((DIV) == RCC_MCODiv_4)  || ((DIV) == RCC_MCODiv_8) || \\r
+                             ((DIV) == RCC_MCODiv_16))\r
+/**\r
+  * @}\r
+  */  \r
+\r
+/** @defgroup RCC_Flag \r
+  * @{\r
+  */\r
+\r
+#define RCC_FLAG_HSIRDY                  ((uint8_t)0x21)\r
+#define RCC_FLAG_MSIRDY                  ((uint8_t)0x29)\r
+#define RCC_FLAG_HSERDY                  ((uint8_t)0x31)\r
+#define RCC_FLAG_PLLRDY                  ((uint8_t)0x39)\r
+#define RCC_FLAG_LSERDY                  ((uint8_t)0x49)\r
+#define RCC_FLAG_LSIRDY                  ((uint8_t)0x41)\r
+#define RCC_FLAG_OBLRST                  ((uint8_t)0x59)\r
+#define RCC_FLAG_PINRST                  ((uint8_t)0x5A)\r
+#define RCC_FLAG_PORRST                  ((uint8_t)0x5B)\r
+#define RCC_FLAG_SFTRST                  ((uint8_t)0x5C)\r
+#define RCC_FLAG_IWDGRST                 ((uint8_t)0x5D)\r
+#define RCC_FLAG_WWDGRST                 ((uint8_t)0x5E)\r
+#define RCC_FLAG_LPWRRST                 ((uint8_t)0x5F)\r
+\r
+#define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \\r
+                           ((FLAG) == RCC_FLAG_MSIRDY) || ((FLAG) == RCC_FLAG_PLLRDY) || \\r
+                           ((FLAG) == RCC_FLAG_LSERDY) || ((FLAG) == RCC_FLAG_LSIRDY) || \\r
+                           ((FLAG) == RCC_FLAG_PINRST) || ((FLAG) == RCC_FLAG_PORRST) || \\r
+                           ((FLAG) == RCC_FLAG_SFTRST) || ((FLAG) == RCC_FLAG_IWDGRST)|| \\r
+                           ((FLAG) == RCC_FLAG_WWDGRST)|| ((FLAG) == RCC_FLAG_LPWRRST)|| \\r
+                           ((FLAG) == RCC_FLAG_WWDGRST))\r
+\r
+#define IS_RCC_HSI_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)\r
+#define IS_RCC_MSI_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x3F)\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup RCC_Exported_Macros\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup RCC_Exported_Functions\r
+  * @{\r
+  */\r
+\r
+void RCC_DeInit(void);\r
+void RCC_HSEConfig(uint8_t RCC_HSE);\r
+ErrorStatus RCC_WaitForHSEStartUp(void);\r
+void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue);\r
+void RCC_AdjustMSICalibrationValue(uint8_t MSICalibrationValue);\r
+void RCC_MSIRangeConfig(uint32_t RCC_MSIRange);\r
+void RCC_MSICmd(FunctionalState NewState);\r
+void RCC_HSICmd(FunctionalState NewState);\r
+void RCC_PLLConfig(uint8_t RCC_PLLSource, uint8_t RCC_PLLMul, uint8_t RCC_PLLDiv);\r
+void RCC_PLLCmd(FunctionalState NewState);\r
+void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource);\r
+uint8_t RCC_GetSYSCLKSource(void);\r
+void RCC_HCLKConfig(uint32_t RCC_SYSCLK);\r
+void RCC_PCLK1Config(uint32_t RCC_HCLK);\r
+void RCC_PCLK2Config(uint32_t RCC_HCLK);\r
+void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState);\r
+void RCC_LSEConfig(uint8_t RCC_LSE);\r
+void RCC_LSICmd(FunctionalState NewState);\r
+void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource);\r
+void RCC_RTCCLKCmd(FunctionalState NewState);\r
+void RCC_RTCResetCmd(FunctionalState NewState);\r
+void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks);\r
+void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);\r
+void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);\r
+void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);\r
+void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);\r
+void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);\r
+void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);\r
+void RCC_AHBPeriphClockLPModeCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);\r
+void RCC_APB2PeriphClockLPModeCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);\r
+void RCC_APB1PeriphClockLPModeCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);\r
+void RCC_ClockSecuritySystemCmd(FunctionalState NewState);\r
+void RCC_MCOConfig(uint8_t RCC_MCOSource, uint8_t RCC_MCODiv);\r
+FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG);\r
+void RCC_ClearFlag(void);\r
+ITStatus RCC_GetITStatus(uint8_t RCC_IT);\r
+void RCC_ClearITPendingBit(uint8_t RCC_IT);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32L1xx_RCC_H */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */ \r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r

diff --git a/Demo/CORTEX_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/inc/stm32l1xx_spi.h b/Demo/CORTEX_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/inc/stm32l1xx_spi.h
new file mode 100644 (file)
index 0000000..86a2b31
--- /dev/null
+++ b/Demo/CORTEX_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/inc/stm32l1xx_spi.h
@@ -0,0 +1,380 @@
+/**\r
+  ******************************************************************************\r
+  * @file    stm32l1xx_spi.h\r
+  * @author  MCD Application Team\r
+  * @version V1.0.0RC1\r
+  * @date    07/02/2010\r
+  * @brief   This file contains all the functions prototypes for the SPI \r
+  *          firmware library.\r
+  ******************************************************************************\r
+  * @copy\r
+  *\r
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+  *\r
+  * <h2><center>&copy; COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+  */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32L1xx_SPI_H\r
+#define __STM32L1xx_SPI_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+  * @{\r
+  */\r
+\r
+/** @addtogroup SPI\r
+  * @{\r
+  */ \r
+\r
+/** @defgroup SPI_Exported_Types\r
+  * @{\r
+  */\r
+\r
+/** \r
+  * @brief  SPI Init structure definition  \r
+  */\r
+\r
+typedef struct\r
+{\r
+  uint16_t SPI_Direction;           /*!< Specifies the SPI unidirectional or bidirectional data mode.\r
+                                         This parameter can be any combination of @ref SPI_data_direction */\r
+\r
+  uint16_t SPI_Mode;                /*!< Specifies the SPI operating mode.\r
+                                         This parameter can be any combination of @ref SPI_mode */\r
+\r
+  uint16_t SPI_DataSize;            /*!< Specifies the SPI data size.\r
+                                         This parameter can be any combination of @ref SPI_data_size */\r
+\r
+  uint16_t SPI_CPOL;                /*!< Specifies the serial clock steady state.\r
+                                         This parameter can be any combination of @ref SPI_Clock_Polarity */\r
+\r
+  uint16_t SPI_CPHA;                /*!< Specifies the clock active edge for the bit capture.\r
+                                         This parameter can be any combination of @ref SPI_Clock_Phase */\r
+\r
+  uint16_t SPI_NSS;                 /*!< Specifies whether the NSS signal is managed by\r
+                                         hardware (NSS pin) or by software using the SSI bit.\r
+                                         This parameter can be any combination of @ref SPI_Slave_Select_management */\r
+ \r
+  uint16_t SPI_BaudRatePrescaler;   /*!< Specifies the Baud Rate prescaler value which will be\r
+                                         used to configure the transmit and receive SCK clock.\r
+                                         This parameter can be any combination of @ref SPI_BaudRate_Prescaler.\r
+                                         @note The communication clock is derived from the master\r
+                                               clock. The slave clock does not need to be set. */\r
+\r
+  uint16_t SPI_FirstBit;            /*!< Specifies whether data transfers start from MSB or LSB bit.\r
+                                         This parameter can be any combination of @ref SPI_MSB_LSB_transmission */\r
+\r
+  uint16_t SPI_CRCPolynomial;       /*!< Specifies the polynomial used for the CRC calculation. */\r
+}SPI_InitTypeDef;\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup SPI_Exported_Constants\r
+  * @{\r
+  */\r
+\r
+#define IS_SPI_ALL_PERIPH(PERIPH) (((PERIPH) == SPI1) || \\r
+                                   ((PERIPH) == SPI2))\r
+\r
+/** @defgroup SPI_data_direction \r
+  * @{\r
+  */\r
+  \r
+#define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000)\r
+#define SPI_Direction_2Lines_RxOnly     ((uint16_t)0x0400)\r
+#define SPI_Direction_1Line_Rx          ((uint16_t)0x8000)\r
+#define SPI_Direction_1Line_Tx          ((uint16_t)0xC000)\r
+#define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_Direction_2Lines_FullDuplex) || \\r
+                                     ((MODE) == SPI_Direction_2Lines_RxOnly) || \\r
+                                     ((MODE) == SPI_Direction_1Line_Rx) || \\r
+                                     ((MODE) == SPI_Direction_1Line_Tx))\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup SPI_mode \r
+  * @{\r
+  */\r
+\r
+#define SPI_Mode_Master                 ((uint16_t)0x0104)\r
+#define SPI_Mode_Slave                  ((uint16_t)0x0000)\r
+#define IS_SPI_MODE(MODE) (((MODE) == SPI_Mode_Master) || \\r
+                           ((MODE) == SPI_Mode_Slave))\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup SPI_data_size \r
+  * @{\r
+  */\r
+\r
+#define SPI_DataSize_16b                ((uint16_t)0x0800)\r
+#define SPI_DataSize_8b                 ((uint16_t)0x0000)\r
+#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DataSize_16b) || \\r
+                                   ((DATASIZE) == SPI_DataSize_8b))\r
+/**\r
+  * @}\r
+  */ \r
+\r
+/** @defgroup SPI_Clock_Polarity \r
+  * @{\r
+  */\r
+\r
+#define SPI_CPOL_Low                    ((uint16_t)0x0000)\r
+#define SPI_CPOL_High                   ((uint16_t)0x0002)\r
+#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_CPOL_Low) || \\r
+                           ((CPOL) == SPI_CPOL_High))\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup SPI_Clock_Phase \r
+  * @{\r
+  */\r
+\r
+#define SPI_CPHA_1Edge                  ((uint16_t)0x0000)\r
+#define SPI_CPHA_2Edge                  ((uint16_t)0x0001)\r
+#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_CPHA_1Edge) || \\r
+                           ((CPHA) == SPI_CPHA_2Edge))\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup SPI_Slave_Select_management \r
+  * @{\r
+  */\r
+\r
+#define SPI_NSS_Soft                    ((uint16_t)0x0200)\r
+#define SPI_NSS_Hard                    ((uint16_t)0x0000)\r
+#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_Soft) || \\r
+                         ((NSS) == SPI_NSS_Hard))\r
+/**\r
+  * @}\r
+  */ \r
+\r
+/** @defgroup SPI_BaudRate_Prescaler \r
+  * @{\r
+  */\r
+\r
+#define SPI_BaudRatePrescaler_2         ((uint16_t)0x0000)\r
+#define SPI_BaudRatePrescaler_4         ((uint16_t)0x0008)\r
+#define SPI_BaudRatePrescaler_8         ((uint16_t)0x0010)\r
+#define SPI_BaudRatePrescaler_16        ((uint16_t)0x0018)\r
+#define SPI_BaudRatePrescaler_32        ((uint16_t)0x0020)\r
+#define SPI_BaudRatePrescaler_64        ((uint16_t)0x0028)\r
+#define SPI_BaudRatePrescaler_128       ((uint16_t)0x0030)\r
+#define SPI_BaudRatePrescaler_256       ((uint16_t)0x0038)\r
+#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BaudRatePrescaler_2) || \\r
+                                              ((PRESCALER) == SPI_BaudRatePrescaler_4) || \\r
+                                              ((PRESCALER) == SPI_BaudRatePrescaler_8) || \\r
+                                              ((PRESCALER) == SPI_BaudRatePrescaler_16) || \\r
+                                              ((PRESCALER) == SPI_BaudRatePrescaler_32) || \\r
+                                              ((PRESCALER) == SPI_BaudRatePrescaler_64) || \\r
+                                              ((PRESCALER) == SPI_BaudRatePrescaler_128) || \\r
+                                              ((PRESCALER) == SPI_BaudRatePrescaler_256))\r
+/**\r
+  * @}\r
+  */ \r
+\r
+/** @defgroup SPI_MSB_LSB_transmission \r
+  * @{\r
+  */\r
+\r
+#define SPI_FirstBit_MSB                ((uint16_t)0x0000)\r
+#define SPI_FirstBit_LSB                ((uint16_t)0x0080)\r
+#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FirstBit_MSB) || \\r
+                               ((BIT) == SPI_FirstBit_LSB))\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup SPI_DMA_transfer_requests \r
+  * @{\r
+  */\r
+\r
+#define SPI_DMAReq_Tx               ((uint16_t)0x0002)\r
+#define SPI_DMAReq_Rx               ((uint16_t)0x0001)\r
+#define IS_SPI_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFFFC) == 0x00) && ((DMAREQ) != 0x00))\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup SPI_NSS_internal_software_mangement \r
+  * @{\r
+  */\r
+\r
+#define SPI_NSSInternalSoft_Set         ((uint16_t)0x0100)\r
+#define SPI_NSSInternalSoft_Reset       ((uint16_t)0xFEFF)\r
+#define IS_SPI_NSS_INTERNAL(INTERNAL) (((INTERNAL) == SPI_NSSInternalSoft_Set) || \\r
+                                       ((INTERNAL) == SPI_NSSInternalSoft_Reset))\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup SPI_CRC_Transmit_Receive \r
+  * @{\r
+  */\r
+\r
+#define SPI_CRC_Tx                      ((uint8_t)0x00)\r
+#define SPI_CRC_Rx                      ((uint8_t)0x01)\r
+#define IS_SPI_CRC(CRC) (((CRC) == SPI_CRC_Tx) || ((CRC) == SPI_CRC_Rx))\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup SPI_direction_transmit_receive \r
+  * @{\r
+  */\r
+\r
+#define SPI_Direction_Rx                ((uint16_t)0xBFFF)\r
+#define SPI_Direction_Tx                ((uint16_t)0x4000)\r
+#define IS_SPI_DIRECTION(DIRECTION) (((DIRECTION) == SPI_Direction_Rx) || \\r
+                                     ((DIRECTION) == SPI_Direction_Tx))\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup SPI_interrupts_definition \r
+  * @{\r
+  */\r
+\r
+#define SPI_IT_TXE                  ((uint8_t)0x71)\r
+#define SPI_IT_RXNE                 ((uint8_t)0x60)\r
+#define SPI_IT_ERR                  ((uint8_t)0x50)\r
+#define IS_SPI_CONFIG_IT(IT) (((IT) == SPI_IT_TXE) || \\r
+                                 ((IT) == SPI_IT_RXNE) || \\r
+                                 ((IT) == SPI_IT_ERR))\r
+#define SPI_IT_OVR                  ((uint8_t)0x56)\r
+#define SPI_IT_MODF                     ((uint8_t)0x55)\r
+#define SPI_IT_CRCERR                   ((uint8_t)0x54)\r
+#define IS_SPI_CLEAR_IT(IT) (((IT) == SPI_IT_CRCERR))\r
+#define IS_SPI_GET_IT(IT) (((IT) == SPI_IT_RXNE) || ((IT) == SPI_IT_TXE) || \\r
+                               ((IT) == SPI_IT_CRCERR) || \\r
+                               ((IT) == SPI_IT_MODF) || ((IT) == SPI_IT_OVR))\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup SPI_flags_definition \r
+  * @{\r
+  */\r
+\r
+#define SPI_FLAG_RXNE               ((uint16_t)0x0001)\r
+#define SPI_FLAG_TXE                ((uint16_t)0x0002)\r
+#define SPI_FLAG_CRCERR                 ((uint16_t)0x0010)\r
+#define SPI_FLAG_MODF                   ((uint16_t)0x0020)\r
+#define SPI_FLAG_OVR                ((uint16_t)0x0040)\r
+#define SPI_FLAG_BSY                ((uint16_t)0x0080)\r
+#define IS_SPI_CLEAR_FLAG(FLAG) (((FLAG) == SPI_FLAG_CRCERR))\r
+#define IS_SPI_GET_FLAG(FLAG) (((FLAG) == SPI_FLAG_BSY) || ((FLAG) == SPI_FLAG_OVR) || \\r
+                                   ((FLAG) == SPI_FLAG_MODF) || ((FLAG) == SPI_FLAG_CRCERR) || \\r
+                                   ((FLAG) == SPI_FLAG_TXE) || ((FLAG) == SPI_FLAG_RXNE))\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup SPI_CRC_polynomial \r
+  * @{\r
+  */\r
+\r
+#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) >= 0x1)\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup SPI_Legacy \r
+  * @{\r
+  */\r
+\r
+#define SPI_I2S_DMAReq_Tx            SPI_DMAReq_Tx\r
+#define SPI_I2S_DMAReq_Rx            SPI_DMAReq_Rx\r
+#define SPI_I2S_IT_TXE               SPI_IT_TXE\r
+#define SPI_I2S_IT_RXNE              SPI_IT_RXNE\r
+#define SPI_I2S_IT_ERR               SPI_IT_ERR\r
+#define SPI_I2S_IT_OVR               SPI_IT_OVR\r
+#define SPI_I2S_FLAG_RXNE            SPI_FLAG_RXNE\r
+#define SPI_I2S_FLAG_TXE             SPI_FLAG_TXE\r
+#define SPI_I2S_FLAG_OVR             SPI_FLAG_OVR\r
+#define SPI_I2S_FLAG_BSY             SPI_FLAG_BSY\r
+#define SPI_I2S_DeInit               SPI_DeInit\r
+#define SPI_I2S_ITConfig             SPI_ITConfig\r
+#define SPI_I2S_DMACmd               SPI_DMACmd\r
+#define SPI_I2S_SendData             SPI_SendData\r
+#define SPI_I2S_ReceiveData          SPI_ReceiveData\r
+#define SPI_I2S_GetFlagStatus        SPI_GetFlagStatus\r
+#define SPI_I2S_ClearFlag            SPI_ClearFlag\r
+#define SPI_I2S_GetITStatus          SPI_GetITStatus\r
+#define SPI_I2S_ClearITPendingBit    SPI_ClearITPendingBit\r
+/**\r
+  * @}\r
+  */\r
+  \r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup SPI_Exported_Macros\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup SPI_Exported_Functions\r
+  * @{\r
+  */\r
+\r
+void SPI_DeInit(SPI_TypeDef* SPIx);\r
+void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct);\r
+void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct);\r
+void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState);\r
+void SPI_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_IT, FunctionalState NewState);\r
+void SPI_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_DMAReq, FunctionalState NewState);\r
+void SPI_SendData(SPI_TypeDef* SPIx, uint16_t Data);\r
+uint16_t SPI_ReceiveData(SPI_TypeDef* SPIx);\r
+void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft);\r
+void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState);\r
+void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize);\r
+void SPI_TransmitCRC(SPI_TypeDef* SPIx);\r
+void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState);\r
+uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC);\r
+uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx);\r
+void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction);\r
+FlagStatus SPI_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_FLAG);\r
+void SPI_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_FLAG);\r
+ITStatus SPI_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_IT);\r
+void SPI_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_IT);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /*__STM32l15x_SPI_H */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r

diff --git a/Demo/CORTEX_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/inc/stm32l1xx_syscfg.h b/Demo/CORTEX_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/inc/stm32l1xx_syscfg.h
new file mode 100644 (file)
index 0000000..cd51e92
--- /dev/null
+++ b/Demo/CORTEX_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/inc/stm32l1xx_syscfg.h
@@ -0,0 +1,381 @@
+/**\r
+  ******************************************************************************\r
+  * @file    stm32l1xx_syscfg.h\r
+  * @author  MCD Application Team\r
+  * @version V1.0.0RC1\r
+  * @date    07/02/2010\r
+  * @brief   This file contains all the functions prototypes for the SYSCFG \r
+  *          firmware library.\r
+  ******************************************************************************\r
+  * @copy\r
+  *\r
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+  *\r
+  * <h2><center>&copy; COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+  */ \r
+\r
+/*!< Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32L1xx_SYSCFG_H\r
+#define __STM32L1xx_SYSCFG_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/*!< Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+  * @{\r
+  */\r
+\r
+/** @addtogroup SYSCFG\r
+  * @{\r
+  */ \r
+  \r
+/** @defgroup SYSCFG_Exported_Types\r
+  * @{\r
+  */\r
+\r
+/** @defgroup EXTI_Port_Sources \r
+  * @{\r
+  */ \r
+#define EXTI_PortSourceGPIOA       ((uint8_t)0x00)\r
+#define EXTI_PortSourceGPIOB       ((uint8_t)0x01)\r
+#define EXTI_PortSourceGPIOC       ((uint8_t)0x02)\r
+#define EXTI_PortSourceGPIOD       ((uint8_t)0x03)\r
+#define EXTI_PortSourceGPIOE       ((uint8_t)0x04)\r
+#define EXTI_PortSourceGPIOH       ((uint8_t)0x05)\r
+                                      \r
+#define IS_EXTI_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == EXTI_PortSourceGPIOA) || \\r
+                                         ((PORTSOURCE) == EXTI_PortSourceGPIOB) || \\r
+                                         ((PORTSOURCE) == EXTI_PortSourceGPIOC) || \\r
+                                         ((PORTSOURCE) == EXTI_PortSourceGPIOD) || \\r
+                                         ((PORTSOURCE) == EXTI_PortSourceGPIOE) || \\r
+                                         ((PORTSOURCE) == EXTI_PortSourceGPIOH)) \r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup EXTI_Pin_sources \r
+  * @{\r
+  */ \r
+#define EXTI_PinSource0            ((uint8_t)0x00)\r
+#define EXTI_PinSource1            ((uint8_t)0x01)\r
+#define EXTI_PinSource2            ((uint8_t)0x02)\r
+#define EXTI_PinSource3            ((uint8_t)0x03)\r
+#define EXTI_PinSource4            ((uint8_t)0x04)\r
+#define EXTI_PinSource5            ((uint8_t)0x05)\r
+#define EXTI_PinSource6            ((uint8_t)0x06)\r
+#define EXTI_PinSource7            ((uint8_t)0x07)\r
+#define EXTI_PinSource8            ((uint8_t)0x08)\r
+#define EXTI_PinSource9            ((uint8_t)0x09)\r
+#define EXTI_PinSource10           ((uint8_t)0x0A)\r
+#define EXTI_PinSource11           ((uint8_t)0x0B)\r
+#define EXTI_PinSource12           ((uint8_t)0x0C)\r
+#define EXTI_PinSource13           ((uint8_t)0x0D)\r
+#define EXTI_PinSource14           ((uint8_t)0x0E)\r
+#define EXTI_PinSource15           ((uint8_t)0x0F)\r
+#define IS_EXTI_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == EXTI_PinSource0) || \\r
+                                       ((PINSOURCE) == EXTI_PinSource1) || \\r
+                                       ((PINSOURCE) == EXTI_PinSource2) || \\r
+                                       ((PINSOURCE) == EXTI_PinSource3) || \\r
+                                       ((PINSOURCE) == EXTI_PinSource4) || \\r
+                                       ((PINSOURCE) == EXTI_PinSource5) || \\r
+                                       ((PINSOURCE) == EXTI_PinSource6) || \\r
+                                       ((PINSOURCE) == EXTI_PinSource7) || \\r
+                                       ((PINSOURCE) == EXTI_PinSource8) || \\r
+                                       ((PINSOURCE) == EXTI_PinSource9) || \\r
+                                       ((PINSOURCE) == EXTI_PinSource10) || \\r
+                                       ((PINSOURCE) == EXTI_PinSource11) || \\r
+                                       ((PINSOURCE) == EXTI_PinSource12) || \\r
+                                       ((PINSOURCE) == EXTI_PinSource13) || \\r
+                                       ((PINSOURCE) == EXTI_PinSource14) || \\r
+                                       ((PINSOURCE) == EXTI_PinSource15))\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup SYSCFG_Memory_Remap_Config \r
+  * @{\r
+  */ \r
+#define SYSCFG_MemoryRemap_Flash       ((uint8_t)0x00)\r
+#define SYSCFG_MemoryRemap_SystemFlash ((uint8_t)0x01)\r
+#define SYSCFG_MemoryRemap_SRAM        ((uint8_t)0x03)\r
+   \r
+#define IS_SYSCFG_MEMORY_REMAP_CONFING(REMAP) (((REMAP) == SYSCFG_MemoryRemap_Flash) || \\r
+                                               ((REMAP) == SYSCFG_MemoryRemap_SystemFlash) || \\r
+                                               ((REMAP) == SYSCFG_MemoryRemap_SRAM))\r
+\r
+\r
+/** @defgroup RI_Resistor\r
+  * @{\r
+  */\r
+\r
+#define RI_Resistor_10KPU          COMP_CSR_10KPU\r
+#define RI_Resistor_400KPU         COMP_CSR_400KPU\r
+#define RI_Resistor_10KPD          COMP_CSR_10KPD\r
+#define RI_Resistor_400KPD         COMP_CSR_400KPD\r
+\r
+#define IS_RI_RESISTOR(RESISTOR)  (((RESISTOR) == COMP_CSR_10KPU) || \\r
+                                   ((RESISTOR) == COMP_CSR_400KPU) || \\r
+                                   ((RESISTOR) == COMP_CSR_10KPD) || \\r
+                                   ((RESISTOR) == COMP_CSR_400KPD))\r
+ \r
+/**\r
+  * @}\r
+  */ \r
+\r
+/** @defgroup RI_InputCapture\r
+  * @{\r
+  */ \r
+  \r
+#define RI_InputCapture_IC1  RI_ICR_IC1    /*!< Input Capture 1 */\r
+#define RI_InputCapture_IC2  RI_ICR_IC2    /*!< Input Capture 2 */\r
+#define RI_InputCapture_IC3  RI_ICR_IC3    /*!< Input Capture 3 */\r
+#define RI_InputCapture_IC4  RI_ICR_IC4    /*!< Input Capture 4 */\r
+\r
+#define IS_RI_INPUTCAPTURE(INPUTCAPTURE) ((((INPUTCAPTURE) & (uint32_t)0xFFC2FFFF) == 0x00) && ((INPUTCAPTURE) != (uint32_t)0x00))\r
+/**\r
+  * @}\r
+  */ \r
+  \r
+/** @defgroup TIM_Select\r
+  * @{\r
+  */ \r
+  \r
+#define TIM_Select_None  ((uint32_t)0x00000000)    /*!< None selected */\r
+#define TIM_Select_TIM2  ((uint32_t)0x00010000)    /*!< Timer 2 selected */\r
+#define TIM_Select_TIM3  ((uint32_t)0x00020000)    /*!< Timer 3 selected */\r
+#define TIM_Select_TIM4  ((uint32_t)0x00030000)    /*!< Timer 4 selected */\r
+\r
+#define IS_RI_TIM(TIM) (((TIM) == TIM_Select_None) || \\r
+                        ((TIM) == TIM_Select_TIM2) || \\r
+                        ((TIM) == TIM_Select_TIM3) || \\r
+                        ((TIM) == TIM_Select_TIM4))\r
+\r
+/**\r
+  * @}\r
+  */ \r
+  \r
+/** @defgroup RI_InputCaptureRouting\r
+  * @{\r
+  */ \r
+                                                          /* TIMx_IC1 TIMx_IC2  TIMx_IC3  TIMx_IC4 */  \r
+#define RI_InputCaptureRouting_0   ((uint32_t)0x00000000) /* PA0       PA1      PA2       PA3      */\r
+#define RI_InputCaptureRouting_1   ((uint32_t)0x00000001) /* PA4       PA5      PA6       PA7      */\r
+#define RI_InputCaptureRouting_2   ((uint32_t)0x00000002) /* PA8       PA9      PA10      PA11     */\r
+#define RI_InputCaptureRouting_3   ((uint32_t)0x00000003) /* PA12      PA13     PA14      PA15     */\r
+#define RI_InputCaptureRouting_4   ((uint32_t)0x00000004) /* PC0       PC1      PC2       PC3      */\r
+#define RI_InputCaptureRouting_5   ((uint32_t)0x00000005) /* PC4       PC5      PC6       PC7      */\r
+#define RI_InputCaptureRouting_6   ((uint32_t)0x00000006) /* PC8       PC9      PC10      PC11     */\r
+#define RI_InputCaptureRouting_7   ((uint32_t)0x00000007) /* PC12      PC13     PC14      PC15     */\r
+#define RI_InputCaptureRouting_8   ((uint32_t)0x00000008) /* PD0       PD1      PD2       PD3      */\r
+#define RI_InputCaptureRouting_9   ((uint32_t)0x00000009) /* PD4       PD5      PD6       PD7      */\r
+#define RI_InputCaptureRouting_10  ((uint32_t)0x0000000A) /* PD8       PD9      PD10      PD11     */\r
+#define RI_InputCaptureRouting_11  ((uint32_t)0x0000000B) /* PD12      PD13     PD14      PD15     */\r
+#define RI_InputCaptureRouting_12  ((uint32_t)0x0000000C) /* PE0       PE1      PE2       PE3      */\r
+#define RI_InputCaptureRouting_13  ((uint32_t)0x0000000D) /* PE4       PE5      PE6       PE7      */\r
+#define RI_InputCaptureRouting_14  ((uint32_t)0x0000000E) /* PE8       PE9      PE10      PE11     */\r
+#define RI_InputCaptureRouting_15  ((uint32_t)0x0000000F) /* PE12      PE13     PE14      PE15     */\r
+\r
+#define IS_RI_INPUTCAPTURE_ROUTING(ROUTING) (((ROUTING) == RI_InputCaptureRouting_0) || \\r
+                                             ((ROUTING) == RI_InputCaptureRouting_1) || \\r
+                                             ((ROUTING) == RI_InputCaptureRouting_2) || \\r
+                                             ((ROUTING) == RI_InputCaptureRouting_3) || \\r
+                                             ((ROUTING) == RI_InputCaptureRouting_4) || \\r
+                                             ((ROUTING) == RI_InputCaptureRouting_5) || \\r
+                                             ((ROUTING) == RI_InputCaptureRouting_6) || \\r
+                                             ((ROUTING) == RI_InputCaptureRouting_7) || \\r
+                                             ((ROUTING) == RI_InputCaptureRouting_8) || \\r
+                                             ((ROUTING) == RI_InputCaptureRouting_9) || \\r
+                                             ((ROUTING) == RI_InputCaptureRouting_10) || \\r
+                                             ((ROUTING) == RI_InputCaptureRouting_11) || \\r
+                                             ((ROUTING) == RI_InputCaptureRouting_12) || \\r
+                                             ((ROUTING) == RI_InputCaptureRouting_13) || \\r
+                                             ((ROUTING) == RI_InputCaptureRouting_14) || \\r
+                                             ((ROUTING) == RI_InputCaptureRouting_15))\r
+\r
+/**\r
+  * @}\r
+  */ \r
+\r
+/** @defgroup RI_IOSwitch\r
+  * @{\r
+  */ \r
+  \r
+/* ASCR1 I/O switch: bit 28 is set to '1' to indicate that the mask is in ASCR1 register */\r
+#define RI_IOSwitch_CH0        ((uint32_t)0x10000001)\r
+#define RI_IOSwitch_CH1        ((uint32_t)0x10000002)\r
+#define RI_IOSwitch_CH2        ((uint32_t)0x10000004)\r
+#define RI_IOSwitch_CH3        ((uint32_t)0x10000008)\r
+#define RI_IOSwitch_CH4        ((uint32_t)0x10000010)\r
+#define RI_IOSwitch_CH5        ((uint32_t)0x10000020)\r
+#define RI_IOSwitch_CH6        ((uint32_t)0x10000040)\r
+#define RI_IOSwitch_CH7        ((uint32_t)0x10000080)\r
+#define RI_IOSwitch_CH8        ((uint32_t)0x10000100)\r
+#define RI_IOSwitch_CH9        ((uint32_t)0x10000200)\r
+#define RI_IOSwitch_CH10       ((uint32_t)0x10000400)\r
+#define RI_IOSwitch_CH11       ((uint32_t)0x10000800)\r
+#define RI_IOSwitch_CH12       ((uint32_t)0x10001000)\r
+#define RI_IOSwitch_CH13       ((uint32_t)0x10002000)\r
+#define RI_IOSwitch_CH14       ((uint32_t)0x10004000)\r
+#define RI_IOSwitch_CH15       ((uint32_t)0x10008000)\r
+#define RI_IOSwitch_CH18       ((uint32_t)0x10040000)\r
+#define RI_IOSwitch_CH19       ((uint32_t)0x10080000)\r
+#define RI_IOSwitch_CH20       ((uint32_t)0x10100000)\r
+#define RI_IOSwitch_CH21       ((uint32_t)0x10200000)\r
+#define RI_IOSwitch_CH22       ((uint32_t)0x10400000)\r
+#define RI_IOSwitch_CH23       ((uint32_t)0x10800000)\r
+#define RI_IOSwitch_CH24       ((uint32_t)0x11000000)\r
+#define RI_IOSwitch_CH25       ((uint32_t)0x12000000)\r
+#define RI_IOSwitch_VCOMP      ((uint32_t)0x14000000) /* VCOMP is an internal switch used to connect \r
+                                                         selected channel to COMP1 non inverting input */\r
+\r
+/* ASCR2 IO switch: : bit 28 is set to '0' to indicate that the mask is in ASCR2 register */  \r
+#define RI_IOSwitch_GR10_1     ((uint32_t)0x00000001)\r
+#define RI_IOSwitch_GR10_2     ((uint32_t)0x00000002)\r
+#define RI_IOSwitch_GR10_3     ((uint32_t)0x00000004)\r
+#define RI_IOSwitch_GR10_4     ((uint32_t)0x00000008)\r
+#define RI_IOSwitch_GR6_1      ((uint32_t)0x00000010)\r
+#define RI_IOSwitch_GR6_2      ((uint32_t)0x00000020)\r
+#define RI_IOSwitch_GR5_1      ((uint32_t)0x00000040)\r
+#define RI_IOSwitch_GR5_2      ((uint32_t)0x00000080)\r
+#define RI_IOSwitch_GR5_3      ((uint32_t)0x00000100)\r
+#define RI_IOSwitch_GR4_1      ((uint32_t)0x00000200)\r
+#define RI_IOSwitch_GR4_2      ((uint32_t)0x00000400)\r
+#define RI_IOSwitch_GR4_3      ((uint32_t)0x00000800)\r
+\r
+#define IS_RI_IOSWITCH(IOSWITCH) (((IOSWITCH) == RI_IOSwitch_CH0) || \\r
+                                  ((IOSWITCH) == RI_IOSwitch_CH1) || \\r
+                                  ((IOSWITCH) == RI_IOSwitch_CH2) || \\r
+                                  ((IOSWITCH) == RI_IOSwitch_CH3) || \\r
+                                  ((IOSWITCH) == RI_IOSwitch_CH4) || \\r
+                                  ((IOSWITCH) == RI_IOSwitch_CH5) || \\r
+                                  ((IOSWITCH) == RI_IOSwitch_CH6) || \\r
+                                  ((IOSWITCH) == RI_IOSwitch_CH7) || \\r
+                                  ((IOSWITCH) == RI_IOSwitch_CH8) || \\r
+                                  ((IOSWITCH) == RI_IOSwitch_CH9) || \\r
+                                  ((IOSWITCH) == RI_IOSwitch_CH10) || \\r
+                                  ((IOSWITCH) == RI_IOSwitch_CH11) || \\r
+                                  ((IOSWITCH) == RI_IOSwitch_CH12) || \\r
+                                  ((IOSWITCH) == RI_IOSwitch_CH13) || \\r
+                                  ((IOSWITCH) == RI_IOSwitch_CH14) || \\r
+                                  ((IOSWITCH) == RI_IOSwitch_CH15) || \\r
+                                  ((IOSWITCH) == RI_IOSwitch_CH18) || \\r
+                                  ((IOSWITCH) == RI_IOSwitch_CH19) || \\r
+                                  ((IOSWITCH) == RI_IOSwitch_CH20) || \\r
+                                  ((IOSWITCH) == RI_IOSwitch_CH21) || \\r
+                                  ((IOSWITCH) == RI_IOSwitch_CH22) || \\r
+                                  ((IOSWITCH) == RI_IOSwitch_CH23) || \\r
+                                  ((IOSWITCH) == RI_IOSwitch_CH24) || \\r
+                                  ((IOSWITCH) == RI_IOSwitch_CH25) || \\r
+                                  ((IOSWITCH) == RI_IOSwitch_VCOMP) || \\r
+                                  ((IOSWITCH) == RI_IOSwitch_GR10_1) || \\r
+                                  ((IOSWITCH) == RI_IOSwitch_GR10_2) || \\r
+                                  ((IOSWITCH) == RI_IOSwitch_GR10_3) || \\r
+                                  ((IOSWITCH) == RI_IOSwitch_GR10_4) || \\r
+                                  ((IOSWITCH) == RI_IOSwitch_GR6_1) || \\r
+                                  ((IOSWITCH) == RI_IOSwitch_GR6_2) || \\r
+                                  ((IOSWITCH) == RI_IOSwitch_GR5_1) || \\r
+                                  ((IOSWITCH) == RI_IOSwitch_GR5_2) || \\r
+                                  ((IOSWITCH) == RI_IOSwitch_GR5_3) || \\r
+                                  ((IOSWITCH) == RI_IOSwitch_GR4_1) || \\r
+                                  ((IOSWITCH) == RI_IOSwitch_GR4_2) || \\r
+                                  ((IOSWITCH) == RI_IOSwitch_GR4_3))\r
+\r
+/** @defgroup RI_Port\r
+  * @{\r
+  */\r
+\r
+#define RI_PortA                 ((uint8_t)0x01)   /*!< GPIOA selected */\r
+#define RI_PortB                 ((uint8_t)0x02)   /*!< GPIOB selected */\r
+#define RI_PortC                 ((uint8_t)0x03)   /*!< GPIOC selected */\r
+#define RI_PortD                 ((uint8_t)0x04)   /*!< GPIOD selected */\r
+#define RI_PortE                 ((uint8_t)0x05)   /*!< GPIOE selected */\r
+\r
+#define IS_RI_PORT(PORT) (((PORT) == RI_PortA) || \\r
+                          ((PORT) == RI_PortB) || \\r
+                          ((PORT) == RI_PortC) || \\r
+                          ((PORT) == RI_PortD) || \\r
+                          ((PORT) == RI_PortE))\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup RI_Pin define \r
+  * @{\r
+  */\r
+#define RI_Pin_0                 ((uint16_t)0x0001)  /*!< Pin 0 selected */\r
+#define RI_Pin_1                 ((uint16_t)0x0002)  /*!< Pin 1 selected */\r
+#define RI_Pin_2                 ((uint16_t)0x0004)  /*!< Pin 2 selected */\r
+#define RI_Pin_3                 ((uint16_t)0x0008)  /*!< Pin 3 selected */\r
+#define RI_Pin_4                 ((uint16_t)0x0010)  /*!< Pin 4 selected */\r
+#define RI_Pin_5                 ((uint16_t)0x0020)  /*!< Pin 5 selected */\r
+#define RI_Pin_6                 ((uint16_t)0x0040)  /*!< Pin 6 selected */\r
+#define RI_Pin_7                 ((uint16_t)0x0080)  /*!< Pin 7 selected */\r
+#define RI_Pin_8                 ((uint16_t)0x0100)  /*!< Pin 8 selected */\r
+#define RI_Pin_9                 ((uint16_t)0x0200)  /*!< Pin 9 selected */\r
+#define RI_Pin_10                ((uint16_t)0x0400)  /*!< Pin 10 selected */\r
+#define RI_Pin_11                ((uint16_t)0x0800)  /*!< Pin 11 selected */\r
+#define RI_Pin_12                ((uint16_t)0x1000)  /*!< Pin 12 selected */\r
+#define RI_Pin_13                ((uint16_t)0x2000)  /*!< Pin 13 selected */\r
+#define RI_Pin_14                ((uint16_t)0x4000)  /*!< Pin 14 selected */\r
+#define RI_Pin_15                ((uint16_t)0x8000)  /*!< Pin 15 selected */\r
+#define RI_Pin_All               ((uint16_t)0xFFFF)  /*!< All pins selected */\r
+\r
+#define IS_RI_PIN(PIN) ((PIN) != (uint16_t)0x00)\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup SYSCFG_Exported_Macros\r
+  * @{\r
+  */ \r
+/**\r
+  * @}\r
+  */ \r
+\r
+/** @defgroup SYSCFG_Exported_Functions\r
+  * @{\r
+  */ \r
+void SYSCFG_DeInit(void);\r
+void SYSCFG_MemoryRemapConfig(uint8_t SYSCFG_MemoryRemap);\r
+void SYSCFG_USBPuCmd(FunctionalState NewState);\r
+void SYSCFG_EXTILineConfig(uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex);\r
+void SYSCFG_RIDeInit(void);\r
+void SYSCFG_RITIMSelect(uint32_t TIM_Select);\r
+void SYSCFG_RITIMInputCaptureConfig(uint32_t RI_InputCapture, uint32_t RI_InputCaptureRouting);\r
+void SYSCFG_RIResistorConfig(uint32_t RI_Resistor, FunctionalState NewState);\r
+void SYSCFG_RISwitchControlModeCmd(FunctionalState NewState);\r
+void SYSCFG_RIIOSwitchConfig(uint32_t RI_IOSwitch, FunctionalState NewState);\r
+void SYSCFG_RIHysteresisConfig(uint8_t RI_Port, uint16_t RI_Pin,\r
+                               FunctionalState NewState);\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /*__STM32L1xx_SYSCFG_H */\r
+/**\r
+  * @}\r
+  */ \r
+\r
+/**\r
+  * @}\r
+  */ \r
+\r
+/**\r
+  * @}\r
+  */ \r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r

diff --git a/Demo/CORTEX_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/inc/stm32l1xx_tim.h b/Demo/CORTEX_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/inc/stm32l1xx_tim.h
new file mode 100644 (file)
index 0000000..7541e09
--- /dev/null
+++ b/Demo/CORTEX_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/inc/stm32l1xx_tim.h
@@ -0,0 +1,901 @@
+/**\r
+  ******************************************************************************\r
+  * @file    stm32l1xx_tim.h\r
+  * @author  MCD Application Team\r
+  * @version V1.0.0RC1\r
+  * @date    07/02/2010\r
+  * @brief   This file contains all the functions prototypes for the TIM firmware \r
+  *          library.\r
+  ******************************************************************************\r
+  * @copy\r
+  *\r
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+  *\r
+  * <h2><center>&copy; COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+  */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32L1xx_TIM_H\r
+#define __STM32L1xx_TIM_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+  * @{\r
+  */\r
+\r
+/** @addtogroup TIM\r
+  * @{\r
+  */ \r
+\r
+/** @defgroup TIM_Exported_Types\r
+  * @{\r
+  */ \r
+\r
+/** \r
+  * @brief  TIM Time Base Init structure definition\r
+  * @note   This sturcture is used with all TIMx except for TIM6 and TIM7.    \r
+  */\r
+\r
+typedef struct\r
+{\r
+  uint16_t TIM_Prescaler;         /*!< Specifies the prescaler value used to divide the TIM clock.\r
+                                       This parameter can be a number between 0x0000 and 0xFFFF */\r
+\r
+  uint16_t TIM_CounterMode;       /*!< Specifies the counter mode.\r
+                                       This parameter can be a value of @ref TIM_Counter_Mode */\r
+\r
+  uint16_t TIM_Period;            /*!< Specifies the period value to be loaded into the active\r
+                                       Auto-Reload Register at the next update event.\r
+                                       This parameter must be a number between 0x0000 and 0xFFFF.  */ \r
+\r
+  uint16_t TIM_ClockDivision;     /*!< Specifies the clock division.\r
+                                      This parameter can be a value of @ref TIM_Clock_Division_CKD */\r
+\r
+} TIM_TimeBaseInitTypeDef;       \r
+\r
+/** \r
+  * @brief  TIM Output Compare Init structure definition  \r
+  */\r
+\r
+typedef struct\r
+{\r
+  uint16_t TIM_OCMode;        /*!< Specifies the TIM mode.\r
+                                   This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */\r
+\r
+  uint16_t TIM_OutputState;   /*!< Specifies the TIM Output Compare state.\r
+                                   This parameter can be a value of @ref TIM_Output_Compare_state */\r
+\r
+  uint16_t TIM_Pulse;         /*!< Specifies the pulse value to be loaded into the Capture Compare Register. \r
+                                   This parameter can be a number between 0x0000 and 0xFFFF */\r
+\r
+  uint16_t TIM_OCPolarity;    /*!< Specifies the output polarity.\r
+                                   This parameter can be a value of @ref TIM_Output_Compare_Polarity */\r
+\r
+} TIM_OCInitTypeDef;\r
+\r
+/** \r
+  * @brief  TIM Input Capture Init structure definition  \r
+  */\r
+\r
+typedef struct\r
+{\r
+\r
+  uint16_t TIM_Channel;      /*!< Specifies the TIM channel.\r
+                                  This parameter can be a value of @ref TIM_Channel */\r
+\r
+  uint16_t TIM_ICPolarity;   /*!< Specifies the active edge of the input signal.\r
+                                  This parameter can be a value of @ref TIM_Input_Capture_Polarity */\r
+\r
+  uint16_t TIM_ICSelection;  /*!< Specifies the input.\r
+                                  This parameter can be a value of @ref TIM_Input_Capture_Selection */\r
+\r
+  uint16_t TIM_ICPrescaler;  /*!< Specifies the Input Capture Prescaler.\r
+                                  This parameter can be a value of @ref TIM_Input_Capture_Prescaler */\r
+\r
+  uint16_t TIM_ICFilter;     /*!< Specifies the input capture filter.\r
+                                  This parameter can be a number between 0x0 and 0xF */\r
+} TIM_ICInitTypeDef;\r
+\r
+/**\r
+  * @}\r
+  */ \r
+\r
+  \r
+/** @defgroup TIM_Exported_constants \r
+  * @{\r
+  */\r
+\r
+#define IS_TIM_ALL_PERIPH(PERIPH) (((PERIPH) == TIM2) || \\r
+                                   ((PERIPH) == TIM3) || \\r
+                                   ((PERIPH) == TIM4) || \\r
+                                   ((PERIPH) == TIM6) || \\r
+                                   ((PERIPH) == TIM7) || \\r
+                                   ((PERIPH) == TIM9) || \\r
+                                   ((PERIPH) == TIM10) || \\r
+                                   ((PERIPH) == TIM11))\r
+\r
+\r
+#define IS_TIM_23491011_PERIPH(PERIPH) (((PERIPH) == TIM2) || \\r
+                                        ((PERIPH) == TIM3) || \\r
+                                        ((PERIPH) == TIM4) || \\r
+                                        ((PERIPH) == TIM9) || \\r
+                                        ((PERIPH) == TIM10) || \\r
+                                        ((PERIPH) == TIM11))\r
+                                        \r
+#define IS_TIM_234_PERIPH(PERIPH) (((PERIPH) == TIM2) || \\r
+                                   ((PERIPH) == TIM3) || \\r
+                                   ((PERIPH) == TIM4))\r
+                                   \r
+#define IS_TIM_2349_PERIPH(PERIPH) (((PERIPH) == TIM2) || \\r
+                                   ((PERIPH) == TIM3) || \\r
+                                   ((PERIPH) == TIM4) ||\\r
+                                   ((PERIPH) == TIM9))\r
+\r
+#define IS_TIM_234679_PERIPH(PERIPH) (((PERIPH) == TIM2) || \\r
+                                      ((PERIPH) == TIM3) || \\r
+                                      ((PERIPH) == TIM4) ||\\r
+                                      ((PERIPH) == TIM6) || \\r
+                                      ((PERIPH) == TIM7) ||\\r
+                                      ((PERIPH) == TIM9))\r
+\r
+#define IS_TIM_23467_PERIPH(PERIPH) (((PERIPH) == TIM2) || \\r
+                                     ((PERIPH) == TIM3) || \\r
+                                     ((PERIPH) == TIM4) ||\\r
+                                     ((PERIPH) == TIM6) || \\r
+                                     ((PERIPH) == TIM7))\r
+\r
+#define IS_TIM_91011_PERIPH(PERIPH) (((PERIPH) == TIM9) || \\r
+                                    ((PERIPH) == TIM10) ||\\r
+                                    ((PERIPH) == TIM11))\r
+\r
+\r
+\r
+/** @defgroup TIM_Output_Compare_and_PWM_modes \r
+  * @{\r
+  */\r
+\r
+#define TIM_OCMode_Timing                  ((uint16_t)0x0000)\r
+#define TIM_OCMode_Active                  ((uint16_t)0x0010)\r
+#define TIM_OCMode_Inactive                ((uint16_t)0x0020)\r
+#define TIM_OCMode_Toggle                  ((uint16_t)0x0030)\r
+#define TIM_OCMode_PWM1                    ((uint16_t)0x0060)\r
+#define TIM_OCMode_PWM2                    ((uint16_t)0x0070)\r
+#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMode_Timing) || \\r
+                              ((MODE) == TIM_OCMode_Active) || \\r
+                              ((MODE) == TIM_OCMode_Inactive) || \\r
+                              ((MODE) == TIM_OCMode_Toggle)|| \\r
+                              ((MODE) == TIM_OCMode_PWM1) || \\r
+                              ((MODE) == TIM_OCMode_PWM2))\r
+#define IS_TIM_OCM(MODE) (((MODE) == TIM_OCMode_Timing) || \\r
+                          ((MODE) == TIM_OCMode_Active) || \\r
+                          ((MODE) == TIM_OCMode_Inactive) || \\r
+                          ((MODE) == TIM_OCMode_Toggle)|| \\r
+                          ((MODE) == TIM_OCMode_PWM1) || \\r
+                          ((MODE) == TIM_OCMode_PWM2) ||       \\r
+                          ((MODE) == TIM_ForcedAction_Active) || \\r
+                          ((MODE) == TIM_ForcedAction_InActive))\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup TIM_One_Pulse_Mode \r
+  * @{\r
+  */\r
+\r
+#define TIM_OPMode_Single                  ((uint16_t)0x0008)\r
+#define TIM_OPMode_Repetitive              ((uint16_t)0x0000)\r
+#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMode_Single) || \\r
+                               ((MODE) == TIM_OPMode_Repetitive))\r
+/**\r
+  * @}\r
+  */ \r
+\r
+/** @defgroup TIM_Channel \r
+  * @{\r
+  */\r
+\r
+#define TIM_Channel_1                      ((uint16_t)0x0000)\r
+#define TIM_Channel_2                      ((uint16_t)0x0004)\r
+#define TIM_Channel_3                      ((uint16_t)0x0008)\r
+#define TIM_Channel_4                      ((uint16_t)0x000C)\r
+\r
+#define IS_TIM_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \\r
+                                 ((CHANNEL) == TIM_Channel_2) || \\r
+                                 ((CHANNEL) == TIM_Channel_3) || \\r
+                                 ((CHANNEL) == TIM_Channel_4))\r
+                                 \r
+#define IS_TIM_PWMI_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \\r
+                                      ((CHANNEL) == TIM_Channel_2))\r
+\r
+/**\r
+  * @}\r
+  */ \r
+\r
+/** @defgroup TIM_Clock_Division_CKD \r
+  * @{\r
+  */\r
+\r
+#define TIM_CKD_DIV1                       ((uint16_t)0x0000)\r
+#define TIM_CKD_DIV2                       ((uint16_t)0x0100)\r
+#define TIM_CKD_DIV4                       ((uint16_t)0x0200)\r
+#define IS_TIM_CKD_DIV(DIV) (((DIV) == TIM_CKD_DIV1) || \\r
+                             ((DIV) == TIM_CKD_DIV2) || \\r
+                             ((DIV) == TIM_CKD_DIV4))\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup TIM_Counter_Mode \r
+  * @{\r
+  */\r
+\r
+#define TIM_CounterMode_Up                 ((uint16_t)0x0000)\r
+#define TIM_CounterMode_Down               ((uint16_t)0x0010)\r
+#define TIM_CounterMode_CenterAligned1     ((uint16_t)0x0020)\r
+#define TIM_CounterMode_CenterAligned2     ((uint16_t)0x0040)\r
+#define TIM_CounterMode_CenterAligned3     ((uint16_t)0x0060)\r
+#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_CounterMode_Up) ||  \\r
+                                   ((MODE) == TIM_CounterMode_Down) || \\r
+                                   ((MODE) == TIM_CounterMode_CenterAligned1) || \\r
+                                   ((MODE) == TIM_CounterMode_CenterAligned2) || \\r
+                                   ((MODE) == TIM_CounterMode_CenterAligned3))\r
+/**\r
+  * @}\r
+  */ \r
+\r
+/** @defgroup TIM_Output_Compare_Polarity \r
+  * @{\r
+  */\r
+\r
+#define TIM_OCPolarity_High                ((uint16_t)0x0000)\r
+#define TIM_OCPolarity_Low                 ((uint16_t)0x0002)\r
+#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPolarity_High) || \\r
+                                      ((POLARITY) == TIM_OCPolarity_Low))\r
+/**\r
+  * @}\r
+  */\r
+\r
+\r
+/** @defgroup TIM_Output_Compare_state\r
+  * @{\r
+  */\r
+\r
+#define TIM_OutputState_Disable            ((uint16_t)0x0000)\r
+#define TIM_OutputState_Enable             ((uint16_t)0x0001)\r
+#define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OutputState_Disable) || \\r
+                                    ((STATE) == TIM_OutputState_Enable))\r
+/**\r
+  * @}\r
+  */ \r
+\r
+\r
+/** @defgroup TIM_Capture_Compare_state \r
+  * @{\r
+  */\r
+\r
+#define TIM_CCx_Enable                      ((uint16_t)0x0001)\r
+#define TIM_CCx_Disable                     ((uint16_t)0x0000)\r
+#define IS_TIM_CCX(CCX) (((CCX) == TIM_CCx_Enable) || \\r
+                         ((CCX) == TIM_CCx_Disable))\r
+/**\r
+  * @}\r
+  */ \r
+\r
+/** @defgroup TIM_Input_Capture_Polarity \r
+  * @{\r
+  */\r
+\r
+#define  TIM_ICPolarity_Rising             ((uint16_t)0x0000)\r
+#define  TIM_ICPolarity_Falling            ((uint16_t)0x0002)\r
+#define  TIM_ICPolarity_BothEdge           ((uint16_t)0x000A)\r
+#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPolarity_Rising) || \\r
+                                      ((POLARITY) == TIM_ICPolarity_Falling)|| \\r
+                                      ((POLARITY) == TIM_ICPolarity_BothEdge))\r
+/**\r
+  * @}\r
+  */ \r
+\r
+/** @defgroup TIM_Input_Capture_Selection \r
+  * @{\r
+  */\r
+\r
+#define TIM_ICSelection_DirectTI           ((uint16_t)0x0001) /*!< TIM Input 1, 2, 3 or 4 is selected to be \r
+                                                                   connected to IC1, IC2, IC3 or IC4, respectively */\r
+#define TIM_ICSelection_IndirectTI         ((uint16_t)0x0002) /*!< TIM Input 1, 2, 3 or 4 is selected to be\r
+                                                                   connected to IC2, IC1, IC4 or IC3, respectively. */\r
+#define TIM_ICSelection_TRC                ((uint16_t)0x0003) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */\r
+#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSelection_DirectTI) || \\r
+                                        ((SELECTION) == TIM_ICSelection_IndirectTI) || \\r
+                                        ((SELECTION) == TIM_ICSelection_TRC))\r
+/**\r
+  * @}\r
+  */ \r
+\r
+/** @defgroup TIM_Input_Capture_Prescaler \r
+  * @{\r
+  */\r
+\r
+#define TIM_ICPSC_DIV1                     ((uint16_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input. */\r
+#define TIM_ICPSC_DIV2                     ((uint16_t)0x0004) /*!< Capture performed once every 2 events. */\r
+#define TIM_ICPSC_DIV4                     ((uint16_t)0x0008) /*!< Capture performed once every 4 events. */\r
+#define TIM_ICPSC_DIV8                     ((uint16_t)0x000C) /*!< Capture performed once every 8 events. */\r
+#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \\r
+                                        ((PRESCALER) == TIM_ICPSC_DIV2) || \\r
+                                        ((PRESCALER) == TIM_ICPSC_DIV4) || \\r
+                                        ((PRESCALER) == TIM_ICPSC_DIV8))\r
+/**\r
+  * @}\r
+  */ \r
+\r
+/** @defgroup TIM_interrupt_sources \r
+  * @{\r
+  */\r
+\r
+#define TIM_IT_Update                      ((uint16_t)0x0001)\r
+#define TIM_IT_CC1                         ((uint16_t)0x0002)\r
+#define TIM_IT_CC2                         ((uint16_t)0x0004)\r
+#define TIM_IT_CC3                         ((uint16_t)0x0008)\r
+#define TIM_IT_CC4                         ((uint16_t)0x0010)\r
+#define TIM_IT_Trigger                     ((uint16_t)0x0040)\r
+#define IS_TIM_IT(IT) ((((IT) & (uint16_t)0xFFA0) == 0x0000) && ((IT) != 0x0000))\r
+\r
+#define IS_TIM_GET_IT(IT) (((IT) == TIM_IT_Update) || \\r
+                           ((IT) == TIM_IT_CC1) || \\r
+                           ((IT) == TIM_IT_CC2) || \\r
+                           ((IT) == TIM_IT_CC3) || \\r
+                           ((IT) == TIM_IT_CC4) || \\r
+                           ((IT) == TIM_IT_Trigger))\r
+/**\r
+  * @}\r
+  */ \r
+\r
+/** @defgroup TIM_DMA_Base_address \r
+  * @{\r
+  */\r
+\r
+#define TIM_DMABase_CR1                    ((uint16_t)0x0000)\r
+#define TIM_DMABase_CR2                    ((uint16_t)0x0001)\r
+#define TIM_DMABase_SMCR                   ((uint16_t)0x0002)\r
+#define TIM_DMABase_DIER                   ((uint16_t)0x0003)\r
+#define TIM_DMABase_SR                     ((uint16_t)0x0004)\r
+#define TIM_DMABase_EGR                    ((uint16_t)0x0005)\r
+#define TIM_DMABase_CCMR1                  ((uint16_t)0x0006)\r
+#define TIM_DMABase_CCMR2                  ((uint16_t)0x0007)\r
+#define TIM_DMABase_CCER                   ((uint16_t)0x0008)\r
+#define TIM_DMABase_CNT                    ((uint16_t)0x0009)\r
+#define TIM_DMABase_PSC                    ((uint16_t)0x000A)\r
+#define TIM_DMABase_ARR                    ((uint16_t)0x000B)\r
+#define TIM_DMABase_RCR                    ((uint16_t)0x000C)\r
+#define TIM_DMABase_CCR1                   ((uint16_t)0x000D)\r
+#define TIM_DMABase_CCR2                   ((uint16_t)0x000E)\r
+#define TIM_DMABase_CCR3                   ((uint16_t)0x000F)\r
+#define TIM_DMABase_CCR4                   ((uint16_t)0x0010)\r
+#define TIM_DMABase_DCR                    ((uint16_t)0x0012)\r
+#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) || \\r
+                               ((BASE) == TIM_DMABase_CR2) || \\r
+                               ((BASE) == TIM_DMABase_SMCR) || \\r
+                               ((BASE) == TIM_DMABase_DIER) || \\r
+                               ((BASE) == TIM_DMABase_SR) || \\r
+                               ((BASE) == TIM_DMABase_EGR) || \\r
+                               ((BASE) == TIM_DMABase_CCMR1) || \\r
+                               ((BASE) == TIM_DMABase_CCMR2) || \\r
+                               ((BASE) == TIM_DMABase_CCER) || \\r
+                               ((BASE) == TIM_DMABase_CNT) || \\r
+                               ((BASE) == TIM_DMABase_PSC) || \\r
+                               ((BASE) == TIM_DMABase_ARR) || \\r
+                               ((BASE) == TIM_DMABase_CCR1) || \\r
+                               ((BASE) == TIM_DMABase_CCR2) || \\r
+                               ((BASE) == TIM_DMABase_CCR3) || \\r
+                               ((BASE) == TIM_DMABase_CCR4) || \\r
+                               ((BASE) == TIM_DMABase_DCR))                     \r
+/**\r
+  * @}\r
+  */ \r
+\r
+/** @defgroup TIM_DMA_Burst_Length \r
+  * @{\r
+  */\r
+\r
+#define TIM_DMABurstLength_1Byte           ((uint16_t)0x0000)\r
+#define TIM_DMABurstLength_2Bytes          ((uint16_t)0x0100)\r
+#define TIM_DMABurstLength_3Bytes          ((uint16_t)0x0200)\r
+#define TIM_DMABurstLength_4Bytes          ((uint16_t)0x0300)\r
+#define TIM_DMABurstLength_5Bytes          ((uint16_t)0x0400)\r
+#define TIM_DMABurstLength_6Bytes          ((uint16_t)0x0500)\r
+#define TIM_DMABurstLength_7Bytes          ((uint16_t)0x0600)\r
+#define TIM_DMABurstLength_8Bytes          ((uint16_t)0x0700)\r
+#define TIM_DMABurstLength_9Bytes          ((uint16_t)0x0800)\r
+#define TIM_DMABurstLength_10Bytes         ((uint16_t)0x0900)\r
+#define TIM_DMABurstLength_11Bytes         ((uint16_t)0x0A00)\r
+#define TIM_DMABurstLength_12Bytes         ((uint16_t)0x0B00)\r
+#define TIM_DMABurstLength_13Bytes         ((uint16_t)0x0C00)\r
+#define TIM_DMABurstLength_14Bytes         ((uint16_t)0x0D00)\r
+#define TIM_DMABurstLength_15Bytes         ((uint16_t)0x0E00)\r
+#define TIM_DMABurstLength_16Bytes         ((uint16_t)0x0F00)\r
+#define TIM_DMABurstLength_17Bytes         ((uint16_t)0x1000)\r
+#define TIM_DMABurstLength_18Bytes         ((uint16_t)0x1100)\r
+#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Byte) || \\r
+                                   ((LENGTH) == TIM_DMABurstLength_2Bytes) || \\r
+                                   ((LENGTH) == TIM_DMABurstLength_3Bytes) || \\r
+                                   ((LENGTH) == TIM_DMABurstLength_4Bytes) || \\r
+                                   ((LENGTH) == TIM_DMABurstLength_5Bytes) || \\r
+                                   ((LENGTH) == TIM_DMABurstLength_6Bytes) || \\r
+                                   ((LENGTH) == TIM_DMABurstLength_7Bytes) || \\r
+                                   ((LENGTH) == TIM_DMABurstLength_8Bytes) || \\r
+                                   ((LENGTH) == TIM_DMABurstLength_9Bytes) || \\r
+                                   ((LENGTH) == TIM_DMABurstLength_10Bytes) || \\r
+                                   ((LENGTH) == TIM_DMABurstLength_11Bytes) || \\r
+                                   ((LENGTH) == TIM_DMABurstLength_12Bytes) || \\r
+                                   ((LENGTH) == TIM_DMABurstLength_13Bytes) || \\r
+                                   ((LENGTH) == TIM_DMABurstLength_14Bytes) || \\r
+                                   ((LENGTH) == TIM_DMABurstLength_15Bytes) || \\r
+                                   ((LENGTH) == TIM_DMABurstLength_16Bytes) || \\r
+                                   ((LENGTH) == TIM_DMABurstLength_17Bytes) || \\r
+                                   ((LENGTH) == TIM_DMABurstLength_18Bytes))\r
+/**\r
+  * @}\r
+  */ \r
+\r
+/** @defgroup TIM_DMA_sources \r
+  * @{\r
+  */\r
+\r
+#define TIM_DMA_Update                     ((uint16_t)0x0100)\r
+#define TIM_DMA_CC1                        ((uint16_t)0x0200)\r
+#define TIM_DMA_CC2                        ((uint16_t)0x0400)\r
+#define TIM_DMA_CC3                        ((uint16_t)0x0800)\r
+#define TIM_DMA_CC4                        ((uint16_t)0x1000)\r
+#define TIM_DMA_Trigger                    ((uint16_t)0x4000)\r
+#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0xA0FF) == 0x0000) && ((SOURCE) != 0x0000))\r
+\r
+/**\r
+  * @}\r
+  */ \r
+\r
+/** @defgroup TIM_External_Trigger_Prescaler \r
+  * @{\r
+  */\r
+\r
+#define TIM_ExtTRGPSC_OFF                  ((uint16_t)0x0000)\r
+#define TIM_ExtTRGPSC_DIV2                 ((uint16_t)0x1000)\r
+#define TIM_ExtTRGPSC_DIV4                 ((uint16_t)0x2000)\r
+#define TIM_ExtTRGPSC_DIV8                 ((uint16_t)0x3000)\r
+#define IS_TIM_EXT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ExtTRGPSC_OFF) || \\r
+                                         ((PRESCALER) == TIM_ExtTRGPSC_DIV2) || \\r
+                                         ((PRESCALER) == TIM_ExtTRGPSC_DIV4) || \\r
+                                         ((PRESCALER) == TIM_ExtTRGPSC_DIV8))\r
+/**\r
+  * @}\r
+  */ \r
+\r
+/** @defgroup TIM_Internal_Trigger_Selection \r
+  * @{\r
+  */\r
+\r
+#define TIM_TS_ITR0                        ((uint16_t)0x0000)\r
+#define TIM_TS_ITR1                        ((uint16_t)0x0010)\r
+#define TIM_TS_ITR2                        ((uint16_t)0x0020)\r
+#define TIM_TS_ITR3                        ((uint16_t)0x0030)\r
+#define TIM_TS_TI1F_ED                     ((uint16_t)0x0040)\r
+#define TIM_TS_TI1FP1                      ((uint16_t)0x0050)\r
+#define TIM_TS_TI2FP2                      ((uint16_t)0x0060)\r
+#define TIM_TS_ETRF                        ((uint16_t)0x0070)\r
+#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \\r
+                                             ((SELECTION) == TIM_TS_ITR1) || \\r
+                                             ((SELECTION) == TIM_TS_ITR2) || \\r
+                                             ((SELECTION) == TIM_TS_ITR3) || \\r
+                                             ((SELECTION) == TIM_TS_TI1F_ED) || \\r
+                                             ((SELECTION) == TIM_TS_TI1FP1) || \\r
+                                             ((SELECTION) == TIM_TS_TI2FP2) || \\r
+                                             ((SELECTION) == TIM_TS_ETRF))\r
+#define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \\r
+                                                      ((SELECTION) == TIM_TS_ITR1) || \\r
+                                                      ((SELECTION) == TIM_TS_ITR2) || \\r
+                                                      ((SELECTION) == TIM_TS_ITR3))\r
+/**\r
+  * @}\r
+  */ \r
+\r
+/** @defgroup TIM_TIx_External_Clock_Source \r
+  * @{\r
+  */\r
+\r
+#define TIM_TIxExternalCLK1Source_TI1      ((uint16_t)0x0050)\r
+#define TIM_TIxExternalCLK1Source_TI2      ((uint16_t)0x0060)\r
+#define TIM_TIxExternalCLK1Source_TI1ED    ((uint16_t)0x0040)\r
+\r
+/**\r
+  * @}\r
+  */ \r
+\r
+/** @defgroup TIM_External_Trigger_Polarity \r
+  * @{\r
+  */ \r
+#define TIM_ExtTRGPolarity_Inverted        ((uint16_t)0x8000)\r
+#define TIM_ExtTRGPolarity_NonInverted     ((uint16_t)0x0000)\r
+#define IS_TIM_EXT_POLARITY(POLARITY) (((POLARITY) == TIM_ExtTRGPolarity_Inverted) || \\r
+                                       ((POLARITY) == TIM_ExtTRGPolarity_NonInverted))\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup TIM_Prescaler_Reload_Mode \r
+  * @{\r
+  */\r
+\r
+#define TIM_PSCReloadMode_Update           ((uint16_t)0x0000)\r
+#define TIM_PSCReloadMode_Immediate        ((uint16_t)0x0001)\r
+#define IS_TIM_PRESCALER_RELOAD(RELOAD) (((RELOAD) == TIM_PSCReloadMode_Update) || \\r
+                                         ((RELOAD) == TIM_PSCReloadMode_Immediate))\r
+/**\r
+  * @}\r
+  */ \r
+\r
+/** @defgroup TIM_Forced_Action \r
+  * @{\r
+  */\r
+\r
+#define TIM_ForcedAction_Active            ((uint16_t)0x0050)\r
+#define TIM_ForcedAction_InActive          ((uint16_t)0x0040)\r
+#define IS_TIM_FORCED_ACTION(ACTION) (((ACTION) == TIM_ForcedAction_Active) || \\r
+                                      ((ACTION) == TIM_ForcedAction_InActive))\r
+/**\r
+  * @}\r
+  */ \r
+\r
+/** @defgroup TIM_Encoder_Mode \r
+  * @{\r
+  */\r
+\r
+#define TIM_EncoderMode_TI1                ((uint16_t)0x0001)\r
+#define TIM_EncoderMode_TI2                ((uint16_t)0x0002)\r
+#define TIM_EncoderMode_TI12               ((uint16_t)0x0003)\r
+#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_EncoderMode_TI1) || \\r
+                                   ((MODE) == TIM_EncoderMode_TI2) || \\r
+                                   ((MODE) == TIM_EncoderMode_TI12))\r
+/**\r
+  * @}\r
+  */ \r
+\r
+\r
+/** @defgroup TIM_Event_Source \r
+  * @{\r
+  */\r
+\r
+#define TIM_EventSource_Update             ((uint16_t)0x0001)\r
+#define TIM_EventSource_CC1                ((uint16_t)0x0002)\r
+#define TIM_EventSource_CC2                ((uint16_t)0x0004)\r
+#define TIM_EventSource_CC3                ((uint16_t)0x0008)\r
+#define TIM_EventSource_CC4                ((uint16_t)0x0010)\r
+#define TIM_EventSource_Trigger            ((uint16_t)0x0040)\r
+#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0xFFA0) == 0x0000) && ((SOURCE) != 0x0000))                                          \r
+   \r
+/**\r
+  * @}\r
+  */ \r
+\r
+/** @defgroup TIM_Update_Source \r
+  * @{\r
+  */\r
+\r
+#define TIM_UpdateSource_Global            ((uint16_t)0x0000) /*!< Source of update is the counter overflow/underflow\r
+                                                                   or the setting of UG bit, or an update generation\r
+                                                                   through the slave mode controller. */\r
+#define TIM_UpdateSource_Regular           ((uint16_t)0x0001) /*!< Source of update is counter overflow/underflow. */\r
+#define IS_TIM_UPDATE_SOURCE(SOURCE) (((SOURCE) == TIM_UpdateSource_Global) || \\r
+                                      ((SOURCE) == TIM_UpdateSource_Regular))\r
+/**\r
+  * @}\r
+  */ \r
+\r
+/** @defgroup TIM_Ouput_Compare_Preload_State \r
+  * @{\r
+  */\r
+\r
+#define TIM_OCPreload_Enable               ((uint16_t)0x0008)\r
+#define TIM_OCPreload_Disable              ((uint16_t)0x0000)\r
+#define IS_TIM_OCPRELOAD_STATE(STATE) (((STATE) == TIM_OCPreload_Enable) || \\r
+                                       ((STATE) == TIM_OCPreload_Disable))\r
+/**\r
+  * @}\r
+  */ \r
+\r
+/** @defgroup TIM_Ouput_Compare_Fast_State \r
+  * @{\r
+  */\r
+\r
+#define TIM_OCFast_Enable                  ((uint16_t)0x0004)\r
+#define TIM_OCFast_Disable                 ((uint16_t)0x0000)\r
+#define IS_TIM_OCFAST_STATE(STATE) (((STATE) == TIM_OCFast_Enable) || \\r
+                                    ((STATE) == TIM_OCFast_Disable))\r
+                                     \r
+/**\r
+  * @}\r
+  */ \r
+\r
+/** @defgroup TIM_Ouput_Compare_Clear_State \r
+  * @{\r
+  */\r
+\r
+#define TIM_OCClear_Enable                 ((uint16_t)0x0080)\r
+#define TIM_OCClear_Disable                ((uint16_t)0x0000)\r
+#define IS_TIM_OCCLEAR_STATE(STATE) (((STATE) == TIM_OCClear_Enable) || \\r
+                                     ((STATE) == TIM_OCClear_Disable))\r
+/**\r
+  * @}\r
+  */ \r
+\r
+/** @defgroup TIM_Trigger_Output_Source \r
+  * @{\r
+  */\r
+\r
+#define TIM_TRGOSource_Reset               ((uint16_t)0x0000)\r
+#define TIM_TRGOSource_Enable              ((uint16_t)0x0010)\r
+#define TIM_TRGOSource_Update              ((uint16_t)0x0020)\r
+#define TIM_TRGOSource_OC1                 ((uint16_t)0x0030)\r
+#define TIM_TRGOSource_OC1Ref              ((uint16_t)0x0040)\r
+#define TIM_TRGOSource_OC2Ref              ((uint16_t)0x0050)\r
+#define TIM_TRGOSource_OC3Ref              ((uint16_t)0x0060)\r
+#define TIM_TRGOSource_OC4Ref              ((uint16_t)0x0070)\r
+#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGOSource_Reset) || \\r
+                                    ((SOURCE) == TIM_TRGOSource_Enable) || \\r
+                                    ((SOURCE) == TIM_TRGOSource_Update) || \\r
+                                    ((SOURCE) == TIM_TRGOSource_OC1) || \\r
+                                    ((SOURCE) == TIM_TRGOSource_OC1Ref) || \\r
+                                    ((SOURCE) == TIM_TRGOSource_OC2Ref) || \\r
+                                    ((SOURCE) == TIM_TRGOSource_OC3Ref) || \\r
+                                    ((SOURCE) == TIM_TRGOSource_OC4Ref))\r
+/**\r
+  * @}\r
+  */ \r
+\r
+/** @defgroup TIM_Slave_Mode \r
+  * @{\r
+  */\r
+\r
+#define TIM_SlaveMode_Reset                ((uint16_t)0x0004)\r
+#define TIM_SlaveMode_Gated                ((uint16_t)0x0005)\r
+#define TIM_SlaveMode_Trigger              ((uint16_t)0x0006)\r
+#define TIM_SlaveMode_External1            ((uint16_t)0x0007)\r
+#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SlaveMode_Reset) || \\r
+                                 ((MODE) == TIM_SlaveMode_Gated) || \\r
+                                 ((MODE) == TIM_SlaveMode_Trigger) || \\r
+                                 ((MODE) == TIM_SlaveMode_External1))\r
+/**\r
+  * @}\r
+  */ \r
+\r
+/** @defgroup TIM_Master_Slave_Mode \r
+  * @{\r
+  */\r
+\r
+#define TIM_MasterSlaveMode_Enable         ((uint16_t)0x0080)\r
+#define TIM_MasterSlaveMode_Disable        ((uint16_t)0x0000)\r
+#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MasterSlaveMode_Enable) || \\r
+                                 ((STATE) == TIM_MasterSlaveMode_Disable))\r
+/**\r
+  * @}\r
+  */ \r
+  \r
+/** @defgroup TIM_Flags \r
+  * @{\r
+  */\r
+\r
+#define TIM_FLAG_Update                    ((uint16_t)0x0001)\r
+#define TIM_FLAG_CC1                       ((uint16_t)0x0002)\r
+#define TIM_FLAG_CC2                       ((uint16_t)0x0004)\r
+#define TIM_FLAG_CC3                       ((uint16_t)0x0008)\r
+#define TIM_FLAG_CC4                       ((uint16_t)0x0010)\r
+#define TIM_FLAG_Trigger                   ((uint16_t)0x0040)\r
+#define TIM_FLAG_CC1OF                     ((uint16_t)0x0200)\r
+#define TIM_FLAG_CC2OF                     ((uint16_t)0x0400)\r
+#define TIM_FLAG_CC3OF                     ((uint16_t)0x0800)\r
+#define TIM_FLAG_CC4OF                     ((uint16_t)0x1000)\r
+#define IS_TIM_GET_FLAG(FLAG) (((FLAG) == TIM_FLAG_Update) || \\r
+                               ((FLAG) == TIM_FLAG_CC1) || \\r
+                               ((FLAG) == TIM_FLAG_CC2) || \\r
+                               ((FLAG) == TIM_FLAG_CC3) || \\r
+                               ((FLAG) == TIM_FLAG_CC4) || \\r
+                               ((FLAG) == TIM_FLAG_Trigger) || \\r
+                               ((FLAG) == TIM_FLAG_CC1OF) || \\r
+                               ((FLAG) == TIM_FLAG_CC2OF) || \\r
+                               ((FLAG) == TIM_FLAG_CC3OF) || \\r
+                               ((FLAG) == TIM_FLAG_CC4OF))\r
+#define IS_TIM_CLEAR_FLAG(TIM_FLAG) ((((TIM_FLAG) & (uint16_t)0xE1A0) == 0x0000) && ((TIM_FLAG) != 0x0000)) \r
+\r
+/**\r
+  * @}\r
+  */ \r
+\r
+/** @defgroup TIM_Input_Capture_Filer_Value \r
+  * @{\r
+  */\r
+\r
+#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF) \r
+/**\r
+  * @}\r
+  */ \r
+\r
+/** @defgroup TIM_External_Trigger_Filter \r
+  * @{\r
+  */\r
+\r
+#define IS_TIM_EXT_FILTER(EXTFILTER) ((EXTFILTER) <= 0xF)\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup TIM_OCReferenceClear \r
+  * @{\r
+  */\r
+#define TIM_OCReferenceClear_ETRF          ((uint16_t)0x0008)\r
+#define TIM_OCReferenceClear_OCREFCLR      ((uint16_t)0x0000)\r
+#define TIM_OCREFERENCECECLEAR_SOURCE(SOURCE) (((SOURCE) == TIM_OCReferenceClear_ETRF) || \\r
+                                              ((SOURCE) == TIM_OCReferenceClear_OCREFCLR)) \r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup TIM_Remap \r
+  * @{\r
+  */\r
+\r
+#define TIM9_GPIO                          ((uint16_t)0x0000)\r
+#define TIM9_LSE                           ((uint16_t)0x0001)\r
+\r
+#define TIM10_GPIO                         ((uint16_t)0x0000)\r
+#define TIM10_LSI                          ((uint16_t)0x0001)\r
+#define TIM10_LSE                          ((uint16_t)0x0002)\r
+#define TIM10_RTC                          ((uint16_t)0x0003)\r
+\r
+#define TIM11_GPIO                         ((uint16_t)0x0000)\r
+#define TIM11_MSI                          ((uint16_t)0x0001)\r
+#define TIM11_HSE_RTC                      ((uint16_t)0x0002)\r
+\r
+#define IS_TIM_REMAP(TIM_REMAP)         (((TIM_REMAP) == TIM9_GPIO)||\\r
+                                  ((TIM_REMAP) == TIM9_LSE)||\\r
+                                  ((TIM_REMAP) == TIM10_GPIO)||\\r
+                                  ((TIM_REMAP) == TIM10_LSI)||\\r
+                                  ((TIM_REMAP) == TIM10_LSE)||\\r
+                                  ((TIM_REMAP) == TIM10_RTC)||\\r
+                                  ((TIM_REMAP) == TIM11_GPIO)||\\r
+                                  ((TIM_REMAP) == TIM11_MSI)||\\r
+                                  ((TIM_REMAP) == TIM11_HSE_RTC)) \r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+  \r
+/** @defgroup TIM_Exported_Macros\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */ \r
+\r
+/** @defgroup TIM_Exported_Functions\r
+  * @{\r
+  */\r
+\r
+void TIM_DeInit(TIM_TypeDef* TIMx);\r
+void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);\r
+void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);\r
+void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);\r
+void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);\r
+void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);\r
+void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct);\r
+void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct);\r
+void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);\r
+void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct);\r
+void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct);\r
+void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState);\r
+void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState);\r
+void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource);\r
+void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength);\r
+void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState);\r
+void TIM_InternalClockConfig(TIM_TypeDef* TIMx);\r
+void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);\r
+void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource,\r
+                                uint16_t TIM_ICPolarity, uint16_t ICFilter);\r
+void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,\r
+                             uint16_t ExtTRGFilter);\r
+void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, \r
+                             uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter);\r
+void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,\r
+                   uint16_t ExtTRGFilter);\r
+void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode);\r
+void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode);\r
+void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);\r
+void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode,\r
+                                uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity);\r
+void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);\r
+void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);\r
+void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);\r
+void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);\r
+void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState);\r
+void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState);\r
+void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState);\r
+void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState);\r
+void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);\r
+void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);\r
+void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);\r
+void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);\r
+void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);\r
+void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);\r
+void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);\r
+void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);\r
+void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);\r
+void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);\r
+void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);\r
+void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);\r
+void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);\r
+void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);\r
+void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);\r
+void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);\r
+void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx);\r
+void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode);\r
+void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState);\r
+void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource);\r
+void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState);\r
+void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode);\r
+void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource);\r
+void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode);\r
+void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode);\r
+void TIM_SetCounter(TIM_TypeDef* TIMx, uint32_t Counter);\r
+void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint32_t Autoreload);\r
+void TIM_SetCompare1(TIM_TypeDef* TIMx, uint32_t Compare1);\r
+void TIM_SetCompare2(TIM_TypeDef* TIMx, uint32_t Compare2);\r
+void TIM_SetCompare3(TIM_TypeDef* TIMx, uint32_t Compare3);\r
+void TIM_SetCompare4(TIM_TypeDef* TIMx, uint32_t Compare4);\r
+void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);\r
+void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);\r
+void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);\r
+void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);\r
+void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD);\r
+uint32_t TIM_GetCapture1(TIM_TypeDef* TIMx);\r
+uint32_t TIM_GetCapture2(TIM_TypeDef* TIMx);\r
+uint32_t TIM_GetCapture3(TIM_TypeDef* TIMx);\r
+uint32_t TIM_GetCapture4(TIM_TypeDef* TIMx);\r
+uint32_t TIM_GetCounter(TIM_TypeDef* TIMx);\r
+uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx);\r
+void TIM_SelectOCREFClear(TIM_TypeDef* TIMx, uint16_t TIM_OCReferenceClear);\r
+void TIM_RemapConfig(TIM_TypeDef* TIMx, uint16_t TIM_Remap);\r
+FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG);\r
+void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG);\r
+ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT);\r
+void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+#endif /*__STM32L1xx_TIM_H */\r
+/**\r
+  * @}\r
+  */ \r
+\r
+/**\r
+  * @}\r
+  */ \r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r

diff --git a/Demo/CORTEX_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/inc/stm32l1xx_usart.h b/Demo/CORTEX_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/inc/stm32l1xx_usart.h
new file mode 100644 (file)
index 0000000..c6a1416
--- /dev/null
+++ b/Demo/CORTEX_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/inc/stm32l1xx_usart.h
@@ -0,0 +1,399 @@
+/**\r
+  ******************************************************************************\r
+  * @file    stm32l1xx_usart.h\r
+  * @author  MCD Application Team\r
+  * @version V1.0.0RC1\r
+  * @date    07/02/2010\r
+  * @brief   This file contains all the functions prototypes for the USART \r
+  *          firmware library.\r
+  ******************************************************************************\r
+  * @copy\r
+  *\r
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+  *\r
+  * <h2><center>&copy; COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+  */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32L1xx_USART_H\r
+#define __STM32L1xx_USART_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+  * @{\r
+  */\r
+\r
+/** @addtogroup USART\r
+  * @{\r
+  */ \r
+\r
+/** @defgroup USART_Exported_Types\r
+  * @{\r
+  */ \r
+\r
+/** \r
+  * @brief  USART Init Structure definition  \r
+  */ \r
+  \r
+typedef struct\r
+{\r
+  uint32_t USART_BaudRate;            /*!< This member configures the USART communication baud rate.\r
+                                           The baud rate is computed using the following formula:\r
+                                            - IntegerDivider = ((PCLKx) / (16 * (USART_InitStruct->USART_BaudRate)))\r
+                                            - FractionalDivider = ((IntegerDivider - ((u32) IntegerDivider)) * 16) + 0.5 */\r
+\r
+  uint16_t USART_WordLength;          /*!< Specifies the number of data bits transmitted or received in a frame.\r
+                                           This parameter can be a value of @ref USART_Word_Length */\r
+\r
+  uint16_t USART_StopBits;            /*!< Specifies the number of stop bits transmitted.\r
+                                           This parameter can be a value of @ref USART_Stop_Bits */\r
+\r
+  uint16_t USART_Parity;              /*!< Specifies the parity mode.\r
+                                           This parameter can be a value of @ref USART_Parity\r
+                                           @note When parity is enabled, the computed parity is inserted\r
+                                                 at the MSB position of the transmitted data (9th bit when\r
+                                                 the word length is set to 9 data bits; 8th bit when the\r
+                                                 word length is set to 8 data bits). */\r
+ \r
+  uint16_t USART_Mode;                /*!< Specifies wether the Receive or Transmit mode is enabled or disabled.\r
+                                           This parameter can be a value of @ref USART_Mode */\r
+\r
+  uint16_t USART_HardwareFlowControl; /*!< Specifies wether the hardware flow control mode is enabled\r
+                                           or disabled.\r
+                                           This parameter can be a value of @ref USART_Hardware_Flow_Control */\r
+} USART_InitTypeDef;\r
+\r
+/** \r
+  * @brief  USART Clock Init Structure definition  \r
+  */ \r
+  \r
+typedef struct\r
+{\r
+\r
+  uint16_t USART_Clock;   /*!< Specifies whether the USART clock is enabled or disabled.\r
+                               This parameter can be a value of @ref USART_Clock */\r
+\r
+  uint16_t USART_CPOL;    /*!< Specifies the steady state value of the serial clock.\r
+                               This parameter can be a value of @ref USART_Clock_Polarity */\r
+\r
+  uint16_t USART_CPHA;    /*!< Specifies the clock transition on which the bit capture is made.\r
+                               This parameter can be a value of @ref USART_Clock_Phase */\r
+\r
+  uint16_t USART_LastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted\r
+                               data bit (MSB) has to be output on the SCLK pin in synchronous mode.\r
+                               This parameter can be a value of @ref USART_Last_Bit */\r
+} USART_ClockInitTypeDef;\r
+\r
+/**\r
+  * @}\r
+  */ \r
+\r
+/** @defgroup USART_Exported_Constants\r
+  * @{\r
+  */ \r
+  \r
+#define IS_USART_ALL_PERIPH(PERIPH) (((PERIPH) == USART1) || \\r
+                                     ((PERIPH) == USART2) || \\r
+                                     ((PERIPH) == USART3))\r
+\r
+/** @defgroup USART_Word_Length \r
+  * @{\r
+  */ \r
+  \r
+#define USART_WordLength_8b                  ((uint16_t)0x0000)\r
+#define USART_WordLength_9b                  ((uint16_t)0x1000)\r
+                                    \r
+#define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WordLength_8b) || \\r
+                                      ((LENGTH) == USART_WordLength_9b))\r
+/**\r
+  * @}\r
+  */ \r
+\r
+/** @defgroup USART_Stop_Bits \r
+  * @{\r
+  */ \r
+  \r
+#define USART_StopBits_1                     ((uint16_t)0x0000)\r
+#define USART_StopBits_0_5                   ((uint16_t)0x1000)\r
+#define USART_StopBits_2                     ((uint16_t)0x2000)\r
+#define USART_StopBits_1_5                   ((uint16_t)0x3000)\r
+#define IS_USART_STOPBITS(STOPBITS) (((STOPBITS) == USART_StopBits_1) || \\r
+                                     ((STOPBITS) == USART_StopBits_0_5) || \\r
+                                     ((STOPBITS) == USART_StopBits_2) || \\r
+                                     ((STOPBITS) == USART_StopBits_1_5))\r
+/**\r
+  * @}\r
+  */ \r
+\r
+/** @defgroup USART_Parity \r
+  * @{\r
+  */ \r
+  \r
+#define USART_Parity_No                      ((uint16_t)0x0000)\r
+#define USART_Parity_Even                    ((uint16_t)0x0400)\r
+#define USART_Parity_Odd                     ((uint16_t)0x0600) \r
+#define IS_USART_PARITY(PARITY) (((PARITY) == USART_Parity_No) || \\r
+                                 ((PARITY) == USART_Parity_Even) || \\r
+                                 ((PARITY) == USART_Parity_Odd))\r
+/**\r
+  * @}\r
+  */ \r
+\r
+/** @defgroup USART_Mode \r
+  * @{\r
+  */ \r
+  \r
+#define USART_Mode_Rx                        ((uint16_t)0x0004)\r
+#define USART_Mode_Tx                        ((uint16_t)0x0008)\r
+#define IS_USART_MODE(MODE) ((((MODE) & (uint16_t)0xFFF3) == 0x00) && ((MODE) != (uint16_t)0x00))\r
+/**\r
+  * @}\r
+  */ \r
+\r
+/** @defgroup USART_Hardware_Flow_Control \r
+  * @{\r
+  */ \r
+#define USART_HardwareFlowControl_None       ((uint16_t)0x0000)\r
+#define USART_HardwareFlowControl_RTS        ((uint16_t)0x0100)\r
+#define USART_HardwareFlowControl_CTS        ((uint16_t)0x0200)\r
+#define USART_HardwareFlowControl_RTS_CTS    ((uint16_t)0x0300)\r
+#define IS_USART_HARDWARE_FLOW_CONTROL(CONTROL)\\r
+                              (((CONTROL) == USART_HardwareFlowControl_None) || \\r
+                               ((CONTROL) == USART_HardwareFlowControl_RTS) || \\r
+                               ((CONTROL) == USART_HardwareFlowControl_CTS) || \\r
+                               ((CONTROL) == USART_HardwareFlowControl_RTS_CTS))\r
+/**\r
+  * @}\r
+  */ \r
+\r
+/** @defgroup USART_Clock \r
+  * @{\r
+  */ \r
+#define USART_Clock_Disable                  ((uint16_t)0x0000)\r
+#define USART_Clock_Enable                   ((uint16_t)0x0800)\r
+#define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_Clock_Disable) || \\r
+                               ((CLOCK) == USART_Clock_Enable))\r
+/**\r
+  * @}\r
+  */ \r
+\r
+/** @defgroup USART_Clock_Polarity \r
+  * @{\r
+  */\r
+  \r
+#define USART_CPOL_Low                       ((uint16_t)0x0000)\r
+#define USART_CPOL_High                      ((uint16_t)0x0400)\r
+#define IS_USART_CPOL(CPOL) (((CPOL) == USART_CPOL_Low) || ((CPOL) == USART_CPOL_High))\r
+\r
+/**\r
+  * @}\r
+  */ \r
+\r
+/** @defgroup USART_Clock_Phase\r
+  * @{\r
+  */\r
+\r
+#define USART_CPHA_1Edge                     ((uint16_t)0x0000)\r
+#define USART_CPHA_2Edge                     ((uint16_t)0x0200)\r
+#define IS_USART_CPHA(CPHA) (((CPHA) == USART_CPHA_1Edge) || ((CPHA) == USART_CPHA_2Edge))\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup USART_Last_Bit\r
+  * @{\r
+  */\r
+\r
+#define USART_LastBit_Disable                ((uint16_t)0x0000)\r
+#define USART_LastBit_Enable                 ((uint16_t)0x0100)\r
+#define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_LastBit_Disable) || \\r
+                                   ((LASTBIT) == USART_LastBit_Enable))\r
+/**\r
+  * @}\r
+  */ \r
+\r
+/** @defgroup USART_Interrupt_definition \r
+  * @{\r
+  */\r
+  \r
+#define USART_IT_PE                          ((uint16_t)0x0028)\r
+#define USART_IT_TXE                         ((uint16_t)0x0727)\r
+#define USART_IT_TC                          ((uint16_t)0x0626)\r
+#define USART_IT_RXNE                        ((uint16_t)0x0525)\r
+#define USART_IT_IDLE                        ((uint16_t)0x0424)\r
+#define USART_IT_LBD                         ((uint16_t)0x0846)\r
+#define USART_IT_CTS                         ((uint16_t)0x096A)\r
+#define USART_IT_ERR                         ((uint16_t)0x0060)\r
+#define USART_IT_ORE                         ((uint16_t)0x0360)\r
+#define USART_IT_NE                          ((uint16_t)0x0260)\r
+#define USART_IT_FE                          ((uint16_t)0x0160)\r
+#define IS_USART_CONFIG_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \\r
+                                ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \\r
+                                ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \\r
+                                ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ERR))\r
+#define IS_USART_GET_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \\r
+                             ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \\r
+                             ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \\r
+                             ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ORE) || \\r
+                             ((IT) == USART_IT_NE) || ((IT) == USART_IT_FE))\r
+#define IS_USART_CLEAR_IT(IT) (((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \\r
+                               ((IT) == USART_IT_LBD) || ((IT) == USART_IT_CTS))\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup USART_DMA_Requests \r
+  * @{\r
+  */\r
+\r
+#define USART_DMAReq_Tx                      ((uint16_t)0x0080)\r
+#define USART_DMAReq_Rx                      ((uint16_t)0x0040)\r
+#define IS_USART_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFF3F) == 0x00) && ((DMAREQ) != (uint16_t)0x00))\r
+\r
+/**\r
+  * @}\r
+  */ \r
+\r
+/** @defgroup USART_WakeUp_methods\r
+  * @{\r
+  */\r
+\r
+#define USART_WakeUp_IdleLine                ((uint16_t)0x0000)\r
+#define USART_WakeUp_AddressMark             ((uint16_t)0x0800)\r
+#define IS_USART_WAKEUP(WAKEUP) (((WAKEUP) == USART_WakeUp_IdleLine) || \\r
+                                 ((WAKEUP) == USART_WakeUp_AddressMark))\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup USART_LIN_Break_Detection_Length \r
+  * @{\r
+  */\r
+  \r
+#define USART_LINBreakDetectLength_10b      ((uint16_t)0x0000)\r
+#define USART_LINBreakDetectLength_11b      ((uint16_t)0x0020)\r
+#define IS_USART_LIN_BREAK_DETECT_LENGTH(LENGTH) \\r
+                               (((LENGTH) == USART_LINBreakDetectLength_10b) || \\r
+                                ((LENGTH) == USART_LINBreakDetectLength_11b))\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup USART_IrDA_Low_Power \r
+  * @{\r
+  */\r
+\r
+#define USART_IrDAMode_LowPower              ((uint16_t)0x0004)\r
+#define USART_IrDAMode_Normal                ((uint16_t)0x0000)\r
+#define IS_USART_IRDA_MODE(MODE) (((MODE) == USART_IrDAMode_LowPower) || \\r
+                                  ((MODE) == USART_IrDAMode_Normal))\r
+/**\r
+  * @}\r
+  */ \r
+\r
+/** @defgroup USART_Flags \r
+  * @{\r
+  */\r
+\r
+#define USART_FLAG_CTS                       ((uint16_t)0x0200)\r
+#define USART_FLAG_LBD                       ((uint16_t)0x0100)\r
+#define USART_FLAG_TXE                       ((uint16_t)0x0080)\r
+#define USART_FLAG_TC                        ((uint16_t)0x0040)\r
+#define USART_FLAG_RXNE                      ((uint16_t)0x0020)\r
+#define USART_FLAG_IDLE                      ((uint16_t)0x0010)\r
+#define USART_FLAG_ORE                       ((uint16_t)0x0008)\r
+#define USART_FLAG_NE                        ((uint16_t)0x0004)\r
+#define USART_FLAG_FE                        ((uint16_t)0x0002)\r
+#define USART_FLAG_PE                        ((uint16_t)0x0001)\r
+#define IS_USART_FLAG(FLAG) (((FLAG) == USART_FLAG_PE) || ((FLAG) == USART_FLAG_TXE) || \\r
+                             ((FLAG) == USART_FLAG_TC) || ((FLAG) == USART_FLAG_RXNE) || \\r
+                             ((FLAG) == USART_FLAG_IDLE) || ((FLAG) == USART_FLAG_LBD) || \\r
+                             ((FLAG) == USART_FLAG_CTS) || ((FLAG) == USART_FLAG_ORE) || \\r
+                             ((FLAG) == USART_FLAG_NE) || ((FLAG) == USART_FLAG_FE))\r
+                              \r
+#define IS_USART_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFC9F) == 0x00) && ((FLAG) != (uint16_t)0x00))\r
+\r
+#define IS_USART_BAUDRATE(BAUDRATE) (((BAUDRATE) > 0) && ((BAUDRATE) < 0x003D0901))\r
+#define IS_USART_ADDRESS(ADDRESS) ((ADDRESS) <= 0xF)\r
+#define IS_USART_DATA(DATA) ((DATA) <= 0x1FF)\r
+\r
+/**\r
+  * @}\r
+  */ \r
+\r
+/**\r
+  * @}\r
+  */ \r
+\r
+/** @defgroup USART_Exported_Macros\r
+  * @{\r
+  */ \r
+\r
+/**\r
+  * @}\r
+  */ \r
+\r
+/** @defgroup USART_Exported_Functions\r
+  * @{\r
+  */\r
+\r
+void USART_DeInit(USART_TypeDef* USARTx);\r
+void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct);\r
+void USART_StructInit(USART_InitTypeDef* USART_InitStruct);\r
+void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct);\r
+void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct);\r
+void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState);\r
+void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState);\r
+void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState);\r
+void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address);\r
+void USART_WakeUpConfig(USART_TypeDef* USARTx, uint16_t USART_WakeUp);\r
+void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState);\r
+void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint16_t USART_LINBreakDetectLength);\r
+void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState);\r
+void USART_SendData(USART_TypeDef* USARTx, uint16_t Data);\r
+uint16_t USART_ReceiveData(USART_TypeDef* USARTx);\r
+void USART_SendBreak(USART_TypeDef* USARTx);\r
+void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime);\r
+void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler);\r
+void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState);\r
+void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState);\r
+void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState);\r
+void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState);\r
+void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState);\r
+void USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode);\r
+void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState);\r
+FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG);\r
+void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG);\r
+ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT);\r
+void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32L1xx_USART_H */\r
+/**\r
+  * @}\r
+  */ \r
+\r
+/**\r
+  * @}\r
+  */ \r
+\r
+/**\r
+  * @}\r
+  */ \r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r

diff --git a/Demo/CORTEX_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/src/misc.c b/Demo/CORTEX_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/src/misc.c
new file mode 100644 (file)
index 0000000..e7648ab
--- /dev/null
+++ b/Demo/CORTEX_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/src/misc.c
@@ -0,0 +1,223 @@
+/**\r
+  ******************************************************************************\r
+  * @file    misc.c\r
+  * @author  MCD Application Team\r
+  * @version V1.0.0RC1\r
+  * @date    07/02/2010\r
+  * @brief   This file provides all the miscellaneous firmware functions (add-on\r
+  *          to CMSIS functions).\r
+  ******************************************************************************\r
+  * @copy\r
+  *\r
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+  *\r
+  * <h2><center>&copy; COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+  */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "misc.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+  * @{\r
+  */\r
+\r
+/** @defgroup MISC \r
+  * @brief MISC driver modules\r
+  * @{\r
+  */\r
+\r
+/** @defgroup MISC_Private_TypesDefinitions\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */ \r
+\r
+/** @defgroup MISC_Private_Defines\r
+  * @{\r
+  */\r
+\r
+#define AIRCR_VECTKEY_MASK    ((uint32_t)0x05FA0000)\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup MISC_Private_Macros\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup MISC_Private_Variables\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup MISC_Private_FunctionPrototypes\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup MISC_Private_Functions\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @brief  Configures the priority grouping: pre-emption priority and subpriority.\r
+  * @param  NVIC_PriorityGroup: specifies the priority grouping bits length. \r
+  *   This parameter can be one of the following values:\r
+  *     @arg NVIC_PriorityGroup_0: 0 bits for pre-emption priority\r
+  *                                4 bits for subpriority\r
+  *     @arg NVIC_PriorityGroup_1: 1 bits for pre-emption priority\r
+  *                                3 bits for subpriority\r
+  *     @arg NVIC_PriorityGroup_2: 2 bits for pre-emption priority\r
+  *                                2 bits for subpriority\r
+  *     @arg NVIC_PriorityGroup_3: 3 bits for pre-emption priority\r
+  *                                1 bits for subpriority\r
+  *     @arg NVIC_PriorityGroup_4: 4 bits for pre-emption priority\r
+  *                                0 bits for subpriority\r
+  * @retval None\r
+  */\r
+void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_NVIC_PRIORITY_GROUP(NVIC_PriorityGroup));\r
+  \r
+  /* Set the PRIGROUP[10:8] bits according to NVIC_PriorityGroup value */\r
+  SCB->AIRCR = AIRCR_VECTKEY_MASK | NVIC_PriorityGroup;\r
+}\r
+\r
+/**\r
+  * @brief  Initializes the NVIC peripheral according to the specified\r
+  *   parameters in the NVIC_InitStruct.\r
+  * @param  NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure that contains\r
+  *   the configuration information for the specified NVIC peripheral.\r
+  * @retval None\r
+  */\r
+void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct)\r
+{\r
+  uint32_t tmppriority = 0x00, tmppre = 0x00, tmpsub = 0x0F;\r
+  \r
+  /* Check the parameters */\r
+  assert_param(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd));\r
+  assert_param(IS_NVIC_PREEMPTION_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority));  \r
+  assert_param(IS_NVIC_SUB_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelSubPriority));\r
+    \r
+  if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE)\r
+  {\r
+    /* Compute the Corresponding IRQ Priority --------------------------------*/    \r
+    tmppriority = (0x700 - ((SCB->AIRCR) & (uint32_t)0x700))>> 0x08;\r
+    tmppre = (0x4 - tmppriority);\r
+    tmpsub = tmpsub >> tmppriority;\r
+\r
+    tmppriority = (uint32_t)NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << tmppre;\r
+    tmppriority |=  NVIC_InitStruct->NVIC_IRQChannelSubPriority & tmpsub;\r
+    tmppriority = tmppriority << 0x04;\r
+        \r
+    NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel] = tmppriority;\r
+    \r
+    /* Enable the Selected IRQ Channels --------------------------------------*/\r
+    NVIC->ISER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =\r
+      (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);\r
+  }\r
+  else\r
+  {\r
+    /* Disable the Selected IRQ Channels -------------------------------------*/\r
+    NVIC->ICER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =\r
+      (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  Sets the vector table location and Offset.\r
+  * @param  NVIC_VectTab: specifies if the vector table is in RAM or FLASH memory.\r
+  *   This parameter can be one of the following values:\r
+  *     @arg NVIC_VectTab_RAM\r
+  *     @arg NVIC_VectTab_FLASH\r
+  * @param  Offset: Vector Table base offset field. This value must be a multiple of 0x100.\r
+  * @retval None\r
+  */\r
+void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset)\r
+{ \r
+  /* Check the parameters */\r
+  assert_param(IS_NVIC_VECTTAB(NVIC_VectTab));\r
+  assert_param(IS_NVIC_OFFSET(Offset));  \r
+   \r
+  SCB->VTOR = NVIC_VectTab | (Offset & (uint32_t)0x1FFFFF80);\r
+}\r
+\r
+/**\r
+  * @brief  Selects the condition for the system to enter low power mode.\r
+  * @param  LowPowerMode: Specifies the new mode for the system to enter low power mode.\r
+  *   This parameter can be one of the following values:\r
+  *     @arg NVIC_LP_SEVONPEND\r
+  *     @arg NVIC_LP_SLEEPDEEP\r
+  *     @arg NVIC_LP_SLEEPONEXIT\r
+  * @param  NewState: new state of LP condition. This parameter can be: ENABLE or DISABLE.\r
+  * @retval None\r
+  */\r
+void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_NVIC_LP(LowPowerMode));\r
+  assert_param(IS_FUNCTIONAL_STATE(NewState));  \r
+  \r
+  if (NewState != DISABLE)\r
+  {\r
+    SCB->SCR |= LowPowerMode;\r
+  }\r
+  else\r
+  {\r
+    SCB->SCR &= (uint32_t)(~(uint32_t)LowPowerMode);\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  Configures the SysTick clock source.\r
+  * @param  SysTick_CLKSource: specifies the SysTick clock source.\r
+  *   This parameter can be one of the following values:\r
+  *     @arg SysTick_CLKSource_HCLK_Div8: AHB clock divided by 8 selected as SysTick clock source.\r
+  *     @arg SysTick_CLKSource_HCLK: AHB clock selected as SysTick clock source.\r
+  * @retval None\r
+  */\r
+void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_SYSTICK_CLK_SOURCE(SysTick_CLKSource));\r
+  if (SysTick_CLKSource == SysTick_CLKSource_HCLK)\r
+  {\r
+    SysTick->CTRL |= SysTick_CLKSource_HCLK;\r
+  }\r
+  else\r
+  {\r
+    SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8;\r
+  }\r
+}\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r

diff --git a/Demo/CORTEX_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_exti.c b/Demo/CORTEX_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_exti.c
new file mode 100644 (file)
index 0000000..348f33c
--- /dev/null
+++ b/Demo/CORTEX_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_exti.c
@@ -0,0 +1,268 @@
+/**\r
+  ******************************************************************************\r
+  * @file    stm32l1xx_exti.c\r
+  * @author  MCD Application Team\r
+  * @version V1.0.0RC1\r
+  * @date    07/02/2010\r
+  * @brief   This file provides all the EXTI firmware functions.\r
+  ******************************************************************************\r
+  * @copy\r
+  *\r
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+  *\r
+  * <h2><center>&copy; COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+  */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx_exti.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+  * @{\r
+  */\r
+\r
+/** @defgroup EXTI \r
+  * @brief EXTI driver modules\r
+  * @{\r
+  */\r
+\r
+/** @defgroup EXTI_Private_TypesDefinitions\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup EXTI_Private_Defines\r
+  * @{\r
+  */\r
+\r
+#define EXTI_LINENONE    ((uint32_t)0x00000)  /* No interrupt selected */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup EXTI_Private_Macros\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup EXTI_Private_Variables\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup EXTI_Private_FunctionPrototypes\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup EXTI_Private_Functions\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @brief  Deinitializes the EXTI peripheral registers to their default reset values.\r
+  * @param  None\r
+  * @retval None\r
+  */\r
+void EXTI_DeInit(void)\r
+{\r
+  EXTI->IMR = 0x00000000;\r
+  EXTI->EMR = 0x00000000;\r
+  EXTI->RTSR = 0x00000000; \r
+  EXTI->FTSR = 0x00000000; \r
+  EXTI->PR = 0x007FFFFF;\r
+}\r
+\r
+/**\r
+  * @brief  Initializes the EXTI peripheral according to the specified\r
+  *   parameters in the EXTI_InitStruct.\r
+  * @param  EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure\r
+  *   that contains the configuration information for the EXTI peripheral.\r
+  * @retval None\r
+  */\r
+void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct)\r
+{\r
+  uint32_t tmp = 0;\r
+\r
+  /* Check the parameters */\r
+  assert_param(IS_EXTI_MODE(EXTI_InitStruct->EXTI_Mode));\r
+  assert_param(IS_EXTI_TRIGGER(EXTI_InitStruct->EXTI_Trigger));\r
+  assert_param(IS_EXTI_LINE(EXTI_InitStruct->EXTI_Line));  \r
+  assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->EXTI_LineCmd));\r
+\r
+  tmp = (uint32_t)EXTI_BASE;\r
+     \r
+  if (EXTI_InitStruct->EXTI_LineCmd != DISABLE)\r
+  {\r
+    /* Clear EXTI line configuration */\r
+    EXTI->IMR &= ~EXTI_InitStruct->EXTI_Line;\r
+    EXTI->EMR &= ~EXTI_InitStruct->EXTI_Line;\r
+    \r
+    tmp += EXTI_InitStruct->EXTI_Mode;\r
+\r
+    *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line;\r
+\r
+    /* Clear Rising Falling edge configuration */\r
+    EXTI->RTSR &= ~EXTI_InitStruct->EXTI_Line;\r
+    EXTI->FTSR &= ~EXTI_InitStruct->EXTI_Line;\r
+    \r
+    /* Select the trigger for the selected external interrupts */\r
+    if (EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling)\r
+    {\r
+      /* Rising Falling edge */\r
+      EXTI->RTSR |= EXTI_InitStruct->EXTI_Line;\r
+      EXTI->FTSR |= EXTI_InitStruct->EXTI_Line;\r
+    }\r
+    else\r
+    {\r
+      tmp = (uint32_t)EXTI_BASE;\r
+      tmp += EXTI_InitStruct->EXTI_Trigger;\r
+\r
+      *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line;\r
+    }\r
+  }\r
+  else\r
+  {\r
+    tmp += EXTI_InitStruct->EXTI_Mode;\r
+\r
+    /* Disable the selected external lines */\r
+    *(__IO uint32_t *) tmp &= ~EXTI_InitStruct->EXTI_Line;\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  Fills each EXTI_InitStruct member with its reset value.\r
+  * @param  EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure which will\r
+  *   be initialized.\r
+  * @retval None\r
+  */\r
+void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct)\r
+{\r
+  EXTI_InitStruct->EXTI_Line = EXTI_LINENONE;\r
+  EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt;\r
+  EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling;\r
+  EXTI_InitStruct->EXTI_LineCmd = DISABLE;\r
+}\r
+\r
+/**\r
+  * @brief  Generates a Software interrupt.\r
+  * @param  EXTI_Line: specifies the EXTI lines to be enabled or disabled.\r
+  *   This parameter can be any combination of EXTI_Linex where x can be (0..22).\r
+  * @retval None\r
+  */\r
+void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_EXTI_LINE(EXTI_Line));\r
+  \r
+  EXTI->SWIER |= EXTI_Line;\r
+}\r
+\r
+/**\r
+  * @brief  Checks whether the specified EXTI line flag is set or not.\r
+  * @param  EXTI_Line: specifies the EXTI line flag to check.\r
+  *   This parameter can be:\r
+  *     @arg EXTI_Linex: External interrupt line x where x(0..22)\r
+  * @retval The new state of EXTI_Line (SET or RESET).\r
+  */\r
+FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line)\r
+{\r
+  FlagStatus bitstatus = RESET;\r
+  /* Check the parameters */\r
+  assert_param(IS_GET_EXTI_LINE(EXTI_Line));\r
+  \r
+  if ((EXTI->PR & EXTI_Line) != (uint32_t)RESET)\r
+  {\r
+    bitstatus = SET;\r
+  }\r
+  else\r
+  {\r
+    bitstatus = RESET;\r
+  }\r
+  return bitstatus;\r
+}\r
+\r
+/**\r
+  * @brief  Clears the EXTI\92s line pending flags.\r
+  * @param  EXTI_Line: specifies the EXTI lines flags to clear.\r
+  *   This parameter can be any combination of EXTI_Linex where x can be (0..22).\r
+  * @retval None\r
+  */\r
+void EXTI_ClearFlag(uint32_t EXTI_Line)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_EXTI_LINE(EXTI_Line));\r
+  \r
+  EXTI->PR = EXTI_Line;\r
+}\r
+\r
+/**\r
+  * @brief  Checks whether the specified EXTI line is asserted or not.\r
+  * @param  EXTI_Line: specifies the EXTI line to check.\r
+  *   This parameter can be:\r
+  *     @arg EXTI_Linex: External interrupt line x where x(0..22)\r
+  * @retval The new state of EXTI_Line (SET or RESET).\r
+  */\r
+ITStatus EXTI_GetITStatus(uint32_t EXTI_Line)\r
+{\r
+  ITStatus bitstatus = RESET;\r
+  uint32_t enablestatus = 0;\r
+  /* Check the parameters */\r
+  assert_param(IS_GET_EXTI_LINE(EXTI_Line));\r
+  \r
+  enablestatus =  EXTI->IMR & EXTI_Line;\r
+  if (((EXTI->PR & EXTI_Line) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET))\r
+  {\r
+    bitstatus = SET;\r
+  }\r
+  else\r
+  {\r
+    bitstatus = RESET;\r
+  }\r
+  return bitstatus;\r
+}\r
+\r
+/**\r
+  * @brief  Clears the EXTI\92s line pending bits.\r
+  * @param  EXTI_Line: specifies the EXTI lines to clear.\r
+  *   This parameter can be any combination of EXTI_Linex where x can be (0..22).\r
+  * @retval None\r
+  */\r
+void EXTI_ClearITPendingBit(uint32_t EXTI_Line)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_EXTI_LINE(EXTI_Line));\r
+  \r
+  EXTI->PR = EXTI_Line;\r
+}\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r

diff --git a/Demo/CORTEX_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_gpio.c b/Demo/CORTEX_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_gpio.c
new file mode 100644 (file)
index 0000000..6c45f16
--- /dev/null
+++ b/Demo/CORTEX_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_gpio.c
@@ -0,0 +1,437 @@
+/**\r
+  ******************************************************************************\r
+  * @file    stm32l1xx_gpio.c\r
+  * @author  MCD Application Team\r
+  * @version V1.0.0RC1\r
+  * @date    07/02/2010\r
+  * @brief   This file provides all the GPIO firmware functions.\r
+  ******************************************************************************\r
+  * @copy\r
+  *\r
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+  *\r
+  * <h2><center>&copy; COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+  */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx_gpio.h"\r
+#include "stm32l1xx_rcc.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+  * @{\r
+  */\r
+\r
+/** @defgroup GPIO \r
+  * @brief GPIO driver modules\r
+  * @{\r
+  */\r
+\r
+/** @defgroup GPIO_Private_TypesDefinitions\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup GPIO_Private_Defines\r
+  * @{\r
+  */ \r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup GPIO_Private_Macros\r
+  * @{\r
+  */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup GPIO_Private_Variables\r
+  * @{\r
+  */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup GPIO_Private_FunctionPrototypes\r
+  * @{\r
+  */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup GPIO_Private_Functions\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @brief  Deinitializes the GPIOx peripheral registers to their default reset \r
+  *         values.\r
+  * @param  GPIOx: where x can be (A, B, C, D, E or H) to select the GPIO peripheral.\r
+  * @retval None\r
+  */\r
+void GPIO_DeInit(GPIO_TypeDef* GPIOx)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r
+\r
+  if(GPIOx == GPIOA)\r
+  {\r
+    RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOA, ENABLE);\r
+    RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOA, DISABLE);  \r
+  }\r
+  else if(GPIOx == GPIOB)\r
+  {\r
+    RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOB, ENABLE);\r
+    RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOB, DISABLE);\r
+  }\r
+  else if(GPIOx == GPIOC)\r
+  {\r
+    RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOC, ENABLE);\r
+    RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOC, DISABLE);\r
+  }\r
+  else if(GPIOx == GPIOD)\r
+  {\r
+    RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOD, ENABLE);\r
+    RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOD, DISABLE);\r
+  }\r
+  else if(GPIOx == GPIOE)\r
+  {\r
+      RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOE, ENABLE);\r
+      RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOE, DISABLE);\r
+  }\r
+  else\r
+  {\r
+    if(GPIOx == GPIOH)\r
+    {\r
+      RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOH, ENABLE);\r
+      RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOH, DISABLE);\r
+    }\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  Initializes the GPIOx peripheral according to the specified \r
+  *         parameters in the GPIO_InitStruct.\r
+  * @param  GPIOx: where x can be (A, B, C, D, E or H) to select the GPIO peripheral.\r
+  * @param  GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure that \r
+  *         contains the configuration information for the specified GPIO\r
+  *         peripheral.\r
+  * @retval None\r
+  */\r
+void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct)\r
+{\r
+  uint32_t pinpos = 0x00, pos = 0x00 , currentpin = 0x00;\r
+  \r
+  /* Check the parameters */\r
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r
+  assert_param(IS_GPIO_PIN(GPIO_InitStruct->GPIO_Pin));\r
+  assert_param(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode));\r
+  assert_param(IS_GPIO_PUPD(GPIO_InitStruct->GPIO_PuPd));\r
+\r
+  /* -------------------------Configure the port pins---------------- */\r
+  /*-- GPIO Mode Configuration --*/\r
+  for (pinpos = 0x00; pinpos < 0x10; pinpos++)\r
+  {\r
+    pos = ((uint32_t)0x01) << pinpos;\r
+\r
+    /* Get the port pins position */\r
+    currentpin = (GPIO_InitStruct->GPIO_Pin) & pos;\r
+\r
+    if (currentpin == pos)\r
+    {\r
+      GPIOx->MODER  &= ~(GPIO_MODER_MODER0 << (pinpos * 2));\r
+\r
+      GPIOx->MODER |= (((uint32_t)GPIO_InitStruct->GPIO_Mode) << (pinpos * 2));\r
+\r
+      if ((GPIO_InitStruct->GPIO_Mode == GPIO_Mode_OUT) || (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_AF))\r
+      {\r
+        /*Check Speed mode parameters */\r
+        assert_param(IS_GPIO_SPEED(GPIO_InitStruct->GPIO_Speed));\r
+\r
+        /*Speed mode configuration */\r
+        GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (pinpos * 2));\r
+        GPIOx->OSPEEDR |= ((uint32_t)(GPIO_InitStruct->GPIO_Speed) << (pinpos * 2));\r
+\r
+        /*Check Output mode parameters */\r
+        assert_param(IS_GPIO_OTYPE(GPIO_InitStruct->GPIO_OType));\r
+\r
+        /* Output mode configuartion*/\r
+        GPIOx->OTYPER  &= ~((GPIO_OTYPER_OT_0) << ((uint16_t)pinpos)) ;\r
+        GPIOx->OTYPER |= (uint16_t)(((uint16_t)GPIO_InitStruct->GPIO_OType) << ((uint16_t)pinpos));\r
+      }\r
+\r
+      /*Pull-up Pull down resistor configuration*/\r
+      GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << ((uint16_t)pinpos * 2));\r
+      GPIOx->PUPDR |= (((uint32_t)GPIO_InitStruct->GPIO_PuPd) << (pinpos * 2));\r
+    }\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  Fills each GPIO_InitStruct member with its default value.\r
+  * @param  GPIO_InitStruct : pointer to a GPIO_InitTypeDef structure which will \r
+  *         be initialized.\r
+  * @retval None\r
+  */\r
+void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct)\r
+{\r
+  /* Reset GPIO init structure parameters values */\r
+  GPIO_InitStruct->GPIO_Pin  = GPIO_Pin_All;\r
+  GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN;\r
+  GPIO_InitStruct->GPIO_Speed = GPIO_Speed_400KHz;\r
+  GPIO_InitStruct->GPIO_OType = GPIO_OType_PP;\r
+  GPIO_InitStruct->GPIO_PuPd = GPIO_PuPd_NOPULL;\r
+}\r
+\r
+/**\r
+  * @brief  Reads the specified input port pin.\r
+  * @param  GPIOx: where x can be (A, B, C, D, E or H) to select the GPIO peripheral.\r
+  * @param  GPIO_Pin: specifies the port bit to read.\r
+  *   This parameter can be GPIO_Pin_x where x can be (0..15).\r
+  * @retval The input port pin value.\r
+  */\r
+uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)\r
+{\r
+  uint8_t bitstatus = 0x00;\r
+  \r
+  /* Check the parameters */\r
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r
+  assert_param(IS_GET_GPIO_PIN(GPIO_Pin));\r
+\r
+  if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)Bit_RESET)\r
+  {\r
+    bitstatus = (uint8_t)Bit_SET;\r
+  }\r
+  else\r
+  {\r
+    bitstatus = (uint8_t)Bit_RESET;\r
+  }\r
+  return bitstatus;\r
+}\r
+\r
+/**\r
+  * @brief  Reads the specified GPIO input data port.\r
+  * @param  GPIOx: where x can be (A, B, C, D, E or H) to select the GPIO peripheral.\r
+  * @retval GPIO input data port value.\r
+  */\r
+uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r
+  \r
+  return ((uint16_t)GPIOx->IDR);\r
+}\r
+\r
+/**\r
+  * @brief  Reads the specified output data port bit.\r
+  * @param  GPIOx: where x can be (A, B, C, D, E or H) to select the GPIO peripheral.\r
+  * @param  GPIO_Pin: Specifies the port bit to read.\r
+  *   This parameter can be GPIO_Pin_x where x can be (0..15).\r
+  * @retval The output port pin value.\r
+  */\r
+uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)\r
+{\r
+  uint8_t bitstatus = 0x00;\r
+\r
+  /* Check the parameters */\r
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r
+  assert_param(IS_GET_GPIO_PIN(GPIO_Pin));\r
+  \r
+  if ((GPIOx->ODR & GPIO_Pin) != (uint32_t)Bit_RESET)\r
+  {\r
+    bitstatus = (uint8_t)Bit_SET;\r
+  }\r
+  else\r
+  {\r
+    bitstatus = (uint8_t)Bit_RESET;\r
+  }\r
+  return bitstatus;\r
+}\r
+\r
+/**\r
+  * @brief  Reads the specified GPIO output data port.\r
+  * @param  GPIOx: where x can be (A, B, C, D, E or H) to select the GPIO peripheral.\r
+  * @retval GPIO output data port value.\r
+  */\r
+uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r
+  \r
+  return ((uint16_t)GPIOx->ODR);\r
+}\r
+\r
+/**\r
+  * @brief  Sets the selected data port bits.\r
+  * @param  GPIOx: where x can be (A, B, C, D, E or H) to select the GPIO peripheral.\r
+  * @param  GPIO_Pin: specifies the port bits to be written.\r
+  *   This parameter can be any combination of GPIO_Pin_x where x can be (0..15).\r
+  * @retval None\r
+  */\r
+void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r
+  assert_param(IS_GPIO_PIN(GPIO_Pin));\r
+  \r
+  GPIOx->BSRRL = GPIO_Pin;\r
+}\r
+\r
+/**\r
+  * @brief  Clears the selected data port bits.\r
+  * @param  GPIOx: where x can be (A, B, C, D, E or H) to select the GPIO peripheral.\r
+  * @param  GPIO_Pin: specifies the port bits to be written.\r
+  *   This parameter can be any combination of GPIO_Pin_x where x can be (0..15).\r
+  * @retval None\r
+  */\r
+void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r
+  assert_param(IS_GPIO_PIN(GPIO_Pin));\r
+  \r
+  GPIOx->BSRRH = GPIO_Pin;\r
+}\r
+\r
+/**\r
+  * @brief  Sets or clears the selected data port bit.\r
+  * @param  GPIOx: where x can be (A, B, C, D, E or H) to select the GPIO peripheral.\r
+  * @param  GPIO_Pin: specifies the port bit to be written.\r
+  *   This parameter can be one of GPIO_Pin_x where x can be (0..15).\r
+  * @param  BitVal: specifies the value to be written to the selected bit.\r
+  *   This parameter can be one of the BitAction enum values:\r
+  *     @arg Bit_RESET: to clear the port pin\r
+  *     @arg Bit_SET: to set the port pin\r
+  * @retval None\r
+  */\r
+void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r
+  assert_param(IS_GET_GPIO_PIN(GPIO_Pin));\r
+  assert_param(IS_GPIO_BIT_ACTION(BitVal));\r
+  \r
+  if (BitVal != Bit_RESET)\r
+  {\r
+    GPIOx->BSRRL = GPIO_Pin;\r
+  }\r
+  else\r
+  {\r
+    GPIOx->BSRRH = GPIO_Pin ;\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  Writes data to the specified GPIO data port.\r
+  * @param  GPIOx: where x can be (A, B, C, D, E or H) to select the GPIO peripheral.\r
+  * @param  PortVal: specifies the value to be written to the port output data \r
+  *                  register.\r
+  * @retval None\r
+  */\r
+void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r
+  \r
+  GPIOx->ODR = PortVal;\r
+}\r
+\r
+/**\r
+  * @brief  Locks GPIO Pins configuration registers.\r
+  * @param  GPIOx: where x can be (A, B, C, D, E or H) to select the GPIO peripheral.\r
+  * @param  GPIO_Pin: specifies the port bit to be written.\r
+  *   This parameter can be any combination of GPIO_Pin_x where x can be (0..15).\r
+  * @retval None\r
+  */\r
+void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)\r
+{\r
+  uint32_t tmp = 0x00010000;\r
+  \r
+  /* Check the parameters */\r
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r
+  assert_param(IS_GPIO_PIN(GPIO_Pin));\r
+  \r
+  tmp |= GPIO_Pin;\r
+  /* Set LCKK bit */\r
+  GPIOx->LCKR = tmp;\r
+  /* Reset LCKK bit */\r
+  GPIOx->LCKR =  GPIO_Pin;\r
+  /* Set LCKK bit */\r
+  GPIOx->LCKR = tmp;\r
+  /* Read LCKK bit*/\r
+  tmp = GPIOx->LCKR;\r
+  /* Read LCKK bit*/\r
+  tmp = GPIOx->LCKR;\r
+}\r
+\r
+/**\r
+  * @brief  Changes the mapping of the specified pin.\r
+  * @param  GPIOx: where x can be (A, B, C, D, E or H) to select the GPIO peripheral.\r
+  * @param  GPIO_PinSource: specifies the pin for the Alternate function.\r
+  *   This parameter can be GPIO_PinSourcex where x can be (0..15).\r
+  * @param  GPIO_AFSelection: selects the pin to used as Alternat function.\r
+  *   This parameter can be one of the following values:\r
+  *     @arg GPIO_AF_RTC_50Hz\r
+  *     @arg GPIO_AF_MCO\r
+  *     @arg GPIO_AF_TAMPER\r
+  *     @arg GPIO_AF_WKUP\r
+  *     @arg GPIO_AF_SWJ\r
+  *     @arg GPIO_AF_TRACE\r
+  *     @arg GPIO_AF_TIMESTAMP\r
+  *     @arg GPIO_AF_CALIB\r
+  *     @arg GPIO_AF_TIM2\r
+  *     @arg GPIO_AF_TIM3\r
+  *     @arg GPIO_AF_TIM4\r
+  *     @arg GPIO_AF_TIM9\r
+  *     @arg GPIO_AF_TIM10\r
+  *     @arg GPIO_AF_TIM11\r
+  *     @arg GPIO_AF_I2C1\r
+  *     @arg GPIO_AF_I2C2\r
+  *     @arg GPIO_AF_SPI1\r
+  *     @arg GPIO_AF_SPI2\r
+  *     @arg GPIO_AF_USART1\r
+  *     @arg GPIO_AF_USART2\r
+  *     @arg GPIO_AF_USART3\r
+  *     @arg GPIO_AF_USB\r
+  *     @arg GPIO_AF_LCD\r
+  *     @arg GPIO_AF_RI\r
+  *     @arg GPIO_AF_EVENTOUT\r
+  * @retval None\r
+  */\r
+void GPIO_PinAFConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO_AF)\r
+{\r
+  uint32_t temp = 0x00;\r
+  uint32_t temp_2 = 0x00;\r
+  \r
+  /* Check the parameters */\r
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r
+  assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource));\r
+  assert_param(IS_GPIO_AF(GPIO_AF));\r
+  \r
+  temp = ((uint32_t)(GPIO_AF) << ((uint32_t)((uint32_t)GPIO_PinSource & (uint32_t)0x07) * 4)) ;\r
+  GPIOx->AFR[GPIO_PinSource >> 0x03] &= ~((uint32_t)0xF << ((uint32_t)((uint32_t)GPIO_PinSource & (uint32_t)0x07) * 4)) ;\r
+  temp_2 = GPIOx->AFR[GPIO_PinSource >> 0x03] | temp;\r
+  GPIOx->AFR[GPIO_PinSource >> 0x03] = temp_2;\r
+}\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r

diff --git a/Demo/CORTEX_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_pwr.c b/Demo/CORTEX_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_pwr.c
new file mode 100644 (file)
index 0000000..e6b8716
--- /dev/null
+++ b/Demo/CORTEX_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_pwr.c
@@ -0,0 +1,464 @@
+/**\r
+  ******************************************************************************\r
+  * @file    stm32l1xx_pwr.c\r
+  * @author  MCD Application Team\r
+  * @version V1.0.0RC1\r
+  * @date    07/02/2010\r
+  * @brief   This file provides all the PWR firmware functions.\r
+  ******************************************************************************\r
+  * @copy\r
+  *\r
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+  *\r
+  * <h2><center>&copy; COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+  */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx_pwr.h"\r
+#include "stm32l1xx_rcc.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+  * @{\r
+  */\r
+\r
+/** @defgroup PWR \r
+  * @brief PWR driver modules\r
+  * @{\r
+  */ \r
+\r
+/** @defgroup PWR_Private_TypesDefinitions\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup PWR_Private_Defines\r
+  * @{\r
+  */\r
+\r
+/* --------- PWR registers bit address in the alias region ---------- */\r
+#define PWR_OFFSET               (PWR_BASE - PERIPH_BASE)\r
+\r
+/* --- CR Register ---*/\r
+\r
+/* Alias word address of DBP bit */\r
+#define CR_OFFSET                (PWR_OFFSET + 0x00)\r
+#define DBP_BitNumber            0x08\r
+#define CR_DBP_BB                (PERIPH_BB_BASE + (CR_OFFSET * 32) + (DBP_BitNumber * 4))\r
+\r
+/* Alias word address of PVDE bit */\r
+#define PVDE_BitNumber           0x04\r
+#define CR_PVDE_BB               (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PVDE_BitNumber * 4))\r
+\r
+/* Alias word address of ULP bit */\r
+#define ULP_BitNumber           0x09\r
+#define CR_ULP_BB               (PERIPH_BB_BASE + (CR_OFFSET * 32) + (ULP_BitNumber * 4))\r
+\r
+/* Alias word address of FWU bit */\r
+#define FWU_BitNumber           0x0A\r
+#define CR_FWU_BB               (PERIPH_BB_BASE + (CR_OFFSET * 32) + (FWU_BitNumber * 4))\r
+\r
+/* --- CSR Register ---*/\r
+\r
+/* Alias word address of EWUP bit */\r
+#define CSR_OFFSET               (PWR_OFFSET + 0x04)\r
+#define EWUP_BitNumber           0x08\r
+#define CSR_EWUP_BB              (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP_BitNumber * 4))\r
+\r
+/* ------------------ PWR registers bit mask ------------------------ */\r
+\r
+/* CR register bit mask */\r
+#define CR_DS_MASK               ((uint32_t)0xFFFFFFFC)\r
+#define CR_PLS_MASK              ((uint32_t)0xFFFFFF1F)\r
+#define CR_VOS_MASK              ((uint32_t)0xFFFFE7FF)\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup PWR_Private_Macros\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup PWR_Private_Variables\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup PWR_Private_FunctionPrototypes\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup PWR_Private_Functions\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @brief  Deinitializes the PWR peripheral registers to their default reset values.\r
+  * @param  None\r
+  * @retval None\r
+  */\r
+void PWR_DeInit(void)\r
+{\r
+  RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE);\r
+  RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE);\r
+}\r
+\r
+/**\r
+  * @brief  Enables or disables access to the RTC and backup registers.\r
+  * @param  NewState: new state of the access to the RTC and backup registers.\r
+  *   This parameter can be: ENABLE or DISABLE.\r
+  * @retval None\r
+  */\r
+void PWR_RTCAccessCmd(FunctionalState NewState)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+  \r
+  *(__IO uint32_t *) CR_DBP_BB = (uint32_t)NewState;\r
+}\r
+\r
+/**\r
+  * @brief  Enables or disables the Power Voltage Detector(PVD).\r
+  * @param  NewState: new state of the PVD.\r
+  *   This parameter can be: ENABLE or DISABLE.\r
+  * @retval None\r
+  */\r
+void PWR_PVDCmd(FunctionalState NewState)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+  \r
+  *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)NewState;\r
+}\r
+\r
+/**\r
+  * @brief  Configures the voltage threshold detected by the Power Voltage Detector(PVD).\r
+  * @param  PWR_PVDLevel: specifies the PVD detection level\r
+  *   This parameter can be one of the following values:\r
+  *     @arg PWR_PVDLevel_0: PVD detection level set to 1.9V\r
+  *     @arg PWR_PVDLevel_1: PVD detection level set to 2.1V\r
+  *     @arg PWR_PVDLevel_2: PVD detection level set to 2.3V\r
+  *     @arg PWR_PVDLevel_3: PVD detection level set to 2.5V\r
+  *     @arg PWR_PVDLevel_4: PVD detection level set to 2.7V\r
+  *     @arg PWR_PVDLevel_5: PVD detection level set to 2.9V\r
+  *     @arg PWR_PVDLevel_6: PVD detection level set to 3.1V\r
+  *     @arg PWR_PVDLevel_7: External input analog voltage (Compare internally to VREFINT)\r
+  * @retval None\r
+  */\r
+void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel)\r
+{\r
+  uint32_t tmpreg = 0;\r
+  \r
+  /* Check the parameters */\r
+  assert_param(IS_PWR_PVD_LEVEL(PWR_PVDLevel));\r
+  \r
+  tmpreg = PWR->CR;\r
+  \r
+  /* Clear PLS[7:5] bits */\r
+  tmpreg &= CR_PLS_MASK;\r
+  \r
+  /* Set PLS[7:5] bits according to PWR_PVDLevel value */\r
+  tmpreg |= PWR_PVDLevel;\r
+  \r
+  /* Store the new value */\r
+  PWR->CR = tmpreg;\r
+}\r
+\r
+/**\r
+  * @brief  Enables or disables the WakeUp Pin functionality.\r
+  * @param  PWR_WakeUpPin: specifies the WakeUpPin.\r
+  *   This parameter can be: PWR_WakeUpPin_1, PWR_WakeUpPin_2 or PWR_WakeUpPin_3.\r
+  * @param  NewState: new state of the WakeUp Pin functionality.\r
+  *   This parameter can be: ENABLE or DISABLE.\r
+  * @retval None\r
+  */\r
+void PWR_WakeUpPinCmd(uint32_t PWR_WakeUpPin, FunctionalState NewState)\r
+{\r
+  __IO uint32_t tmp = 0;\r
+  \r
+  /* Check the parameters */\r
+  assert_param(IS_PWR_WAKEUP_PIN(PWR_WakeUpPin));\r
+  \r
+  assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+  tmp = CSR_EWUP_BB + PWR_WakeUpPin;\r
+  \r
+  *(__IO uint32_t *) (tmp) = (uint32_t)NewState;\r
+}\r
+\r
+/**\r
+  * @brief  Enables or disables the Fast WakeUp from Ultra Low Power mode.\r
+  * @param  NewState: new state of the Fast WakeUp  functionality.\r
+  *   This parameter can be: ENABLE or DISABLE.\r
+  * @retval None\r
+  */\r
+void PWR_FastWakeUpCmd(FunctionalState NewState)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+  *(__IO uint32_t *) CR_FWU_BB = (uint32_t)NewState;\r
+}\r
+\r
+/**\r
+  * @brief  Enables or disables the Ultra Low Power mode.\r
+  * @param  NewState: new state of the Ultra Low Power mode.\r
+  *   This parameter can be: ENABLE or DISABLE.\r
+  * @retval None\r
+  */\r
+void PWR_UltraLowPowerCmd(FunctionalState NewState)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+  *(__IO uint32_t *) CR_ULP_BB = (uint32_t)NewState;\r
+}\r
+\r
+/**\r
+  * @brief  Configures the voltage scaling range.\r
+  * @param  PWR_VoltageScaling: specifies the voltage scaling range.\r
+  *   This parameter can be:\r
+  *     @arg PWR_VoltageScaling_Range1: Voltage Scaling Range 1\r
+  *     @arg PWR_VoltageScaling_Range2: Voltage Scaling Range 2\r
+  *     @arg PWR_VoltageScaling_Range3: Voltage Scaling Range 3      \r
+  * @retval None\r
+  */\r
+void PWR_VoltageScalingConfig(uint32_t PWR_VoltageScaling)\r
+{\r
+  uint32_t tmp = 0;\r
+  \r
+  /* Check the parameters */\r
+  assert_param(IS_PWR_VOLTAGE_SCALING_RANGE(PWR_VoltageScaling));\r
+  \r
+  tmp = PWR->CR;\r
+\r
+  tmp &= CR_VOS_MASK;\r
+  tmp |= PWR_VoltageScaling;\r
+  \r
+  PWR->CR = tmp & 0xFFFFFFF3;\r
+\r
+}\r
+\r
+/**\r
+  * @brief  Enters/Exits the Low Power Run mode.\r
+  * @param  NewState: new state of the Low Power Run mode.\r
+  *   This parameter can be: ENABLE or DISABLE.\r
+  * @retval None\r
+  */\r
+void PWR_EnterLowPowerRunMode(FunctionalState NewState)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+  if (NewState != DISABLE)\r
+  {\r
+    PWR->CR |= PWR_CR_LPSDSR;\r
+    PWR->CR |= PWR_CR_LPRUN;     \r
+  }\r
+  else\r
+  {\r
+    PWR->CR &= (uint32_t)~((uint32_t)PWR_CR_LPRUN); \r
+    PWR->CR &= (uint32_t)~((uint32_t)PWR_CR_LPSDSR);  \r
+  }  \r
+}\r
+\r
+/**\r
+  * @brief  Enters Sleep mode.\r
+  * @param  PWR_Regulator: specifies the regulator state in Sleep mode.\r
+  *   This parameter can be one of the following values:\r
+  *     @arg PWR_Regulator_ON: Sleep mode with regulator ON\r
+  *     @arg PWR_Regulator_LowPower: Sleep mode with regulator in low power mode\r
+  * @param  PWR_SLEEPEntry: specifies if SLEEP mode in entered with WFI or WFE instruction.\r
+  *   This parameter can be one of the following values:\r
+  *     @arg PWR_SLEEPEntry_WFI: enter SLEEP mode with WFI instruction\r
+  *     @arg PWR_SLEEPEntry_WFE: enter SLEEP mode with WFE instruction\r
+  * @retval None\r
+  */\r
+void PWR_EnterSleepMode(uint32_t PWR_Regulator, uint8_t PWR_SLEEPEntry)\r
+{\r
+  uint32_t tmpreg = 0;\r
+\r
+  /* Check the parameters */\r
+  assert_param(IS_PWR_REGULATOR(PWR_Regulator));\r
+\r
+  assert_param(IS_PWR_SLEEP_ENTRY(PWR_SLEEPEntry));\r
+  \r
+  /* Select the regulator state in Sleep mode ---------------------------------*/\r
+  tmpreg = PWR->CR;\r
+  \r
+  /* Clear PDDS and LPDSR bits */\r
+  tmpreg &= CR_DS_MASK;\r
+  \r
+  /* Set LPDSR bit according to PWR_Regulator value */\r
+  tmpreg |= PWR_Regulator;\r
+  \r
+  /* Store the new value */\r
+  PWR->CR = tmpreg;\r
+\r
+  /* Clear SLEEPDEEP bit of Cortex System Control Register */\r
+  SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP);\r
+  \r
+  /* Select SLEEP mode entry -------------------------------------------------*/\r
+  if(PWR_SLEEPEntry == PWR_SLEEPEntry_WFI)\r
+  {   \r
+    /* Request Wait For Interrupt */\r
+    __WFI();\r
+  }\r
+  else\r
+  {\r
+    /* Request Wait For Event */\r
+    __WFE();\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  Enters STOP mode.\r
+  * @param  PWR_Regulator: specifies the regulator state in STOP mode.\r
+  *   This parameter can be one of the following values:\r
+  *     @arg PWR_Regulator_ON: STOP mode with regulator ON\r
+  *     @arg PWR_Regulator_LowPower: STOP mode with regulator in low power mode\r
+  * @param  PWR_STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction.\r
+  *   This parameter can be one of the following values:\r
+  *     @arg PWR_STOPEntry_WFI: enter STOP mode with WFI instruction\r
+  *     @arg PWR_STOPEntry_WFE: enter STOP mode with WFE instruction\r
+  * @retval None\r
+  */\r
+void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry)\r
+{\r
+  uint32_t tmpreg = 0;\r
+  \r
+  /* Check the parameters */\r
+  assert_param(IS_PWR_REGULATOR(PWR_Regulator));\r
+  assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry));\r
+  \r
+  /* Select the regulator state in STOP mode ---------------------------------*/\r
+  tmpreg = PWR->CR;\r
+  /* Clear PDDS and LPDSR bits */\r
+  tmpreg &= CR_DS_MASK;\r
+  \r
+  /* Set LPDSR bit according to PWR_Regulator value */\r
+  tmpreg |= PWR_Regulator;\r
+  \r
+  /* Store the new value */\r
+  PWR->CR = tmpreg;\r
+  \r
+  /* Set SLEEPDEEP bit of Cortex System Control Register */\r
+  SCB->SCR |= SCB_SCR_SLEEPDEEP;\r
+  \r
+  /* Select STOP mode entry --------------------------------------------------*/\r
+  if(PWR_STOPEntry == PWR_STOPEntry_WFI)\r
+  {   \r
+    /* Request Wait For Interrupt */\r
+    __WFI();\r
+  }\r
+  else\r
+  {\r
+    /* Request Wait For Event */\r
+    __WFE();\r
+  }\r
+  /* Reset SLEEPDEEP bit of Cortex System Control Register */\r
+  SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP);  \r
+}\r
+\r
+/**\r
+  * @brief  Enters STANDBY mode.\r
+  * @param  None\r
+  * @retval None\r
+  */\r
+void PWR_EnterSTANDBYMode(void)\r
+{\r
+  /* Clear Wake-up flag */\r
+  PWR->CR |= PWR_CR_CWUF;\r
+  \r
+  /* Select STANDBY mode */\r
+  PWR->CR |= PWR_CR_PDDS;\r
+  \r
+  /* Set SLEEPDEEP bit of Cortex System Control Register */\r
+  SCB->SCR |= SCB_SCR_SLEEPDEEP;\r
+  \r
+/* This option is used to ensure that store operations are completed */\r
+#if defined ( __CC_ARM   )\r
+  __force_stores();\r
+#endif\r
+  /* Request Wait For Interrupt */\r
+  __WFI();\r
+}\r
+\r
+/**\r
+  * @brief  Checks whether the specified PWR flag is set or not.\r
+  * @param  PWR_FLAG: specifies the flag to check.\r
+  *   This parameter can be one of the following values:\r
+  *     @arg PWR_FLAG_WU: Wake Up flag\r
+  *     @arg PWR_FLAG_SB: StandBy flag\r
+  *     @arg PWR_FLAG_PVDO: PVD Output\r
+  *     @arg PWR_FLAG_VREFINTRDY: Internal Voltage Reference Ready flag\r
+  *     @arg PWR_FLAG_VOS: Voltage Scaling select flag\r
+  *     @arg PWR_FLAG_REGLP: Regulator LP flag        \r
+  * @retval The new state of PWR_FLAG (SET or RESET).\r
+  */\r
+FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG)\r
+{\r
+  FlagStatus bitstatus = RESET;\r
+  /* Check the parameters */\r
+  assert_param(IS_PWR_GET_FLAG(PWR_FLAG));\r
+  \r
+  if ((PWR->CSR & PWR_FLAG) != (uint32_t)RESET)\r
+  {\r
+    bitstatus = SET;\r
+  }\r
+  else\r
+  {\r
+    bitstatus = RESET;\r
+  }\r
+  /* Return the flag status */\r
+  return bitstatus;\r
+}\r
+\r
+/**\r
+  * @brief  Clears the PWR's pending flags.\r
+  * @param  PWR_FLAG: specifies the flag to clear.\r
+  *   This parameter can be one of the following values:\r
+  *     @arg PWR_FLAG_WU: Wake Up flag\r
+  *     @arg PWR_FLAG_SB: StandBy flag\r
+  * @retval None\r
+  */\r
+void PWR_ClearFlag(uint32_t PWR_FLAG)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_PWR_CLEAR_FLAG(PWR_FLAG));\r
+         \r
+  PWR->CR |=  PWR_FLAG << 2;\r
+}\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r

diff --git a/Demo/CORTEX_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_rcc.c b/Demo/CORTEX_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_rcc.c
new file mode 100644 (file)
index 0000000..f7bdb49
--- /dev/null
+++ b/Demo/CORTEX_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_rcc.c
@@ -0,0 +1,1225 @@
+/**\r
+  ******************************************************************************\r
+  * @file    stm32l1xx_rcc.c\r
+  * @author  MCD Application Team\r
+  * @version V1.0.0RC1\r
+  * @date    07/02/2010\r
+  * @brief   This file provides all the RCC firmware functions.\r
+  ******************************************************************************\r
+  * @copy\r
+  *\r
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+  *\r
+  * <h2><center>&copy; COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+  */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx_rcc.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+  * @{\r
+  */\r
+\r
+/** @defgroup RCC \r
+  * @brief RCC driver modules\r
+  * @{\r
+  */ \r
+\r
+/** @defgroup RCC_Private_TypesDefinitions\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup RCC_Private_Defines\r
+  * @{\r
+  */\r
+\r
+/* ------------ RCC registers bit address in the alias region ----------- */\r
+#define RCC_OFFSET                (RCC_BASE - PERIPH_BASE)\r
+\r
+/* --- CR Register ---*/\r
+\r
+/* Alias word address of HSION bit */\r
+#define CR_OFFSET                 (RCC_OFFSET + 0x00)\r
+#define HSION_BitNumber           0x00\r
+#define CR_HSION_BB               (PERIPH_BB_BASE + (CR_OFFSET * 32) + (HSION_BitNumber * 4))\r
+\r
+/* Alias word address of MSION bit */\r
+#define MSION_BitNumber           0x08\r
+#define CR_MSION_BB               (PERIPH_BB_BASE + (CR_OFFSET * 32) + (MSION_BitNumber * 4))\r
+\r
+/* Alias word address of PLLON bit */\r
+#define PLLON_BitNumber           0x18\r
+#define CR_PLLON_BB               (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLON_BitNumber * 4))\r
+\r
+/* Alias word address of CSSON bit */\r
+#define CSSON_BitNumber           0x1C\r
+#define CR_CSSON_BB               (PERIPH_BB_BASE + (CR_OFFSET * 32) + (CSSON_BitNumber * 4))\r
+\r
+/* --- CSR Register ---*/\r
+\r
+/* Alias word address of LSION bit */\r
+#define CSR_OFFSET                (RCC_OFFSET + 0x34)\r
+#define LSION_BitNumber           0x00\r
+#define CSR_LSION_BB              (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BitNumber * 4))\r
+\r
+/* Alias word address of RTCEN bit */\r
+#define RTCEN_BitNumber           0x16\r
+#define CSR_RTCEN_BB              (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (RTCEN_BitNumber * 4))\r
+\r
+/* Alias word address of RTCRST bit */\r
+#define RTCRST_BitNumber          0x17\r
+#define CSR_RTCRST_BB             (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (RTCRST_BitNumber * 4))\r
+\r
+\r
+/* ---------------------- RCC registers mask -------------------------------- */\r
+/* RCC Flag Mask */\r
+#define FLAG_MASK                 ((uint8_t)0x1F)\r
+\r
+/* CR register byte 3 (Bits[23:16]) base address */\r
+#define CR_BYTE3_ADDRESS          ((uint32_t)0x40023802)\r
+\r
+/* ICSCR register byte 4 (Bits[31:24]) base address */\r
+#define ICSCR_BYTE4_ADDRESS       ((uint32_t)0x40023807)\r
+\r
+/* CFGR register byte 3 (Bits[23:16]) base address */\r
+#define CFGR_BYTE3_ADDRESS        ((uint32_t)0x4002380A)\r
+\r
+/* CFGR register byte 4 (Bits[31:24]) base address */\r
+#define CFGR_BYTE4_ADDRESS        ((uint32_t)0x4002380B)\r
+\r
+/* CIR register byte 2 (Bits[15:8]) base address */\r
+#define CIR_BYTE2_ADDRESS         ((uint32_t)0x4002380D)\r
+\r
+/* CIR register byte 3 (Bits[23:16]) base address */\r
+#define CIR_BYTE3_ADDRESS         ((uint32_t)0x4002380E)\r
+\r
+/* CSR register byte 2 (Bits[15:8]) base address */\r
+#define CSR_BYTE2_ADDRESS         ((uint32_t)0x40023835)\r
+\r
+/**\r
+  * @}\r
+  */ \r
+\r
+/** @defgroup RCC_Private_Macros\r
+  * @{\r
+  */ \r
+\r
+/**\r
+  * @}\r
+  */ \r
+\r
+/** @defgroup RCC_Private_Variables\r
+  * @{\r
+  */ \r
+\r
+static __I uint8_t PLLMulTable[9] = {3, 4, 6, 8, 12, 16, 24, 32, 48};\r
+static __I uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};\r
+static __I uint8_t MSITable[7] = {0, 0, 0, 0, 1, 2, 4};\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup RCC_Private_FunctionPrototypes\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup RCC_Private_Functions\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @brief  Resets the RCC clock configuration to the default reset state.\r
+  * @param  None\r
+  * @retval None\r
+  */\r
+void RCC_DeInit(void)\r
+{\r
+  \r
+  /* Set MSION bit */\r
+  RCC->CR |= (uint32_t)0x00000100;\r
+\r
+  /* Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], MCOSEL[2:0] and MCOPRE[2:0] bits */\r
+  RCC->CFGR &= (uint32_t)0x88FFC00C;\r
+  \r
+  /* Reset HSION, HSEON, CSSON and PLLON bits */\r
+  RCC->CR &= (uint32_t)0xEEFEFFFE;\r
+\r
+  /* Reset HSEBYP bit */\r
+  RCC->CR &= (uint32_t)0xFFFBFFFF;\r
+\r
+  /* Reset PLLSRC, PLLMUL[3:0] and PLLDIV[1:0] bits */\r
+  RCC->CFGR &= (uint32_t)0xFF02FFFF;\r
+\r
+  /* Disable all interrupts */\r
+  RCC->CIR = 0x00000000;\r
+}\r
+\r
+/**\r
+  * @brief  Configures the External High Speed oscillator (HSE).\r
+  * @note   HSE can not be stopped if it is used directly or through the PLL as system clock.\r
+  * @param RCC_HSE: specifies the new state of the HSE.\r
+  *   This parameter can be one of the following values:\r
+  *     @arg RCC_HSE_OFF: HSE oscillator OFF\r
+  *     @arg RCC_HSE_ON: HSE oscillator ON\r
+  *     @arg RCC_HSE_Bypass: HSE oscillator bypassed with external clock\r
+  * @retval None\r
+  */\r
+void RCC_HSEConfig(uint8_t RCC_HSE)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_RCC_HSE(RCC_HSE));\r
+\r
+  /* Reset HSEON and HSEBYP bits before configuring the HSE ------------------*/\r
+  *(__IO uint8_t *) CR_BYTE3_ADDRESS = RCC_HSE_OFF;\r
+\r
+  /* Set the new HSE configuration -------------------------------------------*/\r
+  *(__IO uint8_t *) CR_BYTE3_ADDRESS = RCC_HSE;\r
+\r
+}\r
+\r
+/**\r
+  * @brief  Waits for HSE start-up.\r
+  * @param  None\r
+  * @retval An ErrorStatus enumuration value:\r
+  *          - SUCCESS: HSE oscillator is stable and ready to use\r
+  *          - ERROR: HSE oscillator not yet ready\r
+  */\r
+ErrorStatus RCC_WaitForHSEStartUp(void)\r
+{\r
+  __IO uint32_t StartUpCounter = 0;\r
+  ErrorStatus status = ERROR;\r
+  FlagStatus HSEStatus = RESET;\r
+  \r
+  /* Wait till HSE is ready and if Time out is reached exit */\r
+  do\r
+  {\r
+    HSEStatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY);\r
+    StartUpCounter++;  \r
+  } while((StartUpCounter != HSE_STARTUP_TIMEOUT) && (HSEStatus == RESET));\r
+  \r
+  if (RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET)\r
+  {\r
+    status = SUCCESS;\r
+  }\r
+  else\r
+  {\r
+    status = ERROR;\r
+  }  \r
+  return (status);\r
+}\r
+\r
+/**\r
+  * @brief  Adjusts the Internal High Speed oscillator (HSI) calibration value.\r
+  * @param  HSICalibrationValue: specifies the HSI calibration trimming value.\r
+  *   This parameter must be a number between 0 and 0x1F.\r
+  * @retval None\r
+  */\r
+void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue)\r
+{\r
+  uint32_t tmpreg = 0;\r
+  \r
+  /* Check the parameters */\r
+  assert_param(IS_RCC_HSI_CALIBRATION_VALUE(HSICalibrationValue));\r
+  \r
+  tmpreg = RCC->ICSCR;\r
+  \r
+  /* Clear HSITRIM[4:0] bits */\r
+  tmpreg &= ~RCC_ICSCR_HSITRIM;\r
+  \r
+  /* Set the HSITRIM[4:0] bits according to HSICalibrationValue value */\r
+  tmpreg |= (uint32_t)HSICalibrationValue << 8;\r
+\r
+  /* Store the new value */\r
+  RCC->ICSCR = tmpreg;\r
+}\r
+\r
+/**\r
+  * @brief  Adjusts the Internal Multi Speed oscillator (MSI) calibration value.\r
+  * @param  MSICalibrationValue: specifies the MSI calibration trimming value.\r
+  *   This parameter must be a number between 0 and 0xFF.\r
+  * @retval None\r
+  */\r
+void RCC_AdjustMSICalibrationValue(uint8_t MSICalibrationValue)\r
+{\r
+  \r
+  /* Check the parameters */\r
+  assert_param(IS_RCC_MSI_CALIBRATION_VALUE(MSICalibrationValue));\r
+\r
+  *(__IO uint8_t *) ICSCR_BYTE4_ADDRESS = MSICalibrationValue;  \r
+}\r
+\r
+/**\r
+  * @brief  Configures the Internal Multi Speed oscillator (MSI) clock range.\r
+  * @param  RCC_MSIRange: specifies the MSI Clcok range.\r
+  *   This parameter must be one of the following values:\r
+  *     @arg RCC_MSIRange_64KHz:  MSI clock is around 64 KHz\r
+  *     @arg RCC_MSIRange_128KHz: MSI clock is around 128 KHz\r
+  *     @arg RCC_MSIRange_256KHz: MSI clock is around 256 KHz\r
+  *     @arg RCC_MSIRange_512KHz: MSI clock is around 512 KHz\r
+  *     @arg RCC_MSIRange_1MHz:   MSI clock is around 1 MHz\r
+  *     @arg RCC_MSIRange_2MHz:   MSI clock is around 2 MHz\r
+  *     @arg RCC_MSIRange_4MHz:   MSI clock is around 4 MHz             \r
+  * @retval None\r
+  */\r
+void RCC_MSIRangeConfig(uint32_t RCC_MSIRange)\r
+{\r
+  uint32_t tmpreg = 0;\r
+  \r
+  /* Check the parameters */\r
+  assert_param(IS_RCC_MSI_CLOCK_RANGE(RCC_MSIRange));\r
+  \r
+  tmpreg = RCC->ICSCR;\r
+  \r
+  /* Clear MSIRANGE[2:0] bits */\r
+  tmpreg &= ~RCC_ICSCR_MSIRANGE;\r
+  \r
+  /* Set the MSIRANGE[2:0] bits according to RCC_MSIRange value */\r
+  tmpreg |= (uint32_t)RCC_MSIRange;\r
+\r
+  /* Store the new value */\r
+  RCC->ICSCR = tmpreg;\r
+}\r
+\r
+/**\r
+  * @brief  Enables or disables the Internal Multi Speed oscillator (MSI).\r
+  * @note   MSI can not be stopped if it is used directly as system clock.\r
+  * @param  NewState: new state of the MSI.\r
+  *   This parameter can be: ENABLE or DISABLE.\r
+  * @retval None\r
+  */\r
+void RCC_MSICmd(FunctionalState NewState)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+  \r
+  *(__IO uint32_t *) CR_MSION_BB = (uint32_t)NewState;\r
+}\r
+\r
+/**\r
+  * @brief  Enables or disables the Internal High Speed oscillator (HSI).\r
+  * @note   HSI can not be stopped if it is used directly or through the PLL as system clock.\r
+  * @param  NewState: new state of the HSI.\r
+  *   This parameter can be: ENABLE or DISABLE.\r
+  * @retval None\r
+  */\r
+void RCC_HSICmd(FunctionalState NewState)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+  \r
+  *(__IO uint32_t *) CR_HSION_BB = (uint32_t)NewState;\r
+}\r
+\r
+/**\r
+  * @brief  Configures the PLL clock source and multiplication factor.\r
+  * @note   This function must be used only when the PLL is disabled.\r
+  * @param  RCC_PLLSource: specifies the PLL entry clock source.\r
+  *   This parameter can be one of the following values:\r
+  *     @arg RCC_PLLSource_HSI: HSI oscillator clock selected as PLL clock entry\r
+  *     @arg RCC_PLLSource_HSE: HSE oscillator clock selected as PLL clock entry\r
+  * @param  RCC_PLLMul: specifies the PLL multiplication factor.\r
+  *   This parameter can be:\r
+  *     @arg RCC_PLLMul_3: PLL Clock entry multiplied by 3\r
+  *     @arg RCC_PLLMul_4: PLL Clock entry multiplied by 4\r
+  *     @arg RCC_PLLMul_6: PLL Clock entry multiplied by 6\r
+  *     @arg RCC_PLLMul_8: PLL Clock entry multiplied by 8\r
+  *     @arg RCC_PLLMul_12: PLL Clock entry multiplied by 12\r
+  *     @arg RCC_PLLMul_16: PLL Clock entry multiplied by 16  \r
+  *     @arg RCC_PLLMul_24: PLL Clock entry multiplied by 24\r
+  *     @arg RCC_PLLMul_32: PLL Clock entry multiplied by 32\r
+  *     @arg RCC_PLLMul_48: PLL Clock entry multiplied by 48             \r
+  * @param  RCC_PLLDiv: specifies the PLL division factor.\r
+  *   This parameter can be:\r
+  *     @arg RCC_PLLDiv_2: PLL Clock output divided by 2  \r
+  *     @arg RCC_PLLDiv_3: PLL Clock output divided by 3         \r
+  *     @arg RCC_PLLDiv_4: PLL Clock output divided by 4   \r
+  * @retval None\r
+  */\r
+void RCC_PLLConfig(uint8_t RCC_PLLSource, uint8_t RCC_PLLMul, uint8_t RCC_PLLDiv)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_RCC_PLL_SOURCE(RCC_PLLSource));\r
+  assert_param(IS_RCC_PLL_MUL(RCC_PLLMul));\r
+  assert_param(IS_RCC_PLL_DIV(RCC_PLLDiv));\r
+  \r
+  *(__IO uint8_t *) CFGR_BYTE3_ADDRESS = (uint8_t)(RCC_PLLSource | ((uint8_t)(RCC_PLLMul | (uint8_t)(RCC_PLLDiv))));\r
+}\r
+\r
+/**\r
+  * @brief  Enables or disables the PLL.\r
+  * @note   The PLL can not be disabled if it is used as system clock.\r
+  * @param  NewState: new state of the PLL.\r
+  *   This parameter can be: ENABLE or DISABLE.\r
+  * @retval None\r
+  */\r
+void RCC_PLLCmd(FunctionalState NewState)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+  \r
+  *(__IO uint32_t *) CR_PLLON_BB = (uint32_t)NewState;\r
+}\r
+\r
+/**\r
+  * @brief  Configures the system clock (SYSCLK).\r
+  * @param  RCC_SYSCLKSource: specifies the clock source used as system clock. \r
+  *   This parameter can be one of the following values:\r
+  *     @arg RCC_SYSCLKSource_MSI:    MSI selected as system clock\r
+  *     @arg RCC_SYSCLKSource_HSI:    HSI selected as system clock\r
+  *     @arg RCC_SYSCLKSource_HSE:    HSE selected as system clock\r
+  *     @arg RCC_SYSCLKSource_PLLCLK: PLL selected as system clock\r
+  * @retval None\r
+  */\r
+void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource)\r
+{\r
+  uint32_t tmpreg = 0;\r
+  \r
+  /* Check the parameters */\r
+  assert_param(IS_RCC_SYSCLK_SOURCE(RCC_SYSCLKSource));\r
+  \r
+  tmpreg = RCC->CFGR;\r
+  \r
+  /* Clear SW[1:0] bits */\r
+  tmpreg &= ~RCC_CFGR_SW;\r
+  \r
+  /* Set SW[1:0] bits according to RCC_SYSCLKSource value */\r
+  tmpreg |= RCC_SYSCLKSource;\r
+  \r
+  /* Store the new value */\r
+  RCC->CFGR = tmpreg;\r
+}\r
+\r
+/**\r
+  * @brief  Returns the clock source used as system clock.\r
+  * @param  None\r
+  * @retval The clock source used as system clock. The returned value can be one \r
+  *         of the following values:\r
+  *              - 0x00: MSI used as system clock\r
+  *              - 0x04: HSI used as system clock  \r
+  *              - 0x08: HSE used as system clock\r
+  *              - 0x0C: PLL used as system clock\r
+  */\r
+uint8_t RCC_GetSYSCLKSource(void)\r
+{\r
+  return ((uint8_t)(RCC->CFGR & RCC_CFGR_SWS));\r
+}\r
+\r
+/**\r
+  * @brief  Configures the AHB clock (HCLK).\r
+  * @param  RCC_SYSCLK: defines the AHB clock divider. This clock is derived from \r
+  *                     the system clock (SYSCLK).\r
+  *   This parameter can be one of the following values:\r
+  *     @arg RCC_SYSCLK_Div1:   AHB clock = SYSCLK\r
+  *     @arg RCC_SYSCLK_Div2:   AHB clock = SYSCLK/2\r
+  *     @arg RCC_SYSCLK_Div4:   AHB clock = SYSCLK/4\r
+  *     @arg RCC_SYSCLK_Div8:   AHB clock = SYSCLK/8\r
+  *     @arg RCC_SYSCLK_Div16:  AHB clock = SYSCLK/16\r
+  *     @arg RCC_SYSCLK_Div64:  AHB clock = SYSCLK/64\r
+  *     @arg RCC_SYSCLK_Div128: AHB clock = SYSCLK/128\r
+  *     @arg RCC_SYSCLK_Div256: AHB clock = SYSCLK/256\r
+  *     @arg RCC_SYSCLK_Div512: AHB clock = SYSCLK/512\r
+  * @retval None\r
+  */\r
+void RCC_HCLKConfig(uint32_t RCC_SYSCLK)\r
+{\r
+  uint32_t tmpreg = 0;\r
+  \r
+  /* Check the parameters */\r
+  assert_param(IS_RCC_HCLK(RCC_SYSCLK));\r
+  \r
+  tmpreg = RCC->CFGR;\r
+  \r
+  /* Clear HPRE[3:0] bits */\r
+  tmpreg &= ~RCC_CFGR_HPRE;\r
+  \r
+  /* Set HPRE[3:0] bits according to RCC_SYSCLK value */\r
+  tmpreg |= RCC_SYSCLK;\r
+  \r
+  /* Store the new value */\r
+  RCC->CFGR = tmpreg;\r
+}\r
+\r
+/**\r
+  * @brief  Configures the Low Speed APB clock (PCLK1).\r
+  * @param  RCC_HCLK: defines the APB1 clock divider. This clock is derived from \r
+  *                   the AHB clock (HCLK).\r
+  *   This parameter can be one of the following values:\r
+  *     @arg RCC_HCLK_Div1:  APB1 clock = HCLK\r
+  *     @arg RCC_HCLK_Div2:  APB1 clock = HCLK/2\r
+  *     @arg RCC_HCLK_Div4:  APB1 clock = HCLK/4\r
+  *     @arg RCC_HCLK_Div8:  APB1 clock = HCLK/8\r
+  *     @arg RCC_HCLK_Div16: APB1 clock = HCLK/16\r
+  * @retval None\r
+  */\r
+void RCC_PCLK1Config(uint32_t RCC_HCLK)\r
+{\r
+  uint32_t tmpreg = 0;\r
+  \r
+  /* Check the parameters */\r
+  assert_param(IS_RCC_PCLK(RCC_HCLK));\r
+  \r
+  tmpreg = RCC->CFGR;\r
+  \r
+  /* Clear PPRE1[2:0] bits */\r
+  tmpreg &= ~RCC_CFGR_PPRE1;\r
+  \r
+  /* Set PPRE1[2:0] bits according to RCC_HCLK value */\r
+  tmpreg |= RCC_HCLK;\r
+  \r
+  /* Store the new value */\r
+  RCC->CFGR = tmpreg;\r
+}\r
+\r
+/**\r
+  * @brief  Configures the High Speed APB clock (PCLK2).\r
+  * @param  RCC_HCLK: defines the APB2 clock divider. This clock is derived from \r
+  *                   the AHB clock (HCLK).\r
+  *   This parameter can be one of the following values:\r
+  *     @arg RCC_HCLK_Div1:  APB2 clock = HCLK\r
+  *     @arg RCC_HCLK_Div2:  APB2 clock = HCLK/2\r
+  *     @arg RCC_HCLK_Div4:  APB2 clock = HCLK/4\r
+  *     @arg RCC_HCLK_Div8:  APB2 clock = HCLK/8\r
+  *     @arg RCC_HCLK_Div16: APB2 clock = HCLK/16\r
+  * @retval None\r
+  */\r
+void RCC_PCLK2Config(uint32_t RCC_HCLK)\r
+{\r
+  uint32_t tmpreg = 0;\r
+  \r
+  /* Check the parameters */\r
+  assert_param(IS_RCC_PCLK(RCC_HCLK));\r
+  \r
+  tmpreg = RCC->CFGR;\r
+  \r
+  /* Clear PPRE2[2:0] bits */\r
+  tmpreg &= ~RCC_CFGR_PPRE2;\r
+  \r
+  /* Set PPRE2[2:0] bits according to RCC_HCLK value */\r
+  tmpreg |= RCC_HCLK << 3;\r
+  \r
+  /* Store the new value */\r
+  RCC->CFGR = tmpreg;\r
+}\r
+\r
+/**\r
+  * @brief  Enables or disables the specified RCC interrupts.\r
+  * @param  RCC_IT: specifies the RCC interrupt sources to be enabled or disabled.\r
+  *   This parameter can be any combination of the following values:\r
+  *     @arg RCC_IT_LSIRDY: LSI ready interrupt\r
+  *     @arg RCC_IT_LSERDY: LSE ready interrupt\r
+  *     @arg RCC_IT_HSIRDY: HSI ready interrupt\r
+  *     @arg RCC_IT_HSERDY: HSE ready interrupt\r
+  *     @arg RCC_IT_PLLRDY: PLL ready interrupt\r
+  *     @arg RCC_IT_MSIRDY: MSI ready interrupt\r
+  * @param  NewState: new state of the specified RCC interrupts.\r
+  *   This parameter can be: ENABLE or DISABLE.\r
+  * @retval None\r
+  */\r
+void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_RCC_IT(RCC_IT));\r
+  assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+  \r
+  if (NewState != DISABLE)\r
+  {\r
+    /* Perform Byte access to RCC_CIR[12:8] bits to enable the selected interrupts */\r
+    *(__IO uint8_t *) CIR_BYTE2_ADDRESS |= RCC_IT;\r
+  }\r
+  else\r
+  {\r
+    /* Perform Byte access to RCC_CIR[12:8] bits to disable the selected interrupts */\r
+    *(__IO uint8_t *) CIR_BYTE2_ADDRESS &= (uint8_t)~RCC_IT;\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  Configures the External Low Speed oscillator (LSE).\r
+  * @param  RCC_LSE: specifies the new state of the LSE.\r
+  *   This parameter can be one of the following values:\r
+  *     @arg RCC_LSE_OFF: LSE oscillator OFF\r
+  *     @arg RCC_LSE_ON: LSE oscillator ON\r
+  *     @arg RCC_LSE_Bypass: LSE oscillator bypassed with external clock\r
+  * @retval None\r
+  */\r
+void RCC_LSEConfig(uint8_t RCC_LSE)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_RCC_LSE(RCC_LSE));\r
+  \r
+  /* Reset LSEON and LSEBYP bits before configuring the LSE ------------------*/\r
+  *(__IO uint8_t *) CSR_BYTE2_ADDRESS = RCC_LSE_OFF;\r
+\r
+  /* Set the new LSE configuration -------------------------------------------*/\r
+  *(__IO uint8_t *) CSR_BYTE2_ADDRESS = RCC_LSE;  \r
+}\r
+\r
+/**\r
+  * @brief  Enables or disables the Internal Low Speed oscillator (LSI).\r
+  * @note   LSI can not be disabled if the IWDG is running.\r
+  * @param  NewState: new state of the LSI.\r
+  *   This parameter can be: ENABLE or DISABLE.\r
+  * @retval None\r
+  */\r
+void RCC_LSICmd(FunctionalState NewState)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+  \r
+  *(__IO uint32_t *) CSR_LSION_BB = (uint32_t)NewState;\r
+}\r
+\r
+/**\r
+  * @brief  Configures the RTC and LCD clock (RTCCLK / LCDCLK).\r
+  * @note   \r
+  *   - Once the RTC clock is selected it can't be changed unless the RTC is\r
+  *     reset using RCC_RTCResetCmd function.\r
+  *   - This RTC clock (RTCCLK) is used to clock the LCD (LCDCLK).  \r
+  * @param  RCC_RTCCLKSource: specifies the RTC clock source.\r
+  *   This parameter can be one of the following values:\r
+  *     @arg RCC_RTCCLKSource_LSE: LSE selected as RTC clock\r
+  *     @arg RCC_RTCCLKSource_LSI: LSI selected as RTC clock\r
+  *     @arg RCC_RTCCLKSource_HSE_Div2: HSE divided by 2 selected as RTC clock\r
+  *     @arg RCC_RTCCLKSource_HSE_Div4: HSE divided by 4 selected as RTC clock\r
+  *     @arg RCC_RTCCLKSource_HSE_Div8: HSE divided by 8 selected as RTC clock\r
+  *     @arg RCC_RTCCLKSource_HSE_Div16: HSE divided by 16 selected as RTC clock      \r
+  * @retval None\r
+  */\r
+void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource)\r
+{\r
+  uint32_t     tmpreg = 0;\r
+\r
+  /* Check the parameters */\r
+  assert_param(IS_RCC_RTCCLK_SOURCE(RCC_RTCCLKSource));\r
+  \r
+  if ((RCC_RTCCLKSource & RCC_CSR_RTCSEL_HSE) == RCC_CSR_RTCSEL_HSE)\r
+  { \r
+    /* If HSE is selected as RTC clock source, configure HSE division factor for RTC clock */\r
+    tmpreg = RCC->CR;\r
+\r
+    /* Clear RTCPRE[1:0] bits */\r
+    tmpreg &= ~RCC_CR_RTCPRE;\r
+\r
+    /* Configure HSE division factor for RTC clock */\r
+    tmpreg |= (RCC_RTCCLKSource & RCC_CR_RTCPRE);\r
+\r
+    /* Store the new value */\r
+    RCC->CR = tmpreg;\r
+  }\r
+         \r
+  RCC->CSR &= ~RCC_CSR_RTCSEL;\r
+  \r
+  /* Select the RTC clock source */\r
+  RCC->CSR |= (RCC_RTCCLKSource & RCC_CSR_RTCSEL);\r
+}\r
+\r
+/**\r
+  * @brief  Enables or disables the RTC clock.\r
+  * @note   This function must be used only after the RTC clock was selected using the \r
+  *   RCC_RTCCLKConfig function.\r
+  * @param  NewState: new state of the RTC clock.\r
+  *   This parameter can be: ENABLE or DISABLE.\r
+  * @retval None\r
+  */\r
+void RCC_RTCCLKCmd(FunctionalState NewState)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+  \r
+  *(__IO uint32_t *) CSR_RTCEN_BB = (uint32_t)NewState;\r
+}\r
+\r
+/**\r
+  * @brief  Forces or releases the RTC peripheral reset.\r
+  * @param  NewState: new state of the RTC reset.\r
+  *   This parameter can be: ENABLE or DISABLE.\r
+  * @retval None\r
+  */\r
+void RCC_RTCResetCmd(FunctionalState NewState)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+  \r
+  *(__IO uint32_t *) CSR_RTCRST_BB = (uint32_t)NewState;\r
+}\r
+\r
+/**\r
+  * @brief  Returns the frequencies of different on chip clocks.\r
+  * @param  RCC_Clocks: pointer to a RCC_ClocksTypeDef structure which will hold \r
+  *   the clocks frequencies.\r
+  * @retval None\r
+  */\r
+void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks)\r
+{\r
+  uint32_t tmp = 0, pllmul = 0, plldiv = 0, pllsource = 0, presc = 0, msirange = 0;\r
+\r
+  /* Get SYSCLK source -------------------------------------------------------*/\r
+  tmp = RCC->CFGR & RCC_CFGR_SWS;\r
+  \r
+  switch (tmp)\r
+  {\r
+    case 0x00:  /* MSI used as system clock */\r
+      msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE ) >> 13;\r
+      RCC_Clocks->SYSCLK_Frequency = (((1 << msirange) * 64000) - (MSITable[msirange] * 24000));\r
+      break;\r
+    case 0x04:  /* HSI used as system clock */\r
+      RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;\r
+      break;\r
+    case 0x08:  /* HSE used as system clock */\r
+      RCC_Clocks->SYSCLK_Frequency = HSE_VALUE;\r
+      break;\r
+    case 0x0C:  /* PLL used as system clock */\r
+      /* Get PLL clock source and multiplication factor ----------------------*/\r
+      pllmul = RCC->CFGR & RCC_CFGR_PLLMUL;\r
+      plldiv = RCC->CFGR & RCC_CFGR_PLLDIV;\r
+      pllmul = PLLMulTable[(pllmul >> 18)];\r
+      plldiv = (plldiv >> 22) + 1;\r
+      \r
+      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;\r
+\r
+      if (pllsource == 0x00)\r
+      {\r
+        /* HSI oscillator clock selected as PLL clock entry */\r
+        RCC_Clocks->SYSCLK_Frequency = (((HSI_VALUE) * pllmul) / plldiv);\r
+      }\r
+      else\r
+      {\r
+        /* HSE selected as PLL clock entry */\r
+        RCC_Clocks->SYSCLK_Frequency = (((HSE_VALUE) * pllmul) / plldiv);\r
+      }\r
+      break;\r
+    default:\r
+      RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;\r
+      break;\r
+  }\r
+  /* Compute HCLK, PCLK1, PCLK2 and ADCCLK clocks frequencies ----------------*/\r
+  /* Get HCLK prescaler */\r
+  tmp = RCC->CFGR & RCC_CFGR_HPRE;\r
+  tmp = tmp >> 4;\r
+  presc = APBAHBPrescTable[tmp]; \r
+  /* HCLK clock frequency */\r
+  RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc;\r
+\r
+  /* Get PCLK1 prescaler */\r
+  tmp = RCC->CFGR & RCC_CFGR_PPRE1;\r
+  tmp = tmp >> 8;\r
+  presc = APBAHBPrescTable[tmp];\r
+  /* PCLK1 clock frequency */\r
+  RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc;\r
+\r
+  /* Get PCLK2 prescaler */\r
+  tmp = RCC->CFGR & RCC_CFGR_PPRE2;\r
+  tmp = tmp >> 11;\r
+  presc = APBAHBPrescTable[tmp];\r
+  /* PCLK2 clock frequency */\r
+  RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> presc;\r
+}\r
+\r
+/**\r
+  * @brief  Enables or disables the AHB peripheral clock.\r
+  * @param  RCC_AHBPeriph: specifies the AHB peripheral to gates its clock.\r
+  *   This parameter can be any combination of the following values:\r
+  *     @arg RCC_AHBPeriph_GPIOA\r
+  *     @arg RCC_AHBPeriph_GPIOB\r
+  *     @arg RCC_AHBPeriph_GPIOC  \r
+  *     @arg RCC_AHBPeriph_GPIOD\r
+  *     @arg RCC_AHBPeriph_GPIOE\r
+  *     @arg RCC_AHBPeriph_GPIOH\r
+  *     @arg RCC_AHBPeriph_CRC\r
+  *     @arg RCC_AHBPeriph_FLITF (has effect only when the Flash memory is in power down mode)  \r
+  *     @arg RCC_AHBPeriph_DMA1\r
+  * @param  NewState: new state of the specified peripheral clock.\r
+  *   This parameter can be: ENABLE or DISABLE.\r
+  * @retval None\r
+  */\r
+void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_RCC_AHB_PERIPH(RCC_AHBPeriph));\r
+  assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+  \r
+  if (NewState != DISABLE)\r
+  {\r
+    RCC->AHBENR |= RCC_AHBPeriph;\r
+  }\r
+  else\r
+  {\r
+    RCC->AHBENR &= ~RCC_AHBPeriph;\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  Enables or disables the High Speed APB (APB2) peripheral clock.\r
+  * @param  RCC_APB2Periph: specifies the APB2 peripheral to gates its clock.\r
+  *   This parameter can be any combination of the following values:\r
+  *     @arg RCC_APB2Periph_SYSCFG\r
+  *     @arg RCC_APB2Periph_TIM9\r
+  *     @arg RCC_APB2Periph_TIM10\r
+  *     @arg RCC_APB2Periph_TIM11\r
+  *     @arg RCC_APB2Periph_ADC1\r
+  *     @arg RCC_APB2Periph_SPI1\r
+  *     @arg RCC_APB2Periph_USART1            \r
+  * @param  NewState: new state of the specified peripheral clock.\r
+  *   This parameter can be: ENABLE or DISABLE.\r
+  * @retval None\r
+  */\r
+void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));\r
+  assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+  if (NewState != DISABLE)\r
+  {\r
+    RCC->APB2ENR |= RCC_APB2Periph;\r
+  }\r
+  else\r
+  {\r
+    RCC->APB2ENR &= ~RCC_APB2Periph;\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  Enables or disables the Low Speed APB (APB1) peripheral clock.\r
+  * @param  RCC_APB1Periph: specifies the APB1 peripheral to gates its clock.\r
+  *   This parameter can be any combination of the following values:\r
+  *     @arg RCC_APB1Periph_TIM2\r
+  *     @arg RCC_APB1Periph_TIM3\r
+  *     @arg RCC_APB1Periph_TIM4\r
+  *     @arg RCC_APB1Periph_TIM6\r
+  *     @arg RCC_APB1Periph_TIM7\r
+  *     @arg RCC_APB1Periph_LCD\r
+  *     @arg RCC_APB1Periph_WWDG\r
+  *     @arg RCC_APB1Periph_SPI2\r
+  *     @arg RCC_APB1Periph_USART2\r
+  *     @arg RCC_APB1Periph_USART3\r
+  *     @arg RCC_APB1Periph_I2C1\r
+  *     @arg RCC_APB1Periph_I2C2\r
+  *     @arg RCC_APB1Periph_USB\r
+  *     @arg RCC_APB1Periph_PWR\r
+  *     @arg RCC_APB1Periph_DAC\r
+  *     @arg RCC_APB1Periph_COMP                                \r
+  * @param  NewState: new state of the specified peripheral clock.\r
+  *   This parameter can be: ENABLE or DISABLE.\r
+  * @retval None\r
+  */\r
+void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));\r
+  assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+  if (NewState != DISABLE)\r
+  {\r
+    RCC->APB1ENR |= RCC_APB1Periph;\r
+  }\r
+  else\r
+  {\r
+    RCC->APB1ENR &= ~RCC_APB1Periph;\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  Forces or releases AHB peripheral reset.\r
+  * @param  RCC_AHBPeriph: specifies the AHB peripheral to reset.\r
+  *   This parameter can be any combination of the following values:\r
+  *     @arg RCC_AHBPeriph_GPIOA\r
+  *     @arg RCC_AHBPeriph_GPIOB\r
+  *     @arg RCC_AHBPeriph_GPIOC  \r
+  *     @arg RCC_AHBPeriph_GPIOD\r
+  *     @arg RCC_AHBPeriph_GPIOE\r
+  *     @arg RCC_AHBPeriph_GPIOH\r
+  *     @arg RCC_AHBPeriph_CRC\r
+  *     @arg RCC_AHBPeriph_FLITF (has effect only when the Flash memory is in power down mode)  \r
+  *     @arg RCC_AHBPeriph_DMA1   \r
+  * @param  NewState: new state of the specified peripheral reset.\r
+  *   This parameter can be: ENABLE or DISABLE.\r
+  * @retval None\r
+  */\r
+void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_RCC_AHB_PERIPH(RCC_AHBPeriph));\r
+  assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+  if (NewState != DISABLE)\r
+  {\r
+    RCC->AHBRSTR |= RCC_AHBPeriph;\r
+  }\r
+  else\r
+  {\r
+    RCC->AHBRSTR &= ~RCC_AHBPeriph;\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  Forces or releases High Speed APB (APB2) peripheral reset.\r
+  * @param  RCC_APB2Periph: specifies the APB2 peripheral to reset.\r
+  *   This parameter can be any combination of the following values:\r
+  *     @arg RCC_APB2Periph_SYSCFG\r
+  *     @arg RCC_APB2Periph_TIM9\r
+  *     @arg RCC_APB2Periph_TIM10\r
+  *     @arg RCC_APB2Periph_TIM11\r
+  *     @arg RCC_APB2Periph_ADC1\r
+  *     @arg RCC_APB2Periph_SPI1\r
+  *     @arg RCC_APB2Periph_USART1  \r
+  * @param  NewState: new state of the specified peripheral reset.\r
+  *   This parameter can be: ENABLE or DISABLE.\r
+  * @retval None\r
+  */\r
+void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));\r
+  assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+  if (NewState != DISABLE)\r
+  {\r
+    RCC->APB2RSTR |= RCC_APB2Periph;\r
+  }\r
+  else\r
+  {\r
+    RCC->APB2RSTR &= ~RCC_APB2Periph;\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  Forces or releases Low Speed APB (APB1) peripheral reset.\r
+  * @param  RCC_APB1Periph: specifies the APB1 peripheral to reset.\r
+  *   This parameter can be any combination of the following values:\r
+  *     @arg RCC_APB1Periph_TIM2\r
+  *     @arg RCC_APB1Periph_TIM3\r
+  *     @arg RCC_APB1Periph_TIM4\r
+  *     @arg RCC_APB1Periph_TIM6\r
+  *     @arg RCC_APB1Periph_TIM7\r
+  *     @arg RCC_APB1Periph_LCD\r
+  *     @arg RCC_APB1Periph_WWDG\r
+  *     @arg RCC_APB1Periph_SPI2\r
+  *     @arg RCC_APB1Periph_USART2\r
+  *     @arg RCC_APB1Periph_USART3\r
+  *     @arg RCC_APB1Periph_I2C1\r
+  *     @arg RCC_APB1Periph_I2C2\r
+  *     @arg RCC_APB1Periph_USB\r
+  *     @arg RCC_APB1Periph_PWR\r
+  *     @arg RCC_APB1Periph_DAC\r
+  *     @arg RCC_APB1Periph_COMP    \r
+  * @param  NewState: new state of the specified peripheral clock.\r
+  *   This parameter can be: ENABLE or DISABLE.\r
+  * @retval None\r
+  */\r
+void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));\r
+  assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+  if (NewState != DISABLE)\r
+  {\r
+    RCC->APB1RSTR |= RCC_APB1Periph;\r
+  }\r
+  else\r
+  {\r
+    RCC->APB1RSTR &= ~RCC_APB1Periph;\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  Enables or disables the AHB peripheral clock during Low Power (SLEEP) mode.\r
+  * @param  RCC_AHBPeriph: specifies the AHB peripheral to gates its clock.\r
+  *   This parameter can be any combination of the following values:\r
+  *     @arg RCC_AHBPeriph_GPIOA\r
+  *     @arg RCC_AHBPeriph_GPIOB\r
+  *     @arg RCC_AHBPeriph_GPIOC  \r
+  *     @arg RCC_AHBPeriph_GPIOD\r
+  *     @arg RCC_AHBPeriph_GPIOE\r
+  *     @arg RCC_AHBPeriph_GPIOH\r
+  *     @arg RCC_AHBPeriph_CRC\r
+  *     @arg RCC_AHBPeriph_FLITF (has effect only when the Flash memory is in power down mode)  \r
+  *     @arg RCC_AHBPeriph_SRAM     \r
+  *     @arg RCC_AHBPeriph_DMA1\r
+  * @param  NewState: new state of the specified peripheral clock.\r
+  *   This parameter can be: ENABLE or DISABLE.\r
+  * @retval None\r
+  */\r
+void RCC_AHBPeriphClockLPModeCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_RCC_AHB_LPMODE_PERIPH(RCC_AHBPeriph));\r
+  assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+  \r
+  if (NewState != DISABLE)\r
+  {\r
+    RCC->AHBLPENR |= RCC_AHBPeriph;\r
+  }\r
+  else\r
+  {\r
+    RCC->AHBLPENR &= ~RCC_AHBPeriph;\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  Enables or disables the APB2 peripheral clock during Low Power (SLEEP) mode.\r
+  * @param  RCC_APB2Periph: specifies the APB2 peripheral to gates its clock.\r
+  *   This parameter can be any combination of the following values:\r
+  *     @arg RCC_APB2Periph_SYSCFG\r
+  *     @arg RCC_APB2Periph_TIM9\r
+  *     @arg RCC_APB2Periph_TIM10\r
+  *     @arg RCC_APB2Periph_TIM11\r
+  *     @arg RCC_APB2Periph_ADC1\r
+  *     @arg RCC_APB2Periph_SPI1\r
+  *     @arg RCC_APB2Periph_USART1            \r
+  * @param  NewState: new state of the specified peripheral clock.\r
+  *   This parameter can be: ENABLE or DISABLE.\r
+  * @retval None\r
+  */\r
+void RCC_APB2PeriphClockLPModeCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));\r
+  assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+  \r
+  if (NewState != DISABLE)\r
+  {\r
+    RCC->APB2LPENR |= RCC_APB2Periph;\r
+  }\r
+  else\r
+  {\r
+    RCC->APB2LPENR &= ~RCC_APB2Periph;\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  Enables or disables the APB1 peripheral clock during Low Power (SLEEP) mode.\r
+  * @param  RCC_APB1Periph: specifies the APB1 peripheral to gates its clock.\r
+  *   This parameter can be any combination of the following values:\r
+  *     @arg RCC_APB1Periph_TIM2\r
+  *     @arg RCC_APB1Periph_TIM3\r
+  *     @arg RCC_APB1Periph_TIM4\r
+  *     @arg RCC_APB1Periph_TIM6\r
+  *     @arg RCC_APB1Periph_TIM7\r
+  *     @arg RCC_APB1Periph_LCD\r
+  *     @arg RCC_APB1Periph_WWDG\r
+  *     @arg RCC_APB1Periph_SPI2\r
+  *     @arg RCC_APB1Periph_USART2\r
+  *     @arg RCC_APB1Periph_USART3\r
+  *     @arg RCC_APB1Periph_I2C1\r
+  *     @arg RCC_APB1Periph_I2C2\r
+  *     @arg RCC_APB1Periph_USB\r
+  *     @arg RCC_APB1Periph_PWR\r
+  *     @arg RCC_APB1Periph_DAC\r
+  *     @arg RCC_APB1Periph_COMP                                \r
+  * @param  NewState: new state of the specified peripheral clock.\r
+  *   This parameter can be: ENABLE or DISABLE.\r
+  * @retval None\r
+  */\r
+void RCC_APB1PeriphClockLPModeCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));\r
+  assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+  \r
+  if (NewState != DISABLE)\r
+  {\r
+    RCC->APB1LPENR |= RCC_APB1Periph;\r
+  }\r
+  else\r
+  {\r
+    RCC->APB1LPENR &= ~RCC_APB1Periph;\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  Enables or disables the Clock Security System.\r
+  * @param  NewState: new state of the Clock Security System..\r
+  *   This parameter can be: ENABLE or DISABLE.\r
+  * @retval None\r
+  */\r
+void RCC_ClockSecuritySystemCmd(FunctionalState NewState)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+  \r
+  *(__IO uint32_t *) CR_CSSON_BB = (uint32_t)NewState;\r
+}\r
+\r
+/**\r
+  * @brief  Selects the clock source to output on MCO pin.\r
+  * @param  RCC_MCOSource: specifies the clock source to output.\r
+  *   This parameter can be one of the following values:\r
+  *     @arg RCC_MCOSource_NoClock: No clock selected\r
+  *     @arg RCC_MCOSource_SYSCLK: System clock selected\r
+  *     @arg RCC_MCOSource_HSI: HSI oscillator clock selected\r
+  *     @arg RCC_MCOSource_MSI: MSI oscillator clock selected  \r
+  *     @arg RCC_MCOSource_HSE: HSE oscillator clock selected\r
+  *     @arg RCC_MCOSource_PLLCLK: PLL clock selected\r
+  *     @arg RCC_MCOSource_LSI: LSI clock selected\r
+  *     @arg RCC_MCOSource_LSE: LSE clock selected    \r
+  * @param  RCC_MCODiv: specifies the MCO prescaler.\r
+  *   This parameter can be one of the following values: \r
+  *     @arg RCC_MCODiv_1: no division applied to MCO clock \r
+  *     @arg RCC_MCODiv_2: division by 2 applied to MCO clock\r
+  *     @arg RCC_MCODiv_4: division by 4 applied to MCO clock\r
+  *     @arg RCC_MCODiv_8: division by 8 applied to MCO clock\r
+  *     @arg RCC_MCODiv_16: division by 16 applied to MCO clock             \r
+  * @retval None\r
+  */\r
+void RCC_MCOConfig(uint8_t RCC_MCOSource, uint8_t RCC_MCODiv)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_RCC_MCO_SOURCE(RCC_MCOSource));\r
+  assert_param(IS_RCC_MCO_DIV(RCC_MCODiv));\r
+    \r
+  /* Select MCO clock source and prescaler */\r
+  *(__IO uint8_t *) CFGR_BYTE4_ADDRESS =  RCC_MCOSource | RCC_MCODiv; \r
+}\r
+\r
+/**\r
+  * @brief  Checks whether the specified RCC flag is set or not.\r
+  * @param  RCC_FLAG: specifies the flag to check.\r
+  *   This parameter can be one of the following values:\r
+  *     @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready\r
+  *     @arg RCC_FLAG_MSIRDY: MSI oscillator clock ready  \r
+  *     @arg RCC_FLAG_HSERDY: HSE oscillator clock ready\r
+  *     @arg RCC_FLAG_PLLRDY: PLL clock ready\r
+  *     @arg RCC_FLAG_LSERDY: LSE oscillator clock ready\r
+  *     @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready\r
+  *     @arg RCC_FLAG_OBLRST: Option Byte Loader (OBL) reset \r
+  *     @arg RCC_FLAG_PINRST: Pin reset\r
+  *     @arg RCC_FLAG_PORRST: POR/PDR reset\r
+  *     @arg RCC_FLAG_SFTRST: Software reset\r
+  *     @arg RCC_FLAG_IWDGRST: Independent Watchdog reset\r
+  *     @arg RCC_FLAG_WWDGRST: Window Watchdog reset\r
+  *     @arg RCC_FLAG_LPWRRST: Low Power reset\r
+  * @retval The new state of RCC_FLAG (SET or RESET).\r
+  */\r
+FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG)\r
+{\r
+  uint32_t tmp = 0;\r
+  uint32_t statusreg = 0;\r
+  FlagStatus bitstatus = RESET;\r
+\r
+  /* Check the parameters */\r
+  assert_param(IS_RCC_FLAG(RCC_FLAG));\r
+\r
+  /* Get the RCC register index */\r
+  tmp = RCC_FLAG >> 5;\r
+\r
+  if (tmp == 1)               /* The flag to check is in CR register */\r
+  {\r
+    statusreg = RCC->CR;\r
+  }\r
+  else          /* The flag to check is in CSR register (tmp == 2) */\r
+  {\r
+    statusreg = RCC->CSR;\r
+  }\r
+\r
+  /* Get the flag position */\r
+  tmp = RCC_FLAG & FLAG_MASK;\r
+\r
+  if ((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET)\r
+  {\r
+    bitstatus = SET;\r
+  }\r
+  else\r
+  {\r
+    bitstatus = RESET;\r
+  }\r
+  /* Return the flag status */\r
+  return bitstatus;\r
+}\r
+\r
+/**\r
+  * @brief  Clears the RCC reset flags.\r
+  *   The reset flags are: RCC_FLAG_OBLRST, RCC_FLAG_PINRST, RCC_FLAG_PORRST, \r
+  *   RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST.\r
+  * @param  None\r
+  * @retval None\r
+  */\r
+void RCC_ClearFlag(void)\r
+{\r
+  /* Set RMVF bit to clear the reset flags */\r
+  RCC->CSR |= RCC_CSR_RMVF;\r
+}\r
+\r
+/**\r
+  * @brief  Checks whether the specified RCC interrupt has occurred or not.\r
+  * @param  RCC_IT: specifies the RCC interrupt source to check.\r
+  *   This parameter can be one of the following values:\r
+  *     @arg RCC_IT_LSIRDY: LSI ready interrupt\r
+  *     @arg RCC_IT_LSERDY: LSE ready interrupt\r
+  *     @arg RCC_IT_HSIRDY: HSI ready interrupt\r
+  *     @arg RCC_IT_HSERDY: HSE ready interrupt\r
+  *     @arg RCC_IT_PLLRDY: PLL ready interrupt\r
+  *     @arg RCC_IT_MSIRDY: MSI ready interrupt \r
+  *     @arg RCC_IT_CSS: Clock Security System interrupt\r
+  * @retval The new state of RCC_IT (SET or RESET).\r
+  */\r
+ITStatus RCC_GetITStatus(uint8_t RCC_IT)\r
+{\r
+  ITStatus bitstatus = RESET;\r
+  /* Check the parameters */\r
+  assert_param(IS_RCC_GET_IT(RCC_IT));\r
+  \r
+  /* Check the status of the specified RCC interrupt */\r
+  if ((RCC->CIR & RCC_IT) != (uint32_t)RESET)\r
+  {\r
+    bitstatus = SET;\r
+  }\r
+  else\r
+  {\r
+    bitstatus = RESET;\r
+  }\r
+  /* Return the RCC_IT status */\r
+  return  bitstatus;\r
+}\r
+\r
+/**\r
+  * @brief  Clears the RCC's interrupt pending bits.\r
+  * @param  RCC_IT: specifies the interrupt pending bit to clear.\r
+  *   This parameter can be any combination of the following values:\r
+  *     @arg RCC_IT_LSIRDY: LSI ready interrupt\r
+  *     @arg RCC_IT_LSERDY: LSE ready interrupt\r
+  *     @arg RCC_IT_HSIRDY: HSI ready interrupt\r
+  *     @arg RCC_IT_HSERDY: HSE ready interrupt\r
+  *     @arg RCC_IT_PLLRDY: PLL ready interrupt\r
+  *     @arg RCC_IT_MSIRDY: MSI ready interrupt  \r
+  *     @arg RCC_IT_CSS: Clock Security System interrupt\r
+  * @retval None\r
+  */\r
+void RCC_ClearITPendingBit(uint8_t RCC_IT)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_RCC_CLEAR_IT(RCC_IT));\r
+  \r
+  /* Perform Byte access to RCC_CIR[23:16] bits to clear the selected interrupt\r
+     pending bits */\r
+  *(__IO uint8_t *) CIR_BYTE3_ADDRESS = RCC_IT;\r
+}\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r

diff --git a/Demo/CORTEX_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_spi.c b/Demo/CORTEX_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_spi.c
new file mode 100644 (file)
index 0000000..67e4b38
--- /dev/null
+++ b/Demo/CORTEX_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_spi.c
@@ -0,0 +1,641 @@
+/**\r
+  ******************************************************************************\r
+  * @file    stm32l1xx_spi.c\r
+  * @author  MCD Application Team\r
+  * @version V1.0.0RC1\r
+  * @date    07/02/2010\r
+  * @brief   This file provides all the SPI firmware functions.\r
+  ******************************************************************************\r
+  * @copy\r
+  *\r
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+  *\r
+  * <h2><center>&copy; COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+  */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx_spi.h"\r
+#include "stm32l1xx_rcc.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+  * @{\r
+  */\r
+\r
+/** @defgroup SPI \r
+  * @brief SPI driver modules\r
+  * @{\r
+  */ \r
+\r
+/** @defgroup SPI_Private_TypesDefinitions\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */ \r
+\r
+\r
+/** @defgroup SPI_Private_Defines\r
+  * @{\r
+  */\r
+\r
+/* SPI registers Masks */\r
+#define CR1_CLEAR_MASK       ((uint16_t)0x3040)\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup SPI_Private_Macros\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup SPI_Private_Variables\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup SPI_Private_FunctionPrototypes\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup SPI_Private_Functions\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @brief  Deinitializes the SPIx peripheral registers to their default\r
+  *         reset values.\r
+  * @param  SPIx: where x can be 1 or 2 to select the SPI peripheral.\r
+  * @retval None\r
+  */\r
+void SPI_DeInit(SPI_TypeDef* SPIx)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+\r
+  if (SPIx == SPI1)\r
+  {\r
+    /* Enable SPI1 reset state */\r
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, ENABLE);\r
+    /* Release SPI1 from reset state */\r
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, DISABLE);\r
+  }\r
+  else\r
+  {\r
+    if (SPIx == SPI2)\r
+    {\r
+      /* Enable SPI2 reset state */\r
+      RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, ENABLE);\r
+      /* Release SPI2 from reset state */\r
+      RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, DISABLE);\r
+    }\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  Initializes the SPIx peripheral according to the specified \r
+  *   parameters in the SPI_InitStruct.\r
+  * @param  SPIx: where x can be 1 or 2 to select the SPI peripheral.\r
+  * @param  SPI_InitStruct: pointer to a SPI_InitTypeDef structure that\r
+  *   contains the configuration information for the specified SPI peripheral.\r
+  * @retval None\r
+  */\r
+void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct)\r
+{\r
+  uint16_t tmpreg = 0;\r
+  \r
+  /* check the parameters */\r
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));   \r
+  \r
+  /* Check the SPI parameters */\r
+  assert_param(IS_SPI_DIRECTION_MODE(SPI_InitStruct->SPI_Direction));\r
+  assert_param(IS_SPI_MODE(SPI_InitStruct->SPI_Mode));\r
+  assert_param(IS_SPI_DATASIZE(SPI_InitStruct->SPI_DataSize));\r
+  assert_param(IS_SPI_CPOL(SPI_InitStruct->SPI_CPOL));\r
+  assert_param(IS_SPI_CPHA(SPI_InitStruct->SPI_CPHA));\r
+  assert_param(IS_SPI_NSS(SPI_InitStruct->SPI_NSS));\r
+  assert_param(IS_SPI_BAUDRATE_PRESCALER(SPI_InitStruct->SPI_BaudRatePrescaler));\r
+  assert_param(IS_SPI_FIRST_BIT(SPI_InitStruct->SPI_FirstBit));\r
+  assert_param(IS_SPI_CRC_POLYNOMIAL(SPI_InitStruct->SPI_CRCPolynomial));\r
+\r
+/*---------------------------- SPIx CR1 Configuration ------------------------*/\r
+  /* Get the SPIx CR1 value */\r
+  tmpreg = SPIx->CR1;\r
+  /* Clear BIDIMode, BIDIOE, RxONLY, SSM, SSI, LSBFirst, BR, MSTR, CPOL and CPHA bits */\r
+  tmpreg &= CR1_CLEAR_MASK;\r
+  /* Configure SPIx: direction, NSS management, first transmitted bit, BaudRate prescaler\r
+     master/salve mode, CPOL and CPHA */\r
+  /* Set BIDImode, BIDIOE and RxONLY bits according to SPI_Direction value */\r
+  /* Set SSM, SSI and MSTR bits according to SPI_Mode and SPI_NSS values */\r
+  /* Set LSBFirst bit according to SPI_FirstBit value */\r
+  /* Set BR bits according to SPI_BaudRatePrescaler value */\r
+  /* Set CPOL bit according to SPI_CPOL value */\r
+  /* Set CPHA bit according to SPI_CPHA value */\r
+  tmpreg |= (uint16_t)((uint32_t)SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_Mode |\r
+                  SPI_InitStruct->SPI_DataSize | SPI_InitStruct->SPI_CPOL |  \r
+                  SPI_InitStruct->SPI_CPHA | SPI_InitStruct->SPI_NSS |  \r
+                  SPI_InitStruct->SPI_BaudRatePrescaler | SPI_InitStruct->SPI_FirstBit);\r
+  /* Write to SPIx CR1 */\r
+  SPIx->CR1 = tmpreg;\r
+  \r
+/*---------------------------- SPIx CRCPOLY Configuration --------------------*/\r
+  /* Write to SPIx CRCPOLY */\r
+  SPIx->CRCPR = SPI_InitStruct->SPI_CRCPolynomial;\r
+}\r
+\r
+/**\r
+  * @brief  Fills each SPI_InitStruct member with its default value.\r
+  * @param  SPI_InitStruct : pointer to a SPI_InitTypeDef structure which will be initialized.\r
+  * @retval None\r
+  */\r
+void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct)\r
+{\r
+/*--------------- Reset SPI init structure parameters values -----------------*/\r
+  /* Initialize the SPI_Direction member */\r
+  SPI_InitStruct->SPI_Direction = SPI_Direction_2Lines_FullDuplex;\r
+  /* initialize the SPI_Mode member */\r
+  SPI_InitStruct->SPI_Mode = SPI_Mode_Slave;\r
+  /* initialize the SPI_DataSize member */\r
+  SPI_InitStruct->SPI_DataSize = SPI_DataSize_8b;\r
+  /* Initialize the SPI_CPOL member */\r
+  SPI_InitStruct->SPI_CPOL = SPI_CPOL_Low;\r
+  /* Initialize the SPI_CPHA member */\r
+  SPI_InitStruct->SPI_CPHA = SPI_CPHA_1Edge;\r
+  /* Initialize the SPI_NSS member */\r
+  SPI_InitStruct->SPI_NSS = SPI_NSS_Hard;\r
+  /* Initialize the SPI_BaudRatePrescaler member */\r
+  SPI_InitStruct->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2;\r
+  /* Initialize the SPI_FirstBit member */\r
+  SPI_InitStruct->SPI_FirstBit = SPI_FirstBit_MSB;\r
+  /* Initialize the SPI_CRCPolynomial member */\r
+  SPI_InitStruct->SPI_CRCPolynomial = 7;\r
+}\r
+\r
+\r
+/**\r
+  * @brief  Enables or disables the specified SPI peripheral.\r
+  * @param  SPIx: where x can be 1 or 2 to select the SPI peripheral.\r
+  * @param  NewState: new state of the SPIx peripheral. \r
+  *   This parameter can be: ENABLE or DISABLE.\r
+  * @retval None\r
+  */\r
+void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+  assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+  if (NewState != DISABLE)\r
+  {\r
+    /* Enable the selected SPI peripheral */\r
+    SPIx->CR1 |= SPI_CR1_SPE;\r
+  }\r
+  else\r
+  {\r
+    /* Disable the selected SPI peripheral */\r
+    SPIx->CR1 &= (uint16_t)~((uint16_t)SPI_CR1_SPE);\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  Enables or disables the specified SPI interrupts.\r
+  * @param  SPIx: where x can be 1 or 2 in SPI mode \r
+  * @param  SPI_IT: specifies the SPI interrupt source to be enabled or disabled. \r
+  *   This parameter can be one of the following values:\r
+  *     @arg SPI_IT_TXE: Tx buffer empty interrupt mask\r
+  *     @arg SPI_IT_RXNE: Rx buffer not empty interrupt mask\r
+  *     @arg SPI_IT_ERR: Error interrupt mask\r
+  * @param  NewState: new state of the specified SPI interrupt.\r
+  *   This parameter can be: ENABLE or DISABLE.\r
+  * @retval None\r
+  */\r
+void SPI_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_IT, FunctionalState NewState)\r
+{\r
+  uint16_t itpos = 0, itmask = 0 ;\r
+  /* Check the parameters */\r
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+  assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+  assert_param(IS_SPI_CONFIG_IT(SPI_IT));\r
+\r
+  /* Get the SPI IT index */\r
+  itpos = SPI_IT >> 4;\r
+\r
+  /* Set the IT mask */\r
+  itmask = (uint16_t)1 << (uint16_t)itpos;\r
+\r
+  if (NewState != DISABLE)\r
+  {\r
+    /* Enable the selected SPI interrupt */\r
+    SPIx->CR2 |= itmask;\r
+  }\r
+  else\r
+  {\r
+    /* Disable the selected SPI interrupt */\r
+    SPIx->CR2 &= (uint16_t)~itmask;\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  Enables or disables the SPIx DMA interface.\r
+  * @param  SPIx: where x can be 1 or 2 in SPI mode \r
+  * @param  SPI_DMAReq: specifies the SPI DMA transfer request to be enabled or disabled. \r
+  *   This parameter can be any combination of the following values:\r
+  *     @arg SPI_DMAReq_Tx: Tx buffer DMA transfer request\r
+  *     @arg SPI_DMAReq_Rx: Rx buffer DMA transfer request\r
+  * @param  NewState: new state of the selected SPI DMA transfer request.\r
+  *   This parameter can be: ENABLE or DISABLE.\r
+  * @retval None\r
+  */\r
+void SPI_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_DMAReq, FunctionalState NewState)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+  assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+  assert_param(IS_SPI_DMAREQ(SPI_DMAReq));\r
+  if (NewState != DISABLE)\r
+  {\r
+    /* Enable the selected SPI DMA requests */\r
+    SPIx->CR2 |= SPI_DMAReq;\r
+  }\r
+  else\r
+  {\r
+    /* Disable the selected SPI DMA requests */\r
+    SPIx->CR2 &= (uint16_t)~SPI_DMAReq;\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  Transmits a Data through the SPIx peripheral.\r
+  * @param  SPIx: where x can be 1 or 2 in SPI mode \r
+  * @param  Data : Data to be transmitted.\r
+  * @retval None\r
+  */\r
+void SPI_SendData(SPI_TypeDef* SPIx, uint16_t Data)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+  \r
+  /* Write in the DR register the data to be sent */\r
+  SPIx->DR = Data;\r
+}\r
+\r
+/**\r
+  * @brief  Returns the most recent received data by the SPIx peripheral. \r
+  * @param  SPIx: where x can be 1 or 2 in SPI mode \r
+  * @retval The value of the received data.\r
+  */\r
+uint16_t SPI_ReceiveData(SPI_TypeDef* SPIx)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+  \r
+  /* Return the data in the DR register */\r
+  return SPIx->DR;\r
+}\r
+\r
+/**\r
+  * @brief  Configures internally by software the NSS pin for the selected SPI.\r
+  * @param  SPIx: where x can be 1 or 2 to select the SPI peripheral.\r
+  * @param  SPI_NSSInternalSoft: specifies the SPI NSS internal state.\r
+  *   This parameter can be one of the following values:\r
+  *     @arg SPI_NSSInternalSoft_Set: Set NSS pin internally\r
+  *     @arg SPI_NSSInternalSoft_Reset: Reset NSS pin internally\r
+  * @retval None\r
+  */\r
+void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+  assert_param(IS_SPI_NSS_INTERNAL(SPI_NSSInternalSoft));\r
+  if (SPI_NSSInternalSoft != SPI_NSSInternalSoft_Reset)\r
+  {\r
+    /* Set NSS pin internally by software */\r
+    SPIx->CR1 |= SPI_NSSInternalSoft_Set;\r
+  }\r
+  else\r
+  {\r
+    /* Reset NSS pin internally by software */\r
+    SPIx->CR1 &= SPI_NSSInternalSoft_Reset;\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  Enables or disables the SS output for the selected SPI.\r
+  * @param  SPIx: where x can be 1 or 2 to select the SPI peripheral.\r
+  * @param  NewState: new state of the SPIx SS output. \r
+  *   This parameter can be: ENABLE or DISABLE.\r
+  * @retval None\r
+  */\r
+void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+  assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+  if (NewState != DISABLE)\r
+  {\r
+    /* Enable the selected SPI SS output */\r
+    SPIx->CR2 |= (uint16_t)SPI_CR2_SSOE;\r
+  }\r
+  else\r
+  {\r
+    /* Disable the selected SPI SS output */\r
+    SPIx->CR2 &= (uint16_t)~((uint16_t)SPI_CR2_SSOE);\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  Configures the data size for the selected SPI.\r
+  * @param  SPIx: where x can be 1 or 2  to select the SPI peripheral.\r
+  * @param  SPI_DataSize: specifies the SPI data size.\r
+  *   This parameter can be one of the following values:\r
+  *     @arg SPI_DataSize_16b: Set data frame format to 16bit\r
+  *     @arg SPI_DataSize_8b: Set data frame format to 8bit\r
+  * @retval None\r
+  */\r
+void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+  assert_param(IS_SPI_DATASIZE(SPI_DataSize));\r
+  /* Clear DFF bit */\r
+  SPIx->CR1 &= (uint16_t)~SPI_DataSize_16b;\r
+  /* Set new DFF bit value */\r
+  SPIx->CR1 |= SPI_DataSize;\r
+}\r
+\r
+/**\r
+  * @brief  Transmit the SPIx CRC value.\r
+  * @param  SPIx: where x can be 1 or 2  to select the SPI peripheral.\r
+  * @retval None\r
+  */\r
+void SPI_TransmitCRC(SPI_TypeDef* SPIx)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+  \r
+  /* Enable the selected SPI CRC transmission */\r
+  SPIx->CR1 |= SPI_CR1_CRCNEXT;\r
+}\r
+\r
+/**\r
+  * @brief  Enables or disables the CRC value calculation of the transfered bytes.\r
+  * @param  SPIx: where x can be 1 or 2  to select the SPI peripheral.\r
+  * @param  NewState: new state of the SPIx CRC value calculation.\r
+  *   This parameter can be: ENABLE or DISABLE.\r
+  * @retval None\r
+  */\r
+void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+  assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+  if (NewState != DISABLE)\r
+  {\r
+    /* Enable the selected SPI CRC calculation */\r
+    SPIx->CR1 |= SPI_CR1_CRCEN;\r
+  }\r
+  else\r
+  {\r
+    /* Disable the selected SPI CRC calculation */\r
+    SPIx->CR1 &= (uint16_t)~((uint16_t)SPI_CR1_CRCEN);\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  Returns the transmit or the receive CRC register value for the specified SPI.\r
+  * @param  SPIx: where x can be 1 or 2  to select the SPI peripheral.\r
+  * @param  SPI_CRC: specifies the CRC register to be read.\r
+  *   This parameter can be one of the following values:\r
+  *     @arg SPI_CRC_Tx: Selects Tx CRC register\r
+  *     @arg SPI_CRC_Rx: Selects Rx CRC register\r
+  * @retval The selected CRC register value..\r
+  */\r
+uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC)\r
+{\r
+  uint16_t crcreg = 0;\r
+  /* Check the parameters */\r
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+  assert_param(IS_SPI_CRC(SPI_CRC));\r
+  if (SPI_CRC != SPI_CRC_Rx)\r
+  {\r
+    /* Get the Tx CRC register */\r
+    crcreg = SPIx->TXCRCR;\r
+  }\r
+  else\r
+  {\r
+    /* Get the Rx CRC register */\r
+    crcreg = SPIx->RXCRCR;\r
+  }\r
+  /* Return the selected CRC register */\r
+  return crcreg;\r
+}\r
+\r
+/**\r
+  * @brief  Returns the CRC Polynomial register value for the specified SPI.\r
+  * @param  SPIx: where x can be 1 or 2  to select the SPI peripheral.\r
+  * @retval The CRC Polynomial register value.\r
+  */\r
+uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+  \r
+  /* Return the CRC polynomial register */\r
+  return SPIx->CRCPR;\r
+}\r
+\r
+/**\r
+  * @brief  Selects the data transfer direction in bi-directional mode for the specified SPI.\r
+  * @param  SPIx: where x can be 1 or 2  to select the SPI peripheral.\r
+  * @param  SPI_Direction: specifies the data transfer direction in bi-directional mode. \r
+  *   This parameter can be one of the following values:\r
+  *     @arg SPI_Direction_Tx: Selects Tx transmission direction\r
+  *     @arg SPI_Direction_Rx: Selects Rx receive direction\r
+  * @retval None\r
+  */\r
+void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+  assert_param(IS_SPI_DIRECTION(SPI_Direction));\r
+  if (SPI_Direction == SPI_Direction_Tx)\r
+  {\r
+    /* Set the Tx only mode */\r
+    SPIx->CR1 |= SPI_Direction_Tx;\r
+  }\r
+  else\r
+  {\r
+    /* Set the Rx only mode */\r
+    SPIx->CR1 &= SPI_Direction_Rx;\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  Checks whether the specified SPI flag is set or not.\r
+  * @param  SPIx: where x can be 1 or 2 in SPI mode \r
+  * @param  SPI_FLAG: specifies the SPI flag to check. \r
+  *   This parameter can be one of the following values:\r
+  *     @arg SPI_FLAG_TXE: Transmit buffer empty flag.\r
+  *     @arg SPI_FLAG_RXNE: Receive buffer not empty flag.\r
+  *     @arg SPI_FLAG_BSY: Busy flag.\r
+  *     @arg SPI_FLAG_OVR: Overrun flag.\r
+  *     @arg SPI_FLAG_MODF: Mode Fault flag.\r
+  *     @arg SPI_FLAG_CRCERR: CRC Error flag.\r
+  * @retval The new state of SPI_FLAG (SET or RESET).\r
+  */\r
+FlagStatus SPI_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_FLAG)\r
+{\r
+  FlagStatus bitstatus = RESET;\r
+  /* Check the parameters */\r
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+  assert_param(IS_SPI_GET_FLAG(SPI_FLAG));\r
+  /* Check the status of the specified SPI flag */\r
+  if ((SPIx->SR & SPI_FLAG) != (uint16_t)RESET)\r
+  {\r
+    /* SPI_FLAG is set */\r
+    bitstatus = SET;\r
+  }\r
+  else\r
+  {\r
+    /* SPI_FLAG is reset */\r
+    bitstatus = RESET;\r
+  }\r
+  /* Return the SPI_FLAG status */\r
+  return  bitstatus;\r
+}\r
+\r
+/**\r
+  * @brief  Clears the SPIx CRC Error (CRCERR) flag.\r
+  * @param  SPIx: where x can be 1 or 2 in SPI mode \r
+  * @param  SPI_FLAG: specifies the SPI flag to clear. \r
+  *   This function clears only CRCERR flag.\r
+  * @note\r
+  *   - OVR (OverRun error) flag is cleared by software sequence: a read \r
+  *     operation to SPI_DR register (SPI_ReceiveData()) followed by a read \r
+  *     operation to SPI_SR register (SPI_GetFlagStatus()).\r
+  *   - UDR (UnderRun error) flag is cleared by a read operation to \r
+  *     SPI_SR register (SPI_GetFlagStatus()).\r
+  *   - MODF (Mode Fault) flag is cleared by software sequence: a read/write \r
+  *     operation to SPI_SR register (SPI_GetFlagStatus()) followed by a \r
+  *     write operation to SPI_CR1 register (SPI_Cmd() to enable the SPI).\r
+  * @retval None\r
+  */\r
+void SPI_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_FLAG)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+  assert_param(IS_SPI_CLEAR_FLAG(SPI_FLAG));\r
+    \r
+    /* Clear the selected SPI CRC Error (CRCERR) flag */\r
+    SPIx->SR = (uint16_t)~SPI_FLAG;\r
+}\r
+\r
+/**\r
+  * @brief  Checks whether the specified SPI interrupt has occurred or not.\r
+  * @param  SPIx: where x can be\r
+  *   - 1 or 2 in SPI mode \r
+  * @param  SPI_IT: specifies the SPI interrupt source to check. \r
+  *   This parameter can be one of the following values:\r
+  *     @arg SPI_IT_TXE: Transmit buffer empty interrupt.\r
+  *     @arg SPI_IT_RXNE: Receive buffer not empty interrupt.\r
+  *     @arg SPI_IT_OVR: Overrun interrupt.\r
+  *     @arg SPI_IT_MODF: Mode Fault interrupt.\r
+  *     @arg SPI_IT_CRCERR: CRC Error interrupt.\r
+  * @retval The new state of SPI_IT (SET or RESET).\r
+  */\r
+ITStatus SPI_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_IT)\r
+{\r
+  ITStatus bitstatus = RESET;\r
+  uint16_t itpos = 0, itmask = 0, enablestatus = 0;\r
+\r
+  /* Check the parameters */\r
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+  assert_param(IS_SPI_GET_IT(SPI_IT));\r
+\r
+  /* Get the SPI IT index */\r
+  itpos = 0x01 << (SPI_IT & 0x0F);\r
+\r
+  /* Get the SPI IT mask */\r
+  itmask = SPI_IT >> 4;\r
+\r
+  /* Set the IT mask */\r
+  itmask = 0x01 << itmask;\r
+\r
+  /* Get the SPI_IT enable bit status */\r
+  enablestatus = (SPIx->CR2 & itmask) ;\r
+\r
+  /* Check the status of the specified SPI interrupt */\r
+  if (((SPIx->SR & itpos) != (uint16_t)RESET) && enablestatus)\r
+  {\r
+    /* SPI_IT is set */\r
+    bitstatus = SET;\r
+  }\r
+  else\r
+  {\r
+    /* SPI_IT is reset */\r
+    bitstatus = RESET;\r
+  }\r
+  /* Return the SPI_IT status */\r
+  return bitstatus;\r
+}\r
+\r
+/**\r
+  * @brief  Clears the SPIx CRC Error (CRCERR) interrupt pending bit.\r
+  * @param  SPIx: where x can be\r
+  *   - 1 or 2 in SPI mode \r
+  * @param  SPI_IT: specifies the SPI interrupt pending bit to clear.\r
+  *   This function clears only CRCERR intetrrupt pending bit.   \r
+  * @note\r
+  *   - OVR (OverRun Error) interrupt pending bit is cleared by software \r
+  *     sequence: a read operation to SPI_DR register (SPI_ReceiveData()) \r
+  *     followed by a read operation to SPI_SR register (SPI_GetITStatus()).\r
+  *   - UDR (UnderRun Error) interrupt pending bit is cleared by a read \r
+  *     operation to SPI_SR register (SPI_GetITStatus()).\r
+  *   - MODF (Mode Fault) interrupt pending bit is cleared by software sequence:\r
+  *     a read/write operation to SPI_SR register (SPI_GetITStatus()) \r
+  *     followed by a write operation to SPI_CR1 register (SPI_Cmd() to enable \r
+  *     the SPI).\r
+  * @retval None\r
+  */\r
+void SPI_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_IT)\r
+{\r
+  uint16_t itpos = 0;\r
+  /* Check the parameters */\r
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+  assert_param(IS_SPI_CLEAR_IT(SPI_IT));\r
+\r
+  /* Get the SPI IT index */\r
+  itpos = 0x01 << (SPI_IT & 0x0F);\r
+\r
+  /* Clear the selected SPI CRC Error (CRCERR) interrupt pending bit */\r
+  SPIx->SR = (uint16_t)~itpos;\r
+}\r
+/**\r
+  * @}\r
+  */ \r
+\r
+/**\r
+  * @}\r
+  */ \r
+\r
+/**\r
+  * @}\r
+  */ \r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r

diff --git a/Demo/CORTEX_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_syscfg.c b/Demo/CORTEX_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_syscfg.c
new file mode 100644 (file)
index 0000000..0d9bef1
--- /dev/null
+++ b/Demo/CORTEX_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_syscfg.c
@@ -0,0 +1,494 @@
+/**\r
+  ******************************************************************************\r
+  * @file    stm32l1xx_syscfg.c\r
+  * @author  MCD Application Team\r
+  * @version V1.0.0RC1\r
+  * @date    07/02/2010\r
+  * @brief   This file provides all the SYSCFG and RI firmware functions.\r
+  ******************************************************************************\r
+  * @copy\r
+  *\r
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+  *\r
+  * <h2><center>&copy; COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+  */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx_syscfg.h"\r
+#include "stm32l1xx_rcc.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+  * @{\r
+  */\r
+\r
+/** @defgroup SYSCFG \r
+  * @brief SYSCFG driver modules\r
+  * @{\r
+  */ \r
+\r
+/** @defgroup SYSCFG_Private_TypesDefinitions\r
+  * @{\r
+  */ \r
+/**\r
+  * @}\r
+  */ \r
+\r
+/** @defgroup SYSCFG_Private_Defines\r
+  * @{\r
+  */ \r
+  \r
+#define RI_ICR_RESET_VALUE          ((uint32_t)0x00000000) /*!< ICR Reset value */\r
+#define RI_ASCR1_RESET_VALUE        ((uint32_t)0x00000000) /*!< ASCR1 Reset value */\r
+#define RI_ASCR2_RESET_VALUE        ((uint32_t)0x00000000) /*!< ASCR2 Reset value */\r
+#define RI_HYSCR1_RESET_VALUE       ((uint32_t)0x00000000) /*!< HYSCR1 Reset value */\r
+#define RI_HYSCR2_RESET_VALUE       ((uint32_t)0x00000000) /*!< HYSCR2 Reset value */\r
+#define RI_HYSCR3_RESET_VALUE       ((uint32_t)0x00000000) /*!< HYSCR3 Reset value */\r
+\r
+#define TIM_SELECT_MASK             ((uint32_t)0xFFFCFFFF) /*!< TIM select mask */\r
+#define IC_ROUTING_MASK             ((uint32_t)0x0000000F) /*!< Input Capture routing mask */\r
+\r
+/**\r
+  * @}\r
+  */ \r
+\r
+/** @defgroup SYSCFG_Private_Macros\r
+  * @{\r
+  */ \r
+/**\r
+  * @}\r
+  */ \r
+\r
+/** @defgroup SYSCFG_Private_Variables\r
+  * @{\r
+  */ \r
+/**\r
+  * @}\r
+  */ \r
+\r
+/** @defgroup SYSCFG_Private_FunctionPrototypes\r
+  * @{\r
+  */ \r
+/**\r
+  * @}\r
+  */ \r
+\r
+/** @defgroup SYSCFG_Private_Functions\r
+  * @{\r
+  */ \r
+\r
+/**\r
+  * @brief  Deinitializes the syscfg registers to their default reset values.\r
+  * @param  None\r
+  * @retval None\r
+  * @ Note: MEMRMP bits are not reset by APB2 reset.\r
+  */\r
+void SYSCFG_DeInit(void)\r
+{\r
+   RCC_APB2PeriphResetCmd(RCC_APB2Periph_SYSCFG, ENABLE);\r
+   RCC_APB2PeriphResetCmd(RCC_APB2Periph_SYSCFG, DISABLE);\r
+}\r
+\r
+/**\r
+  * @brief  Changes the mapping of the specified pin.\r
+  * @param  SYSCFG_Memory: selects the memory remapping.\r
+  *   This parameter can be one of the following values:\r
+  *     @arg SYSCFG_MemoryRemap_Flash: Main Flash memory mapped at 0x00000000  \r
+  *     @arg SYSCFG_MemoryRemap_SystemFlash: System Flash memory mapped at 0x00000000\r
+  *     @arg SYSCFG_MemoryRemap_SRAM: Embedded SRAM mapped at 0x00000000     \r
+  * @retval None\r
+  */\r
+void SYSCFG_MemoryRemapConfig(uint8_t SYSCFG_MemoryRemap)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_SYSCFG_MEMORY_REMAP_CONFING(SYSCFG_MemoryRemap));\r
+  SYSCFG->MEMRMP = SYSCFG_MemoryRemap;\r
+}\r
+\r
+/**\r
+  * @brief  Control the internal pull-up on USB DP line.\r
+  * @param  NewState: New state of the switch control mode. \r
+  *   This parameter can be ENABLE: Connect internal pull-up on USB DP line.\r
+  *                      or DISABLE: Disconnect internal pull-up on USB DP line.\r
+  * @retval None\r
+  */\r
+void SYSCFG_USBPuCmd(FunctionalState NewState)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+  if (NewState != DISABLE)\r
+  { \r
+    /* Connect internal pull-up on USB DP line */\r
+    SYSCFG->PMC |= (uint32_t) SYSCFG_PMC_USB_PU;\r
+  }\r
+  else\r
+  {\r
+    /* Disconnect internal pull-up on USB DP line */\r
+    SYSCFG->PMC &= (uint32_t)(~SYSCFG_PMC_USB_PU);\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  Selects the GPIO pin used as EXTI Line.\r
+  * @param  EXTI_PortSourceGPIOx : selects the GPIO port to be used as source \r
+  *                                for EXTI lines where x can be (A, B, C, D, E or H).\r
+  * @param  EXTI_PinSourcex: specifies the EXTI line to be configured.\r
+  *   This parameter can be EXTI_PinSourcex where x can be (0..15)\r
+  * @retval None\r
+  */\r
+void SYSCFG_EXTILineConfig(uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex)\r
+{\r
+  uint32_t tmp = 0x00;\r
+\r
+  /* Check the parameters */\r
+  assert_param(IS_EXTI_PORT_SOURCE(EXTI_PortSourceGPIOx));\r
+  assert_param(IS_EXTI_PIN_SOURCE(EXTI_PinSourcex));\r
+  \r
+  tmp = ((uint32_t)0x0F) << (0x04 * (EXTI_PinSourcex & (uint8_t)0x03));\r
+  SYSCFG->EXTICR[EXTI_PinSourcex >> 0x02] &= ~tmp;\r
+  SYSCFG->EXTICR[EXTI_PinSourcex >> 0x02] |= (((uint32_t)EXTI_PortSourceGPIOx) << (0x04 * (EXTI_PinSourcex & (uint8_t)0x03)));\r
+}\r
+\r
+/**\r
+  * @brief Deinitializes the RI registers to their default reset values.\r
+  * @param  None\r
+  * @retval None\r
+  */\r
+void SYSCFG_RIDeInit(void)\r
+{\r
+  RI->ICR     = RI_ICR_RESET_VALUE;         /*!< Set RI->ICR to reset value */\r
+  RI->ASCR1   = RI_ASCR1_RESET_VALUE;       /*!< Set RI->ASCR1 to reset value */  \r
+  RI->ASCR2   = RI_ASCR2_RESET_VALUE;       /*!< Set RI->ASCR2 to reset value */  \r
+  RI->HYSCR1  = RI_HYSCR1_RESET_VALUE;      /*!< Set RI->HYSCR1 to reset value */\r
+  RI->HYSCR2  = RI_HYSCR2_RESET_VALUE;      /*!< Set RI->HYSCR2 to reset value */\r
+  RI->HYSCR3  = RI_HYSCR3_RESET_VALUE;      /*!< Set RI->HYSCR3 to reset value */\r
+}\r
+\r
+/**\r
+  * @brief  Configures the routing interface to select which Timer to be routed.\r
+  * @param  TIM_Select: Timer select.\r
+  *   This parameter can be one of the following values:\r
+  *     @arg TIM_Select_None : No timer selected\r
+  *     @arg TIM_Select_TIM2 : Timer 2 selected \r
+  *     @arg TIM_Select_TIM3 : Timer 3 selected \r
+  *     @arg TIM_Select_TIM4 : Timer 4 selected \r
+  * @retval None.\r
+  */\r
+void SYSCFG_RITIMSelect(uint32_t TIM_Select)\r
+{\r
+  uint32_t tmpreg = 0;\r
+\r
+  /* Check the parameters */\r
+  assert_param(IS_RI_TIM(TIM_Select));\r
+\r
+  /* Get the old register value */\r
+  tmpreg = RI->ICR;\r
+\r
+  /* Clear the TIMx select bits */\r
+  tmpreg &= TIM_SELECT_MASK;\r
+\r
+  /* Select the Timer */\r
+  tmpreg |= (TIM_Select);\r
+\r
+  /* Write to RI->ICR register */\r
+  RI->ICR = tmpreg;\r
+}\r
+\r
+/**\r
+  * @brief  Configures the routing interface to select which Timer Input Capture\r
+  *         to be routed to a selected pin.\r
+  * @param  RI_InputCapture selects which input capture to be routed.\r
+  *   This parameter can be one of the following values:\r
+  *     @arg  RI_InputCapture_IC1: Input capture 1 is slected.\r
+  *     @arg  RI_InputCapture_IC2: Input capture 2 is slected.\r
+  *     @arg  RI_InputCapture_IC3: Input capture 3 is slected.\r
+  *     @arg  RI_InputCapture_IC4: Input capture 4 is slected.\r
+  * @param  RI_InputCaptureRouting: selects which pin to be routed to Input Capture.\r
+  *   This parameter can be one of the following values:\r
+  *     @arg  RI_InputCaptureRouting_0 to RI_InputCaptureRouting_15\r
+  * @Note Input capture selection bits are not reset by this function.\r
+  * @retval None.\r
+  */\r
+void SYSCFG_RITIMInputCaptureConfig(uint32_t RI_InputCapture, uint32_t RI_InputCaptureRouting)\r
+{\r
+  uint32_t tmpreg = 0;\r
+\r
+  /* Check the parameters */\r
+  assert_param(IS_RI_INPUTCAPTURE(RI_InputCapture));\r
+  assert_param(IS_RI_INPUTCAPTURE_ROUTING(RI_InputCaptureRouting));\r
+\r
+  /* Get the old register value */\r
+  tmpreg = RI->ICR;\r
+\r
+  /* Select input captures to be routed */\r
+  tmpreg |= (RI_InputCapture);\r
+\r
+  if((RI_InputCapture & RI_InputCapture_IC1) == RI_InputCapture_IC1)\r
+  {\r
+    /* Clear the input capture select bits */\r
+    tmpreg &= (uint32_t)(~IC_ROUTING_MASK);\r
+\r
+    /* Set RI_InputCaptureRouting bits  */\r
+    tmpreg |= (uint32_t)( RI_InputCaptureRouting);\r
+  }\r
+\r
+  if((RI_InputCapture & RI_InputCapture_IC2) == RI_InputCapture_IC2)\r
+  {\r
+    /* Clear the input capture select bits */\r
+    tmpreg &= (uint32_t)(~(IC_ROUTING_MASK << 4));\r
+\r
+    /* Set RI_InputCaptureRouting bits  */\r
+    tmpreg |= (uint32_t)( (RI_InputCaptureRouting << 4)); \r
+  }\r
+\r
+  if((RI_InputCapture & RI_InputCapture_IC3) == RI_InputCapture_IC3)\r
+  {\r
+    /* Clear the input capture select bits */\r
+    tmpreg &= (uint32_t)(~(IC_ROUTING_MASK << 8));\r
+\r
+    /* Set RI_InputCaptureRouting bits  */\r
+    tmpreg |= (uint32_t)( (RI_InputCaptureRouting << 8));  \r
+  }\r
+\r
+  if((RI_InputCapture & RI_InputCapture_IC4) == RI_InputCapture_IC4)\r
+  {\r
+    /* Clear the input capture select bits */\r
+    tmpreg &= (uint32_t)(~(IC_ROUTING_MASK << 12));\r
+\r
+    /* Set RI_InputCaptureRouting bits  */\r
+    tmpreg |= (uint32_t)( (RI_InputCaptureRouting << 12));  \r
+  }\r
+\r
+  /* Write to RI->ICR register */\r
+  RI->ICR = tmpreg;\r
+}\r
+/**\r
+  * @brief  Configures the Pull-up and Pull-down Resistors \r
+  * @param  RI_Resistor selects the resistor to connect. \r
+  *   This parameter can be  one of the following values:\r
+  *     @arg RI_Resistor_10KPU : 10K pull-up resistor\r
+  *     @arg RI_Resistor_400KPU : 400K pull-up resistor \r
+  *     @arg RI_Resistor_10KPD : 10K pull-down resistor \r
+  *     @arg RI_Resistor_400KPD : 400K pull-down resistor\r
+  * @param  NewState: New state of the analog switch associated to the selected resistor.\r
+  *   This parameter can be:\r
+  *      ENABLE so the selected resistor is connected\r
+  *   or DISABLE so the selected resistor is disconnected\r
+  * @retval None\r
+  */\r
+void SYSCFG_RIResistorConfig(uint32_t RI_Resistor, FunctionalState NewState)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_RI_RESISTOR(RI_Resistor));\r
+  assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+  \r
+  if (NewState != DISABLE)\r
+  {\r
+    /* Enable the resistor */\r
+    COMP->CSR |= (uint32_t) RI_Resistor;\r
+  }\r
+  else\r
+  {\r
+    /* Disable the Resistor */\r
+    COMP->CSR &= (uint32_t) (~RI_Resistor);\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  Close or Open the routing interface Input Output switches.\r
+  * @param  RI_IOSwitch: selects the I/O analog switch number.\r
+  *   This parameter can be one of the following values:\r
+  *     @arg RI_IOSwitch_CH0 --> RI_IOSwitch_CH15\r
+  *     @argRI_IOSwitch_CH18 --> RI_IOSwitch_CH25\r
+  *     @arg RI_IOSwitch_GR10_1 --> RI_IOSwitch_GR10_4\r
+  *     @arg RI_IOSwitch_GR6_1 --> RI_IOSwitch_GR6_2\r
+  *     @arg RI_IOSwitch_GR5_1 --> RI_IOSwitch_GR5_3\r
+  *     @arg RI_IOSwitch_GR4_1 --> RI_IOSwitch_GR4_3\r
+  *     @arg  RI_IOSwitch_VCOMP\r
+  * @param  NewState: New state of the analog switch. \r
+  *   This parameter can be \r
+  *     ENABLE so the Input Output switch is closed\r
+  *     or DISABLE so the Input Output switch is open\r
+  * @retval None\r
+  */\r
+void SYSCFG_RIIOSwitchConfig(uint32_t RI_IOSwitch, FunctionalState NewState)\r
+{\r
+  uint32_t IOSwitchmask = 0;\r
+  \r
+  /* Check the parameters */\r
+  assert_param(IS_RI_IOSWITCH(RI_IOSwitch));\r
+  \r
+  /* Read Analog switch register index*/\r
+  IOSwitchmask = RI_IOSwitch >> 28;\r
+  \r
+  /** Get Bits[27:0] of the IO switch */\r
+  RI_IOSwitch  &= 0x0FFFFFFF;\r
+  \r
+  \r
+  if (NewState != DISABLE)\r
+  { \r
+    if (IOSwitchmask != 0)\r
+    {\r
+      /* Close the analog switches */\r
+      RI->ASCR1 |= RI_IOSwitch;\r
+    }\r
+    else\r
+    {\r
+      /* Open the analog switches */\r
+      RI->ASCR2 |= RI_IOSwitch;\r
+    }\r
+  }\r
+  else\r
+  {\r
+    if (IOSwitchmask != 0)\r
+    {\r
+      /* Close the analog switches */\r
+      RI->ASCR1 &= (~ (uint32_t)RI_IOSwitch);\r
+    }\r
+    else\r
+    {\r
+      /* Open the analog switches */\r
+      RI->ASCR2 &= (~ (uint32_t)RI_IOSwitch);\r
+    }\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  Enable or disable the switch control mode.\r
+  * @param  NewState: New state of the switch control mode. This parameter can\r
+  *         be ENABLE: ADC analog switches closed if the corresponding \r
+  *                    I/O switch is also closed. \r
+  *         or DISABLE: ADC analog switches open or controlled by the ADC interface.\r
+  * @retval None\r
+  */\r
+void SYSCFG_RISwitchControlModeCmd(FunctionalState NewState)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_FUNCTIONAL_STATE(NewState));  \r
+  \r
+  if (NewState != DISABLE)\r
+  { \r
+    /* Enable the Switch control mode */  \r
+    RI->ASCR1 |= (uint32_t) RI_ASCR1_SCM;\r
+  }\r
+  else\r
+  {\r
+    /* Disable the Switch control mode */  \r
+    RI->ASCR1 &= (uint32_t)(~RI_ASCR1_SCM);\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  Enable or disable Hysteresis of the input schmitt triger of Ports A..E \r
+  * @param  RI_Port: selects the GPIO Port.\r
+  *   This parameter can be one of the following values:\r
+  *     @arg RI_PortA : Port A is selected\r
+  *     @arg RI_PortB : Port B is selected\r
+  *     @arg RI_PortC : Port C is selected\r
+  *     @arg RI_PortD : Port D is selected\r
+  *     @arg RI_PortE : Port E is selected\r
+  *  @param RI_Pin : Selects the pin(s) on which to enable or disable hysteresis.\r
+  *    This parameter can any value from RI_Pin_x where x can be (0..15) or RI_Pin_All.\r
+  *  @param  NewState new state of the Hysteresis.\r
+  *   This parameter can be:\r
+  *      ENABLE so the Hysteresis is on\r
+  *   or DISABLE so the Hysteresis is off\r
+  * @retval None\r
+  */\r
+void SYSCFG_RIHysteresisConfig(uint8_t RI_Port, uint16_t RI_Pin,\r
+                             FunctionalState NewState)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_RI_PORT(RI_Port));\r
+  assert_param(IS_RI_PIN(RI_Pin));\r
+  assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+  \r
+  if(RI_Port == RI_PortA)\r
+  {  \r
+    if (NewState != DISABLE)\r
+    {\r
+      /* Hysteresis on */\r
+      RI->HYSCR1 &= (uint32_t)~((uint32_t)RI_Pin);\r
+    }\r
+    else\r
+    {\r
+      /* Hysteresis off */\r
+      RI->HYSCR1 |= (uint32_t) RI_Pin;\r
+    }\r
+  }\r
+  \r
+  else if(RI_Port == RI_PortB)\r
+  {\r
+  \r
+    if (NewState != DISABLE)\r
+    {\r
+      /* Hysteresis on */\r
+      RI->HYSCR1 &= (uint32_t) (~((uint32_t)RI_Pin) << 16);\r
+    }\r
+    else\r
+    {\r
+      /* Hysteresis off */\r
+      RI->HYSCR1 |= (uint32_t) ((uint32_t)(RI_Pin) << 16);\r
+    }\r
+  }  \r
+ \r
+  else if(RI_Port == RI_PortC)\r
+  {\r
+  \r
+    if (NewState != DISABLE)\r
+    {\r
+      /* Hysteresis on */\r
+      RI->HYSCR2 &= (uint32_t) (~((uint32_t)RI_Pin));\r
+    }\r
+    else\r
+    {\r
+      /* Hysteresis off */\r
+      RI->HYSCR2 |= (uint32_t) (RI_Pin );\r
+    }\r
+  } \r
+  else if(RI_Port == RI_PortD)\r
+  {\r
+    if (NewState != DISABLE)\r
+    {\r
+      /* Hysteresis on */\r
+      RI->HYSCR2 &= (uint32_t) (~((uint32_t)RI_Pin) << 16);\r
+    }\r
+    else\r
+    {\r
+      /* Hysteresis off */\r
+      RI->HYSCR2 |= (uint32_t) ((uint32_t)(RI_Pin) << 16);\r
+\r
+    }\r
+  }   \r
+  else /* RI_Port == RI_PortE */\r
+  {\r
+    if (NewState != DISABLE)\r
+    {\r
+      /* Hysteresis on */\r
+      RI->HYSCR3 &= (uint32_t) (~((uint32_t)RI_Pin));\r
+    }\r
+    else\r
+    {\r
+      /* Hysteresis off */\r
+      RI->HYSCR3 |= (uint32_t) (RI_Pin );\r
+    }\r
+  }   \r
+}\r
+\r
+/**\r
+  * @}\r
+  */ \r
+\r
+/**\r
+  * @}\r
+  */ \r
+\r
+/**\r
+  * @}\r
+  */ \r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/   \r

diff --git a/Demo/CORTEX_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_tim.c b/Demo/CORTEX_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_tim.c
new file mode 100644 (file)
index 0000000..964dfae
--- /dev/null
+++ b/Demo/CORTEX_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_tim.c
@@ -0,0 +1,2554 @@
+/**\r
+  ******************************************************************************\r
+  * @file    stm32l1xx_tim.c\r
+  * @author  MCD Application Team\r
+  * @version V1.0.0RC1\r
+  * @date    07/02/2010\r
+  * @brief   This file provides all the TIM firmware functions.\r
+  ******************************************************************************\r
+  * @copy\r
+  *\r
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+  *\r
+  * <h2><center>&copy; COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+  */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx_tim.h"\r
+#include "stm32l1xx_rcc.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+  * @{\r
+  */\r
+\r
+/** @defgroup TIM \r
+  * @brief TIM driver modules\r
+  * @{\r
+  */\r
+\r
+/** @defgroup TIM_Private_TypesDefinitions\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup TIM_Private_Defines\r
+  * @{\r
+  */\r
+\r
+/* ---------------------- TIM registers bit mask ------------------------ */\r
+#define SMCR_ETR_MASK               ((uint16_t)0x00FF) \r
+#define CCMR_OFFSET                 ((uint16_t)0x0018)\r
+#define CCER_CCE_SET                ((uint16_t)0x0001)  \r
+  \r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup TIM_Private_Macros\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup TIM_Private_Variables\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup TIM_Private_FunctionPrototypes\r
+  * @{\r
+  */\r
+\r
+static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,\r
+                       uint16_t TIM_ICFilter);\r
+static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,\r
+                       uint16_t TIM_ICFilter);\r
+static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,\r
+                       uint16_t TIM_ICFilter);\r
+static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,\r
+                       uint16_t TIM_ICFilter);\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup TIM_Private_Macros\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup TIM_Private_Variables\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup TIM_Private_FunctionPrototypes\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup TIM_Private_Functions\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @brief  Deinitializes the TIMx peripheral registers to their default reset values.\r
+  * @param  TIMx: where x can be 2 to 11 to select the TIM peripheral.\r
+  * @retval None\r
+  *   \r
+  */\r
+void TIM_DeInit(TIM_TypeDef* TIMx)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_ALL_PERIPH(TIMx)); \r
+   \r
+  if (TIMx == TIM2)\r
+  {\r
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, ENABLE);\r
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, DISABLE);\r
+  }\r
+  else if (TIMx == TIM3)\r
+  {\r
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, ENABLE);\r
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, DISABLE);\r
+  }\r
+  else if (TIMx == TIM4)\r
+  {\r
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, ENABLE);\r
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, DISABLE);\r
+  } \r
+\r
+  else if (TIMx == TIM6)\r
+  {\r
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, ENABLE);\r
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, DISABLE);\r
+  } \r
+  else if (TIMx == TIM7)\r
+  {\r
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, ENABLE);\r
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, DISABLE);\r
+  } \r
+\r
+  else if (TIMx == TIM9)\r
+  {\r
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, ENABLE);\r
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, DISABLE);\r
+  } \r
+  else if (TIMx == TIM10)\r
+  {\r
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, ENABLE);\r
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, DISABLE);\r
+  } \r
+  else\r
+  {\r
+    if (TIMx == TIM11)\r
+    {\r
+      RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM11, ENABLE);\r
+      RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM11, DISABLE); \r
+    }  \r
+  }\r
+     \r
+}\r
+\r
+/**\r
+  * @brief  Initializes the TIMx Time Base Unit peripheral according to \r
+  *         the specified parameters in the TIM_TimeBaseInitStruct.\r
+  * @param  TIMx: where x can be 2 to 11 to select the TIM peripheral.\r
+  * @param  TIM_TimeBaseInitStruct: pointer to a TIM_TimeBaseInitTypeDef\r
+  *         structure that contains the configuration information for\r
+  *         the specified TIM peripheral.\r
+  * @retval None\r
+  */\r
+void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct)\r
+{\r
+  uint16_t tmpcr1 = 0;\r
+\r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_ALL_PERIPH(TIMx)); \r
+  assert_param(IS_TIM_COUNTER_MODE(TIM_TimeBaseInitStruct->TIM_CounterMode));\r
+  assert_param(IS_TIM_CKD_DIV(TIM_TimeBaseInitStruct->TIM_ClockDivision));\r
+\r
+  tmpcr1 = TIMx->CR1;  \r
+\r
+  if(((TIMx) == TIM2) || ((TIMx) == TIM3) || ((TIMx) == TIM4))\r
+  {                                                                                    \r
+    /* Select the Counter Mode */\r
+    tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_CR1_DIR | TIM_CR1_CMS)));\r
+    tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_CounterMode;\r
+  }\r
+ \r
+  if(((TIMx) != TIM6) && ((TIMx) != TIM7))\r
+  {\r
+    /* Set the clock division */\r
+    tmpcr1 &= (uint16_t)(~((uint16_t)TIM_CR1_CKD));\r
+    tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_ClockDivision;\r
+  }\r
+\r
+  TIMx->CR1 = tmpcr1;\r
+\r
+  /* Set the Autoreload value */\r
+  TIMx->ARR = TIM_TimeBaseInitStruct->TIM_Period ;\r
+ \r
+  /* Set the Prescaler value */\r
+  TIMx->PSC = TIM_TimeBaseInitStruct->TIM_Prescaler;\r
+    \r
+  /* Generate an update event to reload the Prescaler value immediatly */\r
+  TIMx->EGR = TIM_PSCReloadMode_Immediate;          \r
+}\r
+\r
+/**\r
+  * @brief  Initializes the TIMx Channel1 according to the specified\r
+  *         parameters in the TIM_OCInitStruct.\r
+  * @param  TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral.\r
+  * @param  TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure\r
+  *         that contains the configuration information for the specified TIM \r
+  *         peripheral.\r
+  * @retval None\r
+  */\r
+void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)\r
+{\r
+  uint16_t tmpccmrx = 0, tmpccer = 0;\r
+   \r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_23491011_PERIPH(TIMx)); \r
+  assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));\r
+  assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));\r
+  assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));   \r
+  /* Disable the Channel 1: Reset the CC1E Bit */\r
+  TIMx->CCER &= (uint16_t)(~(uint16_t)TIM_CCER_CC1E);\r
+  \r
+  /* Get the TIMx CCER register value */\r
+  tmpccer = TIMx->CCER;\r
+  \r
+  /* Get the TIMx CCMR1 register value */\r
+  tmpccmrx = TIMx->CCMR1;\r
+    \r
+  /* Reset the Output Compare Mode Bits */\r
+  tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_OC1M));\r
+  tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_CC1S));\r
+  \r
+  /* Select the Output Compare Mode */\r
+  tmpccmrx |= TIM_OCInitStruct->TIM_OCMode;\r
+  \r
+  /* Reset the Output Polarity level */\r
+  tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1P));\r
+  /* Set the Output Compare Polarity */\r
+  tmpccer |= TIM_OCInitStruct->TIM_OCPolarity;\r
+  \r
+  /* Set the Output State */\r
+  tmpccer |= TIM_OCInitStruct->TIM_OutputState;\r
+  \r
+  /* Set the Capture Compare Register value */\r
+  TIMx->CCR1 = TIM_OCInitStruct->TIM_Pulse;\r
+  \r
+  /* Write to TIMx CCMR1 */\r
+  TIMx->CCMR1 = tmpccmrx;\r
+  \r
+  /* Write to TIMx CCER */\r
+  TIMx->CCER = tmpccer;\r
+}\r
+\r
+/**\r
+  * @brief  Initializes the TIMx Channel2 according to the specified\r
+  *         parameters in the TIM_OCInitStruct.\r
+  * @param  TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral.\r
+  * @param  TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure\r
+  *         that contains the configuration information for the specified TIM \r
+  *         peripheral.\r
+  * @retval None\r
+  */\r
+void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)\r
+{\r
+  uint16_t tmpccmrx = 0, tmpccer = 0;\r
+   \r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_2349_PERIPH(TIMx)); \r
+  assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));\r
+  assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));\r
+  assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));   \r
+  /* Disable the Channel 2: Reset the CC2E Bit */\r
+  TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC2E));\r
+  \r
+  /* Get the TIMx CCER register value */  \r
+  tmpccer = TIMx->CCER;\r
+  \r
+  /* Get the TIMx CCMR1 register value */\r
+  tmpccmrx = TIMx->CCMR1;\r
+    \r
+  /* Reset the Output Compare Mode Bits */\r
+  tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_OC2M));\r
+  \r
+  /* Select the Output Compare Mode */\r
+  tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8);\r
+  \r
+  /* Reset the Output Polarity level */\r
+  tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2P));\r
+  /* Set the Output Compare Polarity */\r
+  tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 4);\r
+  \r
+  /* Set the Output State */\r
+  tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 4);\r
+  \r
+  /* Set the Capture Compare Register value */\r
+  TIMx->CCR2 = TIM_OCInitStruct->TIM_Pulse;\r
+    \r
+  /* Write to TIMx CCMR1 */\r
+  TIMx->CCMR1 = tmpccmrx;\r
+  \r
+  /* Write to TIMx CCER */\r
+  TIMx->CCER = tmpccer;\r
+}\r
+\r
+/**\r
+  * @brief  Initializes the TIMx Channel3 according to the specified\r
+  *         parameters in the TIM_OCInitStruct.\r
+  * @param  TIMx: where x can be  2, 3 or 4 to select the TIM peripheral.\r
+  * @param  TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure\r
+  *         that contains the configuration information for the specified TIM \r
+  *         peripheral.\r
+  * @retval None\r
+  */\r
+void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)\r
+{\r
+  uint16_t tmpccmrx = 0, tmpccer = 0;\r
+   \r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_234_PERIPH(TIMx)); \r
+  assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));\r
+  assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));\r
+  assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));   \r
+\r
+  /* Disable the Channel 2: Reset the CC2E Bit */\r
+  TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC3E));\r
+  \r
+  /* Get the TIMx CCER register value */\r
+  tmpccer = TIMx->CCER;\r
+  \r
+  /* Get the TIMx CCMR2 register value */\r
+  tmpccmrx = TIMx->CCMR2;\r
+    \r
+  /* Reset the Output Compare Mode Bits */\r
+  tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_OC3M));\r
+  \r
+  /* Select the Output Compare Mode */\r
+  tmpccmrx |= TIM_OCInitStruct->TIM_OCMode;\r
+  \r
+  /* Reset the Output Polarity level */\r
+  tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3P));\r
+  /* Set the Output Compare Polarity */\r
+  tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 8);\r
+  \r
+  /* Set the Output State */\r
+  tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 8);\r
+  \r
+  /* Set the Capture Compare Register value */\r
+  TIMx->CCR3 = TIM_OCInitStruct->TIM_Pulse;\r
+  \r
+  /* Write to TIMx CCMR2 */\r
+  TIMx->CCMR2 = tmpccmrx;\r
+  \r
+  /* Write to TIMx CCER */\r
+  TIMx->CCER = tmpccer;\r
+}\r
+\r
+/**\r
+  * @brief  Initializes the TIMx Channel4 according to the specified\r
+  *         parameters in the TIM_OCInitStruct.\r
+  * @param  TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
+  * @param  TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure\r
+  *         that contains the configuration information for the specified TIM \r
+  *         peripheral.\r
+  * @retval None\r
+  */\r
+void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)\r
+{\r
+  uint16_t tmpccmrx = 0, tmpccer = 0;\r
+   \r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_234_PERIPH(TIMx)); \r
+  assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));\r
+  assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));\r
+  assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));   \r
+\r
+  /* Disable the Channel 2: Reset the CC4E Bit */\r
+  TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC4E));\r
+  \r
+  /* Get the TIMx CCER register value */\r
+  tmpccer = TIMx->CCER;\r
+  \r
+  /* Get the TIMx CCMR2 register value */\r
+  tmpccmrx = TIMx->CCMR2;\r
+    \r
+  /* Reset the Output Compare Mode Bits */\r
+  tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_OC4M));\r
+  \r
+  /* Select the Output Compare Mode */\r
+  tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8);\r
+  \r
+  /* Reset the Output Polarity level */\r
+  tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC4P));\r
+  /* Set the Output Compare Polarity */\r
+  tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 12);\r
+  \r
+  /* Set the Output State */\r
+  tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 12);\r
+  \r
+  /* Set the Capture Compare Register value */\r
+  TIMx->CCR4 = TIM_OCInitStruct->TIM_Pulse;\r
+  \r
+  /* Write to TIMx CCMR2 */  \r
+  TIMx->CCMR2 = tmpccmrx;\r
+  \r
+  /* Write to TIMx CCER */\r
+  TIMx->CCER = tmpccer;\r
+}\r
+\r
+/**\r
+  * @brief  Initializes the TIM peripheral according to the specified\r
+  *         parameters in the TIM_ICInitStruct.\r
+  * @param  TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral.\r
+  * @param  TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure\r
+  *         that contains the configuration information for the specified TIM \r
+  *         peripheral.\r
+  * @retval None\r
+  */\r
+void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_23491011_PERIPH(TIMx));\r
+  assert_param(IS_TIM_IC_POLARITY(TIM_ICInitStruct->TIM_ICPolarity));\r
+  assert_param(IS_TIM_IC_SELECTION(TIM_ICInitStruct->TIM_ICSelection));\r
+  assert_param(IS_TIM_IC_PRESCALER(TIM_ICInitStruct->TIM_ICPrescaler));\r
+  assert_param(IS_TIM_IC_FILTER(TIM_ICInitStruct->TIM_ICFilter));\r
+  \r
+  if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1)\r
+  {\r
+    /* TI1 Configuration */\r
+    TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,\r
+               TIM_ICInitStruct->TIM_ICSelection,\r
+               TIM_ICInitStruct->TIM_ICFilter);\r
+    /* Set the Input Capture Prescaler value */\r
+    TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);\r
+  }\r
+  else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_2)\r
+  {\r
+    /* TI2 Configuration */\r
+    TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,\r
+               TIM_ICInitStruct->TIM_ICSelection,\r
+               TIM_ICInitStruct->TIM_ICFilter);\r
+    /* Set the Input Capture Prescaler value */\r
+    TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);\r
+  }\r
+  else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_3)\r
+  {\r
+    /* TI3 Configuration */\r
+    TI3_Config(TIMx,  TIM_ICInitStruct->TIM_ICPolarity,\r
+               TIM_ICInitStruct->TIM_ICSelection,\r
+               TIM_ICInitStruct->TIM_ICFilter);\r
+    /* Set the Input Capture Prescaler value */\r
+    TIM_SetIC3Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);\r
+  }\r
+  else\r
+  {\r
+    /* TI4 Configuration */\r
+    TI4_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,\r
+               TIM_ICInitStruct->TIM_ICSelection,\r
+               TIM_ICInitStruct->TIM_ICFilter);\r
+    /* Set the Input Capture Prescaler value */\r
+    TIM_SetIC4Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  Configures the TIM peripheral according to the specified\r
+  *         parameters in the TIM_ICInitStruct to measure an external PWM signal.\r
+  * @param  TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral.\r
+  * @param  TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure\r
+  *         that contains the configuration information for the specified TIM \r
+  *         peripheral.\r
+  * @retval None\r
+  */\r
+void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct)\r
+{\r
+  uint16_t icoppositepolarity = TIM_ICPolarity_Rising;\r
+  uint16_t icoppositeselection = TIM_ICSelection_DirectTI;\r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_2349_PERIPH(TIMx));\r
+  /* Select the Opposite Input Polarity */\r
+  if (TIM_ICInitStruct->TIM_ICPolarity == TIM_ICPolarity_Rising)\r
+  {\r
+    icoppositepolarity = TIM_ICPolarity_Falling;\r
+  }\r
+  else\r
+  {\r
+    icoppositepolarity = TIM_ICPolarity_Rising;\r
+  }\r
+  /* Select the Opposite Input */\r
+  if (TIM_ICInitStruct->TIM_ICSelection == TIM_ICSelection_DirectTI)\r
+  {\r
+    icoppositeselection = TIM_ICSelection_IndirectTI;\r
+  }\r
+  else\r
+  {\r
+    icoppositeselection = TIM_ICSelection_DirectTI;\r
+  }\r
+  if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1)\r
+  {\r
+    /* TI1 Configuration */\r
+    TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection,\r
+               TIM_ICInitStruct->TIM_ICFilter);\r
+    /* Set the Input Capture Prescaler value */\r
+    TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);\r
+    /* TI2 Configuration */\r
+    TI2_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter);\r
+    /* Set the Input Capture Prescaler value */\r
+    TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);\r
+  }\r
+  else\r
+  { \r
+    /* TI2 Configuration */\r
+    TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection,\r
+               TIM_ICInitStruct->TIM_ICFilter);\r
+    /* Set the Input Capture Prescaler value */\r
+    TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);\r
+    /* TI1 Configuration */\r
+    TI1_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter);\r
+    /* Set the Input Capture Prescaler value */\r
+    TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  Fills each TIM_TimeBaseInitStruct member with its default value.\r
+  * @param  TIM_TimeBaseInitStruct : pointer to a TIM_TimeBaseInitTypeDef\r
+  *         structure which will be initialized.\r
+  * @retval None\r
+  */\r
+void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct)\r
+{\r
+  /* Set the default configuration */\r
+  TIM_TimeBaseInitStruct->TIM_Period = 0xFFFF;\r
+  TIM_TimeBaseInitStruct->TIM_Prescaler = 0x0000;\r
+  TIM_TimeBaseInitStruct->TIM_ClockDivision = TIM_CKD_DIV1;\r
+  TIM_TimeBaseInitStruct->TIM_CounterMode = TIM_CounterMode_Up;\r
+}\r
+\r
+/**\r
+  * @brief  Fills each TIM_OCInitStruct member with its default value.\r
+  * @param  TIM_OCInitStruct : pointer to a TIM_OCInitTypeDef structure which will\r
+  *         be initialized.\r
+  * @retval None\r
+  */\r
+void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct)\r
+{\r
+  /* Set the default configuration */\r
+  TIM_OCInitStruct->TIM_OCMode = TIM_OCMode_Timing;\r
+  TIM_OCInitStruct->TIM_OutputState = TIM_OutputState_Disable;\r
+  TIM_OCInitStruct->TIM_Pulse = 0x0000;\r
+  TIM_OCInitStruct->TIM_OCPolarity = TIM_OCPolarity_High;\r
+}\r
+\r
+/**\r
+  * @brief  Fills each TIM_ICInitStruct member with its default value.\r
+  * @param  TIM_ICInitStruct : pointer to a TIM_ICInitTypeDef structure which will\r
+  *         be initialized.\r
+  * @retval None\r
+  */\r
+void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct)\r
+{\r
+  /* Set the default configuration */\r
+  TIM_ICInitStruct->TIM_Channel = TIM_Channel_1;\r
+  TIM_ICInitStruct->TIM_ICPolarity = TIM_ICPolarity_Rising;\r
+  TIM_ICInitStruct->TIM_ICSelection = TIM_ICSelection_DirectTI;\r
+  TIM_ICInitStruct->TIM_ICPrescaler = TIM_ICPSC_DIV1;\r
+  TIM_ICInitStruct->TIM_ICFilter = 0x00;\r
+}\r
+\r
+/**\r
+  * @brief  Enables or disables the specified TIM peripheral.\r
+  * @param  TIMx: where x can be 2 to 11 to select the TIMx peripheral.\r
+  * @param  NewState: new state of the TIMx peripheral.\r
+  *         This parameter can be: ENABLE or DISABLE.\r
+  * @retval None\r
+  */\r
+void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_ALL_PERIPH(TIMx)); \r
+  assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+  \r
+  if (NewState != DISABLE)\r
+  {\r
+    /* Enable the TIM Counter */\r
+    TIMx->CR1 |= TIM_CR1_CEN;\r
+  }\r
+  else\r
+  {\r
+    /* Disable the TIM Counter */\r
+    TIMx->CR1 &= (uint16_t)(~((uint16_t)TIM_CR1_CEN));\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  Enables or disables the specified TIM interrupts.\r
+  * @param  TIMx: where x can be 2 to 11 to select the TIMx peripheral.\r
+  * @param  TIM_IT: specifies the TIM interrupts sources to be enabled or disabled.\r
+  *   This parameter can be any combination of the following values:\r
+  *     @arg TIM_IT_Update: TIM update Interrupt source\r
+  *     @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source\r
+  *     @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source\r
+  *     @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source\r
+  *     @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source\r
+  *     @arg TIM_IT_Trigger: TIM Trigger Interrupt source\r
+  * @note \r
+  *   - TIM6 and TIM7 can only generate an update interrupt.  \r
+  *   - TIM_IT_CC2, TIM_IT_CC3, TIM_IT_CC4 and TIM_IT_Trigger can not be used with TIM10 and TIM11\r
+  *   - TIM_IT_CC3, TIM_IT_CC4 can not be used with TIM9.   \r
+  * @param  NewState: new state of the TIM interrupts.\r
+  *         This parameter can be: ENABLE or DISABLE.\r
+  * @retval None\r
+  */\r
+void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState)\r
+{  \r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
+  assert_param(IS_TIM_IT(TIM_IT));\r
+  assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+  \r
+  if (NewState != DISABLE)\r
+  {\r
+    /* Enable the Interrupt sources */\r
+    TIMx->DIER |= TIM_IT;\r
+  }\r
+  else\r
+  {\r
+    /* Disable the Interrupt sources */\r
+    TIMx->DIER &= (uint16_t)~TIM_IT;\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  Configures the TIMx event to be generate by software.\r
+  * @param  TIMx: where x can be 2 to 11 to select the TIM peripheral.\r
+  * @param  TIM_EventSource: specifies the event source.\r
+  *   This parameter can be one or more of the following values:          \r
+  *     @arg TIM_EventSource_Update: Timer update Event source\r
+  *     @arg TIM_EventSource_CC1: Timer Capture Compare 1 Event source\r
+  *     @arg TIM_EventSource_CC2: Timer Capture Compare 2 Event source\r
+  *     @arg TIM_EventSource_CC3: Timer Capture Compare 3 Event source\r
+  *     @arg TIM_EventSource_CC4: Timer Capture Compare 4 Event source \r
+  *     @arg TIM_EventSource_Trigger: Timer Trigger Event source\r
+  * @note \r
+  *   - TIM6 and TIM7 can only generate an update event. \r
+  *   - TIM9 can only generate an update event, Capture Compare 1 event, \r
+  *     Capture Compare 2 event and TIM_EventSource_Trigger.  \r
+  *   - TIM10 and TIM11 can only generate an update event and Capture Compare 1 event.            \r
+  * @retval None\r
+  */\r
+void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource)\r
+{ \r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
+  assert_param(IS_TIM_EVENT_SOURCE(TIM_EventSource)); \r
+  /* Set the event sources */\r
+  TIMx->EGR = TIM_EventSource;\r
+}\r
+\r
+/**\r
+  * @brief  Configures the TIMx\92s DMA interface.\r
+  * @param  TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
+  * @param  TIM_DMABase: DMA Base address.\r
+  *   This parameter can be one of the following values:\r
+  *     @arg TIM_DMABase_CR, TIM_DMABase_CR2, TIM_DMABase_SMCR,\r
+  *          TIM_DMABase_DIER, TIM_DMABase_SR, TIM_DMABase_EGR,\r
+  *          TIM_DMABase_CCMR1, TIM_DMABase_CCMR2, TIM_DMABase_CCER,\r
+  *          TIM_DMABase_CNT, TIM_DMABase_PSC, TIM_DMABase_ARR,\r
+  *          TIM_DMABase_CCR1, TIM_DMABase_CCR2, TIM_DMABase_CCR3, \r
+  *          TIM_DMABase_CCR4, TIM_DMABase_DCR.\r
+  * @param  TIM_DMABurstLength: DMA Burst length.\r
+  *   This parameter can be one value between:\r
+  *   TIM_DMABurstLength_1Byte and TIM_DMABurstLength_18Bytes.\r
+  * @retval None\r
+  */\r
+void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_234_PERIPH(TIMx));\r
+  assert_param(IS_TIM_DMA_BASE(TIM_DMABase)); \r
+  assert_param(IS_TIM_DMA_LENGTH(TIM_DMABurstLength));\r
+  /* Set the DMA Base and the DMA Burst Length */\r
+  TIMx->DCR = TIM_DMABase | TIM_DMABurstLength;\r
+}\r
+\r
+/**\r
+  * @brief  Enables or disables the TIMx\92s DMA Requests.\r
+  * @param  TIMx: where x can be 2, 3, 4, 6 or 7 to select the TIM peripheral. \r
+  * @param  TIM_DMASource: specifies the DMA Request sources.\r
+  *   This parameter can be any combination of the following values:\r
+  *     @arg TIM_DMA_Update: TIM update Interrupt source\r
+  *     @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source\r
+  *     @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source\r
+  *     @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source\r
+  *     @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source\r
+  *     @arg TIM_DMA_Trigger: TIM Trigger DMA source\r
+  * @param  NewState: new state of the DMA Request sources.\r
+  *   This parameter can be: ENABLE or DISABLE.\r
+  * @retval None\r
+  */\r
+void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState)\r
+{ \r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_23467_PERIPH(TIMx));\r
+  assert_param(IS_TIM_DMA_SOURCE(TIM_DMASource));\r
+  assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+  \r
+  if (NewState != DISABLE)\r
+  {\r
+    /* Enable the DMA sources */\r
+    TIMx->DIER |= TIM_DMASource; \r
+  }\r
+  else\r
+  {\r
+    /* Disable the DMA sources */\r
+    TIMx->DIER &= (uint16_t)~TIM_DMASource;\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  Configures the TIMx interrnal Clock\r
+  * @param  TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral.\r
+  * @retval None\r
+  */\r
+void TIM_InternalClockConfig(TIM_TypeDef* TIMx)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_2349_PERIPH(TIMx));\r
+  /* Disable slave mode to clock the prescaler directly with the internal clock */\r
+  TIMx->SMCR &=  (uint16_t)(~((uint16_t)TIM_SMCR_SMS));\r
+}\r
+\r
+/**\r
+  * @brief  Configures the TIMx Internal Trigger as External Clock\r
+  * @param  TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral.\r
+  * @param  TIM_ITRSource: Trigger source.\r
+  *   This parameter can be one of the following values:\r
+  * @param  TIM_TS_ITR0: Internal Trigger 0\r
+  * @param  TIM_TS_ITR1: Internal Trigger 1\r
+  * @param  TIM_TS_ITR2: Internal Trigger 2\r
+  * @param  TIM_TS_ITR3: Internal Trigger 3\r
+  * @retval None\r
+  */\r
+void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_2349_PERIPH(TIMx));\r
+  assert_param(IS_TIM_INTERNAL_TRIGGER_SELECTION(TIM_InputTriggerSource));\r
+  /* Select the Internal Trigger */\r
+  TIM_SelectInputTrigger(TIMx, TIM_InputTriggerSource);\r
+  /* Select the External clock mode1 */\r
+  TIMx->SMCR |= TIM_SlaveMode_External1;\r
+}\r
+\r
+/**\r
+  * @brief  Configures the TIMx Trigger as External Clock\r
+  * @param  TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral.\r
+  * @param  TIM_TIxExternalCLKSource: Trigger source.\r
+  *   This parameter can be one of the following values:\r
+  *     @arg TIM_TIxExternalCLK1Source_TI1ED: TI1 Edge Detector\r
+  *     @arg TIM_TIxExternalCLK1Source_TI1: Filtered Timer Input 1\r
+  *     @arg TIM_TIxExternalCLK1Source_TI2: Filtered Timer Input 2\r
+  * @param  TIM_ICPolarity: specifies the TIx Polarity.\r
+  *   This parameter can be one of the following values:\r
+  *     @arg TIM_ICPolarity_Rising\r
+  *     @arg TIM_ICPolarity_Falling\r
+  * @param  ICFilter : specifies the filter value.\r
+  *   This parameter must be a value between 0x0 and 0xF.\r
+  * @retval None\r
+  */\r
+void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource,\r
+                                uint16_t TIM_ICPolarity, uint16_t ICFilter)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_2349_PERIPH(TIMx));\r
+  assert_param(IS_TIM_IC_POLARITY(TIM_ICPolarity));\r
+  assert_param(IS_TIM_IC_FILTER(ICFilter));\r
+  \r
+  /* Configure the Timer Input Clock Source */\r
+  if (TIM_TIxExternalCLKSource == TIM_TIxExternalCLK1Source_TI2)\r
+  {\r
+    TI2_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter);\r
+  }\r
+  else\r
+  {\r
+    TI1_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter);\r
+  }\r
+  /* Select the Trigger source */\r
+  TIM_SelectInputTrigger(TIMx, TIM_TIxExternalCLKSource);\r
+  /* Select the External clock mode1 */\r
+  TIMx->SMCR |= TIM_SlaveMode_External1;\r
+}\r
+\r
+/**\r
+  * @brief  Configures the External clock Mode1\r
+  * @param  TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral.\r
+  * @param  TIM_ExtTRGPrescaler: The external Trigger Prescaler.\r
+  *   This parameter can be one of the following values:\r
+  *     @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.\r
+  *     @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.\r
+  *     @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.\r
+  *     @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.\r
+  * @param  TIM_ExtTRGPolarity: The external Trigger Polarity.\r
+  *   This parameter can be one of the following values:\r
+  *     @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.\r
+  *     @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.\r
+  * @param  ExtTRGFilter: External Trigger Filter.\r
+  *   This parameter must be a value between 0x00 and 0x0F\r
+  * @retval None\r
+  */\r
+void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,\r
+                             uint16_t ExtTRGFilter)\r
+{\r
+  uint16_t tmpsmcr = 0;\r
+  \r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_2349_PERIPH(TIMx));\r
+  assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));\r
+  assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));\r
+  assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));\r
+  \r
+  /* Configure the ETR Clock source */\r
+  TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);\r
+  \r
+  /* Get the TIMx SMCR register value */\r
+  tmpsmcr = TIMx->SMCR;\r
+  /* Reset the SMS Bits */\r
+  tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS));\r
+  /* Select the External clock mode1 */\r
+  tmpsmcr |= TIM_SlaveMode_External1;\r
+  /* Select the Trigger selection : ETRF */\r
+  tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_TS));\r
+  tmpsmcr |= TIM_TS_ETRF;\r
+  /* Write to TIMx SMCR */\r
+  TIMx->SMCR = tmpsmcr;\r
+}\r
+\r
+/**\r
+  * @brief  Configures the External clock Mode2\r
+  * @param  TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral.\r
+  * @param  TIM_ExtTRGPrescaler: The external Trigger Prescaler.\r
+  *   This parameter can be one of the following values:\r
+  *     @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.\r
+  *     @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.\r
+  *     @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.\r
+  *     @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.\r
+  * @param  TIM_ExtTRGPolarity: The external Trigger Polarity.\r
+  *   This parameter can be one of the following values:\r
+  *     @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.\r
+  *     @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.\r
+  * @param  ExtTRGFilter: External Trigger Filter.\r
+  *   This parameter must be a value between 0x00 and 0x0F\r
+  * @retval None\r
+  */\r
+void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, \r
+                             uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_23491011_PERIPH(TIMx));\r
+  assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));\r
+  assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));\r
+  assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));\r
+  \r
+  /* Configure the ETR Clock source */\r
+  TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);\r
+  /* Enable the External clock mode2 */\r
+  TIMx->SMCR |= TIM_SMCR_ECE;\r
+}\r
+\r
+/**\r
+  * @brief  Configures the TIMx External Trigger (ETR).\r
+  * @param  TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral.\r
+  * @param  TIM_ExtTRGPrescaler: The external Trigger Prescaler.\r
+  *   This parameter can be one of the following values:\r
+  *     @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.\r
+  *     @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.\r
+  *     @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.\r
+  *     @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.\r
+  * @param  TIM_ExtTRGPolarity: The external Trigger Polarity.\r
+  *   This parameter can be one of the following values:\r
+  *     @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.\r
+  *     @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.\r
+  * @param  ExtTRGFilter: External Trigger Filter.\r
+  *   This parameter must be a value between 0x00 and 0x0F\r
+  * @retval None\r
+  */\r
+void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,\r
+                   uint16_t ExtTRGFilter)\r
+{\r
+  uint16_t tmpsmcr = 0;\r
+  \r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_23491011_PERIPH(TIMx));\r
+  assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));\r
+  assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));\r
+  assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));\r
+  \r
+  tmpsmcr = TIMx->SMCR;\r
+  /* Reset the ETR Bits */\r
+  tmpsmcr &= SMCR_ETR_MASK;\r
+  /* Set the Prescaler, the Filter value and the Polarity */\r
+  tmpsmcr |= (uint16_t)(TIM_ExtTRGPrescaler | (uint16_t)(TIM_ExtTRGPolarity | (uint16_t)(ExtTRGFilter << (uint16_t)8)));\r
+  /* Write to TIMx SMCR */\r
+  TIMx->SMCR = tmpsmcr;\r
+}\r
+\r
+/**\r
+  * @brief  Configures the TIMx Prescaler.\r
+  * @param  TIMx: where x can be 2 to 11 to select the TIM peripheral.\r
+  * @param  Prescaler: specifies the Prescaler Register value\r
+  * @param  TIM_PSCReloadMode: specifies the TIM Prescaler Reload mode\r
+  *   This parameter can be one of the following values:\r
+  *     @arg TIM_PSCReloadMode_Update: The Prescaler is loaded at the update event.\r
+  *     @arg TIM_PSCReloadMode_Immediate: The Prescaler is loaded immediatly.\r
+  * @retval None\r
+  */\r
+void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
+  assert_param(IS_TIM_PRESCALER_RELOAD(TIM_PSCReloadMode));\r
+  \r
+  /* Set the Prescaler value */\r
+  TIMx->PSC = Prescaler;\r
+  /* Set or reset the UG Bit */\r
+  TIMx->EGR = TIM_PSCReloadMode;\r
+}\r
+\r
+/**\r
+  * @brief  Specifies the TIMx Counter Mode to be used.\r
+  * @param  TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
+  * @param  TIM_CounterMode: specifies the Counter Mode to be used\r
+  *   This parameter can be one of the following values:\r
+  *     @arg TIM_CounterMode_Up: TIM Up Counting Mode\r
+  *     @arg TIM_CounterMode_Down: TIM Down Counting Mode\r
+  *     @arg TIM_CounterMode_CenterAligned1: TIM Center Aligned Mode1\r
+  *     @arg TIM_CounterMode_CenterAligned2: TIM Center Aligned Mode2\r
+  *     @arg TIM_CounterMode_CenterAligned3: TIM Center Aligned Mode3\r
+  * @retval None\r
+  */\r
+void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode)\r
+{\r
+  uint16_t tmpcr1 = 0;\r
+  \r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_234_PERIPH(TIMx));\r
+  assert_param(IS_TIM_COUNTER_MODE(TIM_CounterMode));\r
+  \r
+  tmpcr1 = TIMx->CR1;\r
+  /* Reset the CMS and DIR Bits */\r
+  tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_CR1_DIR | TIM_CR1_CMS)));\r
+  /* Set the Counter Mode */\r
+  tmpcr1 |= TIM_CounterMode;\r
+  /* Write to TIMx CR1 register */\r
+  TIMx->CR1 = tmpcr1;\r
+}\r
+\r
+/**\r
+  * @brief  Selects the Input Trigger source\r
+  * @param  TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral.\r
+  * @param  TIM_InputTriggerSource: The Input Trigger source.\r
+  *   This parameter can be one of the following values:\r
+  *     @arg TIM_TS_ITR0: Internal Trigger 0\r
+  *     @arg TIM_TS_ITR1: Internal Trigger 1\r
+  *     @arg TIM_TS_ITR2: Internal Trigger 2\r
+  *     @arg TIM_TS_ITR3: Internal Trigger 3\r
+  *     @arg TIM_TS_TI1F_ED: TI1 Edge Detector\r
+  *     @arg TIM_TS_TI1FP1: Filtered Timer Input 1\r
+  *     @arg TIM_TS_TI2FP2: Filtered Timer Input 2\r
+  *     @arg TIM_TS_ETRF: External Trigger input\r
+  * @retval None\r
+  */\r
+void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource)\r
+{\r
+  uint16_t tmpsmcr = 0;\r
+\r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_23491011_PERIPH(TIMx)); \r
+  assert_param(IS_TIM_TRIGGER_SELECTION(TIM_InputTriggerSource));\r
+\r
+  /* Get the TIMx SMCR register value */\r
+  tmpsmcr = TIMx->SMCR;\r
+  /* Reset the TS Bits */\r
+  tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_TS));\r
+  /* Set the Input Trigger source */\r
+  tmpsmcr |= TIM_InputTriggerSource;\r
+  /* Write to TIMx SMCR */\r
+  TIMx->SMCR = tmpsmcr;\r
+}\r
+\r
+/**\r
+  * @brief  Configures the TIMx Encoder Interface.\r
+  * @param  TIMx: where x can be  2, 3 or 4 to select the TIM peripheral.\r
+  * @param  TIM_EncoderMode: specifies the TIMx Encoder Mode.\r
+  *   This parameter can be one of the following values:\r
+  *     @arg TIM_EncoderMode_TI1: Counter counts on TI1FP1 edge depending on TI2FP2 level.\r
+  *     @arg TIM_EncoderMode_TI2: Counter counts on TI2FP2 edge depending on TI1FP1 level.\r
+  *     @arg TIM_EncoderMode_TI12: Counter counts on both TI1FP1 and TI2FP2 edges depending\r
+  *                                on the level of the other input.\r
+  * @param  TIM_IC1Polarity: specifies the IC1 Polarity\r
+  *   This parmeter can be one of the following values:\r
+  *     @arg TIM_ICPolarity_Falling: IC Falling edge.\r
+  *     @arg TIM_ICPolarity_Rising: IC Rising edge.\r
+  * @param  TIM_IC2Polarity: specifies the IC2 Polarity\r
+  *   This parmeter can be one of the following values:\r
+  *     @arg TIM_ICPolarity_Falling: IC Falling edge.\r
+  *     @arg TIM_ICPolarity_Rising: IC Rising edge.\r
+  * @retval None\r
+  */\r
+void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode,\r
+                                uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity)\r
+{\r
+  uint16_t tmpsmcr = 0;\r
+  uint16_t tmpccmr1 = 0;\r
+  uint16_t tmpccer = 0;\r
+    \r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_234_PERIPH(TIMx));\r
+  assert_param(IS_TIM_ENCODER_MODE(TIM_EncoderMode));\r
+  assert_param(IS_TIM_IC_POLARITY(TIM_IC1Polarity));\r
+  assert_param(IS_TIM_IC_POLARITY(TIM_IC2Polarity));\r
+  \r
+  /* Get the TIMx SMCR register value */\r
+  tmpsmcr = TIMx->SMCR;\r
+  /* Get the TIMx CCMR1 register value */\r
+  tmpccmr1 = TIMx->CCMR1;\r
+  /* Get the TIMx CCER register value */\r
+  tmpccer = TIMx->CCER;\r
+  /* Set the encoder Mode */\r
+  tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS));\r
+  tmpsmcr |= TIM_EncoderMode;\r
+  /* Select the Capture Compare 1 and the Capture Compare 2 as input */\r
+  tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC1S)) & (uint16_t)(~((uint16_t)TIM_CCMR1_CC2S)));\r
+  tmpccmr1 |= TIM_CCMR1_CC1S_0 | TIM_CCMR1_CC2S_0;\r
+  /* Set the TI1 and the TI2 Polarities */\r
+  tmpccer &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCER_CC1P)) & ((uint16_t)~((uint16_t)TIM_CCER_CC2P)));\r
+   tmpccer |= (uint16_t)(TIM_IC1Polarity | (uint16_t)(TIM_IC2Polarity << (uint16_t)4));\r
+  /* Write to TIMx SMCR */\r
+  TIMx->SMCR = tmpsmcr;\r
+  /* Write to TIMx CCMR1 */\r
+  TIMx->CCMR1 = tmpccmr1;\r
+  /* Write to TIMx CCER */\r
+  TIMx->CCER = tmpccer;\r
+}\r
+\r
+/**\r
+  * @brief  Forces the TIMx output 1 waveform to active or inactive level.\r
+  * @param  TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral.\r
+  * @param  TIM_ForcedAction: specifies the forced Action to be set to the output waveform.\r
+  *   This parameter can be one of the following values:\r
+  *     @arg TIM_ForcedAction_Active: Force active level on OC1REF\r
+  *     @arg TIM_ForcedAction_InActive: Force inactive level on OC1REF.\r
+  * @retval None\r
+  */\r
+void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)\r
+{\r
+  uint16_t tmpccmr1 = 0;\r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_23491011_PERIPH(TIMx));\r
+  assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));\r
+  tmpccmr1 = TIMx->CCMR1;\r
+  /* Reset the OC1M Bits */\r
+  tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1M);\r
+  /* Configure The Forced output Mode */\r
+  tmpccmr1 |= TIM_ForcedAction;\r
+  /* Write to TIMx CCMR1 register */\r
+  TIMx->CCMR1 = tmpccmr1;\r
+}\r
+ \r
+/**\r
+  * @brief  Forces the TIMx output 2 waveform to active or inactive level.\r
+  * @param  TIMx: where x can be 2, 3, 4 or 9 to select the TIM \r
+  *   peripheral.\r
+  * @param  TIM_ForcedAction: specifies the forced Action to be set to the output waveform.\r
+  *   This parameter can be one of the following values:\r
+  *     @arg TIM_ForcedAction_Active: Force active level on OC2REF\r
+  *     @arg TIM_ForcedAction_InActive: Force inactive level on OC2REF.\r
+  * @retval None\r
+  */\r
+void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)\r
+{\r
+  uint16_t tmpccmr1 = 0;\r
+  \r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_2349_PERIPH(TIMx));\r
+  assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));\r
+  \r
+  tmpccmr1 = TIMx->CCMR1;\r
+  /* Reset the OC2M Bits */\r
+  tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2M);\r
+  /* Configure The Forced output Mode */\r
+  tmpccmr1 |= (uint16_t)(TIM_ForcedAction << 8);\r
+  /* Write to TIMx CCMR1 register */\r
+  TIMx->CCMR1 = tmpccmr1;\r
+}\r
+\r
+/**\r
+  * @brief  Forces the TIMx output 3 waveform to active or inactive level.\r
+  * @param  TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
+  * @param  TIM_ForcedAction: specifies the forced Action to be set to the output waveform.\r
+  *   This parameter can be one of the following values:\r
+  *     @arg TIM_ForcedAction_Active: Force active level on OC3REF\r
+  *     @arg TIM_ForcedAction_InActive: Force inactive level on OC3REF.\r
+  * @retval None\r
+  */\r
+void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)\r
+{\r
+  uint16_t tmpccmr2 = 0;\r
+  \r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_234_PERIPH(TIMx));\r
+  assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));\r
+  \r
+  tmpccmr2 = TIMx->CCMR2;\r
+  /* Reset the OC1M Bits */\r
+  tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3M);\r
+  /* Configure The Forced output Mode */\r
+  tmpccmr2 |= TIM_ForcedAction;\r
+  /* Write to TIMx CCMR2 register */\r
+  TIMx->CCMR2 = tmpccmr2;\r
+}\r
+\r
+/**\r
+  * @brief  Forces the TIMx output 4 waveform to active or inactive level.\r
+  * @param  TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
+  * @param  TIM_ForcedAction: specifies the forced Action to be set to the output waveform.\r
+  *   This parameter can be one of the following values:\r
+  *     @arg TIM_ForcedAction_Active: Force active level on OC4REF\r
+  *     @arg TIM_ForcedAction_InActive: Force inactive level on OC4REF.\r
+  * @retval None\r
+  */\r
+void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)\r
+{\r
+  uint16_t tmpccmr2 = 0;\r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_234_PERIPH(TIMx));\r
+  assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));\r
+  \r
+  tmpccmr2 = TIMx->CCMR2;\r
+  /* Reset the OC2M Bits */\r
+  tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4M);\r
+  /* Configure The Forced output Mode */\r
+  tmpccmr2 |= (uint16_t)(TIM_ForcedAction << 8);\r
+  /* Write to TIMx CCMR2 register */\r
+  TIMx->CCMR2 = tmpccmr2;\r
+}\r
+\r
+/**\r
+  * @brief  Enables or disables TIMx peripheral Preload register on ARR.\r
+  * @param  TIMx: where x can be  2 to 11 to select the TIM peripheral.\r
+  * @param  NewState: new state of the TIMx peripheral Preload register\r
+  *   This parameter can be: ENABLE or DISABLE.\r
+  * @retval None\r
+  */\r
+void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
+  assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+  \r
+  if (NewState != DISABLE)\r
+  {\r
+    /* Set the ARR Preload Bit */\r
+    TIMx->CR1 |= TIM_CR1_ARPE;\r
+  }\r
+  else\r
+  {\r
+    /* Reset the ARR Preload Bit */\r
+    TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_ARPE);\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  Selects the TIMx peripheral Capture Compare DMA source.\r
+  * @param  TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
+  * @param  NewState: new state of the Capture Compare DMA source\r
+  *   This parameter can be: ENABLE or DISABLE.\r
+  * @retval None\r
+  */\r
+void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_234_PERIPH(TIMx));\r
+  assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+  \r
+  if (NewState != DISABLE)\r
+  {\r
+    /* Set the CCDS Bit */\r
+    TIMx->CR2 |= TIM_CR2_CCDS;\r
+  }\r
+  else\r
+  {\r
+    /* Reset the CCDS Bit */\r
+    TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_CCDS);\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  Enables or disables the TIMx peripheral Preload register on CCR1.\r
+  * @param  TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral.\r
+  * @param  TIM_OCPreload: new state of the TIMx peripheral Preload register\r
+  *   This parameter can be one of the following values:\r
+  *     @arg TIM_OCPreload_Enable\r
+  *     @arg TIM_OCPreload_Disable\r
+  * @retval None\r
+  */\r
+void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)\r
+{\r
+  uint16_t tmpccmr1 = 0;\r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_23491011_PERIPH(TIMx));\r
+  assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));\r
+  \r
+  tmpccmr1 = TIMx->CCMR1;\r
+  /* Reset the OC1PE Bit */\r
+  tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1PE);\r
+  /* Enable or Disable the Output Compare Preload feature */\r
+  tmpccmr1 |= TIM_OCPreload;\r
+  /* Write to TIMx CCMR1 register */\r
+  TIMx->CCMR1 = tmpccmr1;\r
+}\r
+\r
+/**\r
+  * @brief  Enables or disables the TIMx peripheral Preload register on CCR2.\r
+  * @param  TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral.\r
+  * @param  TIM_OCPreload: new state of the TIMx peripheral Preload register\r
+  *   This parameter can be one of the following values:\r
+  *     @arg TIM_OCPreload_Enable\r
+  *     @arg TIM_OCPreload_Disable\r
+  * @retval None\r
+  */\r
+void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)\r
+{\r
+  uint16_t tmpccmr1 = 0;\r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_2349_PERIPH(TIMx));\r
+  assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));\r
+  \r
+  tmpccmr1 = TIMx->CCMR1;\r
+  /* Reset the OC2PE Bit */\r
+  tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2PE);\r
+  /* Enable or Disable the Output Compare Preload feature */\r
+  tmpccmr1 |= (uint16_t)(TIM_OCPreload << 8);\r
+  /* Write to TIMx CCMR1 register */\r
+  TIMx->CCMR1 = tmpccmr1;\r
+}\r
+\r
+/**\r
+  * @brief  Enables or disables the TIMx peripheral Preload register on CCR3.\r
+  * @param  TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
+  * @param  TIM_OCPreload: new state of the TIMx peripheral Preload register\r
+  *   This parameter can be one of the following values:\r
+  *     @arg TIM_OCPreload_Enable\r
+  *     @arg TIM_OCPreload_Disable\r
+  * @retval None\r
+  */\r
+void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)\r
+{\r
+  uint16_t tmpccmr2 = 0;\r
+  \r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_234_PERIPH(TIMx));\r
+  assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));\r
+  \r
+  tmpccmr2 = TIMx->CCMR2;\r
+  /* Reset the OC3PE Bit */\r
+  tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3PE);\r
+  /* Enable or Disable the Output Compare Preload feature */\r
+  tmpccmr2 |= TIM_OCPreload;\r
+  /* Write to TIMx CCMR2 register */\r
+  TIMx->CCMR2 = tmpccmr2;\r
+}\r
+\r
+/**\r
+  * @brief  Enables or disables the TIMx peripheral Preload register on CCR4.\r
+  * @param  TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
+  * @param  TIM_OCPreload: new state of the TIMx peripheral Preload register\r
+  *   This parameter can be one of the following values:\r
+  *     @arg TIM_OCPreload_Enable\r
+  *     @arg TIM_OCPreload_Disable\r
+  * @retval None\r
+  */\r
+void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)\r
+{\r
+  uint16_t tmpccmr2 = 0;\r
+  \r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_234_PERIPH(TIMx));\r
+  assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));\r
+  \r
+  tmpccmr2 = TIMx->CCMR2;\r
+  /* Reset the OC4PE Bit */\r
+  tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4PE);\r
+  /* Enable or Disable the Output Compare Preload feature */\r
+  tmpccmr2 |= (uint16_t)(TIM_OCPreload << 8);\r
+  /* Write to TIMx CCMR2 register */\r
+  TIMx->CCMR2 = tmpccmr2;\r
+}\r
+\r
+/**\r
+  * @brief  Configures the TIMx Output Compare 1 Fast feature.\r
+  * @param  TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral.\r
+  * @param  TIM_OCFast: new state of the Output Compare Fast Enable Bit.\r
+  *   This parameter can be one of the following values:\r
+  *     @arg TIM_OCFast_Enable: TIM output compare fast enable\r
+  *     @arg TIM_OCFast_Disable: TIM output compare fast disable\r
+  * @retval None\r
+  */\r
+void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)\r
+{\r
+  uint16_t tmpccmr1 = 0;\r
+  \r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_23491011_PERIPH(TIMx));\r
+  assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));\r
+  \r
+  /* Get the TIMx CCMR1 register value */\r
+  tmpccmr1 = TIMx->CCMR1;\r
+  /* Reset the OC1FE Bit */\r
+  tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1FE);\r
+  /* Enable or Disable the Output Compare Fast Bit */\r
+  tmpccmr1 |= TIM_OCFast;\r
+  /* Write to TIMx CCMR1 */\r
+  TIMx->CCMR1 = tmpccmr1;\r
+}\r
+\r
+/**\r
+  * @brief  Configures the TIMx Output Compare 2 Fast feature.\r
+  * @param  TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral.\r
+  * @param  TIM_OCFast: new state of the Output Compare Fast Enable Bit.\r
+  *   This parameter can be one of the following values:\r
+  *     @arg TIM_OCFast_Enable: TIM output compare fast enable\r
+  *     @arg TIM_OCFast_Disable: TIM output compare fast disable\r
+  * @retval None\r
+  */\r
+void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)\r
+{\r
+  uint16_t tmpccmr1 = 0;\r
+  \r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_2349_PERIPH(TIMx));\r
+  assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));\r
+  \r
+  /* Get the TIMx CCMR1 register value */\r
+  tmpccmr1 = TIMx->CCMR1;\r
+  /* Reset the OC2FE Bit */\r
+  tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2FE);\r
+  /* Enable or Disable the Output Compare Fast Bit */\r
+  tmpccmr1 |= (uint16_t)(TIM_OCFast << 8);\r
+  /* Write to TIMx CCMR1 */\r
+  TIMx->CCMR1 = tmpccmr1;\r
+}\r
+\r
+/**\r
+  * @brief  Configures the TIMx Output Compare 3 Fast feature.\r
+  * @param  TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
+  * @param  TIM_OCFast: new state of the Output Compare Fast Enable Bit.\r
+  *   This parameter can be one of the following values:\r
+  *     @arg TIM_OCFast_Enable: TIM output compare fast enable\r
+  *     @arg TIM_OCFast_Disable: TIM output compare fast disable\r
+  * @retval None\r
+  */\r
+void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)\r
+{\r
+  uint16_t tmpccmr2 = 0;\r
+  \r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_234_PERIPH(TIMx));\r
+  assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));\r
+  \r
+  /* Get the TIMx CCMR2 register value */\r
+  tmpccmr2 = TIMx->CCMR2;\r
+  /* Reset the OC3FE Bit */\r
+  tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3FE);\r
+  /* Enable or Disable the Output Compare Fast Bit */\r
+  tmpccmr2 |= TIM_OCFast;\r
+  /* Write to TIMx CCMR2 */\r
+  TIMx->CCMR2 = tmpccmr2;\r
+}\r
+\r
+/**\r
+  * @brief  Configures the TIMx Output Compare 4 Fast feature.\r
+  * @param  TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
+  * @param  TIM_OCFast: new state of the Output Compare Fast Enable Bit.\r
+  *   This parameter can be one of the following values:\r
+  *     @arg TIM_OCFast_Enable: TIM output compare fast enable\r
+  *     @arg TIM_OCFast_Disable: TIM output compare fast disable\r
+  * @retval None\r
+  */\r
+void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)\r
+{\r
+  uint16_t tmpccmr2 = 0;\r
+  \r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_234_PERIPH(TIMx));\r
+  assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));\r
+  \r
+  /* Get the TIMx CCMR2 register value */\r
+  tmpccmr2 = TIMx->CCMR2;\r
+  /* Reset the OC4FE Bit */\r
+  tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4FE);\r
+  /* Enable or Disable the Output Compare Fast Bit */\r
+  tmpccmr2 |= (uint16_t)(TIM_OCFast << 8);\r
+  /* Write to TIMx CCMR2 */\r
+  TIMx->CCMR2 = tmpccmr2;\r
+}\r
+\r
+/**\r
+  * @brief  Clears or safeguards the OCREF1 signal on an external event\r
+  * @param  TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral.\r
+  * @param  TIM_OCClear: new state of the Output Compare Clear Enable Bit.\r
+  *   This parameter can be one of the following values:\r
+  *     @arg TIM_OCClear_Enable: TIM Output clear enable\r
+  *     @arg TIM_OCClear_Disable: TIM Output clear disable\r
+  * @retval None\r
+  */\r
+void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)\r
+{\r
+  uint16_t tmpccmr1 = 0;\r
+  \r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_23491011_PERIPH(TIMx));\r
+  assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));\r
+  \r
+  tmpccmr1 = TIMx->CCMR1;\r
+  /* Reset the OC1CE Bit */\r
+  tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1CE);\r
+  /* Enable or Disable the Output Compare Clear Bit */\r
+  tmpccmr1 |= TIM_OCClear;\r
+  /* Write to TIMx CCMR1 register */\r
+  TIMx->CCMR1 = tmpccmr1;\r
+}\r
+\r
+/**\r
+  * @brief  Clears or safeguards the OCREF2 signal on an external event\r
+  * @param  TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral.\r
+  * @param  TIM_OCClear: new state of the Output Compare Clear Enable Bit.\r
+\r
+  *   This parameter can be one of the following values:\r
+  *     @arg TIM_OCClear_Enable: TIM Output clear enable\r
+  *     @arg TIM_OCClear_Disable: TIM Output clear disable\r
+  * @retval None\r
+  */\r
+void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)\r
+{\r
+  uint16_t tmpccmr1 = 0;\r
+  \r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_2349_PERIPH(TIMx));\r
+  assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));\r
+  \r
+  tmpccmr1 = TIMx->CCMR1;\r
+  /* Reset the OC2CE Bit */\r
+  tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2CE);\r
+  /* Enable or Disable the Output Compare Clear Bit */\r
+  tmpccmr1 |= (uint16_t)(TIM_OCClear << 8);\r
+  /* Write to TIMx CCMR1 register */\r
+  TIMx->CCMR1 = tmpccmr1;\r
+}\r
+\r
+/**\r
+  * @brief  Clears or safeguards the OCREF3 signal on an external event\r
+  * @param  TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
+  * @param  TIM_OCClear: new state of the Output Compare Clear Enable Bit.\r
+  *   This parameter can be one of the following values:\r
+  *     @arg TIM_OCClear_Enable: TIM Output clear enable\r
+  *     @arg TIM_OCClear_Disable: TIM Output clear disable\r
+  * @retval None\r
+  */\r
+void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)\r
+{\r
+  uint16_t tmpccmr2 = 0;\r
+  \r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_234_PERIPH(TIMx));\r
+  assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));\r
+  \r
+  tmpccmr2 = TIMx->CCMR2;\r
+  /* Reset the OC3CE Bit */\r
+  tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3CE);\r
+  /* Enable or Disable the Output Compare Clear Bit */\r
+  tmpccmr2 |= TIM_OCClear;\r
+  /* Write to TIMx CCMR2 register */\r
+  TIMx->CCMR2 = tmpccmr2;\r
+}\r
+\r
+/**\r
+  * @brief  Clears or safeguards the OCREF4 signal on an external event\r
+  * @param  TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
+  * @param  TIM_OCClear: new state of the Output Compare Clear Enable Bit.\r
+  *   This parameter can be one of the following values:\r
+  *     @arg TIM_OCClear_Enable: TIM Output clear enable\r
+  *     @arg TIM_OCClear_Disable: TIM Output clear disable\r
+  * @retval None\r
+  */\r
+void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)\r
+{\r
+  uint16_t tmpccmr2 = 0;\r
+  \r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_234_PERIPH(TIMx));\r
+  assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));\r
+  \r
+  tmpccmr2 = TIMx->CCMR2;\r
+  /* Reset the OC4CE Bit */\r
+  tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4CE);\r
+  /* Enable or Disable the Output Compare Clear Bit */\r
+  tmpccmr2 |= (uint16_t)(TIM_OCClear << 8);\r
+  /* Write to TIMx CCMR2 register */\r
+  TIMx->CCMR2 = tmpccmr2;\r
+}\r
+\r
+/**\r
+  * @brief  Configures the TIMx channel 1 polarity.\r
+  * @param  TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral.\r
+  * @param  TIM_OCPolarity: specifies the OC1 Polarity\r
+  *   This parmeter can be one of the following values:\r
+  *     @arg TIM_OCPolarity_High: Output Compare active high\r
+  *     @arg TIM_OCPolarity_Low: Output Compare active low\r
+  * @retval None\r
+  */\r
+void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)\r
+{\r
+  uint16_t tmpccer = 0;\r
+  \r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_23491011_PERIPH(TIMx));\r
+  assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));\r
+  \r
+  tmpccer = TIMx->CCER;\r
+  /* Set or Reset the CC1P Bit */\r
+  tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC1P);\r
+  tmpccer |= TIM_OCPolarity;\r
+  /* Write to TIMx CCER register */\r
+  TIMx->CCER = tmpccer;\r
+}\r
+\r
+/**\r
+  * @brief  Configures the TIMx channel 2 polarity.\r
+  * @param  TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral.\r
+  * @param  TIM_OCPolarity: specifies the OC2 Polarity\r
+  *   This parmeter can be one of the following values:\r
+  *     @arg TIM_OCPolarity_High: Output Compare active high\r
+  *     @arg TIM_OCPolarity_Low: Output Compare active low\r
+  * @retval None\r
+  */\r
+void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)\r
+{\r
+  uint16_t tmpccer = 0;\r
+  \r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_2349_PERIPH(TIMx));\r
+  assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));\r
+  \r
+  tmpccer = TIMx->CCER;\r
+  /* Set or Reset the CC2P Bit */\r
+  tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC2P);\r
+  tmpccer |= (uint16_t)(TIM_OCPolarity << 4);\r
+  /* Write to TIMx CCER register */\r
+  TIMx->CCER = tmpccer;\r
+}\r
+\r
+/**\r
+  * @brief  Configures the TIMx channel 3 polarity.\r
+  * @param  TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
+  * @param  TIM_OCPolarity: specifies the OC3 Polarity\r
+  *   This parmeter can be one of the following values:\r
+  *     @arg TIM_OCPolarity_High: Output Compare active high\r
+  *     @arg TIM_OCPolarity_Low: Output Compare active low\r
+  * @retval None\r
+  */\r
+void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)\r
+{\r
+  uint16_t tmpccer = 0;\r
+  \r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_234_PERIPH(TIMx));\r
+  assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));\r
+  \r
+  tmpccer = TIMx->CCER;\r
+  /* Set or Reset the CC3P Bit */\r
+  tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC3P);\r
+  tmpccer |= (uint16_t)(TIM_OCPolarity << 8);\r
+  /* Write to TIMx CCER register */\r
+  TIMx->CCER = tmpccer;\r
+}\r
+\r
+/**\r
+  * @brief  Configures the TIMx channel 4 polarity.\r
+  * @param  TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
+  * @param  TIM_OCPolarity: specifies the OC4 Polarity\r
+  *   This parmeter can be one of the following values:\r
+  *     @arg TIM_OCPolarity_High: Output Compare active high\r
+  *     @arg TIM_OCPolarity_Low: Output Compare active low\r
+  * @retval None\r
+  */\r
+void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)\r
+{\r
+  uint16_t tmpccer = 0;\r
+  \r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_234_PERIPH(TIMx));\r
+  assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));\r
+  \r
+  tmpccer = TIMx->CCER;\r
+  /* Set or Reset the CC4P Bit */\r
+  tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC4P);\r
+  tmpccer |= (uint16_t)(TIM_OCPolarity << 12);\r
+  /* Write to TIMx CCER register */\r
+  TIMx->CCER = tmpccer;\r
+}\r
+\r
+/**\r
+  * @brief  Enables or disables the TIM Capture Compare Channel x.\r
+  * @param  TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral.\r
+  * @param  TIM_Channel: specifies the TIM Channel\r
+  *   This parmeter can be one of the following values:\r
+  *     @arg TIM_Channel_1: TIM Channel 1\r
+  *     @arg TIM_Channel_2: TIM Channel 2\r
+  *     @arg TIM_Channel_3: TIM Channel 3\r
+  *     @arg TIM_Channel_4: TIM Channel 4\r
+  * @param  TIM_CCx: specifies the TIM Channel CCxE bit new state.\r
+  *   This parameter can be: TIM_CCx_Enable or TIM_CCx_Disable. \r
+  * @retval None\r
+  */\r
+void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx)\r
+{\r
+  uint16_t tmp = 0;\r
+\r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_23491011_PERIPH(TIMx)); \r
+  assert_param(IS_TIM_CCX(TIM_CCx));\r
+\r
+  tmp = CCER_CCE_SET << TIM_Channel;\r
+\r
+  /* Reset the CCxE Bit */\r
+  TIMx->CCER &= (uint16_t)~ tmp;\r
+\r
+  /* Set or reset the CCxE Bit */ \r
+  TIMx->CCER |=  (uint16_t)(TIM_CCx << TIM_Channel);\r
+}\r
+\r
+/**\r
+  * @brief  Selects the TIM Ouput Compare Mode.\r
+  * @note   This function disables the selected channel before changing the Ouput\r
+  *         Compare Mode.\r
+  *         User has to enable this channel using TIM_CCxCmd and TIM_CCxNCmd functions.\r
+  * @param  TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral.\r
+  * @param  TIM_Channel: specifies the TIM Channel\r
+  *   This parmeter can be one of the following values:\r
+  *     @arg TIM_Channel_1: TIM Channel 1\r
+  *     @arg TIM_Channel_2: TIM Channel 2\r
+  *     @arg TIM_Channel_3: TIM Channel 3\r
+  *     @arg TIM_Channel_4: TIM Channel 4\r
+  * @param  TIM_OCMode: specifies the TIM Output Compare Mode.\r
+  *   This paramter can be one of the following values:\r
+  *     @arg TIM_OCMode_Timing\r
+  *     @arg TIM_OCMode_Active\r
+  *     @arg TIM_OCMode_Toggle\r
+  *     @arg TIM_OCMode_PWM1\r
+  *     @arg TIM_OCMode_PWM2\r
+  *     @arg TIM_ForcedAction_Active\r
+  *     @arg TIM_ForcedAction_InActive\r
+  * @retval None\r
+  */\r
+void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode)\r
+{\r
+  uint32_t tmp = 0;\r
+  uint16_t tmp1 = 0;\r
+\r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_23491011_PERIPH(TIMx));  \r
+  assert_param(IS_TIM_OCM(TIM_OCMode));\r
+  \r
+  tmp = (uint32_t) TIMx;\r
+  tmp += CCMR_OFFSET;\r
+\r
+  tmp1 = CCER_CCE_SET << (uint16_t)TIM_Channel;\r
+\r
+  /* Disable the Channel: Reset the CCxE Bit */\r
+  TIMx->CCER &= (uint16_t) ~tmp1;\r
+\r
+  if((TIM_Channel == TIM_Channel_1) ||(TIM_Channel == TIM_Channel_3))\r
+  {\r
+    tmp += (TIM_Channel>>1);\r
+\r
+    /* Reset the OCxM bits in the CCMRx register */\r
+    *(__IO uint32_t *) tmp &= (uint32_t)~((uint32_t)TIM_CCMR1_OC1M);\r
+   \r
+    /* Configure the OCxM bits in the CCMRx register */\r
+    *(__IO uint32_t *) tmp |= TIM_OCMode;\r
+  }\r
+  else\r
+  {\r
+    tmp += (uint16_t)(TIM_Channel - (uint16_t)4)>> (uint16_t)1;\r
+\r
+    /* Reset the OCxM bits in the CCMRx register */\r
+    *(__IO uint32_t *) tmp &= (uint32_t)~((uint32_t)TIM_CCMR1_OC2M);\r
+    \r
+    /* Configure the OCxM bits in the CCMRx register */\r
+    *(__IO uint32_t *) tmp |= (uint16_t)(TIM_OCMode << 8);\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  Enables or Disables the TIMx Update event.\r
+  * @param  TIMx: where x can be 2 to 11 to select the TIM peripheral.\r
+  * @param  NewState: new state of the TIMx UDIS bit\r
+  *   This parameter can be: ENABLE or DISABLE.\r
+  * @retval None\r
+  */\r
+void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
+  assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+  \r
+  if (NewState != DISABLE)\r
+  {\r
+    /* Set the Update Disable Bit */\r
+    TIMx->CR1 |= TIM_CR1_UDIS;\r
+  }\r
+  else\r
+  {\r
+    /* Reset the Update Disable Bit */\r
+    TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_UDIS);\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  Configures the TIMx Update Request Interrupt source.\r
+  * @param  TIMx: where x can be 2 to 11 to select the TIM peripheral.\r
+  * @param  TIM_UpdateSource: specifies the Update source.\r
+  *   This parameter can be one of the following values:\r
+  *     @arg TIM_UpdateSource_Regular: Source of update is the counter overflow/underflow\r
+                                       or the setting of UG bit, or an update generation\r
+                                       through the slave mode controller.\r
+  *     @arg TIM_UpdateSource_Global: Source of update is counter overflow/underflow.\r
+  * @retval None\r
+  */\r
+void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
+  assert_param(IS_TIM_UPDATE_SOURCE(TIM_UpdateSource));\r
+  \r
+  if (TIM_UpdateSource != TIM_UpdateSource_Global)\r
+  {\r
+    /* Set the URS Bit */\r
+    TIMx->CR1 |= TIM_CR1_URS;\r
+  }\r
+  else\r
+  {\r
+    /* Reset the URS Bit */\r
+    TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_URS);\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  Enables or disables the TIMx\92s Hall sensor interface.\r
+  * @param  TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
+  * @param  NewState: new state of the TIMx Hall sensor interface.\r
+  *   This parameter can be: ENABLE or DISABLE.\r
+  * @retval None\r
+  */\r
+void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_234_PERIPH(TIMx));\r
+  assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+  \r
+  if (NewState != DISABLE)\r
+  {\r
+    /* Set the TI1S Bit */\r
+    TIMx->CR2 |= TIM_CR2_TI1S;\r
+  }\r
+  else\r
+  {\r
+    /* Reset the TI1S Bit */\r
+    TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_TI1S);\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  Selects the TIMx\92s One Pulse Mode.\r
+  * @param  TIMx: where x can be 2 to 11 to select the TIM peripheral.\r
+  * @param  TIM_OPMode: specifies the OPM Mode to be used.\r
+  *   This parameter can be one of the following values:\r
+  *     @arg TIM_OPMode_Single\r
+  *     @arg TIM_OPMode_Repetitive\r
+  * @retval None\r
+  */\r
+void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
+  assert_param(IS_TIM_OPM_MODE(TIM_OPMode));\r
+  \r
+  /* Reset the OPM Bit */\r
+  TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_OPM);\r
+  /* Configure the OPM Mode */\r
+  TIMx->CR1 |= TIM_OPMode;\r
+}\r
+\r
+/**\r
+  * @brief  Selects the TIMx Trigger Output Mode.\r
+  * @param  TIMx: where x can be 2, 3, 4, 6, 7 or 9 to select the TIM peripheral.\r
+  * @param  TIM_TRGOSource: specifies the Trigger Output source.\r
+  *   This paramter can be one of the following values:\r
+  *\r
+  *  - For all TIMx\r
+  *     @arg TIM_TRGOSource_Reset:  The UG bit in the TIM_EGR register is used as the trigger output (TRGO).\r
+  *     @arg TIM_TRGOSource_Enable: The Counter Enable CEN is used as the trigger output (TRGO).\r
+  *     @arg TIM_TRGOSource_Update: The update event is selected as the trigger output (TRGO).\r
+  *\r
+  *  - For all TIMx except TIM6 and TIM7\r
+  *     @arg TIM_TRGOSource_OC1: The trigger output sends a positive pulse when the CC1IF flag\r
+  *                              is to be set, as soon as a capture or compare match occurs (TRGO).\r
+  *     @arg TIM_TRGOSource_OC1Ref: OC1REF signal is used as the trigger output (TRGO).\r
+\r
+  *  - For all TIMx except TIM6, TIM7, TIM10 and TIM11\r
+  *     @arg TIM_TRGOSource_OC2Ref: OC2REF signal is used as the trigger output (TRGO).\r
+\r
+  *  - For TIM2, TIM3 and TIM4\r
+  *     @arg TIM_TRGOSource_OC3Ref: OC3REF signal is used as the trigger output (TRGO).\r
+  *     @arg TIM_TRGOSource_OC4Ref: OC4REF signal is used as the trigger output (TRGO).\r
+  *\r
+  * @retval None\r
+  */\r
+void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_234679_PERIPH(TIMx));\r
+  assert_param(IS_TIM_TRGO_SOURCE(TIM_TRGOSource));\r
+\r
+  /* Reset the MMS Bits */\r
+  TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_MMS);\r
+  /* Select the TRGO source */\r
+  TIMx->CR2 |=  TIM_TRGOSource;\r
+}\r
+\r
+/**\r
+  * @brief  Selects the TIMx Slave Mode.\r
+  * @param  TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral.\r
+  * @param  TIM_SlaveMode: specifies the Timer Slave Mode.\r
+  *   This paramter can be one of the following values:\r
+  *     @arg TIM_SlaveMode_Reset: Rising edge of the selected trigger signal (TRGI) re-initializes\r
+  *                               the counter and triggers an update of the registers.\r
+  *     @arg TIM_SlaveMode_Gated:     The counter clock is enabled when the trigger signal (TRGI) is high.\r
+  *     @arg TIM_SlaveMode_Trigger:   The counter starts at a rising edge of the trigger TRGI.\r
+  *     @arg TIM_SlaveMode_External1: Rising edges of the selected trigger (TRGI) clock the counter.\r
+  * @retval None\r
+  */\r
+void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_2349_PERIPH(TIMx)); \r
+  assert_param(IS_TIM_SLAVE_MODE(TIM_SlaveMode));\r
+  \r
+  /* Reset the SMS Bits */\r
+  TIMx->SMCR &= (uint16_t)~((uint16_t)TIM_SMCR_SMS);\r
+  /* Select the Slave Mode */\r
+  TIMx->SMCR |= TIM_SlaveMode;\r
+}\r
+\r
+/**\r
+  * @brief  Sets or Resets the TIMx Master/Slave Mode.\r
+  * @param  TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral.\r
+  * @param  TIM_MasterSlaveMode: specifies the Timer Master Slave Mode.\r
+  *   This paramter can be one of the following values:\r
+  *     @arg TIM_MasterSlaveMode_Enable: synchronization between the current timer\r
+  *                                      and its slaves (through TRGO).\r
+  *     @arg TIM_MasterSlaveMode_Disable: No action\r
+  * @retval None\r
+  */\r
+void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_2349_PERIPH(TIMx));\r
+  assert_param(IS_TIM_MSM_STATE(TIM_MasterSlaveMode));\r
+  \r
+  /* Reset the MSM Bit */\r
+  TIMx->SMCR &= (uint16_t)~((uint16_t)TIM_SMCR_MSM);\r
+  \r
+  /* Set or Reset the MSM Bit */\r
+  TIMx->SMCR |= TIM_MasterSlaveMode;\r
+}\r
+\r
+/**\r
+  * @brief  Sets the TIMx Counter Register value\r
+  * @param  TIMx: where x can be 2 to 11 to select the TIM peripheral.\r
+  * @param  Counter: specifies the Counter register new value.\r
+  * @retval None\r
+  */\r
+void TIM_SetCounter(TIM_TypeDef* TIMx, uint32_t Counter)\r
+{\r
+  /* Check the parameters */\r
+   assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
+   \r
+  /* Set the Counter Register value */\r
+  TIMx->CNT = Counter;\r
+}\r
+\r
+/**\r
+  * @brief  Sets the TIMx Autoreload Register value\r
+  * @param  TIMx: where x can be 2 to 11 to select the TIM peripheral.\r
+  * @param  Autoreload: specifies the Autoreload register new value.\r
+  * @retval None\r
+  */\r
+void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint32_t Autoreload)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
+  \r
+  /* Set the Autoreload Register value */\r
+  TIMx->ARR = Autoreload;\r
+}\r
+\r
+/**\r
+  * @brief  Sets the TIMx Capture Compare1 Register value\r
+  * @param  TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral.\r
+  * @param  Compare1: specifies the Capture Compare1 register new value.\r
+  * @retval None\r
+\r
+  */\r
+void TIM_SetCompare1(TIM_TypeDef* TIMx, uint32_t Compare1)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_23491011_PERIPH(TIMx));\r
+  \r
+  /* Set the Capture Compare1 Register value */\r
+  TIMx->CCR1 = Compare1;\r
+}\r
+\r
+/**\r
+  * @brief  Sets the TIMx Capture Compare2 Register value\r
+  * @param  TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral.\r
+  * @param  Compare2: specifies the Capture Compare2 register new value.\r
+  * @retval None\r
+\r
+  */\r
+void TIM_SetCompare2(TIM_TypeDef* TIMx, uint32_t Compare2)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_2349_PERIPH(TIMx));\r
+  \r
+  /* Set the Capture Compare2 Register value */\r
+  TIMx->CCR2 = Compare2;\r
+}\r
+\r
+/**\r
+  * @brief  Sets the TIMx Capture Compare3 Register value\r
+  * @param  TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
+  * @param  Compare3: specifies the Capture Compare3 register new value.\r
+  * @retval None\r
+\r
+  */\r
+void TIM_SetCompare3(TIM_TypeDef* TIMx, uint32_t Compare3)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_234_PERIPH(TIMx));\r
+  \r
+  /* Set the Capture Compare3 Register value */\r
+  TIMx->CCR3 = Compare3;\r
+}\r
+\r
+/**\r
+  * @brief  Sets the TIMx Capture Compare4 Register value\r
+  * @param  TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
+  * @param  Compare4: specifies the Capture Compare4 register new value.\r
+  * @retval None\r
+\r
+  */\r
+void TIM_SetCompare4(TIM_TypeDef* TIMx, uint32_t Compare4)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_234_PERIPH(TIMx));\r
+  \r
+  /* Set the Capture Compare4 Register value */\r
+  TIMx->CCR4 = Compare4;\r
+}\r
+\r
+/**\r
+  * @brief  Sets the TIMx Input Capture 1 prescaler.\r
+  * @param  TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral.\r
+  * @param  TIM_ICPSC: specifies the Input Capture1 prescaler new value.\r
+  *   This parameter can be one of the following values:\r
+  *     @arg TIM_ICPSC_DIV1: no prescaler\r
+  *     @arg TIM_ICPSC_DIV2: capture is done once every 2 events\r
+  *     @arg TIM_ICPSC_DIV4: capture is done once every 4 events\r
+  *     @arg TIM_ICPSC_DIV8: capture is done once every 8 events\r
+  * @retval None\r
+  */\r
+void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_23491011_PERIPH(TIMx));\r
+  assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));\r
+  \r
+  /* Reset the IC1PSC Bits */\r
+  TIMx->CCMR1 &= (uint16_t)~((uint16_t)TIM_CCMR1_IC1PSC);\r
+  /* Set the IC1PSC value */\r
+  TIMx->CCMR1 |= TIM_ICPSC;\r
+}\r
+\r
+/**\r
+  * @brief  Sets the TIMx Input Capture 2 prescaler.\r
+  * @param  TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral.\r
+  * @param  TIM_ICPSC: specifies the Input Capture2 prescaler new value.\r
+  *   This parameter can be one of the following values:\r
+  *     @arg TIM_ICPSC_DIV1: no prescaler\r
+  *     @arg TIM_ICPSC_DIV2: capture is done once every 2 events\r
+  *     @arg TIM_ICPSC_DIV4: capture is done once every 4 events\r
+  *     @arg TIM_ICPSC_DIV8: capture is done once every 8 events\r
+  * @retval None\r
+  */\r
+void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_2349_PERIPH(TIMx));\r
+  assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));\r
+  \r
+  /* Reset the IC2PSC Bits */\r
+  TIMx->CCMR1 &= (uint16_t)~((uint16_t)TIM_CCMR1_IC2PSC);\r
+  /* Set the IC2PSC value */\r
+  TIMx->CCMR1 |= (uint16_t)(TIM_ICPSC << 8);\r
+}\r
+\r
+/**\r
+  * @brief  Sets the TIMx Input Capture 3 prescaler.\r
+  * @param  TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
+  * @param  TIM_ICPSC: specifies the Input Capture3 prescaler new value.\r
+  *   This parameter can be one of the following values:\r
+  *     @arg TIM_ICPSC_DIV1: no prescaler\r
+  *     @arg TIM_ICPSC_DIV2: capture is done once every 2 events\r
+  *     @arg TIM_ICPSC_DIV4: capture is done once every 4 events\r
+  *     @arg TIM_ICPSC_DIV8: capture is done once every 8 events\r
+  * @retval None\r
+  */\r
+void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_234_PERIPH(TIMx));\r
+  assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));\r
+  \r
+  /* Reset the IC3PSC Bits */\r
+  TIMx->CCMR2 &= (uint16_t)~((uint16_t)TIM_CCMR2_IC3PSC);\r
+  /* Set the IC3PSC value */\r
+  TIMx->CCMR2 |= TIM_ICPSC;\r
+}\r
+\r
+/**\r
+  * @brief  Sets the TIMx Input Capture 4 prescaler.\r
+  * @param  TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
+  * @param  TIM_ICPSC: specifies the Input Capture4 prescaler new value.\r
+  *   This parameter can be one of the following values:\r
+  *     @arg TIM_ICPSC_DIV1: no prescaler\r
+  *     @arg TIM_ICPSC_DIV2: capture is done once every 2 events\r
+  *     @arg TIM_ICPSC_DIV4: capture is done once every 4 events\r
+  *     @arg TIM_ICPSC_DIV8: capture is done once every 8 events\r
+  * @retval None\r
+  */\r
+void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)\r
+{  \r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_234_PERIPH(TIMx));\r
+  assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));\r
+  \r
+  /* Reset the IC4PSC Bits */\r
+  TIMx->CCMR2 &= (uint16_t)~((uint16_t)TIM_CCMR2_IC4PSC);\r
+  /* Set the IC4PSC value */\r
+  TIMx->CCMR2 |= (uint16_t)(TIM_ICPSC << 8);\r
+}\r
+\r
+/**\r
+  * @brief  Sets the TIMx Clock Division value.\r
+  * @param  TIMx: where x can be  2, 3, 4, 9, 10 or 11 to select the TIM peripheral.\r
+  * @param  TIM_CKD: specifies the clock division value.\r
+  *   This parameter can be one of the following value:\r
+  *     @arg TIM_CKD_DIV1: TDTS = Tck_tim\r
+  *     @arg TIM_CKD_DIV2: TDTS = 2*Tck_tim\r
+  *     @arg TIM_CKD_DIV4: TDTS = 4*Tck_tim\r
+  * @retval None\r
+  */\r
+void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_23491011_PERIPH(TIMx));\r
+  assert_param(IS_TIM_CKD_DIV(TIM_CKD));\r
+  \r
+  /* Reset the CKD Bits */\r
+  TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_CKD);\r
+  /* Set the CKD value */\r
+  TIMx->CR1 |= TIM_CKD;\r
+}\r
+\r
+/**\r
+  * @brief  Gets the TIMx Input Capture 1 value.\r
+  * @param  TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral.\r
+  * @retval Capture Compare 1 Register value.\r
+\r
+  */\r
+uint32_t TIM_GetCapture1(TIM_TypeDef* TIMx)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_23491011_PERIPH(TIMx));\r
+  \r
+  /* Get the Capture 1 Register value */\r
+  return TIMx->CCR1;\r
+}\r
+\r
+/**\r
+  * @brief  Gets the TIMx Input Capture 2 value.\r
+  * @param  TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral.\r
+  * @retval Capture Compare 2 Register value.\r
+\r
+  */\r
+uint32_t TIM_GetCapture2(TIM_TypeDef* TIMx)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_2349_PERIPH(TIMx));\r
+  \r
+  /* Get the Capture 2 Register value */\r
+  return TIMx->CCR2;\r
+}\r
+\r
+/**\r
+  * @brief  Gets the TIMx Input Capture 3 value.\r
+  * @param  TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
+  * @retval Capture Compare 3 Register value.\r
+  */\r
+uint32_t TIM_GetCapture3(TIM_TypeDef* TIMx)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_234_PERIPH(TIMx)); \r
+  \r
+  /* Get the Capture 3 Register value */\r
+  return TIMx->CCR3;\r
+}\r
+\r
+/**\r
+  * @brief  Gets the TIMx Input Capture 4 value.\r
+  * @param  TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
+  * @retval Capture Compare 4 Register value.\r
+  */\r
+uint32_t TIM_GetCapture4(TIM_TypeDef* TIMx)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_234_PERIPH(TIMx));\r
+  \r
+  /* Get the Capture 4 Register value */\r
+  return TIMx->CCR4;\r
+}\r
+\r
+/**\r
+  * @brief  Gets the TIMx Counter value.\r
+  * @param  TIMx: where x can be 2 to 11 to select the TIM peripheral.\r
+  * @retval Counter Register value.\r
+  */\r
+uint32_t TIM_GetCounter(TIM_TypeDef* TIMx)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
+  \r
+  /* Get the Counter Register value */\r
+  return TIMx->CNT;\r
+}\r
+\r
+/**\r
+  * @brief  Gets the TIMx Prescaler value.\r
+  * @param  TIMx: where x can be 2 to 11 to select the TIM peripheral.\r
+  * @retval Prescaler Register value.\r
+  */\r
+uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
+  \r
+  /* Get the Prescaler Register value */\r
+  return TIMx->PSC;\r
+}\r
+\r
+/**\r
+  * @brief  Selects the OCReference Clear source.\r
+  * @param  TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
+  * @param  TIM_OCReferenceClear: specifies the OCReference Clear source.\r
+  *   This parameter can be one of the following values:\r
+  *     @arg TIM_OCReferenceClear_ETRF: The internal OCreference clear input is connected to ETRF.\r
+  *     @arg TIM_OCReferenceClear_OCREFCLR: The internal OCreference clear input is connected to OCREF_CLR input.  \r
+  * @retval None\r
+  */\r
+void TIM_SelectOCREFClear(TIM_TypeDef* TIMx, uint16_t TIM_OCReferenceClear)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_234_PERIPH(TIMx));\r
+  assert_param(TIM_OCREFERENCECECLEAR_SOURCE(TIM_OCReferenceClear));\r
+\r
+  /* Set the TIM_OCReferenceClear source */\r
+  TIMx->SMCR &=  (uint16_t)~((uint16_t)TIM_SMCR_OCCS);\r
+  TIMx->SMCR |=  TIM_OCReferenceClear;\r
+}\r
+\r
+/**\r
+  * @brief  Configures the TIM9, TIM10 and TIM11 Remapping input Capabilities.\r
+  * @param  TIMx: where x can be 9, 10 or 11 to select the TIM peripheral.\r
+  * @param  TIM_Remap: specifies the TIM input reampping source.\r
+  *   This parameter can be one of the following values:\r
+  *     @arg TIM9_GPIO: TIM9 Channel 1 is connected to dedicated Timer pin(default)\r
+  *     @arg TIM9_LSE: TIM9 Channel 1 is connected to LSE clock.\r
+  *     @arg TIM10_GPIO: TIM10 Channel 1 is connected to dedicated Timer pin(default) \r
+  *     @arg TIM10_LSI: TIM10 Channel 1 is connected to LSI clock.\r
+  *     @arg TIM10_LSE: TIM10 Channel 1 is connected to LSE clock.\r
+  *     @arg TIM10_RTC: TIM10 Channel 1 is connected to RTC Output event. \r
+  *     @arg TIM11_GPIO: TIM11 Channel 1 is connected to dedicated Timer pin(default) \r
+  *     @arg TIM11_MSI: TIM11 Channel 1 is connected to MSI clock.\r
+  *     @arg TIM11_HSE_RTC: TIM11 Channel 1 is connected to HSE_RTC clock.  \r
+  * @retval None\r
+  */\r
+void TIM_RemapConfig(TIM_TypeDef* TIMx, uint16_t TIM_Remap)\r
+{\r
+ /* Check the parameters */\r
+  assert_param(IS_TIM_91011_PERIPH(TIMx));\r
+  assert_param(IS_TIM_REMAP(TIM_Remap));\r
+\r
+  /* Set the Timer remapping configuration */\r
+  TIMx->OR =  TIM_Remap;\r
+}\r
+\r
+/**\r
+  * @brief  Checks whether the specified TIM flag is set or not.\r
+  * @param  TIMx: where x can be 2 to 11 to select the TIM peripheral.\r
+  * @param  TIM_FLAG: specifies the flag to check.\r
+  *   This parameter can be one of the following values:\r
+  *     @arg TIM_FLAG_Update: TIM update Flag\r
+  *     @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag\r
+  *     @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag\r
+  *     @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag\r
+  *     @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag\r
+  *     @arg TIM_FLAG_Trigger: TIM Trigger Flag\r
+  *     @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 overcapture Flag\r
+  *     @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 overcapture Flag\r
+  *     @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 overcapture Flag\r
+  *     @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 overcapture Flag\r
+  * @note\r
+  *   - TIM6 and TIM7 can have only one update flag.\r
+  *   - TIM9 can have only update flag, TIM_FLAG_CC1, TIM_FLAG_CC2 and TIM_FLAG_Trigger,\r
+  *     TIM_FLAG_CC1OF or TIM_FLAG_CC2OF flags  \r
+  *   - TIM10 and TIM11 can have only update flag, TIM_FLAG_CC1 or TIM_FLAG_CC1OF flags         \r
+  * @retval The new state of TIM_FLAG (SET or RESET).\r
+  */\r
+FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG)\r
+{ \r
+  ITStatus bitstatus = RESET; \r
+   \r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
+  assert_param(IS_TIM_GET_FLAG(TIM_FLAG));\r
+  \r
+  if ((TIMx->SR & TIM_FLAG) != (uint16_t)RESET)\r
+  {\r
+    bitstatus = SET;\r
+  }\r
+  else\r
+  {\r
+    bitstatus = RESET;\r
+  }\r
+  return bitstatus;\r
+}\r
+\r
+/**\r
+  * @brief  Clears the TIMx's pending flags.\r
+  * @param  TIMx: where x can be 2 to 11 to select the TIM peripheral.\r
+  * @param  TIM_FLAG: specifies the flag bit to clear.\r
+  *   This parameter can be any combination of the following values:\r
+  *     @arg TIM_FLAG_Update: TIM update Flag\r
+  *     @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag\r
+  *     @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag\r
+  *     @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag\r
+  *     @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag\r
+  *     @arg TIM_FLAG_Trigger: TIM Trigger Flag\r
+  *     @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 overcapture Flag\r
+  *     @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 overcapture Flag\r
+  *     @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 overcapture Flag\r
+  *     @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 overcapture Flag\r
+  * @note\r
+  *   - TIM6 and TIM7 can have only one update flag. \r
+  *   - TIM9 can have only update flag, TIM_FLAG_CC1, TIM_FLAG_CC2 and TIM_FLAG_Trigger flags\r
+  *     TIM_FLAG_CC1OF or TIM_FLAG_CC2OF flags  \r
+  *   - TIM10 and TIM11 can have only update flag, TIM_FLAG_CC1\r
+  *     or TIM_FLAG_CC1OF flags      \r
+  * @retval None\r
+  */\r
+void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG)\r
+{  \r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
+  assert_param(IS_TIM_CLEAR_FLAG(TIM_FLAG));\r
+   \r
+  /* Clear the flags */\r
+  TIMx->SR = (uint16_t)~TIM_FLAG;\r
+}\r
+\r
+/**\r
+  * @brief  Checks whether the TIM interrupt has occurred or not.\r
+  * @param  TIMx: where x can be 2 to 11 to select the TIM peripheral.\r
+  * @param  TIM_IT: specifies the TIM interrupt source to check.\r
+  *   This parameter can be one of the following values:\r
+  *     @arg TIM_IT_Update: TIM update Interrupt source\r
+  *     @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source\r
+  *     @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source\r
+  *     @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source\r
+  *     @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source\r
+  *     @arg TIM_IT_Trigger: TIM Trigger Interrupt source\r
+  * @note\r
+  *   - TIM6 and TIM7 can generate only an update interrupt.\r
+  *   - TIM9 can have only update interrupt, TIM_FLAG_CC1 or TIM_FLAG_CC2,\r
+  *     interrupt and TIM_IT_Trigger interrupt.\r
+  *   - TIM10 and TIM11 can have only update interrupt or TIM_FLAG_CC1\r
+  *     interrupt      \r
+  * @retval The new state of the TIM_IT(SET or RESET).\r
+  */\r
+ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT)\r
+{\r
+  ITStatus bitstatus = RESET;  \r
+  uint16_t itstatus = 0x0, itenable = 0x0;\r
+  \r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
+  assert_param(IS_TIM_GET_IT(TIM_IT));\r
+   \r
+  itstatus = TIMx->SR & TIM_IT;\r
+  \r
+  itenable = TIMx->DIER & TIM_IT;\r
+  if ((itstatus != (uint16_t)RESET) && (itenable != (uint16_t)RESET))\r
+  {\r
+    bitstatus = SET;\r
+  }\r
+  else\r
+  {\r
+    bitstatus = RESET;\r
+  }\r
+  return bitstatus;\r
+}\r
+\r
+/**\r
+  * @brief  Clears the TIMx's interrupt pending bits.\r
+  * @param  TIMx: where x can be 2 to 11 to select the TIM peripheral.\r
+  * @param  TIM_IT: specifies the pending bit to clear.\r
+  *   This parameter can be any combination of the following values:\r
+  *     @arg TIM_IT_Update: TIM update Interrupt source\r
+  *     @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source\r
+  *     @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source\r
+  *     @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source\r
+  *     @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source\r
+  *     @arg TIM_IT_Trigger: TIM Trigger Interrupt source\r
+  * @note\r
+  *   - TIM6 and TIM7 can generate only an update interrupt.\r
+  *   - TIM9 can have only update interrupt, TIM_IT_CC1 or TIM_IT_CC2,\r
+  *     and TIM_IT_Trigger interrupt.  \r
+  *   - TIM10 and TIM11 can have only update interrupt or TIM_IT_CC1\r
+  *     interrupt        \r
+  * @retval None\r
+  */\r
+void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
+  assert_param(IS_TIM_IT(TIM_IT));\r
+   \r
+  /* Clear the IT pending Bit */\r
+  TIMx->SR = (uint16_t)~TIM_IT;\r
+}\r
+\r
+/**\r
+  * @brief  Configure the TI1 as Input.\r
+  * @param  TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral.\r
+  * @param  TIM_ICPolarity : The Input Polarity.\r
+  *   This parameter can be one of the following values:\r
+  *     @arg TIM_ICPolarity_Rising\r
+  *     @arg TIM_ICPolarity_Falling\r
+  * @param  TIM_ICSelection: specifies the input to be used.\r
+  *   This parameter can be one of the following values:\r
+  *     @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1.\r
+  *     @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2.\r
+  *     @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC.\r
+  * @param  TIM_ICFilter: Specifies the Input Capture Filter.\r
+  *   This parameter must be a value between 0x00 and 0x0F.\r
+  * @retval None\r
+  */\r
+static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,\r
+                       uint16_t TIM_ICFilter)\r
+{\r
+  uint16_t tmpccmr1 = 0, tmpccer = 0;\r
+  \r
+  /* Disable the Channel 1: Reset the CC1E Bit */\r
+  TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC1E);\r
+  tmpccmr1 = TIMx->CCMR1;\r
+  tmpccer = TIMx->CCER;\r
+  /* Select the Input and set the filter */\r
+  tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC1S)) & ((uint16_t)~((uint16_t)TIM_CCMR1_IC1F)));\r
+  tmpccmr1 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4));\r
+  /* Select the Polarity and set the CC1E Bit */\r
+  tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC1P | TIM_CCER_CC1NP));\r
+  tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC1E);\r
+  /* Write to TIMx CCMR1 and CCER registers */\r
+  TIMx->CCMR1 = tmpccmr1;\r
+  TIMx->CCER = tmpccer;\r
+}\r
+\r
+/**\r
+  * @brief  Configure the TI2 as Input.\r
+  * @param  TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral.\r
+  * @param  TIM_ICPolarity : The Input Polarity.\r
+  *   This parameter can be one of the following values:\r
+  *     @arg TIM_ICPolarity_Rising\r
+  *     @arg TIM_ICPolarity_Falling\r
+  * @param  TIM_ICSelection: specifies the input to be used.\r
+  *   This parameter can be one of the following values:\r
+  *     @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2.\r
+  *     @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1.\r
+  *     @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC.\r
+  * @param  TIM_ICFilter: Specifies the Input Capture Filter.\r
+  *   This parameter must be a value between 0x00 and 0x0F.\r
+  * @retval None\r
+  */\r
+static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,\r
+                       uint16_t TIM_ICFilter)\r
+{\r
+  uint16_t tmpccmr1 = 0, tmpccer = 0, tmp = 0;\r
+  \r
+  /* Disable the Channel 2: Reset the CC2E Bit */\r
+  TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC2E);\r
+  tmpccmr1 = TIMx->CCMR1;\r
+  tmpccer = TIMx->CCER;\r
+  tmp = (uint16_t)(TIM_ICPolarity << 4);\r
+  /* Select the Input and set the filter */\r
+  tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC2S)) & ((uint16_t)~((uint16_t)TIM_CCMR1_IC2F)));\r
+  tmpccmr1 |= (uint16_t)(TIM_ICFilter << 12);\r
+  tmpccmr1 |= (uint16_t)(TIM_ICSelection << 8);\r
+  /* Select the Polarity and set the CC2E Bit */\r
+  tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC2P | TIM_CCER_CC2NP));\r
+  tmpccer |=  (uint16_t)(tmp | (uint16_t)TIM_CCER_CC2E);\r
+  /* Write to TIMx CCMR1 and CCER registers */\r
+  TIMx->CCMR1 = tmpccmr1 ;\r
+  TIMx->CCER = tmpccer;\r
+}\r
+\r
+/**\r
+  * @brief  Configure the TI3 as Input.\r
+  * @param  TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
+  * @param  TIM_ICPolarity : The Input Polarity.\r
+  *   This parameter can be one of the following values:\r
+  *     @arg TIM_ICPolarity_Rising\r
+  *     @arg TIM_ICPolarity_Falling\r
+  * @param  TIM_ICSelection: specifies the input to be used.\r
+  *   This parameter can be one of the following values:\r
+  *     @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3.\r
+  *     @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4.\r
+  *     @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC.\r
+  * @param  TIM_ICFilter: Specifies the Input Capture Filter.\r
+  *   This parameter must be a value between 0x00 and 0x0F.\r
+  * @retval None\r
+  */\r
+static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,\r
+                       uint16_t TIM_ICFilter)\r
+{\r
+  uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0;\r
+  \r
+  /* Disable the Channel 3: Reset the CC3E Bit */\r
+  TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC3E);\r
+  tmpccmr2 = TIMx->CCMR2;\r
+  tmpccer = TIMx->CCER;\r
+  tmp = (uint16_t)(TIM_ICPolarity << 8);\r
+  /* Select the Input and set the filter */\r
+  tmpccmr2 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR2_CC3S)) & ((uint16_t)~((uint16_t)TIM_CCMR2_IC3F)));\r
+  tmpccmr2 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4));\r
+  /* Select the Polarity and set the CC3E Bit */\r
+  tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC3P | TIM_CCER_CC3NP));\r
+  tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC3E);\r
+  /* Write to TIMx CCMR2 and CCER registers */\r
+  TIMx->CCMR2 = tmpccmr2;\r
+  TIMx->CCER = tmpccer;\r
+}\r
+\r
+/**\r
+  * @brief  Configure the TI4 as Input.\r
+  * @param  TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
+  * @param  TIM_ICPolarity : The Input Polarity.\r
+  *   This parameter can be one of the following values:\r
+  *     @arg TIM_ICPolarity_Rising\r
+  *     @arg TIM_ICPolarity_Falling\r
+  * @param  TIM_ICSelection: specifies the input to be used.\r
+  *   This parameter can be one of the following values:\r
+  *     @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4.\r
+  *     @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3.\r
+  *     @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC.\r
+  * @param  TIM_ICFilter: Specifies the Input Capture Filter.\r
+  *   This parameter must be a value between 0x00 and 0x0F.\r
+  * @retval None\r
+  */\r
+static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,\r
+                       uint16_t TIM_ICFilter)\r
+{\r
+  uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0;\r
+  \r
+  /* Disable the Channel 4: Reset the CC4E Bit */\r
+  TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC4E);\r
+  tmpccmr2 = TIMx->CCMR2;\r
+  tmpccer = TIMx->CCER;\r
+  tmp = (uint16_t)(TIM_ICPolarity << 12);\r
+  /* Select the Input and set the filter */\r
+  tmpccmr2 &= (uint16_t)((uint16_t)(~(uint16_t)TIM_CCMR2_CC4S) & ((uint16_t)~((uint16_t)TIM_CCMR2_IC4F)));\r
+  tmpccmr2 |= (uint16_t)(TIM_ICSelection << 8);\r
+  tmpccmr2 |= (uint16_t)(TIM_ICFilter << 12);\r
+\r
+  /* Select the Polarity and set the CC4E Bit */\r
+  tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC4P | TIM_CCER_CC4NP));\r
+  tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC4E);\r
+  /* Write to TIMx CCMR2 and CCER registers */\r
+  TIMx->CCMR2 = tmpccmr2;\r
+  TIMx->CCER = tmpccer ;\r
+}\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r

diff --git a/Demo/CORTEX_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_usart.c b/Demo/CORTEX_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_usart.c
new file mode 100644 (file)
index 0000000..90c1492
--- /dev/null
+++ b/Demo/CORTEX_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_usart.c
@@ -0,0 +1,995 @@
+/**\r
+  ******************************************************************************\r
+  * @file    stm32l1xx_usart.c\r
+  * @author  MCD Application Team\r
+  * @version V1.0.0RC1\r
+  * @date    07/02/2010\r
+  * @brief   This file provides all the USART firmware functions.\r
+  ******************************************************************************\r
+  * @copy\r
+  *\r
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+  *\r
+  * <h2><center>&copy; COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+  */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx_usart.h"\r
+#include "stm32l1xx_rcc.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+  * @{\r
+  */\r
+\r
+/** @defgroup USART \r
+  * @brief USART driver modules\r
+  * @{\r
+  */\r
+\r
+/** @defgroup USART_Private_TypesDefinitions\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup USART_Private_Defines\r
+  * @{\r
+  */\r
+\r
+/*!< USART CR1 register clear Mask ((~(uint16_t)0xE9F3)) */\r
+#define CR1_CLEAR_MASK            ((uint16_t)(USART_CR1_M | USART_CR1_PCE | \\r
+                                              USART_CR1_PS | USART_CR1_TE | \\r
+                                              USART_CR1_RE))\r
+\r
+/*!< USART CR2 register clock bits clear Mask ((~(uint16_t)0xF0FF)) */\r
+#define CR2_CLOCK_CLEAR_MASK      ((uint16_t)(USART_CR2_CLKEN | USART_CR2_CPOL | \\r
+                                              USART_CR2_CPHA | USART_CR2_LBCL))\r
+\r
+/*!< USART CR3 register clear Mask ((~(uint16_t)0xFCFF)) */\r
+#define CR3_CLEAR_MASK            ((uint16_t)(USART_CR3_RTSE | USART_CR3_CTSE))\r
+\r
+/*!< USART Interrupts mask */\r
+#define IT_MASK                   ((uint16_t)0x001F)\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup USART_Private_Macros\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup USART_Private_Variables\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup USART_Private_FunctionPrototypes\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup USART_Private_Functions\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @brief  Deinitializes the USARTx peripheral registers to their default reset values.\r
+  * @param  USARTx: Select the USART peripheral. \r
+  *   This parameter can be one of the following values: USART1, USART2 or USART3.\r
+  * @retval None\r
+  */\r
+void USART_DeInit(USART_TypeDef* USARTx)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+\r
+  if (USARTx == USART1)\r
+  {\r
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, ENABLE);\r
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, DISABLE);\r
+  }\r
+  else if (USARTx == USART2)\r
+  {\r
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, ENABLE);\r
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, DISABLE);\r
+  }\r
+  else \r
+  {\r
+    if (USARTx == USART3)\r
+    {\r
+      RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, ENABLE);\r
+      RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, DISABLE);    \r
+    }\r
+  }    \r
+}\r
+\r
+/**\r
+  * @brief  Initializes the USARTx peripheral according to the specified\r
+  *   parameters in the USART_InitStruct .\r
+  * @param  USARTx: Select the USART peripheral. \r
+  *   This parameter can be one of the following values:\r
+  *   USART1, USART2 or USART3.\r
+  * @param  USART_InitStruct: pointer to a USART_InitTypeDef structure\r
+  *   that contains the configuration information for the specified USART peripheral.\r
+  * @retval None\r
+  */\r
+void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct)\r
+{\r
+  uint32_t tmpreg = 0x00, apbclock = 0x00;\r
+  uint32_t integerdivider = 0x00;\r
+  uint32_t fractionaldivider = 0x00;\r
+  RCC_ClocksTypeDef RCC_ClocksStatus;\r
+\r
+  /* Check the parameters */\r
+  assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+  assert_param(IS_USART_BAUDRATE(USART_InitStruct->USART_BaudRate));  \r
+  assert_param(IS_USART_WORD_LENGTH(USART_InitStruct->USART_WordLength));\r
+  assert_param(IS_USART_STOPBITS(USART_InitStruct->USART_StopBits));\r
+  assert_param(IS_USART_PARITY(USART_InitStruct->USART_Parity));\r
+  assert_param(IS_USART_MODE(USART_InitStruct->USART_Mode));\r
+  assert_param(IS_USART_HARDWARE_FLOW_CONTROL(USART_InitStruct->USART_HardwareFlowControl));\r
+  \r
+/*---------------------------- USART CR2 Configuration -----------------------*/\r
+  tmpreg = USARTx->CR2;\r
+  /* Clear STOP[13:12] bits */\r
+  tmpreg &= (uint32_t)~((uint32_t)USART_CR2_STOP);\r
+\r
+  /* Configure the USART Stop Bits, Clock, CPOL, CPHA and LastBit ------------*/\r
+  /* Set STOP[13:12] bits according to USART_StopBits value */\r
+  tmpreg |= (uint32_t)USART_InitStruct->USART_StopBits;\r
+  \r
+  /* Write to USART CR2 */\r
+  USARTx->CR2 = (uint16_t)tmpreg;\r
+\r
+/*---------------------------- USART CR1 Configuration -----------------------*/\r
+  tmpreg = USARTx->CR1;\r
+  /* Clear M, PCE, PS, TE and RE bits */\r
+  tmpreg &= (uint32_t)~((uint32_t)CR1_CLEAR_MASK);\r
+\r
+  /* Configure the USART Word Length, Parity and mode ----------------------- */\r
+  /* Set the M bits according to USART_WordLength value */\r
+  /* Set PCE and PS bits according to USART_Parity value */\r
+  /* Set TE and RE bits according to USART_Mode value */\r
+  tmpreg |= (uint32_t)USART_InitStruct->USART_WordLength | USART_InitStruct->USART_Parity |\r
+            USART_InitStruct->USART_Mode;\r
+\r
+  /* Write to USART CR1 */\r
+  USARTx->CR1 = (uint16_t)tmpreg;\r
+\r
+/*---------------------------- USART CR3 Configuration -----------------------*/  \r
+  tmpreg = USARTx->CR3;\r
+  /* Clear CTSE and RTSE bits */\r
+  tmpreg &= (uint32_t)~((uint32_t)CR3_CLEAR_MASK);\r
+\r
+  /* Configure the USART HFC -------------------------------------------------*/\r
+  /* Set CTSE and RTSE bits according to USART_HardwareFlowControl value */\r
+  tmpreg |= USART_InitStruct->USART_HardwareFlowControl;\r
+\r
+  /* Write to USART CR3 */\r
+  USARTx->CR3 = (uint16_t)tmpreg;\r
+\r
+/*---------------------------- USART BRR Configuration -----------------------*/\r
+  /* Configure the USART Baud Rate -------------------------------------------*/\r
+  RCC_GetClocksFreq(&RCC_ClocksStatus);\r
+  if (USARTx == USART1) \r
+  {\r
+    apbclock = RCC_ClocksStatus.PCLK2_Frequency;\r
+  }\r
+  else\r
+  {\r
+    apbclock = RCC_ClocksStatus.PCLK1_Frequency;\r
+  }\r
+\r
+  /* Determine the integer part */\r
+  if ((USARTx->CR1 & USART_CR1_OVER8) != 0)\r
+  {\r
+    /* Integer part computing in case Oversampling mode is 8 Samples */\r
+    integerdivider = ((25 * apbclock) / (2 * (USART_InitStruct->USART_BaudRate)));    \r
+  }\r
+  else /* if ((USARTx->CR1 & CR1_OVER8_Set) == 0) */\r
+  {\r
+    /* Integer part computing in case Oversampling mode is 16 Samples */\r
+    integerdivider = ((25 * apbclock) / (4 * (USART_InitStruct->USART_BaudRate)));    \r
+  }\r
+  tmpreg = (integerdivider / 100) << 4;\r
+\r
+  /* Determine the fractional part */\r
+  fractionaldivider = integerdivider - (100 * (tmpreg >> 4));\r
+\r
+  /* Implement the fractional part in the register */\r
+  if ((USARTx->CR1 & USART_CR1_OVER8) != 0)\r
+  {\r
+    tmpreg |= ((((fractionaldivider * 8) + 50) / 100)) & ((uint8_t)0x07);\r
+  }\r
+  else /* if ((USARTx->CR1 & CR1_OVER8_Set) == 0) */\r
+  {\r
+    tmpreg |= ((((fractionaldivider * 16) + 50) / 100)) & ((uint8_t)0x0F);\r
+  }\r
+ \r
+  /* Write to USART BRR */\r
+  USARTx->BRR = (uint16_t)tmpreg;\r
+}\r
+\r
+/**\r
+  * @brief  Fills each USART_InitStruct member with its default value.\r
+  * @param  USART_InitStruct: pointer to a USART_InitTypeDef structure\r
+  *   which will be initialized.\r
+  * @retval None\r
+  */\r
+void USART_StructInit(USART_InitTypeDef* USART_InitStruct)\r
+{\r
+  /* USART_InitStruct members default value */\r
+  USART_InitStruct->USART_BaudRate = 9600;\r
+  USART_InitStruct->USART_WordLength = USART_WordLength_8b;\r
+  USART_InitStruct->USART_StopBits = USART_StopBits_1;\r
+  USART_InitStruct->USART_Parity = USART_Parity_No ;\r
+  USART_InitStruct->USART_Mode = USART_Mode_Rx | USART_Mode_Tx;\r
+  USART_InitStruct->USART_HardwareFlowControl = USART_HardwareFlowControl_None;  \r
+}\r
+\r
+/**\r
+  * @brief  Initializes the USARTx peripheral Clock according to the \r
+  *   specified parameters in the USART_ClockInitStruct .\r
+  * @param  USARTx: where x can be 1, 2, 3 to select the USART peripheral.\r
+  * @param  USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef\r
+  *   structure that contains the configuration information for the specified \r
+  *   USART peripheral.  \r
+  * @retval None\r
+  */\r
+void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct)\r
+{\r
+  uint32_t tmpreg = 0x00;\r
+  /* Check the parameters */\r
+  assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+  assert_param(IS_USART_CLOCK(USART_ClockInitStruct->USART_Clock));\r
+  assert_param(IS_USART_CPOL(USART_ClockInitStruct->USART_CPOL));\r
+  assert_param(IS_USART_CPHA(USART_ClockInitStruct->USART_CPHA));\r
+  assert_param(IS_USART_LASTBIT(USART_ClockInitStruct->USART_LastBit));\r
+  \r
+/*---------------------------- USART CR2 Configuration -----------------------*/\r
+  tmpreg = USARTx->CR2;\r
+  /* Clear CLKEN, CPOL, CPHA and LBCL bits */\r
+  tmpreg &= (uint32_t)~((uint32_t)CR2_CLOCK_CLEAR_MASK);\r
+  /* Configure the USART Clock, CPOL, CPHA and LastBit ------------*/\r
+  /* Set CLKEN bit according to USART_Clock value */\r
+  /* Set CPOL bit according to USART_CPOL value */\r
+  /* Set CPHA bit according to USART_CPHA value */\r
+  /* Set LBCL bit according to USART_LastBit value */\r
+  tmpreg |= (uint32_t)USART_ClockInitStruct->USART_Clock | USART_ClockInitStruct->USART_CPOL | \r
+                 USART_ClockInitStruct->USART_CPHA | USART_ClockInitStruct->USART_LastBit;\r
+  /* Write to USART CR2 */\r
+  USARTx->CR2 = (uint16_t)tmpreg;\r
+}\r
+\r
+/**\r
+  * @brief  Fills each USART_ClockInitStruct member with its default value.\r
+  * @param  USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef\r
+  *   structure which will be initialized.\r
+  * @retval None\r
+  */\r
+void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct)\r
+{\r
+  /* USART_ClockInitStruct members default value */\r
+  USART_ClockInitStruct->USART_Clock = USART_Clock_Disable;\r
+  USART_ClockInitStruct->USART_CPOL = USART_CPOL_Low;\r
+  USART_ClockInitStruct->USART_CPHA = USART_CPHA_1Edge;\r
+  USART_ClockInitStruct->USART_LastBit = USART_LastBit_Disable;\r
+}\r
+\r
+/**\r
+  * @brief  Enables or disables the specified USART peripheral.\r
+  * @param  USARTx: Select the USART peripheral. \r
+  *   This parameter can be one of the following values:\r
+  *   USART1, USART2 or USART3.\r
+  * @param  NewState: new state of the USARTx peripheral.\r
+  *   This parameter can be: ENABLE or DISABLE.\r
+  * @retval None\r
+  */\r
+void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+  assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+  \r
+  if (NewState != DISABLE)\r
+  {\r
+    /* Enable the selected USART by setting the UE bit in the CR1 register */\r
+    USARTx->CR1 |= USART_CR1_UE;\r
+  }\r
+  else\r
+  {\r
+    /* Disable the selected USART by clearing the UE bit in the CR1 register */\r
+    USARTx->CR1 &= (uint16_t)~((uint16_t)USART_CR1_UE);\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  Enables or disables the specified USART interrupts.\r
+  * @param  USARTx: Select the USART peripheral. \r
+  *   This parameter can be one of the following values:\r
+  *   USART1, USART2 or USART3.\r
+  * @param  USART_IT: specifies the USART interrupt sources to be enabled or disabled.\r
+  *   This parameter can be one of the following values:\r
+  *     @arg USART_IT_CTS:  CTS change interrupt (not available for UART4 and UART5)\r
+  *     @arg USART_IT_LBD:  LIN Break detection interrupt\r
+  *     @arg USART_IT_TXE:  Tansmit Data Register empty interrupt\r
+  *     @arg USART_IT_TC:   Transmission complete interrupt\r
+  *     @arg USART_IT_RXNE: Receive Data register not empty interrupt\r
+  *     @arg USART_IT_IDLE: Idle line detection interrupt\r
+  *     @arg USART_IT_PE:   Parity Error interrupt\r
+  *     @arg USART_IT_ERR:  Error interrupt(Frame error, noise error, overrun error)\r
+  * @param  NewState: new state of the specified USARTx interrupts.\r
+  *   This parameter can be: ENABLE or DISABLE.\r
+  * @retval None\r
+  */\r
+void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState)\r
+{\r
+  uint32_t usartreg = 0x00, itpos = 0x00, itmask = 0x00;\r
+  uint32_t usartxbase = 0x00;\r
+  /* Check the parameters */\r
+  assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+  assert_param(IS_USART_CONFIG_IT(USART_IT));\r
+  assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+  \r
+  usartxbase = (uint32_t)USARTx;\r
+\r
+  /* Get the USART register index */\r
+  usartreg = (((uint8_t)USART_IT) >> 0x05);\r
+\r
+  /* Get the interrupt position */\r
+  itpos = USART_IT & IT_MASK;\r
+  itmask = (((uint32_t)0x01) << itpos);\r
+    \r
+  if (usartreg == 0x01) /* The IT is in CR1 register */\r
+  {\r
+    usartxbase += 0x0C;\r
+  }\r
+  else if (usartreg == 0x02) /* The IT is in CR2 register */\r
+  {\r
+    usartxbase += 0x10;\r
+  }\r
+  else /* The IT is in CR3 register */\r
+  {\r
+    usartxbase += 0x14; \r
+  }\r
+  if (NewState != DISABLE)\r
+  {\r
+    *(__IO uint32_t*)usartxbase  |= itmask;\r
+  }\r
+  else\r
+  {\r
+    *(__IO uint32_t*)usartxbase &= ~itmask;\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  Enables or disables the USART\92s DMA interface.\r
+  * @param  USARTx: Select the USART peripheral. \r
+  *   This parameter can be one of the following values:\r
+  *   USART1, USART2 or USART3.\r
+  * @param  USART_DMAReq: specifies the DMA request.\r
+  *   This parameter can be any combination of the following values:\r
+  *     @arg USART_DMAReq_Tx: USART DMA transmit request\r
+  *     @arg USART_DMAReq_Rx: USART DMA receive request\r
+  * @param  NewState: new state of the DMA Request sources.\r
+  *   This parameter can be: ENABLE or DISABLE.\r
+  * @note The DMA mode is not available for UART5.  \r
+  * @retval None\r
+  */\r
+void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+  assert_param(IS_USART_DMAREQ(USART_DMAReq));  \r
+  assert_param(IS_FUNCTIONAL_STATE(NewState)); \r
+\r
+  if (NewState != DISABLE)\r
+  {\r
+    /* Enable the DMA transfer for selected requests by setting the DMAT and/or\r
+       DMAR bits in the USART CR3 register */\r
+    USARTx->CR3 |= USART_DMAReq;\r
+  }\r
+  else\r
+  {\r
+    /* Disable the DMA transfer for selected requests by clearing the DMAT and/or\r
+       DMAR bits in the USART CR3 register */\r
+    USARTx->CR3 &= (uint16_t)~USART_DMAReq;\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  Sets the address of the USART node.\r
+  * @param  USARTx: Select the USART peripheral. \r
+  *   This parameter can be one of the following values:\r
+  *   USART1, USART2 or USART3.\r
+  * @param  USART_Address: Indicates the address of the USART node.\r
+  * @retval None\r
+  */\r
+void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+  assert_param(IS_USART_ADDRESS(USART_Address)); \r
+    \r
+  /* Clear the USART address */\r
+  USARTx->CR2 &= (uint16_t)~((uint16_t)USART_CR2_ADD);\r
+  /* Set the USART address node */\r
+  USARTx->CR2 |= USART_Address;\r
+}\r
+\r
+/**\r
+  * @brief  Selects the USART WakeUp method.\r
+  * @param  USARTx: Select the USART peripheral. \r
+  *   This parameter can be one of the following values:\r
+  *   USART1, USART2 or USART3.\r
+  * @param  USART_WakeUp: specifies the USART wakeup method.\r
+  *   This parameter can be one of the following values:\r
+  *     @arg USART_WakeUp_IdleLine: WakeUp by an idle line detection\r
+  *     @arg USART_WakeUp_AddressMark: WakeUp by an address mark\r
+  * @retval None\r
+  */\r
+void USART_WakeUpConfig(USART_TypeDef* USARTx, uint16_t USART_WakeUp)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+  assert_param(IS_USART_WAKEUP(USART_WakeUp));\r
+  \r
+  USARTx->CR1 &= (uint16_t)~((uint16_t)USART_CR1_WAKE);\r
+  USARTx->CR1 |= USART_WakeUp;\r
+}\r
+\r
+/**\r
+  * @brief  Determines if the USART is in mute mode or not.\r
+  * @param  USARTx: Select the USART peripheral. \r
+  *   This parameter can be one of the following values:\r
+  *   USART1, USART2 or USART3.\r
+  * @param  NewState: new state of the USART mute mode.\r
+  *   This parameter can be: ENABLE or DISABLE.\r
+  * @retval None\r
+  */\r
+void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+  assert_param(IS_FUNCTIONAL_STATE(NewState)); \r
+  \r
+  if (NewState != DISABLE)\r
+  {\r
+    /* Enable the USART mute mode  by setting the RWU bit in the CR1 register */\r
+    USARTx->CR1 |= USART_CR1_RWU;\r
+  }\r
+  else\r
+  {\r
+    /* Disable the USART mute mode by clearing the RWU bit in the CR1 register */\r
+    USARTx->CR1 &= (uint16_t)~((uint16_t)USART_CR1_RWU);\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  Sets the USART LIN Break detection length.\r
+  * @param  USARTx: Select the USART peripheral. \r
+  *   This parameter can be one of the following values:\r
+  *   USART1, USART2 or USART3.\r
+  * @param  USART_LINBreakDetectLength: specifies the LIN break detection length.\r
+  *   This parameter can be one of the following values:\r
+  *     @arg USART_LINBreakDetectLength_10b: 10-bit break detection\r
+  *     @arg USART_LINBreakDetectLength_11b: 11-bit break detection\r
+  * @retval None\r
+  */\r
+void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint16_t USART_LINBreakDetectLength)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+  assert_param(IS_USART_LIN_BREAK_DETECT_LENGTH(USART_LINBreakDetectLength));\r
+  \r
+  USARTx->CR2 &= (uint16_t)~((uint16_t)USART_CR2_LBDL);\r
+  USARTx->CR2 |= USART_LINBreakDetectLength;  \r
+}\r
+\r
+/**\r
+  * @brief  Enables or disables the USART\92s LIN mode.\r
+  * @param  USARTx: Select the USART peripheral. \r
+  *   This parameter can be one of the following values:\r
+  *   USART1, USART2 or USART3.\r
+  * @param  NewState: new state of the USART LIN mode.\r
+  *   This parameter can be: ENABLE or DISABLE.\r
+  * @retval None\r
+  */\r
+void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+  assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+  \r
+  if (NewState != DISABLE)\r
+  {\r
+    /* Enable the LIN mode by setting the LINEN bit in the CR2 register */\r
+    USARTx->CR2 |= USART_CR2_LINEN;\r
+  }\r
+  else\r
+  {\r
+    /* Disable the LIN mode by clearing the LINEN bit in the CR2 register */\r
+    USARTx->CR2 &= (uint16_t)~((uint16_t)USART_CR2_LINEN);\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  Transmits single data through the USARTx peripheral.\r
+  * @param  USARTx: Select the USART peripheral. \r
+  *   This parameter can be one of the following values:\r
+  *   USART1, USART2 or USART3.\r
+  * @param  Data: the data to transmit.\r
+  * @retval None\r
+  */\r
+void USART_SendData(USART_TypeDef* USARTx, uint16_t Data)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+  assert_param(IS_USART_DATA(Data)); \r
+    \r
+  /* Transmit Data */\r
+  USARTx->DR = (Data & (uint16_t)0x01FF);\r
+}\r
+\r
+/**\r
+  * @brief  Returns the most recent received data by the USARTx peripheral.\r
+  * @param  USARTx: Select the USART peripheral. \r
+  *   This parameter can be one of the following values:\r
+  *   USART1, USART2 or USART3.\r
+  * @retval The received data.\r
+  */\r
+uint16_t USART_ReceiveData(USART_TypeDef* USARTx)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+  \r
+  /* Receive Data */\r
+  return (uint16_t)(USARTx->DR & (uint16_t)0x01FF);\r
+}\r
+\r
+/**\r
+  * @brief  Transmits break characters.\r
+  * @param  USARTx: Select the USART peripheral. \r
+  *   This parameter can be one of the following values:\r
+  *   USART1, USART2 or USART3.\r
+  * @retval None\r
+  */\r
+void USART_SendBreak(USART_TypeDef* USARTx)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+  \r
+  /* Send break characters */\r
+  USARTx->CR1 |= USART_CR1_SBK;\r
+}\r
+\r
+/**\r
+  * @brief  Sets the specified USART guard time.\r
+  * @param  USARTx: Select the USART peripheral. \r
+  *   This parameter can be one of the following values:\r
+  *   USART1, USART2 or USART3.\r
+  * @param  USART_GuardTime: specifies the guard time.\r
+  * @note The guard time bits are not available for UART4 and UART5.   \r
+  * @retval None\r
+  */\r
+void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime)\r
+{    \r
+  /* Check the parameters */\r
+  assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+  \r
+  /* Clear the USART Guard time */\r
+  USARTx->GTPR &= USART_GTPR_PSC;\r
+  /* Set the USART guard time */\r
+  USARTx->GTPR |= (uint16_t)((uint16_t)USART_GuardTime << 0x08);\r
+}\r
+\r
+/**\r
+  * @brief  Sets the system clock prescaler.\r
+  * @param  USARTx: Select the USART peripheral. \r
+  *   This parameter can be one of the following values:\r
+  *   USART1, USART2 or USART3.\r
+  * @param  USART_Prescaler: specifies the prescaler clock.  \r
+  * @note   The function is used for IrDA mode with UART4 and UART5.\r
+  * @retval None\r
+  */\r
+void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler)\r
+{ \r
+  /* Check the parameters */\r
+  assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+  \r
+  /* Clear the USART prescaler */\r
+  USARTx->GTPR &= USART_GTPR_GT;\r
+  /* Set the USART prescaler */\r
+  USARTx->GTPR |= USART_Prescaler;\r
+}\r
+\r
+/**\r
+  * @brief  Enables or disables the USART\92s Smart Card mode.\r
+  * @param  USARTx: Select the USART peripheral. \r
+  *   This parameter can be one of the following values:\r
+  *   USART1, USART2 or USART3.\r
+  * @param  NewState: new state of the Smart Card mode.\r
+  *   This parameter can be: ENABLE or DISABLE.     \r
+  * @note The Smart Card mode is not available for UART4 and UART5. \r
+  * @retval None\r
+  */\r
+void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+  assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+  if (NewState != DISABLE)\r
+  {\r
+    /* Enable the SC mode by setting the SCEN bit in the CR3 register */\r
+    USARTx->CR3 |= USART_CR3_SCEN;\r
+  }\r
+  else\r
+  {\r
+    /* Disable the SC mode by clearing the SCEN bit in the CR3 register */\r
+    USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_SCEN);\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  Enables or disables NACK transmission.\r
+  * @param  USARTx: Select the USART peripheral. \r
+  *   This parameter can be one of the following values:\r
+  *   USART1, USART2 or USART3.\r
+  * @param  NewState: new state of the NACK transmission.\r
+  *   This parameter can be: ENABLE or DISABLE.  \r
+  * @note The Smart Card mode is not available for UART4 and UART5.\r
+  * @retval None\r
+  */\r
+void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_USART_ALL_PERIPH(USARTx)); \r
+  assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+  if (NewState != DISABLE)\r
+  {\r
+    /* Enable the NACK transmission by setting the NACK bit in the CR3 register */\r
+    USARTx->CR3 |= USART_CR3_NACK;\r
+  }\r
+  else\r
+  {\r
+    /* Disable the NACK transmission by clearing the NACK bit in the CR3 register */\r
+    USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_NACK);\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  Enables or disables the USART\92s Half Duplex communication.\r
+  * @param  USARTx: Select the USART peripheral. \r
+  *   This parameter can be one of the following values:\r
+  *   USART1, USART2 or USART3.\r
+  * @param  NewState: new state of the USART Communication.\r
+  *   This parameter can be: ENABLE or DISABLE.\r
+  * @retval None\r
+  */\r
+void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+  assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+  \r
+  if (NewState != DISABLE)\r
+  {\r
+    /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */\r
+    USARTx->CR3 |= USART_CR3_HDSEL;\r
+  }\r
+  else\r
+  {\r
+    /* Disable the Half-Duplex mode by clearing the HDSEL bit in the CR3 register */\r
+    USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_HDSEL);\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  Enables or disables the USART's 8x oversampling mode.\r
+  * @param USARTx: Select the USART or the UART peripheral. \r
+  *   This parameter can be one of the following values:\r
+  *     USART1, USART2, USART3.\r
+  * @param NewState: new state of the USART 8x oversampling mode.\r
+  *   This parameter can be: ENABLE or DISABLE.\r
+  *\r
+  * @note\r
+  *   This function has to be called before calling USART_Init()\r
+  *   function in order to have correct baudrate Divider value.\r
+  * @retval : None\r
+  */\r
+void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+  assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+  \r
+  if (NewState != DISABLE)\r
+  {\r
+    /* Enable the 8x Oversampling mode by setting the OVER8 bit in the CR1 register */\r
+    USARTx->CR1 |= USART_CR1_OVER8;\r
+  }\r
+  else\r
+  {\r
+    /* Disable the 8x Oversampling mode by clearing the OVER8 bit in the CR1 register */\r
+    USARTx->CR1 &= (uint16_t)~((uint16_t)USART_CR1_OVER8);\r
+  }\r
+}  \r
+\r
+/**\r
+  * @brief  Enables or disables the USART's one bit sampling methode.\r
+  * @param USARTx: Select the USART or the UART peripheral. \r
+  *   This parameter can be one of the following values:\r
+  *   USART1, USART2, USART3.\r
+  * @param NewState: new state of the USART one bit sampling methode.\r
+  *   This parameter can be: ENABLE or DISABLE.\r
+  * @retval : None\r
+  */\r
+void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+  assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+  \r
+  if (NewState != DISABLE)\r
+  {\r
+    /* Enable the one bit method by setting the ONEBITE bit in the CR3 register */\r
+    USARTx->CR3 |= USART_CR3_ONEBIT;\r
+  }\r
+  else\r
+  {\r
+    /* Disable tthe one bit method by clearing the ONEBITE bit in the CR3 register */\r
+    USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_ONEBIT);\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  Configures the USART\92s IrDA interface.\r
+  * @param  USARTx: Select the USART peripheral. \r
+  *   This parameter can be one of the following values:\r
+  *   USART1, USART2 or USART3.\r
+  * @param  USART_IrDAMode: specifies the IrDA mode.\r
+  *   This parameter can be one of the following values:\r
+  *     @arg USART_IrDAMode_LowPower\r
+  *     @arg USART_IrDAMode_Normal\r
+  * @retval None\r
+  */\r
+void USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+  assert_param(IS_USART_IRDA_MODE(USART_IrDAMode));\r
+    \r
+  USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_IRLP);\r
+  USARTx->CR3 |= USART_IrDAMode;\r
+}\r
+\r
+/**\r
+  * @brief  Enables or disables the USART\92s IrDA interface.\r
+  * @param  USARTx: Select the USART peripheral. \r
+  *   This parameter can be one of the following values:\r
+  *   USART1, USART2 or USART3.\r
+  * @param  NewState: new state of the IrDA mode.\r
+  *   This parameter can be: ENABLE or DISABLE.\r
+  * @retval None\r
+  */\r
+void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+  assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+    \r
+  if (NewState != DISABLE)\r
+  {\r
+    /* Enable the IrDA mode by setting the IREN bit in the CR3 register */\r
+    USARTx->CR3 |= USART_CR3_IREN;\r
+  }\r
+  else\r
+  {\r
+    /* Disable the IrDA mode by clearing the IREN bit in the CR3 register */\r
+    USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_IREN);\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  Checks whether the specified USART flag is set or not.\r
+  * @param  USARTx: Select the USART peripheral. \r
+  *   This parameter can be one of the following values:\r
+  *   USART1, USART2 or USART3.\r
+  * @param  USART_FLAG: specifies the flag to check.\r
+  *   This parameter can be one of the following values:\r
+  *     @arg USART_FLAG_CTS:  CTS Change flag\r
+  *     @arg USART_FLAG_LBD:  LIN Break detection flag\r
+  *     @arg USART_FLAG_TXE:  Transmit data register empty flag\r
+  *     @arg USART_FLAG_TC:   Transmission Complete flag\r
+  *     @arg USART_FLAG_RXNE: Receive data register not empty flag\r
+  *     @arg USART_FLAG_IDLE: Idle Line detection flag\r
+  *     @arg USART_FLAG_ORE:  OverRun Error flag\r
+  *     @arg USART_FLAG_NE:   Noise Error flag\r
+  *     @arg USART_FLAG_FE:   Framing Error flag\r
+  *     @arg USART_FLAG_PE:   Parity Error flag\r
+  * @retval The new state of USART_FLAG (SET or RESET).\r
+  */\r
+FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG)\r
+{\r
+  FlagStatus bitstatus = RESET;\r
+  /* Check the parameters */\r
+  assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+  assert_param(IS_USART_FLAG(USART_FLAG));\r
+  \r
+  if ((USARTx->SR & USART_FLAG) != (uint16_t)RESET)\r
+  {\r
+    bitstatus = SET;\r
+  }\r
+  else\r
+  {\r
+    bitstatus = RESET;\r
+  }\r
+  return bitstatus;\r
+}\r
+\r
+/**\r
+  * @brief  Clears the USARTx's pending flags.\r
+  * @param  USARTx: Select the USART peripheral. \r
+  *   This parameter can be one of the following values:\r
+  *   USART1, USART2 or USART3.\r
+  * @param  USART_FLAG: specifies the flag to clear.\r
+  *   This parameter can be any combination of the following values:\r
+  *     @arg USART_FLAG_CTS:  CTS Change flag.\r
+  *     @arg USART_FLAG_LBD:  LIN Break detection flag.\r
+  *     @arg USART_FLAG_TC:   Transmission Complete flag.\r
+  *     @arg USART_FLAG_RXNE: Receive data register not empty flag.\r
+  *   \r
+  * @note\r
+  *   - PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun \r
+  *     error) and IDLE (Idle line detected) flags are cleared by software \r
+  *     sequence: a read operation to USART_SR register (USART_GetFlagStatus()) \r
+  *     followed by a read operation to USART_DR register (USART_ReceiveData()).\r
+  *   - RXNE flag can be also cleared by a read to the USART_DR register \r
+  *     (USART_ReceiveData()).\r
+  *   - TC flag can be also cleared by software sequence: a read operation to \r
+  *     USART_SR register (USART_GetFlagStatus()) followed by a write operation\r
+  *     to USART_DR register (USART_SendData()).\r
+  *   - TXE flag is cleared only by a write to the USART_DR register \r
+  *     (USART_SendData()).\r
+  * @retval None\r
+  */\r
+void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+  assert_param(IS_USART_CLEAR_FLAG(USART_FLAG));\r
+     \r
+  USARTx->SR = (uint16_t)~USART_FLAG;\r
+}\r
+\r
+/**\r
+  * @brief  Checks whether the specified USART interrupt has occurred or not.\r
+  * @param  USARTx: Select the USART peripheral. \r
+  *   This parameter can be one of the following values:\r
+  *   USART1, USART2 or USART3.\r
+  * @param  USART_IT: specifies the USART interrupt source to check.\r
+  *   This parameter can be one of the following values:\r
+  *     @arg USART_IT_CTS:  CTS change interrupt\r
+  *     @arg USART_IT_LBD:  LIN Break detection interrupt\r
+  *     @arg USART_IT_TXE:  Tansmit Data Register empty interrupt\r
+  *     @arg USART_IT_TC:   Transmission complete interrupt\r
+  *     @arg USART_IT_RXNE: Receive Data register not empty interrupt\r
+  *     @arg USART_IT_IDLE: Idle line detection interrupt\r
+  *     @arg USART_IT_ORE:  OverRun Error interrupt\r
+  *     @arg USART_IT_NE:   Noise Error interrupt\r
+  *     @arg USART_IT_FE:   Framing Error interrupt\r
+  *     @arg USART_IT_PE:   Parity Error interrupt\r
+  * @retval The new state of USART_IT (SET or RESET).\r
+  */\r
+ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT)\r
+{\r
+  uint32_t bitpos = 0x00, itmask = 0x00, usartreg = 0x00;\r
+  ITStatus bitstatus = RESET;\r
+  /* Check the parameters */\r
+  assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+  assert_param(IS_USART_GET_IT(USART_IT)); \r
+  \r
+  /* Get the USART register index */\r
+  usartreg = (((uint8_t)USART_IT) >> 0x05);\r
+  /* Get the interrupt position */\r
+  itmask = USART_IT & IT_MASK;\r
+  itmask = (uint32_t)0x01 << itmask;\r
+  \r
+  if (usartreg == 0x01) /* The IT  is in CR1 register */\r
+  {\r
+    itmask &= USARTx->CR1;\r
+  }\r
+  else if (usartreg == 0x02) /* The IT  is in CR2 register */\r
+  {\r
+    itmask &= USARTx->CR2;\r
+  }\r
+  else /* The IT  is in CR3 register */\r
+  {\r
+    itmask &= USARTx->CR3;\r
+  }\r
+  \r
+  bitpos = USART_IT >> 0x08;\r
+  bitpos = (uint32_t)0x01 << bitpos;\r
+  bitpos &= USARTx->SR;\r
+  if ((itmask != (uint16_t)RESET)&&(bitpos != (uint16_t)RESET))\r
+  {\r
+    bitstatus = SET;\r
+  }\r
+  else\r
+  {\r
+    bitstatus = RESET;\r
+  }\r
+  \r
+  return bitstatus;  \r
+}\r
+\r
+/**\r
+  * @brief  Clears the USARTx\92s interrupt pending bits.\r
+  * @param  USARTx: Select the USART peripheral. \r
+  *   This parameter can be one of the following values:\r
+  *   USART1, USART2 or USART3.\r
+  * @param  USART_IT: specifies the interrupt pending bit to clear.\r
+  *   This parameter can be one of the following values:\r
+  *     @arg USART_IT_CTS:  CTS change interrupt\r
+  *     @arg USART_IT_LBD:  LIN Break detection interrupt\r
+  *     @arg USART_IT_TC:   Transmission complete interrupt. \r
+  *     @arg USART_IT_RXNE: Receive Data register not empty interrupt.\r
+  *   \r
+  * @note\r
+  *   - PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun \r
+  *     error) and IDLE (Idle line detected) pending bits are cleared by \r
+  *     software sequence: a read operation to USART_SR register \r
+  *     (USART_GetITStatus()) followed by a read operation to USART_DR register \r
+  *     (USART_ReceiveData()).\r
+  *   - RXNE pending bit can be also cleared by a read to the USART_DR register \r
+  *     (USART_ReceiveData()).\r
+  *   - TC pending bit can be also cleared by software sequence: a read \r
+  *     operation to USART_SR register (USART_GetITStatus()) followed by a write \r
+  *     operation to USART_DR register (USART_SendData()).\r
+  *   - TXE pending bit is cleared only by a write to the USART_DR register \r
+  *     (USART_SendData()).\r
+  * @retval None\r
+  */\r
+void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT)\r
+{\r
+  uint16_t bitpos = 0x00, itmask = 0x00;\r
+  /* Check the parameters */\r
+  assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+  assert_param(IS_USART_CLEAR_IT(USART_IT)); \r
+  \r
+  bitpos = USART_IT >> 0x08;\r
+  itmask = ((uint16_t)0x01 << (uint16_t)bitpos);\r
+  USARTx->SR = (uint16_t)~itmask;\r
+}\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r

diff --git a/Demo/CORTEX_STM32L152_IAR/system_and_ST_code/startup_stm32l1xx_md.s b/Demo/CORTEX_STM32L152_IAR/system_and_ST_code/startup_stm32l1xx_md.s
new file mode 100644 (file)
index 0000000..8ede05b
--- /dev/null
+++ b/Demo/CORTEX_STM32L152_IAR/system_and_ST_code/startup_stm32l1xx_md.s
@@ -0,0 +1,459 @@
+;/******************** (C) COPYRIGHT 2010 STMicroelectronics ********************\r
+;* File Name          : startup_stm32l15x_lp.s\r
+;* Author             : MCD Application Team\r
+;* Version            : V1.0.0RC1\r
+;* Date               : 07/02/2010\r
+;* Description        : STM32L15x Low Power Devices vector table for EWARM5.x toolchain.\r
+;*                      This module performs:\r
+;*                      - Set the initial SP\r
+;*                      - Set the initial PC == __iar_program_start,\r
+;*                      - Set the vector table entries with the exceptions ISR\r
+;*                        address.\r
+;*                      After Reset the Cortex-M3 processor is in Thread mode,\r
+;*                      priority is Privileged, and the Stack is set to Main.\r
+;********************************************************************************\r
+;* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+;* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
+;* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,\r
+;* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE\r
+;* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING\r
+;* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+;*******************************************************************************/\r
+;\r
+;\r
+; The modules in this file are included in the libraries, and may be replaced\r
+; by any user-defined modules that define the PUBLIC symbol _program_start or\r
+; a user defined start symbol.\r
+; To override the cstartup defined in the library, simply add your modified\r
+; version to the workbench project.\r
+;\r
+; The vector table is normally located at address 0.\r
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.\r
+; The name "__vector_table" has special meaning for C-SPY:\r
+; it is where the SP start value is found, and the NVIC vector\r
+; table register (VTOR) is initialized to this address if != 0.\r
+;\r
+; Cortex-M version\r
+;\r
+\r
+        MODULE  ?cstartup\r
+\r
+        ;; Forward declaration of sections.\r
+        SECTION CSTACK:DATA:NOROOT(3)\r
+\r
+        SECTION .intvec:CODE:NOROOT(2)\r
+\r
+        EXTERN  __iar_program_start\r
+        EXTERN  SystemInit\r
+        EXTERN vPortSVCHandler\r
+        EXTERN xPortPendSVHandler\r
+        EXTERN xPortSysTickHandler             \r
+               \r
+        PUBLIC  __vector_table\r
+\r
+        DATA\r
+__vector_table\r
+        DCD     sfe(CSTACK)\r
+        DCD     Reset_Handler             ; Reset Handler\r
+\r
+        DCD     NMI_Handler               ; NMI Handler\r
+        DCD     HardFault_Handler         ; Hard Fault Handler\r
+        DCD     MemManage_Handler         ; MPU Fault Handler\r
+        DCD     BusFault_Handler          ; Bus Fault Handler\r
+        DCD     UsageFault_Handler        ; Usage Fault Handler\r
+        DCD     0                         ; Reserved\r
+        DCD     0                         ; Reserved\r
+        DCD     0                         ; Reserved\r
+        DCD     0                         ; Reserved\r
+        DCD     vPortSVCHandler           ; SVCall Handler\r
+        DCD     DebugMon_Handler          ; Debug Monitor Handler\r
+        DCD     0                         ; Reserved\r
+        DCD     xPortPendSVHandler        ; PendSV Handler\r
+        DCD     xPortSysTickHandler       ; SysTick Handler\r
+\r
+         ; External Interrupts\r
+        DCD     WWDG_IRQHandler           ; Window Watchdog\r
+        DCD     PVD_IRQHandler            ; PVD through EXTI Line detect\r
+        DCD     TAMPER_STAMP_IRQHandler   ; Tamper and Time Stamp\r
+        DCD     RTC_WKUP_IRQHandler       ; RTC Wakeup\r
+        DCD     FLASH_IRQHandler          ; FLASH\r
+        DCD     RCC_IRQHandler            ; RCC\r
+        DCD     EXTI0_IRQHandler          ; EXTI Line 0\r
+        DCD     EXTI1_IRQHandler          ; EXTI Line 1\r
+        DCD     EXTI2_IRQHandler          ; EXTI Line 2\r
+        DCD     EXTI3_IRQHandler          ; EXTI Line 3\r
+        DCD     EXTI4_IRQHandler          ; EXTI Line 4\r
+        DCD     DMA1_Channel1_IRQHandler  ; DMA1 Channel 1\r
+        DCD     DMA1_Channel2_IRQHandler  ; DMA1 Channel 2\r
+        DCD     DMA1_Channel3_IRQHandler  ; DMA1 Channel 3\r
+        DCD     DMA1_Channel4_IRQHandler  ; DMA1 Channel 4\r
+        DCD     DMA1_Channel5_IRQHandler  ; DMA1 Channel 5\r
+        DCD     DMA1_Channel6_IRQHandler  ; DMA1 Channel 6\r
+        DCD     DMA1_Channel7_IRQHandler  ; DMA1 Channel 7\r
+        DCD     ADC1_IRQHandler           ; ADC1\r
+        DCD     USB_HP_IRQHandler         ; USB High Priority\r
+        DCD     USB_LP_IRQHandler         ; USB Low  Priority\r
+        DCD     DAC_IRQHandler            ; DAC\r
+        DCD     COMP_IRQHandler           ; COMP through EXTI Line\r
+        DCD     EXTI9_5_IRQHandler        ; EXTI Line 9..5\r
+        DCD     LCD_IRQHandler            ; LCD\r
+        DCD     TIM9_IRQHandler           ; TIM9\r
+        DCD     TIM10_IRQHandler          ; TIM10\r
+        DCD     TIM11_IRQHandler          ; TIM11\r
+        DCD     TIM2_IRQHandler           ; TIM2\r
+        DCD     TIM3_IRQHandler           ; TIM3\r
+        DCD     TIM4_IRQHandler           ; TIM4\r
+        DCD     I2C1_EV_IRQHandler        ; I2C1 Event\r
+        DCD     I2C1_ER_IRQHandler        ; I2C1 Error\r
+        DCD     I2C2_EV_IRQHandler        ; I2C2 Event\r
+        DCD     I2C2_ER_IRQHandler        ; I2C2 Error\r
+        DCD     SPI1_IRQHandler           ; SPI1\r
+        DCD     SPI2_IRQHandler           ; SPI2\r
+        DCD     USART1_IRQHandler         ; USART1\r
+        DCD     USART2_IRQHandler         ; USART2\r
+        DCD     USART3_IRQHandler         ; USART3\r
+        DCD     EXTI15_10_IRQHandler      ; EXTI Line 15..10\r
+        DCD     RTC_Alarm_IRQHandler      ; RTC Alarm through EXTI Line\r
+        DCD     USB_FS_WKUP_IRQHandler    ; USB FS Wakeup from suspend\r
+        DCD     TIM6_IRQHandler           ; TIM6\r
+        DCD     TIM7_IRQHandler           ; TIM7\r
+\r
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\r
+;;\r
+;; Default interrupt handlers.\r
+;;\r
+        THUMB\r
+\r
+        PUBWEAK Reset_Handler\r
+        SECTION .text:CODE:REORDER(2)\r
+Reset_Handler\r
+        LDR     R0, =SystemInit\r
+        BLX     R0\r
+        LDR     R0, =__iar_program_start\r
+        BX      R0\r
+\r
+        PUBWEAK NMI_Handler\r
+        SECTION .text:CODE:REORDER(1)\r
+NMI_Handler\r
+        B NMI_Handler\r
+\r
+\r
+        PUBWEAK HardFault_Handler\r
+        SECTION .text:CODE:REORDER(1)\r
+HardFault_Handler\r
+        B HardFault_Handler\r
+\r
+\r
+        PUBWEAK MemManage_Handler\r
+        SECTION .text:CODE:REORDER(1)\r
+MemManage_Handler\r
+        B MemManage_Handler\r
+\r
+\r
+        PUBWEAK BusFault_Handler\r
+        SECTION .text:CODE:REORDER(1)\r
+BusFault_Handler\r
+        B BusFault_Handler\r
+\r
+\r
+        PUBWEAK UsageFault_Handler\r
+        SECTION .text:CODE:REORDER(1)\r
+UsageFault_Handler\r
+        B UsageFault_Handler\r
+\r
+\r
+        PUBWEAK SVC_Handler\r
+        SECTION .text:CODE:REORDER(1)\r
+SVC_Handler\r
+        B SVC_Handler\r
+\r
+\r
+        PUBWEAK DebugMon_Handler\r
+        SECTION .text:CODE:REORDER(1)\r
+DebugMon_Handler\r
+        B DebugMon_Handler\r
+\r
+\r
+        PUBWEAK PendSV_Handler\r
+        SECTION .text:CODE:REORDER(1)\r
+PendSV_Handler\r
+        B PendSV_Handler\r
+\r
+\r
+        PUBWEAK SysTick_Handler\r
+        SECTION .text:CODE:REORDER(1)\r
+SysTick_Handler\r
+        B SysTick_Handler\r
+\r
+\r
+        PUBWEAK WWDG_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+WWDG_IRQHandler\r
+        B WWDG_IRQHandler\r
+\r
+\r
+        PUBWEAK PVD_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+PVD_IRQHandler\r
+        B PVD_IRQHandler\r
+\r
+\r
+        PUBWEAK TAMPER_STAMP_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+TAMPER_STAMP_IRQHandler\r
+        B TAMPER_STAMP_IRQHandler\r
+\r
+\r
+        PUBWEAK RTC_WKUP_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+RTC_WKUP_IRQHandler\r
+        B RTC_WKUP_IRQHandler\r
+\r
+\r
+        PUBWEAK FLASH_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+FLASH_IRQHandler\r
+        B FLASH_IRQHandler\r
+\r
+\r
+        PUBWEAK RCC_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+RCC_IRQHandler\r
+        B RCC_IRQHandler\r
+\r
+\r
+        PUBWEAK EXTI0_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+EXTI0_IRQHandler\r
+        B EXTI0_IRQHandler\r
+\r
+\r
+        PUBWEAK EXTI1_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+EXTI1_IRQHandler\r
+        B EXTI1_IRQHandler\r
+\r
+\r
+        PUBWEAK EXTI2_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+EXTI2_IRQHandler\r
+        B EXTI2_IRQHandler\r
+\r
+\r
+        PUBWEAK EXTI3_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+EXTI3_IRQHandler\r
+        B EXTI3_IRQHandler\r
+\r
+\r
+        PUBWEAK EXTI4_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+EXTI4_IRQHandler\r
+        B EXTI4_IRQHandler\r
+\r
+\r
+        PUBWEAK DMA1_Channel1_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+DMA1_Channel1_IRQHandler\r
+        B DMA1_Channel1_IRQHandler\r
+\r
+\r
+        PUBWEAK DMA1_Channel2_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+DMA1_Channel2_IRQHandler\r
+        B DMA1_Channel2_IRQHandler\r
+\r
+\r
+        PUBWEAK DMA1_Channel3_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+DMA1_Channel3_IRQHandler\r
+        B DMA1_Channel3_IRQHandler\r
+\r
+\r
+        PUBWEAK DMA1_Channel4_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+DMA1_Channel4_IRQHandler\r
+        B DMA1_Channel4_IRQHandler\r
+\r
+\r
+        PUBWEAK DMA1_Channel5_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+DMA1_Channel5_IRQHandler\r
+        B DMA1_Channel5_IRQHandler\r
+\r
+\r
+        PUBWEAK DMA1_Channel6_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+DMA1_Channel6_IRQHandler\r
+        B DMA1_Channel6_IRQHandler\r
+\r
+\r
+        PUBWEAK DMA1_Channel7_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+DMA1_Channel7_IRQHandler\r
+        B DMA1_Channel7_IRQHandler\r
+\r
+\r
+        PUBWEAK ADC1_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+ADC1_IRQHandler\r
+        B ADC1_IRQHandler\r
+\r
+\r
+        PUBWEAK USB_HP_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+USB_HP_IRQHandler\r
+        B USB_HP_IRQHandler\r
+\r
+\r
+        PUBWEAK USB_LP_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+USB_LP_IRQHandler\r
+        B USB_LP_IRQHandler\r
+\r
+\r
+        PUBWEAK DAC_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+DAC_IRQHandler\r
+        B DAC_IRQHandler\r
+\r
+\r
+        PUBWEAK COMP_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+COMP_IRQHandler\r
+        B COMP_IRQHandler\r
+\r
+\r
+        PUBWEAK EXTI9_5_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+EXTI9_5_IRQHandler\r
+        B EXTI9_5_IRQHandler\r
+\r
+\r
+        PUBWEAK LCD_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+LCD_IRQHandler\r
+        B LCD_IRQHandler\r
+\r
+\r
+        PUBWEAK TIM9_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+TIM9_IRQHandler\r
+        B TIM9_IRQHandler\r
+\r
+\r
+        PUBWEAK TIM10_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+TIM10_IRQHandler\r
+        B TIM10_IRQHandler\r
+\r
+\r
+        PUBWEAK TIM11_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+TIM11_IRQHandler\r
+        B TIM11_IRQHandler\r
+\r
+\r
+        PUBWEAK TIM2_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+TIM2_IRQHandler\r
+        B TIM2_IRQHandler\r
+\r
+\r
+        PUBWEAK TIM3_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+TIM3_IRQHandler\r
+        B TIM3_IRQHandler\r
+\r
+\r
+        PUBWEAK TIM4_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+TIM4_IRQHandler\r
+        B TIM4_IRQHandler\r
+\r
+\r
+        PUBWEAK I2C1_EV_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+I2C1_EV_IRQHandler\r
+        B I2C1_EV_IRQHandler\r
+\r
+\r
+        PUBWEAK I2C1_ER_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+I2C1_ER_IRQHandler\r
+        B I2C1_ER_IRQHandler\r
+\r
+\r
+        PUBWEAK I2C2_EV_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+I2C2_EV_IRQHandler\r
+        B I2C2_EV_IRQHandler\r
+\r
+\r
+        PUBWEAK I2C2_ER_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+I2C2_ER_IRQHandler\r
+        B I2C2_ER_IRQHandler\r
+\r
+\r
+        PUBWEAK SPI1_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+SPI1_IRQHandler\r
+        B SPI1_IRQHandler\r
+\r
+\r
+        PUBWEAK SPI2_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+SPI2_IRQHandler\r
+        B SPI2_IRQHandler\r
+\r
+\r
+        PUBWEAK USART1_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+USART1_IRQHandler\r
+        B USART1_IRQHandler\r
+\r
+\r
+        PUBWEAK USART2_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+USART2_IRQHandler\r
+        B USART2_IRQHandler\r
+\r
+\r
+        PUBWEAK USART3_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+USART3_IRQHandler\r
+        B USART3_IRQHandler\r
+\r
+\r
+        PUBWEAK EXTI15_10_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+EXTI15_10_IRQHandler\r
+        B EXTI15_10_IRQHandler\r
+\r
+\r
+        PUBWEAK RTC_Alarm_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+RTC_Alarm_IRQHandler\r
+        B RTC_Alarm_IRQHandler\r
+\r
+\r
+        PUBWEAK USB_FS_WKUP_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+USB_FS_WKUP_IRQHandler\r
+        B USB_FS_WKUP_IRQHandler\r
+\r
+\r
+        PUBWEAK TIM6_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+TIM6_IRQHandler\r
+        B TIM6_IRQHandler\r
+\r
+\r
+        PUBWEAK TIM7_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+TIM7_IRQHandler\r
+        B TIM7_IRQHandler\r
+\r
+        END\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r

diff --git a/Demo/CORTEX_STM32L152_IAR/system_and_ST_code/stm32_eval.h b/Demo/CORTEX_STM32L152_IAR/system_and_ST_code/stm32_eval.h
new file mode 100644 (file)
index 0000000..7d1cabd
--- /dev/null
+++ b/Demo/CORTEX_STM32L152_IAR/system_and_ST_code/stm32_eval.h
@@ -0,0 +1,360 @@
+/**\r
+  ******************************************************************************\r
+  * @file    stm32_eval.h\r
+  * @author  MCD Application Team\r
+  * @version V4.4.0RC1\r
+  * @date    07/02/2010\r
+  * @brief   Header file for stm32_eval.c module.\r
+  ******************************************************************************\r
+  * @copy\r
+  *\r
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+  *\r
+  * <h2><center>&copy; COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+  */ \r
+  \r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32_EVAL_H\r
+#define __STM32_EVAL_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+\r
+/** @addtogroup Utilities\r
+  * @{\r
+  */ \r
+  \r
+/** @addtogroup STM32_EVAL\r
+  * @{\r
+  */ \r
+\r
+/** @defgroup STM32_EVAL_Abstraction_Layer\r
+  * @{\r
+  */\r
+  \r
+/** @defgroup STM32_EVAL_HARDWARE_RESOURCES\r
+  * @{\r
+  */\r
+\r
+/**\r
+@code  \r
+ The table below gives an overview of the hardware resources supported by each \r
+ STM32 EVAL board.\r
+     - LCD: TFT Color LCD (Parallel (FSMC) and Serial (SPI))\r
+     - IOE: IO Expander on I2C\r
+     - sFLASH: serial SPI FLASH (M25Pxxx)\r
+     - sEE: serial I2C EEPROM (M24C08, M24C32, M24C64)\r
+     - TSENSOR: Temperature Sensor (LM75)\r
+     - SD: SD Card memory (SPI and SDIO (SD Card MODE)) \r
+  =================================================================================================================+\r
+    STM32 EVAL     | LED | Buttons  | Com Ports |    LCD    | IOE  | sFLASH | sEE | TSENSOR | SD (SPI) | SD(SDIO)  |\r
+  =================================================================================================================+\r
+   STM3210B-EVAL   |  4  |    8     |     2     | YES (SPI) | NO   |  YES   | NO  |   YES   |    YES   |    NO     |\r
+  -----------------------------------------------------------------------------------------------------------------+\r
+   STM3210E-EVAL   |  4  |    8     |     2     | YES (FSMC)| NO   |  YES   | NO  |   YES   |    NO    |    YES    |\r
+  -----------------------------------------------------------------------------------------------------------------+\r
+   STM3210C-EVAL   |  4  |    3     |     1     | YES (SPI) | YES  |  NO    | YES |   NO    |    YES   |    NO     |\r
+  -----------------------------------------------------------------------------------------------------------------+\r
+   STM32100B-EVAL  |  4  |    8     |     2     | YES (SPI) | NO   |  YES   | NO  |   YES   |    YES   |    NO     |\r
+  -----------------------------------------------------------------------------------------------------------------+\r
+   STM32L152-EVAL  |  4  |    8     |     2     | YES (SPI) | NO   |  NO    | NO  |   YES   |    YES   |    NO     |\r
+  =================================================================================================================+\r
+@endcode\r
+*/\r
+\r
+/**\r
+  * @}\r
+  */\r
+  \r
+/** @defgroup STM32_EVAL_Exported_Types\r
+  * @{\r
+  */\r
+typedef enum \r
+{\r
+  LED1 = 0,\r
+  LED2 = 1,\r
+  LED3 = 2,\r
+  LED4 = 3\r
+} Led_TypeDef;\r
+\r
+typedef enum \r
+{  \r
+  BUTTON_WAKEUP = 0,\r
+  BUTTON_TAMPER = 1,\r
+  BUTTON_KEY = 2,\r
+  BUTTON_RIGHT = 3,\r
+  BUTTON_LEFT = 4,\r
+  BUTTON_UP = 5,\r
+  BUTTON_DOWN = 6,\r
+  BUTTON_SEL = 7\r
+} Button_TypeDef;\r
+\r
+typedef enum \r
+{  \r
+  BUTTON_MODE_GPIO = 0,\r
+  BUTTON_MODE_EXTI = 1\r
+} ButtonMode_TypeDef;\r
+\r
+typedef enum \r
+{ \r
+  JOY_NONE = 0,\r
+  JOY_SEL = 1,\r
+  JOY_DOWN = 2,\r
+  JOY_LEFT = 3,\r
+  JOY_RIGHT = 4,\r
+  JOY_UP = 5\r
+} JOYState_TypeDef\r
+;\r
+\r
+typedef enum \r
+{\r
+  COM1 = 0,\r
+  COM2 = 1\r
+} COM_TypeDef;   \r
+/**\r
+  * @}\r
+  */ \r
+  \r
+/** @defgroup STM32_EVAL_Exported_Constants\r
+  * @{\r
+  */ \r
+\r
+/** \r
+  * @brief  Uncomment the line corresponding to the STMicroelectronics evaluation\r
+  *   board used in your application.\r
+  *   \r
+  *  Tip: To avoid modifying this file each time you need to switch between these\r
+  *       boards, you can define the board in your toolchain compiler preprocessor.    \r
+  */ \r
+#if !defined (USE_STM32100B_EVAL) && !defined (USE_STM3210B_EVAL) &&  !defined (USE_STM3210E_EVAL)\\r
+   &&  !defined (USE_STM3210C_EVAL) &&  !defined (USE_STM32L152_EVAL)\r
+ //#define USE_STM32100B_EVAL\r
+ //#define USE_STM3210B_EVAL\r
+ //#define USE_STM3210E_EVAL\r
+ //#define USE_STM3210C_EVAL\r
+ //#define USE_STM32L152_EVAL\r
+#endif\r
+\r
+#ifdef USE_STM32100B_EVAL\r
+ #include "stm32f10x.h"\r
+ #include "stm32100b_eval/stm32100b_eval.h"\r
+#elif defined USE_STM3210B_EVAL\r
+ #include "stm32f10x.h"\r
+ #include "stm3210b_eval/stm3210b_eval.h" \r
+#elif defined USE_STM3210E_EVAL\r
+ #include "stm32f10x.h"\r
+ #include "stm3210e_eval/stm3210e_eval.h"\r
+#elif defined USE_STM3210C_EVAL\r
+ #include "stm32f10x.h"\r
+ #include "stm3210c_eval/stm3210c_eval.h"\r
+#elif defined USE_STM32L152_EVAL\r
+ #include "stm32l1xx.h"\r
+ #include "stm32l152_eval/stm32l152_eval.h" \r
+#else \r
+ #error "Please select first the STM32 EVAL board to be used (in stm32_eval.h)"\r
+#endif                      \r
+\r
+\r
+/** \r
+  * @brief  STM32 Button Defines Legacy  \r
+  */ \r
+#define Button_WAKEUP        BUTTON_WAKEUP\r
+#define Button_TAMPER        BUTTON_TAMPER\r
+#define Button_KEY           BUTTON_KEY\r
+#define Button_RIGHT         BUTTON_RIGHT\r
+#define Button_LEFT          BUTTON_LEFT\r
+#define Button_UP            BUTTON_UP\r
+#define Button_DOWN          BUTTON_DOWN\r
+#define Button_SEL           BUTTON_SEL\r
+#define Mode_GPIO            BUTTON_MODE_GPIO\r
+#define Mode_EXTI            BUTTON_MODE_EXTI\r
+#define Button_Mode_TypeDef  ButtonMode_TypeDef\r
+#define JOY_CENTER           JOY_SEL\r
+#define JOY_State_TypeDef    JOYState_TypeDef \r
+\r
+/** \r
+  * @brief  LCD Defines Legacy  \r
+  */ \r
+#define LCD_RSNWR_GPIO_CLK  LCD_NWR_GPIO_CLK\r
+#define LCD_SPI_GPIO_PORT   LCD_SPI_SCK_GPIO_PORT\r
+#define LCD_SPI_GPIO_CLK    LCD_SPI_SCK_GPIO_CLK\r
+#define R0                  LCD_REG_0\r
+#define R1                  LCD_REG_1\r
+#define R2                  LCD_REG_2\r
+#define R3                  LCD_REG_3\r
+#define R4                  LCD_REG_4\r
+#define R5                  LCD_REG_5\r
+#define R6                  LCD_REG_6\r
+#define R7                  LCD_REG_7\r
+#define R8                  LCD_REG_8\r
+#define R9                  LCD_REG_9\r
+#define R10                 LCD_REG_10\r
+#define R12                 LCD_REG_12\r
+#define R13                 LCD_REG_13\r
+#define R14                 LCD_REG_14\r
+#define R15                 LCD_REG_15\r
+#define R16                 LCD_REG_16\r
+#define R17                 LCD_REG_17\r
+#define R18                 LCD_REG_18\r
+#define R19                 LCD_REG_19\r
+#define R20                 LCD_REG_20\r
+#define R21                 LCD_REG_21\r
+#define R22                 LCD_REG_22\r
+#define R23                 LCD_REG_23\r
+#define R24                 LCD_REG_24\r
+#define R25                 LCD_REG_25\r
+#define R26                 LCD_REG_26\r
+#define R27                 LCD_REG_27\r
+#define R28                 LCD_REG_28\r
+#define R29                 LCD_REG_29\r
+#define R30                 LCD_REG_30\r
+#define R31                 LCD_REG_31\r
+#define R32                 LCD_REG_32\r
+#define R33                 LCD_REG_33\r
+#define R34                 LCD_REG_34\r
+#define R36                 LCD_REG_36\r
+#define R37                 LCD_REG_37\r
+#define R40                 LCD_REG_40\r
+#define R41                 LCD_REG_41\r
+#define R43                 LCD_REG_43\r
+#define R45                 LCD_REG_45\r
+#define R48                 LCD_REG_48\r
+#define R49                 LCD_REG_49\r
+#define R50                 LCD_REG_50\r
+#define R51                 LCD_REG_51\r
+#define R52                 LCD_REG_52\r
+#define R53                 LCD_REG_53\r
+#define R54                 LCD_REG_54\r
+#define R55                 LCD_REG_55\r
+#define R56                 LCD_REG_56\r
+#define R57                 LCD_REG_57\r
+#define R59                 LCD_REG_59\r
+#define R60                 LCD_REG_60\r
+#define R61                 LCD_REG_61\r
+#define R62                 LCD_REG_62\r
+#define R63                 LCD_REG_63\r
+#define R64                 LCD_REG_64\r
+#define R65                 LCD_REG_65\r
+#define R66                 LCD_REG_66\r
+#define R67                 LCD_REG_67\r
+#define R68                 LCD_REG_68\r
+#define R69                 LCD_REG_69\r
+#define R70                 LCD_REG_70\r
+#define R71                 LCD_REG_71\r
+#define R72                 LCD_REG_72\r
+#define R73                 LCD_REG_73\r
+#define R74                 LCD_REG_74\r
+#define R75                 LCD_REG_75\r
+#define R76                 LCD_REG_76\r
+#define R77                 LCD_REG_77\r
+#define R78                 LCD_REG_78\r
+#define R79                 LCD_REG_79\r
+#define R80                 LCD_REG_80\r
+#define R81                 LCD_REG_81\r
+#define R82                 LCD_REG_82\r
+#define R83                 LCD_REG_83\r
+#define R96                 LCD_REG_96\r
+#define R97                 LCD_REG_97\r
+#define R106                LCD_REG_106\r
+#define R118                LCD_REG_118\r
+#define R128                LCD_REG_128\r
+#define R129                LCD_REG_129\r
+#define R130                LCD_REG_130\r
+#define R131                LCD_REG_131\r
+#define R132                LCD_REG_132\r
+#define R133                LCD_REG_133\r
+#define R134                LCD_REG_134\r
+#define R135                LCD_REG_135\r
+#define R136                LCD_REG_136\r
+#define R137                LCD_REG_137\r
+#define R139                LCD_REG_139\r
+#define R140                LCD_REG_140\r
+#define R141                LCD_REG_141\r
+#define R143                LCD_REG_143\r
+#define R144                LCD_REG_144\r
+#define R145                LCD_REG_145\r
+#define R146                LCD_REG_146\r
+#define R147                LCD_REG_147\r
+#define R148                LCD_REG_148\r
+#define R149                LCD_REG_149\r
+#define R150                LCD_REG_150\r
+#define R151                LCD_REG_151\r
+#define R152                LCD_REG_152\r
+#define R153                LCD_REG_153\r
+#define R154                LCD_REG_154\r
+#define R157                LCD_REG_157\r
+#define R192                LCD_REG_192\r
+#define R193                LCD_REG_193\r
+#define R227                LCD_REG_227\r
+#define R229                LCD_REG_229\r
+#define R231                LCD_REG_231\r
+#define R239                LCD_REG_239\r
+#define White               LCD_COLOR_WHITE\r
+#define Black               LCD_COLOR_BLACK\r
+#define Grey                LCD_COLOR_GREY\r
+#define Blue                LCD_COLOR_BLUE\r
+#define Blue2               LCD_COLOR_BLUE2\r
+#define Red                 LCD_COLOR_RED\r
+#define Magenta             LCD_COLOR_MAGENTA\r
+#define Green               LCD_COLOR_GREEN\r
+#define Cyan                LCD_COLOR_CYAN\r
+#define Yellow              LCD_COLOR_YELLOW\r
+#define Line0               LCD_LINE_0\r
+#define Line1               LCD_LINE_1\r
+#define Line2               LCD_LINE_2\r
+#define Line3               LCD_LINE_3\r
+#define Line4               LCD_LINE_4\r
+#define Line5               LCD_LINE_5\r
+#define Line6               LCD_LINE_6\r
+#define Line7               LCD_LINE_7\r
+#define Line8               LCD_LINE_8\r
+#define Line9               LCD_LINE_9\r
+#define Horizontal          LCD_DIR_HORIZONTAL\r
+#define Vertical            LCD_DIR_VERTICAL\r
+\r
+/**\r
+  * @}\r
+  */ \r
+\r
+/** @defgroup STM32_EVAL_Exported_Macros\r
+  * @{\r
+  */ \r
+/**\r
+  * @}\r
+  */ \r
+\r
+/** @defgroup STM32_EVAL_Exported_Functions\r
+  * @{\r
+  */ \r
+/**\r
+  * @}\r
+  */ \r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+\r
+#endif /* __STM32_EVAL_H */\r
+\r
+/**\r
+  * @}\r
+  */ \r
+\r
+/**\r
+  * @}\r
+  */ \r
+\r
+/**\r
+  * @}\r
+  */   \r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r

diff --git a/Demo/CORTEX_STM32L152_IAR/system_and_ST_code/stm32l1xx_conf.h b/Demo/CORTEX_STM32L152_IAR/system_and_ST_code/stm32l1xx_conf.h
new file mode 100644 (file)
index 0000000..cd79da0
--- /dev/null
+++ b/Demo/CORTEX_STM32L152_IAR/system_and_ST_code/stm32l1xx_conf.h
@@ -0,0 +1,74 @@
+/**\r
+  ******************************************************************************\r
+  * @file    Project/STM32L1xx_StdPeriph_Template/stm32l1xx_conf.h\r
+  * @author  MCD Application Team\r
+  * @version V1.0.0RC1\r
+  * @date    07/02/2010\r
+  * @brief   Library configuration file.\r
+  ******************************************************************************\r
+  * @copy\r
+  *\r
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+  *\r
+  * <h2><center>&copy; COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+  */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32L1xx_CONF_H\r
+#define __STM32L1xx_CONF_H\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+/* Uncomment the line below to enable peripheral header file inclusion */\r
+/* #include "stm32l1xx_adc.h" */\r
+/* #include "stm32l1xx_crc.h" */\r
+/* #include "stm32l1xx_comp.h" */\r
+/* #include "stm32l1xx_dac.h" */\r
+/* #include "stm32l1xx_dbgmcu.h" */\r
+/* #include "stm32l1xx_dma.h" */\r
+#include "stm32l1xx_exti.h"\r
+/* #include "stm32l1xx_flash.h" */\r
+#include "stm32l1xx_gpio.h"\r
+#include "stm32l1xx_syscfg.h"\r
+/* #include "stm32l1xx_i2c.h" */\r
+/* #include "stm32l1xx_iwdg.h" */\r
+/* #include "stm32l1xx_lcd.h" */\r
+#include "stm32l1xx_pwr.h"\r
+#include "stm32l1xx_rcc.h"\r
+/* #include "stm32l1xx_rtc.h" */\r
+#include "stm32l1xx_spi.h"\r
+#include "stm32l1xx_tim.h"\r
+#include "stm32l1xx_usart.h"\r
+/* #include "stm32l1xx_wwdg.h" */\r
+#include "misc.h"  /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/* Exported constants --------------------------------------------------------*/\r
+/* Uncomment the line below to expanse the "assert_param" macro in the\r
+   Standard Peripheral Library drivers code */\r
+/* #define USE_FULL_ASSERT    1 */\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+#ifdef  USE_FULL_ASSERT\r
+\r
+/**\r
+  * @brief  The assert_param macro is used for function's parameters check.\r
+  * @param  expr: If expr is false, it calls assert_failed function which reports\r
+  *         the name of the source file and the source line number of the call\r
+  *         that failed. If expr is true, it returns no value.\r
+  * @retval None\r
+  */\r
+  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))\r
+/* Exported functions ------------------------------------------------------- */\r
+  void assert_failed(uint8_t* file, uint32_t line);\r
+#else\r
+  #define assert_param(expr) ((void)0)\r
+#endif /* USE_FULL_ASSERT */\r
+\r
+#endif /* __STM32L1xx_CONF_H */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r

diff --git a/Demo/CORTEX_STM32L152_IAR/system_and_ST_code/stm32l1xx_flash.icf b/Demo/CORTEX_STM32L152_IAR/system_and_ST_code/stm32l1xx_flash.icf
new file mode 100644 (file)
index 0000000..be00d54
--- /dev/null
+++ b/Demo/CORTEX_STM32L152_IAR/system_and_ST_code/stm32l1xx_flash.icf
@@ -0,0 +1,31 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/\r
+/*-Editor annotation file-*/\r
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */\r
+/*-Specials-*/\r
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;\r
+/*-Memory Regions-*/\r
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000 ;\r
+define symbol __ICFEDIT_region_ROM_end__   = 0x0801FFFF;\r
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;\r
+define symbol __ICFEDIT_region_RAM_end__   = 0x20003FFF;\r
+/*-Sizes-*/\r
+define symbol __ICFEDIT_size_cstack__ = 0x300;\r
+define symbol __ICFEDIT_size_heap__   = 0x0;\r
+/**** End of ICF editor section. ###ICF###*/\r
+\r
+\r
+define memory mem with size = 4G;\r
+define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];\r
+define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];\r
+\r
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };\r
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };\r
+\r
+initialize by copy { readwrite };\r
+do not initialize  { section .noinit };\r
+\r
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };\r
+\r
+place in ROM_region   { readonly };\r
+place in RAM_region   { readwrite,\r
+                        block CSTACK, block HEAP };
\ No newline at end of file

diff --git a/Demo/CORTEX_STM32L152_IAR/system_and_ST_code/stm32l1xx_it.c b/Demo/CORTEX_STM32L152_IAR/system_and_ST_code/stm32l1xx_it.c
new file mode 100644 (file)
index 0000000..5afcd2a
--- /dev/null
+++ b/Demo/CORTEX_STM32L152_IAR/system_and_ST_code/stm32l1xx_it.c
@@ -0,0 +1,160 @@
+/**\r
+  ******************************************************************************\r
+  * @file    Project/STM32L1xx_StdPeriph_Template/stm32l1xx_it.c\r
+  * @author  MCD Application Team\r
+  * @version V1.0.0RC1\r
+  * @date    07/02/2010\r
+  * @brief   Main Interrupt Service Routines.\r
+  *          This file provides template for all exceptions handler and\r
+  *          peripherals interrupt service routine.\r
+  ******************************************************************************\r
+  * @copy\r
+  *\r
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+  *\r
+  * <h2><center>&copy; COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+  */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx_it.h"\r
+\r
+\r
+/** @addtogroup Template_Project\r
+  * @{\r
+  */\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/******************************************************************************/\r
+/*            Cortex-M3 Processor Exceptions Handlers                         */\r
+/******************************************************************************/\r
+\r
+/**\r
+  * @brief  This function handles NMI exception.\r
+  * @param  None\r
+  * @retval None\r
+  */\r
+void NMI_Handler(void)\r
+{\r
+}\r
+\r
+/**\r
+  * @brief  This function handles Hard Fault exception.\r
+  * @param  None\r
+  * @retval None\r
+  */\r
+void HardFault_Handler(void)\r
+{\r
+  /* Go to infinite loop when Hard Fault exception occurs */\r
+  while (1)\r
+  {\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  This function handles Memory Manage exception.\r
+  * @param  None\r
+  * @retval None\r
+  */\r
+void MemManage_Handler(void)\r
+{\r
+  /* Go to infinite loop when Memory Manage exception occurs */\r
+  while (1)\r
+  {\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  This function handles Bus Fault exception.\r
+  * @param  None\r
+  * @retval None\r
+  */\r
+void BusFault_Handler(void)\r
+{\r
+  /* Go to infinite loop when Bus Fault exception occurs */\r
+  while (1)\r
+  {\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  This function handles Usage Fault exception.\r
+  * @param  None\r
+  * @retval None\r
+  */\r
+void UsageFault_Handler(void)\r
+{\r
+  /* Go to infinite loop when Usage Fault exception occurs */\r
+  while (1)\r
+  {\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  This function handles SVCall exception.\r
+  * @param  None\r
+  * @retval None\r
+  */\r
+void SVC_Handler(void)\r
+{\r
+}\r
+\r
+/**\r
+  * @brief  This function handles Debug Monitor exception.\r
+  * @param  None\r
+  * @retval None\r
+  */\r
+void DebugMon_Handler(void)\r
+{\r
+}\r
+\r
+/**\r
+  * @brief  This function handles PendSVC exception.\r
+  * @param  None\r
+  * @retval None\r
+  */\r
+void PendSV_Handler(void)\r
+{\r
+}\r
+\r
+/**\r
+  * @brief  This function handles SysTick Handler.\r
+  * @param  None\r
+  * @retval None\r
+  */\r
+void SysTick_Handler(void)\r
+{\r
+}\r
+\r
+/******************************************************************************/\r
+/*                 STM32L1xx Peripherals Interrupt Handlers                   */\r
+/*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */\r
+/*  available peripheral interrupt handler's name please refer to the startup */\r
+/*  file (startup_stm32l1xx_md.s).                                            */\r
+/******************************************************************************/\r
+\r
+/**\r
+  * @brief  This function handles PPP interrupt request.\r
+  * @param  None\r
+  * @retval None\r
+  */\r
+/*void PPP_IRQHandler(void)\r
+{\r
+}*/\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r

diff --git a/Demo/CORTEX_STM32L152_IAR/system_and_ST_code/stm32l1xx_it.h b/Demo/CORTEX_STM32L152_IAR/system_and_ST_code/stm32l1xx_it.h
new file mode 100644 (file)
index 0000000..7eabc16
--- /dev/null
+++ b/Demo/CORTEX_STM32L152_IAR/system_and_ST_code/stm32l1xx_it.h
@@ -0,0 +1,53 @@
+/**\r
+  ******************************************************************************\r
+  * @file    Project/STM32L1xx_StdPeriph_Template/stm32l1xx_it.h \r
+  * @author  MCD Application Team\r
+  * @version V1.0.0RC1\r
+  * @date    07/02/2010\r
+  * @brief   This file contains the headers of the interrupt handlers.\r
+  ******************************************************************************\r
+  * @copy\r
+  *\r
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+  *\r
+  * <h2><center>&copy; COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+  */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32L1xx_IT_H\r
+#define __STM32L1xx_IT_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx.h"\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/* Exported constants --------------------------------------------------------*/\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */\r
+\r
+void NMI_Handler(void);\r
+void HardFault_Handler(void);\r
+void MemManage_Handler(void);\r
+void BusFault_Handler(void);\r
+void UsageFault_Handler(void);\r
+void SVC_Handler(void);\r
+void DebugMon_Handler(void);\r
+void PendSV_Handler(void);\r
+void SysTick_Handler(void);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32L1xx_IT_H */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r

diff --git a/Demo/CORTEX_STM32L152_IAR/system_and_ST_code/system_stm32l1xx.c b/Demo/CORTEX_STM32L152_IAR/system_and_ST_code/system_stm32l1xx.c
new file mode 100644 (file)
index 0000000..e3881c1
--- /dev/null
+++ b/Demo/CORTEX_STM32L152_IAR/system_and_ST_code/system_stm32l1xx.c
@@ -0,0 +1,934 @@
+/**\r
+  ******************************************************************************\r
+  * @file    system_stm32l1xx.c\r
+  * @author  MCD Application Team\r
+  * @version V1.0.0RC1\r
+  * @date    07/02/2010\r
+  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.\r
+  ******************************************************************************\r
+  *\r
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+  *\r
+  * <h2><center>&copy; COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+  ******************************************************************************\r
+  */\r
+\r
+/** @addtogroup CMSIS\r
+  * @{\r
+  */\r
+\r
+/** @addtogroup stm32l1xx_system\r
+  * @{\r
+  */\r
+\r
+/** @addtogroup STM32L1xx_System_Private_Includes\r
+  * @{\r
+  */\r
+\r
+#include "stm32l1xx.h"\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @addtogroup STM32L1xx_System_Private_TypesDefinitions\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @addtogroup STM32L1xx_System_Private_Defines\r
+  * @{\r
+  */\r
+\r
+/*!< Uncomment the line corresponding to the desired System clock (SYSCLK)\r
+   frequency (after reset the MSI is used as SYSCLK source)\r
+\r
+   IMPORTANT NOTE:\r
+   ==============\r
+   1. After each device reset the MSI is used as System clock source.\r
+\r
+   2. Please make sure that the selected System clock doesn't exceed your device's\r
+      maximum frequency.\r
+\r
+   3. If none of the define below is enabled, the MSI (2MHz default) is used as\r
+      System clock source.\r
+\r
+   4. The System clock configuration functions provided within this file assume that:\r
+        - For Ultra Low Power Medium Mensity devices an external 8MHz crystal is\r
+          used to drive the System clock.\r
+     If you are using different crystal you have to adapt those functions accordingly.\r
+    */\r
+\r
+/* #define SYSCLK_FREQ_MSI */\r
+\r
+#ifndef SYSCLK_FREQ_MSI\r
+/* #define SYSCLK_FREQ_HSI    HSI_VALUE */\r
+/* #define SYSCLK_FREQ_HSE    HSE_VALUE */\r
+/* #define SYSCLK_FREQ_4MHz   4000000 */\r
+/* #define SYSCLK_FREQ_8MHz   8000000 */\r
+/* #define SYSCLK_FREQ_16MHz  16000000 */\r
+#define SYSCLK_FREQ_32MHz  32000000\r
+#else\r
+/* #define SYSCLK_FREQ_MSI_64KHz     64000 */\r
+/* #define SYSCLK_FREQ_MSI_128KHz    128000 */\r
+/* #define SYSCLK_FREQ_MSI_256KHz    256000 */\r
+/* #define SYSCLK_FREQ_MSI_512KHz    512000 */\r
+/* #define SYSCLK_FREQ_MSI_1MHz      1000000 */\r
+/* #define SYSCLK_FREQ_MSI_2MHz      2000000 */\r
+/* #define SYSCLK_FREQ_MSI_4MHz      4000000 */\r
+#endif\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @addtogroup STM32L1xx_System_Private_Macros\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @addtogroup STM32L1xx_System_Private_Variables\r
+  * @{\r
+  */\r
+\r
+/*******************************************************************************\r
+*  Clock Definitions\r
+*******************************************************************************/\r
+#ifndef SYSCLK_FREQ_MSI\r
+#ifdef SYSCLK_FREQ_HSI\r
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_HSI;        /*!< System Clock Frequency (Core Clock) */\r
+#elif defined SYSCLK_FREQ_HSE\r
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */\r
+#elif defined SYSCLK_FREQ_4MHz\r
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_4MHz;       /*!< System Clock Frequency (Core Clock) */\r
+#elif defined SYSCLK_FREQ_8MHz\r
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_8MHz;       /*!< System Clock Frequency (Core Clock) */\r
+#elif defined SYSCLK_FREQ_16MHz\r
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_16MHz;      /*!< System Clock Frequency (Core Clock) */\r
+#elif defined SYSCLK_FREQ_32MHz\r
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_32MHz;      /*!< System Clock Frequency (Core Clock) */\r
+#else /*!< MSI Selected as System Clock source */\r
+  uint32_t SystemCoreClock         = MSI_VALUE;              /*!< System Clock Frequency (Core Clock) */\r
+#endif\r
+#else\r
+#ifdef SYSCLK_FREQ_MSI_64KHz\r
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_MSI_64KHz;  /*!< System Clock Frequency (Core Clock) */\r
+#elif defined SYSCLK_FREQ_MSI_128KHz\r
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_MSI_128KHz; /*!< System Clock Frequency (Core Clock) */\r
+#elif defined SYSCLK_FREQ_MSI_256KHz\r
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_MSI_256KHz; /*!< System Clock Frequency (Core Clock) */\r
+#elif defined SYSCLK_FREQ_MSI_512KHz\r
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_MSI_512KHz; /*!< System Clock Frequency (Core Clock) */\r
+#elif defined SYSCLK_FREQ_MSI_1MHz\r
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_MSI_1MHz;   /*!< System Clock Frequency (Core Clock) */\r
+#elif defined SYSCLK_FREQ_MSI_2MHz\r
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_MSI_2MHz;   /*!< System Clock Frequency (Core Clock) */\r
+#elif defined SYSCLK_FREQ_MSI_4MHz\r
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_MSI_4MHz;   /*!< System Clock Frequency (Core Clock) */\r
+#else\r
+  uint32_t SystemCoreClock         = MSI_VALUE;              /*!< System Clock Frequency (Core Clock) */\r
+#endif\r
+#endif\r
+\r
+__I uint8_t PLLMulTable[9] = {3, 4, 6, 8, 12, 16, 24, 32, 48};\r
+__I uint8_t MSITable[7] = {0, 0, 0, 0, 1, 2, 4};\r
+__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @addtogroup STM32L1xx_System_Private_FunctionPrototypes\r
+  * @{\r
+  */\r
+\r
+static void SetSysClock(void);\r
+\r
+#ifdef SYSCLK_FREQ_HSI\r
+  static void SetSysClockToHSI(void);\r
+#elif defined SYSCLK_FREQ_HSE\r
+  static void SetSysClockToHSE(void);\r
+#elif defined SYSCLK_FREQ_4MHz\r
+  static void SetSysClockTo4(void);\r
+#elif defined SYSCLK_FREQ_8MHz\r
+  static void SetSysClockTo8(void);\r
+#elif defined SYSCLK_FREQ_16MHz\r
+  static void SetSysClockTo16(void);\r
+#elif defined SYSCLK_FREQ_32MHz\r
+  static void SetSysClockTo32(void);\r
+#else\r
+  static void SetSysClockToMSI(void);\r
+#endif\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @addtogroup STM32L1xx_System_Private_Functions\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @brief  Setup the microcontroller system\r
+  *         Initialize the Embedded Flash Interface, the PLL and update the\r
+  *         SystemCoreClock variable\r
+  * @note   This function should be used only after reset.\r
+  * @param  None\r
+  * @retval None\r
+  */\r
+void SystemInit (void)\r
+{\r
+  /*!< Set MSION bit */\r
+  RCC->CR |= (uint32_t)0x00000100;\r
+\r
+  /*!< Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], MCOSEL[2:0] and MCOPRE[2:0] bits */\r
+  RCC->CFGR &= (uint32_t)0x88FFC00C;\r
+\r
+  /*!< Reset HSION, HSEON, CSSON and PLLON bits */\r
+  RCC->CR &= (uint32_t)0xEEFEFFFE;\r
+\r
+  /*!< Reset HSEBYP bit */\r
+  RCC->CR &= (uint32_t)0xFFFBFFFF;\r
+\r
+  /*!< Reset PLLSRC, PLLMUL[3:0] and PLLDIV[1:0] bits */\r
+  RCC->CFGR &= (uint32_t)0xFF02FFFF;\r
+\r
+  /*!< Disable all interrupts */\r
+  RCC->CIR = 0x00000000;\r
+\r
+  /*!< Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */\r
+  /*!< Configure the Flash Latency cycles and enable prefetch buffer */\r
+  SetSysClock();\r
+\r
+}\r
+\r
+/**\r
+  * @brief  Update SystemCoreClock according to Clock Register Values\r
+  * @note   None\r
+  * @param  None\r
+  * @retval None\r
+  */\r
+void SystemCoreClockUpdate (void)\r
+{\r
+  uint32_t tmp = 0, pllmul = 0, plldiv = 0, pllsource = 0, msirange = 0;\r
+\r
+  /* Get SYSCLK source -------------------------------------------------------*/\r
+  tmp = RCC->CFGR & RCC_CFGR_SWS;\r
+\r
+  switch (tmp)\r
+  {\r
+    case 0x00:  /* MSI used as system clock */\r
+      msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13;\r
+      SystemCoreClock = (((1 << msirange) * 64000) - (MSITable[msirange] * 24000));\r
+      break;\r
+    case 0x04:  /* HSI used as system clock */\r
+      SystemCoreClock = HSI_VALUE;\r
+      break;\r
+    case 0x08:  /* HSE used as system clock */\r
+      SystemCoreClock = HSE_VALUE;\r
+      break;\r
+    case 0x0C:  /* PLL used as system clock */\r
+      /* Get PLL clock source and multiplication factor ----------------------*/\r
+      pllmul = RCC->CFGR & RCC_CFGR_PLLMUL;\r
+      plldiv = RCC->CFGR & RCC_CFGR_PLLDIV;\r
+      pllmul = PLLMulTable[(pllmul >> 18)];\r
+      plldiv = (plldiv >> 22) + 1;\r
+\r
+      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;\r
+\r
+      if (pllsource == 0x00)\r
+      {\r
+        /* HSI oscillator clock selected as PLL clock entry */\r
+        SystemCoreClock = (((HSI_VALUE) * pllmul) / plldiv);\r
+      }\r
+      else\r
+      {\r
+        /* HSE selected as PLL clock entry */\r
+        SystemCoreClock = (((HSE_VALUE) * pllmul) / plldiv);\r
+      }\r
+      break;\r
+    default:\r
+      SystemCoreClock = MSI_VALUE;\r
+      break;\r
+  }\r
+  /* Compute HCLK clock frequency --------------------------------------------*/\r
+  /* Get HCLK prescaler */\r
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];\r
+  /* HCLK clock frequency */\r
+  SystemCoreClock >>= tmp;\r
+}\r
+\r
+/**\r
+  * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.\r
+  * @param  None\r
+  * @retval None\r
+  */\r
+static void SetSysClock(void)\r
+{\r
+#ifdef SYSCLK_FREQ_HSI\r
+  SetSysClockToHSI();\r
+#elif defined SYSCLK_FREQ_HSE\r
+  SetSysClockToHSE();\r
+#elif defined SYSCLK_FREQ_4MHz\r
+  SetSysClockTo4();\r
+#elif defined SYSCLK_FREQ_8MHz\r
+  SetSysClockTo8();\r
+#elif defined SYSCLK_FREQ_16MHz\r
+  SetSysClockTo16();\r
+#elif defined SYSCLK_FREQ_32MHz\r
+  SetSysClockTo32();\r
+#else\r
+  SetSysClockToMSI();\r
+#endif\r
+\r
+ /* If none of the define above is enabled, the MSI (2MHz default) is used as\r
+    System clock source (default after reset) */\r
+}\r
+\r
+#ifdef SYSCLK_FREQ_HSI\r
+/**\r
+  * @brief  Selects HSI as System clock source and configure HCLK, PCLK2\r
+  *         and PCLK1 prescalers.\r
+  * @note   This function should be used only after reset.\r
+  * @param  None\r
+  * @retval None\r
+  */\r
+static void SetSysClockToHSI(void)\r
+{\r
+  __IO uint32_t StartUpCounter = 0, HSIStatus = 0;\r
+\r
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/\r
+  /* Enable HSI */\r
+  RCC->CR |= ((uint32_t)RCC_CR_HSION);\r
+\r
+  /* Wait till HSI is ready and if Time out is reached exit */\r
+  do\r
+  {\r
+    HSIStatus = RCC->CR & RCC_CR_HSIRDY;\r
+    StartUpCounter++;\r
+  } while((HSIStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));\r
+\r
+  if ((RCC->CR & RCC_CR_HSIRDY) != RESET)\r
+  {\r
+    HSIStatus = (uint32_t)0x01;\r
+  }\r
+  else\r
+  {\r
+    HSIStatus = (uint32_t)0x00;\r
+  }\r
+\r
+  if (HSIStatus == (uint32_t)0x01)\r
+  {\r
+    /* Enable 64-bit access */\r
+    FLASH->ACR |= FLASH_ACR_ACC64;\r
+\r
+    /* Enable Prefetch Buffer */\r
+    FLASH->ACR |= FLASH_ACR_PRFTEN;\r
+\r
+    /* Flash 1 wait state */\r
+    FLASH->ACR |= FLASH_ACR_LATENCY;\r
+\r
+    /* Enable the PWR APB1 Clock */\r
+    RCC->APB1ENR |= RCC_APB1ENR_PWREN;\r
+\r
+    /* Select the Voltage Range 1 (1.8V) */\r
+    PWR->CR = PWR_CR_VOS_0;\r
+\r
+    /* Wait Until the Voltage Regulator is ready */\r
+    while((PWR->CSR & PWR_CSR_VOSF) != RESET)\r
+    {\r
+    }\r
+\r
+    /* HCLK = SYSCLK */\r
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;\r
+\r
+    /* PCLK2 = HCLK */\r
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;\r
+\r
+    /* PCLK1 = HCLK */\r
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;\r
+\r
+    /* Select HSI as system clock source */\r
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));\r
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSI;\r
+\r
+    /* Wait till HSI is used as system clock source */\r
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)\r
+    {\r
+    }\r
+  }\r
+  else\r
+  {\r
+    /* If HSI fails to start-up, the application will have wrong clock\r
+       configuration. User can add here some code to deal with this error */\r
+  }\r
+}\r
+\r
+#elif defined SYSCLK_FREQ_HSE\r
+/**\r
+  * @brief  Selects HSE as System clock source and configure HCLK, PCLK2\r
+  *         and PCLK1 prescalers.\r
+  * @note   This function should be used only after reset.\r
+  * @param  None\r
+  * @retval None\r
+  */\r
+static void SetSysClockToHSE(void)\r
+{\r
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;\r
+\r
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/\r
+  /* Enable HSE */\r
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);\r
+\r
+  /* Wait till HSE is ready and if Time out is reached exit */\r
+  do\r
+  {\r
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;\r
+    StartUpCounter++;\r
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));\r
+\r
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)\r
+  {\r
+    HSEStatus = (uint32_t)0x01;\r
+  }\r
+  else\r
+  {\r
+    HSEStatus = (uint32_t)0x00;\r
+  }\r
+\r
+  if (HSEStatus == (uint32_t)0x01)\r
+  {\r
+    /* Flash 0 wait state */\r
+    FLASH->ACR &= ~FLASH_ACR_LATENCY;\r
+\r
+    /* Disable Prefetch Buffer */\r
+    FLASH->ACR &= ~FLASH_ACR_PRFTEN;\r
+\r
+    /* Disable 64-bit access */\r
+    FLASH->ACR &= ~FLASH_ACR_ACC64;\r
+\r
+    /* Enable the PWR APB1 Clock */\r
+    RCC->APB1ENR |= RCC_APB1ENR_PWREN;\r
+\r
+    /* Select the Voltage Range 2 (1.5V) */\r
+    PWR->CR = PWR_CR_VOS_1;\r
+\r
+    /* Wait Until the Voltage Regulator is ready */\r
+    while((PWR->CSR & PWR_CSR_VOSF) != RESET)\r
+    {\r
+    }\r
+\r
+    /* HCLK = SYSCLK */\r
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;\r
+\r
+    /* PCLK2 = HCLK */\r
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;\r
+\r
+    /* PCLK1 = HCLK */\r
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;\r
+\r
+    /* Select HSE as system clock source */\r
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));\r
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;\r
+\r
+    /* Wait till HSE is used as system clock source */\r
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)\r
+    {\r
+    }\r
+  }\r
+  else\r
+  {\r
+    /* If HSE fails to start-up, the application will have wrong clock\r
+       configuration. User can add here some code to deal with this error */\r
+  }\r
+}\r
+#elif defined SYSCLK_FREQ_4MHz\r
+/**\r
+  * @brief  Sets System clock frequency to 4MHz and configure HCLK, PCLK2\r
+  *         and PCLK1 prescalers.\r
+  * @note   This function should be used only after reset.\r
+  * @param  None\r
+  * @retval None\r
+  */\r
+static void SetSysClockTo4(void)\r
+{\r
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;\r
+\r
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/\r
+  /* Enable HSE */\r
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);\r
+\r
+  /* Wait till HSE is ready and if Time out is reached exit */\r
+  do\r
+  {\r
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;\r
+    StartUpCounter++;\r
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));\r
+\r
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)\r
+  {\r
+    HSEStatus = (uint32_t)0x01;\r
+  }\r
+  else\r
+  {\r
+    HSEStatus = (uint32_t)0x00;\r
+  }\r
+\r
+  if (HSEStatus == (uint32_t)0x01)\r
+  {\r
+    /* Flash 0 wait state */\r
+    FLASH->ACR &= ~FLASH_ACR_LATENCY;\r
+\r
+    /* Disable Prefetch Buffer */\r
+    FLASH->ACR &= ~FLASH_ACR_PRFTEN;\r
+\r
+    /* Disable 64-bit access */\r
+    FLASH->ACR &= ~FLASH_ACR_ACC64;\r
+\r
+    /* Enable the PWR APB1 Clock */\r
+    RCC->APB1ENR |= RCC_APB1ENR_PWREN;\r
+\r
+    /* Select the Voltage Range 2 (1.5V) */\r
+    PWR->CR = PWR_CR_VOS_1;\r
+\r
+    /* Wait Until the Voltage Regulator is ready */\r
+    while((PWR->CSR & PWR_CSR_VOSF) != RESET)\r
+    {\r
+    }\r
+\r
+    /* HCLK = SYSCLK */\r
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV2;\r
+\r
+    /* PCLK2 = HCLK */\r
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;\r
+\r
+    /* PCLK1 = HCLK */\r
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;\r
+\r
+    /* Select HSE as system clock source */\r
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));\r
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;\r
+\r
+    /* Wait till HSE is used as system clock source */\r
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)\r
+    {\r
+    }\r
+  }\r
+  else\r
+  {\r
+    /* If HSE fails to start-up, the application will have wrong clock\r
+       configuration. User can add here some code to deal with this error */\r
+  }\r
+}\r
+\r
+#elif defined SYSCLK_FREQ_8MHz\r
+/**\r
+  * @brief  Sets System clock frequency to 8MHz and configure HCLK, PCLK2\r
+  *         and PCLK1 prescalers.\r
+  * @note   This function should be used only after reset.\r
+  * @param  None\r
+  * @retval None\r
+  */\r
+static void SetSysClockTo8(void)\r
+{\r
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;\r
+\r
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/\r
+  /* Enable HSE */\r
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);\r
+\r
+  /* Wait till HSE is ready and if Time out is reached exit */\r
+  do\r
+  {\r
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;\r
+    StartUpCounter++;\r
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));\r
+\r
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)\r
+  {\r
+    HSEStatus = (uint32_t)0x01;\r
+  }\r
+  else\r
+  {\r
+    HSEStatus = (uint32_t)0x00;\r
+  }\r
+\r
+  if (HSEStatus == (uint32_t)0x01)\r
+  {\r
+    /* Flash 0 wait state */\r
+    FLASH->ACR &= ~FLASH_ACR_LATENCY;\r
+\r
+    /* Disable Prefetch Buffer */\r
+    FLASH->ACR &= ~FLASH_ACR_PRFTEN;\r
+\r
+    /* Disable 64-bit access */\r
+    FLASH->ACR &= ~FLASH_ACR_ACC64;\r
+\r
+    /* Enable the PWR APB1 Clock */\r
+    RCC->APB1ENR |= RCC_APB1ENR_PWREN;\r
+\r
+    /* Select the Voltage Range 2 (1.5V) */\r
+    PWR->CR = PWR_CR_VOS_1;\r
+\r
+    /* Wait Until the Voltage Regulator is ready */\r
+    while((PWR->CSR & PWR_CSR_VOSF) != RESET)\r
+    {\r
+    }\r
+\r
+    /* HCLK = SYSCLK */\r
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;\r
+\r
+    /* PCLK2 = HCLK */\r
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;\r
+\r
+    /* PCLK1 = HCLK */\r
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;\r
+\r
+    /* Select HSE as system clock source */\r
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));\r
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;\r
+\r
+    /* Wait till HSE is used as system clock source */\r
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)\r
+    {\r
+    }\r
+  }\r
+  else\r
+  {\r
+    /* If HSE fails to start-up, the application will have wrong clock\r
+       configuration. User can add here some code to deal with this error */\r
+  }\r
+}\r
+\r
+#elif defined SYSCLK_FREQ_16MHz\r
+/**\r
+  * @brief  Sets System clock frequency to 16MHz and configure HCLK, PCLK2\r
+  *         and PCLK1 prescalers.\r
+  * @note   This function should be used only after reset.\r
+  * @param  None\r
+  * @retval None\r
+  */\r
+static void SetSysClockTo16(void)\r
+{\r
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;\r
+\r
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/\r
+  /* Enable HSE */\r
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);\r
+\r
+  /* Wait till HSE is ready and if Time out is reached exit */\r
+  do\r
+  {\r
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;\r
+    StartUpCounter++;\r
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));\r
+\r
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)\r
+  {\r
+    HSEStatus = (uint32_t)0x01;\r
+  }\r
+  else\r
+  {\r
+    HSEStatus = (uint32_t)0x00;\r
+  }\r
+\r
+  if (HSEStatus == (uint32_t)0x01)\r
+  {\r
+    /* Enable 64-bit access */\r
+    FLASH->ACR |= FLASH_ACR_ACC64;\r
+\r
+    /* Enable Prefetch Buffer */\r
+    FLASH->ACR |= FLASH_ACR_PRFTEN;\r
+\r
+    /* Flash 1 wait state */\r
+    FLASH->ACR |= FLASH_ACR_LATENCY;\r
+\r
+    /* Enable the PWR APB1 Clock */\r
+    RCC->APB1ENR |= RCC_APB1ENR_PWREN;\r
+\r
+    /* Select the Voltage Range 2 (1.5V) */\r
+    PWR->CR = PWR_CR_VOS_1;\r
+\r
+    /* Wait Until the Voltage Regulator is ready */\r
+    while((PWR->CSR & PWR_CSR_VOSF) != RESET)\r
+    {\r
+    }\r
+\r
+    /* HCLK = SYSCLK */\r
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV2;\r
+\r
+    /* PCLK2 = HCLK */\r
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;\r
+\r
+    /* PCLK1 = HCLK */\r
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;\r
+\r
+    /*  PLL configuration: PLLCLK = (HSE * 12) / 3 = 32MHz */\r
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLMUL |\r
+                                        RCC_CFGR_PLLDIV));\r
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMUL12 | RCC_CFGR_PLLDIV3);\r
+\r
+    /* Enable PLL */\r
+    RCC->CR |= RCC_CR_PLLON;\r
+\r
+    /* Wait till PLL is ready */\r
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)\r
+    {\r
+    }\r
+\r
+    /* Select PLL as system clock source */\r
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));\r
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;\r
+\r
+    /* Wait till PLL is used as system clock source */\r
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x0C)\r
+    {\r
+    }\r
+  }\r
+  else\r
+  {\r
+    /* If HSE fails to start-up, the application will have wrong clock\r
+       configuration. User can add here some code to deal with this error */\r
+  }\r
+}\r
+\r
+#elif defined SYSCLK_FREQ_32MHz\r
+/**\r
+  * @brief  Sets System clock frequency to 32MHz and configure HCLK, PCLK2\r
+  *         and PCLK1 prescalers.\r
+  * @note   This function should be used only after reset.\r
+  * @param  None\r
+  * @retval None\r
+  */\r
+static void SetSysClockTo32(void)\r
+{\r
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;\r
+\r
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/\r
+  /* Enable HSE */\r
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);\r
+\r
+  /* Wait till HSE is ready and if Time out is reached exit */\r
+  do\r
+  {\r
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;\r
+    StartUpCounter++;\r
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));\r
+\r
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)\r
+  {\r
+    HSEStatus = (uint32_t)0x01;\r
+  }\r
+  else\r
+  {\r
+    HSEStatus = (uint32_t)0x00;\r
+  }\r
+\r
+  if (HSEStatus == (uint32_t)0x01)\r
+  {\r
+    /* Enable 64-bit access */\r
+    FLASH->ACR |= FLASH_ACR_ACC64;\r
+\r
+    /* Enable Prefetch Buffer */\r
+    FLASH->ACR |= FLASH_ACR_PRFTEN;\r
+\r
+    /* Flash 1 wait state */\r
+    FLASH->ACR |= FLASH_ACR_LATENCY;\r
+\r
+    /* Enable the PWR APB1 Clock */\r
+    RCC->APB1ENR |= RCC_APB1ENR_PWREN;\r
+\r
+    /* Select the Voltage Range 1 (1.8V) */\r
+    PWR->CR = PWR_CR_VOS_0;\r
+\r
+    /* Wait Until the Voltage Regulator is ready */\r
+    while((PWR->CSR & PWR_CSR_VOSF) != RESET)\r
+    {\r
+    }\r
+\r
+    /* HCLK = SYSCLK */\r
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;\r
+\r
+    /* PCLK2 = HCLK */\r
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;\r
+\r
+    /* PCLK1 = HCLK */\r
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;\r
+\r
+    /*  PLL configuration: PLLCLK = (HSE * 12) / 3 = 32MHz */\r
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLMUL |\r
+                                        RCC_CFGR_PLLDIV));\r
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMUL12 | RCC_CFGR_PLLDIV3);\r
+\r
+    /* Enable PLL */\r
+    RCC->CR |= RCC_CR_PLLON;\r
+\r
+    /* Wait till PLL is ready */\r
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)\r
+    {\r
+    }\r
+\r
+    /* Select PLL as system clock source */\r
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));\r
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;\r
+\r
+    /* Wait till PLL is used as system clock source */\r
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x0C)\r
+    {\r
+    }\r
+  }\r
+  else\r
+  {\r
+    /* If HSE fails to start-up, the application will have wrong clock\r
+       configuration. User can add here some code to deal with this error */\r
+  }\r
+}\r
+\r
+#else\r
+/**\r
+  * @brief  Selects MSI as System clock source and configure HCLK, PCLK2\r
+  *         and PCLK1 prescalers.\r
+  * @note   This function should be used only after reset.\r
+  * @param  None\r
+  * @retval None\r
+  */\r
+static void SetSysClockToMSI(void)\r
+{\r
+  __IO uint32_t StartUpCounter = 0, MSIStatus = 0;\r
+\r
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/\r
+  /* Enable MSI */\r
+  RCC->CR |= ((uint32_t)RCC_CR_MSION);\r
+\r
+  /* Wait till MSI is ready and if Time out is reached exit */\r
+  do\r
+  {\r
+    MSIStatus = RCC->CR & RCC_CR_MSIRDY;\r
+    StartUpCounter++;\r
+  } while((MSIStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));\r
+\r
+  if ((RCC->CR & RCC_CR_MSIRDY) != RESET)\r
+  {\r
+    MSIStatus = (uint32_t)0x01;\r
+  }\r
+  else\r
+  {\r
+    MSIStatus = (uint32_t)0x00;\r
+  }\r
+\r
+  if (MSIStatus == (uint32_t)0x01)\r
+  {\r
+#ifdef SYSCLK_FREQ_MSI\r
+#ifdef SYSCLK_FREQ_MSI_4MHz\r
+    /* Enable 64-bit access */\r
+    FLASH->ACR |= FLASH_ACR_ACC64;\r
+\r
+    /* Enable Prefetch Buffer */\r
+    FLASH->ACR |= FLASH_ACR_PRFTEN;\r
+\r
+    /* Flash 1 wait state */\r
+    FLASH->ACR |= FLASH_ACR_LATENCY;\r
+#else\r
+    /* Flash 0 wait state */\r
+    FLASH->ACR &= ~FLASH_ACR_LATENCY;\r
+\r
+    /* Disable Prefetch Buffer */\r
+    FLASH->ACR &= ~FLASH_ACR_PRFTEN;\r
+\r
+    /* Disable 64-bit access */\r
+    FLASH->ACR &= ~FLASH_ACR_ACC64;\r
+#endif\r
+#endif\r
+    /* Enable the PWR APB1 Clock */\r
+    RCC->APB1ENR |= RCC_APB1ENR_PWREN;\r
+\r
+    /* Select the Voltage Range 3 (1.2V) */\r
+    PWR->CR = PWR_CR_VOS;\r
+\r
+    /* Wait Until the Voltage Regulator is ready */\r
+    while((PWR->CSR & PWR_CSR_VOSF) != RESET)\r
+    {\r
+    }\r
+\r
+    /* HCLK = SYSCLK */\r
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;\r
+\r
+    /* PCLK2 = HCLK */\r
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;\r
+\r
+    /* PCLK1 = HCLK */\r
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;\r
+\r
+#ifdef SYSCLK_FREQ_MSI\r
+  #ifdef SYSCLK_FREQ_MSI_64KHz\r
+    /* Set MSI clock range */\r
+    RCC->ICSCR &= (uint32_t)((uint32_t)~(RCC_ICSCR_MSIRANGE));\r
+    RCC->ICSCR |= (uint32_t)RCC_ICSCR_MSIRANGE_64KHz;\r
+  #elif defined SYSCLK_FREQ_MSI_128KHz\r
+    /* Set MSI clock range */\r
+    RCC->ICSCR &= (uint32_t)((uint32_t)~(RCC_ICSCR_MSIRANGE));\r
+    RCC->ICSCR |= (uint32_t)RCC_ICSCR_MSIRANGE_128KHz;\r
+  #elif defined SYSCLK_FREQ_MSI_256KHz\r
+    /* Set MSI clock range */\r
+    RCC->ICSCR &= (uint32_t)((uint32_t)~(RCC_ICSCR_MSIRANGE));\r
+    RCC->ICSCR |= (uint32_t)RCC_ICSCR_MSIRANGE_256KHz;\r
+  #elif defined SYSCLK_FREQ_MSI_512KHz\r
+    /* Set MSI clock range */\r
+    RCC->ICSCR &= (uint32_t)((uint32_t)~(RCC_ICSCR_MSIRANGE));\r
+    RCC->ICSCR |= (uint32_t)RCC_ICSCR_MSIRANGE_512KHz;\r
+  #elif defined SYSCLK_FREQ_MSI_1MHz\r
+    /* Set MSI clock range */\r
+    RCC->ICSCR &= (uint32_t)((uint32_t)~(RCC_ICSCR_MSIRANGE));\r
+    RCC->ICSCR |= (uint32_t)RCC_ICSCR_MSIRANGE_1MHz;\r
+  #elif defined SYSCLK_FREQ_MSI_2MHz\r
+    /* Set MSI clock range */\r
+    RCC->ICSCR &= (uint32_t)((uint32_t)~(RCC_ICSCR_MSIRANGE));\r
+    RCC->ICSCR |= (uint32_t)RCC_ICSCR_MSIRANGE_2MHz;\r
+  #elif defined SYSCLK_FREQ_MSI_4MHz\r
+    /* Set MSI clock range */\r
+    RCC->ICSCR &= (uint32_t)((uint32_t)~(RCC_ICSCR_MSIRANGE));\r
+    RCC->ICSCR |= (uint32_t)RCC_ICSCR_MSIRANGE_4MHz;\r
+  #endif\r
+#endif\r
+\r
+    /* Select MSI as system clock source */\r
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));\r
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_MSI;\r
+\r
+    /* Wait till MSI is used as system clock source */\r
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x00)\r
+    {\r
+    }\r
+  }\r
+  else\r
+  {\r
+    /* If MSI fails to start-up, the application will have wrong clock\r
+       configuration. User can add here some code to deal with this error */\r
+  }\r
+}\r
+#endif\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r