Remove jtag_rclk from target configs

Some boards might have RCLK omitted from the JTAG connector and if the
interface claims support for it, OpenOCD will end up trying to use
RCLK while it's actually impossible.

This is a "cd tcl/target; sed -i s/jtag_rclk/adapter_khz/g *" patch.

Change-Id: Iee7337107bc1457966b104389ba9db75a9c860b4
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/1695
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-by: Mathias Küster <kesmtp@freenet.de>

diff --git a/tcl/target/altera_fpgasoc.cfg b/tcl/target/altera_fpgasoc.cfg
index 9c7b4196e34b1dfb68f27012530afa3a6e046a2b..e876031c9692267709a3980af1453136966677c7 100644 (file)
--- a/tcl/target/altera_fpgasoc.cfg
+++ b/tcl/target/altera_fpgasoc.cfg
@@ -36,7 +36,7 @@ jtag newtap $_CHIPNAME.fpga tap -irlen 10 -ircapture 0x01 -irmask 0x3 -expected-
 # core 1  -  0x80112000
 
 # Slow speed to be sure it will work
-jtag_rclk 1000
+adapter_khz 1000
 
 set _TARGETNAME1 $_CHIPNAME.cpu.0
 set _TARGETNAME2 $_CHIPNAME.cpu.1
@@ -45,7 +45,7 @@ set _TARGETNAME2 $_CHIPNAME.cpu.1
 target create $_TARGETNAME1 cortex_a -chain-position $_CHIPNAME.dap \
         -coreid 0 -dbgbase 0x80110000
 
-$_TARGETNAME1 configure -event reset-start { jtag_rclk 1000 }
+$_TARGETNAME1 configure -event reset-start { adapter_khz 1000 }
 $_TARGETNAME1 configure -event reset-assert-post "cycv_dbginit $_TARGETNAME1"
 $_TARGETNAME1 configure -event gdb-attach { halt }
 
@@ -54,7 +54,7 @@ $_TARGETNAME1 configure -event gdb-attach { halt }
 #target create $_TARGETNAME2 cortex_a -chain-position $_CHIPNAME.dap \
 #        -coreid 1 -dbgbase 0x80112000
 
-#$_TARGETNAME2 configure -event reset-start { jtag_rclk 1000 }
+#$_TARGETNAME2 configure -event reset-start { adapter_khz 1000 }
 #$_TARGETNAME2 configure -event reset-assert-post "cycv_dbginit $_TARGETNAME2"
 #$_TARGETNAME2 configure -event gdb-attach { halt }
 

diff --git a/tcl/target/at91sam9.cfg b/tcl/target/at91sam9.cfg
index e6b297dcd8d8c8c60522410b59b221f8153e9108..f901ca8130f064eb281ad4267a5c6411188fed49 100644 (file)
--- a/tcl/target/at91sam9.cfg
+++ b/tcl/target/at91sam9.cfg
@@ -27,7 +27,7 @@ jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CP
 adapter_nsrst_delay 300
 jtag_ntrst_delay 200
 
-jtag_rclk 3
+adapter_khz 3
 
 ######################
 # Target configuration

diff --git a/tcl/target/at91sam9260_ext_RAM_ext_flash.cfg b/tcl/target/at91sam9260_ext_RAM_ext_flash.cfg
index f7121ec9ab156e27a09db2c14bb195620c64aa46..9ab7409048eb7aada94386feb62375d72874db3e 100644 (file)
--- a/tcl/target/at91sam9260_ext_RAM_ext_flash.cfg
+++ b/tcl/target/at91sam9260_ext_RAM_ext_flash.cfg
@@ -6,7 +6,7 @@ source [find target/at91sam9261.cfg]
 
 reset_config trst_and_srst
 
-jtag_rclk 4
+adapter_khz 4
 
 adapter_nsrst_delay 200
 jtag_ntrst_delay 200
@@ -14,7 +14,7 @@ jtag_ntrst_delay 200
 scan_chain
 $_TARGETNAME configure -event reset-start {
        # at reset chip runs at 32khz
-       jtag_rclk 8
+       adapter_khz 8
 }
 
 $_TARGETNAME configure -event reset-init {at91sam_init}
@@ -46,7 +46,7 @@ proc at91sam_init { } {
        sleep 10                          ;# wait 10 ms
 
        # Now run at anything fast... ie: 10mhz!
-       jtag_rclk 10000                    ;# Increase JTAG Speed to 6 MHz
+       adapter_khz 10000                    ;# Increase JTAG Speed to 6 MHz
 
        mww 0xffffec00 0x0a0a0a0a         ;# SMC_SETUP0 : Setup SMC for Intel NOR Flash JS28F128P30T85 128MBit
        mww 0xffffec04 0x0b0b0b0b         ;# SMC_PULSE0

diff --git a/tcl/target/at91sam9g20.cfg b/tcl/target/at91sam9g20.cfg
index 8a2e69b91f97530884e0e902064e7e74f2fded56..3f5e3c6264d3e63834e4abe48ea180d34be0ac58 100644 (file)
--- a/tcl/target/at91sam9g20.cfg
+++ b/tcl/target/at91sam9g20.cfg
@@ -12,7 +12,7 @@ source [find target/at91sam9.cfg]
 
 # Set fallback clock to 1/6 of worst-case clock speed (which would be the 32.768 kHz slow clock).
 
-jtag_rclk 5
+adapter_khz 5
 
 # Establish internal SRAM memory work areas that are important to pre-bootstrap loaders, etc.  The
 # AT91SAM9G20 has two SRAM areas, one starting at 0x00200000 and the other starting at 0x00300000.

diff --git a/tcl/target/imx6.cfg b/tcl/target/imx6.cfg
index d7f0b90662296e73a03024c53f558e68ad015ff0..622261fe6cfd12e471df8f340e2009a1281eabbc 100644 (file)
--- a/tcl/target/imx6.cfg
+++ b/tcl/target/imx6.cfg
@@ -51,8 +51,8 @@ proc imx6_dbginit {target} {
 }
 
 # Slow speed to be sure it will work
-jtag_rclk 1000
-$_TARGETNAME configure -event reset-start { jtag_rclk 1000 }
+adapter_khz 1000
+$_TARGETNAME configure -event reset-start { adapter_khz 1000 }
 
 $_TARGETNAME configure -event reset-assert-post "imx6_dbginit $_TARGETNAME"
 $_TARGETNAME configure -event gdb-attach { halt }

diff --git a/tcl/target/is5114.cfg b/tcl/target/is5114.cfg
index defd43c5267dbd5760b4e94c19b9bf5c60c69bc4..331625fd764381e2ff186c67425ce838f1cc7ea3 100644 (file)
--- a/tcl/target/is5114.cfg
+++ b/tcl/target/is5114.cfg
@@ -23,7 +23,7 @@ if { [info exists CPUTAPID] } {
 }
 
 # jtag speed. We need to stick to 16kHz until we've finished reset.
-jtag_rclk 16
+adapter_khz 16
 
 reset_config trst_and_srst
 
@@ -38,9 +38,9 @@ jtag newtap $_CHIPNAME unknown2 -irlen 5 -ircapture 1 -irmask 1
 set _TARGETNAME $_CHIPNAME.cpu
 target create $_TARGETNAME arm966e -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm966e
 
-$_TARGETNAME configure -event reset-start { jtag_rclk 16 }
+$_TARGETNAME configure -event reset-start { adapter_khz 16 }
 $_TARGETNAME configure -event reset-init {
        # We can increase speed now that we know the target is halted.
-       jtag_rclk 3000
+       adapter_khz 3000
 }
 $_TARGETNAME configure -work-area-phys 0x50000000 -work-area-size 16384 -work-area-backup 1

diff --git a/tcl/target/mc13224v.cfg b/tcl/target/mc13224v.cfg
index 8037125577e1b27130a8ef2bec1dee06a145e8ad..27ac8c3b29b3a0acf9e256b8340878076dfadbb8 100644 (file)
--- a/tcl/target/mc13224v.cfg
+++ b/tcl/target/mc13224v.cfg
@@ -35,7 +35,7 @@ reset_config srst_only
 jtag_ntrst_delay 200
 
 # rclk hasn't been working well. This maybe the mc13224v or something else.
-#jtag_rclk 2000
+#adapter_khz 2000
 adapter_khz 2000
 
 ######################

diff --git a/tcl/target/omap3530.cfg b/tcl/target/omap3530.cfg
index 0e20852ca12d499bbd9b851d6b8078e9a75fef0f..f9dcf7cbfe8a6fd47a03bdb0cc72823f1d9ce59c 100644 (file)
--- a/tcl/target/omap3530.cfg
+++ b/tcl/target/omap3530.cfg
@@ -62,8 +62,8 @@ proc omap3_dbginit {target} {
 # be absolutely certain the JTAG clock will work with the worst-case
 # 16.8MHz/2 = 8.4MHz core clock, even before a bootloader kicks in.
 # OK to speed up *after* PLL and clock tree setup.
-jtag_rclk 1000
-$_TARGETNAME configure -event "reset-start" { jtag_rclk 1000 }
+adapter_khz 1000
+$_TARGETNAME configure -event "reset-start" { adapter_khz 1000 }
 
 # Assume SRST is unavailable (e.g. TI-14 JTAG), so we must assert reset
 # ourselves using PRM_RSTCTRL.  RST_GS (2) is a warm reset, like ICEpick

diff --git a/tcl/target/omapl138.cfg b/tcl/target/omapl138.cfg
index 9a10d530cb8a8ef7bed7a9798f4072fb6f0fa0b3..fd9ff4c2e7d061ab5257b24662b9120b3be3fb6e 100644 (file)
--- a/tcl/target/omapl138.cfg
+++ b/tcl/target/omapl138.cfg
@@ -52,8 +52,8 @@ $_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 0x2000
 # be absolutely certain the JTAG clock will work with the worst-case
 # CLKIN = 20 MHz (best case: 30 MHz) even when no bootloader turns
 # on the PLL and starts using it.  OK to speed up after clock setup.
-jtag_rclk 1500
-$_TARGETNAME configure -event "reset-start" { jtag_rclk 1500 }
+adapter_khz 1500
+$_TARGETNAME configure -event "reset-start" { adapter_khz 1500 }
 
 arm7_9 fast_memory_access enable
 arm7_9 dcc_downloads enable

diff --git a/tcl/target/str912.cfg b/tcl/target/str912.cfg
index 599a254a043354ae55b2157066214c06301c1552..38545ac905c27e68adb4780c53e8ddfa83c15627 100644 (file)
--- a/tcl/target/str912.cfg
+++ b/tcl/target/str912.cfg
@@ -13,7 +13,7 @@ if { [info exists ENDIAN] } {
 }
 
 # jtag speed. We need to stick to 16kHz until we've finished reset.
-jtag_rclk 16
+adapter_khz 16
 
 adapter_nsrst_delay 100
 jtag_ntrst_delay 100
@@ -48,11 +48,11 @@ jtag newtap $_CHIPNAME bs -irlen 5 -ircapture 0x1 -irmask 0x1 -expected-id $_BST
 set _TARGETNAME $_CHIPNAME.cpu
 target create $_TARGETNAME arm966e -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm966e
 
-$_TARGETNAME configure -event reset-start { jtag_rclk 16 }
+$_TARGETNAME configure -event reset-start { adapter_khz 16 }
 
 $_TARGETNAME configure -event reset-init {
        # We can increase speed now that we know the target is halted.
-       #jtag_rclk 3000
+       #adapter_khz 3000
 
        # -- Enable 96K RAM
        # PFQBC enabled / DTCM & AHB wait-states disabled

diff --git a/tcl/target/ti_dm355.cfg b/tcl/target/ti_dm355.cfg
index 2903e5d8f8405c088bbe71f2cf44ce6eee9f54bc..4f8f523e889ded0fbc8b04381b4932d862bbd300 100644 (file)
--- a/tcl/target/ti_dm355.cfg
+++ b/tcl/target/ti_dm355.cfg
@@ -98,8 +98,8 @@ $_TARGETNAME configure \
 # be absolutely certain the JTAG clock will work with the worst-case
 # CLKIN = 24 MHz (best case: 36 MHz) even when no bootloader turns
 # on the PLL and starts using it.  OK to speed up after clock setup.
-jtag_rclk 1500
-$_TARGETNAME configure -event "reset-start" { jtag_rclk 1500 }
+adapter_khz 1500
+$_TARGETNAME configure -event "reset-start" { adapter_khz 1500 }
 
 arm7_9 fast_memory_access enable
 arm7_9 dcc_downloads enable

diff --git a/tcl/target/ti_dm365.cfg b/tcl/target/ti_dm365.cfg
index a260278601155a8693f38baf4178b30e4e1747a5..0db83dbaa3cde90840fe253aea20c19756e6a9de 100644 (file)
--- a/tcl/target/ti_dm365.cfg
+++ b/tcl/target/ti_dm365.cfg
@@ -90,8 +90,8 @@ $_TARGETNAME configure \
 # be absolutely certain the JTAG clock will work with the worst-case
 # CLKIN = 19.2 MHz (best case: 36 MHz) even when no bootloader turns
 # on the PLL and starts using it.  OK to speed up after clock setup.
-jtag_rclk 1500
-$_TARGETNAME configure -event "reset-start" { jtag_rclk 1500 }
+adapter_khz 1500
+$_TARGETNAME configure -event "reset-start" { adapter_khz 1500 }
 
 arm7_9 fast_memory_access enable
 arm7_9 dcc_downloads enable

diff --git a/tcl/target/ti_dm6446.cfg b/tcl/target/ti_dm6446.cfg
index 4f100843b18a32957a92f2b0b1d012d9c42008df..fa1e6e957c316cb74552198aa9daacee9fcc5153 100644 (file)
--- a/tcl/target/ti_dm6446.cfg
+++ b/tcl/target/ti_dm6446.cfg
@@ -70,8 +70,8 @@ $_TARGETNAME configure -work-area-phys 0x0000a000 -work-area-size 0x2000
 # be absolutely certain the JTAG clock will work with the worst-case
 # CLKIN = 20 MHz (best case: 30 MHz) even when no bootloader turns
 # on the PLL and starts using it.  OK to speed up after clock setup.
-jtag_rclk 1500
-$_TARGETNAME configure -event "reset-start" { jtag_rclk 1500 }
+adapter_khz 1500
+$_TARGETNAME configure -event "reset-start" { adapter_khz 1500 }
 
 arm7_9 fast_memory_access enable
 arm7_9 dcc_downloads enable