--- /dev/null
+/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************\r
+* File Name : stm32fxxx_eth.c\r
+* Author : MCD Application Team\r
+* Version : V1.0.0\r
+* Date : 12/17/2008\r
+* Updates : 05/2009 Driver optimization.\r
+* - No copy. DMA directly uses Stack packets.\r
+* Desciption : This file provides all the ETHERNET firmware functions.\r
+********************************************************************************\r
+* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,\r
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE\r
+* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING\r
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+*******************************************************************************/\r
+\r
+/* For the delays. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32fxxx_eth.h"\r
+#include "stm32f10x_rcc.h"\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* Global pointers on Tx and Rx descriptor used to track transmit and receive descriptors */\r
+ETH_DMADESCTypeDef *DMATxDescToSet;\r
+ETH_DMADESCTypeDef *DMARxDescToGet;\r
+\r
+ETH_DMADESCTypeDef *DMAPTPTxDescToSet;\r
+ETH_DMADESCTypeDef *DMAPTPRxDescToGet;\r
+\r
+/* ETHERNET MAC address offsets */\r
+#define ETH_MAC_AddrHighBase (ETH_MAC_BASE + 0x40) /* ETHERNET MAC address high offset */\r
+#define ETH_MAC_AddrLowBase (ETH_MAC_BASE + 0x44) /* ETHERNET MAC address low offset */\r
+\r
+/* ETHERNET MACMIIAR register Mask */\r
+#define MACMIIAR_CR_Mask ((u32)0xFFFFFFE3)\r
+/* ETHERNET MACCR register Mask */\r
+#define MACCR_CLEAR_Mask ((u32)0xFF20810F)\r
+/* ETHERNET MACFCR register Mask */\r
+#define MACFCR_CLEAR_Mask ((u32)0x0000FF41)\r
+/* ETHERNET DMAOMR register Mask */\r
+#define DMAOMR_CLEAR_Mask ((u32)0xF8DE3F23)\r
+\r
+/* ETHERNET Remote Wake-up frame register length */\r
+#define ETH_WakeupRegisterLength 8\r
+\r
+/* ETHERNET Missed frames counter Shift */\r
+#define ETH_DMA_RxOverflowMissedFramesCounterShift 17\r
+\r
+/* ETHERNET DMA Tx descriptors Collision Count Shift */\r
+#define ETH_DMATxDesc_CollisionCountShift 3\r
+/* ETHERNET DMA Tx descriptors Buffer2 Size Shift */\r
+#define ETH_DMATxDesc_BufferSize2Shift 16\r
+/* ETHERNET DMA Rx descriptors Frame Length Shift */\r
+#define ETH_DMARxDesc_FrameLengthShift 16\r
+/* ETHERNET DMA Rx descriptors Buffer2 Size Shift */\r
+#define ETH_DMARxDesc_Buffer2SizeShift 16\r
+\r
+/* ETHERNET errors */\r
+#define ETH_ERROR ((u32)0)\r
+#define ETH_SUCCESS ((u32)1)\r
+\r
+#define ethFIVE_SECONDS ( 5000 / portTICK_RATE_MS )\r
+#define ethHUNDRED_MS ( 100 / portTICK_RATE_MS )\r
+\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/*******************************************************************************\r
+* Function Name : ETH_DeInit\r
+* Desciption : Deinitializes the ETHERNET peripheral registers to their\r
+* default reset values.\r
+* Input : None\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void ETH_DeInit(void)\r
+{\r
+// RCC_AHBPeriphResetCmd(RCC_AHBPeriph_ETH_MAC, ENABLE);\r
+// RCC_AHBPeriphResetCmd(RCC_AHBPeriph_ETH_MAC, DISABLE);\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : ETH_Init\r
+* Desciption : Initializes the ETHERNET peripheral according to the specified\r
+* parameters in the ETH_InitStruct .\r
+* Input : - ETH_InitStruct: pointer to a ETH_InitTypeDef structure\r
+* that contains the configuration information for the\r
+* specified ETHERNET peripheral.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+u32 ETH_Init(ETH_InitTypeDef* ETH_InitStruct, u16 PHYAddress)\r
+{\r
+ u32 RegValue = 0, tmpreg = 0;\r
+ RCC_ClocksTypeDef rcc_clocks;\r
+ u32 hclk = 60000000;\r
+ u32 timeout = 0;\r
+\r
+ /* Check the parameters */\r
+ /* MAC --------------------------*/\r
+ eth_assert_param(IS_ETH_AUTONEGOTIATION(ETH_InitStruct->ETH_AutoNegotiation));\r
+ eth_assert_param(IS_ETH_WATCHDOG(ETH_InitStruct->ETH_Watchdog));\r
+ eth_assert_param(IS_ETH_JABBER(ETH_InitStruct->ETH_Jabber));\r
+ eth_assert_param(IS_ETH_JUMBO_FRAME(ETH_InitStruct->ETH_JumboFrame));\r
+ eth_assert_param(IS_ETH_INTER_FRAME_GAP(ETH_InitStruct->ETH_InterFrameGap));\r
+ eth_assert_param(IS_ETH_CARRIER_SENSE(ETH_InitStruct->ETH_CarrierSense));\r
+ eth_assert_param(IS_ETH_SPEED(ETH_InitStruct->ETH_Speed));\r
+ eth_assert_param(IS_ETH_RECEIVE_OWN(ETH_InitStruct->ETH_ReceiveOwn));\r
+ eth_assert_param(IS_ETH_LOOPBACK_MODE(ETH_InitStruct->ETH_LoopbackMode));\r
+ eth_assert_param(IS_ETH_DUPLEX_MODE(ETH_InitStruct->ETH_Mode));\r
+ eth_assert_param(IS_ETH_CHECKSUM_OFFLOAD(ETH_InitStruct->ETH_ChecksumOffload));\r
+ eth_assert_param(IS_ETH_RETRY_TRANSMISSION(ETH_InitStruct->ETH_RetryTransmission));\r
+ eth_assert_param(IS_ETH_AUTOMATIC_PADCRC_STRIP(ETH_InitStruct->ETH_AutomaticPadCRCStrip));\r
+ eth_assert_param(IS_ETH_BACKOFF_LIMIT(ETH_InitStruct->ETH_BackOffLimit));\r
+ eth_assert_param(IS_ETH_DEFERRAL_CHECK(ETH_InitStruct->ETH_DeferralCheck));\r
+ eth_assert_param(IS_ETH_RECEIVE_ALL(ETH_InitStruct->ETH_ReceiveAll));\r
+ eth_assert_param(IS_ETH_SOURCE_ADDR_FILTER(ETH_InitStruct->ETH_SourceAddrFilter));\r
+ eth_assert_param(IS_ETH_CONTROL_FRAMES(ETH_InitStruct->ETH_PassControlFrames));\r
+ eth_assert_param(IS_ETH_BROADCAST_FRAMES_RECEPTION(ETH_InitStruct->ETH_BroadcastFramesReception));\r
+ eth_assert_param(IS_ETH_DESTINATION_ADDR_FILTER(ETH_InitStruct->ETH_DestinationAddrFilter));\r
+ eth_assert_param(IS_ETH_PROMISCUOUS_MODE(ETH_InitStruct->ETH_PromiscuousMode));\r
+ eth_assert_param(IS_ETH_MULTICAST_FRAMES_FILTER(ETH_InitStruct->ETH_MulticastFramesFilter));\r
+ eth_assert_param(IS_ETH_UNICAST_FRAMES_FILTER(ETH_InitStruct->ETH_UnicastFramesFilter));\r
+ eth_assert_param(IS_ETH_PAUSE_TIME(ETH_InitStruct->ETH_PauseTime));\r
+ eth_assert_param(IS_ETH_ZEROQUANTA_PAUSE(ETH_InitStruct->ETH_ZeroQuantaPause));\r
+ eth_assert_param(IS_ETH_PAUSE_LOW_THRESHOLD(ETH_InitStruct->ETH_PauseLowThreshold));\r
+ eth_assert_param(IS_ETH_UNICAST_PAUSE_FRAME_DETECT(ETH_InitStruct->ETH_UnicastPauseFrameDetect));\r
+ eth_assert_param(IS_ETH_RECEIVE_FLOWCONTROL(ETH_InitStruct->ETH_ReceiveFlowControl));\r
+ eth_assert_param(IS_ETH_TRANSMIT_FLOWCONTROL(ETH_InitStruct->ETH_TransmitFlowControl));\r
+ eth_assert_param(IS_ETH_VLAN_TAG_COMPARISON(ETH_InitStruct->ETH_VLANTagComparison));\r
+ eth_assert_param(IS_ETH_VLAN_TAG_IDENTIFIER(ETH_InitStruct->ETH_VLANTagIdentifier));\r
+ /* DMA --------------------------*/\r
+ eth_assert_param(IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(ETH_InitStruct->ETH_DropTCPIPChecksumErrorFrame));\r
+ eth_assert_param(IS_ETH_RECEIVE_STORE_FORWARD(ETH_InitStruct->ETH_ReceiveStoreForward));\r
+ eth_assert_param(IS_ETH_FLUSH_RECEIVE_FRAME(ETH_InitStruct->ETH_FlushReceivedFrame));\r
+ eth_assert_param(IS_ETH_TRANSMIT_STORE_FORWARD(ETH_InitStruct->ETH_TransmitStoreForward));\r
+ eth_assert_param(IS_ETH_TRANSMIT_THRESHOLD_CONTROL(ETH_InitStruct->ETH_TransmitThresholdControl));\r
+ eth_assert_param(IS_ETH_FORWARD_ERROR_FRAMES(ETH_InitStruct->ETH_ForwardErrorFrames));\r
+ eth_assert_param(IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(ETH_InitStruct->ETH_ForwardUndersizedGoodFrames));\r
+ eth_assert_param(IS_ETH_RECEIVE_THRESHOLD_CONTROL(ETH_InitStruct->ETH_ReceiveThresholdControl));\r
+ eth_assert_param(IS_ETH_SECOND_FRAME_OPERATE(ETH_InitStruct->ETH_SecondFrameOperate));\r
+ eth_assert_param(IS_ETH_ADDRESS_ALIGNED_BEATS(ETH_InitStruct->ETH_AddressAlignedBeats));\r
+ eth_assert_param(IS_ETH_FIXED_BURST(ETH_InitStruct->ETH_FixedBurst));\r
+ eth_assert_param(IS_ETH_RXDMA_BURST_LENGTH(ETH_InitStruct->ETH_RxDMABurstLength));\r
+ eth_assert_param(IS_ETH_TXDMA_BURST_LENGTH(ETH_InitStruct->ETH_TxDMABurstLength));\r
+ eth_assert_param(IS_ETH_DMA_DESC_SKIP_LENGTH(ETH_InitStruct->ETH_DescriptorSkipLength));\r
+ eth_assert_param(IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(ETH_InitStruct->ETH_DMAArbitration));\r
+\r
+/*--------------------------------- MAC Config -------------------------------*/\r
+/*----------------------- ETHERNET MACMIIAR Configuration --------------------*/\r
+ /* Get the ETHERNET MACMIIAR value */\r
+ tmpreg = ETH_MAC->MACMIIAR;\r
+ /* Clear CSR Clock Range CR[2:0] bits */\r
+ tmpreg &= MACMIIAR_CR_Mask;\r
+ /* Get hclk frequency value */\r
+ RCC_GetClocksFreq(&rcc_clocks);\r
+ hclk = rcc_clocks.HCLK_Frequency;\r
+\r
+ /* Set CR bits depending on hclk value */\r
+ if((hclk >= 20000000)&&(hclk < 35000000))\r
+ {\r
+ /* CSR Clock Range between 20-35 MHz */\r
+ tmpreg |= (u32)ETH_MACMIIAR_CR_Div16;\r
+ }\r
+ else if((hclk >= 35000000)&&(hclk < 60000000))\r
+ {\r
+ /* CSR Clock Range between 35-60 MHz */\r
+ tmpreg |= (u32)ETH_MACMIIAR_CR_Div26;\r
+ }\r
+ else /* ((hclk >= 60000000)&&(hclk <= 72000000)) */\r
+ {\r
+ /* CSR Clock Range between 60-72 MHz */\r
+ tmpreg |= (u32)ETH_MACMIIAR_CR_Div42;\r
+ }\r
+ /* Write to ETHERNET MAC MIIAR: Configure the ETHERNET CSR Clock Range */\r
+ ETH_MAC->MACMIIAR = (u32)tmpreg;\r
+\r
+/*--------------------- PHY initialization and configuration -----------------*/\r
+ /* Put the PHY in reset mode */\r
+ if(!(ETH_WritePHYRegister(PHYAddress, PHY_BCR, PHY_Reset)))\r
+ {\r
+ /* Return ERROR in case of write timeout */\r
+ return ETH_ERROR;\r
+ }\r
+\r
+ /* Delay to assure PHY reset */\r
+ vTaskDelay( 250 / portTICK_RATE_MS );\r
+\r
+ if(ETH_InitStruct->ETH_AutoNegotiation != ETH_AutoNegotiation_Disable)\r
+ {\r
+ /* We wait for linked satus... */\r
+ timeout = 0;\r
+ do\r
+ {\r
+ /* Wait 100ms before checking for a link again. */\r
+ vTaskDelay( ethHUNDRED_MS );\r
+ timeout++;\r
+\r
+ /* Don't wait any longer than 5 seconds. */\r
+ } while (!(ETH_ReadPHYRegister(PHYAddress, PHY_BSR) & PHY_Linked_Status) && (timeout < ( ethFIVE_SECONDS / ethHUNDRED_MS ) ) );\r
+\r
+ /* Return ERROR in case of timeout */\r
+ if(timeout == ( ethFIVE_SECONDS / ethHUNDRED_MS ))\r
+ {\r
+ return ETH_ERROR;\r
+ }\r
+\r
+ /* Enable Auto-Negotiation */\r
+ if(!(ETH_WritePHYRegister(PHYAddress, PHY_BCR, PHY_AutoNegotiation)))\r
+ {\r
+ /* Return ERROR in case of write timeout */\r
+ return ETH_ERROR;\r
+ }\r
+\r
+ /* Reset Timeout counter */\r
+ timeout = 0;\r
+\r
+ /* Wait until the autonegotiation will be completed */\r
+ do\r
+ {\r
+ /* Wait 100ms before checking for negotiation to complete. */\r
+ vTaskDelay( ethHUNDRED_MS );\r
+ timeout++;\r
+\r
+ /* Don't wait longer than 5 seconds. */\r
+ } while (!(ETH_ReadPHYRegister(PHYAddress, PHY_BSR) & PHY_AutoNego_Complete) && (timeout < ( ethFIVE_SECONDS / ethHUNDRED_MS ) ) );\r
+\r
+ /* Return ERROR in case of timeout */\r
+ if(timeout == ( ethFIVE_SECONDS / ethHUNDRED_MS ))\r
+ {\r
+ return ETH_ERROR;\r
+ }\r
+\r
+ /* Reset Timeout counter */\r
+ timeout = 0;\r
+\r
+ /* Read the result of the autonegotiation */\r
+ RegValue = ETH_ReadPHYRegister(PHYAddress, PHY_SR);\r
+\r
+ /* Configure the MAC with the Duplex Mode fixed by the autonegotiation process */\r
+ if((RegValue & PHY_Duplex_Status) != (u32)RESET)\r
+ {\r
+ /* Set Ethernet duplex mode to FullDuplex following the autonegotiation */\r
+ ETH_InitStruct->ETH_Mode = ETH_Mode_FullDuplex;\r
+\r
+ }\r
+ else\r
+ {\r
+ /* Set Ethernet duplex mode to HalfDuplex following the autonegotiation */\r
+ ETH_InitStruct->ETH_Mode = ETH_Mode_HalfDuplex;\r
+ }\r
+ /* Configure the MAC with the speed fixed by the autonegotiation process */\r
+ if(RegValue & PHY_Speed_Status)\r
+ {\r
+ /* Set Ethernet speed to 100M following the autonegotiation */\r
+ ETH_InitStruct->ETH_Speed = ETH_Speed_10M;\r
+ }\r
+ else\r
+ {\r
+ /* Set Ethernet speed to 10M following the autonegotiation */\r
+ ETH_InitStruct->ETH_Speed = ETH_Speed_100M;\r
+ }\r
+ }\r
+// else\r
+ {\r
+ if(!ETH_WritePHYRegister(PHYAddress, PHY_BCR, ((u16)(ETH_InitStruct->ETH_Mode >> 3) |\r
+ (u16)(ETH_InitStruct->ETH_Speed >> 1))))\r
+ {\r
+ /* Return ERROR in case of write timeout */\r
+ return ETH_ERROR;\r
+ }\r
+\r
+ vTaskDelay( 250 / portTICK_RATE_MS );\r
+ }\r
+\r
+/*------------------------- ETHERNET MACCR Configuration ---------------------*/\r
+ /* Get the ETHERNET MACCR value */\r
+ tmpreg = ETH_MAC->MACCR;\r
+ /* Clear WD, PCE, PS, TE and RE bits */\r
+ tmpreg &= MACCR_CLEAR_Mask;\r
+\r
+ /* Set the WD bit according to ETH_Watchdog value */\r
+ /* Set the JD: bit according to ETH_Jabber value */\r
+ /* Set the JE bit according to ETH_JumboFrame value */\r
+ /* Set the IFG bit according to ETH_InterFrameGap value */\r
+ /* Set the DCRS bit according to ETH_CarrierSense value */\r
+ /* Set the FES bit according to ETH_Speed value */\r
+ /* Set the DO bit according to ETH_ReceiveOwn value */\r
+ /* Set the LM bit according to ETH_LoopbackMode value */\r
+ /* Set the DM bit according to ETH_Mode value */\r
+ /* Set the IPC bit according to ETH_ChecksumOffload value */\r
+ /* Set the DR bit according to ETH_RetryTransmission value */\r
+ /* Set the ACS bit according to ETH_AutomaticPadCRCStrip value */\r
+ /* Set the BL bit according to ETH_BackOffLimit value */\r
+ /* Set the DC bit according to ETH_DeferralCheck value */\r
+ tmpreg |= (u32)(ETH_InitStruct->ETH_Watchdog |\r
+ ETH_InitStruct->ETH_Jabber |\r
+ ETH_InitStruct->ETH_JumboFrame |\r
+ ETH_InitStruct->ETH_InterFrameGap |\r
+ ETH_InitStruct->ETH_CarrierSense |\r
+ ETH_InitStruct->ETH_Speed |\r
+ ETH_InitStruct->ETH_ReceiveOwn |\r
+ ETH_InitStruct->ETH_LoopbackMode |\r
+ ETH_InitStruct->ETH_Mode |\r
+ ETH_InitStruct->ETH_ChecksumOffload |\r
+ ETH_InitStruct->ETH_RetryTransmission |\r
+ ETH_InitStruct->ETH_AutomaticPadCRCStrip |\r
+ ETH_InitStruct->ETH_BackOffLimit |\r
+ ETH_InitStruct->ETH_DeferralCheck);\r
+\r
+ /* Write to ETHERNET MACCR */\r
+ ETH_MAC->MACCR = (u32)tmpreg;\r
+\r
+/*------------------------ ETHERNET MACFFR Configuration ---------------------*/\r
+ /* Set the RA bit according to ETH_ReceiveAll value */\r
+ /* Set the SAF and SAIF bits according to ETH_SourceAddrFilter value */\r
+ /* Set the PCF bit according to ETH_PassControlFrames value */\r
+ /* Set the DBF bit according to ETH_BroadcastFramesReception value */\r
+ /* Set the DAIF bit according to ETH_DestinationAddrFilter value */\r
+ /* Set the PR bit according to ETH_PromiscuousMode value */\r
+ /* Set the PM, HMC and HPF bits according to ETH_MulticastFramesFilter value */\r
+ /* Set the HUC and HPF bits according to ETH_UnicastFramesFilter value */\r
+ /* Write to ETHERNET MACFFR */\r
+ ETH_MAC->MACFFR = (u32)(ETH_InitStruct->ETH_ReceiveAll |\r
+ ETH_InitStruct->ETH_SourceAddrFilter |\r
+ ETH_InitStruct->ETH_PassControlFrames |\r
+ ETH_InitStruct->ETH_BroadcastFramesReception |\r
+ ETH_InitStruct->ETH_DestinationAddrFilter |\r
+ ETH_InitStruct->ETH_PromiscuousMode |\r
+ ETH_InitStruct->ETH_MulticastFramesFilter |\r
+ ETH_InitStruct->ETH_UnicastFramesFilter);\r
+\r
+/*---------------- ETHERNET MACHTHR and MACHTLR Configuration ----------------*/\r
+ /* Write to ETHERNET MACHTHR */\r
+ ETH_MAC->MACHTHR = (u32)ETH_InitStruct->ETH_HashTableHigh;\r
+ /* Write to ETHERNET MACHTLR */\r
+ ETH_MAC->MACHTLR = (u32)ETH_InitStruct->ETH_HashTableLow;\r
+\r
+/*------------------------ ETHERNET MACFCR Configuration ---------------------*/\r
+ /* Get the ETHERNET MACFCR value */\r
+ tmpreg = ETH_MAC->MACFCR;\r
+ /* Clear xx bits */\r
+ tmpreg &= MACFCR_CLEAR_Mask;\r
+\r
+ /* Set the PT bit according to ETH_PauseTime value */\r
+ /* Set the DZPQ bit according to ETH_ZeroQuantaPause value */\r
+ /* Set the PLT bit according to ETH_PauseLowThreshold value */\r
+ /* Set the UP bit according to ETH_UnicastPauseFrameDetect value */\r
+ /* Set the RFE bit according to ETH_ReceiveFlowControl value */\r
+ /* Set the TFE bit according to ETH_TransmitFlowControl value */\r
+ tmpreg |= (u32)((ETH_InitStruct->ETH_PauseTime << 16) |\r
+ ETH_InitStruct->ETH_ZeroQuantaPause |\r
+ ETH_InitStruct->ETH_PauseLowThreshold |\r
+ ETH_InitStruct->ETH_UnicastPauseFrameDetect |\r
+ ETH_InitStruct->ETH_ReceiveFlowControl |\r
+ ETH_InitStruct->ETH_TransmitFlowControl);\r
+\r
+ /* Write to ETHERNET MACFCR */\r
+ ETH_MAC->MACFCR = (u32)tmpreg;\r
+\r
+/*------------------------ ETHERNET MACVLANTR Configuration ------------------*/\r
+ /* Set the ETV bit according to ETH_VLANTagComparison value */\r
+ /* Set the VL bit according to ETH_VLANTagIdentifier value */\r
+ ETH_MAC->MACVLANTR = (u32)(ETH_InitStruct->ETH_VLANTagComparison |\r
+ ETH_InitStruct->ETH_VLANTagIdentifier);\r
+\r
+#ifdef _ETH_DMA\r
+/*--------------------------------- DMA Config -------------------------------*/\r
+/*------------------------ ETHERNET DMAOMR Configuration ---------------------*/\r
+ /* Get the ETHERNET DMAOMR value */\r
+ tmpreg = ETH_DMA->DMAOMR;\r
+ /* Clear xx bits */\r
+ tmpreg &= DMAOMR_CLEAR_Mask;\r
+\r
+ /* Set the DT bit according to ETH_DropTCPIPChecksumErrorFrame value */\r
+ /* Set the RSF bit according to ETH_ReceiveStoreForward value */\r
+ /* Set the DFF bit according to ETH_FlushReceivedFrame value */\r
+ /* Set the TSF bit according to ETH_TransmitStoreForward value */\r
+ /* Set the TTC bit according to ETH_TransmitThresholdControl value */\r
+ /* Set the FEF bit according to ETH_ForwardErrorFrames value */\r
+ /* Set the FUF bit according to ETH_ForwardUndersizedGoodFrames value */\r
+ /* Set the RTC bit according to ETH_ReceiveThresholdControl value */\r
+ /* Set the OSF bit according to ETH_SecondFrameOperate value */\r
+ tmpreg |= (u32)(ETH_InitStruct->ETH_DropTCPIPChecksumErrorFrame |\r
+ ETH_InitStruct->ETH_ReceiveStoreForward |\r
+ ETH_InitStruct->ETH_FlushReceivedFrame |\r
+ ETH_InitStruct->ETH_TransmitStoreForward |\r
+ ETH_InitStruct->ETH_TransmitThresholdControl |\r
+ ETH_InitStruct->ETH_ForwardErrorFrames |\r
+ ETH_InitStruct->ETH_ForwardUndersizedGoodFrames |\r
+ ETH_InitStruct->ETH_ReceiveThresholdControl |\r
+ ETH_InitStruct->ETH_SecondFrameOperate);\r
+\r
+ /* Write to ETHERNET DMAOMR */\r
+ ETH_DMA->DMAOMR = (u32)tmpreg;\r
+\r
+/*------------------------ ETHERNET DMABMR Configuration ---------------------*/\r
+ /* Set the AAL bit according to ETH_AddressAlignedBeats value */\r
+ /* Set the FB bit according to ETH_FixedBurst value */\r
+ /* Set the RPBL and 4*PBL bits according to ETH_RxDMABurstLength value */\r
+ /* Set the PBL and 4*PBL bits according to ETH_TxDMABurstLength value */\r
+ /* Set the DSL bit according to ETH_DesciptorSkipLength value */\r
+ /* Set the PR and DA bits according to ETH_DMAArbitration value */\r
+ ETH_DMA->DMABMR = (u32)(ETH_InitStruct->ETH_AddressAlignedBeats |\r
+ ETH_InitStruct->ETH_FixedBurst |\r
+ ETH_InitStruct->ETH_RxDMABurstLength | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */\r
+ ETH_InitStruct->ETH_TxDMABurstLength |\r
+ (ETH_InitStruct->ETH_DescriptorSkipLength << 2) |\r
+ ETH_InitStruct->ETH_DMAArbitration |\r
+ ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */\r
+#endif /* _ETH_DMA */\r
+\r
+ /* Return Ethernet configuration success */\r
+ return ETH_SUCCESS;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : ETH_StructInit\r
+* Desciption : Fills each ETH_InitStruct member with its default value.\r
+* Input : - ETH_InitStruct: pointer to a ETH_InitTypeDef structure\r
+* which will be initialized.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void ETH_StructInit(ETH_InitTypeDef* ETH_InitStruct)\r
+{\r
+ /* ETH_InitStruct members default value */\r
+ /*------------------------ MAC -----------------------------------*/\r
+ ETH_InitStruct->ETH_AutoNegotiation = ETH_AutoNegotiation_Disable;\r
+ ETH_InitStruct->ETH_Watchdog = ETH_Watchdog_Enable;\r
+ ETH_InitStruct->ETH_Jabber = ETH_Jabber_Enable;\r
+ ETH_InitStruct->ETH_JumboFrame = ETH_JumboFrame_Disable;\r
+ ETH_InitStruct->ETH_InterFrameGap = ETH_InterFrameGap_96Bit;\r
+ ETH_InitStruct->ETH_CarrierSense = ETH_CarrierSense_Enable;\r
+ ETH_InitStruct->ETH_Speed = ETH_Speed_10M;\r
+ ETH_InitStruct->ETH_ReceiveOwn = ETH_ReceiveOwn_Enable;\r
+ ETH_InitStruct->ETH_LoopbackMode = ETH_LoopbackMode_Disable;\r
+ ETH_InitStruct->ETH_Mode = ETH_Mode_HalfDuplex;\r
+ ETH_InitStruct->ETH_ChecksumOffload = ETH_ChecksumOffload_Disable;\r
+ ETH_InitStruct->ETH_RetryTransmission = ETH_RetryTransmission_Enable;\r
+ ETH_InitStruct->ETH_AutomaticPadCRCStrip = ETH_AutomaticPadCRCStrip_Disable;\r
+ ETH_InitStruct->ETH_BackOffLimit = ETH_BackOffLimit_10;\r
+ ETH_InitStruct->ETH_DeferralCheck = ETH_DeferralCheck_Disable;\r
+ ETH_InitStruct->ETH_ReceiveAll = ETH_ReceiveAll_Disable;\r
+ ETH_InitStruct->ETH_SourceAddrFilter = ETH_SourceAddrFilter_Disable;\r
+ ETH_InitStruct->ETH_PassControlFrames = ETH_PassControlFrames_BlockAll;\r
+ ETH_InitStruct->ETH_BroadcastFramesReception = ETH_BroadcastFramesReception_Disable;\r
+ ETH_InitStruct->ETH_DestinationAddrFilter = ETH_DestinationAddrFilter_Normal;\r
+ ETH_InitStruct->ETH_PromiscuousMode = ETH_PromiscuousMode_Disable;\r
+ ETH_InitStruct->ETH_MulticastFramesFilter = ETH_MulticastFramesFilter_Perfect;\r
+ ETH_InitStruct->ETH_UnicastFramesFilter = ETH_UnicastFramesFilter_Perfect;\r
+ ETH_InitStruct->ETH_HashTableHigh = 0x0;\r
+ ETH_InitStruct->ETH_HashTableLow = 0x0;\r
+ ETH_InitStruct->ETH_PauseTime = 0x0;\r
+ ETH_InitStruct->ETH_ZeroQuantaPause = ETH_ZeroQuantaPause_Disable;\r
+ ETH_InitStruct->ETH_PauseLowThreshold = ETH_PauseLowThreshold_Minus4;\r
+ ETH_InitStruct->ETH_UnicastPauseFrameDetect = ETH_UnicastPauseFrameDetect_Disable;\r
+ ETH_InitStruct->ETH_ReceiveFlowControl = ETH_ReceiveFlowControl_Disable;\r
+ ETH_InitStruct->ETH_TransmitFlowControl = ETH_TransmitFlowControl_Disable;\r
+ ETH_InitStruct->ETH_VLANTagComparison = ETH_VLANTagComparison_16Bit;\r
+ ETH_InitStruct->ETH_VLANTagIdentifier = 0x0;\r
+\r
+#ifdef _ETH_DMA\r
+/*------------------------ DMA -----------------------------------*/\r
+ ETH_InitStruct->ETH_DropTCPIPChecksumErrorFrame = ETH_DropTCPIPChecksumErrorFrame_Disable;\r
+ ETH_InitStruct->ETH_ReceiveStoreForward = ETH_ReceiveStoreForward_Enable;\r
+ ETH_InitStruct->ETH_FlushReceivedFrame = ETH_FlushReceivedFrame_Disable;\r
+ ETH_InitStruct->ETH_TransmitStoreForward = ETH_TransmitStoreForward_Enable;\r
+ ETH_InitStruct->ETH_TransmitThresholdControl = ETH_TransmitThresholdControl_64Bytes;\r
+ ETH_InitStruct->ETH_ForwardErrorFrames = ETH_ForwardErrorFrames_Disable;\r
+ ETH_InitStruct->ETH_ForwardUndersizedGoodFrames = ETH_ForwardUndersizedGoodFrames_Disable;\r
+ ETH_InitStruct->ETH_ReceiveThresholdControl = ETH_ReceiveThresholdControl_64Bytes;\r
+ ETH_InitStruct->ETH_SecondFrameOperate = ETH_SecondFrameOperate_Disable;\r
+ ETH_InitStruct->ETH_AddressAlignedBeats = ETH_AddressAlignedBeats_Enable;\r
+ ETH_InitStruct->ETH_FixedBurst = ETH_FixedBurst_Disable;\r
+ ETH_InitStruct->ETH_RxDMABurstLength = ETH_RxDMABurstLength_1Beat;\r
+ ETH_InitStruct->ETH_TxDMABurstLength = ETH_TxDMABurstLength_1Beat;\r
+ ETH_InitStruct->ETH_DescriptorSkipLength = 0x0;\r
+ ETH_InitStruct->ETH_DMAArbitration = ETH_DMAArbitration_RoundRobin_RxTx_1_1;\r
+\r
+#endif /* _ETH_DMA */\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : ETH_Start\r
+* Desciption : Enables ENET MAC and DMA reception/transmission\r
+* Input : None\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void ETH_Start(void)\r
+{\r
+ /* Enable transmit state machine of the MAC for transmission on the MII */\r
+ ETH_MACTransmissionCmd(ENABLE);\r
+ /* Flush Transmit FIFO */\r
+ ETH_FlushTransmitFIFO();\r
+ /* Enable receive state machine of the MAC for reception from the MII */\r
+ ETH_MACReceptionCmd(ENABLE);\r
+\r
+#ifdef _ETH_DMA\r
+ /* Start DMA transmission */\r
+ ETH_DMATransmissionCmd(ENABLE);\r
+ /* Start DMA reception */\r
+ ETH_DMAReceptionCmd(ENABLE);\r
+#endif /* _ETH_DMA */\r
+}\r
+\r
+#ifdef _ETH_DMA\r
+/*******************************************************************************\r
+* Function Name : ETH_HandleTxPkt\r
+* Desciption : Transmits a packet, from application buffer, pointed by ppkt.\r
+* Input : - ppkt: pointer to application packet Buffer.\r
+* - FrameLength: Tx Packet size.\r
+* Output : None\r
+* Return : ETH_ERROR: in case of Tx desc owned by DMA\r
+* ETH_SUCCESS: for correct transmission\r
+*******************************************************************************/\r
+u32 ETH_HandleTxPkt(u32 addr, u16 FrameLength)\r
+{\r
+\r
+ // Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset)\r
+ if((DMATxDescToSet->Status & ETH_DMATxDesc_OWN) != (u32)RESET)\r
+ {\r
+ // Return ERROR: OWN bit set\r
+ return ETH_ERROR;\r
+ }\r
+\r
+ //Set the DMA buffer address to send to the Packet we received from stack\r
+ DMATxDescToSet->Buffer1Addr = (u32)addr;\r
+\r
+ // Setting the Frame Length: bits[12:0]\r
+ DMATxDescToSet->ControlBufferSize = (FrameLength & ETH_DMATxDesc_TBS1);\r
+\r
+ // Setting the last segment and first segment bits (in this case a frame is transmitted in one descriptor)\r
+ DMATxDescToSet->Status |= ETH_DMATxDesc_LS | ETH_DMATxDesc_FS;\r
+\r
+ // Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA\r
+ DMATxDescToSet->Status |= ETH_DMATxDesc_OWN;\r
+\r
+ // When Tx Buffer unavailable flag is set: clear it and resume transmission\r
+ if ((ETH_DMA->DMASR & ETH_DMASR_TBUS) != (u32)RESET)\r
+ {\r
+ // Clear TBUS ETHERNET DMA flag\r
+ ETH_DMA->DMASR = ETH_DMASR_TBUS;\r
+ // Resume DMA transmission\r
+ ETH_DMA->DMATPDR = 0;\r
+ }\r
+\r
+ // Update the ETHERNET DMA global Tx descriptor with next Tx decriptor\r
+ // Chained Mode\r
+ if((DMATxDescToSet->Status & ETH_DMATxDesc_TCH) != (u32)RESET)\r
+ {\r
+ // Selects the next DMA Tx descriptor list for next buffer to send\r
+ DMATxDescToSet = (ETH_DMADESCTypeDef*) (DMATxDescToSet->Buffer2NextDescAddr);\r
+ }\r
+ else // Ring Mode\r
+ {\r
+ if((DMATxDescToSet->Status & ETH_DMATxDesc_TER) != (u32)RESET)\r
+ {\r
+ // Selects the first DMA Tx descriptor for next buffer to send: last Tx descriptor was used\r
+ DMATxDescToSet = (ETH_DMADESCTypeDef*) (ETH_DMA->DMATDLAR);\r
+ }\r
+ else\r
+ {\r
+ // Selects the next DMA Tx descriptor list for next buffer to send\r
+ DMATxDescToSet = (ETH_DMADESCTypeDef*) ((u32)DMATxDescToSet + 0x10 + ((ETH_DMA->DMABMR & ETH_DMABMR_DSL) >> 2));\r
+ }\r
+ }\r
+\r
+\r
+ // Return SUCCESS\r
+ return ETH_SUCCESS;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : ETH_HandleRxPkt\r
+* Desciption : Receives a packet and copies it to memory pointed by ppkt.\r
+* Input : None\r
+* Output : ppkt: pointer on application receive buffer.\r
+* Return : ETH_ERROR: if there is error in reception\r
+* Received packet size: if packet reception is correct\r
+*******************************************************************************/\r
+u32 ETH_HandleRxPkt(u32 addr)\r
+{\r
+ // Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset)\r
+ if((DMARxDescToGet->Status & ETH_DMARxDesc_OWN) != (u32)RESET)\r
+ {\r
+ // Return error: OWN bit set\r
+ return ETH_ERROR;\r
+ }\r
+\r
+ //Set the buffer address to rcv frame for the same descriptor (reserved packet)\r
+ DMARxDescToGet->Buffer1Addr = addr;\r
+\r
+ if(addr) {\r
+ // Set Own bit of the Rx descriptor Status: gives the buffer back to ETHERNET DMA\r
+ DMARxDescToGet->Status = ETH_DMARxDesc_OWN;\r
+ }\r
+\r
+ // Update the ETHERNET DMA global Rx descriptor with next Rx decriptor\r
+ // Chained Mode\r
+ if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RCH) != (u32)RESET)\r
+ {\r
+ // Selects the next DMA Rx descriptor list for next buffer to read\r
+ DMARxDescToGet = (ETH_DMADESCTypeDef*) (DMARxDescToGet->Buffer2NextDescAddr);\r
+ }\r
+ else // Ring Mode\r
+ {\r
+ if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RER) != (u32)RESET)\r
+ {\r
+ // Selects the first DMA Rx descriptor for next buffer to read: last Rx descriptor was used\r
+ DMARxDescToGet = (ETH_DMADESCTypeDef*) (ETH_DMA->DMARDLAR);\r
+ }\r
+ else\r
+ {\r
+ // Selects the next DMA Rx descriptor list for next buffer to read\r
+ DMARxDescToGet = (ETH_DMADESCTypeDef*) ((u32)DMARxDescToGet + 0x10 + ((ETH_DMA->DMABMR & ETH_DMABMR_DSL) >> 2));\r
+ }\r
+ }\r
+\r
+ return(1);\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name : ETH_GetRxPktSize\r
+* Desciption : Get the size of received the received packet.\r
+* Input : None\r
+* Output : None\r
+* Return : Rx packet size\r
+*******************************************************************************/\r
+u32 ETH_GetRxPktSize(void)\r
+{\r
+ u32 FrameLength = 0;\r
+\r
+ //Test DMARxDescToGet is not NULL\r
+ if(DMARxDescToGet)\r
+ {\r
+ /* Get the size of the packet: including 4 bytes of the CRC */\r
+ FrameLength = ETH_GetDMARxDescFrameLength(DMARxDescToGet);\r
+\r
+ }\r
+\r
+ /* Return Frame Length */\r
+ return FrameLength;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : ETH_DropRxPkt\r
+* Desciption : Drop a Received packet (too small packet, etc...)\r
+* Input : None\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void ETH_DropRxPkt(void)\r
+{\r
+\r
+ // Set Own bit of the Rx descriptor Status: gives the buffer back to ETHERNET DMA\r
+ DMARxDescToGet->Status = ETH_DMARxDesc_OWN;\r
+\r
+\r
+ // Chained Mode\r
+ if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RCH) != (u32)RESET)\r
+ {\r
+ // Selects the next DMA Rx descriptor list for next buffer read\r
+ DMARxDescToGet = (ETH_DMADESCTypeDef*) (DMARxDescToGet->Buffer2NextDescAddr);\r
+ }\r
+ else // Ring Mode\r
+ {\r
+ if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RER) != (u32)RESET)\r
+ {\r
+ // Selects the next DMA Rx descriptor list for next buffer read: this will\r
+ // be the first Rx descriptor in this case\r
+ DMARxDescToGet = (ETH_DMADESCTypeDef*) (ETH_DMA->DMARDLAR);\r
+ }\r
+ else\r
+ {\r
+ // Selects the next DMA Rx descriptor list for next buffer read\r
+ DMARxDescToGet = (ETH_DMADESCTypeDef*) ((u32)DMARxDescToGet + 0x10 + ((ETH_DMA->DMABMR & ETH_DMABMR_DSL) >> 2));\r
+ }\r
+ }\r
+}\r
+\r
+#endif /* _ETH_DMA */\r
+/*--------------------------------- PHY ------------------------------------*/\r
+\r
+/*******************************************************************************\r
+* Function Name : ETH_ReadPHYRegister\r
+* Desciption : Read a PHY register\r
+* Input : - PHYAddress: PHY device address, is the index of one of supported\r
+* 32 PHY devices.\r
+* This parameter can be one of the following values: 0,..,31\r
+* - PHYReg: PHY register address, is the index of one of the 32\r
+* PHY register.\r
+* This parameter can be one of the following values:\r
+* - PHY_BCR : Tranceiver Basic Control Register\r
+* - PHY_BSR : Tranceiver Basic Status Register\r
+* - PHY_SR : Tranceiver Status Register\r
+* - More PHY register could be read depending on the used PHY\r
+* Output : None\r
+* Return : ETH_ERROR: in case of timeout\r
+* Data read from the selected PHY register: for correct read\r
+*******************************************************************************/\r
+u16 ETH_ReadPHYRegister(u16 PHYAddress, u16 PHYReg)\r
+{\r
+ u32 tmpreg = 0;\r
+ u32 timeout = 0;\r
+\r
+ /* Check the parameters */\r
+ eth_assert_param(IS_ETH_PHY_ADDRESS(PHYAddress));\r
+ eth_assert_param(IS_ETH_PHY_REG(PHYReg));\r
+\r
+ /* Get the ETHERNET MACMIIAR value */\r
+ tmpreg = ETH_MAC->MACMIIAR;\r
+ /* Keep only the CSR Clock Range CR[2:0] bits value */\r
+ tmpreg &= ~MACMIIAR_CR_Mask;\r
+\r
+ /* Prepare the MII address register value */\r
+ tmpreg |=(((u32)PHYAddress<<11) & ETH_MACMIIAR_PA); /* Set the PHY device address */\r
+ tmpreg |=(((u32)PHYReg<<6) & ETH_MACMIIAR_MR); /* Set the PHY register address */\r
+ tmpreg &= ~ETH_MACMIIAR_MW; /* Set the read mode */\r
+ tmpreg |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */\r
+\r
+ /* Write the result value into the MII Address register */\r
+ ETH_MAC->MACMIIAR = tmpreg;\r
+\r
+ /* Check for the Busy flag */\r
+ do\r
+ {\r
+ timeout++;\r
+ tmpreg = ETH_MAC->MACMIIAR;\r
+ } while ((tmpreg & ETH_MACMIIAR_MB) && (timeout < (u32)PHY_READ_TO));\r
+\r
+ /* Return ERROR in case of timeout */\r
+ if(timeout == PHY_READ_TO)\r
+ {\r
+ return (u16)ETH_ERROR;\r
+ }\r
+\r
+ /* Return data register value */\r
+ return (u16)(ETH_MAC->MACMIIDR);\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : ETH_WritePHYRegister\r
+* Desciption : Write to a PHY register\r
+* Input : - PHYAddress: PHY device address, is the index of one of supported\r
+* 32 PHY devices.\r
+* This parameter can be one of the following values: 0,..,31\r
+* - PHYReg: PHY register address, is the index of one of the 32\r
+* PHY register.\r
+* This parameter can be one of the following values:\r
+* - PHY_BCR : Tranceiver Control Register\r
+* - More PHY register could be written depending on the used PHY\r
+* - PHYValue: the value to write\r
+* Output : None\r
+* Return : ETH_ERROR: in case of timeout\r
+* ETH_SUCCESS: for correct read\r
+*******************************************************************************/\r
+u32 ETH_WritePHYRegister(u16 PHYAddress, u16 PHYReg, u16 PHYValue)\r
+{\r
+ u32 tmpreg = 0;\r
+ u32 timeout = 0;\r
+\r
+ /* Check the parameters */\r
+ eth_assert_param(IS_ETH_PHY_ADDRESS(PHYAddress));\r
+ eth_assert_param(IS_ETH_PHY_REG(PHYReg));\r
+\r
+ /* Get the ETHERNET MACMIIAR value */\r
+ tmpreg = ETH_MAC->MACMIIAR;\r
+ /* Keep only the CSR Clock Range CR[2:0] bits value */\r
+ tmpreg &= ~MACMIIAR_CR_Mask;\r
+\r
+ /* Prepare the MII register address value */\r
+ tmpreg |=(((u32)PHYAddress<<11) & ETH_MACMIIAR_PA); /* Set the PHY device address */\r
+ tmpreg |=(((u32)PHYReg<<6) & ETH_MACMIIAR_MR); /* Set the PHY register address */\r
+ tmpreg |= ETH_MACMIIAR_MW; /* Set the write mode */\r
+ tmpreg |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */\r
+\r
+ /* Give the value to the MII data register */\r
+ ETH_MAC->MACMIIDR = PHYValue;\r
+\r
+ /* Write the result value into the MII Address register */\r
+ ETH_MAC->MACMIIAR = tmpreg;\r
+\r
+ /* Check for the Busy flag */\r
+ do\r
+ {\r
+ timeout++;\r
+ tmpreg = ETH_MAC->MACMIIAR;\r
+ } while ((tmpreg & ETH_MACMIIAR_MB) && (timeout < (u32)PHY_WRITE_TO));\r
+\r
+ /* Return ERROR in case of timeout */\r
+ if(timeout == PHY_WRITE_TO)\r
+ {\r
+ return ETH_ERROR;\r
+ }\r
+\r
+ /* Return SUCCESS */\r
+ return ETH_SUCCESS;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : ETH_PHYLoopBackCmd\r
+* Desciption : Enables or disables the PHY loopBack mode.\r
+* Input : - PHYAddress: PHY device address, is the index of one of supported\r
+* 32 PHY devices.\r
+* This parameter can be one of the following values:\r
+* - NewState: new state of the PHY loopBack mode.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Note: Don't be confused with ETH_MACLoopBackCmd function\r
+* which enables internal loopback at MII level\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+u32 ETH_PHYLoopBackCmd(u16 PHYAddress, FunctionalState NewState)\r
+{\r
+ u16 tmpreg = 0;\r
+\r
+ /* Check the parameters */\r
+ eth_assert_param(IS_ETH_PHY_ADDRESS(PHYAddress));\r
+ eth_assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ /* Get the PHY configuration to update it */\r
+ tmpreg = ETH_ReadPHYRegister(PHYAddress, PHY_BCR);\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the PHY loopback mode */\r
+ tmpreg |= PHY_Loopback;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the PHY loopback mode: normal mode */\r
+ tmpreg &= (u16)(~(u16)PHY_Loopback);\r
+ }\r
+\r
+ /* Update the PHY control register with the new configuration */\r
+ if(ETH_WritePHYRegister(PHYAddress, PHY_BCR, tmpreg) != (u32)RESET)\r
+ {\r
+ return ETH_SUCCESS;\r
+ }\r
+ else\r
+ {\r
+ /* Return SUCCESS */\r
+ return ETH_ERROR;\r
+ }\r
+}\r
+\r
+/*--------------------------------- MAC ------------------------------------*/\r
+\r
+/*******************************************************************************\r
+* Function Name : ETH_MACTransmissionCmd\r
+* Desciption : Enables or disables the MAC transmission.\r
+* Input : - NewState: new state of the MAC transmission.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void ETH_MACTransmissionCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ eth_assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the MAC transmission */\r
+ ETH_MAC->MACCR |= ETH_MACCR_TE;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the MAC transmission */\r
+ ETH_MAC->MACCR &= ~ETH_MACCR_TE;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : ETH_MACReceptionCmd\r
+* Desciption : Enables or disables the MAC reception.\r
+* Input : - NewState: new state of the MAC reception.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void ETH_MACReceptionCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ eth_assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the MAC reception */\r
+ ETH_MAC->MACCR |= ETH_MACCR_RE;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the MAC reception */\r
+ ETH_MAC->MACCR &= ~ETH_MACCR_RE;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : ETH_GetFlowControlBusyStatus\r
+* Desciption : Checks whether the ETHERNET flow control busy bit is set or not.\r
+* Input : None\r
+* Output : None\r
+* Return : The new state of flow control busy status bit (SET or RESET).\r
+*******************************************************************************/\r
+FlagStatus ETH_GetFlowControlBusyStatus(void)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+\r
+ /* The Flow Control register should not be written to until this bit is cleared */\r
+ if ((ETH_MAC->MACFCR & ETH_MACFCR_FCBBPA) != (u32)RESET)\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ return bitstatus;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : ETH_InitiatePauseControlFrame\r
+* Desciption : Initiate a Pause Control Frame (Full-duplex only).\r
+* Input : None\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void ETH_InitiatePauseControlFrame(void)\r
+{\r
+ /* When Set In full duplex MAC initiates pause control frame */\r
+ ETH_MAC->MACFCR |= ETH_MACFCR_FCBBPA;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : ETH_BackPressureActivationCmd\r
+* Desciption : Enables or disables the MAC BackPressure operation activation (Half-duplex only).\r
+* Input : - NewState: new state of the MAC BackPressure operation activation.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void ETH_BackPressureActivationCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ eth_assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Activate the MAC BackPressure operation */\r
+ /* In Half duplex: during backpressure, when the MAC receives a new frame,\r
+ the transmitter starts sending a JAM pattern resulting in a collision */\r
+ ETH_MAC->MACFCR |= ETH_MACFCR_FCBBPA;\r
+ }\r
+ else\r
+ {\r
+ /* Desactivate the MAC BackPressure operation */\r
+ ETH_MAC->MACFCR &= ~ETH_MACFCR_FCBBPA;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : ETH_GetMACFlagStatus\r
+* Desciption : Checks whether the specified ETHERNET MAC flag is set or not.\r
+* Input : - ETH_MAC_FLAG: specifies the flag to check.\r
+* This parameter can be one of the following values:\r
+* - ETH_MAC_FLAG_TST : Time stamp trigger flag\r
+* - ETH_MAC_FLAG_MMCT : MMC transmit flag\r
+* - ETH_MAC_FLAG_MMCR : MMC receive flag\r
+* - ETH_MAC_FLAG_MMC : MMC flag\r
+* - ETH_MAC_FLAG_PMT : PMT flag\r
+* Output : None\r
+* Return : The new state of ETHERNET MAC flag (SET or RESET).\r
+*******************************************************************************/\r
+FlagStatus ETH_GetMACFlagStatus(u32 ETH_MAC_FLAG)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+\r
+ /* Check the parameters */\r
+ eth_assert_param(IS_ETH_MAC_GET_FLAG(ETH_MAC_FLAG));\r
+\r
+ if ((ETH_MAC->MACSR & ETH_MAC_FLAG) != (u32)RESET)\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ return bitstatus;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : ETH_GetMACITStatus\r
+* Desciption : Checks whether the specified ETHERNET MAC interrupt has occurred or not.\r
+* Input : - ETH_MAC_IT: specifies the interrupt source to check.\r
+* This parameter can be one of the following values:\r
+* - ETH_MAC_IT_TST : Time stamp trigger interrupt\r
+* - ETH_MAC_IT_MMCT : MMC transmit interrupt\r
+* - ETH_MAC_IT_MMCR : MMC receive interrupt\r
+* - ETH_MAC_IT_MMC : MMC interrupt\r
+* - ETH_MAC_IT_PMT : PMT interrupt\r
+* Output : None\r
+* Return : The new state of ETHERNET MAC interrupt (SET or RESET).\r
+*******************************************************************************/\r
+ITStatus ETH_GetMACITStatus(u32 ETH_MAC_IT)\r
+{\r
+ ITStatus bitstatus = RESET;\r
+\r
+ /* Check the parameters */\r
+ eth_assert_param(IS_ETH_MAC_GET_IT(ETH_MAC_IT));\r
+\r
+ if ((ETH_MAC->MACSR & ETH_MAC_IT) != (u32)RESET)\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ return bitstatus;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : ETH_MACITConfig\r
+* Desciption : Enables or disables the specified ETHERNET MAC interrupts.\r
+* Input : - ETH_MAC_IT: specifies the ETHERNET MAC interrupt sources to be\r
+* enabled or disabled.\r
+* This parameter can be any combination of the following values:\r
+* - ETH_MAC_IT_TST : Time stamp trigger interrupt\r
+* - ETH_MAC_IT_PMT : PMT interrupt\r
+* - NewState: new state of the specified ETHERNET MAC interrupts.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void ETH_MACITConfig(u32 ETH_MAC_IT, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ eth_assert_param(IS_ETH_MAC_IT(ETH_MAC_IT));\r
+ eth_assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected ETHERNET MAC interrupts */\r
+ ETH_MAC->MACIMR &= (~(u32)ETH_MAC_IT);\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected ETHERNET MAC interrupts */\r
+ ETH_MAC->MACIMR |= ETH_MAC_IT;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : ETH_MACAddressConfig\r
+* Desciption : Configures the selected MAC address.\r
+* Input : - MacAddr: The MAC addres to configure.\r
+* This parameter can be one of the following values:\r
+* - ETH_MAC_Address0 : MAC Address0\r
+* - ETH_MAC_Address1 : MAC Address1\r
+* - ETH_MAC_Address2 : MAC Address2\r
+* - ETH_MAC_Address3 : MAC Address3\r
+* - Addr: Pointer on MAC address buffer data (6 bytes).\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void ETH_MACAddressConfig(u32 MacAddr, u8 *Addr)\r
+{\r
+ u32 tmpreg;\r
+\r
+ /* Check the parameters */\r
+ eth_assert_param(IS_ETH_MAC_ADDRESS0123(MacAddr));\r
+\r
+ /* Calculate the selectecd MAC address high register */\r
+ tmpreg = ((u32)Addr[5] << 8) | (u32)Addr[4];\r
+\r
+ /* Load the selectecd MAC address high register */\r
+ (*(vu32 *) (ETH_MAC_AddrHighBase + MacAddr)) = tmpreg;\r
+\r
+ /* Calculate the selectecd MAC address low register */\r
+ tmpreg = ((u32)Addr[3] << 24) | ((u32)Addr[2] << 16) | ((u32)Addr[1] << 8) | Addr[0];\r
+\r
+ /* Load the selectecd MAC address low register */\r
+ (*(vu32 *) (ETH_MAC_AddrLowBase + MacAddr)) = tmpreg;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : ETH_GetMACAddress\r
+* Desciption : Get the selected MAC address.\r
+* Input : - MacAddr: The MAC addres to return.\r
+* This parameter can be one of the following values:\r
+* - ETH_MAC_Address0 : MAC Address0\r
+* - ETH_MAC_Address1 : MAC Address1\r
+* - ETH_MAC_Address2 : MAC Address2\r
+* - ETH_MAC_Address3 : MAC Address3\r
+* - Addr: Pointer on MAC address buffer data (6 bytes).\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void ETH_GetMACAddress(u32 MacAddr, u8 *Addr)\r
+{\r
+ u32 tmpreg;\r
+\r
+ /* Check the parameters */\r
+ eth_assert_param(IS_ETH_MAC_ADDRESS0123(MacAddr));\r
+\r
+ /* Get the selectecd MAC address high register */\r
+ tmpreg =(*(vu32 *) (ETH_MAC_AddrHighBase + MacAddr));\r
+\r
+ /* Calculate the selectecd MAC address buffer */\r
+ Addr[5] = ((tmpreg >> 8) & (u8)0xFF);\r
+ Addr[4] = (tmpreg & (u8)0xFF);\r
+\r
+ /* Load the selectecd MAC address low register */\r
+ tmpreg =(*(vu32 *) (ETH_MAC_AddrLowBase + MacAddr));\r
+\r
+ /* Calculate the selectecd MAC address buffer */\r
+ Addr[3] = ((tmpreg >> 24) & (u8)0xFF);\r
+ Addr[2] = ((tmpreg >> 16) & (u8)0xFF);\r
+ Addr[1] = ((tmpreg >> 8 ) & (u8)0xFF);\r
+ Addr[0] = (tmpreg & (u8)0xFF);\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : ETH_MACAddressPerfectFilterCmd\r
+* Desciption : Enables or disables the Address filter module uses the specified\r
+* ETHERNET MAC address for perfect filtering\r
+* Input : - MacAddr: specifies the ETHERNET MAC address to be used for prfect filtering.\r
+* This parameter can be one of the following values:\r
+* - ETH_MAC_Address1 : MAC Address1\r
+* - ETH_MAC_Address2 : MAC Address2\r
+* - ETH_MAC_Address3 : MAC Address3\r
+* - NewState: new state of the specified ETHERNET MAC address use.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void ETH_MACAddressPerfectFilterCmd(u32 MacAddr, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ eth_assert_param(IS_ETH_MAC_ADDRESS123(MacAddr));\r
+ eth_assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected ETHERNET MAC address for perfect filtering */\r
+ (*(vu32 *) (ETH_MAC_AddrHighBase + MacAddr)) |= ETH_MACA1HR_AE;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected ETHERNET MAC address for perfect filtering */\r
+ (*(vu32 *) (ETH_MAC_AddrHighBase + MacAddr)) &=(~(u32)ETH_MACA1HR_AE);\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : ETH_MACAddressFilterConfig\r
+* Desciption : Set the filter type for the specified ETHERNET MAC address\r
+* Input : - MacAddr: specifies the ETHERNET MAC address\r
+* This parameter can be one of the following values:\r
+* - ETH_MAC_Address1 : MAC Address1\r
+* - ETH_MAC_Address2 : MAC Address2\r
+* - ETH_MAC_Address3 : MAC Address3\r
+* - Filter: specifies the used frame received field for comparaison\r
+* This parameter can be one of the following values:\r
+* - ETH_MAC_AddressFilter_SA : MAC Address is used to compare\r
+* with the SA fields of the received frame.\r
+* - ETH_MAC_AddressFilter_DA : MAC Address is used to compare\r
+* with the DA fields of the received frame.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void ETH_MACAddressFilterConfig(u32 MacAddr, u32 Filter)\r
+{\r
+ /* Check the parameters */\r
+ eth_assert_param(IS_ETH_MAC_ADDRESS123(MacAddr));\r
+ eth_assert_param(IS_ETH_MAC_ADDRESS_FILTER(Filter));\r
+\r
+ if (Filter != ETH_MAC_AddressFilter_DA)\r
+ {\r
+ /* The selected ETHERNET MAC address is used to compare with the SA fields of the\r
+ received frame. */\r
+ (*(vu32 *) (ETH_MAC_AddrHighBase + MacAddr)) |= ETH_MACA1HR_SA;\r
+ }\r
+ else\r
+ {\r
+ /* The selected ETHERNET MAC address is used to compare with the DA fields of the\r
+ received frame. */\r
+ (*(vu32 *) (ETH_MAC_AddrHighBase + MacAddr)) &=(~(u32)ETH_MACA1HR_SA);\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : ETH_MACAddressMaskBytesFilterConfig\r
+* Desciption : Set the filter type for the specified ETHERNET MAC address\r
+* Input : - MacAddr: specifies the ETHERNET MAC address\r
+* This parameter can be one of the following values:\r
+* - ETH_MAC_Address1 : MAC Address1\r
+* - ETH_MAC_Address2 : MAC Address2\r
+* - ETH_MAC_Address3 : MAC Address3\r
+* - MaskByte: specifies the used address bytes for comparaison\r
+* This parameter can be any combination of the following values:\r
+* - ETH_MAC_AddressMask_Byte6 : Mask MAC Address high reg bits [15:8].\r
+* - ETH_MAC_AddressMask_Byte5 : Mask MAC Address high reg bits [7:0].\r
+* - ETH_MAC_AddressMask_Byte4 : Mask MAC Address low reg bits [31:24].\r
+* - ETH_MAC_AddressMask_Byte3 : Mask MAC Address low reg bits [23:16].\r
+* - ETH_MAC_AddressMask_Byte2 : Mask MAC Address low reg bits [15:8].\r
+* - ETH_MAC_AddressMask_Byte1 : Mask MAC Address low reg bits [7:0].\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void ETH_MACAddressMaskBytesFilterConfig(u32 MacAddr, u32 MaskByte)\r
+{\r
+ /* Check the parameters */\r
+ eth_assert_param(IS_ETH_MAC_ADDRESS123(MacAddr));\r
+ eth_assert_param(IS_ETH_MAC_ADDRESS_MASK(MaskByte));\r
+\r
+ /* Clear MBC bits in the selected MAC address high register */\r
+ (*(vu32 *) (ETH_MAC_AddrHighBase + MacAddr)) &=(~(u32)ETH_MACA1HR_MBC);\r
+\r
+ /* Set the selected Filetr mask bytes */\r
+ (*(vu32 *) (ETH_MAC_AddrHighBase + MacAddr)) |= MaskByte;\r
+}\r
+\r
+/*------------------------ DMA Tx/Rx Desciptors ----------------------------*/\r
+#ifdef _ETH_DMA\r
+/*******************************************************************************\r
+* Function Name : ETH_DMATxDescChainInit\r
+* Desciption : Initializes the DMA Tx descriptors in chain mode.\r
+* Input : - DMATxDescTab: Pointer on the first Tx desc list\r
+* - TxBuff: Pointer on the first TxBuffer list\r
+* - TxBuffCount: Number of the used Tx desc in the list\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void ETH_DMATxDescChainInit(ETH_DMADESCTypeDef *DMATxDescTab, u8* TxBuff, u32 TxBuffCount)\r
+{\r
+ u32 i = 0;\r
+ ETH_DMADESCTypeDef *DMATxDesc;\r
+\r
+ /* Set the DMATxDescToSet pointer with the first one of the DMATxDescTab list */\r
+ DMATxDescToSet = DMATxDescTab;\r
+\r
+ /* Fill each DMATxDesc descriptor with the right values */\r
+ for(i=0; i < TxBuffCount; i++)\r
+ {\r
+ /* Get the pointer on the ith member of the Tx Desc list */\r
+ DMATxDesc = DMATxDescTab + i;\r
+\r
+ /* Set Second Address Chained bit */\r
+ DMATxDesc->Status = ETH_DMATxDesc_TCH;\r
+\r
+ /* Set Buffer1 address pointer */\r
+ DMATxDesc->Buffer1Addr = (u32)*((u32*)TxBuff + i);\r
+\r
+ /* Initialize the next descriptor with the Next Desciptor Polling Enable */\r
+ if(i < (TxBuffCount-1))\r
+ {\r
+ /* Set next descriptor address register with next descriptor base address */\r
+ DMATxDesc->Buffer2NextDescAddr = (u32)(DMATxDescTab+i+1);\r
+ }\r
+ else\r
+ {\r
+ /* For last descriptor, set next descriptor address register equal to the first descriptor base address */\r
+ DMATxDesc->Buffer2NextDescAddr = (u32) DMATxDescTab;\r
+ }\r
+ }\r
+\r
+ /* Set Transmit Desciptor List Address Register */\r
+ ETH_DMA->DMATDLAR = (u32) DMATxDescTab;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : ETH_DMATxDescRingInit\r
+* Desciption : Initializes the DMA Tx descriptors in ring mode.\r
+* Input : - DMATxDescTab: Pointer on the first Tx desc list\r
+* - TxBuff1: Pointer on the first TxBuffer1 list\r
+* - TxBuff2: Pointer on the first TxBuffer2 list\r
+* - TxBuffCount: Number of the used Tx desc in the list\r
+* Note: see decriptor skip length defined in ETH_DMA_InitStruct\r
+ for the number of Words to skip between two unchained descriptors.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void ETH_DMATxDescRingInit(ETH_DMADESCTypeDef *DMATxDescTab, u8 *TxBuff1, u8 *TxBuff2, u32 TxBuffCount)\r
+{\r
+ u32 i = 0;\r
+ ETH_DMADESCTypeDef *DMATxDesc;\r
+\r
+ /* Set the DMATxDescToSet pointer with the first one of the DMATxDescTab list */\r
+ DMATxDescToSet = DMATxDescTab;\r
+\r
+ /* Fill each DMATxDesc descriptor with the right values */\r
+ for(i=0; i < TxBuffCount; i++)\r
+ {\r
+ /* Get the pointer on the ith member of the Tx Desc list */\r
+ DMATxDesc = DMATxDescTab + i;\r
+\r
+ /* Set Buffer1 address pointer */\r
+ DMATxDesc->Buffer1Addr = (u32)(&TxBuff1[i*ETH_MAX_PACKET_SIZE]);\r
+\r
+ /* Set Buffer2 address pointer */\r
+ DMATxDesc->Buffer2NextDescAddr = (u32)(&TxBuff2[i*ETH_MAX_PACKET_SIZE]);\r
+\r
+ /* Set Transmit End of Ring bit for last descriptor: The DMA returns to the base\r
+ address of the list, creating a Desciptor Ring */\r
+ if(i == (TxBuffCount-1))\r
+ {\r
+ /* Set Transmit End of Ring bit */\r
+ DMATxDesc->Status = ETH_DMATxDesc_TER;\r
+ }\r
+ }\r
+\r
+ /* Set Transmit Desciptor List Address Register */\r
+ ETH_DMA->DMATDLAR = (u32) DMATxDescTab;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : ETH_GetDMATxDescFlagStatus\r
+* Desciption : Checks whether the specified ETHERNET DMA Tx Desc flag is set or not.\r
+* Input : - DMATxDesc: pointer on a DMA Tx descriptor\r
+* - ETH_DMATxDescFlag: specifies the flag to check.\r
+* This parameter can be one of the following values:\r
+* - ETH_DMATxDesc_OWN : OWN bit: descriptor is owned by DMA engine\r
+* - ETH_DMATxDesc_IC : Interrupt on completetion\r
+* - ETH_DMATxDesc_LS : Last Segment\r
+* - ETH_DMATxDesc_FS : First Segment\r
+* - ETH_DMATxDesc_DC : Disable CRC\r
+* - ETH_DMATxDesc_DP : Disable Pad\r
+* - ETH_DMATxDesc_TTSE: Transmit Time Stamp Enable\r
+* - ETH_DMATxDesc_TER : Transmit End of Ring\r
+* - ETH_DMATxDesc_TCH : Second Address Chained\r
+* - ETH_DMATxDesc_TTSS: Tx Time Stamp Status\r
+* - ETH_DMATxDesc_IHE : IP Header Error\r
+* - ETH_DMATxDesc_ES : Error summary\r
+* - ETH_DMATxDesc_JT : Jabber Timeout\r
+* - ETH_DMATxDesc_FF : Frame Flushed: DMA/MTL flushed the frame due to SW flush\r
+* - ETH_DMATxDesc_PCE : Payload Checksum Error\r
+* - ETH_DMATxDesc_LCA : Loss of Carrier: carrier lost during tramsmission\r
+* - ETH_DMATxDesc_NC : No Carrier: no carrier signal from the tranceiver\r
+* - ETH_DMATxDesc_LCO : Late Collision: transmission aborted due to collision\r
+* - ETH_DMATxDesc_EC : Excessive Collision: transmission aborted after 16 collisions\r
+* - ETH_DMATxDesc_VF : VLAN Frame\r
+* - ETH_DMATxDesc_CC : Collision Count\r
+* - ETH_DMATxDesc_ED : Excessive Deferral\r
+* - ETH_DMATxDesc_UF : Underflow Error: late data arrival from the memory\r
+* - ETH_DMATxDesc_DB : Deferred Bit\r
+* Output : None\r
+* Return : The new state of ETH_DMATxDescFlag (SET or RESET).\r
+*******************************************************************************/\r
+FlagStatus ETH_GetDMATxDescFlagStatus(ETH_DMADESCTypeDef *DMATxDesc, u32 ETH_DMATxDescFlag)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+\r
+ /* Check the parameters */\r
+ eth_assert_param(IS_ETH_DMATxDESC_GET_FLAG(ETH_DMATxDescFlag));\r
+\r
+ if ((DMATxDesc->Status & ETH_DMATxDescFlag) != (u32)RESET)\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ return bitstatus;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : ETH_GetDMATxDescCollisionCount\r
+* Desciption : Returns the specified ETHERNET DMA Tx Desc collision count.\r
+* Input : - DMATxDesc: pointer on a DMA Tx descriptor\r
+* Output : None\r
+* Return : The Transmit descriptor collision counter value.\r
+*******************************************************************************/\r
+u32 ETH_GetDMATxDescCollisionCount(ETH_DMADESCTypeDef *DMATxDesc)\r
+{\r
+ /* Return the Receive descriptor frame length */\r
+ return ((DMATxDesc->Status & ETH_DMATxDesc_CC) >> ETH_DMATxDesc_CollisionCountShift);\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : ETH_SetDMATxDescOwnBit\r
+* Desciption : Set the specified DMA Tx Desc Own bit.\r
+* Input : - DMATxDesc: Pointer on a Tx desc\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void ETH_SetDMATxDescOwnBit(ETH_DMADESCTypeDef *DMATxDesc)\r
+{\r
+ /* Set the DMA Tx Desc Own bit */\r
+ DMATxDesc->Status |= ETH_DMATxDesc_OWN;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : ETH_DMATxDescTransmitITConfig\r
+* Desciption : Enables or disables the specified DMA Tx Desc Transmit interrupt.\r
+* Input : - DMATxDesc: Pointer on a Tx desc\r
+* - NewState: new state of the DMA Tx Desc transmit interrupt.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void ETH_DMATxDescTransmitITConfig(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ eth_assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the DMA Tx Desc Transmit interrupt */\r
+ DMATxDesc->Status |= ETH_DMATxDesc_IC;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the DMA Tx Desc Transmit interrupt */\r
+ DMATxDesc->Status &=(~(u32)ETH_DMATxDesc_IC);\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : ETH_DMATxDescFrameSegmentConfig\r
+* Desciption : Enables or disables the specified DMA Tx Desc Transmit interrupt.\r
+* Input : - DMATxDesc: Pointer on a Tx desc\r
+* - FrameSegment: specifies is the actual Tx desc contain last or first segment.\r
+* This parameter can be one of the following values:\r
+* - ETH_DMATxDesc_LastSegment : actual Tx desc contain last segment\r
+* - ETH_DMATxDesc_FirstSegment : actual Tx desc contain first segment\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void ETH_DMATxDescFrameSegmentConfig(ETH_DMADESCTypeDef *DMATxDesc, u32 DMATxDesc_FrameSegment)\r
+{\r
+ /* Check the parameters */\r
+ eth_assert_param(IS_ETH_DMA_TXDESC_SEGMENT(DMATxDesc_FrameSegment));\r
+\r
+ /* Selects the DMA Tx Desc Frame segment */\r
+ DMATxDesc->Status |= DMATxDesc_FrameSegment;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : ETH_DMATxDescChecksumInsertionConfig\r
+* Desciption : Selects the specified ETHERNET DMA Tx Desc Checksum Insertion.\r
+* Input : - DMATxDesc: pointer on a DMA Tx descriptor\r
+* - Checksum: specifies is the DMA Tx desc checksum insertion.\r
+* This parameter can be one of the following values:\r
+* - ETH_DMATxDesc_ChecksumByPass : Checksum bypass\r
+* - ETH_DMATxDesc_ChecksumIPV4Header : IPv4 header checksum\r
+* - ETH_DMATxDesc_ChecksumTCPUDPICMPSegment : TCP/UDP/ICMP checksum. Pseudo header checksum is assumed to be present\r
+* - ETH_DMATxDesc_ChecksumTCPUDPICMPFull : TCP/UDP/ICMP checksum fully in hardware including pseudo header\r
+* Output : None\r
+* Return : The Transmit descriptor collision.\r
+*******************************************************************************/\r
+void ETH_DMATxDescChecksumInsertionConfig(ETH_DMADESCTypeDef *DMATxDesc, u32 DMATxDesc_Checksum)\r
+{\r
+ /* Check the parameters */\r
+ eth_assert_param(IS_ETH_DMA_TXDESC_CHECKSUM(DMATxDesc_Checksum));\r
+\r
+ /* Set the selected DMA Tx desc checksum insertion control */\r
+ DMATxDesc->Status |= DMATxDesc_Checksum;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : ETH_DMATxDescCRCCmd\r
+* Desciption : Enables or disables the DMA Tx Desc CRC.\r
+* Input : - DMATxDesc: pointer on a DMA Tx descriptor\r
+* - NewState: new state of the specified DMA Tx Desc CRC.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void ETH_DMATxDescCRCCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ eth_assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected DMA Tx Desc CRC */\r
+ DMATxDesc->Status &= (~(u32)ETH_DMATxDesc_DC);\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected DMA Tx Desc CRC */\r
+ DMATxDesc->Status |= ETH_DMATxDesc_DC;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : ETH_DMATxDescEndOfRingCmd\r
+* Desciption : Enables or disables the DMA Tx Desc end of ring.\r
+* Input : - DMATxDesc: pointer on a DMA Tx descriptor\r
+* - NewState: new state of the specified DMA Tx Desc end of ring.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : NoneH\r
+* Return : None\r
+*******************************************************************************/\r
+void ETH_DMATxDescEndOfRingCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ eth_assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected DMA Tx Desc end of ring */\r
+ DMATxDesc->Status |= ETH_DMATxDesc_TER;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected DMA Tx Desc end of ring */\r
+ DMATxDesc->Status &= (~(u32)ETH_DMATxDesc_TER);\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : ETH_DMATxDescSecondAddressChainedCmd\r
+* Desciption : Enables or disables the DMA Tx Desc second address chained.\r
+* Input : - DMATxDesc: pointer on a DMA Tx descriptor\r
+* - NewState: new state of the specified DMA Tx Desc second address chained.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void ETH_DMATxDescSecondAddressChainedCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ eth_assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected DMA Tx Desc second address chained */\r
+ DMATxDesc->Status |= ETH_DMATxDesc_TCH;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected DMA Tx Desc second address chained */\r
+ DMATxDesc->Status &=(~(u32)ETH_DMATxDesc_TCH);\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : ETH_DMATxDescShortFramePaddingCmd\r
+* Desciption : Enables or disables the DMA Tx Desc padding for frame shorter than 64 bytes.\r
+* Input : - DMATxDesc: pointer on a DMA Tx descriptor\r
+* - NewState: new state of the specified DMA Tx Desc padding for\r
+* frame shorter than 64 bytes.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void ETH_DMATxDescShortFramePaddingCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ eth_assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected DMA Tx Desc padding for frame shorter than 64 bytes */\r
+ DMATxDesc->Status &= (~(u32)ETH_DMATxDesc_DP);\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected DMA Tx Desc padding for frame shorter than 64 bytes*/\r
+ DMATxDesc->Status |= ETH_DMATxDesc_DP;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : ETH_DMATxDescTimeStampCmd\r
+* Desciption : Enables or disables the DMA Tx Desc time stamp.\r
+* Input : - DMATxDesc: pointer on a DMA Tx descriptor\r
+* - NewState: new state of the specified DMA Tx Desc time stamp.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void ETH_DMATxDescTimeStampCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ eth_assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected DMA Tx Desc time stamp */\r
+ DMATxDesc->Status |= ETH_DMATxDesc_TTSE;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected DMA Tx Desc time stamp */\r
+ DMATxDesc->Status &=(~(u32)ETH_DMATxDesc_TTSE);\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : ETH_DMATxDescBufferSizeConfig\r
+* Desciption : Configures the specified DMA Tx Desc buffer1 and buffer2 sizes.\r
+* Input : - DMATxDesc: Pointer on a Tx desc\r
+* - BufferSize1: specifies the Tx desc buffer1 size.\r
+* - BufferSize2: specifies the Tx desc buffer2 size (put "0" if not used).\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void ETH_DMATxDescBufferSizeConfig(ETH_DMADESCTypeDef *DMATxDesc, u32 BufferSize1, u32 BufferSize2)\r
+{\r
+ /* Check the parameters */\r
+ eth_assert_param(IS_ETH_DMATxDESC_BUFFER_SIZE(BufferSize1));\r
+ eth_assert_param(IS_ETH_DMATxDESC_BUFFER_SIZE(BufferSize2));\r
+\r
+ /* Set the DMA Tx Desc buffer1 and buffer2 sizes values */\r
+ DMATxDesc->ControlBufferSize |= (BufferSize1 | (BufferSize2 << ETH_DMATxDesc_BufferSize2Shift));\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : ETH_DMARxDescChainInit\r
+* Desciption : Initializes the DMA Rx descriptors in chain mode.\r
+* Input : - DMARxDescTab: Pointer on the first Rx desc list\r
+* - RxBuff: Pointer on the first RxBuffer list\r
+* - RxBuffCount: Number of the used Rx desc in the list\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void ETH_DMARxDescChainInit(ETH_DMADESCTypeDef *DMARxDescTab, u8 *RxBuff, u32 RxBuffCount)\r
+{\r
+ u32 i = 0;\r
+ ETH_DMADESCTypeDef *DMARxDesc;\r
+\r
+ /* Set the DMARxDescToGet pointer with the first one of the DMARxDescTab list */\r
+ DMARxDescToGet = DMARxDescTab;\r
+\r
+ /* Fill each DMARxDesc descriptor with the right values */\r
+ for(i=0; i < RxBuffCount; i++)\r
+ {\r
+ /* Get the pointer on the ith member of the Rx Desc list */\r
+ DMARxDesc = DMARxDescTab+i;\r
+\r
+ /* Set Own bit of the Rx descriptor Status */\r
+ DMARxDesc->Status = ETH_DMARxDesc_OWN;\r
+// DMARxDesc->Status = 0;\r
+\r
+ /* Set Buffer1 size and Second Address Chained bit */\r
+ DMARxDesc->ControlBufferSize = ETH_DMARxDesc_RCH | (u32)ETH_MAX_PACKET_SIZE;\r
+\r
+ /* Set Buffer1 address pointer */\r
+ DMARxDesc->Buffer1Addr = (u32)*((u32*)RxBuff + i);\r
+\r
+ /* Initialize the next descriptor with the Next Desciptor Polling Enable */\r
+ if(i < (RxBuffCount-1))\r
+ {\r
+ /* Set next descriptor address register with next descriptor base address */\r
+ DMARxDesc->Buffer2NextDescAddr = (u32)(DMARxDescTab+i+1);\r
+ }\r
+ else\r
+ {\r
+ /* For last descriptor, set next descriptor address register equal to the first descriptor base address */\r
+ DMARxDesc->Buffer2NextDescAddr = (u32)(DMARxDescTab);\r
+ }\r
+ }\r
+\r
+ /* Set Receive Desciptor List Address Register */\r
+ ETH_DMA->DMARDLAR = (u32) DMARxDescTab;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : ETH_DMARxDescRingInit\r
+* Desciption : Initializes the DMA Rx descriptors in ring mode.\r
+* Input : - DMARxDescTab: Pointer on the first Rx desc list\r
+* - RxBuff1: Pointer on the first RxBuffer1 list\r
+* - RxBuff2: Pointer on the first RxBuffer2 list\r
+* - RxBuffCount: Number of the used Rx desc in the list\r
+* Note: see decriptor skip length defined in ETH_DMA_InitStruct\r
+ for the number of Words to skip between two unchained descriptors.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void ETH_DMARxDescRingInit(ETH_DMADESCTypeDef *DMARxDescTab, u8 *RxBuff1, u8 *RxBuff2, u32 RxBuffCount)\r
+{\r
+ u32 i = 0;\r
+ ETH_DMADESCTypeDef *DMARxDesc;\r
+\r
+ /* Set the DMARxDescToGet pointer with the first one of the DMARxDescTab list */\r
+ DMARxDescToGet = DMARxDescTab;\r
+\r
+ /* Fill each DMARxDesc descriptor with the right values */\r
+ for(i=0; i < RxBuffCount; i++)\r
+ {\r
+ /* Get the pointer on the ith member of the Rx Desc list */\r
+ DMARxDesc = DMARxDescTab+i;\r
+\r
+ /* Set Own bit of the Rx descriptor Status */\r
+ DMARxDesc->Status = ETH_DMARxDesc_OWN;\r
+\r
+ /* Set Buffer1 size */\r
+ DMARxDesc->ControlBufferSize = ETH_MAX_PACKET_SIZE;\r
+\r
+ /* Set Buffer1 address pointer */\r
+ DMARxDesc->Buffer1Addr = (u32)(&RxBuff1[i*ETH_MAX_PACKET_SIZE]);\r
+\r
+ /* Set Buffer2 address pointer */\r
+ DMARxDesc->Buffer2NextDescAddr = (u32)(&RxBuff2[i*ETH_MAX_PACKET_SIZE]);\r
+\r
+ /* Set Receive End of Ring bit for last descriptor: The DMA returns to the base\r
+ address of the list, creating a Desciptor Ring */\r
+ if(i == (RxBuffCount-1))\r
+ {\r
+ /* Set Receive End of Ring bit */\r
+ DMARxDesc->ControlBufferSize |= ETH_DMARxDesc_RER;\r
+ }\r
+ }\r
+\r
+ /* Set Receive Desciptor List Address Register */\r
+ ETH_DMA->DMARDLAR = (u32) DMARxDescTab;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : ETH_GetDMARxDescFlagStatus\r
+* Desciption : Checks whether the specified ETHERNET Rx Desc flag is set or not.\r
+* Input : - DMARxDesc: pointer on a DMA Rx descriptor\r
+* - ETH_DMARxDescFlag: specifies the flag to check.\r
+* This parameter can be one of the following values:\r
+* - ETH_DMARxDesc_OWN: OWN bit: descriptor is owned by DMA engine\r
+* - ETH_DMARxDesc_AFM: DA Filter Fail for the rx frame\r
+* - ETH_DMARxDesc_ES: Error summary\r
+* - ETH_DMARxDesc_DE: Desciptor error: no more descriptors for receive frame\r
+* - ETH_DMARxDesc_SAF: SA Filter Fail for the received frame\r
+* - ETH_DMARxDesc_LE: Frame size not matching with length field\r
+* - ETH_DMARxDesc_OE: Overflow Error: Frame was damaged due to buffer overflow\r
+* - ETH_DMARxDesc_VLAN: VLAN Tag: received frame is a VLAN frame\r
+* - ETH_DMARxDesc_FS: First descriptor of the frame\r
+* - ETH_DMARxDesc_LS: Last descriptor of the frame\r
+* - ETH_DMARxDesc_IPV4HCE: IPC Checksum Error/Giant Frame: Rx Ipv4 header checksum error\r
+* - ETH_DMARxDesc_RxLongFrame: (Giant Frame)Rx - frame is longer than 1518/1522\r
+* - ETH_DMARxDesc_LC: Late collision occurred during reception\r
+* - ETH_DMARxDesc_FT: Frame type - Ethernet, otherwise 802.3\r
+* - ETH_DMARxDesc_RWT: Receive Watchdog Timeout: watchdog timer expired during reception\r
+* - ETH_DMARxDesc_RE: Receive error: error reported by MII interface\r
+* - ETH_DMARxDesc_DE: Dribble bit error: frame contains non int multiple of 8 bits\r
+* - ETH_DMARxDesc_CE: CRC error\r
+* - ETH_DMARxDesc_MAMPCE: Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error\r
+* Output : None\r
+* Return : The new state of ETH_DMARxDescFlag (SET or RESET).\r
+*******************************************************************************/\r
+FlagStatus ETH_GetDMARxDescFlagStatus(ETH_DMADESCTypeDef *DMARxDesc, u32 ETH_DMARxDescFlag)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+\r
+ /* Check the parameters */\r
+ eth_assert_param(IS_ETH_DMARxDESC_GET_FLAG(ETH_DMARxDescFlag));\r
+\r
+ if ((DMARxDesc->Status & ETH_DMARxDescFlag) != (u32)RESET)\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ return bitstatus;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : ETH_SetDMARxDescOwnBit\r
+* Desciption : Set the specified DMA Rx Desc Own bit.\r
+* Input : - DMARxDesc: Pointer on a Rx desc\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void ETH_SetDMARxDescOwnBit(ETH_DMADESCTypeDef *DMARxDesc)\r
+{\r
+ /* Set the DMA Rx Desc Own bit */\r
+ DMARxDesc->Status |= ETH_DMARxDesc_OWN;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : ETH_GetDMARxDescFrameLength\r
+* Desciption : Returns the specified DMA Rx Desc frame length.\r
+* Input : - DMARxDesc: pointer on a DMA Rx descriptor\r
+* Output : None\r
+* Return : The Rx descriptor received frame length.\r
+*******************************************************************************/\r
+u32 ETH_GetDMARxDescFrameLength(ETH_DMADESCTypeDef *DMARxDesc)\r
+{\r
+ /* Return the Receive descriptor frame length */\r
+ return ((DMARxDesc->Status & ETH_DMARxDesc_FL) >> ETH_DMARxDesc_FrameLengthShift);\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : ETH_DMARxDescReceiveITConfig\r
+* Desciption : Enables or disables the specified DMA Rx Desc receive interrupt.\r
+* Input : - DMARxDesc: Pointer on a Rx desc\r
+* - NewState: new state of the specified DMA Rx Desc interrupt.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void ETH_DMARxDescReceiveITConfig(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ eth_assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the DMA Rx Desc receive interrupt */\r
+ DMARxDesc->ControlBufferSize &=(~(u32)ETH_DMARxDesc_DIC);\r
+ }\r
+ else\r
+ {\r
+ /* Disable the DMA Rx Desc receive interrupt */\r
+ DMARxDesc->ControlBufferSize |= ETH_DMARxDesc_DIC;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : ETH_DMARxDescEndOfRingCmd\r
+* Desciption : Enables or disables the DMA Rx Desc end of ring.\r
+* Input : - DMARxDesc: pointer on a DMA Rx descriptor\r
+* - NewState: new state of the specified DMA Rx Desc end of ring.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void ETH_DMARxDescEndOfRingCmd(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ eth_assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected DMA Rx Desc end of ring */\r
+ DMARxDesc->ControlBufferSize |= ETH_DMARxDesc_RER;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected DMA Rx Desc end of ring */\r
+ DMARxDesc->ControlBufferSize &=(~(u32)ETH_DMARxDesc_RER);\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : ETH_DMARxDescSecondAddressChainedCmd\r
+* Desciption : Enables or disables the DMA Rx Desc second address chained.\r
+* Input : - DMARxDesc: pointer on a DMA Rx descriptor\r
+* - NewState: new state of the specified DMA Rx Desc second address chained.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void ETH_DMARxDescSecondAddressChainedCmd(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ eth_assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected DMA Rx Desc second address chained */\r
+ DMARxDesc->ControlBufferSize |= ETH_DMARxDesc_RCH;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected DMA Rx Desc second address chained */\r
+ DMARxDesc->ControlBufferSize &=(~(u32)ETH_DMARxDesc_RCH);\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : ETH_GetDMARxDescBufferSize\r
+* Desciption : Returns the specified ETHERNET DMA Rx Desc buffer size.\r
+* Input : - DMARxDesc: pointer on a DMA Rx descriptor\r
+* - DMARxDesc_Buffer: specifies the DMA Rx Desc buffer.\r
+* This parameter can be any one of the following values:\r
+* - ETH_DMARxDesc_Buffer1 : DMA Rx Desc Buffer1\r
+* - ETH_DMARxDesc_Buffer2 : DMA Rx Desc Buffer2\r
+* Output : None\r
+* Return : The Receive descriptor frame length.\r
+*******************************************************************************/\r
+u32 ETH_GetDMARxDescBufferSize(ETH_DMADESCTypeDef *DMARxDesc, u32 DMARxDesc_Buffer)\r
+{\r
+ /* Check the parameters */\r
+ eth_assert_param(IS_ETH_DMA_RXDESC_BUFFER(DMARxDesc_Buffer));\r
+\r
+ if(DMARxDesc_Buffer != ETH_DMARxDesc_Buffer1)\r
+ {\r
+ /* Return the DMA Rx Desc buffer2 size */\r
+ return ((DMARxDesc->ControlBufferSize & ETH_DMARxDesc_RBS2) >> ETH_DMARxDesc_Buffer2SizeShift);\r
+ }\r
+ else\r
+ {\r
+ /* Return the DMA Rx Desc buffer1 size */\r
+ return (DMARxDesc->ControlBufferSize & ETH_DMARxDesc_RBS1);\r
+ }\r
+}\r
+\r
+/*--------------------------------- DMA ------------------------------------*/\r
+/*******************************************************************************\r
+* Function Name : ETH_SoftwareReset\r
+* Desciption : Resets all MAC subsystem internal registers and logic.\r
+* Input : None\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void ETH_SoftwareReset(void)\r
+{\r
+ /* Set the SWR bit: resets all MAC subsystem internal registers and logic */\r
+ /* After reset all the registers holds their respective reset values */\r
+ ETH_DMA->DMABMR |= ETH_DMABMR_SR;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : ETH_GetSoftwareResetStatus\r
+* Desciption : Checks whether the ETHERNET software reset bit is set or not.\r
+* Input : None\r
+* Output : None\r
+* Return : The new state of DMA Bus Mode register SR bit (SET or RESET).\r
+*******************************************************************************/\r
+FlagStatus ETH_GetSoftwareResetStatus(void)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+\r
+ if((ETH_DMA->DMABMR & ETH_DMABMR_SR) != (u32)RESET)\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ return bitstatus;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : ETH_GetDMAFlagStatus\r
+* Desciption : Checks whether the specified ETHERNET DMA flag is set or not.\r
+* Input : - ETH_DMA_IT: specifies the flag to check.\r
+* This parameter can be one of the following values:\r
+* - ETH_DMA_FLAG_TST : Time-stamp trigger flag\r
+* - ETH_DMA_FLAG_PMT : PMT flag\r
+* - ETH_DMA_FLAG_MMC : MMC flag\r
+* - ETH_DMA_FLAG_DataTransferError : Error bits 0-data buffer, 1-desc. access\r
+* - ETH_DMA_FLAG_ReadWriteError : Error bits 0-write trnsf, 1-read transfr\r
+* - ETH_DMA_FLAG_AccessError : Error bits 0-Rx DMA, 1-Tx DMA\r
+* - ETH_DMA_FLAG_NIS : Normal interrupt summary flag\r
+* - ETH_DMA_FLAG_AIS : Abnormal interrupt summary flag\r
+* - ETH_DMA_FLAG_ER : Early receive flag\r
+* - ETH_DMA_FLAG_FBE : Fatal bus error flag\r
+* - ETH_DMA_FLAG_ET : Early transmit flag\r
+* - ETH_DMA_FLAG_RWT : Receive watchdog timeout flag\r
+* - ETH_DMA_FLAG_RPS : Receive process stopped flag\r
+* - ETH_DMA_FLAG_RBU : Receive buffer unavailable flag\r
+* - ETH_DMA_FLAG_R : Receive flag\r
+* - ETH_DMA_FLAG_TU : Underflow flag\r
+* - ETH_DMA_FLAG_RO : Overflow flag\r
+* - ETH_DMA_FLAG_TJT : Transmit jabber timeout flag\r
+* - ETH_DMA_FLAG_TBU : Transmit buffer unavailable flag\r
+* - ETH_DMA_FLAG_TPS : Transmit process stopped flag\r
+* - ETH_DMA_FLAG_T : Transmit flag\r
+* Output : None\r
+* Return : The new state of ETH_DMA_FLAG (SET or RESET).\r
+*******************************************************************************/\r
+FlagStatus ETH_GetDMAFlagStatus(u32 ETH_DMA_FLAG)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+\r
+ /* Check the parameters */\r
+ eth_assert_param(IS_ETH_DMA_GET_IT(ETH_DMA_FLAG));\r
+\r
+ if ((ETH_DMA->DMASR & ETH_DMA_FLAG) != (u32)RESET)\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ return bitstatus;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : ETH_DMAClearFlag\r
+* Desciption : Clears the ETHERNET?s DMA pending flag.\r
+* Input : - ETH_DMA_FLAG: specifies the flag to clear.\r
+* This parameter can be any combination of the following values:\r
+* - ETH_DMA_FLAG_NIS : Normal interrupt summary flag\r
+* - ETH_DMA_FLAG_AIS : Abnormal interrupt summary flag\r
+* - ETH_DMA_FLAG_ER : Early receive flag\r
+* - ETH_DMA_FLAG_FBE : Fatal bus error flag\r
+* - ETH_DMA_FLAG_ETI : Early transmit flag\r
+* - ETH_DMA_FLAG_RWT : Receive watchdog timeout flag\r
+* - ETH_DMA_FLAG_RPS : Receive process stopped flag\r
+* - ETH_DMA_FLAG_RBU : Receive buffer unavailable flag\r
+* - ETH_DMA_FLAG_R : Receive flag\r
+* - ETH_DMA_FLAG_TU : Transmit Underflow flag\r
+* - ETH_DMA_FLAG_RO : Receive Overflow flag\r
+* - ETH_DMA_FLAG_TJT : Transmit jabber timeout flag\r
+* - ETH_DMA_FLAG_TBU : Transmit buffer unavailable flag\r
+* - ETH_DMA_FLAG_TPS : Transmit process stopped flag\r
+* - ETH_DMA_FLAG_T : Transmit flag\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void ETH_DMAClearFlag(u32 ETH_DMA_FLAG)\r
+{\r
+ /* Check the parameters */\r
+ eth_assert_param(IS_ETH_DMA_FLAG(ETH_DMA_FLAG));\r
+\r
+ /* Clear the selected ETHERNET DMA FLAG */\r
+ ETH_DMA->DMASR = (u32) ETH_DMA_FLAG;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : ETH_GetDMAITStatus\r
+* Desciption : Checks whether the specified ETHERNET DMA interrupt has occured or not.\r
+* Input : - ETH_DMA_IT: specifies the interrupt source to check.\r
+* This parameter can be one of the following values:\r
+* - ETH_DMA_IT_TST : Time-stamp trigger interrupt\r
+* - ETH_DMA_IT_PMT : PMT interrupt\r
+* - ETH_DMA_IT_MMC : MMC interrupt\r
+* - ETH_DMA_IT_NIS : Normal interrupt summary\r
+* - ETH_DMA_IT_AIS : Abnormal interrupt summary\r
+* - ETH_DMA_IT_ER : Early receive interrupt\r
+* - ETH_DMA_IT_FBE : Fatal bus error interrupt\r
+* - ETH_DMA_IT_ET : Early transmit interrupt\r
+* - ETH_DMA_IT_RWT : Receive watchdog timeout interrupt\r
+* - ETH_DMA_IT_RPS : Receive process stopped interrupt\r
+* - ETH_DMA_IT_RBU : Receive buffer unavailable interrupt\r
+* - ETH_DMA_IT_R : Receive interrupt\r
+* - ETH_DMA_IT_TU : Underflow interrupt\r
+* - ETH_DMA_IT_RO : Overflow interrupt\r
+* - ETH_DMA_IT_TJT : Transmit jabber timeout interrupt\r
+* - ETH_DMA_IT_TBU : Transmit buffer unavailable interrupt\r
+* - ETH_DMA_IT_TPS : Transmit process stopped interrupt\r
+* - ETH_DMA_IT_T : Transmit interrupt\r
+* Output : None\r
+* Return : The new state of ETH_DMA_IT (SET or RESET).\r
+*******************************************************************************/\r
+ITStatus ETH_GetDMAITStatus(u32 ETH_DMA_IT)\r
+{\r
+ ITStatus bitstatus = RESET;\r
+\r
+ /* Check the parameters */\r
+ eth_assert_param(IS_ETH_DMA_GET_IT(ETH_DMA_IT));\r
+\r
+ if ((ETH_DMA->DMASR & ETH_DMA_IT) != (u32)RESET)\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ return bitstatus;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : ETH_DMAClearITPendingBit\r
+* Desciption : Clears the ETHERNET?s DMA IT pending bit.\r
+* Input : - ETH_DMA_IT: specifies the interrupt pending bit to clear.\r
+* This parameter can be any combination of the following values:\r
+* - ETH_DMA_IT_NIS : Normal interrupt summary\r
+* - ETH_DMA_IT_AIS : Abnormal interrupt summary\r
+* - ETH_DMA_IT_ER : Early receive interrupt\r
+* - ETH_DMA_IT_FBE : Fatal bus error interrupt\r
+* - ETH_DMA_IT_ETI : Early transmit interrupt\r
+* - ETH_DMA_IT_RWT : Receive watchdog timeout interrupt\r
+* - ETH_DMA_IT_RPS : Receive process stopped interrupt\r
+* - ETH_DMA_IT_RBU : Receive buffer unavailable interrupt\r
+* - ETH_DMA_IT_R : Receive interrupt\r
+* - ETH_DMA_IT_TU : Transmit Underflow interrupt\r
+* - ETH_DMA_IT_RO : Receive Overflow interrupt\r
+* - ETH_DMA_IT_TJT : Transmit jabber timeout interrupt\r
+* - ETH_DMA_IT_TBU : Transmit buffer unavailable interrupt\r
+* - ETH_DMA_IT_TPS : Transmit process stopped interrupt\r
+* - ETH_DMA_IT_T : Transmit interrupt\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void ETH_DMAClearITPendingBit(u32 ETH_DMA_IT)\r
+{\r
+ /* Check the parameters */\r
+ eth_assert_param(IS_ETH_DMA_IT(ETH_DMA_IT));\r
+\r
+ /* Clear the selected ETHERNET DMA IT */\r
+ ETH_DMA->DMASR = (u32) ETH_DMA_IT;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : ETH_GetDMATransmitProcessState\r
+* Desciption : Returns the ETHERNET DMA Transmit Process State.\r
+* Input : None\r
+* Output : None\r
+* Return : The new ETHERNET DMA Transmit Process State:\r
+* This can be one of the following values:\r
+* - ETH_DMA_TransmitProcess_Stopped : Stopped - Reset or Stop Tx Command issued\r
+* - ETH_DMA_TransmitProcess_Fetching : Running - fetching the Tx descriptor\r
+* - ETH_DMA_TransmitProcess_Waiting : Running - waiting for status\r
+* - ETH_DMA_TransmitProcess_Reading : unning - reading the data from host memory\r
+* - ETH_DMA_TransmitProcess_Suspended : Suspended - Tx Desciptor unavailabe\r
+* - ETH_DMA_TransmitProcess_Closing : Running - closing Rx descriptor\r
+*******************************************************************************/\r
+u32 ETH_GetTransmitProcessState(void)\r
+{\r
+ return ((u32)(ETH_DMA->DMASR & ETH_DMASR_TS));\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : ETH_GetDMAReceiveProcessState\r
+* Desciption : Returns the ETHERNET DMA Receive Process State.\r
+* Input : None\r
+* Output : None\r
+* Return : The new ETHERNET DMA Receive Process State:\r
+* This can be one of the following values:\r
+* - ETH_DMA_ReceiveProcess_Stopped : Stopped - Reset or Stop Rx Command issued\r
+* - ETH_DMA_ReceiveProcess_Fetching : Running - fetching the Rx descriptor\r
+* - ETH_DMA_ReceiveProcess_Waiting : Running - waiting for packet\r
+* - ETH_DMA_ReceiveProcess_Suspended : Suspended - Rx Desciptor unavailable\r
+* - ETH_DMA_ReceiveProcess_Closing : Running - closing descriptor\r
+* - ETH_DMA_ReceiveProcess_Queuing : Running - queuing the recieve frame into host memory\r
+*******************************************************************************/\r
+u32 ETH_GetReceiveProcessState(void)\r
+{\r
+ return ((u32)(ETH_DMA->DMASR & ETH_DMASR_RS));\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : ETH_FlushTransmitFIFO\r
+* Desciption : Clears the ETHERNET transmit FIFO.\r
+* Input : None\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void ETH_FlushTransmitFIFO(void)\r
+{\r
+ /* Set the Flush Transmit FIFO bit */\r
+ ETH_DMA->DMAOMR |= ETH_DMAOMR_FTF;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : ETH_GetFlushTransmitFIFOStatus\r
+* Desciption : Checks whether the ETHERNET transmit FIFO bit is cleared or not.\r
+* Input : None\r
+* Output : None\r
+* Return : The new state of ETHERNET flush transmit FIFO bit (SET or RESET).\r
+*******************************************************************************/\r
+FlagStatus ETH_GetFlushTransmitFIFOStatus(void)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+\r
+ if ((ETH_DMA->DMAOMR & ETH_DMAOMR_FTF) != (u32)RESET)\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ return bitstatus;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : ETH_DMATransmissionCmd\r
+* Desciption : Enables or disables the DMA transmission.\r
+* Input : - NewState: new state of the DMA transmission.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void ETH_DMATransmissionCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ eth_assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the DMA transmission */\r
+ ETH_DMA->DMAOMR |= ETH_DMAOMR_ST;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the DMA transmission */\r
+ ETH_DMA->DMAOMR &= ~ETH_DMAOMR_ST;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : ETH_DMAReceptionCmd\r
+* Desciption : Enables or disables the DMA reception.\r
+* Input : - NewState: new state of the DMA reception.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void ETH_DMAReceptionCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ eth_assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the DMA reception */\r
+ ETH_DMA->DMAOMR |= ETH_DMAOMR_SR;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the DMA reception */\r
+ ETH_DMA->DMAOMR &= ~ETH_DMAOMR_SR;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : ETH_DMAITConfig\r
+* Desciption : Enables or disables the specified ETHERNET DMA interrupts.\r
+* Input : - ETH_DMA_IT: specifies the ETHERNET DMA interrupt sources to be\r
+* enabled or disabled.\r
+* This parameter can be any combination of the following values:\r
+* - ETH_DMA_IT_NIS : Normal interrupt summary\r
+* - ETH_DMA_IT_AIS : Abnormal interrupt summary\r
+* - ETH_DMA_IT_ER : Early receive interrupt\r
+* - ETH_DMA_IT_FBE : Fatal bus error interrupt\r
+* - ETH_DMA_IT_ET : Early transmit interrupt\r
+* - ETH_DMA_IT_RWT : Receive watchdog timeout interrupt\r
+* - ETH_DMA_IT_RPS : Receive process stopped interrupt\r
+* - ETH_DMA_IT_RBU : Receive buffer unavailable interrupt\r
+* - ETH_DMA_IT_R : Receive interrupt\r
+* - ETH_DMA_IT_TU : Underflow interrupt\r
+* - ETH_DMA_IT_RO : Overflow interrupt\r
+* - ETH_DMA_IT_TJT : Transmit jabber timeout interrupt\r
+* - ETH_DMA_IT_TBU : Transmit buffer unavailable interrupt\r
+* - ETH_DMA_IT_TPS : Transmit process stopped interrupt\r
+* - ETH_DMA_IT_T : Transmit interrupt\r
+* - NewState: new state of the specified ETHERNET DMA interrupts.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void ETH_DMAITConfig(u32 ETH_DMA_IT, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ eth_assert_param(IS_ETH_DMA_IT(ETH_DMA_IT));\r
+ eth_assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected ETHERNET DMA interrupts */\r
+ ETH_DMA->DMAIER |= ETH_DMA_IT;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected ETHERNET DMA interrupts */\r
+ ETH_DMA->DMAIER &=(~(u32)ETH_DMA_IT);\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : ETH_GetDMAOverflowStatus\r
+* Desciption : Checks whether the specified ETHERNET DMA overflow flag is set or not.\r
+* Input : - ETH_DMA_Overflow: specifies the DMA overflow flag to check.\r
+* This parameter can be one of the following values:\r
+* - ETH_DMA_Overflow_RxFIFOCounter : Overflow for FIFO Overflow Counter\r
+* - ETH_DMA_Overflow_MissedFrameCounter : Overflow for Missed Frame Counter\r
+* Output : None\r
+* Return : The new state of ETHERNET DMA overflow Flag (SET or RESET).\r
+*******************************************************************************/\r
+FlagStatus ETH_GetDMAOverflowStatus(u32 ETH_DMA_Overflow)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+\r
+ /* Check the parameters */\r
+ eth_assert_param(IS_ETH_DMA_GET_OVERFLOW(ETH_DMA_Overflow));\r
+\r
+ if ((ETH_DMA->DMAMFBOCR & ETH_DMA_Overflow) != (u32)RESET)\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ return bitstatus;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : ETH_GetRxOverflowMissedFrameCounter\r
+* Desciption : Get the ETHERNET DMA Rx Overflow Missed Frame Counter value.\r
+* Input : None\r
+* Output : None\r
+* Return : The value of Rx overflow Missed Frame Counter.\r
+*******************************************************************************/\r
+u32 ETH_GetRxOverflowMissedFrameCounter(void)\r
+{\r
+ return ((u32)((ETH_DMA->DMAMFBOCR & ETH_DMAMFBOCR_MFA)>>ETH_DMA_RxOverflowMissedFramesCounterShift));\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : ETH_GetBufferUnavailableMissedFrameCounter\r
+* Desciption : Get the ETHERNET DMA Buffer Unavailable Missed Frame Counter value.\r
+* Input : None\r
+* Output : None\r
+* Return : The value of Buffer unavailable Missed Frame Counter.\r
+*******************************************************************************/\r
+u32 ETH_GetBufferUnavailableMissedFrameCounter(void)\r
+{\r
+ return ((u32)(ETH_DMA->DMAMFBOCR) & ETH_DMAMFBOCR_MFC);\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : ETH_GetCurrentTxDescStartAddress\r
+* Desciption : Get the ETHERNET DMA DMACHTDR register value.\r
+* Input : None\r
+* Output : None\r
+* Return : The value of the current Tx desc start address.\r
+*******************************************************************************/\r
+u32 ETH_GetCurrentTxDescStartAddress(void)\r
+{\r
+ return ((u32)(ETH_DMA->DMACHTDR));\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : ETH_GetCurrentRxDescStartAddress\r
+* Desciption : Get the ETHERNET DMA DMACHRDR register value.\r
+* Input : None\r
+* Output : None\r
+* Return : The value of the current Rx desc start address.\r
+*******************************************************************************/\r
+u32 ETH_GetCurrentRxDescStartAddress(void)\r
+{\r
+ return ((u32)(ETH_DMA->DMACHRDR));\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : ETH_GetCurrentTxBufferAddress\r
+* Desciption : Get the ETHERNET DMA DMACHTBAR register value.\r
+* Input : None\r
+* Output : None\r
+* Return : The value of the current Tx desc buffer address.\r
+*******************************************************************************/\r
+u32 ETH_GetCurrentTxBufferAddress(void)\r
+{\r
+ return ((u32)(ETH_DMA->DMACHTBAR));\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : ETH_GetCurrentRxBufferAddress\r
+* Desciption : Get the ETHERNET DMA DMACHRBAR register value.\r
+* Input : None\r
+* Output : None\r
+* Return : The value of the current Rx desc buffer address.\r
+*******************************************************************************/\r
+u32 ETH_GetCurrentRxBufferAddress(void)\r
+{\r
+ return ((u32)(ETH_DMA->DMACHRBAR));\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : ETH_ResumeDMATransmission\r
+* Desciption : Resumes the DMA Transmission by writing to the DmaTxPollDemand\r
+* register: (the data written could be anything). This forces\r
+* the DMA to resume transmission.\r
+* Input : None\r
+* Output : None\r
+* Return : None.\r
+*******************************************************************************/\r
+void ETH_ResumeDMATransmission(void)\r
+{\r
+ ETH_DMA->DMATPDR = 0;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : ETH_ResumeDMAReception\r
+* Desciption : Resumes the DMA Transmission by writing to the DmaRxPollDemand\r
+* register: (the data written could be anything). This forces\r
+* the DMA to resume reception.\r
+* Input : None\r
+* Output : None\r
+* Return : None.\r
+*******************************************************************************/\r
+void ETH_ResumeDMAReception(void)\r
+{\r
+ ETH_DMA->DMARPDR = 0;\r
+}\r
+\r
+#endif /* _ETH_DMA */\r
+/*--------------------------------- PMT ------------------------------------*/\r
+/*******************************************************************************\r
+* Function Name : ETH_ResetWakeUpFrameFilterRegisterPointer\r
+* Desciption : Reset Wakeup frame filter register pointer.\r
+* Input : None\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void ETH_ResetWakeUpFrameFilterRegisterPointer(void)\r
+{\r
+ /* Resets the Remote Wake-up Frame Filter register pointer to 0x0000 */\r
+ ETH_MAC->MACPMTCSR |= ETH_MACPMTCSR_WFFRPR;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : ETH_SetWakeUpFrameFilterRegister\r
+* Desciption : Populates the remote wakeup frame registers.\r
+* Input : - Buffer: Pointer on remote WakeUp Frame Filter Register buffer\r
+* data (8 words).\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void ETH_SetWakeUpFrameFilterRegister(u32 *Buffer)\r
+{\r
+ u32 i = 0;\r
+\r
+ /* Fill Remote Wake-up Frame Filter register with Buffer data */\r
+ for(i =0; i<ETH_WakeupRegisterLength; i++)\r
+ {\r
+ /* Write each time to the same register */\r
+ ETH_MAC->MACRWUFFR = Buffer[i];\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : ETH_GlobalUnicastWakeUpCmd\r
+* Desciption : Enables or disables any unicast packet filtered by the MAC\r
+* (DAF) address recognition to be a wake-up frame.\r
+* Input : - NewState: new state of the MAC Global Unicast Wake-Up.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void ETH_GlobalUnicastWakeUpCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ eth_assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the MAC Global Unicast Wake-Up */\r
+ ETH_MAC->MACPMTCSR |= ETH_MACPMTCSR_GU;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the MAC Global Unicast Wake-Up */\r
+ ETH_MAC->MACPMTCSR &= ~ETH_MACPMTCSR_GU;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : ETH_GetPMTFlagStatus\r
+* Desciption : Checks whether the specified ETHERNET PMT flag is set or not.\r
+* Input : - ETH_PMT_FLAG: specifies the flag to check.\r
+* This parameter can be one of the following values:\r
+* - ETH_PMT_FLAG_WUFFRPR : Wake-Up Frame Filter Register Poniter Reset\r
+* - ETH_PMT_FLAG_WUFR : Wake-Up Frame Received\r
+* - ETH_PMT_FLAG_MPR : Magic Packet Received\r
+* Output : None\r
+* Return : The new state of ETHERNET PMT Flag (SET or RESET).\r
+*******************************************************************************/\r
+FlagStatus ETH_GetPMTFlagStatus(u32 ETH_PMT_FLAG)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+\r
+ /* Check the parameters */\r
+ eth_assert_param(IS_ETH_PMT_GET_FLAG(ETH_PMT_FLAG));\r
+\r
+ if ((ETH_MAC->MACPMTCSR & ETH_PMT_FLAG) != (u32)RESET)\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ return bitstatus;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : ETH_WakeUpFrameDetectionCmd\r
+* Desciption : Enables or disables the MAC Wake-Up Frame Detection.\r
+* Input : - NewState: new state of the MAC Wake-Up Frame Detection.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void ETH_WakeUpFrameDetectionCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ eth_assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the MAC Wake-Up Frame Detection */\r
+ ETH_MAC->MACPMTCSR |= ETH_MACPMTCSR_WFE;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the MAC Wake-Up Frame Detection */\r
+ ETH_MAC->MACPMTCSR &= ~ETH_MACPMTCSR_WFE;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : ETH_MagicPacketDetectionCmd\r
+* Desciption : Enables or disables the MAC Magic Packet Detection.\r
+* Input : - NewState: new state of the MAC Magic Packet Detection.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void ETH_MagicPacketDetectionCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ eth_assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the MAC Magic Packet Detection */\r
+ ETH_MAC->MACPMTCSR |= ETH_MACPMTCSR_MPE;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the MAC Magic Packet Detection */\r
+ ETH_MAC->MACPMTCSR &= ~ETH_MACPMTCSR_MPE;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : ETH_PowerDownCmd\r
+* Desciption : Enables or disables the MAC Power Down.\r
+* Input : - NewState: new state of the MAC Power Down.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void ETH_PowerDownCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ eth_assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the MAC Power Down */\r
+ /* This puts the MAC in power down mode */\r
+ ETH_MAC->MACPMTCSR |= ETH_MACPMTCSR_PD;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the MAC Power Down */\r
+ ETH_MAC->MACPMTCSR &= ~ETH_MACPMTCSR_PD;\r
+ }\r
+}\r
+\r
+/*--------------------------------- MMC ------------------------------------*/\r
+#ifdef _ETH_MMC\r
+\r
+/*******************************************************************************\r
+* Function Name : ETH_MMCCounterFreezeCmd\r
+* Desciption : Enables or disables the MMC Counter Freeze.\r
+* Input : - NewState: new state of the MMC Counter Freeze.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void ETH_MMCCounterFreezeCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ eth_assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the MMC Counter Freeze */\r
+ ETH_MMC->MMCCR |= ETH_MMCCR_MCF;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the MMC Counter Freeze */\r
+ ETH_MMC->MMCCR &= ~ETH_MMCCR_MCF;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : ETH_MMCResetOnReadCmd\r
+* Desciption : Enables or disables the MMC Reset On Read.\r
+* Input : - NewState: new state of the MMC Reset On Read.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void ETH_MMCResetOnReadCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ eth_assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the MMC Counter reset on read */\r
+ ETH_MMC->MMCCR |= ETH_MMCCR_ROR;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the MMC Counter reset on read */\r
+ ETH_MMC->MMCCR &= ~ETH_MMCCR_ROR;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : ETH_MMCCounterRolloverCmd\r
+* Desciption : Enables or disables the MMC Counter Stop Rollover.\r
+* Input : - NewState: new state of the MMC Counter Stop Rollover.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void ETH_MMCCounterRolloverCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ eth_assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Disable the MMC Counter Stop Rollover */\r
+ ETH_MMC->MMCCR &= ~ETH_MMCCR_CSR;\r
+ }\r
+ else\r
+ {\r
+ /* Enable the MMC Counter Stop Rollover */\r
+ ETH_MMC->MMCCR |= ETH_MMCCR_CSR;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : ETH_MMCCountersReset\r
+* Desciption : Resets the MMC Counters.\r
+* Input : None\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void ETH_MMCCountersReset(void)\r
+{\r
+ /* Resets the MMC Counters */\r
+ ETH_MMC->MMCCR |= ETH_MMCCR_CR;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : ETH_MMCITConfig\r
+* Desciption : Enables or disables the specified ETHERNET MMC interrupts.\r
+* Input : - ETH_MMC_IT: specifies the ETHERNET MMC interrupt\r
+* sources to be enabled or disabled.\r
+* This parameter can be any combination of Tx interrupt or\r
+* any combination of Rx interrupt (but not both)of the following values:\r
+* - ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value\r
+* - ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value\r
+* - ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value\r
+* - ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value\r
+* - ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value\r
+* - ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value\r
+* - NewState: new state of the specified ETHERNET MMC interrupts.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void ETH_MMCITConfig(u32 ETH_MMC_IT, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ eth_assert_param(IS_ETH_MMC_IT(ETH_MMC_IT));\r
+ eth_assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if ((ETH_MMC_IT & (u32)0x10000000) != (u32)RESET)\r
+ {\r
+ /* Remove egister mak from IT */\r
+ ETH_MMC_IT &= 0xEFFFFFFF;\r
+\r
+ /* ETHERNET MMC Rx interrupts selected */\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected ETHERNET MMC interrupts */\r
+ ETH_MMC->MMCRIMR &=(~(u32)ETH_MMC_IT);\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected ETHERNET MMC interrupts */\r
+ ETH_MMC->MMCRIMR |= ETH_MMC_IT;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* ETHERNET MMC Tx interrupts selected */\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected ETHERNET MMC interrupts */\r
+ ETH_MMC->MMCTIMR &=(~(u32)ETH_MMC_IT);\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected ETHERNET MMC interrupts */\r
+ ETH_MMC->MMCTIMR |= ETH_MMC_IT;\r
+ }\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : ETH_GetMMCITStatus\r
+* Desciption : Checks whether the specified ETHERNET MMC IT is set or not.\r
+* Input : - ETH_MMC_IT: specifies the ETHERNET MMC interrupt.\r
+* This parameter can be one of the following values:\r
+* - ETH_MMC_IT_TxFCGC: When Tx good frame counter reaches half the maximum value\r
+* - ETH_MMC_IT_TxMCGC: When Tx good multi col counter reaches half the maximum value\r
+* - ETH_MMC_IT_TxSCGC: When Tx good single col counter reaches half the maximum value\r
+* - ETH_MMC_IT_RxUGFC: When Rx good unicast frames counter reaches half the maximum value\r
+* - ETH_MMC_IT_RxAEC : When Rx alignment error counter reaches half the maximum value\r
+* - ETH_MMC_IT_RxCEC : When Rx crc error counter reaches half the maximum value\r
+* Output : None\r
+* Return : The value of ETHERNET MMC IT (SET or RESET).\r
+*******************************************************************************/\r
+ITStatus ETH_GetMMCITStatus(u32 ETH_MMC_IT)\r
+{\r
+ ITStatus bitstatus = RESET;\r
+\r
+ /* Check the parameters */\r
+ eth_assert_param(IS_ETH_MMC_GET_IT(ETH_MMC_IT));\r
+\r
+ if ((ETH_MMC_IT & (u32)0x10000000) != (u32)RESET)\r
+ {\r
+ /* ETHERNET MMC Rx interrupts selected */\r
+ /* Check if the ETHERNET MMC Rx selected interrupt is enabled and occured */\r
+ if ((((ETH_MMC->MMCRIR & ETH_MMC_IT) != (u32)RESET)) && ((ETH_MMC->MMCRIMR & ETH_MMC_IT) != (u32)RESET))\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* ETHERNET MMC Tx interrupts selected */\r
+ /* Check if the ETHERNET MMC Tx selected interrupt is enabled and occured */\r
+ if ((((ETH_MMC->MMCTIR & ETH_MMC_IT) != (u32)RESET)) && ((ETH_MMC->MMCRIMR & ETH_MMC_IT) != (u32)RESET))\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ }\r
+\r
+ return bitstatus;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : ETH_GetMMCRegister\r
+* Desciption : Get the specified ETHERNET MMC register value.\r
+* Input : - ETH_MMCReg: specifies the ETHERNET MMC register.\r
+* This parameter can be one of the following values:\r
+* - ETH_MMCCR : MMC CR register\r
+* - ETH_MMCRIR : MMC RIR register\r
+* - ETH_MMCTIR : MMC TIR register\r
+* - ETH_MMCRIMR : MMC RIMR register\r
+* - ETH_MMCTIMR : MMC TIMR register\r
+* - ETH_MMCTGFSCCR : MMC TGFSCCR register\r
+* - ETH_MMCTGFMSCCR: MMC TGFMSCCR register\r
+* - ETH_MMCTGFCR : MMC TGFCR register\r
+* - ETH_MMCRFCECR : MMC RFCECR register\r
+* - ETH_MMCRFAECR : MMC RFAECR register\r
+* - ETH_MMCRGUFCR : MMC RGUFCRregister\r
+* Output : None\r
+* Return : The value of ETHERNET MMC Register value.\r
+*******************************************************************************/\r
+u32 ETH_GetMMCRegister(u32 ETH_MMCReg)\r
+{\r
+ /* Check the parameters */\r
+ eth_assert_param(IS_ETH_MMC_REGISTER(ETH_MMCReg));\r
+\r
+ /* Return the selected register value */\r
+ return (*(vu32 *)(ETH_MAC_BASE + ETH_MMCReg));\r
+}\r
+#endif /* _ETH_MMC */\r
+\r
+/*--------------------------------- PTP ------------------------------------*/\r
+#ifdef _ETH_PTP\r
+\r
+/*******************************************************************************\r
+* Function Name : ETH_EnablePTPTimeStampAddend\r
+* Desciption : Updated the PTP block for fine correction with the Time Stamp\r
+* Addend register value.\r
+* Input : None\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void ETH_EnablePTPTimeStampAddend(void)\r
+{\r
+ /* Enable the PTP block update with the Time Stamp Addend register value */\r
+ ETH_PTP->PTPTSCR |= ETH_PTPTSCR_TSARU;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : ETH_EnablePTPTimeStampInterruptTrigger\r
+* Desciption : Enable the PTP Time Stamp interrupt trigger\r
+* Input : None\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void ETH_EnablePTPTimeStampInterruptTrigger(void)\r
+{\r
+ /* Enable the PTP target time interrupt */\r
+ ETH_PTP->PTPTSCR |= ETH_PTPTSCR_TSITE;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : ETH_EnablePTPTimeStampUpdate\r
+* Desciption : Updated the PTP system time with the Time Stamp Update register\r
+* value.\r
+* Input : None\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void ETH_EnablePTPTimeStampUpdate(void)\r
+{\r
+ /* Enable the PTP system time update with the Time Stamp Update register value */\r
+ ETH_PTP->PTPTSCR |= ETH_PTPTSCR_TSSTU;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : ETH_InitializePTPTimeStamp\r
+* Desciption : Initialize the PTP Time Stamp\r
+* Input : None\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void ETH_InitializePTPTimeStamp(void)\r
+{\r
+ /* Initialize the PTP Time Stamp */\r
+ ETH_PTP->PTPTSCR |= ETH_PTPTSCR_TSSTI;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : ETH_PTPUpdateMethodConfig\r
+* Desciption : Selects the PTP Update method\r
+* Input : - UpdateMethod: the PTP Update method\r
+* This parameter can be one of the following values:\r
+* - ETH_PTP_FineUpdate : Fine Update method\r
+* - ETH_PTP_CoarseUpdate : Coarse Update method\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void ETH_PTPUpdateMethodConfig(u32 UpdateMethod)\r
+{\r
+ /* Check the parameters */\r
+ eth_assert_param(IS_ETH_PTP_UPDATE(UpdateMethod));\r
+\r
+ if (UpdateMethod != ETH_PTP_CoarseUpdate)\r
+ {\r
+ /* Enable the PTP Fine Update method */\r
+ ETH_PTP->PTPTSCR |= ETH_PTPTSCR_TSFCU;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the PTP Coarse Update method */\r
+ ETH_PTP->PTPTSCR &= (~(u32)ETH_PTPTSCR_TSFCU);\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : ETH_PTPTimeStampCmd\r
+* Desciption : Enables or disables the PTP time stamp for transmit and receive frames.\r
+* Input : - NewState: new state of the PTP time stamp for transmit and receive frames\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void ETH_PTPTimeStampCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ eth_assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the PTP time stamp for transmit and receive frames */\r
+ ETH_PTP->PTPTSCR |= ETH_PTPTSCR_TSE;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the PTP time stamp for transmit and receive frames */\r
+ ETH_PTP->PTPTSCR &= (~(u32)ETH_PTPTSCR_TSE);\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : ETH_GetPTPFlagStatus\r
+* Desciption : Checks whether the specified ETHERNET PTP flag is set or not.\r
+* Input : - ETH_PTP_FLAG: specifies the flag to check.\r
+* This parameter can be one of the following values:\r
+* - ETH_PTP_FLAG_TSARU : Addend Register Update\r
+* - ETH_PTP_FLAG_TSITE : Time Stamp Interrupt Trigger Enable\r
+* - ETH_PTP_FLAG_TSSTU : Time Stamp Update\r
+* - ETH_PTP_FLAG_TSSTI : Time Stamp Initialize\r
+* Output : None\r
+* Return : The new state of ETHERNET PTP Flag (SET or RESET).\r
+*******************************************************************************/\r
+FlagStatus ETH_GetPTPFlagStatus(u32 ETH_PTP_FLAG)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+\r
+ /* Check the parameters */\r
+ eth_assert_param(IS_ETH_PTP_GET_FLAG(ETH_PTP_FLAG));\r
+\r
+ if ((ETH_PTP->PTPTSCR & ETH_PTP_FLAG) != (u32)RESET)\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ return bitstatus;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : ETH_SetPTPSubSecondIncrement\r
+* Desciption : Sets the system time Sub-Second Increment value.\r
+* Input : - SubSecondValue: specifies the PTP Sub-Second Increment Register value.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void ETH_SetPTPSubSecondIncrement(u32 SubSecondValue)\r
+{\r
+ /* Check the parameters */\r
+ eth_assert_param(IS_ETH_PTP_SUBSECOND_INCREMENT(SubSecondValue));\r
+\r
+ /* Set the PTP Sub-Second Increment Register */\r
+ ETH_PTP->PTPSSIR = SubSecondValue;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : ETH_SetPTPTimeStampUpdate\r
+* Desciption : Sets the Time Stamp update sign and values.\r
+* Input : - Sign: specifies the PTP Time update value sign.\r
+* This parameter can be one of the following values:\r
+* - ETH_PTP_PositiveTime : positive time value.\r
+* - ETH_PTP_NegativeTime : negative time value.\r
+* - SecondValue: specifies the PTP Time update second value.\r
+* - SubSecondValue: specifies the PTP Time update sub-second value.\r
+* this is a 31 bit value. bit32 correspond to the sign.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void ETH_SetPTPTimeStampUpdate(u32 Sign, u32 SecondValue, u32 SubSecondValue)\r
+{\r
+ /* Check the parameters */\r
+ eth_assert_param(IS_ETH_PTP_TIME_SIGN(Sign));\r
+ eth_assert_param(IS_ETH_PTP_TIME_STAMP_UPDATE_SUBSECOND(SubSecondValue));\r
+\r
+ /* Set the PTP Time Update High Register */\r
+ ETH_PTP->PTPTSHUR = SecondValue;\r
+\r
+ /* Set the PTP Time Update Low Register with sign */\r
+ ETH_PTP->PTPTSLUR = Sign | SubSecondValue;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : ETH_SetPTPTimeStampAddend\r
+* Desciption : Sets the Time Stamp Addend value.\r
+* Input : - Value: specifies the PTP Time Stamp Addend Register value.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void ETH_SetPTPTimeStampAddend(u32 Value)\r
+{\r
+ /* Set the PTP Time Stamp Addend Register */\r
+ ETH_PTP->PTPTSAR = Value;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : ETH_SetPTPTargetTime\r
+* Desciption : Sets the Target Time registers values.\r
+* Input : - HighValue: specifies the PTP Target Time High Register value.\r
+* - LowValue: specifies the PTP Target Time Low Register value.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void ETH_SetPTPTargetTime(u32 HighValue, u32 LowValue)\r
+{\r
+ /* Set the PTP Target Time High Register */\r
+ ETH_PTP->PTPTTHR = HighValue;\r
+ /* Set the PTP Target Time Low Register */\r
+ ETH_PTP->PTPTTLR = LowValue;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : ETH_GetPTPRegister\r
+* Desciption : Get the specified ETHERNET PTP register value.\r
+* Input : - ETH_PTPReg: specifies the ETHERNET PTP register.\r
+* This parameter can be one of the following values:\r
+* - ETH_PTPTSCR : Sub-Second Increment Register\r
+* - ETH_PTPSSIR : Sub-Second Increment Register\r
+* - ETH_PTPTSHR : Time Stamp High Register\r
+* - ETH_PTPTSLR : Time Stamp Low Register\r
+* - ETH_PTPTSHUR : Time Stamp High Update Register\r
+* - ETH_PTPTSLUR : Time Stamp Low Update Register\r
+* - ETH_PTPTSAR : Time Stamp Addend Register\r
+* - ETH_PTPTTHR : Target Time High Register\r
+* - ETH_PTPTTLR : Target Time Low Register\r
+* Output : None\r
+* Return : The value of ETHERNET PTP Register value.\r
+*******************************************************************************/\r
+u32 ETH_GetPTPRegister(u32 ETH_PTPReg)\r
+{\r
+ /* Check the parameters */\r
+ eth_assert_param(IS_ETH_PTP_REGISTER(ETH_PTPReg));\r
+\r
+ /* Return the selected register value */\r
+ return (*(vu32 *)(ETH_MAC_BASE + ETH_PTPReg));\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : ETH_DMAPTPTxDescChainInit\r
+* Desciption : Initializes the DMA Tx descriptors in chain mode with PTP.\r
+* Input : - DMATxDescTab: Pointer on the first Tx desc list\r
+* - DMAPTPTxDescTab: Pointer on the first PTP Tx desc list\r
+* - TxBuff: Pointer on the first TxBuffer list\r
+* - TxBuffCount: Number of the used Tx desc in the list\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void ETH_DMAPTPTxDescChainInit(ETH_DMADESCTypeDef *DMATxDescTab, ETH_DMADESCTypeDef *DMAPTPTxDescTab, u8* TxBuff, u32 TxBuffCount)\r
+{\r
+ u32 i = 0;\r
+ ETH_DMADESCTypeDef *DMATxDesc;\r
+\r
+ /* Set the DMATxDescToSet pointer with the first one of the DMATxDescTab list */\r
+ DMATxDescToSet = DMATxDescTab;\r
+ DMAPTPTxDescToSet = DMAPTPTxDescTab;\r
+\r
+ /* Fill each DMATxDesc descriptor with the right values */\r
+ for(i=0; i < TxBuffCount; i++)\r
+ {\r
+ /* Get the pointer on the ith member of the Tx Desc list */\r
+ DMATxDesc = DMATxDescTab+i;\r
+\r
+ /* Set Second Address Chained bit and enable PTP */\r
+ DMATxDesc->Status = ETH_DMATxDesc_TCH | ETH_DMATxDesc_TTSE;\r
+\r
+ /* Set Buffer1 address pointer */\r
+ DMATxDesc->Buffer1Addr =(u32)(&TxBuff[i*ETH_MAX_PACKET_SIZE]);\r
+\r
+ /* Initialize the next descriptor with the Next Desciptor Polling Enable */\r
+ if(i < (TxBuffCount-1))\r
+ {\r
+ /* Set next descriptor address register with next descriptor base address */\r
+ DMATxDesc->Buffer2NextDescAddr = (u32)(DMATxDescTab+i+1);\r
+ }\r
+ else\r
+ {\r
+ /* For last descriptor, set next descriptor address register equal to the first descriptor base address */\r
+ DMATxDesc->Buffer2NextDescAddr = (u32) DMATxDescTab;\r
+ }\r
+\r
+ /* make DMAPTPTxDescTab points to the same addresses as DMATxDescTab */\r
+ (&DMAPTPTxDescTab[i])->Buffer1Addr = DMATxDesc->Buffer1Addr;\r
+ (&DMAPTPTxDescTab[i])->Buffer2NextDescAddr = DMATxDesc->Buffer2NextDescAddr;\r
+ }\r
+\r
+ /* Store on the last DMAPTPTxDescTab desc status record the first list address */\r
+ (&DMAPTPTxDescTab[i-1])->Status = (u32) DMAPTPTxDescTab;\r
+\r
+ /* Set Transmit Desciptor List Address Register */\r
+ ETH_DMA->DMATDLAR = (u32) DMATxDescTab;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : ETH_DMAPTPRxDescChainInit\r
+* Desciption : Initializes the DMA Rx descriptors in chain mode.\r
+* Input : - DMARxDescTab: Pointer on the first Rx desc list\r
+* - DMAPTPRxDescTab: Pointer on the first PTP Rx desc list\r
+* - RxBuff: Pointer on the first RxBuffer list\r
+* - RxBuffCount: Number of the used Rx desc in the list\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void ETH_DMAPTPRxDescChainInit(ETH_DMADESCTypeDef *DMARxDescTab, ETH_DMADESCTypeDef *DMAPTPRxDescTab, u8 *RxBuff, u32 RxBuffCount)\r
+{\r
+ u32 i = 0;\r
+ ETH_DMADESCTypeDef *DMARxDesc;\r
+\r
+ /* Set the DMARxDescToGet pointer with the first one of the DMARxDescTab list */\r
+ DMARxDescToGet = DMARxDescTab;\r
+ DMAPTPRxDescToGet = DMAPTPRxDescTab;\r
+\r
+ /* Fill each DMARxDesc descriptor with the right values */\r
+ for(i=0; i < RxBuffCount; i++)\r
+ {\r
+ /* Get the pointer on the ith member of the Rx Desc list */\r
+ DMARxDesc = DMARxDescTab+i;\r
+\r
+ /* Set Own bit of the Rx descriptor Status */\r
+ DMARxDesc->Status = ETH_DMARxDesc_OWN;\r
+\r
+ /* Set Buffer1 size and Second Address Chained bit */\r
+ DMARxDesc->ControlBufferSize = ETH_DMARxDesc_RCH | (u32)ETH_MAX_PACKET_SIZE;\r
+\r
+ /* Set Buffer1 address pointer */\r
+ DMARxDesc->Buffer1Addr = (u32)(&RxBuff[i*ETH_MAX_PACKET_SIZE]);\r
+\r
+ /* Initialize the next descriptor with the Next Desciptor Polling Enable */\r
+ if(i < (RxBuffCount-1))\r
+ {\r
+ /* Set next descriptor address register with next descriptor base address */\r
+ DMARxDesc->Buffer2NextDescAddr = (u32)(DMARxDescTab+i+1);\r
+ }\r
+ else\r
+ {\r
+ /* For last descriptor, set next descriptor address register equal to the first descriptor base address */\r
+ DMARxDesc->Buffer2NextDescAddr = (u32)(DMARxDescTab);\r
+ }\r
+\r
+ /* Make DMAPTPRxDescTab points to the same addresses as DMARxDescTab */\r
+ (&DMAPTPRxDescTab[i])->Buffer1Addr = DMARxDesc->Buffer1Addr;\r
+ (&DMAPTPRxDescTab[i])->Buffer2NextDescAddr = DMARxDesc->Buffer2NextDescAddr;\r
+ }\r
+\r
+ /* Store on the last DMAPTPRxDescTab desc status record the first list address */\r
+ (&DMAPTPRxDescTab[i-1])->Status = (u32) DMAPTPRxDescTab;\r
+\r
+ /* Set Receive Desciptor List Address Register */\r
+ ETH_DMA->DMARDLAR = (u32) DMARxDescTab;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : ETH_HandlePTPTxPkt\r
+* Desciption : Transmits a packet, from application buffer, pointed by ppkt with\r
+* Time Stamp values.\r
+* Input : - ppkt: pointer to application packet Buffer.\r
+* - FrameLength: Tx Packet size.\r
+* - PTPTxTab: Pointer on the first PTP Tx table to store Time stamp values.\r
+* Output : None\r
+* Return : ETH_ERROR: in case of Tx desc owned by DMA\r
+* ETH_SUCCESS: for correct transmission\r
+*******************************************************************************/\r
+u32 ETH_HandlePTPTxPkt(u8 *ppkt, u16 FrameLength, u32 *PTPTxTab)\r
+{\r
+ u32 offset = 0, timeout = 0;\r
+\r
+ /* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */\r
+ if((DMATxDescToSet->Status & ETH_DMATxDesc_OWN) != (u32)RESET)\r
+ {\r
+ /* Return ERROR: OWN bit set */\r
+ return ETH_ERROR;\r
+ }\r
+\r
+ /* Copy the frame to be sent into memory pointed by the current ETHERNET DMA Tx descriptor */\r
+ for(offset=0; offset<FrameLength; offset++)\r
+ {\r
+ (*(vu8 *)((DMAPTPTxDescToSet->Buffer1Addr) + offset)) = (*(ppkt + offset));\r
+ }\r
+\r
+ /* Setting the Frame Length: bits[12:0] */\r
+ DMATxDescToSet->ControlBufferSize = (FrameLength & (u32)0x1FFF);\r
+\r
+ /* Setting the last segment and first segment bits (in this case a frame is transmitted in one descriptor) */\r
+ DMATxDescToSet->Status |= ETH_DMATxDesc_LS | ETH_DMATxDesc_FS;\r
+\r
+ /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */\r
+ DMATxDescToSet->Status |= ETH_DMATxDesc_OWN;\r
+\r
+ /* When Tx Buffer unavailable flag is set: clear it and resume transmission */\r
+ if ((ETH_DMA->DMASR & ETH_DMASR_TBUS) != (u32)RESET)\r
+ {\r
+ /* Clear TBUS ETHERNET DMA flag */\r
+ ETH_DMA->DMASR = ETH_DMASR_TBUS;\r
+ /* Resume DMA transmission*/\r
+ ETH_DMA->DMATPDR = 0;\r
+ }\r
+\r
+ /* Wait for ETH_DMATxDesc_TTSS flag to be set */\r
+ do\r
+ {\r
+ timeout++;\r
+ } while (!(DMATxDescToSet->Status & ETH_DMATxDesc_TTSS) && (timeout < 0xFFFF));\r
+\r
+ /* Return ERROR in case of timeout */\r
+ if(timeout == PHY_READ_TO)\r
+ {\r
+ return ETH_ERROR;\r
+ }\r
+\r
+ *PTPTxTab++ = DMATxDescToSet->Buffer1Addr;\r
+ *PTPTxTab = DMATxDescToSet->Buffer2NextDescAddr;\r
+\r
+ /* Update the ENET DMA current descriptor */\r
+ /* Chained Mode */\r
+ if((DMATxDescToSet->Status & ETH_DMATxDesc_TCH) != (u32)RESET)\r
+ {\r
+ /* Selects the next DMA Tx descriptor list for next buffer read */\r
+ DMATxDescToSet = (ETH_DMADESCTypeDef*) (DMAPTPTxDescToSet->Buffer2NextDescAddr);\r
+\r
+ if(DMAPTPTxDescToSet->Status != 0)\r
+ {\r
+ DMAPTPTxDescToSet = (ETH_DMADESCTypeDef*) (DMAPTPTxDescToSet->Status);\r
+ }\r
+ else\r
+ {\r
+ DMAPTPTxDescToSet++;\r
+ }\r
+ }\r
+ else /* Ring Mode */\r
+ {\r
+ if((DMATxDescToSet->Status & ETH_DMATxDesc_TER) != (u32)RESET)\r
+ {\r
+ /* Selects the next DMA Tx descriptor list for next buffer read: this will\r
+ be the first Tx descriptor in this case */\r
+ DMATxDescToSet = (ETH_DMADESCTypeDef*) (ETH_DMA->DMATDLAR);\r
+ DMAPTPTxDescToSet = (ETH_DMADESCTypeDef*) (ETH_DMA->DMATDLAR);\r
+ }\r
+ else\r
+ {\r
+ /* Selects the next DMA Tx descriptor list for next buffer read */\r
+ DMATxDescToSet = (ETH_DMADESCTypeDef*) ((u32)DMATxDescToSet + 0x10 + ((ETH_DMA->DMABMR & ETH_DMABMR_DSL) >> 2));\r
+ DMAPTPTxDescToSet = (ETH_DMADESCTypeDef*) ((u32)DMAPTPTxDescToSet + 0x10 + ((ETH_DMA->DMABMR & ETH_DMABMR_DSL) >> 2));\r
+ }\r
+ }\r
+\r
+ /* Return SUCCESS */\r
+ return ETH_SUCCESS;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : ETH_HandlePTPRxPkt\r
+* Desciption : Receives a packet and copies it to memory pointed by ppkt with\r
+* Time Stamp values.\r
+* Input : - PTPRxTab: Pointer on the first PTP Rx table to store Time stamp values.\r
+* Output : ppkt: pointer on application receive buffer.\r
+* Return : ETH_ERROR: if there is error in reception\r
+* Received packet size: if packet reception is correct\r
+*******************************************************************************/\r
+u32 ETH_HandlePTPRxPkt(u8 *ppkt, u32 *PTPRxTab)\r
+{\r
+ u32 offset = 0, FrameLength = 0;\r
+\r
+ /* Check if the descriptor is owned by the ENET or CPU */\r
+ if((DMARxDescToGet->Status & ETH_DMARxDesc_OWN) != (u32)RESET)\r
+ {\r
+ /* Return error: OWN bit set */\r
+ return ETH_ERROR;\r
+ }\r
+\r
+ if(((DMARxDescToGet->Status & ETH_DMARxDesc_ES) == (u32)RESET) &&\r
+ ((DMARxDescToGet->Status & ETH_DMARxDesc_LS) != (u32)RESET) &&\r
+ ((DMARxDescToGet->Status & ETH_DMARxDesc_FS) != (u32)RESET))\r
+ {\r
+ /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */\r
+ FrameLength = ((DMARxDescToGet->Status & ETH_DMARxDesc_FL) >> ETH_DMARxDesc_FrameLengthShift) - 4;\r
+\r
+ /* Copy the received frame into buffer from memory pointed by the current ETHERNET DMA Rx descriptor */\r
+ for(offset=0; offset<FrameLength; offset++)\r
+ {\r
+ (*(ppkt + offset)) = (*(vu8 *)((DMAPTPRxDescToGet->Buffer1Addr) + offset));\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Return ERROR */\r
+ FrameLength = ETH_ERROR;\r
+ }\r
+\r
+ /* When Rx Buffer unavailable flag is set: clear it and resume reception */\r
+ if ((ETH_DMA->DMASR & ETH_DMASR_RBUS) != (u32)RESET)\r
+ {\r
+ /* Clear RBUS ETHERNET DMA flag */\r
+ ETH_DMA->DMASR = ETH_DMASR_RBUS;\r
+ /* Resume DMA reception */\r
+ ETH_DMA->DMARPDR = 0;\r
+ }\r
+\r
+ *PTPRxTab++ = DMARxDescToGet->Buffer1Addr;\r
+ *PTPRxTab = DMARxDescToGet->Buffer2NextDescAddr;\r
+\r
+ /* Set Own bit of the Rx descriptor Status: gives the buffer back to ETHERNET DMA */\r
+ DMARxDescToGet->Status |= ETH_DMARxDesc_OWN;\r
+\r
+ /* Update the ETHERNET DMA global Rx descriptor with next Rx decriptor */\r
+ /* Chained Mode */\r
+ if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RCH) != (u32)RESET)\r
+ {\r
+ /* Selects the next DMA Rx descriptor list for next buffer read */\r
+ DMARxDescToGet = (ETH_DMADESCTypeDef*) (DMAPTPRxDescToGet->Buffer2NextDescAddr);\r
+\r
+ if(DMAPTPRxDescToGet->Status != 0)\r
+ {\r
+ DMAPTPRxDescToGet = (ETH_DMADESCTypeDef*) (DMAPTPRxDescToGet->Status);\r
+ }\r
+ else\r
+ {\r
+ DMAPTPRxDescToGet++;\r
+ }\r
+ }\r
+ else /* Ring Mode */\r
+ {\r
+ if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RER) != (u32)RESET)\r
+ {\r
+ /* Selects the first DMA Rx descriptor for next buffer to read: last Rx descriptor was used */\r
+ DMARxDescToGet = (ETH_DMADESCTypeDef*) (ETH_DMA->DMARDLAR);\r
+ }\r
+ else\r
+ {\r
+ /* Selects the next DMA Rx descriptor list for next buffer to read */\r
+ DMARxDescToGet = (ETH_DMADESCTypeDef*) ((u32)DMARxDescToGet + 0x10 + ((ETH_DMA->DMABMR & ETH_DMABMR_DSL) >> 2));\r
+ }\r
+ }\r
+\r
+ /* Return Frame Length/ERROR */\r
+ return (FrameLength);\r
+}\r
+\r
+#endif /* _ETH_PTP */\r
+\r
+/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/\r
projects / freertos / commitdiff