Global\r
GlobalSection(SolutionConfigurationPlatforms) = preSolution\r
Debug|ARM = Debug|ARM\r
- Release|ARM = Release|ARM\r
EndGlobalSection\r
GlobalSection(ProjectConfigurationPlatforms) = postSolution\r
{3D8959CD-73CA-4147-9C1B-CFCF2EE40326}.Debug|ARM.ActiveCfg = Debug|ARM\r
{3D8959CD-73CA-4147-9C1B-CFCF2EE40326}.Debug|ARM.Build.0 = Debug|ARM\r
- {3D8959CD-73CA-4147-9C1B-CFCF2EE40326}.Release|ARM.ActiveCfg = Release|ARM\r
- {3D8959CD-73CA-4147-9C1B-CFCF2EE40326}.Release|ARM.Build.0 = Release|ARM\r
EndGlobalSection\r
GlobalSection(SolutionProperties) = preSolution\r
HideSolutionNode = FALSE\r
<AsfVersion>3.1.3</AsfVersion>\r
<AsfFrameworkConfig>\r
<framework-data>\r
- <options>\r
- <option id="common.applications.user_application" value="Add" config="" content-id="Atmel.ASF" />\r
- <option id="common.boards" value="Add" config="" content-id="Atmel.ASF" />\r
- <option id="common.services.basic.gpio" value="Add" config="" content-id="Atmel.ASF" />\r
- <option id="sam.drivers.pio" value="Add" config="" content-id="Atmel.ASF" />\r
- <option id="sam.utils.cmsis.sam4s.source.template" value="Add" config="" content-id="Atmel.ASF" />\r
- </options>\r
- <configurations />\r
- <files>\r
- <file framework="" version="3.1.3" path="src/asf.h" source="./common/applications/user_application/sam4s16c_sam4s_ek/as5_arm_template/asf.h" changed="False" content-id="Atmel.ASF" />\r
- <file framework="" version="3.1.3" path="src/main.c" source="common/applications/user_application/main.c" changed="False" content-id="Atmel.ASF" />\r
- <file framework="" version="3.1.3" path="src/config/conf_board.h" source="common/applications/user_application/sam4s16c_sam4s_ek/conf_board.h" changed="False" content-id="Atmel.ASF" />\r
- <file framework="" version="3.1.3" path="src/asf/common/boards/board.h" source="common/boards/board.h" changed="False" content-id="Atmel.ASF" />\r
- <file framework="" version="3.1.3" path="src/asf/common/services/gpio/gpio.h" source="common/services/gpio/gpio.h" changed="False" content-id="Atmel.ASF" />\r
- <file framework="" version="3.1.3" path="src/asf/common/services/gpio/sam_ioport/sam_gpio.h" source="common/services/gpio/sam_ioport/sam_gpio.h" changed="False" content-id="Atmel.ASF" />\r
- <file framework="" version="3.1.3" path="src/asf/common/utils/interrupt.h" source="common/utils/interrupt.h" changed="False" content-id="Atmel.ASF" />\r
- <file framework="" version="3.1.3" path="src/asf/common/utils/interrupt/interrupt_sam_nvic.c" source="common/utils/interrupt/interrupt_sam_nvic.c" changed="False" content-id="Atmel.ASF" />\r
- <file framework="" version="3.1.3" path="src/asf/common/utils/interrupt/interrupt_sam_nvic.h" source="common/utils/interrupt/interrupt_sam_nvic.h" changed="False" content-id="Atmel.ASF" />\r
- <file framework="" version="3.1.3" path="src/asf/sam/boards/sam4s_ek/init.c" source="sam/boards/sam4s_ek/init.c" changed="False" content-id="Atmel.ASF" />\r
- <file framework="" version="3.1.3" path="src/asf/sam/boards/sam4s_ek/sam4s_ek.h" source="sam/boards/sam4s_ek/sam4s_ek.h" changed="False" content-id="Atmel.ASF" />\r
- <file framework="" version="3.1.3" path="src/asf/sam/drivers/pio/pio.c" source="sam/drivers/pio/pio.c" changed="False" content-id="Atmel.ASF" />\r
- <file framework="" version="3.1.3" path="src/asf/sam/drivers/pio/pio.h" source="sam/drivers/pio/pio.h" changed="False" content-id="Atmel.ASF" />\r
- <file framework="" version="3.1.3" path="src/asf/sam/drivers/pio/pio_handler.c" source="sam/drivers/pio/pio_handler.c" changed="False" content-id="Atmel.ASF" />\r
- <file framework="" version="3.1.3" path="src/asf/sam/drivers/pio/pio_handler.h" source="sam/drivers/pio/pio_handler.h" changed="False" content-id="Atmel.ASF" />\r
- <file framework="" version="3.1.3" path="src/asf/sam/utils/cmsis/sam4s/include/component/component_acc.h" source="sam/utils/cmsis/sam4s/include/component/component_acc.h" changed="False" content-id="Atmel.ASF" />\r
- <file framework="" version="3.1.3" path="src/asf/sam/utils/cmsis/sam4s/include/component/component_adc.h" source="sam/utils/cmsis/sam4s/include/component/component_adc.h" changed="False" content-id="Atmel.ASF" />\r
- <file framework="" version="3.1.3" path="src/asf/sam/utils/cmsis/sam4s/include/component/component_chipid.h" source="sam/utils/cmsis/sam4s/include/component/component_chipid.h" changed="False" content-id="Atmel.ASF" />\r
- <file framework="" version="3.1.3" path="src/asf/sam/utils/cmsis/sam4s/include/component/component_crccu.h" source="sam/utils/cmsis/sam4s/include/component/component_crccu.h" changed="False" content-id="Atmel.ASF" />\r
- <file framework="" version="3.1.3" path="src/asf/sam/utils/cmsis/sam4s/include/component/component_dacc.h" source="sam/utils/cmsis/sam4s/include/component/component_dacc.h" changed="False" content-id="Atmel.ASF" />\r
- <file framework="" version="3.1.3" path="src/asf/sam/utils/cmsis/sam4s/include/component/component_efc.h" source="sam/utils/cmsis/sam4s/include/component/component_efc.h" changed="False" content-id="Atmel.ASF" />\r
- <file framework="" version="3.1.3" path="src/asf/sam/utils/cmsis/sam4s/include/component/component_gpbr.h" source="sam/utils/cmsis/sam4s/include/component/component_gpbr.h" changed="False" content-id="Atmel.ASF" />\r
- <file framework="" version="3.1.3" path="src/asf/sam/utils/cmsis/sam4s/include/component/component_hsmci.h" source="sam/utils/cmsis/sam4s/include/component/component_hsmci.h" changed="False" content-id="Atmel.ASF" />\r
- <file framework="" version="3.1.3" path="src/asf/sam/utils/cmsis/sam4s/include/component/component_matrix.h" source="sam/utils/cmsis/sam4s/include/component/component_matrix.h" changed="False" content-id="Atmel.ASF" />\r
- <file framework="" version="3.1.3" path="src/asf/sam/utils/cmsis/sam4s/include/component/component_pdc.h" source="sam/utils/cmsis/sam4s/include/component/component_pdc.h" changed="False" content-id="Atmel.ASF" />\r
- <file framework="" version="3.1.3" path="src/asf/sam/utils/cmsis/sam4s/include/component/component_pio.h" source="sam/utils/cmsis/sam4s/include/component/component_pio.h" changed="False" content-id="Atmel.ASF" />\r
- <file framework="" version="3.1.3" path="src/asf/sam/utils/cmsis/sam4s/include/component/component_pmc.h" source="sam/utils/cmsis/sam4s/include/component/component_pmc.h" changed="False" content-id="Atmel.ASF" />\r
- <file framework="" version="3.1.3" path="src/asf/sam/utils/cmsis/sam4s/include/component/component_pwm.h" source="sam/utils/cmsis/sam4s/include/component/component_pwm.h" changed="False" content-id="Atmel.ASF" />\r
- <file framework="" version="3.1.3" path="src/asf/sam/utils/cmsis/sam4s/include/component/component_rstc.h" source="sam/utils/cmsis/sam4s/include/component/component_rstc.h" changed="False" content-id="Atmel.ASF" />\r
- <file framework="" version="3.1.3" path="src/asf/sam/utils/cmsis/sam4s/include/component/component_rtc.h" source="sam/utils/cmsis/sam4s/include/component/component_rtc.h" changed="False" content-id="Atmel.ASF" />\r
- <file framework="" version="3.1.3" path="src/asf/sam/utils/cmsis/sam4s/include/component/component_rtt.h" source="sam/utils/cmsis/sam4s/include/component/component_rtt.h" changed="False" content-id="Atmel.ASF" />\r
- <file framework="" version="3.1.3" path="src/asf/sam/utils/cmsis/sam4s/include/component/component_smc.h" source="sam/utils/cmsis/sam4s/include/component/component_smc.h" changed="False" content-id="Atmel.ASF" />\r
- <file framework="" version="3.1.3" path="src/asf/sam/utils/cmsis/sam4s/include/component/component_spi.h" source="sam/utils/cmsis/sam4s/include/component/component_spi.h" changed="False" content-id="Atmel.ASF" />\r
- <file framework="" version="3.1.3" path="src/asf/sam/utils/cmsis/sam4s/include/component/component_ssc.h" source="sam/utils/cmsis/sam4s/include/component/component_ssc.h" changed="False" content-id="Atmel.ASF" />\r
- <file framework="" version="3.1.3" path="src/asf/sam/utils/cmsis/sam4s/include/component/component_supc.h" source="sam/utils/cmsis/sam4s/include/component/component_supc.h" changed="False" content-id="Atmel.ASF" />\r
- <file framework="" version="3.1.3" path="src/asf/sam/utils/cmsis/sam4s/include/component/component_tc.h" source="sam/utils/cmsis/sam4s/include/component/component_tc.h" changed="False" content-id="Atmel.ASF" />\r
- <file framework="" version="3.1.3" path="src/asf/sam/utils/cmsis/sam4s/include/component/component_twi.h" source="sam/utils/cmsis/sam4s/include/component/component_twi.h" changed="False" content-id="Atmel.ASF" />\r
- <file framework="" version="3.1.3" path="src/asf/sam/utils/cmsis/sam4s/include/component/component_uart.h" source="sam/utils/cmsis/sam4s/include/component/component_uart.h" changed="False" content-id="Atmel.ASF" />\r
- <file framework="" version="3.1.3" path="src/asf/sam/utils/cmsis/sam4s/include/component/component_udp.h" source="sam/utils/cmsis/sam4s/include/component/component_udp.h" changed="False" content-id="Atmel.ASF" />\r
- <file framework="" version="3.1.3" path="src/asf/sam/utils/cmsis/sam4s/include/component/component_usart.h" source="sam/utils/cmsis/sam4s/include/component/component_usart.h" changed="False" content-id="Atmel.ASF" />\r
- <file framework="" version="3.1.3" path="src/asf/sam/utils/cmsis/sam4s/include/component/component_wdt.h" source="sam/utils/cmsis/sam4s/include/component/component_wdt.h" changed="False" content-id="Atmel.ASF" />\r
- <file framework="" version="3.1.3" path="src/asf/sam/utils/cmsis/sam4s/include/instance/instance_acc.h" source="sam/utils/cmsis/sam4s/include/instance/instance_acc.h" changed="False" content-id="Atmel.ASF" />\r
- <file framework="" version="3.1.3" path="src/asf/sam/utils/cmsis/sam4s/include/instance/instance_adc.h" source="sam/utils/cmsis/sam4s/include/instance/instance_adc.h" changed="False" content-id="Atmel.ASF" />\r
- <file framework="" version="3.1.3" path="src/asf/sam/utils/cmsis/sam4s/include/instance/instance_chipid.h" source="sam/utils/cmsis/sam4s/include/instance/instance_chipid.h" changed="False" content-id="Atmel.ASF" />\r
- <file framework="" version="3.1.3" path="src/asf/sam/utils/cmsis/sam4s/include/instance/instance_crccu.h" source="sam/utils/cmsis/sam4s/include/instance/instance_crccu.h" changed="False" content-id="Atmel.ASF" />\r
- <file framework="" version="3.1.3" path="src/asf/sam/utils/cmsis/sam4s/include/instance/instance_dacc.h" source="sam/utils/cmsis/sam4s/include/instance/instance_dacc.h" changed="False" content-id="Atmel.ASF" />\r
- <file framework="" version="3.1.3" path="src/asf/sam/utils/cmsis/sam4s/include/instance/instance_efc.h" source="sam/utils/cmsis/sam4s/include/instance/instance_efc.h" changed="False" content-id="Atmel.ASF" />\r
- <file framework="" version="3.1.3" path="src/asf/sam/utils/cmsis/sam4s/include/instance/instance_gpbr.h" source="sam/utils/cmsis/sam4s/include/instance/instance_gpbr.h" changed="False" content-id="Atmel.ASF" />\r
- <file framework="" version="3.1.3" path="src/asf/sam/utils/cmsis/sam4s/include/instance/instance_hsmci.h" source="sam/utils/cmsis/sam4s/include/instance/instance_hsmci.h" changed="False" content-id="Atmel.ASF" />\r
- <file framework="" version="3.1.3" path="src/asf/sam/utils/cmsis/sam4s/include/instance/instance_matrix.h" source="sam/utils/cmsis/sam4s/include/instance/instance_matrix.h" changed="False" content-id="Atmel.ASF" />\r
- <file framework="" version="3.1.3" path="src/asf/sam/utils/cmsis/sam4s/include/instance/instance_pioa.h" source="sam/utils/cmsis/sam4s/include/instance/instance_pioa.h" changed="False" content-id="Atmel.ASF" />\r
- <file framework="" version="3.1.3" path="src/asf/sam/utils/cmsis/sam4s/include/instance/instance_piob.h" source="sam/utils/cmsis/sam4s/include/instance/instance_piob.h" changed="False" content-id="Atmel.ASF" />\r
- <file framework="" version="3.1.3" path="src/asf/sam/utils/cmsis/sam4s/include/instance/instance_pioc.h" source="sam/utils/cmsis/sam4s/include/instance/instance_pioc.h" changed="False" content-id="Atmel.ASF" />\r
- <file framework="" version="3.1.3" path="src/asf/sam/utils/cmsis/sam4s/include/instance/instance_pmc.h" source="sam/utils/cmsis/sam4s/include/instance/instance_pmc.h" changed="False" content-id="Atmel.ASF" />\r
- <file framework="" version="3.1.3" path="src/asf/sam/utils/cmsis/sam4s/include/instance/instance_pwm.h" source="sam/utils/cmsis/sam4s/include/instance/instance_pwm.h" changed="False" content-id="Atmel.ASF" />\r
- <file framework="" version="3.1.3" path="src/asf/sam/utils/cmsis/sam4s/include/instance/instance_rstc.h" source="sam/utils/cmsis/sam4s/include/instance/instance_rstc.h" changed="False" content-id="Atmel.ASF" />\r
- <file framework="" version="3.1.3" path="src/asf/sam/utils/cmsis/sam4s/include/instance/instance_rtc.h" source="sam/utils/cmsis/sam4s/include/instance/instance_rtc.h" changed="False" content-id="Atmel.ASF" />\r
- <file framework="" version="3.1.3" path="src/asf/sam/utils/cmsis/sam4s/include/instance/instance_rtt.h" source="sam/utils/cmsis/sam4s/include/instance/instance_rtt.h" changed="False" content-id="Atmel.ASF" />\r
- <file framework="" version="3.1.3" path="src/asf/sam/utils/cmsis/sam4s/include/instance/instance_smc.h" source="sam/utils/cmsis/sam4s/include/instance/instance_smc.h" changed="False" content-id="Atmel.ASF" />\r
- <file framework="" version="3.1.3" path="src/asf/sam/utils/cmsis/sam4s/include/instance/instance_spi.h" source="sam/utils/cmsis/sam4s/include/instance/instance_spi.h" changed="False" content-id="Atmel.ASF" />\r
- <file framework="" version="3.1.3" path="src/asf/sam/utils/cmsis/sam4s/include/instance/instance_ssc.h" source="sam/utils/cmsis/sam4s/include/instance/instance_ssc.h" changed="False" content-id="Atmel.ASF" />\r
- <file framework="" version="3.1.3" path="src/asf/sam/utils/cmsis/sam4s/include/instance/instance_supc.h" source="sam/utils/cmsis/sam4s/include/instance/instance_supc.h" changed="False" content-id="Atmel.ASF" />\r
- <file framework="" version="3.1.3" path="src/asf/sam/utils/cmsis/sam4s/include/instance/instance_tc0.h" source="sam/utils/cmsis/sam4s/include/instance/instance_tc0.h" changed="False" content-id="Atmel.ASF" />\r
- <file framework="" version="3.1.3" path="src/asf/sam/utils/cmsis/sam4s/include/instance/instance_tc1.h" source="sam/utils/cmsis/sam4s/include/instance/instance_tc1.h" changed="False" content-id="Atmel.ASF" />\r
- <file framework="" version="3.1.3" path="src/asf/sam/utils/cmsis/sam4s/include/instance/instance_twi0.h" source="sam/utils/cmsis/sam4s/include/instance/instance_twi0.h" changed="False" content-id="Atmel.ASF" />\r
- <file framework="" version="3.1.3" path="src/asf/sam/utils/cmsis/sam4s/include/instance/instance_twi1.h" source="sam/utils/cmsis/sam4s/include/instance/instance_twi1.h" changed="False" content-id="Atmel.ASF" />\r
- <file framework="" version="3.1.3" path="src/asf/sam/utils/cmsis/sam4s/include/instance/instance_uart0.h" source="sam/utils/cmsis/sam4s/include/instance/instance_uart0.h" changed="False" content-id="Atmel.ASF" />\r
- <file framework="" version="3.1.3" path="src/asf/sam/utils/cmsis/sam4s/include/instance/instance_uart1.h" source="sam/utils/cmsis/sam4s/include/instance/instance_uart1.h" changed="False" content-id="Atmel.ASF" />\r
- <file framework="" version="3.1.3" path="src/asf/sam/utils/cmsis/sam4s/include/instance/instance_udp.h" source="sam/utils/cmsis/sam4s/include/instance/instance_udp.h" changed="False" content-id="Atmel.ASF" />\r
- <file framework="" version="3.1.3" path="src/asf/sam/utils/cmsis/sam4s/include/instance/instance_usart0.h" source="sam/utils/cmsis/sam4s/include/instance/instance_usart0.h" changed="False" content-id="Atmel.ASF" />\r
- <file framework="" version="3.1.3" path="src/asf/sam/utils/cmsis/sam4s/include/instance/instance_usart1.h" source="sam/utils/cmsis/sam4s/include/instance/instance_usart1.h" changed="False" content-id="Atmel.ASF" />\r
- <file framework="" version="3.1.3" path="src/asf/sam/utils/cmsis/sam4s/include/instance/instance_wdt.h" source="sam/utils/cmsis/sam4s/include/instance/instance_wdt.h" changed="False" content-id="Atmel.ASF" />\r
- <file framework="" version="3.1.3" path="src/asf/sam/utils/cmsis/sam4s/include/pio/pio_sam4s16c.h" source="sam/utils/cmsis/sam4s/include/pio/pio_sam4s16c.h" changed="False" content-id="Atmel.ASF" />\r
- <file framework="" version="3.1.3" path="src/asf/sam/utils/cmsis/sam4s/include/sam4s.h" source="sam/utils/cmsis/sam4s/include/sam4s.h" changed="False" content-id="Atmel.ASF" />\r
- <file framework="" version="3.1.3" path="src/asf/sam/utils/cmsis/sam4s/include/sam4s16c.h" source="sam/utils/cmsis/sam4s/include/sam4s16c.h" changed="False" content-id="Atmel.ASF" />\r
- <file framework="" version="3.1.3" path="src/asf/sam/utils/cmsis/sam4s/source/templates/exceptions.c" source="sam/utils/cmsis/sam4s/source/templates/exceptions.c" changed="False" content-id="Atmel.ASF" />\r
- <file framework="" version="3.1.3" path="src/asf/sam/utils/cmsis/sam4s/source/templates/exceptions.h" source="sam/utils/cmsis/sam4s/source/templates/exceptions.h" changed="False" content-id="Atmel.ASF" />\r
- <file framework="" version="3.1.3" path="src/asf/sam/utils/cmsis/sam4s/source/templates/gcc/startup_sam4s.c" source="sam/utils/cmsis/sam4s/source/templates/gcc/startup_sam4s.c" changed="False" content-id="Atmel.ASF" />\r
- <file framework="" version="3.1.3" path="src/asf/sam/utils/cmsis/sam4s/source/templates/system_sam4s.c" source="sam/utils/cmsis/sam4s/source/templates/system_sam4s.c" changed="False" content-id="Atmel.ASF" />\r
- <file framework="" version="3.1.3" path="src/asf/sam/utils/cmsis/sam4s/source/templates/system_sam4s.h" source="sam/utils/cmsis/sam4s/source/templates/system_sam4s.h" changed="False" content-id="Atmel.ASF" />\r
- <file framework="" version="3.1.3" path="src/asf/sam/utils/compiler.h" source="sam/utils/compiler.h" changed="False" content-id="Atmel.ASF" />\r
- <file framework="" version="3.1.3" path="src/asf/sam/utils/header_files/io.h" source="sam/utils/header_files/io.h" changed="False" content-id="Atmel.ASF" />\r
- <file framework="" version="3.1.3" path="src/asf/sam/utils/linker_scripts/sam4s/sam4s16/gcc/flash.ld" source="sam/utils/linker_scripts/sam4s/sam4s16/gcc/flash.ld" changed="False" content-id="Atmel.ASF" />\r
- <file framework="" version="3.1.3" path="src/asf/sam/utils/make/Makefile.in" source="sam/utils/make/Makefile.in" changed="False" content-id="Atmel.ASF" />\r
- <file framework="" version="3.1.3" path="src/asf/sam/utils/parts.h" source="sam/utils/parts.h" changed="False" content-id="Atmel.ASF" />\r
- <file framework="" version="3.1.3" path="src/asf/sam/utils/preprocessor/mrepeat.h" source="sam/utils/preprocessor/mrepeat.h" changed="False" content-id="Atmel.ASF" />\r
- <file framework="" version="3.1.3" path="src/asf/sam/utils/preprocessor/preprocessor.h" source="sam/utils/preprocessor/preprocessor.h" changed="False" content-id="Atmel.ASF" />\r
- <file framework="" version="3.1.3" path="src/asf/sam/utils/preprocessor/stringz.h" source="sam/utils/preprocessor/stringz.h" changed="False" content-id="Atmel.ASF" />\r
- <file framework="" version="3.1.3" path="src/asf/sam/utils/preprocessor/tpaste.h" source="sam/utils/preprocessor/tpaste.h" changed="False" content-id="Atmel.ASF" />\r
- <file framework="" version="3.1.3" path="src/asf/sam/utils/status_codes.h" source="sam/utils/status_codes.h" changed="False" content-id="Atmel.ASF" />\r
- <file framework="" version="3.1.3" path="src/asf/thirdparty/CMSIS/CMSIS END USER LICENCE AGREEMENT.pdf" source="thirdparty/CMSIS/CMSIS END USER LICENCE AGREEMENT.pdf" changed="False" content-id="Atmel.ASF" />\r
- <file framework="" version="3.1.3" path="src/asf/thirdparty/CMSIS/Include/arm_math.h" source="thirdparty/CMSIS/Include/arm_math.h" changed="False" content-id="Atmel.ASF" />\r
- <file framework="" version="3.1.3" path="src/asf/thirdparty/CMSIS/Include/core_cm4.h" source="thirdparty/CMSIS/Include/core_cm4.h" changed="False" content-id="Atmel.ASF" />\r
- <file framework="" version="3.1.3" path="src/asf/thirdparty/CMSIS/Include/core_cm4_simd.h" source="thirdparty/CMSIS/Include/core_cm4_simd.h" changed="False" content-id="Atmel.ASF" />\r
- <file framework="" version="3.1.3" path="src/asf/thirdparty/CMSIS/Include/core_cmFunc.h" source="thirdparty/CMSIS/Include/core_cmFunc.h" changed="False" content-id="Atmel.ASF" />\r
- <file framework="" version="3.1.3" path="src/asf/thirdparty/CMSIS/Include/core_cmInstr.h" source="thirdparty/CMSIS/Include/core_cmInstr.h" changed="False" content-id="Atmel.ASF" />\r
- <file framework="" version="3.1.3" path="src/asf/thirdparty/CMSIS/Lib/GCC/libarm_cortexM4l_math.a" source="thirdparty/CMSIS/Lib/GCC/libarm_cortexM4l_math.a" changed="False" content-id="Atmel.ASF" />\r
- <file framework="" version="3.1.3" path="src/asf/thirdparty/CMSIS/README.txt" source="thirdparty/CMSIS/README.txt" changed="False" content-id="Atmel.ASF" />\r
- <file framework="" version="3.1.3" path="src/asf/thirdparty/CMSIS/license.txt" source="thirdparty/CMSIS/license.txt" changed="False" content-id="Atmel.ASF" />\r
- </files>\r
- <documentation help="http://asf.atmel.com/docs/3.1.3/common.applications.user_application.sam4s_ek/html/index.html" />\r
- </framework-data>\r
+ <options>\r
+ <option id="common.boards" value="Add" config="" content-id="Atmel.ASF" />\r
+ <option id="common.services.basic.clock" value="Add" config="" content-id="Atmel.ASF" />\r
+ <option id="common.services.basic.gpio" value="Add" config="" content-id="Atmel.ASF" />\r
+ <option id="sam.drivers.pio" value="Add" config="" content-id="Atmel.ASF" />\r
+ <option id="sam.drivers.usart" value="Add" config="" content-id="Atmel.ASF" />\r
+ </options>\r
+ <configurations />\r
+ <files>\r
+ <file path="src/asf.h" framework="" version="3.1.3" source="./common/applications/user_application/sam4s16c_sam4s_ek/as5_arm_template/asf.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/main.c" framework="" version="3.1.3" source="common/applications/user_application/main.c" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/config/conf_board.h" framework="" version="3.1.3" source="common/applications/user_application/sam4s16c_sam4s_ek/conf_board.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/common/boards/board.h" framework="" version="3.1.3" source="common/boards/board.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/common/services/gpio/gpio.h" framework="" version="3.1.3" source="common/services/gpio/gpio.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/common/services/gpio/sam_ioport/sam_gpio.h" framework="" version="3.1.3" source="common/services/gpio/sam_ioport/sam_gpio.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/common/utils/interrupt.h" framework="" version="3.1.3" source="common/utils/interrupt.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/common/utils/interrupt/interrupt_sam_nvic.c" framework="" version="3.1.3" source="common/utils/interrupt/interrupt_sam_nvic.c" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/common/utils/interrupt/interrupt_sam_nvic.h" framework="" version="3.1.3" source="common/utils/interrupt/interrupt_sam_nvic.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/boards/sam4s_ek/init.c" framework="" version="3.1.3" source="sam/boards/sam4s_ek/init.c" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/boards/sam4s_ek/sam4s_ek.h" framework="" version="3.1.3" source="sam/boards/sam4s_ek/sam4s_ek.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/drivers/pio/pio.c" framework="" version="3.1.3" source="sam/drivers/pio/pio.c" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/drivers/pio/pio.h" framework="" version="3.1.3" source="sam/drivers/pio/pio.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/drivers/pio/pio_handler.c" framework="" version="3.1.3" source="sam/drivers/pio/pio_handler.c" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/drivers/pio/pio_handler.h" framework="" version="3.1.3" source="sam/drivers/pio/pio_handler.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam4s/include/component/component_acc.h" framework="" version="3.1.3" source="sam/utils/cmsis/sam4s/include/component/component_acc.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam4s/include/component/component_adc.h" framework="" version="3.1.3" source="sam/utils/cmsis/sam4s/include/component/component_adc.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam4s/include/component/component_chipid.h" framework="" version="3.1.3" source="sam/utils/cmsis/sam4s/include/component/component_chipid.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam4s/include/component/component_crccu.h" framework="" version="3.1.3" source="sam/utils/cmsis/sam4s/include/component/component_crccu.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam4s/include/component/component_dacc.h" framework="" version="3.1.3" source="sam/utils/cmsis/sam4s/include/component/component_dacc.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam4s/include/component/component_efc.h" framework="" version="3.1.3" source="sam/utils/cmsis/sam4s/include/component/component_efc.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam4s/include/component/component_gpbr.h" framework="" version="3.1.3" source="sam/utils/cmsis/sam4s/include/component/component_gpbr.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam4s/include/component/component_hsmci.h" framework="" version="3.1.3" source="sam/utils/cmsis/sam4s/include/component/component_hsmci.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam4s/include/component/component_matrix.h" framework="" version="3.1.3" source="sam/utils/cmsis/sam4s/include/component/component_matrix.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam4s/include/component/component_pdc.h" framework="" version="3.1.3" source="sam/utils/cmsis/sam4s/include/component/component_pdc.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam4s/include/component/component_pio.h" framework="" version="3.1.3" source="sam/utils/cmsis/sam4s/include/component/component_pio.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam4s/include/component/component_pmc.h" framework="" version="3.1.3" source="sam/utils/cmsis/sam4s/include/component/component_pmc.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam4s/include/component/component_pwm.h" framework="" version="3.1.3" source="sam/utils/cmsis/sam4s/include/component/component_pwm.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam4s/include/component/component_rstc.h" framework="" version="3.1.3" source="sam/utils/cmsis/sam4s/include/component/component_rstc.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam4s/include/component/component_rtc.h" framework="" version="3.1.3" source="sam/utils/cmsis/sam4s/include/component/component_rtc.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam4s/include/component/component_rtt.h" framework="" version="3.1.3" source="sam/utils/cmsis/sam4s/include/component/component_rtt.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam4s/include/component/component_smc.h" framework="" version="3.1.3" source="sam/utils/cmsis/sam4s/include/component/component_smc.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam4s/include/component/component_spi.h" framework="" version="3.1.3" source="sam/utils/cmsis/sam4s/include/component/component_spi.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam4s/include/component/component_ssc.h" framework="" version="3.1.3" source="sam/utils/cmsis/sam4s/include/component/component_ssc.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam4s/include/component/component_supc.h" framework="" version="3.1.3" source="sam/utils/cmsis/sam4s/include/component/component_supc.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam4s/include/component/component_tc.h" framework="" version="3.1.3" source="sam/utils/cmsis/sam4s/include/component/component_tc.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam4s/include/component/component_twi.h" framework="" version="3.1.3" source="sam/utils/cmsis/sam4s/include/component/component_twi.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam4s/include/component/component_uart.h" framework="" version="3.1.3" source="sam/utils/cmsis/sam4s/include/component/component_uart.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam4s/include/component/component_udp.h" framework="" version="3.1.3" source="sam/utils/cmsis/sam4s/include/component/component_udp.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam4s/include/component/component_usart.h" framework="" version="3.1.3" source="sam/utils/cmsis/sam4s/include/component/component_usart.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam4s/include/component/component_wdt.h" framework="" version="3.1.3" source="sam/utils/cmsis/sam4s/include/component/component_wdt.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam4s/include/instance/instance_acc.h" framework="" version="3.1.3" source="sam/utils/cmsis/sam4s/include/instance/instance_acc.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam4s/include/instance/instance_adc.h" framework="" version="3.1.3" source="sam/utils/cmsis/sam4s/include/instance/instance_adc.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam4s/include/instance/instance_chipid.h" framework="" version="3.1.3" source="sam/utils/cmsis/sam4s/include/instance/instance_chipid.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam4s/include/instance/instance_crccu.h" framework="" version="3.1.3" source="sam/utils/cmsis/sam4s/include/instance/instance_crccu.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam4s/include/instance/instance_dacc.h" framework="" version="3.1.3" source="sam/utils/cmsis/sam4s/include/instance/instance_dacc.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam4s/include/instance/instance_efc.h" framework="" version="3.1.3" source="sam/utils/cmsis/sam4s/include/instance/instance_efc.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam4s/include/instance/instance_gpbr.h" framework="" version="3.1.3" source="sam/utils/cmsis/sam4s/include/instance/instance_gpbr.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam4s/include/instance/instance_hsmci.h" framework="" version="3.1.3" source="sam/utils/cmsis/sam4s/include/instance/instance_hsmci.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam4s/include/instance/instance_matrix.h" framework="" version="3.1.3" source="sam/utils/cmsis/sam4s/include/instance/instance_matrix.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam4s/include/instance/instance_pioa.h" framework="" version="3.1.3" source="sam/utils/cmsis/sam4s/include/instance/instance_pioa.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam4s/include/instance/instance_piob.h" framework="" version="3.1.3" source="sam/utils/cmsis/sam4s/include/instance/instance_piob.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam4s/include/instance/instance_pioc.h" framework="" version="3.1.3" source="sam/utils/cmsis/sam4s/include/instance/instance_pioc.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam4s/include/instance/instance_pmc.h" framework="" version="3.1.3" source="sam/utils/cmsis/sam4s/include/instance/instance_pmc.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam4s/include/instance/instance_pwm.h" framework="" version="3.1.3" source="sam/utils/cmsis/sam4s/include/instance/instance_pwm.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam4s/include/instance/instance_rstc.h" framework="" version="3.1.3" source="sam/utils/cmsis/sam4s/include/instance/instance_rstc.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam4s/include/instance/instance_rtc.h" framework="" version="3.1.3" source="sam/utils/cmsis/sam4s/include/instance/instance_rtc.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam4s/include/instance/instance_rtt.h" framework="" version="3.1.3" source="sam/utils/cmsis/sam4s/include/instance/instance_rtt.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam4s/include/instance/instance_smc.h" framework="" version="3.1.3" source="sam/utils/cmsis/sam4s/include/instance/instance_smc.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam4s/include/instance/instance_spi.h" framework="" version="3.1.3" source="sam/utils/cmsis/sam4s/include/instance/instance_spi.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam4s/include/instance/instance_ssc.h" framework="" version="3.1.3" source="sam/utils/cmsis/sam4s/include/instance/instance_ssc.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam4s/include/instance/instance_supc.h" framework="" version="3.1.3" source="sam/utils/cmsis/sam4s/include/instance/instance_supc.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam4s/include/instance/instance_tc0.h" framework="" version="3.1.3" source="sam/utils/cmsis/sam4s/include/instance/instance_tc0.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam4s/include/instance/instance_tc1.h" framework="" version="3.1.3" source="sam/utils/cmsis/sam4s/include/instance/instance_tc1.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam4s/include/instance/instance_twi0.h" framework="" version="3.1.3" source="sam/utils/cmsis/sam4s/include/instance/instance_twi0.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam4s/include/instance/instance_twi1.h" framework="" version="3.1.3" source="sam/utils/cmsis/sam4s/include/instance/instance_twi1.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam4s/include/instance/instance_uart0.h" framework="" version="3.1.3" source="sam/utils/cmsis/sam4s/include/instance/instance_uart0.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam4s/include/instance/instance_uart1.h" framework="" version="3.1.3" source="sam/utils/cmsis/sam4s/include/instance/instance_uart1.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam4s/include/instance/instance_udp.h" framework="" version="3.1.3" source="sam/utils/cmsis/sam4s/include/instance/instance_udp.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam4s/include/instance/instance_usart0.h" framework="" version="3.1.3" source="sam/utils/cmsis/sam4s/include/instance/instance_usart0.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam4s/include/instance/instance_usart1.h" framework="" version="3.1.3" source="sam/utils/cmsis/sam4s/include/instance/instance_usart1.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam4s/include/instance/instance_wdt.h" framework="" version="3.1.3" source="sam/utils/cmsis/sam4s/include/instance/instance_wdt.h" changed="False" content-id="Atmel.ASF" />\r
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+ <file path="src/asf/sam/utils/cmsis/sam4s/source/templates/exceptions.c" framework="" version="3.1.3" source="sam/utils/cmsis/sam4s/source/templates/exceptions.c" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam4s/source/templates/exceptions.h" framework="" version="3.1.3" source="sam/utils/cmsis/sam4s/source/templates/exceptions.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam4s/source/templates/gcc/startup_sam4s.c" framework="" version="3.1.3" source="sam/utils/cmsis/sam4s/source/templates/gcc/startup_sam4s.c" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam4s/source/templates/system_sam4s.c" framework="" version="3.1.3" source="sam/utils/cmsis/sam4s/source/templates/system_sam4s.c" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam4s/source/templates/system_sam4s.h" framework="" version="3.1.3" source="sam/utils/cmsis/sam4s/source/templates/system_sam4s.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/compiler.h" framework="" version="3.1.3" source="sam/utils/compiler.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/header_files/io.h" framework="" version="3.1.3" source="sam/utils/header_files/io.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/linker_scripts/sam4s/sam4s16/gcc/flash.ld" framework="" version="3.1.3" source="sam/utils/linker_scripts/sam4s/sam4s16/gcc/flash.ld" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/make/Makefile.in" framework="" version="3.1.3" source="sam/utils/make/Makefile.in" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/parts.h" framework="" version="3.1.3" source="sam/utils/parts.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/preprocessor/mrepeat.h" framework="" version="3.1.3" source="sam/utils/preprocessor/mrepeat.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/preprocessor/preprocessor.h" framework="" version="3.1.3" source="sam/utils/preprocessor/preprocessor.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/preprocessor/stringz.h" framework="" version="3.1.3" source="sam/utils/preprocessor/stringz.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/preprocessor/tpaste.h" framework="" version="3.1.3" source="sam/utils/preprocessor/tpaste.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/status_codes.h" framework="" version="3.1.3" source="sam/utils/status_codes.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/thirdparty/CMSIS/CMSIS END USER LICENCE AGREEMENT.pdf" framework="" version="3.1.3" source="thirdparty/CMSIS/CMSIS END USER LICENCE AGREEMENT.pdf" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/thirdparty/CMSIS/Include/arm_math.h" framework="" version="3.1.3" source="thirdparty/CMSIS/Include/arm_math.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/thirdparty/CMSIS/Include/core_cm4.h" framework="" version="3.1.3" source="thirdparty/CMSIS/Include/core_cm4.h" changed="False" content-id="Atmel.ASF" />\r
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+ <None Include="src\asf\common\services\clock\genclk.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\common\services\clock\osc.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\common\services\clock\sam4s\genclk.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\common\services\clock\pll.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <Compile Include="src\asf\common\services\clock\sam4s\sysclk.c">\r
+ <SubType>compile</SubType>\r
+ </Compile>\r
+ <None Include="src\asf\common\services\clock\sam4s\sysclk.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\common\services\clock\sysclk.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
<Compile Include="src\asf\common\utils\interrupt\interrupt_sam_nvic.c">\r
<SubType>compile</SubType>\r
</Compile>\r
<Compile Include="src\asf\sam\drivers\pio\pio_handler.c">\r
<SubType>compile</SubType>\r
</Compile>\r
+ <Compile Include="src\asf\sam\drivers\pmc\pmc.c">\r
+ <SubType>compile</SubType>\r
+ </Compile>\r
+ <None Include="src\asf\sam\drivers\pmc\pmc.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\drivers\pmc\sleep.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
<Compile Include="src\asf\sam\utils\cmsis\sam4s\source\templates\exceptions.c">\r
<SubType>compile</SubType>\r
</Compile>\r
<Compile Include="src\Common-Demo-Source\blocktim.c">\r
<SubType>compile</SubType>\r
</Compile>\r
+ <Compile Include="src\Common-Demo-Source\comtest.c">\r
+ <SubType>compile</SubType>\r
+ </Compile>\r
<Compile Include="src\Common-Demo-Source\countsem.c">\r
<SubType>compile</SubType>\r
</Compile>\r
<Compile Include="src\Common-Demo-Source\dynamic.c">\r
<SubType>compile</SubType>\r
</Compile>\r
+ <Compile Include="src\Common-Demo-Source\flash_timer.c">\r
+ <SubType>compile</SubType>\r
+ </Compile>\r
<Compile Include="src\Common-Demo-Source\GenQTest.c">\r
<SubType>compile</SubType>\r
</Compile>\r
<Compile Include="src\Common-Demo-Source\include\blocktim.h">\r
<SubType>compile</SubType>\r
</Compile>\r
+ <Compile Include="src\Common-Demo-Source\include\comtest2.h">\r
+ <SubType>compile</SubType>\r
+ </Compile>\r
<Compile Include="src\Common-Demo-Source\include\countsem.h">\r
<SubType>compile</SubType>\r
</Compile>\r
<Compile Include="src\Common-Demo-Source\include\dynamic.h">\r
<SubType>compile</SubType>\r
</Compile>\r
+ <Compile Include="src\Common-Demo-Source\include\flash_timer.h">\r
+ <SubType>compile</SubType>\r
+ </Compile>\r
<Compile Include="src\Common-Demo-Source\include\GenQTest.h">\r
<SubType>compile</SubType>\r
</Compile>\r
<Compile Include="src\Common-Demo-Source\semtest.c">\r
<SubType>compile</SubType>\r
</Compile>\r
+ <None Include="src\config\conf_clock.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
<Compile Include="src\FreeRTOSConfig.h">\r
<SubType>compile</SubType>\r
</Compile>\r
<Folder Include="src\asf\common\" />\r
<Folder Include="src\asf\common\boards\" />\r
<Folder Include="src\asf\common\services\" />\r
+ <Folder Include="src\asf\common\services\clock\" />\r
+ <Folder Include="src\asf\common\services\clock\sam4s\" />\r
<Folder Include="src\asf\common\services\gpio\" />\r
<Folder Include="src\asf\common\services\gpio\sam_ioport\" />\r
<Folder Include="src\asf\common\utils\" />\r
<Folder Include="src\asf\sam\boards\sam4s_ek\" />\r
<Folder Include="src\asf\sam\drivers\" />\r
<Folder Include="src\asf\sam\drivers\pio\" />\r
+ <Folder Include="src\asf\sam\drivers\pmc\" />\r
+ <Folder Include="src\asf\sam\drivers\usart\" />\r
<Folder Include="src\asf\sam\utils\" />\r
<Folder Include="src\asf\sam\utils\cmsis\" />\r
<Folder Include="src\asf\sam\utils\cmsis\sam4s\" />\r
--- /dev/null
+/*\r
+ FreeRTOS V7.1.1 - Copyright (C) 2012 Real Time Engineers Ltd.\r
+ \r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS tutorial books are available in pdf and paperback. *\r
+ * Complete, revised, and edited pdf reference manuals are also *\r
+ * available. *\r
+ * *\r
+ * Purchasing FreeRTOS documentation will not only help you, by *\r
+ * ensuring you get running as quickly as possible and with an *\r
+ * in-depth knowledge of how to use FreeRTOS, it will also help *\r
+ * the FreeRTOS project to continue with its mission of providing *\r
+ * professional grade, cross platform, de facto standard solutions *\r
+ * for microcontrollers - completely free of charge! *\r
+ * *\r
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
+ * *\r
+ * Thank you for using FreeRTOS, and thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+ >>>NOTE<<< The modification to the GPL is included to allow you to\r
+ distribute a combined work that includes FreeRTOS without being obliged to\r
+ provide the source code for proprietary components outside of the FreeRTOS\r
+ kernel. FreeRTOS is distributed in the hope that it will be useful, but\r
+ WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ more details. You should have received a copy of the GNU General Public\r
+ License and the FreeRTOS license exception along with FreeRTOS; if not it\r
+ can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
+ by writing to Richard Barry, contact details for whom are available on the\r
+ FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+ \r
+ ***************************************************************************\r
+ * *\r
+ * Having a problem? Start by reading the FAQ "My application does *\r
+ * not run, what could be wrong? *\r
+ * *\r
+ * http://www.FreeRTOS.org/FAQHelp.html *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ \r
+ http://www.FreeRTOS.org - Documentation, training, latest information, \r
+ license and contact details.\r
+ \r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool.\r
+\r
+ Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell \r
+ the code with commercial support, indemnification, and middleware, under \r
+ the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also\r
+ provide a safety engineered and independently SIL3 certified version under \r
+ the SafeRTOS brand: http://www.SafeRTOS.com.\r
+*/\r
+\r
+\r
+/*\r
+ * This version of comtest. c is for use on systems that have limited stack\r
+ * space and no display facilities. The complete version can be found in\r
+ * the Demo/Common/Full directory.\r
+ *\r
+ * Creates two tasks that operate on an interrupt driven serial port. A\r
+ * loopback connector should be used so that everything that is transmitted is\r
+ * also received. The serial port does not use any flow control. On a\r
+ * standard 9way 'D' connector pins two and three should be connected together.\r
+ *\r
+ * The first task posts a sequence of characters to the Tx queue, toggling an\r
+ * LED on each successful post. At the end of the sequence it sleeps for a\r
+ * pseudo-random period before resending the same sequence.\r
+ *\r
+ * The UART Tx end interrupt is enabled whenever data is available in the Tx\r
+ * queue. The Tx end ISR removes a single character from the Tx queue and\r
+ * passes it to the UART for transmission.\r
+ *\r
+ * The second task blocks on the Rx queue waiting for a character to become\r
+ * available. When the UART Rx end interrupt receives a character it places\r
+ * it in the Rx queue, waking the second task. The second task checks that the\r
+ * characters removed from the Rx queue form the same sequence as those posted\r
+ * to the Tx queue, and toggles an LED for each correct character.\r
+ *\r
+ * The receiving task is spawned with a higher priority than the transmitting\r
+ * task. The receiver will therefore wake every time a character is\r
+ * transmitted so neither the Tx or Rx queue should ever hold more than a few\r
+ * characters.\r
+ *\r
+ */\r
+\r
+/* Scheduler include files. */\r
+#include <stdlib.h>\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/* Demo program include files. */\r
+#include "demo_serial.h"\r
+#include "comtest2.h"\r
+#include "partest.h"\r
+\r
+#define comSTACK_SIZE configMINIMAL_STACK_SIZE\r
+#define comTX_LED_OFFSET ( 0 )\r
+#define comRX_LED_OFFSET ( 1 )\r
+#define comTOTAL_PERMISSIBLE_ERRORS ( 2 )\r
+\r
+/* The Tx task will transmit the sequence of characters at a pseudo random\r
+interval. This is the maximum and minimum block time between sends. */\r
+#define comTX_MAX_BLOCK_TIME ( ( portTickType ) 0x96 )\r
+#define comTX_MIN_BLOCK_TIME ( ( portTickType ) 0x32 )\r
+#define comOFFSET_TIME ( ( portTickType ) 3 )\r
+\r
+/* We should find that each character can be queued for Tx immediately and we\r
+don't have to block to send. */\r
+#define comNO_BLOCK ( ( portTickType ) 0 )\r
+\r
+/* The Rx task will block on the Rx queue for a long period. */\r
+#define comRX_BLOCK_TIME ( ( portTickType ) 0xffff )\r
+\r
+/* The sequence transmitted is from comFIRST_BYTE to and including comLAST_BYTE. */\r
+#define comFIRST_BYTE ( 'A' )\r
+#define comLAST_BYTE ( 'X' )\r
+\r
+#define comBUFFER_LEN ( ( unsigned portBASE_TYPE ) ( comLAST_BYTE - comFIRST_BYTE ) + ( unsigned portBASE_TYPE ) 1 )\r
+#define comINITIAL_RX_COUNT_VALUE ( 0 )\r
+\r
+/* Handle to the com port used by both tasks. */\r
+static xComPortHandle xPort = NULL;\r
+\r
+/* The transmit task as described at the top of the file. */\r
+static portTASK_FUNCTION_PROTO( vComTxTask, pvParameters );\r
+\r
+/* The receive task as described at the top of the file. */\r
+static portTASK_FUNCTION_PROTO( vComRxTask, pvParameters );\r
+\r
+/* The LED that should be toggled by the Rx and Tx tasks. The Rx task will\r
+toggle LED ( uxBaseLED + comRX_LED_OFFSET). The Tx task will toggle LED\r
+( uxBaseLED + comTX_LED_OFFSET ). */\r
+static unsigned portBASE_TYPE uxBaseLED = 0;\r
+\r
+/* Check variable used to ensure no error have occurred. The Rx task will\r
+increment this variable after every successfully received sequence. If at any\r
+time the sequence is incorrect the the variable will stop being incremented. */\r
+static volatile unsigned portBASE_TYPE uxRxLoops = comINITIAL_RX_COUNT_VALUE;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void vAltStartComTestTasks( unsigned portBASE_TYPE uxPriority, unsigned long ulBaudRate, unsigned portBASE_TYPE uxLED )\r
+{\r
+ /* Initialise the com port then spawn the Rx and Tx tasks. */\r
+ uxBaseLED = uxLED;\r
+ xSerialPortInitMinimal( ulBaudRate, comBUFFER_LEN );\r
+\r
+ /* The Tx task is spawned with a lower priority than the Rx task. */\r
+ xTaskCreate( vComTxTask, ( signed char * ) "COMTx", comSTACK_SIZE, NULL, uxPriority - 1, ( xTaskHandle * ) NULL );\r
+ xTaskCreate( vComRxTask, ( signed char * ) "COMRx", comSTACK_SIZE, NULL, uxPriority, ( xTaskHandle * ) NULL );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static portTASK_FUNCTION( vComTxTask, pvParameters )\r
+{\r
+signed char cByteToSend;\r
+portTickType xTimeToWait;\r
+\r
+ /* Just to stop compiler warnings. */\r
+ ( void ) pvParameters;\r
+\r
+ for( ;; )\r
+ {\r
+ /* Simply transmit a sequence of characters from comFIRST_BYTE to\r
+ comLAST_BYTE. */\r
+ for( cByteToSend = comFIRST_BYTE; cByteToSend <= comLAST_BYTE; cByteToSend++ )\r
+ {\r
+ if( xSerialPutChar( xPort, cByteToSend, comNO_BLOCK ) == pdPASS )\r
+ {\r
+ vParTestToggleLED( uxBaseLED + comTX_LED_OFFSET );\r
+ }\r
+ }\r
+\r
+ /* Turn the LED off while we are not doing anything. */\r
+ vParTestSetLED( uxBaseLED + comTX_LED_OFFSET, pdFALSE );\r
+\r
+ /* We have posted all the characters in the string - wait before\r
+ re-sending. Wait a pseudo-random time as this will provide a better\r
+ test. */\r
+ xTimeToWait = xTaskGetTickCount() + comOFFSET_TIME;\r
+\r
+ /* Make sure we don't wait too long... */\r
+ xTimeToWait %= comTX_MAX_BLOCK_TIME;\r
+\r
+ /* ...but we do want to wait. */\r
+ if( xTimeToWait < comTX_MIN_BLOCK_TIME )\r
+ {\r
+ xTimeToWait = comTX_MIN_BLOCK_TIME;\r
+ }\r
+\r
+ vTaskDelay( xTimeToWait );\r
+ }\r
+} /*lint !e715 !e818 pvParameters is required for a task function even if it is not referenced. */\r
+/*-----------------------------------------------------------*/\r
+\r
+static portTASK_FUNCTION( vComRxTask, pvParameters )\r
+{\r
+signed char cExpectedByte, cByteRxed;\r
+portBASE_TYPE xResyncRequired = pdFALSE, xErrorOccurred = pdFALSE;\r
+\r
+ /* Just to stop compiler warnings. */\r
+ ( void ) pvParameters;\r
+\r
+ for( ;; )\r
+ {\r
+ /* We expect to receive the characters from comFIRST_BYTE to\r
+ comLAST_BYTE in an incrementing order. Loop to receive each byte. */\r
+ for( cExpectedByte = comFIRST_BYTE; cExpectedByte <= comLAST_BYTE; cExpectedByte++ )\r
+ {\r
+ /* Block on the queue that contains received bytes until a byte is\r
+ available. */\r
+ if( xSerialGetChar( xPort, &cByteRxed, comRX_BLOCK_TIME ) )\r
+ {\r
+ /* Was this the byte we were expecting? If so, toggle the LED,\r
+ otherwise we are out on sync and should break out of the loop\r
+ until the expected character sequence is about to restart. */\r
+ if( cByteRxed == cExpectedByte )\r
+ {\r
+ vParTestToggleLED( uxBaseLED + comRX_LED_OFFSET );\r
+ }\r
+ else\r
+ {\r
+ xResyncRequired = pdTRUE;\r
+ break; /*lint !e960 Non-switch break allowed. */\r
+ }\r
+ }\r
+ }\r
+\r
+ /* Turn the LED off while we are not doing anything. */\r
+ vParTestSetLED( uxBaseLED + comRX_LED_OFFSET, pdFALSE );\r
+\r
+ /* Did we break out of the loop because the characters were received in\r
+ an unexpected order? If so wait here until the character sequence is\r
+ about to restart. */\r
+ if( xResyncRequired == pdTRUE )\r
+ {\r
+ while( cByteRxed != comLAST_BYTE )\r
+ {\r
+ /* Block until the next char is available. */\r
+ xSerialGetChar( xPort, &cByteRxed, comRX_BLOCK_TIME );\r
+ }\r
+\r
+ /* Note that an error occurred which caused us to have to resync.\r
+ We use this to stop incrementing the loop counter so\r
+ sAreComTestTasksStillRunning() will return false - indicating an\r
+ error. */\r
+ xErrorOccurred++;\r
+\r
+ /* We have now resynced with the Tx task and can continue. */\r
+ xResyncRequired = pdFALSE;\r
+ }\r
+ else\r
+ {\r
+ if( xErrorOccurred < comTOTAL_PERMISSIBLE_ERRORS )\r
+ {\r
+ /* Increment the count of successful loops. As error\r
+ occurring (i.e. an unexpected character being received) will\r
+ prevent this counter being incremented for the rest of the\r
+ execution. Don't worry about mutual exclusion on this\r
+ variable - it doesn't really matter as we just want it\r
+ to change. */\r
+ uxRxLoops++;\r
+ }\r
+ }\r
+ }\r
+} /*lint !e715 !e818 pvParameters is required for a task function even if it is not referenced. */\r
+/*-----------------------------------------------------------*/\r
+\r
+portBASE_TYPE xAreComTestTasksStillRunning( void )\r
+{\r
+portBASE_TYPE xReturn;\r
+\r
+ /* If the count of successful reception loops has not changed than at\r
+ some time an error occurred (i.e. a character was received out of sequence)\r
+ and we will return false. */\r
+ if( uxRxLoops == comINITIAL_RX_COUNT_VALUE )\r
+ {\r
+ xReturn = pdFALSE;\r
+ }\r
+ else\r
+ {\r
+ xReturn = pdTRUE;\r
+ }\r
+\r
+ /* Reset the count of successful Rx loops. When this function is called\r
+ again we expect this to have been incremented. */\r
+ uxRxLoops = comINITIAL_RX_COUNT_VALUE;\r
+\r
+ return xReturn;\r
+}\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V7.1.1 - Copyright (C) 2012 Real Time Engineers Ltd.\r
+ \r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS tutorial books are available in pdf and paperback. *\r
+ * Complete, revised, and edited pdf reference manuals are also *\r
+ * available. *\r
+ * *\r
+ * Purchasing FreeRTOS documentation will not only help you, by *\r
+ * ensuring you get running as quickly as possible and with an *\r
+ * in-depth knowledge of how to use FreeRTOS, it will also help *\r
+ * the FreeRTOS project to continue with its mission of providing *\r
+ * professional grade, cross platform, de facto standard solutions *\r
+ * for microcontrollers - completely free of charge! *\r
+ * *\r
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
+ * *\r
+ * Thank you for using FreeRTOS, and thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+ >>>NOTE<<< The modification to the GPL is included to allow you to\r
+ distribute a combined work that includes FreeRTOS without being obliged to\r
+ provide the source code for proprietary components outside of the FreeRTOS\r
+ kernel. FreeRTOS is distributed in the hope that it will be useful, but\r
+ WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ more details. You should have received a copy of the GNU General Public\r
+ License and the FreeRTOS license exception along with FreeRTOS; if not it\r
+ can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
+ by writing to Richard Barry, contact details for whom are available on the\r
+ FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+ \r
+ ***************************************************************************\r
+ * *\r
+ * Having a problem? Start by reading the FAQ "My application does *\r
+ * not run, what could be wrong? *\r
+ * *\r
+ * http://www.FreeRTOS.org/FAQHelp.html *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ \r
+ http://www.FreeRTOS.org - Documentation, training, latest information, \r
+ license and contact details.\r
+ \r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool.\r
+\r
+ Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell \r
+ the code with commercial support, indemnification, and middleware, under \r
+ the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also\r
+ provide a safety engineered and independently SIL3 certified version under \r
+ the SafeRTOS brand: http://www.SafeRTOS.com.\r
+*/\r
+\r
+/**\r
+ * Repeatedly toggles one or more LEDs using software timers - one timer per\r
+ * LED.\r
+ */\r
+ \r
+/* Scheduler include files. */\r
+#include "FreeRTOS.h"\r
+#include "timers.h"\r
+\r
+/* Demo program include files. */\r
+#include "partest.h"\r
+#include "flash_timer.h"\r
+\r
+/* The toggle rates are all a multple of ledFLASH_RATE_BASE. */\r
+#define ledFLASH_RATE_BASE ( ( ( portTickType ) 333 ) / portTICK_RATE_MS )\r
+\r
+/* A block time of zero simple means "don't block". */\r
+#define ledDONT_BLOCK ( ( portTickType ) 0 )\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * The callback function used by each LED flashing timer. All the timers use\r
+ * this function, and the timer ID is used within the function to determine\r
+ * which timer has actually expired.\r
+ */\r
+static void prvLEDTimerCallback( xTimerHandle xTimer );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void vStartLEDFlashTimers( unsigned portBASE_TYPE uxNumberOfLEDs )\r
+{\r
+unsigned portBASE_TYPE uxLEDTimer;\r
+xTimerHandle xTimer;\r
+\r
+ /* Create and start the requested number of timers. */\r
+ for( uxLEDTimer = 0; uxLEDTimer < uxNumberOfLEDs; ++uxLEDTimer )\r
+ {\r
+ /* Create the timer. */\r
+ xTimer = xTimerCreate( ( const signed char * const ) "Flasher",/* A text name, purely to help debugging. */\r
+ ledFLASH_RATE_BASE * ( uxLEDTimer + 1 ), /* The timer period, which is a multiple of ledFLASH_RATE_BASE. */\r
+ pdTRUE, /* This is an auto-reload timer, so xAutoReload is set to pdTRUE. */\r
+ ( void * ) uxLEDTimer, /* The ID is used to identify the timer within the timer callback function, as each timer uses the same callback. */\r
+ prvLEDTimerCallback /* Each timer uses the same callback. */\r
+ );\r
+ \r
+ /* If the timer was created successfully, attempt to start it. If the\r
+ scheduler has not yet been started then the timer command queue must\r
+ be long enough to hold each command sent to it until such time that the\r
+ scheduler is started. The timer command queue length is set by\r
+ configTIMER_QUEUE_LENGTH in FreeRTOSConfig.h. */\r
+ if( xTimer != NULL )\r
+ {\r
+ xTimerStart( xTimer, ledDONT_BLOCK );\r
+ } \r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvLEDTimerCallback( xTimerHandle xTimer )\r
+{\r
+portBASE_TYPE xTimerID;\r
+\r
+ /* The timer ID is used to identify the timer that has actually expired as\r
+ each timer uses the same callback. The ID is then also used as the number\r
+ of the LED that is to be toggled. */\r
+ xTimerID = ( portBASE_TYPE ) pvTimerGetTimerID( xTimer );\r
+ vParTestToggleLED( xTimerID );\r
+}\r
+\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V7.1.1 - Copyright (C) 2012 Real Time Engineers Ltd.\r
+ \r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS tutorial books are available in pdf and paperback. *\r
+ * Complete, revised, and edited pdf reference manuals are also *\r
+ * available. *\r
+ * *\r
+ * Purchasing FreeRTOS documentation will not only help you, by *\r
+ * ensuring you get running as quickly as possible and with an *\r
+ * in-depth knowledge of how to use FreeRTOS, it will also help *\r
+ * the FreeRTOS project to continue with its mission of providing *\r
+ * professional grade, cross platform, de facto standard solutions *\r
+ * for microcontrollers - completely free of charge! *\r
+ * *\r
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
+ * *\r
+ * Thank you for using FreeRTOS, and thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+ >>>NOTE<<< The modification to the GPL is included to allow you to\r
+ distribute a combined work that includes FreeRTOS without being obliged to\r
+ provide the source code for proprietary components outside of the FreeRTOS\r
+ kernel. FreeRTOS is distributed in the hope that it will be useful, but\r
+ WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ more details. You should have received a copy of the GNU General Public\r
+ License and the FreeRTOS license exception along with FreeRTOS; if not it\r
+ can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
+ by writing to Richard Barry, contact details for whom are available on the\r
+ FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+ \r
+ ***************************************************************************\r
+ * *\r
+ * Having a problem? Start by reading the FAQ "My application does *\r
+ * not run, what could be wrong? *\r
+ * *\r
+ * http://www.FreeRTOS.org/FAQHelp.html *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ \r
+ http://www.FreeRTOS.org - Documentation, training, latest information, \r
+ license and contact details.\r
+ \r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool.\r
+\r
+ Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell \r
+ the code with commercial support, indemnification, and middleware, under \r
+ the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also\r
+ provide a safety engineered and independently SIL3 certified version under \r
+ the SafeRTOS brand: http://www.SafeRTOS.com.\r
+*/\r
+\r
+#ifndef COMTEST_H\r
+#define COMTEST_H\r
+\r
+void vAltStartComTestTasks( unsigned portBASE_TYPE uxPriority, unsigned long ulBaudRate, unsigned portBASE_TYPE uxLED );\r
+portBASE_TYPE xAreComTestTasksStillRunning( void );\r
+\r
+#endif\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V7.1.1 - Copyright (C) 2012 Real Time Engineers Ltd.\r
+ \r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS tutorial books are available in pdf and paperback. *\r
+ * Complete, revised, and edited pdf reference manuals are also *\r
+ * available. *\r
+ * *\r
+ * Purchasing FreeRTOS documentation will not only help you, by *\r
+ * ensuring you get running as quickly as possible and with an *\r
+ * in-depth knowledge of how to use FreeRTOS, it will also help *\r
+ * the FreeRTOS project to continue with its mission of providing *\r
+ * professional grade, cross platform, de facto standard solutions *\r
+ * for microcontrollers - completely free of charge! *\r
+ * *\r
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
+ * *\r
+ * Thank you for using FreeRTOS, and thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+ >>>NOTE<<< The modification to the GPL is included to allow you to\r
+ distribute a combined work that includes FreeRTOS without being obliged to\r
+ provide the source code for proprietary components outside of the FreeRTOS\r
+ kernel. FreeRTOS is distributed in the hope that it will be useful, but\r
+ WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ more details. You should have received a copy of the GNU General Public\r
+ License and the FreeRTOS license exception along with FreeRTOS; if not it\r
+ can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
+ by writing to Richard Barry, contact details for whom are available on the\r
+ FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+ \r
+ ***************************************************************************\r
+ * *\r
+ * Having a problem? Start by reading the FAQ "My application does *\r
+ * not run, what could be wrong? *\r
+ * *\r
+ * http://www.FreeRTOS.org/FAQHelp.html *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ \r
+ http://www.FreeRTOS.org - Documentation, training, latest information, \r
+ license and contact details.\r
+ \r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool.\r
+\r
+ Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell \r
+ the code with commercial support, indemnification, and middleware, under \r
+ the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also\r
+ provide a safety engineered and independently SIL3 certified version under \r
+ the SafeRTOS brand: http://www.SafeRTOS.com.\r
+*/\r
+\r
+#ifndef SERIAL_COMMS_H\r
+#define SERIAL_COMMS_H\r
+\r
+typedef void * xComPortHandle;\r
+\r
+typedef enum\r
+{ \r
+ serCOM1, \r
+ serCOM2, \r
+ serCOM3, \r
+ serCOM4, \r
+ serCOM5, \r
+ serCOM6, \r
+ serCOM7, \r
+ serCOM8 \r
+} eCOMPort;\r
+\r
+typedef enum \r
+{ \r
+ serNO_PARITY, \r
+ serODD_PARITY, \r
+ serEVEN_PARITY, \r
+ serMARK_PARITY, \r
+ serSPACE_PARITY \r
+} eParity;\r
+\r
+typedef enum \r
+{ \r
+ serSTOP_1, \r
+ serSTOP_2 \r
+} eStopBits;\r
+\r
+typedef enum \r
+{ \r
+ serBITS_5, \r
+ serBITS_6, \r
+ serBITS_7, \r
+ serBITS_8 \r
+} eDataBits;\r
+\r
+typedef enum \r
+{ \r
+ ser50, \r
+ ser75, \r
+ ser110, \r
+ ser134, \r
+ ser150, \r
+ ser200,\r
+ ser300, \r
+ ser600, \r
+ ser1200, \r
+ ser1800, \r
+ ser2400, \r
+ ser4800,\r
+ ser9600, \r
+ ser19200, \r
+ ser38400, \r
+ ser57600, \r
+ ser115200\r
+} eBaud;\r
+\r
+xComPortHandle xSerialPortInitMinimal( unsigned long ulWantedBaud, unsigned portBASE_TYPE uxQueueLength );\r
+xComPortHandle xSerialPortInit( eCOMPort ePort, eBaud eWantedBaud, eParity eWantedParity, eDataBits eWantedDataBits, eStopBits eWantedStopBits, unsigned portBASE_TYPE uxBufferLength );\r
+void vSerialPutString( xComPortHandle pxPort, const signed char * const pcString, unsigned short usStringLength );\r
+signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed char *pcRxedChar, portTickType xBlockTime );\r
+signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed char cOutChar, portTickType xBlockTime );\r
+portBASE_TYPE xSerialWaitForSemaphore( xComPortHandle xPort );\r
+void vSerialClose( xComPortHandle xPort );\r
+\r
+#endif\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V7.1.1 - Copyright (C) 2012 Real Time Engineers Ltd.\r
+ \r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS tutorial books are available in pdf and paperback. *\r
+ * Complete, revised, and edited pdf reference manuals are also *\r
+ * available. *\r
+ * *\r
+ * Purchasing FreeRTOS documentation will not only help you, by *\r
+ * ensuring you get running as quickly as possible and with an *\r
+ * in-depth knowledge of how to use FreeRTOS, it will also help *\r
+ * the FreeRTOS project to continue with its mission of providing *\r
+ * professional grade, cross platform, de facto standard solutions *\r
+ * for microcontrollers - completely free of charge! *\r
+ * *\r
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
+ * *\r
+ * Thank you for using FreeRTOS, and thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+ >>>NOTE<<< The modification to the GPL is included to allow you to\r
+ distribute a combined work that includes FreeRTOS without being obliged to\r
+ provide the source code for proprietary components outside of the FreeRTOS\r
+ kernel. FreeRTOS is distributed in the hope that it will be useful, but\r
+ WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ more details. You should have received a copy of the GNU General Public\r
+ License and the FreeRTOS license exception along with FreeRTOS; if not it\r
+ can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
+ by writing to Richard Barry, contact details for whom are available on the\r
+ FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+ \r
+ ***************************************************************************\r
+ * *\r
+ * Having a problem? Start by reading the FAQ "My application does *\r
+ * not run, what could be wrong? *\r
+ * *\r
+ * http://www.FreeRTOS.org/FAQHelp.html *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ \r
+ http://www.FreeRTOS.org - Documentation, training, latest information, \r
+ license and contact details.\r
+ \r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool.\r
+\r
+ Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell \r
+ the code with commercial support, indemnification, and middleware, under \r
+ the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also\r
+ provide a safety engineered and independently SIL3 certified version under \r
+ the SafeRTOS brand: http://www.SafeRTOS.com.\r
+*/\r
+\r
+#ifndef FLASH_TIMER_H\r
+#define FLASH_TIMER_H\r
+\r
+/*\r
+ * Creates the LED flashing timers. xNumberOfLEDs specifies how many timers to\r
+ * create, with each timer toggling a different LED. The first LED to be \r
+ * toggled is LED 0, with subsequent LEDs following on in numerical order. Each\r
+ * timer uses the exact same callback function, with the timer ID being used\r
+ * within the callback function to determine which timer has actually expired\r
+ * (and therefore which LED to toggle).\r
+ */\r
+void vStartLEDFlashTimers( unsigned portBASE_TYPE uxNumberOfLEDs );\r
+\r
+#endif /* FLASH_TIMER_H */\r
--- /dev/null
+/*\r
+ FreeRTOS V7.1.1 - Copyright (C) 2012 Real Time Engineers Ltd.\r
+ \r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS tutorial books are available in pdf and paperback. *\r
+ * Complete, revised, and edited pdf reference manuals are also *\r
+ * available. *\r
+ * *\r
+ * Purchasing FreeRTOS documentation will not only help you, by *\r
+ * ensuring you get running as quickly as possible and with an *\r
+ * in-depth knowledge of how to use FreeRTOS, it will also help *\r
+ * the FreeRTOS project to continue with its mission of providing *\r
+ * professional grade, cross platform, de facto standard solutions *\r
+ * for microcontrollers - completely free of charge! *\r
+ * *\r
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
+ * *\r
+ * Thank you for using FreeRTOS, and thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+ >>>NOTE<<< The modification to the GPL is included to allow you to\r
+ distribute a combined work that includes FreeRTOS without being obliged to\r
+ provide the source code for proprietary components outside of the FreeRTOS\r
+ kernel. FreeRTOS is distributed in the hope that it will be useful, but\r
+ WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ more details. You should have received a copy of the GNU General Public\r
+ License and the FreeRTOS license exception along with FreeRTOS; if not it\r
+ can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
+ by writing to Richard Barry, contact details for whom are available on the\r
+ FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+ \r
+ ***************************************************************************\r
+ * *\r
+ * Having a problem? Start by reading the FAQ "My application does *\r
+ * not run, what could be wrong? *\r
+ * *\r
+ * http://www.FreeRTOS.org/FAQHelp.html *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ \r
+ http://www.FreeRTOS.org - Documentation, training, latest information, \r
+ license and contact details.\r
+ \r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool.\r
+\r
+ Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell \r
+ the code with commercial support, indemnification, and middleware, under \r
+ the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also\r
+ provide a safety engineered and independently SIL3 certified version under \r
+ the SafeRTOS brand: http://www.SafeRTOS.com.\r
+*/\r
+\r
+#ifndef PARTEST_H\r
+#define PARTEST_H\r
+\r
+#define partstDEFAULT_PORT_ADDRESS ( ( unsigned short ) 0x378 )\r
+\r
+void vParTestInitialise( void );\r
+void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue );\r
+void vParTestToggleLED( unsigned portBASE_TYPE uxLED );\r
+\r
+#endif\r
+\r
#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 130 )\r
#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 40960 ) )\r
#define configMAX_TASK_NAME_LEN ( 10 )\r
-#define configUSE_TRACE_FACILITY 1\r
+#define configUSE_TRACE_FACILITY 0\r
#define configUSE_16_BIT_TICKS 0\r
#define configIDLE_SHOULD_YIELD 1\r
#define configUSE_MUTEXES 1\r
-#define configQUEUE_REGISTRY_SIZE 8\r
+#define configQUEUE_REGISTRY_SIZE 0\r
#define configCHECK_FOR_STACK_OVERFLOW 2\r
#define configUSE_RECURSIVE_MUTEXES 1\r
#define configUSE_MALLOC_FAILED_HOOK 1\r
#define configGENERATE_RUN_TIME_STATS 0\r
\r
/* Co-routine definitions. */\r
-#define configUSE_CO_ROUTINES 0\r
+#define configUSE_CO_ROUTINES 0\r
#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )\r
\r
/* Software timer definitions. */\r
{\r
unsigned long ul;\r
\r
- for( l = 0; l < partestNUM_LEDS; l++ )\r
+ for( ul = 0; ul < partestNUM_LEDS; ul++ )\r
{\r
/* Configure the LED, before ensuring it starts in the off state. */\r
- gpio_configure_pin( ulLED[ l ], ( PIO_OUTPUT_1 | PIO_DEFAULT ) );\r
- vParTestSetLED( l, pdFALSE );\r
+ gpio_configure_pin( ulLED[ ul ], ( PIO_OUTPUT_1 | PIO_DEFAULT ) );\r
+ vParTestSetLED( ul, pdFALSE );\r
}\r
}\r
/*-----------------------------------------------------------*/\r
#include <pio.h>\r
#include <pio_handler.h>\r
\r
-// From module: SAM4S startup code\r
-#include <exceptions.h>\r
+// From module: PMC - Power Management Controller\r
+#include <pmc.h>\r
+#include <sleep.h>\r
+\r
+// From module: System Clock Control - SAM4S implementation\r
+#include <sysclk.h>\r
+\r
+// From module: USART - Univ. Syn Async Rec/Trans\r
+#include <usart.h>\r
#endif // ASF_H
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Generic clock management\r
+ *\r
+ * Copyright (c) 2010-2011 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+#ifndef CLK_GENCLK_H_INCLUDED\r
+#define CLK_GENCLK_H_INCLUDED\r
+\r
+#include "parts.h"\r
+\r
+#if SAM3S\r
+# include "sam3s/genclk.h"\r
+#elif SAM3U\r
+# include "sam3u/genclk.h"\r
+#elif SAM3N\r
+# include "sam3n/genclk.h"\r
+#elif SAM3XA\r
+# include "sam3x/genclk.h"\r
+#elif SAM4S\r
+# include "sam4s/genclk.h"\r
+#elif (UC3A0 || UC3A1)\r
+# include "uc3a0_a1/genclk.h"\r
+#elif UC3A3\r
+# include "uc3a3_a4/genclk.h"\r
+#elif UC3B\r
+# include "uc3b0_b1/genclk.h"\r
+#elif UC3C\r
+# include "uc3c/genclk.h"\r
+#elif UC3D\r
+# include "uc3d/genclk.h"\r
+#elif UC3L\r
+# include "uc3l/genclk.h"\r
+#else\r
+# error Unsupported chip type\r
+#endif\r
+\r
+/**\r
+ * \ingroup clk_group\r
+ * \defgroup genclk_group Generic Clock Management\r
+ *\r
+ * Generic clocks are configurable clocks which run outside the system\r
+ * clock domain. They are often connected to peripherals which have an\r
+ * asynchronous component running independently of the bus clock, e.g.\r
+ * USB controllers, low-power timers and RTCs, etc.\r
+ *\r
+ * Note that not all platforms have support for generic clocks; on such\r
+ * platforms, this API will not be available.\r
+ *\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * \def GENCLK_DIV_MAX\r
+ * \brief Maximum divider supported by the generic clock implementation\r
+ */\r
+/**\r
+ * \enum genclk_source\r
+ * \brief Generic clock source ID\r
+ *\r
+ * Each generic clock may be generated from a different clock source.\r
+ * These are the available alternatives provided by the chip.\r
+ */\r
+\r
+//! \name Generic clock configuration\r
+//@{\r
+/**\r
+ * \struct genclk_config\r
+ * \brief Hardware representation of a set of generic clock parameters\r
+ */\r
+/**\r
+ * \fn void genclk_config_defaults(struct genclk_config *cfg,\r
+ * unsigned int id)\r
+ * \brief Initialize \a cfg to the default configuration for the clock\r
+ * identified by \a id.\r
+ */\r
+/**\r
+ * \fn void genclk_config_read(struct genclk_config *cfg, unsigned int id)\r
+ * \brief Read the currently active configuration of the clock\r
+ * identified by \a id into \a cfg.\r
+ */\r
+/**\r
+ * \fn void genclk_config_write(const struct genclk_config *cfg,\r
+ * unsigned int id)\r
+ * \brief Activate the configuration \a cfg on the clock identified by\r
+ * \a id.\r
+ */\r
+/**\r
+ * \fn void genclk_config_set_source(struct genclk_config *cfg,\r
+ * enum genclk_source src)\r
+ * \brief Select a new source clock \a src in configuration \a cfg.\r
+ */\r
+/**\r
+ * \fn void genclk_config_set_divider(struct genclk_config *cfg,\r
+ * unsigned int divider)\r
+ * \brief Set a new \a divider in configuration \a cfg.\r
+ */\r
+/**\r
+ * \fn void genclk_enable_source(enum genclk_source src)\r
+ * \brief Enable the source clock \a src used by a generic clock.\r
+ */\r
+ //@}\r
+\r
+//! \name Enabling and disabling Generic Clocks\r
+//@{\r
+/**\r
+ * \fn void genclk_enable(const struct genclk_config *cfg, unsigned int id)\r
+ * \brief Activate the configuration \a cfg on the clock identified by\r
+ * \a id and enable it.\r
+ */\r
+/**\r
+ * \fn void genclk_disable(unsigned int id)\r
+ * \brief Disable the generic clock identified by \a id.\r
+ */\r
+//@}\r
+\r
+/**\r
+ * \brief Enable the configuration defined by \a src and \a divider\r
+ * for the generic clock identified by \a id.\r
+ *\r
+ * \param id The ID of the generic clock.\r
+ * \param src The source clock of the generic clock.\r
+ * \param divider The divider used to generate the generic clock.\r
+ */\r
+static inline void genclk_enable_config(unsigned int id, enum genclk_source src, unsigned int divider)\r
+{\r
+ struct genclk_config gcfg;\r
+\r
+ genclk_config_defaults(&gcfg, id);\r
+ genclk_enable_source(src);\r
+ genclk_config_set_source(&gcfg, src);\r
+ genclk_config_set_divider(&gcfg, divider);\r
+ genclk_enable(&gcfg, id);\r
+}\r
+\r
+//! @}\r
+\r
+#endif /* CLK_GENCLK_H_INCLUDED */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Oscillator management\r
+ *\r
+ * Copyright (c) 2010 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+#ifndef OSC_H_INCLUDED\r
+#define OSC_H_INCLUDED\r
+\r
+#include "parts.h"\r
+#include "conf_clock.h"\r
+\r
+#if SAM3S\r
+# include "sam3s/osc.h"\r
+#elif SAM3XA\r
+# include "sam3x/osc.h"\r
+#elif SAM3U\r
+# include "sam3u/osc.h"\r
+#elif SAM3N\r
+# include "sam3n/osc.h"\r
+#elif SAM4S\r
+# include "sam4s/osc.h"\r
+#elif (UC3A0 || UC3A1)\r
+# include "uc3a0_a1/osc.h"\r
+#elif UC3A3\r
+# include "uc3a3_a4/osc.h"\r
+#elif UC3B\r
+# include "uc3b0_b1/osc.h"\r
+#elif UC3C\r
+# include "uc3c/osc.h"\r
+#elif UC3D\r
+# include "uc3d/osc.h"\r
+#elif UC3L\r
+# include "uc3l/osc.h"\r
+#elif XMEGA\r
+# include "xmega/osc.h"\r
+#else\r
+# error Unsupported chip type\r
+#endif\r
+\r
+/**\r
+ * \ingroup clk_group\r
+ * \defgroup osc_group Oscillator Management\r
+ *\r
+ * This group contains functions and definitions related to configuring\r
+ * and enabling/disabling on-chip oscillators. Internal RC-oscillators,\r
+ * external crystal oscillators and external clock generators are\r
+ * supported by this module. What all of these have in common is that\r
+ * they swing at a fixed, nominal frequency which is normally not\r
+ * adjustable.\r
+ *\r
+ * \par Example: Enabling an oscillator\r
+ *\r
+ * The following example demonstrates how to enable the external\r
+ * oscillator on XMEGA A and wait for it to be ready to use. The\r
+ * oscillator identifiers are platform-specific, so while the same\r
+ * procedure is used on all platforms, the parameter to osc_enable()\r
+ * will be different from device to device.\r
+ * \code\r
+ osc_enable(OSC_ID_XOSC);\r
+ osc_wait_ready(OSC_ID_XOSC); \endcode\r
+ *\r
+ * \section osc_group_board Board-specific Definitions\r
+ * If external oscillators are used, the board code must provide the\r
+ * following definitions for each of those:\r
+ * - \b BOARD_<osc name>_HZ: The nominal frequency of the oscillator.\r
+ * - \b BOARD_<osc name>_STARTUP_US: The startup time of the\r
+ * oscillator in microseconds.\r
+ * - \b BOARD_<osc name>_TYPE: The type of oscillator connected, i.e.\r
+ * whether it's a crystal or external clock, and sometimes what kind\r
+ * of crystal it is. The meaning of this value is platform-specific.\r
+ *\r
+ * @{\r
+ */\r
+\r
+//! \name Oscillator Management\r
+//@{\r
+/**\r
+ * \fn void osc_enable(uint8_t id)\r
+ * \brief Enable oscillator \a id\r
+ *\r
+ * The startup time and mode value is automatically determined based on\r
+ * definitions in the board code.\r
+ */\r
+/**\r
+ * \fn void osc_disable(uint8_t id)\r
+ * \brief Disable oscillator \a id\r
+ */\r
+/**\r
+ * \fn osc_is_ready(uint8_t id)\r
+ * \brief Determine whether oscillator \a id is ready.\r
+ * \retval true Oscillator \a id is running and ready to use as a clock\r
+ * source.\r
+ * \retval false Oscillator \a id is not running.\r
+ */\r
+/**\r
+ * \fn uint32_t osc_get_rate(uint8_t id)\r
+ * \brief Return the frequency of oscillator \a id in Hz\r
+ */\r
+\r
+#ifndef __ASSEMBLY__\r
+\r
+/**\r
+ * \brief Wait until the oscillator identified by \a id is ready\r
+ *\r
+ * This function will busy-wait for the oscillator identified by \a id\r
+ * to become stable and ready to use as a clock source.\r
+ *\r
+ * \param id A number identifying the oscillator to wait for.\r
+ */\r
+static inline void osc_wait_ready(uint8_t id)\r
+{\r
+ while (!osc_is_ready(id)) {\r
+ /* Do nothing */\r
+ }\r
+}\r
+\r
+#endif /* __ASSEMBLY__ */\r
+\r
+//@}\r
+\r
+//! @}\r
+\r
+#endif /* OSC_H_INCLUDED */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief PLL management\r
+ *\r
+ * Copyright (c) 2010-2011 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+#ifndef CLK_PLL_H_INCLUDED\r
+#define CLK_PLL_H_INCLUDED\r
+\r
+#include "parts.h"\r
+#include "conf_clock.h"\r
+\r
+#if SAM3S\r
+# include "sam3s/pll.h"\r
+#elif SAM3XA\r
+# include "sam3x/pll.h"\r
+#elif SAM3U\r
+# include "sam3u/pll.h"\r
+#elif SAM3N\r
+# include "sam3n/pll.h"\r
+#elif SAM4S\r
+# include "sam4s/pll.h"\r
+#elif (UC3A0 || UC3A1)\r
+# include "uc3a0_a1/pll.h"\r
+#elif UC3A3\r
+# include "uc3a3_a4/pll.h"\r
+#elif UC3B\r
+# include "uc3b0_b1/pll.h"\r
+#elif UC3C\r
+# include "uc3c/pll.h"\r
+#elif UC3D\r
+# include "uc3d/pll.h"\r
+#elif (UC3L0128 || UC3L0256 || UC3L3_L4)\r
+# include "uc3l/pll.h"\r
+#elif XMEGA\r
+# include "xmega/pll.h"\r
+#else\r
+# error Unsupported chip type\r
+#endif\r
+\r
+/**\r
+ * \ingroup clk_group\r
+ * \defgroup pll_group PLL Management\r
+ *\r
+ * This group contains functions and definitions related to configuring\r
+ * and enabling/disabling on-chip PLLs. A PLL will take an input signal\r
+ * (the \em source), optionally divide the frequency by a configurable\r
+ * \em divider, and then multiply the frequency by a configurable \em\r
+ * multiplier.\r
+ *\r
+ * Some devices don't support input dividers; specifying any other\r
+ * divisor than 1 on these devices will result in an assertion failure.\r
+ * Other devices may have various restrictions to the frequency range of\r
+ * the input and output signals.\r
+ *\r
+ * \par Example: Setting up PLL0 with default parameters\r
+ *\r
+ * The following example shows how to configure and enable PLL0 using\r
+ * the default parameters specified using the configuration symbols\r
+ * listed above.\r
+ * \code\r
+ pll_enable_config_defaults(0); \endcode\r
+ *\r
+ * To configure, enable PLL0 using the default parameters and to disable\r
+ * a specific feature like Wide Bandwidth Mode (a UC3A3-specific\r
+ * PLL option.), you can use this initialization process.\r
+ * \code\r
+ struct pll_config pllcfg;\r
+ if (pll_is_locked(pll_id)) {\r
+ return; // Pll already running\r
+ }\r
+ pll_enable_source(CONFIG_PLL0_SOURCE);\r
+ pll_config_defaults(&pllcfg, 0);\r
+ pll_config_set_option(&pllcfg, PLL_OPT_WBM_DISABLE);\r
+ pll_enable(&pllcfg, 0);\r
+ pll_wait_for_lock(0); \endcode\r
+ *\r
+ * When the last function call returns, PLL0 is ready to be used as the\r
+ * main system clock source.\r
+ *\r
+ * \section pll_group_config Configuration Symbols\r
+ *\r
+ * Each PLL has a set of default parameters determined by the following\r
+ * configuration symbols in the application's configuration file:\r
+ * - \b CONFIG_PLLn_SOURCE: The default clock source connected to the\r
+ * input of PLL \a n. Must be one of the values defined by the\r
+ * #pll_source enum.\r
+ * - \b CONFIG_PLLn_MUL: The default multiplier (loop divider) of PLL\r
+ * \a n.\r
+ * - \b CONFIG_PLLn_DIV: The default input divider of PLL \a n.\r
+ *\r
+ * These configuration symbols determine the result of calling\r
+ * pll_config_defaults() and pll_get_default_rate().\r
+ *\r
+ * @{\r
+ */\r
+\r
+//! \name Chip-specific PLL characteristics\r
+//@{\r
+/**\r
+ * \def PLL_MAX_STARTUP_CYCLES\r
+ * \brief Maximum PLL startup time in number of slow clock cycles\r
+ */\r
+/**\r
+ * \def NR_PLLS\r
+ * \brief Number of on-chip PLLs\r
+ */\r
+\r
+/**\r
+ * \def PLL_MIN_HZ\r
+ * \brief Minimum frequency that the PLL can generate\r
+ */\r
+/**\r
+ * \def PLL_MAX_HZ\r
+ * \brief Maximum frequency that the PLL can generate\r
+ */\r
+/**\r
+ * \def PLL_NR_OPTIONS\r
+ * \brief Number of PLL option bits\r
+ */\r
+//@}\r
+\r
+/**\r
+ * \enum pll_source\r
+ * \brief PLL clock source\r
+ */\r
+\r
+//! \name PLL configuration\r
+//@{\r
+\r
+/**\r
+ * \struct pll_config\r
+ * \brief Hardware-specific representation of PLL configuration.\r
+ *\r
+ * This structure contains one or more device-specific values\r
+ * representing the current PLL configuration. The contents of this\r
+ * structure is typically different from platform to platform, and the\r
+ * user should not access any fields except through the PLL\r
+ * configuration API.\r
+ */\r
+\r
+/**\r
+ * \fn void pll_config_init(struct pll_config *cfg,\r
+ * enum pll_source src, unsigned int div, unsigned int mul)\r
+ * \brief Initialize PLL configuration from standard parameters.\r
+ *\r
+ * \note This function may be defined inline because it is assumed to be\r
+ * called very few times, and usually with constant parameters. Inlining\r
+ * it will in such cases reduce the code size significantly.\r
+ *\r
+ * \param cfg The PLL configuration to be initialized.\r
+ * \param src The oscillator to be used as input to the PLL.\r
+ * \param div PLL input divider.\r
+ * \param mul PLL loop divider (i.e. multiplier).\r
+ *\r
+ * \return A configuration which will make the PLL run at\r
+ * (\a mul / \a div) times the frequency of \a src\r
+ */\r
+/**\r
+ * \def pll_config_defaults(cfg, pll_id)\r
+ * \brief Initialize PLL configuration using default parameters.\r
+ *\r
+ * After this function returns, \a cfg will contain a configuration\r
+ * which will make the PLL run at (CONFIG_PLLx_MUL / CONFIG_PLLx_DIV)\r
+ * times the frequency of CONFIG_PLLx_SOURCE.\r
+ *\r
+ * \param cfg The PLL configuration to be initialized.\r
+ * \param pll_id Use defaults for this PLL.\r
+ */\r
+/**\r
+ * \def pll_get_default_rate(pll_id)\r
+ * \brief Get the default rate in Hz of \a pll_id\r
+ */\r
+/**\r
+ * \fn void pll_config_set_option(struct pll_config *cfg,\r
+ * unsigned int option)\r
+ * \brief Set the PLL option bit \a option in the configuration \a cfg.\r
+ *\r
+ * \param cfg The PLL configuration to be changed.\r
+ * \param option The PLL option bit to be set.\r
+ */\r
+/**\r
+ * \fn void pll_config_clear_option(struct pll_config *cfg,\r
+ * unsigned int option)\r
+ * \brief Clear the PLL option bit \a option in the configuration \a cfg.\r
+ *\r
+ * \param cfg The PLL configuration to be changed.\r
+ * \param option The PLL option bit to be cleared.\r
+ */\r
+/**\r
+ * \fn void pll_config_read(struct pll_config *cfg, unsigned int pll_id)\r
+ * \brief Read the currently active configuration of \a pll_id.\r
+ *\r
+ * \param cfg The configuration object into which to store the currently\r
+ * active configuration.\r
+ * \param pll_id The ID of the PLL to be accessed.\r
+ */\r
+/**\r
+ * \fn void pll_config_write(const struct pll_config *cfg,\r
+ * unsigned int pll_id)\r
+ * \brief Activate the configuration \a cfg on \a pll_id\r
+ *\r
+ * \param cfg The configuration object representing the PLL\r
+ * configuration to be activated.\r
+ * \param pll_id The ID of the PLL to be updated.\r
+ */\r
+\r
+//@}\r
+\r
+//! \name Interaction with the PLL hardware\r
+//@{\r
+/**\r
+ * \fn void pll_enable(const struct pll_config *cfg,\r
+ * unsigned int pll_id)\r
+ * \brief Activate the configuration \a cfg and enable PLL \a pll_id.\r
+ *\r
+ * \param cfg The PLL configuration to be activated.\r
+ * \param pll_id The ID of the PLL to be enabled.\r
+ */\r
+/**\r
+ * \fn void pll_disable(unsigned int pll_id)\r
+ * \brief Disable the PLL identified by \a pll_id.\r
+ *\r
+ * After this function is called, the PLL identified by \a pll_id will\r
+ * be disabled. The PLL configuration stored in hardware may be affected\r
+ * by this, so if the caller needs to restore the same configuration\r
+ * later, it should either do a pll_config_read() before disabling the\r
+ * PLL, or remember the last configuration written to the PLL.\r
+ *\r
+ * \param pll_id The ID of the PLL to be disabled.\r
+ */\r
+/**\r
+ * \fn bool pll_is_locked(unsigned int pll_id)\r
+ * \brief Determine whether the PLL is locked or not.\r
+ *\r
+ * \param pll_id The ID of the PLL to check.\r
+ *\r
+ * \retval true The PLL is locked and ready to use as a clock source\r
+ * \retval false The PLL is not yet locked, or has not been enabled.\r
+ */\r
+/**\r
+ * \fn void pll_enable_source(enum pll_source src)\r
+ * \brief Enable the source of the pll.\r
+ * The source is enabled, if the source is not already running.\r
+ *\r
+ * \param src The ID of the PLL source to enable.\r
+ */\r
+/**\r
+ * \fn void pll_enable_config_defaults(unsigned int pll_id)\r
+ * \brief Enable the pll with the default configuration.\r
+ * PLL is enabled, if the PLL is not already locked.\r
+ *\r
+ * \param pll_id The ID of the PLL to enable.\r
+ */\r
+\r
+/**\r
+ * \brief Wait for PLL \a pll_id to become locked\r
+ *\r
+ * \todo Use a timeout to avoid waiting forever and hanging the system\r
+ *\r
+ * \param pll_id The ID of the PLL to wait for.\r
+ *\r
+ * \retval STATUS_OK The PLL is now locked.\r
+ * \retval ERR_TIMEOUT Timed out waiting for PLL to become locked.\r
+ */\r
+static inline int pll_wait_for_lock(unsigned int pll_id)\r
+{\r
+ Assert(pll_id < NR_PLLS);\r
+\r
+ while (!pll_is_locked(pll_id)) {\r
+ /* Do nothing */\r
+ }\r
+\r
+ return 0;\r
+}\r
+\r
+//@}\r
+//! @}\r
+\r
+#endif /* CLK_PLL_H_INCLUDED */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Chip-specific generic clock management.\r
+ *\r
+ * Copyright (c) 2011 - 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef CHIP_GENCLK_H_INCLUDED\r
+#define CHIP_GENCLK_H_INCLUDED\r
+\r
+#include <osc.h>\r
+#include <pll.h>\r
+\r
+/// @cond 0\r
+/**INDENT-OFF**/\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+/**INDENT-ON**/\r
+/// @endcond\r
+\r
+/**\r
+ * \weakgroup genclk_group\r
+ * @{\r
+ */\r
+\r
+//! \name Programmable Clock Identifiers (PCK)\r
+//@{\r
+#define GENCLK_PCK_0 0 //!< PCK0 ID\r
+#define GENCLK_PCK_1 1 //!< PCK1 ID\r
+#define GENCLK_PCK_2 2 //!< PCK2 ID\r
+//@}\r
+\r
+//! \name Programmable Clock Sources (PCK)\r
+//@{\r
+\r
+enum genclk_source {\r
+ GENCLK_PCK_SRC_SLCK_RC = 0, //!< Internal 32kHz RC oscillator as PCK source clock\r
+ GENCLK_PCK_SRC_SLCK_XTAL = 1, //!< External 32kHz crystal oscillator as PCK source clock\r
+ GENCLK_PCK_SRC_SLCK_BYPASS = 2, //!< External 32kHz bypass oscillator as PCK source clock\r
+ GENCLK_PCK_SRC_MAINCK_4M_RC = 3, //!< Internal 4MHz RC oscillator as PCK source clock\r
+ GENCLK_PCK_SRC_MAINCK_8M_RC = 4, //!< Internal 8MHz RC oscillator as PCK source clock\r
+ GENCLK_PCK_SRC_MAINCK_12M_RC = 5, //!< Internal 12MHz RC oscillator as PCK source clock\r
+ GENCLK_PCK_SRC_MAINCK_XTAL = 6, //!< External crystal oscillator as PCK source clock\r
+ GENCLK_PCK_SRC_MAINCK_BYPASS = 7, //!< External bypass oscillator as PCK source clock\r
+ GENCLK_PCK_SRC_PLLACK = 8, //!< Use PLLACK as PCK source clock\r
+ GENCLK_PCK_SRC_PLLBCK = 9, //!< Use PLLBCK as PCK source clock\r
+};\r
+\r
+//@}\r
+\r
+//! \name Programmable Clock Prescalers (PCK)\r
+//@{\r
+\r
+enum genclk_divider {\r
+ GENCLK_PCK_PRES_1 = PMC_PCK_PRES_CLK_1, //!< Set PCK clock prescaler to 1\r
+ GENCLK_PCK_PRES_2 = PMC_PCK_PRES_CLK_2, //!< Set PCK clock prescaler to 2\r
+ GENCLK_PCK_PRES_4 = PMC_PCK_PRES_CLK_4, //!< Set PCK clock prescaler to 4\r
+ GENCLK_PCK_PRES_8 = PMC_PCK_PRES_CLK_8, //!< Set PCK clock prescaler to 8\r
+ GENCLK_PCK_PRES_16 = PMC_PCK_PRES_CLK_16, //!< Set PCK clock prescaler to 16\r
+ GENCLK_PCK_PRES_32 = PMC_PCK_PRES_CLK_32, //!< Set PCK clock prescaler to 32\r
+ GENCLK_PCK_PRES_64 = PMC_PCK_PRES_CLK_64, //!< Set PCK clock prescaler to 64\r
+};\r
+\r
+//@}\r
+\r
+struct genclk_config {\r
+ uint32_t ctrl;\r
+};\r
+\r
+static inline void genclk_config_defaults(struct genclk_config *p_cfg,\r
+ uint32_t ul_id)\r
+{\r
+ ul_id = ul_id;\r
+ p_cfg->ctrl = 0;\r
+}\r
+\r
+static inline void genclk_config_read(struct genclk_config *p_cfg,\r
+ uint32_t ul_id)\r
+{\r
+ p_cfg->ctrl = PMC->PMC_PCK[ul_id];\r
+}\r
+\r
+static inline void genclk_config_write(const struct genclk_config *p_cfg,\r
+ uint32_t ul_id)\r
+{\r
+ PMC->PMC_PCK[ul_id] = p_cfg->ctrl;\r
+}\r
+\r
+//! \name Programmable Clock Source and Prescaler configuration\r
+//@{\r
+\r
+static inline void genclk_config_set_source(struct genclk_config *p_cfg,\r
+ enum genclk_source e_src)\r
+{\r
+ p_cfg->ctrl &= (~PMC_PCK_CSS_Msk);\r
+\r
+ switch (e_src) {\r
+ case GENCLK_PCK_SRC_SLCK_RC:\r
+ case GENCLK_PCK_SRC_SLCK_XTAL:\r
+ case GENCLK_PCK_SRC_SLCK_BYPASS:\r
+ p_cfg->ctrl |= (PMC_MCKR_CSS_SLOW_CLK);\r
+ break;\r
+\r
+ case GENCLK_PCK_SRC_MAINCK_4M_RC:\r
+ case GENCLK_PCK_SRC_MAINCK_8M_RC:\r
+ case GENCLK_PCK_SRC_MAINCK_12M_RC:\r
+ case GENCLK_PCK_SRC_MAINCK_XTAL:\r
+ case GENCLK_PCK_SRC_MAINCK_BYPASS:\r
+ p_cfg->ctrl |= (PMC_MCKR_CSS_MAIN_CLK);\r
+ break;\r
+\r
+ case GENCLK_PCK_SRC_PLLACK:\r
+ p_cfg->ctrl |= (PMC_MCKR_CSS_PLLA_CLK);\r
+ break;\r
+\r
+ case GENCLK_PCK_SRC_PLLBCK:\r
+ p_cfg->ctrl |= (PMC_MCKR_CSS_PLLB_CLK);\r
+ break;\r
+ }\r
+}\r
+\r
+static inline void genclk_config_set_divider(struct genclk_config *p_cfg,\r
+ enum genclk_divider e_divider)\r
+{\r
+ p_cfg->ctrl &= ~PMC_PCK_PRES_Msk;\r
+ p_cfg->ctrl |= e_divider; \r
+}\r
+\r
+//@}\r
+\r
+static inline void genclk_enable(const struct genclk_config *p_cfg, uint32_t ul_id)\r
+{\r
+ PMC->PMC_PCK[ul_id] = p_cfg->ctrl;\r
+ pmc_enable_pck(ul_id);\r
+}\r
+\r
+static inline void genclk_disable(uint32_t ul_id)\r
+{\r
+ pmc_disable_pck(ul_id);\r
+}\r
+\r
+static inline void genclk_enable_source(enum genclk_source e_src)\r
+{\r
+ switch (e_src) {\r
+ case GENCLK_PCK_SRC_SLCK_RC:\r
+ if (!osc_is_ready(OSC_SLCK_32K_RC)) {\r
+ osc_enable(OSC_SLCK_32K_RC);\r
+ osc_wait_ready(OSC_SLCK_32K_RC);\r
+ } \r
+ break;\r
+ \r
+ case GENCLK_PCK_SRC_SLCK_XTAL:\r
+ if (!osc_is_ready(OSC_SLCK_32K_XTAL)) {\r
+ osc_enable(OSC_SLCK_32K_XTAL);\r
+ osc_wait_ready(OSC_SLCK_32K_XTAL);\r
+ }\r
+ break;\r
+ \r
+ case GENCLK_PCK_SRC_SLCK_BYPASS:\r
+ if (!osc_is_ready(OSC_SLCK_32K_BYPASS)) {\r
+ osc_enable(OSC_SLCK_32K_BYPASS);\r
+ osc_wait_ready(OSC_SLCK_32K_BYPASS); \r
+ } \r
+ break;\r
+ \r
+ case GENCLK_PCK_SRC_MAINCK_4M_RC:\r
+ if (!osc_is_ready(OSC_MAINCK_4M_RC)) {\r
+ osc_enable(OSC_MAINCK_4M_RC);\r
+ osc_wait_ready(OSC_MAINCK_4M_RC); \r
+ } \r
+ break;\r
+\r
+ case GENCLK_PCK_SRC_MAINCK_8M_RC:\r
+ if (!osc_is_ready(OSC_MAINCK_8M_RC)) {\r
+ osc_enable(OSC_MAINCK_8M_RC);\r
+ osc_wait_ready(OSC_MAINCK_8M_RC); \r
+ } \r
+ break;\r
+\r
+ case GENCLK_PCK_SRC_MAINCK_12M_RC:\r
+ if (!osc_is_ready(OSC_MAINCK_12M_RC)) {\r
+ osc_enable(OSC_MAINCK_12M_RC);\r
+ osc_wait_ready(OSC_MAINCK_12M_RC); \r
+ } \r
+ break;\r
+\r
+ case GENCLK_PCK_SRC_MAINCK_XTAL:\r
+ if (!osc_is_ready(OSC_MAINCK_XTAL)) {\r
+ osc_enable(OSC_MAINCK_XTAL);\r
+ osc_wait_ready(OSC_MAINCK_XTAL); \r
+ } \r
+ break;\r
+\r
+ case GENCLK_PCK_SRC_MAINCK_BYPASS:\r
+ if (!osc_is_ready(OSC_MAINCK_BYPASS)) {\r
+ osc_enable(OSC_MAINCK_BYPASS);\r
+ osc_wait_ready(OSC_MAINCK_BYPASS); \r
+ } \r
+ break;\r
+\r
+#ifdef CONFIG_PLL0_SOURCE\r
+ case GENCLK_PCK_SRC_PLLACK:\r
+ pll_enable_config_defaults(0); \r
+ break; \r
+#endif\r
+\r
+#ifdef CONFIG_PLL1_SOURCE\r
+ case GENCLK_PCK_SRC_PLLBCK:\r
+ pll_enable_config_defaults(1); \r
+ break; \r
+#endif \r
+\r
+ default:\r
+ Assert(false);\r
+ break;\r
+ }\r
+}\r
+\r
+//! @}\r
+\r
+/// @cond 0\r
+/**INDENT-OFF**/\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+/**INDENT-ON**/\r
+/// @endcond\r
+\r
+#endif /* CHIP_GENCLK_H_INCLUDED */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Chip-specific oscillator management functions.\r
+ *\r
+ * Copyright (c) 2011-2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef CHIP_OSC_H_INCLUDED\r
+#define CHIP_OSC_H_INCLUDED\r
+\r
+#include "board.h"\r
+#include "pmc.h"\r
+\r
+/// @cond 0\r
+/**INDENT-OFF**/\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+/**INDENT-ON**/\r
+/// @endcond\r
+\r
+/**\r
+ * \weakgroup osc_group\r
+ * @{\r
+ */\r
+\r
+//! \name Oscillator identifiers\r
+//@{\r
+#define OSC_SLCK_32K_RC 0 //!< Internal 32kHz RC oscillator.\r
+#define OSC_SLCK_32K_XTAL 1 //!< External 32kHz crystal oscillator.\r
+#define OSC_SLCK_32K_BYPASS 2 //!< External 32kHz bypass oscillator.\r
+#define OSC_MAINCK_4M_RC 3 //!< Internal 4MHz RC oscillator.\r
+#define OSC_MAINCK_8M_RC 4 //!< Internal 8MHz RC oscillator.\r
+#define OSC_MAINCK_12M_RC 5 //!< Internal 12MHz RC oscillator.\r
+#define OSC_MAINCK_XTAL 6 //!< External crystal oscillator.\r
+#define OSC_MAINCK_BYPASS 7 //!< External bypass oscillator.\r
+//@}\r
+\r
+//! \name Oscillator clock speed in hertz\r
+//@{\r
+#define OSC_SLCK_32K_RC_HZ CHIP_FREQ_SLCK_RC //!< Internal 32kHz RC oscillator.\r
+#define OSC_SLCK_32K_XTAL_HZ BOARD_FREQ_SLCK_XTAL //!< External 32kHz crystal oscillator.\r
+#define OSC_SLCK_32K_BYPASS_HZ BOARD_FREQ_SLCK_BYPASS //!< External 32kHz bypass oscillator.\r
+#define OSC_MAINCK_4M_RC_HZ CHIP_FREQ_MAINCK_RC_4MHZ //!< Internal 4MHz RC oscillator.\r
+#define OSC_MAINCK_8M_RC_HZ CHIP_FREQ_MAINCK_RC_8MHZ //!< Internal 8MHz RC oscillator.\r
+#define OSC_MAINCK_12M_RC_HZ CHIP_FREQ_MAINCK_RC_12MHZ //!< Internal 12MHz RC oscillator.\r
+#define OSC_MAINCK_XTAL_HZ BOARD_FREQ_MAINCK_XTAL //!< External crystal oscillator.\r
+#define OSC_MAINCK_BYPASS_HZ BOARD_FREQ_MAINCK_BYPASS //!< External bypass oscillator.\r
+//@}\r
+\r
+static inline void osc_enable(uint32_t ul_id)\r
+{\r
+ switch (ul_id) {\r
+ case OSC_SLCK_32K_RC:\r
+ break;\r
+\r
+ case OSC_SLCK_32K_XTAL:\r
+ pmc_switch_sclk_to_32kxtal(PMC_OSC_XTAL);\r
+ break;\r
+\r
+ case OSC_SLCK_32K_BYPASS:\r
+ pmc_switch_sclk_to_32kxtal(PMC_OSC_BYPASS);\r
+ break;\r
+\r
+\r
+ case OSC_MAINCK_4M_RC:\r
+ pmc_switch_mainck_to_fastrc(CKGR_MOR_MOSCRCF_4_MHz);\r
+ break;\r
+\r
+ case OSC_MAINCK_8M_RC:\r
+ pmc_switch_mainck_to_fastrc(CKGR_MOR_MOSCRCF_8_MHz);\r
+ break;\r
+\r
+ case OSC_MAINCK_12M_RC:\r
+ pmc_switch_mainck_to_fastrc(CKGR_MOR_MOSCRCF_12_MHz);\r
+ break;\r
+\r
+\r
+ case OSC_MAINCK_XTAL:\r
+ pmc_switch_mainck_to_xtal(PMC_OSC_XTAL);\r
+ break;\r
+\r
+ case OSC_MAINCK_BYPASS:\r
+ pmc_switch_mainck_to_xtal(PMC_OSC_BYPASS);\r
+ break;\r
+ }\r
+}\r
+\r
+static inline void osc_disable(uint32_t ul_id)\r
+{\r
+ switch (ul_id) {\r
+ case OSC_SLCK_32K_RC:\r
+ case OSC_SLCK_32K_XTAL:\r
+ case OSC_SLCK_32K_BYPASS:\r
+ break;\r
+\r
+ case OSC_MAINCK_4M_RC:\r
+ case OSC_MAINCK_8M_RC:\r
+ case OSC_MAINCK_12M_RC:\r
+ pmc_osc_disable_fastrc();\r
+ break;\r
+\r
+ case OSC_MAINCK_XTAL:\r
+ pmc_osc_disable_xtal(PMC_OSC_XTAL);\r
+ break;\r
+\r
+ case OSC_MAINCK_BYPASS:\r
+ pmc_osc_disable_xtal(PMC_OSC_BYPASS);\r
+ break;\r
+ }\r
+}\r
+\r
+static inline bool osc_is_ready(uint32_t ul_id)\r
+{\r
+ switch (ul_id) {\r
+ case OSC_SLCK_32K_RC:\r
+ return 1;\r
+\r
+ case OSC_SLCK_32K_XTAL:\r
+ case OSC_SLCK_32K_BYPASS:\r
+ return pmc_osc_is_ready_32kxtal();\r
+\r
+ case OSC_MAINCK_4M_RC:\r
+ case OSC_MAINCK_8M_RC:\r
+ case OSC_MAINCK_12M_RC:\r
+ case OSC_MAINCK_XTAL:\r
+ case OSC_MAINCK_BYPASS:\r
+ return pmc_osc_is_ready_mainck();\r
+ }\r
+\r
+ return 0;\r
+}\r
+\r
+static inline uint32_t osc_get_rate(uint32_t ul_id)\r
+{\r
+ switch (ul_id) {\r
+ case OSC_SLCK_32K_RC:\r
+ return OSC_SLCK_32K_RC_HZ;\r
+\r
+#ifdef BOARD_FREQ_SLCK_XTAL\r
+ case OSC_SLCK_32K_XTAL:\r
+ return BOARD_FREQ_SLCK_XTAL;\r
+#endif\r
+\r
+#ifdef BOARD_FREQ_SLCK_BYPASS\r
+ case OSC_SLCK_32K_BYPASS:\r
+ return BOARD_FREQ_SLCK_BYPASS;\r
+#endif\r
+\r
+ case OSC_MAINCK_4M_RC:\r
+ return OSC_MAINCK_4M_RC_HZ;\r
+\r
+ case OSC_MAINCK_8M_RC:\r
+ return OSC_MAINCK_8M_RC_HZ;\r
+\r
+ case OSC_MAINCK_12M_RC:\r
+ return OSC_MAINCK_12M_RC_HZ;\r
+\r
+#ifdef BOARD_FREQ_MAINCK_XTAL\r
+ case OSC_MAINCK_XTAL:\r
+ return BOARD_FREQ_MAINCK_XTAL;\r
+#endif\r
+\r
+#ifdef BOARD_FREQ_MAINCK_BYPASS\r
+ case OSC_MAINCK_BYPASS:\r
+ return BOARD_FREQ_MAINCK_BYPASS;\r
+#endif\r
+ }\r
+\r
+ return 0;\r
+}\r
+\r
+//! @}\r
+\r
+/// @cond 0\r
+/**INDENT-OFF**/\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+/**INDENT-ON**/\r
+/// @endcond\r
+\r
+#endif /* CHIP_OSC_H_INCLUDED */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Chip-specific PLL definitions.\r
+ *\r
+ * Copyright (c) 2011-2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef CHIP_PLL_H_INCLUDED\r
+#define CHIP_PLL_H_INCLUDED\r
+\r
+#include <osc.h>\r
+\r
+/// @cond 0\r
+/**INDENT-OFF**/\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+/**INDENT-ON**/\r
+/// @endcond\r
+\r
+/**\r
+ * \weakgroup pll_group\r
+ * @{\r
+ */\r
+\r
+#define PLL_OUTPUT_MIN_HZ 80000000\r
+#define PLL_OUTPUT_MAX_HZ 240000000\r
+\r
+#define PLL_INPUT_MIN_HZ 3000000\r
+#define PLL_INPUT_MAX_HZ 32000000\r
+\r
+#define NR_PLLS 2\r
+#define PLLA_ID 0\r
+#define PLLB_ID 1\r
+\r
+#define PLL_COUNT 0x3fU\r
+\r
+enum pll_source {\r
+ PLL_SRC_MAINCK_4M_RC = OSC_MAINCK_4M_RC, //!< Internal 4MHz RC oscillator.\r
+ PLL_SRC_MAINCK_8M_RC = OSC_MAINCK_8M_RC, //!< Internal 8MHz RC oscillator.\r
+ PLL_SRC_MAINCK_12M_RC = OSC_MAINCK_12M_RC, //!< Internal 12MHz RC oscillator.\r
+ PLL_SRC_MAINCK_XTAL = OSC_MAINCK_XTAL, //!< External crystal oscillator.\r
+ PLL_SRC_MAINCK_BYPASS = OSC_MAINCK_BYPASS, //!< External bypass oscillator.\r
+ PLL_NR_SOURCES, //!< Number of PLL sources.\r
+};\r
+\r
+struct pll_config {\r
+ uint32_t ctrl;\r
+};\r
+\r
+#define pll_get_default_rate(pll_id) \\r
+ ((osc_get_rate(CONFIG_PLL##pll_id##_SOURCE) \\r
+ * CONFIG_PLL##pll_id##_MUL) \\r
+ / CONFIG_PLL##pll_id##_DIV)\r
+\r
+/**\r
+ * \note The SAM3S PLL hardware interprets mul as mul+1. For readability the hardware mul+1\r
+ * is hidden in this implementation. Use mul as mul effective value.\r
+ */\r
+static inline void pll_config_init(struct pll_config *p_cfg,\r
+ enum pll_source e_src, uint32_t ul_div, uint32_t ul_mul)\r
+{\r
+ uint32_t vco_hz;\r
+\r
+ Assert(e_src < PLL_NR_SOURCES);\r
+\r
+ /* Calculate internal VCO frequency */\r
+ vco_hz = osc_get_rate(e_src) / ul_div;\r
+ Assert(vco_hz >= PLL_INPUT_MIN_HZ);\r
+ Assert(vco_hz <= PLL_INPUT_MAX_HZ);\r
+ \r
+ vco_hz *= ul_mul;\r
+ Assert(vco_hz >= PLL_OUTPUT_MIN_HZ);\r
+ Assert(vco_hz <= PLL_OUTPUT_MAX_HZ);\r
+\r
+ /* PMC hardware will automatically make it mul+1 */\r
+ p_cfg->ctrl = CKGR_PLLAR_MULA(ul_mul - 1) | CKGR_PLLAR_DIVA(ul_div) | CKGR_PLLAR_PLLACOUNT(PLL_COUNT);\r
+}\r
+\r
+#define pll_config_defaults(cfg, pll_id) \\r
+ pll_config_init(cfg, \\r
+ CONFIG_PLL##pll_id##_SOURCE, \\r
+ CONFIG_PLL##pll_id##_DIV, \\r
+ CONFIG_PLL##pll_id##_MUL)\r
+\r
+static inline void pll_config_read(struct pll_config *p_cfg, uint32_t ul_pll_id)\r
+{\r
+ Assert(ul_pll_id < NR_PLLS);\r
+\r
+ if (ul_pll_id == PLLA_ID)\r
+ p_cfg->ctrl = PMC->CKGR_PLLAR;\r
+ else\r
+ p_cfg->ctrl = PMC->CKGR_PLLBR;\r
+}\r
+\r
+static inline void pll_config_write(const struct pll_config *p_cfg, uint32_t ul_pll_id)\r
+{\r
+ Assert(ul_pll_id < NR_PLLS);\r
+ \r
+ if (ul_pll_id == PLLA_ID) {\r
+ pmc_disable_pllack(); // Always stop PLL first!\r
+ PMC->CKGR_PLLAR = CKGR_PLLAR_ONE | p_cfg->ctrl;\r
+ } else {\r
+ pmc_disable_pllbck();\r
+ PMC->CKGR_PLLBR = p_cfg->ctrl;\r
+ }\r
+}\r
+\r
+static inline void pll_enable(const struct pll_config *p_cfg, uint32_t ul_pll_id)\r
+{\r
+ Assert(ul_pll_id < NR_PLLS);\r
+ \r
+ if (ul_pll_id == PLLA_ID) {\r
+ pmc_disable_pllack(); // Always stop PLL first!\r
+ PMC->CKGR_PLLAR = CKGR_PLLAR_ONE | p_cfg->ctrl;\r
+ } else {\r
+ pmc_disable_pllbck();\r
+ PMC->CKGR_PLLBR = p_cfg->ctrl;\r
+ }\r
+}\r
+\r
+/** \r
+ * \note This will only disable the selected PLL, not the underlying oscillator (mainck).\r
+ */\r
+static inline void pll_disable(uint32_t ul_pll_id)\r
+{\r
+ Assert(ul_pll_id < NR_PLLS);\r
+ \r
+ if (ul_pll_id == PLLA_ID)\r
+ pmc_disable_pllack();\r
+ else\r
+ pmc_disable_pllbck();\r
+}\r
+\r
+static inline uint32_t pll_is_locked(uint32_t ul_pll_id)\r
+{\r
+ Assert(ul_pll_id < NR_PLLS);\r
+ \r
+ if (ul_pll_id == PLLA_ID)\r
+ return pmc_is_locked_pllack();\r
+ else\r
+ return pmc_is_locked_pllbck();\r
+}\r
+\r
+static inline void pll_enable_source(enum pll_source e_src)\r
+{\r
+ switch (e_src) {\r
+ case PLL_SRC_MAINCK_4M_RC:\r
+ case PLL_SRC_MAINCK_8M_RC:\r
+ case PLL_SRC_MAINCK_12M_RC:\r
+ case PLL_SRC_MAINCK_XTAL:\r
+ case PLL_SRC_MAINCK_BYPASS:\r
+ osc_enable(e_src);\r
+ osc_wait_ready(e_src);\r
+ break;\r
+\r
+ default:\r
+ Assert(false);\r
+ break;\r
+ }\r
+}\r
+\r
+static inline void pll_enable_config_defaults(unsigned int ul_pll_id)\r
+{\r
+ struct pll_config pllcfg;\r
+\r
+ if (pll_is_locked(ul_pll_id)) {\r
+ return; // Pll already running\r
+ }\r
+ switch (ul_pll_id) {\r
+#ifdef CONFIG_PLL0_SOURCE\r
+ case 0:\r
+ pll_enable_source(CONFIG_PLL0_SOURCE);\r
+ pll_config_init(&pllcfg,\r
+ CONFIG_PLL0_SOURCE,\r
+ CONFIG_PLL0_DIV,\r
+ CONFIG_PLL0_MUL);\r
+ break;\r
+#endif\r
+#ifdef CONFIG_PLL1_SOURCE\r
+ case 1:\r
+ pll_enable_source(CONFIG_PLL1_SOURCE);\r
+ pll_config_init(&pllcfg,\r
+ CONFIG_PLL1_SOURCE,\r
+ CONFIG_PLL1_DIV,\r
+ CONFIG_PLL1_MUL);\r
+ break;\r
+#endif\r
+ default:\r
+ Assert(false);\r
+ break;\r
+ }\r
+ pll_enable(&pllcfg, ul_pll_id);\r
+ while (!pll_is_locked(ul_pll_id));\r
+}\r
+\r
+//! @}\r
+\r
+/// @cond 0\r
+/**INDENT-OFF**/\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+/**INDENT-ON**/\r
+/// @endcond\r
+\r
+#endif /* CHIP_PLL_H_INCLUDED */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Chip-specific system clock management functions.\r
+ *\r
+ * Copyright (c) 2011 - 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#include <sysclk.h>\r
+\r
+/// @cond 0\r
+/**INDENT-OFF**/\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+/**INDENT-ON**/\r
+/// @endcond\r
+\r
+/**\r
+ * \weakgroup sysclk_group\r
+ * @{\r
+ */\r
+\r
+#if defined(CONFIG_SYSCLK_DEFAULT_RETURNS_SLOW_OSC)\r
+/**\r
+ * \brief boolean signaling that the sysclk_init is done.\r
+ */\r
+uint32_t sysclk_initialized = 0;\r
+#endif\r
+\r
+/**\r
+ * \brief Set system clock prescaler configuration\r
+ *\r
+ * This function will change the system clock prescaler configuration to\r
+ * match the parameters.\r
+ *\r
+ * \note The parameters to this function are device-specific.\r
+ *\r
+ * \param cpu_shift The CPU clock will be divided by \f$2^{mck\_pres}\f$\r
+ */\r
+void sysclk_set_prescalers(uint32_t ul_pres)\r
+{\r
+ pmc_mck_set_prescaler(ul_pres);\r
+ SystemCoreClockUpdate();\r
+}\r
+\r
+/**\r
+ * \brief Change the source of the main system clock.\r
+ *\r
+ * \param src The new system clock source. Must be one of the constants\r
+ * from the <em>System Clock Sources</em> section.\r
+ */\r
+void sysclk_set_source(uint32_t ul_src)\r
+{\r
+ switch (ul_src) {\r
+ case SYSCLK_SRC_SLCK_RC:\r
+ case SYSCLK_SRC_SLCK_XTAL:\r
+ case SYSCLK_SRC_SLCK_BYPASS:\r
+ pmc_mck_set_source(PMC_MCKR_CSS_SLOW_CLK);\r
+ break;\r
+\r
+ case SYSCLK_SRC_MAINCK_4M_RC:\r
+ case SYSCLK_SRC_MAINCK_8M_RC:\r
+ case SYSCLK_SRC_MAINCK_12M_RC:\r
+ case SYSCLK_SRC_MAINCK_XTAL:\r
+ case SYSCLK_SRC_MAINCK_BYPASS:\r
+ pmc_mck_set_source(PMC_MCKR_CSS_MAIN_CLK);\r
+ break;\r
+\r
+ case SYSCLK_SRC_PLLACK:\r
+ pmc_mck_set_source(PMC_MCKR_CSS_PLLA_CLK);\r
+ break;\r
+\r
+ case SYSCLK_SRC_PLLBCK:\r
+ pmc_mck_set_source(PMC_MCKR_CSS_PLLB_CLK);\r
+ break;\r
+ }\r
+ \r
+ SystemCoreClockUpdate();\r
+}\r
+\r
+#if defined(CONFIG_USBCLK_SOURCE) || defined(__DOXYGEN__)\r
+/**\r
+ * \brief Enable USB clock.\r
+ *\r
+ * \note The SAM3S UDP hardware interprets div as div+1. For readability the hardware div+1\r
+ * is hidden in this implementation. Use div as div effective value.\r
+ *\r
+ * \param pll_id Source of the USB clock.\r
+ * \param div Actual clock diviser. Must be superior to 0.\r
+ */\r
+void sysclk_enable_usb(void)\r
+{\r
+ Assert(CONFIG_USBCLK_DIV > 0);\r
+\r
+ switch (CONFIG_USBCLK_SOURCE) {\r
+#ifdef CONFIG_PLL0_SOURCE\r
+ case USBCLK_SRC_PLL0: {\r
+ struct pll_config pllcfg;\r
+\r
+ pll_enable_source(CONFIG_PLL0_SOURCE);\r
+ pll_config_defaults(&pllcfg, 0);\r
+ pll_enable(&pllcfg, 0);\r
+ pll_wait_for_lock(0);\r
+ pmc_switch_udpck_to_pllack(CONFIG_USBCLK_DIV - 1);\r
+ pmc_enable_udpck();\r
+ break;\r
+ }\r
+#endif\r
+\r
+#ifdef CONFIG_PLL1_SOURCE\r
+ case USBCLK_SRC_PLL1: {\r
+ struct pll_config pllcfg;\r
+\r
+ pll_enable_source(CONFIG_PLL1_SOURCE);\r
+ pll_config_defaults(&pllcfg, 1);\r
+ pll_enable(&pllcfg, 1);\r
+ pll_wait_for_lock(1);\r
+ pmc_switch_udpck_to_pllbck(CONFIG_USBCLK_DIV - 1);\r
+ pmc_enable_udpck();\r
+ break;\r
+ }\r
+#endif\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Disable the USB clock.\r
+ *\r
+ * \note This implementation does not switch off the PLL, it just turns off the USB clock.\r
+ */\r
+void sysclk_disable_usb(void)\r
+{\r
+ pmc_disable_udpck();\r
+}\r
+#endif // CONFIG_USBCLK_SOURCE\r
+\r
+void sysclk_init(void)\r
+{\r
+ struct pll_config pllcfg;\r
+\r
+ /* Set a flash wait state depending on the new cpu frequency */\r
+ system_init_flash(sysclk_get_cpu_hz());\r
+\r
+ /* Config system clock setting */\r
+ switch (CONFIG_SYSCLK_SOURCE) {\r
+ case SYSCLK_SRC_SLCK_RC:\r
+ osc_enable(OSC_SLCK_32K_RC);\r
+ osc_wait_ready(OSC_SLCK_32K_RC); \r
+ pmc_switch_mck_to_sclk(CONFIG_SYSCLK_PRES);\r
+ break;\r
+ \r
+ case SYSCLK_SRC_SLCK_XTAL:\r
+ osc_enable(OSC_SLCK_32K_XTAL);\r
+ osc_wait_ready(OSC_SLCK_32K_XTAL); \r
+ pmc_switch_mck_to_sclk(CONFIG_SYSCLK_PRES);\r
+ break;\r
+ \r
+ case SYSCLK_SRC_SLCK_BYPASS:\r
+ osc_enable(OSC_SLCK_32K_BYPASS);\r
+ osc_wait_ready(OSC_SLCK_32K_BYPASS); \r
+ pmc_switch_mck_to_sclk(CONFIG_SYSCLK_PRES);\r
+ break;\r
+ \r
+ case SYSCLK_SRC_MAINCK_4M_RC:\r
+ /* Already running from SYSCLK_SRC_MAINCK_4M_RC */\r
+ break;\r
+\r
+ case SYSCLK_SRC_MAINCK_8M_RC:\r
+ osc_enable(OSC_MAINCK_8M_RC);\r
+ osc_wait_ready(OSC_MAINCK_8M_RC); \r
+ pmc_switch_mck_to_mainck(CONFIG_SYSCLK_PRES);\r
+ break;\r
+\r
+ case SYSCLK_SRC_MAINCK_12M_RC:\r
+ osc_enable(OSC_MAINCK_12M_RC);\r
+ osc_wait_ready(OSC_MAINCK_12M_RC); \r
+ pmc_switch_mck_to_mainck(CONFIG_SYSCLK_PRES);\r
+ break;\r
+\r
+\r
+ case SYSCLK_SRC_MAINCK_XTAL:\r
+ osc_enable(OSC_MAINCK_XTAL);\r
+ osc_wait_ready(OSC_MAINCK_XTAL); \r
+ pmc_switch_mck_to_mainck(CONFIG_SYSCLK_PRES);\r
+ break;\r
+\r
+ case SYSCLK_SRC_MAINCK_BYPASS:\r
+ osc_enable(OSC_MAINCK_BYPASS);\r
+ osc_wait_ready(OSC_MAINCK_BYPASS); \r
+ pmc_switch_mck_to_mainck(CONFIG_SYSCLK_PRES);\r
+ break;\r
+\r
+#ifdef CONFIG_PLL0_SOURCE\r
+ case SYSCLK_SRC_PLLACK:\r
+ pll_enable_source(CONFIG_PLL0_SOURCE);\r
+ pll_config_defaults(&pllcfg, 0);\r
+ pll_enable(&pllcfg, 0);\r
+ pll_wait_for_lock(0);\r
+ pmc_switch_mck_to_pllack(CONFIG_SYSCLK_PRES);\r
+ break; \r
+#endif \r
+\r
+#ifdef CONFIG_PLL1_SOURCE\r
+ case SYSCLK_SRC_PLLBCK:\r
+ pll_enable_source(CONFIG_PLL1_SOURCE);\r
+ pll_config_defaults(&pllcfg, 1);\r
+ pll_enable(&pllcfg, 1);\r
+ pll_wait_for_lock(1);\r
+ pmc_switch_mck_to_pllbck(CONFIG_SYSCLK_PRES);\r
+ break;\r
+#endif \r
+ }\r
+\r
+ /* Update the SystemFrequency variable */\r
+ SystemCoreClockUpdate();\r
+ \r
+#if (defined CONFIG_SYSCLK_DEFAULT_RETURNS_SLOW_OSC)\r
+ /* Signal that the internal frequencies are setup */\r
+ sysclk_initialized = 1;\r
+#endif\r
+}\r
+\r
+//! @}\r
+\r
+/// @cond 0\r
+/**INDENT-OFF**/\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+/**INDENT-ON**/\r
+/// @endcond\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Chip-specific system clock management functions.\r
+ *\r
+ * Copyright (c) 2011 - 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef CHIP_SYSCLK_H_INCLUDED\r
+#define CHIP_SYSCLK_H_INCLUDED\r
+\r
+#include <osc.h>\r
+#include <pll.h>\r
+\r
+/**\r
+ * \page sysclk_quickstart Quick Start Guide for the System Clock Management service (SAM4S)\r
+ *\r
+ * This is the quick start guide for the \ref sysclk_group "System Clock Management"\r
+ * service, with step-by-step instructions on how to configure and use the service for\r
+ * specific use cases.\r
+ *\r
+ * \section sysclk_quickstart_usecases System Clock Management use cases\r
+ * - \ref sysclk_quickstart_basic\r
+ * - \ref sysclk_quickstart_use_case_2\r
+ *\r
+ * \section sysclk_quickstart_basic Basic usage of the System Clock Management service\r
+ * This section will present a basic use case for the System Clock Management service.\r
+ * This use case will configure the main system clock to 120MHz, using an internal PLL\r
+ * module to multiply the frequency of a crystal attached to the microcontroller.\r
+ *\r
+ * \subsection sysclk_quickstart_use_case_1_prereq Prerequisites\r
+ * - None\r
+ *\r
+ * \subsection sysclk_quickstart_use_case_1_setup_steps Initialization code\r
+ * Add to the application initialization code:\r
+ * \code\r
+ * sysclk_init();\r
+ * \endcode\r
+ *\r
+ * \subsection sysclk_quickstart_use_case_1_setup_steps_workflow Workflow\r
+ * -# Configure the system clocks according to the settings in conf_clock.h:\r
+ * \code sysclk_init(); \endcode\r
+ *\r
+ * \subsection sysclk_quickstart_use_case_1_example_code Example code\r
+ * Add or uncomment the following in your conf_clock.h header file, commenting out all other\r
+ * definitions of the same symbol(s):\r
+ * \code\r
+ * #define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_PLLACK\r
+ *\r
+ * // Fpll0 = (Fclk * PLL_mul) / PLL_div\r
+ * #define CONFIG_PLL0_SOURCE PLL_SRC_MAINCK_XTAL\r
+ * #define CONFIG_PLL0_MUL (120000000UL / BOARD_FREQ_MAINCK_XTAL)\r
+ * #define CONFIG_PLL0_DIV 1\r
+ *\r
+ * // Fbus = Fsys / BUS_div\r
+ * #define CONFIG_SYSCLK_PRES SYSCLK_PRES_1\r
+ * \endcode\r
+ *\r
+ * \subsection sysclk_quickstart_use_case_1_example_workflow Workflow\r
+ * -# Configure the main system clock to use the output of the PLL module as its source:\r
+ * \code #define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_PLLACK \endcode\r
+ * -# Configure the PLL module to use the fast external fast crystal oscillator as its source:\r
+ * \code #define CONFIG_PLL0_SOURCE PLL_SRC_MAINCK_XTAL \endcode\r
+ * -# Configure the PLL module to multiply the external fast crystal oscillator frequency up to 120MHz:\r
+ * \code\r
+ * #define CONFIG_PLL0_MUL (120000000UL / BOARD_FREQ_MAINCK_XTAL)\r
+ * #define CONFIG_PLL0_DIV 1 \r
+ * \endcode\r
+ * \note For user boards, \c BOARD_FREQ_MAINCK_XTAL should be defined in the board \c conf_board.h configuration\r
+ * file as the frequency of the fast crystal attached to the microcontroller.\r
+ * -# Configure the main clock to run at the full 120MHz, disable scaling of the main system clock speed:\r
+ * \code\r
+ * #define CONFIG_SYSCLK_PRES SYSCLK_PRES_1\r
+ * \endcode\r
+ * \note Some dividers are powers of two, while others are integer division factors. Refer to the\r
+ * formulas in the conf_clock.h template commented above each division define.\r
+ */\r
+\r
+/**\r
+ * \page sysclk_quickstart_use_case_2 Advanced use case - Peripheral Bus Clock Management (SAM4S)\r
+ *\r
+ * \section sysclk_quickstart_use_case_2 Advanced use case - Peripheral Bus Clock Management\r
+ * This section will present a more advanced use case for the System Clock Management service.\r
+ * This use case will configure the main system clock to 120MHz, using an internal PLL\r
+ * module to multiply the frequency of a crystal attached to the microcontroller. The USB clock\r
+ * will be configured via a seperate PLL module.\r
+ *\r
+ * \subsection sysclk_quickstart_use_case_2_prereq Prerequisites\r
+ * - None\r
+ *\r
+ * \subsection sysclk_quickstart_use_case_2_setup_steps Initialization code\r
+ * Add to the application initialization code:\r
+ * \code\r
+ * sysclk_init();\r
+ * \endcode\r
+ *\r
+ * \subsection sysclk_quickstart_use_case_2_setup_steps_workflow Workflow\r
+ * -# Configure the system clocks according to the settings in conf_clock.h:\r
+ * \code sysclk_init(); \endcode\r
+ *\r
+ * \subsection sysclk_quickstart_use_case_2_example_code Example code\r
+ * Add or uncomment the following in your conf_clock.h header file, commenting out all other\r
+ * definitions of the same symbol(s):\r
+ * \code\r
+ * #define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_PLLACK\r
+ *\r
+ * // Fpll0 = (Fclk * PLL_mul) / PLL_div\r
+ * #define CONFIG_PLL0_SOURCE PLL_SRC_MAINCK_XTAL\r
+ * #define CONFIG_PLL0_MUL (120000000UL / BOARD_FREQ_MAINCK_XTAL)\r
+ * #define CONFIG_PLL0_DIV 1\r
+ *\r
+ * // Fbus = Fsys / BUS_div\r
+ * #define CONFIG_SYSCLK_PRES SYSCLK_PRES_1\r
+ *\r
+ * // Fusb = Fsys / USB_div\r
+ * #define CONFIG_USBCLK_SOURCE USBCLK_SRC_PLL1\r
+ * #define CONFIG_USBCLK_DIV 1\r
+ *\r
+ * // Fpll1 = (Fclk * PLL_mul) / PLL_div\r
+ * #define CONFIG_PLL1_SOURCE PLL_SRC_MAINCK_XTAL\r
+ * #define CONFIG_PLL1_MUL (48000000UL / BOARD_FREQ_MAINCK_XTAL)\r
+ * #define CONFIG_PLL1_DIV 1\r
+ * \endcode\r
+ *\r
+ * \subsection sysclk_quickstart_use_case_2_example_workflow Workflow\r
+ * -# Configure the main system clock to use the output of the PLL0 module as its source:\r
+ * \code #define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_PLLACK \endcode\r
+ * -# Configure the PLL0 module to use the fast external fast crystal oscillator as its source:\r
+ * \code #define CONFIG_PLL0_SOURCE PLL_SRC_MAINCK_XTAL \endcode\r
+ * -# Configure the PLL0 module to multiply the external fast crystal oscillator frequency up to 120MHz:\r
+ * \code\r
+ * #define CONFIG_PLL0_MUL (120000000UL / BOARD_FREQ_MAINCK_XTAL)\r
+ * #define CONFIG_PLL0_DIV 1 \r
+ * \endcode\r
+ * \note For user boards, \c BOARD_FREQ_MAINCK_XTAL should be defined in the board \c conf_board.h configuration\r
+ * file as the frequency of the fast crystal attached to the microcontroller.\r
+ * -# Configure the main clock to run at the full 120MHz, disable scaling of the main system clock speed:\r
+ * \code\r
+ * #define CONFIG_SYSCLK_PRES SYSCLK_PRES_1\r
+ * \endcode\r
+ * \note Some dividers are powers of two, while others are integer division factors. Refer to the\r
+ * formulas in the conf_clock.h template commented above each division define.\r
+ * -# Configure the USB module clock to use the output of the PLL1 module as its source:\r
+ * \code #define CONFIG_SYSCLK_SOURCE USBCLK_SRC_PLL1 \endcode\r
+ * -# Configure the PLL1 module to use the fast external fast crystal oscillator as its source:\r
+ * \code #define CONFIG_PLL1_SOURCE PLL_SRC_MAINCK_XTAL \endcode\r
+ * -# Configure the PLL1 module to multiply the external fast crystal oscillator frequency up to 48MHz:\r
+ * \code\r
+ * #define CONFIG_PLL1_MUL (48000000UL / BOARD_FREQ_MAINCK_XTAL)\r
+ * #define CONFIG_PLL1_DIV 1 \r
+ * \endcode\r
+ */\r
+\r
+/// @cond 0\r
+/**INDENT-OFF**/\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+/**INDENT-ON**/\r
+/// @endcond\r
+\r
+/**\r
+ * \weakgroup sysclk_group\r
+ * @{\r
+ */\r
+ \r
+//! \name Configuration Symbols\r
+//@{\r
+/**\r
+ * \def CONFIG_SYSCLK_SOURCE\r
+ * \brief Initial/static main system clock source\r
+ *\r
+ * The main system clock will be configured to use this clock during\r
+ * initialization.\r
+ */\r
+#ifndef CONFIG_SYSCLK_SOURCE\r
+# define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_MAINCK_4M_RC\r
+#endif\r
+/**\r
+ * \def CONFIG_SYSCLK_PRES\r
+ * \brief Initial CPU clock divider (mck)\r
+ *\r
+ * The MCK will run at\r
+ * \f[\r
+ * f_{MCK} = \frac{f_{sys}}{\mathrm{CONFIG\_SYSCLK\_PRES}}\,\mbox{Hz}\r
+ * \f]\r
+ * after initialization.\r
+ */\r
+#ifndef CONFIG_SYSCLK_PRES\r
+# define CONFIG_SYSCLK_PRES 0\r
+#endif\r
+\r
+//@}\r
+\r
+//! \name Master Clock Sources (MCK)\r
+//@{\r
+#define SYSCLK_SRC_SLCK_RC 0 //!< Internal 32kHz RC oscillator as master source clock\r
+#define SYSCLK_SRC_SLCK_XTAL 1 //!< External 32kHz crystal oscillator as master source clock\r
+#define SYSCLK_SRC_SLCK_BYPASS 2 //!< External 32kHz bypass oscillator as master source clock\r
+#define SYSCLK_SRC_MAINCK_4M_RC 3 //!< Internal 4MHz RC oscillator as master source clock\r
+#define SYSCLK_SRC_MAINCK_8M_RC 4 //!< Internal 8MHz RC oscillator as master source clock\r
+#define SYSCLK_SRC_MAINCK_12M_RC 5 //!< Internal 12MHz RC oscillator as master source clock\r
+#define SYSCLK_SRC_MAINCK_XTAL 6 //!< External crystal oscillator as master source clock\r
+#define SYSCLK_SRC_MAINCK_BYPASS 7 //!< External bypass oscillator as master source clock\r
+#define SYSCLK_SRC_PLLACK 8 //!< Use PLLACK as master source clock\r
+#define SYSCLK_SRC_PLLBCK 9 //!< Use PLLBCK as master source clock\r
+//@}\r
+\r
+//! \name Master Clock Prescalers (MCK)\r
+//@{\r
+#define SYSCLK_PRES_1 PMC_MCKR_PRES_CLK_1 //!< Set master clock prescaler to 1\r
+#define SYSCLK_PRES_2 PMC_MCKR_PRES_CLK_2 //!< Set master clock prescaler to 2\r
+#define SYSCLK_PRES_4 PMC_MCKR_PRES_CLK_4 //!< Set master clock prescaler to 4\r
+#define SYSCLK_PRES_8 PMC_MCKR_PRES_CLK_8 //!< Set master clock prescaler to 8\r
+#define SYSCLK_PRES_16 PMC_MCKR_PRES_CLK_16 //!< Set master clock prescaler to 16\r
+#define SYSCLK_PRES_32 PMC_MCKR_PRES_CLK_32 //!< Set master clock prescaler to 32\r
+#define SYSCLK_PRES_64 PMC_MCKR_PRES_CLK_64 //!< Set master clock prescaler to 64\r
+#define SYSCLK_PRES_3 PMC_MCKR_PRES_CLK_3 //!< Set master clock prescaler to 3\r
+//@}\r
+\r
+//! \name USB Clock Sources\r
+//@{\r
+#define USBCLK_SRC_PLL0 0 //!< Use PLLA\r
+#define USBCLK_SRC_PLL1 1 //!< Use PLLB\r
+//@}\r
+\r
+/**\r
+ * \def CONFIG_USBCLK_SOURCE\r
+ * \brief Configuration symbol for the USB generic clock source\r
+ *\r
+ * Sets the clock source to use for the USB. The source must also be properly\r
+ * configured.\r
+ *\r
+ * Define this to one of the \c USBCLK_SRC_xxx settings. Leave it undefined if\r
+ * USB is not required.\r
+ */\r
+#ifdef __DOXYGEN__\r
+# define CONFIG_USBCLK_SOURCE\r
+#endif\r
+\r
+/**\r
+ * \def CONFIG_USBCLK_DIV\r
+ * \brief Configuration symbol for the USB generic clock divider setting\r
+ *\r
+ * Sets the clock division for the USB generic clock. If a USB clock source is\r
+ * selected with CONFIG_USBCLK_SOURCE, this configuration symbol must also be\r
+ * defined.\r
+ */\r
+#ifdef __DOXYGEN__\r
+# define CONFIG_USBCLK_DIV\r
+#endif\r
+\r
+/**\r
+ * \name Querying the system clock\r
+ *\r
+ * The following functions may be used to query the current frequency of\r
+ * the system clock and the CPU and bus clocks derived from it.\r
+ * sysclk_get_main_hz() and sysclk_get_cpu_hz() can be assumed to be\r
+ * available on all platforms, although some platforms may define\r
+ * additional accessors for various chip-internal bus clocks. These are\r
+ * usually not intended to be queried directly by generic code.\r
+ */\r
+//@{\r
+\r
+/**\r
+ * \brief Return the current rate in Hz of the main system clock\r
+ *\r
+ * \todo This function assumes that the main clock source never changes\r
+ * once it's been set up, and that PLL0 always runs at the compile-time\r
+ * configured default rate. While this is probably the most common\r
+ * configuration, which we want to support as a special case for\r
+ * performance reasons, we will at some point need to support more\r
+ * dynamic setups as well.\r
+ */\r
+#if (defined CONFIG_SYSCLK_DEFAULT_RETURNS_SLOW_OSC)\r
+extern uint32_t sysclk_initialized;\r
+#endif\r
+static inline uint32_t sysclk_get_main_hz(void)\r
+{\r
+#if (defined CONFIG_SYSCLK_DEFAULT_RETURNS_SLOW_OSC)\r
+ if (!sysclk_initialized ) {\r
+ return OSC_MAINCK_4M_RC_HZ;\r
+ }\r
+#endif\r
+\r
+ /* Config system clock setting */\r
+ switch (CONFIG_SYSCLK_SOURCE) {\r
+ case SYSCLK_SRC_SLCK_RC:\r
+ return OSC_SLCK_32K_RC_HZ;\r
+ \r
+ case SYSCLK_SRC_SLCK_XTAL:\r
+ return OSC_SLCK_32K_XTAL_HZ;\r
+ \r
+ case SYSCLK_SRC_SLCK_BYPASS:\r
+ return OSC_SLCK_32K_BYPASS_HZ;\r
+\r
+\r
+ case SYSCLK_SRC_MAINCK_4M_RC:\r
+ return OSC_MAINCK_4M_RC_HZ;\r
+\r
+ case SYSCLK_SRC_MAINCK_8M_RC:\r
+ return OSC_MAINCK_8M_RC_HZ;\r
+\r
+ case SYSCLK_SRC_MAINCK_12M_RC:\r
+ return OSC_MAINCK_12M_RC_HZ;\r
+\r
+ case SYSCLK_SRC_MAINCK_XTAL:\r
+ return OSC_MAINCK_XTAL_HZ;\r
+\r
+ case SYSCLK_SRC_MAINCK_BYPASS:\r
+ return OSC_MAINCK_BYPASS_HZ;\r
+\r
+#ifdef CONFIG_PLL0_SOURCE\r
+ case SYSCLK_SRC_PLLACK:\r
+ return pll_get_default_rate(0); \r
+#endif\r
+\r
+#ifdef CONFIG_PLL1_SOURCE\r
+ case SYSCLK_SRC_PLLBCK:\r
+ return pll_get_default_rate(1); \r
+#endif\r
+ \r
+ default:\r
+ /* unhandled_case(CONFIG_SYSCLK_SOURCE); */\r
+ return 0;\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Return the current rate in Hz of the CPU clock\r
+ *\r
+ * \todo This function assumes that the CPU always runs at the system\r
+ * clock frequency. We want to support at least two more scenarios:\r
+ * Fixed CPU/bus clock dividers (config symbols) and dynamic CPU/bus\r
+ * clock dividers (which may change at run time). Ditto for all the bus\r
+ * clocks.\r
+ *\r
+ * \return Frequency of the CPU clock, in Hz.\r
+ */\r
+static inline uint32_t sysclk_get_cpu_hz(void)\r
+{\r
+ /* CONFIG_SYSCLK_PRES is the register value for setting the expected */\r
+ /* prescaler, not an immediat value. */\r
+ return sysclk_get_main_hz() / ((CONFIG_SYSCLK_PRES >> PMC_MCKR_PRES_Pos) + 1);\r
+}\r
+\r
+/**\r
+ * \brief Retrieves the current rate in Hz of the peripheral clocks.\r
+ *\r
+ * \return Frequency of the peripheral clocks, in Hz.\r
+ */\r
+static inline uint32_t sysclk_get_peripheral_hz(void)\r
+{\r
+ /* CONFIG_SYSCLK_PRES is the register value for setting the expected */\r
+ /* prescaler, not an immediat value. */\r
+ return sysclk_get_main_hz() / ((CONFIG_SYSCLK_PRES >> PMC_MCKR_PRES_Pos) + 1);\r
+}\r
+\r
+//@}\r
+\r
+//! \name Enabling and disabling synchronous clocks\r
+//@{\r
+\r
+/**\r
+ * \brief Enable a peripheral's clock.\r
+ *\r
+ * \param ul_id Id (number) of the peripheral clock.\r
+ */\r
+static inline void sysclk_enable_peripheral_clock(uint32_t ul_id)\r
+{\r
+ pmc_enable_periph_clk(ul_id);\r
+}\r
+\r
+/**\r
+ * \brief Disable a peripheral's clock.\r
+ *\r
+ * \param ul_id Id (number) of the peripheral clock.\r
+ */\r
+static inline void sysclk_disable_peripheral_clock(uint32_t ul_id)\r
+{\r
+ pmc_disable_periph_clk(ul_id);\r
+}\r
+\r
+//@}\r
+\r
+//! \name System Clock Source and Prescaler configuration\r
+//@{\r
+\r
+extern void sysclk_set_prescalers(uint32_t ul_pres);\r
+extern void sysclk_set_source(uint32_t ul_src);\r
+\r
+//@}\r
+\r
+extern void sysclk_enable_usb(void);\r
+extern void sysclk_disable_usb(void);\r
+\r
+extern void sysclk_init(void);\r
+\r
+//! @}\r
+\r
+/// @cond 0\r
+/**INDENT-OFF**/\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+/**INDENT-ON**/\r
+/// @endcond\r
+\r
+#endif /* CHIP_SYSCLK_H_INCLUDED */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief System clock management\r
+ *\r
+ * Copyright (c) 2010-2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+#ifndef SYSCLK_H_INCLUDED\r
+#define SYSCLK_H_INCLUDED\r
+\r
+#include "parts.h"\r
+#include "conf_clock.h"\r
+\r
+#if SAM3S\r
+# include "sam3s/sysclk.h"\r
+#elif SAM3U\r
+# include "sam3u/sysclk.h"\r
+#elif SAM3N\r
+# include "sam3n/sysclk.h"\r
+#elif SAM3XA\r
+# include "sam3x/sysclk.h"\r
+#elif SAM4S\r
+# include "sam4s/sysclk.h"\r
+#elif (UC3A0 || UC3A1)\r
+# include "uc3a0_a1/sysclk.h"\r
+#elif UC3A3\r
+# include "uc3a3_a4/sysclk.h"\r
+#elif UC3B\r
+# include "uc3b0_b1/sysclk.h"\r
+#elif UC3C\r
+# include "uc3c/sysclk.h"\r
+#elif UC3D\r
+# include "uc3d/sysclk.h"\r
+#elif UC3L\r
+# include "uc3l/sysclk.h"\r
+#elif XMEGA\r
+# include "xmega/sysclk.h"\r
+#else\r
+# error Unsupported chip type\r
+#endif\r
+\r
+/**\r
+ * \defgroup clk_group Clock Management\r
+ */\r
+\r
+/**\r
+ * \ingroup clk_group\r
+ * \defgroup sysclk_group System Clock Management\r
+ *\r
+ * See \ref sysclk_quickstart.\r
+ *\r
+ * The <em>sysclk</em> API covers the <em>system clock</em> and all\r
+ * clocks derived from it. The system clock is a chip-internal clock on\r
+ * which all <em>synchronous clocks</em>, i.e. CPU and bus/peripheral\r
+ * clocks, are based. The system clock is typically generated from one\r
+ * of a variety of sources, which may include crystal and RC oscillators\r
+ * as well as PLLs. The clocks derived from the system clock are\r
+ * sometimes also known as <em>synchronous clocks</em>, since they\r
+ * always run synchronously with respect to each other, as opposed to\r
+ * <em>generic clocks</em> which may run from different oscillators or\r
+ * PLLs.\r
+ *\r
+ * Most applications should simply call sysclk_init() to initialize\r
+ * everything related to the system clock and its source (oscillator,\r
+ * PLL or DFLL), and leave it at that. More advanced applications, and\r
+ * platform-specific drivers, may require additional services from the\r
+ * clock system, some of which may be platform-specific.\r
+ *\r
+ * \section sysclk_group_platform Platform Dependencies\r
+ *\r
+ * The sysclk API is partially chip- or platform-specific. While all\r
+ * platforms provide mostly the same functionality, there are some\r
+ * variations around how different bus types and clock tree structures\r
+ * are handled.\r
+ *\r
+ * The following functions are available on all platforms with the same\r
+ * parameters and functionality. These functions may be called freely by\r
+ * portable applications, drivers and services:\r
+ * - sysclk_init()\r
+ * - sysclk_set_source()\r
+ * - sysclk_get_main_hz()\r
+ * - sysclk_get_cpu_hz()\r
+ * - sysclk_get_peripheral_bus_hz()\r
+ *\r
+ * The following functions are available on all platforms, but there may\r
+ * be variations in the function signature (i.e. parameters) and\r
+ * behaviour. These functions are typically called by platform-specific\r
+ * parts of drivers, and applications that aren't intended to be\r
+ * portable:\r
+ * - sysclk_enable_peripheral_clock()\r
+ * - sysclk_disable_peripheral_clock()\r
+ * - sysclk_enable_module()\r
+ * - sysclk_disable_module()\r
+ * - sysclk_module_is_enabled()\r
+ * - sysclk_set_prescalers()\r
+ *\r
+ * All other functions should be considered platform-specific.\r
+ * Enabling/disabling clocks to specific peripherals as well as\r
+ * determining the speed of these clocks should be done by calling\r
+ * functions provided by the driver for that peripheral.\r
+ *\r
+ * @{\r
+ */\r
+\r
+//! \name System Clock Initialization\r
+//@{\r
+/**\r
+ * \fn void sysclk_init(void)\r
+ * \brief Initialize the synchronous clock system.\r
+ *\r
+ * This function will initialize the system clock and its source. This\r
+ * includes:\r
+ * - Mask all synchronous clocks except for any clocks which are\r
+ * essential for normal operation (for example internal memory\r
+ * clocks).\r
+ * - Set up the system clock prescalers as specified by the\r
+ * application's configuration file.\r
+ * - Enable the clock source specified by the application's\r
+ * configuration file (oscillator or PLL) and wait for it to become\r
+ * stable.\r
+ * - Set the main system clock source to the clock specified by the\r
+ * application's configuration file.\r
+ *\r
+ * Since all non-essential peripheral clocks are initially disabled, it\r
+ * is the responsibility of the peripheral driver to re-enable any\r
+ * clocks that are needed for normal operation.\r
+ */\r
+//@}\r
+\r
+//! @}\r
+\r
+#endif /* SYSCLK_H_INCLUDED */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Power Management Controller (PMC) driver for SAM.\r
+ *\r
+ * Copyright (c) 2011-2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#include "pmc.h"\r
+\r
+#if (SAM3N)\r
+# define MAX_PERIPH_ID 31\r
+#elif (SAM3XA)\r
+# define MAX_PERIPH_ID 44\r
+#elif (SAM3U)\r
+# define MAX_PERIPH_ID 29\r
+#elif (SAM3S || SAM4S)\r
+# define MAX_PERIPH_ID 34\r
+#endif\r
+\r
+/// @cond 0\r
+/**INDENT-OFF**/\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+/**INDENT-ON**/\r
+/// @endcond\r
+\r
+/**\r
+ * \defgroup sam_drivers_pmc_group Power Management Controller (PMC)\r
+ *\r
+ * \par Purpose\r
+ *\r
+ * The Power Management Controller (PMC) optimizes power consumption by controlling \r
+ * all system and user peripheral clocks. The PMC enables/disables the clock inputs \r
+ * to many of the peripherals and the Cortex-M Processor.\r
+ *\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * \brief Set the prescaler of the MCK. \r
+ *\r
+ * \param ul_pres Prescaler value.\r
+ */\r
+void pmc_mck_set_prescaler(uint32_t ul_pres)\r
+{\r
+ PMC->PMC_MCKR = \r
+ (PMC->PMC_MCKR & (~PMC_MCKR_PRES_Msk)) | ul_pres;\r
+ while (!(PMC->PMC_SR & PMC_SR_MCKRDY));\r
+}\r
+\r
+/**\r
+ * \brief Set the source of the MCK.\r
+ *\r
+ * \param ul_source Source selection value.\r
+ */\r
+void pmc_mck_set_source(uint32_t ul_source)\r
+{\r
+ PMC->PMC_MCKR = \r
+ (PMC->PMC_MCKR & (~PMC_MCKR_CSS_Msk)) | ul_source;\r
+ while (!(PMC->PMC_SR & PMC_SR_MCKRDY));\r
+}\r
+\r
+/**\r
+ * \brief Switch master clock source selection to slow clock.\r
+ *\r
+ * \param ul_pres Processor clock prescaler.\r
+ *\r
+ * \retval 0 Success.\r
+ * \retval 1 Timeout error.\r
+ */\r
+uint32_t pmc_switch_mck_to_sclk(uint32_t ul_pres)\r
+{\r
+ uint32_t ul_timeout;\r
+\r
+ PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_CSS_Msk)) | PMC_MCKR_CSS_SLOW_CLK;\r
+ for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY); --ul_timeout) {\r
+ if (ul_timeout == 0) {\r
+ return 1;\r
+ }\r
+ }\r
+\r
+ PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_PRES_Msk)) | ul_pres;\r
+ for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY); --ul_timeout) {\r
+ if (ul_timeout == 0) {\r
+ return 1;\r
+ }\r
+ }\r
+\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * \brief Switch master clock source selection to main clock.\r
+ *\r
+ * \param ul_pres Processor clock prescaler.\r
+ *\r
+ * \retval 0 Success.\r
+ * \retval 1 Timeout error.\r
+ */\r
+uint32_t pmc_switch_mck_to_mainck(uint32_t ul_pres)\r
+{\r
+ uint32_t ul_timeout;\r
+\r
+ PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_CSS_Msk)) |\r
+ PMC_MCKR_CSS_MAIN_CLK;\r
+ for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY);\r
+ --ul_timeout) {\r
+ if (ul_timeout == 0) {\r
+ return 1;\r
+ }\r
+ }\r
+\r
+ PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_PRES_Msk)) | ul_pres;\r
+ for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY);\r
+ --ul_timeout) {\r
+ if (ul_timeout == 0) {\r
+ return 1;\r
+ }\r
+ }\r
+\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * \brief Switch master clock source selection to PLLA clock.\r
+ *\r
+ * \param ul_pres Processor clock prescaler.\r
+ *\r
+ * \retval 0 Success.\r
+ * \retval 1 Timeout error.\r
+ */\r
+uint32_t pmc_switch_mck_to_pllack(uint32_t ul_pres)\r
+{\r
+ uint32_t ul_timeout;\r
+\r
+ PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_PRES_Msk)) | ul_pres;\r
+ for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY);\r
+ --ul_timeout) {\r
+ if (ul_timeout == 0) {\r
+ return 1;\r
+ }\r
+ }\r
+ \r
+ PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_CSS_Msk)) |\r
+ PMC_MCKR_CSS_PLLA_CLK;\r
+\r
+ for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY);\r
+ --ul_timeout) {\r
+ if (ul_timeout == 0) {\r
+ return 1;\r
+ }\r
+ }\r
+\r
+ return 0;\r
+}\r
+\r
+#if (SAM3S || SAM4S)\r
+/**\r
+ * \brief Switch master clock source selection to PLLB clock.\r
+ *\r
+ * \param ul_pres Processor clock prescaler.\r
+ *\r
+ * \retval 0 Success.\r
+ * \retval 1 Timeout error.\r
+ */\r
+uint32_t pmc_switch_mck_to_pllbck(uint32_t ul_pres)\r
+{\r
+ uint32_t ul_timeout;\r
+\r
+ PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_PRES_Msk)) | ul_pres;\r
+ for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY);\r
+ --ul_timeout) {\r
+ if (ul_timeout == 0) {\r
+ return 1;\r
+ }\r
+ }\r
+\r
+ PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_CSS_Msk)) |\r
+ PMC_MCKR_CSS_PLLB_CLK;\r
+ for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY);\r
+ --ul_timeout) {\r
+ if (ul_timeout == 0) {\r
+ return 1;\r
+ }\r
+ }\r
+\r
+ return 0;\r
+}\r
+#endif\r
+\r
+#if (SAM3XA || SAM3U)\r
+/**\r
+ * \brief Switch master clock source selection to UPLL clock.\r
+ *\r
+ * \param ul_pres Processor clock prescaler.\r
+ *\r
+ * \retval 0 Success.\r
+ * \retval 1 Timeout error.\r
+ */\r
+uint32_t pmc_switch_mck_to_upllck(uint32_t ul_pres)\r
+{\r
+ uint32_t ul_timeout;\r
+\r
+ PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_PRES_Msk)) | ul_pres;\r
+ for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY);\r
+ --ul_timeout) {\r
+ if (ul_timeout == 0) {\r
+ return 1;\r
+ }\r
+ }\r
+\r
+ PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_CSS_Msk)) |\r
+ PMC_MCKR_CSS_UPLL_CLK;\r
+ for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY);\r
+ --ul_timeout) {\r
+ if (ul_timeout == 0) {\r
+ return 1;\r
+ }\r
+ }\r
+\r
+ return 0;\r
+}\r
+#endif\r
+\r
+/**\r
+ * \brief Switch slow clock source selection to external 32k (Xtal or Bypass).\r
+ * \r
+ * \note This function disables the PLLs.\r
+ *\r
+ * \note Switching SCLK back to 32krc is only possible by shutting down the VDDIO\r
+ * power supply.\r
+ *\r
+ * \param ul_bypass 0 for Xtal, 1 for bypass.\r
+ */\r
+void pmc_switch_sclk_to_32kxtal(uint32_t ul_bypass)\r
+{\r
+ /* Set Bypass mode if required */\r
+ if (ul_bypass == 1) {\r
+ SUPC->SUPC_MR |= SUPC_MR_KEY(SUPC_KEY_VALUE) |\r
+ SUPC_MR_OSCBYPASS;\r
+ }\r
+\r
+ SUPC->SUPC_CR |= SUPC_CR_KEY(SUPC_KEY_VALUE) | SUPC_CR_XTALSEL;\r
+}\r
+\r
+/**\r
+ * \brief Check if the external 32k Xtal is ready.\r
+ *\r
+ * \retval 1 External 32k Xtal is ready.\r
+ * \retval 0 External 32k Xtal is not ready.\r
+ */\r
+uint32_t pmc_osc_is_ready_32kxtal(void)\r
+{\r
+ return ((SUPC->SUPC_SR & SUPC_SR_OSCSEL)\r
+ && (PMC->PMC_SR & PMC_SR_OSCSELS));\r
+}\r
+\r
+/**\r
+ * \brief Switch main clock source selection to internal fast RC.\r
+ *\r
+ * \param ul_moscrcf Fast RC oscillator(4/8/12Mhz).\r
+ *\r
+ * \retval 0 Success.\r
+ * \retval 1 Timeout error.\r
+ * \retval 2 Invalid frequency.\r
+ */\r
+void pmc_switch_mainck_to_fastrc(uint32_t ul_moscrcf)\r
+{\r
+ uint32_t ul_needXTEN = 0;\r
+\r
+ /* Enable Fast RC oscillator but DO NOT switch to RC now */\r
+ if (PMC->CKGR_MOR & CKGR_MOR_MOSCXTEN) {\r
+ PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCRCF_Msk) |\r
+ PMC_CKGR_MOR_KEY_VALUE | CKGR_MOR_MOSCRCEN |\r
+ ul_moscrcf;\r
+ } else {\r
+ ul_needXTEN = 1;\r
+ PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCRCF_Msk) |\r
+ PMC_CKGR_MOR_KEY_VALUE | CKGR_MOR_MOSCRCEN |\r
+ CKGR_MOR_MOSCXTEN | CKGR_MOR_MOSCXTST(PMC_XTAL_STARTUP_TIME) |\r
+ ul_moscrcf;\r
+ }\r
+\r
+ /* Wait the Fast RC to stabilize */\r
+ while (!(PMC->PMC_SR & PMC_SR_MOSCRCS));\r
+\r
+ /* Switch to Fast RC */\r
+ PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCSEL) | PMC_CKGR_MOR_KEY_VALUE;\r
+\r
+ // BUG FIX : clock_example3_sam3s does not switch sclk->mainck with XT disabled.\r
+ if (ul_needXTEN) {\r
+ PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCXTEN) |\r
+ PMC_CKGR_MOR_KEY_VALUE;\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Enable fast RC oscillator.\r
+ *\r
+ * \param ul_rc Fast RC oscillator(4/8/12Mhz).\r
+ */\r
+void pmc_osc_enable_fastrc(uint32_t ul_rc)\r
+{\r
+ /* Enable Fast RC oscillator but DO NOT switch to RC now. Keep MOSCSEL to 1 */\r
+ PMC->CKGR_MOR = PMC_CKGR_MOR_KEY_VALUE | CKGR_MOR_MOSCSEL |\r
+ CKGR_MOR_MOSCXTEN | CKGR_MOR_MOSCRCEN | ul_rc;\r
+ /* Wait the Fast RC to stabilize */\r
+ while (!(PMC->PMC_SR & PMC_SR_MOSCRCS));\r
+}\r
+\r
+/**\r
+ * \brief Disable the internal fast RC.\r
+ */\r
+void pmc_osc_disable_fastrc(void)\r
+{\r
+ /* Disable Fast RC oscillator */\r
+ PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCRCEN) | PMC_CKGR_MOR_KEY_VALUE;\r
+}\r
+\r
+/**\r
+ * \brief Switch main clock source selection to external Xtal/Bypass. \r
+ * The function may switch MCK to SCLK if MCK source is MAINCK to avoid any \r
+ * system crash.\r
+ *\r
+ * \note If used in Xtal mode, the Xtal is automatically enabled.\r
+ *\r
+ * \param ul_bypass 0 for Xtal, 1 for bypass.\r
+ *\r
+ * \retval 0 Success.\r
+ * \retval 1 Timeout error.\r
+ */\r
+void pmc_switch_mainck_to_xtal(uint32_t ul_bypass)\r
+{\r
+ /* Enable Main Xtal oscillator */\r
+ if (ul_bypass) {\r
+ PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCXTEN) |\r
+ PMC_CKGR_MOR_KEY_VALUE | CKGR_MOR_MOSCXTBY |\r
+ CKGR_MOR_MOSCSEL;\r
+ } else {\r
+ PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCXTBY) |\r
+ PMC_CKGR_MOR_KEY_VALUE | CKGR_MOR_MOSCXTEN |\r
+ CKGR_MOR_MOSCXTST(PMC_XTAL_STARTUP_TIME);\r
+ /* Wait the Xtal to stabilize */\r
+ while (!(PMC->PMC_SR & PMC_SR_MOSCXTS));\r
+\r
+ PMC->CKGR_MOR |= PMC_CKGR_MOR_KEY_VALUE | CKGR_MOR_MOSCSEL;\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Disable the external Xtal.\r
+ *\r
+ * \param ul_bypass 0 for Xtal, 1 for bypass.\r
+ */\r
+void pmc_osc_disable_xtal(uint32_t ul_bypass)\r
+{\r
+ /* Disable xtal oscillator */\r
+ if (ul_bypass) {\r
+ PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCXTBY) |\r
+ PMC_CKGR_MOR_KEY_VALUE;\r
+ } else {\r
+ PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCXTEN) |\r
+ PMC_CKGR_MOR_KEY_VALUE;\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Check if the MAINCK is ready. Depending on MOSCEL, MAINCK can be one\r
+ * of Xtal, bypass or internal RC.\r
+ *\r
+ * \retval 1 Xtal is ready.\r
+ * \retval 0 Xtal is not ready.\r
+ */\r
+uint32_t pmc_osc_is_ready_mainck(void)\r
+{\r
+ return PMC->PMC_SR & PMC_SR_MOSCSELS;\r
+}\r
+\r
+/**\r
+ * \brief Enable PLLA clock.\r
+ *\r
+ * \param mula PLLA multiplier.\r
+ * \param pllacount PLLA counter.\r
+ * \param diva Divider.\r
+ */\r
+void pmc_enable_pllack(uint32_t mula, uint32_t pllacount, uint32_t diva)\r
+{\r
+ pmc_disable_pllack(); // Hardware BUG FIX : first disable the PLL to unlock the lock! \r
+ // It occurs when re-enabling the PLL with the same parameters.\r
+\r
+ PMC->CKGR_PLLAR = CKGR_PLLAR_ONE | CKGR_PLLAR_DIVA(diva) |\r
+ CKGR_PLLAR_PLLACOUNT(pllacount) | CKGR_PLLAR_MULA(mula);\r
+ while ((PMC->PMC_SR & PMC_SR_LOCKA) == 0);\r
+}\r
+\r
+/**\r
+ * \brief Disable PLLA clock.\r
+ */\r
+void pmc_disable_pllack(void)\r
+{\r
+ PMC->CKGR_PLLAR = CKGR_PLLAR_ONE | CKGR_PLLAR_MULA(0);\r
+}\r
+\r
+/**\r
+ * \brief Is PLLA locked?\r
+ *\r
+ * \retval 0 Not locked.\r
+ * \retval 1 Locked.\r
+ */\r
+uint32_t pmc_is_locked_pllack(void)\r
+{\r
+ return (PMC->PMC_SR & PMC_SR_LOCKA);\r
+}\r
+\r
+#if (SAM3S || SAM4S)\r
+/**\r
+ * \brief Enable PLLB clock.\r
+ *\r
+ * \param mulb PLLB multiplier.\r
+ * \param pllbcount PLLB counter.\r
+ * \param divb Divider.\r
+ */\r
+void pmc_enable_pllbck(uint32_t mulb, uint32_t pllbcount, uint32_t divb)\r
+{\r
+ pmc_disable_pllbck(); // Hardware BUG FIX : first disable the PLL to unlock the lock! \r
+ // It occurs when re-enabling the PLL with the same parameters.\r
+ PMC->CKGR_PLLBR =\r
+ CKGR_PLLBR_DIVB(divb) | CKGR_PLLBR_PLLBCOUNT(pllbcount)\r
+ | CKGR_PLLBR_MULB(mulb);\r
+ while ((PMC->PMC_SR & PMC_SR_LOCKB) == 0);\r
+}\r
+\r
+/**\r
+ * \brief Disable PLLB clock.\r
+ */\r
+void pmc_disable_pllbck(void)\r
+{\r
+ PMC->CKGR_PLLBR = CKGR_PLLBR_MULB(0);\r
+}\r
+\r
+/**\r
+ * \brief Is PLLB locked?\r
+ *\r
+ * \retval 0 Not locked.\r
+ * \retval 1 Locked.\r
+ */\r
+uint32_t pmc_is_locked_pllbck(void)\r
+{\r
+ return (PMC->PMC_SR & PMC_SR_LOCKB);\r
+}\r
+#endif\r
+\r
+#if (SAM3XA || SAM3U)\r
+/**\r
+ * \brief Enable UPLL clock.\r
+ */\r
+void pmc_enable_upll_clock(void)\r
+{\r
+ PMC->CKGR_UCKR = CKGR_UCKR_UPLLCOUNT(3) | CKGR_UCKR_UPLLEN;\r
+\r
+ /* Wait UTMI PLL Lock Status */\r
+ while (!(PMC->PMC_SR & PMC_SR_LOCKU));\r
+}\r
+\r
+/**\r
+ * \brief Disable UPLL clock.\r
+ */\r
+void pmc_disable_upll_clock(void)\r
+{\r
+ PMC->CKGR_UCKR &= ~CKGR_UCKR_UPLLEN;\r
+}\r
+\r
+/**\r
+ * \brief Is UPLL locked?\r
+ *\r
+ * \retval 0 Not locked.\r
+ * \retval 1 Locked.\r
+ */\r
+uint32_t pmc_is_locked_upll(void)\r
+{\r
+ return (PMC->PMC_SR & PMC_SR_LOCKU);\r
+}\r
+#endif\r
+\r
+/**\r
+ * \brief Enable the specified peripheral clock.\r
+ *\r
+ * \note The ID must NOT be shifted (i.e., 1 << ID_xxx).\r
+ *\r
+ * \param ul_id Peripheral ID (ID_xxx).\r
+ *\r
+ * \retval 0 Success.\r
+ * \retval 1 Invalid parameter.\r
+ */\r
+uint32_t pmc_enable_periph_clk(uint32_t ul_id)\r
+{\r
+ if (ul_id > MAX_PERIPH_ID) {\r
+ return 1;\r
+ }\r
+\r
+ if (ul_id < 32) {\r
+ if ((PMC->PMC_PCSR0 & (1u << ul_id)) != (1u << ul_id)) {\r
+ PMC->PMC_PCER0 = 1 << ul_id;\r
+ }\r
+#if (SAM3S || SAM3XA || SAM4S)\r
+ } else {\r
+ ul_id -= 32;\r
+ if ((PMC->PMC_PCSR1 & (1u << ul_id)) != (1u << ul_id)) {\r
+ PMC->PMC_PCER1 = 1 << ul_id;\r
+ }\r
+#endif\r
+ }\r
+ \r
+ return 0;\r
+}\r
+\r
+/**\r
+ * \brief Disable the specified peripheral clock.\r
+ *\r
+ * \note The ID must NOT be shifted (i.e., 1 << ID_xxx).\r
+ *\r
+ * \param ul_id Peripheral ID (ID_xxx).\r
+ *\r
+ * \retval 0 Success.\r
+ * \retval 1 Invalid parameter.\r
+ */\r
+uint32_t pmc_disable_periph_clk(uint32_t ul_id)\r
+{\r
+ if (ul_id > MAX_PERIPH_ID) {\r
+ return 1;\r
+ }\r
+\r
+ if (ul_id < 32) {\r
+ if ((PMC->PMC_PCSR0 & (1u << ul_id)) == (1u << ul_id)) {\r
+ PMC->PMC_PCDR0 = 1 << ul_id;\r
+ }\r
+#if (SAM3S || SAM3XA || SAM4S)\r
+ } else {\r
+ ul_id -= 32;\r
+ if ((PMC->PMC_PCSR1 & (1u << ul_id)) == (1u << ul_id)) {\r
+ PMC->PMC_PCDR1 = 1 << ul_id;\r
+ }\r
+#endif\r
+ }\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * \brief Enable all peripheral clocks.\r
+ */\r
+void pmc_enable_all_periph_clk(void)\r
+{\r
+ PMC->PMC_PCER0 = PMC_MASK_STATUS0;\r
+ while ((PMC->PMC_PCSR0 & PMC_MASK_STATUS0) != PMC_MASK_STATUS0);\r
+\r
+#if (SAM3S || SAM3XA || SAM4S)\r
+ PMC->PMC_PCER1 = PMC_MASK_STATUS1;\r
+ while ((PMC->PMC_PCSR1 & PMC_MASK_STATUS1) != PMC_MASK_STATUS1);\r
+#endif\r
+}\r
+\r
+/**\r
+ * \brief Disable all peripheral clocks.\r
+ */\r
+void pmc_disable_all_periph_clk(void)\r
+{\r
+ PMC->PMC_PCDR0 = PMC_MASK_STATUS0;\r
+ while ((PMC->PMC_PCSR0 & PMC_MASK_STATUS0) != 0);\r
+ \r
+#if (SAM3S || SAM3XA || SAM4S)\r
+ PMC->PMC_PCDR1 = PMC_MASK_STATUS1;\r
+ while ((PMC->PMC_PCSR1 & PMC_MASK_STATUS1) != 0);\r
+#endif\r
+}\r
+\r
+/**\r
+ * \brief Check if the specified peripheral clock is enabled.\r
+ *\r
+ * \note The ID must NOT be shifted (i.e., 1 << ID_xxx).\r
+ *\r
+ * \param ul_id Peripheral ID (ID_xxx).\r
+ *\r
+ * \retval 0 Peripheral clock is disabled or unknown.\r
+ * \retval 1 Peripheral clock is enabled.\r
+ */\r
+uint32_t pmc_is_periph_clk_enabled(uint32_t ul_id)\r
+{\r
+ if (ul_id > MAX_PERIPH_ID) {\r
+ return 0;\r
+ }\r
+\r
+#if (SAM3S || SAM3XA || SAM4S)\r
+ if (ul_id < 32) {\r
+#endif\r
+ if ((PMC->PMC_PCSR0 & (1u << ul_id))) {\r
+ return 1;\r
+ } else {\r
+ return 0;\r
+ }\r
+#if (SAM3S || SAM3XA || SAM4S)\r
+ } else {\r
+ ul_id -= 32;\r
+ if ((PMC->PMC_PCSR1 & (1u << ul_id))) {\r
+ return 1;\r
+ } else {\r
+ return 0;\r
+ }\r
+ }\r
+#endif\r
+}\r
+\r
+/**\r
+ * \brief Set the prescaler for the specified programmable clock.\r
+ *\r
+ * \param ul_id Peripheral ID.\r
+ * \param ul_pres Prescaler value.\r
+ */\r
+void pmc_pck_set_prescaler(uint32_t ul_id, uint32_t ul_pres)\r
+{\r
+ PMC->PMC_PCK[ul_id] =\r
+ (PMC->PMC_PCK[ul_id] & ~PMC_PCK_PRES_Msk) | ul_pres;\r
+ while ((PMC->PMC_SCER & (PMC_SCER_PCK0 << ul_id))\r
+ && !(PMC->PMC_SR & (PMC_SR_PCKRDY0 << ul_id)));\r
+}\r
+\r
+/**\r
+ * \brief Set the source oscillator for the specified programmable clock.\r
+ *\r
+ * \param ul_id Peripheral ID.\r
+ * \param ul_source Source selection value.\r
+ */\r
+void pmc_pck_set_source(uint32_t ul_id, uint32_t ul_source)\r
+{\r
+ PMC->PMC_PCK[ul_id] =\r
+ (PMC->PMC_PCK[ul_id] & ~PMC_PCK_CSS_Msk) | ul_source;\r
+ while ((PMC->PMC_SCER & (PMC_SCER_PCK0 << ul_id))\r
+ && !(PMC->PMC_SR & (PMC_SR_PCKRDY0 << ul_id)));\r
+}\r
+\r
+/**\r
+ * \brief Switch programmable clock source selection to slow clock.\r
+ *\r
+ * \param ul_id Id of the programmable clock.\r
+ * \param ul_pres Programmable clock prescaler.\r
+ *\r
+ * \retval 0 Success.\r
+ * \retval 1 Timeout error.\r
+ */\r
+uint32_t pmc_switch_pck_to_sclk(uint32_t ul_id, uint32_t ul_pres)\r
+{\r
+ uint32_t ul_timeout;\r
+\r
+ PMC->PMC_PCK[ul_id] = PMC_PCK_CSS_SLOW_CLK | ul_pres;\r
+ for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & (PMC_SR_PCKRDY0 << ul_id));\r
+ --ul_timeout) {\r
+ if (ul_timeout == 0) {\r
+ return 1;\r
+ }\r
+ }\r
+\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * \brief Switch programmable clock source selection to main clock.\r
+ *\r
+ * \param ul_id Id of the programmable clock.\r
+ * \param ul_pres Programmable clock prescaler.\r
+ *\r
+ * \retval 0 Success.\r
+ * \retval 1 Timeout error.\r
+ */\r
+uint32_t pmc_switch_pck_to_mainck(uint32_t ul_id, uint32_t ul_pres)\r
+{\r
+ uint32_t ul_timeout;\r
+\r
+ PMC->PMC_PCK[ul_id] = PMC_PCK_CSS_MAIN_CLK | ul_pres;\r
+ for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & (PMC_SR_PCKRDY0 << ul_id));\r
+ --ul_timeout) {\r
+ if (ul_timeout == 0) {\r
+ return 1;\r
+ }\r
+ }\r
+\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * \brief Switch programmable clock source selection to PLLA clock.\r
+ *\r
+ * \param ul_id Id of the programmable clock.\r
+ * \param ul_pres Programmable clock prescaler.\r
+ *\r
+ * \retval 0 Success.\r
+ * \retval 1 Timeout error.\r
+ */\r
+uint32_t pmc_switch_pck_to_pllack(uint32_t ul_id, uint32_t ul_pres)\r
+{\r
+ uint32_t ul_timeout;\r
+\r
+ PMC->PMC_PCK[ul_id] = PMC_PCK_CSS_PLLA_CLK | ul_pres;\r
+ for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & (PMC_SR_PCKRDY0 << ul_id));\r
+ --ul_timeout) {\r
+ if (ul_timeout == 0) {\r
+ return 1;\r
+ }\r
+ }\r
+\r
+ return 0;\r
+}\r
+\r
+#if (SAM3S || SAM4S)\r
+/**\r
+ * \brief Switch programmable clock source selection to PLLB clock.\r
+ *\r
+ * \param ul_id Id of the programmable clock.\r
+ * \param ul_pres Programmable clock prescaler.\r
+ *\r
+ * \retval 0 Success.\r
+ * \retval 1 Timeout error.\r
+ */\r
+uint32_t pmc_switch_pck_to_pllbck(uint32_t ul_id, uint32_t ul_pres)\r
+{\r
+ uint32_t ul_timeout;\r
+\r
+ PMC->PMC_PCK[ul_id] = PMC_PCK_CSS_PLLB_CLK | ul_pres;\r
+ for (ul_timeout = PMC_TIMEOUT;\r
+ !(PMC->PMC_SR & (PMC_SR_PCKRDY0 << ul_id));\r
+ --ul_timeout) {\r
+ if (ul_timeout == 0) {\r
+ return 1;\r
+ }\r
+ }\r
+\r
+ return 0;\r
+}\r
+#endif\r
+\r
+#if (SAM3XA || SAM3U)\r
+/**\r
+ * \brief Switch programmable clock source selection to UPLL clock.\r
+ *\r
+ * \param ul_id Id of the programmable clock.\r
+ * \param ul_pres Programmable clock prescaler.\r
+ *\r
+ * \retval 0 Success.\r
+ * \retval 1 Timeout error.\r
+ */\r
+uint32_t pmc_switch_pck_to_upllck(uint32_t ul_id, uint32_t ul_pres)\r
+{\r
+ uint32_t ul_timeout;\r
+\r
+ PMC->PMC_PCK[ul_id] = PMC_PCK_CSS_UPLL_CLK | ul_pres;\r
+ for (ul_timeout = PMC_TIMEOUT;\r
+ !(PMC->PMC_SR & (PMC_SR_PCKRDY0 << ul_id));\r
+ --ul_timeout) {\r
+ if (ul_timeout == 0) {\r
+ return 1;\r
+ }\r
+ }\r
+\r
+ return 0;\r
+}\r
+#endif\r
+\r
+/**\r
+ * \brief Enable the specified programmable clock.\r
+ *\r
+ * \param ul_id Id of the programmable clock.\r
+ */\r
+void pmc_enable_pck(uint32_t ul_id)\r
+{\r
+ PMC->PMC_SCER = PMC_SCER_PCK0 << ul_id;\r
+}\r
+\r
+/**\r
+ * \brief Disable the specified programmable clock.\r
+ *\r
+ * \param ul_id Id of the programmable clock.\r
+ */\r
+void pmc_disable_pck(uint32_t ul_id)\r
+{\r
+ PMC->PMC_SCDR = PMC_SCER_PCK0 << ul_id;\r
+}\r
+\r
+/**\r
+ * \brief Enable all programmable clocks.\r
+ */\r
+void pmc_enable_all_pck(void)\r
+{\r
+ PMC->PMC_SCER = PMC_SCER_PCK0 | PMC_SCER_PCK1 | PMC_SCER_PCK2;\r
+}\r
+\r
+/**\r
+ * \brief Disable all programmable clocks.\r
+ */\r
+void pmc_disable_all_pck(void)\r
+{\r
+ PMC->PMC_SCDR = PMC_SCDR_PCK0 | PMC_SCDR_PCK1 | PMC_SCDR_PCK2;\r
+}\r
+\r
+/**\r
+ * \brief Check if the specified programmable clock is enabled.\r
+ *\r
+ * \param ul_id Id of the programmable clock.\r
+ *\r
+ * \retval 0 Programmable clock is disabled or unknown.\r
+ * \retval 1 Programmable clock is enabled.\r
+ */\r
+uint32_t pmc_is_pck_enabled(uint32_t ul_id)\r
+{\r
+ if (ul_id > 2) {\r
+ return 0;\r
+ }\r
+\r
+ return (PMC->PMC_SCSR & (PMC_SCSR_PCK0 << ul_id));\r
+}\r
+\r
+#if (SAM3S || SAM3XA || SAM4S)\r
+/**\r
+ * \brief Switch UDP (USB) clock source selection to PLLA clock.\r
+ *\r
+ * \param ul_usbdiv Clock divisor.\r
+ */\r
+void pmc_switch_udpck_to_pllack(uint32_t ul_usbdiv)\r
+{\r
+ PMC->PMC_USB = PMC_USB_USBDIV(ul_usbdiv);\r
+}\r
+#endif\r
+\r
+#if (SAM3S || SAM4S)\r
+/**\r
+ * \brief Switch UDP (USB) clock source selection to PLLB clock.\r
+ *\r
+ * \param ul_usbdiv Clock divisor.\r
+ */\r
+void pmc_switch_udpck_to_pllbck(uint32_t ul_usbdiv)\r
+{\r
+ PMC->PMC_USB = PMC_USB_USBDIV(ul_usbdiv) | PMC_USB_USBS;\r
+}\r
+#endif\r
+\r
+#if (SAM3XA)\r
+/**\r
+ * \brief Switch UDP (USB) clock source selection to UPLL clock.\r
+ *\r
+ * \param dw_usbdiv Clock divisor.\r
+ */\r
+void pmc_switch_udpck_to_upllck(uint32_t ul_usbdiv)\r
+{\r
+ PMC->PMC_USB = PMC_USB_USBS | PMC_USB_USBDIV(ul_usbdiv);\r
+}\r
+#endif\r
+\r
+#if (SAM3S || SAM3XA || SAM4S)\r
+/**\r
+ * \brief Enable UDP (USB) clock.\r
+ */\r
+void pmc_enable_udpck(void)\r
+{\r
+# if (SAM3S || SAM4S)\r
+ PMC->PMC_SCER = PMC_SCER_UDP;\r
+# else\r
+ PMC->PMC_SCER = PMC_SCER_UOTGCLK;\r
+# endif\r
+}\r
+\r
+/**\r
+ * \brief Disable UDP (USB) clock.\r
+ */\r
+void pmc_disable_udpck(void)\r
+{\r
+# if (SAM3S || SAM4S)\r
+ PMC->PMC_SCDR = PMC_SCDR_UDP;\r
+# else\r
+ PMC->PMC_SCDR = PMC_SCDR_UOTGCLK;\r
+# endif\r
+}\r
+#endif\r
+\r
+/** \r
+ * \brief Enable PMC interrupts.\r
+ *\r
+ * \param ul_sources Interrupt sources bit map.\r
+ */\r
+void pmc_enable_interrupt(uint32_t ul_sources)\r
+{\r
+ PMC->PMC_IER = ul_sources;\r
+}\r
+\r
+/** \r
+ * \brief Disable PMC interrupts.\r
+ *\r
+ * \param ul_sources Interrupt sources bit map.\r
+ */\r
+void pmc_disable_interrupt(uint32_t ul_sources)\r
+{\r
+ PMC->PMC_IDR = ul_sources;\r
+}\r
+\r
+/** \r
+ * \brief Get PMC interrupt mask.\r
+ *\r
+ * \return The interrupt mask value.\r
+ */\r
+uint32_t pmc_get_interrupt_mask(void)\r
+{\r
+ return PMC->PMC_IMR;\r
+}\r
+\r
+/**\r
+ * \brief Get current status.\r
+ *\r
+ * \return The current PMC status.\r
+ */\r
+uint32_t pmc_get_status(void)\r
+{\r
+ return PMC->PMC_SR;\r
+}\r
+\r
+/**\r
+ * \brief Set the wake-up inputs for fast startup mode registers (event generation).\r
+ *\r
+ * \param ul_inputs Wake up inputs to enable.\r
+ */\r
+void pmc_set_fast_startup_input(uint32_t ul_inputs)\r
+{\r
+ ul_inputs &= (~ PMC_FAST_STARTUP_Msk);\r
+ PMC->PMC_FSMR |= ul_inputs;\r
+}\r
+\r
+/**\r
+ * \brief Clear the wake-up inputs for fast startup mode registers (remove event generation).\r
+ *\r
+ * \param ul_inputs Wake up inputs to disable.\r
+ */\r
+void pmc_clr_fast_startup_input(uint32_t ul_inputs)\r
+{\r
+ ul_inputs &= (~ PMC_FAST_STARTUP_Msk);\r
+ PMC->PMC_FSMR &= ~ul_inputs;\r
+}\r
+\r
+/**\r
+ * \brief Enable Sleep Mode.\r
+ * Enter condition: (WFE or WFI) + (SLEEPDEEP bit = 0) + (LPM bit = 0)\r
+ *\r
+ * \param uc_type 0 for wait for interrupt, 1 for wait for event.\r
+ */\r
+void pmc_enable_sleepmode(uint8_t uc_type)\r
+{\r
+ PMC->PMC_FSMR &= (uint32_t) ~ PMC_FSMR_LPM; // Enter Sleep mode\r
+ SCB->SCR &= (uint32_t) ~ SCB_SCR_SLEEPDEEP_Msk; // Deep sleep\r
+\r
+ if (uc_type == 0) {\r
+ __WFI();\r
+ } else {\r
+ __WFE();\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Enable Wait Mode. \r
+ * Enter condition: WFE + (SLEEPDEEP bit = 0) + (LPM bit = 1)\r
+ */\r
+void pmc_enable_waitmode(void)\r
+{\r
+ uint32_t i;\r
+\r
+ PMC->PMC_FSMR |= PMC_FSMR_LPM; // Enter Wait mode\r
+ SCB->SCR &= (uint32_t) ~ SCB_SCR_SLEEPDEEP_Msk; // Deep sleep\r
+ __WFE();\r
+\r
+ /* Waiting for MOSCRCEN bit cleared is strongly recommended\r
+ * to ensure that the core will not execute undesired instructions\r
+ */\r
+ for (i = 0; i < 500; i++) {\r
+ __NOP();\r
+ }\r
+ while (!(PMC->CKGR_MOR & CKGR_MOR_MOSCRCEN));\r
+}\r
+\r
+/**\r
+ * \brief Enable Backup Mode. \r
+ * Enter condition: WFE + (SLEEPDEEP bit = 1)\r
+ */\r
+void pmc_enable_backupmode(void)\r
+{\r
+ SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;\r
+ __WFE();\r
+}\r
+\r
+/** \r
+ * \brief Enable or disable write protect of PMC registers.\r
+ *\r
+ * \param ul_enable 1 to enable, 0 to disable.\r
+ */\r
+void pmc_set_writeprotect(uint32_t ul_enable)\r
+{\r
+ if (ul_enable) {\r
+ PMC->PMC_WPMR = PMC_WPMR_WPKEY_VALUE | PMC_WPMR_WPEN;\r
+ } else {\r
+ PMC->PMC_WPMR = PMC_WPMR_WPKEY_VALUE;\r
+ }\r
+}\r
+\r
+/** \r
+ * \brief Return write protect status.\r
+ *\r
+ * \retval 0 Protection disabled.\r
+ * \retval 1 Protection enabled.\r
+ */\r
+uint32_t pmc_get_writeprotect_status(void)\r
+{\r
+ return PMC->PMC_WPMR & PMC_WPMR_WPEN;\r
+}\r
+\r
+/// @cond 0\r
+/**INDENT-OFF**/\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+/**INDENT-ON**/\r
+/// @endcond\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Power Management Controller (PMC) driver for SAM.\r
+ *\r
+ * Copyright (c) 2011-2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef PMC_H_INCLUDED\r
+#define PMC_H_INCLUDED\r
+\r
+#include "compiler.h"\r
+\r
+/// @cond 0\r
+/**INDENT-OFF**/\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+/**INDENT-ON**/\r
+/// @endcond\r
+\r
+/** Bit mask for peripheral clocks (PCER0) */\r
+#define PMC_MASK_STATUS0 (0xFFFFFFFC)\r
+\r
+/** Bit mask for peripheral clocks (PCER1) */\r
+#define PMC_MASK_STATUS1 (0xFFFFFFFF)\r
+\r
+/** Loop counter timeout value */\r
+#define PMC_TIMEOUT (2048)\r
+\r
+/** Key to unlock CKGR_MOR register */\r
+#define PMC_CKGR_MOR_KEY_VALUE CKGR_MOR_KEY(0x37)\r
+\r
+/** Key used to write SUPC registers */\r
+#define SUPC_KEY_VALUE ((uint32_t) 0xA5)\r
+\r
+/** PMC xtal statup time */\r
+#define PMC_XTAL_STARTUP_TIME (0x3F)\r
+\r
+/** Mask to access fast startup input */\r
+#define PMC_FAST_STARTUP_Msk (0xFFFFu)\r
+\r
+/** PMC_WPMR Write Protect KEY, unlock it */\r
+#define PMC_WPMR_WPKEY_VALUE PMC_WPMR_WPKEY((uint32_t) 0x504D43)\r
+\r
+/** Using external oscillator */\r
+#define PMC_OSC_XTAL 0\r
+\r
+/** Oscillator in bypass mode */\r
+#define PMC_OSC_BYPASS 1\r
+\r
+#define PMC_PCK_0 0 /* PCK0 ID */\r
+#define PMC_PCK_1 1 /* PCK1 ID */\r
+#define PMC_PCK_2 2 /* PCK2 ID */\r
+\r
+/**\r
+ * \name Master clock (MCK) Source and Prescaler configuration\r
+ *\r
+ * The following functions may be used to select the clock source and\r
+ * prescaler for the master clock.\r
+ */\r
+//@{\r
+\r
+void pmc_mck_set_prescaler(uint32_t ul_pres);\r
+void pmc_mck_set_source(uint32_t ul_source);\r
+uint32_t pmc_switch_mck_to_sclk(uint32_t ul_pres);\r
+uint32_t pmc_switch_mck_to_mainck(uint32_t ul_pres);\r
+uint32_t pmc_switch_mck_to_pllack(uint32_t ul_pres);\r
+#if (SAM3S || SAM4S)\r
+uint32_t pmc_switch_mck_to_pllbck(uint32_t ul_pres);\r
+#endif\r
+#if (SAM3XA || SAM3U)\r
+uint32_t pmc_switch_mck_to_upllck(uint32_t ul_pres);\r
+#endif\r
+\r
+//@}\r
+\r
+/**\r
+ * \name Slow clock (SLCK) oscillator and configuration\r
+ *\r
+ */\r
+//@{\r
+\r
+void pmc_switch_sclk_to_32kxtal(uint32_t ul_bypass);\r
+uint32_t pmc_osc_is_ready_32kxtal(void);\r
+\r
+//@}\r
+\r
+/**\r
+ * \name Main Clock (MAINCK) oscillator and configuration\r
+ *\r
+ */\r
+//@{\r
+\r
+void pmc_switch_mainck_to_fastrc(uint32_t ul_moscrcf);\r
+void pmc_osc_enable_fastrc(uint32_t ul_rc);\r
+void pmc_osc_disable_fastrc(void);\r
+void pmc_switch_mainck_to_xtal(uint32_t ul_bypass);\r
+void pmc_osc_disable_xtal(uint32_t ul_bypass);\r
+uint32_t pmc_osc_is_ready_mainck(void);\r
+\r
+//@}\r
+\r
+/**\r
+ * \name PLL oscillator and configuration\r
+ *\r
+ */\r
+//@{\r
+\r
+void pmc_enable_pllack(uint32_t mula, uint32_t pllacount, uint32_t diva);\r
+void pmc_disable_pllack(void);\r
+uint32_t pmc_is_locked_pllack(void);\r
+\r
+#if (SAM3S || SAM4S)\r
+void pmc_enable_pllbck(uint32_t mulb, uint32_t pllbcount, uint32_t divb);\r
+void pmc_disable_pllbck(void);\r
+uint32_t pmc_is_locked_pllbck(void);\r
+#endif\r
+\r
+#if (SAM3XA || SAM3U)\r
+void pmc_enable_upll_clock(void);\r
+void pmc_disable_upll_clock(void);\r
+uint32_t pmc_is_locked_upll(void);\r
+#endif\r
+\r
+//@}\r
+\r
+/**\r
+ * \name Peripherals clock configuration\r
+ *\r
+ */\r
+//@{\r
+\r
+uint32_t pmc_enable_periph_clk(uint32_t ul_id);\r
+uint32_t pmc_disable_periph_clk(uint32_t ul_id);\r
+void pmc_enable_all_periph_clk(void);\r
+void pmc_disable_all_periph_clk(void);\r
+uint32_t pmc_is_periph_clk_enabled(uint32_t ul_id);\r
+\r
+//@}\r
+\r
+/**\r
+ * \name Programmable clock Source and Prescaler configuration\r
+ *\r
+ * The following functions may be used to select the clock source and\r
+ * prescaler for the specified programmable clock.\r
+ */\r
+//@{\r
+\r
+void pmc_pck_set_prescaler(uint32_t ul_id, uint32_t ul_pres);\r
+void pmc_pck_set_source(uint32_t ul_id, uint32_t ul_source);\r
+uint32_t pmc_switch_pck_to_sclk(uint32_t ul_id, uint32_t ul_pres);\r
+uint32_t pmc_switch_pck_to_mainck(uint32_t ul_id, uint32_t ul_pres);\r
+uint32_t pmc_switch_pck_to_pllack(uint32_t ul_id, uint32_t ul_pres);\r
+#if (SAM3S || SAM4S)\r
+uint32_t pmc_switch_pck_to_pllbck(uint32_t ul_id, uint32_t ul_pres);\r
+#endif\r
+#if (SAM3XA || SAM3U)\r
+uint32_t pmc_switch_pck_to_upllck(uint32_t ul_id, uint32_t ul_pres);\r
+#endif\r
+void pmc_enable_pck(uint32_t ul_id);\r
+void pmc_disable_pck(uint32_t ul_id);\r
+void pmc_enable_all_pck(void);\r
+void pmc_disable_all_pck(void);\r
+uint32_t pmc_is_pck_enabled(uint32_t ul_id);\r
+\r
+//@}\r
+\r
+/**\r
+ * \name USB clock configuration\r
+ *\r
+ */\r
+//@{\r
+\r
+#if (SAM3S || SAM3XA || SAM4S)\r
+void pmc_switch_udpck_to_pllack(uint32_t ul_usbdiv);\r
+#endif\r
+#if (SAM3S || SAM4S)\r
+void pmc_switch_udpck_to_pllbck(uint32_t ul_usbdiv);\r
+#endif\r
+#if (SAM3XA)\r
+void pmc_switch_udpck_to_upllck(uint32_t ul_usbdiv);\r
+#endif\r
+#if (SAM3S || SAM3XA || SAM4S)\r
+void pmc_enable_udpck(void);\r
+void pmc_disable_udpck(void);\r
+#endif\r
+\r
+//@}\r
+\r
+/**\r
+ * \name Interrupt and status management\r
+ *\r
+ */\r
+//@{\r
+\r
+void pmc_enable_interrupt(uint32_t ul_sources);\r
+void pmc_disable_interrupt(uint32_t ul_sources);\r
+uint32_t pmc_get_interrupt_mask(void);\r
+uint32_t pmc_get_status(void);\r
+\r
+//@}\r
+\r
+/**\r
+ * \name Power management\r
+ *\r
+ * The following functions are used to configure sleep mode and additionnal \r
+ * wake up inputs.\r
+ */\r
+//@{\r
+\r
+void pmc_set_fast_startup_input(uint32_t ul_inputs);\r
+void pmc_clr_fast_startup_input(uint32_t ul_inputs);\r
+void pmc_enable_sleepmode(uint8_t uc_type);\r
+void pmc_enable_waitmode(void);\r
+void pmc_enable_backupmode(void);\r
+\r
+//@}\r
+\r
+/**\r
+ * \name Write protection\r
+ *\r
+ */\r
+//@{\r
+\r
+void pmc_set_writeprotect(uint32_t ul_enable);\r
+uint32_t pmc_get_writeprotect_status(void);\r
+\r
+//@}\r
+\r
+/// @cond 0\r
+/**INDENT-OFF**/\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+/**INDENT-ON**/\r
+/// @endcond\r
+\r
+//! @}\r
+\r
+/**\r
+ * \page sam_pmc_quickstart Quick start guide for the SAM PMC module\r
+ *\r
+ * This is the quick start guide for the \ref pmc_group "PMC module", with\r
+ * step-by-step instructions on how to configure and use the driver in a\r
+ * selection of use cases.\r
+ *\r
+ * The use cases contain several code fragments. The code fragments in the\r
+ * steps for setup can be copied into a custom initialization function, while\r
+ * the steps for usage can be copied into, e.g., the main application function.\r
+ *\r
+ * \section pmc_use_cases PMC use cases\r
+ * - \ref pmc_basic_use_case Basic use case - Switch Main Clock sources\r
+ * - \ref pmc_use_case_2 Advanced use case - Configure Programmable Clocks\r
+ *\r
+ * \section pmc_basic_use_case Basic use case - Switch Main Clock sources\r
+ * In this use case, the PMC module is configured for a variety of system clock\r
+ * sources and speeds. A LED is used to visually indicate the current clock\r
+ * speed as the source is switched.\r
+ *\r
+ * \section pmc_basic_use_case_setup Setup\r
+ *\r
+ * \subsection pmc_basic_use_case_setup_prereq Prerequisites\r
+ * -# \ref gpio_group "General Purpose I/O Management (gpio)"\r
+ *\r
+ * \subsection pmc_basic_use_case_setup_code Code\r
+ * The following function needs to be added to the user application, to flash a\r
+ * board LED a variable number of times at a rate given in CPU ticks.\r
+ * \r
+ * \code\r
+ * #define FLASH_TICK_COUNT 0x00012345\r
+ *\r
+ * void flash_led(uint32_t tick_count, uint8_t flash_count)\r
+ * {\r
+ * SysTick->CTRL = SysTick_CTRL_ENABLE_Msk;\r
+ * SysTick->LOAD = tick_count;\r
+ * \r
+ * while (flash_count--)\r
+ * {\r
+ * gpio_toggle_pin(LED0_GPIO);\r
+ * while (!(SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk));\r
+ * gpio_toggle_pin(LED0_GPIO);\r
+ * while (!(SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk));\r
+ * }\r
+ * }\r
+ * \endcode\r
+ *\r
+ * \section pmc_basic_use_case_usage Use case\r
+ *\r
+ * \subsection pmc_basic_use_case_usage_code Example code\r
+ * Add to application C-file:\r
+ * \code\r
+ * for (;;)\r
+ * {\r
+ * pmc_switch_mainck_to_fastrc(CKGR_MOR_MOSCRCF_12_MHz);\r
+ * flash_led(FLASH_TICK_COUNT, 5);\r
+ * pmc_switch_mainck_to_fastrc(CKGR_MOR_MOSCRCF_8_MHz);\r
+ * flash_led(FLASH_TICK_COUNT, 5);\r
+ * pmc_switch_mainck_to_fastrc(CKGR_MOR_MOSCRCF_4_MHz);\r
+ * flash_led(FLASH_TICK_COUNT, 5);\r
+ * pmc_switch_mainck_to_xtal(0);\r
+ * flash_led(FLASH_TICK_COUNT, 5);\r
+ * }\r
+ * \endcode\r
+ *\r
+ * \subsection pmc_basic_use_case_usage_flow Workflow\r
+ * -# Wrap the code in an infinite loop:\r
+ * \code\r
+ * for (;;)\r
+ * \endcode\r
+ * -# Switch the Master CPU frequency to the internal 12MHz RC oscillator, flash\r
+ * a LED on the board several times:\r
+ * \code\r
+ * pmc_switch_mainck_to_fastrc(CKGR_MOR_MOSCRCF_12_MHz);\r
+ * flash_led(FLASH_TICK_COUNT, 5); \r
+ * \endcode\r
+ * -# Switch the Master CPU frequency to the internal 8MHz RC oscillator, flash\r
+ * a LED on the board several times:\r
+ * \code\r
+ * pmc_switch_mainck_to_fastrc(CKGR_MOR_MOSCRCF_8_MHz);\r
+ * flash_led(FLASH_TICK_COUNT, 5); \r
+ * \endcode\r
+ * -# Switch the Master CPU frequency to the internal 4MHz RC oscillator, flash\r
+ * a LED on the board several times:\r
+ * \code\r
+ * pmc_switch_mainck_to_fastrc(CKGR_MOR_MOSCRCF_4_MHz);\r
+ * flash_led(FLASH_TICK_COUNT, 5); \r
+ * \endcode\r
+ * -# Switch the Master CPU frequency to the external crystal oscillator, flash\r
+ * a LED on the board several times:\r
+ * \code\r
+ * pmc_switch_mainck_to_xtal(0);\r
+ * flash_led(FLASH_TICK_COUNT, 5); \r
+ * \endcode\r
+ */\r
+\r
+/**\r
+ * \page pmc_use_case_2 Use case #2 - Configure Programmable Clocks\r
+ * In this use case, the PMC module is configured to start the Slow Clock from\r
+ * an attached 32KHz crystal, and start one of the Programmable Clock modules\r
+ * sourced from the Slow Clock divided down with a prescale factor of 64.\r
+ *\r
+ * \section pmc_use_case_2_setup Setup\r
+ *\r
+ * \subsection pmc_use_case_2_setup_prereq Prerequisites\r
+ * -# \ref pio_group "Parallel Input/Output Controller (pio)"\r
+ *\r
+ * \subsection pmc_use_case_2_setup_code Code\r
+ * The following code must be added to the user application:\r
+ * \code\r
+ * pio_set_peripheral(PIOA, PIO_PERIPH_B, PIO_PA17);\r
+ * \endcode\r
+ *\r
+ * \subsection pmc_use_case_2_setup_code_workflow Workflow\r
+ * -# Configure the PCK1 pin to output on a specific port pin (in this case,\r
+ * PIOA pin 17) of the microcontroller.\r
+ * \code\r
+ * pio_set_peripheral(PIOA, PIO_PERIPH_B, PIO_PA17);\r
+ * \endcode\r
+ * \note The peripheral selection and pin will vary according to your selected\r
+ * SAM device model. Refer to the "Peripheral Signal Multiplexing on I/O\r
+ * Lines" of your device's datasheet.\r
+ *\r
+ * \section pmc_use_case_2_usage Use case\r
+ * The generated PCK1 clock output can be viewed on an oscilloscope attached to\r
+ * the correct pin of the microcontroller.\r
+ *\r
+ * \subsection pmc_use_case_2_usage_code Example code\r
+ * Add to application C-file:\r
+ * \code\r
+ * pmc_switch_sclk_to_32kxtal(PMC_OSC_XTAL);\r
+ * pmc_switch_pck_to_sclk(PMC_PCK_1, PMC_PCK_PRES_CLK_64);\r
+ * pmc_enable_pck(PMC_PCK_1);\r
+ *\r
+ * for (;;)\r
+ * {\r
+ * // Do Nothing\r
+ * }\r
+ * \endcode\r
+ *\r
+ * \subsection pmc_use_case_2_usage_flow Workflow\r
+ * -# Switch the Slow Clock source input to an external 32KHz crystal:\r
+ * \code\r
+ * pmc_switch_sclk_to_32kxtal(PMC_OSC_XTAL);\r
+ * \endcode\r
+ * -# Switch the Programmable Clock module PCK1 source clock to the Slow Clock,\r
+ * with a prescaler of 64:\r
+ * \code\r
+ * pmc_switch_pck_to_sclk(PMC_PCK_1, PMC_PCK_PRES_CLK_64);\r
+ * \endcode\r
+ * -# Enable Programmable Clock module PCK1:\r
+ * \code\r
+ * pmc_enable_pck(PMC_PCK_1);\r
+ * \endcode\r
+ * -# Enter an infinite loop:\r
+ * \code\r
+ * for (;;)\r
+ * {\r
+ * // Do Nothing\r
+ * }\r
+ * \endcode\r
+ */\r
+\r
+#endif /* PMC_H_INCLUDED */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Sleep mode access\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef SLEEP_H\r
+#define SLEEP_H\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+#include <compiler.h>\r
+\r
+/**\r
+ * \defgroup sleep_group Power Manager (PM)\r
+ *\r
+ * This is a stub on the SAM Power Manager Control (PMC) for the sleepmgr service.\r
+ *\r
+ * \note To minimize the code overhead, these functions do not feature\r
+ * interrupt-protected access since they are likely to be called inside\r
+ * interrupt handlers or in applications where such protection is not\r
+ * necessary. If such protection is needed, it must be ensured by the calling\r
+ * code.\r
+ *\r
+ * @{\r
+ */\r
+\r
+#if defined(__DOXYGEN__)\r
+/**\r
+ * \brief Sets the MCU in the specified sleep mode\r
+ * \param sleep_mode Sleep mode to set.\r
+ */\r
+#endif\r
+\r
+#if (SAM3S || SAM3N || SAM3XA || SAM3U || SAM4S) // SAM3 and SAM4 series\r
+# include "pmc.h"\r
+\r
+# define SAM_PM_SMODE_ACTIVE 0\r
+# define SAM_PM_SMODE_SLEEP_WFE 1\r
+# define SAM_PM_SMODE_SLEEP_WFI 2\r
+# define SAM_PM_SMODE_WAIT 3\r
+# define SAM_PM_SMODE_BACKUP 4\r
+\r
+/* (SCR) Sleep deep bit */\r
+#define SCR_SLEEPDEEP (0x1 << 2)\r
+\r
+/**\r
+ * Save clock settings and shutdown PLLs\r
+ */\r
+static inline void pmc_save_clock_settings(\r
+ uint32_t *p_osc_setting,\r
+ uint32_t *p_pll0_setting,\r
+ uint32_t *p_pll1_setting,\r
+ uint32_t *p_mck_setting)\r
+{\r
+ if (p_osc_setting) {\r
+ *p_osc_setting = PMC->CKGR_MOR;\r
+ }\r
+ if (p_pll0_setting) {\r
+ *p_pll0_setting = PMC->CKGR_PLLAR;\r
+ }\r
+ if (p_pll1_setting) {\r
+#if SAM3S||SAM4S\r
+ *p_pll1_setting = PMC->CKGR_PLLBR;\r
+#elif SAM3U||SAM3XA\r
+ *p_pll1_setting = PMC->CKGR_UCKR;\r
+#else\r
+ *p_pll1_setting = 0;\r
+#endif\r
+ }\r
+ if (p_mck_setting) {\r
+ *p_mck_setting = PMC->PMC_MCKR;\r
+ }\r
+\r
+ // Switch MCK to Main clock (internal or external 12MHz) for fast wakeup\r
+ // If MAIN_CLK is already the source, just skip\r
+ if ((PMC->PMC_MCKR & PMC_MCKR_CSS_Msk) == PMC_MCKR_CSS_MAIN_CLK) {\r
+ return;\r
+ }\r
+ // If we have to enable the MAIN_CLK\r
+ if ((PMC->PMC_SR & PMC_SR_MOSCXTS) == 0) {\r
+ // Intend to use internal RC as source of MAIN_CLK\r
+ pmc_osc_enable_fastrc(CKGR_MOR_MOSCRCF_12_MHz);\r
+ pmc_switch_mainck_to_fastrc(CKGR_MOR_MOSCRCF_12_MHz);\r
+ }\r
+ pmc_switch_mck_to_mainck(PMC_MCKR_PRES_CLK_1);\r
+}\r
+\r
+/**\r
+ * Restore clock settings\r
+ */\r
+static inline void pmc_restore_clock_setting(\r
+ uint32_t osc_setting,\r
+ uint32_t pll0_setting,\r
+ uint32_t pll1_setting,\r
+ uint32_t mck_setting)\r
+{\r
+ uint32_t mckr;\r
+ if ((pll0_setting & CKGR_PLLAR_MULA_Msk) &&\r
+ pll0_setting != PMC->CKGR_PLLAR) {\r
+ PMC->CKGR_PLLAR = 0;\r
+ PMC->CKGR_PLLAR = CKGR_PLLAR_ONE | pll0_setting;\r
+ while (!(PMC->PMC_SR & PMC_SR_LOCKA));\r
+ }\r
+#if SAM3S||SAM4S\r
+ if ((pll1_setting & CKGR_PLLBR_MULB_Msk) &&\r
+ pll1_setting != PMC->CKGR_PLLBR) {\r
+ PMC->CKGR_PLLBR = 0;\r
+ PMC->CKGR_PLLBR = pll1_setting ;\r
+ while (!(PMC->PMC_SR & PMC_SR_LOCKB));\r
+ }\r
+#elif SAM3U||SAM3XA\r
+ if ((pll1_setting & CKGR_UCKR_UPLLEN) &&\r
+ pll1_setting != PMC->CKGR_UCKR) {\r
+ PMC->CKGR_UCKR = 0;\r
+ PMC->CKGR_UCKR = pll1_setting;\r
+ while (!(PMC->PMC_SR & PMC_SR_LOCKU));\r
+ }\r
+#endif\r
+ /* Switch to faster clock */\r
+ mckr = PMC->PMC_MCKR;\r
+ // Set PRES\r
+ PMC->PMC_MCKR = (mckr & ~PMC_MCKR_PRES_Msk)\r
+ | (mck_setting & PMC_MCKR_PRES_Msk);\r
+ while (!(PMC->PMC_SR & PMC_SR_MCKRDY));\r
+ // Set CSS and others\r
+ PMC->PMC_MCKR = mck_setting;\r
+ while (!(PMC->PMC_SR & PMC_SR_MCKRDY));\r
+ /* Shutdown fastrc */\r
+ if (0 == (osc_setting & CKGR_MOR_MOSCRCEN)) {\r
+ pmc_osc_disable_fastrc();\r
+ }\r
+}\r
+\r
+static inline void pmc_sleep(int sleep_mode)\r
+{\r
+ switch (sleep_mode) {\r
+ case SAM_PM_SMODE_SLEEP_WFI:\r
+ case SAM_PM_SMODE_SLEEP_WFE:\r
+ PMC->PMC_FSMR &= (uint32_t)~PMC_FSMR_LPM;\r
+ SCB->SCR &= (uint32_t)~SCR_SLEEPDEEP;\r
+ cpu_irq_enable();\r
+ if (sleep_mode == SAM_PM_SMODE_SLEEP_WFI)\r
+ __WFI();\r
+ else\r
+ __WFE();\r
+ break;\r
+\r
+ case SAM_PM_SMODE_WAIT: {\r
+ uint32_t mor, pllr0, pllr1, mckr;\r
+ pmc_save_clock_settings(&mor, &pllr0, &pllr1, &mckr);\r
+\r
+ PMC->PMC_FSMR |= PMC_FSMR_LPM;\r
+ SCB->SCR &= (uint32_t)~SCR_SLEEPDEEP ;\r
+ cpu_irq_enable();\r
+ __WFE();\r
+\r
+ cpu_irq_disable();\r
+ pmc_restore_clock_setting(mor, pllr0, pllr1, mckr);\r
+ cpu_irq_enable();\r
+ break;\r
+ }\r
+\r
+ case SAM_PM_SMODE_BACKUP:\r
+ SCB->SCR |= SCR_SLEEPDEEP ;\r
+ cpu_irq_enable();\r
+ __WFE() ;\r
+ break;\r
+ }\r
+}\r
+\r
+#endif\r
+\r
+//! @}\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* SLEEP_H */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Universal Synchronous Asynchronous Receiver Transmitter (USART) driver for SAM.\r
+ *\r
+ * Copyright (c) 2011-2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+ \r
+#include "usart.h"\r
+\r
+/// @cond 0\r
+/**INDENT-OFF**/\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+/**INDENT-ON**/\r
+/// @endcond\r
+\r
+/**\r
+ * \defgroup sam_drivers_usart_group Universal Synchronous Asynchronous Receiver Transmitter (USART)\r
+ *\r
+ * The Universal Synchronous Asynchronous Receiver Transceiver (USART) provides one full duplex \r
+ * universal synchronous asynchronous serial link. Data frame format is widely programmable\r
+ * (data length, parity, number of stop bits) to support a maximum of standards. The receiver\r
+ * implements parity error, framing error and overrun error detection. The receiver time-out enables\r
+ * handling variable-length frames and the transmitter timeguard facilitates communications with\r
+ * slow remote devices. Multidrop communications are also supported through address bit handling\r
+ * in reception and transmission.\r
+ * The driver supports the following modes: RS232, RS485, SPI, IrDA, ISO7816, MODEM,\r
+ * Hardware handshaking and LIN.\r
+ *\r
+ * @{\r
+ */\r
+\r
+/* The write protect key value. */\r
+#define US_WPKEY_VALUE 0x555341\r
+\r
+/* The CD value scope programmed in MR register. */\r
+#define MIN_CD_VALUE 0x01\r
+#define MIN_CD_VALUE_SPI 0x04\r
+#define MAX_CD_VALUE US_BRGR_CD_Msk\r
+\r
+/* Define the default time-out value for USART. */\r
+#define USART_DEFAULT_TIMEOUT 1000\r
+\r
+/* The receiver sampling divide of baudrate clock. */\r
+#define HIGH_FRQ_SAMPLE_DIV 16\r
+#define LOW_FRQ_SAMPLE_DIV 8\r
+\r
+/* Max transmitter timeguard. */\r
+#define MAX_TRAN_GUARD_TIME US_TTGR_TG_Msk\r
+\r
+/* The non-existent parity error number. */\r
+#define USART_PARITY_ERROR 5\r
+\r
+/* ISO7816 protocol type. */\r
+#define ISO7816_T_0 0\r
+#define ISO7816_T_1 1\r
+\r
+/**\r
+ * \brief Calculate a clock divider(CD) and a fractional part (FP) for the \r
+ * USART asynchronous modes to generate a baudrate as close as possible to \r
+ * the baudrate set point.\r
+ *\r
+ * \note Baud rate calculation: Baudrate = ul_mck/(Over * (CD + FP/8))\r
+ * (Over being 16 or 8). The maximal oversampling is selected if it allows to \r
+ * generate a baudrate close to the set point.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ * \param baudrate Baud rate set point.\r
+ * \param ul_mck USART module input clock frequency.\r
+ *\r
+ * \retval 0 Baud rate is successfully initialized.\r
+ * \retval 1 Baud rate set point is out of range for the given input clock \r
+ * frequency.\r
+ */\r
+static uint32_t usart_set_async_baudrate(Usart *p_usart,\r
+ uint32_t baudrate, uint32_t ul_mck)\r
+{\r
+ uint32_t over;\r
+ uint32_t cd_fp;\r
+ uint32_t cd;\r
+ uint32_t fp;\r
+\r
+ /* Calculate the receiver sampling divide of baudrate clock. */\r
+ if (ul_mck >= HIGH_FRQ_SAMPLE_DIV * baudrate) {\r
+ over = HIGH_FRQ_SAMPLE_DIV;\r
+ } else {\r
+ over = LOW_FRQ_SAMPLE_DIV;\r
+ }\r
+\r
+ /* Calculate the clock divider according to the fraction calculated formula. */\r
+ cd_fp = (8 * ul_mck + (over * baudrate) / 2) / (over * baudrate);\r
+ cd = cd_fp >> 3;\r
+ fp = cd_fp & 0x07;\r
+ if (cd < MIN_CD_VALUE || cd > MAX_CD_VALUE) {\r
+ return 1;\r
+ }\r
+\r
+ /* Configure the OVER bit in MR register. */\r
+ if (over == 8) {\r
+ p_usart->US_MR |= US_MR_OVER;\r
+ }\r
+\r
+ /* Configure the baudrate generate register. */\r
+ p_usart->US_BRGR = (cd << US_BRGR_CD_Pos) | (fp << US_BRGR_FP_Pos);\r
+\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * \brief Calculate a clock divider for the USART synchronous master modes\r
+ * to generate a baudrate as close as possible to the baudrate set point.\r
+ *\r
+ * \note Synchronous baudrate calculation: baudrate = ul_mck / cd\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ * \param baudrate Baud rate set point.\r
+ * \param ul_mck USART module input clock frequency.\r
+ *\r
+ * \retval 0 Baud rate is successfully initialized.\r
+ * \retval 1 Baud rate set point is out of range for the given input clock \r
+ * frequency.\r
+ */\r
+static uint32_t usart_set_sync_master_baudrate(Usart *p_usart,\r
+ uint32_t baudrate, uint32_t ul_mck)\r
+{\r
+ uint32_t cd;\r
+\r
+ /* Calculate the clock divider according to the formula in synchronous mode. */\r
+ cd = (ul_mck + baudrate / 2) / baudrate;\r
+\r
+ if (cd < MIN_CD_VALUE || cd > MAX_CD_VALUE) {\r
+ return 1;\r
+ }\r
+\r
+ /* Configure the baudrate generate register. */\r
+ p_usart->US_BRGR = cd << US_BRGR_CD_Pos;\r
+\r
+ p_usart->US_MR = (p_usart->US_MR & ~US_MR_USCLKS_Msk) |\r
+ US_MR_USCLKS_MCK | US_MR_SYNC;\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * \brief Select the SCK pin as the source of baud rate for the USART\r
+ * synchronous slave modes.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ */\r
+static void usart_set_sync_slave_baudrate(Usart *p_usart)\r
+{\r
+ p_usart->US_MR = (p_usart->US_MR & ~US_MR_USCLKS_Msk) |\r
+ US_MR_USCLKS_SCK | US_MR_SYNC;\r
+}\r
+\r
+\r
+/**\r
+ * \brief Calculate a clock divider (\e CD) for the USART ISO7816 mode to \r
+ * generate an ISO7816 clock as close as possible to the clock set point.\r
+ *\r
+ * \note ISO7816 clock calculation: Clock = ul_mck / cd\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ * \param clock ISO7816 clock set point.\r
+ * \param ul_mck USART module input clock frequency.\r
+ *\r
+ * \retval 0 ISO7816 clock is successfully initialized.\r
+ * \retval 1 ISO7816 clock set point is out of range for the given input clock \r
+ * frequency.\r
+ */\r
+static uint32_t usart_set_iso7816_clock(Usart *p_usart,\r
+ uint32_t clock, uint32_t ul_mck)\r
+{\r
+ uint32_t cd;\r
+\r
+ /* Calculate the clock divider according to the formula in ISO7816 mode. */\r
+ cd = (ul_mck + clock / 2) / clock;\r
+\r
+ if (cd < MIN_CD_VALUE || cd > MAX_CD_VALUE) {\r
+ return 1;\r
+ }\r
+\r
+ p_usart->US_MR = (p_usart->US_MR & ~(US_MR_USCLKS_Msk | US_MR_SYNC |\r
+ US_MR_OVER)) | US_MR_USCLKS_MCK | US_MR_CLKO;\r
+\r
+ /* Configure the baudrate generate register. */\r
+ p_usart->US_BRGR = cd << US_BRGR_CD_Pos;\r
+\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * \brief Calculate a clock divider (\e CD) for the USART SPI master mode to\r
+ * generate a baud rate as close as possible to the baud rate set point.\r
+ *\r
+ * \note Baud rate calculation:\r
+ * \f$ Baudrate = \frac{SelectedClock}{CD} \f$.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ * \param baudrate Baud rate set point.\r
+ * \param ul_mck USART module input clock frequency.\r
+ *\r
+ * \retval 0 Baud rate is successfully initialized.\r
+ * \retval 1 Baud rate set point is out of range for the given input clock \r
+ * frequency.\r
+ */\r
+static uint32_t usart_set_spi_master_baudrate(Usart *p_usart,\r
+ uint32_t baudrate, uint32_t ul_mck)\r
+{\r
+ uint32_t cd;\r
+\r
+ /* Calculate the clock divider according to the formula in SPI mode. */\r
+ cd = (ul_mck + baudrate / 2) / baudrate;\r
+\r
+ if (cd < MIN_CD_VALUE_SPI || cd > MAX_CD_VALUE) {\r
+ return 1;\r
+ }\r
+\r
+ p_usart->US_BRGR = cd << US_BRGR_CD_Pos;\r
+\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * \brief Select the SCK pin as the source of baudrate for the USART SPI slave \r
+ * mode.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ */\r
+static void usart_set_spi_slave_baudrate(Usart *p_usart)\r
+{\r
+ p_usart->US_MR &= ~US_MR_USCLKS_Msk;\r
+ p_usart->US_MR |= US_MR_USCLKS_SCK;\r
+}\r
+\r
+/**\r
+ * \brief Reset the USART and disable TX and RX.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ */\r
+void usart_reset(Usart *p_usart)\r
+{\r
+ /* Disable the Write Protect. Some register can't be written if the write protect is enabled. */\r
+ usart_disable_writeprotect(p_usart);\r
+\r
+ /* Reset mode and other registers that could cause unpredictable behavior after reset. */\r
+ p_usart->US_MR = 0;\r
+ p_usart->US_RTOR = 0;\r
+ p_usart->US_TTGR = 0;\r
+\r
+ /* Disable TX and RX, reset status bits and turn off RTS and DTR if exist. */\r
+ usart_reset_tx(p_usart);\r
+ usart_reset_rx(p_usart);\r
+ usart_reset_status(p_usart);\r
+ usart_drive_RTS_pin_high(p_usart);\r
+#if (SAM3S || SAM4S || SAM3U)\r
+ usart_drive_DTR_pin_high(p_usart);\r
+#endif\r
+}\r
+\r
+/**\r
+ * \brief Configure USART to work in RS232 mode.\r
+ *\r
+ * \note By default, the transmitter and receiver aren't enabled.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ * \param p_usart_opt Pointer to sam_usart_opt_t instance.\r
+ * \param ul_mck USART module input clock frequency.\r
+ *\r
+ * \retval 0 on success.\r
+ * \retval 1 on failure.\r
+ */\r
+uint32_t usart_init_rs232(Usart *p_usart,\r
+ const sam_usart_opt_t *p_usart_opt, uint32_t ul_mck)\r
+{\r
+ static uint32_t ul_reg_val;\r
+\r
+ /* Reset the USART and shut down TX and RX. */\r
+ usart_reset(p_usart);\r
+\r
+ ul_reg_val = 0;\r
+ /* Check whether the input values are legal. */\r
+ if (!p_usart_opt ||\r
+ usart_set_async_baudrate(p_usart, p_usart_opt->baudrate, ul_mck)) {\r
+ return 1;\r
+ }\r
+\r
+ /* Configure the character length, parity type, channel mode and stop bit length. */\r
+ ul_reg_val |= p_usart_opt->char_length | p_usart_opt->parity_type |\r
+ p_usart_opt->channel_mode | p_usart_opt->stop_bits;\r
+ \r
+ /* Configure the USART mode as normal mode. */\r
+ ul_reg_val |= US_MR_USART_MODE_NORMAL;\r
+ \r
+ p_usart->US_MR |= ul_reg_val;\r
+ \r
+ return 0;\r
+}\r
+\r
+/**\r
+ * \brief Configure USART to work in hardware handshaking mode.\r
+ *\r
+ * \note By default, the transmitter and receiver aren't enabled.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ * \param p_usart_opt Pointer to sam_usart_opt_t instance.\r
+ * \param ul_mck USART module input clock frequency.\r
+ *\r
+ * \retval 0 on success.\r
+ * \retval 1 on failure.\r
+ */\r
+uint32_t usart_init_hw_handshaking(Usart *p_usart,\r
+ const sam_usart_opt_t *p_usart_opt, uint32_t ul_mck)\r
+{\r
+ /* Initialize the USART as standard RS232. */\r
+ if (usart_init_rs232(p_usart, p_usart_opt, ul_mck)) {\r
+ return 1;\r
+ }\r
+\r
+ /* Set hardware handshaking mode. */\r
+ p_usart->US_MR = (p_usart->US_MR & ~US_MR_USART_MODE_Msk) |\r
+ US_MR_USART_MODE_HW_HANDSHAKING;\r
+\r
+ return 0;\r
+}\r
+\r
+#if (SAM3S || SAM4S || SAM3U)\r
+/**\r
+ * \brief Configure USART to work in modem mode.\r
+ *\r
+ * \note By default, the transmitter and receiver aren't enabled.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ * \param p_usart_opt Pointer to sam_usart_opt_t instance.\r
+ * \param ul_mck USART module input clock frequency.\r
+ *\r
+ * \retval 0 on success.\r
+ * \retval 1 on failure.\r
+ */\r
+uint32_t usart_init_modem(Usart *p_usart,\r
+ const sam_usart_opt_t *p_usart_opt, uint32_t ul_mck)\r
+{\r
+ /* SAM3S || SAM4S series support MODEM mode only on USART1, and \r
+ SAM3U series support MODEM mode only on USART0. */\r
+#if (SAM3S || SAM4S)\r
+ if (p_usart != USART1) {\r
+ return 1;\r
+ }\r
+#elif (SAM3U)\r
+ if (p_usart != USART0) {\r
+ return 1;\r
+ }\r
+#endif\r
+\r
+ /* Initialize the USART as standard RS232. */\r
+ if (usart_init_rs232(p_usart, p_usart_opt, ul_mck)) {\r
+ return 1;\r
+ }\r
+ \r
+ /* Set MODEM mode. */\r
+ p_usart->US_MR = (p_usart->US_MR & ~US_MR_USART_MODE_Msk) |\r
+ US_MR_USART_MODE_MODEM;\r
+\r
+ return 0;\r
+}\r
+#endif\r
+\r
+/**\r
+ * \brief Configure USART to work in SYNC mode and act as a master.\r
+ *\r
+ * \note By default, the transmitter and receiver aren't enabled.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ * \param p_usart_opt Pointer to sam_usart_opt_t instance.\r
+ * \param ul_mck USART module input clock frequency.\r
+ *\r
+ * \retval 0 on success.\r
+ * \retval 1 on failure.\r
+ */\r
+uint32_t usart_init_sync_master(Usart *p_usart,\r
+ const sam_usart_opt_t *p_usart_opt, uint32_t ul_mck)\r
+{\r
+ static uint32_t ul_reg_val;\r
+\r
+ /* Reset the USART and shut down TX and RX. */\r
+ usart_reset(p_usart);\r
+\r
+ ul_reg_val = 0;\r
+ /* Check whether the input values are legal. */\r
+ if (!p_usart_opt ||\r
+ usart_set_sync_master_baudrate(p_usart, p_usart_opt->baudrate, ul_mck)) {\r
+ return 1;\r
+ }\r
+\r
+ /* Configure the character length, parity type, channel mode and stop bit length. */\r
+ ul_reg_val |= p_usart_opt->char_length | p_usart_opt->parity_type |\r
+ p_usart_opt->channel_mode | p_usart_opt->stop_bits;\r
+ \r
+ /* Set normal mode and output clock on the SCK pin as synchronous master. */\r
+ ul_reg_val |= US_MR_USART_MODE_NORMAL | US_MR_CLKO;\r
+ p_usart->US_MR |= ul_reg_val;\r
+\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * \brief Configure USART to work in SYNC mode and act as a slave.\r
+ *\r
+ * \note By default, the transmitter and receiver aren't enabled.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ * \param p_usart_opt Pointer to sam_usart_opt_t instance.\r
+ *\r
+ * \retval 0 on success.\r
+ * \retval 1 on failure.\r
+ */\r
+uint32_t usart_init_sync_slave(Usart *p_usart,\r
+ const sam_usart_opt_t *p_usart_opt)\r
+{\r
+ static uint32_t ul_reg_val;\r
+ \r
+ /* Reset the USART and shut down TX and RX. */\r
+ usart_reset(p_usart);\r
+ \r
+ ul_reg_val = 0;\r
+ usart_set_sync_slave_baudrate(p_usart);\r
+ \r
+ /* Check whether the input values are legal. */\r
+ if (!p_usart_opt) {\r
+ return 1;\r
+ }\r
+\r
+ /* Configure the character length, parity type, channel mode and stop bit length. */\r
+ ul_reg_val |= p_usart_opt->char_length | p_usart_opt->parity_type |\r
+ p_usart_opt->channel_mode | p_usart_opt->stop_bits;\r
+\r
+ /* Set normal mode. */\r
+ ul_reg_val |= US_MR_USART_MODE_NORMAL;\r
+ p_usart->US_MR |= ul_reg_val; \r
+\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * \brief Configure USART to work in RS485 mode.\r
+ *\r
+ * \note By default, the transmitter and receiver aren't enabled.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ * \param p_usart_opt Pointer to sam_usart_opt_t instance.\r
+ * \param ul_mck USART module input clock frequency.\r
+ *\r
+ * \retval 0 on success.\r
+ * \retval 1 on failure.\r
+ */\r
+uint32_t usart_init_rs485(Usart *p_usart,\r
+ const sam_usart_opt_t *p_usart_opt, uint32_t ul_mck)\r
+{\r
+ /* Initialize the USART as standard RS232. */\r
+ if (usart_init_rs232(p_usart, p_usart_opt, ul_mck)) {\r
+ return 1;\r
+ }\r
+\r
+ /* Set RS485 mode. */\r
+ p_usart->US_MR = (p_usart->US_MR & ~US_MR_USART_MODE_Msk) |\r
+ US_MR_USART_MODE_RS485;\r
+\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * \brief Configure USART to work in IrDA mode.\r
+ *\r
+ * \note By default, the transmitter and receiver aren't enabled.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ * \param p_usart_opt Pointer to sam_usart_opt_t instance.\r
+ * \param ul_mck USART module input clock frequency.\r
+ *\r
+ * \retval 0 on success.\r
+ * \retval 1 on failure.\r
+ */\r
+uint32_t usart_init_irda(Usart *p_usart,\r
+ const sam_usart_opt_t *p_usart_opt, uint32_t ul_mck)\r
+{\r
+ /* Initialize the USART as standard RS232. */\r
+ if (usart_init_rs232(p_usart, p_usart_opt, ul_mck)) {\r
+ return 1;\r
+ }\r
+\r
+ /* Set IrDA filter. */\r
+ p_usart->US_IF = p_usart_opt->irda_filter;\r
+\r
+ /* Set IrDA mode. */\r
+ p_usart->US_MR = (p_usart->US_MR & ~US_MR_USART_MODE_Msk) |\r
+ US_MR_USART_MODE_IRDA;\r
+\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * \brief Configure USART to work in ISO7816 mode.\r
+ *\r
+ * \note By default, the transmitter and receiver aren't enabled.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ * \param p_usart_opt Pointer to sam_usart_opt_t instance.\r
+ * \param ul_mck USART module input clock frequency.\r
+ *\r
+ * \retval 0 on success.\r
+ * \retval 1 on failure.\r
+ */\r
+uint32_t usart_init_iso7816(Usart *p_usart,\r
+ const usart_iso7816_opt_t *p_usart_opt, uint32_t ul_mck)\r
+{\r
+ static uint32_t ul_reg_val;\r
+ \r
+ /* Reset the USART and shut down TX and RX. */\r
+ usart_reset(p_usart);\r
+ \r
+ ul_reg_val = 0;\r
+ \r
+ /* Check whether the input values are legal. */\r
+ if (!p_usart_opt || ((p_usart_opt->parity_type != US_MR_PAR_EVEN) &&\r
+ (p_usart_opt->parity_type != US_MR_PAR_ODD))) {\r
+ return 1;\r
+ }\r
+ \r
+ if (p_usart_opt->protocol_type == ISO7816_T_0) {\r
+ ul_reg_val |= US_MR_USART_MODE_IS07816_T_0 | US_MR_NBSTOP_2_BIT |\r
+ (p_usart_opt->max_iterations << US_MR_MAX_ITERATION_Pos);\r
+\r
+ if (p_usart_opt->bit_order) {\r
+ ul_reg_val |= US_MR_MSBF;\r
+ }\r
+ } else if (p_usart_opt->protocol_type == ISO7816_T_1) {\r
+ /* Only LSBF is used in the T=1 protocol, and max_iterations field is only used in T=0 mode.*/\r
+ if (p_usart_opt->bit_order || p_usart_opt->max_iterations) {\r
+ return 1;\r
+ }\r
+ \r
+ /* Set USART mode to ISO7816, T=1, and always uses 1 stop bit. */\r
+ ul_reg_val |= US_MR_USART_MODE_IS07816_T_1 | US_MR_NBSTOP_1_BIT;\r
+ } else {\r
+ return 1;\r
+ }\r
+\r
+ /* Set up the baudrate. */\r
+ if (usart_set_iso7816_clock(p_usart, p_usart_opt->iso7816_hz, ul_mck)) {\r
+ return 1;\r
+ }\r
+\r
+ /* Set FIDI register: bit rate = iso7816_hz / fidi_ratio. */\r
+ p_usart->US_FIDI = p_usart_opt->fidi_ratio;\r
+\r
+ /* Set ISO7816 parity type in the MODE register. */\r
+ ul_reg_val |= p_usart_opt->parity_type;\r
+ \r
+ if (p_usart_opt->inhibit_nack) {\r
+ ul_reg_val |= US_MR_INACK;\r
+ }\r
+ if (p_usart_opt->dis_suc_nack) {\r
+ ul_reg_val |= US_MR_DSNACK;\r
+ }\r
+ \r
+ p_usart->US_MR |= ul_reg_val;\r
+\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * \brief Configure USART to work in SPI mode and act as a master.\r
+ *\r
+ * \note By default, the transmitter and receiver aren't enabled.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ * \param p_usart_opt Pointer to sam_usart_opt_t instance.\r
+ * \param ul_mck USART module input clock frequency.\r
+ *\r
+ * \retval 0 on success.\r
+ * \retval 1 on failure.\r
+ */\r
+uint32_t usart_init_spi_master(Usart *p_usart,\r
+ const usart_spi_opt_t *p_usart_opt, uint32_t ul_mck)\r
+{\r
+ static uint32_t ul_reg_val;\r
+ \r
+ /* Reset the USART and shut down TX and RX. */\r
+ usart_reset(p_usart);\r
+ \r
+ ul_reg_val = 0;\r
+ /* Check whether the input values are legal. */\r
+ if (!p_usart_opt ||\r
+ (p_usart_opt->spi_mode > SPI_MODE_3) ||\r
+ usart_set_spi_master_baudrate(p_usart, p_usart_opt->baudrate, ul_mck)) {\r
+ return 1;\r
+ }\r
+\r
+ /* Configure the character length bit in MR register. */\r
+ ul_reg_val |= p_usart_opt->char_length;\r
+ \r
+ /* Set SPI master mode and channel mode. */\r
+ ul_reg_val |= US_MR_USART_MODE_SPI_MASTER | US_MR_CLKO |\r
+ p_usart_opt->channel_mode;\r
+ \r
+ switch (p_usart_opt->spi_mode) {\r
+ case SPI_MODE_0:\r
+ ul_reg_val |= US_MR_CPHA;\r
+ ul_reg_val &= ~US_MR_CPOL;\r
+ break;\r
+ case SPI_MODE_1:\r
+ ul_reg_val &= ~US_MR_CPHA;\r
+ ul_reg_val &= ~US_MR_CPOL;\r
+ break;\r
+ case SPI_MODE_2:\r
+ ul_reg_val |= US_MR_CPHA;\r
+ ul_reg_val |= US_MR_CPOL;\r
+ break;\r
+ case SPI_MODE_3:\r
+ ul_reg_val |= US_MR_CPOL;\r
+ ul_reg_val &= ~US_MR_CPHA;\r
+ break;\r
+ default:\r
+ break;\r
+ }\r
+ \r
+ p_usart->US_MR |= ul_reg_val;\r
+\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * \brief Configure USART to work in SPI mode and act as a slave.\r
+ *\r
+ * \note By default, the transmitter and receiver aren't enabled.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ * \param p_usart_opt Pointer to sam_usart_opt_t instance.\r
+ *\r
+ * \retval 0 on success.\r
+ * \retval 1 on failure.\r
+ */\r
+uint32_t usart_init_spi_slave(Usart *p_usart,\r
+ const usart_spi_opt_t *p_usart_opt)\r
+{\r
+ static uint32_t ul_reg_val;\r
+\r
+ /* Reset the USART and shut down TX and RX. */\r
+ usart_reset(p_usart);\r
+ \r
+ ul_reg_val = 0;\r
+ usart_set_spi_slave_baudrate(p_usart);\r
+ \r
+ /* Check whether the input values are legal. */\r
+ if (!p_usart_opt ||\r
+ p_usart_opt->spi_mode > SPI_MODE_3) {\r
+ return 1;\r
+ }\r
+\r
+ /* Configure the character length bit in MR register. */\r
+ ul_reg_val |= p_usart_opt->char_length;\r
+ \r
+ /* Set SPI slave mode and channel mode. */\r
+ ul_reg_val |= US_MR_USART_MODE_SPI_SLAVE | p_usart_opt->channel_mode;\r
+ \r
+ switch (p_usart_opt->spi_mode) {\r
+ case SPI_MODE_0:\r
+ ul_reg_val |= US_MR_CPHA;\r
+ ul_reg_val &= ~US_MR_CPOL;\r
+ break;\r
+ case SPI_MODE_1:\r
+ ul_reg_val &= ~US_MR_CPHA;\r
+ ul_reg_val &= ~US_MR_CPOL;\r
+ break;\r
+ case SPI_MODE_2:\r
+ ul_reg_val |= US_MR_CPHA;\r
+ ul_reg_val |= US_MR_CPOL;\r
+ break;\r
+ case SPI_MODE_3:\r
+ ul_reg_val |= US_MR_CPOL;\r
+ ul_reg_val &= ~US_MR_CPHA;\r
+ break;\r
+ default:\r
+ break;\r
+ }\r
+\r
+ p_usart->US_MR |= ul_reg_val;\r
+\r
+ return 0;\r
+}\r
+\r
+#if SAM3XA\r
+/**\r
+ * \brief Configure USART to work in LIN mode and act as a LIN master.\r
+ *\r
+ * \note By default, the transmitter and receiver aren't enabled.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ * \param p_usart_opt Pointer to sam_usart_opt_t instance.\r
+ * \param ul_mck USART module input clock frequency.\r
+ *\r
+ * \retval 0 on success.\r
+ * \retval 1 on failure.\r
+ */\r
+uint32_t usart_init_lin_master(Usart *p_usart,\r
+ const sam_usart_opt_t *p_usart_opt, uint32_t ul_mck)\r
+{\r
+ /* Reset the USART and shut down TX and RX. */\r
+ usart_reset(p_usart);\r
+\r
+ /* Set up the baudrate. */\r
+ if (usart_set_async_baudrate(p_usart, p_usart_opt->baudrate, ul_mck)) {\r
+ return 1;\r
+ }\r
+ \r
+ /* Set LIN master mode. */\r
+ p_usart->US_MR = (p_usart->US_MR & ~US_MR_USART_MODE_Msk) |\r
+ US_MR_USART_MODE_LIN_MASTER; \r
+\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * \brief Configure USART to work in LIN mode and act as a LIN slave.\r
+ *\r
+ * \note By default, the transmitter and receiver aren't enabled.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ * \param p_usart_opt Pointer to sam_usart_opt_t instance.\r
+ * \param ul_mck USART module input clock frequency.\r
+ *\r
+ * \retval 0 on success.\r
+ * \retval 1 on failure.\r
+ */\r
+uint32_t usart_init_lin_slave(Usart *p_usart,\r
+ const sam_usart_opt_t *p_usart_opt, uint32_t ul_mck)\r
+{\r
+ /* Reset the USART and shut down TX and RX. */\r
+ usart_reset(p_usart);\r
+\r
+ /* Set up the baudrate. */\r
+ if (usart_set_async_baudrate(p_usart, p_usart_opt->baudrate, ul_mck)) {\r
+ return 1;\r
+ }\r
+ \r
+ /* Set LIN slave mode. */\r
+ p_usart->US_MR = (p_usart->US_MR & ~US_MR_USART_MODE_Msk) |\r
+ US_MR_USART_MODE_LIN_SLAVE;\r
+\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * \brief Abort the current LIN transmission.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ */\r
+void usart_lin_abort_tx(Usart *p_usart)\r
+{\r
+ p_usart->US_CR = US_CR_LINABT;\r
+}\r
+\r
+/**\r
+ * \brief Send a wakeup signal on the LIN bus.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ */\r
+void usart_lin_send_wakeup_signal(Usart *p_usart)\r
+{\r
+ p_usart->US_CR = US_CR_LINWKUP;\r
+}\r
+\r
+/**\r
+ * \brief Configure the LIN node action, which should be one of PUBLISH,\r
+ * SUBSCRIBE or IGNORE.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ * \param uc_action 0 for PUBLISH, 1 for SUBSCRIBE, 2 for IGNORE.\r
+ */\r
+void usart_lin_set_node_action(Usart *p_usart, uint8_t uc_action)\r
+{\r
+ p_usart->US_LINMR = (p_usart->US_LINMR & ~US_LINMR_NACT_Msk) |\r
+ (uc_action << US_LINMR_NACT_Pos);\r
+}\r
+\r
+/**\r
+ * \brief Disable the parity check during the LIN communication.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ */\r
+void usart_lin_disable_parity(Usart *p_usart)\r
+{\r
+ p_usart->US_LINMR |= US_LINMR_PARDIS;\r
+}\r
+\r
+/**\r
+ * \brief Enable the parity check during the LIN communication.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ */\r
+void usart_lin_enable_parity(Usart *p_usart)\r
+{\r
+ p_usart->US_LINMR &= ~US_LINMR_PARDIS;\r
+}\r
+\r
+/**\r
+ * \brief Disable the checksum during the LIN communication.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ */\r
+void usart_lin_disable_checksum(Usart *p_usart)\r
+{\r
+ p_usart->US_LINMR |= US_LINMR_CHKDIS;\r
+}\r
+\r
+/**\r
+ * \brief Enable the checksum during the LIN communication.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ */\r
+void usart_lin_enable_checksum(Usart *p_usart)\r
+{\r
+ p_usart->US_LINMR &= ~US_LINMR_CHKDIS;\r
+}\r
+\r
+/**\r
+ * \brief Configure the checksum type during the LIN communication.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ * \param uc_type 0 for LIN 2.0 Enhanced checksum or 1 for LIN 1.3 Classic checksum.\r
+ */\r
+void usart_lin_set_checksum_type(Usart *p_usart, uint8_t uc_type)\r
+{\r
+ p_usart->US_LINMR = (p_usart->US_LINMR & ~US_LINMR_CHKTYP) |\r
+ (uc_type << 4);\r
+}\r
+\r
+/**\r
+ * \brief Configure the data length mode during the LIN communication.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ * \param uc_mode Indicate the checksum type: 0 if the data length is defined by the \r
+ * DLC of LIN mode register or 1 if the data length is defined by the bit 5 and 6 of \r
+ * the identifier.\r
+ */\r
+void usart_lin_set_data_len_mode(Usart *p_usart, uint8_t uc_mode)\r
+{\r
+ p_usart->US_LINMR = (p_usart->US_LINMR & ~US_LINMR_DLM) |\r
+ (uc_mode << 5);\r
+}\r
+\r
+/**\r
+ * \brief Disable the frame slot mode during the LIN communication.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ */\r
+void usart_lin_disable_frame_slot(Usart *p_usart)\r
+{\r
+ p_usart->US_LINMR |= US_LINMR_FSDIS;\r
+}\r
+\r
+/**\r
+ * \brief Enable the frame slot mode during the LIN communication.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ */\r
+void usart_lin_enable_frame_slot(Usart *p_usart)\r
+{\r
+ p_usart->US_LINMR &= ~US_LINMR_FSDIS;\r
+}\r
+\r
+/**\r
+ * \brief Configure the wakeup signal type during the LIN communication.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ * \param uc_type Indicate the checksum type: 0 if the wakeup signal is a LIN 2.0 \r
+ * wakeup signal; 1 if the wakeup signal is a LIN 1.3 wakeup signal.\r
+ */\r
+void usart_lin_set_wakeup_signal_type(Usart *p_usart, uint8_t uc_type)\r
+{\r
+ p_usart->US_LINMR = (p_usart->US_LINMR & ~US_LINMR_WKUPTYP) |\r
+ (uc_type << 7);\r
+}\r
+\r
+/**\r
+ * \brief Configure the response data length if the data length is defined by\r
+ * the DLC field during the LIN communication.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ * \param uc_len Indicate the response data length.\r
+ */\r
+void usart_lin_set_response_data_len(Usart *p_usart, uint8_t uc_len)\r
+{\r
+ p_usart->US_LINMR = (p_usart->US_LINMR & ~US_LINMR_DLC_Msk) |\r
+ (uc_len << US_LINMR_DLC_Pos);\r
+}\r
+\r
+/**\r
+ * \brief The LIN mode register is not written by the PDC.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ */\r
+void usart_lin_disable_pdc_mode(Usart *p_usart)\r
+{\r
+ p_usart->US_LINMR &= ~US_LINMR_PDCM;\r
+}\r
+\r
+/**\r
+ * \brief The LIN mode register (except this flag) is written by the PDC.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ */\r
+void usart_lin_enable_pdc_mode(Usart *p_usart)\r
+{\r
+ p_usart->US_LINMR |= US_LINMR_PDCM;\r
+}\r
+\r
+/**\r
+ * \brief Configure the LIN identifier when USART works in LIN master mode.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ * \param uc_id The identifier to be transmitted.\r
+ */\r
+void usart_lin_set_tx_identifier(Usart *p_usart, uint8_t uc_id)\r
+{\r
+ p_usart->US_LINIR = (p_usart->US_LINIR & ~US_LINIR_IDCHR_Msk) |\r
+ US_LINIR_IDCHR(uc_id);\r
+}\r
+\r
+/**\r
+ * \brief Read the identifier when USART works in LIN mode.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ *\r
+ * \return The last identifier received in LIN slave mode or the last identifier \r
+ * transmitted in LIN master mode. \r
+ */\r
+uint8_t usart_lin_read_identifier(Usart *p_usart)\r
+{\r
+ return (p_usart->US_LINMR & US_LINIR_IDCHR_Msk);\r
+}\r
+#endif\r
+\r
+/**\r
+ * \brief Enable USART transmitter.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ */\r
+void usart_enable_tx(Usart *p_usart)\r
+{\r
+ p_usart->US_CR = US_CR_TXEN;\r
+}\r
+\r
+/**\r
+ * \brief Disable USART transmitter.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ */\r
+void usart_disable_tx(Usart *p_usart)\r
+{\r
+ p_usart->US_CR = US_CR_TXDIS;\r
+}\r
+\r
+/**\r
+ * \brief Immediately stop and disable USART transmitter.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ */\r
+void usart_reset_tx(Usart *p_usart)\r
+{\r
+ /* Reset transmitter */\r
+ p_usart->US_CR = US_CR_RSTTX | US_CR_TXDIS;\r
+}\r
+\r
+/**\r
+ * \brief Configure the transmit timeguard register.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ * \param timeguard The value of transmit timeguard.\r
+ */\r
+void usart_set_tx_timeguard(Usart *p_usart, uint32_t timeguard)\r
+{\r
+ p_usart->US_TTGR = timeguard;\r
+}\r
+\r
+/**\r
+ * \brief Enable USART receiver.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ */\r
+void usart_enable_rx(Usart *p_usart)\r
+{\r
+ p_usart->US_CR = US_CR_RXEN;\r
+}\r
+\r
+/**\r
+ * \brief Disable USART receiver.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ */\r
+void usart_disable_rx(Usart *p_usart)\r
+{\r
+ p_usart->US_CR = US_CR_RXDIS;\r
+}\r
+\r
+/**\r
+ * \brief Immediately stop and disable USART receiver.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ */\r
+void usart_reset_rx(Usart *p_usart)\r
+{\r
+ /* Reset Receiver */\r
+ p_usart->US_CR = US_CR_RSTRX | US_CR_RXDIS;\r
+}\r
+\r
+/**\r
+ * \brief Configure the receive timeout register.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ * \param timeout The value of receive timeout.\r
+ */\r
+void usart_set_rx_timeout(Usart *p_usart, uint32_t timeout)\r
+{\r
+ p_usart->US_RTOR = timeout;\r
+}\r
+\r
+/**\r
+ * \brief Enable USART interrupts.\r
+ *\r
+ * \param p_usart Pointer to a USART peripheral.\r
+ * \param ul_sources Interrupt sources bit map.\r
+ */\r
+void usart_enable_interrupt(Usart *p_usart, uint32_t ul_sources)\r
+{\r
+ p_usart->US_IER = ul_sources;\r
+}\r
+\r
+/**\r
+ * \brief Disable USART interrupts.\r
+ *\r
+ * \param p_usart Pointer to a USART peripheral.\r
+ * \param ul_sources Interrupt sources bit map.\r
+ */\r
+void usart_disable_interrupt(Usart *p_usart, uint32_t ul_sources)\r
+{\r
+ p_usart->US_IDR = ul_sources;\r
+}\r
+\r
+/**\r
+ * \brief Read USART interrupt mask.\r
+ *\r
+ * \param p_usart Pointer to a USART peripheral.\r
+ *\r
+ * \return The interrupt mask value.\r
+ */\r
+uint32_t usart_get_interrupt_mask(Usart *p_usart)\r
+{\r
+ return p_usart->US_IMR;\r
+}\r
+\r
+/**\r
+ * \brief Get current status.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ *\r
+ * \return The current USART status.\r
+ */\r
+uint32_t usart_get_status(Usart *p_usart)\r
+{\r
+ return p_usart->US_CSR;\r
+}\r
+\r
+/**\r
+ * \brief Reset status bits (PARE, OVER, MANERR, UNRE and PXBRK in US_CSR).\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ */\r
+void usart_reset_status(Usart *p_usart)\r
+{\r
+ p_usart->US_CR = US_CR_RSTSTA;\r
+}\r
+\r
+/**\r
+ * \brief Start transmission of a break.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ */\r
+void usart_start_tx_break(Usart *p_usart)\r
+{\r
+ p_usart->US_CR = US_CR_STTBRK;\r
+}\r
+\r
+/**\r
+ * \brief Stop transmission of a break.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ */\r
+void usart_stop_tx_break(Usart *p_usart)\r
+{\r
+ p_usart->US_CR = US_CR_STPBRK;\r
+}\r
+\r
+/**\r
+ * \brief Start waiting for a character before clocking the timeout count.\r
+ * Reset the status bit TIMEOUT in US_CSR. \r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ */\r
+void usart_start_rx_timeout(Usart *p_usart)\r
+{\r
+ p_usart->US_CR = US_CR_STTTO;\r
+}\r
+\r
+/**\r
+ * \brief In Multidrop mode only, the next character written to the US_THR\r
+ * is sent with the address bit set. \r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ * \param ul_addr The address to be sent out.\r
+ *\r
+ * \retval 0 on success.\r
+ * \retval 1 on failure.\r
+ */\r
+uint32_t usart_send_address(Usart *p_usart, uint32_t ul_addr)\r
+{\r
+ if ((p_usart->US_MR & US_MR_PAR_MULTIDROP) != US_MR_PAR_MULTIDROP) {\r
+ return 1;\r
+ }\r
+ \r
+ p_usart->US_CR = US_CR_SENDA;\r
+ \r
+ if (usart_write(p_usart, ul_addr)) {\r
+ return 1;\r
+ } else {\r
+ return 0;\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Reset the ITERATION in US_CSR when the ISO7816 mode is enabled.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ */\r
+void usart_reset_iterations(Usart *p_usart)\r
+{\r
+ p_usart->US_CR = US_CR_RSTIT;\r
+}\r
+\r
+/**\r
+ * \brief Reset NACK in US_CSR.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ */\r
+void usart_reset_nack(Usart *p_usart)\r
+{\r
+ p_usart->US_CR = US_CR_RSTNACK;\r
+}\r
+\r
+/**\r
+ * \brief Restart the receive timeout.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ */\r
+void usart_restart_rx_timeout(Usart *p_usart)\r
+{\r
+ p_usart->US_CR = US_CR_RETTO;\r
+}\r
+\r
+#if (SAM3S || SAM4S || SAM3U)\r
+/**\r
+ * \brief Drive the pin DTR to 0.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ */\r
+void usart_drive_DTR_pin_low(Usart *p_usart)\r
+{\r
+ p_usart->US_CR = US_CR_DTREN;\r
+}\r
+\r
+/**\r
+ * \brief Drive the pin DTR to 1.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ */\r
+void usart_drive_DTR_pin_high(Usart *p_usart)\r
+{\r
+ p_usart->US_CR = US_CR_DTRDIS;\r
+}\r
+#endif\r
+\r
+/**\r
+ * \brief Drive the pin RTS to 0.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ */\r
+void usart_drive_RTS_pin_low(Usart *p_usart)\r
+{\r
+ p_usart->US_CR = US_CR_RTSEN;\r
+}\r
+\r
+/**\r
+ * \brief Drive the pin RTS to 1.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ */\r
+void usart_drive_RTS_pin_high(Usart *p_usart)\r
+{\r
+ p_usart->US_CR = US_CR_RTSDIS;\r
+}\r
+\r
+/**\r
+ * \brief Drive the slave select line NSS (RTS pin) to 0 in SPI master mode.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ */\r
+void usart_spi_force_chip_select(Usart *p_usart)\r
+{\r
+ p_usart->US_CR = US_CR_FCS;\r
+}\r
+\r
+/**\r
+ * \brief Drive the slave select line NSS (RTS pin) to 1 in SPI master mode.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ */\r
+void usart_spi_release_chip_select(Usart *p_usart)\r
+{\r
+ p_usart->US_CR = US_CR_RCS;\r
+}\r
+\r
+/**\r
+ * \brief Check if Transmit is Ready.\r
+ * Check if data have been loaded in USART_THR and are waiting to be loaded \r
+ * into the Transmit Shift Register (TSR).\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ *\r
+ * \retval 1 No data is in the Transmit Holding Register.\r
+ * \retval 0 There is data in the Transmit Holding Register.\r
+ */\r
+uint32_t usart_is_tx_ready(Usart *p_usart)\r
+{\r
+ return (p_usart->US_CSR & US_CSR_TXRDY) > 0;\r
+}\r
+\r
+/**\r
+ * \brief Check if Transmit Holding Register is empty.\r
+ * Check if the last data written in USART_THR have been loaded in TSR and the last\r
+ * data loaded in TSR have been transmitted.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ *\r
+ * \retval 1 Transmitter is empty.\r
+ * \retval 0 Transmitter is not empty.\r
+ */\r
+uint32_t usart_is_tx_empty(Usart *p_usart)\r
+{\r
+ return (p_usart->US_CSR & US_CSR_TXEMPTY) > 0;\r
+}\r
+\r
+/**\r
+ * \brief Check if the received data are ready.\r
+ * Check if Data have been received and loaded into USART_RHR.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ *\r
+ * \retval 1 Some data has been received.\r
+ * \retval 0 No data has been received.\r
+ */\r
+uint32_t usart_is_rx_ready(Usart *p_usart)\r
+{\r
+ return (p_usart->US_CSR & US_CSR_RXRDY) > 0;\r
+}\r
+\r
+/**\r
+ * \brief Check if one receive buffer is filled.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ *\r
+ * \retval 1 Receive is complete.\r
+ * \retval 0 Receive is still pending.\r
+ */\r
+uint32_t usart_is_rx_buf_end(Usart *p_usart)\r
+{\r
+ return (p_usart->US_CSR & US_CSR_ENDRX) > 0;\r
+}\r
+\r
+/**\r
+ * \brief Check if one transmit buffer is empty.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ *\r
+ * \retval 1 Transmit is complete.\r
+ * \retval 0 Transmit is still pending.\r
+ */\r
+uint32_t usart_is_tx_buf_end(Usart *p_usart)\r
+{\r
+ return (p_usart->US_CSR & US_CSR_ENDTX) > 0;\r
+}\r
+\r
+/**\r
+ * \brief Check if both receive buffers are full.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ *\r
+ * \retval 1 Receive buffers are full.\r
+ * \retval 0 Receive buffers are not full.\r
+ */\r
+uint32_t usart_is_rx_buf_full(Usart *p_usart)\r
+{\r
+ return (p_usart->US_CSR & US_CSR_RXBUFF) > 0;\r
+}\r
+\r
+/**\r
+ * \brief Check if both transmit buffers are empty.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ *\r
+ * \retval 1 Transmit buffers are empty.\r
+ * \retval 0 Transmit buffers are not empty.\r
+ */\r
+uint32_t usart_is_tx_buf_empty(Usart *p_usart)\r
+{\r
+ return (p_usart->US_CSR & US_CSR_TXBUFE) > 0;\r
+}\r
+\r
+/**\r
+ * \brief Write to USART Transmit Holding Register.\r
+ *\r
+ * \note Before writing user should check if tx is ready (or empty).\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ * \param c Data to be sent.\r
+ *\r
+ * \retval 0 on success.\r
+ * \retval 1 on failure.\r
+ */\r
+uint32_t usart_write(Usart *p_usart, uint32_t c)\r
+{\r
+ if (!(p_usart->US_CSR & US_CSR_TXRDY)) {\r
+ return 1;\r
+ }\r
+\r
+ p_usart->US_THR = US_THR_TXCHR(c);\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * \brief Write to USART Transmit Holding Register.\r
+ *\r
+ * \note Before writing user should check if tx is ready (or empty).\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ * \param c Data to be sent.\r
+ *\r
+ * \retval 0 on success.\r
+ * \retval 1 on failure.\r
+ */\r
+uint32_t usart_putchar(Usart *p_usart, uint32_t c)\r
+{\r
+ uint32_t timeout = USART_DEFAULT_TIMEOUT;\r
+\r
+ while (!(p_usart->US_CSR & US_CSR_TXRDY)) {\r
+ if (!timeout--) {\r
+ return 1;\r
+ }\r
+ }\r
+\r
+ p_usart->US_THR = US_THR_TXCHR(c);\r
+\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * \brief Write one-line string through USART.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ * \param string Pointer to one-line string to be sent.\r
+ */\r
+void usart_write_line(Usart *p_usart, const char *string)\r
+{\r
+ while (*string != '\0') {\r
+ usart_putchar(p_usart, *string++);\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Read from USART Receive Holding Register.\r
+ *\r
+ * \note Before reading user should check if rx is ready.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ * \param c Pointer where the one-byte received data will be stored.\r
+ *\r
+ * \retval 0 on success.\r
+ * \retval 1 if no data is available or errors.\r
+ */\r
+uint32_t usart_read(Usart *p_usart, uint32_t *c)\r
+{\r
+ if (!(p_usart->US_CSR & US_CSR_RXRDY)) {\r
+ return 1;\r
+ }\r
+ \r
+ /* Read character */\r
+ *c = p_usart->US_RHR & US_RHR_RXCHR_Msk;\r
+ \r
+ return 0;\r
+}\r
+\r
+/**\r
+ * \brief Read from USART Receive Holding Register.\r
+ * Before reading user should check if rx is ready.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ * \param c Pointer where the one-byte received data will be stored.\r
+ *\r
+ * \retval 0 Data has been received.\r
+ * \retval 1 on failure.\r
+ */\r
+uint32_t usart_getchar(Usart *p_usart, uint32_t *c)\r
+{\r
+ uint32_t timeout = USART_DEFAULT_TIMEOUT;\r
+\r
+ /* If the receiver is empty, wait until it's not empty or timeout has reached. */\r
+ while (!(p_usart->US_CSR & US_CSR_RXRDY)) {\r
+ if (!timeout--) {\r
+ return 1;\r
+ }\r
+ }\r
+\r
+ /* Read character */\r
+ *c = p_usart->US_RHR & US_RHR_RXCHR_Msk;\r
+\r
+ return 0;\r
+}\r
+\r
+#if (SAM3XA || SAM3U)\r
+/**\r
+ * \brief Get Transmit address for DMA operation.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ *\r
+ * \return Transmit address for DMA access.\r
+ */\r
+uint32_t *usart_get_tx_access(Usart *p_usart)\r
+{\r
+ return (uint32_t *)&(p_usart->US_THR);\r
+}\r
+\r
+/**\r
+ * \brief Get Receive address for DMA operation.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ *\r
+ * \return Receive address for DMA access.\r
+ */\r
+uint32_t *usart_get_rx_access(Usart *p_usart)\r
+{\r
+ return (uint32_t *)&(p_usart->US_RHR);\r
+}\r
+#endif\r
+\r
+/**\r
+ * \brief Get USART PDC base address.\r
+ *\r
+ * \param p_usart Pointer to a UART instance.\r
+ *\r
+ * \return USART PDC registers base for PDC driver to access.\r
+ */\r
+Pdc *usart_get_pdc_base(Usart *p_usart)\r
+{\r
+ Pdc *p_pdc_base;\r
+\r
+ p_pdc_base = (Pdc *) NULL;\r
+\r
+ if (p_usart == USART0) {\r
+ p_pdc_base = PDC_USART0;\r
+ return p_pdc_base;\r
+ }\r
+#if (SAM3S || SAM4S || SAM3XA || SAM3U)\r
+ else if (p_usart == USART1) {\r
+ p_pdc_base = PDC_USART1;\r
+ return p_pdc_base;\r
+ }\r
+#endif\r
+#if (SAM3SD8 || SAM3XA || SAM3U)\r
+ else if (p_usart == USART2) {\r
+ p_pdc_base = PDC_USART2;\r
+ return p_pdc_base;\r
+ }\r
+#endif\r
+#if (SAM3XA || SAM3U)\r
+ else if (p_usart == USART3) {\r
+ p_pdc_base = PDC_USART3;\r
+ return p_pdc_base;\r
+ }\r
+#endif\r
+\r
+ return p_pdc_base;\r
+}\r
+\r
+/**\r
+ * \brief Enable write protect of USART registers.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ */\r
+void usart_enable_writeprotect(Usart *p_usart)\r
+{\r
+ p_usart->US_WPMR = US_WPMR_WPEN | US_WPMR_WPKEY(US_WPKEY_VALUE);\r
+}\r
+\r
+/**\r
+ * \brief Disable write protect of USART registers.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ */\r
+void usart_disable_writeprotect(Usart *p_usart)\r
+{\r
+ p_usart->US_WPMR = US_WPMR_WPKEY(US_WPKEY_VALUE);\r
+}\r
+\r
+/**\r
+ * \brief Get write protect status.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ *\r
+ * \return 0 if the peripheral is not protected. \r
+ * \return 16-bit Write Protect Violation Status otherwise.\r
+ */\r
+uint32_t usart_get_writeprotect_status(Usart *p_usart)\r
+{\r
+ uint32_t reg_value;\r
+\r
+ reg_value = p_usart->US_WPSR;\r
+ if (reg_value & US_WPSR_WPVS) {\r
+ return (reg_value & US_WPSR_WPVSRC_Msk) >> US_WPSR_WPVSRC_Pos;\r
+ } else {\r
+ return 0;\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Get the total number of errors that occur during an ISO7816 transfer.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ *\r
+ * \return The number of errors that occured.\r
+ */\r
+uint8_t usart_get_error_number(Usart *p_usart)\r
+{\r
+ return (p_usart->US_NER & US_NER_NB_ERRORS_Msk);\r
+}\r
+\r
+#if (SAM3S || SAM4S || SAM3U || SAM3XA)\r
+/**\r
+ * \brief Configure the transmitter preamble length when the Manchester \r
+ * encode/decode is enabled.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ * \param uc_len The transmitter preamble length, which should be 0 ~ 15.\r
+ */\r
+void usart_man_set_tx_pre_len(Usart *p_usart, uint8_t uc_len)\r
+{\r
+ p_usart->US_MAN = (p_usart->US_MAN & ~US_MAN_TX_PL_Msk) |\r
+ US_MAN_TX_PL(uc_len);\r
+}\r
+\r
+/**\r
+ * \brief Configure the transmitter preamble pattern when the Manchester \r
+ * encode/decode is enabled, which should be 0 ~ 3.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ * \param uc_pattern 0 if the preamble is composed of '1's;\r
+ * 1 if the preamble is composed of '0's;\r
+ * 2 if the preamble is composed of '01's;\r
+ * 3 if the preamble is composed of '10's.\r
+ */\r
+void usart_man_set_tx_pre_pattern(Usart *p_usart, uint8_t uc_pattern)\r
+{\r
+ p_usart->US_MAN = (p_usart->US_MAN & ~US_MAN_TX_PP_Msk) |\r
+ (uc_pattern << US_MAN_TX_PP_Pos);\r
+}\r
+\r
+/**\r
+ * \brief Configure the transmitter Manchester polarity when the Manchester \r
+ * encode/decode is enabled.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ * \param uc_polarity Indicate the transmitter Manchester polarity, which \r
+ * should be 0 or 1.\r
+ */\r
+void usart_man_set_tx_polarity(Usart *p_usart, uint8_t uc_polarity)\r
+{\r
+ p_usart->US_MAN = (p_usart->US_MAN & ~US_MAN_TX_MPOL) |\r
+ (uc_polarity << 12);\r
+}\r
+\r
+/**\r
+ * \brief Configure the detected receiver preamble length when the Manchester \r
+ * encode/decode is enabled.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ * \param uc_len The detected receiver preamble length, which should be 0 ~ 15.\r
+ */\r
+void usart_man_set_rx_pre_len(Usart *p_usart, uint8_t uc_len)\r
+{\r
+ p_usart->US_MAN = (p_usart->US_MAN & ~US_MAN_RX_PL_Msk) |\r
+ US_MAN_RX_PL(uc_len);\r
+}\r
+\r
+/**\r
+ * \brief Configure the detected receiver preamble pattern when the Manchester \r
+ * encode/decode is enabled, which should be 0 ~ 3.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ * \param uc_pattern 0 if the preamble is composed of '1's;\r
+ * 1 if the preamble is composed of '0's;\r
+ * 2 if the preamble is composed of '01's;\r
+ * 3 if the preamble is composed of '10's.\r
+ */\r
+void usart_man_set_rx_pre_pattern(Usart *p_usart, uint8_t uc_pattern)\r
+{\r
+ p_usart->US_MAN = (p_usart->US_MAN & ~US_MAN_RX_PP_Msk) |\r
+ (uc_pattern << US_MAN_RX_PP_Pos);\r
+}\r
+\r
+/**\r
+ * \brief Configure the receiver Manchester polarity when the Manchester \r
+ * encode/decode is enabled.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ * \param uc_polarity Indicate the receiver Manchester polarity, which should \r
+ * be 0 or 1.\r
+ */\r
+void usart_man_set_rx_polarity(Usart *p_usart, uint8_t uc_polarity)\r
+{\r
+ p_usart->US_MAN = (p_usart->US_MAN & ~US_MAN_RX_MPOL) |\r
+ (uc_polarity << 28);\r
+}\r
+\r
+/**\r
+ * \brief Enable drift compensation.\r
+ *\r
+ * \note The 16X clock mode must be enabled.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ */\r
+void usart_man_enable_drift_compensation(Usart *p_usart)\r
+{\r
+ p_usart->US_MAN |= US_MAN_DRIFT;\r
+}\r
+\r
+/**\r
+ * \brief Disable drift compensation.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ */\r
+void usart_man_disable_drift_compensation(Usart *p_usart)\r
+{\r
+ p_usart->US_MAN &= ~US_MAN_DRIFT;\r
+}\r
+#endif\r
+\r
+//@}\r
+\r
+/// @cond 0\r
+/**INDENT-OFF**/\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+/**INDENT-ON**/\r
+/// @endcond\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Universal Synchronous Asynchronous Receiver Transmitter (USART) driver for SAM.\r
+ *\r
+ * Copyright (c) 2011-2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef USART_H_INCLUDED\r
+#define USART_H_INCLUDED\r
+\r
+#include "compiler.h"\r
+\r
+/**\r
+ * \defgroup usart_group Universal Synchronous Asynchronous Receiver Transmitter (USART)\r
+ *\r
+ * See \ref sam_usart_quickstart.\r
+ *\r
+ * This is a low-level driver implementation for the SAM Universal\r
+ * Synchronous/Asynchronous Receiver/Transmitter.\r
+ *\r
+ * @{\r
+ */\r
+\r
+/// @cond 0\r
+/**INDENT-OFF**/\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+/**INDENT-ON**/\r
+/// @endcond\r
+\r
+/** Clock phase. */\r
+#define SPI_CPHA (1 << 0)\r
+\r
+/** Clock polarity. */\r
+#define SPI_CPOL (1 << 1)\r
+\r
+/** SPI mode definition. */\r
+#define SPI_MODE_0 (SPI_CPHA)\r
+#define SPI_MODE_1 0\r
+#define SPI_MODE_2 (SPI_CPOL | SPI_CPHA)\r
+#define SPI_MODE_3 (SPI_CPOL)\r
+\r
+//! Input parameters when initializing RS232 and similar modes.\r
+typedef struct {\r
+ //! Set baud rate of the USART (unused in slave modes).\r
+ uint32_t baudrate;\r
+ \r
+ //! Number of bits, which should be one of the following: US_MR_CHRL_5_BIT,\r
+ //! US_MR_CHRL_6_BIT, US_MR_CHRL_7_BIT, US_MR_CHRL_8_BIT or US_MR_MODE9.\r
+ uint32_t char_length;\r
+ \r
+ //! Parity type, which should be one of the following: US_MR_PAR_EVEN, US_MR_PAR_ODD,\r
+ //! US_MR_PAR_SPACE, US_MR_PAR_MARK, US_MR_PAR_NO or US_MR_PAR_MULTIDROP.\r
+ uint32_t parity_type;\r
+\r
+ //! Number of stop bits between two characters: US_MR_NBSTOP_1_BIT,\r
+ //! US_MR_NBSTOP_1_5_BIT, US_MR_NBSTOP_2_BIT.\r
+ //! \note US_MR_NBSTOP_1_5_BIT is supported in asynchronous modes only.\r
+ uint32_t stop_bits;\r
+\r
+ //! Run the channel in test mode, which should be one of following: US_MR_CHMODE_NORMAL,\r
+ //! US_MR_CHMODE_AUTOMATIC, US_MR_CHMODE_LOCAL_LOOPBACK, US_MR_CHMODE_REMOTE_LOOPBACK\r
+ uint32_t channel_mode;\r
+\r
+ //! Filter of IrDA mode, useless in other modes. \r
+ uint32_t irda_filter;\r
+} sam_usart_opt_t;\r
+\r
+//! Input parameters when initializing ISO7816 mode.\r
+typedef struct {\r
+ //! Set the frequency of the ISO7816 clock.\r
+ uint32_t iso7816_hz;\r
+ \r
+ //! The number of ISO7816 clock ticks in every bit period (1 to 2047, 0 = disable clock).\r
+ //! Baudrate rate = iso7816_hz / fidi_ratio\r
+ uint32_t fidi_ratio;\r
+\r
+ //! How to calculate the parity bit: US_MR_PAR_EVEN for normal mode or\r
+ //! US_MR_PAR_ODD for inverse mode.\r
+ uint32_t parity_type;\r
+\r
+ //! Inhibit Non Acknowledge:\r
+ //! - 0: the NACK is generated;\r
+ //! - 1: the NACK is not generated.\r
+ //!\r
+ //! \note This bit will be used only in ISO7816 mode, protocol T = 0 receiver.\r
+ uint32_t inhibit_nack;\r
+\r
+ //! Disable successive NACKs.\r
+ //! - 0: NACK is sent on the ISO line as soon as a parity error occurs in the received character.\r
+ //! Successive parity errors are counted up to the value in the max_iterations field.\r
+ //! These parity errors generate a NACK on the ISO line. As soon as this value is reached,\r
+ //! No additional NACK is sent on the ISO line. The ITERATION flag is asserted.\r
+ uint32_t dis_suc_nack;\r
+\r
+ //! Max number of repetitions (0 to 7).\r
+ uint32_t max_iterations;\r
+\r
+ //! Bit order in transmitted characters:\r
+ //! - 0: LSB first;\r
+ //! - 1: MSB first.\r
+ uint32_t bit_order;\r
+ \r
+ //! Which protocol is used:\r
+ //! - 0: T = 0;\r
+ //! - 1: T = 1.\r
+ uint32_t protocol_type;\r
+} usart_iso7816_opt_t;\r
+\r
+//! Input parameters when initializing SPI mode.\r
+typedef struct {\r
+ //! Set the frequency of the SPI clock (unused in slave mode).\r
+ uint32_t baudrate;\r
+\r
+ //! Number of bits, which should be one of the following: US_MR_CHRL_5_BIT,\r
+ //! US_MR_CHRL_6_BIT, US_MR_CHRL_7_BIT, US_MR_CHRL_8_BIT or US_MR_MODE9.\r
+ uint32_t char_length;\r
+\r
+ //! Which SPI mode to use, which should be one of the following:\r
+ //! SPI_MODE_0, SPI_MODE_1, SPI_MODE_2, SPI_MODE_3.\r
+ uint32_t spi_mode;\r
+\r
+ //! Run the channel in test mode, which should be one of following: US_MR_CHMODE_NORMAL,\r
+ //! US_MR_CHMODE_AUTOMATIC, US_MR_CHMODE_LOCAL_LOOPBACK, US_MR_CHMODE_REMOTE_LOOPBACK\r
+ uint32_t channel_mode;\r
+} usart_spi_opt_t;\r
+\r
+void usart_reset(Usart *p_usart);\r
+uint32_t usart_init_rs232(Usart *p_usart, const sam_usart_opt_t *p_usart_opt, uint32_t ul_mck);\r
+uint32_t usart_init_hw_handshaking(Usart *p_usart, const sam_usart_opt_t *p_usart_opt, uint32_t ul_mck);\r
+#if (SAM3S || SAM4S || SAM3U)\r
+uint32_t usart_init_modem(Usart *p_usart, const sam_usart_opt_t *p_usart_opt, uint32_t ul_mck);\r
+#endif\r
+uint32_t usart_init_sync_master(Usart *p_usart, const sam_usart_opt_t *p_usart_opt, uint32_t ul_mck);\r
+uint32_t usart_init_sync_slave(Usart *p_usart, const sam_usart_opt_t *p_usart_opt);\r
+uint32_t usart_init_rs485(Usart *p_usart, const sam_usart_opt_t *p_usart_opt, uint32_t ul_mck);\r
+uint32_t usart_init_irda(Usart *p_usart, const sam_usart_opt_t *p_usart_opt, uint32_t ul_mck);\r
+uint32_t usart_init_iso7816(Usart *p_usart, const usart_iso7816_opt_t *p_usart_opt, uint32_t ul_mck);\r
+uint32_t usart_init_spi_master(Usart *p_usart, const usart_spi_opt_t *p_usart_opt, uint32_t ul_mck);\r
+uint32_t usart_init_spi_slave(Usart *p_usart, const usart_spi_opt_t *p_usart_opt);\r
+#if SAM3XA\r
+uint32_t usart_init_lin_master(Usart *p_usart, const sam_usart_opt_t *p_usart_opt, uint32_t ul_mck);\r
+uint32_t usart_init_lin_slave(Usart *p_usart, const sam_usart_opt_t *p_usart_opt, uint32_t ul_mck);\r
+void usart_lin_abort_tx(Usart *p_usart);\r
+void usart_lin_send_wakeup_signal(Usart *p_usart);\r
+void usart_lin_set_node_action(Usart *p_usart, uint8_t uc_action);\r
+void usart_lin_disable_parity(Usart *p_usart);\r
+void usart_lin_enable_parity(Usart *p_usart);\r
+void usart_lin_disable_checksum(Usart *p_usart);\r
+void usart_lin_enable_checksum(Usart *p_usart);\r
+void usart_lin_set_checksum_type(Usart *p_usart, uint8_t uc_type);\r
+void usart_lin_set_data_len_mode(Usart *p_usart, uint8_t uc_mode);\r
+void usart_lin_disable_frame_slot(Usart *p_usart);\r
+void usart_lin_enable_frame_slot(Usart *p_usart);\r
+void usart_lin_set_wakeup_signal_type(Usart *p_usart, uint8_t uc_type);\r
+void usart_lin_set_response_data_len(Usart *p_usart, uint8_t uc_len);\r
+void usart_lin_disable_pdc_mode(Usart *p_usart);\r
+void usart_lin_enable_pdc_mode(Usart *p_usart);\r
+void usart_lin_set_tx_identifier(Usart *p_usart, uint8_t uc_id);\r
+uint8_t usart_lin_read_identifier(Usart *p_usart);\r
+#endif\r
+void usart_enable_tx(Usart *p_usart);\r
+void usart_disable_tx(Usart *p_usart);\r
+void usart_reset_tx(Usart *p_usart);\r
+void usart_set_tx_timeguard(Usart *p_usart, uint32_t timeguard);\r
+void usart_enable_rx(Usart *p_usart);\r
+void usart_disable_rx(Usart *p_usart);\r
+void usart_reset_rx(Usart *p_usart);\r
+void usart_set_rx_timeout(Usart *p_usart, uint32_t timeout);\r
+void usart_enable_interrupt(Usart *p_usart,uint32_t ul_sources);\r
+void usart_disable_interrupt(Usart *p_usart,uint32_t ul_sources);\r
+uint32_t usart_get_interrupt_mask(Usart *p_usart);\r
+uint32_t usart_get_status(Usart *p_usart);\r
+void usart_reset_status(Usart *p_usart);\r
+void usart_start_tx_break(Usart *p_usart);\r
+void usart_stop_tx_break(Usart *p_usart);\r
+void usart_start_rx_timeout(Usart *p_usart);\r
+uint32_t usart_send_address(Usart *p_usart, uint32_t ul_addr);\r
+void usart_reset_iterations(Usart *p_usart);\r
+void usart_reset_nack(Usart *p_usart);\r
+void usart_restart_rx_timeout(Usart *p_usart);\r
+#if (SAM3S || SAM4S || SAM3U)\r
+void usart_drive_DTR_pin_low(Usart *p_usart);\r
+void usart_drive_DTR_pin_high(Usart *p_usart);\r
+#endif\r
+void usart_drive_RTS_pin_low(Usart *p_usart);\r
+void usart_drive_RTS_pin_high(Usart *p_usart);\r
+void usart_spi_force_chip_select(Usart *p_usart);\r
+void usart_spi_release_chip_select(Usart *p_usart);\r
+uint32_t usart_is_tx_ready(Usart *p_usart);\r
+uint32_t usart_is_tx_empty(Usart *p_usart);\r
+uint32_t usart_is_rx_ready(Usart *p_usart);\r
+uint32_t usart_is_rx_buf_end(Usart *p_usart);\r
+uint32_t usart_is_tx_buf_end(Usart *p_usart);\r
+uint32_t usart_is_rx_buf_full(Usart *p_usart);\r
+uint32_t usart_is_tx_buf_empty(Usart *p_usart);\r
+uint32_t usart_write(Usart *p_usart, uint32_t c);\r
+uint32_t usart_putchar(Usart *p_usart, uint32_t c);\r
+void usart_write_line(Usart *p_usart, const char *string);\r
+uint32_t usart_read(Usart *p_usart, uint32_t *c);\r
+uint32_t usart_getchar(Usart *p_usart, uint32_t *c);\r
+#if (SAM3XA || SAM3U)\r
+uint32_t * usart_get_tx_access(Usart *p_usart);\r
+uint32_t * usart_get_rx_access(Usart *p_usart);\r
+#endif\r
+Pdc *usart_get_pdc_base(Usart *p_usart);\r
+void usart_enable_writeprotect(Usart *p_usart);\r
+void usart_disable_writeprotect(Usart *p_usart);\r
+uint32_t usart_get_writeprotect_status(Usart *p_usart);\r
+uint8_t usart_get_error_number(Usart *p_usart);\r
+#if (SAM3S || SAM4S || SAM3U || SAM3XA)\r
+void usart_man_set_tx_pre_len(Usart *p_usart, uint8_t uc_len);\r
+void usart_man_set_tx_pre_pattern(Usart *p_usart, uint8_t uc_pattern);\r
+void usart_man_set_tx_polarity(Usart *p_usart, uint8_t uc_polarity);\r
+void usart_man_set_rx_pre_len(Usart *p_usart, uint8_t uc_len);\r
+void usart_man_set_rx_pre_pattern(Usart *p_usart, uint8_t uc_pattern);\r
+void usart_man_set_rx_polarity(Usart *p_usart, uint8_t uc_polarity);\r
+void usart_man_enable_drift_compensation(Usart *p_usart);\r
+void usart_man_disable_drift_compensation(Usart *p_usart);\r
+#endif\r
+\r
+/// @cond 0\r
+/**INDENT-OFF**/\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+/**INDENT-ON**/\r
+/// @endcond\r
+\r
+//! @}\r
+\r
+/**\r
+ * \page sam_usart_quickstart Quick start guide for the SAM USART module\r
+ *\r
+ * This is the quick start guide for the \ref usart_group "USART module", with\r
+ * step-by-step instructions on how to configure and use the driver in a\r
+ * selection of use cases.\r
+ *\r
+ * The use cases contain several code fragments. The code fragments in the\r
+ * steps for setup can be copied into a custom initialization function, while\r
+ * the steps for usage can be copied into, e.g., the main application function.\r
+ *\r
+ * \note Some SAM devices contain both USART and UART modules, with the latter\r
+ * being a subset in functionality of the former but physically seperate\r
+ * peripherals. UART modules are compatible with the USART driver, but\r
+ * only for the functions and modes suported by the base UART driver.\r
+ *\r
+ * \section usart_basic_use_case Basic use case\r
+ * \section usart_use_cases USART use cases\r
+ * - \ref usart_basic_use_case\r
+ * - \subpage usart_use_case_1\r
+ * - \subpage usart_use_case_2\r
+ *\r
+ * \section usart_basic_use_case Basic use case - transmit a character\r
+ * In this use case, the USART module is configured for:\r
+ * - Using USART0\r
+ * - Baudrate: 9600\r
+ * - Character length: 8 bit\r
+ * - Parity mode: Disabled\r
+ * - Stop bit: None\r
+ * - RS232 mode\r
+ *\r
+ * \section usart_basic_use_case_setup Setup steps\r
+ *\r
+ * \subsection usart_basic_use_case_setup_prereq Prerequisites\r
+ * -# \ref sysclk_group "System Clock Management (sysclock)"\r
+ * -# \ref pio_group "Parallel Input/Output Controller (pio)"\r
+ * -# \ref pmc_group "Power Management Controller (pmc)"\r
+ *\r
+ * \subsection usart_basic_use_case_setup_code Example code\r
+ * The following configuration must be added to the project (typically to a \r
+ * conf_usart.h file, but it can also be added to your main application file.)\r
+ * \code\r
+ * #define USART_SERIAL USART0\r
+ * #define USART_SERIAL_ID ID_USART0\r
+ * #define USART_SERIAL_PIO PINS_USART_PIO\r
+ * #define USART_SERIAL_TYPE PINS_USART_TYPE\r
+ * #define USART_SERIAL_PINS PINS_USART_PINS\r
+ * #define USART_SERIAL_MASK PINS_USART_MASK\r
+ * #define USART_SERIAL_BAUDRATE 9600\r
+ * #define USART_SERIAL_CHAR_LENGTH US_MR_CHRL_8_BIT\r
+ * #define USART_SERIAL_PARITY US_MR_PAR_NO\r
+ * #define USART_SERIAL_STOP_BIT US_MR_NBSTOP_1_BIT\r
+ * \endcode\r
+ *\r
+ * Add to application initialization:\r
+ * \code\r
+ * sysclk_init();\r
+ *\r
+ * pio_configure(USART_SERIAL_PIO, USART_SERIAL_TYPE,\r
+ * USART_SERIAL_MASK, USART_SERIAL_ATTR);\r
+ * \r
+ * const sam_usart_opt_t usart_console_settings = {\r
+ * USART_SERIAL_BAUDRATE,\r
+ * USART_SERIAL_CHAR_LENGTH,\r
+ * USART_SERIAL_PARITY,\r
+ * USART_SERIAL_STOP_BIT,\r
+ * US_MR_CHMODE_NORMAL\r
+ * };\r
+ * \r
+ * pmc_enable_periph_clk(USART_SERIAL_ID);\r
+ * \r
+ * usart_init_rs232(USART_SERIAL, &usart_console_settings, sysclk_get_main_hz());\r
+ * usart_enable_tx(USART_SERIAL);\r
+ * usart_enable_rx(USART_SERIAL);\r
+ * \endcode\r
+ *\r
+ * \subsection usart_basic_use_case_setup_flow Workflow\r
+ * -# Initialize system clock:\r
+ * \code\r
+ * sysclk_init();\r
+ * \endcode\r
+ * -# Configure the USART Tx and Rx pins as Outputs and Inputs respectively:\r
+ * \code\r
+ * pio_configure(PINS_UART_PIO, PINS_UART_TYPE, PINS_UART_MASK,\r
+ * PINS_UART_ATTR);\r
+ * \endcode\r
+ * -# Create USART options struct:\r
+ * \code\r
+ * const sam_usart_opt_t usart_console_settings = {\r
+ * USART_SERIAL_BAUDRATE,\r
+ * USART_SERIAL_CHAR_LENGTH,\r
+ * USART_SERIAL_PARITY,\r
+ * USART_SERIAL_STOP_BIT,\r
+ * US_MR_CHMODE_NORMAL\r
+ * };\r
+ * \endcode\r
+ * -# Enable the clock to the USART module:\r
+ * \code\r
+ * pmc_enable_periph_clk(USART_SERIAL_ID);\r
+ * \endcode\r
+ * -# Initialize the USART module in RS232 mode:\r
+ * \code\r
+ * usart_init_rs232(USART_SERIAL, &usart_console_settings, sysclk_get_main_hz());\r
+ * \endcode\r
+ * -# Enable the Rx and Tx modes of the USART module:\r
+ * \code\r
+ * usart_enable_tx(USART_SERIAL);\r
+ * usart_enable_rx(USART_SERIAL);\r
+ * \endcode\r
+ *\r
+ * \section usart_basic_use_case_usage Usage steps\r
+ *\r
+ * \subsection usart_basic_use_case_usage_code Example code\r
+ * Add to application C-file:\r
+ * \code\r
+ * usart_putchar(USART_SERIAL, 'a');\r
+ * \endcode\r
+ *\r
+ * \subsection usart_basic_use_case_usage_flow Workflow\r
+ * -# Send an 'a' character via USART\r
+ * \code usart_putchar(USART_SERIAL, 'a'); \endcode\r
+ */\r
+\r
+/**\r
+ * \page usart_use_case_1 USART receive character and echo back\r
+ *\r
+ * In this use case, the USART module is configured for:\r
+ * - Using USART0\r
+ * - Baudrate: 9600\r
+ * - Character length: 8 bit\r
+ * - Parity mode: Disabled\r
+ * - Stop bit: None\r
+ * - RS232 mode\r
+ *\r
+ * The use case waits for a received character on the configured USART and\r
+ * echoes the character back to the same USART.\r
+ *\r
+ * \section usart_use_case_1_setup Setup steps\r
+ *\r
+ * \subsection usart_use_case_1_setup_prereq Prerequisites\r
+ * -# \ref sysclk_group "System Clock Management (sysclock)"\r
+ * -# \ref pio_group "Parallel Input/Output Controller (pio)"\r
+ * -# \ref pmc_group "Power Management Controller (pmc)"\r
+ *\r
+ * \subsection usart_use_case_1_setup_code Example code\r
+ * The following configuration must be added to the project (typically to a \r
+ * conf_usart.h file, but it can also be added to your main application file.):\r
+ * \code\r
+ * #define USART_SERIAL USART0\r
+ * #define USART_SERIAL_ID ID_USART0\r
+ * #define USART_SERIAL_PIO PINS_USART_PIO\r
+ * #define USART_SERIAL_TYPE PINS_USART_TYPE\r
+ * #define USART_SERIAL_PINS PINS_USART_PINS\r
+ * #define USART_SERIAL_MASK PINS_USART_MASK\r
+ * #define USART_SERIAL_BAUDRATE 9600\r
+ * #define USART_SERIAL_CHAR_LENGTH US_MR_CHRL_8_BIT\r
+ * #define USART_SERIAL_PARITY US_MR_PAR_NO\r
+ * #define USART_SERIAL_STOP_BIT US_MR_NBSTOP_1_BIT\r
+ * \endcode\r
+ *\r
+ * A variable for the received byte must be added:\r
+ * \code\r
+ * uint32_t received_byte;\r
+ * \endcode\r
+ *\r
+ * Add to application initialization:\r
+ * \code\r
+ * sysclk_init();\r
+ *\r
+ * pio_configure(USART_SERIAL_PIO, USART_SERIAL_TYPE,\r
+ * USART_SERIAL_MASK, USART_SERIAL_ATTR);\r
+ * \r
+ * const sam_usart_opt_t usart_console_settings = {\r
+ * USART_SERIAL_BAUDRATE,\r
+ * USART_SERIAL_CHAR_LENGTH,\r
+ * USART_SERIAL_PARITY,\r
+ * USART_SERIAL_STOP_BIT,\r
+ * US_MR_CHMODE_NORMAL\r
+ * };\r
+ * \r
+ * pmc_enable_periph_clk(USART_SERIAL_ID);\r
+ * \r
+ * usart_init_rs232(USART_SERIAL, &usart_console_settings, sysclk_get_main_hz());\r
+ * usart_enable_tx(USART_SERIAL);\r
+ * usart_enable_rx(USART_SERIAL);\r
+ * \endcode\r
+ *\r
+ * \subsection usart_use_case_1_setup_flow Workflow\r
+ * -# Initialize system clock:\r
+ * \code\r
+ * sysclk_init();\r
+ * \endcode\r
+ * -# Configure the USART Tx and Rx pins as Outputs and Inputs respectively:\r
+ * \code\r
+ * pio_configure(USART_SERIAL_PIO, USART_SERIAL_TYPE,\r
+ * USART_SERIAL_MASK, USART_SERIAL_ATTR);\r
+ * \endcode\r
+ * -# Create USART options struct:\r
+ * \code\r
+ * const sam_usart_opt_t usart_console_settings = {\r
+ * USART_SERIAL_BAUDRATE,\r
+ * USART_SERIAL_CHAR_LENGTH,\r
+ * USART_SERIAL_PARITY,\r
+ * USART_SERIAL_STOP_BIT,\r
+ * US_MR_CHMODE_NORMAL\r
+ * };\r
+ * \endcode\r
+ * -# Enable the clock to the USART module:\r
+ * \code pmc_enable_periph_clk(USART_SERIAL_ID); \endcode\r
+ * -# Initialize the USART module in RS232 mode:\r
+ * \code usart_init_rs232(USART_SERIAL, &usart_console_settings, sysclk_get_main_hz()); \endcode\r
+ * -# Enable the Rx and Tx modes of the USART module:\r
+ * \code\r
+ * usart_enable_tx(USART_SERIAL);\r
+ * usart_enable_rx(USART_SERIAL);\r
+ * \endcode\r
+ *\r
+ * \section usart_use_case_1_usage Usage steps\r
+ *\r
+ * \subsection usart_use_case_1_usage_code Example code\r
+ * Add to, e.g., main loop in application C-file:\r
+ * \code\r
+ * received_byte = usart_getchar(USART_SERIAL);\r
+ * usart_putchar(USART_SERIAL, received_byte);\r
+ * \endcode\r
+ *\r
+ * \subsection usart_use_case_1_usage_flow Workflow\r
+ * -# Wait for reception of a character:\r
+ * \code usart_getchar(USART_SERIAL, &received_byte); \endcode\r
+ * -# Echo the character back:\r
+ * \code usart_putchar(USART_SERIAL, received_byte); \endcode\r
+ */\r
+\r
+/**\r
+ * \page usart_use_case_2 USART receive character and echo back via interrupts\r
+ *\r
+ * In this use case, the USART module is configured for:\r
+ * - Using USART0\r
+ * - Baudrate: 9600\r
+ * - Character length: 8 bit\r
+ * - Parity mode: Disabled\r
+ * - Stop bit: None\r
+ * - RS232 mode\r
+ *\r
+ * The use case waits for a received character on the configured USART and\r
+ * echoes the character back to the same USART. The character reception is\r
+ * performed via an interrupt handler, rather than the polling method used\r
+ * in \ref usart_use_case_1.\r
+ *\r
+ * \section usart_use_case_2_setup Setup steps\r
+ *\r
+ * \subsection usart_use_case_2_setup_prereq Prerequisites\r
+ * -# \ref sysclk_group "System Clock Management (sysclock)"\r
+ * -# \ref pio_group "Parallel Input/Output Controller (pio)"\r
+ * -# \ref pmc_group "Power Management Controller (pmc)"\r
+ *\r
+ * \subsection usart_use_case_2_setup_code Example code\r
+ * The following configuration must be added to the project (typically to a \r
+ * conf_usart.h file, but it can also be added to your main application file.):\r
+ * \code\r
+ * #define USART_SERIAL USART0\r
+ * #define USART_SERIAL_ID ID_USART0\r
+ * #define USART_SERIAL_ISR_HANDLER USART0_Handler\r
+ * #define USART_SERIAL_PIO PINS_USART_PIO\r
+ * #define USART_SERIAL_TYPE PINS_USART_TYPE\r
+ * #define USART_SERIAL_PINS PINS_USART_PINS\r
+ * #define USART_SERIAL_MASK PINS_USART_MASK\r
+ * #define USART_SERIAL_BAUDRATE 9600\r
+ * #define USART_SERIAL_CHAR_LENGTH US_MR_CHRL_8_BIT\r
+ * #define USART_SERIAL_PARITY US_MR_PAR_NO\r
+ * #define USART_SERIAL_STOP_BIT US_MR_NBSTOP_1_BIT\r
+ * \endcode\r
+ *\r
+ * A variable for the received byte must be added:\r
+ * \code\r
+ * uint32_t received_byte;\r
+ * \endcode\r
+ *\r
+ * Add to application initialization:\r
+ * \code\r
+ * sysclk_init();\r
+ *\r
+ * pio_configure(USART_SERIAL_PIO, USART_SERIAL_TYPE,\r
+ * USART_SERIAL_MASK, USART_SERIAL_ATTR);\r
+ * \r
+ * const sam_usart_opt_t usart_console_settings = {\r
+ * USART_SERIAL_BAUDRATE,\r
+ * USART_SERIAL_CHAR_LENGTH,\r
+ * USART_SERIAL_PARITY,\r
+ * USART_SERIAL_STOP_BIT,\r
+ * US_MR_CHMODE_NORMAL\r
+ * };\r
+ * \r
+ * pmc_enable_periph_clk(USART_SERIAL_ID);\r
+ * \r
+ * usart_init_rs232(USART_SERIAL, &usart_console_settings, sysclk_get_main_hz());\r
+ * usart_enable_tx(USART_SERIAL);\r
+ * usart_enable_rx(USART_SERIAL);\r
+ * \r
+ * usart_enable_interrupt(USART_SERIAL, US_IER_RXRDY);\r
+ * NVIC_EnableIRQ(USART_SERIAL_IRQ);\r
+ * \endcode\r
+ *\r
+ * \subsection usart_use_case_2_setup_flow Workflow\r
+ * -# Initialize system clock:\r
+ * \code\r
+ * sysclk_init();\r
+ * \endcode\r
+ * -# Configure the USART Tx and Rx pins as Outputs and Inputs respectively:\r
+ * \code\r
+ * pio_configure(USART_SERIAL_PIO, USART_SERIAL_TYPE,\r
+ * USART_SERIAL_MASK, USART_SERIAL_ATTR);\r
+ * \endcode\r
+ * -# Create USART options struct:\r
+ * \code\r
+ * const sam_usart_opt_t usart_console_settings = {\r
+ * USART_SERIAL_BAUDRATE,\r
+ * USART_SERIAL_CHAR_LENGTH,\r
+ * USART_SERIAL_PARITY,\r
+ * USART_SERIAL_STOP_BIT,\r
+ * US_MR_CHMODE_NORMAL\r
+ * };\r
+ * \endcode\r
+ * -# Enable the clock to the USART module:\r
+ * \code pmc_enable_periph_clk(USART_SERIAL_ID); \endcode\r
+ * -# Initialize the USART module in RS232 mode:\r
+ * \code usart_init_rs232(USART_SERIAL, &usart_console_settings, sysclk_get_main_hz()); \endcode\r
+ * -# Enable the Rx and Tx modes of the USART module:\r
+ * \code\r
+ * usart_enable_tx(USART_SERIAL);\r
+ * usart_enable_rx(USART_SERIAL);\r
+ * \endcode\r
+ * -# Enable the USART character reception interrupt, and general interrupts for the USART module.\r
+ * \code\r
+ * usart_enable_interrupt(USART_SERIAL, US_IER_RXRDY);\r
+ * NVIC_EnableIRQ(USART_SERIAL_IRQ);\r
+ * \endcode\r
+ * \section usart_use_case_2_usage Usage steps\r
+ *\r
+ * \subsection usart_use_case_2_usage_code Example code\r
+ * Add to your main application C-file the USART interrupt handler:\r
+ * \code\r
+ * void USART_SERIAL_ISR_HANDLER(void)\r
+ * {\r
+ * uint32_t dw_status = usart_get_status(USART_SERIAL);\r
+ * \r
+ * if (dw_status & US_CSR_RXRDY) {\r
+ * uint32_t received_byte;\r
+ * \r
+ * usart_read(USART_SERIAL, &received_byte);\r
+ * usart_write(USART_SERIAL, received_byte);\r
+ * }\r
+ * }\r
+ * \endcode\r
+ *\r
+ * \subsection usart_use_case_2_usage_flow Workflow\r
+ * -# When the USART ISR fires, retrieve the USART module interrupt flags:\r
+ * \code uint32_t dw_status = usart_get_status(USART_SERIAL); \endcode\r
+ * -# Check if the USART Receive Character interrupt has fired:\r
+ * \code if (dw_status & US_CSR_RXRDY) \endcode\r
+ * -# If a character has been received, fetch it into a temporary variable:\r
+ * \code usart_read(USART_SERIAL, &received_byte); \endcode\r
+ * -# Echo the character back:\r
+ * \code usart_write(USART_SERIAL, received_byte); \endcode\r
+ */\r
+\r
+#endif /* USART_H_INCLUDED */\r
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)\r
__ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) );\r
#endif\r
+ ( void ) fpscr;\r
}\r
\r
#endif /* (__CORTEX_M == 0x04) */\r
#define CONF_BOARD_H\r
\r
/* Configure UART pins */\r
-#define CONF_BOARD_UART_CONSOLE\r
+//#define CONF_BOARD_UART_CONSOLE\r
\r
/* Configure ADC example pins */\r
//#define CONF_BOARD_ADC\r
//#define CONF_BOARD_SPI_NPCS3\r
\r
/* Configure USART RXD pin */\r
-//#define CONF_BOARD_USART_RXD\r
+#define CONF_BOARD_USART_RXD\r
\r
/* Configure USART TXD pin */\r
-//#define CONF_BOARD_USART_TXD\r
+#define CONF_BOARD_USART_TXD\r
\r
/* Configure USART CTS pin */\r
//#define CONF_BOARD_USART_CTS\r
//#define CONF_BOARD_USART_SCK\r
\r
/* Configure ADM33312 enable pin */\r
-//#define CONF_BOARD_ADM3312_EN\r
+#define CONF_BOARD_ADM3312_EN\r
\r
/* Configure IrDA transceiver shutdown pin */\r
//#define CONF_BOARD_TFDU4300_SD\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief SAM4S clock configuration.\r
+ *\r
+ * Copyright (c) 2011 - 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef CONF_CLOCK_H_INCLUDED\r
+#define CONF_CLOCK_H_INCLUDED\r
+\r
+// ===== System Clock (MCK) Source Options\r
+//#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_SLCK_RC\r
+//#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_SLCK_XTAL\r
+//#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_SLCK_BYPASS\r
+//#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_MAINCK_4M_RC\r
+//#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_MAINCK_8M_RC\r
+//#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_MAINCK_12M_RC\r
+//#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_MAINCK_XTAL\r
+//#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_MAINCK_BYPASS\r
+#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_PLLACK\r
+//#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_PLLBCK\r
+\r
+// ===== System Clock (MCK) Prescaler Options (Fmck = Fsys / (SYSCLK_PRES))\r
+//#define CONFIG_SYSCLK_PRES SYSCLK_PRES_1\r
+#define CONFIG_SYSCLK_PRES SYSCLK_PRES_2\r
+//#define CONFIG_SYSCLK_PRES SYSCLK_PRES_4\r
+//#define CONFIG_SYSCLK_PRES SYSCLK_PRES_8\r
+//#define CONFIG_SYSCLK_PRES SYSCLK_PRES_16\r
+//#define CONFIG_SYSCLK_PRES SYSCLK_PRES_32\r
+//#define CONFIG_SYSCLK_PRES SYSCLK_PRES_64\r
+//#define CONFIG_SYSCLK_PRES SYSCLK_PRES_3\r
+\r
+// ===== PLL0 (A) Options (Fpll = (Fclk * PLL_mul) / PLL_div)\r
+// Use mul and div effective values here.\r
+#define CONFIG_PLL0_SOURCE PLL_SRC_MAINCK_XTAL\r
+#define CONFIG_PLL0_MUL 20\r
+#define CONFIG_PLL0_DIV 1\r
+\r
+// ===== PLL1 (B) Options (Fpll = (Fclk * PLL_mul) / PLL_div)\r
+// Use mul and div effective values here.\r
+//#define CONFIG_PLL1_SOURCE PLL_SRC_MAINCK_XTAL\r
+//#define CONFIG_PLL1_MUL 16\r
+//#define CONFIG_PLL1_DIV 2\r
+\r
+// ===== USB Clock Source Options (Fusb = FpllX / USB_div)\r
+// Use div effective value here.\r
+//#define CONFIG_USBCLK_SOURCE USBCLK_SRC_PLL0\r
+//#define CONFIG_USBCLK_SOURCE USBCLK_SRC_PLL1\r
+//#define CONFIG_USBCLK_DIV 2\r
+\r
+// ===== Target frequency (System clock)\r
+// - XTAL frequency: 12MHz\r
+// - System clock source: PLLA\r
+// - System clock prescaler: 2 (divided by 2)\r
+// - PLLA source: XTAL\r
+// - PLLA output: XTAL * 20 / 1\r
+// - System clock: 12 * 20 / 1 / 2 = 120MHz\r
+// ===== Target frequency (USB Clock)\r
+// - USB clock source: PLLB\r
+// - USB clock devider: 2 (devided by 2)\r
+// - PLLB output: XTAL * 16 / 2\r
+// - USB clock: 12 * 16 / 2 / 2 = 48MHz\r
+\r
+\r
+#endif /* CONF_CLOCK_H_INCLUDED */\r
***************************************************************************\r
* *\r
* Having a problem? Start by reading the FAQ "My application does *\r
- * not run, what could be wrong? *\r
+ * not run, what could be wrong?" *\r
* *\r
* http://www.FreeRTOS.org/FAQHelp.html *\r
* *\r
* This file implements the code that is not demo specific, including the\r
* hardware setup and FreeRTOS hook functions.\r
*\r
- * \r
- * Additional code:\r
- * \r
- * This demo does not contain a non-kernel interrupt service routine that\r
- * can be used as an example for application writers to use as a reference.\r
- * Therefore, the framework of a dummy (not installed) handler is provided\r
- * in this file. The dummy function is called Dummy_IRQHandler(). Please\r
- * ensure to read the comments in the function itself, but more importantly,\r
- * the notes on the function contained on the documentation page for this demo\r
- * that is found on the FreeRTOS.org web site.\r
*/\r
\r
/* Standard includes. */\r
#include "FreeRTOS.h"\r
#include "task.h"\r
\r
+/* Standard demo includes - just needed for the LED (ParTest) initialisation\r
+function. */\r
+#include "partest.h"\r
+\r
/* Atmel library includes. */\r
#include <asf.h>\r
\r
/* Set mainCREATE_SIMPLE_BLINKY_DEMO_ONLY to one to run the simple blinky demo,\r
or 0 to run the more comprehensive test and demo application. */\r
-#define mainCREATE_SIMPLE_BLINKY_DEMO_ONLY 1\r
+#define mainCREATE_SIMPLE_BLINKY_DEMO_ONLY 0\r
\r
/*-----------------------------------------------------------*/\r
\r
\r
/*-----------------------------------------------------------*/\r
\r
+/* See the documentation page for this demo on the FreeRTOS.org web site for\r
+full information - including hardware setup requirements. */\r
+\r
int main( void )\r
{\r
/* Prepare the hardware to run this demo. */\r
{\r
extern void SystemCoreClockUpdate( void );\r
\r
- /* Ensure SystemCoreClock variable is set. */\r
- SystemCoreClockUpdate();\r
+ /* ASF function to setup clocking. */\r
+ sysclk_init();\r
\r
/* Ensure all priority bits are assigned as preemption priority bits. */\r
NVIC_SetPriorityGrouping( 0 );\r
\r
/* Atmel library function to setup for the evaluation kit being used. */\r
board_init();\r
+\r
+ /* Perform any configuration necessary to use the ParTest LED output \r
+ functions. */\r
+ vParTestInitialise();\r
}\r
/*-----------------------------------------------------------*/\r
\r
}\r
/*-----------------------------------------------------------*/\r
\r
-#ifdef JUST_AN_EXAMPLE_ISR\r
-\r
-void Dummy_IRQHandler(void)\r
-{\r
-long lHigherPriorityTaskWoken = pdFALSE;\r
-\r
- /* Clear the interrupt if necessary. */\r
- Dummy_ClearITPendingBit();\r
- \r
- /* This interrupt does nothing more than demonstrate how to synchronise a\r
- task with an interrupt. A semaphore is used for this purpose. Note\r
- lHigherPriorityTaskWoken is initialised to zero. */\r
- xSemaphoreGiveFromISR( xTestSemaphore, &lHigherPriorityTaskWoken );\r
- \r
- /* If there was a task that was blocked on the semaphore, and giving the\r
- semaphore caused the task to unblock, and the unblocked task has a priority\r
- higher than the current Running state task (the task that this interrupt\r
- interrupted), then lHigherPriorityTaskWoken will have been set to pdTRUE\r
- internally within xSemaphoreGiveFromISR(). Passing pdTRUE into the \r
- portEND_SWITCHING_ISR() macro will result in a context switch being pended to\r
- ensure this interrupt returns directly to the unblocked, higher priority, \r
- task. Passing pdFALSE into portEND_SWITCHING_ISR() has no effect. */\r
- portEND_SWITCHING_ISR( lHigherPriorityTaskWoken );\r
-}\r
-\r
-#endif /* JUST_AN_EXAMPLE_ISR */\r
the queue empty. */\r
#define mainQUEUE_LENGTH ( 1 )\r
\r
-/* Values passed to the two tasks just to check the task parameter\r
+/* Values passed to the two tasks just to check the task parameter \r
functionality. */\r
#define mainQUEUE_SEND_PARAMETER ( 0x1111UL )\r
#define mainQUEUE_RECEIVE_PARAMETER ( 0x22UL )\r
*/\r
void main_blinky( void );\r
\r
-/*\r
- * The hardware only has a single LED. Simply toggle it.\r
- */\r
-extern void vMainToggleLED( void );\r
-\r
/*-----------------------------------------------------------*/\r
\r
/* The queue used by both tasks. */\r
* In addition to the standard demo tasks, the following tasks and tests are\r
* defined and/or created within this file:\r
*\r
- * "Reg test" tasks - These fill both the core and floating point registers with\r
- * known values, then check that each register maintains its expected value for\r
- * the lifetime of the task. Each task uses a different set of values. The reg\r
- * test tasks execute with a very low priority, so get preempted very\r
- * frequently. A register containing an unexpected value is indicative of an\r
- * error in the context switching mechanism.\r
- *\r
* "Check" timer - The check software timer period is initially set to three\r
* seconds. The callback function associated with the check software timer\r
- * checks that all the standard demo tasks, and the register check tasks, are\r
- * not only still executing, but are executing without reporting any errors. If\r
- * the check software timer discovers that a task has either stalled, or\r
- * reported an error, then it changes its own execution period from the initial\r
- * three seconds, to just 200ms. The check software timer callback function\r
- * also toggles the single LED each time it is called. This provides a visual\r
- * indication of the system status: If the LED toggles every three seconds,\r
- * then no issues have been discovered. If the LED toggles every 200ms, then\r
- * an issue has been discovered with at least one task.\r
+ * checks that all the standard demo tasks are not only still executing, but \r
+ * are executing without reporting any errors. If the check software timer \r
+ * discovers that a task has either stalled, or reported an error, then it \r
+ * changes its own execution period from the initial three seconds, to just \r
+ * 200ms. The check software timer callback function also toggles the green \r
+ * LED each time it is called. This provides a visual indication of the system \r
+ * status: If the green LED toggles every three seconds, then no issues have \r
+ * been discovered. If the green LED toggles every 200ms, then an issue has \r
+ * been discovered with at least one task.\r
+ *\r
+ * See the documentation page for this demo on the FreeRTOS.org web site for\r
+ * full information, including hardware setup requirements. \r
*/\r
\r
/* Standard includes. */\r
#include "GenQTest.h"\r
#include "recmutex.h"\r
#include "death.h"\r
+#include "flash_timer.h"\r
#include "partest.h"\r
+#include "comtest2.h"\r
+\r
\r
/* Atmel library includes. */\r
#include "asf.h"\r
#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2UL )\r
#define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + 3UL )\r
#define mainFLOP_TASK_PRIORITY ( tskIDLE_PRIORITY )\r
+#define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
\r
/* A block time of zero simply means "don't block". */\r
#define mainDONT_BLOCK ( 0UL )\r
in ticks using the portTICK_RATE_MS constant. */\r
#define mainERROR_CHECK_TIMER_PERIOD_MS ( 200UL / portTICK_RATE_MS )\r
\r
-/* The LED toggles by the check timer. */\r
-#define mainCHECK_LED ( 3 )\r
+/* The standard demo flash timers can be used to flash any number of LEDs. In\r
+this case, because only three LEDs are available, and one is in use by the\r
+check timer, only two are used by the flash timers. */\r
+#define mainNUMBER_OF_FLASH_TIMERS_LEDS ( 2 )\r
+\r
+/* The LED toggled by the check timer. The first two LEDs are toggle by the\r
+standard demo flash timers. */\r
+#define mainCHECK_LED ( 2 )\r
+\r
+/* Baud rate used by the comtest tasks. */\r
+#define mainCOM_TEST_BAUD_RATE ( 115200 )\r
+\r
+/* The LED used by the comtest tasks. In this case, there are no LEDs available\r
+for the comtest, so the LED number is deliberately out of range. */\r
+#define mainCOM_TEST_LED ( 3 )\r
\r
/*-----------------------------------------------------------*/\r
\r
vStartRecursiveMutexTasks();\r
vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY );\r
vStartSemaphoreTasks( mainSEM_TEST_PRIORITY );\r
+ vStartLEDFlashTimers( mainNUMBER_OF_FLASH_TIMERS_LEDS );\r
+ vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainCOM_TEST_BAUD_RATE, mainCOM_TEST_LED );\r
\r
/* Create the software timer that performs the 'check' functionality,\r
as described at the top of this file. */\r
unsigned long ulErrorFound = pdFALSE;\r
\r
/* Check all the demo tasks (other than the flash tasks) to ensure\r
- that they are all still running, and that none have detected an error. */\r
+ they are all still running, and that none have detected an error. */\r
\r
if( xAreIntegerMathsTaskStillRunning() != pdTRUE )\r
{\r
ulErrorFound = pdTRUE;\r
}\r
\r
+ if( xAreComTestTasksStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorFound = pdTRUE;\r
+ }\r
+\r
/* Toggle the check LED to give an indication of the system status. If\r
the LED toggles every mainCHECK_TIMER_PERIOD_MS milliseconds then\r
everything is ok. A faster toggle indicates an error. */\r
--- /dev/null
+/*\r
+ FreeRTOS V7.1.1 - Copyright (C) 2012 Real Time Engineers Ltd.\r
+ \r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS tutorial books are available in pdf and paperback. *\r
+ * Complete, revised, and edited pdf reference manuals are also *\r
+ * available. *\r
+ * *\r
+ * Purchasing FreeRTOS documentation will not only help you, by *\r
+ * ensuring you get running as quickly as possible and with an *\r
+ * in-depth knowledge of how to use FreeRTOS, it will also help *\r
+ * the FreeRTOS project to continue with its mission of providing *\r
+ * professional grade, cross platform, de facto standard solutions *\r
+ * for microcontrollers - completely free of charge! *\r
+ * *\r
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
+ * *\r
+ * Thank you for using FreeRTOS, and thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+ >>>NOTE<<< The modification to the GPL is included to allow you to\r
+ distribute a combined work that includes FreeRTOS without being obliged to\r
+ provide the source code for proprietary components outside of the FreeRTOS\r
+ kernel. FreeRTOS is distributed in the hope that it will be useful, but\r
+ WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ more details. You should have received a copy of the GNU General Public\r
+ License and the FreeRTOS license exception along with FreeRTOS; if not it\r
+ can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
+ by writing to Richard Barry, contact details for whom are available on the\r
+ FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+ \r
+ ***************************************************************************\r
+ * *\r
+ * Having a problem? Start by reading the FAQ "My application does *\r
+ * not run, what could be wrong? *\r
+ * *\r
+ * http://www.FreeRTOS.org/FAQHelp.html *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ \r
+ http://www.FreeRTOS.org - Documentation, training, latest information, \r
+ license and contact details.\r
+ \r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool.\r
+\r
+ Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell \r
+ the code with commercial support, indemnification, and middleware, under \r
+ the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also\r
+ provide a safety engineered and independently SIL3 certified version under \r
+ the SafeRTOS brand: http://www.SafeRTOS.com.\r
+*/\r
+\r
+/*\r
+ BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER FOR USART1.\r
+ \r
+ ***Note*** This example uses queues to send each character into an interrupt\r
+ service routine and out of an interrupt service routine individually. This\r
+ is done to demonstrate queues being used in an interrupt, and to deliberately\r
+ load the system to test the FreeRTOS port. It is *NOT* meant to be an \r
+ example of an efficient implementation. An efficient implementation should\r
+ use FIFO's or DMA if available, and only use FreeRTOS API functions when \r
+ enough has been received to warrant a task being unblocked to process the\r
+ data.\r
+*/\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "queue.h"\r
+#include "semphr.h"\r
+#include "comtest2.h"\r
+\r
+/* Library includes. */\r
+#include "asf.h"\r
+\r
+/* Demo application includes. */\r
+#include "demo_serial.h"\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Misc defines. */\r
+#define serINVALID_QUEUE ( ( xQueueHandle ) 0 )\r
+#define serNO_BLOCK ( ( portTickType ) 0 )\r
+#define serPMC_USART_ID ( BOARD_ID_USART )\r
+\r
+/* The USART supported by this file. */\r
+#define serUSART_PORT ( USART1 )\r
+#define serUSART_IRQ ( USART1_IRQn )\r
+\r
+/* Every bit in the interrupt mask. */\r
+#define serMASK_ALL_INTERRUPTS ( 0xffffffffUL )\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* The queue used to hold received characters. */\r
+static xQueueHandle xRxedChars;\r
+static xQueueHandle xCharsForTx;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * See the serial.h header file.\r
+ */\r
+xComPortHandle xSerialPortInitMinimal( unsigned long ulWantedBaud, unsigned portBASE_TYPE uxQueueLength )\r
+{\r
+uint32_t ulChar;\r
+xComPortHandle xReturn;\r
+const sam_usart_opt_t xUSARTSettings = \r
+{\r
+ ulWantedBaud,\r
+ US_MR_CHRL_8_BIT,\r
+ US_MR_PAR_NO,\r
+ US_MR_NBSTOP_1_BIT,\r
+ US_MR_CHMODE_NORMAL, \r
+ 0 /* Only used in IrDA mode. */\r
+};\r
+\r
+ /* Create the queues used to hold Rx/Tx characters. */\r
+ xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed char ) );\r
+ xCharsForTx = xQueueCreate( uxQueueLength + 1, ( unsigned portBASE_TYPE ) sizeof( signed char ) );\r
+ \r
+ /* If the queues were created correctly then setup the serial port\r
+ hardware. */\r
+ if( ( xRxedChars != serINVALID_QUEUE ) && ( xCharsForTx != serINVALID_QUEUE ) )\r
+ {\r
+ /* Enable the peripheral clock in the PMC. */\r
+ pmc_enable_periph_clk( serPMC_USART_ID );\r
+\r
+ /* Configure USART in serial mode. */\r
+ usart_init_rs232( serUSART_PORT, &xUSARTSettings, sysclk_get_cpu_hz() );\r
+\r
+ /* Disable all the interrupts. */\r
+ usart_disable_interrupt( serUSART_PORT, serMASK_ALL_INTERRUPTS );\r
+\r
+ /* Enable the receiver and transmitter. */\r
+ usart_enable_tx( serUSART_PORT );\r
+ usart_enable_rx( serUSART_PORT );\r
+ \r
+ /* Clear any characters before enabling interrupt. */\r
+ usart_getchar( serUSART_PORT, &ulChar );\r
+ \r
+ /* Enable Rx end interrupt. */\r
+ usart_enable_interrupt( serUSART_PORT, US_IER_RXRDY );\r
+\r
+ /* Configure and enable interrupt of USART. */\r
+ NVIC_SetPriority( serUSART_IRQ, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );\r
+ NVIC_EnableIRQ( serUSART_IRQ );\r
+ }\r
+ else\r
+ {\r
+ xReturn = ( xComPortHandle ) 0;\r
+ }\r
+\r
+ /* This demo file only supports a single port but we have to return\r
+ something to comply with the standard demo header file. */\r
+ return xReturn;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed char *pcRxedChar, portTickType xBlockTime )\r
+{\r
+ /* The port handle is not required as this driver only supports one port. */\r
+ ( void ) pxPort;\r
+\r
+ /* Get the next character from the buffer. Return false if no characters\r
+ are available, or arrive before xBlockTime expires. */\r
+ if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) )\r
+ {\r
+ return pdTRUE;\r
+ }\r
+ else\r
+ {\r
+ return pdFALSE;\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vSerialPutString( xComPortHandle pxPort, const signed char * const pcString, unsigned short usStringLength )\r
+{\r
+signed char *pxNext;\r
+\r
+ /* A couple of parameters that this port does not use. */\r
+ ( void ) usStringLength;\r
+ ( void ) pxPort;\r
+\r
+ /* NOTE: This implementation does not handle the queue being full as no\r
+ block time is used! */\r
+\r
+ /* The port handle is not required as this driver only supports USART1. */\r
+ ( void ) pxPort;\r
+\r
+ /* Send each character in the string, one at a time. */\r
+ pxNext = ( signed char * ) pcString;\r
+ while( *pxNext )\r
+ { \r
+ xSerialPutChar( pxPort, *pxNext, serNO_BLOCK );\r
+ pxNext++;\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed char cOutChar, portTickType xBlockTime )\r
+{\r
+signed portBASE_TYPE xReturn;\r
+\r
+ /* This simple example only supports one port. */\r
+ ( void ) pxPort;\r
+\r
+ if( xQueueSend( xCharsForTx, &cOutChar, xBlockTime ) == pdPASS )\r
+ {\r
+ xReturn = pdPASS;\r
+ usart_enable_interrupt( serUSART_PORT, US_IER_TXRDY );\r
+ }\r
+ else\r
+ {\r
+ xReturn = pdFAIL;\r
+ }\r
+\r
+ return xReturn;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vSerialClose( xComPortHandle xPort )\r
+{\r
+ /* Not supported as not required by the demo application. */\r
+ ( void ) xPort;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void USART1_Handler( void )\r
+{\r
+portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE;\r
+uint8_t ucChar;\r
+uint32_t ulChar;\r
+uint32_t ulUSARTStatus, ulUSARTMask;\r
+\r
+ ulUSARTStatus = usart_get_status( serUSART_PORT );\r
+ ulUSARTMask = usart_get_interrupt_mask( serUSART_PORT );\r
+ ulUSARTStatus &= ulUSARTMask;\r
+\r
+ if( ( ulUSARTStatus & US_CSR_TXRDY ) != 0UL )\r
+ {\r
+ /* The interrupt was caused by the TX register becoming empty. Are \r
+ there any more characters to transmit? */\r
+ if( xQueueReceiveFromISR( xCharsForTx, &ucChar, &xHigherPriorityTaskWoken ) == pdTRUE )\r
+ {\r
+ /* A character was retrieved from the queue so can be sent to the\r
+ USART now. */\r
+ usart_putchar( serUSART_PORT, ( uint32_t ) ucChar );\r
+ }\r
+ else\r
+ {\r
+ usart_disable_interrupt( serUSART_PORT, US_IER_TXRDY ); \r
+ } \r
+ }\r
+ \r
+ if( ( ulUSARTStatus & US_CSR_RXRDY ) != 0UL )\r
+ {\r
+ /* A character has been received on the USART, send it to the Rx\r
+ handler task. */\r
+ usart_getchar( serUSART_PORT, &ulChar );\r
+ ucChar = ( uint8_t ) ( ulChar & 0xffUL );\r
+ xQueueSendFromISR( xRxedChars, &ucChar, &xHigherPriorityTaskWoken );\r
+ } \r
+\r
+ /* If sending or receiving from a queue has caused a task to unblock, and\r
+ the unblocked task has a priority equal to or higher than the currently \r
+ running task (the task this ISR interrupted), then xHigherPriorityTaskWoken \r
+ will have automatically been set to pdTRUE within the queue send or receive \r
+ function. portEND_SWITCHING_ISR() will then ensure that this ISR returns \r
+ directly to the higher priority unblocked task. */\r
+ portEND_SWITCHING_ISR( xHigherPriorityTaskWoken );\r
+}\r
+\r
+\r
+\r
+\r
+\r
+ \r
projects / freertos / commitdiff