at91: add at91sam9263 chip register definition

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Cc: Nicolas Ferre <nicolas.ferre@atmel.com>
Cc: Patrice Vilchez <patrice.vilchez@atmel.com>

diff --git a/tcl/chip/atmel/at91/at91sam9263.cfg b/tcl/chip/atmel/at91/at91sam9263.cfg
new file mode 100644 (file)
index 0000000..8e22eb2
--- /dev/null
+++ b/tcl/chip/atmel/at91/at91sam9263.cfg
@@ -0,0 +1,113 @@
+#
+# Peripheral identifiers/interrupts.
+#
+set AT91_ID_FIQ                0       ;# Advanced Interrupt Controller (FIQ)
+set AT91_ID_SYS                1       ;# System Peripherals
+set AT91SAM9263_ID_PIOA        2       ;# Parallel IO Controller A
+set AT91SAM9263_ID_PIOB        3       ;# Parallel IO Controller B
+set AT91SAM9263_ID_PIOCDE      4       ;# Parallel IO Controller C, D and E
+set AT91SAM9263_ID_US0 7       ;# USART 0
+set AT91SAM9263_ID_US1 8       ;# USART 1
+set AT91SAM9263_ID_US2 9       ;# USART 2
+set AT91SAM9263_ID_MCI0        10      ;# Multimedia Card Interface 0
+set AT91SAM9263_ID_MCI1        11      ;# Multimedia Card Interface 1
+set AT91SAM9263_ID_CAN 12      ;# CAN
+set AT91SAM9263_ID_TWI 13      ;# Two-Wire Interface
+set AT91SAM9263_ID_SPI0        14      ;# Serial Peripheral Interface 0
+set AT91SAM9263_ID_SPI1        15      ;# Serial Peripheral Interface 1
+set AT91SAM9263_ID_SSC0        16      ;# Serial Synchronous Controller 0
+set AT91SAM9263_ID_SSC1        17      ;# Serial Synchronous Controller 1
+set AT91SAM9263_ID_AC97C       18      ;# AC97 Controller
+set AT91SAM9263_ID_TCB 19      ;# Timer Counter 0, 1 and 2
+set AT91SAM9263_ID_PWMC        20      ;# Pulse Width Modulation Controller
+set AT91SAM9263_ID_EMAC        21      ;# Ethernet
+set AT91SAM9263_ID_2DGE        23      ;# 2D Graphic Engine
+set AT91SAM9263_ID_UDP 24      ;# USB Device Port
+set AT91SAM9263_ID_ISI 25      ;# Image Sensor Interface
+set AT91SAM9263_ID_LCDC        26      ;# LCD Controller
+set AT91SAM9263_ID_DMA 27      ;# DMA Controller
+set AT91SAM9263_ID_UHP 29      ;# USB Host port
+set AT91SAM9263_ID_IRQ0        30      ;# Advanced Interrupt Controller (IRQ0)
+set AT91SAM9263_ID_IRQ1        31      ;# Advanced Interrupt Controller (IRQ1)
+
+
+#
+# User Peripheral physical base addresses.
+#
+set AT91SAM9263_BASE_UDP               0xfff78000
+set AT91SAM9263_BASE_TCB0              0xfff7c000
+set AT91SAM9263_BASE_TC0               0xfff7c000
+set AT91SAM9263_BASE_TC1               0xfff7c040
+set AT91SAM9263_BASE_TC2               0xfff7c080
+set AT91SAM9263_BASE_MCI0              0xfff80000
+set AT91SAM9263_BASE_MCI1              0xfff84000
+set AT91SAM9263_BASE_TWI               0xfff88000
+set AT91SAM9263_BASE_US0               0xfff8c000
+set AT91SAM9263_BASE_US1               0xfff90000
+set AT91SAM9263_BASE_US2               0xfff94000
+set AT91SAM9263_BASE_SSC0              0xfff98000
+set AT91SAM9263_BASE_SSC1              0xfff9c000
+set AT91SAM9263_BASE_AC97C             0xfffa0000
+set AT91SAM9263_BASE_SPI0              0xfffa4000
+set AT91SAM9263_BASE_SPI1              0xfffa8000
+set AT91SAM9263_BASE_CAN               0xfffac000
+set AT91SAM9263_BASE_PWMC              0xfffb8000
+set AT91SAM9263_BASE_EMAC              0xfffbc000
+set AT91SAM9263_BASE_ISI               0xfffc4000
+set AT91SAM9263_BASE_2DGE              0xfffc8000
+set AT91_BASE_SYS                      0xffffe000
+
+#
+# System Peripherals (offset from AT91_BASE_SYS)
+#
+set AT91_ECC0          0xffffe000
+set AT91_SDRAMC0       0xffffe200
+set AT91_SMC0          0xffffe400
+set AT91_ECC1          0xffffe600
+set AT91_SDRAMC1       0xffffe800
+set AT91_SMC1          0xffffea00
+set AT91_MATRIX                0xffffec00
+set AT91_CCFG          0xffffed10
+set AT91_DBGU          0xffffee00
+set AT91_AIC           0xfffff000
+set AT91_PIOA          0xfffff200
+set AT91_PIOB          0xfffff400
+set AT91_PIOC          0xfffff600
+set AT91_PIOD          0xfffff800
+set AT91_PIOE          0xfffffa00
+set AT91_PMC           0xfffffc00
+set AT91_RSTC          0xfffffd00
+set AT91_SHDWC         0xfffffd10
+set AT91_RTT0          0xfffffd20
+set AT91_PIT           0xfffffd30
+set AT91_WDT           0xfffffd40
+set AT91_RTT1          0xfffffd50
+set AT91_GPBR          0xfffffd60
+
+set AT91_USART0        $AT91SAM9263_BASE_US0
+set AT91_USART1        $AT91SAM9263_BASE_US1
+set AT91_USART2        $AT91SAM9263_BASE_US2
+
+set AT91_SMC   $AT91_SMC0
+set AT91_SDRAMC        $AT91_SDRAMC0
+
+#
+# Internal Memory.
+#
+set AT91SAM9263_SRAM0_BASE     0x00300000      ;# Internal SRAM 0 base address
+set AT91SAM9263_SRAM0_SIZE     0x00014000      ;# Internal SRAM 0 size (80Kb)
+
+set AT91SAM9263_ROM_BASE       0x00400000      ;# Internal ROM base address
+set AT91SAM9263_ROM_SIZE       0x00020000      ;# Internal ROM size (128Kb)
+
+set AT91SAM9263_SRAM1_BASE     0x00500000      ;# Internal SRAM 1 base address
+set AT91SAM9263_SRAM1_SIZE     0x00004000      ;# Internal SRAM 1 size (16Kb)
+
+set AT91SAM9263_LCDC_BASE      0x00700000      ;# LCD Controller
+set AT91SAM9263_DMAC_BASE      0x00800000      ;# DMA Controller
+set AT91SAM9263_UHP_BASE       0x00a00000      ;# USB Host controller
+
+#
+# Cpu Name
+#
+set AT91_CPU_NAME      "AT91SAM9263"

diff --git a/tcl/chip/atmel/at91/at91sam9263_matrix.cfg b/tcl/chip/atmel/at91/at91sam9263_matrix.cfg
new file mode 100644 (file)
index 0000000..8a74bcd
--- /dev/null
+++ b/tcl/chip/atmel/at91/at91sam9263_matrix.cfg
@@ -0,0 +1,112 @@
+set AT91_MATRIX_MCFG0  [expr ($AT91_MATRIX + 0x00)]    ;# Master Configuration Register 0
+set AT91_MATRIX_MCFG1  [expr ($AT91_MATRIX + 0x04)]    ;# Master Configuration Register 1
+set AT91_MATRIX_MCFG2  [expr ($AT91_MATRIX + 0x08)]    ;# Master Configuration Register 2
+set AT91_MATRIX_MCFG3  [expr ($AT91_MATRIX + 0x0C)]    ;# Master Configuration Register 3
+set AT91_MATRIX_MCFG4  [expr ($AT91_MATRIX + 0x10)]    ;# Master Configuration Register 4
+set AT91_MATRIX_MCFG5  [expr ($AT91_MATRIX + 0x14)]    ;# Master Configuration Register 5
+set AT91_MATRIX_MCFG6  [expr ($AT91_MATRIX + 0x18)]    ;# Master Configuration Register 6
+set AT91_MATRIX_MCFG7  [expr ($AT91_MATRIX + 0x1C)]    ;# Master Configuration Register 7
+set AT91_MATRIX_MCFG8  [expr ($AT91_MATRIX + 0x20)]    ;# Master Configuration Register 8
+set            AT91_MATRIX_ULBT        [expr (7 << 0)  ;# Undefined Length Burst Type
+set                    AT91_MATRIX_ULBT_INFINITE       [expr (0 << 0)]
+set                    AT91_MATRIX_ULBT_SINGLE         [expr (1 << 0)]
+set                    AT91_MATRIX_ULBT_FOUR           [expr (2 << 0)]
+set                    AT91_MATRIX_ULBT_EIGHT          [expr (3 << 0)]
+set                    AT91_MATRIX_ULBT_SIXTEEN        [expr (4 << 0)]
+
+set AT91_MATRIX_SCFG0  [expr ($AT91_MATRIX + 0x40)]    ;# Slave Configuration Register 0
+set AT91_MATRIX_SCFG1  [expr ($AT91_MATRIX + 0x44)]    ;# Slave Configuration Register 1
+set AT91_MATRIX_SCFG2  [expr ($AT91_MATRIX + 0x48)]    ;# Slave Configuration Register 2
+set AT91_MATRIX_SCFG3  [expr ($AT91_MATRIX + 0x4C)]    ;# Slave Configuration Register 3
+set AT91_MATRIX_SCFG4  [expr ($AT91_MATRIX + 0x50)]    ;# Slave Configuration Register 4
+set AT91_MATRIX_SCFG5  [expr ($AT91_MATRIX + 0x54)]    ;# Slave Configuration Register 5
+set AT91_MATRIX_SCFG6  [expr ($AT91_MATRIX + 0x58)]    ;# Slave Configuration Register 6
+set AT91_MATRIX_SCFG7  [expr ($AT91_MATRIX + 0x5C)]    ;# Slave Configuration Register 7
+set            AT91_MATRIX_SLOT_CYCLE          [expr (0xff << 0)]      ;# Maximum Number of Allowed Cycles for a Burst
+set            AT91_MATRIX_DEFMSTR_TYPE        [expr (3    << 16)]     ;# Default Master Type
+set                    AT91_MATRIX_DEFMSTR_TYPE_NONE   [expr (0 << 16)]
+set                    AT91_MATRIX_DEFMSTR_TYPE_LAST   [expr (1 << 16)]
+set                    AT91_MATRIX_DEFMSTR_TYPE_FIXED  [expr (2 << 16)]
+set            AT91_MATRIX_FIXED_DEFMSTR       [expr (0xf  << 18)]     ;# Fixed Index of Default Master
+set            AT91_MATRIX_ARBT                [expr (3    << 24)]     ;# Arbitration Type
+set                    AT91_MATRIX_ARBT_ROUND_ROBIN    [expr (0 << 24)]
+set                    AT91_MATRIX_ARBT_FIXED_PRIORITY [expr (1 << 24)]
+
+set AT91_MATRIX_PRAS0  [expr ($AT91_MATRIX + 0x80)]    ;# Priority Register A for Slave 0
+set AT91_MATRIX_PRBS0  [expr ($AT91_MATRIX + 0x84)]    ;# Priority Register B for Slave 0
+set AT91_MATRIX_PRAS1  [expr ($AT91_MATRIX + 0x88)]    ;# Priority Register A for Slave 1
+set AT91_MATRIX_PRBS1  [expr ($AT91_MATRIX + 0x8C)]    ;# Priority Register B for Slave 1
+set AT91_MATRIX_PRAS2  [expr ($AT91_MATRIX + 0x90)]    ;# Priority Register A for Slave 2
+set AT91_MATRIX_PRBS2  [expr ($AT91_MATRIX + 0x94)]    ;# Priority Register B for Slave 2
+set AT91_MATRIX_PRAS3  [expr ($AT91_MATRIX + 0x98)]    ;# Priority Register A for Slave 3
+set AT91_MATRIX_PRBS3  [expr ($AT91_MATRIX + 0x9C)]    ;# Priority Register B for Slave 3
+set AT91_MATRIX_PRAS4  [expr ($AT91_MATRIX + 0xA0)]    ;# Priority Register A for Slave 4
+set AT91_MATRIX_PRBS4  [expr ($AT91_MATRIX + 0xA4)]    ;# Priority Register B for Slave 4
+set AT91_MATRIX_PRAS5  [expr ($AT91_MATRIX + 0xA8)]    ;# Priority Register A for Slave 5
+set AT91_MATRIX_PRBS5  [expr ($AT91_MATRIX + 0xAC)]    ;# Priority Register B for Slave 5
+set AT91_MATRIX_PRAS6  [expr ($AT91_MATRIX + 0xB0)]    ;# Priority Register A for Slave 6
+set AT91_MATRIX_PRBS6  [expr ($AT91_MATRIX + 0xB4)]    ;# Priority Register B for Slave 6
+set AT91_MATRIX_PRAS7  [expr ($AT91_MATRIX + 0xB8)]    ;# Priority Register A for Slave 7
+set AT91_MATRIX_PRBS7  [expr ($AT91_MATRIX + 0xBC)]    ;# Priority Register B for Slave 7
+set            AT91_MATRIX_M0PR                [expr (3 << 0)]         ;# Master 0 Priority
+set            AT91_MATRIX_M1PR                [expr (3 << 4)]         ;# Master 1 Priority
+set            AT91_MATRIX_M2PR                [expr (3 << 8)]         ;# Master 2 Priority
+set            AT91_MATRIX_M3PR                [expr (3 << 12)]        ;# Master 3 Priority
+set            AT91_MATRIX_M4PR                [expr (3 << 16)]        ;# Master 4 Priority
+set            AT91_MATRIX_M5PR                [expr (3 << 20)]        ;# Master 5 Priority
+set            AT91_MATRIX_M6PR                [expr (3 << 24)]        ;# Master 6 Priority
+set            AT91_MATRIX_M7PR                [expr (3 << 28)]        ;# Master 7 Priority
+set            AT91_MATRIX_M8PR                [expr (3 << 0)]         ;# Master 8 Priority (in Register B)
+
+set AT91_MATRIX_MRCR   [expr ($AT91_MATRIX + 0x100)]   ;# Master Remap Control Register
+set            AT91_MATRIX_RCB0                [expr (1 << 0)] ;# Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master)
+set            AT91_MATRIX_RCB1                [expr (1 << 1)] ;# Remap Command for AHB Master 1 (ARM926EJ-S Data Master)
+set            AT91_MATRIX_RCB2                [expr (1 << 2)]
+set            AT91_MATRIX_RCB3                [expr (1 << 3)]
+set            AT91_MATRIX_RCB4                [expr (1 << 4)]
+set            AT91_MATRIX_RCB5                [expr (1 << 5)]
+set            AT91_MATRIX_RCB6                [expr (1 << 6)]
+set            AT91_MATRIX_RCB7                [expr (1 << 7)]
+set            AT91_MATRIX_RCB8                [expr (1 << 8)]
+
+set AT91_MATRIX_TCMR   [expr ($AT91_MATRIX + 0x114)]   ;# TCM Configuration Register
+set            AT91_MATRIX_ITCM_SIZE           [expr (0xf << 0)]       ;# Size of ITCM enabled memory block
+set                    AT91_MATRIX_ITCM_0              [expr (0 << 0)]
+set                    AT91_MATRIX_ITCM_16             [expr (5 << 0)]
+set                    AT91_MATRIX_ITCM_32             [expr (6 << 0)]
+set            AT91_MATRIX_DTCM_SIZE           [expr (0xf << 4)]       ;# Size of DTCM enabled memory block
+set                    AT91_MATRIX_DTCM_0              [expr (0 << 4)]
+set                    AT91_MATRIX_DTCM_16             [expr (5 << 4)]
+set                    AT91_MATRIX_DTCM_32             [expr (6 << 4)]
+
+set AT91_MATRIX_EBI0CSA        [expr ($AT91_MATRIX + 0x120)]   ;# EBI0 Chip Select Assignment Register
+set            AT91_MATRIX_EBI0_CS1A           [expr (1 << 1)] ;# Chip Select 1 Assignment
+set                    AT91_MATRIX_EBI0_CS1A_SMC               [expr (0 << 1)]
+set                    AT91_MATRIX_EBI0_CS1A_SDRAMC            [expr (1 << 1)]
+set            AT91_MATRIX_EBI0_CS3A           [expr (1 << 3)] ;# Chip Select 3 Assignmen
+set                    AT91_MATRIX_EBI0_CS3A_SMC               [expr (0 << 3)]
+set                    AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA    [expr (1 << 3)]
+set            AT91_MATRIX_EBI0_CS4A           [expr (1 << 4)] ;# Chip Select 4 Assignment
+set                    AT91_MATRIX_EBI0_CS4A_SMC               [expr (0 << 4)]
+set                    AT91_MATRIX_EBI0_CS4A_SMC_CF1           [expr (1 << 4)]
+set            AT91_MATRIX_EBI0_CS5A           [expr (1 << 5)] ;# Chip Select 5 Assignment
+set                    AT91_MATRIX_EBI0_CS5A_SMC               [expr (0 << 5)]
+set                    AT91_MATRIX_EBI0_CS5A_SMC_CF2           [expr (1 << 5)]
+set            AT91_MATRIX_EBI0_DBPUC          [expr (1 << 8)] ;# Data Bus Pull-up Configuration
+set            AT91_MATRIX_EBI0_VDDIOMSEL      [expr (1 << 16)]        ;# Memory voltage selection
+set                    AT91_MATRIX_EBI0_VDDIOMSEL_1_8V         [expr (0 << 16)]
+set                    AT91_MATRIX_EBI0_VDDIOMSEL_3_3V         [expr (1 << 16)]
+
+set AT91_MATRIX_EBI1CSA        [expr ($AT91_MATRIX + 0x124)]   ;# EBI1 Chip Select Assignment Register
+set            AT91_MATRIX_EBI1_CS1A           [expr (1 << 1)] ;# Chip Select 1 Assignment
+set                    AT91_MATRIX_EBI1_CS1A_SMC               [expr (0 << 1)]
+set                    AT91_MATRIX_EBI1_CS1A_SDRAMC            [expr (1 << 1)]
+set            AT91_MATRIX_EBI1_CS2A           [expr (1 << 3)] ;# Chip Select 3 Assignment
+set                    AT91_MATRIX_EBI1_CS2A_SMC               [expr (0 << 3)]
+set                    AT91_MATRIX_EBI1_CS2A_SMC_SMARTMEDIA    [expr (1 << 3)]
+set            AT91_MATRIX_EBI1_DBPUC          [expr (1 << 8)] ;# Data Bus Pull-up Configuration
+set            AT91_MATRIX_EBI1_VDDIOMSEL      [expr (1 << 16)]        ;# Memory voltage selection
+set                    AT91_MATRIX_EBI1_VDDIOMSEL_1_8V         [expr (0 << 16)]
+set                    AT91_MATRIX_EBI1_VDDIOMSEL_3_3V         [expr (1 << 16)]
+
+

diff --git a/tcl/chip/atmel/at91/at91sam9_init.cfg b/tcl/chip/atmel/at91/at91sam9_init.cfg
index 47d22e0ac0cc1a838072bd34ff71ddf5fd3e34ec..d75d668809f61b0fa994fa9563f397ede5d45b87 100644 (file)
--- a/tcl/chip/atmel/at91/at91sam9_init.cfg
+++ b/tcl/chip/atmel/at91/at91sam9_init.cfg
@@ -54,10 +54,19 @@ proc at91sam9_reset_init { config } {
        set rstc_mr_val [expr ($rstc_mr_val | $::AT91_RSTC_URSTEN)]
        mww $::AT91_RSTC_MR $rstc_mr_val        ;# user reset enable
 
-       set pdr_addr [expr ($::AT91_PIOC + $::PIO_PDR)]
-       mww $pdr_addr 0xffff0000                                ;# define PDC[31:16] as DATA[31:16]
-       set pudr_addr [expr ($::AT91_PIOC + $::PIO_PUDR)]
-       mww $pudr_addr 0xffff0000                               ;# no pull-up for D[31:16]
+       if { [info exists config(sdram_piod) ] } {
+               set pdr_addr    [expr ($::AT91_PIOD + $::PIO_PDR)]
+               set pudr_addr   [expr ($::AT91_PIOD + $::PIO_PUDR)]
+               set asr_addr    [expr ($::AT91_PIOD + $::PIO_ASR)]
+               mww $pdr_addr 0xffff0000                                ;# define PDC[31:16] as DATA[31:16]
+               mww $pudr_addr 0xffff0000                               ;# no pull-up for D[31:16]
+               mww $asr_addr 0xffff0000
+       } else {
+               set pdr_addr    [expr ($::AT91_PIOC + $::PIO_PDR)]
+               set pudr_addr   [expr ($::AT91_PIOC + $::PIO_PUDR)]
+               mww $pdr_addr 0xffff0000                                ;# define PDC[31:16] as DATA[31:16]
+               mww $pudr_addr 0xffff0000                               ;# no pull-up for D[31:16]
+       }
 
        mww $config(matrix_ebicsa_addr) $config(matrix_ebicsa_val)
        mww $::AT91_SDRAMC_MR   $::AT91_SDRAMC_MODE_NORMAL      ;# SDRAMC_MR Mode register