Ferdinand Postema <ferdinand@postema.eu>:

Updates to private TAP state tables in amtjtagaccel interface driver.

The first change is the neccesary one to correct a long-standing bug that
caused the IDCODE to be shifted by one bit too many.  This was caused by
an incorrect path from state RESET to state DRSHIFT.

The value of those 2 bytes were 0x8a and 0x04. This means that the
bitstream to do this transition is 0b 00100 01010 (send LSB first). This
will bring you from the reset state to the shift state; however, you
enter the shift-state twice, which explains why the ID-CODE that will be
read next will be shifted 1 bit.  The fix changes these to 0x05 and 0x00.
This will send the bitstream 0b 00101 (send LSB first).  This will bring
the TAP controller from the RESET state to the DRSHIFT state directly,
without entering the DRSHIFT state twice.

After checking the whole table, two other transitions were found that
could be optimized (5 bits in stead of 10 bits).

Summary off all changes:
  From   To       Old values  Old Bitstream  New values  New Bitstream  Remarks
  ----   -------  ----------  -------------  ----------  -------------  -------
  RESET  DRSHIFT  0x8a 0x04   0b00100 01010  0x05 0x00   0b00101        1,2
  IDLE   DRSHIFT  0x85 0x08   0b01000 00101  0x04 0x00   0b00100        2
  IDLE   IRSHIFT  0x8b 0x08   0b01000 01011  0x06 0x00   0b00110        2

[1] Fixes the IDCODE bug
[2] Optimization

git-svn-id: svn://svn.berlios.de/openocd/trunk@2472 b42882b7-edfa-0310-969c-e2dbd0fdcd60

diff --git a/src/jtag/amt_jtagaccel.c b/src/jtag/amt_jtagaccel.c
index 6c39d88e88053e93a2193bf58b2f0794ef9c0885..c8fcc54f93032191b110a4d62af9166147156dc5 100644 (file)
--- a/src/jtag/amt_jtagaccel.c
+++ b/src/jtag/amt_jtagaccel.c
@@ -92,8 +92,8 @@ static int amt_jtagaccel_handle_rtck_command(struct command_context_s *cmd_ctx,
 static uint8_t amt_jtagaccel_tap_move[6][6][2] =
 {
        /*         RESET         IDLE        DRSHIFT       DRPAUSE       IRSHIFT       IRPAUSE             */
-       {{0x1f, 0x00}, {0x0f, 0x00}, {0x8a, 0x04}, {0x0a, 0x00}, {0x06, 0x00}, {0x96, 0x00}},   /* RESET */
-       {{0x1f, 0x00}, {0x00, 0x00}, {0x85, 0x08}, {0x05, 0x00}, {0x8b, 0x08}, {0x0b, 0x00}},   /* IDLE */
+       {{0x1f, 0x00}, {0x0f, 0x00}, {0x05, 0x00}, {0x0a, 0x00}, {0x06, 0x00}, {0x96, 0x00}},   /* RESET */
+       {{0x1f, 0x00}, {0x00, 0x00}, {0x04, 0x00}, {0x05, 0x00}, {0x06, 0x00}, {0x0b, 0x00}},   /* IDLE */
        {{0x1f, 0x00}, {0x0d, 0x00}, {0x00, 0x00}, {0x01, 0x00}, {0x8f, 0x09}, {0x8f, 0x01}},   /* DRSHIFT  */
        {{0x1f, 0x00}, {0x0c, 0x00}, {0x08, 0x00}, {0x00, 0x00}, {0x8f, 0x09}, {0x8f, 0x01}},   /* DRPAUSE  */
        {{0x1f, 0x00}, {0x0d, 0x00}, {0x07, 0x00}, {0x97, 0x00}, {0x00, 0x00}, {0x01, 0x00}},   /* IRSHIFT  */