--- /dev/null
+/*\r
+ FreeRTOS V8.0.0:rc1 - Copyright (C) 2014 Real Time Engineers Ltd.\r
+ All rights reserved\r
+\r
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS provides completely free yet professionally developed, *\r
+ * robust, strictly quality controlled, supported, and cross *\r
+ * platform software that has become a de facto standard. *\r
+ * *\r
+ * Help yourself get started quickly and support the FreeRTOS *\r
+ * project by purchasing a FreeRTOS tutorial book, reference *\r
+ * manual, or both from: http://www.FreeRTOS.org/Documentation *\r
+ * *\r
+ * Thank you! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
+\r
+ >>! NOTE: The modification to the GPL is included to allow you to distribute\r
+ >>! a combined work that includes FreeRTOS without being obliged to provide\r
+ >>! the source code for proprietary components outside of the FreeRTOS\r
+ >>! kernel.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+ FOR A PARTICULAR PURPOSE. Full license text is available from the following\r
+ link: http://www.freertos.org/a00114.html\r
+\r
+ 1 tab == 4 spaces!\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * Having a problem? Start by reading the FAQ "My application does *\r
+ * not run, what could be wrong?" *\r
+ * *\r
+ * http://www.FreeRTOS.org/FAQHelp.html *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
+ license and Real Time Engineers Ltd. contact details.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
+ Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS\r
+ licenses offer ticketed support, indemnification and middleware.\r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
+ mission critical applications that require provable dependability.\r
+\r
+ 1 tab == 4 spaces!\r
+*/\r
+\r
+/* Standard includes. */\r
+#include <stdlib.h>\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+#ifndef configINTERRUPT_CONTROLLER_BASE_ADDRESS\r
+ #error configINTERRUPT_CONTROLLER_BASE_ADDRESS must be defined. See http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html\r
+#endif\r
+\r
+#ifndef configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET\r
+ #error configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET must be defined. See http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html\r
+#endif\r
+\r
+#ifndef configUNIQUE_INTERRUPT_PRIORITIES\r
+ #error configUNIQUE_INTERRUPT_PRIORITIES must be defined. See http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html\r
+#endif\r
+\r
+#ifndef configSETUP_TICK_INTERRUPT\r
+ #error configSETUP_TICK_INTERRUPT() must be defined. See http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html\r
+#endif /* configSETUP_TICK_INTERRUPT */\r
+\r
+#ifndef configMAX_API_CALL_INTERRUPT_PRIORITY\r
+ #error configMAX_API_CALL_INTERRUPT_PRIORITY must be defined. See http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html\r
+#endif\r
+\r
+#if configMAX_API_CALL_INTERRUPT_PRIORITY == 0\r
+ #error configMAX_API_CALL_INTERRUPT_PRIORITY must not be set to 0\r
+#endif\r
+\r
+#if configMAX_API_CALL_INTERRUPT_PRIORITY > configUNIQUE_INTERRUPT_PRIORITIES\r
+ #error configMAX_API_CALL_INTERRUPT_PRIORITY must be less than or equal to configUNIQUE_INTERRUPT_PRIORITIES as the lower the numeric priority value the higher the logical interrupt priority\r
+#endif\r
+\r
+#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1\r
+ /* Check the configuration. */\r
+ #if( configMAX_PRIORITIES > 32 )\r
+ #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.\r
+ #endif\r
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */\r
+\r
+/* In case security extensions are implemented. */\r
+#if configMAX_API_CALL_INTERRUPT_PRIORITY <= ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )\r
+ #error configMAX_API_CALL_INTERRUPT_PRIORITY must be greater than ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )\r
+#endif\r
+\r
+/* A critical section is exited when the critical section nesting count reaches\r
+this value. */\r
+#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 )\r
+\r
+/* In all GICs 255 can be written to the priority mask register to unmask all\r
+(but the lowest) interrupt priority. */\r
+#define portUNMASK_VALUE ( 0xFF )\r
+\r
+/* Tasks are not created with a floating point context, but can be given a\r
+floating point context after they have been created. A variable is stored as\r
+part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task\r
+does not have an FPU context, or any other value if the task does have an FPU\r
+context. */\r
+#define portNO_FLOATING_POINT_CONTEXT ( ( StackType_t ) 0 )\r
+\r
+/* Constants required to setup the initial task context. */\r
+#define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */\r
+#define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 )\r
+#define portINTERRUPT_ENABLE_BIT ( 0x80UL )\r
+#define portTHUMB_MODE_ADDRESS ( 0x01UL )\r
+\r
+/* Used by portASSERT_IF_INTERRUPT_PRIORITY_INVALID() when ensuring the binary\r
+point is zero. */\r
+#define portBINARY_POINT_BITS ( ( uint8_t ) 0x03 )\r
+\r
+/* Masks all bits in the APSR other than the mode bits. */\r
+#define portAPSR_MODE_BITS_MASK ( 0x1F )\r
+\r
+/* The value of the mode bits in the APSR when the CPU is executing in user\r
+mode. */\r
+#define portAPSR_USER_MODE ( 0x10 )\r
+\r
+/* Macro to unmask all interrupt priorities. */\r
+#define portCLEAR_INTERRUPT_MASK() \\r
+{ \\r
+ __asm volatile ( "cpsid i" ); \\r
+ portICCPMR_PRIORITY_MASK_REGISTER = portUNMASK_VALUE; \\r
+ __asm( "DSB \n" \\r
+ "ISB \n" ); \\r
+ __asm volatile( "cpsie i" ); \\r
+}\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Starts the first task executing. This function is necessarily written in\r
+ * assembly code so is implemented in portASM.s.\r
+ */\r
+extern void vPortRestoreTaskContext( void );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* A variable is used to keep track of the critical section nesting. This\r
+variable has to be stored as part of the task context and must be initialised to\r
+a non zero value to ensure interrupts don't inadvertently become unmasked before\r
+the scheduler starts. As it is stored as part of the task context it will\r
+automatically be set to 0 when the first task is started. */\r
+volatile uint32_t ulCriticalNesting = 9999UL;\r
+\r
+/* Saved as part of the task context. If ulPortTaskHasFPUContext is non-zero then\r
+a floating point context must be saved and restored for the task. */\r
+uint32_t ulPortTaskHasFPUContext = pdFALSE;\r
+\r
+/* Set to 1 to pend a context switch from an ISR. */\r
+uint32_t ulPortYieldRequired = pdFALSE;\r
+\r
+/* Counts the interrupt nesting depth. A context switch is only performed if\r
+if the nesting depth is 0. */\r
+uint32_t ulPortInterruptNesting = 0UL;\r
+\r
+__attribute__(( used )) const uint32_t ulICCIAR = portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS;\r
+__attribute__(( used )) const uint32_t ulICCEOIR = portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * See header file for description.\r
+ */\r
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )\r
+{\r
+ /* Setup the initial stack of the task. The stack is set exactly as\r
+ expected by the portRESTORE_CONTEXT() macro.\r
+\r
+ The fist real value on the stack is the status register, which is set for\r
+ system mode, with interrupts enabled. A few NULLs are added first to ensure\r
+ GDB does not try decoding a non-existent return address. */\r
+ *pxTopOfStack = ( StackType_t ) NULL;\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) NULL;\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) NULL;\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;\r
+\r
+ if( ( ( uint32_t ) pxCode & portTHUMB_MODE_ADDRESS ) != 0x00UL )\r
+ {\r
+ /* The task will start in THUMB mode. */\r
+ *pxTopOfStack |= portTHUMB_MODE_BIT;\r
+ }\r
+\r
+ pxTopOfStack--;\r
+\r
+ /* Next the return address, which in this case is the start of the task. */\r
+ *pxTopOfStack = ( StackType_t ) pxCode;\r
+ pxTopOfStack--;\r
+\r
+ /* Next all the registers other than the stack pointer. */\r
+ *pxTopOfStack = ( StackType_t ) 0x00000000; /* R14 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */\r
+ pxTopOfStack--;\r
+\r
+ /* The task will start with a critical nesting count of 0 as interrupts are\r
+ enabled. */\r
+ *pxTopOfStack = portNO_CRITICAL_NESTING;\r
+ pxTopOfStack--;\r
+\r
+ /* The task will start without a floating point context. A task that uses\r
+ the floating point hardware must call vPortTaskUsesFPU() before executing\r
+ any floating point instructions. */\r
+ *pxTopOfStack = portNO_FLOATING_POINT_CONTEXT;\r
+\r
+ return pxTopOfStack;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+BaseType_t xPortStartScheduler( void )\r
+{\r
+uint32_t ulAPSR;\r
+\r
+ /* Only continue if the CPU is not in User mode. The CPU must be in a\r
+ Privileged mode for the scheduler to start. */\r
+ __asm volatile ( "MRS %0, APSR" : "=r" ( ulAPSR ) );\r
+ ulAPSR &= portAPSR_MODE_BITS_MASK;\r
+ configASSERT( ulAPSR != portAPSR_USER_MODE );\r
+\r
+ if( ulAPSR != portAPSR_USER_MODE )\r
+ {\r
+ /* Only continue if the binary point value is set to its lowest possible\r
+ setting. See the comments in vPortValidateInterruptPriority() below for\r
+ more information. */\r
+ configASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE );\r
+\r
+ if( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE )\r
+ {\r
+ /* Start the timer that generates the tick ISR. */\r
+ configSETUP_TICK_INTERRUPT();\r
+\r
+ __asm volatile( "cpsie i" );\r
+ vPortRestoreTaskContext();\r
+ }\r
+ }\r
+\r
+ /* Will only get here if xTaskStartScheduler() was called with the CPU in\r
+ a non-privileged mode or the binary point register was not set to its lowest\r
+ possible value. */\r
+ return 0;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortEndScheduler( void )\r
+{\r
+ /* Not implemented in ports where there is nothing to return to.\r
+ Artificially force an assert. */\r
+ configASSERT( ulCriticalNesting == 1000UL );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortEnterCritical( void )\r
+{\r
+ /* Disable interrupts as per portDISABLE_INTERRUPTS(); */\r
+ ulPortSetInterruptMask();\r
+\r
+ /* Now interrupts are disabled ulCriticalNesting can be accessed\r
+ directly. Increment ulCriticalNesting to keep a count of how many times\r
+ portENTER_CRITICAL() has been called. */\r
+ ulCriticalNesting++;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortExitCritical( void )\r
+{\r
+ if( ulCriticalNesting > portNO_CRITICAL_NESTING )\r
+ {\r
+ /* Decrement the nesting count as the critical section is being\r
+ exited. */\r
+ ulCriticalNesting--;\r
+\r
+ /* If the nesting level has reached zero then all interrupt\r
+ priorities must be re-enabled. */\r
+ if( ulCriticalNesting == portNO_CRITICAL_NESTING )\r
+ {\r
+ /* Critical nesting has reached zero so all interrupt priorities\r
+ should be unmasked. */\r
+ portCLEAR_INTERRUPT_MASK();\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void FreeRTOS_Tick_Handler( void )\r
+{\r
+ /* Set interrupt mask before altering scheduler structures. The tick\r
+ handler runs at the lowest priority, so interrupts cannot already be masked,\r
+ so there is no need to save and restore the current mask value. */\r
+ __asm volatile( "cpsid i" );\r
+ portICCPMR_PRIORITY_MASK_REGISTER = ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );\r
+ __asm( "dsb \n"\r
+ "isb \n"\r
+ "cpsie i ");\r
+\r
+ /* Increment the RTOS tick. */\r
+ if( xTaskIncrementTick() != pdFALSE )\r
+ {\r
+ ulPortYieldRequired = pdTRUE;\r
+ }\r
+\r
+ /* Ensure all interrupt priorities are active again. */\r
+ portCLEAR_INTERRUPT_MASK();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortTaskUsesFPU( void )\r
+{\r
+uint32_t ulInitialFPSCR = 0;\r
+\r
+ /* A task is registering the fact that it needs an FPU context. Set the\r
+ FPU flag (which is saved as part of the task context). */\r
+ ulPortTaskHasFPUContext = pdTRUE;\r
+\r
+ /* Initialise the floating point status register. */\r
+ __asm( "FMXR FPSCR, %0" :: "r" (ulInitialFPSCR) );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortClearInterruptMask( uint32_t ulNewMaskValue )\r
+{\r
+ if( ulNewMaskValue == pdFALSE )\r
+ {\r
+ portCLEAR_INTERRUPT_MASK();\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+uint32_t ulPortSetInterruptMask( void )\r
+{\r
+uint32_t ulReturn;\r
+\r
+ __asm volatile ( "cpsid i" );\r
+ if( portICCPMR_PRIORITY_MASK_REGISTER == ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) )\r
+ {\r
+ /* Interrupts were already masked. */\r
+ ulReturn = pdTRUE;\r
+ }\r
+ else\r
+ {\r
+ ulReturn = pdFALSE;\r
+ portICCPMR_PRIORITY_MASK_REGISTER = ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );\r
+ __asm( "dsb \n"\r
+ "isb \n" );\r
+ }\r
+ __asm volatile ( "cpsie i" );\r
+\r
+ return ulReturn;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+#if( configASSERT_DEFINED == 1 )\r
+\r
+ void vPortValidateInterruptPriority( void )\r
+ {\r
+ /* The following assertion will fail if a service routine (ISR) for\r
+ an interrupt that has been assigned a priority above\r
+ configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API\r
+ function. ISR safe FreeRTOS API functions must *only* be called\r
+ from interrupts that have been assigned a priority at or below\r
+ configMAX_SYSCALL_INTERRUPT_PRIORITY.\r
+\r
+ Numerically low interrupt priority numbers represent logically high\r
+ interrupt priorities, therefore the priority of the interrupt must\r
+ be set to a value equal to or numerically *higher* than\r
+ configMAX_SYSCALL_INTERRUPT_PRIORITY.\r
+\r
+ FreeRTOS maintains separate thread and ISR API functions to ensure\r
+ interrupt entry is as fast and simple as possible.\r
+\r
+ The following links provide detailed information:\r
+ http://www.freertos.org/RTOS-Cortex-M3-M4.html\r
+ http://www.freertos.org/FAQHelp.html */\r
+ configASSERT( portICCRPR_RUNNING_PRIORITY_REGISTER >= ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) );\r
+\r
+ /* Priority grouping: The interrupt controller (GIC) allows the bits\r
+ that define each interrupt's priority to be split between bits that\r
+ define the interrupt's pre-emption priority bits and bits that define\r
+ the interrupt's sub-priority. For simplicity all bits must be defined\r
+ to be pre-emption priority bits. The following assertion will fail if\r
+ this is not the case (if some bits represent a sub-priority).\r
+\r
+ The priority grouping is configured by the GIC's binary point register\r
+ (ICCBPR). Writting 0 to ICCBPR will ensure it is set to its lowest\r
+ possible value (which may be above 0). */\r
+ configASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE );\r
+ }\r
+\r
+#endif /* configASSERT_DEFINED */\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortRestoreTaskContext( void )\r
+{\r
+}\r
+\r
+void vPortRestoreContext( void )\r
+{\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V8.0.0:rc1 - Copyright (C) 2014 Real Time Engineers Ltd.\r
+ All rights reserved\r
+\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS tutorial books are available in pdf and paperback. *\r
+ * Complete, revised, and edited pdf reference manuals are also *\r
+ * available. *\r
+ * *\r
+ * Purchasing FreeRTOS documentation will not only help you, by *\r
+ * ensuring you get running as quickly as possible and with an *\r
+ * in-depth knowledge of how to use FreeRTOS, it will also help *\r
+ * the FreeRTOS project to continue with its mission of providing *\r
+ * professional grade, cross platform, de facto standard solutions *\r
+ * for microcontrollers - completely free of charge! *\r
+ * *\r
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
+ * *\r
+ * Thank you for using FreeRTOS, and thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+ >>>NOTE<<< The modification to the GPL is included to allow you to\r
+ distribute a combined work that includes FreeRTOS without being obliged to\r
+ provide the source code for proprietary components outside of the FreeRTOS\r
+ kernel. FreeRTOS is distributed in the hope that it will be useful, but\r
+ WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ more details. You should have received a copy of the GNU General Public\r
+ License and the FreeRTOS license exception along with FreeRTOS; if not it\r
+ can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
+ by writing to Richard Barry, contact details for whom are available on the\r
+ FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+\r
+ http://www.FreeRTOS.org - Documentation, latest information, license and\r
+ contact details.\r
+\r
+ http://www.SafeRTOS.com - A version that is certified for use in safety\r
+ critical systems.\r
+\r
+ http://www.OpenRTOS.com - Commercial support, development, porting,\r
+ licensing and training services.\r
+*/\r
+\r
+\r
+ .org 0\r
+ .text\r
+\r
+ .set SYS_MODE, 0x1f\r
+ .set SVC_MODE, 0x13\r
+ .set IRQ_MODE, 0x12\r
+\r
+ .extern _boot\r
+ .extern vTaskSwitchContext\r
+ .extern ulICCIAR\r
+ .extern ulICCEOIR\r
+\r
+ .global _vector_table\r
+ .global FIQInterrupt\r
+ .global Undefined\r
+ .global PrefetchAbortHandler\r
+ .global DataAbortInterrupt\r
+ .global FreeRTOS_IRQ_Handler\r
+ .global FreeRTOS_SWI_Handler\r
+\r
+ .section .vectors\r
+\r
+_vector_table:\r
+ B _boot\r
+ B Undefined\r
+ ldr pc, _swi\r
+ B PrefetchAbortHandler\r
+ B DataAbortHandler\r
+ NOP /* Placeholder for address exception vector*/\r
+ LDR PC, _irq\r
+ B FIQHandler\r
+\r
+_irq: .word FreeRTOS_IRQ_Handler\r
+_swi: .word FreeRTOS_SWI_Handler\r
+\r
+/******************************************************************************\r
+ * SVC handler is used to start the scheduler and yield a task.\r
+ *****************************************************************************/\r
+FreeRTOS_SWI_Handler:\r
+\r
+ /* Save the context of the current task and select a new task to run. */\r
+// portSAVE_CONTEXT\r
+ LDR R0, =vTaskSwitchContext\r
+ BLX R0\r
+\r
+vPortRestoreTaskContext:\r
+// portRESTORE_CONTEXT\r
+\r
+FreeRTOS_IRQ_Handler:\r
+ /* Return to the interrupted instruction. */\r
+ SUB lr, lr, #4\r
+\r
+ /* Push the return address and SPSR. */\r
+ PUSH {lr}\r
+ MRS lr, SPSR\r
+ PUSH {lr}\r
+\r
+ /* Change to supervisor mode to allow reentry. */\r
+ CPS #SVC_MODE\r
+\r
+ /* Push used registers. */\r
+ PUSH {r0-r4, r12}\r
+\r
+ /* Increment nesting count. r3 holds the address of ulPortInterruptNesting\r
+ for future use. r1 holds the original ulPortInterruptNesting value for\r
+ future use. */\r
+ LDR r3, =ulPortInterruptNesting\r
+ LDR r1, [r3]\r
+ ADD r4, r1, #1\r
+ STR r4, [r3]\r
+\r
+ /* Read value from the interrupt acknowledge register, which is stored in r0\r
+ for future parameter and interrupt clearing use. */\r
+ LDR r2, ulICCIARConst\r
+ LDR r0, [r2]\r
+\r
+ /* Ensure bit 2 of the stack pointer is clear. r2 holds the bit 2 value for\r
+ future use. */\r
+ MOV r2, sp\r
+ AND r2, r2, #4\r
+ SUB sp, sp, r2\r
+\r
+ /* Call the interrupt handler. */\r
+ PUSH {r0-r3, lr}\r
+ BL vApplicationIRQHandler\r
+ POP {r0-r3, lr}\r
+ ADD sp, sp, r2\r
+\r
+ CPSID i\r
+\r
+ /* Write the value read from ICCIAR to ICCEOIR. */\r
+ LDR r4, ulICCEOIRConst\r
+ STR r0, [r4]\r
+\r
+ /* Restore the old nesting count. */\r
+ STR r1, [r3]\r
+\r
+ /* A context switch is never performed if the nesting count is not 0. */\r
+ CMP r1, #0\r
+ BNE exit_without_switch\r
+\r
+ /* Did the interrupt request a context switch? r1 holds the address of\r
+ ulPortYieldRequired and r0 the value of ulPortYieldRequired for future\r
+ use. */\r
+ LDR r1, =ulPortYieldRequired\r
+ LDR r0, [r1]\r
+ CMP r0, #0\r
+ BNE switch_before_exit\r
+\r
+exit_without_switch:\r
+ /* No context switch. Restore used registers, LR_irq and SPSR before\r
+ returning. */\r
+ POP {r0-r4, r12}\r
+ CPS #IRQ_MODE\r
+ POP {LR}\r
+ MSR SPSR_cxsf, LR\r
+ POP {LR}\r
+ MOVS PC, LR\r
+\r
+switch_before_exit:\r
+ /* A context swtich is to be performed. Clear the context switch pending\r
+ flag. */\r
+ MOV r0, #0\r
+ STR r0, [r1]\r
+\r
+ /* Restore used registers, LR-irq and SPSR before saving the context\r
+ to the task stack. */\r
+ POP {r0-r4, r12}\r
+ CPS #IRQ_MODE\r
+ POP {LR}\r
+ MSR SPSR_cxsf, LR\r
+ POP {LR}\r
+// portSAVE_CONTEXT\r
+\r
+ /* Call the function that selects the new task to execute.\r
+ vTaskSwitchContext() if vTaskSwitchContext() uses LDRD or STRD\r
+ instructions, or 8 byte aligned stack allocated data. LR does not need\r
+ saving as a new LR will be loaded by portRESTORE_CONTEXT anyway. */\r
+ BL vTaskSwitchContext\r
+\r
+ /* Restore the context of, and branch to, the task selected to execute\r
+ next. */\r
+// portRESTORE_CONTEXT\r
+\r
+ulICCIARConst: .word ulICCIAR\r
+ulICCEOIRConst: .word ulICCEOIR\r
+\r
+\r
+Undefined:\r
+ B .\r
+\r
+PrefetchAbortHandler:\r
+ B .\r
+\r
+FIQHandler:\r
+ B .\r
+\r
+DataAbortHandler:\r
+ B .\r
+\r
+.end\r
+\r
+\r
+\r
+\r
+\r
--- /dev/null
+;/*\r
+; FreeRTOS V8.0.0:rc1 - Copyright (C) 2014 Real Time Engineers Ltd.\r
+; All rights reserved\r
+;\r
+;\r
+; ***************************************************************************\r
+; * *\r
+; * FreeRTOS tutorial books are available in pdf and paperback. *\r
+; * Complete, revised, and edited pdf reference manuals are also *\r
+; * available. *\r
+; * *\r
+; * Purchasing FreeRTOS documentation will not only help you, by *\r
+; * ensuring you get running as quickly as possible and with an *\r
+; * in-depth knowledge of how to use FreeRTOS, it will also help *\r
+; * the FreeRTOS project to continue with its mission of providing *\r
+; * professional grade, cross platform, de facto standard solutions *\r
+; * for microcontrollers - completely free of charge! *\r
+; * *\r
+; * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
+; * *\r
+; * Thank you for using FreeRTOS, and thank you for your support! *\r
+; * *\r
+; ***************************************************************************\r
+;\r
+;\r
+; This file is part of the FreeRTOS distribution.\r
+;\r
+; FreeRTOS is free software; you can redistribute it and/or modify it under\r
+; the terms of the GNU General Public License (version 2) as published by the\r
+; Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+; >>>NOTE<<< The modification to the GPL is included to allow you to\r
+; distribute a combined work that includes FreeRTOS without being obliged to\r
+; provide the source code for proprietary components outside of the FreeRTOS\r
+; kernel. FreeRTOS is distributed in the hope that it will be useful, but\r
+; WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+; more details. You should have received a copy of the GNU General Public\r
+; License and the FreeRTOS license exception along with FreeRTOS; if not it\r
+; can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
+; by writing to Richard Barry, contact details for whom are available on the\r
+; FreeRTOS WEB site.\r
+;\r
+; 1 tab == 4 spaces!\r
+;\r
+; http://www.FreeRTOS.org - Documentation, latest information, license and\r
+; contact details.\r
+;\r
+; http://www.SafeRTOS.com - A version that is certified for use in safety\r
+; critical systems.\r
+;\r
+; http://www.OpenRTOS.com - Commercial support, development, porting,\r
+; licensing and training services.\r
+;*/\r
+\r
+ EXTERN vTaskSwitchContext\r
+ EXTERN ulCriticalNesting\r
+ EXTERN pxCurrentTCB\r
+ EXTERN ulPortTaskHasFPUContext\r
+ EXTERN ulAsmAPIPriorityMask\r
+\r
+portSAVE_CONTEXT macro\r
+\r
+ ; Save the LR and SPSR onto the system mode stack before switching to\r
+ ; system mode to save the remaining system mode registers\r
+ SRSDB sp!, #SYS_MODE\r
+ CPS #SYS_MODE\r
+ PUSH {R0-R12, R14}\r
+\r
+ ; Push the critical nesting count\r
+ LDR R2, =ulCriticalNesting\r
+ LDR R1, [R2]\r
+ PUSH {R1}\r
+\r
+ ; Does the task have a floating point context that needs saving? If\r
+ ; ulPortTaskHasFPUContext is 0 then no.\r
+ LDR R2, =ulPortTaskHasFPUContext\r
+ LDR R3, [R2]\r
+ CMP R3, #0\r
+\r
+ ; Save the floating point context, if any\r
+ FMRXNE R1, FPSCR\r
+ VPUSHNE {D0-D15}\r
+ VPUSHNE {D16-D31}\r
+ PUSHNE {R1}\r
+\r
+ ; Save ulPortTaskHasFPUContext itself\r
+ PUSH {R3}\r
+\r
+ ; Save the stack pointer in the TCB\r
+ LDR R0, =pxCurrentTCB\r
+ LDR R1, [R0]\r
+ STR SP, [R1]\r
+\r
+ endm\r
+\r
+; /**********************************************************************/\r
+\r
+portRESTORE_CONTEXT macro\r
+\r
+ ; Switch to system mode\r
+ CPS #SYS_MODE\r
+\r
+ ; Set the SP to point to the stack of the task being restored.\r
+ LDR R0, =pxCurrentTCB\r
+ LDR R1, [R0]\r
+ LDR SP, [R1]\r
+\r
+ ; Is there a floating point context to restore? If the restored\r
+ ; ulPortTaskHasFPUContext is zero then no.\r
+ LDR R0, =ulPortTaskHasFPUContext\r
+ POP {R1}\r
+ STR R1, [R0]\r
+ CMP R1, #0\r
+\r
+ ; Restore the floating point context, if any\r
+ LDMFDNE SP!, {R0}\r
+ VPOPNE {D16-D31}\r
+ VPOPNE {D0-D15}\r
+ VMSRNE FPSCR, R0\r
+\r
+ ; Restore the critical section nesting depth\r
+ LDR R0, =ulCriticalNesting\r
+ POP {R1}\r
+ STR R1, [R0]\r
+\r
+ ; Ensure the priority mask is correct for the critical nesting depth\r
+ LDR R2, =portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS\r
+ CMP R1, #0\r
+ MOVEQ R4, #255\r
+ LDRNE R4, =( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT )\r
+ STR R4, [r2]\r
+\r
+ ; Restore all system mode registers other than the SP (which is already\r
+ ; being used)\r
+ POP {R0-R12, R14}\r
+\r
+ ; Return to the task code, loading CPSR on the way.\r
+ RFEIA sp!\r
+\r
+ endm\r
+\r
+\r
+\r
+\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V8.0.0:rc1 - Copyright (C) 2014 Real Time Engineers Ltd.\r
+ All rights reserved\r
+\r
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS provides completely free yet professionally developed, *\r
+ * robust, strictly quality controlled, supported, and cross *\r
+ * platform software that has become a de facto standard. *\r
+ * *\r
+ * Help yourself get started quickly and support the FreeRTOS *\r
+ * project by purchasing a FreeRTOS tutorial book, reference *\r
+ * manual, or both from: http://www.FreeRTOS.org/Documentation *\r
+ * *\r
+ * Thank you! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
+\r
+ >>! NOTE: The modification to the GPL is included to allow you to distribute\r
+ >>! a combined work that includes FreeRTOS without being obliged to provide\r
+ >>! the source code for proprietary components outside of the FreeRTOS\r
+ >>! kernel.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+ FOR A PARTICULAR PURPOSE. Full license text is available from the following\r
+ link: http://www.freertos.org/a00114.html\r
+\r
+ 1 tab == 4 spaces!\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * Having a problem? Start by reading the FAQ "My application does *\r
+ * not run, what could be wrong?" *\r
+ * *\r
+ * http://www.FreeRTOS.org/FAQHelp.html *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
+ license and Real Time Engineers Ltd. contact details.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
+ Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS\r
+ licenses offer ticketed support, indemnification and middleware.\r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
+ mission critical applications that require provable dependability.\r
+\r
+ 1 tab == 4 spaces!\r
+*/\r
+\r
+#ifndef PORTMACRO_H\r
+#define PORTMACRO_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/*-----------------------------------------------------------\r
+ * Port specific definitions.\r
+ *\r
+ * The settings in this file configure FreeRTOS correctly for the given hardware\r
+ * and compiler.\r
+ *\r
+ * These settings should not be altered.\r
+ *-----------------------------------------------------------\r
+ */\r
+\r
+/* Type definitions. */\r
+#define portCHAR char\r
+#define portFLOAT float\r
+#define portDOUBLE double\r
+#define portLONG long\r
+#define portSHORT short\r
+#define portSTACK_TYPE uint32_t\r
+#define portBASE_TYPE long\r
+\r
+typedef portSTACK_TYPE StackType_t;\r
+typedef long BaseType_t;\r
+typedef unsigned long UBaseType_t;\r
+\r
+typedef uint32_t TickType_t;\r
+#define portMAX_DELAY ( TickType_t ) 0xffffffffUL\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Hardware specifics. */\r
+#define portSTACK_GROWTH ( -1 )\r
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )\r
+#define portBYTE_ALIGNMENT 8\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Task utilities. */\r
+\r
+/* Called at the end of an ISR that can cause a context switch. */\r
+#define portEND_SWITCHING_ISR( xSwitchRequired )\\r
+{ \\r
+extern uint32_t ulPortYieldRequired; \\r
+ \\r
+ if( xSwitchRequired != pdFALSE ) \\r
+ { \\r
+ ulPortYieldRequired = pdTRUE; \\r
+ } \\r
+}\r
+\r
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )\r
+#define portYIELD() __asm( "SWI 0" );\r
+\r
+\r
+/*-----------------------------------------------------------\r
+ * Critical section control\r
+ *----------------------------------------------------------*/\r
+\r
+extern void vPortEnterCritical( void );\r
+extern void vPortExitCritical( void );\r
+extern uint32_t ulPortSetInterruptMask( void );\r
+extern void vPortClearInterruptMask( uint32_t ulNewMaskValue );\r
+\r
+/* These macros do not globally disable/enable interrupts. They do mask off\r
+interrupts that have a priority below configMAX_API_CALL_INTERRUPT_PRIORITY. */\r
+#define portENTER_CRITICAL() vPortEnterCritical();\r
+#define portEXIT_CRITICAL() vPortExitCritical();\r
+#define portDISABLE_INTERRUPTS() ulPortSetInterruptMask()\r
+#define portENABLE_INTERRUPTS() vPortClearInterruptMask( 0 )\r
+#define portSET_INTERRUPT_MASK_FROM_ISR() ulPortSetInterruptMask()\r
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vPortClearInterruptMask(x)\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Task function macros as described on the FreeRTOS.org WEB site. These are\r
+not required for this port but included in case common demo code that uses these\r
+macros is used. */\r
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )\r
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )\r
+\r
+/* Prototype of the FreeRTOS tick handler. This must be installed as the\r
+handler for whichever peripheral is used to generate the RTOS tick. */\r
+void FreeRTOS_Tick_Handler( void );\r
+\r
+/* Any task that uses the floating point unit MUST call vPortTaskUsesFPU()\r
+before any floating point instructions are executed. */\r
+void vPortTaskUsesFPU( void );\r
+#define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU()\r
+\r
+#define portLOWEST_INTERRUPT_PRIORITY ( ( ( uint32_t ) configUNIQUE_INTERRUPT_PRIORITIES ) - 1UL )\r
+#define portLOWEST_USABLE_INTERRUPT_PRIORITY ( portLOWEST_INTERRUPT_PRIORITY - 1UL )\r
+\r
+/* Architecture specific optimisations. */\r
+#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1\r
+\r
+ /* Store/clear the ready priorities in a bit map. */\r
+ #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )\r
+ #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )\r
+\r
+ /*-----------------------------------------------------------*/\r
+\r
+ #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31 - __builtin_clz( uxReadyPriorities ) )\r
+\r
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */\r
+\r
+#ifdef configASSERT\r
+ void vPortValidateInterruptPriority( void );\r
+ #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority()\r
+#endif /* configASSERT */\r
+\r
+#define portNOP() __asm volatile( "NOP" )\r
+\r
+\r
+#ifdef __cplusplus\r
+ } /* extern C */\r
+#endif\r
+\r
+\r
+/* The number of bits to shift for an interrupt priority is dependent on the\r
+number of bits implemented by the interrupt controller. */\r
+#if configUNIQUE_INTERRUPT_PRIORITIES == 16\r
+ #define portPRIORITY_SHIFT 4\r
+ #define portMAX_BINARY_POINT_VALUE 3\r
+#elif configUNIQUE_INTERRUPT_PRIORITIES == 32\r
+ #define portPRIORITY_SHIFT 3\r
+ #define portMAX_BINARY_POINT_VALUE 2\r
+#elif configUNIQUE_INTERRUPT_PRIORITIES == 64\r
+ #define portPRIORITY_SHIFT 2\r
+ #define portMAX_BINARY_POINT_VALUE 1\r
+#elif configUNIQUE_INTERRUPT_PRIORITIES == 128\r
+ #define portPRIORITY_SHIFT 1\r
+ #define portMAX_BINARY_POINT_VALUE 0\r
+#elif configUNIQUE_INTERRUPT_PRIORITIES == 256\r
+ #define portPRIORITY_SHIFT 0\r
+ #define portMAX_BINARY_POINT_VALUE 0\r
+#else\r
+ #error Invalid configUNIQUE_INTERRUPT_PRIORITIES setting. configUNIQUE_INTERRUPT_PRIORITIES must be set to the number of unique priorities implemented by the target hardware\r
+#endif\r
+\r
+/* Interrupt controller access addresses. */\r
+#define portICCPMR_PRIORITY_MASK_OFFSET ( 0x04 )\r
+#define portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET ( 0x0C )\r
+#define portICCEOIR_END_OF_INTERRUPT_OFFSET ( 0x10 )\r
+#define portICCBPR_BINARY_POINT_OFFSET ( 0x08 )\r
+#define portICCRPR_RUNNING_PRIORITY_OFFSET ( 0x14 )\r
+\r
+#define portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS ( configINTERRUPT_CONTROLLER_BASE_ADDRESS + configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET )\r
+#define portICCPMR_PRIORITY_MASK_REGISTER ( *( ( volatile uint8_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET ) ) )\r
+#define portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET )\r
+#define portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCEOIR_END_OF_INTERRUPT_OFFSET )\r
+#define portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET )\r
+#define portICCBPR_BINARY_POINT_REGISTER ( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCBPR_BINARY_POINT_OFFSET ) ) )\r
+#define portICCRPR_RUNNING_PRIORITY_REGISTER ( *( ( const volatile uint8_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCRPR_RUNNING_PRIORITY_OFFSET ) ) )\r
+\r
+#endif /* PORTMACRO_H */\r
+\r
projects / freertos / commitdiff