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+"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX62N_Renesas\RTOSDemo\RTOSDemo.c" \r
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+"" \r
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+"" 0 0 "" 0 "" 0 0 "" 0 0 0 0 0 0 0 "" "" "" "" "" \r
+[BREAKPOINTS]\r
+[END]\r
--- /dev/null
+/*\r
+ FreeRTOS V6.0.5 - Copyright (C) 2010 Real Time Engineers Ltd.\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * If you are: *\r
+ * *\r
+ * + New to FreeRTOS, *\r
+ * + Wanting to learn FreeRTOS or multitasking in general quickly *\r
+ * + Looking for basic training, *\r
+ * + Wanting to improve your FreeRTOS skills and productivity *\r
+ * *\r
+ * then take a look at the FreeRTOS eBook *\r
+ * *\r
+ * "Using the FreeRTOS Real Time Kernel - a Practical Guide" *\r
+ * http://www.FreeRTOS.org/Documentation *\r
+ * *\r
+ * A pdf reference manual is also available. Both are usually delivered *\r
+ * to your inbox within 20 minutes to two hours when purchased between 8am *\r
+ * and 8pm GMT (although please allow up to 24 hours in case of *\r
+ * exceptional circumstances). Thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+ ***NOTE*** The exception to the GPL is included to allow you to distribute\r
+ a combined work that includes FreeRTOS without being obliged to provide the\r
+ source code for proprietary components outside of the FreeRTOS kernel.\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT\r
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\r
+ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ more details. You should have received a copy of the GNU General Public \r
+ License and the FreeRTOS license exception along with FreeRTOS; if not it \r
+ can be viewed here: http://www.freertos.org/a00114.html and also obtained \r
+ by writing to Richard Barry, contact details for whom are available on the\r
+ FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+\r
+ http://www.FreeRTOS.org - Documentation, latest information, license and\r
+ contact details.\r
+\r
+ http://www.SafeRTOS.com - A version that is certified for use in safety\r
+ critical systems.\r
+\r
+ http://www.OpenRTOS.com - Commercial support, development, porting,\r
+ licensing and training services.\r
+*/\r
+\r
+#ifndef FREERTOS_CONFIG_H\r
+#define FREERTOS_CONFIG_H\r
+\r
+/* Board specifics. */\r
+#include "yrdkrx62ndef.h"\r
+\r
+/*-----------------------------------------------------------\r
+ * Application specific definitions.\r
+ *\r
+ * These definitions should be adjusted for your particular hardware and\r
+ * application requirements.\r
+ *\r
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE\r
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.\r
+ *\r
+ * See http://www.freertos.org/a00110.html.\r
+ *----------------------------------------------------------*/\r
+\r
+#define configUSE_PREEMPTION 1\r
+#define configUSE_IDLE_HOOK 0\r
+#define configUSE_TICK_HOOK 0\r
+#define configCPU_CLOCK_HZ ( ICLK_FREQUENCY ) /* Set in rskrx62ndef.h. */\r
+#define configPERIPHERAL_CLOCK_HZ ( PCLK_FREQUENCY ) /* Set in rskrx62ndef.h. */\r
+#define configTICK_RATE_HZ ( ( portTickType ) 1000 )\r
+#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 140 )\r
+#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 45 * 1024 ) )\r
+#define configMAX_TASK_NAME_LEN ( 12 )\r
+#define configUSE_TRACE_FACILITY 1\r
+#define configUSE_16_BIT_TICKS 0\r
+#define configIDLE_SHOULD_YIELD 1\r
+#define configUSE_CO_ROUTINES 0\r
+#define configUSE_MUTEXES 1\r
+#define configGENERATE_RUN_TIME_STATS 0\r
+#define configCHECK_FOR_STACK_OVERFLOW 2\r
+#define configUSE_RECURSIVE_MUTEXES 1\r
+#define configQUEUE_REGISTRY_SIZE 0\r
+#define configUSE_MALLOC_FAILED_HOOK 1\r
+#define configUSE_APPLICATION_TASK_TAG 0\r
+\r
+#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 5 )\r
+#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )\r
+\r
+/* The interrupt priority used by the kernel itself for the tick interrupt and\r
+the pended interrupt. This would normally be the lowest priority. */\r
+#define configKERNEL_INTERRUPT_PRIORITY 1\r
+\r
+/* The maximum interrupt priority from which FreeRTOS API calls can be made.\r
+Interrupts that use a priority above this will not be effected by anything the\r
+kernel is doing. */\r
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY 4\r
+\r
+/* The peripheral used to generate the tick interrupt is configured as part of\r
+the application code. This constant should be set to the vector number of the\r
+peripheral chosen. As supplied this is CMT0. */\r
+#define configTICK_VECTOR _CMT0_CMI0\r
+\r
+/* Set the following definitions to 1 to include the API function, or zero\r
+to exclude the API function. */\r
+\r
+#define INCLUDE_vTaskPrioritySet 1\r
+#define INCLUDE_uxTaskPriorityGet 1\r
+#define INCLUDE_vTaskDelete 1\r
+#define INCLUDE_vTaskCleanUpResources 0\r
+#define INCLUDE_vTaskSuspend 1\r
+#define INCLUDE_vTaskDelayUntil 1\r
+#define INCLUDE_vTaskDelay 1\r
+#define INCLUDE_uxTaskGetStackHighWaterMark 1\r
+#define INCLUDE_xTaskGetSchedulerState 1\r
+\r
+\r
+\r
+/*-----------------------------------------------------------\r
+ * Ethernet configuration.\r
+ *-----------------------------------------------------------*/\r
+\r
+/* MAC address configuration. */\r
+#define configMAC_ADDR0 0x00\r
+#define configMAC_ADDR1 0x12\r
+#define configMAC_ADDR2 0x13\r
+#define configMAC_ADDR3 0x10\r
+#define configMAC_ADDR4 0x15\r
+#define configMAC_ADDR5 0x11\r
+\r
+/* IP address configuration. */\r
+#define configIP_ADDR0 192\r
+#define configIP_ADDR1 168\r
+#define configIP_ADDR2 0\r
+#define configIP_ADDR3 201\r
+\r
+/* Netmask configuration. */\r
+#define configNET_MASK0 255\r
+#define configNET_MASK1 255\r
+#define configNET_MASK2 255\r
+#define configNET_MASK3 0\r
+\r
+#endif /* FREERTOS_CONFIG_H */\r
--- /dev/null
+/*\r
+ FreeRTOS V6.0.5 - Copyright (C) 2010 Real Time Engineers Ltd.\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * If you are: *\r
+ * *\r
+ * + New to FreeRTOS, *\r
+ * + Wanting to learn FreeRTOS or multitasking in general quickly *\r
+ * + Looking for basic training, *\r
+ * + Wanting to improve your FreeRTOS skills and productivity *\r
+ * *\r
+ * then take a look at the FreeRTOS eBook *\r
+ * *\r
+ * "Using the FreeRTOS Real Time Kernel - a Practical Guide" *\r
+ * http://www.FreeRTOS.org/Documentation *\r
+ * *\r
+ * A pdf reference manual is also available. Both are usually delivered *\r
+ * to your inbox within 20 minutes to two hours when purchased between 8am *\r
+ * and 8pm GMT (although please allow up to 24 hours in case of *\r
+ * exceptional circumstances). Thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+ ***NOTE*** The exception to the GPL is included to allow you to distribute\r
+ a combined work that includes FreeRTOS without being obliged to provide the\r
+ source code for proprietary components outside of the FreeRTOS kernel.\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT\r
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\r
+ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ more details. You should have received a copy of the GNU General Public \r
+ License and the FreeRTOS license exception along with FreeRTOS; if not it \r
+ can be viewed here: http://www.freertos.org/a00114.html and also obtained \r
+ by writing to Richard Barry, contact details for whom are available on the\r
+ FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+\r
+ http://www.FreeRTOS.org - Documentation, latest information, license and\r
+ contact details.\r
+\r
+ http://www.SafeRTOS.com - A version that is certified for use in safety\r
+ critical systems.\r
+\r
+ http://www.OpenRTOS.com - Commercial support, development, porting,\r
+ licensing and training services.\r
+*/\r
+\r
+/* \r
+ * High frequency timer test as described in main.c. \r
+ */\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+\r
+/* Hardware specifics. */\r
+#include "iodefine.h"\r
+\r
+/* The set frequency of the interrupt. Deviations from this are measured as\r
+the jitter. */\r
+#define timerINTERRUPT_FREQUENCY ( 20000UL )\r
+\r
+/* The expected time between each of the timer interrupts - if the jitter was\r
+zero. */\r
+#define timerEXPECTED_DIFFERENCE_VALUE ( ( unsigned short ) ( ( configPERIPHERAL_CLOCK_HZ / 8UL ) / timerINTERRUPT_FREQUENCY ) )\r
+\r
+/* The highest available interrupt priority. */\r
+#define timerHIGHEST_PRIORITY ( 15 )\r
+\r
+/* Misc defines. */\r
+#define timerTIMER_3_COUNT_VALUE ( *( ( unsigned short * ) 0x8801a ) ) /*( CMT3.CMCNT )*/\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Interrupt handler in which the jitter is measured. */\r
+static void prvTimer2IntHandler( void );\r
+\r
+/* Stores the value of the maximum recorded jitter between interrupts. */\r
+volatile unsigned short usMaxJitter = 0;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void vSetupHighFrequencyTimer( void )\r
+{\r
+ /* Timer CMT2 is used to generate the interrupts, and CMT3 is used\r
+ to measure the jitter. */\r
+\r
+ /* Enable compare match timer 2 and 3. */\r
+ MSTP( CMT2 ) = 0;\r
+ MSTP( CMT3 ) = 0;\r
+ \r
+ /* Interrupt on compare match. */\r
+ CMT2.CMCR.BIT.CMIE = 1;\r
+ \r
+ /* Set the compare match value. */\r
+ CMT2.CMCOR = ( unsigned short ) ( ( ( configPERIPHERAL_CLOCK_HZ / timerINTERRUPT_FREQUENCY ) -1 ) / 8 );\r
+ \r
+ /* Divide the PCLK by 8. */\r
+ CMT2.CMCR.BIT.CKS = 0;\r
+ CMT3.CMCR.BIT.CKS = 0;\r
+ \r
+ /* Enable the interrupt... */\r
+ _IEN( _CMT2_CMI2 ) = 1;\r
+ \r
+ /* ...and set its priority to the maximum possible, this is above the priority\r
+ set by configMAX_SYSCALL_INTERRUPT_PRIORITY so will nest. */\r
+ _IPR( _CMT2_CMI2 ) = timerHIGHEST_PRIORITY;\r
+ \r
+ /* Start the timers. */\r
+ CMT.CMSTR1.BIT.STR2 = 1;\r
+ CMT.CMSTR1.BIT.STR3 = 1;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+#pragma interrupt ( prvTimer2IntHandler( vect = _VECT( _CMT2_CMI2 ), enable ) )\r
+static void prvTimer2IntHandler( void )\r
+{\r
+volatile unsigned short usCurrentCount;\r
+static unsigned short usMaxCount = 0;\r
+static unsigned long ulErrorCount = 0UL;\r
+\r
+ /* We use the timer 1 counter value to measure the clock cycles between\r
+ the timer 0 interrupts. First stop the clock. */\r
+ CMT.CMSTR1.BIT.STR3 = 0;\r
+ nop();\r
+ nop();\r
+ usCurrentCount = timerTIMER_3_COUNT_VALUE;\r
+\r
+ /* Is this the largest count we have measured yet? */\r
+ if( usCurrentCount > usMaxCount )\r
+ {\r
+ if( usCurrentCount > timerEXPECTED_DIFFERENCE_VALUE )\r
+ {\r
+ usMaxJitter = usCurrentCount - timerEXPECTED_DIFFERENCE_VALUE;\r
+ }\r
+ else\r
+ {\r
+ /* This should not happen! */\r
+ ulErrorCount++;\r
+ }\r
+ \r
+ usMaxCount = usCurrentCount;\r
+ }\r
+ \r
+ /* Clear the timer. */\r
+ timerTIMER_3_COUNT_VALUE = 0;\r
+ \r
+ /* Then start the clock again. */\r
+ CMT.CMSTR1.BIT.STR3 = 1;\r
+}\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V6.0.5 - Copyright (C) 2010 Real Time Engineers Ltd.\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * If you are: *\r
+ * *\r
+ * + New to FreeRTOS, *\r
+ * + Wanting to learn FreeRTOS or multitasking in general quickly *\r
+ * + Looking for basic training, *\r
+ * + Wanting to improve your FreeRTOS skills and productivity *\r
+ * *\r
+ * then take a look at the FreeRTOS eBook *\r
+ * *\r
+ * "Using the FreeRTOS Real Time Kernel - a Practical Guide" *\r
+ * http://www.FreeRTOS.org/Documentation *\r
+ * *\r
+ * A pdf reference manual is also available. Both are usually delivered *\r
+ * to your inbox within 20 minutes to two hours when purchased between 8am *\r
+ * and 8pm GMT (although please allow up to 24 hours in case of *\r
+ * exceptional circumstances). Thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+ ***NOTE*** The exception to the GPL is included to allow you to distribute\r
+ a combined work that includes FreeRTOS without being obliged to provide the\r
+ source code for proprietary components outside of the FreeRTOS kernel.\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT\r
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\r
+ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ more details. You should have received a copy of the GNU General Public \r
+ License and the FreeRTOS license exception along with FreeRTOS; if not it \r
+ can be viewed here: http://www.freertos.org/a00114.html and also obtained \r
+ by writing to Richard Barry, contact details for whom are available on the\r
+ FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+\r
+ http://www.FreeRTOS.org - Documentation, latest information, license and\r
+ contact details.\r
+\r
+ http://www.SafeRTOS.com - A version that is certified for use in safety\r
+ critical systems.\r
+\r
+ http://www.OpenRTOS.com - Commercial support, development, porting,\r
+ licensing and training services.\r
+*/\r
+\r
+/*\r
+ * This file contains the non-portable and therefore RX62N specific parts of\r
+ * the IntQueue standard demo task - namely the configuration of the timers\r
+ * that generate the interrupts and the interrupt entry points.\r
+ */\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/* Demo includes. */\r
+#include "IntQueueTimer.h"\r
+#include "IntQueue.h"\r
+\r
+/* Hardware specifics. */\r
+#include "iodefine.h"\r
+\r
+#define tmrTIMER_0_1_FREQUENCY ( 2000UL )\r
+#define tmrTIMER_2_3_FREQUENCY ( 2001UL )\r
+\r
+void vInitialiseTimerForIntQueueTest( void )\r
+{\r
+ /* Ensure interrupts do not start until full configuration is complete. */\r
+ portENTER_CRITICAL();\r
+ {\r
+ /* Cascade two 8bit timer channels to generate the interrupts. \r
+ 8bit timer unit 1 (TMR0 and TMR1) and 8bit timer unit 2 (TMR2 and TMR3 are\r
+ utilised for this test. */\r
+\r
+ /* Enable the timers. */\r
+ SYSTEM.MSTPCRA.BIT.MSTPA5 = 0;\r
+ SYSTEM.MSTPCRA.BIT.MSTPA4 = 0;\r
+\r
+ /* Enable compare match A interrupt request. */\r
+ TMR0.TCR.BIT.CMIEA = 1;\r
+ TMR2.TCR.BIT.CMIEA = 1;\r
+\r
+ /* Clear the timer on compare match A. */\r
+ TMR0.TCR.BIT.CCLR = 1;\r
+ TMR2.TCR.BIT.CCLR = 1;\r
+\r
+ /* Set the compare match value. */\r
+ TMR01.TCORA = ( unsigned short ) ( ( ( configPERIPHERAL_CLOCK_HZ / tmrTIMER_0_1_FREQUENCY ) -1 ) / 8 );\r
+ TMR23.TCORA = ( unsigned short ) ( ( ( configPERIPHERAL_CLOCK_HZ / tmrTIMER_0_1_FREQUENCY ) -1 ) / 8 );\r
+\r
+ /* 16 bit operation ( count from timer 1,2 ). */\r
+ TMR0.TCCR.BIT.CSS = 3;\r
+ TMR2.TCCR.BIT.CSS = 3;\r
+ \r
+ /* Use PCLK as the input. */\r
+ TMR1.TCCR.BIT.CSS = 1;\r
+ TMR3.TCCR.BIT.CSS = 1;\r
+ \r
+ /* Divide PCLK by 8. */\r
+ TMR1.TCCR.BIT.CKS = 2;\r
+ TMR3.TCCR.BIT.CKS = 2;\r
+ \r
+ /* Enable TMR 0, 2 interrupts. */\r
+ IEN( TMR0, CMIA0 ) = 1;\r
+ IEN( TMR2, CMIA2 ) = 1;\r
+\r
+ /* Set the timer interrupts to be above the kernel. The interrupts are\r
+ assigned different priorities so they nest with each other. */\r
+ IPR( TMR0, CMIA0 ) = configMAX_SYSCALL_INTERRUPT_PRIORITY - 1;\r
+ IPR( TMR2, CMIA2 ) = ( configMAX_SYSCALL_INTERRUPT_PRIORITY - 2 );\r
+ }\r
+ portEXIT_CRITICAL();\r
+ \r
+ /* Ensure the interrupts are clear as they are edge detected. */\r
+ IR( TMR0, CMIA0 ) = 0;\r
+ IR( TMR2, CMIA2 ) = 0;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+#pragma interrupt ( vT0_1InterruptHandler( vect = VECT_TMR0_CMIA0, enable ) )\r
+void vT0_1InterruptHandler( void )\r
+{\r
+ portYIELD_FROM_ISR( xFirstTimerHandler() );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+#pragma interrupt ( vT2_3InterruptHandler( vect = VECT_TMR2_CMIA2, enable ) )\r
+void vT2_3InterruptHandler( void )\r
+{\r
+ portYIELD_FROM_ISR( xSecondTimerHandler() );\r
+}\r
+\r
+\r
+\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V6.0.5 - Copyright (C) 2010 Real Time Engineers Ltd.\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * If you are: *\r
+ * *\r
+ * + New to FreeRTOS, *\r
+ * + Wanting to learn FreeRTOS or multitasking in general quickly *\r
+ * + Looking for basic training, *\r
+ * + Wanting to improve your FreeRTOS skills and productivity *\r
+ * *\r
+ * then take a look at the FreeRTOS eBook *\r
+ * *\r
+ * "Using the FreeRTOS Real Time Kernel - a Practical Guide" *\r
+ * http://www.FreeRTOS.org/Documentation *\r
+ * *\r
+ * A pdf reference manual is also available. Both are usually delivered *\r
+ * to your inbox within 20 minutes to two hours when purchased between 8am *\r
+ * and 8pm GMT (although please allow up to 24 hours in case of *\r
+ * exceptional circumstances). Thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+ ***NOTE*** The exception to the GPL is included to allow you to distribute\r
+ a combined work that includes FreeRTOS without being obliged to provide the\r
+ source code for proprietary components outside of the FreeRTOS kernel.\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT\r
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\r
+ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ more details. You should have received a copy of the GNU General Public\r
+ License and the FreeRTOS license exception along with FreeRTOS; if not it\r
+ can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
+ by writing to Richard Barry, contact details for whom are available on the\r
+ FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+\r
+ http://www.FreeRTOS.org - Documentation, latest information, license and\r
+ contact details.\r
+\r
+ http://www.SafeRTOS.com - A version that is certified for use in safety\r
+ critical systems.\r
+\r
+ http://www.OpenRTOS.com - Commercial support, development, porting,\r
+ licensing and training services.\r
+*/\r
+\r
+/*-----------------------------------------------------------\r
+ * Simple IO routines to control the LEDs.\r
+ *-----------------------------------------------------------*/\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/* Demo includes. */\r
+#include "partest.h"\r
+\r
+/* Hardware specifics. */\r
+#include "iodefine.h"\r
+\r
+#define partestNUM_LEDS ( 12 )\r
+\r
+long lParTestGetLEDState( unsigned long ulLED );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestInitialise( void )\r
+{\r
+ /* Port pin configuration is done by the low level set up prior to this\r
+ function being called. */\r
+\r
+ /* Start with all LEDs off. */\r
+ LED0 = LED_OFF;\r
+ LED1 = LED_OFF;\r
+ LED2 = LED_OFF;\r
+ LED3 = LED_OFF;\r
+ LED4 = LED_OFF;\r
+ LED5 = LED_OFF;\r
+ LED6 = LED_OFF;\r
+ LED7 = LED_OFF;\r
+ LED8 = LED_OFF;\r
+ LED9 = LED_OFF;\r
+ LED10 = LED_OFF;\r
+ LED11 = LED_OFF;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestSetLED( unsigned long ulLED, signed long xValue )\r
+{\r
+ if( ulLED < partestNUM_LEDS )\r
+ {\r
+ if( xValue != 0 )\r
+ {\r
+ /* Turn the LED on. */\r
+ taskENTER_CRITICAL();\r
+ {\r
+ switch( ulLED )\r
+ {\r
+ case 0: LED0 = LED_ON;\r
+ break;\r
+ case 1: LED1 = LED_ON;\r
+ break;\r
+ case 2: LED2 = LED_ON;\r
+ break;\r
+ case 3: LED3 = LED_ON;\r
+ break;\r
+ case 4: LED4 = LED_ON;\r
+ break;\r
+ case 5: LED5 = LED_ON;\r
+ break;\r
+ case 6: LED6 = LED_ON;\r
+ break;\r
+ case 7: LED7 = LED_ON;\r
+ break;\r
+ case 8: LED8 = LED_ON;\r
+ break;\r
+ case 9: LED9 = LED_ON;\r
+ break;\r
+ case 10:LED10 = LED_ON;\r
+ break;\r
+ case 11:LED11 = LED_ON;\r
+ break;\r
+ }\r
+ }\r
+ taskEXIT_CRITICAL();\r
+ }\r
+ else\r
+ {\r
+ /* Turn the LED off. */\r
+ taskENTER_CRITICAL();\r
+ {\r
+ switch( ulLED )\r
+ {\r
+ case 0: LED0 = LED_OFF;\r
+ break;\r
+ case 1: LED1 = LED_OFF;\r
+ break;\r
+ case 2: LED2 = LED_OFF;\r
+ break;\r
+ case 3: LED3 = LED_OFF;\r
+ break;\r
+ case 4: LED4 = LED_OFF;\r
+ break;\r
+ case 5: LED5 = LED_OFF;\r
+ break;\r
+ case 6: LED6 = LED_OFF;\r
+ break;\r
+ case 7: LED7 = LED_OFF;\r
+ break;\r
+ case 8: LED8 = LED_OFF;\r
+ break;\r
+ case 9: LED9 = LED_OFF;\r
+ break;\r
+ case 10:LED10 = LED_OFF;\r
+ break;\r
+ case 11:LED11 = LED_OFF;\r
+ break;\r
+ }\r
+\r
+ }\r
+ taskEXIT_CRITICAL();\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestToggleLED( unsigned long ulLED )\r
+{\r
+ if( ulLED < partestNUM_LEDS )\r
+ {\r
+ taskENTER_CRITICAL();\r
+ {\r
+ if( lParTestGetLEDState( ulLED ) != 0x00 )\r
+ {\r
+ vParTestSetLED( ulLED, 0 );\r
+ }\r
+ else\r
+ {\r
+ vParTestSetLED( ulLED, 1 );\r
+ }\r
+ }\r
+ taskEXIT_CRITICAL();\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+long lParTestGetLEDState( unsigned long ulLED )\r
+{\r
+long lReturn = pdFALSE;\r
+\r
+ if( ulLED < partestNUM_LEDS )\r
+ {\r
+ switch( ulLED )\r
+ {\r
+ case 0 : if( LED0 != 0 )\r
+ {\r
+ lReturn = pdTRUE;\r
+ }\r
+ break;\r
+ case 1 : if( LED1 != 0 )\r
+ {\r
+ lReturn = pdTRUE;\r
+ }\r
+ break;\r
+ case 2 : if( LED2 != 0 )\r
+ {\r
+ lReturn = pdTRUE;\r
+ }\r
+ break;\r
+ case 3 : if( LED3 != 0 )\r
+ {\r
+ lReturn = pdTRUE;\r
+ }\r
+ break;\r
+ case 4 : if( LED4 != 0 )\r
+ {\r
+ lReturn = pdTRUE;\r
+ }\r
+ break;\r
+ case 5 : if( LED5 != 0 )\r
+ {\r
+ lReturn = pdTRUE;\r
+ }\r
+ break;\r
+ case 6 : if( LED6 != 0 )\r
+ {\r
+ lReturn = pdTRUE;\r
+ }\r
+ break;\r
+ case 7 : if( LED7 != 0 )\r
+ {\r
+ lReturn = pdTRUE;\r
+ }\r
+ break;\r
+ case 8 : if( LED8 != 0 )\r
+ {\r
+ lReturn = pdTRUE;\r
+ }\r
+ break;\r
+ case 9 : if( LED9 != 0 )\r
+ {\r
+ lReturn = pdTRUE;\r
+ }\r
+ break;\r
+ case 10 : if( LED10 != 0 )\r
+ {\r
+ lReturn = pdTRUE;\r
+ }\r
+ break;\r
+ case 11 : if( LED11 != 0 )\r
+ {\r
+ lReturn = pdTRUE;\r
+ }\r
+ break;\r
+ }\r
+ }\r
+\r
+ return lReturn;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
--- /dev/null
+[HIMDBVersion]\r
+2.0\r
+[DATABASE_VERSION]\r
+"2.8" \r
+[PROJECT_DETAILS]\r
+"RTOSDemo" "C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX62N-RDK_Renesas\RTOSDemo" "C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX62N-RDK_Renesas\RTOSDemo\RTOSDemo.hwp" "RX" "Renesas RX Standard" "Application" "RX600" "Other" \r
+[INFORMATION]\r
+"No project information available" \r
+[TOOL_CHAIN]\r
+"Renesas RX Standard Toolchain" "1.0.0.0" \r
+[CONFIGURATIONS]\r
+"Blinky" "C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX62N-RDK_Renesas\RTOSDemo\Blinky" \r
+"Debug" "C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX62N-RDK_Renesas\RTOSDemo\Debug" \r
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+"Debug_with_optimisation" "C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX62N-RDK_Renesas\RTOSDemo\Debug_with_optimisation" \r
+"SimDebug_RX600" "C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX62N-RDK_Renesas\RTOSDemo\SimDebug_RX600" \r
+[BUILD_PHASES]\r
+"Renesas OptLinker" 1 \r
+"Renesas RX Assembler" 1 \r
+"Renesas RX C/C++ Compiler" 1 \r
+"Renesas RX C/C++ Library Generator" 1 \r
+"Renesas RX Configurator" 1 \r
+[TOOL_ENVIRONMENT]\r
+[EXTENSIONS]\r
+"Absolute file" "ABS" \r
+"Assembly include file" "INC" \r
+"Assembly list file" "LST" \r
+"Assembly source file" "S" \r
+"Assembly source file" "SRC" \r
+"Binary file" "BIN" \r
+"C header file" "H" \r
+"C source file" "C" \r
+"C++ header file" "HPP" \r
+"C++ source file" "CC" \r
+"C++ source file" "CP" \r
+"C++ source file" "CPP" \r
+"CPU information file" "CPU" \r
+"Calling information file" "CAL" \r
+"Configuration file" "CFG" \r
+"Debug information file" "DBG" \r
+"Hex file" "HEX" \r
+"Library file" "LIB" \r
+"Library information file" "LBP" \r
+"Linkage map file" "MAP" \r
+"Linkage symbol file" "FSY" \r
+"Object file" "OBJ" \r
+"Optimize map file" "bls" \r
+"Preprocessed C source file" "P" \r
+"Preprocessed C++ source file" "PP" \r
+"Relocatable file" "REL" \r
+"Rts information file" "RTS" \r
+"S-Record file" "MOT" \r
+"Stack information file" "SNI" \r
+"TD include object file" "RTI" \r
+[FILE_GROUPS]\r
+"Absolute file" "BIN" "NONE" "" \r
+"Assembly include file" "TEXT" "EDITOR" "" \r
+"Assembly list file" "TEXT" "EDITOR" "" \r
+"Assembly source file" "TEXT" "EDITOR" "" \r
+"Binary file" "BIN" "NONE" "" \r
+"C header file" "TEXT" "EDITOR" "" \r
+"C source file" "TEXT" "EDITOR" "" \r
+"C++ header file" "TEXT" "EDITOR" "" \r
+"C++ source file" "TEXT" "EDITOR" "" \r
+"CPU information file" "BIN" "NONE" "" \r
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+"Hex file" "TEXT" "EDITOR" "" \r
+"Library file" "BIN" "NONE" "" \r
+"Library information file" "TEXT" "EDITOR" "" \r
+"Linkage map file" "TEXT" "EDITOR" "" \r
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+"Preprocessed C source file" "TEXT" "EDITOR" "" \r
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+"S-Record file" "TEXT" "EDITOR" "" \r
+"Stack information file" "BIN" "NONE" "" \r
+"TD include object file" "BIN" "NONE" "" \r
+[ASSOCIATED_APPLICATIONS]\r
+[TOOLCHAIN_PHASE]\r
+"Renesas OptLinker" \r
+"Renesas RX Assembler" \r
+"Renesas RX C/C++ Compiler" \r
+"Renesas RX C/C++ Library Generator" \r
+"Renesas RX Configurator" \r
+[UTILITY_PHASE]\r
+[CUSTOM_PHASES]\r
+[CUSTOM_PHASE_INPUT_GROUP]\r
+[CUSTOM_PHASE_OUTPUT_SYNTAX]\r
+[BUILD_ORDER]\r
+"Renesas RX C/C++ Library Generator" 1 \r
+"Renesas RX C/C++ Compiler" 1 \r
+"Renesas RX Assembler" 1 \r
+"Renesas OptLinker" 1 \r
+"Renesas RX Configurator" 0 \r
+[BUILD_PHASE_DETAILS]\r
+"Renesas OptLinker" "Object file|Library file|Relocatable file" 0 \r
+"Renesas RX Assembler" "Assembly source file|Linkage symbol file" 1 \r
+"Renesas RX C/C++ Compiler" "C source file|C++ source file" 1 \r
+"Renesas RX C/C++ Library Generator" "" 0 \r
+"Renesas RX Configurator" "Configuration file" 0 \r
+[BUILD_FILE_ORDER_Assembly source file]\r
+"Renesas RX Assembler" 1 \r
+[BUILD_FILE_ORDER_C source file]\r
+"Renesas RX C/C++ Compiler" 1 \r
+[BUILD_FILE_ORDER_C++ source file]\r
+"Renesas RX C/C++ Compiler" 1 \r
+[BUILD_FILE_ORDER_Linkage symbol file]\r
+"Renesas RX Assembler" 1 \r
+[SCRAP]\r
+"Project Generator Setup File" "" \r
+[MAPPINGS]\r
+"Assembly source file" "Renesas RX Assembler" "Renesas RX C/C++ Compiler" \r
+"Library file" "Renesas OptLinker" "Renesas RX C/C++ Library Generator" \r
+"Object file" "Renesas OptLinker" "Renesas RX Assembler" \r
+"Object file" "Renesas OptLinker" "Renesas RX C/C++ Compiler" \r
+[PROJECT_FILES]\r
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+"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\Common\Minimal\GenQTest.c" "User" "C source file|Common demo tasks" 2 \r
+"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\Common\Minimal\IntQueue.c" "User" "C source file|Common demo tasks" 2 \r
+"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\Common\Minimal\PollQ.c" "User" "C source file|Common demo tasks" 2 \r
+"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\Common\Minimal\QPeek.c" "User" "C source file|Common demo tasks" 2 \r
+"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\Common\Minimal\blocktim.c" "User" "C source file|Common demo tasks" 2 \r
+"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\Common\Minimal\death.c" "User" "C source file|Common demo tasks" 2 \r
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+"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\Common\Minimal\flop.c" "User" "C source file|Common demo tasks" 2 \r
+"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\Common\Minimal\integer.c" "User" "C source file|Common demo tasks" 2 \r
+"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\Common\Minimal\recmutex.c" "User" "C source file|Common demo tasks" 2 \r
+"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\Common\Minimal\semtest.c" "User" "C source file|Common demo tasks" 2 \r
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+[OPTIONS_Blinky_Renesas RX Configurator]\r
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+[OPTIONS_Blinky]\r
+"" 0 \r
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+" 3 \r
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+" 2 \r
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+" 1 \r
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+" 5 \r
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+"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\Common\Minimal\death.c" \r
+"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\Common\Minimal\flash.c" \r
+"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\Common\Minimal\flop.c" \r
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+"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\Common\Minimal\integer.c" \r
+"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\Common\Minimal\IntQueue.c" \r
+"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\Common\Minimal\PollQ.c" \r
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+"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX62N-RDK_Renesas\RTOSDemo\HighFrequencyTimerTest.c" \r
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+[OPTIONS_Debug_Renesas RX Configurator]\r
+"Single Shot" "02c169eb6f14bc10" 6 \r
+[OPTIONS_Debug]\r
+"" 0 \r
+"[V|VERSION|1] [B|COMMAND|1] [S|SPEC|UITRON4] [S|OUTPUTPATH|^"$(CONFIGDIR)^"] [S|CPU|RX600] [S|ENDIAN|LITTLE] [S|FINT_REGISTER|0]" 6 \r
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+" 4 \r
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+" 2 \r
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+[OPTIONS_Debug_RX600_E1_E20_SYSTEM_Renesas RX C/C++ Library Generator]\r
+"Single Shot" "0cb120ca4793bc10" 1 \r
+[OPTIONS_Debug_RX600_E1_E20_SYSTEM_Renesas RX Configurator]\r
+"Single Shot" "02c169eb6f14bc10" 5 \r
+[OPTIONS_Debug_RX600_E1_E20_SYSTEM]\r
+"" 0 \r
+"[S|OUTPUTPATH|^"$(CONFIGDIR)\$(PROJECTNAME).lib^"] [V|VERSION|1] [S|CPU|RX600] [S|ENDIAN|LITTLE] [S|ROUND|NEAREST] [S|DBL_SIZE|4] [B|SIGNED_CHAR|0] [B|SIGNED_BITFIELD|0] [S|BIT_ORDER|RIGHT] [S|FINT_REGISTER|0] [S|BRANCH|24] [S|LANG|C] [B|RUNTIME|1] [B|CTYPE|0] [B|MATH|0] [B|MATHF|0] [B|STDARG|0] [B|STDIO|0] [B|STDLIB|0] [B|STRING|0] [B|IOS|0] [B|NEW|1] [B|COMPLEX|0] [B|CPPSTRING|0] [S|MODE|BUILD/CHANGED]" 1 \r
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+[LINKAGE_ORDER_Debug_with_optimisation]\r
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+"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\Common\Minimal\recmutex.c" "05d6fdab4a04bc10" 2 \r
+"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\Common\Minimal\semtest.c" "05d6fdab4a04bc10" 2 \r
+"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX62N-RDK_Renesas\RTOSDemo\HighFrequencyTimerTest.c" "00526507a114bc10" 2 \r
+"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX62N-RDK_Renesas\RTOSDemo\IntQueueTimer.c" "0a762c328df3bc10" 2 \r
+"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX62N-RDK_Renesas\RTOSDemo\ParTest.c" "08d08b78d2d3bc10" 2 \r
+"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX62N-RDK_Renesas\RTOSDemo\Renesas-Files\dbsct.c" "0cd92d23ed14bc10" 2 \r
+"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX62N-RDK_Renesas\RTOSDemo\Renesas-Files\hwsetup.c" "0cd92d23ed14bc10" 2 \r
+"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX62N-RDK_Renesas\RTOSDemo\Renesas-Files\intprg.c" "0cd92d23ed14bc10" 2 \r
+"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX62N-RDK_Renesas\RTOSDemo\Renesas-Files\lowsrc.c" "0cd92d23ed14bc10" 2 \r
+"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX62N-RDK_Renesas\RTOSDemo\Renesas-Files\resetprg.c" "0cd92d23ed14bc10" 2 \r
+"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX62N-RDK_Renesas\RTOSDemo\Renesas-Files\sbrk.c" "0cd92d23ed14bc10" 2 \r
+"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX62N-RDK_Renesas\RTOSDemo\Renesas-Files\vecttbl.c" "0cd92d23ed14bc10" 2 \r
+"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX62N-RDK_Renesas\RTOSDemo\main-blinky.c" "02c169eb6f14bc10" 2 \r
+"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\RX600_RX62N-RDK_Renesas\RTOSDemo\main-full.c" "03ceac85ed14bc10" 2 \r
+"C:\E\Dev\FreeRTOS\WorkingCopy\Source\list.c" "04345d232893bc10" 2 \r
+"C:\E\Dev\FreeRTOS\WorkingCopy\Source\portable\MemMang\heap_2.c" "0b083d452893bc10" 2 \r
+"C:\E\Dev\FreeRTOS\WorkingCopy\Source\portable\Renesas\RX600\port.c" "0b8497895893bc10" 2 \r
+"C:\E\Dev\FreeRTOS\WorkingCopy\Source\queue.c" "04345d232893bc10" 2 \r
+"C:\E\Dev\FreeRTOS\WorkingCopy\Source\tasks.c" "04345d232893bc10" 2 \r
+[OPTIONS_SimDebug_RX600_Renesas RX C/C++ Library Generator]\r
+"Single Shot" "0cb120ca4793bc10" 1 \r
+[OPTIONS_SimDebug_RX600_Renesas RX Configurator]\r
+"Single Shot" "02c169eb6f14bc10" 5 \r
+[OPTIONS_SimDebug_RX600]\r
+"" 0 \r
+"[S|OUTPUTPATH|^"$(CONFIGDIR)\$(PROJECTNAME).lib^"] [V|VERSION|1] [S|CPU|RX600] [S|ENDIAN|LITTLE] [S|ROUND|NEAREST] [S|DBL_SIZE|4] [B|SIGNED_CHAR|0] [B|SIGNED_BITFIELD|0] [S|BIT_ORDER|RIGHT] [S|FINT_REGISTER|0] [S|BRANCH|24] [S|LANG|C] [B|RUNTIME|1] [B|CTYPE|0] [B|MATH|0] [B|MATHF|0] [B|STDARG|0] [B|STDIO|0] [B|STDLIB|0] [B|STRING|0] [B|IOS|0] [B|NEW|1] [B|COMPLEX|0] [B|CPPSTRING|0] [S|MODE|BUILD/CHANGED]" 1 \r
+"[V|VERSION|1] [B|COMMAND|1] [S|SPEC|UITRON4] [S|OUTPUTPATH|^"$(CONFIGDIR)^"] [S|CPU|RX600] [S|ENDIAN|LITTLE] [S|FINT_REGISTER|0]" 5 \r
+"[V|VERSION|1] [B|DEBUG|1] [S|OUTPUTPATH|^"$(CONFIGDIR)\$(FILELEAF).obj^"] [B|LISTFILE|0] [S|CPU|RX600] [S|ENDIAN|LITTLE] [S|FINT_REGISTER|0]" 3 \r
+"[V|VERSION|1] [B|DEBUG|1] [S|OUTPUTPATH|^"$(CONFIGDIR)\$(FILELEAF).obj^"] [B|LISTFILE|0] [S|CPU|RX600] [S|ENDIAN|LITTLE] [S|ROUND|NEAREST] [S|DBL_SIZE|4] [B|SIGNED_CHAR|0] [B|SIGNED_BITFIELD|0] [S|BIT_ORDER|RIGHT] [S|FINT_REGISTER|0] [S|BRANCH|24]" 2 \r
+"[V|VERSION|6] [B|DEBUG|1] [S|OUTPUT|^"$(CONFIGDIR)\$(PROJECTNAME).abs^"] [B|LIST|1] [S|LIST|^"$(CONFIGDIR)\$(PROJECTNAME).map^"] [B|OPTIMIZE|0] [S|ROM|(D,R)|(D_1,R_1)|(D_2,R_2)] [S|FORM|STYPE] [S|OUTPUT|^"$(CONFIGDIR)\$(PROJECTNAME).mot^"] [S|START|B_1,R_1,B_2,R_2,B,R,SU,SI(1000)|PResetPRG(FFFF8000)|C_1,C_2,C,C$*,D*,P,PIntPRG,W*(FFFF8100)|FIXEDVECT(FFFFFFD0)]" 4 \r
+[EXCLUDED_FILES_SimDebug_RX600]\r
+[LINKAGE_ORDER_SimDebug_RX600]\r
+[GENERAL_DATA_CONFIGURATION_SimDebug_RX600]\r
+[GENERAL_DATA_CONFIGURATION_SESSION_Blinky_DefaultSession]\r
+[SESSION_DATA_CONFIGURATION_SESSION_Blinky_DefaultSession]\r
+"MEMORY_MAPPING_OPTIONS" "" \r
+[GENERAL_DATA_CONFIGURATION_SESSION_Blinky_SessionRX600_E1_E20_SYSTEM]\r
+[SESSION_DATA_CONFIGURATION_SESSION_Blinky_SessionRX600_E1_E20_SYSTEM]\r
+"MEMORY_MAPPING_OPTIONS" "Unknown Options" \r
+[GENERAL_DATA_CONFIGURATION_SESSION_Blinky_SimSessionRX600]\r
+[SESSION_DATA_CONFIGURATION_SESSION_Blinky_SimSessionRX600]\r
+"MEMORY_MAPPING_OPTIONS" "[V|VERSION|1] [S|CPUTYPE|^"Other (RX600)^"] [S|MAP|^"0x00000000,0x0001FFFF,RAM,32,0101,2 0x00080000,0x000FFFFF,I/O,32,0101,2 0x00100000,0x00107FFF,ROM,32,0101,2 0x007F8000,0x007F9FFF,RAM,32,0101,2 0x007FC000,0x007FC4FF,I/O,32,0101,2 0x007FFC00,0x007FFFFF,I/O,32,0101,2 0x00E00000,0x00FFFFFF,ROM,32,0101,2 0xFEFFE000,0xFEFFFFFF,ROM,32,0101,2 0xFF7FC000,0xFF7FFFFF,ROM,32,0101,2 0xFFE00000,0xFFFFFFFF,ROM,32,0101,2^"] [S|RESOURCE|^"0x00000000,0x0001FFFF,R/W 0x00080000,0x000FFFFF,R/W 0x007FC000,0x007FC4FF,R/W 0x007FFC00,0x007FFFFF,R/W 0xFFFF8000,0xFFFFFFFF,R/W ^"] [B|SIMIOF|0] [I|SIMIOADR|0x0] [I|BUS_MODE|0] [S|ENDIAN|^"LITTLE^"] [S|PATCH|^"OFF^"]" \r
+[GENERAL_DATA_CONFIGURATION_SESSION_Debug_DefaultSession]\r
+[SESSION_DATA_CONFIGURATION_SESSION_Debug_DefaultSession]\r
+"MEMORY_MAPPING_OPTIONS" "" \r
+[GENERAL_DATA_CONFIGURATION_SESSION_Debug_SessionRX600_E1_E20_SYSTEM]\r
+[SESSION_DATA_CONFIGURATION_SESSION_Debug_SessionRX600_E1_E20_SYSTEM]\r
+"MEMORY_MAPPING_OPTIONS" "Unknown Options" \r
+[GENERAL_DATA_CONFIGURATION_SESSION_Debug_SimSessionRX600]\r
+[SESSION_DATA_CONFIGURATION_SESSION_Debug_SimSessionRX600]\r
+"MEMORY_MAPPING_OPTIONS" "[V|VERSION|1] [S|CPUTYPE|^"Other (RX600)^"] [S|MAP|^"0x00000000,0x0001FFFF,RAM,32,0101,2 0x00080000,0x000FFFFF,I/O,32,0101,2 0x00100000,0x00107FFF,ROM,32,0101,2 0x007F8000,0x007F9FFF,RAM,32,0101,2 0x007FC000,0x007FC4FF,I/O,32,0101,2 0x007FFC00,0x007FFFFF,I/O,32,0101,2 0x00E00000,0x00FFFFFF,ROM,32,0101,2 0xFEFFE000,0xFEFFFFFF,ROM,32,0101,2 0xFF7FC000,0xFF7FFFFF,ROM,32,0101,2 0xFFE00000,0xFFFFFFFF,ROM,32,0101,2^"] [S|RESOURCE|^"0x00000000,0x0001FFFF,R/W 0x00080000,0x000FFFFF,R/W 0x007FC000,0x007FC4FF,R/W 0x007FFC00,0x007FFFFF,R/W 0xFFFF8000,0xFFFFFFFF,R/W ^"] [B|SIMIOF|0] [I|SIMIOADR|0x0] [I|BUS_MODE|0] [S|ENDIAN|^"LITTLE^"] [S|PATCH|^"OFF^"]" \r
+[GENERAL_DATA_CONFIGURATION_SESSION_Debug_RX600_E1_E20_SYSTEM_DefaultSession]\r
+[SESSION_DATA_CONFIGURATION_SESSION_Debug_RX600_E1_E20_SYSTEM_DefaultSession]\r
+"MEMORY_MAPPING_OPTIONS" "" \r
+[GENERAL_DATA_CONFIGURATION_SESSION_Debug_RX600_E1_E20_SYSTEM_SessionRX600_E1_E20_SYSTEM]\r
+[SESSION_DATA_CONFIGURATION_SESSION_Debug_RX600_E1_E20_SYSTEM_SessionRX600_E1_E20_SYSTEM]\r
+"MEMORY_MAPPING_OPTIONS" "Unknown Options" \r
+[GENERAL_DATA_CONFIGURATION_SESSION_Debug_RX600_E1_E20_SYSTEM_SimSessionRX600]\r
+[SESSION_DATA_CONFIGURATION_SESSION_Debug_RX600_E1_E20_SYSTEM_SimSessionRX600]\r
+"MEMORY_MAPPING_OPTIONS" "[V|VERSION|1] [S|CPUTYPE|^"Other (RX600)^"] [S|MAP|^"0x00000000,0x0001FFFF,RAM,32,0101,2 0x00080000,0x000FFFFF,I/O,32,0101,2 0x00100000,0x00107FFF,ROM,32,0101,2 0x007F8000,0x007F9FFF,RAM,32,0101,2 0x007FC000,0x007FC4FF,I/O,32,0101,2 0x007FFC00,0x007FFFFF,I/O,32,0101,2 0x00E00000,0x00FFFFFF,ROM,32,0101,2 0xFEFFE000,0xFEFFFFFF,ROM,32,0101,2 0xFF7FC000,0xFF7FFFFF,ROM,32,0101,2 0xFFE00000,0xFFFFFFFF,ROM,32,0101,2^"] [S|RESOURCE|^"0x00000000,0x0001FFFF,R/W 0x00080000,0x000FFFFF,R/W 0x007FC000,0x007FC4FF,R/W 0x007FFC00,0x007FFFFF,R/W 0xFFFF8000,0xFFFFFFFF,R/W ^"] [B|SIMIOF|0] [I|SIMIOADR|0x0] [I|BUS_MODE|0] [S|ENDIAN|^"LITTLE^"] [S|PATCH|^"OFF^"]" \r
+[GENERAL_DATA_CONFIGURATION_SESSION_Debug_with_optimisation_DefaultSession]\r
+[SESSION_DATA_CONFIGURATION_SESSION_Debug_with_optimisation_DefaultSession]\r
+"MEMORY_MAPPING_OPTIONS" "" \r
+[GENERAL_DATA_CONFIGURATION_SESSION_Debug_with_optimisation_SessionRX600_E1_E20_SYSTEM]\r
+[SESSION_DATA_CONFIGURATION_SESSION_Debug_with_optimisation_SessionRX600_E1_E20_SYSTEM]\r
+"MEMORY_MAPPING_OPTIONS" "Unknown Options" \r
+[GENERAL_DATA_CONFIGURATION_SESSION_Debug_with_optimisation_SimSessionRX600]\r
+[SESSION_DATA_CONFIGURATION_SESSION_Debug_with_optimisation_SimSessionRX600]\r
+"MEMORY_MAPPING_OPTIONS" "[V|VERSION|1] [S|CPUTYPE|^"Other (RX600)^"] [S|MAP|^"0x00000000,0x0001FFFF,RAM,32,0101,2 0x00080000,0x000FFFFF,I/O,32,0101,2 0x00100000,0x00107FFF,ROM,32,0101,2 0x007F8000,0x007F9FFF,RAM,32,0101,2 0x007FC000,0x007FC4FF,I/O,32,0101,2 0x007FFC00,0x007FFFFF,I/O,32,0101,2 0x00E00000,0x00FFFFFF,ROM,32,0101,2 0xFEFFE000,0xFEFFFFFF,ROM,32,0101,2 0xFF7FC000,0xFF7FFFFF,ROM,32,0101,2 0xFFE00000,0xFFFFFFFF,ROM,32,0101,2^"] [S|RESOURCE|^"0x00000000,0x0001FFFF,R/W 0x00080000,0x000FFFFF,R/W 0x007FC000,0x007FC4FF,R/W 0x007FFC00,0x007FFFFF,R/W 0xFFFF8000,0xFFFFFFFF,R/W ^"] [B|SIMIOF|0] [I|SIMIOADR|0x0] [I|BUS_MODE|0] [S|ENDIAN|^"LITTLE^"] [S|PATCH|^"OFF^"]" \r
+[GENERAL_DATA_CONFIGURATION_SESSION_SimDebug_RX600_DefaultSession]\r
+[SESSION_DATA_CONFIGURATION_SESSION_SimDebug_RX600_DefaultSession]\r
+"MEMORY_MAPPING_OPTIONS" "" \r
+[GENERAL_DATA_CONFIGURATION_SESSION_SimDebug_RX600_SessionRX600_E1_E20_SYSTEM]\r
+[SESSION_DATA_CONFIGURATION_SESSION_SimDebug_RX600_SessionRX600_E1_E20_SYSTEM]\r
+"MEMORY_MAPPING_OPTIONS" "Unknown Options" \r
+[GENERAL_DATA_CONFIGURATION_SESSION_SimDebug_RX600_SimSessionRX600]\r
+[SESSION_DATA_CONFIGURATION_SESSION_SimDebug_RX600_SimSessionRX600]\r
+"MEMORY_MAPPING_OPTIONS" "[V|VERSION|1] [S|CPUTYPE|^"Other (RX600)^"] [S|MAP|^"0x00000000,0x0001FFFF,RAM,32,0101,2 0x00080000,0x000FFFFF,I/O,32,0101,2 0x00100000,0x00107FFF,ROM,32,0101,2 0x007F8000,0x007F9FFF,RAM,32,0101,2 0x007FC000,0x007FC4FF,I/O,32,0101,2 0x007FFC00,0x007FFFFF,I/O,32,0101,2 0x00E00000,0x00FFFFFF,ROM,32,0101,2 0xFEFFE000,0xFEFFFFFF,ROM,32,0101,2 0xFF7FC000,0xFF7FFFFF,ROM,32,0101,2 0xFFE00000,0xFFFFFFFF,ROM,32,0101,2^"] [S|RESOURCE|^"0x00000000,0x0001FFFF,R/W 0x00080000,0x000FFFFF,R/W 0x007FC000,0x007FC4FF,R/W 0x007FFC00,0x007FFFFF,R/W 0xFFFF8000,0xFFFFFFFF,R/W ^"] [B|SIMIOF|0] [I|SIMIOADR|0x0] [I|BUS_MODE|0] [S|ENDIAN|^"LITTLE^"] [S|PATCH|^"OFF^"]" \r
+[EXT_DEBUGGER_INFO]\r
+0 "" "" "" "" \r
+[END]\r
--- /dev/null
+[HIMDBVersion]\r
+2.0\r
+[DATABASE_VERSION]\r
+"1.1" \r
+[SESSIONS_]\r
+"DefaultSession" \r
+"SessionRX600_E1_E20_SYSTEM" \r
+"SimSessionRX600" \r
+[CONFIGURATIONS]\r
+"Blinky" \r
+"Debug" \r
+"Debug_RX600_E1_E20_SYSTEM" \r
+"Debug_with_optimisation" \r
+"SimDebug_RX600" \r
+[CURRENT_CONFIGURATION]\r
+"Debug" \r
+[CURRENT_SESSION]\r
+"SessionRX600_E1_E20_SYSTEM" \r
+[GENERAL_DATA_PROJECT]\r
+[GENERAL_DATA_CONFIGURATION_Blinky]\r
+"PROJECT_FILES_MODIFIED_DATA_TAG" "TRUE" \r
+[SESSIONS_Blinky]\r
+"DefaultSession" \r
+"SessionRX600_E1_E20_SYSTEM" \r
+"SimSessionRX600" \r
+[GENERAL_DATA_CONFIGURATION_Debug]\r
+"PROJECT_FILES_MODIFIED_DATA_TAG" "FALSE" \r
+[SESSIONS_Debug]\r
+"DefaultSession" \r
+"SessionRX600_E1_E20_SYSTEM" \r
+"SimSessionRX600" \r
+[GENERAL_DATA_CONFIGURATION_Debug_RX600_E1_E20_SYSTEM]\r
+"PROJECT_FILES_MODIFIED_DATA_TAG" "TRUE" \r
+[SESSIONS_Debug_RX600_E1_E20_SYSTEM]\r
+"DefaultSession" \r
+"SessionRX600_E1_E20_SYSTEM" \r
+"SimSessionRX600" \r
+[GENERAL_DATA_CONFIGURATION_Debug_with_optimisation]\r
+"PROJECT_FILES_MODIFIED_DATA_TAG" "TRUE" \r
+[SESSIONS_Debug_with_optimisation]\r
+"DefaultSession" \r
+"SessionRX600_E1_E20_SYSTEM" \r
+"SimSessionRX600" \r
+[GENERAL_DATA_CONFIGURATION_SimDebug_RX600]\r
+"PROJECT_FILES_MODIFIED_DATA_TAG" "TRUE" \r
+[SESSIONS_SimDebug_RX600]\r
+"DefaultSession" \r
+"SessionRX600_E1_E20_SYSTEM" \r
+"SimSessionRX600" \r
+[GENERAL_DATA_SESSION_SimSessionRX600]\r
+[GENERAL_DATA_SESSION_DefaultSession]\r
+[GENERAL_DATA_CONFIGURATION_SESSION_Debug_with_optimisation_SimSessionRX600]\r
+[GENERAL_DATA_CONFIGURATION_SESSION_Debug_RX600_E1_E20_SYSTEM_SimSessionRX600]\r
+[GENERAL_DATA_CONFIGURATION_SESSION_Blinky_SessionRX600_E1_E20_SYSTEM]\r
+[GENERAL_DATA_CONFIGURATION_SESSION_Blinky_DefaultSession]\r
+[GENERAL_DATA_CONFIGURATION_SESSION_Debug_RX600_E1_E20_SYSTEM_SessionRX600_E1_E20_SYSTEM]\r
+[GENERAL_DATA_CONFIGURATION_SESSION_Debug_DefaultSession]\r
+[GENERAL_DATA_CONFIGURATION_SESSION_SimDebug_RX600_SessionRX600_E1_E20_SYSTEM]\r
+[GENERAL_DATA_CONFIGURATION_SESSION_Debug_RX600_E1_E20_SYSTEM_DefaultSession]\r
+[GENERAL_DATA_CONFIGURATION_SESSION_SimDebug_RX600_DefaultSession]\r
+[GENERAL_DATA_CONFIGURATION_SESSION_Debug_SessionRX600_E1_E20_SYSTEM]\r
+[GENERAL_DATA_CONFIGURATION_SESSION_Debug_SimSessionRX600]\r
+[GENERAL_DATA_CONFIGURATION_SESSION_SimDebug_RX600_SimSessionRX600]\r
+[GENERAL_DATA_CONFIGURATION_SESSION_Debug_with_optimisation_DefaultSession]\r
+[GENERAL_DATA_CONFIGURATION_SESSION_Blinky_SimSessionRX600]\r
+[GENERAL_DATA_CONFIGURATION_SESSION_Debug_with_optimisation_SessionRX600_E1_E20_SYSTEM]\r
+[GENERAL_DATA_SESSION_SessionRX600_E1_E20_SYSTEM]\r
+[END]\r
--- /dev/null
+/***********************************************************************/\r
+/* */\r
+/* FILE :dbsct.c */\r
+/* DATE :Wed, Aug 11, 2010 */\r
+/* DESCRIPTION :Setting of B,R Section */\r
+/* CPU TYPE :Other */\r
+/* */\r
+/* This file is generated by Renesas Project Generator (Ver.4.50). */\r
+/* NOTE:THIS IS A TYPICAL EXAMPLE. */\r
+/* */\r
+/***********************************************************************/\r
+ \r
+\r
+/*********************************************************************\r
+*\r
+* Device : RX\r
+*\r
+* File Name : dbsct.c\r
+*\r
+* Abstract : Setting of B,R Section.\r
+*\r
+* History : 1.00 (2009-08-07)\r
+*\r
+* NOTE : THIS IS A TYPICAL EXAMPLE.\r
+*\r
+* Copyright(c) 2009 Renesas Technology Corp.\r
+* And Renesas Solutions Corp.,All Rights Reserved. \r
+*\r
+*********************************************************************/\r
+\r
+#include "typedefine.h"\r
+\r
+#pragma unpack\r
+\r
+#pragma section C C$DSEC\r
+extern const struct {\r
+ _UBYTE *rom_s; /* Start address of the initialized data section in ROM */\r
+ _UBYTE *rom_e; /* End address of the initialized data section in ROM */\r
+ _UBYTE *ram_s; /* Start address of the initialized data section in RAM */\r
+} _DTBL[] = {\r
+ { __sectop("D"), __secend("D"), __sectop("R") },\r
+ { __sectop("D_2"), __secend("D_2"), __sectop("R_2") },\r
+ { __sectop("D_1"), __secend("D_1"), __sectop("R_1") }\r
+};\r
+#pragma section C C$BSEC\r
+extern const struct {\r
+ _UBYTE *b_s; /* Start address of non-initialized data section */\r
+ _UBYTE *b_e; /* End address of non-initialized data section */\r
+} _BTBL[] = {\r
+ { __sectop("B"), __secend("B") },\r
+ { __sectop("B_2"), __secend("B_2") },\r
+ { __sectop("B_1"), __secend("B_1") }\r
+};\r
+\r
+#pragma section\r
+\r
+/*\r
+** CTBL prevents excessive output of L1100 messages when linking.\r
+** Even if CTBL is deleted, the operation of the program does not change.\r
+*/\r
+_UBYTE * const _CTBL[] = {\r
+ __sectop("C_1"), __sectop("C_2"), __sectop("C"),\r
+ __sectop("W_1"), __sectop("W_2"), __sectop("W")\r
+};\r
+\r
+#pragma packoption\r
--- /dev/null
+/******************************************************************************\r
+* DISCLAIMER\r
+\r
+* This software is supplied by Renesas Technology Corp. and is only \r
+* intended for use with Renesas products. No other uses are authorized.\r
+\r
+* This software is owned by Renesas Technology Corp. and is protected under \r
+* all applicable laws, including copyright laws.\r
+\r
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES\r
+* REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, \r
+* INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A \r
+* PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY \r
+* DISCLAIMED.\r
+\r
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS \r
+* TECHNOLOGY CORP. NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE \r
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES \r
+* FOR ANY REASON RELATED TO THE THIS SOFTWARE, EVEN IF RENESAS OR ITS \r
+* AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
+\r
+* Renesas reserves the right, without notice, to make changes to this \r
+* software and to discontinue the availability of this software. \r
+* By using this software, you agree to the additional terms and \r
+* conditions found by accessing the following link:\r
+* http://www.renesas.com/disclaimer\r
+******************************************************************************\r
+* Copyright (C) 2008. Renesas Technology Corp., All Rights Reserved.\r
+******************************************************************************* \r
+* File Name : hwsetup.c\r
+* Version : 1.00\r
+* Description : Power up hardware initializations\r
+******************************************************************************\r
+* History : DD.MM.YYYY Version Description\r
+* : 15.02.2010 1.00 First Release\r
+******************************************************************************/\r
+\r
+\r
+/******************************************************************************\r
+Includes <System Includes> , "Project Includes"\r
+******************************************************************************/\r
+#include <stdint.h>\r
+#include "iodefine.h"\r
+#include "yrdkrx62ndef.h"\r
+// #include "lcd.h" Uncomment this if an LCD is present.\r
+\r
+/******************************************************************************\r
+Typedef definitions\r
+******************************************************************************/\r
+\r
+/******************************************************************************\r
+Macro definitions\r
+******************************************************************************/\r
+\r
+/******************************************************************************\r
+Imported global variables and functions (from other files)\r
+******************************************************************************/\r
+\r
+/******************************************************************************\r
+Exported global variables and functions (to be accessed by other files)\r
+******************************************************************************/\r
+\r
+/******************************************************************************\r
+Private global variables and functions\r
+******************************************************************************/\r
+\r
+/******************************************************************************\r
+* Function Name: HardwareSetup\r
+* Description : This function does initial setting for CPG port pins used in\r
+* : the Demo including the MII pins of the Ethernet PHY connection.\r
+* Arguments : none\r
+* Return Value : none\r
+******************************************************************************/\r
+void HardwareSetup(void)\r
+{\r
+\r
+ uint32_t sckcr = 0;\r
+\r
+ /* Configure system clocks based on header */\r
+ sckcr += (ICLK_MUL==8) ? (0ul << 24) : (ICLK_MUL==4) ? (1ul << 24) : (ICLK_MUL==2) ? (2ul << 24) : (3ul << 24);\r
+ sckcr += (BCLK_MUL==8) ? (0ul << 16) : (BCLK_MUL==4) ? (1ul << 16) : (BCLK_MUL==2) ? (2ul << 16) : (3ul << 16);\r
+ sckcr += (PCLK_MUL==8) ? (0ul << 8) : (PCLK_MUL==4) ? (1ul << 8) : (PCLK_MUL==2) ? (2ul << 8) : (3ul << 8);\r
+ SYSTEM.SCKCR.LONG = sckcr;\r
+\r
+ /* Configure LED pins as outputs */\r
+ LED0_DDR = 1; \r
+ LED1_DDR = 1;\r
+ LED2_DDR = 1;\r
+ LED3_DDR = 1;\r
+ LED4_DDR = 1;\r
+ LED5_DDR = 1;\r
+ LED6_DDR = 1;\r
+ LED7_DDR = 1;\r
+ LED8_DDR = 1;\r
+ LED9_DDR = 1;\r
+ LED10_DDR = 1;\r
+ LED11_DDR = 1;\r
+ \r
+ /* Configure LCD pins as outputs - uncomment this if an LCD is present.\r
+ LCD_RS_DDR = 1;\r
+ LCD_EN_DDR = 1;\r
+ LCD_DATA_DDR = 0xF0; */\r
+\r
+ /* Initialize display - uncomment this if an LCD is present.\r
+ InitialiseDisplay(); */\r
+}\r
+\r
--- /dev/null
+/***********************************************************************/\r
+/* */\r
+/* FILE :intprg.c */\r
+/* DATE :Wed, Aug 11, 2010 */\r
+/* DESCRIPTION :Interrupt Program */\r
+/* CPU TYPE :Other */\r
+/* */\r
+/* This file is generated by Renesas Project Generator (Ver.4.50). */\r
+/* NOTE:THIS IS A TYPICAL EXAMPLE. */\r
+/* */\r
+/***********************************************************************/\r
+ \r
+\r
+\r
+/*********************************************************************\r
+*\r
+* Device : RX/RX600\r
+*\r
+* File Name : intprg.c\r
+*\r
+* Abstract : Interrupt Program.\r
+*\r
+* History : 1.00 (2009-08-07)\r
+*\r
+* NOTE : THIS IS A TYPICAL EXAMPLE.\r
+*\r
+* Copyright(c) 2009 Renesas Technology Corp.\r
+* And Renesas Solutions Corp.,All Rights Reserved. \r
+*\r
+*********************************************************************/\r
+\r
+#include <machine.h>\r
+#include "vect.h"\r
+#pragma section IntPRG\r
+\r
+// Exception(Supervisor Instruction)\r
+void Excep_SuperVisorInst(void){/* brk(); */}\r
+\r
+// Exception(Undefined Instruction)\r
+void Excep_UndefinedInst(void){/* brk(); */}\r
+\r
+// Exception(Floating Point)\r
+void Excep_FloatingPoint(void){/* brk(); */}\r
+\r
+// NMI\r
+void NonMaskableInterrupt(void){/* brk(); */}\r
+\r
+// Dummy\r
+void Dummy(void){/* brk(); */}\r
+\r
+// BRK\r
+void Excep_BRK(void){ wait(); }\r
+\r
--- /dev/null
+\r
+; Comment out the orginal code\r
+ .IF 0 \r
+\r
+;------------------------------------------------------------------------\r
+; |\r
+; FILE :lowlvl.src |\r
+; DATE :Wed, Jun 16, 2010 |\r
+; DESCRIPTION :Program of Low level |\r
+; CPU TYPE :Other |\r
+; |\r
+; This file is generated by Renesas Project Generator (Ver.4.50). |\r
+; NOTE:THIS IS A TYPICAL EXAMPLE. |\r
+; |\r
+;------------------------------------------------------------------------\r
+ \r
+\r
+ .GLB _charput\r
+ .GLB _charget\r
+\r
+SIM_IO .EQU 0h\r
+\r
+ .SECTION P,CODE\r
+;-----------------------------------------------------------------------\r
+; _charput:\r
+;-----------------------------------------------------------------------\r
+_charput:\r
+ MOV.L #IO_BUF,R2\r
+ MOV.B R1,[R2]\r
+ MOV.L #1220000h,R1\r
+ MOV.L #PARM,R3\r
+ MOV.L R2,[R3]\r
+ MOV.L R3,R2\r
+ MOV.L #SIM_IO,R3\r
+ JSR R3\r
+ RTS\r
+\r
+;-----------------------------------------------------------------------\r
+; _charget:\r
+;----------------------------------------------------------------------- \r
+_charget:\r
+ MOV.L #1210000h,R1\r
+ MOV.L #IO_BUF,R2\r
+ MOV.L #PARM,R3\r
+ MOV.L R2,[R3]\r
+ MOV.L R3,R2\r
+ MOV.L #SIM_IO,R3\r
+ JSR R3\r
+ MOV.L #IO_BUF,R2\r
+ MOVU.B [R2],R1\r
+ RTS\r
+\r
+;-----------------------------------------------------------------------\r
+; I/O Buffer\r
+;-----------------------------------------------------------------------\r
+ .SECTION B,DATA,ALIGN=4\r
+PARM: .BLKL 1\r
+ .SECTION B_1,DATA\r
+IO_BUF: .BLKB 1\r
+; .END ; Commented out for conditional assembly\r
+\r
+; Code below is for debug console\r
+ .ELSE \r
+\r
+;-----------------------------------------------------------------------\r
+;\r
+; FILE :lowlvl.src\r
+; DATE :Wed, Jul 01, 2009\r
+; DESCRIPTION :Program of Low level\r
+; CPU TYPE :RX\r
+;\r
+;-----------------------------------------------------------------------\r
+ .GLB _charput\r
+ .GLB _charget\r
+\r
+FC2E0 .EQU 00084080h\r
+FE2C0 .EQU 00084090h\r
+DBGSTAT .EQU 000840C0h\r
+RXFL0EN .EQU 00001000h\r
+TXFL0EN .EQU 00000100h\r
+\r
+ .SECTION P,CODE\r
+\r
+;-----------------------------------------------------------------------\r
+; _charput:\r
+;-----------------------------------------------------------------------\r
+_charput:\r
+ .STACK _charput = 00000000h\r
+__C2ESTART: MOV.L #TXFL0EN,R3\r
+ MOV.L #DBGSTAT,R4\r
+__TXLOOP: MOV.L [R4],R5\r
+ AND R3,R5\r
+ BNZ __TXLOOP\r
+__WRITEFC2E0: MOV.L #FC2E0,R2\r
+ MOV.L R1,[R2]\r
+__CHARPUTEXIT: RTS\r
+\r
+;-----------------------------------------------------------------------\r
+; _charget:\r
+;-----------------------------------------------------------------------\r
+_charget:\r
+ .STACK _charget = 00000000h\r
+__E2CSTART: MOV.L #RXFL0EN,R3\r
+ MOV.L #DBGSTAT,R4\r
+__RXLOOP: MOV.L [R4],R5\r
+ AND R3,R5\r
+ BZ __RXLOOP\r
+__READFE2C0: MOV.L #FE2C0,R2\r
+ MOV.L [R2],R1\r
+__CHARGETEXIT: RTS\r
+\r
+;-----------------------------------------------------------------------\r
+\r
+; End of conditional code\r
+ .ENDIF \r
+\r
+ .END\r
+\r
+\r
+\r
--- /dev/null
+/***********************************************************************/\r
+/* */\r
+/* FILE :lowsrc.c */\r
+/* DATE :Wed, Jun 16, 2010 */\r
+/* DESCRIPTION :Program of I/O Stream */\r
+/* CPU TYPE :Other */\r
+/* */\r
+/* This file is generated by Renesas Project Generator (Ver.4.50). */\r
+/* NOTE:THIS IS A TYPICAL EXAMPLE. */\r
+/* */\r
+/***********************************************************************/\r
+ \r
+\r
+\r
+/*********************************************************************\r
+*\r
+* Device : RX\r
+*\r
+* File Name : lowsrc.c\r
+*\r
+* Abstract : Program of I/O Stream.\r
+*\r
+* History : 1.00 (2009-08-07)\r
+*\r
+* NOTE : THIS IS A TYPICAL EXAMPLE.\r
+*\r
+* Copyright(c) 2009 Renesas Technology Corp.\r
+* And Renesas Solutions Corp.,All Rights Reserved. \r
+*\r
+*********************************************************************/\r
+\r
+#include <string.h>\r
+#include <stdio.h>\r
+#include <stddef.h>\r
+#include "lowsrc.h"\r
+\r
+/* file number */\r
+#define STDIN 0 /* Standard input (console) */\r
+#define STDOUT 1 /* Standard output (console) */\r
+#define STDERR 2 /* Standard error output (console) */\r
+\r
+#define FLMIN 0 /* Minimum file number */\r
+#define _MOPENR 0x1\r
+#define _MOPENW 0x2\r
+#define _MOPENA 0x4\r
+#define _MTRUNC 0x8\r
+#define _MCREAT 0x10\r
+#define _MBIN 0x20\r
+#define _MEXCL 0x40\r
+#define _MALBUF 0x40\r
+#define _MALFIL 0x80\r
+#define _MEOF 0x100\r
+#define _MERR 0x200\r
+#define _MLBF 0x400\r
+#define _MNBF 0x800\r
+#define _MREAD 0x1000\r
+#define _MWRITE 0x2000\r
+#define _MBYTE 0x4000\r
+#define _MWIDE 0x8000\r
+/* File Flags */\r
+#define O_RDONLY 0x0001 /* Read only */\r
+#define O_WRONLY 0x0002 /* Write only */\r
+#define O_RDWR 0x0004 /* Both read and Write */\r
+#define O_CREAT 0x0008 /* A file is created if it is not existed */\r
+#define O_TRUNC 0x0010 /* The file size is changed to 0 if it is existed. */\r
+#define O_APPEND 0x0020 /* The position is set for next reading/writing */\r
+ /* 0: Top of the file 1: End of file */\r
+\r
+/* Special character code */\r
+#define CR 0x0d /* Carriage return */\r
+#define LF 0x0a /* Line feed */\r
+\r
+#if defined( __RX )\r
+const long _nfiles = IOSTREAM; /* The number of files for input/output files */\r
+#else\r
+const int _nfiles = IOSTREAM; /* The number of files for input/output files */\r
+#endif\r
+char flmod[IOSTREAM]; /* The location for the mode of opened file. */\r
+\r
+unsigned char sml_buf[IOSTREAM];\r
+\r
+#define FPATH_STDIN "C:\\stdin"\r
+#define FPATH_STDOUT "C:\\stdout"\r
+#define FPATH_STDERR "C:\\stderr"\r
+\r
+/* H8 Normal mode ,SH and RX */\r
+#if defined( __2000N__ ) || defined( __2600N__ ) || defined( __300HN__ ) || defined( _SH )\r
+/* Output one character to standard output */\r
+extern void charput(char);\r
+/* Input one character from standard input */\r
+extern char charget(void);\r
+/* Output one character to the file */\r
+extern char fcharput(char, unsigned char);\r
+/* Input one character from the file */\r
+extern char fcharget(char*, unsigned char);\r
+/* Open the file */\r
+extern char fileopen(char*, unsigned char, unsigned char*);\r
+/* Close the file */\r
+extern char fileclose(unsigned char);\r
+/* Move the file offset */\r
+extern char fpseek(unsigned char, long, unsigned char);\r
+/* Get the file offset */\r
+extern char fptell(unsigned char, long*);\r
+\r
+/* RX */\r
+#elif defined( __RX )\r
+/* Output one character to standard output */\r
+extern void charput(unsigned char);\r
+/* Input one character from standard input */\r
+extern unsigned char charget(void);\r
+\r
+/* H8 Advanced mode */\r
+#elif defined( __2000A__ ) || defined( __2600A__ ) || defined( __300HA__ ) || defined( __H8SXN__ ) || defined( __H8SXA__ ) || defined( __H8SXM__ ) || defined( __H8SXX__ )\r
+/* Output one character to standard output */\r
+extern void charput(char);\r
+/* Input one character from standard input */\r
+extern char charget(void);\r
+/* Output one character to the file */\r
+extern char fcharput(char, unsigned char);\r
+/* Input one character from the file */\r
+extern char fcharget(char*, unsigned char);\r
+/* Open the file */\r
+/* Specified as the number of register which stored paramter is 3 */\r
+extern char __regparam3 fileopen(char*, unsigned char, unsigned char*);\r
+/* Close the file */\r
+extern char fileclose(unsigned char);\r
+/* Move the file offset */\r
+extern char fpseek(unsigned char, long, unsigned char);\r
+/* Get the file offset */\r
+extern char fptell(unsigned char, long*);\r
+\r
+/* H8300 and H8300L */\r
+#elif defined( __300__ ) || defined( __300L__ )\r
+/* Output one character to standard output */\r
+extern void charput(char);\r
+/* Input one character from standard input */\r
+extern char charget(void);\r
+/* Output one character to the file */\r
+extern char fcharput(char, unsigned char);\r
+/* Input one character from the file */\r
+extern char fcharget(char*, unsigned char);\r
+/* Open the file */\r
+/* Specified as the number of register which stored paramter is 3 */\r
+extern char __regparam3 fileopen(char*, unsigned char, unsigned char*);\r
+/* Close the file */\r
+extern char fileclose(unsigned char);\r
+/* Move the file offset */\r
+/* Move the file offset */\r
+extern char __regparam3 fpseek(unsigned char, long, unsigned char);\r
+/* Get the file offset */\r
+extern char fptell(unsigned char, long*);\r
+#endif\r
+\r
+#include <stdio.h>\r
+FILE *_Files[IOSTREAM]; // structure for FILE\r
+char *env_list[] = { // Array for environment variables(**environ)\r
+ "ENV1=temp01",\r
+ "ENV2=temp02",\r
+ "ENV9=end",\r
+ '\0' // Terminal for environment variables\r
+};\r
+\r
+char **environ = env_list;\r
+\r
+/****************************************************************************/\r
+/* _INIT_IOLIB */\r
+/* Initialize C library Functions, if necessary. */\r
+/* Define USES_SIMIO on Assembler Option. */\r
+/****************************************************************************/\r
+void _INIT_IOLIB( void )\r
+{\r
+ /* A file for standard input/output is opened or created. Each FILE */\r
+ /* structure members are initialized by the library. Each _Buf member */\r
+ /* in it is re-set the end of buffer pointer. */\r
+\r
+ /* Standard Input File */\r
+ if( freopen( FPATH_STDIN, "r", stdin ) == NULL )\r
+ stdin->_Mode = 0xffff; /* Not allow the access if it fails to open */\r
+ stdin->_Mode = _MOPENR; /* Read only attribute */\r
+ stdin->_Mode |= _MNBF; /* Non-buffering for data */\r
+ stdin->_Bend = stdin->_Buf + 1; /* Re-set pointer to the end of buffer */\r
+\r
+ /* Standard Output File */\r
+ if( freopen( FPATH_STDOUT, "w", stdout ) == NULL ) \r
+ stdout->_Mode = 0xffff; /* Not allow the access if it fails to open */\r
+ stdout->_Mode |= _MNBF; /* Non-buffering for data */\r
+ stdout->_Bend = stdout->_Buf + 1;/* Re-set pointer to the end of buffer */\r
+ \r
+ /* Standard Error File */\r
+ if( freopen( FPATH_STDERR, "w", stderr ) == NULL )\r
+ stderr->_Mode = 0xffff; /* Not allow the access if it fails to open */\r
+ stderr->_Mode |= _MNBF; /* Non-buffering for data */\r
+ stderr->_Bend = stderr->_Buf + 1;/* Re-set pointer to the end of buffer */\r
+}\r
+\r
+/****************************************************************************/\r
+/* _CLOSEALL */\r
+/****************************************************************************/\r
+void _CLOSEALL( void )\r
+{\r
+ long i;\r
+\r
+ for( i=0; i < _nfiles; i++ )\r
+ {\r
+ /* Checks if the file is opened or not */\r
+ if( _Files[i]->_Mode & (_MOPENR | _MOPENW | _MOPENA ) )\r
+ fclose( _Files[i] ); /* Closes the file */\r
+ }\r
+}\r
+\r
+/**************************************************************************/\r
+/* open:file open */\r
+/* Return value:File number (Pass) */\r
+/* -1 (Failure) */\r
+/**************************************************************************/\r
+#if defined( __RX )\r
+long open(const char *name, /* File name */\r
+ long mode, /* Open mode */\r
+ long flg) /* Open flag */\r
+#else\r
+int open(char *name, /* File name */\r
+ int mode, /* Open mode */\r
+ int flg) /* Open flag */\r
+#endif\r
+{\r
+\r
+\r
+ if( strcmp( name, FPATH_STDIN ) == 0 ) /* Standard Input file? */\r
+ {\r
+ if( ( mode & O_RDONLY ) == 0 ) return -1;\r
+ flmod[STDIN] = mode;\r
+ return STDIN;\r
+ }\r
+ else if( strcmp( name, FPATH_STDOUT ) == 0 )/* Standard Output file? */\r
+ {\r
+ if( ( mode & O_WRONLY ) == 0 ) return -1;\r
+ flmod[STDOUT] = mode;\r
+ return STDOUT;\r
+ }\r
+ else if(strcmp(name, FPATH_STDERR ) == 0 ) /* Standard Error file? */\r
+ {\r
+ if( ( mode & O_WRONLY ) == 0 ) return -1;\r
+ flmod[STDERR] = mode;\r
+ return STDERR;\r
+ }\r
+ else return -1; /*Others */\r
+}\r
+\r
+#if defined( __RX )\r
+long close( long fileno )\r
+#else\r
+int close( int fileno )\r
+#endif\r
+{\r
+ return 1;\r
+}\r
+\r
+/**************************************************************************/\r
+/* write:Data write */\r
+/* Return value:Number of write characters (Pass) */\r
+/* -1 (Failure) */\r
+/**************************************************************************/\r
+#if defined( __RX )\r
+long write(long fileno, /* File number */\r
+ const unsigned char *buf, /* The address of destination buffer */\r
+ long count) /* The number of chacter to write */\r
+#else\r
+int write(int fileno, /* File number */\r
+ char *buf, /* The address of destination buffer */\r
+ int count) /* The number of chacter to write */\r
+#endif\r
+{\r
+ long i; /* A variable for counter */\r
+ unsigned char c; /* An output character */\r
+\r
+ /* Checking the mode of file , output each character */\r
+ /* Checking the attribute for Write-Only, Read-Only or Read-Write */\r
+ if(flmod[fileno]&O_WRONLY || flmod[fileno]&O_RDWR)\r
+ {\r
+ if( fileno == STDIN ) return -1; /* Standard Input */\r
+ else if( (fileno == STDOUT) || (fileno == STDERR) ) \r
+ /* Standard Error/output */\r
+ {\r
+ for( i = count; i > 0; --i )\r
+ {\r
+ c = *buf++;\r
+ charput(c);\r
+ }\r
+ return count; /*Return the number of written characters */\r
+ }\r
+ else return -1; /* Incorrect file number */\r
+ }\r
+ else return -1; /* An error */\r
+}\r
+\r
+#if defined( __RX )\r
+long read( long fileno, unsigned char *buf, long count )\r
+#else\r
+int read( int fileno, char *buf, unsigned int count )\r
+#endif\r
+{\r
+ long i;\r
+\r
+ /* Checking the file mode with the file number, each character is input and stored the buffer */\r
+\r
+ if((flmod[fileno]&_MOPENR) || (flmod[fileno]&O_RDWR)){\r
+ for(i = count; i > 0; i--){\r
+ *buf = charget();\r
+ if(*buf==CR){ /* Replace the new line character */\r
+ *buf = LF;\r
+ }\r
+ buf++;\r
+ }\r
+ return count;\r
+ }\r
+ else {\r
+ return -1;\r
+ }\r
+}\r
+\r
+#if defined( __RX )\r
+long lseek( long fileno, long offset, long base )\r
+#else\r
+long lseek( int fileno, long offset, int base )\r
+#endif\r
+{\r
+ return -1L;\r
+}\r
+\r
--- /dev/null
+/***********************************************************************/\r
+/* */\r
+/* FILE :resetprg.c */\r
+/* DATE :Wed, Aug 11, 2010 */\r
+/* DESCRIPTION :Reset Program */\r
+/* CPU TYPE :Other */\r
+/* */\r
+/* This file is generated by Renesas Project Generator (Ver.4.50). */\r
+/* NOTE:THIS IS A TYPICAL EXAMPLE. */\r
+/* */\r
+/***********************************************************************/\r
+ \r
+\r
+\r
+/*********************************************************************\r
+*\r
+* Device : RX/RX600\r
+*\r
+* File Name : resetprg.c\r
+*\r
+* Abstract : Reset Program.\r
+*\r
+* History : 1.00 (2009-08-07)\r
+*\r
+* NOTE : THIS IS A TYPICAL EXAMPLE.\r
+*\r
+* Copyright(c) 2009 Renesas Technology Corp.\r
+* And Renesas Solutions Corp.,All Rights Reserved. \r
+*\r
+*********************************************************************/\r
+\r
+#include <machine.h>\r
+#include <_h_c_lib.h>\r
+//#include <stddef.h> // Remove the comment when you use errno\r
+//#include <stdlib.h> // Remove the comment when you use rand()\r
+#include "typedefine.h"\r
+#include "stacksct.h"\r
+\r
+#pragma inline_asm Change_PSW_PM_to_UserMode\r
+static void Change_PSW_PM_to_UserMode(void);\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+void PowerON_Reset_PC(void);\r
+void main(void);\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#ifdef __cplusplus // Use SIM I/O\r
+extern "C" {\r
+#endif\r
+extern void _INIT_IOLIB(void);\r
+extern void _CLOSEALL(void);\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#define PSW_init 0x00010000\r
+#define FPSW_init 0x00000100\r
+\r
+//extern void srand(_UINT); // Remove the comment when you use rand()\r
+//extern _SBYTE *_s1ptr; // Remove the comment when you use strtok()\r
+ \r
+//#ifdef __cplusplus // Use Hardware Setup\r
+//extern "C" {\r
+//#endif\r
+//extern void HardwareSetup(void);\r
+//#ifdef __cplusplus\r
+//}\r
+//#endif\r
+ \r
+//#ifdef __cplusplus // Remove the comment when you use global class object\r
+//extern "C" { // Sections C$INIT and C$END will be generated\r
+//#endif\r
+//extern void _CALL_INIT(void);\r
+//extern void _CALL_END(void);\r
+//#ifdef __cplusplus\r
+//}\r
+//#endif\r
+\r
+#pragma section ResetPRG\r
+\r
+#pragma entry PowerON_Reset_PC\r
+\r
+void PowerON_Reset_PC(void)\r
+{ \r
+ set_intb((unsigned long)__sectop("C$VECT"));\r
+ set_fpsw(FPSW_init);\r
+\r
+ _INITSCT();\r
+\r
+// _INIT_IOLIB(); // Use SIM I/O\r
+\r
+// errno=0; // Remove the comment when you use errno\r
+// srand((_UINT)1); // Remove the comment when you use rand()\r
+// _s1ptr=NULL; // Remove the comment when you use strtok()\r
+ \r
+// HardwareSetup(); // Use Hardware Setup\r
+ nop();\r
+\r
+// _CALL_INIT(); // Remove the comment when you use global class object\r
+\r
+ set_psw(PSW_init); // Set Ubit & Ibit for PSW\r
+// Change_PSW_PM_to_UserMode(); // Change PSW PMbit (SuperVisor->User)\r
+ ( void ) Change_PSW_PM_to_UserMode;\r
+\r
+ main();\r
+\r
+ _CLOSEALL(); // Use SIM I/O\r
+ \r
+// _CALL_END(); // Remove the comment when you use global class object\r
+\r
+ brk();\r
+}\r
+\r
+static void Change_PSW_PM_to_UserMode(void)\r
+{\r
+ MVFC PSW,R1\r
+ OR #00100000h,R1\r
+ PUSH.L R1\r
+ MVFC PC,R1\r
+ ADD #10,R1\r
+ PUSH.L R1\r
+ RTE\r
+ NOP\r
+ NOP\r
+}\r
--- /dev/null
+#include <stddef.h>\r
+#include <stdio.h>\r
+#define HEAPSIZE 0x400\r
+signed char *sbrk( size_t size );\r
+union HEAP_TYPE\r
+{\r
+ signed long dummy;\r
+ signed char heap[HEAPSIZE];\r
+};\r
+static union HEAP_TYPE heap_area;\r
+\r
+/* End address allocated by sbrk */\r
+static signed char *brk = ( signed char * ) &heap_area;\r
+signed char *sbrk( size_t size )\r
+{\r
+ signed char *p;\r
+ if( brk + size > heap_area.heap + HEAPSIZE )\r
+ {\r
+ p = ( signed char * ) - 1;\r
+ }\r
+ else\r
+ {\r
+ p = brk;\r
+ brk += size;\r
+ }\r
+\r
+ return p;\r
+}\r
--- /dev/null
+/***********************************************************************/\r
+/* */\r
+/* FILE :vecttbl.c */\r
+/* DATE :Wed, Aug 11, 2010 */\r
+/* DESCRIPTION :Initialize of Vector Table */\r
+/* CPU TYPE :Other */\r
+/* */\r
+/* This file is generated by Renesas Project Generator (Ver.4.50). */\r
+/* NOTE:THIS IS A TYPICAL EXAMPLE. */\r
+/* */\r
+/***********************************************************************/\r
+ \r
+\r
+\r
+/*********************************************************************\r
+*\r
+* Device : RX/RX600\r
+*\r
+* File Name : vecttbl.c\r
+*\r
+* Abstract : Initialize of Vector Table.\r
+*\r
+* History : 1.00 (2009-08-07)\r
+*\r
+* NOTE : THIS IS A TYPICAL EXAMPLE.\r
+*\r
+* Copyright(c) 2009 Renesas Technology Corp.\r
+* And Renesas Solutions Corp.,All Rights Reserved. \r
+*\r
+*********************************************************************/\r
+\r
+#include "vect.h"\r
+\r
+#pragma section C FIXEDVECT\r
+\r
+void* const Fixed_Vectors[] = {\r
+//;0xffffffd0 Exception(Supervisor Instruction)\r
+ (void*) Excep_SuperVisorInst,\r
+//;0xffffffd4 Reserved\r
+ Dummy,\r
+//;0xffffffd8 Reserved\r
+ Dummy,\r
+//;0xffffffdc Exception(Undefined Instruction)\r
+ (void*) Excep_UndefinedInst,\r
+//;0xffffffe0 Reserved\r
+ Dummy,\r
+//;0xffffffe4 Exception(Floating Point)\r
+ (void*) Excep_FloatingPoint,\r
+//;0xffffffe8 Reserved\r
+ Dummy,\r
+//;0xffffffec Reserved\r
+ Dummy,\r
+//;0xfffffff0 Reserved\r
+ Dummy,\r
+//;0xfffffff4 Reserved\r
+ Dummy,\r
+//;0xfffffff8 NMI\r
+ (void*) NonMaskableInterrupt,\r
+//;0xfffffffc RESET\r
+//;<<VECTOR DATA START (POWER ON RESET)>>\r
+//;Power On Reset PC\r
+PowerON_Reset_PC \r
+//;<<VECTOR DATA END (POWER ON RESET)>>\r
+};\r
--- /dev/null
+[HIMDBVersion]\r
+2.0\r
+[DATABASE_VERSION]\r
+"2.3" \r
+[SESSION_DETAILS]\r
+"" \r
+[INFORMATION]\r
+"" \r
+[GENERAL_DATA]\r
+"FIRST_CONNECTION_TAG" "NO" \r
+"MRULABELS_DATAMANAGER_KEY" "00000000|FFFFFFFF|88218|000870B4|000870AE|88204|88208|18b8" \r
+"RESET_CPU_AFTER_DOWNLOAD_TAG" "VARIANT_TRUE_STORE_TAG" \r
+"{228DB593-0AB2-4EBE-A098-A2CABF094E46}RamMonitorCtrlViews" "0" \r
+"{287A8023-99B5-49E1-A54E-4DDCA43D7959}MapCtrlECX_MAP_FIND_SYMBOL_LIST" "" \r
+"{287A8023-99B5-49E1-A54E-4DDCA43D7959}MapCtrlViews" "0" \r
+"{2BA6A3EE-6488-11D5-80D4-00C04F68EAD7}ECXLABEL_ADDDLG_ADDR" "" \r
+"{2BA6A3EE-6488-11D5-80D4-00C04F68EAD7}LabelCtrlSymbolFileDir" "" \r
+"{2BA6A3EE-6488-11D5-80D4-00C04F68EAD7}LabelCtrlSymbolFileName" "" \r
+"{2BA6A3EE-6488-11D5-80D4-00C04F68EAD7}LabelCtrlViews" "0" \r
+"{2BA6A3EF-6488-11D5-80D4-00C04F68EAD7}StatusCtrlViews" "0" \r
+"{313F4FC1-6566-11D5-8BBE-0004E2013C71}CmdLineCtrlBatchFileName" "" \r
+"{313F4FC1-6566-11D5-8BBE-0004E2013C71}CmdLineCtrlBreakpointFlag" "-1 " \r
+"{313F4FC1-6566-11D5-8BBE-0004E2013C71}CmdLineCtrlBreakpointStatus" "-1 " \r
+"{313F4FC1-6566-11D5-8BBE-0004E2013C71}CmdLineCtrlBrowseDirectory" "" \r
+"{313F4FC1-6566-11D5-8BBE-0004E2013C71}CmdLineCtrlLogFileName" "" \r
+"{313F4FC1-6566-11D5-8BBE-0004E2013C71}CmdLineCtrlSplitterPosition" "242" \r
+"{313F4FC1-6566-11D5-8BBE-0004E2013C71}CmdLineCtrlViews" "1" \r
+"{313F4FC1-6566-11D5-8BBE-0004E2013C71}CmdLineCtrlWindowProperties" "17" \r
+"{313F4FC1-6566-11D5-8BBE-0004E2013C71}CmdLineWndInstanceKey0" "{WK_00000001_CmdLine}" \r
+"{313F4FC1-6566-11D5-8BBE-0004E2013C71}TclTkCtrlLogFileName" "" \r
+"{313F4FC2-6566-11D5-8BBE-0004E2013C71}ECX_MEMORY_COMPARE_END_ADDRESS" "" \r
+"{313F4FC2-6566-11D5-8BBE-0004E2013C71}ECX_MEMORY_COMPARE_START_ADDRESS" "" \r
+"{313F4FC2-6566-11D5-8BBE-0004E2013C71}ECX_MEMORY_DISPLAY_DEST_ADDRESS" "88218" \r
+"{313F4FC2-6566-11D5-8BBE-0004E2013C71}ECX_MEMORY_DISPLAY_END_ADDRESS" "FFFFFFFF" \r
+"{313F4FC2-6566-11D5-8BBE-0004E2013C71}ECX_MEMORY_DISPLAY_START_ADDRESS" "00000000" \r
+"{313F4FC2-6566-11D5-8BBE-0004E2013C71}ECX_MEMORY_FILL_END_ADDRESS" "" \r
+"{313F4FC2-6566-11D5-8BBE-0004E2013C71}ECX_MEMORY_FILL_START_ADDRESS" "" \r
+"{313F4FC2-6566-11D5-8BBE-0004E2013C71}ECX_MEMORY_MOVE_END_ADDRESS" "" \r
+"{313F4FC2-6566-11D5-8BBE-0004E2013C71}ECX_MEMORY_MOVE_START_ADDRESS" "" \r
+"{313F4FC2-6566-11D5-8BBE-0004E2013C71}ECX_MEMORY_SEARCH_END_ADDRESS" "" \r
+"{313F4FC2-6566-11D5-8BBE-0004E2013C71}ECX_MEMORY_SEARCH_START_ADDRESS" "" \r
+"{313F4FC2-6566-11D5-8BBE-0004E2013C71}ECX_MEMORY_SET_DEST_ADDRESS" "000870B4" \r
+"{313F4FC2-6566-11D5-8BBE-0004E2013C71}ECX_MEMORY_TEST_END_ADDRESS" "" \r
+"{313F4FC2-6566-11D5-8BBE-0004E2013C71}ECX_MEMORY_TEST_START_ADDRESS" "" \r
+"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryCtrlViews" "0" \r
+"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryWndViewA0AutoRefreshEnableTopPane" "0" \r
+"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryWndViewA0AutoRefreshIntervalTopPane" "100" \r
+"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryWndViewA0DataLength" "1" \r
+"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryWndViewA0DispAddressTopPane" "553134" \r
+"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryWndViewA0DispCode" "42208" \r
+"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryWndViewA0DispColumnCount" "16" \r
+"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryWndViewA0IsDispCode" "1" \r
+"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryWndViewA0IsDispFloat" "0" \r
+"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryWndViewA0IsDispLabel" "0" \r
+"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryWndViewA0IsDispRegister" "0" \r
+"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryWndViewA0IsRegFollowEnableTopPane" "0" \r
+"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryWndViewA0LabelWidth" "96" \r
+"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryWndViewA0Radix" "16" \r
+"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryWndViewA0RegFollowRegTblIDTopPane" "0" \r
+"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryWndViewA0RegisterWidth" "96" \r
+"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryWndViewA0ScrollEndAddress" "-1" \r
+"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryWndViewA0ScrollStartAddress" "0" \r
+"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryWndViewA0StartUpSymbolTopPane" "" \r
+"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryWndViewAInstanceKey0" "{WK_00000001_MEMORY}RTOSDemoSessionRX600_E1_E20_SYSTEM" \r
+"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryWndViewB0AutoRefreshEnableTopPane" "0" \r
+"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryWndViewB0AutoRefreshIntervalTopPane" "100" \r
+"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryWndViewB0DataLength" "1" \r
+"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryWndViewB0DispAddressTopPane" "553134" \r
+"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryWndViewB0DispCode" "42208" \r
+"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryWndViewB0DispColumnCount" "16" \r
+"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryWndViewB0IsDispCode" "1" \r
+"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryWndViewB0IsDispFloat" "0" \r
+"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryWndViewB0IsDispLabel" "0" \r
+"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryWndViewB0IsDispRegister" "0" \r
+"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryWndViewB0IsRegFollowEnableTopPane" "0" \r
+"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryWndViewB0LabelWidth" "96" \r
+"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryWndViewB0Radix" "16" \r
+"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryWndViewB0RegFollowRegTblIDTopPane" "0" \r
+"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryWndViewB0RegisterWidth" "96" \r
+"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryWndViewB0ScrollEndAddress" "-1" \r
+"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryWndViewB0ScrollStartAddress" "0" \r
+"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryWndViewB0StartUpSymbolTopPane" "" \r
+"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryWndViewBInstanceKey0" "{WK_00000001_MEMORY}RTOSDemoSessionRX600_E1_E20_SYSTEMViewB" \r
+"{4F025ABC-BE66-4CB6-9CEE-06C61418278E}Trace2CtrlSaveFileDir" "" \r
+"{4F025ABC-BE66-4CB6-9CEE-06C61418278E}Trace2CtrlSaveFileName" "" \r
+"{4F025ABC-BE66-4CB6-9CEE-06C61418278E}Trace2CtrlViews" "0" \r
+"{5F75FDA0-6FF0-11D5-B7CE-00E029352378}PACtrlSaveFileDir" "" \r
+"{5F75FDA0-6FF0-11D5-B7CE-00E029352378}PACtrlSaveFileName" "" \r
+"{5F75FDA0-6FF0-11D5-B7CE-00E029352378}PACtrlViews" "0" \r
+"{64753FED-D387-4B8C-A91D-D3419C869C07}C_EVAL_DENORMAL_MODE" "16777216" \r
+"{64753FED-D387-4B8C-A91D-D3419C869C07}C_EVAL_ROUND_MODE" "768" \r
+"{64753FED-D387-4B8C-A91D-D3419C869C07}C_REGISTER_REG_0" "00000000000071F0" \r
+"{64753FED-D387-4B8C-A91D-D3419C869C07}C_REGISTER_REG_1" "0000000000006FA8" \r
+"{64753FED-D387-4B8C-A91D-D3419C869C07}C_REGISTER_REG_10" "00000000A5A5A5A5" \r
+"{64753FED-D387-4B8C-A91D-D3419C869C07}C_REGISTER_REG_11" "00000000A5A5A5A5" \r
+"{64753FED-D387-4B8C-A91D-D3419C869C07}C_REGISTER_REG_12" "00000000A5A5A5A5" \r
+"{64753FED-D387-4B8C-A91D-D3419C869C07}C_REGISTER_REG_13" "00000000A5A5A5A5" \r
+"{64753FED-D387-4B8C-A91D-D3419C869C07}C_REGISTER_REG_14" "000000000000CDBC" \r
+"{64753FED-D387-4B8C-A91D-D3419C869C07}C_REGISTER_REG_15" "0000000000006FA8" \r
+"{64753FED-D387-4B8C-A91D-D3419C869C07}C_REGISTER_REG_16" "00000000000071F0" \r
+"{64753FED-D387-4B8C-A91D-D3419C869C07}C_REGISTER_REG_17" "000000000000D354" \r
+"{64753FED-D387-4B8C-A91D-D3419C869C07}C_REGISTER_REG_18" "0000000004030001" \r
+"{64753FED-D387-4B8C-A91D-D3419C869C07}C_REGISTER_REG_19" "00000000FFF88980" \r
+"{64753FED-D387-4B8C-A91D-D3419C869C07}C_REGISTER_REG_2" "0000000000000000" \r
+"{64753FED-D387-4B8C-A91D-D3419C869C07}C_REGISTER_REG_20" "00000000FFF81644" \r
+"{64753FED-D387-4B8C-A91D-D3419C869C07}C_REGISTER_REG_21" "0000000080000000" \r
+"{64753FED-D387-4B8C-A91D-D3419C869C07}C_REGISTER_REG_22" "0000000000000000" \r
+"{64753FED-D387-4B8C-A91D-D3419C869C07}C_REGISTER_REG_23" "0000000000000000" \r
+"{64753FED-D387-4B8C-A91D-D3419C869C07}C_REGISTER_REG_24" "0000000000000100" \r
+"{64753FED-D387-4B8C-A91D-D3419C869C07}C_REGISTER_REG_25" "1234567887650000" \r
+"{64753FED-D387-4B8C-A91D-D3419C869C07}C_REGISTER_REG_3" "0000000000000000" \r
+"{64753FED-D387-4B8C-A91D-D3419C869C07}C_REGISTER_REG_4" "0000000000000001" \r
+"{64753FED-D387-4B8C-A91D-D3419C869C07}C_REGISTER_REG_5" "0000000000000000" \r
+"{64753FED-D387-4B8C-A91D-D3419C869C07}C_REGISTER_REG_6" "0000000000006A68" \r
+"{64753FED-D387-4B8C-A91D-D3419C869C07}C_REGISTER_REG_7" "00000000A5A5A5A5" \r
+"{64753FED-D387-4B8C-A91D-D3419C869C07}C_REGISTER_REG_8" "00000000A5A5A5A5" \r
+"{64753FED-D387-4B8C-A91D-D3419C869C07}C_REGISTER_REG_9" "00000000A5A5A5A5" \r
+"{64753FED-D387-4B8C-A91D-D3419C869C07}C_REGISTER_REG_COUNT" "26" \r
+"{6C4D5B81-FD67-46A9-A089-EA44DCDE47FD}RAMMonitorManagerCtrlBlockInfoFileDir" "" \r
+"{6C4D5B81-FD67-46A9-A089-EA44DCDE47FD}RAMMonitorManagerCtrlBlockInfoFileName" "" \r
+"{7943C44E-7D44-422A-9140-4CF55C88F7D3}DifferenceCtrlViews" "0" \r
+"{855C64C3-E49C-4450-9BCA-C9822566D214}OSObjectCtrlViews" "0" \r
+"{8A898260-6F1D-11D5-8EB6-00004CC34E9D}ECX_WAVE" "00000000,00000000,0,0" \r
+"{8A898260-6F1D-11D5-8EB6-00004CC34E9D}ECX_WAVE_ADDRESS_NAME" "" \r
+"{8A898260-6F1D-11D5-8EB6-00004CC34E9D}ECX_WAVE_COMB_ADDRESS" ",,,," \r
+"{8A898260-6F1D-11D5-8EB6-00004CC34E9D}ECX_WAVE_COMB_BUFFER" ",,,," \r
+"{8A898260-6F1D-11D5-8EB6-00004CC34E9D}ECX_WAVE_SAMPLING_RATE" "1000" \r
+"{8A898260-6F1D-11D5-8EB6-00004CC34E9D}WaveformCtrlViews" "0" \r
+"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegistersCtrlViews" "1" \r
+"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegistersWnd0ColumnWidth" "47,153,35" \r
+"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegistersWnd0ECX_REGISTER_COUNT" "33" \r
+"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegistersWnd0ECX_REGISTER_DISPLAYED" "1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1" \r
+"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegistersWnd0HideFLAGs" "0" \r
+"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegistersWnd0HideRadix" "0" \r
+"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegistersWnd0LastFileName" "" \r
+"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegistersWnd0RadixList" "16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,2,16,16,16,16,16,16,16," \r
+"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegistersWndInstanceKey0" "{WK_00000001_REGISTERS}RTOSDemoSessionRX600_E1_E20_SYSTEM" \r
+"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegistersWndViewB0ColumnWidth" "47,153,35" \r
+"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegistersWndViewB0ECX_REGISTER_COUNT" "33" \r
+"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegistersWndViewB0ECX_REGISTER_DISPLAYED" "1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1" \r
+"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegistersWndViewB0HideFLAGs" "0" \r
+"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegistersWndViewB0HideRadix" "0" \r
+"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegistersWndViewB0LastFileName" "" \r
+"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegistersWndViewB0RadixList" "16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,2,16,16,16,16,16,16,16," \r
+"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegistersWndViewBInstanceKey0" "{WK_00000001_REGISTERS}RTOSDemoSessionRX600_E1_E20_SYSTEMViewB" \r
+"{AC411480-6F0A-11D5-8EB6-00004CC34E9D}ECX_IMAGE_ADDRESS_NAME" "" \r
+"{AC411480-6F0A-11D5-8EB6-00004CC34E9D}ECX_IMAGE_BUFFER" "00000000,00000000,0,0" \r
+"{AC411480-6F0A-11D5-8EB6-00004CC34E9D}ECX_IMAGE_COLOR" "0,0,0,0" \r
+"{AC411480-6F0A-11D5-8EB6-00004CC34E9D}ECX_IMAGE_COMB_ADDRESS" ",,,," \r
+"{AC411480-6F0A-11D5-8EB6-00004CC34E9D}ECX_IMAGE_COMB_PALETTE" ",,,," \r
+"{AC411480-6F0A-11D5-8EB6-00004CC34E9D}ECX_IMAGE_PALETTE_NAME" "" \r
+"{AC411480-6F0A-11D5-8EB6-00004CC34E9D}ECX_IMAGE_REDRAW_CONTINUOUSLY" "0,2" \r
+"{AC411480-6F0A-11D5-8EB6-00004CC34E9D}ECX_IMAGE_SAMPLEING_RATE" "1000" \r
+"{AC411480-6F0A-11D5-8EB6-00004CC34E9D}ECX_IMAGE_VIEW" "0,0,0,0,0,0" \r
+"{AC411480-6F0A-11D5-8EB6-00004CC34E9D}ImageCtrlViews" "0" \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchCtrlViews" "4" \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd0ColWidth0" "234" \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd0ColWidth1" "190" \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd0ColWidth12" "200" \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd0ColWidth2" "120" \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd0ColWidth3" "200" \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd0ECX_WATCH_ITEM0000" "cErrorText, 10, 0, P, Col, Hex, N" \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd0ECX_WATCH_ITEM0000_SCOPE" "Current Scope," \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd0ECX_WATCH_ITEMCnt" "1" \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd1ColWidth0" "120" \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd1ColWidth1" "150" \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd1ColWidth12" "200" \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd1ColWidth2" "120" \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd1ColWidth3" "200" \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd1ECX_WATCH_ITEMCnt" "0" \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd2ColWidth0" "120" \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd2ColWidth1" "150" \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd2ColWidth12" "200" \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd2ColWidth2" "120" \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd2ColWidth3" "200" \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd2ECX_WATCH_ITEMCnt" "0" \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd3ColWidth0" "120" \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd3ColWidth1" "150" \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd3ColWidth12" "200" \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd3ColWidth2" "120" \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd3ColWidth3" "200" \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd3ECX_WATCH_ITEMCnt" "0" \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWndInitial_Radix" "0" \r
+"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWndInstanceKey0" "{WK_00000001_WATCH}RTOSDemoSessionRX600_E1_E20_SYSTEM" \r
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--- /dev/null
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--- /dev/null
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+[STATUSBAR_STATEINFO_VD3]\r
+"MasterShowState" 1 \r
+"ApplicationShowState" 1 \r
+"DebuggerShowState" 1 \r
+[STATUSBAR_STATEINFO_VD4]\r
+"MasterShowState" 1 \r
+"ApplicationShowState" 1 \r
+"DebuggerShowState" 1 \r
+[STATUSBAR_DEBUGGER_PANESTATE_VD1]\r
+[STATUSBAR_DEBUGGER_PANESTATE_VD2]\r
+[STATUSBAR_DEBUGGER_PANESTATE_VD3]\r
+[STATUSBAR_DEBUGGER_PANESTATE_VD4]\r
+[DEBUGGER_OPTIONS]\r
+"[V|VERSION|1] [S|CPUTYPE|^"Other (RX600)^"] [S|MAP|^"0x00000000,0x0001FFFF,RAM,32,0101,2 0x00080000,0x000FFFFF,I/O,32,0101,2 0x00100000,0x00107FFF,ROM,32,0101,2 0x007F8000,0x007F9FFF,RAM,32,0101,2 0x007FC000,0x007FC4FF,I/O,32,0101,2 0x007FFC00,0x007FFFFF,I/O,32,0101,2 0x00E00000,0x00FFFFFF,ROM,32,0101,2 0xFEFFE000,0xFEFFFFFF,ROM,32,0101,2 0xFF7FC000,0xFF7FFFFF,ROM,32,0101,2 0xFFE00000,0xFFFFFFFF,ROM,32,0101,2^"] [S|RESOURCE|^"0x00000000,0x0001FFFF,R/W 0x00080000,0x000FFFFF,R/W 0x007FC000,0x007FC4FF,R/W 0x007FFC00,0x007FFFFF,R/W 0xFFFF8000,0xFFFFFFFF,R/W ^"] [B|SIMIOF|0] [I|SIMIOADR|0x0] [I|BUS_MODE|0] [S|ENDIAN|^"LITTLE^"] [S|PATCH|^"OFF^"]" \r
+[DOWNLOAD_MODULES]\r
+"$(CONFIGDIR)\$(PROJECTNAME).abs" 0 "Elf/Dwarf2" 0 0 1 0 \r
+[CONNECT_ON_GO]\r
+"FALSE" \r
+[DOWNLOAD_MODULES_AFTER_BUILD]\r
+"TRUE" \r
+[REMOVE_BREAKPOINTS_ON_DOWNLOAD]\r
+"FALSE" \r
+[DISABLE_MEMORY_ACCESS_PRIOR_TO_COMMAND_FILE_EXECUTION]\r
+"FALSE" \r
+[LIMIT_DISASSEMBLY_MEMORY_ACCESS]\r
+"FALSE" \r
+[DISABLE_MEMORY_ACCESS_DURING_EXECUTION]\r
+"FALSE" \r
+[DEBUGGER_OPTIONS_PROPERTIES]\r
+"1" \r
+[COMMAND_FILES]\r
+[DEFAULT_DEBUG_FORMAT]\r
+"" \r
+[FLASH_DETAILS]\r
+"" 0 0 "" 0 "" 0 0 "" 0 0 0 0 0 0 0 "" "" "" "" "" \r
+[BREAKPOINTS]\r
+[END]\r
--- /dev/null
+/*\r
+ FreeRTOS V6.0.5 - Copyright (C) 2010 Real Time Engineers Ltd.\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * If you are: *\r
+ * *\r
+ * + New to FreeRTOS, *\r
+ * + Wanting to learn FreeRTOS or multitasking in general quickly *\r
+ * + Looking for basic training, *\r
+ * + Wanting to improve your FreeRTOS skills and productivity *\r
+ * *\r
+ * then take a look at the FreeRTOS eBook *\r
+ * *\r
+ * "Using the FreeRTOS Real Time Kernel - a Practical Guide" *\r
+ * http://www.FreeRTOS.org/Documentation *\r
+ * *\r
+ * A pdf reference manual is also available. Both are usually delivered *\r
+ * to your inbox within 20 minutes to two hours when purchased between 8am *\r
+ * and 8pm GMT (although please allow up to 24 hours in case of *\r
+ * exceptional circumstances). Thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+ ***NOTE*** The exception to the GPL is included to allow you to distribute\r
+ a combined work that includes FreeRTOS without being obliged to provide the\r
+ source code for proprietary components outside of the FreeRTOS kernel.\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT\r
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\r
+ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ more details. You should have received a copy of the GNU General Public \r
+ License and the FreeRTOS license exception along with FreeRTOS; if not it \r
+ can be viewed here: http://www.freertos.org/a00114.html and also obtained \r
+ by writing to Richard Barry, contact details for whom are available on the\r
+ FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+\r
+ http://www.FreeRTOS.org - Documentation, latest information, license and\r
+ contact details.\r
+\r
+ http://www.SafeRTOS.com - A version that is certified for use in safety\r
+ critical systems.\r
+\r
+ http://www.OpenRTOS.com - Commercial support, development, porting,\r
+ licensing and training services.\r
+*/\r
+\r
+#ifndef INT_QUEUE_TIMER_H\r
+#define INT_QUEUE_TIMER_H\r
+\r
+void vInitialiseTimerForIntQueueTest( void );\r
+portBASE_TYPE xTimer0Handler( void );\r
+portBASE_TYPE xTimer1Handler( void );\r
+\r
+#endif\r
+\r
--- /dev/null
+/********************************************************************************/\r
+/* */\r
+/* Device : RX/RX600/RX62N */\r
+/* File Name : ioedfine.h */\r
+/* Abstract : Definition of I/O Register. */\r
+/* History : V1.1 (2010-04-21) [Hardware Manual Revision : 0.50] */\r
+/* Note : This is a typical example. */\r
+/* */\r
+/* Copyright(c) 2010 Renesas Electronics Corp. */\r
+/* And Renesas Solutions Corp. ,All Rights Reserved. */\r
+/* */\r
+/********************************************************************************/\r
+/* */\r
+/* DESCRIPTION : Definition of ICU Register */\r
+/* CPU TYPE : RX62N */\r
+/* */\r
+/* Usage : IR,DTCER,IER,IPR of ICU Register */\r
+/* The following IR, DTCE, IEN, IPR macro functions simplify usage. */\r
+/* The bit access operation is "Bit_Name(interrupt source,name)". */\r
+/* A part of the name can be omitted. */\r
+/* for example : */\r
+/* IR(MTU0,TGIA0) = 0; expands to : */\r
+/* ICU.IR[114].BIT.IR = 0; */\r
+/* */\r
+/* DTCE(ICU,IRQ0) = 1; expands to : */\r
+/* ICU.DTCER[64].BIT.DTCE = 1; */\r
+/* */\r
+/* IEN(CMT0,CMI0) = 1; expands to : */\r
+/* ICU.IER[0x03].BIT.IEN4 = 1; */\r
+/* */\r
+/* IPR(MTU1,TGIA1) = 2; expands to : */\r
+/* IPR(MTU1,TGI ) = 2; // TGIA1,TGIB1 share IPR level. */\r
+/* ICU.IPR[0x53].BIT.IPR = 2; */\r
+/* */\r
+/* IPR(SCI0,ERI0) = 3; expands to : */\r
+/* IPR(SCI0, ) = 3; // SCI0 uses single IPR for all sources. */\r
+/* ICU.IPR[0x80].BIT.IPR = 3; */\r
+/* */\r
+/* Usage : #pragma interrupt Function_Identifier(vect=**) */\r
+/* The number of vector is "(interrupt source, name)". */\r
+/* for example : */\r
+/* #pragma interrupt INT_IRQ0(vect=VECT(ICU,IRQ0)) expands to : */\r
+/* #pragma interrupt INT_IRQ0(vect=64) */\r
+/* #pragma interrupt INT_CMT0_CMI0(vect=VECT(CMT0,CMI0)) expands to : */\r
+/* #pragma interrupt INT_CMT0_CMI0(vect=28) */\r
+/* #pragma interrupt INT_MTU0_TGIA0(vect=VECT(MTU0,TGIA0)) expands to : */\r
+/* #pragma interrupt INT_MTU0_TGIA0(vect=114) */\r
+/* */\r
+/* Usage : MSTPCRA,MSTPCRB,MSTPCRC of SYSTEM Register */\r
+/* The bit access operation is "MSTP(name)". */\r
+/* The name that can be used is a macro name defined with "iodefine.h". */\r
+/* for example : */\r
+/* MSTP(TMR2) = 0; // TMR2,TMR3,TMR23 expands to : */\r
+/* SYSTEM.MSTPCRA.BIT.MSTPA4 = 0; */\r
+/* MSTP(SCI0) = 0; // SCI0,SMCI0 expands to : */\r
+/* SYSTEM.MSTPCRB.BIT.MSTPB31 = 0; */\r
+/* MSTP(MTU4) = 0; // MTUA,MTU0,MTU1,MTU2,MTU3,MTU4,MTU5 expands to : */\r
+/* SYSTEM.MSTPCRA.BIT.MSTPA9 = 0; */\r
+/* MSTP(CMT3) = 0; // CMT2,CMT3 expands to : */\r
+/* SYSTEM.MSTPCRA.BIT.MSTPA14 = 0; */\r
+/* */\r
+/********************************************************************************/\r
+#ifndef __RX62NIODEFINE_HEADER__\r
+#define __RX62NIODEFINE_HEADER__\r
+#pragma bit_order left\r
+#pragma unpack\r
+struct st_system {\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :8;\r
+ unsigned short MDE:1;\r
+ unsigned short :5;\r
+ unsigned short MD1:1;\r
+ unsigned short MD0:1;\r
+ } BIT;\r
+ } MDMONR;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :9;\r
+ unsigned short UBTS:1;\r
+ unsigned short :1;\r
+ unsigned short BOTS:1;\r
+ unsigned short BSW:2;\r
+ unsigned short EXB:1;\r
+ unsigned short IROM:1;\r
+ } BIT;\r
+ } MDSR;\r
+ unsigned char wk0[2];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short KEY:8;\r
+ unsigned short :6;\r
+ unsigned short EXBE:1;\r
+ unsigned short ROME:1;\r
+ } BIT;\r
+ } SYSCR0;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :15;\r
+ unsigned short RAME:1;\r
+ } BIT;\r
+ } SYSCR1;\r
+ unsigned char wk1[2];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short SSBY:1;\r
+ unsigned short OPE:1;\r
+ unsigned short :1;\r
+ unsigned short STS:5;\r
+ unsigned short :8;\r
+ } BIT;\r
+ } SBYCR;\r
+ unsigned char wk2[2];\r
+ union {\r
+ unsigned long LONG;\r
+ struct {\r
+ unsigned long ACSE:1;\r
+ unsigned long :1;\r
+ unsigned long MSTPA29:1;\r
+ unsigned long MSTPA28:1;\r
+ unsigned long :4;\r
+ unsigned long MSTPA23:1;\r
+ unsigned long MSTPA22:1;\r
+ unsigned long :2;\r
+ unsigned long MSTPA19:1;\r
+ unsigned long :1;\r
+ unsigned long MSTPA17:1;\r
+ unsigned long :1;\r
+ unsigned long MSTPA15:1;\r
+ unsigned long MSTPA14:1;\r
+ unsigned long :2;\r
+ unsigned long MSTPA11:1;\r
+ unsigned long MSTPA10:1;\r
+ unsigned long MSTPA9:1;\r
+ unsigned long MSTPA8:1;\r
+ unsigned long :2;\r
+ unsigned long MSTPA5:1;\r
+ unsigned long MSTPA4:1;\r
+ unsigned long :4;\r
+ } BIT;\r
+ } MSTPCRA;\r
+ union {\r
+ unsigned long LONG;\r
+ struct {\r
+ unsigned long MSTPB31:1;\r
+ unsigned long MSTPB30:1;\r
+ unsigned long MSTPB29:1;\r
+ unsigned long MSTPB28:1;\r
+ unsigned long :1;\r
+ unsigned long MSTPB26:1;\r
+ unsigned long MSTPB25:1;\r
+ unsigned long :1;\r
+ unsigned long MSTPB23:1;\r
+ unsigned long :1;\r
+ unsigned long MSTPB21:1;\r
+ unsigned long MSTPB20:1;\r
+ unsigned long MSTPB19:1;\r
+ unsigned long MSTPB18:1;\r
+ unsigned long MSTPB17:1;\r
+ unsigned long MSTPB16:1;\r
+ unsigned long MSTPB15:1;\r
+ unsigned long :14;\r
+ unsigned long MSTPB0:1;\r
+ } BIT;\r
+ } MSTPCRB;\r
+ union {\r
+ unsigned long LONG;\r
+ struct {\r
+ unsigned long :30;\r
+ unsigned long MSTPC1:1;\r
+ unsigned long MSTPC0:1;\r
+ } BIT;\r
+ } MSTPCRC;\r
+ unsigned char wk3[4];\r
+ union {\r
+ unsigned long LONG;\r
+ struct {\r
+ unsigned long :4;\r
+ unsigned long ICK:4;\r
+ unsigned long PSTOP1:1;\r
+ unsigned long PSTOP0:1;\r
+ unsigned long :2;\r
+ unsigned long BCK:4;\r
+ unsigned long :4;\r
+ unsigned long PCK:4;\r
+ unsigned long :8;\r
+ } BIT;\r
+ } SCKCR;\r
+ unsigned char wk4[12];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char BCLKDIV:1;\r
+ } BIT;\r
+ } BCKCR;\r
+ unsigned char wk5[15];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short KEY:8;\r
+ unsigned short OSTDE:1;\r
+ unsigned short OSTDF:1;\r
+ unsigned short :6;\r
+ } BIT;\r
+ } OSTDCR;\r
+ unsigned char wk6[49726];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char DPSBY:1;\r
+ unsigned char IOKEEP:1;\r
+ unsigned char RAMCUT2:1;\r
+ unsigned char RAMCUT1:1;\r
+ unsigned char :3;\r
+ unsigned char RAMCUT0:1;\r
+ } BIT;\r
+ } DPSBYCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char WTSTS:6;\r
+ } BIT;\r
+ } DPSWCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char DNMIE:1;\r
+ unsigned char DUSBE:1;\r
+ unsigned char DRTCE:1;\r
+ unsigned char DLVDE:1;\r
+ unsigned char DIRQ3E:1;\r
+ unsigned char DIRQ2E:1;\r
+ unsigned char DIRQ1E:1;\r
+ unsigned char DIRQ0E:1;\r
+ } BIT;\r
+ } DPSIER;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char DNMIF:1;\r
+ unsigned char DUSBF:1;\r
+ unsigned char DRTCFF:1;\r
+ unsigned char DLVDF:1;\r
+ unsigned char DIRQ3F:1;\r
+ unsigned char DIRQ2F:1;\r
+ unsigned char DIRQ1F:1;\r
+ unsigned char DIRQ0F:1;\r
+ } BIT;\r
+ } DPSIFR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char DNMIEG:1;\r
+ unsigned char :3;\r
+ unsigned char DIRQ3EG:1;\r
+ unsigned char DIRQ2EG:1;\r
+ unsigned char DIRQ1EG:1;\r
+ unsigned char DIRQ0EG:1;\r
+ } BIT;\r
+ } DPSIEGR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char DPSRSTF:1;\r
+ unsigned char :4;\r
+ unsigned char LVD2F:1;\r
+ unsigned char LVD1F:1;\r
+ unsigned char PORF:1;\r
+ } BIT;\r
+ } RSTSR;\r
+ unsigned char wk7[4];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char SUBSTOP:1;\r
+ } BIT;\r
+ } SUBOSCCR;\r
+ unsigned char wk8[1];\r
+ unsigned char LVDKEYR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char LVD2E:1;\r
+ unsigned char LVD2RI:1;\r
+ unsigned char :2;\r
+ unsigned char LVD1E:1;\r
+ unsigned char LVD1RI:1;\r
+ unsigned char :2;\r
+ } BIT;\r
+ } LVDCR;\r
+ unsigned char wk9[2];\r
+ unsigned char DPSBKR[32];\r
+};\r
+\r
+struct st_bsc {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char STSCLR:1;\r
+ } BIT;\r
+ } BERCLR;\r
+ unsigned char wk0[3];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :6;\r
+ unsigned char TOEN:1;\r
+ unsigned char IGAEN:1;\r
+ } BIT;\r
+ } BEREN;\r
+ unsigned char wk1[3];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char MST:3;\r
+ unsigned char :2;\r
+ unsigned char TO:1;\r
+ unsigned char IA:1;\r
+ } BIT;\r
+ } BERSR1;\r
+ unsigned char wk2[1];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short ADDR:13;\r
+ unsigned short :3;\r
+ } BIT;\r
+ } BERSR2;\r
+ unsigned char wk3[7414];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short PRMOD:1;\r
+ unsigned short :5;\r
+ unsigned short PWENB:1;\r
+ unsigned short PRENB:1;\r
+ unsigned short :4;\r
+ unsigned short EWENB:1;\r
+ unsigned short :2;\r
+ unsigned short WRMOD:1;\r
+ } BIT;\r
+ } CS0MOD;\r
+ union {\r
+ unsigned long LONG;\r
+ struct {\r
+ unsigned long :3;\r
+ unsigned long CSRWAIT:5;\r
+ unsigned long :3;\r
+ unsigned long CSWWAIT:5;\r
+ unsigned long :5;\r
+ unsigned long CSPRWAIT:3;\r
+ unsigned long :5;\r
+ unsigned long CSPWWAIT:3;\r
+ } BIT;\r
+ } CS0WCR1;\r
+ union {\r
+ unsigned long LONG;\r
+ struct {\r
+ unsigned long :1;\r
+ unsigned long CSON:3;\r
+ unsigned long :1;\r
+ unsigned long WDON:3;\r
+ unsigned long :1;\r
+ unsigned long WRON:3;\r
+ unsigned long :1;\r
+ unsigned long RDON:3;\r
+ unsigned long :5;\r
+ unsigned long WDOFF:3;\r
+ unsigned long :1;\r
+ unsigned long CSWOFF:3;\r
+ unsigned long :1;\r
+ unsigned long CSROFF:3;\r
+ } BIT;\r
+ } CS0WCR2;\r
+ unsigned char wk4[6];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short PRMOD:1;\r
+ unsigned short :5;\r
+ unsigned short PWENB:1;\r
+ unsigned short PRENB:1;\r
+ unsigned short :4;\r
+ unsigned short EWENB:1;\r
+ unsigned short :2;\r
+ unsigned short WRMOD:1;\r
+ } BIT;\r
+ } CS1MOD;\r
+ union {\r
+ unsigned long LONG;\r
+ struct {\r
+ unsigned long :3;\r
+ unsigned long CSRWAIT:5;\r
+ unsigned long :3;\r
+ unsigned long CSWWAIT:5;\r
+ unsigned long :5;\r
+ unsigned long CSPRWAIT:3;\r
+ unsigned long :5;\r
+ unsigned long CSPWWAIT:3;\r
+ } BIT;\r
+ } CS1WCR1;\r
+ union {\r
+ unsigned long LONG;\r
+ struct {\r
+ unsigned long :1;\r
+ unsigned long CSON:3;\r
+ unsigned long :1;\r
+ unsigned long WDON:3;\r
+ unsigned long :1;\r
+ unsigned long WRON:3;\r
+ unsigned long :1;\r
+ unsigned long RDON:3;\r
+ unsigned long :5;\r
+ unsigned long WDOFF:3;\r
+ unsigned long :1;\r
+ unsigned long CSWOFF:3;\r
+ unsigned long :1;\r
+ unsigned long CSROFF:3;\r
+ } BIT;\r
+ } CS1WCR2;\r
+ unsigned char wk5[6];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short PRMOD:1;\r
+ unsigned short :5;\r
+ unsigned short PWENB:1;\r
+ unsigned short PRENB:1;\r
+ unsigned short :4;\r
+ unsigned short EWENB:1;\r
+ unsigned short :2;\r
+ unsigned short WRMOD:1;\r
+ } BIT;\r
+ } CS2MOD;\r
+ union {\r
+ unsigned long LONG;\r
+ struct {\r
+ unsigned long :3;\r
+ unsigned long CSRWAIT:5;\r
+ unsigned long :3;\r
+ unsigned long CSWWAIT:5;\r
+ unsigned long :5;\r
+ unsigned long CSPRWAIT:3;\r
+ unsigned long :5;\r
+ unsigned long CSPWWAIT:3;\r
+ } BIT;\r
+ } CS2WCR1;\r
+ union {\r
+ unsigned long LONG;\r
+ struct {\r
+ unsigned long :1;\r
+ unsigned long CSON:3;\r
+ unsigned long :1;\r
+ unsigned long WDON:3;\r
+ unsigned long :1;\r
+ unsigned long WRON:3;\r
+ unsigned long :1;\r
+ unsigned long RDON:3;\r
+ unsigned long :5;\r
+ unsigned long WDOFF:3;\r
+ unsigned long :1;\r
+ unsigned long CSWOFF:3;\r
+ unsigned long :1;\r
+ unsigned long CSROFF:3;\r
+ } BIT;\r
+ } CS2WCR2;\r
+ unsigned char wk6[6];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short PRMOD:1;\r
+ unsigned short :5;\r
+ unsigned short PWENB:1;\r
+ unsigned short PRENB:1;\r
+ unsigned short :4;\r
+ unsigned short EWENB:1;\r
+ unsigned short :2;\r
+ unsigned short WRMOD:1;\r
+ } BIT;\r
+ } CS3MOD;\r
+ union {\r
+ unsigned long LONG;\r
+ struct {\r
+ unsigned long :3;\r
+ unsigned long CSRWAIT:5;\r
+ unsigned long :3;\r
+ unsigned long CSWWAIT:5;\r
+ unsigned long :5;\r
+ unsigned long CSPRWAIT:3;\r
+ unsigned long :5;\r
+ unsigned long CSPWWAIT:3;\r
+ } BIT;\r
+ } CS3WCR1;\r
+ union {\r
+ unsigned long LONG;\r
+ struct {\r
+ unsigned long :1;\r
+ unsigned long CSON:3;\r
+ unsigned long :1;\r
+ unsigned long WDON:3;\r
+ unsigned long :1;\r
+ unsigned long WRON:3;\r
+ unsigned long :1;\r
+ unsigned long RDON:3;\r
+ unsigned long :5;\r
+ unsigned long WDOFF:3;\r
+ unsigned long :1;\r
+ unsigned long CSWOFF:3;\r
+ unsigned long :1;\r
+ unsigned long CSROFF:3;\r
+ } BIT;\r
+ } CS3WCR2;\r
+ unsigned char wk7[6];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short PRMOD:1;\r
+ unsigned short :5;\r
+ unsigned short PWENB:1;\r
+ unsigned short PRENB:1;\r
+ unsigned short :4;\r
+ unsigned short EWENB:1;\r
+ unsigned short :2;\r
+ unsigned short WRMOD:1;\r
+ } BIT;\r
+ } CS4MOD;\r
+ union {\r
+ unsigned long LONG;\r
+ struct {\r
+ unsigned long :3;\r
+ unsigned long CSRWAIT:5;\r
+ unsigned long :3;\r
+ unsigned long CSWWAIT:5;\r
+ unsigned long :5;\r
+ unsigned long CSPRWAIT:3;\r
+ unsigned long :5;\r
+ unsigned long CSPWWAIT:3;\r
+ } BIT;\r
+ } CS4WCR1;\r
+ union {\r
+ unsigned long LONG;\r
+ struct {\r
+ unsigned long :1;\r
+ unsigned long CSON:3;\r
+ unsigned long :1;\r
+ unsigned long WDON:3;\r
+ unsigned long :1;\r
+ unsigned long WRON:3;\r
+ unsigned long :1;\r
+ unsigned long RDON:3;\r
+ unsigned long :5;\r
+ unsigned long WDOFF:3;\r
+ unsigned long :1;\r
+ unsigned long CSWOFF:3;\r
+ unsigned long :1;\r
+ unsigned long CSROFF:3;\r
+ } BIT;\r
+ } CS4WCR2;\r
+ unsigned char wk8[6];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short PRMOD:1;\r
+ unsigned short :5;\r
+ unsigned short PWENB:1;\r
+ unsigned short PRENB:1;\r
+ unsigned short :4;\r
+ unsigned short EWENB:1;\r
+ unsigned short :2;\r
+ unsigned short WRMOD:1;\r
+ } BIT;\r
+ } CS5MOD;\r
+ union {\r
+ unsigned long LONG;\r
+ struct {\r
+ unsigned long :3;\r
+ unsigned long CSRWAIT:5;\r
+ unsigned long :3;\r
+ unsigned long CSWWAIT:5;\r
+ unsigned long :5;\r
+ unsigned long CSPRWAIT:3;\r
+ unsigned long :5;\r
+ unsigned long CSPWWAIT:3;\r
+ } BIT;\r
+ } CS5WCR1;\r
+ union {\r
+ unsigned long LONG;\r
+ struct {\r
+ unsigned long :1;\r
+ unsigned long CSON:3;\r
+ unsigned long :1;\r
+ unsigned long WDON:3;\r
+ unsigned long :1;\r
+ unsigned long WRON:3;\r
+ unsigned long :1;\r
+ unsigned long RDON:3;\r
+ unsigned long :5;\r
+ unsigned long WDOFF:3;\r
+ unsigned long :1;\r
+ unsigned long CSWOFF:3;\r
+ unsigned long :1;\r
+ unsigned long CSROFF:3;\r
+ } BIT;\r
+ } CS5WCR2;\r
+ unsigned char wk9[6];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short PRMOD:1;\r
+ unsigned short :5;\r
+ unsigned short PWENB:1;\r
+ unsigned short PRENB:1;\r
+ unsigned short :4;\r
+ unsigned short EWENB:1;\r
+ unsigned short :2;\r
+ unsigned short WRMOD:1;\r
+ } BIT;\r
+ } CS6MOD;\r
+ union {\r
+ unsigned long LONG;\r
+ struct {\r
+ unsigned long :3;\r
+ unsigned long CSRWAIT:5;\r
+ unsigned long :3;\r
+ unsigned long CSWWAIT:5;\r
+ unsigned long :5;\r
+ unsigned long CSPRWAIT:3;\r
+ unsigned long :5;\r
+ unsigned long CSPWWAIT:3;\r
+ } BIT;\r
+ } CS6WCR1;\r
+ union {\r
+ unsigned long LONG;\r
+ struct {\r
+ unsigned long :1;\r
+ unsigned long CSON:3;\r
+ unsigned long :1;\r
+ unsigned long WDON:3;\r
+ unsigned long :1;\r
+ unsigned long WRON:3;\r
+ unsigned long :1;\r
+ unsigned long RDON:3;\r
+ unsigned long :5;\r
+ unsigned long WDOFF:3;\r
+ unsigned long :1;\r
+ unsigned long CSWOFF:3;\r
+ unsigned long :1;\r
+ unsigned long CSROFF:3;\r
+ } BIT;\r
+ } CS6WCR2;\r
+ unsigned char wk10[6];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short PRMOD:1;\r
+ unsigned short :5;\r
+ unsigned short PWENB:1;\r
+ unsigned short PRENB:1;\r
+ unsigned short :4;\r
+ unsigned short EWENB:1;\r
+ unsigned short :2;\r
+ unsigned short WRMOD:1;\r
+ } BIT;\r
+ } CS7MOD;\r
+ union {\r
+ unsigned long LONG;\r
+ struct {\r
+ unsigned long :3;\r
+ unsigned long CSRWAIT:5;\r
+ unsigned long :3;\r
+ unsigned long CSWWAIT:5;\r
+ unsigned long :5;\r
+ unsigned long CSPRWAIT:3;\r
+ unsigned long :5;\r
+ unsigned long CSPWWAIT:3;\r
+ } BIT;\r
+ } CS7WCR1;\r
+ union {\r
+ unsigned long LONG;\r
+ struct {\r
+ unsigned long :1;\r
+ unsigned long CSON:3;\r
+ unsigned long :1;\r
+ unsigned long WDON:3;\r
+ unsigned long :1;\r
+ unsigned long WRON:3;\r
+ unsigned long :1;\r
+ unsigned long RDON:3;\r
+ unsigned long :5;\r
+ unsigned long WDOFF:3;\r
+ unsigned long :1;\r
+ unsigned long CSWOFF:3;\r
+ unsigned long :1;\r
+ unsigned long CSROFF:3;\r
+ } BIT;\r
+ } CS7WCR2;\r
+ unsigned char wk11[1926];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :7;\r
+ unsigned short EMODE:1;\r
+ unsigned short :2;\r
+ unsigned short BSIZE:2;\r
+ unsigned short :3;\r
+ unsigned short EXENB:1;\r
+ } BIT;\r
+ } CS0CR;\r
+ unsigned char wk12[6];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :4;\r
+ unsigned short WRCV:4;\r
+ unsigned short :4;\r
+ unsigned short RRCV:4;\r
+ } BIT;\r
+ } CS0REC;\r
+ unsigned char wk13[6];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :7;\r
+ unsigned short EMODE:1;\r
+ unsigned short :2;\r
+ unsigned short BSIZE:2;\r
+ unsigned short :3;\r
+ unsigned short EXENB:1;\r
+ } BIT;\r
+ } CS1CR;\r
+ unsigned char wk14[6];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :4;\r
+ unsigned short WRCV:4;\r
+ unsigned short :4;\r
+ unsigned short RRCV:4;\r
+ } BIT;\r
+ } CS1REC;\r
+ unsigned char wk15[6];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :7;\r
+ unsigned short EMODE:1;\r
+ unsigned short :2;\r
+ unsigned short BSIZE:2;\r
+ unsigned short :3;\r
+ unsigned short EXENB:1;\r
+ } BIT;\r
+ } CS2CR;\r
+ unsigned char wk16[6];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :4;\r
+ unsigned short WRCV:4;\r
+ unsigned short :4;\r
+ unsigned short RRCV:4;\r
+ } BIT;\r
+ } CS2REC;\r
+ unsigned char wk17[6];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :7;\r
+ unsigned short EMODE:1;\r
+ unsigned short :2;\r
+ unsigned short BSIZE:2;\r
+ unsigned short :3;\r
+ unsigned short EXENB:1;\r
+ } BIT;\r
+ } CS3CR;\r
+ unsigned char wk18[6];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :4;\r
+ unsigned short WRCV:4;\r
+ unsigned short :4;\r
+ unsigned short RRCV:4;\r
+ } BIT;\r
+ } CS3REC;\r
+ unsigned char wk19[6];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :7;\r
+ unsigned short EMODE:1;\r
+ unsigned short :2;\r
+ unsigned short BSIZE:2;\r
+ unsigned short :3;\r
+ unsigned short EXENB:1;\r
+ } BIT;\r
+ } CS4CR;\r
+ unsigned char wk20[6];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :4;\r
+ unsigned short WRCV:4;\r
+ unsigned short :4;\r
+ unsigned short RRCV:4;\r
+ } BIT;\r
+ } CS4REC;\r
+ unsigned char wk21[6];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :7;\r
+ unsigned short EMODE:1;\r
+ unsigned short :2;\r
+ unsigned short BSIZE:2;\r
+ unsigned short :3;\r
+ unsigned short EXENB:1;\r
+ } BIT;\r
+ } CS5CR;\r
+ unsigned char wk22[6];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :4;\r
+ unsigned short WRCV:4;\r
+ unsigned short :4;\r
+ unsigned short RRCV:4;\r
+ } BIT;\r
+ } CS5REC;\r
+ unsigned char wk23[6];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :7;\r
+ unsigned short EMODE:1;\r
+ unsigned short :2;\r
+ unsigned short BSIZE:2;\r
+ unsigned short :3;\r
+ unsigned short EXENB:1;\r
+ } BIT;\r
+ } CS6CR;\r
+ unsigned char wk24[6];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :4;\r
+ unsigned short WRCV:4;\r
+ unsigned short :4;\r
+ unsigned short RRCV:4;\r
+ } BIT;\r
+ } CS6REC;\r
+ unsigned char wk25[6];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :7;\r
+ unsigned short EMODE:1;\r
+ unsigned short :2;\r
+ unsigned short BSIZE:2;\r
+ unsigned short :3;\r
+ unsigned short EXENB:1;\r
+ } BIT;\r
+ } CS7CR;\r
+ unsigned char wk26[6];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :4;\r
+ unsigned short WRCV:4;\r
+ unsigned short :4;\r
+ unsigned short RRCV:4;\r
+ } BIT;\r
+ } CS7REC;\r
+ unsigned char wk27[900];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char BSIZE:2;\r
+ unsigned char :3;\r
+ unsigned char EXENB:1;\r
+ } BIT;\r
+ } SDCCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char EMODE:1;\r
+ } BIT;\r
+ } SDCMOD;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char BE:1;\r
+ } BIT;\r
+ } SDAMOD;\r
+ unsigned char wk28[13];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char SFEN:1;\r
+ } BIT;\r
+ } SDSELF;\r
+ unsigned char wk29[3];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short REFW:4;\r
+ unsigned short RFC:12;\r
+ } BIT;\r
+ } SDRFCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char RFEN:1;\r
+ } BIT;\r
+ } SDRFEN;\r
+ unsigned char wk30[9];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char INIRQ:1;\r
+ } BIT;\r
+ } SDICR;\r
+ unsigned char wk31[3];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :5;\r
+ unsigned short PRC:3;\r
+ unsigned short ARFC:4;\r
+ unsigned short ARFI:4;\r
+ } BIT;\r
+ } SDIR;\r
+ unsigned char wk32[26];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :6;\r
+ unsigned char MXC:2;\r
+ } BIT;\r
+ } SDADR;\r
+ unsigned char wk33[3];\r
+ union {\r
+ unsigned long LONG;\r
+ struct {\r
+ unsigned long :13;\r
+ unsigned long RAS:3;\r
+ unsigned long :2;\r
+ unsigned long RCD:2;\r
+ unsigned long RP:3;\r
+ unsigned long WR:1;\r
+ unsigned long :5;\r
+ unsigned long CL:3;\r
+ } BIT;\r
+ } SDTR;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :1;\r
+ unsigned short MR:15;\r
+ } BIT;\r
+ } SDMOD;\r
+ unsigned char wk34[6];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char SRFST:1;\r
+ unsigned char INIST:1;\r
+ unsigned char :2;\r
+ unsigned char MRSST:1;\r
+ } BIT;\r
+ } SDSR;\r
+};\r
+\r
+struct st_dmac0 {\r
+ void *DMSAR;\r
+ void *DMDAR;\r
+ unsigned long DMCRA;\r
+ unsigned short DMCRB;\r
+ unsigned char wk0[2];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short MD:2;\r
+ unsigned short DTS:2;\r
+ unsigned short :2;\r
+ unsigned short SZ:2;\r
+ unsigned short :6;\r
+ unsigned short DCTG:2;\r
+ } BIT;\r
+ } DMTMD;\r
+ unsigned char wk1[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char DTIE:1;\r
+ unsigned char ESIE:1;\r
+ unsigned char RPTIE:1;\r
+ unsigned char SARIE:1;\r
+ unsigned char DARIE:1;\r
+ } BIT;\r
+ } DMINT;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short SM:2;\r
+ unsigned short :1;\r
+ unsigned short SARA:5;\r
+ unsigned short DM:2;\r
+ unsigned short :1;\r
+ unsigned short DARA:5;\r
+ } BIT;\r
+ } DMAMD;\r
+ unsigned char wk2[2];\r
+ unsigned long DMOFR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char DTE:1;\r
+ } BIT;\r
+ } DMCNT;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char CLRS:1;\r
+ unsigned char :3;\r
+ unsigned char SWREQ:1;\r
+ } BIT;\r
+ } DMREQ;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ACT:1;\r
+ unsigned char :2;\r
+ unsigned char DTIF:1;\r
+ unsigned char :3;\r
+ unsigned char ESIF:1;\r
+ } BIT;\r
+ } DMSTS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char DISEL:1;\r
+ } BIT;\r
+ } DMCSL;\r
+};\r
+\r
+struct st_dmac1 {\r
+ void *DMSAR;\r
+ void *DMDAR;\r
+ unsigned long DMCRA;\r
+ unsigned short DMCRB;\r
+ unsigned char wk0[2];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short MD:2;\r
+ unsigned short DTS:2;\r
+ unsigned short :2;\r
+ unsigned short SZ:2;\r
+ unsigned short :6;\r
+ unsigned short DCTG:2;\r
+ } BIT;\r
+ } DMTMD;\r
+ unsigned char wk1[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char DTIE:1;\r
+ unsigned char ESIE:1;\r
+ unsigned char RPTIE:1;\r
+ unsigned char SARIE:1;\r
+ unsigned char DARIE:1;\r
+ } BIT;\r
+ } DMINT;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short SM:2;\r
+ unsigned short :1;\r
+ unsigned short SARA:5;\r
+ unsigned short DM:2;\r
+ unsigned short :1;\r
+ unsigned short DARA:5;\r
+ } BIT;\r
+ } DMAMD;\r
+ unsigned char wk2[6];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char DTE:1;\r
+ } BIT;\r
+ } DMCNT;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char CLRS:1;\r
+ unsigned char :3;\r
+ unsigned char SWREQ:1;\r
+ } BIT;\r
+ } DMREQ;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ACT:1;\r
+ unsigned char :2;\r
+ unsigned char DTIF:1;\r
+ unsigned char :3;\r
+ unsigned char ESIF:1;\r
+ } BIT;\r
+ } DMSTS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char DISEL:1;\r
+ } BIT;\r
+ } DMCSL;\r
+};\r
+\r
+struct st_dmac {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char DMST:1;\r
+ } BIT;\r
+ } DMAST;\r
+};\r
+\r
+struct st_dtc {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char RRS:1;\r
+ unsigned char :4;\r
+ } BIT;\r
+ } DTCCR;\r
+ unsigned char wk0[3];\r
+ void *DTCVBR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char SHORT:1;\r
+ } BIT;\r
+ } DTCADMOD;\r
+ unsigned char wk1[3];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char DTCST:1;\r
+ } BIT;\r
+ } DTCST;\r
+ unsigned char wk2[1];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short ACT:1;\r
+ unsigned short :7;\r
+ unsigned short VECN:8;\r
+ } BIT;\r
+ } DTCSTS;\r
+};\r
+\r
+struct st_exdmac0 {\r
+ void *EDMSAR;\r
+ void *EDMDAR;\r
+ unsigned long EDMCRA;\r
+ unsigned short EDMCRB;\r
+ unsigned char wk0[2];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short MD:2;\r
+ unsigned short DTS:2;\r
+ unsigned short :2;\r
+ unsigned short SZ:2;\r
+ unsigned short :6;\r
+ unsigned short DCTG:2;\r
+ } BIT;\r
+ } EDMTMD;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :4;\r
+ unsigned char DACKS:1;\r
+ unsigned char DACKE:1;\r
+ unsigned char DACKW:1;\r
+ unsigned char :1;\r
+ } BIT;\r
+ } EDMOMD;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char DTIE:1;\r
+ unsigned char ESIE:1;\r
+ unsigned char RPTIE:1;\r
+ unsigned char SARIE:1;\r
+ unsigned char DARIE:1;\r
+ } BIT;\r
+ } EDMINT;\r
+ union {\r
+ unsigned long LONG;\r
+ struct {\r
+ unsigned long :14;\r
+ unsigned long AMS:1;\r
+ unsigned long DIR:1;\r
+ unsigned long SM:2;\r
+ unsigned long :1;\r
+ unsigned long SARA:5;\r
+ unsigned long DM:2;\r
+ unsigned long :1;\r
+ unsigned long DARA:5;\r
+ } BIT;\r
+ } EDMAMD;\r
+ unsigned long EDMOFR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char DTE:1;\r
+ } BIT;\r
+ } EDMCNT;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char CLRS:1;\r
+ unsigned char :3;\r
+ unsigned char SWREQ:1;\r
+ } BIT;\r
+ } EDMREQ;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ACT:1;\r
+ unsigned char :2;\r
+ unsigned char DTIF:1;\r
+ unsigned char :3;\r
+ unsigned char ESIF:1;\r
+ } BIT;\r
+ } EDMSTS;\r
+ unsigned char wk1[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :6;\r
+ unsigned char DREQS:2;\r
+ } BIT;\r
+ } EDMRMD;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char EREQ:1;\r
+ } BIT;\r
+ } EDMERF;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char PREQ:1;\r
+ } BIT;\r
+ } EDMPRF;\r
+};\r
+\r
+struct st_exdmac {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char DMST:1;\r
+ } BIT;\r
+ } EDMAST;\r
+ unsigned char wk0[479];\r
+ unsigned long CLSBR0;\r
+ unsigned long CLSBR1;\r
+ unsigned long CLSBR2;\r
+ unsigned long CLSBR3;\r
+ unsigned long CLSBR4;\r
+ unsigned long CLSBR5;\r
+ unsigned long CLSBR6;\r
+ unsigned long CLSBR7;\r
+};\r
+\r
+struct st_icu {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char IR:1;\r
+ } BIT;\r
+ } IR[254];\r
+ unsigned char wk17[2];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char DTCE:1;\r
+ } BIT;\r
+ } DTCER[254];\r
+ unsigned char wk47[2];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char IEN7:1;\r
+ unsigned char IEN6:1;\r
+ unsigned char IEN5:1;\r
+ unsigned char IEN4:1;\r
+ unsigned char IEN3:1;\r
+ unsigned char IEN2:1;\r
+ unsigned char IEN1:1;\r
+ unsigned char IEN0:1;\r
+ } BIT;\r
+ } IER[32];\r
+ unsigned char wk50[192];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char SWINT:1;\r
+ } BIT;\r
+ } SWINTR;\r
+ unsigned char wk51[15];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short FIEN:1;\r
+ unsigned short :7;\r
+ unsigned short FVCT:8;\r
+ } BIT;\r
+ } FIR;\r
+ unsigned char wk52[14];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :4;\r
+ unsigned char IPR:4;\r
+ } BIT;\r
+ } IPR[144];\r
+ unsigned char wk67[112];\r
+ unsigned char DMRSR0;\r
+ unsigned char wk68[3];\r
+ unsigned char DMRSR1;\r
+ unsigned char wk69[3];\r
+ unsigned char DMRSR2;\r
+ unsigned char wk70[3];\r
+ unsigned char DMRSR3;\r
+ unsigned char wk71[243];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :4;\r
+ unsigned char IRQMD:2;\r
+ unsigned char :2;\r
+ } BIT;\r
+ } IRQCR[16];\r
+ unsigned char wk72[112];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :5;\r
+ unsigned char OSTST:1;\r
+ unsigned char LVDST:1;\r
+ unsigned char NMIST:1;\r
+ } BIT;\r
+ } NMISR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :5;\r
+ unsigned char OSTEN:1;\r
+ unsigned char LVDEN:1;\r
+ unsigned char NMIEN:1;\r
+ } BIT;\r
+ } NMIER;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :5;\r
+ unsigned char OSTCLR:1;\r
+ unsigned char :1;\r
+ unsigned char NMICLR:1;\r
+ } BIT;\r
+ } NMICLR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :4;\r
+ unsigned char NMIMD:1;\r
+ unsigned char :3;\r
+ } BIT;\r
+ } NMICR;\r
+};\r
+\r
+struct st_cmt {\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :14;\r
+ unsigned short STR1:1;\r
+ unsigned short STR0:1;\r
+ } BIT;\r
+ } CMSTR0;\r
+ unsigned char wk0[14];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :14;\r
+ unsigned short STR3:1;\r
+ unsigned short STR2:1;\r
+ } BIT;\r
+ } CMSTR1;\r
+};\r
+\r
+struct st_cmt0 {\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :9;\r
+ unsigned short CMIE:1;\r
+ unsigned short :4;\r
+ unsigned short CKS:2;\r
+ } BIT;\r
+ } CMCR;\r
+ unsigned short CMCNT;\r
+ unsigned short CMCOR;\r
+};\r
+\r
+union un_wdt {\r
+ struct {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char TMS:1;\r
+ unsigned char TME:1;\r
+ unsigned char :2;\r
+ unsigned char CKS:3;\r
+ } BIT;\r
+ } TCSR;\r
+ unsigned char TCNT;\r
+ unsigned char wk0[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char WOVF:1;\r
+ unsigned char RSTE:1;\r
+ unsigned char :6;\r
+ } BIT;\r
+ } RSTCSR;\r
+ } READ;\r
+ struct {\r
+ unsigned short WINA;\r
+ unsigned short WINB;\r
+ } WRITE;\r
+};\r
+\r
+struct st_iwdt {\r
+ unsigned char IWDTRR;\r
+ unsigned char wk0[1];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :8;\r
+ unsigned short CKS:4;\r
+ unsigned short :2;\r
+ unsigned short TOPS:2;\r
+ } BIT;\r
+ } IWDTCR;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :1;\r
+ unsigned short UNDFF:1;\r
+ unsigned short CNTVAL:14;\r
+ } BIT;\r
+ } IWDTSR;\r
+};\r
+\r
+struct st_ad {\r
+ unsigned short ADDRA;\r
+ unsigned short ADDRB;\r
+ unsigned short ADDRC;\r
+ unsigned short ADDRD;\r
+ unsigned char wk0[8];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char ADIE:1;\r
+ unsigned char ADST:1;\r
+ unsigned char :1;\r
+ unsigned char CH:4;\r
+ } BIT;\r
+ } ADCSR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char TRGS:3;\r
+ unsigned char :1;\r
+ unsigned char CKS:2;\r
+ unsigned char MODE:2;\r
+ } BIT;\r
+ } ADCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char DPSEL:1;\r
+ unsigned char :7;\r
+ } BIT;\r
+ } ADDPR;\r
+ unsigned char ADSSTR;\r
+ unsigned char wk1[11];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :6;\r
+ unsigned char DIAG:2;\r
+ } BIT;\r
+ } ADDIAGR;\r
+};\r
+\r
+struct st_da {\r
+ unsigned short DADR0;\r
+ unsigned short DADR1;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char DAOE1:1;\r
+ unsigned char DAOE0:1;\r
+ unsigned char DAE:1;\r
+ unsigned char :5;\r
+ } BIT;\r
+ } DACR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char DPSEL:1;\r
+ unsigned char :7;\r
+ } BIT;\r
+ } DADPR;\r
+};\r
+\r
+struct st_ppg0 {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char G3CMS:2;\r
+ unsigned char G2CMS:2;\r
+ unsigned char G1CMS:2;\r
+ unsigned char G0CMS:2;\r
+ } BIT;\r
+ } PCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char G3INV:1;\r
+ unsigned char G2INV:1;\r
+ unsigned char G1INV:1;\r
+ unsigned char G0INV:1;\r
+ unsigned char G3NOV:1;\r
+ unsigned char G2NOV:1;\r
+ unsigned char G1NOV:1;\r
+ unsigned char G0NOV:1;\r
+ } BIT;\r
+ } PMR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char NDER15:1;\r
+ unsigned char NDER14:1;\r
+ unsigned char NDER13:1;\r
+ unsigned char NDER12:1;\r
+ unsigned char NDER11:1;\r
+ unsigned char NDER10:1;\r
+ unsigned char NDER9:1;\r
+ unsigned char NDER8:1;\r
+ } BIT;\r
+ } NDERH;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char NDER7:1;\r
+ unsigned char NDER6:1;\r
+ unsigned char NDER5:1;\r
+ unsigned char NDER4:1;\r
+ unsigned char NDER3:1;\r
+ unsigned char NDER2:1;\r
+ unsigned char NDER1:1;\r
+ unsigned char NDER0:1;\r
+ } BIT;\r
+ } NDERL;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char POD15:1;\r
+ unsigned char POD14:1;\r
+ unsigned char POD13:1;\r
+ unsigned char POD12:1;\r
+ unsigned char POD11:1;\r
+ unsigned char POD10:1;\r
+ unsigned char POD9:1;\r
+ unsigned char POD8:1;\r
+ } BIT;\r
+ } PODRH;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char POD7:1;\r
+ unsigned char POD6:1;\r
+ unsigned char POD5:1;\r
+ unsigned char POD4:1;\r
+ unsigned char POD3:1;\r
+ unsigned char POD2:1;\r
+ unsigned char POD1:1;\r
+ unsigned char POD0:1;\r
+ } BIT;\r
+ } PODRL;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char NDR15:1;\r
+ unsigned char NDR14:1;\r
+ unsigned char NDR13:1;\r
+ unsigned char NDR12:1;\r
+ unsigned char NDR11:1;\r
+ unsigned char NDR10:1;\r
+ unsigned char NDR9:1;\r
+ unsigned char NDR8:1;\r
+ } BIT;\r
+ } NDRH;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char NDR7:1;\r
+ unsigned char NDR6:1;\r
+ unsigned char NDR5:1;\r
+ unsigned char NDR4:1;\r
+ unsigned char NDR3:1;\r
+ unsigned char NDR2:1;\r
+ unsigned char NDR1:1;\r
+ unsigned char NDR0:1;\r
+ } BIT;\r
+ } NDRL;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :4;\r
+ unsigned char NDR11:1;\r
+ unsigned char NDR10:1;\r
+ unsigned char NDR9:1;\r
+ unsigned char NDR8:1;\r
+ } BIT;\r
+ } NDRH2;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :4;\r
+ unsigned char NDR3:1;\r
+ unsigned char NDR2:1;\r
+ unsigned char NDR1:1;\r
+ unsigned char NDR0:1;\r
+ } BIT;\r
+ } NDRL2;\r
+};\r
+\r
+struct st_ppg1 {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char PTRSL:1;\r
+ } BIT;\r
+ } PTRSLR;\r
+ unsigned char wk0[5];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char G3CMS:2;\r
+ unsigned char G2CMS:2;\r
+ unsigned char G1CMS:2;\r
+ unsigned char G0CMS:2;\r
+ } BIT;\r
+ } PCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char G3INV:1;\r
+ unsigned char G2INV:1;\r
+ unsigned char G1INV:1;\r
+ unsigned char G0INV:1;\r
+ unsigned char G3NOV:1;\r
+ unsigned char G2NOV:1;\r
+ unsigned char G1NOV:1;\r
+ unsigned char G0NOV:1;\r
+ } BIT;\r
+ } PMR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char NDER31:1;\r
+ unsigned char NDER30:1;\r
+ unsigned char NDER29:1;\r
+ unsigned char NDER28:1;\r
+ unsigned char NDER27:1;\r
+ unsigned char NDER26:1;\r
+ unsigned char NDER25:1;\r
+ unsigned char NDER24:1;\r
+ } BIT;\r
+ } NDERH;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char NDER23:1;\r
+ unsigned char NDER22:1;\r
+ unsigned char NDER21:1;\r
+ unsigned char NDER20:1;\r
+ unsigned char NDER19:1;\r
+ unsigned char NDER18:1;\r
+ unsigned char NDER17:1;\r
+ unsigned char NDER16:1;\r
+ } BIT;\r
+ } NDERL;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char POD31:1;\r
+ unsigned char POD30:1;\r
+ unsigned char POD29:1;\r
+ unsigned char POD28:1;\r
+ unsigned char POD27:1;\r
+ unsigned char POD26:1;\r
+ unsigned char POD25:1;\r
+ unsigned char POD24:1;\r
+ } BIT;\r
+ } PODRH;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char POD23:1;\r
+ unsigned char POD22:1;\r
+ unsigned char POD21:1;\r
+ unsigned char POD20:1;\r
+ unsigned char POD19:1;\r
+ unsigned char POD18:1;\r
+ unsigned char POD17:1;\r
+ unsigned char POD16:1;\r
+ } BIT;\r
+ } PODRL;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char NDR31:1;\r
+ unsigned char NDR30:1;\r
+ unsigned char NDR29:1;\r
+ unsigned char NDR28:1;\r
+ unsigned char NDR27:1;\r
+ unsigned char NDR26:1;\r
+ unsigned char NDR25:1;\r
+ unsigned char NDR24:1;\r
+ } BIT;\r
+ } NDRH;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char NDR23:1;\r
+ unsigned char NDR22:1;\r
+ unsigned char NDR21:1;\r
+ unsigned char NDR20:1;\r
+ unsigned char NDR19:1;\r
+ unsigned char NDR18:1;\r
+ unsigned char NDR17:1;\r
+ unsigned char NDR16:1;\r
+ } BIT;\r
+ } NDRL;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :4;\r
+ unsigned char NDR27:1;\r
+ unsigned char NDR26:1;\r
+ unsigned char NDR25:1;\r
+ unsigned char NDR24:1;\r
+ } BIT;\r
+ } NDRH2;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :4;\r
+ unsigned char NDR19:1;\r
+ unsigned char NDR18:1;\r
+ unsigned char NDR17:1;\r
+ unsigned char NDR16:1;\r
+ } BIT;\r
+ } NDRL2;\r
+};\r
+\r
+struct st_tmr0 {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char CMIEB:1;\r
+ unsigned char CMIEA:1;\r
+ unsigned char OVIE:1;\r
+ unsigned char CCLR:2;\r
+ unsigned char :3;\r
+ } BIT;\r
+ } TCR;\r
+ unsigned char wk0[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char ADTE:1;\r
+ unsigned char OSB:2;\r
+ unsigned char OSA:2;\r
+ } BIT;\r
+ } TCSR;\r
+ unsigned char wk1[1];\r
+ unsigned char TCORA;\r
+ unsigned char wk2[1];\r
+ unsigned char TCORB;\r
+ unsigned char wk3[1];\r
+ unsigned char TCNT;\r
+ unsigned char wk4[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char TMRIS:1;\r
+ unsigned char :2;\r
+ unsigned char CSS:2;\r
+ unsigned char CKS:3;\r
+ } BIT;\r
+ } TCCR;\r
+};\r
+\r
+struct st_tmr1 {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char CMIEB:1;\r
+ unsigned char CMIEA:1;\r
+ unsigned char OVIE:1;\r
+ unsigned char CCLR:2;\r
+ unsigned char :3;\r
+ } BIT;\r
+ } TCR;\r
+ unsigned char wk0[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :4;\r
+ unsigned char OSB:2;\r
+ unsigned char OSA:2;\r
+ } BIT;\r
+ } TCSR;\r
+ unsigned char wk1[1];\r
+ unsigned char TCORA;\r
+ unsigned char wk2[1];\r
+ unsigned char TCORB;\r
+ unsigned char wk3[1];\r
+ unsigned char TCNT;\r
+ unsigned char wk4[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char TMRIS:1;\r
+ unsigned char :2;\r
+ unsigned char CSS:2;\r
+ unsigned char CKS:3;\r
+ } BIT;\r
+ } TCCR;\r
+};\r
+\r
+struct st_tmr01 {\r
+ unsigned short TCORA;\r
+ unsigned short TCORB;\r
+ unsigned short TCNT;\r
+ unsigned short TCCR;\r
+};\r
+\r
+struct st_sci {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char CM:1;\r
+ unsigned char CHR:1;\r
+ unsigned char PE:1;\r
+ unsigned char PM:1;\r
+ unsigned char STOP:1;\r
+ unsigned char MP:1;\r
+ unsigned char CKS:2;\r
+ } BIT;\r
+ } SMR;\r
+ unsigned char BRR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char TIE:1;\r
+ unsigned char RIE:1;\r
+ unsigned char TE:1;\r
+ unsigned char RE:1;\r
+ unsigned char MPIE:1;\r
+ unsigned char TEIE:1;\r
+ unsigned char CKE:2;\r
+ } BIT;\r
+ } SCR;\r
+ unsigned char TDR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char ORER:1;\r
+ unsigned char FER:1;\r
+ unsigned char PER:1;\r
+ unsigned char TEND:1;\r
+ unsigned char MPB:1;\r
+ unsigned char MPBT:1;\r
+ } BIT;\r
+ } SSR;\r
+ unsigned char RDR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :4;\r
+ unsigned char SDIR:1;\r
+ unsigned char SINV:1;\r
+ unsigned char :1;\r
+ unsigned char SMIF:1;\r
+ } BIT;\r
+ } SCMR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char ABCS:1;\r
+ unsigned char :3;\r
+ unsigned char ACS0:1;\r
+ } BIT;\r
+ } SEMR;\r
+};\r
+\r
+struct st_smci {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char GM:1;\r
+ unsigned char BLK:1;\r
+ unsigned char PE:1;\r
+ unsigned char PM:1;\r
+ unsigned char BCP:2;\r
+ unsigned char CKS:2;\r
+ } BIT;\r
+ } SMR;\r
+ unsigned char BRR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char TIE:1;\r
+ unsigned char RIE:1;\r
+ unsigned char TE:1;\r
+ unsigned char RE:1;\r
+ unsigned char :1;\r
+ unsigned char TEIE:1;\r
+ unsigned char CKE:2;\r
+ } BIT;\r
+ } SCR;\r
+ unsigned char TDR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char ORER:1;\r
+ unsigned char ERS:1;\r
+ unsigned char PER:1;\r
+ unsigned char TEND:1;\r
+ unsigned char :2;\r
+ } BIT;\r
+ } SSR;\r
+ unsigned char RDR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char BCP2:1;\r
+ unsigned char :3;\r
+ unsigned char SDIR:1;\r
+ unsigned char SINV:1;\r
+ unsigned char :1;\r
+ unsigned char SMIF:1;\r
+ } BIT;\r
+ } SCMR;\r
+};\r
+\r
+struct st_crc {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char DORCLR:1;\r
+ unsigned char :4;\r
+ unsigned char LMS:1;\r
+ unsigned char GPS:2;\r
+ } BIT;\r
+ } CRCCR;\r
+ unsigned char CRCDIR;\r
+ unsigned short CRCDOR;\r
+};\r
+\r
+struct st_riic {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ICE:1;\r
+ unsigned char IICRST:1;\r
+ unsigned char CLO:1;\r
+ unsigned char SOWP:1;\r
+ unsigned char SCLO:1;\r
+ unsigned char SDAO:1;\r
+ unsigned char SCLI:1;\r
+ unsigned char SDAI:1;\r
+ } BIT;\r
+ } ICCR1;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char BBSY:1;\r
+ unsigned char MST:1;\r
+ unsigned char TRS:1;\r
+ unsigned char :1;\r
+ unsigned char SP:1;\r
+ unsigned char RS:1;\r
+ unsigned char ST:1;\r
+ unsigned char :1;\r
+ } BIT;\r
+ } ICCR2;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char MTWP:1;\r
+ unsigned char CKS:3;\r
+ unsigned char BCWP:1;\r
+ unsigned char BC:3;\r
+ } BIT;\r
+ } ICMR1;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char DLCS:1;\r
+ unsigned char SDDL:3;\r
+ unsigned char :1;\r
+ unsigned char TMOH:1;\r
+ unsigned char TMOL:1;\r
+ unsigned char TMOS:1;\r
+ } BIT;\r
+ } ICMR2;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char SMBS:1;\r
+ unsigned char WAIT:1;\r
+ unsigned char RDRFS:1;\r
+ unsigned char ACKWP:1;\r
+ unsigned char ACKBT:1;\r
+ unsigned char ACKBR:1;\r
+ unsigned char NF:2;\r
+ } BIT;\r
+ } ICMR3;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char FMPE:1;\r
+ unsigned char SCLE:1;\r
+ unsigned char NFE:1;\r
+ unsigned char NACKE:1;\r
+ unsigned char SALE:1;\r
+ unsigned char NALE:1;\r
+ unsigned char MALE:1;\r
+ unsigned char TMOE:1;\r
+ } BIT;\r
+ } ICFER;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char HOAE:1;\r
+ unsigned char :1;\r
+ unsigned char DIDE:1;\r
+ unsigned char :1;\r
+ unsigned char GCAE:1;\r
+ unsigned char SAR2E:1;\r
+ unsigned char SAR1E:1;\r
+ unsigned char SAR0E:1;\r
+ } BIT;\r
+ } ICSER;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char TIE:1;\r
+ unsigned char TEIE:1;\r
+ unsigned char RIE:1;\r
+ unsigned char NAKIE:1;\r
+ unsigned char SPIE:1;\r
+ unsigned char STIE:1;\r
+ unsigned char ALIE:1;\r
+ unsigned char TMOIE:1;\r
+ } BIT;\r
+ } ICIER;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char HOA:1;\r
+ unsigned char :1;\r
+ unsigned char DID:1;\r
+ unsigned char :1;\r
+ unsigned char GCA:1;\r
+ unsigned char AAS2:1;\r
+ unsigned char AAS1:1;\r
+ unsigned char AAS0:1;\r
+ } BIT;\r
+ } ICSR1;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char TDRE:1;\r
+ unsigned char TEND:1;\r
+ unsigned char RDRF:1;\r
+ unsigned char NACKF:1;\r
+ unsigned char STOP:1;\r
+ unsigned char START:1;\r
+ unsigned char AL:1;\r
+ unsigned char TMOF:1;\r
+ } BIT;\r
+ } ICSR2;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char SVA:7;\r
+ unsigned char SVA0:1;\r
+ } BIT;\r
+ } SARL0;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :5;\r
+ unsigned char SVA:2;\r
+ unsigned char FS:1;\r
+ } BIT;\r
+ } SARU0;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char SVA:7;\r
+ unsigned char SVA0:1;\r
+ } BIT;\r
+ } SARL1;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :5;\r
+ unsigned char SVA:2;\r
+ unsigned char FS:1;\r
+ } BIT;\r
+ } SARU1;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char SVA:7;\r
+ unsigned char SVA0:1;\r
+ } BIT;\r
+ } SARL2;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :5;\r
+ unsigned char SVA:2;\r
+ unsigned char FS:1;\r
+ } BIT;\r
+ } SARU2;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char BRL:5;\r
+ } BIT;\r
+ } ICBRL;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char BRH:5;\r
+ } BIT;\r
+ } ICBRH;\r
+ unsigned char ICDRT;\r
+ unsigned char ICDRR;\r
+};\r
+\r
+struct st_rspi {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char SPRIE:1;\r
+ unsigned char SPE:1;\r
+ unsigned char SPTIE:1;\r
+ unsigned char SPEIE:1;\r
+ unsigned char MSTR:1;\r
+ unsigned char MODFEN:1;\r
+ unsigned char TXMD:1;\r
+ unsigned char SPMS:1;\r
+ } BIT;\r
+ } SPCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :4;\r
+ unsigned char SSLP3:1;\r
+ unsigned char SSLP2:1;\r
+ unsigned char SSLP1:1;\r
+ unsigned char SSLP0:1;\r
+ } BIT;\r
+ } SSLP;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char MOIFE:1;\r
+ unsigned char MOIFV:1;\r
+ unsigned char :1;\r
+ unsigned char SPOM:1;\r
+ unsigned char SPLP2:1;\r
+ unsigned char SPLP:1;\r
+ } BIT;\r
+ } SPPCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :4;\r
+ unsigned char PERF:1;\r
+ unsigned char MODF:1;\r
+ unsigned char IDLNF:1;\r
+ unsigned char OVRF:1;\r
+ } BIT;\r
+ } SPSR;\r
+ union {\r
+ unsigned long LONG;\r
+ struct {\r
+ unsigned short H;\r
+ unsigned short L;\r
+ } WORD;\r
+ } SPDR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :5;\r
+ unsigned char SPSLN:3;\r
+ } BIT;\r
+ } SPSCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char SPECM:3;\r
+ unsigned char :1;\r
+ unsigned char SPCP:3;\r
+ } BIT;\r
+ } SPSSR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char SPR7:1;\r
+ unsigned char SPR6:1;\r
+ unsigned char SPR5:1;\r
+ unsigned char SPR4:1;\r
+ unsigned char SPR3:1;\r
+ unsigned char SPR2:1;\r
+ unsigned char SPR1:1;\r
+ unsigned char SPR0:1;\r
+ } BIT;\r
+ } SPBR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char SPLW:1;\r
+ unsigned char SPRDTD:1;\r
+ unsigned char SLSEL:2;\r
+ unsigned char SPFC:2;\r
+ } BIT;\r
+ } SPDCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :5;\r
+ unsigned char SCKDL:3;\r
+ } BIT;\r
+ } SPCKD;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :5;\r
+ unsigned char SLNDL:3;\r
+ } BIT;\r
+ } SSLND;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :5;\r
+ unsigned char SPNDL:3;\r
+ } BIT;\r
+ } SPND;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :4;\r
+ unsigned char PTE:1;\r
+ unsigned char SPIIE:1;\r
+ unsigned char SPOE:1;\r
+ unsigned char SPPE:1;\r
+ } BIT;\r
+ } SPCR2;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short SCKDEN:1;\r
+ unsigned short SLNDEN:1;\r
+ unsigned short SPNDEN:1;\r
+ unsigned short LSBF:1;\r
+ unsigned short SPB:4;\r
+ unsigned short SSLKP:1;\r
+ unsigned short SSLA:3;\r
+ unsigned short BRDV:2;\r
+ unsigned short CPOL:1;\r
+ unsigned short CPHA:1;\r
+ } BIT;\r
+ } SPCMD0;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short SCKDEN:1;\r
+ unsigned short SLNDEN:1;\r
+ unsigned short SPNDEN:1;\r
+ unsigned short LSBF:1;\r
+ unsigned short SPB:4;\r
+ unsigned short SSLKP:1;\r
+ unsigned short SSLA:3;\r
+ unsigned short BRDV:2;\r
+ unsigned short CPOL:1;\r
+ unsigned short CPHA:1;\r
+ } BIT;\r
+ } SPCMD1;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short SCKDEN:1;\r
+ unsigned short SLNDEN:1;\r
+ unsigned short SPNDEN:1;\r
+ unsigned short LSBF:1;\r
+ unsigned short SPB:4;\r
+ unsigned short SSLKP:1;\r
+ unsigned short SSLA:3;\r
+ unsigned short BRDV:2;\r
+ unsigned short CPOL:1;\r
+ unsigned short CPHA:1;\r
+ } BIT;\r
+ } SPCMD2;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short SCKDEN:1;\r
+ unsigned short SLNDEN:1;\r
+ unsigned short SPNDEN:1;\r
+ unsigned short LSBF:1;\r
+ unsigned short SPB:4;\r
+ unsigned short SSLKP:1;\r
+ unsigned short SSLA:3;\r
+ unsigned short BRDV:2;\r
+ unsigned short CPOL:1;\r
+ unsigned short CPHA:1;\r
+ } BIT;\r
+ } SPCMD3;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short SCKDEN:1;\r
+ unsigned short SLNDEN:1;\r
+ unsigned short SPNDEN:1;\r
+ unsigned short LSBF:1;\r
+ unsigned short SPB:4;\r
+ unsigned short SSLKP:1;\r
+ unsigned short SSLA:3;\r
+ unsigned short BRDV:2;\r
+ unsigned short CPOL:1;\r
+ unsigned short CPHA:1;\r
+ } BIT;\r
+ } SPCMD4;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short SCKDEN:1;\r
+ unsigned short SLNDEN:1;\r
+ unsigned short SPNDEN:1;\r
+ unsigned short LSBF:1;\r
+ unsigned short SPB:4;\r
+ unsigned short SSLKP:1;\r
+ unsigned short SSLA:3;\r
+ unsigned short BRDV:2;\r
+ unsigned short CPOL:1;\r
+ unsigned short CPHA:1;\r
+ } BIT;\r
+ } SPCMD5;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short SCKDEN:1;\r
+ unsigned short SLNDEN:1;\r
+ unsigned short SPNDEN:1;\r
+ unsigned short LSBF:1;\r
+ unsigned short SPB:4;\r
+ unsigned short SSLKP:1;\r
+ unsigned short SSLA:3;\r
+ unsigned short BRDV:2;\r
+ unsigned short CPOL:1;\r
+ unsigned short CPHA:1;\r
+ } BIT;\r
+ } SPCMD6;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short SCKDEN:1;\r
+ unsigned short SLNDEN:1;\r
+ unsigned short SPNDEN:1;\r
+ unsigned short LSBF:1;\r
+ unsigned short SPB:4;\r
+ unsigned short SSLKP:1;\r
+ unsigned short SSLA:3;\r
+ unsigned short BRDV:2;\r
+ unsigned short CPOL:1;\r
+ unsigned short CPHA:1;\r
+ } BIT;\r
+ } SPCMD7;\r
+};\r
+\r
+struct st_mtu {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char OE4D:1;\r
+ unsigned char OE4C:1;\r
+ unsigned char OE3D:1;\r
+ unsigned char OE4B:1;\r
+ unsigned char OE4A:1;\r
+ unsigned char OE3B:1;\r
+ } BIT;\r
+ } TOER;\r
+ unsigned char wk0[2];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char BCD:1;\r
+ unsigned char N:1;\r
+ unsigned char P:1;\r
+ unsigned char FB:1;\r
+ unsigned char WF:1;\r
+ unsigned char VF:1;\r
+ unsigned char UF:1;\r
+ } BIT;\r
+ } TGCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char PSYE:1;\r
+ unsigned char :2;\r
+ unsigned char TOCL:1;\r
+ unsigned char TOCS:1;\r
+ unsigned char OLSN:1;\r
+ unsigned char OLSP:1;\r
+ } BIT;\r
+ } TOCR1;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char BF:2;\r
+ unsigned char OLS3N:1;\r
+ unsigned char OLS3P:1;\r
+ unsigned char OLS2N:1;\r
+ unsigned char OLS2P:1;\r
+ unsigned char OLS1N:1;\r
+ unsigned char OLS1P:1;\r
+ } BIT;\r
+ } TOCR2;\r
+ unsigned char wk1[4];\r
+ unsigned short TCDR;\r
+ unsigned short TDDR;\r
+ unsigned char wk2[8];\r
+ unsigned short TCNTS;\r
+ unsigned short TCBR;\r
+ unsigned char wk3[12];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char T3AEN:1;\r
+ unsigned char T3ACOR:3;\r
+ unsigned char T4VEN:1;\r
+ unsigned char T4VCOR:3;\r
+ } BIT;\r
+ } TITCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char T3ACNT:3;\r
+ unsigned char :1;\r
+ unsigned char T4VCNT:3;\r
+ } BIT;\r
+ } TITCNT;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :6;\r
+ unsigned char BTE:2;\r
+ } BIT;\r
+ } TBTER;\r
+ unsigned char wk4[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char TDRE:1;\r
+ } BIT;\r
+ } TDER;\r
+ unsigned char wk5[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char OLS3N:1;\r
+ unsigned char OLS3P:1;\r
+ unsigned char OLS2N:1;\r
+ unsigned char OLS2P:1;\r
+ unsigned char OLS1N:1;\r
+ unsigned char OLS1P:1;\r
+ } BIT;\r
+ } TOLBR;\r
+ unsigned char wk6[41];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char CCE:1;\r
+ unsigned char :6;\r
+ unsigned char WRE:1;\r
+ } BIT;\r
+ } TWCR;\r
+ unsigned char wk7[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char CST4:1;\r
+ unsigned char CST3:1;\r
+ unsigned char :3;\r
+ unsigned char CST2:1;\r
+ unsigned char CST1:1;\r
+ unsigned char CST0:1;\r
+ } BIT;\r
+ } TSTR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char SYNC4:1;\r
+ unsigned char SYNC3:1;\r
+ unsigned char :3;\r
+ unsigned char SYNC2:1;\r
+ unsigned char SYNC1:1;\r
+ unsigned char SYNC0:1;\r
+ } BIT;\r
+ } TSYR;\r
+ unsigned char wk8[2];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char RWE:1;\r
+ } BIT;\r
+ } TRWER;\r
+};\r
+\r
+struct st_mtu0 {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char CCLR:3;\r
+ unsigned char CKEG:2;\r
+ unsigned char TPSC:3;\r
+ } BIT;\r
+ } TCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char BFE:1;\r
+ unsigned char BFB:1;\r
+ unsigned char BFA:1;\r
+ unsigned char MD:4;\r
+ } BIT;\r
+ } TMDR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char IOB:4;\r
+ unsigned char IOA:4;\r
+ } BIT;\r
+ } TIORH;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char IOD:4;\r
+ unsigned char IOC:4;\r
+ } BIT;\r
+ } TIORL;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char TTGE:1;\r
+ unsigned char :2;\r
+ unsigned char TCIEV:1;\r
+ unsigned char TGIED:1;\r
+ unsigned char TGIEC:1;\r
+ unsigned char TGIEB:1;\r
+ unsigned char TGIEA:1;\r
+ } BIT;\r
+ } TIER;\r
+ unsigned char TSR;\r
+ unsigned short TCNT;\r
+ unsigned short TGRA;\r
+ unsigned short TGRB;\r
+ unsigned short TGRC;\r
+ unsigned short TGRD;\r
+ unsigned char wk0[16];\r
+ unsigned short TGRE;\r
+ unsigned short TGRF;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :6;\r
+ unsigned char TGIEF:1;\r
+ unsigned char TGIEE:1;\r
+ } BIT;\r
+ } TIER2;\r
+ unsigned char wk1[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :5;\r
+ unsigned char TTSE:1;\r
+ unsigned char TTSB:1;\r
+ unsigned char TTSA:1;\r
+ } BIT;\r
+ } TBTM;\r
+};\r
+\r
+struct st_mtu1 {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char CCLR:3;\r
+ unsigned char CKEG:2;\r
+ unsigned char TPSC:3;\r
+ } BIT;\r
+ } TCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :4;\r
+ unsigned char MD:4;\r
+ } BIT;\r
+ } TMDR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char IOB:4;\r
+ unsigned char IOA:4;\r
+ } BIT;\r
+ } TIOR;\r
+ unsigned char wk0[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char TTGE:1;\r
+ unsigned char :1;\r
+ unsigned char TCIEU:1;\r
+ unsigned char TCIEV:1;\r
+ unsigned char :2;\r
+ unsigned char TGIEB:1;\r
+ unsigned char TGIEA:1;\r
+ } BIT;\r
+ } TIER;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char TCFD:1;\r
+ unsigned char :7;\r
+ } BIT;\r
+ } TSR;\r
+ unsigned short TCNT;\r
+ unsigned short TGRA;\r
+ unsigned short TGRB;\r
+ unsigned char wk1[4];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :4;\r
+ unsigned char I2BE:1;\r
+ unsigned char I2AE:1;\r
+ unsigned char I1BE:1;\r
+ unsigned char I1AE:1;\r
+ } BIT;\r
+ } TICCR;\r
+};\r
+\r
+struct st_mtu2 {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char CCLR:3;\r
+ unsigned char CKEG:2;\r
+ unsigned char TPSC:3;\r
+ } BIT;\r
+ } TCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :4;\r
+ unsigned char MD:4;\r
+ } BIT;\r
+ } TMDR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char IOB:4;\r
+ unsigned char IOA:4;\r
+ } BIT;\r
+ } TIOR;\r
+ unsigned char wk0[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char TTGE:1;\r
+ unsigned char :1;\r
+ unsigned char TCIEU:1;\r
+ unsigned char TCIEV:1;\r
+ unsigned char :2;\r
+ unsigned char TGIEB:1;\r
+ unsigned char TGIEA:1;\r
+ } BIT;\r
+ } TIER;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char TCFD:1;\r
+ unsigned char :7;\r
+ } BIT;\r
+ } TSR;\r
+ unsigned short TCNT;\r
+ unsigned short TGRA;\r
+ unsigned short TGRB;\r
+};\r
+\r
+struct st_mtu3 {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char CCLR:3;\r
+ unsigned char CKEG:2;\r
+ unsigned char TPSC:3;\r
+ } BIT;\r
+ } TCR;\r
+ unsigned char wk0[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char BFE:1;\r
+ unsigned char BFB:1;\r
+ unsigned char BFA:1;\r
+ unsigned char MD:4;\r
+ } BIT;\r
+ } TMDR;\r
+ unsigned char wk1[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char IOB:4;\r
+ unsigned char IOA:4;\r
+ } BIT;\r
+ } TIORH;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char IOD:4;\r
+ unsigned char IOC:4;\r
+ } BIT;\r
+ } TIORL;\r
+ unsigned char wk2[2];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char TTGE:1;\r
+ unsigned char TTGE2:1;\r
+ unsigned char TCIEU:1;\r
+ unsigned char TCIEV:1;\r
+ unsigned char TGIED:1;\r
+ unsigned char TGIEC:1;\r
+ unsigned char TGIEB:1;\r
+ unsigned char TGIEA:1;\r
+ } BIT;\r
+ } TIER;\r
+ unsigned char wk3[7];\r
+ unsigned short TCNT;\r
+ unsigned char wk4[6];\r
+ unsigned short TGRA;\r
+ unsigned short TGRB;\r
+ unsigned char wk5[8];\r
+ unsigned short TGRC;\r
+ unsigned short TGRD;\r
+ unsigned char wk6[4];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char TCFD:1;\r
+ unsigned char :7;\r
+ } BIT;\r
+ } TSR;\r
+ unsigned char wk7[11];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :5;\r
+ unsigned char TTSE:1;\r
+ unsigned char TTSB:1;\r
+ unsigned char TTSA:1;\r
+ } BIT;\r
+ } TBTM;\r
+};\r
+\r
+struct st_mtu4 {\r
+ unsigned char DMMY;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char CCLR:3;\r
+ unsigned char CKEG:2;\r
+ unsigned char TPSC:3;\r
+ } BIT;\r
+ } TCR;\r
+ unsigned char wk0[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char BFE:1;\r
+ unsigned char BFB:1;\r
+ unsigned char BFA:1;\r
+ unsigned char MD:4;\r
+ } BIT;\r
+ } TMDR;\r
+ unsigned char wk1[2];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char IOB:4;\r
+ unsigned char IOA:4;\r
+ } BIT;\r
+ } TIORH;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char IOD:4;\r
+ unsigned char IOC:4;\r
+ } BIT;\r
+ } TIORL;\r
+ unsigned char wk2[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char TTGE:1;\r
+ unsigned char TTGE2:1;\r
+ unsigned char TCIEU:1;\r
+ unsigned char TCIEV:1;\r
+ unsigned char TGIED:1;\r
+ unsigned char TGIEC:1;\r
+ unsigned char TGIEB:1;\r
+ unsigned char TGIEA:1;\r
+ } BIT;\r
+ } TIER;\r
+ unsigned char wk3[8];\r
+ unsigned short TCNT;\r
+ unsigned char wk4[8];\r
+ unsigned short TGRA;\r
+ unsigned short TGRB;\r
+ unsigned char wk5[8];\r
+ unsigned short TGRC;\r
+ unsigned short TGRD;\r
+ unsigned char wk6[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char TCFD:1;\r
+ unsigned char :7;\r
+ } BIT;\r
+ } TSR;\r
+ unsigned char wk7[11];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :5;\r
+ unsigned char TTSE:1;\r
+ unsigned char TTSB:1;\r
+ unsigned char TTSA:1;\r
+ } BIT;\r
+ } TBTM;\r
+ unsigned char wk8[6];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short BF:2;\r
+ unsigned short :6;\r
+ unsigned short UT4AE:1;\r
+ unsigned short DT4AE:1;\r
+ unsigned short UT4BE:1;\r
+ unsigned short DT4BE:1;\r
+ unsigned short ITA3AE:1;\r
+ unsigned short ITA4VE:1;\r
+ unsigned short ITB3AE:1;\r
+ unsigned short ITB4VE:1;\r
+ } BIT;\r
+ } TADCR;\r
+ unsigned char wk9[2];\r
+ unsigned short TADCORA;\r
+ unsigned short TADCORB;\r
+ unsigned short TADCOBRA;\r
+ unsigned short TADCOBRB;\r
+};\r
+\r
+struct st_mtu5 {\r
+ unsigned short TCNTU;\r
+ unsigned short TGRU;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char CCLR:3;\r
+ unsigned char CKEG:2;\r
+ unsigned char TPSC:3;\r
+ } BIT;\r
+ } TCRU;\r
+ unsigned char wk0[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char IOC:5;\r
+ } BIT;\r
+ } TIORU;\r
+ unsigned char wk1[9];\r
+ unsigned short TCNTV;\r
+ unsigned short TGRV;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char CCLR:3;\r
+ unsigned char CKEG:2;\r
+ unsigned char TPSC:3;\r
+ } BIT;\r
+ } TCRV;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char IOC:5;\r
+ } BIT;\r
+ } TIORV;\r
+ unsigned char wk2[9];\r
+ unsigned short TCNTW;\r
+ unsigned short TGRW;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char CCLR:3;\r
+ unsigned char CKEG:2;\r
+ unsigned char TPSC:3;\r
+ } BIT;\r
+ } TCRW;\r
+ unsigned char wk3[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char IOC:5;\r
+ } BIT;\r
+ } TIORW;\r
+ unsigned char wk4[11];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :5;\r
+ unsigned char TGIE5U:1;\r
+ unsigned char TGIE5V:1;\r
+ unsigned char TGIE5W:1;\r
+ } BIT;\r
+ } TIER;\r
+ unsigned char wk5[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :5;\r
+ unsigned char CSTU5:1;\r
+ unsigned char CSTV5:1;\r
+ unsigned char CSTW5:1;\r
+ } BIT;\r
+ } TSTR;\r
+ unsigned char wk6[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :5;\r
+ unsigned char CMPCLR5U:1;\r
+ unsigned char CMPCLR5V:1;\r
+ unsigned char CMPCLR5W:1;\r
+ } BIT;\r
+ } TCNTCMPCLR;\r
+};\r
+\r
+struct st_poe {\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short POE3F:1;\r
+ unsigned short POE2F:1;\r
+ unsigned short POE1F:1;\r
+ unsigned short POE0F:1;\r
+ unsigned short :3;\r
+ unsigned short PIE1:1;\r
+ unsigned short POE3M:2;\r
+ unsigned short POE2M:2;\r
+ unsigned short POE1M:2;\r
+ unsigned short POE0M:2;\r
+ } BIT;\r
+ } ICSR1;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short OSF1:1;\r
+ unsigned short :5;\r
+ unsigned short OCE1:1;\r
+ unsigned short OIE1:1;\r
+ unsigned short :8;\r
+ } BIT;\r
+ } OCSR1;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short POE7F:1;\r
+ unsigned short POE6F:1;\r
+ unsigned short POE5F:1;\r
+ unsigned short POE4F:1;\r
+ unsigned short :3;\r
+ unsigned short PIE2:1;\r
+ unsigned short POE7M:2;\r
+ unsigned short POE6M:2;\r
+ unsigned short POE5M:2;\r
+ unsigned short POE4M:2;\r
+ } BIT;\r
+ } ICSR2;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short OSF2:1;\r
+ unsigned short :5;\r
+ unsigned short OCE2:1;\r
+ unsigned short OIE2:1;\r
+ unsigned short :8;\r
+ } BIT;\r
+ } OCSR2;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :3;\r
+ unsigned short POE8F:1;\r
+ unsigned short :2;\r
+ unsigned short POE8E:1;\r
+ unsigned short PIE3:1;\r
+ unsigned short :6;\r
+ unsigned short POE8M:2;\r
+ } BIT;\r
+ } ICSR3;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :4;\r
+ unsigned char CH6HIZ:1;\r
+ unsigned char CH910HIZ:1;\r
+ unsigned char CH0HIZ:1;\r
+ unsigned char CH34HIZ:1;\r
+ } BIT;\r
+ } SPOER;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char PE7ZE:1;\r
+ unsigned char PE6ZE:1;\r
+ unsigned char PE5ZE:1;\r
+ unsigned char PE4ZE:1;\r
+ unsigned char PE3ZE:1;\r
+ unsigned char PE2ZE:1;\r
+ unsigned char PE1ZE:1;\r
+ unsigned char PE0ZE:1;\r
+ } BIT;\r
+ } POECR1;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :1;\r
+ unsigned short P1CZEA:1;\r
+ unsigned short P2CZEA:1;\r
+ unsigned short P3CZEA:1;\r
+ unsigned short :1;\r
+ unsigned short P1CZEB:1;\r
+ unsigned short P2CZEB:1;\r
+ unsigned short P3CZEB:1;\r
+ unsigned short :1;\r
+ unsigned short P4CZE:1;\r
+ unsigned short P5CZE:1;\r
+ unsigned short P6CZE:1;\r
+ unsigned short :4;\r
+ } BIT;\r
+ } POECR2;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :3;\r
+ unsigned short POE9F:1;\r
+ unsigned short :2;\r
+ unsigned short POE9E:1;\r
+ unsigned short PIE4:1;\r
+ unsigned short :6;\r
+ unsigned short POE9M:2;\r
+ } BIT;\r
+ } ICSR4;\r
+};\r
+\r
+struct st_s12ad {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ADST:1;\r
+ unsigned char ADCS:1;\r
+ unsigned char :1;\r
+ unsigned char ADIE:1;\r
+ unsigned char CKS:2;\r
+ unsigned char TRGE:1;\r
+ unsigned char EXTRG:1;\r
+ } BIT;\r
+ } ADCSR;\r
+ unsigned char wk0[3];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :8;\r
+ unsigned short ANS:8;\r
+ } BIT;\r
+ } ADANS;\r
+ unsigned char wk1[2];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :8;\r
+ unsigned short ADS:8;\r
+ } BIT;\r
+ } ADADS;\r
+ unsigned char wk2[2];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :6;\r
+ unsigned char ADC:2;\r
+ } BIT;\r
+ } ADADC;\r
+ unsigned char wk3[1];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short ADRFMT:1;\r
+ unsigned short :9;\r
+ unsigned short ACE:1;\r
+ unsigned short :5;\r
+ } BIT;\r
+ } ADCER;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :4;\r
+ unsigned char ADSTRS:4;\r
+ } BIT;\r
+ } ADSTRGR;\r
+ unsigned char wk4[15];\r
+ unsigned short ADDRA;\r
+ unsigned short ADDRB;\r
+ unsigned short ADDRC;\r
+ unsigned short ADDRD;\r
+ unsigned short ADDRE;\r
+ unsigned short ADDRF;\r
+ unsigned short ADDRG;\r
+ unsigned short ADDRH;\r
+};\r
+\r
+struct st_port0 {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char :1;\r
+ unsigned char B5:1;\r
+ unsigned char :1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } DDR;\r
+ unsigned char wk0[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char :1;\r
+ unsigned char B5:1;\r
+ unsigned char :1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } DR;\r
+ unsigned char wk1[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char :1;\r
+ unsigned char B5:1;\r
+ unsigned char :1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PORT;\r
+ unsigned char wk2[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char :1;\r
+ unsigned char B5:1;\r
+ unsigned char :1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } ICR;\r
+ unsigned char wk3[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char :1;\r
+ unsigned char B5:1;\r
+ unsigned char :1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } ODR;\r
+};\r
+\r
+struct st_port1 {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } DDR;\r
+ unsigned char wk0[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } DR;\r
+ unsigned char wk1[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PORT;\r
+ unsigned char wk2[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } ICR;\r
+ unsigned char wk3[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } ODR;\r
+};\r
+\r
+struct st_port2 {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } DDR;\r
+ unsigned char wk0[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } DR;\r
+ unsigned char wk1[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PORT;\r
+ unsigned char wk2[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } ICR;\r
+ unsigned char wk3[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } ODR;\r
+};\r
+\r
+struct st_port3 {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } DDR;\r
+ unsigned char wk0[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } DR;\r
+ unsigned char wk1[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PORT;\r
+ unsigned char wk2[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } ICR;\r
+ unsigned char wk3[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } ODR;\r
+};\r
+\r
+struct st_port4 {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } DDR;\r
+ unsigned char wk0[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } DR;\r
+ unsigned char wk1[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PORT;\r
+ unsigned char wk2[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } ICR;\r
+};\r
+\r
+struct st_port5 {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } DDR;\r
+ unsigned char wk0[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } DR;\r
+ unsigned char wk1[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PORT;\r
+ unsigned char wk2[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } ICR;\r
+};\r
+\r
+struct st_port6 {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } DDR;\r
+ unsigned char wk0[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } DR;\r
+ unsigned char wk1[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PORT;\r
+ unsigned char wk2[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } ICR;\r
+};\r
+\r
+struct st_port7 {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } DDR;\r
+ unsigned char wk0[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } DR;\r
+ unsigned char wk1[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PORT;\r
+ unsigned char wk2[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } ICR;\r
+};\r
+\r
+struct st_port8 {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } DDR;\r
+ unsigned char wk0[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } DR;\r
+ unsigned char wk1[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PORT;\r
+ unsigned char wk2[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } ICR;\r
+};\r
+\r
+struct st_port9 {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } DDR;\r
+ unsigned char wk0[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } DR;\r
+ unsigned char wk1[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PORT;\r
+ unsigned char wk2[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } ICR;\r
+ unsigned char wk3[95];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PCR;\r
+};\r
+\r
+struct st_porta {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } DDR;\r
+ unsigned char wk0[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } DR;\r
+ unsigned char wk1[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PORT;\r
+ unsigned char wk2[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } ICR;\r
+ unsigned char wk3[95];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PCR;\r
+};\r
+\r
+struct st_portb {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } DDR;\r
+ unsigned char wk0[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } DR;\r
+ unsigned char wk1[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PORT;\r
+ unsigned char wk2[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } ICR;\r
+ unsigned char wk3[95];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PCR;\r
+};\r
+\r
+struct st_portc {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } DDR;\r
+ unsigned char wk0[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } DR;\r
+ unsigned char wk1[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PORT;\r
+ unsigned char wk2[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } ICR;\r
+ unsigned char wk3[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } ODR;\r
+ unsigned char wk4[63];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PCR;\r
+};\r
+\r
+struct st_portd {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } DDR;\r
+ unsigned char wk0[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } DR;\r
+ unsigned char wk1[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PORT;\r
+ unsigned char wk2[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } ICR;\r
+ unsigned char wk3[95];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PCR;\r
+};\r
+\r
+struct st_porte {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } DDR;\r
+ unsigned char wk0[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } DR;\r
+ unsigned char wk1[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PORT;\r
+ unsigned char wk2[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } ICR;\r
+ unsigned char wk3[95];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PCR;\r
+};\r
+\r
+struct st_portf {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } DDR;\r
+ unsigned char wk0[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } DR;\r
+ unsigned char wk1[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PORT;\r
+ unsigned char wk2[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } ICR;\r
+};\r
+\r
+struct st_portg {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } DDR;\r
+ unsigned char wk0[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } DR;\r
+ unsigned char wk1[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PORT;\r
+ unsigned char wk2[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } ICR;\r
+ unsigned char wk3[95];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PCR;\r
+};\r
+\r
+struct st_ioport {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char CS7E:1;\r
+ unsigned char CS6E:1;\r
+ unsigned char CS5E:1;\r
+ unsigned char CS4E:1;\r
+ unsigned char CS3E:1;\r
+ unsigned char CS2E:1;\r
+ unsigned char CS1E:1;\r
+ unsigned char CS0E:1;\r
+ } BIT;\r
+ } PF0CSE;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char CS7S:2;\r
+ unsigned char CS6S:2;\r
+ unsigned char CS5S:2;\r
+ unsigned char CS4S:2;\r
+ } BIT;\r
+ } PF1CSS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char CS3S:2;\r
+ unsigned char CS2S:2;\r
+ unsigned char CS1S:2;\r
+ unsigned char :1;\r
+ unsigned char CS0S:1;\r
+ } BIT;\r
+ } PF2CSS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char A23E:1;\r
+ unsigned char A22E:1;\r
+ unsigned char A21E:1;\r
+ unsigned char A20E:1;\r
+ unsigned char A19E:1;\r
+ unsigned char A18E:1;\r
+ unsigned char A17E:1;\r
+ unsigned char A16E:1;\r
+ } BIT;\r
+ } PF3BUS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char A15E:1;\r
+ unsigned char A14E:1;\r
+ unsigned char A13E:1;\r
+ unsigned char A12E:1;\r
+ unsigned char A11E:1;\r
+ unsigned char A10E:1;\r
+ unsigned char ADRLE:2;\r
+ } BIT;\r
+ } PF4BUS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char WR32BC32E:1;\r
+ unsigned char WR1BC1E:1;\r
+ unsigned char DH32E:1;\r
+ unsigned char DHE:1;\r
+ unsigned char :2;\r
+ unsigned char ADRHMS:1;\r
+ unsigned char :1;\r
+ } BIT;\r
+ } PF5BUS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char SDCLKE:1;\r
+ unsigned char DQM1E:1;\r
+ unsigned char :1;\r
+ unsigned char MDSDE:1;\r
+ unsigned char :2;\r
+ unsigned char WAITS:2;\r
+ } BIT;\r
+ } PF6BUS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char EDMA1S:2;\r
+ unsigned char EDMA0S:2;\r
+ unsigned char :4;\r
+ } BIT;\r
+ } PF7DMA;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ITS15:1;\r
+ unsigned char :1;\r
+ unsigned char ITS13:1;\r
+ unsigned char :1;\r
+ unsigned char ITS11:1;\r
+ unsigned char ITS10:1;\r
+ unsigned char ITS9:1;\r
+ unsigned char ITS8:1;\r
+ } BIT;\r
+ } PF8IRQ;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ITS7:1;\r
+ unsigned char ITS6:1;\r
+ unsigned char ITS5:1;\r
+ unsigned char ITS4:1;\r
+ unsigned char ITS3:1;\r
+ unsigned char ITS2:1;\r
+ unsigned char ITS1:1;\r
+ unsigned char ITS0:1;\r
+ } BIT;\r
+ } PF9IRQ;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char ADTRG0S:1;\r
+ } BIT;\r
+ } PFAADC;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :4;\r
+ unsigned char TMR3S:1;\r
+ unsigned char TMR2S:1;\r
+ unsigned char :2;\r
+ } BIT;\r
+ } PFBTMR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char TCLKS:1;\r
+ unsigned char MTUS6:1;\r
+ unsigned char MTUS5:1;\r
+ unsigned char MTUS4:1;\r
+ unsigned char MTUS3:1;\r
+ unsigned char MTUS2:1;\r
+ unsigned char MTUS1:1;\r
+ unsigned char MTUS0:1;\r
+ } BIT;\r
+ } PFCMTU;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char TCLKS:1;\r
+ unsigned char MTUS6:1;\r
+ unsigned char :6;\r
+ } BIT;\r
+ } PFDMTU;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char EE:1;\r
+ unsigned char :2;\r
+ unsigned char PHYMODE:1;\r
+ unsigned char ENETE3:1;\r
+ unsigned char ENETE2:1;\r
+ unsigned char ENETE1:1;\r
+ unsigned char ENETE0:1;\r
+ } BIT;\r
+ } PFENET;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char SCI6S:1;\r
+ unsigned char :2;\r
+ unsigned char SCI3S:1;\r
+ unsigned char SCI2S:1;\r
+ unsigned char SCI1S:1;\r
+ unsigned char :1;\r
+ } BIT;\r
+ } PFFSCI;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char SSL3E:1;\r
+ unsigned char SSL2E:1;\r
+ unsigned char SSL1E:1;\r
+ unsigned char SSL0E:1;\r
+ unsigned char MISOE:1;\r
+ unsigned char MOSIE:1;\r
+ unsigned char RSPCKE:1;\r
+ unsigned char RSPIS:1;\r
+ } BIT;\r
+ } PFGSPI;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char SSL3E:1;\r
+ unsigned char SSL2E:1;\r
+ unsigned char SSL1E:1;\r
+ unsigned char SSL0E:1;\r
+ unsigned char MISOE:1;\r
+ unsigned char MOSIE:1;\r
+ unsigned char RSPCKE:1;\r
+ unsigned char RSPIS:1;\r
+ } BIT;\r
+ } PFHSPI;\r
+ unsigned char wk0[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char CAN0E:1;\r
+ } BIT;\r
+ } PFJCAN;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char USBE:1;\r
+ unsigned char PDHZS:1;\r
+ unsigned char PUPHZS:1;\r
+ unsigned char USBMD:2;\r
+ } BIT;\r
+ } PFKUSB;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char USBE:1;\r
+ unsigned char PDHZS:1;\r
+ unsigned char PUPHZS:1;\r
+ unsigned char USBMD:2;\r
+ } BIT;\r
+ } PFLUSB;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char POE7E:1;\r
+ unsigned char POE6E:1;\r
+ unsigned char POE5E:1;\r
+ unsigned char POE4E:1;\r
+ unsigned char POE3E:1;\r
+ unsigned char POE2E:1;\r
+ unsigned char POE1E:1;\r
+ unsigned char POE0E:1;\r
+ } BIT;\r
+ } PFMPOE;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :6;\r
+ unsigned char POE9E:1;\r
+ unsigned char POE8E:1;\r
+ } BIT;\r
+ } PFNPOE;\r
+};\r
+\r
+struct st_flash {\r
+ unsigned char DMMY;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :6;\r
+ unsigned char FLWE:2;\r
+ } BIT;\r
+ } FWEPROR;\r
+ unsigned char wk0[7799160];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char FRDMD:1;\r
+ unsigned char :4;\r
+ } BIT;\r
+ } FMODR;\r
+ unsigned char wk1[13];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ROMAE:1;\r
+ unsigned char :2;\r
+ unsigned char CMDLK:1;\r
+ unsigned char DFLAE:1;\r
+ unsigned char :1;\r
+ unsigned char DFLRPE:1;\r
+ unsigned char DFLWPE:1;\r
+ } BIT;\r
+ } FASTAT;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ROMAEIE:1;\r
+ unsigned char :2;\r
+ unsigned char CMDLKIE:1;\r
+ unsigned char DFLAEIE:1;\r
+ unsigned char :1;\r
+ unsigned char DFLRPEIE:1;\r
+ unsigned char DFLWPEIE:1;\r
+ } BIT;\r
+ } FAEINT;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char FRDYIE:1;\r
+ } BIT;\r
+ } FRDYIE;\r
+ unsigned char wk2[45];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short KEY:8;\r
+ unsigned short DBRE07:1;\r
+ unsigned short DBRE06:1;\r
+ unsigned short DBRE05:1;\r
+ unsigned short DBRE04:1;\r
+ unsigned short DBRE03:1;\r
+ unsigned short DBRE02:1;\r
+ unsigned short DBRE01:1;\r
+ unsigned short DBRE00:1;\r
+ } BIT;\r
+ } DFLRE0;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short KEY:8;\r
+ unsigned short DBRE15:1;\r
+ unsigned short DBRE14:1;\r
+ unsigned short DBRE13:1;\r
+ unsigned short DBRE12:1;\r
+ unsigned short DBRE11:1;\r
+ unsigned short DBRE10:1;\r
+ unsigned short DBRE09:1;\r
+ unsigned short DBRE08:1;\r
+ } BIT;\r
+ } DFLRE1;\r
+ unsigned char wk3[12];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short KEY:8;\r
+ unsigned short DBWE07:1;\r
+ unsigned short DBWE06:1;\r
+ unsigned short DBWE05:1;\r
+ unsigned short DBWE04:1;\r
+ unsigned short DBWE03:1;\r
+ unsigned short DBWE02:1;\r
+ unsigned short DBWE01:1;\r
+ unsigned short DBWE00:1;\r
+ } BIT;\r
+ } DFLWE0;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short KEY:8;\r
+ unsigned short DBWE15:1;\r
+ unsigned short DBWE14:1;\r
+ unsigned short DBWE13:1;\r
+ unsigned short DBWE12:1;\r
+ unsigned short DBWE11:1;\r
+ unsigned short DBWE10:1;\r
+ unsigned short DBWE09:1;\r
+ unsigned short DBWE08:1;\r
+ } BIT;\r
+ } DFLWE1;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short KEY:8;\r
+ unsigned short :7;\r
+ unsigned short FCRME:1;\r
+ } BIT;\r
+ } FCURAME;\r
+ unsigned char wk4[15194];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char FRDY:1;\r
+ unsigned char ILGLERR:1;\r
+ unsigned char ERSERR:1;\r
+ unsigned char PRGERR:1;\r
+ unsigned char SUSRDY:1;\r
+ unsigned char :1;\r
+ unsigned char ERSSPD:1;\r
+ unsigned char PRGSPD:1;\r
+ } BIT;\r
+ } FSTATR0;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char FCUERR:1;\r
+ unsigned char :2;\r
+ unsigned char FLOCKST:1;\r
+ unsigned char :4;\r
+ } BIT;\r
+ } FSTATR1;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short FEKEY:8;\r
+ unsigned short FENTRYD:1;\r
+ unsigned short :6;\r
+ unsigned short FENTRY0:1;\r
+ } BIT;\r
+ } FENTRYR;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short FPKEY:8;\r
+ unsigned short :7;\r
+ unsigned short FPROTCN:1;\r
+ } BIT;\r
+ } FPROTR;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short FPKEY:8;\r
+ unsigned short :7;\r
+ unsigned short FRESET:1;\r
+ } BIT;\r
+ } FRESETR;\r
+ unsigned char wk5[2];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short CMDR:8;\r
+ unsigned short PCMDR:8;\r
+ } BIT;\r
+ } FCMDR;\r
+ unsigned char wk6[12];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :15;\r
+ unsigned short ESUSPMD:1;\r
+ } BIT;\r
+ } FCPSR;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :5;\r
+ unsigned short BCADR:8;\r
+ unsigned short :2;\r
+ unsigned short BCSIZE:1;\r
+ } BIT;\r
+ } DFLBCCNT;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :8;\r
+ unsigned short PEERRST:8;\r
+ } BIT;\r
+ } FPESTAT;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :15;\r
+ unsigned short BCST:1;\r
+ } BIT;\r
+ } DFLBCSTAT;\r
+ unsigned char wk7[24];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :8;\r
+ unsigned short PCKA:8;\r
+ } BIT;\r
+ } PCKAR;\r
+};\r
+\r
+struct st_rtc {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char F64HZ:1;\r
+ unsigned char F32HZ:1;\r
+ unsigned char F16HZ:1;\r
+ unsigned char F8HZ:1;\r
+ unsigned char F4HZ:1;\r
+ unsigned char F2HZ:1;\r
+ unsigned char F1HZ:1;\r
+ unsigned char :1;\r
+ } BIT;\r
+ } R64CNT;\r
+ unsigned char wk0[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char SEC10:3;\r
+ unsigned char SEC1:4;\r
+ } BIT;\r
+ } RSECCNT;\r
+ unsigned char wk1[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char MIN10:3;\r
+ unsigned char MIN1:4;\r
+ } BIT;\r
+ } RMINCNT;\r
+ unsigned char wk2[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char HOUR10:2;\r
+ unsigned char HOUR1:4;\r
+ } BIT;\r
+ } RHRCNT;\r
+ unsigned char wk3[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :5;\r
+ unsigned char DAY:3;\r
+ } BIT;\r
+ } RWKCNT;\r
+ unsigned char wk4[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char DAY10:2;\r
+ unsigned char DAY1:4;\r
+ } BIT;\r
+ } RDAYCNT;\r
+ unsigned char wk5[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char MON10:1;\r
+ unsigned char MON1:4;\r
+ } BIT;\r
+ } RMONCNT;\r
+ unsigned char wk6[1];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short YEAR1000:4;\r
+ unsigned short YEAR100:4;\r
+ unsigned short YEAR10:4;\r
+ unsigned short YEAR1:4;\r
+ } BIT;\r
+ } RYRCNT;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ENB:1;\r
+ unsigned char SEC10:3;\r
+ unsigned char SEC1:4;\r
+ } BIT;\r
+ } RSECAR;\r
+ unsigned char wk7[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ENB:1;\r
+ unsigned char MIN10:3;\r
+ unsigned char MIN1:4;\r
+ } BIT;\r
+ } RMINAR;\r
+ unsigned char wk8[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ENB:1;\r
+ unsigned char :1;\r
+ unsigned char HOUR10:2;\r
+ unsigned char HOUR1:4;\r
+ } BIT;\r
+ } RHRAR;\r
+ unsigned char wk9[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ENB:1;\r
+ unsigned char :4;\r
+ unsigned char DAY:3;\r
+ } BIT;\r
+ } RWKAR;\r
+ unsigned char wk10[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ENB:1;\r
+ unsigned char :1;\r
+ unsigned char DAY10:2;\r
+ unsigned char DAY1:4;\r
+ } BIT;\r
+ } RDAYAR;\r
+ unsigned char wk11[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ENB:1;\r
+ unsigned char :2;\r
+ unsigned char MON10:1;\r
+ unsigned char MON1:4;\r
+ } BIT;\r
+ } RMONAR;\r
+ unsigned char wk12[1];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short YEAR1000:4;\r
+ unsigned short YEAR100:4;\r
+ unsigned short YEAR10:4;\r
+ unsigned short YEAR1:4;\r
+ } BIT;\r
+ } RYRAR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ENB:1;\r
+ unsigned char :7;\r
+ } BIT;\r
+ } RYRAREN;\r
+ unsigned char wk13[3];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char PES:3;\r
+ unsigned char :1;\r
+ unsigned char PIE:1;\r
+ unsigned char CIE:1;\r
+ unsigned char AIE:1;\r
+ } BIT;\r
+ } RCR1;\r
+ unsigned char wk14[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :4;\r
+ unsigned char RTCOE:1;\r
+ unsigned char ADJ:1;\r
+ unsigned char RESET:1;\r
+ unsigned char START:1;\r
+ } BIT;\r
+ } RCR2;\r
+};\r
+\r
+struct st_can {\r
+ struct {\r
+ union {\r
+ unsigned long LONG;\r
+ union {\r
+ unsigned short H;\r
+ unsigned short L;\r
+ } WORD;\r
+ struct {\r
+ unsigned char HH;\r
+ unsigned char HL;\r
+ unsigned char LH;\r
+ unsigned char LL;\r
+ } BYTE;\r
+ struct {\r
+ unsigned long IDE:1;\r
+ unsigned long RTR:1;\r
+ unsigned long :1;\r
+ unsigned long SID:11;\r
+ unsigned long EID:18;\r
+ } BIT;\r
+ } ID;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned char :8;\r
+ unsigned char :4;\r
+ unsigned char DLC:4;\r
+ } BIT;\r
+ } DLC;\r
+ unsigned char DATA[8];\r
+ union{ \r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned char TSH;\r
+ unsigned char TSL;\r
+ } BYTE;\r
+ } TS;\r
+ } MB[32];\r
+ union {\r
+ unsigned long LONG;\r
+ struct {\r
+ unsigned short H;\r
+ unsigned short L;\r
+ } WORD;\r
+ struct {\r
+ unsigned char HH;\r
+ unsigned char HL;\r
+ unsigned char LH;\r
+ unsigned char LL;\r
+ } BYTE;\r
+ struct {\r
+ unsigned long :3;\r
+ unsigned long SID:11;\r
+ unsigned long EID:18;\r
+ } BIT;\r
+ } MKR[8];\r
+ union {\r
+ unsigned long LONG;\r
+ struct {\r
+ unsigned short H;\r
+ unsigned short L;\r
+ } WORD;\r
+ struct {\r
+ unsigned char HH;\r
+ unsigned char HL;\r
+ unsigned char LH;\r
+ unsigned char LL;\r
+ } BYTE;\r
+ struct {\r
+ unsigned long IDE:1;\r
+ unsigned long RTR:1;\r
+ unsigned long :1;\r
+ unsigned long SID:11;\r
+ unsigned long EID:18;\r
+ } BIT;\r
+ } FIDCR0;\r
+ union {\r
+ unsigned long LONG;\r
+ struct {\r
+ unsigned short H;\r
+ unsigned short L;\r
+ } WORD;\r
+ struct {\r
+ unsigned char HH;\r
+ unsigned char HL;\r
+ unsigned char LH;\r
+ unsigned char LL;\r
+ } BYTE;\r
+ struct {\r
+ unsigned long IDE:1;\r
+ unsigned long RTR:1;\r
+ unsigned long :1;\r
+ unsigned long SID:11;\r
+ unsigned long EID:18;\r
+ } BIT;\r
+ } FIDCR1;\r
+ unsigned long MKIVLR;\r
+ unsigned long MIER;\r
+ unsigned char wk32[1008];\r
+ union {\r
+ unsigned char BYTE;\r
+ union {\r
+ struct {\r
+ unsigned char TRMREQ:1;\r
+ unsigned char RECREQ:1;\r
+ unsigned char :1;\r
+ unsigned char ONESHOT:1;\r
+ unsigned char :1;\r
+ unsigned char TRMABT:1;\r
+ unsigned char TRMACTIVE:1;\r
+ unsigned char SENTDATA:1;\r
+ } TX;\r
+ struct {\r
+ unsigned char TRMREQ:1;\r
+ unsigned char RECREQ:1;\r
+ unsigned char :1;\r
+ unsigned char ONESHOT:1;\r
+ unsigned char :1;\r
+ unsigned char MSGLOST:1;\r
+ unsigned char INVALDATA:1;\r
+ unsigned char NEWDATA:1;\r
+ } RX;\r
+ } BIT;\r
+ } MCTL[32];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned char H;\r
+ unsigned char L;\r
+ } BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char RBOC:1;\r
+ unsigned char BOM:2;\r
+ unsigned char SLPM:1;\r
+ unsigned char CANM:2;\r
+ unsigned char TSPS:2;\r
+ unsigned char TSRC:1;\r
+ unsigned char TPM:1;\r
+ unsigned char MLM:1;\r
+ unsigned char IDFM:2;\r
+ unsigned char MBM:1;\r
+ } BIT;\r
+ } CTLR;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned char H;\r
+ unsigned char L;\r
+ } BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char RECST:1;\r
+ unsigned char TRMST:1;\r
+ unsigned char BOST:1;\r
+ unsigned char EPST:1;\r
+ unsigned char SLPST:1;\r
+ unsigned char HLTST:1;\r
+ unsigned char RSTST:1;\r
+ unsigned char EST:1;\r
+ unsigned char TABST:1;\r
+ unsigned char FMLST:1;\r
+ unsigned char NMLST:1;\r
+ unsigned char TFST:1;\r
+ unsigned char RFST:1;\r
+ unsigned char SDST:1;\r
+ unsigned char NDST:1;\r
+ } BIT;\r
+ } STR;\r
+ union {\r
+ unsigned long LONG;\r
+ struct {\r
+ unsigned short H;\r
+ unsigned short L;\r
+ } WORD;\r
+ struct {\r
+ unsigned char HH;\r
+ unsigned char HL;\r
+ unsigned char LH;\r
+ unsigned char LL;\r
+ } BYTE;\r
+ struct {\r
+ unsigned long TSEG1:4;\r
+ unsigned long :2;\r
+ unsigned long BRP:10;\r
+ unsigned long :2;\r
+ unsigned long SJW:2;\r
+ unsigned long :1;\r
+ unsigned long TSEG2:3;\r
+ unsigned long :8;\r
+ } BIT;\r
+ } BCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char RFEST:1;\r
+ unsigned char RFWST:1;\r
+ unsigned char RFFST:1;\r
+ unsigned char RFMLF:1;\r
+ unsigned char RFUST:3;\r
+ unsigned char RFE:1;\r
+ } BIT;\r
+ } RFCR;\r
+ unsigned char RFPCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char TFEST:1;\r
+ unsigned char TFFST:1;\r
+ unsigned char :2;\r
+ unsigned char TFUST:3;\r
+ unsigned char TFE:1;\r
+ } BIT;\r
+ } TFCR;\r
+ unsigned char TFPCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char BLIE:1;\r
+ unsigned char OLIE:1;\r
+ unsigned char ORIE:1;\r
+ unsigned char BORIE:1;\r
+ unsigned char BOEIE:1;\r
+ unsigned char EPIE:1;\r
+ unsigned char EWIE:1;\r
+ unsigned char BEIE:1;\r
+ } BIT;\r
+ } EIER;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char BLIF:1;\r
+ unsigned char OLIF:1;\r
+ unsigned char ORIF:1;\r
+ unsigned char BORIF:1;\r
+ unsigned char BOEIF:1;\r
+ unsigned char EPIF:1;\r
+ unsigned char EWIF:1;\r
+ unsigned char BEIF:1;\r
+ } BIT;\r
+ } EIFR;\r
+ unsigned char RECR;\r
+ unsigned char TECR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char EDPM:1;\r
+ unsigned char ADEF:1;\r
+ unsigned char BE0F:1;\r
+ unsigned char BE1F:1;\r
+ unsigned char CEF:1;\r
+ unsigned char AEF:1;\r
+ unsigned char FEF:1;\r
+ unsigned char SEF:1;\r
+ } BIT;\r
+ } ECSR;\r
+ unsigned char CSSR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char SEST:1;\r
+ unsigned char :2;\r
+ unsigned char MBNST:5;\r
+ } BIT;\r
+ } MSSR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :6;\r
+ unsigned char MBSM:2;\r
+ } BIT;\r
+ } MSMR;\r
+ unsigned short TSR;\r
+ unsigned short AFSR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :5;\r
+ unsigned char TSTM:2;\r
+ unsigned char TSTE:1;\r
+ } BIT;\r
+ } TCR;\r
+};\r
+\r
+struct st_usb0 {\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :5;\r
+ unsigned short SCKE:1;\r
+ unsigned short :3;\r
+ unsigned short DCFM:1;\r
+ unsigned short DRPD:1;\r
+ unsigned short DPRPU:1;\r
+ unsigned short :3;\r
+ unsigned short USBE:1;\r
+ } BIT;\r
+ } SYSCFG;\r
+ unsigned char wk0[2];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short OVCMON:2;\r
+ unsigned short :7;\r
+ unsigned short HTACT:1;\r
+ unsigned short :3;\r
+ unsigned short IDMON:1;\r
+ unsigned short LNST:2;\r
+ } BIT;\r
+ } SYSSTS0;\r
+ unsigned char wk1[2];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :4;\r
+ unsigned short HNPBTOA:1;\r
+ unsigned short EXICEN:1;\r
+ unsigned short VBUSEN:1;\r
+ unsigned short WKUP:1;\r
+ unsigned short RWUPE:1;\r
+ unsigned short USBRST:1;\r
+ unsigned short RESUME:1;\r
+ unsigned short UACT:1;\r
+ unsigned short :1;\r
+ unsigned short RHST:3;\r
+ } BIT;\r
+ } DVSTCTR0;\r
+ unsigned char wk2[10];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned char L;\r
+ unsigned char H;\r
+ } BYTE;\r
+ } CFIFO;\r
+ unsigned char wk3[2];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned char L;\r
+ unsigned char H;\r
+ } BYTE;\r
+ } D0FIFO;\r
+ unsigned char wk4[2];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned char L;\r
+ unsigned char H;\r
+ } BYTE;\r
+ } D1FIFO;\r
+ unsigned char wk5[2];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short RCNT:1;\r
+ unsigned short REW:1;\r
+ unsigned short :3;\r
+ unsigned short MBW:1;\r
+ unsigned short :1;\r
+ unsigned short BIGEND:1;\r
+ unsigned short :2;\r
+ unsigned short ISEL:1;\r
+ unsigned short :1;\r
+ unsigned short CURPIPE:4;\r
+ } BIT;\r
+ } CFIFOSEL;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short BVAL:1;\r
+ unsigned short BCLR:1;\r
+ unsigned short FRDY:1;\r
+ unsigned short :4;\r
+ unsigned short TLN:1;\r
+ unsigned short DTLN:8;\r
+ } BIT;\r
+ } CFIFOCTR;\r
+ unsigned char wk6[4];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short RCNT:1;\r
+ unsigned short REW:1;\r
+ unsigned short DCLRM:1;\r
+ unsigned short DREQE:1;\r
+ unsigned short :1;\r
+ unsigned short MBW:1;\r
+ unsigned short :1;\r
+ unsigned short BIGEND:1;\r
+ unsigned short :4;\r
+ unsigned short CURPIPE:4;\r
+ } BIT;\r
+ } D0FIFOSEL;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short BVAL:1;\r
+ unsigned short BCLR:1;\r
+ unsigned short FRDY:1;\r
+ unsigned short :4;\r
+ unsigned short TLN:1;\r
+ unsigned short DTLN:8;\r
+ } BIT;\r
+ } D0FIFOCTR;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short RCNT:1;\r
+ unsigned short REW:1;\r
+ unsigned short DCLRM:1;\r
+ unsigned short DREQE:1;\r
+ unsigned short :1;\r
+ unsigned short MBW:1;\r
+ unsigned short :1;\r
+ unsigned short BIGEND:1;\r
+ unsigned short :4;\r
+ unsigned short CURPIPE:4;\r
+ } BIT;\r
+ } D1FIFOSEL;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short BVAL:1;\r
+ unsigned short BCLR:1;\r
+ unsigned short FRDY:1;\r
+ unsigned short :4;\r
+ unsigned short TLN:1;\r
+ unsigned short DTLN:8;\r
+ } BIT;\r
+ } D1FIFOCTR;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short VBSE:1;\r
+ unsigned short RSME:1;\r
+ unsigned short SOFE:1;\r
+ unsigned short DVSE:1;\r
+ unsigned short CTRE:1;\r
+ unsigned short BEMPE:1;\r
+ unsigned short NRDYE:1;\r
+ unsigned short BRDYE:1;\r
+ unsigned short :8;\r
+ } BIT;\r
+ } INTENB0;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short OVRCRE:1;\r
+ unsigned short BCHGE:1;\r
+ unsigned short :1;\r
+ unsigned short DTCHE:1;\r
+ unsigned short ATTCHE:1;\r
+ unsigned short :4;\r
+ unsigned short EOFERRE:1;\r
+ unsigned short SIGNE:1;\r
+ unsigned short SACKE:1;\r
+ unsigned short :4;\r
+ } BIT;\r
+ } INTENB1;\r
+ unsigned char wk7[2];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :6;\r
+ unsigned short PIPE9BRDYE:1;\r
+ unsigned short PIPE8BRDYE:1;\r
+ unsigned short PIPE7BRDYE:1;\r
+ unsigned short PIPE6BRDYE:1;\r
+ unsigned short PIPE5BRDYE:1;\r
+ unsigned short PIPE4BRDYE:1;\r
+ unsigned short PIPE3BRDYE:1;\r
+ unsigned short PIPE2BRDYE:1;\r
+ unsigned short PIPE1BRDYE:1;\r
+ unsigned short PIPE0BRDYE:1;\r
+ } BIT;\r
+ } BRDYENB;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :6;\r
+ unsigned short PIPE9BRDYE:1;\r
+ unsigned short PIPE8BRDYE:1;\r
+ unsigned short PIPE7BRDYE:1;\r
+ unsigned short PIPE6BRDYE:1;\r
+ unsigned short PIPE5BRDYE:1;\r
+ unsigned short PIPE4BRDYE:1;\r
+ unsigned short PIPE3BRDYE:1;\r
+ unsigned short PIPE2BRDYE:1;\r
+ unsigned short PIPE1BRDYE:1;\r
+ unsigned short PIPE0BRDYE:1;\r
+ } BIT;\r
+ } NRDYENB;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :6;\r
+ unsigned short PIPE9BEMPE:1;\r
+ unsigned short PIPE8BEMPE:1;\r
+ unsigned short PIPE7BEMPE:1;\r
+ unsigned short PIPE6BEMPE:1;\r
+ unsigned short PIPE5BEMPE:1;\r
+ unsigned short PIPE4BEMPE:1;\r
+ unsigned short PIPE3BEMPE:1;\r
+ unsigned short PIPE2BEMPE:1;\r
+ unsigned short PIPE1BEMPE:1;\r
+ unsigned short PIPE0BEMPE:1;\r
+ } BIT;\r
+ } BEMPENB;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :7;\r
+ unsigned short TRNENSEL:1;\r
+ unsigned short :1;\r
+ unsigned short BRDYM:1;\r
+ unsigned short :1;\r
+ unsigned short EDGESTS:1;\r
+ unsigned short :4;\r
+ } BIT;\r
+ } SOFCFG;\r
+ unsigned char wk8[2];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short VBINT:1;\r
+ unsigned short RESM:1;\r
+ unsigned short SOFR:1;\r
+ unsigned short DVST:1;\r
+ unsigned short CTRT:1;\r
+ unsigned short BEMP:1;\r
+ unsigned short NRDY:1;\r
+ unsigned short BRDY:1;\r
+ unsigned short VBSTS:1;\r
+ unsigned short DVSQ:3;\r
+ unsigned short VALID:1;\r
+ unsigned short CTSQ:3;\r
+ } BIT;\r
+ } INTSTS0;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short OVRCR:1;\r
+ unsigned short BCHG:1;\r
+ unsigned short :1;\r
+ unsigned short DTCH:1;\r
+ unsigned short ATTCH:1;\r
+ unsigned short :4;\r
+ unsigned short EOFERR:1;\r
+ unsigned short SIGN:1;\r
+ unsigned short SACK:1;\r
+ unsigned short :4;\r
+ } BIT;\r
+ } INTSTS1;\r
+ unsigned char wk9[2];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :6;\r
+ unsigned short PIPE9BRDY:1;\r
+ unsigned short PIPE8BRDY:1;\r
+ unsigned short PIPE7BRDY:1;\r
+ unsigned short PIPE6BRDY:1;\r
+ unsigned short PIPE5BRDY:1;\r
+ unsigned short PIPE4BRDY:1;\r
+ unsigned short PIPE3BRDY:1;\r
+ unsigned short PIPE2BRDY:1;\r
+ unsigned short PIPE1BRDY:1;\r
+ unsigned short PIPE0BRDY:1;\r
+ } BIT;\r
+ } BRDYSTS;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :6;\r
+ unsigned short PIPE9BRDY:1;\r
+ unsigned short PIPE8BRDY:1;\r
+ unsigned short PIPE7BRDY:1;\r
+ unsigned short PIPE6BRDY:1;\r
+ unsigned short PIPE5BRDY:1;\r
+ unsigned short PIPE4BRDY:1;\r
+ unsigned short PIPE3BRDY:1;\r
+ unsigned short PIPE2BRDY:1;\r
+ unsigned short PIPE1BRDY:1;\r
+ unsigned short PIPE0BRDY:1;\r
+ } BIT;\r
+ } NRDYSTS;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :6;\r
+ unsigned short PIPE9BENP:1;\r
+ unsigned short PIPE8BENP:1;\r
+ unsigned short PIPE7BENP:1;\r
+ unsigned short PIPE6BENP:1;\r
+ unsigned short PIPE5BENP:1;\r
+ unsigned short PIPE4BENP:1;\r
+ unsigned short PIPE3BENP:1;\r
+ unsigned short PIPE2BENP:1;\r
+ unsigned short PIPE1BENP:1;\r
+ unsigned short PIPE0BENP:1;\r
+ } BIT;\r
+ } BEMPSTS;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short OVRN:1;\r
+ unsigned short CRCE:1;\r
+ unsigned short :3;\r
+ unsigned short FRNM:11;\r
+ } BIT;\r
+ } FRMNUM;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short DVCHG:1;\r
+ unsigned short :15;\r
+ } BIT;\r
+ } DVCHGR;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :4;\r
+ unsigned short STSRECOV:4;\r
+ unsigned short :1;\r
+ unsigned short USBADDR:7;\r
+ } BIT;\r
+ } USBADDR;\r
+ unsigned char wk10[2];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short BREQUEST:8;\r
+ unsigned short BMREQUESTTYPE:8;\r
+ } BIT;\r
+ } USBREQ;\r
+ unsigned short USBVAL;\r
+ unsigned short USBINDX;\r
+ unsigned short USBLENG;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :8;\r
+ unsigned short SHTNAK:1;\r
+ unsigned short :2;\r
+ unsigned short DIR:1;\r
+ unsigned short :4;\r
+ } BIT;\r
+ } DCPCFG;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short DEVSEL:4;\r
+ unsigned short :5;\r
+ unsigned short MXPS:7;\r
+ } BIT;\r
+ } DCPMAXP;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short BSTS:1;\r
+ unsigned short SUREQ:1;\r
+ unsigned short :2;\r
+ unsigned short SUREQCLR:1;\r
+ unsigned short :2;\r
+ unsigned short SQCLR:1;\r
+ unsigned short SQSET:1;\r
+ unsigned short SQMON:1;\r
+ unsigned short PBUSY:1;\r
+ unsigned short :2;\r
+ unsigned short CCPL:1;\r
+ unsigned short PID:2;\r
+ } BIT;\r
+ } DCPCTR;\r
+ unsigned char wk11[2];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :12;\r
+ unsigned short PIPESEL:4;\r
+ } BIT;\r
+ } PIPESEL;\r
+ unsigned char wk12[2];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short TYPE:2;\r
+ unsigned short :3;\r
+ unsigned short BFRE:1;\r
+ unsigned short DBLB:1;\r
+ unsigned short :1;\r
+ unsigned short SHTNAK:1;\r
+ unsigned short :2;\r
+ unsigned short DIR:1;\r
+ unsigned short EPNUM:4;\r
+ } BIT;\r
+ } PIPECFG;\r
+ unsigned char wk13[2];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short DEVSEL:4;\r
+ unsigned short :3;\r
+ unsigned short XPS:1;\r
+ unsigned short MXPS:8;\r
+ } BIT;\r
+ } PIPEMAXP;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :3;\r
+ unsigned short IFIS:1;\r
+ unsigned short :9;\r
+ unsigned short IITV:3;\r
+ } BIT;\r
+ } PIPEPERI;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short BSTS:1;\r
+ unsigned short INBUFM:1;\r
+ unsigned short :3;\r
+ unsigned short ATREPM:1;\r
+ unsigned short ACLRM:1;\r
+ unsigned short SQCLR:1;\r
+ unsigned short SQSET:1;\r
+ unsigned short SQMON:1;\r
+ unsigned short PBUSY:1;\r
+ unsigned short :3;\r
+ unsigned short PID:2;\r
+ } BIT;\r
+ } PIPE1CTR;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short BSTS:1;\r
+ unsigned short INBUFM:1;\r
+ unsigned short :3;\r
+ unsigned short ATREPM:1;\r
+ unsigned short ACLRM:1;\r
+ unsigned short SQCLR:1;\r
+ unsigned short SQSET:1;\r
+ unsigned short SQMON:1;\r
+ unsigned short PBUSY:1;\r
+ unsigned short :3;\r
+ unsigned short PID:2;\r
+ } BIT;\r
+ } PIPE2CTR;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short BSTS:1;\r
+ unsigned short INBUFM:1;\r
+ unsigned short :3;\r
+ unsigned short ATREPM:1;\r
+ unsigned short ACLRM:1;\r
+ unsigned short SQCLR:1;\r
+ unsigned short SQSET:1;\r
+ unsigned short SQMON:1;\r
+ unsigned short PBUSY:1;\r
+ unsigned short :3;\r
+ unsigned short PID:2;\r
+ } BIT;\r
+ } PIPE3CTR;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short BSTS:1;\r
+ unsigned short INBUFM:1;\r
+ unsigned short :3;\r
+ unsigned short ATREPM:1;\r
+ unsigned short ACLRM:1;\r
+ unsigned short SQCLR:1;\r
+ unsigned short SQSET:1;\r
+ unsigned short SQMON:1;\r
+ unsigned short PBUSY:1;\r
+ unsigned short :3;\r
+ unsigned short PID:2;\r
+ } BIT;\r
+ } PIPE4CTR;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short BSTS:1;\r
+ unsigned short INBUFM:1;\r
+ unsigned short :3;\r
+ unsigned short ATREPM:1;\r
+ unsigned short ACLRM:1;\r
+ unsigned short SQCLR:1;\r
+ unsigned short SQSET:1;\r
+ unsigned short SQMON:1;\r
+ unsigned short PBUSY:1;\r
+ unsigned short :3;\r
+ unsigned short PID:2;\r
+ } BIT;\r
+ } PIPE5CTR;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short BSTS:1;\r
+ unsigned short :5;\r
+ unsigned short ACLRM:1;\r
+ unsigned short SQCLR:1;\r
+ unsigned short SQSET:1;\r
+ unsigned short SQMON:1;\r
+ unsigned short PBUSY:1;\r
+ unsigned short :3;\r
+ unsigned short PID:2;\r
+ } BIT;\r
+ } PIPE6CTR;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short BSTS:1;\r
+ unsigned short :5;\r
+ unsigned short ACLRM:1;\r
+ unsigned short SQCLR:1;\r
+ unsigned short SQSET:1;\r
+ unsigned short SQMON:1;\r
+ unsigned short PBUSY:1;\r
+ unsigned short :3;\r
+ unsigned short PID:2;\r
+ } BIT;\r
+ } PIPE7CTR;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short BSTS:1;\r
+ unsigned short :5;\r
+ unsigned short ACLRM:1;\r
+ unsigned short SQCLR:1;\r
+ unsigned short SQSET:1;\r
+ unsigned short SQMON:1;\r
+ unsigned short PBUSY:1;\r
+ unsigned short :3;\r
+ unsigned short PID:2;\r
+ } BIT;\r
+ } PIPE8CTR;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short BSTS:1;\r
+ unsigned short :5;\r
+ unsigned short ACLRM:1;\r
+ unsigned short SQCLR:1;\r
+ unsigned short SQSET:1;\r
+ unsigned short SQMON:1;\r
+ unsigned short PBUSY:1;\r
+ unsigned short :3;\r
+ unsigned short PID:2;\r
+ } BIT;\r
+ } PIPE9CTR;\r
+ unsigned char wk14[14];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :6;\r
+ unsigned short TRENB:1;\r
+ unsigned short TRCLR:1;\r
+ unsigned short :8;\r
+ } BIT;\r
+ } PIPE1TRE;\r
+ unsigned short PIPE1TRN;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :6;\r
+ unsigned short TRENB:1;\r
+ unsigned short TRCLR:1;\r
+ unsigned short :8;\r
+ } BIT;\r
+ } PIPE2TRE;\r
+ unsigned short PIPE2TRN;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :6;\r
+ unsigned short TRENB:1;\r
+ unsigned short TRCLR:1;\r
+ unsigned short :8;\r
+ } BIT;\r
+ } PIPE3TRE;\r
+ unsigned short PIPE3TRN;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :6;\r
+ unsigned short TRENB:1;\r
+ unsigned short TRCLR:1;\r
+ unsigned short :8;\r
+ } BIT;\r
+ } PIPE4TRE;\r
+ unsigned short PIPE4TRN;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :6;\r
+ unsigned short TRENB:1;\r
+ unsigned short TRCLR:1;\r
+ unsigned short :8;\r
+ } BIT;\r
+ } PIPE5TRE;\r
+ unsigned short PIPE5TRN;\r
+ unsigned char wk15[44];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :8;\r
+ unsigned short USBSPD:2;\r
+ unsigned short :6;\r
+ } BIT;\r
+ } DEVADD0;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :8;\r
+ unsigned short USBSPD:2;\r
+ unsigned short :6;\r
+ } BIT;\r
+ } DEVADD1;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :8;\r
+ unsigned short USBSPD:2;\r
+ unsigned short :6;\r
+ } BIT;\r
+ } DEVADD2;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :8;\r
+ unsigned short USBSPD:2;\r
+ unsigned short :6;\r
+ } BIT;\r
+ } DEVADD3;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :8;\r
+ unsigned short USBSPD:2;\r
+ unsigned short :6;\r
+ } BIT;\r
+ } DEVADD4;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :8;\r
+ unsigned short USBSPD:2;\r
+ unsigned short :6;\r
+ } BIT;\r
+ } DEVADD5;\r
+};\r
+\r
+struct st_usb {\r
+ union {\r
+ unsigned long LONG;\r
+ struct {\r
+ unsigned long DVSTS1:1;\r
+ unsigned long :1;\r
+ unsigned long DOVCB1:1;\r
+ unsigned long DOVCA1:1;\r
+ unsigned long :2;\r
+ unsigned long DM1:1;\r
+ unsigned long DP1:1;\r
+ unsigned long DVBSTS0:1;\r
+ unsigned long :1;\r
+ unsigned long DOVCB0:1;\r
+ unsigned long DOVCA0:1;\r
+ unsigned long :2;\r
+ unsigned long DM0:1;\r
+ unsigned long DP0:1;\r
+ unsigned long :3;\r
+ unsigned long FIXPHY1:1;\r
+ unsigned long :3;\r
+ unsigned long SRPC1:1;\r
+ unsigned long :3;\r
+ unsigned long FIXPHY0:1;\r
+ unsigned long :3;\r
+ unsigned long SRPC0:1;\r
+ } BIT;\r
+ } DPUSR0R;\r
+ union {\r
+ unsigned long LONG;\r
+ struct {\r
+ unsigned long DVBINT1:1;\r
+ unsigned long :1;\r
+ unsigned long DOVRCRB1:1;\r
+ unsigned long DOVRCRA1:1;\r
+ unsigned long :2;\r
+ unsigned long DMINT1:1;\r
+ unsigned long DPINT1:1;\r
+ unsigned long DVBINT0:1;\r
+ unsigned long :1;\r
+ unsigned long DOVRCRB0:1;\r
+ unsigned long DOVRCRA0:1;\r
+ unsigned long :2;\r
+ unsigned long DMINT0:1;\r
+ unsigned long DPINT0:1;\r
+ unsigned long DVBSE1:1;\r
+ unsigned long :1;\r
+ unsigned long DOVRCRBE1:1;\r
+ unsigned long DOVRCRAE1:1;\r
+ unsigned long :2;\r
+ unsigned long DMINTE1:1;\r
+ unsigned long DPINTE1:1;\r
+ unsigned long DVBSE0:1;\r
+ unsigned long :1;\r
+ unsigned long DOVRCRBE0:1;\r
+ unsigned long DOVRCRAE0:1;\r
+ unsigned long :2;\r
+ unsigned long DMINTE0:1;\r
+ unsigned long DPINTE0:1;\r
+ } BIT;\r
+ } DPUSR1R;\r
+};\r
+\r
+struct st_edmac {\r
+ union {\r
+ unsigned long LONG;\r
+ struct {\r
+ unsigned long :25;\r
+ unsigned long DE:1;\r
+ unsigned long DL:2;\r
+ unsigned long :3;\r
+ unsigned long SWR:1;\r
+ } BIT;\r
+ } EDMR;\r
+ unsigned char wk0[4];\r
+ union {\r
+ unsigned long LONG;\r
+ struct {\r
+ unsigned long :31;\r
+ unsigned long TR:1;\r
+ } BIT;\r
+ } EDTRR;\r
+ unsigned char wk1[4];\r
+ union {\r
+ unsigned long LONG;\r
+ struct {\r
+ unsigned long :31;\r
+ unsigned long RR:1;\r
+ } BIT;\r
+ } EDRRR;\r
+ unsigned char wk2[4];\r
+ void *TDLAR;\r
+ unsigned char wk3[4];\r
+ void *RDLAR;\r
+ unsigned char wk4[4];\r
+ union {\r
+ unsigned long LONG;\r
+ struct {\r
+ unsigned long :1;\r
+ unsigned long TWB:1;\r
+ unsigned long :3;\r
+ unsigned long TABT:1;\r
+ unsigned long RABT:1;\r
+ unsigned long RFCOF:1;\r
+ unsigned long ADE:1;\r
+ unsigned long ECI:1;\r
+ unsigned long TC:1;\r
+ unsigned long TDE:1;\r
+ unsigned long TFUF:1;\r
+ unsigned long FR:1;\r
+ unsigned long RDE:1;\r
+ unsigned long RFOF:1;\r
+ unsigned long :4;\r
+ unsigned long CND:1;\r
+ unsigned long DLC:1;\r
+ unsigned long CD:1;\r
+ unsigned long TRO:1;\r
+ unsigned long RMAF:1;\r
+ unsigned long :2;\r
+ unsigned long RRF:1;\r
+ unsigned long RTLF:1;\r
+ unsigned long RTSF:1;\r
+ unsigned long PRE:1;\r
+ unsigned long CERF:1;\r
+ } BIT;\r
+ } EESR;\r
+ unsigned char wk5[4];\r
+ union {\r
+ unsigned long LONG;\r
+ struct {\r
+ unsigned long :1;\r
+ unsigned long TWBIP:1;\r
+ unsigned long :3;\r
+ unsigned long TABTIP:1;\r
+ unsigned long RABTIP:1;\r
+ unsigned long RFCOFIP:1;\r
+ unsigned long ADEIP:1;\r
+ unsigned long ECIIP:1;\r
+ unsigned long TCIP:1;\r
+ unsigned long TDEIP:1;\r
+ unsigned long TFUFIP:1;\r
+ unsigned long FRIP:1;\r
+ unsigned long RDEIP:1;\r
+ unsigned long RFOFIP:1;\r
+ unsigned long :4;\r
+ unsigned long CNDIP:1;\r
+ unsigned long DLCIP:1;\r
+ unsigned long CDIP:1;\r
+ unsigned long TROIP:1;\r
+ unsigned long RMAFIP:1;\r
+ unsigned long :2;\r
+ unsigned long RRFIP:1;\r
+ unsigned long RTLFIP:1;\r
+ unsigned long RTSFIP:1;\r
+ unsigned long PREIP:1;\r
+ unsigned long CERFIP:1;\r
+ } BIT;\r
+ } EESIPR;\r
+ unsigned char wk6[4];\r
+ union {\r
+ unsigned long LONG;\r
+ struct {\r
+ unsigned long :20;\r
+ unsigned long CNDCE:1;\r
+ unsigned long DLCCE:1;\r
+ unsigned long CDCE:1;\r
+ unsigned long TROCE:1;\r
+ unsigned long RMAFCE:1;\r
+ unsigned long :2;\r
+ unsigned long RRFCE:1;\r
+ unsigned long RTLFCE:1;\r
+ unsigned long RTSFCE:1;\r
+ unsigned long PRECE:1;\r
+ unsigned long CERFCE:1;\r
+ } BIT;\r
+ } TRSCER;\r
+ unsigned char wk7[4];\r
+ union {\r
+ unsigned long LONG;\r
+ struct {\r
+ unsigned long :16;\r
+ unsigned long MFC:16;\r
+ } BIT;\r
+ } RMFCR;\r
+ unsigned char wk8[4];\r
+ union {\r
+ unsigned long LONG;\r
+ struct {\r
+ unsigned long :21;\r
+ unsigned long TFT:11;\r
+ } BIT;\r
+ } TFTR;\r
+ unsigned char wk9[4];\r
+ union {\r
+ unsigned long LONG;\r
+ struct {\r
+ unsigned long :19;\r
+ unsigned long TFD:5;\r
+ unsigned long :3;\r
+ unsigned long RFD:5;\r
+ } BIT;\r
+ } FDR;\r
+ unsigned char wk10[4];\r
+ union {\r
+ unsigned long LONG;\r
+ struct {\r
+ unsigned long :30;\r
+ unsigned long RNC:1;\r
+ unsigned long RNR:1;\r
+ } BIT;\r
+ } RMCR;\r
+ unsigned char wk11[8];\r
+ union {\r
+ unsigned long LONG;\r
+ struct {\r
+ unsigned long :16;\r
+ unsigned long UNDER:16;\r
+ } BIT;\r
+ } TFUCR;\r
+ union {\r
+ unsigned long LONG;\r
+ struct {\r
+ unsigned long :16;\r
+ unsigned long OVER:16;\r
+ } BIT;\r
+ } RFOCR;\r
+ union {\r
+ unsigned long LONG;\r
+ struct {\r
+ unsigned long :31;\r
+ unsigned long TLB:1;\r
+ } BIT;\r
+ } IOSR;\r
+ union {\r
+ unsigned long LONG;\r
+ struct {\r
+ unsigned long :13;\r
+ unsigned long RFFO:3;\r
+ unsigned long :13;\r
+ unsigned long RFDO:3;\r
+ } BIT;\r
+ } FCFTR;\r
+ unsigned char wk12[4];\r
+ union {\r
+ unsigned long LONG;\r
+ struct {\r
+ unsigned long :14;\r
+ unsigned long PADS:2;\r
+ unsigned long :10;\r
+ unsigned long PADR:6;\r
+ } BIT;\r
+ } RPADIR;\r
+ union {\r
+ unsigned long LONG;\r
+ struct {\r
+ unsigned long :27;\r
+ unsigned long TIM:1;\r
+ unsigned long :3;\r
+ unsigned long TIS:1;\r
+ } BIT;\r
+ } TRIMD;\r
+ unsigned char wk13[72];\r
+ void *RBWAR;\r
+ void *RDFAR;\r
+ unsigned char wk14[4];\r
+ void *TBRAR;\r
+ void *TDFAR;\r
+};\r
+\r
+struct st_etherc {\r
+ union {\r
+ unsigned long LONG;\r
+ struct {\r
+ unsigned long :11;\r
+ unsigned long TPC:1;\r
+ unsigned long ZPE:1;\r
+ unsigned long PFR:1;\r
+ unsigned long RXF:1;\r
+ unsigned long TXF:1;\r
+ unsigned long :3;\r
+ unsigned long PRCEF:1;\r
+ unsigned long :2;\r
+ unsigned long MPDE:1;\r
+ unsigned long :2;\r
+ unsigned long RE:1;\r
+ unsigned long TE:1;\r
+ unsigned long :1;\r
+ unsigned long ILB:1;\r
+ unsigned long RTM:1;\r
+ unsigned long DM:1;\r
+ unsigned long PRM:1;\r
+ } BIT;\r
+ } ECMR;\r
+ unsigned char wk0[4];\r
+ union {\r
+ unsigned long LONG;\r
+ struct {\r
+ unsigned long :20;\r
+ unsigned long RFL:12;\r
+ } BIT;\r
+ } RFLR;\r
+ unsigned char wk1[4];\r
+ union {\r
+ unsigned long LONG;\r
+ struct {\r
+ unsigned long :26;\r
+ unsigned long BFR:1;\r
+ unsigned long PSRTO:1;\r
+ unsigned long :1;\r
+ unsigned long LCHNG:1;\r
+ unsigned long MPD:1;\r
+ unsigned long ICD:1;\r
+ } BIT;\r
+ } ECSR;\r
+ unsigned char wk2[4];\r
+ union {\r
+ unsigned long LONG;\r
+ struct {\r
+ unsigned long :26;\r
+ unsigned long BFSIPR:1;\r
+ unsigned long PSRTOIP:1;\r
+ unsigned long :1;\r
+ unsigned long LCHNGIP:1;\r
+ unsigned long MPDIP:1;\r
+ unsigned long ICDIP:1;\r
+ } BIT;\r
+ } ECSIPR;\r
+ unsigned char wk3[4];\r
+ union {\r
+ unsigned long LONG;\r
+ struct {\r
+ unsigned long :28;\r
+ unsigned long MDI:1;\r
+ unsigned long MDO:1;\r
+ unsigned long MMD:1;\r
+ unsigned long MDC:1;\r
+ } BIT;\r
+ } PIR;\r
+ unsigned char wk4[4];\r
+ union {\r
+ unsigned long LONG;\r
+ struct {\r
+ unsigned long :31;\r
+ unsigned long LMON:1;\r
+ } BIT;\r
+ } PSR;\r
+ unsigned char wk5[20];\r
+ union {\r
+ unsigned long LONG;\r
+ struct {\r
+ unsigned long :12;\r
+ unsigned long RMD:20;\r
+ } BIT;\r
+ } RDMLR;\r
+ unsigned char wk6[12];\r
+ union {\r
+ unsigned long LONG;\r
+ struct {\r
+ unsigned long :27;\r
+ unsigned long IPG:5;\r
+ } BIT;\r
+ } IPGR;\r
+ union {\r
+ unsigned long LONG;\r
+ struct {\r
+ unsigned long :16;\r
+ unsigned long AP:16;\r
+ } BIT;\r
+ } APR;\r
+ union {\r
+ unsigned long LONG;\r
+ struct {\r
+ unsigned long :16;\r
+ unsigned long MP:16;\r
+ } BIT;\r
+ } MPR;\r
+ unsigned char wk7[4];\r
+ union {\r
+ unsigned long LONG;\r
+ struct {\r
+ unsigned long :24;\r
+ unsigned long RPAUSE:8;\r
+ } BIT;\r
+ } RFCF;\r
+ union {\r
+ unsigned long LONG;\r
+ struct {\r
+ unsigned long :16;\r
+ unsigned long TPAUSE:16;\r
+ } BIT;\r
+ } TPAUSER;\r
+ union {\r
+ unsigned long LONG;\r
+ struct {\r
+ unsigned long :24;\r
+ unsigned long TXP:8;\r
+ } BIT;\r
+ } TPAUSECR;\r
+ union {\r
+ unsigned long LONG;\r
+ struct {\r
+ unsigned long :16;\r
+ unsigned long BCF:16;\r
+ } BIT;\r
+ } BCFRR;\r
+ unsigned char wk8[80];\r
+ unsigned long MAHR;\r
+ unsigned char wk9[4];\r
+ union {\r
+ unsigned long LONG;\r
+ struct {\r
+ unsigned long :16;\r
+ unsigned long MA:16;\r
+ } BIT;\r
+ } MALR;\r
+ unsigned char wk10[4];\r
+ unsigned long TROCR;\r
+ unsigned long CDCR;\r
+ unsigned long LCCR;\r
+ unsigned long CNDCR;\r
+ unsigned char wk11[4];\r
+ unsigned long CEFCR;\r
+ unsigned long FRECR;\r
+ unsigned long TSFRCR;\r
+ unsigned long TLFRCR;\r
+ unsigned long RFCR;\r
+ unsigned long MAFCR;\r
+};\r
+\r
+enum enum_ir {\r
+IR_BSC_BUSERR=16,\r
+IR_FCU_FIFERR=21,IR_FCU_FRDYI=23,\r
+IR_ICU_SWINT=27,\r
+IR_CMT0_CMI0,\r
+IR_CMT1_CMI1,\r
+IR_CMT2_CMI2,\r
+IR_CMT3_CMI3,\r
+IR_ETHER_EINT,\r
+IR_USB0_D0FIFO0=36,IR_USB0_D1FIFO0,IR_USB0_USBI0,\r
+IR_USB1_D0FIFO1=40,IR_USB1_D1FIFO1,IR_USB1_USBI1,\r
+IR_RSPI0_SPEI0=44,IR_RSPI0_SPRI0,IR_RSPI0_SPTI0,IR_RSPI0_SPII0,\r
+IR_RSPI1_SPEI1,IR_RSPI1_SPRI1,IR_RSPI1_SPTI1,IR_RSPI1_SPII1,\r
+IR_CAN0_ERS0=56,IR_CAN0_RXF0,IR_CAN0_TXF0,IR_CAN0_RXM0,IR_CAN0_TXM0,\r
+IR_RTC_PRD=62,IR_RTC_CUP,\r
+IR_ICU_IRQ0,IR_ICU_IRQ1,IR_ICU_IRQ2,IR_ICU_IRQ3,IR_ICU_IRQ4,IR_ICU_IRQ5,IR_ICU_IRQ6,IR_ICU_IRQ7,IR_ICU_IRQ8,IR_ICU_IRQ9,IR_ICU_IRQ10,IR_ICU_IRQ11,IR_ICU_IRQ12,IR_ICU_IRQ13,IR_ICU_IRQ14,IR_ICU_IRQ15,\r
+IR_USB_USBR0=90,IR_USB_USBR1,\r
+IR_RTC_ALM,\r
+IR_WDT_WOVI=96,\r
+IR_AD0_ADI0=98,\r
+IR_AD1_ADI1,\r
+IR_S12AD_ADI=102,\r
+IR_MTU0_TGIA0=114,IR_MTU0_TGIB0,IR_MTU0_TGIC0,IR_MTU0_TGID0,IR_MTU0_TCIV0,IR_MTU0_TGIE0,IR_MTU0_TGIF0,\r
+IR_MTU1_TGIA1,IR_MTU1_TGIB1,IR_MTU1_TCIV1,IR_MTU1_TCIU1,\r
+IR_MTU2_TGIA2,IR_MTU2_TGIB2,IR_MTU2_TCIV2,IR_MTU2_TCIU2,\r
+IR_MTU3_TGIA3,IR_MTU3_TGIB3,IR_MTU3_TGIC3,IR_MTU3_TGID3,IR_MTU3_TCIV3,\r
+IR_MTU4_TGIA4,IR_MTU4_TGIB4,IR_MTU4_TGIC4,IR_MTU4_TGID4,IR_MTU4_TCIV4,\r
+IR_MTU5_TGIU5,IR_MTU5_TGIV5,IR_MTU5_TGIW5,\r
+IR_MTU6_TGIA6,IR_MTU6_TGIB6,IR_MTU6_TGIC6,IR_MTU6_TGID6,IR_MTU6_TCIV6,IR_MTU6_TGIE6,IR_MTU6_TGIF6,\r
+IR_MTU7_TGIA7,IR_MTU7_TGIB7,IR_MTU7_TCIV7,IR_MTU7_TCIU7,\r
+IR_MTU8_TGIA8,IR_MTU8_TGIB8,IR_MTU8_TCIV8,IR_MTU8_TCIU8,\r
+IR_MTU9_TGIA9,IR_MTU9_TGIB9,IR_MTU9_TGIC9,IR_MTU9_TGID9,IR_MTU9_TCIV9,\r
+IR_MTU10_TGIA10,IR_MTU10_TGIB10,IR_MTU10_TGIC10,IR_MTU10_TGID10,IR_MTU10_TCIV10,\r
+IR_MTU11_TGIU11,IR_MTU11_TGIV11,IR_MTU11_TGIW11,\r
+IR_POE_OEI1,IR_POE_OEI2,IR_POE_OEI3,IR_POE_OEI4,\r
+IR_TMR0_CMIA0,IR_TMR0_CMIB0,IR_TMR0_OVI0,\r
+IR_TMR1_CMIA1,IR_TMR1_CMIB1,IR_TMR1_OVI1,\r
+IR_TMR2_CMIA2,IR_TMR2_CMIB2,IR_TMR2_OVI2,\r
+IR_TMR3_CMIA3,IR_TMR3_CMIB3,IR_TMR3_OVI3,\r
+IR_DMACA_DMAC0I=198,IR_DMACA_DMAC1I,IR_DMACA_DMAC2I,IR_DMACA_DMAC3I,\r
+IR_EXDMAC_EXDMAC0I,IR_EXDMAC_EXDMAC1I,\r
+IR_SCI0_ERI0=214,IR_SCI0_RXI0,IR_SCI0_TXI0,IR_SCI0_TEI0,\r
+IR_SCI1_ERI1,IR_SCI1_RXI1,IR_SCI1_TXI1,IR_SCI1_TEI1,\r
+IR_SCI2_ERI2,IR_SCI2_RXI2,IR_SCI2_TXI2,IR_SCI2_TEI2,\r
+IR_SCI3_ERI3,IR_SCI3_RXI3,IR_SCI3_TXI3,IR_SCI3_TEI3,\r
+IR_SCI5_ERI5=234,IR_SCI5_RXI5,IR_SCI5_TXI5,IR_SCI5_TEI5,\r
+IR_SCI6_ERI6,IR_SCI6_RXI6,IR_SCI6_TXI6,IR_SCI6_TEI6,\r
+IR_RIIC0_ICEEI0=246,IR_RIIC0_ICRXI0,IR_RIIC0_ICTXI0,IR_RIIC0_ICTEI0,\r
+IR_RIIC1_ICEEI1,IR_RIIC1_ICRXI1,IR_RIIC1_ICTXI1,IR_RIIC1_ICTEI1\r
+};\r
+\r
+enum enum_dtce {\r
+DTCE_BSC_BUSERR=16,\r
+DTCE_FCU_FIFERR=21,DTCE_FCU_FRDYI=23,\r
+DTCE_ICU_SWINT=27,\r
+DTCE_CMT0_CMI0,\r
+DTCE_CMT1_CMI1,\r
+DTCE_CMT2_CMI2,\r
+DTCE_CMT3_CMI3,\r
+DTCE_ETHER_EINT,\r
+DTCE_USB0_D0FIFO0=36,DTCE_USB0_D1FIFO0,DTCE_USB0_USBI0,\r
+DTCE_USB1_D0FIFO1=40,DTCE_USB1_D1FIFO1,DTCE_USB1_USBI1,\r
+DTCE_RSPI0_SPEI0=44,DTCE_RSPI0_SPRI0,DTCE_RSPI0_SPTI0,DTCE_RSPI0_SPII0,\r
+DTCE_RSPI1_SPEI1,DTCE_RSPI1_SPRI1,DTCE_RSPI1_SPTI1,DTCE_RSPI1_SPII1,\r
+DTCE_CAN0_ERS0=56,DTCE_CAN0_RXF0,DTCE_CAN0_TXF0,DTCE_CAN0_RXM0,DTCE_CAN0_TXM0,\r
+DTCE_RTC_PRD=62,DTCE_RTC_CUP,\r
+DTCE_ICU_IRQ0,DTCE_ICU_IRQ1,DTCE_ICU_IRQ2,DTCE_ICU_IRQ3,DTCE_ICU_IRQ4,DTCE_ICU_IRQ5,DTCE_ICU_IRQ6,DTCE_ICU_IRQ7,DTCE_ICU_IRQ8,DTCE_ICU_IRQ9,DTCE_ICU_IRQ10,DTCE_ICU_IRQ11,DTCE_ICU_IRQ12,DTCE_ICU_IRQ13,DTCE_ICU_IRQ14,DTCE_ICU_IRQ15,\r
+DTCE_USB_USBR0=90,DTCE_USB_USBR1,\r
+DTCE_RTC_ALM,\r
+DTCE_WDT_WOVI=96,\r
+DTCE_AD0_ADI0=98,\r
+DTCE_AD1_ADI1,\r
+DTCE_S12AD_ADI=102,\r
+DTCE_MTU0_TGIA0=114,DTCE_MTU0_TGIB0,DTCE_MTU0_TGIC0,DTCE_MTU0_TGID0,DTCE_MTU0_TCIV0,DTCE_MTU0_TGIE0,DTCE_MTU0_TGIF0,\r
+DTCE_MTU1_TGIA1,DTCE_MTU1_TGIB1,DTCE_MTU1_TCIV1,DTCE_MTU1_TCIU1,\r
+DTCE_MTU2_TGIA2,DTCE_MTU2_TGIB2,DTCE_MTU2_TCIV2,DTCE_MTU2_TCIU2,\r
+DTCE_MTU3_TGIA3,DTCE_MTU3_TGIB3,DTCE_MTU3_TGIC3,DTCE_MTU3_TGID3,DTCE_MTU3_TCIV3,\r
+DTCE_MTU4_TGIA4,DTCE_MTU4_TGIB4,DTCE_MTU4_TGIC4,DTCE_MTU4_TGID4,DTCE_MTU4_TCIV4,\r
+DTCE_MTU5_TGIU5,DTCE_MTU5_TGIV5,DTCE_MTU5_TGIW5,\r
+DTCE_MTU6_TGIA6,DTCE_MTU6_TGIB6,DTCE_MTU6_TGIC6,DTCE_MTU6_TGID6,DTCE_MTU6_TCIV6,DTCE_MTU6_TGIE6,DTCE_MTU6_TGIF6,\r
+DTCE_MTU7_TGIA7,DTCE_MTU7_TGIB7,DTCE_MTU7_TCIV7,DTCE_MTU7_TCIU7,\r
+DTCE_MTU8_TGIA8,DTCE_MTU8_TGIB8,DTCE_MTU8_TCIV8,DTCE_MTU8_TCIU8,\r
+DTCE_MTU9_TGIA9,DTCE_MTU9_TGIB9,DTCE_MTU9_TGIC9,DTCE_MTU9_TGID9,DTCE_MTU9_TCIV9,\r
+DTCE_MTU10_TGIA10,DTCE_MTU10_TGIB10,DTCE_MTU10_TGIC10,DTCE_MTU10_TGID10,DTCE_MTU10_TCIV10,\r
+DTCE_MTU11_TGIU11,DTCE_MTU11_TGIV11,DTCE_MTU11_TGIW11,\r
+DTCE_POE_OEI1,DTCE_POE_OEI2,DTCE_POE_OEI3,DTCE_POE_OEI4,\r
+DTCE_TMR0_CMIA0,DTCE_TMR0_CMIB0,DTCE_TMR0_OVI0,\r
+DTCE_TMR1_CMIA1,DTCE_TMR1_CMIB1,DTCE_TMR1_OVI1,\r
+DTCE_TMR2_CMIA2,DTCE_TMR2_CMIB2,DTCE_TMR2_OVI2,\r
+DTCE_TMR3_CMIA3,DTCE_TMR3_CMIB3,DTCE_TMR3_OVI3,\r
+DTCE_DMACA_DMAC0I=198,DTCE_DMACA_DMAC1I,DTCE_DMACA_DMAC2I,DTCE_DMACA_DMAC3I,\r
+DTCE_EXDMAC_EXDMAC0I,DTCE_EXDMAC_EXDMAC1I,\r
+DTCE_SCI0_ERI0=214,DTCE_SCI0_RXI0,DTCE_SCI0_TXI0,DTCE_SCI0_TEI0,\r
+DTCE_SCI1_ERI1,DTCE_SCI1_RXI1,DTCE_SCI1_TXI1,DTCE_SCI1_TEI1,\r
+DTCE_SCI2_ERI2,DTCE_SCI2_RXI2,DTCE_SCI2_TXI2,DTCE_SCI2_TEI2,\r
+DTCE_SCI3_ERI3,DTCE_SCI3_RXI3,DTCE_SCI3_TXI3,DTCE_SCI3_TEI3,\r
+DTCE_SCI5_ERI5=234,DTCE_SCI5_RXI5,DTCE_SCI5_TXI5,DTCE_SCI5_TEI5,\r
+DTCE_SCI6_ERI6,DTCE_SCI6_RXI6,DTCE_SCI6_TXI6,DTCE_SCI6_TEI6,\r
+DTCE_RIIC0_ICEEI0=246,DTCE_RIIC0_ICRXI0,DTCE_RIIC0_ICTXI0,DTCE_RIIC0_ICTEI0,\r
+DTCE_RIIC1_ICEEI1,DTCE_RIIC1_ICRXI1,DTCE_RIIC1_ICTXI1,DTCE_RIIC1_ICTEI1\r
+};\r
+\r
+enum enum_ier {\r
+IER_BSC_BUSERR=0x02,\r
+IER_FCU_FIFERR=0x02,IER_FCU_FRDYI=0x02,\r
+IER_ICU_SWINT=0x03,\r
+IER_CMT0_CMI0=0x03,\r
+IER_CMT1_CMI1=0x03,\r
+IER_CMT2_CMI2=0x03,\r
+IER_CMT3_CMI3=0x03,\r
+IER_ETHER_EINT=0x04,\r
+IER_USB0_D0FIFO0=0x04,IER_USB0_D1FIFO0=0x04,IER_USB0_USBI0=0x04,\r
+IER_USB1_D0FIFO1=0x05,IER_USB1_D1FIFO1=0x05,IER_USB1_USBI1=0x05,\r
+IER_RSPI0_SPEI0=0x05,IER_RSPI0_SPRI0=0x05,IER_RSPI0_SPTI0=0x05,IER_RSPI0_SPII0=0x05,\r
+IER_RSPI1_SPEI1=0x06,IER_RSPI1_SPRI1=0x06,IER_RSPI1_SPTI1=0x06,IER_RSPI1_SPII1=0x06,\r
+IER_CAN0_ERS0=0x07,IER_CAN0_RXF0=0x07,IER_CAN0_TXF0=0x07,IER_CAN0_RXM0=0x07,IER_CAN0_TXM0=0x07,\r
+IER_RTC_PRD=0x07,IER_RTC_CUP=0x07,\r
+IER_ICU_IRQ0=0x08,IER_ICU_IRQ1=0x08,IER_ICU_IRQ2=0x08,IER_ICU_IRQ3=0x08,IER_ICU_IRQ4=0x08,IER_ICU_IRQ5=0x08,IER_ICU_IRQ6=0x08,IER_ICU_IRQ7=0x08,IER_ICU_IRQ8=0x09,IER_ICU_IRQ9=0x09,IER_ICU_IRQ10=0x09,IER_ICU_IRQ11=0x09,IER_ICU_IRQ12=0x09,IER_ICU_IRQ13=0x09,IER_ICU_IRQ14=0x09,IER_ICU_IRQ15=0x09,\r
+IER_USB_USBR0=0x0B,IER_USB_USBR1=0x0B,\r
+IER_RTC_ALM=0x0B,\r
+IER_WDT_WOVI=0x0C,\r
+IER_AD0_ADI0=0x0C,\r
+IER_AD1_ADI1=0x0C,\r
+IER_S12AD_ADI=0x0C,\r
+IER_MTU0_TGIA0=0x0E,IER_MTU0_TGIB0=0x0E,IER_MTU0_TGIC0=0x0E,IER_MTU0_TGID0=0x0E,IER_MTU0_TCIV0=0x0E,IER_MTU0_TGIE0=0x0E,IER_MTU0_TGIF0=0x0F,\r
+IER_MTU1_TGIA1=0x0F,IER_MTU1_TGIB1=0x0F,IER_MTU1_TCIV1=0x0F,IER_MTU1_TCIU1=0x0F,\r
+IER_MTU2_TGIA2=0x0F,IER_MTU2_TGIB2=0x0F,IER_MTU2_TCIV2=0x0F,IER_MTU2_TCIU2=0x10,\r
+IER_MTU3_TGIA3=0x10,IER_MTU3_TGIB3=0x10,IER_MTU3_TGIC3=0x10,IER_MTU3_TGID3=0x10,IER_MTU3_TCIV3=0x10,\r
+IER_MTU4_TGIA4=0x10,IER_MTU4_TGIB4=0x10,IER_MTU4_TGIC4=0x11,IER_MTU4_TGID4=0x11,IER_MTU4_TCIV4=0x11,\r
+IER_MTU5_TGIU5=0x11,IER_MTU5_TGIV5=0x11,IER_MTU5_TGIW5=0x10,\r
+IER_MTU6_TGIA6=0x11,IER_MTU6_TGIB6=0x11,IER_MTU6_TGIC6=0x12,IER_MTU6_TGID6=0x12,IER_MTU6_TCIV6=0x12,IER_MTU6_TGIE6=0x12,IER_MTU6_TGIF6=0x12,\r
+IER_MTU7_TGIA7=0x12,IER_MTU7_TGIB7=0x12,IER_MTU7_TCIV7=0x12,IER_MTU7_TCIU7=0x13,\r
+IER_MTU8_TGIA8=0x13,IER_MTU8_TGIB8=0x13,IER_MTU8_TCIV8=0x13,IER_MTU8_TCIU8=0x13,\r
+IER_MTU9_TGIA9=0x13,IER_MTU9_TGIB9=0x13,IER_MTU9_TGIC9=0x13,IER_MTU9_TGID9=0x14,IER_MTU9_TCIV9=0x14,\r
+IER_MTU10_TGIA10=0x14,IER_MTU10_TGIB10=0x14,IER_MTU10_TGIC10=0x14,IER_MTU10_TGID10=0x14,IER_MTU10_TCIV10=0x14,\r
+IER_MTU11_TGIU11=0x14,IER_MTU11_TGIV11=0x15,IER_MTU11_TGIW11=0x15,\r
+IER_POE_OEI1=0x15,IER_POE_OEI2=0x15,IER_POE_OEI3=0x15,IER_POE_OEI4=0x15,\r
+IER_TMR0_CMIA0=0x15,IER_TMR0_CMIB0=0x15,IER_TMR0_OVI0=0x16,\r
+IER_TMR1_CMIA1=0x16,IER_TMR1_CMIB1=0x16,IER_TMR1_OVI1=0x16,\r
+IER_TMR2_CMIA2=0x16,IER_TMR2_CMIB2=0x16,IER_TMR2_OVI2=0x16,\r
+IER_TMR3_CMIA3=0x16,IER_TMR3_CMIB3=0x17,IER_TMR3_OVI3=0x17,\r
+IER_DMACA_DMAC0I=0x18,IER_DMACA_DMAC1I=0x18,IER_DMACA_DMAC2I=0x19,IER_DMACA_DMAC3I=0x19,\r
+IER_EXDMAC_EXDMAC0I=0x19,IER_EXDMAC_EXDMAC1I=0x19,\r
+IER_SCI0_ERI0=0x1A,IER_SCI0_RXI0=0x1A,IER_SCI0_TXI0=0x1B,IER_SCI0_TEI0=0x1B,\r
+IER_SCI1_ERI1=0x1B,IER_SCI1_RXI1=0x1B,IER_SCI1_TXI1=0x1B,IER_SCI1_TEI1=0x1B,\r
+IER_SCI2_ERI2=0x1B,IER_SCI2_RXI2=0x1B,IER_SCI2_TXI2=0x1C,IER_SCI2_TEI2=0x1C,\r
+IER_SCI3_ERI3=0x1C,IER_SCI3_RXI3=0x1C,IER_SCI3_TXI3=0x1C,IER_SCI3_TEI3=0x1C,\r
+IER_SCI5_ERI5=0x1D,IER_SCI5_RXI5=0x1D,IER_SCI5_TXI5=0x1D,IER_SCI5_TEI5=0x1D,\r
+IER_SCI6_ERI6=0x1D,IER_SCI6_RXI6=0x1D,IER_SCI6_TXI6=0x1E,IER_SCI6_TEI6=0x1E,\r
+IER_RIIC0_ICEEI0=0x1E,IER_RIIC0_ICRXI0=0x1E,IER_RIIC0_ICTXI0=0x1F,IER_RIIC0_ICTEI0=0x1F,\r
+IER_RIIC1_ICEEI1=0x1F,IER_RIIC1_ICRXI1=0x1F,IER_RIIC1_ICTXI1=0x1F,IER_RIIC1_ICTEI1=0x1F\r
+};\r
+\r
+enum enum_ipr {\r
+IPR_BSC_BUSERR=0x00,\r
+IPR_FCU_FIFERR=0x01,IPR_FCU_FRDYI=0x02,\r
+IPR_ICU_SWINT=0x03,\r
+IPR_CMT0_CMI0=0x04,\r
+IPR_CMT1_CMI1=0x05,\r
+IPR_CMT2_CMI2=0x06,\r
+IPR_CMT3_CMI3=0x07,\r
+IPR_ETHER_EINT=0x08,\r
+IPR_USB0_D0FIFO0=0x0C,IPR_USB0_D1FIFO0=0x0D,IPR_USB0_USBI0=0x0E,\r
+IPR_USB1_D0FIFO1=0x10,IPR_USB1_D1FIFO1=0x11,IPR_USB1_USBI1=0x12,\r
+IPR_RSPI0_SPEI0=0x14,IPR_RSPI0_SPRI0=0x14,IPR_RSPI0_SPTI0=0x14,IPR_RSPI0_SPII0=0x14,\r
+IPR_RSPI1_SPEI1=0x15,IPR_RSPI1_SPRI1=0x15,IPR_RSPI1_SPTI1=0x15,IPR_RSPI1_SPII1=0x15,\r
+IPR_CAN0_ERS0=0x18,IPR_CAN0_RXF0=0x18,IPR_CAN0_TXF0=0x18,IPR_CAN0_RXM0=0x18,IPR_CAN0_TXM0=0x18,\r
+IPR_RTC_PRD=0x1E,IPR_RTC_CUP=0x1F,\r
+IPR_ICU_IRQ0=0x20,IPR_ICU_IRQ1=0x21,IPR_ICU_IRQ2=0x22,IPR_ICU_IRQ3=0x23,IPR_ICU_IRQ4=0x24,IPR_ICU_IRQ5=0x25,IPR_ICU_IRQ6=0x26,IPR_ICU_IRQ7=0x27,IPR_ICU_IRQ8=0x28,IPR_ICU_IRQ9=0x29,IPR_ICU_IRQ10=0x2A,IPR_ICU_IRQ11=0x2B,IPR_ICU_IRQ12=0x2C,IPR_ICU_IRQ13=0x2D,IPR_ICU_IRQ14=0x2E,IPR_ICU_IRQ15=0x2F,\r
+IPR_USB_USBR0=0x3A,IPR_USB_USBR1=0x3B,\r
+IPR_RTC_ALM=0x3C,\r
+IPR_WDT_WOVI=0x40,\r
+IPR_AD0_ADI0=0x44,\r
+IPR_AD1_ADI1=0x45,\r
+IPR_S12AD_ADI=0x48,\r
+IPR_MTU0_TGIA0=0x51,IPR_MTU0_TGIB0=0x51,IPR_MTU0_TGIC0=0x51,IPR_MTU0_TGID0=0x51,IPR_MTU0_TCIV0=0x52,IPR_MTU0_TGIE0=0x52,IPR_MTU0_TGIF0=0x52,\r
+IPR_MTU1_TGIA1=0x53,IPR_MTU1_TGIB1=0x53,IPR_MTU1_TCIV1=0x54,IPR_MTU1_TCIU1=0x54,\r
+IPR_MTU2_TGIA2=0x55,IPR_MTU2_TGIB2=0x55,IPR_MTU2_TCIV2=0x56,IPR_MTU2_TCIU2=0x56,\r
+IPR_MTU3_TGIA3=0x57,IPR_MTU3_TGIB3=0x57,IPR_MTU3_TGIC3=0x57,IPR_MTU3_TGID3=0x57,IPR_MTU3_TCIV3=0x58,\r
+IPR_MTU4_TGIA4=0x59,IPR_MTU4_TGIB4=0x59,IPR_MTU4_TGIC4=0x59,IPR_MTU4_TGID4=0x59,IPR_MTU4_TCIV4=0x5A,\r
+IPR_MTU5_TGIU5=0x5B,IPR_MTU5_TGIV5=0x5B,IPR_MTU5_TGIW5=0x5B,\r
+IPR_MTU6_TGIA6=0x5C,IPR_MTU6_TGIB6=0x5C,IPR_MTU6_TGIC6=0x5C,IPR_MTU6_TGID6=0x5C,IPR_MTU6_TCIV6=0x5D,IPR_MTU6_TGIE6=0x5D,IPR_MTU6_TGIF6=0x5D,\r
+IPR_MTU7_TGIA7=0x5E,IPR_MTU7_TGIB7=0x5E,IPR_MTU7_TCIV7=0x5F,IPR_MTU7_TCIU7=0x5F,\r
+IPR_MTU8_TGIA8=0x60,IPR_MTU8_TGIB8=0x60,IPR_MTU8_TCIV8=0x61,IPR_MTU8_TCIU8=0x61,\r
+IPR_MTU9_TGIA9=0x62,IPR_MTU9_TGIB9=0x62,IPR_MTU9_TGIC9=0x62,IPR_MTU9_TGID9=0x62,IPR_MTU9_TCIV9=0x63,\r
+IPR_MTU10_TGIA10=0x64,IPR_MTU10_TGIB10=0x64,IPR_MTU10_TGIC10=0x64,IPR_MTU10_TGID10=0x64,IPR_MTU10_TCIV10=0x65,\r
+IPR_MTU11_TGIU11=0x66,IPR_MTU11_TGIV11=0x66,IPR_MTU11_TGIW11=0x66,\r
+IPR_POE_OEI1=0x67,IPR_POE_OEI2=0x67,IPR_POE_OEI3=0x67,IPR_POE_OEI4=0x67,\r
+IPR_TMR0_CMIA0=0x68,IPR_TMR0_CMIB0=0x68,IPR_TMR0_OVI0=0x68,\r
+IPR_TMR1_CMIA1=0x69,IPR_TMR1_CMIB1=0x69,IPR_TMR1_OVI1=0x69,\r
+IPR_TMR2_CMIA2=0x6A,IPR_TMR2_CMIB2=0x6A,IPR_TMR2_OVI2=0x6A,\r
+IPR_TMR3_CMIA3=0x6B,IPR_TMR3_CMIB3=0x6B,IPR_TMR3_OVI3=0x6B,\r
+IPR_DMACA_DMAC0I=0x70,IPR_DMACA_DMAC1I=0x71,IPR_DMACA_DMAC2I=0x72,IPR_DMACA_DMAC3I=0x73,\r
+IPR_EXDMAC_EXDMAC0I=0x74,IPR_EXDMAC_EXDMAC1I=0x75,\r
+IPR_SCI0_ERI0=0x80,IPR_SCI0_RXI0=0x80,IPR_SCI0_TXI0=0x80,IPR_SCI0_TEI0=0x80,\r
+IPR_SCI1_ERI1=0x81,IPR_SCI1_RXI1=0x81,IPR_SCI1_TXI1=0x81,IPR_SCI1_TEI1=0x81,\r
+IPR_SCI2_ERI2=0x82,IPR_SCI2_RXI2=0x82,IPR_SCI2_TXI2=0x82,IPR_SCI2_TEI2=0x82,\r
+IPR_SCI3_ERI3=0x83,IPR_SCI3_RXI3=0x83,IPR_SCI3_TXI3=0x83,IPR_SCI3_TEI3=0x83,\r
+IPR_SCI5_ERI5=0x85,IPR_SCI5_RXI5=0x85,IPR_SCI5_TXI5=0x85,IPR_SCI5_TEI5=0x85,\r
+IPR_SCI6_ERI6=0x86,IPR_SCI6_RXI6=0x86,IPR_SCI6_TXI6=0x86,IPR_SCI6_TEI6=0x86,\r
+IPR_RIIC0_ICEEI0=0x88,IPR_RIIC0_ICRXI0=0x89,IPR_RIIC0_ICTXI0=0x8A,IPR_RIIC0_ICTEI0=0x8B,\r
+IPR_RIIC1_ICEEI1=0x8C,IPR_RIIC1_ICRXI1=0x8D,IPR_RIIC1_ICTXI1=0x8E,IPR_RIIC1_ICTEI1=0x8F,\r
+IPR_BSC_=0x00,\r
+IPR_CMT0_=0x04,\r
+IPR_CMT1_=0x05,\r
+IPR_CMT2_=0x06,\r
+IPR_CMT3_=0x07,\r
+IPR_ETHER_=0x08,\r
+IPR_RSPI0_=0x14,\r
+IPR_RSPI1_=0x15,\r
+IPR_CAN0_=0x18,\r
+IPR_WDT_=0x40,\r
+IPR_AD0_=0x44,\r
+IPR_AD1_=0x45,\r
+IPR_S12AD_=0x48,\r
+IPR_MTU1_TGI=0x53,\r
+IPR_MTU1_TCI=0x54,\r
+IPR_MTU2_TGI=0x55,\r
+IPR_MTU2_TCI=0x56,\r
+IPR_MTU3_TGI=0x57,\r
+IPR_MTU4_TGI=0x59,\r
+IPR_MTU5_=0x5B,\r
+IPR_MTU5_TGI=0x5B,\r
+IPR_MTU7_TGI=0x5E,\r
+IPR_MTU7_TCI=0x5F,\r
+IPR_MTU8_TGI=0x60,\r
+IPR_MTU8_TCI=0x61,\r
+IPR_MTU9_TGI=0x62,\r
+IPR_MTU10_TGI=0x64,\r
+IPR_MTU11_=0x66,\r
+IPR_MTU11_TGI=0x66,\r
+IPR_POE_=0x67,\r
+IPR_POE_OEI=0x67,\r
+IPR_TMR0_=0x68,\r
+IPR_TMR1_=0x69,\r
+IPR_TMR2_=0x6A,\r
+IPR_TMR3_=0x6B,\r
+IPR_SCI0_=0x80,\r
+IPR_SCI1_=0x81,\r
+IPR_SCI2_=0x82,\r
+IPR_SCI3_=0x83,\r
+IPR_SCI5_=0x85,\r
+IPR_SCI6_=0x86\r
+};\r
+\r
+#define IEN_BSC_BUSERR IEN0\r
+#define IEN_FCU_FIFERR IEN5\r
+#define IEN_FCU_FRDYI IEN7\r
+#define IEN_ICU_SWINT IEN3\r
+#define IEN_CMT0_CMI0 IEN4\r
+#define IEN_CMT1_CMI1 IEN5\r
+#define IEN_CMT2_CMI2 IEN6\r
+#define IEN_CMT3_CMI3 IEN7\r
+#define IEN_ETHER_EINT IEN0\r
+#define IEN_USB0_D0FIFO0 IEN4\r
+#define IEN_USB0_D1FIFO0 IEN5\r
+#define IEN_USB0_USBI0 IEN6\r
+#define IEN_USB1_D0FIFO1 IEN0\r
+#define IEN_USB1_D1FIFO1 IEN1\r
+#define IEN_USB1_USBI1 IEN2\r
+#define IEN_RSPI0_SPEI0 IEN4\r
+#define IEN_RSPI0_SPRI0 IEN5\r
+#define IEN_RSPI0_SPTI0 IEN6\r
+#define IEN_RSPI0_SPII0 IEN7\r
+#define IEN_RSPI1_SPEI1 IEN0\r
+#define IEN_RSPI1_SPRI1 IEN1\r
+#define IEN_RSPI1_SPTI1 IEN2\r
+#define IEN_RSPI1_SPII1 IEN3\r
+#define IEN_CAN0_ERS0 IEN0\r
+#define IEN_CAN0_RXF0 IEN1\r
+#define IEN_CAN0_TXF0 IEN2\r
+#define IEN_CAN0_RXM0 IEN3\r
+#define IEN_CAN0_TXM0 IEN4\r
+#define IEN_RTC_PRD IEN6\r
+#define IEN_RTC_CUP IEN7\r
+#define IEN_ICU_IRQ0 IEN0\r
+#define IEN_ICU_IRQ1 IEN1\r
+#define IEN_ICU_IRQ2 IEN2\r
+#define IEN_ICU_IRQ3 IEN3\r
+#define IEN_ICU_IRQ4 IEN4\r
+#define IEN_ICU_IRQ5 IEN5\r
+#define IEN_ICU_IRQ6 IEN6\r
+#define IEN_ICU_IRQ7 IEN7\r
+#define IEN_ICU_IRQ8 IEN0\r
+#define IEN_ICU_IRQ9 IEN1\r
+#define IEN_ICU_IRQ10 IEN2\r
+#define IEN_ICU_IRQ11 IEN3\r
+#define IEN_ICU_IRQ12 IEN4\r
+#define IEN_ICU_IRQ13 IEN5\r
+#define IEN_ICU_IRQ14 IEN6\r
+#define IEN_ICU_IRQ15 IEN7\r
+#define IEN_USB_USBR0 IEN2\r
+#define IEN_USB_USBR1 IEN3\r
+#define IEN_RTC_ALM IEN4\r
+#define IEN_WDT_WOVI IEN0\r
+#define IEN_AD0_ADI0 IEN2\r
+#define IEN_AD1_ADI1 IEN3\r
+#define IEN_S12AD_ADI IEN6\r
+#define IEN_MTU0_TGIA0 IEN2\r
+#define IEN_MTU0_TGIB0 IEN3\r
+#define IEN_MTU0_TGIC0 IEN4\r
+#define IEN_MTU0_TGID0 IEN5\r
+#define IEN_MTU0_TCIV0 IEN6\r
+#define IEN_MTU0_TGIE0 IEN7\r
+#define IEN_MTU0_TGIF0 IEN0\r
+#define IEN_MTU1_TGIA1 IEN1\r
+#define IEN_MTU1_TGIB1 IEN2\r
+#define IEN_MTU1_TCIV1 IEN3\r
+#define IEN_MTU1_TCIU1 IEN4\r
+#define IEN_MTU2_TGIA2 IEN5\r
+#define IEN_MTU2_TGIB2 IEN6\r
+#define IEN_MTU2_TCIV2 IEN7\r
+#define IEN_MTU2_TCIU2 IEN0\r
+#define IEN_MTU3_TGIA3 IEN1\r
+#define IEN_MTU3_TGIB3 IEN2\r
+#define IEN_MTU3_TGIC3 IEN3\r
+#define IEN_MTU3_TGID3 IEN4\r
+#define IEN_MTU3_TCIV3 IEN5\r
+#define IEN_MTU4_TGIA4 IEN6\r
+#define IEN_MTU4_TGIB4 IEN7\r
+#define IEN_MTU4_TGIC4 IEN0\r
+#define IEN_MTU4_TGID4 IEN1\r
+#define IEN_MTU4_TCIV4 IEN2\r
+#define IEN_MTU5_TGIU5 IEN3\r
+#define IEN_MTU5_TGIV5 IEN4\r
+#define IEN_MTU5_TGIW5 IEN7\r
+#define IEN_MTU6_TGIA6 IEN6\r
+#define IEN_MTU6_TGIB6 IEN7\r
+#define IEN_MTU6_TGIC6 IEN0\r
+#define IEN_MTU6_TGID6 IEN1\r
+#define IEN_MTU6_TCIV6 IEN2\r
+#define IEN_MTU6_TGIE6 IEN3\r
+#define IEN_MTU6_TGIF6 IEN4\r
+#define IEN_MTU7_TGIA7 IEN5\r
+#define IEN_MTU7_TGIB7 IEN6\r
+#define IEN_MTU7_TCIV7 IEN7\r
+#define IEN_MTU7_TCIU7 IEN0\r
+#define IEN_MTU8_TGIA8 IEN1\r
+#define IEN_MTU8_TGIB8 IEN2\r
+#define IEN_MTU8_TCIV8 IEN3\r
+#define IEN_MTU8_TCIU8 IEN4\r
+#define IEN_MTU9_TGIA9 IEN5\r
+#define IEN_MTU9_TGIB9 IEN6\r
+#define IEN_MTU9_TGIC9 IEN7\r
+#define IEN_MTU9_TGID9 IEN0\r
+#define IEN_MTU9_TCIV9 IEN1\r
+#define IEN_MTU10_TGIA10 IEN2\r
+#define IEN_MTU10_TGIB10 IEN3\r
+#define IEN_MTU10_TGIC10 IEN4\r
+#define IEN_MTU10_TGID10 IEN5\r
+#define IEN_MTU10_TCIV10 IEN6\r
+#define IEN_MTU11_TGIU11 IEN7\r
+#define IEN_MTU11_TGIV11 IEN0\r
+#define IEN_MTU11_TGIW11 IEN1\r
+#define IEN_POE_OEI1 IEN2\r
+#define IEN_POE_OEI2 IEN3\r
+#define IEN_POE_OEI3 IEN4\r
+#define IEN_POE_OEI4 IEN5\r
+#define IEN_TMR0_CMIA0 IEN6\r
+#define IEN_TMR0_CMIB0 IEN7\r
+#define IEN_TMR0_OVI0 IEN0\r
+#define IEN_TMR1_CMIA1 IEN1\r
+#define IEN_TMR1_CMIB1 IEN2\r
+#define IEN_TMR1_OVI1 IEN3\r
+#define IEN_TMR2_CMIA2 IEN4\r
+#define IEN_TMR2_CMIB2 IEN5\r
+#define IEN_TMR2_OVI2 IEN6\r
+#define IEN_TMR3_CMIA3 IEN7\r
+#define IEN_TMR3_CMIB3 IEN0\r
+#define IEN_TMR3_OVI3 IEN1\r
+#define IEN_DMACA_DMAC0I IEN6\r
+#define IEN_DMACA_DMAC1I IEN7\r
+#define IEN_DMACA_DMAC2I IEN0\r
+#define IEN_DMACA_DMAC3I IEN1\r
+#define IEN_EXDMAC_EXDMAC0I IEN2\r
+#define IEN_EXDMAC_EXDMAC1I IEN3\r
+#define IEN_SCI0_ERI0 IEN6\r
+#define IEN_SCI0_RXI0 IEN7\r
+#define IEN_SCI0_TXI0 IEN0\r
+#define IEN_SCI0_TEI0 IEN1\r
+#define IEN_SCI1_ERI1 IEN2\r
+#define IEN_SCI1_RXI1 IEN3\r
+#define IEN_SCI1_TXI1 IEN4\r
+#define IEN_SCI1_TEI1 IEN5\r
+#define IEN_SCI2_ERI2 IEN6\r
+#define IEN_SCI2_RXI2 IEN7\r
+#define IEN_SCI2_TXI2 IEN0\r
+#define IEN_SCI2_TEI2 IEN1\r
+#define IEN_SCI3_ERI3 IEN2\r
+#define IEN_SCI3_RXI3 IEN3\r
+#define IEN_SCI3_TXI3 IEN4\r
+#define IEN_SCI3_TEI3 IEN5\r
+#define IEN_SCI5_ERI5 IEN2\r
+#define IEN_SCI5_RXI5 IEN3\r
+#define IEN_SCI5_TXI5 IEN4\r
+#define IEN_SCI5_TEI5 IEN5\r
+#define IEN_SCI6_ERI6 IEN6\r
+#define IEN_SCI6_RXI6 IEN7\r
+#define IEN_SCI6_TXI6 IEN0\r
+#define IEN_SCI6_TEI6 IEN1\r
+#define IEN_RIIC0_ICEEI0 IEN6\r
+#define IEN_RIIC0_ICRXI0 IEN7\r
+#define IEN_RIIC0_ICTXI0 IEN0\r
+#define IEN_RIIC0_ICTEI0 IEN1\r
+#define IEN_RIIC1_ICEEI1 IEN2\r
+#define IEN_RIIC1_ICRXI1 IEN3\r
+#define IEN_RIIC1_ICTXI1 IEN4\r
+#define IEN_RIIC1_ICTEI1 IEN5\r
+\r
+#define VECT_BSC_BUSERR 16\r
+#define VECT_FCU_FIFERR 21\r
+#define VECT_FCU_FRDYI 23\r
+#define VECT_ICU_SWINT 27\r
+#define VECT_CMT0_CMI0 28\r
+#define VECT_CMT1_CMI1 29\r
+#define VECT_CMT2_CMI2 30\r
+#define VECT_CMT3_CMI3 31\r
+#define VECT_ETHER_EINT 32\r
+#define VECT_USB0_D0FIFO0 36\r
+#define VECT_USB0_D1FIFO0 37\r
+#define VECT_USB0_USBI0 38\r
+#define VECT_USB1_D0FIFO1 40\r
+#define VECT_USB1_D1FIFO1 41\r
+#define VECT_USB1_USBI1 42\r
+#define VECT_RSPI0_SPEI0 44\r
+#define VECT_RSPI0_SPRI0 45\r
+#define VECT_RSPI0_SPTI0 46\r
+#define VECT_RSPI0_SPII0 47\r
+#define VECT_RSPI1_SPEI1 48\r
+#define VECT_RSPI1_SPRI1 49\r
+#define VECT_RSPI1_SPTI1 50\r
+#define VECT_RSPI1_SPII1 51\r
+#define VECT_CAN0_ERS0 56\r
+#define VECT_CAN0_RXF0 57\r
+#define VECT_CAN0_TXF0 58\r
+#define VECT_CAN0_RXM0 59\r
+#define VECT_CAN0_TXM0 60\r
+#define VECT_RTC_PRD 62\r
+#define VECT_RTC_CUP 63\r
+#define VECT_ICU_IRQ0 64\r
+#define VECT_ICU_IRQ1 65\r
+#define VECT_ICU_IRQ2 66\r
+#define VECT_ICU_IRQ3 67\r
+#define VECT_ICU_IRQ4 68\r
+#define VECT_ICU_IRQ5 69\r
+#define VECT_ICU_IRQ6 70\r
+#define VECT_ICU_IRQ7 71\r
+#define VECT_ICU_IRQ8 72\r
+#define VECT_ICU_IRQ9 73\r
+#define VECT_ICU_IRQ10 74\r
+#define VECT_ICU_IRQ11 75\r
+#define VECT_ICU_IRQ12 76\r
+#define VECT_ICU_IRQ13 77\r
+#define VECT_ICU_IRQ14 78\r
+#define VECT_ICU_IRQ15 79\r
+#define VECT_USB_USBR0 90\r
+#define VECT_USB_USBR1 91\r
+#define VECT_RTC_ALM 92\r
+#define VECT_WDT_WOVI 96\r
+#define VECT_AD0_ADI0 98\r
+#define VECT_AD1_ADI1 99\r
+#define VECT_S12AD_ADI 102\r
+#define VECT_MTU0_TGIA0 114\r
+#define VECT_MTU0_TGIB0 115\r
+#define VECT_MTU0_TGIC0 116\r
+#define VECT_MTU0_TGID0 117\r
+#define VECT_MTU0_TCIV0 118\r
+#define VECT_MTU0_TGIE0 119\r
+#define VECT_MTU0_TGIF0 120\r
+#define VECT_MTU1_TGIA1 121\r
+#define VECT_MTU1_TGIB1 122\r
+#define VECT_MTU1_TCIV1 123\r
+#define VECT_MTU1_TCIU1 124\r
+#define VECT_MTU2_TGIA2 125\r
+#define VECT_MTU2_TGIB2 126\r
+#define VECT_MTU2_TCIV2 127\r
+#define VECT_MTU2_TCIU2 128\r
+#define VECT_MTU3_TGIA3 129\r
+#define VECT_MTU3_TGIB3 130\r
+#define VECT_MTU3_TGIC3 131\r
+#define VECT_MTU3_TGID3 132\r
+#define VECT_MTU3_TCIV3 133\r
+#define VECT_MTU4_TGIA4 134\r
+#define VECT_MTU4_TGIB4 135\r
+#define VECT_MTU4_TGIC4 136\r
+#define VECT_MTU4_TGID4 137\r
+#define VECT_MTU4_TCIV4 138\r
+#define VECT_MTU5_TGIU5 139\r
+#define VECT_MTU5_TGIV5 140\r
+#define VECT_MTU5_TGIW5 141\r
+#define VECT_MTU6_TGIA6 142\r
+#define VECT_MTU6_TGIB6 143\r
+#define VECT_MTU6_TGIC6 144\r
+#define VECT_MTU6_TGID6 145\r
+#define VECT_MTU6_TCIV6 146\r
+#define VECT_MTU6_TGIE6 147\r
+#define VECT_MTU6_TGIF6 148\r
+#define VECT_MTU7_TGIA7 149\r
+#define VECT_MTU7_TGIB7 150\r
+#define VECT_MTU7_TCIV7 151\r
+#define VECT_MTU7_TCIU7 152\r
+#define VECT_MTU8_TGIA8 153\r
+#define VECT_MTU8_TGIB8 154\r
+#define VECT_MTU8_TCIV8 155\r
+#define VECT_MTU8_TCIU8 156\r
+#define VECT_MTU9_TGIA9 157\r
+#define VECT_MTU9_TGIB9 158\r
+#define VECT_MTU9_TGIC9 159\r
+#define VECT_MTU9_TGID9 160\r
+#define VECT_MTU9_TCIV9 161\r
+#define VECT_MTU10_TGIA10 162\r
+#define VECT_MTU10_TGIB10 163\r
+#define VECT_MTU10_TGIC10 164\r
+#define VECT_MTU10_TGID10 165\r
+#define VECT_MTU10_TCIV10 166\r
+#define VECT_MTU11_TGIU11 167\r
+#define VECT_MTU11_TGIV11 168\r
+#define VECT_MTU11_TGIW11 169\r
+#define VECT_POE_OEI1 170\r
+#define VECT_POE_OEI2 171\r
+#define VECT_POE_OEI3 172\r
+#define VECT_POE_OEI4 173\r
+#define VECT_TMR0_CMIA0 174\r
+#define VECT_TMR0_CMIB0 175\r
+#define VECT_TMR0_OVI0 176\r
+#define VECT_TMR1_CMIA1 177\r
+#define VECT_TMR1_CMIB1 178\r
+#define VECT_TMR1_OVI1 179\r
+#define VECT_TMR2_CMIA2 180\r
+#define VECT_TMR2_CMIB2 181\r
+#define VECT_TMR2_OVI2 182\r
+#define VECT_TMR3_CMIA3 183\r
+#define VECT_TMR3_CMIB3 184\r
+#define VECT_TMR3_OVI3 185\r
+#define VECT_DMACA_DMAC0I 198\r
+#define VECT_DMACA_DMAC1I 199\r
+#define VECT_DMACA_DMAC2I 200\r
+#define VECT_DMACA_DMAC3I 201\r
+#define VECT_EXDMAC_EXDMAC0I 202\r
+#define VECT_EXDMAC_EXDMAC1I 203\r
+#define VECT_SCI0_ERI0 214\r
+#define VECT_SCI0_RXI0 215\r
+#define VECT_SCI0_TXI0 216\r
+#define VECT_SCI0_TEI0 217\r
+#define VECT_SCI1_ERI1 218\r
+#define VECT_SCI1_RXI1 219\r
+#define VECT_SCI1_TXI1 220\r
+#define VECT_SCI1_TEI1 221\r
+#define VECT_SCI2_ERI2 222\r
+#define VECT_SCI2_RXI2 223\r
+#define VECT_SCI2_TXI2 224\r
+#define VECT_SCI2_TEI2 225\r
+#define VECT_SCI3_ERI3 226\r
+#define VECT_SCI3_RXI3 227\r
+#define VECT_SCI3_TXI3 228\r
+#define VECT_SCI3_TEI3 229\r
+#define VECT_SCI5_ERI5 234\r
+#define VECT_SCI5_RXI5 235\r
+#define VECT_SCI5_TXI5 236\r
+#define VECT_SCI5_TEI5 237\r
+#define VECT_SCI6_ERI6 238\r
+#define VECT_SCI6_RXI6 239\r
+#define VECT_SCI6_TXI6 240\r
+#define VECT_SCI6_TEI6 241\r
+#define VECT_RIIC0_ICEEI0 246\r
+#define VECT_RIIC0_ICRXI0 247\r
+#define VECT_RIIC0_ICTXI0 248\r
+#define VECT_RIIC0_ICTEI0 249\r
+#define VECT_RIIC1_ICEEI1 250\r
+#define VECT_RIIC1_ICRXI1 251\r
+#define VECT_RIIC1_ICTXI1 252\r
+#define VECT_RIIC1_ICTEI1 253\r
+\r
+#define MSTP_EXDMAC SYSTEM.MSTPCRA.BIT.MSTPA29\r
+#define MSTP_DMACA SYSTEM.MSTPCRA.BIT.MSTPA28\r
+#define MSTP_DTC SYSTEM.MSTPCRA.BIT.MSTPA28\r
+#define MSTP_AD0 SYSTEM.MSTPCRA.BIT.MSTPA23\r
+#define MSTP_AD1 SYSTEM.MSTPCRA.BIT.MSTPA22\r
+#define MSTP_DA SYSTEM.MSTPCRA.BIT.MSTPA19\r
+#define MSTP_S12AD SYSTEM.MSTPCRA.BIT.MSTPA17\r
+#define MSTP_CMT0 SYSTEM.MSTPCRA.BIT.MSTPA15\r
+#define MSTP_CMT1 SYSTEM.MSTPCRA.BIT.MSTPA15\r
+#define MSTP_CMT2 SYSTEM.MSTPCRA.BIT.MSTPA14\r
+#define MSTP_CMT3 SYSTEM.MSTPCRA.BIT.MSTPA14\r
+#define MSTP_PPG0 SYSTEM.MSTPCRA.BIT.MSTPA11\r
+#define MSTP_PPG1 SYSTEM.MSTPCRA.BIT.MSTPA10\r
+#define MSTP_MTUA SYSTEM.MSTPCRA.BIT.MSTPA9\r
+#define MSTP_MTU0 SYSTEM.MSTPCRA.BIT.MSTPA9\r
+#define MSTP_MTU1 SYSTEM.MSTPCRA.BIT.MSTPA9\r
+#define MSTP_MTU2 SYSTEM.MSTPCRA.BIT.MSTPA9\r
+#define MSTP_MTU3 SYSTEM.MSTPCRA.BIT.MSTPA9\r
+#define MSTP_MTU4 SYSTEM.MSTPCRA.BIT.MSTPA9\r
+#define MSTP_MTU5 SYSTEM.MSTPCRA.BIT.MSTPA9\r
+#define MSTP_MTUB SYSTEM.MSTPCRA.BIT.MSTPA8\r
+#define MSTP_MTU6 SYSTEM.MSTPCRA.BIT.MSTPA8\r
+#define MSTP_MTU7 SYSTEM.MSTPCRA.BIT.MSTPA8\r
+#define MSTP_MTU8 SYSTEM.MSTPCRA.BIT.MSTPA8\r
+#define MSTP_MTU9 SYSTEM.MSTPCRA.BIT.MSTPA8\r
+#define MSTP_MTU10 SYSTEM.MSTPCRA.BIT.MSTPA8\r
+#define MSTP_MTU11 SYSTEM.MSTPCRA.BIT.MSTPA8\r
+#define MSTP_TMR0 SYSTEM.MSTPCRA.BIT.MSTPA5\r
+#define MSTP_TMR1 SYSTEM.MSTPCRA.BIT.MSTPA5\r
+#define MSTP_TMR01 SYSTEM.MSTPCRA.BIT.MSTPA5\r
+#define MSTP_TMR2 SYSTEM.MSTPCRA.BIT.MSTPA4\r
+#define MSTP_TMR3 SYSTEM.MSTPCRA.BIT.MSTPA4\r
+#define MSTP_TMR23 SYSTEM.MSTPCRA.BIT.MSTPA4\r
+#define MSTP_SCI0 SYSTEM.MSTPCRB.BIT.MSTPB31\r
+#define MSTP_SMCI0 SYSTEM.MSTPCRB.BIT.MSTPB31\r
+#define MSTP_SCI1 SYSTEM.MSTPCRB.BIT.MSTPB30\r
+#define MSTP_SMCI1 SYSTEM.MSTPCRB.BIT.MSTPB30\r
+#define MSTP_SCI2 SYSTEM.MSTPCRB.BIT.MSTPB29\r
+#define MSTP_SMCI2 SYSTEM.MSTPCRB.BIT.MSTPB29\r
+#define MSTP_SCI3 SYSTEM.MSTPCRB.BIT.MSTPB28\r
+#define MSTP_SMCI3 SYSTEM.MSTPCRB.BIT.MSTPB28\r
+#define MSTP_SCI5 SYSTEM.MSTPCRB.BIT.MSTPB26\r
+#define MSTP_SMCI5 SYSTEM.MSTPCRB.BIT.MSTPB26\r
+#define MSTP_SCI6 SYSTEM.MSTPCRB.BIT.MSTPB25\r
+#define MSTP_SMCI6 SYSTEM.MSTPCRB.BIT.MSTPB25\r
+#define MSTP_CRC SYSTEM.MSTPCRB.BIT.MSTPB23\r
+#define MSTP_RIIC0 SYSTEM.MSTPCRB.BIT.MSTPB21\r
+#define MSTP_RIIC1 SYSTEM.MSTPCRB.BIT.MSTPB20\r
+#define MSTP_USB0 SYSTEM.MSTPCRB.BIT.MSTPB19\r
+#define MSTP_USB1 SYSTEM.MSTPCRB.BIT.MSTPB18\r
+#define MSTP_RSPI0 SYSTEM.MSTPCRB.BIT.MSTPB17\r
+#define MSTP_RSPI1 SYSTEM.MSTPCRB.BIT.MSTPB16\r
+#define MSTP_EDMAC SYSTEM.MSTPCRB.BIT.MSTPB15\r
+#define MSTP_CAN0 SYSTEM.MSTPCRB.BIT.MSTPB0\r
+#define MSTP_RAM0 SYSTEM.MSTPCRC.BIT.MSTPC1\r
+#define MSTP_RAM1 SYSTEM.MSTPCRC.BIT.MSTPC0\r
+\r
+#define __IR( x ) ICU.IR[ IR ## x ].BIT.IR\r
+#define _IR( x ) __IR( x )\r
+#define IR( x , y ) _IR( _ ## x ## _ ## y )\r
+#define __DTCE( x ) ICU.DTCER[ DTCE ## x ].BIT.DTCE\r
+#define _DTCE( x ) __DTCE( x )\r
+#define DTCE( x , y ) _DTCE( _ ## x ## _ ## y )\r
+#define __IEN( x ) ICU.IER[ IER ## x ].BIT.IEN ## x\r
+#define _IEN( x ) __IEN( x )\r
+#define IEN( x , y ) _IEN( _ ## x ## _ ## y )\r
+#define __IPR( x ) ICU.IPR[ IPR ## x ].BIT.IPR\r
+#define _IPR( x ) __IPR( x )\r
+#define IPR( x , y ) _IPR( _ ## x ## _ ## y )\r
+#define __VECT( x ) VECT ## x\r
+#define _VECT( x ) __VECT( x )\r
+#define VECT( x , y ) _VECT( _ ## x ## _ ## y )\r
+#define __MSTP( x ) MSTP ## x\r
+#define _MSTP( x ) __MSTP( x )\r
+#define MSTP( x ) _MSTP( _ ## x )\r
+\r
+#define SYSTEM (*(volatile struct st_system __evenaccess *)0x80000)\r
+#define BSC (*(volatile struct st_bsc __evenaccess *)0x81300)\r
+#define DMAC0 (*(volatile struct st_dmac0 __evenaccess *)0x82000)\r
+#define DMAC1 (*(volatile struct st_dmac1 __evenaccess *)0x82040)\r
+#define DMAC2 (*(volatile struct st_dmac1 __evenaccess *)0x82080)\r
+#define DMAC3 (*(volatile struct st_dmac1 __evenaccess *)0x820C0)\r
+#define DMAC (*(volatile struct st_dmac __evenaccess *)0x82200)\r
+#define DTC (*(volatile struct st_dtc __evenaccess *)0x82400)\r
+#define EXDMAC0 (*(volatile struct st_exdmac0 __evenaccess *)0x82800)\r
+#define EXDMAC1 (*(volatile struct st_exdmac0 __evenaccess *)0x82840)\r
+#define EXDMAC (*(volatile struct st_exdmac __evenaccess *)0x82A00)\r
+#define ICU (*(volatile struct st_icu __evenaccess *)0x87000)\r
+#define CMT (*(volatile struct st_cmt __evenaccess *)0x88000)\r
+#define CMT0 (*(volatile struct st_cmt0 __evenaccess *)0x88002)\r
+#define CMT1 (*(volatile struct st_cmt0 __evenaccess *)0x88008)\r
+#define CMT2 (*(volatile struct st_cmt0 __evenaccess *)0x88012)\r
+#define CMT3 (*(volatile struct st_cmt0 __evenaccess *)0x88018)\r
+#define WDT (*(volatile union un_wdt __evenaccess *)0x88028)\r
+#define IWDT (*(volatile struct st_iwdt __evenaccess *)0x88030)\r
+#define AD0 (*(volatile struct st_ad __evenaccess *)0x88040)\r
+#define AD1 (*(volatile struct st_ad __evenaccess *)0x88060)\r
+#define DA (*(volatile struct st_da __evenaccess *)0x880C0)\r
+#define PPG0 (*(volatile struct st_ppg0 __evenaccess *)0x881E6)\r
+#define PPG1 (*(volatile struct st_ppg1 __evenaccess *)0x881F0)\r
+#define TMR0 (*(volatile struct st_tmr0 __evenaccess *)0x88200)\r
+#define TMR1 (*(volatile struct st_tmr1 __evenaccess *)0x88201)\r
+#define TMR01 (*(volatile struct st_tmr01 __evenaccess *)0x88204)\r
+#define TMR2 (*(volatile struct st_tmr0 __evenaccess *)0x88210)\r
+#define TMR3 (*(volatile struct st_tmr1 __evenaccess *)0x88211)\r
+#define TMR23 (*(volatile struct st_tmr01 __evenaccess *)0x88214)\r
+#define SCI0 (*(volatile struct st_sci __evenaccess *)0x88240)\r
+#define SCI1 (*(volatile struct st_sci __evenaccess *)0x88248)\r
+#define SCI2 (*(volatile struct st_sci __evenaccess *)0x88250)\r
+#define SCI3 (*(volatile struct st_sci __evenaccess *)0x88258)\r
+#define SCI5 (*(volatile struct st_sci __evenaccess *)0x88268)\r
+#define SCI6 (*(volatile struct st_sci __evenaccess *)0x88270)\r
+#define SMCI0 (*(volatile struct st_smci __evenaccess *)0x88240)\r
+#define SMCI1 (*(volatile struct st_smci __evenaccess *)0x88248)\r
+#define SMCI2 (*(volatile struct st_smci __evenaccess *)0x88250)\r
+#define SMCI3 (*(volatile struct st_smci __evenaccess *)0x88258)\r
+#define SMCI5 (*(volatile struct st_smci __evenaccess *)0x88268)\r
+#define SMCI6 (*(volatile struct st_smci __evenaccess *)0x88270)\r
+#define CRC (*(volatile struct st_crc __evenaccess *)0x88280)\r
+#define RIIC0 (*(volatile struct st_riic __evenaccess *)0x88300)\r
+#define RIIC1 (*(volatile struct st_riic __evenaccess *)0x88320)\r
+#define RSPI0 (*(volatile struct st_rspi __evenaccess *)0x88380)\r
+#define RSPI1 (*(volatile struct st_rspi __evenaccess *)0x883A0)\r
+#define MTUA (*(volatile struct st_mtu __evenaccess *)0x8860A)\r
+#define MTU0 (*(volatile struct st_mtu0 __evenaccess *)0x88700)\r
+#define MTU1 (*(volatile struct st_mtu1 __evenaccess *)0x88780)\r
+#define MTU2 (*(volatile struct st_mtu2 __evenaccess *)0x88800)\r
+#define MTU3 (*(volatile struct st_mtu3 __evenaccess *)0x88600)\r
+#define MTU4 (*(volatile struct st_mtu4 __evenaccess *)0x88600)\r
+#define MTU5 (*(volatile struct st_mtu5 __evenaccess *)0x88880)\r
+#define POE (*(volatile struct st_poe __evenaccess *)0x88900)\r
+#define MTUB (*(volatile struct st_mtu __evenaccess *)0x88A0A)\r
+#define MTU6 (*(volatile struct st_mtu0 __evenaccess *)0x88B00)\r
+#define MTU7 (*(volatile struct st_mtu1 __evenaccess *)0x88B80)\r
+#define MTU8 (*(volatile struct st_mtu2 __evenaccess *)0x88C00)\r
+#define MTU9 (*(volatile struct st_mtu3 __evenaccess *)0x88A00)\r
+#define MTU10 (*(volatile struct st_mtu4 __evenaccess *)0x88A00)\r
+#define MTU11 (*(volatile struct st_mtu5 __evenaccess *)0x88C80)\r
+#define S12AD (*(volatile struct st_s12ad __evenaccess *)0x89000)\r
+#define PORT0 (*(volatile struct st_port0 __evenaccess *)0x8C000)\r
+#define PORT1 (*(volatile struct st_port1 __evenaccess *)0x8C001)\r
+#define PORT2 (*(volatile struct st_port2 __evenaccess *)0x8C002)\r
+#define PORT3 (*(volatile struct st_port3 __evenaccess *)0x8C003)\r
+#define PORT4 (*(volatile struct st_port4 __evenaccess *)0x8C004)\r
+#define PORT5 (*(volatile struct st_port5 __evenaccess *)0x8C005)\r
+#define PORT6 (*(volatile struct st_port6 __evenaccess *)0x8C006)\r
+#define PORT7 (*(volatile struct st_port7 __evenaccess *)0x8C007)\r
+#define PORT8 (*(volatile struct st_port8 __evenaccess *)0x8C008)\r
+#define PORT9 (*(volatile struct st_port9 __evenaccess *)0x8C009)\r
+#define PORTA (*(volatile struct st_porta __evenaccess *)0x8C00A)\r
+#define PORTB (*(volatile struct st_portb __evenaccess *)0x8C00B)\r
+#define PORTC (*(volatile struct st_portc __evenaccess *)0x8C00C)\r
+#define PORTD (*(volatile struct st_portd __evenaccess *)0x8C00D)\r
+#define PORTE (*(volatile struct st_porte __evenaccess *)0x8C00E)\r
+#define PORTF (*(volatile struct st_portf __evenaccess *)0x8C00F)\r
+#define PORTG (*(volatile struct st_portg __evenaccess *)0x8C010)\r
+#define IOPORT (*(volatile struct st_ioport __evenaccess *)0x8C100)\r
+#define FLASH (*(volatile struct st_flash __evenaccess *)0x8C288)\r
+#define RTC (*(volatile struct st_rtc __evenaccess *)0x8C400)\r
+#define CAN0 (*(volatile struct st_can __evenaccess *)0x90200)\r
+#define USB0 (*(volatile struct st_usb0 __evenaccess *)0xA0000)\r
+#define USB1 (*(volatile struct st_usb0 __evenaccess *)0xA0200)\r
+#define USB (*(volatile struct st_usb __evenaccess *)0xA0400)\r
+#define EDMAC (*(volatile struct st_edmac __evenaccess *)0xC0000)\r
+#define ETHERC (*(volatile struct st_etherc __evenaccess *)0xC0100)\r
+#pragma bit_order\r
+#pragma packoption\r
+#endif
\ No newline at end of file
--- /dev/null
+/***********************************************************************/\r
+/* */\r
+/* FILE :lowsrc.h */\r
+/* DATE :Wed, Aug 11, 2010 */\r
+/* DESCRIPTION :Header file of I/O Stream file */\r
+/* CPU TYPE :Other */\r
+/* */\r
+/* This file is generated by Renesas Project Generator (Ver.4.50). */\r
+/* NOTE:THIS IS A TYPICAL EXAMPLE. */\r
+/* */\r
+/***********************************************************************/\r
+/*Number of I/O Stream*/\r
+#define IOSTREAM 20\r
--- /dev/null
+/***********************************************************************/\r
+/* */\r
+/* FILE :stacksct.h */\r
+/* DATE :Wed, Aug 11, 2010 */\r
+/* DESCRIPTION :Setting of Stack area */\r
+/* CPU TYPE :Other */\r
+/* */\r
+/* This file is generated by Renesas Project Generator (Ver.4.50). */\r
+/* NOTE:THIS IS A TYPICAL EXAMPLE. */\r
+/* */\r
+/***********************************************************************/\r
+#pragma stacksize su=0x300 \r
+#pragma stacksize si=0x100 \r
--- /dev/null
+/***********************************************************************/\r
+/* */\r
+/* FILE :typedefine.h */\r
+/* DATE :Wed, Aug 11, 2010 */\r
+/* DESCRIPTION :Aliases of Integer Type */\r
+/* CPU TYPE :Other */\r
+/* */\r
+/* This file is generated by Renesas Project Generator (Ver.4.50). */\r
+/* NOTE:THIS IS A TYPICAL EXAMPLE. */\r
+/* */\r
+/***********************************************************************/\r
+ \r
+\r
+\r
+/*********************************************************************\r
+*\r
+* Device : RX\r
+*\r
+* File Name : typedefine.h\r
+*\r
+* Abstract : Aliases of Integer Type.\r
+*\r
+* History : 1.00 (2009-08-07)\r
+*\r
+* NOTE : THIS IS A TYPICAL EXAMPLE.\r
+*\r
+* Copyright(c) 2009 Renesas Technology Corp.\r
+* And Renesas Solutions Corp.,All Rights Reserved. \r
+*\r
+*********************************************************************/\r
+\r
+typedef signed char _SBYTE;\r
+typedef unsigned char _UBYTE;\r
+typedef signed short _SWORD;\r
+typedef unsigned short _UWORD;\r
+typedef signed int _SINT;\r
+typedef unsigned int _UINT;\r
+typedef signed long _SDWORD;\r
+typedef unsigned long _UDWORD;\r
+typedef signed long long _SQWORD;\r
+typedef unsigned long long _UQWORD;\r
--- /dev/null
+/***********************************************************************/\r
+/* */\r
+/* FILE :vect.h */\r
+/* DATE :Wed, Aug 11, 2010 */\r
+/* DESCRIPTION :Definition of Vector */\r
+/* CPU TYPE :Other */\r
+/* */\r
+/* This file is generated by Renesas Project Generator (Ver.4.50). */\r
+/* NOTE:THIS IS A TYPICAL EXAMPLE. */\r
+/* */\r
+/***********************************************************************/\r
+ \r
+\r
+\r
+/*********************************************************************\r
+*\r
+* Device : RX/RX600\r
+*\r
+* File Name : vect.h\r
+*\r
+* Abstract : Definition of Vector.\r
+*\r
+* History : 1.00 (2009-08-07)\r
+*\r
+* NOTE : THIS IS A TYPICAL EXAMPLE.\r
+*\r
+* Copyright(c) 2009 Renesas Technology Corp.\r
+* And Renesas Solutions Corp.,All Rights Reserved. \r
+*\r
+*********************************************************************/\r
+\r
+// Exception(Supervisor Instruction)\r
+#pragma interrupt (Excep_SuperVisorInst)\r
+void Excep_SuperVisorInst(void);\r
+\r
+// Exception(Undefined Instruction)\r
+#pragma interrupt (Excep_UndefinedInst)\r
+void Excep_UndefinedInst(void);\r
+\r
+// Exception(Floating Point)\r
+#pragma interrupt (Excep_FloatingPoint)\r
+void Excep_FloatingPoint(void);\r
+\r
+// NMI\r
+#pragma interrupt (NonMaskableInterrupt)\r
+void NonMaskableInterrupt(void);\r
+\r
+// Dummy\r
+#pragma interrupt (Dummy)\r
+void Dummy(void);\r
+\r
+// BRK\r
+#pragma interrupt (Excep_BRK(vect=0))\r
+void Excep_BRK(void);\r
+\r
+//;<<VECTOR DATA START (POWER ON RESET)>>\r
+//;Power On Reset PC\r
+extern void PowerON_Reset_PC(void); \r
+//;<<VECTOR DATA END (POWER ON RESET)>>\r
+\r
--- /dev/null
+\r
+/******************************************************************************\r
+* DISCLAIMER\r
+* Please refer to http://www.renesas.com/disclaimer\r
+******************************************************************************\r
+ Copyright (C) 2008. Renesas Technology Corp., All Rights Reserved.\r
+*******************************************************************************\r
+* File Name : rsksh7216.h\r
+* Version : 1.00\r
+* Description : RSK 7216 board specific settings\r
+******************************************************************************\r
+* History : DD.MM.YYYY Version Description\r
+* : 06.10.2009 1.00 First Release\r
+******************************************************************************/\r
+\r
+#ifndef RSKRX62N_H\r
+#define RSKRX62N_H\r
+\r
+/******************************************************************************\r
+Includes <System Includes> , "Project Includes"\r
+******************************************************************************/\r
+\r
+/******************************************************************************\r
+Typedef definitions\r
+******************************************************************************/\r
+\r
+/******************************************************************************\r
+Macro definitions\r
+******************************************************************************/\r
+\r
+/* System Clock Settings */\r
+#define XTAL_FREQUENCY (12000000L)\r
+#define ICLK_MUL (8)\r
+#define PCLK_MUL (4)\r
+#define BCLK_MUL (4)\r
+#define ICLK_FREQUENCY (XTAL_FREQUENCY * ICLK_MUL)\r
+#define PCLK_FREQUENCY (XTAL_FREQUENCY * PCLK_MUL)\r
+#define BCLK_FREQUENCY (XTAL_FREQUENCY * BCLK_MUL)\r
+\r
+#define CMT0_CLK_SELECT (512)\r
+\r
+/* General Values */\r
+#define LED_ON (1)\r
+#define LED_OFF (0)\r
+\r
+/* LEDs */\r
+/* Define LEDs to Port Numbers */\r
+#define LED0 PORTD.DR.BIT.B0\r
+#define LED1 PORTD.DR.BIT.B1\r
+#define LED2 PORTD.DR.BIT.B2\r
+#define LED3 PORTD.DR.BIT.B3\r
+#define LED4 PORTD.DR.BIT.B4\r
+#define LED5 PORTD.DR.BIT.B5\r
+#define LED6 PORTD.DR.BIT.B6\r
+#define LED7 PORTD.DR.BIT.B7\r
+#define LED8 PORTE.DR.BIT.B0\r
+#define LED9 PORTE.DR.BIT.B1\r
+#define LED10 PORTE.DR.BIT.B2\r
+#define LED11 PORTE.DR.BIT.B3\r
+\r
+#define LED0_DDR PORTD.DDR.BIT.B0\r
+#define LED1_DDR PORTD.DDR.BIT.B1\r
+#define LED2_DDR PORTD.DDR.BIT.B2\r
+#define LED3_DDR PORTD.DDR.BIT.B3\r
+#define LED4_DDR PORTD.DDR.BIT.B4\r
+#define LED5_DDR PORTD.DDR.BIT.B5\r
+#define LED6_DDR PORTD.DDR.BIT.B6\r
+#define LED7_DDR PORTD.DDR.BIT.B7\r
+#define LED8_DDR PORTE.DDR.BIT.B0\r
+#define LED9_DDR PORTE.DDR.BIT.B1\r
+#define LED10_DDR PORTE.DDR.BIT.B2\r
+#define LED11_DDR PORTE.DDR.BIT.B3\r
+\r
+\r
+\r
+\r
+/******************************************************************************\r
+Variable Externs\r
+******************************************************************************/\r
+\r
+/******************************************************************************\r
+Functions Prototypes\r
+******************************************************************************/\r
+\r
+\r
+\r
+/* RSKRX62N_H */\r
+#endif \r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V6.0.5 - Copyright (C) 2010 Real Time Engineers Ltd.\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * If you are: *\r
+ * *\r
+ * + New to FreeRTOS, *\r
+ * + Wanting to learn FreeRTOS or multitasking in general quickly *\r
+ * + Looking for basic training, *\r
+ * + Wanting to improve your FreeRTOS skills and productivity *\r
+ * *\r
+ * then take a look at the FreeRTOS eBook *\r
+ * *\r
+ * "Using the FreeRTOS Real Time Kernel - a Practical Guide" *\r
+ * http://www.FreeRTOS.org/Documentation *\r
+ * *\r
+ * A pdf reference manual is also available. Both are usually delivered *\r
+ * to your inbox within 20 minutes to two hours when purchased between 8am *\r
+ * and 8pm GMT (although please allow up to 24 hours in case of *\r
+ * exceptional circumstances). Thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+ ***NOTE*** The exception to the GPL is included to allow you to distribute\r
+ a combined work that includes FreeRTOS without being obliged to provide the\r
+ source code for proprietary components outside of the FreeRTOS kernel.\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT\r
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\r
+ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ more details. You should have received a copy of the GNU General Public \r
+ License and the FreeRTOS license exception along with FreeRTOS; if not it \r
+ can be viewed here: http://www.freertos.org/a00114.html and also obtained \r
+ by writing to Richard Barry, contact details for whom are available on the\r
+ FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+\r
+ http://www.FreeRTOS.org - Documentation, latest information, license and\r
+ contact details.\r
+\r
+ http://www.SafeRTOS.com - A version that is certified for use in safety\r
+ critical systems.\r
+\r
+ http://www.OpenRTOS.com - Commercial support, development, porting,\r
+ licensing and training services.\r
+*/\r
+\r
+/* \r
+ * This is a very simple demo that creates two tasks and one queue. One task\r
+ * (the queue receive task) blocks on the queue to wait for data to arrive, \r
+ * toggling an LED each time '100' is received. The other task (the queue send\r
+ * task) repeatedly blocks for a fixed period before sending '100' to the queue\r
+ * (causing the first task to toggle the LED). \r
+ *\r
+ * For a much more complete and complex example select either the Debug or\r
+ * Debug_with_optimisation build configurations within the HEW IDE. \r
+*/\r
+\r
+/* Hardware specific includes. */\r
+#include "iodefine.h"\r
+\r
+/* Kernel includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "queue.h"\r
+\r
+/* Priorities at which the tasks are created. */\r
+#define configQUEUE_RECEIVE_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 )\r
+#define configQUEUE_SEND_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
+\r
+/* The rate at which data is sent to the queue, specified in milliseconds. */\r
+#define mainQUEUE_SEND_FREQUENCY_MS ( 500 / portTICK_RATE_MS )\r
+\r
+/* The number of items the queue can hold. This is 1 as the receive task\r
+will remove items as they are added so the send task should always find the\r
+queue empty. */\r
+#define mainQUEUE_LENGTH ( 1 )\r
+\r
+/*\r
+ * The tasks as defined at the top of this file.\r
+ */\r
+static void prvQueueReceiveTask( void *pvParameters );\r
+static void prvQueueSendTask( void *pvParameters );\r
+\r
+/* The queue used by both tasks. */\r
+static xQueueHandle xQueue = NULL;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void main(void)\r
+{\r
+extern void HardwareSetup( void );\r
+\r
+ /* Renesas provided CPU configuration routine. The clocks are configured in\r
+ here. */\r
+ HardwareSetup();\r
+ \r
+ /* Turn all LEDs off. */\r
+ vParTestInitialise();\r
+ \r
+ /* Create the queue. */\r
+ xQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( unsigned long ) );\r
+\r
+ if( xQueue != NULL )\r
+ {\r
+ /* Start the two tasks as described at the top of this file. */\r
+ xTaskCreate( prvQueueReceiveTask, "Rx", configMINIMAL_STACK_SIZE, NULL, configQUEUE_RECEIVE_TASK_PRIORITY, NULL );\r
+ xTaskCreate( prvQueueSendTask, "TX", configMINIMAL_STACK_SIZE, NULL, configQUEUE_SEND_TASK_PRIORITY, NULL );\r
+\r
+ /* Start the tasks running. */\r
+ vTaskStartScheduler();\r
+ }\r
+ \r
+ /* If all is well we will never reach here as the scheduler will now be\r
+ running. If we do reach here then it is likely that there was insufficient\r
+ heap available for the idle task to be created. */\r
+ for( ;; );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvQueueSendTask( void *pvParameters )\r
+{\r
+portTickType xNextWakeTime;\r
+const unsigned long ulValueToSend = 100UL;\r
+\r
+ /* Initialise xNextWakeTime - this only needs to be done once. */\r
+ xNextWakeTime = xTaskGetTickCount();\r
+\r
+ for( ;; )\r
+ {\r
+ /* Place this task in the blocked state until it is time to run again. \r
+ The block state is specified in ticks, the constant used converts ticks\r
+ to ms. */\r
+ vTaskDelayUntil( &xNextWakeTime, mainQUEUE_SEND_FREQUENCY_MS );\r
+\r
+ /* Send to the queue - causing the queue receive task to flash its LED. 0\r
+ is used so the send does not block - it shouldn't need to as the queue\r
+ should always be empty here. */\r
+ xQueueSend( xQueue, &ulValueToSend, 0 );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvQueueReceiveTask( void *pvParameters )\r
+{\r
+unsigned long ulReceivedValue;\r
+\r
+ for( ;; )\r
+ {\r
+ /* Wait until something arives in the queue - this will block \r
+ indefinitely provided INCLUDE_vTaskSuspend is set to 1 in\r
+ FreeRTOSConfig.h. */\r
+ xQueueReceive( xQueue, &ulReceivedValue, portMAX_DELAY );\r
+\r
+ /* To get here something must have arrived, but is it the expected\r
+ value? If it is, toggle the LED. */\r
+ if( ulReceivedValue == 100UL )\r
+ {\r
+ vParTestToggleLED( 0 );\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationSetupTimerInterrupt( void )\r
+{\r
+ /* Enable compare match timer 0. */\r
+ MSTP( CMT0 ) = 0;\r
+ \r
+ /* Interrupt on compare match. */\r
+ CMT0.CMCR.BIT.CMIE = 1;\r
+ \r
+ /* Set the compare match value. */\r
+ CMT0.CMCOR = ( unsigned short ) ( ( ( configPERIPHERAL_CLOCK_HZ / configTICK_RATE_HZ ) -1 ) / 8 );\r
+ \r
+ /* Divide the PCLK by 8. */\r
+ CMT0.CMCR.BIT.CKS = 0;\r
+ \r
+ /* Enable the interrupt... */\r
+ _IEN( _CMT0_CMI0 ) = 1;\r
+ \r
+ /* ...and set its priority to the application defined kernel priority. */\r
+ _IPR( _CMT0_CMI0 ) = configKERNEL_INTERRUPT_PRIORITY;\r
+ \r
+ /* Start the timer. */\r
+ CMT.CMSTR0.BIT.STR0 = 1;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* This function is explained by the comments above its prototype at the top\r
+of this file. */\r
+void vApplicationMallocFailedHook( void )\r
+{\r
+ for( ;; );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* This function is explained by the comments above its prototype at the top\r
+of this file. */\r
+void vApplicationStackOverflowHook( xTaskHandle *pxTask, signed char *pcTaskName )\r
+{\r
+ for( ;; );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* This function is explained by the comments above its prototype at the top\r
+of this file. */\r
+void vApplicationIdleHook( void )\r
+{\r
+}\r
+/*-----------------------------------------------------------*/\r
--- /dev/null
+/*\r
+ FreeRTOS V6.0.5 - Copyright (C) 2010 Real Time Engineers Ltd.\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * If you are: *\r
+ * *\r
+ * + New to FreeRTOS, *\r
+ * + Wanting to learn FreeRTOS or multitasking in general quickly *\r
+ * + Looking for basic training, *\r
+ * + Wanting to improve your FreeRTOS skills and productivity *\r
+ * *\r
+ * then take a look at the FreeRTOS eBook *\r
+ * *\r
+ * "Using the FreeRTOS Real Time Kernel - a Practical Guide" *\r
+ * http://www.FreeRTOS.org/Documentation *\r
+ * *\r
+ * A pdf reference manual is also available. Both are usually delivered *\r
+ * to your inbox within 20 minutes to two hours when purchased between 8am *\r
+ * and 8pm GMT (although please allow up to 24 hours in case of *\r
+ * exceptional circumstances). Thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+ ***NOTE*** The exception to the GPL is included to allow you to distribute\r
+ a combined work that includes FreeRTOS without being obliged to provide the\r
+ source code for proprietary components outside of the FreeRTOS kernel.\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT\r
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\r
+ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ more details. You should have received a copy of the GNU General Public\r
+ License and the FreeRTOS license exception along with FreeRTOS; if not it\r
+ can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
+ by writing to Richard Barry, contact details for whom are available on the\r
+ FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+\r
+ http://www.FreeRTOS.org - Documentation, latest information, license and\r
+ contact details.\r
+\r
+ http://www.SafeRTOS.com - A version that is certified for use in safety\r
+ critical systems.\r
+\r
+ http://www.OpenRTOS.com - Commercial support, development, porting,\r
+ licensing and training services.\r
+*/\r
+\r
+/*\r
+ * This project includes a lot of tasks and tests and is therefore complex.\r
+ * If you would prefer a much simpler project to get started with then select\r
+ * the 'Blinky' build configuration within the HEW IDE.\r
+ *\r
+ * Creates all the demo application tasks, then starts the scheduler. The web\r
+ * documentation provides more details of the standard demo application tasks,\r
+ * which provide no particular functionality but do provide a good example of\r
+ * how to use the FreeRTOS API. The tasks defined in flop.c are included in the\r
+ * set of standard demo tasks to ensure the floating point unit gets some\r
+ * exercise.\r
+ *\r
+ * In addition to the standard demo tasks, the following tasks and tests are\r
+ * defined and/or created within this file:\r
+ *\r
+ * "Reg test" tasks - These fill the registers with known values, then check\r
+ * that each register still contains its expected value. Each task uses\r
+ * different values. The tasks run with very low priority so get preempted\r
+ * very frequently. A check variable is incremented on each iteration of the\r
+ * test loop. A register containing an unexpected value is indicative of an\r
+ * error in the context switching mechanism and will result in a branch to a\r
+ * null loop - which in turn will prevent the check variable from incrementing\r
+ * any further and allow the check task (described below) to determine that an\r
+ * error has occurred. The nature of the reg test tasks necessitates that they\r
+ * are written in assembly code.\r
+ *\r
+ * "Check" task - This only executes every five seconds but has a high priority\r
+ * to ensure it gets processor time. Its main function is to check that all the\r
+ * standard demo tasks are still operational. While no errors have been\r
+ * discovered the check task will toggle LED 5 every 5 seconds - the toggle\r
+ * rate increasing to 200ms being a visual indication that at least one task has\r
+ * reported unexpected behaviour.\r
+ *\r
+ * "High frequency timer test" - A high frequency periodic interrupt is\r
+ * generated using a timer - the interrupt is assigned a priority above\r
+ * configMAX_SYSCALL_INTERRUPT_PRIORITY so should not be effected by anything\r
+ * the kernel is doing. The interrupt service routine measures the number of\r
+ * counts a separate timer performs between each interrupt to determine the\r
+ * jitter in the interrupt timing.\r
+ *\r
+ * *NOTE 1* If LED5 is toggling every 5 seconds then all the demo application\r
+ * tasks are executing as expected and no errors have been reported in any\r
+ * tasks. The toggle rate increasing to 200ms indicates that at least one task\r
+ * has reported unexpected behaviour.\r
+ *\r
+ * *NOTE 2* vApplicationSetupTimerInterrupt() is called by the kernel to let\r
+ * the application set up a timer to generate the tick interrupt. In this\r
+ * example a compare match timer is used for this purpose.\r
+ *\r
+ * *NOTE 3* The CPU must be in Supervisor mode when the scheduler is started.\r
+ * The PowerON_Reset_PC() supplied in resetprg.c with this demo has\r
+ * Change_PSW_PM_to_UserMode() commented out to ensure this is the case.\r
+ *\r
+ * *NOTE 4* The IntQueue common demo tasks test interrupt nesting and make use\r
+ * of all the 8bit timers (as two cascaded 16bit units).\r
+*/\r
+\r
+/* Hardware specific includes. */\r
+#include "iodefine.h"\r
+\r
+/* Kernel includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/* Standard demo includes. */\r
+#include "partest.h"\r
+#include "flash.h"\r
+#include "IntQueue.h"\r
+#include "BlockQ.h"\r
+#include "death.h"\r
+#include "integer.h"\r
+#include "blocktim.h"\r
+#include "semtest.h"\r
+#include "PollQ.h"\r
+#include "GenQTest.h"\r
+#include "QPeek.h"\r
+#include "recmutex.h"\r
+#include "flop.h"\r
+\r
+/* Values that are passed into the reg test tasks using the task parameter. The\r
+tasks check that the values are passed in correctly. */\r
+#define mainREG_TEST_1_PARAMETER ( 0x12121212UL )\r
+#define mainREG_TEST_2_PARAMETER ( 0x12345678UL )\r
+\r
+/* Priorities at which the tasks are created. */\r
+#define mainCHECK_TASK_PRIORITY ( configMAX_PRIORITIES - 1 )\r
+#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 1 )\r
+#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 )\r
+#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
+#define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 )\r
+#define mainFLASH_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 )\r
+#define mainuIP_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
+#define mainINTEGER_TASK_PRIORITY ( tskIDLE_PRIORITY )\r
+#define mainGEN_QUEUE_TASK_PRIORITY ( tskIDLE_PRIORITY )\r
+#define mainFLOP_TASK_PRIORITY ( tskIDLE_PRIORITY )\r
+\r
+/* The LED toggled by the check task. */\r
+#define mainCHECK_LED ( 5 )\r
+\r
+/* The rate at which mainCHECK_LED will toggle when all the tasks are running\r
+without error. Controlled by the check task as described at the top of this\r
+file. */\r
+#define mainNO_ERROR_CYCLE_TIME ( 5000 / portTICK_RATE_MS )\r
+\r
+/* The rate at which mainCHECK_LED will toggle when an error has been reported\r
+by at least one task. Controlled by the check task as described at the top of\r
+this file. */\r
+#define mainERROR_CYCLE_TIME ( 200 / portTICK_RATE_MS )\r
+\r
+/* The period of the peripheral clock in nano seconds. This is used to calculate\r
+the jitter time in nano seconds as part of the high frequency timer test. The\r
+clock driving the timer is divided by 8. */\r
+#define mainNS_PER_CLOCK ( ( unsigned long ) ( ( 1.0 / ( ( double ) configPERIPHERAL_CLOCK_HZ ) / 8.0 ) * 1000000000.0 ) )\r
+\r
+/*\r
+ * vApplicationMallocFailedHook() will only be called if\r
+ * configUSE_MALLOC_FAILED_HOOK is set to 1 in FreeRTOSConfig.h. It is a hook\r
+ * function that will execute if a call to pvPortMalloc() fails.\r
+ * pvPortMalloc() is called internally by the kernel whenever a task, queue or\r
+ * semaphore is created. It is also called by various parts of the demo\r
+ * application.\r
+ */\r
+void vApplicationMallocFailedHook( void );\r
+\r
+/*\r
+ * vApplicationIdleHook() will only be called if configUSE_IDLE_HOOK is set to 1\r
+ * in FreeRTOSConfig.h. It is a hook function that is called on each iteration\r
+ * of the idle task. It is essential that code added to this hook function\r
+ * never attempts to block in any way (for example, call xQueueReceive() with\r
+ * a block time specified). If the application makes use of the vTaskDelete()\r
+ * API function (as this demo application does) then it is also important that\r
+ * vApplicationIdleHook() is permitted to return to its calling function because\r
+ * it is the responsibility of the idle task to clean up memory allocated by the\r
+ * kernel to any task that has since been deleted.\r
+ */\r
+void vApplicationIdleHook( void );\r
+\r
+/*\r
+ * vApplicationStackOverflowHook() will only be called if\r
+ * configCHECK_FOR_STACK_OVERFLOW is set to a non-zero value. The handle and\r
+ * name of the offending task should be passed in the function parameters, but\r
+ * it is possible that the stack overflow will have corrupted these - in which\r
+ * case pxCurrentTCB can be inspected to find the same information.\r
+ */\r
+void vApplicationStackOverflowHook( xTaskHandle *pxTask, signed char *pcTaskName );\r
+\r
+/*\r
+ * The reg test tasks as described at the top of this file.\r
+ */\r
+static void prvRegTest1Task( void *pvParameters );\r
+static void prvRegTest2Task( void *pvParameters );\r
+\r
+/*\r
+ * The actual implementation of the reg test functionality, which, because of\r
+ * the direct register access, have to be in assembly.\r
+ */\r
+static void prvRegTest1Implementation( void );\r
+static void prvRegTest2Implementation( void );\r
+\r
+/*\r
+ * The check task as described at the top of this file.\r
+ */\r
+static void prvCheckTask( void *pvParameters );\r
+\r
+/* Variables that are incremented on each iteration of the reg test tasks -\r
+provided the tasks have not reported any errors. The check task inspects these\r
+variables to ensure they are still incrementing as expected. If a variable\r
+stops incrementing then it is likely that its associate task has stalled. */\r
+unsigned long ulRegTest1CycleCount = 0UL, ulRegTest2CycleCount = 0UL;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void main(void)\r
+{\r
+extern void HardwareSetup( void );\r
+\r
+ /* Renesas provided CPU configuration routine. The clocks are configured in\r
+ here. */\r
+ HardwareSetup();\r
+\r
+ /* Turn all LEDs off. */\r
+ vParTestInitialise();\r
+\r
+ /* Start the reg test tasks which test the context switching mechanism. */\r
+ xTaskCreate( prvRegTest1Task, "RegTst1", configMINIMAL_STACK_SIZE, ( void * ) mainREG_TEST_1_PARAMETER, tskIDLE_PRIORITY, NULL );\r
+ xTaskCreate( prvRegTest2Task, "RegTst2", configMINIMAL_STACK_SIZE, ( void * ) mainREG_TEST_2_PARAMETER, tskIDLE_PRIORITY, NULL );\r
+\r
+ /* Start the check task as described at the top of this file. */\r
+ xTaskCreate( prvCheckTask, "Check", configMINIMAL_STACK_SIZE * 3, NULL, mainCHECK_TASK_PRIORITY, NULL );\r
+\r
+ /* Create the standard demo tasks. */\r
+ vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY );\r
+ vCreateBlockTimeTasks();\r
+ vStartSemaphoreTasks( mainSEM_TEST_PRIORITY );\r
+ vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY );\r
+ vStartIntegerMathTasks( mainINTEGER_TASK_PRIORITY );\r
+ vStartGenericQueueTasks( mainGEN_QUEUE_TASK_PRIORITY );\r
+ vStartLEDFlashTasks( mainFLASH_TASK_PRIORITY );\r
+ vStartQueuePeekTasks();\r
+ vStartRecursiveMutexTasks();\r
+ vStartInterruptQueueTasks();\r
+ vStartMathTasks( mainFLOP_TASK_PRIORITY );\r
+\r
+ /* The suicide tasks must be created last as they need to know how many\r
+ tasks were running prior to their creation in order to ascertain whether\r
+ or not the correct/expected number of tasks are running at any given time. */\r
+ vCreateSuicidalTasks( mainCREATOR_TASK_PRIORITY );\r
+\r
+ /* Start the tasks running. */\r
+ vTaskStartScheduler();\r
+\r
+ /* If all is well we will never reach here as the scheduler will now be\r
+ running. If we do reach here then it is likely that there was insufficient\r
+ heap available for the idle task to be created. */\r
+ for( ;; );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvCheckTask( void *pvParameters )\r
+{\r
+static volatile unsigned long ulLastRegTest1CycleCount = 0UL, ulLastRegTest2CycleCount = 0UL;\r
+portTickType xNextWakeTime, xCycleFrequency = mainNO_ERROR_CYCLE_TIME;\r
+extern void vSetupHighFrequencyTimer( void );\r
+extern volatile unsigned short usMaxJitter;\r
+volatile unsigned long ulActualJitter = 0;\r
+static char cErrorText[ 100 ];\r
+\r
+ /* If this is being executed then the kernel has been started. Start the high\r
+ frequency timer test as described at the top of this file. This is only\r
+ included in the optimised build configuration - otherwise it takes up too much\r
+ CPU time. */\r
+ #ifdef INCLUDE_HIGH_FREQUENCY_TIMER_TEST\r
+ vSetupHighFrequencyTimer();\r
+ #endif\r
+\r
+ /* Initialise xNextWakeTime - this only needs to be done once. */\r
+ xNextWakeTime = xTaskGetTickCount();\r
+\r
+ for( ;; )\r
+ {\r
+ /* Place this task in the blocked state until it is time to run again. */\r
+ vTaskDelayUntil( &xNextWakeTime, xCycleFrequency );\r
+\r
+ /* Check the standard demo tasks are running without error. */\r
+ if( xAreGenericQueueTasksStillRunning() != pdTRUE )\r
+ {\r
+ /* Increase the rate at which this task cycles, which will increase the\r
+ rate at which mainCHECK_LED flashes to give visual feedback that an error\r
+ has occurred. */\r
+ xCycleFrequency = mainERROR_CYCLE_TIME;\r
+ strcpy( cErrorText, "Error: GenQueue" );\r
+ }\r
+ else if( xAreQueuePeekTasksStillRunning() != pdTRUE )\r
+ {\r
+ xCycleFrequency = mainERROR_CYCLE_TIME;\r
+ strcpy( cErrorText, "Error: QueuePeek" );\r
+ }\r
+ else if( xAreBlockingQueuesStillRunning() != pdTRUE )\r
+ {\r
+ xCycleFrequency = mainERROR_CYCLE_TIME;\r
+ strcpy( cErrorText, "Error: BlockQueue" );\r
+ }\r
+ else if( xAreBlockTimeTestTasksStillRunning() != pdTRUE )\r
+ {\r
+ xCycleFrequency = mainERROR_CYCLE_TIME;\r
+ strcpy( cErrorText, "Error: BlockTime" );\r
+ }\r
+ else if( xAreSemaphoreTasksStillRunning() != pdTRUE )\r
+ {\r
+ xCycleFrequency = mainERROR_CYCLE_TIME;\r
+ strcpy( cErrorText, "Error: SemTest" );\r
+ }\r
+ else if( xArePollingQueuesStillRunning() != pdTRUE )\r
+ {\r
+ xCycleFrequency = mainERROR_CYCLE_TIME;\r
+ strcpy( cErrorText, "Error: PollQueue" );\r
+ }\r
+ else if( xIsCreateTaskStillRunning() != pdTRUE )\r
+ {\r
+ xCycleFrequency = mainERROR_CYCLE_TIME;\r
+ strcpy( cErrorText, "Error: Death" );\r
+ }\r
+ else if( xAreIntegerMathsTaskStillRunning() != pdTRUE )\r
+ {\r
+ xCycleFrequency = mainERROR_CYCLE_TIME;\r
+ strcpy( cErrorText, "Error: IntMath" );\r
+ }\r
+ else if( xAreRecursiveMutexTasksStillRunning() != pdTRUE )\r
+ {\r
+ xCycleFrequency = mainERROR_CYCLE_TIME;\r
+ strcpy( cErrorText, "Error: RecMutex" );\r
+ }\r
+ else if( xAreIntQueueTasksStillRunning() != pdPASS )\r
+ {\r
+ xCycleFrequency = mainERROR_CYCLE_TIME;\r
+ strcpy( cErrorText, "Error: IntQueue" );\r
+ }\r
+ else if( xAreMathsTaskStillRunning() != pdPASS )\r
+ {\r
+ xCycleFrequency = mainERROR_CYCLE_TIME;\r
+ strcpy( cErrorText, "Error: Flop" );\r
+ }\r
+\r
+ /* Check the reg test tasks are still cycling. They will stop incrementing\r
+ their loop counters if they encounter an error. */\r
+ if( ulRegTest1CycleCount == ulLastRegTest1CycleCount )\r
+ {\r
+ xCycleFrequency = mainERROR_CYCLE_TIME;\r
+ strcpy( cErrorText, "Error: RegTest1" );\r
+ }\r
+\r
+ if( ulRegTest2CycleCount == ulLastRegTest2CycleCount )\r
+ {\r
+ xCycleFrequency = mainERROR_CYCLE_TIME;\r
+ strcpy( cErrorText, "Error: RegTest2" );\r
+ }\r
+\r
+ ulLastRegTest1CycleCount = ulRegTest1CycleCount;\r
+ ulLastRegTest2CycleCount = ulRegTest2CycleCount;\r
+\r
+ /* Toggle the check LED to give an indication of the system status. If\r
+ the LED toggles every 5 seconds then everything is ok. A faster toggle\r
+ indicates an error. */\r
+ vParTestToggleLED( mainCHECK_LED );\r
+\r
+ /* Calculate the maximum jitter experienced by the high frequency timer\r
+ test and print it out. It is ok to use printf without worrying about\r
+ mutual exclusion as it is not used anywhere else in this demo. */\r
+ //sprintf( cTempBuf, "%s [%fns]\n", "Max Jitter = ", ( ( float ) usMaxJitter ) * mainNS_PER_CLOCK );\r
+ ulActualJitter = ( ( unsigned long ) usMaxJitter ) * mainNS_PER_CLOCK;\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* The RX port uses this callback function to configure its tick interrupt.\r
+This allows the application to choose the tick interrupt source. */\r
+void vApplicationSetupTimerInterrupt( void )\r
+{\r
+ /* Enable compare match timer 0. */\r
+ MSTP( CMT0 ) = 0;\r
+\r
+ /* Interrupt on compare match. */\r
+ CMT0.CMCR.BIT.CMIE = 1;\r
+\r
+ /* Set the compare match value. */\r
+ CMT0.CMCOR = ( unsigned short ) ( ( ( configPERIPHERAL_CLOCK_HZ / configTICK_RATE_HZ ) -1 ) / 8 );\r
+\r
+ /* Divide the PCLK by 8. */\r
+ CMT0.CMCR.BIT.CKS = 0;\r
+\r
+ /* Enable the interrupt... */\r
+ _IEN( _CMT0_CMI0 ) = 1;\r
+\r
+ /* ...and set its priority to the application defined kernel priority. */\r
+ _IPR( _CMT0_CMI0 ) = configKERNEL_INTERRUPT_PRIORITY;\r
+\r
+ /* Start the timer. */\r
+ CMT.CMSTR0.BIT.STR0 = 1;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* This function is explained by the comments above its prototype at the top\r
+of this file. */\r
+void vApplicationMallocFailedHook( void )\r
+{\r
+ for( ;; );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* This function is explained by the comments above its prototype at the top\r
+of this file. */\r
+void vApplicationStackOverflowHook( xTaskHandle *pxTask, signed char *pcTaskName )\r
+{\r
+ for( ;; );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* This function is explained by the comments above its prototype at the top\r
+of this file. */\r
+void vApplicationIdleHook( void )\r
+{\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* This function is explained in the comments at the top of this file. */\r
+static void prvRegTest1Task( void *pvParameters )\r
+{\r
+ if( ( ( unsigned long ) pvParameters ) != mainREG_TEST_1_PARAMETER )\r
+ {\r
+ /* The parameter did not contain the expected value. */\r
+ for( ;; )\r
+ {\r
+ /* Stop the tick interrupt so its obvious something has gone wrong. */\r
+ taskDISABLE_INTERRUPTS();\r
+ }\r
+ }\r
+\r
+ /* This is an inline asm function that never returns. */\r
+ prvRegTest1Implementation();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* This function is explained in the comments at the top of this file. */\r
+static void prvRegTest2Task( void *pvParameters )\r
+{\r
+ if( ( ( unsigned long ) pvParameters ) != mainREG_TEST_2_PARAMETER )\r
+ {\r
+ /* The parameter did not contain the expected value. */\r
+ for( ;; )\r
+ {\r
+ /* Stop the tick interrupt so its obvious something has gone wrong. */\r
+ taskDISABLE_INTERRUPTS();\r
+ }\r
+ }\r
+\r
+ /* This is an inline asm function that never returns. */\r
+ prvRegTest2Implementation();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* This function is explained in the comments at the top of this file. */\r
+#pragma inline_asm prvRegTest1Implementation\r
+static void prvRegTest1Implementation( void )\r
+{\r
+ ; Put a known value in each register.\r
+ MOV.L #1, R1\r
+ MOV.L #2, R2\r
+ MOV.L #3, R3\r
+ MOV.L #4, R4\r
+ MOV.L #5, R5\r
+ MOV.L #6, R6\r
+ MOV.L #7, R7\r
+ MOV.L #8, R8\r
+ MOV.L #9, R9\r
+ MOV.L #10, R10\r
+ MOV.L #11, R11\r
+ MOV.L #12, R12\r
+ MOV.L #13, R13\r
+ MOV.L #14, R14\r
+ MOV.L #15, R15\r
+\r
+ ; Loop, checking each itteration that each register still contains the\r
+ ; expected value.\r
+TestLoop1:\r
+\r
+ ; Push the registers that are going to get clobbered.\r
+ PUSHM R14-R15\r
+\r
+ ; Increment the loop counter to show this task is still getting CPU time.\r
+ MOV.L #_ulRegTest1CycleCount, R14\r
+ MOV.L [ R14 ], R15\r
+ ADD #1, R15\r
+ MOV.L R15, [ R14 ]\r
+\r
+ ; Yield to extend the text coverage. Set the bit in the ITU SWINTR register.\r
+ MOV.L #1, R14\r
+ MOV.L #0872E0H, R15\r
+ MOV.B R14, [R15]\r
+ NOP\r
+ NOP\r
+\r
+ ; Restore the clobbered registers.\r
+ POPM R14-R15\r
+\r
+ ; Now compare each register to ensure it still contains the value that was\r
+ ; set before this loop was entered.\r
+ CMP #1, R1\r
+ BNE RegTest1Error\r
+ CMP #2, R2\r
+ BNE RegTest1Error\r
+ CMP #3, R3\r
+ BNE RegTest1Error\r
+ CMP #4, R4\r
+ BNE RegTest1Error\r
+ CMP #5, R5\r
+ BNE RegTest1Error\r
+ CMP #6, R6\r
+ BNE RegTest1Error\r
+ CMP #7, R7\r
+ BNE RegTest1Error\r
+ CMP #8, R8\r
+ BNE RegTest1Error\r
+ CMP #9, R9\r
+ BNE RegTest1Error\r
+ CMP #10, R10\r
+ BNE RegTest1Error\r
+ CMP #11, R11\r
+ BNE RegTest1Error\r
+ CMP #12, R12\r
+ BNE RegTest1Error\r
+ CMP #13, R13\r
+ BNE RegTest1Error\r
+ CMP #14, R14\r
+ BNE RegTest1Error\r
+ CMP #15, R15\r
+ BNE RegTest1Error\r
+\r
+ ; All comparisons passed, start a new itteratio of this loop.\r
+ BRA TestLoop1\r
+\r
+RegTest1Error:\r
+ ; A compare failed, just loop here so the loop counter stops incrementing\r
+ ; causing the check task to indicate the error.\r
+ BRA RegTest1Error\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* This function is explained in the comments at the top of this file. */\r
+#pragma inline_asm prvRegTest2Implementation\r
+static void prvRegTest2Implementation( void )\r
+{\r
+ ; Put a known value in each register.\r
+ MOV.L #10, R1\r
+ MOV.L #20, R2\r
+ MOV.L #30, R3\r
+ MOV.L #40, R4\r
+ MOV.L #50, R5\r
+ MOV.L #60, R6\r
+ MOV.L #70, R7\r
+ MOV.L #80, R8\r
+ MOV.L #90, R9\r
+ MOV.L #100, R10\r
+ MOV.L #110, R11\r
+ MOV.L #120, R12\r
+ MOV.L #130, R13\r
+ MOV.L #140, R14\r
+ MOV.L #150, R15\r
+\r
+ ; Loop, checking on each itteration that each register still contains the\r
+ ; expected value.\r
+TestLoop2:\r
+\r
+ ; Push the registers that are going to get clobbered.\r
+ PUSHM R14-R15\r
+\r
+ ; Increment the loop counter to show this task is still getting CPU time.\r
+ MOV.L #_ulRegTest2CycleCount, R14\r
+ MOV.L [ R14 ], R15\r
+ ADD #1, R15\r
+ MOV.L R15, [ R14 ]\r
+\r
+ ; Restore the clobbered registers.\r
+ POPM R14-R15\r
+\r
+ CMP #10, R1\r
+ BNE RegTest2Error\r
+ CMP #20, R2\r
+ BNE RegTest2Error\r
+ CMP #30, R3\r
+ BNE RegTest2Error\r
+ CMP #40, R4\r
+ BNE RegTest2Error\r
+ CMP #50, R5\r
+ BNE RegTest2Error\r
+ CMP #60, R6\r
+ BNE RegTest2Error\r
+ CMP #70, R7\r
+ BNE RegTest2Error\r
+ CMP #80, R8\r
+ BNE RegTest2Error\r
+ CMP #90, R9\r
+ BNE RegTest2Error\r
+ CMP #100, R10\r
+ BNE RegTest2Error\r
+ CMP #110, R11\r
+ BNE RegTest2Error\r
+ CMP #120, R12\r
+ BNE RegTest2Error\r
+ CMP #130, R13\r
+ BNE RegTest2Error\r
+ CMP #140, R14\r
+ BNE RegTest2Error\r
+ CMP #150, R15\r
+ BNE RegTest2Error\r
+\r
+ ; All comparisons passed, start a new itteratio of this loop.\r
+ BRA TestLoop2\r
+\r
+RegTest2Error:\r
+ ; A compare failed, just loop here so the loop counter stops incrementing\r
+ ; - causing the check task to indicate the error.\r
+ BRA RegTest2Error\r
+}\r
+\r
+\r
+\r
+\r
+\r
projects / freertos / commitdiff