return ERROR_NAND_OPERATION_NOT_SUPPORTED;
}
- if (oob && (oob_size > 6))
+ if (oob && (oob_size > 24))
{
- LOG_ERROR("LPC3180 MLC controller can't write more than 6 bytes of OOB data");
+ LOG_ERROR("LPC3180 MLC controller can't write more "
+ "than 6 bytes for each quarter's OOB data");
return ERROR_NAND_OPERATION_NOT_SUPPORTED;
}
data += thisrun_data_size;
}
- memset(oob_buffer, 0xff, (nand->page_size == 512) ? 6 : 24);
+ memset(oob_buffer, 0xff, 6);
if (oob)
{
- memcpy(page_buffer, oob, thisrun_oob_size);
+ memcpy(oob_buffer, oob, thisrun_oob_size);
oob_size -= thisrun_oob_size;
oob += thisrun_oob_size;
}
/* write MLC_ECC_ENC_REG to start encode cycle */
target_write_u32(target, 0x200b8008, 0x0);
- target_write_memory(target, 0x200a8000, 4, 128, page_buffer + (quarter * 512));
- target_write_memory(target, 0x200a8000, 1, 6, oob_buffer + (quarter * 6));
+ target_write_memory(target, 0x200a8000,
+ 4, 128, page_buffer);
+ target_write_memory(target, 0x200a8000,
+ 1, 6, oob_buffer);
/* write MLC_ECC_AUTO_ENC_REG to start auto encode */
target_write_u32(target, 0x200b8010, 0x0);
{
struct lpc3180_nand_controller *lpc3180_info = nand->controller_priv;
struct target *target = lpc3180_info->target;
- uint8_t status = 0x0;
if (target->state != TARGET_HALTED)
{
return ERROR_NAND_OPERATION_FAILED;
}
+ LOG_DEBUG("lpc3180_controller_ready count start=%d", timeout);
+
do
{
if (lpc3180_info->selected_controller == LPC3180_MLC_CONTROLLER)
{
+ uint8_t status;
+
/* Read MLC_ISR, wait for controller to become ready */
target_read_u8(target, 0x200b8048, &status);
- if (status & 2)
+ if (status & 2) {
+ LOG_DEBUG("lpc3180_controller_ready count=%d",
+ timeout);
return 1;
+ }
}
else if (lpc3180_info->selected_controller == LPC3180_SLC_CONTROLLER)
{
- /* we pretend that the SLC controller is always ready */
- return 1;
+ uint32_t status;
+
+ /* Read SLC_STAT and check READY bit */
+ target_read_u32(target, 0x20020018, &status);
+
+ if (status & 1) {
+ LOG_DEBUG("lpc3180_controller_ready count=%d",
+ timeout);
+ return 1;
+ }
}
alive_sleep(1);
return ERROR_NAND_OPERATION_FAILED;
}
+ LOG_DEBUG("lpc3180_nand_ready count start=%d", timeout);
+
do
{
if (lpc3180_info->selected_controller == LPC3180_MLC_CONTROLLER)
/* Read MLC_ISR, wait for NAND flash device to become ready */
target_read_u8(target, 0x200b8048, &status);
- if (status & 1)
+ if (status & 1) {
+ LOG_DEBUG("lpc3180_nand_ready count end=%d",
+ timeout);
return 1;
+ }
}
else if (lpc3180_info->selected_controller == LPC3180_SLC_CONTROLLER)
{
/* Read SLC_STAT and check READY bit */
target_read_u32(target, 0x20020018, &status);
- if (status & 1)
+ if (status & 1) {
+ LOG_DEBUG("lpc3180_nand_ready count end=%d",
+ timeout);
return 1;
+ }
}
alive_sleep(1);
}
unsigned num;
- COMMAND_PARSE_NUMBER(uint, CMD_ARGV[1], num);
+ COMMAND_PARSE_NUMBER(uint, CMD_ARGV[0], num);
struct nand_device *nand = get_nand_device_by_num(num);
if (!nand)
{