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+ <option id="com.renesas.cdt.core.Compiler.option.warning31.531473224" name="Give string constants the type 'const char[length]'(-Wwrite-strings)" superClass="com.renesas.cdt.core.Compiler.option.warning31" value="false" valueType="boolean"/>\r
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</toolChain>\r
</folderInfo>\r
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- </fileInfo>\r
<sourceEntries>\r
<entry excluding="System/GCC/src/gnu_io.c|System/GCC/src/syscalls.c" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>\r
</sourceEntries>\r
R_ATCM_WaitSet(ATCM_WAIT_1_OPT);\r
\r
/* Initialise I1, D1 Cache and MPU setting */\r
-#warning Cache not enabled.\r
-// cache_init();\r
+ cache_init();\r
\r
/* Set RZ/T1 to Low-vector (SCTLR.V = 0) */\r
set_low_vec(); \r
\r
/* FreeRTOS includes. */\r
#include "FreeRTOS.h"\r
-#include "ISR_Support.h"\r
\r
/* Renesas includes. */\r
#include "r_cg_macrodriver.h"\r
/*-----------------------------------------------------------*/\r
\r
/*\r
- * Entry point for the FreeRTOS tick interrupt. This provides the prolog code\r
- * necessary to support interrupt nesting.\r
+ * Entry point for the FreeRTOS tick interrupt. This sets the pxISRFunction\r
+ * variable to point to the RTOS tick handler, then branches to the FreeRTOS\r
+ * IRQ handler.\r
*/\r
static void FreeRTOS_Tick_Handler_Entry( void ) __attribute__((naked));\r
\r
+/*\r
+ * The FreeRTOS IRQ handler, which is implemented in the RTOS port layer.\r
+ */\r
+extern void FreeRTOS_IRQ_Handler( void );\r
+\r
+/*\r
+ * The function called by the FreeRTOS_IRQ_Handler() to call the actual\r
+ * peripheral handler.\r
+ */\r
+void vApplicationIRQHandler( void );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Variable used to hold the address of the interrupt handler the FreeRTOS IRQ\r
+ * handler will branch to.\r
+ */\r
+ISRFunction_t pxISRFunction = NULL;\r
+\r
/*-----------------------------------------------------------*/\r
\r
/*\r
/* Interrupt on compare match. */\r
CMT5.CMCR.BIT.CMIE = 1;\r
\r
-#warning Tick rate is not yet accurate.\r
/* Calculate the compare match value. */\r
ulCompareMatchValue = configCPU_CLOCK_HZ / ulPeripheralClockDivider;\r
ulCompareMatchValue /= ulCMTClockDivider;\r
}\r
/*-----------------------------------------------------------*/\r
\r
+/*\r
+ * The function called by the FreeRTOS IRQ handler, after it has managed\r
+ * interrupt entry. This function creates a local copy of pxISRFunction before\r
+ * re-enabling interrupts and actually calling the handler pointed to by\r
+ * pxISRFunction.\r
+ */\r
+void vApplicationIRQHandler( void )\r
+{\r
+ISRFunction_t pxISRToCall = pxISRFunction;\r
+\r
+ portENABLE_INTERRUPTS();\r
+\r
+ /* Call the installed ISR. */\r
+ pxISRToCall();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * The RZ/T vectors directly to a peripheral specific interrupt handler, rather\r
+ * than using the Cortex-R IRQ vector. Therefore each interrupt handler\r
+ * installed by the application must follow the example below, which saves a\r
+ * pointer to a standard C function in the pxISRFunction variable, before\r
+ * branching to the FreeRTOS IRQ handler. The FreeRTOS IRQ handler then manages\r
+ * interrupt entry (including interrupt nesting), before calling the C function\r
+ * saved in the pxISRFunction variable. NOTE: This entry point is a naked\r
+ * function - do not add C code to this function.\r
+ */\r
static void FreeRTOS_Tick_Handler_Entry( void )\r
{\r
- /* This is a naked function, and should not include any C code. */\r
- portNESTING_INTERRUPT_ENTRY();\r
- __asm volatile( " LDR r1, vTickHandlerConst \t\n"\r
- " BLX r1 \t\n"\r
- " vTickHandlerConst: .word FreeRTOS_Tick_Handler " );\r
- portNESTING_INTERRUPT_EXIT();\r
+ __asm volatile ( \\r
+ "PUSH {r0-r1} \t\n" \\r
+ "LDR r0, =pxISRFunction \t\n" \\r
+ "LDR R1, =FreeRTOS_Tick_Handler \t\n" \\r
+ "STR R1, [r0] \t\n" \\r
+ "POP {r0-r1} \t\n" \\r
+ "B FreeRTOS_IRQ_Handler "\r
+ );\r
}\r
/*-----------------------------------------------------------*/\r
\r
#include "r_cg_cmt.h"\r
#include "r_reset.h"\r
\r
-#define tmrCMT_1_CHANNEL_0_HZ ( 2000UL )\r
+#define tmrCMT_1_CHANNEL_0_HZ ( 4000UL )\r
#define tmrCMT_1_CHANNEL_1_HZ ( 2011UL )\r
\r
-/* Handlers for the two timers used. See the documentation page\r
-for this port on http://www.FreeRTOS.org for more information on writing\r
-interrupt handlers. */\r
+/*\r
+ * Handlers for the two timers used. See the documentation page\r
+ * for this port on TBD for more information on writing\r
+ * interrupt handlers.\r
+ */\r
void vCMT_1_Channel_0_ISR( void );\r
void vCMT_1_Channel_1_ISR( void );\r
\r
+/*\r
+ * Entry point for the handlers. These set the pxISRFunction variable to point\r
+ * to the C handler for each timer, then branch to the FreeRTOS IRQ handler.\r
+ */\r
+static void vCMT_1_Channel_0_ISR_Entry( void ) __attribute__((naked));\r
+static void vCMT_1_Channel_1_ISR_Entry( void ) __attribute__((naked));\r
+\r
/*-----------------------------------------------------------*/\r
\r
void vInitialiseTimerForIntQueueTest( void )\r
{\r
uint32_t ulCompareMatchValue;\r
const uint32_t ulPeripheralClockDivider = 6UL, ulCMTClockDivider = 8UL;\r
-extern void FreeRTOS_IRQ_Handler( void );\r
\r
/* Disable CMI2 and CMI3 interrupts. */\r
VIC.IEC0.LONG = ( 1UL << 23UL ) | ( 1UL << 24UL );\r
VIC.PLS0.LONG |= ( 1UL << 23UL ) | ( 1UL << 24UL );\r
\r
/* Set CMI2 and CMI3 priority levels so they nest. */\r
- VIC.PRL23.LONG = _CMT_PRIORITY_LEVEL10;\r
+ VIC.PRL23.LONG = _CMT_PRIORITY_LEVEL2;\r
VIC.PRL24.LONG = _CMT_PRIORITY_LEVEL9;\r
\r
/* Set CMI2 and CMI3 interrupt address. */\r
-#warning Int 1 timer handler addresses not set.\r
- VIC.VAD23.LONG = ( uint32_t ) NULL;\r
- VIC.VAD24.LONG = ( uint32_t ) NULL;\r
+ VIC.VAD23.LONG = ( uint32_t ) vCMT_1_Channel_0_ISR_Entry;\r
+ VIC.VAD24.LONG = ( uint32_t ) vCMT_1_Channel_1_ISR_Entry;\r
\r
/* Enable CMI2 and CMI3 interrupts in ICU. */\r
- VIC.IEN0.LONG |= ( 1UL << 23UL ) | ( 1UL << 24UL );\r
+ VIC.IEN0.LONG |= ( 1UL << 23UL ) | ( 1UL << 24UL );\r
\r
/* Start CMT1 channel 0 and 1 count. */\r
CMT.CMSTR1.BIT.STR2 = 1U;\r
\r
void vCMT_1_Channel_0_ISR( void )\r
{\r
- /* Re-enabled interrupts. */\r
- taskENABLE_INTERRUPTS();\r
+ /* Clear the interrupt. */\r
+ VIC.PIC0.LONG = ( 1UL << 23UL );\r
\r
/* Call the handler that is part of the common code - this is where the\r
non-portable code ends and the actual test is performed. */\r
\r
void vCMT_1_Channel_1_ISR( void )\r
{\r
- /* Re-enabled interrupts. */\r
- portENABLE_INTERRUPTS();\r
+ /* Clear the interrupt. */\r
+ VIC.PIC0.LONG = ( 1UL << 24UL );\r
\r
/* Call the handler that is part of the common code - this is where the\r
non-portable code ends and the actual test is performed. */\r
}\r
/*-----------------------------------------------------------*/\r
\r
+/*\r
+ * The RZ/T vectors directly to a peripheral specific interrupt handler, rather\r
+ * than using the Cortex-R IRQ vector. Therefore each interrupt handler\r
+ * installed by the application must follow the examples below, which save a\r
+ * pointer to a standard C function in the pxISRFunction variable, before\r
+ * branching to the FreeRTOS IRQ handler. The FreeRTOS IRQ handler then manages\r
+ * interrupt entry (including interrupt nesting), before calling the C function\r
+ * saved in the pxISRFunction variable. NOTE: The entry points are naked\r
+ * functions - do not add C code to these functions.\r
+ */\r
+static void vCMT_1_Channel_0_ISR_Entry( void )\r
+{\r
+ __asm volatile ( \\r
+ "PUSH {r0-r1} \t\n" \\r
+ "LDR r0, =pxISRFunction \t\n" \\r
+ "LDR r1, =vCMT_1_Channel_0_ISR \t\n" \\r
+ "STR r1, [r0] \t\n" \\r
+ "POP {r0-r1} \t\n" \\r
+ "B FreeRTOS_IRQ_Handler "\r
+ );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void vCMT_1_Channel_1_ISR_Entry( void )\r
+{\r
+ __asm volatile ( \\r
+ "PUSH {r0-r1} \t\n" \\r
+ "LDR r0, =pxISRFunction \t\n" \\r
+ "LDR r1, =vCMT_1_Channel_1_ISR \t\n" \\r
+ "STR r1, [r0] \t\n" \\r
+ "POP {r0-r1} \t\n" \\r
+ "B FreeRTOS_IRQ_Handler "\r
+ );\r
+}\r
\r
\r
\r
/* Start all the other standard demo/test tasks. They have no particular\r
functionality, but do demonstrate how to use the FreeRTOS API and test the\r
kernel port. */\r
-#warning IntQ tasks not included.\r
-// vStartInterruptQueueTasks();\r
+ vStartInterruptQueueTasks();\r
vStartDynamicPriorityTasks();\r
vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY );\r
vCreateBlockTimeTasks();\r
\r
/* Check all the demo tasks (other than the flash tasks) to ensure\r
that they are all still running, and that none have detected an error. */\r
-#warning Int q tasks not created.\r
-if( 0 )// if( xAreIntQueueTasksStillRunning() != pdTRUE )\r
+ if( xAreIntQueueTasksStillRunning() != pdTRUE )\r
{\r
ulErrorFound |= 1UL << 0UL;\r
}\r
\r
/* End user code. Do not edit comment generated here */\r
\r
-extern void r_set_exception_handler(void);\r
/***********************************************************************************************************************\r
* Function Name: R_Systeminit\r
* Description : This function initializes every macro.\r
-#if 1\r
/*\r
FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd.\r
All rights reserved\r
\r
/*-----------------------------------------------------------*/\r
\r
+/*\r
+ * The start up code does not include a routine to clear the BSS segment to 0\r
+ * (as would be normal before calling main()), so the BSS is cleared manually\r
+ * using the following function.\r
+ */\r
static void prvClearBSS( void );\r
\r
/*\r
\r
/*-----------------------------------------------------------*/\r
\r
-volatile uint32_t ultest = 0, ultest2 = 9999;\r
-\r
int main( void )\r
{\r
+ /* The start up code does not include a routine to clear the BSS segment to\r
+ 0 (as would be normal before calling main()), so the BSS is cleared manually\r
+ using the following function. */\r
prvClearBSS();\r
\r
- configASSERT( ultest == 0 );\r
- configASSERT( ultest2 == 9999 );\r
-\r
/* Configure the hardware ready to run the demo. */\r
prvSetupHardware();\r
\r
}\r
/*-----------------------------------------------------------*/\r
\r
-/* The function called by the RTOS port layer after it has managed interrupt\r
-entry. */\r
-void vApplicationIRQHandler( void )\r
-{\r
-#if 1\r
-extern void FreeRTOS_Tick_Handler( void );\r
-\r
- /* Clear the interrupt source CMI5. */\r
- VIC.PIC9.LONG = 0x00001000UL;\r
-\r
- FreeRTOS_Tick_Handler();\r
-\r
- /* Dummy write */\r
- portDISABLE_INTERRUPTS();\r
- // Done in the epilogue code VIC.HVA0.LONG = 0x00000000UL;\r
-\r
-#else\r
-typedef void (*ISRFunction_t)( void );\r
-ISRFunction_t pxISRFunction;\r
-volatile uint32_t * pulAIC_IVR = ( uint32_t * ) configINTERRUPT_VECTOR_ADDRESS;\r
-\r
- /* Obtain the address of the interrupt handler from the AIR. */\r
- pxISRFunction = ( ISRFunction_t ) *pulAIC_IVR;\r
-\r
- /* Write back to the SAMA5's interrupt controller's IVR register in case the\r
- CPU is in protect mode. If the interrupt controller is not in protect mode\r
- then this write is not necessary. */\r
- *pulAIC_IVR = ( uint32_t ) pxISRFunction;\r
-\r
- /* Ensure the write takes before re-enabling interrupts. */\r
- __DSB();\r
- __ISB();\r
- __enable_irq();\r
-\r
- /* Call the installed ISR. */\r
- pxISRFunction();\r
-#endif\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
static void prvClearBSS( void )\r
{\r
extern uint32_t __bss_start__[];\r
\r
\r
\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-#else\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-#include "FreeRTOS.h"\r
-#include "task.h"\r
-\r
-/***********************************************************************************************************************\r
-Includes\r
-***********************************************************************************************************************/\r
-#include "r_cg_macrodriver.h"\r
-#include "r_cg_cgc.h"\r
-#include "r_cg_icu.h"\r
-#include "r_cg_port.h"\r
-#include "r_cg_tpu.h"\r
-#include "r_cg_cmt.h"\r
-#include "r_cg_scifa.h"\r
-#include "r_cg_rspi.h"\r
-#include "r_cg_s12ad.h"\r
-/* Start user code for include. Do not edit comment generated here */\r
-#include "r_cg_mpc.h"\r
-#include "r_system.h"\r
-#include "r_reset.h"\r
-#include "lcd_pmod.h"\r
-#include "logo_data.h"\r
-#include "stdio.h"\r
-#include "siochar.h"\r
-/* End user code. Do not edit comment generated here */\r
-#include "r_cg_userdefine.h"\r
-\r
-/* Start user code for global. Do not edit comment generated here */\r
-\r
-#define LZ_ENABLE (1)\r
-#define LZ_DISABLE (0)\r
-\r
-/* Welcome banner - displayed on serial port at startup*/\r
-static uint8_t welcome_banner[] = "\n\n\rRSK+RZT1 \n\n\r- Tutorial - Press 'c' or SW3 for ADC Conversion\r\n\0";\r
-\r
-/* Used as a Data Transmit counter */\r
-static uint8_t uart_buffer[] = " ADC count: x. Value: xxxxx\r\n";\r
-\r
-/* Used as a Data Transmit counter */\r
-static uint8_t lcd_buffer[] = " ADC = xxxx ";\r
-\r
-/* Function prototype for displaying the 2 bit binary counter using LEDs */\r
-static void led_display_count (const uint8_t count);\r
-\r
-extern void R_Systeminit(void);\r
-void R_MAIN_UserInit(void);\r
-\r
-/* Prototypes for the standard FreeRTOS callback/hook functions implemented\r
-within this file. */\r
-void vApplicationMallocFailedHook( void );\r
-void vApplicationIdleHook( void );\r
-void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName );\r
-void vApplicationTickHook( void );\r
-\r
-\r
-/* Prototype for the IRQ handler called by the generic Cortex-A5 RTOS port\r
-layer. */\r
-void vApplicationIRQHandler( void );\r
-\r
-void main(void)\r
-{\r
-uint32_t adc_count = 0;\r
-\r
- R_Systeminit();\r
-\r
- R_MAIN_UserInit();\r
-\r
- /* SW3 interrupts */\r
- R_ICU_IRQ12_Start();\r
-\r
- /* Clear flags */\r
- g_switch_press_flg = 0;\r
- g_terminal_request = 0;\r
-\r
- /* Display the welcome banner on the serial terminal */\r
- R_SCIFA2_Serial_Send((uint8_t *)&welcome_banner, sizeof(welcome_banner));\r
- \r
- /* Data transmission and reception done in the infinite loop */\r
- while (1U)\r
- { \r
- /* Check for a valid request from the switch or serial terminal */\r
- if ((g_terminal_request) || (g_switch_press_flg & SW3_PRESS_FLG))\r
- { \r
- /* Update the binary count using LED2 and LED3 */\r
- led_display_count(adc_count);\r
-\r
- while(0u == SCIFA2.FSR.BIT.TDFE)\r
- {\r
- /* Wait for previous transmission to complete */\r
- }\r
-\r
- /* Write send data */\r
- R_SCIFA2_Serial_Send((uint8_t *)&uart_buffer, sizeof(uart_buffer));\r
-\r
- /* Clear TDFE */\r
- SCIFA2.FSR.BIT.TDFE = 0U;\r
- \r
- if (g_terminal_request)\r
- {\r
- /* Clear the request */\r
- g_terminal_request = 0U;\r
- }\r
- \r
- if (g_switch_press_flg & SW3_PRESS_FLG)\r
- {\r
- /* Clear the request */\r
- g_switch_press_flg &= ((uint8_t)~SW3_PRESS_FLG);\r
- }\r
-\r
- adc_count++;\r
- }\r
- }\r
-}\r
-/***********************************************************************************************************************\r
-* Function Name: R_MAIN_UserInit\r
-* Description : This function adds user code before implementing main function.\r
-* Arguments : None\r
-* Return Value : None\r
-***********************************************************************************************************************/\r
-void R_MAIN_UserInit(void)\r
-{\r
- /* Enable RSPI1 operations */\r
- R_RSPI1_Start();\r
- \r
- /* Configure UART channel for communication with host PC via RL78/G1C device */\r
- io_init_scifa2();\r
- \r
- /* Enable SCIFA2 operations */\r
- R_SCIFA2_Start();\r
-}\r
-\r
-static void led_display_count (const uint8_t count)\r
-{\r
- /* Set LEDs according to lower nibble of count parameter */\r
- LED2 = (uint8_t) ((count & 0x01) ? LED_ON : LED_OFF);\r
- LED3 = (uint8_t) ((count & 0x02) ? LED_ON : LED_OFF);\r
-}\r
-\r
-/*-----------------------------------------------------------*/\r
-\r
-void vApplicationMallocFailedHook( void )\r
-{\r
- /* Called if a call to pvPortMalloc() fails because there is insufficient\r
- free memory available in the FreeRTOS heap. pvPortMalloc() is called\r
- internally by FreeRTOS API functions that create tasks, queues, software\r
- timers, and semaphores. The size of the FreeRTOS heap is set by the\r
- configTOTAL_HEAP_SIZE configuration constant in FreeRTOSConfig.h. */\r
-\r
- /* Force an assert. */\r
- configASSERT( ( volatile void * ) NULL );\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName )\r
-{\r
- ( void ) pcTaskName;\r
- ( void ) pxTask;\r
-\r
- /* Run time stack overflow checking is performed if\r
- configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook\r
- function is called if a stack overflow is detected. */\r
-\r
- /* Force an assert. */\r
- configASSERT( ( volatile void * ) NULL );\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-void vApplicationIdleHook( void )\r
-{\r
-volatile size_t xFreeHeapSpace;\r
-\r
- /* This is just a trivial example of an idle hook. It is called on each\r
- cycle of the idle task. It must *NOT* attempt to block. In this case the\r
- idle task just queries the amount of FreeRTOS heap that remains. See the\r
- memory management section on the http://www.FreeRTOS.org web site for memory\r
- management options. If there is a lot of heap memory free then the\r
- configTOTAL_HEAP_SIZE value in FreeRTOSConfig.h can be reduced to free up\r
- RAM. */\r
- xFreeHeapSpace = xPortGetFreeHeapSize();\r
-\r
- /* Remove compiler warning about xFreeHeapSpace being set but never used. */\r
- ( void ) xFreeHeapSpace;\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-void vApplicationTickHook( void )\r
-{\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-void vApplicationIRQHandler( void )\r
-{\r
-}\r
-\r
-\r
-#endif\r
-\r
else if( xCallCount == xClearBitsCount )\r
{\r
/* Clear the bits again. */\r
- uxReturned = xEventGroupClearBitsFromISR( xISREventGroup, uxBitsToSet );\r
+ uxReturned = ( EventBits_t ) xEventGroupClearBitsFromISR( xISREventGroup, uxBitsToSet );\r
\r
/* Check the message was posted. */\r
if( uxReturned != pdPASS )\r
\r
/* Utility function to generate a pseudo random number. */\r
ulNextRand = ( ulMultiplier * ulNextRand ) + ulIncrement;\r
- return( ( int ) ( ulNextRand >> 16UL ) & 0x7fffUL );\r
+ return( ( ulNextRand >> 16UL ) & 0x7fffUL );\r
}\r
/*-----------------------------------------------------------*/\r
+++ /dev/null
-/*\r
- FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd.\r
- All rights reserved\r
-\r
-\r
- ***************************************************************************\r
- * *\r
- * FreeRTOS tutorial books are available in pdf and paperback. *\r
- * Complete, revised, and edited pdf reference manuals are also *\r
- * available. *\r
- * *\r
- * Purchasing FreeRTOS documentation will not only help you, by *\r
- * ensuring you get running as quickly as possible and with an *\r
- * in-depth knowledge of how to use FreeRTOS, it will also help *\r
- * the FreeRTOS project to continue with its mission of providing *\r
- * professional grade, cross platform, de facto standard solutions *\r
- * for microcontrollers - completely free of charge! *\r
- * *\r
- * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
- * *\r
- * Thank you for using FreeRTOS, and thank you for your support! *\r
- * *\r
- ***************************************************************************\r
-\r
-\r
- This file is part of the FreeRTOS distribution.\r
-\r
- FreeRTOS is free software; you can redistribute it and/or modify it under\r
- the terms of the GNU General Public License (version 2) as published by the\r
- Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
- >>>NOTE<<< The modification to the GPL is included to allow you to\r
- distribute a combined work that includes FreeRTOS without being obliged to\r
- provide the source code for proprietary components outside of the FreeRTOS\r
- kernel. FreeRTOS is distributed in the hope that it will be useful, but\r
- WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
- more details. You should have received a copy of the GNU General Public\r
- License and the FreeRTOS license exception along with FreeRTOS; if not it\r
- can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
- by writing to Richard Barry, contact details for whom are available on the\r
- FreeRTOS WEB site.\r
-\r
- 1 tab == 4 spaces!\r
-\r
- http://www.FreeRTOS.org - Documentation, latest information, license and\r
- contact details.\r
-\r
- http://www.SafeRTOS.com - A version that is certified for use in safety\r
- critical systems.\r
-\r
- http://www.OpenRTOS.com - Commercial support, development, porting,\r
- licensing and training services.\r
-*/\r
-\r
-#define portNESTING_INTERRUPT_ENTRY() \\r
- __asm volatile ( \\r
- ".extern ulPortYieldRequired \t\n" \\r
- ".extern ulPortInterruptNesting \t\n" \\r
- ".extern FreeRTOS_SVC_Handler \t\n" \\r
- /* Return to the interrupted instruction. */ \\r
- "SUB LR, LR, #4 \t\n" \\r
- \\r
- /* Push the return address and SPSR. */ \\r
- "PUSH {LR} \t\n" \\r
- "MRS LR, SPSR \t\n" \\r
- "PUSH {LR} \t\n" \\r
- \\r
- /* Change to supervisor mode to allow reentry. */ \\r
- "CPS #0x13 \t\n" \\r
- \\r
- /* Push used registers. */ \\r
- "PUSH {r0-r4, r12} \t\n" \\r
- \\r
- /* Increment nesting count. r3 holds the address */ \\r
- /* of ulPortInterruptNesting future use. */ \\r
- "LDR r2, =ulPortInterruptNestingConst \t\n" \\r
- "LDR r3, [r2] \t\n" \\r
- \\r
- "LDR r1, [r3] \t\n" \\r
- "ADD r4, r1, #1 \t\n" \\r
- "STR r4, [r3] \t\n" \\r
- \\r
- /* Ensure bit 2 of the stack pointer is clear. */ \\r
- /* r2 holds the bit 2 value for future use. */ \\r
- "MOV r2, sp \t\n" \\r
- "AND r2, r2, #4 \t\n" \\r
- "SUB sp, sp, r2 \t\n" \\r
- \\r
- /* Call the interrupt handler. */ \\r
- "PUSH {r0-r3, LR} " \\r
- );\r
-\r
-#warning Why is ulPortYieldRequired accessed differently to the other variables?\r
-#warning R0 seems to being pushed even though it is not used.\r
-#warning Writing to the EOI register uses R4 on consecutive lines.\r
-\r
-\r
-#define portNESTING_INTERRUPT_EXIT() \\r
- __asm volatile ( \\r
- "POP {r0-r3, LR} \t\n" \\r
- "ADD sp, sp, r2 \t\n" \\r
- " \t\n" \\r
- "CPSID i \t\n" \\r
- "DSB \t\n" \\r
- "ISB \t\n" \\r
- " \t\n" \\r
- /* Write to the EOI register. */ \\r
- "LDR r4, ulICCEOIRConst \t\n" \\r
- "LDR r4, [r4] \t\n" \\r
- "STR r0, [r4] \t\n" \\r
- \\r
- /* Restore the old nesting count. */ \\r
- "STR r1, [r3] \t\n" \\r
- \\r
- /* A context switch is never performed if the */ \\r
- /* nesting count is not 0. */ \\r
- "CMP r1, #0 \t\n" \\r
- "BNE 1f \t\n" \\r
- \\r
- /* Did the interrupt request a context switch? */ \\r
- /* r1 holds the address of ulPortYieldRequired */ \\r
- /* and r0 the value of ulPortYieldRequired for */ \\r
- /* future use. */ \\r
- "LDR r1, =ulPortYieldRequired \t\n" \\r
- "LDR r0, [r1] \t\n" \\r
- "CMP r0, #0 \t\n" \\r
- "BNE 2f \t\n" \\r
- \\r
- "1: \t\n" \\r
- /* No context switch. Restore used registers, */ \\r
- /* LR_irq and SPSR before returning. 0x12 is IRQ */ \\r
- /* mode. */ \\r
- "POP {r0-r4, r12} \t\n" \\r
- "CPS #0x12 \t\n" \\r
- "POP {LR} \t\n" \\r
- "MSR SPSR_cxsf, LR \t\n" \\r
- "POP {LR} \t\n" \\r
- "MOVS PC, LR \t\n" \\r
- \\r
- "2: \t\n" \\r
- /* A context switch is to be performed. */ \\r
- /* Clear the context switch pending flag. */ \\r
- "MOV r0, #0 \t\n" \\r
- "STR r0, [r1] \t\n" \\r
- \\r
- /* Restore used registers, LR-irq and */ \\r
- /* SPSR before saving the context to the */ \\r
- /* task stack. 0x12 is IRQ mode. */ \\r
- "POP {r0-r4, r12} \t\n" \\r
- "CPS #0x12 \t\n" \\r
- "POP {LR} \t\n" \\r
- "MSR SPSR_cxsf, LR \t\n" \\r
- "POP {LR} \t\n" \\r
- "b FreeRTOS_SVC_Handler \t\n" \\r
- "ISB \t\n" \\r
- "ulICCEOIRConst: .word ulICCEOIR \t\n" \\r
- " ulPortInterruptNestingConst: .word ulPortInterruptNesting " \\r
- );\r
-\r
.global vPortRestoreTaskContext\r
\r
\r
-\r
-\r
.macro portSAVE_CONTEXT\r
\r
/* Save the LR and SPSR onto the system mode stack before switching to\r
PUSH {lr}\r
\r
/* Change to supervisor mode to allow reentry. */\r
+ CPS #0x13\r
\r
/* Push used registers. */\r
- PUSH {r0-r4, r12}\r
+ PUSH {r0-r3, r12}\r
\r
/* Increment nesting count. r3 holds the address of ulPortInterruptNesting\r
for future use. r1 holds the original ulPortInterruptNesting value for\r
future use. */\r
LDR r3, ulPortInterruptNestingConst\r
LDR r1, [r3]\r
- ADD r4, r1, #1\r
- STR r4, [r3]\r
+ ADD r0, r1, #1\r
+ STR r0, [r3]\r
\r
/* Ensure bit 2 of the stack pointer is clear. r2 holds the bit 2 value for\r
future use. */\r
- MOV r2, sp\r
- AND r2, r2, #4\r
+ MOV r0, sp\r
+ AND r2, r0, #4\r
SUB sp, sp, r2\r
\r
/* Call the interrupt handler. */\r
ISB\r
\r
/* Write to the EOI register. */\r
- LDR r4, ulICCEOIRConst\r
- LDR r4, [r4]\r
- STR r0, [r4]\r
+ LDR r0, ulICCEOIRConst\r
+ LDR r2, [r0]\r
+ STR r0, [r2]\r
\r
/* Restore the old nesting count. */\r
STR r1, [r3]\r
/* Did the interrupt request a context switch? r1 holds the address of\r
ulPortYieldRequired and r0 the value of ulPortYieldRequired for future\r
use. */\r
- LDR r1, =ulPortYieldRequired\r
+ LDR r1, ulPortYieldRequiredConst\r
LDR r0, [r1]\r
CMP r0, #0\r
BNE switch_before_exit\r
exit_without_switch:\r
/* No context switch. Restore used registers, LR_irq and SPSR before\r
returning. */\r
- POP {r0-r4, r12}\r
+ POP {r0-r3, r12}\r
CPS #IRQ_MODE\r
POP {LR}\r
MSR SPSR_cxsf, LR\r
\r
/* Restore used registers, LR-irq and SPSR before saving the context\r
to the task stack. */\r
- POP {r0-r4, r12}\r
+ POP {r0-r3, r12}\r
CPS #IRQ_MODE\r
POP {LR}\r
MSR SPSR_cxsf, LR\r
vTaskSwitchContextConst: .word vTaskSwitchContext\r
vApplicationIRQHandlerConst: .word vApplicationIRQHandler\r
ulPortInterruptNestingConst: .word ulPortInterruptNesting\r
+ulPortYieldRequiredConst: .word ulPortYieldRequired\r
\r
.end\r
\r
/* Called at the end of an ISR that can cause a context switch. */\r
#define portEND_SWITCHING_ISR( xSwitchRequired )\\r
{ \\r
-extern uint32_t ulPortYieldRequired; \\r
+extern volatile uint32_t ulPortYieldRequired; \\r
\\r
if( xSwitchRequired != pdFALSE ) \\r
{ \\r
projects / freertos / commitdiff