--- /dev/null
+# The IMX35PDK eval board has a single IMX35 chip
+source [find target/imx35.cfg]
+$_TARGETNAME configure -event reset-init { imx35pdk_init }
+
+memwrite burst disable
+#arm11 no_increment enable
+
+
+global TARGETNAME
+set TARGETNAME $_TARGETNAME
+
+# rewrite commands of the form below to arm11 mcr...
+# Data.Set c15:0x042f %long 0x40000015
+proc setc15 {regs value} {
+ global TARGETNAME
+
+ echo [format "set p15 0x%04x, 0x%08x" $regs $value]
+
+ arm11 mcr $TARGETNAME 15 [expr ($regs>>12)&0x7] [expr ($regs>>0)&0xf] [expr ($regs>>4)&0xf] [expr ($regs>>8)&0x7] $value
+}
+
+proc imx35pdk_init { } {
+
+
+ echo "Target Setup: initialize DRAM controller and peripherals"
+
+# Data.Set c15:0x01 %long 0x00050078
+ setc15 0x01 0x00050078
+
+ echo "configuring CP15 for enabling the peripheral bus"
+# Data.Set c15:0x042f %long 0x40000015
+ setc15 0x042f 0x40000015
+
+ mww 0x43f00040 0x00000000
+ mww 0x43f00044 0x00000000
+ mww 0x43f00048 0x00000000
+ mww 0x43f0004C 0x00000000
+ mww 0x43f00050 0x00000000
+ mww 0x43f00000 0x77777777
+ mww 0x43f00004 0x77777777
+ mww 0x53f00040 0x00000000
+ mww 0x53f00044 0x00000000
+ mww 0x53f00048 0x00000000
+ mww 0x53f0004C 0x00000000
+ mww 0x53f00050 0x00000000
+ mww 0x53f00000 0x77777777
+ mww 0x53f00004 0x77777777
+
+ # clock setup
+ mww 0x53F80004 0x00821000 # first need to set IPU_HND_BYP
+ mww 0x53F80004 0x00821000 #arm clock is 399Mhz and ahb clock is 133Mhz.
+
+ #=================================================
+ # WEIM config
+ #=================================================
+ # CS0U
+ mww 0xB8002000 0x0000CC03
+ # CS0L
+ mww 0xB8002004 0xA0330D01
+ # CS0A
+ mww 0xB8002008 0x00220800
+ # CS5U
+ mww 0xB8002050 0x0000dcf6
+ # CS5L
+ mww 0xB8002054 0x444a4541
+ # CS5A
+ mww 0xB8002058 0x44443302
+
+ # IO SW PAD Control registers - setting of 0x0002 is high drive, mDDR
+ mww 0x43FAC368 0x00000006
+ mww 0x43FAC36C 0x00000006
+ mww 0x43FAC370 0x00000006
+ mww 0x43FAC374 0x00000006
+ mww 0x43FAC378 0x00000006
+ mww 0x43FAC37C 0x00000006
+ mww 0x43FAC380 0x00000006
+ mww 0x43FAC384 0x00000006
+ mww 0x43FAC388 0x00000006
+ mww 0x43FAC38C 0x00000006
+ mww 0x43FAC390 0x00000006
+ mww 0x43FAC394 0x00000006
+ mww 0x43FAC398 0x00000006
+ mww 0x43FAC39C 0x00000006
+ mww 0x43FAC3A0 0x00000006
+ mww 0x43FAC3A4 0x00000006
+ mww 0x43FAC3A8 0x00000006
+ mww 0x43FAC3AC 0x00000006
+ mww 0x43FAC3B0 0x00000006
+ mww 0x43FAC3B4 0x00000006
+ mww 0x43FAC3B8 0x00000006
+ mww 0x43FAC3BC 0x00000006
+ mww 0x43FAC3C0 0x00000006
+ mww 0x43FAC3C4 0x00000006
+ mww 0x43FAC3C8 0x00000006
+ mww 0x43FAC3CC 0x00000006
+ mww 0x43FAC3D0 0x00000006
+ mww 0x43FAC3D4 0x00000006
+ mww 0x43FAC3D8 0x00000006
+
+ # DDR data bus SD 0 through 31
+ mww 0x43FAC3DC 0x00000082
+ mww 0x43FAC3E0 0x00000082
+ mww 0x43FAC3E4 0x00000082
+ mww 0x43FAC3E8 0x00000082
+ mww 0x43FAC3EC 0x00000082
+ mww 0x43FAC3F0 0x00000082
+ mww 0x43FAC3F4 0x00000082
+ mww 0x43FAC3F8 0x00000082
+ mww 0x43FAC3FC 0x00000082
+ mww 0x43FAC400 0x00000082
+ mww 0x43FAC404 0x00000082
+ mww 0x43FAC408 0x00000082
+ mww 0x43FAC40C 0x00000082
+ mww 0x43FAC410 0x00000082
+ mww 0x43FAC414 0x00000082
+ mww 0x43FAC418 0x00000082
+ mww 0x43FAC41c 0x00000082
+ mww 0x43FAC420 0x00000082
+ mww 0x43FAC424 0x00000082
+ mww 0x43FAC428 0x00000082
+ mww 0x43FAC42c 0x00000082
+ mww 0x43FAC430 0x00000082
+ mww 0x43FAC434 0x00000082
+ mww 0x43FAC438 0x00000082
+ mww 0x43FAC43c 0x00000082
+ mww 0x43FAC440 0x00000082
+ mww 0x43FAC444 0x00000082
+ mww 0x43FAC448 0x00000082
+ mww 0x43FAC44c 0x00000082
+ mww 0x43FAC450 0x00000082
+ mww 0x43FAC454 0x00000082
+ mww 0x43FAC458 0x00000082
+
+ # DQM setup
+ mww 0x43FAC45c 0x00000082
+ mww 0x43FAC460 0x00000082
+ mww 0x43FAC464 0x00000082
+ mww 0x43FAC468 0x00000082
+
+ mww 0x43FAC46c 0x00000006
+ mww 0x43FAC470 0x00000006
+ mww 0x43FAC474 0x00000006
+ mww 0x43FAC478 0x00000006
+ mww 0x43FAC47c 0x00000006
+ mww 0x43FAC480 0x00000006 # CSD0
+ mww 0x43FAC484 0x00000006 # CSD1
+ mww 0x43FAC488 0x00000006
+ mww 0x43FAC48c 0x00000006
+ mww 0x43FAC490 0x00000006
+ mww 0x43FAC494 0x00000006
+ mww 0x43FAC498 0x00000006
+ mww 0x43FAC49c 0x00000006
+ mww 0x43FAC4A0 0x00000006
+ mww 0x43FAC4A4 0x00000006 # RAS
+ mww 0x43FAC4A8 0x00000006 # CAS
+ mww 0x43FAC4Ac 0x00000006 # SDWE
+ mww 0x43FAC4B0 0x00000006 # SDCKE0
+ mww 0x43FAC4B4 0x00000006 # SDCKE1
+ mww 0x43FAC4B8 0x00000002 # SDCLK
+
+ # SDQS0 through SDQS3
+ mww 0x43FAC4Bc 0x00000082
+ mww 0x43FAC4C0 0x00000082
+ mww 0x43FAC4C4 0x00000082
+ mww 0x43FAC4C8 0x00000082
+
+
+ # *==================================================
+ # Initialization script for 32 bit DDR2 on RINGO 3DS
+ # *==================================================
+
+ #--------------------------------------------
+ # Init CCM
+ #--------------------------------------------
+ mww 0x53F80028 0x7D000028
+
+ #--------------------------------------------
+ # Init IOMUX for JTAG
+ #--------------------------------------------
+ mww 0x43FAC5EC 0x000000C3
+ mww 0x43FAC5F0 0x000000C3
+ mww 0x43FAC5F4 0x000000F3
+ mww 0x43FAC5F8 0x000000F3
+ mww 0x43FAC5FC 0x000000F3
+ mww 0x43FAC600 0x000000F3
+ mww 0x43FAC604 0x000000F3
+
+
+ # ESD_MISC : enable DDR2
+ mww 0xB8001010 0x00000304
+
+ #--------------------------------------------
+ # Init 32-bit DDR2 memeory on CSD0
+ # COL=10-bit, ROW=13-bit, BA[1:0]=Addr[26:25]
+ #--------------------------------------------
+
+ # ESD_ESDCFG0 : set timing paramters
+ mww 0xB8001004 0x007ffC2f
+
+ # ESD_ESDCTL0 : select Prechare-All mode
+ mww 0xB8001000 0x92220000
+ # DDR2 : Prechare-All
+ mww 0x80000400 0x12345678
+
+ # ESD_ESDCTL0 : select Load-Mode-Register mode
+ mww 0xB8001000 0xB2220000
+ # DDR2 : Load reg EMR2
+ mwb 0x84000000 0xda
+ # DDR2 : Load reg EMR3
+ mwb 0x86000000 0xda
+ # DDR2 : Load reg EMR1 -- enable DLL
+ mwb 0x82000400 0xda
+ # DDR2 : Load reg MR -- reset DLL
+ mwb 0x80000333 0xda
+
+ # ESD_ESDCTL0 : select Prechare-All mode
+ mww 0xB8001000 0x92220000
+ # DDR2 : Prechare-All
+ mwb 0x80000400 0x12345678
+
+ # ESD_ESDCTL0 : select Manual-Refresh mode
+ mww 0xB8001000 0xA2220000
+ # DDR2 : Manual-Refresh 2 times
+ mww 0x80000000 0x87654321
+ mww 0x80000000 0x87654321
+
+ # ESD_ESDCTL0 : select Load-Mode-Register mode
+ mww 0xB8001000 0xB2220000
+ # DDR2 : Load reg MR -- CL=3, BL=8, end DLL reset
+ mwb 0x80000233 0xda
+ # DDR2 : Load reg EMR1 -- OCD default
+ mwb 0x82000780 0xda
+ # DDR2 : Load reg EMR1 -- OCD exit
+ mwb 0x82000400 0xda # ODT disabled
+
+ # ESD_ESDCTL0 : select normal-operation mode
+ # DSIZ=32-bit, BL=8, COL=10-bit, ROW=13-bit
+ # disable PWT & PRCT
+ # disable Auto-Refresh
+ mww 0xB8001000 0x82220080
+
+ ## ESD_ESDCTL0 : enable Auto-Refresh
+ mww 0xB8001000 0x82228080
+ ## ESD_ESDCTL1 : enable Auto-Refresh
+ mww 0xB8001008 0x00002000
+
+
+ #***********************************************
+ # Adjust the ESDCDLY5 register
+ #***********************************************
+ # Vary DQS_ABS_OFFSET5 for writes
+ mww 0xB8001020 0x00F48000 # this is the default value
+ mww 0xB8001024 0x00F48000 # this is the default value
+ mww 0xB8001028 0x00F48000 # this is the default value
+ mww 0xB800102c 0x00F48000 # this is the default value
+
+
+ #Then you can make force measure with the dedicated bit (Bit 7 at ESDMISC)
+ mww 0xB8001010 0x00000384
+ # wait a while
+ sleep 1000
+ # now clear the force measurement bit
+ mww 0xB8001010 0x00000304
+
+ # dummy write to DDR memory to set DQS low
+ mww 0x80000000 0x00000000
+
+ mww 0x30000100 0x0
+ mww 0x30000104 0x31024
+
+
+}
projects / openocd / commitdiff