+++ /dev/null
-/**************************************************************************//**\r
- * @file core_cm3.h\r
- * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File\r
- * @version V1.30\r
- * @date 30. October 2009\r
- *\r
- * @note\r
- * Copyright (C) 2009 ARM Limited. All rights reserved.\r
- *\r
- * @par\r
- * ARM Limited (ARM) is supplying this software for use with Cortex-M \r
- * processor based microcontrollers. This file can be freely distributed \r
- * within development tools that are supporting such ARM based processors. \r
- *\r
- * @par\r
- * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
- * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
- *\r
- ******************************************************************************/\r
-\r
-#ifndef __CM3_CORE_H__\r
-#define __CM3_CORE_H__\r
-\r
-/** @addtogroup CMSIS_CM3_core_LintCinfiguration CMSIS CM3 Core Lint Configuration\r
- *\r
- * List of Lint messages which will be suppressed and not shown:\r
- * - Error 10: \n\r
- * register uint32_t __regBasePri __asm("basepri"); \n\r
- * Error 10: Expecting ';'\r
- * .\r
- * - Error 530: \n\r
- * return(__regBasePri); \n\r
- * Warning 530: Symbol '__regBasePri' (line 264) not initialized\r
- * . \r
- * - Error 550: \n\r
- * __regBasePri = (basePri & 0x1ff); \n\r
- * Warning 550: Symbol '__regBasePri' (line 271) not accessed\r
- * .\r
- * - Error 754: \n\r
- * uint32_t RESERVED0[24]; \n\r
- * Info 754: local structure member '<some, not used in the HAL>' (line 109, file ./cm3_core.h) not referenced\r
- * .\r
- * - Error 750: \n\r
- * #define __CM3_CORE_H__ \n\r
- * Info 750: local macro '__CM3_CORE_H__' (line 43, file./cm3_core.h) not referenced\r
- * .\r
- * - Error 528: \n\r
- * static __INLINE void NVIC_DisableIRQ(uint32_t IRQn) \n\r
- * Warning 528: Symbol 'NVIC_DisableIRQ(unsigned int)' (line 419, file ./cm3_core.h) not referenced\r
- * .\r
- * - Error 751: \n\r
- * } InterruptType_Type; \n\r
- * Info 751: local typedef 'InterruptType_Type' (line 170, file ./cm3_core.h) not referenced\r
- * .\r
- * Note: To re-enable a Message, insert a space before 'lint' *\r
- *\r
- */\r
-\r
-/*lint -save */\r
-/*lint -e10 */\r
-/*lint -e530 */\r
-/*lint -e550 */\r
-/*lint -e754 */\r
-/*lint -e750 */\r
-/*lint -e528 */\r
-/*lint -e751 */\r
-\r
-\r
-/** @addtogroup CMSIS_CM3_core_definitions CM3 Core Definitions\r
- This file defines all structures and symbols for CMSIS core:\r
- - CMSIS version number\r
- - Cortex-M core registers and bitfields\r
- - Cortex-M core peripheral base address\r
- @{\r
- */\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif \r
-\r
-#define __CM3_CMSIS_VERSION_MAIN (0x01) /*!< [31:16] CMSIS HAL main version */\r
-#define __CM3_CMSIS_VERSION_SUB (0x30) /*!< [15:0] CMSIS HAL sub version */\r
-#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */\r
-\r
-#define __CORTEX_M (0x03) /*!< Cortex core */\r
-\r
-#include <stdint.h> /* Include standard types */\r
-\r
-#if defined (__ICCARM__)\r
- #include <intrinsics.h> /* IAR Intrinsics */\r
-#endif\r
-\r
-\r
-#ifndef __NVIC_PRIO_BITS\r
- #define __NVIC_PRIO_BITS 4 /*!< standard definition for NVIC Priority Bits */\r
-#endif\r
-\r
-\r
-\r
-\r
-/**\r
- * IO definitions\r
- *\r
- * define access restrictions to peripheral registers\r
- */\r
-\r
-#ifdef __cplusplus\r
- #define __I volatile /*!< defines 'read only' permissions */\r
-#else\r
- #define __I volatile const /*!< defines 'read only' permissions */\r
-#endif\r
-#define __O volatile /*!< defines 'write only' permissions */\r
-#define __IO volatile /*!< defines 'read / write' permissions */\r
-\r
-\r
-\r
-/*******************************************************************************\r
- * Register Abstraction\r
- ******************************************************************************/\r
-/** @addtogroup CMSIS_CM3_core_register CMSIS CM3 Core Register\r
- @{\r
-*/\r
-\r
-\r
-/** @addtogroup CMSIS_CM3_NVIC CMSIS CM3 NVIC\r
- memory mapped structure for Nested Vectored Interrupt Controller (NVIC)\r
- @{\r
- */\r
-typedef struct\r
-{\r
- __IO uint32_t ISER[8]; /*!< Offset: 0x000 Interrupt Set Enable Register */\r
- uint32_t RESERVED0[24]; \r
- __IO uint32_t ICER[8]; /*!< Offset: 0x080 Interrupt Clear Enable Register */\r
- uint32_t RSERVED1[24]; \r
- __IO uint32_t ISPR[8]; /*!< Offset: 0x100 Interrupt Set Pending Register */\r
- uint32_t RESERVED2[24]; \r
- __IO uint32_t ICPR[8]; /*!< Offset: 0x180 Interrupt Clear Pending Register */\r
- uint32_t RESERVED3[24]; \r
- __IO uint32_t IABR[8]; /*!< Offset: 0x200 Interrupt Active bit Register */\r
- uint32_t RESERVED4[56]; \r
- __IO uint8_t IP[240]; /*!< Offset: 0x300 Interrupt Priority Register (8Bit wide) */\r
- uint32_t RESERVED5[644]; \r
- __O uint32_t STIR; /*!< Offset: 0xE00 Software Trigger Interrupt Register */\r
-} NVIC_Type; \r
-/*@}*/ /* end of group CMSIS_CM3_NVIC */\r
-\r
-\r
-/** @addtogroup CMSIS_CM3_SCB CMSIS CM3 SCB\r
- memory mapped structure for System Control Block (SCB)\r
- @{\r
- */\r
-typedef struct\r
-{\r
- __I uint32_t CPUID; /*!< Offset: 0x00 CPU ID Base Register */\r
- __IO uint32_t ICSR; /*!< Offset: 0x04 Interrupt Control State Register */\r
- __IO uint32_t VTOR; /*!< Offset: 0x08 Vector Table Offset Register */\r
- __IO uint32_t AIRCR; /*!< Offset: 0x0C Application Interrupt / Reset Control Register */\r
- __IO uint32_t SCR; /*!< Offset: 0x10 System Control Register */\r
- __IO uint32_t CCR; /*!< Offset: 0x14 Configuration Control Register */\r
- __IO uint8_t SHP[12]; /*!< Offset: 0x18 System Handlers Priority Registers (4-7, 8-11, 12-15) */\r
- __IO uint32_t SHCSR; /*!< Offset: 0x24 System Handler Control and State Register */\r
- __IO uint32_t CFSR; /*!< Offset: 0x28 Configurable Fault Status Register */\r
- __IO uint32_t HFSR; /*!< Offset: 0x2C Hard Fault Status Register */\r
- __IO uint32_t DFSR; /*!< Offset: 0x30 Debug Fault Status Register */\r
- __IO uint32_t MMFAR; /*!< Offset: 0x34 Mem Manage Address Register */\r
- __IO uint32_t BFAR; /*!< Offset: 0x38 Bus Fault Address Register */\r
- __IO uint32_t AFSR; /*!< Offset: 0x3C Auxiliary Fault Status Register */\r
- __I uint32_t PFR[2]; /*!< Offset: 0x40 Processor Feature Register */\r
- __I uint32_t DFR; /*!< Offset: 0x48 Debug Feature Register */\r
- __I uint32_t ADR; /*!< Offset: 0x4C Auxiliary Feature Register */\r
- __I uint32_t MMFR[4]; /*!< Offset: 0x50 Memory Model Feature Register */\r
- __I uint32_t ISAR[5]; /*!< Offset: 0x60 ISA Feature Register */\r
-} SCB_Type; \r
-\r
-/* SCB CPUID Register Definitions */\r
-#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */\r
-#define SCB_CPUID_IMPLEMENTER_Msk (0xFFul << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */\r
-\r
-#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */\r
-#define SCB_CPUID_VARIANT_Msk (0xFul << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */\r
-\r
-#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */\r
-#define SCB_CPUID_PARTNO_Msk (0xFFFul << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */\r
-\r
-#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */\r
-#define SCB_CPUID_REVISION_Msk (0xFul << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */\r
-\r
-/* SCB Interrupt Control State Register Definitions */\r
-#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */\r
-#define SCB_ICSR_NMIPENDSET_Msk (1ul << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */\r
-\r
-#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */\r
-#define SCB_ICSR_PENDSVSET_Msk (1ul << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */\r
-\r
-#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */\r
-#define SCB_ICSR_PENDSVCLR_Msk (1ul << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */\r
-\r
-#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */\r
-#define SCB_ICSR_PENDSTSET_Msk (1ul << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */\r
-\r
-#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */\r
-#define SCB_ICSR_PENDSTCLR_Msk (1ul << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */\r
-\r
-#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */\r
-#define SCB_ICSR_ISRPREEMPT_Msk (1ul << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */\r
-\r
-#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */\r
-#define SCB_ICSR_ISRPENDING_Msk (1ul << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */\r
-\r
-#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */\r
-#define SCB_ICSR_VECTPENDING_Msk (0x1FFul << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */\r
-\r
-#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */\r
-#define SCB_ICSR_RETTOBASE_Msk (1ul << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */\r
-\r
-#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */\r
-#define SCB_ICSR_VECTACTIVE_Msk (0x1FFul << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */\r
-\r
-/* SCB Interrupt Control State Register Definitions */\r
-#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */\r
-#define SCB_VTOR_TBLBASE_Msk (0x1FFul << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */\r
-\r
-#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */\r
-#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFul << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */\r
-\r
-/* SCB Application Interrupt and Reset Control Register Definitions */\r
-#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */\r
-#define SCB_AIRCR_VECTKEY_Msk (0xFFFFul << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */\r
-\r
-#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */\r
-#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFul << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */\r
-\r
-#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */\r
-#define SCB_AIRCR_ENDIANESS_Msk (1ul << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */\r
-\r
-#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */\r
-#define SCB_AIRCR_PRIGROUP_Msk (7ul << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */\r
-\r
-#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */\r
-#define SCB_AIRCR_SYSRESETREQ_Msk (1ul << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */\r
-\r
-#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */\r
-#define SCB_AIRCR_VECTCLRACTIVE_Msk (1ul << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r
-\r
-#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */\r
-#define SCB_AIRCR_VECTRESET_Msk (1ul << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */\r
-\r
-/* SCB System Control Register Definitions */\r
-#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */\r
-#define SCB_SCR_SEVONPEND_Msk (1ul << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */\r
-\r
-#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */\r
-#define SCB_SCR_SLEEPDEEP_Msk (1ul << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */\r
-\r
-#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */\r
-#define SCB_SCR_SLEEPONEXIT_Msk (1ul << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */\r
-\r
-/* SCB Configuration Control Register Definitions */\r
-#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */\r
-#define SCB_CCR_STKALIGN_Msk (1ul << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */\r
-\r
-#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */\r
-#define SCB_CCR_BFHFNMIGN_Msk (1ul << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */\r
-\r
-#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */\r
-#define SCB_CCR_DIV_0_TRP_Msk (1ul << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */\r
-\r
-#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */\r
-#define SCB_CCR_UNALIGN_TRP_Msk (1ul << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */\r
-\r
-#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */\r
-#define SCB_CCR_USERSETMPEND_Msk (1ul << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */\r
-\r
-#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */\r
-#define SCB_CCR_NONBASETHRDENA_Msk (1ul << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */\r
-\r
-/* SCB System Handler Control and State Register Definitions */\r
-#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */\r
-#define SCB_SHCSR_USGFAULTENA_Msk (1ul << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */\r
-\r
-#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */\r
-#define SCB_SHCSR_BUSFAULTENA_Msk (1ul << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */\r
-\r
-#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */\r
-#define SCB_SHCSR_MEMFAULTENA_Msk (1ul << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */\r
-\r
-#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */\r
-#define SCB_SHCSR_SVCALLPENDED_Msk (1ul << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */\r
-\r
-#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */\r
-#define SCB_SHCSR_BUSFAULTPENDED_Msk (1ul << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */\r
-\r
-#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */\r
-#define SCB_SHCSR_MEMFAULTPENDED_Msk (1ul << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */\r
-\r
-#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */\r
-#define SCB_SHCSR_USGFAULTPENDED_Msk (1ul << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */\r
-\r
-#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */\r
-#define SCB_SHCSR_SYSTICKACT_Msk (1ul << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */\r
-\r
-#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */\r
-#define SCB_SHCSR_PENDSVACT_Msk (1ul << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */\r
-\r
-#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */\r
-#define SCB_SHCSR_MONITORACT_Msk (1ul << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */\r
-\r
-#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */\r
-#define SCB_SHCSR_SVCALLACT_Msk (1ul << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */\r
- \r
-#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */\r
-#define SCB_SHCSR_USGFAULTACT_Msk (1ul << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */\r
-\r
-#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */\r
-#define SCB_SHCSR_BUSFAULTACT_Msk (1ul << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */\r
-\r
-#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */\r
-#define SCB_SHCSR_MEMFAULTACT_Msk (1ul << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */\r
-\r
-/* SCB Configurable Fault Status Registers Definitions */\r
-#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */\r
-#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFul << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */\r
-\r
-#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */\r
-#define SCB_CFSR_BUSFAULTSR_Msk (0xFFul << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */\r
-\r
-#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */\r
-#define SCB_CFSR_MEMFAULTSR_Msk (0xFFul << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */\r
-\r
-/* SCB Hard Fault Status Registers Definitions */\r
-#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */\r
-#define SCB_HFSR_DEBUGEVT_Msk (1ul << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */\r
-\r
-#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */\r
-#define SCB_HFSR_FORCED_Msk (1ul << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */\r
-\r
-#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */\r
-#define SCB_HFSR_VECTTBL_Msk (1ul << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */\r
-\r
-/* SCB Debug Fault Status Register Definitions */\r
-#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */\r
-#define SCB_DFSR_EXTERNAL_Msk (1ul << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */\r
-\r
-#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */\r
-#define SCB_DFSR_VCATCH_Msk (1ul << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */\r
-\r
-#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */\r
-#define SCB_DFSR_DWTTRAP_Msk (1ul << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */\r
-\r
-#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */\r
-#define SCB_DFSR_BKPT_Msk (1ul << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */\r
-\r
-#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */\r
-#define SCB_DFSR_HALTED_Msk (1ul << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */\r
-/*@}*/ /* end of group CMSIS_CM3_SCB */\r
-\r
-\r
-/** @addtogroup CMSIS_CM3_SysTick CMSIS CM3 SysTick\r
- memory mapped structure for SysTick\r
- @{\r
- */\r
-typedef struct\r
-{\r
- __IO uint32_t CTRL; /*!< Offset: 0x00 SysTick Control and Status Register */\r
- __IO uint32_t LOAD; /*!< Offset: 0x04 SysTick Reload Value Register */\r
- __IO uint32_t VAL; /*!< Offset: 0x08 SysTick Current Value Register */\r
- __I uint32_t CALIB; /*!< Offset: 0x0C SysTick Calibration Register */\r
-} SysTick_Type;\r
-\r
-/* SysTick Control / Status Register Definitions */\r
-#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */\r
-#define SysTick_CTRL_COUNTFLAG_Msk (1ul << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */\r
-\r
-#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */\r
-#define SysTick_CTRL_CLKSOURCE_Msk (1ul << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */\r
-\r
-#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */\r
-#define SysTick_CTRL_TICKINT_Msk (1ul << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */\r
-\r
-#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */\r
-#define SysTick_CTRL_ENABLE_Msk (1ul << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */\r
-\r
-/* SysTick Reload Register Definitions */\r
-#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */\r
-#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFul << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */\r
-\r
-/* SysTick Current Register Definitions */\r
-#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */\r
-#define SysTick_VAL_CURRENT_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */\r
-\r
-/* SysTick Calibration Register Definitions */\r
-#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */\r
-#define SysTick_CALIB_NOREF_Msk (1ul << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */\r
-\r
-#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */\r
-#define SysTick_CALIB_SKEW_Msk (1ul << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */\r
-\r
-#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */\r
-#define SysTick_CALIB_TENMS_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */\r
-/*@}*/ /* end of group CMSIS_CM3_SysTick */\r
-\r
-\r
-/** @addtogroup CMSIS_CM3_ITM CMSIS CM3 ITM\r
- memory mapped structure for Instrumentation Trace Macrocell (ITM)\r
- @{\r
- */\r
-typedef struct\r
-{\r
- __O union \r
- {\r
- __O uint8_t u8; /*!< Offset: ITM Stimulus Port 8-bit */\r
- __O uint16_t u16; /*!< Offset: ITM Stimulus Port 16-bit */\r
- __O uint32_t u32; /*!< Offset: ITM Stimulus Port 32-bit */\r
- } PORT [32]; /*!< Offset: 0x00 ITM Stimulus Port Registers */\r
- uint32_t RESERVED0[864]; \r
- __IO uint32_t TER; /*!< Offset: ITM Trace Enable Register */\r
- uint32_t RESERVED1[15]; \r
- __IO uint32_t TPR; /*!< Offset: ITM Trace Privilege Register */\r
- uint32_t RESERVED2[15]; \r
- __IO uint32_t TCR; /*!< Offset: ITM Trace Control Register */\r
- uint32_t RESERVED3[29]; \r
- __IO uint32_t IWR; /*!< Offset: ITM Integration Write Register */\r
- __IO uint32_t IRR; /*!< Offset: ITM Integration Read Register */\r
- __IO uint32_t IMCR; /*!< Offset: ITM Integration Mode Control Register */\r
- uint32_t RESERVED4[43]; \r
- __IO uint32_t LAR; /*!< Offset: ITM Lock Access Register */\r
- __IO uint32_t LSR; /*!< Offset: ITM Lock Status Register */\r
- uint32_t RESERVED5[6]; \r
- __I uint32_t PID4; /*!< Offset: ITM Peripheral Identification Register #4 */\r
- __I uint32_t PID5; /*!< Offset: ITM Peripheral Identification Register #5 */\r
- __I uint32_t PID6; /*!< Offset: ITM Peripheral Identification Register #6 */\r
- __I uint32_t PID7; /*!< Offset: ITM Peripheral Identification Register #7 */\r
- __I uint32_t PID0; /*!< Offset: ITM Peripheral Identification Register #0 */\r
- __I uint32_t PID1; /*!< Offset: ITM Peripheral Identification Register #1 */\r
- __I uint32_t PID2; /*!< Offset: ITM Peripheral Identification Register #2 */\r
- __I uint32_t PID3; /*!< Offset: ITM Peripheral Identification Register #3 */\r
- __I uint32_t CID0; /*!< Offset: ITM Component Identification Register #0 */\r
- __I uint32_t CID1; /*!< Offset: ITM Component Identification Register #1 */\r
- __I uint32_t CID2; /*!< Offset: ITM Component Identification Register #2 */\r
- __I uint32_t CID3; /*!< Offset: ITM Component Identification Register #3 */\r
-} ITM_Type; \r
-\r
-/* ITM Trace Privilege Register Definitions */\r
-#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */\r
-#define ITM_TPR_PRIVMASK_Msk (0xFul << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */\r
-\r
-/* ITM Trace Control Register Definitions */\r
-#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */\r
-#define ITM_TCR_BUSY_Msk (1ul << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */\r
-\r
-#define ITM_TCR_ATBID_Pos 16 /*!< ITM TCR: ATBID Position */\r
-#define ITM_TCR_ATBID_Msk (0x7Ful << ITM_TCR_ATBID_Pos) /*!< ITM TCR: ATBID Mask */\r
-\r
-#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */\r
-#define ITM_TCR_TSPrescale_Msk (3ul << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */\r
-\r
-#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */\r
-#define ITM_TCR_SWOENA_Msk (1ul << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */\r
-\r
-#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */\r
-#define ITM_TCR_DWTENA_Msk (1ul << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */\r
-\r
-#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */\r
-#define ITM_TCR_SYNCENA_Msk (1ul << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */\r
-\r
-#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */\r
-#define ITM_TCR_TSENA_Msk (1ul << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */\r
-\r
-#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */\r
-#define ITM_TCR_ITMENA_Msk (1ul << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */\r
-\r
-/* ITM Integration Write Register Definitions */\r
-#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */\r
-#define ITM_IWR_ATVALIDM_Msk (1ul << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */\r
-\r
-/* ITM Integration Read Register Definitions */\r
-#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */\r
-#define ITM_IRR_ATREADYM_Msk (1ul << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */\r
-\r
-/* ITM Integration Mode Control Register Definitions */\r
-#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */\r
-#define ITM_IMCR_INTEGRATION_Msk (1ul << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */\r
-\r
-/* ITM Lock Status Register Definitions */\r
-#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */\r
-#define ITM_LSR_ByteAcc_Msk (1ul << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */\r
-\r
-#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */\r
-#define ITM_LSR_Access_Msk (1ul << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */\r
-\r
-#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */\r
-#define ITM_LSR_Present_Msk (1ul << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */\r
-/*@}*/ /* end of group CMSIS_CM3_ITM */\r
-\r
-\r
-/** @addtogroup CMSIS_CM3_InterruptType CMSIS CM3 Interrupt Type\r
- memory mapped structure for Interrupt Type\r
- @{\r
- */\r
-typedef struct\r
-{\r
- uint32_t RESERVED0;\r
- __I uint32_t ICTR; /*!< Offset: 0x04 Interrupt Control Type Register */\r
-#if ((defined __CM3_REV) && (__CM3_REV >= 0x200))\r
- __IO uint32_t ACTLR; /*!< Offset: 0x08 Auxiliary Control Register */\r
-#else\r
- uint32_t RESERVED1;\r
-#endif\r
-} InterruptType_Type;\r
-\r
-/* Interrupt Controller Type Register Definitions */\r
-#define InterruptType_ICTR_INTLINESNUM_Pos 0 /*!< InterruptType ICTR: INTLINESNUM Position */\r
-#define InterruptType_ICTR_INTLINESNUM_Msk (0x1Ful << InterruptType_ICTR_INTLINESNUM_Pos) /*!< InterruptType ICTR: INTLINESNUM Mask */\r
-\r
-/* Auxiliary Control Register Definitions */\r
-#define InterruptType_ACTLR_DISFOLD_Pos 2 /*!< InterruptType ACTLR: DISFOLD Position */\r
-#define InterruptType_ACTLR_DISFOLD_Msk (1ul << InterruptType_ACTLR_DISFOLD_Pos) /*!< InterruptType ACTLR: DISFOLD Mask */\r
-\r
-#define InterruptType_ACTLR_DISDEFWBUF_Pos 1 /*!< InterruptType ACTLR: DISDEFWBUF Position */\r
-#define InterruptType_ACTLR_DISDEFWBUF_Msk (1ul << InterruptType_ACTLR_DISDEFWBUF_Pos) /*!< InterruptType ACTLR: DISDEFWBUF Mask */\r
-\r
-#define InterruptType_ACTLR_DISMCYCINT_Pos 0 /*!< InterruptType ACTLR: DISMCYCINT Position */\r
-#define InterruptType_ACTLR_DISMCYCINT_Msk (1ul << InterruptType_ACTLR_DISMCYCINT_Pos) /*!< InterruptType ACTLR: DISMCYCINT Mask */\r
-/*@}*/ /* end of group CMSIS_CM3_InterruptType */\r
-\r
-\r
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1)\r
-/** @addtogroup CMSIS_CM3_MPU CMSIS CM3 MPU\r
- memory mapped structure for Memory Protection Unit (MPU)\r
- @{\r
- */\r
-typedef struct\r
-{\r
- __I uint32_t TYPE; /*!< Offset: 0x00 MPU Type Register */\r
- __IO uint32_t CTRL; /*!< Offset: 0x04 MPU Control Register */\r
- __IO uint32_t RNR; /*!< Offset: 0x08 MPU Region RNRber Register */\r
- __IO uint32_t RBAR; /*!< Offset: 0x0C MPU Region Base Address Register */\r
- __IO uint32_t RASR; /*!< Offset: 0x10 MPU Region Attribute and Size Register */\r
- __IO uint32_t RBAR_A1; /*!< Offset: 0x14 MPU Alias 1 Region Base Address Register */\r
- __IO uint32_t RASR_A1; /*!< Offset: 0x18 MPU Alias 1 Region Attribute and Size Register */\r
- __IO uint32_t RBAR_A2; /*!< Offset: 0x1C MPU Alias 2 Region Base Address Register */\r
- __IO uint32_t RASR_A2; /*!< Offset: 0x20 MPU Alias 2 Region Attribute and Size Register */\r
- __IO uint32_t RBAR_A3; /*!< Offset: 0x24 MPU Alias 3 Region Base Address Register */\r
- __IO uint32_t RASR_A3; /*!< Offset: 0x28 MPU Alias 3 Region Attribute and Size Register */\r
-} MPU_Type; \r
-\r
-/* MPU Type Register */\r
-#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */\r
-#define MPU_TYPE_IREGION_Msk (0xFFul << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */\r
-\r
-#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */\r
-#define MPU_TYPE_DREGION_Msk (0xFFul << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */\r
-\r
-#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */\r
-#define MPU_TYPE_SEPARATE_Msk (1ul << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */\r
-\r
-/* MPU Control Register */\r
-#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */\r
-#define MPU_CTRL_PRIVDEFENA_Msk (1ul << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */\r
-\r
-#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */\r
-#define MPU_CTRL_HFNMIENA_Msk (1ul << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */\r
-\r
-#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */\r
-#define MPU_CTRL_ENABLE_Msk (1ul << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */\r
-\r
-/* MPU Region Number Register */\r
-#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */\r
-#define MPU_RNR_REGION_Msk (0xFFul << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */\r
-\r
-/* MPU Region Base Address Register */\r
-#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */\r
-#define MPU_RBAR_ADDR_Msk (0x7FFFFFFul << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */\r
-\r
-#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */\r
-#define MPU_RBAR_VALID_Msk (1ul << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */\r
-\r
-#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */\r
-#define MPU_RBAR_REGION_Msk (0xFul << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */\r
-\r
-/* MPU Region Attribute and Size Register */\r
-#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: XN Position */\r
-#define MPU_RASR_XN_Msk (1ul << MPU_RASR_XN_Pos) /*!< MPU RASR: XN Mask */\r
-\r
-#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: AP Position */\r
-#define MPU_RASR_AP_Msk (7ul << MPU_RASR_AP_Pos) /*!< MPU RASR: AP Mask */\r
-\r
-#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: TEX Position */\r
-#define MPU_RASR_TEX_Msk (7ul << MPU_RASR_TEX_Pos) /*!< MPU RASR: TEX Mask */\r
-\r
-#define MPU_RASR_S_Pos 18 /*!< MPU RASR: Shareable bit Position */\r
-#define MPU_RASR_S_Msk (1ul << MPU_RASR_S_Pos) /*!< MPU RASR: Shareable bit Mask */\r
-\r
-#define MPU_RASR_C_Pos 17 /*!< MPU RASR: Cacheable bit Position */\r
-#define MPU_RASR_C_Msk (1ul << MPU_RASR_C_Pos) /*!< MPU RASR: Cacheable bit Mask */\r
-\r
-#define MPU_RASR_B_Pos 16 /*!< MPU RASR: Bufferable bit Position */\r
-#define MPU_RASR_B_Msk (1ul << MPU_RASR_B_Pos) /*!< MPU RASR: Bufferable bit Mask */\r
-\r
-#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */\r
-#define MPU_RASR_SRD_Msk (0xFFul << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */\r
-\r
-#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */\r
-#define MPU_RASR_SIZE_Msk (0x1Ful << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */\r
-\r
-#define MPU_RASR_ENA_Pos 0 /*!< MPU RASR: Region enable bit Position */\r
-#define MPU_RASR_ENA_Msk (0x1Ful << MPU_RASR_ENA_Pos) /*!< MPU RASR: Region enable bit Disable Mask */\r
-\r
-/*@}*/ /* end of group CMSIS_CM3_MPU */\r
-#endif\r
-\r
-\r
-/** @addtogroup CMSIS_CM3_CoreDebug CMSIS CM3 Core Debug\r
- memory mapped structure for Core Debug Register\r
- @{\r
- */\r
-typedef struct\r
-{\r
- __IO uint32_t DHCSR; /*!< Offset: 0x00 Debug Halting Control and Status Register */\r
- __O uint32_t DCRSR; /*!< Offset: 0x04 Debug Core Register Selector Register */\r
- __IO uint32_t DCRDR; /*!< Offset: 0x08 Debug Core Register Data Register */\r
- __IO uint32_t DEMCR; /*!< Offset: 0x0C Debug Exception and Monitor Control Register */\r
-} CoreDebug_Type;\r
-\r
-/* Debug Halting Control and Status Register */\r
-#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */\r
-#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFul << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */\r
-\r
-#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */\r
-#define CoreDebug_DHCSR_S_RESET_ST_Msk (1ul << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */\r
-\r
-#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */\r
-#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1ul << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */\r
-\r
-#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */\r
-#define CoreDebug_DHCSR_S_LOCKUP_Msk (1ul << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */\r
-\r
-#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */\r
-#define CoreDebug_DHCSR_S_SLEEP_Msk (1ul << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */\r
-\r
-#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */\r
-#define CoreDebug_DHCSR_S_HALT_Msk (1ul << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */\r
-\r
-#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */\r
-#define CoreDebug_DHCSR_S_REGRDY_Msk (1ul << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */\r
-\r
-#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */\r
-#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1ul << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */\r
-\r
-#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */\r
-#define CoreDebug_DHCSR_C_MASKINTS_Msk (1ul << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */\r
-\r
-#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */\r
-#define CoreDebug_DHCSR_C_STEP_Msk (1ul << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */\r
-\r
-#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */\r
-#define CoreDebug_DHCSR_C_HALT_Msk (1ul << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */\r
-\r
-#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */\r
-#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1ul << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */\r
-\r
-/* Debug Core Register Selector Register */\r
-#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */\r
-#define CoreDebug_DCRSR_REGWnR_Msk (1ul << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */\r
-\r
-#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */\r
-#define CoreDebug_DCRSR_REGSEL_Msk (0x1Ful << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */\r
-\r
-/* Debug Exception and Monitor Control Register */\r
-#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */\r
-#define CoreDebug_DEMCR_TRCENA_Msk (1ul << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */\r
-\r
-#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */\r
-#define CoreDebug_DEMCR_MON_REQ_Msk (1ul << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */\r
-\r
-#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */\r
-#define CoreDebug_DEMCR_MON_STEP_Msk (1ul << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */\r
-\r
-#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */\r
-#define CoreDebug_DEMCR_MON_PEND_Msk (1ul << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */\r
-\r
-#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */\r
-#define CoreDebug_DEMCR_MON_EN_Msk (1ul << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */\r
-#define CoreDebug_DEMCR_VC_HARDERR_Msk (1ul << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */\r
-#define CoreDebug_DEMCR_VC_INTERR_Msk (1ul << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */\r
-#define CoreDebug_DEMCR_VC_BUSERR_Msk (1ul << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */\r
-#define CoreDebug_DEMCR_VC_STATERR_Msk (1ul << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */\r
-#define CoreDebug_DEMCR_VC_CHKERR_Msk (1ul << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */\r
-#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1ul << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */\r
-#define CoreDebug_DEMCR_VC_MMERR_Msk (1ul << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */\r
-#define CoreDebug_DEMCR_VC_CORERESET_Msk (1ul << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */\r
-/*@}*/ /* end of group CMSIS_CM3_CoreDebug */\r
-\r
-\r
-/* Memory mapping of Cortex-M3 Hardware */\r
-#define SCS_BASE (0xE000E000) /*!< System Control Space Base Address */\r
-#define ITM_BASE (0xE0000000) /*!< ITM Base Address */\r
-#define CoreDebug_BASE (0xE000EDF0) /*!< Core Debug Base Address */\r
-#define SysTick_BASE (SCS_BASE + 0x0010) /*!< SysTick Base Address */\r
-#define NVIC_BASE (SCS_BASE + 0x0100) /*!< NVIC Base Address */\r
-#define SCB_BASE (SCS_BASE + 0x0D00) /*!< System Control Block Base Address */\r
-\r
-#define InterruptType ((InterruptType_Type *) SCS_BASE) /*!< Interrupt Type Register */\r
-#define SCB ((SCB_Type *) SCB_BASE) /*!< SCB configuration struct */\r
-#define SysTick ((SysTick_Type *) SysTick_BASE) /*!< SysTick configuration struct */\r
-#define NVIC ((NVIC_Type *) NVIC_BASE) /*!< NVIC configuration struct */\r
-#define ITM ((ITM_Type *) ITM_BASE) /*!< ITM configuration struct */\r
-#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */\r
-\r
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1)\r
- #define MPU_BASE (SCS_BASE + 0x0D90) /*!< Memory Protection Unit */\r
- #define MPU ((MPU_Type*) MPU_BASE) /*!< Memory Protection Unit */\r
-#endif\r
-\r
-/*@}*/ /* end of group CMSIS_CM3_core_register */\r
-\r
-\r
-/*******************************************************************************\r
- * Hardware Abstraction Layer\r
- ******************************************************************************/\r
-\r
-#if defined ( __CC_ARM )\r
- #define __ASM __asm /*!< asm keyword for ARM Compiler */\r
- #define __INLINE __inline /*!< inline keyword for ARM Compiler */\r
-\r
-#elif defined ( __ICCARM__ )\r
- #define __ASM __asm /*!< asm keyword for IAR Compiler */\r
- #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */\r
-\r
-#elif defined ( __GNUC__ )\r
- #define __ASM __asm /*!< asm keyword for GNU Compiler */\r
- #define __INLINE inline /*!< inline keyword for GNU Compiler */\r
-\r
-#elif defined ( __TASKING__ )\r
- #define __ASM __asm /*!< asm keyword for TASKING Compiler */\r
- #define __INLINE inline /*!< inline keyword for TASKING Compiler */\r
-\r
-#endif\r
-\r
-\r
-/* ################### Compiler specific Intrinsics ########################### */\r
-\r
-#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/\r
-/* ARM armcc specific functions */\r
-\r
-#define __enable_fault_irq __enable_fiq\r
-#define __disable_fault_irq __disable_fiq\r
-\r
-#define __NOP __nop\r
-#define __WFI __wfi\r
-#define __WFE __wfe\r
-#define __SEV __sev\r
-#define __ISB() __isb(0)\r
-#define __DSB() __dsb(0)\r
-#define __DMB() __dmb(0)\r
-#define __REV __rev\r
-#define __RBIT __rbit\r
-#define __LDREXB(ptr) ((unsigned char ) __ldrex(ptr))\r
-#define __LDREXH(ptr) ((unsigned short) __ldrex(ptr))\r
-#define __LDREXW(ptr) ((unsigned int ) __ldrex(ptr))\r
-#define __STREXB(value, ptr) __strex(value, ptr)\r
-#define __STREXH(value, ptr) __strex(value, ptr)\r
-#define __STREXW(value, ptr) __strex(value, ptr)\r
-\r
-\r
-/* intrinsic unsigned long long __ldrexd(volatile void *ptr) */\r
-/* intrinsic int __strexd(unsigned long long val, volatile void *ptr) */\r
-/* intrinsic void __enable_irq(); */\r
-/* intrinsic void __disable_irq(); */\r
-\r
-\r
-/**\r
- * @brief Return the Process Stack Pointer\r
- *\r
- * @return ProcessStackPointer\r
- *\r
- * Return the actual process stack pointer\r
- */\r
-extern uint32_t __get_PSP(void);\r
-\r
-/**\r
- * @brief Set the Process Stack Pointer\r
- *\r
- * @param topOfProcStack Process Stack Pointer\r
- *\r
- * Assign the value ProcessStackPointer to the MSP \r
- * (process stack pointer) Cortex processor register\r
- */\r
-extern void __set_PSP(uint32_t topOfProcStack);\r
-\r
-/**\r
- * @brief Return the Main Stack Pointer\r
- *\r
- * @return Main Stack Pointer\r
- *\r
- * Return the current value of the MSP (main stack pointer)\r
- * Cortex processor register\r
- */\r
-extern uint32_t __get_MSP(void);\r
-\r
-/**\r
- * @brief Set the Main Stack Pointer\r
- *\r
- * @param topOfMainStack Main Stack Pointer\r
- *\r
- * Assign the value mainStackPointer to the MSP \r
- * (main stack pointer) Cortex processor register\r
- */\r
-extern void __set_MSP(uint32_t topOfMainStack);\r
-\r
-/**\r
- * @brief Reverse byte order in unsigned short value\r
- *\r
- * @param value value to reverse\r
- * @return reversed value\r
- *\r
- * Reverse byte order in unsigned short value\r
- */\r
-extern uint32_t __REV16(uint16_t value);\r
-\r
-/**\r
- * @brief Reverse byte order in signed short value with sign extension to integer\r
- *\r
- * @param value value to reverse\r
- * @return reversed value\r
- *\r
- * Reverse byte order in signed short value with sign extension to integer\r
- */\r
-extern int32_t __REVSH(int16_t value);\r
-\r
-\r
-#if (__ARMCC_VERSION < 400000)\r
-\r
-/**\r
- * @brief Remove the exclusive lock created by ldrex\r
- *\r
- * Removes the exclusive lock which is created by ldrex.\r
- */\r
-extern void __CLREX(void);\r
-\r
-/**\r
- * @brief Return the Base Priority value\r
- *\r
- * @return BasePriority\r
- *\r
- * Return the content of the base priority register\r
- */\r
-extern uint32_t __get_BASEPRI(void);\r
-\r
-/**\r
- * @brief Set the Base Priority value\r
- *\r
- * @param basePri BasePriority\r
- *\r
- * Set the base priority register\r
- */\r
-extern void __set_BASEPRI(uint32_t basePri);\r
-\r
-/**\r
- * @brief Return the Priority Mask value\r
- *\r
- * @return PriMask\r
- *\r
- * Return state of the priority mask bit from the priority mask register\r
- */\r
-extern uint32_t __get_PRIMASK(void);\r
-\r
-/**\r
- * @brief Set the Priority Mask value\r
- *\r
- * @param priMask PriMask\r
- *\r
- * Set the priority mask bit in the priority mask register\r
- */\r
-extern void __set_PRIMASK(uint32_t priMask);\r
-\r
-/**\r
- * @brief Return the Fault Mask value\r
- *\r
- * @return FaultMask\r
- *\r
- * Return the content of the fault mask register\r
- */\r
-extern uint32_t __get_FAULTMASK(void);\r
-\r
-/**\r
- * @brief Set the Fault Mask value\r
- *\r
- * @param faultMask faultMask value\r
- *\r
- * Set the fault mask register\r
- */\r
-extern void __set_FAULTMASK(uint32_t faultMask);\r
-\r
-/**\r
- * @brief Return the Control Register value\r
- * \r
- * @return Control value\r
- *\r
- * Return the content of the control register\r
- */\r
-extern uint32_t __get_CONTROL(void);\r
-\r
-/**\r
- * @brief Set the Control Register value\r
- *\r
- * @param control Control value\r
- *\r
- * Set the control register\r
- */\r
-extern void __set_CONTROL(uint32_t control);\r
-\r
-#else /* (__ARMCC_VERSION >= 400000) */\r
-\r
-/**\r
- * @brief Remove the exclusive lock created by ldrex\r
- *\r
- * Removes the exclusive lock which is created by ldrex.\r
- */\r
-#define __CLREX __clrex\r
-\r
-/**\r
- * @brief Return the Base Priority value\r
- *\r
- * @return BasePriority\r
- *\r
- * Return the content of the base priority register\r
- */\r
-static __INLINE uint32_t __get_BASEPRI(void)\r
-{\r
- register uint32_t __regBasePri __ASM("basepri");\r
- return(__regBasePri);\r
-}\r
-\r
-/**\r
- * @brief Set the Base Priority value\r
- *\r
- * @param basePri BasePriority\r
- *\r
- * Set the base priority register\r
- */\r
-static __INLINE void __set_BASEPRI(uint32_t basePri)\r
-{\r
- register uint32_t __regBasePri __ASM("basepri");\r
- __regBasePri = (basePri & 0xff);\r
-}\r
-\r
-/**\r
- * @brief Return the Priority Mask value\r
- *\r
- * @return PriMask\r
- *\r
- * Return state of the priority mask bit from the priority mask register\r
- */\r
-static __INLINE uint32_t __get_PRIMASK(void)\r
-{\r
- register uint32_t __regPriMask __ASM("primask");\r
- return(__regPriMask);\r
-}\r
-\r
-/**\r
- * @brief Set the Priority Mask value\r
- *\r
- * @param priMask PriMask\r
- *\r
- * Set the priority mask bit in the priority mask register\r
- */\r
-static __INLINE void __set_PRIMASK(uint32_t priMask)\r
-{\r
- register uint32_t __regPriMask __ASM("primask");\r
- __regPriMask = (priMask);\r
-}\r
-\r
-/**\r
- * @brief Return the Fault Mask value\r
- *\r
- * @return FaultMask\r
- *\r
- * Return the content of the fault mask register\r
- */\r
-static __INLINE uint32_t __get_FAULTMASK(void)\r
-{\r
- register uint32_t __regFaultMask __ASM("faultmask");\r
- return(__regFaultMask);\r
-}\r
-\r
-/**\r
- * @brief Set the Fault Mask value\r
- *\r
- * @param faultMask faultMask value\r
- *\r
- * Set the fault mask register\r
- */\r
-static __INLINE void __set_FAULTMASK(uint32_t faultMask)\r
-{\r
- register uint32_t __regFaultMask __ASM("faultmask");\r
- __regFaultMask = (faultMask & 1);\r
-}\r
-\r
-/**\r
- * @brief Return the Control Register value\r
- * \r
- * @return Control value\r
- *\r
- * Return the content of the control register\r
- */\r
-static __INLINE uint32_t __get_CONTROL(void)\r
-{\r
- register uint32_t __regControl __ASM("control");\r
- return(__regControl);\r
-}\r
-\r
-/**\r
- * @brief Set the Control Register value\r
- *\r
- * @param control Control value\r
- *\r
- * Set the control register\r
- */\r
-static __INLINE void __set_CONTROL(uint32_t control)\r
-{\r
- register uint32_t __regControl __ASM("control");\r
- __regControl = control;\r
-}\r
-\r
-#endif /* __ARMCC_VERSION */ \r
-\r
-\r
-\r
-#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/\r
-/* IAR iccarm specific functions */\r
-\r
-#define __enable_irq __enable_interrupt /*!< global Interrupt enable */\r
-#define __disable_irq __disable_interrupt /*!< global Interrupt disable */\r
-\r
-static __INLINE void __enable_fault_irq() { __ASM ("cpsie f"); }\r
-static __INLINE void __disable_fault_irq() { __ASM ("cpsid f"); }\r
-\r
-#define __NOP __no_operation /*!< no operation intrinsic in IAR Compiler */ \r
-static __INLINE void __WFI() { __ASM ("wfi"); }\r
-static __INLINE void __WFE() { __ASM ("wfe"); }\r
-static __INLINE void __SEV() { __ASM ("sev"); }\r
-static __INLINE void __CLREX() { __ASM ("clrex"); }\r
-\r
-/* intrinsic void __ISB(void) */\r
-/* intrinsic void __DSB(void) */\r
-/* intrinsic void __DMB(void) */\r
-/* intrinsic void __set_PRIMASK(); */\r
-/* intrinsic void __get_PRIMASK(); */\r
-/* intrinsic void __set_FAULTMASK(); */\r
-/* intrinsic void __get_FAULTMASK(); */\r
-/* intrinsic uint32_t __REV(uint32_t value); */\r
-/* intrinsic uint32_t __REVSH(uint32_t value); */\r
-/* intrinsic unsigned long __STREX(unsigned long, unsigned long); */\r
-/* intrinsic unsigned long __LDREX(unsigned long *); */\r
-\r
-\r
-/**\r
- * @brief Return the Process Stack Pointer\r
- *\r
- * @return ProcessStackPointer\r
- *\r
- * Return the actual process stack pointer\r
- */\r
-extern uint32_t __get_PSP(void);\r
-\r
-/**\r
- * @brief Set the Process Stack Pointer\r
- *\r
- * @param topOfProcStack Process Stack Pointer\r
- *\r
- * Assign the value ProcessStackPointer to the MSP \r
- * (process stack pointer) Cortex processor register\r
- */\r
-extern void __set_PSP(uint32_t topOfProcStack);\r
-\r
-/**\r
- * @brief Return the Main Stack Pointer\r
- *\r
- * @return Main Stack Pointer\r
- *\r
- * Return the current value of the MSP (main stack pointer)\r
- * Cortex processor register\r
- */\r
-extern uint32_t __get_MSP(void);\r
-\r
-/**\r
- * @brief Set the Main Stack Pointer\r
- *\r
- * @param topOfMainStack Main Stack Pointer\r
- *\r
- * Assign the value mainStackPointer to the MSP \r
- * (main stack pointer) Cortex processor register\r
- */\r
-extern void __set_MSP(uint32_t topOfMainStack);\r
-\r
-/**\r
- * @brief Reverse byte order in unsigned short value\r
- *\r
- * @param value value to reverse\r
- * @return reversed value\r
- *\r
- * Reverse byte order in unsigned short value\r
- */\r
-extern uint32_t __REV16(uint16_t value);\r
-\r
-/**\r
- * @brief Reverse bit order of value\r
- *\r
- * @param value value to reverse\r
- * @return reversed value\r
- *\r
- * Reverse bit order of value\r
- */\r
-extern uint32_t __RBIT(uint32_t value);\r
-\r
-/**\r
- * @brief LDR Exclusive (8 bit)\r
- *\r
- * @param *addr address pointer\r
- * @return value of (*address)\r
- *\r
- * Exclusive LDR command for 8 bit values)\r
- */\r
-extern uint8_t __LDREXB(uint8_t *addr);\r
-\r
-/**\r
- * @brief LDR Exclusive (16 bit)\r
- *\r
- * @param *addr address pointer\r
- * @return value of (*address)\r
- *\r
- * Exclusive LDR command for 16 bit values\r
- */\r
-extern uint16_t __LDREXH(uint16_t *addr);\r
-\r
-/**\r
- * @brief LDR Exclusive (32 bit)\r
- *\r
- * @param *addr address pointer\r
- * @return value of (*address)\r
- *\r
- * Exclusive LDR command for 32 bit values\r
- */\r
-extern uint32_t __LDREXW(uint32_t *addr);\r
-\r
-/**\r
- * @brief STR Exclusive (8 bit)\r
- *\r
- * @param value value to store\r
- * @param *addr address pointer\r
- * @return successful / failed\r
- *\r
- * Exclusive STR command for 8 bit values\r
- */\r
-extern uint32_t __STREXB(uint8_t value, uint8_t *addr);\r
-\r
-/**\r
- * @brief STR Exclusive (16 bit)\r
- *\r
- * @param value value to store\r
- * @param *addr address pointer\r
- * @return successful / failed\r
- *\r
- * Exclusive STR command for 16 bit values\r
- */\r
-extern uint32_t __STREXH(uint16_t value, uint16_t *addr);\r
-\r
-/**\r
- * @brief STR Exclusive (32 bit)\r
- *\r
- * @param value value to store\r
- * @param *addr address pointer\r
- * @return successful / failed\r
- *\r
- * Exclusive STR command for 32 bit values\r
- */\r
-extern uint32_t __STREXW(uint32_t value, uint32_t *addr);\r
-\r
-\r
-\r
-#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/\r
-/* GNU gcc specific functions */\r
-\r
-static __INLINE void __enable_irq(void) { __ASM volatile ("cpsie i"); }\r
-static __INLINE void __disable_irq(void) { __ASM volatile ("cpsid i"); }\r
-\r
-static __INLINE void __enable_fault_irq(void) { __ASM volatile ("cpsie f"); }\r
-static __INLINE void __disable_fault_irq(void) { __ASM volatile ("cpsid f"); }\r
-\r
-static __INLINE void __NOP(void) { __ASM volatile ("nop"); }\r
-static __INLINE void __WFI(void) { __ASM volatile ("wfi"); }\r
-static __INLINE void __WFE(void) { __ASM volatile ("wfe"); }\r
-static __INLINE void __SEV(void) { __ASM volatile ("sev"); }\r
-static __INLINE void __ISB(void) { __ASM volatile ("isb"); }\r
-static __INLINE void __DSB(void) { __ASM volatile ("dsb"); }\r
-static __INLINE void __DMB(void) { __ASM volatile ("dmb"); }\r
-static __INLINE void __CLREX(void) { __ASM volatile ("clrex"); }\r
-\r
-\r
-/**\r
- * @brief Return the Process Stack Pointer\r
- *\r
- * @return ProcessStackPointer\r
- *\r
- * Return the actual process stack pointer\r
- */\r
-extern uint32_t __get_PSP(void);\r
-\r
-/**\r
- * @brief Set the Process Stack Pointer\r
- *\r
- * @param topOfProcStack Process Stack Pointer\r
- *\r
- * Assign the value ProcessStackPointer to the MSP \r
- * (process stack pointer) Cortex processor register\r
- */\r
-extern void __set_PSP(uint32_t topOfProcStack);\r
-\r
-/**\r
- * @brief Return the Main Stack Pointer\r
- *\r
- * @return Main Stack Pointer\r
- *\r
- * Return the current value of the MSP (main stack pointer)\r
- * Cortex processor register\r
- */\r
-extern uint32_t __get_MSP(void);\r
-\r
-/**\r
- * @brief Set the Main Stack Pointer\r
- *\r
- * @param topOfMainStack Main Stack Pointer\r
- *\r
- * Assign the value mainStackPointer to the MSP \r
- * (main stack pointer) Cortex processor register\r
- */\r
-extern void __set_MSP(uint32_t topOfMainStack);\r
-\r
-/**\r
- * @brief Return the Base Priority value\r
- *\r
- * @return BasePriority\r
- *\r
- * Return the content of the base priority register\r
- */\r
-extern uint32_t __get_BASEPRI(void);\r
-\r
-/**\r
- * @brief Set the Base Priority value\r
- *\r
- * @param basePri BasePriority\r
- *\r
- * Set the base priority register\r
- */\r
-extern void __set_BASEPRI(uint32_t basePri);\r
-\r
-/**\r
- * @brief Return the Priority Mask value\r
- *\r
- * @return PriMask\r
- *\r
- * Return state of the priority mask bit from the priority mask register\r
- */\r
-extern uint32_t __get_PRIMASK(void);\r
-\r
-/**\r
- * @brief Set the Priority Mask value\r
- *\r
- * @param priMask PriMask\r
- *\r
- * Set the priority mask bit in the priority mask register\r
- */\r
-extern void __set_PRIMASK(uint32_t priMask);\r
-\r
-/**\r
- * @brief Return the Fault Mask value\r
- *\r
- * @return FaultMask\r
- *\r
- * Return the content of the fault mask register\r
- */\r
-extern uint32_t __get_FAULTMASK(void);\r
-\r
-/**\r
- * @brief Set the Fault Mask value\r
- *\r
- * @param faultMask faultMask value\r
- *\r
- * Set the fault mask register\r
- */\r
-extern void __set_FAULTMASK(uint32_t faultMask);\r
-\r
-/**\r
- * @brief Return the Control Register value\r
-* \r
-* @return Control value\r
- *\r
- * Return the content of the control register\r
- */\r
-extern uint32_t __get_CONTROL(void);\r
-\r
-/**\r
- * @brief Set the Control Register value\r
- *\r
- * @param control Control value\r
- *\r
- * Set the control register\r
- */\r
-extern void __set_CONTROL(uint32_t control);\r
-\r
-/**\r
- * @brief Reverse byte order in integer value\r
- *\r
- * @param value value to reverse\r
- * @return reversed value\r
- *\r
- * Reverse byte order in integer value\r
- */\r
-extern uint32_t __REV(uint32_t value);\r
-\r
-/**\r
- * @brief Reverse byte order in unsigned short value\r
- *\r
- * @param value value to reverse\r
- * @return reversed value\r
- *\r
- * Reverse byte order in unsigned short value\r
- */\r
-extern uint32_t __REV16(uint16_t value);\r
-\r
-/**\r
- * @brief Reverse byte order in signed short value with sign extension to integer\r
- *\r
- * @param value value to reverse\r
- * @return reversed value\r
- *\r
- * Reverse byte order in signed short value with sign extension to integer\r
- */\r
-extern int32_t __REVSH(int16_t value);\r
-\r
-/**\r
- * @brief Reverse bit order of value\r
- *\r
- * @param value value to reverse\r
- * @return reversed value\r
- *\r
- * Reverse bit order of value\r
- */\r
-extern uint32_t __RBIT(uint32_t value);\r
-\r
-/**\r
- * @brief LDR Exclusive (8 bit)\r
- *\r
- * @param *addr address pointer\r
- * @return value of (*address)\r
- *\r
- * Exclusive LDR command for 8 bit value\r
- */\r
-extern uint8_t __LDREXB(uint8_t *addr);\r
-\r
-/**\r
- * @brief LDR Exclusive (16 bit)\r
- *\r
- * @param *addr address pointer\r
- * @return value of (*address)\r
- *\r
- * Exclusive LDR command for 16 bit values\r
- */\r
-extern uint16_t __LDREXH(uint16_t *addr);\r
-\r
-/**\r
- * @brief LDR Exclusive (32 bit)\r
- *\r
- * @param *addr address pointer\r
- * @return value of (*address)\r
- *\r
- * Exclusive LDR command for 32 bit values\r
- */\r
-extern uint32_t __LDREXW(uint32_t *addr);\r
-\r
-/**\r
- * @brief STR Exclusive (8 bit)\r
- *\r
- * @param value value to store\r
- * @param *addr address pointer\r
- * @return successful / failed\r
- *\r
- * Exclusive STR command for 8 bit values\r
- */\r
-extern uint32_t __STREXB(uint8_t value, uint8_t *addr);\r
-\r
-/**\r
- * @brief STR Exclusive (16 bit)\r
- *\r
- * @param value value to store\r
- * @param *addr address pointer\r
- * @return successful / failed\r
- *\r
- * Exclusive STR command for 16 bit values\r
- */\r
-extern uint32_t __STREXH(uint16_t value, uint16_t *addr);\r
-\r
-/**\r
- * @brief STR Exclusive (32 bit)\r
- *\r
- * @param value value to store\r
- * @param *addr address pointer\r
- * @return successful / failed\r
- *\r
- * Exclusive STR command for 32 bit values\r
- */\r
-extern uint32_t __STREXW(uint32_t value, uint32_t *addr);\r
-\r
-\r
-#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/\r
-/* TASKING carm specific functions */\r
-\r
-/*\r
- * The CMSIS functions have been implemented as intrinsics in the compiler.\r
- * Please use "carm -?i" to get an up to date list of all instrinsics,\r
- * Including the CMSIS ones.\r
- */\r
-\r
-#endif\r
-\r
-\r
-/** @addtogroup CMSIS_CM3_Core_FunctionInterface CMSIS CM3 Core Function Interface\r
- Core Function Interface containing:\r
- - Core NVIC Functions\r
- - Core SysTick Functions\r
- - Core Reset Functions\r
-*/\r
-/*@{*/\r
-\r
-/* ########################## NVIC functions #################################### */\r
-\r
-/**\r
- * @brief Set the Priority Grouping in NVIC Interrupt Controller\r
- *\r
- * @param PriorityGroup is priority grouping field\r
- *\r
- * Set the priority grouping field using the required unlock sequence.\r
- * The parameter priority_grouping is assigned to the field \r
- * SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used.\r
- * In case of a conflict between priority grouping and available\r
- * priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\r
- */\r
-static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)\r
-{\r
- uint32_t reg_value;\r
- uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */\r
- \r
- reg_value = SCB->AIRCR; /* read old register configuration */\r
- reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */\r
- reg_value = (reg_value |\r
- (0x5FA << SCB_AIRCR_VECTKEY_Pos) | \r
- (PriorityGroupTmp << 8)); /* Insert write key and priorty group */\r
- SCB->AIRCR = reg_value;\r
-}\r
-\r
-/**\r
- * @brief Get the Priority Grouping from NVIC Interrupt Controller\r
- *\r
- * @return priority grouping field \r
- *\r
- * Get the priority grouping from NVIC Interrupt Controller.\r
- * priority grouping is SCB->AIRCR [10:8] PRIGROUP field.\r
- */\r
-static __INLINE uint32_t NVIC_GetPriorityGrouping(void)\r
-{\r
- return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */\r
-}\r
-\r
-/**\r
- * @brief Enable Interrupt in NVIC Interrupt Controller\r
- *\r
- * @param IRQn The positive number of the external interrupt to enable\r
- *\r
- * Enable a device specific interupt in the NVIC interrupt controller.\r
- * The interrupt number cannot be a negative value.\r
- */\r
-static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)\r
-{\r
- NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */\r
-}\r
-\r
-/**\r
- * @brief Disable the interrupt line for external interrupt specified\r
- * \r
- * @param IRQn The positive number of the external interrupt to disable\r
- * \r
- * Disable a device specific interupt in the NVIC interrupt controller.\r
- * The interrupt number cannot be a negative value.\r
- */\r
-static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)\r
-{\r
- NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */\r
-}\r
-\r
-/**\r
- * @brief Read the interrupt pending bit for a device specific interrupt source\r
- * \r
- * @param IRQn The number of the device specifc interrupt\r
- * @return 1 = interrupt pending, 0 = interrupt not pending\r
- *\r
- * Read the pending register in NVIC and return 1 if its status is pending, \r
- * otherwise it returns 0\r
- */\r
-static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
-{\r
- return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */\r
-}\r
-\r
-/**\r
- * @brief Set the pending bit for an external interrupt\r
- * \r
- * @param IRQn The number of the interrupt for set pending\r
- *\r
- * Set the pending bit for the specified interrupt.\r
- * The interrupt number cannot be a negative value.\r
- */\r
-static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
-{\r
- NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */\r
-}\r
-\r
-/**\r
- * @brief Clear the pending bit for an external interrupt\r
- *\r
- * @param IRQn The number of the interrupt for clear pending\r
- *\r
- * Clear the pending bit for the specified interrupt. \r
- * The interrupt number cannot be a negative value.\r
- */\r
-static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
-{\r
- NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */\r
-}\r
-\r
-/**\r
- * @brief Read the active bit for an external interrupt\r
- *\r
- * @param IRQn The number of the interrupt for read active bit\r
- * @return 1 = interrupt active, 0 = interrupt not active\r
- *\r
- * Read the active register in NVIC and returns 1 if its status is active, \r
- * otherwise it returns 0.\r
- */\r
-static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)\r
-{\r
- return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */\r
-}\r
-\r
-/**\r
- * @brief Set the priority for an interrupt\r
- *\r
- * @param IRQn The number of the interrupt for set priority\r
- * @param priority The priority to set\r
- *\r
- * Set the priority for the specified interrupt. The interrupt \r
- * number can be positive to specify an external (device specific) \r
- * interrupt, or negative to specify an internal (core) interrupt.\r
- *\r
- * Note: The priority cannot be set for every core interrupt.\r
- */\r
-static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r
-{\r
- if(IRQn < 0) {\r
- SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M3 System Interrupts */\r
- else {\r
- NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */\r
-}\r
-\r
-/**\r
- * @brief Read the priority for an interrupt\r
- *\r
- * @param IRQn The number of the interrupt for get priority\r
- * @return The priority for the interrupt\r
- *\r
- * Read the priority for the specified interrupt. The interrupt \r
- * number can be positive to specify an external (device specific) \r
- * interrupt, or negative to specify an internal (core) interrupt.\r
- *\r
- * The returned priority value is automatically aligned to the implemented\r
- * priority bits of the microcontroller.\r
- *\r
- * Note: The priority cannot be set for every core interrupt.\r
- */\r
-static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)\r
-{\r
-\r
- if(IRQn < 0) {\r
- return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M3 system interrupts */\r
- else {\r
- return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */\r
-}\r
-\r
-\r
-/**\r
- * @brief Encode the priority for an interrupt\r
- *\r
- * @param PriorityGroup The used priority group\r
- * @param PreemptPriority The preemptive priority value (starting from 0)\r
- * @param SubPriority The sub priority value (starting from 0)\r
- * @return The encoded priority for the interrupt\r
- *\r
- * Encode the priority for an interrupt with the given priority group,\r
- * preemptive priority value and sub priority value.\r
- * In case of a conflict between priority grouping and available\r
- * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.\r
- *\r
- * The returned priority value can be used for NVIC_SetPriority(...) function\r
- */\r
-static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\r
-{\r
- uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */\r
- uint32_t PreemptPriorityBits;\r
- uint32_t SubPriorityBits;\r
-\r
- PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;\r
- SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;\r
- \r
- return (\r
- ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |\r
- ((SubPriority & ((1 << (SubPriorityBits )) - 1)))\r
- );\r
-}\r
-\r
-\r
-/**\r
- * @brief Decode the priority of an interrupt\r
- *\r
- * @param Priority The priority for the interrupt\r
- * @param PriorityGroup The used priority group\r
- * @param pPreemptPriority The preemptive priority value (starting from 0)\r
- * @param pSubPriority The sub priority value (starting from 0)\r
- *\r
- * Decode an interrupt priority value with the given priority group to \r
- * preemptive priority value and sub priority value.\r
- * In case of a conflict between priority grouping and available\r
- * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.\r
- *\r
- * The priority value can be retrieved with NVIC_GetPriority(...) function\r
- */\r
-static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)\r
-{\r
- uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */\r
- uint32_t PreemptPriorityBits;\r
- uint32_t SubPriorityBits;\r
-\r
- PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;\r
- SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;\r
- \r
- *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);\r
- *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);\r
-}\r
-\r
-\r
-\r
-/* ################################## SysTick function ############################################ */\r
-\r
-#if (!defined (__Vendor_SysTickConfig)) || (__Vendor_SysTickConfig == 0)\r
-\r
-/**\r
- * @brief Initialize and start the SysTick counter and its interrupt.\r
- *\r
- * @param ticks number of ticks between two interrupts\r
- * @return 1 = failed, 0 = successful\r
- *\r
- * Initialise the system tick timer and its interrupt and start the\r
- * system tick timer / counter in free running mode to generate \r
- * periodical interrupts.\r
- */\r
-static __INLINE uint32_t SysTick_Config(uint32_t ticks)\r
-{ \r
- if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */\r
- \r
- SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */\r
- NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */\r
- SysTick->VAL = 0; /* Load the SysTick Counter Value */\r
- SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | \r
- SysTick_CTRL_TICKINT_Msk | \r
- SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
- return (0); /* Function successful */\r
-}\r
-\r
-#endif\r
-\r
-\r
-\r
-\r
-/* ################################## Reset function ############################################ */\r
-\r
-/**\r
- * @brief Initiate a system reset request.\r
- *\r
- * Initiate a system reset request to reset the MCU\r
- */\r
-static __INLINE void NVIC_SystemReset(void)\r
-{\r
- SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | \r
- (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | \r
- SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */\r
- __DSB(); /* Ensure completion of memory access */ \r
- while(1); /* wait until reset */\r
-}\r
-\r
-/*@}*/ /* end of group CMSIS_CM3_Core_FunctionInterface */\r
-\r
-\r
-\r
-/* ##################################### Debug In/Output function ########################################### */\r
-\r
-/** @addtogroup CMSIS_CM3_CoreDebugInterface CMSIS CM3 Core Debug Interface\r
- Core Debug Interface containing:\r
- - Core Debug Receive / Transmit Functions\r
- - Core Debug Defines\r
- - Core Debug Variables\r
-*/\r
-/*@{*/\r
-\r
-extern volatile int ITM_RxBuffer; /*!< variable to receive characters */\r
-#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< value identifying ITM_RxBuffer is ready for next character */\r
-\r
-\r
-/**\r
- * @brief Outputs a character via the ITM channel 0\r
- *\r
- * @param ch character to output\r
- * @return character to output\r
- *\r
- * The function outputs a character via the ITM channel 0. \r
- * The function returns when no debugger is connected that has booked the output. \r
- * It is blocking when a debugger is connected, but the previous character send is not transmitted. \r
- */\r
-static __INLINE uint32_t ITM_SendChar (uint32_t ch)\r
-{\r
- if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk) && /* Trace enabled */\r
- (ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */\r
- (ITM->TER & (1ul << 0) ) ) /* ITM Port #0 enabled */\r
- {\r
- while (ITM->PORT[0].u32 == 0);\r
- ITM->PORT[0].u8 = (uint8_t) ch;\r
- } \r
- return (ch);\r
-}\r
-\r
-\r
-/**\r
- * @brief Inputs a character via variable ITM_RxBuffer\r
- *\r
- * @return received character, -1 = no character received\r
- *\r
- * The function inputs a character via variable ITM_RxBuffer. \r
- * The function returns when no debugger is connected that has booked the output. \r
- * It is blocking when a debugger is connected, but the previous character send is not transmitted. \r
- */\r
-static __INLINE int ITM_ReceiveChar (void) {\r
- int ch = -1; /* no character available */\r
-\r
- if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {\r
- ch = ITM_RxBuffer;\r
- ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */\r
- }\r
- \r
- return (ch); \r
-}\r
-\r
-\r
-/**\r
- * @brief Check if a character via variable ITM_RxBuffer is available\r
- *\r
- * @return 1 = character available, 0 = no character available\r
- *\r
- * The function checks variable ITM_RxBuffer whether a character is available or not. \r
- * The function returns '1' if a character is available and '0' if no character is available. \r
- */\r
-static __INLINE int ITM_CheckChar (void) {\r
-\r
- if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {\r
- return (0); /* no character available */\r
- } else {\r
- return (1); /* character available */\r
- }\r
-}\r
-\r
-/*@}*/ /* end of group CMSIS_CM3_core_DebugInterface */\r
-\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-/*@}*/ /* end of group CMSIS_CM3_core_definitions */\r
-\r
-#endif /* __CM3_CORE_H__ */\r
-\r
-/*lint -restore */\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file core_cm3.h\r
+ * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File\r
+ * @version V1.30\r
+ * @date 30. October 2009\r
+ *\r
+ * @note\r
+ * Copyright (C) 2009 ARM Limited. All rights reserved.\r
+ *\r
+ * @par\r
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M \r
+ * processor based microcontrollers. This file can be freely distributed \r
+ * within development tools that are supporting such ARM based processors. \r
+ *\r
+ * @par\r
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+ *\r
+ ******************************************************************************/\r
+\r
+#ifndef __CM3_CORE_H__\r
+#define __CM3_CORE_H__\r
+\r
+/** @addtogroup CMSIS_CM3_core_LintCinfiguration CMSIS CM3 Core Lint Configuration\r
+ *\r
+ * List of Lint messages which will be suppressed and not shown:\r
+ * - Error 10: \n\r
+ * register uint32_t __regBasePri __asm("basepri"); \n\r
+ * Error 10: Expecting ';'\r
+ * .\r
+ * - Error 530: \n\r
+ * return(__regBasePri); \n\r
+ * Warning 530: Symbol '__regBasePri' (line 264) not initialized\r
+ * . \r
+ * - Error 550: \n\r
+ * __regBasePri = (basePri & 0x1ff); \n\r
+ * Warning 550: Symbol '__regBasePri' (line 271) not accessed\r
+ * .\r
+ * - Error 754: \n\r
+ * uint32_t RESERVED0[24]; \n\r
+ * Info 754: local structure member '<some, not used in the HAL>' (line 109, file ./cm3_core.h) not referenced\r
+ * .\r
+ * - Error 750: \n\r
+ * #define __CM3_CORE_H__ \n\r
+ * Info 750: local macro '__CM3_CORE_H__' (line 43, file./cm3_core.h) not referenced\r
+ * .\r
+ * - Error 528: \n\r
+ * static __INLINE void NVIC_DisableIRQ(uint32_t IRQn) \n\r
+ * Warning 528: Symbol 'NVIC_DisableIRQ(unsigned int)' (line 419, file ./cm3_core.h) not referenced\r
+ * .\r
+ * - Error 751: \n\r
+ * } InterruptType_Type; \n\r
+ * Info 751: local typedef 'InterruptType_Type' (line 170, file ./cm3_core.h) not referenced\r
+ * .\r
+ * Note: To re-enable a Message, insert a space before 'lint' *\r
+ *\r
+ */\r
+\r
+/*lint -save */\r
+/*lint -e10 */\r
+/*lint -e530 */\r
+/*lint -e550 */\r
+/*lint -e754 */\r
+/*lint -e750 */\r
+/*lint -e528 */\r
+/*lint -e751 */\r
+\r
+\r
+/** @addtogroup CMSIS_CM3_core_definitions CM3 Core Definitions\r
+ This file defines all structures and symbols for CMSIS core:\r
+ - CMSIS version number\r
+ - Cortex-M core registers and bitfields\r
+ - Cortex-M core peripheral base address\r
+ @{\r
+ */\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif \r
+\r
+#define __CM3_CMSIS_VERSION_MAIN (0x01) /*!< [31:16] CMSIS HAL main version */\r
+#define __CM3_CMSIS_VERSION_SUB (0x30) /*!< [15:0] CMSIS HAL sub version */\r
+#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */\r
+\r
+#define __CORTEX_M (0x03) /*!< Cortex core */\r
+\r
+#include <stdint.h> /* Include standard types */\r
+\r
+#if defined (__ICCARM__)\r
+ #include <intrinsics.h> /* IAR Intrinsics */\r
+#endif\r
+\r
+\r
+#ifndef __NVIC_PRIO_BITS\r
+ #define __NVIC_PRIO_BITS 4 /*!< standard definition for NVIC Priority Bits */\r
+#endif\r
+\r
+\r
+\r
+\r
+/**\r
+ * IO definitions\r
+ *\r
+ * define access restrictions to peripheral registers\r
+ */\r
+\r
+#ifdef __cplusplus\r
+ #define __I volatile /*!< defines 'read only' permissions */\r
+#else\r
+ #define __I volatile const /*!< defines 'read only' permissions */\r
+#endif\r
+#define __O volatile /*!< defines 'write only' permissions */\r
+#define __IO volatile /*!< defines 'read / write' permissions */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Register Abstraction\r
+ ******************************************************************************/\r
+/** @addtogroup CMSIS_CM3_core_register CMSIS CM3 Core Register\r
+ @{\r
+*/\r
+\r
+\r
+/** @addtogroup CMSIS_CM3_NVIC CMSIS CM3 NVIC\r
+ memory mapped structure for Nested Vectored Interrupt Controller (NVIC)\r
+ @{\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t ISER[8]; /*!< Offset: 0x000 Interrupt Set Enable Register */\r
+ uint32_t RESERVED0[24]; \r
+ __IO uint32_t ICER[8]; /*!< Offset: 0x080 Interrupt Clear Enable Register */\r
+ uint32_t RSERVED1[24]; \r
+ __IO uint32_t ISPR[8]; /*!< Offset: 0x100 Interrupt Set Pending Register */\r
+ uint32_t RESERVED2[24]; \r
+ __IO uint32_t ICPR[8]; /*!< Offset: 0x180 Interrupt Clear Pending Register */\r
+ uint32_t RESERVED3[24]; \r
+ __IO uint32_t IABR[8]; /*!< Offset: 0x200 Interrupt Active bit Register */\r
+ uint32_t RESERVED4[56]; \r
+ __IO uint8_t IP[240]; /*!< Offset: 0x300 Interrupt Priority Register (8Bit wide) */\r
+ uint32_t RESERVED5[644]; \r
+ __O uint32_t STIR; /*!< Offset: 0xE00 Software Trigger Interrupt Register */\r
+} NVIC_Type; \r
+/*@}*/ /* end of group CMSIS_CM3_NVIC */\r
+\r
+\r
+/** @addtogroup CMSIS_CM3_SCB CMSIS CM3 SCB\r
+ memory mapped structure for System Control Block (SCB)\r
+ @{\r
+ */\r
+typedef struct\r
+{\r
+ __I uint32_t CPUID; /*!< Offset: 0x00 CPU ID Base Register */\r
+ __IO uint32_t ICSR; /*!< Offset: 0x04 Interrupt Control State Register */\r
+ __IO uint32_t VTOR; /*!< Offset: 0x08 Vector Table Offset Register */\r
+ __IO uint32_t AIRCR; /*!< Offset: 0x0C Application Interrupt / Reset Control Register */\r
+ __IO uint32_t SCR; /*!< Offset: 0x10 System Control Register */\r
+ __IO uint32_t CCR; /*!< Offset: 0x14 Configuration Control Register */\r
+ __IO uint8_t SHP[12]; /*!< Offset: 0x18 System Handlers Priority Registers (4-7, 8-11, 12-15) */\r
+ __IO uint32_t SHCSR; /*!< Offset: 0x24 System Handler Control and State Register */\r
+ __IO uint32_t CFSR; /*!< Offset: 0x28 Configurable Fault Status Register */\r
+ __IO uint32_t HFSR; /*!< Offset: 0x2C Hard Fault Status Register */\r
+ __IO uint32_t DFSR; /*!< Offset: 0x30 Debug Fault Status Register */\r
+ __IO uint32_t MMFAR; /*!< Offset: 0x34 Mem Manage Address Register */\r
+ __IO uint32_t BFAR; /*!< Offset: 0x38 Bus Fault Address Register */\r
+ __IO uint32_t AFSR; /*!< Offset: 0x3C Auxiliary Fault Status Register */\r
+ __I uint32_t PFR[2]; /*!< Offset: 0x40 Processor Feature Register */\r
+ __I uint32_t DFR; /*!< Offset: 0x48 Debug Feature Register */\r
+ __I uint32_t ADR; /*!< Offset: 0x4C Auxiliary Feature Register */\r
+ __I uint32_t MMFR[4]; /*!< Offset: 0x50 Memory Model Feature Register */\r
+ __I uint32_t ISAR[5]; /*!< Offset: 0x60 ISA Feature Register */\r
+} SCB_Type; \r
+\r
+/* SCB CPUID Register Definitions */\r
+#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */\r
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFul << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */\r
+\r
+#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */\r
+#define SCB_CPUID_VARIANT_Msk (0xFul << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */\r
+\r
+#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */\r
+#define SCB_CPUID_PARTNO_Msk (0xFFFul << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */\r
+\r
+#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */\r
+#define SCB_CPUID_REVISION_Msk (0xFul << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */\r
+\r
+/* SCB Interrupt Control State Register Definitions */\r
+#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */\r
+#define SCB_ICSR_NMIPENDSET_Msk (1ul << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */\r
+#define SCB_ICSR_PENDSVSET_Msk (1ul << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */\r
+#define SCB_ICSR_PENDSVCLR_Msk (1ul << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */\r
+\r
+#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */\r
+#define SCB_ICSR_PENDSTSET_Msk (1ul << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */\r
+\r
+#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */\r
+#define SCB_ICSR_PENDSTCLR_Msk (1ul << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */\r
+\r
+#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */\r
+#define SCB_ICSR_ISRPREEMPT_Msk (1ul << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */\r
+\r
+#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */\r
+#define SCB_ICSR_ISRPENDING_Msk (1ul << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */\r
+\r
+#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */\r
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFul << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */\r
+\r
+#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */\r
+#define SCB_ICSR_RETTOBASE_Msk (1ul << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */\r
+\r
+#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */\r
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFul << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */\r
+\r
+/* SCB Interrupt Control State Register Definitions */\r
+#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */\r
+#define SCB_VTOR_TBLBASE_Msk (0x1FFul << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */\r
+\r
+#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */\r
+#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFul << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */\r
+\r
+/* SCB Application Interrupt and Reset Control Register Definitions */\r
+#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */\r
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFul << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */\r
+\r
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */\r
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFul << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */\r
+\r
+#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */\r
+#define SCB_AIRCR_ENDIANESS_Msk (1ul << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */\r
+\r
+#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */\r
+#define SCB_AIRCR_PRIGROUP_Msk (7ul << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */\r
+\r
+#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */\r
+#define SCB_AIRCR_SYSRESETREQ_Msk (1ul << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */\r
+\r
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */\r
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1ul << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r
+\r
+#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */\r
+#define SCB_AIRCR_VECTRESET_Msk (1ul << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */\r
+\r
+/* SCB System Control Register Definitions */\r
+#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */\r
+#define SCB_SCR_SEVONPEND_Msk (1ul << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */\r
+\r
+#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */\r
+#define SCB_SCR_SLEEPDEEP_Msk (1ul << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */\r
+\r
+#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */\r
+#define SCB_SCR_SLEEPONEXIT_Msk (1ul << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */\r
+\r
+/* SCB Configuration Control Register Definitions */\r
+#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */\r
+#define SCB_CCR_STKALIGN_Msk (1ul << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */\r
+\r
+#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */\r
+#define SCB_CCR_BFHFNMIGN_Msk (1ul << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */\r
+\r
+#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */\r
+#define SCB_CCR_DIV_0_TRP_Msk (1ul << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */\r
+\r
+#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */\r
+#define SCB_CCR_UNALIGN_TRP_Msk (1ul << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */\r
+\r
+#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */\r
+#define SCB_CCR_USERSETMPEND_Msk (1ul << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */\r
+\r
+#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */\r
+#define SCB_CCR_NONBASETHRDENA_Msk (1ul << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */\r
+\r
+/* SCB System Handler Control and State Register Definitions */\r
+#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */\r
+#define SCB_SHCSR_USGFAULTENA_Msk (1ul << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */\r
+#define SCB_SHCSR_BUSFAULTENA_Msk (1ul << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */\r
+#define SCB_SHCSR_MEMFAULTENA_Msk (1ul << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */\r
+#define SCB_SHCSR_SVCALLPENDED_Msk (1ul << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */\r
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1ul << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */\r
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1ul << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */\r
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1ul << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */\r
+#define SCB_SHCSR_SYSTICKACT_Msk (1ul << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */\r
+\r
+#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */\r
+#define SCB_SHCSR_PENDSVACT_Msk (1ul << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */\r
+\r
+#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */\r
+#define SCB_SHCSR_MONITORACT_Msk (1ul << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */\r
+\r
+#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */\r
+#define SCB_SHCSR_SVCALLACT_Msk (1ul << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */\r
+ \r
+#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */\r
+#define SCB_SHCSR_USGFAULTACT_Msk (1ul << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */\r
+#define SCB_SHCSR_BUSFAULTACT_Msk (1ul << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */\r
+#define SCB_SHCSR_MEMFAULTACT_Msk (1ul << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */\r
+\r
+/* SCB Configurable Fault Status Registers Definitions */\r
+#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */\r
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFul << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */\r
+\r
+#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */\r
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFul << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */\r
+\r
+#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */\r
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFul << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */\r
+\r
+/* SCB Hard Fault Status Registers Definitions */\r
+#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */\r
+#define SCB_HFSR_DEBUGEVT_Msk (1ul << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */\r
+\r
+#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */\r
+#define SCB_HFSR_FORCED_Msk (1ul << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */\r
+\r
+#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */\r
+#define SCB_HFSR_VECTTBL_Msk (1ul << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */\r
+\r
+/* SCB Debug Fault Status Register Definitions */\r
+#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */\r
+#define SCB_DFSR_EXTERNAL_Msk (1ul << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */\r
+\r
+#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */\r
+#define SCB_DFSR_VCATCH_Msk (1ul << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */\r
+\r
+#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */\r
+#define SCB_DFSR_DWTTRAP_Msk (1ul << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */\r
+\r
+#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */\r
+#define SCB_DFSR_BKPT_Msk (1ul << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */\r
+\r
+#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */\r
+#define SCB_DFSR_HALTED_Msk (1ul << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */\r
+/*@}*/ /* end of group CMSIS_CM3_SCB */\r
+\r
+\r
+/** @addtogroup CMSIS_CM3_SysTick CMSIS CM3 SysTick\r
+ memory mapped structure for SysTick\r
+ @{\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t CTRL; /*!< Offset: 0x00 SysTick Control and Status Register */\r
+ __IO uint32_t LOAD; /*!< Offset: 0x04 SysTick Reload Value Register */\r
+ __IO uint32_t VAL; /*!< Offset: 0x08 SysTick Current Value Register */\r
+ __I uint32_t CALIB; /*!< Offset: 0x0C SysTick Calibration Register */\r
+} SysTick_Type;\r
+\r
+/* SysTick Control / Status Register Definitions */\r
+#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */\r
+#define SysTick_CTRL_COUNTFLAG_Msk (1ul << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */\r
+\r
+#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */\r
+#define SysTick_CTRL_CLKSOURCE_Msk (1ul << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */\r
+\r
+#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */\r
+#define SysTick_CTRL_TICKINT_Msk (1ul << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */\r
+\r
+#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */\r
+#define SysTick_CTRL_ENABLE_Msk (1ul << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */\r
+\r
+/* SysTick Reload Register Definitions */\r
+#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */\r
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFul << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */\r
+\r
+/* SysTick Current Register Definitions */\r
+#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */\r
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */\r
+\r
+/* SysTick Calibration Register Definitions */\r
+#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */\r
+#define SysTick_CALIB_NOREF_Msk (1ul << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */\r
+\r
+#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */\r
+#define SysTick_CALIB_SKEW_Msk (1ul << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */\r
+\r
+#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */\r
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */\r
+/*@}*/ /* end of group CMSIS_CM3_SysTick */\r
+\r
+\r
+/** @addtogroup CMSIS_CM3_ITM CMSIS CM3 ITM\r
+ memory mapped structure for Instrumentation Trace Macrocell (ITM)\r
+ @{\r
+ */\r
+typedef struct\r
+{\r
+ __O union \r
+ {\r
+ __O uint8_t u8; /*!< Offset: ITM Stimulus Port 8-bit */\r
+ __O uint16_t u16; /*!< Offset: ITM Stimulus Port 16-bit */\r
+ __O uint32_t u32; /*!< Offset: ITM Stimulus Port 32-bit */\r
+ } PORT [32]; /*!< Offset: 0x00 ITM Stimulus Port Registers */\r
+ uint32_t RESERVED0[864]; \r
+ __IO uint32_t TER; /*!< Offset: ITM Trace Enable Register */\r
+ uint32_t RESERVED1[15]; \r
+ __IO uint32_t TPR; /*!< Offset: ITM Trace Privilege Register */\r
+ uint32_t RESERVED2[15]; \r
+ __IO uint32_t TCR; /*!< Offset: ITM Trace Control Register */\r
+ uint32_t RESERVED3[29]; \r
+ __IO uint32_t IWR; /*!< Offset: ITM Integration Write Register */\r
+ __IO uint32_t IRR; /*!< Offset: ITM Integration Read Register */\r
+ __IO uint32_t IMCR; /*!< Offset: ITM Integration Mode Control Register */\r
+ uint32_t RESERVED4[43]; \r
+ __IO uint32_t LAR; /*!< Offset: ITM Lock Access Register */\r
+ __IO uint32_t LSR; /*!< Offset: ITM Lock Status Register */\r
+ uint32_t RESERVED5[6]; \r
+ __I uint32_t PID4; /*!< Offset: ITM Peripheral Identification Register #4 */\r
+ __I uint32_t PID5; /*!< Offset: ITM Peripheral Identification Register #5 */\r
+ __I uint32_t PID6; /*!< Offset: ITM Peripheral Identification Register #6 */\r
+ __I uint32_t PID7; /*!< Offset: ITM Peripheral Identification Register #7 */\r
+ __I uint32_t PID0; /*!< Offset: ITM Peripheral Identification Register #0 */\r
+ __I uint32_t PID1; /*!< Offset: ITM Peripheral Identification Register #1 */\r
+ __I uint32_t PID2; /*!< Offset: ITM Peripheral Identification Register #2 */\r
+ __I uint32_t PID3; /*!< Offset: ITM Peripheral Identification Register #3 */\r
+ __I uint32_t CID0; /*!< Offset: ITM Component Identification Register #0 */\r
+ __I uint32_t CID1; /*!< Offset: ITM Component Identification Register #1 */\r
+ __I uint32_t CID2; /*!< Offset: ITM Component Identification Register #2 */\r
+ __I uint32_t CID3; /*!< Offset: ITM Component Identification Register #3 */\r
+} ITM_Type; \r
+\r
+/* ITM Trace Privilege Register Definitions */\r
+#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */\r
+#define ITM_TPR_PRIVMASK_Msk (0xFul << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */\r
+\r
+/* ITM Trace Control Register Definitions */\r
+#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */\r
+#define ITM_TCR_BUSY_Msk (1ul << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */\r
+\r
+#define ITM_TCR_ATBID_Pos 16 /*!< ITM TCR: ATBID Position */\r
+#define ITM_TCR_ATBID_Msk (0x7Ful << ITM_TCR_ATBID_Pos) /*!< ITM TCR: ATBID Mask */\r
+\r
+#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */\r
+#define ITM_TCR_TSPrescale_Msk (3ul << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */\r
+\r
+#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */\r
+#define ITM_TCR_SWOENA_Msk (1ul << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */\r
+\r
+#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */\r
+#define ITM_TCR_DWTENA_Msk (1ul << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */\r
+\r
+#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */\r
+#define ITM_TCR_SYNCENA_Msk (1ul << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */\r
+\r
+#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */\r
+#define ITM_TCR_TSENA_Msk (1ul << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */\r
+\r
+#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */\r
+#define ITM_TCR_ITMENA_Msk (1ul << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */\r
+\r
+/* ITM Integration Write Register Definitions */\r
+#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */\r
+#define ITM_IWR_ATVALIDM_Msk (1ul << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */\r
+\r
+/* ITM Integration Read Register Definitions */\r
+#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */\r
+#define ITM_IRR_ATREADYM_Msk (1ul << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */\r
+\r
+/* ITM Integration Mode Control Register Definitions */\r
+#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */\r
+#define ITM_IMCR_INTEGRATION_Msk (1ul << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */\r
+\r
+/* ITM Lock Status Register Definitions */\r
+#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */\r
+#define ITM_LSR_ByteAcc_Msk (1ul << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */\r
+\r
+#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */\r
+#define ITM_LSR_Access_Msk (1ul << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */\r
+\r
+#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */\r
+#define ITM_LSR_Present_Msk (1ul << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */\r
+/*@}*/ /* end of group CMSIS_CM3_ITM */\r
+\r
+\r
+/** @addtogroup CMSIS_CM3_InterruptType CMSIS CM3 Interrupt Type\r
+ memory mapped structure for Interrupt Type\r
+ @{\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t RESERVED0;\r
+ __I uint32_t ICTR; /*!< Offset: 0x04 Interrupt Control Type Register */\r
+#if ((defined __CM3_REV) && (__CM3_REV >= 0x200))\r
+ __IO uint32_t ACTLR; /*!< Offset: 0x08 Auxiliary Control Register */\r
+#else\r
+ uint32_t RESERVED1;\r
+#endif\r
+} InterruptType_Type;\r
+\r
+/* Interrupt Controller Type Register Definitions */\r
+#define InterruptType_ICTR_INTLINESNUM_Pos 0 /*!< InterruptType ICTR: INTLINESNUM Position */\r
+#define InterruptType_ICTR_INTLINESNUM_Msk (0x1Ful << InterruptType_ICTR_INTLINESNUM_Pos) /*!< InterruptType ICTR: INTLINESNUM Mask */\r
+\r
+/* Auxiliary Control Register Definitions */\r
+#define InterruptType_ACTLR_DISFOLD_Pos 2 /*!< InterruptType ACTLR: DISFOLD Position */\r
+#define InterruptType_ACTLR_DISFOLD_Msk (1ul << InterruptType_ACTLR_DISFOLD_Pos) /*!< InterruptType ACTLR: DISFOLD Mask */\r
+\r
+#define InterruptType_ACTLR_DISDEFWBUF_Pos 1 /*!< InterruptType ACTLR: DISDEFWBUF Position */\r
+#define InterruptType_ACTLR_DISDEFWBUF_Msk (1ul << InterruptType_ACTLR_DISDEFWBUF_Pos) /*!< InterruptType ACTLR: DISDEFWBUF Mask */\r
+\r
+#define InterruptType_ACTLR_DISMCYCINT_Pos 0 /*!< InterruptType ACTLR: DISMCYCINT Position */\r
+#define InterruptType_ACTLR_DISMCYCINT_Msk (1ul << InterruptType_ACTLR_DISMCYCINT_Pos) /*!< InterruptType ACTLR: DISMCYCINT Mask */\r
+/*@}*/ /* end of group CMSIS_CM3_InterruptType */\r
+\r
+\r
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1)\r
+/** @addtogroup CMSIS_CM3_MPU CMSIS CM3 MPU\r
+ memory mapped structure for Memory Protection Unit (MPU)\r
+ @{\r
+ */\r
+typedef struct\r
+{\r
+ __I uint32_t TYPE; /*!< Offset: 0x00 MPU Type Register */\r
+ __IO uint32_t CTRL; /*!< Offset: 0x04 MPU Control Register */\r
+ __IO uint32_t RNR; /*!< Offset: 0x08 MPU Region RNRber Register */\r
+ __IO uint32_t RBAR; /*!< Offset: 0x0C MPU Region Base Address Register */\r
+ __IO uint32_t RASR; /*!< Offset: 0x10 MPU Region Attribute and Size Register */\r
+ __IO uint32_t RBAR_A1; /*!< Offset: 0x14 MPU Alias 1 Region Base Address Register */\r
+ __IO uint32_t RASR_A1; /*!< Offset: 0x18 MPU Alias 1 Region Attribute and Size Register */\r
+ __IO uint32_t RBAR_A2; /*!< Offset: 0x1C MPU Alias 2 Region Base Address Register */\r
+ __IO uint32_t RASR_A2; /*!< Offset: 0x20 MPU Alias 2 Region Attribute and Size Register */\r
+ __IO uint32_t RBAR_A3; /*!< Offset: 0x24 MPU Alias 3 Region Base Address Register */\r
+ __IO uint32_t RASR_A3; /*!< Offset: 0x28 MPU Alias 3 Region Attribute and Size Register */\r
+} MPU_Type; \r
+\r
+/* MPU Type Register */\r
+#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */\r
+#define MPU_TYPE_IREGION_Msk (0xFFul << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */\r
+\r
+#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */\r
+#define MPU_TYPE_DREGION_Msk (0xFFul << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */\r
+\r
+#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */\r
+#define MPU_TYPE_SEPARATE_Msk (1ul << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */\r
+\r
+/* MPU Control Register */\r
+#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */\r
+#define MPU_CTRL_PRIVDEFENA_Msk (1ul << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */\r
+\r
+#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */\r
+#define MPU_CTRL_HFNMIENA_Msk (1ul << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */\r
+\r
+#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */\r
+#define MPU_CTRL_ENABLE_Msk (1ul << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */\r
+\r
+/* MPU Region Number Register */\r
+#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */\r
+#define MPU_RNR_REGION_Msk (0xFFul << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */\r
+\r
+/* MPU Region Base Address Register */\r
+#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */\r
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFul << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */\r
+\r
+#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */\r
+#define MPU_RBAR_VALID_Msk (1ul << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */\r
+\r
+#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */\r
+#define MPU_RBAR_REGION_Msk (0xFul << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */\r
+\r
+/* MPU Region Attribute and Size Register */\r
+#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: XN Position */\r
+#define MPU_RASR_XN_Msk (1ul << MPU_RASR_XN_Pos) /*!< MPU RASR: XN Mask */\r
+\r
+#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: AP Position */\r
+#define MPU_RASR_AP_Msk (7ul << MPU_RASR_AP_Pos) /*!< MPU RASR: AP Mask */\r
+\r
+#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: TEX Position */\r
+#define MPU_RASR_TEX_Msk (7ul << MPU_RASR_TEX_Pos) /*!< MPU RASR: TEX Mask */\r
+\r
+#define MPU_RASR_S_Pos 18 /*!< MPU RASR: Shareable bit Position */\r
+#define MPU_RASR_S_Msk (1ul << MPU_RASR_S_Pos) /*!< MPU RASR: Shareable bit Mask */\r
+\r
+#define MPU_RASR_C_Pos 17 /*!< MPU RASR: Cacheable bit Position */\r
+#define MPU_RASR_C_Msk (1ul << MPU_RASR_C_Pos) /*!< MPU RASR: Cacheable bit Mask */\r
+\r
+#define MPU_RASR_B_Pos 16 /*!< MPU RASR: Bufferable bit Position */\r
+#define MPU_RASR_B_Msk (1ul << MPU_RASR_B_Pos) /*!< MPU RASR: Bufferable bit Mask */\r
+\r
+#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */\r
+#define MPU_RASR_SRD_Msk (0xFFul << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */\r
+\r
+#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */\r
+#define MPU_RASR_SIZE_Msk (0x1Ful << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */\r
+\r
+#define MPU_RASR_ENA_Pos 0 /*!< MPU RASR: Region enable bit Position */\r
+#define MPU_RASR_ENA_Msk (0x1Ful << MPU_RASR_ENA_Pos) /*!< MPU RASR: Region enable bit Disable Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_CM3_MPU */\r
+#endif\r
+\r
+\r
+/** @addtogroup CMSIS_CM3_CoreDebug CMSIS CM3 Core Debug\r
+ memory mapped structure for Core Debug Register\r
+ @{\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t DHCSR; /*!< Offset: 0x00 Debug Halting Control and Status Register */\r
+ __O uint32_t DCRSR; /*!< Offset: 0x04 Debug Core Register Selector Register */\r
+ __IO uint32_t DCRDR; /*!< Offset: 0x08 Debug Core Register Data Register */\r
+ __IO uint32_t DEMCR; /*!< Offset: 0x0C Debug Exception and Monitor Control Register */\r
+} CoreDebug_Type;\r
+\r
+/* Debug Halting Control and Status Register */\r
+#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */\r
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFul << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */\r
+\r
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */\r
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1ul << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */\r
+\r
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */\r
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1ul << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */\r
+\r
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */\r
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1ul << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */\r
+\r
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */\r
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1ul << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */\r
+\r
+#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */\r
+#define CoreDebug_DHCSR_S_HALT_Msk (1ul << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */\r
+\r
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */\r
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1ul << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */\r
+\r
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */\r
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1ul << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */\r
+\r
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */\r
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1ul << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */\r
+\r
+#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */\r
+#define CoreDebug_DHCSR_C_STEP_Msk (1ul << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */\r
+\r
+#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */\r
+#define CoreDebug_DHCSR_C_HALT_Msk (1ul << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */\r
+\r
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */\r
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1ul << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */\r
+\r
+/* Debug Core Register Selector Register */\r
+#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */\r
+#define CoreDebug_DCRSR_REGWnR_Msk (1ul << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */\r
+\r
+#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */\r
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1Ful << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */\r
+\r
+/* Debug Exception and Monitor Control Register */\r
+#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */\r
+#define CoreDebug_DEMCR_TRCENA_Msk (1ul << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */\r
+#define CoreDebug_DEMCR_MON_REQ_Msk (1ul << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */\r
+#define CoreDebug_DEMCR_MON_STEP_Msk (1ul << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */\r
+#define CoreDebug_DEMCR_MON_PEND_Msk (1ul << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */\r
+#define CoreDebug_DEMCR_MON_EN_Msk (1ul << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */\r
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1ul << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */\r
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1ul << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */\r
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1ul << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */\r
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1ul << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */\r
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1ul << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */\r
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1ul << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */\r
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1ul << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */\r
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1ul << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */\r
+/*@}*/ /* end of group CMSIS_CM3_CoreDebug */\r
+\r
+\r
+/* Memory mapping of Cortex-M3 Hardware */\r
+#define SCS_BASE (0xE000E000) /*!< System Control Space Base Address */\r
+#define ITM_BASE (0xE0000000) /*!< ITM Base Address */\r
+#define CoreDebug_BASE (0xE000EDF0) /*!< Core Debug Base Address */\r
+#define SysTick_BASE (SCS_BASE + 0x0010) /*!< SysTick Base Address */\r
+#define NVIC_BASE (SCS_BASE + 0x0100) /*!< NVIC Base Address */\r
+#define SCB_BASE (SCS_BASE + 0x0D00) /*!< System Control Block Base Address */\r
+\r
+#define InterruptType ((InterruptType_Type *) SCS_BASE) /*!< Interrupt Type Register */\r
+#define SCB ((SCB_Type *) SCB_BASE) /*!< SCB configuration struct */\r
+#define SysTick ((SysTick_Type *) SysTick_BASE) /*!< SysTick configuration struct */\r
+#define NVIC ((NVIC_Type *) NVIC_BASE) /*!< NVIC configuration struct */\r
+#define ITM ((ITM_Type *) ITM_BASE) /*!< ITM configuration struct */\r
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */\r
+\r
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1)\r
+ #define MPU_BASE (SCS_BASE + 0x0D90) /*!< Memory Protection Unit */\r
+ #define MPU ((MPU_Type*) MPU_BASE) /*!< Memory Protection Unit */\r
+#endif\r
+\r
+/*@}*/ /* end of group CMSIS_CM3_core_register */\r
+\r
+\r
+/*******************************************************************************\r
+ * Hardware Abstraction Layer\r
+ ******************************************************************************/\r
+\r
+#if defined ( __CC_ARM )\r
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */\r
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */\r
+\r
+#elif defined ( __ICCARM__ )\r
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */\r
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */\r
+\r
+#elif defined ( __GNUC__ )\r
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */\r
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */\r
+\r
+#elif defined ( __TASKING__ )\r
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */\r
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */\r
+\r
+#endif\r
+\r
+\r
+/* ################### Compiler specific Intrinsics ########################### */\r
+\r
+#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/\r
+/* ARM armcc specific functions */\r
+\r
+#define __enable_fault_irq __enable_fiq\r
+#define __disable_fault_irq __disable_fiq\r
+\r
+#define __NOP __nop\r
+#define __WFI __wfi\r
+#define __WFE __wfe\r
+#define __SEV __sev\r
+#define __ISB() __isb(0)\r
+#define __DSB() __dsb(0)\r
+#define __DMB() __dmb(0)\r
+#define __REV __rev\r
+#define __RBIT __rbit\r
+#define __LDREXB(ptr) ((unsigned char ) __ldrex(ptr))\r
+#define __LDREXH(ptr) ((unsigned short) __ldrex(ptr))\r
+#define __LDREXW(ptr) ((unsigned int ) __ldrex(ptr))\r
+#define __STREXB(value, ptr) __strex(value, ptr)\r
+#define __STREXH(value, ptr) __strex(value, ptr)\r
+#define __STREXW(value, ptr) __strex(value, ptr)\r
+\r
+\r
+/* intrinsic unsigned long long __ldrexd(volatile void *ptr) */\r
+/* intrinsic int __strexd(unsigned long long val, volatile void *ptr) */\r
+/* intrinsic void __enable_irq(); */\r
+/* intrinsic void __disable_irq(); */\r
+\r
+\r
+/**\r
+ * @brief Return the Process Stack Pointer\r
+ *\r
+ * @return ProcessStackPointer\r
+ *\r
+ * Return the actual process stack pointer\r
+ */\r
+extern uint32_t __get_PSP(void);\r
+\r
+/**\r
+ * @brief Set the Process Stack Pointer\r
+ *\r
+ * @param topOfProcStack Process Stack Pointer\r
+ *\r
+ * Assign the value ProcessStackPointer to the MSP \r
+ * (process stack pointer) Cortex processor register\r
+ */\r
+extern void __set_PSP(uint32_t topOfProcStack);\r
+\r
+/**\r
+ * @brief Return the Main Stack Pointer\r
+ *\r
+ * @return Main Stack Pointer\r
+ *\r
+ * Return the current value of the MSP (main stack pointer)\r
+ * Cortex processor register\r
+ */\r
+extern uint32_t __get_MSP(void);\r
+\r
+/**\r
+ * @brief Set the Main Stack Pointer\r
+ *\r
+ * @param topOfMainStack Main Stack Pointer\r
+ *\r
+ * Assign the value mainStackPointer to the MSP \r
+ * (main stack pointer) Cortex processor register\r
+ */\r
+extern void __set_MSP(uint32_t topOfMainStack);\r
+\r
+/**\r
+ * @brief Reverse byte order in unsigned short value\r
+ *\r
+ * @param value value to reverse\r
+ * @return reversed value\r
+ *\r
+ * Reverse byte order in unsigned short value\r
+ */\r
+extern uint32_t __REV16(uint16_t value);\r
+\r
+/**\r
+ * @brief Reverse byte order in signed short value with sign extension to integer\r
+ *\r
+ * @param value value to reverse\r
+ * @return reversed value\r
+ *\r
+ * Reverse byte order in signed short value with sign extension to integer\r
+ */\r
+extern int32_t __REVSH(int16_t value);\r
+\r
+\r
+#if (__ARMCC_VERSION < 400000)\r
+\r
+/**\r
+ * @brief Remove the exclusive lock created by ldrex\r
+ *\r
+ * Removes the exclusive lock which is created by ldrex.\r
+ */\r
+extern void __CLREX(void);\r
+\r
+/**\r
+ * @brief Return the Base Priority value\r
+ *\r
+ * @return BasePriority\r
+ *\r
+ * Return the content of the base priority register\r
+ */\r
+extern uint32_t __get_BASEPRI(void);\r
+\r
+/**\r
+ * @brief Set the Base Priority value\r
+ *\r
+ * @param basePri BasePriority\r
+ *\r
+ * Set the base priority register\r
+ */\r
+extern void __set_BASEPRI(uint32_t basePri);\r
+\r
+/**\r
+ * @brief Return the Priority Mask value\r
+ *\r
+ * @return PriMask\r
+ *\r
+ * Return state of the priority mask bit from the priority mask register\r
+ */\r
+extern uint32_t __get_PRIMASK(void);\r
+\r
+/**\r
+ * @brief Set the Priority Mask value\r
+ *\r
+ * @param priMask PriMask\r
+ *\r
+ * Set the priority mask bit in the priority mask register\r
+ */\r
+extern void __set_PRIMASK(uint32_t priMask);\r
+\r
+/**\r
+ * @brief Return the Fault Mask value\r
+ *\r
+ * @return FaultMask\r
+ *\r
+ * Return the content of the fault mask register\r
+ */\r
+extern uint32_t __get_FAULTMASK(void);\r
+\r
+/**\r
+ * @brief Set the Fault Mask value\r
+ *\r
+ * @param faultMask faultMask value\r
+ *\r
+ * Set the fault mask register\r
+ */\r
+extern void __set_FAULTMASK(uint32_t faultMask);\r
+\r
+/**\r
+ * @brief Return the Control Register value\r
+ * \r
+ * @return Control value\r
+ *\r
+ * Return the content of the control register\r
+ */\r
+extern uint32_t __get_CONTROL(void);\r
+\r
+/**\r
+ * @brief Set the Control Register value\r
+ *\r
+ * @param control Control value\r
+ *\r
+ * Set the control register\r
+ */\r
+extern void __set_CONTROL(uint32_t control);\r
+\r
+#else /* (__ARMCC_VERSION >= 400000) */\r
+\r
+/**\r
+ * @brief Remove the exclusive lock created by ldrex\r
+ *\r
+ * Removes the exclusive lock which is created by ldrex.\r
+ */\r
+#define __CLREX __clrex\r
+\r
+/**\r
+ * @brief Return the Base Priority value\r
+ *\r
+ * @return BasePriority\r
+ *\r
+ * Return the content of the base priority register\r
+ */\r
+static __INLINE uint32_t __get_BASEPRI(void)\r
+{\r
+ register uint32_t __regBasePri __ASM("basepri");\r
+ return(__regBasePri);\r
+}\r
+\r
+/**\r
+ * @brief Set the Base Priority value\r
+ *\r
+ * @param basePri BasePriority\r
+ *\r
+ * Set the base priority register\r
+ */\r
+static __INLINE void __set_BASEPRI(uint32_t basePri)\r
+{\r
+ register uint32_t __regBasePri __ASM("basepri");\r
+ __regBasePri = (basePri & 0xff);\r
+}\r
+\r
+/**\r
+ * @brief Return the Priority Mask value\r
+ *\r
+ * @return PriMask\r
+ *\r
+ * Return state of the priority mask bit from the priority mask register\r
+ */\r
+static __INLINE uint32_t __get_PRIMASK(void)\r
+{\r
+ register uint32_t __regPriMask __ASM("primask");\r
+ return(__regPriMask);\r
+}\r
+\r
+/**\r
+ * @brief Set the Priority Mask value\r
+ *\r
+ * @param priMask PriMask\r
+ *\r
+ * Set the priority mask bit in the priority mask register\r
+ */\r
+static __INLINE void __set_PRIMASK(uint32_t priMask)\r
+{\r
+ register uint32_t __regPriMask __ASM("primask");\r
+ __regPriMask = (priMask);\r
+}\r
+\r
+/**\r
+ * @brief Return the Fault Mask value\r
+ *\r
+ * @return FaultMask\r
+ *\r
+ * Return the content of the fault mask register\r
+ */\r
+static __INLINE uint32_t __get_FAULTMASK(void)\r
+{\r
+ register uint32_t __regFaultMask __ASM("faultmask");\r
+ return(__regFaultMask);\r
+}\r
+\r
+/**\r
+ * @brief Set the Fault Mask value\r
+ *\r
+ * @param faultMask faultMask value\r
+ *\r
+ * Set the fault mask register\r
+ */\r
+static __INLINE void __set_FAULTMASK(uint32_t faultMask)\r
+{\r
+ register uint32_t __regFaultMask __ASM("faultmask");\r
+ __regFaultMask = (faultMask & 1);\r
+}\r
+\r
+/**\r
+ * @brief Return the Control Register value\r
+ * \r
+ * @return Control value\r
+ *\r
+ * Return the content of the control register\r
+ */\r
+static __INLINE uint32_t __get_CONTROL(void)\r
+{\r
+ register uint32_t __regControl __ASM("control");\r
+ return(__regControl);\r
+}\r
+\r
+/**\r
+ * @brief Set the Control Register value\r
+ *\r
+ * @param control Control value\r
+ *\r
+ * Set the control register\r
+ */\r
+static __INLINE void __set_CONTROL(uint32_t control)\r
+{\r
+ register uint32_t __regControl __ASM("control");\r
+ __regControl = control;\r
+}\r
+\r
+#endif /* __ARMCC_VERSION */ \r
+\r
+\r
+\r
+#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/\r
+/* IAR iccarm specific functions */\r
+\r
+#define __enable_irq __enable_interrupt /*!< global Interrupt enable */\r
+#define __disable_irq __disable_interrupt /*!< global Interrupt disable */\r
+\r
+static __INLINE void __enable_fault_irq() { __ASM ("cpsie f"); }\r
+static __INLINE void __disable_fault_irq() { __ASM ("cpsid f"); }\r
+\r
+#define __NOP __no_operation /*!< no operation intrinsic in IAR Compiler */ \r
+static __INLINE void __WFI() { __ASM ("wfi"); }\r
+static __INLINE void __WFE() { __ASM ("wfe"); }\r
+static __INLINE void __SEV() { __ASM ("sev"); }\r
+static __INLINE void __CLREX() { __ASM ("clrex"); }\r
+\r
+/* intrinsic void __ISB(void) */\r
+/* intrinsic void __DSB(void) */\r
+/* intrinsic void __DMB(void) */\r
+/* intrinsic void __set_PRIMASK(); */\r
+/* intrinsic void __get_PRIMASK(); */\r
+/* intrinsic void __set_FAULTMASK(); */\r
+/* intrinsic void __get_FAULTMASK(); */\r
+/* intrinsic uint32_t __REV(uint32_t value); */\r
+/* intrinsic uint32_t __REVSH(uint32_t value); */\r
+/* intrinsic unsigned long __STREX(unsigned long, unsigned long); */\r
+/* intrinsic unsigned long __LDREX(unsigned long *); */\r
+\r
+\r
+/**\r
+ * @brief Return the Process Stack Pointer\r
+ *\r
+ * @return ProcessStackPointer\r
+ *\r
+ * Return the actual process stack pointer\r
+ */\r
+extern uint32_t __get_PSP(void);\r
+\r
+/**\r
+ * @brief Set the Process Stack Pointer\r
+ *\r
+ * @param topOfProcStack Process Stack Pointer\r
+ *\r
+ * Assign the value ProcessStackPointer to the MSP \r
+ * (process stack pointer) Cortex processor register\r
+ */\r
+extern void __set_PSP(uint32_t topOfProcStack);\r
+\r
+/**\r
+ * @brief Return the Main Stack Pointer\r
+ *\r
+ * @return Main Stack Pointer\r
+ *\r
+ * Return the current value of the MSP (main stack pointer)\r
+ * Cortex processor register\r
+ */\r
+extern uint32_t __get_MSP(void);\r
+\r
+/**\r
+ * @brief Set the Main Stack Pointer\r
+ *\r
+ * @param topOfMainStack Main Stack Pointer\r
+ *\r
+ * Assign the value mainStackPointer to the MSP \r
+ * (main stack pointer) Cortex processor register\r
+ */\r
+extern void __set_MSP(uint32_t topOfMainStack);\r
+\r
+/**\r
+ * @brief Reverse byte order in unsigned short value\r
+ *\r
+ * @param value value to reverse\r
+ * @return reversed value\r
+ *\r
+ * Reverse byte order in unsigned short value\r
+ */\r
+extern uint32_t __REV16(uint16_t value);\r
+\r
+/**\r
+ * @brief Reverse bit order of value\r
+ *\r
+ * @param value value to reverse\r
+ * @return reversed value\r
+ *\r
+ * Reverse bit order of value\r
+ */\r
+extern uint32_t __RBIT(uint32_t value);\r
+\r
+/**\r
+ * @brief LDR Exclusive (8 bit)\r
+ *\r
+ * @param *addr address pointer\r
+ * @return value of (*address)\r
+ *\r
+ * Exclusive LDR command for 8 bit values)\r
+ */\r
+extern uint8_t __LDREXB(uint8_t *addr);\r
+\r
+/**\r
+ * @brief LDR Exclusive (16 bit)\r
+ *\r
+ * @param *addr address pointer\r
+ * @return value of (*address)\r
+ *\r
+ * Exclusive LDR command for 16 bit values\r
+ */\r
+extern uint16_t __LDREXH(uint16_t *addr);\r
+\r
+/**\r
+ * @brief LDR Exclusive (32 bit)\r
+ *\r
+ * @param *addr address pointer\r
+ * @return value of (*address)\r
+ *\r
+ * Exclusive LDR command for 32 bit values\r
+ */\r
+extern uint32_t __LDREXW(uint32_t *addr);\r
+\r
+/**\r
+ * @brief STR Exclusive (8 bit)\r
+ *\r
+ * @param value value to store\r
+ * @param *addr address pointer\r
+ * @return successful / failed\r
+ *\r
+ * Exclusive STR command for 8 bit values\r
+ */\r
+extern uint32_t __STREXB(uint8_t value, uint8_t *addr);\r
+\r
+/**\r
+ * @brief STR Exclusive (16 bit)\r
+ *\r
+ * @param value value to store\r
+ * @param *addr address pointer\r
+ * @return successful / failed\r
+ *\r
+ * Exclusive STR command for 16 bit values\r
+ */\r
+extern uint32_t __STREXH(uint16_t value, uint16_t *addr);\r
+\r
+/**\r
+ * @brief STR Exclusive (32 bit)\r
+ *\r
+ * @param value value to store\r
+ * @param *addr address pointer\r
+ * @return successful / failed\r
+ *\r
+ * Exclusive STR command for 32 bit values\r
+ */\r
+extern uint32_t __STREXW(uint32_t value, uint32_t *addr);\r
+\r
+\r
+\r
+#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/\r
+/* GNU gcc specific functions */\r
+\r
+static __INLINE void __enable_irq(void) { __ASM volatile ("cpsie i"); }\r
+static __INLINE void __disable_irq(void) { __ASM volatile ("cpsid i"); }\r
+\r
+static __INLINE void __enable_fault_irq(void) { __ASM volatile ("cpsie f"); }\r
+static __INLINE void __disable_fault_irq(void) { __ASM volatile ("cpsid f"); }\r
+\r
+static __INLINE void __NOP(void) { __ASM volatile ("nop"); }\r
+static __INLINE void __WFI(void) { __ASM volatile ("wfi"); }\r
+static __INLINE void __WFE(void) { __ASM volatile ("wfe"); }\r
+static __INLINE void __SEV(void) { __ASM volatile ("sev"); }\r
+static __INLINE void __ISB(void) { __ASM volatile ("isb"); }\r
+static __INLINE void __DSB(void) { __ASM volatile ("dsb"); }\r
+static __INLINE void __DMB(void) { __ASM volatile ("dmb"); }\r
+static __INLINE void __CLREX(void) { __ASM volatile ("clrex"); }\r
+\r
+\r
+/**\r
+ * @brief Return the Process Stack Pointer\r
+ *\r
+ * @return ProcessStackPointer\r
+ *\r
+ * Return the actual process stack pointer\r
+ */\r
+extern uint32_t __get_PSP(void);\r
+\r
+/**\r
+ * @brief Set the Process Stack Pointer\r
+ *\r
+ * @param topOfProcStack Process Stack Pointer\r
+ *\r
+ * Assign the value ProcessStackPointer to the MSP \r
+ * (process stack pointer) Cortex processor register\r
+ */\r
+extern void __set_PSP(uint32_t topOfProcStack);\r
+\r
+/**\r
+ * @brief Return the Main Stack Pointer\r
+ *\r
+ * @return Main Stack Pointer\r
+ *\r
+ * Return the current value of the MSP (main stack pointer)\r
+ * Cortex processor register\r
+ */\r
+extern uint32_t __get_MSP(void);\r
+\r
+/**\r
+ * @brief Set the Main Stack Pointer\r
+ *\r
+ * @param topOfMainStack Main Stack Pointer\r
+ *\r
+ * Assign the value mainStackPointer to the MSP \r
+ * (main stack pointer) Cortex processor register\r
+ */\r
+extern void __set_MSP(uint32_t topOfMainStack);\r
+\r
+/**\r
+ * @brief Return the Base Priority value\r
+ *\r
+ * @return BasePriority\r
+ *\r
+ * Return the content of the base priority register\r
+ */\r
+extern uint32_t __get_BASEPRI(void);\r
+\r
+/**\r
+ * @brief Set the Base Priority value\r
+ *\r
+ * @param basePri BasePriority\r
+ *\r
+ * Set the base priority register\r
+ */\r
+extern void __set_BASEPRI(uint32_t basePri);\r
+\r
+/**\r
+ * @brief Return the Priority Mask value\r
+ *\r
+ * @return PriMask\r
+ *\r
+ * Return state of the priority mask bit from the priority mask register\r
+ */\r
+extern uint32_t __get_PRIMASK(void);\r
+\r
+/**\r
+ * @brief Set the Priority Mask value\r
+ *\r
+ * @param priMask PriMask\r
+ *\r
+ * Set the priority mask bit in the priority mask register\r
+ */\r
+extern void __set_PRIMASK(uint32_t priMask);\r
+\r
+/**\r
+ * @brief Return the Fault Mask value\r
+ *\r
+ * @return FaultMask\r
+ *\r
+ * Return the content of the fault mask register\r
+ */\r
+extern uint32_t __get_FAULTMASK(void);\r
+\r
+/**\r
+ * @brief Set the Fault Mask value\r
+ *\r
+ * @param faultMask faultMask value\r
+ *\r
+ * Set the fault mask register\r
+ */\r
+extern void __set_FAULTMASK(uint32_t faultMask);\r
+\r
+/**\r
+ * @brief Return the Control Register value\r
+* \r
+* @return Control value\r
+ *\r
+ * Return the content of the control register\r
+ */\r
+extern uint32_t __get_CONTROL(void);\r
+\r
+/**\r
+ * @brief Set the Control Register value\r
+ *\r
+ * @param control Control value\r
+ *\r
+ * Set the control register\r
+ */\r
+extern void __set_CONTROL(uint32_t control);\r
+\r
+/**\r
+ * @brief Reverse byte order in integer value\r
+ *\r
+ * @param value value to reverse\r
+ * @return reversed value\r
+ *\r
+ * Reverse byte order in integer value\r
+ */\r
+extern uint32_t __REV(uint32_t value);\r
+\r
+/**\r
+ * @brief Reverse byte order in unsigned short value\r
+ *\r
+ * @param value value to reverse\r
+ * @return reversed value\r
+ *\r
+ * Reverse byte order in unsigned short value\r
+ */\r
+extern uint32_t __REV16(uint16_t value);\r
+\r
+/**\r
+ * @brief Reverse byte order in signed short value with sign extension to integer\r
+ *\r
+ * @param value value to reverse\r
+ * @return reversed value\r
+ *\r
+ * Reverse byte order in signed short value with sign extension to integer\r
+ */\r
+extern int32_t __REVSH(int16_t value);\r
+\r
+/**\r
+ * @brief Reverse bit order of value\r
+ *\r
+ * @param value value to reverse\r
+ * @return reversed value\r
+ *\r
+ * Reverse bit order of value\r
+ */\r
+extern uint32_t __RBIT(uint32_t value);\r
+\r
+/**\r
+ * @brief LDR Exclusive (8 bit)\r
+ *\r
+ * @param *addr address pointer\r
+ * @return value of (*address)\r
+ *\r
+ * Exclusive LDR command for 8 bit value\r
+ */\r
+extern uint8_t __LDREXB(uint8_t *addr);\r
+\r
+/**\r
+ * @brief LDR Exclusive (16 bit)\r
+ *\r
+ * @param *addr address pointer\r
+ * @return value of (*address)\r
+ *\r
+ * Exclusive LDR command for 16 bit values\r
+ */\r
+extern uint16_t __LDREXH(uint16_t *addr);\r
+\r
+/**\r
+ * @brief LDR Exclusive (32 bit)\r
+ *\r
+ * @param *addr address pointer\r
+ * @return value of (*address)\r
+ *\r
+ * Exclusive LDR command for 32 bit values\r
+ */\r
+extern uint32_t __LDREXW(uint32_t *addr);\r
+\r
+/**\r
+ * @brief STR Exclusive (8 bit)\r
+ *\r
+ * @param value value to store\r
+ * @param *addr address pointer\r
+ * @return successful / failed\r
+ *\r
+ * Exclusive STR command for 8 bit values\r
+ */\r
+extern uint32_t __STREXB(uint8_t value, uint8_t *addr);\r
+\r
+/**\r
+ * @brief STR Exclusive (16 bit)\r
+ *\r
+ * @param value value to store\r
+ * @param *addr address pointer\r
+ * @return successful / failed\r
+ *\r
+ * Exclusive STR command for 16 bit values\r
+ */\r
+extern uint32_t __STREXH(uint16_t value, uint16_t *addr);\r
+\r
+/**\r
+ * @brief STR Exclusive (32 bit)\r
+ *\r
+ * @param value value to store\r
+ * @param *addr address pointer\r
+ * @return successful / failed\r
+ *\r
+ * Exclusive STR command for 32 bit values\r
+ */\r
+extern uint32_t __STREXW(uint32_t value, uint32_t *addr);\r
+\r
+\r
+#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/\r
+/* TASKING carm specific functions */\r
+\r
+/*\r
+ * The CMSIS functions have been implemented as intrinsics in the compiler.\r
+ * Please use "carm -?i" to get an up to date list of all instrinsics,\r
+ * Including the CMSIS ones.\r
+ */\r
+\r
+#endif\r
+\r
+\r
+/** @addtogroup CMSIS_CM3_Core_FunctionInterface CMSIS CM3 Core Function Interface\r
+ Core Function Interface containing:\r
+ - Core NVIC Functions\r
+ - Core SysTick Functions\r
+ - Core Reset Functions\r
+*/\r
+/*@{*/\r
+\r
+/* ########################## NVIC functions #################################### */\r
+\r
+/**\r
+ * @brief Set the Priority Grouping in NVIC Interrupt Controller\r
+ *\r
+ * @param PriorityGroup is priority grouping field\r
+ *\r
+ * Set the priority grouping field using the required unlock sequence.\r
+ * The parameter priority_grouping is assigned to the field \r
+ * SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used.\r
+ * In case of a conflict between priority grouping and available\r
+ * priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\r
+ */\r
+static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)\r
+{\r
+ uint32_t reg_value;\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */\r
+ \r
+ reg_value = SCB->AIRCR; /* read old register configuration */\r
+ reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */\r
+ reg_value = (reg_value |\r
+ (0x5FA << SCB_AIRCR_VECTKEY_Pos) | \r
+ (PriorityGroupTmp << 8)); /* Insert write key and priorty group */\r
+ SCB->AIRCR = reg_value;\r
+}\r
+\r
+/**\r
+ * @brief Get the Priority Grouping from NVIC Interrupt Controller\r
+ *\r
+ * @return priority grouping field \r
+ *\r
+ * Get the priority grouping from NVIC Interrupt Controller.\r
+ * priority grouping is SCB->AIRCR [10:8] PRIGROUP field.\r
+ */\r
+static __INLINE uint32_t NVIC_GetPriorityGrouping(void)\r
+{\r
+ return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */\r
+}\r
+\r
+/**\r
+ * @brief Enable Interrupt in NVIC Interrupt Controller\r
+ *\r
+ * @param IRQn The positive number of the external interrupt to enable\r
+ *\r
+ * Enable a device specific interupt in the NVIC interrupt controller.\r
+ * The interrupt number cannot be a negative value.\r
+ */\r
+static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */\r
+}\r
+\r
+/**\r
+ * @brief Disable the interrupt line for external interrupt specified\r
+ * \r
+ * @param IRQn The positive number of the external interrupt to disable\r
+ * \r
+ * Disable a device specific interupt in the NVIC interrupt controller.\r
+ * The interrupt number cannot be a negative value.\r
+ */\r
+static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */\r
+}\r
+\r
+/**\r
+ * @brief Read the interrupt pending bit for a device specific interrupt source\r
+ * \r
+ * @param IRQn The number of the device specifc interrupt\r
+ * @return 1 = interrupt pending, 0 = interrupt not pending\r
+ *\r
+ * Read the pending register in NVIC and return 1 if its status is pending, \r
+ * otherwise it returns 0\r
+ */\r
+static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */\r
+}\r
+\r
+/**\r
+ * @brief Set the pending bit for an external interrupt\r
+ * \r
+ * @param IRQn The number of the interrupt for set pending\r
+ *\r
+ * Set the pending bit for the specified interrupt.\r
+ * The interrupt number cannot be a negative value.\r
+ */\r
+static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */\r
+}\r
+\r
+/**\r
+ * @brief Clear the pending bit for an external interrupt\r
+ *\r
+ * @param IRQn The number of the interrupt for clear pending\r
+ *\r
+ * Clear the pending bit for the specified interrupt. \r
+ * The interrupt number cannot be a negative value.\r
+ */\r
+static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */\r
+}\r
+\r
+/**\r
+ * @brief Read the active bit for an external interrupt\r
+ *\r
+ * @param IRQn The number of the interrupt for read active bit\r
+ * @return 1 = interrupt active, 0 = interrupt not active\r
+ *\r
+ * Read the active register in NVIC and returns 1 if its status is active, \r
+ * otherwise it returns 0.\r
+ */\r
+static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)\r
+{\r
+ return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */\r
+}\r
+\r
+/**\r
+ * @brief Set the priority for an interrupt\r
+ *\r
+ * @param IRQn The number of the interrupt for set priority\r
+ * @param priority The priority to set\r
+ *\r
+ * Set the priority for the specified interrupt. The interrupt \r
+ * number can be positive to specify an external (device specific) \r
+ * interrupt, or negative to specify an internal (core) interrupt.\r
+ *\r
+ * Note: The priority cannot be set for every core interrupt.\r
+ */\r
+static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r
+{\r
+ if(IRQn < 0) {\r
+ SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M3 System Interrupts */\r
+ else {\r
+ NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */\r
+}\r
+\r
+/**\r
+ * @brief Read the priority for an interrupt\r
+ *\r
+ * @param IRQn The number of the interrupt for get priority\r
+ * @return The priority for the interrupt\r
+ *\r
+ * Read the priority for the specified interrupt. The interrupt \r
+ * number can be positive to specify an external (device specific) \r
+ * interrupt, or negative to specify an internal (core) interrupt.\r
+ *\r
+ * The returned priority value is automatically aligned to the implemented\r
+ * priority bits of the microcontroller.\r
+ *\r
+ * Note: The priority cannot be set for every core interrupt.\r
+ */\r
+static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)\r
+{\r
+\r
+ if(IRQn < 0) {\r
+ return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M3 system interrupts */\r
+ else {\r
+ return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */\r
+}\r
+\r
+\r
+/**\r
+ * @brief Encode the priority for an interrupt\r
+ *\r
+ * @param PriorityGroup The used priority group\r
+ * @param PreemptPriority The preemptive priority value (starting from 0)\r
+ * @param SubPriority The sub priority value (starting from 0)\r
+ * @return The encoded priority for the interrupt\r
+ *\r
+ * Encode the priority for an interrupt with the given priority group,\r
+ * preemptive priority value and sub priority value.\r
+ * In case of a conflict between priority grouping and available\r
+ * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.\r
+ *\r
+ * The returned priority value can be used for NVIC_SetPriority(...) function\r
+ */\r
+static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\r
+{\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */\r
+ uint32_t PreemptPriorityBits;\r
+ uint32_t SubPriorityBits;\r
+\r
+ PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;\r
+ SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;\r
+ \r
+ return (\r
+ ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |\r
+ ((SubPriority & ((1 << (SubPriorityBits )) - 1)))\r
+ );\r
+}\r
+\r
+\r
+/**\r
+ * @brief Decode the priority of an interrupt\r
+ *\r
+ * @param Priority The priority for the interrupt\r
+ * @param PriorityGroup The used priority group\r
+ * @param pPreemptPriority The preemptive priority value (starting from 0)\r
+ * @param pSubPriority The sub priority value (starting from 0)\r
+ *\r
+ * Decode an interrupt priority value with the given priority group to \r
+ * preemptive priority value and sub priority value.\r
+ * In case of a conflict between priority grouping and available\r
+ * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.\r
+ *\r
+ * The priority value can be retrieved with NVIC_GetPriority(...) function\r
+ */\r
+static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)\r
+{\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */\r
+ uint32_t PreemptPriorityBits;\r
+ uint32_t SubPriorityBits;\r
+\r
+ PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;\r
+ SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;\r
+ \r
+ *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);\r
+ *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);\r
+}\r
+\r
+\r
+\r
+/* ################################## SysTick function ############################################ */\r
+\r
+#if (!defined (__Vendor_SysTickConfig)) || (__Vendor_SysTickConfig == 0)\r
+\r
+/**\r
+ * @brief Initialize and start the SysTick counter and its interrupt.\r
+ *\r
+ * @param ticks number of ticks between two interrupts\r
+ * @return 1 = failed, 0 = successful\r
+ *\r
+ * Initialise the system tick timer and its interrupt and start the\r
+ * system tick timer / counter in free running mode to generate \r
+ * periodical interrupts.\r
+ */\r
+static __INLINE uint32_t SysTick_Config(uint32_t ticks)\r
+{ \r
+ if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */\r
+ \r
+ SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */\r
+ NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */\r
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */\r
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | \r
+ SysTick_CTRL_TICKINT_Msk | \r
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
+ return (0); /* Function successful */\r
+}\r
+\r
+#endif\r
+\r
+\r
+\r
+\r
+/* ################################## Reset function ############################################ */\r
+\r
+/**\r
+ * @brief Initiate a system reset request.\r
+ *\r
+ * Initiate a system reset request to reset the MCU\r
+ */\r
+static __INLINE void NVIC_SystemReset(void)\r
+{\r
+ SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | \r
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | \r
+ SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */\r
+ __DSB(); /* Ensure completion of memory access */ \r
+ while(1); /* wait until reset */\r
+}\r
+\r
+/*@}*/ /* end of group CMSIS_CM3_Core_FunctionInterface */\r
+\r
+\r
+\r
+/* ##################################### Debug In/Output function ########################################### */\r
+\r
+/** @addtogroup CMSIS_CM3_CoreDebugInterface CMSIS CM3 Core Debug Interface\r
+ Core Debug Interface containing:\r
+ - Core Debug Receive / Transmit Functions\r
+ - Core Debug Defines\r
+ - Core Debug Variables\r
+*/\r
+/*@{*/\r
+\r
+extern volatile int ITM_RxBuffer; /*!< variable to receive characters */\r
+#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< value identifying ITM_RxBuffer is ready for next character */\r
+\r
+\r
+/**\r
+ * @brief Outputs a character via the ITM channel 0\r
+ *\r
+ * @param ch character to output\r
+ * @return character to output\r
+ *\r
+ * The function outputs a character via the ITM channel 0. \r
+ * The function returns when no debugger is connected that has booked the output. \r
+ * It is blocking when a debugger is connected, but the previous character send is not transmitted. \r
+ */\r
+static __INLINE uint32_t ITM_SendChar (uint32_t ch)\r
+{\r
+ if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk) && /* Trace enabled */\r
+ (ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */\r
+ (ITM->TER & (1ul << 0) ) ) /* ITM Port #0 enabled */\r
+ {\r
+ while (ITM->PORT[0].u32 == 0);\r
+ ITM->PORT[0].u8 = (uint8_t) ch;\r
+ } \r
+ return (ch);\r
+}\r
+\r
+\r
+/**\r
+ * @brief Inputs a character via variable ITM_RxBuffer\r
+ *\r
+ * @return received character, -1 = no character received\r
+ *\r
+ * The function inputs a character via variable ITM_RxBuffer. \r
+ * The function returns when no debugger is connected that has booked the output. \r
+ * It is blocking when a debugger is connected, but the previous character send is not transmitted. \r
+ */\r
+static __INLINE int ITM_ReceiveChar (void) {\r
+ int ch = -1; /* no character available */\r
+\r
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {\r
+ ch = ITM_RxBuffer;\r
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */\r
+ }\r
+ \r
+ return (ch); \r
+}\r
+\r
+\r
+/**\r
+ * @brief Check if a character via variable ITM_RxBuffer is available\r
+ *\r
+ * @return 1 = character available, 0 = no character available\r
+ *\r
+ * The function checks variable ITM_RxBuffer whether a character is available or not. \r
+ * The function returns '1' if a character is available and '0' if no character is available. \r
+ */\r
+static __INLINE int ITM_CheckChar (void) {\r
+\r
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {\r
+ return (0); /* no character available */\r
+ } else {\r
+ return (1); /* character available */\r
+ }\r
+}\r
+\r
+/*@}*/ /* end of group CMSIS_CM3_core_DebugInterface */\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+/*@}*/ /* end of group CMSIS_CM3_core_definitions */\r
+\r
+#endif /* __CM3_CORE_H__ */\r
+\r
+/*lint -restore */\r
<name>JLINK_ID</name>\r
<archiveVersion>2</archiveVersion>\r
<data>\r
- <version>12</version>\r
+ <version>13</version>\r
<wantNonLocal>1</wantNonLocal>\r
<debug>1</debug>\r
<option>\r
</option>\r
<option>\r
<name>CCUSBDevice</name>\r
- <version>0</version>\r
- <state>0</state>\r
+ <version>1</version>\r
+ <state>1</state>\r
</option>\r
<option>\r
<name>CCRDICatchReset</name>\r
</option>\r
<option>\r
<name>CCJLinkResetList</name>\r
- <version>4</version>\r
+ <version>5</version>\r
<state>7</state>\r
</option>\r
<option>\r
<name>OCJLinkScriptFile</name>\r
<state>1</state>\r
</option>\r
+ <option>\r
+ <name>CCJLinkUsbSerialNo</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCTcpIpAlt</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkTcpIpSerialNo</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCCpuClockEdit</name>\r
+ <state>72.0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSwoClockAuto</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSwoClockEdit</name>\r
+ <state>2000</state>\r
+ </option>\r
</data>\r
</settings>\r
<settings>\r
<name>RDI_ID</name>\r
<archiveVersion>2</archiveVersion>\r
<data>\r
- <version>1</version>\r
+ <version>2</version>\r
<wantNonLocal>1</wantNonLocal>\r
<debug>1</debug>\r
<option>\r
<name>CCRDICatchFIQ</name>\r
<state>0</state>\r
</option>\r
- <option>\r
- <name>CCRDIUseETM</name>\r
- <state>0</state>\r
- </option>\r
<option>\r
<name>OCDriverInfo</name>\r
<state>1</state>\r
<name>STLINK_ID</name>\r
<archiveVersion>2</archiveVersion>\r
<data>\r
- <version>1</version>\r
+ <version>2</version>\r
<wantNonLocal>1</wantNonLocal>\r
<debug>1</debug>\r
<option>\r
<name>CCSTLinkInterfaceCmdLine</name>\r
<state>0</state>\r
</option>\r
+ <option>\r
+ <name>CCSTLinkResetList</name>\r
+ <version>1</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCpuClockEdit</name>\r
+ <state>72.0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSwoClockAuto</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSwoClockEdit</name>\r
+ <state>2000</state>\r
+ </option>\r
</data>\r
</settings>\r
<settings>\r
</option>\r
<option>\r
<name>OCLastSavedByProductVersion</name>\r
- <state>6.10.1.52170</state>\r
+ <state>6.20.1.52589</state>\r
</option>\r
<option>\r
<name>OCDownloadAttachToProgram</name>\r
<name>JLINK_ID</name>\r
<archiveVersion>2</archiveVersion>\r
<data>\r
- <version>12</version>\r
+ <version>13</version>\r
<wantNonLocal>1</wantNonLocal>\r
<debug>1</debug>\r
<option>\r
</option>\r
<option>\r
<name>CCUSBDevice</name>\r
- <version>0</version>\r
- <state>0</state>\r
+ <version>1</version>\r
+ <state>1</state>\r
</option>\r
<option>\r
<name>CCRDICatchReset</name>\r
</option>\r
<option>\r
<name>CCJLinkResetList</name>\r
- <version>4</version>\r
+ <version>5</version>\r
<state>7</state>\r
</option>\r
<option>\r
<name>OCJLinkScriptFile</name>\r
<state>1</state>\r
</option>\r
+ <option>\r
+ <name>CCJLinkUsbSerialNo</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCTcpIpAlt</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkTcpIpSerialNo</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCCpuClockEdit</name>\r
+ <state>72.0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSwoClockAuto</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSwoClockEdit</name>\r
+ <state>2000</state>\r
+ </option>\r
</data>\r
</settings>\r
<settings>\r
<name>RDI_ID</name>\r
<archiveVersion>2</archiveVersion>\r
<data>\r
- <version>1</version>\r
+ <version>2</version>\r
<wantNonLocal>1</wantNonLocal>\r
<debug>1</debug>\r
<option>\r
<name>CCRDICatchFIQ</name>\r
<state>0</state>\r
</option>\r
- <option>\r
- <name>CCRDIUseETM</name>\r
- <state>0</state>\r
- </option>\r
<option>\r
<name>OCDriverInfo</name>\r
<state>1</state>\r
<name>STLINK_ID</name>\r
<archiveVersion>2</archiveVersion>\r
<data>\r
- <version>1</version>\r
+ <version>2</version>\r
<wantNonLocal>1</wantNonLocal>\r
<debug>1</debug>\r
<option>\r
<name>CCSTLinkInterfaceCmdLine</name>\r
<state>0</state>\r
</option>\r
+ <option>\r
+ <name>CCSTLinkResetList</name>\r
+ <version>1</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCpuClockEdit</name>\r
+ <state>72.0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSwoClockAuto</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSwoClockEdit</name>\r
+ <state>2000</state>\r
+ </option>\r
</data>\r
</settings>\r
<settings>\r
<name>JLINK_ID</name>\r
<archiveVersion>2</archiveVersion>\r
<data>\r
- <version>12</version>\r
+ <version>13</version>\r
<wantNonLocal>1</wantNonLocal>\r
<debug>1</debug>\r
<option>\r
</option>\r
<option>\r
<name>CCUSBDevice</name>\r
- <version>0</version>\r
- <state>0</state>\r
+ <version>1</version>\r
+ <state>1</state>\r
</option>\r
<option>\r
<name>CCRDICatchReset</name>\r
</option>\r
<option>\r
<name>CCJLinkResetList</name>\r
- <version>4</version>\r
+ <version>5</version>\r
<state>7</state>\r
</option>\r
<option>\r
<name>OCJLinkScriptFile</name>\r
<state>1</state>\r
</option>\r
+ <option>\r
+ <name>CCJLinkUsbSerialNo</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCTcpIpAlt</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkTcpIpSerialNo</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCCpuClockEdit</name>\r
+ <state>72.0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSwoClockAuto</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSwoClockEdit</name>\r
+ <state>2000</state>\r
+ </option>\r
</data>\r
</settings>\r
<settings>\r
<name>RDI_ID</name>\r
<archiveVersion>2</archiveVersion>\r
<data>\r
- <version>1</version>\r
+ <version>2</version>\r
<wantNonLocal>1</wantNonLocal>\r
<debug>1</debug>\r
<option>\r
<name>CCRDICatchFIQ</name>\r
<state>0</state>\r
</option>\r
- <option>\r
- <name>CCRDIUseETM</name>\r
- <state>0</state>\r
- </option>\r
<option>\r
<name>OCDriverInfo</name>\r
<state>1</state>\r
<name>STLINK_ID</name>\r
<archiveVersion>2</archiveVersion>\r
<data>\r
- <version>1</version>\r
+ <version>2</version>\r
<wantNonLocal>1</wantNonLocal>\r
<debug>1</debug>\r
<option>\r
<name>CCSTLinkInterfaceCmdLine</name>\r
<state>0</state>\r
</option>\r
+ <option>\r
+ <name>CCSTLinkResetList</name>\r
+ <version>1</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCpuClockEdit</name>\r
+ <state>72.0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSwoClockAuto</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSwoClockEdit</name>\r
+ <state>2000</state>\r
+ </option>\r
</data>\r
</settings>\r
<settings>\r
<name>General</name>\r
<archiveVersion>3</archiveVersion>\r
<data>\r
- <version>18</version>\r
+ <version>21</version>\r
<wantNonLocal>1</wantNonLocal>\r
<debug>1</debug>\r
<option>\r
</option>\r
<option>\r
<name>Variant</name>\r
- <version>17</version>\r
+ <version>19</version>\r
<state>37</state>\r
</option>\r
<option>\r
</option>\r
<option>\r
<name>Input variant</name>\r
- <version>1</version>\r
- <state>3</state>\r
+ <version>3</version>\r
+ <state>6</state>\r
</option>\r
<option>\r
<name>Input description</name>\r
</option>\r
<option>\r
<name>Output variant</name>\r
- <version>0</version>\r
- <state>3</state>\r
+ <version>2</version>\r
+ <state>7</state>\r
</option>\r
<option>\r
<name>Output description</name>\r
</option>\r
<option>\r
<name>FPU</name>\r
- <version>1</version>\r
+ <version>2</version>\r
<state>0</state>\r
</option>\r
<option>\r
</option>\r
<option>\r
<name>OGLastSavedByProductVersion</name>\r
- <state>6.10.1.52170</state>\r
+ <state>6.20.1.52589</state>\r
</option>\r
<option>\r
<name>GeneralEnableMisra</name>\r
<name>RTConfigPath2</name>\r
<state>$TOOLKIT_DIR$\INC\c\DLib_Config_Normal.h</state>\r
</option>\r
+ <option>\r
+ <name>GFPUCoreSlave</name>\r
+ <version>19</version>\r
+ <state>37</state>\r
+ </option>\r
+ <option>\r
+ <name>GBECoreSlave</name>\r
+ <version>19</version>\r
+ <state>37</state>\r
+ </option>\r
+ <option>\r
+ <name>OGUseCmsis</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OGUseCmsisDspLib</name>\r
+ <state>0</state>\r
+ </option>\r
</data>\r
</settings>\r
<settings>\r
<name>ICCARM</name>\r
<archiveVersion>2</archiveVersion>\r
<data>\r
- <version>26</version>\r
+ <version>28</version>\r
<wantNonLocal>1</wantNonLocal>\r
<debug>1</debug>\r
<option>\r
<state>1</state>\r
</option>\r
<option>\r
- <name>IccRelaxedFpPrecision</name>\r
+ <name>IccCppInlineSemantics</name>\r
<state>0</state>\r
</option>\r
<option>\r
- <name>IccCppInlineSemantics</name>\r
+ <name>IccCmsis</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IccFloatSemantics</name>\r
<state>0</state>\r
</option>\r
</data>\r
<name>ILINK</name>\r
<archiveVersion>0</archiveVersion>\r
<data>\r
- <version>11</version>\r
+ <version>13</version>\r
<wantNonLocal>1</wantNonLocal>\r
<debug>1</debug>\r
<option>\r
<name>IlinkOptExceptionsForce</name>\r
<state>0</state>\r
</option>\r
+ <option>\r
+ <name>IlinkCmsis</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkOptMergeDuplSections</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkOptUseVfe</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkOptForceVfe</name>\r
+ <state>0</state>\r
+ </option>\r
</data>\r
</settings>\r
<settings>\r
<name>General</name>\r
<archiveVersion>3</archiveVersion>\r
<data>\r
- <version>18</version>\r
+ <version>21</version>\r
<wantNonLocal>1</wantNonLocal>\r
<debug>1</debug>\r
<option>\r
</option>\r
<option>\r
<name>Variant</name>\r
- <version>17</version>\r
+ <version>19</version>\r
<state>37</state>\r
</option>\r
<option>\r
</option>\r
<option>\r
<name>Input variant</name>\r
- <version>1</version>\r
- <state>3</state>\r
+ <version>3</version>\r
+ <state>6</state>\r
</option>\r
<option>\r
<name>Input description</name>\r
</option>\r
<option>\r
<name>Output variant</name>\r
- <version>0</version>\r
- <state>3</state>\r
+ <version>2</version>\r
+ <state>7</state>\r
</option>\r
<option>\r
<name>Output description</name>\r
</option>\r
<option>\r
<name>FPU</name>\r
- <version>1</version>\r
+ <version>2</version>\r
<state>0</state>\r
</option>\r
<option>\r
</option>\r
<option>\r
<name>OGLastSavedByProductVersion</name>\r
- <state>6.10.1.52170</state>\r
+ <state>6.20.1.52589</state>\r
</option>\r
<option>\r
<name>GeneralEnableMisra</name>\r
<name>RTConfigPath2</name>\r
<state>$TOOLKIT_DIR$\INC\c\DLib_Config_Normal.h</state>\r
</option>\r
+ <option>\r
+ <name>GFPUCoreSlave</name>\r
+ <version>19</version>\r
+ <state>37</state>\r
+ </option>\r
+ <option>\r
+ <name>GBECoreSlave</name>\r
+ <version>19</version>\r
+ <state>37</state>\r
+ </option>\r
+ <option>\r
+ <name>OGUseCmsis</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OGUseCmsisDspLib</name>\r
+ <state>0</state>\r
+ </option>\r
</data>\r
</settings>\r
<settings>\r
<name>ICCARM</name>\r
<archiveVersion>2</archiveVersion>\r
<data>\r
- <version>26</version>\r
+ <version>28</version>\r
<wantNonLocal>1</wantNonLocal>\r
<debug>1</debug>\r
<option>\r
<state>1</state>\r
</option>\r
<option>\r
- <name>IccRelaxedFpPrecision</name>\r
+ <name>IccCppInlineSemantics</name>\r
<state>0</state>\r
</option>\r
<option>\r
- <name>IccCppInlineSemantics</name>\r
+ <name>IccCmsis</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IccFloatSemantics</name>\r
<state>0</state>\r
</option>\r
</data>\r
<name>ILINK</name>\r
<archiveVersion>0</archiveVersion>\r
<data>\r
- <version>11</version>\r
+ <version>13</version>\r
<wantNonLocal>1</wantNonLocal>\r
<debug>1</debug>\r
<option>\r
<name>IlinkOptExceptionsForce</name>\r
<state>0</state>\r
</option>\r
+ <option>\r
+ <name>IlinkCmsis</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkOptMergeDuplSections</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkOptUseVfe</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkOptForceVfe</name>\r
+ <state>0</state>\r
+ </option>\r
</data>\r
</settings>\r
<settings>\r
<name>General</name>\r
<archiveVersion>3</archiveVersion>\r
<data>\r
- <version>18</version>\r
+ <version>21</version>\r
<wantNonLocal>1</wantNonLocal>\r
<debug>1</debug>\r
<option>\r
</option>\r
<option>\r
<name>Variant</name>\r
- <version>17</version>\r
+ <version>19</version>\r
<state>37</state>\r
</option>\r
<option>\r
</option>\r
<option>\r
<name>Input variant</name>\r
- <version>1</version>\r
- <state>3</state>\r
+ <version>3</version>\r
+ <state>6</state>\r
</option>\r
<option>\r
<name>Input description</name>\r
</option>\r
<option>\r
<name>Output variant</name>\r
- <version>0</version>\r
- <state>3</state>\r
+ <version>2</version>\r
+ <state>7</state>\r
</option>\r
<option>\r
<name>Output description</name>\r
</option>\r
<option>\r
<name>FPU</name>\r
- <version>1</version>\r
+ <version>2</version>\r
<state>0</state>\r
</option>\r
<option>\r
</option>\r
<option>\r
<name>OGLastSavedByProductVersion</name>\r
- <state>6.10.1.52170</state>\r
+ <state>6.20.1.52589</state>\r
</option>\r
<option>\r
<name>GeneralEnableMisra</name>\r
<name>RTConfigPath2</name>\r
<state>$TOOLKIT_DIR$\INC\c\DLib_Config_Normal.h</state>\r
</option>\r
+ <option>\r
+ <name>GFPUCoreSlave</name>\r
+ <version>19</version>\r
+ <state>37</state>\r
+ </option>\r
+ <option>\r
+ <name>GBECoreSlave</name>\r
+ <version>19</version>\r
+ <state>37</state>\r
+ </option>\r
+ <option>\r
+ <name>OGUseCmsis</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OGUseCmsisDspLib</name>\r
+ <state>0</state>\r
+ </option>\r
</data>\r
</settings>\r
<settings>\r
<name>ICCARM</name>\r
<archiveVersion>2</archiveVersion>\r
<data>\r
- <version>26</version>\r
+ <version>28</version>\r
<wantNonLocal>1</wantNonLocal>\r
<debug>1</debug>\r
<option>\r
<state>1</state>\r
</option>\r
<option>\r
- <name>IccRelaxedFpPrecision</name>\r
+ <name>IccCppInlineSemantics</name>\r
<state>0</state>\r
</option>\r
<option>\r
- <name>IccCppInlineSemantics</name>\r
+ <name>IccCmsis</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IccFloatSemantics</name>\r
<state>0</state>\r
</option>\r
</data>\r
<name>ILINK</name>\r
<archiveVersion>0</archiveVersion>\r
<data>\r
- <version>11</version>\r
+ <version>13</version>\r
<wantNonLocal>1</wantNonLocal>\r
<debug>1</debug>\r
<option>\r
<name>IlinkOptExceptionsForce</name>\r
<state>0</state>\r
</option>\r
+ <option>\r
+ <name>IlinkCmsis</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkOptMergeDuplSections</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkOptUseVfe</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkOptForceVfe</name>\r
+ <state>0</state>\r
+ </option>\r
</data>\r
</settings>\r
<settings>\r
<settings>\r
<name>ICCARM</name>\r
<data>\r
- <version>26</version>\r
+ <version>28</version>\r
<wantNonLocal>0</wantNonLocal>\r
<debug>1</debug>\r
<option>\r
<state>1</state>\r
</option>\r
<option>\r
- <name>IccRelaxedFpPrecision</name>\r
+ <name>IccCppInlineSemantics</name>\r
<state>0</state>\r
</option>\r
<option>\r
- <name>IccCppInlineSemantics</name>\r
+ <name>IccCmsis</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IccFloatSemantics</name>\r
<state>0</state>\r
</option>\r
</data>\r
\r
#endif /* __ARMCC_VERSION */ \r
\r
-\r
-\r
#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/\r
/* IAR iccarm specific functions */\r
\r
-#define __enable_irq __enable_interrupt /*!< global Interrupt enable */\r
-#define __disable_irq __disable_interrupt /*!< global Interrupt disable */\r
+#if (__VER__ >= 6020000) // If iccarm version is 6.20.0 or later ----------\r
\r
-static __INLINE void __enable_fault_irq() { __ASM ("cpsie f"); }\r
-static __INLINE void __disable_fault_irq() { __ASM ("cpsid f"); }\r
+#include <cmsis_iar.h>\r
\r
-static __INLINE void __WFI() { __ASM ("wfi"); }\r
-static __INLINE void __WFE() { __ASM ("wfe"); }\r
-static __INLINE void __SEV() { __ASM ("sev"); }\r
-static __INLINE void __CLREX() { __ASM ("clrex"); }\r
+#else\r
\r
-/**\r
- * @brief Return the Process Stack Pointer\r
- *\r
- * @param none\r
- * @return uint32_t ProcessStackPointer\r
- *\r
- * Return the actual process stack pointer\r
- */\r
-extern uint32_t __get_PSP(void);\r
+#pragma diag_suppress=Pe940\r
+#pragma diag_suppress=Pe177\r
\r
-/**\r
- * @brief Set the Process Stack Pointer\r
- *\r
- * @param uint32_t Process Stack Pointer\r
- * @return none\r
- *\r
- * Assign the value ProcessStackPointer to the MSP \r
- * (process stack pointer) Cortex processor register\r
- */\r
-extern void __set_PSP(uint32_t topOfProcStack);\r
+#define __enable_irq __enable_interrupt\r
+#define __disable_irq __disable_interrupt\r
+#define __NOP __no_operation\r
\r
-/**\r
- * @brief Return the Main Stack Pointer\r
- *\r
- * @param none\r
- * @return uint32_t Main Stack Pointer\r
- *\r
- * Return the current value of the MSP (main stack pointer)\r
- * Cortex processor register\r
- */\r
-extern uint32_t __get_MSP(void);\r
+#if (__VER__ < 6020000) // If iccarm version is older than 6.20.0 ----------\r
\r
-/**\r
- * @brief Set the Main Stack Pointer\r
- *\r
- * @param uint32_t Main Stack Pointer\r
- * @return none\r
- *\r
- * Assign the value mainStackPointer to the MSP \r
- * (main stack pointer) Cortex processor register\r
- */\r
-extern void __set_MSP(uint32_t topOfMainStack);\r
+#if (__VER__ < 6010002) // If iccarm version is older than 6.10.2 ----------\r
\r
-/**\r
- * @brief Reverse byte order in unsigned short value\r
- *\r
- * @param uint16_t value to reverse\r
- * @return uint32_t reversed value\r
- *\r
- * Reverse byte order in unsigned short value\r
- */\r
-extern uint32_t __REV16(uint16_t value);\r
+static uint32_t __get_APSR(void)\r
+{\r
+ __ASM("mrs r0, apsr");\r
+}\r
\r
-/**\r
- * @brief Reverse bit order of value\r
- *\r
- * @param uint32_t value to reverse\r
- * @return uint32_t reversed value\r
- *\r
- * Reverse bit order of value\r
- */\r
-extern uint32_t __RBIT(uint32_t value);\r
+static uint32_t __get_xPSR(void)\r
+{\r
+ __ASM("mrs r0, psr"); // assembler does not know "xpsr"\r
+}\r
\r
-/**\r
- * @brief LDR Exclusive\r
- *\r
- * @param uint8_t* address\r
- * @return uint8_t value of (*address)\r
- *\r
- * Exclusive LDR command\r
- */\r
-extern uint8_t __LDREXB(uint8_t *addr);\r
+#endif // __VER__ < 6010002\r
\r
-/**\r
- * @brief LDR Exclusive\r
- *\r
- * @param uint16_t* address\r
- * @return uint16_t value of (*address)\r
- *\r
- * Exclusive LDR command\r
- */\r
-extern uint16_t __LDREXH(uint16_t *addr);\r
+static uint32_t __get_IPSR(void)\r
+{\r
+ __ASM("mrs r0, ipsr");\r
+}\r
\r
-/**\r
- * @brief LDR Exclusive\r
- *\r
- * @param uint32_t* address\r
- * @return uint32_t value of (*address)\r
- *\r
- * Exclusive LDR command\r
- */\r
-extern uint32_t __LDREXW(uint32_t *addr);\r
+static uint32_t __get_PSR(void)\r
+{\r
+ __ASM("mrs r0, psr");\r
+}\r
\r
-/**\r
- * @brief STR Exclusive\r
- *\r
- * @param uint8_t *address\r
- * @param uint8_t value to store\r
- * @return uint32_t successful / failed\r
- *\r
- * Exclusive STR command\r
- */\r
-extern uint32_t __STREXB(uint8_t value, uint8_t *addr);\r
+static uint32_t __get_PSP(void)\r
+{\r
+ __ASM("mrs r0, psp");\r
+}\r
+ \r
+static void __set_PSP(uint32_t topOfProcStack)\r
+{\r
+ __ASM("msr psp, r0");\r
+}\r
\r
-/**\r
- * @brief STR Exclusive\r
- *\r
- * @param uint16_t *address\r
- * @param uint16_t value to store\r
- * @return uint32_t successful / failed\r
- *\r
- * Exclusive STR command\r
- */\r
-extern uint32_t __STREXH(uint16_t value, uint16_t *addr);\r
+static uint32_t __get_MSP(void)\r
+{\r
+ __ASM("mrs r0, msp");\r
+}\r
+ \r
+static void __set_MSP(uint32_t topOfMainStack)\r
+{\r
+ __ASM("msr msp, r0");\r
+}\r
\r
-/**\r
- * @brief STR Exclusive\r
- *\r
- * @param uint32_t *address\r
- * @param uint32_t value to store\r
- * @return uint32_t successful / failed\r
- *\r
- * Exclusive STR command\r
- */\r
-extern uint32_t __STREXW(uint32_t value, uint32_t *addr);\r
+static __INLINE void __WFI(void)\r
+{\r
+ __ASM ("wfi");\r
+}\r
+\r
+static __INLINE void __WFE(void)\r
+{\r
+ __ASM ("wfe");\r
+}\r
+\r
+static __INLINE void __SEV(void)\r
+{\r
+ __ASM ("sev");\r
+}\r
+\r
+static uint32_t __REV16(uint32_t value)\r
+{\r
+ __ASM("rev16 r0, r0");\r
+}\r
+\r
+#endif // __VER__ < 6020000\r
+\r
+#if (__CORTEX_M >= 0x03) // __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h.\r
+\r
+#if (__VER__ < 6020000) // If iccarm version is older than 6.20.0 ----------\r
+\r
+static __INLINE void __enable_fault_irq(void)\r
+{\r
+ __ASM ("cpsie f");\r
+}\r
+\r
+static __INLINE void __disable_fault_irq(void)\r
+{\r
+ __ASM ("cpsid f");\r
+}\r
+\r
+static uint32_t __RBIT(uint32_t value)\r
+{\r
+ __ASM("rbit r0, r0");\r
+}\r
+\r
+static uint8_t __LDREXB(volatile uint8_t *addr)\r
+{\r
+ __ASM("ldrexb r0, [r0]");\r
+}\r
+\r
+static uint16_t __LDREXH(volatile uint16_t *addr)\r
+{\r
+ __ASM("ldrexh r0, [r0]");\r
+}\r
+\r
+static uint32_t __LDREXW(volatile uint32_t *addr)\r
+{\r
+ __ASM("ldrex r0, [r0]");\r
+}\r
+\r
+static uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)\r
+{\r
+ __ASM("strexb r0, r0, [r1]");\r
+}\r
+\r
+static uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)\r
+{\r
+ __ASM("strexh r0, r0, [r1]");\r
+}\r
+\r
+static uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)\r
+{\r
+ __ASM("strex r0, r0, [r1]");\r
+}\r
+\r
+static __INLINE void __CLREX(void)\r
+{\r
+ __ASM ("clrex");\r
+}\r
+\r
+#else // __VER__ >= 6020000 ---------------------\r
+\r
+#define __LDREXW __LDREX\r
+#define __STREXW __STREX\r
+#define __enable_fault_irq __enable_fiq\r
+#define __disable_fault_irq __disable_fiq\r
+\r
+#endif // __VER__ < 6020000\r
+\r
+#endif /* (__CORTEX_M >= 0x03) */\r
+\r
+#if (__CORTEX_M == 0x04) // __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h.\r
+\r
+#if (__VER__ < 6020000) // If iccarm version is older than 6.20.0 ----------\r
+\r
+static uint32_t __get_FPSCR(void)\r
+{\r
+#if (__FPU_PRESENT == 1) // __FPU_PRESENT is defined in the device header file, if present in current device.\r
+ __ASM("vmrs r0, fpscr"); \r
+#else\r
+ return(0);\r
+#endif\r
+}\r
+\r
+static void __set_FPSCR(uint32_t fpscr)\r
+{\r
+#if (__FPU_PRESENT == 1) // __FPU_PRESENT is defined in the device header file, if present in current device.\r
+ __ASM("vmsr fpscr, r0");\r
+#endif\r
+}\r
\r
+#endif // __VER__ < 6020000\r
\r
-/* intrinsic void __set_PRIMASK(); */\r
-/* intrinsic void __get_PRIMASK(); */\r
-/* intrinsic void __set_FAULTMASK(); */\r
-/* intrinsic void __get_FAULTMASK(); */\r
-/* intrinsic uint32_t __REV(uint32_t value); */\r
-/* intrinsic uint32_t __REVSH(uint32_t value); */\r
-/* intrinsic unsigned long __STREX(unsigned long, unsigned long); */\r
-/* intrinsic unsigned long __LDREX(unsigned long *); */\r
+#endif /* (__CORTEX_M == 0x04) */\r
\r
+#pragma diag_default=Pe940\r
+#pragma diag_default=Pe177\r
\r
+#endif // __VER__ >= 6020000\r
\r
#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/\r
/* GNU gcc specific functions */\r
</option>\r
<option>\r
<name>OCLastSavedByProductVersion</name>\r
- <state>5.50.5.51996</state>\r
+ <state>6.20.1.52589</state>\r
</option>\r
<option>\r
<name>OCDownloadAttachToProgram</name>\r
<settings>\r
<name>IARROM_ID</name>\r
<archiveVersion>2</archiveVersion>\r
- <data>\r
- <version>0</version>\r
- <wantNonLocal>1</wantNonLocal>\r
- <debug>1</debug>\r
- <option>\r
- <name>CRomLogFileCheck</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CRomLogFileEditB</name>\r
- <state>$PROJ_DIR$\cspycomm.log</state>\r
- </option>\r
- <option>\r
- <name>CRomCommunication</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CRomCommPort</name>\r
- <version>0</version>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CRomCommBaud</name>\r
- <version>0</version>\r
- <state>7</state>\r
- </option>\r
- <option>\r
- <name>OCDriverInfo</name>\r
- <state>1</state>\r
- </option>\r
- </data>\r
- </settings>\r
- <settings>\r
- <name>JLINK_ID</name>\r
- <archiveVersion>2</archiveVersion>\r
- <data>\r
- <version>11</version>\r
- <wantNonLocal>1</wantNonLocal>\r
- <debug>1</debug>\r
- <option>\r
- <name>JLinkSpeed</name>\r
- <state>32</state>\r
- </option>\r
- <option>\r
- <name>CCJLinkDoLogfile</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CCJLinkLogFile</name>\r
- <state>$PROJ_DIR$\cspycomm.log</state>\r
- </option>\r
- <option>\r
- <name>CCJLinkHWResetDelay</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>OCDriverInfo</name>\r
- <state>1</state>\r
- </option>\r
- <option>\r
- <name>JLinkInitialSpeed</name>\r
- <state>32</state>\r
- </option>\r
- <option>\r
- <name>CCDoJlinkMultiTarget</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CCScanChainNonARMDevices</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CCJLinkMultiTarget</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CCJLinkIRLength</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CCJLinkCommRadio</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CCJLinkTCPIP</name>\r
- <state>aaa.bbb.ccc.ddd</state>\r
- </option>\r
- <option>\r
- <name>CCJLinkSpeedRadioV2</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CCUSBDevice</name>\r
- <version>0</version>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CCRDICatchReset</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CCRDICatchUndef</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CCRDICatchSWI</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CCRDICatchData</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CCRDICatchPrefetch</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CCRDICatchIRQ</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CCRDICatchFIQ</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CCJLinkBreakpointRadio</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CCJLinkDoUpdateBreakpoints</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CCJLinkUpdateBreakpoints</name>\r
- <state>main</state>\r
- </option>\r
- <option>\r
- <name>CCJLinkInterfaceRadio</name>\r
- <state>1</state>\r
- </option>\r
- <option>\r
- <name>OCJLinkAttachSlave</name>\r
- <state>1</state>\r
- </option>\r
- <option>\r
- <name>CCJLinkResetList</name>\r
- <version>2</version>\r
- <state>7</state>\r
- </option>\r
- <option>\r
- <name>CCJLinkInterfaceCmdLine</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CCCatchCORERESET</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CCCatchMMERR</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CCCatchNOCPERR</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CCCatchCHRERR</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CCCatchSTATERR</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CCCatchBUSERR</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CCCatchINTERR</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CCCatchHARDERR</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CCCatchDummy</name>\r
- <state>0</state>\r
- </option>\r
- </data>\r
- </settings>\r
- <settings>\r
- <name>LMIFTDI_ID</name>\r
- <archiveVersion>2</archiveVersion>\r
- <data>\r
- <version>2</version>\r
- <wantNonLocal>1</wantNonLocal>\r
- <debug>1</debug>\r
- <option>\r
- <name>OCDriverInfo</name>\r
- <state>1</state>\r
- </option>\r
- <option>\r
- <name>LmiftdiSpeed</name>\r
- <state>500</state>\r
- </option>\r
- <option>\r
- <name>CCLmiftdiDoLogfile</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CCLmiftdiLogFile</name>\r
- <state>$PROJ_DIR$\cspycomm.log</state>\r
- </option>\r
- <option>\r
- <name>CCLmiFtdiInterfaceRadio</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CCLmiFtdiInterfaceCmdLine</name>\r
- <state>0</state>\r
- </option>\r
- </data>\r
- </settings>\r
- <settings>\r
- <name>MACRAIGOR_ID</name>\r
- <archiveVersion>2</archiveVersion>\r
- <data>\r
- <version>3</version>\r
- <wantNonLocal>1</wantNonLocal>\r
- <debug>1</debug>\r
- <option>\r
- <name>jtag</name>\r
- <version>0</version>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>EmuSpeed</name>\r
- <state>1</state>\r
- </option>\r
- <option>\r
- <name>TCPIP</name>\r
- <state>aaa.bbb.ccc.ddd</state>\r
- </option>\r
- <option>\r
- <name>DoLogfile</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>LogFile</name>\r
- <state>$PROJ_DIR$\cspycomm.log</state>\r
- </option>\r
- <option>\r
- <name>DoEmuMultiTarget</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>EmuMultiTarget</name>\r
- <state>0@ARM7TDMI</state>\r
- </option>\r
- <option>\r
- <name>EmuHWReset</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CEmuCommBaud</name>\r
- <version>0</version>\r
- <state>4</state>\r
- </option>\r
- <option>\r
- <name>CEmuCommPort</name>\r
- <version>0</version>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>jtago</name>\r
- <version>0</version>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>OCDriverInfo</name>\r
- <state>1</state>\r
- </option>\r
- <option>\r
- <name>UnusedAddr</name>\r
- <state>0x00800000</state>\r
- </option>\r
- <option>\r
- <name>CCMacraigorHWResetDelay</name>\r
- <state></state>\r
- </option>\r
- <option>\r
- <name>CCJTagBreakpointRadio</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CCJTagDoUpdateBreakpoints</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CCJTagUpdateBreakpoints</name>\r
- <state>main</state>\r
- </option>\r
- <option>\r
- <name>CCMacraigorInterfaceRadio</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CCMacraigorInterfaceCmdLine</name>\r
- <state>0</state>\r
- </option>\r
- </data>\r
- </settings>\r
- <settings>\r
- <name>RDI_ID</name>\r
- <archiveVersion>2</archiveVersion>\r
- <data>\r
- <version>1</version>\r
- <wantNonLocal>1</wantNonLocal>\r
- <debug>1</debug>\r
- <option>\r
- <name>CRDIDriverDll</name>\r
- <state>###Uninitialized###</state>\r
- </option>\r
- <option>\r
- <name>CRDILogFileCheck</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CRDILogFileEdit</name>\r
- <state>$PROJ_DIR$\cspycomm.log</state>\r
- </option>\r
- <option>\r
- <name>CCRDIHWReset</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CCRDICatchReset</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CCRDICatchUndef</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CCRDICatchSWI</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CCRDICatchData</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CCRDICatchPrefetch</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CCRDICatchIRQ</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CCRDICatchFIQ</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CCRDIUseETM</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>OCDriverInfo</name>\r
- <state>1</state>\r
- </option>\r
- </data>\r
- </settings>\r
- <settings>\r
- <name>STLINK_ID</name>\r
- <archiveVersion>2</archiveVersion>\r
- <data>\r
- <version>1</version>\r
- <wantNonLocal>1</wantNonLocal>\r
- <debug>1</debug>\r
- <option>\r
- <name>OCDriverInfo</name>\r
- <state>1</state>\r
- </option>\r
- <option>\r
- <name>CCSTLinkInterfaceRadio</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CCSTLinkInterfaceCmdLine</name>\r
- <state>0</state>\r
- </option>\r
- </data>\r
- </settings>\r
- <settings>\r
- <name>THIRDPARTY_ID</name>\r
- <archiveVersion>2</archiveVersion>\r
- <data>\r
- <version>0</version>\r
- <wantNonLocal>1</wantNonLocal>\r
- <debug>1</debug>\r
- <option>\r
- <name>CThirdPartyDriverDll</name>\r
- <state>###Uninitialized###</state>\r
- </option>\r
- <option>\r
- <name>CThirdPartyLogFileCheck</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CThirdPartyLogFileEditB</name>\r
- <state>$PROJ_DIR$\cspycomm.log</state>\r
- </option>\r
- <option>\r
- <name>OCDriverInfo</name>\r
- <state>1</state>\r
- </option>\r
- </data>\r
- </settings>\r
- <debuggerPlugins>\r
- <plugin>\r
- <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file>\r
- <loadFlag>0</loadFlag>\r
- </plugin>\r
- <plugin>\r
- <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file>\r
- <loadFlag>0</loadFlag>\r
- </plugin>\r
- <plugin>\r
- <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>\r
- <loadFlag>0</loadFlag>\r
- </plugin>\r
- <plugin>\r
- <file>$TOOLKIT_DIR$\plugins\rtos\OSE\OseEpsilonPlugin.ewplugin</file>\r
- <loadFlag>0</loadFlag>\r
- </plugin>\r
- <plugin>\r
- <file>$TOOLKIT_DIR$\plugins\rtos\PowerPac\PowerPacRTOS.ewplugin</file>\r
- <loadFlag>0</loadFlag>\r
- </plugin>\r
- <plugin>\r
- <file>$TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB5_Plugin.ewplugin</file>\r
- <loadFlag>0</loadFlag>\r
- </plugin>\r
- <plugin>\r
- <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file>\r
- <loadFlag>0</loadFlag>\r
- </plugin>\r
- <plugin>\r
- <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file>\r
- <loadFlag>0</loadFlag>\r
- </plugin>\r
- <plugin>\r
- <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>\r
- <loadFlag>0</loadFlag>\r
- </plugin>\r
- <plugin>\r
- <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin</file>\r
- <loadFlag>1</loadFlag>\r
- </plugin>\r
- <plugin>\r
- <file>$EW_DIR$\common\plugins\FreeRTOS\FreeRTOSPlugin.ewplugin</file>\r
- <loadFlag>0</loadFlag>\r
- </plugin>\r
- <plugin>\r
- <file>$EW_DIR$\common\plugins\OpenRTOS\OpenRTOSPlugin.ewplugin</file>\r
- <loadFlag>0</loadFlag>\r
- </plugin>\r
- <plugin>\r
- <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>\r
- <loadFlag>0</loadFlag>\r
- </plugin>\r
- <plugin>\r
- <file>$EW_DIR$\common\plugins\Profiling\Profiling.ENU.ewplugin</file>\r
- <loadFlag>1</loadFlag>\r
- </plugin>\r
- <plugin>\r
- <file>$EW_DIR$\common\plugins\Stack\Stack.ENU.ewplugin</file>\r
- <loadFlag>1</loadFlag>\r
- </plugin>\r
- <plugin>\r
- <file>$EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin</file>\r
- <loadFlag>1</loadFlag>\r
- </plugin>\r
- </debuggerPlugins>\r
- </configuration>\r
- <configuration>\r
- <name>Release</name>\r
- <toolchain>\r
- <name>ARM</name>\r
- </toolchain>\r
- <debug>1</debug>\r
- <settings>\r
- <name>C-SPY</name>\r
- <archiveVersion>2</archiveVersion>\r
- <data>\r
- <version>22</version>\r
- <wantNonLocal>1</wantNonLocal>\r
- <debug>1</debug>\r
- <option>\r
- <name>CInput</name>\r
- <state>1</state>\r
- </option>\r
- <option>\r
- <name>CEndian</name>\r
- <state>1</state>\r
- </option>\r
- <option>\r
- <name>CProcessor</name>\r
- <state>1</state>\r
- </option>\r
- <option>\r
- <name>OCVariant</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>MacOverride</name>\r
- <state>1</state>\r
- </option>\r
- <option>\r
- <name>MacFile</name>\r
- <state>$PROJ_DIR$\system\at91sam3u-ek-flash.mac</state>\r
- </option>\r
- <option>\r
- <name>MemOverride</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>MemFile</name>\r
- <state>$TOOLKIT_DIR$\CONFIG\debugger\Atmel\ioAT91SAM3U4.ddf</state>\r
- </option>\r
- <option>\r
- <name>RunToEnable</name>\r
- <state>1</state>\r
- </option>\r
- <option>\r
- <name>RunToName</name>\r
- <state>main</state>\r
- </option>\r
- <option>\r
- <name>CExtraOptionsCheck</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CExtraOptions</name>\r
- <state></state>\r
- </option>\r
- <option>\r
- <name>CFpuProcessor</name>\r
- <state>1</state>\r
- </option>\r
- <option>\r
- <name>OCDDFArgumentProducer</name>\r
- <state></state>\r
- </option>\r
- <option>\r
- <name>OCDownloadSuppressDownload</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>OCDownloadVerifyAll</name>\r
- <state>1</state>\r
- </option>\r
- <option>\r
- <name>OCProductVersion</name>\r
- <state>5.30.0.51236</state>\r
- </option>\r
- <option>\r
- <name>OCDynDriverList</name>\r
- <state>JLINK_ID</state>\r
- </option>\r
- <option>\r
- <name>OCLastSavedByProductVersion</name>\r
- <state>5.30.0.51236</state>\r
- </option>\r
- <option>\r
- <name>OCDownloadAttachToProgram</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>UseFlashLoader</name>\r
- <state>1</state>\r
- </option>\r
- <option>\r
- <name>CLowLevel</name>\r
- <state>1</state>\r
- </option>\r
- <option>\r
- <name>OCBE8Slave</name>\r
- <state>1</state>\r
- </option>\r
- <option>\r
- <name>MacFile2</name>\r
- <state></state>\r
- </option>\r
- <option>\r
- <name>CDevice</name>\r
- <state>1</state>\r
- </option>\r
- <option>\r
- <name>FlashLoadersV3</name>\r
- <state>$PROJ_DIR$\RTOSDemo_Release.board</state>\r
- </option>\r
- <option>\r
- <name>OCImagesSuppressCheck1</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>OCImagesPath1</name>\r
- <state></state>\r
- </option>\r
- <option>\r
- <name>OCImagesSuppressCheck2</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>OCImagesPath2</name>\r
- <state></state>\r
- </option>\r
- <option>\r
- <name>OCImagesSuppressCheck3</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>OCImagesPath3</name>\r
- <state></state>\r
- </option>\r
- <option>\r
- <name>OverrideDefFlashBoard</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>OCImagesOffset1</name>\r
- <state></state>\r
- </option>\r
- <option>\r
- <name>OCImagesOffset2</name>\r
- <state></state>\r
- </option>\r
- <option>\r
- <name>OCImagesOffset3</name>\r
- <state></state>\r
- </option>\r
- <option>\r
- <name>OCImagesUse1</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>OCImagesUse2</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>OCImagesUse3</name>\r
- <state>0</state>\r
- </option>\r
- </data>\r
- </settings>\r
- <settings>\r
- <name>ARMSIM_ID</name>\r
- <archiveVersion>2</archiveVersion>\r
<data>\r
<version>1</version>\r
<wantNonLocal>1</wantNonLocal>\r
<debug>1</debug>\r
- <option>\r
- <name>OCSimDriverInfo</name>\r
- <state>1</state>\r
- </option>\r
- <option>\r
- <name>OCSimEnablePSP</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>OCSimPspOverrideConfig</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>OCSimPspConfigFile</name>\r
- <state></state>\r
- </option>\r
- </data>\r
- </settings>\r
- <settings>\r
- <name>ANGEL_ID</name>\r
- <archiveVersion>2</archiveVersion>\r
- <data>\r
- <version>0</version>\r
- <wantNonLocal>1</wantNonLocal>\r
- <debug>1</debug>\r
- <option>\r
- <name>CCAngelHeartbeat</name>\r
- <state>1</state>\r
- </option>\r
- <option>\r
- <name>CAngelCommunication</name>\r
- <state>1</state>\r
- </option>\r
- <option>\r
- <name>CAngelCommBaud</name>\r
- <version>0</version>\r
- <state>3</state>\r
- </option>\r
- <option>\r
- <name>CAngelCommPort</name>\r
- <version>0</version>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>ANGELTCPIP</name>\r
- <state>aaa.bbb.ccc.ddd</state>\r
- </option>\r
- <option>\r
- <name>DoAngelLogfile</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>AngelLogFile</name>\r
- <state>$PROJ_DIR$\cspycomm.log</state>\r
- </option>\r
- <option>\r
- <name>OCDriverInfo</name>\r
- <state>1</state>\r
- </option>\r
- </data>\r
- </settings>\r
- <settings>\r
- <name>GDBSERVER_ID</name>\r
- <archiveVersion>2</archiveVersion>\r
- <data>\r
- <version>0</version>\r
- <wantNonLocal>1</wantNonLocal>\r
- <debug>1</debug>\r
- <option>\r
- <name>OCDriverInfo</name>\r
- <state>1</state>\r
- </option>\r
- <option>\r
- <name>TCPIP</name>\r
- <state>aaa.bbb.ccc.ddd</state>\r
- </option>\r
- <option>\r
- <name>DoLogfile</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>LogFile</name>\r
- <state>$PROJ_DIR$\cspycomm.log</state>\r
- </option>\r
- <option>\r
- <name>CCJTagBreakpointRadio</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CCJTagDoUpdateBreakpoints</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CCJTagUpdateBreakpoints</name>\r
- <state>main</state>\r
- </option>\r
- </data>\r
- </settings>\r
- <settings>\r
- <name>IARROM_ID</name>\r
- <archiveVersion>2</archiveVersion>\r
- <data>\r
- <version>0</version>\r
- <wantNonLocal>1</wantNonLocal>\r
- <debug>1</debug>\r
<option>\r
<name>CRomLogFileCheck</name>\r
<state>0</state>\r
<name>CRomLogFileEditB</name>\r
<state>$PROJ_DIR$\cspycomm.log</state>\r
</option>\r
- <option>\r
- <name>CRomCommunication</name>\r
- <state>0</state>\r
- </option>\r
<option>\r
<name>CRomCommPort</name>\r
<version>0</version>\r
<name>JLINK_ID</name>\r
<archiveVersion>2</archiveVersion>\r
<data>\r
- <version>11</version>\r
+ <version>13</version>\r
<wantNonLocal>1</wantNonLocal>\r
<debug>1</debug>\r
<option>\r
</option>\r
<option>\r
<name>CCUSBDevice</name>\r
- <version>0</version>\r
- <state>0</state>\r
+ <version>1</version>\r
+ <state>1</state>\r
</option>\r
<option>\r
<name>CCRDICatchReset</name>\r
</option>\r
<option>\r
<name>CCJLinkResetList</name>\r
- <version>2</version>\r
+ <version>5</version>\r
<state>7</state>\r
</option>\r
<option>\r
<name>CCCatchDummy</name>\r
<state>0</state>\r
</option>\r
+ <option>\r
+ <name>OCJLinkScriptFile</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkUsbSerialNo</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCTcpIpAlt</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkTcpIpSerialNo</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCCpuClockEdit</name>\r
+ <state>72.0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSwoClockAuto</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSwoClockEdit</name>\r
+ <state>2000</state>\r
+ </option>\r
</data>\r
</settings>\r
<settings>\r
</option>\r
</data>\r
</settings>\r
+ <settings>\r
+ <name>PEMICRO_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>0</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OCPEMicroAttachSlave</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPEMicroInterfaceList</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPEMicroResetDelay</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCPEMicroJtagSpeed</name>\r
+ <state>#UNINITIALIZED#</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJPEMicroShowSettings</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>DoLogfile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>LogFile</name>\r
+ <state>$PROJ_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPEMicroUSBDevice</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPEMicroSerialPort</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJPEMicroTCPIPAutoScanNetwork</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPEMicroTCPIP</name>\r
+ <state>10.0.0.1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPEMicroCommCmdLineProducer</name>\r
+ <state>0</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
<settings>\r
<name>RDI_ID</name>\r
<archiveVersion>2</archiveVersion>\r
<data>\r
- <version>1</version>\r
+ <version>2</version>\r
<wantNonLocal>1</wantNonLocal>\r
<debug>1</debug>\r
<option>\r
<name>CCRDICatchFIQ</name>\r
<state>0</state>\r
</option>\r
- <option>\r
- <name>CCRDIUseETM</name>\r
- <state>0</state>\r
- </option>\r
<option>\r
<name>OCDriverInfo</name>\r
<state>1</state>\r
<name>STLINK_ID</name>\r
<archiveVersion>2</archiveVersion>\r
<data>\r
- <version>1</version>\r
+ <version>2</version>\r
<wantNonLocal>1</wantNonLocal>\r
<debug>1</debug>\r
<option>\r
<name>CCSTLinkInterfaceCmdLine</name>\r
<state>0</state>\r
</option>\r
+ <option>\r
+ <name>CCSTLinkResetList</name>\r
+ <version>1</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCpuClockEdit</name>\r
+ <state>72.0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSwoClockAuto</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSwoClockEdit</name>\r
+ <state>2000</state>\r
+ </option>\r
</data>\r
</settings>\r
<settings>\r
<loadFlag>0</loadFlag>\r
</plugin>\r
<plugin>\r
- <file>$TOOLKIT_DIR$\plugins\rtos\OSE\OseEpsilonPlugin.ewplugin</file>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file>\r
<loadFlag>0</loadFlag>\r
</plugin>\r
<plugin>\r
<loadFlag>0</loadFlag>\r
</plugin>\r
<plugin>\r
- <file>$TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB5_Plugin.ewplugin</file>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB6_Plugin.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file>\r
<loadFlag>0</loadFlag>\r
</plugin>\r
<plugin>\r
<file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>\r
<loadFlag>0</loadFlag>\r
</plugin>\r
- <plugin>\r
- <file>$EW_DIR$\common\plugins\Profiling\Profiling.ENU.ewplugin</file>\r
- <loadFlag>1</loadFlag>\r
- </plugin>\r
<plugin>\r
<file>$EW_DIR$\common\plugins\Stack\Stack.ENU.ewplugin</file>\r
<loadFlag>1</loadFlag>\r
<name>General</name>\r
<archiveVersion>3</archiveVersion>\r
<data>\r
- <version>17</version>\r
+ <version>21</version>\r
<wantNonLocal>1</wantNonLocal>\r
<debug>1</debug>\r
<option>\r
</option>\r
<option>\r
<name>Variant</name>\r
- <version>17</version>\r
+ <version>19</version>\r
<state>37</state>\r
</option>\r
<option>\r
</option>\r
<option>\r
<name>Input variant</name>\r
- <version>1</version>\r
- <state>3</state>\r
+ <version>3</version>\r
+ <state>6</state>\r
</option>\r
<option>\r
<name>Input description</name>\r
</option>\r
<option>\r
<name>Output variant</name>\r
- <version>0</version>\r
- <state>3</state>\r
+ <version>2</version>\r
+ <state>7</state>\r
</option>\r
<option>\r
<name>Output description</name>\r
</option>\r
<option>\r
<name>FPU</name>\r
- <version>1</version>\r
+ <version>2</version>\r
<state>0</state>\r
</option>\r
<option>\r
<name>RTDescription</name>\r
<state>Use the normal configuration of the C/C++ runtime library. No locale interface, C locale, no file descriptor support, no multibytes in printf and scanf, and no hex floats in strtod.</state>\r
</option>\r
- <option>\r
- <name>RTConfigPath</name>\r
- <state>$TOOLKIT_DIR$\INC\DLib_Config_Normal.h</state>\r
- </option>\r
<option>\r
<name>OGProductVersion</name>\r
<state>5.10.0.159</state>\r
</option>\r
<option>\r
<name>OGLastSavedByProductVersion</name>\r
- <state>5.30.0.51236</state>\r
+ <state>6.20.1.52589</state>\r
</option>\r
<option>\r
<name>GeneralEnableMisra</name>\r
<version>0</version>\r
<state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>\r
</option>\r
+ <option>\r
+ <name>RTConfigPath2</name>\r
+ <state>$TOOLKIT_DIR$\INC\c\DLib_Config_Normal.h</state>\r
+ </option>\r
+ <option>\r
+ <name>GFPUCoreSlave</name>\r
+ <version>19</version>\r
+ <state>37</state>\r
+ </option>\r
+ <option>\r
+ <name>GBECoreSlave</name>\r
+ <version>19</version>\r
+ <state>37</state>\r
+ </option>\r
+ <option>\r
+ <name>OGUseCmsis</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OGUseCmsisDspLib</name>\r
+ <state>0</state>\r
+ </option>\r
</data>\r
</settings>\r
<settings>\r
<name>ICCARM</name>\r
<archiveVersion>2</archiveVersion>\r
<data>\r
- <version>22</version>\r
+ <version>28</version>\r
<wantNonLocal>1</wantNonLocal>\r
<debug>1</debug>\r
<option>\r
<name>OutputFile</name>\r
<state>$FILE_BNAME$.o</state>\r
</option>\r
- <option>\r
- <name>CCLangSelect</name>\r
- <state>0</state>\r
- </option>\r
<option>\r
<name>CCLibConfigHeader</name>\r
<state>1</state>\r
<name>CCStdIncCheck</name>\r
<state>0</state>\r
</option>\r
- <option>\r
- <name>CCStdIncludePath</name>\r
- <state>$TOOLKIT_DIR$\INC\</state>\r
- </option>\r
<option>\r
<name>CCCodeSection</name>\r
<state>.text</state>\r
<name>CCPosIndNoDynInit</name>\r
<state>0</state>\r
</option>\r
+ <option>\r
+ <name>IccLang</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IccCDialect</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IccAllowVLA</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IccCppDialect</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IccExceptions</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IccRTTI</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IccStaticDestr</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IccCppInlineSemantics</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IccCmsis</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IccFloatSemantics</name>\r
+ <state>0</state>\r
+ </option>\r
</data>\r
</settings>\r
<settings>\r
<name>AARM</name>\r
<archiveVersion>2</archiveVersion>\r
<data>\r
- <version>7</version>\r
+ <version>8</version>\r
<wantNonLocal>1</wantNonLocal>\r
<debug>1</debug>\r
<option>\r
<name>AIgnoreStdInclude</name>\r
<state>0</state>\r
</option>\r
- <option>\r
- <name>AStdIncludes</name>\r
- <state>$TOOLKIT_DIR$\INC\</state>\r
- </option>\r
<option>\r
<name>AUserIncludes</name>\r
<state>$PROJ_DIR$/.</state>\r
<name>ILINK</name>\r
<archiveVersion>0</archiveVersion>\r
<data>\r
- <version>9</version>\r
+ <version>13</version>\r
<wantNonLocal>1</wantNonLocal>\r
<debug>1</debug>\r
<option>\r
<name>IlinkLogUnusedFragments</name>\r
<state>0</state>\r
</option>\r
- </data>\r
- </settings>\r
- <settings>\r
- <name>IARCHIVE</name>\r
- <archiveVersion>0</archiveVersion>\r
- <data>\r
- <version>0</version>\r
- <wantNonLocal>1</wantNonLocal>\r
- <debug>1</debug>\r
- <option>\r
- <name>IarchiveInputs</name>\r
- <state></state>\r
- </option>\r
- <option>\r
- <name>IarchiveOverride</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>IarchiveOutput</name>\r
- <state>###Unitialized###</state>\r
- </option>\r
- </data>\r
- </settings>\r
- <settings>\r
- <name>BILINK</name>\r
- <archiveVersion>0</archiveVersion>\r
- <data/>\r
- </settings>\r
- </configuration>\r
- <configuration>\r
- <name>Release</name>\r
- <toolchain>\r
- <name>ARM</name>\r
- </toolchain>\r
- <debug>1</debug>\r
- <settings>\r
- <name>General</name>\r
- <archiveVersion>3</archiveVersion>\r
- <data>\r
- <version>17</version>\r
- <wantNonLocal>1</wantNonLocal>\r
- <debug>1</debug>\r
- <option>\r
- <name>ExePath</name>\r
- <state>Release\Exe</state>\r
- </option>\r
- <option>\r
- <name>ObjPath</name>\r
- <state>Release\Obj</state>\r
- </option>\r
- <option>\r
- <name>ListPath</name>\r
- <state>Release\List</state>\r
- </option>\r
- <option>\r
- <name>Variant</name>\r
- <version>17</version>\r
- <state>37</state>\r
- </option>\r
- <option>\r
- <name>GEndianMode</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>Input variant</name>\r
- <version>1</version>\r
- <state>3</state>\r
- </option>\r
- <option>\r
- <name>Input description</name>\r
- <state>No specifier n, no float nor long long, no scan set, no assignment suppressing.</state>\r
- </option>\r
- <option>\r
- <name>Output variant</name>\r
- <version>0</version>\r
- <state>3</state>\r
- </option>\r
- <option>\r
- <name>Output description</name>\r
- <state>No specifier a, A, no specifier n, no float nor long long, no flags.</state>\r
- </option>\r
- <option>\r
- <name>GOutputBinary</name>\r
- <state>0</state>\r
- </option>\r
<option>\r
- <name>FPU</name>\r
- <version>1</version>\r
+ <name>IlinkCrcReverseByteOrder</name>\r
<state>0</state>\r
</option>\r
<option>\r
- <name>OGCoreOrChip</name>\r
- <state>1</state>\r
- </option>\r
- <option>\r
- <name>GRuntimeLibSelect</name>\r
- <version>0</version>\r
- <state>1</state>\r
- </option>\r
- <option>\r
- <name>GRuntimeLibSelectSlave</name>\r
- <version>0</version>\r
+ <name>IlinkCrcUseAsInput</name>\r
<state>1</state>\r
</option>\r
<option>\r
- <name>RTDescription</name>\r
- <state>Use the normal configuration of the C/C++ runtime library. No locale interface, C locale, no file descriptor support, no multibytes in printf and scanf, and no hex floats in strtod.</state>\r
- </option>\r
- <option>\r
- <name>RTConfigPath</name>\r
- <state>$TOOLKIT_DIR$\INC\DLib_Config_Normal.h</state>\r
- </option>\r
- <option>\r
- <name>OGProductVersion</name>\r
- <state>5.10.0.159</state>\r
- </option>\r
- <option>\r
- <name>OGLastSavedByProductVersion</name>\r
- <state>5.30.0.51236</state>\r
- </option>\r
- <option>\r
- <name>GeneralEnableMisra</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>GeneralMisraVerbose</name>\r
+ <name>IlinkOptInline</name>\r
<state>0</state>\r
</option>\r
<option>\r
- <name>OGChipSelectEditMenu</name>\r
- <state>AT91SAM3U4 Atmel AT91SAM3U4</state>\r
- </option>\r
- <option>\r
- <name>GenLowLevelInterface</name>\r
- <state>1</state>\r
- </option>\r
- <option>\r
- <name>GEndianModeBE</name>\r
+ <name>IlinkOptExceptionsAllow</name>\r
<state>1</state>\r
</option>\r
<option>\r
- <name>OGBufferedTerminalOutput</name>\r
+ <name>IlinkOptExceptionsForce</name>\r
<state>0</state>\r
</option>\r
<option>\r
- <name>GenStdoutInterface</name>\r
+ <name>IlinkCmsis</name>\r
<state>1</state>\r
</option>\r
<option>\r
- <name>GeneralMisraRules98</name>\r
- <version>0</version>\r
- <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>\r
- </option>\r
- <option>\r
- <name>GeneralMisraVer</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>GeneralMisraRules04</name>\r
- <version>0</version>\r
- <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>\r
- </option>\r
- </data>\r
- </settings>\r
- <settings>\r
- <name>ICCARM</name>\r
- <archiveVersion>2</archiveVersion>\r
- <data>\r
- <version>22</version>\r
- <wantNonLocal>1</wantNonLocal>\r
- <debug>1</debug>\r
- <option>\r
- <name>CCDefines</name>\r
- <state>at91sam3u4</state>\r
- <state>flash</state>\r
- </option>\r
- <option>\r
- <name>CCPreprocFile</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CCPreprocComments</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CCPreprocLine</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CCListCFile</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CCListCMnemonics</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CCListCMessages</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CCListAssFile</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CCListAssSource</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CCEnableRemarks</name>\r
+ <name>IlinkOptMergeDuplSections</name>\r
<state>0</state>\r
</option>\r
<option>\r
- <name>CCDiagSuppress</name>\r
- <state>pa082</state>\r
- </option>\r
- <option>\r
- <name>CCDiagRemark</name>\r
- <state></state>\r
- </option>\r
- <option>\r
- <name>CCDiagWarning</name>\r
- <state></state>\r
- </option>\r
- <option>\r
- <name>CCDiagError</name>\r
- <state></state>\r
- </option>\r
- <option>\r
- <name>CCObjPrefix</name>\r
+ <name>IlinkOptUseVfe</name>\r
<state>1</state>\r
</option>\r
<option>\r
- <name>CCAllowList</name>\r
- <version>1</version>\r
- <state>1111101</state>\r
- </option>\r
- <option>\r
- <name>CCDebugInfo</name>\r
- <state>1</state>\r
- </option>\r
- <option>\r
- <name>IEndianMode</name>\r
- <state>1</state>\r
- </option>\r
- <option>\r
- <name>IProcessor</name>\r
- <state>1</state>\r
- </option>\r
- <option>\r
- <name>IExtraOptionsCheck</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>IExtraOptions</name>\r
- <state></state>\r
- </option>\r
- <option>\r
- <name>CCLangConformance</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CCSignedPlainChar</name>\r
- <state>1</state>\r
- </option>\r
- <option>\r
- <name>CCRequirePrototypes</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CCMultibyteSupport</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CCDiagWarnAreErr</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CCCompilerRuntimeInfo</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>IFpuProcessor</name>\r
- <state>1</state>\r
- </option>\r
- <option>\r
- <name>OutputFile</name>\r
- <state>$FILE_BNAME$.o</state>\r
- </option>\r
- <option>\r
- <name>CCLangSelect</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CCLibConfigHeader</name>\r
- <state>1</state>\r
- </option>\r
- <option>\r
- <name>PreInclude</name>\r
- <state></state>\r
- </option>\r
- <option>\r
- <name>CompilerMisraOverride</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CCIncludePath2</name>\r
- <state>$PROJ_DIR$/system</state>\r
- <state>$PROJ_DIR$/AT91Lib/peripherals</state>\r
- <state>$PROJ_DIR$/AT91Lib/components</state>\r
- <state>$PROJ_DIR$/AT91Lib/drivers</state>\r
- <state>$PROJ_DIR$/AT91Lib</state>\r
- <state>$PROJ_DIR$/../../Source/include</state>\r
- <state>$PROJ_DIR$/../../Source/portable/IAR/ARM_CM3</state>\r
- <state>$PROJ_DIR$/.</state>\r
- <state>$PROJ_DIR$/../common/include</state>\r
- </option>\r
- <option>\r
- <name>CCStdIncCheck</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CCStdIncludePath</name>\r
- <state>$TOOLKIT_DIR$\INC\</state>\r
- </option>\r
- <option>\r
- <name>CCCodeSection</name>\r
- <state>.text</state>\r
- </option>\r
- <option>\r
- <name>IInterwork2</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>IProcessorMode2</name>\r
- <state>1</state>\r
- </option>\r
- <option>\r
- <name>CCOptLevel</name>\r
- <state>3</state>\r
- </option>\r
- <option>\r
- <name>CCOptStrategy</name>\r
- <version>0</version>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CCOptLevelSlave</name>\r
- <state>3</state>\r
- </option>\r
- <option>\r
- <name>CompilerMisraRules98</name>\r
- <version>0</version>\r
- <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>\r
- </option>\r
- <option>\r
- <name>CompilerMisraRules04</name>\r
- <version>0</version>\r
- <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>\r
- </option>\r
- <option>\r
- <name>CCPosIndRopi</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CCPosIndRwpi</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CCPosIndNoDynInit</name>\r
- <state>0</state>\r
- </option>\r
- </data>\r
- </settings>\r
- <settings>\r
- <name>AARM</name>\r
- <archiveVersion>2</archiveVersion>\r
- <data>\r
- <version>7</version>\r
- <wantNonLocal>1</wantNonLocal>\r
- <debug>1</debug>\r
- <option>\r
- <name>AObjPrefix</name>\r
- <state>1</state>\r
- </option>\r
- <option>\r
- <name>AEndian</name>\r
- <state>1</state>\r
- </option>\r
- <option>\r
- <name>ACaseSensitivity</name>\r
- <state>1</state>\r
- </option>\r
- <option>\r
- <name>MacroChars</name>\r
- <version>0</version>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>AWarnEnable</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>AWarnWhat</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>AWarnOne</name>\r
- <state></state>\r
- </option>\r
- <option>\r
- <name>AWarnRange1</name>\r
- <state></state>\r
- </option>\r
- <option>\r
- <name>AWarnRange2</name>\r
- <state></state>\r
- </option>\r
- <option>\r
- <name>ADebug</name>\r
- <state>1</state>\r
- </option>\r
- <option>\r
- <name>AltRegisterNames</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>ADefines</name>\r
- <state></state>\r
- </option>\r
- <option>\r
- <name>AList</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>AListHeader</name>\r
- <state>1</state>\r
- </option>\r
- <option>\r
- <name>AListing</name>\r
- <state>1</state>\r
- </option>\r
- <option>\r
- <name>Includes</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>MacDefs</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>MacExps</name>\r
- <state>1</state>\r
- </option>\r
- <option>\r
- <name>MacExec</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>OnlyAssed</name>\r
- <state>0</state>\r
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- <option>\r
- <name>MultiLine</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>PageLengthCheck</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>PageLength</name>\r
- <state>80</state>\r
- </option>\r
- <option>\r
- <name>TabSpacing</name>\r
- <state>8</state>\r
- </option>\r
- <option>\r
- <name>AXRef</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>AXRefDefines</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>AXRefInternal</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>AXRefDual</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>AProcessor</name>\r
- <state>1</state>\r
- </option>\r
- <option>\r
- <name>AFpuProcessor</name>\r
- <state>1</state>\r
- </option>\r
- <option>\r
- <name>AOutputFile</name>\r
- <state>$FILE_BNAME$.o</state>\r
- </option>\r
- <option>\r
- <name>AMultibyteSupport</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>ALimitErrorsCheck</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>ALimitErrorsEdit</name>\r
- <state>100</state>\r
- </option>\r
- <option>\r
- <name>AIgnoreStdInclude</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>AStdIncludes</name>\r
- <state>$TOOLKIT_DIR$\INC\</state>\r
- </option>\r
- <option>\r
- <name>AUserIncludes</name>\r
- <state>$PROJ_DIR$/.</state>\r
- </option>\r
- <option>\r
- <name>AExtraOptionsCheckV2</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>AExtraOptionsV2</name>\r
- <state></state>\r
- </option>\r
- </data>\r
- </settings>\r
- <settings>\r
- <name>OBJCOPY</name>\r
- <archiveVersion>0</archiveVersion>\r
- <data>\r
- <version>1</version>\r
- <wantNonLocal>1</wantNonLocal>\r
- <debug>1</debug>\r
- <option>\r
- <name>OOCOutputFormat</name>\r
- <version>2</version>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>OCOutputOverride</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>OOCOutputFile</name>\r
- <state>RTOSDemo.srec</state>\r
- </option>\r
- <option>\r
- <name>OOCCommandLineProducer</name>\r
- <state>1</state>\r
- </option>\r
- <option>\r
- <name>OOCObjCopyEnable</name>\r
- <state>0</state>\r
- </option>\r
- </data>\r
- </settings>\r
- <settings>\r
- <name>CUSTOM</name>\r
- <archiveVersion>3</archiveVersion>\r
- <data>\r
- <extensions></extensions>\r
- <cmdline></cmdline>\r
- </data>\r
- </settings>\r
- <settings>\r
- <name>BICOMP</name>\r
- <archiveVersion>0</archiveVersion>\r
- <data/>\r
- </settings>\r
- <settings>\r
- <name>BUILDACTION</name>\r
- <archiveVersion>1</archiveVersion>\r
- <data>\r
- <prebuild></prebuild>\r
- <postbuild></postbuild>\r
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- </settings>\r
- <settings>\r
- <name>ILINK</name>\r
- <archiveVersion>0</archiveVersion>\r
- <data>\r
- <version>9</version>\r
- <wantNonLocal>1</wantNonLocal>\r
- <debug>1</debug>\r
- <option>\r
- <name>IlinkOutputFile</name>\r
- <state>RTOSDemo.out</state>\r
- </option>\r
- <option>\r
- <name>IlinkLibIOConfig</name>\r
- <state>1</state>\r
- </option>\r
- <option>\r
- <name>XLinkMisraHandler</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>IlinkInputFileSlave</name>\r
- <state>0</state>\r
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- <option>\r
- <name>IlinkDebugInfoEnable</name>\r
- <state>1</state>\r
- </option>\r
- <option>\r
- <name>IlinkKeepSymbols</name>\r
- <state></state>\r
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- <option>\r
- <name>IlinkRawBinaryFile</name>\r
- <state></state>\r
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- <option>\r
- <name>IlinkRawBinarySymbol</name>\r
- <state></state>\r
- </option>\r
- <option>\r
- <name>IlinkRawBinarySegment</name>\r
- <state></state>\r
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- <option>\r
- <name>IlinkRawBinaryAlign</name>\r
- <state></state>\r
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- <option>\r
- <name>IlinkDefines</name>\r
- <state></state>\r
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- <option>\r
- <name>IlinkConfigDefines</name>\r
- <state></state>\r
- </option>\r
- <option>\r
- <name>IlinkMapFile</name>\r
- <state>0</state>\r
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- <option>\r
- <name>IlinkLogFile</name>\r
- <state>0</state>\r
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- <option>\r
- <name>IlinkLogInitialization</name>\r
- <state>0</state>\r
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- <option>\r
- <name>IlinkLogModule</name>\r
- <state>0</state>\r
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- <option>\r
- <name>IlinkLogSection</name>\r
- <state>0</state>\r
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- <option>\r
- <name>IlinkLogVeneer</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>IlinkIcfOverride</name>\r
- <state>1</state>\r
- </option>\r
- <option>\r
- <name>IlinkIcfFile</name>\r
- <state>C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\CORTEX_AT91SAM3U256_IAR\system\flash.icf</state>\r
- </option>\r
- <option>\r
- <name>IlinkIcfFileSlave</name>\r
- <state></state>\r
- </option>\r
- <option>\r
- <name>IlinkEnableRemarks</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>IlinkSuppressDiags</name>\r
- <state></state>\r
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+@REM This batch file has been generated by the IAR Embedded Workbench\r
+@REM C-SPY Debugger, as an aid to preparing a command line for running\r
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+@REM by the name of the debug file (usually an ELF/DWARF or UBROF file).\r
+@REM Note that this file is generated every time a new debug session\r
+@REM is initialized, so you may want to move or rename the file before\r
+@REM making changes.\r
+@REM \r
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-/**************************************************************************//**\r
- * @file core_cm3.h\r
- * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File\r
- * @version V1.30\r
- * @date 30. October 2009\r
- *\r
- * @note\r
- * Copyright (C) 2009 ARM Limited. All rights reserved.\r
- *\r
- * @par\r
- * ARM Limited (ARM) is supplying this software for use with Cortex-M \r
- * processor based microcontrollers. This file can be freely distributed \r
- * within development tools that are supporting such ARM based processors. \r
- *\r
- * @par\r
- * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
- * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
- *\r
- ******************************************************************************/\r
-\r
-#ifndef __CM3_CORE_H__\r
-#define __CM3_CORE_H__\r
-\r
-/** @addtogroup CMSIS_CM3_core_LintCinfiguration CMSIS CM3 Core Lint Configuration\r
- *\r
- * List of Lint messages which will be suppressed and not shown:\r
- * - Error 10: \n\r
- * register uint32_t __regBasePri __asm("basepri"); \n\r
- * Error 10: Expecting ';'\r
- * .\r
- * - Error 530: \n\r
- * return(__regBasePri); \n\r
- * Warning 530: Symbol '__regBasePri' (line 264) not initialized\r
- * . \r
- * - Error 550: \n\r
- * __regBasePri = (basePri & 0x1ff); \n\r
- * Warning 550: Symbol '__regBasePri' (line 271) not accessed\r
- * .\r
- * - Error 754: \n\r
- * uint32_t RESERVED0[24]; \n\r
- * Info 754: local structure member '<some, not used in the HAL>' (line 109, file ./cm3_core.h) not referenced\r
- * .\r
- * - Error 750: \n\r
- * #define __CM3_CORE_H__ \n\r
- * Info 750: local macro '__CM3_CORE_H__' (line 43, file./cm3_core.h) not referenced\r
- * .\r
- * - Error 528: \n\r
- * static __INLINE void NVIC_DisableIRQ(uint32_t IRQn) \n\r
- * Warning 528: Symbol 'NVIC_DisableIRQ(unsigned int)' (line 419, file ./cm3_core.h) not referenced\r
- * .\r
- * - Error 751: \n\r
- * } InterruptType_Type; \n\r
- * Info 751: local typedef 'InterruptType_Type' (line 170, file ./cm3_core.h) not referenced\r
- * .\r
- * Note: To re-enable a Message, insert a space before 'lint' *\r
- *\r
- */\r
-\r
-/*lint -save */\r
-/*lint -e10 */\r
-/*lint -e530 */\r
-/*lint -e550 */\r
-/*lint -e754 */\r
-/*lint -e750 */\r
-/*lint -e528 */\r
-/*lint -e751 */\r
-\r
-\r
-/** @addtogroup CMSIS_CM3_core_definitions CM3 Core Definitions\r
- This file defines all structures and symbols for CMSIS core:\r
- - CMSIS version number\r
- - Cortex-M core registers and bitfields\r
- - Cortex-M core peripheral base address\r
- @{\r
- */\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif \r
-\r
-#define __CM3_CMSIS_VERSION_MAIN (0x01) /*!< [31:16] CMSIS HAL main version */\r
-#define __CM3_CMSIS_VERSION_SUB (0x30) /*!< [15:0] CMSIS HAL sub version */\r
-#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */\r
-\r
-#define __CORTEX_M (0x03) /*!< Cortex core */\r
-\r
-#include <stdint.h> /* Include standard types */\r
-\r
-#if defined (__ICCARM__)\r
- #include <intrinsics.h> /* IAR Intrinsics */\r
-#endif\r
-\r
-\r
-#ifndef __NVIC_PRIO_BITS\r
- #define __NVIC_PRIO_BITS 4 /*!< standard definition for NVIC Priority Bits */\r
-#endif\r
-\r
-\r
-\r
-\r
-/**\r
- * IO definitions\r
- *\r
- * define access restrictions to peripheral registers\r
- */\r
-\r
-#ifdef __cplusplus\r
- #define __I volatile /*!< defines 'read only' permissions */\r
-#else\r
- #define __I volatile const /*!< defines 'read only' permissions */\r
-#endif\r
-#define __O volatile /*!< defines 'write only' permissions */\r
-#define __IO volatile /*!< defines 'read / write' permissions */\r
-\r
-\r
-\r
-/*******************************************************************************\r
- * Register Abstraction\r
- ******************************************************************************/\r
-/** @addtogroup CMSIS_CM3_core_register CMSIS CM3 Core Register\r
- @{\r
-*/\r
-\r
-\r
-/** @addtogroup CMSIS_CM3_NVIC CMSIS CM3 NVIC\r
- memory mapped structure for Nested Vectored Interrupt Controller (NVIC)\r
- @{\r
- */\r
-typedef struct\r
-{\r
- __IO uint32_t ISER[8]; /*!< Offset: 0x000 Interrupt Set Enable Register */\r
- uint32_t RESERVED0[24]; \r
- __IO uint32_t ICER[8]; /*!< Offset: 0x080 Interrupt Clear Enable Register */\r
- uint32_t RSERVED1[24]; \r
- __IO uint32_t ISPR[8]; /*!< Offset: 0x100 Interrupt Set Pending Register */\r
- uint32_t RESERVED2[24]; \r
- __IO uint32_t ICPR[8]; /*!< Offset: 0x180 Interrupt Clear Pending Register */\r
- uint32_t RESERVED3[24]; \r
- __IO uint32_t IABR[8]; /*!< Offset: 0x200 Interrupt Active bit Register */\r
- uint32_t RESERVED4[56]; \r
- __IO uint8_t IP[240]; /*!< Offset: 0x300 Interrupt Priority Register (8Bit wide) */\r
- uint32_t RESERVED5[644]; \r
- __O uint32_t STIR; /*!< Offset: 0xE00 Software Trigger Interrupt Register */\r
-} NVIC_Type; \r
-/*@}*/ /* end of group CMSIS_CM3_NVIC */\r
-\r
-\r
-/** @addtogroup CMSIS_CM3_SCB CMSIS CM3 SCB\r
- memory mapped structure for System Control Block (SCB)\r
- @{\r
- */\r
-typedef struct\r
-{\r
- __I uint32_t CPUID; /*!< Offset: 0x00 CPU ID Base Register */\r
- __IO uint32_t ICSR; /*!< Offset: 0x04 Interrupt Control State Register */\r
- __IO uint32_t VTOR; /*!< Offset: 0x08 Vector Table Offset Register */\r
- __IO uint32_t AIRCR; /*!< Offset: 0x0C Application Interrupt / Reset Control Register */\r
- __IO uint32_t SCR; /*!< Offset: 0x10 System Control Register */\r
- __IO uint32_t CCR; /*!< Offset: 0x14 Configuration Control Register */\r
- __IO uint8_t SHP[12]; /*!< Offset: 0x18 System Handlers Priority Registers (4-7, 8-11, 12-15) */\r
- __IO uint32_t SHCSR; /*!< Offset: 0x24 System Handler Control and State Register */\r
- __IO uint32_t CFSR; /*!< Offset: 0x28 Configurable Fault Status Register */\r
- __IO uint32_t HFSR; /*!< Offset: 0x2C Hard Fault Status Register */\r
- __IO uint32_t DFSR; /*!< Offset: 0x30 Debug Fault Status Register */\r
- __IO uint32_t MMFAR; /*!< Offset: 0x34 Mem Manage Address Register */\r
- __IO uint32_t BFAR; /*!< Offset: 0x38 Bus Fault Address Register */\r
- __IO uint32_t AFSR; /*!< Offset: 0x3C Auxiliary Fault Status Register */\r
- __I uint32_t PFR[2]; /*!< Offset: 0x40 Processor Feature Register */\r
- __I uint32_t DFR; /*!< Offset: 0x48 Debug Feature Register */\r
- __I uint32_t ADR; /*!< Offset: 0x4C Auxiliary Feature Register */\r
- __I uint32_t MMFR[4]; /*!< Offset: 0x50 Memory Model Feature Register */\r
- __I uint32_t ISAR[5]; /*!< Offset: 0x60 ISA Feature Register */\r
-} SCB_Type; \r
-\r
-/* SCB CPUID Register Definitions */\r
-#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */\r
-#define SCB_CPUID_IMPLEMENTER_Msk (0xFFul << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */\r
-\r
-#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */\r
-#define SCB_CPUID_VARIANT_Msk (0xFul << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */\r
-\r
-#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */\r
-#define SCB_CPUID_PARTNO_Msk (0xFFFul << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */\r
-\r
-#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */\r
-#define SCB_CPUID_REVISION_Msk (0xFul << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */\r
-\r
-/* SCB Interrupt Control State Register Definitions */\r
-#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */\r
-#define SCB_ICSR_NMIPENDSET_Msk (1ul << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */\r
-\r
-#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */\r
-#define SCB_ICSR_PENDSVSET_Msk (1ul << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */\r
-\r
-#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */\r
-#define SCB_ICSR_PENDSVCLR_Msk (1ul << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */\r
-\r
-#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */\r
-#define SCB_ICSR_PENDSTSET_Msk (1ul << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */\r
-\r
-#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */\r
-#define SCB_ICSR_PENDSTCLR_Msk (1ul << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */\r
-\r
-#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */\r
-#define SCB_ICSR_ISRPREEMPT_Msk (1ul << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */\r
-\r
-#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */\r
-#define SCB_ICSR_ISRPENDING_Msk (1ul << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */\r
-\r
-#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */\r
-#define SCB_ICSR_VECTPENDING_Msk (0x1FFul << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */\r
-\r
-#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */\r
-#define SCB_ICSR_RETTOBASE_Msk (1ul << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */\r
-\r
-#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */\r
-#define SCB_ICSR_VECTACTIVE_Msk (0x1FFul << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */\r
-\r
-/* SCB Interrupt Control State Register Definitions */\r
-#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */\r
-#define SCB_VTOR_TBLBASE_Msk (0x1FFul << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */\r
-\r
-#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */\r
-#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFul << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */\r
-\r
-/* SCB Application Interrupt and Reset Control Register Definitions */\r
-#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */\r
-#define SCB_AIRCR_VECTKEY_Msk (0xFFFFul << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */\r
-\r
-#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */\r
-#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFul << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */\r
-\r
-#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */\r
-#define SCB_AIRCR_ENDIANESS_Msk (1ul << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */\r
-\r
-#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */\r
-#define SCB_AIRCR_PRIGROUP_Msk (7ul << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */\r
-\r
-#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */\r
-#define SCB_AIRCR_SYSRESETREQ_Msk (1ul << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */\r
-\r
-#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */\r
-#define SCB_AIRCR_VECTCLRACTIVE_Msk (1ul << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r
-\r
-#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */\r
-#define SCB_AIRCR_VECTRESET_Msk (1ul << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */\r
-\r
-/* SCB System Control Register Definitions */\r
-#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */\r
-#define SCB_SCR_SEVONPEND_Msk (1ul << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */\r
-\r
-#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */\r
-#define SCB_SCR_SLEEPDEEP_Msk (1ul << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */\r
-\r
-#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */\r
-#define SCB_SCR_SLEEPONEXIT_Msk (1ul << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */\r
-\r
-/* SCB Configuration Control Register Definitions */\r
-#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */\r
-#define SCB_CCR_STKALIGN_Msk (1ul << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */\r
-\r
-#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */\r
-#define SCB_CCR_BFHFNMIGN_Msk (1ul << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */\r
-\r
-#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */\r
-#define SCB_CCR_DIV_0_TRP_Msk (1ul << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */\r
-\r
-#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */\r
-#define SCB_CCR_UNALIGN_TRP_Msk (1ul << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */\r
-\r
-#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */\r
-#define SCB_CCR_USERSETMPEND_Msk (1ul << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */\r
-\r
-#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */\r
-#define SCB_CCR_NONBASETHRDENA_Msk (1ul << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */\r
-\r
-/* SCB System Handler Control and State Register Definitions */\r
-#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */\r
-#define SCB_SHCSR_USGFAULTENA_Msk (1ul << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */\r
-\r
-#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */\r
-#define SCB_SHCSR_BUSFAULTENA_Msk (1ul << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */\r
-\r
-#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */\r
-#define SCB_SHCSR_MEMFAULTENA_Msk (1ul << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */\r
-\r
-#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */\r
-#define SCB_SHCSR_SVCALLPENDED_Msk (1ul << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */\r
-\r
-#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */\r
-#define SCB_SHCSR_BUSFAULTPENDED_Msk (1ul << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */\r
-\r
-#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */\r
-#define SCB_SHCSR_MEMFAULTPENDED_Msk (1ul << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */\r
-\r
-#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */\r
-#define SCB_SHCSR_USGFAULTPENDED_Msk (1ul << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */\r
-\r
-#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */\r
-#define SCB_SHCSR_SYSTICKACT_Msk (1ul << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */\r
-\r
-#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */\r
-#define SCB_SHCSR_PENDSVACT_Msk (1ul << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */\r
-\r
-#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */\r
-#define SCB_SHCSR_MONITORACT_Msk (1ul << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */\r
-\r
-#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */\r
-#define SCB_SHCSR_SVCALLACT_Msk (1ul << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */\r
- \r
-#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */\r
-#define SCB_SHCSR_USGFAULTACT_Msk (1ul << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */\r
-\r
-#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */\r
-#define SCB_SHCSR_BUSFAULTACT_Msk (1ul << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */\r
-\r
-#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */\r
-#define SCB_SHCSR_MEMFAULTACT_Msk (1ul << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */\r
-\r
-/* SCB Configurable Fault Status Registers Definitions */\r
-#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */\r
-#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFul << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */\r
-\r
-#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */\r
-#define SCB_CFSR_BUSFAULTSR_Msk (0xFFul << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */\r
-\r
-#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */\r
-#define SCB_CFSR_MEMFAULTSR_Msk (0xFFul << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */\r
-\r
-/* SCB Hard Fault Status Registers Definitions */\r
-#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */\r
-#define SCB_HFSR_DEBUGEVT_Msk (1ul << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */\r
-\r
-#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */\r
-#define SCB_HFSR_FORCED_Msk (1ul << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */\r
-\r
-#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */\r
-#define SCB_HFSR_VECTTBL_Msk (1ul << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */\r
-\r
-/* SCB Debug Fault Status Register Definitions */\r
-#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */\r
-#define SCB_DFSR_EXTERNAL_Msk (1ul << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */\r
-\r
-#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */\r
-#define SCB_DFSR_VCATCH_Msk (1ul << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */\r
-\r
-#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */\r
-#define SCB_DFSR_DWTTRAP_Msk (1ul << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */\r
-\r
-#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */\r
-#define SCB_DFSR_BKPT_Msk (1ul << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */\r
-\r
-#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */\r
-#define SCB_DFSR_HALTED_Msk (1ul << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */\r
-/*@}*/ /* end of group CMSIS_CM3_SCB */\r
-\r
-\r
-/** @addtogroup CMSIS_CM3_SysTick CMSIS CM3 SysTick\r
- memory mapped structure for SysTick\r
- @{\r
- */\r
-typedef struct\r
-{\r
- __IO uint32_t CTRL; /*!< Offset: 0x00 SysTick Control and Status Register */\r
- __IO uint32_t LOAD; /*!< Offset: 0x04 SysTick Reload Value Register */\r
- __IO uint32_t VAL; /*!< Offset: 0x08 SysTick Current Value Register */\r
- __I uint32_t CALIB; /*!< Offset: 0x0C SysTick Calibration Register */\r
-} SysTick_Type;\r
-\r
-/* SysTick Control / Status Register Definitions */\r
-#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */\r
-#define SysTick_CTRL_COUNTFLAG_Msk (1ul << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */\r
-\r
-#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */\r
-#define SysTick_CTRL_CLKSOURCE_Msk (1ul << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */\r
-\r
-#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */\r
-#define SysTick_CTRL_TICKINT_Msk (1ul << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */\r
-\r
-#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */\r
-#define SysTick_CTRL_ENABLE_Msk (1ul << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */\r
-\r
-/* SysTick Reload Register Definitions */\r
-#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */\r
-#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFul << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */\r
-\r
-/* SysTick Current Register Definitions */\r
-#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */\r
-#define SysTick_VAL_CURRENT_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */\r
-\r
-/* SysTick Calibration Register Definitions */\r
-#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */\r
-#define SysTick_CALIB_NOREF_Msk (1ul << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */\r
-\r
-#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */\r
-#define SysTick_CALIB_SKEW_Msk (1ul << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */\r
-\r
-#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */\r
-#define SysTick_CALIB_TENMS_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */\r
-/*@}*/ /* end of group CMSIS_CM3_SysTick */\r
-\r
-\r
-/** @addtogroup CMSIS_CM3_ITM CMSIS CM3 ITM\r
- memory mapped structure for Instrumentation Trace Macrocell (ITM)\r
- @{\r
- */\r
-typedef struct\r
-{\r
- __O union \r
- {\r
- __O uint8_t u8; /*!< Offset: ITM Stimulus Port 8-bit */\r
- __O uint16_t u16; /*!< Offset: ITM Stimulus Port 16-bit */\r
- __O uint32_t u32; /*!< Offset: ITM Stimulus Port 32-bit */\r
- } PORT [32]; /*!< Offset: 0x00 ITM Stimulus Port Registers */\r
- uint32_t RESERVED0[864]; \r
- __IO uint32_t TER; /*!< Offset: ITM Trace Enable Register */\r
- uint32_t RESERVED1[15]; \r
- __IO uint32_t TPR; /*!< Offset: ITM Trace Privilege Register */\r
- uint32_t RESERVED2[15]; \r
- __IO uint32_t TCR; /*!< Offset: ITM Trace Control Register */\r
- uint32_t RESERVED3[29]; \r
- __IO uint32_t IWR; /*!< Offset: ITM Integration Write Register */\r
- __IO uint32_t IRR; /*!< Offset: ITM Integration Read Register */\r
- __IO uint32_t IMCR; /*!< Offset: ITM Integration Mode Control Register */\r
- uint32_t RESERVED4[43]; \r
- __IO uint32_t LAR; /*!< Offset: ITM Lock Access Register */\r
- __IO uint32_t LSR; /*!< Offset: ITM Lock Status Register */\r
- uint32_t RESERVED5[6]; \r
- __I uint32_t PID4; /*!< Offset: ITM Peripheral Identification Register #4 */\r
- __I uint32_t PID5; /*!< Offset: ITM Peripheral Identification Register #5 */\r
- __I uint32_t PID6; /*!< Offset: ITM Peripheral Identification Register #6 */\r
- __I uint32_t PID7; /*!< Offset: ITM Peripheral Identification Register #7 */\r
- __I uint32_t PID0; /*!< Offset: ITM Peripheral Identification Register #0 */\r
- __I uint32_t PID1; /*!< Offset: ITM Peripheral Identification Register #1 */\r
- __I uint32_t PID2; /*!< Offset: ITM Peripheral Identification Register #2 */\r
- __I uint32_t PID3; /*!< Offset: ITM Peripheral Identification Register #3 */\r
- __I uint32_t CID0; /*!< Offset: ITM Component Identification Register #0 */\r
- __I uint32_t CID1; /*!< Offset: ITM Component Identification Register #1 */\r
- __I uint32_t CID2; /*!< Offset: ITM Component Identification Register #2 */\r
- __I uint32_t CID3; /*!< Offset: ITM Component Identification Register #3 */\r
-} ITM_Type; \r
-\r
-/* ITM Trace Privilege Register Definitions */\r
-#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */\r
-#define ITM_TPR_PRIVMASK_Msk (0xFul << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */\r
-\r
-/* ITM Trace Control Register Definitions */\r
-#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */\r
-#define ITM_TCR_BUSY_Msk (1ul << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */\r
-\r
-#define ITM_TCR_ATBID_Pos 16 /*!< ITM TCR: ATBID Position */\r
-#define ITM_TCR_ATBID_Msk (0x7Ful << ITM_TCR_ATBID_Pos) /*!< ITM TCR: ATBID Mask */\r
-\r
-#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */\r
-#define ITM_TCR_TSPrescale_Msk (3ul << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */\r
-\r
-#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */\r
-#define ITM_TCR_SWOENA_Msk (1ul << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */\r
-\r
-#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */\r
-#define ITM_TCR_DWTENA_Msk (1ul << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */\r
-\r
-#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */\r
-#define ITM_TCR_SYNCENA_Msk (1ul << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */\r
-\r
-#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */\r
-#define ITM_TCR_TSENA_Msk (1ul << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */\r
-\r
-#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */\r
-#define ITM_TCR_ITMENA_Msk (1ul << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */\r
-\r
-/* ITM Integration Write Register Definitions */\r
-#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */\r
-#define ITM_IWR_ATVALIDM_Msk (1ul << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */\r
-\r
-/* ITM Integration Read Register Definitions */\r
-#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */\r
-#define ITM_IRR_ATREADYM_Msk (1ul << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */\r
-\r
-/* ITM Integration Mode Control Register Definitions */\r
-#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */\r
-#define ITM_IMCR_INTEGRATION_Msk (1ul << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */\r
-\r
-/* ITM Lock Status Register Definitions */\r
-#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */\r
-#define ITM_LSR_ByteAcc_Msk (1ul << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */\r
-\r
-#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */\r
-#define ITM_LSR_Access_Msk (1ul << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */\r
-\r
-#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */\r
-#define ITM_LSR_Present_Msk (1ul << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */\r
-/*@}*/ /* end of group CMSIS_CM3_ITM */\r
-\r
-\r
-/** @addtogroup CMSIS_CM3_InterruptType CMSIS CM3 Interrupt Type\r
- memory mapped structure for Interrupt Type\r
- @{\r
- */\r
-typedef struct\r
-{\r
- uint32_t RESERVED0;\r
- __I uint32_t ICTR; /*!< Offset: 0x04 Interrupt Control Type Register */\r
-#if ((defined __CM3_REV) && (__CM3_REV >= 0x200))\r
- __IO uint32_t ACTLR; /*!< Offset: 0x08 Auxiliary Control Register */\r
-#else\r
- uint32_t RESERVED1;\r
-#endif\r
-} InterruptType_Type;\r
-\r
-/* Interrupt Controller Type Register Definitions */\r
-#define InterruptType_ICTR_INTLINESNUM_Pos 0 /*!< InterruptType ICTR: INTLINESNUM Position */\r
-#define InterruptType_ICTR_INTLINESNUM_Msk (0x1Ful << InterruptType_ICTR_INTLINESNUM_Pos) /*!< InterruptType ICTR: INTLINESNUM Mask */\r
-\r
-/* Auxiliary Control Register Definitions */\r
-#define InterruptType_ACTLR_DISFOLD_Pos 2 /*!< InterruptType ACTLR: DISFOLD Position */\r
-#define InterruptType_ACTLR_DISFOLD_Msk (1ul << InterruptType_ACTLR_DISFOLD_Pos) /*!< InterruptType ACTLR: DISFOLD Mask */\r
-\r
-#define InterruptType_ACTLR_DISDEFWBUF_Pos 1 /*!< InterruptType ACTLR: DISDEFWBUF Position */\r
-#define InterruptType_ACTLR_DISDEFWBUF_Msk (1ul << InterruptType_ACTLR_DISDEFWBUF_Pos) /*!< InterruptType ACTLR: DISDEFWBUF Mask */\r
-\r
-#define InterruptType_ACTLR_DISMCYCINT_Pos 0 /*!< InterruptType ACTLR: DISMCYCINT Position */\r
-#define InterruptType_ACTLR_DISMCYCINT_Msk (1ul << InterruptType_ACTLR_DISMCYCINT_Pos) /*!< InterruptType ACTLR: DISMCYCINT Mask */\r
-/*@}*/ /* end of group CMSIS_CM3_InterruptType */\r
-\r
-\r
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1)\r
-/** @addtogroup CMSIS_CM3_MPU CMSIS CM3 MPU\r
- memory mapped structure for Memory Protection Unit (MPU)\r
- @{\r
- */\r
-typedef struct\r
-{\r
- __I uint32_t TYPE; /*!< Offset: 0x00 MPU Type Register */\r
- __IO uint32_t CTRL; /*!< Offset: 0x04 MPU Control Register */\r
- __IO uint32_t RNR; /*!< Offset: 0x08 MPU Region RNRber Register */\r
- __IO uint32_t RBAR; /*!< Offset: 0x0C MPU Region Base Address Register */\r
- __IO uint32_t RASR; /*!< Offset: 0x10 MPU Region Attribute and Size Register */\r
- __IO uint32_t RBAR_A1; /*!< Offset: 0x14 MPU Alias 1 Region Base Address Register */\r
- __IO uint32_t RASR_A1; /*!< Offset: 0x18 MPU Alias 1 Region Attribute and Size Register */\r
- __IO uint32_t RBAR_A2; /*!< Offset: 0x1C MPU Alias 2 Region Base Address Register */\r
- __IO uint32_t RASR_A2; /*!< Offset: 0x20 MPU Alias 2 Region Attribute and Size Register */\r
- __IO uint32_t RBAR_A3; /*!< Offset: 0x24 MPU Alias 3 Region Base Address Register */\r
- __IO uint32_t RASR_A3; /*!< Offset: 0x28 MPU Alias 3 Region Attribute and Size Register */\r
-} MPU_Type; \r
-\r
-/* MPU Type Register */\r
-#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */\r
-#define MPU_TYPE_IREGION_Msk (0xFFul << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */\r
-\r
-#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */\r
-#define MPU_TYPE_DREGION_Msk (0xFFul << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */\r
-\r
-#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */\r
-#define MPU_TYPE_SEPARATE_Msk (1ul << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */\r
-\r
-/* MPU Control Register */\r
-#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */\r
-#define MPU_CTRL_PRIVDEFENA_Msk (1ul << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */\r
-\r
-#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */\r
-#define MPU_CTRL_HFNMIENA_Msk (1ul << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */\r
-\r
-#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */\r
-#define MPU_CTRL_ENABLE_Msk (1ul << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */\r
-\r
-/* MPU Region Number Register */\r
-#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */\r
-#define MPU_RNR_REGION_Msk (0xFFul << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */\r
-\r
-/* MPU Region Base Address Register */\r
-#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */\r
-#define MPU_RBAR_ADDR_Msk (0x7FFFFFFul << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */\r
-\r
-#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */\r
-#define MPU_RBAR_VALID_Msk (1ul << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */\r
-\r
-#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */\r
-#define MPU_RBAR_REGION_Msk (0xFul << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */\r
-\r
-/* MPU Region Attribute and Size Register */\r
-#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: XN Position */\r
-#define MPU_RASR_XN_Msk (1ul << MPU_RASR_XN_Pos) /*!< MPU RASR: XN Mask */\r
-\r
-#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: AP Position */\r
-#define MPU_RASR_AP_Msk (7ul << MPU_RASR_AP_Pos) /*!< MPU RASR: AP Mask */\r
-\r
-#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: TEX Position */\r
-#define MPU_RASR_TEX_Msk (7ul << MPU_RASR_TEX_Pos) /*!< MPU RASR: TEX Mask */\r
-\r
-#define MPU_RASR_S_Pos 18 /*!< MPU RASR: Shareable bit Position */\r
-#define MPU_RASR_S_Msk (1ul << MPU_RASR_S_Pos) /*!< MPU RASR: Shareable bit Mask */\r
-\r
-#define MPU_RASR_C_Pos 17 /*!< MPU RASR: Cacheable bit Position */\r
-#define MPU_RASR_C_Msk (1ul << MPU_RASR_C_Pos) /*!< MPU RASR: Cacheable bit Mask */\r
-\r
-#define MPU_RASR_B_Pos 16 /*!< MPU RASR: Bufferable bit Position */\r
-#define MPU_RASR_B_Msk (1ul << MPU_RASR_B_Pos) /*!< MPU RASR: Bufferable bit Mask */\r
-\r
-#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */\r
-#define MPU_RASR_SRD_Msk (0xFFul << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */\r
-\r
-#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */\r
-#define MPU_RASR_SIZE_Msk (0x1Ful << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */\r
-\r
-#define MPU_RASR_ENA_Pos 0 /*!< MPU RASR: Region enable bit Position */\r
-#define MPU_RASR_ENA_Msk (0x1Ful << MPU_RASR_ENA_Pos) /*!< MPU RASR: Region enable bit Disable Mask */\r
-\r
-/*@}*/ /* end of group CMSIS_CM3_MPU */\r
-#endif\r
-\r
-\r
-/** @addtogroup CMSIS_CM3_CoreDebug CMSIS CM3 Core Debug\r
- memory mapped structure for Core Debug Register\r
- @{\r
- */\r
-typedef struct\r
-{\r
- __IO uint32_t DHCSR; /*!< Offset: 0x00 Debug Halting Control and Status Register */\r
- __O uint32_t DCRSR; /*!< Offset: 0x04 Debug Core Register Selector Register */\r
- __IO uint32_t DCRDR; /*!< Offset: 0x08 Debug Core Register Data Register */\r
- __IO uint32_t DEMCR; /*!< Offset: 0x0C Debug Exception and Monitor Control Register */\r
-} CoreDebug_Type;\r
-\r
-/* Debug Halting Control and Status Register */\r
-#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */\r
-#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFul << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */\r
-\r
-#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */\r
-#define CoreDebug_DHCSR_S_RESET_ST_Msk (1ul << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */\r
-\r
-#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */\r
-#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1ul << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */\r
-\r
-#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */\r
-#define CoreDebug_DHCSR_S_LOCKUP_Msk (1ul << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */\r
-\r
-#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */\r
-#define CoreDebug_DHCSR_S_SLEEP_Msk (1ul << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */\r
-\r
-#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */\r
-#define CoreDebug_DHCSR_S_HALT_Msk (1ul << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */\r
-\r
-#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */\r
-#define CoreDebug_DHCSR_S_REGRDY_Msk (1ul << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */\r
-\r
-#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */\r
-#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1ul << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */\r
-\r
-#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */\r
-#define CoreDebug_DHCSR_C_MASKINTS_Msk (1ul << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */\r
-\r
-#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */\r
-#define CoreDebug_DHCSR_C_STEP_Msk (1ul << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */\r
-\r
-#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */\r
-#define CoreDebug_DHCSR_C_HALT_Msk (1ul << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */\r
-\r
-#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */\r
-#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1ul << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */\r
-\r
-/* Debug Core Register Selector Register */\r
-#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */\r
-#define CoreDebug_DCRSR_REGWnR_Msk (1ul << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */\r
-\r
-#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */\r
-#define CoreDebug_DCRSR_REGSEL_Msk (0x1Ful << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */\r
-\r
-/* Debug Exception and Monitor Control Register */\r
-#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */\r
-#define CoreDebug_DEMCR_TRCENA_Msk (1ul << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */\r
-\r
-#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */\r
-#define CoreDebug_DEMCR_MON_REQ_Msk (1ul << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */\r
-\r
-#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */\r
-#define CoreDebug_DEMCR_MON_STEP_Msk (1ul << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */\r
-\r
-#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */\r
-#define CoreDebug_DEMCR_MON_PEND_Msk (1ul << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */\r
-\r
-#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */\r
-#define CoreDebug_DEMCR_MON_EN_Msk (1ul << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */\r
-#define CoreDebug_DEMCR_VC_HARDERR_Msk (1ul << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */\r
-#define CoreDebug_DEMCR_VC_INTERR_Msk (1ul << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */\r
-#define CoreDebug_DEMCR_VC_BUSERR_Msk (1ul << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */\r
-#define CoreDebug_DEMCR_VC_STATERR_Msk (1ul << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */\r
-#define CoreDebug_DEMCR_VC_CHKERR_Msk (1ul << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */\r
-#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1ul << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */\r
-#define CoreDebug_DEMCR_VC_MMERR_Msk (1ul << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */\r
-#define CoreDebug_DEMCR_VC_CORERESET_Msk (1ul << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */\r
-/*@}*/ /* end of group CMSIS_CM3_CoreDebug */\r
-\r
-\r
-/* Memory mapping of Cortex-M3 Hardware */\r
-#define SCS_BASE (0xE000E000) /*!< System Control Space Base Address */\r
-#define ITM_BASE (0xE0000000) /*!< ITM Base Address */\r
-#define CoreDebug_BASE (0xE000EDF0) /*!< Core Debug Base Address */\r
-#define SysTick_BASE (SCS_BASE + 0x0010) /*!< SysTick Base Address */\r
-#define NVIC_BASE (SCS_BASE + 0x0100) /*!< NVIC Base Address */\r
-#define SCB_BASE (SCS_BASE + 0x0D00) /*!< System Control Block Base Address */\r
-\r
-#define InterruptType ((InterruptType_Type *) SCS_BASE) /*!< Interrupt Type Register */\r
-#define SCB ((SCB_Type *) SCB_BASE) /*!< SCB configuration struct */\r
-#define SysTick ((SysTick_Type *) SysTick_BASE) /*!< SysTick configuration struct */\r
-#define NVIC ((NVIC_Type *) NVIC_BASE) /*!< NVIC configuration struct */\r
-#define ITM ((ITM_Type *) ITM_BASE) /*!< ITM configuration struct */\r
-#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */\r
-\r
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1)\r
- #define MPU_BASE (SCS_BASE + 0x0D90) /*!< Memory Protection Unit */\r
- #define MPU ((MPU_Type*) MPU_BASE) /*!< Memory Protection Unit */\r
-#endif\r
-\r
-/*@}*/ /* end of group CMSIS_CM3_core_register */\r
-\r
-\r
-/*******************************************************************************\r
- * Hardware Abstraction Layer\r
- ******************************************************************************/\r
-\r
-#if defined ( __CC_ARM )\r
- #define __ASM __asm /*!< asm keyword for ARM Compiler */\r
- #define __INLINE __inline /*!< inline keyword for ARM Compiler */\r
-\r
-#elif defined ( __ICCARM__ )\r
- #define __ASM __asm /*!< asm keyword for IAR Compiler */\r
- #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */\r
-\r
-#elif defined ( __GNUC__ )\r
- #define __ASM __asm /*!< asm keyword for GNU Compiler */\r
- #define __INLINE inline /*!< inline keyword for GNU Compiler */\r
-\r
-#elif defined ( __TASKING__ )\r
- #define __ASM __asm /*!< asm keyword for TASKING Compiler */\r
- #define __INLINE inline /*!< inline keyword for TASKING Compiler */\r
-\r
-#endif\r
-\r
-\r
-/* ################### Compiler specific Intrinsics ########################### */\r
-\r
-#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/\r
-/* ARM armcc specific functions */\r
-\r
-#define __enable_fault_irq __enable_fiq\r
-#define __disable_fault_irq __disable_fiq\r
-\r
-#define __NOP __nop\r
-#define __WFI __wfi\r
-#define __WFE __wfe\r
-#define __SEV __sev\r
-#define __ISB() __isb(0)\r
-#define __DSB() __dsb(0)\r
-#define __DMB() __dmb(0)\r
-#define __REV __rev\r
-#define __RBIT __rbit\r
-#define __LDREXB(ptr) ((unsigned char ) __ldrex(ptr))\r
-#define __LDREXH(ptr) ((unsigned short) __ldrex(ptr))\r
-#define __LDREXW(ptr) ((unsigned int ) __ldrex(ptr))\r
-#define __STREXB(value, ptr) __strex(value, ptr)\r
-#define __STREXH(value, ptr) __strex(value, ptr)\r
-#define __STREXW(value, ptr) __strex(value, ptr)\r
-\r
-\r
-/* intrinsic unsigned long long __ldrexd(volatile void *ptr) */\r
-/* intrinsic int __strexd(unsigned long long val, volatile void *ptr) */\r
-/* intrinsic void __enable_irq(); */\r
-/* intrinsic void __disable_irq(); */\r
-\r
-\r
-/**\r
- * @brief Return the Process Stack Pointer\r
- *\r
- * @return ProcessStackPointer\r
- *\r
- * Return the actual process stack pointer\r
- */\r
-extern uint32_t __get_PSP(void);\r
-\r
-/**\r
- * @brief Set the Process Stack Pointer\r
- *\r
- * @param topOfProcStack Process Stack Pointer\r
- *\r
- * Assign the value ProcessStackPointer to the MSP \r
- * (process stack pointer) Cortex processor register\r
- */\r
-extern void __set_PSP(uint32_t topOfProcStack);\r
-\r
-/**\r
- * @brief Return the Main Stack Pointer\r
- *\r
- * @return Main Stack Pointer\r
- *\r
- * Return the current value of the MSP (main stack pointer)\r
- * Cortex processor register\r
- */\r
-extern uint32_t __get_MSP(void);\r
-\r
-/**\r
- * @brief Set the Main Stack Pointer\r
- *\r
- * @param topOfMainStack Main Stack Pointer\r
- *\r
- * Assign the value mainStackPointer to the MSP \r
- * (main stack pointer) Cortex processor register\r
- */\r
-extern void __set_MSP(uint32_t topOfMainStack);\r
-\r
-/**\r
- * @brief Reverse byte order in unsigned short value\r
- *\r
- * @param value value to reverse\r
- * @return reversed value\r
- *\r
- * Reverse byte order in unsigned short value\r
- */\r
-extern uint32_t __REV16(uint16_t value);\r
-\r
-/**\r
- * @brief Reverse byte order in signed short value with sign extension to integer\r
- *\r
- * @param value value to reverse\r
- * @return reversed value\r
- *\r
- * Reverse byte order in signed short value with sign extension to integer\r
- */\r
-extern int32_t __REVSH(int16_t value);\r
-\r
-\r
-#if (__ARMCC_VERSION < 400000)\r
-\r
-/**\r
- * @brief Remove the exclusive lock created by ldrex\r
- *\r
- * Removes the exclusive lock which is created by ldrex.\r
- */\r
-extern void __CLREX(void);\r
-\r
-/**\r
- * @brief Return the Base Priority value\r
- *\r
- * @return BasePriority\r
- *\r
- * Return the content of the base priority register\r
- */\r
-extern uint32_t __get_BASEPRI(void);\r
-\r
-/**\r
- * @brief Set the Base Priority value\r
- *\r
- * @param basePri BasePriority\r
- *\r
- * Set the base priority register\r
- */\r
-extern void __set_BASEPRI(uint32_t basePri);\r
-\r
-/**\r
- * @brief Return the Priority Mask value\r
- *\r
- * @return PriMask\r
- *\r
- * Return state of the priority mask bit from the priority mask register\r
- */\r
-extern uint32_t __get_PRIMASK(void);\r
-\r
-/**\r
- * @brief Set the Priority Mask value\r
- *\r
- * @param priMask PriMask\r
- *\r
- * Set the priority mask bit in the priority mask register\r
- */\r
-extern void __set_PRIMASK(uint32_t priMask);\r
-\r
-/**\r
- * @brief Return the Fault Mask value\r
- *\r
- * @return FaultMask\r
- *\r
- * Return the content of the fault mask register\r
- */\r
-extern uint32_t __get_FAULTMASK(void);\r
-\r
-/**\r
- * @brief Set the Fault Mask value\r
- *\r
- * @param faultMask faultMask value\r
- *\r
- * Set the fault mask register\r
- */\r
-extern void __set_FAULTMASK(uint32_t faultMask);\r
-\r
-/**\r
- * @brief Return the Control Register value\r
- * \r
- * @return Control value\r
- *\r
- * Return the content of the control register\r
- */\r
-extern uint32_t __get_CONTROL(void);\r
-\r
-/**\r
- * @brief Set the Control Register value\r
- *\r
- * @param control Control value\r
- *\r
- * Set the control register\r
- */\r
-extern void __set_CONTROL(uint32_t control);\r
-\r
-#else /* (__ARMCC_VERSION >= 400000) */\r
-\r
-/**\r
- * @brief Remove the exclusive lock created by ldrex\r
- *\r
- * Removes the exclusive lock which is created by ldrex.\r
- */\r
-#define __CLREX __clrex\r
-\r
-/**\r
- * @brief Return the Base Priority value\r
- *\r
- * @return BasePriority\r
- *\r
- * Return the content of the base priority register\r
- */\r
-static __INLINE uint32_t __get_BASEPRI(void)\r
-{\r
- register uint32_t __regBasePri __ASM("basepri");\r
- return(__regBasePri);\r
-}\r
-\r
-/**\r
- * @brief Set the Base Priority value\r
- *\r
- * @param basePri BasePriority\r
- *\r
- * Set the base priority register\r
- */\r
-static __INLINE void __set_BASEPRI(uint32_t basePri)\r
-{\r
- register uint32_t __regBasePri __ASM("basepri");\r
- __regBasePri = (basePri & 0xff);\r
-}\r
-\r
-/**\r
- * @brief Return the Priority Mask value\r
- *\r
- * @return PriMask\r
- *\r
- * Return state of the priority mask bit from the priority mask register\r
- */\r
-static __INLINE uint32_t __get_PRIMASK(void)\r
-{\r
- register uint32_t __regPriMask __ASM("primask");\r
- return(__regPriMask);\r
-}\r
-\r
-/**\r
- * @brief Set the Priority Mask value\r
- *\r
- * @param priMask PriMask\r
- *\r
- * Set the priority mask bit in the priority mask register\r
- */\r
-static __INLINE void __set_PRIMASK(uint32_t priMask)\r
-{\r
- register uint32_t __regPriMask __ASM("primask");\r
- __regPriMask = (priMask);\r
-}\r
-\r
-/**\r
- * @brief Return the Fault Mask value\r
- *\r
- * @return FaultMask\r
- *\r
- * Return the content of the fault mask register\r
- */\r
-static __INLINE uint32_t __get_FAULTMASK(void)\r
-{\r
- register uint32_t __regFaultMask __ASM("faultmask");\r
- return(__regFaultMask);\r
-}\r
-\r
-/**\r
- * @brief Set the Fault Mask value\r
- *\r
- * @param faultMask faultMask value\r
- *\r
- * Set the fault mask register\r
- */\r
-static __INLINE void __set_FAULTMASK(uint32_t faultMask)\r
-{\r
- register uint32_t __regFaultMask __ASM("faultmask");\r
- __regFaultMask = (faultMask & 1);\r
-}\r
-\r
-/**\r
- * @brief Return the Control Register value\r
- * \r
- * @return Control value\r
- *\r
- * Return the content of the control register\r
- */\r
-static __INLINE uint32_t __get_CONTROL(void)\r
-{\r
- register uint32_t __regControl __ASM("control");\r
- return(__regControl);\r
-}\r
-\r
-/**\r
- * @brief Set the Control Register value\r
- *\r
- * @param control Control value\r
- *\r
- * Set the control register\r
- */\r
-static __INLINE void __set_CONTROL(uint32_t control)\r
-{\r
- register uint32_t __regControl __ASM("control");\r
- __regControl = control;\r
-}\r
-\r
-#endif /* __ARMCC_VERSION */ \r
-\r
-\r
-\r
-#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/\r
-/* IAR iccarm specific functions */\r
-\r
-#define __enable_irq __enable_interrupt /*!< global Interrupt enable */\r
-#define __disable_irq __disable_interrupt /*!< global Interrupt disable */\r
-\r
-static __INLINE void __enable_fault_irq() { __ASM ("cpsie f"); }\r
-static __INLINE void __disable_fault_irq() { __ASM ("cpsid f"); }\r
-\r
-#define __NOP __no_operation /*!< no operation intrinsic in IAR Compiler */ \r
-static __INLINE void __WFI() { __ASM ("wfi"); }\r
-static __INLINE void __WFE() { __ASM ("wfe"); }\r
-static __INLINE void __SEV() { __ASM ("sev"); }\r
-static __INLINE void __CLREX() { __ASM ("clrex"); }\r
-\r
-/* intrinsic void __ISB(void) */\r
-/* intrinsic void __DSB(void) */\r
-/* intrinsic void __DMB(void) */\r
-/* intrinsic void __set_PRIMASK(); */\r
-/* intrinsic void __get_PRIMASK(); */\r
-/* intrinsic void __set_FAULTMASK(); */\r
-/* intrinsic void __get_FAULTMASK(); */\r
-/* intrinsic uint32_t __REV(uint32_t value); */\r
-/* intrinsic uint32_t __REVSH(uint32_t value); */\r
-/* intrinsic unsigned long __STREX(unsigned long, unsigned long); */\r
-/* intrinsic unsigned long __LDREX(unsigned long *); */\r
-\r
-\r
-/**\r
- * @brief Return the Process Stack Pointer\r
- *\r
- * @return ProcessStackPointer\r
- *\r
- * Return the actual process stack pointer\r
- */\r
-extern uint32_t __get_PSP(void);\r
-\r
-/**\r
- * @brief Set the Process Stack Pointer\r
- *\r
- * @param topOfProcStack Process Stack Pointer\r
- *\r
- * Assign the value ProcessStackPointer to the MSP \r
- * (process stack pointer) Cortex processor register\r
- */\r
-extern void __set_PSP(uint32_t topOfProcStack);\r
-\r
-/**\r
- * @brief Return the Main Stack Pointer\r
- *\r
- * @return Main Stack Pointer\r
- *\r
- * Return the current value of the MSP (main stack pointer)\r
- * Cortex processor register\r
- */\r
-extern uint32_t __get_MSP(void);\r
-\r
-/**\r
- * @brief Set the Main Stack Pointer\r
- *\r
- * @param topOfMainStack Main Stack Pointer\r
- *\r
- * Assign the value mainStackPointer to the MSP \r
- * (main stack pointer) Cortex processor register\r
- */\r
-extern void __set_MSP(uint32_t topOfMainStack);\r
-\r
-/**\r
- * @brief Reverse byte order in unsigned short value\r
- *\r
- * @param value value to reverse\r
- * @return reversed value\r
- *\r
- * Reverse byte order in unsigned short value\r
- */\r
-extern uint32_t __REV16(uint16_t value);\r
-\r
-/**\r
- * @brief Reverse bit order of value\r
- *\r
- * @param value value to reverse\r
- * @return reversed value\r
- *\r
- * Reverse bit order of value\r
- */\r
-extern uint32_t __RBIT(uint32_t value);\r
-\r
-/**\r
- * @brief LDR Exclusive (8 bit)\r
- *\r
- * @param *addr address pointer\r
- * @return value of (*address)\r
- *\r
- * Exclusive LDR command for 8 bit values)\r
- */\r
-extern uint8_t __LDREXB(uint8_t *addr);\r
-\r
-/**\r
- * @brief LDR Exclusive (16 bit)\r
- *\r
- * @param *addr address pointer\r
- * @return value of (*address)\r
- *\r
- * Exclusive LDR command for 16 bit values\r
- */\r
-extern uint16_t __LDREXH(uint16_t *addr);\r
-\r
-/**\r
- * @brief LDR Exclusive (32 bit)\r
- *\r
- * @param *addr address pointer\r
- * @return value of (*address)\r
- *\r
- * Exclusive LDR command for 32 bit values\r
- */\r
-extern uint32_t __LDREXW(uint32_t *addr);\r
-\r
-/**\r
- * @brief STR Exclusive (8 bit)\r
- *\r
- * @param value value to store\r
- * @param *addr address pointer\r
- * @return successful / failed\r
- *\r
- * Exclusive STR command for 8 bit values\r
- */\r
-extern uint32_t __STREXB(uint8_t value, uint8_t *addr);\r
-\r
-/**\r
- * @brief STR Exclusive (16 bit)\r
- *\r
- * @param value value to store\r
- * @param *addr address pointer\r
- * @return successful / failed\r
- *\r
- * Exclusive STR command for 16 bit values\r
- */\r
-extern uint32_t __STREXH(uint16_t value, uint16_t *addr);\r
-\r
-/**\r
- * @brief STR Exclusive (32 bit)\r
- *\r
- * @param value value to store\r
- * @param *addr address pointer\r
- * @return successful / failed\r
- *\r
- * Exclusive STR command for 32 bit values\r
- */\r
-extern uint32_t __STREXW(uint32_t value, uint32_t *addr);\r
-\r
-\r
-\r
-#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/\r
-/* GNU gcc specific functions */\r
-\r
-static __INLINE void __enable_irq() { __ASM volatile ("cpsie i"); }\r
-static __INLINE void __disable_irq() { __ASM volatile ("cpsid i"); }\r
-\r
-static __INLINE void __enable_fault_irq() { __ASM volatile ("cpsie f"); }\r
-static __INLINE void __disable_fault_irq() { __ASM volatile ("cpsid f"); }\r
-\r
-static __INLINE void __NOP() { __ASM volatile ("nop"); }\r
-static __INLINE void __WFI() { __ASM volatile ("wfi"); }\r
-static __INLINE void __WFE() { __ASM volatile ("wfe"); }\r
-static __INLINE void __SEV() { __ASM volatile ("sev"); }\r
-static __INLINE void __ISB() { __ASM volatile ("isb"); }\r
-static __INLINE void __DSB() { __ASM volatile ("dsb"); }\r
-static __INLINE void __DMB() { __ASM volatile ("dmb"); }\r
-static __INLINE void __CLREX() { __ASM volatile ("clrex"); }\r
-\r
-\r
-/**\r
- * @brief Return the Process Stack Pointer\r
- *\r
- * @return ProcessStackPointer\r
- *\r
- * Return the actual process stack pointer\r
- */\r
-extern uint32_t __get_PSP(void);\r
-\r
-/**\r
- * @brief Set the Process Stack Pointer\r
- *\r
- * @param topOfProcStack Process Stack Pointer\r
- *\r
- * Assign the value ProcessStackPointer to the MSP \r
- * (process stack pointer) Cortex processor register\r
- */\r
-extern void __set_PSP(uint32_t topOfProcStack);\r
-\r
-/**\r
- * @brief Return the Main Stack Pointer\r
- *\r
- * @return Main Stack Pointer\r
- *\r
- * Return the current value of the MSP (main stack pointer)\r
- * Cortex processor register\r
- */\r
-extern uint32_t __get_MSP(void);\r
-\r
-/**\r
- * @brief Set the Main Stack Pointer\r
- *\r
- * @param topOfMainStack Main Stack Pointer\r
- *\r
- * Assign the value mainStackPointer to the MSP \r
- * (main stack pointer) Cortex processor register\r
- */\r
-extern void __set_MSP(uint32_t topOfMainStack);\r
-\r
-/**\r
- * @brief Return the Base Priority value\r
- *\r
- * @return BasePriority\r
- *\r
- * Return the content of the base priority register\r
- */\r
-extern uint32_t __get_BASEPRI(void);\r
-\r
-/**\r
- * @brief Set the Base Priority value\r
- *\r
- * @param basePri BasePriority\r
- *\r
- * Set the base priority register\r
- */\r
-extern void __set_BASEPRI(uint32_t basePri);\r
-\r
-/**\r
- * @brief Return the Priority Mask value\r
- *\r
- * @return PriMask\r
- *\r
- * Return state of the priority mask bit from the priority mask register\r
- */\r
-extern uint32_t __get_PRIMASK(void);\r
-\r
-/**\r
- * @brief Set the Priority Mask value\r
- *\r
- * @param priMask PriMask\r
- *\r
- * Set the priority mask bit in the priority mask register\r
- */\r
-extern void __set_PRIMASK(uint32_t priMask);\r
-\r
-/**\r
- * @brief Return the Fault Mask value\r
- *\r
- * @return FaultMask\r
- *\r
- * Return the content of the fault mask register\r
- */\r
-extern uint32_t __get_FAULTMASK(void);\r
-\r
-/**\r
- * @brief Set the Fault Mask value\r
- *\r
- * @param faultMask faultMask value\r
- *\r
- * Set the fault mask register\r
- */\r
-extern void __set_FAULTMASK(uint32_t faultMask);\r
-\r
-/**\r
- * @brief Return the Control Register value\r
-* \r
-* @return Control value\r
- *\r
- * Return the content of the control register\r
- */\r
-extern uint32_t __get_CONTROL(void);\r
-\r
-/**\r
- * @brief Set the Control Register value\r
- *\r
- * @param control Control value\r
- *\r
- * Set the control register\r
- */\r
-extern void __set_CONTROL(uint32_t control);\r
-\r
-/**\r
- * @brief Reverse byte order in integer value\r
- *\r
- * @param value value to reverse\r
- * @return reversed value\r
- *\r
- * Reverse byte order in integer value\r
- */\r
-extern uint32_t __REV(uint32_t value);\r
-\r
-/**\r
- * @brief Reverse byte order in unsigned short value\r
- *\r
- * @param value value to reverse\r
- * @return reversed value\r
- *\r
- * Reverse byte order in unsigned short value\r
- */\r
-extern uint32_t __REV16(uint16_t value);\r
-\r
-/**\r
- * @brief Reverse byte order in signed short value with sign extension to integer\r
- *\r
- * @param value value to reverse\r
- * @return reversed value\r
- *\r
- * Reverse byte order in signed short value with sign extension to integer\r
- */\r
-extern int32_t __REVSH(int16_t value);\r
-\r
-/**\r
- * @brief Reverse bit order of value\r
- *\r
- * @param value value to reverse\r
- * @return reversed value\r
- *\r
- * Reverse bit order of value\r
- */\r
-extern uint32_t __RBIT(uint32_t value);\r
-\r
-/**\r
- * @brief LDR Exclusive (8 bit)\r
- *\r
- * @param *addr address pointer\r
- * @return value of (*address)\r
- *\r
- * Exclusive LDR command for 8 bit value\r
- */\r
-extern uint8_t __LDREXB(uint8_t *addr);\r
-\r
-/**\r
- * @brief LDR Exclusive (16 bit)\r
- *\r
- * @param *addr address pointer\r
- * @return value of (*address)\r
- *\r
- * Exclusive LDR command for 16 bit values\r
- */\r
-extern uint16_t __LDREXH(uint16_t *addr);\r
-\r
-/**\r
- * @brief LDR Exclusive (32 bit)\r
- *\r
- * @param *addr address pointer\r
- * @return value of (*address)\r
- *\r
- * Exclusive LDR command for 32 bit values\r
- */\r
-extern uint32_t __LDREXW(uint32_t *addr);\r
-\r
-/**\r
- * @brief STR Exclusive (8 bit)\r
- *\r
- * @param value value to store\r
- * @param *addr address pointer\r
- * @return successful / failed\r
- *\r
- * Exclusive STR command for 8 bit values\r
- */\r
-extern uint32_t __STREXB(uint8_t value, uint8_t *addr);\r
-\r
-/**\r
- * @brief STR Exclusive (16 bit)\r
- *\r
- * @param value value to store\r
- * @param *addr address pointer\r
- * @return successful / failed\r
- *\r
- * Exclusive STR command for 16 bit values\r
- */\r
-extern uint32_t __STREXH(uint16_t value, uint16_t *addr);\r
-\r
-/**\r
- * @brief STR Exclusive (32 bit)\r
- *\r
- * @param value value to store\r
- * @param *addr address pointer\r
- * @return successful / failed\r
- *\r
- * Exclusive STR command for 32 bit values\r
- */\r
-extern uint32_t __STREXW(uint32_t value, uint32_t *addr);\r
-\r
-\r
-#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/\r
-/* TASKING carm specific functions */\r
-\r
-/*\r
- * The CMSIS functions have been implemented as intrinsics in the compiler.\r
- * Please use "carm -?i" to get an up to date list of all instrinsics,\r
- * Including the CMSIS ones.\r
- */\r
-\r
-#endif\r
-\r
-\r
-/** @addtogroup CMSIS_CM3_Core_FunctionInterface CMSIS CM3 Core Function Interface\r
- Core Function Interface containing:\r
- - Core NVIC Functions\r
- - Core SysTick Functions\r
- - Core Reset Functions\r
-*/\r
-/*@{*/\r
-\r
-/* ########################## NVIC functions #################################### */\r
-\r
-/**\r
- * @brief Set the Priority Grouping in NVIC Interrupt Controller\r
- *\r
- * @param PriorityGroup is priority grouping field\r
- *\r
- * Set the priority grouping field using the required unlock sequence.\r
- * The parameter priority_grouping is assigned to the field \r
- * SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used.\r
- * In case of a conflict between priority grouping and available\r
- * priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\r
- */\r
-static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)\r
-{\r
- uint32_t reg_value;\r
- uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */\r
- \r
- reg_value = SCB->AIRCR; /* read old register configuration */\r
- reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */\r
- reg_value = (reg_value |\r
- (0x5FA << SCB_AIRCR_VECTKEY_Pos) | \r
- (PriorityGroupTmp << 8)); /* Insert write key and priorty group */\r
- SCB->AIRCR = reg_value;\r
-}\r
-\r
-/**\r
- * @brief Get the Priority Grouping from NVIC Interrupt Controller\r
- *\r
- * @return priority grouping field \r
- *\r
- * Get the priority grouping from NVIC Interrupt Controller.\r
- * priority grouping is SCB->AIRCR [10:8] PRIGROUP field.\r
- */\r
-static __INLINE uint32_t NVIC_GetPriorityGrouping(void)\r
-{\r
- return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */\r
-}\r
-\r
-/**\r
- * @brief Enable Interrupt in NVIC Interrupt Controller\r
- *\r
- * @param IRQn The positive number of the external interrupt to enable\r
- *\r
- * Enable a device specific interupt in the NVIC interrupt controller.\r
- * The interrupt number cannot be a negative value.\r
- */\r
-static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)\r
-{\r
- NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */\r
-}\r
-\r
-/**\r
- * @brief Disable the interrupt line for external interrupt specified\r
- * \r
- * @param IRQn The positive number of the external interrupt to disable\r
- * \r
- * Disable a device specific interupt in the NVIC interrupt controller.\r
- * The interrupt number cannot be a negative value.\r
- */\r
-static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)\r
-{\r
- NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */\r
-}\r
-\r
-/**\r
- * @brief Read the interrupt pending bit for a device specific interrupt source\r
- * \r
- * @param IRQn The number of the device specifc interrupt\r
- * @return 1 = interrupt pending, 0 = interrupt not pending\r
- *\r
- * Read the pending register in NVIC and return 1 if its status is pending, \r
- * otherwise it returns 0\r
- */\r
-static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
-{\r
- return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */\r
-}\r
-\r
-/**\r
- * @brief Set the pending bit for an external interrupt\r
- * \r
- * @param IRQn The number of the interrupt for set pending\r
- *\r
- * Set the pending bit for the specified interrupt.\r
- * The interrupt number cannot be a negative value.\r
- */\r
-static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
-{\r
- NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */\r
-}\r
-\r
-/**\r
- * @brief Clear the pending bit for an external interrupt\r
- *\r
- * @param IRQn The number of the interrupt for clear pending\r
- *\r
- * Clear the pending bit for the specified interrupt. \r
- * The interrupt number cannot be a negative value.\r
- */\r
-static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
-{\r
- NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */\r
-}\r
-\r
-/**\r
- * @brief Read the active bit for an external interrupt\r
- *\r
- * @param IRQn The number of the interrupt for read active bit\r
- * @return 1 = interrupt active, 0 = interrupt not active\r
- *\r
- * Read the active register in NVIC and returns 1 if its status is active, \r
- * otherwise it returns 0.\r
- */\r
-static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)\r
-{\r
- return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */\r
-}\r
-\r
-/**\r
- * @brief Set the priority for an interrupt\r
- *\r
- * @param IRQn The number of the interrupt for set priority\r
- * @param priority The priority to set\r
- *\r
- * Set the priority for the specified interrupt. The interrupt \r
- * number can be positive to specify an external (device specific) \r
- * interrupt, or negative to specify an internal (core) interrupt.\r
- *\r
- * Note: The priority cannot be set for every core interrupt.\r
- */\r
-static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r
-{\r
- if(IRQn < 0) {\r
- SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M3 System Interrupts */\r
- else {\r
- NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */\r
-}\r
-\r
-/**\r
- * @brief Read the priority for an interrupt\r
- *\r
- * @param IRQn The number of the interrupt for get priority\r
- * @return The priority for the interrupt\r
- *\r
- * Read the priority for the specified interrupt. The interrupt \r
- * number can be positive to specify an external (device specific) \r
- * interrupt, or negative to specify an internal (core) interrupt.\r
- *\r
- * The returned priority value is automatically aligned to the implemented\r
- * priority bits of the microcontroller.\r
- *\r
- * Note: The priority cannot be set for every core interrupt.\r
- */\r
-static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)\r
-{\r
-\r
- if(IRQn < 0) {\r
- return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M3 system interrupts */\r
- else {\r
- return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */\r
-}\r
-\r
-\r
-/**\r
- * @brief Encode the priority for an interrupt\r
- *\r
- * @param PriorityGroup The used priority group\r
- * @param PreemptPriority The preemptive priority value (starting from 0)\r
- * @param SubPriority The sub priority value (starting from 0)\r
- * @return The encoded priority for the interrupt\r
- *\r
- * Encode the priority for an interrupt with the given priority group,\r
- * preemptive priority value and sub priority value.\r
- * In case of a conflict between priority grouping and available\r
- * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.\r
- *\r
- * The returned priority value can be used for NVIC_SetPriority(...) function\r
- */\r
-static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\r
-{\r
- uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */\r
- uint32_t PreemptPriorityBits;\r
- uint32_t SubPriorityBits;\r
-\r
- PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;\r
- SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;\r
- \r
- return (\r
- ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |\r
- ((SubPriority & ((1 << (SubPriorityBits )) - 1)))\r
- );\r
-}\r
-\r
-\r
-/**\r
- * @brief Decode the priority of an interrupt\r
- *\r
- * @param Priority The priority for the interrupt\r
- * @param PriorityGroup The used priority group\r
- * @param pPreemptPriority The preemptive priority value (starting from 0)\r
- * @param pSubPriority The sub priority value (starting from 0)\r
- *\r
- * Decode an interrupt priority value with the given priority group to \r
- * preemptive priority value and sub priority value.\r
- * In case of a conflict between priority grouping and available\r
- * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.\r
- *\r
- * The priority value can be retrieved with NVIC_GetPriority(...) function\r
- */\r
-static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)\r
-{\r
- uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */\r
- uint32_t PreemptPriorityBits;\r
- uint32_t SubPriorityBits;\r
-\r
- PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;\r
- SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;\r
- \r
- *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);\r
- *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);\r
-}\r
-\r
-\r
-\r
-/* ################################## SysTick function ############################################ */\r
-\r
-#if (!defined (__Vendor_SysTickConfig)) || (__Vendor_SysTickConfig == 0)\r
-\r
-/**\r
- * @brief Initialize and start the SysTick counter and its interrupt.\r
- *\r
- * @param ticks number of ticks between two interrupts\r
- * @return 1 = failed, 0 = successful\r
- *\r
- * Initialise the system tick timer and its interrupt and start the\r
- * system tick timer / counter in free running mode to generate \r
- * periodical interrupts.\r
- */\r
-static __INLINE uint32_t SysTick_Config(uint32_t ticks)\r
-{ \r
- if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */\r
- \r
- SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */\r
- NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */\r
- SysTick->VAL = 0; /* Load the SysTick Counter Value */\r
- SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | \r
- SysTick_CTRL_TICKINT_Msk | \r
- SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
- return (0); /* Function successful */\r
-}\r
-\r
-#endif\r
-\r
-\r
-\r
-\r
-/* ################################## Reset function ############################################ */\r
-\r
-/**\r
- * @brief Initiate a system reset request.\r
- *\r
- * Initiate a system reset request to reset the MCU\r
- */\r
-static __INLINE void NVIC_SystemReset(void)\r
-{\r
- SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | \r
- (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | \r
- SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */\r
- __DSB(); /* Ensure completion of memory access */ \r
- while(1); /* wait until reset */\r
-}\r
-\r
-/*@}*/ /* end of group CMSIS_CM3_Core_FunctionInterface */\r
-\r
-\r
-\r
-/* ##################################### Debug In/Output function ########################################### */\r
-\r
-/** @addtogroup CMSIS_CM3_CoreDebugInterface CMSIS CM3 Core Debug Interface\r
- Core Debug Interface containing:\r
- - Core Debug Receive / Transmit Functions\r
- - Core Debug Defines\r
- - Core Debug Variables\r
-*/\r
-/*@{*/\r
-\r
-extern volatile int ITM_RxBuffer; /*!< variable to receive characters */\r
-#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< value identifying ITM_RxBuffer is ready for next character */\r
-\r
-\r
-/**\r
- * @brief Outputs a character via the ITM channel 0\r
- *\r
- * @param ch character to output\r
- * @return character to output\r
- *\r
- * The function outputs a character via the ITM channel 0. \r
- * The function returns when no debugger is connected that has booked the output. \r
- * It is blocking when a debugger is connected, but the previous character send is not transmitted. \r
- */\r
-static __INLINE uint32_t ITM_SendChar (uint32_t ch)\r
-{\r
- if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk) && /* Trace enabled */\r
- (ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */\r
- (ITM->TER & (1ul << 0) ) ) /* ITM Port #0 enabled */\r
- {\r
- while (ITM->PORT[0].u32 == 0);\r
- ITM->PORT[0].u8 = (uint8_t) ch;\r
- } \r
- return (ch);\r
-}\r
-\r
-\r
-/**\r
- * @brief Inputs a character via variable ITM_RxBuffer\r
- *\r
- * @return received character, -1 = no character received\r
- *\r
- * The function inputs a character via variable ITM_RxBuffer. \r
- * The function returns when no debugger is connected that has booked the output. \r
- * It is blocking when a debugger is connected, but the previous character send is not transmitted. \r
- */\r
-static __INLINE int ITM_ReceiveChar (void) {\r
- int ch = -1; /* no character available */\r
-\r
- if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {\r
- ch = ITM_RxBuffer;\r
- ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */\r
- }\r
- \r
- return (ch); \r
-}\r
-\r
-\r
-/**\r
- * @brief Check if a character via variable ITM_RxBuffer is available\r
- *\r
- * @return 1 = character available, 0 = no character available\r
- *\r
- * The function checks variable ITM_RxBuffer whether a character is available or not. \r
- * The function returns '1' if a character is available and '0' if no character is available. \r
- */\r
-static __INLINE int ITM_CheckChar (void) {\r
-\r
- if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {\r
- return (0); /* no character available */\r
- } else {\r
- return (1); /* character available */\r
- }\r
-}\r
-\r
-/*@}*/ /* end of group CMSIS_CM3_core_DebugInterface */\r
-\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-/*@}*/ /* end of group CMSIS_CM3_core_definitions */\r
-\r
-#endif /* __CM3_CORE_H__ */\r
-\r
-/*lint -restore */\r
<name>C-SPY</name>\r
<archiveVersion>2</archiveVersion>\r
<data>\r
- <version>21</version>\r
+ <version>22</version>\r
<wantNonLocal>1</wantNonLocal>\r
<debug>1</debug>\r
<option>\r
</option>\r
<option>\r
<name>OCLastSavedByProductVersion</name>\r
- <state>5.41.2.51798</state>\r
+ <state>6.20.1.52589</state>\r
</option>\r
<option>\r
<name>OCDownloadAttachToProgram</name>\r
<name>OverrideDefFlashBoard</name>\r
<state>0</state>\r
</option>\r
+ <option>\r
+ <name>OCImagesOffset1</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesOffset2</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesOffset3</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesUse1</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesUse2</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesUse3</name>\r
+ <state>0</state>\r
+ </option>\r
</data>\r
</settings>\r
<settings>\r
<name>IARROM_ID</name>\r
<archiveVersion>2</archiveVersion>\r
<data>\r
- <version>0</version>\r
+ <version>1</version>\r
<wantNonLocal>1</wantNonLocal>\r
<debug>1</debug>\r
<option>\r
<name>CRomLogFileEditB</name>\r
<state>$PROJ_DIR$\cspycomm.log</state>\r
</option>\r
- <option>\r
- <name>CRomCommunication</name>\r
- <state>0</state>\r
- </option>\r
<option>\r
<name>CRomCommPort</name>\r
<version>0</version>\r
<name>JLINK_ID</name>\r
<archiveVersion>2</archiveVersion>\r
<data>\r
- <version>10</version>\r
+ <version>13</version>\r
<wantNonLocal>1</wantNonLocal>\r
<debug>1</debug>\r
<option>\r
</option>\r
<option>\r
<name>CCUSBDevice</name>\r
- <version>0</version>\r
- <state>0</state>\r
+ <version>1</version>\r
+ <state>1</state>\r
</option>\r
<option>\r
<name>CCRDICatchReset</name>\r
</option>\r
<option>\r
<name>CCJLinkResetList</name>\r
- <version>2</version>\r
+ <version>5</version>\r
<state>7</state>\r
</option>\r
<option>\r
<name>CCJLinkInterfaceCmdLine</name>\r
<state>0</state>\r
</option>\r
+ <option>\r
+ <name>CCCatchCORERESET</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCatchMMERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCatchNOCPERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCatchCHRERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCatchSTATERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCatchBUSERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCatchINTERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCatchHARDERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCatchDummy</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCJLinkScriptFile</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkUsbSerialNo</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCTcpIpAlt</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkTcpIpSerialNo</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCCpuClockEdit</name>\r
+ <state>72.0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSwoClockAuto</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSwoClockEdit</name>\r
+ <state>2000</state>\r
+ </option>\r
</data>\r
</settings>\r
<settings>\r
</option>\r
</data>\r
</settings>\r
+ <settings>\r
+ <name>PEMICRO_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>0</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OCPEMicroAttachSlave</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPEMicroInterfaceList</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPEMicroResetDelay</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCPEMicroJtagSpeed</name>\r
+ <state>#UNINITIALIZED#</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJPEMicroShowSettings</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>DoLogfile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>LogFile</name>\r
+ <state>$PROJ_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPEMicroUSBDevice</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPEMicroSerialPort</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJPEMicroTCPIPAutoScanNetwork</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPEMicroTCPIP</name>\r
+ <state>10.0.0.1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPEMicroCommCmdLineProducer</name>\r
+ <state>0</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
<settings>\r
<name>RDI_ID</name>\r
<archiveVersion>2</archiveVersion>\r
<data>\r
- <version>1</version>\r
+ <version>2</version>\r
<wantNonLocal>1</wantNonLocal>\r
<debug>1</debug>\r
<option>\r
<name>CCRDICatchFIQ</name>\r
<state>0</state>\r
</option>\r
- <option>\r
- <name>CCRDIUseETM</name>\r
- <state>0</state>\r
- </option>\r
<option>\r
<name>OCDriverInfo</name>\r
<state>1</state>\r
<name>STLINK_ID</name>\r
<archiveVersion>2</archiveVersion>\r
<data>\r
- <version>1</version>\r
+ <version>2</version>\r
<wantNonLocal>1</wantNonLocal>\r
<debug>1</debug>\r
<option>\r
<name>CCSTLinkInterfaceCmdLine</name>\r
<state>0</state>\r
</option>\r
+ <option>\r
+ <name>CCSTLinkResetList</name>\r
+ <version>1</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCpuClockEdit</name>\r
+ <state>72.0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSwoClockAuto</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSwoClockEdit</name>\r
+ <state>2000</state>\r
+ </option>\r
</data>\r
</settings>\r
<settings>\r
<loadFlag>0</loadFlag>\r
</plugin>\r
<plugin>\r
- <file>$TOOLKIT_DIR$\plugins\rtos\OSE\OseEpsilonPlugin.ewplugin</file>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file>\r
<loadFlag>0</loadFlag>\r
</plugin>\r
<plugin>\r
<loadFlag>0</loadFlag>\r
</plugin>\r
<plugin>\r
- <file>$TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB5_Plugin.ewplugin</file>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB6_Plugin.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file>\r
<loadFlag>0</loadFlag>\r
</plugin>\r
<plugin>\r
<loadFlag>0</loadFlag>\r
</plugin>\r
<plugin>\r
- <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>\r
- <loadFlag>0</loadFlag>\r
- </plugin>\r
- <plugin>\r
- <file>$EW_DIR$\common\plugins\Profiling\Profiling.ENU.ewplugin</file>\r
- <loadFlag>1</loadFlag>\r
- </plugin>\r
- <plugin>\r
- <file>$EW_DIR$\common\plugins\Stack\Stack.ENU.ewplugin</file>\r
- <loadFlag>1</loadFlag>\r
- </plugin>\r
- <plugin>\r
- <file>$EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin</file>\r
- <loadFlag>1</loadFlag>\r
- </plugin>\r
- </debuggerPlugins>\r
- </configuration>\r
- <configuration>\r
- <name>Release</name>\r
- <toolchain>\r
- <name>ARM</name>\r
- </toolchain>\r
- <debug>0</debug>\r
- <settings>\r
- <name>C-SPY</name>\r
- <archiveVersion>2</archiveVersion>\r
- <data>\r
- <version>21</version>\r
- <wantNonLocal>1</wantNonLocal>\r
- <debug>0</debug>\r
- <option>\r
- <name>CInput</name>\r
- <state>1</state>\r
- </option>\r
- <option>\r
- <name>CEndian</name>\r
- <state>1</state>\r
- </option>\r
- <option>\r
- <name>CProcessor</name>\r
- <state>1</state>\r
- </option>\r
- <option>\r
- <name>OCVariant</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>MacOverride</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>MacFile</name>\r
- <state></state>\r
- </option>\r
- <option>\r
- <name>MemOverride</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>MemFile</name>\r
- <state></state>\r
- </option>\r
- <option>\r
- <name>RunToEnable</name>\r
- <state>1</state>\r
- </option>\r
- <option>\r
- <name>RunToName</name>\r
- <state>main</state>\r
- </option>\r
- <option>\r
- <name>CExtraOptionsCheck</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CExtraOptions</name>\r
- <state></state>\r
- </option>\r
- <option>\r
- <name>CFpuProcessor</name>\r
- <state>1</state>\r
- </option>\r
- <option>\r
- <name>OCDDFArgumentProducer</name>\r
- <state></state>\r
- </option>\r
- <option>\r
- <name>OCDownloadSuppressDownload</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>OCDownloadVerifyAll</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>OCProductVersion</name>\r
- <state>5.41.2.51798</state>\r
- </option>\r
- <option>\r
- <name>OCDynDriverList</name>\r
- <state>ARMSIM_ID</state>\r
- </option>\r
- <option>\r
- <name>OCLastSavedByProductVersion</name>\r
- <state></state>\r
- </option>\r
- <option>\r
- <name>OCDownloadAttachToProgram</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>UseFlashLoader</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CLowLevel</name>\r
- <state>1</state>\r
- </option>\r
- <option>\r
- <name>OCBE8Slave</name>\r
- <state>1</state>\r
- </option>\r
- <option>\r
- <name>MacFile2</name>\r
- <state></state>\r
- </option>\r
- <option>\r
- <name>CDevice</name>\r
- <state>1</state>\r
- </option>\r
- <option>\r
- <name>FlashLoadersV3</name>\r
- <state></state>\r
- </option>\r
- <option>\r
- <name>OCImagesSuppressCheck1</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>OCImagesPath1</name>\r
- <state></state>\r
- </option>\r
- <option>\r
- <name>OCImagesSuppressCheck2</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>OCImagesPath2</name>\r
- <state></state>\r
- </option>\r
- <option>\r
- <name>OCImagesSuppressCheck3</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>OCImagesPath3</name>\r
- <state></state>\r
- </option>\r
- <option>\r
- <name>OverrideDefFlashBoard</name>\r
- <state>0</state>\r
- </option>\r
- </data>\r
- </settings>\r
- <settings>\r
- <name>ARMSIM_ID</name>\r
- <archiveVersion>2</archiveVersion>\r
- <data>\r
- <version>1</version>\r
- <wantNonLocal>1</wantNonLocal>\r
- <debug>0</debug>\r
- <option>\r
- <name>OCSimDriverInfo</name>\r
- <state>1</state>\r
- </option>\r
- <option>\r
- <name>OCSimEnablePSP</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>OCSimPspOverrideConfig</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>OCSimPspConfigFile</name>\r
- <state></state>\r
- </option>\r
- </data>\r
- </settings>\r
- <settings>\r
- <name>ANGEL_ID</name>\r
- <archiveVersion>2</archiveVersion>\r
- <data>\r
- <version>0</version>\r
- <wantNonLocal>1</wantNonLocal>\r
- <debug>0</debug>\r
- <option>\r
- <name>CCAngelHeartbeat</name>\r
- <state>1</state>\r
- </option>\r
- <option>\r
- <name>CAngelCommunication</name>\r
- <state>1</state>\r
- </option>\r
- <option>\r
- <name>CAngelCommBaud</name>\r
- <version>0</version>\r
- <state>3</state>\r
- </option>\r
- <option>\r
- <name>CAngelCommPort</name>\r
- <version>0</version>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>ANGELTCPIP</name>\r
- <state>aaa.bbb.ccc.ddd</state>\r
- </option>\r
- <option>\r
- <name>DoAngelLogfile</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>AngelLogFile</name>\r
- <state>$PROJ_DIR$\cspycomm.log</state>\r
- </option>\r
- <option>\r
- <name>OCDriverInfo</name>\r
- <state>1</state>\r
- </option>\r
- </data>\r
- </settings>\r
- <settings>\r
- <name>GDBSERVER_ID</name>\r
- <archiveVersion>2</archiveVersion>\r
- <data>\r
- <version>0</version>\r
- <wantNonLocal>1</wantNonLocal>\r
- <debug>0</debug>\r
- <option>\r
- <name>OCDriverInfo</name>\r
- <state>1</state>\r
- </option>\r
- <option>\r
- <name>TCPIP</name>\r
- <state>aaa.bbb.ccc.ddd</state>\r
- </option>\r
- <option>\r
- <name>DoLogfile</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>LogFile</name>\r
- <state>$PROJ_DIR$\cspycomm.log</state>\r
- </option>\r
- <option>\r
- <name>CCJTagBreakpointRadio</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CCJTagDoUpdateBreakpoints</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CCJTagUpdateBreakpoints</name>\r
- <state>main</state>\r
- </option>\r
- </data>\r
- </settings>\r
- <settings>\r
- <name>IARROM_ID</name>\r
- <archiveVersion>2</archiveVersion>\r
- <data>\r
- <version>0</version>\r
- <wantNonLocal>1</wantNonLocal>\r
- <debug>0</debug>\r
- <option>\r
- <name>CRomLogFileCheck</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CRomLogFileEditB</name>\r
- <state>$PROJ_DIR$\cspycomm.log</state>\r
- </option>\r
- <option>\r
- <name>CRomCommunication</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CRomCommPort</name>\r
- <version>0</version>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CRomCommBaud</name>\r
- <version>0</version>\r
- <state>7</state>\r
- </option>\r
- <option>\r
- <name>OCDriverInfo</name>\r
- <state>1</state>\r
- </option>\r
- </data>\r
- </settings>\r
- <settings>\r
- <name>JLINK_ID</name>\r
- <archiveVersion>2</archiveVersion>\r
- <data>\r
- <version>10</version>\r
- <wantNonLocal>1</wantNonLocal>\r
- <debug>0</debug>\r
- <option>\r
- <name>JLinkSpeed</name>\r
- <state>32</state>\r
- </option>\r
- <option>\r
- <name>CCJLinkDoLogfile</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CCJLinkLogFile</name>\r
- <state>$PROJ_DIR$\cspycomm.log</state>\r
- </option>\r
- <option>\r
- <name>CCJLinkHWResetDelay</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>OCDriverInfo</name>\r
- <state>1</state>\r
- </option>\r
- <option>\r
- <name>JLinkInitialSpeed</name>\r
- <state>32</state>\r
- </option>\r
- <option>\r
- <name>CCDoJlinkMultiTarget</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CCScanChainNonARMDevices</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CCJLinkMultiTarget</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CCJLinkIRLength</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CCJLinkCommRadio</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CCJLinkTCPIP</name>\r
- <state>aaa.bbb.ccc.ddd</state>\r
- </option>\r
- <option>\r
- <name>CCJLinkSpeedRadioV2</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CCUSBDevice</name>\r
- <version>0</version>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CCRDICatchReset</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CCRDICatchUndef</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CCRDICatchSWI</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CCRDICatchData</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CCRDICatchPrefetch</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CCRDICatchIRQ</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CCRDICatchFIQ</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CCJLinkBreakpointRadio</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CCJLinkDoUpdateBreakpoints</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CCJLinkUpdateBreakpoints</name>\r
- <state>main</state>\r
- </option>\r
- <option>\r
- <name>CCJLinkInterfaceRadio</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>OCJLinkAttachSlave</name>\r
- <state>1</state>\r
- </option>\r
- <option>\r
- <name>CCJLinkResetList</name>\r
- <version>2</version>\r
- <state>5</state>\r
- </option>\r
- <option>\r
- <name>CCJLinkInterfaceCmdLine</name>\r
- <state>0</state>\r
- </option>\r
- </data>\r
- </settings>\r
- <settings>\r
- <name>LMIFTDI_ID</name>\r
- <archiveVersion>2</archiveVersion>\r
- <data>\r
- <version>2</version>\r
- <wantNonLocal>1</wantNonLocal>\r
- <debug>0</debug>\r
- <option>\r
- <name>OCDriverInfo</name>\r
- <state>1</state>\r
- </option>\r
- <option>\r
- <name>LmiftdiSpeed</name>\r
- <state>500</state>\r
- </option>\r
- <option>\r
- <name>CCLmiftdiDoLogfile</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CCLmiftdiLogFile</name>\r
- <state>$PROJ_DIR$\cspycomm.log</state>\r
- </option>\r
- <option>\r
- <name>CCLmiFtdiInterfaceRadio</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CCLmiFtdiInterfaceCmdLine</name>\r
- <state>0</state>\r
- </option>\r
- </data>\r
- </settings>\r
- <settings>\r
- <name>MACRAIGOR_ID</name>\r
- <archiveVersion>2</archiveVersion>\r
- <data>\r
- <version>3</version>\r
- <wantNonLocal>1</wantNonLocal>\r
- <debug>0</debug>\r
- <option>\r
- <name>jtag</name>\r
- <version>0</version>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>EmuSpeed</name>\r
- <state>1</state>\r
- </option>\r
- <option>\r
- <name>TCPIP</name>\r
- <state>aaa.bbb.ccc.ddd</state>\r
- </option>\r
- <option>\r
- <name>DoLogfile</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>LogFile</name>\r
- <state>$PROJ_DIR$\cspycomm.log</state>\r
- </option>\r
- <option>\r
- <name>DoEmuMultiTarget</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>EmuMultiTarget</name>\r
- <state>0@ARM7TDMI</state>\r
- </option>\r
- <option>\r
- <name>EmuHWReset</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CEmuCommBaud</name>\r
- <version>0</version>\r
- <state>4</state>\r
- </option>\r
- <option>\r
- <name>CEmuCommPort</name>\r
- <version>0</version>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>jtago</name>\r
- <version>0</version>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>OCDriverInfo</name>\r
- <state>1</state>\r
- </option>\r
- <option>\r
- <name>UnusedAddr</name>\r
- <state>0x00800000</state>\r
- </option>\r
- <option>\r
- <name>CCMacraigorHWResetDelay</name>\r
- <state></state>\r
- </option>\r
- <option>\r
- <name>CCJTagBreakpointRadio</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CCJTagDoUpdateBreakpoints</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CCJTagUpdateBreakpoints</name>\r
- <state>main</state>\r
- </option>\r
- <option>\r
- <name>CCMacraigorInterfaceRadio</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CCMacraigorInterfaceCmdLine</name>\r
- <state>0</state>\r
- </option>\r
- </data>\r
- </settings>\r
- <settings>\r
- <name>RDI_ID</name>\r
- <archiveVersion>2</archiveVersion>\r
- <data>\r
- <version>1</version>\r
- <wantNonLocal>1</wantNonLocal>\r
- <debug>0</debug>\r
- <option>\r
- <name>CRDIDriverDll</name>\r
- <state>###Uninitialized###</state>\r
- </option>\r
- <option>\r
- <name>CRDILogFileCheck</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CRDILogFileEdit</name>\r
- <state>$PROJ_DIR$\cspycomm.log</state>\r
- </option>\r
- <option>\r
- <name>CCRDIHWReset</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CCRDICatchReset</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CCRDICatchUndef</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CCRDICatchSWI</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CCRDICatchData</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CCRDICatchPrefetch</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CCRDICatchIRQ</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CCRDICatchFIQ</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CCRDIUseETM</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>OCDriverInfo</name>\r
- <state>1</state>\r
- </option>\r
- </data>\r
- </settings>\r
- <settings>\r
- <name>STLINK_ID</name>\r
- <archiveVersion>2</archiveVersion>\r
- <data>\r
- <version>1</version>\r
- <wantNonLocal>1</wantNonLocal>\r
- <debug>0</debug>\r
- <option>\r
- <name>OCDriverInfo</name>\r
- <state>1</state>\r
- </option>\r
- <option>\r
- <name>CCSTLinkInterfaceRadio</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CCSTLinkInterfaceCmdLine</name>\r
- <state>0</state>\r
- </option>\r
- </data>\r
- </settings>\r
- <settings>\r
- <name>THIRDPARTY_ID</name>\r
- <archiveVersion>2</archiveVersion>\r
- <data>\r
- <version>0</version>\r
- <wantNonLocal>1</wantNonLocal>\r
- <debug>0</debug>\r
- <option>\r
- <name>CThirdPartyDriverDll</name>\r
- <state>###Uninitialized###</state>\r
- </option>\r
- <option>\r
- <name>CThirdPartyLogFileCheck</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CThirdPartyLogFileEditB</name>\r
- <state>$PROJ_DIR$\cspycomm.log</state>\r
- </option>\r
- <option>\r
- <name>OCDriverInfo</name>\r
- <state>1</state>\r
- </option>\r
- </data>\r
- </settings>\r
- <debuggerPlugins>\r
- <plugin>\r
- <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file>\r
- <loadFlag>0</loadFlag>\r
- </plugin>\r
- <plugin>\r
- <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file>\r
- <loadFlag>0</loadFlag>\r
- </plugin>\r
- <plugin>\r
- <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>\r
- <loadFlag>0</loadFlag>\r
- </plugin>\r
- <plugin>\r
- <file>$TOOLKIT_DIR$\plugins\rtos\OSE\OseEpsilonPlugin.ewplugin</file>\r
- <loadFlag>0</loadFlag>\r
- </plugin>\r
- <plugin>\r
- <file>$TOOLKIT_DIR$\plugins\rtos\PowerPac\PowerPacRTOS.ewplugin</file>\r
- <loadFlag>0</loadFlag>\r
- </plugin>\r
- <plugin>\r
- <file>$TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB5_Plugin.ewplugin</file>\r
- <loadFlag>0</loadFlag>\r
- </plugin>\r
- <plugin>\r
- <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file>\r
- <loadFlag>0</loadFlag>\r
- </plugin>\r
- <plugin>\r
- <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file>\r
- <loadFlag>0</loadFlag>\r
- </plugin>\r
- <plugin>\r
- <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>\r
- <loadFlag>0</loadFlag>\r
- </plugin>\r
- <plugin>\r
- <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin</file>\r
- <loadFlag>1</loadFlag>\r
- </plugin>\r
- <plugin>\r
- <file>$EW_DIR$\common\plugins\FreeRTOS\FreeRTOSPlugin.ewplugin</file>\r
+ <file>$EW_DIR$\common\plugins\OpenRTOS\OpenRTOSPlugin.ewplugin</file>\r
<loadFlag>0</loadFlag>\r
</plugin>\r
<plugin>\r
<file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>\r
<loadFlag>0</loadFlag>\r
</plugin>\r
- <plugin>\r
- <file>$EW_DIR$\common\plugins\Profiling\Profiling.ENU.ewplugin</file>\r
- <loadFlag>1</loadFlag>\r
- </plugin>\r
<plugin>\r
<file>$EW_DIR$\common\plugins\Stack\Stack.ENU.ewplugin</file>\r
<loadFlag>1</loadFlag>\r
<name>General</name>\r
<archiveVersion>3</archiveVersion>\r
<data>\r
- <version>17</version>\r
+ <version>21</version>\r
<wantNonLocal>1</wantNonLocal>\r
<debug>1</debug>\r
<option>\r
</option>\r
<option>\r
<name>Variant</name>\r
- <version>13</version>\r
- <state>36</state>\r
+ <version>19</version>\r
+ <state>37</state>\r
</option>\r
<option>\r
<name>GEndianMode</name>\r
</option>\r
<option>\r
<name>Input variant</name>\r
- <version>1</version>\r
- <state>0</state>\r
+ <version>3</version>\r
+ <state>1</state>\r
</option>\r
<option>\r
<name>Input description</name>\r
</option>\r
<option>\r
<name>Output variant</name>\r
- <version>0</version>\r
- <state>0</state>\r
+ <version>2</version>\r
+ <state>1</state>\r
</option>\r
<option>\r
<name>Output description</name>\r
</option>\r
<option>\r
<name>FPU</name>\r
- <version>0</version>\r
+ <version>2</version>\r
<state>0</state>\r
</option>\r
<option>\r
<name>RTDescription</name>\r
<state>Use the normal configuration of the C/C++ runtime library. No locale interface, C locale, no file descriptor support, no multibytes in printf and scanf, and no hex floats in strtod.</state>\r
</option>\r
- <option>\r
- <name>RTConfigPath</name>\r
- <state>$TOOLKIT_DIR$\INC\DLib_Config_Normal.h</state>\r
- </option>\r
<option>\r
<name>OGProductVersion</name>\r
<state>5.41.0.51757</state>\r
</option>\r
<option>\r
<name>OGLastSavedByProductVersion</name>\r
- <state>5.41.2.51798</state>\r
+ <state>6.20.1.52589</state>\r
</option>\r
<option>\r
<name>GeneralEnableMisra</name>\r
<version>0</version>\r
<state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>\r
</option>\r
+ <option>\r
+ <name>RTConfigPath2</name>\r
+ <state>$TOOLKIT_DIR$\INC\c\DLib_Config_Normal.h</state>\r
+ </option>\r
+ <option>\r
+ <name>GFPUCoreSlave</name>\r
+ <version>19</version>\r
+ <state>37</state>\r
+ </option>\r
+ <option>\r
+ <name>GBECoreSlave</name>\r
+ <version>19</version>\r
+ <state>37</state>\r
+ </option>\r
+ <option>\r
+ <name>OGUseCmsis</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OGUseCmsisDspLib</name>\r
+ <state>0</state>\r
+ </option>\r
</data>\r
</settings>\r
<settings>\r
<name>ICCARM</name>\r
<archiveVersion>2</archiveVersion>\r
<data>\r
- <version>21</version>\r
+ <version>28</version>\r
<wantNonLocal>1</wantNonLocal>\r
<debug>1</debug>\r
<option>\r
<name>OutputFile</name>\r
<state>$FILE_BNAME$.o</state>\r
</option>\r
- <option>\r
- <name>CCLangSelect</name>\r
- <state>0</state>\r
- </option>\r
<option>\r
<name>CCLibConfigHeader</name>\r
<state>1</state>\r
<name>CCStdIncCheck</name>\r
<state>0</state>\r
</option>\r
- <option>\r
- <name>CCStdIncludePath</name>\r
- <state>$TOOLKIT_DIR$\INC\</state>\r
- </option>\r
<option>\r
<name>CCCodeSection</name>\r
<state>.text</state>\r
<version>0</version>\r
<state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>\r
</option>\r
+ <option>\r
+ <name>CCPosIndRopi</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPosIndRwpi</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPosIndNoDynInit</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IccLang</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IccCDialect</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IccAllowVLA</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IccCppDialect</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IccExceptions</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IccRTTI</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IccStaticDestr</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IccCppInlineSemantics</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IccCmsis</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IccFloatSemantics</name>\r
+ <state>0</state>\r
+ </option>\r
</data>\r
</settings>\r
<settings>\r
<name>AARM</name>\r
<archiveVersion>2</archiveVersion>\r
<data>\r
- <version>7</version>\r
+ <version>8</version>\r
<wantNonLocal>1</wantNonLocal>\r
<debug>1</debug>\r
<option>\r
<name>AIgnoreStdInclude</name>\r
<state>0</state>\r
</option>\r
- <option>\r
- <name>AStdIncludes</name>\r
- <state>$TOOLKIT_DIR$\INC\</state>\r
- </option>\r
<option>\r
<name>AUserIncludes</name>\r
<state>$PROJ_DIR$\</state>\r
<name>ILINK</name>\r
<archiveVersion>0</archiveVersion>\r
<data>\r
- <version>8</version>\r
+ <version>13</version>\r
<wantNonLocal>1</wantNonLocal>\r
<debug>1</debug>\r
<option>\r
<name>IlinkIElfToolPostProcess</name>\r
<state>0</state>\r
</option>\r
- </data>\r
- </settings>\r
- <settings>\r
- <name>IARCHIVE</name>\r
- <archiveVersion>0</archiveVersion>\r
- <data>\r
- <version>0</version>\r
- <wantNonLocal>1</wantNonLocal>\r
- <debug>1</debug>\r
- <option>\r
- <name>IarchiveInputs</name>\r
- <state></state>\r
- </option>\r
- <option>\r
- <name>IarchiveOverride</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>IarchiveOutput</name>\r
- <state>###Unitialized###</state>\r
- </option>\r
- </data>\r
- </settings>\r
- <settings>\r
- <name>BILINK</name>\r
- <archiveVersion>0</archiveVersion>\r
- <data/>\r
- </settings>\r
- </configuration>\r
- <configuration>\r
- <name>Release</name>\r
- <toolchain>\r
- <name>ARM</name>\r
- </toolchain>\r
- <debug>0</debug>\r
- <settings>\r
- <name>General</name>\r
- <archiveVersion>3</archiveVersion>\r
- <data>\r
- <version>17</version>\r
- <wantNonLocal>1</wantNonLocal>\r
- <debug>0</debug>\r
- <option>\r
- <name>ExePath</name>\r
- <state>Release\Exe</state>\r
- </option>\r
- <option>\r
- <name>ObjPath</name>\r
- <state>Release\Obj</state>\r
- </option>\r
- <option>\r
- <name>ListPath</name>\r
- <state>Release\List</state>\r
- </option>\r
- <option>\r
- <name>Variant</name>\r
- <version>13</version>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>GEndianMode</name>\r
- <state>0</state>\r
- </option>\r
<option>\r
- <name>Input variant</name>\r
- <version>1</version>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>Input description</name>\r
- <state></state>\r
- </option>\r
- <option>\r
- <name>Output variant</name>\r
- <version>0</version>\r
+ <name>IlinkLogAutoLibSelect</name>\r
<state>0</state>\r
</option>\r
<option>\r
- <name>Output description</name>\r
- <state></state>\r
- </option>\r
- <option>\r
- <name>GOutputBinary</name>\r
+ <name>IlinkLogRedirSymbols</name>\r
<state>0</state>\r
</option>\r
<option>\r
- <name>FPU</name>\r
- <version>0</version>\r
+ <name>IlinkLogUnusedFragments</name>\r
<state>0</state>\r
</option>\r
<option>\r
- <name>OGCoreOrChip</name>\r
+ <name>IlinkCrcReverseByteOrder</name>\r
<state>0</state>\r
</option>\r
<option>\r
- <name>GRuntimeLibSelect</name>\r
- <version>0</version>\r
- <state>1</state>\r
- </option>\r
- <option>\r
- <name>GRuntimeLibSelectSlave</name>\r
- <version>0</version>\r
+ <name>IlinkCrcUseAsInput</name>\r
<state>1</state>\r
</option>\r
<option>\r
- <name>RTDescription</name>\r
- <state></state>\r
- </option>\r
- <option>\r
- <name>RTConfigPath</name>\r
- <state>dl-stnl0.a</state>\r
- </option>\r
- <option>\r
- <name>OGProductVersion</name>\r
- <state>5.41.0.51757</state>\r
- </option>\r
- <option>\r
- <name>OGLastSavedByProductVersion</name>\r
- <state></state>\r
- </option>\r
- <option>\r
- <name>GeneralEnableMisra</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>GeneralMisraVerbose</name>\r
+ <name>IlinkOptInline</name>\r
<state>0</state>\r
</option>\r
<option>\r
- <name>OGChipSelectEditMenu</name>\r
- <state></state>\r
- </option>\r
- <option>\r
- <name>GenLowLevelInterface</name>\r
- <state>0</state>\r
+ <name>IlinkOptExceptionsAllow</name>\r
+ <state>1</state>\r
</option>\r
<option>\r
- <name>GEndianModeBE</name>\r
+ <name>IlinkOptExceptionsForce</name>\r
<state>0</state>\r
</option>\r
<option>\r
- <name>OGBufferedTerminalOutput</name>\r
- <state>0</state>\r
+ <name>IlinkCmsis</name>\r
+ <state>1</state>\r
</option>\r
<option>\r
- <name>GenStdoutInterface</name>\r
+ <name>IlinkOptMergeDuplSections</name>\r
<state>0</state>\r
</option>\r
<option>\r
- <name>GeneralMisraRules98</name>\r
- <version>0</version>\r
- <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>\r
+ <name>IlinkOptUseVfe</name>\r
+ <state>1</state>\r
</option>\r
<option>\r
- <name>GeneralMisraVer</name>\r
+ <name>IlinkOptForceVfe</name>\r
<state>0</state>\r
</option>\r
- <option>\r
- <name>GeneralMisraRules04</name>\r
- <version>0</version>\r
- <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>\r
- </option>\r
</data>\r
</settings>\r
<settings>\r
- <name>ICCARM</name>\r
- <archiveVersion>2</archiveVersion>\r
+ <name>IARCHIVE</name>\r
+ <archiveVersion>0</archiveVersion>\r
<data>\r
- <version>21</version>\r
+ <version>0</version>\r
<wantNonLocal>1</wantNonLocal>\r
- <debug>0</debug>\r
- <option>\r
- <name>CCDefines</name>\r
- <state>NDEBUG</state>\r
- </option>\r
- <option>\r
- <name>CCPreprocFile</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CCPreprocComments</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CCPreprocLine</name>\r
- <state>0</state>\r
- </option>\r
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- <Top><Row0><Sizes><Toolbar-00abb208><key>iaridepm.enu1</key></Toolbar-00abb208></Sizes></Row0><Row1><Sizes/></Row1></Top><Left><Row0><Sizes><Wnd0><Rect><Top>-2</Top><Left>-2</Left><Bottom>740</Bottom><Right>302</Right><x>-2</x><y>-2</y><xscreen>200</xscreen><yscreen>200</yscreen><sizeHorzCX>119048</sizeHorzCX><sizeHorzCY>203666</sizeHorzCY><sizeVertCX>180952</sizeVertCX><sizeVertCY>755601</sizeVertCY></Rect></Wnd0></Sizes></Row0></Left><Right><Row0><Sizes/></Row0></Right><Bottom><Row0><Sizes><Wnd1><Rect><Top>-2</Top><Left>-2</Left><Bottom>198</Bottom><Right>1682</Right><x>-2</x><y>-2</y><xscreen>1684</xscreen><yscreen>200</yscreen><sizeHorzCX>1002381</sizeHorzCX><sizeHorzCY>203666</sizeHorzCY><sizeVertCX>119048</sizeVertCX><sizeVertCY>203666</sizeVertCY></Rect></Wnd1></Sizes></Row0></Bottom><Float><Sizes/></Float></Positions>\r
+ <Top><Row0><Sizes><Toolbar-01336218><key>iaridepm.enu1</key></Toolbar-01336218></Sizes></Row0></Top><Left><Row0><Sizes><Wnd0><Rect><Top>-2</Top><Left>-2</Left><Bottom>740</Bottom><Right>302</Right><x>-2</x><y>-2</y><xscreen>200</xscreen><yscreen>200</yscreen><sizeHorzCX>119048</sizeHorzCX><sizeHorzCY>203666</sizeHorzCY><sizeVertCX>180952</sizeVertCX><sizeVertCY>755601</sizeVertCY></Rect></Wnd0></Sizes></Row0></Left><Right><Row0><Sizes/></Row0></Right><Bottom><Row0><Sizes><Wnd1><Rect><Top>-2</Top><Left>-2</Left><Bottom>198</Bottom><Right>1682</Right><x>-2</x><y>-2</y><xscreen>1684</xscreen><yscreen>200</yscreen><sizeHorzCX>1002381</sizeHorzCX><sizeHorzCY>203666</sizeHorzCY><sizeVertCX>119048</sizeVertCX><sizeVertCY>203666</sizeVertCY></Rect></Wnd1></Sizes></Row0></Bottom><Float><Sizes/></Float></Positions>\r
</Desktop>\r
</Workspace>\r
\r
<?xml version="1.0" encoding="iso-8859-1"?>\r
\r
<project>\r
- <fileVersion>1</fileVersion>\r
+ <fileVersion>2</fileVersion>\r
<configuration>\r
<name>Debug</name>\r
<toolchain>\r
<name>C-SPY</name>\r
<archiveVersion>2</archiveVersion>\r
<data>\r
- <version>15</version>\r
+ <version>22</version>\r
<wantNonLocal>1</wantNonLocal>\r
<debug>1</debug>\r
<option>\r
</option>\r
<option>\r
<name>MemFile</name>\r
- <state>$TOOLKIT_DIR$\CONFIG\debugger\Luminary\iolm3s316.ddf</state>\r
+ <state>$TOOLKIT_DIR$\CONFIG\debugger\TexasInstruments\iolm3s316.ddf</state>\r
</option>\r
<option>\r
<name>RunToEnable</name>\r
</option>\r
<option>\r
<name>OCLastSavedByProductVersion</name>\r
- <state>5.11.0.50615</state>\r
+ <state>6.20.1.52589</state>\r
</option>\r
<option>\r
<name>OCDownloadAttachToProgram</name>\r
<state>0</state>\r
</option>\r
- <option>\r
- <name>FlashLoaders</name>\r
- <state>,,,,(default),</state>\r
- </option>\r
<option>\r
<name>UseFlashLoader</name>\r
<state>1</state>\r
<name>OCBE8Slave</name>\r
<state>1</state>\r
</option>\r
+ <option>\r
+ <name>MacFile2</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CDevice</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>FlashLoadersV3</name>\r
+ <state>$TOOLKIT_DIR$\config\flashloader\TexasInstruments\FlashLM3S3xx.board</state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesSuppressCheck1</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesPath1</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesSuppressCheck2</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesPath2</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesSuppressCheck3</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesPath3</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OverrideDefFlashBoard</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesOffset1</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesOffset2</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesOffset3</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesUse1</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesUse2</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesUse3</name>\r
+ <state>0</state>\r
+ </option>\r
</data>\r
</settings>\r
<settings>\r
<name>IARROM_ID</name>\r
<archiveVersion>2</archiveVersion>\r
<data>\r
- <version>0</version>\r
+ <version>1</version>\r
<wantNonLocal>1</wantNonLocal>\r
<debug>1</debug>\r
<option>\r
<name>CRomLogFileEditB</name>\r
<state>$TOOLKIT_DIR$\cspycomm.log</state>\r
</option>\r
- <option>\r
- <name>CRomCommunication</name>\r
- <state>0</state>\r
- </option>\r
<option>\r
<name>CRomCommPort</name>\r
<version>0</version>\r
<name>JLINK_ID</name>\r
<archiveVersion>2</archiveVersion>\r
<data>\r
- <version>9</version>\r
+ <version>13</version>\r
<wantNonLocal>1</wantNonLocal>\r
<debug>1</debug>\r
<option>\r
</option>\r
<option>\r
<name>CCUSBDevice</name>\r
- <version>0</version>\r
- <state>0</state>\r
+ <version>1</version>\r
+ <state>1</state>\r
</option>\r
<option>\r
<name>CCRDICatchReset</name>\r
</option>\r
<option>\r
<name>CCJLinkResetList</name>\r
+ <version>5</version>\r
+ <state>7</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkInterfaceCmdLine</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCatchCORERESET</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCatchMMERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCatchNOCPERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCatchCHRERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCatchSTATERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCatchBUSERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCatchINTERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCatchHARDERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCatchDummy</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCJLinkScriptFile</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkUsbSerialNo</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCTcpIpAlt</name>\r
<version>0</version>\r
- <state>5</state>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkTcpIpSerialNo</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCCpuClockEdit</name>\r
+ <state>72.0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSwoClockAuto</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSwoClockEdit</name>\r
+ <state>2000</state>\r
</option>\r
</data>\r
</settings>\r
<name>LMIFTDI_ID</name>\r
<archiveVersion>2</archiveVersion>\r
<data>\r
- <version>1</version>\r
+ <version>2</version>\r
<wantNonLocal>1</wantNonLocal>\r
<debug>1</debug>\r
<option>\r
<name>CCLmiftdiLogFile</name>\r
<state>$TOOLKIT_DIR$\cspycomm.log</state>\r
</option>\r
+ <option>\r
+ <name>CCLmiFtdiInterfaceRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCLmiFtdiInterfaceCmdLine</name>\r
+ <state>0</state>\r
+ </option>\r
</data>\r
</settings>\r
<settings>\r
<name>MACRAIGOR_ID</name>\r
<archiveVersion>2</archiveVersion>\r
<data>\r
- <version>2</version>\r
+ <version>3</version>\r
<wantNonLocal>1</wantNonLocal>\r
<debug>1</debug>\r
<option>\r
<name>CCJTagUpdateBreakpoints</name>\r
<state>main</state>\r
</option>\r
+ <option>\r
+ <name>CCMacraigorInterfaceRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCMacraigorInterfaceCmdLine</name>\r
+ <state>0</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>PEMICRO_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>0</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OCPEMicroAttachSlave</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPEMicroInterfaceList</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPEMicroResetDelay</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCPEMicroJtagSpeed</name>\r
+ <state>#UNINITIALIZED#</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJPEMicroShowSettings</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>DoLogfile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>LogFile</name>\r
+ <state>$PROJ_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPEMicroUSBDevice</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPEMicroSerialPort</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJPEMicroTCPIPAutoScanNetwork</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPEMicroTCPIP</name>\r
+ <state>10.0.0.1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPEMicroCommCmdLineProducer</name>\r
+ <state>0</state>\r
+ </option>\r
</data>\r
</settings>\r
<settings>\r
<name>RDI_ID</name>\r
<archiveVersion>2</archiveVersion>\r
<data>\r
- <version>1</version>\r
+ <version>2</version>\r
<wantNonLocal>1</wantNonLocal>\r
<debug>1</debug>\r
<option>\r
<state>0</state>\r
</option>\r
<option>\r
- <name>CCRDIUseETM</name>\r
- <state>0</state>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
</option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>STLINK_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>2</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
<option>\r
<name>OCDriverInfo</name>\r
<state>1</state>\r
</option>\r
+ <option>\r
+ <name>CCSTLinkInterfaceRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSTLinkInterfaceCmdLine</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSTLinkResetList</name>\r
+ <version>1</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCpuClockEdit</name>\r
+ <state>72.0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSwoClockAuto</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSwoClockEdit</name>\r
+ <state>2000</state>\r
+ </option>\r
</data>\r
</settings>\r
<settings>\r
</settings>\r
<debuggerPlugins>\r
<plugin>\r
- <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ewplugin</file>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file>\r
<loadFlag>0</loadFlag>\r
</plugin>\r
<plugin>\r
- <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ewplugin</file>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file>\r
<loadFlag>0</loadFlag>\r
</plugin>\r
<plugin>\r
<loadFlag>0</loadFlag>\r
</plugin>\r
<plugin>\r
- <file>$TOOLKIT_DIR$\plugins\rtos\OSE\OseEpsilonPlugin.ewplugin</file>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file>\r
<loadFlag>0</loadFlag>\r
</plugin>\r
<plugin>\r
<loadFlag>0</loadFlag>\r
</plugin>\r
<plugin>\r
- <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ewplugin</file>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB6_Plugin.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file>\r
<loadFlag>0</loadFlag>\r
</plugin>\r
<plugin>\r
<loadFlag>0</loadFlag>\r
</plugin>\r
<plugin>\r
- <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>\r
+ <file>$EW_DIR$\common\plugins\FreeRTOS\FreeRTOSPlugin.ewplugin</file>\r
<loadFlag>0</loadFlag>\r
</plugin>\r
<plugin>\r
- <file>$EW_DIR$\common\plugins\Profiling\Profiling.ENU.ewplugin</file>\r
+ <file>$EW_DIR$\common\plugins\OpenRTOS\OpenRTOSPlugin.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>\r
<loadFlag>0</loadFlag>\r
</plugin>\r
<plugin>\r
<file>$EW_DIR$\common\plugins\Stack\Stack.ENU.ewplugin</file>\r
<loadFlag>0</loadFlag>\r
</plugin>\r
+ <plugin>\r
+ <file>$EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin</file>\r
+ <loadFlag>1</loadFlag>\r
+ </plugin>\r
</debuggerPlugins>\r
</configuration>\r
</project>\r
<?xml version="1.0" encoding="iso-8859-1"?>\r
\r
<project>\r
- <fileVersion>1</fileVersion>\r
+ <fileVersion>2</fileVersion>\r
<configuration>\r
<name>Debug</name>\r
<toolchain>\r
<name>General</name>\r
<archiveVersion>3</archiveVersion>\r
<data>\r
- <version>14</version>\r
+ <version>21</version>\r
<wantNonLocal>1</wantNonLocal>\r
<debug>1</debug>\r
<option>\r
</option>\r
<option>\r
<name>Variant</name>\r
- <version>7</version>\r
- <state>31</state>\r
+ <version>19</version>\r
+ <state>37</state>\r
</option>\r
<option>\r
<name>GEndianMode</name>\r
</option>\r
<option>\r
<name>Input variant</name>\r
- <version>1</version>\r
- <state>3</state>\r
+ <version>3</version>\r
+ <state>6</state>\r
</option>\r
<option>\r
<name>Input description</name>\r
</option>\r
<option>\r
<name>Output variant</name>\r
- <version>0</version>\r
- <state>3</state>\r
+ <version>2</version>\r
+ <state>7</state>\r
</option>\r
<option>\r
<name>Output description</name>\r
</option>\r
<option>\r
<name>FPU</name>\r
- <version>0</version>\r
+ <version>2</version>\r
<state>0</state>\r
</option>\r
<option>\r
<name>RTDescription</name>\r
<state>Use the normal configuration of the C/C++ runtime library. No locale interface, C locale, no file descriptor support, no multibytes in printf and scanf, and no hex floats in strtod.</state>\r
</option>\r
- <option>\r
- <name>RTConfigPath</name>\r
- <state>$TOOLKIT_DIR$\INC\DLib_Config_Normal.h</state>\r
- </option>\r
<option>\r
<name>OGProductVersion</name>\r
<state>4.39B</state>\r
<name>OGLastSavedByProductVersion</name>\r
<state>5.11.0.50615</state>\r
</option>\r
- <option>\r
- <name>GeneralMisraRules</name>\r
- <version>0</version>\r
- <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>\r
- </option>\r
<option>\r
<name>GeneralEnableMisra</name>\r
<state>0</state>\r
<name>OGBufferedTerminalOutput</name>\r
<state>0</state>\r
</option>\r
+ <option>\r
+ <name>GenStdoutInterface</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>GeneralMisraRules98</name>\r
+ <version>0</version>\r
+ <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>\r
+ </option>\r
+ <option>\r
+ <name>GeneralMisraVer</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>GeneralMisraRules04</name>\r
+ <version>0</version>\r
+ <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>\r
+ </option>\r
+ <option>\r
+ <name>RTConfigPath2</name>\r
+ <state>$TOOLKIT_DIR$\INC\c\DLib_Config_Normal.h</state>\r
+ </option>\r
+ <option>\r
+ <name>GFPUCoreSlave</name>\r
+ <version>19</version>\r
+ <state>37</state>\r
+ </option>\r
+ <option>\r
+ <name>GBECoreSlave</name>\r
+ <version>19</version>\r
+ <state>37</state>\r
+ </option>\r
+ <option>\r
+ <name>OGUseCmsis</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OGUseCmsisDspLib</name>\r
+ <state>0</state>\r
+ </option>\r
</data>\r
</settings>\r
<settings>\r
<name>ICCARM</name>\r
<archiveVersion>2</archiveVersion>\r
<data>\r
- <version>19</version>\r
+ <version>28</version>\r
<wantNonLocal>1</wantNonLocal>\r
<debug>1</debug>\r
<option>\r
<name>OutputFile</name>\r
<state>$FILE_BNAME$.o</state>\r
</option>\r
- <option>\r
- <name>CCLangSelect</name>\r
- <state>0</state>\r
- </option>\r
<option>\r
<name>CCLibConfigHeader</name>\r
<state>1</state>\r
<name>PreInclude</name>\r
<state></state>\r
</option>\r
- <option>\r
- <name>CompilerMisraRules</name>\r
- <version>0</version>\r
- <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>\r
- </option>\r
<option>\r
<name>CompilerMisraOverride</name>\r
<state>0</state>\r
<name>CCStdIncCheck</name>\r
<state>0</state>\r
</option>\r
- <option>\r
- <name>CCStdIncludePath</name>\r
- <state>$TOOLKIT_DIR$\INC\</state>\r
- </option>\r
<option>\r
<name>CCCodeSection</name>\r
<state>.text</state>\r
<name>CCOptLevelSlave</name>\r
<state>1</state>\r
</option>\r
+ <option>\r
+ <name>CompilerMisraRules98</name>\r
+ <version>0</version>\r
+ <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>\r
+ </option>\r
+ <option>\r
+ <name>CompilerMisraRules04</name>\r
+ <version>0</version>\r
+ <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPosIndRopi</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPosIndRwpi</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPosIndNoDynInit</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IccLang</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IccCDialect</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IccAllowVLA</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IccCppDialect</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IccExceptions</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IccRTTI</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IccStaticDestr</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IccCppInlineSemantics</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IccCmsis</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IccFloatSemantics</name>\r
+ <state>0</state>\r
+ </option>\r
</data>\r
</settings>\r
<settings>\r
<name>AARM</name>\r
<archiveVersion>2</archiveVersion>\r
<data>\r
- <version>7</version>\r
+ <version>8</version>\r
<wantNonLocal>1</wantNonLocal>\r
<debug>1</debug>\r
<option>\r
<name>AIgnoreStdInclude</name>\r
<state>0</state>\r
</option>\r
- <option>\r
- <name>AStdIncludes</name>\r
- <state>$TOOLKIT_DIR$\INC\</state>\r
- </option>\r
<option>\r
<name>AUserIncludes</name>\r
<state>$PROJ_DIR$\</state>\r
<debug>1</debug>\r
<option>\r
<name>OOCOutputFormat</name>\r
- <version>1</version>\r
+ <version>2</version>\r
<state>0</state>\r
</option>\r
<option>\r
<name>ILINK</name>\r
<archiveVersion>0</archiveVersion>\r
<data>\r
- <version>5</version>\r
+ <version>13</version>\r
<wantNonLocal>1</wantNonLocal>\r
<debug>1</debug>\r
<option>\r
<name>IlinkProgramEntryLabel</name>\r
<state>__iar_program_start</state>\r
</option>\r
- <option>\r
- <name>IlinkNXPLPCChecksum</name>\r
- <state>0</state>\r
- </option>\r
<option>\r
<name>DoFill</name>\r
<state>0</state>\r
<name>IlinkBufferedTerminalOutput</name>\r
<state>1</state>\r
</option>\r
+ <option>\r
+ <name>IlinkStdoutInterfaceSlave</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CrcFullSize</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkIElfToolPostProcess</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkLogAutoLibSelect</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkLogRedirSymbols</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkLogUnusedFragments</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkCrcReverseByteOrder</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkCrcUseAsInput</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkOptInline</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkOptExceptionsAllow</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkOptExceptionsForce</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkCmsis</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkOptMergeDuplSections</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkOptUseVfe</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkOptForceVfe</name>\r
+ <state>0</state>\r
+ </option>\r
</data>\r
</settings>\r
<settings>\r
[TermIOLog]\r
LoggingEnabled=_ 0\r
LogFile=_ ""\r
-[Disassemble mode]\r
-mode=1\r
[Breakpoints]\r
Count=0\r
[TraceHelper]\r
Enabled=0\r
ShowSource=1\r
+[Stack]\r
+FillEnabled=0\r
+OverflowWarningsEnabled=1\r
+WarningThreshold=90\r
+SpWarningsEnabled=1\r
+WarnLogOnly=1\r
+UseTrigger=1\r
+TriggerName=main\r
+LimitSize=0\r
+ByteLimit=50\r
+[Disassemble mode]\r
+mode=1\r
+[Breakpoints2]\r
+Count=0\r
+[Aliases]\r
+Count=0\r
+SuppressDialog=0\r
\r
\r
\r
- <Column0>186</Column0><Column1>27</Column1><Column2>27</Column2><Column3>27</Column3></ColumnWidths>\r
+ <Column0>238</Column0><Column1>27</Column1><Column2>27</Column2><Column3>27</Column3></ColumnWidths>\r
</Workspace>\r
<Build>\r
\r
<Windows>\r
\r
\r
- <Wnd0>\r
+ <Wnd2>\r
<Tabs>\r
<Tab>\r
<Identity>TabID-2928-28933</Identity>\r
<Factory>Workspace</Factory>\r
<Session>\r
\r
- <NodeDict><ExpandedNode>RTOSDemo</ExpandedNode><ExpandedNode>RTOSDemo/Libraries</ExpandedNode></NodeDict></Session>\r
+ <NodeDict><ExpandedNode>RTOSDemo</ExpandedNode><ExpandedNode>RTOSDemo/Demo Source</ExpandedNode><ExpandedNode>RTOSDemo/Libraries</ExpandedNode></NodeDict></Session>\r
</Tab>\r
</Tabs>\r
\r
- <SelectedTab>0</SelectedTab></Wnd0><Wnd1><Tabs><Tab><Identity>TabID-24894-24921</Identity><TabName>Build</TabName><Factory>Build</Factory><Session/></Tab><Tab><Identity>TabID-10790-31422</Identity><TabName>Debug Log</TabName><Factory>Debug-Log</Factory><Session/></Tab><Tab><Identity>TabID-27705-5723</Identity><TabName>Find in Files</TabName><Factory>Find-in-Files</Factory><Session/></Tab></Tabs><SelectedTab>0</SelectedTab></Wnd1></Windows>\r
+ <SelectedTab>0</SelectedTab></Wnd2><Wnd3><Tabs><Tab><Identity>TabID-24894-24921</Identity><TabName>Build</TabName><Factory>Build</Factory><Session/></Tab><Tab><Identity>TabID-10790-31422</Identity><TabName>Debug Log</TabName><Factory>Debug-Log</Factory><Session/></Tab><Tab><Identity>TabID-27705-5723</Identity><TabName>Find in Files</TabName><Factory>Find-in-Files</Factory><Session/></Tab></Tabs><SelectedTab>0</SelectedTab></Wnd3></Windows>\r
<Editor>\r
\r
\r
\r
\r
- <Pane><Tab><Factory>TextEditor</Factory><Filename>
C:\E\Dev\FreeRTOS\WorkingCopy2\Demo\CORTEX_LM3S316_IAR\main.c</Filename><XPos>0</XPos><YPos>195</YPos><SelStart>8048</SelStart><SelEnd>8048</SelEnd></Tab><ActiveTab>0</ActiveTab></Pane><ActivePane>0</ActivePane><Sizes><Pane><X>1000000</X><Y>1000000</Y></Pane></Sizes><SplitMode>1</SplitMode></Editor>
\r+ <Pane><Tab><Factory>TextEditor</Factory><Filename>
$WS_DIR$\main.c</Filename><XPos>0</XPos><YPos>0</YPos><SelStart>0</SelStart><SelEnd>0</SelEnd></Tab><ActiveTab>0</ActiveTab></Pane><ActivePane>0</ActivePane><Sizes><Pane><X>1000000</X><Y>1000000</Y></Pane></Sizes><SplitMode>1</SplitMode></Editor>
\r <Positions>\r
\r
\r
\r
\r
\r
- <Top><Row0><Sizes><Toolbar-01282618><key>iaridepm.enu1</key></Toolbar-01282618></Sizes></Row0><Row1><Sizes/></Row1></Top><Left><Row0><Sizes><Wnd0><Rect><Top>-2</Top><Left>-2</Left><Bottom>738</Bottom><Right>260</Right><x>-2</x><y>-2</y><xscreen>200</xscreen><yscreen>202</yscreen><sizeHorzCX>142857</sizeHorzCX><sizeHorzCY>205703</sizeHorzCY><sizeVertCX>187143</sizeVertCX><sizeVertCY>753564</sizeVertCY></Rect></Wnd0></Sizes></Row0></Left><Right><Row0><Sizes/></Row0></Right><Bottom><Row0><Sizes><Wnd1><Rect><Top>-2</Top><Left>-2</Left><Bottom>200</Bottom><Right>1402</Right><x>-2</x><y>-2</y><xscreen>1404</xscreen><yscreen>202</yscreen><sizeHorzCX>1002857</sizeHorzCX><sizeHorzCY>205703</sizeHorzCY><sizeVertCX>142857</sizeVertCX><sizeVertCY>205703</sizeVertCY></Rect></Wnd1></Sizes></Row0></Bottom><Float><Sizes/></Float></Positions>\r
+ <Top><Row0><Sizes><Toolbar-01336218><key>iaridepm.enu1</key></Toolbar-01336218></Sizes></Row0></Top><Left><Row0><Sizes><Wnd2><Rect><Top>-2</Top><Left>-2</Left><Bottom>738</Bottom><Right>312</Right><x>-2</x><y>-2</y><xscreen>240</xscreen><yscreen>202</yscreen><sizeHorzCX>142857</sizeHorzCX><sizeHorzCY>205703</sizeHorzCY><sizeVertCX>186905</sizeVertCX><sizeVertCY>753564</sizeVertCY></Rect></Wnd2></Sizes></Row0></Left><Right><Row0><Sizes/></Row0></Right><Bottom><Row0><Sizes><Wnd3><Rect><Top>-2</Top><Left>-2</Left><Bottom>200</Bottom><Right>1682</Right><x>-2</x><y>-2</y><xscreen>1684</xscreen><yscreen>202</yscreen><sizeHorzCX>1002381</sizeHorzCX><sizeHorzCY>205703</sizeHorzCY><sizeVertCX>142857</sizeVertCX><sizeVertCY>205703</sizeVertCY></Rect></Wnd3></Sizes></Row0></Bottom><Float><Sizes/></Float></Positions>\r
</Desktop>\r
</Workspace>\r
\r
<?xml version="1.0" encoding="iso-8859-1"?>\r
\r
<project>\r
- <fileVersion>1</fileVersion>\r
+ <fileVersion>2</fileVersion>\r
<configuration>\r
<name>Debug</name>\r
<toolchain>\r
<name>C-SPY</name>\r
<archiveVersion>2</archiveVersion>\r
<data>\r
- <version>15</version>\r
+ <version>22</version>\r
<wantNonLocal>1</wantNonLocal>\r
<debug>1</debug>\r
<option>\r
</option>\r
<option>\r
<name>MemFile</name>\r
- <state>$TOOLKIT_DIR$\CONFIG\debugger\Luminary\iolm3s811.ddf</state>\r
+ <state>$TOOLKIT_DIR$\CONFIG\debugger\TexasInstruments\iolm3s811.ddf</state>\r
</option>\r
<option>\r
<name>RunToEnable</name>\r
</option>\r
<option>\r
<name>OCLastSavedByProductVersion</name>\r
- <state>5.11.0.50615</state>\r
+ <state>6.20.1.52589</state>\r
</option>\r
<option>\r
<name>OCDownloadAttachToProgram</name>\r
<state>0</state>\r
</option>\r
- <option>\r
- <name>FlashLoaders</name>\r
- <state>,,,,(default),</state>\r
- </option>\r
<option>\r
<name>UseFlashLoader</name>\r
<state>1</state>\r
<name>OCBE8Slave</name>\r
<state>1</state>\r
</option>\r
+ <option>\r
+ <name>MacFile2</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CDevice</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>FlashLoadersV3</name>\r
+ <state>$TOOLKIT_DIR$\config\flashloader\TexasInstruments\FlashLM3S8xx.board</state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesSuppressCheck1</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesPath1</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesSuppressCheck2</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesPath2</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesSuppressCheck3</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesPath3</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OverrideDefFlashBoard</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesOffset1</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesOffset2</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesOffset3</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesUse1</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesUse2</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesUse3</name>\r
+ <state>0</state>\r
+ </option>\r
</data>\r
</settings>\r
<settings>\r
<name>IARROM_ID</name>\r
<archiveVersion>2</archiveVersion>\r
<data>\r
- <version>0</version>\r
+ <version>1</version>\r
<wantNonLocal>1</wantNonLocal>\r
<debug>1</debug>\r
<option>\r
<name>CRomLogFileEditB</name>\r
<state>$TOOLKIT_DIR$\cspycomm.log</state>\r
</option>\r
- <option>\r
- <name>CRomCommunication</name>\r
- <state>0</state>\r
- </option>\r
<option>\r
<name>CRomCommPort</name>\r
<version>0</version>\r
<name>JLINK_ID</name>\r
<archiveVersion>2</archiveVersion>\r
<data>\r
- <version>9</version>\r
+ <version>13</version>\r
<wantNonLocal>1</wantNonLocal>\r
<debug>1</debug>\r
<option>\r
</option>\r
<option>\r
<name>CCUSBDevice</name>\r
- <version>0</version>\r
- <state>0</state>\r
+ <version>1</version>\r
+ <state>1</state>\r
</option>\r
<option>\r
<name>CCRDICatchReset</name>\r
</option>\r
<option>\r
<name>CCJLinkResetList</name>\r
- <version>0</version>\r
+ <version>5</version>\r
<state>5</state>\r
</option>\r
+ <option>\r
+ <name>CCJLinkInterfaceCmdLine</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCatchCORERESET</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCatchMMERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCatchNOCPERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCatchCHRERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCatchSTATERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCatchBUSERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCatchINTERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCatchHARDERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCatchDummy</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCJLinkScriptFile</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkUsbSerialNo</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCTcpIpAlt</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkTcpIpSerialNo</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCCpuClockEdit</name>\r
+ <state>72.0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSwoClockAuto</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSwoClockEdit</name>\r
+ <state>2000</state>\r
+ </option>\r
</data>\r
</settings>\r
<settings>\r
<name>LMIFTDI_ID</name>\r
<archiveVersion>2</archiveVersion>\r
<data>\r
- <version>1</version>\r
+ <version>2</version>\r
<wantNonLocal>1</wantNonLocal>\r
<debug>1</debug>\r
<option>\r
<name>CCLmiftdiLogFile</name>\r
<state>$TOOLKIT_DIR$\cspycomm.log</state>\r
</option>\r
+ <option>\r
+ <name>CCLmiFtdiInterfaceRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCLmiFtdiInterfaceCmdLine</name>\r
+ <state>0</state>\r
+ </option>\r
</data>\r
</settings>\r
<settings>\r
<name>MACRAIGOR_ID</name>\r
<archiveVersion>2</archiveVersion>\r
<data>\r
- <version>2</version>\r
+ <version>3</version>\r
<wantNonLocal>1</wantNonLocal>\r
<debug>1</debug>\r
<option>\r
<name>CCJTagUpdateBreakpoints</name>\r
<state>main</state>\r
</option>\r
+ <option>\r
+ <name>CCMacraigorInterfaceRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCMacraigorInterfaceCmdLine</name>\r
+ <state>0</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>PEMICRO_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>0</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OCPEMicroAttachSlave</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPEMicroInterfaceList</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPEMicroResetDelay</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCPEMicroJtagSpeed</name>\r
+ <state>#UNINITIALIZED#</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJPEMicroShowSettings</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>DoLogfile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>LogFile</name>\r
+ <state>$PROJ_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPEMicroUSBDevice</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPEMicroSerialPort</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJPEMicroTCPIPAutoScanNetwork</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPEMicroTCPIP</name>\r
+ <state>10.0.0.1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPEMicroCommCmdLineProducer</name>\r
+ <state>0</state>\r
+ </option>\r
</data>\r
</settings>\r
<settings>\r
<name>RDI_ID</name>\r
<archiveVersion>2</archiveVersion>\r
<data>\r
- <version>1</version>\r
+ <version>2</version>\r
<wantNonLocal>1</wantNonLocal>\r
<debug>1</debug>\r
<option>\r
<state>0</state>\r
</option>\r
<option>\r
- <name>CCRDIUseETM</name>\r
- <state>0</state>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
</option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>STLINK_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>2</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
<option>\r
<name>OCDriverInfo</name>\r
<state>1</state>\r
</option>\r
+ <option>\r
+ <name>CCSTLinkInterfaceRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSTLinkInterfaceCmdLine</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSTLinkResetList</name>\r
+ <version>1</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCpuClockEdit</name>\r
+ <state>72.0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSwoClockAuto</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSwoClockEdit</name>\r
+ <state>2000</state>\r
+ </option>\r
</data>\r
</settings>\r
<settings>\r
</settings>\r
<debuggerPlugins>\r
<plugin>\r
- <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ewplugin</file>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file>\r
<loadFlag>0</loadFlag>\r
</plugin>\r
<plugin>\r
- <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ewplugin</file>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file>\r
<loadFlag>0</loadFlag>\r
</plugin>\r
<plugin>\r
<loadFlag>0</loadFlag>\r
</plugin>\r
<plugin>\r
- <file>$TOOLKIT_DIR$\plugins\rtos\OSE\OseEpsilonPlugin.ewplugin</file>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file>\r
<loadFlag>0</loadFlag>\r
</plugin>\r
<plugin>\r
<loadFlag>0</loadFlag>\r
</plugin>\r
<plugin>\r
- <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ewplugin</file>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB6_Plugin.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file>\r
<loadFlag>0</loadFlag>\r
</plugin>\r
<plugin>\r
<loadFlag>0</loadFlag>\r
</plugin>\r
<plugin>\r
- <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>\r
+ <file>$EW_DIR$\common\plugins\FreeRTOS\FreeRTOSPlugin.ewplugin</file>\r
<loadFlag>0</loadFlag>\r
</plugin>\r
<plugin>\r
- <file>$EW_DIR$\common\plugins\Profiling\Profiling.ENU.ewplugin</file>\r
+ <file>$EW_DIR$\common\plugins\OpenRTOS\OpenRTOSPlugin.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>\r
<loadFlag>0</loadFlag>\r
</plugin>\r
<plugin>\r
<file>$EW_DIR$\common\plugins\Stack\Stack.ENU.ewplugin</file>\r
<loadFlag>0</loadFlag>\r
</plugin>\r
+ <plugin>\r
+ <file>$EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin</file>\r
+ <loadFlag>1</loadFlag>\r
+ </plugin>\r
</debuggerPlugins>\r
</configuration>\r
</project>\r
<?xml version="1.0" encoding="iso-8859-1"?>\r
\r
<project>\r
- <fileVersion>1</fileVersion>\r
+ <fileVersion>2</fileVersion>\r
<configuration>\r
<name>Debug</name>\r
<toolchain>\r
<name>General</name>\r
<archiveVersion>3</archiveVersion>\r
<data>\r
- <version>14</version>\r
+ <version>21</version>\r
<wantNonLocal>1</wantNonLocal>\r
<debug>1</debug>\r
<option>\r
</option>\r
<option>\r
<name>Variant</name>\r
- <version>7</version>\r
- <state>31</state>\r
+ <version>19</version>\r
+ <state>37</state>\r
</option>\r
<option>\r
<name>GEndianMode</name>\r
</option>\r
<option>\r
<name>Input variant</name>\r
- <version>1</version>\r
- <state>0</state>\r
+ <version>3</version>\r
+ <state>1</state>\r
</option>\r
<option>\r
<name>Input description</name>\r
</option>\r
<option>\r
<name>Output variant</name>\r
- <version>0</version>\r
- <state>0</state>\r
+ <version>2</version>\r
+ <state>1</state>\r
</option>\r
<option>\r
<name>Output description</name>\r
</option>\r
<option>\r
<name>FPU</name>\r
- <version>0</version>\r
+ <version>2</version>\r
<state>0</state>\r
</option>\r
<option>\r
<name>RTDescription</name>\r
<state>Use the full configuration of the C/C++ runtime library. Full locale interface, C locale, file descriptor support, multibytes in printf and scanf, and hex floats in strtod.</state>\r
</option>\r
- <option>\r
- <name>RTConfigPath</name>\r
- <state>$TOOLKIT_DIR$\INC\DLib_Config_Full.h</state>\r
- </option>\r
<option>\r
<name>OGProductVersion</name>\r
<state>4.40A</state>\r
<name>OGLastSavedByProductVersion</name>\r
<state>5.11.0.50615</state>\r
</option>\r
- <option>\r
- <name>GeneralMisraRules</name>\r
- <version>0</version>\r
- <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>\r
- </option>\r
<option>\r
<name>GeneralEnableMisra</name>\r
<state>0</state>\r
<name>OGBufferedTerminalOutput</name>\r
<state>0</state>\r
</option>\r
+ <option>\r
+ <name>GenStdoutInterface</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>GeneralMisraRules98</name>\r
+ <version>0</version>\r
+ <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>\r
+ </option>\r
+ <option>\r
+ <name>GeneralMisraVer</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>GeneralMisraRules04</name>\r
+ <version>0</version>\r
+ <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>\r
+ </option>\r
+ <option>\r
+ <name>RTConfigPath2</name>\r
+ <state>$TOOLKIT_DIR$\INC\c\DLib_Config_Full.h</state>\r
+ </option>\r
+ <option>\r
+ <name>GFPUCoreSlave</name>\r
+ <version>19</version>\r
+ <state>37</state>\r
+ </option>\r
+ <option>\r
+ <name>GBECoreSlave</name>\r
+ <version>19</version>\r
+ <state>37</state>\r
+ </option>\r
+ <option>\r
+ <name>OGUseCmsis</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OGUseCmsisDspLib</name>\r
+ <state>0</state>\r
+ </option>\r
</data>\r
</settings>\r
<settings>\r
<name>ICCARM</name>\r
<archiveVersion>2</archiveVersion>\r
<data>\r
- <version>19</version>\r
+ <version>28</version>\r
<wantNonLocal>1</wantNonLocal>\r
<debug>1</debug>\r
<option>\r
<name>OutputFile</name>\r
<state>$FILE_BNAME$.o</state>\r
</option>\r
- <option>\r
- <name>CCLangSelect</name>\r
- <state>0</state>\r
- </option>\r
<option>\r
<name>CCLibConfigHeader</name>\r
<state>1</state>\r
<name>PreInclude</name>\r
<state></state>\r
</option>\r
- <option>\r
- <name>CompilerMisraRules</name>\r
- <version>0</version>\r
- <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>\r
- </option>\r
<option>\r
<name>CompilerMisraOverride</name>\r
<state>0</state>\r
<name>CCStdIncCheck</name>\r
<state>0</state>\r
</option>\r
- <option>\r
- <name>CCStdIncludePath</name>\r
- <state>$TOOLKIT_DIR$\INC\</state>\r
- </option>\r
<option>\r
<name>CCCodeSection</name>\r
<state>.text</state>\r
<name>CCOptLevelSlave</name>\r
<state>1</state>\r
</option>\r
+ <option>\r
+ <name>CompilerMisraRules98</name>\r
+ <version>0</version>\r
+ <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>\r
+ </option>\r
+ <option>\r
+ <name>CompilerMisraRules04</name>\r
+ <version>0</version>\r
+ <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPosIndRopi</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPosIndRwpi</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPosIndNoDynInit</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IccLang</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IccCDialect</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IccAllowVLA</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IccCppDialect</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IccExceptions</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IccRTTI</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IccStaticDestr</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IccCppInlineSemantics</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IccCmsis</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IccFloatSemantics</name>\r
+ <state>0</state>\r
+ </option>\r
</data>\r
</settings>\r
<settings>\r
<name>AARM</name>\r
<archiveVersion>2</archiveVersion>\r
<data>\r
- <version>7</version>\r
+ <version>8</version>\r
<wantNonLocal>1</wantNonLocal>\r
<debug>1</debug>\r
<option>\r
<name>AIgnoreStdInclude</name>\r
<state>0</state>\r
</option>\r
- <option>\r
- <name>AStdIncludes</name>\r
- <state>$TOOLKIT_DIR$\INC\</state>\r
- </option>\r
<option>\r
<name>AUserIncludes</name>\r
<state>$PROJ_DIR$\.</state>\r
<debug>1</debug>\r
<option>\r
<name>OOCOutputFormat</name>\r
- <version>1</version>\r
+ <version>2</version>\r
<state>0</state>\r
</option>\r
<option>\r
<name>ILINK</name>\r
<archiveVersion>0</archiveVersion>\r
<data>\r
- <version>5</version>\r
+ <version>13</version>\r
<wantNonLocal>1</wantNonLocal>\r
<debug>1</debug>\r
<option>\r
<name>IlinkProgramEntryLabel</name>\r
<state>__iar_program_start</state>\r
</option>\r
- <option>\r
- <name>IlinkNXPLPCChecksum</name>\r
- <state>0</state>\r
- </option>\r
<option>\r
<name>DoFill</name>\r
<state>0</state>\r
<name>IlinkBufferedTerminalOutput</name>\r
<state>1</state>\r
</option>\r
+ <option>\r
+ <name>IlinkStdoutInterfaceSlave</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CrcFullSize</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkIElfToolPostProcess</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkLogAutoLibSelect</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkLogRedirSymbols</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkLogUnusedFragments</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkCrcReverseByteOrder</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkCrcUseAsInput</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkOptInline</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkOptExceptionsAllow</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkOptExceptionsForce</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkCmsis</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkOptMergeDuplSections</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkOptUseVfe</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkOptForceVfe</name>\r
+ <state>0</state>\r
+ </option>\r
</data>\r
</settings>\r
<settings>\r
<name>C-SPY</name>\r
<archiveVersion>2</archiveVersion>\r
<data>\r
- <version>18</version>\r
+ <version>22</version>\r
<wantNonLocal>1</wantNonLocal>\r
<debug>1</debug>\r
<option>\r
</option>\r
<option>\r
<name>MemFile</name>\r
- <state>$TOOLKIT_DIR$\CONFIG\debugger\Luminary\iolm3sxxxx.ddf</state>\r
+ <state>$TOOLKIT_DIR$\CONFIG\debugger\TexasInstruments\iolm3sxxxx.ddf</state>\r
</option>\r
<option>\r
<name>RunToEnable</name>\r
</option>\r
<option>\r
<name>OCLastSavedByProductVersion</name>\r
- <state>5.30.0.51236</state>\r
+ <state>6.20.1.52589</state>\r
</option>\r
<option>\r
<name>OCDownloadAttachToProgram</name>\r
<state>1</state>\r
</option>\r
<option>\r
- <name>FlashLoadersV2</name>\r
- <state>,,,,(default),</state>\r
+ <name>FlashLoadersV3</name>\r
+ <state>$TOOLKIT_DIR$\config\flashloader\TexasInstruments\FlashLM3Sx8xx.board</state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesSuppressCheck1</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesPath1</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesSuppressCheck2</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesPath2</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesSuppressCheck3</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesPath3</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OverrideDefFlashBoard</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesOffset1</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesOffset2</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesOffset3</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesUse1</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesUse2</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesUse3</name>\r
+ <state>0</state>\r
</option>\r
</data>\r
</settings>\r
<name>IARROM_ID</name>\r
<archiveVersion>2</archiveVersion>\r
<data>\r
- <version>0</version>\r
+ <version>1</version>\r
<wantNonLocal>1</wantNonLocal>\r
<debug>1</debug>\r
<option>\r
<name>CRomLogFileEditB</name>\r
<state>$TOOLKIT_DIR$\cspycomm.log</state>\r
</option>\r
- <option>\r
- <name>CRomCommunication</name>\r
- <state>0</state>\r
- </option>\r
<option>\r
<name>CRomCommPort</name>\r
<version>0</version>\r
<name>JLINK_ID</name>\r
<archiveVersion>2</archiveVersion>\r
<data>\r
- <version>10</version>\r
+ <version>13</version>\r
<wantNonLocal>1</wantNonLocal>\r
<debug>1</debug>\r
<option>\r
</option>\r
<option>\r
<name>CCUSBDevice</name>\r
- <version>0</version>\r
- <state>0</state>\r
+ <version>1</version>\r
+ <state>1</state>\r
</option>\r
<option>\r
<name>CCRDICatchReset</name>\r
</option>\r
<option>\r
<name>CCJLinkResetList</name>\r
- <version>0</version>\r
+ <version>5</version>\r
<state>5</state>\r
</option>\r
<option>\r
<name>CCJLinkInterfaceCmdLine</name>\r
<state>0</state>\r
</option>\r
+ <option>\r
+ <name>CCCatchCORERESET</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCatchMMERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCatchNOCPERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCatchCHRERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCatchSTATERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCatchBUSERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCatchINTERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCatchHARDERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCatchDummy</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCJLinkScriptFile</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkUsbSerialNo</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCTcpIpAlt</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkTcpIpSerialNo</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCCpuClockEdit</name>\r
+ <state>72.0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSwoClockAuto</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSwoClockEdit</name>\r
+ <state>2000</state>\r
+ </option>\r
</data>\r
</settings>\r
<settings>\r
<name>LMIFTDI_ID</name>\r
<archiveVersion>2</archiveVersion>\r
<data>\r
- <version>1</version>\r
+ <version>2</version>\r
<wantNonLocal>1</wantNonLocal>\r
<debug>1</debug>\r
<option>\r
<name>CCLmiftdiLogFile</name>\r
<state>$TOOLKIT_DIR$\cspycomm.log</state>\r
</option>\r
+ <option>\r
+ <name>CCLmiFtdiInterfaceRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCLmiFtdiInterfaceCmdLine</name>\r
+ <state>0</state>\r
+ </option>\r
</data>\r
</settings>\r
<settings>\r
</option>\r
</data>\r
</settings>\r
+ <settings>\r
+ <name>PEMICRO_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>0</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OCPEMicroAttachSlave</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPEMicroInterfaceList</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPEMicroResetDelay</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCPEMicroJtagSpeed</name>\r
+ <state>#UNINITIALIZED#</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJPEMicroShowSettings</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>DoLogfile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>LogFile</name>\r
+ <state>$PROJ_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPEMicroUSBDevice</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPEMicroSerialPort</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJPEMicroTCPIPAutoScanNetwork</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPEMicroTCPIP</name>\r
+ <state>10.0.0.1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPEMicroCommCmdLineProducer</name>\r
+ <state>0</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
<settings>\r
<name>RDI_ID</name>\r
<archiveVersion>2</archiveVersion>\r
<data>\r
- <version>1</version>\r
+ <version>2</version>\r
<wantNonLocal>1</wantNonLocal>\r
<debug>1</debug>\r
<option>\r
<name>CCRDICatchFIQ</name>\r
<state>0</state>\r
</option>\r
- <option>\r
- <name>CCRDIUseETM</name>\r
- <state>0</state>\r
- </option>\r
<option>\r
<name>OCDriverInfo</name>\r
<state>1</state>\r
<name>STLINK_ID</name>\r
<archiveVersion>2</archiveVersion>\r
<data>\r
- <version>0</version>\r
+ <version>2</version>\r
<wantNonLocal>1</wantNonLocal>\r
<debug>1</debug>\r
<option>\r
<name>OCDriverInfo</name>\r
<state>1</state>\r
</option>\r
+ <option>\r
+ <name>CCSTLinkInterfaceRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSTLinkInterfaceCmdLine</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSTLinkResetList</name>\r
+ <version>1</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCpuClockEdit</name>\r
+ <state>72.0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSwoClockAuto</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSwoClockEdit</name>\r
+ <state>2000</state>\r
+ </option>\r
</data>\r
</settings>\r
<settings>\r
<loadFlag>0</loadFlag>\r
</plugin>\r
<plugin>\r
- <file>$TOOLKIT_DIR$\plugins\rtos\OSE\OseEpsilonPlugin.ewplugin</file>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file>\r
<loadFlag>0</loadFlag>\r
</plugin>\r
<plugin>\r
<file>$TOOLKIT_DIR$\plugins\rtos\PowerPac\PowerPacRTOS.ewplugin</file>\r
<loadFlag>0</loadFlag>\r
</plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB6_Plugin.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
<plugin>\r
<file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file>\r
<loadFlag>0</loadFlag>\r
</plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
<plugin>\r
<file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>\r
<loadFlag>0</loadFlag>\r
<loadFlag>1</loadFlag>\r
</plugin>\r
<plugin>\r
- <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>\r
+ <file>$EW_DIR$\common\plugins\FreeRTOS\FreeRTOSPlugin.ewplugin</file>\r
<loadFlag>0</loadFlag>\r
</plugin>\r
<plugin>\r
- <file>$EW_DIR$\common\plugins\Profiling\Profiling.ENU.ewplugin</file>\r
- <loadFlag>1</loadFlag>\r
+ <file>$EW_DIR$\common\plugins\OpenRTOS\OpenRTOSPlugin.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
</plugin>\r
<plugin>\r
<file>$EW_DIR$\common\plugins\Stack\Stack.ENU.ewplugin</file>\r
<?xml version="1.0" encoding="iso-8859-1"?>\r
\r
<project>\r
- <fileVersion>1</fileVersion>\r
+ <fileVersion>2</fileVersion>\r
<configuration>\r
<name>Debug</name>\r
<toolchain>\r
<name>General</name>\r
<archiveVersion>3</archiveVersion>\r
<data>\r
- <version>14</version>\r
+ <version>21</version>\r
<wantNonLocal>1</wantNonLocal>\r
<debug>1</debug>\r
<option>\r
</option>\r
<option>\r
<name>Variant</name>\r
- <version>7</version>\r
- <state>31</state>\r
+ <version>19</version>\r
+ <state>37</state>\r
</option>\r
<option>\r
<name>GEndianMode</name>\r
</option>\r
<option>\r
<name>Input variant</name>\r
- <version>1</version>\r
- <state>3</state>\r
+ <version>3</version>\r
+ <state>6</state>\r
</option>\r
<option>\r
<name>Input description</name>\r
</option>\r
<option>\r
<name>Output variant</name>\r
- <version>0</version>\r
- <state>2</state>\r
+ <version>2</version>\r
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</option>\r
<option>\r
<name>Output description</name>\r
</option>\r
<option>\r
<name>FPU</name>\r
- <version>0</version>\r
+ <version>2</version>\r
<state>0</state>\r
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<option>\r
<name>RTDescription</name>\r
<state>Use the normal configuration of the C/C++ runtime library. No locale interface, C locale, no file descriptor support, no multibytes in printf and scanf, and no hex floats in strtod.</state>\r
</option>\r
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<option>\r
<name>OGLastSavedByProductVersion</name>\r
<state>5.11.0.50615</state>\r
</option>\r
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<option>\r
<name>GeneralEnableMisra</name>\r
<state>0</state>\r
<name>OGBufferedTerminalOutput</name>\r
<state>0</state>\r
</option>\r
+ <option>\r
+ <name>GenStdoutInterface</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>GeneralMisraRules98</name>\r
+ <version>0</version>\r
+ <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>\r
+ </option>\r
+ <option>\r
+ <name>GeneralMisraVer</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>GeneralMisraRules04</name>\r
+ <version>0</version>\r
+ <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>\r
+ </option>\r
+ <option>\r
+ <name>RTConfigPath2</name>\r
+ <state>$TOOLKIT_DIR$\INC\c\DLib_Config_Normal.h</state>\r
+ </option>\r
+ <option>\r
+ <name>GFPUCoreSlave</name>\r
+ <version>19</version>\r
+ <state>37</state>\r
+ </option>\r
+ <option>\r
+ <name>GBECoreSlave</name>\r
+ <version>19</version>\r
+ <state>37</state>\r
+ </option>\r
+ <option>\r
+ <name>OGUseCmsis</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OGUseCmsisDspLib</name>\r
+ <state>0</state>\r
+ </option>\r
</data>\r
</settings>\r
<settings>\r
<name>ICCARM</name>\r
<archiveVersion>2</archiveVersion>\r
<data>\r
- <version>19</version>\r
+ <version>28</version>\r
<wantNonLocal>1</wantNonLocal>\r
<debug>1</debug>\r
<option>\r
<name>OutputFile</name>\r
<state>$FILE_BNAME$.o</state>\r
</option>\r
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<option>\r
<name>CCLibConfigHeader</name>\r
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<name>PreInclude</name>\r
<state></state>\r
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- <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>\r
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<option>\r
<name>CompilerMisraOverride</name>\r
<state>0</state>\r
<name>CCStdIncCheck</name>\r
<state>0</state>\r
</option>\r
- <option>\r
- <name>CCStdIncludePath</name>\r
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<option>\r
<name>CCCodeSection</name>\r
<state>.text</state>\r
<name>CCOptLevelSlave</name>\r
<state>1</state>\r
</option>\r
+ <option>\r
+ <name>CompilerMisraRules98</name>\r
+ <version>0</version>\r
+ <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>\r
+ </option>\r
+ <option>\r
+ <name>CompilerMisraRules04</name>\r
+ <version>0</version>\r
+ <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPosIndRopi</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPosIndRwpi</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPosIndNoDynInit</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IccLang</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IccCDialect</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IccAllowVLA</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IccCppDialect</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IccExceptions</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IccRTTI</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IccStaticDestr</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IccCppInlineSemantics</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IccCmsis</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IccFloatSemantics</name>\r
+ <state>0</state>\r
+ </option>\r
</data>\r
</settings>\r
<settings>\r
<name>AARM</name>\r
<archiveVersion>2</archiveVersion>\r
<data>\r
- <version>7</version>\r
+ <version>8</version>\r
<wantNonLocal>1</wantNonLocal>\r
<debug>1</debug>\r
<option>\r
<name>AIgnoreStdInclude</name>\r
<state>0</state>\r
</option>\r
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<option>\r
<name>AUserIncludes</name>\r
<state>$PROJ_DIR$\</state>\r
<debug>1</debug>\r
<option>\r
<name>OOCOutputFormat</name>\r
- <version>1</version>\r
+ <version>2</version>\r
<state>0</state>\r
</option>\r
<option>\r
<name>ILINK</name>\r
<archiveVersion>0</archiveVersion>\r
<data>\r
- <version>5</version>\r
+ <version>13</version>\r
<wantNonLocal>1</wantNonLocal>\r
<debug>1</debug>\r
<option>\r
<name>IlinkProgramEntryLabel</name>\r
<state>__iar_program_start</state>\r
</option>\r
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- <state>0</state>\r
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<option>\r
<name>DoFill</name>\r
<state>0</state>\r
<name>IlinkBufferedTerminalOutput</name>\r
<state>1</state>\r
</option>\r
+ <option>\r
+ <name>IlinkStdoutInterfaceSlave</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CrcFullSize</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkIElfToolPostProcess</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkLogAutoLibSelect</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkLogRedirSymbols</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkLogUnusedFragments</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkCrcReverseByteOrder</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkCrcUseAsInput</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkOptInline</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkOptExceptionsAllow</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkOptExceptionsForce</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkCmsis</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkOptMergeDuplSections</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkOptUseVfe</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkOptForceVfe</name>\r
+ <state>0</state>\r
+ </option>\r
</data>\r
</settings>\r
<settings>\r
-@REM This bat file has been generated by the IAR Embeddded Workbench\r
-@REM C-SPY interactive debugger,as an aid to preparing a command\r
-@REM line for running the cspybat command line utility with the\r
-@REM appropriate settings.\r
+@REM This batch file has been generated by the IAR Embedded Workbench\r
+@REM C-SPY Debugger, as an aid to preparing a command line for running\r
+@REM the cspybat command line utility using the appropriate settings.\r
@REM\r
-@REM After making some adjustments to this file, you can launch cspybat\r
-@REM by typing the name of this file followed by the name of the debug\r
-@REM file (usually an ubrof file). Note that this file is generated\r
-@REM every time a new debug session is initialized, so you may want to\r
-@REM move or rename the file before making changes.\r
-@REM\r
-@REM Note: some command line arguments cannot be properly generated\r
-@REM by this process. Specifically, the plugin which is responsible\r
-@REM for the Terminal I/O window (and other C runtime functionality)\r
-@REM comes in a special version for cspybat, and the name of that\r
-@REM plugin dll is not known when generating this file. It resides in\r
-@REM the $TOOLKIT_DIR$\bin folder and is usually called XXXbat.dll or\r
-@REM XXXlibsupportbat.dll, where XXX is the name of the corresponding\r
-@REM tool chain. Replace the '<libsupport_plugin>' parameter\r
-@REM below with the appropriate file name. Other plugins loaded by\r
-@REM C-SPY are usually not needed by, or will not work in, cspybat\r
-@REM but they are listed at the end of this file for reference.\r
+@REM You can launch cspybat by typing the name of this batch file followed\r
+@REM by the name of the debug file (usually an ELF/DWARF or UBROF file).\r
+@REM Note that this file is generated every time a new debug session\r
+@REM is initialized, so you may want to move or rename the file before\r
+@REM making changes.\r
+@REM \r
\r
\r
-"C:\Devtools\IAR Systems\Embedded Workbench 5.0\common\bin\cspybat" "C:\Devtools\IAR Systems\Embedded Workbench 5.0\ARM\bin\armproc.dll" "C:\Devtools\IAR Systems\Embedded Workbench 5.0\ARM\bin\armlmiftdi.dll" %1 --plugin "C:\Devtools\IAR Systems\Embedded Workbench 5.0\ARM\bin\<libsupport_plugin>" --backend -B "--endian" "little" "--cpu" "Cortex-M3" "--fpu" "None" "--proc_device_desc_file" "C:\Devtools\IAR Systems\Embedded Workbench 5.0\ARM\CONFIG\debugger\Luminary\iolm3sxxxx.ddf" "--drv_verify_download" "all" "--proc_no_semihosting" "--proc_driver" "lmiftdi" "--lmiftdi_speed" "500" \r
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\r
\r
-@REM Loaded plugins:\r
-@REM armlibsupport.dll\r
-@REM C:\Devtools\IAR Systems\Embedded Workbench 5.0\common\plugins\CodeCoverage\CodeCoverage.dll\r
-@REM C:\Devtools\IAR Systems\Embedded Workbench 5.0\common\plugins\Profiling\Profiling.dll\r
-@REM C:\Devtools\IAR Systems\Embedded Workbench 5.0\common\plugins\stack\stack.dll\r
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LimitSize=0\r
ByteLimit=50\r
-[Disassemble mode]\r
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-[Breakpoints]\r
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-Count=1\r
[Log file]\r
LoggingEnabled=_ 0\r
LogFile=_ ""\r
[TermIOLog]\r
LoggingEnabled=_ 0\r
LogFile=_ ""\r
+[Stack]\r
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+WarningThreshold=90\r
+SpWarningsEnabled=1\r
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+UseTrigger=1\r
+TriggerName=main\r
+LimitSize=0\r
+ByteLimit=50\r
+[Disassemble mode]\r
+mode=1\r
+[Breakpoints]\r
+Bp0=_ "STD_CODE" "{$PROJ_DIR$\..\..\..\WorkingCopy2\Demo\Common\Minimal\IntQueue.c}.363.2@1" 1 0 0 0 "" 0 ""\r
+Count=1\r
+[Aliases]\r
+Count=0\r
+SuppressDialog=0\r
<Find-in-Files><ColumnWidth0>482</ColumnWidth0><ColumnWidth1>68</ColumnWidth1><ColumnWidth2>826</ColumnWidth2></Find-in-Files><Build><ColumnWidth0>19</ColumnWidth0><ColumnWidth1>1007</ColumnWidth1><ColumnWidth2>268</ColumnWidth2><ColumnWidth3>67</ColumnWidth3></Build><TerminalIO/><Debug-Log/></Static>\r
<Windows>\r
\r
- <Wnd0>\r
+ <Wnd2>\r
<Tabs>\r
<Tab>\r
<Identity>TabID-18883-22024</Identity>\r
<Factory>Workspace</Factory>\r
<Session>\r
\r
- <NodeDict><ExpandedNode>RTOSDemo</ExpandedNode><ExpandedNode>RTOSDemo/Demo files</ExpandedNode><ExpandedNode>RTOSDemo/Scheduler files</ExpandedNode></NodeDict></Session>\r
+ <NodeDict><ExpandedNode>RTOSDemo</ExpandedNode><ExpandedNode>RTOSDemo/Demo files</ExpandedNode></NodeDict></Session>\r
</Tab>\r
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+ <SelectedTab>0</SelectedTab></Wnd2><Wnd3><Tabs><Tab><Identity>TabID-29040-7360</Identity><TabName>Find in Files</TabName><Factory>Find-in-Files</Factory><Session/></Tab><Tab><Identity>TabID-19024-10413</Identity><TabName>Build</TabName><Factory>Build</Factory><Session/></Tab><Tab><Identity>TabID-19202-19100</Identity><TabName>Debug Log</TabName><Factory>Debug-Log</Factory><Session/></Tab></Tabs><SelectedTab>1</SelectedTab></Wnd3></Windows>\r
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\r+ <Pane><Tab><Factory>TextEditor</Factory><Filename>
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</Desktop>\r
</Workspace>\r
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<name>C-SPY</name>\r
<archiveVersion>2</archiveVersion>\r
<data>\r
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<debug>1</debug>\r
<option>\r
</option>\r
<option>\r
<name>OCLastSavedByProductVersion</name>\r
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</option>\r
<option>\r
<name>OCDownloadAttachToProgram</name>\r
<name>OverrideDefFlashBoard</name>\r
<state>0</state>\r
</option>\r
+ <option>\r
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</data>\r
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<settings>\r
<name>IARROM_ID</name>\r
<archiveVersion>2</archiveVersion>\r
<data>\r
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<wantNonLocal>1</wantNonLocal>\r
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<state>$PROJ_DIR$\cspycomm.log</state>\r
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<name>JLINK_ID</name>\r
<archiveVersion>2</archiveVersion>\r
<data>\r
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<option>\r
</option>\r
<option>\r
<name>CCUSBDevice</name>\r
- <version>0</version>\r
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+ <version>1</version>\r
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<option>\r
<name>CCRDICatchReset</name>\r
</option>\r
<option>\r
<name>CCJLinkResetList</name>\r
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<state>7</state>\r
</option>\r
<option>\r
<name>CCJLinkInterfaceCmdLine</name>\r
<state>0</state>\r
</option>\r
+ <option>\r
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+ <state>0</state>\r
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+ <name>CCCatchMMERR</name>\r
+ <state>0</state>\r
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+ <state>0</state>\r
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+ <state>0</state>\r
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+ <state>0</state>\r
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+ <state>0</state>\r
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+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCJLinkScriptFile</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkUsbSerialNo</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCTcpIpAlt</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkTcpIpSerialNo</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCCpuClockEdit</name>\r
+ <state>72.0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSwoClockAuto</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSwoClockEdit</name>\r
+ <state>2000</state>\r
+ </option>\r
</data>\r
</settings>\r
<settings>\r
</option>\r
</data>\r
</settings>\r
+ <settings>\r
+ <name>PEMICRO_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>0</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OCPEMicroAttachSlave</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPEMicroInterfaceList</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPEMicroResetDelay</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCPEMicroJtagSpeed</name>\r
+ <state>#UNINITIALIZED#</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJPEMicroShowSettings</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>DoLogfile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>LogFile</name>\r
+ <state>$PROJ_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPEMicroUSBDevice</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPEMicroSerialPort</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJPEMicroTCPIPAutoScanNetwork</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPEMicroTCPIP</name>\r
+ <state>10.0.0.1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPEMicroCommCmdLineProducer</name>\r
+ <state>0</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
<settings>\r
<name>RDI_ID</name>\r
<archiveVersion>2</archiveVersion>\r
<data>\r
- <version>1</version>\r
+ <version>2</version>\r
<wantNonLocal>1</wantNonLocal>\r
<debug>1</debug>\r
<option>\r
<name>CCRDICatchFIQ</name>\r
<state>0</state>\r
</option>\r
- <option>\r
- <name>CCRDIUseETM</name>\r
- <state>0</state>\r
- </option>\r
<option>\r
<name>OCDriverInfo</name>\r
<state>1</state>\r
<name>STLINK_ID</name>\r
<archiveVersion>2</archiveVersion>\r
<data>\r
- <version>0</version>\r
+ <version>2</version>\r
<wantNonLocal>1</wantNonLocal>\r
<debug>1</debug>\r
<option>\r
<name>OCDriverInfo</name>\r
<state>1</state>\r
</option>\r
+ <option>\r
+ <name>CCSTLinkInterfaceRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSTLinkInterfaceCmdLine</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSTLinkResetList</name>\r
+ <version>1</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCpuClockEdit</name>\r
+ <state>72.0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSwoClockAuto</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSwoClockEdit</name>\r
+ <state>2000</state>\r
+ </option>\r
</data>\r
</settings>\r
<settings>\r
<loadFlag>0</loadFlag>\r
</plugin>\r
<plugin>\r
- <file>$TOOLKIT_DIR$\plugins\rtos\OSE\OseEpsilonPlugin.ewplugin</file>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file>\r
<loadFlag>0</loadFlag>\r
</plugin>\r
<plugin>\r
<file>$TOOLKIT_DIR$\plugins\rtos\PowerPac\PowerPacRTOS.ewplugin</file>\r
<loadFlag>0</loadFlag>\r
</plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB6_Plugin.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
<plugin>\r
<file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file>\r
<loadFlag>0</loadFlag>\r
<loadFlag>0</loadFlag>\r
</plugin>\r
<plugin>\r
- <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>\r
- <loadFlag>0</loadFlag>\r
- </plugin>\r
- <plugin>\r
- <file>$EW_DIR$\common\plugins\Profiling\Profiling.ENU.ewplugin</file>\r
- <loadFlag>1</loadFlag>\r
- </plugin>\r
- <plugin>\r
- <file>$EW_DIR$\common\plugins\Stack\Stack.ENU.ewplugin</file>\r
- <loadFlag>1</loadFlag>\r
- </plugin>\r
- <plugin>\r
- <file>$EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin</file>\r
- <loadFlag>1</loadFlag>\r
- </plugin>\r
- </debuggerPlugins>\r
- </configuration>\r
- <configuration>\r
- <name>Release</name>\r
- <toolchain>\r
- <name>ARM</name>\r
- </toolchain>\r
- <debug>0</debug>\r
- <settings>\r
- <name>C-SPY</name>\r
- <archiveVersion>2</archiveVersion>\r
- <data>\r
- <version>21</version>\r
- <wantNonLocal>1</wantNonLocal>\r
- <debug>0</debug>\r
- <option>\r
- <name>CInput</name>\r
- <state>1</state>\r
- </option>\r
- <option>\r
- <name>CEndian</name>\r
- <state>1</state>\r
- </option>\r
- <option>\r
- <name>CProcessor</name>\r
- <state>1</state>\r
- </option>\r
- <option>\r
- <name>OCVariant</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>MacOverride</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>MacFile</name>\r
- <state></state>\r
- </option>\r
- <option>\r
- <name>MemOverride</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>MemFile</name>\r
- <state></state>\r
- </option>\r
- <option>\r
- <name>RunToEnable</name>\r
- <state>1</state>\r
- </option>\r
- <option>\r
- <name>RunToName</name>\r
- <state>main</state>\r
- </option>\r
- <option>\r
- <name>CExtraOptionsCheck</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CExtraOptions</name>\r
- <state></state>\r
- </option>\r
- <option>\r
- <name>CFpuProcessor</name>\r
- <state>1</state>\r
- </option>\r
- <option>\r
- <name>OCDDFArgumentProducer</name>\r
- <state></state>\r
- </option>\r
- <option>\r
- <name>OCDownloadSuppressDownload</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>OCDownloadVerifyAll</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>OCProductVersion</name>\r
- <state>5.40.0.51529</state>\r
- </option>\r
- <option>\r
- <name>OCDynDriverList</name>\r
- <state>ARMSIM_ID</state>\r
- </option>\r
- <option>\r
- <name>OCLastSavedByProductVersion</name>\r
- <state></state>\r
- </option>\r
- <option>\r
- <name>OCDownloadAttachToProgram</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>UseFlashLoader</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CLowLevel</name>\r
- <state>1</state>\r
- </option>\r
- <option>\r
- <name>OCBE8Slave</name>\r
- <state>1</state>\r
- </option>\r
- <option>\r
- <name>MacFile2</name>\r
- <state></state>\r
- </option>\r
- <option>\r
- <name>CDevice</name>\r
- <state>1</state>\r
- </option>\r
- <option>\r
- <name>FlashLoadersV3</name>\r
- <state></state>\r
- </option>\r
- <option>\r
- <name>OCImagesSuppressCheck1</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>OCImagesPath1</name>\r
- <state></state>\r
- </option>\r
- <option>\r
- <name>OCImagesSuppressCheck2</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>OCImagesPath2</name>\r
- <state></state>\r
- </option>\r
- <option>\r
- <name>OCImagesSuppressCheck3</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>OCImagesPath3</name>\r
- <state></state>\r
- </option>\r
- <option>\r
- <name>OverrideDefFlashBoard</name>\r
- <state>0</state>\r
- </option>\r
- </data>\r
- </settings>\r
- <settings>\r
- <name>ARMSIM_ID</name>\r
- <archiveVersion>2</archiveVersion>\r
- <data>\r
- <version>1</version>\r
- <wantNonLocal>1</wantNonLocal>\r
- <debug>0</debug>\r
- <option>\r
- <name>OCSimDriverInfo</name>\r
- <state>1</state>\r
- </option>\r
- <option>\r
- <name>OCSimEnablePSP</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>OCSimPspOverrideConfig</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>OCSimPspConfigFile</name>\r
- <state></state>\r
- </option>\r
- </data>\r
- </settings>\r
- <settings>\r
- <name>ANGEL_ID</name>\r
- <archiveVersion>2</archiveVersion>\r
- <data>\r
- <version>0</version>\r
- <wantNonLocal>1</wantNonLocal>\r
- <debug>0</debug>\r
- <option>\r
- <name>CCAngelHeartbeat</name>\r
- <state>1</state>\r
- </option>\r
- <option>\r
- <name>CAngelCommunication</name>\r
- <state>1</state>\r
- </option>\r
- <option>\r
- <name>CAngelCommBaud</name>\r
- <version>0</version>\r
- <state>3</state>\r
- </option>\r
- <option>\r
- <name>CAngelCommPort</name>\r
- <version>0</version>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>ANGELTCPIP</name>\r
- <state>aaa.bbb.ccc.ddd</state>\r
- </option>\r
- <option>\r
- <name>DoAngelLogfile</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>AngelLogFile</name>\r
- <state>$PROJ_DIR$\cspycomm.log</state>\r
- </option>\r
- <option>\r
- <name>OCDriverInfo</name>\r
- <state>1</state>\r
- </option>\r
- </data>\r
- </settings>\r
- <settings>\r
- <name>GDBSERVER_ID</name>\r
- <archiveVersion>2</archiveVersion>\r
- <data>\r
- <version>0</version>\r
- <wantNonLocal>1</wantNonLocal>\r
- <debug>0</debug>\r
- <option>\r
- <name>OCDriverInfo</name>\r
- <state>1</state>\r
- </option>\r
- <option>\r
- <name>TCPIP</name>\r
- <state>aaa.bbb.ccc.ddd</state>\r
- </option>\r
- <option>\r
- <name>DoLogfile</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>LogFile</name>\r
- <state>$PROJ_DIR$\cspycomm.log</state>\r
- </option>\r
- <option>\r
- <name>CCJTagBreakpointRadio</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CCJTagDoUpdateBreakpoints</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CCJTagUpdateBreakpoints</name>\r
- <state>main</state>\r
- </option>\r
- </data>\r
- </settings>\r
- <settings>\r
- <name>IARROM_ID</name>\r
- <archiveVersion>2</archiveVersion>\r
- <data>\r
- <version>0</version>\r
- <wantNonLocal>1</wantNonLocal>\r
- <debug>0</debug>\r
- <option>\r
- <name>CRomLogFileCheck</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CRomLogFileEditB</name>\r
- <state>$PROJ_DIR$\cspycomm.log</state>\r
- </option>\r
- <option>\r
- <name>CRomCommunication</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CRomCommPort</name>\r
- <version>0</version>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CRomCommBaud</name>\r
- <version>0</version>\r
- <state>7</state>\r
- </option>\r
- <option>\r
- <name>OCDriverInfo</name>\r
- <state>1</state>\r
- </option>\r
- </data>\r
- </settings>\r
- <settings>\r
- <name>JLINK_ID</name>\r
- <archiveVersion>2</archiveVersion>\r
- <data>\r
- <version>10</version>\r
- <wantNonLocal>1</wantNonLocal>\r
- <debug>0</debug>\r
- <option>\r
- <name>JLinkSpeed</name>\r
- <state>32</state>\r
- </option>\r
- <option>\r
- <name>CCJLinkDoLogfile</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CCJLinkLogFile</name>\r
- <state>$PROJ_DIR$\cspycomm.log</state>\r
- </option>\r
- <option>\r
- <name>CCJLinkHWResetDelay</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>OCDriverInfo</name>\r
- <state>1</state>\r
- </option>\r
- <option>\r
- <name>JLinkInitialSpeed</name>\r
- <state>32</state>\r
- </option>\r
- <option>\r
- <name>CCDoJlinkMultiTarget</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CCScanChainNonARMDevices</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CCJLinkMultiTarget</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CCJLinkIRLength</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CCJLinkCommRadio</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CCJLinkTCPIP</name>\r
- <state>aaa.bbb.ccc.ddd</state>\r
- </option>\r
- <option>\r
- <name>CCJLinkSpeedRadioV2</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CCUSBDevice</name>\r
- <version>0</version>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CCRDICatchReset</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CCRDICatchUndef</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CCRDICatchSWI</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CCRDICatchData</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CCRDICatchPrefetch</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CCRDICatchIRQ</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CCRDICatchFIQ</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CCJLinkBreakpointRadio</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CCJLinkDoUpdateBreakpoints</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CCJLinkUpdateBreakpoints</name>\r
- <state>main</state>\r
- </option>\r
- <option>\r
- <name>CCJLinkInterfaceRadio</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>OCJLinkAttachSlave</name>\r
- <state>1</state>\r
- </option>\r
- <option>\r
- <name>CCJLinkResetList</name>\r
- <version>0</version>\r
- <state>5</state>\r
- </option>\r
- <option>\r
- <name>CCJLinkInterfaceCmdLine</name>\r
- <state>0</state>\r
- </option>\r
- </data>\r
- </settings>\r
- <settings>\r
- <name>LMIFTDI_ID</name>\r
- <archiveVersion>2</archiveVersion>\r
- <data>\r
- <version>2</version>\r
- <wantNonLocal>1</wantNonLocal>\r
- <debug>0</debug>\r
- <option>\r
- <name>OCDriverInfo</name>\r
- <state>1</state>\r
- </option>\r
- <option>\r
- <name>LmiftdiSpeed</name>\r
- <state>500</state>\r
- </option>\r
- <option>\r
- <name>CCLmiftdiDoLogfile</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CCLmiftdiLogFile</name>\r
- <state>$PROJ_DIR$\cspycomm.log</state>\r
- </option>\r
- <option>\r
- <name>CCLmiFtdiInterfaceRadio</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CCLmiFtdiInterfaceCmdLine</name>\r
- <state>0</state>\r
- </option>\r
- </data>\r
- </settings>\r
- <settings>\r
- <name>MACRAIGOR_ID</name>\r
- <archiveVersion>2</archiveVersion>\r
- <data>\r
- <version>3</version>\r
- <wantNonLocal>1</wantNonLocal>\r
- <debug>0</debug>\r
- <option>\r
- <name>jtag</name>\r
- <version>0</version>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>EmuSpeed</name>\r
- <state>1</state>\r
- </option>\r
- <option>\r
- <name>TCPIP</name>\r
- <state>aaa.bbb.ccc.ddd</state>\r
- </option>\r
- <option>\r
- <name>DoLogfile</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>LogFile</name>\r
- <state>$PROJ_DIR$\cspycomm.log</state>\r
- </option>\r
- <option>\r
- <name>DoEmuMultiTarget</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>EmuMultiTarget</name>\r
- <state>0@ARM7TDMI</state>\r
- </option>\r
- <option>\r
- <name>EmuHWReset</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CEmuCommBaud</name>\r
- <version>0</version>\r
- <state>4</state>\r
- </option>\r
- <option>\r
- <name>CEmuCommPort</name>\r
- <version>0</version>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>jtago</name>\r
- <version>0</version>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>OCDriverInfo</name>\r
- <state>1</state>\r
- </option>\r
- <option>\r
- <name>UnusedAddr</name>\r
- <state>0x00800000</state>\r
- </option>\r
- <option>\r
- <name>CCMacraigorHWResetDelay</name>\r
- <state></state>\r
- </option>\r
- <option>\r
- <name>CCJTagBreakpointRadio</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CCJTagDoUpdateBreakpoints</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CCJTagUpdateBreakpoints</name>\r
- <state>main</state>\r
- </option>\r
- <option>\r
- <name>CCMacraigorInterfaceRadio</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CCMacraigorInterfaceCmdLine</name>\r
- <state>0</state>\r
- </option>\r
- </data>\r
- </settings>\r
- <settings>\r
- <name>RDI_ID</name>\r
- <archiveVersion>2</archiveVersion>\r
- <data>\r
- <version>1</version>\r
- <wantNonLocal>1</wantNonLocal>\r
- <debug>0</debug>\r
- <option>\r
- <name>CRDIDriverDll</name>\r
- <state>###Uninitialized###</state>\r
- </option>\r
- <option>\r
- <name>CRDILogFileCheck</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CRDILogFileEdit</name>\r
- <state>$PROJ_DIR$\cspycomm.log</state>\r
- </option>\r
- <option>\r
- <name>CCRDIHWReset</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CCRDICatchReset</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CCRDICatchUndef</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CCRDICatchSWI</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CCRDICatchData</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CCRDICatchPrefetch</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CCRDICatchIRQ</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CCRDICatchFIQ</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CCRDIUseETM</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>OCDriverInfo</name>\r
- <state>1</state>\r
- </option>\r
- </data>\r
- </settings>\r
- <settings>\r
- <name>STLINK_ID</name>\r
- <archiveVersion>2</archiveVersion>\r
- <data>\r
- <version>0</version>\r
- <wantNonLocal>1</wantNonLocal>\r
- <debug>0</debug>\r
- <option>\r
- <name>OCDriverInfo</name>\r
- <state>1</state>\r
- </option>\r
- </data>\r
- </settings>\r
- <settings>\r
- <name>THIRDPARTY_ID</name>\r
- <archiveVersion>2</archiveVersion>\r
- <data>\r
- <version>0</version>\r
- <wantNonLocal>1</wantNonLocal>\r
- <debug>0</debug>\r
- <option>\r
- <name>CThirdPartyDriverDll</name>\r
- <state>###Uninitialized###</state>\r
- </option>\r
- <option>\r
- <name>CThirdPartyLogFileCheck</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CThirdPartyLogFileEditB</name>\r
- <state>$PROJ_DIR$\cspycomm.log</state>\r
- </option>\r
- <option>\r
- <name>OCDriverInfo</name>\r
- <state>1</state>\r
- </option>\r
- </data>\r
- </settings>\r
- <debuggerPlugins>\r
- <plugin>\r
- <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file>\r
- <loadFlag>0</loadFlag>\r
- </plugin>\r
- <plugin>\r
- <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file>\r
- <loadFlag>0</loadFlag>\r
- </plugin>\r
- <plugin>\r
- <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>\r
- <loadFlag>0</loadFlag>\r
- </plugin>\r
- <plugin>\r
- <file>$TOOLKIT_DIR$\plugins\rtos\OSE\OseEpsilonPlugin.ewplugin</file>\r
- <loadFlag>0</loadFlag>\r
- </plugin>\r
- <plugin>\r
- <file>$TOOLKIT_DIR$\plugins\rtos\PowerPac\PowerPacRTOS.ewplugin</file>\r
- <loadFlag>0</loadFlag>\r
- </plugin>\r
- <plugin>\r
- <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file>\r
- <loadFlag>0</loadFlag>\r
- </plugin>\r
- <plugin>\r
- <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file>\r
- <loadFlag>0</loadFlag>\r
- </plugin>\r
- <plugin>\r
- <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>\r
- <loadFlag>0</loadFlag>\r
- </plugin>\r
- <plugin>\r
- <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin</file>\r
- <loadFlag>1</loadFlag>\r
- </plugin>\r
- <plugin>\r
- <file>$EW_DIR$\common\plugins\FreeRTOS\FreeRTOSPlugin.ewplugin</file>\r
+ <file>$EW_DIR$\common\plugins\OpenRTOS\OpenRTOSPlugin.ewplugin</file>\r
<loadFlag>0</loadFlag>\r
</plugin>\r
<plugin>\r
<file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>\r
<loadFlag>0</loadFlag>\r
</plugin>\r
- <plugin>\r
- <file>$EW_DIR$\common\plugins\Profiling\Profiling.ENU.ewplugin</file>\r
- <loadFlag>1</loadFlag>\r
- </plugin>\r
<plugin>\r
<file>$EW_DIR$\common\plugins\Stack\Stack.ENU.ewplugin</file>\r
<loadFlag>1</loadFlag>\r
<name>General</name>\r
<archiveVersion>3</archiveVersion>\r
<data>\r
- <version>17</version>\r
+ <version>21</version>\r
<wantNonLocal>1</wantNonLocal>\r
<debug>1</debug>\r
<option>\r
</option>\r
<option>\r
<name>Variant</name>\r
- <version>11</version>\r
- <state>35</state>\r
+ <version>19</version>\r
+ <state>37</state>\r
</option>\r
<option>\r
<name>GEndianMode</name>\r
</option>\r
<option>\r
<name>Input variant</name>\r
- <version>1</version>\r
- <state>3</state>\r
+ <version>3</version>\r
+ <state>6</state>\r
</option>\r
<option>\r
<name>Input description</name>\r
</option>\r
<option>\r
<name>Output variant</name>\r
- <version>0</version>\r
- <state>3</state>\r
+ <version>2</version>\r
+ <state>7</state>\r
</option>\r
<option>\r
<name>Output description</name>\r
</option>\r
<option>\r
<name>FPU</name>\r
- <version>0</version>\r
+ <version>2</version>\r
<state>0</state>\r
</option>\r
<option>\r
<name>RTDescription</name>\r
<state>Use the normal configuration of the C/C++ runtime library. No locale interface, C locale, no file descriptor support, no multibytes in printf and scanf, and no hex floats in strtod.</state>\r
</option>\r
- <option>\r
- <name>RTConfigPath</name>\r
- <state>$TOOLKIT_DIR$\INC\DLib_Config_Normal.h</state>\r
- </option>\r
<option>\r
<name>OGProductVersion</name>\r
<state>5.10.0.159</state>\r
</option>\r
<option>\r
<name>OGLastSavedByProductVersion</name>\r
- <state>5.40.0.51529</state>\r
+ <state>6.20.1.52589</state>\r
</option>\r
<option>\r
<name>GeneralEnableMisra</name>\r
<version>0</version>\r
<state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>\r
</option>\r
+ <option>\r
+ <name>RTConfigPath2</name>\r
+ <state>$TOOLKIT_DIR$\INC\c\DLib_Config_Normal.h</state>\r
+ </option>\r
+ <option>\r
+ <name>GFPUCoreSlave</name>\r
+ <version>19</version>\r
+ <state>37</state>\r
+ </option>\r
+ <option>\r
+ <name>GBECoreSlave</name>\r
+ <version>19</version>\r
+ <state>37</state>\r
+ </option>\r
+ <option>\r
+ <name>OGUseCmsis</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OGUseCmsisDspLib</name>\r
+ <state>0</state>\r
+ </option>\r
</data>\r
</settings>\r
<settings>\r
<name>ICCARM</name>\r
<archiveVersion>2</archiveVersion>\r
<data>\r
- <version>21</version>\r
+ <version>28</version>\r
<wantNonLocal>1</wantNonLocal>\r
<debug>1</debug>\r
<option>\r
<name>OutputFile</name>\r
<state>$FILE_BNAME$.o</state>\r
</option>\r
- <option>\r
- <name>CCLangSelect</name>\r
- <state>0</state>\r
- </option>\r
<option>\r
<name>CCLibConfigHeader</name>\r
<state>1</state>\r
<name>CCStdIncCheck</name>\r
<state>0</state>\r
</option>\r
- <option>\r
- <name>CCStdIncludePath</name>\r
- <state>$TOOLKIT_DIR$\INC\</state>\r
- </option>\r
<option>\r
<name>CCCodeSection</name>\r
<state>.text</state>\r
<version>0</version>\r
<state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>\r
</option>\r
+ <option>\r
+ <name>CCPosIndRopi</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPosIndRwpi</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPosIndNoDynInit</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IccLang</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IccCDialect</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IccAllowVLA</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IccCppDialect</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IccExceptions</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IccRTTI</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IccStaticDestr</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IccCppInlineSemantics</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IccCmsis</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IccFloatSemantics</name>\r
+ <state>0</state>\r
+ </option>\r
</data>\r
</settings>\r
<settings>\r
<name>AARM</name>\r
<archiveVersion>2</archiveVersion>\r
<data>\r
- <version>7</version>\r
+ <version>8</version>\r
<wantNonLocal>1</wantNonLocal>\r
<debug>1</debug>\r
<option>\r
<name>AIgnoreStdInclude</name>\r
<state>0</state>\r
</option>\r
- <option>\r
- <name>AStdIncludes</name>\r
- <state>$TOOLKIT_DIR$\INC\</state>\r
- </option>\r
<option>\r
<name>AUserIncludes</name>\r
<state>$PROJ_DIR$</state>\r
<name>ILINK</name>\r
<archiveVersion>0</archiveVersion>\r
<data>\r
- <version>8</version>\r
+ <version>13</version>\r
<wantNonLocal>1</wantNonLocal>\r
<debug>1</debug>\r
<option>\r
<name>IlinkIElfToolPostProcess</name>\r
<state>0</state>\r
</option>\r
- </data>\r
- </settings>\r
- <settings>\r
- <name>IARCHIVE</name>\r
- <archiveVersion>0</archiveVersion>\r
- <data>\r
- <version>0</version>\r
- <wantNonLocal>1</wantNonLocal>\r
- <debug>1</debug>\r
- <option>\r
- <name>IarchiveInputs</name>\r
- <state></state>\r
- </option>\r
- <option>\r
- <name>IarchiveOverride</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>IarchiveOutput</name>\r
- <state>###Unitialized###</state>\r
- </option>\r
- </data>\r
- </settings>\r
- <settings>\r
- <name>BILINK</name>\r
- <archiveVersion>0</archiveVersion>\r
- <data/>\r
- </settings>\r
- </configuration>\r
- <configuration>\r
- <name>Release</name>\r
- <toolchain>\r
- <name>ARM</name>\r
- </toolchain>\r
- <debug>0</debug>\r
- <settings>\r
- <name>General</name>\r
- <archiveVersion>3</archiveVersion>\r
- <data>\r
- <version>17</version>\r
- <wantNonLocal>1</wantNonLocal>\r
- <debug>0</debug>\r
- <option>\r
- <name>ExePath</name>\r
- <state>Release\Exe</state>\r
- </option>\r
- <option>\r
- <name>ObjPath</name>\r
- <state>Release\Obj</state>\r
- </option>\r
- <option>\r
- <name>ListPath</name>\r
- <state>Release\List</state>\r
- </option>\r
- <option>\r
- <name>Variant</name>\r
- <version>11</version>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>GEndianMode</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>Input variant</name>\r
- <version>1</version>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>Input description</name>\r
- <state>Full formatting.</state>\r
- </option>\r
<option>\r
- <name>Output variant</name>\r
- <version>0</version>\r
+ <name>IlinkLogAutoLibSelect</name>\r
<state>0</state>\r
</option>\r
<option>\r
- <name>Output description</name>\r
- <state>Full formatting.</state>\r
- </option>\r
- <option>\r
- <name>GOutputBinary</name>\r
+ <name>IlinkLogRedirSymbols</name>\r
<state>0</state>\r
</option>\r
<option>\r
- <name>FPU</name>\r
- <version>0</version>\r
+ <name>IlinkLogUnusedFragments</name>\r
<state>0</state>\r
</option>\r
<option>\r
- <name>OGCoreOrChip</name>\r
+ <name>IlinkCrcReverseByteOrder</name>\r
<state>0</state>\r
</option>\r
<option>\r
- <name>GRuntimeLibSelect</name>\r
- <version>0</version>\r
- <state>1</state>\r
- </option>\r
- <option>\r
- <name>GRuntimeLibSelectSlave</name>\r
- <version>0</version>\r
+ <name>IlinkCrcUseAsInput</name>\r
<state>1</state>\r
</option>\r
<option>\r
- <name>RTDescription</name>\r
- <state>Use the normal configuration of the C/C++ runtime library. No locale interface, C locale, no file descriptor support, no multibytes in printf and scanf, and no hex floats in strtod.</state>\r
- </option>\r
- <option>\r
- <name>RTConfigPath</name>\r
- <state>$TOOLKIT_DIR$\INC\DLib_Config_Normal.h</state>\r
- </option>\r
- <option>\r
- <name>OGProductVersion</name>\r
- <state>5.10.0.159</state>\r
- </option>\r
- <option>\r
- <name>OGLastSavedByProductVersion</name>\r
- <state>5.10.0.159</state>\r
- </option>\r
- <option>\r
- <name>GeneralEnableMisra</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>GeneralMisraVerbose</name>\r
+ <name>IlinkOptInline</name>\r
<state>0</state>\r
</option>\r
<option>\r
- <name>OGChipSelectEditMenu</name>\r
- <state>default None</state>\r
- </option>\r
- <option>\r
- <name>GenLowLevelInterface</name>\r
- <state>0</state>\r
+ <name>IlinkOptExceptionsAllow</name>\r
+ <state>1</state>\r
</option>\r
<option>\r
- <name>GEndianModeBE</name>\r
+ <name>IlinkOptExceptionsForce</name>\r
<state>0</state>\r
</option>\r
<option>\r
- <name>OGBufferedTerminalOutput</name>\r
- <state>0</state>\r
+ <name>IlinkCmsis</name>\r
+ <state>1</state>\r
</option>\r
<option>\r
- <name>GenStdoutInterface</name>\r
+ <name>IlinkOptMergeDuplSections</name>\r
<state>0</state>\r
</option>\r
<option>\r
- <name>GeneralMisraRules98</name>\r
- <version>0</version>\r
- <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>\r
+ <name>IlinkOptUseVfe</name>\r
+ <state>1</state>\r
</option>\r
<option>\r
- <name>GeneralMisraVer</name>\r
+ <name>IlinkOptForceVfe</name>\r
<state>0</state>\r
</option>\r
- <option>\r
- <name>GeneralMisraRules04</name>\r
- <version>0</version>\r
- <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>\r
- </option>\r
</data>\r
</settings>\r
<settings>\r
- <name>ICCARM</name>\r
- <archiveVersion>2</archiveVersion>\r
+ <name>IARCHIVE</name>\r
+ <archiveVersion>0</archiveVersion>\r
<data>\r
- <version>21</version>\r
+ <version>0</version>\r
<wantNonLocal>1</wantNonLocal>\r
- <debug>0</debug>\r
- <option>\r
- <name>CCDefines</name>\r
- <state>NDEBUG</state>\r
- </option>\r
- <option>\r
- <name>CCPreprocFile</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CCPreprocComments</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CCPreprocLine</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CCListCFile</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CCListCMnemonics</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CCListCMessages</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CCListAssFile</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CCListAssSource</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CCEnableRemarks</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CCDiagSuppress</name>\r
- <state></state>\r
- </option>\r
- <option>\r
- <name>CCDiagRemark</name>\r
- <state></state>\r
- </option>\r
- <option>\r
- <name>CCDiagWarning</name>\r
- <state></state>\r
- </option>\r
- <option>\r
- <name>CCDiagError</name>\r
- <state></state>\r
- </option>\r
- <option>\r
- <name>CCObjPrefix</name>\r
- <state>1</state>\r
- </option>\r
- <option>\r
- <name>CCAllowList</name>\r
- <version>1</version>\r
- <state>1111111</state>\r
- </option>\r
- <option>\r
- <name>CCDebugInfo</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>IEndianMode</name>\r
- <state>1</state>\r
- </option>\r
- <option>\r
- <name>IProcessor</name>\r
- <state>1</state>\r
- </option>\r
- <option>\r
- <name>IExtraOptionsCheck</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>IExtraOptions</name>\r
- <state></state>\r
- </option>\r
- <option>\r
- <name>CCLangConformance</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CCSignedPlainChar</name>\r
- <state>1</state>\r
- </option>\r
- <option>\r
- <name>CCRequirePrototypes</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CCMultibyteSupport</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CCDiagWarnAreErr</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CCCompilerRuntimeInfo</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>IFpuProcessor</name>\r
- <state>1</state>\r
- </option>\r
- <option>\r
- <name>OutputFile</name>\r
- <state>$FILE_BNAME$.o</state>\r
- </option>\r
- <option>\r
- <name>CCLangSelect</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CCLibConfigHeader</name>\r
- <state>1</state>\r
- </option>\r
- <option>\r
- <name>PreInclude</name>\r
- <state></state>\r
- </option>\r
- <option>\r
- <name>CompilerMisraOverride</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CCIncludePath2</name>\r
- <state></state>\r
- </option>\r
- <option>\r
- <name>CCStdIncCheck</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CCStdIncludePath</name>\r
- <state>$TOOLKIT_DIR$\INC\</state>\r
- </option>\r
- <option>\r
- <name>CCCodeSection</name>\r
- <state>.text</state>\r
- </option>\r
- <option>\r
- <name>IInterwork2</name>\r
- <state>1</state>\r
- </option>\r
- <option>\r
- <name>IProcessorMode2</name>\r
- <state>1</state>\r
- </option>\r
- <option>\r
- <name>CCOptLevel</name>\r
- <state>3</state>\r
- </option>\r
- <option>\r
- <name>CCOptStrategy</name>\r
- <version>0</version>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CCOptLevelSlave</name>\r
- <state>3</state>\r
- </option>\r
- <option>\r
- <name>CompilerMisraRules98</name>\r
- <version>0</version>\r
- <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>\r
- </option>\r
- <option>\r
- <name>CompilerMisraRules04</name>\r
- <version>0</version>\r
- <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>\r
- </option>\r
- </data>\r
- </settings>\r
- <settings>\r
- <name>AARM</name>\r
- <archiveVersion>2</archiveVersion>\r
- <data>\r
- <version>7</version>\r
- <wantNonLocal>1</wantNonLocal>\r
- <debug>0</debug>\r
- <option>\r
- <name>AObjPrefix</name>\r
- <state>1</state>\r
- </option>\r
- <option>\r
- <name>AEndian</name>\r
- <state>1</state>\r
- </option>\r
- <option>\r
- <name>ACaseSensitivity</name>\r
- <state>1</state>\r
- </option>\r
- <option>\r
- <name>MacroChars</name>\r
- <version>0</version>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>AWarnEnable</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>AWarnWhat</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>AWarnOne</name>\r
- <state></state>\r
- </option>\r
- <option>\r
- <name>AWarnRange1</name>\r
- <state></state>\r
- </option>\r
- <option>\r
- <name>AWarnRange2</name>\r
- <state></state>\r
- </option>\r
- <option>\r
- <name>ADebug</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>AltRegisterNames</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>ADefines</name>\r
- <state></state>\r
- </option>\r
- <option>\r
- <name>AList</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>AListHeader</name>\r
- <state>1</state>\r
- </option>\r
- <option>\r
- <name>AListing</name>\r
- <state>1</state>\r
- </option>\r
- <option>\r
- <name>Includes</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>MacDefs</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>MacExps</name>\r
- <state>1</state>\r
- </option>\r
- <option>\r
- <name>MacExec</name>\r
- <state>0</state>\r
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+++ /dev/null
-/******************************************************************************\r
- * @file: core_cm3.h\r
- * @purpose: CMSIS Cortex-M3 Core Peripheral Access Layer Header File\r
- * @version: V1.20\r
- * @date: 22. May 2009\r
- *----------------------------------------------------------------------------\r
- *\r
- * Copyright (C) 2009 ARM Limited. All rights reserved.\r
- *\r
- * ARM Limited (ARM) is supplying this software for use with Cortex-Mx \r
- * processor based microcontrollers. This file can be freely distributed \r
- * within development tools that are supporting such ARM based processors. \r
- *\r
- * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
- * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
- *\r
- ******************************************************************************/\r
-\r
-#ifndef __CM3_CORE_H__\r
-#define __CM3_CORE_H__\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif \r
-\r
-#define __CM3_CMSIS_VERSION_MAIN (0x01) /*!< [31:16] CMSIS HAL main version */\r
-#define __CM3_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */\r
-#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */\r
-\r
-#define __CORTEX_M (0x03) /*!< Cortex core */\r
-\r
-/**\r
- * Lint configuration \n\r
- * ----------------------- \n\r
- *\r
- * The following Lint messages will be suppressed and not shown: \n\r
- * \n\r
- * --- Error 10: --- \n\r
- * register uint32_t __regBasePri __asm("basepri"); \n\r
- * Error 10: Expecting ';' \n\r
- * \n\r
- * --- Error 530: --- \n\r
- * return(__regBasePri); \n\r
- * Warning 530: Symbol '__regBasePri' (line 264) not initialized \n\r
- * \n\r
- * --- Error 550: --- \n\r
- * __regBasePri = (basePri & 0x1ff); \n\r
- * } \n\r
- * Warning 550: Symbol '__regBasePri' (line 271) not accessed \n\r
- * \n\r
- * --- Error 754: --- \n\r
- * uint32_t RESERVED0[24]; \n\r
- * Info 754: local structure member '<some, not used in the HAL>' (line 109, file ./cm3_core.h) not referenced \n\r
- * \n\r
- * --- Error 750: --- \n\r
- * #define __CM3_CORE_H__ \n\r
- * Info 750: local macro '__CM3_CORE_H__' (line 43, file./cm3_core.h) not referenced \n\r
- * \n\r
- * --- Error 528: --- \n\r
- * static __INLINE void NVIC_DisableIRQ(uint32_t IRQn) \n\r
- * Warning 528: Symbol 'NVIC_DisableIRQ(unsigned int)' (line 419, file ./cm3_core.h) not referenced \n\r
- * \n\r
- * --- Error 751: --- \n\r
- * } InterruptType_Type; \n\r
- * Info 751: local typedef 'InterruptType_Type' (line 170, file ./cm3_core.h) not referenced \n\r
- * \n\r
- * \n\r
- * Note: To re-enable a Message, insert a space before 'lint' * \n\r
- *\r
- */\r
-\r
-/*lint -save */\r
-/*lint -e10 */\r
-/*lint -e530 */\r
-/*lint -e550 */\r
-/*lint -e754 */\r
-/*lint -e750 */\r
-/*lint -e528 */\r
-/*lint -e751 */\r
-\r
-\r
-#include <stdint.h> /* Include standard types */\r
-\r
-#if defined (__ICCARM__)\r
- #include <intrinsics.h> /* IAR Intrinsics */\r
-#endif\r
-\r
-\r
-#ifndef __NVIC_PRIO_BITS\r
- #define __NVIC_PRIO_BITS 4 /*!< standard definition for NVIC Priority Bits */\r
-#endif\r
-\r
-\r
-\r
-\r
-/**\r
- * IO definitions\r
- *\r
- * define access restrictions to peripheral registers\r
- */\r
-\r
-#ifdef __cplusplus\r
-#define __I volatile /*!< defines 'read only' permissions */\r
-#else\r
-#define __I volatile const /*!< defines 'read only' permissions */\r
-#endif\r
-#define __O volatile /*!< defines 'write only' permissions */\r
-#define __IO volatile /*!< defines 'read / write' permissions */\r
-\r
-\r
-\r
-/*******************************************************************************\r
- * Register Abstraction\r
- ******************************************************************************/\r
-\r
-\r
-/* System Reset */\r
-#define NVIC_VECTRESET 0 /*!< Vector Reset Bit */\r
-#define NVIC_SYSRESETREQ 2 /*!< System Reset Request */\r
-#define NVIC_AIRCR_VECTKEY (0x5FA << 16) /*!< AIRCR Key for write access */\r
-#define NVIC_AIRCR_ENDIANESS 15 /*!< Endianess */\r
-\r
-/* Core Debug */\r
-#define CoreDebug_DEMCR_TRCENA (1 << 24) /*!< DEMCR TRCENA enable */\r
-#define ITM_TCR_ITMENA 1 /*!< ITM enable */\r
-\r
-\r
-\r
-\r
-/* memory mapping struct for Nested Vectored Interrupt Controller (NVIC) */\r
-typedef struct\r
-{\r
- __IO uint32_t ISER[8]; /*!< Interrupt Set Enable Register */\r
- uint32_t RESERVED0[24];\r
- __IO uint32_t ICER[8]; /*!< Interrupt Clear Enable Register */\r
- uint32_t RSERVED1[24];\r
- __IO uint32_t ISPR[8]; /*!< Interrupt Set Pending Register */\r
- uint32_t RESERVED2[24];\r
- __IO uint32_t ICPR[8]; /*!< Interrupt Clear Pending Register */\r
- uint32_t RESERVED3[24];\r
- __IO uint32_t IABR[8]; /*!< Interrupt Active bit Register */\r
- uint32_t RESERVED4[56];\r
- __IO uint8_t IP[240]; /*!< Interrupt Priority Register, 8Bit wide */\r
- uint32_t RESERVED5[644];\r
- __O uint32_t STIR; /*!< Software Trigger Interrupt Register */\r
-} NVIC_Type;\r
-\r
-\r
-/* memory mapping struct for System Control Block */\r
-typedef struct\r
-{\r
- __I uint32_t CPUID; /*!< CPU ID Base Register */\r
- __IO uint32_t ICSR; /*!< Interrupt Control State Register */\r
- __IO uint32_t VTOR; /*!< Vector Table Offset Register */\r
- __IO uint32_t AIRCR; /*!< Application Interrupt / Reset Control Register */\r
- __IO uint32_t SCR; /*!< System Control Register */\r
- __IO uint32_t CCR; /*!< Configuration Control Register */\r
- __IO uint8_t SHP[12]; /*!< System Handlers Priority Registers (4-7, 8-11, 12-15) */\r
- __IO uint32_t SHCSR; /*!< System Handler Control and State Register */\r
- __IO uint32_t CFSR; /*!< Configurable Fault Status Register */\r
- __IO uint32_t HFSR; /*!< Hard Fault Status Register */\r
- __IO uint32_t DFSR; /*!< Debug Fault Status Register */\r
- __IO uint32_t MMFAR; /*!< Mem Manage Address Register */\r
- __IO uint32_t BFAR; /*!< Bus Fault Address Register */\r
- __IO uint32_t AFSR; /*!< Auxiliary Fault Status Register */\r
- __I uint32_t PFR[2]; /*!< Processor Feature Register */\r
- __I uint32_t DFR; /*!< Debug Feature Register */\r
- __I uint32_t ADR; /*!< Auxiliary Feature Register */\r
- __I uint32_t MMFR[4]; /*!< Memory Model Feature Register */\r
- __I uint32_t ISAR[5]; /*!< ISA Feature Register */\r
-} SCB_Type;\r
-\r
-\r
-/* memory mapping struct for SysTick */\r
-typedef struct\r
-{\r
- __IO uint32_t CTRL; /*!< SysTick Control and Status Register */\r
- __IO uint32_t LOAD; /*!< SysTick Reload Value Register */\r
- __IO uint32_t VAL; /*!< SysTick Current Value Register */\r
- __I uint32_t CALIB; /*!< SysTick Calibration Register */\r
-} SysTick_Type;\r
-\r
-\r
-/* memory mapping structur for ITM */\r
-typedef struct\r
-{\r
- __O union \r
- {\r
- __O uint8_t u8; /*!< ITM Stimulus Port 8-bit */\r
- __O uint16_t u16; /*!< ITM Stimulus Port 16-bit */\r
- __O uint32_t u32; /*!< ITM Stimulus Port 32-bit */\r
- } PORT [32]; /*!< ITM Stimulus Port Registers */\r
- uint32_t RESERVED0[864];\r
- __IO uint32_t TER; /*!< ITM Trace Enable Register */\r
- uint32_t RESERVED1[15];\r
- __IO uint32_t TPR; /*!< ITM Trace Privilege Register */\r
- uint32_t RESERVED2[15];\r
- __IO uint32_t TCR; /*!< ITM Trace Control Register */\r
- uint32_t RESERVED3[29];\r
- __IO uint32_t IWR; /*!< ITM Integration Write Register */\r
- __IO uint32_t IRR; /*!< ITM Integration Read Register */\r
- __IO uint32_t IMCR; /*!< ITM Integration Mode Control Register */\r
- uint32_t RESERVED4[43];\r
- __IO uint32_t LAR; /*!< ITM Lock Access Register */\r
- __IO uint32_t LSR; /*!< ITM Lock Status Register */\r
- uint32_t RESERVED5[6];\r
- __I uint32_t PID4; /*!< ITM Product ID Registers */\r
- __I uint32_t PID5;\r
- __I uint32_t PID6;\r
- __I uint32_t PID7;\r
- __I uint32_t PID0;\r
- __I uint32_t PID1;\r
- __I uint32_t PID2;\r
- __I uint32_t PID3;\r
- __I uint32_t CID0;\r
- __I uint32_t CID1;\r
- __I uint32_t CID2;\r
- __I uint32_t CID3;\r
-} ITM_Type;\r
-\r
-\r
-/* memory mapped struct for Interrupt Type */\r
-typedef struct\r
-{\r
- uint32_t RESERVED0;\r
- __I uint32_t ICTR; /*!< Interrupt Control Type Register */\r
-#if ((defined __CM3_REV) && (__CM3_REV >= 0x200))\r
- __IO uint32_t ACTLR; /*!< Auxiliary Control Register */\r
-#else\r
- uint32_t RESERVED1;\r
-#endif\r
-} InterruptType_Type;\r
-\r
-\r
-/* Memory Protection Unit */\r
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1)\r
-typedef struct\r
-{\r
- __I uint32_t TYPE; /*!< MPU Type Register */\r
- __IO uint32_t CTRL; /*!< MPU Control Register */\r
- __IO uint32_t RNR; /*!< MPU Region RNRber Register */\r
- __IO uint32_t RBAR; /*!< MPU Region Base Address Register */\r
- __IO uint32_t RASR; /*!< MPU Region Attribute and Size Register */\r
- __IO uint32_t RBAR_A1; /*!< MPU Alias 1 Region Base Address Register */\r
- __IO uint32_t RASR_A1; /*!< MPU Alias 1 Region Attribute and Size Register */\r
- __IO uint32_t RBAR_A2; /*!< MPU Alias 2 Region Base Address Register */\r
- __IO uint32_t RASR_A2; /*!< MPU Alias 2 Region Attribute and Size Register */\r
- __IO uint32_t RBAR_A3; /*!< MPU Alias 3 Region Base Address Register */\r
- __IO uint32_t RASR_A3; /*!< MPU Alias 3 Region Attribute and Size Register */\r
-} MPU_Type;\r
-#endif\r
-\r
-\r
-/* Core Debug Register */\r
-typedef struct\r
-{\r
- __IO uint32_t DHCSR; /*!< Debug Halting Control and Status Register */\r
- __O uint32_t DCRSR; /*!< Debug Core Register Selector Register */\r
- __IO uint32_t DCRDR; /*!< Debug Core Register Data Register */\r
- __IO uint32_t DEMCR; /*!< Debug Exception and Monitor Control Register */\r
-} CoreDebug_Type;\r
-\r
-\r
-/* Memory mapping of Cortex-M3 Hardware */\r
-#define SCS_BASE (0xE000E000) /*!< System Control Space Base Address */\r
-#define ITM_BASE (0xE0000000) /*!< ITM Base Address */\r
-#define CoreDebug_BASE (0xE000EDF0) /*!< Core Debug Base Address */\r
-#define SysTick_BASE (SCS_BASE + 0x0010) /*!< SysTick Base Address */\r
-#define NVIC_BASE (SCS_BASE + 0x0100) /*!< NVIC Base Address */\r
-#define SCB_BASE (SCS_BASE + 0x0D00) /*!< System Control Block Base Address */\r
-\r
-#define InterruptType ((InterruptType_Type *) SCS_BASE) /*!< Interrupt Type Register */\r
-#define SCB ((SCB_Type *) SCB_BASE) /*!< SCB configuration struct */\r
-#define SysTick ((SysTick_Type *) SysTick_BASE) /*!< SysTick configuration struct */\r
-#define NVIC ((NVIC_Type *) NVIC_BASE) /*!< NVIC configuration struct */\r
-#define ITM ((ITM_Type *) ITM_BASE) /*!< ITM configuration struct */\r
-#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */\r
-\r
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1)\r
- #define MPU_BASE (SCS_BASE + 0x0D90) /*!< Memory Protection Unit */\r
- #define MPU ((MPU_Type*) MPU_BASE) /*!< Memory Protection Unit */\r
-#endif\r
-\r
-\r
-\r
-/*******************************************************************************\r
- * Hardware Abstraction Layer\r
- ******************************************************************************/\r
-\r
-\r
-#if defined ( __CC_ARM )\r
- #define __ASM __asm /*!< asm keyword for ARM Compiler */\r
- #define __INLINE __inline /*!< inline keyword for ARM Compiler */\r
-\r
-#elif defined ( __ICCARM__ )\r
- #define __ASM __asm /*!< asm keyword for IAR Compiler */\r
- #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */\r
-\r
-#elif defined ( __GNUC__ )\r
- #define __ASM __asm /*!< asm keyword for GNU Compiler */\r
- #define __INLINE inline /*!< inline keyword for GNU Compiler */\r
-\r
-#elif defined ( __TASKING__ )\r
- #define __ASM __asm /*!< asm keyword for TASKING Compiler */\r
- #define __INLINE inline /*!< inline keyword for TASKING Compiler */\r
-\r
-#endif\r
-\r
-\r
-/* ################### Compiler specific Intrinsics ########################### */\r
-\r
-#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/\r
-/* ARM armcc specific functions */\r
-\r
-#define __enable_fault_irq __enable_fiq\r
-#define __disable_fault_irq __disable_fiq\r
-\r
-#define __NOP __nop\r
-#define __WFI __wfi\r
-#define __WFE __wfe\r
-#define __SEV __sev\r
-#define __ISB() __isb(0)\r
-#define __DSB() __dsb(0)\r
-#define __DMB() __dmb(0)\r
-#define __REV __rev\r
-#define __RBIT __rbit\r
-#define __LDREXB(ptr) ((unsigned char ) __ldrex(ptr))\r
-#define __LDREXH(ptr) ((unsigned short) __ldrex(ptr))\r
-#define __LDREXW(ptr) ((unsigned int ) __ldrex(ptr))\r
-#define __STREXB(value, ptr) __strex(value, ptr)\r
-#define __STREXH(value, ptr) __strex(value, ptr)\r
-#define __STREXW(value, ptr) __strex(value, ptr)\r
-\r
-\r
-/* intrinsic unsigned long long __ldrexd(volatile void *ptr) */\r
-/* intrinsic int __strexd(unsigned long long val, volatile void *ptr) */\r
-/* intrinsic void __enable_irq(); */\r
-/* intrinsic void __disable_irq(); */\r
-\r
-\r
-/**\r
- * @brief Return the Process Stack Pointer\r
- *\r
- * @param none\r
- * @return uint32_t ProcessStackPointer\r
- *\r
- * Return the actual process stack pointer\r
- */\r
-extern uint32_t __get_PSP(void);\r
-\r
-/**\r
- * @brief Set the Process Stack Pointer\r
- *\r
- * @param uint32_t Process Stack Pointer\r
- * @return none\r
- *\r
- * Assign the value ProcessStackPointer to the MSP \r
- * (process stack pointer) Cortex processor register\r
- */\r
-extern void __set_PSP(uint32_t topOfProcStack);\r
-\r
-/**\r
- * @brief Return the Main Stack Pointer\r
- *\r
- * @param none\r
- * @return uint32_t Main Stack Pointer\r
- *\r
- * Return the current value of the MSP (main stack pointer)\r
- * Cortex processor register\r
- */\r
-extern uint32_t __get_MSP(void);\r
-\r
-/**\r
- * @brief Set the Main Stack Pointer\r
- *\r
- * @param uint32_t Main Stack Pointer\r
- * @return none\r
- *\r
- * Assign the value mainStackPointer to the MSP \r
- * (main stack pointer) Cortex processor register\r
- */\r
-extern void __set_MSP(uint32_t topOfMainStack);\r
-\r
-/**\r
- * @brief Reverse byte order in unsigned short value\r
- *\r
- * @param uint16_t value to reverse\r
- * @return uint32_t reversed value\r
- *\r
- * Reverse byte order in unsigned short value\r
- */\r
-extern uint32_t __REV16(uint16_t value);\r
-\r
-/*\r
- * @brief Reverse byte order in signed short value with sign extension to integer\r
- *\r
- * @param int16_t value to reverse\r
- * @return int32_t reversed value\r
- *\r
- * Reverse byte order in signed short value with sign extension to integer\r
- */\r
-extern int32_t __REVSH(int16_t value);\r
-\r
-\r
-#if (__ARMCC_VERSION < 400000)\r
-\r
-/**\r
- * @brief Remove the exclusive lock created by ldrex\r
- *\r
- * @param none\r
- * @return none\r
- *\r
- * Removes the exclusive lock which is created by ldrex.\r
- */\r
-extern void __CLREX(void);\r
-\r
-/**\r
- * @brief Return the Base Priority value\r
- *\r
- * @param none\r
- * @return uint32_t BasePriority\r
- *\r
- * Return the content of the base priority register\r
- */\r
-extern uint32_t __get_BASEPRI(void);\r
-\r
-/**\r
- * @brief Set the Base Priority value\r
- *\r
- * @param uint32_t BasePriority\r
- * @return none\r
- *\r
- * Set the base priority register\r
- */\r
-extern void __set_BASEPRI(uint32_t basePri);\r
-\r
-/**\r
- * @brief Return the Priority Mask value\r
- *\r
- * @param none\r
- * @return uint32_t PriMask\r
- *\r
- * Return the state of the priority mask bit from the priority mask\r
- * register\r
- */\r
-extern uint32_t __get_PRIMASK(void);\r
-\r
-/**\r
- * @brief Set the Priority Mask value\r
- *\r
- * @param uint32_t PriMask\r
- * @return none\r
- *\r
- * Set the priority mask bit in the priority mask register\r
- */\r
-extern void __set_PRIMASK(uint32_t priMask);\r
-\r
-/**\r
- * @brief Return the Fault Mask value\r
- *\r
- * @param none\r
- * @return uint32_t FaultMask\r
- *\r
- * Return the content of the fault mask register\r
- */\r
-extern uint32_t __get_FAULTMASK(void);\r
-\r
-/**\r
- * @brief Set the Fault Mask value\r
- *\r
- * @param uint32_t faultMask value\r
- * @return none\r
- *\r
- * Set the fault mask register\r
- */\r
-extern void __set_FAULTMASK(uint32_t faultMask);\r
-\r
-/**\r
- * @brief Return the Control Register value\r
- * \r
- * @param none\r
- * @return uint32_t Control value\r
- *\r
- * Return the content of the control register\r
- */\r
-extern uint32_t __get_CONTROL(void);\r
-\r
-/**\r
- * @brief Set the Control Register value\r
- *\r
- * @param uint32_t Control value\r
- * @return none\r
- *\r
- * Set the control register\r
- */\r
-extern void __set_CONTROL(uint32_t control);\r
-\r
-#else /* (__ARMCC_VERSION >= 400000) */\r
-\r
-\r
-/**\r
- * @brief Remove the exclusive lock created by ldrex\r
- *\r
- * @param none\r
- * @return none\r
- *\r
- * Removes the exclusive lock which is created by ldrex.\r
- */\r
-#define __CLREX __clrex\r
-\r
-/**\r
- * @brief Return the Base Priority value\r
- *\r
- * @param none\r
- * @return uint32_t BasePriority\r
- *\r
- * Return the content of the base priority register\r
- */\r
-static __INLINE uint32_t __get_BASEPRI(void)\r
-{\r
- register uint32_t __regBasePri __ASM("basepri");\r
- return(__regBasePri);\r
-}\r
-\r
-/**\r
- * @brief Set the Base Priority value\r
- *\r
- * @param uint32_t BasePriority\r
- * @return none\r
- *\r
- * Set the base priority register\r
- */\r
-static __INLINE void __set_BASEPRI(uint32_t basePri)\r
-{\r
- register uint32_t __regBasePri __ASM("basepri");\r
- __regBasePri = (basePri & 0x1ff);\r
-}\r
-\r
-/**\r
- * @brief Return the Priority Mask value\r
- *\r
- * @param none\r
- * @return uint32_t PriMask\r
- *\r
- * Return the state of the priority mask bit from the priority mask\r
- * register\r
- */\r
-static __INLINE uint32_t __get_PRIMASK(void)\r
-{\r
- register uint32_t __regPriMask __ASM("primask");\r
- return(__regPriMask);\r
-}\r
-\r
-/**\r
- * @brief Set the Priority Mask value\r
- *\r
- * @param uint32_t PriMask\r
- * @return none\r
- *\r
- * Set the priority mask bit in the priority mask register\r
- */\r
-static __INLINE void __set_PRIMASK(uint32_t priMask)\r
-{\r
- register uint32_t __regPriMask __ASM("primask");\r
- __regPriMask = (priMask);\r
-}\r
-\r
-/**\r
- * @brief Return the Fault Mask value\r
- *\r
- * @param none\r
- * @return uint32_t FaultMask\r
- *\r
- * Return the content of the fault mask register\r
- */\r
-static __INLINE uint32_t __get_FAULTMASK(void)\r
-{\r
- register uint32_t __regFaultMask __ASM("faultmask");\r
- return(__regFaultMask);\r
-}\r
-\r
-/**\r
- * @brief Set the Fault Mask value\r
- *\r
- * @param uint32_t faultMask value\r
- * @return none\r
- *\r
- * Set the fault mask register\r
- */\r
-static __INLINE void __set_FAULTMASK(uint32_t faultMask)\r
-{\r
- register uint32_t __regFaultMask __ASM("faultmask");\r
- __regFaultMask = (faultMask & 1);\r
-}\r
-\r
-/**\r
- * @brief Return the Control Register value\r
- * \r
- * @param none\r
- * @return uint32_t Control value\r
- *\r
- * Return the content of the control register\r
- */\r
-static __INLINE uint32_t __get_CONTROL(void)\r
-{\r
- register uint32_t __regControl __ASM("control");\r
- return(__regControl);\r
-}\r
-\r
-/**\r
- * @brief Set the Control Register value\r
- *\r
- * @param uint32_t Control value\r
- * @return none\r
- *\r
- * Set the control register\r
- */\r
-static __INLINE void __set_CONTROL(uint32_t control)\r
-{\r
- register uint32_t __regControl __ASM("control");\r
- __regControl = control;\r
-}\r
-\r
-#endif /* __ARMCC_VERSION */ \r
-\r
-\r
-\r
-#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/\r
-/* IAR iccarm specific functions */\r
-\r
-#define __enable_irq __enable_interrupt /*!< global Interrupt enable */\r
-#define __disable_irq __disable_interrupt /*!< global Interrupt disable */\r
-\r
-static __INLINE void __enable_fault_irq() { __ASM ("cpsie f"); }\r
-static __INLINE void __disable_fault_irq() { __ASM ("cpsid f"); }\r
-\r
-#define __NOP __no_operation() /*!< no operation intrinsic in IAR Compiler */ \r
-static __INLINE void __WFI() { __ASM ("wfi"); }\r
-static __INLINE void __WFE() { __ASM ("wfe"); }\r
-static __INLINE void __SEV() { __ASM ("sev"); }\r
-static __INLINE void __CLREX() { __ASM ("clrex"); }\r
-\r
-/* intrinsic void __ISB(void) */\r
-/* intrinsic void __DSB(void) */\r
-/* intrinsic void __DMB(void) */\r
-/* intrinsic void __set_PRIMASK(); */\r
-/* intrinsic void __get_PRIMASK(); */\r
-/* intrinsic void __set_FAULTMASK(); */\r
-/* intrinsic void __get_FAULTMASK(); */\r
-/* intrinsic uint32_t __REV(uint32_t value); */\r
-/* intrinsic uint32_t __REVSH(uint32_t value); */\r
-/* intrinsic unsigned long __STREX(unsigned long, unsigned long); */\r
-/* intrinsic unsigned long __LDREX(unsigned long *); */\r
-\r
-\r
-/**\r
- * @brief Return the Process Stack Pointer\r
- *\r
- * @param none\r
- * @return uint32_t ProcessStackPointer\r
- *\r
- * Return the actual process stack pointer\r
- */\r
-extern uint32_t __get_PSP(void);\r
-\r
-/**\r
- * @brief Set the Process Stack Pointer\r
- *\r
- * @param uint32_t Process Stack Pointer\r
- * @return none\r
- *\r
- * Assign the value ProcessStackPointer to the MSP \r
- * (process stack pointer) Cortex processor register\r
- */\r
-extern void __set_PSP(uint32_t topOfProcStack);\r
-\r
-/**\r
- * @brief Return the Main Stack Pointer\r
- *\r
- * @param none\r
- * @return uint32_t Main Stack Pointer\r
- *\r
- * Return the current value of the MSP (main stack pointer)\r
- * Cortex processor register\r
- */\r
-extern uint32_t __get_MSP(void);\r
-\r
-/**\r
- * @brief Set the Main Stack Pointer\r
- *\r
- * @param uint32_t Main Stack Pointer\r
- * @return none\r
- *\r
- * Assign the value mainStackPointer to the MSP \r
- * (main stack pointer) Cortex processor register\r
- */\r
-extern void __set_MSP(uint32_t topOfMainStack);\r
-\r
-/**\r
- * @brief Reverse byte order in unsigned short value\r
- *\r
- * @param uint16_t value to reverse\r
- * @return uint32_t reversed value\r
- *\r
- * Reverse byte order in unsigned short value\r
- */\r
-extern uint32_t __REV16(uint16_t value);\r
-\r
-/**\r
- * @brief Reverse bit order of value\r
- *\r
- * @param uint32_t value to reverse\r
- * @return uint32_t reversed value\r
- *\r
- * Reverse bit order of value\r
- */\r
-extern uint32_t __RBIT(uint32_t value);\r
-\r
-/**\r
- * @brief LDR Exclusive\r
- *\r
- * @param uint8_t* address\r
- * @return uint8_t value of (*address)\r
- *\r
- * Exclusive LDR command\r
- */\r
-extern uint8_t __LDREXB(uint8_t *addr);\r
-\r
-/**\r
- * @brief LDR Exclusive\r
- *\r
- * @param uint16_t* address\r
- * @return uint16_t value of (*address)\r
- *\r
- * Exclusive LDR command\r
- */\r
-extern uint16_t __LDREXH(uint16_t *addr);\r
-\r
-/**\r
- * @brief LDR Exclusive\r
- *\r
- * @param uint32_t* address\r
- * @return uint32_t value of (*address)\r
- *\r
- * Exclusive LDR command\r
- */\r
-extern uint32_t __LDREXW(uint32_t *addr);\r
-\r
-/**\r
- * @brief STR Exclusive\r
- *\r
- * @param uint8_t *address\r
- * @param uint8_t value to store\r
- * @return uint32_t successful / failed\r
- *\r
- * Exclusive STR command\r
- */\r
-extern uint32_t __STREXB(uint8_t value, uint8_t *addr);\r
-\r
-/**\r
- * @brief STR Exclusive\r
- *\r
- * @param uint16_t *address\r
- * @param uint16_t value to store\r
- * @return uint32_t successful / failed\r
- *\r
- * Exclusive STR command\r
- */\r
-extern uint32_t __STREXH(uint16_t value, uint16_t *addr);\r
-\r
-/**\r
- * @brief STR Exclusive\r
- *\r
- * @param uint32_t *address\r
- * @param uint32_t value to store\r
- * @return uint32_t successful / failed\r
- *\r
- * Exclusive STR command\r
- */\r
-extern uint32_t __STREXW(uint32_t value, uint32_t *addr);\r
-\r
-\r
-\r
-#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/\r
-/* GNU gcc specific functions */\r
-\r
-static __INLINE void __enable_irq() { __ASM volatile ("cpsie i"); }\r
-static __INLINE void __disable_irq() { __ASM volatile ("cpsid i"); }\r
-\r
-static __INLINE void __enable_fault_irq() { __ASM volatile ("cpsie f"); }\r
-static __INLINE void __disable_fault_irq() { __ASM volatile ("cpsid f"); }\r
-\r
-static __INLINE void __NOP() { __ASM volatile ("nop"); }\r
-static __INLINE void __WFI() { __ASM volatile ("wfi"); }\r
-static __INLINE void __WFE() { __ASM volatile ("wfe"); }\r
-static __INLINE void __SEV() { __ASM volatile ("sev"); }\r
-static __INLINE void __ISB() { __ASM volatile ("isb"); }\r
-static __INLINE void __DSB() { __ASM volatile ("dsb"); }\r
-static __INLINE void __DMB() { __ASM volatile ("dmb"); }\r
-static __INLINE void __CLREX() { __ASM volatile ("clrex"); }\r
-\r
-\r
-/**\r
- * @brief Return the Process Stack Pointer\r
- *\r
- * @param none\r
- * @return uint32_t ProcessStackPointer\r
- *\r
- * Return the actual process stack pointer\r
- */\r
-extern uint32_t __get_PSP(void);\r
-\r
-/**\r
- * @brief Set the Process Stack Pointer\r
- *\r
- * @param uint32_t Process Stack Pointer\r
- * @return none\r
- *\r
- * Assign the value ProcessStackPointer to the MSP \r
- * (process stack pointer) Cortex processor register\r
- */\r
-extern void __set_PSP(uint32_t topOfProcStack);\r
-\r
-/**\r
- * @brief Return the Main Stack Pointer\r
- *\r
- * @param none\r
- * @return uint32_t Main Stack Pointer\r
- *\r
- * Return the current value of the MSP (main stack pointer)\r
- * Cortex processor register\r
- */\r
-extern uint32_t __get_MSP(void);\r
-\r
-/**\r
- * @brief Set the Main Stack Pointer\r
- *\r
- * @param uint32_t Main Stack Pointer\r
- * @return none\r
- *\r
- * Assign the value mainStackPointer to the MSP \r
- * (main stack pointer) Cortex processor register\r
- */\r
-extern void __set_MSP(uint32_t topOfMainStack);\r
-\r
-/**\r
- * @brief Return the Base Priority value\r
- *\r
- * @param none\r
- * @return uint32_t BasePriority\r
- *\r
- * Return the content of the base priority register\r
- */\r
-extern uint32_t __get_BASEPRI(void);\r
-\r
-/**\r
- * @brief Set the Base Priority value\r
- *\r
- * @param uint32_t BasePriority\r
- * @return none\r
- *\r
- * Set the base priority register\r
- */\r
-extern void __set_BASEPRI(uint32_t basePri);\r
-\r
-/**\r
- * @brief Return the Priority Mask value\r
- *\r
- * @param none\r
- * @return uint32_t PriMask\r
- *\r
- * Return the state of the priority mask bit from the priority mask\r
- * register\r
- */\r
-extern uint32_t __get_PRIMASK(void);\r
-\r
-/**\r
- * @brief Set the Priority Mask value\r
- *\r
- * @param uint32_t PriMask\r
- * @return none\r
- *\r
- * Set the priority mask bit in the priority mask register\r
- */\r
-extern void __set_PRIMASK(uint32_t priMask);\r
-\r
-/**\r
- * @brief Return the Fault Mask value\r
- *\r
- * @param none\r
- * @return uint32_t FaultMask\r
- *\r
- * Return the content of the fault mask register\r
- */\r
-extern uint32_t __get_FAULTMASK(void);\r
-\r
-/**\r
- * @brief Set the Fault Mask value\r
- *\r
- * @param uint32_t faultMask value\r
- * @return none\r
- *\r
- * Set the fault mask register\r
- */\r
-extern void __set_FAULTMASK(uint32_t faultMask);\r
-\r
-/**\r
- * @brief Return the Control Register value\r
-* \r
-* @param none\r
-* @return uint32_t Control value\r
- *\r
- * Return the content of the control register\r
- */\r
-extern uint32_t __get_CONTROL(void);\r
-\r
-/**\r
- * @brief Set the Control Register value\r
- *\r
- * @param uint32_t Control value\r
- * @return none\r
- *\r
- * Set the control register\r
- */\r
-extern void __set_CONTROL(uint32_t control);\r
-\r
-/**\r
- * @brief Reverse byte order in integer value\r
- *\r
- * @param uint32_t value to reverse\r
- * @return uint32_t reversed value\r
- *\r
- * Reverse byte order in integer value\r
- */\r
-extern uint32_t __REV(uint32_t value);\r
-\r
-/**\r
- * @brief Reverse byte order in unsigned short value\r
- *\r
- * @param uint16_t value to reverse\r
- * @return uint32_t reversed value\r
- *\r
- * Reverse byte order in unsigned short value\r
- */\r
-extern uint32_t __REV16(uint16_t value);\r
-\r
-/*\r
- * Reverse byte order in signed short value with sign extension to integer\r
- *\r
- * @param int16_t value to reverse\r
- * @return int32_t reversed value\r
- *\r
- * @brief Reverse byte order in signed short value with sign extension to integer\r
- */\r
-extern int32_t __REVSH(int16_t value);\r
-\r
-/**\r
- * @brief Reverse bit order of value\r
- *\r
- * @param uint32_t value to reverse\r
- * @return uint32_t reversed value\r
- *\r
- * Reverse bit order of value\r
- */\r
-extern uint32_t __RBIT(uint32_t value);\r
-\r
-/**\r
- * @brief LDR Exclusive\r
- *\r
- * @param uint8_t* address\r
- * @return uint8_t value of (*address)\r
- *\r
- * Exclusive LDR command\r
- */\r
-extern uint8_t __LDREXB(uint8_t *addr);\r
-\r
-/**\r
- * @brief LDR Exclusive\r
- *\r
- * @param uint16_t* address\r
- * @return uint16_t value of (*address)\r
- *\r
- * Exclusive LDR command\r
- */\r
-extern uint16_t __LDREXH(uint16_t *addr);\r
-\r
-/**\r
- * @brief LDR Exclusive\r
- *\r
- * @param uint32_t* address\r
- * @return uint32_t value of (*address)\r
- *\r
- * Exclusive LDR command\r
- */\r
-extern uint32_t __LDREXW(uint32_t *addr);\r
-\r
-/**\r
- * @brief STR Exclusive\r
- *\r
- * @param uint8_t *address\r
- * @param uint8_t value to store\r
- * @return uint32_t successful / failed\r
- *\r
- * Exclusive STR command\r
- */\r
-extern uint32_t __STREXB(uint8_t value, uint8_t *addr);\r
-\r
-/**\r
- * @brief STR Exclusive\r
- *\r
- * @param uint16_t *address\r
- * @param uint16_t value to store\r
- * @return uint32_t successful / failed\r
- *\r
- * Exclusive STR command\r
- */\r
-extern uint32_t __STREXH(uint16_t value, uint16_t *addr);\r
-\r
-/**\r
- * @brief STR Exclusive\r
- *\r
- * @param uint32_t *address\r
- * @param uint32_t value to store\r
- * @return uint32_t successful / failed\r
- *\r
- * Exclusive STR command\r
- */\r
-extern uint32_t __STREXW(uint32_t value, uint32_t *addr);\r
-\r
-\r
-#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/\r
-/* TASKING carm specific functions */\r
-\r
-/*\r
- * The CMSIS functions have been implemented as intrinsics in the compiler.\r
- * Please use "carm -?i" to get an up to date list of all instrinsics,\r
- * Including the CMSIS ones.\r
- */\r
-\r
-#endif\r
-\r
-\r
-\r
-/* ########################## NVIC functions #################################### */\r
-\r
-\r
-/**\r
- * @brief Set the Priority Grouping in NVIC Interrupt Controller\r
- *\r
- * @param uint32_t priority_grouping is priority grouping field\r
- * @return none \r
- *\r
- * Set the priority grouping field using the required unlock sequence.\r
- * The parameter priority_grouping is assigned to the field \r
- * SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used.\r
- * In case of a conflict between priority grouping and available\r
- * priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\r
- */\r
-static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)\r
-{\r
- uint32_t reg_value;\r
- uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */\r
- \r
- reg_value = SCB->AIRCR; /* read old register configuration */\r
- reg_value &= ~((0xFFFFU << 16) | (0x0F << 8)); /* clear bits to change */\r
- reg_value = ((reg_value | NVIC_AIRCR_VECTKEY | (PriorityGroupTmp << 8))); /* Insert write key and priorty group */\r
- SCB->AIRCR = reg_value;\r
-}\r
-\r
-/**\r
- * @brief Get the Priority Grouping from NVIC Interrupt Controller\r
- *\r
- * @param none\r
- * @return uint32_t priority grouping field \r
- *\r
- * Get the priority grouping from NVIC Interrupt Controller.\r
- * priority grouping is SCB->AIRCR [10:8] PRIGROUP field.\r
- */\r
-static __INLINE uint32_t NVIC_GetPriorityGrouping(void)\r
-{\r
- return ((SCB->AIRCR >> 8) & 0x07); /* read priority grouping field */\r
-}\r
-\r
-/**\r
- * @brief Enable Interrupt in NVIC Interrupt Controller\r
- *\r
- * @param IRQn_Type IRQn specifies the interrupt number\r
- * @return none \r
- *\r
- * Enable a device specific interupt in the NVIC interrupt controller.\r
- * The interrupt number cannot be a negative value.\r
- */\r
-static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)\r
-{\r
- NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */\r
-}\r
-\r
-/**\r
- * @brief Disable the interrupt line for external interrupt specified\r
- * \r
- * @param IRQn_Type IRQn is the positive number of the external interrupt\r
- * @return none\r
- * \r
- * Disable a device specific interupt in the NVIC interrupt controller.\r
- * The interrupt number cannot be a negative value.\r
- */\r
-static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)\r
-{\r
- NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */\r
-}\r
-\r
-/**\r
- * @brief Read the interrupt pending bit for a device specific interrupt source\r
- * \r
- * @param IRQn_Type IRQn is the number of the device specifc interrupt\r
- * @return uint32_t 1 if pending interrupt else 0\r
- *\r
- * Read the pending register in NVIC and return 1 if its status is pending, \r
- * otherwise it returns 0\r
- */\r
-static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
-{\r
- return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */\r
-}\r
-\r
-/**\r
- * @brief Set the pending bit for an external interrupt\r
- * \r
- * @param IRQn_Type IRQn is the Number of the interrupt\r
- * @return none\r
- *\r
- * Set the pending bit for the specified interrupt.\r
- * The interrupt number cannot be a negative value.\r
- */\r
-static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
-{\r
- NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */\r
-}\r
-\r
-/**\r
- * @brief Clear the pending bit for an external interrupt\r
- *\r
- * @param IRQn_Type IRQn is the Number of the interrupt\r
- * @return none\r
- *\r
- * Clear the pending bit for the specified interrupt. \r
- * The interrupt number cannot be a negative value.\r
- */\r
-static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
-{\r
- NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */\r
-}\r
-\r
-/**\r
- * @brief Read the active bit for an external interrupt\r
- *\r
- * @param IRQn_Type IRQn is the Number of the interrupt\r
- * @return uint32_t 1 if active else 0\r
- *\r
- * Read the active register in NVIC and returns 1 if its status is active, \r
- * otherwise it returns 0.\r
- */\r
-static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)\r
-{\r
- return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */\r
-}\r
-\r
-/**\r
- * @brief Set the priority for an interrupt\r
- *\r
- * @param IRQn_Type IRQn is the Number of the interrupt\r
- * @param priority is the priority for the interrupt\r
- * @return none\r
- *\r
- * Set the priority for the specified interrupt. The interrupt \r
- * number can be positive to specify an external (device specific) \r
- * interrupt, or negative to specify an internal (core) interrupt. \n\r
- *\r
- * Note: The priority cannot be set for every core interrupt.\r
- */\r
-static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r
-{\r
- if(IRQn < 0) {\r
- SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M3 System Interrupts */\r
- else {\r
- NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */\r
-}\r
-\r
-/**\r
- * @brief Read the priority for an interrupt\r
- *\r
- * @param IRQn_Type IRQn is the Number of the interrupt\r
- * @return uint32_t priority is the priority for the interrupt\r
- *\r
- * Read the priority for the specified interrupt. The interrupt \r
- * number can be positive to specify an external (device specific) \r
- * interrupt, or negative to specify an internal (core) interrupt.\r
- *\r
- * The returned priority value is automatically aligned to the implemented\r
- * priority bits of the microcontroller.\r
- *\r
- * Note: The priority cannot be set for every core interrupt.\r
- */\r
-static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)\r
-{\r
-\r
- if(IRQn < 0) {\r
- return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M3 system interrupts */\r
- else {\r
- return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */\r
-}\r
-\r
-\r
-/**\r
- * @brief Encode the priority for an interrupt\r
- *\r
- * @param uint32_t PriorityGroup is the used priority group\r
- * @param uint32_t PreemptPriority is the preemptive priority value (starting from 0)\r
- * @param uint32_t SubPriority is the sub priority value (starting from 0)\r
- * @return uint32_t the priority for the interrupt\r
- *\r
- * Encode the priority for an interrupt with the given priority group,\r
- * preemptive priority value and sub priority value.\r
- * In case of a conflict between priority grouping and available\r
- * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.\r
- *\r
- * The returned priority value can be used for NVIC_SetPriority(...) function\r
- */\r
-static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\r
-{\r
- uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */\r
- uint32_t PreemptPriorityBits;\r
- uint32_t SubPriorityBits;\r
-\r
- PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;\r
- SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;\r
- \r
- return (\r
- ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |\r
- ((SubPriority & ((1 << (SubPriorityBits )) - 1)))\r
- );\r
-}\r
-\r
-\r
-/**\r
- * @brief Decode the priority of an interrupt\r
- *\r
- * @param uint32_t Priority the priority for the interrupt\r
- * @param uint32_t PrioGroup is the used priority group\r
- * @param uint32_t* pPreemptPrio is the preemptive priority value (starting from 0)\r
- * @param uint32_t* pSubPrio is the sub priority value (starting from 0)\r
- * @return none\r
- *\r
- * Decode an interrupt priority value with the given priority group to \r
- * preemptive priority value and sub priority value.\r
- * In case of a conflict between priority grouping and available\r
- * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.\r
- *\r
- * The priority value can be retrieved with NVIC_GetPriority(...) function\r
- */\r
-static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)\r
-{\r
- uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */\r
- uint32_t PreemptPriorityBits;\r
- uint32_t SubPriorityBits;\r
-\r
- PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;\r
- SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;\r
- \r
- *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);\r
- *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);\r
-}\r
-\r
-\r
-\r
-/* ################################## SysTick function ############################################ */\r
-\r
-#if (!defined (__Vendor_SysTickConfig)) || (__Vendor_SysTickConfig == 0)\r
-\r
-/* SysTick constants */\r
-#define SYSTICK_ENABLE 0 /* Config-Bit to start or stop the SysTick Timer */\r
-#define SYSTICK_TICKINT 1 /* Config-Bit to enable or disable the SysTick interrupt */\r
-#define SYSTICK_CLKSOURCE 2 /* Clocksource has the offset 2 in SysTick Control and Status Register */\r
-#define SYSTICK_MAXCOUNT ((1<<24) -1) /* SysTick MaxCount */\r
-\r
-/**\r
- * @brief Initialize and start the SysTick counter and its interrupt.\r
- *\r
- * @param uint32_t ticks is the number of ticks between two interrupts\r
- * @return none\r
- *\r
- * Initialise the system tick timer and its interrupt and start the\r
- * system tick timer / counter in free running mode to generate \r
- * periodical interrupts.\r
- */\r
-static __INLINE uint32_t SysTick_Config(uint32_t ticks)\r
-{ \r
- if (ticks > SYSTICK_MAXCOUNT) return (1); /* Reload value impossible */\r
-\r
- SysTick->LOAD = (ticks & SYSTICK_MAXCOUNT) - 1; /* set reload register */\r
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- SysTick->CTRL = (1 << SYSTICK_CLKSOURCE) | (1<<SYSTICK_ENABLE) | (1<<SYSTICK_TICKINT); /* Enable SysTick IRQ and SysTick Timer */\r
- return (0); /* Function successful */\r
-}\r
-\r
-#endif\r
-\r
-\r
-\r
-\r
-\r
-/* ################################## Reset function ############################################ */\r
-\r
-/**\r
- * @brief Initiate a system reset request.\r
- *\r
- * @param none\r
- * @return none\r
- *\r
- * Initialize a system reset request to reset the MCU\r
- */\r
-static __INLINE void NVIC_SystemReset(void)\r
-{\r
- SCB->AIRCR = (NVIC_AIRCR_VECTKEY | (SCB->AIRCR & (0x700)) | (1<<NVIC_SYSRESETREQ)); /* Keep priority group unchanged */\r
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- while(1); /* wait until reset */\r
-}\r
-\r
-\r
-/* ################################## Debug Output function ############################################ */\r
-\r
-\r
-/**\r
- * @brief Outputs a character via the ITM channel 0\r
- *\r
- * @param uint32_t character to output\r
- * @return uint32_t input character\r
- *\r
- * The function outputs a character via the ITM channel 0. \r
- * The function returns when no debugger is connected that has booked the output. \r
- * It is blocking when a debugger is connected, but the previous character send is not transmitted. \r
- */\r
-static __INLINE uint32_t ITM_SendChar (uint32_t ch)\r
-{\r
- if (ch == '\n') ITM_SendChar('\r');\r
- \r
- if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA) &&\r
- (ITM->TCR & ITM_TCR_ITMENA) &&\r
- (ITM->TER & (1UL << 0)) ) \r
- {\r
- while (ITM->PORT[0].u32 == 0);\r
- ITM->PORT[0].u8 = (uint8_t) ch;\r
- } \r
- return (ch);\r
-}\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
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-#endif /* __CM3_CORE_H__ */\r
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+@REM C-SPY Debugger, as an aid to preparing a command line for running\r
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- <state>$TOOLKIT_DIR$\CONFIG\debugger\ST\iostm32f10x.ddf</state>\r
+ <state>$TOOLKIT_DIR$\CONFIG\debugger\ST\iostm32f10xxb.ddf</state>\r
</option>\r
<option>\r
<name>RunToEnable</name>\r
</option>\r
<option>\r
<name>OCLastSavedByProductVersion</name>\r
- <state>5.11.0.50615</state>\r
+ <state>6.20.1.52589</state>\r
</option>\r
<option>\r
<name>OCDownloadAttachToProgram</name>\r
<state>0</state>\r
</option>\r
- <option>\r
- <name>FlashLoaders</name>\r
- <state>,,,,(default),</state>\r
- </option>\r
<option>\r
<name>UseFlashLoader</name>\r
<state>1</state>\r
<name>OCBE8Slave</name>\r
<state>1</state>\r
</option>\r
+ <option>\r
+ <name>MacFile2</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CDevice</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>FlashLoadersV3</name>\r
+ <state>$TOOLKIT_DIR$\config\flashloader\ST\FlashSTM32F10xxB.board</state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesSuppressCheck1</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesPath1</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesSuppressCheck2</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesPath2</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesSuppressCheck3</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesPath3</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OverrideDefFlashBoard</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesOffset1</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesOffset2</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesOffset3</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesUse1</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesUse2</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesUse3</name>\r
+ <state>0</state>\r
+ </option>\r
</data>\r
</settings>\r
<settings>\r
<name>IARROM_ID</name>\r
<archiveVersion>2</archiveVersion>\r
<data>\r
- <version>0</version>\r
+ <version>1</version>\r
<wantNonLocal>1</wantNonLocal>\r
<debug>1</debug>\r
<option>\r
<name>CRomLogFileEditB</name>\r
<state>$TOOLKIT_DIR$\cspycomm.log</state>\r
</option>\r
- <option>\r
- <name>CRomCommunication</name>\r
- <state>0</state>\r
- </option>\r
<option>\r
<name>CRomCommPort</name>\r
<version>0</version>\r
<name>JLINK_ID</name>\r
<archiveVersion>2</archiveVersion>\r
<data>\r
- <version>9</version>\r
+ <version>13</version>\r
<wantNonLocal>1</wantNonLocal>\r
<debug>1</debug>\r
<option>\r
</option>\r
<option>\r
<name>CCUSBDevice</name>\r
- <version>0</version>\r
- <state>0</state>\r
+ <version>1</version>\r
+ <state>1</state>\r
</option>\r
<option>\r
<name>CCRDICatchReset</name>\r
</option>\r
<option>\r
<name>CCJLinkResetList</name>\r
+ <version>5</version>\r
+ <state>7</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkInterfaceCmdLine</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCatchCORERESET</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCatchMMERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCatchNOCPERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCatchCHRERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCatchSTATERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCatchBUSERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCatchINTERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCatchHARDERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCatchDummy</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCJLinkScriptFile</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkUsbSerialNo</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCTcpIpAlt</name>\r
<version>0</version>\r
- <state>5</state>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkTcpIpSerialNo</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCCpuClockEdit</name>\r
+ <state>72.0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSwoClockAuto</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSwoClockEdit</name>\r
+ <state>2000</state>\r
</option>\r
</data>\r
</settings>\r
<name>LMIFTDI_ID</name>\r
<archiveVersion>2</archiveVersion>\r
<data>\r
- <version>1</version>\r
+ <version>2</version>\r
<wantNonLocal>1</wantNonLocal>\r
<debug>1</debug>\r
<option>\r
<name>CCLmiftdiLogFile</name>\r
<state>$TOOLKIT_DIR$\cspycomm.log</state>\r
</option>\r
+ <option>\r
+ <name>CCLmiFtdiInterfaceRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCLmiFtdiInterfaceCmdLine</name>\r
+ <state>0</state>\r
+ </option>\r
</data>\r
</settings>\r
<settings>\r
<name>MACRAIGOR_ID</name>\r
<archiveVersion>2</archiveVersion>\r
<data>\r
- <version>2</version>\r
+ <version>3</version>\r
<wantNonLocal>1</wantNonLocal>\r
<debug>1</debug>\r
<option>\r
<name>CCJTagUpdateBreakpoints</name>\r
<state>main</state>\r
</option>\r
+ <option>\r
+ <name>CCMacraigorInterfaceRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCMacraigorInterfaceCmdLine</name>\r
+ <state>0</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>PEMICRO_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>0</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OCPEMicroAttachSlave</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPEMicroInterfaceList</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPEMicroResetDelay</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCPEMicroJtagSpeed</name>\r
+ <state>#UNINITIALIZED#</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJPEMicroShowSettings</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>DoLogfile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>LogFile</name>\r
+ <state>$PROJ_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPEMicroUSBDevice</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPEMicroSerialPort</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJPEMicroTCPIPAutoScanNetwork</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPEMicroTCPIP</name>\r
+ <state>10.0.0.1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPEMicroCommCmdLineProducer</name>\r
+ <state>0</state>\r
+ </option>\r
</data>\r
</settings>\r
<settings>\r
<name>RDI_ID</name>\r
<archiveVersion>2</archiveVersion>\r
<data>\r
- <version>1</version>\r
+ <version>2</version>\r
<wantNonLocal>1</wantNonLocal>\r
<debug>1</debug>\r
<option>\r
<state>0</state>\r
</option>\r
<option>\r
- <name>CCRDIUseETM</name>\r
- <state>0</state>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
</option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>STLINK_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>2</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
<option>\r
<name>OCDriverInfo</name>\r
<state>1</state>\r
</option>\r
+ <option>\r
+ <name>CCSTLinkInterfaceRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSTLinkInterfaceCmdLine</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSTLinkResetList</name>\r
+ <version>1</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCpuClockEdit</name>\r
+ <state>72.0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSwoClockAuto</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSwoClockEdit</name>\r
+ <state>2000</state>\r
+ </option>\r
</data>\r
</settings>\r
<settings>\r
</settings>\r
<debuggerPlugins>\r
<plugin>\r
- <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ewplugin</file>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file>\r
<loadFlag>0</loadFlag>\r
</plugin>\r
<plugin>\r
- <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ewplugin</file>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file>\r
<loadFlag>0</loadFlag>\r
</plugin>\r
<plugin>\r
<loadFlag>0</loadFlag>\r
</plugin>\r
<plugin>\r
- <file>$TOOLKIT_DIR$\plugins\rtos\OSE\OseEpsilonPlugin.ewplugin</file>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file>\r
<loadFlag>0</loadFlag>\r
</plugin>\r
<plugin>\r
<loadFlag>0</loadFlag>\r
</plugin>\r
<plugin>\r
- <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ewplugin</file>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB6_Plugin.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file>\r
<loadFlag>0</loadFlag>\r
</plugin>\r
<plugin>\r
<loadFlag>0</loadFlag>\r
</plugin>\r
<plugin>\r
- <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>\r
+ <file>$EW_DIR$\common\plugins\FreeRTOS\FreeRTOSPlugin.ewplugin</file>\r
<loadFlag>0</loadFlag>\r
</plugin>\r
<plugin>\r
- <file>$EW_DIR$\common\plugins\Profiling\Profiling.ENU.ewplugin</file>\r
+ <file>$EW_DIR$\common\plugins\OpenRTOS\OpenRTOSPlugin.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>\r
<loadFlag>0</loadFlag>\r
</plugin>\r
<plugin>\r
<file>$EW_DIR$\common\plugins\Stack\Stack.ENU.ewplugin</file>\r
<loadFlag>0</loadFlag>\r
</plugin>\r
+ <plugin>\r
+ <file>$EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin</file>\r
+ <loadFlag>1</loadFlag>\r
+ </plugin>\r
</debuggerPlugins>\r
</configuration>\r
</project>\r
<?xml version="1.0" encoding="iso-8859-1"?>\r
\r
<project>\r
- <fileVersion>1</fileVersion>\r
+ <fileVersion>2</fileVersion>\r
<configuration>\r
<name>Debug</name>\r
<toolchain>\r
<name>General</name>\r
<archiveVersion>3</archiveVersion>\r
<data>\r
- <version>14</version>\r
+ <version>21</version>\r
<wantNonLocal>1</wantNonLocal>\r
<debug>1</debug>\r
<option>\r
</option>\r
<option>\r
<name>Variant</name>\r
- <version>7</version>\r
- <state>31</state>\r
+ <version>19</version>\r
+ <state>37</state>\r
</option>\r
<option>\r
<name>GEndianMode</name>\r
</option>\r
<option>\r
<name>Input variant</name>\r
- <version>1</version>\r
- <state>3</state>\r
+ <version>3</version>\r
+ <state>6</state>\r
</option>\r
<option>\r
<name>Input description</name>\r
</option>\r
<option>\r
<name>Output variant</name>\r
- <version>0</version>\r
- <state>3</state>\r
+ <version>2</version>\r
+ <state>7</state>\r
</option>\r
<option>\r
<name>Output description</name>\r
</option>\r
<option>\r
<name>FPU</name>\r
- <version>0</version>\r
+ <version>2</version>\r
<state>0</state>\r
</option>\r
<option>\r
<name>RTDescription</name>\r
<state>Use the full configuration of the C/C++ runtime library. Full locale interface, C locale, file descriptor support, multibytes in printf and scanf, and hex floats in strtod.</state>\r
</option>\r
- <option>\r
- <name>RTConfigPath</name>\r
- <state>$TOOLKIT_DIR$\INC\DLib_Config_Full.h</state>\r
- </option>\r
<option>\r
<name>OGProductVersion</name>\r
<state>4.41A</state>\r
<name>OGLastSavedByProductVersion</name>\r
<state>5.11.0.50615</state>\r
</option>\r
- <option>\r
- <name>GeneralMisraRules</name>\r
- <version>0</version>\r
- <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>\r
- </option>\r
<option>\r
<name>GeneralEnableMisra</name>\r
<state>0</state>\r
</option>\r
<option>\r
<name>OGChipSelectEditMenu</name>\r
- <state>STM32F10x ST STM32F10x</state>\r
+ <state>STM32F10xxB ST STM32F10xxB</state>\r
</option>\r
<option>\r
<name>GenLowLevelInterface</name>\r
<name>OGBufferedTerminalOutput</name>\r
<state>0</state>\r
</option>\r
+ <option>\r
+ <name>GenStdoutInterface</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>GeneralMisraRules98</name>\r
+ <version>0</version>\r
+ <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>\r
+ </option>\r
+ <option>\r
+ <name>GeneralMisraVer</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>GeneralMisraRules04</name>\r
+ <version>0</version>\r
+ <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>\r
+ </option>\r
+ <option>\r
+ <name>RTConfigPath2</name>\r
+ <state>$TOOLKIT_DIR$\INC\c\DLib_Config_Full.h</state>\r
+ </option>\r
+ <option>\r
+ <name>GFPUCoreSlave</name>\r
+ <version>19</version>\r
+ <state>37</state>\r
+ </option>\r
+ <option>\r
+ <name>GBECoreSlave</name>\r
+ <version>19</version>\r
+ <state>37</state>\r
+ </option>\r
+ <option>\r
+ <name>OGUseCmsis</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OGUseCmsisDspLib</name>\r
+ <state>0</state>\r
+ </option>\r
</data>\r
</settings>\r
<settings>\r
<name>ICCARM</name>\r
<archiveVersion>2</archiveVersion>\r
<data>\r
- <version>19</version>\r
+ <version>28</version>\r
<wantNonLocal>1</wantNonLocal>\r
<debug>1</debug>\r
<option>\r
<name>OutputFile</name>\r
<state>$FILE_BNAME$.o</state>\r
</option>\r
- <option>\r
- <name>CCLangSelect</name>\r
- <state>0</state>\r
- </option>\r
<option>\r
<name>CCLibConfigHeader</name>\r
<state>1</state>\r
<name>PreInclude</name>\r
<state></state>\r
</option>\r
- <option>\r
- <name>CompilerMisraRules</name>\r
- <version>0</version>\r
- <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>\r
- </option>\r
<option>\r
<name>CompilerMisraOverride</name>\r
<state>0</state>\r
<name>CCStdIncCheck</name>\r
<state>0</state>\r
</option>\r
- <option>\r
- <name>CCStdIncludePath</name>\r
- <state>$TOOLKIT_DIR$\INC\</state>\r
- </option>\r
<option>\r
<name>CCCodeSection</name>\r
<state>.text</state>\r
<name>CCOptLevelSlave</name>\r
<state>1</state>\r
</option>\r
+ <option>\r
+ <name>CompilerMisraRules98</name>\r
+ <version>0</version>\r
+ <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>\r
+ </option>\r
+ <option>\r
+ <name>CompilerMisraRules04</name>\r
+ <version>0</version>\r
+ <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPosIndRopi</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPosIndRwpi</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPosIndNoDynInit</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IccLang</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IccCDialect</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IccAllowVLA</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IccCppDialect</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IccExceptions</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IccRTTI</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IccStaticDestr</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IccCppInlineSemantics</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IccCmsis</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IccFloatSemantics</name>\r
+ <state>0</state>\r
+ </option>\r
</data>\r
</settings>\r
<settings>\r
<name>AARM</name>\r
<archiveVersion>2</archiveVersion>\r
<data>\r
- <version>7</version>\r
+ <version>8</version>\r
<wantNonLocal>1</wantNonLocal>\r
<debug>1</debug>\r
<option>\r
<name>AIgnoreStdInclude</name>\r
<state>0</state>\r
</option>\r
- <option>\r
- <name>AStdIncludes</name>\r
- <state>$TOOLKIT_DIR$\INC\</state>\r
- </option>\r
<option>\r
<name>AUserIncludes</name>\r
<state>$PROJ_DIR$\.</state>\r
<debug>1</debug>\r
<option>\r
<name>OOCOutputFormat</name>\r
- <version>1</version>\r
+ <version>2</version>\r
<state>0</state>\r
</option>\r
<option>\r
<name>ILINK</name>\r
<archiveVersion>0</archiveVersion>\r
<data>\r
- <version>5</version>\r
+ <version>13</version>\r
<wantNonLocal>1</wantNonLocal>\r
<debug>1</debug>\r
<option>\r
<name>IlinkProgramEntryLabel</name>\r
<state>__iar_program_start</state>\r
</option>\r
- <option>\r
- <name>IlinkNXPLPCChecksum</name>\r
- <state>0</state>\r
- </option>\r
<option>\r
<name>DoFill</name>\r
<state>0</state>\r
<name>IlinkBufferedTerminalOutput</name>\r
<state>1</state>\r
</option>\r
+ <option>\r
+ <name>IlinkStdoutInterfaceSlave</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CrcFullSize</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkIElfToolPostProcess</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkLogAutoLibSelect</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkLogRedirSymbols</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkLogUnusedFragments</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkCrcReverseByteOrder</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkCrcUseAsInput</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkOptInline</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkOptExceptionsAllow</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkOptExceptionsForce</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkCmsis</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkOptMergeDuplSections</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkOptUseVfe</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkOptForceVfe</name>\r
+ <state>0</state>\r
+ </option>\r
</data>\r
</settings>\r
<settings>\r
</option>\r
<option>\r
<name>OCLastSavedByProductVersion</name>\r
- <state>6.10.1.52170</state>\r
+ <state>6.20.1.52589</state>\r
</option>\r
<option>\r
<name>OCDownloadAttachToProgram</name>\r
<name>JLINK_ID</name>\r
<archiveVersion>2</archiveVersion>\r
<data>\r
- <version>12</version>\r
+ <version>13</version>\r
<wantNonLocal>1</wantNonLocal>\r
<debug>1</debug>\r
<option>\r
</option>\r
<option>\r
<name>CCUSBDevice</name>\r
- <version>0</version>\r
- <state>0</state>\r
+ <version>1</version>\r
+ <state>1</state>\r
</option>\r
<option>\r
<name>CCRDICatchReset</name>\r
</option>\r
<option>\r
<name>CCJLinkResetList</name>\r
- <version>4</version>\r
+ <version>5</version>\r
<state>7</state>\r
</option>\r
<option>\r
<name>OCJLinkScriptFile</name>\r
<state>1</state>\r
</option>\r
+ <option>\r
+ <name>CCJLinkUsbSerialNo</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCTcpIpAlt</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkTcpIpSerialNo</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCCpuClockEdit</name>\r
+ <state>72.0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSwoClockAuto</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSwoClockEdit</name>\r
+ <state>2000</state>\r
+ </option>\r
</data>\r
</settings>\r
<settings>\r
<name>RDI_ID</name>\r
<archiveVersion>2</archiveVersion>\r
<data>\r
- <version>1</version>\r
+ <version>2</version>\r
<wantNonLocal>1</wantNonLocal>\r
<debug>1</debug>\r
<option>\r
<name>CCRDICatchFIQ</name>\r
<state>0</state>\r
</option>\r
- <option>\r
- <name>CCRDIUseETM</name>\r
- <state>0</state>\r
- </option>\r
<option>\r
<name>OCDriverInfo</name>\r
<state>1</state>\r
<name>STLINK_ID</name>\r
<archiveVersion>2</archiveVersion>\r
<data>\r
- <version>1</version>\r
+ <version>2</version>\r
<wantNonLocal>1</wantNonLocal>\r
<debug>1</debug>\r
<option>\r
<name>CCSTLinkInterfaceCmdLine</name>\r
<state>0</state>\r
</option>\r
+ <option>\r
+ <name>CCSTLinkResetList</name>\r
+ <version>1</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCpuClockEdit</name>\r
+ <state>72.0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSwoClockAuto</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSwoClockEdit</name>\r
+ <state>2000</state>\r
+ </option>\r
</data>\r
</settings>\r
<settings>\r
<file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>\r
<loadFlag>0</loadFlag>\r
</plugin>\r
- <plugin>\r
- <file>$EW_DIR$\common\plugins\Profiling\Profiling.ENU.ewplugin</file>\r
- <loadFlag>1</loadFlag>\r
- </plugin>\r
<plugin>\r
<file>$EW_DIR$\common\plugins\Stack\Stack.ENU.ewplugin</file>\r
<loadFlag>1</loadFlag>\r
<name>JLINK_ID</name>\r
<archiveVersion>2</archiveVersion>\r
<data>\r
- <version>12</version>\r
+ <version>13</version>\r
<wantNonLocal>1</wantNonLocal>\r
<debug>1</debug>\r
<option>\r
</option>\r
<option>\r
<name>CCUSBDevice</name>\r
- <version>0</version>\r
- <state>0</state>\r
+ <version>1</version>\r
+ <state>1</state>\r
</option>\r
<option>\r
<name>CCRDICatchReset</name>\r
</option>\r
<option>\r
<name>CCJLinkResetList</name>\r
- <version>4</version>\r
+ <version>5</version>\r
<state>7</state>\r
</option>\r
<option>\r
<name>OCJLinkScriptFile</name>\r
<state>1</state>\r
</option>\r
+ <option>\r
+ <name>CCJLinkUsbSerialNo</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCTcpIpAlt</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkTcpIpSerialNo</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCCpuClockEdit</name>\r
+ <state>72.0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSwoClockAuto</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSwoClockEdit</name>\r
+ <state>2000</state>\r
+ </option>\r
</data>\r
</settings>\r
<settings>\r
<name>RDI_ID</name>\r
<archiveVersion>2</archiveVersion>\r
<data>\r
- <version>1</version>\r
+ <version>2</version>\r
<wantNonLocal>1</wantNonLocal>\r
<debug>1</debug>\r
<option>\r
<name>CCRDICatchFIQ</name>\r
<state>0</state>\r
</option>\r
- <option>\r
- <name>CCRDIUseETM</name>\r
- <state>0</state>\r
- </option>\r
<option>\r
<name>OCDriverInfo</name>\r
<state>1</state>\r
<name>STLINK_ID</name>\r
<archiveVersion>2</archiveVersion>\r
<data>\r
- <version>1</version>\r
+ <version>2</version>\r
<wantNonLocal>1</wantNonLocal>\r
<debug>1</debug>\r
<option>\r
<name>CCSTLinkInterfaceCmdLine</name>\r
<state>0</state>\r
</option>\r
+ <option>\r
+ <name>CCSTLinkResetList</name>\r
+ <version>1</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCpuClockEdit</name>\r
+ <state>72.0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSwoClockAuto</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSwoClockEdit</name>\r
+ <state>2000</state>\r
+ </option>\r
</data>\r
</settings>\r
<settings>\r
<file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>\r
<loadFlag>0</loadFlag>\r
</plugin>\r
- <plugin>\r
- <file>$EW_DIR$\common\plugins\Profiling\Profiling.ENU.ewplugin</file>\r
- <loadFlag>1</loadFlag>\r
- </plugin>\r
<plugin>\r
<file>$EW_DIR$\common\plugins\Stack\Stack.ENU.ewplugin</file>\r
<loadFlag>1</loadFlag>\r
<name>General</name>\r
<archiveVersion>3</archiveVersion>\r
<data>\r
- <version>18</version>\r
+ <version>21</version>\r
<wantNonLocal>1</wantNonLocal>\r
<debug>1</debug>\r
<option>\r
</option>\r
<option>\r
<name>Variant</name>\r
- <version>17</version>\r
+ <version>19</version>\r
<state>37</state>\r
</option>\r
<option>\r
</option>\r
<option>\r
<name>Input variant</name>\r
- <version>1</version>\r
- <state>3</state>\r
+ <version>3</version>\r
+ <state>6</state>\r
</option>\r
<option>\r
<name>Input description</name>\r
</option>\r
<option>\r
<name>Output variant</name>\r
- <version>0</version>\r
- <state>3</state>\r
+ <version>2</version>\r
+ <state>7</state>\r
</option>\r
<option>\r
<name>Output description</name>\r
</option>\r
<option>\r
<name>FPU</name>\r
- <version>1</version>\r
+ <version>2</version>\r
<state>0</state>\r
</option>\r
<option>\r
</option>\r
<option>\r
<name>OGLastSavedByProductVersion</name>\r
- <state>6.10.1.52170</state>\r
+ <state>6.20.1.52589</state>\r
</option>\r
<option>\r
<name>GeneralEnableMisra</name>\r
<name>RTConfigPath2</name>\r
<state>$TOOLKIT_DIR$\INC\c\DLib_Config_Normal.h</state>\r
</option>\r
+ <option>\r
+ <name>GFPUCoreSlave</name>\r
+ <version>19</version>\r
+ <state>37</state>\r
+ </option>\r
+ <option>\r
+ <name>GBECoreSlave</name>\r
+ <version>19</version>\r
+ <state>37</state>\r
+ </option>\r
+ <option>\r
+ <name>OGUseCmsis</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OGUseCmsisDspLib</name>\r
+ <state>0</state>\r
+ </option>\r
</data>\r
</settings>\r
<settings>\r
<name>ICCARM</name>\r
<archiveVersion>2</archiveVersion>\r
<data>\r
- <version>26</version>\r
+ <version>28</version>\r
<wantNonLocal>1</wantNonLocal>\r
<debug>1</debug>\r
<option>\r
<state>1</state>\r
</option>\r
<option>\r
- <name>IccRelaxedFpPrecision</name>\r
+ <name>IccCppInlineSemantics</name>\r
<state>0</state>\r
</option>\r
<option>\r
- <name>IccCppInlineSemantics</name>\r
+ <name>IccCmsis</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IccFloatSemantics</name>\r
<state>0</state>\r
</option>\r
</data>\r
<name>ILINK</name>\r
<archiveVersion>0</archiveVersion>\r
<data>\r
- <version>11</version>\r
+ <version>13</version>\r
<wantNonLocal>1</wantNonLocal>\r
<debug>1</debug>\r
<option>\r
<name>IlinkOptExceptionsForce</name>\r
<state>0</state>\r
</option>\r
+ <option>\r
+ <name>IlinkCmsis</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkOptMergeDuplSections</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkOptUseVfe</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkOptForceVfe</name>\r
+ <state>0</state>\r
+ </option>\r
</data>\r
</settings>\r
<settings>\r
<name>General</name>\r
<archiveVersion>3</archiveVersion>\r
<data>\r
- <version>18</version>\r
+ <version>21</version>\r
<wantNonLocal>1</wantNonLocal>\r
<debug>1</debug>\r
<option>\r
</option>\r
<option>\r
<name>Variant</name>\r
- <version>17</version>\r
+ <version>19</version>\r
<state>37</state>\r
</option>\r
<option>\r
</option>\r
<option>\r
<name>Input variant</name>\r
- <version>1</version>\r
- <state>3</state>\r
+ <version>3</version>\r
+ <state>6</state>\r
</option>\r
<option>\r
<name>Input description</name>\r
</option>\r
<option>\r
<name>Output variant</name>\r
- <version>0</version>\r
- <state>3</state>\r
+ <version>2</version>\r
+ <state>7</state>\r
</option>\r
<option>\r
<name>Output description</name>\r
</option>\r
<option>\r
<name>FPU</name>\r
- <version>1</version>\r
+ <version>2</version>\r
<state>0</state>\r
</option>\r
<option>\r
</option>\r
<option>\r
<name>OGLastSavedByProductVersion</name>\r
- <state>6.10.1.52170</state>\r
+ <state>6.20.1.52589</state>\r
</option>\r
<option>\r
<name>GeneralEnableMisra</name>\r
<name>RTConfigPath2</name>\r
<state>$TOOLKIT_DIR$\INC\c\DLib_Config_Normal.h</state>\r
</option>\r
+ <option>\r
+ <name>GFPUCoreSlave</name>\r
+ <version>19</version>\r
+ <state>37</state>\r
+ </option>\r
+ <option>\r
+ <name>GBECoreSlave</name>\r
+ <version>19</version>\r
+ <state>37</state>\r
+ </option>\r
+ <option>\r
+ <name>OGUseCmsis</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OGUseCmsisDspLib</name>\r
+ <state>0</state>\r
+ </option>\r
</data>\r
</settings>\r
<settings>\r
<name>ICCARM</name>\r
<archiveVersion>2</archiveVersion>\r
<data>\r
- <version>26</version>\r
+ <version>28</version>\r
<wantNonLocal>1</wantNonLocal>\r
<debug>1</debug>\r
<option>\r
<state>1</state>\r
</option>\r
<option>\r
- <name>IccRelaxedFpPrecision</name>\r
+ <name>IccCppInlineSemantics</name>\r
<state>0</state>\r
</option>\r
<option>\r
- <name>IccCppInlineSemantics</name>\r
+ <name>IccCmsis</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IccFloatSemantics</name>\r
<state>0</state>\r
</option>\r
</data>\r
<name>ILINK</name>\r
<archiveVersion>0</archiveVersion>\r
<data>\r
- <version>11</version>\r
+ <version>13</version>\r
<wantNonLocal>1</wantNonLocal>\r
<debug>1</debug>\r
<option>\r
<name>IlinkOptExceptionsForce</name>\r
<state>0</state>\r
</option>\r
+ <option>\r
+ <name>IlinkCmsis</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkOptMergeDuplSections</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkOptUseVfe</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkOptForceVfe</name>\r
+ <state>0</state>\r
+ </option>\r
</data>\r
</settings>\r
<settings>\r
@REM \r
\r
\r
-"C:\devtools\IAR Systems\Embedded Workbench 6.0\common\bin\cspybat" "C:\devtools\IAR Systems\Embedded Workbench 6.0\arm\bin\armproc.dll" "C:\devtools\IAR Systems\Embedded Workbench 6.0\arm\bin\armjlink.dll" %1 --plugin "C:\devtools\IAR Systems\Embedded Workbench 6.0\arm\bin\armbat.dll" --flash_loader "C:\devtools\IAR Systems\Embedded Workbench 6.0\arm\config\flashloader\ST\FlashSTM32L15xxB.board" --backend -B "--endian=little" "--cpu=Cortex-M3" "--fpu=None" "-p" "C:\devtools\IAR Systems\Embedded Workbench 6.0\arm\CONFIG\debugger\ST\iostm32l152xx.ddf" "--semihosting" "--device=STM32L152xB" "--drv_communication=USB0" "--jlink_speed=auto" "--jlink_initial_speed=32" "--jlink_reset_strategy=0,0" "--jlink_interface=SWD" "--drv_catch_exceptions=0x000" \r
+"C:\devtools\IAR Systems\Embedded Workbench 6.0\common\bin\cspybat" "C:\devtools\IAR Systems\Embedded Workbench 6.0\arm\bin\armproc.dll" "C:\devtools\IAR Systems\Embedded Workbench 6.0\arm\bin\armjlink.dll" %1 --plugin "C:\devtools\IAR Systems\Embedded Workbench 6.0\arm\bin\armbat.dll" --flash_loader "C:\devtools\IAR Systems\Embedded Workbench 6.0\arm\config\flashloader\ST\FlashSTM32L15xxB.board" --backend -B "--endian=little" "--cpu=Cortex-M3" "--fpu=None" "-p" "C:\devtools\IAR Systems\Embedded Workbench 6.0\arm\CONFIG\debugger\ST\iostm32l152xx.ddf" "--semihosting" "--device=STM32L152xB" "--drv_communication=USB0" "--jlink_speed=auto" "--jlink_initial_speed=32" "--jlink_reset_strategy=0,0" "--jlink_interface=SWD" "--drv_catch_exceptions=0x000" "--drv_swo_clock_setup=72000000,0,2000000" \r
\r
\r
Mode=3\r
Graph=0\r
Symbiont=0\r
+[Breakpoints]\r
+Count=0\r
+[Stack]\r
+FillEnabled=0\r
+OverflowWarningsEnabled=1\r
+WarningThreshold=90\r
+SpWarningsEnabled=1\r
+WarnLogOnly=1\r
+UseTrigger=1\r
+TriggerName=main\r
+LimitSize=0\r
+ByteLimit=50\r
[Disassemble mode]\r
mode=0\r
-[Breakpoints]\r
+[Breakpoints2]\r
Count=0\r
[Aliases]\r
Count=0\r
<Build><ColumnWidth0>20</ColumnWidth0><ColumnWidth1>1216</ColumnWidth1><ColumnWidth2>324</ColumnWidth2><ColumnWidth3>81</ColumnWidth3></Build><TerminalIO/><Debug-Log><ColumnWidth0>20</ColumnWidth0><ColumnWidth1>1622</ColumnWidth1></Debug-Log></Static>\r
<Windows>\r
\r
- <Wnd2>\r
+ <Wnd0>\r
<Tabs>\r
<Tab>\r
<Identity>TabID-27630-4718</Identity>\r
</Tab>\r
</Tabs>\r
\r
- <SelectedTab>0</SelectedTab></Wnd2><Wnd3><Tabs><Tab><Identity>TabID-10002-7709</Identity><TabName>Build</TabName><Factory>Build</Factory><Session/></Tab><Tab><Identity>TabID-18437-21512</Identity><TabName>Debug Log</TabName><Factory>Debug-Log</Factory><Session/></Tab></Tabs><SelectedTab>0</SelectedTab></Wnd3></Windows>\r
+ <SelectedTab>0</SelectedTab></Wnd0><Wnd1><Tabs><Tab><Identity>TabID-10002-7709</Identity><TabName>Build</TabName><Factory>Build</Factory><Session/></Tab><Tab><Identity>TabID-18437-21512</Identity><TabName>Debug Log</TabName><Factory>Debug-Log</Factory><Session/></Tab></Tabs><SelectedTab>0</SelectedTab></Wnd1></Windows>\r
<Editor>\r
\r
\r
\r
\r
\r
- <Top><Row0><Sizes><Toolbar-012aad60><key>iaridepm.enu1</key></Toolbar-012aad60></Sizes></Row0><Row1><Sizes/></Row1></Top><Left><Row0><Sizes><Wnd2><Rect><Top>-2</Top><Left>-2</Left><Bottom>740</Bottom><Right>438</Right><x>-2</x><y>-2</y><xscreen>200</xscreen><yscreen>200</yscreen><sizeHorzCX>119048</sizeHorzCX><sizeHorzCY>203666</sizeHorzCY><sizeVertCX>261905</sizeVertCX><sizeVertCY>755601</sizeVertCY></Rect></Wnd2></Sizes></Row0></Left><Right><Row0><Sizes/></Row0></Right><Bottom><Row0><Sizes><Wnd3><Rect><Top>-2</Top><Left>-2</Left><Bottom>198</Bottom><Right>1682</Right><x>-2</x><y>-2</y><xscreen>1684</xscreen><yscreen>200</yscreen><sizeHorzCX>1002381</sizeHorzCX><sizeHorzCY>203666</sizeHorzCY><sizeVertCX>119048</sizeVertCX><sizeVertCY>203666</sizeVertCY></Rect></Wnd3></Sizes></Row0></Bottom><Float><Sizes/></Float></Positions>\r
+ <Top><Row0><Sizes><Toolbar-01336218><key>iaridepm.enu1</key></Toolbar-01336218></Sizes></Row0></Top><Left><Row0><Sizes><Wnd0><Rect><Top>-2</Top><Left>-2</Left><Bottom>740</Bottom><Right>438</Right><x>-2</x><y>-2</y><xscreen>200</xscreen><yscreen>200</yscreen><sizeHorzCX>119048</sizeHorzCX><sizeHorzCY>203666</sizeHorzCY><sizeVertCX>261905</sizeVertCX><sizeVertCY>755601</sizeVertCY></Rect></Wnd0></Sizes></Row0></Left><Right><Row0><Sizes/></Row0></Right><Bottom><Row0><Sizes><Wnd1><Rect><Top>-2</Top><Left>-2</Left><Bottom>198</Bottom><Right>1682</Right><x>-2</x><y>-2</y><xscreen>1684</xscreen><yscreen>200</yscreen><sizeHorzCX>1002381</sizeHorzCX><sizeHorzCY>203666</sizeHorzCY><sizeVertCX>119048</sizeVertCX><sizeVertCY>203666</sizeVertCY></Rect></Wnd1></Sizes></Row0></Bottom><Float><Sizes/></Float></Positions>\r
</Desktop>\r
</Workspace>\r
\r
+++ /dev/null
-/**************************************************************************//**\r
- * @file core_cm3.h\r
- * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File\r
- * @version V1.30\r
- * @date 30. October 2009\r
- *\r
- * @note\r
- * Copyright (C) 2009 ARM Limited. All rights reserved.\r
- *\r
- * @par\r
- * ARM Limited (ARM) is supplying this software for use with Cortex-M\r
- * processor based microcontrollers. This file can be freely distributed\r
- * within development tools that are supporting such ARM based processors.\r
- *\r
- * @par\r
- * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
- * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
- *\r
- ******************************************************************************/\r
-\r
-#ifndef __CM3_CORE_H__\r
-#define __CM3_CORE_H__\r
-\r
-/** @addtogroup CMSIS_CM3_core_LintCinfiguration CMSIS CM3 Core Lint Configuration\r
- *\r
- * List of Lint messages which will be suppressed and not shown:\r
- * - Error 10: \n\r
- * register uint32_t __regBasePri __asm("basepri"); \n\r
- * Error 10: Expecting ';'\r
- * .\r
- * - Error 530: \n\r
- * return(__regBasePri); \n\r
- * Warning 530: Symbol '__regBasePri' (line 264) not initialized\r
- * .\r
- * - Error 550: \n\r
- * __regBasePri = (basePri & 0x1ff); \n\r
- * Warning 550: Symbol '__regBasePri' (line 271) not accessed\r
- * .\r
- * - Error 754: \n\r
- * uint32_t RESERVED0[24]; \n\r
- * Info 754: local structure member '<some, not used in the HAL>' (line 109, file ./cm3_core.h) not referenced\r
- * .\r
- * - Error 750: \n\r
- * #define __CM3_CORE_H__ \n\r
- * Info 750: local macro '__CM3_CORE_H__' (line 43, file./cm3_core.h) not referenced\r
- * .\r
- * - Error 528: \n\r
- * static __INLINE void NVIC_DisableIRQ(uint32_t IRQn) \n\r
- * Warning 528: Symbol 'NVIC_DisableIRQ(unsigned int)' (line 419, file ./cm3_core.h) not referenced\r
- * .\r
- * - Error 751: \n\r
- * } InterruptType_Type; \n\r
- * Info 751: local typedef 'InterruptType_Type' (line 170, file ./cm3_core.h) not referenced\r
- * .\r
- * Note: To re-enable a Message, insert a space before 'lint' *\r
- *\r
- */\r
-\r
-/*lint -save */\r
-/*lint -e10 */\r
-/*lint -e530 */\r
-/*lint -e550 */\r
-/*lint -e754 */\r
-/*lint -e750 */\r
-/*lint -e528 */\r
-/*lint -e751 */\r
-\r
-\r
-/** @addtogroup CMSIS_CM3_core_definitions CM3 Core Definitions\r
- This file defines all structures and symbols for CMSIS core:\r
- - CMSIS version number\r
- - Cortex-M core registers and bitfields\r
- - Cortex-M core peripheral base address\r
- @{\r
- */\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-#define __CM3_CMSIS_VERSION_MAIN (0x01) /*!< [31:16] CMSIS HAL main version */\r
-#define __CM3_CMSIS_VERSION_SUB (0x30) /*!< [15:0] CMSIS HAL sub version */\r
-#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */\r
-\r
-#define __CORTEX_M (0x03) /*!< Cortex core */\r
-\r
-#include <stdint.h> /* Include standard types */\r
-\r
-#if defined (__ICCARM__)\r
- #include <intrinsics.h> /* IAR Intrinsics */\r
-#endif\r
-\r
-\r
-#ifndef __NVIC_PRIO_BITS\r
- #define __NVIC_PRIO_BITS 4 /*!< standard definition for NVIC Priority Bits */\r
-#endif\r
-\r
-\r
-\r
-\r
-/**\r
- * IO definitions\r
- *\r
- * define access restrictions to peripheral registers\r
- */\r
-\r
-#ifdef __cplusplus\r
- #define __I volatile /*!< defines 'read only' permissions */\r
-#else\r
- #define __I volatile const /*!< defines 'read only' permissions */\r
-#endif\r
-#define __O volatile /*!< defines 'write only' permissions */\r
-#define __IO volatile /*!< defines 'read / write' permissions */\r
-\r
-\r
-\r
-/*******************************************************************************\r
- * Register Abstraction\r
- ******************************************************************************/\r
-/** @addtogroup CMSIS_CM3_core_register CMSIS CM3 Core Register\r
- @{\r
-*/\r
-\r
-\r
-/** @addtogroup CMSIS_CM3_NVIC CMSIS CM3 NVIC\r
- memory mapped structure for Nested Vectored Interrupt Controller (NVIC)\r
- @{\r
- */\r
-typedef struct\r
-{\r
- __IO uint32_t ISER[8]; /*!< Offset: 0x000 Interrupt Set Enable Register */\r
- uint32_t RESERVED0[24];\r
- __IO uint32_t ICER[8]; /*!< Offset: 0x080 Interrupt Clear Enable Register */\r
- uint32_t RSERVED1[24];\r
- __IO uint32_t ISPR[8]; /*!< Offset: 0x100 Interrupt Set Pending Register */\r
- uint32_t RESERVED2[24];\r
- __IO uint32_t ICPR[8]; /*!< Offset: 0x180 Interrupt Clear Pending Register */\r
- uint32_t RESERVED3[24];\r
- __IO uint32_t IABR[8]; /*!< Offset: 0x200 Interrupt Active bit Register */\r
- uint32_t RESERVED4[56];\r
- __IO uint8_t IP[240]; /*!< Offset: 0x300 Interrupt Priority Register (8Bit wide) */\r
- uint32_t RESERVED5[644];\r
- __O uint32_t STIR; /*!< Offset: 0xE00 Software Trigger Interrupt Register */\r
-} NVIC_Type;\r
-/*@}*/ /* end of group CMSIS_CM3_NVIC */\r
-\r
-\r
-/** @addtogroup CMSIS_CM3_SCB CMSIS CM3 SCB\r
- memory mapped structure for System Control Block (SCB)\r
- @{\r
- */\r
-typedef struct\r
-{\r
- __I uint32_t CPUID; /*!< Offset: 0x00 CPU ID Base Register */\r
- __IO uint32_t ICSR; /*!< Offset: 0x04 Interrupt Control State Register */\r
- __IO uint32_t VTOR; /*!< Offset: 0x08 Vector Table Offset Register */\r
- __IO uint32_t AIRCR; /*!< Offset: 0x0C Application Interrupt / Reset Control Register */\r
- __IO uint32_t SCR; /*!< Offset: 0x10 System Control Register */\r
- __IO uint32_t CCR; /*!< Offset: 0x14 Configuration Control Register */\r
- __IO uint8_t SHP[12]; /*!< Offset: 0x18 System Handlers Priority Registers (4-7, 8-11, 12-15) */\r
- __IO uint32_t SHCSR; /*!< Offset: 0x24 System Handler Control and State Register */\r
- __IO uint32_t CFSR; /*!< Offset: 0x28 Configurable Fault Status Register */\r
- __IO uint32_t HFSR; /*!< Offset: 0x2C Hard Fault Status Register */\r
- __IO uint32_t DFSR; /*!< Offset: 0x30 Debug Fault Status Register */\r
- __IO uint32_t MMFAR; /*!< Offset: 0x34 Mem Manage Address Register */\r
- __IO uint32_t BFAR; /*!< Offset: 0x38 Bus Fault Address Register */\r
- __IO uint32_t AFSR; /*!< Offset: 0x3C Auxiliary Fault Status Register */\r
- __I uint32_t PFR[2]; /*!< Offset: 0x40 Processor Feature Register */\r
- __I uint32_t DFR; /*!< Offset: 0x48 Debug Feature Register */\r
- __I uint32_t ADR; /*!< Offset: 0x4C Auxiliary Feature Register */\r
- __I uint32_t MMFR[4]; /*!< Offset: 0x50 Memory Model Feature Register */\r
- __I uint32_t ISAR[5]; /*!< Offset: 0x60 ISA Feature Register */\r
-} SCB_Type;\r
-\r
-/* SCB CPUID Register Definitions */\r
-#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */\r
-#define SCB_CPUID_IMPLEMENTER_Msk (0xFFul << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */\r
-\r
-#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */\r
-#define SCB_CPUID_VARIANT_Msk (0xFul << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */\r
-\r
-#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */\r
-#define SCB_CPUID_PARTNO_Msk (0xFFFul << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */\r
-\r
-#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */\r
-#define SCB_CPUID_REVISION_Msk (0xFul << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */\r
-\r
-/* SCB Interrupt Control State Register Definitions */\r
-#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */\r
-#define SCB_ICSR_NMIPENDSET_Msk (1ul << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */\r
-\r
-#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */\r
-#define SCB_ICSR_PENDSVSET_Msk (1ul << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */\r
-\r
-#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */\r
-#define SCB_ICSR_PENDSVCLR_Msk (1ul << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */\r
-\r
-#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */\r
-#define SCB_ICSR_PENDSTSET_Msk (1ul << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */\r
-\r
-#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */\r
-#define SCB_ICSR_PENDSTCLR_Msk (1ul << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */\r
-\r
-#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */\r
-#define SCB_ICSR_ISRPREEMPT_Msk (1ul << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */\r
-\r
-#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */\r
-#define SCB_ICSR_ISRPENDING_Msk (1ul << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */\r
-\r
-#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */\r
-#define SCB_ICSR_VECTPENDING_Msk (0x1FFul << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */\r
-\r
-#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */\r
-#define SCB_ICSR_RETTOBASE_Msk (1ul << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */\r
-\r
-#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */\r
-#define SCB_ICSR_VECTACTIVE_Msk (0x1FFul << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */\r
-\r
-/* SCB Interrupt Control State Register Definitions */\r
-#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */\r
-#define SCB_VTOR_TBLBASE_Msk (0x1FFul << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */\r
-\r
-#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */\r
-#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFul << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */\r
-\r
-/* SCB Application Interrupt and Reset Control Register Definitions */\r
-#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */\r
-#define SCB_AIRCR_VECTKEY_Msk (0xFFFFul << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */\r
-\r
-#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */\r
-#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFul << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */\r
-\r
-#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */\r
-#define SCB_AIRCR_ENDIANESS_Msk (1ul << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */\r
-\r
-#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */\r
-#define SCB_AIRCR_PRIGROUP_Msk (7ul << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */\r
-\r
-#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */\r
-#define SCB_AIRCR_SYSRESETREQ_Msk (1ul << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */\r
-\r
-#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */\r
-#define SCB_AIRCR_VECTCLRACTIVE_Msk (1ul << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r
-\r
-#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */\r
-#define SCB_AIRCR_VECTRESET_Msk (1ul << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */\r
-\r
-/* SCB System Control Register Definitions */\r
-#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */\r
-#define SCB_SCR_SEVONPEND_Msk (1ul << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */\r
-\r
-#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */\r
-#define SCB_SCR_SLEEPDEEP_Msk (1ul << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */\r
-\r
-#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */\r
-#define SCB_SCR_SLEEPONEXIT_Msk (1ul << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */\r
-\r
-/* SCB Configuration Control Register Definitions */\r
-#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */\r
-#define SCB_CCR_STKALIGN_Msk (1ul << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */\r
-\r
-#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */\r
-#define SCB_CCR_BFHFNMIGN_Msk (1ul << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */\r
-\r
-#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */\r
-#define SCB_CCR_DIV_0_TRP_Msk (1ul << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */\r
-\r
-#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */\r
-#define SCB_CCR_UNALIGN_TRP_Msk (1ul << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */\r
-\r
-#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */\r
-#define SCB_CCR_USERSETMPEND_Msk (1ul << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */\r
-\r
-#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */\r
-#define SCB_CCR_NONBASETHRDENA_Msk (1ul << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */\r
-\r
-/* SCB System Handler Control and State Register Definitions */\r
-#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */\r
-#define SCB_SHCSR_USGFAULTENA_Msk (1ul << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */\r
-\r
-#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */\r
-#define SCB_SHCSR_BUSFAULTENA_Msk (1ul << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */\r
-\r
-#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */\r
-#define SCB_SHCSR_MEMFAULTENA_Msk (1ul << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */\r
-\r
-#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */\r
-#define SCB_SHCSR_SVCALLPENDED_Msk (1ul << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */\r
-\r
-#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */\r
-#define SCB_SHCSR_BUSFAULTPENDED_Msk (1ul << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */\r
-\r
-#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */\r
-#define SCB_SHCSR_MEMFAULTPENDED_Msk (1ul << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */\r
-\r
-#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */\r
-#define SCB_SHCSR_USGFAULTPENDED_Msk (1ul << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */\r
-\r
-#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */\r
-#define SCB_SHCSR_SYSTICKACT_Msk (1ul << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */\r
-\r
-#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */\r
-#define SCB_SHCSR_PENDSVACT_Msk (1ul << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */\r
-\r
-#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */\r
-#define SCB_SHCSR_MONITORACT_Msk (1ul << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */\r
-\r
-#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */\r
-#define SCB_SHCSR_SVCALLACT_Msk (1ul << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */\r
-\r
-#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */\r
-#define SCB_SHCSR_USGFAULTACT_Msk (1ul << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */\r
-\r
-#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */\r
-#define SCB_SHCSR_BUSFAULTACT_Msk (1ul << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */\r
-\r
-#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */\r
-#define SCB_SHCSR_MEMFAULTACT_Msk (1ul << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */\r
-\r
-/* SCB Configurable Fault Status Registers Definitions */\r
-#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */\r
-#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFul << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */\r
-\r
-#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */\r
-#define SCB_CFSR_BUSFAULTSR_Msk (0xFFul << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */\r
-\r
-#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */\r
-#define SCB_CFSR_MEMFAULTSR_Msk (0xFFul << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */\r
-\r
-/* SCB Hard Fault Status Registers Definitions */\r
-#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */\r
-#define SCB_HFSR_DEBUGEVT_Msk (1ul << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */\r
-\r
-#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */\r
-#define SCB_HFSR_FORCED_Msk (1ul << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */\r
-\r
-#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */\r
-#define SCB_HFSR_VECTTBL_Msk (1ul << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */\r
-\r
-/* SCB Debug Fault Status Register Definitions */\r
-#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */\r
-#define SCB_DFSR_EXTERNAL_Msk (1ul << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */\r
-\r
-#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */\r
-#define SCB_DFSR_VCATCH_Msk (1ul << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */\r
-\r
-#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */\r
-#define SCB_DFSR_DWTTRAP_Msk (1ul << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */\r
-\r
-#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */\r
-#define SCB_DFSR_BKPT_Msk (1ul << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */\r
-\r
-#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */\r
-#define SCB_DFSR_HALTED_Msk (1ul << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */\r
-/*@}*/ /* end of group CMSIS_CM3_SCB */\r
-\r
-\r
-/** @addtogroup CMSIS_CM3_SysTick CMSIS CM3 SysTick\r
- memory mapped structure for SysTick\r
- @{\r
- */\r
-typedef struct\r
-{\r
- __IO uint32_t CTRL; /*!< Offset: 0x00 SysTick Control and Status Register */\r
- __IO uint32_t LOAD; /*!< Offset: 0x04 SysTick Reload Value Register */\r
- __IO uint32_t VAL; /*!< Offset: 0x08 SysTick Current Value Register */\r
- __I uint32_t CALIB; /*!< Offset: 0x0C SysTick Calibration Register */\r
-} SysTick_Type;\r
-\r
-/* SysTick Control / Status Register Definitions */\r
-#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */\r
-#define SysTick_CTRL_COUNTFLAG_Msk (1ul << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */\r
-\r
-#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */\r
-#define SysTick_CTRL_CLKSOURCE_Msk (1ul << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */\r
-\r
-#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */\r
-#define SysTick_CTRL_TICKINT_Msk (1ul << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */\r
-\r
-#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */\r
-#define SysTick_CTRL_ENABLE_Msk (1ul << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */\r
-\r
-/* SysTick Reload Register Definitions */\r
-#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */\r
-#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFul << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */\r
-\r
-/* SysTick Current Register Definitions */\r
-#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */\r
-#define SysTick_VAL_CURRENT_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */\r
-\r
-/* SysTick Calibration Register Definitions */\r
-#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */\r
-#define SysTick_CALIB_NOREF_Msk (1ul << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */\r
-\r
-#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */\r
-#define SysTick_CALIB_SKEW_Msk (1ul << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */\r
-\r
-#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */\r
-#define SysTick_CALIB_TENMS_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */\r
-/*@}*/ /* end of group CMSIS_CM3_SysTick */\r
-\r
-\r
-/** @addtogroup CMSIS_CM3_ITM CMSIS CM3 ITM\r
- memory mapped structure for Instrumentation Trace Macrocell (ITM)\r
- @{\r
- */\r
-typedef struct\r
-{\r
- __O union\r
- {\r
- __O uint8_t u8; /*!< Offset: ITM Stimulus Port 8-bit */\r
- __O uint16_t u16; /*!< Offset: ITM Stimulus Port 16-bit */\r
- __O uint32_t u32; /*!< Offset: ITM Stimulus Port 32-bit */\r
- } PORT [32]; /*!< Offset: 0x00 ITM Stimulus Port Registers */\r
- uint32_t RESERVED0[864];\r
- __IO uint32_t TER; /*!< Offset: ITM Trace Enable Register */\r
- uint32_t RESERVED1[15];\r
- __IO uint32_t TPR; /*!< Offset: ITM Trace Privilege Register */\r
- uint32_t RESERVED2[15];\r
- __IO uint32_t TCR; /*!< Offset: ITM Trace Control Register */\r
- uint32_t RESERVED3[29];\r
- __IO uint32_t IWR; /*!< Offset: ITM Integration Write Register */\r
- __IO uint32_t IRR; /*!< Offset: ITM Integration Read Register */\r
- __IO uint32_t IMCR; /*!< Offset: ITM Integration Mode Control Register */\r
- uint32_t RESERVED4[43];\r
- __IO uint32_t LAR; /*!< Offset: ITM Lock Access Register */\r
- __IO uint32_t LSR; /*!< Offset: ITM Lock Status Register */\r
- uint32_t RESERVED5[6];\r
- __I uint32_t PID4; /*!< Offset: ITM Peripheral Identification Register #4 */\r
- __I uint32_t PID5; /*!< Offset: ITM Peripheral Identification Register #5 */\r
- __I uint32_t PID6; /*!< Offset: ITM Peripheral Identification Register #6 */\r
- __I uint32_t PID7; /*!< Offset: ITM Peripheral Identification Register #7 */\r
- __I uint32_t PID0; /*!< Offset: ITM Peripheral Identification Register #0 */\r
- __I uint32_t PID1; /*!< Offset: ITM Peripheral Identification Register #1 */\r
- __I uint32_t PID2; /*!< Offset: ITM Peripheral Identification Register #2 */\r
- __I uint32_t PID3; /*!< Offset: ITM Peripheral Identification Register #3 */\r
- __I uint32_t CID0; /*!< Offset: ITM Component Identification Register #0 */\r
- __I uint32_t CID1; /*!< Offset: ITM Component Identification Register #1 */\r
- __I uint32_t CID2; /*!< Offset: ITM Component Identification Register #2 */\r
- __I uint32_t CID3; /*!< Offset: ITM Component Identification Register #3 */\r
-} ITM_Type;\r
-\r
-/* ITM Trace Privilege Register Definitions */\r
-#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */\r
-#define ITM_TPR_PRIVMASK_Msk (0xFul << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */\r
-\r
-/* ITM Trace Control Register Definitions */\r
-#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */\r
-#define ITM_TCR_BUSY_Msk (1ul << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */\r
-\r
-#define ITM_TCR_ATBID_Pos 16 /*!< ITM TCR: ATBID Position */\r
-#define ITM_TCR_ATBID_Msk (0x7Ful << ITM_TCR_ATBID_Pos) /*!< ITM TCR: ATBID Mask */\r
-\r
-#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */\r
-#define ITM_TCR_TSPrescale_Msk (3ul << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */\r
-\r
-#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */\r
-#define ITM_TCR_SWOENA_Msk (1ul << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */\r
-\r
-#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */\r
-#define ITM_TCR_DWTENA_Msk (1ul << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */\r
-\r
-#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */\r
-#define ITM_TCR_SYNCENA_Msk (1ul << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */\r
-\r
-#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */\r
-#define ITM_TCR_TSENA_Msk (1ul << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */\r
-\r
-#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */\r
-#define ITM_TCR_ITMENA_Msk (1ul << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */\r
-\r
-/* ITM Integration Write Register Definitions */\r
-#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */\r
-#define ITM_IWR_ATVALIDM_Msk (1ul << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */\r
-\r
-/* ITM Integration Read Register Definitions */\r
-#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */\r
-#define ITM_IRR_ATREADYM_Msk (1ul << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */\r
-\r
-/* ITM Integration Mode Control Register Definitions */\r
-#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */\r
-#define ITM_IMCR_INTEGRATION_Msk (1ul << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */\r
-\r
-/* ITM Lock Status Register Definitions */\r
-#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */\r
-#define ITM_LSR_ByteAcc_Msk (1ul << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */\r
-\r
-#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */\r
-#define ITM_LSR_Access_Msk (1ul << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */\r
-\r
-#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */\r
-#define ITM_LSR_Present_Msk (1ul << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */\r
-/*@}*/ /* end of group CMSIS_CM3_ITM */\r
-\r
-\r
-/** @addtogroup CMSIS_CM3_InterruptType CMSIS CM3 Interrupt Type\r
- memory mapped structure for Interrupt Type\r
- @{\r
- */\r
-typedef struct\r
-{\r
- uint32_t RESERVED0;\r
- __I uint32_t ICTR; /*!< Offset: 0x04 Interrupt Control Type Register */\r
-#if ((defined __CM3_REV) && (__CM3_REV >= 0x200))\r
- __IO uint32_t ACTLR; /*!< Offset: 0x08 Auxiliary Control Register */\r
-#else\r
- uint32_t RESERVED1;\r
-#endif\r
-} InterruptType_Type;\r
-\r
-/* Interrupt Controller Type Register Definitions */\r
-#define InterruptType_ICTR_INTLINESNUM_Pos 0 /*!< InterruptType ICTR: INTLINESNUM Position */\r
-#define InterruptType_ICTR_INTLINESNUM_Msk (0x1Ful << InterruptType_ICTR_INTLINESNUM_Pos) /*!< InterruptType ICTR: INTLINESNUM Mask */\r
-\r
-/* Auxiliary Control Register Definitions */\r
-#define InterruptType_ACTLR_DISFOLD_Pos 2 /*!< InterruptType ACTLR: DISFOLD Position */\r
-#define InterruptType_ACTLR_DISFOLD_Msk (1ul << InterruptType_ACTLR_DISFOLD_Pos) /*!< InterruptType ACTLR: DISFOLD Mask */\r
-\r
-#define InterruptType_ACTLR_DISDEFWBUF_Pos 1 /*!< InterruptType ACTLR: DISDEFWBUF Position */\r
-#define InterruptType_ACTLR_DISDEFWBUF_Msk (1ul << InterruptType_ACTLR_DISDEFWBUF_Pos) /*!< InterruptType ACTLR: DISDEFWBUF Mask */\r
-\r
-#define InterruptType_ACTLR_DISMCYCINT_Pos 0 /*!< InterruptType ACTLR: DISMCYCINT Position */\r
-#define InterruptType_ACTLR_DISMCYCINT_Msk (1ul << InterruptType_ACTLR_DISMCYCINT_Pos) /*!< InterruptType ACTLR: DISMCYCINT Mask */\r
-/*@}*/ /* end of group CMSIS_CM3_InterruptType */\r
-\r
-\r
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1)\r
-/** @addtogroup CMSIS_CM3_MPU CMSIS CM3 MPU\r
- memory mapped structure for Memory Protection Unit (MPU)\r
- @{\r
- */\r
-typedef struct\r
-{\r
- __I uint32_t TYPE; /*!< Offset: 0x00 MPU Type Register */\r
- __IO uint32_t CTRL; /*!< Offset: 0x04 MPU Control Register */\r
- __IO uint32_t RNR; /*!< Offset: 0x08 MPU Region RNRber Register */\r
- __IO uint32_t RBAR; /*!< Offset: 0x0C MPU Region Base Address Register */\r
- __IO uint32_t RASR; /*!< Offset: 0x10 MPU Region Attribute and Size Register */\r
- __IO uint32_t RBAR_A1; /*!< Offset: 0x14 MPU Alias 1 Region Base Address Register */\r
- __IO uint32_t RASR_A1; /*!< Offset: 0x18 MPU Alias 1 Region Attribute and Size Register */\r
- __IO uint32_t RBAR_A2; /*!< Offset: 0x1C MPU Alias 2 Region Base Address Register */\r
- __IO uint32_t RASR_A2; /*!< Offset: 0x20 MPU Alias 2 Region Attribute and Size Register */\r
- __IO uint32_t RBAR_A3; /*!< Offset: 0x24 MPU Alias 3 Region Base Address Register */\r
- __IO uint32_t RASR_A3; /*!< Offset: 0x28 MPU Alias 3 Region Attribute and Size Register */\r
-} MPU_Type;\r
-\r
-/* MPU Type Register */\r
-#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */\r
-#define MPU_TYPE_IREGION_Msk (0xFFul << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */\r
-\r
-#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */\r
-#define MPU_TYPE_DREGION_Msk (0xFFul << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */\r
-\r
-#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */\r
-#define MPU_TYPE_SEPARATE_Msk (1ul << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */\r
-\r
-/* MPU Control Register */\r
-#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */\r
-#define MPU_CTRL_PRIVDEFENA_Msk (1ul << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */\r
-\r
-#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */\r
-#define MPU_CTRL_HFNMIENA_Msk (1ul << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */\r
-\r
-#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */\r
-#define MPU_CTRL_ENABLE_Msk (1ul << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */\r
-\r
-/* MPU Region Number Register */\r
-#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */\r
-#define MPU_RNR_REGION_Msk (0xFFul << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */\r
-\r
-/* MPU Region Base Address Register */\r
-#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */\r
-#define MPU_RBAR_ADDR_Msk (0x7FFFFFFul << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */\r
-\r
-#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */\r
-#define MPU_RBAR_VALID_Msk (1ul << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */\r
-\r
-#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */\r
-#define MPU_RBAR_REGION_Msk (0xFul << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */\r
-\r
-/* MPU Region Attribute and Size Register */\r
-#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: XN Position */\r
-#define MPU_RASR_XN_Msk (1ul << MPU_RASR_XN_Pos) /*!< MPU RASR: XN Mask */\r
-\r
-#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: AP Position */\r
-#define MPU_RASR_AP_Msk (7ul << MPU_RASR_AP_Pos) /*!< MPU RASR: AP Mask */\r
-\r
-#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: TEX Position */\r
-#define MPU_RASR_TEX_Msk (7ul << MPU_RASR_TEX_Pos) /*!< MPU RASR: TEX Mask */\r
-\r
-#define MPU_RASR_S_Pos 18 /*!< MPU RASR: Shareable bit Position */\r
-#define MPU_RASR_S_Msk (1ul << MPU_RASR_S_Pos) /*!< MPU RASR: Shareable bit Mask */\r
-\r
-#define MPU_RASR_C_Pos 17 /*!< MPU RASR: Cacheable bit Position */\r
-#define MPU_RASR_C_Msk (1ul << MPU_RASR_C_Pos) /*!< MPU RASR: Cacheable bit Mask */\r
-\r
-#define MPU_RASR_B_Pos 16 /*!< MPU RASR: Bufferable bit Position */\r
-#define MPU_RASR_B_Msk (1ul << MPU_RASR_B_Pos) /*!< MPU RASR: Bufferable bit Mask */\r
-\r
-#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */\r
-#define MPU_RASR_SRD_Msk (0xFFul << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */\r
-\r
-#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */\r
-#define MPU_RASR_SIZE_Msk (0x1Ful << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */\r
-\r
-#define MPU_RASR_ENA_Pos 0 /*!< MPU RASR: Region enable bit Position */\r
-#define MPU_RASR_ENA_Msk (0x1Ful << MPU_RASR_ENA_Pos) /*!< MPU RASR: Region enable bit Disable Mask */\r
-\r
-/*@}*/ /* end of group CMSIS_CM3_MPU */\r
-#endif\r
-\r
-\r
-/** @addtogroup CMSIS_CM3_CoreDebug CMSIS CM3 Core Debug\r
- memory mapped structure for Core Debug Register\r
- @{\r
- */\r
-typedef struct\r
-{\r
- __IO uint32_t DHCSR; /*!< Offset: 0x00 Debug Halting Control and Status Register */\r
- __O uint32_t DCRSR; /*!< Offset: 0x04 Debug Core Register Selector Register */\r
- __IO uint32_t DCRDR; /*!< Offset: 0x08 Debug Core Register Data Register */\r
- __IO uint32_t DEMCR; /*!< Offset: 0x0C Debug Exception and Monitor Control Register */\r
-} CoreDebug_Type;\r
-\r
-/* Debug Halting Control and Status Register */\r
-#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */\r
-#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFul << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */\r
-\r
-#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */\r
-#define CoreDebug_DHCSR_S_RESET_ST_Msk (1ul << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */\r
-\r
-#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */\r
-#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1ul << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */\r
-\r
-#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */\r
-#define CoreDebug_DHCSR_S_LOCKUP_Msk (1ul << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */\r
-\r
-#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */\r
-#define CoreDebug_DHCSR_S_SLEEP_Msk (1ul << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */\r
-\r
-#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */\r
-#define CoreDebug_DHCSR_S_HALT_Msk (1ul << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */\r
-\r
-#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */\r
-#define CoreDebug_DHCSR_S_REGRDY_Msk (1ul << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */\r
-\r
-#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */\r
-#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1ul << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */\r
-\r
-#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */\r
-#define CoreDebug_DHCSR_C_MASKINTS_Msk (1ul << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */\r
-\r
-#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */\r
-#define CoreDebug_DHCSR_C_STEP_Msk (1ul << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */\r
-\r
-#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */\r
-#define CoreDebug_DHCSR_C_HALT_Msk (1ul << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */\r
-\r
-#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */\r
-#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1ul << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */\r
-\r
-/* Debug Core Register Selector Register */\r
-#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */\r
-#define CoreDebug_DCRSR_REGWnR_Msk (1ul << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */\r
-\r
-#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */\r
-#define CoreDebug_DCRSR_REGSEL_Msk (0x1Ful << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */\r
-\r
-/* Debug Exception and Monitor Control Register */\r
-#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */\r
-#define CoreDebug_DEMCR_TRCENA_Msk (1ul << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */\r
-\r
-#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */\r
-#define CoreDebug_DEMCR_MON_REQ_Msk (1ul << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */\r
-\r
-#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */\r
-#define CoreDebug_DEMCR_MON_STEP_Msk (1ul << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */\r
-\r
-#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */\r
-#define CoreDebug_DEMCR_MON_PEND_Msk (1ul << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */\r
-\r
-#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */\r
-#define CoreDebug_DEMCR_MON_EN_Msk (1ul << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */\r
-#define CoreDebug_DEMCR_VC_HARDERR_Msk (1ul << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */\r
-#define CoreDebug_DEMCR_VC_INTERR_Msk (1ul << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */\r
-#define CoreDebug_DEMCR_VC_BUSERR_Msk (1ul << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */\r
-#define CoreDebug_DEMCR_VC_STATERR_Msk (1ul << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */\r
-#define CoreDebug_DEMCR_VC_CHKERR_Msk (1ul << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */\r
-#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1ul << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */\r
-#define CoreDebug_DEMCR_VC_MMERR_Msk (1ul << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */\r
-#define CoreDebug_DEMCR_VC_CORERESET_Msk (1ul << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */\r
-/*@}*/ /* end of group CMSIS_CM3_CoreDebug */\r
-\r
-\r
-/* Memory mapping of Cortex-M3 Hardware */\r
-#define SCS_BASE (0xE000E000) /*!< System Control Space Base Address */\r
-#define ITM_BASE (0xE0000000) /*!< ITM Base Address */\r
-#define CoreDebug_BASE (0xE000EDF0) /*!< Core Debug Base Address */\r
-#define SysTick_BASE (SCS_BASE + 0x0010) /*!< SysTick Base Address */\r
-#define NVIC_BASE (SCS_BASE + 0x0100) /*!< NVIC Base Address */\r
-#define SCB_BASE (SCS_BASE + 0x0D00) /*!< System Control Block Base Address */\r
-\r
-#define InterruptType ((InterruptType_Type *) SCS_BASE) /*!< Interrupt Type Register */\r
-#define SCB ((SCB_Type *) SCB_BASE) /*!< SCB configuration struct */\r
-#define SysTick ((SysTick_Type *) SysTick_BASE) /*!< SysTick configuration struct */\r
-#define NVIC ((NVIC_Type *) NVIC_BASE) /*!< NVIC configuration struct */\r
-#define ITM ((ITM_Type *) ITM_BASE) /*!< ITM configuration struct */\r
-#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */\r
-\r
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1)\r
- #define MPU_BASE (SCS_BASE + 0x0D90) /*!< Memory Protection Unit */\r
- #define MPU ((MPU_Type*) MPU_BASE) /*!< Memory Protection Unit */\r
-#endif\r
-\r
-/*@}*/ /* end of group CMSIS_CM3_core_register */\r
-\r
-\r
-/*******************************************************************************\r
- * Hardware Abstraction Layer\r
- ******************************************************************************/\r
-\r
-#if defined ( __CC_ARM )\r
- #define __ASM __asm /*!< asm keyword for ARM Compiler */\r
- #define __INLINE __inline /*!< inline keyword for ARM Compiler */\r
-\r
-#elif defined ( __ICCARM__ )\r
- #define __ASM __asm /*!< asm keyword for IAR Compiler */\r
- #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */\r
-\r
-#elif defined ( __GNUC__ )\r
- #define __ASM __asm /*!< asm keyword for GNU Compiler */\r
- #define __INLINE inline /*!< inline keyword for GNU Compiler */\r
-\r
-#elif defined ( __TASKING__ )\r
- #define __ASM __asm /*!< asm keyword for TASKING Compiler */\r
- #define __INLINE inline /*!< inline keyword for TASKING Compiler */\r
-\r
-#endif\r
-\r
-\r
-/* ################### Compiler specific Intrinsics ########################### */\r
-\r
-#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/\r
-/* ARM armcc specific functions */\r
-\r
-#define __enable_fault_irq __enable_fiq\r
-#define __disable_fault_irq __disable_fiq\r
-\r
-#define __NOP __nop\r
-#define __WFI __wfi\r
-#define __WFE __wfe\r
-#define __SEV __sev\r
-#define __ISB() __isb(0)\r
-#define __DSB() __dsb(0)\r
-#define __DMB() __dmb(0)\r
-#define __REV __rev\r
-#define __RBIT __rbit\r
-#define __LDREXB(ptr) ((unsigned char ) __ldrex(ptr))\r
-#define __LDREXH(ptr) ((unsigned short) __ldrex(ptr))\r
-#define __LDREXW(ptr) ((unsigned int ) __ldrex(ptr))\r
-#define __STREXB(value, ptr) __strex(value, ptr)\r
-#define __STREXH(value, ptr) __strex(value, ptr)\r
-#define __STREXW(value, ptr) __strex(value, ptr)\r
-\r
-\r
-/* intrinsic unsigned long long __ldrexd(volatile void *ptr) */\r
-/* intrinsic int __strexd(unsigned long long val, volatile void *ptr) */\r
-/* intrinsic void __enable_irq(); */\r
-/* intrinsic void __disable_irq(); */\r
-\r
-\r
-/**\r
- * @brief Return the Process Stack Pointer\r
- *\r
- * @return ProcessStackPointer\r
- *\r
- * Return the actual process stack pointer\r
- */\r
-extern uint32_t __get_PSP(void);\r
-\r
-/**\r
- * @brief Set the Process Stack Pointer\r
- *\r
- * @param topOfProcStack Process Stack Pointer\r
- *\r
- * Assign the value ProcessStackPointer to the MSP\r
- * (process stack pointer) Cortex processor register\r
- */\r
-extern void __set_PSP(uint32_t topOfProcStack);\r
-\r
-/**\r
- * @brief Return the Main Stack Pointer\r
- *\r
- * @return Main Stack Pointer\r
- *\r
- * Return the current value of the MSP (main stack pointer)\r
- * Cortex processor register\r
- */\r
-extern uint32_t __get_MSP(void);\r
-\r
-/**\r
- * @brief Set the Main Stack Pointer\r
- *\r
- * @param topOfMainStack Main Stack Pointer\r
- *\r
- * Assign the value mainStackPointer to the MSP\r
- * (main stack pointer) Cortex processor register\r
- */\r
-extern void __set_MSP(uint32_t topOfMainStack);\r
-\r
-/**\r
- * @brief Reverse byte order in unsigned short value\r
- *\r
- * @param value value to reverse\r
- * @return reversed value\r
- *\r
- * Reverse byte order in unsigned short value\r
- */\r
-extern uint32_t __REV16(uint16_t value);\r
-\r
-/**\r
- * @brief Reverse byte order in signed short value with sign extension to integer\r
- *\r
- * @param value value to reverse\r
- * @return reversed value\r
- *\r
- * Reverse byte order in signed short value with sign extension to integer\r
- */\r
-extern int32_t __REVSH(int16_t value);\r
-\r
-\r
-#if (__ARMCC_VERSION < 400000)\r
-\r
-/**\r
- * @brief Remove the exclusive lock created by ldrex\r
- *\r
- * Removes the exclusive lock which is created by ldrex.\r
- */\r
-extern void __CLREX(void);\r
-\r
-/**\r
- * @brief Return the Base Priority value\r
- *\r
- * @return BasePriority\r
- *\r
- * Return the content of the base priority register\r
- */\r
-extern uint32_t __get_BASEPRI(void);\r
-\r
-/**\r
- * @brief Set the Base Priority value\r
- *\r
- * @param basePri BasePriority\r
- *\r
- * Set the base priority register\r
- */\r
-extern void __set_BASEPRI(uint32_t basePri);\r
-\r
-/**\r
- * @brief Return the Priority Mask value\r
- *\r
- * @return PriMask\r
- *\r
- * Return state of the priority mask bit from the priority mask register\r
- */\r
-extern uint32_t __get_PRIMASK(void);\r
-\r
-/**\r
- * @brief Set the Priority Mask value\r
- *\r
- * @param priMask PriMask\r
- *\r
- * Set the priority mask bit in the priority mask register\r
- */\r
-extern void __set_PRIMASK(uint32_t priMask);\r
-\r
-/**\r
- * @brief Return the Fault Mask value\r
- *\r
- * @return FaultMask\r
- *\r
- * Return the content of the fault mask register\r
- */\r
-extern uint32_t __get_FAULTMASK(void);\r
-\r
-/**\r
- * @brief Set the Fault Mask value\r
- *\r
- * @param faultMask faultMask value\r
- *\r
- * Set the fault mask register\r
- */\r
-extern void __set_FAULTMASK(uint32_t faultMask);\r
-\r
-/**\r
- * @brief Return the Control Register value\r
- *\r
- * @return Control value\r
- *\r
- * Return the content of the control register\r
- */\r
-extern uint32_t __get_CONTROL(void);\r
-\r
-/**\r
- * @brief Set the Control Register value\r
- *\r
- * @param control Control value\r
- *\r
- * Set the control register\r
- */\r
-extern void __set_CONTROL(uint32_t control);\r
-\r
-#else /* (__ARMCC_VERSION >= 400000) */\r
-\r
-/**\r
- * @brief Remove the exclusive lock created by ldrex\r
- *\r
- * Removes the exclusive lock which is created by ldrex.\r
- */\r
-#define __CLREX __clrex\r
-\r
-/**\r
- * @brief Return the Base Priority value\r
- *\r
- * @return BasePriority\r
- *\r
- * Return the content of the base priority register\r
- */\r
-static __INLINE uint32_t __get_BASEPRI(void)\r
-{\r
- register uint32_t __regBasePri __ASM("basepri");\r
- return(__regBasePri);\r
-}\r
-\r
-/**\r
- * @brief Set the Base Priority value\r
- *\r
- * @param basePri BasePriority\r
- *\r
- * Set the base priority register\r
- */\r
-static __INLINE void __set_BASEPRI(uint32_t basePri)\r
-{\r
- register uint32_t __regBasePri __ASM("basepri");\r
- __regBasePri = (basePri & 0xff);\r
-}\r
-\r
-/**\r
- * @brief Return the Priority Mask value\r
- *\r
- * @return PriMask\r
- *\r
- * Return state of the priority mask bit from the priority mask register\r
- */\r
-static __INLINE uint32_t __get_PRIMASK(void)\r
-{\r
- register uint32_t __regPriMask __ASM("primask");\r
- return(__regPriMask);\r
-}\r
-\r
-/**\r
- * @brief Set the Priority Mask value\r
- *\r
- * @param priMask PriMask\r
- *\r
- * Set the priority mask bit in the priority mask register\r
- */\r
-static __INLINE void __set_PRIMASK(uint32_t priMask)\r
-{\r
- register uint32_t __regPriMask __ASM("primask");\r
- __regPriMask = (priMask);\r
-}\r
-\r
-/**\r
- * @brief Return the Fault Mask value\r
- *\r
- * @return FaultMask\r
- *\r
- * Return the content of the fault mask register\r
- */\r
-static __INLINE uint32_t __get_FAULTMASK(void)\r
-{\r
- register uint32_t __regFaultMask __ASM("faultmask");\r
- return(__regFaultMask);\r
-}\r
-\r
-/**\r
- * @brief Set the Fault Mask value\r
- *\r
- * @param faultMask faultMask value\r
- *\r
- * Set the fault mask register\r
- */\r
-static __INLINE void __set_FAULTMASK(uint32_t faultMask)\r
-{\r
- register uint32_t __regFaultMask __ASM("faultmask");\r
- __regFaultMask = (faultMask & 1);\r
-}\r
-\r
-/**\r
- * @brief Return the Control Register value\r
- *\r
- * @return Control value\r
- *\r
- * Return the content of the control register\r
- */\r
-static __INLINE uint32_t __get_CONTROL(void)\r
-{\r
- register uint32_t __regControl __ASM("control");\r
- return(__regControl);\r
-}\r
-\r
-/**\r
- * @brief Set the Control Register value\r
- *\r
- * @param control Control value\r
- *\r
- * Set the control register\r
- */\r
-static __INLINE void __set_CONTROL(uint32_t control)\r
-{\r
- register uint32_t __regControl __ASM("control");\r
- __regControl = control;\r
-}\r
-\r
-#endif /* __ARMCC_VERSION */\r
-\r
-\r
-\r
-#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/\r
-/* IAR iccarm specific functions */\r
-\r
-#define __enable_irq __enable_interrupt /*!< global Interrupt enable */\r
-#define __disable_irq __disable_interrupt /*!< global Interrupt disable */\r
-\r
-static __INLINE void __enable_fault_irq() { __ASM ("cpsie f"); }\r
-static __INLINE void __disable_fault_irq() { __ASM ("cpsid f"); }\r
-\r
-#define __NOP __no_operation /*!< no operation intrinsic in IAR Compiler */\r
-static __INLINE void __WFI() { __ASM ("wfi"); }\r
-static __INLINE void __WFE() { __ASM ("wfe"); }\r
-static __INLINE void __SEV() { __ASM ("sev"); }\r
-static __INLINE void __CLREX() { __ASM ("clrex"); }\r
-\r
-/* intrinsic void __ISB(void) */\r
-/* intrinsic void __DSB(void) */\r
-/* intrinsic void __DMB(void) */\r
-/* intrinsic void __set_PRIMASK(); */\r
-/* intrinsic void __get_PRIMASK(); */\r
-/* intrinsic void __set_FAULTMASK(); */\r
-/* intrinsic void __get_FAULTMASK(); */\r
-/* intrinsic uint32_t __REV(uint32_t value); */\r
-/* intrinsic uint32_t __REVSH(uint32_t value); */\r
-/* intrinsic unsigned long __STREX(unsigned long, unsigned long); */\r
-/* intrinsic unsigned long __LDREX(unsigned long *); */\r
-\r
-\r
-/**\r
- * @brief Return the Process Stack Pointer\r
- *\r
- * @return ProcessStackPointer\r
- *\r
- * Return the actual process stack pointer\r
- */\r
-extern uint32_t __get_PSP(void);\r
-\r
-/**\r
- * @brief Set the Process Stack Pointer\r
- *\r
- * @param topOfProcStack Process Stack Pointer\r
- *\r
- * Assign the value ProcessStackPointer to the MSP\r
- * (process stack pointer) Cortex processor register\r
- */\r
-extern void __set_PSP(uint32_t topOfProcStack);\r
-\r
-/**\r
- * @brief Return the Main Stack Pointer\r
- *\r
- * @return Main Stack Pointer\r
- *\r
- * Return the current value of the MSP (main stack pointer)\r
- * Cortex processor register\r
- */\r
-extern uint32_t __get_MSP(void);\r
-\r
-/**\r
- * @brief Set the Main Stack Pointer\r
- *\r
- * @param topOfMainStack Main Stack Pointer\r
- *\r
- * Assign the value mainStackPointer to the MSP\r
- * (main stack pointer) Cortex processor register\r
- */\r
-extern void __set_MSP(uint32_t topOfMainStack);\r
-\r
-/**\r
- * @brief Reverse byte order in unsigned short value\r
- *\r
- * @param value value to reverse\r
- * @return reversed value\r
- *\r
- * Reverse byte order in unsigned short value\r
- */\r
-extern uint32_t __REV16(uint16_t value);\r
-\r
-/**\r
- * @brief Reverse bit order of value\r
- *\r
- * @param value value to reverse\r
- * @return reversed value\r
- *\r
- * Reverse bit order of value\r
- */\r
-extern uint32_t __RBIT(uint32_t value);\r
-\r
-/**\r
- * @brief LDR Exclusive (8 bit)\r
- *\r
- * @param *addr address pointer\r
- * @return value of (*address)\r
- *\r
- * Exclusive LDR command for 8 bit values)\r
- */\r
-extern uint8_t __LDREXB(uint8_t *addr);\r
-\r
-/**\r
- * @brief LDR Exclusive (16 bit)\r
- *\r
- * @param *addr address pointer\r
- * @return value of (*address)\r
- *\r
- * Exclusive LDR command for 16 bit values\r
- */\r
-extern uint16_t __LDREXH(uint16_t *addr);\r
-\r
-/**\r
- * @brief LDR Exclusive (32 bit)\r
- *\r
- * @param *addr address pointer\r
- * @return value of (*address)\r
- *\r
- * Exclusive LDR command for 32 bit values\r
- */\r
-extern uint32_t __LDREXW(uint32_t *addr);\r
-\r
-/**\r
- * @brief STR Exclusive (8 bit)\r
- *\r
- * @param value value to store\r
- * @param *addr address pointer\r
- * @return successful / failed\r
- *\r
- * Exclusive STR command for 8 bit values\r
- */\r
-extern uint32_t __STREXB(uint8_t value, uint8_t *addr);\r
-\r
-/**\r
- * @brief STR Exclusive (16 bit)\r
- *\r
- * @param value value to store\r
- * @param *addr address pointer\r
- * @return successful / failed\r
- *\r
- * Exclusive STR command for 16 bit values\r
- */\r
-extern uint32_t __STREXH(uint16_t value, uint16_t *addr);\r
-\r
-/**\r
- * @brief STR Exclusive (32 bit)\r
- *\r
- * @param value value to store\r
- * @param *addr address pointer\r
- * @return successful / failed\r
- *\r
- * Exclusive STR command for 32 bit values\r
- */\r
-extern uint32_t __STREXW(uint32_t value, uint32_t *addr);\r
-\r
-\r
-\r
-#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/\r
-/* GNU gcc specific functions */\r
-\r
-static __INLINE void __enable_irq() { __ASM volatile ("cpsie i"); }\r
-static __INLINE void __disable_irq() { __ASM volatile ("cpsid i"); }\r
-\r
-static __INLINE void __enable_fault_irq() { __ASM volatile ("cpsie f"); }\r
-static __INLINE void __disable_fault_irq() { __ASM volatile ("cpsid f"); }\r
-\r
-static __INLINE void __NOP() { __ASM volatile ("nop"); }\r
-static __INLINE void __WFI() { __ASM volatile ("wfi"); }\r
-static __INLINE void __WFE() { __ASM volatile ("wfe"); }\r
-static __INLINE void __SEV() { __ASM volatile ("sev"); }\r
-static __INLINE void __ISB() { __ASM volatile ("isb"); }\r
-static __INLINE void __DSB() { __ASM volatile ("dsb"); }\r
-static __INLINE void __DMB() { __ASM volatile ("dmb"); }\r
-static __INLINE void __CLREX() { __ASM volatile ("clrex"); }\r
-\r
-\r
-/**\r
- * @brief Return the Process Stack Pointer\r
- *\r
- * @return ProcessStackPointer\r
- *\r
- * Return the actual process stack pointer\r
- */\r
-extern uint32_t __get_PSP(void);\r
-\r
-/**\r
- * @brief Set the Process Stack Pointer\r
- *\r
- * @param topOfProcStack Process Stack Pointer\r
- *\r
- * Assign the value ProcessStackPointer to the MSP\r
- * (process stack pointer) Cortex processor register\r
- */\r
-extern void __set_PSP(uint32_t topOfProcStack);\r
-\r
-/**\r
- * @brief Return the Main Stack Pointer\r
- *\r
- * @return Main Stack Pointer\r
- *\r
- * Return the current value of the MSP (main stack pointer)\r
- * Cortex processor register\r
- */\r
-extern uint32_t __get_MSP(void);\r
-\r
-/**\r
- * @brief Set the Main Stack Pointer\r
- *\r
- * @param topOfMainStack Main Stack Pointer\r
- *\r
- * Assign the value mainStackPointer to the MSP\r
- * (main stack pointer) Cortex processor register\r
- */\r
-extern void __set_MSP(uint32_t topOfMainStack);\r
-\r
-/**\r
- * @brief Return the Base Priority value\r
- *\r
- * @return BasePriority\r
- *\r
- * Return the content of the base priority register\r
- */\r
-extern uint32_t __get_BASEPRI(void);\r
-\r
-/**\r
- * @brief Set the Base Priority value\r
- *\r
- * @param basePri BasePriority\r
- *\r
- * Set the base priority register\r
- */\r
-extern void __set_BASEPRI(uint32_t basePri);\r
-\r
-/**\r
- * @brief Return the Priority Mask value\r
- *\r
- * @return PriMask\r
- *\r
- * Return state of the priority mask bit from the priority mask register\r
- */\r
-extern uint32_t __get_PRIMASK(void);\r
-\r
-/**\r
- * @brief Set the Priority Mask value\r
- *\r
- * @param priMask PriMask\r
- *\r
- * Set the priority mask bit in the priority mask register\r
- */\r
-extern void __set_PRIMASK(uint32_t priMask);\r
-\r
-/**\r
- * @brief Return the Fault Mask value\r
- *\r
- * @return FaultMask\r
- *\r
- * Return the content of the fault mask register\r
- */\r
-extern uint32_t __get_FAULTMASK(void);\r
-\r
-/**\r
- * @brief Set the Fault Mask value\r
- *\r
- * @param faultMask faultMask value\r
- *\r
- * Set the fault mask register\r
- */\r
-extern void __set_FAULTMASK(uint32_t faultMask);\r
-\r
-/**\r
- * @brief Return the Control Register value\r
-*\r
-* @return Control value\r
- *\r
- * Return the content of the control register\r
- */\r
-extern uint32_t __get_CONTROL(void);\r
-\r
-/**\r
- * @brief Set the Control Register value\r
- *\r
- * @param control Control value\r
- *\r
- * Set the control register\r
- */\r
-extern void __set_CONTROL(uint32_t control);\r
-\r
-/**\r
- * @brief Reverse byte order in integer value\r
- *\r
- * @param value value to reverse\r
- * @return reversed value\r
- *\r
- * Reverse byte order in integer value\r
- */\r
-extern uint32_t __REV(uint32_t value);\r
-\r
-/**\r
- * @brief Reverse byte order in unsigned short value\r
- *\r
- * @param value value to reverse\r
- * @return reversed value\r
- *\r
- * Reverse byte order in unsigned short value\r
- */\r
-extern uint32_t __REV16(uint16_t value);\r
-\r
-/**\r
- * @brief Reverse byte order in signed short value with sign extension to integer\r
- *\r
- * @param value value to reverse\r
- * @return reversed value\r
- *\r
- * Reverse byte order in signed short value with sign extension to integer\r
- */\r
-extern int32_t __REVSH(int16_t value);\r
-\r
-/**\r
- * @brief Reverse bit order of value\r
- *\r
- * @param value value to reverse\r
- * @return reversed value\r
- *\r
- * Reverse bit order of value\r
- */\r
-extern uint32_t __RBIT(uint32_t value);\r
-\r
-/**\r
- * @brief LDR Exclusive (8 bit)\r
- *\r
- * @param *addr address pointer\r
- * @return value of (*address)\r
- *\r
- * Exclusive LDR command for 8 bit value\r
- */\r
-extern uint8_t __LDREXB(uint8_t *addr);\r
-\r
-/**\r
- * @brief LDR Exclusive (16 bit)\r
- *\r
- * @param *addr address pointer\r
- * @return value of (*address)\r
- *\r
- * Exclusive LDR command for 16 bit values\r
- */\r
-extern uint16_t __LDREXH(uint16_t *addr);\r
-\r
-/**\r
- * @brief LDR Exclusive (32 bit)\r
- *\r
- * @param *addr address pointer\r
- * @return value of (*address)\r
- *\r
- * Exclusive LDR command for 32 bit values\r
- */\r
-extern uint32_t __LDREXW(uint32_t *addr);\r
-\r
-/**\r
- * @brief STR Exclusive (8 bit)\r
- *\r
- * @param value value to store\r
- * @param *addr address pointer\r
- * @return successful / failed\r
- *\r
- * Exclusive STR command for 8 bit values\r
- */\r
-extern uint32_t __STREXB(uint8_t value, uint8_t *addr);\r
-\r
-/**\r
- * @brief STR Exclusive (16 bit)\r
- *\r
- * @param value value to store\r
- * @param *addr address pointer\r
- * @return successful / failed\r
- *\r
- * Exclusive STR command for 16 bit values\r
- */\r
-extern uint32_t __STREXH(uint16_t value, uint16_t *addr);\r
-\r
-/**\r
- * @brief STR Exclusive (32 bit)\r
- *\r
- * @param value value to store\r
- * @param *addr address pointer\r
- * @return successful / failed\r
- *\r
- * Exclusive STR command for 32 bit values\r
- */\r
-extern uint32_t __STREXW(uint32_t value, uint32_t *addr);\r
-\r
-\r
-#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/\r
-/* TASKING carm specific functions */\r
-\r
-/*\r
- * The CMSIS functions have been implemented as intrinsics in the compiler.\r
- * Please use "carm -?i" to get an up to date list of all instrinsics,\r
- * Including the CMSIS ones.\r
- */\r
-\r
-#endif\r
-\r
-\r
-/** @addtogroup CMSIS_CM3_Core_FunctionInterface CMSIS CM3 Core Function Interface\r
- Core Function Interface containing:\r
- - Core NVIC Functions\r
- - Core SysTick Functions\r
- - Core Reset Functions\r
-*/\r
-/*@{*/\r
-\r
-/* ########################## NVIC functions #################################### */\r
-\r
-/**\r
- * @brief Set the Priority Grouping in NVIC Interrupt Controller\r
- *\r
- * @param PriorityGroup is priority grouping field\r
- *\r
- * Set the priority grouping field using the required unlock sequence.\r
- * The parameter priority_grouping is assigned to the field\r
- * SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used.\r
- * In case of a conflict between priority grouping and available\r
- * priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\r
- */\r
-static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)\r
-{\r
- uint32_t reg_value;\r
- uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */\r
-\r
- reg_value = SCB->AIRCR; /* read old register configuration */\r
- reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */\r
- reg_value = (reg_value |\r
- (0x5FA << SCB_AIRCR_VECTKEY_Pos) |\r
- (PriorityGroupTmp << 8)); /* Insert write key and priorty group */\r
- SCB->AIRCR = reg_value;\r
-}\r
-\r
-/**\r
- * @brief Get the Priority Grouping from NVIC Interrupt Controller\r
- *\r
- * @return priority grouping field\r
- *\r
- * Get the priority grouping from NVIC Interrupt Controller.\r
- * priority grouping is SCB->AIRCR [10:8] PRIGROUP field.\r
- */\r
-static __INLINE uint32_t NVIC_GetPriorityGrouping(void)\r
-{\r
- return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */\r
-}\r
-\r
-/**\r
- * @brief Enable Interrupt in NVIC Interrupt Controller\r
- *\r
- * @param IRQn The positive number of the external interrupt to enable\r
- *\r
- * Enable a device specific interupt in the NVIC interrupt controller.\r
- * The interrupt number cannot be a negative value.\r
- */\r
-static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)\r
-{\r
- NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */\r
-}\r
-\r
-/**\r
- * @brief Disable the interrupt line for external interrupt specified\r
- *\r
- * @param IRQn The positive number of the external interrupt to disable\r
- *\r
- * Disable a device specific interupt in the NVIC interrupt controller.\r
- * The interrupt number cannot be a negative value.\r
- */\r
-static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)\r
-{\r
- NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */\r
-}\r
-\r
-/**\r
- * @brief Read the interrupt pending bit for a device specific interrupt source\r
- *\r
- * @param IRQn The number of the device specifc interrupt\r
- * @return 1 = interrupt pending, 0 = interrupt not pending\r
- *\r
- * Read the pending register in NVIC and return 1 if its status is pending,\r
- * otherwise it returns 0\r
- */\r
-static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
-{\r
- return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */\r
-}\r
-\r
-/**\r
- * @brief Set the pending bit for an external interrupt\r
- *\r
- * @param IRQn The number of the interrupt for set pending\r
- *\r
- * Set the pending bit for the specified interrupt.\r
- * The interrupt number cannot be a negative value.\r
- */\r
-static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
-{\r
- NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */\r
-}\r
-\r
-/**\r
- * @brief Clear the pending bit for an external interrupt\r
- *\r
- * @param IRQn The number of the interrupt for clear pending\r
- *\r
- * Clear the pending bit for the specified interrupt.\r
- * The interrupt number cannot be a negative value.\r
- */\r
-static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
-{\r
- NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */\r
-}\r
-\r
-/**\r
- * @brief Read the active bit for an external interrupt\r
- *\r
- * @param IRQn The number of the interrupt for read active bit\r
- * @return 1 = interrupt active, 0 = interrupt not active\r
- *\r
- * Read the active register in NVIC and returns 1 if its status is active,\r
- * otherwise it returns 0.\r
- */\r
-static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)\r
-{\r
- return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */\r
-}\r
-\r
-/**\r
- * @brief Set the priority for an interrupt\r
- *\r
- * @param IRQn The number of the interrupt for set priority\r
- * @param priority The priority to set\r
- *\r
- * Set the priority for the specified interrupt. The interrupt\r
- * number can be positive to specify an external (device specific)\r
- * interrupt, or negative to specify an internal (core) interrupt.\r
- *\r
- * Note: The priority cannot be set for every core interrupt.\r
- */\r
-static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r
-{\r
- if(IRQn < 0) {\r
- SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M3 System Interrupts */\r
- else {\r
- NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */\r
-}\r
-\r
-/**\r
- * @brief Read the priority for an interrupt\r
- *\r
- * @param IRQn The number of the interrupt for get priority\r
- * @return The priority for the interrupt\r
- *\r
- * Read the priority for the specified interrupt. The interrupt\r
- * number can be positive to specify an external (device specific)\r
- * interrupt, or negative to specify an internal (core) interrupt.\r
- *\r
- * The returned priority value is automatically aligned to the implemented\r
- * priority bits of the microcontroller.\r
- *\r
- * Note: The priority cannot be set for every core interrupt.\r
- */\r
-static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)\r
-{\r
-\r
- if(IRQn < 0) {\r
- return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M3 system interrupts */\r
- else {\r
- return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */\r
-}\r
-\r
-\r
-/**\r
- * @brief Encode the priority for an interrupt\r
- *\r
- * @param PriorityGroup The used priority group\r
- * @param PreemptPriority The preemptive priority value (starting from 0)\r
- * @param SubPriority The sub priority value (starting from 0)\r
- * @return The encoded priority for the interrupt\r
- *\r
- * Encode the priority for an interrupt with the given priority group,\r
- * preemptive priority value and sub priority value.\r
- * In case of a conflict between priority grouping and available\r
- * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.\r
- *\r
- * The returned priority value can be used for NVIC_SetPriority(...) function\r
- */\r
-static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\r
-{\r
- uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */\r
- uint32_t PreemptPriorityBits;\r
- uint32_t SubPriorityBits;\r
-\r
- PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;\r
- SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;\r
-\r
- return (\r
- ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |\r
- ((SubPriority & ((1 << (SubPriorityBits )) - 1)))\r
- );\r
-}\r
-\r
-\r
-/**\r
- * @brief Decode the priority of an interrupt\r
- *\r
- * @param Priority The priority for the interrupt\r
- * @param PriorityGroup The used priority group\r
- * @param pPreemptPriority The preemptive priority value (starting from 0)\r
- * @param pSubPriority The sub priority value (starting from 0)\r
- *\r
- * Decode an interrupt priority value with the given priority group to\r
- * preemptive priority value and sub priority value.\r
- * In case of a conflict between priority grouping and available\r
- * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.\r
- *\r
- * The priority value can be retrieved with NVIC_GetPriority(...) function\r
- */\r
-static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)\r
-{\r
- uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */\r
- uint32_t PreemptPriorityBits;\r
- uint32_t SubPriorityBits;\r
-\r
- PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;\r
- SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;\r
-\r
- *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);\r
- *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);\r
-}\r
-\r
-\r
-\r
-/* ################################## SysTick function ############################################ */\r
-\r
-#if (!defined (__Vendor_SysTickConfig)) || (__Vendor_SysTickConfig == 0)\r
-\r
-/**\r
- * @brief Initialize and start the SysTick counter and its interrupt.\r
- *\r
- * @param ticks number of ticks between two interrupts\r
- * @return 1 = failed, 0 = successful\r
- *\r
- * Initialise the system tick timer and its interrupt and start the\r
- * system tick timer / counter in free running mode to generate\r
- * periodical interrupts.\r
- */\r
-static __INLINE uint32_t SysTick_Config(uint32_t ticks)\r
-{\r
- if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */\r
-\r
- SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */\r
- NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */\r
- SysTick->VAL = 0; /* Load the SysTick Counter Value */\r
- SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
- SysTick_CTRL_TICKINT_Msk |\r
- SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
- return (0); /* Function successful */\r
-}\r
-\r
-#endif\r
-\r
-\r
-\r
-\r
-/* ################################## Reset function ############################################ */\r
-\r
-/**\r
- * @brief Initiate a system reset request.\r
- *\r
- * Initiate a system reset request to reset the MCU\r
- */\r
-static __INLINE void NVIC_SystemReset(void)\r
-{\r
- SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |\r
- (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |\r
- SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */\r
- __DSB(); /* Ensure completion of memory access */\r
- while(1); /* wait until reset */\r
-}\r
-\r
-/*@}*/ /* end of group CMSIS_CM3_Core_FunctionInterface */\r
-\r
-\r
-\r
-/* ##################################### Debug In/Output function ########################################### */\r
-\r
-/** @addtogroup CMSIS_CM3_CoreDebugInterface CMSIS CM3 Core Debug Interface\r
- Core Debug Interface containing:\r
- - Core Debug Receive / Transmit Functions\r
- - Core Debug Defines\r
- - Core Debug Variables\r
-*/\r
-/*@{*/\r
-\r
-extern volatile int ITM_RxBuffer; /*!< variable to receive characters */\r
-#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< value identifying ITM_RxBuffer is ready for next character */\r
-\r
-\r
-/**\r
- * @brief Outputs a character via the ITM channel 0\r
- *\r
- * @param ch character to output\r
- * @return character to output\r
- *\r
- * The function outputs a character via the ITM channel 0.\r
- * The function returns when no debugger is connected that has booked the output.\r
- * It is blocking when a debugger is connected, but the previous character send is not transmitted.\r
- */\r
-static __INLINE uint32_t ITM_SendChar (uint32_t ch)\r
-{\r
- if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk) && /* Trace enabled */\r
- (ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */\r
- (ITM->TER & (1ul << 0) ) ) /* ITM Port #0 enabled */\r
- {\r
- while (ITM->PORT[0].u32 == 0);\r
- ITM->PORT[0].u8 = (uint8_t) ch;\r
- }\r
- return (ch);\r
-}\r
-\r
-\r
-/**\r
- * @brief Inputs a character via variable ITM_RxBuffer\r
- *\r
- * @return received character, -1 = no character received\r
- *\r
- * The function inputs a character via variable ITM_RxBuffer.\r
- * The function returns when no debugger is connected that has booked the output.\r
- * It is blocking when a debugger is connected, but the previous character send is not transmitted.\r
- */\r
-static __INLINE int ITM_ReceiveChar (void) {\r
- int ch = -1; /* no character available */\r
-\r
- if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {\r
- ch = ITM_RxBuffer;\r
- ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */\r
- }\r
-\r
- return (ch);\r
-}\r
-\r
-\r
-/**\r
- * @brief Check if a character via variable ITM_RxBuffer is available\r
- *\r
- * @return 1 = character available, 0 = no character available\r
- *\r
- * The function checks variable ITM_RxBuffer whether a character is available or not.\r
- * The function returns '1' if a character is available and '0' if no character is available.\r
- */\r
-static __INLINE int ITM_CheckChar (void) {\r
-\r
- if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {\r
- return (0); /* no character available */\r
- } else {\r
- return (1); /* character available */\r
- }\r
-}\r
-\r
-/*@}*/ /* end of group CMSIS_CM3_core_DebugInterface */\r
-\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-/*@}*/ /* end of group CMSIS_CM3_core_definitions */\r
-\r
-#endif /* __CM3_CORE_H__ */\r
-\r
-/*lint -restore */\r
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