Clarify what exactly the RISC-V code supports.

Change-Id: I8da657426cc52c738ab41bfb0164cbc6721c0aef
Signed-off-by: Tim Newsome <tim@sifive.com>
Reviewed-on: http://openocd.zylin.com/4655
Tested-by: jenkins
Reviewed-by: Philipp Guehring <pg@futureware.at>
Reviewed-by: Liviu Ionescu <ilg@livius.net>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>

diff --git a/doc/openocd.texi b/doc/openocd.texi
index e87d8c2967507b933bfa917c7fe581ef3da02eb6..bbe6cffd4df533965894b75b7bd65f76f2efeef2 100644 (file)
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -9022,8 +9022,11 @@ Display all registers in @emph{group}.
 @section RISC-V Architecture
 
 @uref{http://riscv.org/, RISC-V} is a free and open ISA. OpenOCD supports JTAG
-debug of targets that implement version 0.11 and 0.13 of the RISC-V Debug
-Specification.
+debug of RV32 and RV64 cores in heterogeneous multicore systems of up to 32
+harts. (It's possible to increase this limit to 1024 by changing
+RISCV_MAX_HARTS in riscv.h.) OpenOCD primarily supports 0.13 of the RISC-V
+Debug Specification, but there is also support for legacy targets that
+implement version 0.11.
 
 @subsection RISC-V Terminology